1995_IDT_Specialized_Memories_FIFOs_and_Modules_Data_Book 1995 IDT Specialized Memories FIFOs And Modules Data Book
User Manual: 1995_IDT_Specialized_Memories_FIFOs_and_Modules_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 1276
| Download | |
| Open PDF In Browser | View PDF |
Integrated Device Technology, Inc.
1995
SPECIALIZED MEMORIES
&MODULES
DATA BOOK
2975 Stender Way, Santa Clara, California 95054
Telephone: (408) 727-6116 • TWX: 910-338-2070 • FAX: (408) 492-8674
Printed in U.S.A.
©1995 Integrated Device Technology, Inc.
GENERAL INFORMATION
II
CONTENTS OVERVIEW
For ease of use for our customers, Integrated Device Technology provides four separate data books
- Logic, Specialized Memories and Modules, RISC and RISC SubSystems, and Static RAM.
lOT's 1995 Specialized Memories and Modules Data Book is comprised of new and revised data sheets
for the FIFO, Specialty Memory and Subsystem product groups. Also included is a current packaging
section for the products included in this book. This section will be updated in each subsequent data book
to reflect packages offered for products included in that book.
The 1995 Specialized Memories and Modules Data Book's Table of Contents contains a listing of the
products contained in that data book only. In the past we have included products that appeared in other
lOT data books. The numbering scheme for the book is consistent with the 1990-91 data books. The
number in the bottom center of the page denotes the section number and the sequence of the data sheet
within that section, (Le. 5.5 would be the fifth data sheet in the fifth section). The number in the lower right
hand corner is the page number of that particular data sheet.
Integrated Device Technology, a recognized leader in high-speed CMOS technology, produces a broad
line of products. This enables us to provide a complete CMOS solution to designers of high-performance
digital systems. Not only do our product lines include industry standard devices, they also feature products
with 3.3V technology, faster speed, lower power, and package and/or architectural benefits that allow the
designer to achieve significantly improved system performance.
To find ordering information: Ordering Information for all products in this book appears in Section
1, along with the Package Outline Index, Product Selector Guides, and Cross Reference Guides.
Reference data on our Technology Capabilities and Quality Commitments is included in separate sections
(2 and 3, respectively).
To find product data: Start with the Table of Contents, organized by product line (page 1.2), or with
the Numeric Table of Contents (page 1.4). These indexes will direct you to the page on which the complete
technical data sheet can be found. Data sheets may be of the following type:
ADVANCE INFORMATION - contain initial descriptions, subject to change, for products that are in
development, including features and block diagrams.
PRELIMINARY - contain descriptions for products soon to be, or recently, released to production,
including features, pinouts and block diagrams. Timing data are based on simulation or it:litial characterization and are subject to change upon full characterization.
FINAL - contain minimum and maximum limits specified over the complete supply and temperature
range for full production devices.
New products, product performance enhancements, additional package types and new product
families are being introduced frequently. Please contact your local lOT sales representative to determine
the latest device specifications, package types and product availability.
1.1
II
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components In life support devices or systems
unless a specific written agreement pertaining to such Intended use is executed between the manufacturer and an officer of lOT.
1. Life support devices or systems are devices or systems which (a) are Intended for surgical implant into the body or (b) support
or sustain life and whose failure to perform, when properly used In accordance with Instructions for use provided In the
labeling, can be reasonably expected to result In a significant Injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect Its safety or effectiveness.
Note: Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve
design or performance and to supply the best possible product. lOT does not assume any responsibility for use of any circuitry described other than the circuitry
embodied in an lOT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device
TeChnology, Inc.
The lOT logo is a registered trademark and BiCameral, BurstRAM, BUSMUX, CacheRAM, DECnet, Double-Density, FASTX, Four-Port, FLEXI-CACHE,
Flexi-PAK, Flow-thruEDC, IDT/c, IDTenvY, IDT/sae, IDT/sim, IDT/ux, MacStation, MICROSLlCE, NICStAR, Orion, PalatteDAC, REAL8, R3041 , R3051 ,
R3052, R3081 , R3721 , R4600, RISCompiler, RISController, RISCard, RISCore, RISC Subsystem, RISC Windows, SARAM, SmartLogic, SolutionPak,
SyncFIFO, SyncBiFIFO, SPC, and TargetSystem are trademarks of Integrated Device Technology, Inc.
MIPS is a registered trademark of MIPS Computer Systems, Inc
All others are trademarks of their respective companies.
1.1
2
1995 SPECIALIZED MEMORIES & MODULES DATA BOOK
TABLE OF CONTENTS
PAGE
GENERAL INFORMATION
Contents Overview. ........................................... ...... ....... .... ...... .................. ... .......... .............. ................................
Table of Contents ............................................................................................... .... ...................... ........................
Numeric Table of Contents ... ...................................................................................................... ............. .............
Ordering Information ............................................................. .................................................. ................. .............
IDT Package Marking Description ........................................................................................................................
FIFO Product Selector Guide ...............................................................................................................................
Specialty Memory Product Selector Guide ...........................................................................................................
Subsystems Product Selector Guide .................................................................................... ........... ... ..................
FIFO Cross Reference Guide ...............................................................................................................................
Specialty Memory Cross Reference Guide ... .................... ............................................................................ ........
Subsystems Cross Reference Guide .................................................................... ................ ................................
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
TECHNOLOGY AND CAPABILITIES
IDT... Leading the CMOS Future ...........................................................................................................................
IDT Military and DESC-SMD Program ................................................................................................................:.
Radiation Hardened Technology ..................................................................................................... .... .................
IDT Leading Edge CMOS Technology .................................................................................................................
State-of-the-Art Facilities and Capabilities ......................................................... ...................... ........ ........... ..........
Superior Quality and Reliability..... ............. ......... ....... ... ..................... ...... .... ........... ..... .... ..... ...................... ..........
2.1
2.2
2.3
2.4
2.5
2.6
QUALITY AND RELIABILITY
Quality, Service and Performance ........................................................................................ ... ........... ..................
IDT Quality Conformance Program ......................................................................................................................
Radiation Tolerant/Enhanced/Hardened Products for Radiation Environments ...................................................
3.1
3.2
3.3
PACKAGE DIAGRAM OUTLINES
Thermal Performance Calculations for I DT's Packages .......................................................... .............................
Package Diagram Outline Index ......................................................................................... ................. .................
Monolithic Package Diagram Outlines .... ................. .... ..... ..... ... ... .................... ...... .... ..................................... ......
4.1
4.2
4.3
FIFO PRODUCTS
IDT77201
IDT72261
IDT72271
IDT72255
IDT72265
IDT72423
IDT72203
IDT72213
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
IDT72421
IDT72201
IDT72211
IDT72221
155bps ATM SAR Controller for PCI-Based Networking Applications ......................
CMOS SuperSync™ FIFO 16,384 x 9-bit.................................................................
CMOS SuperSync FIFO 32,768 x 9-bit ....................................................................
CMOS SuperSync FIFO 8,192 x 18-bit ....................................................................
CMOS SuperSync FIFO 16,384 x 18-bit ..................................................................
CMOS Single Bit SyncFIFOTM 64 x 1-bit ..................................................................
CMOS Single Bit SyncFIFO 256 x 1-bit....................................................................
CMOS Single Bit SyncFIFO 512 x 1-bit....................................................................
CMOS SyncFIFO 64 x 8-bit ......................................................................................
CMOS SyncFIFO 256 x 8-bit ....................................................................................
CMOS SyncFIFO 512 x 8-bit ....................................................................................
CMOS SyncFIFO 1,024 x 8-bit .................................................................................
CMOS SyncFIFO 2,048 x 8-bit .................................................................................
CMOS SyncFIFO 4,096 x 8-bit .................................................................................
CMOS SyncFIFO 64 x 9-bit ......................................................................................
CMOS SyncFIFO 256 x 9-bit ....................................................................................
CMOS SyncFIFO 512 x 9-bit....................................................................................
CMOS SyncFIFO 1,024 x 9-bit .................................................................................
1.2
5.1
5.2
5.2
5.3
5.3
5.4
5.4
5.4
5.5
5.5
5.5
5.5
5.5
5.5
5.6
5.6
5.6
5.6
II
1995 SPECIALIZED MEMORIES & MODULES DATA BOOK (CONTINUED) ..................... PAGE
FIFO PRODUCTS (CONTINUED)
CMOS SyncFIFO 2,048 x 9-bit .................................................................................
IDT72231
CMOS SyncFIFO 4,096 x 9-bit .................................................................................
IDT72241
Dual CMOS SyncFIFO 256 x 9 x 2 ...........................................................................
IDT72801
Dual CMOS SyncFIFO 512 x 9 x 2 .......................................................................... .
IDT72811
Dual CMOS SyncFIFO 1,024 x 9 x 2 ...................................................................... ..
IDT72821
Dual CMOS SyncFIFO 2,048 x 9 x 2 ........................................................................
IDT72831
Dual CMOS SyncFIFO 4,096 x 9 x 2 ...................................................................... ..
IDT72841
CMOS SyncFIFO 256 x 18-bit ...................................................................................
IDT72205
CMOS SyncFIFO 512 x 18-bit ...................................................................................
IDT72215
CMOS SyncFIFO 1,024 x 18-bit ................................................................................
IDT72225
IDT72235
CMOS SyncFIFO 2,048 x 18-bit """"""""""""""""""""""""""""""""""""""""
CMOS SyncFIFO 4,096 x 18-bit .............................................................................. ..
IDT72245
CMOS Dual SyncFIFO 256 x 18 x 2 ........................................................................ ..
IDT72805
CMOS Dual SyncFIFO 512 x 18 x 2 ........................................................................ ..
IDT72815
CMOS Dual SyncFIFO 1,024 x 18 x 2 ...................................................................... .
IDT72825
BiCMOS SyncFIFO 64 x 36-bit .................................................................................
IDT723611
CMOS SyncFIFO with Bus Matching and Byte Swapping 64 x 36-bit.. .................. ..
IDT723613
CMOS SyncFIFO 512 x 36-bit ................................................................................ ..
IDT723631
CMOS SyncFIFO 1,024 x 36-bit ............................................................................. ..
IDT723641
CMOS SyncFIFO 2,048 x 36-bit ............................................................................. ..
IDT723651
CMOS SyncBiFIFOTM 256 x 18 x 2 ........................................................................ ..
IDT72605
CMOS SyncBiFIFO™512 x 18 x 2 ......................................................................... .
IDT72615
BiCMOS SyncFIFO 64 x 36 x 2 .............................................................................. ..
IDT723612
CMOS SyncBiFIFO with Bus Matching and Byte Swapping 64 x 36 x 2 ................. .
IDT723614
CMOS SyncBiFIFO 256 x 36 x 2 ..............................................................................
IDT723622
CMOS SyncBiFIFO 512 x 36 x 2 ............................................................................ ..
IDT723632
CMOS SyncBiFIFO 1024 x 36 x 2 .......................................................................... ..
IDT723642
CMOS Parallel FIFO 64 x 4-bit ............................................................................... ..
IDT72401
CMOS Parallel FIFO 64 x 5-bit ............................................................................... ..
IDT72402
CMOS Parallel FIFO 64 x 4-bit ................................................................................ .
IDT72403
CMOS Parallel FIFO 64 x 5-bit ............................................................................... ..
IDT72404
CMOS Parallel FIFO with Flags 64 x 5-bit.. ............................................................ ..
IDT72413
CMOS Asynchronous FIFO 256 x 9-bit .................................................................. ..
IDT7200
CMOS Asynchronous FIFO 512 x 9-bit ....................................................................
IDT7201
CMOS Asynchronous FIFO 1,024 x 9-bit ............................................................... ..
IDT7202
CMOS Asynchronous FIFO 2,048 x 9-bit ................................................................ .
IDT7203
CMOS Asynchronous FIFO 4,096 x 9-bit ................................................................ .
IDT7204
CMOS Asynchronous FIFO 8,192 x 9-bit ................................................................ .
IDT7205
CMOS Asynchronous FIFO 16,384 x 9-bit .............................................................. .
IDT7206
CMOS Asynchronous FIFO 32,768 x 9-bit .............................................................. .
IDT7207
3.3V CMOS Asynchronous FIFO 512 x 9-bit ............................................................
IDT72V01
3.3V CMOS Asynchronous FIFO 1,024 x 9-bit.. ...................................................... .
IDT72V02
3.3V CMOS Asynchronous FIFO 2,048 x 9-bit.. ...................................................... .
IDT72V03
3.3V CMOS Asynchronous FIFO 4,096 x 9-bit.. ...................................................... .
IDT72V04
Bus-Matching BiDirectional FIFO 512 x 18-bit-1,024 x 9-bit ................................ ..
IDT72510
Bus-Matching BiDirectional FIFO 1,024 x 18-bit-2,048 x 9-bit .............................. .
IDT72520
Parallel BiDirectional FIFO 512 x 18-bit .................................................................. .
IDT72511
Parallel BiDirectional FIFO 1024 x 18-bit ................................................................ .
IDT72521
CMOS Asynchronous FIFO with Retransmit 1,024 x 9-bit ...................................... .
IDT72021
CMOS Asynchronous FIFO with Retransmit 2,048 x 9-bit ..................................... ..
IDT72031
CMOS Asynchronous FIFO with Retransmit 4,096 x 9-bit ...................................... .
IDT72041
CMOS Parallel-to-Serial FIFO 2,048 x 9-bit ........................................................... ..
IDT72103
CMOS Parallel-to-Serial FIFO 4,096 x 9-bit ............................................................ .
IDT72104
CMOS Parallel-to-Serial FIFO 256 x 16-bit ............................................................. .
IDT72105
1.2
5.6
5.6
5.7
5.7
5.7
5.7
5.7
5.8
5.8
5.8
5.8
5.8
5.09
5.09
5.09
5.10
5.11
5.12
5.12
5.12
5.13
5.13
5.14
5.15
5.16
5.16
5.16
5.17
5.17
5.17
5.17
5.18
5.19
5.19
5.19
5.20
5.20
5.20
5.20
5.21
5.22
5.22
5.22
5.22
5.23
5.23
5.24
5.24
5.25
5.25
5.25
5.26
5.26
5.27
2
1995 SPECIALIZED MEMORIES & MODULES DATA BOOK (CONTINUED) ....................... PAGE
I DT7115
IDT7125
IDT72131
IDT72141
IDT72132
IDT72142
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Parallel-to-Serial
Parallel-to-Serial
Parallel-to-Serial
Parallel-to-Serial
Serial-to-Parallel
Serial-to-Parallel
FI FO
FIFO
FIFO
FIFO
FIFO
FIFO
512 x 16-bit ........ ......... ........ ......... ...... .... ... ...............
1,024 x 16-bit ...........................................................
2,048 x 9-bit .............................................................
4,096 x 9-bit .............................................................
2,048 x 9-bit .............................................................
4,096 x 9-bit .............................................................
II
5.27
5.27
5.28
5.28
5.29
5.29
FIFO MODULES
Please refer to Subsystems Products listing for FIFO Modules.
SPECIALTY MEMORY PRODUCTS
IDT7130SAlLA
I DT7140SAlLA
IDT7132SAlLA
I DT7142SAlLA
IDT71321SAlLA
IDT71421SAlLA
IDT7134SAlLA
I DT71342SAlLA
IDT7005S/L
IDT7006S/L
IDT7007S/L
IDT7008S/L
IDT70121S/L
IDT70125S/L
IDT7014S
IDT7015S/L
IDT7016S/L
IDT7133SAlLA
IDT7143SAlLA
IDT7024S/L
IDT7025S/L
IDT7026S/L
IDT70261 S/L
IDT7027S/L
IDT7099S
I DT70908S/L
I DT70927S/L
IDT7052S/L
IDT70824S/L
I DT70825S/L
IDT71V321 S/L
IDT70V05S/L
IDT70V06S/L
IDT70V07S/L
I DT70V24S/L
I DT70V25S/L
IDT70V26S/L
IDT70V261 S/L
8K (1 K x 8) Dual-Port RAM (Master) ................................................................. ........
8K (1 K x 8) Dual-Port RAM (Slave) ...........................................................................
16K (2K x 8) Dual-Port RAM (Master) .......................................................................
16K (2K x 8) Dual-Port RAM (Slave) .........................................................................
16K (2K x 8) Dual-Port RAM (Master with Interrupts) ...............................................
16K (2K x 8) Dual-Port RAM (Slave with Interrupts) .................................................
32K (4K x 8) Dual-Port RAM .....................................................................................
32K (4K x 8) Dual-Port RAM (with Semaphore) ........................................................
64K (8K x 8) Dual-Port RAM ................................................................ .....................
128K (16K x 8) Dual-Port RAM .................................................................................
256K (32K x 8) Dual-Port RAM ........ ...... ... ... ..... ............. ...... ...... .......... .....................
512K (64K x 8) Dual-Port RAM .................................................................................
18K (2K x 9) Dual-Port RAM (Master with Busy and Interrupt) .................................
18K (2K x 9) Dual-Port RAM (Slave with Busy and Interrupt) .............. .....................
36K (4K x 9-Bit) Dual-Port RAM ................................................................................
72K (8K x 9-Bit) Dual-Port RAM .................................................................... ............
144K (16K x 9-Bit) Dual-Port RAM ............................................................................
32K (2K x 16-Bit) Dual-Port RAM (Master) .... ........... ...... ...... ...... ......................... ... ...
32K (2K x 16-Bit) Dual-Port RAM (Slave)........ ....... ............ ..... .................... ..... ... ......
64K (4K x 16-Bit) Dual-Port RAM......... ..... ........... ......... ................. ...... ................. ....
128K (8K x 16-Bit) Dual-Port RAM ....... ...... ..... ..... ............ ....... ... .......... .....................
256K (16K x 16-Bit) Dual-Port RAM ..........................................................................
256K (16K x 16-Bit) High-Speed Dual-Port RAM ......................................................
512K (32K x 16-Bit) High-Speed Dual-Port RAM ......................................................
36K (4K x 9) Synchronous Dual-Port RAM ...............................................................
512K (64K x 8-Bit) Synchronous Dual-Port RAM ......................................................
512K (32K x 16) Synchronous Dual-Port RAM .........................................................
16K (2K x 8) FourPort™ Static RAM... ..... ... ... ...... ....... .......... ........ ............. ....... ........
64K (4K x 16-Bit) Sequential-Access/Random Access Memory (SARAMTM) ...........
128K (8K x 16-Bit) Sequential-Access/Random Access Memory (SARAMTM) .........
16K (2K x 8-Bit) 3.3V CMOS Dual-Port RAM with Interrupts ....................................
64K (8K x 8-Bit) 3.3V Dual-Port RAM ........................................................................
128K (16K x 8-Bit) 3.3V Dual-Port RAM ....................................................................
256K (32K x 8-Bit) 3.3V Dual-Port RAM.. ...... ............ ........ ... .... ... .... ..... ....... ....... .......
64K (4K x 16-Bit) 3.3V Dual-Port RAM ......................................................................
128K (8K x 16-Bit) 3.3V Dual-Port RAM ....................................................................
256K (16K x 16-Bit) 3.3V Dual-Port RAM ..................................................................
256K (16K x 16-Bit) 3.3V Dual-Port RAM ..................................................................
6.1
6.1
6.2
6.2
6.3
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.10
6.11
6.12
6.13
6.14
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
6.29
6.30
6.31
6.32
6.33
MULTI-PORT MODULES
Please refer to Subsystems Products listing for Multi-Port Modules
1.2
3
1995 SPECIALIZED MEMORIES & MODULES DATA BOOK (CONTINUED) ....................... PAGE
SUBSYSTEMS PRODUCTS
IDT7MP1015
IDT7MP1016
IDT7M1002
IDT7M1014
IDT7M1024
IDT7M1001
IDT7M1003
IDT7M208
IDT7M209
IDT7MP4120
IDT7MP4145
IDT7MP4045
IDT7MP4095
IDT7M4084
IDT7MB4048
IDT7M4048
IDT7MP2009
IDT7MP2010
IDT7M208
IDT7M207
32K x 32 CMOS Dual-Port Static Ram Module .........................................................
64K x 32 CMOS Dual-Port Static RAM Module.. ........ ...... ...... ............................ .......
16K x 32 CMOS Dual-Port Static RAM Module.........................................................
4K x 36 BiCMOS Dual-Port Static RAM Module .......................................................
4K x 36 BiCMOS Synchronous Dual-Port Static RAM Module .................................
128K x 8 CMOS Dual-Port Static RAM Module.........................................................
64K x 8 CMOS Dual-Port Static RAM Module ...........................................................
64K x 9 CMOS Parallel In-Out FIFO Module .............................................................
128K x 9 CMOS Parallel In-Out FIFO Module ...........................................................
1M x 32 CMOS Static RAM Module ..........................................................................
256K x 32 CMOS Static RAM Module...................... .................................................
256K x 32 BiCMOS/CMOS Static RAM Module.. ........ ...... ...... ...... ........ ...... ........ ......
128K x 32 CMOS Static RAM Module .......................................................................
2M x 8 CMOS Static RAM Module ............................................................................
512K x 8 CMOS Static RAM Module .........................................................................
512K x 8 CMOS Static RAM Module .........................................................................
32Kx 18 CMOS Parallel In-Out FIFO Module...........................................................
16Kx 18 CMOS Parallel In-Out FIFO Module...........................................................
64K x 9 Parallel In-Out FIFO Module.. ........ ...... ...... ........ ...... ............................ ........
32K x 9 Parallel In-Out FIFO Module ........................................................................
7.1
7.1
7.2
7.3
7.4
7.5
7.5
7.6
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.12
7.12
7.13
7.13
IDT SALES OFFICE, REPRESENTATIVE AND DISTRIBUTOR LOCATIONS
1.2
4
NUMERICAL TABLE OF CONTENTS
PART NO.
IDT7005S/L
IDT7006S/L
IDT7007S/L
IDT7008S/L
IDT70121S/L
IDT70125S/L
IDT7014S
IDT7015S/L
IDT7016S/L
IDT7024S/L
IDT7025S/L
IDT7026S/L
IDT70261 S/L
IDT7027S/L
IDT7052S/L
IDT70824S/L
IDT70825S/L
IDT70908S/L
IDT70927S/L
IDT7099S
IDT70V05S/L
IDT70V06S/L
I DT70V07S/L
IDT70V24S/L
I DT70V25S/L
IDT70V26S/L
IDT70V261 S/L
IDT7115
IDT7125
I DT7130SAlLA
I DT7132SAlLA
IDT71321 SAiLA
IDT7133SAlLA
I DT7134SAlLA
IDT71342SAlLA
I DT7140SAlLA
I DT7142SAlLA
I DT71421 SAiLA
IDT7143SAlLA
IDT71V321S/L
IDT7200
IDT7201
IDT7202
IDT72021
IDT7203
IDT72031
IDT7204
IDT72041
IDT7205
IDT7206
IDT7207
IDT72103
IDT72104
IDT72105
PAGE
64K (8K x 8) Dual-Port RAM ...............................................................................................
128K (16K x 8) Dual-Port RAM ...........................................................................................
256K (32K x 8) Dual-Port RAM ..... ..... ........ ......... ....... ........ ..... ....... ....... ...... .... ...... .... ... .......
512K (64K x 8) Dual-Port RAM ...........................................................................................
18K (2K x 9) Dual-Port RAM (Master with Busy and Interrupt) ........... ...... .......... .... ... .........
18K (2K x 9) Dual-Port RAM (Slave with Busy and Interrupt) .............................................
36K (4K x 9-Bit) Dual-Port RAM ..........................................................................................
72K (8K x 9-Bit) Dual-Port RAM .......... ........ .......... ...... .... ................ ....... ....... ........... ...........
144K (16K x 9-Bit) Dual-Port RAM ......................................................................................
64K (4K x 16-Bit) Dual-Port RAM ..................................................................................... ...
128K (8K x 16-Bit) Dual-Port RAM ....... .......... ....... ............. ....... ................ ................... .......
256K (16K x 16-Bit) Dual-Port RAM ....................................................................................
256K (16K x 16-Bit) High-Speed Dual-Port RAM ................................................................
512K (32K x 16-Bit) High-Speed Dual-Port RAM ................................................................
16K (2K x 8) FourPort™ Static RAM .... ......... ..... ... ...... .... ... ............. ....... ....... ... ...................
64K (4K x 16-Bit) Sequential-Access/Random Access Memory (SARAMTM) .....................
128K (8K x 16-Bit) Sequential-Access/Random Access Memory (SARAMTM) ... ................
512K (64K x 8-Bit) Synchronous Dual-Port RAM ................................................................
512K (32K x 16) Synchronous Dual-Port RAM ...................................................................
36K (4K x 9) Synchronous Dual-Port RAM .........................................................................
64K (8K x 8-Bit) 3.3V Dual-Port RAM .... ....... ... ....... ...... ...... ....... .............. ........ ... ....... .........
128K (16K x 8-Bit) 3.3V Dual-Port RAM .............................................................................
256K (32K x 8-Bit) 3.3V Dual-Port RAM .... ... ........ ..... ........ ...... .... ... ...... ........ ............ .... ......
64K (4K x 16-Bit) 3.3V Dual-Port RAM ...............................................................................
128K (8K x 16-Bit) 3.3V Dual-Port RAM .... ... ........ ............ ....... ..................... ... ......... .... ......
256K (16K x 16-Bit) 3.3V Dual-Port RAM ......................... ..................................................
256K (16K x 16-Bit) 3.3V Dual-Port RAM ...........................................................................
CMOS Parallel-to-Serial FI FO 512 x 16-bit ...................................... '" ......... ... .... .... ... ........
CMOS Parallel-to-Serial FIFO 1,024 x 16-bit.....................................................................
8K (1 K x 8) Dual-Port RAM (Master) ...................................................................................
16K (2K x 8) Dual-Port RAM (Master) ............................... ............................... ...................
16K (2K x 8) Dual-Port RAM (Master with Interrupts) ...................................... ...................
32K (2K x 16-Bit) Dual-Port RAM (Master) ...................................... '" ...... ....... ... .... ... .........
32K (4K x 8) Dual-Port RAM ...............................................................................................
32K (4K x 8) Dual-Port RAM (with Semaphore) ..................................................................
8K (1 K x 8) Dual-Port RAM (Slave) .....................................................................................
16K (2K x 8) Dual-Port RAM (Slave) ...................................................................................
16K (2K x 8) Dual-Port RAM (Slave with Interrupts) ...........................................................
32K (2K x 16-Bit) Dual-Port RAM (Slave) ...........................................................................
16K (2K x 8-Bit) 3.3V CMOS Dual-Port RAM with Interrupts ..............................................
CMOS Asynchronous FIFO 256 x 9-bit ..............................................................................
CMOS Asynchronous FIFO 512 x 9-bit..............................................................................
CMOS Asynchronous FIFO 1,024 x 9-bit ...........................................................................
CMOS Asynchronous FIFO with Retransmit 1,024 x 9-bit .................................................
CMOS Asynchronous FIFO 2,048 x 9-bit ...........................................................................
CMOS Asynchronous FIFO with Retransmit 2,048 x 9-bit .................................................
CMOS Asynchronous FIFO 4,096 x 9-bit ...........................................................................
CMOS Asynchronous FIFO with Retransmit 4,096 x 9-bit .................................................
CMOS Asynchronous FIFO 8,192 x 9-bit...........................................................................
CMOS Asynchronous FIFO 16,384 x 9-bit .........................................................................
CMOS Asynchronous FIFO 32,768 x 9-bit.........................................................................
CMOS Parallel-to-Serial FIFO 2,048 x 9-bit ................................................... ....................
CMOS Parallel-to-Serial FIFO 4,096 x 9-bit .......................................................................
CMOS Parallel-to-Serial FI FO 256 x 16-bit........ ...... .... ... ....... ............. ....... ....... ....... ..........
1.3
6.6
6.7
6.8
6.9
6.10
6.10
6.11
6.12
6.13
6.15
6.16
6.17
6.18
6.19
6.23
6.24
6.25
6.21
6.22
6.20
6.27
6.28
6.29
6.30
6.31
6.32
6.33
5.27
5.27
6.1
6.2
6.3
6.14
6.4
6.5
6.1
6.2
6.3
6.14
6.26
5.19
5.19
5.19
5.25
5.20
5.25
5.20
5.25
5.20
5.20
5.21
5.26
5.26
5.27
II
NUMERICAL TABLE OF CONTENTS (CONTINUED)
PART NO.
IOT72131
IOT72141
IOT72132
IOT72142
IOT72200
IOT72201
IOT72203
IOT72205
IOT72210
IOT72211
IOT72213
IOT72215
IOT72220
IOT72221
IOT72225
IOT72230
IOT72231
IOT72235
IOT72240
IOT72241
IOT72245
IOT72255
IOT72261
IOT72265
IOT72271
IOT723611
IOT723612
IOT723613
IOT723614
IOT723622
IOT723631
IOT723632
IOT723641
IOT723642
IOT723651
IOT72401
IOT72402
IOT72403
IOT72404
IOT72413
IOT72420
IOT72421
IOT72423
IOT72510
IOT72511
IOT72520
IOT72521
IOT72605
IOT72615
IOT72801
IOT72805
IOT72811
IOT72815
IOT72821
IOT72825
PAGE
CMOS Parallel-to-Serial FIFO 2,048 x 9-bit ...................................................................... .
CMOS Parallel-to-Serial FIFO 4,096 x 9-bit ...................................................................... .
CMOS Serial-to-Parallel FIFO 2,048 x 9-bit ...................................................................... .
CMOS Serial-to-Parallel FIFO 4,096 x 9-bit ...................................................................... .
CMOS SyncFIFO 256 x 8-bit ..............................................................................................
CMOS SyncFIFO 256 x 9-bit ..............................................................................................
CMOS Single Bit SyncFIFO 256 x 1-bit .............................................................................
CMOS SyncFIFO 256 x 18-bit .............................................................................................
CMOS SyncFIFO 512 x 8-bit ..............................................................................................
CMOS SyncFIFO 512 x 9-bit ..............................................................................................
CMOS Single Bit SyncFIFO 512 x 1-bit .............................................................................
CMOS SyncFIFO 512 x 18-bit .............................................................................................
CMOS SyncFIFO 1,024 x 8-bit ...........................................................................................
CMOS SyncFIFO 1,024 x 9-bit ...........................................................................................
CMOS SyncFIFO 1,024 x 18-bit ..........................................................................................
CMOS SyncFIFO 2,048 x 8-bit ...........................................................................................
CMOS SyncFIFO 2,048 x 9-bit ...........................................................................................
CMOS SyncFIFO 2,048 x 18-bit ..........................................................................................
CMOS SyncFIFO 4,096 x 8-bit ...........................................................................................
CMOS SyncFIFO 4,096 x 9-bit ...........................................................................................
CMOS SyncFIFO 4,096 x 18-bit ..........................................................................................
CMOS SuperSync FIFO 8,192 x 18-bit ............................................................................. .
CMOS SuperSync™ FIFO 16,384 x 9-bit ..........................................................................
CMOS SuperSync FIFO 16,384 x 18-bit ........................................................................... .
CMOS SuperSync FIFO 32,768 x 9-bit ............................................................................. .
BiCMOS SyncFIFO 64 x 36-bit ..........................................................................................
BiCMOS SyncFIFO 64 x 36 x 2 ..........................................................................................
CMOS SyncFIFO with Bus Matching and Byte Swapping 64 x 36-bit .............................. .
CMOS SyncBiFIFO with Bus Matching and Byte Swapping 64 x 36 x 2 .......................... .
CMOS SyncBiFIFO 256 x 36 x 2 ........................................................................................
CMOS SyncFIFO 512 x 36-bit .......................................................................................... ..
CMOS SyncBiFIFO 512 x 36 x 2 ........................................................................................
CMOS SyncFIFO 1,024 x 36-bit ........................................................................................ .
CMOS SyncBiFIFO 1024 x 36 x 2 ..................................................................................... .
CMOS SyncFIFO 2,048 x 36-bit .........................................................................................
CMOS Parallel FIFO 64 x 4-bit ...........................................................................................
CMOS Parallel FIFO 64 x 5-bit ...........................................................................................
CMOS Parallel FIFO 64 x 4-bit ......................................................................................... ..
CMOS Parallel FIFO 64 x 5-bit ...........................................................................................
CMOS Parallel FIFO with Flags 64 x 5-bit ............................................ ,.......................... ..
CMOS SyncFIFO 64 x' 8-bit ................................................................................................
CMOS SyncFIFO 64 x 9-bit ................................................................................................
CMOS Single Bit SyncFIFOTM 64 x 1-bit .......................................................................... ..
Bus-Matching BiOirectional FIFO 512 x 18-bit-1,024 x 9-bit .......................................... ..
Parallel BiDirectional FIFO 512 x 18-bit .............................................................................
Bus-Matching BiOirectional FIFO 1,024 x 18-bit-2,048 x 9-bit ....................................... ..
Parallel BiOirectional FIFO 1024 x 18-bit .......................................................................... .
CMOS SyncBiFIFOTM 256 x 18 x 2 .................................................................................. ..
CMOS SyncBiFIFOTM 512 x 18 x 2 ....................................................................................
Oual CMOS SyncFIFO 256 x 9 x 2 .................................................................................. ..
CMOS Dual SyncFIFO 256 x 18 x 2 ...................................................................................
Oual CMOS SyncFIFO 512 x 9 x 2 .................................................................................. ..
CMOS Oual SyncFIFO 512 x 18 x 2 ...................................................................................
Dual CMOS SyncFIFO 1,024 x 9 x 2 .................................................................................
CMOS Oual SyncFIFO 1,024 x 18 x 2 .............................................................................. ..
1.3
5.28
5.28
5.29
5.29
5.5
5.6
5.4
5.8
5.5
5.6
5.4
5.8
5.5
5.6
5.8
5.5
5.6
5.8
5.5
5.6
5.8
5.3
5.2
5.3
5.2
5.10
5.14
5.11
5.15
5.16
5.12
5.16
5.12
5.16
5.12
5.17
5.17
5.17
5.17
5.18
5.5
5.6
5.4
5.23
5.24
5.23
5.24
5.13
5.13
5.7
5.09
5.7
5.09
5.7
5.09
2
NUMERICAL TABLE OF CONTENTS (CONTINUED)
PAGE
PART NO.
IDT72831
IDT72841
IDT72V01
IDT72V02
IDT72V03
IDT72V04
IDT77201
IDT7M1001
IDT7M1002
IDT7M1003
IDT7M1014
IDT7M1024
IDT7M208
IDT7M209
IDT7M4048
IDT7M4084
IDT7MS4048
IDT7MP1015
IDT7MP1016
IDT7MP4045
IDT7MP4095
IDT7MP4120
IDT7MP4145
Dual CMOS SyncFIFO 2,048 x 9 x 2 .................................................................................
Dual CMOS SyncFIFO 4,096 x 9 x 2 .................................................................................
3.3V CMOS Asynchronous FIFO 512 x 9-bit .................................................................... .
3.3V CMOS Asynchronous FIFO 1,024 x 9-bit ..................................................................
3.3V CMOS Asynchronous FIFO 2,048 x 9-bit ................................................................. .
3.3V CMOS Asynchronous FIFO 4,096 x 9-bit ................................................................. .
155bps ATM SAR Controller for PCI-Sased Networking Applications ............................... .
128K x 8 CMOS Dual-Port Static RAM Module ..................................................................
16K x 32 CMOS Dual-Port Static RAM Module ................................................................. .
64K x 8 CMOS Dual-Port Static RAM Module ................................................ '" ................ .
4K x 36 SiCMOS Dual-Port Static RAM Module .................................................................
4K x 36 SiCMOS Synchronous Dual-Port Static RAM Module .......................................... .
64K x 9 CMOS Parallel In-Out FIFO Module ......................................................................
128K x 9 CMOS Parallel In-Out FIFO Module ................................................................... .
512K x 8 CMOS Static RAM Module .................................................................................. .
2M x 8 CMOS Static RAM Module ......................................................................................
512K x 8 CMOS Static RAM Module ...................................................................................
32K x 32 CMOS Dual-Port Static Ram Module .................................................................. .
64K x 32 CMOS Dual-Port Static RAM Module ................................................................. .
256K x 32 SiCMOS/CMOS Static RAM Module ................................................................. .
128K x 32 CMOS Static RAM Module .................................................................................
1M x 32 CMOS Static RAM Module ....................................................................... '" ......... .
256K x 32 CMOS Static RAM Module ................................................................................ .
1.3
5.7
5.7
5.22
5.22
5.22
5.22
5.1
7.5
7.2
7.5
7.3
7.4
7.6
7.6
7.13
7.11
7.12
7.1
7.1
7.9
7.10
7.7
7.8
3
ORDERING INFORMATION
When ordering by TWX or Telex, the following format must be used:
A. Complete Bill To.
B. Complete Ship To.
C. Purchase Order Number.
O. Certificate of Conformance. Y or N.
E. Customer Source Inspection. Y or N.
F. Government Source Inspection. Y or N
G. Government Contract Number and Rating.
H. Requested Routing.
I. lOT Part NumberEach item ordered must use the complete part number exactly as listed in the price book.
J. SCD Number - SpeCification Control Document (Internal Traveller).
K. Customer Part Number/Drawing Number/Revision level Specify whether part number is for reference only, mark only, or if extended processing to customer specification is
required.
l. Customer General Specification Numbers/Other Referenced Drawing Numbers/Revision levels.
M. Request Date With Exact Quantity.
N. Unit Price.
O. Special Instructions, Including Q.A. Clauses, Special Processing.
Federal Supply Code Number/Cage Number Dun & Bradstreet Number - 03-814-2600
Federal Tax I.D. - 94-2669985
TLX# - 887766
FAX# - 408-727-3468
61772
PART NUMBER DESCRIPTION
A
IDT
XXXXX
A
DEVICE TYPE
X
999
=Alpha Character
AA
N
=Numeric Character
AA
AA
TEMP.
SPECIAL
PROCESS
POWER "'iiEViSiON SP'EEii' 'PAcKAG'E PiiOcESSi
~
RE
YRT
L----------4:
BLANK
M*
B
Radiation Enhanced
Radiation Tolerant
Commercial- O°C to +70°C
Commercial - -55°C to + 125°C
Military - -55°C to + 125°C (Fully compliant
to MIL-STD-883, Method 5004, Class B)
See Package Description Table
L...------------f SPEED
L--------------i A
L...------------------f
L-__________________
Guaranteed Minimum Performance
Measured in Nanoseconds or MHz
BLANK
POWER S/SA - Standard Power
ULA - Low Power
- - I DEVICE e.g. 6116
TYPE
PACKAGE DESCRIPTION TABLE
C
D
F
J
L
P
Y
Ceramic Sidebraze
PF Plastic Quad Flatpack
Cerdip
PZ TSOP Type 1
Flatpack
SO Plastic Small Outline IC
Plastic Leaded Chip Carrier TC Sidebraze Thindip (300-MIL)
Leadless Chip Carrier
TP Plastic Thin Dual In-Line
Plastic DIP
TY Thin SOJ
SOJ
XE Cerpack (F11 Config. only)
'Consult Factory
1.4
lOT PACKAGE MARKING DESCRIPTION
PART NUMBER DESCRIPTION
4.
lOT's part number identifies the basic product, speed,
power, package(s) available, operating temperature and
processing grade. Each data sheet has a detailed description,
using the part number, for ordering the proper product for the
user's application. The part number is comprised of a series
of alpha-numeric characters:
5.
1. An "lOT" corporate identifier for Integrated Oevice
6.
2.
3.
Technology, Inc.
A basic device part number composed of alpha-numeric
characters.
A device power identifier, composed of one or two alpha
characters, is used to identify the power options. In most
cases, the following alpha characters are used:
"S" or "SA" is used for the standard power product.
"L" or "LA" is used for lower power than the standard
power product.
7.
A device speed identifier, when applicable, is either alpha
characters, such as "A" or "8", or numbers, such as 20 or
45. The speed units, depending on the product, are in
nanoseconds or megahertz.
A package identifier, composed of one ortwo characters.
The data sheet should be consulted to determine the
packages available and the package identifiers for that
particular product.
A temperature/process identifier. The product is available
in either the commercial or military temperature range,
processed to a commercial specification, or the product is
available in the military temperature range with full
compliance to MIL-STO-883. Many of lOT's products
have burn-in included as part of the standard commercial
process flow.
A special process identifier, composed of alpha characters,
is used for products which require radiation enhancement
(RE) or radiation tolerance (RT).
Example for Monolithic Devices:
lOT
XXX ... XXX
xx
X.. X
X... X
x
XX
TL;
Special Process
Processffemperature*
PackageSpeed
Power
Device Type-
* Field Identifier Applicable To All Products
2507 drw 01
ASSEMBLY LOCATION DESIGNATOR
MIL-STD-883C COMPLIANT DESIGNATOR
lOT uses various locations for assembly. These are
identified by an alpha character in the last letter of the date
code marked on the package. Presently, the assembly
location alpha character is as follows:
A = Anam, Korea
I = USA
P = Penang, Malaysia
lOT ships military products which are compliant to the latest
revision of MIL-STO-883C. Such products are identified by a
"e" designation on the package. The location ofthis designator
is specified by internal documentation at lOT.
1.5
II
First-In, First-Out Memories (FIFOs)
•
•
•
•
•
Largest and most complete FIFO product line
Easy to use, highly integrated data buffering solutions
Represents the culmination of over 11 years of architectural
innovation and technical expertise
SYNCHRONOUS (CLOCKED) BIDIRECTIONAL FIFOs
•
•
•
•
SUPERSYNCS: NEXT GENERATION CLOCKED
FIFOs
•
•
•
•
•
•
Large density: SK, 16K, and 32K words (9- and 1S-bit wide)
Ultra high-performance pipe lined architecture-100MHz
(Sns access time)
Utilizes less expensive SRAM technology for low costlbit
Read, write clocks can be synchronous or simultaneous
Auto Power Down minimizes external power management
logic circuit needs
Numerous easy to use add ons: partial reset, retransmit,
serial loading, programmable flags, standard or first word
fall through
mode, and space saving 64-pin Thin Quad Flat Pack
(TQFP)
•
•
•
•
Bus-matching for 1S/9-bit, 36/9-bit or 36/1S-bit connections
Bi-directional FIFOs for 9 or 1S bit parallel connections
Bypass path for direct status/command or data interchange
Programmable depths for Almost-Empty and Almost- Full
flags
Standard DMA control pins for peripheral interfaces
Rereadlrewrite capabilities
ASYNCHRONOUS UNIDIRECTIONAL FIFOs
• High-performance-12ns data access times
• 3.3V versions for low power consumption
• Various FIFO depths-256 to 16K
• Asynchronous or simultaneous reads and writes
• Simple width and depth expansion
• Surface mount package solutions
• Multiple flags- Full, Empty. and Half-Full
• Configurable Parallel/Serial versions
• Dedicated serial to parallel or parallel to serial versions
Ultra high-performance-S3MHz
1-,S-, 9-, 1S- and 36-bit wide widths
Various FIFO depths-64 to 4K
Read, write clocks can be asynchronous or simultaneous
Programmable depths for Almost-Empty and Almost-Full
flags
Simple word width expansion
Part
No.
Very high-performance-50MHz
1S-, and 36-bit wide words
Read, write clocks can by asynchronous or simultaneous
Programmable depths for Almost-Empty and Almost-Full
flags
Space saving 64-pin Thin Quad Flat Pack (TQFP)
ASYNCHRONOUS BIDIRECTIONAL FIFOs
•
•
•
•
SYNCHRONOUS (CLOCKED) UNIDIRECTIONAL
FIFOs
•
•
•
•
•
Depth expansion versions available
Space saving 64-pin Thin Quad Flat Pack (TQFP)
Descrietion
Max.
Max. Speed (ns) Power
Mil.
Com'l. ImWl Avail.
Fax
Doc.
No.
Data
Book
Pase
SUPERSYNCS: NEXT GENERATION CLOCKED FIFOs
IDT72261
16Kx 9
(Depth expandable)
15
10
660
NOW
3036
15.20.
IDT72271
32Kx 9
(Depth expandable)
15
10
660
NOW
3036
15.20.
IDT72255
8Kx 18
(Depth expandable)
15
10
770
NOW
3037
15.21.
IDT72265
16K x 18 ~Deeth exeandablel
15
10
770
NOW
3037
15.21.
CAL~
SYNCHRONOUS {CLOCKED} UNIDIRECTIONAL FIFOs
IDT72423
64 x 1
15
10
440
NOW
2747
IDT72203
256 x 1
15
10
440
NOW
2747 CALL.
IDT72213
512 x 1
15
10
440
NOW
2747 CALL.
IDT72420
64 x8
20
12
440
NOW
2680
5.12
IDT72200
256x8
20
12
440
NOW
2680
5.12
IDT72210
512x 8
20
12
440
NOW
2655
5.12
IDT72220
1Kx 8
25
15
440
NOW
2680
5.12
IDT72230
2Kx8
25
15
440
NOW
2680
5.12
IDT72240
4Kx8
25
15
440
NOW
2680
5.12
IDT72421
64 x9
20
12
440
NOW
2655
5.13
IDT72201
256 x 9
20
12
440
NOW
2655
5.13
IDT72211
512x 9
20
12
440
NOW
2655
5.13
IDT72221
1K x 9
25
15
440
NOW
2655
5.13
IDT72231
2Kx 9
25
15
440
NOW
2655
5.13
IDT72241
4Kx9
25
15
440
NOW
2655
5.13
IDT72801
Dual 256 x 9 (Configurable)
15
700
NOW
3034
5.15
1.6
First-In, First-Out Memories
~FIFOsl
Part
No.
Descrietion
IDT72811
Dual512 x 9 (Configurable)
IDT72821
Dual 1K x 9 (Configurable)
IDT72831
IDT72841
IDT72205LB
256 x 18 (Depth expandable)
IDT72215LB
512 x 18 (Depth expandable)
Max.
Max. Speed (ns) Power
Mil.
Com'l. ~mWl Avail.
15
700
NOW
Fax
Doc.
No.
Data
Book
Pase
3034
15.15
15
700
NOW
3034
15.15
Dual2K x 9 (Configurable)
15
700
NOW
3034
15.15
Dual 4K x 9 (Configurable)
15
700
NOW
3034
15.15
25
15
1100
NOW
2766
15.14
25
15
1100
NOW
2766
15.14
IDT72225LB
1K x 18 (Depth expandable)
25
15
1100
NOW
2766
15.14
IDT72235LB
2K x 18 (Depth expandable)
25
15
1100
NOW
2766
15.14
IDT72245LB
4K x 18 (Depth expandable)
25
15
1100
NOW
2766
15.14
3024
15.22.
IDT72825
Dual 1K x 18 (Configurable)
20
1700
NOW
IDT723611
64 x36
15
1100
NOW
CALL.
CALL.
IDT723613
64 x 36 bus matching
15
1100
NOW
IDT723631
512 x 36
15
1200
NOW
IDT723641
1K x36
15
,!101:723651
!2KX36i '!'
15
NOW 3023 15.26
1400' ;20f95;;' 3023':" 15!26::':!!!"
SYNCHRONOUS~CLOCKEDl
3023
15.26
1300
BIDIRECTIONAL FIFOs
IDT72605
256 x 18 x 2 dual memory bank
30
20
1375
NOW
2704
15.16
IDT72615
512 x 18 x 2 dual memory bank
30
20
1375
NOW
2704
15.16
3025
IDT723612
64 x 36 x 2
15
1200
NOW
IDT723614
64 x 36 x 2 bus matching
15
1200
NOW
IDT723622
256 x 36 x 2
15
1250
NOW
3043
15.25
15
1300
NOW
3022
15.24
IDT723632
512 x 36 x 2
iHO"F'l23642!,i'! h
Heade r ......
if
AAL 3/4
Payloadas
Trahsferred
toHost
Bi~31
Bit
n>
';"'.:'
____ ?c/
.... :;,."";
Ie
/.~
,,"
'~
> Cell 1
':,:
....
';',
:.;"
jiL/
.,".
::,
.':::: ;;;,: ;'~r\
9
.';;'''':'>
,
..:
'"
>Ce1l1
:"<
TrailE
',.",
'l'"
<>,,':;;:
'.
'.1
.. ,'1::.,:.;
if
a
··;··:·;10··......
)
Trailer
Header
I'"
Header '\
:':';;;:':";':
'"''
:
""",":"
'::,;::::;::
"'''''''':
Cell 2
> Cell 2
::>:'.,',':.
Trl'lilp.r
';;;;;;;
;,,,,,,,
.;,,:;
/
:.
Trailer
Header I......
3138 drw05
AAL5 cell contains a 48 byte payload (with the possible
exception of the last cell), the cell payload is mapped directly
into 12 32-bit words and transferred as shown below.
The above diagram illustrates a Small Free Buffer for
storing the first ATM cell payload, followed by successive
Large Free Buffers. The NICStAR accumulates a CRC-32
value for all AAL5 cells from a VC, and stores the running total
in the Receive Connection Table. When the last AAL5 cell is
received from a specific VC, the NICStAR compares it's final
calculated CRC-32 value to the CRC-32 value contained
within the last AAL5 cell's payload.
3138 drw04
- AAL3/4
9. After an "end of PDU" is detected, the device driver
reads the Receive Status Queue, generates a list of host
memory buffer addresses which constitute the received
CS-PDU and then provides the list of addresses to the
application program(s) for converting back to user data.
- ATM Adaptation Layer (AAL) Support
As a VC connection is being established, the NICStAR
assigns it a specific AAL format identifier, which is maintained
in the local SRAM's Receive Connection Table. The following
are descriptions of how each AAL format is supported:
-AAL5
AAL5 cells are reassembled by the NICStAR and stored
directly to the appropriate host memory buffers. As each
5.01
As the first byte (header) and the last two bytes (trailer) of
an AAL3/4 payload contain overhead information, AAL3/4
cells receive special processing.
As illustrated in drawing 5, the NICStAR shifts the header
to payload byte positions 47 and 48, and leaves the AAL3/4
trailer in it's original location (payload bytes 45 and 46). In
addition, payload data is all shifted to an even word boundary.
Transferring the cell payload in this format to the host system
supports subsequent data processing effiiciency. On receiving the cell payload, the device driver merely decodes the
AAL3/4 header and trailer, followed by a simple word-aligned
reassembly into a complete CS-PDU. The NICStAR calculates a payload CRC-1 0 value and stores it in the trailer. If the
NICStAR detects a CRC error, it will set an error bit in the
Receive Status Queue for the host memory buffers associated with this CS-PDU.
12
II
I0T7720 1
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
-OAM Cells
COMMERCIAL TEMPERATURE RANGE
- "AALO"
Operations and Management (OAM) cells are identified by
"AALO" cells are ATM cells which conform to the 5 byte
several reserved (ATM Forum specification) VPINCI ad- header, 48 byte payload structure of "general" ATM cells, but
dresses, as well as several of the possible states contained in which do not fit within the requirements of other AAL formats.
the Payload Type Identifier (PTI) field ofthe cell header. Since These "AALO" cells are treated identical to AAL5 format cells,
the header of OAM cells contains useful information, the entire but without CRC processing and checking.
cell is transferred to host memory; specifically stored in the
Using "AALO", the NICStAR provides a means to support
Raw Cell Queue (see Raw Cell below). There are three future AAL definitions. The device driver, on receipt of an
AALO CS-PDU could perform additional payload (or PDU)
possible OAM cell states:
1. Currently established VPINCI connections which may processing as required by the newly defined AAL.
be passing application data; these connections may also pass
OAM cells (ie, without application data) by setting certain PTI - "Raw Cells"
bits in the cell header. OAM cells of this type are detected by
"Raw Cells" are defined as follows:
the NICStAR and transferred to the Raw Cell Queue in host
1. Identified as "Raw Cell" in the Receive Connection
memory. The NICStAR may optionally generate an interrupt Table, by a particular VC.
upon completion of the transfer.
Host Memory
SRAM
Rx SRAM CELL
FIFO
Rx Input FIFO
IIIIIIIIIIII-----+----.-~
UTOPIA IIF •
Queue size = 3 words.
Queue size
=315 cells
Rx Cell Queue
Tail Pointer
......
......
......
......
~
~
......
...... ~
Rx BIU FIFO
IIIIIIIIIIIII-+------.-
IIIIIIIIIIII_PCI~BUS
......""
tgr:c::::;:=::~:=;::r~
Queue size = 12 words
......
/
/
Rx Cell Queue Head
Pointer
/
I
Raw Cell Queue Tail
Pointer
I
Raw Cell Queue
Head Pointer
3138 dlW 06
2. 'Special' VPINCI connections which may be assigned
for OAM cell communication. These are assembled according to their AAL format (created on establishment of connection). Operation continues as 'normal'; the device driver is
interrupted as each CS-PDU is reassembled.
3. 'Unidentified' VPINCI combinations are those ATM cells
which are received, but which do not have a corresponding
entry in the Receive Connection Table. These cells are
passed on to the "Raw Cell Queue" (described in the- AALO
section below) for identification processing.
5.01
2. Unknown VPINCI (entry not found in Receive Connection Table). This is selectable via the host driver: "Unknown"
traffic may either be discarded, or placed in a Raw Cell Queue.
3. OAM cells (defined either by specific VC or PTI bits).
The diagram below illustrates the path flow of an incoming
"Raw Cell" arriving via the UTOPIA interface, and its deposition
into a Raw Cell Queue.
Note that Raw Cells are transferred in their entirety (payload
and header) to the Raw Cell Buffer Queue for processing within
the host.NICStAR Transmit Operation.
13
IOTI7201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
Transmit
Schedule
Table
Segment
Descriptor
Cache
SRAM
COMMERCIAL TEMPERATURE RANGE
SAR
PCI BUS
.~~W
LtJ'l-1----'
CPU
Host Memory
lOT n201 SAR Controller Transmission Data Flow
As CS-PDUs are available, the NICStAR continuously
segments and transmit ATM cells at the full 155 Mbps "wire
speed". It simultaneously accomodates Constant Bit Rate
(CBR), Unassigned Bit Rate (UBR), Available Bit Rate (ABR),
and Variable Bit Rate (VBR) traffic types. Depending on the
amount of external SRAM, the NICStAR supports up to 16K
open CBR connections; independent of the size of the SRAM,
it always supports the maximum of 16,000,000 VC connections (the full 24 bit VPINCI address space).
This section describes the overall transmission portion of the
NICStAR. Following sections describe the Transmit Buffer Descriptors (TBDs) and the Transmit Cell Schedule Table (TCST), which
manages the overall channel bandwidth and provides CBR connections with "guaranteed" bandwidth allocation.
Following the above diagram by the numbers:
1. As a CS-PDU becomes available for transmit, the
device driver creates Transmit Buffer Descriptors (TBDs)
for the sequence of buffers in host memory which constitute the CS-PDU, and then writes the TBDs into a TBD
queue, located in host memory.
2. The device driver then causes the NICStAR to copy the
first one or two TBDs to local SRAM.
3. The NICStAR reads the first TBD. The ATM cell
header, also part of this buffer descriptor, is loaded into
3138 drw 07
the output FIFO. During this process, a HEC byte place
holder (OOh) is added as the fifth byte of the header.
4. The PCI bus is arbitrated using the address and length
taken from the TBD.
5. The ATM cell payload is transferred from host memory
to the output FIFO via DMA. On completion, the 53-byte
ATM cell is transferred out of the NICStAR via the
UTOPIA interface.
6. Status information is returned to the host system to
communicate transmission state, error conditions, etc.
• Transmit Buffer Descriptors
A Transmit Buffer Descriptor (TBD) is a four word descriptor which contains information such as the base address of a
buffer in host memory, the number of words in the buffer, the
AAL format of the information in the buffer (used when
segmenting the buffer into ATM cells) and the ATM cell header
(all TBDs in the same queue have identical cell headers; that
of the first ATM cell of the CS-POU).
The device driver writes the TBDs into a TBO Queue in host
memory, and then increments a pointer to the queue in local
SRAM, which causes the NICStAR to copy the first one or two
TBOs to local SRAM. The NICStAR then reads the TBO and
begins it's transmits process. The information contained in a
5.01
14
10177201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
TBD is dependent upon which traffic type is stored in the
corresponding Tx buffer:
COMMERCIAL TEMPERATURE RANGE
Tx Cell Schedule
Table TCST
CBR Traffic:
• Control Information (e.g. interrupt at end, etc)
• Cell Header
• Buffer Size, Base FIFO Address
SRAM
CBR
Descriptor
........
........
Caclie
........
( CH1 Buf
( Desc cache
,, , -, v.
l-
UBR/ABRNBR Traffic:
• Timer mantissa and exponent
• Interrupt at EOB
• Buffer Address, Size
• Status
• Segment Length
• Cell Header
I-
~
~.,,>j
-
X:/
-/
-/
The NICStAR maintains 3 types of transmit descriptor
caches (queues):
1. CBR
This cache holds two entries from each open CBR connection. This ensures that an entry is always immediately available for each connection, under schedule control of the
NICStAR's Transmit Cell Schedule Table.
~
i"-J
:~~~::~
( :«««,
CH2 Buf
Desc cache
CHn Buf
Desc cache
Last Table entry
OAMTx
Cell
Descriptor
•. §
ABRNBR
Descriptor
Cacne
2. DAM
This cache is reserved for OAM cells which are considered
higher priority than UBRNBR traffic, but are to be sent only
during time slots not reserved for CBR connections.
3. UBR/ABRNB~
This cache consists of two sections a "high speed" cache
and "low speed" cache. This separation provides a 'passing
.~
(
(
(
(
(
(
(
(
(
IABR cell Timer 11
IABR cell Timer 21
§F
High Speed'
~.:.:
~()\V~PE!E!~
OAM Cell
Desc cache
ABR Buf Desc
cache for High
Speed.
ABR Buf Desc.
cache for Low
Speed.
3138 drw 09
SAR
lane' for higher-speed/higher-prioritytraffic. Descriptors in the
"Low Speed" queue are serviced only after the "High Speed"
queue is empty, ensuring that higher-speed traffic is shipped
at the highest data rate possible without exceeding its negotiated bandwidth. The facility operates under software control
such that it can be tailored for specific applications and/or
current operating conditions .
..
Host Write
..
Host Write
Host Write
..
Host Read
•
ABR/CBR Tx
Status Queues
SAR Write
..
IQIXIIXII
Host Write
ABR CH1 Tx Desc.
..
a
SAR Read
111111111111
Ho t W 't ABRHighSpeedTx'Oesc:a SAR Read
s
~I e i,
11111111111\
..
Host Write ~BR Low Speed Tx Desc. SAR Read
a
::
11111111111:
OAM
TxCell
Descriptor
..
ABRNBR TxBuf.
Desc.l Status
Queues
---l~~
• Transmit Schedule Table (TST)
The Transmit Schedule Table is used to guarantee CBR
transmission at fixed data rates and specific timing intervals
within the system bandwidth. The TST is a circular table, in
local SRAM, which the NICStAR continually scans to allocate
bandwidth and control which connection is serviced. The
number of entries in the table is equivalent to the line speed
divided by the desired bandwidth resolution .
As an example, a 155Mb/s line would support 2430 64Kb/
CBR conneactions. Since the TST is scanned many times
each second, any CBR channel may be allocated bandwidth
in multiples of 64Kb/s. Each 64Kb/s entry 'contains' one linespeed cell time, which at 155Mb/s equals 2.7.lls. lit contains
ABRNBR
Descriptor
Cache
..
3138 drw 0,8
5.01
15
IDT77201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
COMMERCIAL TEMPERATURE RANGE
TCST Entry Control Flow Chart
II
3138 drw 10
It contains three entry types:
1. CBR
2.0AM
3. ABR
4. VBR
CBR entries are VC-specific: it tells the SAR exactly which
connection is to be serviced at that time. All other entry types
designate available opportunities to transmit these data types.
Each TCST entry is either CBR, OAM, or ABRNBR. If the entry
is not defined, or cells are not available for transmission, a null cell is
generated and transmitted. This feature is provided to assist users
in integrating the 77201 SAR with PHY transceivers which may not
have automatic null cell generation.
Each ABRNBR entry has associated with it, a timer value which
is used to throttle its transmission speed based upon the bandwidth
allocated to it when the connection was established. Thus, if the
TCST is servicing an ABRNBR entry, the entry can point to one of
two possible states:
1. A new buffer descriptor. In this case, the ~imer' is set to zero,
since this connection has not been serviced yet. Once a cell
has been transmitted, the timer is set for countdown.
2. A buffer descriptor whose transmission is 'in progress'. Data
remains in the buffer. If the bandwidth-timer has timed out, a
cell from this buffer is transmitted. Otherwise, flow control is
transferred to check the "Low Speed" timer (Timer #2), which
operates in the same way for entries in the "Low Speed"
buffer descriptor cache.
5.01
16
IDT77201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
COMMERCIAL TEMPERATURE RANGE
PCLCLK
AD31-0
Add
C/BE3-0
Cmd
Data3
BE3-0
FRAME#
IRDY#
DEVSEL#
TRDY#
REQ#
__________________________________________-J/
,'------3138 drw fig 02
Figure 1. The NICStAR as a PCI master (illustrates a 4-word write by the NICStAR to host memory)
5.01
17
IDT77201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
COMMERCIAL TEMPERATURE RANGE
PCLCLK
AD31-0
( Add
X
C/BE3-0
(
X
Cmd
FRAME#
IRDY#
DEVSEL#
TRDY#
PERR#
SERR#
Data1
X
Data2
>< Data3 )
)
BE3-0
( ParA
PAR
X
DataO
X
ParDO
X
ParD1
X
ParD2
>< ParD3 >
/
"
/
"
"
"
"
/
II
/
"
/
/
3138 drw fig 01
Figure 2. The NICStAR as a PCI target (illustrates a 4-word write operation by the host device driver to the
NICStAR)
5.01
18
IDT77201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
COMMERCIAL TEMPERATURE RANGE
-
~t7'
I-t5- -t6
.. t2..
TxClk,RxClk
TxData 7-0
~t1J~
~
I--tS-}t9•
t4"
--' h.--rrLL r ' -
I
t1
TxSOC
\
TxEnb#
I
TxParity
TxFull#
RxEnb#
\
.-
RxData 7-0
'--------"
"
I
RxSOC
\'-_ _----t!
RxEmpty#
3138 drwfig 03
Figure 3. UTOPIA Bus Timing
5.01
19
-
IDT77201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
COMMERCIAL TEMPERATURE RANGE
--~----------------M6------------------~
~--------~~------M4--------------------~
I4--+---M5-.l:1
1-------tw9-----------:t-·- tw10 -
------------~<~~A~d~d~r~es~s~~>____<~_________________V~a~li~d~D~a~ta~____~>_____
3138 drw lig 04
Figure 4. Utility Bus Write Cycle
II
r
tr6
t
'l
~tr7
- tr2
.... ~tr8 ~I+- tr3 -
/
tr4
I
\
tr5
tr9
\
----------~<~
:1
tr10 -
I
__lA~d~d~re~ss~__J>____<~________________~V~a~hd~D~a~ta~______J>_____
3138 drwlig 05
Figure 5. Utility Bus Read Cycle
5.01
20
IDT77201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
COMMERCIAL TEMPERATURE RANGE
l-t3-
t41
Address
I--
t5
~t1"
t7t2-.
-
\
tB-
t6"
/
Data31-0 --------------------------------------------~<~
___________J>___
3138 dlWfig 06
Figure 6. SRAM Bus Write Cycle Timing
Address
_----..~~I_===-~~-tBI========f+-1-----..X-t1
>-
~t1"
r
- t2
tS
-
_
\
t5r- t3"'
\
Data31-0
------------------------------------------~<~----------~>--3138 dlW fig 07
Figure 7. SRAM Bus Read Cycle Timing
5.01
21
IDT77201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
t2~
COMMERCIAL TEMPERATURE RANGE
t5
~t3~-
t6
r----------------------------------------------+~
Address
)
t4
\
<
Data31-0
t1
Valid Data
-I
>-
3138 drw fig 08
Figure 8. EPROM Timing
II
SAR_CLK
EECS
\
/
EECLK
EEDO
I
\
\
/
,
I
EEDI
I
'--
'--3138 drw fig 09
Figure 9. EEPROM Timing
5.01
22
IOTI7201
155Mb/s ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
nnnnn
a
nnn
a
Device Type
Power
Speed
Package
a
--t:
Process/
Temp. Range
L...--_I
Commercial
Blank
155
Speed in Mb/s
77201
155Mb/s ATM Segmentation &
Reassembly (SAR) Controller for the
PCI Local Bus
3138 drw 13
ADVANCE INFORMATION DATASHEET: DEFINITION
"Advance Information" datasheets contain initial descriptions, subject to change, for products that are in development,
" including features and block diagrams.
Datasheet Document History
8/11/94: Initial Public Release
9/28/94: Pinout and Pin Definitions updated.
12/8/94: Pinout revised to final.
12/21/94: Pin 133 changed from EECS* to EECS with
input polarity selectable via command register.
5.01
23
t;J®
CMOS SUPERSYNC FIFOTM
16,384 x 9, 32,768 x 9
PRELIMINARY
IDT72261
IDT72271
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16,384 X 9-bit storage capacity (IDT72261)
32,768 x 9-bit storage capacity (lDT72271)
10ns read/write cycle time (8ns access time)
Retransmit Capability
Auto power down reduces power consumption
Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
Empty, Full and Half-full flags signal FIFO status
Programmable Almost Empty and Almost Full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select lOT Standard timing (using EF and FF f~s) or
First Word Fall Through timing (using OR and IR flags)
Easily expandable in depth and width
Independent read and write clocks (permit simUltaneous
reading and writing with one clock signal
Available in the 64-pin Thin Quad Flat Pack (TQFP), 64pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
Output enable puts data outputs into high impedance
High-performance submicron CMOS technology
DESCRIPTION:
The IDT72261172271 are monolithic, CMOS, high capac-
ity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs are
applicable for a wide variety of data buffering needs, such as
optical disk controllers, local area networks (LANs), and interprocessor communication.
Both FIFOs have a 9-bit input port (On) and a 9-bit output
port (Qn). The input port is controlled by a free-running clock
(WCLK) and a data input enable pin (WEN). Data is written
into the synchronous FIFO on every clock when WEN is
asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (REN). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output
enable pin (OE) is provided on the read port for three-state
control of the outputs.
The IDT72261172271 have two modes of operation: In the
lOT Standard Mode, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the First Word Fall Through Mode
(FWFT), the first word written to an empty FIFO appears
automatically on the outputs, no read operation required. The
state of the FWFT/SI pin during Master Reset determines the
mode in use.
The IDT72261/72271 FIFOs have five flag functions, EFI
FUNCTIONAL BLOCK DIAGRAM
WEN
00-08
WCLK
FFiiFi
PAF
EEL.9R
HF
,EAE
RAM ARRAY
16,384 x 9
8,192 x 9
RESET LOGIC
FWFT/SI
'-----...-----i-~ RCLK
'----------------e--. REN
FS
~
TIMING
I
-
SyncFIFO is a trademark and the lOT logo
IS
00-08
a registered trademark of Inte9,fii,d DeVice Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994 Integrated Device Technology. Inc
3036drw 01
MAY 1995
DSC-206314
5.02
IDTI2261n2271 SyncFIFOTM
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input
Ready), and HF (Half-full Flag). The EF and FF functions are
selected in the IDT Standard Mode.
The IRand ORfunctions are selected in the First Word Fall
Through Mode. IR indicates that the FIFO has free space to
receive data. OR indicates that data contained in the FIFO is
available for reading.
HF is a flag whose threshold is fixed at the half-way point in
memory. This flag can always be used irrespective of mode.
PAE, PAF can be programmed independantly to any point
in memory. They, also, can be used irrespective of mode.
Programmable offsets determine the flag threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, such that PAE can be set at
127 or 1023 locations from the empty boundary and the PAF
threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with LD during Master
Reset.
In the serial method, SEN together with LD are used to load
the offset registers via the Serial Input (SI). In the parallel
method, WEN together with LD can be used to load the offset
registers via Dn. REN together with LD can be usedto read the
offsets in parallel from On regardless of whether serial or
parallel offset loading is selected.
During Master Reset (MRS), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The LD pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.
The Partial Reset (PRS) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly. PRS is
useful for resetting a device in mid-operation, when reprogramming offset registers may not be convenient.
The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when RT is LOW. This feature is convenient for
PIN CONFIGURATIONS
PIN 1
r- r- r- r- r-
-
r- ;- r- r- r- r-
f- f- f- f- f-
-
f- ;- r
f - f - ff- f- f- f - f - f-
l- I- l- f- f-
-
-
r- r- r-
r'-
~
-
r
f-
64636261605958575655545352515049
1
48
I I
47
I I
I ONe
3
46
4
45
44
I I
I I
I I
I GNO
I ONe
I ONe
43
I I
I
42
I I
I ONe
I
I
I
I
Vee
I
I I
5
GNO(2) I
Ij
6
GNO(2) I
I I
7
GNO(2) I
II
I I
8
GNO(2) I
I I
10
39
GNO(2) I
GNO(2) I
Ll
11
I I
12
GNO(2) I
11
13
GNO(2) I
I
I
I
I
2
WEN I
SEN I
FS I
Vee I
PN64-1
PP64-1
9
I ONe
Vee
41
I I
I ONe
40
I ONe
I GNO
38
I I
I I
I I
37
I I
I ONe
36
I 08
J 07
I 06
I GNO
GNO(2) I
I I
14
35
08 I
07 I
I I
I I
15
34
I I
I I
I I
16
33
I I
j ONe
1718 192021 2223 24252627 28 293031 32
-- -- -- -- -- - '-
ff-
- - -
'-
- -
-- -- -
'f-
--
If-
'- '- '-
-
- -
;-
-
'-
-
3036 drw 02
NOTES:
1. DNe = Do not connect.
2. This pin may either be tied to ground or left open.
TQFP
STQFP
TOP VIEW
5.02
2
IDn2261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
sending the same data more than once.
If,atanytime, the FIFO is not actively perfonning a function,
the chip will automatically power down. This occurs if neither
a read nor a write occurs within 10 cycles of the faster clock,
RCLKorWCLK. Duringthe Power Down state, supply current
consumption (lCC2) is ata minimum. Initiating any operation
(by activating control inputs) will immediately take the device
out of the Power Down state.
The IDT7226102271 are depth expandable. The addition
of external components is unnecessary. The IR and OR
functions, together with REN and WEN, are used to extend the
total FIFO memory capacity.
The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency
The IDT7226102271 is fabricated using lOT's high speed
submicron CMOS technology.
PIN CONFIGURATIONS (CONT.)
DNC 05 Vee 02
11
10
09
06 GND 04
01 GND D1
D3
D5
Do
D4
D6
03 GND 00
D2
(1
08 07
GNO
(1
DNC GND
GNO
G68-1
06 DNC DNC
03 DNC DNC
Pin 1 Designator
B
./
C
GNOCll
w
GNO(1 )
Vee Vee
SEN FS
FE DNC LD weLK WEN
IR
EFt Vee PAF GND
RT RCLK OR
A
)
Cll
GNO
02 DNe OE REN GND PAE HF
01
D8
GNOCll GNO
05 DNC Vee
04 GND DNC
)
(1
GNd 1 ) GNO )
08 DNC DNC
07
D7
D
E
F
FWFTI
G
SI
H
MRS PRS
J
K
L
3036drw 03
PGA
TOP VIEW
NOTES:
1. DNC = Do not connect.
2. This pin may either be tied to ground or left open.
5.02
3
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
va
Description
Do-Os
Data Inputs
I
Data inputs for a 9-bit bus.
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or lOT
Standard Mode, one of two programmable flag default settings. and serial or
parallel programming of the offset settings.
PRS
Partial Reset
I
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset,the existing mode (lOT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT
Retransmit
I
Allows data to be resent starting with the first location of FIFO memory.
FWFT/SI
First Word Fall
Through/Serial In
I
During Master Reset, selects First Word Fall Through or lOT Standard mode.
After Master Reset, this pin fUnctions as a serial input for loading offset registers
WCLK
Write Clock
I
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers.
WEN
Write Enable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by REN. the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN enables RCLK for reading data from the FIFO memory and offset registers.
REN
Read Enable
I
OE
Output Enable
I
SEN
Serial Enable
I
SEN enables serial loading of programmable flag offsets
LD
Load
I
During Master Reset, LD selects one of two partial flag default offsets (127 and
1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.
OE controls the output impedance of
an
FS
Frequency Select
I
The FS setting optimizes data flow through the FIFO.
FF/IR
Full Flag/
Input Ready
0
In the lOT Standard Mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the TR function is selected. iR
indicates whether or not there is space available for writing to the FIFO memory.
EF/OR
Empty Flag!
Output Ready
0
In the lOT Standard Mode, the EF function is selected ...,Ef indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR fUnction is selected.
OR indicates whether or not there is valid data available at the outputs.
PAF
Programmable
Almost Full Flag
0
PAF goes HIGH if the number of free locations in the FIFO memory is more than
offset m which is store in Almost Full which is stored in the Full Offset register. PAF
goes LOW if the number of free locations in the FIFO memory is less than m.
PAE
Programmable
0
Almost Empty Flag
PAE goes LOW if the number of words in the FIFO memory is less than offset n
which is stored in theEmpty Offset register. PAE goes HIGH if the number of
words in the FIFO memory is greater than offset n.
HF
Half-full Flag
00-08
Data Outputs
Vee
Power
+5 volt power supply pins.
GND
Ground
Ground pins.
0
0
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 9-bit bus.
3097tblOl
5.02
4
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TA
Rating
Commercial
Terminal Voltage
-0.5 to +7.0
with respect to GND
o to +70
Operating
Temperature
Mlllitary
Unit
-0.5 to +7.0
V
-55 to +125
DC
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
Min.
Typ.
Max.
Unit
VCCM
Military Supply
Voltage
Parameter
4.5
5.0
5.5
V
Vccc
Commercial Supply
Voltage
4.5
5.0
5.5
V
TSIAS
Temperature Under -55 to +125
Bias
-65 to +135
DC
GND
Supply Voltage
TSTG
Storage
Temperature
-55 to +125
-65 to +155
DC
VIH
lOUT
DC Output Current
50
50
mA
VIH
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
NOTE:
3097tb102
VIL(l)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maimum rating conditions for extended periods may
affect reliabilty.
0
0
0
V
2.0
-
-
V
2.2
-
-
V
-
-
0.8
V
NOTE:
3097tb103
1. 1.5V undershoots are allowed for 1Ons once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc =5V ± 10%, TA =O°C to +70°C; Military: Vcc =5V ± 10%, TA =-55°C to +125°C)
D172261L
ID172271L
Commercial
tCLK 10, 12,15, 20ns
ID172261L
ID172271L
Military
tCLK 15, 25ns
=
Symbol
Parameter
=
Min.
Typ.
Max.
Min.
IU(l)
Input Leakage Current (any input)
-1
-
1
-10
-
10
ILd2)
Output Leakage Current
-10
-
10
-10
-
10
VOH
Output Logic "1" Voltage, IOH = -2 mA
2.4
2.4
V
0.4
0.4
V
ICC1(3)
Active Power Supply Current
-
Icc2(3,4)
Power Down Current (All inputs = VCC - 0.2V or
-
-
-
Output Logic "0" Voltage, IOL = 8 mA
-
-
VOL
-
150
15
Typ.
-
Max.
Unit
IlA
IlA
200
mA
25
mA
GND + 0.2V, RCLK and WCLK are free-running)
NOTES:
1.
2.
3.
4.
3097tb104
Measurements with 0.4 :'> VIN :'> Vcc.
OE= VIH
Tested at f = 20 MHz with outputs unloaded.
No data written or read for more than 10 cycles
CAPACITANCE (TA =+25°C, f
= 1.0MHz)
Symbol
Parameter(l)
Conditions
Max.
Unit
CIN(2)
Input
Capacitance
VIN =OV
10
pF
COUT(l,2)
Output
Capacitance
VOUT= OV
10
pF
3097tb105
NOTES:
1. With output deselected, (OE=HIGH).
2. Characterized values, not currently tested.
5.02
5
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: vcc = 5V ± 10%, TA= O°C to +70°C; Military: Vcc= 5V ± 10%, TA= -55°C to +125°C)
Commercial
72261L10
72271L10
Symbol
Parameter
fs
Clock Cycle FrequenQY
tA
Data Access Time
tCLK
Clock Cycle Time
tCLKH
Clock Hiqh Time
tCLKL
Clock Low Time
Max.
Min.
Max.
-
100
8
-
83.3
-
2
12
5
5(2)
9
2
15
6
6(2)
3.5
0
3.5
tDS
Data Set-up Time
tDH
Data Hold Time
tENS
Enable Set-up Time
tENH
Enable Hold Time
0
tLDS
Load Set-up Time
-
-
-
3.5
0
3.5
0
3.5
8.5
12
12
12
10
-
12
-
0
3.5
0
3
7.5
3
7.5
tLDH
Load Hold Time
tAS
Reset Pulse Width(3)
tASS
Reset Set-up Time
tASA
Reset Recovery Time
3.5
6.5
10
10
10
tASF
Reset to Flag and Output Time
-
tFWFT
Mode Select Time
tATS
Retransmit Set-U~ Time
tOLZ
Output Enable to Output in Low
tOE
Output Enable to Output Valid
to HZ
Output Enable to Output in High
0
3.5
0
3
3
twFF
Write Clock to FF or IR
tAEF
Read Clock to EF or OR
-
tPAF
Write Clock to PAF
-
tPAE
Read Clock to PAE
-
tHF
Clock to HF
-
7
7
8
8
8
8
16
2(4)
72261L15
72271L15
Min.
2
10
4.5
4.5(2)
2(4)
Com'l & Mil. Commercial
72261L12
72271L12
-
-
-
-
Min.
4
72261L25
72271L25
Max.
Min.
Max.
Min.
66.7
10
-
50
12
-
1
4
-
-
1
-
-
4
10
15
15
15
-
-
-
0
4
0
3
3
-
9
9
-
18
-
9
9
Military
72261L20
72271L20
-
15
-
-
2
20
8
8
5
1
5
1
5
10
20
-
20
20
-
-
20
0
5
0
3
3
-
-
8
8
10
10
10
10
20
-
10
10
12
12
12
12
22
-
-
3
25
10
10
6
Max.
Unit
40
15
MHz
ns
ns
1
-
6
-
ns
ns
ns
ns
ns
1
-
ns
6
10
25
25
25
-
-
ns
ns
-
ns
0
6
0
3
3
ns
-
ns
25
ns
-
ns
13
ns
ns
-
13
15
15
15
15
25
ns
-
-
ns
ns
ns
ns
ns
ns
tSKEW1
Skew time between RCLK and WCLK
for FF and TR
8
-
10
-
12
-
15
-
20
-
ns
tSKEW2
Skew time between RCLK and
WCLK for PAE and PAF
15
-
18
-
21
-
25
-
35
-
ns
3097tb106
NOTES:
1. All AC timings apply to both Standard lOT Mode and First Word Fall
Through Mode.
2. For the RCLK line: tCLKL (min.) =7 ns only when reading the offsets from
the programmable flag registers; otherwise, use the table value. For the
WCLK line, use the tCLKL (min.) value given in the table.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
UK
D.U.T.
680n
30pF*
GND to 3.0V
3ns
3036 drw 04
1.5V
1.5V
See Figure 1
Figure 1. Output Load
• Includes jig and scope capacitances.
3097tb108
5.02
6
IDT72261n2271 SyncFIFOTM
16,384 x 9,32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming flag settings may
not be convenient.
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (Do - Os)
Data inputs for 9-bit wide data.
RETRAN~MIT
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the Master
Reset (M RS) input is taken to a LOW state. This operation sets
the internal read and write pointers to the first location of the
RAM array. PAEwill go LOW, PAFwillgoHIGH,and HFwill
go HIGH.
If FWFT is LOW during Master Reset then the lOT Standard
Mode, along with EF and FF are selected. EF will go LOW and
FF will go HIGH. If FWFT is HIGH, then the First Word Fall
through Mode (FWFT), along with IR and OR, are selected.
OR will go HIGH and iR will go LOW.
If LO is LOW during Master Reset, then PAE is assigned a
threshold 127 words from the empty boundary and PAF is
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.
If LO is HIGH during Master Reset, then PAE is assigned a
threshold 1023 words from the empty boundary and PAF is
assigned a threshold 1023 words from the full boundary;
1023 words corresponds to an offset value of 3FFH. Following
Master Reset, serial loading of the offsets is permitted, but not
parallel loading.
Regardless of whether serial or parallel offset loading has
been selected, parallel reading of the registers is always
permitted. (See section describing the LO line for further
details).
During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place. MRS is asynchronous.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the Partial
Reset (PRS) input is taken to a LOW state. As in the case of
the Master Reset, the intemal read and write pointers are set
to the first location of the RAM array, PAE goes LOW, PAF
goes HIGH, and HF goes HIGH.
Whichever mode is active at the time of partial reset, lOT
Standard Mode or First Word Fall-through, that mode will
remain selected. If the lOT Standard Mode is active, then FF
will go HIGH and EFwill go LOW. If the First word Fall-through
Mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes. PRS
is asynchronous.
(HT)
The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.
Retransmit Setup is initiated by holding AT LOW during a
rising RCLK edge. REN and WEN must be HIGH before
bringing AT LOW. At least one word, but no more than Full 2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit Setup
(Full = 16,384 words for the 72261, 32.768 words for the
72271 ).
If lOT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit Setup by setting EF LOW. The
change in level will only be noticeable if EF was HIGH before
setup. Ouringthis period, the internal read pointer is initialized
to the first location of the RAM array.
When EF goes HIGH, Retransmit Setup is complete and
read operations may begin starting with the first location in
memory. Since lOT Standard Mode is selected, every word
read including the first word following Retransmit Setup requires a LOW on REN to enable the rising edge of RCLK.
Writing operations can begin after one of two conditions have
been met: EF is HIGH or 14 cycles of the faster clock (RCLK
or WCLK) have elapsed since the RCLK rising edge enabled
by the AT pulse.
The deassertion time of EF during Retransmit Setup is
variable. The parameter tRTF1, which is measured from the
rising RCLK edge enabled by AT to the rising edge of EF is
described by the following equation:
tRTF1 max. = 14*Tf + 3~TRCLK (in ns)
where Tf is either the RCLK orthe WCLK period, whichever is
shorter, and TRCLK is the RCLK period.
Regarding FF: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, FFwill
remain HIGH throughout the setup procedure.
For lOT Standard mode, updating the PAE, HF, and PAF
flags begins with the "first" REN-enabled rising RCLK edge
following the end of Retransmit Setup (the point at which EF
goes HIGH). This same RCLK rising edge is used to access
the "first" memory location. HF is updated on the first RCLK
rising edge. PAE is updated after two more rising RCLK
edges. PAF is updated after the "first" rising RCLK edge,
followed by the next two rising WCLK edges. (If the tskew2
specification is not met, add one more WCLK cycle.)
If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit Setup by setting OR HIGH. The change in
level will only be noticeable if OR was LOW before setup.
During this period, the internal read pointer is set to the first
location of the RAM array.
5.02
7
IDT72261172271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
When ORgoes LOW, Retransmit Setup is complete; atthe
same time, the contents of the first location are automatically
displayed on the outputs. Since FWFT Mode is selected, the
first word appears on the outputs, no read request necessary.
Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. Writing operations can begin
after one of two conditions have been met: OR is LOW or 14
cycles of the faster clock (RCLKorWCLK) have elapsed since
the RCLK rising edge enabled by the RT pulse.
The assertion time of OR during Retransmit Setup is
variable. The parameter tRTF2, which is measured from the
rising RCLK edge enabled by RT to the falling edge of OR is
described by the following equation:
tRTF2 max.
= 14*Tf + 4*TRCLK (in ns)
where Tf is eitherthe RCLK orthe WCLK period, whichever
is shorter, and TRCLK is the RCLK period. Note that a
Retransmit Setup in FWFT mode requires one more RCLK
cycle than in lOT Standard mode.
Regarding IR: Note that since no more than Full- 2 ~ites
are allowed between a Reset and a Retransmit Setup, IR will
remain LOW throughout the setup procedure.
_
For FWFT mode, updating the PAE, HF, and PAF flags
begins with the "last" rising edge of RCLK before the end of
Retransmit Setup. This is the same edge that asserts OR and
automatically accesses the first memory location. Note that,
in this case, REN is not required to initiate flag updating. HF
is updated on the "last" RCLK rising edge. PAE is updated
after two more rising RCLK edges. PAF is updated after the
"last" rising RCLK edge, followed by the next two rising WCLK
edges. (If the tskew2 specification is not met, add one more
WCLK cycle.)
RT is synchronized to RCLK. The Retransmit operation is
useful in the event of a transmission error on a network, since
it allows a data packet to be resent.
FIRST WORD FAll THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. Ouring Master Reset, the state
of the FWFT/SI helps determine whether the device will
operate in lOT Standard mode or First Word Fall Through
(FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then lOT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FI FO memory. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO memory has any free
space for writing. In lOT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (REN) line.
If at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there i~alid data at the data
outputs (an). It also uses Input Ready (IR) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to an, no read request necessary. Subsequent words
must be accessed using the Read Enable (REN) line.
After Master Reset, FWFT/SI acts as a serial input for
loading PAEand PAF offsets into the programmable registers.
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
FWFT/SI functions the same way in both lOT Standard and
FWFT modes.
WRITE CLOCK (WClK)
A write cycle is initiated on the rising edge of the write clock
(WCLK). Oata set-up and hold times must be met with respect
to the LOW-to-HIGH transition of the WCLK. The write and
read clocks lines can either be asynchronous or coincident.
WRITE ENABLE (WEN)
When Write Enable (WEN) is LOW, data can be loaded into
the input register on the rising edge of every WCLK cycle.
Oata is stored in the RAM array sequentially and independently of anyon-going read operation.
.
When WEN is HIGH, the input register holds the prevIous
data and no new data is loaded into the FIFO.
To prevent data overflow inthelOTStandardMode, FF will
go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
_
occur. WEN is ignored when the FIFO is full.
To prevent data overflow in the FWFT mode, IR will go
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle, IR will go LOW allowing a write to occur.
WEN is ignored when the FIFO is full.
READ CLOCK (RClK)
Oata can be read on the outputs, on the rising edge of the
read clock (RCLK), when Output Enable (OE) is set LOW. The
write and read clocks can be asynchronous or coincident.
READ ENABLE (REN)
When Read Enable (REN) is LOW, data is loaded from the
RAM array into the output register on the rising edge of the
RCLK.
When REN is HIGH, the output register holds the previous
data and no new data is loaded into the output register.
In the lOT Standard Mode, every word accessed at an,
including the first word written to an empty FIFO, must be
requested using REN. When all the data has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH after tFWL1 +tREF
and a read is permitted.
In the FWFT Mode, the first word written to an empty FIFO
automatically goes to the outputs an, no need for any read
request. In order to access all other words, a read must be
executed using REN. When all the data has been read from
the FIFO, Output Ready (OR) will go HIGH, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, OR will go LOW after tFWL2 +tREF.
when the first word appears at an ; if a second word is written
into the FIFO, then REN can be used to read it out.
5.02
8
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL ENABLE (SEN)
Serial Enable is (SEN) is an enable used only for serial
programming of the offset registers. The serial programming
method must be selected during Master Reset. SEN is always
used in conjunction with LO. When these lines are both LOW,
data at the SI input can be loaded into the input register one
bit for each LOW-to-HIGH transition of WCLK.
When SEN is HIGH, the programmable registers retains
the previous settings and no offsets are loaded.
SEN functions the same way in both lOT Standard and
FWFT modes.
OUTPUT ENABLE fOE)
When Output Enable (OE) is enabled (LOW), the parallel
output buffers receive data from the output register. When OE
is HIGH, the output data bus (an) goes into a high impedance
state.
LOAD (LO)
This is a dual purpose pin. During Master Reset, the state
ofthe Load line (LO) determines one oftwo default values (127
or1023)forthe PAEandPAFflags, along with the method by
which these flags can be programmed, parallel or serial. After
[5
WEN
REN'
SEN
0
0
1
1
0
1
0
Master Reset, LO enables write operations to and read
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.
Associated with each of the programmable flags, PAE and
PAF, are two registers which can either be written to or read
from. Offset values contained in these registers determine
how many words need to be in the FIFO memory to switch a
partial flag. A LOW on LO during Master Reset selects a
default PAE offset value of 07FH (a threshold 127 words from
the empty boundary), a default PAF offset value of 07FH (a
threshold 127 words from the full boundary), and parallel
loading of other offset values. A HIGH on LO during Master
Reset selects a default PAE offset value of 3FFH (a threshold
1023 words from the empty boundary), a default PAF offset
value of 3FFH (a threshold 1023 words form the full boundary), and serial loading of other offset values.
The act of writing offsets (in parallel or serial) employs a
dedicated write offset register pointer. The act of reading
offsets employs a dedicated read offset register pointer. The
WCLK
S
X
S
S
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSS)
Full Offset ~LSSd
Full Offset MS )
X
0
1
1
0
0
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
X
S
0
0
Parallel write to registers:
Empty Offset (LSB)
Em ty Offset (MSB)
FullOffset (LSS)
Full Offset (MSS)
X
1
Selection
RCLK
Serial shift into registers:
28 bits for the 72261
30 bits for the 72271
1 bit for each rising WCLK edge
Starting with Empty Offset (LSS)
Ending with Full Offset (MSB)
X
No Operation
X
Write Memory
S
Read Memory
X
No Operation
NOTES:
1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.
3097tbl01
2. The programming method can only be selected at Master Reset.
3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
4. The programming sequence applies to both lOT Standard and FWFT modes.
Figure 2. Partial Flag Programming Sequence
5.02
9
II
IDT72261172271 SyncFIFOTM
16,384 x 9,32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
two pointers operate independently; however, a read and a
write should not be performed simultaneously to the offset
registers. A Master Reset initializes both pointers to the
Empty Offset (LSB) register. A Partial Reset has no effect on
the position of these pointers.
Once serial offset loading has been selected, then programming PAE and PAF procedes as follows: When LD and
SEN are set LOW, data on the SI input are written, one bit for
each WCLK rising edge, starting with the Empty Offset LSB (8
bits for both the 72261 and 72271), then the Empty Offset
MSB (6 bits forthe 72261,7 bits forthe 72271) , then the Full
Offset LSB (8 bits for both the 72261 and 72271), ending with
the Full Offset MSB (6 bits forthe 72261,7 bits forthe 72271).
A total of 28 bits are necessary to program the 72261; a total
of 30 bits are necessary to program the 72271. Individual
registers cannot be loaded serially; rather, all four must be
programmed in sequence, no padding allowed. PAEand PAF
can show a valid status only after the the full set of bits have
been entered. The registers can be re-programmed, as long
as all four offsets are loaded. When LD is LOW and SEN is
HIGH, no serial write to the registers can occur.
Once parallel offset loading has been selected, then
programming PAE and PAF procedes as follows: When LD
and WEN are set LOW, data on the inputs On are written into
the LSB Empty Offset Register on the first LOW-to-HIGH
transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, data at the inputs are written into the MSB
Empty Offset Register. Upon the third LOW-to-HIGH transition of WCLK, data at the inputs are written into the LSB Full
Offset Register. Upon the fourth LOW-to-HIGH transition of
WCLK, data at the inputs are written into the MSB Full Offset
Register. The fifth transition of WCLK writes, once again, to
the LSB Empty Offset Register.
To ensure proper programming (serial or parallel) of the
offset registers, no read operation is permitted from the time
of reset (master or partial) to the time of programming. (During
this period, the read pointer must be pointing to the first
location of the memory array.) After the programming has
been accomplished, read operations may begin.
Write operations to memory are allowed before and during
the parallel programming sequence. In this case, the programming of all offset registers does not have to occur at one
time. One or two offset registers can be written to and then,
by bringing LD HIGH, write operations can be redirected to the
FIFO memory. When LD is set LOW again, and WEN is LOW,
the next offset register in sequence is written to. As an
altemative to holding WEN LOW and toggling LD, parallel
programming can also be interrupted by setting LD LOW and
toggling WEN.
Write operations to memory are allowed before and during
the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing LD and SEN HIGH, data can be written to FIFO
memory via On by toggling WEN. When WEN is brought HIGH
with LD and SEN restored to a LOW, the next offset bit in
sequence is written to the registers via SI. If a mere interuption
of serial programming is desired, it is sufficient eitherto set LD
LOW and deactivate SEN or to set SEN LOW and deactivate
LD. Once LD and SEN are both restored to a LOW level, serial
offset programming continues from where it left off.
Note that the status of a partial flag (PAE or PAF) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset words have been written
to the LSB and MSB registers pertaining to that flag. From the
time serial programming has begun, neither partial flag will be
valid until the full set of bits requiredto fill all the offset registers
has been written. Measuring from the rising WCLK edge that
achieves eitherof the above criteria; PAFwili be valid aftertwo
more rising WCLK edges plus tPAF, PAE will will be valid after
the next two rising RCLK edges plus tPAE (Add one more
RCLK cycle if tSKEW2 is not met.)
The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset
registers can be read on the output lines when LD is set LOW
and REN is set LOW; then, data are read via On from the LSB
Empty Offset Register on the first LOW-to-HIGH transition of
RCLK. Upon the second LOW-to-HIGH transition of RCLK,
data are read from the MSB Empty Offset Register. Upon the
third LOW-to-H IGH transition of RCLK, data are read from the
LSB Full Offset Register. Upon the fourth LOW-to-HIGH
transition of RCLK, data are read from the MSB Full Offset
Register. The fifth transition of RCLK reads, once again, from
the LSB Empty Offset Register.
It is permissable to interrupt the the offset register access
sequence with reads or writes to memory. The interruption
is accomplished by deasserting REN, LD, or both together.
When REN and LD are restored to a LOW level, access of the
registers continues where it left off.
LD functions the same way in both lOT Standard and
FWFT modes.
FREQUENCY SELECT INPUT (FS)
An internal state machine manages the movement of data
through the Supersync FIFO. The FS line determines whether
RCLK or WCLK will synchronize the state machine. Tie FS to
Vee if the RCLK line is running at a lower frequency than the
WCLK line. In this case, the state machine will be synchronized to WCLK. Tie FS to GND if the RCLK line is running at
a higher frequency than the WCLK line. In this case, the state
machine will be synchronized to RCLK. Note that FS must be
set so the clock line running at the higher frequency drives the
state machine; this ensures efficient handling of the data
within the FIFO. If the same clock signal drives both the
WCLK and the RCLK pins, then tie FS to GND.
The frequency of the clock tied to the state machine
(referred to as the "selected clock") may be changed at any
time, so long as it is always greater than or equal to the
frequency of the clock that is not tied to the state machine
(referred to as the "non-selected clock"). The frequency of
the non-selected clock can also be varied with time, so long
as it never exceeds the frequency of the selected clock. To
be more specific, the frequencies of both RCLK and WCLK
may be varied during FIFO operation, provided that, at any
given point in time, the cycle period of the selected clock is
5.02
10
IDT72261n2271 SyncFIFOTM
16,384 X 9,32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The iR status not only measures the contents of the FIFO
memory, but also counts the presence of a word in the out.put
register. Thus, in FWFT mode, the total number of writes
necessary to deassert IR is one greater than needed to assert
FF in lOT Standard mode.
equal to or less than the cycle period of the non-selected
clock.
The selected clock must be continuous. It is, however,
permissible to stop the non-selected clock. Note, so long as
RCLK is idle, EF/OR and PAE will not be updated. Likewise,
as long as WCLK is idle, FF/iR and PAF will not be updated.
Changing the FS setting during FIFO operation (Le. reading or writing) is not permitted; however, such a change at the
time of Master Reset or Partial Reset is all right. FS is an
asynchronous input.
FF/iRis synchronized to WCLK. It is double-registered to
enhance metastable immunity.
EMPTY FLAG (EF/QR)
This is a dual purpose pin. In the lOT Standard Mode, the
Empty Flag (EF) function is selected. When the FIFO is empty
(i.e. the read pointer catches up to the write pointe.!h EF will go
LOW, inhibiting further read operations. When EF is HIGH,
the FIFO is not empty.
When writing the first word to an empty FIFO, the deassertion
time of EF is variable, and can be represent by the First Word
Latency parameter, tFWL 1, which is measured from the rising
WCLK edge that writes the first word to the rising RCLK edge
that updates the flag. tFWL 1 includes any delays due to clock
skew and can be expressed as follows: .
OUTPUTS:
FULL FLAG (FF/IR)
This is a dual purpose pin. In lOT Standard Mode, the Full
Flag (FF) function is selected. When the FIF~is full (Le. the
write pointer catches up to the read pointer), FFwill go LOW,
inhibiting further write operation. When FF is HIGH, the FIFO
is not full. If no reads are performed after a reset (either MRS
or PRS), FFwili go LOW after 16,384 writes torthe IOT72261
and 32,768 writes to the 10T72271.
In FWFT Mode, the Input Ready (iR) function is selected. iR
goes LOW when memory space is available for writing in
data. When there is no longer any free space left, IR goes
HIGH, inhibiting further write operati~. I~o reads are
performed after a reset (either MRS or PRS), IR will go HIGH
after 16,385 writes forthe 10T72261 and 32,769 writes forthe
IOT72271.
tFWL1 max. = 10*Tf + 2*TRCLK (in ns)
where Tf is either the RCLK or the WCLK period, whichever
is shorter and TRCLK is the RCLK period. Since no read can
take plac~ until EF goes HIGH, the tFWL1 delay determines
how early the first word can be available at an. This delay has
no effect on the reading of subsequent words.
72261 -16,384 x 9-BIT
8
o
7
8
7
72271 - 32,768 x 9-BIT
EMPTY OFFSET (LSB) REG.
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
~
8
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
0
5
EMPTY OFFSET (MSB) REG.
I
OOH
0
7
8
~
8
0
6
EMPTY OFFSET (MSB) REG.
OOH
0
7
FULL OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
..Qj:FAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
~
0
5
o
FULL OFFSET (MSB) REG.
OOH
3036 drw 05
8
0
6
I~
FULL OFFSET (MSB) REG.
OOH
3036 drw 06
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
5.02
11
II
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
In FWFT Mode, the Ouput Ready (OR) function is selected.
OR goes LOW at the same time that the first word written to an
empty FIFO appears valid on the outputs. ORgoes HIGH one
cycle after RCLK shifts the last word from the FIFO memory
to the outputs. Then further data reads are inhibited until OR
goes LOW again.
When writing the first word to an empty FIFO, the assertion
time of OR is variable, and can be represented by the First
Word Latency parameter, tFWL2, which is measured from the
rising WCLK edge that writes the first word to the rising RCLK
edge that updates the flag. tFWL2 includes any delay due to
clock skew and can be expressed as follows:
tFWL2 max. = 10*Tf + 3*TRCLK (in ns)
shorter, and TRCLK is the RCLK period. Note that the First
Word Latency in FWFT mode is one RCLK cycle longer than
in lOT Standard mode. The tFWL2 delay determines how early
the first word can be available at an. This delay has no effect
on the reading of subsequent words.
EF/OR is sychronized to the RCLK. It is double-registered
to enhance metastable immunity.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW
when the FIFO reaches the Almost-Full condition as specified
by the offset m stored in the Full Offset register.
At the time of Master Reset, depending on the state of LO,
one of two possible default offset values are chosen. If LO is
where Tf is either the RCLK orthe WCLK period, whichever is
TABLE 1- STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO Memory
72261
72271
0
0
(1)
FF
H
J5AF
H
HF
H
J5AE
L
EF
L
1 to n(2)
1 to n(2)
H
H
H
L
H
(n+1) to 8,192
(n+ 1) t016,384
H
H
H
H
H
8,193 to (16,384-(m+1))
16,385 to (32, 768-(m+ 1))
H
H
L
H
H
(16,384-m) (3)to 16,383
(32,768-m)(3)fo 32,767
H
L
L
H
H
16,384
32,768
L
L
L
H
H
3097tbl03
NOTES:
1. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
TABLE 11- STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO Memory
(I)
72261
72271
iR
J5AF
RF
PAE
0
0
L
H
H
L
H(4)
L
H
H
L
L
1 to n(2)
1 to n(2)
OR
(n+1) to 8,192
(n+1) t016,384
L
H
H
H
L
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+ 1))
L
H
L
H
L
(32,768-m)(3) to 32,767
L
L
L
H
L
L
H
L
(16,384-m)(3) to 16,383
16,384
32,768
H
L
3097 tbl 04
NOTES:
1. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
4. Following a reset (Master or Partial), the FIFO memory is empty and OR = HIGH. After writing the first word, the FIFO memory remains empty, the data
is placed into the output register, and OR goes LOW. In this case, or any time the last word in the FIFO memory has been read into the output register;
a rising RCLK edge, enabled by REN, will set OR HIGH.
5.02
12
IDT72261n2271 SyncFIFOTM
16,384 x 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW, then m = 07FH and the PAF switching threshold is 127
words from the Full boundary, if LD is HIGH, then m = 3FFH
and the PAF switching threshold is 1023 words away from the
Full boundary.
Any integral value of m from 0 to the maximum FIFO depth
minus 1 (16,383 words for the 72261,32,767 words for the
72271) can be programmed into the Full Offset register.
In IDT Standard Mode, if no reads are performed after reset
(MRSor PRS), PAFwill go LOW after (16,384-m) writes to the
IDT72261, and (32,768-m) writes to the IDT72271.
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), PAF will go LOW after (16,385-m) writes to the
IDT72261, and (32,769-m) writes to the IDT72271. In this
case, the first word written to an empty FIFO does not stay in
memory, but goes unrequested to the output register; therefore, it has no effect on determining the state of PAF.
Note that even though PAF is programmed to switch LOW
during the first word latency period (tFWL), attempts to read
data will be ignored until EF goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAF is synchronous and updated on the rising edge of
WCLK. It is double-registered to enhance metastable immunity.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty Flag (PAE) will go LOW
when the FIFO reaches the Almost-Empty condition as specified by the offset n stored in the Empty Offset register.
At the time of Master Reset, depending on the state of LD,
one of two possible default offset values are chosen. If LD is
LOW, then n = 07FH and the PAEswitching threshold is 127
words from the Empty boundary, if LD is HIGH, then n =3FFH
and the PAE switching threshold is 1023 words away from the
Empty boundary.
Any integral value of n from 0 to the maximum FIFO depth
minus 1 (16,383 words for the 72261, 32,767 words for the
72271) can be programmed into the Empty Offset register.
In IDT Standard Mode, if no reads are performed afterreset
(MRS or PRS), PAE will go HIGH after (n + 1) writes to the
IDT72261n2271.
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), PAE will go HIGH after (n+2) writes to the IDT722611
72271. In this case, the first word written to an empty FIFO
does not stay in memory, but goes unrequested to the output
register; therefore, it has no effect on determining the state of
PAE.
Note that even though PAE is programmed to switch HIGH
during the first word latency period (tFWL), attempts to read
data will be ignored until EF goes HIGH indicating that data is
available atthe output port. This is true for both timing modes.
PAE is synchronous and updated on the rising edge of
RCLK. It is double-registered to enhance metastable immunity.
HALF-FULL FLAG (HF)
This output indicates a half-full memory. The rising WCLK
edge that fills the memory beyond half-full sets HF LOW. The
flag remains LOW until the difference between the write and
read pointers becomes less than or equal to one half of the
total depth of the device, the rising RCLK edge that accomplishes this condition also sets HF HIGH.
In IDT Standard Mode, if no reads are performed after reset
(MRSor PRS), HFwill go LOW after (D/2 + 1) writes, where D
is the maximum FIFO depth ( 16,384 words forthe IDT72261,
32,768 words for the IDT72271).
In FWFT Mode, if no reads are performed after reset (MRS
or PRS) , HF will go LOW after (D/2+2) writes to the IDT722611
72271. In this case, the first word written to an empty FIFO
does not stay in memory, but goes unrequested to the output
register; therefore, it has no effect on determining the state of
HF.
Because HF uses both RCLK and WCLK for synchronization purposes, it is asynchronous.
DATA OUTPUTS (QO-Q8)
00-08 are data outputs for 9-bit wide data.
5.02
13
II
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~-----------tRS------------*
1 4 - - - - - - - tRSS --------.,....1 - - - - tRSR-----~
i + - - - - - - - tRSS ---------.,~r----- tRSR-----~
~---- tRSR-----~
FWFT/SI
tRSS
LD
II
------~~r__---tRSR-----~
)
tRSS
RT
tRSS
SEN
tRSF
If FWFT = HIGH, OR = HIGH
EF/OR
If FWFT = LOW, EF = LOW
tRSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, TR= LOW
FF/iR
tRSF
PAE
~--------tRSF---------'~
I ..
00
-as
tRSF--------t
(1)
-----------------------------
OE = HIGH
-------------------------~
- - - - - - - - - - - - - - OE=LOW
3036drw 07
Figure 4. Master Reset Timing
5.02
14
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
......
tAS
~~
J ~
I
1
tAss
tASA
tASS
tASA
.J.
~
XX; ~
L
J
XX.; KX*
1
tRSS
1
~
•
•
tASF
tRSF
FF/iR
...
tASF
tASF
{
....
tASS
-*
J
--"
I
If FWFT =HIGH. OR =HIGH
**
.1
If FWFT - LOW.
EF -
If FWFT =LOW.
FF =HIGH
LOW
II
If FWFT - HIGH. iR- LOW
J
~
I
I
~
...
tASF
i---------
(1)
OE= HIGH
00 -08
- - - - - - - - - - - - - - - -...... -
-
-
-
-
-
-
-OE
-------
=LOW
-
-
-
-
--;Q3-;:;rw-;
Figure 5. Partial Reset Timing
5.02
15
IDT72261n2271 SyncFIFOTM
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tClK - - - - - - . . l
WCLK_ _ ___
NO OPERATION
tWFF--~
twFF--~
RCLK
REN
3036 drw 09
/
------'
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus twFF).
If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra WCLK
cycle.
2. LD = HIGH
Figure 6. Write Cycle Timing (lOT Standard Mode)
5.02
16
lon2261n2271 SyncFIFOTM
16,384 X 9,32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~------------tCLK------------~
- - tCLKH
tCLKL
RCLK
tENS tENH
NO OPERATION
tREF
------1~
. - - tREF
Qo-em ------------4----IJ
WCLK
-/
\
-/
\t_tE_N_S_-+_ _
Do - [)j
3036 drw 10
NOTES:
1. tFWll contributes a variable delay to the overall first word latency (this parameter includes delays due to skew):
tFWl1 max. (in ns) = 10*Tf + 2* TRClK
where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRClK is the RCLK period
2. LD = HIGH
Figure 7. Read Cycle Timing (lOT Standard Mode)
5.02
17
IDT72261n2271 SyncFIFOTM
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
14-----tFWL:+l(__
1)_ _....1
EF _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
REN __________________________________________-+__________________+-___________
DO
Qo-~--------------------------_+----~
01
3036drw 11
NOTES:
1. tFWL 1 max. (in ns) = 10* Tf + 2* TRCLK
Where TI is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period
2. LD = HIGH
Figure S. First Data Word Latency (IDT Standard Moda)
5.02
18
10T72261n2271 SyncFIFOTM
16,384 X 9,32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK_ _~
Do - [)j
II
OE LOW
Qo-QI
DATA READ
NEXT DATA READ
3036 drw 12
NOTES:
1. tSKEWl is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus twFF).
If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tsKEW1, then the FF deassertion may be delayed an extra
WCLKcycle.
2. LD =HIGH
Figure 9. Full Flag Timing (lOT Standard Mode)
5.02
19
IDT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
00- 08
tENS~
r;
tENH
RCLK
LOW
00-08
---"?--~
DATA IN OUTPUT REGISTER
WORD 1
3036 drw 13
NOTES:
1. tFWL 1 max. (in ns) =10*Tl + 2*TRCLK
Where Tl is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the period.
2. LD =HIGH
Figure 10. Empty Flag Timing (lOT Standard Mode)
5.02
20
IOT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 11. Serial Loading of Programmable Flag Registers (lOT Standard and FWFT modes)
NOTE:
1. For the 72261, X
For the 72271, X
3036 drw 14
=5.
=6.
Figure 12. Parallel Loading of Programmable Flag Registers (lOT Standard and FWFT modes)
5.02
21
10T72261n2271 SyncFIFOTM
16,384 x 9, 32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RCLK
:1,
X""'P-A--F-O--FF~S""'E"""TA'------tA
DATA IN OUTPUT
REGISTER
00-08
~_~X
PAE OFFSET
PAE OFFSET
(LSB)
(MSB)
(LSB)
PAF OFFSET
(MSB)
3036 drw 16
Figure 13. Parallel Read of Programmable Flag Registers (lOT Standard and FWFT modes)
NOTES:
1. OE= LOW
WCLK
n words
in FIFO
memory
n+1 words in FIFO memory
RCLK
tEN~
(IENH
3036drw 17
NOTES:
1. PAE offset n
2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
3. tSKEW2 is the minimum time between a rising WCLKedge and a rising RCLK edge for PAEto go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
=
Figure 14. Programmable Almost Empty Flag Timing (lOT Standard and FWFT modes)
5.02
22
IDT72261n2271 SyncFIFOTM
16,384 X 9,32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
PAF ________________________________________
~
D - m words in
FIFO memory
(1,2)
D-(m+1)
Words in
FIFO
D - (m+1) words in
FIFO memory
RCLK
REN ----------------------------------------~~
3036d/W 18
NOTES:
1. PAFoffset= m. D = 16,384 for IDT72261. 32,768 words for IDT72271.
2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary). it is not included in the FIFO memory count.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLKedge for PAFto go HIGH (after one WCLKcycie plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2. then the PAF deassertion time may be delayed an extra WCLK cycle.
Figure 15. Programmable Almost Full Flag Timing (lOT Standard and FWFT modes)
WCLK
tHF~
D/2 words
=J
D/2 + 1 words
D/2 words
tHF
RCLK
3036 drw 19
NOTES:
1. D = maximum FIFO depth = 16,384 for IDT72261. 32.768 words for IDT72271.
Figure 16. Half - Full Flag Timing (lOT Standard and FWFT modes)
5.02
23
II
I0T72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
Do - [)}
RCLK
00 -CB
tREF.
tHF
j=f)
3036 drw20
NOTES:
1. tRTF1 contributes a variable delay to the overall retransmit recovery time:
tRFTF1 max = 14*Tf + 3*TRCLK (in ns)
Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. Retransmit Setup is complete after EFreturns HIGH, only then can a read operation begin. Write operations are permitted after one of two conditions have
been met: EF is HIGH or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the RT pulse.
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of HF, PAE, and PAF.
4. No more than D - 2 words (D = 16,384 words for the 72261, 32,768 words for the 72271) should have been written to the FIFO between Reset (Master
or Partial) and Retransmit Setup. Therefore, FF will be HIGH throughout the Retransmit Setup procedure.
5. OE= LOW
Figure 17. Retransmit Timing (lOT Standard mode)
5.02
24
Q;8
w:::j
CDN
""N
>< en
~:5
~n~
~j
CDCII
><'<
WCLK
105"TI
:;;
~
WEN
Do - Os
RCLK
REN
Qo- Os
OR
en
0
N
,tPAE
PAE
FiF
s:
r=
~
:0
PAF
-<
____________________________________________________________________________________________________________________________~_t_W_F~
iR
3036 !l"w 21
NOTES:
1. tFWl2 max. (in ns) = 10*TI + 3*TRCLK
where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH (after one RCLK cycle plus IPAE). If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD HIGH, OE LOW
4. PAE offset n, PAF offset m, D maximum FIFO depth 16,384 words for the IDT 72261,32,768 words for the IDT72271
=
=
=
=
=
=
z~
c
o
o
s:
s:m
:0
o
~
r
-I
m
s:
"m
:0
~
c:
m
:0
Figure 18. Write Timing (First Word Fall Through Mode)
:0
~
Z
N
en
G)
m
CII
II
..AS
~::j
CD I\)
~
WCLK
))
~I\)
><::2
IOn
"TI
Do - Ds
~
RCLK
REN
OE
00- Os
OR
en
b
I\)
m
RF
b:~F
m
6
iR
~eAF
3:
r=
=i
lo
:c
-<
lo
Z
C
(1
3036drw 22
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that iR will go LOW (after one WCLK cycle plus twFF). If the time between the rising ege of RCLK
and the rising edge of WCLK is less than tSKEW1, then the iR assertion may be delayed an extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of RCLK and the rising
edge of WCLK is less than tSKEW2, then the PAF deassertion may be delayed an extra WCLK cycle.
3. LD = HIGH
4. PAE offset n, PAF offset m, D maximum FIFO depth = 16,384 words for the IDT 72261,32,768 words for the IDT72271
=
=
=
Figure 19. Read Timing (First Word Fall Through Mode)
o
3:
3:
m
:c
(1
:;
I
-I
m
3:
"tI
m
:c
:.
c:
:c
m
:c
lo
I\)
aI
z
"m
Vl
IDTI2261172271 SyncFIFOTM
16.384 X 9. 32.768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
Do - OJ
RCLK
00 -Os
II
tHF
tPAF
TR(4)
---------------------------------------------------------------------------------------------
NOTES:
3036 drw 23
1. tRTF2 contribute a variable delay to the overall retransmit time:
tRTF2 max = 14*Tf + 4*TRCLK (in ns)
Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. Retransmit Setup is complete after OR returns LOW, only then can a read operation begin. Write operations are permitted after one of two conditions
have been met: OR is LOW or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enable~ the RT pulse.
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of HF, PAE, and PAF.
4. No more than D - 2 words (D = 16,384 words for the 72261, 32,768 words for the 72271) should have been written to the FIFO between Reset (Master
or Partial) and Retransmit Setup. Therefore, iR will be LOW throughout the Retransmit Setup procedure.
5. OE= LOW
Figure 20. Retransmit Timing (FWFT mode)
5.02
27
IDT72261n2271 SyncFIFOTM
16,384 x 9,32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
tion requirements are for 16,384/32,768 words or less. The
IDT72261n2271 can always be used in Single Device Configuration, whether IDT Standard Mode or FWFT Mode has
SINGLE DEVICE CONFIGURATION
A single IDT72261/722171 may be used when the applica- been selected. No special set up procedure is necessary.
PARTIAL RESET (PRS)
MASTER RESET (MRS)
~
WRITE CLOCK (WCLK)
+
LOAD (LD)
READ CLOCK (RCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
..
DATA OUT (Qo - Q8)
DATA IN (Do - 081
lOT
-"'
SERIAL ENABLE(SEN)
72261/
72271
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST EMPTY (PAE)
FULL FLAG/INPUT READY (FF/iR)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST FULL (PAF)
t
FREQUENCY SELECT (FS)
3036 drw 24
Figure 21. Block Diagram of Single 16,384x9/32,768x9 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting togetherthe control signals of multiple devices. Status flags can
be detected from anyone device. The exceptions are the EF
and FF functions in IDT Standard mode and the fA and OR
functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion
and 'fRIOR assertion to vary by one cycle between FIFOs. In
IDT Standard mode, such problems can be avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and
separately ORing IR of every FIFO. Figure 22 demonstrates
an 18-word width by using two IDT72261n2271s. Any word
width can be attained by adding additiona11DT7226172271 s.
5.02
28
1DT72261n2271 SyncFIFOTM
16,384 X 9, 32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PARTIAL RESET (PAS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (R'i)
DATA IN (Dn)
1
/
WRITE CLOCK (WCLK)
.----.
GAT~111
(FFiiR) #1
FULL FLAG/INPUT READY
(FF/iR) #2
72261/
72271/
-
-
PROGRAMMABLE (PAF)
#1
HALF FULL FLAG (HF)
OUTPUT ENABLE (DE)
lOT
IDT
72261/
722711
~
READ ENABLE (REN)
-
-
LOAD (ill)
READ CLOCK (RCLK)
-
-
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY
1
~
J
/181/ 9
/
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY
(EFtOR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
/9
#2
DATA OUT (Qn)
7
~
]GAT~11
/18
rl
FREQUENCY SELECT (FS)
3036 drw 25
NOTE:
1. Use an AND gate in lOT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
II
Figure 22. Block Diagram of 16,384x18/32,768x18 72261n1 Width Expansion
DEPTH EXPANSION CONFIGURATION
The IDT72261 172271 can easily be adapted to applications
requiring more than 16,384/32,768 words of buffering. In
FWFT mode, the FIFOs can be arranged in series (the data
outputs of one FI FO connected to the data inputs of the next)no external logic necessary. The resulting configuration
provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 23 shows a depth
expansion using two IDT72261172271s.
Care should be taken to select FWFT mode during Master
Reset for all FIFOs in the depth expansion configuration. The
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the
outputs of the last FIFO in the chain-no read operation is
necessary. Each time the data word appears at the outputs
of one FIFO, that device's OR line goes LOW, enabling a write
to the next FIFO in line.
The OR assertion time is variable and is described with the
help of the tFWl2 parameter, which includes including delay
caused by clock skew:
tFWl2 max.= 1O*Tf + 3*TRCLK
TRANSFER CLOCK
WRITE CLOCK
WCLK
RCLK
--I
WCLK
WRITE ENABLE
RCLK
WEN
OR
REN
READ CLOCK
READ ENABLE
WEN
INPUT READY
722611
72271
TR
REN
722611
72271
OUTPUT READY
OR
TR
OUTPUT ENABLE
OE
DATA BUSJ 9
I
Dn
J 9
an
FS
OE
GND
I
.
D':lAOUT
an
Dn
FS
I
I
/9
..
~
3036 dlW 26
Figure 23. Block Diagram of 32,768x9/65,536x9 Synchronous FIFO Memory
With Programmable Flags used in Depth Expansion Configuration
5.02
/
29
IDT72261n2271 SyncFIFOTM
16,384 x 9,32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's TR line goes LOW, enabling the preceding
FIFO to write a word to fill it.
The amount oftime ittakes for TRofthe first FIFO in the chain
to assert after a word is read from the last FIFO is the sum of
the delays for each individual FIFO:
where TRCLK is the RCLK period and Tf is either the RCLK or
the WCLK period, whichever is shorter.
The maximum amount of time it takes for a word to pass
from the inputs of the first FIFO to the outputs of the last FIFO
in the chain is the sum of the delays for each individual FIFO:
tFWL2(1) + tFWL2(2) + ... + tFWL2(N)+ N*TRCLK
N*(3*TwCLK)
where N is the number of FIFOs in the expansion.
Note that the additional RCLK term accounts for the time it
takes to pass data between FIFOs.
The ripple down delay is only noticeable for the first word
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.
The first free location created by reading from a full depth
expansion configuration will "bubble up" from the last FIFO to
the previous one until it finally moves into the first FIFO of the
where N is the number of FIFOs in the expansion and TWCLK
is the WCLK period. Note that one of the three WCLK cycle
accounts for TSKEW1 delays.
In a Supersync depth expansion, set FS individually for
each FIFO in the chain. The Transfer Clock line should be tied
to either WCLK or RCLK, whichever is faster. Both these
actions result in moving, as quickly as possible, data to the
end of the chain and free locations to the beginning of the
chain.
ORDERING INFORMATION
lOT
XXXXX
x
XX
Device Type
Power
Speed
X
Package
x
Process I
Temperature
Range
y~LANK
L -_ _ _ _ _- - l1
~F
Pin Grid Array (PGA)
Thin Plastic Quad Flatpack
Slim Thin Quad Flatpack
I TF
10
12
'---------------115
20
25
Com'l Only
Com'l OnlX
Com'I&MII.
Com'l Only
Mil. Only
--I: L
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I
5.02
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
72261
72271
}
Clock Cycle Time (tCLK)
.
Speed In Nanoseconds
Low Power
16,384 x 9 Synchronous FIFO
32,768 x 9 Synchronous FIFO
3036 drw 27
30
G®
PRELIMINARY
IDT72255
IDT72265
CMOS SUPERSYNC FIFOTM
8,192 x 18,16,384 x 18
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
The I0T72255172265 are monolithic, CMOS, high capacity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs are
applicable for a wide variety of data buffering needs, such as
optical disk controllers, local area networks (lANs), and interprocessor communication.
Both FI FOs have an 18-bit input port (On) and an 18-bit
output port (Qn). The input port is controlled by a free-running
clock (WCll<) and a data input enable pin (WEN). Data is
written into the synchronous FIFO on every clock when WEN
is asserted. The output port is controlled by another clock pin
(RClK) and enable pin (REN). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output
enable pin (OE) is provided on the read port for three-state
control of the outputs.
The I0T72255172265 have two modes of operation: In the
lOT Standard Mode, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the First Word Fall Through Mode
•
•
•
•
•
•
•
•
•
8,192 X 18-bit storage capacity (lOT72255)
16,384 x 18-bit storage capacity (IDT72265)
10ns read/write cycle time (8ns access time)
Retransmit Capability
Auto power down reduces power consumption
Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
Empty, Full and Half-full flags signal FIFO status
Programmable Almost Empty and Almost Full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select lOT Standard timing (using EF and FF f~s) or
First Word Fall Through timing (using OR and IR flags)
Easily expandable in depth and width
Independent read and write clocks (permit simultaneous
reading and writing with one clock signal)
Available in the 64-pin Thin Quad Flat Pack (TQFP), 64pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
Output enable puts data outputs into high impedance
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
Do-D17
:~
EF/OR
EAr
HF
FWFT/SI
3037 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc
MAY 1995
DSC-206215
5.03
I
II
IDT722ssn226S SyncFIFOTM
8,192 x 18,16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(FWFT) , the first word written to an empty FIFO appears
automatically on the outputs, no read operation required. The
state of the FWFT/SI pin during Master Reset determines the
mode in use.
The I DT72255/72265 FI FOs have five flag functions, EFt
OR (Empty Flag or Output Ready), FFijR (Full Flag or Input
Ready), and HF (Half-full Flag). The EF and FFfunctions are
selected in the IDT Standard Mode.
The I Rand OR functions are selected in the First Word Fall
Through Mode. IR indicates that the FIFO has free space to
receive data. OR indicates that data contained in the FIFO is
available for reading.
HF is a flag whose threshold is fixed at the half-way point in
memory. This flag can always be used irrespective of mode.
PAE, PAF can be programmed independantly to any point
in memory. They, also, can be used irrespective of mode.
Programmable offsets determine the flag threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, such that PAE can be set at
127 or 1023 locations from the empty boundary and the PAF
threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with LD during Master
Reset.
In the serial method, SEN together with LD are used to load
the offset registers via the Serial Input (SI). In the parallel
method, WEN together with LD can be used to load the offset
registers via Dn. REN together with LD can be used to read the
offsets in parallel from an regardless of whether serial or
parallel offset loading is selected.
During Master Reset (MRS), the read and write pointers are
setto the first location ofthe FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The LD pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.
The Partial Reset (PRS) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly. PRS is
PIN CONFIGURATIONS
r- r- r- r- r-
I'"
r- r- r- r-
I'"
I'"
I'"
r- r- r-
1-1- f-I- f-I- f- I-f- f-f- f-I- f- f-fI-f- f-I- f-I- f- I-f- f-I- 1-1- f- 1-1-
PIN 1
/
WEN I
SEN I
FS I
I I
I
I
I I
I I
I
I I
Vee
GNO
017
016
015
014
013
012
011
010
09
08
07
I I
I I
I
I
I I
I
I I
I
I I
I
I
I I
I I
I
I I
I
I I
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PN64-1
PP64-1
I I
I I
I 017
I 016
Ll
J GNO
I I
I 015
44
lJ
J 014
43
42
41
40
39
38
37
36
35
I I
I Vee
I I
I I
I 013
I 012
lJ
J 011
I I
I I
I GNO
I 010
I I
I 09
Ll
Jl
J 08
J 07
34
I I
33
I I
I 06
J GNO
17 18 1920 21 22 23 2425 2627 28 29 30 31 32
f- lI- l-
I- 1-1-1- I- ~ 1-1- 1-1I- 1-1-1- l- I- 1-1- 1-1-
....
'- '-
'-
........ ....
'-
'-
.... ........
-
l-
~
I-
-
....
3037 drw02
TQFP
STQFP
TOP VIEW
5.03
2
IDT72255n2265 SyncFIFOTM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8,192 x 18,16,384 x 18
useful for resetting a device in mid-operation, when reprogramming offset registers may not be convenient.
The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when RT is LOW. This feature is convenient for
sending the same data more than once.
If, at anytime, the FIFO is not actively performing a function,
the chip will automatically power down. This occurs if neither
a read nor a write occurs within 10 cycles of the faster clock,
RCLK orWCLK. During the Power Down state, supply current
consumption (lCC2) is at a minimum. Initiating any operation
(by activating control inputs) will immediately take the device
out of the Power Down state.
The IDT72255172265 are depth expandable. The addition
of external components is unnecessary. The iR and OR
functions, together with REN and WEN, are used to extend the
total FIFO memory capacity.
The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency
The IDT72255172265 is fabricated using IDT's high speed
submicron CMOS technology.
PIN CONFIGURATIONS (CO NT.)
11
ONC
05
VCC
02
01
GNO
01
03
05
04
03
GNO
00
Do
02
04
06
07
10
06
GNO
09
08
07
09
08
08
010
09
011
010
07
011
GNO
013
012
06
013 012
05
014
Vee
04
GNO
015
03
017 016
G68-1
015 014
017 016
l i n 1 Designator
Vec GNO
SEN FS
•
ONC OE REN GNO PAE HF FFI
IR ONC LO WCLK WEN
EFI Vce PAF GNO FWFTI
MRS PRS
RT RCLK OR
01
Sl
02
A
B
C
o
E
F
G
H
J
K
L
3037 drw03
PGA
TOP VIEW
NOTES:
1. DNC
=Do not connect
5.03
3
IDT72255n2265 SyncFIFOTM
8,192 x 18,16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
I/O
Symbol
Name
Do-D17
Data Inputs
I
Data inputs for a 18-bit bus.
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
Partial Reset
I
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT
Retransmit
I
Allows data to be resent starting with the first location of FIFO memory.
FWFT/SI
First Word Fall
Through/Serial In
I
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
WCLK
Write Clock
I
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers.
WEN
Write Enable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN enables RCLK for reading data from the FI FO memory and offset registers.
Description
REN
Read Enable
I
OE
Output Enable
I
OE controls the output impedance of On
SEN
Serial Enable
I
SEN enables serial loading of programmable flag offsets
LD
Load
I
During Master Reset, LD selects one of two partial flag default offsets (127 and
1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.
FS
Frequency Select
I
The FS setting optimizes data flow through the FIFO.
FFIIR
Full Flag!
Input Ready
0
In the IDT Standard Mode, the FF function is selecte~ FF indicates whether.Q!
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
EF/OR
Empty Flag/
Output Ready
0
In the IDT Standard Mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
PAF
Programmable
Almost Full Flag
0
PAF goes HIGH if the number of free locations in the FIFO memory is more than
offset m which is store in Almost Full which is stored in the Full Offset register. PAF
goes LOW if the number of free locations in the FIFO memo_ry is less than m.
PAE
Programmable
Almost Empty
Flag
0
PAE goes LOW if the number of words in the FIFO memory is less than offset n
which is stored in theEmpty Offset register. PAE goes HIGH if the number of
words in the FIFO memory is greater than offset n.
0
0
HF indicates whether the FIFO memory is more or less than half-full.
HF
Half-fu" Flag
00-017
Data Outputs
Vee
Power
+5 volt power supply pins.
GND
Ground
Ground pins.
Data outputs for a 18-bit bus.
3037tbl01
5.03
4
IDT72255n2265 SyncFIFOTM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8,192 x 18, 16,384 x 18
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Commercial
Terminal Voltage
-0.5 to +7.0
with respect to GND
TA
Operating
Temperature
TBIAS
Mlilitary
Unit
-0.5 to +7.0
V
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
VCCM
o to +70
Parameter
Military Supply
Voltage
Commercial Supply
Voltage
-55 to +125
°C
Temperature Under -55 to +125
Bias
-65 to +135
°C
GND
Supply Voltage
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
VIH
lOUT
DC Output Current
50
50
mA
VIH
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
Vccc
NOTE:
3037tbl02
VIL\l}
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maimum rating conditions for extended periods may
affect reliabilty.
Min.
4.5
Typ.
5.0
Max.
Unit
5.5
V
4.5
5.0
5.5
V
0
0
0
V
2.0
-
-
V
2.2
-
-
V
-
-
0.8
V
NOTE:
3037 tbl 03
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc=5V± 10%, TA=0°Cto+70°C; Military: Vcc=5V± 10%, TA=-55°Cto +125°C)
DT72255L
IDT72265L
Commercial
tCLK = 10, 12,15, 20ns
Symbol
Parameter
Min.
Typ.
Max.
Min.
Input Leakage Current (any input)
-1
Output Leakage Current
-10
-
1
-10
10
-10
-
2.4
-
-
0.4
-
-
180
-
-
15
-
lu(1)
ILO(2)
VOH
VOL
Output Logic "1" Voltage, IOH -2 rnA
Output Logic "0" Voltage, IOL = 8 mA
2.4
ICC1(3)
Active Power Supply Current
=
ICC2(3.4) Power Down Current (Ail inputs
=VCC - 0.2V or
II
IDT72255L
IDT72265L
Military
tCLK = 15, 25ns
Typ.
-
Max.
Unit
10
~
10
0.4
~
V
V
250
mA
25
rnA
-
GND + 0.2V, RCLK and WCLK are free-running)
NOTES:
1. Measurements with 0.4 :s; VIN :s; Vcc.
2. OE= VIH
3. Tested at f = 20 MHz with outputs unloaded.
3037tbl04
4. No data written or read for more than 10 cycles
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(l)
Conditions
Max.
Unit
CIN(2)
Input
Capacitance
VIN = OV
10
pF
COUT(1·2)
Output
Capacitance
VOUT=OV
10
pF
NOTES:
3037tbl05
1. With output deselected, (OE=HIGH).
2. Characterized values, not currently tested.
5.03
5
IDT72255n2265 SyncFIFOTM
8,192
x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: Vcc = 5V ± 10%, TA = O°C to +70°C; Military: Vcc = 5V ± 10%, TA = -55°C to +125°C)
Commercial
72255L10
72265L10
Symbol
fs
Parameter
Clock Cycle Frequency
Com'I&MiI. Commercial
72255L12
72265L12
Min.
Max.
Min.
Max.
-
100
-
83.3
72255L15
72265L15
Min.
Max.
-
66.7
72255L25
72265L25
Min.
Min.
-
tA
Data Access Time
2
8
2
9
2
10
tCLK
Clock Cycle Time
10
-
12
15
Clock HiQh Time
4.5
tCLKL
Clock Low Time
4.5(2)
5
5(2)
3.5
0
-
0
-
8
3.5
-
-
20
tCLKH
-
3.5
-
3.5
-
4
5
-
0
-
1
-
4
-
5
6
6(2)
Military
72255L20
72265L20
2
8
Max.
-
50
12
3
Max.
Unit
40
MHz
15
ns
-
ns
ns
1
-
6
-
ns
-
25
10
10
ns
tos
Data Set-up Time
tOH
Data Hold Time
tENS
Enable Set-up Time
tENH
Enable Hold Time
0
tLOS
Load Set-up Time
3.5
tLOH
Load Hold Time
6.5
-
8.5
-
10
tRS
Reset Pulse Width(3)
10
12
-
15
-
20
tRSS
Reset Set-up Time
10
-
-
12
15
-
20
-
25
tRSR
Reset Recovery Time
10
-
12
-
15
-
20
-
25
-
ns
tRSF
Reset to Flag and Output Time
-
10
-
12
-
15
-
20
-
25
ns
0
-
0
0
-
0
-
ns
3.5
-
0
3.5
5
-
6
-
ns
ns
3.5
4
1
5
1
1
10
6
ns
ns
1
-
ns
6
ns
10
-
25
-
ns
-
ns
ns
tRTS
Retransmit Set-Up Time
tOLZ
Output Enable to Output in Low
0
-
0
-
0
-
0
-
0
-
tOE
Output Enable to Output Valid
3
7
3
7.5
3
8
3
10
3
13
ns
to HZ
Output Enable to Output in High Z(4)
3
7
3
7.5
3
8
3
10
3
13
ns
tWFF
Write Clock to FF or IR
-
8
-
9
-
10
-
12
A
9
-
-.i(l
-
12
8
-
-
12
-
-
10
8
9
9
10
12
16
-
18
-
20
-
-
22
tFWFT
Mode Select Time
tPAF
FF nr OR
Write Clock to PAF
tPAE
Read Clock to PAE
tHF
Clock to HF
tRFF
Z(4)
RMrl c":lnr:k tn
4
15
ns
15
ns
15
ns
15
ns
-
25
ns
tSKEW1
Skew time between RCLK and WCLK
for FF and iR
8
-
10
-
12
-
15
-
20
-
ns
tSKEW2
Skew time between RCLK and
WCLK for PAE and PAF
15
-
18
-
21
-
25
-
35
-
ns
3037 tbl 06
NOTES:
5V
1. All AC timings apply to both Standard IDT Mode and First Word Fall
Through Mode.
2. Forthe RCLK line: tClKl (min.) 7 ns only when reading the offsets from
the programmable flag registers; otherwise, use the table value. Forthe
WCLK line, use the tClKl (min.) value given in the table.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
=
1.1K
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
680n
30pF*
GNDto3.0V
3ns
1.SV
3037 drw04
1.SV
Figure 1. Output Load
See Figure 1
* Includes jig and scope capacitances.
3037 tbl 08
5.03
6
IDT72255n2265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming flag settings may
not be convenient.
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (Do - D17)
Data inputs for 18-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the Master
Reset (MRS) input is taken to a LOW state. This operation sets
the internal read and write pointers to the first location of the
RAM array. PAEwill go LOW, PAFwili go HIGH, and HFwill
go HIGH.
If FWFT is LOW during Master Resetthen the IDT Standard
Mode, along with EF and FF are selected. EFwili go LOW and
FF will go HIGH. If FWFT is HIGH, then the First Word Fall
through Mode (FWFT), along with TR and OR, are selected.
OR will go HIGH and TR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a
threshold 127 words from the empty boundary and PAF is
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a
threshold 1023 words from the empty boundary and PAF is
assigned a threshold 1023 words from the full boundary;
1023 words corresponds to an offset value of 3FFH. Following
Master Reset, serial loading of the offsets is permitted, but not
parallel loading.
Regardless of whether serial or parallel offset loading has
been selected, parallel reading of the registers is always
permitted. (See section describing the LD line for further
details).
During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place. MRS is asynchronous.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the Partial
Reset (PRS) input is taken to a LOW state. As in the case of
the Master Reset, the internal read and write pointers are set
to the first location of the RAM array, PAE goes LOW, PAF
goes HIGH, and HF goes HIGH.
Whichever mode is active at the time of partial reset, IDT
Standard Mode or First Word Fall-through, that mode will
remain selected. If the IDT Standard Mode is active, then FF
will go HIGH and EFwili go LOW. Ifthe First word Fall-through
Mode is active, then OR will go HIGH, and TR will go LOW.
Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes. PRS
is asynchronous.
RETRANSMIT (Rl)
The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.
Retransmit Setup is initiated by holding RT LOW during a
rising RCLK edge. REN and WEN must be HIGH before
bringing RT LOW. At least one word, but no more than Full 2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit Setup
(Full = 8,192 words for the 72255, 16,384 words for the
72265).
If IDT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit Setup by setting EF LOW. The
change in level will only be noticeable if EF was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.
When EF goes HIGH, Retransmit Setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard Mode is selected, every word
read including the first word following Retransmit Setup requires a LOW on REN to enable the riSing edge of RCLK.
Writing operations can begin after one of two conditions have
been met: EF is HIGH or 14 cycles of the faster clock (RCLK
or WCLK) have elapsed since the RCLK rising edge enabled
by the RT pulse.
The deassertion time of EF during Retransmit Setup is
variable. The parameter tRTF1, which is measured from the
rising RCLK edge enabled by RT to the rising edge of EF is
described by the following equation:
tRTF1 max. = 14*Tf + 3*TRCLK (in ns)
where Tf is either the RCLK or the WCLK period, whichever is
shorter, and TRCLK is the RCLK period.
Regarding FF: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, FFwill
remain HIGH throughout the setup procedure.
For IDT Standard mode, updating the PAE, HF, and PAF
flags begins with the "first" REN-enabled rising RCLK edge
following the end of Retransmit Setup (the point at which EF
goes HIGH). This same RCLK rising edge is used to access
the "first" memory location. HF is updated on the first RCLK
rising edge. PAE is updated after two more rising RCLK
edges. PAF is updated after the "first" rising RCLK edge,
followed by the next two rising WCLK edges. (If the tskew2
specification is not met, add one more WCLK cycle.)
If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit Setup by setting OR HIGH. The change in
level will only be noticeable if OR was LOW before setup.
During this period, the internal read pointer is set to the first
location of the RAM array.
5.03
7
II
I
I
IDT72255n2265 SyncFIFOTM
8,192 X 18, 16,384 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
When ORgoes LOW, Retransmit Setup is complete; atthe
same time, the contents of the first location are automatically
displayed on the outputs. Since FWFT Mode is selected, the
first word appears on the outputs, no read request necessary.
Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. Writing operations can begin
after one of two conditions have been met: OR is LOW or 14
cycles of the faster clock (RCLK orWCLK) have elapsed since
the RCLK rising edge enabled by the RT pulse.
The assertion time of OR during Retransmit Setup is
variable. The parameter tRTF2, which is measured from the
rising RCLK edge enabled by RT to the falling edge of OR is
described by the following equation:
tRTF2 max. = 14*Tf + 4*TRCLK (in ns)
where Tf is eitherthe RCLK orthe WCLK period, whichever
is shorter, and TRCLK is the RCLK period. Note that a
Retransmit Setup in FWFT mode requires one more RCLK
cycle than in lOT Standard mode.
Regarding IR: Note that since no more than Full- 2 ~ites
are allowed between a Reset and a Retransmit Setup, IR will
remain LOW throughout the setup procedure.
For FWFT mode, updating the PAE, HF, and PAF flags
begins with the "last" rising edge of RCLK before the end of
Retransmit Setup. This is the same edge that asserts OR and
automatically accesses the first memory location. Note that,
in this case, REN is not required to initiate flag updating. HF
is updated on the "last" RCLK rising edge. PAE is updated
after two more rising RCLK edges. PAF is updated after the
"last" rising RCLK edge, followed by the next two rising WCLK
edges. (If the tskew2 specification is not met, add one more
WCLK cycle.)
RT is synchronized to RCLK. The Retransmit operation is
useful in the event of a transmission error on a network, since
it allows a data packet to be resent.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state
of the FWFT/SI helps determine whether the device will
operate in lOT Standard mode or First Word Fall Through
(FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then lOT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FIFO memory. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO memory has any free
space for writing. In lOT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (REN) line.
If at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there i~alid data at the data
outputs (an). It also uses Input Ready (IR) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to an, no read request necessary. Subsequent words
must be accessed using the Read Enable (REN) line.
After Master Reset, FWFT/SI acts as a serial input for
loading PAEand PAF offsets into the programmable registers.
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
FWFT/SI functions the same way in both lOT Standard and
FWFT modes.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the write clock
(WCLK). Data set-up and hold times must be met with respect
to the LOW-to-HIGH transition of the WCLK. The write and
read clocks can either be asynchronous or coincident.
WRITE ENABLE (WEN)
When Write Enable (WEN) is LOW, data can be loaded into
the input register on the rising edge of every WCLK cycle.
Data is stored in the RAM array sequentially and independently of anyon-going read operation.
When WEN is HIGH, the input register holds the previous
data and no new data is loaded into the FIFO.
To prevent data overflow in the lOT Standard Mode, FF will
go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
_
occur. WEN is ignored when the FIFO is full.
To prevent data overflow in the FWFT mode, IR will go
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle, iR will go LOW allowing a write to occur.
WEN is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs, on the rising edge of the
read clock (RCLK), when Output Enable (OE) isset LOW. The
write and read clocks can be asynchronous or coincident.
READ ENABLE (REN)
When Read Enable (REN) is LOW, data is loaded from the
RAM array into the output register on the rising edge of the
RCLK.
When REN is HIGH, the output register holds the previous
data and no new data is loaded into the output register.
In the lOT Standard Mode, every word accessed at an,
including the first word written to an empty FIFO, must be
requested using REN. When all the data has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH after tFWL1 +tREF
and a read is permitted.
In the FWFT Mode, the first word written to an empty FIFO
automatically goes to the outputs an, no need for any read
request. In order to access all other words, a read must be
executed using REN . When all the data has been read from
the FIFO, Output Ready (OR) will go HIGH, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, OR will go LOW after tFWL2 +tREF.
when the first word appears at an ; if a second word is written
into the FIFO, then REN can be used to read it out.
5.03
8
IDT72255n2265 SyncFIFOTM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8,192 x 18,16,384 x 18
when the first word appears at an ; if a second word is written
into the FIFO, then REN can be used to read it out.
SERIAL ENABLE (SEN)
Serial Enable is (SEN) is an enable used only for serial
programming of the offset registers. The serial programming
method must be selected during Master Reset. SEN is always
used in conjunction with LD. When these lines are both LOW,
data at the SI input can be loaded into the input register one
bit for each LOW-to-HIGH transition of WCLK.
When SEN is HIGH, the programmable registers retains
the previous settings and no offsets are loaded.
SEN functions the same way in both lOT Standard and
FWFTmodes.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel
output buffers receive data from the output register. When OE
is HIGH, the output data bus (an) goes into a high impedance
state.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state
LD
WEN
REN
SEN
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
ofthe Load line (LD) determines one of two defaultvalues (127
or 1023) for the PAE and PAF flags, along with the method by
which these flags can be programmed, parallel or serial. After
Master Reset, LD enables write operations to and read
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.
Associated with each of the programmable flags, PAE and
PAF, is one register which can either be written to or read from.
Offset values contained in these registers determine how
many words need to be in the FI FO memory to switch a partial
flag. A LOW on LD during Master Reset selects a default PAE
offset value of 07FH ( a threshold 127 words from the empty
boundary), a default PAF offset value of 07FH (a threshold 127
words from the full boundary), and parallel loading of other
offset values. A HIGH on LD during Master Reset selects a
default PAE offset value of 3FFH (a threshold 1023 words from
the empty boundary), a default PAF offset value of 3FFH (a
threshold 1023 words form the full boundary), and serial
loading of other offset values.
WCLK
Selection
RCLK
S
X
S
X
S
X
S
D
D
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
X
Serial shift into registers:
26 bits for the 72255
28 bits for the 72265
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
No Operation
X
Write Memory
S
Read Memory
X
No Operation
3037 Ibl 02
NOTES:
1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.
2. The programming method can only be selected at Master Reset.
3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
4. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 2. Partial Flag Programming Sequence
5.03
9
II
IDT72255n2265 SyncFIFOTM
8,192 x 18, 16,384 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
two pointers operate independently; however, a read and a
write should not be perfonned simultaneously to the offset
registers. A Master Reset initializes both pointers to the
Empty Offset (LSB) register. A Partial Reset has no effect on
the position of these pointers.
Once serial offset loading has been selected, then programming PAE and PAF procedes as follows: When LD and
SEN are set LOW, data on the SI input are written, one bit for
each WCLK rising edge, sta rting with the Empty Offset (13 bits
forthe 72255, 14 bits forthe 72265), ending with the Full Offset
(13 bits for the 72255, 14 bits for the 72265). A total of 26 bits
are necessary to program the 72255; a total of 28 bits are
necessary to program the 72265. Individual registers cannot
be loaded serially; rather, both must be programmed in
sequence, no padding allowed. PAE and PAF can show a
valid status only afterthe the full set of bits have been entered.
The registers can be re-programmed, as long as both offsets
are loaded. When LD is LOW and SEN is HIGH, no serial write
to the registers can occur.
Once parallel offset loading has been selected, then
programming PAE and PAF procedes as follows: When LD
and WEN are set LOW, data on the inputs On are written into
the Empty Offset Registeron the first LOW-to-HIGH transition
of WCLK.
Upon the second LOW-to-HIGH transition of
WCLK, dataatthe inputs are written intothe Full Register. The
third transition of WCLK writes, once again, to the Empty
Offset Register.
To ensure proper programming (serial or parallel) of the
offset registers, no read operation is permitted from the time
of reset (masteror partial) to the time of programming. (During
this period, the read pointer must be pointing to the first
location of the memory array.) After the programming has
been accomplished, read operations may begin.
Write operations to memory are allowed before and during
the parallel programming sequence. In this case, the programming of all offset registers does not have to occur at one
time. One or two offset registers can be written to and then,
by bringing LD HIGH, write operations can be redirected to the
FIFO memory. When LD is set LOW again, and WEN is LOW,
the next offset register in sequence is written to. As an
altemative to holding WEN LOW and toggling LD, parallel
programming can also be interrupted by setting LD LOWand
toggling WEN.
Write operations to memory are allowed before and during
the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing LD and SEN HIGH, data can be written to FIFO
memory via DnbytogglingWEN. When WEN is brought HIGH
with LD and SEN restored to a LOW, the next offset bit in
sequence is written to the registers via SI. If a mere interuption
of serial programming is desired, it is sufficient eitherto set LD
LOW and deactivate SEN or to set SEN LOW and deactivate
LD. Once LD and SEN are both restored to a LOW level, serial
offset programming continues from where it left off.
Note that the status of a partial flag (PAE or PAF) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
the register pertaining to that flag. From the time serial
programming has begun, neither partial flag will be valid until
thefull set of bits requiredto fill allthe offset registers has been
written. Measuring from the rising WCLK edge that achieves
either of the above criteria; PAF will be valid after two more
rising WCLK edges plus tpAF, PAE will will be valid after the
next two rising RCLK edges plus tPAE (Add one more RCLK
cycle if tSKEW2 is not met.)
The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset registers can be read on the output lines when LD is set LOW and
REN is set LOW; then, data are read via an from the LSB
Empty Offset Register on the first LOW-to-HIGH transition of
RCLK. Upon the second LOW-to-HIGH transition of RCLK,
data are read from the MSB Empty Offset Register. Upon the
third LOW-to-H IGH transition of RCLK, data are read from the
LSB Full Offset Register. Upon the fourth LOW-to-HIGH
transition of RCLK, data are read from the MSB Full Offset
Register. The fifth transition of RCLK reads, once again, from
the LSB Empty Offset Register.
It is permissable to interrupt the the offset register access
sequence with reads or writes to memory. The interruption is
accomplished by deasserting REN, LD, or both together.
When REN and LD are restored to a LOW level, access of the
registers continues where it left off.
LD functions the same way in both lOT Standard and
FWFT modes.
FREQUENCY SELECT INPUT (FS)
An intemal state machine manages the movement of data
through the Supersync FIFO. The FS line detennines whether
RCLK orWCLK will synchronize the state machine. Tie FS to
Vee if the RCLK line is running at a lower frequency than the
WCLK line. In this case, the state machine will be synchronized to WCLK. Tie FS to GND if the RCLK line is running at
a higher frequency than the WCLK line. In this case, the state
machine will be synchronized to RCLK. Note that FS must be
set so the clock line running at the higher frequency drives the
state machine; this ensures efficient handling of the data
within the FIFO. Ifthe same clock signal drives both the WCLK
and the RCLK pins, then tie FS to GND.
The frequency of the clock tied to the state machine
(referred to as the "selected clock") may be changed at any
time, so long as it is always greater than or equal to the
frequency of the clock that is not tied to the state machine
(referred to as the "non-selected clock"). The frequency of the
non-selected clock can also be varied with time, so long as it
never exceeds the frequency of the selected clock. To be
more specific, the frequencies of both RCLK and WCLK may
be varied during FIFO operation, provided that, at any given
point in time, the cycle period of the selected clock is equal to
or less than the cycle period of the non-selected clock.
The selected clock must be continuous. It is, however,
permissible to stop the non-selected clock. Note, so long as
RCLK is idle, EF/OR and PAE will not be updated. Likewise,
as long as WCLK is idle, FFIIR and PAF will not be updated.
Changing the FS setting during FIFO operation (Le. read-
5.03
10
IDT72255n2265 SyncFIFOTM
8,192 x 18, 16,384 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ing or writing) is not pennitted; however, such a change at the
time of Master Reset or Partial Reset is all right. FS is an
asynchronous input.
OUTPUTS:
FULL FLAG (FFIIR)
This is a dual purpose pin. In lOT Standard Mode, the Full
Flag (FF) function is selected. When the FIFO is full (Le. the
write pointer catches up to the read pointer), FF will go LOW,
inhibiting further write operation. When FF is HIGH, the FIFO
is not full. If no reads are performed after a reset (either MRS
or PRS), FF will go LOW after 8,192 writes tor the IOT72255
and 16,384 writes to the IOT72265.
In FWFT Mode, the Input Ready (IR) function is selected.
IR goes LOW when memory space is available for writing in
data. When there is no longer any free space left, IR goes
HIGH, inhibiting further write operation. If no reads are
performed after a reset (either MRS or PRS), IR will go HIGH
after 8,193 writes for the IOT72255 and 16,385 writes for the
IOT72265.
The IR status not only measures the contents of the FIFO
memory, but also counts the presence of a word in the output
register. Thus, in FWFT mode, the total number of writes
necessary to deassert IR is one greater than needed to assert
FF in lOT Standard mode.
FFIIR is synchronized to WCLK. It is double-registered to
enhance metastable immunity.
When writingthefirst word to an empty FIFO, thedeassertion
time of EF is variable, and can be represent by the First Word
Latency parameter, tFWL 1, which is measured from the rising
WCLK edge that writes the first word to the rising RCLK edge
that updates the flag. tFWL 1 includes any delays due to clock
skew and can be expressed as follows:
tFWL 1 max.
where Tf is either the RCLK orthe WCLK period, whichever is
shorter, and TRCLK is the RCLK period. Since no read can
take place until EF goes HIGH, the tFWL1 delay detennines
how early the first word can be available at an. This delay has
no effect on the reading of subsequent words.
In FWFT Mode, the Ouput Ready (OR) function is selected.
OR goes LOW at the same time that the first word written to an
empty FIFO appears valid on the outputs. OR goes HIGH one
cycle after RCLK shifts the last word from the FIFO memory
to the outputs. Then further data reads are inhibited until OR
goes LOW again.
When writing the first word to an empty FIFO, the assertion
time of OR is variable, and can be represented by the First
Word Latency parameter, tFWL2, which is measured from the
rising WCLK edge that writes the first word to the rising RCLK
edge that updates the flag. tFWL2 includes any delay due to
clock skew and can be expressed as follows:
tFWL2 max.
EMPTY FLAG (EFIOR)
This is a dual purpose pin. In the lOT Standard Mode, the
Empty Flag (EF) function is selected. When the FIFO is empty
(Le. the read pointer catches up tothe write pointer), EFwill go
LOW, inhibiting further read operations. When EFisHIGH, the
FIFO is not empty.
72265 - 16,384 x 18-BIT
o
12
17
13
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
o
12
0
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
17
= 10*Tf + 3*TRCLK (in ns)
where Tf is either the RCLK orthe WCLK period, whichever is
shorter, and TRCLK is the RCLK period. Note that the First
Word Latency in FWFT mode is one RCLK cycle longer than
in lOT Standard mode. The tFWL2 delay determines how early
the first word can be available at an. This delay has no effect
72255 - 8,192 x 18-BIT
17
= 1O*Tf + 2*TRCLK (in ns)
17
FULL OFFSET REGISTER
13
0
FULL OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
3037 drw 05
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
3037 drw 06
Figure 3. Offset Register Location and Default Values
5.03
11
IDT72255n2265 SyncFIFOTM
8,192 X 18, 16,384 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
on the reading of subsequent words.
EF/OR is sychronized to the RCLK. It is double-registered
to enhance metastable immunity.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW
when the FIFO reaches the Almost-Full condition as specified
by the offset m stored in the Full Offset register.
At the time of Master Reset, depending on the state of LO,
one of two possible default offset values are chosen. If LO is
LOW, then m = 07FH and the PAF switching threshold is 127
words from the Full boundary, if LO is HIGH, then m = 3FFH
and the PAF switching threshold is 1023 words away from the
Full boundary.
Any integral value of m from 0 to the maximum FIFO depth
minus 1 (8,191 words for the 72255, 16,383 words for the
72265) can be programmed into the Full Offset register.
In lOT Standard Mode, if no reads are performed after reset
(MRS or PRS) , PAF will go LOW after (8, 192-m) writes to the
IOT72255, and (16,384-m) writes to the IOT72265.
In FWFT Mode, if no reads are performed after reset (MRS
or PRS) , PAF will go LOW after (8,193-m) writes to the
IOT72255, and (16,385-m) writes to the IOT72265. In this
case, the first word written to an empty FIFO does not stay in
memory, but goes unrequested to the output register; therefore, it has no effect on determining the state of PAF.
Note that even though PAF is programmed to switch LOW
during the first word latency period (tFWL), attempts to read
data will be ignored until EF goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAF is synchronous and updated on the rising edge of
WCLK. It is double-registered to enhance metastable immunity.
TABLE 1- STATUS FLAGS FOR lOT STANDARD MODE
Number of Words in FIFO Memory
(1)
72265
FF
°
H
H
H
H
L
H
(n+ 1) to 4,096
(n+1)to 8,192
H
H
H
H
H
4,097 to (8192-(m+1»
8,193 to (16,3B4-(m+ 1»
H
H
L
H
H
(16,3B4-m)(3)to 16,383
H
L
L
H
H
16,384
L
L
L
H
H
72255
°
1 to n (2)
(B,192-m)(3)to B,191
B,192
1 to n(2)
PAF
H
HF
H
PAE
L
EF
L
3037tb103
NOTES:
1. Data in the output register does not count as a 'word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes
unrequested to the output register (no read operation necessary), it is not inclUded in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
TABLE 11- STATUS FLAGS FOR FWFT MODE
Number of Words In FIFO Memory
72255
°
1 to n (2)
(1)
72265
fA
PAF
HF
PAE
°
1 to n
L
H
H
L
OR
H(4)
L
H
H
L
L
(n+ 1) to 4,096
(n+1) to B,192
L
H
H
H
L
4,097 to (B192-(m+1»
B,193to (16,3B4-(m+1»
L
H
L
H
L
(B,192-m)(3)to B,191
(16,3B4-m) (3)to 16,3B3
L
L
L
H
L
H
L
L
H
8,192
(2)
16,3B4
L
3037tbl04
NOTES:
, .Data in the output register does not COUnt as a 'word in FiFO memory". 8ince in FWFT mode, the first word wrinen to an empty FiFO
goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
4. Following a reset (Master or Partial), the FIFO memory is empty and OR = HIGH. After writing the first word, the FIFO memory remains empty,
the data is placed into the output register, and OR goes LOW. In this case, or any time the last word in the FIFO memory has been read into the
output register; a rising RCLK edge, enabled by REN, will set OR HIGH.
5.03
12
IDT72255n2265 SyncFIFOTM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8,192 x 18, 16,384 x 18
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty Flag (PAE) will go LOW
when the FIFO reaches the Almost-Empty condition as specified by the offset n stored in the Empty Offset register.
At the time of Master Reset, depending on the state of LD,
one of two possible default offset values are chosen. If LD is
LOW, then n = 07FH and the PAE switching threshold is 127
words from the Empty boundary, if LD is HIGH, then n = 3FFH
and the PAE switching threshold is 1023 words away from the
Empty boundary.
Any integral value of n from 0 to the maximum FIFO depth
minus 1 (8,191 words for the 72255, 16,383 words for the
72265) can be programmed into the Empty Offset register.
In IDT Standard Mode, if no reads are performed after
reset (MRS or PRS) , the PAE will go HIGH after (n + 1) writes
to the IDT72255/72265.
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), the PAE will go HIGH after (n+2) writes to the
IDT72255/72265. In this case, the first word written to an
empty FIFO does not stay in memory, but goes unrequested
to the output register; therefore, it has no effect on determining the state of PAE.
Note that even though PAE is programmed to switch HIGH
during the first word latency period (tFWL) , attempts to read
data will be ignored until EFgoes HIGH indicating that data is
available at the output port.
This is true for both timing
modes.
PAE is synchronous and updated on the rising edge of
RCLK. It is double-registered to enhance metastable immunity.
HALF-FULL FLAG (HF)
This output indicates a half-full memory. The rising WCLK
edge that fills the memory beyond half-full sets HF LOW. The
flag remains LOW until the difference between the write and
read pointers becomes less than or equal to half of the total
depth of the device; the rising RCLK edge that accomplishes
this condition also sets HF HIGH.
In IDT Standard Mode, if no reads are performed after reset
(MRS or PRS), HFwill go LOW after (D/2 + 1) writes, where D
is the maximum FIFO depth (8,192 words for the IDT72255,
16,384 words for the IDT72265).
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), HFwill go LOW after (D/2+2) writes to the IDT72255/
72265. In this case, the first word written to an empty FIFO
does not stay in memory, but goes unrequested to the output
register; therefore, it has no effect on determining the state of
HF.
Because HF uses both RCLK and WCLK for synchronization purposes, it is asynchronous.
DATA OUTPUTS (Qo-Q17)
00-017 are data outputs for 18-bit wide data.
5.03
13
II
IDT72255n2265 SyncFIFOTM
8,192 x 18,16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~----------tRS------------~
f4--------
tRSS
---------.14------ tRSR-----~
-++-------
tRSS
----____.-14------ tRSR-----~
~----
tRSR ------t~
---------."i+----
tRSR-----~
FWFT/SI
tRSS
LD(I)
tRSS
RT
tRSS
SEN
tRSF
If FWFT = HIGH, OR = HIGH
EF/OR
If FWFT = LOW, EF = LOW
tRSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, iFf= LOW
FFiiR
tRSF
PAE
~----tRSF----~
I•
tRSF-----ti
(1)·
--------------00 - 017
------------------~
OE= HIGH
- - - - - - - - - - - - - - -OE=LOW
3037 drw 07
Figure 4. Master Reset Timing
5.03
14
IDT72255n2265 SyncFIFOTM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8,192 X 18,16,384 X 18
--
tRS
~~
J
I
I
IL
tRSS
tRSR
tRSS
tRSR
J
{
XXj K~
I
I
J
{
XX;KX*
tRSS
I
-*I
..
..
tRSS
~
tRSF
tRSF
--'
If FWFT = HIGH. OR = HIGH
*:
If FWFT - LOW.
J
EF = LOW
II
If FWFT = LOW. FF = HIGH
If FWFT = HIGH. 1R= LOW
..
tRSF
-
tRSF
I
~
J
I
7
.
00 - 017
tRSF
t----------
-------------~
-
-
-
-
-
-
-
(1)
__
OE= HIGH
-----OE= LOW - - - -
3037 drw 08
Figure 5. Partial Reset Timing
5.03
15
I0T72255n2265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
Do - 017
WEN
FF
RCLK
REN
/
3037 drw 09
NOTES:
1. tSKEWl is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF).
If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra WCLK
~cle.
2. LD =HIGH
Figure 6. Write Cycle Timing (lOT Standard Mode)
5.03
16
10T72255n2265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~------------tCLK------------~
tCLKL
- - tCLKH
RCLK
NO OPERATION
tREF ----~~
_tREF
..
00 - 017
WCLK
Do - 017
3037 drw 10
NOTES:
1. tFWL1 contributes a variable delay to the overall first word latency (this parameter includes delays due to skew):
tFWL1 max. (in ns) 10*TI + 2* TRCLK
where TI is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period
=
2. LD
=HIGH
Figure 7. Read Cycle Timing (lOT Standard Mode)
5.03
17
IDT72255n2265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS~
DO
00·017
01
tENS~
~------'/
...............
~'_ _ _ _ tFWl1(c:...l)_ _ _~.!
RCLK
~
3037 drw 11
NOTES:
1. tFWL1 max. (in ns) 10* TI + 2* TRCLK
Where TI is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period
2. LD HIGH
=
=
Figure 8. First Data Word Latency (IDT Standard Mode)
5.03
18
IDT722Ssn226S SyncFIFOTM
8,192 x 18,16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
3037 drw 12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF).
If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra
WCLK cycle.
2. LD
=HIGH
Figure 9. Full Flag Timing (lOT Standard Mode)
5.03
19
II
10T722ssn226S SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
Do - 017
RCLK
LOW
00- 017
-----------------~~--------------==*
DATA IN OUTPUT REGISTER
WORD 1
3037drw 13
NOTES:
1. tFWL1 max. (in ns) 10*TI + 2*TRCLK
Where TI is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the period.
=
2. LD
=HIGH
Figure 10. Empty Flag Timing (lOT Standard Mode)
5.03
20
I0T72255n2265 SyncFIFOTM
8,192 x 18,16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
P
,
81
BITX(l)
~
-~·I~
3037 drw 14
Figure 11. Serial Loading of Programmable Flag Registers (lOT Standard and FWFT modes)
II
NOTE:
1. For the 72255, X = 12.
For the 72265, X 13.
=
1-o----tcLK - - - - I
WCLK
ritENH
00·017
Figure 12. Parallel Loading of Programmable Flag Registers (lOT Standard and FWFT modes)
5.03
21
I0T72255n2265 SyncFIFOTM
8,192 x 18,16,384 x 18
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
t - - - - tcLK _ _ _- !
RCLK
00·017
DATA IN OUTPUT REGISTER
PAEOFFSET
PAFOFFSET
3037 drw 16
Figure 13. Parallel Read of Programmable Flag Registers (lOT Standard and FWFT modes)
NOTE:
1. OE=LOW
WCLK
n+1 words in FIFO memory
RCLK
REN -------------------------------~~
3037drw 17
NOTES:
1. PAE offset = n
2. Data inthe output register does not count as a "word in FI FO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO me~ count.
3. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH (after one RCLK cycle plus tPAE). If the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
Figure 14. Programmable Almost Empty Flag Timing (lOT Standard and FWFT modes)
5.03
22
IDT72255n2265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
D-(m+1)
Words in FIFO
Memory
RCLK
3037 drw 18
NOTES:
1. PAF offset = m, D = 8,192 for IDT 72255, 16,384 word for IDT 72265.
2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAFto go HIGH (after one WCLK cycle plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
Figure 15. Programmable Almost Full Flag Timing (lOT Standard and FWFT modes)
II
I
WCLK
RCLK
3037 drw 19
NOTE:
1. D
= maximum FIFO depth =8,192 for IDT 72255, 16,384 word for IDT 72265.
Figure 16. Half - Full Flag Timing (lOT Standard and FWFT modes)
5.03
23
IDT72255n2265 SyncFIFOTM
8,192
X
18, 16,384
X
MILITARY AND COMMERCIAL TEMPERATURE RANGES
18
WCLK
wrn
Do - 017
RCLK
~
Qo- Q17
m
tREF
~
tPAE
J5AE
tHF
Rr
tPAF
~
IT(')
3037 drw 20
NOTES:
1. tRTFl contributes a variable delay to the overall retransmit recovery time:
tRFTFl max = 14*TI + 3*TRCLK (in ns)
Where TI is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. Retransmit set u£..!s complete after EF returns HIGH, only then can a read operation begin. Write operations are permitted after one of two conditions
have been met: EF is HIGH or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the RT pulse.
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of HF, PAE, and PAF.
4. No more than D-2 words (D = 8,192 words for the 72255, 16,384 words for the 72265) should have been written to the FIFO between Reset (Master or
Partial) and Retransmit Setup. Therefore, FF will be HIGH throughout the Restransmit Setup procedure.
5. OE=LOW
Figure 17. Retransmit Timing (lOT Standard mode)
5.03
24
SOc
~:::1
1\)1\)
><~
.... (11
J" ~
.... 1\)
all\)
'Wm
WCLK
~~
><
:J
.... 0
co"
:;;
WEN
o
i1
Do - 017
RCLK
REN
00- Q17
OR
,tPAE
(11
PAE
(:)
w
HF
PAF
fA
:i:
r=
______________________________________________________________________________________________________________________~__m__
FF~
3037 drw21
i1
::0
-<
>
z
c
(")
o
NOTES:
1. tFWl2 max. (in ns) 10*Tf + 3*TRCLK
where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE =LOW
4. PAE offset n, PAF offset m, D maximum FIFO depth 8,192 words for the IDT72255, 16,384 words for the IDT72265.
=
=
=
=
=
:i:
:i:
m
::0
(")
;t;
r
-l
m
:i:
"tI
m
::0
~
Figure 18. Write Timing (First Word Fall Through Mode)
c:
::0
m
::0
>
Z
I\)
(11
C>
m
en
II
01-
~~
i')i')
Xi')
en
~!S
~
WCLK
... i')
Q)i')
~
Q)
Wen
~~
x :::s
WEN
"'0
01.,..
=n
~
Do - D17
RCLK
REN
OE
Qo- Q17
OR
en
0
W
PAE
RF
~,
PAF
iR
~'M
[;
a:
r=
~
:rJ
-<
»z
c
o
3037 drw22
o
a:
a:
m
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that fA will go LOW (after one WCLK cycle plus twFF). If the time between the rising ege of RCLK
and the rising edge of WCLK is less than tSKEW1, then the fA assertion may be delayed an extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAFto go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of RCLK and the rising
edge of WCLK is less than tSKEW2, then the PAF deassertion may be delayed an extra WCLK cycle.
3. LD =HIGH
4. PAE Offset n, PAF offset m, D maximum FIFO depth 8,192 words for the IDT72255, 16,384 words for the IDT72265.
=
=
=
=
:rJ
o
r
);
-I
m
a:
"
m
:rJ
~
c:
:rJ
m
Figure 19. Read Timing (First Word Fall Through Mode)
i')
Q)
:rJ
»z
c;)
m
rn
IDT72255n2265 SyncFIFOTM
8,192
X
MILITARY AND COMMERCIAL TEMPERATURE RANGES
18,16,384 X 18
WCLK
Do - 017
RCLK
Qo-017
II
IPAF
I
m
(4
)
3037 drw 23
NOTES:
1. tRTF2 contribute a variable delay to the overall retransmit time:
tRTF2 max = 13*Tf + 4*TRCLK (in ns)
Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. Retransmit set up is complete after OR returns LOW, only then can a read operation begin. Write operations are permitted after one of two conditions
have been met: OR is LOW or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the RT pulse.
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of HF, PAE, and PAF.
4. No more than D-2 words (D = 8,192 words for the 72255, 16,384 words for the 72265) should have been written to the FI FO between Reset (Master or
Partial) and Retransmit Setup. Therefore, TR will be LOW throughout the Retransmit Setup procedure.
5. OE=LOW
Figure 20. Retransmit Timing (FWFT mode)
5.03
27
IDT12255n2265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
tion requirements are for 8,192116,384 words or less. The
IDT72255172265 can always be used in Single Device ConSINGLE DEVICE CONFIGURATION
figuration, whether IDT Standard Mode or FWFT Mode has
A single IDT72255172265 may be used when the applica- been selected. No special set up procedure is necessary.
PARTIAL RESET (PRS)
MASTER RESET (MRS)
it
WRITE CLOCK (WCLK).
READ CLOCK (RCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
LOAD (LD)
OUTPUT ENABLE (OE)
~
DATA OUT (Qo - Q17)
DATA IN (Do - D17).
IDT
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
72255/
72265
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST EMPTY (PA,!=)
FULL FLAG/INPUT READY (FF/IR)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST FULL (PAF)
t
FREQUENCY SELECT (FS)
3037 drw 24
Figure 21. Block Diagram of Single 8,192x18/16,384x18 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting togetherthe control signals of multiple devices. Status flags can
be detected from any c;me device. The exceptions are the EF
and FF functions in IDT Standard mode and the fA and OR
functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion
and fRiOR assertion to vary by one cycle between FIFOs. In
IDT Standard mode, such problems can be avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and
separately ORing fA of every FIFO. Figure 22 demonstrates
an 36-word width by using two IDT72255172265s. Any word
width can be attained by adding additiona11DT72255172265s.
5.03
28
IDT72255172265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT
DATA IN (Dn)
(fIT)
I1/
/36
1
1
~
18
WRITE CLOCK (WCLK)
-
-
WRITE ENABLE (WEN)
IDT
IDT
72255/
72265/
722551
722651
-
LOAD (ill)
-R
1
~
FULL FLAGIINPUT READY (FF/iR) #1
FULL FLAG/INPUT READY (FF/iR) #2
-
-
~
PROGRAMMABLE (PAF)
#1
HALF FULL FLAG (HF)
READ ENABLE (REN)
OUTPUT ENABLE
(OE)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
IGAT~ll
EMPTY FLAG/OUTPUT READY (EF/OR) #2
#2
~8
READ CLOCK (RCLK)
/18 DATA OUT (On)
/36
[I
1
FREOUENCY SELECT (FS)
3037 drw 25
II
NOTE:
1. Use an AND gate in lOT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
Figure 22. Block Diagram of 8,192x36/16,384x36 72255/65 Width Expansion
I
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the
outputs of the last FIFO in the chain-no read operation is
necessary. Each time the data word appears at the outputs
of one FIFO, that device's OR line goes LOW, enabling a write
to the next FIFO in line.
The OR assertion time is variable and is described with the
help of the tFWL2 parameter, which includes including delay
caused by clock skew:
DEPTH EXPANSION CONFIGURATION
The IDT72255/72265 can easily be adapted to applications
requiring more than 8,192116,384 words of buffering. In
FWFT mode, the FIFOs can be arranged in series (the data
outputs of one FI FO connected to the data inputs of the next)no external logic necessary. The resulting configuration
provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 23 shows a depth
expansion using two IDT72255/72265s.
Care should be taken to select FWFT mode during Master
Reset for all FIFOs in the depth expansion configuration. The
tFWL2 max.= 10*TI + 3*TRCLK
TRANSFER CLOCK
WRITE CLOCK
WCLK
RCLK
WRITE ENABLE
OR
WEN
INPUT READY
TR
72255/
72265
/
On
RCLK
WEN
REN
72255/
72265
GND
/18
an
FS
WCLK
iR
REN
OE
DATA BUS /18
I
/
I
READ CLOCK
READ ENABLE
OUTPUT READY
OR
OUTPUT ENABLE
OE
18/ DATA OUT
an
On
FS
/
I
3037 drw 26
Figure 23. Block Diagram of 16,384x18/32,768x18 Synchronous FIFO Memory
With Programmable Flags used in Depth Expansion Configuration
5.03
29
IDT12255f72265 SyncFIFOTM
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
where TRCLK is the RCLK period and Tf is either the RCLK or
the WCLK period, whichever is shorter.
The maximum amount of time it takes for a word to pass
from the inputs of the first FI FO to the outputs of the last FI FO
in the chain is the sum of the delays for each individual FIFO:
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's iR line goes LOW, enabling the preceding
FIFO to write a word to fill it.
The amount oftime it takes for I R of the first FI FO in the chain
to assert after a word is read from the last FIFO is the sum of
the delays for each individual FIFO:
N*(3*TwCLK)
tFWL2(1) + tFWL2(2) + ... + tFWL2(N)+ N*TRCLK
where N is the number of FIFOs in the expansion.
Note that the additional RCLK term accounts for the time it
takes to pass data between FI FOs.
The ripple down delay is only noticeable for the first word
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.
The first free location created by reading from a full depth
expansion configuration will "bubble up" from the last FIFO to
the previous one until it finally moves into the first FIFO of the
where N is the number of FIFOs in the expansion and TWCLK
is the WCLK period. Note that one of the three WCLK cycle
accounts for TSKEW1 delays.
In a Supersync depth expansion, set FS individually for
each FIFO in the chain. The Transfer Clock line should be tied
to either WCLK or RCLK, whichever is faster. Both these
actions result in moving, as quickly as possible, data to the
end of the chain and free locations to the beginning of the
chain.
ORDERING INFORMATION
IDT
XXX XX
Device I ype
X
Power
xx
~
X
PacKage
X
Process I
Temperature
Range
y~LANK
L..----------t
G
PF
TF
10
12
L . . . - - - - - - - - - - - - - i 15
20
25
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
L...---------------------t
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Pin Grid Array (PGA)
Thin Plastic Quad Flatpack
Slim Thin Quad Flatpack
Com'l Only
Com:1 OnlX
Com I & Mil.
Com' I Only
Mil. Only
L
72255
72265
}
Clock Cycle Time (tLK)
Speed in Nanoseconds
Low Power
8,192 x 18 Synchronous FIFO
16,384 x 18 Synchronous FIFO
3037 drw 27
5.03
30
(;)®
PRELIMINARY
IDT72423
IDT72203
IDT72213
CMOS SINGLE BIT SyncFIFO™
64 X 1, 256 x 1, 512 x 1
Integrated Devlc.e Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
64 X 1-bit organization (IDT72423)
256 x 1-bit organization (IDT72203)
512 x 1-bit organization (lDT72213)
10 ns read/write cycle time (I DT72423172203172213)
Independent read and write clock lines
Empty and Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can
be programmed to any depth via a dedicated port (Pn).
These flags default to Empty+7 and Full-7, respectively.
• Output enable puts output data bus in high impedance
state
• Available in 24-pin SOIC, 24-pin plastic DIP (300 mil.),
and 24-pin ceramic DIP (300 mil.)
• Military product compliant to MIL-STD-883, Class B
Advanced submicron CMOS technology
DESCRIPTION:
The IDT72423172203172213 SyncFIFO™ are very highspeed, low-power First-In, First-Out (FIFO) memories with a
word width of 1 and clocked read and write controls. The
IDT72423172203172213 have a 64, 256, and 512 x 1-bit
memory arrays, respectively. These FIFOs are appropriate
FUNCTIONAL BLOCK DIAGRAM
for a wide variety of serial data buffering needs, especially
telecommunications applications such as networks, modems,
signal processing, and serial interfaces.
These single-bit FIFOs have 1-bit input (D) and output ports
(Q).The input port is controlled by a free-running clock (WCLK),
and two write enable pins (WEN1 , WEN2). Data is written into
the Synchronous FIFO on every riSing clock edge when the
write enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and a read enable pin (REN). The
read clock can be tied to the write clock for single clock
operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF). Two programmable flags, Almost-Empty (PAE)
and Almost-Full (PAF), are provided for improved system
contro.!:..!tle programmable flags default to Empty+7 and Full7 for PAE and PAF, respectively. The programmable flag
offset is loaded via the Program Inputs (PO - P7), on the rising
WCLK when the load pin (LD) is asserted.
The IDT72423172203/722131 are fabricated using IDT's
high-speed submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
D
Po - P7
W LK
W N1
W N2
r---~----------~EF
L....-+-+-~
---~ PAE
---~.EAF
"--~------~--~~FF
RAM ARRAY
64 x 1
256 x 1
512
x1
RCLK
REN
Q
3111 drw01
The lOT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1994
DSC-20651-
©1995 Integrated Device Technology. Inc
5.04
1
II
1D172423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1,512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
P5
P4
24
2
23
P7
P3
3
22
D
P2
4
21
RS
P1
5
Po
6
20
WEN1
19
WCLK
PAF
7
18
WEN2/LD
8
17
Vee
Vss
9
16
Q
10
15
FF
RCLK
11
14
EF
REN
12
13
OE
DIP/SOle
TOP VIEW
PIN DESCRIPTIONS
Name
P24-1
D24-1
S024-2
PAE
NC
Symbol
Ps
3111 drw02
Description
I/O
D
RS
Data Input
I
Reset
I
WCLK
Write Clock
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s) are asserted.
WEN1
Write Enable 1
I
WEN2ILD
Write Enable 2/
Load
I
PO-P7
Program Inputs
I
Q
RCLK
Data Output
If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin.
When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW.
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2I
LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2ILD is held LOW to write or read the programmable flag
offsets.
Offsets for the programmable flag registers are entered at these inputs on the rising edge of
WCLK when LD and WEN are LOW
Output for serial data.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
REN
Read Enable 1
I
OE
Output Enable
I
EF
Empty Flag
0
PAE
Programmable
Almost-Empty
Flag
0
PAF
Programmable
Almost-Full Flag
Full Flag
0
FF
Vee
GND
Read Clock
Power
Ground
0
I
0
Input for serial data.
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after
power-up.
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
hiqh impedance state.
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7. PAE is synchronized to RCLK.
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7. PAF is synchronized to WCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
One +5Volt power supply pin.
One OVoit ground pin.
3111 tbl01
5.04
2
1DT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64x1,256x1,512x1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TA
RECOMMENDED OPERATING CONDITIONS
Military
Unit
Symbol
Parameter
Min.
Typ.
Max.
Unit
Terminal Voltage -0.5 to +7.0
with Respect to
GND
Operating
a to +70
Temperature
-0.5 to +7.0
V
VeeM
Military Supply Voltage
Commercial
Supply Voltage
5.0
5.0
5.5
5.5
V
Veee
4.5
4.5
GND
Supply Voltage
0
a
V
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
VIL
Input Low Voltage
Commercial & Military
-
-
0.8
V
Rating
Commercial
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
DC Output
Current
-55 to +125
-65 to +135
°C
50
50
mA
lOUT
a
3111 tbl03
NOTE:
3111 tbl02
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthe specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
(TA= +25°C, f= 1.0MHz)
Parameter
Conditions
Max.
Symbol
CIN(2)
Input Capacitance
COUT(I,2)
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
± 10%, TA =
ODC to +70 DC; Military: Vcc = 5V
± 10%, TA=
10
pF
VOUT= OV
10
pF
IDT72423
IDT72203
IDT72213
Commercial
tCLK 10, 12, 15n5
Max.
Min.
Typ.
Parameter
3111 tbl04
II
-55 DC to +12SDC)
=
Symbol
Unit
VIN = OV
NOTES:
1. With output deselected (OE = HIGH).
2. Characterized values, not currently tested.
(Commercial: Vcc = 5V
V
IDT72423
IDT72203
IDT72213
Military
tCLK 15, 25ns
Min.
Typ.
Max.
=
Unit
IU(I)
Input Leakage Current (Any Input)
-1
-
1
-10
-
10
(.LA
ILot2)
Output Leakage Current
-10
10
-10
-
10
(.LA
VOH
Output Logic "1" Voltage, IOH = -2 mA
2.4
V
Output Logic "0" Voltage, IOL = 8 mA
0.4
V
lec(3)
Active Power Supply Current
-
-
-
VOL
-
-
2.4
0.4
-
80
-
100
mA
3111 tbl05
NOTES:
1. Measurements with 0.4 :0; VIN :0; Vee.
2. OE:2! VIH, 0.4 :0; VOUT:O; Vee.
3. Measurements are made with outputs unloaded. Tested at fCLK
=20MHz.
5.04
3
IDTI2423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = SV ± 10%, TA = O°C to + 70°C; Military: Vcc = SV ± 10%, TA = -SsoC to +12S0C)
Commmercial
Symbol
Com'l & Mil.
Military
72423L10
72423L12
72423L15
72423L25
72203L10
72203L12
72203L15
72203L25
72213L10
72213L12
72213L15
Parameter
Min.
fS
tA
Clock Cycle Frequency
Data Access Time
100
2
Min.
Max.
-
-
7.5
2
12
tCLK
Clock Cycle Time
10
tCLKH
Clock High Time
4.5
tCLKL
Clock Low Time
4.5
tDS
Data Set-up Time
3
tDH
Data Hold Time
0
-
tENS
Enable Set-up Time
3
tENH
Enable Hold Time
0
tRS
Reset Pulse Width(l)
10
tRSS
Reset Set-up Time
10
tRSR
Reset Recovery Time
10
tRSF
Reset to Flag and Output Time
10
tOLZ
Output Enable to Output in Low-Z(2)
tOE
tOHZ
tWFF
Write Clock to Full Flag
7.5
tREF
Read Clock to Empty Flag
tAF
Max.
Min.
Max.
83.3
8
-
66.7
10
2
15
0
-
-
3
-
4
-
0.2
-
1
12
-
15
12
15
12
-
-
0
-
Output Enable to Output Valid
3
Output Enable to Output in High-Z(2)
3
72213L25
Min.
Max.
Unit
40
15
Mhz
ns
3
-
25
-
ns
6
10
-
ns
6
-
10
ns
4
-
6
-
6
-
1
-
ns
25
ns
25
-
15
-
25
-
ns
12
-
15
-
25
ns
0
-
0
-
0
-
ns
6.5
3
7
3
8
3
13
ns
6.5
3
7
3
8
3
13
ns
-
8
ns
10
-
15
8
-
10
7.5
-
15
ns
Write Clock to Almost-Full Flag
7.5
-
-
8
-
10
-
15
ns
tAE
Read Clock to Almost-Empty Flag
7.5
-
-
8
-
10
-
15
ns
tSKEW1
Skew time between Read Clock &
Write Clock for Empty Flag &Full Flag
5
-
5
-
6
-
10
-
ns
tSKEW2
Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full FlaQ
22
-
22
-
28
-
40
-
ns
5
5
3
1
1
NOTES:
ns
ns
ns
ns
3111 tbt06
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
1.1Kn
D.U.T.---........- -...
680n
30pF*
See Figure 1
3111 tbl07
3111 drw03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.04
4
1DT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
Data In (D) -
Input for serial data.
CONTROLS:
--.!Ieset (RS)-Reset is accomplished whenever the Reset
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(PAF) will be reset to HIGH aftertRsF. The Empty Flag (EF) and
Programmable Almost-Empty Flag (PAE) will be reset to low
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Write Clock (WCLK)-A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (PAF) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or coincident.
Write Enable 1 (WEN1}-1f the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of anyon-going read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FI Fa is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go high after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) is
ignored when the FIFO is full.
Read Clock (RCLK) - Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (EF) and Programmable Almost-Empty Flag (PAE)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or coincident.
Read Enables (REN}-When the Read Enable (REN) is
LOW, data is read from the RAM array to the output register
on the LOW-to-HIGH transition of the read clock (RCLK).
When the Read Enable (REN) is HIGH, the output register
holds the previous data and no new data is allowed to be
loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a vali~write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enable (REN) is ignored when the FIFO is empty.
Output Enable (OE)-When Output Enable (OE) is enabled (LOW), the output buffer receives data from the output
register. When Output Enable (OE) is disabled (HIGH), the Q
data output is in a high-impedance state.
Write Enable 21Load (WEN2ILD)-This is a dual-purpose
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows depth expansion. If Write Enable 21Load (WEN2ILD) is set HIGH at Reset
(RS =LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when
Write Enable (WEN1) is LOW and Write Enable 21Load
(WEN2ILD) is HIGH, data can be loaded into the input register
and RAM array on the LOW-to-HIGH transition of every write
clock (WCLK). Data is stored in the RAM array sequentially
and independently of anyon-going read operation.
In this configuration, when Write Enable (WEN1) is HIGH
and/or Write Enable 21Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
TO'prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) and
Write Enable 2/Load (WEN2ILD) are ignored when the FIFO
is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/LD) is set LOW at Reset (RS
= LOW). The IDT72423n2203n2213 devices contain four 8bit offset registers which can be loaded with data on the
Program Inputs (Po - P7). See Figure 3 for details of the size
of the registers and the default values.
If the FI Fa is configured to have programmable flags when
the Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2I
LD) are set LOW, data on the Program Inputs (Po - P7) are
written into the Empty (Least Significant Bit) offset register on
the first LOW-to-HIGH transition of the write clock (WCLK).
Data is written into the Empty (Most Significant Bit) offset
register on the second LOW-to-HIGH transition of the write
clock (WCLK), into the Full (Least Significant Bit) offset
register on the third transition, and into the Full (Most Significant Bit) offset register on the fourth transition. The fifth
transition of the write clock (WCLK) again writes to the Empty
(Least Significant Bit) offset register.
5.04
5
II
I
1DT72423n2203n2213 CMOS SINGLE BIT SyncFlFOTM
64x 1, 256x 1, 512x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
However, writing all offset registers does not have to occur
at one time. One ortwo offset registers can be written and then
by bringing the Write Enable 21Load (WEN2ILD) pin HIGH, the
FIFO is returned to normal read/write operation. When the
Write Enable 21Load (WEN2/LD) pin is set LOW, and Write
Enable 1 (WEN1) is LOW, the next offset register in sequence
is written.
Program Inputs {Po - P7)-Flag offsets on these inputs are
entered into the programmable offset registers on the rising
edge of WCLK when LD and WEN are LOW.
LD
WEN1
WCLK(1)
0
0
S-
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
SS-
1
1
r
Selection
0
Write into FIFO
No Operation
3111 tblOB
Figure 2. Write Offset Register
72423 - 64 x 1-BIT
65
0
Empty Offset (LSB) Reg.
Default Value 007H
72203 - 256 x 1-BIT
r-__T-__________________
72213 - 512 x 1-BIT
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Default Value 007H
IXxxxxxI IXxxxxxI
(LSB) Reg.
Default Value 007H
8 1 0
o
o
Ful~Offset
o
~O
o
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
IXxxxxxllXxxxxxl
Default Value 007H
8 1 0
3111 drw05
Figure 3. Offset Register Location and Default Values'
5.04
6
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 xl, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUTS:
Full Flag (FF)-The Full Flag (FF) will go LOW, inhibiting
further write operation, when the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 64 writes for the I DT72423, 256 writes for the I DT72203,
512 writes for the IDT72213.
The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK).
Empty Flag (EF)-The Empty Flag (EF) will go LOW,
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
Programmable Almost-Full Flag (PAF)-The Programmable Almost-Full Flag (PAF) will go LOW when the FIFO
reaches the Almost-Full condition. If no reads are performed
after Reset (RS), the Programmable Almost-Full Flag (PAF)
will go LOW after (64-m) writes for the IDT72423, (256-m)
writes forthe IDT72203, (512-m) writes forthe IDT72213. The
offset u m" is defined in the Full offset registers.
If there is no Full offset specified, the Programmable
Almost-Full Flag (PAF) will go LOW at Full-7 words.
The Programmable Almost-Full Flag (PAF) is synchronized
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).
Programmable Almost-Empty Flag (PAE)-The Programmable Almost-Empty Flag (PAE) will go LOW when the
read pointer is "n+1" locations less than the write pointer. The
offset "n" is defined in the Empty offset registers. If no reads
are performed after Reset the Programmable Almost-Empty
Flag (PAE) will go HIGH after "n+ 1" for the IDT72423fi2203/
72213. If there is no Empty offset specified, the Programmable Almost-Empty Flag (PAE) will go LOW at Empty+7
words.
The Programmable Almost-Empty Flag (PAE) is synchronized with respect to the LOW-to-HIGH transition of the read
clock (RCLK).
Data Outputs (0) -
Output for serial data.
II
TABLE 1: STATUS FLAGS
NUMBER OF WORDS IN FIFO
72423
72203
72213
FF
PAF
PAE
EF
0
0
0
H
H
H
L
L
L
H
H
L
H
L
H
H
H
H
I
(n+1) to (64-(m+1))
(n+ 1) to (256-(m+ 1))
(n+1) to (512-(m+1))
(64-m)2) to 63
(256-mj2) to 255
(512-mj2) to 511
H
H
H
H
64
256
512
L
1 to n(l)
1 ton(1)
1 to n(l)
3111 tbl09
NOTES:
1. n Empty Offset (n 7 default value)
2. m = Full Offset (m = 7 default value)
=
=
5.04
7
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1,512 x 1
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
~------------ tRS------------~~
----------~-------tRSR--------~
----------~-------tRSR--------~
--------~~------tRSR------~~
WEN2/LD(1)
L-~~wr~~~~--------------------~----------------'
OE
Q
~~~04_~~~~~~~o.....3o.~:Iio.....3o~~~
=1 (2)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
3111 drw05
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2ILD LOW during reset will make the pin act as
a load enable for the programmable flag offset registers.
2. After reset, the outputs will be LOW if OE 0 and tri-state if OE 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
=
=
Figure 4. Reset Timing
5.04
8
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64x1, 256x 1, 512x 1
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
~------------tCLK----------~~
WCLK
D
NO OPERATION
WEN2I
(If Applicable)
NO OPERATION
~------tWFF----~Pi
.------- twFF - - - - P i
tSKEW1(1
RCLK
2655 drw07
NOTE:
1. tSKEWl is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 5. Write Cycle Timing
5.04
9
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~------------tCLK----------~~
RCLK
NO OPERATION
~------
tREF
Q
tSKEW1(1)
WCLK
,,~--------------------------------WEN2
------/
2655 drw 08
Note:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK ~e for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle
·Timing
Figure 6. Read Cycle Timing
5.04
10
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64x 1, 256x 1, 512 x1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
o
WEN1
WEN2
(If Applicable)
t------- tFRL (11-_ _--I~
RCLK
EF
tA
Q
Do
01
tOLZ
____________________________,
~~----------tOE----~
2655 drw09
Note:
1. When tSKEW1 ~ minimum specification, tFRl =tClK + tSKEW1
When tSKEW1 < minimum specification, tFRl =2tClK + tSKEW1 or tClK + tSKEW1
The Latency Timings apply only at the Empty Boundary (8= =LOW).
Figure 7. First Data Word Latency Timing
5.04
11
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
D
FF
WEN2
(If Applicable)
RCLK
LOW
Q
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
2655 drw 10
Figure 8. Full Flag Timing
5.04
12
IDn2423n2203n2213 CMOS SINGLE BIT SyncFlFOTM
64 x 1, 256 x 1, 512 x 1
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
D
WEN2
(If Applicable)
(1)
t--------- tFFL (_1)______---t~
~------------tFRL------~
RCLK
II
EF
LOW
Q
_ _~1:,........___=1<
DATA IN OUTPUT REGISTER
DATA READ
2655 drw
11
Note:
1. When tSKEW1 ~ minimum specification, tFRL maximum tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at at the Empty Boundary (EF LOW).
=
=
=
Figure 9. Empty Flag Timing
5.04
13
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1, 512 X 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tENS~
r-;tENH
WEN2
(If Applicable.~_ _ _~.-r.....-r.....J
tPAF
(1)
Full - m words in FIFO(2)
Full- (m+1) words in FIFO
PAF
RCLK
2655 drw 12
NOTES:
1. PAF offset m.
2. 64 - m words in for IDT72423, 256 - m words in FIFO for IDT72203, 512 - m words for IDT72213.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK riSing edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FI Fa when PAF goes LOW.
=
Figure 10. Programmable Full Flag Timing
5.04
14
IDT72423n2203n2213 CMOS SINGLE BIT SyncFlFOTM
64 x " 256 X " 512 X 1
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
WEN2
(If Applicable),_ _ _ _-L-L-£..../
(1)
PAE
n+1 words in FIFO
n words in FIFO
RCLK
I
II
2655 drw 13
NOTES:
1. PAE offset =n.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing
WCLK
LD
WEN1
Po - P7
2655 drw 14
Figure 12. Write Offset Registers Timing
5.04
15
IDT72423n2203n2213 CMOS SINGLE BIT SyncFIFOTM
64 x 1, 256 x 1, 512 x 1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
are for 64/256/512 bits or less. In this configuration, the Write
Enable 2/Load (WEN2/LD) pin is set LOW at Reset so that the
pin operates as a control to load and read the programmable
flag offsets.
SINGLE DEVICE CONFIGURATION-A single IDT724231
72203n2213 may be used when the application re,quirements
RESET (RS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
WRITE ENABLE 1 (WEN1)
READ ENABLE (REN)
lOT
72423/
72203/
72213
WRITE ENABLE 2/LOAD (WEN2/LD)
DATA IN (D)
OUTPUT ENABLE (bE)
DATA OUT (Q)
FULL FLAG (FF)
EMPTY FLAGjEi:)
PROGRAMMABLE (PAF)
PROGRAM INPUTS (Po - P7)
PROGRAMMABLE (PAE)
.
3111 drw1S
'---
Figure 14. Block Diagram of Single 64 x 1/256 x 1/512 x 1 Synchronous FIFO
DEPTH EXPANSION-The IDT72423n2203n2213 can
be adapted to applications when the requirements are for
greater than 64/256/512 words. The existence of two enable
pins on the write port facilitates depth expansion. The Write
Enable 21Load pin is used as a second write enable in a depth
expansion configuration thus the Programmable flags are set
to the default values. Two read enables can be created by
adding a two-input AND gate to the REN line of the FIFO.
Depth expansion is possible by using one enable input for
system control while the other enable input is controlled by
expansion logic to direct the flow of data. A typical application
would have the expansion logic alternate data access from
one device to the next in a sequential manner. The IDT724231
72203n2213 operates in the Depth Expansion configuration
when the following conditions are met:
1. The WEN2/LD pin is held HIGH during Reset so that this
pin operates a second Write Enable.
2.An external two-input AND gate is used to create two
read enables, REN1 and REN2. The output of the AND
gate is tied to the REN pin of the FIFO device, one input
of the AND gate is designated REN1, the other REN2.
3. External logic is used to control the flow of data.
Please see the Application Note "Depth Expansion of IDT's
Synchronous FIFOs Using the Ring Counter Approach" for
details of this configuration.
ORDERING INFORMATION
lOT
XXXXX
_X_
XX
_ _X_
Device Type
Power
Speed
Package
X
Process/
Temperature
Range
I~
I BBLANK
TP
' - - - - - - - - - - i TO
SO
'--_____________
~
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ;
'------------------------l
5.04
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Plastic Thin DIP (300 mils wide)
Ceramic Thin DIP (300 mils wide)
Small Outline IC
15
25
Com'\. Only
Com'\. Only
Com'l and Mil.
Mi\.Only
L
Low Power
72423
72203
72213
64 x 1 Synchronous FIFO
256 x 1 Synchronous FIFO
512 x 1 Synchronous FIFO
10
12
}
Clock Cycle Time (tCLK)
Speed in Nanoseconds
3111drw18
16
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
CMOS SyncFIFOTM
64 x 8, 256 x 8, 512 x 8,
1024 x 8,2048 x 8 and 4096 x 8
(;5
Integrated Device Technology, Inc.
SyncFIFOTM are very high-speed, low-power First-In, FirstOut (FIFO) memories with clocked read and write controls.
The IOT72420/7220017221 0/72220172230172240 have a 64,
256,512, 1024,2048, and 4096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data
buffering needs, such as graphics, Local Area Networks
(LANs), and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a write
enable pin (WEN). Data is written into the Synchronous FIFO
on every clock when WEN is asserted. The output port is
controlled by another clock pin (RCLK) and a read enable pin
(REN). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
These Synchronous FI FOs have two end-pointflags, Empty
(EF) and Full (FF). Two partial flags, Almost-Empty (AE) and
Almost-Full (AF), are provided for improved system control.
The partial (AE) flags are set to Empty+ 7 and Full-7 for AE and
AF respectively.
The IOT72420/7220017221 0172220/72230/72240 are fabricated using lOT's high-speed submicron CMOS technology.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 X 8-bit organization (IOT72420)
256 x 8-bit organization (10T72200)
512 x 8-bit organization (IOT72210)
1024 x 8-bit organization (IOT72220)
2048 x 8-bit organization (IOT72230)
4096 x 8-bit organization (IOT72240)
12 ns read/write cycle time (IOT7242017220017221 0)
15 ns read/write cycle time (IOT72220172230172240)
Read and write clocks can be asynchronous or
coincidental
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Almost-empty and almost-full flags set to Empty+7 and
Full-7, respectively
Output enable puts output data bus in high-impedance
state
Produced with advanced submicron CMOS technology
Available in 28-pin 300 mil plastic DIP and 300 mil
ceramic DIP
For surface mount product please see the IOT72421/
72201172211172221/72231172241 data sheet
Military product compliant to MIL-STO-883, Class B
DESCRIPTION:
Th e I OT72420/72200/7221 0/72220/72230/72240
FUNCTIONAL BLOCK DIAGRAM
DO - 07
WCLK
WEN
I--_EF
FLAG
LOGIC
~
RESET LOGIC
t
____
~
I----AE
1 - - -.... AF
____
~--~FF
I
RCLK
RS
The lOT logo is a registered trademark and
SyncFIFO is a trademark of Integrated Device Technology. Inc.
00-07
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2680 drw 01
AUGUST 1993
oSC-203914
©1995 Integrated Device Technology, Inc.
5.05
1
IDT72420n2200n2210n2220n2230n2240 CMOS SyncFIFOTM
64 X 8,256 X 8, 512 X 8,1024 X 8,2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
04
28
05
27
06
03
2
02
3
26
07
01
4
25
RS
DO
5
24
WEN
AF
6
23
WCLK
AE
7
22
VCC
GND
8
21
07
RCLK
9
20
06
10
19
05
OE
11
18
04
EF
12
17
03
FF
13
16
02
00
14
15
01
REN
P28-2
C28-1
DIP TOP
VIEW
2680 drw 02
PIN DESCRIPTIONS
Symbol
Do - 07
Name
Data Inputs
RS
VO
Description
I
Data inputs for a 8-bit bus.
Reset
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM
array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE
after power-up.
WCLK
Write Clock
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted.
WEN
Write Enable
I
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
Data will not be written into the FIFO if the FF is LOW.
00- 07
Data Outputs
0
Data outputs for a 8-bit bus.
RCLK
Read Clock
I
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
REN
Read Enable
I
When RENis LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
OE
Output Enable
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
EF
Empty Flag
0
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited., When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
AE
Almost-Empty
Flag
0
When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized
to RCLK.
AF
Almost-Full Flag
0
When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to
WCLK.
FF
Full Flag
a
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
Vee
Power
One +5 volt power supply pin.
GND
Ground
One 0 volt ground pin.
high-impedance state.
2680 Ibl 01
5.05
2
1DT72420n2200n2210n2220n2230n2240 CMOS SyncFIFOTM
64 X 8,256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TA
Rating
Commercial
RECOMMENDED OPERATING CONDITIONS
Military
Unit
Terminal Voltage -0.5 to + 7.0 -0.5 to + 7.0
with Respect to
GND
Operating
Temperature
a to + 70
-55 to + 125
°C
TSIAS
Temperature
Under Bias
-55 to + 125 -65 to + 135
°C
TSTG
Storage
Temperature
-55 to + 125 -65 to + 135
°C
lOUT
DC Output
Current
50
50
Symbol
V
mA
Parameter
VCCM
Military Supply Voltage
Vccc
Commercial Supply
Voltage
Min.
Typ.
Max.
Unit
4.5
4.5
5.0
5.0
5.5
5.5
V
a
V
GND
Supply Voltage
a
a
V
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
VIL
Input Low Voltage
Commercial & Military
-
-
0.8
V
2680 tbl 03
2680 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposureto absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE (TA =+2S0C, f = 1.0 MHz)
Symbol
Parameter
CIN(2)
Input Capacitance
COUT(1.2) Output Capacitance
Conditions
Max.
VIN= OV
10
pF
VOUT=OV
10
pF
NOTES:
1. With output deselected. COE HIGH)
2. Characterized values. not currently tested.
Unit
2680 tbl 04
=
DC ELECTRICAL CHARACTERISTICS
Commercial: Vcc
Symbol
=SV + 10%, TA =O°C to +70°C; Military:
Parameter
Vcc
II
=SV + 10%, TA =-SsoC to +12S°C)
IDT72420
IDT72200
IDT72210
IDT72420
IDT72200
IDT72210
Commercial
tCLK = 12,15,20,25,35,50 ns
Min.
Typ.
Max.
Military
tCLK = 20, 25,35, 50 ns
Min.
Typ.
Max.
IU(l)
Input Leakage Current (any input)
ILO(2)
Output Leakage Current
VOH
Output Logic "1" Voltage, IOH
=-2 mA
2.4
VOL
Output Logic "0" Voltage, IOL
=8 mA
ICC1(3)
Active Power Supply Current
-
-1
-10
-
1
-10
10
-10
-
2.4
0.4
-
140
Units
-
-
V
0.4
V
-
160
mA
10
MA
10
MA
2680 tbl 05
IDT72220
IDT72230
IDT72240
IDT72220
IDT72230
IDT72240
Military
Commercial
Symbol
tCLK
Min.
Parameter
IU(l)
Input Leakage Current (any input)
ILO(2)
Output Leakage Current
-1
-10
=-2 mA
VOH
Output Logic "1" Voltage, IOH
VOL
Output Logic "0" Voltage, IOL =8 mA
ICC1(4)
Active Power Supply Current
2.4
-
=15, 20, 25, 35, 50 ns
Typ.
-
NOTES:
1. Measurements with 0.4 ::; VIN ::; Vcc.
2. OE;:: VIH, 0.4::; VOUT ::; Vcc.
3 & 4.
Measurements are made with outputs open. Tested at fClK =20 MHz.
(3) Typicallccl = 65 + (fClK * 1.1/MHz) + (fClK * Cl * 0.03/MHz-pF) mA
(4) Typicallccl = 80 + (fClK * 2.1/MHz) + (fClK * Cl * 0.03/MHz-pF) mA
fClK 1 / tClK
Cl external capacitive load (30 pF typical)
Max.
tCLK
Min.
=25, 35, 50 ns
Typ.
Max.
Units
-
10
MA
10
MA
1
-10
10
-10
-
2.4
-
-
V
0.4
-
-
0.4
V
180
mA
160
2680 tbl 06
=
=
5.05
3
IDT72420n2200n2210n222on2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8,2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V ± 10%, TA = O°C to + 70°C; Military: Vcc = 5V ± 10%, TA = -55°C to +125°C)
Commercial
Commercial & Military
72200L12 72200L15 72200L20 72200L25
72210L12 72210L15 72210L20 72210L25
72420L12 72420L15 72420L20 72420L25
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
fS
Clock Cycle Frequency
-
tA
Data Access Time
tCLK
Clock Cycle Time
tCLKH
Clock High Time
tCLKL
Clock .Low Time
lOS
Data Set-up Time
lOH
Data Hold Time
tENS
Enable Set-up Time
tENH
Enable Hold Time
tRS
Reset Pulse Width(l)
tRSS
Reset Set-up Time
tRSR
Reset Recovery Time
tRSF
Reset to Flag and Output Time
2
12
5
::.::"
5
3
0.5
3 :~(
0.5 i,iJ2:
12 ,i,"::;;'"
12;!;;L
12 ',"i_-:<';;;;'12
tOLZ
Output Enable to Output in LOW-Z(2)
0'::",':'-
tOE
Output Enable to Output Valid
3
tOHZ
Output Enable to Output in High-Z(2)
tWFF
Write Clock to Full Flag
tREF
Read Clock to Empty Flag
tAF
Write Clock to Almost-Full Flag
tAE
Read Clock to Almost-Empty Flag
tSKEW1
Skew time between Read Clock &
Write Clock for Empty Flag & Full Flag
tSKEW2 Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full Flag
72200L35 72200L50
72210L35 72210L50
72420L35 72420L50
83.3
-
66.7
10
2
8 '
1'15 ~;!i
6 6
-
4
1
4
1
15
15
15
-
-
2
20
8
8
5
1
5
1
20
20
20
-
15
0
3
3
-
-:'
~:l
7
·3".' 7
..
...
8
.
8
8
P;"'t- 8
22
-
13
13
15
15
15
15
-
10
-
-
40
-
42
-
3
25
10
10
-
-
-
6
-
-
1
25
25
25
-
20
-
25
0
3
3
-
0
3
3
-
-
8
-
28
-
35
-
-
10
10
12
12
12
12
-
-
28.6
3 20
35 14 14 8 2 8 2 35 35 35 - 35
0 3 15
3 15
- 20
- 20
- 20
- 20
12 -
1
6
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
40
15
-
-
-
.:.~
-
6
-
-
50
12
-
8
8
10
10
10
10
~
li,',:,5
-
-
-
-
-
-
Min.Max. Unit
-
20
3 25
50 20 20 10 2 10 2 50 50 50 - 50
0 3 28
3 28
- 30
- 30
- 30
- 30
15 45
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2680 tbl 07
5.05
4
1DT72420n2200n2210n2220n2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8,2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc
=5V ± 10%, TA =O°C to + 70°C; Military:
Vcc
=5V ± 10%, TA =-55°C to +125°C)
Commercial
72220L15
72230L15
72240L15
Symbol
Parameter
Commercial & Military
72220L20
72230L20
72240L20
Min. Max. Min. Max.
72220L25 72220L35
72230L25 72230L35
72240L25 72240L35
72220L50
72230L50
72240L50
Min. Max. Min. Max. Min.
fs
Clock Cycle Frequency
-
66.7
-
50
-
40
tA
Data Access Time
2
10
2
12
3
tClK
Clock Cycle Time
15
20
25
5
-
1
-
20
Max.
Unit
-
20
MHz
20
3
25
ns
-
50
ns
10
-
2
-
ns
50
ns
-
50
-
35
-
50
ns
-
28.6
15
3
-
35
10
-
14
10
-
14
6
-
8
2
-
6 1 25 -
35
20
-
25
-
35
-
20
-
25
-
35
-
20
-
25
-
tClKH
Clock High Time
6
tClKl
Clock Low Time
6
tDS
Data Set-up Time
4
tDH
Data Hold Time
1
tENS
Enable Set-up Time
4
tENH
Enable Hold Time
1
tRS
Reset Pulse Width(l)
15
tRSS
Reset Set-up Time
15
tRSR
Reset Recovery Time
15
-
tRSF
Reset to Flag and Output Time
-
15
tOLZ
Output Enable to Output in Low-Z(2)
0
-
0
-
0
-
0
-
0
-
ns
tOE
Output Enable to Output Valid
3
8
3
10
3
13
3
15
3
23
ns
8
8
5
1
1
8
2
20
20
10
2
50
ns
ns
ns
ns
ns
ns
ns
tOHZ
Output Enable to Output in High-Z(2)
3
8
3
10
3
13
3
15
3
23
ns
tWFF
Write Clock to Full Flag
-
10
-
12
15
-
20
30
ns
30
ns
30
ns
tAE
Read Clock to Almost-Empty Flag
10
-
12
-
15
-
20
-
30
ns
tSKEWl
Skew time between Read Clock & Write Clock
for Empty Flag & Full Flag
6
-
8
-
10
-
12
-
15
-
ns
tSKEW2
Skew time between Read Clock & Write Clock
for Almost-Empty Flag & Almost-Full Flag
28
-
35
-
40
-
42
-
45
-
ns
tREF
Read Clock to Empty Flag
-
10
-
12
tAF
Write Clock to Almost-Full Flag
-
10
12
15
15
20
20
NOTES:
2680 tbJ 08
SV
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
1.1KO
AC TEST CONDITIONS
Input Pulse Levels
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
D.U.T. - - - - - . . . . - - - - - - .
GND to 3.0V
Input Rise/Fall Times
6800
30pF*
1.5V
See Figure 1
2680 tbJ 09
2680 drw 03
or equivalent circuit
Figure 1. Output Load
'Includes jig and scope capacitances.
5.05
5
11
IDT72420n2200n2210n222on2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
Data In (00-07) -
Output Enable (OE) - When Output Enable (OE) is enabled
(L~W), the parallel output buffers receive data from the output
register. When Output Enable (OE) is disabled (HIGH), the
Q output data bus is in a high-impedance state.
Data inputs for 8-bit wide data.
CONTROLS:
Reset (RS) - Reset is accomplished whenever the Reset
(RS) input is taken to a LOW state. During reset, both internal
read and write pOinters are set to the first location. A reset is
required after power up before a write operation can take
place. The Full Flag (FF) and Almost Full Flag (AF) will be reset
to HIGH after tRSF. The Empty Flag (EF) and Almost Empty
Flag (AE) will be reset to LOW after tRSF. During reset, the
output register is initialized to all zeros.
Write Clock (WCLK) - A write cycle is initiated on the LOWto-HIGH transition of the write clock (WCLK). Data set-up and
hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Almost Full Flag (AF) are synchronized with respect to the
LOW-to-HIGH transition of the write clock (WCLK).
The write and read clocks can be asynchronous or coincident.
Write Enable (WEN) - When Write Enable (WEN) is LOW,
data can be loaded into the input register and RAM array on
the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in t!1e RAM array sequentially and independently of anyon-going read operation.
When Write Enable (WEN) is HIGH, the input register holds
the previous data and no new data is allowed to be loaded into
the register.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable (WEN) is ignored
when the FIFO is full.
Read Clock (RCLK) --:- Data can be read on the outputs on the
LOW-to-HIGH transition of the read clock (RCLK). The Empty
Flag (~F) and Almost-Empty Flag (AE) are synchronized with
respect to the LOW-to-HIGH transition of the read clock
(RCLK).
The write and read clocks can be asynchronous or coincident.
OUTPUTS:
Full Flag (FF) - The Full Flag (FF) will go LOW, inhibiting
further write operation, when the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 64 writes for the IDT72420, 256 writes forthe IDT72200,
512 writes for the IDT72210, 1024 writes for the IDT72220,
2048 writes forthe IDT72230, and 4096 writes forthe IDT72240.
The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK).
Empty Flag (EF) - The Empty Flag (EF) will go LOW,
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
Almost Full Flag (AF) - The Almost Full Flag (AF) will go
LOW when the FIFO reaches the Almost-Full condition. If no
reads are performed after Reset (RS), the Almost Full Flag
(AF) will go LOW after 57 writes for the IDT72420, 249 writes
for the IDT72200, 505 writes for the IDT7221 0, 1017 writes for
the IDT72220, 2041 writes for the IDT72230 and 4089 writes
for the IDT72240.
The Almost Full Flag (AF) is synchronized with respect to
the LOW-to-HIGH transition of the write clock (WCLK).
Almost Empty Flag (AE) - The Almost Empty Flag (AE) will
go LOW when the FIFO reaches the Almost-Empty condition.
If no reads are performed after Reset (RS), the Almost Empty
Flag (AE) will go HIGH after 8 writes for the IDT72420,
IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240.
The Almost Empty Flag (AE) is synchronized with respect
to the LOW-to-HIGH transition of the read clock (RCLK).
Data Outputs (00-07) -
Data outputs for a 8-bit wide data.
Read Enable (REN) - When Read Enable (REN) is LOW,
data is read from the RAM array to the output register on the
LOW-to-HIGH transition of the read clock (RCLK).
When Read Enable (REN) is HIGH, the output register
holds the previous data and no new data is allowed to be
loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a vali~write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
Read Enable (REN) is ignored when the FIFO is empty.
5.05
6
IDT72420n2200n2210n2220n2230n2240 CMOS SyncFIFOTM
64 X 8,256 X 8, 512 X 8,1024 X 8,2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 1: STATUS FLAGS
Number of Words in FIFO
10172420
10172200
10172210
10172220
10172230
10172240
FF
AF
AE
0
0
0
0
0
0
H
H
L
L
1 to 7
1 to 7
1 to 7
1 to 7
1 to 7
1 t07
H
H
L
H
8 to 1016
8 to 2040
8 to 4088
H
H
H
H
H
L
H
H
L
L
H
8 to 56
8 to 248
8 to 504
57to 63
249 to 255
505 to 511
64
256
512
1017 to 1023 2041 to 2047 4089 to 4095
1024
2048
4096
EF
H
2680 tbll0
~------------ tRS------------~~
--------~._-----tRSR------~*
I
II
--------~._-----tRSR------~~
I
00- Q7
2680 drw 04
NOTE:
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 2. Reset Timing
5.05
7
IDT72420n2200n2210n222on2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
tCLK -------I~
WCLK
00- 07
NO OPERATION
tWFF - - - - l....
tWFF----l-.
RCLK
_____---J/
2680 drw 05
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK ed~ for FF to change during the curent clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 3. Write Cycle Timing
5.05
8
IDT72420n2200n2210n222on2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8,2048 X 8 and 4096 X 8
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
tCLK -------t~
tCLKL
NO OPERATION
tREF
00 - OJ
VALID DATA
tOHZ
II
OE
tSKEW1(1)
WCLK
WEN
,,~--------------------------------2680 dIW06
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the curent clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 4. Read Cycle Timing
5.05
9
IDT72420n2200n2210n2220172230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
00- D7
RCLK
tA
Qo- 07
00
01
toLZ
~1-----tOE
---------------~
NOTE:
1. When tSKEW1 ~ minimum specification, tFRl maximum tClK + tSKEW1
tSKEW1 < minimum specification, tFRl maximum 2tClK + tSKEW1 or tClK + tSKEW1
The Latency Timing apply only at the Empty Boundry (8= LOW).
=
=
2680 drw 07
=
Figure 5. First Data Word Latency Timing
5.05
10
1DT72420n2200n2210n222on2230n2240 CMOS SyncFIFOTM
64 X 8,256 X 8,512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
Do- 07
RCLK
LOW
00 - 07
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2680 drw08
Figure 6. Full Flag Timing
5.05
11
IDT72420n2200n2210n2220n2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS~
tDS~
Do- D7
RCLK
OE
Qo- Q7
LOW
_
_ _"--?J
-.Ji' _ __
DATA IN OUTPUT REGISTER
DATA READ
NOTE:
1. When tSKEWl ~ minimum specification, tFRL maximum tCLK + tSKEWl
tSKEWl < minimum specification, tFRL maximum 2tCLK + tSKEWl or tCLK + tSKEWl
The Latency Timing apply only at the Empty Boundry (EF LOW).
=
=
2680 drw 09
=
Figure 7. Empty Flag Timing
5.05
12
IDTI2420n2200n2210n222Dn2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tAF
Full - 7 words in FIFO
Full - 8 words in FIFO
tSKEW2
(1)
tAF
RCLK
2680 drw 10
NOTES:
1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the curent clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge.
2. If a write is performed on this riSing edge of the write clock, there will be Full - 6 words in the FIFO when AF goes LOW.
Figure 8. Almost Full Flag Timing
5.05
13
IDT72420n2200n2210n222on2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8,2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
Empty+8
Empty+7
tSKEWi
tAE
1)
tAE
RCLK
NOTES:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the curent clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge.
2. If a read is perfonned on this rising edge of the read clock, there will be Empty - 6 words in the FIFO when AE goes LOW.
Figure 9. Almost Empty Flag Timing
5.05
14
IDT72420n2200n2210n2220n2230n2240 CMOS SyncFIFOTM
64 X 8, 256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION - A single IOT724201
72200/72210172220/72230172240 may be used when the
applicationrequirementsarefor64/256/512/1024/2048/4096
words or less. See Figure 10.
~
RESET (RS)
..-
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
DATA IN (DJ-D7)
-
IDT
724201722001
722101
722201
722301
.......
........
--..
--
OUTPUT ENABLE (OE)
......
........
-
EMPTY FLAG (EF)
ALMOST FULL (AF)
....
READ ENABLE (REN)
DATA OUT (OJ- 07)
72240
FULL FLAG (FF)
READ CLOCK (RCLK)
ALMOST EMPTY(AE)
-
2680 drw 12
Figure 10. Block Diagram of Single 64 x 8/256 x 8/512 x 8/1024 x 8/2048 x 8/4096 x 8 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION - Word width may
be increased simply by connecting the corresponding input
control signals of multiple devices. A composite flag should be
created for each of the end-point status flags (EF and FF) The
partial status flags (AE and AF) can be detected from anyone
device. Figure 11 demonstrates a 16-bit word width by using
twoIOT72420172200/72210/72220172230172240s. Anyword
width can be attained by adding additional IOT724201722001
72210/72220/72230172240s.
RESET (RS)
RESET (RS)
1,
1,
DATA IN (D)
/ 16
t
I!
I WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
:
..... ALMOST FULL (AF)
JULL FLAG (FF) #1
DULL FLAG (FF) #2
......
-----------------IDT
724201
722001
722101
722201
722301
72240
It..
--
I
-
-
-..
-
~-
--....
-----------------IDT
724201
722001
722101
722201
722301
I 8
I
72240
--
--
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
-..
ALMOST EMPTY (AE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
II
8
:1
DATA OUT (0)
,16
7
I
2680 drw 13
Figure 11. Block Diagram of 64 x 16/256 x 16/512 x 16/1024 x 16/2048 x 16/4096 x 16 Synchronous FIFO
Used in a Width Expansion Configuration
5.05
15
IDT72420n2200n2210n2220n2230n2240 CMOS SyncFIFOTM
64 X 8,256 X 8, 512 X 8,1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION - The IDT724201722001722101722201
72230172240 can be adapted to applications when the requirements are for greater than 64/256/51211024/2048/4096
words. Depth expansion is possible by using expansion logic
to direct the flow of data. A typical application would have the
expansion logic alternate data accesses from one device to
the next in a sequential manner.
Please see the Application Note "DEPTH EXPANSION
lOT'S SYNCHRONOUS FIFOs USING RING COUNTER
APPROACH" for details of this configuration.
ORDERING INFORMATION
IDT
XXXXX
Device
Type
x
XX
XX
Power Speed Package
X
Process /
Temperature
Range
~ ~LANK
I TP
Plastic THINDIP
Sidebraze THINDIP
l TC
'---------i
L----------------i
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
12
15
20
25
35
50
Com'\. (72420172200172210) Only
}
Com'\. Only
All except 72220172230172240 Military
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Low Power
L
72420
72200
72210
72220
72230
72240
5.05
64 X 8 Synchronous FIFO
256 x 8 Synchronous FIFO
512 x 8 Synchronous FIFO
1024 x 8 Synchronous FIFO
2048 x 8 Synchronous FIFO
4098 x 8 Synchronous FIFO
2680 drw 14
16
G@
IDT72421
IDT72201
IDT72211
IDT72221
IDT72231
IDT72241
CMOS SyncFIFOTM
64 X 9, 256 x 9, 512 x 9,
1024 X 9, 2048 X 9 and 4096 x 9
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 X 9-bit organization (IDT72421)
256 x 9-bit organization (IDT72201)
512 x 9-bit organization (IDT72211)
1024 x 9-bit organization (IDT72221)
2048 x 9-bit organization (IDT72231)
4096 x 9-bit organization (IDT72241)
12 ns read/write cycle time (IDT72421172201172211)
15 ns read/write cycle time (IDT72221172231172241)
Read and write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can
be set to any depth
Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance
state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC) and
ceramic leadless chip carrier (LCC)
For Through-Hole product please see the IDT72420/
72200/72210/72220/72230/72240 data sheet
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The I DT72421 /72201 /72211 /72221 /72231 /72241
SyncFIFOTM are very high-speed, low-power First-In, First-
FUNCTIONAL BLOCK DIAGRAM
WCLK
Out (FIFO) memories with clocked read and write controls.
The IDT72421/72201/72211172221/72231/72241 have a 64,
256, 512, 1024, 2048, and 4096 x 9-bit memory array,
respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks
and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and two
write enable pins (WEN1, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (REN1,
REN2). The read clock can be tied to the write clock for single
clock operation orthe two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF). Two programmable flags, Almost-Empty (PAE)
and Almost-Full (PAF), are provided for improved system
control. The programmable flags default to Empty+7 and Full7forPAEand PAF, respectively. The programmable flag offset
loading is controlled by a simple state machine and is initiated
by asserting the load pin (LD).
The IDT72421/72201/72211/72221/72231/72241 are
fabricated using lOT's high-speed submicron CMOS
technology. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B.
Do - Ds
WEN1
WEN2
EF
PAE
PAF
- -....-_.a..-__ Fi=
RAM ARRAY
64 X 9, 256 x 9,
512 X 9,1024 X 9,
2048 X 9,4096 X 9
RCLK
REN1
REN2
SyncFIFO is a trademark and
the lOT logo is a registered trademark of Integrated Device Technology, Inc.
Oo-Os
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2655drwOl
AUGUST 1993
DSC-204014
©1995 Integrated Device Technology, Inc
5.06
1
1DT72421n2201n2211n2221n2231n2241 CMOS SyncFIFOTM
64 x 9, 256 x 9,512 x 9,1024 x 9,2048 x 9 and 4096 x 9
PIN CONFIGURATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
"1111
II
II
IU"L.J
L.JL.JL.JiIW'
4
3
-1
2
32 31 30
1
29
RS
WEN1
WCLK
J32-1
L32-1
WEN2ILD
Vee
Oa
LCC/PLCC
07
06
TOP VIEW
05
Itt Itt
aa a 8 a
2655 dow 02
PIN DESCRIPTIONS
Symbol
Name
Description
I/O
Do-Da
RS
Data Inputs
Reset
I
I
WCLK
Write Clock
I
WEN1
Write Enable 1
I
WEN2/LD
Write Enable 2/
Load
I
Oo-Oa
Data Outputs
0
RCLK
Read Clock
I
REN1
Read Enable 1
I
REN2
Read Enable 2
I
OE
Output Enable
I
EF
Empty Flag
0
PAE
0
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO.
The default offset at reset is Empty+7. PAE is synchronized to RCLK.
0
FF
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
Full Flag
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The
default offset at reset is Full-7. PAF is synchronized to WCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FFis
HIGH, the FIFO is not full. FF is synchronized to WCLK.
Vee
Power
One +5 volt power supply pin.
GND
Ground
One 0 volt ground pin.
PAF
0
Data inputs for a 9-bit bus.
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after
power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write
Enable(s)are asserted.
If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin.
When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If
the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW.
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset,
this pin operates as a control to load and read the programmable flag offsets. If the FIFO is
configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write
data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2ILD is held LOW to write or read the programmable flag
offsets.
Data outputs for a 9-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are
asserted.
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition
of RCLK. Data will not be read from the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
When EF is LOW, the FIFO is empty~nd further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
26551bl01
5.06
2
1DT72421n2201n2211n2221n2231n2241 CMOS SyncFIFOTM
64 x 9, 256 x 9, 512 x 9,1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(l)
Symbol
VTERM
Rating
Commercial
Military
Terminal Voltage -0.5 to +7.0
with Respect to
GND
-0.5 to +7.0
Unit
o to +70
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +135
°C
lOUT
DC Output
Current
50
50
mA
-55 to +125
Parameter
Min.
Typ.
Max.
Unit
VCCM
Military Supply Voltage
4.5
5.0
5.5
V
Vccc
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
VIL
Input Low Voltage
Commercial & Military
-
-
O.S
V
V
Operating
Temperature
TA
Symbol
°C
0
0
0
V
2655 tbl 03
C APACITANCE
2655 tbl 02
NOTE:
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthe specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(TA = +25°C, f = 1.0MHz)
Parameter
Conditions
Max.
Symbol
CIN(2)
Input Capacitance
COUT(1,2)
Output Capacitance
Unit
VIN = OV
10
pF
VOUT= OV
10
pF
2655 tbl 04
NOTES:
1. With output deselected (OE HIGH).
2. Characterized values, not currently tested.
=
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V
± 10%, TA
Symbol
= O°C to +70°C; Military: Vcc = 5V
Parameter
± 10%, TA=
-55°C to +12S°C)
IDT72421
IDT72201
IDT72211
Commercial
tCLK = 12, 15,20,25,35, SOns
Min.
Typ.
Max.
IDT72421
IDT72201
IDT72211
Military
tCLK = 20, 25,35, SOns
Min.
Typ.
Max.
Unit
IU(l)
Input Leakage Current (Any Input)
-10
-
10
IlA
Output Leakage Current
-10
-
-1
ILd2)
10
-10
-
10
IlA
VOH
Output Logic "1" Voltage, 10H = -2mA
2.4
-
-
2.4
-
VOL
Output Logic "0" Voltage, 10L = SmA
0.4
-
Active Power Supply Current
-
-
Icd 3 )
-
140
-
-
-1
V
0.4
V
160
mA
2655 tbl 05
Symbol
Parameter
IDT72221
IDT72231
IDT72241
Commercial
tCLK = 15, 20, 25, 35, SOns
Min.
Typ.
Max.
-
IDT72221
IDT72231
IDT72241
Military
tCLK 25, 35, SOns
Min.
Typ.
Max.
=
lu(1)
Input Leakage Current (Any Input)
ILO(2)
Output Leakage Current
-10
VOH
Output Logic "1" Voltage, 10H
2.4
VOL
=-2mA
Output Logic "0" Voltage, 10L =SmA
-
-
Active Power Supply Current
-
-
0.4
ICC1(4)
160
-
-1
NOTES:
1. Measurements with 0.4 :::; VIN :::; Vcc.
2. OE 63 bytes, tCLK = 20ns.
2. Valid for programmable PAE or PAF values S 63 bytes from respective boundary. With programmable PAE or PAF values> 63 bytes, tCLK= 20ns.
3. Pulse widths less than minimum values are not allowed.
4 .• Values guaranteed by design, not currently tested.
5.06
4
1DT72421n2201n2211n2221n2231n2241 CMOS SyncFIFOTM
64 x 9,256 x 9, 512 x 9,1024 x 9, 2048 x 9 and 4096 x 9
MIUTARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Commercial: Vcc
=5V + 10%, TA =O°C to +70°C; Military:
=
vcc 5V + 10%, TA
Commercial
72221L15
72231L15
72241L15
Symbol
fS
-
66.7
10
tA
Data Access Time
tCLK
Clock Cycle Time
2
15(1)
tCLKH
Clock HIGH Time
6
-
tCLKL
Clock LOW Time
6
-
tDS
Data Set-up Time
-
tDH
Data Hold Time
tENS
Enable Set-up Time
tENH
Enable Hold Time
tRS
Reset Pulse Width(2)
tRSS
Reset Set-up Time
tRSR
Reset Recovery Time
4
1
4
1
15
15
15
tRSF
Reset to Flag Time and Output Time
tOLZ
Output Enable to Output in Low-Z(3)
tOE
Output Enable to Output Valid
to HZ
Output Enable to Output in High-Z(3)
tWFF
Write Clock to Full Flag
tREF
Read Clock to Empty Flag
-
tPAF
Write Clock to Programmable Almost-Full Flag
-
tPAE
Read Clock to Programmable Almost-Empty Flag
tSKEW1
tSKEW2
-
-
2
20
8
8
5
1
5
1
20
20
20
-
15
0
3
3
-
-
-
-
Commercial and Military
72221L20 72221L25
72231L20 72231L25
72241L20 72241L25
Min. Max. Min. Max.
Parameter
Clock Cycle Frequency
=-55°C to +125°C)
50
12
Min. Max Min. Max. Min. Max.
-
-
3
25
10
10
6
1
-
6
-
-
1
25
25
25
-
20
0
3
3
-
-
-
-
-
-
8
8
10
10
10
10
-
10
10
12
12
12
12
Skew Time Between Read Clock and Write Clock
for Empty Flag and Full Flag
6
-
8
Skew Time Between Read Clock and Write Clock
for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag
28
-
35
-
72221L35 72221L50
72231L35 72231L50
72241L35 72241L50
40
15
-
-
3
35
14
14
8
2
8
2
35
35
35
-
25
0
3
3
-
-
-
-
-
13
13
15
15
15
15
-
10
-
40
-
-
28.6
20
-
Unit
20
25
MHz
-
ns
-
ns
-
3
50
20
20
10
2
10
2
50
50
50
-
35
-
50
ns
0
3
3
-
0
3
3
-
ns
-
-
-
-
-
ns
ns
-
ns
-
ns
ns
-
ns
-
ns
-
ns
-
ns
-
15
15
20
20
20
20
-
28
28
30
30
30
30
-
12
-
15
-
ns
-
42
-
45
-
ns
-
-
-
NOTES:
ns
ns
ns
ns
ns
ns
2655 tbl 08
1. Valid for programmable PAE or PAF offset values s; 511 bytes from respective boundary.
With programmable PAE or PAF offset values> 511 bytes, tCLK =20ns.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
1.lK
D.U.T.
680n
AC TEST CONDITIONS
In Pulse Levels
GND to
3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
30pF*
2655 drw03
or equivalent circuit
Figure 1. Output Load
See Figure 1
*Includes jig and scope capacitances.
2655 tbl 09
5.06
5
IDT72421n2201n2211n2221n2231n2241 CMOS SyncFIFOTM
64 x 9,256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
Data In (Do • Os) -
Data inputs for 9-bit wide data.
CONTROLS:
Reset (RS) - Reset is accomplished whenever the Reset
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(PAF) will be resetto HIGH aftertRsF. The Empty Flag (EF) and
Programmable Almost-Empty Flag (PAE) will be reset to LOW
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Write Clock (WCLK) - A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (PAF) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or
coincident.
Write Enable 1 (WEN1) - If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only
enable control pin. In this configuration, when Write Enable 1
(WEN1) is low, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of anyon-going read operatio_n_._
In this configuration, when Write Enable 1 (WEN1) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
_
To prevent data overflOW, the Full Flag (FF) will go LOW,
inhibiting further write operation~ Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) is
ignored when the FIFO is full.
Read Clock (RCLK) - Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (EF) and Programmable Almost-Empty Flag (PAE)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or
coincident.
Read Enables (REN1, REN2) - When both Read Enables
(REN1, REN2) are LOW, data is read from the RAM array to
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).
_ _ __
When either Read Enable (REN1, REN2) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
Output Enable (OE) - When Output Enable (OE) is
enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
Write Enable 21Load (WEN2ILD) - This is a dualpurpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which
allows depth expansion. If Write Enable 21Load (WEN2ILD)
is set high at Reset (RS =LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when
Write Enable (WEN 1) is LOWand Write Enable 21Load (WEN2I
LD) is HIGH, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of anyon-going read operatio_n_._
In this configuration, when Write Enable (WEN1) is HIGH
and/or Write Enable 21Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operation~ Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN 1) and Write
Enable 21Load (WEN2ILD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when
the Write Enable 21Load (WEN2ILD) is set LOW at Reset
(RS=low). The IDT72421 17220 1172211172221172231172241
devices contain four 8-bit offset registers which can be loaded
with data on the inputs, or read on the outputs. See Figure 3
for details of the size of the registers and the default values.
If the FI FO is configured to have programmable flags when
the Write Enable 1 (WEN 1) and Write Enable 21Load (WEN2I
LD) are set low, data on the inputs D is written into the Empty
(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
LOW-to-HIGH transition of the write clock (WCLK), into the
Full (Least Significant Bit) offset register on the third transition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
again writes to the Empty (Least Significant Bit) offset register.
5.06
6
IDT72421n2201n2211n2221n2231n2241 CMOS SyncFIFOTM
64 x 9, 256 x 9, 512 x 9,1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing the Write Enable 21Load (WEN2ILD) pin HIGH, the
FIFO is returned to normal read/write operation. When the
Write Enable 21Load (WEN2ILD) pin is set LOW, and Write
Enable 1 (WEN 1) is LOW, the next offset register in sequence
is written.
The contents of the offset registers can be read on the
output lines when the Write Enable 2/Load (WEN2ILD) pin is
set low and both Read Enables (REN1, REN2) are set LOW.
Data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
A read and write should not be performed simultaneously
to the offset registers.
72421 - 64 x 9-BIT
65
0
Empty Offset (LSB) Reg.
r-__
LD
WEN1
0
0
0
1
1
0
1
1
WCLK(l)
r
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
~
~
~
No Operation
Write Into FIFO
No Operation
NOTE:
2655 drw 04
1. The same selection sequence applies to reading from the registers. REN1
and REN2 are enabled and read is performed on the LOW-to-HIGH
transition of RCLK.
Figure 2. Write Offset Register
72201 - 256 x 9-BIT
,7~
__________________
72211 - 512 x 9-BIT
o
~0
Empty Offset (LSB)
Empty Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Default Value 007H
IXXxxxxI IXXxxxxI
o
r-__
~
=:J
____________________
Full Offset (LSB) Reg.
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
8
1
0
o
~O
Full Offset (LSB)
Default Value 007H
8
1
0
~
72221 - 1024 x 9-BIT
72231 - 2048 x 9-BIT
o
7
72241 - 4096 x 9-BIT
o
7
o
7
Empty Offset (LSB) Reg.
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Default Value 007H
Default Value 007H
1
o
7
7
o
7
Full Offset (LSB) Reg.
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Iw::>a_~:"--~~.....:lII~--300t......J,-1_{M_:....;.OB_)---J1
&ooa-3_-~M-0~-~-)--I1
Full Offset (LSB)
Default Value 007H
1><>oooru~2.-;...(~_~_:..;.,.)
0
3
8
I ~
---I
7
0
Full Offset (LSB) Reg.
0
x9 x2
7
Empty Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Default Value 007H
8
o
7
Full Offset (LSB)
Full Offset (LSB) Reg.
0
(MSB)
0000
I
0
7
Full Offset (LSB)
Default Value 007H
1>ooru_2_(_~_~_:_)---II ~~3_~M_0~_~_)_--11
3034 drw 05
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
5.07
7
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
OUTPUTS:
writes to the 72831 's FIFO A (B), or (4096-m) writes to the
72841's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-toHIGH transition of the write clock WCLKA (WCLKB). The
offset "m" is defined in the Full Offset Registers.
If there is no Full offset specified, PAFA (PAFS) will go LOW
at Full-7 words.
PAFA (PAFB) is synchronized with respect to the LOW-toHIGH transition of the write clock WCLKA (WCLKB).
Full Flag (FFA, FFB) - FFA (FFB) will go LOW, inhibiting
further write operations, when Array A (B) is full. If no reads
are performed after reset, FFA (FFB) will go LOW after 256
writes to the 72801's FIFO A (B), 512 writes to the 72811's
FIFO A (B), 1024 writes to the 72821's FIFO A (B), 2048 writes
to the 72831 's FIFO A (B), or 4096 writes to the 72841's FIFO
A (B).
FFA (FFB) is synchronized with respect to the LOW-toHIGH transition of the write clock WCLKA (WCLKB).
~grammable Almost-Empty Flag (PAEA, PAEB) -
Empty Flag (EFA, EFB) - EFA (EFB) will go LOW,
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating that Array A (B) is empty.
EFA (EFB) is synchronized with respect to the LOW-toHIGH transition of the read clock RCLKA (RCLKB).
Programmable Almost-Full Flag (PAFA, PAFB) - PAFA
(PAFB) will go LOW when the amount of data in Array A (B)
reaches the Almost-Full condition. If no reads are performed
after reset, PAFA (PAFB) will go LOW after (256-m) writes to·
the 72801's FIFO A (B), (512-m) writes to the 72811 's FIFO A
(B), (1024-m) writes to the 72821's FIFO A (B), (2048-m)
PAEA (PAEB) will go LOW when the read pointer is "n+ 1"
locations less than the write pointer. The offset "n" is defined
in the Empty Offset Registers. If no reads are performed after
reset, PAEA (PAEB) will go HIGH after "n+ 1" writes to FIFO A
(B).
If there is no Empty offset specified, PAEA (PAEB) will go
LOW at Empty+7 words.
PAEA (PAEB) is synchronized with respect to the LOW-toHIGH transition of the read clock RCLKA (RCLKB).
Data Outputs (OAo - OAs, OBo - OBs ) - OAo - OAs are
the nine data outputs for memory array A, OBo - OBs are the
nine data outputs for memory array B.
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NUMBER OF WORDS IN ARRAY A
FFA
PAFA
PAEA
EFA
NUMBER OF WORDS IN ARRAY B
FFB
PAFB
PAEB
EFB
72801
72811
72821
0
0
H
L
L
1 to n(l)
0
1 to n(l)
H
1 to n(l)
H
H
L
H
(n+ 1) to (256-(m+ 1))
(n+1) to (512-(m+1))
(n+1) to (1024-(m+1))
H
H
H
H
(256-m)(2) to 255
(512-m)(2) to 511
(1024-m)(2) to 1023
H
L
H
H
256
512
1024
L
L
H
H
NUMBER OF WORDS IN ARRAY A
FFA
PAFA
PAEA
EFA
NUMBER OF WORDS IN ARRAY B
FFB
PAFB
PAEB
EFB
72831
72841
0
0
H
H
L
L
1 to n(l)
1 to n(l)
H
H
L
H
(n+1) to (2048-(m+1))
(n+1) to (4096-(m+1))
H
H
H
H
(2048-m)(2) to 2047
(4096-m)(2) to 4095
H
L
H
H
2048
4096
L
L
H
NOTES.
1. n Empty Offset (n 7 default value)
2. m Full Offset (m 7 default value)
=
=
H
3034 tbl 09
=
=
5.07
s
II
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFO"'"
256 x 9, 512 x 9, 1024 x 9,2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
--------~~~----tRSR------~
RENA 1. RENA2
(RENB1, RENB2)
--------~~~----tRSR------~
--------~~~----tRSR------~
WENA2L!Jll\ (1)
(WENB2ILDB)
EFA. PAEA
(EFB, PAEB)
FFA. PAFA
(FFA, PAFA)
OAo - OAs
(OBo - OBs)
OEA(OEB)=O
3034 drw06
NOTES:
1. Holding WENA2JLDA (WENB2ILDB) HIGH during reset will make the pin act as a second write enable pin. Holding WEN2ILDA (WENB2ILDB) LOW during
reset will make the pin act as a load enable for the....E!£9rammable flag offset registers._
2. After reset, OAo - OA8 (OBo - OB8) will be LOW if OEA (OEB) 0 and tri-state if OEA (OEB) =1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
=
Figure 4. Reset Timing
5.07
9
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9,1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
~-----------tCLK----------~
WCLKA (WCLKB)
(DAo - DAa
DBo - DBa)
NO OPERATION
WENA2 (WENB2)
(If Applicable)
NO OPERATION
~-----tWFF-----'~
~-----tWFF----~
FFA
(FFB)
II
tSKEW1(1
RCLKA (RCLKB)
RENA1 RENA2
(RENB1, RENB2)
3034 drw07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock
cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change
state until the next RCLKA (RCLKB) edge.
Figure 5. Write Cycle Timing
5.07
10
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
~------------tCLK----------~
--__.-14---- tCLKL
RCLKA (RCLKB)
RENA 1, RENA2
(RENB1, RENB2)
NO OPERATION
1+------
/ + - - - - - - tREF----....
tREF----~
EFA (EFB)
OAo - OAs
(OBo - OBs)
WCLKA, WCLKB
WENA1 (WENB1)
WENA2 (WENB2)
,,~-----------------------------------------------------------------------------____-J/
3034 drw 08
NOTE:
1. tSKEWl is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock
cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change
state until the next RCLKA (RCLKB) edge.
Figure 6. Read Cycle Timing
5.07
11
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9,2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA
(WCLKB)
DAo - DAa
(DBo - DBa)
WENA2 (WENB2)
(If Applicable)
. .- - - - t F R L ( l ) , - - -....
RCLKA
(RCLKB)
II
EFA (EFB)
RENA 1, RENA2
(RENB1, RENB2)
OAo - OAa
(OBo- OBa)
Do
01
tOLZ
____________
~~------tOE-----~~
OEA(OEB)
3034 drw 09
NOTE:
1. When tSKEW1 ;:: minimum specification, tFRL tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB LOW).
=
=
=
Figure 7. First Data Word Latency Timing
5.07
12
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA
(WCLKB)
DAo - DAa
(DBo - DBa)
WENA2
(WENB2)
(If Applicable)
RCLKA
(RCLKB)
LOW
OAo- OAa
(OBo - OBa)
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
3034 drw 10
Figure 8. Full Flag Timing
5.07
13
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA (WCLKB)
DAo - DAa
(DBo - DBa)
WENA2 (WENB2)
(If Applicable)
RCLKA (RLCKB)
II
RENA 1, RENA2
(RENB1, RENB2)
LOW
_
QAo - QAa
(QBo - QBa)
tA~.....-----_
_
DATA IN OUTPUT REGISTER
_
.
DATA READ
3034 drw 11
NOTE:
~ minimum specification, tFRL maximum =tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL maximum =2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at at the Empty Boundary (EFA, EFB =LOW).
1. When tSKEW1
Figure 9. Empty Flag Timing
5.07
14
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA
(WCLKB)
WENA2
(WENB2)
(If Applicable)
(1)
Full - (m+ 1) words in FIFO
Full- m words in FIFO(2)
RCLKA
(RCLKB)
RENA1 RENA2
(RENB1, RENB2)
3034 drw 12
Notes:
1. PAF offset =m.
2. (256-m) words for the 72801, (512-m) words the 72811, (1024-m) words forthe 72821, (2048-m) words forthe 72831, or (4096-m) words forthe 72841.
3. tSKEW2 is the minimum time between a rising RCLKA (RCLKS) edge and a rising WCLKA (WCLKS) edge for PAFA (PAFS) to change during that clock
cycle. If the time between the rising edge of RCLKA (RCLKS) and the rising edge of WCLKA (WCLKS) is less than tSKEW2, then PAFA (PAFS) may not
change state until the next WCLKA (WCLKS) rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FI Fa A (S) when PAFA (PAFS) goes LOW.
Figure 10. Programmable Full Flag Timing
5.07
15
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA
(WCLKB)
WENA2
(WENB2)
(If Applicable)
(1)
PAEA
PAEB
n+ 1 words in FIFO
n words in FIFO
RCLKA
(RCLKB)
RENA1,RENA2
(RENB1, RENB2)
3034 drw 13
NOTES:
1. PAE offset
=n.
2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock
cycle. If the time between the rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not
change state until the next RCLKA (RCLKB) rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
Figure 11. Programmable Empty Flag Timing
5.07
16
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9,1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA (WCLKB)
OAo - OM
(OBo - OB7)
3034 drw 14
Figure 12. Write Offset Register Timing
RCLKA (RCLKB)
RENA1 RENA2
(RENB1, RENB2)
OAo - OA7
(OBo - OB7)
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
3034 drw 15
Figure 13. Read Offset Register Timing
5.07
17
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION - When FIFO A (B)
is in a Single Device Configuration, the Read Enable 2 RENA2
(RENB2) control input can be grounded (see Figure 14). In
WCLKA (WCLKB)
this configuration, the Write Enable 2ILoad WENA2ILDA
(WENB2ILDB) pin is set LOW at Reset so that the pin
operates as a control to load and read the programmable flag
offsets.
!
RSA (RSB)
..
RCLKA (RCLKB)
WENA1 (WENB1)
RENA 1 (RENB1)
IDT
72801
72811
72821
72831
72841
IE
WENA2ILDA (WENB2ILDB)
IE
DAo - DAa (DBa - DBa)
FFA(FFB)
OEA (OEB)
OAo - OAa (OBo - OBa)
EFA (EFB)
FIFO
A (B)
PAFA (PAFB)
PAEA (PAEB)
1
RENA2 (AENB2)
3034 drw 16
Figure 14. Block Diagram of One of the 72801172811172821172831172841's two FIFOs configured as a Single device
WIDTH EXPANSION CONFIGURATION - Word width
may be increased simply by connecting the corresponding
input control signals of FIFOs A and B. A composite flag
should be created for each of the end-point status flags EFA
and EFB, also FFA and FFB). The partial status flags PAEA,
PAFB, PAEA and PAFB can be detected from anyone device.
Figure 15 demonstrates an 18-bit word width using the two
FI FOs contained in one IDT72801172811172821172831172841.
Any word width can be attained by adding additionallDT28011
72811/72821172831172841s.
When the IDT2801172811172821172831172841 is in a Width
Expansion Configuration, the Read Enable 2 (RENA2 and
RENB2) control inputs can be grounded (see Figure 15). In
this configuration, the Write Enable 2ILoad (WENA2ILDA,
WENB2ILDB) pins are set LOW at Reset so that the pin
operates as a control to load and read the programmable flag
offsets.
9
RESET
DBO - DB8
RSA
DATA IN
9
DAO - DAB
WCLKA
WENA1
WENA2/LDA
FFA
RAM
ARRAY
A
CLKA
WCLKB
RENAl
256x9
WENB1
OEA1
512x9
1024x9 2WENB2ILDB
2048X9
4096x9
RSB
RAM
ARRAY
B-
EFA
EFB
RCLKB
EMPTY FLA
READ CLOCK
RENB1
256x9
512x9
1024X9
2048x9
4096x9
OEB
OUTPUT ENABLE
OBO- OB8
FFB
RENA2
OAO - OA8 RENB2
9
3034 drw 17
Figure 15. Block diagram of the two FIFOs contained in one 72801172811172821172831172841configured for an 18-bit width-expansion
5.07
18
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
TWO PRIORITY DATA BUFFER CONFIGURATION
The two FIFOs contained in the IDT28011728111728211
72831172841 can be used to prioritize two different types of
data shared on a system bus. When writing from the bus to
the FIFO, control logic sorts the intermixed data according to
type, sending one kind to FIFO A and the other kind to FIFO
B. Then, at the outputs, each data type is transferred to its
appropriate destination. Additional IDT28011728111728211
72831172841s permit more than two priority levels. Priority
buffering is particularly useful in network applications.
Image
Processing
Card
RAM ARRAY A
WClKA
WENA1
-
9
"-
Vcc
Address
Control
~
. ..
e-- -
II
8--1
...
RAM
"""'I
9•
.
9'
I ~'g
OAO-OAB
WENA2 RENA2
-00
8--1
9 "
~ri'
Address
Control
I/O Data
Data
72801
72811
72821
72831
72841
Co
.....
OEA
RENA
lOT
...
Data
Clock
DAo-DAB
v
Processor
Clock
RClKA
...
Voice
Processing
Card
RAM ARRAY B
--I ..
"
....
~
..
WClKB
RClKB
Clock
WENB1
OEB2
I ~'g
8--1
00
RENB1
"9
"
_L _......
DBO-DBB
QBO-QBB
WENB2 RENB2
•
9 v
Address
Control
I/O Data
Data
--L
Vce
3034 drw 18
Figure 16. Block Diagram of Two Priority Configuration
5.07
19
72801n2811n2821n2831n2841 DUAL CMOS SyncFIFOTM
256 x 9, 512 x 9,1024 x 9,2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
BIDIRIECTIONAL CONFIGURATION
The two FI FOs of the I DT2801 172811 172821 172831 172841
can be used to buffer data flow in two directions. In the
RAM ARRAY A
WENA2 RENA2
Vcc ___
-....
WCLKA RCLKA
OEA
WENA1 _ _
RENA1
DAO-DA8
QAO-QA8
~
Processor
Clock
Address
Control
m
9
v
~
A
RAM
"'-J
v
9
9'
...
"-
v
III
-
~~~ r0
I':
V
lOT
72801
72811
72821
72831
72841
cOl
8-l
f8
D-
~ ~ :> >
D-
I~
ex:
Vee
014
013
GNO
012
011
Vee
010
09
GNO
08
07
Vee
06
05
GNO
04
(!)
2766 drw 03
PLCC
TOP VIEW
5.08
2
IDT72205LB172215LB172225LB172235LB172245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 x 18, 1024 x 18,2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
..- ..-
r-
t- t- t-
PIN 1
..- ..-
..... .....
r- r- r- r-
~
~
~
~
I-- I-- I-- ~ f-- l-
/
015
014 I
013
012 I
011 I
I I
I I
I I
010
09
08
07
06
I
I I
I
I I
I
I I
05 I
I I
04
03 I
02 I
I I
I I
01
Do
I
I
I
~
~
I- l - I-
..- r-
r- r- r-
~ f-- l - f-- f-- t- f-f-- f-- l - I-- l - t- t-
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
PN 64-1
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
1617 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
t- f-- tt- f-- t-
~
~
~
~
I-- ~ l- f-- l- f-- f-- l - I-- I-- I-l- I- l- I- l - I- I-- l - I-- I-- I--
'--
L-
L-
l-
'--
'--
I-
I-
'-- '-- '-- '--
L-
'--
L-
I I
II
I
I
I J
II
I I
TT
I
I
I
I
rl
I
I
TI
J i
T:I
TI
II
I
014
1 013
I
GNO
J 012
1 011
I VCC
1 010
I 09
I
GNO
J 08
I 07
1 06
J 05
J GNO
I 04
1 Vee
II
L-
2766 drw 04
TQFP
TOP VIEW
NOTE:
1. For information on the flatpack (F6S-1), contact factory.
5.08
3
IDT72205LBf72215LBf72225LBf72235LBf72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
110
Symbol
Name
00-017
Data Inputs
I
Data inputs for a 18-bit bus.
RS
Reset
I
When RS is set LOW, internal read and write pointers are set to the first location of the
RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an
initial WRITE after power-up.
WCLK
Write Clock
I
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
WEN
Write Enable
I
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of
WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written
into the FIFO if the FF is LOW.
RCLK
Read Clock
I
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if
the FIFO is not empty.
REN
Read Enable
I
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of
RCLK. When REN is HIGH, the output register holds the previous data. Data will not be
read from the FIFO if the EF is LOW.
OE
Output Enable
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will
be in a high-impedance state.
LO
Load
I
When LO is LOW, data on the inputs 00-011 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LO is LOW,
data on the outputs 00-011 is read from the offset and depth registers on the LOW-toHIGH transition of the RCLK, when REN is LOW.
FL
First Load
I
In the single device or width expansion configuration, FL is grounded. In the depth
expansion configuration, FL is grounded on the first device (first load device) and set to
HIGH for all other devices in the daisy chain.
WXI
Write Expansion
Input
I
In the single device or width expansion configuration, WXI is grounded. In the depth
expansion configuration, WXI is connected to WXO (Write Expansion Out) of the
previous device.
RXI
Read Expansion
Input
I
In the single device or width expansion configuration, RXI is grounded. In the depth
expansion configuration, RXI is connected to RXO (Read Expansion Out) of the previous
device.
EF
Empty Flag
0
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited.
When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
Almost-Empty Fla~
0
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the
FIFO. The default offset at reset is 31 from empty for 72205LB, 63 from empty for
72215LB, and 127 from empty for 72225LB172235LB172245LB.
PAF
Programmable
0
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO
The default offset at reset is 31 from full for 72205LB, 63 from full for 72215LB, and
127 from full for 72225LB/72235LB172245LB.
FF
Full Flag
0
When FF is LOW, the FIFO is full and further data writes into the input are inhibited.
When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.
WXO/HF
Write Expansion
Out/Half-Full Flag
0
In the single device or width expansion configuration, the device is more than half full
when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to
WXI of the next device when the last location in the FIFO is written.
RXO
Read Expansion
Out
0
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device
when the last location in the FIFO is read.
00-Q17
Data Outputs
0
Data outputs for a 18-bit bus.
VCC
Power
Eight +5V power supply pins for the PLCC and PGA, five pins for the TOFP.
GND
Ground
Eight ground pins for the PLCC and PGA, seven pins for the TOFP.
Description
2766 tbl 01
5.08
4
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 x 18,1024 X 18,2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Commercial
Terminal Voltage
-0.5 to +7.0
with respect to GND
TA
Operating
Temperature
TBIAS
o to +70
Mlilitary
Unit
-0.5 to +7.0
V
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
VCCM
Parameter
Military Supply
Voltage
Commercial Supply
Voltage
-55 to +125
°C
Temperature Under -55 to +125
Bias
-65 to +135
°C
GND
Supply Voltage
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
VIH
lOUT
DC Output Current
50
50
rnA
VIH
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
Vccc
NOTE:
2766 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation ofthe device at these or any otherconditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maimum rating conditions for extended
VIL(I)
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
4.5
5.0
5.5
V
0
0
0
V
2.0
-
V
2.2
-
-
V
-
-
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2766 tbl 03
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V + 10%, TA = O°C to +70°C; Military: Vcc = SV -+ 10%, TA = -SsoC to +12S0C)
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
Commercial
tCLK = 15, 20, 25, 35, 50ns
II
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
Military
tCLK = 25, 35, 50ns
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
1u!1)
Input Leakage Current (any input)
-1
1
-10
~
Output Leakage Current
-10
10
-10
10
VOH
Output Logic "1" Voltage, IOH = -2 mA
2.4
-
2.4
~
V
VOL
ICC1(3)
Output Logic "0" Voltage, IOl = 8 mA
-
0.4
Active Power Supply Current
-
-
-
10
ILO(2)
-
Symbol
Parameter
ICC2(3)
Average Standby Current (All Input = VCC - 0.2V,
except RCLK and WCLK which are free-running)
NOTES:
1. Measurements with 0.4 s; Y,N S; Vee.
2. OE 2: VIH, 0.4 S; VOUT S; Vcc.
3. Tested at f 20MHz with outputs open.
200
70
0.4
V
250
mA
85
rnA
2766 tbl 04
=
CAPACITANCE (TA
=+2SoC, f =1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN(2)
Input
Capacitance
VIN =OV
10
pF
Courl 1 ,2)
Output
Capacitance
VOUT=OV
10
pF
NOTES:
1. With output deselected, (OE HIGH).
2. Characterized values, not currently tested.
=
2766 tbl 05
5.08
5
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18, 512 X 18, 1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = sv ± 10%, TA = O°C to +70°C; Military: Vcc = SV +
- 10%, TA = -SsoC to +12S°C)
Commercial
Commercial and Military
Symbol
Parameter
72205LB15
72215LB15
72225LB15
72235LB15
72245LB15
72205LB20
72215LB20
72225LB20
72235LB20
72245LB20
72205LB25
72215LB25
72225LB25
72235LB25
72245LB25
72205LB35
72215LB35
72225LB35
72235LB35
72245LB35
Min. Max.
Min.
72205LB50
72215LB50
72225LB50
72235LB50
72245LB50
Min.
Max.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
-
66.7
-
50
-
40
-
28.6
-
20
MHz
tA
Data Access Time
2
10
2
12
3
15
3
20
3
25
ns
tCLK
Clock Cycle Time
15
20
-
25
-
50
-
ns
Clock HIGH Time
6.5
8
-
10
14
6.5
8
10
tDS
Data Set-up Time
4
-
6
tDH
Data Hold Time
1
-
1
1
-
2
tENS
Enable Set-up Time
4
5
6
-
7
1
1
2
2
tRS
Reset Pulse Width(l)
15
20
-
-
ns
Enable Hold Time
-
10
tENH
35
-
50
-
ns
tASS
Reset Set-up Time
10
12
-
30
-
ns
Reset Recovery Time
10
12
-
15
-
20
tASR
-
-
-
ns
Clock LOW Time
-
20
tCLKL
-
35
tCLKH
-
20
-
30
-
ns
tRSF
Reset to Flag and Output Time
-
35
-
35
-
40
-
45
-
50
ns
toLZ
Output Enable to Output in Low-Z(2)
0
-
0
-
0
-
0
-
0
-
ns
tOE
Output Enable to Output Valid
-
8
-
12
-
15
-
20
ns
Output Enable to Output in High-Z(2)
1
8
1
9
9
-
tOHZ
1
12
1
15
1
20
ns
tWFF
Write Clock to Full Flag
-
10
12
-
30
ns
-
10
15
-
20
Read Clock to Empty Flag
20
-
30
ns
tPAF
Clock to Programmable
Almost-Full Flag
-
28
-
30
-
15
tREF
-
35
-
40
-
40
ns
tPAE
Clock to Programmable
Almost-Empty Flag
-
28
-
30
-
35
-
40
-
40
ns
tHF
Clock to Half-Full Flag
-
28
-
30
-
40
-
40
ns
Clock to Expansion Out
-
10
-
12
-
35
tXO
15
-
20
-
30
ns
tXI
Expansion In Pulse Width
6.5
-
8
-
10
14
-
20
-
ns
tXIS
Expansion In Set-Up Time
5
-
8
10
15
10
-
14
16
-
18
20
-
ns
Skew time between Read Clock &
Write Clock for Full Flag
-
20
tSKEW1
-
-
tSKEW2
Skew time between Read Clock &
Write Clock for Empty Flag
10
-
14
-
16
-
18
-
20
-
ns
5
1
25
15
12
14
7
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
Max. Min.
20
10
2
ns
ns
ns
ns
ns
2766 tbl 06
5V
1.1 K
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
680n
1.5V
30pF*
2766 drw 05
See Figure 1
2766 tbl 07
5.08
Figure 1. Output Load
* Includes jig and scope capacitances.
6
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 X 18, 1024 X 18,2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS:
a write is performed, the EFwill go HIGH aftertREF and a read
can begin. REN is ignored when the FIFO is empty.
INPUTS:
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel
output buffers receive data from the output register. When OE
is disabled (HIGH), the Q output data bus is in a highimpedance state.
DATA IN (Do - 017)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and
write pointers are set to the first location. A reset is required
after power-up before a write operation can take place. The
Full Flag (FF), Half-Full Flag (HF), and Programmable AlmostFull Flag (PAF) will be reset to HIGH after tRSF. The Empty
Flag (EF) and Programmable Almost-Empty Flag (PAE) will be
reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to
their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of
the write clock (WCLK). Data set-up and hold times must be
met with respect to the LOW-to-HIGH transition of the write
clock (WCLK).
The write and read clocks can be asynchronous or
coincident.
WRITE ENABLE (WEN)
When Write Enable (WEN) is LOW, data can be loaded into
the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM
array sequentially and independently of anyon-going read
operation.
When WEN is HIGH, the input register holds the previous
data and no new data is loaded into the FIFO.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the FFwill go HIGH aftertwFF allowing a write
to begin. WEN is ignored when the FIFO is full.
LOAD (LD)
The IDT7220SLB17221SLB17222SLB17223SLB17224SLB
devices contain two 12-bit offset registers with data on the
inputs, or read on the outputs. When the Load (LD) pin is set
LOW and WEN is set LOW, data on the inputs 00-011 is
written into the Empty offset registeron the first LOW-to-HIGH
transition of the write clock (WCLK). When the LD pin and
(WEN) are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the write
clock (WCLK). The third transition of the write clock (WCLK)
again writes to the Empty offset register.
However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing the LD pin HIGH, the FIFO is returned to normal
read/write operation. When the LD pin is set LOW, and WEN
is LOW, the next offset register in sequence is written.
When the LD pin is LOWand WEN is HIGH, the WCLK input
is disabled; then a signal at this input can neither incrementthe
write offset register pointer, nor execute a write.
The contents of the offset registers can be read on the
output lines when the LD pin is set LOW and REN is set LOW;
then, data can be read on the LOW-to-HIGH transition of the
read clock (RCLK). The act of reading the control registers
employs a dedicated read offset register pointer. (The read
and write pointers operate independently).
A read and a write should not be performed simultaneously
to the offset registers.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH
transition of the read clock (RCLK), when Output Enable (OE)
is set LOW.
The write and read clocks can be asynchronous or
coincident.
READ ENABLE (REN)
When Read Enable (REN) is LOW, data is loaded into the
RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK).
When REN is HIGH, the output register holds the previous
data and no new data is loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
LD
WEN
0
0
WCLK(1)
I
Selection
Writing to offset registers:
Empty Offset
Full Offset
0
1
1
0
1
1
I
I
I
0
No Operation
Write Into FIFO
No Operation
NOTE:
2766 tbl 08
1. The same selection sequence applies to reading from the registers. REN
is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
5.08
Figure 2. Write Offset Register
7
II
IDT72205LBf72215LBf72225LBf72235LBf72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
First Load (FL)
First Load (FL) is grounded to indicate operation in the
Single Device or Width Expansion mode. Inthe Depth Expansion configuration, FL is grounded to indicate it is the first
device loaded and is set to HIGH for all other devices in the
daisy chain. (See Operating Configurations for further details.)
WRITE EXPANSION INPUT (WXI)
This is a dual purpose pin. Write Expansion In (WXI) is
grounded to indicate operation in the Single Device or Width
Expansion mode. WXI is connected to Write Expansion Out
(WXO) of the previous device in the Depth Expansion or Daisy
Chain mode.
The Full Flag (FF) is updated on the LOW-to-HIGH transition of the write clock (WCLK).
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read
operations, when the read pointer is equal to the write pointer,
indicating the device is empty.
The EF is updated on the LOW-to-HIGH transition the read
clock (RCLK).
17
o
11
EMPTY OFFSET REGISTER
READ EXPANSION INPUT (RXI)
This is a dual purpose pin. Read Expansion In (RXI) is
grounded to indicate operation in the Single Device or Width
Expansion mode. RXI is connected to Read Expansion Out
(RXO) of the previous device in the Depth Expansion or Daisy
Chain mode.
DEFAULT VALUE
001 FH (72205) 003FH (72215):
007FH (72225n2235n2245)
17
o
11
OUTPUTS:
FULL OFFSET REGISTER
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write
operation, indicating that the device is full. If no reads are
performed after Reset (RS), the Full Flag (FF) will go LOW
after 256 writes for the IDT72205LB, 512 writes for the
IDT72215LB, 1024 writes forthe I DT72225LB, 2048 writes for
the IDT72235LB and 4096 writes for the IDT72245LB.
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH 72225n2235n2245
NOTE:
2766 drw 06
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
TABLE 1- STATUS FLAGS
Number of Words in FIFO
PAE EF
72205
72215
72225
72235
72245
FF PAF
HF
0
1 to n(l)
0
1 to n(l)
0
1 to n(l)
0
1 to n(l)
0
1 to n(l)
H
H
H
L
L
H
H
H
L
H
(n + 1)to 128
(n + 1) to 256
(n+1)t0512
(n+1)t01024
(n + 1) to 2048
H
H
H
H
H
H
H
L
H
H
129 to (256-(m+ 1)) 257 to (512-(m+1)) 513 to (1 024-(m+ 1)) 1025 to (2048-(m+ 1)) 2049 to (4096-(m+1))
(256-m)(2) to 255
(512-m)(2) to 511
(1 024-m)(2) to 1023
(2048-m)(2) to 2047
(4096-m )(2) to 4095
H
L
L
H
H
256
512
1024
2048
4096
L
L
L
H
H
NOTES:
1. n Empty Offset (Default Values: 72205 n=31, 72215 n 63, 72225/72235/72245 n 127)
2. m = Full Offset (Default Values: 72205 n=31 , 72215 n = 63, 72225/72235/72245 n = 127)
=
=
=
2766 Ibl 09
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW
when FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (RS), the PAF will go LOW after (256m) writes for the IDT7220SLB, (S12-m) writes for the
IDT72215LB, (1024-m) writesforthe IDT72225LB, (2048-m)
writes for the IDT7223SLB and (4096-m) writes for the
IDT7224SLB. The offset "m" is defined in the FULL offset
register.
If there is no Full offset specified, the PAFwill be LOW when
the device is 31 away from completely full for 72205LB, 63
away from completely full for 72215LB, and 127 away from
completely full for 72225LB172235LS172245LB.
The PAF is asserted LOW on the LOW-to-HIGH transition
of the write clock (WCLK). PAF is reset to HIGH on the LOWto-HIGH transition of the read clock (RCLK). Thus PAF is
asychronous.
5.08
8
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty Flag (PAE) will go LOW
when the read pointer is "n+1" locations less than the write
pointer. The offset "n" is defined in the EMPTY offset register.
If there is no Empty offset specified, the Programmable
Almost Empty Flag (PAE) will be LOW when the device is 31
away from completely empty for 72205LB, 63 away from
completely empty for 72215LB, and 127 away from completely empty for 72225LBn2235LBn2245LB.
The PAE is asserted LOW on the LOW-to-HIGH transition
of the read clock (RCLK). PAE is reset to HIGH on the LOWto-HIGH transition of the write clock (WCLK). Thus PAF is
asychronous.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
This is a dual-purpose output. In the Single Device and
Width Expansion mode, when Write Expansion In (WXI) is
grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled, and at the LOW-to-HIGH
transition of the next write cycle, the Half-Full Flag goes LOW
and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memoryofthe device. The Half-Full Flag (HF) isthen reset
to HIGH by the LOW-to-HIGH transition of the read clock
(RCLK). The HF is asychronous.
In the Depth Expansion or Daisy Chain mode, WXI is
connected to WXO of the previous device. This output acts as
a signal to the next device in the Daisy Chain by providing a
pulse when the previous device writes to the last location of
memory.
READ EXPANSION OUT (AXO)
In the Depth Expansion or Daisy Chain configuration, Read
Expansion In (AXI) is connected to Read Expansion Out
(AXO) of the previous device. This output acts as a signal to
the next device in the Daisy Chain by providing a pulse when
the previous device reads from the last location of memory.
DATA OUTPUTS (00-017)
00-017 are data outputs for 18-bit wide data.
II
t RS ------~
. .- - - tRSS
----~
EF ,PAE
~~~~~~~~~~~~~~~~~----------------------
FF, PAF, HF
t RSF
OE-1(1)
00 -
~7 ~~~~~~~ ---.---.--.--.-.--.----.-.-------.--.---.------.-.----.--f-=.....-..~........-__.........
'- OE=O
2766 drw07
NOTES:
1. After reset, the outputs will be LOW if OE 0 and tri-state if OE
2. The clocks (RCLK, WCLK) can be free-running during reset.
=
=1.
Figure 5. Reset Timing(2)
5.08
9
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 X 18, 512 X 18, 1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
/"1111------ tCLK -------I~
WCLK
Do - 017
" - NO OPERATION
twFF----~
RCLK
_____--J/
2766 drw08
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If
the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 6. Write Cycle Timing
5.08
10
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
...1 - - - - - - tCLK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-------I~
RCLK
00 - 017
II
WCLK
,,-------------------------------------2766 drw 09
NOTE:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the
time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
Figure 7. Read Cycle Timing
5.08
11
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 X 18, 512 X 18, 1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS~
Do (first valid write)
Do - 017
01
02
03
04
tENS
WEN
(1)
tFRL
RCLK
tREFJ
EF
00 - 017
Do
______________. to.._---- t DE
2766 drw 10
NOTES:
1. When tSKEW2 ~ minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2· tCLK +
tSKEW20rtCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF LOW).
2. The first word is available the cycle after EF goes HIGH, always.
=
Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write
5.08
12
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 X 18-BIT, 512 X 18,1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
II
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2766 drw 11
Figure 9. Full Flag Timing
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1. then FF may not change state until the next WCLK edge.
5.08
13
IDT72205LBf72215LBf72225LBf72235LBf72245LB CMOS SyncFIFOTM
256 X 18,512 X 18, 1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
tDS~
Do - 017
tDS~
DATA WRITE 1
DATA WRITE 2
tENS
~I-_ _ _ _ _ _ tFRL (1) ----I~
~I-_ _ _ _ _ _ tFRL(l)
RCLK
OE
00-017
LOW
_ _ _~=~L_ __
~
DATA IN OUTPUT REGISTER
DATA READ
2766 drw 12
Figure 10. Empty Flag Timing
NOTE:
1. When tSKEW2;:: minimum specification, tFRL (maximum) tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum)
or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF LOW).
=
=
5.08
=either 2' tCLK + tSKEW2.
14
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 x 18, 1024 x 18,2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
LO
00-015
Figure 11. Write Programmable Registers
RCLK
00-015
PAEOFFSET
PAFOFFSET
2766 drw 14
Figure 12. Read Programmable Registers
5.08
15
IDT7220SLBn221SLBn222SLBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18,512 X 18,1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
PAE
n words in FIFO
------------------------------------------------'
RCLK
tENS
T\
~
NOTE:
1. PAE is offset
= n.
Number of data words written into FIFO already
2766 drw 15
=n.
Figure 13. Programmable Almost Empty Flag Timing
tCLKH ...- -......--~ tCLKL
WCLK
FulI-m words
in FIFO(2)
Full - m + 1 words
in FIFO(3)
RCLK
tENS"
REN------------------------------------------------~~~
2766 drw 16
NOTES:
c
1. PAF offset = m. Number of data words written into FIFO already =256 - m + 1 for the IDT722058, 512 - m + 1 for the IDT722158, 1024 - m + 1 for the
IDT722258, 2048 - m + 1 for the IDT722358 and 4096 - m +1 for the IDT722458.
2. 256- m words in IDT722058, 512 - m words in IDT722158, 1024 - m words in IDT722258, 2048- m words in IDT722358 and 4096- m words in IDT722458.
3. 256 - m + 1 words in IDT72205B, 512 - m + 1 words in IDT722158, 1024 - m + 1 words in IOT722258, 2048 - m + 1 words in IDT722358 and 4096 - m
+ 1 words in IDT722458.
Figure 14. Programmable Almost-Full Flag Timing
5.08
16
IDT72205LB172215LB172225LB172235LB172245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
tCLKH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tcLKL
WCLK
Half Full or Less
Half Full or Less
RCLK
tENS"
~
2766 drw 17
Figure 15. Half-Full Flag Timing
II
NOTE:
1. Write to Last Physical Location.
Figure 16. Write Expansion Out Timing
RCLK
REN
2766 drw 19
NOTE:
1. Read from Last Physical Location.
Figure 17. Read Expansion Out Timing
5.08
17
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 X 18, 512 X 18,1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tXl~f--WCLK
2766 drw 20
Figure 18. Write Expansion In Timing
RCLK
2766 drw 21
Figure 19. Read Expansion In Timing
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72205LB/72215LB/72225LB/72235LBI
72245LB may be used when the application requirements are
for256/51211 024/2048/4096 words or less. The IDT72205LBI
72215LB172225LB172235LB172245LB are in a single Device
Configuration when the Write Exansion In (WXI), Read Expansion In (RXI), and First Load (FLl control inputs are
grounded (Figure 20).
l
WRITE CLOCK (WCLK)
RESET (RS)
READ CLOCK (RCLK)
WRITE ENABLE (WEN)
READ ENABLE (REN)
LOAD (LD)
lOT
72205LBI
72215LBI
72225LBI
72235LBI
72245LB
DATA IN (Do - 017)
FULL FLAG (FF)
OUTPUT ENABLE
(bE)
DATA OUT (00 - 017)
EMPTY FLAG (EF)
PROGRAMMABLE (PAE)
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
FIRST LOAD (FL)
t
t
--L-
J
READ EXPANSION IN (RXI)
-
WRITE EXPANSION IN (WXI)
2766 drw 22
Figure 20. Block Diagram of Single 256 x 18/512 x 18/1024 x 18/2048 x 18/4096 x 18 Synchronous FIFO
5.08
18
IDT72205LBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 x 18-BIT, 512 x 18, 1024 x 18,2048 X 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can
be detected from anyone device. The exceptions are the
Empty Flag and Full Flag. 8ecause of variations in skew
between RCLK and WCLK, it is possible for flag assertion and
de assertion to vary by one cycle between FIFOs. To avoid
problems the user must create composite flags by ANDing the
Empty Flags of every FIFO, and separately ANDing all Full
Flags. Figure 21 demonstrates a 36-word width by using two
IDT722058/722158/722258/722358/722458s. Any word
width can be attained by adding additional IDT7220581722158/
72225817223581722458s. Please see the Application Note
AN-83.
RESET (RS)
RESET (RS)
18
...
WRITE CLOCK (WCLK)
------------~--~~~-----+---------~~
WRITE ENABLE (WEN)
---------
.....------~~--------~~-----~--------~~
LOAD (LD)
----72205LB!
.....------~~--------~~-----~--------~~
PROGRAMMABLE (PAE)
72205LB!
..
READ CLOCK (RCLK)
•
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
72215LB!
72225LB!
72235LB!
72245LB
72215LB!
72225LB!
72235LB!
72245LB
t=~:::_-I~F,=-
HALF FULL FLAG (HF)
___ §E . . . . . ._ _
-----
EF
---.1
II
~-----I
18
DATA OUT (Q)
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (AXI)
2766 drw23
NOTE:
1. Do not connect any output control signals directly together.
Figure 21. Block Diagram of 256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a
Width Expansion Configuration
DEPTH EXPANSION CONFIGURATION
(WITH PROGRAMMABLE FLAGS)
The IDT72205L8172215L8172225L8172235L8172245LB can
easily be adapted to applications requiring more than 256/
512/1024/2048/4096 words of buffering. Figure 22 shows
Depth Expansion using three IDT72205L8172215L8172225L8/
72235L8172245L8s. Maximum depth is limited only by signal
loading. Follow these steps:
1. The first device must be designated by grounding the
First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device
must be tied to the Write Expansion In (WXI) pin of
the next device. See Figure 24.
5.08
4. The Read Expansion Out (RXO) pin of each device
must be tied to the Read Expansion In (RXI) pin of
the next device. See Figure 24.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth
Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite
flags by ORing together every respective flags for
monitoring. The composite PAE and PAF flags are not
precise.
19
IDT7220SLBn2215LBn2225LBn2235LBn2245LB CMOS SyncFIFOTM
256 X 18,512 X 18, 1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
J
WXO AXO
r
r
IDT
72205LBI
72215LBI
72225LBI
72235LBI
72245LB
Vee
L
FIRST LOAD (FL)
FF
PAF
EF
PAE
WXI AXI
t
WXO AXO
DATA IN (D)
IDT
72205LBI
72215LBI
72225LBI
72235LBI
72245LB
I I
I I
Vee
FIRST LOAD (FL)
I I
I
L
FF
PAF
-
DATA OUT (0)
EF
PAE
-
WXI AXI
t
WRITE CLOCK (WCLK)
WXO AXO
READ ENABLE (REN)
WRITE ENABLE (WEN)
IDT
72205LBI
72215LBI
72225LBI
72235LBI
72245LB
RESET (RS)
LOAD (LD)
•
PAF
.L.
Cf
I
,
\
I
READ CLOCK (RCLK)
-
PAF
1
II
EF I - -
FF
FIRST LOAD (FL)
OUTPUT ENABLE (OE)
WXI
PAE
AXI
D_EF
,
I
~PAE
t
2766 drw 24
Figure 22. Block Diagram of 768 X 18/1536 X 18/3072 x 18/6144 x 18/12288 x 18 Synchronous FIFO Memory
With Programmable Flags used in Depth Expansion Configuration
5.08
20
IDT72205LB172215LB172225LB172235LB172245LB CMOS SyncFIFOTM
256 X 18-BIT, 512 X 18, 1024 X 18, 2048 X 18 and 4096 X 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
y~LANK
J JG
. . . . . ---------1
I PF
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic Leaded Chip Carrier
Pin Grid Array
Thin Plastic Quad Flatpack
15 Com'l Only
20 Com'l Only
~-----------~25
}
Clock Cycle Time (tCLK)
Speed in Nanoseconds
35
50
~------------------i-: LB
72205
72215
~---------------------~ 72225
72235
72245
Low Power
256 x 18 Synchronous FIFO
512 x 18 Synchronous FIFO
1024 x 18 Synchronous FIFO
2048 x 18 Synchronous FIFO
4096 x 18 Synchronous FIFO
II
2766 drw2S
5.08
21
~®
CMOS DUAL SyncFIFOTM
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1024 x 18
PRELIMINARY
IDT12805LB
IDT12815LB
IDT72825LB
Integrated Device Technology, Inc.
• Enable puts output data bus in high impedance state
• High-performance submicron CMOS technology
• Available in a 121-lead, 16 x 16 mm plastic Ball Grid
Array (BGA)
FEATURES:
• The 72805 is equivalent to two 72205LB 256 x 18
FIFOs
• The 72815 is equivalent to two 72215LB 512 x 18
FIFOs
• The 72825 is equivalent to two 72225LB 1024 x 18
FIFOs
• Offers optimal combination of large capacity (2K), high
speed, design flexibility, and small footprint
• Ideal for the following applications:
Network switching
- Two level prioritization of parallel data
Bidirectional data transfer
Busmatching between 18-bit and 36-bit data paths
- Width expansion to 36-bit per package
Depth expansion to 2048 words per package
• 20ns read/write cycle time, 12ns access time
• Read and write clocks can be asynchronous or coincident (permits simultaneous reading and writing of data
on a single clock edge)
• Programmable almost-empty and almost-full flags
• Empty and Full flags signal FIFO status
• Half-Full flag capability in single device configuration
DESCRIPTION:
The IDT72805LB172815LB172825LB are dual 18-bit-wide
synchronous (clocked) first-in, first-out (FIFO) memories.
These devices are functionally equivalent to two IDT72205LB/
72215LB172225LB FIFOs in a single package with all associated control, data, and flag lines assigned to independent
pins. These FIFOs are applicable for a wide variety of data
buffering needs, such as optical disk controllers, local area
networks (LANs), and interprocessor communication.
Each of the two FIFOs contained in the IDT72805LB/
72815LB172825LB has an 18-bit input data port (DO - D17)
and an 18-bit output data port (00 - 017). Each input port is
controlled by a free-running Write Clock (WCLK) and a data
input Write Enable pin (WEN). Data is written into each array
on every rising clock edge of the appropriate Write Clock
(WCLK) when its corresponding Write Enable line (WEN) is
asserted.
The output port of each FIFO bank is controlled by a Read
Clock pin (RCLK) and a Read Enable pin (REN). The Read
HFAI(WXOA)
PAEA
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
WCLKB
DAo-DA17
LDA
PAFA
WENB
DBO-DB17
1- _
RCLKA
RENA
RXOB
RXIB
RCLKB
RENB
(HFB)/wxOB
WXIB
FLB
3139drw01
The lOT logo Is a registered trademark, and SyncFIFO is a trademark of Integrated Device Technology, Inc
FEBRUARY 1995
COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device Technology, Inc.
DSC-20701-
5.09
1
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
Clock can be tied to the Write Clock for single clock operation
or the two clock lines can run asynchronously to one another
for dual clock operation. An Output Enable pin (OE) is
provided on the read port of each FIFO for three-state output
control.
Each of the two FIFOs has fixed flags, an Empty (EF) and
a Full (FF). Two kinds of programmable flags, an AlmostEmpty (PAE) and an Almost-Full (PAF), are provided to
improve the utilization of each FIFO memory bank. The offset
loading of the programmable flags is controlled by a simple
state machine and is initiated by asserting the load pin (LO).
A Half-Full flag (HF) is available for each FIFO that is
implemented as a single device.
The I0T7280SLBn281SLBn282SLB are depth expandable using a daisy-chain technique. A set of expansion pins
(XI and XO) are provided for each FI FO. In depth expansion
configuration, FL is grounded on the first device and set high
for all other devices in the daisy-chain.
The I0T7280SLBn281SLBn282SLB is fabricated using
lOT's high speed submicron CMOS technology.
PIN CONFIGURATION
PIN 1
\.--------..
A
B
c
o
E
F
G
H
J
K
IwC,BEJEJBI DB16 IIRCLKBI I LOB" RSB II OB1711 OB161
IPAFA I IWENAI I DB121
IRENB" OEB "
OB15 II OB14 I
I FFA "RXIA II-AIBI DB141BEJBEJI OB131B
EJ B B
II
EFB "
BBEJEJBBEJEJBBB
EJBEJI~NII PAEAIBBEJEJB
B
EJBEJEJEJEJEJEJEJBEJ
EJ
81 PAEB II~~~I
BB BE]
EJB EJ
BBBBBBBGBBEJ
EJBEJBEJBBB8EJG
IOA14 II OA15 I EFA II OEA I RENA II DA15 II DA12 IB IWENBI B IPAFB I
I B B B IWCLK,
L I0A1611 om II RSA II LDA I RCKLAII DA16 DA13 I
2
3
4
5
6
BGA
(BG 121-1)
TOP VIEW
5.09
7
8
9
10
11
3139 drw02
2
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name
VO
Data Inputs
I
Data inputs for a 18-bit bus.
Reset
I
When RS is set LOW, internal read and write pointers are set to the first location of the
RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before
an initial WRITE after power-up.
Write Clock
I
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
WENA
WENB
Write Enable
I
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of
WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written
into the FIFO if the FF is LOW.
RCLKA
RCLKB
Read Clock
I
When REN is LOW, data is.read from the FIFO on a LOW-to-HIGH transition of RCLK, if
the FIFO is not empty.
Read Enable
I
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of
RCLK. When REN is HIGH, the output register holds the previous data. Data will notbe
read from the FIFO if the EF is LOW.
OEA
OEB
Output Enable
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will
be in a high-impedance state.
LOA
LDB
Load
I
When LD is LOW, data on the inputs 00-D9 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW,
data on the outputs 00-09 is read from the offset and depth registers on the LOW-toHIGH transition of the RCLK, when REN is LOW.
FLA
FLB
First Load
I
In the single device or width expansion configuration, FL is grounded. In the depth
expansion configuration, FL is grounded on the first device (first load device) and set to
HIGH for all other devices in the daisy chain.
WXIA
WXIB
Write Expansion
Input
I
In the single device or width expansion configuration, WXI is grounded. In the depth
expansion configuration, WXI is connected to WXO (Write Expansion Out) of the
previous device.
AXIA
AXIB
Read Expansion
Input
I
In the single device or width expansion configuration, RXI is grounded. In the depth
expansion configuration, AXI is connected to AXO (Read Expansion Out) of the previous
device.
EFA
EFB
Empty Flag
0
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited.
When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAEA
PAEB
Programmable
Almost-Empty Flag
0
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the
FIFO. The default offset at reset is 31 from empty for 72805LB, 63 from empty for
72815LB, and 127 from empty for 72825LB.
PAFA
PAFB
Programmable
0
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO
The default offset at reset is 31 from full for 72805LB, 63 from full for 72815LB, and
127 from full for 72825LB.
Full Flag
0
When FF is LOW, the FIFO is full and further data writes into the input are inhibited.
When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.
Write Expansion
Out/Half-Full Flag
0
In the single device or width expansion configuration, the device is more than half full
when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to
WXI of the next device when the last location in the FIFO is written.
Read Expansion
Out
0
In the depth expansion configuration, a pulse is sent from AXO to AXI of the next device
when the last location in the FIFO is read.
Data Outputs
0
Data outputs for a 18-bit bus.
Symbol
DAD-OA17
DBD-OB17
RSA
RSB
WCLKA
WCLKB
RENA
RENB
FFA
FFB
WXONHFA
WXOB/HFB
AXOA
AXOB
OAO-OA17
OBO-OB17
Description
VCC
Power
8 Vcc pins
GNO
Ground
9 GNO pins
3139 tbl 01
5.09
3
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TA
Rating
Commercial
Unit
Terminal Voltage
with respect to GND
-0.5 to +7.0
V
o to +70
°C
Operating
Temperature
TSIAS
Temperature Under
Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output Current
50
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
mA
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.0
-
-
V
VIL(I)
Input Low Voltage
-
-
0.8
V
NOTE:
NOTE:
3139 tbl02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation ofthe device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maimum rating conditions for extended
periods may affect reliabilty.
3139 tbl 03
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V ± 10%, TA = O°C to +70°C)
II
IDT72805LB
IDT72815LB
IDT72825LB
Commercial
tCLK = 20, 25, 35ns
Symbol
Min.
Typ.
lu(1)
Input Leakage Current (any input)
-1
ILO(2)
Output Leakage Current
-10
VOH
Output Logic "1" Voltage, IOH = -2 mA
2.4
VOL
Output Logic "0" Voltage, IOL = 8 mA
-
leCl(3)
Active Power Supply Current
-
leC2(3)
Average Standby Current (All Input = VCC - 0.2V,
except RCLK and WCLK which are free-running)
-
-
Parameter
NOTES:
1. Measurements with 0.4 :5; VIN :5; Vcc.
2. OE ~ VIH, 0.4 :5; VOUT :5; Vcc.
3. Tested at f 20MHz with outputs unloaded.
Max
Unit
1
~
10
~
-
V
0.4
V
250
mA
80
mA
3139tbl04
=
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN(2)
Input
Capacitance
VIN = OV
10
pF
COUT(I,2)
Output
Capacitance
VOUT=OV
10
pF
NOTES:
1. With output deselected, (OE HIGH).
2. Characterized values, not currently tested.
=
3139 tbl 05
5.09
4
IDT12805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
D
(Commercial: Vcc = 5V +
- 10%, TA = ODC to +70 C)
Commercial
72805LB20
72815LB20
72825LB20
Symbol
fS
Min.
Parameter
-
Clock Cycle Frequency
Max.
50
72805LB25
72815LB25
72825LB25
Min.
-
40
tA
Data Access Time
2
tCLK
Clock Cycle Time
20
-
25
tCLKH
Clock HIGH Time
8
-
10
tCLKL
Clock LOW Time
8
10
tDS
Data Set-up Time
5
tDH
Data Hold Time
1
tENS
Enable Set-up Time
5
tENH
Enable Hold Time
12
Reset Pulse Width(l)
20
tRSS
Reset Set-up Time
12
tRSR
Reset Recovery Time
12
-
tRSF
Reset to Flag and Output Time
-
35
tRS
1
Max.
3
72805LB35
72815LB35
72825LB35
Min.
Max.
Unit
28.6
MHz
ns
-
15
3
20
35
6
-
1
-
2
6
7
35
15
-
20
-
-
40
-
45
ns
ns
1
25
15
14
14
7
2
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOLZ
Output Enable to Output in Low-Z(2)
0
-
0
-
0
-
tOE
Output Enable to Output Valid
-
9
-
12
-
15
ns
15
ns
20
ns
20
ns
40
ns
35
-
tOHZ
Output Enable to Output in High-Z(2)
tWFF
Write Clock to Full Flag
tREF
Read Clock to Empty Flag .
tPAF
Clock to Programmable Almost-Full Flag
tPAE
Clock to Programmable Almost-Empty Flag
-
tHF
Clock to Half-Full Flag
-
txo
Clock to Expansion Out
tXI
Expansion In Pulse Width
1
9
1
12
30
-
-
12
-
15
-
20
ns
8
-
10
14
-
ns
15
-
ns
18
-
ns
18
-
ns
12
12
30
30
15
15
35
35
Expansion In Set-Up Time
8
Skew time between Read Clock & Write Clock for
Full Flag
14
-
10
tSKEW1
16
-
tSKEW2
Skew time between Read Clock & Write Clock for
Empty Flag
14
-
16
-
tXIS
1
40
ns
40
ns
NOTES:
3139 tbl 06
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
680Q
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
30pF*
GND to 3.0V
3139 dow 05
Figure 1. Output Load
See Figure 1
* Includes jig and scope capacitances.
3139 tbl 07
5.09
5
IDT72805n2815172825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS:
performed, the EF will go HIGH after tREF and a read can
begin. REN is ignored when the FIFO is empty.
INPUTS:
OUTPUT ENABLE (OEA, OEB)
When Output Enable (OEA, OEB) is enabled (LOW), the
parallel output buffers receive data from the output register.
When OE is disabled (HIGH), the Q outPl,lt data bus is in a
high-impedance state.
DATA IN (DAD - DA17, DBo - DB17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RSA, RSB)
Reset is accomplished whenever the Reset (RSA, RSB)
input is taken to a LOW state. During reset, both internal read
and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FFA, FFB), Half-Full Flag (HFA, HFB),
and Programmable Almost-Full Flag (PAFA, PAFB) will be
reset to HIGH after tRSF. The Empty Flag (EFA, EFB) and
Programmable Almost-Empty Flag (PAEA, PAEB) will be
reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to
their default values.
WRITE CLOCK (WClKA, WClKB)
A write cycle is initiated on the LOW-to-HIGH transition of
the write clock (WCLKA, WCLKB). Data set-up and hold times
must be met with respect to the LOW-to-HIGH transition of
WCLK.
The write and read clocks can be asynchronous or
coincident.
WRITE ENABLE (WENA, WENB)
When Write Enable (WENA, WENB) is LOW, data can be
loaded into the input register and RAM array on the LOW-toHIGH transition of every WCLK. Data is stored in the RAM
array sequentially and independently of anyon-going read
operation.
When WEN is HIGH, the input register holds the previous
data and no new data is loaded into the FIFO.
To prevent data overflow, FFwili go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle,
the FF will go HIGH after tWFF allowing a write to begin. WEN
is ignored when the FIFO is full.
lOAD (LOA, LOB)
The IDT72805LB172815LB172825LB devices contain two
10-bit offset registers with data on the inputs, or read on the
outputs. When the Load (LOA, LOB) pin is set LOW and WEN
is set LOW, data on the inputs 00-019 is written into the Empty
offset register on the first LOW-to-HIGH transition of WCLK.
When LD and WEN are held LOW then data is written into the
Full offset register on the second LOW-to-HIGH transition of
WCLK. The third transition of WCLK again writes to the Empty
offset register.
However, writing all offset registers does not have to occur
at one time. One ortwo offset registers can be written and then
by bringing LD HIGH, the FIFO is returned to normal read!
write operation. When LD is set LOW, and WEN is LOW, the
next offset register in sequence is written.
When LD is LOW and WEN is HIGH, the WCLK input is
disabled; then a signal at this input can neither increment the
write offset register pointer, nor execute a write.
The contents of the offset registers can be read on the
output lines when LD is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of RCLK. The
act of reading the control registers employs a dedicated read
offset register pointer. (The read and write pointers operate
independently) .
A read and a write should not be performed simultaneously
to the offset registers.
READ CLOCK (RCLKA, RCLKB)
Data can be read on the outputs on the LOW-to-HIGH
transition of the read clock (RCLKA, RCLKB), when the
Output Enable (OEA, OEB) is set LOW.
The write and read clocks can be asynchronous or
coincident.
READ ENABLE (RENA, RENB)
When Read Enable (RENA, RENB) is LOW, data is loaded
into the RAM array to the output register on the LOW-to-HIGH
transition of the RCLK.
When REN is HIGH, the output register holds the previous
data and no new data is loaded into the register.
When all the data has been read from the FIFO, EFwill go
LOW, inhibiting further read operations. Once a write is
LOA
LOB
WENA
WENB
0
0
WCLKA(l)
WCLKB(l)
S
Selection
Writing to offset registers:
Empty Offset
Full Offset
0
1
1
0
1
1
S
S
S
0
No Operation
Write Into FIFO
No Operation
NOTE:
3139 tbl 08
1. The same selection sequence applies to reading from the registers. REN
is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
5.09
Figure 2. Write Offset Register
6
II
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-8IT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
FIRST LOAD (FLA, FLB)
First Load (FLA, FLB) is grounded to indicate operation in
the Single Device or Width Expansion mode. In the Depth
Expansion configuration, FL is grounded to indicate it is the
first deBvice loaded and is set to HIGH for all other devices in
the daisy chain. (See Operating Configurations for further
details.)
EMPTY FLAG (EFA, EFB)
The Empty Flag (EFA, EFB) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write
pointer, indicating the device is empty.
The EFis updated on the LOW-to-HIGH transition of RCLK.
WRITE EXPANSION INPUT (WXIA, WXIB)
This is a dual purpose pin. Write Expansion In (WXIA,
WXIB) is grounded to indicate operation in the Single Device
or Width Expansion mode. WXI is connected to Write Expansion Out (WXOA, WXOB) of the previous device in the Depth
Expansion or Daisy Chain mode.
o
EMPTY OFFSET REGISTER
DEFAULT VALUE
001 FH (72805) 003FH (72815):
007FH 72825
o
READ EXPANSION INPUT (AXIA, AXIB)
This is a dual purpose pin. Read Expansion In (RXIA, RXIB)
is grounded to indicate operation in the Single Device or Width
Expansion mode. RXI is connected to Read Expansion Out
(RXOA, RXOB) of the previous device in the Depth Expansion
or Daisy Chain mode.
OUTPUTS:
FULL OFFSET REGISTER
DEFAULT VALUE
001 FH (72805) 003FH (72815):
007FH 72825
3139 drw 03
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
FULL FLAG (FFA, FFB)
The Full Flag (FFA, FFB) will go LOW, inhibiting further write
operation, indicating that the device is full. If no reads are
performed after RS, FF will go LOW after 256 writes for the
IDT72805LB, 512 writes for the IDT72815LB, 1024 writes for
the IDT72825LB. FF is updated on the LOW-to-HIGH transition of WCLK.
Figure 3. Offset Register Location and Default Values
TABLE 1- STATUS FLAGS
FFA
PAFA
HFA
PAEA
EFA
72805
Number of Words in FIFO
72815
72825
FFB
PAFB
HFB
PAEB
EFB
0
1 to n(1)
0
1 to n{l)
0
1 to n(1)
H
H
H
L
L
H
H
H
L
H
H
(n + 1) to 128
(n + 1) to 256
(n+1)t0512
H
H
H
H
129to (256-(m+1))
257 to (512-(m+1))
513 to (1024-(m+1))
H
H
L
H
H
(256-m){2) to 255
(512-m){2) to 511
(1 024-m){2) to 1023
H
L
L
H
H
256
512
1024
L
L
L
H
NOTES:
1. n = Empty Offset (Default Values: 72805 n=31, 72815 n = 63, 72825 n = 127)
2. m = Full Offset (Default Values: 72805 n=31, 72815 n = 63, 722825 n = 127)
H
3139 tbl 09
PROGRAMMABLE ALMOST-FULL FLAG (PAFA, PAFB)
The Programmable Almost-Full Flag (PAFA, PAFB) will go
LOW when FIFO reaches the Almost-Full condition. If no
reads are performed after RS, the PAFwili go LOW after (256m) writes for the IDT72805LB, (512-m) writes for the
IDT72815LB, (1 024-m) writes forthe IDT72825LB. The offset
"m" is defined in the FULL offset register.
If there is no Full offset specified, the PAFwill be LOWwhen
the device is 31 away from completely full for 72805LB, 63
away from completely full for 72815LB, and 127 away from
completely full for 72825LB.
The PAF is asserted LOW on the LOW-to-HIGH transition
of the WCLK. PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK. Thus PAF is asychronous.
5.09
7
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18,512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE ALMOST·EMPTY FLAG (PAEA,
PAEB)
The Programmable Almost-Empty Flag (PAEA, PAEB) will
go LOW when the read pointer is un" locations less than the
write pointer. The offset "n" is defined in the EMPTY offset
register.
If there is no Empty offset specified, PAE will be LOW when
the device is 31 away from completely empty for 72805LB, 63
away from completely emptyfor72815LB, and 127 away from
completely empty for 72825LB.
The PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition
of WCLK. Thus PAF is asychronous.
WRITE EXPANSION OUT/HALF·FULL FLAG
(WXOAlHFA, WXOBlHFB)
This is a dual-purpose output. In the Single Device and
Width Expansion mode, when WXI is grounded, this output
acts as an indication of a half-full memory.
After half of the memory is filled, and at the LOW-to-HIGH
transition of the next write cycle, the Half-Full Flag goes LOW
and will remain set until the difference between the write
pOinter and read pOinter is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HFA, HFB) is
then reset to HIGH by the LOW-to-HIGH transition of the read
clock (RCLK). The HF is asychronous.
In the Depth Expansion or Daisy Chain mode, WXI is
connected to WXO of the previous device. This output acts as
a signal to the next device in the Daisy Chain by providing a
pulse when the previous device writes to the last location of
memory.
READ EXPANSION OUT (RXOA, RXOB)
In the Depth Expansion or Daisy Chain configuration, Read
Expansion In (RXIA, RXIB) is connected to Read Expansion
Out (RXOA, RXOB) of the previous device. This output acts as
a signal to the next device in the Daisy Chain by providing a
pulse when the previous device reads from the last location of
memory.
DATA OUTPUTS (OOA·OA17, OBO·OB17)
00-017 are data outputs for 18-bit wide data.
II
----I~_--
EF ,PAE
tRSR - - - - - "
~~~~~~~~~~~~~~~~~-------------------
FF, PAF, HF
t RSF
OE-1(1)
Qo -
017
~'%,~~~---------------------------------------------------- - - -0- - - -~- -----------------OE=O
NOTES:
1. After reset, the outputs will be LOW if OE 0 and tn-state if OE
2. The clocks (RCLK, WCLK) can be free-running during reset.
=
3139drw04
=1.
Figure 4. Reset Timing(2)
5.09
8
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
tCLK----------------~
WCLK
WEN
'----NO
OPERATION
tWFF-----~
tWFF
FF
tSKEW1 (1)
RCLK
REN
/
3139 drw 05
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
5.09
9
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
tCLKL
RCLK
NO OPERATION
REN
tREF - - - - ' " '
EF
00 - 017
VALID DATA
OE
tSKEW2 (1)
WCLK
WEN
NOTE:
I
"
3139 drw 06
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the
time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
5.09
10
II
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
WCLK
DO-D17~~~~
RCLK
EF ________________________________- '
REN ~__________________________________________~---------------_+-----------------------
tOll
1--------
OE _ _ _ _ _ _ _ _ _ _ _ _ _..........
tOE
3139 drw 07
NOTES:
1. When tSKEW2 ~ minimum specification, tFRL (maximum) tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum)
tSKEW20rtCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF LOW).
2. The first word is available the cycle after EF goes HIGH, always.
=
=
=either
2 * tCLK +
Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write
5.09
11
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
WCLK
DO - D17
FF __________+-____________
RCLK
OE
00 - 017
LOW
DATA IN OUTPUT REGISTER
DATA READ
EXT DATA READ
3139 drw 11
NOTE:
1. tSKEWl is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FFwill go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 8. Full Flag Timing
5.09
12
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
Do - 017
DATA WRITE 1
(
tENH
~_ _ _ _ _ _ _
OE
COMMERCIAL TEMPERATURE RANGE
~_ _ _ _ _ _ _ tFRL (1) _ _ _~
tFRL (1) _ _ _~
LOW
tA~~
00 - 017
DATA IN OUTPUT REGISTER
---1'________
D_A_T_A_R_EA_D
_ _ _ __
3139 drw09
NOTE:
1. When tSKEW2 <: minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL(maximum)=either2*tcLK + tSKEW2.
or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
5.09
13
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
WCLK
DO-D15
Figure 10. Write Programmable Registers
RCLK
00-015
Figure 11. Read Programmable Registers
5.09
14
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
tCLKH 1 . - - -......J...oI~-___.j tCLKL
WCLK
tENS~
r.
tENH
tPAE
n + 1 words
in FIFO
n words in FIFO
RCLK
tENS
T"\
REN------------------------------~~~~
3139 drw 12
NOTE:
1. PAE is offset = n. Number of data words written into FIFO already = n.
Figure 12. Programmable Almost Empty Flag Timing
tCLKH 1 4 - -__....I---I~ tCLKL
WCLK
Full-m words
in FIFO(2)
Full- (m + 1) words
in FIFO(3)
3139 drw 13
NOTES:
1. PAF offset = m. Number of data words written into FIFO already = 256 - (m + 1) for the IDT72805LB. 512 - (m + 1) for the IDT72815LB. 1024 - (m + 1)
for the IDT72825LB.
2. 256 - m words in IDT72805LB. 512 - m words in IDT72815LB. 1024 - m words in IDT72825LB.
3. 256 - (m + 1) words in IDT72805LB. 512 - (m + 1) words in IDT72815LB. 1024 - (m + 1) words in IDT72825LB.
Figure 13. Programmable Almost-Full Flag Timing
5.09
15
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
tCLKH ~--__"""I----I~ tCLKL
WCLK
Half Full + 1
or More
Half Full or Less
Half Full or Less
RCLK
tENS"
~
3139 drw 14
II
Figure 14. Half-Full Flag Timing
WCLK
3139 dlW 15
NOTE:
1. Write to Last Physical Location.
Figure 15. Write Expansion Out Timing
RCLK
3139 dlW 16
REN
NOTE:
Figure 16. Read Expansion Out Timing
5.09
16
IDT72805172815172825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
WCLK
3139 drw 17
Figure 17. Write Expansion In Timing
Figure 18. Read Expansion In Timing
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72805LB/
72815LB172825LB may be operated as a stand-alone device
when the application requirements are for 256/51211024
words or less. The IDT72805LB172815LB/72825LB are in a
single Device Configuration when the Write Exansion In
(WXI), Read Expansion In (AXI), and First Load (FL) control
inputs are grounded (Figure 19).
l
WRITE CLOCK (WCLK)
RESET (RS)
READ CLOCK (RCLK)
WRITE ENABLE ~EN)
READ ENABLE (REN)
LOAD (LD)
lOT
72805LBI
72815LBI
72825LB
DATA IN (OJ - 017)
OUTPUT ENABLE
(bE)
DATA OUT (OJ - 017)
r
FIFO A or B
FULL FLAG (FF)
EMPTY FLAG (EF)
PROGRAMMABLE (PAE)
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
FIRST LOAD (FL)
t
t
---1-
t
READ EXPANSION IN (AXI)
WRITE EXPANSION IN
-
~I)
3139 drw 19
Figure 19. Block Diagram of Single 256 x 18/512 x 18/1024 x 18 Synchronous FIFO
(One of the Two FIFOs contained in the 72805172815172825)
5.09
17
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18. 512 x 18. and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
WIDTH EXPANSION CONFIGURATION - Word width
may be increased simply by connecting together the control
signals of FI FOs A and B. A composite flag should be created
for each of the end-point status flags (EFA and EFB, also FFA
and FFB). The partial status flags (PAEA and PAEB, also
J
PAFA and PAFB) can be detected from anyone device.
Figure 20 demonstrates a 36-bit word width using the two
FIFOs contained in one IDT72805172815172825. Any word
width can be attained by adding additiona11DT28051728151
72825.
18
f
RESET
72805/
72815/
72825
DATA IN
,18
/36
I
RSA
DAO - DA17
/
WRITE CLOCK
WCLKA
WRITE ENABLE
WENA
RSB
DBO- DB17
r-L--
r--"--
FIFO A
-
256x18
512x18
1024X18
...... FIFOB
RCLKA
WCLKB
RENA
WENB
OEA
256x18
o12x'rn
1024x18
-
I
EFA
EFB
EMPTY FLAG.
1
RCLKB
READ CLOCK
RENB
READ ENABLE
OEB
OUTPUT ENABLE
f--
FULL FLAG
FFA
~
I
-
FFB
L---
t--
1
I~
J 18
OBO - OB17
I
/36
DATA OUT
I
II
OAO-OA17
J 18
3139 drw20
I
NOTE:
1. Do not tie any output control signals directly together.
2. Tie FLA, FLB, WXIA, WXIB, AXIA and AXIB to GND.
Figure 20. Block Diagram of the two FIFOs contained in one 72805n2815n2825
configured for a 36-bit Width Expansion
DEPTH EXPANSION CONFIGURATION
(WITH PROGRAMMABLE FLAGS)
The IDT72805LB172815LB172825LB can easily be adapted
to applications requiring more than 256/51211024 words of
buffering. Figure 21 shows a Depth Expansion using the two
FIFOs contained in one IDT72805LB172815LB172825LB.
Maximum depth is limited only by signal loading. Followthese
steps:
1. The first FIFO must be designated by grounding the
First Load (FL) control input.
2. All other FIFOs must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device
must be tied to the Write Expansion In (WXI) pin of
the next FIFO.
5.09
4. The Read Expansion Out (AXO) pin of each device
must be tied to the Read Expansion In (AXI) pin of
the next FIFO.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth
Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite
flags by ORing together every respective flags for
monitoring. The composite PAE and PAF flags are not
precise.
18
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
~~
IrWXOA
I
I
I
RXOA
LOA
RCLKA
WCLKA
RENA
OEA
WEN A
RSA
OAn
DAn
I
I
I
FIFOA
Vee
TFIRST LOAD I
1024x18
FLA
I
I
I
~mlA
I 72825~IA~I
FFA
DATA IN
EFA
WXOB
WRITE CLOCK
WRITE ENABLE
I
RESET
LOAD
I
I
FULL FLAG
1
f
J
I
FIRST LOAD
+
I
RXOB
WCLKB RCLKB
WENB
RENB
RSB
OEB
DBn
LDB
OBn
READ CLOCK
READ ENABLE
J
FIFOB
I
1024x18
FFB
EFB
I
FLB
WXIB
- f-
DATA OUT
RXIB
OUTPUT ENABLE
I
EMPTY FLAG
I
I
f-
3139drw21
Figure 21. Block Diagram of 2048 x 18 Synchronous FIFO Memory With Programmable
Flags used in Depth Expansion Configuration
5.09
19
IDT72805n2815n2825 CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
xxxxx
x
xx
x
x
Device Type
Power
Speed
Package
Process /
Temperature
Range
~BLANK
Commercial (O°C to +70°C)
BG
Ball Grid Array
20
25
35
}
LB
Low Power
72805
72815
72825
256 x 18 Dual Synchronous FIFO
512 x 18 Dual Synchronous FIFO
1024 x 18 Dual Synchronous FIFO
Commercial Only
Clock Cycle Time (teu<)
Speed in Nanoseconds
3139 drw 22
5.09
20
II
G®
IDT723611
BiCMOSClocked FIFO
64x36
Integrated Device Technology, Inc.
FEATURES:
• Free-running ClKA and ClKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
64 x 36 storage capacity
Synchronous data buffering from Port A to Port B
Mailbox bypass register in each direction
Programmable Almost-Full (AF) and Almost-Empty (AE)
flags
Microprocessor Interface Control logic
Full Flag (FF) and Almost-Full (AF) flags synchronized by
ClKA
Empty Flag (EF) and Almost-Empty (AE) flags synchronized by ClKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Supports clock frequencies up to 67MHz
• Fast access times of 10ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• low-power advanced BiCMOS technology
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power,
BiCMOS Synchronous (clocked) FIFO memory which supports clock frequencies up to 67MHz and has read access
times as fast as 1Ons. The 64 x 36 dual-port FIFO buffers data
from PortA to Port B. The FIFO has flags to indicate empty and
full conditions, and two programmable flags, Almost-Full (AF)
and Almost-Empty (AE), to indicate when a selected number
of words is stored in memory. Communication between each
port can take place through two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been
stored. Parity is checked passively on each port and may be
FUNCTIONAL BLOCK DIAGRAM
ClKA
CSA
WiRA
ENA
MBA
PGB
Reset
logic
36
Ao - /435
~
_ _~.
Bo - 835
FF~------~~------------~
r--------------------~~~~~-
AF~------+;-r----rl--------_L__~--Jr--------------4-------~~~----
,-FIFO-
EF
AE
-'
FSo ________~~----------~
FS1 ________~~----------~
Port-B
Control
~
logic
ClKB
CSB
W/RB
ENS
_______r--MBB
3024 drw 01
Sync FIFO is a trademark and the lOT logo is a registered trademark of Integrated Device Technology, Inc.
APRIL 1995
COMMERCIAL TEMPERATURE RANGE
DSC-205811
©1995 Integrated Device Technology, Inc.
5.10
1
IOTI23611 BiCMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
ignored if not desired. Parity generation can be selected for
data read from each port. Two or more devices may be used
in parallel to create wider data paths.
The IDT723611 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide
a simple bidirectional interface between microprocessors
and/or buses with synchronous control.
The Full-Flag (FF) and Almost-Full (AF) flag of the FIFO are
two-stage synchronized to the port clock that writes data into
its array (CLKA). The Empty Flag (EF) and Almost-Empty (AE)
flag of the FIFO are two-stage synchronized to the port clock
that reads data from its array.
The IDT723611 is characterized for operation from ODC to
70 D C.
PIN CONFIGURATION
A23
A22
A21
822
821
GND
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
PN120-1
820
819
818
817
B16
815
814
813
812
811
810
II
GND
GND
B9
88
87
A9
A8
A7
Vec
Vcc
86
85
84
83
A6
A5
A4
A3
GND
GND
B2
81
Bo
EF
AE
A2
A1
Ao
NC
NC
NC
TQFP
TOP VIEW
Note:
1.
NC
=No internal connection
5.10
2
IDT723611 BiCMOS SyncFIFOTM
64x36
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION (CONTINUED)
GND
GND
NC
NC
Ao
AE
EF
80
81
Al
A2
82
GND
GND
A3
83
A4
A5
A6
85
84
86
Vee
Vee
A7
87
A8
A9
88
89
GND
GND
AlO
810
A11
Vee
Vee
A12
A13
813
811
812
A14
814
GND
GND
A15
A16
815
816
A17
817
A18
A19
818
819
A20
820
GND
GND
A21
821
A22
822
823
A23
3024 drw 03
PQFPACKAGE
TOP VIE\/Il
5.10
3
IDT723611 BiCMOS SyncFIFOTM
64x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
I/O
Description
Port-A Data
I/O 36-bit bidirectional data port for side A.
AE
Almost-Empty Flag
a
Programmable almost-empty flag synchronized to ClKB. It is lOW when
the number of words in the FIFO is less than or equal to the value in the offset
reQister, X.
AF
Almost-Full Flag.
a
Programmable almost-full flag synchronized to ClKA. It is lOW when the
number of empty locations in the FIFO is less than or equal to the value in the
offset register, X.
BO-B35
Port-B Data.
I/O 36-bit bidirectional data port for side B.
ClKA
Port-A Clock
I
ClKA is a continuous clock that synchronizes all data transfers through port-A
and can be aynchronous or coincident to ClKB. FF and AF are synchronized
to the lOW-to-HIGH transition of ClKA.
ClKB
Port-B Clock
I
CSA
Port-A Chip Select
I
ClKB is a continuous clock that synchronizes all data transfers through port-B
and can be asynchronous or coincident to ClKA. EF and AE are synchronized
to the lOW-to-HIGH transition of ClKB.
CSA must be lOW to enable a lOW-to-HIGH transition of ClKA to read or
write data on port-A. The AO-A35 outputs are in the high-impedance state
when CSA is HIGH.
CSB
Port-B Chip Select
I
CSB must be lOW to enable a lOW-to-HIGH transition of ClKB to read or
write data on port-B. The BO-B35 outputs are in the high-impedance state
when CSB is HIGH.
Empty Flag
a
EF is synchronized to the lOW-to-HIGH transition of ClKB. When EF is lOW,
the FIFO is empty, and reads from its memory are disabled. Data can be read
from the FIFO to its output register when EF is HIGH. EF is forced lOW when
the device is reset and is set HIGH by the second lOW-to-HIGH transition of
ClKB after data is loaded into empty FIFO memory.
AO-A35
EF
ENA
Port-A Enable
I
ENA must be HIGH to enable a lOW-to-HIGH transition of ClKA to read or
write data on port-A.
ENB
Port-B Enable
I
ENB must be HIGH to enable a lOW-to-HIGH transition of ClKB to read or
write data on port-B.
Full Flag
a
FF is synchronized to the lOW-to-HIGH transition of ClKA. When FF is lOW,
the FIFO is full, and writes to its memory are disabled. FF is forced lOW when
the device is reset and is set HIGH by the second lOW-to-HIGH transition of
ClKA after reset.
Flag-Offset Selects
I
The lOW-to-HIGH transition of RST latches the values of FSO and FS1,
which loads one of four preset values into the almost-full and almost-empty
offset register (X).
MBA
Port-A Mailbox Select
I
A HIGH level on MBA chooses a mailbox register for a port-A read or write
operation.
MBB
Port-B Mailbox Select
I
A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the BO-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a lOW level selects the FIFO
output register data for output.
MBF1
Mail1 Register Flag
a
MBF1 is set lOW by a lOW-to-HIGH transition of ClKA that writes data to
the ma~ister. Writes to the mail1 register are inhibited while MBF1 is set
lOW. MBF1 is set HIGH by a lOW-to-HIGH transition of ClKB when a port-B
read is selected and MBB is HIGH. MBF1 is set HIGH when the device is
reset.
FF
FS1, FSO
5.10
4
II
I
IDT723611 BICMOS SyncFIFOTM
64x36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
110
MBF2
Mail2 Register Flag
0
MBF2 is set LOW by a LOW-to-HIGH transition of ClKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while MBF2 is
lOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a portA read is selected and MBA is HIGH. MBF2 is set HIGH when the device is
reset.
000/
Odd/Even Parity
Select
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even
parity is checked when ODD/EVEN is lOW. ODD/EVEN also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
Svmbol
EVEN
Description
PEFA
Port-A Parity Error
Flag
0
When any byte applied to terminals AO-A35 fails parity, PEFA is LOW.
(Port A) Bytes are organized as AO-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the Rarity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the AO-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected ..Qy£GA. Therefore, if a mi!il2 read with
parity generation is setup by having CSA LOW, ENA HIGH, W/RA LOW, MBA
HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of
AO-A35 inputs.
PEFB
Port-B Parity Error
Flag
0
When any byte applied to terminals BO-B35 fails parity, PEFB is LOW.
(Port B) Bytes are organized as BO-B8, B9-B17, B18-B26, B27-B35, with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the BO-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected ..Qy£GB. Therefore, if a mi!il1 read with
parity generation is setup by having CSB LOW, ENB HIGH, W/RB LOW,
MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the
state of the BO-B35 inputs
PGA
Port-A Parity
Generation
I
Parity is generated for mail2 register reads from port A when PGA is HIGH.
The type of parity generated is selected by the state of the ODD/EVEN input.
Bytes are organized as AO-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB
Port-B Parity
Generation
I
Parity is generated for data reads from port B when PGB is HIGH. The type
of parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as BO-B8, B9-B 17, B 18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
RST
Reset
I
To reset the device, four lOW-to-HIGH transitions of ClKA and four lOW-toHIGH transitions of ClKB must occur while RST is LOW. This sets the AF,
MBF1, and MBF2 fla~GH and the EF, AE, and FF flags LOW. The LOWto-HIGH transition of RST latches the status of the FS1 and FSO inputs to
select almost-full and almost-empty flag offset.
W/RA
Port-A Write/Read
Select
I
A HIGH selects a write operation and a lOW selects a read operation on
port A for a LOW-to-HIGH tran~ion of CLKA. The AO-A35 outputs are in the
high-impedance state when W/RA is HIGH.
W/RB
Port-B Write/Read
Select
I
A HIGH selects a write operation and a lOW selects a read operation on
port B for a lOW-to-HIGH tran~ion of elKB. The BO-B35 outputs are in the
high-impedance state when W/RB is HIGH.
5.10
5
IDT723611 BiCMOS SyncFIFOTM
64x 36
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol
Rating
VCC
W 2)
Supply Voltage Range
VO(2)
Commercial
Unit
-0.5 to 7
V
Input Voltage Range
-0.5 to Vcc+0.5
V
Output Voltage Range
-0.5 to Vcc+0.5
V
±20
rnA
rnA
11K
Input Clamp Current, (VI < 0 or VI > Vee)
10K
Output Clamp Current, (Vo = < 0 or Vo > Vee)
±50
lOUT
Continuous Output Current, (Vo = 0 to Vee)
±50
rnA
lee
Continuous Current Through Vee or GND
±500
TA
Operating Free Air Temperature Range
Oto 70
rnA
DC
TSTG
Storage Temperature Range
-65 to 150
DC
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min. Max. Unit
Vee
Supply Voltage
VIH
High-Level Input Voltage
4.5
5.5
VIL
Low-Level Input Voltage
0.8
V
10H
High-Level Output Current
-4
rnA
10L
Low-Level Output Current
8
TA
Operating Free-Air
Temperature
rnA
DC
2
V
V
0
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions
Min.
= -4 rnA
2.4
Typ.(1)
Max.
Unit
VOH
Vee
Vee
10L = 8 rnA
0.5
V
III
= 4.5V,
= 4.5 V,
Vee = 5.5 V,
10H
VOL
VI = Vee or 0
±50
IlA
ILO
Vee = 5.5 V,
vo = Vec or 0
lee
Vee = 5.5 V,
10 = 0 rnA,
VI = Vee or GND
V
±50
IlA
Outputs HIGH
60
rnA
Outputs LOW
130
Outputs Disabled
60
CIN
VI=O,
f = 1 MHz
4
pF
COUT
Vo=O,
f = 1 MHZ
8
pF
Notes:
1. All typical values are at Vee = 5 V, TA = 25 DC.
5.10
6
IDT723611 BiCMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGES
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURES
IDT723611L15 IDT723611L20 IDT723611L30
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fs
Clock Frequency, ClKA or ClKB
-
66.7
-
50
-
33.4
Mhz
tCLK
Clock Cycle Time, ClKA or ClKB
15
20
6
tCLKL
Pulse Duration, ClKA or ClKB lOW
6
tDS
Setup Time, AO-A35 before ClKAi and BO-B35
before ClKBi
4
5
6
-
Mhz
Pulse Duration, ClKA or ClKB HIGH
-
30
tCLKH
-
tENS1
CSA, WiRA, before ClKAi; CSB, WiRB before
ClKBi
6
-
6
-
7
-
ns
tENS2
ENA before ClKAi; ENB before ClKBi
4
4
Setup Time, ODD/EVEN and PGB before
ClKBi(l)
4
5
6
-
ns
tPGS
-
6
MBA before ClKAi; ENB before ClKBi
-
5
tENS3
tRSTS
Setup Time, RST lOW before ClKAi
or ClKBi(2)
5
-
6
-
7
-
ns
tFSS
Setup Time, FSO and FS1 before RST HIGH
5
1
1
-
ns
1
-
7
Hold Time, AO-A35 after ClKA i and BO-B35
after ClKBi
-
6
tDH
tENH1
CSA, W/RA after ClKAi; CSB, W/RB
after ClKBi
1
-
1
-
1
-
ns
tENH2
ENA after ClKAi; ENB after ClKBi
1
8
8
5
1
tENH3
MBA after ClKA i; MBB after ClKBi
1
tPGH
Hold Time, ODD/EVEN and PGB after ClKBi(l)
0
-
0
tRSTH
Hold Time, RST lOW after ClKA i or ClKBi(2)
6
-
6
tFSH
Hold Time, FSO and FS1 after RST HIGH
4
4
tSKEW1(3j Skew Time, between ClKAi and ClKBi
for EF, FF
8
-
tSKEW2(3j Skew Time, between ClKAi and ClKBi
for AE, AF
9
-
12
12
6
1
1
8
16
-
ns
ns
ns
ns
ns
ns
ns
1
-
ns
ns
10
-
20
-
ns
0
7
4
ns
ns
ns
Notes:
1. Only applies for a rising edge of ClKB that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and ClKB cycle.
5.10
7
IDT723611 BiCMOS SyncFIFOTM
64x36
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL 30 pF
=
IDT723611L15 IDT723611L20 IDT723611L30
Svmbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fs
Clock Frequency, CLKA or CLKB
-
66.7
-
50
-
33.4
MHz
tA
Access Time, CLKBi to BO-B35
2
10
2
12
2
15
ns
tWFF
Propagation Delay Time, CLKAito FF
2
10
2
12
2
15
ns
tREF
Propagation Delay Time, CLKBi to EF
2
10
2
12
2
15
ns
tPAE
Propagation Delay Time, CLKBi to AE
2
10
2
12
2
15
ns
tPAF
Propagation Delay Time, CLKAito AF
2
10
2
12
2
15
ns
tPMF
Propagation Delay Time, CLKAito MBF1
LOW or MBF2 HIGH and CLKBi to MBF2
LOW or MBF1 HIGH
1
9
1
12
1
15
ns
tPMR
Propagation Delay Time, CLKAito BO-B35(1)
and CLKBi to AO-A35(2)
3
12
3
14
3
16
ns
tMOV
Propagation Delay Time, MBB to BO-B35 Valid
1
11
1
11.5
1
12
ns
tpOPE
Propagation Delay Time, AO-A35 Valid to PEFA
Valid; BO-B35 Valid to PEFS Valid
3
12
3
13
3
14
ns
tpOPE
Propagation Delay Time, ODD/EVEN to PEFA
and PEFS
3
11
3
12
3
14
ns
tPoPS(3)
Propagation Delay Time, ODD/EVEN to Parity
Bits (A8, A 17, A26, A35) and (B8, B 17, B26,
B35)
2
12
2
13
2
15
ns
tPEPE
Propagation Delay Time, CSA, ENA, W/RA,
MBA, or PGAto PEFA; CSB, ENB, WiRB,
MBB, or PGB to PEFS
1
12
1
13
1
15
ns
tPEPS(3)
Propagation Delay Time, CSA, ENA W/RA,
MBA, or PGA to Parity Bits (A8, A17, A26,
A35); CSB, ENB, WJRB, MBB, or PGB to Parity
Bits (B8, B17, B26, B35)
3
14
3
15
3
16
ns
tRSF
Propagation Delay Time, RST to AE LOW and
(AF, MBF1, MBF2) HIGH
1
15
1
20
1
30
ns
tEN
Enable Time, GSA and W/RA LOW to AO-A35
Active and GSB LOW and W/RB HIGH to
BO-B35 Active
2
10
2
12
2
14
ns
tOIS
Disable Time, GSA or W/RA HIGH to AO-A35
at high impedance and GSB HIGH or W/RB
LOW to BO-B35 at high impedance
1
9
1
10
1
11
ns
II
I
Notes:
1. Writing data to the mail1 register when the BO-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the AO-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
5.10
8
IDT723611 BiCMOS SyncFIFOTM
64x36
COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTION
RESET (RSl)
The JDT723611 is reset by taking the reset (RST) input
LOW for at least four port-A clock (CLKA) and four port-B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of the FI FO and forces the fullflag (FF) LOW, the empty flag (EF) LOW, the almost-empty
flag (AE) LOW, and the almost-full flag (AF) HIGH. A reset also
forces the mailbox flags (MBF1, MBF2) HIGH. After a reset,
FF is set HIGH after two LOW-to-HIGH transitions of CLKA.
Almost-Full and
Almost-Empty Flag
Offset Register (X)
FS1
FSO
RST
16
H
H
12
H
L
8
L
H
4
L
L
i
i
i
i
Table 1. Flag Programming
The device must be reset after power up before data is written
to its memory.
A LOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty offset register (X) with the value
selected by the flag select (FSO, FS1) inputs. The values that
can be loaded into the register are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of the port-A data (AO-A35) outputs is controlled
by the port-A chip select (CSA) and the port-A write/read
select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or WiRA is HIGH. The AO-A35
outputs are active when both CSA and WiRA are LOW. Data
is loaded into the FIFO from the AO-A35 inputs on a LOW-toHIGH transition of CLKA when CSA is LOW, WiRA is HIGH,
ENA is HIGH, MBA is LOW, and FF is HIGH (see Table 2).
The port-B control signals are identical to those of port A.
The state of the port-B data (BO-B35) outputs is controlled by
the port-B chip select (CSB) and the port-B write/read select
(W/RB). The BO-B35 outputs are in the high-impedance state
when either CSB or W/RB is HIGH. The BO-B35 outputs are
active when both CSB and W/RB are LOW. Data is read from
the FIFO to the BO-B35 outputs by a LOW-to-HIGH transition
of ClKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB
is lOW, and EF is HIGH (see Table 3).
CSA
W/RA
ENA
MBA
CLKA
AO-A35 Outputs
H
X
X
None
H
L
X
X
In High-Impedance State
L
X
X
In High-Impedance State
None
H
L
In High-Impedance State
FIFO Write
In High-Impedance State
Mail1 Write
Port Functions
L
H
L
H
H
H
i
i
L
L
L
L
X
Active, Mail2 Register
None
L
L
H
L
i
Active, Mail2 Register
None
L
L
L
H
X
Active, Mail2 Register
None
L
L
H
H
i
Active, Mail2 Register
Mail2 Read (set MBF2 HIGH)
Table 2. Port-A Enable Function Table
CSB
W/RB
ENB
MBB
ClKB
BO-B35 Outputs
Port Functions
H
X
X
X
X
In High-Impedance State
None
In High-Impedance State
None
In High-Impedance State
None
In High-Impedance State
Mail2 Write
L
H
L
X
X
L
H
H
L
L
H
H
H
i
i
L
L
L
L
X
Active, FIFO Output Register
None
L
L
H
L
i
Active, FIFO Output Register
FIFO Read
L
L
L
H
X
Active, Mail1 Register
None
L
L
H
H
i
Active, Mail1 Register
Mail1 Read (set MBF1 HIGH)
Table 3. Port-B Enable Function Table
5.10
9
IDT723611 BiCMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGES
The setup and hold-time constraints to the port clocks for
the port chip selects (CSA, CSS) and write/read selects (W/
RA, W/RS) are only for enabling write and read operations and
are not related to HIGH-impedance control of the data outputs. If a port enable is lOW during a clock cycle, the port's
chip select and write/read select can change states during the
setup and hold-time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FI FO flag is synchronized to its port clock through two
flip-flop stages. This is done to improve the flags' reliability by
reducing the probability of mestastable events on their outputs
when ClKA and ClKS operate asynchronously to one another. FF and AF are synchronized to ClKA. EF and AE are
synchronized to ClKS. Table 4 shows the relationship to the
flags to the FIFO.
EMPTY FLAG (EF)
The FIFO empty flag is synchronized to the port clock that
reads data from its array (ClKS). When the empty flag is
HIGH, new data can be read to the FIFO output register.
When the empty flag is lOW, the FIFO is empty and attempted
FIFO reads are ignored.
The FIFO read pointer is incremented each time a new
word is clocked to its output register. The state machine that
controls an empty flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+ 1, or empty+2. A word written to the
FIFO can be read to the FIFO output register in a minimum of
three port-S clock (ClKS) cycles. Therefore, an empty flag is
lOW if a word in memory is the next data to be sent to the FIFO
output register and two ClKS cycles have not elapsed since
the time the word was written. The empty flag of the FIFO is
set HIGH by the second lOW-to-HIGH transition of ClKS,
and the new data word can be read to the FI FO output register
in the following cycle.
A lOW-to-HIGH transition oli ClKS begins the first synchronized cycle of a write if the clock transition occurs at time
tSKEW1 or greater after the write. Otherwise, the subsequent
Synchronized
Number of Words
Synchronized
to CLKB
to CLKA
in the FIFO
EF
AE
AF
FF
0
l
l
H
H
1 to X
H
l
H
H
H
(X+ 1) to [64-(X+ 1)]
H
H
H
(64-X) to 63
H
H
l
H
64
H
H
l
l
Table 4. FIFO Flag Operation
Note:
X is the value in the almost-empty flag and almost-full
flag register.
ClKS cycle can be the first synchronization cycle (see figure
4).
FULL FLAG (FF)
The FIFO full flag is synchronized to the port clock that
writes data to its array (ClKA). When the full flag is HIGH, an
SRAM location is free to receive new data. No memory
locations are free when the full flag is lOW and attempted
writes to the FIFO are ignored.
Each time a word is written to the FIFO, its write pointer is
incremented. The state machine that controls the full flag
monitors a write pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from the FIFO, its previous
memory location is ready to be written in a minimum of three
port-A clock cycles. Therefore, a full flag is lOW if less than
two ClKA cycles have elapsed since the next memory write
location has been read. The second lOW-to-HIGH transition
on ClKA after the read sets the full flag HIGH and data can be
written in the following clock cycle.
A lOW-to-HIGH transition on ClKA begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see
figure 5).
ALMOST-EMPTY FLAG (AE)
The FI FO almost empty-flag is synchronized to the port
clock that reads data from its array (ClKS). The state
machine that controls the almost-empty flag monitors a write
pointer and read pointer comparator that indicates when the
FIFO SRAM status is almost empty, almost empty+ 1, or
almost empty+2. The almost-empty state is defined by the
value of the almost-full and almost-empty offset register (X).
This register is loaded with one of four creset values during a
device reset (see reset above). The alm·)st-empty flag is lOW
when the FIFO contains X or less words in memory and is
HIGH when the FIFO contains (X+1) or more words.
Two lOW-to-HIGH transitions on the port-S clock (ClKS)
are required after a FIFO write for the almost-empty flag to
reflect the new level of fill. Therefore, the almost-empty flag
of a FI FO containing (X+ 1) or more words remains lOW if two
ClKS cycles have not elapsed since the write that filled the
memory to the (X+ 1) level. The almost-empty flag is set HIGH
by the second ClKS lOW-to-HIGH transition after the FIFO
write that fills memory to the (X+ 1) level. A lOW-to-HIGH
transition on ClKS begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the write that fills the
FI FO to (X+ 1) words. Otherwise, the subsequent ClKS cycle
can be the first synchronization cycle (see figure 6).
ALMOST FULL FLAG (AF)
The FIFO almost-full flag is synchronized to the port clock
that writes data to its array (ClKA). The state machine that
controls an almost-full flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almost-
5.10
10
II
IDT723611 BiCMOS SyncFIFOTM
64 x36
COMMERCIAL TEMPERATURE RANGES
empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset above).
The almost-full flag is lOW when the FIFO contains (64-X) or
more words in memory and is HIGH when the FIFO contains
[64-(X+ 1)] or less words.
Two lOW-to-HIGH transitions on the port-A clock (GlKA)
are required after a FIFO read for the almost-full flag to reflect
the new level of fill. Therefore, the almost-full flag of a FIFO
containing [64-(X+ 1)] or less words remains lOW if two GlKA
cycles have not elapsed since the read that reduced the
number of words in memory to [64-(X+ 1)]. The almost-full flag
is set HIGH by the second GlKA lOW-to-HIGH transition
after the FIFO. read that reduces the number of words in
memory to [64-(X+ 1)]. A lOW-to-HIGH transition on GlKA
begins the first synchronization cycle if it occurs at time tSKEW2
or greater after the read that reduces the number of words in
memory to [64-(X+ 1)]. Otherwise, the subsequent GlKA
cycle can be the first synchronization cycle (see figure 7).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723611 to pass
command and control information between port A and port B.
The mailbox-select (MBA, MBB) inputs choose between a
mail register and a FIFO for a port data transfer operation. A
lOW-to-HIGH transition on GlKA writes AO-A35 data to the
mail1 register when port-A write is selected by GSA, WiRA,
and ENA with MBA HIGH. A lOW-to-HIGH transition on
GlKB writes BO-B35 data to the mail2 register when port-B
write is selected by GSB, WiRB, and ENB with MBB HIGH.
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) lOW. Attempted writes to a mail register are
ignored while its mail flag is lOW.
When the port-B data (BO-B35) outputs are active, the data
on the bus comes from the FIFO output registerwhen the portB mailbox select (MBB) input is lOW and from the mail1
register when MBB is HIGH. Mail2 data is always present on
the port-A data (AO-A35) outputs when they are active. The
mail1 register flag (MBF1) is set HIGH by a lOW-to-HIGH
transition on GlKB when a port-B read is selected by GSB, W/
RB, and ENB with MBB HIGH. The mail2 register flag (MBF2)
is set HIGH by a lOW-to-HIGH transition on GlKA when a
port-A ·read is selected by GSA, WiRA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.
PARITY CHECKING
The port-A (AO-A35) inputs and port-B (BO-B35) inputs
each have four parity trees to check the parity of incoming (or
outgoing) data. A parity failure on one or more bytes of the
input bus is reported by a LOW level on the port parity error flag
(PEFA, PEFB). Odd or even parity checking can be selected,
and the parity error flags can be ignored if this feature is not
desired.
Parity status is checked on each input bus according to the
level of the odd/even parity (ODD/EVEN) select input. A parity
error on one or more bytes of a port is reported by a lOW level
on the corresponding port parity error flag (PEFA, PEFB)
output. Port-A bytes are arranged as AO-A8, A9-A 17, A 18A26, and A27-A35, and port-B bytes are arranged as BO-B8,
B9-B17, B18-B26, and B27-B35. When odd/even parity is
selected, a port parity error flag (PEFA, PEFB) is lOW if any
byte on the port has an odd/even number of lOW levels
applied to its bits.
The four parity trees used to check the AO-A35 inputs are
shared by the mail2 register when parity generation is selected for port-A reads (PGA=HIGH). When port-A read from
the mail2 register with parity generation is selected with GSA
lOW, ENA HIGH, wif5.A lOW, MBA HIGH, and PGA HIGH,
the port-A parity error flag (PEFA) is held HIGH regardless of
the levels applied to the AO-A35 inputs. Likewise, the parity
trees used to check the BO-B35 inputs are shared by the mail1
register when parity generation is selected for port-B reads
(PGB=HIGH). When a port-B read from the mail1 register with
parity generation is selected with GSB lOW, ENB HIGH, W/
RB lOW, MBB HIGH, and PGB HIGH, the port-B parity error
flag (PEFB) is held HIGH regardless of the levels applied to the
BO-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A parity generate select (PGA) or
port-B generate select (PGB) enables the IDT723611 to
generate parity bits for port reads from a FIFO or mailbox
register. Port-A bytes are arranged as AO-A8, A9-A 17, A 18A26, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as BO-B8, B9B 17, B 18-B26, and B27 -B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all thirty-six inputs regardless of the state of the parity generate select (PGA, PGB)
inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate
a parity bit according to the level on the ODD/EVEN select.
The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the
word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port-B parity generate select (PGB)
and ODD/EVEN have setup and hold time constraints to the
port-B clock (GlKB) for a rising edge of GlKB used to read a
new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port-B bus (BO-B35) to check parity and the
circuit used to generate parity for the mail2 data is shared by
the port-A bus (AO-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in
a mail register when the port write/read select (WiRA, W/RB)
input is lOW, the port mail select (MBA, MBB) input is HIGH,
chip select (GSA, GSB) is LOW, enable ENA, ENB) is HIGH,
and the port parity generate select (PGA, PGB) is HIGH.
Generating parity for mail register data does not change the
contents of the register.
5.10
11
IDT723611 BiCMOS SyncFIFOTM
64x36
COMMERCIAL TEMPERATURE RANGES
ClKA
ClKB
FS1,FSO
MBF1,
MBF2
II
Figure 1. Device Reset Loading the X Register with the Value of Eight
ClKA
WiRA
MBA
ENA
AO - A35
ODD!
EVEN
Valid
3024 drw 05
Figure 2. FIFO Write Cycle Timing
5.10
12
IDT723611 SiCMOS SyncFIFOTM
64x36
COMMERCIAL TEMPERATURE RANGES
elKB
EF
(HIGH)
CSB
W/RB
MBB
ENB
80 - 835
PGS,
0001
EVEN
3024 drw06
Figure 3. FIFO Read Cycle Timing
ClKA
CSA
WRA
MBA
ENA
FFA
AD - A35
ClKB
EF
______________=E~m~p~ty~F~IF~O~____________~?r
CSB
LOW
W/RB
LOW
~~--------------------
MBB
ENB
BO-B35
3024 drw07
Note:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFta transition HIGH in the next CLKS cycle. If the time between
the rising CLKA edge and rising CLKS edge is less than tSKEW1 , then the transition of EF HIGH may occur one CLKS cycle later than shown.
Figure 4. EF Flag Timing and First Data Read when the FIFO is Empty
5.10
13
IDT723611 BiCMOS SyncFIFOTM
64 x36
COMMERCIAL TEMPERATURE RANGES
ClKB
CSB
lOW
wiRB
lOW
MBB
lOW
ENB
EFB
BO-B35
ClKA
FF
CSA
II
WRA
MBA
ENA
AO - A35
3024 drwOB
Note:
1. tSKEW1 is the minimum time between a rising ClKS edge and a rising ClKA edge for FFto transition HIGH in the next ClKA cycle. If the time between
the rising ClKS edge and rising ClKA edge is less than tSKEW1, then the transition of FF HIGH may occur one ClKA cycle later than shown.
Figure 5. FF Flag Timing and First Available Write when the FIFO is Full
ClKA
ENA
ClKB
ENB
3024 drw 09
Notes:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next
CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may
transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA =L, WiRA = H, MBA = L), FIFO read (CSB =L, W/RB =L, MBB =L).
Figure 6. Timing for AE when the FIFO is Almost Empty
5.10
14
IDT723611 BiCMOS SyncFIFOTM
64x36
COMMERCIAL TEMPERATURE RANGES
ClKA
ENA
(64-X) Words in FIFO
[64-(X+l)) Words in FIFO
ClKB
ENB
3024 drw 10
Notes:
1.
2.
tSKEW2 is the minimum time between a rising GlKA edge and arising GlKB edge for AF to transition HIGH in the next
ClKA cycle. If the time between the rising GlKA edge and rising GlKB edge is less than tSKEW2, then AF may
transition HIGH one ClKB cycle later than shown.
FIFO write (GSA =l, WlRA = H, MBA = l), FIFO read (GSB =l, W/RB =l, MBB =L).
Figure 7. Timing for AFwhen the FIFO is Almost Full
ClKA
wifS.A
MBA
ENA
AO - A35
ClKB
W/RB
MBB
ENB
BO - B35
FIFO Output Register
3024 drw 11
Note:
1. Port-B parity generation off (PGB = l)
Figure 8. Timing for Maill Register and MBF1 Flag
5.10
15
101723611 BiCMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGES
ClKB
wiRB
MBB
ENB
BO - B35
ClKA
WiRA
II
MBA
ENA
AO - A35
3024 drw 12
Note:
1. Port-A parity generation off (PGA
= L)
Figure 9. Timing for Mail2 Register and MBF2 Flag
ODDI
EVEN
WiRA
MBA
PGA
Note:
1. CSA = Land ENA
= H.
Figure 10. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
5.10
16
IDT723611 BiCMOS SyncFIFOTM
64 x36
COMMERCIAL TEMPERATURE RANGES
0001
EVEN
W/RB
MBB
PGB
Valid
3024 drw 14
Note:
1. CSS
=L and ENS =H.
Figure 11. ODD/EVEN, WIRB, MBB, and PGB to PEFB Timing
0001
~~
EVEN
CSA
W/RA
LOW
~~
MBA
/ / /V / / / /
PGA
/ / /V / / / /
I-tEN
A8, A17,
A26,A35
Note:
1. ENA = H.
~
tPEP
Mail2 Data
_I
*
I---tPops-1
Generated Parity
X
CtPEPS
Generated Parity
_I
-I
)I(
Mail2 Data
3024 drw 15
Figure 12. Parity Generation Timing when reading from the Mail2 Register
0001
EVEN
CSB
~L~O~W~
__________________________
~
_____________________________________
W/RB
MBB
PGB
B8, B17,
B26,B35
Mail1 Data
3024 drw 16
Note:
1. ENS = H.
Figure 13. Parity Generation Timing when reading from the Mail1 Register
5.10
17
IDT723611 BiCMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGES
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENr.V
400
350
f data =1/2 f s
TA =25°C
CL
300
=0 pF
250
~
E
I
1:
200
~
~
()
>-
0..
c.
150
:::J
CI)
II
I
8()
100
50
0
0
10
20
40
30
50
60
70
80
f clock - Clock Frequency - MHz
3024 drw 17
Figure 14.
CALCULATING POWER DISSIPATION
The Icc(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT723611 with
ClKA and ClKS operating at frequency f8. All data inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.
Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from Figure 14, the maximum power dissipation (PT) of the IDT723611 may be calculated by:
PT
= Vcc x ICC(f) + I(CL x VOH - VOL)2 X fa)
where:
CL
fa
output capacitance load
switching frequency of an output
VOH
output high-level voltage
VOL
output low-level voltage
When no read or writes are occurring on the IDT723611 , the power dissipated by a single clock (ClKA or ClKS) input
running at frequency f8 is calculated by:
PT
=Vcc x f8 x 0.290 mA/MHz
5.10
18
IDT723611 BiCMOS SyncFIFOTM
64x 36
COMMERCIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kil
From Output
Under Test
_~
_ _ _ _ _.....
30pF(1)
680il
PROPAGATION DELAY
LOAD CIRCUIT
3V
Timing
Input
High-Level
Input
GND
3V
1.5 V
GND
tw
3V
Data,
Enable
Input
3V
Low-Level
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
GND
- "'3V
Input - {1.5 V
Low-Level
Qutput - - t - - "
tPD}
1.5 V
High-Level
Output
In-Phase
Output_____
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
3V
l~
. V-
tPD~
...-----1.5 V
GND
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3024 drw lB
Note:
1. Includes probe and jig capacitance.
Figure 15. Load Circuit and Voltage Waveforms
5.10
19
ID1723611 BiCMOS SyncFIFOTM
64x 36
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
xxxxxx
_x_
xx
__x_
x
Device Type
Power
Speed
Package
Process/
Temperature
Range
~
L...-------f
BLANK
Commercial WC to +70'C)
PF
PQF
Thin Quad Flat Pack
Plastic Quad Flat Pack
15
20
30
}
'----------------/ L
L...-------------------f
5.10
723611
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Low Power
64 x 36 Synchronous FIFO
3024 drw 19
20
II
'~J
PRELIMINARY
CMOS Clocked FIFO
IDT723613
With Bus Matching and Byte Swapping
64x36
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
• Free-running GlKA and GlKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• 64 x 36 storage capacity FIFO buffering data from Port A
to Port B
• Mailbox bypass registers in each direction
• Dynamic Port B bus sizing of 36-bits (long word), 18-bits
(word), and 9-bits (byte)
• Selection of Big- or Little-Endian format for word and byte
bus sizes
• Three modes of byte-order swapping on Port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• FF, AF flags synchronized by GlKA
• EF, AE flags synchronized by GlKB
• Passive parity checking on each Port
Parity Generation can be selected for each Port
low-power advanced BiGMOS technology
Supports clock frequencies up to 67 MHz
Fast access times of 10 ns
Available in 132-pin quad flatpack (POF) or space-saving
120-pin thin quad flatpack (TOFP)
DESCRIPTION:
The IDT723613 is a monolithic, high-speed, low-power,
BiGMOS synchronous (clocked) FIFO memory which supports clock frequencies up to 67 MHz and has read-access
times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO
buffers data from port A to port B. The FIFO has flags to
indicate empty and full conditions, and two programmable
flags, Almost-Full (AF) and Almost-Empty (AE), to indicate
when a selected number of words is stored in memory. FIFO
data on port B can be output in 36-bit, 18-bit, and 9-bit formats
FUNCTIONAL BLOCK DIAGRAM
ClKACSAWiRAENA-
Port-A
Control
logic
Ir----------r=~~==~================:::
I Parity I _
MBA- L...--r-r----r--rl
r-------,
RST 0001 _
EVEN
Device
Control
i
r-+-4-~-+-I---""~I:-~M~ailiI11
--ll~"""~ Gen/Check..r=,
Register
r~-----=;~====I=====I~-!-""""
;[J[~"il~1
64 x36
L ..
ro"
SRAM
36, I-
~
I
'---I------~
I
Write
Pointer
co
0..
4
I Read
Q)
fi5
C)
~
I
p;inter
1----"
:c Vcc)
±20
mA
10K
Output Clamp Current, (Vo < 0 or Vo > Vee)
±50
mA
lOUT
Continuous Output Current, (Vo = 0 to Vec)
±50
mA
Icc
Continuous Current Through Vee or GND
±500
mA
TA
Operating Free-Air Temperature Range
Oto 70
°C
TSTG
Storage Temperature Range
-65 to 150
°C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min. Max. Unit
Parameter
Vee
Supply Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
0.8
V
10H
High-Level Output Current
-4
mA
8
mA
70
°C
4.5
10L
Low-Level Output Current
TA
Operating Free-Air
Temperature
5.5
2
0
V
V
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions
Min.
2.4
Typ.(1)
Max.
Unit
V
VOH
Vee = 4.5V,
10H = -4 mA
VOL
Vee = 4.5 V,
10L = 8 mA
0.5
V
II
Vee = 5.5 V,
VI = Vee or 0
±50
loz
Vee = 5.5 V,
Vo = Vee or 0
Icc
Vee = 5.5 V,
10 = 0 mA,
VI = Vee or GND
±50
IlA
IlA
Outputs HIGH
60
mA
Outputs LOW
130
Outputs Disabled
60
Ci
VI =0,
f = 1 MHz
4
pF
Co
Vo=O,
f = 1 MHz
8
pF
NOTE:
1. All typical
values are at vee = 5 V. TA = 25°C.
5.11
6
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE (SEE FIGURE 4 THROUGH 18)
Symbol
IDT723613L15 IDT723613L20 IDT723613L30
Min.
Min.
Max.
Min.
Max.
Max.
Parameter
fs
Clock Frequency, ClKA or ClKB
-
66.7
-
Unit
50
-
33.4
MHz
ns
tCLK
Clock Cycle Time, ClKA or ClKB
15
-
20
-
30
tClKH
Pulse Duration, ClKA and ClKB HIGH
6
-
12
tClKl
Pulse Duration, ClKA and ClKB lOW
6
-
8
8
-
12
tos
Setup Time, AO-A35 before ClKA i and BO-B35
before ClKBi
4
-
5
-
6
-
tENS
Setup Time, CSA, WiRA, ENA, and MBA before
ClKAi; CSB,wiRB, and ENB before ClKBi
5
-
5
-
6
-
ns
5
-
6
-
8
5
-
6
-
ns
7
-
7
-
ns
ns
ns
ns
tszs
Setup Time, SIZO, SIZ1 ,and BE before ClKBi
4
tsws
Setup Time, SWO and SW1 before ClKBi
5
tPGS
Setup Time, ODD/EVEN and PGB before
ClKBi(1)
4
-
tRSTS
Setup Time, RST lOW before ClKA i
or ClKBi(2)
5
-
6
tFSS
Setup Time, FSO and FS1 before RST HIGH
5
-
7
1
1
-
1
-
ns
Hold Time, AO-A35 after ClKA i and BO-B35
after ClKBi
-
6
tOH
tENH
Hold Time, CSA W/RA, ENA and MBA after
ClKAi; CSB, WiRB, and ENB after ClKBi
1
-
1
-
1
-
ns
tSZH
Hold Time, SIZO, SIZ1, and BE after ClKBi
2
tPGH
Hold Time, ODD/EVEN and PGB after ClKBi(l)
0
tRSTH
Hold Time, RST lOW after ClKA i or ClKBi(2)
5
tFSH
Hold Time, FSO and FS1 after RST HIGH
4
tSKEW1(3)
Skew Time, between ClKA i and ClKBi
for EF and FF
8
8
10
-
ns
0
-
2
Hold Time, SWO and SW1 after ClKBi
-
2
tSWH
tSKEW2(3)
Skew Time, between ClKAi and ClKBi
for AE and AF
9
-
16
-
20
-
ns
0
0
6
4
0
0
7
4
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and ClKS
cycle.
5.11
7
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL =30pF (SEE FIGURE 4 THROUGH 18)
Symbol
IDT723613L 15 IDT723613L20 IDT723613L30
Min.
Max.
Min.
Max.
Min.
Max.
Parameter
tA
Access Time, CLKA i to AO-A35 and CLKBi
to BO-B35
2
10
2
12
2
Unit
15
ns
ns
tWFF
Propagation Delay Time, CLKAito FF
2
10
2
12
2
15
tREF
Propagation Delay Time, CLKBi to EF
2
10
2
12
2
15
ns
tPAE
Propagation Delay Time, CLKBi to AE
2
10
2
12
2
15
ns
tPAF
Propagation Delay Time, CLKAito AF
2
10
2
12
2
15
ns
tPMF
Propagation Delay Time, CLKA i to MBF1 LOW
or MBF2 HIGH and CLKBi to MBF2 LOW or
MBF1 HIGH
1
9
1
12
1
15
ns
tPMR
Propagation Delay Time, CLKA i to BO-B35(1)
-and CLKSi to AO-A35(2)
3
11
3
12
3
15
ns
tpPE(3)
Propagation delay time, CLKBi to PEFB
2
11
2
12
2
13
ns
tMOV
Propagation Delay Time, Sll1, SilO to
BO-B35 valid
1
11
1
11.5
1
12
ns
tPOPE
Propagation Delay Time, AO-A35 valid to PEFA
valid; BO-B35 valid to PEFB valid
3
10
3
11
3
13
ns
tpOPE
Propagation Delay Time, ODD/EVEN to PEFA
and PEFB
3
11
3
12
3
14
ns
tPOPB(4)
Propagation Delay Time, ODD/EVEN to parity
bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
2
12
2
13
2
15
ns
tPEPE
Propagation Delay Time, CSA, ENA, W/RA,
MBA, or PGA to PEFA; CSB, ENB, WiRB, Sll1,
SilO, or PGB to PEFB
1
11
1
12
1
14
ns
tPEPB(4)
Propagation Delay Time, CSA, ENA, W/RA,
MBA, or PGA to parity bits (A8, A 17, A26, A35);
CSB, ENB, WiRB, Sll1, SilO, or PGB to parity
bits (B8, B17, B26, B35)
3
12
3
13
3
14
ns
tRSF
Propagation Delay Time, RST to AE, EF
LOW and AF, MBF1, MBF2 HIGH
1
15
1
20
1
25
ns
tEN
Enable Time, CSA and W/RA LOW to AO-A35
active and CSB LOW and W/RB HIGH to
BO-B35 active
2
10
2
12
2
14
ns
tOIS
Disable Time, CSA or W/RA HIGH to AO-A35
at high impedance and CSB HIGH or W/RB
LOW to BO-B35 at high impedance
1
8
1
9
1
11
ns
NOTES:
1. Writing data to the
2. Writing data to the
3. Only applies when
4. Only applies when
mail1 register when the BO-835 outputs are active and SIZ1 and SIZO are HIGH.
mail2 register when the AO-A35 outputs are active.
a new port-8 bus size is implemented by the rising ClK8 edge.
reading data from a mail register.
5.11
8
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
FUNCTIONAL DESCRIPTION
COMMERCIAL TEMPERATURE RANGES
FIFO WRITE/READ OPERATION
RESET (RST)
The IDT723613 is reset by taking the reset (RSl) input
lOW for at least four port A clock (ClKA) and four port B clock
(ClKB) lOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of the FIFO and forces the fullflag (FF) lOW, the empty flag (EF) lOW, the almost-empty
flag (AE) lOW, and the almost-full flag (AF) HIGH. A reset also
forces the mailbox flags (MBF1, MBF2) HIGH. After a reset,
FF is set HIGH after two lOW-to-HIGH transitions of ClKA.
The device must be reset after power up before data is written
to its memory.
_
A lOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty offset register (X) with the value
selected by the flag select (FSO, FS 1) inputs. The values that
can be loaded into the register are shown in Table 1.
TABLE 1: FLAG PROGRAMMING
FS1
FSO
RST
ALMOST-FUll AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H
H
i
16
H
l
i
12
l
H
i
8
l
l
i
4
The state of the port A data (AO-A35) outputs is controlled
by the port-A chip select (CSA) and the port-A write/read
select (WiRA). The AO-A35 outputs are in the high-impedance
state when either eSA or WiRA is HIGH. The AO-A35 outputs
are active when both CSA and WiRA are LOW.
Data is loaded into the FIFO from the AO-A35 inputs on
a lOW-to-HIGH transition of ClKA when CSA is lOW, WiRA
is HIGH, ENA is HIGH, MBA is lOW, and FFA is HIGH (see
Table 2).
The state of the port B data (BO-B35) outputs is controlled by the port B chip select (CSB) and the port B write/read
select (WiRB). The BO-B35 o~tputs are in the high-impedance
state when either CSB or W/RB is HIGH. The BO-B35 outputs
are active when both CSB and WiRB are lOW. Data is read
from the FIFO to the BO-B35 outputs by a lOW-to-HIGH
transition of ClKB when eSB is lOW, W/RB is lOW, ENB is
HIGH, EFB is HIGH, and either SIZO or SIZ1 is lOW (see
Table 3).
The setup and hold-time constraints to the port clocks for
the port chip selects (CSA, CSB) and write/read sel~cts (W/
RA, W/RB) are only for enabling write and read operations and
are not related to high-impedance control of the data outputs.
If a port enable is lOW during a clock cycle, the po~'s chip
select and write/read select can change states dunng the
setup and hold time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO flag is synchronized to its port clock through
two flip-flop stages. This is done to improve the flags'
reliability by reducing the probability of metastable events on
their outputs when ClKA and ClKB operate asynchronously
to one another. FF and AF are synchronized to ClKA. EF and
AE are synchronized to ClKB. Table 4 shows the relationship
of each port flag to the level of FIFO fill.
TABLE 2: PORT A ENABLE FUNCTION TABLE
CSA
wif5.A
ENA
MBA
CLKA
AO-A350UPTUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
l
H
l
X
X
In high-impedance state
None
l
H
H
l
i
In high-impedance state
FIFO write
l
H
H
H
i
In high impedence state
Mail1 write
l
l
l
l
X
Active, mail2 register
None
l
l
H
l
i
Active, mail2 register
None
l
l
l
H
X
Active, mail2 register
None
l
l
H
H
i
Active, mail2 register
Mail2 read (set MBF2 HIGH)
5.11
9
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
TABLE 3: PORT B ENABLE FUNCTION TABLE
CSB
W/RB
ENB
SIZ1, SIZO
CLKB
H
X
X
X
X
In high-impedance state
None
l
H
l
X
X
In high-impedance state
None
l
H
H
One, both lOW
i
In high-impedance state
None
l
H
H
Both HIGH
i
In high-impedance state
Mail2 write
l
l
l
One, both lOW
X
Active, FIFO output regisger
None
l
l
H
One, both lOW
i
Active, FIFO output register
FIFO read
l
l
l
Both HIGH
X
Active, mail1 register
None
l
l
H
Both HIGH
i
Active mail1 register
Mail1 read (set MBF1 HIGH)
BO-B35 OUTPUTS
EMPTY FLAG (EF)
The FIFO empty flag is synchronized to the port clock
that reads data from its array (ClKB). When the empty flag
is HIGH, new data can be read to the FIFO output register.
When the empty flag is lOW, the FIFO is empty and attempted FIFO reads are ignored. When reading the FIFO with
a byte or word size on port B, EF is set lOW when the fourth
byte or second word of the last long word is read.
The FI FO read pointer is incremented each time a new
word is clocked to its output register. The state machine that
controls the empty flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is empty, empty+ 1, or empty+2. A word written to the
FIFO can be read to the FIFO output register in a minimum of
three port B clock (ClKB) cycles. Therefore, an empty flag is
lOW if a word in memory is the next data to be sent to the FI FO
output register and two ClKB cycles have not elapsed since
TABLE 4: FIFO FLAG OPERATION
NUMBER OF 36-BIT
WORDS IN THE FIFO
(1)
SYNCHRONIZED
TO CLKB
EF
AE
SYNCHRONIZED
TO CLKA
AF
FF
0
l
l
H
H
1 to X
H
l
H
H
(X+ 1) to [64 - (X + 1)]
H
H
H
H
(64 - X) to 63
H
H
l
H
64
H
H
l
l
NOTE:
1. x is 1he value in the almost-empty flag and almost-full flag offset register
5.11
PORT FUNCTION
the time the word was written. The empty flag of the FIFO is
set HIGH by the second lOW-to-HIGH transition of ClKB,
and the new data word can be read to the FI FO output register
in the following cycle.
A lOW-to-HIGH transition on ClKB begins the first
synchronization cycle of a write if the clock transition occurs at
time tSKEW1 or greater after the write. Otherwise, the subsequent ClKB cycle can be the first synchronization cycle (see
Figure 9).
FULL FLAG (FF)
The FIFO full flag is synchronized to the port clock that
writes data to its array (ClKA). When the full flag is HIGH, a
SRAM location is free to receive new data. No memory
locations are free when the full flag is lOW and attempted
writes to the FIFO are ignored.
Each time a word is written to the FIFO, its write-pointer
is incremented. The state machine that controls the full flag
monitors. a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from the FIFO, its previous
memory location is ready to be written in a minimum of three
ClKA cycles. Therefore, a full flag is lOW if less than two
ClKA cycles have elapsed since the next memory write
location has been read. The second lOW-to-HIGH transition
on the full flag synchronizing clock after the read sets the full
flag HIGH and data can be written in the following clock cycle.
A lOW-to-HIGH transition on ClKA begins the first
synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see
Figure 10).
ALMOST-EMPTY FLAG (AE)
The FIFO almost empty-flag is synchronized to the port
clock that reads data from its array (ClKB). The state machine
that controls the almost-empty flag monitors a write-pointer
and read-pointer comparator that indicates when the FIFO
SRAM status is almost empty, almost empty+ 1, or almost
10
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x36
empty+2. The almost-empty state is defined by the value of
the almost-full and almost-empty offset register (X). This
register is loaded with one of four preset values during a
device reset (see reset above). The almost -empty flag is lOW
when the FIFO contains X or less long words in memory and
is HIGH when the FIFO contains (X+ 1) or more long words.
Two lOW-to-HIGH transitions on the port B clock (ClKB)
are required after a FIFO write for the almost-empty flag to
reflect the new level of fill. Therefore, the almost-empty flag
of a FIFO containing (X+ 1) or more long words remains lOW
if two ClKB cycles have not elapsed since the write that filled
the memory to the (X+ 1) level. The almost-empty flag is set
HIGH by the second ClKB lOW-to-HIGH transition after the
FIFO write that fills memory to the (X+1) level. A lOW-toHIGH transition of ClKB begins the first synchronization cycle
if it occurs at time tSKEW2 or greater after the write that fills the
FIFO to (X+1) long words. Otherwise, the subsequent ClKB
cycle can be the first synchronization cycle (see Figure 11).
ALMOST FUll FLAG (AF)
The FIFO almost-full flag is synchronized to the port
clock that writes data to its array (ClKA). The state machine
that controls an almost-full flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almostempty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset above).
The almost-full flag is lOW when the FIFO contains (64-X) or
more long words in memory and is HIGH when the FIFO
contains [64-(X+ 1)] or less long words.
Two lOW-to-HIGH transitions on the portA clock (ClKA)
are required after a FIFO read forthe almost-full flag to reflect
the new level of fill. Therefore, the almost-full flag of a FIFO
containing [64-(X+ 1)] or less words remains lOW if two ClKA
cycles have not elapsed since the read that reduced the
number of long words in memory to [64-(X+ 1)]. The almostfull flag is set HIGH by the second ClKA lOW-to-HIGH
transition after the FIFO read that reduces the number of long
words in memory to [64-(X+ 1)]. A lOW-to-HIGH transition on
ClKA begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
long words in memory to [64-(X+1)]. Otherwise, the subsequent ClKA cycle can be the first synchronization cycle (see
Figure 12).
MAilBOX REGISTERS
Two 36-bit bypass registers (mail1, mail2) are on the
10T723613 to pass command and control information between port A and port B without putting it in queue. A lOW-toHIGH transition on ClKA writes AO-A35 data to the mail1
register when a port A write is selected by CSA, W/RA, and
ENA (with MBA HIGH). A lOW-to-HIGH transition on ClKB
writes BO-B35 data to the mail2 register when a port B write is
selected by CSB, W/RB, and ENB (and both SIZO and SIZ1
are HIGH). Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) lOW. Attempted writes to a mail
register are ignored while its mail flag is lOW.
When the port B data (BO-B35) outputs are active, the
COMMERCIAL TEMPERATURE RANGES
data on the bus comes from the FIFO output register when
either one or both SIZ1 and SIZO are lOW and from the mail1
register when both SIZ1 and SIZO are HIGH. The mail1
register flag (MBF1) is set HIGH by a rising ClKB edge when
a port B read is selected by CSB, W/RB, and ENB, (and both
SIZ1 and SIZO HIGH). The mail2 register flag (MBF2) is set
HIGH by a rising ClKA edge when a port A read is selected
by CSA, W/RA, and ENA (with MBA HIGH). The data in a mail
register remains intact after it is read and changes only when
new data is written to the register.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word,
18-bit word, or 9-bit byte format for data read from the FIFO.
Word- and byte-size bus selections can utilize the most
significant bytes of the bus (big endian) or least significant
bytes of the bus (little endian). Port B bus-size can be
changed dynamically and synchronous to ClKB to communicate with peripherals of various bus widths.
The levels applied to the port B bus-size select (SIZO,
SIZ1) inputs and the big-endian select (BE) input are stored
on each ClKB lOW-to-HIGH transition. The stored port B
bus-size selection is implemented by the next rising edge on
ClKB according to Figure 1.
Only 36-bit long-word data is written to or read from the
FIFO memory on the IOT723613. Bus-matching operations
are done after data is read from the FIFO RAM. Port B bus
sizing does not apply to mail register operations.
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long-word
increments. If a long-word bus-size is implemented, the entire
long word immediately shifts to the FIFO output register upon
a read. If byte or word size is implemented on port B, only the
first one or two bytes appear on the selected portion of the FI FO
output register, with the rest of the long word stored in auxiliary
registers. In this case, subsequent FIFO reads with the same
bus-size implementation output the rest of the long word to the
FIFO output register in the order shown by Figure 1.
Each FIFO read with a new bus-size implementation
automatically unloads data from the FIFO RAM to its output
register and auxiliary registers. Therefore, implementing a
new port B bus-size and performing a FIFO read before all
bytes orwords stored in the auxiliary registers have been read
results in a loss of the unread data in these registers.
When reading data from FI FO in byte or word format, the
unused BO-B35 outputs remain inactive but static, with the
unused FIFO output register bits holding the last data value to
decrease power consumption.
5.11
BYTE SWAPPING
The byte-order arrangement of data read from the FIFO
can be changed synchronous to the rising edge of ClKB.
Byte-order swapping is not available for mail register data.
Four modes of byte-order swapping (including no swap) can
be done with any data port size selection. The order of the
bytes are rearranged within the long word, but the bit order
within the bytes remaines constant.
11
ID1723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x36
A:G
A35 A27
BYTE ORDER ON PORT
COMMERCIAL TEMPERATURE RANGES
A26 A18
A17 A9
~
G
~
B26 B18
B17
B8
~
G
~
B35 B27
B26 B18
B17 B9
B8
G
~
[f{ij
~
B26 B18
B17
B8
G
[f{ij
B35 B27
G
B9
A8
AO
Wnte to FIFO
BO
Read from FIFO
(a) LONG WORD SIZE
B35 B27
~
B26 B18
~
[f{ij
B35 B27
B26 B18
~
~
(c) WORD SIZE -
BO
~ 2nd: Read from FIFO
G G
G [3
B17
B17
B9
B9
B8
B8
BO
II
2nd: Read from FIFO
LITTLE ENDIAN
B17
B9
B8
BO
B26 B18
G
~
[f{ij
[f{ij
~
817
B8
B35 B27
B26 B18
817
G
~
~
1st: Read from FIFO
BO
B35 B27
B35 B27
1st Read from FIFO
BIG EN DIAN
(b) WORD SIZE -
B35 B27
B9
BO
B26 B18
835 B27
B26 B18
~
~
(d) BYTE SIZE -
B9
~
B9
~
817
B9
~
BIG ENDIAN
BO
~
B8
1st: Read from FIFO
2nd: Read from FIFO
80
~ 3rd: Read from FIFO
88
BO
~ 4th: Read from FIFO
3145 fig 01
Figure 1. Dynamic Bus Sizing
5.11
12
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 X 36
835 827
826 818
~
~
817 89
~
817
~
A26 A18
A17 A9
~
~
~
835 827
826 818
~
~
817
88
80
~ 2nd: Read from FIFO
A8
AO
~ 3rd: Read from FIFO
o
89
88
~
(d) BYTE SIZE -
80
~ 1st: Read from FIFO
89
~
A35 A27
88
~
826 818
835 827
COMMERCIAL TEMPERATURE RANGES
LITTLE EN DIAN
80
4th: Read from FIFO
3145 drwfig 01a
Figure 1. Dynamic Bus Sizing (continued)
8yte arrangement is chosen by the port 8 swap select
(SWO, SW1) inputs on a elK8 rising edge that reads a new
long word from the FIFO. The byte order chosen on the first
byte or first word of a new long word read from the FIFO is
maintained until the entire long word is transferred, regardless of the SWO and SW1 states during subsequent reads.
Figure 3 is an example of the byte-order swapping available
for long word reads. Performing a byte swap and bus-size
simulationeouslyfor a FIFO read first rearranges the bytes as
shown in Figure 3, then outputs the bytes as shown in Figure
1.
PORT-B MAIL REGISTER ACCESS
In addition to selecting port B bus sizes for FIFO
reads, the port B bus size select (SIZO, SIZ1) inputs also
access the mail registers. When both SIZO and SIZ1 are
HIGH, the mail1 register is accessed for a port B long-word
read and the mail2 register is accessed for a port 8 long-word
write. The mail register is accessed immediately and any
bus-sizing operation that can be underway is unaffected by
the mail register access. After the mail register access is
complete, the previous FIFO access can resume in the next
elK8
rrD
SIZO
SIZ1
8E
G1 MUX
t.:;
'-L...-1
f-
ro--
D
Q
I--
1
SIZO_Q
SIZ1_Q
BE_Q
3145 drw fig 02
Figure 2. Logic Diagram for SIZO, SIZ1, and BE Register
5.11
13
101723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x36
A35 A27
I
SW1
L
A26 A18
~
Iswo
I
L
835 827
ctJ
826 818
COMMERCIAL TEMPERATURE RANGES
A17 A9
A8
AO
~
[3
dJ cb
88
80
A17 A9
A8
AO
89
88
80
817
89
(a) NO SWAP
I
SW1
L
A35 A27
A26 A18
835 827
826 818
Iswo
I
H
817
II
(b) BYTE SWAP
I
SW1
H
A35 A27
A26 A18
A17 A9
A8
AO
835 827
826 818
817
88
80
A8
AO
IswoL I
89
(c) WORD SWAP
A35 A27
I
SW1
H
A26 A18
A17 A9
Iswo
I
H
835 827
826 818
817
89
88
(d) BYTE-WORD SWAP
80
3145 drw fig 03
Figure 3. Byte Swapping for FIFO Reads (Long-Word Size Example)
5.11
14
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 X 36
ClK8 cycle. The logic diagram in Figure 2 shows the
previous bus-size selection is preserved when the mail
registers are accessed from port 8. A port 8 bus-size is
implemented on each rising ClKB edge according to the
states of SI20_0, SI21_0, and 8E_O.
PARITY CHECKING
The port A data inputs (AO-A35) and port 8 data inputs (BOB35) each have four parity trees to check the parity of
incoming (or outgoing) data. A parity failure on one or more
bytes of the port A data bus is reported by a low level on the
port A parity error flag (PEFA). A parity failure on one or more
bytes of the port 8 data inputs that are valid for the bus-size
implementation is reported by a low level on the port B parity
error flag (PEF8). Odd or even parity checking can be selected, and the parity error flags can be ignored if this feature
is not desired.
Parity status is checked on each input bus according to the
level of the odd/even parity (ODD/EVEN) select input. A parity
error on one or more valid bytes of a port is reported by a lOW
level on the corresponding port-parity-errorflag (PEFA, PEF8)
output. Port A bytes are arranged as AO-A8, A9-A 17, A 18A26, and A27-A35, and port 8 bytes are arranged as 80-B8,
89-817, B18-B26, and 827-B35, and its valid bytes are those
used in a port 8 bus size implementation. When odd/even
parity is selected, a port-parity-errorflag (PEFA, PEF8) is lOW
if any byte on the port has an odd/even number of lOW levels
applied to its bits.
The four parity trees used to check the AO-A35 inputs are
shared by the mail2 register when parity generation is selected for port-A reads (PGA = HIGH). When a port A read
from the mail2 register with parity generation is selected with
CSA lOW, ENA HIGH, WiRA lOW, MBA HIGH, and PGA
HIGH, the port A parity error flag (PEFA) is held HIGH
regardless of the levels applied to the AO-A35 inputs. likewise, the parity trees used to check the 80-835 inputs are
shared by the mail1 register when parity generation is selected for port Breads (PG8 =HIGH). When a port B read from
the mail1 register with parity generation is selected with CSB
lOW, ENB HIGH, WiR8 lOW, both SI20 and SI21 HIGH, and
COMMERCIAL TEMPERATURE RANGES
PGB HIGH, the port 8 parity error flag (PEF8) is held HIGH
regardless of the levels applied to the BO-835 inputs.
PARITY GENERATION
A HIGH level on the port A parity generate select (PGA) or
port 8 generate select (PGB) enables the IDT723613 to
generate parity bits for port reads from a FIFO or mailbox
register. Port A bytes are arranged as AO-A8, A9-A 17, A 18A26, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port 8 bytes are arranged as BO-B8, 89817, 818-B26, and 827-835, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all nine inputs of a byte
regardless of the state of the parity generate select (PGA,
PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used
to generate a parity bit according to the level on the 000/
EVEN select. The generated parity bits are substituted for the
levels originally written to the most significant bits of each byte
as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port A parity generate select (PGA)
and odd/even parity select (ODD/EVEN) have setup and hold
time constraints to the port A clock (ClKA) and the port B
parity generate select (PGB) and ODD/EVEN select have
setup and hold time constraints to the port 8 clock (ClK8).
These timing constraints only apply for a rising clock edge
used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port B bus (BO-835) to check parity and the circuit
used to generate parity for the mail2 data is shared by the port
A bus (AO-A35) to check parity. The shared parity trees of a port
are used to generate parity bits for the data in a mail register
when the port chip select (CSA, CS8) is lOW, enable (ENA,
EN8) is HIGH, and writelread select (WiRA, WiRB) input is
lOW, the mail register is selected (M8A HIGH for port A; both
SI20 and SI21 are HIGH for port 8), and port parity generate
select (PGA, PG8) is HIGH. Generating parity for mail register
data does not change the contents of the register.
5.11
15
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x 36
COMMERCIAL TEMPERATURE RANGES
ClKA
ClKB
FS1,FSO
01
FF~~~~~~~~~~~~~~
________________________________- J I
EF~~~~~~~~~~~~~~~
_________________________________________
AE~~~~~~~~~~~~~~~~
_______________________________________
3145 drw04
Figure 4. Device Reset Loading the X Register with the Value of Eight
1 + - - - - - tCLK-----I~~1
CLKA
wiRA
MBA
ENA
AO - A3S
ODD/
EVEN
NOTE:
1. Written to the FIFO.
Figure 5. FIFO Write Cycle Timing
5.11
16
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
-.~
,L-
elKB
COMMERCIAL TEMPERATURE RANGES
-~
i£
HIGH
",,"' ."""
W/RB
ENB / / / / / / / / / /
...
/"LL///
tENS
/ /7Ftsws ~
SW1,
SWO
xx)
XXXxx xxx xx
tszs
tSZH
tsz
tSZH
NOT (11
BE ~
SIZ1,
SIZO
xxxx
~
X)~_(O,O)
dDGd]'
EVEN
tENS
tENH
-
--
'\.'\.'\.'\.'\.'\.'\.\,b--
K-XXXX/\'Y
-¥
tENH
//////
No Operation
tSWH
I(xxxxxx
~
XXxxxxXXXXx
x:xx~ ~xxxxxxxx
~gD<
1)
I
xxXXX)
XXXXXXXXXXXX)( XXXXXX
Xx xxxXXX
NOT(11)l')
tPGS~ ~ltPGH
xxxxxxxxxx
tEN
xxX
..
.. L
BO-B35
NOTES:
1. SIZO HIGH and SIZ1
2. Data read from FIF01.
=
-
=HIGH selects the mail1
XXXXXX )(
r---
XXXXXXX XXXX >CXXXXX
~tA
~ tA..::=!1
Previous Data )I(
W1\LI
tDIS~
-I
)I(
W2(2)
3146 drw 06
register for output on 80-835.
DATA SWAP TA8LE FOR FIFO LONG-WORD READS
SWAP MODE
FIFO DATA WRITE
FIFO DATA READ
817-89
88-80
B
C
D
D
C
B
A
L
C
D
A
B
H
B
A
D
C
835-827 826-818
A35-A27
A26-A18
A17-A9
A8-AO
SW1
SWO
A
B
C
D
L
L
A
A
B
C
D
L
H
A
B
C
D
H
A
B
C
D
H
Figure 6. FIFO long-Word Read Cycle Timing
5.11
17
IDT123613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x36
. .J£.
~
elKB
COMMERCIAL TEMPERATURE RANGES
-.~
HIGH
",,'
wiRB
.,,L
..301<-
~",,'\
//////
tENS
tENH
'--3145 drw 07
NOTES;
1. SIZO = HIGH and SIZ1 = HIGH selects the mail1 register for output on 80-835.
2. Unused word 80-817 or 818-835 holds last FIF01 output register data for word-size reads.
DATA SWAP TABLE FOR FIFO WORD READS
FIFO DATA WRITE
A35-A27
A26-A18
SWAP MODE
A17-A9
A8-AO
SW1
FIFO DATA READ
READ
NO.
sWO
81G ENDIAN
835-827 826-818
A
B
C
D
LITTLE ENDIAN
C
A
88-80
D
B
817-89
A
B
C
D
L
L
1
2
A
B
C
D
L
H
1
2
D
B
C
A
B
D
A
C
B
C
D
H
L
1
2
C
A
D
B
A
C
B
A
B
C
D
H
H
1
2
B
D
A
C
0
A
C
A
B
0
Figure 7. FIFO Word Read-Cycle Timing
5.11
18
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x36
COMMERCIAL TEMPERATURE RANGES
ClKB
EF
CSB
W/RB ~~~~~~~__~________~__________~________+-________~~-'~~~
ENB~~~~~~~
SW1, ~~~rn~~7I.
swo
'-~~'~~~~~~~~~~~~~~~~~~~~~~~~~~
BE
S121,
SI20
BO-B8 -------~_-+-___, I_~..;;...;.;.;~---'r 1'-_'-+'=-=;"""'''' I'_~.;;;.;;;...;;.....-'
B27-B35 --------\.!::r!~~~~~L~~~__i
' -_____
'-....:..:.:=-=---'
'---:..:=:....:..._>-----
NOTES:
1. SIZO HIGH and SIZ1 HIGH selects the mail1 register for output on 80-835.
2.
Unused bytes hold last FIFO output register data for byte-size reads.
=
=
3145 drwOB
DATA SWAP TABLE FOR FIFO BYTE READS
FIFO DATA READ
SWAP MODE
FIFO DATA WRITE
A35-A27
A
A
A
A
A26-A1S
B
B
B
B
A17-A9
C
C
C
C
AS-AO
SW1
D
L
0
L
D
H
D
H
READ
NO.
SWO
L
H
L
H
81G
ENDIAN
LITTLE
ENDIAN
835-827
8S-80
1
2
3
A
D
B
C
C
B
4
D
A
1
D
A
2
3
C
B
B
C
4
A
D
1
2
3
C
B
D
A
A
D
4
B
C
1
2
3
B
C
A
D
D
A
4
C
B
Figure 8. FIFO Byte Read-Cycle Timing
5.11
19
ID1723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x36
COMMERCIAL TEMPERATURE RANGES
ClKA
CSA
WRA
MBA
ENA
FF
AO - A35
ClKB
EF
FIFO Empty
CSB
lOW
wiRB
lOW
II
SIZ1,
SIZO
ENB
I
3145 drw 09
NOTES:
1. tSKEW1 is the minimum time between a rising ClKA edge and a rising ClKS edge for EFta transition HIGH in the next ClKS cycle. If the time between
the rising ClKA edge and rising ClKS edge is less than tSKEW1, then the transition of EF HIGH may occur one ClKS cycle later than shown.
2. Port S size of long word is selected for the FIFO read by SIZ1 lOW, SIZO lOW. If port-S size is word or byte, EF is set lOW by the last word or byte
read from the FIFO, respectively.
=
=
Figure 9. EF Flag Timing and First Data Read when the FIFO is Empty
5.11
20
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x 36
ClKB
COMMERCIAL TEMPERATURE RANGES
--_/
CSB
lOW
WIRB
lOW
81Z1,
SIZO
lOW
,'----
r;-tENH
tENS -;-:-..,
ENB
EF
BO-B35
ClKA
FF ________________
CSA ___
~~
~~~
____________________________"
__________________________________________________
~-----------------
WRA
MBA~~~~~~~~~~~~~~~~~~~~~~~~~~~1,~~~~~~~
To FIFO
3145 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising ClKS edge and a rising ClKA edge for EF to transition HIGH in the next ClKA cycle. If the time between
the rising ClKS edge and rising ClKA edge is less than tSKEW1, then the transition of EF HIGH may occur one ClKA cycle later than shown.
2. Port S size of long word is selected forthe FIFO read by SIZ1 lOW, SIZO lOW. If port S size is word or byte, tSKEW1 is referenced from the rising
ClKS edge that reads the first word or byte of the long word, respectively.
=
=
Figure 10. FF Flag Timing and First Available Write when the FIFO is Full
5.11
21
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
~s ~;.:
ClKA/
ENA
COMMERCIAL TEMPERATURE RANGES
"---------.,../
~;5f~~
____
,~S;~~~
___________________________________________
tSKEW2(1)~
ClKB
X Long Words in FIFO
ENB ________________________________________________________
~~~~
NOTES:
1. tSKEW2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AE to transition HIGH in the next ClKB cycle. If the time between
the rising ClKA edge and rising ClKB edge is less than tSKEW2, then AE may transition HIGH one ClKB cycle later than shown.
2. FIFO write (CSA = lOW, W/RA = HIGH, MBA =lOW), FIFO read (CSS = lOW, W/RB =lOW, MBB = lOW).
3. Port B size of long word is selected for the FIFO read by SIZ1 = lOW, SIZO = lOW. If port B size is word or byte, tSKEW2 is referenced to the first word
or byte of the long word, respectively.
Figure 11. Timing for AE when the FIFO is Almost Empty
II
ClKA/
ENA
~
tSKEW2(1)
~s~ ;':N" ,
=r=:
"
t2
' . . . __r---
~~_===~,~S;~~~______~----------------~----------------
AF [64-(X+ 1)] Long Words in FIFO
tPAF ~
tPAF
(64-X) Long Words in FIFO
ClKB _____
ENB
3145 drw 12
NOTES:
1. tSKEW2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AF to transition HIGH in the next ClKA cycle. If the time between
the rising ClKA edge and rising ClKS edge is less than tSKEW2, then AF may transition HIGH one ClKB cycle later than shown.
2. FIFO write (CSA = lOW, W/RA = HIGH, MBA =lOW), FIFO read (CSS = lOW, W/RB =lOW, MBB =lOW).
3. Port-B size of long word is selected for FIFO read by SIZ1 = lOW, SIZO = lOW. If port B size is word or byte, tSKEW2 is referenced from the first word or
byte read of the long word, respectively.
Figure 12. Timing for AFwhen the FIFO is Almost Full
5.11
22
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x36
COMMERCIAL TEMPERATURE RANGES
ClKA
wiRA
MBA
ENA
AO - A35
ClKB
WIRB
81Z1,81Z0
ENB
BO - B35
FIFO Output Register
NOTE:
1. Port-B parity generation off (PGB
3145 drw 13
=LOW).
Figure 13. Timing for Mail1 Register and MBF1 Flag
5.11
23
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x 36
COMMERCIAL TEMPERATURE RANGES
ClKB
W/RB
81Z1,
81Z0
ENB
BO - B35
ClKA
II
W/RA
MBA
ENA
AO - A35
3145 drw 14
NOTE:
1. Port-A parity generation off (PGA
=LOW).
Figure 14. Timing for Mail2 Register and MBF2 Flag
5.11
24
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 X 36
COMMERCIAL TEMPERATURE RANGES
0001
EVEN-----'-.
I'-----------------~I
WiRA
PEFA _ _ _ _ _ _
~~
_ _ _ _ _ _" '_ _ _ _ _ _
~~
_ _ _ __ J ' ' __ _ _ _ _ _
~~
_ _ _ _J '
NOTE:
1. CSA = LOW and ENA = HIGH.
3145 drw 15
Figure 15. ODD/EVEN, WiRA, MBA, and PGA to PEFA Timing
0001 _ _ _ _ _,1
EVEN
W/RB
51Z1 ,"""7'~7"""'7'"""7"'~7h'"""7"'~'7'_::I,...._r~7"""'7'"""7"'_,./_7"""'7"""7'"~7"""'7"""7'"""7"""':r_7_h_------~~~~~~~~
5 IZO ..........:......L~""'_..........~_"_""'_L_J.~_"_""'_
..........:......L_f_""'-C--<~~""'-L-I.;,....,L._'l
PEffi _ _ _~~_ _~,,~_ _~~_ _J I '_ _ _ _~~_
__"
Valid
3145 drw 16
NOTE:
1. CSS
= LOW and ENS =HIGH.
Figure 16. ODD/EVEN, W/RB, SIZ1, SIZO, and PGB to PEFB Timing
5.11
25
IDTI23613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x36
0001
COMMERCIAL TEMPERATURE RANGES
.3~
EVEN
CSA LOW
WiRA
~Ic-
MBA / / /V////'?
il'
PGA
I- tEN
AB,A17
Mail2 Data
A26, A35
NOTE:
1. ENA
~
tPEP
=HIGH.
I
*
-tPOPB-!
X
Generated Parity
~tPEPB
Generated Parik
_I
I
X
Mail2 Data
3145drw 17
Figure 17. Parity Generation Timing when Reading from the Mail2 Register
0oo/------------------------------~1
EVEN
1'---------------------------------------
CSB LOW
WiRB
SIZ1,~~~~~~~-----------------+---------------------------------------SIZO
~~-!C-.L....c....I.:.......L-'I
BB,B17,-----------~~~~~~~~~*=~~~~~~c:~<=~~~~~~::~<=:JM~a~iITI1Jo~aWta~
B26,B35
NOTE:
1. ENS
3145 drw 18
=HIGH.
Figure 18. Parity Generation Timing when Reading from the Mail1 Register
5.11
26
II
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x 36
COMMERCIAL TEMPERATURE RANGES
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
350
f data
=1/2
fs
=25°C
C L =0 pF
TA
300
ii
c..
::J
(/)
150
I
c-
O'
~
100
50
0
0
10
20
30
40
50
f s - Clock Frequency - MHz
60
80
70
3145 drw 19
FIGURE 19
CALCULATING POWER DISSIPATION
The ICC, current for the graph in Figure 19 was taken while simultaneously reading and writing the FIFO on the
IDT723613 with ClKA and ClKS set to fs' All date inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-copacitance load.
Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from Figure 19, the maximum power dissipation (PT) of the IDT723613 may be calculated by:
PT
=Vcc x ICC(f) + I[CL x (VOH - voL)2 X fo)
where:
CL
fo
output capacitive load
switching frequency of an output
VOH
output high-level voltage
VOL
output high-level voltage
When no reads or writes are occurring on the IDT723613, the power dissipated by a single clock (ClKA or ClKS)
input running at frequency fs is calculated by:
PT
=VCC x fs x O.29ma/MHz
5.11
27
101723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64x36
COMMERCIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kn
From Output _ _. _ - - - -......
Under Test
30
pF(1)
680n
PROPAGATION DELAY
LOAD CIRCUIT
3V
Timing
Input
3V
High-Level
Input
GND
1.5 V
3V
Data,
Enable
Input
II
GND
tw
3V
Low-Level
Input
GND
1.5 V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Output
Enable
GND
- ""3V
Low-Level
Output
Input
1.5 V
--+---"
VOL
VOH
High-Level
Output
1.5 V
ktP~
~.5V
-~tP1
In-Phase
Output _ _ _---J
3V
"S.k~v-
1.5 V
GND
1.5 V
_ =OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3145 drw 20
NOTE:
1.
Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms
5.11
28
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxxxx
x
xx
x
Device Type
Power
Speed
Package
x
Process!
Temperature
Range
Y
BLANK Commercial (D'C to +7D'C)
'--_ _ _ _ _ _~ PF
PQF
15
0
23 0
'--------------------j L
Thin Quad Flat Pack
Plastic Quad Flat Pack
}
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Low Power
' - - - - - - - - - - - - - - - - - - - - - 1 723613 64 x 36 Synchronous FIFO
3145 drw 21
5.11
29
G®
IDT723631
IDT723641
IDT723651
CMOS SyncFIFO™
512 X 36,1024 x 36,
2048 X 36
Integrated Device Technology, Inc.
Advance mformatlon for the IDT723631
Final information for the IDT723641
Advance information for the IDT723651
• Output-Ready (OR) and Almost-Empty (AE) flags synchronized by ClKB
• low-power 0.8-micron advanced CMOS technology
• Supports clock frequencies up to 67 Mhz
• Fast access times of 11 ns
• Available in 132-pin plastic quad flat package (POF) or
space-saving 120-pin thin quad flat package (TOFP)
FEATURES:
• Free-running ClKA and ClKB can be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• Clocked FIFO buffering data from Port A to Port B
• Storage capacity: IDT723631 - 512 x 36
IDT723641 - 1024 x 36
IDT723651 - 2048 x 36
• Synchronous read retransmit capability
• Mailbox register in each direction
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• Input-Ready (IR) and Almost-Full (AF) flags synchronized
by ClKA
DESCRIPTION:
The IDT723631/723641n23651 is a monolithic highspeed, low-power, CMOS clocked FIFO memory. It supports
clock frequencies up to 67 MHz and has read access times as
fast as 12ns. The 512/1024/2048 x 36 dual-port SRAM FIFO
buffers data from port A to Port B. The FIFO memory has
retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full
conditions and two programmable flags (almost full and al-
II
FUNCTIONAL BLOCK DIAGRAM
WiRA ENA MBA ClKA
CSA
•
-I
Port-A
Control
logic 1 - -
.--
I-
I
Mail 1
Register
I
r---
"5*
0..'COl
-w
.......
.. MBF1
a:
--
512 x 36
1024 x 36
2048 x 36
SRAM
~ii~
::JOl
OW
a:
L...--
ST-
Reset
logic
(J'~ (J
~~'g>~
,
RTM
~~~~ ~
36. "
Pointer
Ao- A35
C/)!::...J
Pointer....oL
RFM
'--
. . . . . Bo-B35
OR
AE
1 Status .Flag ,
IR
AF
logiC
t
-,
FSOI SD
FS1/S EN
Flag Offset
Registers
I
,
~
1
I
-L--
~
0...:./1
"I
Mail 2
Register
L
I--
Port-B
Control
logic
~ ClKB
~ .Q.SB
~ W/RB
I--- ENB
'-- MBB
T
3023 drw 01
The lOT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MARCH 1995
COMMERCIAL TEMPERATURE RANGE
DSC-2067/-
©1995 Integrated Device Technology, Inc.
5.12
1
IDT723631/723641/723651 CMOS SyncFIFOTM
512 X 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
most empty) to indicate when a selected number of words is
stored in memory. Communication between each port may
take place with two 36-bit mailbox registers. Each mailbox
register has a flag to signal when new mail has been stored.
Two or more devices may be used in parallel to create wider
data paths. Expansion is also possible in word depth.
The IDT723631 1723641 1723651 is a clocked FIFO, which
means each port employs a synchronous interface. All data
transfers through a port are gated to the lOW-to-HIGH
transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent
of one another and can be asynChronous or coincident. The
enables for each port are arranged to provide a simple
interface between microprocessors and/or buses with synchronous control.
The input-ready (IR) flag and almost-fuJI (AF) flag of the
FI FO are two-stage synchronized to ClKA. The output-ready
(OR) flag and almost-empty (AE) flag of the FIFO are twostage synchronized to ClKS. Offset values for the almost-full
and almost empty flags of the FIFO can be programmed from
port A or through a serial input.
PIN CONFIGURATION
NC
NC
NC
835
834
833
832
A35
A34
A33
A32
GND
831
830
829
828
827
826
A30
Vee
A27
Vce
A31
GND
A29
A28
825
824
GND
823
822
821
820
819
818
A26
A25
PO 132-1
A24
A23
GND
A22
Vce
A21
A20
GND
A19
A18
817
816
GND
Vcc
A17
A16
815
814
813
812
A15
A14
A13
GND
NC
NC
Vce
A12
NC
3023 drw 02
Notes:
1.
2.
NC - No internal connection
Uses Yamaichi socket IC51-1324-828
PQFPACKAGE
TOP VIEW
5.12
2
IDT723631n23641n23651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (CONTINUED)
omOO~W~~MN~omOO~W~~MN~OmOO~W~~MN~
N~~~~~~~~~~oooooooooommmmmmmmm
~~~~~~~~~~~~~~~~~~~~~
1
A35
A34
A33
A32
3
4
A31
A30
7
Vee
835
834
833
832
2
5
GND
6
GND
8
A29
A28
A27
A26
A25
A24
A23
9
831
830
829
828
827
826
10
11
Vee
12
13
14
15
GND
16
A22
17
825
824
PN120 - 1
GND
823
822
821
820
819
818
Vee
18
A21
A20
A19
A18
20
21
22
A17
24
A16
A15
A14
A13
25
Vee
26
27
815
814
813
812
GND
19
GND
23
817
816
28
Vee
29
A12
30
GND
3023 drw 02a
Note:
1. NC - No internal connection
TQFP
TOP VIEW
5.12
3
10T72363117236411723651 CMOS SyncFIFOTM
512 X 36,1024 X 36, 2048 X 36
CO~.~~.~ERC!A!.. TE~.~r'EnATUnE ~ANGE
PIN DESCRIPTION
Symbol
AO-A35
Name
Port-A Data
1/0
Description
1/0 36-bit bidirectional data port for side A.
AE
Almost-Empty Flag
0
Programmable flag synchronized to ClKB. It is lOW when the number of
words in the FIFO is less than or equal to the value in the almost-empty
reqister (X).
AF
Almost-Full Flag.
0
Programmable flag synchronized to ClKA. It is lOW when the number of
empty locations in the FIFO is less than or equal to the value in the almost-full
offset register (Y).
BO-B35
Port-B Data.
I/O 36-bit bidirectional data port for side B.
ClKA
Port-A Clock
I
ClKA is a continuous clock that synchronizes all data transfers through port-A
and may be aynchronous or coincident to ClKB. IR and AF are synchronous
to the lOW-to-HIGH transition of ClKA.
ClKB
Port-B Clock
I
ClKB is a continuous clock that synchronizes all data transfers through port-B
and may be asynchronous or coincident to ClKA. OR and AE are synchro
nous to the lOW-to-HIGH transition of ClKB.
CSA
Port-A Chip Select
I
CSA must be lOW to enable a lOW-to-HIGH transition of ClKA to read or
write data on port-A. The AO-A35 outputs are in the high-impedance state
when CSA is HIGH.
CSB
Port-B Chip Select
I
CSB must be lOW to enable a lOW-to-HIGH transition of ClKB to read or
write data on port-B. The BO-B35 outputs are in the high-impedance state
when CSB is HIGH.
ENA
Port-A Enable
I
ENA must be HIGH to enable a lOW-to-HIGH transition of ClKA to read or
write data on port-A.
ENB
Port-B Enable
I
ENB must be HIGH to enable a lOW-to-HIGH transition of ClKB to read or
write data on port-B.
Flag-Offset Select 1I
Serial Enable,
Flag Offset 01
Serial Data
I
FS1/SEN and FSO/SD are dual-purpose inputs used for flag offset register
programming. During a device reset, FS1/SEN and FSO/SD selects the flag
offset programming method. Three offset register programming methods are
available: automatically load one of two preset values, parallel load from port
A, and serial load. When serial load is selected for flag offset register program
ming, FS1/SEN is used as an enable synchronous to the lOW-to-HIGH
transition of ClKA. When FS1/SEN is lOW, a rising edge onClKA load the
bit present on FSO/SD into the X and Y registers. The number of bit writes
required to program the offset registers is 18120/22. The first bit write stores
the V-register MSB and the last bit write stores the X-register lSB.
Input-Ready Flag
0
IR is synchronized to the lOW-to-HIGH transition of ClKA. When IR is lOW,
the FIFO is full and writes to its array are disabled. When the FIFO is in
retransmit mode, IR indicates when the memory has been filled to the point of
the retransmit data and prevents further writes. IR is set lOW during reset
and is set HIGH after reset.
FS1/SEN,
FSO/SD
IR
MBA
Port-A Mailbox Select
I
A HIGH level chooses a mailbox register for a port-A read or write operation.
MBB
Port-B Mailbox Select
I
A HIGH level chooses a mailbox register for a port-B read or write operation.
When the BO-B35 outputs are active, a HIGH level on MBB selects data from
the mail1 register for output and a lOW level selects FIFO data for output.
MBF1
Mail1 Register Flag
0
MBF1 is set lOW b~lOW-to-HIGH transition of ClKA that writes data to
the mail1 register. MBF1 is set HIGH by a lOW-to-HIGH transition of ClKB
when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH by a
reset.
3023 tbl 01
5.12
4
IDT72363117236411723651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol
Name
1/0
MSF2
Mail2 Register Flag
0
MSF2 is set lOW b~lOW-to-HIGH transition of elKS that writes data to
the mail2 register. MSF2 is set HIGH by a lOW-to-HIGH transition of ClKA
when a port-A read is selected and MSA is HIGH. MSF2 is set HIGH by a
reset.
OR
Output-Ready Flag
0
OR is synchronized to the lOW-to-HIGH transition of ClKS. When OR is
lOW, the FIFO is empty and reads are disabled. Ready data is present in the
output register of the FIFO when OR is HIGH. OR is forced lOW during the
reset and goes HIGH on the third lOW-to-HIGH transition of ClKS after a
word is loaded to empty memory.
RFM
Read From Mark
I
When the FIFO is in retransmit mode, a HIGH on RFM enables a lOW-toHIGH transition of ClKS to reset the read pointer to the beginning retransmit
location and output the first selected retransmit data.
RST
Reset
I
To reset the device, four lOW-to-HIGH transitions of ClKA and four lOW-toHIGH transitions of ClKS must occur while RST is lOW. The lOW-to-HIGH
transition of RST latches the status of FSO and FS1 for AF and AE offset
selection.
RTM
Retransmit Mode
I
When RTM is HIGH and valid data is present in the FIFO output register (OR
is HIGH), a lOW-to-HIGH transition of ClKS selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word
remains the initial retransmit point until a lOW-to-HIGH transition of ClKS
occurs while RTM is lOW, taking the FIFO out of retransmit mode.
W/RA
W/RS
Port-A Write/Read
Select
I
Port-S Write/Read
Select
I
Description
A HIGH selects a write operation and a lOW selects a read operation on
port A for a lOW-to-HIGH tran~ion of ClKA. The AO-A35 outputs are in the
high-impedance state when W/RA is HIGH.
A lOW selects a write operation and a HIGH selects a read operation on
port S for a lOW-to-HIGH tr~sition of ClKS. The SO-S35 outputs are in the
high-impedance state when W/RS is HIGH.
3023 tbl 02
5.12
5
I
II
I
IDT123631n23641n23651 CMOS SyncFIFOTM
512 x 36, 1024 x 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(2)
Symbol
Commercial
Unit
-0.5 to 7
V
Input Voltage Range
-0.5 to Vee+0.5
V
Output Voltage Range
-0.5 to Vee+0.5
V
Input Clamp Current, (VI < 0 or VI > Vee)
±20
rnA
±50
rnA
lOUT
=< 0 orVo > Vee)
Continuous Output Current,.(Vo =0 to Vee)
±50
rnA
Icc
Continuous Current Through Vee or GND
±400
rnA
TA
Operating Free Air Temperature Range
TSTG
Storage Temperature Range
Rating
Vee
VI(2)
Supply Voltage Range
VO(2)
11K
Output Clamp Current, (Va
10K
Oto 70
°C
-65 to 150
°C
3023 tbl 03
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure
to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VIH
Min.
Max. Unit
V
4.5
5.5
HIGH Level Input Voltage
2
-
V
VIL
LOW-Level Input Voltage
-
0.8
V
IOH
HIGH-Level Output Current
-
-4
rnA
IOL
LOW-Level Output Current
-
8
rnA
TA
Operating Free-air
Temperature
0
70
°C
3023 tbl 04
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
=4.5V,
Test Conditions
Min.
=-4 rnA
2.4
Typ.(1)
Max.
Unit
V
VOH
Vee
VOL
Vee =4.5 V,
IOL= 8 rnA
0.5
V
III
Vee = 5.5 V,
VI = Vee or 0
±5
~A
ILO
Vee = 5.5 V,
Va = Vee or 0
±5
~A
Ice
i1lee(2)
Vee = 5.5 V,
VI = Vee -0.2 V or 0
400
Vee = 5.5 V,
One Input at 3.4 V,
IOH
Other Inputs at Vee or GND
AO-A35
0
CS8 =VIH
'80-835
0
CSA=VIL
AO-A35
1
80-35
1
CS8
=VIL
All Other Inputs
~A
rnA
CSA=VIH
1
CIN
VI=O,
f = 1 MHz
4
pF
COUT
Vo=O,
f = 1 MHZ
8
pF
3023 tbl 05
NOTES:
1. All typical
values are at vee =5 V. TA =25°C.
2. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0 V or vee.
5.12
6
IDT723631n23641n23651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE
Symbol
IDT723631L15 IDT723631L20 IDT723631L30
IDT723641L15 IDT723641L20 IDT723641L30
IDT723651L15 IDT723651L20 IDT723651L30
Min.
Max.
Max.
Min.
Max.
Min.
Parameter
Unit
fs
Clock Frequency, ClKA or ClKB
-
66.7
-
50
-
33.4
MHz
tClK
Clock Cycle Time, ClKA or ClKB
15
-
ns
6
12
-
ns
tClKl
Pulse Duration, ClKA or ClKB lOW
6
12
Setup Time, AO-A35 before ClKAi and BO-B35
before ClKBi
5
-
ns
tos
-
30
Pulse Duration, ClKA or ClKB HIGH
-
20
tClKH
-
ns
8
8
6
7
6
-
7
7.5
-
8
-
6.5
-
7
-
10
-
11
-
0
-
0
0
9
-
12
-
tENS1
Setup Time, ENA to ClKAi; ENB to ClKBi
5
tENS2
Setup Time, CSA, W/RA, and MBA to ClKAi;
CSB, W/RB, and MBB to ClKBi
7
tRMS
Setup Time, RTM and RFM to ClKBi
6
tRSTS
Setup Time, RST lOW before ClKA i
or ClKBi(l)
5
tFSS
Setup Time, FSO and FS1 before RST HIGH
9
tsOS(2)
Setup Time, FSO/SD before ClKA i
5
tSENS(2)
Setup Time, FS1/SEN before ClKA i
5
tOH
Hold Time, AO-A35 after ClKA i and BO-835
after ClKBi
0
tENH1
Hold Time, ENA after ClKAi; ENB after ClKBi
0
tENH2
Hold Time, CSA, W/RA, and MBA after ClKAi;
CSB, W/RB, and MBB after ClKBi
0
tRMH
Hold Time, RTM and RFM after ClKBi
0
tRSTH
Hold Time, RST lOW after ClKAi or ClKBi(l)
5
tFSH
Hold Time, FSO and FS1 after RST HIGH
0
tSPH(2)
Hold Time, FS1/SEN HIGH after RST HIGH
0
tSOH(2)
Hold Time, FSO/SD after ClKA i
0
tSENH(2)
Hold Time, FS1/SEN after CLKAi
0
tSKEW1(3)
Skew Time, between ClKAi and ClKBi
for OR and IR
tSKEW2(3)
Skew Time, between ClKAi and ClKBi
for AE and AF
-
6
6
6
0
0
7
7
7
0
-
ns
ns
ns
ns
ns
ns
-
ns
ns
ns
0
-
0
ns
0
-
ns
11
-
13
-
ns
16
-
20
-
ns
6
0
0
0
0
0
7
0
0
II
ns
ns
ns
ns
ns
3023 tbl 06
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Only applies when serial load method is used to program flag offset registers.
3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and ClKB
cycle.
5.12
7
IDT723631n236411723651 CMOS SyncFIFOTM
512 x 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
IDT723631 L 15 IDT723631L20 IDT723631 L30
IDT723641L15 I DT723641 L20 IDT723641L30
IDT723651 L 15 IDT723651 L20 IDT723651L30
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Is
Clock Frequency, ClKA or ClKB
-
66.7
-
50
-
33.4
MHz
tA
Access Time, ClKB! to BO-B35
3
11
3
13
3
15
ns
tPIR
Propagation Delay Time, ClKA! to IR
1
8
1
10
1
12
ns
tPOR
Propa~ation Delay Time, ClKB! to OR
1
8
1
10
1
12
ns
tPAE
Propagation Delay Time, ClKB! to AE
1
8
1
10
1
12
ns
tPAF
Propagation Delay Time, ClKA! to AF
1
8
1
10
1
12
ns
tPMF
Propagation Delay Time, ClKA! to MBF1
lOW or MBF2 HIGH and ClKB! to MBF2
lOW or MBF1 HIGH
0
8
0
10
0
12
ns
tPMR
Propagation Delay Time, ClKA! to BO-B35(1)
and ClKB! to AO-A35(2)
3
13.5
3
15
3
17
ns
tMDV
Propagation Delay Time, MBB to BO-B35 Valid
3
13
3
15
3
17
ns
tRSF
Propagation Delay Time, RST lOW to AE lOW
and AFHIGH
1
15
1
20
1
30
ns
tEN
Enable Time, CSA and W/RA lOW to AO-A35
Active and CSB lOW and VV/RB HIGH to
BO-B35 Active
2
12
2
13
2
14
ns
tDIS
Disable Time, CSA or WiRA HIGH to AO-A35
at high impedance and CSB HIGH or VV/RB
lOW to BO-B35 at high impedance
1
8
1
10
1
11
ns
3023 tbl 07
NOTES:
1. Writing data to the mail1 register when the
2. Writing data to the mail2 register when the
BO-B35 outputs are active and MBB is HIGH.
AO-A35 outputs are active and MBA is HIGH.
5.12
8
IDT723631n23641n23651 CMOS SyncFIFOTM
512 X 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION
RESET
The IDT723631n23641n23651 is reset by taking the
reset (RSl) input LOW for at least four port-A clock (CLKA)
and four port-B (CLKB) LOW-to-HIGH transitions. The reset
input may switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the
input-ready (IR) flag LOW, the output-ready (OR) flag HIGH,
the almost-empty (AE) flag LOW, and the almost-full (AF) flag
HIGH. Resetting the device also forces the mailbox flags
(MBF1, MBF2) HIGH. After a FIFO is reset, its input-ready flag
is set HIGH after at least two clock cycles to begin normal
operation. A FIFO must be reset after power up before data
is written to its memory.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING
Two registers in the IDT723631 n23641 n23651 are used
to hold the offset values for the almost-empty and almost full
flags. The almost-empty (AE) flag offset register is labeled X,
and the almost-full (AF) flag offset register is labeled Y. The
offset register can be loaded with a value in three ways: one
of two preset values are loaded into the offset registers,
parallel load from port A, or serial load. The offset register
programming mode is chosen by the flag select (FS1, FSO)
inputs during a LOW-to-HIGH transition on the RST input (See
Table 1).
PRESET VALUES
If the preset value of 8 or64 is chosen by the FS1 and FSO
inputs at the time of a RST LOW-to-HIGH transition according
to Table 1, the preset value is automatically loaded into the X
and Y registers. No other device initialization is necessary to
begin normal operation, and the IR flag is set HIGH after two
LOW-to-HIGH transitions on CLKA.
PARALLEL LOAD FROM PORT A
To program the X and Y registers from port A, the device
is reset with FSO and FS1 LOW during the LOW-to-HIGH
transition of RST. After this reset is complete, the IR flag is set
HIGH after two LOW-to-HIGH transitions on CLKA. The first
two writes to the FI Fa do not store data in its memory but load
the offset registers in the order Y, X. Each offset register of the
IDT723631, IDT723641, and IDT723651 uses port-A inputs
(A8-AO), (A9-AO), and (A 1O-AO), respectively. The highest
number input is used as the most significant bit of the binary
number in each case. Each register value can be programmed from 1 to 508 (IDT723631), 1 to 1020 (IDT723641),
and 1 to 2044 (IDT723651). After both offset registers are
programmed from port A, subsequent FIFO writes store data
in the SRAM.
Y register values are loaded bitwise through the FSO/SD input
on each LOW-to-HIGH transition of CLKA that the FS1/SEN
input is LOW. Eighteen-, 20-, or 22-bit writes are needed to
complete the programming forthe IDT723631, IDT723641, or
IDT723651, repsectively. The first-bit write stores the most
significant bit of the Y register, and the last-bit write stores the
least significant bit of the X register. Each register value can
be programmed from 1 to 508 (IDT723631), 1 to 1020
(IDT723641), or 1 to 2044 (IDT723651).
When the option to program the offset registers serially is
chosen, the input-ready (IR) flag remains LOW until all register bits are written. The IR flag is set HIGH by the LOW-toHIGH transition of CLKA after the last bit is loaded to allow
normal FIFO operation.
FIFO WRITE/READ OPERATION
The state of the port-A data (AO-A35) outputs is controlled
by the port-A chip select (CSA) and the port-A write/read
select (WiRA). The AO-A35 outputs are in the high-impedance state when either CSA or WiRA is HIGH. The AO-A35
outputs are active when both CSA and WiRA are LOW.
Data is loaded into the FIFO from the AO-A35 inputs on a
LOW-to-HIGH transition of CLKA when CSA and the port-A
mailbox select (MBA) are LOW, WiRA, the port-A enable
(ENA), and the input-ready (IR) flag are HIGH (see Table 2).
Writes to the FIFO are independent of any concurrent FIFO
read.
The port-B control signals are identical to those ~ port-A
with the exception that the port-B write/read select (W/RB) is
the inverse of the port-A write/read select (WiRA). The state
of the port-B data (BO-B35) outputs is controlled by t~ portB chip select (CSB) and the port-B writelread select (W/RB).
The BO-B35 outputs are in the high-impedance state when
either CSB is HIGH or W/RB is LOW. The BO-B35 outputs are
active when CSB is LOW and W/RB is HIGH.
Data is read from the FI Fa to its output register on a LOWto-HIGH transition of CLKB when CSB and the port-B mailbox
select (MBB) are LOW, W/RB, the port-B enable (ENB), and
the output-ready (OR) flag are HIGH (see Table 3). Reads
from the FIFO are independent of any concurrent FIFO writes.
The setup- and hold-time constraints to the port clocks for
the port-chip selects and write/read selects are only for
enabling write and read operations and are not related to high-
FS1
H
FSO
H
H
L
L
H
L
L
RST
i
i
i
i
X and Y Registers (1)
Serial Load
64
8
Parallel Load From Port A
3023 tbl 08
SERIAL LOAD
To program the X and Y registers serially, the device is
reset with FSO/SD and FS1/SEN HIGH during the LOW-toHIGH transition of RST. After this reset is complete, the X and
5.12
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
Table 1. Flag Programming
9
I
II
IDT72363117236411723651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
impedance control of the data outputs. If a port enable is lOW
during a clock cycle, the port chip select and write/read select
may change states during the setup- and hold time window of
the cycle.
When the output-ready (OR) flag is lOW, the next data
word is sent to the FIFO output register automatically by the
ClKS lOW-to-HIGH transition that sets the output-ready flag
HIGH. When OR is HIGH, an available data word is clocked
to the FIFO output register only when a FIFO read is selected
by the port-S chip select (CSS), write/read select (Vii/RS),
enable (ENS), and mailbox select (MSS).
SYNCHRONIZED FIFO FLAGS
Each IDT723631n23641/723651 FIFO flag is synchronized to its port clock through at least two flip-flop stages. This
is done to improve the flags' reliability by reducing the probability of metastable events on their outputs when ClKA and
ClKS operate asynchronously to one another. OR and AE are
synchronized to ClKS. I Rand AF are synchronized to ClKA.
Table 4 shows the relationship of each flag to the number of
words stored in memory.
OUTPUT-READY FLAG (OR)
The output-ready flag of a FIFO is synchronized to the port
clock that reads data from its array (ClKS). When the outputready flag is HIGH, new data is present in the FIFO output
register. When the output-ready flag is lOW, the previous
data word is present in the FI FO output register and attempted
FIFO reads are ignored. '
A FI FO read pointer is incremented each time a new word
is clocked to its output register. The state machine that
controls an output-ready flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM
status is empty, empty+ 1, or empty+2. From the time a word
is written to a FIFO, it can be shifted to the FIFO output register
in a minimum of three cycles of ClKS. Therefore, an outputready flag is lOW if a word in memory is the next data to be
sent to the FIFO output register and three ClKS cycles have
not elapsed since the time the word was written. The outputready flag of the FIFO remains lOW until the third lOW-toHIGH transition of ClKS occurs, simultaneously forcing the
output-ready flag HIGH and shifting the word to the FIFO
output register.
A lOW-to-HIGH transition on ClKS begins the first synchronization cycle of a write if the clock transition occurs at
time tSKEW1 or greater after the write. Otherwise, the subsequent ClKS cycle may be the first synchronization cycle (see
Figure 6).
INPUT READY FLAG (IR)
The input ready flag of a FIFO is synchronized to the port
clock that writes data to its array (ClKA). When the input-
WiRA
ENA
MBA
ClKA
AO-A35 Outputs
Port Functions
H
X
X
l
X
X
None
H
X
X
In High-Impedance State
l
In High-Impedance State
None
l
H
H
l
In High-Impedance State
FIFO Write
CSA
l
H
H
H
i
i
In High-Impedance State
Mail1 Write
l
l
l
l
X
Active, Mail2 Register
None
l
l
H
l
i
Active, Mail2 Register
None
l
l
l
H
X
Active, Mail2 Register
None
l
l
H
H
i
Active, Mail2 Register
Mail2 Read (Set MSF2 HIGH)
3023 tbl 09
Table 2. Port·A Enable Function Table
CSS
W/RB
ENB
MBB
ClKB
BO-A35 Outputs
Port Functions
H
X
X
None
l
l
X
X
In High-Impedance State
l
X
X
In High-Impedance State
None
l
l
H
l
In High-Impedance State
None
l
l
H
H
i
i
In High-Impedance State
Mail2 Write
l
H
l
l
X
Active, FIFO Output Register
None
L
H
H
l
i
Active, FIFO Output Register
FIFO read
l
H
l
H
X
Active, Mail1 Register
None
l
H
H
H
i
Active, Mail1 Register
Mail1 Read (Set MSF1 HIGH)
3023 tbl10
Table 3. Port·B Enable Function Table
5.12
10
IDT723631n23641n23651 CMOS SyncFIFOTM
512 X 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
ready flag is HIGH, a memory location is free in the SRAM to
write new data. No memory locations are free when the inputready flag is lOW and attempted writes to the FIFO are
ignored.
Each time a word is written to a FIFO, its write pointer is
incremented. The state machine that controls an input-ready
flag monitors a write-pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory
location is ready to be written in a minimum of three cycles of
ClKA. Therefore, an input-ready flag is lOW if less than two
cycles of ClKA have elapsed since the next memory write
location has been read. The second lOW-to-HIGH transition
on ClKA after the read sets the input-ready flag HIGH, and
data can be written in the following cycle.
A lOW-to-HIGH transition on ClKA begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent ClKA cycle may be the first synchronization cycle (see
Figure 7).
ALMOST-EMPTY FLAG (AE)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array (ClKS). The state
machine that controls an almost-empty flag monitors a writepointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost empty, almost empty+1, or
almost empty+2. The almost-empty state is defined by the
contents of register X. This register is loaded with a preset
value during a FIFO reset,programmed from port A, or programmed serially (see almost-empty flag and almost-full flag
offset programming above). The almost-empty flag is lOW
when the FIFO contains X or less words and is HIGH when the
FIFO contains (X+ 1) or more words. A data word present in
the FIFO output register has been read from memory.
Two lOW-to-HIGH transitions of ClKS are required after
a FIFO write for the almost-empty flag to reflect the new level
of fill; therefore, the almost-empty flag of a FIFO containing
(X+ 1) or more words remains lOW if two cycles of ClKS have
not elapsed since the write that filled the memory to the (X+ 1)
level. An almost-empty flag is set HIGH by the second lOWto-HIGH transition of ClKS after the FIFO write that fills
memory to the (X+ 1) level. A lOW-to-HIGH transition of
ClKS begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the write that fills the FI FO to (X+ 1)
words. Otherwise, the subsequent ClKS cycle may be the
first synchronization cycle (see Figure 8).
ALMOST-FULL FLAG (AF)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array (ClKA). The state machine
that controls an almost-full flag monitors a write-pointer and
read-pointer comparator that indicates when the FI FO SRAM
status is almost full, almost full-1 , or almost full-2. The almostfull state is defined by the contents of register Y. This register
is loaded with a preset value during a FI FO reset, programmed
from port A, or programmed serially (see almost-empty flag
and almost-full flag offset programming). The almost-full flag
is lOW when the number of words in the FIFO is greater than
orequalto(512-Y), (1 024-Y), OR (2048-Y) forthe IDT723631,
IDT723641, or IDT723651, respectively. The almost-full flag
is HIGH when the number of words in the FIFO is less than or
equal to [512-(Y+1)], [1024-(Y+1)], or [2048-(Y+1)] for the
IDT723631, IDT723641, or IDT723651, respectively. A data
word present in the FIFO output register has been read from
memory.
Two lOW-to-HIGH transitions of ClKA are required after
a FIFO read for its almost-full flag to reflect the new level of fill.
Therefore, the almost-full flag of a FIFO containing [51211 0241
2048-(Y+ 1)] or less words remains lOW if two cycles of ClKA
have not elapsed since the read that reduced the number of
words in memory to [512/1024/2048-(Y+1)]. An almost-full
flag is set HIGH by the second lOW-to-HIGH transition of
ClKA after the FIFO read that reduces the number of words
in memory to [51211024/2048-(Y+1)]. A lOW-to-HIGH transition of ClKA begins the first synchronization cycle if it occurs
at time tSKEW2 or greater after the read that reduces the
number of words in memory to [51211 024/2048-(Y + 1)]. Otherwise, the subsequent ClKA cycle may be the first synchronization cycle (see Figure 9).
Number of Words in the FIFO(l,2)
Synchronized
Synchronized
to ClKB
to CLKA
IDT723631
IDT723641
IDT723651
OR
AE
AF
IR
0
0
0
l
l
H
H
1 to X
1 to X
1 to X
H
l
H
H
(X+1) to [512-(Y+1)]
(X+ 1) to [1 024-(Y+ 1)]
(X+1) to [2048-(Y+1)]
H
H
H
H
(512-Y) to 511
(1024-Y) to 1023
(2048-Y) to 2047
H
H
l
H
512
1024
2048
H
H
l
l
3023 !bIll
NOTES:
1. X is the almost-empty offset for AE Y is the almost-full offset for AF.
2. When a word is present in the FIFO output register, its previous memory location is free.
Table 4. FIFO Flag Operation
5.12
11
II
IDT7236311723641n23651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
SYNCHRONOUS RETRANSMIT
The synchronous retransmit feature of the IDT7236311
723641n23651 allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into
retransmit mode to select a beginning word and prevent ongoing FIFO write operations from destroying retransmit data.
Data vectors with a minimum length of three words can
retransmit repeatedly starting at the selected word. The FIFO
can be taken out of retransmit mode at any time and allow
normal device operation.
The FIFO is put in retransmit mode by a lOW-to-HIGH
transition on ClKS when the retransmit mode (RTM) input is
HIGH and OR is HIGH. The rising ClKS edge marks the data
present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a lOW-to-HIGH
transition occurs while RTM is lOW.
When two or more reads have been done past the initial
retransmit word, a retransmit is initiated by a lOW-to-HIGH
transition on ClKS when the read-from-mark (RFM) input is
HIGH. This rising ClKS edge shifts the first retransmit word
to the FI FO output register and subsequent reads can begin
immediately. Retransmit loops can be done endlessly while
the FIFO is in retransmit mode. RFM must be lOW during the
ClKS rising edge that takes the FIFO out of retransmit mode.
When the FIFO is put into retransmit mode, it operates
with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the
FIFO output register and used by the OR and AE flags. The
shadow read pointer stores the SRAM location at the time the
device is put into retransmit mode and does not change until
the device is taken out of retransmit mode. The shadow read
pointer is used by the IR and AF flags. Data writes can
proceed while the FIFO is in retransmit mode, but AF is set
lOW by the write that stores (512 - V), (1024 - V), or (2048 Y) words after the first retransmit word for the IDT723631,
IDT723641, or IDT723651, respectively. The IR flag is set
lOW by the 512th, 1024th, or 2048th write after the first
retransmit word forthe IDT723631 , IDT723641 , or I DT723651 ,
respectively.
SYNCHRONOUS TRANSMIT
When the FIFO is in retransmit mode and RFM is HIGH,
a rising elKS edge loads the current read pointer with the
shadow read-pointer value and the OR flag reflect the new
level of fill immediately. If the retransmit changes the FIFO
status out of the almost-empty range, up to two ClKS rising
edges after the retransmit cycle are needed to switch AE high
(see Figure 11 ).The rising ClKS edge that takes the FIFO out
of retransmit mode shifts the read pointer used by the IR and
AF flags from the shadow to the current read pointer. If the
change of read pointer used by IR and AF should cause one
or both flags to transmit HIGH, at least two ClKA synchronizing cycles are needed before the flags reflect the change. A
rising ClKA edge after the FIFO is taken out of retransmit
mode is the first synchronizing cycle of IR if it occurs at time
tSKEW1 or greater after the rising ClKS edge (see Figure 12).
A riSing ClKA edge after the FIFO is taken out of retransmit
mode is the first synchronizing cycle of AF if it occurs at time
tSKEW2 or greater after the rising ClKB edge (see Figure 14).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723631 n23641 I
723651 to pass command and control information between
port A and port B. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A lOW-to-HIGH transition on ClKA writes
AO-A35 data to the mail1 register when a port-A write is
selected by CSA, W/RA, and ENA with MBA HIGH. A lOWto-HIGH transition on ClKB writes BO-B35 data to the mail2
register when a port-B write is selected by CSB, W/RB, and
ENB with MBB HIGH. Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) lOW. Attempted writes
to a mail register are ignored while its mail flag is lOW.
When the port-B data (BO-B35) outputs are active, the
data on the bus comes from the FI FO output register when the
port-B mailbox select (MBB) input is lOW and from the mail1
register when MBB is HIGH. Mail2 data is always present on
the port-A data (AO-A35) outputs when they are active. The
mail1 register flag (MSF1) is set HIGH by a LOW-to-HIGH
transition on ClKB when a port-B read is selected by CSB, WI
RB, and ENB with MBB HIGH. The mail2 register flag (MBF2)
is set HIGH by a lOW-to-HIGH transition on ClKA when a
port-A read is selected by CSA, W/RA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.
5.12
12
10T72363117236411723651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ClKA
ClKB
FS1,FSO
IR
OR
MBF1,
MBF2
11
Figure 1. FIFO Reset Loading X and Y with a Preset Value of Eight
ClKA
FS1,FSO
IR
ENA
AO - A35
AFOffset
(Y)
AEOffset
(X)
First Word
Stored in FIFO
3023 drw05
NOTE:
1. CSA =LOW, W/RA.
=HIGH, MBA =LOW.
It is not necessary to program offset register on consecutive clock cycles.
Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values from Port A
5.12
13
IDT723631n23641n23651 CMOS SyncFIFOTM
512 X 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
ClKA
IR
tFSSI4-:'\-'+II4-_ _ _ tSPH _ _ _ _+-~~1
FS1/SEN
FSO/SD
AFOffset
(Y)MSB
AEOffset
(X) lSB
NOTE:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored untillR is set HIGH.
3023 drw06
Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially
ClKA
IR
W/RA
MBA
ENA
AO - A35
3023 drw07
Figure 4. FIFO Write-Cycle Timing
ClKB
OR
HIGH
CSB
W/RB
MBB
ENB
BO - B35
Figure 5. FIFO Read-Cycle Timing
5.12
14
IDT723631n23641n23651 CMOS SyncFIFOTM
512 X 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
ClKA
CSA
WRA
MBA
ENA
IR
AO - A35
ClKB
OR
Old Data in FIF01 Output Register
CSB
lOW
VV/RB
HIGH
MBB
lOW
BO-B35
II
Old Data in FIFO Output Register
W1
3023 drw 09
NOTE:
1. tSKEW1 is the minimum time between a rising ClKA edge and a rising ClKS edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three ClKS cycles. If the time between the rising ClKA edge and rising ClKS edge is less than tSKEW1, then the transition of OR HIGH and
the first word load to the output register may occur one ClKS cycle later than shown.
Figure 6. OR Flag Timing and First Data Word Fallthrough when the FIFO is Empty
5.12
15
IDT123631n23641n23651 CMOS SyncFIFOTM
512 x 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
------"
ClKB
CSB
lOW
W/RB
MBB
HIGH
,~-----
lOW
r,tENHl
tENS1;-::--,.
ENB
OR
BO-B35 ______________
~~
______
~I'
______________________________________________________
ClKA
IR
~~~~
CSA __
~~
____________________________________________- - ' I
r_-------------------
______________________________________________________
WRA
MBA~~~~~~~~~~~~~~~~~~~~~~~~~,~~~~-~~~~~~~
3023 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising ClKS edge and a rising ClKA edge for IR to transition HIGH in the next ClKA cycle. If the time between
the rising ClKS edge and rising ClKA edge is less than tSKEW1, then IR may transition HIGH one ClKA cycle later than shown.
Figure 7. IR Flag Timing and First Available Write when the FIFO is Full
CLKA /
ENA
~ ~;.:~
" _ _ _, ,
~~~
___S;~~~~~__________________________________________
tSKEW2 (1l.-
ClKB
X Word in FIFO
ENB ________________________________________________________
~~~~
3023 drw 11
NOTES:
1. tSKEW2 is the minimum time between a rising ClKA edge and a rising ClKS edge for AE to transition HIGH in the next ClKS cycle. If the time between
the rising ClKA edge and rising ClKS edge is less than tSKEW2, then AE may transition HIGH one ClKS cycle later than shown.
2. FIFO write (CSA = lOW, WlRA = HIGH, MSA = lOW), FIFO read (CSS = lOW, W/RS = HIGH, MSS = lOW).
Figure 8. Timing for AEwhen FIFO is Almost Empty
5.12
16
IDT723631n23641n23651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ClKA
AF
(Depth (~,'r') Words in FIFO
[Depth (::l(Y+l)] Words in FIFO
ClKS _ _--'
ENS
3023 drw 12
NOTES:
1. tSKEW2 is the minimum time between a rising GLKA edge and a rising GLKB edge for AF to transition HIGH in the next GLKA cycle. If the time between
the rising GLKB edge and rising GLKA edge is less than tSKEW2, then AF may transition HIGH one GLKA cycle later than shown.
2. Depth is 512 for the IDT723631, 1024 for the IDT723641, and 2048 for the IDT723651.
3. FIFO write (GSA LOW, WiRA HIGH, MBA LOW), FIFO read (GSB LOW, W/RB HIGH, MBB LOW).
=
=
=
=
=
=
Figure 9. Timing for AFwhen FIFO is Almost Full
ClKS
II
ENS
RTM
RFM
OR
BO-B35
HIGH
--------~W~0-------t-A:;k----~W~1----t-A:;k----~W~2----Initiate Retransmit Mode
with WO as First Word
WO
tA:;k----,W..,....,...,...1- -
End Retransmit
Mode
Retransmit from
Selected Position
3023 drw 13
NOTE:
1. GSB LOW, W/RB HIGH, MBB LOW. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit. Other
enables are shown only to relate retransmit operations to the FIFO output register.
=
=
=
Figure 10. Retransmit Timing Showing Minimum Retransmit Length
ClKB
RTM
HIGH
tRMS~
K,tRMH
RFM
...-:-;- tPAE
x or fewer words from Empt
(x+ 1) or more
words from Empty
3023 drw fig 11
NOTE:
1. X is the value loaded in the almost empgy flag offset register.
Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X.
5.12
17
IDT723631n23641n23651 CMOS SyncFIFOTM
512 X 36,1024 X 36, 2048 X 36
ClKA
IR
"
/
FIFO Filled to First Restransmit Word
COMMERCIAL TEMPERATURE RANGE
f
(1)
SKEW1
::r-
1
'~----~2
,~----~~
,~----~/
1- t P I R - - J r _ - - - - - - - - - - - - - One or More Write locations Available
ClKS
RTM
3023 drw 14
NOTE:
1. tSKEW1 is the minimum time between a rising ClKS edge and a rising ClKA edge for IR to transition HIGH in the next ClKA cycle. If the time between
the rising ClKS edge and rising ClKA edge is less than tSKEW1. then IR may transition HIGH one ClKA cycle later than shown.
Figure 12.IR Timing from the End of Retransmit Mode when One or More Write Locations are Available
ClKA
AF~~__~____________~----------------------------"
ClKS
,.-.tRMH
RTM
3023 drw 15
NOTES:
1. tSKEW2 is the minimum time between a rising ClKS edge and a rising ClKA edge for AF to transition HIGH in the next ClKA cycle. If the time between
the rising ClKS edge and rising ClKA edge is less than tSKEW2. then AF may transition HIGH one ClKA cycle later than shown.
2. Depth is 512 for the IDT723631. 1024 for the IDT723641. and 2048 for the IDT723651.
3. Y is the value loaded in the almost-full flag offset register.
Figure 13. AFTiming from the End of Retransmit Mode when (Y+1) or More Write Locations are Available
5.12
18
IDT723631n23641n23651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ClKA
WiRA
MBA
ENA
AO - A35
ClKB
W/RB
MBB
ENB
BO - B35
FIFO Output Register
3023 drw 16
Figure 14. Timing for Mail1 Register and MBF1 Flag
5.12
19
IDT72363117236411723651 CMOS SyncFIFOTM
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ClKS
Vii/RS
MSS
ENS
so - S35
ClKA
WiRA
MSA
ENA
AO - A35
3023 drw 17
Figure 15. Timing for Mail2 Register and MBF2 Flag
5.12
20
IDT723631n23641n23651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
250
fdata
=1/2g
TA = 25°e
eL=OpF
Vee = 5.5 V
200
Vee =5.0V
c:(
E
I
150
'E
f!
:;
0
>-
c..
Co
:s
(1)_
100
I::"
0
-lJ
11
50
I
o
o
10
20
40
30
f 5 - Clock Frequency - MHz
50
60
70
3023 drw 18
Figure 16
CALCULATING POWER DISSIPATION
The lee(f) current for the graph in Figure 16 was taken while simultaneously reading and writing the FIFO on the IDT723641
with ClKA and ClKS set to f8. All data inputs and data outputs change state during each clock cycle to consume the highest
supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitance
load per data-output channel and the number of IDT723631 n23641n23651 inputs driven by TTL HIGH levels are known, the
power dissipation can be calculated with the equation below.
With lee(f) taken from Figure 16, the maximum power dissipation (PT) of the I DT723631 n23641 n23651 may be calculated
by:
PT =Vee x [Iee(f) + (N x Lllee x dc)) + 'L(CL X Vee 2 x fa)
where:
N
Lllee
dc
CL
fa
=
number of inputs driven by TTL levels
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4
output capacitance load
switching frequency of an output
When no reads or writes are occurring on the IDT723631n23641n23651, the power dissipated by a single clock (ClKA
or ClKS) input running at frequency f8 is calculated by:
PT =Vee x fs x 0.209 mA/MHz
5.12
21
IDT72363117236411723651 CMOS SyncFIFOTM
512 x 36,1024 X 36, 2048 X 36
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kn
From Output
Under Test
30 pF(l)
680n
3V
Timing
Input
3V
High-Level
Input
GND
1.5 V
3V
Data,
Enable
Input
GND
tw
3V
Low-Level
Input
GND
1.5 V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Output
Enable
GND
- <=3V
Low-Level
Output
1.5 V
High-Level
Output
1.5 V
VOL
VOH
Input
~.5V
-' f.-
1
-
[;tP~
tp
In-Phase
Output _ _ _- - I
3V
~;SV-
1.5 V
GND
1.5 V
_ <=OV
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
3023 drw 19
NOTE:
1. Includes probe and jig capacitance
Figure 17. Load Circuit and Voltage Waveforms
5.12
22
IDT723631n23641n23651 CMOS SyncFIFOTM
512 x 36,1024 x 36, 2048 x 36
ORDERING INFORMATION
xxxxxx
X
lOT
xx
Device Type
Power
Speed
COMMERCIAL TEMPERATURE RANGE
x
Package
x
Process/
Temperature
Range
Y
BLANK
Commercial (O°C to +70°C)
PF
Thin Quad Flat Pack
Plastic Quad Flat Pack
15
20
30
}
' - - - - - - - - - 1 PQF
'-----------------1 L
723631
' - - - - - - - - - - - - - - - - - - - - - - 1 723641
723651
5.12
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Low Power
512 x 36 Synchronous FIFO
1024 x 36 Synchronous FIFO
2048 x 36 Synchronous FIFO
3023 drw 20
23
II
(;)®
CMOS SyncBiFIFOTM
256 X 18 x 2 and 512 x 18 x 2
IDT72605
IDT72615
Integrated Device Technology. Inc.
FEATURES:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 x 2 organization (IDT 72605)
• 512 x 18 x 2 organization (lDT 72615)
• Synchronous interface for fast (20ns) read and write
cycle times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-
FUNCTIONAL BLOCK DIAGRAM
power bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFOTM is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memories. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT's high-speed,
submicron CMOS technology.
OAO-0A17
t
INPUT REGISTER
EFAB
EEBp.
EAEAB
PAFAB
FFAB ---,._ _ _. .
L...w_ _ _ _
~~
3
CLKB------~----~~~_____~------. .~
OBO-OB17
EA,EBA
EAFBA
FFBA
VCC
GNO
INPUT REGISTER
2704 drw 01
SyncBiFIFO is a trademark and the lOT logo is a registered trademark of Integrated Device Technology, Inc.
AUGUST 1993
COMMERCIAL TEMPERATURE RANGES
DSC-2045/3
©1995 Integrated Device Technology, Inc.
5.13
1
10172605/10172615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
11
DB3
DB4
DB5
DB7
GND
DB6
DB8
10
DB1
DB2
09
RS
DBO
08
RiWB ClKB
07
DEB
06
Vee
DB11
DB13 GND
GND DB10
DB12
DB14
DB9
DB15
DB16
DEA
DB17
PAEAB PAFAB
ENB
G68-1
GND BYPB
05 PAEBJI PAFBA
Pin
EFAB
FFAB
A2
Vee
Ao
A1
ENA
CSA
1 Designator
/
04
EFBA FFBA
03
DA1
DAO
•
02
DA2
DA3
GND
DA6
DA8
GND DA10
DA12
DA4
DA5
DA7
DA9
Vee
DA11
DA13 GND DA15
B
C
D
E
F
G
01
A
ClKA RiWA
H
DA14
DA16
J
K
II
DA17
l
2704 drw 02
PGA
Top View
LJLJLJLJLJLJLJLJIILJLJLJLJLJLJLJLJ
DA16
DA17
ClKA
RiWA
ENA
CSA
Ao
A1
A2
9 8 7 6 5 4 3 2 LJ 6867666564636261
::: 10
1
60::
:::11
::: 12
::: 13
::: 14
J68-1
Vee
EFAB
FFAB
PAEAB
PAFAB
OEA
DB17
DB16
47::
46::
45::
::: 26
44::
2728293031323334353637383940414243
r1r1r1r1r1r1r1r1r1r1r1r1r1r1r1r1r1
DA2
DA1
DAO
EFBA
FFBA
PAEBA
PAFBA
GND
BYPB
OEB
ENB
RiWB
ClKs
RS
DBO
DB1
DB2
~O~MN~Ooomoo~m~O~M
mzmwmwm~z~8~8~z88
O(!lODODO
(!l
(!l
2704 drw 03
PLCC
Top View
5.13
2
IDT72605I1DT72615 CMOS SyncBiFIFO
256 X 18 X 2 and 512 X 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PIN 1
-
roo-
,...-
II-
- - -
I""""
ff-
-
--
I""""
I""""
f-
f-
f-
f-
-
roo-
ff-
-
I""""
I""""
-
I""""
I""""
- f- f- - f- r- r- - r-
I-
!-
-
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DA2 I
DA3 I
I I
I I
DA4
I I
3
46
I
I
I
I
I
I
I
I
I
I
I
I
4
45
5
44
I
DA5 I
DAs I
DA7
I
DAa I
DA9 I
GND I
vee
I
DA10 I
DAn I
DA12 I
DA13 I
DA14 I
DA15 I
I
I
I
I
I
I
I
I
I
I
I
I
I1
1
48
2
47
6
43
7
42
8
41
9
40
1 I
J
10
39
I I
I DBn
11
38
I I
I DB12
I DB13
PN64-1
I
I
I
I
I
I
I
I
I
I
I
I
I
J
I
I
DB3
I
I
I
I
I
1
I
I
12
37
13
36
14
35
I I
I I
I I
15
34
I I
16
33
I I
DB4
GND
DB5
DBs
DB7
DBa
DB9
DBw
I DB14
I GND
I DB15
I DB1S
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
-
f-
f-
- r-
-
- r-
-
-- r- r- - r- - - --- -- - -- - - -f-
~
rf-
-,...-
r-
I-
f-
I-
- - - -
-
--'------~--2704 drw 04
TQFP
Top View
5.13
3
IDT72605I1DT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
DAO-DA17
Name
Data A
va
I/O
Description
Data inputs & outputs for the 18-bit Port A bus.
CSA
Chip Select A
I
Port A is accessed when CSA is lOW. Port A is inactive if CSA is HIGH.
RIWA
ReadlWrite A
I
This pin controls the rea~ or write direction of Port A. If RIWA is lOW, Data A input data is
written i~ Port A. If RIWA is HIGH, Data A output data is read from Po.!!. A. In bypass mode,
when RIWA is lOW, message is written into A~8 output register. If RIWA is HIGH, message
is read from 8~A output register.
ClKA
Clock A
I
ClKA is typically a free running clock. Data is read or written into Port A on the rising edge of
ClKA.
ENA
Enable A
I
When ENA is lOW, data can be read or written to Port A. When ENA is HIGH, no data
transfers occur.
OEA
Output Enable A
I
When RIWA is HIGH, Port A is an output bus and OEA controls the high-impedance state of
DAO-DA17. If OEA is HIGH, Port A is in a high-impedance state. If OEA is lOW while CSA is
lOW and RlWA is HIGH, Port A is in an active (low-impedance) state.
I
When CSA is asserted, Ao, Al, A2 and RIWA are used to select one of six internal resources.
Ao, Al, A2 Addresses
DBO-DB17
Data 8
RIWB
ReadlWrite 8
I
This pin controls the read or write direction of Port 8. If RIWB is lOW, Data 8 input data is
written into Port 8. If RlWB is HIGH, Data 8 output data is read from Port 8. In bypass mode,
when RlWB is lOW, message is written into 8~A output register. If RlWB is HIGH, message
is read from A~8 output register.
ClKB
Clock 8
I
Clock 8 is typically a free running clock. Data is read or written into Port 8 on the rising edge
of ClKB.
ENB
Enable 8
I
When ENB is lOW, data can be read or written to Port 8. When ENB is HIGH, no data
transfers occur.
OEB
Output Enable 8
I
When RIWB is HIGH, Port 8 is an output bus and OEB controls the high-impedance state of
DBO-DB17. If OEB is HIGH, Port 8 is in a high-impedance state. If OEB is lOW while RMiB
is HIGH, Port 8 is in an active (low-impedance) state.
EFAB
A~B
0
When EFAB is lOW, the A~B FIFO is empty and further data reads from Port 8 are inhibited.
When EFAB is HIGH, the FIFO is not empty. EFAB is synchronized to ClKB. In the bypass
mode, EFAB HIGH indicates that data DAO-DA17 is available for passing through. After the
data DBO-DB17 has been read, EFAB goes lOW.
PAEAB
A~8
0
When PAEAB is lOW, the A~8 FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into PAEAB Register. When PAEAB is HIGH, the
A~8 FIFO contains more than offset in PAEAB Register. The default offset value for PAEAB
Register is 8. PAEAB is synchronized to ClKB.
0
When PAFAB is lOW, the A~8 FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into PAFAB Register. When PAFAB is HIGH,
the A~8 FIFO contains less than or equal to the depth minus the offset in PAFAB Register.
The default offset value for PAFAB Register is 8. PAFAB is synchronized to ClKA.
Empty Flag
I/O
Programmable
Almost-Empty Flag
PAFAB
A~8
Programmable
Almost-Full Flag
Data inputs & outputs for the 18-bit Port 8 bus.
FFAB
A~8
Full Flag
0
When FFAB is lOW, the A~8 FIFO is full and further data writes into Port A are inhibited.
When FFAB is HIGH, the FIFO is not full. FFAB is synchronized to ClKA. In bypass mode,
FFAB tells Port A that a message is waiting in Port 8's output register. If FFAB is lOW, a
bypass message is in the register. If FFAB is HIGH, Port 8 has read the message and another
message can be written into Port A.
EFBA
8~A
Empty Flag
0
When EFBA is lOW, the 8~A FIFO is empty and further data reads from Port A are inhibited.
When EFBA is HIGH, the FIFO is not empty. EFBA is synchronized to ClKA. In the bypass
mode, EFBA HIGH indicates that data DBO-DB17 is available for passing through. After the
data DAO-DA17 has been read, EFBA goes lOW on the following cycle.
0
When PAEBA is lOW, the 8~A FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into PAEBA Register. When PAEBA is HIGH, the
8~A FIFO contains more than offset in PAEBA Register. The default offset value for PAEBA
Register is 8. PAEBA is synchronized to ClKA.
0
When PAFBA is lOW, the 8~A FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into PAFBA Register. When PAFBA is HIGH,
the 8~A FIFO contains less than or equal to the depth minus the offset in PAFBA Register.
The default offset value for PAFBA Register is 8. PAFBA is synchronized to ClKB.
PAEBA
8~A
Programmable
Almost-Empty Flag
PAFBA
8~A
Programmable
Almost-Full Flag
2704 tbl 01
5.13
4
I
II
IDT72605I1DT72615 CMOS SyncBiFIFO
256 X 18 X 2 and 512 X 18 X 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued)
UO
Description
FFsA
B~A
Full Flag
0
When FFsA is LOW, the B~A FIFO is full and further data writes into Port B are inhibited.
When FFsA is HIGH, the FIFO is not full. FFsA is synchronized to CLKs. In bypass mode,
FFsA tells Port B that a message is waiting in Port A's output register. If FFsA is LOW, a
bypass message is in the register. If FFsA is HIGH, Port A has read the message and another
message can be written into Port B.
BYPB
Port B Bypass
Flag
0
This flag informs Port B that the Synchronous BiFIFO is in bypass mode. When BYPs is
LOW, Port A has placed the FIFO into bypass mode. If BYPB is HIGH, the Synchronous
BiFIFO passes data into memory. BYPB is synchronized to CLKs.
Symbol
Name
RS
Reset
Vee
Power
There are three +5V power pins for the PLCC and PGA packages and two for the TQFP.
GND
Ground
There are seven ground pins for the PLCC and PGA packages and four for the TQFP.
I
A LOW on this pin will perform a reset of all Synchronous BiFIFO functions.
2704 tbl 02
RECOMMENDED DC
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Com'l.
Mil.
Unit
VTERM
Terminal Voltage
with Respect
to Ground
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
50
50
rnA
Symbol
°C
Parameter
Min. Typ. Max. Unit
VCC
Supply Voltage
4.5
5.0
5.5
GND
Supply Voltage
0
0
0
V
VIH
VIL(I)
Input High Voltage
2.0
-
-
V
Input Low Voltage
-
-
O.S
V
2704 tbl 04
NOTE:
NOTE:
V
1. 1.SV undershoots are allowed for 10ns once per cycle.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
2704 tbt 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Symbol
CIN(2)
COUT(I.2)
Max.
Unit
Input Capacitance
VIN = OV
10
pF
Output Capacitance
VOUT= OV
10
Parameter
Conditions
pF
2704 tbl 05
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
DC ELECTRICAL. CHARACTERISTICS
(Commercial: Vcc = 5V ± 10%, TA = ODC to +70DC)
Symbol
IIL(I)
lOLl;'::)
VOH
VOL
lee(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic "1" Voltage lOUT = -2mA
Output Logic "0" Voltage lOUT = SmA
Average Vee Power Supply Current
Min.
-1
-10
2.4
-
IDT72615L
IDT72605L
Commercial
tCLK = 20, 25, 35, 50ns
Typ.
-
Max.
1
10
Unit
~A
-
0.4
V
-
230
rnA
-
~
V
2704 tbl 06
NOTES:
1. Measurements with O.4V S VIN S Vee.
2. OEA, OEB ~ VIH; 0.4 S VOUT S Vee.
3. Tested with outputs open. Testing frequency f=20MHz
5.13
5
10172605110172615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
In Pulse Levels
+5V
t
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.1Kn
1.5V
D.U.T. - - -.....- - - - t
See Figure 2
680n
2704 tbl 07
30pF*
2704 drw05
or equivalent circuit
Figure 2. Output Load
* Includes jig and scope capacitances.
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V±10%, TA = O°C to +70°C)
Commercial
Symbol
Parameter
72615L20
72605L20
Min.
Max.
72615L25
72605L25
Min. Max.
72615L50
72615L35
72605L35
72605L50
Min. Max. Min.
Max. Unit
20
28
MHz
-
fClK
Clock frequency
-
50
-
40
tClK
Clock cycle time
20
25
-
35
tClKH
Clock HIGH time
8
10
14
tClKl
Clock LOW time
8
25
15
tRS
Reset pulse width
20
-
tRSS
Reset set-up time
12
-
-
tRSR
Reset recovery time
12
-
15
-
21
-
30
-
ns
3
tRSF
Reset to flags in intial state
-
27
-
28
-
35
-
50
ns
3
tA
10
14
35
21
-
Timing Figures
50
20
20
50
30
ns
4,5,6,7
ns
4,5,6,7,12,13,14,15
ns
4,5,6,7,12,13,14,15
ns
3
ns
3
Data access time
3
10
3
15
3
21
3
25
ns
5,7,8,9,10,11
tcs
Control signal set-up time(l)
6
-
6
-
8
-
10
-
ns
4,5,6,7,8,9,10,11,
12,13,14,15
tCH
Control signal hold time(l)
1
-
1
-
1
-
1
-
ns
4,5,6,7,10,11,12,
13, 14,15
tDS
Data set-up time
6
-
6
-
8
-
10
4,6,8,9,10,11
Data hold time
1
-
1
-
1
-
1
-
ns
tDH
ns
4,6
tOE
Output Enable LOW to
output data valid(2)
3
10
3
13
3
20
3
28
ns
5,7,8,9,10,11
tOll
Output Enable LOW to data
bus at LOW-Z(2)
0
-
0
-
0
-
0
-
ns
5,7,8,9,10,11
to HZ
Output Enable HIGH to data
bus at High-Z(2)
3
10
3
13
3
20
3
28
ns
5,7,10,11
-
10
-
15
10
15
12
-
21
-
30
ns
4,6,10,11
21
ns
5,7,8,9,10,11
21
-
30
15
-
30
ns
12,14
-
15
-
21
-
30
ns
13,15
-
12
-
17
-
20
-
ns
4,5,6,7,8,9,10,11
-
19
-
25
-
34
-
ns
4,7,12,13,14,15
tFF
Clock to Full Flag time
tEF
Clock to Empty Flag time
tPAE
Clock to Programmable
Almost Empty Flag time
tPAF
Clock to Programmable
Almost Full Flag time
-
12
tSKEWl
Skew between CLKA & CLKB
for Empty/Full Flags(2)
10
tSKEW2
Skew between CLKA & CLKB
for Programmable Flags(2)
17
NOTES:
1. Control signals refer to CSA, RiWA, ENA, A2, Al, Ao, RiWB, ENB.
2. Minimum values are guaranteed by design.
2704 tbl 08
5.13
6
IDT72605I1DT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
RESET
IDTs SyncBiFIFO is versatile for both multiprocessor and
peripheral applications. Data can be stored or retrieved from
two sources simultaneously.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data
buffer for each direction. Each port has its own independent
clock. Data transfers to the I/O registers are gated by the
enable signals. The transfer direction for each port is controlled independently by a read/write signal. Individual output
enable signals control whether the SyncBiFIFO is driving the
data lines of a port or whether those data lines are in a highimpedance state. The processor connected to Port A of the
BiFIFO can send or receive messages directly to the Port B
device using the 18-bit bypass path.
The SyncBiFIFO can be used in multiples of 18-bits.ln a 36to 36-bit configuration, two SyncBiFIFOs operate in parallel.
Both devices are programmed simultaneously, 18 data bits to
each device. This configuration can be extended to wider bus
widths (54- to 54-bits, 72- to 72-bits, etc.) by adding more
SyncBiFIFOs to the configuration. Figure 1 shows multiple
SyncBiFIFOs configured for multiprocessor communication.
The microprocessor or microcontroller connected to Port A
controls all operations of the SyncBiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B interfaces with a second processor. The Port B control
pins are inputs driven by the second processor.
Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state with GSA, ENA and ENB HIGH. During
reset, both internal read and write pointers are set to the first
location. A reset is required after power up before a write
operation can take place. The A~B and B~A FIFO Empty
Flags (EFAB, EFBA) and Programmable Almost Empty Flags
(PAEAB, PAEBA) will be set to LOW after tRSF. The A~B and
B~A FIFO Full Flags (FFAB, FFBA) and Programmable Almost
Full Flags (PAFAB, PAFBA) will be set to HIGH aftertRsF. After
the reset, the offsets of the Almost-Empty Flags and AlmostFull Flags for the A~B and B~A FIFO offset default to 8.
PORT A INTERFACE
The SyncBiFIFO is straightforward to use in micro-processor-based systems because each port has a standard
microprocessor control set. Port A interfaces with microprocessorthrough the three address pins (A2-Ao) and a Ghip Select
GSA pins. When GSA is asserted, A2,A 1,Ao and RiWA are used
to select one of six internal resources (Table 1).
With A2=O and A1=O, Ao determines whether data can be
read out of output register or be written into the FIFO (Ao=O),
or the data can pass through the FIFO through the bypass
path (Ao=1).
With A2=1, four programmable flags (two A~B FIFO programmable flags and two B~A FIFO programmable flags)
can be selected: the A~B FIFO Almost-Empty Flag Offset
(A1=O, Ao=O),A~B FIFOAlmost-Full Flag Offset (A1=O, Ao=1),
B~A FIFO Almost-Empty Flag Offset (A1=1, Ao=O) , B~A FIFO
Almost-Full Flag Offset (A1=1, Ao=1).
Port A is disabled when GSA is deasserted and data A is in
high-impedance state.
IDT
SYNCBIFIFO
1--.. DATA A
ClK
~
MICROPROCESSOR
A
DATAB ~
ClKA
ClKB
CONTROL A CONTROL B ~
DATA
ADDR,I/O HCONTROlllOGIC
I
RAM A
I-
-
-
.....
--~
ClK
--l CONTROL~•
IDT
SYNCBIFIFO
DATA A
DATA B ~
ClKA
ClKB lCONTROlA CONTROlB I-
--
SYSTEM
CLOCK B
SYSTEM
CLOCK A
lOGIC
-I
MICROPROCESSOR
B
DATA
ADDR,I/O
RAMB
2704 drw 06
NOTES:
1. Upper SyncBiFI FO only is used in 18- to 18-bit configuration.
2. Control A Consists of RiWA, ENA, OEA, CSA, A2, Al, Ao. Control B consists of RtWB, ENB, OEB.
Figure 1. 36- to 36-bit Processor Interface Configuration.
5.13
,
7
ID172605I1D172615 CMOS SyncBiFIFO
256 X 18 X 2 and 512 X 18 X 2
COMMERCIAL TEMPERATURE RANGE
Data A
0
R1WA
0
ENA
0
OEA
110
0
I
Data A is written on CLKA"#. This write cycle immediately following
low-impedance cycle is prohibited. Note that even though OEA 0, a
LOW logic level on RIWA, once qualified by a rising edge on CLKA. will
put Data A into a high-impedance state.
0
0
0
0
0
1
0
1
I
Data A is written on CLKA "#
1
0
X
I
Data A is ignored
0
a
Data is read(l) from RAM array to output register on CLKA "#,
Data A is low-impedance
0
1
0
1
a
Data is read(l) from RAM array to output register on CLKA"#,
Data A is high-impedance
0
1
1
1
0
1
1
a
a
Output register does not change(2), Data A is low-impedance
0
1
1
0
1
X
X
X
X
CSA
I
a
Port A Operation
=
Output register does not change(2), Data A is high-impedance
Data A is ignored(3)
Data A is high-impedance(3)
NOTES:
2704 tbl 09
1. When A2A1Ao =000, the next S-tA FIFO value is read out of the output register and the read pointer advances. If A2A1Ao =001, the bypass path is
selected and bypass data from the Port S input register is read from the Port A output register. If A2A1AoO =1XX, a flag offset register is selected
and its offset is read out through Port A output register.
2. Regardless of the condition of A2A1Ao, the data in the Port A output register does not change and the S-tA read pointer does not advance.
3. If CSA# is HIGH, then SYPs is HIGH. No bypass occur under this condition.
Table 1. Port A Operation Control Signals
BYPASS PATH
The bypass paths provide direct communication between
Port A and Port B. There are two full 18-bit bypass paths, one
in each direction. Ouring a bypass operation, data is passed
directly between the input and output registers, and the FIFO
memory is undisturbed.
Port A initiates and terminates all bypass operations. The
bypass flag, BYPs, is asserted to inform Port B that a bypass
operation is beginning. The bypass flag state is controlled by
the Port A controls, although the BYPs signal is synchronized
to ClKs. So, BYPs is asserted on the next rising edge of ClKs
when A2A1Ao=001and CSA is lOW. When Port A returns to
normal FIFO mode (A2A1Ao=OOO or CSA is HIGH), BYPs is
deasserted on the next ClKs rising edge.
Once the SyncBiFIFO is in bypass mode, all data transfers
are controlled by the standard Port A (RiWA, ClKA, ENA, OEA)
and Port B (RiWs, ClKs, ENs, OEs) interface pins. Each
bypass path can be considered as a one word deep FIFO.
Oata is held in each input register until it is read. Since the
controls of each port operate independently, Port A can be
reading bypass data at the same time Port B is reading bypass
data.
When RiWA and ENA is lOW, data on pins OAO-OA17 is
written into Port A input register. Following the rising edge of
ClKA for this write, the A~B Full Flag (FFAS) goes lOW.
Subsequent writes into Port A are blocked by internal logic
until FFAS goes HIGH again. On the next ClKB rising edge,
the A~B Empty Flag (EFAS) goes HIGH indicating to Port B
that data is available. Once RiWs is HIGH and ENs is lOW,
data is read into the Port B output register. OEs still controls
whether Port B is in a high-impedance state. When OEs is lOW,
the output register data appears at OSO-OS17. EFAS goes lOW
following the ClKs rising edge forthis read. FFAB goes HIGH
on the next ClKA rising e9ge, letting Port A know that another
word can be written through the bypass path.
Bypass data transfers from Port B to Port A work in a similar
manner with EFBA and FFBA indicating the Port A output
register state.
When the Port A address changes from bypass mode
(A2A1Ao=001) to FIFO mode (A2A1Ao=OOO) on the rising edge
of ClKA, the data held in the Port B output register may be
overwritten. Unless Port A monitors the BYPs pin and waits
for Port B to clock out the last bypass word, data from the A~B
FI Fa will overwrite data in the Port B output register. BYPs will
go HIGH on the rising edge of ClKs signifying that Port B has
finished its last bypass operation. Port B must read any
bypass data in the output register on this last ClKs clock or it
is lost and the SyncBiFIFO returns to FIFO operations. It is
especially important to monitor BYPs when ClKs is much
slower than ClKA to avoid this condition. BYPs will also go
HIGH after CSA is brought HIGH; in this manner the Port B
bypass data may also be lost.
Since the Port A processor controls CSA and the bypass
mode, this scenario can be handled for B~A bypass data. The
Port A processor must be set up to read the last bypass word
before leaving bypass mode.
5.13
8
II
IDT72605n0T72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CSA
A2
A1
Ao
Read
0
0
0
0
B~A FIFO
0
0
0
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
X
X
X
I
PROGRAMMABLE FLAGS
Write
I A~B FIFO
18-bit Bypass Path
A~B
FIFO Almost-Empty
Flag Offset
A~B
B~A
FIFO Almost-Full
Flag Offset
FIFO Almost-Empty
Flag Offset
B~A
FIFO Almost-Full
Flag Offset
Port A Disabled
2704 tbl10
Table 2. Accessing Port A Resources Using CSA, A2, A1, and AO.
PORT A CONTROL SIGNALS
The Port A control signals pins dictate the various operations shown in Table 2. Port A is accessed when CSA is lOW,
and is inactive if CSA is HIGH. R/WA and ENA lines determine
when Data A can be written or read. If RiWA and ENA are lOW,
data is written into input registeron the lOW-to-HIGH transition
of ClKA. If RiWA is HIGH and OEA is lOW, data comes out
of bus and is read from output register into three-state buffer.
Refer to pin descriptions for more information.
PAEAB Register
PAFAB Register
PAEBA Register
PAFBA Register
The lOT SyncBiFIFO haseightflags: four flags for A~B FIFO
(EFAS, PAEAs, PAFAS, FFAS), and four flags for B~A FIFO
(EFsA, PAEsA, PAFsA, FFsA). The Empty and Full flags are
fixed, while the Almost Empty and Almost Full offsets can be
set to any depth through the Flag Offset Registers (see Table
3). The flags are asserted at the depths shown in the Flag
Truth Table (Table 4). After reset, the programmable flag
offsets are set to 8. This means the Almost Empty flags are
asserted at Empty +8 words deep, and the Almost Full flags
are asserted at Full -8 words deep.
The PAEAs is synchronized to ClKs, while PAEAs is synchronized to ClKA; and PAEsA is synchronized to ClKA, while
PAEsA is synchronized to ClKs. If the minimum time (tSKEW2)
between a rising ClKs and a rising ClKA is met, the flag will
change state on the current clock; otherwise, the flag may not
change state until the next clock rising edge. For the specific
flag timings, refer to Figures 12-15.
PORT B CONTROL SIGNALS
The Port B control signal pins dictate the various operations
shown in Table 5. Port B is independent of CSA. RiWs and
ENs lines determine when Data can be written or read in Port
B. If RiWs and ENs are lOW, data is written into input register,
and on lOW-to-HIGH transition of ClKs data is written into
17
16
15
14
13
12
11
10
X
X
X
X
X
X
X
X
17
16
15
14
13
12
11
10
X
X
IX
X
X
X
X
X
17
16
15
14
13
12
11
10
X
X
X
X
X
X
X
X
17
16
15
14
13
12
11
10
X
X
X
X
X
X
X
X
0
9
X
8
5
4
2
7
6
3
A-tB FIFO Almost-Empty Flag Offset
9
X
8
7
9
X
8
5
2
7
6
4
3
B-tA FIFO Almost-Empty Flag Offset
0
9
X
8
7
0
6
A~B
2
5
4
3
FIFO Almost-Full Flag Offset
6
5
4
3
2
0
B-tA FIFO Almost-Full Flag Offset
2704 tbl11
NOTE:
1. Sit 8 must be set to 0 for the 1DT72605 (256 x 18) Synchronous SiFIFO.
Table 3. Flag Offset Register Format.
Number of Words
in FIFO
From
To
0
0
1
n
n+1
O-m
0
0-(m+1)
0-1
0
EF
LOW
PAE
LOW
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
NOTES:
n = Programmable Empty Offset (PAEAB Register or PAEBA Register)
m = Programmable Full Offset (PAFAB Register or PAFBA Register)
D = FIFO Depth (lDT72605 = 256 words, IDT72615= 512 words)
PAF
FF
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
2704 tbl12
Table 4. Internal Flag Truth Table.
5.13
9
IDT72605I1DT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
input register and the FIFO memory. If RIWB is HIGH and OEB
is LOW, data comes out of bus and is read from output register
into three-state buffer. In bypass mode, if RIWB is LOW,
bypass messages are transferred into B--"7A output register. If
RIWA is HIGH, bypass messages are transferred into A--"7B
output register. Refer to pin descriptions for more information.
Data B
RfiiJe
ENB
OEB
VO
0
0
0
I
Port B Operation
Data B is written on elKB i. This write cycle immediately following output lowimpedance cycle is prohibited. Note that even though OEs 0, a lOW logic level on
RNVB, once qualified by a rising edge on elKs. will put Data B into a high-impedance
state.
=
i.
0
0
Data B is written on elKB
1
1
X
I
0
I
Data B is ignored
1
0
0
0
Data is read(l) from RAM array to output register on elKB:t, Data B is lOW
impedance
1
0
1
0
Data is read(l) from RAM array to output register on elKB:t, Data B is HIGH
impedance
1
1
1
1
0
0
Output register does not change(2), Data B is low-impedance
1
0
Output register does not change(2), Data B is high-impedance
NOTES:
2704 tbl13
1. When A2A1Ao = 000 or 1XX, the next A~8 FIFO value is read out of the output register and the read pOinter advances. If A2A1Ao = 001, the bypass
path is selected and bypass data is read from the Port B output register.
2. Regardless of the condition of A2A1Ao, the data in the Port B output register does not change and the A~B read pointer does not advance.
Table 5. Port B Operation Control Signals.
5.13
10
II
IDT72605I1DT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
~--------------tRS--------------~
~---------------tRSF------------~--~
EFAB.
PAEAS.--~~~~--~~~~--~~~~--~~--~~&-~
EFBA.~~~
__~~~~__~~~~__~~~~~~~+-~~~___________________________________
PAEBA
EFAB.
PAEAS.~r-~--~~--~~r-~~r-~--~~--~~~~~r-----------------------------------
EFBA' __~~~-L_ _~~~-L_ _~~~~_ _L-~_ _~~~-r
PAEBA
::77zzd
tRss--------~~--------tRSR--------~~~~________________
Figure 3. Reset Timing
2704 drw 07
~-------------tCLK ------------~
'-----tCLKH -----t-------tCLKL
ClKA
AO,A1,A2,
L-~~~~~~~L-~~~~
tcs -----.J!-.-i
DAO-DA17
NO READ
OPERATION
ClKs
2704 drw 08
Figure 4. Port A
(A~B)
5.13
Write Timing
11
10172605110172615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
AO,A1,A2,
~......:lIo~~~
DAO-DA17
-----------1-------«:
toLZ
ClKs
II
NO WRITE
2704 drw09
Figure 5. Port A
~------tc
(B~A)
Read Timing
K-------..j
~--tcLKH---..j~--
ClKs
RlWs
ENs
Dso-Ds17
NO READ
OPERATION
ClKA
2704 drw 10
Figure 6. Port B (B~A) Write Timing
5.13
12
IDT72605n0T72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
ClKs
R/ws
ENs
Dso-DB17
----------+-----i(
tOLZ
OEs
ClKA
NO WRITE
OPERATION
2704 drw 11
Figure 7. Port B (A-7B) Read Timing
5.13
13
IDT72605I1DT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
AO,A1,A2,
OAO-OA17
ClKB
RIWB
II
ENB
OBO-OB17
t~
tA1<
___ Fto~l~'----oo- __
01 -
DEB
~
2704 drw 12
NOTE:
1. When tSKEW1 ;::: minimum specification, tFRL(Max.) tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing applies only at the Empty Boundary (EF LOW).
=
=
=
Figure 8. A-7B First Data Word Latency after Reset for Simultaneous Read and Write
5.13
14
IDT72605nDT72615 CMOS SyncBIFIFO
256 x 18 x2and 512 x 18 x2
COMMERCIAL TEMPERATURE RANGE
CLKB
R/WB
ENB
DBO-DB17
CLKA
AO,A1,A2,
~~~'-~~~~'-~~wr~~~~v
CSA
,Et-+..
tA
~..----IA:-j:_
~XXXXXX
DAO-DA17
___
OEA
~IOLZ.j'
IO~ j
~O_O
_--'*
01
'}..
2704 drw 13
NOTE:
1. When tSKEW1 ~ minimum specification, tFRL(Max.) tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) 2tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (s= LOW).
=
=
Figure 9.
B~A
=
First Data Word Latency after Reset for Simultaneous Read and Write
5.13
15
10T72605110T72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
Ao,A1,A2,
A2, A1 ,Ao, = 001
FIFO FLAG
OAO-OA17
ClKs
II
RNJs
ENs
BYPASS FLAG
OSO-OS17
DEB
---------------------11
~
DATA OUTPUT
_____________________________________________
FIFO FLAG
)i
~_tO_H_Z--~---------2704 drw 14
NOTES:
1. When CSA is brought HIGH, A~B Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition.
2. After the bypass operation is completed, the BYPs goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for
the next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 10.
A~B
Bypass Timing
5.13
16
I0T72605n0T72615 CMOS SyncBiFIFO
256 X 18 X 2 and 512 X 18 X 2
COMMERCIAL TEMPERATURE RANGE
ClKs
RlWs
ENs
DBO-DB17
ClKA
A2,Al,Ao,= 001
Ao,Al,A2,
RIWA
EFBA
--------1-------------------------;-~-'--'
FIFO FLAG
BYPASS FLAG
---------------+~----------------------'
DATA OUTPUT
DAD-DA17
>t-
~----------------------------------------~
2704 drw 15
NOTES:
1. When CSA is brought HIGH, A--7B Bypass mode will switch to FIFO mode on the following CLKA going LOW-to-HIGH.
2. ,After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for
the next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 11. B--7A Bypass Timing
5.13
17
IDT72605I1DT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
ClKA
tCLKH
ICLKL
~Sl\
ENA
(RiWA= 0)
PAEAS
COMMERCIAL TEMPERATURE RANGE
fit
WRITE
n+ 1 words
.
In
FIFO
I
n words in FIFO
ClKs
READ
2704 drw 16
NOTES:
1. tSKEW2 the minimum time between a rising ClKA edge and a rising ClKB edge for PAEAB to change during that clock cycle. If the time between the
rising edge of ClKA and the rising edge of ClKB is less than tSKEW, then PAEAB may not go HIGH until the next ClKB rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes lOW.
Figure 12.
A~B
Programmable Almost-Empty Flag Timing
11
ClKA
WRITE
Full - (m+ 1) words in FIFO
NOTES:
1. tSKEW2 is the minimum time between a rising ClKB edge and a rising ClKA edge for PAFAB to change during that clock cycle. If the time between the
rising edge of ClKB and the rising edge of ClKA is less than tSKEW2, then PAFAB may not go HIGH until the next ClKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full- (m + 1) words in the FIFO when PAF goes lOW.
Figure 13.
A~B
Programmable Almost-Full Flag Timing
5.13
18
10T72605110T72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
elK.
tCSI\
(itCH
ENB
(Rm A= 0)
WRITE
n words in
~IFO
n+ 1 words in FIFO
CLKA
ENA
2704 drw 18
(RmA= 1)
READ
NOTES:
1. tSKEW2 is the minimum time between a rising ClKs edge and a rising ClKA edge for PAEBA to change during that clock cycle. If the time between the
rising edge of ClKs and the rising edge of ClKA is less than tSKEW2, then PAEsA may not go HIGH until the next ClKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes lOW.
Figure 14. B~A Programmable Almost-Empty Flag Timing
CLKB
ENB
(RIWA= 0)
PAFsA
Full- (m+1) words in FIFO
CLKA
tPAF
.
~
tSKEW2{l)
SI\
(it~
ENA
(RiWA= 1)
READ
2704 drw 19
NOTES:
1. tSKEW2 is the minimum time between a rising ClKs edge and a rising ClKA edge for PAFsA to change during that clock cycle. If the time between the
rising edge of ClKs and the rising edge of ClKA is less than tSKEW2, then PAFsA may not go HIGH until the next ClKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes lOW.
Figure 15.
B~A
Programmable Almost-Full Flag Timing
5.13
19
I0T72605n0T72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
XXXXX
Device Type
_X_
Power
ASpeed
_X_ _
Package
x
Process/
Temperature
Range
~BLANK
Commercial (O°C to +70°C)
68-pin PGA
68-pin PLCC
64-pinTQFP
~
20
________________~ 25
35
}
Clock Cycle Time (I ClK) in ns
50
~--------------------~II
L
'----------------------------------1 72605
72615
Low Power
256 x 18 Parallel Synchronous Bidirectional FIFO
512 x 18 Parallel Synchronous Bidirectional FIFO
2704 drw20
5.13
20
II
G®
IDT723612
BiCMOS SyncBiFIFOTM
64 x 36 x 2
Integrated Device Technology, Inc.
• Parity generation can be selected for each port
• low-power advanced SiCMOS technology
Supports clock frequencies up to 67 MHz
• Fast access times of 10ns
• Available in 132-pin plastic quad flat package (POF) or
space-saving 120-pin thin quad flat package (TOFP)
FEATURES:
• Free-running ClKA and ClKS can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage
capacity each) buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
Microprocessor interface control logic
• EFA, FFA, AEA, and AFA flags synchronized by ClKA
• EFS, FFS, AES, and AFS flags synchronized by ClKS
• Passive parity checking on each port
DESCRIPTION:
The IDT723612 is a monolithic high-speed, low-power
SiC MaS bi-directional clocked FIFO memory. It supports
clock frequencies up to 67 MHz and has read access times as
fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs
FUNCTIONAL BLOCK DIAGRAM
CLKACSAW/RAENAMBA-
Port-A
Control
Logic
MBF1
I
0001
EVEN
I
I
I
I
Device
Control
+
-
-
r---
~~
Eg
-
a:
I
-
-
f$~
36,. ...
PGA
4J
I.-
52
-
Parity
Gen/Check
I
I
I
-
-
-
I
r----c:
-
~~
Pointer
64 x 36
SRAM
-
rI
-
Mail 2
Register
r---
-
-
I
36
...
s~~
~~.~
a:
11-~
-
1
I
~~
....,.
-
I
I
I
~.6, f- .~ ~ I-
o~
I
.
Pointer
r-
'----
Status Flag
Logic
I
~
-
.~
Programmable Flag
Offset Register
IFIF02
I
I
I
I
I
I
-
36
I
a:
Vee)
10K
Output Clamp Current, (Vo < 0 or Vo > Vee)
lOUT
Continuous Output Current, (Vo
lee
Continuous Current Through Vee or GND
TA
Operating Free Air Temperature Range
TSTG
Storage Temperature Range
= 0 to Vee)
±50
rnA
±500
o to 70
mA
DC
-65 to 150
DC
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min.
Parameter
Max. Unit
VCC
Supply Voltage
4.5
5.5
V
VIH
HIGH Level Input Voltage
2
-
V
VIL
LOW-Level Input Voltage
0.8
V
IOH
HIGH-Level Output Current
-
-4
mA
8
0
70
mA
DC
IOL
LOW-Level Output Current
TA
Operating Free-air
Temperature
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions
VOL
=4.5V,
Vee =4.5 V,
=-4 mA
10L =8 mA
III
Vee = 5.5 V,
VI = Vee or 0
ILO
Vee = 5.5 V,
Vo
VOH
Vee
Min.
=5.5 V,
VI = Vee or GND
Unit
V
=Vee or 0
10 =0 mA,
Max.
2.4
10H
lee
Vee
Typ.(1)
0.5
V
±50
~A
±50
~A
Outputs HIGH
60
mA
Outputs LOW
130
mA
60
mA
Outputs Disabled
CIN
VI=O,
f = 1 MHz
4
pF
COUT
Vo=O,
f = 1 MHZ
8
pF
Note:
1. All typical values are at Vee
= 5 V, TA = 25DC.
5.14
6
II
IDT723612 BiCMOS SyncBiFIFOTM
64x36x2
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE
Symbol
IDT723612L15 IDT723612L20 IDT723612L30
Min.
Max.
Min.
Min.
Max.
Max.
Parameter
Unit
fs
Clock Frequency, ClKA or ClKB
-
66.7
-
50
-
33.4
MHz
tCLK
Clock Cycle Time, CLKA or ClKB
15
tCLKL
Pulse Duration, CLKA and ClKB lOW
6
tDS
Setup Time, AO-A35 before CLKAi and BO-B35
before CLKBi
4
5
6
-
ns
6
-
30
Pulse Duration, CLKA and ClKB HIGH
-
20
tCLKH
tENS1
Setup Time, CSA, WiRA before ClKAi; CSB,
WiRB before ClKBi
6
-
6
-
7
-
ns
tENS2
Setup Time, ENA, before CLKAi; ENB before
ClKBi
4
-
5
-
6
-
ns
tENS3
Setup Time, MBA before CLKAi: MBB before
CLKBi
4
-
5
-
6
-
ns
tPGS
Setup Time, ODD/EVEN and PGA before
ClKAi; ODD/EVEN and PGB before CLKBi(l)
4
-
5
-
6
-
ns
tRSTS
Setup Time, RST lOW before ClKAi
orCLKBi(2)
5
-
6
-
7
-
ns
tFSS
Setup Time, FSO/FS1 before RST HIGH
5
2.5
2.5
-
ns
2.5
-
7
Hold Time, AO-A35 after CLKA i and BO-B35
after CLKBi
-
6'
tDH
tENH1
Hold Time, CSA W/RA after CLKAi; CSB,
WiRB after CLKBi
2
-
2
-
2
-
ns
tENH2
Hold Time, ENA, after ClKAi; ENB after CLKBi
2.5
-
2.5
1
1
tPGH
Hold Time, ODD/EVEN and PGA after CLKAi;
ODD/EVEN and PGB after CLKBi(l)
1
-
1
-
1
-
ns
Hold Time, MBA after ClKAi; MBB after CLKBi
-
2.5
tENH3
tRSTH
Hold Time, RST lOW after ClKA i or ClKBi(2)
5
6
ns
tFSH
Hold Time, FSO and FS1 after RST HIGH
4
tSKEW1(3) Skew Time, between CLKAi and CLKBi
for EFA, EFB, FFA, and FFB
1SKEW2(3) Skew Time, between CLKAi and CLKBi
For AEA, AEB, AFA, and AFB
ns
8
8
12
12
1
4
-
4
8
-
8
-
10
-
9
-
16
-
20
-
7
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Only applies for a clock edge that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
5.14
7
IDT723612 BiCMOS SyncBiFIFOTM
64 x36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL =30pF
Symbol
IDT723612L15 IDT723612L20 IDT723612L30
Min.
Max.
Min.
Max.
Min.
Max.
Parameter
Unit
tA
Access Time, ClKA i to AO-A35 and ClKBi
to BO-B35
2
10
2
12
2
15
ns
tWFF
Propagation Delay Time, ClKA ito FFA and
ClKBi to FFB
2
10
2
12
2
15
ns
tREF
Propagation Delay Time, ClKA ito EFA and
and ClKBi to EFB
2
10
2
12
2
15
ns
tPAE
Propagation Delay Time, ClKAito AEA and
ClKBito AEB
2
10
2
12
2
15
ns
tPAF
Propagation Delay Time, ClKAito AFA and
ClKBito AFB
2
10
2
12
2
15
ns
tPMF
Propagation Delay Time, ClKA i to MBF1 lOW
or MBF2 HIGH and ClKBi to MBF2 lOW or
MBF1 HIGH
1
9
1
12
1
15
ns
tPMR
Propagation Delay Time, ClKAito BO-B35(1)
and ClKBi to AO-A35(2)
3
11
3
13
3
15
ns
tMOV
Propagation Delay Time, MBA to AO-A35 valid
and MBB to BO-B35 valid
1
11
1
11.5
1
12
ns
tpOPE
Propagation Delay Time, AO-A35 valid to PEFA
valid; BO-B35 valid to PEFB valid
3
10
3
11
3
13
ns
tpOPE
Propagation Delay Time, ODD/EVEN to PEFA
and PEFB
3
11
3
12
3
14
ns
tpoPS(3)
Propagation Delay Time, ODD/EVEN to parity
bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
2
11
2
12
2
14
ns
tPEPE
Propagation Delay Time, WIRA, CSA, ENA, MBA or
PGA to PEFA; W/RB, CSB, ENB. MBB, PGB to PEFB
1
11
1
12
1
14
ns
tpEPS(3)
Propagation Delay Time, W/RA, CSA, ENA, MBA or
PGA to parity bits (A8, A17, A26, A35); wIPB, CSB,
ENB. MBB or PGB to parity bits (B8, B17, B26, B35
3
12
3
13
3
14
ns
tRSF
Propagation Delay Time, RST to (AEA, AEB)
lOW and (AFA, AFB, MBF1, MBF2) HIGH
1
15
1
20
1
30
ns
tEN
Enable Time, CSA and W/RA lOW to AO-A35
active and CSB lOW and WiRB HIGH to
BO-B35 active
2
10
2
12
2
14
ns
tOIS
Disable Time, CSA or WiRA HIGH to AO-A35
at high impedance and CSB HIGH or WiRB
lOW to BO-B35 at high impedance
1
8
1
9
1
11
ns
Notes:
1. Writing data to the mail1 register when the BO-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the AO-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
5.14
8
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
RESET
The IDT723612 is reset by taking the reset (RSn input
LOW for at least four port-A clock (eLKA) and four port-B clock
(eLKB) LOW-to-HIGH transitions. The reset input can switch
asyncbronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (FFA, FFB) LOW, the empty flags (EFA, EFB) LOW,
the almost-empty flags (AEA, AEB) LOW and the almost-full
flags (AFAr AFB) HIGH. A reset also forces the mailbox flags
(MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two
LOW-to-HIGH transitions of eLKA and FFB is set HIGH after
two LOW-to-HIGH transitions of eLKB. The device must be
reset after power up before data is written to its memory.
FS1
FSO
RST
H
H
H
L
L
H
L
L
i
i
i
i
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER eX)
16
12
8
4
Table 1. Flag Programming
A LOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty registers (X) with the values
selected by the flag-select (FSO, FS1) inputs. The values that
can be loaded into the registers are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of port-A data AO-A35 outputs is controlled by
the port-A chip select (CSA) and the port-A write/read select
(WiRA). The AO-A35 outputs are in the high-impedance state
when either eSA or WiRA is HIGH. The AO-A35 outputs are
active when both eSA and W/RA are LOW.
Data is loaded into FIF01 from the AO-A35 inputs on a
LOW-to-HIGH transition·of eLKA when eSA is LOW, WiRA is
HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is
read from FIF02 to the AO-A35 outputs by a LOW-to-HIGH
transition of eLKA when eSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA is HIGH (see Table 2).
The port-B control signals are identical to those of port A.
The state of the port-B data (BO-B35) outputs is controlled by
the port-B chip select (eSB) and the port-B write/read select
(W/RB). The BO-B35 outputs are in the high-impedance state
when either eSB or W/RB is HIGH. The BO-B35 outputs are
active when both eSB and W/RB are LOW.
Data is loaded into FIF02 from the BO-B35 inputs on a
LOW-to-HIGH transition of eLKB when eSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and FFB is HIGH. Data is
read from FIF01 to the BO-B35 outputs by a LOW-to-HIGH
CSA
W/RA
ENA
MBA
ClKA
AO-A35 Outputs
H
X
X
L
X
X
None
H
X
X
In High-Impedance State
L
In High-Impedance State
None
Port Functions
L
H
H
L
FIF01 Write
H
H
H
i
i
In High-Impedance State
L
In High-Impedance State
Mail1 Write
L
L
L
L
X
Active, FIF02 Output Register
None
L
L
H
L
i
Active, FIF02 Output Register
FIF02 Read
L
L
L
H
X
Active, Mail2 Register
None
L
L
H
H
i
Active, Mail2 Register
Mail2 Read (Set MBF2 HIGH)
Table 2. Port-A Enable Function Table
eSB
W/RB
ENB
MBB
ClKB
BO-B35 Outputs
Port Functions
H
X
X
L
X
X
None
H
X
X
In High-Impedance State
L
In High-Impedance State
None
L
H
H
L
In High-Impedance State
FIF02 Write
L
H
H
H
i
i
In High-Impedance State
Mail2 Write
L
L
L
L
X
Active, FIF01 Output Register
None
L
L
H
L
i
Active, FIF01 Output Register
FIF01 read
L
L
L
H
X
Active, Mail1 Register
None
L
L
H
H
i
Active, Mail1 Register
Mail1 Read (Set MBF1 HIGH)
Table 3. Port-B Enable Function Table
5.14
9
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
transition of ClKB when CSB is lOW, WiRB is lOW, ENB is
HIGH, MBB is lOW, and EFB is HIGH (see Table 3).
The setup and hold time constraints to the port clocks for
!be par:!..chip selects (CSA, CSB) and write/read selects (WI
RA, W/RB) are only for enabling write and read operations and
are not related to high-impedance control of the data outputs.
If a port enable is LOW during a clock cycle, the port chip select
and write/read select may change states during the setup and
hold time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two
flip-flop stages. This is done to improve flag reliability by
reducing the probability of metastable events on the output
when ClKA and ClKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized by CLKA.
EFB, AEB, FFB, and AFB are synchronized to ClKB. Tables
4 and 5 show the relationship of each port flag to FIF01 and
FIF02.
EMPTY FLAGS (EFA, EFB)
The empty flag of a FI FO is synchronized to the port clock
that reads data from its array. When the empty flag is HIGH,
new data can be read to the FIFO output register. When the
empty flag is lOW, the FIFO is empty and attempted FIFO
reads are ignored.
The read pointer of a FIFO is incremented each time a
new word is clocked to the output register. The state machine
that controls an empty flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is empty, empty+ 1, or empty+2. A word written to a
FIFO can be read to the FIFO output register in a minimum of
three cycles of the empty flag synchronizing clock. Therefore,
an empty flag is LOW if a word in memory is the next data to
be sent to the FIFO output register and two cycles of the port
clock that reads data from the FI FO have not elapsed since the
time the word was written. The empty flag of the FI FO is set
HIGH by the second LOW-to-HIGH transition of the synchronizing clock, and the new data word can be read to the FIFO
output register in the following cycle.
Number of Words
Synchronized
Synchronized
to CLKB
to CLKA
A lOW-to-HIGH transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the
clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent clock cycle can be the first synchronization cycle.
FULL FLAG (FFA, FFS)
The full flag of a FIFO is synchronized to the port clock
that writes data to its array. When the full flag is HIGH, a
memory location is free in the SRAM to receive new data. No
memory locations are free when the full flag is lOW and
attempted writes to the FIFO are ignored.
Each time a word is written to a FI FO, the write pointer is
incremented. The state machine that controls a full flag
monitors a write-pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous
memory location is ready to be written in a minimum of three
cycles of the full flag synchronizing clock. Therefore, a full flag
is LOW if less than two cycles of the full flag synchronizing
clock have elapsed since the next memory write location has
been read. The second lOW-to-HIGH transition on the full
flag synchronization clock after the read sets the full flag HIGH
and the data can be written in the following clock cycle.
A lOW-to-HIGH transition on a full flag synchronizing
clock begins the first synchronization cycle of a read if the
clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle.
ALMOST EMPTY FLAGS (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array. The state machine
that controls an almost-empty flag monitors a write-pointer
comparator that indicates when the FIFO SRAM status is
almost empty, almost empty+1, or almost empty+2. The
almost-empty state is defined by the value of the almost-full
and almost-empty offset register (X). This register is loaded
with one of four preset values during a device reset (see Reset
above). An almost-empty flag is lOW when the FI FO contains
Synchronized
Number of Words
to CLKB
Synchronized
to CLKA
in the FIF01(1)
EFB
AEB
AFA
FFA
in the FIFO(1)
EFA
AEA
AFB
0
L
L
H
H
0
L
L
H
H
H
L
H
H
H
H
H
H
FFB
1 to X
H
L
H
H
1 to X
(X+ 1) to [64-(X+ 1)]
H
H
H
H
(X+ 1) to [64-(X+ 1)]
(64-X) to 63
H
H
L
H
(64-X) to 63
H
H
L
H
64
H
H
L
L
64
H
H
L
l
Table 5. FIF02 Flag Operation
Table 4. FIF01 Flag Operation
Note:
1. X is the value in the almost-empty flag and almost-full flag offset register.
5.14
10
EI
IDT723612 BiCMOS SyncBiFIFOTM
64 x36 x 2
COMMERCIAL TEMPERATURE RANGE
X or less words in memory and is HIGH when the FIFO
contains (X+ 1) or more words.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clocks are required after a FIFO write for the
almost-empty flag to reflect the new level of fill. Therefore, the
almost-empty flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the write that filled the memory to the (X+ 1)
level. An almost-empty flag is set HIGH by the second LOWto-HIGH transition of the synchronizing clock after the FIFO
write that fills memory to the (X+ 1) level. A LOW-to-HIGH
transition of an almost-empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figure 6 and 7).
ALMOST FULL FLAGS (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almostempty offset register (X). This register is loaded with one of
four preset values during a device reset (see Reset above).
An almost-full flag is LOW when the FIFO contains (64-X) or
more words in memory and is HIGH when the FIFO contains
[64-(X+ 1)] or less words.
Two LOW-to-HIGH transitions of the almost-full flag
synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing [64-(X+ 1)]or less words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the read that reduced the number of words in
memory to [64-(X+ 1)]. An almost-full flag is set HIGH by the
second LOW-to-HIGH transition of the synchronizing clock
after the FIFO read that reduces the number of words in
memory to [64-(X+ 1)], A second LOW-to-HIGH transition of
an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs attime tSKEW2 or greater after the
read that reduces the number of words in memory to [64(X+ 1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 13 and 14).
MAILBOX REGISTERS
Each FI Fa has a 36-bit bypass registerto pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on GLKA writes
AO-A35 data to the mail1 register when a port-A write is
selected by GSA, W/RA, and ENA and MBA HIGH. A LOWto-HIGH transition on GLKB writes BO-B35 data to the mail2
register when a port-B write is selected by GSB, WiRB, and
ENB and MBB is HIGH. Writing data to a mail register sets the
corresponding flag (MBF1 or MBF2) LOW. Attempted writes
to a mail register are ignored while the mail flag is LOW.
When a port's data outputs are active, the data on the bus
comes from the FIFO output register when the port mailboxselect input (MBA, MBB) is LOW and from the mail register
when the port mailbox-select input is HIGH. The mail1 register
flag (MBF1) is set HIGH by a LOW-to-HIGH transition on
GLKB when a port-B read is selected by GSB, WiRB, and ENB
and MBB is HIGH. The mail2 register flag (MBF2) is set HIGH
by a LOW-to-HIGH transition on GLKA when port-A read is
selected by GSA, W/RA, and ENA and MBA is HIGH. The data
in a mail register remains intact after it is read and changes
only when new data is written to the register.
PARITY CHECKING
The port-A inputs (AO-A35) and port-B inputs (BO-B35)
each have four parity trees to check the parity of incoming (or
outgoing) data. A parity failure on one or more bytes of the
input bus is reported by a LOW level on the port parity error flag
(PEFA, PEFB). Odd or even parity checking can be selected,
and the parity error flags can be ignored if this feature is not
desired.
Parity status is checked on each input bus according to
the level of the odd/even parity (ODD/EVEN) select input. A
parity error on one or more bytes of a port is reported by a LOW
level on the corresponding port parity error flag (PEFA, PEFB)
output. Port-A bytes are arranged as AO-A8, A9-A17, A18A26, and A27 -A35 with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as BO-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. When odd/even parity is
selected, a port parity error flag (PEFA, PEFB) is LOW if any
byte on the port has an odd/even number of LOW levels
applied to the bits.
The four parity trees used to check the AO-A35 inputs are
shared by the mail2 register when parity generation is selected for port-A reads (PGA = HIGH). When a port-A read
from the mail2 register with parity generation is selected with
W/RA LOW, GSA LOW, ENA HIGH, MBA HIGH, and PGA
HIGH, the port-A parity error flag (PEFA) is held HIGH regardless of the levels applied to the AO-A35 inputs. Likewise, the
parity trees used to check the BO-B35 inputs are shared by the
mail1 register when parity generation is selected for port-B
reads (PGB = HIGH). When a port-B read from the mail1
register with parity generation is selected with wiRB LOW,
GSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH, the portB parity error flag (PEFB) is held HIGH regardless of the levels
applied to the BO-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A parity generate select (PGA)
or port-B parity generate select (PGB) enables the IDT723612
to generate parity bits for port reads from a FIFO or mailbox
register. Port-A bytes are arranged as AO-A8, A9-A 17, A 1826, and A27 -A35, with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as BO-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all thirty-six inputs regardless of the state of the parity generate select (PGA, PGB)
5.14
11
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate
a parity bit according to the level on the ODD/EVEN select.
The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the
word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port-A parity generate select (PGA)
and odd/even parity select (ODD/EVEN) have setup and hold
time constraints to the port-A clock (ClKA) and the port-B
parity generate select (PGB) and ODD/EVEN have setup and
hold-time constraints to the port-B clock (ClKB). These
COMMERCIAL TEMPERATURE RANGE
timing constraints only apply for a rising clock edge used to
read a new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port-B bus (BO-B35) to check parity and the
circuit used to generate parity for the mail2 data is shared by
the port-A bus (AO-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in
a mail register when the port write/read select (WiRA, W/RB)
input is lOW, the port mail select (MBA, MBB) input is HIGH,
chip select (CSA, CSB) is lOW, enable (ENA, ENB) is HIGH,
and port parity generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents
of the register.
II
5.14
12
IDT723612 BICMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
CLKS
FS1,FSO
MBF1,
MSF2
tPAF77;!z
3012 drw04
Figure 1. Device Reset Loading the X Register with the Value of Eight
5.14
13
10T723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
WiRA
MBA
ENA
AO - A35
0001
EVEN
3012 drw 05
Note:
1. Written to FIF01
Figure 2. Port-A Write Cycle Timing for FIF01
5.14
14
II
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
elK8
W/R8
M88
EN8
80·835
0001
EVEN
3012 drw 06
Note:
1. Written to FIF02
Figure 3. Port-B Write Cycle Timing for FIF02
5.14
15
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKB
EFB
HIGH
WiRB
MBB
ENB
BO - B35
PGB,
0001
EVEN
3012 drw07
Note:
1. Read from FIF01
Figure 4. Port-B Read Cycle Timing for FIF01
ClKA
EFA
HIGH
WiRA
MBA
ENA
AO - A35
PGA,
0001
EVEN
3012 drw08
Note:
1. Read from FIF02
Figure 5. Port-A Read Cycle Timing for FIF02
5.14
16
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
CSA
WRA
MBA
ENA
AO - A3S
ClKB
EFB
CSB
W/RB
MBB
FIF01 Empty
__
lO~W~
________________________________4-__________________________
~l~O~W~
~l~O~W~
________________________________4-__________________________
________________________________4-___________________________
ENB
3012 drw 09
Note:
1. tSKEW1 is the minimum time between a rising ClKA edge and a rising ClKB edge for EFB to transition HIGH in the
next ClKB cycle .. If the time between the rising ClKA edge and rising ClKB edge is less than tSKEW1, then the
transition of EFB HIGH may occur one ClKB cycle later than shown.
Figure 6. EFB Flag Timing and First Data Read when FIF01 is Empty
5.14
17
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKS
CSS
WRS
MSS
ENS
so - S35
ClKA
FIF02 Empty
EFA
CSA
lOW
WiRA
lOW
MSA
lOW
II
ENA
AO-A35
3012drw 10
Note:
1. tSKEW1 is the minimum time between a rising ClKS edge and a rising ClKA edge for EFA to transition HIGH in the
next ClKA cycle. If the time between the rising ClKS edge and rising ClKA edge is less than tSKEW1, then the
transition of EFA HIGH may occur one ClKA cycle later than shown.
Figure 7. EFA Flag Timing and First Data Read when FIF02 is Empty
5.14
18
10T723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKB
CSB
lOW
W/RB
lOW
MBB
lOW
ENB
EFB
BO - B35
Next Word From FIF01
ClKA
WRA
MBA
ENA
AO - A35
To FIF01
3012 drw 11
Note:
1. tSKEW1 is the minimum time between a rising ClKB edge and a rising ClKA edge for FFA to transition HIGH in the
next ClKA cycle. If the time between the rising ClKB edge and rising ClKA edge is less than tSKEW1, then FFA may
transition HIGH one ClKA cycle later than shown.
Figure 8. FFA Flag Timing and First Available Write when FIF01 is Full.
5.14
19
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
CSA
lOW
WiRA
lOW
MBA
lOW
ENA
EFA
AO - A35
Next Word From FIF02
ClKB
FFB
CSB
lOW
WRB
HIGH
MBB
ENB
BO - B35
3012 drw 12
Note:
1. tSKEW1 is the minimum time between a rising ClKA edge and a rising ClKB edge for FFB to transition HIGH in the
next ClKB cycle. If the time between the rising ClKA edge and rising ClKB edge is less than tSKEW1, then FFB may
transition HIGH one ClKB cycle later than shown.
Figure 9. FFB Flag Timing and First Available Write when FIF02 is Full
5.14
20
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
ENA
ClKS
ENS
3012 drw 13
Notes:
1. tSKEW2 is the minimum time between a rising ClKA edge and a rising ClKB edge for AEB to transition HIGH in the
next ClKB cycle. If the time between the rising ClKA edge and rising ClKB edge is less than tSKEW2, then AEB may
transition HIGH one ClKB cycle later than shown.
2. FIF01 Write (CSA = lOW, W/RA = HIGH, MBA = lOW), FIF01 read (CSB = lOW, W/RB = lOW, MBB = lOW).
Figure 10. Timing for AEB when FIF01 is Almost Empty
ClKS
ENS
ClKA
X Words in FIF02
(X+1) Words in FIF02
tENS2C\
rrtENH2
ENA
3012 drw 14
Notes:
1. tSKEW2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AEA to transition HIGH in the
next ClKA cycle. If the time between the rising ClKB edge and rising ClKA edge is less than tSKEW2, then AEA may
transition HIGH one ClKA cycle later than shown.
2. FIF02 Write (CSB = lOW, W/RB = HIGH, MBS = lOW), FIF02 read (CSA = lOW, W/RA = lOW, MBA = lOW).
Figure 11. Timing for AEA when FIF02 is Almost Empty
5.14
21
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
ENA
(64-X) Words in FIF01
ClKS
ENS
3012 drw 15
Notes:
1. tSKEW2 is the minimum time between a rising ClKA edge and a rising ClKS edge for AFA to transition HIGH in the
next ClKA cycle. If the time between the rising ClKA edge and rising ClKB edge is less than tSKEW2, then AFA may
transition HIGH one ClKB cycle later than shown.
2. FIF01 Write (CSA = lOW, WiRA = HIGH, MBA =lOW), FIF01 read (CSB = lOW, WiRB =lOW, MSS = lOW).
Figure 12. Timing for AFA when FIF01 is Almost Full
ClKS
ENS
(64-X) Words in FIF02
ClKA
ENA
3022 drw 16
Notes:
1. tSKEW2 is the minimum time between a rising ClKB edge and a rising ClKA edge for AFB to transition HIGH in the
next ClKB cycle. If the time between the rising ClKB edge and rising ClKA edge is less than tSKEW2, then AFB may
transition HIGH one ClKA cycle later than shown.
2. FIF02 Write (CSB =lOW, WiRB = HIGH, MBB =lOW), FIF02 read (CSA =lOW, WiRA = lOW, MSA = lOW).
Figure 13. Timing for AFB when FIF02 is Almost Full
5.14
22
II
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
W/RA
MBA
ENA
AO - A35
ClKB
W/RB
MBB
ENB
BO - B35
FI FO 1 Output Register
3012 drw 17
Note:
1. Port-B parity generation off (PGB
=LOW)
Figure 14. Timing for Mail1 Register and MBF1 Flag
5.14
23
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClK8
WiR8
M88
EN8
80 - 835
ClKA
WiRA
II
M8A
ENA
AO - A35
FIF02 Output Register
3012 drw 18
Note:
1. Port-A parity generation off (PGA = LOW)
Figure 15. Timing for Mail2 Register and MBF2 Flag
5.14
24
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
0001
EVEN
WiRA
MBA
PGA
3012drw 19
Note:
1. ENA is HIGH, and CSA is LOW
Figure 16. ODD/EVEN WiRl~, MBA, and PGA to PEFA Timing
0001
EVEN
W/RB
MBB
PGB
Valid
3012 drw 20
Note:
1. ENS is HIGH, and CSS is LOW
Figure 17. ODD/EVEN WIRB, MBB, and PGB to PEFB Timing
5.14
25
IDT123612 BiCMOS SyncBiFIFOTM
64 x36 x 2
COMMERCIAL TEMPERATURE RANGE
0001
EVEN
eSA
~L~O~W~
__________________________
~
_______________________________________
wiFi.A
MBA
PGA
A8, A17,
A26,A35
Mail2 Data
3012 drw21
Note:
1. ENA is HIGH
Figure 18. Parity Generation Timing when Reading from Mail2 Register
II
I
0001
EVEN
eSB
~L~O~W~
__________________________
~
______________________________________
WiRB
MBB
PGB
B8, B17,
B26,B35
Mail1 Data
3012drw 22
Note:
1. ENS is HIGH
Figure 19. Parity Generation Timing when Reading from Mail1 Register
5.14
26
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
350
f data = 1/2 fs
T A = 25°C
300
ct:
E
C L = 0 pF
250
I
'E
~
200
::::I
0
>a.
::::I
en
Q.
150
I
fr
0
100
50
0
0
10
20
30
40
50
60
70
80
f s - Clock Frequency - MHz
3012 drw 23
Figure 20
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 20 was taken while simultaneously reading and writing the FIFO on the
IDT723612 with ClKA and ClKS set to fs. All data inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.
Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f} taken from Figure 28, the maximum power dissipation (PD) of the IDT723612 may be calculated by:
PD = Vcc x ICC(f) + I(CL x Vcc x (VOH - VOL) x fo}
where:
CL
fo
VOH
VOL
output capacitance load
switching frequency of an output
output HIGH level voltage
output lOW level voltage
When no reads or writes are occurring on the IDT723612, the power dissipated by a single clock (ClKA or ClKS)
input running at frequency fs is calculated by:
PT
=Vcc x fs x 0.290 mA/MHz
5.14
27
IDT723612 SiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kQ
From Output _ - - . _ - - - -..
Under Test
30 pF(1)
6800
LOAD CIRCUIT
3V
Timing
Input
High-Level
Input
GND
3V
1.5 V
3V
Data,
Enable
Input
3V
Low-Level
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
GND
- "'3V
Low-Level
Output
GND
tw
--+--~
VOL
High-Level
Output
Input - - {
1.5 V
tPD}
In-Phase
Output _ _ _- "
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t;S
.
3V
V- -
tPD~
----1.5 V
GND
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3012 drw 24
Note:
1. Includes probe and jig capacitance
Figure 21. Load Circuit and Voltage Waveforms
5.14
28
II
IDT723612 BiCMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
xxxxxx
Device Type
x
Power
xx
x
Speed
Package
x
Process/
Temperature
Range
Y
'----------l
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
I...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- j
BLANK
Commercial (O°Clo +70°C)
PF
PQF
Thin Quad Flat Pack
Plastic Quad Flat Pack
15
0
23 0
}
L
Low Power
723612
64 x 36 x 2 SyncBiFIFO
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
3012 drw 25
5.14
29
G®
IDT723614
CMOS SyncBiFIFOTM
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
Integrated Device Technology, Inc.
P~ogrammable ~Imost-Full and Almost-Empty Flags
Microprocessor Interface control logic
EFA, FFA, AEA, and AFA flags synchronized by ClKA
EFB, FFB, AEB, and AFB flags synchronized by ClKB
Passive parity checking on each port
Parity generation can be selected for each port
low-power advanced BiCMOS technology
Supports clock frequencies up to 67 MHz
Fast access times of 10 ns
Available in 132-pin plastic quad flat package (POF) or
space-saving 120-pin thin quad flat package (TOFP)
•
•
•
•
•
•
•
•
•
•
FEATURES:
• Free-running ClKA and ClKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage
capacity each) buffering data in opposite directions
Mailbox bypass Register for each FIFO
• Dynamic Port B bus sizing of 36-bits (long word), 18-bits
(word), and 9-bits (byte)
• Selection of Big- or Little-Endian format for word and byte
bus sizes
• Three modes of byte-order swapping on port B
FUNCTIONAL BLOCK DIAGRAM
CLKAC.§A-
W/RAENAMBA-
Port-A
Control
Logic
r...=
~
ODDI
EVEN
-
~
FW
T'"'"~
Write
Pointer
I
I
FSO
FS1
Ao-Pas
3~1-
-
-
~
I
PGA
1
"I"
1
,
1
E
--.J
.-.
-
I
OlC
Parity
Gen/Check
64 x36
SRAM
.~'1i
~~
-
-
-
~ R~gi!t~r I
I I
I
~~
I
a:
~'-----J
-
36
''
:;2
~ OJ 3: f4-c..~
::2 Ul j-!: al'
~~
-
I
r-
Bo-B3S
F
A
I
Pointer
~
0
36
A
Status Flag
Logic
.....--;::
~~~
4
-
Pointer
~
,~
I
~~
r--
"'""
I
-
I
P GB
_ -
Programmable Flag
Offset Register
I
L..---
p'" 1
Oj~
Read
--t-
-
IFlF02
..... 1-
r-
oro::::lOl
Status Flag
Logic
LFIF~
P
g>.~ :; ill
::il..
row
c..r::
I
FFA
AFA
f'8""Q;
C
~.g
64 x 36
SRAM
I ~.1f-
Device
Control
M
Parity
Gen/CheckJ.,
----l1L~.;:: l'!1.~ .&.!!i~~
-ij~.~ II ~I
Mail 1
Register
~l
I
RST
• r-t
-
I
1
I
Port-B
Control
logic
f+- ClKB
f+- CSB
I-W/RB
I-ENB
BE
rI--SIZO
__ SIZ1
--SWO
- - SW1
3146 dIW01
The lOT logo is a registered trademark of Integrated DeVice Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1995
©t995 Integrated Device Technology, Inc
DSC-2071/-
5.15
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The IDT723614 is a monolithic, high-speed, low-power
SiCMOS bidirectional clocked FIFO memory. It supports
clock frequencies up to 67MHz and has read access times as
fast as 1Ons. Two independent 64 x 36 dual-port SRAM FI FOs
on board the chip buffer data in opposite directions. Each
FIFO has flags to indicate empty and full conditions and two
programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory.
FIFO data on port B can be input and output in 36-bit, 18-bit,
and 9-bit formats with a choice of big- or little-end ian configurations. Three modes of byte-order swapping are possible
with any bus size selection. Communication between each
port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has
been stored. Parity is checked passively on each port and may
be ignored if not desired. Parity generation can be selected for
data read from each port. Two or more devices can be used
in parallel to create wider data paths.
The IDT723614 is a clocked FIFO, which means each port
employs a synchronous interface. All data transfers through a
port are gated to the LOW-to-HIGH transition of a continuous
(free-running) port clock by enable signals. The clocks for
PIN CONFIGURATIONS
GND
18
AEA
EFA
19
20
Ao
A1
A2
GND
21
A7
A8
A9
31
32
Vee
GND
AE8
EF8
80
81
82
22
23
24
25
26
27
28
29
30
A3
A4
A5
A6
o
GND
83
84
85
86
Vee
PO 132 - 1
87
88
89
GND
33
A10
34
A11
Vee
A12
35
36
37
Vee
A13
A14
38
39
813
40
GND
GND
A15
A16
A17
A18
A19
A20
GND
810
811
812
814
41
815
42
816
817
43
44
45
818
819
820
46
GND
47
A21
A22
49
GND
48
821
822
A23
823
3146 drw 02
NOTES:
1. NC - No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
PQFPACKAGE
TOP VIEW
5.15
2
IDT123614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous
interface.
The full flag (FFA, FFB) and almost-full flag (AFA, AFB) of
a FI FO are two-stage synchronized to the port clock that writes
COMMERCIAL TEMPERATURE RANGE
data to its array. The empty flag (EFA, EFB) and almost-empty
(AEA, AEB) flag of a FI FO are two stage synchronized to the
port clock that reads data from its array.
The IDT723614 is characterized for operation from O°C to
70 o e.
PIN CONFIGURATIONS (CO NT.)
A23
A22
A21
1
822
821
2
3
GND
A20
A19
5
820
819
6
818
A18
A17
A16
A15
A14
A13
7
A12
13
14
15
817
816
815
814
813
812
811
810
GND
All
Al0
4
8
9
10
11
12
GND
16
A9
17
18
A8
A7
Vee
A6
A5
A4
A3
PN 120-1
GND
89
88
87
Vee
19
20
21
86
85
84
83
22
23
GND
24
GND
25
A2
26
27
81
Al
Ao
EFA
AEA
28
29
30
EF8
82
80
AE8
AF8
3146 drw03
TQFP
TOP VIEW
5.15
3
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
AO-A35
Name
Port A Data
110
I/O
Description
36-bit bidirectional data port for side A.
a
AEA
Port A Almost-Empty
Flag
Programmable almost-empty flag synchronized to ClKA. It is lOW when
(Port A) the number of 36-bit words in FIF02 is less than or equal to the value in
the offset register, X.
AEB
Port B Almost-Empty
Flag
Programmable almost-empty flag synchronized to ClKB. It is lOW when the
(Port B) number of 36-bit words in FIF01 is less than or equal to the value in the
offset register, X.
AFA
Port A Almost-Full
Flag
Programmable almost-full flag synchronized to ClKA. It is lOW when the
(Port A) number of 36-bit empty locations in FIF01 is less than or equal to the value
in the offset register, X.
AFB
Port B Almost-Full
Flag
Programmable almost-full flag synchronized to ClKB. It is lOW when the
(Port B) number of 36-bit empty locations in FIF02 is less than or equal to the value
in the offset register, X.
BO-B35
Port B Data.
a
a
a
I/O
36-bit bidirectional data port for side B.
Big-endian select
I
Selects the bytes on port B used during byte or word data transfer. A lOW
on BE selects the most significant bytes on BO-B35 for use, and a HIGH
selects the least significant bytes
ClKA
Port A Clock
I
ClKA is a continuous clock that synchronizes all data transfers through...£,Q£t A
and can be asynchronous or coincident to ClKB. EFA, FFA, AFA, and AEA
are synchronized to the lOW-to-HIGH transition of ClKA.
ClKB
Port B Clock
I
ClKB is a continuous clock that synchronizes all data transfers through port B
and can be asynchronous or coincident to ClKA. Port B byte swapping and
data port sizin.9..QPerations are als~chronous to the lOW-to-HIGH transition of ClKB. EFB, FFB, AFB, and AEB are synchronized to the lOW-to-HIGH
transition of ClKB.
CSA
Port A Chip Select
I
CSA must be lOW to enable a lOW-to-HIGH transition of ClKA to read or
write data on port A. The AO-A35 outputs are in the high-impedance state
when CSA is HIGH.
CSB
Port B Chip Select
I
CSB must be lOW to enable a lOW-to-HIGH transition of ClKB to read or
write data on port B. The BO-B35 outputs are in the high-impedance state
when CSB is HIGH.
EFA
Port A Empty Flag
EFA is synchronized to the lOW-to-HIGH transition of ClKA. When EFA is
(Port A) lOW, FIF02 is empty, and reads from its mem0lY..i!re disablecL..Q.ata can
be read from FIF02 to the output register when EFA is HIGH. EFA is forced
lOW when the device is reset and is set HIGH by the second lOW-to-HIGH
transition of ClKA after data is loaded into empty FIF02 memory.
EFB
Port B Empty Flag
EFB is synchronized to the lOW-to-HIGH transition of ClKB. When EFB is
(Port B) lOW, the FIF01 is empty, and reads from its memory are disabled. Data can
be read from FIF01 to the output register when EFB is HIGH. EFB is forced
lOW when the device is reset and is set HIGH by the second lOW-to-HIGH
transition of ClKB after data is loaded into empty FIF01 memory.
ENA
Port A Enable
I
ENA must be HIGH to enable a lOW-to-HIGH transition of ClKA to read or
write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a lOW-to-HIGH transition of ClKB to read or
write data on port B.
FFA
Port A Full Flag
FFA is synchronized to the lOW-to-HIGH transition of Cl~hen FFA is
(Port A) lOW, FIF01 is full, and writes to its memory are disabled. FFA is forced lOW
when the device is reset and is set HIGH by the second lOW-to-HIGH transition of ClKA after reset.
FFB
Port B Full Flag
FFB is synchronized to the lOW-to-HIGH transition of ClKl!.....Yv'hen FFB is
(Port B) lOW, FIF02 is full, and writes to its memory are disabled. FFB is forced lOW
when the device is reset and is set HIGH by the second lOW-to-HIGH transition of ClKB after reset.
BE
a
a
a
a
5.15
4
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 X 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol
Name
FS1, FSO Flag-Offset Selects
110
Description
I
The lOW-to-HIGH transition of RST latches the values of FSO and FS1, which
selects one of four preset values for the almost-full flag and almost-empty flag
offset.
I
A HIGH level on MBA chooses a mailbox register for a port A read or write
operation. When the AO-A35 outputs are active, a HIGH level on MBA selects
data from the mail2 register for output, and a lOW level selects FIF02 output
register data for output.
MBA
Port A Mailbox
Select
MBF1
Mail1 Register Flag
a
MBF1 is set lOW by a lOW-to-HIGH transition of ClKA that writes data to the
mail1 register. Writes to the mail1 register are inhibited while MBF1 is set lOW.
MBF1 is set HIGH by a lOW-to-HIGH transition of ClKB when a port B read is
selected and both SIZ1 and SIZO are HIGH. MBF1 is set HIGH when the device
is reset.
MBF2
Mail2 Register Flag
a
MBF2 is set lOW by a lOW-to-HIGH transition of ClKB that writes data to the
mail2 register. Writes to the mail2 register are inhibited while MBF2 is set lOW.
MBF2 is set HIGH by a lOW-to-HIGH transition of ClKA when a port A read is
selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
000/
EVEN
Odd/Even Parity
Select
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is
checked when ODD/EVEN is lOW. ODD/EVEN also selects the type of parity
generated for each port if parity generation is enabled for a readoperation.
PEFA
Port A Parity Error
Flag
a
When any byte applied to terminals AO-A35 fails parity, PEFA is lOW. Bytes are
(Port A) organized as AO-AS, A9-A17, A1S-A26, and A27-A35, with the most significant
bit of each byte serving as the l2arity bit. The type of parity checked is deter
mined by the state of the ODD/EVEN input.
The parity trees used to check the AO-A35 inputs are shared by the mail2 register
to generate parity if parity generation is sele~ed by PGA. Therefore, if a mail2
read parity generation is setup by having W/RA lOW, MBA HIGH, and PGA
HIGH, the PEFA flag is forced HIGH regardless of the AO-A35 inputs.
PEFS
Port B Parity Error
Flag
a
When any valid byte applied to terminals BO-B35 fails parity, PEFS is lOW. Bytes
(Port B) are organized as BO-BS, B9-B 17, B 18-B26, B27 -B35 with the most significant bit
of each byte serving as the parity bit. A byte is valid when it is used by the bus
size selected for Port B. The type of parity checked is determined by the state of
the ODD/EVEN input.
The parity trees used to check the BO-B35 inputs are sharedby the mail 1 register to
generate parity if parity generation isselecteQ by PGB. Therefore, if a mail1 read
with parity generation is setup by having W/RB lOW, SIZ1 and SIZO HIGH, and
PGB HIGH, the PEFS flag is forced HIGH regardless of the state of the BO-B35
inputs.
PGA
Port A Parity
Generation
I
Parity is generated for data reads from port A when PGA is HIGH. The type of
parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as AO-AS, A9-A 17, A 1S-A26, and A27 -A35. The generated parity
bits are output in the most significant bit of each byte.
PGB
Port B Parity
Generation
I
Parity is generated for data reads from port B when PGB is HIGH. The type
of parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as BO-BS, B9-B17, B1S-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
RST
Reset
I
To reset the device, four lOW-to-HIGH transitions of ClKA and four lOW-toHIGH transitions of ClKB must occur while RST is lO~his sets the AFA,
AFS, MBF1, and MBF2 flags HIGH and the EFA, EFS, AEA, AEB, FFA, and
FFS flags lOW. The lOW-to-HIGH transition of RST latches the status of the
FS1 and FSO inputs to select almost-full and almost-empty flag offsets
SIZO, SIZ1
Port B bus size
selects
I
A lOW-to-HIGH transition of ClKB latches the states of SIZO, SIZ1, and BE, and
(Port B) the following lOW-to-HIGH transition of ClKB implements the latched states as a
port B bus size. Port B bus sizes can be long word, word, or byte. A high on both
SIZO and SIZ1 accesses the mailbox reegisters for a port B 36-bit write or read.
5.15
5
II
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 X 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol
Name
ISwo, SW1 Port B byte swap
Select
1/0
Description
I
At the beginning of each long word transfer, one of four modes of byte-order
(Port B) swapping is selected by SWO and SW1. The four modes are no swap, byte
swap, word swap, and byte-word swap. Byte-order swapping is possible with
any bus-size selection.
W/RA
Port A Write/Read
Select
I
A HIGH selects a write operation and a lOW selects a read operation on
port A for a lOW-to-HIGH tran~ion of ClKA. The AO-A35 outputs are in the
high-impedance state when W/RA is HIGH.
W/RB
Port B Write/Read
Select
I
A HIGH selects a write operation and a lOW selects a read operation on
port B for a lOW-to-HIGH tran~ion of ClKB. The BO-B35 outputs are in the
high-impedance state when W/RB is HIGH.
SIGNAL DESCRIPTIONS
RESET
The IDT723614 is reset by taking the reset (RST) input
lOW for at least four port A clock (ClKA) and four port B clock
(ClKB) lOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (FFA, FFB) lOW, the empty flags (EFA, EFB) lOW,
the almost-empty flags (AEA, AEB) lOW and the almost-full
flags (AFA, AFB) HIGH. A reset also forces the mailbox flags
(MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two
lOW-to-HIGH transitions of ClKA and FFB is set HIGH after
two lOW-to-HIGH transitions of ClKB. The device must be
reset after power up before data is written to its memory.
A lOW-to-HIGH transition on the RST input loads the
almost-full and almost-empty offset register (X) with the values selected by the flag-select (FSO, FS 1) inputs. The values
that can be loaded into the registers are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of port A data AO-A35 outputs is controlled by
the port A chip select (CSA) and the port A writelread select
(WiRA). The AO-A35 outputs are in the high-impedance state
when either CSA or WiRA is HIGH. The AO-A35 outputs are
active when both CSA and WiRA are lOW. Data is loaded into
FIF01 from the AO-A35 inputs on a lOW-to-HIGH transition
of ClKA when CSA is lOW, WiRA is HIGH, ENA is HIGH,
MBA is lOW, and FFA is HIGH. Data is read from FIF02 to
the AO-A35 outputs by a lOW-to-HIGH transition of ClKA
when CSA is lOW, WiRA is lOW, ENA is HIGH, MBA is lOW,
and EFA is HIGH (see Table 2).
The port B control signals are identical to those of port A.
The state of the port B data (BO-B35) outputs is controlled by
the port B chip select (CSB) and the port B write/read select
(WiRB). The BO-B35 outputs are in the high-impedance state
when either CSB or WiRB is HIGH. The BO-B35 outputs are
active when both CSB and WiRB are lOW. Data is loaded into
FIF02 from the BO-B35 inputs on a lOW-to-HIGH transition
of ClKB when CSB is lOW, wiRB is HIGH, ENB is HIGH, EFB
is HIGH, and either SIZO or SIZ1 is lOW. Data is read from
FIF01 to the BO-B35 outputs by a lOW-to-HIGH transition of
ClKB when CSB is lOW, wiRB is lOW, ENB is HIGH, EFB
is HIGH, and either SIZO or SIZ1 is lOW (see Table 3).
The setup and hold time constraints to the port clocks
forthe port chip selects (CSA, CSB) and write/read selects (W/
RA, W/RB) are onlyforenabling write and read operations and
are not related to high-impedance control of the data outputs.
If a port enable is lOW during a clock cycle, the port chip select
and write/read select can change states during the setup and
hold time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two
flip-flop stages. This is done to improve flag reliability by
reducing the probability of metastable events on the output
when ClKA and ClKB operate asynchronously to one another. EFA, AEA' FFA, and AFA are synchronized to ClKA.
EFB, AEB, FFB, and AFB are synchronized to ClKB. Tables
4 and 5 show the relationship of each port flag to FIF01 and
FIF02.
EMPTY FLAGS (EFA, EFB)
The empty flag of a FI Fa is synchronized to the port clock
that reads data from its array. When the empty flag is HIGH,
new data can be read to the FIFO output register. When the
empty flag is lOW, the FIFO is empty and attempted FIFO
reads are ignored. When reading FIF01 with a byte or word
size on port B, EFB is set lOW when the fourth byte or second
word of the last long word is read.
The read pointer of a FIFO is incremented each time a
new word is clocked to the output register. The state machine
that controls an empty flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is empty, empty+ 1, or empty+2. A word written to a
FIFO can be read to the FIFO output register in a minimum of
three cycles of the empty flag synchronizing clock. Therefore,
an empty flag is lOW if a word in memory is the next data to
be sent to the FIFO output register and two cycles of the port
5.15
6
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 X 36 X 2
clock that reads data from the FI Fa have not elapsed since the
time the word was written. The empty flag of the FIFO is set
HIGH by the second LOW-to-HIGH transition of the synchronizing clock, and the new data word can be read to the FIFO
output register in the following cycle.
A LOW-to-HIGH transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the
clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 13 and 14).
TABLE 1: FLAG PROGRAMMING
FS1
FSO
RST
H
H
i
i
i
i
H
L
L
H
L
L
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
16
12
8
COMMERCIAL TEMPERATURE RANGE
FULL FLAG (FFA, FFB)
The full flag of a FIFO is synchronized to the port clock
that writes data to its array. When the full flag is HIGH, a
memory location is free in the SRAM to receive new data. No
memory locations are free when the full flag is LOW and
attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is
incremented. The state machine that controls a full flag
monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous
memory location is ready to be written in a minimum of three
cycles of the full flag synchronizing clock. Therefore, a full flag
is LOW if less than two cycles of the full flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the full
flag synchronization clock after the read sets the full flag HIGH
and the data can be written in the following clock cycle.
A LOW-to-HIGH transition on a full flag synchronizing
clock begins the first synchronization cycle of a read if the
clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 15 and 16).
4
TABLE 2· PORT-A ENABLE FUNCTION TABLE
GSA
W/RA
ENA
MBA
CLKA
AO-A35 Outputs
Port Functions
H
X
X
None
H
L
X
X
In High-Impedance State
L
X
X
In High-Impedance State
None
L
H
H
L
In High-Impedance State
FIF01 Write
L
H
H
H
i
i
In High-Impedance State
Mail1 Write
L
L
L
L
X
Active, FIF02 Output Register
None
FIF02 Read
L
L
H
L
i
Active, FIF02 Output Register
L
L
L
H
X
Active, Mail2 Register
None
L
L
H
H
i
Active, Mail2 Register
Mail2 Read (Set MBF2 HIGH)
TABLE 3: PORT-B ENABLE FUNCTION TABLE
GSB
WIRB
ENB
SIZ1, SIZO
CLKB
BO-B35 Outputs
Port Functions
H
X
X
None
H
L
X
X
In High-Impedance State
L
X
X
L
H
H
One, both LOW
L
H
H
L
L
L
L
L
L
L
In High-Impedance State
None
In High-Impedance State
FIF02 Write
Both HIGH
i
i
In High-Impedance State
Mail2 Write
One, both LOW
X
Active, FIF01 Output Register
None
H
One, both LOW
i
Active, FIF01 Output Register
FIF01 read
L
L
Both HIGH
X
Active, Mail1 Register
None
L
H
Both HIGH
i
Active, Mail1 Register
Mail1 Read (Set MBF1 HIGH)
5.15
7
11
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 X 36 X 2
ALMOST EMPTY FLAGS (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array. The state machine
that controls an almost-empty flag monitors a write-pointer
and a read-pointer comparator that indicates when the FIFO
SRAM status is almost empty, almost empty+1, or almost
empty+2. The almost-empty state is defined by the value of
the almost-full and almost-empty offset register (X). This
register is loaded with one of four preset values during a
device reset (see Reset above). An almost-empty flag is LOW
when the FIFO contains X or less long words in memory and
is HIGH when the FIFO contains (X+ 1) or more long words.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill. Therefore, the
almost-empty flag of a FIFO containing (X+ 1) or more long
words remains LOW if two cycles of the synchronizing clock
have not elapsed since the write that filled the memory to the
(X+ 1) level. An almost-empty flag is set HIGH by the second
LOW-to-HIGH transition of the synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-toHIGH transition of an almost-empty flag synchronizing clock
begins the first synchronization cycle if it occurs at time tSKEW2
or greater after the write that fills the FI Fa to (X+ 1) long words.
Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figure 17 and 18).
COMMERCIAL TEMPERATURE RANGE
more long words in memory and is HIGH when the FIFO
contains [64-(X+ 1)] or less long words.
Two LOW-to-HIGH transitions of the almost-full flag
synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing [64-(X+ 1)] or less words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the read that reduced the number of long words
in memory to [64-(X+1)]. An almost-full flag is set HIGH by the
second LOW-to-HIGH transition of the synchronizing clock
after the FIFO read that reduces the number of long words in
memory to [64-(X+ 1)]. A LOW-to-HIGH transition of an
almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read
that reduces the number of long words in memory to [64(X+ 1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 19 and 20).
ALMOST FULL FLAGS (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almostempty offset register (X). This register is loaded with one of
four preset values during a device reset (see Reset above).
An almost-full flag is LOW when the FIFO contains (64-X) or
MAILBOX REGISTERS
Each FI Fa has a 36-bit bypass register to pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on GLKA writes
AO-A35 data to the mail1 register when a port A write is
selected by GSA, WiRA, and ENA with MBA HIGH. A LOWto-HIGH transition on GLKB writes BO-B35 data to the mail2
register when a port B write is selected by GSB, WiRB, and
ENB with both SIZ1 and SIZO HIGH. Writing data to a mail
register sets the corresponding flag (MBF1 or MBF2) LOW.
Attempted writes to a mail register are ignored while the mail
flag is LOW.
When the port A data outputs (AO-A35) are active, the
data on the bus comes from the FIF02 output register when
MBA is LOW and from the mail2 register when MBA is HIGH.
When the port B data outputs (BO-B35) are active, the data on
the bus comes from the FI F01 output register when either one
TABLE 4: FIF01 FLAG OPERATION
TABLE 5: FIF02 FLAG OPERATION
Synchronized
Number of 36-Bit
to CLKB
Synchronized
Number of 36-Bit
to CLKA
Synchronized
Synchronized
to CLKB
to CLKA
Words in the FIF01(1
EFB
AEB
AFA
FFA
Words in the FIF02(1)
EFA
AEA
AFB
FFB
0
L
L
H
H
0
L
L
H
H
1 to X
H
L
H
H
1 to X
H
L
H
H
(X+ 1) to [64-(X+ 1)]
H
H
H
H
(X+1) to [64-(X+1)]
H
H
H
H
H
H
L
H
H
H
L
L
(64-X) to 63
H
H
L
H
(64-X) to 63
64
H
H
L
L
64
NOTE:
1. X is the value in the almost-empty flag and almost-full flag offset register.
5.15
8
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)(1)
Symbol
Rating
Commercial
Unit
-0.5 to 7
V
Input Voltage Range
-0.5 to Vce+0.5
V
Output Voltage Range
-0.5 to Vee+0.5
V
VCC
W2)
Supply Voltage Range
VO(2)
11K
Input Clamp Current, (VI < 0 or VI > Vee)
±20
rnA
10K
Output Clamp Current, (Vo < 0 or Vo > Vee)
±50
rnA
lOUT
Continuous Output Current, (Vo = 0 to Vee)
±50
rnA
Icc
Continuous Current Through Vee or GND
±500
TA
Operating Free Air Temperature Range
o to 70
rnA
DC
TSTG
Storage Temperature Range
-65 to 150
DC
NOTES:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
1.
I
II
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VIH
Min.
Max. Unit
4.5
5.5
V
HIGH level Input Voltage
2
-
V
Vil
lOW-level Input Voltage
V
HIGH-level Output Current
-
0.8
IOH
-4
rnA
8
0
70
rnA
DC
IOl
lOW-level Output Current
TA
Operating Free-air
Temperature
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions
Min.
2.4
Typ.(1)
Max.
Unit
V
VOH
Vee=4.5V,
10H = -4 rnA
VOL
Vee = 4.5 V,
10l = 8 rnA
0.5
V
II
Vee = 5.5 V,
VI = Vee orO
±50
I1A
loz
Vee = 5.5 V,
vo = Vee or 0
±50
I1A
Outputs HIGH
30
rnA
Vee = 5.5 V,
10 = 0 rnA,
Outputs lOW
130
rnA
30
rnA
Icc
VI = Vee or GND
Outputs Disabled
CIN
VI=O,
f = 1 MHz
4
pF
COUT
Vo=O,
f = 1 MHZ
8
pF
NOTE:
1 . All typical
values are at vee =5 v, TA =25°C.
5.15
9
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE (See Figures 4 through 26)
Symbol
IDT723614L 15 IDT723614L20 IDT723614L30
Min.
Max.
Min.
Max.
Min.
Max.
Parameter
Unit
50
-
33.4
20
-
30
8
-
12
-
8
-
12
4
-
5
-
6
-
5
-
5
-
6
-
ns
66.7
-
15
-
6
-
Pulse Duration, ClKA and ClKB lOW
6
tDS
Setup Time, AO-A35 before ClKA i and BO-B35
before ClKBi
tENS
Setup Time, CSA, WiRA, ENA and MBA before
ClKAi; CSB,wiRB and ENB before ClKBi
fs
Clock Frequency, ClKA or ClKB
-
tClK
Clock Cycle Time, ClKA or ClKB
tClKH
Pulse Duration, ClKA and ClKB HIGH
tClKl
MHz
ns
ns
ns
ns
tszs
Setup Time, SIZO, SIZ1 ,and BE before ClKBi
4
-
6
5
7
-
8
-
ns
Setup Time, SWO and SW1 before ClKBi
-
5
tsws
tPGS
Setup Time, ODD/EVEN and PGA before
4
-
5
-
6
-
ns
ns
ClKA i; ODD/EVEN and PGB before ClKBi(1)
tRSTS
Setup Time, RST lOW before ClKA i
or ClKBi(2)
5
-
6
-
7
-
ns
tFSS
Setup Time, FSO and FS1 before RST HIGH
5
-
7
1
1
-
1
-
ns
Hold Time, AO-A35 after ClKA i and BO-B35
after ClKBi
-
6
tDH
tENH
Hold Time, CSA, W/RA, ENA and MBA after
ClKA i; CSB, W/RB, and ENB after ClKBi
1
-
1
-
1
-
ns
tSZH
Hold Time, SIZO, SIZ1 , and BE after ClKBi
2
0
0
0
-
0
-
ns
0
-
2
Hold Time, SWO and SW1 after ClKBi
-
2
tSWH
7
-
ns
4
-
ns
10
-
ns
20
-
ns
tPGH
Hold Time, ODD/EVEN and PGA after ClKAi;
ODD/EVEN and PGB after ClKBi(1)
0
tRSTH
Hold Time, RST lOW after ClKA i or ClKBi(2)
5
-
6
tFSH
Hold Time, FSO and FS1 after RST HIGH
4
-
4
tSKEW1(3)
Skew Time, between ClKA i and ClKBi
for EFA, EFB, FFA, and FFB
8
-
8
-
tSKEW2(3)
Skew Time, between ClKA i and ClKBi
for AEA, AEB, AFA, and AFB
9
-
16
-
ns
ns
ns
NOTES:
1.
2.
3.
Only applies for a clock edge that does a FIFO read.
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between ClKA cycle and
ClKS cycle.
5.15
10
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 X 36 X 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL 30pF (See Figures 4 through 26)
=
Symbol
IDT723614L15 IDT723614L20 IDT723614L30
Min.
Max.
Min.
Max.
Min.
Max.
Parameter
Unit
tA
Access Time, CLKAi to AO-A35 and CLKBi
to BO-B35
2
10
2
12
2
15
ns
tWFF
Propagation Delay Time, CLKAito FFA and
CLKBi to FFB
2
10
2
12
2
15
ns
tREF
Propagation Delay Time, CLKA i to EFA and
and CLKBi to EFB
2
10
2
12
2
15
ns
tPAE
Propagation Delay Time, CLKA i to AEA and
CLKBito AEB
2
10
2
12
2
15
ns
tPAF
Propagation Delay Time, CLKA ito AFA and
CLKBito AFB
2
10
2
12
2
15
ns
tPMF
Propagation Delay Time, CLKAito MBF1 LOW
or MBF2 HIGH and CLKBi to MBF2 LOW or
MBF1 HIGH
1
9
1
12
1
15
ns
tPMR
Propagation Delay Time, CLKA i to BO-B35(1)
and CLKBi to AO-A35(2)
3
11
3
13
3
15
ns
tPPE(3)
Propagation delay time, CLKBi to PEFB
2
11
2
12
2
13
ns
tMDV
Propagation Delay Time, MBA to AO-A35 valid
and SIZ1 , SIZO to BO-B35 valid
1
11
1
11.5
1
12
ns
tPDPE
Propagation Delay Time, AO-A35 valid to PEFA
valid; BO-B35 valid to PEFB valid
3
10
3
11
3
13
ns
tpOPE
Propagation Delay Time, ODD/EVEN to PEFA
and PEFB
3
11
3
12
3
14
ns
tpOPB(4)
Propagation Delay Time, ODD/EVEN to parity
bits (A8, A17, A26, A35) and (B8, B17, B26,
B35)
2
11
2
12
2
14
ns
tPEPE
Propagation Delay Time, CSA, ENA,W/RA,
MBA, or PGA to PEFA; CSB, ENB, WiRB, SIZ1,
SIZO, or PGB to PEFS
1
11
1
12
1
14
ns
tPEPB(4)
Propagation Delay Time, CSA, ENA, W/RA,
MBA, or PGA to parity bits (A8, A17, A26, A35);
CSB, ENB, WiRB,SIZ1, SIZO, or PGB to parity
bits (B8, B17, B26, B35)
3
12
3
13
3
14
ns
tRSF
Propagation Delay Time, RST to (MBF1, MBF2)
HIGH
1
15
1
20
1
30
ns
tEN
Enable Time, CSA and W/RA LOW to AO-A35
active and CSB LOW and W/RB HIGH to
BO-B35 active
2
10
2
12
2
14
ns
tDIS
Disable Time, CSA or W/RA HIGH to AO-A35
at high impedance and CSB HIGH or W/RB
LOW to BO-B35 at high impedance
1
8
1
9
1
11
ns
NOTES:
1.
2.
3.
4.
Writing data to the mail1 register when the BO-B35 outputs are active and SIZ1, SIZO are HIGH.
Writing data to the mail2 register when the AO-A35 outputs are active and MBA is HIGH.
Only applies when a new port B bus size is implemented by the rising elKB edge.
Only applies when reading data from a mail register.
5.15
11
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
0 0 0
A35--A27
BYTE ORDER ON PORT A:
835--827
8E
SIZ1
X
L
SIZO
L
A26--A18
826--818
COMMERCIAL TEMPERATURE RANGE
A17--A9
817--89
A8--AO
~
Write to FIF011
Read From FIF02
88--80
000~
Read from FIF011
Write to FI F02
(a) LONG WORD SIZE
835--827
BE
SIZ1
SIZO
L
L
H
826--818
817--89
88--80
00~~
835--827
826--818
817--89
88--80
~0~~
(b) WORD SIZE -
BE
SIZ1
SIZO
H
L
H
1st: Read from FIF011
Write to FI F02
2nd: Read from FIF011
Write to FIF02
BIG ENDIAN
1st: Read from FIF01/
Write to FIF02
835--827
826--818
817--89
88--80
~~0~
2nd: Read from FIF011
Write to FI F02
(c) WORD SIZE - LITTLE EN DIAN
835--827
BE
SIZ1
SIZO
L
H
L
826--818
817--89
88--80
0~~~
835--827
826--818
817--89
88--80
0~~~
835--827
826--818
817-89
826--818
817-89
BIG ENDIAN
3rd: Read from FIF011
Write to FI F02
88-80
0~~~
(d) BYTE SIZE -
2nd: Read from FIF01/
Write to FIF02
88-80
~~~~
835--827
1st: Read from FIF011
Write to FI F02
4th: Read from FIF011
Write to FI F02
3146 drw fig 01
Figure 1. Dynamic Bus Sizing
5.15
12
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
B35--B27
B26--B18
B17--B9
COMMERCIAL TEMPERATURE RANGE
B8--BO
~~~G
B35--B27
B26--B18
B17--B9
B8--BO
~~~0
B35--B27
B26--B18
B17--B9
B26--B18
B17--B9
3rd: Read from FIF01/
Write to FIF02
B8--BO
~~~0
(d) BYTE SIZE -
2nd: Read from FIF01/
Write to FIF02
B8--BO
~~~0
B35--B27
1st: Read from FIF01/
Write to FI F02
4th: Read from FIF01/
Write to FIF02
LITTLE EN DIAN
3146 drw fig 01a
Figure 1. Dynamic Bus Sizing (continued)
DESCRIPTION (CONTINUED)
or both SIZ1 and SIZO are lOW and from the mail2 register
when both SIZ1 and SIZO are HIGH.The mail1 register flag
(MBF1) is set HIGH by a rising ClKB edge when a port Bread
is selected by CSB, WiRB, and ENB with both SIZ1 and SIZO
HIGH. The mail2 register flag (MBF2) is set HIGH by a lOWto-HIGH transition on ClKA when port A read is selected by
CSA, W/RA, and ENA and MBA is HIGH. The data in the mail
register remains intact after it is read and changes only when
new data is written to the register.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word,
18-bit word, or 9-bit byte format for data read from FIF01 or
written to FIF02. Word- and byte-size bus selections can
utilize the most significant bytes ofthe bus (big endian) or least
significant bytes of the bus (little endian). Port B bus size can
be changed dynamically and synchronous to ClKB to communicate with peripherals of various bus widths.
The levels applied to the port B bus size select (SIZO,
SIZ1) inputs and the big-end ian select (BE) input are stored on
each ClKB lOW-to-HIGH transition. The stored port B bus
size selection is implemented by the next rising edge on ClKB
according to Figure 1.
Only 36-bit long-word data is written to or read from the
two FIFO memories on the IDT723614. Bus-matching operations are done after data is read from the FIF01 RAM and
before data is written to the FIF02 RAM. Port B bus sizing
does not apply to mail register operations.
BUS-MATCHING FIF01 READS
Data is read from the FIF01 RAM in 36-bit long word
increments. If a long word bus size is implemented, the entire
long word immediately shifts to the FIF01 output register. If
byte or word size is implemented on port B, only the first one
or two bytes appear on the selected portion of the FIF01
output register, with the rest of the long word stored in auxiliary
registers. In this case, subsequent FIF01 reads with the same
bus-size implementation output the rest of the long word to the
FIF01 output register in the order shown by Figure1.
Each FIF01 read with a new bus-size implementation
automatically unloads data from the FIF01 RAM to its output
register and auxiliary registers .. Therefore, implementing a
new port B bus size and performing a FIF01 read before all
bytes orwords stored in the auxiliary registers have been read
results in a loss of the unread long word data.
When reading data from FIF01 in byte orword format, the
unused BO-B35 outputs remain inactive but static, with the
unused FIF01 output register bits holding the last data value
to decrease power consumption.
BUS-MATCHING FIF02 WRITES
Data is written to the FIF02 RAM in 36-bit long word
increments. FIF02 writes, with a long-word bus size, immediately store each long word in FIF02 RAM. Data written to
FIF02 with a byte or word bus size stores the initial bytes or
words in auxiliary registers. The ClKB rising edge that writes
the fourth byte or the second word of long word to FIF02 also
stores the entire long word in FIF02 RAM. The bytes are
arranged in the manner shown in Figure 1.
Each FIF02 write with a new bus-size implementation
resets the state machine that controls the data flow from the
auxiliary registers to the FIF02 RAM. Therefore, implementing a new bus size and performing a FIF02 write before bytes
or words stored in the auxiliary registers have been loaded to
FIF02 RAM results in a loss of data.
5.15
13
II
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
PORT-8 MAIL REGISTER ACCESS
In addition to selecting port-B bus sizes for FIFO reads
and writes, the port B bus size select (SIZO, SIZ1) inputs also
access the mail registers. When both SIZO and SIZ1 are
HIGH, the mail1 register is accessed for a port B long word
read and the mail2 register is accessed for a port B long word
write. The mail register is accessed immediately and any bussizing operation that may be underway is unaffected by the
mail register access. After the mail register access is complete, the previous FIFO access can resume in the next ClKB
cycle. The logic diagram in Figure 2 shows the previous bussize selection is preserved when the mail registers are accessed from port B. A port B bus size is implemented on each
rising ClKB edge according to the states of SIZO_O, SIZLO,
and BE_Q.
BYTE SWAPPING
The byte-order arrangement of data read from FI F01 or
data written to FIF02 can be changed synchronous to the
rising edge of ClKB. Byte-order swapping is not available for
mail register data. Four modes of byte-order swapping (including no swap) can be done with any data port size selection. The order of the bytes are rearranged within the long
word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port B swap select
(SWO, SW1) inputs on a ClKB rising edge that reads a new
long word from FIF01 or writes a new long word to FIF02. The
byte order chosen on the first byte or first word of a new long
COMMERCIAL TEMPERATURE RANGE
word read from FIF01 or written to FIF02 is maintained until
the entire long word is transferred, regardless of the SWO and
SW1 states during subsequent writes or reads. Figure 3 is an
example of the byte-order swapping available for long words.
Performing a byte swap and bus size simultaneously for a
FIF01 read first rearranges the bytes as shown in Figure 3,
then outputs the bytes as shown in Figure 1. Simultaneous
bus-sizing and byte-swapping operations for FIF02 writes,
first loads the data according to Figure 1, then swaps the bytes
as shown in Figure 3 when the long word is loaded to FIF02
RAM.
PARITY CHECKING
The port A inputs (AO-A35) and port B inputs (BO-B35)
each have four parity trees to check the parity of incoming (or
outgoing) data. A parity failure on one or more bytes of the port
A data bus is reported by a lOW level on the port parity error
flag (PEFA). A parity failure on one or more bytes of the port
B data input that are valid for the bus-size implementation is
reported by a lOW level on the port B parity error flag
(PEFB).Odd or even parity checking can be selected, and the
parity error flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to
the level of the odd/even parity (ODD/EVEN) select input. A
parity error on one or more valid bytes of a port is reported by
a lOW level on the corresponding port parity error flag (PEFA,
PEFB) output. Port A bytes are arranged as AO-A8, A9-A 17,
ClKB----------------------------~
SIZO_O
SIZ1_O
1 - - - - - 4 1 - BE_O
.......-..t.....-
--------------4
Io-___~-
SIZO - - _......
SIZ1 ----....-------------1
BE - - - - - - - - - L__--'
3146 drw fig 02
Figure 2. Logic Diagrams for SIZO, SIZ1, and BE Register
5.15
14
101723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
A35-A27
I SW1L Iswo
I
L
835-827
COMMERCIAL TEMPERATURE RANGE
A26-A18
A17-A9
A8-AO
~
~
~
826-818
817-89
88-80
ctJ cb ctJ
(a) NO SWAP
A35-A27
A26-A18
A17-A9
A8-AO
835-827
826-818
817-89
88-80
I SW1L Iswo
I
H
(b) BYTE SWAP
A35-A27
A26-A18
A17-A9
A8-AO
835-827
826-818
817-89
88-80
ISW1H Iswo
I
L
(c) WORD SWAP
A35-A27
A26-A18
I SW1H Iswo
I
H
835-827
826-818
817-89
88-80
(d) BYTE-WORD SWAP
3146 drw fig 03
Figure 3. Byte Swapping (Long Word Size Example)
5.15
15
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
A 18-A26, and A27 -A35. Port B bytes are arranged as BO-B8,
B9-B17, B18-B26, and B27-B35, and its valid bytes are those
used in a port B bus-size implementation. When odd/even
parity is selected, a port parity error flag (PEFA, PEFS) is lOW
if any byte on the port has an odd/even number of lOW levels
applied to the bits.
The four parity trees used to check the AO-A35 inputs are
shared by the mail2 register when parity generation is selected for port A reads (PGA = HIGH). When a port A read from
the mail2 register with parity generation is selected with CSA
lOW, ENA HIGH, WiRA lOW, MBA HIGH, and PGA HIGH,
the port A parity error flag (PEFA) is held HIGH regardless of
the levels applied to the AO-A35 inputs. Likewise, the parity
trees used to check the BO-B35 inputs are shared by the mail1
register when parity generation is selected for port Breads
(PGB = HIGH). When a port B read from the mail1 registerwith
parity generation is selected with CSB lOW, ENB HIGH, W/
RB lOW, both SI20 and SI21 HIGH, and PGB HIGH, the port
B parity error flag (PEFS) is held HIGH regardless of the levels
applied to the BO-B35 inputs.
PARITY GENERATION
A HIGH level on the port A parity generate select (PGA)
or port B parity generate select (PGB) enables the IDT723614
to generate parity bits for port reads from a FIFO or mailbox
register. Port A bytes are arranged as AO-A8, A9-A 17, A 1826, and A27 -A35, with the most significant bit of each byte
used as the parity bit. Port B bytes are arranged as BO-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of
COMMERCIAL TEMPERATURE RANGE
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all nine inputs of a byte
regardless of the state of the parity generate select (PGA,
PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used
to generate a parity bit according to the level on the ODO/
EVEN select. The generated parity bits are substituted for the
levels originally written to the most significant bits of each byte
as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port A parity generate select (PGA)
and odd/even parity select (ODD/EVEN) have setup and hold
time constraints to the port A clock (ClKA) and the port B
parity generate select (PGB) and ODD/EVEN have setup and
hold-time constraints to the port B clock (ClKB). These timing
constraints only apply for a rising clock edge used to read a
new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port B bus (BO-B35) to check parity and the
circuit used to generate parity for the mail2 data is shared by
the port A bus (AO-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in
a mail register when the port chip select (CSA, CSB) is lOW,
enable (ENA, ENB) is HIGH, write/read select (WiRA., W/RB)
input is lOW, the mail register is selected (MBA is HIGH for
portA; both SI20and SI21 are HIGH for port B), and port parity
generate select (PGA, PGB) is HIGH. Generating parity for
mail register data does not change the contents of the register.
5.15
16
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
ClKB
FS1,FSO
EFB
MBF1,
MBF2
Figure 4. Device Reset Loading the X Register with the Value of Eight
5.15
17
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
WiRA
MBA
ENA
AO - A35
ODD/
EVEN
PEFA
3146 drw05
NOTE:
1. Written to FIF01.
Figure 5. Port-A Write Cycle Timing for FIF01
5.15
18
IDTI23614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
elKS
WiRS
ENS
SW1,
SWO
SE
SIZ1,
SIZO
SO-S35
0001
EVEN
II
PEFS
3146 drw06
NOTE:
1. SIZO
=HIGH and SIZ1 =HIGH writes data to the mail2 register
DATA SWAP TA8LE FOR LONG-WORD WRITES TO FIF02
DATA READ FROM FIF02
DATA WRITTEN TO FIF02
SWAP MODE
SW1
SWO
835-27
826-18
817-89
88-80
A35-27
A26-A18
A17-A9
A8-AO
L
L
A
B
C
0
A
B
C
0
L
H
0
C
B
A
A
B
C
0
H
L
C
0
A
B
A
B
C
0
H
H
B
A
0
C
A
B
C
0
Figure 6. Port-8 Long-Word Write Cycle Timing for FIF02
5.15
19
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
elKB
COMMERCIAL TEMPERATURE RANGE
~
/
~
HIGH
tENS-
M:NH
--
~..-
tENS
wiRB /LL/. V//1/L//L-,£
ENB / / / /
~/
/ / / / / / /7'-
ID
tSZH
Li.ttle)BO-B17
Endlan,(
ID
}XXXXXXXXXXXXXXXXXXXXXXXX
tszs
tSZH
(0,1) ) XXXXXXX K (0,1)
~
ODD/EVEN
XX
XXXXX~..NOT(1,11(1i)(
X XXXXXX XXXXX
tOH
tos
XXXXXXXXXXXXXK
XXXXXXXX
xxxxxxxxxXXXX
tOH
tos
Bi9h
Endian'l:1S-B35
xxxxxxxxxxxX
tSZH
) XXXXXXX
tszs
SIZ1, SIZO
}lXXXXXXXX
tszs
tSZH
I
tSWH
xxxxxxxx
tszs
~""""",'
~I-XXXXXXX}f-
tsws
SW1, SWO XXXX
·i tENH
tENS,
tENH
tENS
XXXXXXXXXXXXX
)
xxxxxxXX
xxxxxxxxxxxxx
ID<
tPOPE~
1_
tpPE
x xxxxxxxxxx XX x
xx.x.x~XXXXXXX VALID
xxxxxxxx
NOTES:
1.
SIZO =HIGH and SIZ1 = HIGH writes data to the mail2 register.
2.
PEF8 indicates parity error for the following bytes: 835-827 and 826-818 for big-endian bus, and 817-89 and 8-8-80 for little-endian bus.
3146 drw 07
DATA SWAP TA8LE FOR WORD WRITES TO FIF02
SWAP
MODE
SW1
SWO
L
L
L
H
H
H
L
H
WRITE
NO.
DATA WRITTEN TO FIF02
81G ENDIAN
DATA READ FROM FIF02
LITTLE ENDIAN
835-27
826-18
817-89
88-80
A35-27
A26-A18
A17-A9
A8-AO
1
A
B
C
D
A
B
C
D
2
C
D
A
B
1
D
C
B
A
A
B
C
D
2
B
A
D
C
1
C
D
A
B
A
B
C
D
2
A
B
C
D
1
B
A
D
C
A
B
C
D
2
D
C
B
A
Figure 7. Port-8 Word Write Cycle Timing for FIF02
5.15
20
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x36 x 2
COMMERCIAL TEMPERATURE RANGE
elKB
W/RB
ENB
SW1,
SWO
SIZ1,
SIZO
Not (1,1)(1)
Little fBOEndian \..J38
Big ....J827-
Endian~35
II
ODD/EVEN
Valid
3146 drw08
NOTES:
1.
SIZO = HIGH amd SIZ1 = HIGH writes data to the mail2 register.
2.
PEF8 indicates parity error for the following by1es: 835-827 for big-endian bus and 817-89 for little-endian bus.
Figure 8. Port-B Byte Write Cycle Timing for FIF02
5.15
21
1DT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DATA SWAP TABLE FOR BYTE WRITES TO FIF02
DATA WRITTEN
TO FIF02
SWAP MODE
SW1
WRITE
NO.
SWO
1
L
L
H
H
L
H
L
H
BIG
ENDIAN
LITTLE
ENDIAN
B35-B27
BS-SO
A
D
2
B
C
3
C
B
4
D
A
1
D
A
2
C
B
3
B
C
4
A
D
1
C
B
2
D
A
3
A
D
4
B
C
1
B
C
2
A
D
3
D
A
4
C
B
DATA READ FROM FIF02
A35-A27
A26-A1S
A 17-A9
AS-AO
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
Figure S. Port-B Byte Write Cycle Timing for FIF02 (continued)
5.15
22
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
-;~
-:~
elKB
COMMERCIAL TEMPERATURE RANGE
~
-~
HIGH
"
~
'\.'\.'\.'\." r\.'\.'\.'\.'\.'\
wiRB
//////
tENS
ENB / / / / / 1 / / / / / /
tsws ~
SW1,
SWO
BE
S121,
SI20
/~f-
xx)
xxxxx xxxxx
tszs
tSZH
-5C"
tsz
.,...,..
X
cf'DGD~'
EVEN
-
...-
tENS
tENH
~XXXXAY
tSWH
XXX xxX
I
tENH
¥ "//////
" " " " " " "No'J.-Operation
XXXXXXXXXXX
XXXXX)
--
XXXX X.XxJC:: ~xxxxxxxx XXXXXXXXXXXXX XXXXXX
(0,0)
tSZH
NOT (11 1)
XlOo))(
-roo---
NOT (1 1)l1)
tPGS~ ~ltPGH
xxxxxxxXXx
tEN
xxX
..
..
BO-B35
xxxxxxX
I.,
f+-- tA ..==!1
Previous Data )I(
xxxxxxxXXXx KXXXXX
tDIS~
W2(2)
~tA~1
W1\4)
X
NOTES:
1. SIZO = HIGH and SIZ1 = HIGH selects the mail1 register for output on 80-835.
2. Data read from FIF01.
3146 drw 09
DATA SWAP TA8LE FOR FIFO LONG-WORD READS FROM FIF01
DATA WRITTEN TO FIF01
SWAP MODE
DATA READ FROM FIF01
A35-A27
A26-A18
A17-A9
A8-AO
SW1
SWO
A
B
C
D
L
L
A
A
B
C
D
L
H
A
B
C
D
H
A
B
C
D
H
835-827 826-818
817-89
88-80
B
C
D
D
C
B
A
L
C
D
A
B
H
B
A
D
C
Figure 9. Port-8 Long-Word Read Cycle Timing for FIF01
5.15
23
II
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
~
-.~
~
elKB
COMMERCIAL TEMPERATURE RANGE
HIGH
:i~
"'Ie-
~""""I ~"""""
WiRB
ENB
//////
tENS
tENH
/ / / / // / / / / / / /
SW1,
SWO
dDGD~'
xxxxxxxxxxxx
xxxxx
-- --
tSZH
XXXX IX.XX~ -XXXX XXXX)( XXXXXXXXXXXX}c xx x')()()(
tszs
SIZ1,
SIZO ~
xxxxxxxx
- -
~//////
/
No Operation
tSWH
XXXX} XXXX)C XX
BE ~
X
","','
:"(XXXXAY
tsws
tSZH
NOT (1 1 (1)
(0,1)
)((01)"'
" - ' - " ..........,
tPGs,
XXXXXXXXX)c XXX
EVEN
tEN
Litt.le (2) fcBO-B17
Endlan l...::::
NOT (1 1)(1)
tPGH
.lI(
x
X
X
X
X
X
X
X
XXXXXXXXXxxx
I
..
.. 1"
Big
h B18-B35
Endian(2) ~
<
!-tA>(
Read 1
tOISf.-Read 2
Read 1
-tA' Previous Data K
xXXAX
tOIS ~
Read 2
~tA-
-tAPrevious Data
-
3146drw 10
NOTES:
1.
SIZO = HIGH and SIZ1 HIGH selects the mail1 register for output on 80-835.
2.
Unused word 80-817 or 818-835 holds last FIF01 output register data for word-size reads.
=
DATA SWAP TA8LE FOR WORD READS FROM FIF01
DATA READ FROM FIF01
SWAP MODE
DATA WRITTEN TO FIF01
A35-A27
A26-A18
A17-A9
A8-AO
SW1
READ
NO.
81G ENDIAN
817-89
88-80
B
0
C
A
0
B
835-827 826-818
SWO
LITTLE ENDIAN
A
B
C
0
L
L
2
A
C
1
0
A
B
C
0
L
H
2
B
C
A
B
0
A
C
1
A
B
C
0
H
L
2
C
A
0
B
A
C
B
0
A
B
C
0
H
H
2
B
0
A
C
0
B
C
A
1
1
Figure 10. Port-8 Word Read Cycle Timing for FIF01
5.15
24
IDTI23614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKB
EFB
CSB
W/RB ~~~~~~~____+-________~__________~________~~__________~~~-L-'-
ENB
'--'~-'--'F--L.....L........q....1
SW1, ~~~~~~~~
SWO
'-~~'~~~~~~~~~~~~~~~~~~~~~~~~~~~
BE~~~~~I~~~.;--r~~~~'--L~~~~~
S121, ~.~ I-'~:-'"
SI20
B27-B35
NOTES:
1. SIZO = HIGH and SIZ1 = HIGH selects the mail1 register for output on 80-835.
2.
Unused bytes hold last FIF01 output regisger data for byte-size reads.
3146 drw 11
DATA SWAP TABLE FOR BYTE READS FROM FIF01
DATA READ FROM FIFO 1
DATA WRITTEN TO FIFO 1
A35-A27
A
A
A
A
A26-A18
8
8
8
8
A17-A9
C
C
C
C
SWAP MODE
A8-AO
SW1
L
0
L
0
H
0
H
0
READ
NO.
SWO
L
H
L
H
BIG
ENDIAN
LITTLE
ENDIAN
B35-B27
B8-BO
1
2
3
4
A
0
0
C
8
A
1
2
3
4
0
C
8
A
A
8
C
0
1
2
3
4
C
0
A
8
8
A
0
C
1
2
3
4
8
A
0
C
C
0
A
8
B
C
Figure 11. Port-B Byte Read Cycle Timing for FIF01
5.15
25
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
EFA
HIGH
W/RA
MBA
ENA
AD - A3S
PGA,
0001
EVEN
3146 drw 12
NOTE:
1. Read from FIF02 ..
Figure 12. Port-A Read Cycle Timing for FIF02
5.15
26
10T723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 x36 x 2
COMMERCIAL TEMPERATURE RANGE
ClKA
CSA
WRA
MBA
ENA
AO - A35
ClKB
FIF01 Empty
EFB
CSB
lOW
WiRB
lOW
SIZ1,
SIZO
lOW
II
tENS"i::"',
r-:-:tENH
ENB
BO -B35
~~_____W.;. ;. . ;. 1_ _ _ __
~XXXXXXXXX~I'r'7~~PIr"'::I~~XXXX~ft""7~XXXXXX~~II'r"7O~"'7'XXXXX>Ii
Co
150
:l
(J)
I
fr
2
II
100
50
0
0
10
20
30
40
50
60
70
80
f 5 - Clock Frequency - MHz
3146 drw 27
Figure 27
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 27 was taken while simultaneously reading and writing the FIFO on the
IDT723614 with ClKA and ClKS set to fs. All data inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.
Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from Figure 28, the maximum power dissipation (PT) of the IDT723614 can be calculated by:
PT
=Vcc x ICC(f) + I(CL x VOH2 X
fa)
where:
CL
fa
VOH
output capacitance load
switching frequency of an output
output high level voltage
When no reads or writes are occurring on the IDT723614, the power dissipated by a single clock (ClKA or ClKS)
input running at frequency f5 is calculated by:
PT=VCC x f5 x 0.290 mA/MHz
5.15
37
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kil
From Output
Under Test
--.._----_e
30pF(1)
LOAD CIRCUIT
3V
Timing
Input
High-Level
Input
GND
3V
1.5 V
3V
Data,
Enable
Input
GND
tw
3V
Low-Level
Input
GND
1.5 V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Output
Enable
GND
- ""3V
Low-Level
Output _ _j...-..JI
1.5 V
High-Level
Output
1.5 V·
InpUI -t::D}V
In-Phase
Output _ _ _~
-
~:D~V1.5 V
3V
GND
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
3146 drw 28
NOTE:
1. Includes probe and jig capacitance.
Figure 28. Load Circuit and Voltage Waveforms
5.15
38
IDT723614 CMOS SyncBiFIFOTM WITH BUS MATCHING AND BYTE SWAPPING
64 X 36 X 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
723614
Device Type
x
xx
Power
Speed
x
Package
x
Process/
Temperature
Range
BLANK
Commercial (ODC to +70DC)
PF
PQF
Thin Quad Flat Pack
Plastic Quad Flat Pack
15
20
30
}
L
Low Power
723614
64 x 36 x 2 SyncBiFIFO
Commercial Only
Clock Cycle Time (elK)
Speed in Nanoseconds
3146 drw 29
5.15
39
~®
IDT723622
IDT723632
IDT723642
CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2,
1024 x 36 x 2
Integrated Device Technology, Inc.
Advance information for the IOT723622
Final for the 10T723632
Advance information for the IOT723642
•
•
•
•
•
•
•
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control logic
IRA, ORA, AEA, and AFA flags synchronized by ClKA
IRB, ORB, AEB, and AFB flags synchronized by ClKB
Supports clock frequencies up to 67MHz
Fast access times of 11 ns
Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• low-power O.S-Micron Advanced CMOS technology
FEATURES:
• Free-running ClKA and ClKB may be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs buffering data in opposite directions
• Memory storage capacity:
IOT723622-256 x 36 x 2
IOT723632-512 x 36 x 2
IOT723642-1 024 x 36 x 2
• Mailbox bypass register for each FIFO
FUNCTIONAL BLOCK DIAGRAM
-
ClKA
CSA WiRA -
ENA -
MBA
-
-
I--
l~
2
I '5O,.!!!~
-
J
FIF01,
Mail1
Reset
logic
t
Write
Pointer
I
I
I
I
~ Read
Pointer
t
J Status .Flag,
-,
logic
VIFQj
-
.
36
ORB
AEB
--.1
-
I Programmable
FSo
FS1
Ao - A3s
'-
O~.l.--
t
I
t
J
IRA
AFA
::3_
r-..S·6, 1
'-
1'-36
~~R
-wM
256 x 36
512 x 36
1024 x 36
SRAM
E£
I
I
The I0T72362217236321723642 is a monolithic, high-speed,
low-power, CMOS Bidirectional Synchronous (clocked) FIFO
memory which supports clock frequencies up to 67MHz and
have read access times as fast as 11 ns. Two independent
I
Mail 1
Register
I
Port-A
Control
logic I -
DESCRIPTION:
Flagi
Bo - 935
' Offset Registers
"
'9
IRF02
ORA
AEA
36
.~
Read
Pointer
-
I S'~~
I
L
-
+
.--~
0.'\-+- '5"*
COl
-Q)
a:
-
-
Mail 2
Register
I
1
IRB
AFB
I
Write
Pointer
256 x 36
512 x 36
1024 x 36
SRAM
-Q)
::3_
*~
-
~
I I
+
---.r
L-
-
: Status .Flag,
logic
I
I I
I I
I
-+- -
-
-
I
":=- -
I
I
I
I
I
I
-
36
FIF02,
Mail2
Reset
logic
L---
--
.....
~
~
Port-B
Control
logic
~
ClKB
CSB
:: W/RB
ENB
-
MBB
3022 drw01
SyncFIFO is a trademark and the lOT logo is a registered trademark of Integrated Device Technology. Inc.
JANUARY 1995
COMMERCIAL TEMPERATURE RANGE
DSC-20S6I1
©1995 Integrated Device Technology, Inc.
5.16
1
IDT723622f723632f723642 CMOS SyncBiFIFOTM
256 x 36 x 2,512 X 36 X 2,1024 X 36 X 2
COMMERC~LTEMPERATURERANGE
DESCRIPTION (CONTINUED)
256/512/1 024x36 dual-port SRAM FIFOs on board each chip
buffer data in opposite directions. Each FIFO has flags to
indicate empty and full conditions and two programable flags
(almost Full and almost Empty) to indicate when a selected
number of words is stored in memory. Communication between each port may bypass the FIFOs via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new
mail has been stored. Two or more devices may be used in
parallel to create wider data paths.
The IDT72362217236321723642 is a synchronous (clocked)
FIFO, meaning each port employs a synchronous interface.
All data transfers through a port are gated to the LOW-toHIGH transition of a port clock by enable signals. The clocks
for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are
arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB)
flags of a FIFO are two-stage synchronized to the port clock
that writes data into its array. The Output Ready (ORA, ORB)
and Almost-Empty (AEA, AEB) flags of a FIFO are two-stage
synchronized to the port clock that reads data from its array.
Offset values for the Almost-Full and Almost-Empty flags of
both FIFOs can be programmed from Port A.
PIN CONFIGURATION
NC
835
834
833
832
GND
831
830
829
828
827
826
Vee
825
824
GND
823
822
821
820
819
818
GND
817
816
Vee
815
814
813
812
GND
NC
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
NC
NC
II
A35
A34
A33
A32
Vee
A31
A30
GND
PQ132-1
A29
A28
A27
A26
A25
A24
A23
GND
A22
Vee
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vee
A12
NC
3022 drw 02
PQF Package
TOP VIEW
NOTES:
1. NC - no internal connection
2. Uses Yamaichi socket IC51-1324-828
5.16
2
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2, 512 X 36 X 2,1024 X 36 X 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
A35
A34
A33
A32
1
2
A31
A30
6
Vee
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
Vee
A21
A20
A19
A18
GND
A17
3
4
GND
5
7
8
9
10
11
12
13
14
15
16
17
B31
B30
B29
B28
B27
B26
Vee
PN120-1
19
20
21
22
23
24
25
A12
30
B25
B24
GND
B23
B22
B21
B20
B19
B18
18
A16
A15
A14
A13
Vee
B35
B34
B33
B32
GND
B17
B16
Vee
B15
B14
B13
B12
26
27
28
29
GND
3022 drw 03
TQFP
TOP VIEW
5.16
3
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2,512 x 36 x 2,1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
Name
110
Description
AO-A35
Port-A Data
I/O
36-bit bidirectional data port for side A.
AEA
Port-A Almost
-Empty Flag
a
(Port A)
Programmable almost-empty flag synchronized to ClKA. It is lOW
when the number of words in FIF02 is less than or equal to the value in the
almost-empty A offset register, X2.
Port-B Almost
-Empty Flag
(Port B)
Port-A Almost
-Full Flag
(Port A)
Port-B Almost
-Full Flag
(Port B)
AEB
AFA
AFB
a
a
a
Programmable almost-empty flag synchronzed to ClKB. It is lOW
when the number of words in FIF01 is less than or equal to the value in the
almost-empty B offset register, X1.
Programmable almost-full flag synchronized to ClKA. It is lOW when
the number of empty locations in FIF01 is less than or equal to the value in
the almost-full A offset register, Y1.
Programmable almost-full flag synchronized to ClKB. It is lOW when
the number of empty locations in FIF02 is less than or equal to the value in
the almost-full B offset register, Y2.
BO - B35
Port-B Data
1/0
ClKA
Port-A Clock
I
ClKA is a continuous clock that synchronizes all data transfers through port A
and can be asynchronous or coincident to ClKB. IRA, ORA, AFA, and AEA
are all synchronized to the lOW-to-HIGH transition of ClKA.
ClKB
Port-B Clock
I
ClKB is a continuous clock that synchronizes all data transfers through port B
and can be asynchronous or coincident to ClKA. IRB, ORB, AFB, and AEB
are synchronized to the lOW-to-HIGH transition of ClKB.
CSA
Port-A Chip
Select
I
CSA must be lOW to enable to lOW-to-HIGH transition of ClKA to read or
write on port A. The AO-A35 outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port-B Chip
Select
I
CSB must be lOW to enable a lOW-to-HIGH transition of ClKB to read or
write data on port B. The BO- B35 outputs are in the high-impedance state
when CSB is HIGH.
ENA
Port-A Enable
I
ENA must be HIGH to enable a lOW-to-HIGH transition of ClKA to read or
write data on port A.
ENB
Port-B Enable
I
ENB must be HIGH to enable a lOW-to-HIGH transition of ClKB to read or
write data on port B.
FS1,
FSO
Flag Offset
Selects
I
The lOW-to-HIGH transition of a FIFO's reset input latches the values of FSO
and FS1. If either FSO or FS1 is HIGH when a reset input goes HIGH, one
of the three preset values is selected as the offset for the FIFOs almost-full
and almost-empty flags. If both FIFOs are reset simultaneously and both FSO
and FS1 are lOW when RST1 and RST2 go HIGH, the first four writes to
FIF01 almost empty offsets for both FIFOs.
IRA
Input-Ready
Flag
a
(Port A)
IRA is synchronized to the lOW-to-HIGH transition of ClKA. When IRA is
lOW, FIF01 is full and writes to its array are disabled. IRA is set lOW
when FIF01 is reset and is set HIGH on the second lOW-to-HIGH transition
of ClKA after reset.
Input-Ready
Flag
(Port B)
IRB
MBA
Port-A Mailbox
Select
a
I
36-bit bidirectional data port for side B.
IRB is synchronized to the lOW-to-HIGH transition of ClKB. When IRB is
lOW, FIF02 is full and writes to its array are disabled. IRB is set lOW when
FIF02 is reset and is set HIGH·on the second lOW-to-HIGH transition of
ClKB after reset.
A HIGH level on MBA chooses a mailbox register for a port-A read or
write operation. When the AO-A35 outputs are active, a HIGH level on MBA
selects data from the mail2 register for output and a lOW level selects FIF02
output-register data for output.
5.16
4
II
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2,512 X 36 X 2,1024 X 36 X 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CO NT.)
Symbol
Name
I/O
MBB
Port-B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port-B read or
write operation. When the BO-B35 outputs are active, a HIGH level on
MBB selects data from the mail1 register or output and a lOW level selects
FIF01 output-register data for output.
MBF1
Mail1 Register
Flag
a
MBF1 is set lOW by a lOW-to-HIGH transition of ClKA that writes data
to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is
lOW. MBF1 is set HIGH by a lOW-to-HIGH transition of ClKB when a port-B
read is selected and MBB is HIGH. MBF1 is set HIGH when FIF01 is reset.
MBF2
Mail2 Register
Flag
a
MBF2 is set lOW by a lOW-to-HIGH transition of ClKB that writes data to the
mail2 register. Writes to the mail2 register are inhibited while MBF2 is lOW.
MBF2 is set HIGH by a lOW-to-HIGH transition of ClKA when a port-A read is
selected and MBA is HIGH. MBF2 is also set HIGH when FIF02 is reset.
ORA
Output-Ready
Flag
a
(Port A)
ORA is synchronized to the lOW-to-HIGH transition of ClKA. When ORA is
lOW, FIF02 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIF02 when ORA is HIGH. ORA is
forced lOW when FIF02 is reset and goes HIGH on the third lOW-to-HIGH
transition of ClKA after a word is loaded to empty memory.
Output-Ready
Flag
(Port B)
RST1
FIF01 Reset
I
To reset FIF01, four lOW-to-HIGH transitions of ClKA and four lOW-to-HIGH
transitions of ClKB must occur while RST1 is lOW. The lOW-to-HIGH transition
of RST1 latches the status of FSO and FS1 for AFA and AEB offset selection.
FIF01 must be reset upon power up before data is written to its RAM.
RST2
FIF02 Reset
I
To reset FIF02, four lOW-to-HIGH transitions of ClKA and four lOW-to-HIGH
transitions of ClKB must occur while RST2 is lOW. The lOW-to-HIGH transition
of RST2 latches the status of FSO and FS1 for AFB and AEA offset selection.
FIF02 must be reset upon power up before data is written to its RAM.
W/RA
Port-A Write/
Read Select
I
A HIGH selects a write operation and a lOW selects a read operation on port A
for a lOW-to-HIGH transition of ClKA. The AO-A35 outputs are in
the HIGH impedance state when WiRA is HIGH.
W/RB
Port-B Write/
Read Select
I
A lOW selects a write operation and a HIGH selects a read operation on port B
for a lOW-to-HIGH transition of ClKB. The BO-B35 outputs are in the HIGH
impedance state when W/RB is lOW.
ORB
a
Description
ORB is synchronized to the lOW-to-HIGH transition of ClKB. When ORB
is lOW, FIF01 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIF01 when ORB is HIGH. ORB is forced lOW
when FIF01 is reset and goes HIGH on the third lOW-to-HIGH transition of ClKB
after a word is loaded to empty memory.
5.16
5
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2, 512 X 36 X 2,1024 X 36 X 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol
Rating
Vce
Supply Voltage Range
W2)
VO(2)
Commercial
Unit
-0.5 to 7
V
Input Voltage Range
-0.5 to Vee+0.5
V
Output Voltage Range
-0.5 to Vee+0.5
V
11K
Input Clamp Current (VI < 0 or VI > Vee)
±20
mA
10K
±50
mA
lOUT
=< 0 or Vo > Vee)
Continuous Output Current (Vo =0 to Vec)
±50
mA
Icc
Continuous Current Through Vee or GND
±400
mA
TA
Operating Free Air Temperature Range
Ot070
°C
TSTG
Storage Temperature Range
-65 to 150
°C
Output Clamp Current (Vo
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
II
Min. Max. Unit
4.5
5.5
V
Vee
Supply Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
0.8
IOH
High-Level Output Current
-4
mA
IOL
Low-Level Output Current
8
mA
TA
Operating Free-Air
Temperature
70
°C
V
2
0
V
5.16
6
IDT7236221723632f723642 CMOS SyncBiFIFOTM
256 X 36 x 2,512 X 36 X 2,1024 X 36 X 2
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
IDT723622
IDT723632
IDT723642
Commerical
tA
Parameter
Test Conditions
Min.
2.4
=15, 20, 30 ns
Typ.(1)
Max.
Unit
VOH
Vee = 4.5V,
IOH = -4 rnA
VOL
Vee = 4.5 V,
IOL = 8 rnA
0.5
V
III
Vee = 5.5 V,
VI = Vee or 0
±5
~A
ILO
Vee = 5.5 V,
Vo = Vee or 0
±5
~A
lee
illee(2)
Vee = 5.5 V,
VI = Vee -0.2 V or 0
Vee = 5.5 V,
One Input at 3.4 V,
Other Inputs at Vee or GND
V
400
GSA=VIH
AO-A35
0
0
GSB =VIH
BO-B35
GSA = VIL
AO-A35
GSB =VIL
BO-35
~A
rnA
1
1
All Other Inputs
1
GIN
VI=O,
f = 1 MHz
4
pF
GOUT
VO=O,
f = 1 MHZ
8
pF
NOTES:
1. All typical values are at Vee == 5V, TA == 25°e.
2. This is the supply current when each input is at least one of the specified TTL voltage levels rather than OV or Vee.
5.16
7
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 X 36 X 2,512 X 36 X 2,1024 X 36 X 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
723622-15
723622-20
723622-30
723632-15
723632-20
723632-30
723642-15
Symbol
Parameter
Min.
fs
Clock Frequency, ClKA or ClKB
tClK
Clock Cycle Time, ClKA or ClKB
15
tClKH
Pulse Duration, ClKA or ClKB HIGH
6
tClKl
Pulse Duration, ClKA and ClKB lOW
6
Setup Time, AO-A35 before ClKA; and BO-B35
before ClKB;
4
tDS
Max.
723642-20
Min.
66.7
tENS
Setup Time, CSA, W/RA, ENA, and MBA before
ClKA;; CSB, W/RB, ENB, and MBB before ClKB;
tASTS
Setup Time, RST1 or RST2 lOW before ClKA;
orClKB;(1)
Max.
723642-30
Min.
50
20
Max.
Unit
33.4
MHz
30
ns
8
10
ns
8
10
ns
5
6
ns
4.5
5
6
ns
5
6
7
ns
tFSS
Setup Time, FSO and FS1 before RST1 and RST2
HIGH
7.5
8.5
9.5
ns
tDH
Hold Time, AO-A35 after ClKA; and BO-B35 after
ClKB;
1
1
1
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after ClKA;;
CSB, W/RB, ENB, and MBB after ClKB;
1
1
1
ns
tASTH
Hold Time, RST1 or RST2 lOW after ClKA; or
ClKB;(1)
4
4
5
ns
Hold Time, FSO and FS1 after RST1 and RST2 HIGH
tFSH
tSKEW1(2) Skew Time, between ClKA; and ClKB; for ORA,
ORB, IRA, and IRB
tSKEW2(2) Skew Time, between ClKA; and ClKB; for AEA,
AEB, AFA, and AFB
2
3
3
ns
7.5
9
11
ns
12
16
20
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between
cycle.
2.
5.16
ClKA cycle and ClKS
8
II
IOTI23622fl236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2,1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL 30 pF
=
723632-15
Symbol
Parameter
723632-20
723632-30
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tA
Access Time, CLKAi to AO-A35 and CLKBi
to BO-B35
3
11
3
13
3
15
ns
tPIR
Propagation Delay Time, CLKAi to IRA and
CLKBito IRB
2
8
2
10
2
12
ns
tpOR
Propagation Delay Time, CLKA i to ORA and
CLKBi to ORB
1
8
1
10
1
12
ns
tPAE
Propagation Delay Time, CLKAi to AEA and
CLKBi to AEB
1
8
1
10
1
12
ns
tPAF
Propagation Delay Time, CLKAito AFA and
and CLKBi to AFB
1
8
1
10
1
12
ns
tPMF
Propagation Delay Time, CLKAito MBF1 LOW or
MBF2 HIGH and CLKBi to MBF2 LOW or MBF1
HIGH
0
8
0
10
0
12
ns
tPMR
Propagation Delay Time, CLKAito BO-B35(1) and
CLKBi to AO-A35(2)
3
13.5
3
15
3
17
ns
tMDV
Propagation Delay Time, MBA to AO-A35 valid and
MBB to BO-B35 Valid
3
11
3
13
3
15
ns
tPRF
Propagation Delay Time, RST1 LOW to AEB LOW,
AFA HIGH, and MBF1 HIGH, and RST2 LOW to
AEA LOW, AFB HIGH, and MBF2 HIGH
1
15
1
20
1
30
ns
tEN
Enable Time, CSA and W/RA LOW to AO-A35 Active
and CSB LOW and W/RB HIGH to BO-B35 Active
2
12
2
13
2
14
ns
tDIS
Disable Time, CSA or W/RA HIGH to AO-A35 at
high impedance and CSB HIGH or W/RB LOW
to BO-B35 at HIGH impedance
1
8
1
12
1
11
ns
NOTES:
1. Writing data to the mail1 register when the
2. Writing data to the mail2 register when the
BO-B35 outputs are active and MBB is HIGH.
AO-A35 outputs are active and MBA is HIGH.
5.16
9
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2,512 x 36 x 2,1024 X 36 X 2
COMMER~ALTEMPERATURERANGE
during the LOW-to-HIGH transition of its reset input. For
example, to load the preset value of 64 into Xi and Yi, FSO
and FS1 must be HIGH when FIF01 reset (RST1) returns
HIGH. Flag-offset registers associated with FIF02 are loaded
with one of the preset values in the same way with FIF02 reset
(RST2). When using one of the preset values for the flag
offsets, the FIFOs can be reset simultaneously or at different
times.
To program the Xi, X2, Y1, and Y2 registers from port A,
both FIFOs should be reset simultaneously with FSO and FS1
LOW during the LOW-to-HIGH transition of the reset inputs.
After this reset is complete, the first four writes to FIF01 do not
store data in RAM but load the offset registers in the order Y1,
Xi, Y2, X2. The port A data inputs used by the offset registers
are (A7-AO), (A8-AO), or (A9-AO) for the IDT723622,
IDT723632, or IDT723642, respectively. The highest numbered in~ut is used as the most significant bit of the binary
number In each case. Valid programming values for the
registers ranges from 1 to 252 for the I DT723622; 1 to 508 for
the IDT723632; and 1 to 1020 for the IDT723642. After all the
offset registers are programmed from port A, the port-B inputready flag (IRB) is set HIGH, and both FIFOs begin normal
operation.
SIGNAL DESCRIPTION
RESET
The FIFO memories of the IDT72362217236321723642
are reset separately by taking their reset (RST1, RST2) inputs
LOWfor at least four port-A clock (CLKA) and four port-B clock
(CLKB) LOW-to-HIGH transitions. The reset inputs can switch
asynchronously to the clocks. A FIFO reset initializes the
internal read and write pointers and forces the input-ready flag
(IRA, IRB) LOW, the output-ready flag (ORA, ORB) LOW, the
almost-empty flag (AEA, AEB) LOW, and the almost-full flag
(AFA, AFB) HIGH. Resetting a FIFO also forces the mailbox
flag (MBF1, MBF2) of the parallel mailbox register HIGH. After
a FIFO is reset, its input-ready flag is set HIGH after two clock
cycles to begin normal operation. A FIFO must be reset after
power up before data is written to its memory.
.
A LOW-to HIGH transition on a FIFO reset (RST1, RST2)
Input latches the value of the flag-select (FSO, FS1) inputs for
choosing the almost-full and almost-empty offset programming method (see almost-empty and almost-full flag offset
programming below).
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING
Four registers in the IDT72362217236321723642 are used
to hold the offset values for the almost-empty and almost-full
flags. The port-B almost-empty flag (AEB) offset register is
labeled Xi and the port-A almost-empty flag (AEA) offset
register is labeled X2. The port-A almost-full flag (AFA) offset
register is labeled Y1 and the port-B almost-full flag (AFB)
offset register is labeled Y2. The index of each register name
corresponds to its FIFO number. The offset registers can be
loaded with preset values during the reset of a FIFO or they
can be programmed from port A (see Table 1 ) .
To load a FIFO almost-empty flag and almost-full flag
offset registers with one of the three preset values listed in
Table1, at least one of the flag-select inputs must be HIGH
FIFO WRITE/READ OPERATION
The state of the port-A data (AO-A35) outputs is controlled
~ port-A chip select (CSA) and port-A write/read select (W/
RA). The AO-A35 outp~ts are in the High-impedance state
wh~n either CSA or W/RA is ~GH. The AO-A35 outputs are
active when both CSA and W/RA are LOW.
Data is loaded into FIF01 from the AO-A35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, WiRA is
HIGH, ENA is HIGH, MBA is LOW, and IRA is HIGH. Data is
read from FIF02 to the AO-A35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, WiRA is LOW, ENA is
HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO
reads and writes on port A are independent of any concurrent
X2 AND Y2 REGISTERS(2)
FS1
FSO
RST1
RST2
X1 AND Y1 REGISTERS(l)
H
H
t
X
64
X
H
H
X
t
X
64
H
L
t
X
16
X
H
L
X
t
X
16
L
H
t
X
8
X
L
H
X
X
8
L
L
t
t
t
Programmed from port A
Programmed from port A
NOTES:
1. X1 register holds the offset for AE8; Y1 register holds the offset for AFA.
2. X2 register holds the offset tor AEA; Y2 register holds the offset for AFB.
Table 1. Flag Programming
5.16
10
II
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2,1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
port-B operation.
The port-B control signals are identical to those of port A
with the exception that the port-B writelread select (W/RB) is
the inverse of the port-A writelread select (wiRA). The state
of the port-B data (BO-B35) outputs is controlled by the portB chip select (CSB) and port-B writelread select (W/RB). The
BO-B35 outputs are in the high-impedance state when either
CSB is HIGH or W/RB is lOW. The BO-B35 outputs are active
when CSS is lOW and W/RB is HIGH.
Data is loaded into FIF02 from the BO-B35 inputs on a
lOW-to-HIGH transition of ClKB when CSB is lOW, W/RB is
lOW, ENS is HIGH, MBB is lOW, and IRB is HIGH. Data is
read from FIF01 to the BO-B35 outputs by a lOW-to-HIGH
transition of CLIc.
:J
en
Q.
150
Vee =4.5 V
I
fr0
II
100
50
o
o
10
20
30
40
50
60
70
3022 drw 18
fS - Clock Frequency - MHz
CALCULATING POWER DISSIPATION
Figure 17.
The ICC(f) current for the graph in Figure 17 was taken while simultaneously reading and writing a FIFO on the
IOT723622/10T723632/10T723642 with ClKA and ClKB set to f8. All data inputs and data outputs change state during
each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero
capacitance load. Once the capacitance load per data-output channel and the number of IOT723622110T7236321
IOT62342 inputs driven by TIL HIGH levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 17, the maximum power dissipation (PT) of the IOT723622/10T723632110T723642 may
be calculated by:
PT = VCC x [ICC(f) + (N x illCC x dc)] + I(Cl X VCC2 X fO)
where:
number of inputs driven by TIL levels
N
increase in power supply current for each input at a TIL HIGH level
ilICC=
dc
duty cycle of inputs at a TIL HIGH level of 3.4 V
output capacitance load
Cl
fO
switching frequency of an output
When no read or writes are occurring on the I OT723632, the power dissipated by a single clock (ClKA or ClKB) input
running at frequency fS is calculated by:
PT = Vcc x f8 x 0.184 mA/MHz
5.16
24
IDT72362217236321723642 CMOS SyncBiFIFOTM
256 x 36x 2, 512 x 36 x 2,1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kn
From Output - - e _ - - - - _ _ e
Under Test
30
pF(l)
680n
PROPAGATION DELAY
LOAD CIRCUIT
GND
3V
Timing
Input
3V
High-Level
Input
GND
1.5 V
Data,
Enable
Input
GND
tw
3V
3V
Low-Level
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
GND
- ""3V
Low-Level
Output - - t - - "
1.5 V
High-Level
Output
1.5 V
tPD}
In-Phase
Output _ _ _--'
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
3V
~1~
. V-
Input - {1.5 V
tPD~
- - - - -......
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
GND
1.5 V
3022 drw20
NOTE:
1._ Includes probe and jig capacitance.
Figure 18. Load Circuit and Voltage Waveforms.
5.16
25
10T72362217236321723642 CMOS SyncBiFIFOTM
256 x 36 x 2,512 x 36 x 2,1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
xxxxxx
x
--2QS...
x
Device Type
Power
Speed
Package
x
Process/
Temperature
Range
Y
BLANK
L..-_ _ _ _ _ _ _ _ _---1
L..-_ _ _ _ _ _ _ _ _ _ _ _ _~
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
15
20
30
L
Commercial (O°C to +70°C)
Thin Quad Flat Pack
Plastic Quad Flat Pack
PF
' - - - - - - - - l PQF
}
Commercial Only
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Low Power
723622 256 x 36 Synchronous BiFI Fa
723632 512 x 36 Synchronous BiFIFO
723642 1024 x 36 Synchronous BiFIFO
3022 drw 22
II
I
5.16
26
G
IDT72401
IDT72402
IDT72403
IDT72404
CMOS PARALLEL FIFO
64 x 4-BIT AND 64 x 5-BIT
Integrated Device Tec.hnology, Inc..
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
First-In/First-Out Dual-Port memory
64 x 4 organization (IDT72401/03)
64 x 5 organization (IDT72402/04)
I DT72401/02 pin and functionally compatible with
MM167401/02
RAM-based FI FO with low fall-through time
Low-power consumption
- Active: 175mW (typ.)
Maximum shift rate - 45MHz
High data output drive capability
Asynchronous and simultaneous read and write
Fully expandable by bit width
Fully expandable by word depth
I DT72403/04 have Output Enable pin to enable output
data
High-speed data communications applications
High-performance CMOS technology
Available in CERDIP, plastiC DIP and SOIC
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous highperformance First-In/First-Out memories organized 64 words
by 4 bits. The IDT72402 and IDT72404 are asynchronous
high-performance First-In/First-Out memories organized as
64 words by 5 bits. The IDT72403 and IDT72404 also have an
Output Enable (OE) pin. The FIFOs accept 4-bit or 5-bit data
at the data input (DO-D3, 4). The stored data stack up on a firstin/first-out basis.
A Shift Out (SO) signal causes the data at the next to last
word to be shifted to the output while all other data shifts down
one location in the stack. The Input Ready (IR) signal acts like
a flag to indicate when the input is ready for new data
(IR =HIGH) or to signal when the FIFO is full (IR = LOW). The
Input Ready signal can also be used to cascade multiple
devices together. The Output Ready (OR) signal is a flag to
indicate that the output remains valid data (OR = HIGH) or to
indicate that the FIFO is empty (OR = LOW). The Output
Ready can also be used to cascade multiple devices together.
Width expansion is accomplished by logically ANDing the
Input Ready (IR) and Output Ready (OR) signals to form
composite signals.
Depth expansion is accomplished by tying the data inputs
of one device to the data outputs of the previous device. The
Input Ready pin of the receiving device is connected to the
Shift Out pin of the sending device and the Output Ready pin
of the sending device is connected to the Shift In pin of the
receiving device.
Reading and writing operations are completely asynchronous allowing the FIFO to be used as a buffer between two
digital machines of widely varying operating frequencies. The
45MHz speed makes these FIFOs ideal for high-speed
communication and controller applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
SI
WRITE POINTER
IR
WRITE MULTIPLEXER
DO-3
MEMORY
ARRAY
D4
(IDT72402
and IDT72404)
MR
MASTER
RESET
READ MULTIPLEXER
OE (IDT72403 and
IDT72404)
00-3
04 (lDT72402 and
IDT72404)
SO
READ POINTER
OR
2747 dlWOl
The lOT logo Is a registered trademark of tntegrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1994
DSC-2011/5
©1995 Integrated Device Technology, Inc.
5.17
1
10T72401, 10T72402, 10T72403, 10T72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
10T72401n0T72403
NC/OE(l)
Vcc
OR
00
01
02
03
MR
IR
SI
00
01
02
03
04
GNO
so
IR
SI
Do
01
02
03
GNO
OIP/SOIC
TOP VIEW
(10T72404 Only)
10T72402ll0T72404
NC/OE(2)
2747 drw02
Vcc
SO
OR
00
01
02
03
04
MR
OE
NC
IR
'SI
Do
01
02
03
04
GNO
2747 drw 03
OIP/SOIC
TOP VIEW
Vcc
NC
SO
OR
00
01
02
03
04
MR
2747 drw04
CERPACK
TOP VIEW
NOTES:
1. Pin 1: NC - No Connection IDT72401, QE - IDT72403
2. Pin 1: NC - No Connection IDT72402,QE - IDT72404
ABSOLUTE 'MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Commercial
Military
Unit
Symbol
Min.
Typ.
Max.
Unit
VTERM
Terminal Voltage
with Respect
toGNO
-0.5 to +7.0
-0.5 to +7.0
V
Vee
Mil. Supply Voltage
Parameter
4.5
5.0
5.5
V
Vee
Com'l. Supply Voltage
4.5
5.0
5.5
V
Supply Voltage
0
0
0
V
TA
Operating Temp.
o to +70
GNO
-55 to +125
°C
VIH
Input High Voltage
2.0
V
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
-
VIL(l)
Input High Voltage
-
O.S
V
TSTG
lOUT
Storage Temp.
OC Output
Current
-55 to +125
-65 to +150
50
50
°C
rnA
-
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE:
2747tbiOl
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, f
Parameter(l)
II
2747tbl02
= 1.0MHz)
Max.
Unit
CIN
Input Capacitance
VIN = OV
5
pF
COUT
Output Capacitance
VOUT= OV
7
Symbol
Conditions
NOTE:
1. This parameter is sampled and not 100% tested.
pF
2747 tbl 03
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc
Symbol
=5.0V ± 10%, TA =O°C to +70°C; Military:
Parameter
Vcc
=5.0V ± 10%, TA =-55°C to +125°C)
Test Conditions
Min.
IlL
Low-Level Input Current
Vee = Max., GNO ~ VI ~ Vee
-10
IIH
High-Level Input Current
Vee = Max., GNO ~ VI ~ Vee
VOL
Low-I evel Output Voltage
Vee = Min., 10L = SmA
VOH
High-Level Output Voltage
Vee = Min., 10H = -4mA
2.4
10S(1)
Output Short-Circuit Current
Vee = Max., Vo = GNO
-20
1HZ
Off-State Output Current
Vee = Max., Vo = 2.4V
ILZ
lee(2,3)
(10T72403 and 10T72404)
Vee = Max., Vo = O.4V
Supply Current
Vee = Max., f = 10MHz
-
-20
I Com'l.
I Military
-
Max.
Unit
-
~
10
JlA
0.4
V
-110
V
rnA
20
~
-
JlA
35
45
rnA
rnA
NOTES:
2747 tbl
1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.
2. Icc measurements are made with outputs open. QE is HIGH for IDT72403172404.
3 For frequencies greater than 10MHZ, Icc =35mA + (1.5mA x [f - 1OM Hz]) commercial, and Icc =45mA + (1.5mA x [f - 1OM Hz]) military.
5.17
2
04
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 X 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONDITIONS
(Commercial: Vee =5.0V ± 10%, TA =ODC to +70DC; Military: Vee =5.0V ± 10%, TA =-55 DC to +125DC)
Commercial
Symbol
Parameters
IDT72401 L45
IDT72402L45
IDT72403L45
IDT72404L45
IDT72401 L35
IDT72402L35
IDT72403L35
IDT72404L35
Military and Commercial
IDT72401 L25 IDT72401L15
IDT72402L25 IDT72402L15
IDT72403L25 IDT72403L15
IDT72404L25 IDT72404L15
IDT72401 L 10
IDT72402L10
IDT72403L10
IDT72404L10
Min.
Max.
Min.
Max.
Min.
Min.
9
-
11
11
Figure
Min.
tSIH(l)
Shift in HIGH Time
2
9
Max.
tSIL
Shift in LOW Time
2
11
tlOS
Input Data Set-up
2
0
tlOH
Input Data Hold Time
2
13
tSOH(l)
Shift Out HIGH Time
5
9
tSOL
Shift Out LOW Time
5
11
tMRW
Master Reset Pulse
8
20
tMRS
Master Reset Pulse to SI
8
10
-
tSIR
Data Set-up to IR
4
3
tHIR
Data Hold from IR
4
tSOR(4)
Data Set-up to OR HIGH
7
25
10
-
10
-
-
3
-
5
13
-
15
0
-
0
-
17
0
15
9
17
25
-
24
0
20
25
0
30
Max.
-
-
Max.
Unit
11
-
ns
30
-
ns
0
-
ns
40
-
ns
11
ns
30
-
35
-
ns
25
-
-
5
-
5
-
ns
20
-
30
-
30
ns
0
-
0
-
0
-
11
24
11
25
25
25
ns
ns
ns
2747 tbl 05
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee =5.0V ± 10%, TA =ODC to +70 DC; Military: Vee =5.0V ± 10%, TA
Commercial
Symbol
Parameters
Figure
Military and Commercial
IDT72401 L45
IDT72402L45
IDT72403L45
IDT72404L45
IDT72401 L35
IDT72402L35
IDT72403L35
IDT72404L35
IDT72401L25
IDT72402L25
IDT72403L25
IDT72404L25
IDT72401 L 15
IDT72402L15
IDT72403L15
IDT72404L15
IDT72401L10
IDT72402L10
IDT72403L10
IDT72404L10
Min.
Min.
Min.
Min.
Min.
Max.
Shift In Rate
2
-
45
tIRL(l)
Shift In to Input Ready LOW
2
-
18
tIRH(l)
Shift In to Input Ready HIGH
2
18
toUT
Shift Out Rate
5
tORL(l)
Shift Out to Output Ready LOW
5
tORH(l)
Shift Out to Output Ready HIGH
5
-
tiN
=-55 DC to +125 DC)
-
45
18
19
Max.
Max.
-
25
-
15
18
-
21
28
35
-
25
18
-
19
34
-
35
20
20
tOOH
Output Data Hold (Previous Word)
5
5
-
5
-
5
-
toos
Output Data Shift (Next Word)
5
19
Data Throughput or "Fall-Through"
Master Reset to OR LOW
8
-
34
tMRORL
tMRIRH
Master Reset to IR HIGH
8
-
20
tPT
tMRQ
Master Reset to Data Output LOW
8
-
-
tOOE(3)
Output Valid from Q.E LOW
9
tHZOE(3.4j
Output High-Z from Q.E HIGH
9
-
4,7
30
25
25
12
-
20
12
Max.
35
5
35
-
40
40
15
Max.
Unit
10
MHz
40
ns
45
ns
10
MHz
40
ns
-
55
ns
-
5
-
ns
40
55
ns
-
65
-
65
ns
35
-
40
ns
35
-
35
-
40
ns
25
-
35
-
40
ns
20
ns
25
-
35
15
-
30
12
-
30
ns
34
28
28
20
15
40
35
tIPH(2,4)
Input Ready Pulse HIGH
4
9
-
9
-
11
-
11
-
11
-
ns
tOPH(2.4)
Ouput Ready Pulse HIGH
7
9
-
9
-
11
-
11
-
11
-
ns
NOTES:
2747 tbl 06
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of O.1IIF directly between Vee and GND with very short lead length is recommended.
2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of
like speed grades.
3. IDT72403 and IDT72404 only.
4. Guaranteed by design but not currently tested.
5.17
3
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64
x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
SV
GNDto 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.SV
Output Reference Levels
Output Load
1.SV
OUTPUT
See Figure 1
UK
n
2747 tbl 07
2747 drw 06
ALL INPUT PULSES:
3.0V
or equivalent circuit
---~~..._ _ _ _ I
GND ---=';';;"1
<3ns
Figure 1. AC Test Load
<3ns
"Including scope and jig
2747 drw 05
SIGNAL DESCRIPTIONS
OUTPUTS:
INPUTS:
DATA OUTPUT (aO-3, 4)
Data Output lines. The IDT72401 and IDT72403 have a 4bit data output. The IDT72402 and IDT72404 have a 5-bit data
output.
DATA INPUT (00-3, 4)
Data input lines. The IDT72401 and IDT72403 have a 4-bit
data input. The IDT72402 and IDT72404 have a 5-bit data
input.
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When
SI is HIGH, data can be written to the FIFOvia the DO-3,4Iines.
SHIFT OUT (SO)
Shift Out controls the output of data of the FIFO. When SO
is HIGH, data can be read from the FIFO via the Data Output
(OO-3,4) lines.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within.
Upon power up, the FIFO should be cleared with a Master
Reset. Master Reset is active LOW.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input
data to be written to it. When I R is LOW the FI FO is unavailable
for new input data. Input Ready is also used to cascade many
FIFOs together, as shown in Figures 10 and 11 in the Applications section.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (00-3,4) contains
valid data. When OR is LOW, the FIFO is unavailable for new
output data. Output Ready is also used to cascade many
FIFOs together, as shown in Figures 10 and 11.
FUNCTIONAL DESCRIPTION
These 64 x 4 and 64 x 5 FIFOs are designed using a dual
port RAM architecture as opposed to the traditional shift
register approach. This FIFO architecture has a write pointer,
a read pointer and control logic, which allow simultaneous
read and write operations. The write pointer is incremented by
the falling edge of the Shift In (SI) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
FIFO Reset
The FIFO must be reset upon power up using the Master
Reset (MR) signal. This causes the FIFO to enter an empty
state, signified by Output Ready (OR) being LOW and Input
Ready (IR) being HIGH. In this state, the data outputs (00-3,
4) will be LOW.
Data Input
Data is shifted in on the LOW-to-HIGH transition of Shift In
(SI). This loads input data into the first word location of the
FIFO and causes Input Ready to go LOW. On the HIGH-toLOW transition of Shift In, the write pointer is moved to the next
word pOSition and Input Ready (IR) goes HIGH, indicating the
readiness to accept new data. If the FIFO is full, Input Ready
will remain LOW until a word of data is shifted out.
OUTPUT ENABLE (OE) (IDT72403 AND IDT72404 ONLY)
Output enable is used to read FIFO data onto a bus. Output
Enable is active LOW.
5.17
4
II
IDT72401,IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64
x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Data Output
Fall-Through Mode
Data is shifted out on the HIGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be
advanced to the next word location. If data is present, valid
data will appear on the outputs and Output Ready (OR) will
go HIGH. If data is not present, Output Ready will stay
LOW indicating the FIFO is empty. The last valid word read
from the FIFO will remain at the FIFOs output when it is empty.
When the FIFO is not empty, Output Ready (OR) goes LOW
on the LOW-to-HIGH transition of Shift Out. Previous data
remains on the output until the HIGH-to-LOW transition of
Shift Out (SO).
The FIFO operates in a fall-through mode when data gets
shifted into an empty FIFO. After a fall-through delay the data
propagates to the output. When the data reaches the output,
the Output Ready (OR) goes HIGH. Fall-through mode also
occurs when the FIFO is completely full. When data is shifted
out of the full FIFO, a location is available for new data. After
a fall-through delay, the Input Ready goes HIGH. If Shift In is
HIGH, the new data can be written to the FIFO.
Since these FIFOs are based on an internal dual-port RAM
architecture with separate read and write pointers, the fallthrough time (tPT) is one cycle long. A word may be written
into the FI FO on a clock cycle and can be accessed on the next
clock cycle.
TIMING DIAGRAMS
SHIFT IN
INPUT READY
INPUT DATA
2747 drw07
Figure 2. Input Timing
SHIFTIN~
INPUT READY
INPUT
~
(4~
l
-..:..:...----+\.--~2 (3)
~ _ _ _-l(w5)/~------
.....---l~~\~_____________________________________
- ________~, ______ J~
_____ _
DATA~ STABLE DATA
2747 drwoa
NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the first word.
3. Input Ready goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FI FO is ready for the next word.
6. If the FIFO is full then the Input Ready remains LOW.
7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).
Figure 3. The Mechanism of Shifting Data Into the FIFO
5.17
5
IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
(2)
SHIFT OUT
~-----}~,------------------------------------(3)
(5)
SHIFT IN
INPUT READY
2747 drw09
NOTES:
FIFO is initially full.
Shift Out pulse is applied.
Shift In is held HIGH.
As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH).
1.
2.
3.
4.
5.
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
II
~-----1/foUT-----t~t--------1/foUT----"""'~
SHIFT OUT
OUTPUT READY
OUTPUTDATA __-+~~~
__~I~O£~Q£~Dlr~~~~__~~~~~~~~___C_-D_A_T_A____
(1)
2747 drw 10
NOTES:
1. This data is loaded consecutively A, 8, C.
2. Data is shifted out when Shift Out makes a HIGH to LOW transition.
Figure 5. Output Timing
(4~
SHIFTOUT(7) ~
-;OUTPUT READY
OUTPUT DATA
l
I
\-------I.~~(3)
(5),r-------
______ _____ _
~?
~
A-DATA
l~
B-DATA
------------------------------------------'~~~'~---------27-47-d-rw-1-1
NOTES:
Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
Shift Out goes HIGH causing the next step.
Output Ready goes LOW.
The read pointer is incremented.
Output Ready goes HIGH indicating that new data (8) is now available at the FIFO outputs.
If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs.
Shift Out pulses applied when Output Ready is LOW will be ignored.
1.
2.
3.
4.
5.
6.
7.
Figure 6. The Mechanism of Shifting Data Out of the FIFO
5.17
6
IDT72401, 1DT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN
SHIFT OUT
---1
\~------------------------------------------------------------------------------------
----i~k
WAVEFORM
22 )
O.5V
[-~--L-~F-===2S
1.5V
I\.
t
VOL
1';,~-1==~t=
VOH
~1
1.5V
O.5V
NOTES:
2748 drw 14
1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
2. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
Figure 12. Enable and Disable
5.18
9
10172413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APPLICATIONS
COMPOSITE
INPUT
READY
SHIFT IN
OE AF/E
HF
IR
SI
Do
D1
D2
D3
D4
MR
HF
IR
SI
Do
D1
D2
D3
D4
OE AF/E
SO
OR
00
01
02
03
04
MR
HF
IR
SI
Do
D1
D2
D3
D4
OE AF/E
SO
OR
00
01
02
03
04
MR
so
SHIFT OUT
OR
00
01
02
03
04
COMPOSITE
OUTPUT
READY
2748 drw 15
NOTE:
1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready
flags. This requirement is due to the different fall-through times of the FIFOs.
Figure 13. 64 x 15 FIFO with 10172413
SYSTEM 1
ENBLSI
TWO
IDD2413
64 x 8
SI
SO
IR
OR
SYSTEM 2
10 ROY
ALMOST-FULU
EMPTY
INTERRUPT
INTERRUPT
HALF-FULL FLAG
2748 drw 16
NOTE:
1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.
Figure 14. Application for 10172413 for Two Asynchronous Systems
5.18
10
IDT72413
CMOS PARALLEL 64
x 5-BIT FIFO WITH
FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OR
SO
SHIFT IN
INPUT READY
I---~
OR
SO
SI
IR
00
01
02
03'-'---'"
04
DATAIN{--~
00
01
02
03
04
OUTPUT READY
SHIFT OUT
} DATA OUT
2748 drw 17
MR~""''''''''''''''''''''''-'''''''''''''''''''''''''''''''''''~
NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing
of the devices.
Figure 15. 128 x 5 Depth Expansion
ORDERING INFORMATION
IDT XXXXX
Device Type
x
x
x
x
Power
Speed
Package
Process/
Temperature
Range
Y:lank
~------------~ D
P
SO
45
~------------------~35
25
~--------------------------~ L
1---------------------172413
II
Commercial (O°C to+70°C)
Military (-55°C to+ 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP (600 mils wide)
Plastic DIP (600 mils wide)
Small Outline IC
Com'l. Only
}
Com'l. and Mil
Com'l. and Mil
Shift Fr~quency (fs)
Speed In MHz
Low Power
64 x 5 FIFO
2748 drw 18
5.18
11
(;)
IDT7200L
IDT7201LA
IDT7202LA
CMOS ASYNCHRONOUS FIFO
256
X
9, 512 x 9, 1 K x 9
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1K x 9 organization (IDT7202)
Low power consumption
- Active: 770mW (max.)
-Power-doWn: 2.75mW (max.)
Ultra high speed-12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Pin and functionally compatible with 720X family
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOSTM technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666,
5962-89863 and 5962-89536 are listed on this function.
DESCRIPTION:
The IDT7200!7201!7202 are dual-port memories that load
and empty data on a first-in/first-out basis. The devices use
Full and Empty flags to prevent data overflow and underflow
and expansion logicto allow for unlimited expansion capability
in both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins.
The devices utilizes a 9-bit wide data array to allow for
control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
The IDT7200!7201!7202 are fabricated using IDT's highspeed CMOS technology. They are designed for those
applications requiring asynchronous and simultaneous read/
writes in multiprocessing and rate buffer applications. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(Do-Da)
THREESTATE
BUFFERS
"-./'
DATA OUTPUTS
(Uo-Oa)
A
r----+--~
L-~~J--I--
Xi ----------IL.-~..::;,:.,:....-J_---~
EE
FF
XO/HF
FURT
2679 drw01
The lOT logo Is a Irademark 01 Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DECEMBER 1994
DSC-2000l5
©1995 Integrated Device Technology. Inc.
5.19
IDT7200n201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1 K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
8
w
1
28
08
2
27
04
03
D2
3
26
Os
4
25
06
01
5
Do
6
Xi
7
P28-1,
P28-2,
028-1,
028-3,
E28-2,
S028-3
Vee
24
07
23
FURT
22
RS
FF
8
21
EF
00
9
20
XO/HF
01
10
19
07
02
11
18
06
03
12
17
Os
08
13
16
04
GNO
14
15
R
02
5
29
01
6
28
07
Do
7
27
NC
26
FURT
Xi
8
FF
9
00
11
23
XO/HF
12
22
Q7
02
13
21
06
Unit
V
Operating
Temperature
o to +70
-55 to +125
°C
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output
Current
50
50
mA
CIN
COUT
'-----2679 drw 05
Figure 3. Asynchronous Write and Read Operation
5.19
7
IDT720017201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9
LAST WRITE
IGNORED
WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
FF
2679 drw 06
Figure 4. Full Flag From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
W
EF
DATA OUT
-+----<
2679 drw 07
Figure 5. Empty Flag From Last Read to First Write
~---------------tRTC----------------------~
~---------------tRT--------------~
RT
W,R
FLAG VALID
HF,EF,FF
2679 drwOB
Figure 6. Retransmit
5.19
8
IDT7200n201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2679 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
2679 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
'k-
I- t
RHF-+
~~
R
HALF-FULL OR LESS
I--tWH~
\:
MORE THAN HALF-FULL
~Il
HALF-FULL OR LESS
2678 drw 11
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
w
xo
READ FROM
LAST PHYSICAL
LOCATION
tXOL~__________t_X_O~H~,
tXOHf
2679 drw 12
Figure 10. Expansion Out
5.19
9
IDT7200n201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1 K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
\ 4 - - - tXI
tXIS
tXIR
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
2679 drw 13
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (Le. FF is monitored on the device
where Wis used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and
Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT720017201A17202A may be used when the
application requirements are for 256/51211 024 words or less.
The IDT720017201A17202A is in a Single Device Configuration when the Expansion In (Xi) control input is grounded (see
Figure 12).
Depth Expansion
The I DT720017201 Al7202A can easily be adapted to applications when the requirements are for greater than 256/5121
1024 words. Figure 14 demonstrates Depth Expansion using
three IDT720017201A17202As. Any depth can be attained by
adding additional IDT720017201A17202As. The IDT7200/
7201 Al7202A operates in the Depth Expansion mode when
the following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (Xi) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EFs and ORing of all FFs (Le. all must be setto generate the
correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: Cascading
FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Status flags (EF, FFand HF) can be detected from anyone device.
Figure 13 demonstrates an 18-bit word width by using two
I DT720017201 Al7202As. Any word width can be attained by
adding additional IDT720017201 Al7202As (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT720017201 Al7202As as shown
in Figure 16. Both Depth Expansion and Width Expansion
may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FI FO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the
bus until the R line is raised from low-to-high, after which the
bus would go into a three-state mode aftertRHz ns. The EFline
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the Wline being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.19
10
II
IDT7200n201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1 K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HALF-FULL FLAG)
(HF)
0fi) _ _ _...r----L.il.-_ _ _
WRITE
lOT
DATA IN (D)
7200/
FULL FLAG (FF) ~------4 7201 N
RESET (RS)
1-----
7202A
EXPANSION IN
READ
(R)
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
(Xi)
2679 drw 14
Figure 12. Block Diagram of Single 256/51211024 x 9 FIFO
DATAIN (D)
------+----tWRITE
fiii)
lOT
72001
7201 AI
7202A
RESET (RS) - - - - -...... - - - - - -
~--+
FULL FLAG (FF)
- - - - - - .....- - - lOT
72001
1-------
+---~
7201 AI
7202A
READ (R)
EMPTY FLAG (EF)
.....~--- RETRANSMIT (RT)
DATA OUT (Q)
2679 drw 15
Figure 13. Block Diagram of 256/51211024 x 18 FIFO Memory Used in Width Expansion Mode
TABLE I-RESET AND RETRANSMIT
Single Device Configuration/width Expansion Mode
Inputs
Mode
RS
Internal Status
Read Pointer
XI
0
Location Zero
Outputs
Write Pointer
Reset.
0
RT
X
FF
Location Zero
EF
0
1
HF
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
ReadlWrite
1
1
0
Incrementl' )
Incrementl' )
X
X
X
X
NOTE:
1. Pointer will increment if flag is High.
2679tbl09
TABLE II-RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
Mode
Reset First Device
RS
0
FL
Internal Status
Outputs
Read Pointer
Write Pointer
0
XI
(1 )
Location Zero
Location Zero
Location Zero
Location Zero
Reset All Other Devices
0
1
(1)
ReadlWrite
1
X
(1 )
X
X
EF
0
FF
1
0
1
X
X
NOTE:
2679 tbll0
1. Xiis connected to XO of previous device. See Figure 14. RS= Reset Input, roRT= First Load/Retransmit, EF= Empty Flag Output, FF= Flag Full Output,
Xi = Expansion Input, HF = Half-Full Flag Output
5.19
11
IDT7200n201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 X 9 and 1 K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~::----...----+----------R
w--------------.-----~~
o ___....::9'-+-_ _ _,....-,--.
Q
~_._r~------vcc
RS----------~-~
II
2679 drw 16
Figure 14. Block Diagram of 768 x 9/1536 x 9/3072 x 9 FIFO Memory (Depth Expansion)
I
R,W,RS
Oo-Os
09-017
Oo-Os
09-017
IDT7200/
IDT7201N
IDT7202A
DEPTH
EXPANSION
BLOCK
IDT7200/
IDT7201N
IDT7202A
DEPTH
EXPANSION
BLOCK
IDT7200/
IDT7201A1
IDT7202A
DEPTH
EXPANSION
BLOCK
D(N-S)-DN
D9 -D17
Do-Os
DO-ON _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
D1s -ON
Dg-DN
D(N-S)-DN
2679 drw 17
Figure 15. Compound FIFO Expansion
NOTES:
1. For depth expsansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
5.19
12
IDT7200n201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1 K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Rs
EFs
HFs
SYSTEM A
SYSTEM S
2679 drw 18
Figure 16. Bidirectional FIFO Mode
DATA IN
w
R
EF
twLZ
DATA OUT
2679 drw 19
Figure 17. Read Data Flow-Through Mode
W
~~~~~4-----------------+-----------~------------~
FF
t DH
DATA IN
tA ;:;;II
DATA OUT
--------------~ ~ATAOUT VALID t:J:lJ~------------------------2679 drw 20
Figure 18. Write Data Flow-Through Mode
5.19
13
IDT7200n201A17202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 X 9 and 1 K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXX
x
xxx
x
x
Device Type
Power
Speed
Package
Process/
Temperature
Range
y~lank
P
TP
o
1 - - - - - - - - - 1 TO
J
SO
L
XE
12
15
20
25
30
35
40
50
65 }
80
120
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP (7201 & 7202 Only)
Plastic THINDIP
CERDIP (7201 & 7202 Only)
Ceramic THINDIP
Plastic Leaded Chip Carrier
SOIC
Leadless Chip Carrier (7201 & 7202 Only)
CERPACK (7201 & 7202 Only)
Commerical Only
Commercial Only
Commercial Only
Military Only
Commercial Only
Military Only
Military only-except XE
package
I LA
Low Power"
7200
7201
1 7202
256 x 9-Bit FIFO
512 x 9-Bit FIFO
1024 x 9-Bit FIFO
1
II
Access Time (fA)
Speed in Nanoseconds
2679 drw21
" "A" to be included for 7201 and 7202 ordering part number.
5.19
14
(;)®
CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9,
8192 X 9 and 16384 x 9
IDT7203
IDT7204
IDT7205
IDT7206
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
The IDT7203172041720517206 are dual-port memory buffers with internal pointers that load and empty data on a firstin/first-out basis. The device uses Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of
the Write (W) and Read (R) pins.
The devices 9-bit width provides a bit for a control or parity
at the user's option. It also features a Retransmit (RT) capability that allows the read pointerto be reset to its initial position
when RT is pulsed LOW. A Half-Full Flag is available in the
single device and width expansion modes.
The IDT72031720417205n206 are fabricated using lOT's
high-speed CMOS technology. They are designed for applications requiring asynchronous and simultaneous read/writes
in multiprocessing, rate buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
•
•
•
•
•
•
•
•
First-In/First-Out Dual-Port memory
2048 x 9 organization (IDT7203)
4096 x 9 organization (IDT7204)
8192 x 9 organization (IDT7205)
16384 x 9 organization (IDT7206)
High-speed: 12ns access time
Low power consumption
- Active: 770mW (max.)
- Power-down: 44mW (max.)
Asynchronous and simultaneous read and write
Fully expandable in both word depth and width
Pin and functionally compatible with IDT720X family
Status Flags: Empty, Half-Full, Full
Retransmit capability
High-performance CMOS technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing for #5962-88669 (IDT7203),
5962-89567 (lDT7203), and 5962-89568 (IDT7204) are
listed on this function.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(Do -Da)
w
THREESTATE
BUFFERS
DATA OUTPUTS
(00 -Oa)
FURT
X i - - - - -....I1 . -_ _ _ _.....1
2661 drw 01
The lOT logo is a registered trademark of Integrated Device Techology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1994
DSC-200417
©1995 Integrated Device Technology, Inc.
5.20
1
IDT7203n204n20sn206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9,8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
W
Vee
Oa
04
05
06
07
03
02
01
00
"'00
08~l!)
INOEX OOI:5:Z>oo
L......JL-JL..JIIL-JL......JL......J
~
02
01
00
FLIRT
Xi
Xi
RS
EF
XO/HF
FF
00
01
02
03
FF
00
01
Q7
06
05
04
Oa
NC
02
I C\I
~ 0
';:! '" '" "'29[ D6
2a[ D7
27[ NC
J32-1
26[ fliRT
&
2S[ RS
L32-1
24[ EF
23[ XO/HF
22[ 07
to I"- 00 en 021 [ 06
..-,-""'T"""T"""""'C\J
r--1 r - l r I r-1 r-1 r--1 , . ,
00
"'0
0 OI£I:O~Ol!)
0
ZZ
R
GNO
' " C\l1
Js
J6
J7
Ja
J9
J10
J 11
J 12
J 13~ l!)
~
2661 drw 02b
2661 drw 02a
PLCC/LCC
TOP VIEW
DIP
TOP VIEW
NOTES:
1. The THINOI Ps p2a-2 and 02a-3 are only available for the 7203n204/
7205.
2. The small outline package S02a-3 is only available for the 7204.
3. Consult factory for CERPACK pinout.
II
I
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Commercial
Military
Terminal
Voltage with
Respect to
GND
-0.5 to + 7.0
-0.5 to +7.0
TA
Operating
Temperature
a to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +155
°C
VTERM
lOUT
Rating
DC Output
Current
50
50
RECOMMENDED DC OPERATING
CONDITIONS
Unit
Symbol
V
Min.
Typ.
Max.
Unit
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
VCCC
Commercial Supply
Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
a
a
V
VIH(1)
Input High Voltage
Commercial
2.0
-
-
V
VIH(1)
Input High Voltage
Military
2.2
-
-
V
VIL(1)
Input Low Voltage
Commercial and
Military
-
-
0.8
V
mA
NOTE:
2661 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Parameter
a
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
5.20
2661 tbl02
2
IDT7203n204n205n206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 X 9, 8192 X 9 and 16384 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204
(Commercial: Vee
=5.0V±1 0%, TA =O°C to +70°C; Military: Vee =5.0V±10%, TA =-55°C to + 125°C)
IOTI20317204
IOTI20317204
Military(l)
Commercial
tA
Parameter
Symbol
IU(2)
Input Leakage Current (Any Input)
=12, 15,20,25,35,50 ns
Typ.
tA
=20, 30, 40, 50, 65, 80, 120 ns
Max.
Min.
-1
-
1
-1
-
10
-10
-
2.4
Min.
ILO(3)
Output Leakage Current
-10
VOH
Output Logic "1" Voltage IOH = -2mA
2.4
VOL
Output Logic "0" Voltage IOL = 8mA
ICC1(4)
Active Power Supply Current
ICC2(4)
Standby Current (R=W=RS=FURT=VIH)
ICC3(L)(4)
Power Down Current (All Input = Vcc - 0.2V)
ICC3(S)(4)
Power Down Current (All Input = Vcc - 0.2V)
-
0.4
120(5)
12
2
8
Typ.
Max.
Unit
1
JlA
10
JlA
-
-
-
-
-
V
0.4
150(5)
V
mA
25
mA
4
mA
12
NOTES:
1. Speed grades 65,80, and 120ns are only available in the ceramic DIP.
2. Measurements with 0.4 ~ VIN ~ Vee.
3. R ----
--------(~ DATA IN VALID )j)!-------«r-D-A-T-A-IN-VA-Ll-D......
2661 drw 05
Figure 3. Asynchronous Write and Read Operation
5.20
7
IDT7203n204n205n206 CMOS ASYNCHRONOUS FIFO
2048 x 9,4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITE
IGNORED
WRITE
FIRST READ
2661 drw06
Figure 4. Full FlagTiming From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
DATA OUT
2661 drw07
Figure 5. Empty Flag Timing From Last Read to First Write
~---------------tRTC----------------------~
~---------------tRT--------------~
W,R
FLAG VALID
HF, EF, FF
2661 drwoe
NOTE:
1.
8=, FF and H F
may change status during Retransmit, but flags will be valid at tRTe.
Figure 6. Retransmit
5.20
8
IDT7203n204n205n206 CMOS ASYNCHRONOUS FIFO
2048 x 9,4096 X 9, 8192 x 9 and 16384 x 9
"
MILITARY AND COMMERCIAL TEMPERATURE RANGES
"---------------~
,k
tWEF
2661 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
" '-------~-.k
tRFF
2661 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
MORE THAN HALF-FULL
HALF-FULL OR LESS
HALF-FULL OR LESS
2661 drw 11
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
tXOL1
tXOH1
"--
~~-----~"
_____
txo~-------t-xo-~
2661 drw 12
Figure 10. Expansion Out
5.20
9
IDT7203n204n205n206 CMOS ASYNCHRONOUS FIFO
2048 X 9, 4096 X 9, 8192 X 9 and 16384 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~---t XI----t~-- tXIR
READ FROM
FIRST PHYSICAL
LOCATION
2661 drw 11
Figure 11. Expansion In
OPERATING MODES:
USAGE MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (Le. FF is monitored on the device
where W is used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and
Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT7203172041720S17206 may be used when the
application requirements are for 2048/4096/8192116384 words
or less. The IDT7203/72041720S17206 is in a Single Device
Configuration when the Expansion In (Xi) control input is
grounded (see Figure 12).
Depth Expansion
The IDT7203172041720S17206 can easily be adapted to
applications when the requirements are for greater than 20481
4096/8192116384 words. Figure 14 demonstrates Depth Expansion using three IDT7203172041720S/7206s. Any depth
can be attained by adding additional IDT7203/72041720S1
72065. The IDT7203172041720S17206 operates in the Depth
Expansion mode when the following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (Xi) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EFs and ORing of all FFs (i.e. all must be setto generate the
correct composite FF or EF). See Figure 14.
S. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: Cascading
FIFOs or FIFO Modules.
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Status flags (EF, FF and H F) can be detected from anyone device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7203172041720S17206s. Any word width can be attained
by adding additionaIIDT7203/72041720S17206s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7203172041720S17206s as
shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge ofW, called the first write edge, and it remains on the bus
until the R line is raised from LOW-to-HIGH, after which the
bus would go into a three-state mode aftertRHz ns. The EFline
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being LOW causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 1S).
5.20
10
II
IDT7203n204n20sn206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HALF-FULL FLAG)
WRITE
(HF)
fiJ) ---.r--'-.4----
READ (R)
lOT
7203/ 1--1--,.1 DATA OUT (0)
7204// l----.. EMPTY FLAG (EF)
7205
7206
RETRANSMIT (AT)
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
EXPANSION IN
(Xi)
2661 drw 14
Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used In Single Device Mode
HF
HF
DATAIN (D)
WRITE
fiJ)
------
FULL FLAG (FF)
RESET (RS)
------
lOT
7203/
7204/
7205/
7206
lOT
7203/
7204/
7205/
7206
-------
------
L.....-_ _ _ _ _ _ _ _+--,/'
READ
fR)
EMPTY FLAG (EF)
RETRANSMIT (RT)
DATAoUT(O)
2661 drw 15
NOTE:
1. Flag detection is accomplished by monitoring the
Do not connect any output signals together.
FF. EF and HF signals on either (any) device used in the width expansion configuration.
Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode
S.20
11
1017203172041720517206 CMOS ASYNCHRONOUS FIFO
2048 x 9,4096 X 9, 8192 X 9 and 16384 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATIONIVVIDTH EXPANSION MODE
Inputs
Mode
Internal Status
Outputs
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
Reset
0
X
Location Zero
Location Zero
a
1
1
Retransmit
1
a
Location Zero
Unchanged
X
X
X
ReadIVVrite
1
1
a
a
a
Increment (1)
Increment(1)
X
X
X
HF
NOTE:
1. Pointer will Increment if flag is HIGH.
2661 tbl09
TABLE 11- RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Internal Status
Inputs
Outputs
RS
FL
XI
Read Pointer
Write Pointer
EF
Reset First Device
0
a
(1 )
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1 )
Location Zero
Location Zero
a
1
ReadlWrite
1
X
(1 )
X
X
X
X
Mode
NOTES:
2661 tbl10
1. Xi is connected to XO of previous device. See Figure 14.
2. RS Reset Input, FURT First Load/Retransmit, EF Empty Flag Output,
=
FF
=
=
FF =Full Flag Output, Xi =Expansion Input, HF =Half-Full Flag Output
~-__1>---__+-----R
w-----------~
Q
D _ _--"9~--_.__ro
1-+--.--+-1------- Vee
RS---------~~~
2661 drw 16
Figure 14. Block Diagram of 6149 X 9/12298 X 9/24596 X 9/49152 X 9 FIFO Memory (Depth Expansion)
5.20
12
IDT7203n204n205n206 CMOS ASYNCHRONOUS FIFO
2048 x 9,4096 x 9, 8192 x 9 and 16384 x 9
R,W,RS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Oo-Os
09-Q17
Oo-Os
09-017
IDT7203!
IDT7204!
IDT7205!
IDT7206
DEPTH
EXPANSION
BLOCK
IDT7203!
IDT7204!
IDT7205!
IDT7206
DEPTH
EXPANSION
BLOCK
O(N-S) -ON
IDT7203!
IDT7204!
IDT7205!
IDT7206
DEPTH
EXPANSION
BLOCK
Do-Os
09 -017
DO-ON ___________________________________________
09 -ON
D1s -ON
D(N-S)-DN
D(N-S)-DN
2661 drw 17
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
Rs
EFS
HFs
FFA
SYSTEM A
SYSTEM S
Ws
FFs
2661 drw 1S
Figure 16. Bidirectional FIFO Operation
DATAIN~~___________________________________________________
tRPE---~
twLZ
DATAoUT----------------------------~
2661 drw 19
Figure 17. Read Data Flow-Through Mode
5.20
13
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 X 9, 4096 X 9,8192 X 9 and 16384 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Vii
DATAIN
DATA OUT
-------------+------------------------------<
tA=;j
---------------00\
DATA OUT VALID
>00---------------2661 drw 20
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
lOT
xxxx
x
XX
X
x
Device
Type
Power
Speed
Package
Processl
Temperature
Range
y:,ank
P
TP
o
1..-------------00-4 TO
J
L
SO
12
15
20
25
30
1..-____________________--1 35
40
50
65 }
80
120
---I1 S
L -_ _ _ _ _ _ _ _ _ _ _
IL
1..-________________________________
7203
~7204
1
7205
1 7206
II
Commercial (DOC to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class 8
Plastic DIP
Plastic THINDIP (all except 7206)
Ceramic DIP
Ceramic THINDIP (all except 7206)
Plastic Leaded Chip Carriar
Leadless Chip Carrier (Military only)
Small Outline IC (7204 only)
Commercial 7203/04 Only
Commercial Only
Commercial Only
Military Only
Commercial Only
Military 7203/04 Only
Access Time (tA)
Speed in ns
Military 7203/0408 Only
Standard Power (720317204 only)
Low Power
2048 x 9 FIFO
4096 x 9 FIFO
8192 x 9 FIFO
16384 x 9 FIFO
2661 drw 21
5.20
14
t;)®
CMOS ASYNCHRONOUS FIFO
32,768
X
PRELIMINARY
1017207
9
Integrated Device Technology, Inc.
FEATURES:
• 32768 X 9 storage capacity
• High-speed: 15ns access time
• Low power consumption
- Active: 660mW (max.)
- Power-down: 44mW (max.)
• Asynchronous and simultaneous read and write
• Fully expandable in both word depth and width
• Pin and functionally compatible with IDT720x family
• Status Flags: Empty, Half-Full, Full
• Retransmit capability
• High-performance CMOS technology
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7207 is a monolithic dual-port memory buffer with
internal pointers that load and empty data on a first-in/first-out
basis. The device uses Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for
unlimited expansion capability in both word size and depth.
Data is toggled in and out of the device through the use of
the Write (W) and Read (R) pins.
The devices 9-bit width provides a bit for a control or parity
at the user's option. It also features a Retransmit (RT) capabilitythatallowsthe read pointerto be reset to its initial position
when RT is pulsed LOW. A Half-Full Flag is available in the
single device and width expansion modes.
The IDT7207 is fabricated using lOT's high-speed CMOS
technology. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate
buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
iN
READ
POINTER
THREESTATE
BUFFERS
DATA OUTPUTS
(00
-as)
EF
FF
FURT
3140 drw01
The lOT logo is a regislered trademark of Integrated Device Techology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1995
DSC-20691·
©1995 Integrated Device Technology, Inc.
5.21
1
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IN
INOEX
Vcc
04
08
"-
06
07
FURT
RS
EF
XO/HF
07
06
Xi
L...JL......JL....JIIL...JL......JL....J
C') C\J I IC\I,... 0
v
';::! C') C') C')29[
02 ]5
06
2a[ 07
01 ]6
27[ NC
Do J7
J32-1
26[ .EL./RT
Xi Ja
&
2S[
RS
FF J9
L32-1
24[ EF
00 J10
23[
J11
XO/HF
01
22[ 07
NC J12
J
13:::
~
~
~
~
~
~21
[
02
06
05
03
02
01
00
ogV1l'l
C')OO
oo13: z >oo
FF
00
01
02
03
05
,.-,...-,,.-,,.-,,.....,,.....,,....,
08
04
ao~~p:ao
R
GNO
C!l
3140 drw 03
3140 drw02
PLCC/LCC
TOP VIEW
DIP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Commercial
Military
Terminal
Voltage with
Respect to
GNO
-0.5 to + 7.0
-0.5 to +7.0
TA
Operating
Temperature
a to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +155
°C
lOUT
OC Output
Current
50
50
mA
VTERM
Rating
RECOMMENDED DC OPERATING
CONDITIONS
Unit
Min.
Typ.
Max.
Unit
VeeM
Military Supply
Voltage
Parameter
4.5
5.0
5.5
V
veee
Commercial Supply
Voltage
4.5
5.0
5.5
V
a
0
a
V
Symbol
V
NOTE:
3140 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device atthese or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
GNO
Supply Voltage
VIH(l)
Input High Voltage
Commercial
2.0
-
-
V
VIH(l)
Input High Voltage
Military
2.2
-
-
V
VIL(l)
Input Low Voltage
Commercial and
Military
-
-
0.8
V
NOTE:
1. 1.SV undershoots are allowed for 10ns once per cycle.
3140 tbl 02
DC ELECTRICAL CHARACTERISTICS FOR THE 7207
(Commercial: Vee
= 5.0V±1 0%, TA = O°C to +70°C; Military: Vee:::;; 5.0V±1 0%, TA = -55°C to +125°C)
10T7207
Commercial
tA = 15,20,25,35,50 ns
Symbol
IU(l)
Parameter
Min.
Typ.
10T7207
Military
tA = 20, 30, 50 ns
Max.
Min.
1
-1
10
Typ.
-10
VOH
Output Logic "1" Voltage 10H = -2mA
2.4
-
-
2.4
-
VOL
Output Logic "0" Voltage 10L = 8mA
-
0.4
Active Power Supply Current
-
120(4)
-
-
ICC1(3)
lee2(3)
Standby Current (FbIN=RS=FURT=VIH)
-
12
-
leC3(L)(3)
Power Oown Current (All Input = Vee - 0.2V)
-
-
8
-
5.21
/-LA
10
/-LA
-
Output Leakage Current
NOTES:
1. Measurements with 0.4 :5: V,N :5: Vee.
2. R 2: VIH, 0.4 :5: VOUT :5: Vee.
3. Icc measurements are made with outputs open (only capacitive loading).
4. Tested at f =20MHz.
Unit
1
-10
ILO(2)
-1
Max.
-
-
Input Leakage Current (Any Input)
-
0.4
150(4)
V
V
mA
25
mA
12
mA
3140 tbl 04
2
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
Commercial: Vcc =5V ± 10%, TA =ODC to +70DC; Military: Vcc =5V ± 10%, TA =-55 DC to +125 DC)
Com'l
7207L15
Symbol
Parameters
Min.
Com'l & Mil.
7207L20
Com'l
Military
Com'l
7207L25
7207L30
7207L35
Max. Min. Max. Min. Max. Min. Max Min. Max.
Com'l & Mil.
7207L50
Min. Max. Unit
fS
Shift Frequency
-
40
-
33.3
-
28.5
-
25
-
22.2
-
15
tRC
Read Cycle Time
25
-
30
-
35
-
40
-
45
-
65
-
ns
tA
Access Time
-
15
-
20
-
25
-
30
-
35
-
50
ns
tRR
Read Recovery Time
-
tWLZ
Write HIGH to Data Bus Low-Z(3.4)
-
-
-
-
-
-
15
50
10
15
5
ns
-
10
35
5
10
5
ns
-
10
30
5
5
5
-
Read LOW to Data Bus LOW(3)
10
25
5
5
5
-
tRLZ
-
-
Read Pulse Width(2)
10
20
5
5
5
-
tRPW
-
-
ns
15
-
18
-
20
-
20
-
30
ns
-
-
40
30
10
18
0
40
30
30
10
40
30
30
10
-
45
35
10
18
0
45
35
35
10
45
35
35
10
-
-
35
25
10
15
0
35
25
25
10
35
25
25
10
65
50
15
30
5
65
50
50
15
65
50
50
15
-
35
35
35
25
25
-
-
-
40
40
40
30
30
-
45
45
45
30
30
tOV
Data Valid from Read HIGH
10
15
5
5
5
tRHZ
Read HIGH to Data Bus High-Z(3)
-
15
-
25
15
10
11
0
25
15
15
10
25
15
15
10
-
-
30
20
10
12
0
30
20
20
10
30
20
20
10
25
25
25
15
15
-
30
30
30
20
20
tWC
Write Cycle Time
tWPW
Write Pulse Width(2)
tWR
Write Recovery Time
tDS
Data Set-up Time
tDH
Data Hold Time
tRSC
Reset Cycle Time
tRS
Reset Pulse Width(2)
tRSS
Reset Set-up Time(3)
tRTR
Reset Recovery Time
tRTC
Retransmit Cycle Time
tRT
Retransmit Pulse Width(2)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
ns
ns
-
ns
-
ns
-
ns
-
ns
ns
-
ns
-
ns
-
ns
-
ns
-
ns
ns
-
65
65
65
45
45
ns
ns
ns
tATS
Retransmit Set-up Time(3)
tRSR
Retransmit Recovery Time
tEFL
Reset to EF LOW
tHFH, tFFH
Reset to HF and FF HIGH
tRTF
Retransmit LOW to Flags Valid
tREF
Read LOW to EF LOW
tRFF
Read HIGH to FF HIGH
-
tRPE
Read Pulse Width after EF HIGH
15
-
20
-
25
-
30
-
35
-
50
-
ns
tWEF
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF Flag LOW
Read HIGH to HF Flag HIGH
-
20
20
30
30
-
25
25
35
35
-
30
30
40
40
-
30
30
45
45
-
tRHF
-
-
tWHF
15
15
25
25
-
45
45
65
65
ns
tWFF
-
tWPF
Write Pulse Width after FF HIGH
15
-
20
-
25
-
30
-
35
-
50
-
ns
tXOL
Read/Write LOW to XO LOW
-
-
-
-
25
25
-
30
30
-
35
35
-
50
50
tXI
Read/Write HIGH to XO HIGH
XI Pulse Width(2)
20
20
ns
tXOH
15
15
XI Set-up Time
25
10
10
-
30
10
10
35
10
15
-
50
10
15
-
ns
XI Recovery Time
20
10
10
-
tXIR
-
-
tXIS
15
10
10
-
-
-
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3140 tbl 05
5.21
3
IDT7207 CMOS ASYNCHRONOUS FIFO
32,76S X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
SV
GNDto 3.0V
Sns
1.1Kn
1.SV
1.SV
See Fiqure 1
D.U.T. --""'---1
3140 tbl 07
680n
30pF*
CAPACITANCE(l) (TA = +2SoC, f = 1.0 MHz)
Symbol
CIN(l)
Parameter
Condition
Max.
Input Capacitance
VIN = OV
10
pF
COur!1,2)
Output Capacitance
VOUT= OV
10
pF
NOTES.
Unit
OR EQUIVALENT CIRCUIT
Figure 1. Output Load
31 4 0 tbl08
1. This parameter is sampled and not 100% tested.
2. With output deselected.
SIGNAL DESCRIPTIONS
Inputs:
DATA IN (Do-Os) - Data inputs for 9-bit wide data.
Controls:
RESET (RS) - Reset is accomplished whenever the Reset
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location, A reset is
required after power-up ~fore a write operatio~an take place.
Both the Read Enable (R) and Write Enable ('1'1) inputs must
be in the HIGH state during the window shown in Figure 2
(i.e. tRSS before the rising edge of RS) and should not
change until tRSR after the rising edge of RS.
WRITE ENABLE (W}-A write cycle is initiated on the falling
edge of this input if the Full Flag (FF) is not set. Data set-up and
hold times must be adhered-to, with respect to the rising edge
of the Write Enable (W). Data is stored in the RAM array
sequentially and independently of anyon-going read operation.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to LOW,
and will remain set until the difference between the write pointer
and read pointer is less-than or equal to one-half of the total
memory of the device. The Half-Full Flag (HF) is reset by the
rising edge of the read operation.
_
To prevent data overflow, the Full Flag (FF) will go LOW on
the falling edge of the last write signal, which inhibits further write
operations. Upon the completion of a valid read operation, the
Full Flag (FF) will go HIGH after tRFF, allowing a new valid write
to begin. When the FIFO is full, the ~ternal write pointer is
blocked from W, so external changes in Wwill not affectthe FIFO
when it is full.
3140 dIW04
"Includes jig and scope capacitances.
READ ENABLE fR) - A read cycle is initiated on the falling
edge ofthe Read Enable (R), provided the Empty Flag (EF) is not
set. The data is accessed on a First-ln/First-Out basis, ind~
pendent of any ongoing write operations. After Read Enable (R)
goes HIGH, the Data Outputs (00 through 08) will return to a
high-impedance condition until the next Read operation. When
all the data has been read from the FIFO, the Empty Flag (EF)
will go LOW, allowing the ''final'' read cycle but inhibiting further
read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been acco~
plished, the Empty Flag (EF) will go HIGH aftertwEF and a valid
Read can then begin. When the FIFO is empty, the internal read
pointer is blocked from Rso external changes will not affect the
FIFO when it is empty.
FIRST LOAD/RETRANSMIT (FURl) - This is a dualpurpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first device loaded (see
Operating Modes). The Sin~e Device Mode is initiated by
grounding the Expansion In (XI).
The IDT7207 can be made to retransmit data when the
Retransmit Enable Control (Rl) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location
and will not affect the write pointer. The status of the Flags will
change depending on the relative locations of!!!,e read and write
pointers. Read Enable (R) and Write Enable ('1'1) must be in the
HIGH state during retransmit. This feature is useful when less
than 32,768 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode.
EXPANSION IN (Xi) - This input is a dual-purpose pin.
Expansion In (Xi) is grounded to in~cate an operation in the
single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or
Daisy-Chain Mode.
----------------------------------------------------------4
5.21
IDT1207 CMOS ASYNCHRONOUS FIFO
32,76S x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Outputs:
FULL FLAG (FF)-The Full Flag (FF) will go LOW, inhibiting
further write operations, when the device is full. If the read
pointer is not moved after Reset (RS), the Full Flag (FF) will go
LOW after 32,768 writes.
EMPTY FLAG (EF) - The Empty Flag (EF) will go LOW,
inhibiting further read operations, when the read pointer is equal
to the write pointer, indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (XO/HF) - This is a
dual-pu!E0se output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a halffull memory.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to LOW
and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
memory of the device. The Half-Full Flag (HF) is then reset by
the rising edge of the read operation.
In the Depth Expansion~ode, Expansion In (Xi) is connected to Expansion Out (XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an XO pulse
when the Write pointer reaches the last location of memory, and
an additional XO pulse when the Read pointer reaches the last
location of memory.
DATA OUTPUTS (aD-aS) - 00-08 are data outputs for 9bit wide data. The~e outputs are in a high-impedance condition
whenever Read (R) is in a HIGH state.
~---------------------- tRsc--------------------------~~
3140 drw 05
NOTE:
1. Wand R VIH around the rising edge of RS.
=
Figure 2. Reset
00 -08
Do -08
.WRq
/_---
r;'Dsr'DH~ ~
_ { " , - - _ t w P _ w_.we
---------4:K
DATA IN VALID
~
(r-O-A-T-A-IN-V-A-Ll-O-.....)>----•
3140 drw 06
Figure 3. Asynchronous Write and Read Operation
5.21
5
1017207 CMOS ASYNCHRONOUS FIFO
32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITE
IGNORED
WRITE
FIRST READ
W
3140 drw07
Figure 4. Full FlagTiming From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
W
DATAoUT
3171 drw 08
Figure 5. Empty Flag Timing From Last Read to First Write
~--------------------tRTC----------------------------~
t RT
W,R
FLAG VALID
HF, EF, FF
3140 drw09
NOTE:
1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
5.21
6
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9
w
MILITARY AND COMMERCIAL TEMPERATURE RANGES
'"'------~j{
tWEF
t RPE
3140 drw 10
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
tWPF
w
3140 drw 11
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
w
tWHF
HALF-FULL OR LESS
MORE THAN HALF-FULL
HALF-FULL OR LESS
3140 drw 12
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
w
t_x_OL_=-'~
XO _______
~
tx_O_H_~
_________
READ FROM
LAST PHYSICAL
LOCATION
~-----t-XO_L'_~
~
_____________
tX_O_H
l'
~------
/f
3140drN13
Figure 10. Expansion Out
5.21
7
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9
~----
Vi
t XIS
{
t
MILITARY AND COMMERCIAL TEMPERATURE RANGES
XI -----I~IJ---
t XIR
--J'/
FIRST
PHYSICAL
___
_
W_R_IT_E_T_O
__
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
3140 drw 14
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (Le. FF is monitored on the device
where Wis used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and
Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT7207 may be used when the application
requirements are for 32,768 words or less. The IDT7207 is
in a Single Device Configuration when the Expansion In (Xi)
control input is grounded (see Figure 12).
corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from anyone device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7207s. Any word width can be attained by adding additionallDT7207s (Figure 13).
Bidirectional Operation
II
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7207s as shown in Figure 16.
Both Depth Expansion and Width Expansion may be used in
this mode.
Data Flow-Through
Depth Expansion
The IDT7207 can easily be adapted to applications when
the requirements are for greater than 32,768 words. Figure 14
demonstrates Depth Expansion using three IDT7207s. Any
depth can be attained by adding additionallDT7207s. The
IDT7207 operates in the Depth Expansion mode when the
following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (Xi) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EFs and ORing of all FFs (Le. all must be set to generate the
correct composite FF or EF). See Figure 14.
5. The Retransmit (RD function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
For additional information, referto Tech Note 9: Cascading
FIFOs or FIFO Modules.
USAGE MODES:
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. Forthe read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus
until the R line is raised from LOW-to-HIGH, after which the
bus would go into a three-state mode aftertRHz ns. The EFline
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the Wline being LOW causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The W
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
Width Expansion
Word width may be increased simply by connecting the
5.21
8
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HALF-FULL FLAG)
WRITE
0N> ---~
(HF)
. . - - - - - READ
(R)
DATAOUT(Q)
DATA IN (D)_-I-_,/
FULL FLAG (FF) ~----f
. - - - . EMPTY FLAG (EF)
---~
.....- - - RETRANSMIT (RT)
RESET (RS)
3140 drw 15
Figure 12. Block Diagram of 32,768 x 9 FIFO Used In Single Device Mode
HF
HF
DATAIN (D)
WRITE
0N>
------
------
IDT
IDT
7207
7207
FULL FLAG (FF)
RESET (RS)
READ
(R)
EMPTY FLAG (EF)
------RETRANSMIT (RT)
DATA OUT(Q)
3140 drw 16
NOTE:
1. Flag detection is accomplished by monitoring the FF,
Do not connect any output signals together.
EF and HF signals on either (any) device used in the width expansion configuration.
Figure 13. Block Diagram of 32,768 x 18 FIFO Memory Used In Width Expansion Mode
5.21
9
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I - RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION MODE
Inputs
Mode
Internal Status
Outputs
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
ReadIWrite
1
1
0
Increment(1)
Increment(1)
X
X
X
HF
NOTE:
1. Pointer will Increment if flag is HIGH.
3140tbl09
TABLE II - RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
Internal Status
Outputs
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset First Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1 )
Location Zero
Location Zero
0
1
Read/Write
1
X
(1 )
X
X
X
X
Mode
NOTES:
3140 tbll0
1. Xi is connected to XO of previous device. See Figure 14.
2. RS Reset Input, FURT First Load/Retransmit, EF Empty Flag Output, FF
=
=
=
=Full Flag Output, Xi =Expansion Input, HF =Half-Full Flag Output
I XO
FF
o
9,/
--
~
I
I
....
/ 9)
,
V"
~
lOT
7207
I
- FL
i~
...-
EF
I
9 ,/
~
...-
....
Q
V"
Vee
XO
FF
~
"-
~
.....
lOT
7207
9/,)
1r
-FL
_t
...- -
i~
XO
~
FF
"---
9 ,/
~
.....
)
v
lOT
7207
I
-.--'
~
YF ~
-
FL
XI
-""~
--='--
~
-
3 140 drw 17
Figure 14. Block Diagram of 98,304 x 9 FIFO Memory (Depth Expansion)
5.21
10
II
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
00 -Os
II
o (N-S)
09 -017
II
Qo-Q,
IDT7207
DEPTH
EXPANSION
BLOCK
09-017
IDT7207
DEPTH
EXPANSION
BLOCK
IDT7207
DEPTH
EXPANSION
BLOCK
A, W, RS
-ON
r-
l'r
i'r
Do -Ds
D(N-S) -DN
D9 -D17
Do -DN
D9 -DN
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
D(N-S) -DN
3140 drw 18
Figure 15. Compound FIFO Expansion
SYSTEMB
SYSTEM A
3140 drw 19
Figure 16. Bidirectional FIFO Operation
DATAIN ~_____________________________________________________________________
tAPE
tWl2
DATA OUT
OUT
3171 drw20
Figure 17. Read Data Flow-Through Mode
5.21
11
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t RFF
DATA IN
tA=;j
DATA
OUT
----------- a:
len () len
DM
DA3
DA2
DA1
DAD
GSA
DA11
JS2-1
RNiA
RER
REW
REO
AGK
GlK
DBa
PLCC
TOP VIEW
5.23
2
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
Name
110
Description
DAO-DA15
Data A
1/0
Data inputs and outputs for 16 bits of the 1B-bit Port A bus.
DA16-DA17
Parity A
1/0
DA16 is the parity bit for DAO-DA7. DA17 is the parity bit for DABDA 15. DA 16 and DA 17 can be used as two extra data bits if the
parity generate function is disabled.
CSA
Chip Select A
I
Port A is accessed when Chip Select A is LOW.
DSA
Data Strobe A
I
Data is written into Port A on the rising edge of Data Strobe when
Chip Select is LOW. Data is read out of Port A on the falling edge of
Data Strobe when Chip Select is LOW.
RIWA
ReadIWrite A
I
This pin controls the read or write direction of Port A. When CSA is
LOW and RiWA is HIGH, data is read from Port A on the falling edge
of DSA. When CSA is LOW and RiWA is LOW, data is written into
Port A on the rising edge of DSA.
AO, A1
Addresses
I
When Chip Select A is asserted, AO, A 1, and ReadIWrite A are used
to select one of six internal resources.
DBO-DB7
Data B
1/0
Data inputs and outputs for B bits of the 9-bit Port B bus.
DBB
ParityB
1/0
DBB is the parity bit for DBO-DB7. DBB can be used as a data bit if
the parity generate function is disabled.
RB (DSB)
Read B
10rO
If Port B is programmed to processor mode, this pin functions as an
input. If Port B is programmed to peripheral mode this pin functions
II
as an output. This pin can function as part of an Intel-style interface
(RB) or as part of a Motorola-style interface (DSB). As an Intel-style
interface, data is read from Port B on a falling edge of RB. As a
Motorola-style interface, data is read on the falling edge of DSB or
written on the rising edge of DSB through Port B. The Default is Intelstyle processor mode (RB as an input).
If Port B is programmed to processor mode, this pin functions as an
input. If Port B is programmed to peripheral mode this pin functions
as an output. This pin can function as part of an Intel-style interface
(WB) or as part of a Motorola-style interface (RiWB). As an Intel
style interface, data is written to Port B on a rising edge of WB. As
a Motorola-style interface, data is read (RiWB = HIGH) or written (R/
WB = LOW) to Port B in conjunction with a Data Strobe B faJling or
rising edge. The Default is Intel-style processor mode (WB as input).
WB (RiWB)
WriteB
10rO
RER
Reread
I
Loads A-to-B FIFO Read Pointer with the value of the Reread
Pointer when LOW.
REW
Rewrite
I
Loads B-to-A FIFO Write Pointer with the value of the Rewrite
Pointer when LOW.
LDRER
Load Reread
I
Loads the Reread Pointer with the value of the A-to-B FIFO Read
Pointer when HIGH. This signal is accessible through the Command
Register.
LDREW
Load Rewrite
I
Loads the Rewrite Pointer with the value of the B-to-A FIFO Write
Pointer when HIGH. This signal is accessible through the Command
Register.
REO
Request
I
When Port B is programmed in peripheral mode, asserting this pin
begins a data transfer. Request can be programmed either active
HIGH or active LOW.
2669 tbl 01
5.23
3
IDT72510, 1DT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
Name
110
Description
ACK
Acknowledge
0
When Port B is programmed in peripheral mode, Acknowledge is
asserted in response to a Request signal. This confirms that a data
transfer may begin. Acknowledge can be programmed either active
HIGH or active LOW.
CLK
Clock
I
This pin is used to generate timing for ACK,RB, ViB,
DSB and RIWB when Port B is in the peripheral mode.
FLGA-FLGD
Flags
0
These four outputs pins can be assigned to anyone of the eight
internal flags in the BiFIFO. Each of the two internal FIFOs (A-to-B
and B-to-A) has four internal flags: Empty, Almost-Empty, AlmostFull, and Full. If parity checking is enabled, the FLGA pin can also
be assigned as a parity error output.
RS
Reset
I
A LOW on this pin will perform a reset of all BiFIFO functions.
Software reset can be achieved through command register.
VCC
Power
There are two +5V power pins on all four devices.
Ground
There are four ground pins
GND
2669 tbl 02
5.23
4
c
m
-I
PortB
Control
lDRERt
LDREWt
RER
REW.......
~
r
m
C
OJ
RB (DSB) tt
WB (R/WB) tt5
- ..
~
I .. )
~ I ..
9
(DAO-DA7,DA 16)
I ~ I.
m~
o
~
r
»
:::!
*T1
=n
o
s:
I
DAO-DA17'"
C)N
5°
C
::D
(DBo-DB7)
:::to
z::j
ii
m
o
C')
,
3:~
lo ....
-loP
0-
o
"l>
Port A
~5
cn::j
•
Port 8
DBo-DBB
B~A
FIFO
en
N
(,)
1
Write
Parity Erro
r
FlGN
FlGB·
FlGc·
FlGD·
(DAo-DA1s)
...-----.....
I
__________
Status
.-
DMA
Control
RS t
REQ*
ACK*
ClK
o
o
3:
3:
m
::IJ
o
>
r
99~f~g~~a!i~~ ~
9~~f~g~~a!i~r: ~
1
j.---
J~~~--------------------------------------~
Configuration 0
9~~f~g~~a!i~r: :
9~~f~g~~a!i~r: ~
9~~f~g~~a~i~~ ~
Programmable . . _
l
Flag logic
'-
--------------------
9~~f~g~~a!i~r: ~
Configuration 7
en
I
Reset
------------------r----~-----~
I
I
I
---------------.----~
-I
m
3:
"tI
m
::IJ
~
c:
::IJ
NOTES:
m
(.) Can be programmed either active high or active low in intemal configuration registers.
(t) Accessible through internal registers.
(tt) Can be programmed through an internal configuration register to be either an input or an output.
::IJ
lo
Z
C)
m
II
IDT72510, 1DT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
lOT's BiFIFO family is versatile for both multiprocessor
and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the lOT
BiFIFO, making simultaneous data exchange possible. Each
FIFO is monitored by separate internal read and write pointers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor connected to Port A of the BiFIFO can send or receive messages directly to the Port B device using the BiFIFO's 9-bit
bypass path.
The BiFIFOs can be used in three different bus configurations: 18 bits to 9 bits, 36 bits to 9 bits and 36 bits to 18 bits.
One BiFIFO can be used for the 18- to 9-bit configuration,
and two BiFIFOs are required for 36- to 9-bit or 36- to 18-bit
configurations. Bits 11 and 12 of Configuration Register 5
determine the BiFIFO configuration (see Table 11 for
Configuration Register 5 format).
The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFOs. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed
in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device
is connected to the BiFIFOs, Port B is programmed to peripheral interface mode and the interface pins are outputs.
18- to 9-bit Configurations
A single BiFIFO can be configured to connect an 18-bit
processor to another 9-bit processor or a 9-bit peripheral.
Bits 11 and 12 of Configuration Register 5 should be set to
00 for a stand-alone configuration. Figures 1 and 2 show the
BiFIFO in 18- to 9-bit configurations for processor and
peripheral interface modes respectively.
36- to 9-bit Configurations
Two BiFIFOs can be hooked together to create a 36-bit to
9-bit configuration. This means that a 36-bit processor can
36-BIT PROCESSOR to 18-BIT PROCESSOR CONFIGURATION
lOT
BiFIFO
Processor
B
Processor
A
Address
Control
Control
Data
RAM
RAM
2669 dIW04
Figure 1. 36- to 18-Bit Processor Interface Configuration
NOTE:
1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that Gntl A refers to CSA. Al, Ao, RiWA and DSA; Gntl B refers to RiWB and DSS or RS
andWs.
5.23
6
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
36-BIT PROCESSOR to 18-BIT PERIPHERAL CONFIGURATION
lOT
BiFIFO
. . . . .- - - t - H - - -
DMA~~~~stem
Peripheral
Controller
Processor
Address
Cnll
ACK
REQ
Control
Data
Data
I/O
Data
lOT
BiFIFO
RAM
EI
2669 drw05
Figure 2. 36- to 18-Bit Peripheral Interface Configuration
NOTE:
1. Upper SiFIFO only is used in 18- to 9-bit configuration. Note that Gntl A refers to CSA, AI, Ao, RiWA and DSA; Gntl B refers to RiWB and DSs or AB
andWB.
talk to a 9-bit processor or a 9-bit peripheral. Both BiFIFOs
are programmed simultaneously through Port A by placing
one command word on the most significant 16 data bits and
one command word on the least significant 16 data bits
(parity bits should be ignored).
One BiFIFO must be programmed as the master device
and the other BiFIFO is the slave device. Bits 11 and 12 of
Configuration Register 5 are set to 10 for the slave device
and 11 for the master device. The first two 9-bit words on
Port B are read from or written to the slave device and the
next two 9-bit words go to the master device.
When both BiFIFOs are in peripheral interface mode, the
Port B interface pins of the master device are outputs and
this BiFIFO controls the bus. The Port B interface pins of the
slave device are inputs driven by the master BiFIFO. Two
BiFIFOs are connected in Figure 4 to create a 36- to 9-bit
peripheral interface.
The two BiFIFOs shown in Figure 3 are configured to
connect a 36-bit processor to a 9-bit processor.
36- to 18-bit Configurations
In a 36- to 18-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 16
data bits to each device with the 4 parity bits ignored.
Both BiFIFOs must be programmed into stand-alone mode
for a 36-bit processor to communicate with an 18-bit processor or an 18-bit peripheral. This means that bits 11 and 12 of
Configuration Register 5 must be set to 00.
This configuration can be extended to wider bus widths
(54- to 27-bits, 72- to 36-bits, ... ) by adding more BiFIFOs to
the configuration. Figures 1 and 2 show multiple BiFIFOs
configured for processor and peripheral interface modes
respectively.
Processor Interface Mode
When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B interface
controls are inputs. Both REO and ClK pins should be pulled
lOW to ensure that the set-up and hold time requirements for
these pins are met during reset. Figures 1 and 3 show
BiFIFOs in processor interface mode.
Peripheral Interface Mode
If Port B is connected to a peripheral controller, all BiFIFOs
in the configuration must be programmed in the peripheral
interface mode. To assure fixed high states for Rs and Ws
before they are programmed into an output, both pins should
be pulled-up to Vce with 10K resistors.
If the BiFIFOs are in stand-alone configuration mode
(18- to 9-bit, 36- to 18-bit, ... ), then the Port B interface pins are
all outputs. Of course, only one set of Port B interface pins
should be used to control a single peripheral device, while the
other interface pins are all ignored. Figure 2 shows stand-
5.23
7
IDT72510, 10172520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
alone configuration BiFIFOs connected to a peripheral.
In a 36- to 9-bit configuration, the master device controls
the bus. The Port B interface pins of the master device are
outputs and the interface pins of the slave device are inputs.
A 36- to 9-bit configuration of two BiFIFOs connected to a
peripheral is shown in Figure 4.
Port A Interface
The BiFIFO is straightforward to use in microprocessorbased systems because each BiFIFO port has a standard
microprocessor control set. Port A has access to six re-
sources: the A~B FIFO, the B~A FIFO, the 9-bit direct data
bus (bypass path), the configuration registers, status and
command registers. The Port A Address and ReadlWrite pins
determine the resource being accessed as shown in Table 1.
Data Strobe is used to move data in and out of the BiFIFO.
When either of the internal FiFOs are accessed 18 bits of
data are transferred across Port A. Since the bypass path is
only 9 bits wide, the least significant byte with parity
(DAO-DA7, DA16) is used on Port A. All of the registers are 16
bits wide which means only the data bits (DAO-DA1S) are
passed by Port A.
36-BIT PROCESSOR to 9-BIT PROCESSOR CONFIGURATION
Processor
B
Processor
A
Address
Control
Control
Data
RAM
RAM
2669drw06
Figure 3. 36- to 9-Bit Processor Interface Configuration
NOTE:
1. Cntl A refers to
CSA, A1, Ao, RiWA and DSA; Cntl B refers to R!WB and DSs or RS and Ws.
5.23
8
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
36-BIT PROCESSOR to 9-BIT PERIPHERAL CONFIGURATION
lOT
BiFIFO
(Master)
DMAor
System
Clock
Peripheral
Controller
Processor
Address
Cntl
Control
ACK
REO
Data
1"-,..--1/1
Data
1/0
Data
RAM
2669 drw 07
Figure 4. 36- to 9-Bit Peripheral Interface Configuration
NOTE:
1.
Gntl A refers to CSA, Al, Ao, RiWA and DSA; Cntl B refers to RIWs and DSS or RS and Ws.
5.23
9
IDT12510,IDT12520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
PORT A RESOURCES
COMMAND OPERATIONS
CSA
A1
Ao
0
0
0
0
0
0
1
1
9-bit Bypass Path
9-bit Bypass Path
0
Configuration
Registers
Configuration
Registers
0
1
1
1
Status Register
Command Register
X
X
Disabled
Disabled
Read
B~A
Write
A~B
FIFO
Command
Opcode
FIFO
0000
0001
0010
0011
0100
0101
2669 tbl 03
Table 1. Accessing Port A Resources Using CSA, AO, and A1
Bypass Path
The bypass path acts as a bidirectional bus transceiver
directly between Port A and Port B. The direct connection
requires that the Port A interface pins are inputs and the Port
B interface pins are outputs. The bypass path is 9 bits wide in
an 18- to 9-bit configuration or in a 36- to 9-bit configuration.
Only in the 36- to 18-bit configuration is the bypass path 18 bits
wide.
During bypass operations, the BiFIFOs must be programmed into peripheral interface mode. Bit 10 of Configuration Register 5 (see Table 11) is set to 1 for peripheral interface
mode. In a 36- to 9-bit configuration, both Port B data buses
will be active. Data written into Port A will appear on both
master and slave Port B buses concurrently. To avoid Port B
bus contention, the data on DAO-DA7 and DA16 of both BiFIFOs
should be exactly the same. Data read from Port A will appear
on pins DAO-DA7 and DA16 of both BiFIFOs within the same 36bit word.
Function
Reset BiFIFO (see Table 3)
Select Configuration Register (see Table 4)
Load Reread Pointer with Read Pointer Value
Load Rewrite Pointer with Write Pointer Value
Load Read Pointer with Reread Pointer Value
Load Write Pointer with Rewrite Pointer Value
0110
0111
1000
Set DMA Transfer Direction (see Table 5)
1001
Increment in byte for
(Port B)
1010
1011
Clear Write Parity Error Flag
Set Status Register Format (see Table 6)
Increment in byte for A~B FIFO Read Pointer
(Port B)
B~A
FIFO Write Pointer
Clear Read Parity Error Flag
2669 tbl 04
Table 2. Functions Performed by Port A Commands
Command Register
Ten registers are accessible through Port A, a Command
Register, a Status Register, and eight Configuration Registers.
The Command Register is written by setting CSA = 0, A1 =
1, Ao = 1. Commands written into the BiFIFO have a 4-bit
opcode (bit 8 - bit 11) and a 3-bit operand (bit 0 - bit 2) as
shown in Figure 5. The commands can be used to reset the
BiFIFO, to select the Configuration Register, to perform intelligent reread/rewrite, to setthe Port B DMA direction, to setthe
Status Register format, to modify the Port B Read and Write
Pointers, and to clear Port B parity errors. The command
opcodes are shown in Table 2.
The reset command initializes different portions of the
BiFIFO depending on the command operand. Table 3 shows
the reset command operands.
The Configuration Register address is set directly by the
command operands shown in Table 4.
Intelligent reread/rewrite is performed by changing the Port
B Read Pointer with the Reread Pointer or by changing the
Port B Write Pointer with the Rewrite Pointer. No command
operands are required to perform a reread/rewrite operation.
When Port B of the BiFIFO is in peripheral mode, the DMA
direction is controlled by the Command Register. Table 5
shows the Port Bread/write DMA direction operands.
The BiFIFO supports two Status Register formats. Status
Registerformat 1 gives all the internal flag status, while Status
Register format 0 provides the data in the Odd Byte Register.
Table 6 gives the operands for selecting the appropriate
Status Register format. See Table 8 for the details of the two
Status Register formats.
Two commands are provided to increment the Port BRead
and Write Pointers in case reread/rewrite is performed.
Incrementing the pointers guarantees that pointers will be on
a word boundary when an odd number of bytes is transmitted
through Port B. No operands are required for these commands.
When parity check errors occur on Port B, a clear parity
error command is needed to remove the parity error. There are
no operands for these commands.
Reset
-Ihe IDT72510 and IDT72520 have a hardware reset pin
(RS) that resets all BiFIFO functions. A hardware reset requires the following four conditions: Rs and Ws must be HIGH,
RER and REW must be HIGH, LDRER and LDREW must be
LOW, and DSA must be HIGH (Figure 9). After a hardware
reset, the BiFIFO is in the following state: Configuration
Registers 0-3 are OOOOH, Configuration Register 4 is set to
COMMAND FORMAT
I
15
X
x
x
12
X
11
8
7
X
Command Opcode
x
x
x
o
3
2
x
Command Operand
2669 tbl 05
Figure 5. Format for Commands Written Into Port A
5.23
10
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
RESET COMMAND FUNCTIONS
Reset
Operands
SELECT CONFIGURATION REGISTER
COMMAND FUNCTIONS
Function
Operands
000
No Operation
001
Reset B~A FIFO (Read, Write, and Rewrite
Pointers 0)
000
=
010
Reset A~B FIFO (Read, Write, and Reread
Pointers 0)
=
011
Reset
B~A
and
A~B
FIFO
100
Reset Internal DMA Request Circuitry
101
No Operation
110
No Operation
111
Reset All
Function
Select Configuration Register 0
001
Select Configuration Register 1
010
Select Configuration Register 2
011
Select Configuration Register 3
100
Select Configuration Register 4
101
Select Configuration Register 5
110
Select Configuration Register 6
111
Select Configuration Register 7
2669tbl07
Table 4. Select Configuration Register Command Functions.
2669 tbl 06
Table 3. Reset Command Functions
DMA DIRECTION COMMAND FUNCTIONS
6420H, and Configuration Registers 5 and 7 are OOOOH.
Additionally, Status Register format 0 is selected, all the
pointers including the Reread and Rewrite Pointers are set to
0, the odd byte register valid bit is cleared, the DMA direction
is set to B~A write, the internal DMA request circuitry is
cleared (set to its initial state), and all parity errors are cleared.
A software reset command can reset A~B pointers and
the B~A pointers to 0 independently or together. The request
(REO) DMA circuitry can also be reset independently. A
software Reset All command resets all the pointers, the DMA
request circuitry, and sets all the Configuration Registers to
their default condition. Note that a hardware reset is NOT the
same as a software Reset All command. Table 7 shows the
BiFIFO state after the different hardware and software resets.
Operands
Function
XXO
Write B~A FIFO
XX1
Read
A~B
FIFO
2669 tbl 08
Table 5. Set DMA Direction Command Functions. Command Only
Operates in Peripheral Interface Mode
STATUS REGISTER FORMAT COMMAND
FUNCTIONS
Operands
Function
XXO
Status Register Format 0
XX1
Status Register Format 1
2669 tbl 09
Table 6. Command Functions to Set the Status Register Format
STATE AFTER RESET
Hardware Reset
(RS asserted)
Configuration Registers 0-3
OOOOH
Configuration Register 4
6420H
Configuration Register 5
OOOOH
Configuration Register 7
OOOOH
Software Reset
~A(001)
A~B
(010)
B~A and
A~B (011)
-
-
-
Internal
Request
(100)
All (111)
-
-
OOOOH
-
-
6420H
-
OOOOH
-
OOOOH
-
Status Register format
0
B~A
Read, Write, Rewrite
Pointers
0
0
-
0
-
0
A~B
0
-
0
0
-
0
clear
clear
clear
-
clear
Read, Write, Reread
Pointers
Odd byte register valid bit
DMA direction
~Awrite
DMA internal request
clear
Parity errors
clear
-
-
-
-
-
clear
clear
-
2669 tbltO
Table 7. The BiFIFO State After a Reset Command
5.23
11
IDTI2510, IDTI2520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
Status Register
The eight Configuration Register formats are shown in
Table 9. Configuration Registers 0-3 contain the programmable flag offsets for the Almost Empty and Almost Full flags.
These offsets are set to 0 when a hardware reset or a software
reset all is applied. Note that Table 9 shows that Configuration
Registers 0-3 are 10 bits wide to accommodate the 1024
locations in each FIFO memory of the IDT72520. Only 9 least
significant bits are usedforthe 512 locations of the IDT72510;
the most significant bit, bit 9, must be set to O.
Configuration Register 4 is used to assign the internal flags
to the external flag pins (FlGA-FlGD). Each external flag pin
is assigned an internal flag based on the four bit codes shown
in Table 10. The default condition for Configuration Register
4 is 6420H as shown in Table 7. The default flag assignments
are: FlGD is assigned B~A Full, FlGc is assigned B~A Empty,
FlGs is assigned A~B Full, FlGA is assigned A~B Empty.
Configuration Register 5 is a general control register. The
format of Configuration Register 5 is shown in Table 11. Bit 0
sets the Intel-style interface (RS, Ws) or Motorola-style interface (DSs, RIWs) for Port B. Bit 1 changes the byte order for
data coming through Port B. Bits 2 and 3 redefine Full and
Empty Flags for reread/rewrite data protection.
Bits 4-9 control the DMA interface and are only applicable
in peripheral interface mode. In processor interface mode,
these bits are don't care states. Bits 4 and 5 set the polarity
of the DMA control pins REO and ACK, respectively. An
internal clock controls all DMA operations. This internal clock
is derived from the external clock (ClK). Bit 9 determines the
internal clock frequency: the internal clock = ClK or the
internal clock = ClK divided by 2. Bit 8 sets whether RS, Ws,
and DSs are asserted for either one ortwo internal clocks. Bits
6 and 7 set the number of internal clocks between REO
assertion and ACK assertion. The timing can be from 2 to 5
cycles as shown in Figure 17.
Bit 10 controls Port B processor or peripheral interface
mode. In processor mode, the Port B control pins (RS, Ws, DSs,
RIWs) are inputs and the DMA controls are ignored. In
peripheral mode, the Port B control pins are outputs and the
DMA controls are active.
Bits 11 and 12 set the width expansion mode. For 18- to
9-bit configurations or 36- to 18-bit configurations, the BiFIFO
should be set in stand-alone mode. For a 36- to 9-bit
configuration, one BiFIFO must be in slave mode and the
other BiFIFO must be in master mode. The master BiFIFO
allows the first two bytes transferred across Port B to go to the
slave BiFIFO, then the next two bytes go to the master BiFIFO.
Configuration Register 7 controls the parity functions of
Port B as shown in Table 12. Either parity generation or parity
STATUS REGISTER FORMAT 0
STATUS REGISTER FORMAT 1
The Status Register reports the state of the programmable
flags, the DMA read/write direction, the Odd Byte Register
valid bit, and parity errors. The Status Register is read by
setting CSA 0, A1 1, Ao 1 (see Table 1).
There are two Status Register formats that are set by a
Status Register format command. Format 0 stores the Odd
Byte Register data in the lower eight bits of the Status
Register, while format 1 reports the flag states and the DMA
read/write direction in the lower eight bits. The upper eight bits
are identical for both formats. The flag states, the parity errors,
the Odd Byte Registervalid bit, and the Status Register format
are all in the upper eight bits of the Status Register. See Table
8 for both Status Register formats.
=
=
=
Configuration Registers
Signal
Bit
Signal
Bit
0
0
1
1
Reserved
2
2
Reserved
Reserved
3
DMA Direction
4
4
A~B
Empty Flag
5
5
A~B
Almost-Empty Flag
6
6
B~A
Full Flag
7
B~A
Almost-Full Flag
8
Valid Bit
3
Odd Byte Register
7
8
Valid Bit
9
Write Parity Error
10
Read Parity Error
11
Status Register Format
12
A~B
13
A~B
14
15
9
Write Parity Error
10
Read Parity Error
11
Status Register Format
Full Flag
12
A~B
Full Flag
Almost-Full Flag
13
A~B
Almost-Full Flag
B~A
Empty Flag
14
B~A
Empty Flag
B~A
Almost-Empty Flag
15
B~A
Almost-Empty Flag
=0
26691blll
=1
26691bl12
Table 8. The Two Status Register Formats
5.23
12
IOTI2510,IOTI2520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
CONFIGURATION REGISTER FORMATS
o
10
15
A~
Config. Reg. 0
x
o
10
15
Config. Reg. 1
FIFO Almost-Empty Flag Offset
x
x
x
x
x
A~
FIFO Almost-Full Flag Offset
o
9
B~
Config. Reg. 2
FIFO Almost-Empty Flag Offset
o
B~A
Config. Reg. 3
15
Config. Reg. 4
12
Flag 0 Pin Assignment
FIFO Almost-Full Flag Offset
Flag C Pin Assignment
o
4
7
11
Flag B Pin Assignment
Flag A Pin Assignment
o
15
General Control
Config. Reg. 5
o
15
Reserved
Config. Reg. 6
o
15
Config. Reg. 7
Parity Control
NOTE:
1.
2CC9 tbl13
Bit 9 of Configuration Registers 0-3 must be set to 0 on the ID172510.
Table 9. The BiFIFO Configuration Register Formats
checking is enabled for data read and written through Port B.
Bit 8 controls parity checking and generation for B~A write data.
Bit 9 controls parity checking and generation for A~B read data.
Bit 10 controls whether the parity is odd or even. Bit 11 is used
to assign the internal parity checking error to the FLGA pin.
When the parity error is assigned to FLGA, the Configuration
Register 4 flag assignment for FLGA is ignored.
EXTERNAL FLAG ASSIGNMENT CODES
Programmable Flags
The lOT BiFIFO has eight internal flags; four of these flags
have programmable offsets, the other four are empty or full.
Associated with each FIFO memory array are four internal
flags, Empty, Almost-Empty, Almost-Full and Full, forthe total
of eight internal flags. The Almost-Empty and Almost-Full
offsets can be set to any depth through the Configuration
Registers 0-3 (see Table 9). The offset (or depth) of FIFO RAM
array is based on the unit of an 18-bit word. The flags are
asserted at the depths shown in Table 13. After a hardware
reset or a software reset all, the almost flag offsets are set to
O. Even though the offsets are equivalent, the Empty and
Almost-Empty flags have different timing which means that
the flags are not coincident. Similarly, the Full and Almost-Full
flags are not coincident because of timing.
These eight internal flags can be assigned to any of four
external flag pins (FLGA-FLGD) through Configuration Register 4 (see Table 10). For the specific flag timings, see
Figures 20-23.
The current state of all eight flags is available in the Status
Register in Status Registerformat 1. In Status Registerformat
0, only four flags can be found in the Status Register (see
Table 8).
5.23
Internal Flag Assigned to Flag Pin
Assignment
Code
0000
A~B
Empty
0001
A~B
Almost-Empty
0010
A~B
Full
0011
A~B
Almost-Full
0100
B~A
Empty
0101
B~A
Almost-Empty
0110
B~A
Full
0111
B~A
Almost-Full
1000
A~B
Empty
1001
A~B
Almost-Empty
1010
A~B
Full
1011
A~B
Almost-Full
1100
B~AEmpty
1101
B~A
Almost-Empty
1110
B~AFull
1111
B~A
Almost-Full
2669 tbl14
Table 10. Configuration Register 4 Internal Flag Assignments to
External Flag Pins.
13
II
10172510,10T72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
Port B Interface
Port B also has parity, reread/rewrite and OMA functions.
Port B can be configured to interface to either Intel-style (RS,
WS) or Motorola-style (OSs, RtWs) devices in Configuration
Register 5 (see Table 11). Port B can also be configured to talk
to a processor or a peripheral device through Configuration
Register 5. In processor interface mode, the Port B interface
controls are inputs. In peripheral interface mode, the Port B
interface controls are outputs. After a hardware reset or a
software Reset All command, Port B defaults to an Intel-style
processor interface; the controls are inputs.
Two 9-bit words are put together to create each 18-bit word
stored in the internal FIFOs. The first 9-bit word written to Port
B goes into the Odd Byte Register shown in the detailed block
diagram. The Odd Byte Register valid bit (Bit 8) in the Status
Register is 1 when this first 9-bit word is written. The data bits
from Port B (OSO-OS7) are also stored in the lower 8 bits of the
Status Register when Status Register format 0 is selected
(see Table 8). The second write on Port B moves the 9-bits
from Port B and the 9-bits in the Odd Byte Register into the
B-7A FIFO and advances the B-7A Write Pointer. The Status
Register valid bit is set to 0 after the second write.
When Port B reads data from the A-7B FIFO, two buffers
choose which 9 of the 18 memory bits are sent to Port B.
These buffers alternate between the upper 9 bits (OA8-0A15,
OA17) and the lower 9 bits (OAO-OA7, OA16). The A-7B Read
Pointer is advanced after every two Port Breads.
The BiFIFO can be set to order the 9-bit data so the first 9-
CONFIGURATION REGISTER 5 FORMAT
Bit
Function
0
Select Port B Interface
0
Pins are RB and WB (Intel-style interface)
As & WB or DSB & RiWB
1
Pins are DSB and R/WB (Motorola-style interface)
Byte Order of 18-bit Word
0
lower byte DA7-DAO and parity DA16 are read or written first on Port
B
1
Upper byte DA15-DAB and parity DA17 are read or written first on
Port B
1
2
3
4
5
Full Flag Definition
Empty Flag Definition
REO Pin Polarity
ACK Pin Polarity
0
Full Flag is asserted when write pointer meets read pointer
1
Full Flag is asserted when write pointer meets reread pointer
0
Empty Flag is asserted when read pointer meets write pointer
1
Empty Flag is asserted when read pointer meets rewrite pointer
0
REO pin active HIGH
1
REO pin active lOW
0
ACK pin active lOW
1
7-6
8
9
10
REO / ACK Timing
2 internal clocks between REO assertion and ACK assertion
01
3 internal clocks between REO assertion and ACK assertion
10
4 internal clocks between REO assertion and ACK assertion
11
5 internal clocks between REO assertion and ACK assertion
RB, WB, and DSB are asserted for 1 internal clock
Port B Read and Write
0
Timing Control for Peripheral Mode
1
RB, WB, and DSB are asserted for 2 internal clocks
Internal Clock
0
internal clock
Frequency Control
1
internal clock
Port B Interface
0
Processor interface mode (Port B controls are inputs)
Mode Control
1
00
12-11
ACK pin active HIGH
00
=ClK
=ClK divided by 2
Peripheral interface mode (Port B controls are outputs)
Stand-alone mode (18- to 9-bits, 36- to 18-bits)
Width Expansion
01
Reserved
Mode Control
10
Slave width expansion mode (36- to 9-bits)
11
Master width expansion mode (36- to 9-bits)
13
Unused
14
Unused
15
Unused
2669 tb115
Table 11. BiFIFO Configuration Register 5 Format
5.23
14
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
CONFIGURATION REGISTER 7 FORMAT
BIT
FUNCTION
0-7
Unused
8
Parity Input Control
0
Disable Parity Generate, Enable Parity Check
B~A
1
Enable Parity Generate, Disable Parity Check
Parity Output Control
0
Disable Parity Generate, Enable Parity Check
A~B
1
Enable Parity Generate, Disable Parity Check
Parity Odd/Even
0
Odd
Control
1
Even
Assign Parity Error to
0
No Parity Error Output
Flag A Pin
1
Parity Error on Flag A Pin
9
10
11
12-15
Unused
2669 tbl16
Table 12. BiFIFO Configuration Register 7 Format
bitsgotothe lSB (DAO-DA7, DA16) orthe MSB (DAB-DA15, DA17)
of Port A. This data ordering is controlled by bit 1 of Configuration Register 5 (see Table 11).
DMA Control Interface
The BiFI FO has DMA control to simplify data transfers with
peripherals. For the BiFIFO DMA controls (REO, ACK and
ClK) to operate, the BiFIFO must be in peripheral interface
mode (Configuration Register 5, Table 11).
DMA timing is controlled by the external clock input, ClK.
An internal clock is derived from this ClK signal to generate
the Rs, Ws, DSs and RIWs output signals. The internal clock
also determines the timing between REO assertion and ACK
assertion. Bit 9 of Configuration Register 5 determines whether
the internal clock is the same as ClK or whether the internal
clock is elK divided by 2.
Bit 8 of Configuration Register 5 sets whether Rs, Ws and
DSs are asserted for 1 or 2 internal clocks. Bits 6 and 7 of
Configuration Register 5 set the number of clocks between
REO assertion and ACK assertion. The clocks between REO
assertion and ACK assertion can be 2, 3, 4 or 5.
Bits 4 and 5 of Configuration Register 5 set the polarity of
the REO and ACK pins, respectively.
A DMA transfer command sets the Port B read/write direction (see Table 5). The timing diagram for DMA transfers is
shown in Figure 17. The basic DMA transfer starts with REO
assertion. After 2 to 5 internal clocks, ACK is asserted by the
BiFIFO. ACK will not be asserted if a read is attempted on an
Empty A-7B FIFO orif a write is attempted on a Full B-7A FIFO.
If the BiFIFO is in Motorola-style interface mode, RIWs is set
at the same time that ACK is asserted. One internal clock later,
DSs is asserted. If the BiFIFO is in Intel-style interface mode,
either Rs or Ws is asserted one internal clock after ACK
assertion. These read/write controls stay asserted for 1 or 2
internal clocks, then ACK, DSs, Rs and Ws are made inactive.
This completes the transfer of one 9-bit word.
On the next rising edge of ClK, REO is sampled. If REO is
still asserted, another DMA transfer starts with the assertion
of ACK. Data transfers will continue as long as REO is
asserted.
Parity Checking and Generation
Parity generation or checking is performed by the BiFIFO
on data passing through Port B. Parity can either be odd or
even as determined by Bit 10 of Configuration Register 7.
When parity checking is enabled, DSB is treated as a data
bit. DSB data will be passed to DA16 (bypass operation) or stored
in the RAM array (FI FO operation) for 8->A operation; similarly,
DA16 or parity bits from the RAM array will be passed to DSB
for A->B operations. A->B read parity errors and B->A write
parity errors are shown in Bit 9 and 10 in the Status Register.
If an external parity error signal is required, a logical OR of the
INTERNAL FLAG TRUTH TABLE
Number of Words in FIFO
From
To
Empty Flag
Almost-Empty Flag
Almost-Full Flag
Full Flag
0
0
Asserted
Asserted
Not Asserted
Not Asserted
1
n
Not Asserted
Asserted
Not Asserted
Not Asserted
n+1
D-(m+1)
Not Asserted
Not Asserted
Not Asserted
Not Asserted
D-m
D-1
Not Asserted
Not Asserted
Asserted
Not Asserted
D
D
Not Asserted
Not Asserted
Asserted
Asserted
NOTE:
1. SiFIFO flags can be assigned to external flag pins to be observed. D =FIFO depth (IDT72510 =512, IDT72520 =1024),
n =Almost-Empty flag offset, m =Almost-Full flag offset.
Table 13. Internal Flag Truth Table.
5.23
2669 tbl17
15
II
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
two parity error bits is brought out to FLGA pin by setting Bit 11
of Configuration Register 7.
Parity generation creates the ninth bit. This ninth bit is
placed on DB8 for A->B read operation, and on DA16 or RAM
array for B->A write operation.
It is recommended that ifthe parity pins (DB8, DA16, and DA17)
are not used, they should be pulled down with 10K resistors
for noise immunity.
Intelligent rereadlrewrite is a method the BiFIFO uses to
help assure data integrity. Port B of the BiFIFO has two extra
painters, the Reread Pointer and the Rewrite Pointer. The
Reread Pointer is associated with the A->B FIFO Read
Pointer, while the Rewrite Pointer is associated with the B->A
FIFO Write Pointer. The Reread Pointer holds the start address of a data block in the A->B FIFO RAM, and the Read
Pointer is the current address of the same FIFO RAM array.
By loading the Read Pointer with the value held in the Reread
Pointer (RER asserted), reads will start over at the beginning
of the data block. In order to mark the beginning of a data
block, the Reread Pointer should be loaded with the Read
Pointer value (LDRER asserted) before the first read is
performed on this data block. Figure 6 shows a Reread
operation.
Similarly, the Rewrite Pointer holds the start address of a
data block in the B->A FIFO RAM, while the Write Pointer is
the current address within the RAM array. The operation of the
REW and LDREW is identical to the RER and LDRER discussed above. Figure 7 shows a Rewrite operation.
For the reread data protection, Bit 2 of Configuration
Register 5 can be set to 1 to prevent the data block form being
overwritten. In this way, the assertion of A->B full flag will occur
when the write pointer meets the reread pointer instead of the
read pointer as in the normal definition. For the rewrite data
protection, Bit 3 of Configuration Register 5 can be set to 1 to
prevent the data block from being read. In this case, the
assertion of B->A empty flag will occur when the read pointer
meets the rewrite pointer instead of the write pointer.
In conclusion, Bit 2 and 3 of Configuration Register 5 are
used to redefine Full & Empty flags for data block partition.
Although it can serve the purpose of data protection, the
setting of these 2 bits is independent of the functions caused
by RER/REW, or LDRER/LDREW assertions.
REREAD OPERATIONS
REWRITE OPERATIONS
Intelligent Reread/Rewrite
(1,2)
(3,4)
Reread
Pointer
Write
Pointer
Write
Pointer ~
k
Load
Reread
function
Read
Pointer
Rewrite
function
2669 drw 08
NOTES:
1. If bit 2 is set to 1,
Empty flag asserted if Read Write
Full flag asserted if Reread + FIFO size Write
2. If bit 2 is set to 0,
Empty flag asserted if Read =Write
Full flag asserted if Read + FIFO size Write
=
=
=
NOTES:
1. If bit 3 is set to 1,
Empty flag asserted if Read = Rewrite
Full flag asserted if Read + FIFO size =Write
2. If bit 3 is set to 0,
Empty flag asserted if Read Write
Full flag asserted if Read + FIFO size =Write
2669 drw 09
=
Figure 6. BiFIFO Reread Operations
Figure 7. BiFIFO Rewrite Operations
5.23
16
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Commercial
Unit
Terminal
Voltage with
Respect to
Ground
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
°C
TSIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Stotage
Temperature
-55 to +125
°C
lOUT
DC Output
Current
50
mA
VTERM
Rating
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input HIGH
Voltage
2.0
-
-
V
VIL(1)
Input LOW Voltage
-
-
0.8
NOTE:
1. 1.SV undershoots are allowed for 1Ons once per cycle.
Unit
V
2669 tbl19
NOTE:
2669tbl18
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vec = 5V ± 10%, TA
11
=ODC to +70DC)
IDT72510L
IDT72520L
Commercial
tA
=25, 35, 50 ns
Max.
Unit
IIL(1)
Input Leakage Current (Any Input)
-1
-
1
IOL(2)
Output Leakage Current
-10
10
Il A
Il A
VOH
Output Logic "1" Voltage I OUT
VOL
Output Logic "0" Voltage lOUT
-
-
0.4
V
lec1(3)
Average Vcc Power Supply Current
-
150
220
mA
Icc2(3)
Average Standby Current (Rs
VIH)
-
16
30
mA
Symbol
Typ.
Min.
Parameter
=-1 mA
=4mA
2.4
=Ws =DSA =
-
V
2669 tbl20
NOTES:
1. Measurements with O.4V $; VIN $; vee, DSA = DSB ~ VIH.
2. Measurements with O.4V $; VOUT $; vee, DSA = DSB ~ VIH.
3. Measurements are made with outputs open. Tested at f = 20 MHz.
+5V
AC TEST CONDITIONS
1.1 kn
GNDto 3.0V
Input Pulse Levels
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
D.U.T.
See Figure 8
30 pF
680n
*
2669 tbl21
CAPACITANCE (TA =+25 C, f = 1.0MHz)
D
Symbol
Parameter
CIN(2)
Input Capacitance
COUT(1.2)
Output Capacitance
Conditions
Max.
Unit
VIN =OV
8
pF
VOUT= OV
12
pF
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
2669 drw 10
2669 tbl22
or equivalent circuit
Figure 8. Output Load
* Includes jig and scope capacitances
5.23
17
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: VeC= 5V±10%, TA = O°C to +70°C)
Commercial
Symbol
Parameter
IDT12510l25
IDT12510l35
IDT12520l25
IDT12520l35
Min.
Max.
Min.
Max.
IDT12510l50
IDT12520l50
Min.
Max.
Timing
Unit
Figure
RESET TIMING (Port A and Port B)
tRSC
Reset cycle time
35
-
45
-
65
9
Reset pulse width
25
-
35
50
ns
9
tRSS
Reset set-up time
25
-
35
50
-
ns
9
tRSR
Reset recovery time
10
-
10
-
-
ns
tRS
15
-
ns
9
tRSF
Flag reset pulse width
-
35
-
45
-
65
ns
9
-
PORT A TIMING
taA
Port A access time
-
25
-
35
tall
Read or write pulse
LOW to data bus at
Low-Z
5
-
5
-
taHz
Read or write pulse
HIGH to data bus at
High-Z
-
15
-
20
taov
Data valid from read
pulse HIGH
5
-
5
taRc
Read cycle time
35
Read pulse width
25
taRR
Read r~covery time
10
tas
CSA, Ao, A1, RNJA setuptime
5
-
45
taRPW
taH
CSA, Ao, A1, RNJA hold
time
5
taos
Data set-up time
15
taoH (1)
Data hold time
0
50
ns
12,14,15
-
ns
12,15,16
-
30
ns
12,14,15,16
-
5
-
ns
12, 14, 16
65
-
ns
12
50
12, 14, 15
ns
12
5
-
5
-
ns
10
-
ns
10,12,16
-
5
-
5
-
ns
10, 12
-
18
-
30
-
ns
11, 12, 14, 15
5
-
ns
11,12,14,15
65
-
ns
12
ns
11, 12, 14
15
-
ns
12
50
-
ns
11
35
0
tawc
Write cycle time
tawpw
Write pulse width
25
tawR
Write recovery time
10
-
35
10
-
tawRCOM
Write recovery time after
a command
25
-
35
-
35
45
5
15
50
NOTE:
1. The minimum data hold time is 5ns (10ns for tha 80ns speed grade) when writing to the Command or Configuration registers.
5.23
2669 tbl23
18
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: \tc= SV±10%, TA = DoC to +70°C)
Commercial
Symbol
Parameter
IDT72510l25
IDT72510L35
IDT72520l25
IDT72520l35
Min.
IDT72510l50
IDT72520l50
Timing
Max.
Min.
Max.
Min.
Max.
Unit
Figure
PORT B PROCESSOR INTERFACE TIMING
tbAl
Port B access time with
no parity
-
25
-
35
-
50
ns
13,14,15
tbA2
Port B access time with
parity
-
30
-
42
-
60
ns
13, 14, 15
tbLZ
Read or write pulse
lOW to data bus at
Low-Z
5
-
5
-
5
-
ns
13,14,15
tbHZ
Read or write pulse
HIGH to data bus at
High-Z
-
15
-
20
-
30
ns
13,14,15
tbov
Data valid from read
pulse HIGH
5
-
5
-
5
-
ns
13,14,15,16
tbRC
Read cycle time
45
-
tbRR
Read recovery time
35
10
65
50
15
13
13
13
30
-
ns
Read pulse width
35
25
10
-
tbRPW
ns
13
13
13,14,15
tbs
R/WB set-up time
tbH
R/WB hold time
tbOSl
Data set-up time with no
parity
tbOHl
Data hold time with no
parity
tbOS2
Data set-up time with
parity
tbOH2
Data hold time with
parity
tbwc
Write cycle time
tbwpw
Write pulse width
tbWR
Write recovery time
-
5
5
-
18
-
0
-
0
-
5
-
ns
13. 14. 15
18
-
22
-
35
-
ns
13.14, 15
0
-
0
-
5
-
ns
13,14,15
35
25
10
-
45
-
35
10
-
65
50
15
-
ns
-
ns
13
13,15
13
5
5
15
-
5
5
ns
ns
ns
ns
ns
PORT B PERIPHERAL INTERFACE TIMING
tbAl
Port B access time with
no parity
-
25
-
40
-
55
ns
17
tbA2
Port B access time with
parity
-
30
-
42
-
60
ns
17
tbCKC
Clock cycle time
15
-
tbCKL
Clock pulse LOW time
Request set-up time
-
ns
17
tbREQH
Request hold time
-
17
17
17
tbREQS
10
10
10
-
ns
6
6
5
5
20
6
6
5
5
25
Clock pulse HIGH time
-
-
tbCKH
5
-
ns
17
tbAcKL
Delay from a rising clock
edge to ACK switching
-
15
-
18
-
25
ns
17
ns
ns
2669tbl24
5.23
19
II
IDT72510,IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V±1 0%, TA =O°C to +70°C)
Commercial
Parameter
Symbol
IDT12510l25
IDT12510l35
IDT12520l25
IDT12520l35
Min.
IDT12510l50
IDT12520l50
Max.
Min.
Max.
Min.
Max.
Timing
Unit
Figure
PORT B RETRANSMIT and PARITY TIMING
tbDSBH
RER, REW, LDRER,
LDREW set-up and
recovery time
10
-
10
-
15
-
ns
9, 18
tbPER
Parity error time
20
-
25
-
30
-
ns
19
-
15
-
20
ns
16
15
-
30
10
20
ns
BYPASS TIMING
tBYA
Bypass access time
tBYD
Bypass delay
taBYDV
Bypass data valid time
from DSA
15
-
15
-
15
-
ns
16
16
tbBYDV (3)
Bypa~data valid time
fromDSB
3
-
3
-
3
-
ns
16
FLAG TIMING
tREF
Read clock edge to
Empty Flag asserted
-
25
-
35
-
45
ns
14,15,20,22
tWEF
Write clock edge to
Empty Flag not asserted
-
25
-
35
-
45
ns
14,15,20,22
tRFF
Read clock edge to Full
Flag not asserted
-
25
-
35
-
45
ns
14,15,21,23
tWFF
Write clock edge to Full
Flag asserted
-
25
-
35
-
45
ns
14,15,21,23
tRAEF
Read clock edge to
Almost-Empty Flag
asserted
-
40
-
50
-
60
ns
20,22
tWAEF
Write clock edge to
Almost-Empty Flag not
asserted
-
40
-
50
-
60
ns
20, 22
tRAFF
Read clock edge to
Almost-Full Flag not
asserted
-
40
-
50
-
60
ns
21,23
tWAFF
Write clock edge to
Almost-Full Flag
asserted
-
40
-
50
-
60
ns
21,23
NOTES:
266911:>1 25
1. Read and Write are intemal signals derived frofnS\, RMiA, DSB, RJWB, RB, andWB.
2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are intemal flags, the timing given is for those assigned to external pins.
3. Values guaranteed by design, not currently tested.
5.23
20
10172510,10T72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
~I------- tRSC -------~
tRS -----tII~
Ws, RB
(or RlWs, DS3)
LDRER
LDREW
REO
DSA
FLGA,
FLGc
FLGs ..
FLGD
2669 drw 11
Figure 9. Hardware Reset Timing for 10T7251 0/520
5.23
21
10172510, 10172520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
Ao, A1
tas
2669 drw 12
Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing)
\-----~/
\'-----tWRCOM
Opcode
DAB-DA12
or
Operand
OAO-OA2
2669 drw 13
taos
taoH
Figure 11. Port A Command Timing (Write)
5.23
22
IDTI2510, IDTI2520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
WRITE
~~----- tawc------~~
DSA
tas
taH
Input
DAD - [)I.17
taDs
taDH
READ
RiWA
taRe
DSA
tas
Output
DAD - [)I.17
Figure 12. Read and Write Timing for Port A
5.23
23
IDT72510, 1DT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
WRITE
(R/WB)
iNB
(or DSB)
-
)~
-
~
tbs
~
-
tbOS1 or tbOS2
...,l
I
tbwpw
.. IL-
V
Input
DBo-DBa
...
tbwc
~
tbwR~
...
If-
1
tbH
J
..
. ../!
/
tbOH1 ortbOH2
NOTES:
1. tbDS1 and tbDH1 are with parity checking or if parity is ignored, tbDS2 and tbDH2 are with parity generation.
2. RB 1
=
(RMiB)
i " ' l l 1 I - - - - - tbRC -----tl~
RB
(or DSB)
tbs
Output
DBo-DBa
tbLZ .
tbA1 or tbA2
NOTES:
1. tbA 1 is with parity checking or if parity is ignored, tbA2 is with parity generation.
2. RB 1
.
=
Figure 13. Port B Read and Write Timing. Processor Interface Mode Only
5.23
24
10172510,10172520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
AJES FIFO WRITE FLOW-THROUGH
OSA
DAO-DA17
A~B
Full Flag (1)
1 4 - - tRFF - -........I---I~ tWFF
RB (or
DS3)
DBO-DBB
~tbHZ~
1 4 - -___... 1 tbA1 or tbA2(2)
II
NOTES:
1. Assume the flag pin is programmed active LOW.
2. tbA1 is with parity checking or if parity is ignored, tbA2 is with parity
generation.
3. RlWA =0
BJEA FIFO READ FLOW·THROUGH
OSA
tall
DAO-DA17
B~A
Empty Flag (~)
WB (or
DS3)
DBO-DBB
DATA INPUT
2669 drw 16
NOTES:
1. Assume the flag pin is programmed active LOW.
2. tbDS1 & tbDH1 are with parity checking or if parity is ignored, tbDS2 &
tbDH2 is with parity generation.
3. RlWA= 1
Figure 14. Port A Read and Write Flow-Through Timing. Processor Interface Mode Only
5.23
25
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
BJEA FIFO WRITE FLOW-THROUGH
taA ....---.~I
~---taHz----.~1
B-tA
Full Flag(1)
tRFF ~----II~""--~
~---~tWFF
WB(orOSB) - - -......
DBo-DBa
tbOS1 or tbOS2 (2)
tboH10rtboH12
NOTES:
1. Assume the flag pin is programmed active LOW.
2. tbDS1 & tbDH1 are with parity checking or if parity is ignored, tbDS2 &
tbDH2 are with parity generation.
3. R1WA=1
(2)
AJEB FIFO READ FLOW-THROUGH
DAD-OA17
taos
14-"~-_~1
taoH
A--tB
Empty Flag (~)
~_t_W_E_F-.~~_ _~tbRPW
RB (orOSB)
DBo-DBa
NOTES:
1. Assume the flag pin is programmed active LOW.
2. tbA 1 is with parity checking or if parity is ignored, tbA2 is with parity
generation.
3. RlWA= 0
2669 drw 17
Figure 15. Port B Read and Write Flow-Through Timing
5.23
26
10172510,10172520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
_____________________________________
B~AREADBYPASrS
RfiJA
DAO-DA7,
DA16
(RNVB)
___________jt}/ __ IBYo
DBO-DBB
BYTE 0
=>K
BYTE 1
)>-----C(""_____B_YT_E_2_ _ _ __
NOTES:
1. Once the bypass starts, any data changes on Port B bus (Byte 0 JEByte
1) will be passed to Port A bus.
2. WB= 1.
A~B
WRITE BYPASS
DAO-DA7,
DA16
WB(2) (or DSB)
(RtWs)
DBO-DBB
2669 drw 18
NOTES:
1. Once the bypass starts, any data changes on Port A bus (Byte 0 JEByte
1) will be passed to Port B bus.
2. RB
=1.
Figure 16. Bypass Path Timing. BiFIFO Must be in Peripheral Interface Mode
5.23
27
10172510,10172520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
SINGLE WORD DMA TRANSFER
~
2 to 5 cycles
1 to 2 cycles
tCKC~
tCKH
elK
~ltCKL
REO
tREQS
14-~~--Ir..t
tREQH
WRITE
(R/WB)
tACKL
WB (orOSB)
tACKL
Output
OBO-OB17
tbLZ ~-~I
1·.4---....~1 tbov
~ tbHz ~
tbA1 or tbA2
READ
(R/WB)
RB (orOSB)
tACKL
tACKL
Input
OBO-OB17
NOTES:
1. tbA 1, tbDS1 and tbDH1 are with parity checking or if parity is ignored, tbA2
& tbDS2 and tbDH2 are with parity.
tbOSl or tboS2 1 4 - -. . . . .- - + 1 tboHl or tbOH2
1 to 2
1 to 2
cycles
H
REO
ACK, R/WB
RB, ViiB (orOSB)
J
BLOCK QMA TRANSFrER
I
I
I
"
I
I
I
I
V
--i---~,
I
"
1/
--'---~.I
2669 drw 19
Figure 17. Port B Read and Write DMA Timing. Peripheral Interface Mode Only
5.23
28
IDT72510. IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
As, Ws
(or Rfiiis. OSs)
tbOSSH
tbWPWH
tbOSSH
LORER,
LOREW
2669 drw 20
Figure 18. Port B Reread and Rewrite Timing for Intelligent Retransmit
SET PARITY ERROR: FLGA IS ASSIGNED AS
THE PARITY ERROR PIN
RiWs
~~
J~
'------------------------------
tbH fooI__- - - I..~
i"I.......- - I I...~ tbs
~~/~
As, Ws (orOSs)
'---------'
'''-4.-.--- tPER - - -....,~ •
FLGA _______________________________
~~~-------------
CLEAR PARITY ERROR: COMMAND WRITTEN INTO PORT A CLEARS PARITY ERROR
ON FLGA PIN
RiWA
~~'-
/
~£
'-----------------------------~
i"I-I---~"
taH i"I-._---II
....~
tas
~"'--------'7 K
_____________________________________'_-4_______t_PE_R_=1
FLGA
~-------------
2669 drw21
NOTE:
1. FLGA is the only pin that can be assigned as a parity error output.
Figure 19. Port B Parity Error Timing
5.23
29
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
Read
--------------------------~\~------------------------~
Ir
Write
_ WB
(or
RtW~~~)
B~A
Empty Flag
~
tWEF
------t
~
tRAEF
B~AAlmost
Empty Flag
~------------~'~(----------2669 drw 22
Figure 20. Empty and Almost-Empty Flag Timing for BJEA FIFO. (n
= Programmed Offset)
NOTES:
1. BJEA FIFO is initially empty.
2. Assume the flag pins are programmed active LOW.
3. For stand-alone mode only; in a 36- to 9-bit configuration, Port Breads
must be doubled.
4. RfWA= 1
Read
--------------------------~\~------------------~
_ WB
(or RM'B=O,
DSB)
B~AAlmost
Full Flag
Write
1
2m+ 1
2
3
4
1{:'WAFF
\~----~------------------r_----------_; r - - - r - -
B~A
Full Flag
2669 drw 23
Figure 21. Full and Almost-Full Flag Timing for BJEA FIFO. (m
=Programmed Offset)
NOTES:
1. BJEA FIFO initially contains D-(M+1) data words. D 512 for IDT72510;
D 1024 for IDT72520.
2. Assume the flag pins are programmed active LOW.
3. For stand-alone mode only; in a 36- to 9-bit configuration, Port Breads
must be doubled.
4. RlWA= 1
=
=
5.23
30
IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
OSA
COMMERCIAL TEMPERATURE RANGE
Write
~ . r---l
L2-.J
~~
I--------------------------------~\'~t--------------~
L2.J
Read
RB
(or WB=1, OS B)
A~B
Empty Flag
A~B
Almost-Empty Flag
______________________
~\~----~J
2669 drw24
Figure 22. Empty and Almost-Empty Flag Timing for A.lEB FIFO. (n
=Programmed Offset)
NOTES:
1. AlES FIFO is initially empty.
2. Assume the flag pins are programmed active LOW.
3. For stand·alone mode only; in a 36- to 9-bit configuration, Port S reads
must be doubled.
4. RlWA= 1
~Write r---l
~
~~
II
I--------------------------------~\'~<----------------
I..!!!ill
u.J
Rs
~~+112~~
UO
(or WB=1, OSB)
B~A
Almost- Full
Flag
' -____
tW_A_F_F__
~~~--~------------------_;--~--------~~
tWFF
---------~ "'\~C--------------
B~A Full
Flag
2669 drw 25
Figure 23. Full and Almost-Full Flag Timing for AJEB FIFO. (m
=Programmed Offset)
NOTES:
1. AlES FIFO initially contains D-(M+ 1) data words. D 512 for IDT 7251 0;
D 1024 for IDT72520.
2. Assume the flag pins are programmed active LOW.
3. For stand-alone mode only; in a 36- to 9-bit configuration, Port S reads
must be doubled.
4. RlWA=O
=
=
5.23
31
IDTI2510,IDTI2520
BUS MATCHING BIDIRECTIONAL FIFO
lOT
COMMERCIAL TEMPERATURE RANGE
xxxxx
L
xx
J
Device
Type
Power
Speed
Package
Process!
Temperature
Range
I
I Blank
Commercial (O°C to +70°C)
:J
Plastic Leaded Chip Carrier
25
35
50
~
I
L
}
Commerical Only
Access Time (fA)
in ns
Low Power
I 72510
512 x 18 -to-1024 x 9 BiFIFO
I 72520
1024 x 18 -to- 2048 x 9 BiFIFO
2669 drw26
5.23
32
~
IDT72511
IDT72521
PARALLEL BIDIRECTIONAL FIFO
X 18 & 1024 x 18
512
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Two side-by-side FIFO memory arrays for bidirectional
data transfers
• 512 x 18-Bit - 512 x 18-Bit (IOT72511)
• 1024 x 18-Bit - 1024 x 18-Bit (I OT72521 )
• 18-bit data buses on Port A side and Port B side
• Can be configured for 18-to-18-bit or 36-to-36-bit communication
• Fast 35ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Two programmable flags, Almost-Empty and Almost-Full
for each FI FO
• Programmable flag offset can be set to any depth in the
FIFO
• Any of the eight flags can be assigned to four external
flag pins
• Flexible reread/rewrite capabilities
• Six general-purpose programmable I/O pins
• Standard OMA control pins for data exchange with
peripherals
• 68-pin PGA and PLCC packages
The IOT72511 and I0T72521 are highly integrated first-in,
first-out memories that enhance processor-to-processor and
processor-to-peripheral communications. lOT 8iFIFOs integrate two side-by-side memory arrays for data transfers in
two directions.
The 8iFIFOs have two ports, A and 8, that both have
standard microprocessor interfaces. All 8iFIFO operations
are controlled from the 18-bit wide Port A. Port 8 is also 18
bits wide and can be connected to another processor or a
peripheral controller. The BiFIFOs have a 9-bit bypass path
that allows the device connected to Port A to pass messages
directly to the Port B device.
Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration
Registers.
The lOT BiFIFO has programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight internal flags can be assigned to any of four external flag pins
(FLGA-FLGD) through one Configuration Register.
Port B has programmable I/O, reread/rewrite and OMA
functions. Six programmable I/O pins are manipulated through
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
Data
Data
Port
Port
A
8
I/O
....~....~ Control
Control
Handshake
Interface
...........-~.~ DMA
Flags
2668 drw 01
The lOT logo is a registered trademark of Integrated Device Techology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
AUGUST 1993
DSC-2031/5
5.24
1
II
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
two Configuration Registers. The Reread and Rewrite controls
will read or write Port B data blocks multiple times. The
BiFIFO has three pins, REO, ACK and ClK, to control DMA
transfers from Port B devices.
PIN CONFIGURATIONS
11
DB17 FlGB FlGo
DB13
DB14
DB15 FlGA FlGe
10
DB11
DB12
09
DB9
08
DA13
DA14 DA12
DA11
PI04
DB10
DA9
DA10
GND
DB8
PI03
DA8
07
-RB
GND
06
WB
Vce
G68-1
Vec
DSA
05
DB7
DB16
PGA
TOP VIEW
GND
RS
04
DB5
DB6
PI02 LORE....
03
DB3
DB4
DA7
DA16
02
DB2
DB1
ClK
REO
DA6
01
•
DBO
ACK
REW GND
/A
DA17
DA15
PI05
PIN1
DESIGNATOR
A1
Ao
GND LORER
8
C
o
-RER RlWA
CSA
F
E
PIOo
DAD
DA2
DA5
PI01
DA1
DA3
OM
J
K
G
H
l
2668 drwO~
INDEX
~
DA5
DA6
DA7
DA16
PI02
lDREW
GND
RS
Vee
DSA
GND
lDRER
PI03
DA8
DA9
DA10
PI04
...... ........,..-........,......., - - " ' 1
I ............... ......., .................................
9 8 7 6 5 4 3 2 I I 68 67 66 65 64 63 62 61
] 10
60 [ DB2
] 11
59 [ DB3
58 [ DB4
] 12
] 13
57 [ DB5
] 14
56 [ DB6
55 [ DB7
] 15
] 16
54 [ DB16
] 17
53 [ WB (RJWB)
] 18
J68-1
52 [ Vee
] 19
51 [ RB(DSB)
]w
~[ GND
] 21
PLCC
49 [ GND
] 22
TOP VIEW
48 [ DB8
J~
Q[ DB9
]M
~[ DBlO
]~
~[ DB11
]~
«[ DB12
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
'1
~~~~~~~~~~~~~~~~~
2668 drw 03
5.24
2
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
I/O
1/0
Description
DAD-DA17
Data A
CSA
Chip Select A
I
Port A is accessed when Chip Select A is LOW.
DSA
Data Strobe
A
I
Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is
read out of Port A on the falling edge of Data Strobe when Chip Select is LOW.
RIWA
ReadlWrite A
I
This pin controls the read or write direction of Port A. When CSA is LOW and RIWA is HIGH,
data is read from Port A on the falling edge of DSA When CSA is LOW and RiWA is LOW, data
is written into Port A on the rising edge of DSA.
Ao, A1
Addresses
I
When Chip Select A is asserted, Ao, A1, and ReadlWrite A are used to select one of six internal
resources.
Dso-Ds17
Data B
Rs (DSs)
Read B
10rO If Port B is programmed to processor mode, this pin functions as an input. If Port B is
programmed to peripher~ mode this pin functions as an output. This pin can function as part of
an Intel-style interface (As) or as part of a Motorola-style interface (DSs). As an Intel-style
interface, data is read from Port B on a falling edge of Rs. As a...,Motorola-style interface, data is
read on the falling edge of DSs..,9r written on the rising edge of DSs through Port B. The default
is Intel-style processor mode. (Rs as an input).
Ws(RlWs)
Write B
10rO If Port B is programmed to processor mode, this pin functions as an input. If Port B is
programmed to peripher~ mode this pin functions as an output. This pin ~n function as part of
an Intel-style interface (Ws) or as part of a Motorola~tyle interface (R/Ws). As an Intel-style
interface--,---data is written to Port B ~ a rising edge of Ws. As a Motorola-style interface, data is
read (RlWs = HIGH) or written (RlWs = LOW) to Port B in conl.!:!nction with a Data Strobe B
falling or rising edge. The default is Intel-style processor mode (Wsas an input.)
RER
Reread
I
Loads
A~B
FIFO Read Pointer with the value of the Reread Pointer when LOW.
REW
Rewrite
I
Loads
~A
FIFO Write Pointer with the value of the Rewrite Pointer when LOW.
LDRER
Load Reread
I
Loads the Reread Pointer with the value of the
1/0
Data inputs and outputs for the 18-bit Port A bus.
Data inputs and outputs for the 18-bit Port B bus.
A~B
FIFO Read Pointer when HIGH.
LDREW
Load Rewrite
I
Loads the Rewrite Pointer with the value of the B~A FIFO Write Pointer when HIGH.
REO
Request
I
When Port B is programmed in peripheral mode, asserting this pin begins a data transfer.
Request can be programmed either active HIGH or active LOW.
ACK
Acknowledge
0
When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a
Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed
either active HIGH or active LOW.
CLK
Clock
I
This pin is used to generate timing for ACK, Rs, WB, DSs and RlWs when Port B is in the
peripheral mode.
FLGAFLGD
Flags
0
These four outputs pins can be assigned anyone of the eight internal flags in the BiFIFO. Each
of the two internal FIFOs (A~B and B~A) has four internal flags: Empty, Almost-Empty,
Almost-Full and FUll.
PIOo-PIOs
Programmabie Inputsl
Outputs
1/0
Six general purpose I/O pins. The input or output direction of each pin can be set independently.
I
A LOW on this pin will perform a reset of all BiFIFO functions.
RS
Reset
Vee
Power
There are two +5V power pins.
GND
Ground
There are five Ground pins at OV.
2668 tbl 01
5.24
3
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCI.AL TEMPERATURE RANGES
DETAILED BLOCK DIAGRAM
GsA
DSA
RiWA
A1
PortA
Control
A~
BFIFO
18
18
Port B
Control
I
I
I
I
I
I
I
I
I
I
Ao
Bypass Path
lDRER
lDREW
RER
REw
Rs(DSs) ==
'Ws(RJWs) ==
PortA
Port B
DAo-DA17
Dso-Ds17
B~
A FIFO
18
18
16
FlGA*~--~------------~
FlGB*
Programmable
-FlGC
Flag logic
FlGD ____-----,_ _ _ _-1
Command
~ RS
L..-_R_e_s_e_t_ .....
Status
Configuration 0
H
~_o!,~~U!~t~o_n_ ~
I
I
Configuration 2
----------_C_o!'~~~~t~o_n_~
?_o!'~~U!~t~o_n_~
?_o!,~~U!~t~o_n_~
~REQ*
ACK*
ClK
L.....------I
I
____________ l I
Configuration 5
-----------
DMA
Control
Programmable
~
I/O Logic
J-oIII-----------...
Configuration 7
NOTES:
PI05 ==
PI04==
PI03 ==
PI02 ==
PI01 ==
PIOO ==
2668 dlW04
(*) Can be programmed either active high or active low in internal configuration registerers.
(tt) Can be programmed through an internal configuration register to be either an input or an output.
5.24
4
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
lOT's BiFIFO family is versatile for both multiprocessor
and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the lOT
BiFIFO, making simUltaneous data exchange possible. Each
FIFO is monitored by separate internal read and write pointers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor connected to Port A of the BiFIFO can send or receive messages directly to the Port B device using the BiFIFO's 9-bit
bypass path.
The BiFIFO can be used in different bus configurations:
18 bits to 18 bits and 36 bits to 36 bits. One BiFIFO can be
used for the 18- to 18-bit configuration, and two BiFIFOs are
required for 36- to 36-bit configuration. This configuration
can be extended to wider bus widths (54- to 54-bits, 72- to
72-bits, ... ) by adding more BiFIFOs to the configuration.
The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed
in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device
is connected to the BiFIFO, Port B is programmed to peripheral interface mode and the interface pins are outputs.
18- to 18-bit Configurations
A single BiFIFO can be configured to connect an 18-bit
processor to another 18-bit processor or an 18-bit peripheral.
The upper BiFIFO shown in each of the Figures 1 and 2 can
be used in 18- to 18-bit configurations for processor and
peripheral interface modes respectively.
36- to 36-bit Configurations
In a 36- to 36-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 18
data bits to each device. Figures 1 and 2 show multiple
BiFIFOs configured for processor and peripheral interface
modes respectively.
Processor Interface Mode
When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B interface controls are inputs. Both REQ and elK pins should be
pulled lOW to ensure that the setup and hold time requirements for these pins are met during reset. Figure 1 shows
the BiFIFO in processor interface mode.
lOT
BiFIFO
Processor
B
Processor
A
2668 drw05
Figure 1. 36-Bit Processor to 36-Bit Processor Configuration
NOTE:
1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, Al, Ao, AI
WA, and DSA; Cntl B refers to RIYlB and DSB or and WB.
Be
5.24
5
II
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Peripheral Interface Mode
If Port B is connected to a peripheral controller, all
BiFIFOs in the configuration must be programmed in peripheral interface mode. In this mode, all the Port B interface
pins are all outputs. To assure fixed high states for Rs and
Ws before they are programmed into an output, these two
pins should be pulled up to vcc with 10K resistors. Of
course, only one set of Port B interface pins should be used
to control a single peripheral device, while the other interface
pins are all ignored. Figure 2 shows a BiFIFO configuration
connected to a peripheral.
Port A Interface
The BiFIFO is straightforward to use in microprocessorbased systems because each BiFIFO port has a standard
microprocessor control set. Port A has access to six resources: the A~B FIFO, the B~A FIFO, the 9-bit direct data
bus (bypass path), the configuration registers, status and
command registers. The Port A Address and ReadlWrite
pins determine the resource being accessed as shown in
Table 1. Data Strobe is used to move data in and out of the
BiFIFO.
When either of the internal FIFOs are accessed, 18 bits of
data are transferred across Port A. Since the bypass path is
only 9 bits wide, the least significant byte (DAO-DA7, DA16) is
used on Port A. All of the registers are 16 bits wide which
means only the data bits (DAO-DA1S) are passed by Port A.
Bypass Path
The bypass path acts as a bidirectional bus transceiver
directly between Port A and Port B. The direct connection
requires that the Port A interface pins are inputs and the Port
B interface pins are outputs. The bypass path is 9 bits wide in
an 18- to 18-bit configuration or 18 bits wide in a 36- to 36bit configuration.
During bypass operations, the BiFIFOs must be programmed into peripheral interface mode. Bit 10 of Configuration Register 5 (see Table 10) is set to 1 for peripheral
interface mode.
Command Register
Ten registers are accessible through Port A, a Command
Register, a Status Register, and eight Configuration
Registers.
lOT
BiFIFO
Peripheral
Controller
Cntl
ACK
REO
lOT
BiFIFO
1","~\--1..""'" Data
36
110
Data
2668 drw06
Figure 2. 36-Bit Processor to 36-Bit Peripheral Configuration
NOTE:
1. 36- to 36-bit peripheral interface configuration. Upper SiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, Al, Ao, RI
WA, and DSA; Cntl B refers to R!Ws and DSB or Be and We.
5.24
6
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The Command Register is written by setting CSA = 0, A1 =
1, Ao = 1. Commands written into the BiFIFO have a 4-bit
opcode (bit8 - bit 11) and a 3-bit operand (bit 0 - bit 2) as
shown in Figure 3. The commands can be used to reset the
BiFIFO, to select the Configuration Register, to perform intelligent reread/rewrite, to set the Port B DMA direction, to set
the Status Register format, and to modify the Port BRead
and Write Pointers. The command opcodes are shown in
Table 2.
The reset command initializes different portions of the
BiFIFO depending on the command operand. Table 3 shows
the reset command operands.
The configuration Register address is set directly by the
command operands shown in Table 4.
Intelligent reread/rewrite is performed by interchanging
the Port B Read Pointer with the Reread Pointer or by
interchanging the Port B Write Pointer with the Rewrite Pointer.
No command operands are required to perform a reread/
rewrite operation.
When Port B of the BiFIFO is in peripheral mode, the DMA
direction is controlled by the Command Register. Table 5
shows the Port Bread/write DMA direction operands.
Two commands are provided to increment the Port BRead
and Write Pointers. No operands are required for these
commands.
COMMAND FORMAT
12
15
x
x
x
x
11
8
Command Opcode
3
7
x
x
x
x
x
o
2
Command Operand
I
2668 tbl 02
Figure 3. Format for Commands Written into Port A
EI
5.24
7
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Reset
The IDT72511 and IDT72521 have a hardware reset pin
(BS) that resets all BiFIFO functions. A hardware reset requires the following four conditions: BsandWs mustbe HIGH,
REB and REW must be HIGH, LDRER and LDREW must be
LOW, and QSA must be HIGH (Figure 9). After a hardware
reset, the BiFIFO is in the fOllowing· state: Configuration
Registers 0-3 are OOOOH, Configuration Register 4 is set to
6420H, and Configuration Registers 5, 6 and 7 are OOOOH.
Additionally, all the pointers including the Reread and Rewrite
Pointers are set to 0, the DMA direction is set to B~A write,
and the internal DMA request circuitry is cleared (set to its
initial state).
A software reset command can reset A~B pointers and the
B~A pointers to 0 independently or together. The internal
At
Ao
0
0
0
Read
B~AFIFO
1
9-bit Bypass Path
9-bit Bypass Path
1
0
Configuration
Registers
Configuration
Registers
Status Register
Command
Register
X
1
X
The eight Configuration Register formats are shown in
A~BFIFO
0
1
Configuration Registers
Reset
Operands
0
1
The Status Register reports the state of the programmable
flags and the DMA read/write direction. The Status Register
is read by setting CSA = 0, A1 = 1, Ao = 1 (see Table 1). See
Table 7 for the Status Register format.
Write
0
0
Status Register
RESET COMMAND FUNCTIONS
PORT A RESOURCE SELECTION
CSA
request DMA circuitry can also be reset independently. A
software Reset All command resets all the pOinters, the DMA
request circuitry, and sets all the Configuration Registers to
their default condition. Note that a hardware reset is NOT the
same as a software Reset All command. Table 6 shows the
BiFIFO state after the different hardware and software resets
Disabled
Disabled
2668 tbl 03
Table 1. Accessing Port A Resources Using ~A, AO and At
COMMAND OPERATIONS
Command
Opcode
No Operation
001
Reset B~A FIFO (Read, Write, and Rewrite
Pointers 0)
010
Reset A~B FIFO (Read, Write, and Reread
Pointers 0)
011
Reset
100
Reset Internal DMA Request Circuitry
=
=
B~A
and
101
No Operation
110
No Operation
111
Reset All
A~B
FIFO
2668 tbl 04
Function
Table 3. Reset Command Functions
0000
Reset BiFIFO (see Table 3)
0001
Select Configuration Register (see Table 4)
0010
Load Reread Pointer with Read Pointer Value
0011
Load Rewrite Pointer with Write Pointer Value
Operands
Load Read Pointer with Reread Pointer Value
000
0100
Function
000
SELECT CONFIGURATION REGISTER!
COMMAND FUNCTIONS
Function
Select Configuration Register 0
0101
Load Write Pointer with Rewrite Pointer Value
001
Select Configuration Register 1
Q110
Set DMA Transfer Direction (see Table 5)
010
Select Configuration Register 2
0111
Reserved
011
Select Configuration Register 3
1000
Increment A~B FIFO Read Pointer (Port B)
100
Select Configuration Register 4
1001
Increment
101
Select Configuration Register 5
1010
1011
B~A
FIFO Write Pointer (Port B)
Reserved
Reserved
110
Select Configuration Register 6
111
Select Configuration Register 7
2668 tbl 06
2668 tbl 05
Table 4. Select Configuration Register Functions.
Table 2. Functions Performed by Port A Commands
DMA DIRECTION COMMAND FUNCTIONS
Operands
Function
XXO
Write
B~A
FIFO
XX1
Read
A~B
FIFO
2668 tbl 07
Table 5. Set DMA Direction Command Functions. Command Only
Operates in Peripheral Interface Mode
5.24
8
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATE AFTER RESET
Software Reset
B~Aand
Hardware Reset
(RS asserted)
B~A(001)
Configuration Registers 0-3
OOOOH
-
Configuration Register 4
6420H
-
Configuration Register 5
OOOOH
Configuration Register 6-7
OOOOH
-
Status Register format
0
-
B~A
Read, Write, Rewrite Pointers
0
0
A~B
Read, Write, Reread Pointers
0
-
DMA direction
DMA internal request
B~Awrite
clear
A~B(010)
A~B(011)
-
-
Internal
Request
(100)
AII(111)
-
OOOOH
-
6420H
OOOOH
0
-
0
0
-
0
-
-
clear
OOOOH
0
clear
2668 tbl 08
Table 6. The BiFIFO State After a Reset Command
Table 8. Configuration Registers 0-3 contain the programmable
flag offsets forthe Almost-Empty and Almost-Full flags. These
offsets are set to 0 when a hardware reset or a software Reset
All is applied. Note that Table 8 shows that Configuration
Registers 0-3 are 10 bits wide to accommodate the 1024
locations in each FIFO memory of the IDT7252/520. Only 9
least significant bits are used for the 512 locations of the
IDT7251/510; the most significant bit, bit 9, must be set to O.
Configuration Register 4 is used to assign the internal flags
to the external flag pins (FlGA-FlGD). Each external flag pin
is assigned an internal flag based on the four bit codes shown
in Table 9. The default condition for Configuration Register 4
is 6420H as shown in Table 6. The default flag assignments
are: FlGD is assigned B~A Full, FlGc is assigned B~A
Empty, FlGB is assigned A~B Full, FlGA is assigned A~B
Empty.
Configuration Register 5 is a general control register. The
format of Configuration Register 5 is shown in Table 10.
Bit 0 sets the Intel-style interface (RB, WB) or Motorola-style
interface (DSB, RIWB) for Port B. Bits 2 and 3 redefine Full and
Empty Flags for reread/rewrite data protection.
Bits 4-9 control the DMA interface and are only applicable
in peripheral interface mode. In processor interface mode,
these bits are don't care states. Bits 4 and 5 set the polarity of
the DMA control pins REO and ACK respectively. An internal
clock controls all DMA operations. This internal clock is
derived from the external clock (ClK). Bit 9 determines the
internal clock frequency: the internal clock = ClK or the
internal clock =ClK divided by 2. Bit 8 sets whether RB, WB,
and DSB are asserted for either one ortwo internal clocks. Bits
6 and 7 set the number of internal clocks between REO
assertion and ACK assertion. The timing can be from 2 to 5
cycles as shown in Figure 17.
Bit 10 controls Port B processor or peripheral interface
mode. In processor mode, the Port B control pins (RB, WB,
DSB, RIWB) are inputs and the DMA controls are ignored. In
peripheral mode, the Port B control pins are outputs and the
DMA controls are active.
Six PIO pins can be programmed as an input or output
by the corresponding mask bits in Configuration Register 7.
The format of Configuration Register 7 is shown in Figure
5. Each bit of the register set the I/O direction independently. A logic 1 indicates that the corresponding PIO pin is
an output, while a logic 0 indicates that the PIO pin is an
input. This I/O mask register can be read or written.
A programmed output PIOi pin (i = 0, 1, ... 5) displays the
data latched in Bit i of Configuration Register 6. A programmed
input PIOi pin allows Port A bus to sample the data on DAi by
reading Configuration Register 6.
STATUS REGISTER FORMAT
Bit
Signal
0
Reserved
1
Reserved
2
Reserved
3
DMA Direction
4
A~B
Empty Flag
5
A~B
Almost-Empty Flag
6
B~A
Full Flag
7
B~A
Almost-Full Flag
8
Reserved
9
Reserved
10
Reserved
11
Reserved
12
A~B
Full Flag
13
A~B
Almost-Full Flag
14
B~A
Empty Flag
15
B~A
Almost-Empty Flag
2668 tbl 09
Table 7. The Status Register Format
5.24
9
II
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATION REGISTER FORMATS
o
Config. Reg. 0
15
Config. Reg. 1
X
X
X
X
15
A~
FIFO Almost Full Flag Offset
o
X
o
10
84 FIFO Almost Empty Flag Offset
X
15
o
10
15
Config. Reg. 4
FIFO Almost Empty Flag Offset
10
X
Config. Reg. 2
Config. Reg. 3
A~
X
X
X
X
X
12
11
Flag D Pin Assignment
84 FIFO Almost Full Flag Offset
7
Flag C Pin Assignment
4
Flag 8 Pin Assignment
o
3
Flag A Pin Assignment
o
15
Config. Reg. 5
General Control
o
15
Config. Reg. 6
1/0 Data
o
15
Config. Reg. 7
I/O Direction Control
2668 tbllO
NOTE:
Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT72511.
1.
Table 8. The BiFIFO Configuration Register Formats
EXTERNAL FLAG ASSIGNMENT CODES
Programmable Flags
The lOT BiFIFO has eight internal flags. Associated with
each FIFO memory array are four internal flags, Empty,
Almost-Empty, Almost-Full and Full, for the total of eight
internal flags. The Almost-Empty and Almost-Full offsets can
be set to any depth through the Configuration Registers 0-3
(see Table 8). The flags are asserted at the depths shown in
Table 11. After a hardware reset or a software Reset All, the
almost flag offsets are set to O. Even though the offsets are
equivalent, the Empty and Almost-Empty flags have different
timing which means that the flags are not coincident. Similarly,
the Full and Almost-Full flags are not coincident after reset
because of timing.
These eight internal flags can be assigned to any of four
external flag pins (FLGA-FLGD) through Configuration Register 4 (see Table 9). For the specific flag timings, see Figures
20-23.
The current state of all eight flags is available in the Status
Register.
Assignment
Code
Internal Flag Assigned to Flag Pin
0000
A~B
Empty
0001
A~B
Almost-Empty
0010
A~B
Full
0011
A~B
Almost-Full
0100
B~A
Empty
0101
B~A
Almost-Empty
0110
B~AFull
0111
B~A
1000
A~B
Empty
1001
A~B
Almost-Empty
1010
A~B
Full
1011
A~B
Almost-Full
1100
B~AEmpty
1101
B~A
1110
B~AFull
1111
B~A
Almost-Full
Almost-Empty
Almost-Full
2668 tblll
Table 9. Configuration Register 4 Internal Flag Assignments to
External Flag Pins
5.24
10
IDTI251111DTI2521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATION REGISTER 5 FORMAT
Bit
0
Function
Select Port B Interface
Rs and Ws or DSs and RiWs
1
Unused
2
Full Flag Definition
3
4
5
7-6
Empty Flag Definition
REO Pin Polarity
ACK Pin Polarity
REO / ACK Timing
0
Pins are Rs and Ws (Intel-style interface)
1
Pins are DSs and RlWs (Motorola-style interface)
0
Write pointer meets read pointer
1
Write pointer meets reread pointer
0
Read pointer meets write pointer
1
Read pointer meets rewrite pointer
0
REO pin active HIGH
1
REO pin active lOW
0
ACK pin active lOW
1
ACK pin active HIGH
00
2 internal clocks between REO assertion and ACK assertion
01
3 internal clocks between REO assertion and ACK assertion
10
4 internal clocks between REO assertion and ACK assertion
11
5 internal clocks between REO assertion and ACK assertion
Port BRead & Write
Timing Control for Peripheral Mode
0
Rs, Ws, and DSs are asserted for 1 internal clock
1
Rs, Ws, and DSs are asserted for 2 internal clocks
9
Internal Clock
Frequency Control
0
=ClK
Internal clock =ClK divided by 2
10
Port B Interface
Mode Control
0
Processor interface mode (Port B controls are inputs)
1
Peripheral interface mode (Port B controls are outputs)
8
11
II
Internal clock
1
Unused
12
Unused
13
Unused
14
Unused
15
Unused
2668 tb112
Table 10. BiFIFO Configuration Register 5 Format
CONFIGURATION REGISTER 6 FORMAT
15
6
Unused
5
4
3
2
PI05
PI04
PI03
PI02
o
PI01
PIOO
2668 tb113
Figure 4. BiFIFO Configuration Register 6 Format for Programmable 1/0 Data
CONFIGURATION REGISTER 7 FORMAT
15
6
Unused
5
4
3
2
MI05
MI04
MI03
MI02
o
MI01
MIOO
2668 tb114
Figure 5. BiFIFO Configuration Register 7 Format for Programmable VO Direction Mask
5.24
11
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Port B Interface
Port B has reread/rewrite and DMA functions. Port B can
be configured to interface to either Intel-style (Rs, WS) or
Motorola-style (DSs, RIWs) devices in Configuration Register
5 (see Table 10). Port B can also be configured to talk to a
processor or a peripheral device through Configuration Register 5. In processor interface mode, the Port B interface
controls are inputs. In peripheral interface mode, the Port B
interface controls are outputs. After a hardware reset or a
software Reset All command, Port B defaults to an Intel-style
processor interface; the controls are inputs.
DMA Control Interface
The BiFIFO has DMA control to simplify data transfers with
peripherals. For the BiFIFO DMA controls (REO, ACK and
ClK) to operate, the BiFIFO must be in peripheral interface
mode (Configuration Register 5, Table 10).
DMA timing is controlled by the external clock input, ClK.
An internal clock is derived from this ClK signal to generate
the RS, Ws, DSs and RIWs output Signals. The internal clock
also determines the timing between REO assertion and ACK
assertion. Bit 9 of Configuration Register 5 determines whether
the internal clock is the same as ClK or whether the internal
clock is ClK divided by 2.
Bit 8 of Configuration Register 5 set whether RS, Ws and
DSs are asserted for 1 or 2 internal clocks. Bits 6 and 7 of
Configuration Register 5 set the number of clocks between
REO assertion and ACK assertion. The clocks between REO
assertion and ACK assertion can be 2, 3, 4 or 5.
Bits 4 and 5 of Configuration Register 5 set the polarity of
the REO and ACK pins respectively.
A DMA transfer command sets the Port Bread/write
direction (see Table 5). The timing diagram for DMA transfers
is shown in Figure 17. The basic DMA transfer starts with REO
assertion. After 2 to 5 internal clocks, ACK is asserted by the
BiFIFO. ACi< will not be asserted if a read is attempted on an
empty A~B FI FO or if a write is attempted on a full B~A FIFO.
If the BiFIFO is in Motorola-style interface mode, RIWs is set
at the same time that ACK is asserted. One internal clock later,
DSs is asserted. If the BiFI FO is in Intel-style interface mode,
either Rs or Ws is asserted one internal clock after ACK
assertion. These read/write controls stay asserted for 1 or 2
internal clocks, then ACK, DSs, Rs and Ws are made inactive.
This completes the transfer of one 9-bit word.
On the next rising edge of ClK, REO is sampled. If REO
is still asserted, another DMA transfer starts with the assertion
of ACK. Data transfers will continue as long as REO is
asserted.
Intelligent Reread/Rewrite
Intelligent reread/rewrite is a method the BiFIFO uses to
help assure data integrity. Port B of the BiFIFO has two extra
pointers, the Reread Pointer and the Rewrite Pointer.The
Reread Pointer is associated with the A->B FIFO Read
Pointer, while the Rewrite Pointer is associated with the B->A
FIFO Write Pointer. The Reread Pointer holds the start address of a data block in the A->B FIFO RAM, and the Read
Pointer is the current address of the same FIFO RAM array.
By loading the Read Pointer with the value held in the Reread
Pointer (RER asserted), reads will start over at the beginning
of the data block. In order to mark the beginning of a data
block, the Reread Pointer should be loaded with the Read
Pointer value (lDRER asserted) before the first read is
performed. on this data block. Figure 6 shows a Reread
operation.
Similarly, the Rewrite Pointer holds the start address of a
data block in the B->A FIFO RAM, while the Write Pointer is
the current address within the RAM array. The operation of the
REW and lDREW is identical to the RER and lDRER discussed above. Figure 7 shows a Rewrite operation.
For the reread data protection, Bit 2 of Configuration
Register 5 can be set to 1 to prevent the data block from being
overwritten. In this way, the assertion of A->B full flag will occur
when the write pointer meets the reread pOinter instead of the
read pointer as in the normal definition. For the rewrite data
protection, Bit 3 of Configuration Register 5 can be set to 1 to
INTERNAL FLAG TRUTH TABLE
Number of Words in FIFO
From
To
Empty Flag
Almost-Empty Flag
Almost-Full Flag
Full Flag
0
0
Asserted
Asserted
Not Asserted
Not Asserted
1
n
Not Asserted
Asserted
Not Asserted
Not Asserted
n+1
D-(m+ 1)
Not Asserted
Not Asserted
Not Asserted
Not Asserted
D-m
D-1
Not Asserted
Not Asserted
Asserted
Not Asserted
D
D
Not Asserted
Not Asserted
Asserted
Asserted
NOTE:
1. SiFIFO flags must be assigned to extemal flag pins to be observed. D
offset. m Almost-Full flag offset.
=
2668 tbl15
=FIFO depth (1OT72511 =512. IDT72521 =1024). n =Almost-Empty flag
Table 11. Internal Flag Truth Table
5.24
12
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
prevent the data block from being read. In this case the
assertion of B->A empty flag will occur when the read pointer
meets the rewrite pointer instead of the write pointer.
In conclusion, Bit 2 and 3 of Configuration Register 5 are
used to redefine Full & Empty flags for data block partition.
Although it can serve the purpose of data protection, the
setting of these 2 bits is independent of the functions caused
by RER/REW, or LDRER/LDREW assertions.
The BiFIFO has six programmable I/O pins (PIOo - PIOs)
which are controlled by Port 'A through Configuration Registers 6 and 7. Data from the programmable I/O pins is mapped
directly to the six least significant bits of Configuration Regis-
ter 6. Figure 4 shows the format of Configuration Register 6.
This data is read or written by Port A on the data pins
(DAo- DAs). A programmed output PIOi pin (i = 0, 1, ... , 5)
displays the data latched in Bit i of Configuration Register 6.
A programmed input PIOi pin allows Port A bus to sample its
data on DAi by reading Configuration Register 6. The read and
write timing for the programmable I/O pins is shown in Figure
19. The direction of each programmable I/O pin can be set
independently by programming the mask in Configuration
Register 7. Each P10 pin has a corresponding input/output
direction mask bit in Configuration Register 7. Figure 5 shows
the format of Configuration Register 7. Setting a mask bit to a
logic 1 makes the corresponding 1/0 pin an output. Mask bits
set to logic 0 force the corresponding I/O pin to an input.
REREAD OPERATIONS
REWRITE OPERATIONS
Programmable Input/Output
(1,2)
(3,4)
Reread
Pointer
II
Write
Pointer --...
Load
Reread
function
Read
Pointer
Rewrite
function
2668 drw08
NOTES:
1. If bit 2 is set to 1,
Empty flag asserted if Read Write
Full flag asserted if Reread + FIFO size =Write
2. If bit 2 is set to 0,
Empty flag asserted if Read = Write
Full flag asserted if Read + FIFO size Write
=
=
2668 drw09
NOTES:
1. If bit 3 is set to 1,
Empty flag asserted if Read =Rewrite
Full flag asserted if Read + FIFO size Write
2. If bit 3 is set to 0,
Empty flag asserted if Read Write
Full flag asserted if Read + FIFO size =Write
=
=
Figure 6. BiFIFO Reread Operations
Figure 7. BiFIFO Rewrite Operations
5.24
13
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Commercial
Military
Unit
Terminal Voltage
With Respect To
Ground
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
lOUT
DC Output
Current
-55 to +125
-65 to +155
°C
50
50
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTE:
2668 tbl16
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation ofthe device atthese or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Min.
Typ.
Max.
Unit
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
Vccc
Commercial Supply
Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
VIH
Input HIGH Voltage
Commercial
2.0
VIH
Input HIGH Voltage
Military
VIL(l)
Input LOW Voltage
Commercial and
Military
V
0
-
-
V
2.2
-
-
V
-
-
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2668 tbl17
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc
=SV ± 10%, TA =O°C to +70°C; Military: Vcc =SV ± 10%, TA =-SsoC to +12S°C)
IDT72511L
IDT72521L
Commercial
tA 25, 35, 50ns
Min.
Typ.
Max.
=
Symbol
Parameter
Max.
Unit
-
1
-10
-
10
~A
Output Leakage Current
-10
10
-10
-
10
~
Output Logic "1" Voltage I OUT
=-1 mA
Output Logic "0" Voltage lOUT =4mA
2.4
-
2.4
V
0.4
-
-
0.4
V
Average VCC Power Supply Current
-
150
230
-
180
250
mA
-
16
30
-
24
50
mA
Input Leakage Current (Any Input)
IOL(2)
VOH
ICCl
(3)(4)
ICC2 (3)
=
-1
IIL(l)
VOL
IDT72521L
Military
tA 40, 50ns
Typ.
Average Standby Current (RB
VIH)
=We =DSA =
Min.
2668 tbl18
NOTES:
1. Measurements with DAV ::; VIN ::; Vcc, DSA = DSa 2! VIH
2. Measurements with DAV ::; VOUT ::; Vec, DSA = DSa 2! VIH
3. Measurements are made with outputs open.
+SV
AC TEST CONDITIONS
1.1 kn
Input Pulse Levels
GNDto 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
D.U.T.
680n
1.5V
Output Load
30 pF*
See Figure 8
2668 tbl19
CAPACITANCE (TA =+2SoC, f = 1.0MHz)
Symbol
Parameter
CIN(2)
Input CapaCitance
COUT(l,2)
Output Capacitance
2668 drw09
Conditions
Max.
Unit
VIN =OV
8
pF
VOUT= OV
12
pF
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
or equivalent circuit
Figure 8. Output Load
*Includes jig and scope capacitances
2668 tbl20
5.24
14
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
=5V ± 10%, TA = O°C to + 70°C; Military: Vcc
(Commercial: Vcc
5V ± 10%, TA
Commercial
Symbol
Parameter
Military
IDT72511 L25
IDT72511 L35
IDT72521 L25
Min.
=-55°C to + 125°C)
Com'l & MiI.(2)
IDT72511L50
IDT72521 L35
IDT72521 L40
IDT72521 L50
Max.
Min.
Max.
Min.
Min.
-
-
-
-
50
40
40
10
35
45
35
35
10
-
45
-
50
65
50
50
15
-
Max.
Unit
Timing
Figure
-
ns
9
ns
9
-
ns
9
-
ns
9
65
ns
9
Max.
RESET TIMING (Port A and Port B)
tRSC
Reset cycle time
tRS
Reset pulse width
tRSS
Reset set-up time
tRSR
Reset recovery time
35
25
25
10
tRSF
Reset to flag time
-
-
-
-
-
PORT A TIMING
taA
Port A access time
-
25
-
35
-
40
-
50
ns
taLZ
Read or write pulse
LOW to data bus at
Low-Z
5
-
5
-
5
-
5
-
ns
12,14,15
12, 15, 16
taHz
Read or write pulse
HIGH to data bus at
High- Z
-
15
-
20
-
25
-
30
ns
12, 14, 15, 16
taDv
Data valid from read
pulse HIGH
5
-
5
.-
5
-
5
-
ns
12, 14, 16
taRc
Read cycle time
35
-
45
-
50
-
65
-
ns
12
-
-
50
-
ns
-
-
ns
-
15
5
-
ns
12,14,15
12
10, 12, 16
ns
10,12
ns
11, 12, 14, 15
11, 12, 14, 15
12
taRPW
Read pulse width
25
taRR
Read recovery time
CSA, Ao, Al, RIWA setuptime
-
35
10
5
-
taS
10
5
-
40
10
5
taH
CSA, Ao, Al, RIWA hold
time
5
-
5
-
5
-
5
-
taos
Data set-up time
-
Write cycle time
20
5
50
-
-
tawc
18
2
45
-
Data hold time
tawpw
Write pulse width
tawR
Write recovery time
tawRCOM
Write recovery time after
a command
15
0
35
25
10
25
-
taDH(l)
30
5
65
50
15
50
-
-
-
35
10
35
-
-
40
10
40
-
-
-
ns
ns
ns
ns
ns
11, 12, 14
12
11
2668 tbl21
NOTE:
1. The minimum data hold time is 5ns (iOns for the 80ns speed grade) when writing to the Command or Configuration registers.
2. IDT72511 not available in military.
5.24
15
II
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee
=5V ± 10%, TA = O°C to + 70°C; Military: Vee = 5V ± 10%, TA =-55°C to + 125°C)
Commercial
Symbol
Parameter
Military
IDT72511L25
IDT72511 L35
IDT72521L25
IDT72521 L35
Min.
Max.
Min.
Max.
Com'l & MII,(1)
IDT72511 L50
IDT72521 L40
IDT72521 L50
Min.
Min.
Max.
Max.
Timing
Unit
Figure
PORT 8 PROCESSOR INTERFACE TIMING
tbA
Port 8 access time
-
25
-
35
-
40
-
50
ns
13,14,15
tbLZ
Read or write pulse
LOW to data bus at
Low-Z
5
-
5
-
5
-
5
-
ns
13,14,15
tbHZ
Read or write pulse
HIGH to data bus at
High-Z
-
15
-
20
-
25
-
30
ns
14,13,15
tbov
Data valid from read
pulse HIGH
5
-
5
-
5
-
5
-
ns
13, 14, 15, 16
tbRC
Read cycle time
35
45
-
50
-
65
-
ns
13
tbRPW
Read pulse width
25
35
-
40
50
-
ns
13
tbRR
Read recovery time
10
10
-
10
-
15
ns
13
-
40
-
5
5
-
10
-
15
tbs
RlWB set-up time
5
-
tbH
RlWB hold time
5
-
5
tbos
Data set-up time
15
18
tbOH
Data hold time
0
tbwc
Write cycle time
35
45
tbwpw
Write pulse width
25
tbWR
Write recovery time
10
-
5
2
35
10
5
20
5
50
5
30
5
65
50
-
ns
13
ns
13
ns
13, 14, 15
ns
13,14,15
ns
13
ns
13,15
ns
13
PORT B PERIPHERAL INTERFACE TIMING
tbA
Port 8 access time
-
25
-
40
-
45
-
55
ns
17
tbCKC
Clock cycle time
15
-
20
20
17
6
ns
17
tbCKL
Clock pulse LOW time
6
6
10
ns
17
tbREOS
Request set-up time
5
-
6
-
ns
Clock pulse HIGH time
5
-
5
-
25
tbCKH
-
10
-
ns
17
tbREOH
Request hol,d time
5
-
5
-
5
-
5
-
ns
17
tbACKL
Delay from a rising clock
edge to ACK switching
-
15
-
18
-
20
-
25
ns
17
NOTE:
8
8
10
2668 tbl22
1. IDT72511 not available in military.
5.24
16
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee
=5V ± 10%, TA = O°C to + 70°C; Military: Vee
5V
Commercial
Symbol
Parameter
± 10%, TA
Military
=-55°C to + 125°C)
Com'l & MiI.(4)
IDT72511 L25
IDT72511L35
IDT72521 L25
IDT72521L35
IDT72521 L40
IDT72521 L50
Min.
Max.
Min.
Max.
Min.
Min.
10
-
10
-
10
-
15
IDT72511L50
Max.
Max.
Timing
Unit
Figure
-
ns
9, 1a
PORT B RETRANSMIT TIMING
tbDSBH
RER, RE'N, LDRER,
LDREW set-up and
recovery time
PROGRAMMABLE I/O TIMING
tPIOA
Programmable I/O
access time
-
20
-
25
-
25
-
30
ns
19
tPIOS
Programmable I/O setuptime
a
-
10
-
10
-
15
-
ns
19
tPIOH
Programmable I/O hold
time.
8
-
10
-
10
-
15
-
ns
19
BYPASS TIMING
tBYA
Bypass access time
-
18
-
20
-
25
ns
16
Bypass delay
-
10
-
15
-
20
-
30
tBYD
20
ns
16
taBYDV
Bypa~data
15
-
15
-
15
-
15
-
ns
16
3
-
3
-
3
-
3
-
ns
16
valid time
from DSA
tbBYDV (3) Bypass data valid time
fromDSB
FLAG TIMING
(1) (2)
tREF
Read clock edge to
Empty Flag asserted
-
25
-
35
-
40
-
45
ns
14,15,20,22
twEF
Write clock edge to
Empty Flag not asserted
-
25
-
35
-
40
-
45
ns
14,15,20,22
tRFF
Read clock edge to Full
Flag not asserted
-
25
-
35
-
40
-
45
ns
14,15,21,23
twFF
Write clock edge to Full
Flag asserted
-
25
-
35
-
40
-
45
ns
14,15,21,23
tRAEF
Read clock edge to
Almost-Empty Flag
asserted
-
40
-
50
-
55
-
60
ns
20,22
twAEF
Write clock edge to
Almost-Empty Flag not
asserted
-
40
-
50
-
55
-
60
ns
20,22
tRAFF
Read clock edge to
Almost-Full Flag not
asserted
-
40
-
50
-
55
-
60
ns
21,23
twAFF
Write clock edge to
Almost-Full Flag
asserted
-
40
-
50
-
55
-
60
ns
21,23
2668tbl23
NOTES:
1. Read and write are internal signals derived from DSA, RiWA, DSs, Rlws, Rs, and Ws.
2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are internal flags, the timing given is for those assigned to external pins.
3. Values guaranteed by design, not currently tested.
4. IDT72511 not available in military.
5.24
17
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~I--------
1 4 1 - - - - - tRS
tRse - - - - - - -....~
-------j~
WB,RB
(or RfiiB, DSB)
LDRER,
LDREW
REO
FLGA,
FLGc
FLGB,
FLGo
2668 drw 10
Figure 9. Hardware Reset Timing
AO,A1
tas
2668 drw 11
Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing)
5.24
18
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
\'---_ _ _-J/
\ ......._ - - - tWRCOM
Opcode
DAB - 0\12
or
Operand
2668 drw 12
DAO - 0\12
Figure 11. Port A Command Timing (write).
WRITE
DSA
tas
Input
DAO - [l4.17
taDs
taDH
READ
RNVA
taRe
DSA
tas
Output
DAO - [l4.17
Figure 12. Read and Write Timing for Port A
5.24
19
IDT72511nDTI2521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE
(RiWs)
..
\
}
Ws
(or DSB)
..
tbwc
...
tbs
....\ 1\ ..
tbwpw
.. "'-
tbWR~
..
~"
1
.I
Input
~
DBo-DBa
I
tbDS
....
tbDH
..
Y- ....
/1
tbH
./
./
I
NOTE:
1. RB= 1
READ
(R/WB)
RB
(or DSB) ---~I-----"
Output
DBo-DBa
266B drw 14
NOTE:
1. WB
=1
Figure 13. Port B Read and Write Timing, Processor Interface Mode Only
5.24
20
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
A-7B FIFO WRITE FLOW-THROUGH
DAD - [}!I.17
taoH
A~B
Full Flag(1) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
~-- tRFF --~~--I~ tWFF
Rs(or ooB)
DATA OUT
DBD - [E17
1 4 - -__~ tbA
NOTES:
1. Assume the flag pin is programmed active LOW.
2. RiWA=O
II
B-7A FIFO READ FLOW-THROUGH
taLZ
DAD - [}!I.17
B~A
Empty Flag (1) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+-____-'
WB(or DSB)
DATA INPUT
DBD - [E17
1 4 - - - tbos ---~
2668 drw 15
NOTES:
1. Assume the flag pin is programmed active LOW.
2. RiWA= 1
Figure 14. Port A Read and Write Flow-Through Timing, Processor Interface Mode Only
5.24
21
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
A~B
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIFO WRITE FLOW-THROUGH
DSA
DAO-DA17
B-tA
Full Flag(1)
As = 1 (or RIWB = 0)
ViB (or DSB) - - -.....
DBO-DBB
NOTES:
1. Assume the flag pin is programmed active LOW.
. .-
....i4--II~ tbDH
2. RJWA= 1
A~B
FIFO READ FLOW-THROUGH
DAD-DA17
taDs
~-"''''''':''''''-II~
taDH
A-tB
Empty Flag (1)
tWEF
ViB
tREF ---II~
=1 (or RIWB =1)
RB (orDSB)
taLZ
t4--~
DBO-DBB
tbA
2668 drw 16
NOTES:
1. Assume the flag pin is programmed active LOW.
2. R1WA=O
Figure 15. Port B Read and Write Flow-Through Timing, Processor Interface Mode Only
5.24
22
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
B~A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
READ BYPASS
DSA
DAD-DA7,
DA16
As (or DSB)
(RIWB)
DBD-DBB
BYTE 0
~__B__
YTE__
1 __~)~------~(~____________
BYT
__E
__
2 _________
NOTES:
1. Once the bypass mode starts, any data change on Port B bus (Byle 0-7Byle 1) will be passed to Port A bus.
2. WB= 1
A~B
WRITE BYPASS
DAD-DA7,
DA16
BYTE 2
~ tBYD
WB (crDSB)
(RIWB)
DBD-DB8
2666 drw 17
NOTES:
1. Once the bypass mode starts, any data change on Port A bus (Byle 0-7Byle 1) will be passed to Port B bus.
2. RB
=1
Figure 16. Bypass Path Timing, BiFIFO Must Be in Peripheral Interface Mode
5.24
23
II
10172511/10172521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE WORD DMA TRANSFER
~
t05CYCles
~1CYCle~
l ' t o 2 cycles
tCKC
tCKH
ClK
tCKL
REO
tREOS
14-~14-"'"
tREOH
WRITE
(RJWB)
tACKL
WB(orOSB)
--------------------------------------------------------------------------------------------------+~
tacKL
Output
OBo-0817
READ
(RtWB)
As (orOSB)
tACKL
tACKL
Input
OBo-0817
tbos ,...----------~----~ tbOH
BLOCK DMA TRANSFER
1 to 2
2
ClK
REO
ACK, RtWB
As, WB (orOSB)
5
cycles
2t 5
~ cy~~es -1
H
~ cyc~es -1
LfLJL.JLJUU
.
J
1 to 2
cycles
H
.
"
V
.
'--/
"""'---i-----------..J!.
" o ~/
"""'---'-----------.."
2668 drw 18
Figure 17. Port B Read and Write OMA timing. Peripheral Interface Mode Only
5.24
24
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
As, INs
(or RtWs, DSB)
tbOSBH
tbwpw
tbOSBH
LDRER,
LDREW _____________________- J
2668 drw 19
Figure 18. Port B Reread and Rewrite Timing for Intelligent Reread/Rewrite
Port A
~
PIO WRITE
1-"111---- tawc -----1~
DSA
tawR
tas
taH
II
Input
DAO-DAS
taos
taoH
Output
PIOo-PIOs
PIO
~
Port A READ
r - I - - - - - - taRc
------I~
tas
Output
DAO-DAS
Input
PIOo-PIOs
tPIOS
tPIOH
2668 drw 20
Figure 19. Programmable YO Timing
5.24
25
IDT72511nDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Read
DSA ----------------------~~~--------------------------~
We
(or RJWB =0, DSB) ------,
Write
. .----, _
L.2.J
r1..
L!.J
tREF
B~A
Empty
Flag - - - - - - t - . 1
B~AAlmost
---------~~I----------
Empty Flag - - - - - - - - - - - -
2668 drw21
NOTES:
1. B-tA FIFO is initially empty.
2. Assume the flag pins are programmed active LOW.
3. RiWA = 1.
Figure 20. Empty and Almost-Empty Flag Timing for B-tA FIFO, (n
= programmed offset)
Read
DSA ----------------------~\~-----------------------,
WB
Write
(orRNVB=1, ------, . r---l _ ~
)
L-2-J ~
(2)
B~A Almost-
Full Flag
=1 t
tWEF
-----+-
_ _ _ _~ ~---+---+---------f---il------\
\--__-1-.1
(2)
B~A --------------~ ~--_t__
Full Flag
2668 drw 22
NOTES:
1. B-tA FIFO initially contains 0 - (M + 1) data words. 0
2. Assume the flag pins are programmed active LOW.
3. RiWA= 1.
=512 for IDT72511; 0 =1024 for IDT72521.
Figure 21. Full and Almost-Full Flag Timing for B-tA FIFO, (m
5.24
=programmed offset)
26
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Write
DSA ~
.
r---l
~
~t-.
L2J
I----------------------------------~\\
~
~
(orRANB=1,DSB) ----------+--+------~~----~~------------~
~~
A~B Empty(2)
Flag __________+_'
A~B
Almost-(2)
---------t'\-t-------
Empty Flag -----------~ \ - - - - t - - '
2668 drw 23
NOTES:
1. A~B FIFO is initially empty.
2. Assume the flag pins are programmed active LOW.
3. RlWA 1.
=
Figure 22. Empty and Almost-Empty Flag Timing for
A~B
FIFO, (n
=programmed offset)
II
Read
DSA
----------------~\\---------------~
(2)
B~A-------------~ ~--~~,
Full Flag
2668 drw 24
NOTES:
1. B~A FIFO initially contains D - (M + 1) data words. D
2. Assume the flag pins are programmed active LOW.
3. RIWA= 1.
=512 for IDT72511; D =1024 for IDT72521.
Figure 23. Full and Almost-FuJI Flag Timing for A~B FIFO, (m
5.24
=programmed offset)
27
IDT72511I1DT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXXX
x
XXX
X
x
Device
Type
Power
Speed
Package
Process!
Temperature
Range
Y:lank
'--------1\IGJ
L....-_ _ _ _ _ _ _ _ _ _ _- ;
25
35
40
50
L....-.--------------------------f'I
L--------------------il
L
72511
I 72521
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
68-pin PGA
68-pin PLCC
Commercial Only }
Commercial Only
Military Only *
Com'l & Mil. *
,
Acces.s Time (tA)
In ns
Low Power
512 x 18 Parallel BiFIFO
1024 x 18 Parallel BiFIFO
2668 drw 25
• 40 Military Only, IDT12521
• 50 Commercial and Military, IDT12511 available In commercial only
5.24
28
t;)
IDT72021
IDT72031
IDT72041
CMOS ASYNCHRONOUS FIFO WITH
RETRANSMIT
1 K x 9, 2K x 9, 4K x 9
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
IDT72021/031/041s are high-speed, low-power, dual-port
memory devices commonly known as FIFOs (First-ln/FirstOut). Data can be written into and read from the memory at
independent rates. The order of information stored and extracted does not change, butthe rate of data entering the FIFO
might be different than the rate leaving the FIFO. Unlike a
Static RAM, no address information is required because the
read and write pointers advance sequentially. The IDT72021/
031/041s can perform asynchronous and simultaneous read
and write operations. There are four status flags, (HF, FF, EF,
AEF) to monitor data overflow and underflow. Output Enable
(OE) is provided to control the flow of data through the output
port. Additional key features are Write (W), Read (R), Retransmit (R1), First Load (FL), Expansion In (Xi) and Expansion Out
(XO). The IDT72021/031/041s are designed for those applications requiring data control flags and Output Enable (OE) in
multiprocessing and rate buffer applications.
The IDT72021/031/041s are fabricated using lOT's CMOS
technology. Military grade product is manufactured in compliance with the latest version of MIL-STD-883, Class B, for high
reliability systems.
•
•
•
•
•
•
•
•
•
First-In/First-Out Dual-Port memory
Bit organization
- IDT72021-1 K x 9
- IDT72031-2K x 9
- IDT72041-4K x 9
Ultra high speed
- I DT72021-25ns access time
- IDT72031-35ns access time
- I DT72041-35ns access time
Easily expandable in word depth and/or width
Asynchronous and simultaneous read and write
Functionally equivalent to IDT7202/03/04 with Output
Enable (OE) and Almost Empty/Almost Full Flag (AEF)
Four status flags: Full, Empty, Half-Full (single device
mode), and Almost Empty/Almost Full (7/8 empty or 718
full in single device mode)
Output Enable controls the data output port
Auto-retransmit capability
Available in 32-pin DIP and PLCC
Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
DATA INPUT
(00-08)
. - - - - + - 1 - - - - - - OE
THREESTATE
BUFFERS
DATA OUTPUTS
(00-08)
.--------~EF
~----~-~
FF
~-------~AEF
Xi----.t
l-----------------l~XO/HF
I-----~
2677 drw 01
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
AUGUST 1993
DSC-2003lS
5.25
1
II
IDT72021, 1DT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1 K
x 9, 2K x 9, 4K X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Vee
Vee
W
04
05
Os
02
01
06
07
03
06
02
07
01
FURT
Do
RS
Do
FlIRT
Xi
RS
OE
AEF
FF
EF
IT
EF
00
01
02
XO/HF
00
07
07
06
01
06
02
03
05
Os
R
AEF
Xi
OE
XOIHF
04
GNO
GND
2677 drw03
PLCC TOP VIEW
DIP TOP VIEW
2677 drw02
PIN DESCRIPTIONS
Symbol
Name
VO
Oo-Da
Inputs
I
Data inputs for 9-bit wide data.
RS
Reset
I
When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM
array. HF and FF,9o HI111
1. Oi refers to the rnost significant bit of the serial word. If multiple devices are width cascaded, Oi is the rnost Significant bit from the most signifi
device.
OUTPUT CONFIGURATION TABLE
Serial Output
Width Expansion
Pin
SO/PO
Parallel
Output
Single
Device
Least Significant
Device
All Other
Devices
Most Significant
Device
HIGH
LOW
LOW
LOW
LOW
-
Output Data
Output Data
Output Data
Output Data
HIGH or LOW
Output Clock
Output Clock
Output Clock
Output Clock
HIGH
HIGH
HIGH
Os of next least
significant device
Os of next least
significant device
R
Read Control
Oi
Oi of most
significant device
Oi of most
significant device
Oi of most
significant device
Q)-Oa
Output Data
No connect
except Di
No connect except Q
No connect except (}
No connect except Oi
-
R of all devices
SO
SOCP
SOX
Oi(1)
Os
-
R
-
SOX of next most
significant device
NOTE:
SOX of next most
significant device
2753lb112
1. Oi refers to the most significant bit of the serial word. If multiple devices are width cascaded, Oi is the most significant bit from the most signifil
device.
5.26
20
IDT72103,IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATAIN
~~--~-------
Vee
EMPTY FLA
RESET
RETRANSMIT
(Q) DATPoUT
2753 drw 31
NOTE:
1. Flag detection is accomplished by monitoring all the flag signals of either (any) device used in the width expansion configuration. Do not connect any
flag signals together.
II
Figure 28. Block Diagram of 2048 X 18/4096 X 18 FIFO Memory Used in Width Expansion in Parallel Mode
TRUTH TABLES
TABLE 2: RESET AND RETRANSMITSINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION IN PARALLEL MODE
Input~2)
Internal Status ' )
Write Pointer
FF
Location Zero
a
1
1
Location Zero
Unchanged
Incremenf 1)
Incremenf 1)
X
X
X
X
X
X
EL
XI.
Read Pointer
Reset
a
x
Location Zero
Retransmit
1
a
Read/Write
1
1
a
a
a
NOTES:
1. Pointer will increment if appropriate flag is HIGH.
2. RS Reset InputLLfBI First LoadlRetransmit.EE
=
=
Outputs
AEF: EF
RS
Mode
HF
2753 tbl13
=Empty Flag OutputEE =Full Flag OutputX!. =Expansion Input.
5.26
21
IDT72103,IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT72103/4 can be easily adapted to applications
where the requirements are for greater than 2048/4096 words.
Figure 29 demonstrates Depth Expansion using three
IDT72103/4s. Any memory depth can be attained by adding
additional IDT72103/4s. The IDT72103/4 operates in the
Depth Expansion configuration when the following conditions
are met:
1. The first device must be designated by grounding the
First Load (FL) control input pin.
2. All other devices must have the FL pin in the high state.
3. The Expansion Out (XO) pin of each device must be tied
to the Expansion In (XI) pin of the next device. See
Figure 29.
4. External logic is needed to generate a composite
Full Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (Le., all must be
set to generate the correct composite FF or EF). See
Figure 29.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion mode.
xo
w------4III----.-r-.L...;...;..I---___--~---R
D
1-4___1---1--1--------
Vee
D--
t-+-+--t--.....
EMPTY
RS ------------------~--~' - - - - - r -.......
XI
2753 drw 32
NOTE:
1. SIIPI and SO/PO pins are tied to VCC.
Figure 29. Block Diagram of 6,144 x 9/12,288 x 9-FIFO Memory, Depth Expansion in Parallel Mode
5.26
22
IDT72103,IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BIDIRECTIONAL MODE
Applications requiring data buffering between two systems
(each system capable of Read and Write operations) can be
achieved by pairing IDT721 03/4 as shown in Figure 30. Both
Depth Expansion and Width Expansion may be used in this
mode.
Rs
EFs
HFs
lOT
72103/04 _
DE
, - -_ _ _ _--..;1'
Os 0-8
SYSTEM A
SYSTEM B
OA0-8
OE
RA
HFA
EFA
Os 0-8
lOT
72103/04
Ws
II
FFs
2573 drw 33
NOTE:
1. SI/PI and SO/PO pins are tied to VCC.
Figure 30. Bidirectional FIFO Mode
COMPOUND EXPANSION MODE
The two expansion techniques described above can be
applied togeth er in a straightforward manner to achieve large
FIFO arrays (see Figure 31).
09-017
00-0 a
Oo-Oa
R.W.RS
•••
----,
09-017
IDT721 031721 04
DEPTH
EXPANSION
IDT721 03/721 04
DEPTH
EXPANSION
BLOCK
BLOCK
•••
IDT721 03/721 04
DEPTH
EXPANSION
BLOCK
DN-8-DN
Do-Da
_ _D_o;...-_D....;,N~_ _ _ _ _ _ _ _D....;,9_-_D_N_ _ _D_1_a_-_D_N • • • DN-8-DN
2753 drw 34
NOTE:
1. SIIPI and SO/PO pins are tied to VCC.
2. For depth expansion block see DEPTH EXPANSION Section and Figure 29.
3. For Flag Detection see WIDTH EXPANSION SECTION and Figure 28.
Figure 31. Compound FIFO Expansion
5.26
23
IOT72103, 10T72104
CMOS PARALLEL-SERIAL FIFO 2048 X 9,4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 3: RESET AND FIRST LOAD TRUTH TABLE DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inoutg2)
Internal Status
Outputs
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset-First
Device
0
0
(1)
Location Zero
Location Zero
0
1
Retransmit all
Other Devices
0
1
(1 )
Location Zero
Location Zero
0
1
Read/Write
1
X
(1 )
X
X
X
X
Mode
NOTES:
1. XI. is connected toXO of previous device.
2. ~= Reset Input.ElJ8T = First Load/Retransmit.EE= Empty Flag OuputEE = Full Flag OutputXl.= Expansion Input.
SERIAL OPERATING MODES:
Serial Data Input
The Serial Input mode is selected by grounding the SIIPI
line. The 00-8 lines are then outputs which are used to
program the width of the serial word. They are taps off a digital
delay line which are meant for connection to the W input. For
instance, connecting 06 to W will program a serial word width
of 7 bits, connecting 07 to W will program a serial word width
of 8 bits and so on.
By programming the serial word width, an economy of
clock cycles is achieved. As an example, if the word width is
6 bits, then on every 6th clock cycle the serial data register is
written in parallel into the FIFO RAM array. Thus, the possible
clock cycles for an extra 3 bits of width in the RAM array are
not required.
The SIX signal is used for Serial-In Expansion. When the
serial word width is 9 or less, the SIX input must betied HIGH.
When more than 9 bits of serial word width is required, more
than one device is required. The SIX input of the least
significant device must be tied HIGH. The D8 pin of the least
significant device must be tied to SIX of the next significant
device. In other words, the SIX input of the most significant
and intermediate devices must always be connected to the 08
of the next least significant device.
Figure 32 shows the relationship of the SIX, SICP and
00-8 lines. In the stand alone case (Figure 32), on the first
LOW-to-HIGHof SICP, the 01-Slinesgo LOWandthe DO line
remains HIGH. On the next SICP clock edge, the 01 goes
HIGH, then 02andsoon. This continues until the 0 line, which
is connected to W, goes HIGH. On the next clock cycle, after
W is HIGH, all of the 0 lines go LOW again and a new serial
word input starts.
In the cascaded case, the first LOW-to-HIGH SICP clock
edge for a serial word will cause all timed outputs (D) to go
LOW except for DO of the least significant device. The 0
outputs of the least significant device will go high on consecutive clock cycles until 08. When 08 goes HIGH, the SIX of the
next device goes HIGH. On the next cycle after the SIX input
is brought HIGH, the OOgoes HIGH; then onthe next cycle 01
and so on. A Oi output from the most significant device is
issued to create the W for all cascaded devices.
2753tbl14
The minimum serial word width is 4 bits and the maximum
is virtually unlimited.
When in the Serial mode, the Least Significant Bit of a serial
stream is shifted in first. If the FIFO output is in the Parallel
mode, the first serial bit will come out on QO. The second bit
shifted in is on Q1 and so on.
In the Serial Cascade mode, the serial input (SI) pins must
be connected together. Each of the devices then receives
serial information together and uses the SIX and 00-8 lines to
determine whether to store it or not.
The example shown in Figure 34 shows the interconnections for a serializing FIFO that transfers data to the internal
RAM in 16-bit quantities (Le. every 16 SICP cycles). This
corresponds to incrementing the write pointer every 16 SICP
cycles.
Once W goes HIGH with the last serial bit in, SICP should
not be clocked again until FF goes HIGH.
5.26
24
10172103,10172104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE DEVICE SERIAL INPUT CONFIGURATION
GND
Vee
SERIAL-IN CLOCK
SERIAL-IN DATA
Vee
4
6
7
o
SICP
Do=1
D1\J
D2\
D3\
D4\
D5\
V
I
\
\
/
I
/
I
I
\
/
D6\
\
/
~
1\
1\
D7 \
iN
I
\
/
\
"'""""~
2753 drw 35
Figure 32. Serial-In Mode Where 8-Bit Parallel Output Data is Read
SERIAL DATA IN
DATA INfTlMED
OUTPUTS Do-a
SERIAL-INPUT _ _ _--....,
CLOCK
~-+--- Si/PI
DELAYED
TIMING
GENERATOR
DATA INTO
FIFO RAM
Figure 33. Serial-Input Circuitry
5.26
25
IDTI2103, IDTI2104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096
x9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL INPUT WIDTH EXPANSION
GND
SERIAL-IN
DATA
SERIAL-IN
CLOCK
Vee
Vee
GND
SI
SICP
---I
I-------t
SI
I - -_ _~
SICP
IDT721 03/1 04
FIFO #2
SIX
00-8
o
SICP
IDT721 03/1 04
FIFO #1
Vee
W
I\J\
D8
7
9
10
14
15
;-\f\f\
55
D60E.FIFO#2~
ANDWOF
FIFO #1 AND
FIFO #2
\
'~
L
'-----------\551. . - - - - - - - - - ,/
2753 drw 37
Figure 34. Serial-In Configuration for Serial-In to Parallel-Out Data of 16 bits
SERIAL INPUT WITH DEPTH EXPANSION
00-7
Vee
GND
Vee
SI/PI
SIX
FuRT
so/po
00-7
R14---'--;-+---R
IDT72104
SI
SICP
XO
Xi
SICP
XI XO
GND
IDT72104
FURT
Vee
SI
SICP
2753 drw 38
SI
NOTE:
1. All SIIPI pins are tied to GND and SO/PO pins are tied to VCC. OE is tied LOW. For FF and EF connections see Figure 29.
Figure 35. An 8K x 8 Serial-In, Parallel-Out FIFO
5.26
26
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048
X
9 AND 4096
X
9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
\tC
l
I
--.
SIX
SI
D8
SIX
SI
SICP
IDT72104
SICP
IDT72104
I
r-'-----
00-8
Xi
W ~
AL..
XO
!
SERIAL
INPUT
CLOCK
I
R
XO
SIX
SI
SICP
IDT72104
Xi
W
IDT72104
1+1-
RL..
I
SIX SI D8 XO
SICP
Xi
IDT72104
•1r
W
R
1+"-
SICP
IDT72104
00-8
00-5
L
~
!
1
w I+tRI+ t - - READ
~
L
PO-8
____________________
XO
SIX SI D5 XO XI
00-8
~
w I+R 14--
~
-. l
L
D5
Xi
00-5
~.
I
SIX SI D8 XO
SICP
Xi
00-8
L
\tC
W~
r
!
•
I
D8
P18-23
P9-17
______________________- - J
~y~
2753 drw39
PARALLEL DATA OUT
NOTE:
1. All SIIPI pins are tied to GND. SO/PO pins are tied to
Figure 36. An 8K X 24 Serial-In, Parallel-Out FIFO Using Six IDT72104s
SERIAL DATA OUTPUT
The Serial Output mode is selected by setting the SO/PO
line LOW. When in the Serial-Out mode, one of the 01-Slines
should be used to control the R signal. In the Serial-Out mode,
the OO-S are taps off a digital delay line. By selecting one of
these taps and connecting it to R, the width of the serial word
to be read and shifted is programmed. For instance, if the 05
line is connected to the R input, on every sixth clock cycle a
new word is read from the FIFO RAM array and begins to be
shifted out. The serial word is shifted out Least Significant Bit
first. If the input mode of the FIFO is parallel, the information
that was written into the DO bit will come out as the first bit of
the serial word. The second bit of the serial stream will be the
01 bit and so on.
In the stand alone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the soep clock, all of the
Q outputs except for 00 go LOW and a new serial word is
started. On the next clock cycle, 01 will go HIGH, 02 on the
next clock cycle and so on, as shown in Figure 37. This
continues until the line, which is connected to R, goes HIGH
at which point all of the 0 lines go LOW on the next clock and
a new word is started.
In the cascaded case, word width of more than 9 bits can
a
II
I
vee. For FURT. FF and EF connections see Rgure 29.
be achieved by using more than one device. By tying the SOX
line of the least significant device HIGH and the SOX of the
subsequent devices to OS of the previous device, a cascaded
serial word is achieved. On the first LOW-to-HIGH clock edge
of soep, all the 0 lines go low except for 00. Just as in the
stand alone case, on each consecutive clock cycle, each 0
line goes HIGH in the order of least to most significant. When
08 (which is connected to the SOX input of the next device)
goes HIGH, the DO of that device goes HIGH, thus cascading
from one device to the next. The line of the most significant
device, which programs the serial word width, is connected to
all R inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is tri-stated, only
the device which is currently shifting out is enabled and driving
the 1-bit bus.
Figure 39 shows an example of the interconnections for a
16-bit serialized FIFO.
Once R goes HIGH with the last serial bit out, soep should
not be clocked again until EF goes HIGH.
5.26
a
27
IDT72103,IDT72104
CMOS PARALLEL-SERIAL FIFO 2048
x 9, 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Vee
GND PARALLEL DATA IN
SERIAL-OUT CLOCK
SERIAL-OUT DATA
GND
Vee
7
0
5
3
7
V
\
\
/
\
'----------/
\
/
/
\
1\
1\
/
/
/
/
''''''~
~
2753 drw 40
NOTE:
1. Input data is loaded in 8-bit quantities and read out serially.
Figure 37. Serial-Out Configuration
5.26
28
IDT72103,IDT72104
CMOS PARALLEL-SERIAL FIFO 2048
x 9 AND 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SOCP-SERIAL
OUTPUT CLOCK
OUTPUT FROM
RAM ARRAY
SO/PO
DELAYED
TIMING
GENERATOR
SERIAL-OUT
REGISTER
SO/PO----t
PARALLEL-OUT DATAl
TIMED OUTPUT 00-8
2753 drw 41
Figure 38. Serial-Output Circuitry
II
PARALLEL DATA IN
16-BITS WIDE
Vee
GND
Si/PI
00-8
SERIAL-OUT
DATA
SO/PO
SOX
1
R
08
a
7
9
10
a aOF FIFO #1 "'"""\
/
AND SOX OF
\
«
FIFO #2
\..---~"}l'~---J
15
0
,rv\f\
S5
\
~
I\.
f
~
06 OF FIFO #2","""\
\
06
14
~
ANDR OF FIFO,
#1 AND FIFO #2
FIFO #2
SOCP
SOX
R
SOCP
SO/PO
00-6
FIFO #1
SOCP
o
GND
SO
SO
SERIAL-OUTPUT
CLOCK
Vee
Vee
7
'--------oi55lr----------
2753 drw42
NOTE:
1_ The parallel Data In is tied to DO-8 of FIFO #1 and DO-6 of FIFO #2.
Figure 39_ Serial-Output for 16-Bit Parallel Data In
5.26
29
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL OUTPUT WITH DEPTH EXPANSION
00-7
00-7
IN ..........-+-+--.... W
10T72104
SOCP~Ir--~==========~__L-L-~L--,
Vee
2753 drw43
SO - t.......- - - - - - - - '
NOTE:
1. All SI/PI pins are tied to
vee and SO/PO pins are tied to GND.
OE is tied LOW. For FF and EF connections see Figure 17.
Figure 40. An 8K x 8 Parallel-In Serial-Out FIFO
SERIAL IN AND SERIAL OUT WITH WIDTH AND DEPTH EXPANSION
SICP
SI
~
FULL
FLAG
.a--
Vee
~
Vee
sOCP
~
SIX
FURT
SIX
SI
SICP
Wl+R~
SOX SO
f
SOCP XO XI 06
1
I
L
~
l
1
SI
SICP XI XO 08
FURT
IOT72104
FF
EF
SOX SO SOCP
r
IN I+-
i
06
10T72104
+
'*
L
+
I
SIX
SI SICP
08
FURT
IN IlOT721 04
FF
Fi~
EF
SOX SO SOCP XO XI 08
I
EMPTY
FLAG
l
V-¥
-J="
t
~
SIX
SI
IN
FURT
10T72104
Fil+08
l
r
SICP XI XO 06
SOX SO
J
I
I
+
so
SOCP
i
..
Fi~
06
1
2753 drw 44
NOTE:
1. All RS pins are connected together. All OE pins are connected LOW. All SIIPI and SO/PO pins are grounded.
Figure 41. 128K x 1 Serial-In Serial-Out FIFO
5.26
30
10172103,10172104
CMOS PARALLEL-SERIAL FIFO 2048
X
9 AND 4096
X
9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
X
XXX
X
x
Power
Speed
Package
Process/
Temperature
Range
y~lank
L--..._ _ _ _ _ _ _- \
1.-_ _ _ _ _ _ _ _ _ _ _-1
P
D
J
40-pin Plastic DIP
40-pin CERDIP
40-pin Plastic Leaded Chip Carrier
35
40
50
Commerical Only (50MHz serial shift rate)
Military
(47MHz serial shift rate)
Com'/. & Mi/'
(40MHz serial shift rate)
I.-----------------f L
1.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
72103
72104
Low Power
2048 X 9-Bit Configurable Parallel-Serial FIFO
4096 x 9-Bit Configurable Parallel-Serial FIFO
2753 drw45
5.26
31
'~J
IDT72105
IDT72115
IDT72125
CMOS PARALLEL-TO-SERIAL FIFO
256 X 16,512 x 16, 1024 x 16
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
•
The IDT721 05/72115/72125s are very high-speed, lowpower,dedicated, parallel-to-serial FIFOs. These FIFOs
possess a 16-bit parallel input port and a serial output port with
256,512 and 1K word depths, respectively.
The ability to buffer wide word widths (x16) make these
FIFOs ideal for laser printers, FAX machines, local area
networks (LANs), video storage and disk/tape controller
applications.
Expansion in width and depth can be achieved using
multiple chips. IDT's unique serial expansion logic makes this
possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO)
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.
Monitoring the FIFO is eased by the availability of four
status flags: Empty, Full, Half-Full and Almost-Empty/AlmostFull. The Full and Empty flags prevent any FI Fa data overflow
or underflow conditions. The Half-Full Flag is available in both
single and expansion mode configurations. The Almost-Emptyl
Almost-Full Flag is available only in a single device mode.
The IDT72105/15/25 are fabricated using IDT's leading
edge, submicron CMOS technology. Military grade product is
manufactured in compliance with the latest revision of MiISTD-883, Class B.
25ns parallel port access time, 35ns cycle time
45MHz serial output shift rate
Wide x16 organization offering easy expansion
Low power consumption (SOmA typical)
Least/Most Significant Bit first read selected by asserting
the FUDIR pin
• Four memory status flags: Empty, Full, Half-Full, and
Almost-Empty/Almost-Full
• Dual-Port zero fall-through architecture
• Available in 28-pin 300 mil plastic DIP, 28-pin SOIC, and
32-pin PLCC
FUNCTIONAL BLOCK DIAGRAM
00-15
RS
1"
WRITE
POINTER
RAM
ARRAY
~r-
256 x 16
512 x 16
1024 x 16
1+-<>-
~
RSIX
RSOX
READ
POINTER
FLAG
LOGIC
EXPANSION
LOGIC
FUDIR
I
~
I-- ~
r-- f-+
r-- f-+
I-- ~
SERIAL OUTPUT
LOGIC
~
i
The lOT logo Is a registered trademark of Integrated Device Technology, Inc.
FAST Is a trademark of National Semiconductor Co.
SO
SOCP
COMMERCIAL TEMPERATURE RANGE
2665 drwOl
AUGUST 1993
DSC-203814
©1995 Integrated Device Technology, Inc.
5.27
1
10172105,10172115, 10172125,
256 X 16, 512 X 16,1024 X 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
o
INDEX
w
01
02
015
014
013
03
04
012
011
05
06
07
010
09
J5
LJLJLJIILJLJLJ
0
'<_________________________________________________________________
\ '---------.r!.--
t WEF
EF ________________________________
~
n-1
~
NOTE 1
socp
NOTE 2
SO
NOTE:
1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.
2665 drw09
Figure 6. Empty Boundary Condition Timing
o
secp
FF
-~f---tDH
DATA IN
------t-----~
DATA IN VALID
'--------------------'
SO
NOTE 1
DATA OUT VALID
2665 drw 10
NOTE:
1. Single Device Mode will not tri-state but will retain the last valid data.
Figure 7. Full Boundary Condition Timing
Vi
1,------..-J/
HALF-FULL
HALF-FULL (112)
HF
HALF-FULL + 1
seep
AEF
AEF
ALMOST-FULL (7/B FULL + 1)
ALMOST-EMPTY
(lIB FULL-l)
lIB FULL
7/B FULL
ALMOST-EMPTY
(lIB FULL-l)
2665 drw 11
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
5.27
7
10172105,10172115, 10172125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
RS
soCP
,,'------1
________: t::! FLS
FUDIR
RSIX
t
---------'>K.-
:}
COMMERCIAL TEMPERATURE RANGES
15
o
F,"~ :=======:-;--_""""
_
-------------------;'r------...I
2665 dlW 12
Figure 9. Serial Read Expansion
OPERATING CONFIGURATIONS
Single Device Mode
The device must be reset before beginning operation so
that aI/ flags are set to location zero. In the standalone case,
the RSIX line is tied HIGH and indicates single device operation to the device. The RSOXlAEF pin defaults to AEF and
outputs the Almost-Empty and Almost-Full Flag.
Width Expansion Mode
.
In the cascaded case, word widths of more than 16 bits can
be achieved by using more than one device. By tying the
RSOX and RSIX pins together, as shown in Figure 11, and
programming which is the Least Significant Device, a cascaded serial word is achieved. The Least Significant Device
is programmed by a LOW on the FUDIR pin during reset. ~II
other devices should be programmed HIGH on the FUDIR pIn
at reset.
PARALLEL DATA IN
D0-15
Vee
SERIAL OUTPUT CLOCK
RSOXlAEF
RSIX
SOCP
SO
ALMOST-EMPTY/FULL FLAG
SERIAL DATA OUT
2665 dlW 13
Figure 10. Single Device Configuration
5.27
8
IDT12105, 1DT12115, IDT12125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
Inputs
RS
FL
Reset
a
ReadlWrite
1
Mode
Internal Status
Outputs
FF
HF
DIR
Read Pointer
Write Pointer
x
X
Location Zero
Location Zero
a
1
1
X
0,1
Increment(1)
Increment(1)
X
X
X
AEF, EF
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
2665 tbt 09
Table 1. Reset and First Load Truth Table-Single Device Configuration
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is three stated,
only the device which is currently shifting out is enabled and
driving the 1-bit bus. NOTE: After reset, the level on the
FUDIR pin decides if the Least Significant or Most Significant
SERIAL OUTPUT CLOCK
PARALLEL DATA IN
-
W
RSIX
~
LOW AT RESET
,,
D0-15
Bit is read first out of each device.
The three flag outputs, Empty (EF), Half-Full (HF) and
Full (FF), should be taken from the Most Significant Device (in
the example, FIFO #2). The Almost-Empty/Almost-Full flag is
not available. The RSOX pin is used for expansion.
~
SOCP
FUDIR
FIFO #1
RSOX
SO
EF
D16-31
-
-
HF
W
FF
RSIX
HIGH AT RESET
1
sOCP
FUDIR
HF ~ HALF-FULL FLAG
FIFO #2
RSOX
EF ~ EMPTY FLAG
SO
FF ~ FULL FLAG
i
SERIAL DATA OUT
2665 drw 14
Figure 11. Width Expansion for 32-bit Parallel Data In
Depth Expansion (Daisy Chain) Mode
The I DT721 05/15/25 can easily be adapted to applications
requiring greater than 1024 words. Figure 12 demonstrates
Depth Expansion using three IDT72105/15/25s and an
IDT74FCT138 Address Decoder. Any depth can be attained
by adding additional devices. The Address Decoder is necessary to determine which FI Fa is being written. A word of data
must be written sequentially into each FIFO so that the data
will be read in the correct sequence. The IDT721 05/15/25
operates in the Depth Expansion Mode when the following
conditions are met:
1. The first device must be programmed by holding FL LOW
at Reset. All other devices must be programmed by holding
FL HIGH at reset.
2. The Read Serial Out Expansion pin (RSOX) of each device
must be tied to the Read Serial In Expansion pin (RSIX) of
the next device (see Figure 12).
3. External logic is needed to generate composite Empty,
Half-Full and Full Flags. This requires the OR-ing of all EF,
HF and FF Flags.
4. The Almost-Empty and Almost-Full Flag is not available
due to using the RSOX pin for expansion.
Compound Expansion (Daisy Chain) Mode
The IDT72105/15/25 can be expanded in both depth and
width as Figure 13 indicates:
1. The RSOX-to-RSIX expansion signals are wrapped
around sequentially.
2. The write (Vii) signal is expanded in width.
3. Flag signals are only taken from the Most Significant
Devices.
4. The Least Significant Device in the array must be
programmed with a LOW on FUDIR during reset.
5.27
9
IDT72105,IDT72115, IDT72125,
256 x 16, 512 x 16,1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
LOW AT RESET
!
....
PA RALLEL DATA IN
00-15
,..... -
FUDIR
RSIX
,
EF
EMPTY
FLAG
J
W
...... SOCP
HF I -
FIFO #1
RSOX
SO
FF
I-
I
ADDRESS 00
DECODER 01
74FCT138 10 I-- ~~
HIGH AT RESET
....
-~
SERIAL 0 UTPUTCLOCK
i
00-15
-
W
FUDIR
RSIX
FIFO #2
SOCP
EF --~HF
RSOX
SO
FF
-,
HALF-FULL
FLAG
I
-- -
I
HIGH AT RESET
..
r
-
i
00-15
f---
W
Y
SOCP
FUDIR
RSIX
EF
HF
FIFO #3
--
FULL
FLAG
I
RSOX
SO
I
FF
I
SERIAL 0 ATA
OUT
2665 drw 15
Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125
Inputs
Mode
AS
FL
Outputs
Internal Status
DIR
Read Pointer
Write Pointer
EF
HF.. FF
Location Zero
0
1
Reset-First Device
0
0
X
Location Zero
Reset All Other Devices
0
1
X
Location Zero
Location Zero
0
1
ReadlWrite
1
X
0,1
X
X
X
X
NOTE:
1. RS
=Reset Input, FUFIR =First Load/Direction, EF =Empty Flag Output, HF =Half- Full Flag Output, FF =Full Flag Output.
2665 tbt 10
Table 2. Reset and First Load Truth Table-WidthlDepth Compound Expansion Mode
5.27
10
IDT72105,IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
AOORESS
OECOOER
74FCT138
PARALLEL OATAIN
00
I
01
10
SERIAL OUTPUT CLOCK
LOW ON RESET
I
~
•
SOCP
~
+
FLlOIR
~ 00-15
EF
W
RSIX
RSOX
SO
I
I
~
•
SOCP
RSIX
t
L--
---
W
RSOX
RSIX
•
SO
'-
I
+
t
SOCP
FLlOIR
SO
I
I
FF
FIFO #4
'-f-+ W
RSOX
RSIX
..
•
SO
I
•
EF
FLlOIR
00-15
EMPTY
FLAG
EF f-f-f-
FF
,
I
HALF-FULL
FLAG
I
I
FULL
FLAG
-r--- r--
1
•
FLlOIR
SOCP
~
FFr---
HF
I
~
r--
1
I
HF
RSOX
SOCP
W
4-
FF
HF
016-31
FIFO #3
.
FIFO #2
EF
FLlOIR
00-15
.... 10-
EF
016-31
+
'-f-+ W
FLlOIR
SOCP
HF
FIFO #1
L.....,
HIGH ON RESET
EF
016-31
RSIX
1
FIFO #5
HF
RSOX
SO
FF
I
I
'----
f-+ W
RSIX
..
FIFO #6
HF
RSOX
FF
I
SO
'-I-
1
SERIAL OATA
OUT
2665 drw 16
Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125
5.27
11
10T72105,10T72115, 10T72125,
256 x 16, 512 x 16,1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
xxxxx
x
x
x
x
Device
Type
Power
Speed
Package
Process/
Temperature
Range
'--------.,/ BLANK Commercial (O°C to +70°C)
TP
'----------------~ SO
J
'--_ _ _ _ _ _ _ _ _ _ _
~
25
50
~----------------------------~ L
L----------------------------------------l
72105
72115
72125
Plastic THINDIP (300mil)
Small Outline (Gull Wing)
Plastic Leaded Chip Carrier
(50 MHz serial shift rate)} Commercial only
(40MHz serial shift rate)
P~rallel A~cess
Time (lA) In ns
Low Power
256 x 16-8it Parallel-to-Serial FIFO
512 x 16-Bit Parallel-to-Serial FIFO
1024 x 16-Bit Parallel-to-Serial FIFO
2665 drw 17
EI
5.27
12
t;)
CMOS PARALLEL-TO-SERIAL FIFO
IOT72131
IOT72141
2048 x 9
4096 x 9
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
The IDT72131n2141 are high-speed, low power parallelto-serial FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IDT72131n2141 can be configured with the IDTs serial-to-parallel FIFOs (IDT7213W2142)
for bidirectional serial data buffering.
The FIFO has a 9-bit parallel input port and a serial output
port~ Wider and deeper parallel-to-serial data buffers can be
built using multiple IDT72131/72141 chips. lOTs unique
Flexishift serial expansion logic (SOX, NR) makes width
expansion possible with no additional components. These
FI FOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IDT72131/141 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The almost-full (7/8), half-full, and almost empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72131/72141 is fabricated using IDTs high-speed
submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD883, Class B.
•
•
•
•
•
•
•
•
35ns parallel port access time, 45ns cycle time
50MHz serial port shift rate
Expandable in depth and width with no external
components
Programmable word lengths including 7-9,16-18,32-36
bit using FlexishiftTM serial output without using any
additional components
Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
Asynchronous and simultaneous read and write
operations
Dual-Port zero fall-through architecture
Retransmit capability in single device mode
Produced with high-performance, low power CMOS
technology
Available in 28-pin ceramic and plastic DIP.
Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
Do-Da
@
FLAG
LOGIC
28
Vee
27
05
~
03
26
06
FF
02
25
07
01
24
08
23
AEF
RAM ARRAY
2048 x 9
4096 x 9
FU:~ RESET LOGIC I
04 06 07 Oa
W
04
EF
2751 drw01
Do
P28-1
Xi
SOX
SOCP
SO
AEF
FF
C28-3
10
19
FURT
RS
EF
XO/HF
GNO
11
18
08
12
17
07
04
13
16
06
GNO
14
15
&
22
21
20
DIP
TOP VIEW
NR
2751 dIW02a
The lOT logo is a registered trademark 01 Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1993
DSG-202914
©1995 Integrated Device Technology, Inc.
5.28
1
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 & 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
00-08
Inputs
I
Data inputs for 9-bit wide data.
RS
Reset
I
When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM
array. HF and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE
after power-up. Wmust be HIGH and SOCP must be LOW during RS cycle.
W
Write
I
A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data setup and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored
in the RAM array sequentially and independently of any ongoing read operation.
Serial Output
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
SOCP
Clock
NR
Next Read
I
To program the Serial Out data word width, connect NR with one of the Data Set pins (04, 06,
07 and 08). For example, NR - 07 programs for a 8-bit Serial Out word width.
FURT
First Loadl
I
This is a dual purpose input. In the single device configuration (XI grounded), activating retransmit
(FURT-LOW) will set the internal READ pointer to the first location. There is no effect on the
WRITE pointer. Wmust be high and SOCP must be low before setting FURT LOW. Retransmit
is not compatible with depth expansion. In the depth expansion configuration, FURT grounded
indicates the first activated device.
Retransmit
Xi
Expansion In
I
!0. the single device configuration, Xi is grounded.
SOX
Serial Output
I
In the Serial Output Expansion mode, the SOX pin of the least significant device is tied HIGH.
The SOX pin of all other devices is connected to the 08 pin of the previous device. Data is then
clocked out least significant bit first. For single device operation, SOX is tied HIGH.
In depth expansion or daisy chain expansion,
XI is connected to XO (expansion out) of the previous device.
Expansion
SO
Serial Output
0
Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first.
In the Serial Width Expansion mode the SO pins are tied together and each SO pin is tristated
at the end of the byte.
FF
Full Flag
0
When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is
HIGH, the device is not full.
EF
Empty Flag
0
When EF goes LOW, the device is empty and further READ operations are inhibited. When EF
is HIGH, the device is not empty. See the description on page 6 for more details.
AEF
Almost-Emptyl
Almost-Full Flag
0
When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
XO/HF
Expansion Out!
Half-Full Flag
0
This is a dual-purpose output. In the single device configuration (XI grounded), the device is more
than half full when HF is LOW. In the depth expansion configuration (XO connected to Xi of the
next device), a pulse is sent from XO to Xi when the last location in the RAM array is filled.
04,06,
07 and
08
Data Set
0
The appropriate Data Set pin (04, 06, 07 and 08) is connected to NR to program the Serial Out
data word width. For example: 06 - NR programs a 7-bit word width, 08 - NR programs a 9-bit
word width, etc.
Vee
Power Supply
Single Power Supply of 5V.
GND
Ground
Single ground at OV.
2751 tbl01
STATUS FLAGS
Number of Words in FIFO
IDT72131
IDT72141
FF
AEF
HF
0
0
H
L
H
L
1-255
1-511
H
L
H
H
EF
256-1024
512-2048
H
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L
H
2048
4096
L
L
L
H
2751 tbl02
5.28
2
II
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 & 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Commercial
Military
Unit
Symbol
Min.
Typ.
Max.
Unit
VTERM
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
5.0
5.5
V
-55 to +125
°C
Commercial Supply
Voltage
4.5
Operating
Temperature
o to +70
Vcc
TA
GND
Supply Voltage
0
0
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
VIH
Input High Voltage
Commercial
2.0
-
-
V
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
VIH
Input High Voltage
Military
2.2
-
-
V
lOUT
DC Output
Current
50
50
mA
VIL(1)
Input Low Voltage
-
-
0.8
V
NOTE:
2751 tbl03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
0
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2751 tbl04
CAPACITANCE (TA =+25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = OV
10
pF
COUT
Output Capacitance
VOUT= OV
12
NOTE:
1. This parameter is sampled and not 100% tested.
pF
2751 tbl05
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee =5.0V ± 10%, TA =O°C to +70°C; Military: Vee =5.0V ± 10%, TA
=-55°C to +125°C)
10172131110172141
10172131110T72141
Commercial
Symbol
IIL(1)
Parameter
Input Leakage Current
(Any Input)
Military
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
-1
-
1
-10
-
10
flA
~A
lOL(2) .
Output Leakage Current
-10
-10
-
10
Output Logic "1" Voltage,
lOUT = -SmA
2.4
-
10
VOH
-
2.4
-
-
V
VOL
Output Logic "0" Voltage
lOUT = 16mA
-
-
0.4
-
-
0.4
V
Icc1(3)
Power Supply Current
140
-
100
160
mA
Average Standby Current
(W =.RS = FURT = VIH)
(SOCP = VIL)
-
90
ICC2(3)
S
12
-
12
25
mA
ICC3(L)(3,4)
Power Down Current
-
-
2
-
-
NOTES:
1. Measurements with 0.4 s VIN s Vee.
2. soep s VIL, 0.4 s VOUT s Vee.
3. lee measurements are made with outputs open.
4. RS =FDRT =W =Vee -0.2V; soep:o:; 0.2V; all other inputs ~ Vcc -0.2V or:O:; 0.2V.
5.28
4
mA
2751 tbl 06
3
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048
x 9 & 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee =5.0V ± 10%, TA =ODC to +70DC; Military: Vee =5.0V ± 10%, TA =-55 DC to +125 DC)
Commercial
IDT72131L35
IDT72141L35
Symbol
Parameter
Min.
Max.
Military
Mil. and Com'l.
IDT72131L40
IDT72141L40
IDT72131L50
IDT72141L50
Min.
Min.
Max.
Max.
Unit
15
MHz
40
MHz
50
-
20
-
30
-
ns
0
-
5
ns
-
50
65
50
-
ns
10
-
-
15
-
ns
30
-
35
-
45
ns
30
35
45
ns
50
-
65
ns
-
50
-
ns
ts
Parallel Shift Frequency
-
22.2
tsocp
Serial-Out Shift Frequency
-
50
-
-
20
PARALLEL INPUT TIMINGS
tos
Data Set-up Time
18
tOH
Data Hold Time
0
twc
Write Cycle Time
45
twpw
Write Pulse Width
35
tWR
Write Recovery Time
10
tWEF
Write High to EF HIGH
tWFF
Write Low to FF LOW
-
tWF
Write'Low to Transitioning HF, AEF
-
45
-
tWPF
Write Pulse Width After FF HIGH
35
-
40
40
ns
SERIAL OUTPUT TIMINGS
tSOHZ
SOCP Rising Edge to SO at High-Z(1)
5
16
5
16
5
26
ns
tSOLZ
SOCP Rising Edge to SO at Low-Z(1)
5
22
5
22
5
22
ns
tsoPO
SOCP Rising Edge to Valid Data on SO
-
18
-
18
-
18
ns
tsox
SOX Set-up Time to SOCP Rising Edge
5
5
-
5
Serial In Clock Width HIGH/LOW
8
8
-
10
-
ns
tSOCW
-
tSOCEF
SOCP Rising Edge (Bit 0 - Last Word) to EF LOW
20
ns
30
35
40
ns
tSOCF
SOCP Rising Edge to HF, AEF, HIGH
30
-
35
-
25
SOCP Risinq Edqe to FF HIGH
-
25
tSOCFF
-
40
ns
tREFSO
Recovery Time SOCP After EF HIGH
35
-
40
-
50
-
ns
50
65
15
-
ns
10
-
ns
RESET TIMINGS
tRSC
Reset Cycle Time
45
tRS
Reset Pulse Width
35
tRSS
Reset Set-up Time
35
tRSR
Reset Recovery Time
10
-
tRSFl
Reset to EF and AEF LOW
-
45
-
50
-
65
ns
tRSF2
Reset to HF and FF HIGH
-
45
-
50
-
65
ns
tRSQL
Reset to
20
-
20
-
35
-
ns
-
50
tRSQH
a LOW
Reset to a HIGH
20
40
40
20
50
50
35
ns
ns
ns
ns
RETRANSMIT TIMINGS
tRTC
Retransmit Cycle Time
45
tRT
Retransmit Pulse Width
35
tRTS
Retransmit Set-up Time
35
-
tRTR
Retransmit Recovery Time
10
-
-
50
40
-
50
10
-
15
-
40
40
40
40
65
-
ns
ns
-
ns
-
50
ns
50
ns
-
50
ns
10
-
10
-
15
-
15
-
ns
ns
DEPTH EXPANSION MODE TIMINGS
tXOL
ReadlWrite to XO LOW
ReadlWrite to XO HIGH
-
35
tXOH
tXI
XI Pulse Width
35
tXIR
XI Recovery Time
10
tXIS
XI Set-up Time
15
-
NOTE:
1. Guaranteed by design minimum times, not tested.
35
ns
2751 tbl 07
5.28
4
II
IDT72131, 1DT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048
x 9 & 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
sv
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.SV
D.U.T. _
See Figure A
Output Load
........_---.
680n
30pF"
2751 tbt 08
2751 drw 03
or equivalent circuit
Figure A. Ouput Load
"Including jig and scope capacitances
FUNCTIONAL DESCRIPTION
Serial Data Output
Parallel Data Input
The data is written into the FIFO in parallel through the
00-8 input data lines. A write cycle is initiated on the falling
edge of the Write (Vii) signal provided the Full Flag (FF) is not
asserted. If the Wsignal changes from HIGH-to-LOW and the
Full-Flag (FF) is already set, the write line is inhibited internally
from incrementing the write pointer and no write operation
occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. The data is written to the RAM at the write
pointer. On the rising edge of W, the write pointer is
incremented. Write operations can occur simultaneously or
asynchronously with read operations.
The serial data is output on the SO pin. The data is clocked
out on the rising edge of soep providing the Empty Flag (EF)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by soep. NOTE: soep should not be clocked
once the last bit of the last word has been clocked out. If it is,
then two things will occur. One, the SO pin will go High-Z and
two, soep will be out of sync with Next Read (NR).
The serial word is shifted out Least Significant Bit first, that
is the first bit will be DO, then 01 and so on up to the serial word
width. The serial word width must be programmed by connecting the appropriate Data Set line (04, 06, 07 or 08) to the NR
input. The Data Set lines are taps off a digital delay line.
Selecting one of these taps, programs the width of the serial
word to be read and shifted out.
~--------------------------tRSC--------------------------~
~------------------tRS------------------~
RS
soep
Q4,06,Q7,Qs
2751 drw 04
Figure 1. Reset
5.28
5
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
twc
w ~.:\
~[-
.,f.
~
J
twpw
tWR
\1
V
00-8
~
tos
I
I
I
tOH
2751 drw05
Figure 2. Write Operation
n-1
\_--
SOCP
sox
t - - - - . j tsox
tSOHZ
SO (2)
tSOLZ
2751 drw06
~---tsoPO
Figure 3. Read Operation
NOTES:
1. This timing applies to the Active Device in Width Expansion Mode.
2. This timing applies to Single Device Mode at Empty Boundary (8=
LAST WRITE
=LOW) and the Next Active Device in Width Expansion Mode.
FIRST READ
IGNORED
WRITE
o
ADDITIONAL
READS
FIRST WRITE
~~-.---------------
SOCP
Figure 4. Full Flag from Last Write to First Read
5.28
2751 drw07
6
iii
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048
LAST READ
o
x 9 & 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NO READ
FIRST WRITE
FIRST READ
n-1
SOCP
(1)
VALID
SO
2751 drw 08
NOTE:
1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
Figure 5. Empty Flag from Last Read to First Write
DATAIN ________~)E~
_______________________________________________________________
(
\
'-----
SOCP
tWEF
(1)
SO
2751 drw 09
NOTE:
1. SOCP should not be clocked until
EF goes HIGH.
Figure 6. Empty Boundary Condition Timing
5.28
7
10T72131, 10T72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SOCP
DATA IN
so
DATAoUT VALID
2751 drw 10
Figure 7. Full Boundry Condition Timing
w
~'---__~I
HALF-FULL (1/2)
HF
HALF-FULL +1
HALF-FULL
SOCP
tWF
AEF
AEF
ALMOST FULL (7/8 FULL + 1)
ALMOST-EMPTY
(1/8 FULL-1)
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
1/8 FULL
2751 drw 11
Figure 8. Half Full, Almost Full and Almost Empty Timings
5.28
8
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048
x 9 & 4096 X 9
MILITARY AND COMMERCI.AL TEMPERATURE RANGES
~------------------------tRTC----------------------~
~----------------tRT----------------~
NOTE:
1. EF, AEF,HF and
2751 drw 12
FF may change status during Retransmit, but flags will be valid at tRTe.
Figure 9. Retransmit
WRITE TO LAST PHYSICAL LOCATION
READ FROM LAST
PHYSICAL LOCATION
,..--------t\
LAST -1
LAST
SOCP
tXOH
tXOL
2751 drw 13
Figure 10. Expansion-Out
-----~~-- tXIR
SOCP
2751 drw 14
Figure 11. Expansion-In
5.28
9
IDT72131.IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048
x 9 & 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Data Set lines (04, 06, 07,08) go LOW and a new serial word
is started. The Data Set lines then go HIGH on the equivalent
soep clock pulse. This continues until the 0 line connected
to NR goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of soep.
Single Device Configuration
In the standalone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the soep clock, all of the
PARALLEL DATA IN
~
00-7
SOCP
SERIAL OUTPUT CLOCK
Vcc
SOX
4
0
SERIAL DATA OUTPUT
SO
GND
XI
6
NR
04 06 07 Oa
I
I I I I
0
6
7
0
SOCP
/
04\
\
/
06\
07\
NR\
''-
/
\
1\
1\
/
II
~
~
2751 drw 15
Figure 12. Eight-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMITSINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION MODE
Inputs
Internal Status
Outputs
RS
FURT
XI
Read Pointer
Write Pointer
AEF, EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment(1 )
Increment(1)
X
X
Mode
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
HF
X
2751 tbl09
5.28
10
IDT72131, 1DT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 & 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can
be achieved by using more than one device. By tying the SOX
line of the least significant device HIGH and the SOX of the
subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of soep, all lines go
LOW. Just as in the standalone case, on each corresponding
clock cycle, the equivalent Data Set line goes HIGH in order
of least to most significant. When the Data Set line which is
connected to the SOX input of the next device goes HIGH, the
Do of that device goes HIGH, the cascading from one device
to the next. The Data Set line of the most significant bit
programs the serial word width by being connected to all NR
inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is three stated,
only the device which is currently shifting out is enabled and
driving the 1-bit-bus.
PARALLEL DATA IN
16-BITS WIDE
f9
,
I
G~D
I
XI
Do-s
SERIAL DATA
OUTPUT
DO-6
SO
SERIAL OUTPUT CLOCK
FIFO #1
NR
r
as
I
I
•
I
1
10
7
SOCP~
as OF FIFO #1 AND~
SOX OF FIFO #2
\.
XI
FIFO #2
SOCP
SOX
o
GNi
SO
SOCP
Vcc
.. I- 7
SOX
NR
1
14
15
06
~
0
/\J\f\
/
~------~\~~------~
06 OF FIFO #2 AND~
NR OF FIFO #1 AND
\.
/
FIFO #2
~------~\ ~~------------------------~\ ~~ _ _---J
2751 drw 16
Figure 13. Width Wxpansion for 16-bit Parallel Data In. The Parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2.
5.28
11
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode
The IDT72131/41 can be easily adapted to applications
where the requirements are for greater than 2048/4096 words.
Figure 14 demonstrates Depth Expansion using three
IDT72131141. Any depth can be attained by adding additional
IDT72131/41 operates in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the
First Load (FL) control input.
---.L
-
~~
SO
SOCP
I
r
XO
Q7
NR
00-7
IN I+----<
SO
SOCP
I
r
~
XO
XI
vtc
Q7
NR
~Z
W ~
SO
SOCP
I
r
~
tJ
00-7
FIFO #3
IDT72141
FURT
11
~Z
FIFO #2
IDT72141
FURl"
SOX
00-7
IN
XI
SOX
00-7
FIFO #1
IDT72141
SOCP
-c.
5.
All other devices must have FL in the HIGH state.
The Expansion Out (XO) pin of each device must be
tied to the Expansion In (Xi) pin of the next device.
External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (Le., all must be
set to generate the correct composite FF or EF).
The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion mode.
XI
~
so
4.
--
FURT
SOX
~
2.
3.
XO
Q7
NR
11
2751 drw 17
Figure 14. A 12K x 8 Parallel-In Serial-Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
Mode
RS
FL
Outputs
Internal Status
XI
Read Pointer
Write Pointer
EF
FF
Location Zero
0
1
Reset-First
Device
0
0
(1 )
Location Zero
Reset-All
Other Devices
0
1
(1 )
Location Zero
Location Zero
0
1
ReadlWrite
1
X
(1 )
X
X
X
X
NOTES:
1. Xi is connected to XO of previous device.
2. RS = Reset Input, FDRT = First Load/Retransmit,
2751 tbl10
EF = Empty Flag Ouput, FF = Full Flag Output, Xi = Expansion Input.
5.28
12
IDT72131,IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 & 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
x
xxx
x
x
Power
Speed
Package
Process!
Temperature
Range
y~lank
'--------------i
Commercial (O°C to +70°C)
Military (-SSOC to + 12S°C)
Compliant to MIL-STD-883, Class B
P
C
Plastic DIP
Sidebraze DIP
3S·
(SOMHz serial shift rate) }
(SOMHz serial shift rate)
(40MHz serial shift rate)
' - - - - - - - - - - - - - - - 1 40
so
'---_ _ _ _ _ _ _ _ _ _ _ _ _ _--1 L
'---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 72131
72141
Parallel Access Time (":
Low Power
2048 x 9-Bit Parallel-Serial FIFO
4096 x 9-Bit Parallel-Serial FIFO
2751 drw 18
5.28
13
G
CMOS SERIAL-TO-PARALLEL FIFO
2048 X 9
4096 X 9
IDT72132
IDT72142
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
The IDT72132172142 are high-speed, low-power serial-toparallel FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IDT72132172142 can be configured with the IDTs parallel-to-serial FIFOs (IDT72131fi2141)
for bidirectional serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output
port. Wider and deeper serial-to-parallel data buffers can be
built using multiple IDT72132172142 chips. IDTs unique
Flexshift serial expansion logic (SIX, NW) makes width
expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IDT72132/142 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The Almost-Full (7/8), Half-Full, and Almost Empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72132/72142 is fabricated using IDTs high-speed
submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD883, Class B.
•
•
•
•
•
•
•
•
35ns parallel-port access time, 45ns cycle time
50MHz serial port shift rate
Expandable in depth and width with no external
components
Programmable word lengths including 8,9,16-18, and
32-36 bit using FlexshiftTM serial input without using any
additional components
Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
Asynchronous and simultaneous read and write
operations
Dual-Port zero fall-through architecture
Retransmit capability in single device mode
Produced with high-performance, low-power CMOS
technology
Available in the 28-pin ceramic and plastic DIPs
Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
SICP
Bff
SIX
SI
FLAG
LOGIC
AEF
~
FF
RAM ARRAY
2048 x 9
4096 x 9
R
NW
Vee
GNO
07
XI
08
FURT
AEF
FF
RS
00
P28-1
01
C28-3
&
02
SIX
03
OE
EF
04
GNO
2752 dow 01
SI
SICP
XO/HF
R
GNO
Os
08
06
07
DIP
TOP VIEW
2752 dow 02
The lOT logo is a registered trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1993
DSC-203Of4
©199S Integrated Device Technology, Inc.
5.29
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
VO
Name
Description
SI
Serial Input
I
Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input
(SI) pins are tied together and SIX plus 07, Os determine which device stores the data.
RS
Reset
I
When RS is set LOW, internal READ and WRITE pointers are set to the first location of the
RAM array. HF and FF go HIGH, and AEF, and EF go LOW. A reset is required before an initial
WRITE after power-up. R must be HIGH during an RS cycle.
NW
Next Write
I
To program the Serial In word width, connect NW with one of the Data Set pins (07, Os).
SICP
Serial Input Clock
I
Serial data is read into the serial input register on the rising edge of SICP. In both Depth and
Serial Word Width Expansion modes, all of the SICP pins are tied together.
R
Read
I
When READ is LOW, data can b~ad from the RAM array sequentially, independent of SICP.
In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the
internal READ operation is blocked and Oo-Os are in a high impedance condition.
FURT
First Loadl
Retransmit
I
This is a dual-purpose input. In the single device configuration (XI grounded), activating
retransmit (FURT-LOW) will s~t the internal READ pointer to the first location. There is ~
effect on the WRITE pointer. R must be HIGH and SICP must be LOW before setting FURT
LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration,
FURT grounded indicates the first activated device.
XI
Expansion In
I
In the single device configuration, XI is grounded. In depth expansion or daisy chain
expansion, Xi is connected to XO (expansion out) of the previous device.
SIX
Serial Input
I
In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin
of all other devices is connected to the 07 or Os pin of the previous device. For single device
operation, SIX is tied HIGH.
Output Enable
I
When OE is set LOW, the parallel output buffers receive data from the RAM array. When OE
is set HIGH, parallel three state buffers inhibit data flow.
Oo-Qs
Output Data
FF
Full Flag
0
0
EF
Empty Flag
0
When EF goes LOW, the device is empty and further READ operations are inhibited. When
EF is HIGH, the device is not empty.
AEF
Almost-Emptyl
Almost-Full Flag
0
When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
XO/HF
Expansion OuV
. Half-Full Flag
0
This is a dual-purpose output. In the single device configuration (XI grounded), the device is
more than half full when HF is LOW. In the depth expansion configuration (XO connected to
Xi of the next device), a pulse is sent from XO to Xi when the last location in the RAM array
is filled.
07,08
Data Set
0
The appropriate Data Set pin (07, Os) is connected to NWto prog~ the Serial In data word
width. For example: 07 - NW programs a 8-bit word width, Os - NW programs a 9-bit word
width, etc.
Expansion
OE
Data outputs for 9-bit wide data.
When FF goes LOW, the device is full and data must not be clocked by SICP. When FF is
HIGH, the device is not full. See the diagram on page 7 for more details.
lIee
Power Supply
Single Power Supply of 5V.
GNO
Ground
Three grounds at
av.
2752 tbl 01
STATUS FLAGS
Number of Words in FIFO
.EE
10172132
10172142
EE
A.EE
HE
0
0
H
L
H
L
1-255
1-511
H
L
H
H
256-1024
512-2048
H
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L
H
2048
4096
L
L
L
H
2752 tbl 02
5.29
2
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 X 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Rating
Commercial
Military
Unit
Symbol
Min.
Typ.
VTERM
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
5.0
5.5
V
-55 to +125
°C
Commercial Supply
Voltage
4.5
Operating
Temperature
o to +70
VCC
TA
0
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
NOTE:
2752 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
Max. Unit
GND
Supply Voltage
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
VIL(1)
Input Low Voltage
-
-
O.S
V
0
0
NOTE:
1. 1.SV undershoots are allowed for 10ns once per cycle.
2752 tbl 04
CAPACITANCE (TA = +25"C, f = 1.0MHz)
Parameter(1)
Max.
Unit
CIN
Input Capacitance
VIN = OV
10
pF
COUT
Output Capacitance
VOUT= OV
12
Symbol
Conditions
NOTE:
1. This parameter is sampled and not 100% tested.
pF
2752 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc =5.0V ± 10%, TA
=O°C to +70°C; Military:
Vcc =5.0V
± 10%, TA =-55°C to +125°C)
IDT7213211DT72142
Military
IDT7213211DT72142
Commercial
Symbol
IIL(1)
Max.
Min.
Typ.
Max.
Unit
Input Leakage Current
(Any Input)
-1
-
1
-10
-
10
~A
10
~A
Parameter
Min.
Typ.
IOL(2)
Output Leakage Current
-10
-10
Output Logic "1" Voltage,
lOUT = -2mA
2.4
-
10
VOH
-
2.4
-
-
V
VOL
Output Logic "0" Voltage,
IOUT- SmA
-
-
0.4
-
-
0.4
V
ICC1(3)
Power Supply Current
140
-
100
160
mA
Average Standby Current
(R = RS = FURT = VIH)
(SICP = VIL)
-
90
ICC2(3)
S
12
-
12
25
mA
ICC3(L)(3,4)
Power Down Current
-
-
2
-
-
4
mA
NOTES:
1. Measurements with 0.4 ~ VIN s Vee.
2. R ~ VIL, 0.4 ~ VOUT ~ Vee.
3. Ice m.llil.lillf.emj1nts are made with outputs open.
4. RS FURT R Vee -0.2V; SICP S; 0.2V; all other inputs ~ Vee -0.2V or S; 0.2V.
=
2752 tbl 06
= =
5.29
3
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048
x 9 AND 4096 x 9·
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Commercial: Vee= 5.0V + 10%, TA = O°C to +70°C; Military: Vee = 5.0V ± 10%, TA = -55°C to +125°C)
Symbol
Parameter
ts
Parallel Shift Frequency
tSICP
Serial-lnShift Frequency
Commercial
IDT72132L35
IDT72142L35
Min.
Max.
-
22.2
Military
IDT72132L40
IDT72142L40
Min.
Max.
20
50
-
Mil. and Com'l.
IDT72132L50
IDT72142L50
Min.
Max.
Unit
15
MHz
50
-
40
MHz
PARALLEL OUTPUT TIMINGS
tA
Access Time
-
35
-
40
-
50
ns
tRR
tRPW
Read Recoverv Time
Read Pulse Width
10
35
10
40
Read Cycle Time
45
Read Pulse LOW to Data Bus at Low-Z(1)
5
-
5
10
-
ns
ns
tRLZ
-
15
50
tRC
-
tRHZ
Read Pulse HIGH to Data Bus at High-Z(1)
-
20
-
25
-
30
ns
tov
Data Valid from Read Pulse HIGH
Output Enable to High-Z (Disable)ll)
5
-
5
-
5
-
-
15
-
15
-
15
ns
ns
~tOEHZ
50
65
ns
ns
tOELZ
Output Enable to Low-Z (Enable)(l)
5
-
5
-
5
-
ns
tAOE
Output Enable to Data Valid (Oo-a)
-
20
-
20
-
22
ns
-
12
-
15
-
0
5
10
-
ns
0
5
SERIAL INPUT TIMINGS
tSIS
Serial Data in Set-Up Time to SICP Rising Edge
12
tSIH
tSIX
Serial Data in Hold Time to SICP Rising Edge
SIX Set-Up Time to SICP Rising Edge
0
5
tSICW
Serial-In Clock Width HIGH/LOW
8
-
8
-
ns
ns
ns
FLAG TIMINGS
tSICEF
SICP Rising Edge (Last Bit - First Word) to EF HIGH
65
ns
30
45
-
-
SICP Rising Edge (Bit 1 - Last Word) to FF LOW
SICP Rising Edge to HF, AEF
-
50
tSICFF
tSICF
35
50
-
40
-
65
ns
ns
tRFFSI
Recovery Time SICP After FF Goes HIGH
15
-
15
-
15
-
ns
tREF
Read LOW to EF LOW
30
45
ns
Read HIGH to FF HIGH
35
-
45
ns
tRF
tRPE
Read HIGH to Transitioning HF and AEF
45
-
35
tRFF
-
50
-
65
ns
35
-
40
-
50
-
ns
50
65
ns
Read Pulse Width After EF HIGH
RESET TIMINGS
45
30
tRSC
Reset Cycle Time
45
tRS
Reset Pulse Width
35
-
40
-
50
tRSS
Reset Set-up Time
35
-
40
-
50
tRSR
Reset Recovery Time
10
-
10
-
15
-
tRSF1
Reset to EF and AEF LOW
-
45
65
Reset to HF and FF HIGH
-
45
50
50
-
tRSF2
-
-
65
ns
ns
ns
tRSOL
tpOI
Reset to D LOW
20
-
20
-
35
-
ns
SICP Rising Edge to D
5
17
5
17
5
20
ns
45
50
40
65
50
-
ns
-
ns
-
ns
ns
ns
RETRANSMIT TIMINGS
tRTC
Retransmit Cycle Time
tRT
Retransmit Pulse Width
35
tRTS
35
-
Retransmit Recovery Time
DEPTH EXPANSION MODE TIMINGS
tXOL
Read/Write to XO LOW
txOH
Read/Write to XO HIGH
10
-
10
-
-
40
40
-
45
45
-
50
tXI
XI Pulse Width
35
-
50
XI Recovery Time
XI Set-up Time
10
-
40
tXIR
10
-
10
-
Retransmit Set-up Time
tRTR
tXIS
16
NOTE:
1. Guaranteed by design minimum times, not tested
40
15
50
15
15
50
ns
ns
ns
ns
ns
ns
2752 tbl 07
5.29
4
10172132,10172142
CMOS SERIAL-TO-PARALLEL FIFO 2048 X 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
5V
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.1K
n
1.5V
D.U.T. - - . - -...
See Figure A
2752 tbl 08
680n
30pF*
"::"
2752 drw03
or equivalent circuit
Figure A. Output Load
*Includies jig and scope capacitances
FUNCTIONAL DESCRIPTION
Serial Data Input
The serial data is input on the SI pin. The data is clocked
in on the rising edge of SICP providing the Full Flag (FF) is not
asserted. If the Full Flag is asserted then the next parallel data
word is inhibited from moving into the RAM array. NOTE:
SICP should not be clocked once the last bit of the last word
has been shifted in, as indicated by NW HIGH and FF LOW.
If it is, then the input data will be lost.
The serial word is shifted in Least Significant Bit first. Thus,
when the FIFO is read, the Least Significant Bit will come out
on 00 and the second bit is on 01 and so on. The serial word
width must be programmed by connecting the appropriate
Data Set line (07, Os) to the NW input. The data set lines are
taps off a digital delay line. Selecting one of these taps
programs the width of the serial word to be written in.
Parallel Data Output
A read cycle is initiated on the falling edge of Read (R)
provided the Empty Flag is not set. The output data is
accessed on a first-in/first-out basis, independent of the
ongoing write operations. The data is available tA after the
falling edge of R and the output bus Q goes into high impedance after R goes HIGH.
Alternately, the user can access the FIFO by keeping R
LOW and enabling data on the bus by asserting Output Enable
(OE). When R is LOW, the OE signal enables data on the
output bus. When R is LOW and OE is HIGH, the output bus
is three-stated. When R is HIGH, the output bus is disabled
irrespective of OE.
~-----------------------tRSC--------------------~~
~-------------------tRS------------------~
SICP
tPDI
D7,D3
QO~~~~~~---------------------------------------~
2752 drw 04
NOTE:
1. Input bits are numbered 0 to n-1. D7 and D8 correspond to n=S and n=9 respectively
Figure 1. Reset
5.29
5
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048
x 9 AND 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
0-1 (1)
J
SICP
\'----
SIX
SI
2752 drw 05
Figure 2. Write Operation
NOTE:
1. Input bits are numbered 0 to n-1.
tRC
--------------~~~------------tRR
Qo-a - - - - 1 - - - - - - - 1 :
VALID DATA
tov
~-------
tA
tRHZ
----------~
2752 drw 06
Figure 3. Read Operation
~--------------------------tRC-----------------------------~
Qo-a -------------~
2752 drw07
Figure 4. Output Enable Timings
5.29
6
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 X 9 AND 4096 X 9
LAST WRITE
NO WRITE
SICP
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIRST READ
ADDITIONAL
READS
FIRST WRITE
(1)
2752 drw 08
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 5. Full Flag from Last Write to First Read
LAST READ
IGNORED
READ
ADDITIONAL
WRITES
FIRST WRITE
FIRST READ
n-1
n-1
SICP
DATA OUT
2752 drw 09
Figure 6. Empty Flag from Last Read to First Write
~---
o
SECOND SERIAL-IN W~
FIRST SERIAL-IN WORD
I
~
'~
n-1
SICP
~------------tA
DATA OUT
2752 drw 10
Figure 7. Empty Boundry Condition Timing
5.29
7
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
n-1
SICP
/\--
(1)
SI
14--~tA
DATA OUT
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
2752 drw 11
Figure 8. Full Boundry Condition Timing
0
n-2
SICP
HALF-FULL
HF
R
AEF
AEF
7/8 FULL
ALMOST FULL (7/8 + 1)
ALMOST-EMPTY
(1/8 FULL-1)
ALMOST-EMPTY
(1/8 FULL-1)
1/8 FULL
2752 drw 12
Figure 9. Half Full, Almost Full and Almost Empty Timings
~---------------------tRTC--------------------~~
~---------------tRT---------------4~
2752 drw 13
NOTE:
1. EF, AEF,HF and FF may change status during Retransmit, but flags will be valid at tRTe.
Figure 10. Retransmit
5.29
8
10172132,10172142
CMOS SERIAL-TO-PARALLEL FIFO 2048 X 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE TO LAST PHYSICAL LOCATION
o
1
n-l
SICP
~
READ FROM LAST
PHYSICAL LOCATION
__
~~
____
~I~~\~
~_tXOH
__
2752 drw 14
Figure 11. Expansion-Out
---_~--tXIR
SICP
Read from
physical location
Write to first
physical location
2752 drw 15
Figure 12. Expansion-In
5.29
9
IDT72132, 1DT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 X 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SIX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SICP clock, both of the
Data Set lines (07, Os) go LOW and a new serial word is
started. The Data Set lines then go HIGH on the equivalent
SICP clock pulse. This continues until the 0 line connected to
NW goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SICP.
SERIAL DATA IN
~
SI
SICP
SERIAL INPUT CLOCK
\tc
00-8
-
SIX
XI
NW
PARALLEL DATA OUTPUT
GND
D7 D8
i
I
SICP
----'1
~
\\.-_ _ _ _ _---..JI
D7 \ \ . . -_ _ _ _ _
---J/\
~
D8 \ " - _ _ _ _
NW\~_ _ _ _ _ _ _ _ _ _ _ _ _ _~;__\~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
2752 dlW 16
Figure 13. Nine-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION MODE
Internal Status
Inputs
Outputs
HF
RS
FURT
XI
Read Pointer
Write Pointer
AEF, EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment\l)
Increment\ 1 )
X
X
Mode
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
X
2752 tbl 09
5.29
10
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 X 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can
be achieved by using more than one device. By tying the SIX
line of the least significant device HIGH and the SIX of the
subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of SICP, both the
Data Set lines go LOW. Just as in the standalone case, on
each corresponding clock cycle, the equivalent Data Set line
goes HIGH in order of least to most significant.
SERIAL DATA IN
1
l
Q~7 W
SI
SICP
SERIAL-IN CLOCK
FIFO #1
NW
07
r
0
I
SOCP~
07 OF FIFO #1
AND SIXOF
FIFO #2
0 7 OF FIFO #2
AND NWTO
FIFO #1 AND
FIFO #2
\
\
QO-7
PARALLE L
DATAOUT
8
FIFO #2
SICP
SIX
NW
07
I
10
7
1
SI
r
SIX
\tc
8
I
+
1
14
15
0
Af\J\
\J
n
n
n
/
''-
II
2752 drw 17
Figure 14. Serial-In to Parallel-Out Data of 16 Bits
5.29
11
IDT72132,1DT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode
The IDT72132/42 can be easily adapted to applications
where the requirements are for greaterthan 2048/4096 words.
Figure 15 demonstrates Depth Expansion using three
IDT72132142. Any depth can be attained by adding additional
IDT72132142 operates in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the
First Load (FL) control input.
2.
3.
4.
5.
All other devices must have FL in the high state.
The Expansion Out (XO) pin and Expansion In (Xi) pin
of each device must be tied together.
External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (Le., all must be
set to generate the correct composite (FF) or (EF).
The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion mode.
r--.
I I
\ C c - SIX
~
00-7
FIFO #1
IDT72142
FURT
SI
SICP
t
SICP
~
00-7
v
R
XO
Xi
D7
XI
XO
00-7
r
NW
I I
FIFO #2
IDT72142
SIX
FURT
SI
R ~
D7
SICP
t
SI
n
NW
n
r
2752 drw 18
Figure 15. An 8K x 8 Serial-In Parallel-Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
Outputs
Internal Status
RS
FURT
XI
Read Pointer
Write Pointer
EF
FF
0
0
(1 )
Location Zero
Location Zero
0
1
Reset all
Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
ReadlWrite
1
X
(1 )
X
X
X
X
Mode
Reset~First
Device
NOTES:
1. Xi is connected to XO of the previous device.
2. RS = Reset input, FURT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output,
5.29
2752 tbll0
Xi = Expansion Input.
12
IDT72132,IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
l
vtc,
SI
SIX
,-1----
R
Xi
QO-7
I
•
1
vtc,
R
Xi
..
I
Xi _
NW 1+1-
SICP
R
L
NW ~
RI-
.. l
I
Xi _
I+r--
NW
L-..t SICP
XO
R
r
SIX SI D7 XO XI _
NW 1+1L-..t SICP
RI+1 - - - READ
QO-7
QO-7
QO-7
l
~
~
~
P8-15
P16-23
!
Xi
QO-7
XO
t
SIX SI D7 XO
!
PO-7
r
D7
SICP
•
SIX SI D7 XO
SERIAL
INPUT
CLOCK
~r---
NW
QO-7
I
SI
SIX
SICP
XO
l
•
I
D7
SI
SIX
NW + - - - -
SICP
l
•
I
D7
2752 drw 19
y
PARALLEL DATA OUT
Figure 16. An 8K x 24 Serial-In, Parallel-Out FIFO Using Six IDT72142s
ORDERING INFORMATION
IDT XXXXX
Device
Type
X
XXX
x
x
Power
Speed
Package
Process!
Temperature
Range
yglank
L - - - - - - - - il
P
IC
I 35
~----------------~140
50
~--------------------------~I L
I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I
72132
72142
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze DIP
(50MHz serial shift rate)}
(50MHz serial shift rate)
Parallel Access Time (t A )
(40MHz serial shift rate)
Low Power
2048 x 9-Bit Serial-Parallel FIFO
4096 x 9-Bit Serial-Parallel FIFO
2752 drw 20
5.29
13
SPECIALITY MEMORY PRODUCTS
•
MULTI-PORT RAMS
Integrated Device Technology has emerged as the leading
multi-port RAM supplier by combining CMOS/BiCMOS technology with innovative circuit design. With system performance advantages as a goal, we have brought system design
expertise together with circuit and technology expertise in
defining dual-port and four-port RAM products. Our dual-port
memories are now industry standards. The synergistic relationship between advanced process technology, system expertise and unique design capability add value beyond that
normally achieved. As an example, our dual-port memories
provide arbitration along with a completely tested solution to
the metastability problem. Various arbitration techniques are
available to the designer to prevent contention and system
wait states. On-chip hardware arbitration, "semaphore" token
passing or software arbitration allow the most efficient memory
to be selected for each application. At IDT, innovation counts
only when it provides system advantages to the user.
IDT offers the largest selection of Multi-Port RAMS in the
industry with offerings in x8, x9 and x16 configurations. We
also offer a wide variety of packaging option with most product
available in plastic DIP, Ceramic DIP, ceramic flat pack, PGA,
PLCC, LCC as well as our latest innovation the space-saving
TQFP(Thin Quad Flat Pack).
IDT has embarked on a mission to reduce the cost of a shared
memory solutions We will accomplish this though the introduction of higher density products offered at a m~ch lower cost
per bit as well as continuing to cost reduce exiSting products
by upgrading them to our latest technology. The combination
of these will continue to drive down the cost of a ''True DualPort" shared memory solution no matter what the size or
configuration that is needed.
Both commercial and military versions of alllDT memories are
available. Our military devices are manufactured and processed strictly in conformance with all the administrative
processing and performance requirements of MIL-STD-883.
Because we anticipated increased military radiation resistance requirements, all devices are also offered with special
radiation resistant processing and guarantees. As the leading
supplier of military specialty RAMs, IDT provides performance
and quality levels second to none.
Our commercial dual-port and four-port memories, in fact,
share most processing steps with military devices.
I
6.0
TABLE OF CONTENTS
SPECIALTY MEMORY PRODUCTS
x8 Dual-Port Section
IDT7130/40SAlLA
IDT7132/42SA/LA
IDT71321/421 SAiLA
IDT7134SA/LA
IDT71342SA/LA
IDT7005S/L
IDT7006S/L
IDT7007S/L
IDT7008S/L
Page
8K (1 K x 8) Dual-Port RAM ................................................................................... 6.01
16K (2K x 8) Dual-Port RAM ................................................................................. 6.02
16K (2K x 8) Dual-Port RAM wI Inter ................................................................... 6.03
32K (4K x 8) Dual-Port RAM ................................................................................. 6.04
32K (4K x 8) Dual-Port RAM wI Sem ................................................................... 6.05
64K (8K x 8) Dual-Port RAM ................................................................................. 6.06
128K (16K x 8) Dual-Port RAM ............................................................................. 6.07
256K (32K x 8) Dual-Port RAM ............................................................................ 6.08
512K (64K x 8) Dual-Port RAM ............................................................................ 6.09
x9 Dual-Port Section
IDT70121/125S/L
IDT7014S
IDT7015S/L
IDT7016S/L
x16 Dual-Port Section
IDT7133/43SA/LA
IDT7024S/L
IDT7025S/L
IDT7026S/L
IDT70261 S/L
IDT7027S/L
18K (2K x 9)
36K (4K x 9)
72K (8K x 9)
144K (16K x
Dual-Port RAM wI Inter ................................................................... 6.10
Dual-Port RAM ................................................................................. 6.11
Dual-Port RAM ................................................................................. 6.12
9) Dual-Port RAM ............................................................................ 6.13
32K (2K x 16) Dual-Port RAM ............................................................................... 6.14
64K (4K x 16) Dual-Port RAM ............................................................................... 6.15
128K (8K x 16) Dual-Port RAM ............................................................................ 6.16
256K (16K x 16) Dual-Port RAM .......................................................................... 6.17
256K (16K x 16) Dual-Port RAM wI Inter ............................................................. 6.18
512K (32K x 16) Dual-Port RAM .......................................................................... 6.19
Synchronous Dual-Port Section
36K (4K x 9) Synchronous Dual-Port RAM .......................................................... 6.20
IDT7099S
512K (64K x 8) Synchronous Dual-Port RAM ...................................................... 6.21
I DT70908S/L
512K (32K x 16) Synchronous Dual-Port RAM .................................................... 6.22
IDT70927S/L
Four-Port™ Section
IDT7052S/L
16K (2K x 8) Four-Port™ RAM .............................................................................. 6.23
SARAMTM Section
I DT70824S/L
I DT70825S/L
64K (4K x 16) Sequential Access RAM ............................................................... 6.24
128K (8K x 16) Sequential Access RAM ............................................................. 6.25
3.3V x8 Dual-Port Section
IDT71 V321 SA/LA
IDT70V05S/L
IDT70V06S/L
IDT70V07S/L
16K (2K x 8) 3.3V Dual-Port RAM ........................................................................
64K (8K x 8) 3.3V Dual-Port RAM ........................................................................
128K (16K x 8) 3.3V Dual-Port RAM ....................................................................
256K (32K x 8) 3.3V Dual-Port RAM ....................................................................
6.26
6.27
6.28
6.29
3.3V x16 Dual-Port Section
I DT70V24S/L
IDT70V25S/L
I DT70V26S/L
IDT70V261 S/L
64K (4K x 16) 3.3V Dual-Port RAM ......................................................................
128K (8K x 16) 3.3V Dual-Port RAM ....................................................................
256K (16K x 16) 3.3V Dual-Port RAM ..................................................................
256K (16K x 16) 3.3V Dual-Port RAM wI Inter....................................................
6.30
6.31
6.32
6.33
6.0
2
(~5
IDT7130SAlLA
IDT7140SAlLA
CMOS DUAL-PORT RAM
8K (1 K x 8-BIT)
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High-speed access
-Military: 25/35/55/1 OOns (max.)
-Commercial: 25/35/55/100ns (max.)
-Commercial: 20ns in PLCC only for 7130
• Low-power operation
-IDT7130/IDT7140SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
-IDT7130/IDT7140LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
• MASTER IDT7130 easily expands data bus width to
16-or-more-bits using SLAVE IDT7140
• On-chip port arbitration logic (IDT7130 Only)
• BUSY output flag on IDT7130; BUSY input on IDT7140
• INT flag for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention (LA only)
• TTL-compatible, single 5V ±1 0% power supply
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-86875
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" DualPort RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results iniull-speed, error-free
operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consuming 200llW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCCs
and 64-pin TQFPs. Military grade product is manufactured
in compliance with the latest revision of MIL-STD-883, Class
B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
r~
"\
11
_./
\.
~
4{
Il00L-1I07L
1/0
Control
1,2)
As L
AOL
..
+
Address
Decoder
A
"-
"
v
L.
A
J\.
~
j
INT~
A
"-
"
v
'0
ca,
1
I
1I00R-1I07R
+
MEMORY
ARRAY
OEL
RlWL
2)
I
1/0
Control
ARBITRATION
and
INTERRUPT
LOGIC
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
Address
Decoder
..
ASR
AOR
I
:~
OER
RlWR
t
INTR(2)
2689dIW01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~1995
f-
'0
NOTES:
1. IDT7130 (MASTER): BUSY is open
drain output and requires pullup
resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor.
I
1
[
APRIL 1995
DSC-l00014
Integrated Device Technology, Inc.
6.01
1
IDT7130SAILA AND IDT7140SA/LA
CMOS DUAL-PORT RAM BK (1 K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
CEL
RIWL
BUSYL
INTL
OEL
AOL
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/OOL
I/01L
I/02L
I/03L
I/04L
I/05L
I/06L
I/07L
GND
Vee
1
2
3
4
5
6
7
8
a:
..J
CER
RIWR
BUSYR
INTR
OER
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/07R
1I06R
I/05R
I/04R
I/03R
I/02R
I/01R
I/OOR
llii
~ I~ ~ I~
ffi
..J
INDEX""
llii a:
I~I~ ~ I~ I~ ffil~ ~
a:
..J
LJLJLJLJLJLJIILJLJLJLJLJLJ
7 6 5 4 3 2
LJ
1
52 51 50 49 48 47
46[
OEA
45[
AOA
44[
AlA
A2R
All
J8
A2l
A3l
A4l
J9
J10
J 11
ASl
J12
ASl
J13
A7l
J14
40[
ASA
ASl
J15
39[
ASA
A9l
I/00l
J16
38[
37[
A7R
I/Oll
I/02l
J18
J19
1I03l
J20
43[
IDT7130/40
J52-1
42[
41[
52-PIN PLCC
TOP VIEW (1)
J17
21 2223 2425 2627 2829 3031 3233
A3A
A4A
36[
ASA
A9A
35[
34[
N/C
I/07A
nnnnnnnnnnnnn
U C a: a: a: a: a: a: a:
oooozz8c5ooooo
Cl::::::::::::::::::::::::::::::
..J
..J
..J
..J
2689drw04
::::::::::::::::
2689 drw02
~ I~I~ I~~ I~I~
INDEX""
..J
a:
..Jr-
1
42[
41[
A2l J8
40[
A3l J9
A4l J10
ASl J 11
A6l J12
A7L
39[
IDT7130/40
L48-1
38[
&
37[
F48-1
J13
ASl J14
ASl J15
I/OOl J16
1I01l ]17
36[
48-PIN LeCI FLATPACK
TOP VIEW (1)
..J
ZZZ-tD
LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ
6 5 4 3 2 L ~ 48 47 46 45 44 43
A1l J7
[I:
QQ QI~ ~I~I~U»U
ggl~l~a:llii~I~a: ~QQ
zz
llii a:
~I@ I~ ffi I~I@
a:
35[
34[
33[
32[
1I02l J18
31[
19 20 21 22 23 24 25 26 27 28 29 30
OEL
AOl
All
A2l
A3l
A4l
ASl
ASl
N/C
A7l
ASl
A9l
N/C
I/OOl
I/Oll
I/02l
AOA
A1R
A2A
A3A
A4A
ASA
ASA
A7A
ASA
ASA
N/C
1I07A
I/OSA
tD_
IDT7130/40
PN64-1
64-PIN TQFP
TOP VIEW (1)
OEA
AOR
AlA
A2R
A3R
A4A
ASA
ASA
N/C
A7R
ASR
A9A
N/C
N/C
I/07A
I/OSA
nnnnnnnnnnnn
~ ~ ~ ~ ~
c
~ ~ ~ ~ ~
ffi
~Q~~~~QCC8~N~Q"1()
2689 drw 03
~~~~~8~~~~~~
~z~~~~zt§t§:::=~~~z~~
NOTE:
1. This text does not indicate orientation of the actual part-marking.
6.01
2
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM SK (1 K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED
DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
Operating
Temperature
o to +70
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
TA
-55 to +125
Symbol
°C
Min.
Typ.
Max.
Vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6.0(2)
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
Unit
NOTE:
1. VIL (min.) ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
2689 tbl 02
2689 tbl 01
NOTE:
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 1Ons maximum, and is limited to!>. 20mA for the period of VTERM ~ Vcc
+0.5V.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Ambient
Temperature
GND
Vee
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
Commercial
2689 tbl 03
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vce =5.0V ± 10%)
7130SA
Svmbol
Parameter
7130LA
7140SA
Min.
Max.
Test Conditions
7140LA
Max.
Max.
Unit
-
10
-
5
~
Vee = 5.5V,
CE = VIH, Your = OV to Vee
-
10
-
5
Il A
Output Low Voltage
(1/00-1/07)
IOL=4mA
-
0.4
-
0.4
V
VOL
Open Drain Output
Low Voltage (BUSY INl)
IOL = 16mA
-
0.5
-
0.5
V
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-
IILlI
Input Leakage
Current(1)
Vee =5.5V,
VIN = OV to Vee
IILOI
Output Leakage
Current(1)
VOL
I
NOTES:
1. At Vcc<2.0V leakages are undefined.
CAPACITANCE
(TA
V
2689tbl04
= +25°C, f = 1.0MHz) TQFP Package Only
2689 tbl 05
NOTE:
1. This parameter is determined by device characterization but is not production tested.
2. 3dv references the interpolated capacitance when the input and output signals switch from OV to
3V or from 3V to OV.
6.01
3
IDT7130SAILA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (Vcc = s.OV ± 10%)
7130X20(2) 7130X25(3)
7140X25(3)
Symbol
Parameter
lee
Dynamic Operating
Current (Both Ports
Active)
7130X35 7130X55
7130X100
7140X35 7140X55
7140X100
Typ. Max. Typ. Max. Typ. Max. Typ.Max. Typ. Max. Unit
Version
Test Conditions
=
SA
CEL and CER VIL, MIL.
LA
Outputs open,
f fMAX(4)
COM'L. SA
=
LA
ISS1
ISS2
ISS3
Iss4
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports - All
CMOS Level Inputs
Full Standby Current
(One Port - All
CMOS Level Inputs)
=VIH,
-
-
110
110
250
200
-
-
280
220
220
170
80
80
80
80
230
170
165
120
65
65
65
65
190
140
155
110
65
65
65
65
190
140
155
110
mA
80
60
65
45
25
25
25
25
80
60
65
45
20
20
20
20
65
45
65
35
20
20
20
20
65
45
55
35
mA
mA
LA
30
30
65
45
30
30
30
30
SA
-
-
65
160
50
150
40
125
-
-
Active Port Outputs COM'L. SA
Open, f fMAX(4)
LA
65
65
165
125
65
65
65
125
150
115
50
50
50
115
125
90
40
40
40
90
110
75
40
40
40
40
125
LA
CEL and
CER ~ Vee -0.2V,
VIN ~ Vee -0.2V or
VIN!:: 0.2V,f 0(5)
-
15
5
30
10
15
5
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
mA
1.0
0.2
1.0
0.2
1.0
0.2
-
155
115
155
115
145
105
45
45
45
45
145
105
110
85
40
40
40
40
110
85
100
70
40
40
40
40
110
80
95
70
mA
60
60
60
60
60
60
CEL and CER
f fMAX(4)
=
MiL.
SA
110
110
110
110
-
LA
COM'L. SA
CE·A· =VIL and
CE"s· =VIH (7)
MIL.
=
=
MIL.
SA
LA
COM'L. SA
LA
CE"A" !:: O.2V and
MIL.
CE·s" ~ Vee -0.2V(7)
VIN ~ Vee -0.2V or COM'L.
VIN !::0.2V,
Active Port Outputs
Open, f fMAX(4)
SA
LA
SA
LA
-
90
110
75
=
NOTES:
2689 tbl 06
1.
2.
3.
4.
'X' in part numbers indicates power rating (SA or LA).
Com'l Only, O°C to +70°C temperature range. PLCC package only.
Not available in DIP packages ..
Atf =fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using· AC TEST CONDITIONS·
of input levels of GND to 3V.
5. f =0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc =5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
VDR
Vee for Data Retention
leeDR
Data Retention Current
teDR(3)
Chip Deselect to Data
lMil.
Vee
Retention Time
tR(3)
IDT7130LAIIDT7140LA
Typ.(1)
Min.
Max.
Test Conditions
Parameter
=2.0V, CE~ Vee -0.2V I Com'l.
VIN ~ Vee -0.2V or VIN !:: 0.2V
-
-
100
4000
IlA
100
1500
0
-
-
IlA
ns
-
-
ns
tRc!2)
Operation Recovery
-
Unit
2.0
V
Time
2689 tbl 07
NOTES:
1. Vcc = 2V, TA =+25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
6.01
4
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1 K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
VOR2:2.0V
4.5V
tCOR
d
,~______
V_O_R____-J/
'~H
tRb
~H
2692 dlW 06
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1, 2, and 3
2689tbl08
t
;(
DATAoUT
1250Q
12500
Tt
DATA OUT .......----+--....
7750
7750 Y 3 0 PF*
(*1 OOpF for 55 and
100ns versions)
Figure 1. Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, twz, and tow)
* including scope and jig
;t
"
~
270Q
BUSYOrIN~
I
- 30pF*
·'OOpF for 55 and 'OOns versions
2689 dlW 07
Figure 3. BUSY and INT
AC Output Test Load
6.01
5
IDT7130SA/lA AND IDT7140SAILA
CMOS DUAL-PORT RAM 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
7130X20(2) 7130X25(5)
7140X25(5)
Symbol
Parameter
Min. Max.
Read Cycle
tRC
Read Cvcle Time
tAA
Address Access Time
tACE
Chio Enable Access Time
tAOE
Outout Enable Access Time
tOH
Output Hold From Address Change
Output Low-Z Time(l,4/
tLZ
Output High-Z Time(l,4)
tHZ
tpu
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
tPD
20
3
0
0
-
20
20
11
10
20
7130X35
7140X35
7130X55
7140X55
7130X100
7140X100
Min. Max. Min. Max. Min. Max. Min.
-
25
-
-
25
25
12
-
3
0
-
-
35
35
20
-
3
0
-
-
10
-
15
-
0
-
0
-
0
-
25
-
35
-
35
55
NOTES:
1. Transition is measured ±SOOmV from Low or High impedance voltage Output Test Load (Figure 2).
2. Com'l Only, O°C to +70°C temperature range. PLCC package only.
3. "X" in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
-
-
100
Max. Unit
-
55
55
25
-
100
100
40
3
-
5
-
10
5
-
25
-
40
-
0
-
50
-
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689tbl09
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE{l)
~
..
ADDRESS
tRC----..%;
tAA -----~
----
DATAoUT
-t-O-H------------
tOH
DATA VALID
---------------~~~~
BUSyOUT----------~~~_r~~~~~------------------------------------------------tBDDH
(2,3)
2669 drw 06
NOTES:
1. RJlN = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE
transition Low.
2. tBDD delay is required only in case where the opposite is port is completing a write operation to
same the address location. For simultanious read operations BUSY has no relationship to valid
output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.01
6
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM SK (1 K x S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(3)
lACE
~l
~r-
CE
(4)
tHZ(2)
IAOE
f
~r
OE
(1)
tHZ(~
tLZ
-. ... L /_ ...
DATAoUT
VALID DATA
-r\ \-'r
tLZ(l)
-tpu
Icc
tPO(4)
!~
4
~- 50%
-,f-
50%~
_ _ _ __
CURRENT ________________
Iss
2689 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is deaserted first, OE or CEo
3. RiW = VIH, and the address is valid prior to other coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBOO.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
7130X20(2) 7130X25(6)
7140X25(6)
Symbol
Parameter
Write Cycle
Write Cycle Time(:$)
twc
Min.
Max.
Min. Max.
25
20
20
tEW
Chip Enable to End-ot-Write
tAW
Address Valid to End-ot-Write
tAS
twp
Address Set-up Time
Write Pulse Width(4)
15
tWR
Write Recovery Time
a
tow
10
tHZ
Data Valid to End-ot-Write
Output High-Z Time(1)
-
-
10
tOH
twz
Data Hold Time
Write Enabled to Output in High-Z(1)
a
-
a
20
15
15
a
7130X35
7140X35
Min.
35
30
30
12
-
-
10
-
a
-
10
-
10
-
a
-
a
a
a
15
a
a
25
a
15
Max.
7130X55
7140X55
Min.
Max.
Min.
100
90
90
-
20
-
15
-
25
55
40
40
a
30
a
7130X100
7140X100
Max.
Unit
ns
40
-
-
40
ns
a
55
a
ns
ns
ns
ns
ns
ns
-
a
-
a
-
ns
15
-
25
-
40
ns
-
a
-
a
-
Output Active From End-ot-Write(1)
tow
ns
NOTES:
2689 tbll0
1. Transition is measured ±500mV from Low or High impedance voltage with Output Test Load (Figure 2). This parameter guaranteed
device characterization but is not production tested.
2. O°C to +70°C temperature range only, PLCC package only.
3. For MASTER/SLAVE combination, twe =tBAA + twp, since Rm=VIL must occur after tBAA.
4. If OE is low during a Rm controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to tum off
data to be placed on the bus for the required tow. If OE is High during a Rm controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
5. "X" in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
6.01
7
IDT7130SAILA AND IDT7140SAILA
CMOS DUAL-PORT RAM 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (R/W CONTROLLED TIMING)(1,5,8)
ADDRESS
1+--_'tHZ....:..(7'-'-)_ _~
- + + - _ - - - - - - t W P · ( 2 ) - - - - - -...._
DATA OUT
14----tow---...._---tOH-----..,~
DATAIN-------------------------------K
2689 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)(1,5)
twc
ADDRESS
)K
~~
•
tAW
tAs$
f
tRC-----.l
INTERRUPT CLEAR ADDRESS
tAS(3)
'.
OE'B'
t-------tINR.:.:(3!...)---~~
INT'A'
2689 drw 17
NOTES:.
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.01
11
IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I. NON-CONTENTION
READIWRITE CONTROL(4)
Left or Right Port(1)
RIW
CE
DE
00-7
X
H
X
Z
Port Disabled and in PowerDown Mode, IS82 or IS84
X
H
X
Z
CER CEl VIH, Power-Down
Mode IS81 or IS83
L
L
X
H
L
L
H
L
H
Function
=
DATAIN
=
Data on Port Written Into Memory(2
DATAoUT Data in Memory Output on Port(3)
Z
High Impedance Outputs
NOTES:
2689 tbl 13
1. ADl - Al0l ADR - Al0R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tODD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE, 'Z' = HIGH IMPEDANCE
*
TABLE II. INTERRUPT FLAG(1,4)
Left Port
Right Port
RlWl
CEL
OEl
A9l-Aol
INTl
RIWR
CER
OER
A9l-AoR
L
L
3FF
X
INTR
L(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
3FF
H(3)
L(3)
L
L
3FE
L
L
3FE
H(2)
X
X
X
X
X
X
NOTES:
1. Assumes BUSYl = BUSYR =VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR =VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON'T CARE
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTl Flag
Reset Left INTl Flag
2689 tbl14
TABLE 11- ADDRESS BUSY ARBITRATION
Inputs
Outputs
CEl
CER
AOl-A9l
AOR-A9R
BUSYl(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write.lnhibit\;j}
Function
2689tbl15
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for IDT7140 (slave). BUSYx outputs on the IDT7130 are open drain, not
push-pull outputs. On slaves the BUSYx input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving Low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving Low regardless of actual logic level on the pin.
6.01
12
ID17130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAM 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT71301lDT7140 provides two ports with separate control, address and I/O pins that permit independent access for
reads or writes to any location in memory. The IDT7130/
IDT7140 has an automatic power down feature controlled by
CEo The CE controls on-chip power down circuitry that permits
the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the
entire memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (INTL) is asserted when the
right port writes to memory location 3FE (HEX), where a write
is defined as the CE = Rm = VIL per the Truth Table. The left
port clears the interrupt by access address location FFE
access when CER = OER =VIL. RiW is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port
writes to memory location 3FF (HEX) and to clear the interrupt
flag (INTR), the right port must access the memory location
3FF. The message (8 bits) at 3FE or 3FF is user-defined,
since it is an addressable SRAM location. If the interrupt
function is not used, address locations 3FE and 3FF are not
used as mail boxes, but as part of the random access
memory. Refer to Table I for the interrupt operation.
The Busy outputs on the IDT7130 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy
pin is an output if the part is Master (IDT7031), and the Busy
pin is an input if the part is a Slave (IDT7140) as shown in
Figure 3.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is "Busy". The Busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the BUSY pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the BUSY pins High. If desired, unintended write
operations can be prevented to a port by tying the Busy pin for
that port Low.
6.01
2S89drw19
Figure 3. Busy and chip enable routing for both width and depth
expansion with ID17030 (Master) and ID17140 (Slave)RAMs.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the Rm signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
13
IDT7130SAILA AND IDT7140SAILA
CMOS DUAL-PORT RAM 8K (1 K x 8-em
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT _...:..:X::..;X::....:.XX:...:....-___A_
Device Type Power
~
_A
__
A
Speed
Package
Process/
Temperature
Range
Y
BLANK Commercial (O°C to +70°C)
B
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
C
J
~----------~ L48
F
PF
~----------------~
~
20
25
35
55
100
__________________~ILA
I SA
~----------------------------~
7130
7140
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
64-pin TQFP (PN64-1)
Commercial PLCC Only }
Speed in nanoseconds
Low Power
Standard Power
aK (1 K x a-Bit) MASTER Dual-Port RAM
8K (1K x a-Bit) SLAVE Dual-Port RAM
2689 drw 19
6.01
14
'~5
IDT7132SAlLA
IDT7142SAlLA
CMOS DUAL-PORT RAM
16K (2K x a-BIT)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 25/35/55/1 OOns (max.)
- Commercial: 25/35/55/100ns (max.)
- Commercial: 20ns only in PLCC for 7132
• Low-power operation
- IDT7132/42SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
- IDT7132142LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• MASTER IDT7132 easily expands data bus width to 16-ormore bits using SLAVE IDT7142
• On-chip port arbitration logic (IDT7132 only)
• BUSY output flag on IDT7132; BUSY input on IDT7142
• Battery backup operation -2V data retention
• TIL-compatible, single 5V ±1 0% power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD, Class B
• Standard Military Drawing # 5962-87002
• Industrial temperature range (-40°C to +85°C) is available,
tested to miliary electrical specifications
The IDT71321IDT7142 are high-speed 2K x 8 Dual-Port
Static RAMs. The IDT7132 is designed to be used as a standalone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM
together with the IDT714? "SLAVE" Dual-Port in 16-bit-ormore word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous access for reads orwrites to any location in memory.
An automatic power down feature, controlled by CE permits
the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each Dual-Port typically consuming 200llW
from a 2V battery.
The IDT713217142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and
48-lead flatpacks. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
,
OEl
GEL
R/Wl
r\.
--...I
1I
1
f--
1/0
Control
1,2)
AOl
·
NOTES:
1. IDT7132 (MASTER): BUSY is open
drain output and requires pullup
resistor.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor.
I
A
~
'I
"
I/OOR-I/07R
L......a.
~
'lr
1/0
Control
+
MEMORY
ARRAY
11
BUSYR (1.2)
A
~
'I
"
,
11
ARBITRATION
LOGIC
GEL:
OEl:
Address
Decoder
··
A10R
AOR
I
GER
'OER
IR/WR
R/Wl •
f
The lOT logo Is a registered trademark of Integrated Device Technology, Inc.
t
2692 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1995 Integrated Device Technology, Inc.
A
t
Address
Decoder
i
~.
)j
I/OOl- 1/07l
A10l
J
[
]
6.02
APRIL 1995
DSC-1001/4
1
IDT7132SAILA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGUARATIONS
CEl
RlfiJl
1
2
BUSYl
3
A10l
4
5
6
OEl
AOl
A1l
A2l
A3l
A4L
ASL
ASL
A7L
ASL
A9L
I/OOL
I/01L
I/02L
I/03L
I/04L
I/OSL
I/OSL
I/07L
VCC
CER
RIfiJR
~ I~ 1~led
5 led
u
8
5 ~ ~ 5 ~ 8 ~ ~ ~ $ ffi
::::'::::'::::'::::'::::'CJ::::.gggg~
AOA
AlA
A2A
A3A
A4A
ASA
ASA
AlA
ASA
A9A
N/C
I/07A
I/OSA
2692 drw 03
NOTE:
1. This text does not indicate orientation of the actual part-marking.
2692 drw02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
I~
~ I~ ~ ~ ~ I~I~
INDEX
J8
J9
J10
J 11
J12
J13
J14
J 15
J16
J17
J18
J19
J20
Military
Commercial
-55°C to +125°C
O°C to +70°C
Vee
OV
OV
5.0V± 10%
5.0V± 10%
2692 Ibl 02
5 4
OEA
AOR
A1R
A2R
A3R
A4R
ASR
ASR
A7R
ASR
A9R
N/C
I/07A
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
GND
3 2 •• 52 51 50 49 48 47
1
46[
45[
44[
43[
IOT7130/40
42[
J52-1
41[
52-PIN PLCC
40[
TOP VIEW (1)
39[
38[
37[
36[
35[
34[
21 2223 2425 2627 2829 3031 3233
nnnnnnnnnnnnn
7 6
All
A2l
A3L
A4l
ASL
A6l
A7L
ASL
A9L
I/OOl
I/Oll
I/02l
I/03L
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
~I~ I~I~ ~!
L..I L..I L..I L..I L..I L..II I L..I L..I L..I L..I L..I L..I
NOTE:
2692 Ibl 01
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
abov~ those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTEAM must not exceed Vcc + O.SV for more than 2S% of the cycle time
or 1Ons maximum, and is limited to!> 20m A forthe period of VTERM ~ Vcc
+0.5V.
Grade
II:
-J
Min.
Typ.
Max.
Vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
V
VIH
Input High Voltage
0
6.0(2)
VIL
Inout Low Voltage
2.2
-0.5(1)
NOTE:
1. VIL (min.) -1.5V for pulse width less than 10ns.
2. VTEAM must not exceed Vcc + 0.5V.
-
0.8
Unit
V
V
2692 Ibl 03
=
6.02
2
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (Vcc =S.OV ± 10%)
7132X20(2) 7132X25(3)
7142X25(3)
Symbol
Parameter
lee
Dynamic Operating
Current (Both Ports
Active)
ISBl
Standby Current
(Both Ports - TIL
Level Inputs)
Test Conditions
Version
-
-
LA
110
110
250
200
SA
-
-
LA
-
-
30
30
65
45
-
-
65
65
165
125
-
-
-
1.0
0.2
15
5
-
-
60
60
155
115
CEl and CER = Vll, MIL.
SA
Outputs open,
LA
f = fMAX(4)
COM'L. SA
CEl and CER =-VIH, MIL.
f = fMAX(4)
COM'L. SA
LA
ISB2
18B3
18B4
Standby Current
(One Port- TIL
Level Inputs)
Full Standby Current
(Both Ports - All
CMOS Level Inputs
Full Standby Current
(One Port - All
CMOS Level Inputs)
MIL.
CE'A" = Vil and
CE'B' = VIH (7)
Active Port Outputs COM'L.
Open, f = fMAX(4)
CEl and
CER ~ Vee -0.2V,
VIN ~ Vee -0.2V or
VIN s 0.2V,f = 0(5)
SA
LA
SA
LA
MIL.
SA
LA
COM'L. SA
MIL.
CE'A' S O.2V and
CE'B' ~ Vee -0.2V(7)
VIN ~ Vee -0.2V or COM'L.
VIN S 0.2V,
Active Port Outputs
Open, f = fMAX(4)
7132X35 7132X55
7132X100
7142X35 7142X55
7142X100
Typ. Max. Typ. Max. Typ. Max. Typ.Max. Typ. Max. Unit
LA
SA
LA
SA
LA
110
110
110
110
280
220
220
170
80
80
80
80
230
170
165
120
65
65
65
65
190
140
155
110
65
65
65
65
190
140
155
110
mA
30
30
30
30
80
60
65
45
25
25
25
25
80
60
65
45
20
20
20
20
65
45
65
35
20
20
20
20
65
45
55
35
mA
65
65
65
65
160
125
150
115
50
50
50
50
150
115
125
90
40
40
40
40
125
90
110
75
40
40
40
40
125
90
110
75
mA
1.0
0.2
1.0
0.2
30
10
15
5
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
mA
60
60
60
60
155
115
145
105
45
45
45
45
145
105
110
85
40
40
40
40
110
85
100
70
40
40
40
40
110
80
95
70
mA
2689 tbl 04
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, O°C to +70°C temperature range. PLCC package only.
3. Not available in DIP packages ..
4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC TEST CONDITIONS'
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC =S.OV ± 10%)
7132LA
7132SA
Symbol
Ilul
Parameter
7142SA
Min.
Max.
Test Conditions
7142LA
Max.
Max.
Unit
-
10
-
5
flA
Vee = 5.5V,
CE = VIH, VOUT = OV to Vee
-
10
-
5
flA
IOl= 4mA
-
0.4
-
0.4
V
Input Leakage
Current(l)
Vee = 5.5V,
IIl01
Output Leakage
Current(l)
VOL
Output Low Voltage
VIN = OV to Vee
(1/00-1/07)
VOL
Open Drain Output
Low Voltage (BUSY INTI
10L = 16mA
-
0.5
-
0.5
V
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-
V
NOTES:
1. At Vcc<2.0V leakages are undefined.
2689 tbl 05
6.02
3
IDT7132SAILA AND IDT7142SAILA
CMOS DUAL-PORT RAM 16K {2K x a-BIT}
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
Parameter
VDR
Vcc for Data Retention
ICCDR
Data Retention Current
Vcc =2.0V, CE ~ Vcc -0.2V
VIN
tCDR(3)
tR I"!
IDT7132LAnDT7142LA
Min.
Typ.
Max.
Test Conditions
~
IMil.
Vcc -0.2V or VIN :5 0.2V
I Com'l,
V
100
4000
100
1500
IlA
IlA
-
0
Chip Deselect to Data
Retention Time
tRC l:.!)
Operation Recovery
Unit
-
2.0
-
-
ns
-
-
ns
Time
NOTES:
1. Vcc 2V, TA +25°C, and is not production tested.
2. tAC Read Cycle Time
3. This parameter is guaranteed but not production tested.
=
=
26921b106
=
AC TEST CONDITIONS
DATA RETENTION WAVEFORM
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA RETENTION MODE
Vcc
4.5V
d
VDR~2.0V
tCDR
,~______
V_DR____--J/
V~
GNDTO 3.0V
5ns
1.5V
1.5V
See Figures 1, 2, & 3
tR~
2692 tbl 07
V~
2692 drw 05
5V
12500
12500
DATA OUT
DATA OUT
7750
30pF*
- - - - - - . -....
7750
5pF*
100pF for 55 and 100ns versions
Figure 1. Output Test
~I,
Figure 2. Output Test Load
{for tHZ, tLl, twz, and tow}
• Including scope and jig
2700
BUSY or INT
2692 drw 06
30pF*
DOOF
'0' 55 and' OOns .....on.
Figure 3. Busy AC Output TestLoad
{IDT7132 only}
6.02
4
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
7132X20(2) 7132X25(5)
7142X25(5)
Symbol
Min. Max.
Parameter
7132X35
7142X35
Min. Max. Min.
7132X55
7142X55
7132X100
7142X100
Max. Min. Max Min.
Max. Unit
Read Cycle
tRC
Read Cvcle Time
20
tAA
Address Access Time
tACE
Chip Enable Access Time
-
tAOE
Output Enable Access Time
tOH
Output Hold From Address Change
tLZ
Output Low-Z Time(1,4)
tHZ
Output High-Z Time(1,4)
-
tpu
Chip Enable to Power Up Time(4)
0
tPD
Chip Disable to Power Down Time(4)
-
3
0
-
25
20
20
11
-
-
3
0
10
20
0
-
-
35
-
-
35
35
20
-
3
0
-
10
25
-
-
15
-
0
-
35
NOTES:
1. Transition is measured ±SOOmV from Low or High impedance voltage Output Test Load (Figure 2).
2. Com'l Only, O°C to +70°C temperature range. PLCC package only.
3. "X" in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
TIMING
-
25
25
12
55
3
5
0
-
-
100
-
-
100
100
40
-
10
5
-
ns
25
-
40
ns
0
-
ns
-
50
ns
55
55
25
-
50
-
ns
ns
ns
ns
ns
2689 tbl 08
WAVEF~~F READ CYCL~R~O.1, EITHER SIDE(1t;)
ADDRESS
---
tAA
-t-O-H-------------
tOH
DATAoUT
_____________
DATA VALID
~~~~I~-------------------J~~~~~~~~~~
BUSyOUT--------~~~~~~~r+----~-----------------------------------------
tBDDH
NOTES:
=
=
(2,3)
2692 drw 07
=
1. RIW VIH, CE VIL, and is OE VIL. Address is valid prior to the coincidental with CE transition Low.
2. tBDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultanious read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.02
5
IDT7132SAlLA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE,3)
tACE
~r
CE
.,~
~
J
tAOE
tHZ(2)
(4)
I
~ ....
OE
-l-
\
tLZ
-:'-//-:'-' .... \ \-'r-
DATAoUT
tLZ
tHZ(~
(1)
VALID DATA
'.
(1)
4
I4-tpu
Icc
CURRENT _ _ _ _ _ _ _ _ _
-1l50%
.,~
tPO(4)
50%~
Iss
_ _ _ __
2692 drwOS
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal Is deaserted first, OE or CEo
3. RfiJ VIH, and the address Is valid prior to other coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBOO.
=
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
7132X20(2)
Symbol
Parameter
Write Cycle
Write Cycle Time''>}
twc
Chip Enable to End of Write
tEW
Address Valid to End of Write
tAW
Address Set-up Time
tAS
twp
Write Pulse Width\4)
Write Recovery Time
tWR
tow
uata valla to t:no ot wnte
Output High Z Time"}
tHZ
LJata HOIO Time
tOH
Write Enabled to Output in High Z")
twz
Output Active From End of Write(1)
tow
Min.
20
15
15
0
15
0
7132X25(6)
7142X25(6)
Max. Min. Max.
-
25
20
20
0
15
0
-
-
-
1U
-
10
-
0
10
-
0
-
0
7132X55
7142X35
Min. Max.
7142X55
Min. Max.
35
30
30
0
25
0
-
10
1~
-
u
-
7132X35
10
10
-
0
0
55
40
40
0
30
0
-
-
-
15
15
-
u
0
7142X100
Min. Max.
100
90
90
0
-
55
-
0
-
-
4U
~U
-
7132X100
25
30
-
u
0
40
40
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2692 Ibl 09
NOTES:
1. Transition is measured ±500mV from Low or High impedance voltage with Output Test Load (Figure 2). This parameter guaranteed
device characterization but is not production tested.
2. O°C to +70°C temperature range only, PLCC package only.
3. For Master/Slave combination, twc tBM + twP, since pJijj VIL must occur after tBM.
4. If OE is low during a RfiJ controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to tum off
data to be placed on the bus for the required tow. If OE is High during a pJijj controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
5. "X' in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
=
=
CAPACITANCE
,
,
,Symbol,
CIN
COUT
,
,
(TA = +25°C,f = 1.0MHz)
Parameter (1)
Conditions
Input Capacitance
VIN= OV
Output Capacitance
VIN= OV
NOTE:
1. This parameter is sampled and not 100% tested.
Max.
11
11
Unit,
pF ,
pF ,
26921bll0
6.02
6
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (R/W CONTROLLED TIMING)(1,5,8))
ADDRESS
1.----tHz (7)
-+f.oIt--------twp·(2) --------i~-
Rm
DATA OUT
..----tow----t-t_---tOH----i~
DATAIN
------------------1<
2692 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)(1,5)
ADDRESS
twc
=>K
....... /
/~
tAW
lAS'"
Rm
J
1
/
tEW(2)
tWR(3)-
tow
I.
DATA IN
I
/
tOH
J
/I
2692 drw 11
NOTES:
1. RiW or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or twp) of CE = VIL and RlW= VIL
3. tWR is measured from the earlier of CE or
going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the RNJ Low transition, the outputs remain in the High impedance state.
6. Timing depends on which enable signal (CE or RiW) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off
data to be placed on the bus for the required tow. If OE is High during a RNJ controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
Rm
6.02
7
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)
7132X20(1)
Svmbol
Parameter
Min. Max.
7132X25(9)
7132X35
7132X55
7132X100
7142X25(9)
7142X35
7142X55
7142X100
Min.
Max.
Max.
Min.
Min. Max. Min.
Max.
Unit
50
ns
50
ns
50
ns
Busy Timing (For Master IDT7130 Only)
-
20
20
-
20
50
-
20
-
30
20
20
30
20
20
30
20
20
30
-
50
ns
-
50
-
-
-
-
-
-
80
120
ns
55
-
100
ns
-
5
-
ns
55
-
100
ns
-
0
-
ns
20
120
ns
100
ns
tBAA
BUSY Access Time from Address
tBDA
BUSY Disable Time from Address
tBAC
BUSY Access Time from Chip Enable
tBDe
BUSY Disable Time from ChiD Enable
tWDD
Write Pulse to Data Delav(2)
tDDD
Write Data Valid to Read Data Delav(2)
tAPS
Arbitration Prioritv_Set-up_ Time(3)
5
-
5
-
5
-
tBDD
BUSY Disable to Valid Data(4)
-
20
-
25
-
35
-
0
-
0
15
20
-
20
20
20
35
35
60
35
5
Busy Timing (For Slave IDT7140 Only)
tWB
Write to BUSY Input(5)
0
tWH
Write Hold After BUSy(6)
12
-
tWDD
Write Pulse to Data Delay(2)
-
40
tDDD
Write Data Valid to Read Data Delay(2)
-
30
-
-
50
35
60
35
0
-
80
55
-
ns
2689 tblll
NOTES:
1.Com'l Only, O°C to +70°C temperature range. PLCC package only.
2.
3.
4.
5.
6.
7.
8.
Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port -to-Port Read and BUSY.
To ensure that the earlier of the two ports wins.
teoo is a calculated parameter and is the greater of 0, twoo - twp (actual) or tODD - tow (actual).
To ensure that a write cycle is inhibited on port 'B' during contention on port 'A' ..
To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
·X" in part numbers indicates power rating (S or L).
Not available in DIP package
___ (1,2,3,6)
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY
twc
ADDR'A
)(
)(
MATCH
twp
RNI'A'
~,
V
/
~H
tDW
)(
DATAIN'A'
VALID
-~P9E;
ADDR'B'
MATCH
)
BUSY'B'
tBDA--'
\~
tBDD~
tWDD
)K
DATAourB'
VALID
LDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
2. eEt. = CER = VIL
3. OE = VIL for the reading port.
4. Alltiming is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is opposite from port "A".
6.02
2692 drw 12
8
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSVC3)
twp
BUSYR
(2)
NOTES:
1. tBDD must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'S' goes High.
3. A" timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is oppsite from port "A".
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CETIMING
ADDR
'A' AND 'B'
(1)
~_____________________A_D_D_R_E_S_S_E_S_M_A_T_C_H______________________~
BUSY'A'
2692 drw 13
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING
~-----·tRC
ADDR'A'
OR
(1)
tW()-----~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR'B'
BUSY'B'
~~~~~~~_tB_D_A~~~~~:}~
tBAA=t'--_ _ _ _ _
_--------2692 drw 15
NOTES:
1. A" timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7032 only).
6.02
9
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I. NON-CONTENTION
READIWRITE CONTROL(4)
Left or Right Port(1)
Function
RIW
CE
OE
00-7
X
H
X
Z
Port Disabled and in PowerDown Mode, 1582 or 1584
X
H
X
Z
GER GEL VIH, Power-Down
Mode 1581 or 1583
L
L
X
H
L
L
H
L
H
DATAIN
=
=
Data on Port Written Into Memory(2
DATAoUT Data in Memory Output on Port(3)
Z
High Impedance Outputs
NOTES:
1. AOL- Al0L;c AOR - Al0R.
2. If BUSY L, data is not written.
3. If BUSY L, data may not be valid, see twoo and toDD timing.
4. 'H' = VIH, 'L' =VIL, 'X' DON'T CARE, 'Z' HIGH IMPEDANCE
=
=
=
2654tbl12
=
TABLE II. INTERRUPT FLAG(1,4)
Left Port
Right Port
RIWL
GEL
OEL
A10L- AOL
INTL
RIWR
GER
OER
A10L-AoR
L
L
7FF
X
INTR
L(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
7FF
H(3)
L(3)
L
L
7FE
L
L
7FE
H(2)
X
X
X
X
X
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL =VIL, then No Change.
3. If BUSYR VIL, then No Change.
4. 'H' = HIGH,' L' =LOW,' X' =DON'T CARE
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2654 tbl13
=
TABLE 111- ADDRESS BUSY ARBITRATION
Outputs
Inputs
GEL
CER
AOL-A10L
AOR-A10R
BUSYL(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
L
L
MATCH
(2)
(2)
Function
Normal
Write Inhibit(3)
2654 tbl13
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for IDT7140 (slave). BUSYx outputs on the IDT7130 are open drain, not
push-pull outputs. On slaves the BUSYx input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR Low will result. BUSYL and BUSYR outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving Low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving Low regardless of actual logic level on the pin.
=
6.02
10
IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT7132/IDT7142 provides two ports with separate
control, address and 1/0 pins that permit independent access
for reads or writes to any location in memory. The IDT7132/
I DT7142 has an automatic power down feature controlled by
CEo The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (CE= VIL). When a port is enabled, access to the
entire memory array is permitted.
BUSY LOGIC
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/lDT7140 RA~ the busy
pin is an output if the part is used as a master (MIS pin::. H),
and the busy pin is an input if the part used as a slave (MIS pin
=L) as shown in Figure 3.
LEFT
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is "busy". The busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the BUSY pins high.
If desired, unintended write operations can be prevented to
a port by tying the busy pin for that port low.
The busy outputs on the IDT7132/1DT7142 RAM in master
mode, are push-pull type outputs and do not require pull up
resistors to operate. If these RAMs are being expanded in
depth, then the busy indication forthe resulting array requires
the use of an external AND gate.
RIGHT
RiW-o------+I RiW
1DT7132
MASTER
......_--_----1
BUSY I---~t--- BUSY
lUSY -1---...---1 BUSY
+5V
' - t - - - I RiW
+5V
IDT7142
SLAVE (1)
RJW I----f--J
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7032 (Master) and (Slave) IDT7142 RAMs.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a masterlslave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the Rm signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
6.02
11
IDT7132SAILA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
IDT
xxxx
_A_
Device Type Power
~
Speed
MILITARY AND COMMERCIAL TEMPERATURE RANGES
_A
__
Package
A
Process!
Temperature
Range
Y:LANK
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP (P48-1)
Sidebraze DIP (C4'8-2)
PLCC (J52-1)
LCC (L48-1)
Ceramic Flatpack (F48-1)
P
C
48-pin
48-pin
52-pin
48-pin
48-pin
20
25
Commercial PLCC onlY}
'--------IJ
L48
F
L----------------~35
Speed in nanoseconds
55
100
ILA
~--------------------~ISA
'--_________________________
~7132
7142
Low Power
Standard Power
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
2692 drw 16
6.02
12
~'5
IDT71321SAlLA
IDT71421SAlLA
CMOS DUAL-PORT RAM
16K (2K x a-BIT)
WITH INTERRUPTS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
-Commercial: 20/25/35/45/55ns (max.)
The IDT7132111DT71421 are high-speed 2K x a DualPort Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used
as a stand-alone a-bit Dual-Port RAM or as a "MASTER"
Dual-Port RAM together with the I DT71421 "SLAVE" DualPort in 16-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-or-morebit memory system applications results in full speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consuming 200llW from a 2V battery.
The IDT71321I1DT71421 devices are packaged in 52-pin
PLCCs and 64-pin TQFPs.
• Low-power operation
-IDT7132111DT71421 SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
-IDT71321/421LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
• Two INT flags for port-to-port communications
• MASTER IDT71321 easily expands data bus width to 16or-more-bits using SLAVE IDT71421
• On-chip port arbitration logic (IDT71321 only)
• BUSY output flag on IDT71321; BUSY input on IDT71421
• Fully asynchronous operation from either port
• Battery backup operation -2V data retention (LA Only)
• TTL-compatible, single 5V ±1 0% power supply
• Available in popular hermetic and plastic packages
FUNCTIONAL BLOCK DIAGRAM
-
'\
1I
I-
liD
Control
1,2)
AOl
.
A
Address
Decoder
I
NOTES:
1. IDT71321 (MASTER): BUSY
is open drain output and
requires pullup resistor.
IDT71421 (SLAVE): BUSYis in put.
2. Open drain output: requires pu lIup
resistor.
A
"-
"
v
"
I/00R-I/07R
liD
Control
--.
BUSYR (1,2)
A
MEMORY
ARRAY
-II
'f
11
11
ARBITRATION
and
INTERRUPT
LOGIC
CEl,
OEL.-
RIWL.
t
2)
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
Address
Decoder
··
Al0R
AOR
I
-,;CER
--:OER
-,;R!WR
-f
I
I
INTR(2)
2691 drw 01
APRIL 1995
COMMERCIAL TEMPERATURE RANGES
«:11995 Integrated Device Technology, Inc.
L.-
~r
f
1
~
)j
I/00l- 1/07l
Al0 l
I
[
]
1
I
\
-.-1
6.03
DSC-1031/4
1
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
L.J L.J L.J L.J L.J L.J
I I L.J L.J L.J L.J L.J L.J
5251 504948 4J6[
OER
J9
45[
AOR
J10
44[
A1R
J11
43[
A2R
J12
42[
A3R
41[
A4R
40[
ASR
39[
A6R
38[
A7R
J87 6
5 4
3 2
L J
1
IDT71321/421
J52-1
J13
J14
J15
PLCC(1)
J16
TOP VIEW
J17
37[
ABR
J18
36[
A9R
J19
35[
NC
J2~1
22 23 24 25 26 27 28 29 30 31 32 3~4[
nnnnnnnnnnnnn
OER
AOR
A1R
A2R
A3R
A4R
ASR
A6R
IDT71321/421
PN64-1
64-PIN TQFP
TOP VIEW (1)
N/C
A7R
ABR
A9R
N/C
N/C
I/07R
I/0 6R
I/07R
NOTES:
1. This text does not indicate orientation of the actual part-marking.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Commercial
Unit
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
°C
TSIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output
Current
50
mA
VTERM(2)
Rating
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Vee
Commercial
O°C to +70°C
OV
5.0V± 10%
2691 tbl02
RECOMMENDED
DC OPERATING CONDITIONS
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
V
VIH
Input High Voltage
2.2
0
6.0(2)
VIL
Input Low Voltage
-0.5(1
0.8
V
Symbol
2691 tblOl
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXI MUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 1Ons maximum, and is limited to ~ 20mA forthe period of VTERM ~ Vcc
+0.5V.
Parameter
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + 0.5V.
6.03
-
V
2691 tbl03
2
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (Vcc =S.OV ± 10%)
Symbol
Parameter
lee
Dynamic Operating
Current (Both Ports
Active)
71321X20(2) 171321X25(3) 71321X35 71321X55 71321X100
'1421X25(3) 71421X35 71421X55 71421X100
Version Typ. Max. Typ. Max. Typ. Max. Typ.Max. Typ. Max. Unit
Test Conditions
CEl and CER = Vll, MIL.
SA
Outputs open,
LA
f = fMAX(4)
COM'L. SA
LA
1561
Standby Current
(Both Ports - TTL
Level Inputs)
CEl and CER = VIH, MIL.
f = fMAX(4)
110
110
1583
1584
Standby Current
(One Port - TTL
Level Inputs)
-
30
30
65
45
SA
-
LA
-
-
SA
65
65
165
125
-
-
LA
1.0
0.2
15
5
SA
-
-
60
60
155
115
LA
COM'L. SA
Full Standby Current
(Both Ports - All
CMOS Level Inputs
Full Standby Current
(One Port - All
CMOS Level Inputs)
MIL.
CE'A' = Vil and
CE'6' = VIH (7)
Active Port Outputs COM'L.
Open, f = fMAX(4)
CEl and
CER?! Vee -0.2V,
VIN ?! Vee -0.2V or
VIN S 0.2V,f = 0(5)
MIL.
VIN ?! Vee -0.2V or
VINS 0.2V,
LA
SA
LA
COM'L. SA
MIL.
CE'A' S O.2V and
CE'8' ~ Vee -0.2V(7)
250
200
-
SA
LA
1562
-
LA
COM'L. SA
LA
110
110
110
110
280
220
220
170
80
80
80
80
230
170
165
120
65
65
65
65
190
140
155
110
65
65
65
65
190
140
155
110
mA
30
30
30
30
80
60
65
45
25
25
25
25
80
60
65
45
20
20
20
20
65
45
65
35
20
20
20
20
65
45
55
35
mA
65
65
65
65
160
125
150
115
50
50
50
50
150
115
125
90
40
40
40
40
125
90
110
75
40
40
40
40
125
90
110
75
mA
1.0
0.2
1.0
0.2
30
10
15
5
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
1.0
0.2
1.0
0.2
30
10
15
4
mA
60
60
60
60
155
115
145
105
45
45
45
45
145
105
110
85
40
40
40
40
110
85
100
70
40
40
40
40
110
80
95
70
mA
-
Active Port Outputs
Open, f =fMAX(4)
NOTES:
2689 tbl 04
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, O°C to +70°C temperature range. PLCC package only.
3. Not available in DIP packages ..
4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1ItRC, and using "AC TEST CONDITIONS"
of input levels of GND to 3V.
S. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = SV, TA=+2SoC for Typ and is not production tested. Vcc DC = 100mA (Typ)
7. Port "A" may be either left or right port. Port "8" is opposite from port "A".
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = S.OV +
- 10%)
Symbol
Parameter
IDT71321SA
IDT71421SA
Min.
Max.
Test Conditions
IDT71321LA
IDT71421LA
Min.
Max.
Unit
Ilul
Input Leakage
Current(l)
Vee = 5.5V,
VIN = OV to Vee
-
10
-
5
Il A
lila I
Output Leakage
Current(1)
CE = VIH, VOUT = OV to Vee
Vee = 5.5V
-
10
-
5
Il A
Val
Output Low Voltage
IOl= 4mA
-
0.4
-
0.4
V
10L = 16mA
-
0.5
-
0.5
V
IOH = -4mA
2.4
-
2.4
-
(1/00-1/07)
VOL
Open Drain Output Low
Voltaae (BUSY/INTI
VOH
Output Hiqh Voltaqe
V
2691 tbl05
NOTE: 1. At Vec < 2.0V leakages are undefined.
6.03
3
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (LA Version Only)
71321LAI71421LA
Symbol
Test Conditions
Parameter
VDR
VCC for Data Retention
ICCDR
tCDR(3)
Data Retention Current
VCC = 2.0V, CE ~ VCC - 0.2V
Chip Deselect to Data
VIN
~
VCC - 0.2V or
VIN~
I COM'L.
Min.
Typ.(1)
Max.
2.0
-
0
V
100
1500
Il A
-
0.2V
Unit
0
-
-
ns
tRC(2)
-
-
ns
Retention Time
tR(3)
Operation Recovery
Time
2691 tbl06
NOTES:
1. Vcc 2V, TA +25°C, and is not production tested.
2. tRC Read Cycle Time
3. This parameter is guaranteed but not production tested.
=
=
=
AC TEST CONDITIONS
DATA RETENTION WAVEFORM
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA RETENTION MODE
v: d~::f VD~::.OV ~~:b
~H
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2691 tbl07
~H
2691 drw 04
5V
12500.
12500.
DATA OUT
DATA OUT
7750.
_--4-_
7750.
5pF
1OOpF for 55 and 100ns versions
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, twz, and tow)
* Including scope and jig.
~2700
2691 drw05
BUSY or I N T - +
-30pF
l"PF
for 55 a.d 100••
'''.'0••
Figure 3. BUSY and INT
AC Output Test Load
6.03
4
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGfS
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
71321 X20(2) ~1321 X25(5) 71321X35 71321X55
71421 X25(5) 71421X35 71421X55
Symbol
Min. Max.
Parameter
Min. Max. Min.
71321X100
71421X100
Max. Min. Max. Min.
Max. Unit
Read Cycle
tRC
tAA
tACE
tAOE
tOH
tLZ
tHZ
tpu
tPD
Read Cvcle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time(1,4)
Output High-Z Time(l,4)
20
-
25
-
35
-
55
-
-
20
20
11
-
35
35
20
-
55
55
25
100
100
40
-
3
0
-
-
-
-
25
25
12
3
0
-
3
5
-
10
5
10
-
-
-
10
-
15
-
25
-
40
50
3
0
-
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
-
0
-
0
-
0
-
0
-
0
20
-
25
-
35
-
50
-
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE
..
tRC
~
DATAoUT
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbl 08
%;
(1)
~AA;
---
-
-
NOTES:
1. Transition is measured ±SOOmV from Low or High impedance voltage Output Test Load (Figure 2).
2. Com'l Only, O°C to +70°C temperature range. PLCC package only.
3. "X" in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
ADDRESS
100
-t-O-H------------
tOH
DATA VALID
---------~~~~I'--------------~
BUSyOUT-----~~~~~~~~~------------------------------
tBDDH
(2,3)
2691 drw 06
NOTES:
1. RIW VIH, CE VIL, and is OE VIL. Address is valid prior to the coincidental with CE
transition Low.
2. tBDD delay is required only in case where the opposite is port is completing a write operation to
same the address location. For simultanious read operations BUSY has no relationship to valid
output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
=
=
=
6.03
5
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE (3)
,-f\
tACE
-J
J
tHZ(2)
tAOE (4)
I
~(-
LtHZ
r\
(1)
tLZ
-.'-/ /-.'-'.-\ \-'.-
DATAoUT
tLZ
k-tPU
O
"---..
:-
VALID DATA
(1)
...,'-
tPD(4)
'II
50%~,,---
=:j,
Icc
CURRENT _________________
-1I50%
Iss
_ _ __
2691 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is deaserted first, OE or CEo
3. RiW VIH, and the address is valid prior to other coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE. tAA. and tBDD.
=
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
71321 X20(2) 71321X25(6)
71421X25(6)
Symbol
Parameter
Write Cycle
Write Cycle Time(3)
twc
Chip Enable to End of Write
tEW
Address Valid to End of Write
tAW
Address Set-up Time
tAS
twp
Write Pulse Width(4)
Write Recovery Time
tWR
lOW
uata valla to t:na or vvrlte
Output High Z Tlmel'/
tHZ
uata HOld lime
tDH
Write Enabled to Output in High Zl'l
twz
Output Active From End of Write(l)
tow
Min.
20
15
15
0
15
0
Max.
Min. Max.
-
25
20
20
0
15
0
-
-
lU
-
71321X35
71421X35
Min.
35
30
30
0
25
0
71321X100
71421X100
Max. Min.
Max.
Min.
-
-
100
90
90
0
55
0
55
40
40
0
30
0
20
15
l~
71321X55
71421X55
Max.
-
4U
-
10
-
10
-
15
-
25
-
40
0
-
0
-
0
-
0
-
0
-
-
10
-
10
-
15
-
30
-
40
0
-
0
-
0
-
0
-
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26921bl09
NOTES:
1. Transition is measured ±500mV from Low or High impedance voltage with Output Test Load (Figure 2). This parameter guaranteed
device characterization but is not production tested.
2. O°C to +70°C temperature range only, PLCC package only.
3. For Master/Slave combination, twc tBM + twP, since Rm VIL must occur after tBAA.
4. If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off
data to be placed on the bus for the required tow. If OE is High during a RIW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specifie:\ twP.
5. "XU in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
=
=
6.03
6
IDT71321SA/lA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (R/W CONTROLLED TIMING)(1,5,8)
twc
ADDRESS
~K
)(
tHZ·(7)----+
f
tAw
~ I\.
/
I4-tAS(6)
tWp.(2)
'\
tWA@.
i\.
/
~tHZ~
~
/
14--tWZ(7)
tow
1r
(4)
DATA OUT
tow
DATA IN
(4)
)
~
tOH
'\
/
1,\
2691 drw08
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)(1,5)
twc
ADDRESS
~~
)K
tAW
tAS(6)
'}
~
/V
tEW(2)
I.
DATA IN
J
I"
tWR(3)I--
tow
tOH
.J
~.
'I
NOTES:
1. RiW or CE must be High during all address transitions.
2691 drw 09
2. A write occurs during the overlap (tEW or twp) of CE = VIL and RiW= VIL
3. tWA is measured from the earlier of CE or RiW going High to the end of the write cycle.
4. Durin9!lis period, the 1/0 pins are in the output state and input si~als must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High impedance state.
6. Timing depends on which enable signal (CE or RIW) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +1- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tDW) to allow the 1/0 drivers to turn off
data to be placed on the bus for the required tow. If OE is High during a RJW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
6.03
7
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)
Svmbol
Parameter
71321X20(1) 71321 X25(9)
71321X35
71321X55 71321X100
71421X25(9)
71421X35
71421X55 71421X100
Min. Max.
Min.
Max.
Min.
Max.
-
20
20
20
20
60
35
Min. Max. Min.
Max.
Unit
Busy Timing (For Master IDT71321 Only)
-
20
20
20
20
50
35
-
20
20
20
20
50
35
-
30
30
30
30
80
55
-
50
50
50
50
120
100
tBDC
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
SLiSY Disable Time from ChiD Enable
tWDD
Write Pulse to Data Delav(2)
tDDD
Write Data Valid to Read Data Delay~2)
tAPS
Arbitration Priority Set-up Time(3)
5
-
5
-
5
-
5
-
5
-
ns
tBDD
BUSY Disable to Valid Data(4)
-
20
-
25
-
35
-
55
-
100
ns
tBAA
tBDA
tBAC
ns
ns
ns
ns
ns
ns
Busy Timing (For Slave IDT71421 Only)
tWB
Write to BUSY Input(5)
Write Hold After BUSy(6)
0
12
-
0
15
-
0
20
-
0
20
-
0
20
-
ns
tWH
tWDD
Write Pulse to Data Delay(2)
-
-
60
35
80
55
120
100
ns
-
50
35
-
Write Data Valid to Read Data Delay(2)
-
-
tDDD
40
30
-
-
ns
ns
2689 tbl10
NOTES:
1.Com'l Only, O°C to +70°C temperature range. PLCC package only.
2. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port -to· Port Read and BUSY.
3. To ensure that the earlier of the two ports wins.
4. teDD is a calculated parameter and is the greater of 0, tWDD - twp (actual) or tODD - tow (actual).
5. To ensure that a write cycle is inhibited on port '8' during contention on port 'A' ..
6. To ensure that a write cycle is completed on port '8' after contention on port 'A'.
7. "X" in part numbers indicates power rating (S or L).
8. Not available in DIP package
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
BUS'«2,3,4)
twp
RIWL
BUSYR
(2)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (10T7142).
2. CEl CER Vil
3. OE Vil for the reading port.
4. All-timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "8" is opposite from port "A".
=
=
=
6.03
a
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSV<3)
twp
BUSYR
(2)
NOTES:
1. tWH must be met for both BUSY Input (IDT71421, slave) or Output (IDT71321 master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is oppsite from port "A".
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CETIMING
ADDR 'A'
AND'B'
CE'B'
CE'A'
BUSY'A'
=><
(1)
ADDRESSES MATCH
~~PS~
tBA9 LmDJ
>C
•
2691 drw 12
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING
14------tRC
ADDR'A'
(1)
OR t W D - - - - - - + !
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR'B'
BUSY'B'
_________________tB_AA_~~__________::~~~~~_tB_D_A~~~~~~~~
2691 drw 13
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be
asserted (71321 only).
6.03
9
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL·PORT RAM 16K (2K x a·BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
25
25
35
45
ns
2689 tblll
NOTES:
1. O°C to +70°C temperature range only, PLCC package only.
2.
"X" in part numbers indicates power rating (SA or LA).
3.
Not available in DIP packages.
TIMING WAVEFORM OF INTERRUPT MODE
SETINT
~
ADDR'A'
INTERRUP~:DDRESs")
:f~s~
M
x'--__
JWR'~
RIW'A'
1-t'NS"t_____________________________
INT'B'
2691 drw 14
CLEARINT
ADDR'B'
tRC
xxxxxxxxx~
INTERRUPT CLEAR ADDRESS
tAS (3)
OE'8'
INT'A'
NOTES:.
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or RfiN) is asserted last.
4. Timing depends on which enable signal (CE or RfiN) is de·asserted first.
6.03
10
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I. NON-CONTENTION
READIWRITE CONTROL(4)
Left or Right Port(1)
Function
R/W
CE
OE
00-7
X
H
X
Z
Port Disabled and in PowerDown Mode, 1582 or 1584
X
H
X
Z
CER CEL VIH, Power~Down
Mode 1581 or 1583
L
L
X
H
L
L
H
L
H
=
DATAIN
=
Data on Port Written Into Memory(2
DATAoUT Data in Memory Output on Port(3)
Z
High Impedance Outputs
2654 tbl12
NOTES:
1. AOL - Al0L;o! AOR - Al0R.
2. If BUSY L, data is not written.
3. If BUSY L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = Vll, 'X' = DON'T CARE, 'Z' = HIGH IMPEDANCE
=
=
TABLE II. INTERRUPT FLAG(1,4)
Right Port
Left Port
R/WL
CEL
OEL
Al0L- AOL
INTL
R/WR
CER
OER
Al0L-AoR
INTR
L
L
3FF
X
L(~J
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
3FF
H(3)
L(3)
L
L
3FE
L
L
3FE
H(2)
X
X
X
X
X
X
X
NOTES:
1. Assumes BUSYl = BUSYR = VIH
2. If BUSYl Vll, then No Change.
3. If BUSYR VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON'T CARE
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2654 tbl13
=
=
TABLE 111- ADDRESS BUSY ARBITRATION
Outputs
In!luts
CEL
CER
AOL-Al0L
AOR-Al0R
BUSYL(l)
BUSYR(l)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
Function
2689 tbl14
NOTE:
1. Pins BUSYl and BUSYR are both outputs for IDT71321 (master). Both are inputs for IDT71421 (slave). BUSYx outputs on the IDT71321 are open drain,
not push-pull outputs. On slaves the BUSYx input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR Low will result. BUSYl and BUSYR outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving Low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving Low regardless of actual logic level on the pin.
=
6.03
11
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT71321/IDT71421 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT71321/
IDT71421 has an automatic power down feature controlled
by CEo The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (CE = VIH). When a port is enabled, access to the
entire memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (INTL) is asserted when the
right port writes to memory location 7FE (HEX), where a write
is defined as the CE = RiW = VILperthe Truth Table. The left
port clears the interrupt by access address location 7FE
access when CER = OER = VIL. RiW is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when
the left port writes to memory location 7FF (HEX) and to clear
the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF
is user-defined, since it is an addressable SRAM location. If
the interrupt function is not used, address locations 7FE and
7FF are not used as mail boxes, but as part of the random
access memory. Refer to Table I for the interrupt operation.
The Busy outputs on the IDT71321 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT71321/IDT71421 RAMs the
Busy pin is an output if the part is Master (I DT71321), and the
Busy pin is an input if the part is a Slave (IDT71421) as shown
in Figure 3.
270n
2691 drw16
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is "Busy". The Busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the BUSY pin operates solely as
a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins High. If desired, unintended
write operations can be prevented to a port by tying the Busy
pin for that port Low.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 RAMs.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the RiW signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
6.03
12
IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAM 16K (2K x a-SIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
xxxx
_A_~
Device Type Power
Speed
A
A
Package
Processl
Temperature
Range
Y
II
L...-------I
BLANK
Commercial (O°Clo +70°C)
J
pF
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
14~:O~5
'-------------1.
}
LA
SA
71321
~---------------~
71421
Speed in nanoseconds
Low Power
Standard Power
16K (2K x a-Bit) MASTER Dual-Port RAM
wi Interrupt
16K (2K x a-Bit) SLAVE Dual-Port RAM
wi Interrupt
2691 drw 17
6.03
13
t;)®
IDT1134SA
IDT7134LA
CMOS DUAL-PORT RAM
32K (4K x a-BIT)
Integrated Device Technology, Inc.
FEATURES:
• High-speed access
Military: 25/35/45/55nOns (max.)
Commercial: 20/25/35/45/55nOns (max.)
• Low-power operation
IDT7134SA
Active: 500mW (typ.)
Standby: 5mW (typ.)
IDT7134LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in several popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40°C to +85°C) is available,
tested to military electrical specifications
DESCRIPTION:
The IDT7134 is an extremely high-speed 4K x 8 Dual-Port
Static RAM designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself
to those systems which cannot tolerate wait states or are
designed to be able to externally arbitrate or withstand
contention when both sides simultaneously access the same
Dual-Port RAM location.
The IDT7134 provides two independent ports with separate
control, address, and 110 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. It is the user's responsibility to ensure data integrity
when simultaneously accessing the same memory location
from both ports. An automatic power down feature, controlled
by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
Fabricated using lOT's CMOS high-performance
technology, these Dual-Port typically on only 500mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each port typically consuming 200J..LW
from a 2V battery.
The IDT7134 is packaged on either a sidebraze or plastic
48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Ceramic
Flatpack. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
RiWl
CEl
RtWR
CER
OEl
OER
I/OOl- I/07l
AOl- A11l
I/OOR- I/07R
LEFT SIDE
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
RIGHT SIDE
ADDRESS
DECODE
LOGIC
AOR- A11R
2720 drw01
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1995 Integrated Device Technology, Inc.
6.04
APRIL 1995
DSC-127912
1
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1)
CEL
~
Vee
CER
RtWR
A11R
A10R
OER
AOR
A1R
A2R
A3R
A4R
ASR
A6R
RtWl
A11l
A10l
OEL
AOl
A1l
A2l
A3l
A4l
ASl
A6l
All
A8l
A9l
1I00l
~ ~
L-J L-J L-J L-J L-J L-J I I LJ L-J L-J L-J L-J L-J
765
2
4 3
L
~
5251 5049 4847
1
46[
OEA
45[
AOA
J 10
44[
AlA
A4l
J 11
43[
A2A
ASl
J 12
42[
A3A
ASl
J 13
41[
A4A
A7R
A7l
J 14
A8R
A9R
ABl
J 15
I/0lR
1/06R
1I03l
1I04l
I/OSR
1I04R
I/0Sl
1/06l
I/0ll
1/03R
1/02R
1/01R
I/OOR
=
~
J9
1/01l
1/02l
GND-...:;:~_ _ _
~
cllID ~ ;::: ~ I lID
[3 ICli I~ ~ ;::: ~
«O««z
u>u
z««
INDEX
J8
IDT7134
J52-1
PLCC
TOP VIEW
40[
ASA
39[
ASA
38[
A7R
37[
ABA
A9l
J 16
1I0ol
J 17
I/Oll
J 18
36[
A9A
I/02l
J 19
35[
I/03l
J 20
34[
N/C
I/07R
(1)
21 22 23 24 25 26 27 28 29 30 31 32 33
nnnnnnnnnnnnn
..J
~
~
U')
~
uQ
....
z
ZC)
~
<&>
....
~ ~ ~~
2720 drw 02
~
~
o
~
M
~
C\I
-
~
-.:t
~
~
II)
(Q
~~~~~~~
2720 drw 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2 Terminal Voltage
Com'l.
Mil.
Unit
-0.5 to +7.0
-0.5 to +7.0
V
with Respect
to Ground
INDEX~
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
Pr(3)
Power Dissipation
1.5
1.5
W
lOUT
DC Outout Current
50
50
mA
6 5 4 3 2 L ~ 48 47 46 45 44 43
1
All J7
42[
A2l J8
41[
A3l J9
40C
A4l J10
39C
ASl J 11
38C
IDT7134
L48-1
ASl J12
37C
&
A7l J13
36C
F48-1
(1)
ABl J14
A9l J15
LCClFJatpack
TOP VIEW (2)
I/OOl J16
I/Oll J17
I/02l J18
31C
19 2021 2223 2425 2627 2829 30
2720 tbJ 01
NOTE:
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or
10 ns maximum, and is limited to :s 20mA for the period of VTERM ~ Vcc
+0.5V.
CAPACITANCE(1)
Symbol
(TA
•
c5 ,ill ~ :! I~ ,ill 8 ,65 I~ ~ ~ ,&i
«0««
u>()
««0
L-J L-J L-J L-J L-J I J L-J LJ L-J L-J L-J L-J
AOA
AlA
A2A
A3A
A4A
ASA
ASA
A7A
ABA
A9A
1/07R
I/OSA
nnnnnnnl""lr-'lr-'lr-'lr-'l
....J
M
....J
"o:t
....J
I.()
....J
CD
....J
,.....
~~~~~
Q
a:
~
a:
a:
a: a:
~~~ ~ § ~ ~
2720 drw 04
= +25°C, f = 1.0MHz)
Parameter
CIN
Input Capacitance
COUT
Outp_ut Ca~acitance
Conditions
Max.
Unit
= 3dv(2)
VOUT = 3dv(2)
9
pF
VIN
10
NOTE:
1. This text does not indicate orientation of actual part-marking.
J>F
2720 tbJ 02
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
Signals switch from OV to 3V and from 3V to OV.
6.04
2
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Ambient
Temperature
GND
Vee
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
Parameter
Vee
Supply Voltage
GND
Ground
VIH
Input High Voltage
Input Low Voltage
VIL
2720 tbl 03
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
a
a
V
2.2
a
-
6.0(2)
V
-0.5(1)
-
0.8
NOTES:
1. VIL (min.) ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
V
2720 tbl 04
DC ELECTRICAL CHARACTERISTICS QVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = SV ± 10%)
IDT7134SA
Symbol
Parameter
Test Conditions
IDT7134LA
Min.
Max.
Min.
Max.
Unit
-
5
IlA
5
IlA
0.4
V
0.5
V
-
V
1IL11
Input Leakage Current(l)
Vee = 5.5V. VIN = OV to Vee
-
10
IILOI
Output Leakage Current
CE
=VIH. Your =OV to Vee
10
VOL
Output Low Voltage
IOL= 6mA
-
0.4
IOL= 8mA
-
0.5
-
IOH =-4mA
2.4
-
2.4
VOH
Output High Voltage
1. At Vcc < 2.0V Input leakages are undefined.
2720 tbl 05
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc = S.OV ± 10%)
7134X20(4)
Symbol
Parameter
Icc
Dynamic Operating
Current
CE=VIL
Outputs Open
MIL.
(Both Ports Active)
f =fMAX(3)
COM'L.S
L
170
170
Standby Current
(Both Ports-TTL
CEL and CER = VIH
f = fMAX(3)
MIL.
IS91
Test Conditions
Level Inputs)
IS92
IS93
ISB4
Version
7134X25
7134X35
7134X45
7134X55
7134X70
Typ,l2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
-
160
160
310
260
150
150
300
250
140
140
280
240
140
140
270
220
140 270
140 220
280
240
160
160
280
220
150
150
260
210
140
140
240
200
140
140
240
200
140 240
140 200
-
-
25
25
100
80
25
25
75
55
25
25
70
50
25
25
70
50
25
25
70
50
COM'L.S
L
25
25
110
80
25
25
80
50
25
25
75
45
25
25
70
40
25
25
70
40
25
25
70
40
MIL.
-
-
95
95
210
170
85
85
200
160
75
75
190
150
75
75
180
150
75
75
180
150
105
105
180
150
95
95
180
140
85
85
170
130
75
75
160
130
75
75
160
130
75
75
160
130
-
-
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
S
L
S
L
Standby Current
(One Port-TTL
CEA• = V 1L and
CE e·= V 1H
Level Inputs)
Active Port Outputs COM'L.S
Open. f = fMAX(3)
L
Full Standby Current Both Ports CEL and MIL.
(Both Ports-All
CER ;:: Vee - 0.2V
S
L
S
L
-
CMOS Level Inputs) VIN;:: Vee - 0.2V or
VIN ~ 0.2V. f = 0(3)
COM'L.S
L
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
Full Standby Current One Port CEA• or
(One Port-All
CE e• ;:: Vee· 0.2V
CMOS Level Inputs) VIN ;:: Vee - 0.2V or
VIN ~0.2V
MIL.
-
-
95
95
210
150
85
85
190
130
75
75
180
120
75
75
170
120
75
75
170
120
105
105
170
130
95
95
170
120
85
85
160
110
75
75
150
100
75
75
150
100
75
75
150
100
S
L
COM'L.S
L
rnA
rnA
rnA
rnA
rnA
Active Port Outputs
Open, f = fMAX(3)
NOTES:
2720tbl06
1. "X" in part number indicates power rating (SA or LA).
2. Vee = 5V. TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRe = All inputs cycling atf = 1/tRe (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby IS93.
4. (Commercial only) O°C to +70°C temperature range.
6.04
3
'~
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(LA Version Only) VLC
Symbol
=O.2V, VHC =VCC - O.2V
Test Condition
Parameter
Min.
=2V
VDR
VCC for Data Retention
Vcc
ICCDR
Data Retention Current
CE~VHC
I
MIL.
VIN ~ VHC or ~ VLC
r
COM'L.
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
Typ.(1)
Max.
2.0
-
-
-
100
100
4000
1500
0
-
tRC(2)
-
-
NOTES:
1. VCC::: 2V, TA +25°C, and are not production tested.
2. tAC::: Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
Unit
V
llA
ns
ns
2720 tbl 07
=
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
2720 drw 05
AC TEST CONDITIONS
GND to 3.0V
5ns
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
See Figures 1 and 2
2720 tbl 08
+5V
+5V
DATAoUT - . . - - - .
DATAoUT - - -...
30pF *
2720 drw 06
2720 drw07
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
*Including scope and jig
Figure 1. AC Output Test Load
6.04
4
IDT1134SAlLA
CMOS DUAL-PORT RAM 32K (4K
x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
'OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
7134X20(3)
Symbol
Parameter
Min.
Max.
7134X25
Min.
Max.
7134X35
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
-
25
-
35
-
ns
tM
Address Access Time
-
20
20
15
-
25
25
15
-
ns
-
35
35
20
0
-
0
ns
0
-
0
-
-
15
-
20
ns
tACE
Chip Enable Access Time
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(l, 2)
3
-
tHZ
Output High-Z Time(l, 2)
-
15
tpu
Chip Enable to Power Up Time\~)
tPD
Chip Disable to Power Down Time(2)
-
ns
ns
ns
0
-
0
-
0
-
ns
-
20
-
25
-
35
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4) (CONTI D)
7134X45
Symbol
Parameter
Min.
Max.
7134X55
Min.
Max.
7134X70
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
-
55
-
70
-
ns
tM
Address Access Time
-
45
45
25
-
55
55
30
-
ns
-
70
70
40
0
0
-
ns
tACE
Chip Enable Access Time
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
0
tLZ
Output Low-Z Time(l, 2)
5
-
5
-
5
-
ns
tHZ
Output High-Z Time(l, 2)
-
20
-
25
-
30
ns
tpu
Chip Enable to Power Up Time\~)
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
45
-
50
-
50
NOTES:
1. Transition is measured ±500mV from Low or High impedance voltage with the Output Test Load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. (Commercial only) O°C to +70°C temperature range only.
4. "X" in part number indicates power rating (SA or LA).
ns
ns
ns
2720 tbl 09
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1, 2, 4)
ADDRESS
DATAoUT
DATA VALID
PREVIOUS DATA VALID
2720 drw OB
6.04
5
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1,3)
tACE
/~
~,
AOE(4)
HZ(2)
~,
tLZ(I)
.
.., / /..,
DATAoUT
-'{"
~
Icc
CURRENT
ISB
~~50%
tLZ(I!
"' "
CHZO'-
.
-'{"
I
tpu
__________
~~
VALID DATA(4)
tPD
.11
50%L
2720 drw09
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is de-asserted first, OE or CEo
3. RIW V 1H and OE V 1L , unless otherwise noted.
4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
=
=
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
7134X20(5)
Symbol
Parameter
Min.
20
15
15
0
7134X25
Max.
Max.
Min.
-
15
7134X35
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
tEW
Chip Enable to End-of-Write
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write RecoveryTime
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(l, 2)
tDH
Data Hold Time(3)
twz
Write Enabled to Output in High-Z(l, 2)
tow
Output Active from End-of-Write(l, 2, 3)
tWDD
Write Pulse to Data Delay(4)
tDDD
Write Data Valid to Read Data Del ay(4)lf)
NOTES:
15
0
15
-
25
20
20
0
20
0
15
-
15
-
-
-
ns
-
ns
ns
25
0
20
-
-
20
35
30
30
0
ns
ns
ns
ns
ns
0
-
0
-
3
-
ns
-
15
-
15
-
20
ns
3
-
3
-
3
-
ns
-
40
-
50
-
60
ns
30
30
35
ns
2720 tbllO
1. Transition is measured ±500mV from Low or High impedance voltage with Output Test Load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for toH must be met by the device supplying write data to the RAM under all operating conditions. Although toH and tow values will vary
over voltage and temperature, the actual toH will always be smaller than the actual tow.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to ''Timing Waveform of Write with Port - to - Port Read".
5. (Commercial only), O°C to +70°C temperature range.
6. "X' in part number indicates power rating (SA or LA).
7. tODD = 35ns for military temperature range.
6.04
6
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K
x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6) (CONrO)
7134X45
Symbol
Parameter
Min.
7134X55
Max.
Min.
Max.
7134X70
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
45
tEW
Chip Enable to End-of-Write
40
tAW
Address Valid to End-of-Write
40
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write RecoveryTime
tow
Data Valid to End-of-Write
20
-
-
tHZ
Output High-Z Time(l, 2)
tDH
Data Hold Time(3)
50
-
60
50
-
0
25
-
20
-
-
3
-
20
3
-
0
40
0
3
twz
Write Enabled to Output in High-Z(l, 2)
tow
Output Active from End-of-Write(1, 2, 3)
tWDD
Write Pulse to Data Delay (4)
-
70
tODD
Write Data Valid to Read Data Delay(4)
-
45
-
ns
60
-
ns
0
30
-
25
-
30
ns
-
3
-
ns
-
25
-
30
ns
3
-
3
-
ns
-
80
-
90
ns
55
50
0
55
70
60
0
ns
ns
ns
ns
ns
70
ns
2720 tbl10
NOTES:
1. Transition is measured ±500mV fromLow orHigh impedance voltage with Output Test Load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tow values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tow.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port - to - Port Read".
5. (Commercial only), O°C to +70"C temperature range.
6. "X" in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF WRITE WITH PORT - TO - PORT READ
I
ADDR "A"
RiW'A"(l)
(1)
twc
f
)(
MATCH
twp
"--tAW
,,~
/'
~tDW~
'V
DATAIN "A"
/i'\.
ADDR 'B"
VALID
MATCH
tWDD
)K VALID
DATAoUT"B"
tODD
2720 drw 10
NOTE:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEl =CER =VIL. OE'B' =VIL.
3. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
6.04
7
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1, 5,8)
twc
ADDRESS
OE
CE
twp(2
RNi
DATAoUT
DATAIN
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1, 5)
twc
ADDRESS
",V
)(
/r-....
tAW
~AS(6)
}
I
/V
__________________________________
DATAIN
•
tEW(2)
tWR(3) •
~r:___-t-DW-----.-I-.----t-D-H___:i.__________________
L
--.-/1
2720 drw 11
NOTES:
RiW or CE must be High during all address transitions.
A write occurs during the overlap (tEw or twp) of a CE =VIL and RJW"=-VIL.
tWR is measured from the earlier of CE or Rm going high to the end-of-write cycle.
Durin[!lis period, the I/O pins are in the output state, and input ~nals must not be applied.
If the CE low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
Timing depends on which enable signal ( CE or RiW")iS asserted last.
This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± SOOmV from steady state with the Output
Test Load (Figure 2).
8. If DE is low during a RiW controlled write ~Ie, the write pulse w~h must be the larger of twp or (twz + tow) to allow the liD drivers to turn off data to be
placed on the bus for the required tow. If DE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified twP.
1.
2.
3.
4.
S.
6.
7.
6.04
8
IDT7134SAlLA
CMOS DUAL-PORT RAM 32K (4K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE I - READIWRITE CONTROL
FUNCTIONAL DESCRIPTION
The IDT7134 provides two ports with separate control,
address, and 1/0 pins that permit independent access for
reads or writes to any location in memory. These devices have
an automatic power down feature controlled by CE. The CE
controls on-Chip power down circuitry that permits the
respective port to go into standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output
Enable control (OE). In the read mode, the port's OEturns on
the output drivers when set LOW. Non-contention READI
WRITE conditions are illustrated in the table below.
Left or Right Port(1)
Function
RIW
CE
OE
00-7
X
H
X
Z
Port Disabled and in Power
Down Mode, IS82 or IS84
X
H
X
Z
CER = CEl = H, Power Down
Mode, IS81 or IS83
L
L
X
DATAIN
H
L
L
DATAoUT
X
X
H
Z
Data on port written into
memory
Data in memory output on port
High impedance outputs
2720 tbl11
NOTE:
1.
AOL - A11L
"H"
* AOR - A11R
=HIGH, "L" =LOW, "X" =Don't Care, and "Z" =High Impedance
ORDERING INFORMATION
IDT
XXXX
Device Type
_A_
Power
~
Speed
__
A_
Package
A
Process/
Temperature
Range
Y:lank
P
C
1....---------1
J
L48
F
20
25
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
48-pin
48-pin
52-pin
48-pin
48-pin
Plastic DIP (P48-1)
Ceramic DIP (C48-2)
PLCC (J52-1)
LCC (L48-1)
Ceramic Flatpack (F48-1)
Commercial onlY}
35
1....-_ _ _ _ _ _ _ _ _ _--1 45
Speed in nanoseconds
55
70
ILA
~--------------------------tISA
L---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I
7134
Low Power
Standard Power
32K (4K x 8-Bit) Dual-Port RAM
2720 drw 13
6.04
9
~®
Integrated Device Technology, Inc.
IDT71342SA
IDT71342LA
CMOS DUAL-PORT RAM
32K (4K x a-BIT)
WITH SEMAPHORE
FEATURES:
DESCRIPTION:
• High-speed access
Commercial: 20/25/35/45/55/70ns (max.)
• Low-power opera(7) tion
IDT71342SA
Active: 500mW (typ.)
Standby: 5mW (typ.)
IDT71342LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation-2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in plastiC packages
The I DT71342 is an extremely high-speed 4K x 8 Dual-Port
Static RAM with full on-chip hardware support of semaphore
signalling between the two ports.
The IDT71342 provides two independent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. To assist in arbitrating between ports, a fully
independent semaphore logic block is provided. This block
contains unassigned flags which can be accessed by either
side; however, only one side can control the flag at any time.
An automatic power down feature, controlled by CE and SEM,
permits the on-chip circuitry of each port to enter a very low
standby power mode (both CE and SEM high).
Fabricated using lOT's CMOS high-performance
technology, this device typically operates on only 500mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each port typically consuming 200llW
from a 2V battery. The device is packaged in either a 64-pin
TQFP, thin quad plastic flatpack, or a 52-pin PLCC.
FUNCTIONAL BLOCK DIAGRAM
t:
:::l
~
I/00l- 1107L
!
!
COLUMN
1/0
~
AOl- A11l
.Ii
I\.
~r
COLUMN
1/0
MEMORY
ARRAY
-
SEMAPHORE
LOGIC
RIGHT SIDE
ADDRESS
DECODE
LOGIC
LEFT SIDE
ADDRESS
DECODE
LOGIC
;:J
IIOOA - 1/07A
SEMA
AOA- A11A
2721 drw01
The IDT logo Is a registered trademark of Integrated Device Technology. Inc.
COMMERCIAL TEMPERATURE RANGES
Qt 995 Integ rated Device Technology. Inc.
APRIL 1995
6.05
DSC-123513
1
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1)
...J
...J
a: a:
...J
31 tTI ~ ;: IrE I~ ItTIu>u
8 10] I~ IrE(I)
«0««(1)
INDEX
LJ LJ LJ LJ LJ L...J
I I
LJ LJ LJ LJ LJ LJ
765 4 3 2
L J
52 51 50 49 48 47
All J8
A2l J9
A3l J 10
A4l J 11
ASl J 12
ASl J 13
A7l J 14
ASl
A9l
I/OOl J
I/Oll J
J
J
~ a:
0
~ ~
1
46[
45[
44[
43[
42[
IDT71342
J52-1
41[
40[
PLCC (2)
TOP VIEW
""'"C')C\I ..... OO>COl' COlt') ""'"C')C\I ..... OO>
OER
AOR
A1R
A2R
A3R
A4R
ASR
ASR
A7R
ASR
A9R
N/C
I/07R
39[
38[
17
18
19
34[
20
21 2223 2425 2627 2829 3031 3233
OEl
AOl
All
A2l
A3l
A4l
ASl
ASl
N/C
A7l
ASl
A9l
N/C
I/OOl
I/Oll
I/02l
~COCOCOCOlt')lt')lt')lt')lt')lt')lt')lt')lt')lt')""'"~
2
3
OER
AOR
A1R
A2R
A3R
A4R
ASR
ASR
N/C
A7R
ASR
A9R
N/C
N/C
I/07R
I/OSR
47
4
71342
PN64-1
64-PIN TQFP(2)
TOP VIEW
nnnnnnnnnnnnn
...J
...J
...J
...J
a:: a: a:: a:
a:
UCl a:: a:: (\j
L{)
(0
co r-.
M V
"""z o
000
~ ~ ~~ Z 0 ~~ ~ 0
::::::::::::::::::::
' 20m A for the period of VTERM ~ Vcc
+O.5V.
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Vee
5.0V± 10%
2721 tbl03
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Vee
Supply Voltage
GND
Ground
VIH
VIL
Input High Voltage
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
-0.5(1)
-
6.0(2)
V
0.8
V
2721 tbl04
NOTE:
1. VIL (min.) ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.5V.
6.05
2
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x S-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (vcc =SV ± 10%)
IDT71342SA
Symbol
Min,
Test Conditions
Parameter
IDT71342LA
Max,
Min,
0.4
V
V
Max,
Unit
5
~A
5
~A
lIul
Input Leakage Current(l)
Vee = 5,5V, VIN = OV to Vee
-
10
IILOI
Output Leakage Current
CE = VIH,
Your =
10
VOL
Output Low Voltage
IOL= 6mA
-
0.4
-
IOL= 8mA
-
0.5
-
0.5
IOH =-4mA
2.4
-
2.4
-
VOH
Output High Voltage
OV to Vee
V
2721 tbl05
NOTES:
1. At Vcc .$. 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = S.OV ± 10%)
71342X20
Symbol
Parameter
ICC
ICC1
ISB1
ISB2
ISB3
ISB4
Typ,(2) Max,
Test Conditions
Version
Dynamic Operating
CE=Vll
COM'L. S
-
280
Current
(Both Ports Active)
Outputs Open
SEM = Don't Care
f=fMAX(3)
L
-
240
COM'L. S
-
Dynamic Operating
CE=VIH
Current
(Semaphores
Both Sides)
Outputs Open
SEM .$.Vll
f=fMAX(3)
L
71342X25
T~p.(2
71342X35
71342X45
71342X55 71342X70
Max, Typ.(2) Max, TYp.(2) Max. TYQ.(2 Max, TypP Max, Unit
-
280
280
-
200
240
-
-
260
170
-
240
-
240
185
-
170
155
-
140
220
200
-
240
-
240
200
-
200
-
170
-
140
-
140
170
Standby Current
CEL and CER = VIH
COM'L. S
25
80
25
80
25
75
25
70
25
70
25
70
(Both Ports-TTL
Level Inputs)
SEMl = SEMR ~ VIH
f = fMAX(3)
L
25
80
25
50
25
45
25
40
25
40
25
40
Standby Current
CE'A'= Viland
COM'L. S
-
180
-
180
-
170
-
160
L
-
150
-
150
-
140
-
130
-
160
CE'B'=VIH
Active Port Outputs
Open, f = fMAX(3)
-
160
(One Port-TTL
Level Inputs)
1.0
0.2
15
4.5
1.0
15
4.0
1.0
1.0
0.2
15
4.0
1.0
0.2
1.0
0.2
15
4.0
15
0.2
4.0
0.2
4.0
-
170
150
-
150
-
150
-
120
-
150
120
Full Standby Current Both Ports CEl and COM'L. S
(Both Ports-All
CER ~ Vee - 0.2V
L
CMOS Level Inputs) VIN ~ Vee - 0.2V or
VIN.$.0.2V
SEMl= SEMR~
Vee - 0.2V, f = 0(3)
Full Standby Current
One Port CE'A' or
(One Port-All
CE'B' ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
VIN.$.0.2V
CMOS Level Inputs)
COM'L. S
L
140
-
170
140
-
130
15
130
mA
rnA
rnA
rnA
130
rnA
rnA
120
SEMl=SEMR~
Vee- 0.2V
Active Port Outputs
Open f = fMAX(3)
2721 tbl 06
NOTES:
1. "X· in part number indicates power rating (SA or LA).
2. Vee = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1ltRe = All inputs cycling at f = 1ltRe (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby IS83.
6,05
3
IDT71342SAILA
CMOS DUAL-PORT RAM 32K (4K
x S-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS
(LA Version Only) VLC =O.2V, VHC
Symbol
=Vcc - O.2V
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Test Condition
Min.
Typ.(1)
-
2.0
-
-
100
Vcc = 2V, CE ~ VHC
I
COM'L,
Max.
-
Unit
V
1500
JlA
SEM ~VHC
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
0
-
tRC(2)
-
VIN ~ VHC or ~ VLC
-
ns
ns
2721 tbl07
NOTES:
1. Vcc 2V, TA +25°C, and are not production tested.
2. tAC Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
=
=
=
DATA RETENTION WAVEFORM
VCC
4
:f
DATA RETENTION MODE
{
5 ""'-____V_D_R_~_2V_ _ _ ____'
4.5 V .-I
~ tCD~
W/ff/#//?fVIH
tR _I
,
VDR
/
VIH~~
2721 drw04
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2721 tbl08
+5V
+5V
1250n
DATAoUT - . . - -...
775
DATAoUT - . - -......
30pF
5pF *
2721 drw05
2721 drw06
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
*Including scope and jig
Figure 1. AC Output Test Load
6.05
4
IDT71342SA/LA
CMOS DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
71342X20
Symbol
Parameter
Min.
71342X25
Max.
. Min.
Max.
71342X35
Min •
Max.
Unit
flEAD CYCLE
tRC
Read Cycle Time
20
-
25
-
35
-
ns
tAA
Address Access Time
20
-
25
-
35
ns
25
-
15
-
35
20
ns
0
-
0
tACE
Chip Enable Access Time(3)
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(1. 2)
3
-
0
-
tHZ
Output High-Z Time(1. 2)
-
15
-
15
tpu
Chip Enable to Power Up Time(2)
0
-
0
tPD
Chip Disable to Power Down Time(2)
-
50
20
15
ns
ns
p
-
-
20
ns
-
0
-
ns
-
50
-
50
ns
ns
tsop
SEM Flag Update Pulse (OE or SEM)
-
-
10
-
15
-
ns
tWDD
Write Pulse to Data Delay(4)
40
ns
30
Semaphore Address Access Time
-
-
35
35
ns
tSAA
-
60
Write Data Valid to Read Data Delay(4)
-
50
tODD
-
30
25
ns
2721 tbl09
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5) (CONT/D)
71342X45
Symbol
Parameter
Min.
Max.
71342X55
Min.
Max.
71342X70
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
-
55
-
70
-
ns
tAA
Address Access Time
-
45
55
ns
55
30
-
70
45
25
-
70
40
ns
-
0
5
-
0
ns
-
5
-
tACE
Chip Enable Access Time(3)
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1. 2)
0
5
tHZ
Output High-Z Time(1. 2)
-
20
-
25
-
30
ns
tpu
Chip Enable to Power Up Time(2)
0
-
0
-
0
-
ns
ns
ns
tPD
Chip Disable to Power Down Time(2)
-
50
-
50
-
50
ns
tsop
SEM Flag Update Pulse (OE or SEM)
15
-
20
-
20
-
ns
tWDD
Write Pulse to Data Delay(4)
70
-
80
ns
Write Data Valid to Read Data Delay(4)
tSAA
Semaphore Address Access Time
45
45
-
55
55
-
90
tODD
-
70
70
ns
-
ns
2721 tbll0
NOTES:
1.
2.
3.
4.
Transition is measured ±500mV from Low or High impedance voltage with the Ouput Test Load (Figure 2).
This parameter is~aranteed by device characterization, but is not production tested.
To access RAM, CE VIL. SEM VIH. To access semaphore, CE VIH, and SEM VIL.
"X" in part number indicates power rating (SA or LA).
=
=
=
=
6.05
5
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1, 2, 4)
ADDRESS
----~
- t~O~H~-_~ _-~ _-~ _-~ -t~R-C~ ~ ~ ~ ~ -.- -1~~~~~~~t~------t-O-H==~~~~~-
......:----:---------
.. -
PREVIOUS DATA VALID
DATAoUT
DATA VALID
2721 drw07
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1, 3)
) -:;
/
r-- tso
~K
tACE
/£
tAOE(4)
tso
tHZ
~K
/'£
CIHZ(:!-
tLZ(l)
-,:,<-/ /-::<-
DATAoUT
tLZ
.. ~" ".;~
(1)
CURRENT
ISB
:~
VALID DATA (4)
I,-
===~~~~~~-~-:4t~r5-00-~----------------------5--0%~
• tpu
Icc
(2)
tPD
2721 drw OS
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is de-asserted first, OE or CEo
3. RIW = VIH and OE = Vll, unless otherwise noted.
4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA
5. To access RAM, CE Vil and SEM VIH. To access semaphore, CE VIH and SEM VIL. tAA is for RAM Address Access and tSAA is for Semaphore
Address Access.
=
=
=
=
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1,2)
,
ADDR 'A'
twc
f
)(
MATCH
twp
",
/
/
tDW
)(
DATAIN'A"
ADDR "B"
tDH .1
)k
VALID
MATCH
tWDD
)K
DATAOUT'B"
tDDD
VALID
2721 drw 09
NOTE:
1. Write ~Ie parameters should be adhered to, in order to ensure proper writing.
2. CEl =CER =VIL. CE-B' = VIL.
3. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
6.05
6
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K
x a-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
71342X20
Symbol
Parameter
71342X25
Min.
Max.
-Min.
-
20
71342X35
Max.
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
20
tEW
Chip Enable to End-of-Write(3)
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End-of-Write
15
15
0
15
0
15
tHZ
Output High-Z Time(1· 2)
-
-
25
-
30
30
0
25
0
20
-
-
20
-
20
0
20
0
15
15
-
15
-
-
35
ns
ns
ns
ns
ns
ns
ns
ns
tOH
Data Hold Time\~)
0
-
0
-
3
-
ns
twz
Write Enabled to Output in High-ZP'~)
-
15
-
15
-
20
ns
3
10
10
-
3
10
10
-
3
10
10
-
ns
-
-
ns
tow
Output Active from End-of-Write\ I. ~. ~)
tSWR
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
-
ns
2721 tbl11
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)(CONT ' D}
71342X45
Symbol
Parameter
Min.
71342X55
Max.
71342X70
Min.
Max.
Min.
55
-
70
-
60
60
0
60
0
30
-
Max.
Unit
WRITE CYCLE
-
twc
Write Cycle Time
45
tEW
Chip Enable to End-of-Write(3)
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
-
50
50
0
50
0
25
ns
I
tow
Data Valid to End-of-Write
40
40
0
40
0
20
tHZ
Output High-Z Time(1· 2)
-
20
-
25
-
30
ns
tbH
Data Hold Time(4)
3
-
3
-
3
-
ns
-
-
ns
ns
ns
ns
ns
ns
twz
Write Enabled to Output in High-Z(l. 2)
-
20
-
25
-
30
ns
tow
Output Active from End-of-Write(1· 2. 4)
3
-
3
-
3
ns
tSWR
SEM Flag Write to Read Time
SEM Flag Contention Window
10
10
-
10
10
-
tsps
10
10
-
-
ns
ns
2721 tbl12
NOTES:
1. Transition is measured ±SOOmV from Low or High impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access RAM. CE VIL and SEM VIH. To access semaphore, CE VIH and SEM VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tow values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tow.
5. "X" in part number indicates power rating (SA or LA).
=
=
=
6.05
EI
=
7
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x B-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, RlWCONTROLLED TIMING(1,5,B)
~........................................--twC""''''''''''''''''''''''''''''''''''''~~
ADDRESS
twp (....;2)....._
.....---t~
Rm
DATAoUT
DATAIN
2721 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1, 5)
twc
)(
ADDRESS
)(
tAW
CEorSEM
(9)
_tAS'O,
DATAIN
l
/
tEW(2)
/
twR(~
-i~_t_DW.........._._'_..........._t_D_H~~............................................._
__................................................................................
2721 drw 11
NOTES:
1. RJW or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or twp) of either CE or SEM = VIL and RJW"= V,L.
3. tWR is measured from the earlier of CE or pJW going High to the end-of-write cycle.
4. Durin~is period, the 1/0 pins are in the output state, and input s~als must not be applied.
5. If the CE Low transition occurs simultaneously with or after the RIW Low transition, the outputs remain in the High - impedance state.
6. Timing depends on which enable signal (CE or RIW) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± 500mV from steady state with the Output
Test Load (Figure 2).
8. If OE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 1/0 drivers to turn off data to be
placed on the bus for the required tow. If OE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified twP.
9. To access RAM, CE =V,L and SEM = VIH. To access semaphore, CE = V,H and SEM = V,L. Either condition must be valid for the entire tEW time.
6.05
s
IDT71342SAILA
CMOS DUAL-PORT RAM 32K (4K x S-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
1 . . - - - - tSAA--~~
Ao-A2
VALID ADDRESS
DATPoUT
VALID
DATAo
tAOE
2721 drw 12
NOTE:
1. CE
=VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
II
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from the point where RiW "A" or SEM "A" goes High until RiW "a" or SEM "a" goes High.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.05
9
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K
x 8-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer's software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAMs and can be read from or written to at the
same time, with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-Chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Table 1 where CE and
SEM are both high.
Systems which Gan best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT71342's hardware semaphores, which
provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT71342 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that a shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor had set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to gain
control of the token via the set and test sequence. Once the
right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT71342 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RiW) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through the address pins Ao-A2. When accessing
the semaphores, none of the other address pins has any
effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other (see
Table II). That semaphore can now only be modified by the
side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this
feature follows shortly.) A zero written into the same location
from the other side will be stored in the semaphore request
latch for that side until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence of WRITE/READ must be used by the
semaphore in order to guarantee that no system level
contention will occur. A processor requests access to shared
resources by attempting to write a zero into a semaphore
location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will
appear as a one, a fact which the processor will verify by the
subsequent read (see Table II). As an example, assume a
6.05
10
IDT71342SAILA
CMOS DUAL-PORT RAM 32K (4K x S-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
processor writes a zero in the left port at a free semaphore
location. On a subsequent read, the processor will verify that
it has written successfully to that location and will assume
control overthe resource in question. Meanwhile, if a processor
on the right side attempts to write a zero to the same semaphore
flag it will fail, as will be verified by the fact that a one will be
read from that semaphore on the right side during a subsequent
read. Had a sequence of READIWRITE been used instead,
system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 3. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
TABLE I -
the semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will now stay low
until its semaphore request latch is written to a one. From this
it is easy to understand that, if a semaphore is requested and
the processor which requested it no longer needs the resource,
the entire can hang up until a one is written into that semaphore
request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous re.quests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
NON-CONTENTION READIWRITE CONTROL
Left or Right Port(1)
RiW
C£:
X
H
H
H
X
X
.;H
L
X
SEM
H
OE
00-7
X
Z
Function
Port Disabled and in Power Down Mode
Data in Semaphore Flag Output on Port
L
L
X
H
DATAoUT
H
L
X
DATAIN
Port Data Bit DO Written Into Semaphore Flag
L
L
DATAoUT
Data in Memory Output on Port
L
H
H
X
DATAIN
L
L
X
-
Z
Output Disabled
Data on Port Written Into Memory
NotAl/owed
2721 tbl13
NOTE:
1. AOL
"H"
"y"
=A10L AOR - A1oR.
=HIGH, "L" =LOW, "X" =Don't
¢
=Low-to-High transition.
Care, "Z"
=High Impedance, and
TABLE 11- EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE(1)
Function
Do - 07 Left
Do - 07 Right
No Action
1
1
Status
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left side has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
;.!f;'!llDll,
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
6.05
11
IDT71342SAlLA
CMOS DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen. Code integrity is of the
utmost importance when semaphores are used instead of
slower, more restrictive hardware intensive schemes.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-Some examples
Perhaps the simplest application of semaphores is their
application as resource markers for the I DT71342's Dual-Port
RAM. Say the 4K x 8 RAM was to be divided into two 2K x 8
blocks which were to be dedicated at anyone time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of the memory.
To take a resource, in this example the lower 2K of DualPort RAM, the processor on the left port could write and then
read a zero into Semaphore O. If this task were successfully
completed (a zero was read back rather than a one), the left
processor would assume control of the lower 2K. Meanwhile,
the right processor would attempt to perform the same function.
Since this processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
O. At this point, the software could choose to try and gain
control ofthe second 2K section bywriting, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 2K blocks of Dual-Port RAM with each
other.
The blocks do not have to by any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices had determined which memory area was "off limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors
can access their aSSigned RAM segments at full speed.
Another application is in the area of complex data structures.
In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
LPORT
RPORT
SEMAPHORE
REQUEST FLIP FLOP
WRl~: ~L-D
Q
. . m1_Q___ ~
___
SEMAPHORE
READ
rm
SEMAPHORE
REQUEST FLIP FLOP
•
~
D.....
:RITE
SEMAPHORE
READ
2721 drw 14
Figure 3. IDT71342 Semaphore Logic
6.05
12
IDT71342SAILA
CMOS DUAL-PORT RAM 32K (4K
x a-BIT) WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
xxxx
Device Type
_ A_
Power
~
__
A_
Speed
Package
A
Process/
Temperature
Range
~
Blank
J
PF
25
20
35
45
55
70
'---------------------1
Commercial (O°C to
+70°C)
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
I
Speed in nanoseconds
LA
SA
Low Power
Standard Power
71342
32K (4K x a-Bit) Dual-Port RAM w/ Semaphore
2721 drw 15
6.05
13
t;)
IDT7005S/L
HIGH-SPEED
8K X 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001 V
electrostatic discharge
• Battery backup operation-2V data retention
• TTL-compatible, single 5V (±1 0%) power supply
• Available in 68-pin PGA, quad flatpack, and PLCC, and
a 64-pin TQFP
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 25/35/55170ns (max.)
- Commercial:17/20/25/35/55ns (max.)
• Low-power operation
- IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7005L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7005 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• Mis = H for BUSY output flag on Master,
Mis =L for BUSY input on Slave
DESCRIPTION:
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM.
The IDT7005 is designed to be used as a stand-alone 64K-bit
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
FUNCTIONAL BLOCK DIAGRAM
r-r::-[
J
--.J
1
'"
1
~
~
I/00l- 1/07l
~
1/0
Control
1.2)
A12l
:
AOl
NOTES:
1. (MASTER):
BUSY is output ;
(SLAVE): BUSY
is input.
2. BUSY outputs
and INT outputs
are non-tri-stated
push-pull.
SEMl
INT~2
)
Address
Decoder
I
A
~
[
"
A
I/OOR-I/07R
L-.,
,
~r
"v
MEMORY
ARRAY
1/0
Control
13
+
BUSYR (1,2)
A
'"
"I
V
Address
Decoder
CELlOEl}
RiWl:
t
I M~S
Ii t
A12R
AOR
I
13/
-/
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
··
-leER
,-
,O~
IRIWR
SEMR(2)
INTR
2738 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
«:l1995 Integrated Device Technology, Inc.
6.06
APRIL 1995
DSC-104313
1
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Port RAM for 16-bit-or-more word systems. Using the lOT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOS high-performance technol-
PIN CONFIGURATIONS
INDEX
ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500llW from a 2V
battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, an 68pin quad flatpack, a PLCC and a 64-pin thin plastic quad
flatpack, (TOFP). Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
6
8 u ItTIl~ I~ ItTI u u 8 ~ ~ ~ ~ c5 ~ cB
:::::::::: Z 0 c: en U z z > « « « « « « «
"-.9
1/02
1/03
1/04
1/05
GND
1/06
1/07
Vcc
GND
I/OOR
1/01R
1/02R
IDT7005
J68-1
F68-1
PLCC I FLATPACK
TOP VIEW
7005
PN-64
TOFP
TOP VIEW
1/04
1/05
NOTE:
This text does not indicate orientation
of the the actual part-marking.
ASl
A4l
A3l
A2l
All
AOl
INTl
BUSYl
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
II
A4l
A3l
A2l
All
AOl
INTL
BUSYl
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
2738 drw 03
6.06
2
IDTIOOSS/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
51
11
10
52
A7l
55
09
08
07
A11l
59
VCC
61
06
05
02
47
A3l
44
63
SEMl
OEl
45
43
INTl
A1l
II01l
•
/A
Mis
41
40
38
INTR
39
GND BUSYR
36
A1R
37
AOR
A3R
35
A2R
34
A4R
32
56
30
28
58
N/C
26
62
24
64
22
66
20
N/C
1
5
3
2
7
GND
II02l II04l
6
4
II03l II05l
B
9
11
\lO7l GND
10
12
II06l
VCC
IIOOR
II02R
D
E
F
G
C
8
II01R
13
15
VCC II04R
14
16
CER
21
OER
R1WR
18
19
II07R
N/C
17
II03R II05R
H
N/C
23
SEMR
R1Wl
A12R
25
N/C
CEl
A10R
27
GND
68-PIN PGA
TOP VIEW (3)
ASR
29
A11R
IDT7005
G68-1
A12l
A6R
31
A9R
A10l
A5R
33
A7R
ASl
IIOOl
68
42
AOl BUSYl
60
67
03
46
A2l
54
N/C
65
04
A4l
49
A6l
A9l
57
48
50
A5l
53
MILITARY !,ND COMMERCIAL TEMPERATURE RANGES
J
II06R
K
L
INDEX
2738 drw04
PIN NAMES
Right Port
Left Port
CEl
CER
Names
Chip Enable
RNJl
RNJR
ReadNJrite Enable
OEl
OER
Output Enable
AOl- A12l
AOR - A12R
Address
I/OOl - I/07l
I/OOR - I/07R
Data .lnputlOutput
SEMl
SEMR
Semaphore Enable
INTl
INTR
Interrupt Flag
BUSYl
BUSYR
MIS
Busy Flag
Master or Slave Select
Vee
Power
GND
Ground
2738 tbl 01
NOTES:
1. All Vec pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate oriention of the actual part-marking
6.06
3
IDT7005SJL
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
Outputs
Mode
CE
RIW
OE
SEM
UOO-7
H
X
H
High-Z
Deselected: Power-Down
Write to Memory
L
L
X
X
H
DATAIN
L
H
L
H
DATAoUT
X
X
H
X
High-Z
Read Memory
Outputs Disabled
NOTE:
1. AOL -
2738 tbl 02
A12L IS NOT EQUAL TO AOR -
A12R
TRUTH TABLE: SEMAPHORE READIWRITE CONTROl(l)
Inputs
Outputs
CE
RIW
OE
SEM
UOO-7
H
H
L
L
DATAoUT
H
/
X
X
X
L
DATAIN
L
Mode
Read in Semaphore Flag Data Out
Write 1/00 into Semaphore Flag
-
L
Not Allowed
2738 tbl 03
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Terminal Voltage -0.5 to +7.0
with Respect
toGND
Military
Unit
-0.5 to +7.0
V
Military
Commercial
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
louT
DC Output
Current
Grade
50
GND
Vee
-55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
2738 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
50
Ambient
Temperature
mA
NOTES:
2738 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10% maximum, and is limited to::; 20mA for the period of VTERM ~ Vcc
+ 0.5V.
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
-
6.0(2)
V
0.8
V
NOTES:
1. VIL ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
2738 tbl 06
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN= 3dvV
9
pF
COUT
Output
Capacitance
VOUT = 3dvV
10
pF
NOTE:
2738tbl07
1. This parameter is determined by device characterization but is not
production tested. TQFP Package only.
2. 3dv references the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
6.06
4
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V ± 10%)
IDT7005S
Symbol
Parameter
lIul
Input Leakage Current(l)
IILol
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
NOTE:
1. At Vcc
Test Conditions
Min.
=5.5V, VIN =OV to Vee
CE =VIH, VOUT =OV to Vee
IOL =4mA
IOH =-4mA
2.4
Vee
IDT7005L
Max.
Min.
Max.
Unit
5
f.l.A
10
-
5
f.l.A
0.4
-
0.4
V
-
2.4
-
10
V
2738tbl08
=2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc =5.0V ± 10%)
Parameter
Symbol
lee
ISB1
ISB2
CE.$. VIL, Outputs Open
(Both Ports Active)
f
Standby Current
(Both Ports - TTL
CEL CER ~ VIH
SEMR SEML ~ VIH
Level Inputs)
f
=fMAX(3)
=
=
=fMAX(3)
-
-
COM'L.
S
L
170
170
MIL.
S
L
-
-
-
-
-
S
L
25
25
60
50
COM'L.
-
7005X20
7005X25
Com'lOnly
Typ.(2) Max. Typ.(2) Max. Unit
S
L
MIL.
SEM~VIH
310
260
-
155
155
340
280
155
155
265
220
-
16
16
80
65
20
20
60
50
16
16
60
50
160
160
290
240
Standby Current
CE'A'=VIL and CE"B'=VIH(5) MIL.
S
-
-
215
L
-
90
Active Port Outputs Open
-
-
(One Port -
90
180
S
105
190
95
180
90
170
L
105
160
95
150
90
140
S
L
-
-
-
-
1.0
0.2
30
10
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
MIL.
S
-
-
-
-
85
200
L
-
-
-
-
85
170
COM'L.
S
100
170
90
155
85
145
L
100
140
90
130
85
120
TTL
=fMAX(3)
SEMR =SEML> VIH
f
COM'L.
Full Standby Current
(Both Ports - All
Both Ports CEL and
CER ~ Vee - 0.2V
CMOS Level Inputs)
COM'L.
VIN > Vee - 0.2V or
VIN ~ 0.2V, f 0(4)
SEMR SEML> Vee - 0.2V
Full Standby Current
(One Port-All
CE'A' .$. 0.2V and
CER ~ Vee - 0.2v
CMOS Level Inputs)
SEMR
=
ISB4
7005X17
Com'lOnly
Typ.(2) Max.
Version
Dynamic Operating
Current
Level Inputs)
ISB3
Test
Condition
MIL.
=
=SEML ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
VIN.$. 0.2v
Active Port Outputs Open,
f fMAX(3)
=
mA
mA
mA
mA
mA
NOTES:
2738 tbl 09
1. "X" in part numbers indicates power rating (8 or L)
2. Vee 5V. TA +25°C. and are not production tested. Icc DC 120mA (TYP)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions'
of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "8" is the port opposite port "A".
=
=
=
=
6.06
5
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued)
7005X35
Symbol
Icc
ISB1
ISB2
Test
Condition
Typ:(2)
Max.
MIL.
S
L
150
150
300
250
150
150
300
250
140
140
(Both Ports Active)
f = fMAX(3)
COM'L.
S
L
150
150
250
210
150
150
250
210
-
-
Standby Current
(Both Ports - TTL
CEl = CER = VIH
SEMR = SEMl = VIH
MIL.
S
L
13
13
80
65
13
13
80
65
10
10
80
65
Level Inputs)
f = fMAX(3)
COM'L.
S
L
13
13
60
50
13
13
60
50.
-
-
Version
=
Typ.(2) Max.
7005X70
MIL ONLY
Typ.(2) Max. Unit
CE Vll, Outputs Open
SEM = VIH
Parameter
300
250
mA
Standby Current
CE"A"=Vll and CE"B"=Vll(5) MIL.
S
85
190
85
190
80
190
Active Port Outputs Open
f = fMAX(3)
L
85
160
85
160
80
160
S
85
155
85
155
L
85
130
85
130
-
-
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
TTL
COM'L.
MIL.
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vce - 0.2V
CMOS Level Inputs)
COM'L.
VIN ~ VCC - 0.2V or
VIN .s 0.2V, f = 0(4)
SEMR = SEMl > Vcc - 0.2V
S
L
1.0
0.2
15
5
1.0
0.2
15
5
-
-
Full Standby Current
(One Port-All
CMOS Level Inputs)
One Port CE"A' .s 0.2V
CE"B" ~ Vec - 0.2V(5)
S
80
175
80
175
75
175
L
S
80
80
150
135
80
80
150
135
75
150
-
-
L
80
110
80
110
-
-
MIL.
SEMR = SEMl~ Vcc - 0.2V
COM'L.
VIN ~ Vcc - 0.2V or
VIN.s 0.2V
Active Port Outputs Open,
f = fMAX(3)
mA
-
(One Port -
SEMR = SEMl = VIH
ISB4
=S.OV ± 10%)
Dynamic Operating
Current
Level Inputs)
ISB3
(Vcc
7005X55
mA
mA
mA
NOTES:
2738 tbl10
1. 'X' in part numbers indicates power rating (S or L)
2. Vcc 5V, TA = +25°C and are not production tested. Icc DC = 120mA{TVP)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1ItRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the port opposite port "A".
=
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC = 0.2V, VHC = VCC - 0.2V)(4)
Symbol
Parameter
Test Condition
VD~
Vee for Data Retention
Vcc = 2V
ICCDR
Data Retention Current
CE~
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
VIN
~
VHC
VHC or .s VlC
SEM~
Min.
I MIL.
I COM'L.
VHC
Typ..
A'
tHZ (7)
}
tAW
(9)
If
J
tWp(2)
I-tAS (6t
tWR(3)
~t-
RIW
-J
1\
~twz
DATAoUT
J
(7)
tow
(4)
V
1\
I
III
,
J
--~E--JI----tow
DATAIN
(4)
. ' II
tOH
2738 drw09
TIMING WAVEFORM OF WRITE CYCLE NO.2, GE CONTROLLED TIMING(1,5)
,
ADDRESS
twc
~~
JI\
I~
tAW
.1
CEorSEM
(9)
_1AS(S)
1:
...,~
j
tWR(3)~
tEW(2)
\\\
----------iE
____J_l-----tow
DATAN
.1 ..
tOH
2738 drw 10
NOTES:
1. RiWor CE must be high during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a low CE and a low RIW for memory array writing cycle.
3. tWA is measured from the earlier of CE or RIW (or SEM or RiW) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last, CE or RIW.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/. SOOmv from steady state with the Output
Test Load (Figure 2).
8. If OE is low during RIW controlled write cycle, the write pulse width must be the larger oftwP or (twz + tow) to allow the I/O drivers to tum off and data to
be placed on the bus for the required tow. If OE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
9. To access RAM, CE = VIH and SEM = VIL. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.06
10
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao-A2
VALID ADDRESS
DATAo---------~--------+_~
RAN---------~------~
tAOE
Read Cycle ---~
Write Cycle
2738 drw 11
NOTE:
1. CE VIH for the duration of the above timing (both write and read cycle).
=
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
-'X. . _______
AO"A"-A2"A'_'___M_AT_C_H_ _ _
SIDE(2) "A"
SEM"A"
AO"B"-A2"B"
SIDE(2) "B"
SEM"B"
2738 drw 12
NOTES:
1. DOR DOL VIL, CER CEL VIH.
2. All timing is the same for left and rig~ports. Port "A" may be eith~left ~ht port. "B" is the opposite from port "A".
3. This parameter is measured from RfWA or SEMA going High to RfWB or SEMB going High.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
=
=
6.06
11
IDT7005SJL
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT7005X17
Com'lOnlv
Min.
Max.
Parameter
Svmbol
IDT7005X20
Com'lOnlv
Min.
Max.
IDT7005X25
Min.
Max.
Unit
BUSY TIMING (MiS = H)
tBM
BUSY Access Time from Address Match
-
17
tBOA
BUSY Disable Time from Address Not Matched
-
17
-
20
20
-
17
-
17
-
tBAC
BUSY Access Time from Chip Enable
-
17
tBOC
BUSY Disable Time from Chip Enable
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
5
tBOO
BUSY Disable to Valid Data(3)
-
17
-
20
-
-
0
15
-
17
20
20
ns
20
ns
20
ns
17
ns
-
ns
25
ns
-
ns
BUSY TIMING (MIS = L)
tWB
BUSY Input to Write(4)
0
tWH
Write Hold After BUSV(5)
13
0
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(l)
-
30
-
45
-
50
ns
tODD
Write Data Valid to Read Data Delay(1)
-
25
-
35
-
35
ns
Parameter
Svmbol
IDT7005X35
IDT7005X55
Min.
Min.
Max.
Max.
IDT7005X70
MIL ONLY
Min.
Max.
Unit
BUSY TIMING (MIS = H)
20
BUSY Access Time from Chip Enable
-
tBM
BUSY Access Time from Address Match
tBOA
BUSY Disable Time from Address Not Matched
tBAC
20
-
45
-
45
40
-
40
ns
40
40
ns
ns
tBOC
BUSY Disable Time from Chip Enable
-
20
-
35
-
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
5
-
ns
tBOO
BUSY Disable to Valid Data(3)
-
35
-
55
-
70
ns
20
BUSY TIMING (MIS = L)
tWB
BUSY Input to Write(4)
0
-
0
-
0
-
ns
tWH
Write Hold After BUSV(5)
25
-
25
-
25
-
ns
-
80
-
95
ns
80
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(1)
-
60
tODD
Write Data Valid to Read Data Delay(1)
-
45
65
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 8USY".
2. To ensure that the earlier of the two ports wins.
3. t8DD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tODD - tOW (actual).
4. To ensure that the write cycle is inhibited on port "8" during contention with port "A".
5. To ensure that a write cycle is completed on port "8" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
6.06
2738 tbJ 15
12
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY
~ND
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH BUS'«2,5) (MIS
=
VIH)
twc
ADDR"A"
)K
)K
MATCH
twp
~
/'
"
tDW
)
DATAIN"A"
tAPS (1)
ADDR"s"
)
K""
DATAoUT"S"
V
K
tDH
)(
VALID
MATCH
\.
I-- tSDA
"---""
tSDD
/'
/
tWDD
)
tDDD (3)
E
2738 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for Mis= VIL (slave).
2. CEl = CER = VIL
3. OE = VIL for the reading port.
4. If Mis = VIL (slave), then BUSY is an input (BUSY'A" =VIH), and BUSY's" = "don't care", for this example.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
TIMING WAVEFORM OF WITH WRITE BUSY
~------twP------~
RlW-B'
~
'"
Jm.---\....l.-~-----------.Lf'+'.
2
2773388 d
drwrw 114
NOTE:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B" Blocking RIW'B", until BUSY'B" goes High.
6.06
13
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MiS = H)
x=
-------------------------------------------------------
ADDR"A"=X
and "B"
ADDRESSES MATCH
tAPS (2) ~_ _~
'BAC
BUSY"B"
1 ______
WDC=f
2738 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDR"A"
ADDRESS "N"
ADDR"B"
MATCHING ADDRESS "N"
'BM
BUSY"B"
=1___ 1
t_BOA
2738 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from port "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
IDT7005X17
Com'lOnly
Min.
Max.
Parameter
IDT7005X20
Com'lOnly
Min.
Max.
IDT7005X25
Min.
Max.
Unit
INTERRUPT TIMING
-
15
-
15
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
Symbol
Parameter
0
-
0
0
-
0
-
20
-
20
-
IDT7005X35
IDT7005X55
Min.
Min.
Max.
Max.
-
ns
20
ns
20
ns
IDT7005X70
MIL. ONLY
Min.
Max.
ns
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
-
0
-
ns
Write Recovery Time
0
-
0
-
0
tWR
0
-
ns
tiNS
Interrupt Set Time
-
25
-
40
ns
Interrupt Reset Time
-
25
-
40
-
50
tlNR
50
ns
NOTE:
1. "X" in part numbers indicates power rating (8 or L).
2738 tbl16
6.06
14
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~------------------------ twc--------------------~
(2)
INTERRUPT SET ADDRESS
ADDR'A'
tWR
(4)
CE'A'
RiW"A'
INT's'
IINS (3)
1---------------------------2738 drw 17
~---------------------- tRC --------------------~
INTERRUPT CLEAR ADDRESS
ADDR's'
(2)
INT's'
2738 drw 18
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from port "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or RiW) asserted last.
4. Timing depends on which enable signal (CE or RiW) is de-asserted first.
T~UTH
TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Left Port
RrNL
CEL
L
L
X
X
X
Right Port
DEL A12L-AoL INTL
RrNR
CER
X
X
X
X
X
L
L
1FFF
H(3)
X
X
1FFE
X
X
1FFF
X
X
X
X
X
X
X
L(3)
L
L
L
L
1FFE
H(2)
X
X
DER A12R-AoR INTR
L(2)
X
X
NOTES:
1. Assumes 8USYL 8USYR VIH.
2. If BUSYL =VIL, then no change.
3. If 8USYR VIL, then no change.
=
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2738 tb117
=
=
6.06
15
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE II - ADDRESS BUSY
ARBITRATION
Outputs
Inputs
CEl
CER
X
X
AOl-A12l
AOR-A12R
H
X
X
H
NO MATCH
MATCH
MATCH
L
L
MATCH
BUSYl(1)
BUSYR(1)
H
H
Function
Normal
H
H
Normal
H
H
Normal
(2)
(2)
Write Inhibit(3)
NOTES:
2738 tbl18
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDT700S are push-pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the oPPosite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(l)
Functions
00 - 07 Left
Status
00 - 07 Right
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT700S.
2738 tbl19
FUNCTIONAL DESCRIPTION
The IDT7005 provides two ports with separate control,
address and 1/0 pins that permit independent access for reads
or writes to any location in memory. The IDT7005 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE
high). When a port is enabled, access to the entire memory
array is permitted.
the left port writes to memory location 1 FFF (HEX) and to clear
the interrupt flag (INTR), the right port must read the memory
location 1FFF. The message (8 bits) at 1FFE or 1FFF is userdefined, since it is an addressable SRAM location. If the
interrupt function is not used, address locations 1FFE and
1FFF are not used as mail boxes, but as part of the random
access memory. Referto Table I forthe interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (I NTL) is asserted when the right port
writes to memory location 1 FFE (HEX), where a write is
defined as CE = R/W= VIL per the Truth Table. The left port
clears the interrupt through access of address location 1FFE
when CE = OE = VIL. For this example, RIW is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.06
16
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
r---
T
I
MASTER
Dual Port
CE
SLAVE
Dual Port
CE
w
0
0
w
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
c:
()
.BAM..
.BAM..
-
0
'-
1
I
I
MASTER
Dual Port
SLAVE
Dual Port
CE
.BAM..
.BAM..
BUSY (L)
BUSY (L)
BUSY (L) BUSY (R)
I
1
CE
BUSY (R)
I
BUSY (R)
1
I
2738 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the Mis pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintendetl write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 7005 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
initiated with the Rm signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
data in the slave.
SEMAPHORES
The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer's software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
WIDTH EXPANSION WITH BUSY LOGIC
of the right port. Both ports are identical in function to standard
MASTER/SLAVE ARRAYS
CMOS Static RAM and can be read from, or written to, at the
When expanding an IDT7005 RAM array in width while same time with the only possible conflict arising from the
using busy logic, one master part is used to decide which side simultaneous writing of, or a simultaneous READIWRITE of,
of the RAM array will receive a busy indication, and to output a non-semaphore location. Semaphores are protected against
that indication. Any number of slaves to be addressed in the such ambiguous situations and may be used by the system
same address range as the master, use the busy signal as a program to avoid any conflicts in the non-semaphore portion
write inhibit signal. Thus on the IDT7005 RAM the busy pin is of the Dual-Port RAM. These devices have an automatic
an output if the part is used as a master (MIS pin H), and the power-down feature controlled by CE, the Dual-Port RAM
busy pin is an input if the part used as a slave (M/S pin L) as enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
shown in Figure 3.
If two or more master parts were used when expanding in respective port to go into standby mode when not selected.
width, a split decision could result with one master indicating This is the condition which is shown in Truth Table where CE
busy on one side of the array and another master indicating and SEM are both high.
Systems which can best use the IDT7005 contain multiple
busy on one other side of the array. This would inhibit the write.
operations from one port for part of a word and inhibit the write processors or controllers and are typically very high-speed
operations from the other port for the other part of the word. systems which are software controlled or software intensive.
The busy arbitration, on a master, is based on the chip These systems can benefit from a performance increase
enable and address signals only. It ignores whether an access offered by the IDT7005's hardware semaphores, which prois read or write. In a master/slave array, both address and vide a lockout mechanism without requiring complex pro.
chip enable must be valid long enough for a busy flag to be gramming.
Software handshaking between processors offers the
output from the master before the actual write pulse can be
=
=
a
6.06
17
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7005 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
''Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If itwas not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7005 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/VV) as they
would be used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guar~ntee that access to a
resource is secure. As with any powerful programming
6.06
18
IDT700SS/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 4K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT700S's Dual-Port
RAM. Say the 8K x 8 RAM was to be divided into two 4K x 8
blocks which were to be dedicated at anyone time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of memory.
To take a resource, in this example the lower 4K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 4K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore O. At this point, the software could choose to try
and gain control 01 the second 4K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
LPORT
RPORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
WRI~~:I__~ _Q~",,-Q
SEMAPHORE
READ
4
~
Do
rr .
Figure 4. IDT700S Semaphore Logic
6.06
~ WRITE
_D
SEMAPHORE
READ
2738drw 20
19
IDT700SSlL
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
.IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Y:lank
PF
L....-_______--l G
J
F
L....-------------l
17
20
25
35
55
70
IS
'-------------------;1 L
L....---------------------i:
7005
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
64-pin TQFP (PN64-1)
68-pin PGA (<368-1)
68-pin PLCC (J68-i)
68-pin Flatpack (F64-1)
Commercial Only
Commercial Only
}
Speed in nanoseconds
Military Only
Standard Power
Low Power
64K (8K x 8) Dual-Port RAM
2738 drw 21
6.06
20
(;)
IDT7006S/L
HIGH-SPEED
16K X 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
MIS =L for BUSY input on Slave
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001 V
electrostatic discharge
• Battery backup operation-2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 68-pin PGA, quad flatpack, PLCC, and a 64pin TQFP
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 25/35/55170ns (max.)
- Commercial: 17/20/25/35/55ns (max.)
• Low-power operation
- IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7006L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7006 easily expands data bus width to 16 bits or
more using the MasterlSlave select when cascading
more than one device
• MIS = H for BUSY output flag on Master,
DESCRIPTION:
The IDT7006 is a high-speed 16K x 8 Dual-Port Static
FUNCTIONAL BLOCK DIAGRAM
r-r::
\.
j~
I
-
[
]
~
,
I/00l- 1/07l
Control
,~)
··
AOl
NOTES:
1. (MASTER) :
BUSY is
output;
(SLAVE):
BUSY is inp ut.
2. BUSYoutp uts
and INT
outputs are
non-tri-stat ed
push-pull.
SEMl
INT~2
)
Address
Decoder
I
~
,
~
l/L
"-
+
~r
'"
MEMORY
ARRAY
v
'I
~
I--
1/0
A13l
[
14"
Control
+
BUSYR (1,2)
'"
A
v
'I
Address
Decoder
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
f
Ils Ii t
.:
A13R
AOR
I
14
CEl:
OEl:
RiWl:
I/00R-I/07R
1/0
.-
.CER
:O~
IRIWR
SEMR
INTR(2)
2739 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1995 Integrated Device Technology, Inc.
6.07
APRIL 1995
CSC-1044/3
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RAM. The IDT7006 is designed to be used as a stand-alone
128K-bit Dual-Port RAM or as a combination MASTERI
SLAVE Dual-Port RAM for 16-bit-or-more word systems.
Using the I DT MASTERISLAVE Dual-Port RAM approach in
16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
PIN CONFIGURATIONS
~ ~ ~ I~I~ ~ I~ ~ ~ g~ ~ ~ ~ ~ ~ ~
INDEX
1/02
1/03
1/04
1/05
standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capabilitywithtypicaipowerconsumptionof500JlWfroma2V
battery.
The IDT7006 is packaged in a ceramic 68-pin PGA, an 68pin quad flatpack, a PLCC, and a 64-pin thin plastic quad
flatpack, TQFP. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
'"
987654321
A5l
A4l
A3l
A2l
GN
IDT7006
J68-1
F68-1
1/06
1/07
Vc
All
AOl
INTl
BUSYl
GND
PLCC I FLATPACK
TOPVIEW(1)
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
a: 0 a: a: a: a: 0 a: 0 a: a: a: a: a: a: a: a:
~ -IWI~I~IW- M z N ~ 0 m 00 ~ ~ ~
QZOj MIL.
S
-
215
-
-
90
L
-
-
Active Port Outputs Open
80
180
S
105
190
95
180
90
170
L
105
160
95
150
90
140
S
L
-
-
-
-
-
1.0
0.2
30
10
TTL
f
=fMAX(3)
=SEM~ VIH
COM'L.
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ? Vee - 0.2V
CMOS Level Inputs)
VIN ? Vee - 0.2V or
COM'L.
VIN !'> 0.2V, f 0(4)
SEMR SEMl ? Vee - 0.2V
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
CE"A"!,> 0.2V and
CE"B" ? Vee - 0.2V (5)
S
-
-
-
-
85
200
CMOS Level Inputs)
SEMR = SEM ? Vee - 0.2~
COM'L.
VIN ? Vee - 0.2V or
=
MIL.
=
MIL.
mA
mA
(One Port -
SEMR
18B4
-
S
L
Standby Current
Level Inputs)
18B3
-
(VCC= 5.0V± 10%)
7006X20
7006X25
Com'lOnly
Typ.(2) Max. Typ.(2) Max. Unit
mA
mA
L
-
-
-
-
85
S
100
170
90
155
85
170
145
L
100
140
90
130
85
120
mA
VIN!,> 0.2V
Active Port Outputs Open,
f fMAX(3)
=
NUTES:
2739 tbl 09
1. 'X' in part numbers indicates power rating (8 or L)
2. Vcc = 5V, TA = +25°C, and are not production tested. ICC DC =120mA (TYP)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or comtrollines change.
5. Port "A" may be either left of right port. Port "8" is the opposite from port "A".
6.07
5
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued)
7006X35
Parameter
Symbol
lee
1891
1892
Test
Condition
Typ.(2)
Max.
=S.OV ± 10%)
7006X70
MIL ONLY
Typ.(2) Max. Typ.(2) Max. Unit
Dynamic Operating
Current
CE = Vll, Outputs Open
SEM = VIH
MIL.
S
L
150
150
300
250
150
150
300
250
140
140
(Both Ports Active)
f = fMAX(3)
COM'L.
S
L
150
150
250
210
150
150
250
210
-
S
L
13
13
80
65
13
13
S
L
13
13
60
50
Standby Current
(Both Ports - TTL
CEl = CER = VIH
SEMR = SEMl = VIH
Level Inputs)
f = fMAX(3)
MIL.
·COM'l,
-
-
80
65
10
10
80
65
13
13
60
50.
-
-
mA
Standby Current
CE"A"=Vll and CEl"9"=VIH(b) MIL.
S
85
190
85
190
80
190
Active Port Outputs Open,
f = fMAX(3)
l,;UM'L.
L
85
160
85
160
80
160
S
85
155
85
155
-
SEMR = SEMl = VIH
L
85
130
85
130
-
-
TTL
mA
300
250
(One Port Level Inputs)
1893
Version
(Vcc
7006X55
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ?: Vee - 0.2V
MIL.
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
CMOS Level Inputs)
VIN ?: Vee - 0.2V or
VIN.$ 0.2V, f = 0(4)
COM'L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
-
-
CE"A" < 0.2V and
CE"B" ; Vee - 0.2V(5)
MIL.
S
80
175
80
175
75
175
L
S
80
80
150
135
80
80
150
135
75
150
-
-
L
80
110
80
110
-
-
mA
mA
SEMR = SEML?: Vee - 0.2\
1894
Full Standby Current
(One Port-All
CMOS Level Inputs)
SEMR = SEML?: Vee - 0.2V
COM'L.
VIN ?: Vee - 0.2V or
VIN .$ 0.2V
Active Port Outputs Open,
f = fMAX(3)
NUIt:~:
mA
2739 tbll0
1. 'X' in part numbers indicates power rating (S or L)
2. Vcc = 5V, TA +25°C, and are not production tested. Icc DC =120ma (TYP)
3. At f fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or comtrollines change.
5. Port "A" may be either left or right port. Port "8"is the opposite from port "A".
=
=
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC
=0.2V, VHC = VCC - 0.2V)(4)
Symbol
Parameter
Test Condition
VDR
Vee for Data Retention
Vee = 2V
leeDR
Data Retention Current
CE?:VHe
2.0
I MIL.
I COM'L.
VIN ?: VHe or :;:; Vle
teDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
SEM ?:VHe
DATA RETENTION WAVEFORM
f
teDR
:£=
j j--r"j.,-rjj~/r+r-VIH~\
CE -rZZ"T""'7
_
-
Max.
Unit
-
100
4000
-
100
1500
0
-
V
IlA
-
ns
-
ns
2739 tblll
=
4.5V
Typ.(1)
-
tRd 2)
NOTES:
1. TA =+25°C, Vcc =2V, and are not production tested.
2. tRC Read Cycle Time
3. This parameter is guaranteed but not tested.
4. At Vcc =2V input leakages are undefined
Vee
Min.
DATA RETENTION MODE
VDR?: 2V
:e
_
4.5V
tR==:L
/r---~-rl-HHt'T""'T\\""'r"'"\'T""'T\\""'r"'"\'T""'T\\""'r"'"\-r-c\\---.-\~\
VDR
2739 drw 05
6.07
6
IDT7006SIL
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
DATAoUT
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
~ ~
5V1250n
AC TEST CONDITIONS
1250n
DATAoUT
BUSY
INT
See Figures 1 & 2
5V
775n
775n
30pF
5pF
2739 tbl12
Figure 1. AC Output Test
Load
Figure 2. Output Load
(5pF for tLZ, tHZ, twz, tow)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
Symbol
IDT7006X17
Com'lOnly
Min.
Max.
Parameter
IDT7006X20
Com'lOnly
Min.
Max.
IDT7006X25
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
17
-
20
-
25
-
ns
tM
Address Access Time
17
-
25
ns
Chip Enable Access Time(3)
20
-
25
ns
tAOE
Output Enable Access Time
-
20
tACE
-
12
-
13
ns
tOH
Output Hold from Address Change
3
3
-
ns
Output Low-Z Time(l, 2)
3
3
-
3
tLZ
-
3
-
ns
tHZ
Output High-Z Time(1, 2)
-
10
-
12
-
15
ns
tpu
Chip ~nable to Power Up Time\~)
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
17
-
20
-
25
ns
tsop
Semaphore Flag Update Pulse (OE or SEM)
10
-
10
-
10
-
ns
tSM
Semaphore Address Access Time
-
17
-
20
-
25
ns
17
10
IDT7006X35
Parameter
Symbol
Min.
Max.
IDT7006X55
Min.
Max.
IDT7006X70
MIL ONLY
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
-
55
-
70
-
ns
tM
Address Access Time
-
35
55
-
70
ns
tACE
Chip Enable Access Time(3)
-
35
55
-
70
ns
tAOE
Output Enable Access Time
-
20
-
30
-
35
ns
tOH
Output Hold from Address Change
3
-
3
3
Output Low-Z Time\l,~)
3
-
3
3
-
ns
tLZ
-
tHZ
Output High-Z Time(1, 2)
-
15
-
25
-
30
ns
tpu
Chip Enable to Power Up Time\~)
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
35
-
50
-
50
ns
tsop
Semaphore Flag Update Pulse (OE or SEM)
15
-
15
-
15
-
ns
tSM
Semaphore Address Access Time
-
35
-
55
-
70
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL and SEM VIH. To access semaphore, CE VIH and SEM VIL
4. 'X' in part numbers indicates power rating (S or L).
=
=
=
6.07
ns
ns
2739 tbl13
=
7
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
ADDR
tRC
\1
J\.
I\ I
tAA (4)
\ \ \ \1.--
/1111
tACE (4)
I
J - - - tAOE (4)
\\\:
/111
I
RNi
DATAoUT
I
I
! . - - tLZ (1)
-it
I
-tOH'-+j
1\X'I
J\.
VALID DATA (4)
tHZ(2)
~~
I
BUSYOUT
\\\\\\\~
-tBDD(3,4)
2739 drw 0
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBOO delay is required only in cases where the opposite port is completing a write operation tothe same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBOO.
5. SEM =VIH.
TIMING OF POWER-UP POWER-DOWN
2739 drw 08
6.07
8
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
Symbol
IDT7006X17
Com'IOnly_
Max.
Min.
Parameter
IDT7006X20
Com'lOnly
Max.
Min.
J
IDT7006X25
I
Max.
Unit
ns
20
-
0
-
ns
20
-
ns
Min.
WRITE CYCLE
twc
Write Cycle Time
17
-
20
-
25
tEW
Chip Enable to End-of-Write(3)
12
-
15
20
tAW
Address Valid to End-of-Write
12
15
tAS
Address Set-up Time(3)
0
twp
Write Pulse Width
12
tWR
Write Recovery Time
0
tow
Data Valid to End-of-Write
10
-
-
tHZ
Output High-Z Time(1, 2)
-
10
-
12
-
15
ns
tOH
Data Hold Time(4)
0
-
0
-
0
-
ns
twz
Write Enable to Output in High-Z(1, 2)
-
10
-
12
-
15
ns
tow
Output Active from End-of-Write(1, 2, 4)
0
0
-
0
SEM Flag Write to Read Time
5
5
-
5
tsps
SEM Flag Contention Window
5
5
-
5
-
ns
tSWRO
-
Symbol
Parameter
0
15
0
15
IDT7006X35
IDT7006X55
Min.
Max.
Min.
-
I
Max.
0
15
IDT7006X70
MIL. ONLY
Min.
Max.
ns
ns
ns
ns
ns
ns
Unit
WRITE CYCLE
55
-
70
-
ns
45
-
50
ns
45
50
30
-
40
-
15
-
25
-
30
ns
0
-
0
-
0
-
ns
Write Enable to Output in High-Z(1, 2)
-
15
-
25
-
30
ns
tow
Output Active from End-of-Write(1, 2, 4)
0
0
5
5
5
tsps
SEM Flag Contention Window
5
5
-
5
-
ns
SEM Flag Write to Read Time
-
0
tSWRD
-
twc
Write Cycle Time
35
tEW
Chip Enable to End-of-Write(3)
30
tAW
Address Valid to End-of-Write
30
tAS
Address Set-up Time(3)
0
twp
Write Pulse Width
25
tWR
Write Recovery Time
0
-
0
tow
Data Valid to End-of-Write
15
-
tHZ
Output High-Z Time(1, 2)
-
tOH
Data Hold Time(4)
twz
0
40
0
50
0
ns
ns
ns
ns
ns
ns
ns
NOTES:
2739 tbl14
1. Transition is measured ±SOOmV from low or high impedance voltage with load (Figures 2).
2. This parameter is guaranteed by device characterization, but is not production tested but not tested.
3. To access RAM, CE L, 8EM H. To access semaphore, CE Hand 8EM L. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. 'X' in part numbers indicates power rating (8 or L).
=
=
=
=
6.07
9
IDT7006S/L
HIGH·SPEED 16K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING(1,5,8)
twc
~~
~~
Ir-...
ADDRESS
1\
tHZ (7)
j
OE
tAW
(9)
twp (2)
:+--tAS (6\
tWR(3)
~'l
~[1\
RIW
J
f+--twz~
DATAoUT
tow~
\I
(4)
~
.'.
f\
(4)
\
J
---iF
___________]J---tow
DATAIN
tOH
2739 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,5)
twc
~~
ADDRESS
~~
1\
11\
tAW
CEorSEM
(9)
_tAS(6)
}
-J.
J
tWR(3) __
tEW(2)
\\\
RtW
-------rF_ _]l----.. I.
tow
DATAN
tOH
2739 drw 10
NOTES:
1. Rm or CE must be high during all address transitions.
2.
3.
4.
5.
6.
7.
8.
9.
A write occurs during the overlap (tEW or twp) of a low CE and a low R/W for memory array writing cycle.
tWR is measured from the earlier of CE or RNV (or SEM or RNV) going high to the end of write cycle.
During this period, the 1/0 pins are in the output state and input signals must not be applied.
If the CE or SEM low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
Timing depends on which enable signal is asserted last, CE or Rm.
This parameter is guaranteed by device characterization, but is not production tested. Transition is measured by +1- 500mV from steady state with the
Output Test Load (Figure 2)
If OE is low during R!W controlled write cycle, the write pulse width must be the larger of twp or (twz + tDW) to allow the 1/0 drivers to turn off and data to
be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
To access RAM, CE VIL and SEM
VIH. To access semaphore CE VIH and SEM
VIL. tEW must be met for either condition.
=
=
=
6.07
=
10
IDT7006S1L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao-A2
VALID ADDRESS
DATAo------~~------~~
RAN------~------,
tADE
Write Cycle
Read Cycle
2739 drw 11
NOTE:
1. CE VIH for the duration of the above timing (both write and read cycle).
=
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
X'---_____________
AO"A"-A2"A'_'_____M
__
A_TC
__
H_ _ _ _
SIDE(2) "A"
SEM"A"
------------
AO"B"-A2"B"
SIDE(2) liS"
NOTES:
1. DOR DOL VIL, CER CEL VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and rig~ports. Port "An may be either ~ft or ri~ort. Port "8" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going High to RlW"B" or SEM"B" going High.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
=
=
6"07
11
IDTI006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
IDT7006X17
Com'l_Onlv
Min.
Max.
Parameter
IDT7006X20
Com'l Onlv
Min.
Max.
IDT7006X25
Min.
Max.
Unit
20
20
20
ns
17
ns
BUSY TIMING (MIS = H)
17
17
17
-
20
20
20
BUSY Disable Time from Chip Enable HIGH
-
17
-
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
5
-
ns
taDD
BUSY Disable to Valid Data(3)
-
17
-
20
-
25
ns
-
a
-
ns
17
-
ns
taAA
BUSY Access Time from Address Match
taDA
BUSY Disable Time from Address Not Matched
taAc
BUSY Access Time from Chip Enable LOW
taDc
17
ns
ns
BUSY TIMING (MIS = L)
twa
BUSY Input to Write(4)
a
-
a
tWH
Write Hold After BUS'(5)
13
-
15
-
30
-
45
-
50
ns
25
-
30
-
35
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(l)
tDDD
Write Data Valid to Read Data Delay(1)
Symbol
Parameter
BUSY TIMING (MIS
IDT7006X35
IDT7006X55
Min.
Min.
Max.
Unit
=H)
-
45
40
40
35
ns
-
45
40
40
35
-
5
-
5
-
ns
-
35
-
55
-
70
ns
a
-
a
-
ns
25
25
-
ns
-
95
ns
80
ns
BUSY Disable Time from Chip Enable HIGH
-
20
20
20
20
tAPS
Arbitration Priority Set-up Time(2)
5
taDD
BUSY Disable to Valid Data(3)
taAA
BUSY Access Time from Address Match
taDA
BUSY Disable Time from Address Not Matched
taAc
BUSY Access Time from Chip Enable LOW
taDc
BUSY TIMING (MIS
Max.
IDT7006X70
MIL. ONLY
Min.
Max.
-
ns
ns
ns
=L)
twa
BUSY Input to Write\'1J
a
tWH
Write Hold After BUSy(5)
25
-
-
45
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(l)
tDDD
Write Data Valid to Read Data Delay(1)
60
-
80
65
NOTES:
2739 tbl15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 8USY".
2. To ensure that the earlier of the two ports wins.
3. t8DD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual).
4. To ensure that the write cycle is inhibited with port "8" during contention on port "A".
5. To ensure that a write cycle is completed on port "8" after contention with port "A".
6. "X" is part numbers indicates power rating (S or L).
6.07
12
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUS'«2,5) (MIS = VIH)
twc
ADDR"A"
)(
)
MATCH
~
twp
,
/
K
V
tow
)K
DATAIN"A"
tAPS (1)
) K~
ADDR"B"
)K
VALID
MATCH
\
BUSY"B"
tOH
r-- tBOA
"'--",
tBOO
/ k'
twoo
)
DATAoUT"B"
toDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for-MIS = VIL (SLAVE).
2. CEL CER VIL
3. OE ViL for the reading port.
4. If MIS VIL(slave) then BUSY is input (BUSY'A' VIH and BUSY'B' "don't care", for this example.
5. All timing is the san:)e for left and right port. Port "A' may be either left or right port. Port "8" is the port opposite from Port "A".
=
=
E
2739 dlW 13
=
=
=
=
TIMING WAVEFORM OF WRITE WITH BUSY
~------twP------~
RlW-B"
~
'"
lw
------------""'~'I-'
2739dIW 14
2
NOTES:
1. tWH must be met for both 8USY input (sla~) and output (master).
2. 8USY is asserted on Port "8" Blocking R/W"B", until BUSY"B" goes High.
6.07
13
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY GE TIMING(1) (Mig
A~~~:~: ____-J:><:~
=H)
__________________
:><:~
A_D_D_R
__
ES_S_E_S__
M_A_T_C_H_____________________
_____
CE"A"
tAPS (2) ~_ _~
BUSY"B"
2739 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/g = H)
)K"'--______~--A--D-D-R-E-S-S-"N-'-'_________)K____________________________
ADDR"A" ____
tAPS (2)
ADDR"B"
)(
----------
MATCHING ADDRESS "N"
_tBAA
={
~tBDA}
BUSY"B"
2739 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
IDT7006X17
Com'lOnlv
Min.
Max.
Parameter
IDT7006X20
Com'lOnlv
Min.
Max.
IDT7006X25
Min.
Max.
Unit
-
0
-
ns
20
-
20
ns
20
ns
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
Symbol
Parameter
-
0
15
-
15
0
20
IDT7006X35
IDT7006X55
Min.
Min.
Max.
-
Max.
0
IDT7006X70
MIL. ONLY
Max.
Min.
ns
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
-
0
tWR
Write Recovery Time
0
-
0
tiNS
Interrupt Set Time
25
tlNR
Interrupt Reset Time
-
-
NOTE:
1. "X" in part numbers indicates power rating (S or L).
25
40
40
0
0
-
-
ns
ns
50
ns
50
ns
2739tbJ 16
6.07
14
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~---------------------- twc--------------------~
(2)
INTERRUPT SET ADDRESS
ADDR"A"
CE"A"
INT"B"
2739 drw 17
~--------------------- tRC -------------------~
INTERRUPT CLEAR ADDRESS
ADDR"B"
(2)
tAS (3)
OE"B"
1
--l ,-----------------------------------------------------
...?\'
__________________
tl_NR
__
(3_
INT"B" _
2739 drw 18
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from port "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or RIW) is asserted last.
4. Timing depends on which enable signal (CE or RIW) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I--INTERRUPT FLAG(1)
Right Port
Left Port
RIWL
CEL
L
L
X
X
X
X
X
L
OEl A13l-Aol INTl
X
X
CER
X
X
X
L
L
1FFF
H(3)
X
X
1FFE
X
X
X
X
X
X
X
L(3)
L
L
L
1FFE
H(2)
X
X
1FFF
OER A13R-AoR INTR
L(2)
X
X
RIWR
NOTES:
1. Assumes 8USYL = BUSYR = VIH.
2. If 8USYL = Vll, then no change.
3. If BUSYR = VIL, then no change.
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTl Flag
Reset Left INTl Flag
2739 tbl17
6.07
15
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
TRUTH TABLE II ARBITRATION
Inputs
CEL
X
H
X
L
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ADDRESS BUSY
Outputs
AOL-A13L
Function
CER AOR-A13R BUSYL(1) BUSYR(1)
Normal
H
H
X NO MATCH
Normal
MATCH
H
X
H
MATCH
Normal
H
H
H
Write Inhibit{3j
MATCH
(2)
(2)
L
NOTES:
2739 tbl18
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDn006 are push pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR =Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Do - 07 Right
Functions
Do - 07 Left
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
1
1
0
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
0
1
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
1
0
1
0
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
0
1
1
1
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
1
0
1
1
Right port has semaphore token
Semaphore free
LeftPortWrites "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDn006.
I
2739 tbl19
FUNCTIONAL DESCRIPTION
The IDT7006 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7006 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
writes to memory location 3FFF (HEX) and to clear the
interrupt flag (INTR), the right port must read the memory
location 3FFF. The message (8 bits) at 3FFE or 3FFF is userdefined, since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random
access memory. Refer to Table 1 forthe interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (I NTL) is asserted when the right port
writes to memory location 3FFE (HEX) where a write is
defined as CE = Rm = VIL per the Truth Table. The left port
clears the interrupt by reading address location 3FFE access
when CER =OER =VIL, RIW is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.07
16
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
roo--
MASTER
Dual Port
T
I
CE
SLAVE
Dual Port
.BAM...
CE
0
u
w
.BAM...
BUSY (L) BUSY (R)
cr:
r- W
Cl
BUSY (L) BUSY (R)
Cl
'-
1
MASTER
Dual Port
SLAVE
Dual Port
CE
.BAM...
BUSY (L)
BUSY (L) BUSY (R)
1
CE
.BAM...
BUSY (L) BUSY(R)
BUSY (R)
I
2739 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7006 RAMs.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 7006 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7006 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAMs array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7006 RAM the busy pin is
an output if the part is used as a master (MIS pin =H), and the
busy pin is an input if the part used as a slave (MIS pin =L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
6.07
initiated with the Rm signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
data in the slave.
SEMAPHORES
The IDT7006 is an extremely fast Dual-Port 16K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer's software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simUltaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT7006 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7006s hardware semaphores, which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
17
IDTI006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
to be allocated in varying configurations. The IDT7006 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is release.d when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7006 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AD -A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
l0.oking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
6.07
18
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7006's Dual-Port
RAM. Say the 16K x B RAM was to be divided into two BK x
B blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower BK of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore o. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower BK. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
o. At this point, the software could choose to try and gain
control of the second BK section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap BK blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the 1/0 device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the 1/0 devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
LPORT
RPORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
t
WRI~~=1L.D_ _a ~L-Q
_ _D
.....
SEMAPHORE.
READ
~~
~ORITE
• SEMAPHORE
READ
2739 drw 20
Figure 4. IDT7006 Semaphore Logic
6.07
19
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Y:lank
PF
G
L-----------------~J
F
~----------------------~
~
17
20
25
35
55
70
____________________~Is
IL
L-______________________________________
~:
7006
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
64-pin
68-pin
68-pin
68-pin
TQFP (PN64-1)
PGA (G68-1)
PLCC (J68-i)
Flatpack (F64-1)
Commercial onlY}
Commercial Only
Speed in Nanoseconds
Military Only
Standard Power
Low Power
128K (16K x 8) Dual-Port RAM
2739 drw 21
6.07
20
G
HIGH-SPEED
32K X 8 DUAL-PORT
STATIC RAM
IDT7007S/L
Integrated Device Technology, Inc.
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 25/35/55ns (max.)
- Commercial: 20/25/35/55ns (max.)
• Low-power operation
- IDT7007S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7007L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7007 easily expands data bus width to 16 bits or
•
•
•
•
•
•
•
•
•
more using the Master/Slave select when cascading
more than one device
Mis =H for BUSY output flag on Master,
Mis = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001 V
electrostatic discharge
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA and PLCC and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
r-L..
J~
---..J
1
'--....
[
]
~
4{
I/00l- 1/07 l
~
1/0
+
,2)
··
A14l
AOl
Address
Decoder
I
'"
A
~
1/0
Control
+
'v"
'\j
15,
15,
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEq
OEl!
t
IM~sll
··
Address
Decoder
A14R
AOR
I
~CER
OER
IRmR
Rml!
)
BUSYR (1,2)
A
MEMORY
ARRAY
v
1I00R-I/07R
L...,..
~r
Control
t
SEMR(2)
INTR
2940 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
<01995 Integrated Dev!ce Techno!ogy. Inc.
6.08
APRIL 1995
DSC-1083f2
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7007 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT7007 is designed to be used as a stand-alone
256K-bit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 16-bit-or-more word systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in
16-bit or wider memory system applications results in fu"speed, error-free operation without the need for additional
discrete loglc.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using I DT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin
PlCC, and a 80-pin thin plastic quad flatpack, TQFP. Military
grade product is manufactured in compliance with the latest
revision of Mll-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level
of performance and reliability.
PIN CONFIGURATIONS
I/02L
A5L
I
I/03L
59
A4L
I/04l
58
A3l
I/05l
57
A2l
GND
56
A1l
I/06l
IDT7007
55
AOL
J68-1
54
INTL
VCC
GND
PLCC
TOP VIEW(1)
53
BUSYl
52
GND
51
Mis
I/01R
50
BUSYR
I/02R
49
INTR
Vee
48
AOR
I/03R
47
A1R
I/04R
46
I/OOR
A2R
I/05R
A3R
I/06R
A4R
-IW
W
a: 0 a: a: a: a: a: a: 0 a: a: a: a: a: a: a: a:
f'
I~ I~ I ~
z C\I
0
0)
ex> f'
LO
O
~ZO~~O~~~~~~~~~~~
('I)
T"-
(0
2940 d
02
rw
NOTE:
1. This text does not indicate orientation of the actual part marking.
6.08
2
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Continued)
N/C
N/C
I/02L
I/03L
I/04L
I/05L
GND
I/06L
I/07L
59
58
57
56
7007
PN80-1
Vee
N/C
TQFP
TOP VIEW(1)
GND
I/OOR
I/01R
I/02R
55
54
53
52
51
50
49
48
47
Vee
46
I/03R
I/04R
I/05R
I/06R
45
44
43
N/C
42
20
41
~N~~~ID~romo~N~~~ID~rom~
A5L
A4L
A3L
A2L
A1L
AOL
INTL
BUSYL
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
N/C
N/C
2940 drw03
NOTE:
1. This text does not indicate orientation of the actual part-marking.
6.08
3
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
51
11
10
09
55
A11l
59
vee
61
06
05
63
65
OEl
67
02
45
43
INTl
A1l
If01l
•
/A
Mis
41
GND BUSYF
40
INTR
39
AOR
38
36
A1R
37
A3R
35
A2R
A4R
32
A7R
ASl
56
30
A9R
A10l
58
28
A11R
IDT7007
G68-1
A12l
A13l
26
GND
68-PIN PG.A!3)
TOP VIEW
62
24
A14R
CEl
64
22
SEMR
RIWl
66
IfOOl
68
42
54
SEMl
03
47
A3l
44
AOl BUSYl
60
A14l
04
46
A2l
49
A6l
A9l
57
48
A4l
52
A7l
08
07
50
ASl
53
MILITARY AND COMMERCIAL TEMPERATURE RANGES
20
3
GND
If02l If04l
2
4
C
9
11
If07L GND
8
If01R
10
12
I/06l
vee
I/OOR
I/02R
D
E
F
G
6
If03l I/OSl
B
7
5
13
vee
14
A6R
31
ASR
29
A10R
27
A12R
25
A13R
23
CER
21
RlWR
15
18
19
If04R
If07R
16
NfC
17
I/03R I/OSR
H
ASR
33
OER
NfC
1
34
J
I/06R
K
L
INDEX
2940drw 04
PIN NAMES
Left Port
Right Port
CEl
CER
Names
Chip Enable
RIWL
RlWR
Read/Write Enable
OEl
OER
Output Enable
AOl-A14l
AOR - A14R
Address
I/OOl - I/07L
I/OOR - I/07R
Data InpuVOutput
SEMl
SEMR
Semaphore Enable
INTl
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
2940 tbl 01
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part marking.
6.08
4
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
Outputs
CE
RIW
OE
SEM
1100-7
H
X
H
High-Z
Deselected: Power-Down
Write to Memory
Mode
L
L
X
X
H
DATAIN
L
H
L
H
DATAoUT
X
X
H
X
High-Z
NOTE:
1. AOL -
Read Memory
Outputs Disabled
2940 tbl 02
A14L
¢
AOA -
A14A
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL(1)
Inputs
Outputs
CE
RIW
OE
SEM
1100-7
H
H
L
L
DATAoUT
Read Semaphore Flag Data Out
H
.f
DATAIN
Write 1/00 into Semaphore Flag
X
X
X
L
L
Mode
-
L
Not Allowed
2940 tbl 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Terminal Voltage -0.5 to +7.0
with Respect
toGND
Military
Unit
-0.5 to +7.0
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
Commercial
Ambient
Temperature
GND
Vee
-55°C to + 125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V± 10%
2940 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTE:
2940 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTEAM must not exceed Vcc + O.5V for more than 25% of the cycle time
or 1Ons maximum, and is limited to!S 20mA for the period of VTEAM ~ Vcc
+O.5V.
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6.0(2)
V
Input Low Voltage
-0.5(1)
-
0.8
V
VIL
Parameter
NOTES:
2940 tbl 06
1. VIL~ -1.5V for pulse width less than 10ns.
2. VTEAM must not exceed Vcc + O.5V.
CAPACITANCE (TA =+25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
9
pF
COUT
Output
Capacitance
VOUT= 3dV
10
pF
NOTE:
2940 tbl 07
1. This parameter is determined by device characterization but is not
production tested. TQFP package only.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
6.08
5
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc =5.0V ± 10%)
IDT7007S
Parameter
Symbol
Test Conditions
Min.
IOL= 4mA
-
IOH =-4mA
2.4
lIul
Input Leakage Current(1)
Vee = 5.5V, VIN = OV to Vee
IILOI
Output Leakage Current
CE = VIH, VOUT = OV to Vee
VOL
Output Low Voltage
VOH
Output High Voltage
IDT7007L
Max.
Min.
Max.
Unit
5
~A
5
~A
0.4
V
0.4
-
-
2.4
-
10
10
NOTE:
1. At Vcc
V
2940 tbl 08
=2.0V, input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc = 5.0V ± 10%
7007X25
7007X20
COM'LONLY
Typ.(2) Max. Typ.(2) Max. Unit
Test
Symbol
lee
ISB1
ISB2
Condition
Parameter
Version
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
Standby Current
(Both Ports - TTL
Level Inputs)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L.
=VIL and CE'B' =VIH(5)
CE'A'
(One Port -
Active Port Outputs Open,
Level Inputs)
COM'L.
MIL.
Standby Current
TTL
MIL.
f = fMAX(3)
MIL.
COM'L.
SEMR = SEML = VIH
ISB3
ISB4
315
275
170
345
17n
~nc;
170
170
305
265
25
25
25
25
100
80
85
60
rnA
105
230
mA
105
200
-
-
30
30
85
60
S
-
L
-
-
S
115
210
105
200
L
115
180
105
170
1.0
0.2
30
10
S
L
S
L
-
COM'L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
MIL.
S
L
-
-
100
100
200
175
COM'L.
S
110
185
100
170
L
110
160
100
145
MIL.
CMOS Level Inputs)
VIN > Vee - 0.2V or
VIN ~ 0.2V, f = 0(4)
SEMR = SEML > Vee - 0.2V
Full Standby Current
(One Port-All
CE'A' < 0.2V and
CE"B' ~ Vee - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML ~ Vee - 0.2V
NOTES:
180
180
-
-
Both Ports CEL and
CER ~ Vee - 0.2V
VIN ~ Vee - 0.2V or VIN ~ 0.2V
-
S
L
Full Standby Current
(Both Ports - All
Active Port Outputs Open,
f = fMAX(3)
S
I
S
L
-
rnA
mA
rnA
2940 tbl 09
1. "X" in part numbers indicates power rating (8 or L)
2. Vee = 5V, TA = +25°C, and are not production tested. leeDC = 120mA (Typ.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC. and using "AC Test Conditions"
of input levels of GND to 3V.
4. f =0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
6.08
6
IDT7007S/L
HIGH·SPEED 32K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued) (Vcc =5.0V ± 10%)
7007X35
Symbol
lee
ISB1
ISB2
Test
Condition
Parameter
Version
=
=
Dynamic Operating
Current
CE Vll, Outputs Open
SEM VIH
(Both Ports Active)
f
Standby Current
(Both Ports - TIL
CEl CER VIH
SEMR SEMl VIH
Level Inputs)
f
S
L
-
COM'L.
S
L
160
160
MIL.
S
L
COM'L.
MIL.
MIL.
=fMAX(3)
= =
=
=
=fMAX(3)
=Vil and CE"B" =VIH(5)
Standby Current
CE"A"
(One Port-TIL
Active Port Outputs Open,
Level Inputs)
f
COM'L.
SEMR
ISB3
150
150
310
270
295
255
150
150
270
230
-
100
80
13
13
100
80
S
L
20
20
85
60
13
13
85
60
S
-
215
85
195
185
85
165
S
95
185
85
165
L
95
155
85
135
-
mA
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee· 0.2V
MIL.
S
L
-
30
10
1.0
0.2
30
10
CMOS Level Inputs)
VIN > Vee· 0.2V or
VIN :;; 0.2V, f 0(4)
SEMR SEMl > Vee· 0.2V
COM'L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
CE"A" < 0.2V and
CE"B" ; Vee· 0.2V(5)CER
MIL.
S
L
-
190
165
80
80
165
140
S
90
160
80
135
L
90
135
80
110
=
ISB4
Max. Typ.(2) Max. ~nit
335
295
L
=fMAX(3)
=SEMl =VIH
Typ.(2)
7007X55
CMOS Level Inputs)
SEMR
=
~ Vee· 0.2V
-
mA
mA
mA
mA
=SEMl ~ Vee· 0.2V
VIN ~ Vee· 0.2V or
COM'L.
VIN ~ 0.2V
Active Port Outputs Open,
f fMAX(3)
=
NOTES:
1. "X" in part numbers indicates power rating (8 or L)
2. Vec 5V, TA = +25°C, and are not production tested. leeDe 120mA (Typ.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 11 tRC, and using
"AC Test Conditions" of input levels of GND to 3V.
4. f a means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
=
2940 tbl10
=
=
6.08
7
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns Max.
DATAoUT
1.5V
1.5V
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAoUT--......--+-_
BUSY---.---+---.
INT
347n
30pF
347n
See Figures 1 & 2
5pF
2940 tblll
2940 drw 05
2940 drw 06
Figure 1. AC Output Load
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
Symbol
IDT7007X20
COM'LONLY
Min.
Max.
Parameter
IDT7007X25
Min.
Max.
Unit
-
25
-
ns
20
20
12
-
ns
-
3
25
25
13
-
3
-
ns
12
-
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
20
-
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(1, 2)
tHZ
Output High-Z Time(1, 2)
3
-
tpu
Chip Enable to Power Up Time(2)
tPD
Chip Disable to Power Down Time(2)
tsop
tSAA
-
-
ns
ns
ns
-
0
20
-
25
ns
Semaphore Flag Update Pulse (OE or SEM)
0
10
15
-
-
12
-
ns
Semaphore Address Access Time
-
20
-
25
ns
IDT7007X35
Symbol
Parameter
ns
IDT7007X55
Min.
Max.
Min.
35
35
20
-
Max.
Unit
55
-
ns
-
55
55
ns
30
ns
3
3
-
-
ns
25
ns
ns
READ CYCLE
tRG
Read Cycle Time
35
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1, 2)
3
3
tHZ
Output High-Z Time(l, 2)
-
tpu
Chip Enable to Power Up Time(2)
0
tPD
Chip Disable to Power Down Time(2)
tsop
tSAA
-
ns
ns
0
-
-
15
35
-
50
ns
Semaphore Flag Update Pulse (OE or SEM)
15
-
15
-
ns
Semaphore Address Access Time
-
35
-
55
NOTES:
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed b~vice characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
6.08
ns
2940 tbl12
8
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
~------------------ tRC --------------------~
ADDR
Rm
VALID DATA4)
DATAoUT------------------------~
BUSYOUT
tBDD(3,4)
2940 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBOO delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBOO.
5. SEM =VIH.
TIMING OF POWER-UP POWER-DOWN
r
eEl
: : ~ tpu1-l-tp0=t2940 drw08
S.08
9
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
Symbol
IDT7007X20
COM'L ONLY
Min.
Max
Parameter
IDT7007X25
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWA
Write Recovery Time
tow
Data Valid to End-of-Write
20
15
15
0
15
0
15
tHZ
Output High-Z Time(1· 2)
tOH
Data Hold Time(4)
twz
Write Enable to Output in High-Z(1· 2)
tow
Output Active from End-of-Write(1· 2. 4)
tSWRO
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
-
-
ns
ns
-
-
-
12
-
15
ns
-
-
ns
ns
ns
ns
0
-
0
-
ns
12
-
15
ns
0
5
5
-
0
5
5
-
ns
-
Min.
Parameter
ns
-
IDT7007X35
Symbol
-
25
20
20
0
20
0
15
ns
ns
IDT7007X55
Max
Min.
Max.
-
-
-
55
45
45
0
40
0
30
Unit
WRITE CYCLE
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End-of-Write
35
30
30
0
25
0
15
tHZ
Output High-Z Time(1. 2)
-
15
tOH
Data Hold Time(4)
0
twz
Write Enable to Output in High-Z(1. 2)
tow
Output Active from End-of-Write(1· 2. 4)
tSWAO
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
twc
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
-
-
ns
ns
ns
ns
ns
-
ns
-
ns
-
25
ns
-
0
-
ns
-
15
-
25
ns
0
5
5
-
0
5
5
-
ns
ns
ns
2940 tbl13
NOTES:
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature. the actual tOH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
6.08
10
IDT7007S/L
HIGH·SPEED 32K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING{1,5,8)
twc
~~
Jr>,.
"
ADDRESS
)~
tHZ(7)
j
tAw
If
CEarSEM (9)
J
twp(2)
f4-tAS(6\
Rm
tWR(3)
~r
-J:
J
-tw~
DATAoUT
tow
If
\I
(4)
~
tow
..
~
'.
(4)
,
J
9_l-----
to
D A T A I N - - - - - - - - I_
F ___
2940 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,5,)
twc
~~
Jr>,.
~~
ADDR ESS
J\
tAW
CEar SEM
9
.J
)
_IAJ6) }
Rm
tWR(3)
tEW(2)
\\\
.1.-
~
tOH
DATAIN----------------------------~F~---------------~~r-----------------tow
2940 drw 10
NOTES:
1. RiW or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a LOW CE and a LOW RNJ for memory array writing cycle.
3. tWR is measured from the earlier of CE or Rm (or SEM or RtW) going HIGH to the end of write cycle.
4. Durin~is period, the I/O pins are in the output state and input signals mu~ not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with .or after the RIW LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE or RiW.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to tuin off and data
to be placed on the bus for the required tow. If OE is HIGH during an RNJ controlled write cycle, this requirement does not apply and the write pulse can
be as short as th~ecified twp_._
__
9. To access RAM, CE VIL and SEM VIH. To access semaphore, CE VIH and SEM VIL. tEW must be met for either condition.
=
=
=
6.08
=
11
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao-A2
DATAo----+-----~
Rm - - - - + - - " ' "
2940 drw 11
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
-'X'-_________
AO"A"-A2"A"____M_A_T_C_H
____
SIDE(2) "A"
RiW"A" _ _ _ _ _ _J
SEM"A"
AO"B"-A2"B"
SIDE(2) "8"
2940 drw 12
NOTES:
1. DOR DOL Vll, CER CEl VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "8" is the opposite from port "A".
3. This parameter is measured from RIWA or SEMA going HIGH to R1Ws or SEMs going HIGH.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
=
=
6.08
12
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
IDT7007X20
COM'LONLY
Min.
Max.
Parameter
IDT7007X25
Min.
Max.
Unit
ns
BUSY TIMING (MIS = H)
tBAA
BUSY Access Time from Address Match
-
20
-
20
tBDA
BUSY Disable Time from Address Not Matched
-
20
20
ns
tBAC
BUSY Access Time from Chip Enable LOW
-
20
20
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
tAPS
Arbitration Priority Set-up Time (2 )
BUSY Disable to Valid Data(3)
tBDD
17
-
17
ns
5
-
5
-
ns
-
20
-
25
ns
BUSY TIMING (MiS = L)
tWB
BUSY Input to Write(4)
0
-
0
-
ns
tWH
Write Hold After BUSV(5)
15
-
17
-
ns
-
45
-
50
ns
35
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
30
IDT7007X35
Symbol
Parameter
IDT7007X55
Min.
Max.
20
-
45
ns
20
-
40
ns
20
Min.
Max.
Unit
BUSY TIMING (MIS = H)
tBAA
BUSY Access Time from Address Match
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
-
ns
BUSY Disable Time from Chip Enable HIGH
-
20
-
40
tBDC
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
ns
tBDD
BUSY Disable to Valid Data(3)
-
35
-
55
ns
0
-
0
25
-
ns
80
ns
65
ns
BUSY TIMING (MIS = L)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSV(5)
25
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
-
60
45
-
NOTES:
2940tbl14
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 8USY {MIS VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBOO is a calculated parameter and is the greater of 0, twoo - twp (actual) or tODD - tow (actual).
4. To ensure that the write cycle is inhibited on port "8" during contention on port "A".
5. To ensure that a write cycle is completed on port "8" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
=
6.08
13
IDT7007S/L
HIGH·SPEED 32K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,5) (MiS = VIH)
twe
ADDR'A
"=>(
)K
MATCH
twp
/~
~K
tow
)K
DATAIN 'A
VALID
tAPS (1)
)K"
ADDR"s
MATCH
'" "r-",
BUSY"s
.1 tOH
*
i-IBDF
twoo
DATAOUT"s
tODD (3)
!Boo
)E
2940 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Mis = Vil (SLAVE).
2. CEl CER Vil
3. OE =Vil for the reading port.
4. If Mis =Vil (SLAVE), then BUSY is an input (BUSY'A' =VIH and BUSY's' = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
=
=
TIMING WAVEFORM OF WRITE WITH BUSY (MiS =VIL)
twp
BUSY"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking RIW"B", until BUSY"B" goes High.
6,08
14
IDT7007S/L
HIGH-SPEED 32K X 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(l) (MiS
ADDR"A"=X
and "B"
=H)
x=
ADDRESSES MATCH
-------
BUSY"B"
2940 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(l){M/S H)
=
ADDRESS "N"
MATCHING ADDRESS "N"
BUSY'B"
2940 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from port "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(l)
IDT7007X20
COM'LONLY
Min.
Max.
Parameter
Symbol
II
IDT7007X25
Min
Max.
I Unit
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
0
0
-
0
0
-
ns
-
-
20
20
-
20
20
ns
IDT7007X35
Symbol
Parameter
ns
ns
IDT7007X55
Min.
Max.
I
Min
Max.
Unit
-
0
-
ns
25
25
-
40
ns
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
-
tlNR
Interrupt Reset Time
-
NOTE:
1. "X" in part numbers indicates power rating (8 or L).
0
40
ns
ns
2739 tbl15
S.08
15
IDT7007S/L
HIGH·SPEED 32K x 8 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~----------------twc:
.....------------~
ADDR"A"
CE"A"
RiW"A"
"i. . .___________________
3L
t",S(
INT"B"
2940 drw 17
~----------------tRC--------------~
INTERRUPT CLEAR ADDRESS (2)
OE"B"
2940 drw 18
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or RiW) is asserted last.
4. Timing depends on which enable signal (CE or RiW) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Right Port
Left Port
RlWL
CEL
L
L
X
X
X
OEL A14L-AoL INTL
RlWR
CER
X
OER A14R-AoR INTR
L(2)
X
X
Function
Set Right INTR Flag
7FFF
X
X
X
X
X
X
X
X
X
X
X
L
L
7FFF
H(3)
Ll;j)
L
L
7FFE
X
Set Left INTL Flag
L
L
7FFE
H(2)
X
X
X
X
X
X
Reset Left INTL Flag
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Reset Right INTR Flag
2739 tbl16
6.08
16
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
TRUTH TABLE II ARBITRATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ADDRESS BUSY
Outputs
Inputs
CEL
CER
AOL-A14L
AOR-A14R
BUSYL(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
Function
NOTES:
2940 tbl17
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT7007 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAps is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
Do - 07 Left
Do - 07 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
a
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.
2940 tbl18
FUNCTIONAL DESCRIPTION
The IDT7007 provides two ports with separate control,
address and 1/0 pins that permit independent access for reads
or writes to any location in memory. The IDT7007 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box ormessage center) is assigned to each port.
The left port interrupt flag (I NTL) is asserted when the right port
writes to memory location 7FFE (HEX), where a write is
defined as CE = RiW = VIL per the Truth Table. The left port
clears the interrupt through access of address location 7FFE
when CER =OER =VIL, RiW is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
writes to memory location 7FFF (HEX) and to clear the
interrupt flag (INTR), the right port must read the memory
location 7FFF. The message (8 bits) at 7FFE or 7FFF is userdefined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 7FFE and
7FFF are not used as mail boxes, but as part of the random
access memory. Referto Table 1 forthe interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
6.08
17
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port LOW.
The busy outputs on the IDT 7007 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7007 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAMs array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7007 RAM the busy pin is
MASTER
Dual Port
BAM.
I
CE
BUSY (L) BUSY (R)
T
SLAVE
Dual Port
BAM.
CE
MASTER
BUSY(L)
CE
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
1
SLAVE
Dual Port
BAM.
0
-
CE
BUSY(L) BUSY (R)
I
0
0
w
()
1
Dual Port
BAM.
-a:
_W
BUSY (R)
~
2940 drw 19
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7007 RAMs.
an output if the part is used as a master (MIS pin =H), and the
busy pin is an input if the part used as a slave (MIS pin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a masterlslave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with the RNi signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
data in the slave.
SEMAPHORES
The IDT7007 is an extremely fast Dual-Port 16K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer's software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both HIGH.
Systems which can best use the IDT7007 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7007s hardware semaphores, which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be
allocated in varying configurations. The IDT7007 does not
use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
''Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
6.08
18
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is
released when the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7007 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RNV) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW
and the other side HIGH. This condition will continue until a
one is written to the same semaphore request latch. Should
the other side's semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
LPORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
OJ
OJ
WRITE
WRITE
SEMAPHORE.-____~~
READ
'----'--____•
SEMAPHORE
READ
2940 drw20
Figure 4. IDT7007 Semaphore Logic
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7007's Dual-Port
RAM. Say the 32K x 8 RAM was to be divided into two 16K x
8 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
6.08
19
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
indicator for the upper section of memory.
To take a resource, in this example the lower 16K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower
16K. Meanwhile the right processor was attempting to gain
control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore O. At this point, the software could choose to try
and gain control of the second 16K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 16K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the 1/0 device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the 1/0 devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Processl
Temperature
Range
Y:lank
PF
'-------------1 G
J
~-----------~
20
25
35
55
L - - - - - - - - - - - - - - - tlILS
~----------------------~: 7007
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
Commercial Only }
Speed in nanoseconds
Standard Power
Low Power
256K (32K x 8) Dual-Port RAM
2940 drw 21
6.08
20
~
HIGH-SPEED
64K X 8 DUAL-PORT
STATIC RAM
ADVANCED
IDT7008S/L
Integrated Device Technology. Inc.
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 35/55ns (max.)
- Commercial: 25/35/55ns (max.)
• Low-power operation
- IDT7008S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7008L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7008 easily expands data bus width to 16 bits or
•
•
•
•
•
•
•
•
•
more using the Master/Slave select when cascading
more than one device
Mis = H for BUSY output flag on Master,
Mis =L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001 V
electrostatic discharge
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA and PLCC and a 1OO-pin TQFP
Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
-'-
OEl
'J
RlWl
I/O
Control
.:
AOl
Address
Decoder
1
"v
A
~
f--
'"
A
OEl~
MEMORY
ARRAY
+
BUSYR (1,2)
"
/l.
~
---y
16/
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
RIWL:
)
I/00R-I/07R
1/0
Control
16/
CEl:
[
L.,
, ~r
,g)
I:
~
~
I/Ool-1/07l
A15l
-L
-
--./
1
CEl
(
\.
.:
Address
Decoder
A15R
AOR
I
WER
:OER
IRMiR
t flM~slf t
3198 d/W 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
«'J1995 Integrated Device Technology, Inc.
6.09
APRIL 1995
DSC-l083/-
1
ADVANCED
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7008S/L
HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
PIN NAMES
DESCRIPTION:
The IDT7008 is a high-speed 64K x 8 Dual-Port Static
RAM. The IDT7008 is designed to be used as a stand-alone
512K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 16-bit-or-more word systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or
wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and 110 pins that permit independent,
asynchronous access for reads or writes to .any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
The IDT7008 is packaged in an 84-pin pin PGA, an 84-pin
PLCC, and a 1000-pin thin plastic quad flatpack, TQFP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
Left Port
Right Port
CER
CEl
Names
Chip Enable
RIWL
RIWR
ReadlWrite Enable
OEl
OER
Output Enable
AOl-A15l
AOR-A15R
Address
I/OOl - I/07L
I/OOR - I/07R
Data Input/Output
SEMl
SEMR
Semaphore Enable
INTl
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vcc
Power
GND
Ground
3198 tbl 01
NOTES:
1. All Vce pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part marking.
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
Power
999
Speed
A
A
Package
Process/
Temperature
Range
y:,ank
~
________________
PF
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
J
100-pin TQFP (PN100-1)
84-pln PGA (G84-1)
84-pin PLCC (J84-i)
25
Commercial Only }
~G
~----------------------~ 35
Speed in nanoseconds
55
1..--_ _ _ _ _ _ _ _ _ _
---11 S
IL
L -______________________________________
~:
7008
Standard Power
Low Power
512K (64K x 8) Dual-Port RAM
3198 drw 21
6.09
2
G
IDT70121S/L
IDT70125S/L
HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM
WITH BUSY & INTERRUPT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
- Commercial: 25/35/45/55ns (max.)
• Low-power operation
-IDT70121n0125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
-IDT70121n0125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
• On-chip port arbitration logic (IDT70121 only)
• BUSY output flag on Master; BUSY input on Slave
• INT flag for port-to-port communication
• Battery backup operation-2V data retention
• TTL-compatible, signal 5V (±10%) power supply
• Available in 52-pin PLCC
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a "MASTER" Dual-Port
RAM together with the IDT70125 "SLAVE" Dual-Port in 18bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous access for reads orwrites to any location in memory.
An automatic power-down feature, controlled by CE, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user's option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
FUNCTIONAL BLOCK DIAGRAM
~
(
-...J
I
1
'--
~
)J
I/OOl-I/OSl
f--
1/0
Control
AOl
··
Address
Decoder
I
'If
A
t-..
"
v
MEMORY
ARRAY
t
11
A
J-.
"
v
,
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEl'--'
OEl
t
I
Address
Decoder
··
A11R
AOR
I
--'CER
·:OER
'IRIWR
RlWl •
2)
BUSYR (1,2)
11
NOTES:
1. 70121 (MASTER):
BUSY is non-tristated push-pull
output.
70125 (SLAVE):
BUSY is input.
2. INT is totem-pole
output.
1/0
Control
t-..
A
I/OOR-I/OSR
L..,
,
1,2)
A10l
I1
I
[
]
i
I
INTR(2)
2654 drw01
COMMERCIAL TEMPERATURE RANGES
Q1995 Integrated Device Technology, Inc.
APRIL 1995
6.10
eSC-10S0.'3
lOT 70121nDT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Continued):
retention capability with each port typically consuming 200llW
from a 2V battery.
The I OT70121 II OT70125 devices are packaged in a 52-pin
PLCC.
Fabricated using lOT's CMOS high-performance
technology, these devices typically operate on only 400mW of
power. Low-power (L) versions offer battery backup data
PIN CONFIGURATIONS
RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
NOEX
Ambient Temperature
2654 tbl 02
A3L
A4L
A5L
A6L
A7L
ASL
A9L
1I0oL
I/OIL
I/02L
I/03L
10T70121/125
J52-1
RECOMMENDED DC
OPERATING CONDITIONS
PLCC
TOP VIEW (1)
Symbol
A9R
I/OSR
I/07R
Parameter
Min.
Typ.
Max.
Unit
5
0
VIH
Input High Voltage
2.2
VIL
Input Low Voltaqe
-0.5(1)
-
5.5
0.0
6.0(2)
V
Supply Voltage
4.5
0
Vee
Supply Voltage
GND
0.8
NOTE:
2654 drw 02
V
V
V
2654 tbl 03
1. VIL ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.5V.
NOTE:
1. This tex1 does not indicate the orientation of the actual part-marking.
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE
Symbol
Rating
Commercial
Unit
VTERM(2)
Terminal Voltage
with Respect to GNO
Operating
Temperature
-0.5 to +7.0
V
o to +70
°C
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output
Current
50
mA
TA
TBIAS
Symbol
CIN
COUT
(TA
= +25°C, f = 1.0MHz)
Parameter(l)
Condition
Max.
Unit
Input Capacitance
VIN = 3dV
pF
Output Capacitance
VOUT= 3dV
9
10
pF
2654 tbl13
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
NOTE:
2654 tbl 01
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for ex1ended
periods may affect reliabilty.
2. VTERM must not exceed Vcc + O.5V for more than 25% of the cycle time or
10ns maximum, and is limited to !> 20mA for the period of VTERM ~ Vee +
O.5V.
6.10
2
IDT 7012111DT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V ± 10%)
Symbol
Parameter
70121S
70125S
Min, Max,
Test Condition
-
10
IOL -4mA
-
IOH --4mA
2.4
IiLiI
Input Leakage Current(5)
Vee = 5.5V, VIN = OV to Vee
IiLOI
Output Leakage Current(5)
Vee = 5.5V, CE = VIH
VOL
Outout Low Voltaae
VOH
Outout Hiah Voltaae
70121L
70125L
Min, Max, Unit
-
5
IlA
5
IlA
0.4
-
0.4
V
-
2.4
-
10
VOLJT - OV to Vee
NOTE:
1. At Vcc < 2.0V leakages are undefined.
V
2654 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,4) (Vcc = 5V ± 10%)
Symbol
lee
Test
Condition
Parameter
Dynamic Operating
Current (Both Ports
70121 X 25 70121 X 35 70121 X 45 70121 X 55
70125 X25 70125 X35 70125 X45 70125 X 55
Typ, Max, Typ, Max, Typ, Max, Typ, Max, Unit
Version
CE = VIL,Outputs Open,
f = fMAX(2)
Com'!.
S
L
125
125
260
220
125
125
250
210
125
125
245
205
125
125
240
200
rnA
CE'A' and CE's' = VIH,
f = fMAX(2)
Com'!.
S
30
65
30
65
30
65
30
65
rnA
L
30
45
30
45
30
45
30
45
Standby Current
CE'A'=VIL and CE'S'=VIH(5)
Com'!.
S
80
175
80
165
80
160
80
155
(One Port-TTL
Active Port Outputs Open,
L
80
145
80
135
80
130
80
125
Level Inputs)
f
Full Standby
CE'A' and CE's' ~ Vee - 0.2V,
S
1.0
15
1.0
15
1.0
15
1.0
15
Current (Both Ports
L
0.2
5
0.2
5
0.2
5
0.2
5
CMOS Level Inputs)
VIN ~ Vee - 0.2V
or VIN ~ 0.2V, f = 0(3)
Full Standby
Current (One Port
S
L
70
70
170
140
70
160
70
155
VIN ~ Vee - 0.2V or
70
130
70
125
70
70
120
Active)
IS81
Standby Current
(Both Ports-TTL
Level Inputs)
IS82
IS83
IS84
CMOS Level Inputs)
=
rnA
fMAX(2)
CE"A"~O.2V
and
CE's·~VCC-O.2V(5)
Com'!.
rnA
;F
Com'!.
150
rnA
VIN ~ 0.2V, Active Port
Outputs Open, f = fMAX(2)
NOTES:
1. "X" in part numbers indicates power rating (S or L).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1ItRC, and using "AC TEST
CONDITIONS" of input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, TA=+25°C for Typ, and is not production tested.
5. Port "A" may be either left or right port. Port "8" is opposite from port "A".
6.10
2654 tbl 05
3
IDT 70121nDT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (L Version Only)
Symbol
Parameter
VOR
Vcc for Data Retention
ICCOR
tCOR(3)
tR(3)
Data Retention Current
70121 Ll70125L
Typ.(l)
Max.
Test Condition
Min.
Vcc =2.0V, CE ~ Vcc - 0.2V
VIN ~ VCC - 0.2V or VIN :5 0.2V
Chip Deselect to Data Retention Time
ICom'1.
-
-
100
0
tRC(2)
Operation Recovery Time
Unit
-
2
V
1500
-
IlA
ns
-
ns
NOTES:
1. Vcc = 2V, TA = +25°C, and are not production tested.
2. tRC Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
2654 tbl06
=
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
VOR::::: 2V
f
tcDR
tR~
VOR
~\\\\\\\\\\\
\~----------------------~I
2654 drw 03
5V
5V
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
1250n
DATAoUT
OATAouT--_-+-....
BUSy--....---+--.....
INT
Output Reference Levels
1.5V
Output Load
See Figure 1 and 2
775n
30pF
775n
5pF
2654 drw 04
2654 tbl 07
Figure 2. Output Test Load
Figure 1. AC Output Test Load
(For tLZ, tHZ, tWZ, tOW)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
70121 X 25
70125 X25
Symbol
Parameter
70121 X 35
70125 X 35
70121 X 45
70125 X 45
70121 X 55
70125 X 55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
25
-
35
-
45
-
55
-
tM
Address Access Time
-
25
-
35
-
45
-
55
ns
tACE
Chip Enable Access Time
25
-
45
-
55
ns
Output Enable Access Time
-
35
tAOE
-
35
ns
tOH
Output Hold from Address Change
Output Low-Z Time( 1,~)
0
-
0
0
-
ns
12
25
30
ns
0
-
0
-
0
-
0
-
ns
tHZ
tpu
Output High-Z Time\"~)
-
10
-
15
-
20
-
30
ns
Chip Enable to Power-Up Time\~)
0
-
0
-
0
-
0
-
ns
tpo
Chip Disable to Power-Down Time\~)
-
50
50
-
50
-
50
ns
tLZ
0
-
NOTES:
1. Transition is measured ±500mV from Low or High impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. "X" in part numbers indicates power rating (S or L).
6.10
2654 tbl 08
4
IDT 7012111DT 70125 HIGH·SPEED 2K x 9
DUAL·PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1,2,4)
ADDRESS
~.~'----tA-A----tRC
~
-~- - t - t O HtOH
DATAOUT~~~~~~~~==~~~YI,________~D~A~T~A~V~A~L=I~D________-,.~~~~~~~~~~
BUSyOUT----------~~~~~~~,_r_-----------------------------------------------2654 drw 05
tsoo (3,4)
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(5)
tACE
CE
~,..
\
lAOE
tHZ(2)
j
~,..
\
OE
tLZ
tHZ(L.,
(1)
-;'-/ /-;f-
DATAoUT
...;,..\ \- .....
tLZ (1)
Icc
.J
J
(4)
-tPU
=4
VALID DATA
tPO(4)
I.
.,f-
50%1_____
CURRENT _________~~ 50%
Iss
2654 drw06
NOTES:
1. Timing depends on which signal is aserted last, OE or CEo
2. Timing depends on which signal is deaserted first, OE or CEo
3. tBoo delay is required only in a case where the opposite port is completing
a write operation to the same address location. For simultanious read operations
BUSY has no relationship to valid output data.
4. Start·of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBOO.
5. RiW VIH, and the address is valid prior to other coincidental with CE transition Low.
=
6.10
5
lOT 7012111DT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
70121 X 25
70125 X25
Parameter
Symbol
Write Cycle
Write Cycle Time\"J
twc
tEW
Chip Enable to End-of-Write
Address Valid to End-of-Write
tAw
70121 X 35 70121 X 45
70125 X 35 70125 X45
70121 X 55
70125 X 55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
-
35
20
20
-
30
0
-
20
10
-
25
30
tAs
twp
Address Set-up Time
Write Pulse Width\b)
tWR
Write Recovery Time
tDW
tHZ
tDH
twz
Data Valid to End-of-Write
Output High-Z Time\l,~)
Data Hold Time(5)
-
Write Enabled to Output in High-Z\1.2)
-
10
tow
Output Active from End-of-Write(1,2)
0
-
20
0
12
0
0
30
0
-
0
0
-
45
-
55
-
35
40
-
ns
-
35
-
40
ns
0
-
35
40
ns
ns
0
-
-
20
-
20
-
ns
ns
30
30
ns
ns
ns
-
ns
15
-
-
20
-
0
15
-
-
20
-
0
0
0
-
-
0
0
ns
NOTES:
2654 tbl 09
1.Transition is measured ±SOOmV from low or high impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, twe = tBAA + twP, since RIW = VIL must occur after tBAA .
4. "X" in part numbers indicates power rating (S or L).
5. The specified tOH must be met by the device supplying write date to the RAM under all operating conditions.
Although tOH and tow values will vary over voltage nad temperature. The actual tOH will always be smaller than the actual tow.
6. If OE is low during a RIW controlled write cycle, the write pulse width must be the larger of twp or (twz + tDW) to allow the 1/0 drivers to turn off\
data to be placed on the bus for the required tow. If OE is High during a RIW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING(1,5,8)
twc
ADDRESS
~I
~~
1[\
1\
f
tHZ(7)
I
(3)
tWR f - -
tAW
~\\\~\
(2)
-tAS(6)
twp
tHZ-
~rI\.
..,~
1
I+--twz
DATAoUT
L~
(4)
(7)
tow~
III
1\
E
t
OW
.'ot
tOH
(4)
,
j
~
DATAIN--------------------------------~. ____
~________________~----r-------------------NOTES:
2654 drw07
1. RIW or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a CE VIL and a RIW VIL
3. tWR is measured from the earlier of CE or RIW going High to the end of the write cycle.
4. Durin[!!lis period, the 1/0 pins are in the output state and input si~als must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal (CE or RIW) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +I- SOOmV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a RIW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 1/0 drivers to turn off
data to be placed on the bus for the required tow. If OE is High during a RIW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
=
=
6.10
6
lOT 70121/10T 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,5)
twc
ADDRESS
~~
\I
/\
II\.
tAW
_~.,)
.,~
J
tEW
(2)
tWR(3)14-
Rm
tow
tOH
DATAIN------------------------------~~~---------------~---~-----------------.111
2654 drw08
NOTES:
RiW or CE must be High during all address transitions.
A write occurs during the overlap (tEW or twp) of a CE YIL and a RiW YIL
tWR is measured from the earlier of CE or RiW going High to the end of the write cycle.
During this period, the I/O pins are in the output state and input signals must not be applied.
If the CE Low transition occurs simultaneously with or after the Rfjj Low transition, the outputs remain in the high-impedance state.
Timing depends on which enable signal (CE or RiW) is asserted last.
This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mY from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a RflJ controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off
data to be placed on the bus for the required tow. If OE is High during a RflJ controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
1.
2.
3.
4.
5.
6.
7.
=
=
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
70121 X 25 70121 X 35 70121 X 45 70121 X 55
70125 X 25 70125 X 35 70125 X 45 70125 X 55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Symbol
Parameter
Busy Timing (For Master IDT70121 Only)
-
tBAA
BUSY Access Time from Address
tBOA
BUSY Disable Time from Address
tBAC
BUSY Access Time from Chip Enable
tBOC
BUSY Disable Time from Chip Enable
tWDD
Write Pulse to Data Delay\l)
tODD
Write Data Valid to Read Data Delay\l)
tAPS
Arbitration Priority Set-up Time\2)
5
tBDD
BUSY Disable to Valid Data(3)
-
20
20
-
20
-
20
50
-
45
5
-
20
20
35
-
20
20
60
5
20
-
30
ns
20
-
30
ns
20
20
70
55
-
5
30
ns
30
ns
80
ns
65
ns
-
ns
55
ns
35
-
-
0
-
0
20
-
20
-
ns
20
50
-
60
70
-
80
ns
35
-
45
-
55
-
65
ns
25
-
-
45
-
Busy Timing (For Slave IDT70125 Only)
tWB
Write to BUSY Input(4)
0
tWH
Write Hold After BUSY\O)
15
tWDD
Write Pulse to Data Delay\l)
tODD
Write Data Valid to Read Data Delay\l)
-
0
NOTES:
1.
2.
3.
4.
5.
6.
ns
2654tbll0
Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port -to-Port Read and BUSY.
To ensure that the earlier of the two ports wins.
tsoo is a calculated parameter and is the greater of 0, twoo - twp (actual) or toDD - tow (actual).
To ensure that a write cycle is inhibited on port 'B' during contention on port 'A' ..
To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
"X" in part numbers indicates power rating (S or L).
6~0
7
lOT 70121nDT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSy(1,2,3)
twe
ADDR'A'
~~
If
MATCH
/~
J\
twp
~r
-.l
I
\
tow
"
DATAIN'A'
....
ADDR's'
BUSY's'
.J\
tOH
VALID
tAPS(1)r:
l~
L
MATCH
....
t:= tsoo-
1
'- -\
two ....
I
tSOA
~~
DATAoUT'S'
J\
VALID
tOOO(4)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT 70125).
2654 drw09
2. CEl =CER =V,l
3. OE =V,l for the reading port.
4. Aii"timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is oppsite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
J . - - - - - twP ---~
pjijij"AOO
BUSY"s'
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) -and output (master).
2. BUSY is asserted on port 'B' blocking Rfij·s·. until BUSY's' goes High.
3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "Boo is the opposite from port "A".
6.10
8
lOT 70121nDT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CETIMIING(1}
Lt~~~
____~X~__________________
X_____
A_D_D_R_E_S_S_E_S_M_A_T_C_H____________________- J
r-=--=--=-___
CER
J-tAPS
CEl
~tBAC~------------------------------
BUSYl
2654 drw 12
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
2. If tAPS is not satisified, the 8USY will be asserted on one side orthe other, but there is no guarantee on which side 8USY will be asserted (70121 only).
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS
(1)
tRC OR twc
ADDR'A
~~
- . tAPS
AD DR's
~?
ADDRESSES MATCH
/\
J;""
ADDRESSES DO NOT MATCH
r-
~?
J~
~t8AA
BUSY's'
I ..
tSDA
9---f
2654 drw 13
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
2. If tAPS is not satisified, the 8USY will be asserted on one side or the other, but there is no guarantee on which side 8USY will be asserted (70121 only).
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
Parameter
Interrupt Timing
tAS
Address Set-up Time
Write Recovery Time
tWR
tiNS
tlNR
70121 X 25
70125 X 25
70121 X 35 70121 X 45
70125 X 35 70125 X 45
Min. Max
Min. Max. Min. Max Min. Max. Unit
0
0
-
Interrupt Set Time
Interrupt Reset Time
NOTES;
1. "X" in part numbers indicates power rating (S or l).
25
25
70121 X 55
70125 X 55
0
0
-
0
0
-
0
0
-
ns
ns
-
25
35
-
40
40
-
45
45
ns
ns
2654 tbl11
6.10
9
lOT 70121nDT 70125 HIGH-SPEED 2K x 9
DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT MODE
!~ t.ST
INTERRUPT
ADDR'A'
~:~
x___
M
JfiYR(~
ADDRESS'
RiW'A'
l-t Vee - 0.2V
COM'L.
S
CE'A'< 0.2V and
MIL.
L
-mA
170
170
310
260
-
25
25
....... - ... .
(~:;!;/
1O~::~
~~160
60
50
-
~~
105
190
109
160
-
·· ... :.::.1
"-'"
1.()::·::rL 15
O.~ if In 5
mA
1.0
15
0.2
5
mA
mA
L:::::.i:::.~j
S
L
Active Port Outputs Open,
25 -r--·SO
25 (::[F50
105c::: ::·~~190
MIL.
SEMR = SEML ~ Vee - 0.2V
VIN ~ Vee - 0.2V or VIN .s 0.2V
-
-
S
Both Ports CEL and
CER ~ Vee - 0.2V
CMOS Level Inputs)
170
310
170~ ::260
-
L
CE'B'~ Vee - 0.2V(5)
-
L
Full Standby Current
(Both Ports - All
Full Standby Current
(One Port-All
-
I
-lf~~)r'~':)
-
~. ~.:.:. :J
-
-
mA
/;.-..Il..
COM'L.
S
L
1ciO-···
100
170
140
100
100
170
140
f = fMAX(3)
NOTES:
2954 tbl 09
1. "X" in part numbers indicates power rating (8 or L)
o
2. Vee SV, TA +2S C, and are not production tested. IceDe 120mA(typ.)
3. At f fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC. and using "AC Test Conditions"
of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite of port "A".
=
=
=
=
=
6.12
5
IDT7015 SIL
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued) (Vcc =S.OV ± 10%)
7015X20
7015X25
7015X35
Test
Symbol
lee
18B1
18B2
Parameter
Typ.(2) Max. Typ.(2) Max. ~nit
MIL.
S
L
-
-
155
155
340
280
150
150
300
250
(Both Ports Active)
f = fMAX(3)
COM'L.
S
L
160
160
290
240
155
155
265
220
150
150
250
210
Standby Current
(Both Ports - TTL
CEl = CER = VIH
SEMR = SEMl = VIH
MIL.
S
L
-
-
16
16
80
65
13
13
80
65
Level Inputs)
f = fMAX(3)
COM'L.
S
L
20
20
60
50
16
16
60
50
13
13
60
50
CE"A'=Vll and CE'B'=VIH(5) MIL.
S
90
215
85
190
Active Port Outputs Open
f = fMAX(3)
L
-
-
(One Port -
-
90
180
85
160
S
95
180
90
170
85
155
L
95
150
90
140
85
130
S
L
-
-
1.0
0.2
30
10
1.0
0.2
30
10
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
S
L
-
-
-
-
85
85
200
170
80
80
175
150
S
L
90
90
155
130
85
145
120
80
80
135
110
TTL
COM'L.
MIL.
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee - 0.2V
CMOS Level Inputs)
COM'L.
VIN > Vee - 0.2V or
VIN ~ 0.2V, f = 0(4)
SEMR = SEMl > Vee - 0.2\1
MIL.
CE"A"~ 0.2V and
CE"B" ;:::, Vee - 0.2V(5)
Full Standby Current
(One Port-All
CMOS Level Inputs)
mA
mA
Standby Current
SEMR = SEMl = VIH
18B4
Max.
CE = Vll, Outputs Open
SEM = VIH
Level Inputs)
18B3
Typ.(2)
Version
Condition
Dynamic Operating
Current
mA
mA
mA
SEMR = SEMl ;:::, Vee - 0.2\1
COM'L.
VIN ;:::, Vee - 0.2V or
VIN~ 0.2V
Active Port Outputs Open,
f - fMAX(3)
85
2954 tbl10
NOTES:
1. "X" in part numbers indicates power rating (8 or L)
2. Vee = 5V, TA = +25°C, and are not production tested. IceDe = 120mA(typ.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 11 tRC, and using
"AC Test Conditions" of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite of port "A".
=
OUTPUT LOADS AND AC TEST
CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels 1.5V
Output Reference Levels
1.5V
Output Load
Figure 1 & 2
5V
5V
DATAoUT
8U8Y----~~--+_~
INT
347(1
30pF
2940 drwOS
Figure 1. AC Output Test Load
6.12
DATAoUT----~~--+__
347(1
5pF*
2940 drw06
Figure 2. Output Test Load
(For tLZ, tHZ, twz, tow)
Including scope and jig.
6
IDT7015 S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4}
Symbol
IDT7015X15
COM'LONLY
Min.
Max.
Parameter
READ CYCLE
"...
,;~:
tRC
Read Cycle Time
15
tM
Address Access Time
tACE
Chip Enable Access Time(3)
-
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(l, 2)
3
tHZ
Output High-Z Time(l, 2)
tpu
Chip Enable to Power Up Time(2)
tPD
Chip Disable to Power Down Time(2)
tsop
Semaphore Flag Update Pulse (OE or SEM)
tSM
Semaphore Address Access Time
Symbol
-
-
.
17
-
ns
17
ns
17
ns
10
-
10
ns
-
3
-
ns
3
-
ns
10
-
10
ns
-
0
-
ns
15
-
17
ns
-
10
-
ns
15
-
17
ns
:.~:::~::, 15
'\'( 15
<1',::":::::;
l::
::::;
(::::
,
,..:,......
<>
-<:::"
,;;::y
,::Jii,
!!::/~
Unit
-
, , " Y""
q;':::::
Parameter
"
IDT7015X17
COM'LONLY
Min.
Max.
IDT7015X20
IDT7015X25
IDT7015X35
Min.
Max.
Min.
Min.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
-
25
-
35
-
tM
Address Access Time
20
-
25
-
35
ns
tACE
Chip Enable Access Time(3)
20
-
25
ns
Output Enable Access Time
12
-
13
-
35
tAOE
-
20
ns
tOH
Output Hold from Address Change
3
-
3
3
-
ns
tLZ
Output Low-Z Time\l,~)
3
-
3
-
3
-
ns
tHZ
Output High-Z Time(1, 2)
-
12
-
15
-
20
ns
ns
tpu
Chip Enable to Power Up Time\~)
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
20
-
25
-
35
ns
tsop
Semaphore Flag Update Pulse (OE or SEM)
10
-
10
-
15
-
ns
tSM
Semaphore Address Access Time
-
20
-
25
-
35
NOTES:
1. Transition is measured ±500mV from low- or high-impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE VIL and SEM VIH. To access semaphore, CE VIN and SEM VIL.
4. "X" in part numbers indicates power rating (S or L).
=
=
=
6.12
ns
2954 tbl11
=
7
IDT7015 S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
'II'
Ii\.
'I
Ii\.
tAA(4)
\\\'
\\\\
~ tACE(4)
\.
i----
)'///
tAOE(4)
/'1///
\.
Rm
~
: - tOH--J
tLZ(1)-=-:lt
DATAoUT
1\XV
VALID DATA
J\.
(4)
tHZ(2)
BUSYOUT
\\\\\\\\¥
:+-
t800(3, 4)
~
I
2954 drw 0
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tsoo delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tsoo.
5. SEM =VIH.
TIMING OF POWER-UP I POWER-DOWN
CE
Icc
~tPU3
(tPD=L
ISB
2954 c!rw08
6.12
8
IDT7015 S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT7015X15
COM'LONLY
Symbol
Max
Min.
Parameter
IDT7015X17
COM'LONLY
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
tEW
Chip Enable to End-ot-Write(3)
tAW
Address Valid to End-at-Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWA
Write Recovery Time
tow
Data Valid to End-at-Write
tHZ
Output High-Z Time(1, 2)
15
12
o
2
.--:'
I,<~(C?
'::r::;.~;
.::~
17
ns
12
12
ns
_
ns
o
ns
12
ns
2
ns
-
10
ns
10
10
o
ns
tOH
Data Hold Time(4j
twz
Write Enable to Output in High-Z(1, 2)
tow
Output Active tram End-ot-Write(1, 2, 4)
o
ns
tSWRO
SEM Flag Write to Read Time
5
ns
tsps
SEM Flag Contention Window
5
ns
Symbol
ns
10
10
5-'
Parameter
IDT7015X20
IDT7015X25
IDT7015X35
Min.
Min.
Min.
Max.
Max.
Max.
ns
Unit
WRITE CYCLE
25
20
20
35
-
ns
30
-
ns
Address Valid to End-at-Write
20
15
15
30
ns
tAS
Address Set-up Time(3)
o
o
o
ns
twp
Write Pulse Width
15
20
25
ns
tWA
Write Recovery Time
2
2
2
ns
tow
Data Valid to End-at-Write
15
15
15
tHZ
Output High-Z Time(1,
tOH
Data Hold Time(4)
twz
Write Enable to Output in High-Z(1, 2)
tow
Output Active from End-of-Write(1, 2, 4)
3
3
3
ns
tSWAO
SEM Flag Write to Read Time
5
5
5
ns
tsps
SEM Flag Contention Window
5
5
5
ns
twc
Write Cycle Time
tEW
Chip Enable to End-ot-Write(3)
tAW
12
2)
15
o
o
12
ns
20
o
15
ns
ns
20
ns
NOTES:
2954 tbl12
1. Transition is measured ±500mV from low - or high-impedance voltage with the output test load (Figure 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification fortDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tow values will vary
over voltage and temperature, the actuallDH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
6.12
9
IDT7015 SIL
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,5,S)
twc
~~
ADDRESS
~~
II\.
Jr\.
tHZ (7)
f
tAW
CEorSEM
(9)
If
I
tWp(2)
/4--tAS (6
tWR(3)
~k-
RiW
-:~
I\.
j
~tWZ(7)
DATPoUT
tow~
(4)
.II
~
,
I
-------iE""'--___J_l------tow
DATAIN
'.
(4)
~
tOH
2954 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, GE CONTROLLED TIMING(1,5)
twc
~~
II\.
ADDRESS
~~
11\
tAW
(9)
CEorSEM
i+-IAJ6)
1
f
tWR(3)\4-
tEW(2)
\\\
DATAIN ________________________________
--i~-----tD-W----~-'-~----t-D-H~
~~-------------------__
2954 drw 10
NOTES:
1. RJWor CE must be high during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a low CE and a low RJW for memory array writing cycle.
3. tWR is measured from the earlier of CE or Rm (or SEM or RNI) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the Rm low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last, CE or RJW.
7. This parameter is guaranteed by device characterization but is not production tested, transition is measured +/-200mV from steady state with the Output
Test load (Figure 2).
S. If OE is low during Rm controlled write cycle, the write pulse width must be the larger of t WP or (twz + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t WP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore,CE= VIH and SEM = VIL. tEW must be met for either condition.
6.12
10
IDT7015 s/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao-A2
1/00 -----+-----+-<
R/W----+----....
....- - - Write Cycle
---+1'----- Read Cycle---~
2954 drw 11
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
. . _______
AO'A'-A2'A'_ _ _M_A_T_C_H
_ _ _~X
SIDE(2) "A"
ANi'A'_ _ _ _ _.....J
SEM'A'_ _ _ _ _.....J
AO'B'-A2'B'
SIDE(2) "B"
NOTES:
1. DOR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and rig'1!.port~rt"A" may be eith~ left ~ht port. "S" is the opposite port from "A".
3. This parameter is measured from RiWA or SEMA going high to RiWs or SEMs going High.
4. If tsps is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.12
11
IDT7015 S/L
HIGH-SPEED 8K
x
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
9 DUAL-PORT STATIC RAMS
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
IDT7015X15
COM'LONLY
Min.
Max.
Parameter
BUSY TIMING (MIS
BUSY Access Time from Address Match
-
,>-::1 5
tBOA
BUSY Disable Time from Address Not Matched
-
i;;~:':::::::15
tBAC
BUSY Access Time from Chip Enable LOW
.'~~:;; 15
tBOC
BUSY Disable Time from Chip Enable HIGH
-
tAPS
Arbitration Priority Set-up Time\~)
5
tBOO
BUSY Disable to Valid Data\J)
-
;::~
!~:~;:
.::c"
-
5
-
ns
::::
15
-
17
ns
-
0
-
ns
13
30
ns
25
ns
~:
... "
17
ns
17
ns
17
ns
17
ns
,~~;:,~:;
=L)
'>.
BUSY Input to Write(4)
0
tWH
Write Hold After BUSy(5)
13} ,'i
:' rl
ns
<,
:,'",;::::.'
PORT-TO-PORT DELAY TIMING
tWOD
Write Pulse to Data Delay(l)
tOOD
Write Data Valid to Read Data Delay(1)
Symbol
15
-
....
tWB
:.:0::.':::.
Parameter
BUSY TIMING (MIS
Unit
=H)
tBAA
BUSY TIMING (MIS
IDT7015X17
COM'LONLY
Min.
Max.
c:,
30
!~,iJ:::;
25
-
IDT7015X20
IDT7015X25
IDT7015X35
Min.
Min.
Min.
Max.
Max.
Max.
Unit
20
ns
20
ns
20
ns
17
-
20
ns
=H)
tBAA
BUSY Access Time from Address Match
-
20
tBOA
BUSY Disable Time from Address Not Matched
-
20
tBAC
BUSY Access Time from Chip Enable LOW
20
tBOC
BUSY Disable Time from Chip Enable HIGH
-
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
5
-
ns
tBOD
BUSY Disable to Valid Data(3)
-
20
-
25
-
35
ns
n5
BUSY TIMING (MIS
17
-
20
20
20
=L)
tWB
BUSY Input to Write(4)
0
-
0
-
0
tWH
Write Hold After BUSy(5)
15
-
17
-
25
-
-
45
-
50
-
60
ns
45
ns
n5
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(l)
tODD
Write Data Valid to Read Data Delay(1)
30
35
NOTES:
2940 tbl13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (MIS VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD - twp (actual) or tODD - tow (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
=
6.12
12
IDTI015 S/L
HIGH·SPEED 8K x 9 DUAL·PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSV(2) (MIS
ADDR'A'
=VIH)
twe
==>(
)K
MATCH
twp
~,
/~
tDH
I+--tDW
)K
DATAIN'A'
tAPS
VALID
r ""
(1)
) (~
ADDR's'
\
BUSY's'
MATCH
I-- IBOA
'--",
tWDD
)
DATAOUT'S'
tODD
(3)
~
2954drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S::VIL
2. CEl = CEA = VIL
3. OE = VIL for the reading port.
4. If M/S::VIL (SLAVE), the BUSY is an input (BUSY=VIH). For this example, BUSY="don't care".
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "N.
TIMING WAVEFORM OF WRITE WITH BUSY
twp
BUSY's'
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking RIW'B", until BUSY"B" goes High.
6,12
2954 drw 14
13
IDT1015 S/L
HIGH-SPEED 8K X 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MiS
ADDR"A"
and"B"
=VIH)
~
ADDRESSES MATCH
~
A.......________________________
~
tA"(:t. . . .-~----------1
CE"A'
t=IBAC:j
~
BUSY"B"
-btBDC~,~
A
2954drw15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(MiS VIH)
=
ADDR"A"
ADDRESS "N"
ADDR"B"
MATCHING ADDRESS "N"
BUSY"B"
tBM
={-......--__t_BDA}
2954 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
IDT1015X15
COM'LONLY
Min.
Max.
Parameter
IDT7015X17
COM'LONLY
Min
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
-tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
Symbol
Parameter
-
0
15
-
-
0
15
ns
ns
17
ns
17
ns
IDT1015X20
IDT1015X25
IDT1015X35
Min.
Max.
Min.
Min.
Max.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
-
0
0
0
0
tiNS
Interrupt Set Time
-
20
-
25
ns
tlNR
Interrupt Reset Time
-
20
-
20
-
ns
Write Recovery Time
-
0
tWR
20
-
25
NOTE:
1. "X" in part numbers indicates power rating (S or L).
ns
ns
2739 tbl14
6.12
14
IDT7015 s/L
HIGH-SPEED BK x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~-------------------mc------------------~
CE'A'
_________________tl_NS_(_3)~
INT'B'
----------------------------------------------
2954 drw 17
~------------------- tRC------------------~
INTERRUPT CLEAR ADDRESS
ADDR'B'
(2)
DE'B'
liN" ., )
__- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2954drw 18
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or RiW) is asserted last.
4. Timing depends on which enable signal (CE or RiW) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I--INTERRUPT FLAG(1)
Left Port
Right Port
RlWL
CEL
OEL
L
L
1FFF
X
X
X
X
X
X
X
X
L
L
A12L-AoL INTL
OER A12R-AoR
X
X
iNi'R
R!WR
CER
X
X
X
X
X
X
X
L
L
1FFF
H(3)
L(3)
L
L
X
1FFE
1FFE
H(2)
X
X
X
X
X
X
NOTES:
L(2)
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2954 tbl15
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL VIL, then no change.
3. If BUSYR VIL, then no change.
=
=
6.12
15
IDT7015 S/L
HIGH-SPEED BK x 9 DUAL-PORT STATIC RAMS
TRUTH TABLE II ARBITRATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ADDRESS BUSY
Inputs
Outputs
CEl
CER
AOl-A12l
AOR-A12R
BUSYl(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
Normal
H
X
MATCH
H
H
X
H
MATCH
H
H
L
L
MATCH
(2)
(2)
Function
Normal
Write Inhibit(3)
NOTES:
2954 tbl16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDT7015 are push-pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1}
Functions
Do - 08 Left
Do - 08 Right
Status
No Action
1
1
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Right port obtains semaphore token
Semaphore free
Left Port Writes "1" to Semaphore
1
0
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "-1" to Semaphore
0
1
Left port obtains semaphore token
Semaphore free
Left Port Writes "1" to Semaphore
1
1
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015.
2954 tbl17
FUNCTIONAL DESCRIPTION
The IOT7015 provides two ports with separate control,
aqdressand 1/0 pins that permit independent access for reads
or writes to any location in memory. The IOT7015 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down Circuitry that permits the respective port to go into a standby mode when not selected (CE
High). When a port is enabled, access to the entire memory
array is permitted.
memory location 1 FFF and to clear the interrupt flag (INTR),
the right port must access memory location 1 FFF. The
message (9 bits) at 1 FFE or 1 FFF isuser-defined since it is an
addressable SRAM location. If the interrupt function is not
used, address locations 1FFE and 1 FFF are not used as mail
boxes but are still part of the random access memory. Refer
to Table I for the interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (I NTL) is asserted when the right port
writes to memory location 1 FFE where a write is defined as
the CE = RtW = Vil per the Truth Table. The left port clears
the interrupt by an address location 1 FFE access when CER
=OER =VIL, RtW is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.12
16
IDT7015 SIL
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.--
r
MASTER
Dual Port
BAM...
1
CE
SLAVE
Dual Port
BAM...
CE
cr:
l.LJ
Cl
0
(,)
l.LJ
BUSY(L) BUSY(R)
BUSY (L) BUSY (R)
.-
Cl
I.-
1
MASTER
Dual Port
BAM...
BUSY (L)
SLAVE
CE
Dual Port
BAM...
BUSY(L) BUSY(R)
CE
BUSY (L) BUSY (R)
1
BUSY(R)
I
2954 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7015 RAMs.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the Mis pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT7015 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7015 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7015 RAM the busy pin is
an output if the part is used as a master (M/S pin =H), and the
busy pin is an input if the part used as a slave (M/S pin =L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a master/slave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
can be initiated with the Rm signal. Failure to observe this
timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
SEMAPHORES
The IDT7015 are extremely fast Dual-Port aKx9 Static
RAMs with an additional a address locations dedicated to
binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer's software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by GE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IOT7015 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7015's hardware semaphores, which provide a lockout mechanism without requiring complex programming.
6.12
17
IDT7015 S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7015 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment ~method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If itwas not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7015 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RIW) as they
would ~e used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore r~quest latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the aSSignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
6.12
18
IDT7015 SlL
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7015's Dual-Port
RAM. Say the 8K x 9 RAM was to be divided into two 4K x 9
blocks which were to be dedicated at anyone time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of memory.
To take a resource, in this example the lower 4K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were
successfully completed (a zero was read back rather than a
one), the leftprocessorwouldassumecontrolofthelower4K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore O. At this point, the software could choose to try
and gain control of the second 4K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processor§ to swap 4K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the 1/0 device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits"to
the CPU, both the CPU and the 1/0 devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
LPORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D>-1D
SEMAPHORE
REQUEST FLIP FLOP
Q~Q
WRITE---tL..._ _.
Dt WRITE
D>
.L......-_.....I
SEMAPHORE.
READ
• SEMAPHORE
READ
2954drw 20
Figure 4. IDT7015n016 Semaphore Logic
6.12
19
IDT7015 s/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAMS
MILITARY "ND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Y:lank
I
PF
L...---------iIJG
L..-_ _ _ _ _ _ _ _ _ _ _....,
~
________________________
15
17
20
25
35
S
IL
~J
1 . - - - - - - - - - - - - - - - - - 7015
1
6.12
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
80-pin TQFP (PN80-1)
68-pin PGA(G68-1)
68-pin PLCC (J68-1)
Commercial Only }
Commercial Only
Commercial Only
.
Speed In Nanoseconds
Standard Power
Low Power
72K (8K x 9) Dual-Port RAM
2954 drw21
20
PRELIMINARY
IDT7016S/L
HIGH-SPEED
16K X 9 DUAL-PORT
G
STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001 V
electrostatic discharge
• TTL-compatible, single 5V (±1 0%) power supply
• Available in ceramic 68-pin PGA, 68~pin PLCC, and an
80-pin TQFP
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 25/35ns (max.)
- Commercial:15117/20/25/35ns (max.)
• Low-power operation
- IDT7016S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7016L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7016 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading
more than one device
• Mis = H for BUSY output flag on Master
MIS = L for BUSY input on Slave
DESCRIPTION:
The IDT7016 is a high-speed 16K x 9 Dual-Port Static
RAMs. The IDT7016 is designed to be used as stand-alone
144K bit Dual-Port RAMs or as a combination MASTER/
SLAVE Dual-Port RAM for 18-bit-or-more word systems.
FUNCTIONAL BLOCK DIAGRAM
-
1I
1
r-
~
I
A
"-
~
-]I
La
"
A
MEMORY
ARRAY
"/
l
RIWl :
t
I
>-
A
'l"
II
Address
Decoder
L-
··
I
~CER
.093
IRIWR
Js 11
~
3190 drw 01
NOTES:
1_ In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSYis input.
2. BUSY outputs and INT outputs are non-tristated push-pull drivers_
MILITARY AND COMMERCIAL TEMPERATURE RANGES
«:11995 Integrated Device Technology, Inc.
BUSYR (1,2)
"
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEl '
--~
OE _
)
1/0
Control
~r •
+
~)
~
I---
I/O
Control
Address
Decoder
11
r
1
1
··
1
'---
J
APRIL 1995
6.13
DSC-1296/-
IDTI016 SIL
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Using the lOT MASTERISLAVE Dual-Port RAM approach in
18-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
The 10T7016 is packaged in a ceramic 68-pin PGA, a 64pin PLCC and an 80-pinTQFP (Thin Quad FlatPack). Military
grade product is manufactured in compliance with the latest
revision of MIL-STO-883, Class B, making it ideally suited to
military temperature applications demanding the highest level
of performance and reliability.
PIN CONFIGURATIONS
IDT7016
(16K x 9)
J68-1
PLCC
(1)
TOP VIEW
A5L
A4L
A3L
A2L
A1L
AOL
INTL
BUSYL
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
Ri~ht
Left Port
Chip Enable
RtWl
RtWR
Read/Write Enable
OEl
OER
Output Enable
AOl-A13l
AOR-A13R
Address
IIOOl-I/OSl
IIOOR -IIOSR
Data Input/Output
SEMl
SEMR
Semaphore Enable
INTl
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
NOTES:
1. This text does not imply orientation of Part-Mark.
Names
Port
CER
CEl
Master or Slave Select
VCC(I)
Power
GND(2)
Ground
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
6.13
3190 tbl 01
2
IDT7016 s/L
HIGH·SPEED 16K x 9 DUAL·PORT STATIC RAMS
NC
1I02l
1/03l
1/04l
I/0Sl
GND
1/06l
1/07l
Vee
NC
GND
I/OOA
1/01 A
1/02R
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NC
ASl
A4l
A3l
A2l
A1l
AOl
INTL
IDT7016
(16K X 9)
PN·80
TQFP
TOPVIEW(1)
1/03 A
MIS
BUSYA
INTR
AOA
A1A
A2A
A3A
I/OSA_
1/06A- 19
NC_
NC
NC
Vee
50
51
11
ASl
53
10
A7l
55
09
A11l
59
07
vee
61
06
OEL
67
03
41
INTL GND BUSYF
A1l
40
38
INTR
39
36
A1R
37
AOA
/A
A3R
35
A2A
34
A4R
32
A7R
A8l
56
30
58
28
IDT7016
(16Kx9)
A12l
A13l
62
G68-1
68-PIN PGA
26
TOPVIEW(1)
24
N/C
22
SEMR
RIWL
20
66
1
5
3
2
4
GND
C
9
11
1/07L GND
1/01R
13
vee
23
CER
21
AlWR
19
/l04R
/l07R
16
17
12
I/OOR
1/02R I/03A 1/05R 1/06R
D
E
F
H
A13R
18
10
G
14
A12R
25
15
Vee
8
A10R
OER
1/06l
6
1/03l 1/05l
B
7
A8R
27
GND
64
A6R
29
A11R
CEl
A5R
33
31
A9R
A10l
1/01l 1/02l 1/04l
•
NOTES:
1. This text does not imply orientation of Part-Mark.
43
45
MIS
I/00l 1/08l
68
02
42
54
SEML
65
04
A3l
44
AOl BUSYl
60
N/C
63
05
46
A2l
47
49
A6l
A9l
57
08
52
48
A4l
J
K
1/08R
L
INDEX
3190 drw 04
6.13
3
IDT7016 SIL
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
Outputs
CE
RNI
OE
SEM
1/00-8
H
X
H
High-Z
Deselected: Power-Down
Write to Memory
Mode
L
L
X
X
H
DATAIN
L
H
L
H
DATAoUT
X
X
H
X
High-Z
Read Memory
Outputs Disabled
NOTE:
1. Condition: AOL - A13L is not equal to AOR - A13R
3190 tbl 02
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
CE
RNI
OE
SEM
1/00-8
H
H
L
L
DATAouT
Read Semaphore Flag Data Out
H
;-
DATAIN
Write 1/00 into Semaphore Flag
X
X
X
L
L
Mode
-
L
Not Allowed
3190 tbl 03
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Terminal Voltage -0.5 to +7.0
with Respect
toGND
Military
-0.5 to +7.0
Unit
Grade
V
Military
Commercial
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
Ambient
Temperature
GND
Vee
-55°C to +125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
3190 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTES:
3190 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
- conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + O.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to $.. 20mA forthe period OfVTERM ~ Vcc
+O.5V.
Min.
Typ.
Max.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0(2)
V
Input Low Voltage
-0.5(1)
0.8
V
VIL
Parameter
-
NOTES:
1. VIL~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.5V.
CAPACITANCE (TA =+25°C, f
Unit
3190 tbl 06
=1.0MHz, for TQFP
Paekage)(1)
Conditions(2)
Max.
CIN
Input Capacitance
VIN = 3dV
9
pF
COUT
Output
Capacitance
VOUT
10
pF
Symbol
Parameter
=3dV
Unit
3190 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
output signals switch from OV to 3V or from 3V to OV .
6.13
4
1017016 SlL
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vee = S.OV ± 10%)
7016 S
Symbol
Parameter
7016 L
Test Conditions
Min.
Max,
Min,
Max,
Unit
10
-
5
JlA
10
-
5
uA
1IL11
Input Leakage Current(5)
Vee = S.SV, VIN = OV to Vee
IILOI
Output Leakaqe Current
CE = VIH VOUT = OV to Vee
-
VOL
Output Low Voltage
IOL= 4mA
-
0.4
-
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-
V
NOTES:
At Vee = 2.0V, Input leakages are undefined.
3190 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1) (Vee = S.OV ± 10%
Symbol
Icc
1881
1882
Parameter
Test
Condition
Version
-
-
170
170
310
260
170
170
310
260
-
-
-
-
25
25
60
50
25
25
60
50
S
-
-
L
-
-
-
-
CE = VIL, Outputs Open
SEM= VIH
f = fMAX(3)
MIL.
COM'L.
S
L
Standby Current
(Both Ports - TTL
Level Inputs)
CER = CEL = VIH
SEMR = SEML = VIH
f =fMAX(3)
MIL.
COM'L.
S
L
S
L
Standby Current
CE'A'=VIL and CE"8' = VIH(5)
MIL.
(One Port -
Active Port Outputs Open
f = fMAX(3)
TTL
S
I
COM'L.
SEMR = SEML = VIH
1884
-
Dynamic Operating
Current
(Both Ports Active)
Level Inputs)
1883
7016X15
7016X17
COM'LONLY COM'LONLY
Typ,(2) Max, T~p,(2) Max, Unit
-
-
S
105
190
105
190
L
105
160
109
160
S
L
-
-
-
-
-
Full Standby Current
(Both Ports - All
Both Ports CEL and
CER ~ Vee - 0.2V
MIL.
CMOS Level Inputs)
VIN ~ Vee - 0.2V or
VIN ~ 0.2V, f = d 4)
SEMR = SEML > Vee - 0.2V
COM'L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
CE'A'< 0.2V and
CE'8'~ Vee - 0.2V(5)
MIL.
S
L
-
-
-
-
-
CMOS Level Inputs)
SEMR = SEML ~ Vee - 0.2V
S
L
100
100
100
100
170
140
VIN ~ Vee - 0.2V or VIN ~ 0.2V
Active Port Outputs Open,
f = fMAX(3)
COM'L.
-
170
140
-
mA
mA
mA
mA
mA
-
NOTES:
3190 tbl 09
1. "X" in part numbers indicates power rating (8 or L)
o
2. Vee SV, TA +2S e, and are not production tested. leeDe 120mA(typ.)
3. At f fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRe. and using "AC Test Conditions·
of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite of port "A".
=
=
=
=
=
6.13
5
IDTI016 S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY !\ND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1){Continued) (vcc= 5.0V ± 10%)
7016X20
7016X25
7016X35
Test
Symbol
lee
ISBl
ISB2
Parameter
Typ.(2)
Max. Typ.(2) Max. Unit
CE = Vll, Outputs Open
SEM = VIH
MIL.
S
L
-
-
155
155
340
280
150
150
300
250
(Both Ports Active)
f = fMAX(3)
COM'L.
S
L
160
160
290
240
155
155
265
220
150
150
250
210
Standby Current
(Both Ports - TTL
CEl = CER = VIH
SEMR = SEMl = VIH
MIL.
S
L
-
-
16
16
80
65
13
13
80
65
Level Inputs)
f = fMAX(3)
COM'L.
S
L
20
20
60
50
16
16
60
50
13
13
60
50
CE"A"=Vll and CE"B"=VIH(5) MIL.
S
-
215
85
190
Active Port Outputs Open
f = fMAX(3)
L
-
-
90
(One Port -
90
180
85
160
TTL
COM'L.
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee - 0.2V
MIL.
CMOS Level Inputs)
VIN > Vee - 0.2V or
COM'L.
VIN ~ 0.2V, f = 0(4)
SEMR = SEMl > Vee - 0.2V
Full Standby Current
(One Port-All
CE"A"< 0.2V and
CE"B"? Vee - 0.2V(5)
CMOS Level Inputs)
SEMR = SEMl ~ Vee - 0.2V
MIL.
VIN ~ Vee - 0.2V or
COM'L.
VIN~
0.2V
Active Port Outputs Open,
f = fMAX(3)
S
95
180
90
170
85
155
L
95
150
90
140
85
130
S
L
-
-
-
1.0
0.2
30
10
1.0
0.2
30
10
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
S
L
-
-
85
85
200
170
80
80
175
150
S
90
155
85
145
80
135
L
90
130
85
120
80
110
NOTES:
1. "X" in part numbers indicates power rating (S or L)
2. Vcc 5V, TA +2S o C, and are not production tested. ICCDC 120mA(typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1ItRC, and using
"AC Test Conditions" of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite of port "A".
=
=
mA
mA
Standby Current
SEMR = SEMl = VIH
ISB4
Max.
Dynamic Operating
Current
Level Inputs)
ISB3
Typ.(2)
Version
Condition
mA
mA
mA
3190lbl10
=
=
OUTPUT LOADS AND AC TEST
CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels 1.5V
Output Reference Levels
Output Load
1.5V
Figure 1 & 2
DATAoUT
8USY----_-~~~
INT
3470
30pF
3190 drw 05
Figure 1. AC Output Test Load
6.13
DATAoUT--_---K
)(
MATCH
twp
~K
RiVi-A,
/,/
I tDH
I---tDW
)K
DATAIN'A'
tAPS
ADDR's'
BUSY's'
VALID
(1)
) K~
MATCH
\
f--
toDA.::p: toDD
"[--'"
tWDD
)~
DATAoUT's'
tDDD
(3)
3190 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL
2. CEl = CER = VIL
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), the BUSY is an input (BUSY=VIH). For this example, BUSY="don't care".
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
twp
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
6,13
3190 drw 14
13
PRELIMINARY
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
IDT7016 S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) {MIS
ADDR"A"
and "B"
=><
><=
ADDRESSES MATCH
.~s~
CE"A"
=VIH)
t-" 1 t:reoc}
CE"B"
AC
BUSY"B"
3190 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(MIS VIH)
=
ADDR"A"
ADDRESS "N"
ADDR"B"
MATCHING ADDRESS "N"
'MA
=1______ 1t_'OA
3190 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7016X15
COM'LONLY
Max.
Min.
Parameter
Symbol
IDT7016X17
COM'LONLY
Min
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
1WR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
Parameter
Symbol
-
0
-
ns
0
-
ns
15
-
17
ns
17
ns
15
IDT7016X20
IDT7016X25
IDT7016X35
Min.
Max.
Min.
Max.
Min.
Max.
Unit
-
0
-
0
0
-
0
-
ns
-
25
ns
25
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
-
20
-
20
tlNR
Interrupt Reset Time
-
20
-
20
NOTE:
1. "X" in part numbers indicates power rating (S or L).
ns
ns
2739 tbl14
6.13
14
1017016 S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(l)
~--------------------mc------------------~
ADDR'A'
--~
CE'A'
R/W'A'
INT'B'
',"S,3)
=t-------------------------
3190 drw 17
~------------------ tRC------------------~
(2)
INTERRUPT CLEAR ADDRESS
ADDR'B'
CE'B'
liN" (3) } . . . . - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
3190 drw 18
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or RlW) is asserted last.
4. Timing depends on which enable signal (CE or RlW) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I -
INTERRUPT FLAG(l)
Left Port
Right Port
RlWL
eEL
DEL
A13L-AoL
INTL
RlWR
CER
L
L
3FFF
X
X
X
X
L(2)
X
X
X
X
X
X
X
X
X
X
L
L
3FFF
H(3)
L(3)
L
L
X
3FFE
X
Set Left INTL Flag
X
L
L
3FFE
H(2)
X
X
X
X
X
Reset Left INTL Flag
X
X
OER A13R-AoR iN'fR
NOTES:
Function
Set Right INTR Flag
Reset Right INTR Flag
3190 tbl15
=
=
1. Assumes 8USYL 8USYR VIH.
2. If 8USYL = VIL, then no change.
3. If 8USYR VIL, then no change.
=
6.13
15
IDT7016 S/L
PRELIMINARY
MILITARY ~ND COMMERCIAL TEMPERATURE RANGES
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
TRUTH TABLE 11- ADDRESS BUSY
ARBITRATION
Outputs
Inputs
AOL-A13L
AOR-A13R
eEL
CER
X
X
X
NO MATCH
H
L
H
X
L
BUSYL(1) BUSYR(1)
Function
H
H
H
Normal
MATCH
H
H
H
MATCH
(2)
(2)
Write Inhibit(3)
MATCH
Normal
Normal
NOTES:
3190 tbl16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDT7016 are push-pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable Inputs of this port. "H" if the inputs to th~osite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR Low will result. BUSYL and BUSYR outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
=
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
Do - 08 Left
Status
Do - 08 Right
Semaphore free
1
No Action
1
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
'~1
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes
" to Semaphore
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016.
3190 tbl17
FUNCTIONAL DESCRIPTION
The IDT7016 provides two ports with separate control,
address and 1/0 pins that permit independent access for reads
or- writes to any location in memory. The IDT7016 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE
High). When a port is enabled, access to the entire memory
array is permitted.
memory location 3FFF and to clear the interrupt flag (INTR),
the right port must access memory location 3FFF. The
message (9 bits) at 3FFE or 3FFF is user-defined since it is in
an addressable SRAM location. If the interrupt function is not
used, address locations 3FFE and 3FFF are not used as mail
boxes but are still part of the random access memory. Refer
to Table I for the interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is asserted when the right port
writes to memory location 3FFE where a write is defined as
the CE Rm VIL per the Truth Table. The left port clears
the interrupt by an address location 3FFE access when CER
=OER =VIL, Rm is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to
=
=
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.13
16
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7016 S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
r--
MASTER
Dual Port
.BAM..
1
I
CE
SLAVE
Dual Port
.BAM..
CE
Cl
0
uw
BUSY (L) BUSY(R)
BUSY (L) BUSY (R)
a:
r-w
Cl
""--
1
MASTER
Dual Port
.BAM..
BUSY (L)
SLAVE
CE
Dual Port
BAM..
BUSY(L) BUSY(R)
CE
BUSY (L) BUSY (R)
1
BUSY(R)
I
3190 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7016 RAMs.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
. desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT7016 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7016 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7016 RAM the busy pin is
an output if the part is used as a master (MIS pin =H), and the
busy pin is an input if the part used as a slave (MIS pin =L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a masterlslave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
can be initiated with the Rm signal. Failure to observe this
timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
SEMAPHORES
The IDT7016 are extremely fast Dual-Port 16Kx9 Static
RAMs with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer's software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT7016 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7016's hardware semaphores, which provide a lockout mechanism without requiring complex programming.
6.13
17
IDT7016 S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7016 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7016 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RiW) as they
would be used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
a
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
6.13
18
1017016 S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7016's Dual-Port
RAM. Say the 16K x 9 RAM was to be divided into two 8K x
9 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 8K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore O. At this point, the software could choose to try
and gain control of the second 8K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the JlO device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the 1/0 devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
LPORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D>-1D
SEMAPHORE
REQUEST FLIP FLOP
Q~Q
D>
.L--_.....Dt WRITE
WRITE-.I....____.
SEMAPHORE.
READ
• SEMAPHORE
READ
3190 drw 20
Figure 4. 1017016 Semaphore Logic
6.13
19
IDT7016 S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAMS
PRELIMINARY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process!
Temperature
Range
Y:lank
I
PF
L-----------iIJG
15
17
L-_ _ _ _ _ _ _ _ _ _ _~ 20
25
35
I LS
--1
1.-.._ _ _ _ _ _ _ _ _ _ _ _ _ _
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
80-pin TQFP lPN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-i)
Commercial Only }
Commercial Only
Commercial Only
Speed
.
In
Nanoseconds
Standard
Power
Low
Power
1
7016
144K (16K x 9) Dual-Port RAM
3190 drw 21
6.13
20
(;)®
IDT7133SAlLA
IDT7143SAlLA
CMOSDUA~PORTRAMS
32K (2K x 16-8IT)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
Military: 35/45/55170/90ns (max.)
Commercial: 25/35/45/55170/90ns (max.)
• Low-power operation
IDT7133/43SA
Active: 500 mW (typ.)
Standby: 5mW (typ.)
IDT7133/43LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Versatile control for write: separate write control for
lower and upper byte of each port
• MASTER IDT7133 easily expands data bus width to 32
bits or more using SLAVE IDT7143
• On-chip port arbitration logic (IDT7133 only)
• BUSY output flag on IDT7133; BUSY input on IDT7143
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in 68-pin ceramic PGA, Flatpack, and PLCC
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
The IDT713317143 are high-speed 2K x 16 Dual-Port Static
RAMs. The IDT7133 is designed to be used as a stand-alone
16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM
together with the IDT7143 "SLAVE" Dual-Port in 32-bit-ormore word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 32-bit-or-wider memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic. '
Both devices provide two independent ports with separate
control, address, and 110 pins that permit independent, asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each port typically consuming 200JlW for a 2V
battery.
The IDT713317143 devices have identical pinouts. Each is
packed in a 68-pin ceramic PGA, 68-pin flatpack, and 68-pin
PLCC. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
RlWlUB
aa
-.__--f"____
----++...---..q
RlWlLB
r-1----__.--
RlWRUB
I>---..-+-t---
RlWRLB
~-------4
~--------.
~
~-----~~----~
00. ----;::::::::::______-1---,
r-;;;:-'"-"1-------4-!----.''--
1I0Sl· I/OIsl -~#-------r-'-;;:;-"'t
I/Ool - 1/07l -~"*---------L~~:::JC:
BUSy~l)
I/OsR· I/OIsR
1--------+--.'-- I/OoR· 1/07R
~/"---r--'
BUSYR(I)
AIOl
AIOR
AOl
AOR
NOTES:
1. IDT7133 (MASTER): BUSY is
open drain output and requires
pull-up resistor.
IDT7143 (SLAVE): BUSY is
input.
2. LB LOWER BYTE
3. UB UPPER BYTE
aa \ - - - - - - - + 1
ARBITRATION
LOGIC
(IDT7133 ONLY)
=
=
2746drw 01
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
«:>1995 Integrated Device Technology, Inc.
APRIL 1995
DSC-1233P.
6.14
1
6
IDT7133SAlLA, IDT7143SAILA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
PIN
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATIONS(1,2,3)
INDEX
L..J L.....J L..J L-.I L-.I L-.I L..J L-.I
9 8 7
I/09L
I/010L
I/011L
I/012L
I/013L
I/014L
I/015L
654 3
] 10
]
]
]
]
]
]
VCC(1)
]
GND(2) ]
I/OOR ]
I/01R ]
I/02R ]
I/03R ]
I/04R· ]
I/05R ]
I/06R ]
I/07R ]
2
I I
I I
LJ
L-.I L..J L-.I L..J L-.I L..J L-.I L..J
68 67 66 65 64 63 62 61
1
1.1
12
13
14
60
57
15
IDT7133/43
J68-1
16
&
F681
17
18
PLCC/FLATPACK
TOPVIEW(4)
19
20
21
22
23
24
25
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A6L
A5L
A4L
A3L
A2L
A1L
AOL
BUSYL
CEL
CER
BUSYR
AOR
A1R
A2R
A3R
A4R
A5R
~~~~~~~~~~~~~~~~~
2746 drw02
NOTES:
1. Both Vcc pins must be connected to the supply to assure
reliable operation.
2. Both GND pins must be· connected to the supply to assure
reliable operation.
3. UB Upper Byte, LB Lower Byte
4. - This text does not indicate orientation of the actual part-marking.
=
=
6.14
2
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONTINUED)(1,2,3)
51
50
A5l
A6l
11
53
52
49
A7l
10
Aal
09
55
Al0l
08
57
56
RMhB OEl
07
59
58
VCC(l) RJWlUB
61
A2l
43
CEl
AOl
40
CEA
41
39
BUSYA
36
38
AOA
A1A
A2A
37
A3A
28
IDT7133143
GU68-1
68
01
•
/
Pin 1
Designator A
29
24
22
1/04l
1/06l
2
1/010l
B
5
I/0lll
11
9
1/015l GND(2) 1/01A
7
1/013l
4
6
8
1/012l 1/014l VCc(l)
10
I/OOA
D
F
C
E
13
15
1/015A
23
1/012A
3
OEA
25
1/014A
1/09l
• A9A
26
27
GND(2) RIWAUB
PGA (4)
TOP VIEW
1
1I0al
A7A
31
RIWAlB
66
02
A6A
33
AlaR
1/02l
1I07l
34
A5A
30
64
67
35
A8R
1/00l
1/05l
A4A
32
62
65
03
45
BUSYl
A9l
1/03l
04
47
A4l
42
44
All
60
63
05
46
54
I/0ll
06
4a
A3l
1/013A
20
21
1/010R
1/011 A
18
19
1/03A
1/05R
I/0aR
12
1/02A
14
1/04R
16
1/06A
17
1/07A
G
H
J
K
1/09R
L
2746 drw 03
PIN NAMES
Left Port
Right Port
Names
CEl
CEA
Chip Enable
RlWlUB
RfWAUB
U~per
RJWllB
RIWAlB
Lower Byte ReadlWrite Enable
Byte ReadlWrite Enable
OEl
OEA
Output Enable
AOl-Al0l
AOA - AlaR
Address
I/OOl - 1/015l
I/OOR - 1/015R
Data InpuVOutput
BUSYl
BUSYR
Busy Flag
Vee
Power
GND
Ground
NOTES:
2746 tbl 01
1. Both Vee pins must be connected to the supply to assure reliable operation.
2. Both GND pins must be connected to the supply to assure reliable operation.
3. UB Upper Byte, LB Lower Byte
4. This text does not indicate orientation of the actual part-marking.
=
=
6.14
3
IDT7133SAILA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCI.AL TEMPERATURE RANGES
CAPACITANCE (TA =+25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1}
Symbol
VTERM(2)
Rating
Commercial
Terminal Voltage -0.5 to +7.0
with Respect
toGND
Military
Unit
-0.5 to +7.0
V
TA
Operating
TemRerature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT(3)
Power
Dissipation
2.0
2.0
W
DC Output
Current
50
lOUT
Parameter<1)
Symbol
Max.
Unit
CIN
Input CapaCitance
VIN = OV
11
pF
COUT
InpuVOutput
Capacitance
VOUT=OV
11
pF
NOTE:
2746 tbl 03
1. This parameter is determined by device characterization but is not
production tested.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
50
Conditions
mA
Military
Commercial
NOTES:
2746 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + O.5V for more than 25% of the cycle time
or 1Ons maximum, and is limited to ~ 20mA for the period of VTERM ~ Vcc
+O.5V.
Ambient
Temperature
GND
Vee
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
2746 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
-
6.0
V
VIL
Input Low Voltage
-
0.8
V
2.2
-0.5(1)
NOTES:
1. VIL (min.) -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.5V.
=
6.14
Max. Unit
2746 tbl 05
4
IDT7133SAlLA,IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Either port, VCC = 5.0V +
- 10%)
IDT7133SA
IDT7143SA
Symbol
IDT7133LA
IDT7143LA
Test Conditions
Min.
Max.
Min.
Max.
Unit
=5.5V, VIN =OV to Vee
=VIH, VOUT =OV to Vee
IOl =4mA
IOl =16mA
-
10
5
~A
5
~A
0.4
V
0.5
-
0.5
V
-
2.4
Parameter
lIul
Input Leakage Current(1)
Vee
IlLOI
Output Leakage Current
CE
VOL
Output Low Voltage (1/00-1/015)
VOL
Open Drain Output Low Voltage
(BUSY)
VOH
Output High Voltage
IOH
=-4mA
10
0.4
2.4
-
NOTES:
V
2746 tbl 06
1. At Vcc < 2.0V, input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3) (VcC=5.0V± 10%)
7133X25(1)
7143X25(1)
Test
Symbol
lee
ISB1
Parameter
Condition
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max.
Version
Typ.(2) Max. Unit
S
L
250
230
330
300
240
220
325
295
230
210
320
290
230
210
315
285
230
210
310 mA
280
(Both Ports Active)
f = fMAX(4)
COM'L. S
L
250
230
300
270
240
220
295
265
230
210
290
260
230
210
285
255
230
210
280
250
Standby Current
(Both Ports - TIL
CEl and CER = VIH
f = fMAX(4)
MIL.
S
L
25
25
90
80
25
25
85
75
25
25
80
70
25
25
80
70
25
25
75
65
COM'L. S
25
75
25
75
25
?~
80
70
25
I
?~
fl~
?~
fl~
?~
70
60
25
25
70
60
S
mA
Standby Current
(One Port-TIL
CE"A" = Vil and
CE"B" = VIH(5),
MIL.
140
120
230
210
130
110
220
200
120
100
210
HlO
120
100
210
190
120
100
200
L
Level Inputs)
f =fMAX(4), Active
Port Outputs Open
COM'L. S
L
140
120
200
180
130
110
190
170
120
100
190
170
120
100
180
160
120
100
180
160
MIL.
1
0_2
30
10
1
30
10
1
O?
30
10
1
O?
O?
30
10
1
02
30
10
1
0.2
15
4
1
0.2
15
4
1
0.2
15
4
1
0.2
15
4
1
0.2
15
4
S
140
220
130
210
120
200
120
200
120
190 mA
VIN ~ Vee - 0.2V or
VIN < 0.2V, f = 0(5)
S
II
COM'L. S
L
MIL.
Full Standby Current CE"A" < 0.2V and
CE"B" ~ Vee - 0.2V(6)
(One Port - All
CMOS Level Inputs) VIN ~ Vee - 0.2V or
VIN.s: 0.2V
Active Port Out~uts
Open, f = fMAX 4)
mA
180
L
120
200
110
190
100
180
100
180
100
170
COM'L. S
140
190
130
180
120
180
120
170
120
170
L
120
170
110
160
100
160
100
150
100
150
NOTES:
1.
2.
3.
4.
7133X70/90
7143X70/90
MIL.
CMOS Level Inputs)
ISB4
7133X55
7143X55
CE= Vil
Outputs Open
Full Standby Current Both Ports CEl &
(Both PortsCER ~ Vee - 0.2V
ISB3
7133X45
7143X45
Dynamic Operating
Current
Level Inputs)
ISB2
7133X35
7143X35
mA
2746 tbl 07
Commercial only, O°C to +70°C temperature range.
Vcc SV. TA +2SoC for Typ., and are not production tested. leeDe 180mA (Typ.)
"X" in part numbers indicates power rating (SA or LA)
At f fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 11 IRe. and using "AC Test Conditions"
of input levels of GND to 3V.
S. f 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
=
=
=
=
=
6.14
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS
(LA Version Only) VLe = O.2V, VHC = Vee - O.2V
IDT7133LAIIDT7143LA
Symbol
Test Condition
Parameter
Vcc for Data Retention
Vcc
ICCDR
Data Retention Current
CE~VHC
I
VIN ~ VHC or ~ VLC
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
Typ.
2.0
-
MIL.
-
100
4000
COM'L.
-
100
1S00
=2V
VDR
tCDR(3)
Min.
I
0
tRC(2)
Max.
-
-
-
NOTES:
Unit
V
~A
ns
ns
2746 tbl 08
=
1. Vcc = 2V, TA +25°e, and are not production tested.
2. tRG Read Cycle Time
3. This parameter is guaranteed but is not production tested.
=
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDR~
2V
VDR
2746 drw 04
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
Sns
Input Timing Reference Levels
1.SV
1.SV
Output Reference Levels
See Figures 1, 2 & 3
Output Load
2746 tbl 09
SV
SV
_
DATAoUT
----~----.---~
77S0
30pF
Figure 1. Output Load
12700
BUSY~
DATAoUT
SpF*
Figure 2. Output Load
(for tLZ, tHZ, twz, tow)
30 PF
1
2746 drw 05
Figure 3. BUSY Output Load
(IDT7133 only)
"Including scope and jig
6.14
6
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
I
Symbol
I
IDT7133X25(2) IDT7133X35
IDT7143X25(2) IDT7143X35
Min. Max. Min. Max.
Parameter
IDT7133X45
IDT7143X45
Min. Max.
IDT7133X55 IDT7133X70/90
IDT7143X55 IDT7143X70/90
Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
45
-
55
-
tAA
Address Access Time
25
-
45
-
70/90
35
45
55
-
70/90
ns
tAOE
Output Enable Access Time
-
25
-
55
Chip Enable Access Time
-
35
lACE
-
30
-
40/40
ns
25
15
20
70/90
tOH
Output Hold from Address Change
0
-
0
-
010
0
0
-
0
Output Low-Z Time(l. 3)
-
0
tLZ
0
-
5
-J
SIS
tHZ
Output High-Z Time(l, 3)
-
15
-
20
-
20
-
tpu
Chip Enable to Power Up Time(3)
0
-
0
-
0
tPD
Chip Disable to Power Down Time(::!)
-
50
-
50
-
NOTES:
20
010
-
0
-
50
-
50
-
-
-
ns
ns
ns
ns
25/25
ns
-
ns
50/50
ns
2746 tbll0
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2, and 3).
2. O°C to +70°C temperature range only.
3. This parameter is guaranteed by device characterization, but is not production tested.
4. "X" in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1,2,4)
tRC
=1
~~-------------_-_-_- -_-~-~------------~.~I
ADDRESS
_ _MA
___
...
-~------- tOH
• '
PREVIOUS DATA VALID
DATAoUT
BUSYOUT
tBOD
(3,4)
2746 drw 06
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1,3)
1+------------tACE
~--------tAOE(4)-----_+I
1+-______
tLZ~(I)~-~
DATAoUT ------------~------------~~----~&_E_~~
1+-__________ tLZ(~I)------~I'-~~~--------_+------~~--~1
CURRENT
Icc ---------------+~----------------------------------------------~
50%
IS8 - - - - - - - - - '
2746 drw07
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is deasserted last, OE or CEo
3. tBoo delay is required onlyin a case where the opposite port is completing a write operation tothe same address location. Forsimultaneous read operations,
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, lAOE, tACE, 1M, or tBoo.
5. RiW =-VIH, and the address is valid prior to others coincidental with CE transition Low.
6.14
7
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
IDT7133x25(2)
IDT7143x25(2)
Symbol
Parameter
Min.
Max.
IDT7133x35
IDT7143x35
Min. Max.
IDT7133x45
IDT7143x45
Min. Max.
IDT7133x55 IDT7133x70/90
IDT7143x55 IDT7143x70/90
Min. Max_
Min. Max. Unit
WRITE CYCLE
twc
Write Cycle Time\4J
25
tEW
Chip Enable to End-of-Write
20
tAw
Address Valid to End-of-Write
20
tAS
Address Set-up Time
twP
Write Pulse Width(6)
0
20
tWR
Write Recovery Time
0
tDW
Data Valid to End-of-Write
15
-
25
-
35
25
25
0
55
30
-
0
30
45
30
0
-
0
20
-
20
70/90
40
-
-
0
-
-
40
25
-
-
40
0
ns
0/0
-
50/50
-
ns
0/0
-
ns
50/50
50/50
30/30
tHZ
Output High-Z Time(1, 3)
-
15
-
20
-
20
tDH
Data Hold Time(5)
0
-
0
-
5
-
5
twz
Write Enable to Output in High-Z(l, 3)
-
15
-
20
-
20
-
20
-
tow
Output Active from End-of-Write(l, 3, 5)
0
-
0
-
5
-
5
-
5/5
20
-
-
5/5
25/25
25/25
-
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
2746 tbltt
1. Transition is measured ±SOOmV from Low- or High-impedance voltage with the Output Test Load (Figures 2).
2. ooe to +70oe temperature range only.
3. This parameter is guaranteed but not tested.
4. For MASTER/SLAVE combination, twc = tBAA + tWR +twp, since R!W= VIL must occur aftertBAA.
5. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tow values
will vary over voltage and temperature, the actual tOH will always be smaller than the actual tow.
6. This parameter is determined by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
7. "X" in part number indicates power rating (SA or LA).
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
Symbol
Parameter
IDT7133x25(1 ) IDT7133x35
IDT7143x25(1 ) IDT7143x35
Min. Max. Min. Max.
IDT7133x45
IDT7143x45
Min. Max.
IDT7133x55 IDT7133x70/90
IDT7143x55 IDT7143x70/90
Min. Max. Min. Max. Unit
BUSY TIMING (For MASTER IDT7133)
tBAA
BUSY Access Time from Address
tBDA
BUSY Disable Time from Address
tBAC
BUSY Access Time from Chip Enable
tBOC
BUSY Disable Time from Chip Enable
tWDD
Write Pulse to Data Delay(2)
tDDD
Write Data Valid to Read Data Delay(2)
tBOO
BUSY Disable to Valid Data(3)
tAPS
Arbitration Priority Set Up Time(4)
-
-
35
-
45
30
-
40
20
-
25
-
30
20
-
20
-
25
25
20
50
35
Note 3
60
45
Note 3
80
55
Note 3
-
50
40
35
30
80
55
Note 3
5
-
5
-
5
-
5
0
0
-
0
30
-
0
25
30
80
-
80
55
-
55
-
55/55
ns
45/45
ns
35/35
ns
30/30
ns
90/90
ns
70nO
ns
Note 3
ns
5/5
-
ns
-
0/0
-
ns
-
30/30
-
-
BUSY INPUT TIMING (For SLAVE IDT7143)
tWB
Write to BUSy(5)
tWH
Write Hold After BUSy(6)
20
-
tWDD
Write Pulse to Data Delay(2)
-
50
tDDD
Write Data Valid to Read Data Delay(2)
-
35
-
60
45
-
-
90/90
70nO
NOTES:
1. ooe to +70oe temperature range only.
2. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 8usy".
3. t BDD is calculated parameter and is greater of 0, twDD - twp (actual) or tDDD - tow (actual).
4 To ensure that the earlier of the two ports wins.
5. To ensure that the write cycle is inhibited on port "8" during contention on port "A".
6. To ensure that a write cycle is completed on port "8" after contention on port "A".
7. "X" in part number indicates powerrating (SA or LA).
6~4
ns
ns
ns
2746 tblt2
8
IDT7133SAlLA,IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (RlWCONTROLLED TIMING)(1,5,S)
twc
<
)
ADDRESS
)
K
.-tA~
/' f::'
tWR(4
tAW
~~
?f
tWp(2)
~~
.......
/'
Z
tHZ(7)
. . . - tWZ(7) ......
tLZ
DATAoUT
tHZ(7) . . .
I
tow
V
"
(4)
I........
l
/'
tOW-+-
DATAIN
(4)
)
f-
tJH
"
r
/'
2746 drw 08
WRITE CYCLE NO.2 (CE CONTROLLED TIMING)(1, 5)
twc
ADDRESS
)
K
)
K
tAW
_
DATAIN
tA~6)
/'
'}.
Z
tEW(2)
-------ICE
twR
tow
"III
tOH
2746 drw 09
NOTES:
1. RiW or CE must be high during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a CE VIL and a RiW VIL.
3. tWR is measured from the earlier of CE or RiW going High to the end of the write cycle.
4. Durin~is period, the I/O pins are in the output state, and input ~nals must not be applied.
5. If the CE low transition occurs simultaneously with or after the RJW low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or RIW) is asserted last.
7. This parameter is determined by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
S. If DE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the lID drivers to tum off and data
to be placed on the bus for the required tow. If DE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. RiW for either upper or lower byte.
=
=
6.14
9
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-8IT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
ADDR'A'
BUSy(1,2,3)
twc
---y (
)
MATCH
fC
twp
~
Rm'A'
K
/
4--
)(
DATAIN 'A"
/
~t
tow
VALID
tAPS(1)
)
ADDR"B'
K,
MATCH
""r----."
BUSY'B'
I-
tBOA
~
tBOO
twoo
)
DATAoUT'B'
toOO(4)
E
2746 drw 10
NOTES:
1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143).
2. eEL CER Vil
3. OE VIL for the reading port.
4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from port "A".
=
=
=
TIMING WAVEFORM OF WRITE WITH BUSY (MIS =VIL)
twp
BUSY'B'
(2)
2746 drw 11
NOTES:
1. tWH must be met for both 8USY input (SLAVE) and output (MASTER).
2. 8USY is asserted on port "8" blocking RiW 'B', until 8USY 'B" goes High.
3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.14
10
IDT7133SAlLA, IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY GETIMING (1)
ADDR 'A' AND 'B'
:::::
><=
==><_________
A_D_D_R_E_S_S_E_S_M_A_T_C_H_ _ _ _ _ _ _ _ _ _
-~11-tBAc1_--i--r-tBDcJ----=---==
BUSY'B'
2746 drw 12
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESSES (1)
....- - - tRC OR
ADDR'A'
twc
----~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR 'B"
BUSY'B'
mAA~ "_________tB_DA_-_-_-_-_~"1~,__- - - - -_ ___
~
,.f"
2746drw13
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(ID17133 only).
6.14
11
IDT7133SAlLA,IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The IDT7133/43 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7133143 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted. Non-contention READIWRITE
conditions are illustrated in Table 1.
RIGHT
LEFT
Rm
RiW
IDT7133
RiW
MASTER
BUSY
BUSY
'i-"Nv- +5V
ANI
+5V~
IDT7143
RfIN
SLAVE
BUSY LOGIC
' - - - - BUSY
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is "busy". The busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
BUSY I - - -
2746 drw 14
Figure 4. Busy and chip enable routing for both width and depth
expansion with the IDT7133 (MASTER) and the IDT7143 (SLAVE).
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by using the IDT7143
(SLAVE). In the IDT7143, the busy pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the BUSY pins high. If desired, unintended write
operations can be prevented to a port by tying the busy pin for
that port low. The busy outputs on the IDT7133 RAM are open
drain and require pull-up resistors.
WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS
When expanding an IDT7133/43 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7133 RAM the busy pin is
an output and on the IDT7143 RAM, the busy pin is an input
(see Figure 3).
Expanding the data bus width to 32 bits or more in a DualPort RAM system implies that several chips will be active at
the same time. If each chip includes a hardware arbitrator,
and the addresses for each chip arrive at the same time, it is
possible that one will activate its BUSYL while another
activates its BUSYR signal. Both sides are now busy and the
CPUs will await indefinately for their port to become free.
To avoid the "Busy Lock-Out" problem, lOT has developed
a MASTER/SLAVE approach where only one hardware
arbitrator, in the MASTER, is used. The SLAVE has BUSY
inputs which allow an interface to the MASTER with no
external components and with a speed advantage over other
systems.
When expanding Dual-Port RAMs in width, the writing ofthe
SLAVE RAMs must be delayed until after the BUSYinput has
settled. Otherwise, the SLAVE chip may begin a write cycle
during a contention situation. Conversely, the write pulse
must extend a hold time past BUSYto ensure that a write cycle
takes place after the contention is resolved. This timing is
inherent in all Dual-Port memory systems where more than
one chip is active at the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due to
BUSY from the MASTER.
6.14
12
IDT7133SAlLA,IDT7143SAlLA
CMOS DUAL-PORT RAMS 32K (2K
x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I - NON-CONTENTION READIWRITE CONTROU4)
LEFT OR RIGHT PORT(l)
RlWLB
R/WuB
CE
OE
1/00-7
1/08-15
X
X
X
X
H
Z
Z
Z
Z
L
L
L
X
X
X
DATAIN
DATAIN
L
H
L
L
DATAIN
DATAoUT
Data on Lower Byte Written into Memory(2), Data in Memory Output on
Upper Byte(3)
H
L
L
L
DATAoUT
DATAIN
Data in Memory Output on Lower Byte(3), Data on Upper Byte Written
into Memory(2)
H
Function
Port Disabled and in Power Down Mode, IS82, IS84
CER
=GEL =VIH, Power Down Mode, IS81 or IS83
Data on Lower Byte and Upper Byte Written into Memory(2)
L
H
L
H
DATAIN
Z
Data on Lower Byte Written into Memory(2)
H
L
L
H
Z
DATAIN
Data on Upper Byte Written into Memory(2)
H
H
L
L
H
H
L
H
DATAoUT DATAoUT
Z
Z
Data in Memory Output on Lower Byte and Upper Byte
High Impedance Outputs
NOTES:
1. AOL - Al0L # AOR - Al0R
2. If BUSY LOW, data is not writ1en.
3. If BUSY LOW, data may not be valid, see !woo and tODD timing.
4. "H" HIGH, "L" LOW, "X" Don't Care, "Z" High Impedance, "LB"
=
=
=
=
TRUTH TABLE I I ARBITRATION
=
=
=Lower Byte, "UB" =Upper Byte
ADDRESS BUSY
Inputs
AOl-Al0l
AOR-Al0R
2746 tbl13
Outputs
CEL
CER
BUSYl(l)
BUSYR(l)
X
NO MATCH
H
H
Normal
H
X
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
Function
NOTES:
2746 tbl14
1. Pins BUSYL and BUSYR are both outputs on the IDT7133 (MASTER). Both are inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally
inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If lAps is not met, either BUSYL or BUSYR LOW will result. BUSYL and BUSYR outputs can not be LOW
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
=
6.14
13
IDTI133SAlLA, IDTI143SAlLA
CMOS DUAL-PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXX
xx
XX
X
x
Device
Type
Power
Speed
Package
Process!
Temperature
Range
~:Iank
~
______________
J
~G
F
1.-------------------1
25
35
45
55
70
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
68-pin PLCC (J68-1)
68-pin PGA (GU68-1)
68-pin Flatplack (F68-1)
Commercial Only }
Speed in nanoseconds
90
~
________________________
~J
~
I
17133
~--------------------------------~17143
Low Power
Standard Power
32K (2K x 16-Bit) MASTER Dual-Port RAM
32K (2K x 16-Bit) SLAVE Dual-Port RAM
2746 drw 15
6.14
14
t;j
IDT7024S/L
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
more than one device
• M/S =H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Devices are capable of withstanding greater than 2001 V
electrostatic discharge.
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 84-pin PGA, quad flatpack, PLCC, and 100pin Thin Quad Plastic Flatpack
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 25/35/55/70ns (max.)
- Commercial: 17/20/25/35/55ns (max.)
• Low-power operation
- IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
FUNCTIONAL BLOCK DIAGRAM
RlWl
UBl
(
'\
I
'---.-
~I
~
d
I
~
Ij~
I/OSl-1/015l
1/0
Control
A11l
AOl
··
NOTES:
1. (MASTER):
BUSYis outp ut;
(SLAVE): B"O"SY
is input.
2. BUSY output S
and INToutp uts
are non-tri-stated
push-pull.
SEMl
\
INTL2
Address
Decoder
I
CEl.
OEl •
RiWl.
.11
~
"
..
~r
"
MEMORY
ARRAY
I/OOl-1/07 l
BUSy[1,2 )
~
Vt
~----v
r-O
~~
I/OSR-I/015R
1/0
Control
I/00R-I/07R
..
BUSy~1,2)
.11
"
V
'l
12
12
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
1'1
1
Mis
I
Address
Decoder
-
··
A11R
AOR
I
.CER
:OER
.R!WR
T
SEMR
INT~2)
2740 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1C1995 Integrated Device Technology. Inc.
6.15
APRIL 1995
DSC-104SI3
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7024 is a high-speed 4K x 16 Dual-Port Static
RAM. The IDT7024 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 32-bit or more word systems. Using the
lOT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
PIN CONFIGURATIONS
memory ~n automatic power down feature controlled by chip
enable ( CE) permits the on-Chip circuitry of each port to enter
a very low standby power mode.
Fabricated using lOT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500llW from a 2V
battery.
The IDT7024 is packaged in a ceramic 84-pin PGA, an 84pin quad flatpack and PLCC, and a 100-pin TQFP. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class S, making it ideally suited to
military temperature applications demanding the highest level
of performance and reliability.
INDEX
A7l
ASl
ASL
I/010L
A2L
AlL
AOL
IDT7024
J84-1
F84-2
TN'i'L
84-PIN PLCC I
FLATPACK
TOP VIEW (1)
BUS'i'L
GND
MIS
BUS'i'A
iN'i'R
Vee
AOA
AlA
A2A
A3R
A4A
ASA
ASR
I/03A
I/04R
I/OSR
I/OSR
I/OaR
N/C
N/C
N/C
N/C
ASL
A4L
V010L
I/OllL
V012L
I/013L
GND
A3L
IDT7024
PN100-l
IIOOR
VOlA
I/02A
100-PIN
TQFP
TOPVIEW(l)
A2L
AlL
AOL
iN'fL
BUSYL
GND
MIS
BUSYA
iNTA
Vee
AOA
AlA
A2A
I/03A
I/04A
I/OSA
V06A
N/C
N/C
N/C
N/C
A3A
A4A
N/C
N/C
N/C
N/C
NOTE:
1. This text does not indicate orientation of the actual part-marking_
6.15
2
IDT7024S/L
HIGH-SPEED 4K
x 16 DUAL-PORT STATIC RAM
63
11
61
I/07l
66
10
1/010l
09
47
50
UBl
53
46
LBl
CEL
Alll
44
N/C
RlWl
1/03R
BUSYl
Vee
IDT7024
G84-3
GND
32
84-PIN PGA
TOPVIEW(3)
GND
Vee
AOR
11
GND
2
1I09R
1101 OR
I/0llR
1I013R
1/012R
1/015R
1/014R
GND
Mis
All
30
INTR
BUSYR
27
RIWR
OER
23
SEMR
14
15
9
6
12
10
8
5
4
3
1/08R
INTl
36
A2R
7
1/07R
1/06R
AOl
26
1
84
A2l
34
29
1/04R
1/05R
A4l
37
31
28
83
82
39
35
80
81
A5l
A8l
A3l
78
1/02R
AlL
40
A6l
33
74
GND
I/0lA
43
41
73
77
79
42
A10l
A9l
52
Vee
45
38
1/014l
I/OOR
01
I/0ll
GND
70
76
02
1/03l
SEMl
1I012L
1/015l
03
49
57
71
75
04
1/06l
48
51
OEl
56
1/09l
1/013l
05
59
54
1/00l
68
72
06
55
1/02l
62
1/08l
I/0lll
07
58
1/04l
65
69
08
60
I/0Sl
64
67
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LBR
A5R
UBR
Al1R
16
CER
22
20
17
13
A1R
25
A8R
18
N/C
A4R
A6R
19
Al0R
A3R
24
21
A9R
A7R
K
L
~
A
B
0
C
E
F
G
H
J
Index
PIN NAMES
Left Port
Right Port
CEL
CER
Names
Chip Enable
RIWL
RIWR
ReadlWrite Enable
OEL
OER
Output Enable
AOL-AllL
AOR - AllR
Address
I/OOL - I/015L
I/OOR - I/015R
Data InpuVOutput
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
2740 tbll
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.15
3
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
Outputs
Mode
CE
RIW
OE
UB
LB
SEM
1108-15
1100-7
H
X
H
High-Z
High-Z
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
L
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
H
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
L
X
X
X
X
X
X
X
X
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAoUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
L
H
L
L
L
H
X
X
H
X
X
X
Deselected: Power-Down
DATAoUT Read Lower Byte Only
DATAoUT DATAoUT Read Both Bytes
High-Z
High-Z
Outputs Disabled
NOTE:
2740 tbl 02
1. AOL-AllLarenotequalto AOR-A11R
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Outputs
Inputs
1100-7
1108-15
Mode
CE
RIW
OE
UB
LB
SEM
H
H
L
X
X
L
DATAoUT DATAoUT Read Semaphore Flag Data Out
DATAoUT DATAouT Read Semaphore Flag Data Out
X
H
L
H
H
L
H
.f
./
X
X
X
X
X
X
L
DATAIN
DATAIN
Write 1/00 into Semaphore Flag
H
H
L
DATAIN
DATAIN
Write 1/00 into Semaphore Flag
L
X
L
-
-
Not Allowed
X
L
L
-
-
Not Allowed
X
L
L
X
X
2740 tbl 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Terminal Voltage -0.5 to +7.0
with Respect
toGND
Military
Unit
-0.5 to +7.0
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
Commercial
Ambient
Temperature
GND
Vee
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
2740 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTE:
2740 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min.
Typ.
Vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
6.0(2)
V
0.8
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
-
Max. Unit
NOTE:
1. VIL ~ -1.5V for pulse width less than·1 Ons.
2. VTERM must not exceed Vcc + 0.5V.
2740 tbl 06
CAPACITANCE (TA =+25°C, F =1.0MHZ) (1)
2. VTERM must not exceed Vcc +0.5V for more than 25% of the cycle time or
1Ons maximum, and is limited to :;:,20ma forthe period over VTERM ~ Vcc
+O.5V.
Symbol
Parameter
Condition(2)
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
9
pF
COUT
Output Capacitance
VOUT= 3dV
10
pF
Note:
2740 tbl 07
1. This parameter are determined by device characterization, but is not
production tested. TQFP Package only.
2. 3dV references the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
6.15
4
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(Vcc = s.OV
± 10%)
IDT7024S
Symbol
Min.
Test Conditions
Parameter
IOL = 4mA
-
IOH = -4mA
2.4
lIul
Input Leakage Current(l)
Vee = 5.5V, VIN = OV to Vee
IILOI
Output Leakage Current
CE = VIH, VOUT = OV to Vee
VOL
Output Low Voltage
VOH
Output High Voltage
IDT7024L
Max.
Min.
Max.
0.4
-
-
2.4
-
10
10
Unit
5
I!A
5
IlA
0.4
V
V
2740 tbl 08
NOTE:
1. At Vcc = 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1)
Test
Svmbol
Icc
ISB1
ISB2
Parameter
Condition
Version
ISB4
-
-
-
COM
S
L
170
170
CER = CEL = VIH
SEMR = SEML = VIH
MIL
S
L
-
-
-
f = fMAX(3)
COM
S
L
20
20
60
50
Standby Current
CE'A"=VIL and CE"B"=VIH(5)
MIL
(One Port-TIL
Active Port Outputs Open
S
L
-
Level Inputs)
f
S
L
CE = VIL, Outputs Open
SEM = VIH
MIL
(Both Ports Active)
f = fMAX(3)
Standby Current
(Both Ports - TIL
Level Inputs)
=fMAX(3)
=SEML =VIH
COM
10%'
7024X20
7024X25
COM'LONLY
TVD.'2) Max. rrVD.(2) Max. IUni1
S
L
Dynamic Operating
Current
SEMR
ISB3
(VCC = s.OV ±
7024X17
COM'LONLY
TVD,(2) Max
-
155
155
340
280
155
155
265
220
-
-
16
16
80
65
20
20
60
50
16
16
60
50
-
-
-
90
215
90
180
105
190
95
180
90
170
105
160
95
150
90
140
-
310
260
160
160
290
240
mA
Full Standby Current
(Both Ports - All
Both Ports GEL and
GER ~Vee - 0.2V
MIL
S
L
-
-
-
-
1.0
0.2
30
10
CMOS Level Inputs)
VIN > Vee - 0.2V or
VIN 0.2V, f 0(4)
SEMR SEML > Vee-0.2V
COM
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
CE"A' ~ 0.2 and
CE"B" ~ Vee - 0.2V(5)
MIL
S
L
-
-
-
-
-
85
85
200
170
Full Standby Current
(One Port-All
CMOS Level Inputs)
$
SEMR
=
=
mA
mA
mA
mA
=SEML ~ Vee-O.2V
VIN ~ Vee - 0.2V or
COM
VIN ~ 0.2V, Active Port
Outputs Open,
f fMAX(3)
S
100
170
90
155
85
145
L
100
140
90
130
85
120
=
NOTES:
2740 tbl 09
1. 'X' in part numbers indicates power rating (8 or L)
2. Vcc =5V, TA =+25°C, and are not production tested. Icc DC =120mA (TYP.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f =0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the oppOsite from port "AU.
6.15
5
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued) (Vcc = S.OV ± 10%)
7024X35
7024X55
Test
Typ.(2)
Max.
Typ.(2)
Dynamic Operating
Current
CE = Vll, Outputs Open
SEM = VIH
MIL.
S
L
150
150
300
250
150
150
300
250
140
140
(Both Ports Active)
f = fMAX(3)
COM'L.
S
L
150
150
250
210
150
150
250
210
-
-
Standby Current
(Both Ports - TTL
CEl = CER = VIH
SEMR = SEMl = VIH
MIL.
S
L
13
13
80
65
13
13
80
65
10
10
80
65
Level Inputs)
f = fMAX(3)
COM'L.
S
L
13
13
60
50
13
13
60
50
-
-
Standby Current
CE"A"=Vll and CE"8"=VIH(5)
MIL.
S
85
190
85
190
80
190
(One Port -
Active Port Outputs Open
f = fMAX(3)
L
85
160
85
160
80
160
Symbol
lee
IS81
IS82
Condition
Parameter
TTL
Level Inputs)
Version
IS84
mA
-
85
155
85
155
85
130
85
130
-
-
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
S
L
1.0
0.2
15
5
1.0
0.2
15
5
-
-
MIL.
S
L
80
80
175
150
80
80
175
150
75
75
COM'L.
S
80
135
80
135
L
80
110
80
110
-
Both Ports CEl and
CER ~ Vee - 0.2V
MIL.
CMOS Level Inputs)
COM'L.
VIN > Vec - 0.2V or
VIN ~ 0.2V, f = 0(4)
SEMR = SEMl ~ Vec - 0.2\1
Full Standby Current
(One Port-All
CE"A' < 0.2 and
CE"8" ~ Vcc - 0.2V(5)
mA
-
S
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
300
250
L
COM'L.
SEMR = SEMl = VIH
IS83
7024X70
MIL ONLY
Max. Typ.(2) Max. ~nit
mA
mA
175
150
mA
SEMR = SEMl ~ Vec - 0.2\1
VIN ~ Vec - 0.2V or
VIN.s 0.2V,
-
-
Active Port Outputs Open,
f - fMAX(3)
NOTES:
2740 tbl10
1. "X" in part numbers indicates power rating (S or L)
2. Vee =5V, TA =+25°C, and are not production tested.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
VLC
(
= 0.2V VHC = VCC - 0.2V)l4)
Symbol
Parameter
Test Condition
VDR
Vec for Data Retention
Vce = 2V
IceDR
Data Retention Current
CE~ VHC
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
VIN ~ VHe or .s VlC
SEM~
I MIL.
I COM'L.
VHC
Min.
Typ.(1)
Max.
2.0
-
-
100
4000
-
100
1500
0
-
tRC(2)
-
-
-
NOTES:
1. TA = +2S o C, Vee
Unit
V
J.lA
ns
ns
2740 tbl11
=2V, and are guaranted by characterization but are not production tested.
2. tRe Read Cycle Time
3. This parameter is guaranteed but not tested.
4. At Vcc =2.0V, input leakages are not defined.
=
DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vce
VDR~
2V
VDR
\~----------------------~I
tR~
~\\\\\\\\\\\\\
2740 drw 05
6.15
6
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
1.5V
Output Reference Levels
1.5V
DATAoUT
BUSY
See Figures 1 & 2
Output Load
~ ~
5V1250n
5ns Max.
Input Timing Reference Levels
DATAoUT
INT 775n
2740 tbl12
5V1250n
30pF
775n
Figure 1. AC Output Test Load
5pF
2740drw06
Figure 2. Output Test Load
(for tL2, tHZ, tWZ, tOW)
Including scope and Jig
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
ID17024X17
COM'L ONLY
Min.
Max.
Parameter
Symbol
ID17024X20
COM'LONLY
Min.
Max.
ID17024X25
Min.
Max.
Unit
ns
READ CYCLE
tRC
Read Cycle Time
17
-
20
-
25
-
tAA
Address Access Time
17
-
20
ns
Chip Enable Access Time(3)
17
-
20
-
25
tACE
-
25
ns
tABE
Byte Enable Access Time(3)
-
17
-
20
tAOE
Output Enable Access Time
-
10
-
12
-
3
-
3
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(l,
3
2)
3
3
25
ns
13
ns
-
ns
ns
tHZ
Output High-Z Time(l, 2)
-
10
-
12
-
15
ns
tpu
Chip Enable to Power Up Time(l,2)
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(l,2)
-
17
-
20
-
25
ns
tsoP
Semaphore Flag Update Pulse (OE or SEM)
10
-
10
-
10
-
ns
tSAA
Semaphore Address Access(3)
-
17
-
20
-
25
ns
ID17024X35
Symbol
Parameter
Min.
I
Max.
ID17024X55
Min.
I
Max.
ID17024X70
MIL ONLY
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
-
55
-
70
-
ns
tAA
Address Access Time
35
-
55
-
70
ns
tACE
Chip Enable Access Time(3)
35
ns
tAOE
Output Enable Access Time
30
-
70
Byte Enable Access Time(3)
-
55
tABE
-
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(1, 2)
3
tHZ
Output High-Z Time(1, 2)
tpu
Chip Enable to Power Up Time(l,2)
35
20
55
70
ns
35
ns
-
ns
-
3
-
3
3
-
3
-
15
-
25
-
30
ns
0
-
0
-
0
-
ns
Chip Disable to Power Down Time(l,2)
-
35
-
50
-
50
ns
tsop
Semaphore Flag Update Pulse (OE or SEM)
15
-
15
-
15
-
ns
tSAA
Semaphore Address Access(3)
-
35
-
55
-
70
ns
, tPD
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIl.
4. "X" in part numbers indicates power rating (S or L).
6.15
ns
2740 tbl13
7
IDT7024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
/ + - - - - - - tAA (4) ---~~
-----...--...--.........
tACE(4) - - - - - . i
CE
tAOE(4)
----..j
UB, LB
Rm
VALID DATA(4)
DATAoUT----------------------------~
BUSYOUT
tBDD(3,4)
2740 drw 07
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBOO delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBOO.
5. SEM =VIH.
TIMING OF POWER-UP POWER-DOWN
CE
Icc
~tPU1
(tPD=t-
ISB
2740 drw08
6.15
8
IDT7024S/L
HIGH-SPEED 4K X 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
IDT7024X17
COM'LONLY
Min.
Max.
Parameter
Symbol
IDT7024X20
COM'L ONLY
Min.
Max.
IDT7024X25
Min.
Max.
Unit
WRITE CYCLE
15
-
12
-
15
ns
a
-
a
-
ns
10
-
12
-
15
ns
a
-
a
-
a
ns
5
5
-
5
5
-
-
5
5
-
twc
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
17
12
12
0
12
tWR
Write Recovery Time
a
tow
Data Valid to End-of-Write
tHZ
-
-
20
15
15
-
a
10
-
15
-
Output High-Z Time(l, 2)
-
10
-
tOH
Data Hold Time(4)
a
-
twz
Write Enable to Output in High-Z(l, 2)
-
tow
Output Active from End-of-Write(l, 2, 4)
tswRO
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
Symbol
Parameter
25
20
20
0
20
-
15
a
a
-
IDT7024X35
IDT7024X55
Min.
Min.
Max.
I
Max.
IDT7024X70
MIL. ONLY
Min.
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
WRITE CYCLE
ns
40
twp
Write Pulse Width
25
Write Recovery Time
a
tow
Data Valid to End-of-Write
15
tHZ
Output High-Z Time(l, 2)
-
15
-
25
-
30
ns
tOH
Data Hold Time(4)
a
-
a
-
a
-
ns
twz
Write Enable to Output in High-Z(l, 2)
-
15
-
25
-
30
ns
tow
Output Active from End-of-Write(1, 2, 4)
a
a
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
5
5
-
0
5
5
-
ns
tSWRO
-
tAW
Address Valid to End-of-Write
35
30
30
tAS
Address Set-up Time(3)
a
40
0
30
ns
-
tWR
Write Cycle Time
Chip Enable to End-of-Write(3)
-
-
-
twc
tEW
55
45
45
a
5
5
70
50
50
a
50
a
NOTES:
1. Transition is measured ±SOOmV from low or high impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL, US or LS VIL, SEM VIH. To access semaphore, CE VIH or US & LS VIH, and SEM VIL.
Either condition must be valid for the entire t EW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH
and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
=
=
=
=
6.15
=
ns
ns
ns
ns
ns
ns
ns
2740 tbl14
=
9
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING(1,5,8)
twc
~~
/~
ADDRESS
~~
/\
i
tAW
(9)
CE or SEM
tHZ(7)
-.~
/
(9)
CE or SEM
-.~
/
~tAS(6
tWp(2)
~[-
RiW
(3)
tWR
,~
/
~
f4-tw~
DATAoUT
tow~
'\J
(4)
~
tow
..
~
'.
(4)
\
j
tOH
D A T A I N - - - - - - - - I_
E ___
] ____
t----2740 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE, UB, LB CONTROLLED TIMING(1,5)
twc
~~
ADDRESS
-,~
/~
J\
tAW
CEorSEM
~r-
(9)
~tAS(6)
US or LS
RiW
-,If...
~
I
tWR(3)~
tEW(2)
~t-
(9)
-~
~
\\\
--------IE
_ _]J---tow
DATAIN
"III
tOH
2740 drw 10
NOTES:
1. RIW or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or ill and a low CE and a low Riw for memory array writing cycle.
3. tWR is measured from the earlier of CE or Rm (or SEM or RiW) going high to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the RIW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last, CE, RIW, UB, or LB.
7. This parameter is guaranted by device characterization, but is not production tested.Transition is measured +/- 500mV steady state with the Output Test
Load (Figure 2).
B. If OE is low during RiW controlled write cycle, the write pulse width must be the larger of twp for (twz + tDW) to allow the I/O drivers to tum off and data
to be placed on the bus for the required tOW. If OE is high during an RIW controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified twp .
9. To access RAM, CE =VIL, UB or LB = VIL, and SEM =VIH. To access Semephore, CE = VIH or UB & ill =VIH, and SEM =VIL. tEW must be
met for either condition.
6.15
10
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao - A2
VALID ADDRESS
DATAo-------4--------~~
RAN------~------~
---~-___.j tAOE
2740 drw 11
NOTE:
1. CE = VIH or U8 & L8 = VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
...JX'-________
AO"A"-A2"A'_'_____M
__
A_T_C_H______
SIDE(2) "A"
RfiJ"A"
SEM"A"
AO"B"-A2"B"
SIDE(2) "B"
NOTES:
1. DOR DOL VIL, CER CEl VIH, or both U8 & [8 VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and rift ports. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
3. This parameter is measured from RJWA or SEMA going High to RlWB or SEMB going High.
4. If tsps is not satisfied, there is no guarantee which side will obtain the Semephore flag.
=
=
=
=
=
6.15
11
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
IDT7024X17
COM'LONLY
Min.
Max.
Parameter
IDT7024X20
COM'LONLY
Min.
Max.
IDT7024X25
Min.
Max.
Unit
BUSY TIMING (MIS = H)
-
17
BUSY Disable Time from Chip Enable HIGH
-
tAPS
Arbitration Priority Set-up Time(2)
tBOO
BUSY Disable to Valid Data(3)
tBAA
BUSY Access Time from Address Match
tBOA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
tBOC
-
20
-
20
ns
20
-
20
ns
-
20
-
20
ns
17
17
-
17
ns
5
-
5
-
5
-
ns
-
17
-
20
-
25
ns
-
0
-
0
17
-
ns
15
45
-
50
ns
30
-
35
ns
17
17
BUSY TIMING (MiS = L)
tWB
BUSY Input to Write(4)
0
tWH
Write Hold After BUSV(5)
13
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(1)
tODD
Write Data Valid to Read Data Delay(1)
-
30
25
-
IDT7024X35
IDT7024X55
IDT7024X70
Min.
Min.
Min.
MIL ONLY
Svmbol
Parameter
Max.
Max.
Max.
Unit
BUSY TIMING (MiS = H)
tBAA
BUSY Access Time from Address Match
-
20
tBOA
BUSY Disable Time from Address Not Matched
-
20
tBAC
BUSY Access Time from Chip Enable LOW
-
20
tBOC
BUSY Disable Time from Chip Enable HIGH
-
20
-
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
5
-
ns
tBOO
BUSY Disable to Valid Data(3)
-
35
-
55
-
70
ns
0
-
ns
25
-
ns
-
95
ns
80
ns
45
-
45
ns
40
-
40
ns
40
-
40
ns
35
-
35
ns
BUSY TIMING (MIS = L)
tWB
BUSY Input to Write(4)
0
-
0
tWH
Write Hold After BUSV(5)
25
-
25
-
-
60
45
-
65
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(1)
tODD
Write Data Valid to Read Data Delay(1)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With
8USY (M
= H)" or "Timing Waveform of Write With Port-To-Port Delay (M
= L)".
2. To ensure that the earlier of the two ports wins.
3. t8DD is a calculated parameter and is the greater of Ons, tWDD - tWP (actual) or tODD - tOw (actual).
4. To ensure that the write cycle is inhibited on port '8' during contention with port 'A'.
5. To ensure that a write cycle is completed on port '8' after contention with port 'A'.
6. "X" in part numbers indicates power rating (8 or L).
is
80
2740 tbl15
is
6.15
12
IDT7024S/L
HIGH·SPEED 4K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,5) (MIS
=VIH)
twc
ADDR'A
)
K
/
) "'-
MATCH
twp
~
"'-
tOW
)(
DATAIN 'A
/'
/
~<"
VALID
tAps (1)
) (-----
ADDR'B
MATCH
tBAA
""I--"
BUSY"B
f4- tBDA
twDD
I
i
)
DATAOUT"B
tODD
(3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for MIS Vil (SLAVE).
2. CEl CER Vil.
3. OE Vil for the reading port.
4. If MIS= Vll(slave) then BUSY is an input BUSY'A' = Vil and BUSY's' = don't care, for this example.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from
port "A".
=
=
tBDD
~
2740 drw 13
=
=
TIMING WAVEFORM OF WRITE WITH BUSY
~------- twp------~
RJWIIA"
BUSyIlB"
RJW"B"
(2)
Note:
1. tWH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" Blocking RIW'B", until BUSY"B" goes High.
6,15
13
IDT7024S/L
HIGH~SPEED
4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) {MiS
=H)
ADDR'A'~
~
and "B'~,-_ _ _ _ _ _ _ _ _A_D_D_R_E_SS_E_S_M_A_TC_H
___________~
tAPS(~""---~-----------1
CE"A'
1--
-r:=-mAC --j
~
BUSY"B'
tBoC
~ ,..____-
A
2740drw14
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1){MIS H)
=
ADDR'A'
ADDRESS "N"
ADDR"B"
MATCHING ADDRESS "N"
BUSY"B'
2740 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7024X17
COM'LONLY
Min.
Max.
Parameter
Symbol
IDT7024X20
COM'LONLY
Min.
Max.
IDT7024X25
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
Symbol
Parameter
-
0
-
0
0
15
-
20
20
-
15
IDT7024X35
IDT7024X55
Min.
Min.
Max.
Max.
0
-
ns
ns
20
ns
20
ns20
IDT7024X70
MIL. ONLY
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Inter~upt
-
Reset Time
NOTE:
1. "XU in part numbers indicates power rating (8 or L).
-
0
-
0
-
ns
0
0
-
ns
25
-
40
50
ns
25
-
40
-
50
ns
2740 tbl16
6.15
14
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
twc--------------------~
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
___________________t_IN_S_3)_~
INT"B"
------------------------------------------------
2740 drw 17
tRC
----------------.-1
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
OE"B"
tl_N_R(_3)_~---------------------------------------------------
__________________
INT"B"
2740 drw 18
NOTES:
1.
2.
3.
4.
All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
See Interrupt truth table.
Timing depends on which enable signal (CE' or Am) is asserted last.
Timing depends on which enable signal (eE or Am) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Left Port
Right Port
INTl
RN/R
CER
OER
A11R-AoR
X
X
X
X
X
INTR
L(2)
X
X
X
L
L
FFF
H(3)
L
L
X
FFE
X
Set Left INTl Flag
X
X
X
X
X
Reset Left INTL Flag
RN/l
eEL
OEl A11l-Aol
L
L
X
FFF
X
X
X
X
X
X
X
L(3)
X
L
L
FFE
H(2)
NOTES:
Function
Set Right INTR Flag
Reset Right INTR Flag
2740 tbl17
1. Assumes BUSYL =BUSYR =VIH.
2. If BUSYL =VIL, then no change.
3. If BUSYR =VIL, then no change.
6.15
15
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE 11- ADDRESS BUSY ARBITRATION
Inputs
AOL-A11L
AOR-A11R
Outputs
CEL
CER
BUSYL(1)
BUSYR(1)
X
NO MATCH
H
H
Normal
H
X
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibitl"'l
Function
NOTES:
2740 tbl16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDT7024 are push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
00 - 015 Left
No Action
1
po - 015 Right
1
Status
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Hight I-'ort wntes "0" to ~emaphore
1
Right Port Wntes "1" to Semaphore
1
,
Semaphore tree
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Lett I-'ort Wntes "1" to ~emaphore
1
1
Semaphore free
0
Right port has semaphore token
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.
2740 tbl19
FUNCTIONAL DESCRIPTION
The IDT7024 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7024 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
.
memory array is permitted.
memory location FFF (HEX) and to clear the interrupt flag
(INTR), the right port must access the memory location FFF.
The message (16 bits) at FFE or FFF is user-defined, since it
is an addressable SRAM location. If the interrupt function is
not used, address locations FFE and FFF are not used as mail
boxes, but as part of the random access memory. Refer to
Table I for the interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is asserted when the right port
writes to memory location FFE (HEX), where a write is defined
as the CE =RiW =VIL per the Truth Table. The left port clears
the interrupt by access address location FFE access when
CER = OER =VIL, RNi is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.15
16
IDT7024S/L
HIGH-SPEED 4Kx 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-
T
1
MASTER
Dual Port
SLAVE
Dual Port
CE
BUSY (L) BUSY (R)
J
SLAVE
Dual Port
CE
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
1
CE
BAM..
.BAM...
SY(L)
1
0
-
J
I
MASTER
Dual Port
w
BUSY (L) BUSY (R)
I
0
0
()
BAM.
BAM.
1
CE
a:::
r-w
I
I
I
BUSY (R)
1
2740 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7024 RAMs.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the lOT 7024 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7024 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7024 RAM the busy pin is
an output if the part is used as a master (MIS pin =H), and the
busy pin is an input if the part used as a slave (MIS pin =L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side ofthe array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a masterlslave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
can be initiated with either the Rm signal or the byte enables.
Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
SEMAPHORES
The IDT7024 is an extremely fast Dual-Port 4K x 16 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer's software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT7024 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7024's hardware semaphores, which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
6.15
17
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7024 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7024 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RiW) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either Signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain. a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
6.15
18
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7024's Dual-Port
RAM. Say the 4K x 16 RAM was to be divided into two 2K x
16 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 2K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore o. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 2K. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
o. At this point, the software could choose to try and gain
control of the second 2K section bywriting, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 2K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Q'?WM1Q ~ D~
WRI~=I_D_ _
SEMAPHORE..
READ
~ Ll
Do
WRITE
_
SEMAPHORE
READ
2740 drw 20
Figure 4. IDT7024 Semaphore Logic
6.15
19
IDT7024S/L
HIGH-SPEED 4K X 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Y:lank
PF
~
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
F
100-pin TQFP (PN1 00-1)
84-pln PGA (G84-3)
84-pin PLCC (J84-i)
84-pin Flatpack (F84-2)
17
20
25
Commercial onlY}
Commercial Only
G
'----------iJ
'--_ _ _ _ _ _ _ _ _ _ _
Commercial (O°C to +70°C)
~~
70
'-----------------ll S
IL
' - - - - - - - - - - - - - - - - - - - - - - - 1 : 7024
Speed in nanoseconds
Military Only
Standard Power
Low Power
64K (4K x 16) Dual-Port RAM
2740 drw 21
6.15
20
(;)
IDT7025S/L
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
more than one device
FEATURES:
• Mis =H for BUSY output flag on
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 25/35/55/70ns (max.)
- Commercial: 17/20/25/35/55ns (max.)
• Low-power operation
- IDT7025S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7025 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
•
•
•
•
•
•
•
•
•
Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Devices are capable of withstanding greater than 2001 V
electrostatic discharge
Fully asynchronous operation from either port
Battery backup operation-2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, quad flatpack, PLCC, and 100pin Thin Quad Plastic Flatpack
Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
~
r
r
'\
\.
-
~
~
-~
~~
~
~
!j4
I/OSl-1/015l
1/0
Control
I/OOl-1/07 L
BUSy[1,2
•
)
A12l
AOl
··
NOTES:
1. (MASTER):
BUSYis outp ut;
(SLAVE):
SY
is input.
2. BUSY output s
and INToutp uts
are non-tri-slated
push-pull.
Address
Decoder
1
A
"-
'I
V
A
~
"
1r
~
1/0
Control
•
~
A
"-
"
V
K
13
13
,
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEL,
OEL
RiWl:
I
tI t ~
Mis
I/OsA-I/015A
I/OOA-1/07A
MEMORY
ARRAY
sr:r-
SEMl
\
INTt2
~
~~
Address
Decoder
-
-
··
BUSy~1,2)
A12A
AOA
I
:CEA
'OEA
:R!WA
I
~
SEMA
INT~2)
2683 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101995 Integrated Device Technology, Inc.
6.16
APRIL 1995
DSC104614
1
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Enable ( CE) permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500ll W from a 2V
battery.
The I DT7025 is packaged in a ceramic 84-pin PGA, an 84pin quad flatpack, PLCC, and a 1OO-pin TQFP. Military grade
product is manufactured in compliance with the latest revision
of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of
pe~ormance and reliability.
DESCRIPTION:
The IDT7025 is a high-speed 8K x 16 Dual-Port Static
RAM. The IDT7025 is designed to be used as a stand-alone
128K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 32-bit or more word systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by Chip
PIN CONFIGURATIONS
INDEX
~ Vee-0.2V
COM
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
CMOS Level Inputs)
One Port CE"A" .::: 0.2 and
CE"8" Vee· O.2V or
VIN ~ 0.2V, f = 0(4)
SEMR = SEML > Vee· 0.2V
COM'L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
CMOS Level Inputs)
CE"A" .s 0.2V and
CE"B" ~ Vee· 0.2V(5)
MIL.
S
L
-
-
100
100
200
175
COM'L.
S
110
185
100
170
L
110
160
100
145
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
(Both Ports Active)
f = fMAX(3)
Standby Current
(Both Ports - TIL
CER = CEL = VIH
SEMR = SEML = VIH
Level Inputs)
f = fMAX(3)
Standby Current
(One Port-TIL
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Open,
Level Inputs)
SEMR = SEML ~ Vee· 0.2V
VIN ~ Vee· 0.2V or
VIN.s 0.2V
Active Port Outputs Open,
f = fMAX(3)
210
180
rnA
rnA
rnA
rnA
rnA
NOTES:
2939 tbl 09
1. "X" in part numbers indicates power rating (8 or L)
2. Vee SV, TA +2S o C, and are not production tested. leeDe 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 11 tRe, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
=
=
=
=
6.17
5
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Continued) (Vcc = 5.0V ± 10%)
7026X35
7026X55
Test
lee
1881
1892
1893
Max. Typ.(2)
Max. Unit
CE = Vll, Outputs Open
SEM = VIH
MIL.
S
L
160
160
335
295
150
150
310
270
(Both Ports Active)
f = fMAX(3)
COM'L.
S
L
160
160
295
255
150
150
270
230
Standby Current
(Both Ports - TTL
CEl = CER = VIH
SEMR = SEMl= VIH
MIL.
S
L
20
20
100
80
13
13
100
80
Level Inputs)
f = fMAX(3)
COM'L.
S
L
20
20
85
60
13
13
85
60
Standby Current
(One Port - TTL
CE"A"=Vll and CE"9"=VIH(5)
Active Port Outputs Open,
MIL.
S
L
95
95
215
185
85
85
195
165
Level Inputs)
f fMAX(3)
SEMR = SEMl = VIH
COM'L.
S
L
95
95
185
155
85
85
165
135
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee - 0.2V
MIL.
S
L
1.0
0.2
30
10
1.0
0.2
30
10
CMOS Level Inputs)
VIN ~ Vee - 0.2V or
VIN!> 0.2V, f 0(4)
SEMR SEMl~Vee - 0.2V
COM'L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port-All
CMOS Level Inputs)
CE"A" < 0.2V and
CE"9" ;, Vee - 0.2V(5)
SEMR = SEMl~Vee - 0.2V
MIL.
S
L
90
90
190
165
80
80
165
140
mA
VIN ~ Vee - 0.2V or
VIN!> 0.2V
Active Port Outputs Open,
f fMAX(3)
COM'L.
S
L
90
90
160
135
80
80
135
110
mA
Parameter
Version
Condition
=
=
1894
Typ.(2)
Dynamic Operating
Current
Symbol
=
mA
mA
mA
mA
=
NOTES:
2939 tbl1 0
1. "X" in part numbers indicates power rating (8 or L)
2. Vcc 5V, TA +25°C, and are not production tested. ICCDC 120mA (Typ.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 11 tRC, and using
"AC Test Conditions" of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
=
=
=
=
6.17
6
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to
Input Rise/Fall Times
3.0V
8930
5ns Max.
1.5V
1.5V
Input Timing Reference Levels
Output Reference Levels
8930
DATAoUT
BUSy---..---+----.
INT
DATAoUT'-----..---+-_
30pF
3470
3470
5pF
See Figures 1 & 2
Output Load
2939 tbl11
2939 drw 05
2939drw04
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
• Including scope and jig.
Figure 1. AC Output Load
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT7026X20
COM'L ONLY
Min.
Max.
Parameter
Symbol
IDT7026X25
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
-
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
tABE
Byte Enable Access Time(3)
-
20
20
20
12
-
ns
ns
-
25
25
25
13
-
3
3
-
ns
ns
25
-
ns
ns
ns
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1. 2)
3
3
-
12
-
15
0
-
0
-
ns
-
20
-
25
25
ns
tHZ
Output High-Z Time(1, 2)
tpu
Chip Enable to Power Up Time(2)
tPD
Chip Disable to Power Down Time(2)
tsop
Semaphore Flag Update Pulse (OE or SEM)
10
-
12
tSAA
Semaphore Address Access Time
-
20
-
Parameter
Symbol
IDT7026X35
IDT7026X55
Min.
Max.
Min.
35
35
35
20
55
-
-
3
3
-
3
3
55
55
55
30
-
-
15
Max.
ns
ns
ns
Unit
READ CYCLE
tRC
Read Cycle Time
35
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
-
tABE
Byte Enable Access Time(3)
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1, 2)
tHZ
Output High-Z Time(1, 2)
tpu
Chip Enable to Power Up Time(2)
0
tPD
Chip Disable to Power Down Time(2)
-
tsop
Semaphore Flag Update Pulse (OE or SEM)
15
tSAA
Semaphore Address Access Time
-
NOTES:
1.
2.
3.
4.
-
ns
ns
ns
ns
ns
ns
-
ns
-
25
ns
-
0
-
ns
35
35
-
50
ns
15
-
ns
-
55
ns
2939 tbl12
Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
This parameter is guaranteed b~vice characterization, but is not ~duction tested.
To access RAM, CE =V,L and SEM =VIH. To access semaphore, CE =VIH and SEM =V,L.
"X" in part numbers indicates power rating (S or L).
6.17
7
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
....- - - - - tAA (4)
------4~
tACE(4) ---~
tAOE(4) ---~
UB, LB
RNi
VALID DATA(4)
DATAoUT----------------------------~
BUSYOUT
tBOO(3,4)
2939drW06
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBOO delay is requireQ only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBOO.
5. SEM =VIH.
TIMING OF POWER-UP POWER-DOWN
2939 drw 07
6.17
8
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
Symbol
IDT7026X20
COM'LONLY
Max.
Min.
Parameter
IDT7026X05
Min.
Max.
Unit
WRITE CYCLE
tDH
Data Hold Time(4)
20
15
15
0
15
0
15
0
twz
Write Enable to Output in High-Z(l, 2)
-
tow
Output Active from End-of-Write\ I, <:, 4)
tSWRD
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
twc
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(l, 2)
Symbol
Parameter
-
20
-
a
15
-
12
-
15
ns
ns
-
-
25
20
20
a
ns
ns
ns
ns
ns
ns
ns
-
0
-
-
15
ns
a
12
-
0
ns
5
5
-
-
5
5
ns
ns
IDT7026X35
IDT7026X55
Min.
Min.
Max.
55
45
45
0
40
0
30
-
-
25
ns
a
-
ns
-
25
ns
0
5
5
-
ns
-
ns
Max.
Unit
WRITE CYCLE
tDW
Data Valid to End-of-Write
35
30
30
0
25
0
15
tHZ
Output High-Z Time(1,
-
tDH
Data Hold Time(4)
0
twz
Write Enable to Output in High-z(l, 2)
-
tow
Output Active from End-of-Write(l, 2, 4)
tSWRD
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
0
5
5
twc
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWR
Write Recovery Time
2)
-
15
15
-
-
-
-
ns
ns
-
ns
-
ns
ns
ns
ns
ns
NOTES:
2939 tbl13
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL and 8EM VIH. To access semaphore, CE V,H and 8EM V,L. Either condition must be valid for the entire tEW time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (8 or L).
=
=
=
6.17
=
9
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING(1,5,8)
twc
w
ADDRESS
~t
1\
j~
tHZ(7)
j
tAW
GEar SEM
GEar SEM
-~
(9)
I
-,~
(9)
J
f4-tAS(6 1
twp(2)
,-f\
(3)
tWR
-,~
J
~tw~
DATAoUT
tow
V
(4)
~
J1
tDW
.'11
tDH
(4)
,
1
]_l-------
D A T A I N - - - - - - - - I_
F
_______
2939 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2, GE, UB, LB CONTROLLED TIMING(1,5)
twc
~~
\I
ADDRESS
1\
Jr...
tAW
GEar SEM
J
\
-tAs(6)
US ar LS
-,~
~r
(9)
tWR(3)~
tEW(2)
)
(9)
...,'J
\
\\\
DATAIN
-,.
------iF
________]1---tDW
tDH
2939 drw 09
NOTES:
1. RJW or CE or US and LS must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a LOW CE and a LOW RiW for memory array writing cycle.
3. tWR is measured from the earlier of CE or RfiJ (or SEM or RiW) going HIGH to the end of write cycle.
4. Durina!lis period, the 1/0 pins are in the output state and input signals mu~ not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R!W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE or Rm.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during RJW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tow. If OE is HIGH during an RJW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. To access RAM, CE =VIL and SEM =VIH. To access semaphore, CE =VIH and SEM =VIL. tEW must be met for either condition.
6.17
10
IDT7026S/L
HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao - A2
VALID ADDRESS
DATAo-------4--------+_~
RAN-------4------,
-------r---.j
tAOE
2939 drw 10
NOTE:
1. CE VIH or U8 and [8
=
=VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
-'X'-________
AO"A"-A2"A'_'_ _ _M_A_T_C_H_ _ _
SIDE(2) "A"
RfiJ"A"
SEM"A"
AO"B"-A2"B"
SIDE(2) "8"
NOTES:
1. DOR = DOL = Vll, GER = GEL = VIH, or both U8 & LB = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
3. This parameter is measured from RJWiA' or SEM"A' going HIGH to RJWiB' or SEM"B' going HIGH.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6,17
11
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Svmbol
IDT7026X20
COM'LONLY
Min.
Max.
Parameter
IDT7026X25
Min.
Max.
Unit
BUSY TIMING (MiS = Hl
20
20
20
17
-
20
20
20
17
ns
BUSY Disable Time from Chip Enable HIGH
-
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
ns
tBDD
BUSY Disable to Valid Data(3)
-
20
-
25
ns
0
15
-
0
-
ns
17
-
45
30
-
50
35
ns
tBAA
BUSY Access Time from Address Match
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
tBDC
ns
ns
ns
BUSY TIMING (MIS = L)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSy(5)
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(l)
Symbol
Parameter
IDT7026X35
IDT7026X55
Min.
Min.
Max.
ns
Max.
Unit
45
ns
40
ns
ns
-
40
35
BUSY TIMING (MiS = H)
20
BUSY Disable Time from Chip Enable HIGH
-
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
ns
tBDD
BUSY Disable to Valid Data(3)
-
35
-
55
ns
0
25
-
0
25
-
ns
-
60
45
-
80
65
ns
tBAA
BUSY,Access Time from Address Match
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
tBDC
20
20
20
-
ns
BUSY TIMING (MIS = L)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSy(5)
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
~DDD
Write Data Valid to Read Data Delay(l)
ns
NOTES:
2939tbl15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wavefonn of Write with Port-to-Port Read and 8USY (MIS VIH)".
2. To ensure that the earlier of the two ports wins.
3. teoo is a calculated parameter and is the greater of 0, twoo - twp (actual) or tODD - tow (actual).
4. To ensure that the write cycle is inhibited on port "8" during contention on port "A".
5. To ensure that a write cycle is completed on port "8" after contention on port "A".
6. "X" in part numbers indicates power rating (8 or L).
=
6.17
12
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,5) (MIS
=VIH)
twc
ADDR"A
)~
)(
MATCH
twp
~
,/
K
toW
)~
DATAIN'A
tAps (1)
AD DR's
) (~
/
>KH
VALID
MATCH
"
tSM
f+- tSDA
"r-",
BUSY's
tSDD
/
/
twDD
)
DATAoUT'S
tODD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Mis Vil (SLAVE).
2. CEl CER Vil
3. OE Vil for the reading port.
4. If MIS Vil (SLAVE), then SUSYis an input (SUSY'A' VIH and BUSY's' "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
=
= =
=
=
=
E
2939 drw 12
=
TIMING WAVEFORM OF WRITE WITH BUSY (MIS
=VIL)
~------twP------~
RJW"A"
BUSY"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking RiW'B', until BUSY"B' goes High.
6,17
13
IDT7026S/L
HIGH·SPEED 16K x 16 DUAL·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MIS
=H)
ADDR"A"=X
and "B"
><=
ADDRESSES MATCH
--------
tAPS(:t----~-------------"1
1=
--b ~
IBAC:j
IBDC
~
BUSY"B"
, _ _ _ _ __
A
2939 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1){MlS = H)
ADDR"A"
ADDRESS "N"
ADDR"B"
MATCHING ADDRESS "N"
IBM
BUSY"B"
={____1mDA
2939 drw 15
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
TRUTH TABLE 1- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
Do - 015 Left
Do - 015 Right
No Action
1
1
Status
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Right port obtains semaphore token
Left Port Writes "1" to Semaphore
1
0
.Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Semaphore free
Left Port Writes "1" to Semaphore
1
1
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7026.
6.17
2683 tbl16
14
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
TRUTH TABLE II ARBITRATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
ADDRESS BUSY
Inputs
Outputs
eEL
CER
AOL-A13L
AOR-A13R
BUSYL(1)
BUSYR(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3j
NOTES:
Function
2683 tbl17
When expanding an IDT7026 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7026 RAM the busy pin is
an output if the part is used as a master (MIS pin = H), and the
busy pin is an input if the part used as a slave (MIS pin = L) as
shown in Figure 3.
r--
1. Pins BUSYL and BUSYR are both outputs when the part is configured as
a master. Both are inputs when configured as a slave. BUSYx outputs on
the IDT7026 are push pull, not open drain outputs. On slaves the BUSYx
input internally inhibits writes.
2. LOW if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. HIGH if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either BUSYL or BUSYR ;:: LOW will result. BUSYL and BUSYR outputs
cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are
driving LOW regardless of actual logic level on the pin. Writes to the right
port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
r
MASTER
Dual Port
.BAM..
BUSY (L) BUSY (R)
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port LOW.
The busy outputs on the lOT 7026 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
SLAVEJ
Dual Port
CE
a:
,....w
0
0
()
w
.BAM..
BUSY (L) BUSY (R)
0
L--
1
MASTER
Dual Port
.BAM..
BUSY(L)
CE
BUSY(L) BUSY(R)
1
FUNCTIONAL DESCRIPTION
The IDT7026 provides two ports with separate control,
address and 1/0 pins that permit independent access for reads
or writes to any location in memory. The IDT7026 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
CE
T
SLAVE
Dual Port
.BAM..
CE
BUSY(L) BUSY(R)
I
BUSY(R)
2939 drw 16
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7026 RAMs.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a masterlslave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with either the Rm signal or the byte enables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
SEMAPHORES
The IDT7026 is an extremely fast Dual-Port 16K x 16
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
6.17
15
I DT7026 S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both HIGH.
Systems which can best use the IDT7026 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7026's hardware semaphores, which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7026 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred-in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
''Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If itwas not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is
released when the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7026 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RiW) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that
the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch forthat side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW
and the other side HIGH. This condition will continue until a
6.17
16
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.L...fQBI
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do
Do
WRITE
WRITE
SEMAPHORE4-____~_
READ
L--L-_ _ _ _. .
SEMAPHORE
READ
2939 drw 17
Figure 4. IDT7026 Semaphore Logic
one is written to the same semaphore request latch. Should
the other side's semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay LOW until
its semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7026's Dual-Port
RAM. Say the 16K x 16 RAM was to be divided into two 8K
x 16 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 8K. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
O. At this point, the software could choose to try and gain
control of the second 8K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still.Dccupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors' can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads and
interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
6.17
17
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Y:lank
~
________________
~
G
J
20
25
'---------------------------1 35
55
L - -_ _ _ _ _ _ _ _ _ _ _ _~I
S
IL
L -______________________________________
~:
7026
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
84-pin PGA (G84-3)
84-pin PLCC (J84-i)
Commercial OnlY}
Speed in nanoseconds
Standard Power
Low Power
256K (16K x 16) Dual-Port
RAM
2939 drw 18
6.17
18
(;J
HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM
IDT70261 S/L
Integrated Device Technology, Inc.
• MIS =H for BUSY output flag on Master,
MIS = L for BUSY input on Slave
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Commercial: 20/25/35/55ns (max.)
• Low-power operation
- IDT70261S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT70261L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT70261 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• TTL-compatible, single 5V (±1 0%) power supply
• Available in 1~O-pin Thin Quad Plastic Flatpack
DESCRIPTION:
The IDT70261 is a high-speed 16K x 16 Dual-Port Static
RAM. The IDT70261 is designed to be used as a stand-alone
256K-bit Dual-Port RAM or as a combination MASTERI
SLAVE Dual-Port RAM for 32-bit-or-more word systems.
Using the IDT MASTERISLAVE Dual-Port RAM approach in
32-bit or wider memory system applications results in full-
FUNCTIONAL BLOCK DIAGRAM
RIWl
UBl
f
"\
"--
1
1\
L...J
J
4<~
I/OSl-1/015l
1/0
Control
BUSy[l,2)
AOl
··
Address
Decoder
I
A
~
L!
_l'-.
A
~r
"
MEMORY
ARRAY
v
"
~~
•
I/00l-1/0? l
A13l
r-r
->-i
I/OSR-1I015R
1/0
Control
14
I/00R-I/07R
•
BUSy~l,2)
"
A
f'\..
v
14
,
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEl'
OEl.
RiWl:
-'
I
t It I
I MIS
Address
Decoder
··
A13R
AOR
I
.CER
:O~
.RlWR
SEMR
INTFf2)
3039 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGES
IC>1995 Integrated Device Technology. Inc.
APRIL 1995
6.18
DSC108212
1
IDT70261 SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate
control, address, and 110 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
The IDT70261 is packaged in a 100-pin TQFP.
PIN CONFIGURATIONS
NI
NI
NI
NI
N/C
N/C
N/C
IDT70261
PN100-1
100-PIN
TQFP (3)
TOP VIEW
ASl
ASl
A4l
A3l
A2l
All
Aol
INTl
BUSYl
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
ASR
N/C
N/C
N/C
PIN NAMES (1,2)
Left Port
Right Port
CEl
CER
Names
Chip Enable
R!WL
RIWR
ReadIWrite Enable
DEL
OER
Output Enable
AOl-A13l
AOR - A13R
Address
I/OOl - I/015l
I/OOR - I/015R
Data Input/Output
SEMl
SEMR
Semaphore Enable
UBl
UBR
Upper Byte Select
LBl
LBR
Lower Byte Select
INTl
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
30391b~OI
6.18
2
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
X
RIW
X
X
L
L
L
L
L
L
X
X
X
X
X
L
H
L
H
CE
H
Outputs
DE
UB
LB
SEM
1108-15
1100-7
X
X
H
High-Z
High-Z
Mode
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
Deselected: Power-Down
H
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
L
H
H
DATAoUT
High-Z
Read Upper Byte Only
L
H
L
H
High-Z
L
H
L
L
L
H
X
X
H
X
X
X
DATAoUT Read Lower Byte Only
DATAoUT DATAoUT Read Both Bytes
High-Z
High-Z
Outputs Disabled
NOTE:
1. AOL-AI3L;eAoR-AI3R
3039 tbl 02
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
CE
RIW
OE
UB
LB
SEM
1108-15
H
H
L
X
X
L
DATAoUT DATAoUT Read Data in Semaphore Flag
1100-7
Mode
X
DATAoUT DATAouT Read Data in Semaphore Flag
H
L
H
H
L
H
f
X
X
X
L
DATAIN
DATAIN
Write 1/00 into Semaphore Flag
X
f
X
X
X
H
H
L
DATAIN
DATAIN
Write 1/00 into Semaphore Flag
L
X
L
X
L
L
L
L
X
X
-
-
Not Allowed
-
Not Allowed
3039 tbl 03
ABSOLUTE MAXIMUM RATINGS(1}
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
toGND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Commercial Unit
-0.5 to +7.0
Grade
Ambient
Temperature
GND
Vee
Commercial
O°C to +70°C
OV
5.0V± 10%
V
TA
Operating
Temperature
o to +70
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output
Current
50
mA
3039 tbl 05
NOTE:
3039 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + O.SV for more than 2S% of the cycle time
or 10ns maximum, and is limited to!> 20mA forthe period of VTERM ~ Vcc
+O.SV.
NOTE:
1. VIL ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.SV.
3039 tbl 06
CAPACITANCE (TA =+25°C, f =1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
9
pF
COUT
Output
Capacitance
VOUT= 3dV
10
pF
NOTE:
3039 tbl 07
1. This parameter is determined by device characterization but is not
production tested. TQFP package only.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
6.18
3
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(Vcc = S.OV ± 10%)
IDT70261S
Symbol
Test Conditions
Parameter
Min.
IDT70261L
Max.
Min.
Max.
Unit
5
j.1A
IILOI
Output Leakage Current
CE = VIH, Your = OV to Vee
-
10
-
5
j.1A
VOL
Output Low Voltage
IOL = 4mA
-
0.4
-
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-
lIul
Input Leakage Current(1)
Vee = 5.5V, VIN = OV to Vee
10
V
NOTE:
3039 tbl 08
1. At Vcc =2.0V, input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
(Vcc= S.OV ± 10%)
70261X20
Symbol
lee
Parameter
18B2
18B3
18B4
70261X25
Typ.(2) Max. Typ.(2) Max. Unit
Version
CE = VIL, Outputs Open
SEM =VIH
f = fMAX(3)
COM'L.
S
L
180
180
315
275
170
170
305
265
mA
COM'L.
S
L
30
30
85
60
25
25
85
60
mA
Level Inputs)
CER = CEL = VIH
SEMR =SEML = VIH
f =fMAX(3)
Standby Current
(One Port - TTL
CE"A' =VIL and CE"B" = VIH(5)
Active Port Outputs Open,
COM'L.
S
L
115
115
210
180
105
105
200
170
mA
Level Inputs)
f =fMAX(3)
SEMR =SEML = VIH
Full Standby Current
(Both Ports - All
Both Ports GEL and
CER ~ Vee - 0.2V
COM'L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
CMOS Level Inputs)
VIN > Vee - 0.2V or
VIN ~ 0.2V, f =0(4)
SEMR =SEML> Vee - 0.2V
Full Standby Current
(One Port-All
CMOS Level Inputs)
CE"A' .$. 0.2V and
CE"B' ~ Vee - 0.2V(5)
COM'L.
S
L
110
110
185
160
100
100
170
145
mA
Dynamic Operating
Current
(Both Ports Active)
18B1
Test
Condition
Standby Current
(Both Ports - TTL
SEMR =SEML ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
VIN.$. 0.2V
Active Port Outputs Open,
f =fMAX(3)
NOTES:
3039 tbl 09
1. "X" in part numbers indicates power rating (8 or L)
2. Vee =5V, TA =+25°C, and are not production tested. leeDe =120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC. and using "AC Test Conditions"
of input levels of GND to 3V.
4. f =0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
6.18
4
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc =S.OV ± 10%)
70261X35
70261X55
Test
Symbol
lee
18B1
18B2
18B3
18B4
CE = Vll, Outputs Open
SEM = VIH
(Both Ports Active)
f
Standby Current
(Both Ports - TTL
CER CEl = VIH
SEMR SEMl = VIH
Level Inputs)
f
Standby Current
(One Port - TTL
CE"A" Vil and CPB' VIH(5)
Active Port Outputs Open,
Level Inputs)
f = fMAX(3)
SEMR = SEMl = VIH
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee - 0.2V
CMOS Level Inputs)
VIN > Vee - 0.2V or
VIN ~ 0.2V, f == 0(4)
SEMR = SEMl ~ Vee - 0.2V
Full Standby Current
(One Port-All
CE"A" < 0.2V and
CE"B" ;. Vee - 0.2V(5)
CMOS Level Inputs)
Typ.(2) Max.
Version
Condition
Parameter
Dynamic Operating
Current
Typ.(2) Max. Unit
COM'l,
S
L
160
160
295
255
150
150
270
230
mA
COM'l,
S
L
20
20
85
60
13
13
85
60
mA
COM'l,
S
L
95
95
185
155
85
85
165
135
mA
COM'l,
S
L
1.0
0.2
15
1.0
0.2
15
5
mA
5
S
L
90
90
160
135
90
80
135
110
mA
=fMAX(3)
=
=
=fMAX(3)
=
SEMR
VIN~
=
COM'l,
=SEMl ~ Vee - 0.2V
Vc
265
VIN.s: 0.2V
Active Port Outputs Open,
f = fMAX(3)
NOTES:
1. "X" in part numbers indicates power rating (8 or L)
3039 !b110
2. Vce =SV, TA =+2S C, and are not production tested. leeDe =120mA (Typ.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using
"AC Test Conditions" of input levels of GND to 3V.
4. f =0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
o
6.18
5
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
DATAoUT
Output Reference Levels
1.5V
INT
BUSy--..--.--....
347n
DATAoUT---.--+-....
30pF
347(1
See Figures 1 & 2
Output Load
5pF
3039 tblll
2939 drw 03
2939drw04
Figure 1. AC Output Load
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
Including scope and jig.
ACELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
Symbol
Parameter
IDT70261 X20
IDT70261X25
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
-
25
-
ns
tAA
Address Access Time
20
ns
Chip Enable Access Time(3)
tABE
Byte Enable Access Time(3)
20
-
25
tACE
tAOE
Output Enable Access Time
-
12
-
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(1, 2)
tHZ
20
25
ns
25
ns
13
ns
3
-
ns
3
-
3
-
ns
Output High-Z Time(1, 2)
-
12
-
15
ns
tpu
Chip Enable to Power Up Time(2)
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
20
-
25
ns
tsop
Semaphore Flag Update Pulse (OE or SEM)
10
-
12
-
ns
tSAA
Semaphore Address Access Time
-
20
-
25
ns
Parameter
Symbol
IDT70261 X35
IDT70261X55
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
-
55
-
ns
-tAA
Address Access Time
35
ns
Chip Enable Access Time(3)
55
ns
tABE
Byte Enable Access Time(3)
55
ns
tAOE
Output Enable Access Time
-
55
tACE
-
30
ns
tOH
Output Hold from Address Change
3
-
3
ns
tLZ
Output Low-Z Time(1, 2)
3
-
3
-
tHZ
Output High-Z Time(1, 2)
-
15
-
25
ns
tpu
Chip Enable to Power Up Time(2)
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
35
-
55
ns
ns
35
35
20
tsop
Semaphore Flag Update Pulse (OE or SEM)
15
-
15
-
tSAA
Semaphore Address Access Time
-
35
-
55
NOTES:
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter iSJ!!:laranteed b~vice characterization, but is not production tested.
3. To access RAM, CE VIL and 8EM VIH. To access semaphore, CE VIH and 8EM VIL.
4. "X" in part numbers indicates power rating (8 or L).
=
=
=
6.18
ns
ns
3039 tbl12
=
6
IDT70261SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
1-+------ tAA (4)
-----I~
tACE(4) ---~
tAOE(4) ---~
UB,LB
RNi
DATAoUT--------------------------~
VALID DATA(4)
BUSYOUT
tBOO(3,4)
3039 drw05
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective lasl IAOE, lACE, lAA or tBDD.
5. SEM =VIH.
TIMING OF POWER-UP POWER-DOWN
CE
ICC
~~U]
(tPD1-
ISB
3039 drw06
6.18
7
II
IDT70261 S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
Symbol
Parameter
IDT70261X20
IDT70261X25
Min.
Min.
Max.
Max.
Unit
WRITE CYCLE
twe
Write Cycle Time
20
-
25
-
ns
tEW
Chip Enable to End-of-Write(3)
15
20
Address Valid to End-of-Write
15
tAS
Address Set-up Time(3)
0
0
0
-
ns
tAW
-
15
-
ns
20
ns
twp
Write Pulse Width
15
tWR
Write Recovery Time
0
tow
Data Valid to End-of-Write
15
-
tHZ
Output High-Z Time(1, 2)
-
12
-
15
ns
tOH
Data Hold Time(4)
0
-
0
-
ns
twz
Write Enable to Output in High-Z(1, 2)
-
12
-
15
ns
tow
Output Active from End.of-Write(1, 2, 4)
0
-
0
ns
tSWRO
SEM Flag Write to Read Time
5
5
tsps
SEM Flag Contention Window
5
-
-
Symbol
Parameter
20
5
IDT70261X35
IDT70261 X55
Min.
Min.
Max.
Max.
ns
ns
ns
ns
ns
Unit
WRITE CYCLE
twe
Write Cycle Time
35
-
55
-
ns
tEW
Chip Enable to End-of-Write(3)
30
45
-
ns
tAW
Address Valid to End-of-Write
30
45
-
ns
tAS
Address Set-up Time(3)
0
0
Write Pulse Width
25
40
-
ns
twp
tWR
Write Recovery Time
0
0
-
ns
tow
Data Valid to End-of-Write
15
-
30
-
ns
tHZ
Output High-Z Time(1, 2)
-
15
-
25
ns
tOH
Data Hold Time(4)
0
-
0
-
ns
twz
Write Enable to Output in High-Z(1, 2)
-
15
-
25
ns
tow
Output Active from End.of-Write(1, 2, 4)
0
0
-
ns
tSWRO
SEM Flag Write to Read Time
5
-
5
-
ns
tsps
SEM Flag Contention Window
5
-
5
-
ns
ns
NOTES:
3039tbl13
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL and 8EM VIH. To access semaphore, CE VIH and 8EM VIL. Either condition must be valid for the entire tEW time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (8 or L).
=
=
=
6.18
=
8
IDT70261SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING(1,5,S)
twc
y
ADDRESS
~~
Jr'\
J\
tHZ(7)
I
I
tAW
-,'t.
GEar SEM (9)
GEarSEM
J
(9)
-.l
J
tWp(2)
-tAS(61
~
(3)
tWR
...r'\
-,l
J
-=-=:J;.
~ tWZ(7)
DATAoUT
tow
(4)
.I]
-III
1\
(4)
,
J
DATAIN----------------------------~~~---------------~~~-----------------tow
tOH
3039 drw07
TIMING WAVEFORM OF WRITE CYCLE NO.2, GE, UB, LB CONTROLLED TIMING(1,5)
twc
~~
ADDRESS
-,~
J\
J\
tAW
GEar SEM
~t\
(9)
_tAs(6)
US
-.l
J
tWR(3)4-
tEW(2)
~r
r'\
ar LS (9)
-.l
J
\\\
.1-
------{~--J~tow
DATAIN
tOH
3039 drw08
NOTES:
1. RiW or CE or US and LS must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a LOW CE and a LOW RJW for memory array writing cycle.
3. tWR is measured from the earlier of CE or Rm (or SEM or RIW) going HIGH to the end of write cycle.
4. Durin~is period, the I/O pins are in the output state and input signals mu~ not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the RIW LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE or Rm.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tow. If OE is HIGH during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. To access RAM, CE V,L and SEM VIH. To access semaphore, CE V,H and SEM V,L. tEW must be met for either condition.
=
=
=
6.18
=
9
IDT10261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
~--tSAA
Ao - A2
VALID ADDRESS
DATA OUT
VALID
DATAo-------+------~-<
RAN-------4------,
tAOE
NOTE:
1. CE
3039 drw 09
=VIH or U8 and L8 =VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
r
...JX___________
Ao"A"-A2"A"____
M_A_TC_H
___
SIDE(2)
"A"
1
SEM"A"_ _ _ _ _ _. J
AO"B"-A2"B"
SIDE(2) "8"
NOTES:
1. OOR = DOL = Vll, CER = CEl = VIH, or both US & [8 = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "8" is the opposite from port "An.
3. This parameter is measured from RJ'iiif'A" or SEM"A" going HIGH to RJ'iiif'S" or SEM"s" going HIGH.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6"18
10
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Parameter
Svmbol
BUSY TIMING (MIS
IDT70261 X20
IDT70261X25
Min.
Max.
Min.
20
Max.
Unit
20
ns
=Hl
tBOC
BUSY Disable Time from Chip Enable HIGH
-
17
-
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
ns
tBOO
BUSY Disable to Valid Data(3)
-
20
-
25
ns
-
0
-
ns
17
50
ns
30
ns
tBAA
BUSY Access Time from Address Match
tBOA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
BUSY TIMING (MIS
20
20
20
ns
20
ns
17
ns
=L)
tWB
BUSY Input to Write(4)
0
tWH
Write Hold After BUSV(5)
15
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(1)
tODD
Write Data Valid to Read Data Delay(1)
Symbol
-
Parameter
BUSY TIMING (MIS
30
-
IDT70261X35
IDT70261 X55
Min.
Min.
Max.
Max.
Unit
=H)
tBAA
BUSY Access Time from Address Match
tBOA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
tBOC
BUSY Disable Time from Chip Enable HIGH
tAPS
Arbitration Priority Set-up Time(2)
tBOO
BUSY Disable to Valid Data(3)
BUSY TIMING (MIS
45
-
45
ns
40
ns
40
ns
20
-
35
ns
-
5
-
ns
-
35
-
55
ns
0
-
ns
25
5
20
20
20
=L)
tWB
BUSY Input to Write\'1)
0
tWH
Write Hold After BUS'(\5)
25
-
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay\l)
-
60
toDD
Write Data Valid to Read Data Delay\')
-
35
-
80
ns
55
ns
NOTES:
3039 tbl14
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and 8USY (MiS =VIH)".
2. To ensure that the earlier of the two ports wins.
3. tsoo is a calculated parameter and is the greater of 0, twoo - twp (actual) or tODD - tow (actual).
4. To ensure that the write cycle is inhibited on port "8" during contention on port "A".
5. To ensure that a write cycle is completed on port "8" after contention on port "AM.
6. "X" in part numbers indicates power rating (S or L).
6.18
11
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,5) (MiS
=VIH)
twc
ADDRnA
)(
)
MATCH
twp
~
K
toW
)(
DATAIN"A
/
<
'/
~<"
VALID
tAPS (1)
ADDR"B
) (~
\
BUSY"B
MATCH
tBAA
'l--'"
-
tBoA
J
tBDD
tWDD
)
DATAoUT"B
tDDD (3)
E
3039 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Mis = Vil (SLAVE).
2. eEL = CER = Vil
3. OE = Vil for the reading port.
4. If Mis =Vil (SLAVE), then BUSY is an input (BUSY'A' =VIH and BUSY"B' ="don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY (MiS
=VIL)
~----------------twP------------~
RiW"A"
BUSY"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking Rm"B", until BUSY"B" goes High.
6,18
12
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MIS
=H)
--JX,-__________
A~~:::~:: _ _
X. . ___
A_D_D_R_E_S_S_E_S_M_A_T_C_H_ _ _ _ _ _ _ _ _ _ _ _
IAPSI;c----~-----------
-e= q,"----IBAC
3039 drw 13
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDRESS "N"
ADDR"A"
'---.I tAps (2)
MATCHING ADDRESS "N"
ADDR"B'
lMA
~_
1-
_
IBDA
BUSY"B"
3039 drw 14
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from port "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
Parameter
IDT7025X20
IDT7025X25
Min.
Min.
Max.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
Symbol
Parameter
-
0
-
0
-
ns
20
-
20
ns
20
-
20
ns
IDT7025X35
IDT7025X55
Min.
Min.
Max.
Max.
ns
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
-
tiNS
Interrupt Set Time
-
25
tlNR
Interrupt Reset Time
-
25
NOTE:
1. "X" in part numbers indicates power rating (8 or L).
0
0
-
-
ns
40
ns
40
ns
ns
2683 tbl14
6.18
13
IDT70261SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
WVC--------------------~
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A'
__________________
tIN_S_3_)~
INT"B"
---------------------------------------------------
3039 drw 15
tRC --------------------~
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
OE"B"
tINR(3)
~_-------------------------------------------------3039 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "S" is the port opposite from port "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or RiW) is asserted last.
4. Timing depends on which enable signal (CE or RiW) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I--INTERRUPT FLAG(1)
Right Port
Left Port
RlWL
CEL
OEL A13L-AoL
L
L
X
3FFF
X
X
X
A13R-AoR INTR
L(2)
X
Function
INTL
RlWR
CER
OER
X
X
X
X
X
X
X
L
L
3FFF
H(3)
L
L
X
3FFE
X
Set Left INTL Flag
X
X
X
X
X
Reset Left INTL Flag
X
X
X
X
L(3)
X
L
L
3FFE
Hl~)
NOTES:
1. Assumes BUSYL = SUSYR =VIH.
2. If SUSYL VIL, then no change.
3. If SUSYR VIL, then no change.
Set Right INTR Flag
Reset Right INTR Flag
26831b116
=
=
6.18
14
IDT70261 S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
TRUTH TABLE II ARBITRATION
ADDRESS BUSY
Inputs
CEt.
CER
X
H
X
X
X
H
L
L
AOL-A13L
AOR-A13R
NO MATCH
MATCH
MATCH
MATCH
COMMERCIAL TEMPERATURE RANGES
Outputs
BUSYL(1)
BUSYR(1)
H
H
Function
Normal
H
H
Normal
H
H
Normal
(2)
(2)
Write Inhibit(3)
NOTES:
2683 tbl 17
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70261 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
00·015 Left
00·015 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Semaphore free
Left Port Writes "1" to Semaphore
1
1
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70261.
2683 tbl18
FUNCTIONAL DESCRIPTION
The IDT70261 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in m~mory. The IDT70261 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (lNTL) is asserted when the right port
writes to memory location 3FFE (HEX), where a write is
defined as CE =RiW =VIL per the Truth Table. The left port
clears the interrupt through access of address location 3FFE
when CER =OER =VIL, RiW is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
writes to memory location 3FFF (HEX) and to clear the
interrupt flag (INTR), the right port must read the memory
location 3FFF. The message (16 bits) at 3FFE or 3FFF is
user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random
access memory. Referto Table I forthe interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side thatthe RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
6.18
15
IDT70261SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 70261 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70261 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70261 RAM the busy pin
MASTER
Dual Port
fWL
I
CE
BUSY (L) BUSY (R)
T
SLAVE
Dual Port
.MM...
CE
roc
,w
0
0
u
w
BUSY (L) BUSY (R)
0
'--
1
MASTER
Dual Port
fWL
BUSY(L)
CE
BUSY(L) BUSY(R)
1
SLAVE
Dual Port
.MM...
CE
BUSY(L) BUSY(R)
I
BUSY(R)
3039 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70261 RAMs.
is an output if the part is used as a master (MIS pin = H), and
the busy pin is an input if the part used as a slave (MIS pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a masterlslave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with either the Rm signal orthe byte enables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
SEMAPHORES
The I DT70261 is an extremely fast Dual-Port 16K x 16
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT70261 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT70261's hardware semaphores, which
provide a lockout mechanism without requiring complex programming .
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT70261 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
6.18
16
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
semaphore's status or remove its request for that semaphore
to . perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the I DT7D261 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pi~ (which acts as a chip select for the semaphore flags) and
uSing the other control pins (Address, OE, and RiW) as they
would be used in accessing a standard Static RAM. Each of
t~e fla~s has a unique address which can be accessed by
either Side through address pins AD - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see .Table III): That semaphore can now only be modified by
the Side shOWing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that
the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch forthat side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
activ~. This s.erves to disallow the semaphore from changing
state In the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
sema~hor~ in a test loop must cause either signal (SEM or OE)
to go Inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a s~quence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
.B..EQ8I
J....E.Q..BI
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do
Do
WRITE
WRITE
SEMAPHORE __----~~
READ
'---"--____•
SEMAPHORE
READ
3039 drw 16
Figure 4. IDT70261 Semaphore Logic
the ~ame location. The reason for this is easily understood by
lo.oklng at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made the
logic guarantees that only one side receives the token. If'one
s~de is earlier than the other in making the request, the first
Side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resou~ce i~ secure.
As with any powerful programming
technique, If semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers forthe IDT70261 's Dual-Port
RAM. Say the 16K x 16 RAM was to be divided into two 8K
6.18
17
IDT70261S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGES
x 16 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 8K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore O. At this point, the software could choose to try
and gain control of the second 8K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the' semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT" state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
YBlank
L . . - - - - - - - - - - i PF
20
' " - - - - - - - - - - - - - - - i 25
35
55
Is
~----------------------~IL
L..----------------------l:
70261
1OO-pin TQFP (PN 100-1 )
} Speed in nanoseconds
Standard Power
Low Power
256K (16K x 16) Dual-Port RAM with Interrupt
3039 drw 19
6.18
18
t;)
HIGH-SPEED
32K X 16 DUAL-PORT
STATIC RAM
ADVANCED
IDT7027S/L
Integrated Device Technology, Inc.
• M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• TTL-compatible, single 5V (±10%) power supply
Available in an 108-pin PGA and a 100-pin Thin Quad
Plastic Flatpack TQFP
• Industrial temperature range (-40°C to +85°C) is available, tested to military electrical specifications
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Military: 35/55ns (max.)
- Commercial: 25/35/55ns (max.)
• Low-power operation
- IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
- IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7027 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
DESCRIPTION:
The IDT7027 is a high-speed 32K x 16 Dual-Port Static
RAM. The IDT7027 is designed to be used as a stand-alone
512K-bit Dual-Port RAM oras acombination MASTER/SLAVE
FUNCTIONAL BLOCK DIAGRAM
,
RlWl
UBl
I
-J
1
r-
1\
'-=
b!
I
h
I/0al-1/0 15l
!J4 I::1/0
Control
I/00l-1/0? l
•
BUSy[1.2)
··
A14l
AOl
Address
Decoder
I
~
'I
"
.A
~r
"v
.A
~
~~
I/OaR-I/015R
1/0
Control
~
•
MEMORY
ARRAY
15
"-
'I
V
L-
Address
Decoder
I
\
t
Mis
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
··
A14R
AOR
I
.-
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OEl.
RlWl:
\
.A
15
CEl'
_
..
I/OOR-I/O?R
BUSy~1,2)
.CER
tOER
~ .RlWR
I
\
SEMR
INT~2)
3199 drw 01
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
101995 Integrated Device Technology, Inc.
APRIL 1995
6.19
DSC108212
1
IDT7027SIL
HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
ADVANCED
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Dual-Port RAM for 32-bit-or-more word systems. Using the
lOT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOS high-performance technology, these devices typically operate on only 750mW of power.
The IDT7027 is packaged in a 100-pin TQFP and a 108pin PGA. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Clas B, making
it ideally suited to military temperature applications demanding the highest level of performance and reliability.
PIN NAMES (1,2)
Left Port
CEL
RIWL
OEL
AOL-A13L
Right Port
CER
RIWR
OER
AOR - A13R
I/OOL - I/015L
I/OOR - I/015R
SEML
UBL
LBL
INTL
BUSYL
SEMR
UBR
LBR
INTR
BUSYR
MIS
Vce
GND
Names
Chip Enable
ReadlWrite Enable
Output Enable
Address
Data InpuVOutput
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
3199 tbl 01
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
ORDERING INFORMATION
lOT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Processl
Temperature
Range
Y:lank
~----------------~
PF
G
~-----------------------1
25
35
55
~-----------------------1ls
IL
~--------------------------------------~: 7027
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
100-pin TQFP (PN100-1)
108-pin PGA (<3108-1)
Commercial Only }
Speed in nanoseconds
Standard Power
Low Power
512K (32K x 16) Dual-Port RAM with Interrupt
3199 drw 19
6.19
2
G@
HIGH-SPEED 3SK (4K x 9-BIT)
SYNCHRONOUS
DUAL-PORT RAM
IDT7099S
Integrated DevIce Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed clock-to-data output times
- Military: 20/25/30ns (max.)
- Commercial: 15/20/25ns (max.)
• Low-power operation
- IDT7099S
Active: 900 mW (typ.)
Standby: 50 mW (typ.)
• 4K X 9 bits
• Architecture based on Dual-Port RAM cells
- Allows full simultaneous access from both ports
- Independent bit/byte Read and Write inputs for control
functions
• Synchronous operation
- 4ns setup to clock, 1ns hold on all control, data, and
address inputs
- Data input, address, and control registers
- Fast 15ns clock to data out
- Self-timed write allows fast write cycle
- 20ns cycle times, 50MHz operation
• Clock enable feature
• Guaranteed data output hold times
• Available in 68-pin PGA, PLCC, and 80-pin TOFP
• Military product compliant to MIL-STD-883, Class B
The IDT7099 is a high-speed 4K x 9 bit synchronous DualPort RAM. The memory array is based on Dual-Port memory
cells to allow simultaneous access from both ports. Registers
on control, data, and address inputs provide low set-up and
hold times. The timing latitude provided by this approach
allow systems to be designed with very short realized cycle
times. With an input data register, thjs device has been
optimized for applications having unidirectional data flow or
bi-directional data flow in bursts. Changing data direction from
reading to writing normally requires one dead cycle.
Fabricated using IDT's BiCMOS high-performance technology, these Dual-Ports typically operate on only 900mW of
power at maximum high-speed clock-to-data output times as
fast as 15ns. An automatic power down feature, controlled
by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
The IDT7099 is packaged in a 68-pin PGA, 68-pin PLCC,
and a 80-pin TOFP. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
1I0Sl
I/Oo-7l .....---...01
WRITE
LOGIC
J-_ _. . . . I/OSR
I/Oo-7R
WRITE
LOGIC
MEMORY
ARRAY
SENSE
I - - - - - - , - - - - - i AMPS ...".-+-t--r--!-I~
BITOER
BITOEL
BYTE OEL - - - + - '
'----+--BYTEOER
L_+--U-W_-4-+I=::;=~-- CLKR
CLKl----~~~H-+_--~~--~--~
CLKEN-------r~r_+_--_r~--r_----~
BIT R!Wt.
~----4--ff~r_--+-+r~r_-----CLKENR
ST
ST
I-'-I-+-~WT
WT
GEN(1)
GEN(1)
BIT RlWR
BYTE RlWR
BYTE RlWl
AOl-A11l
AOR-A11R
3007 drwOl
NOTE:
1. Self-timed write generator.
APRIL 1995
MILITARY AND COMMERCIAL TEMPERATURE RANGE
C1995 Integrated Device Technology. Inc.
6.20
DSC-109713
1
IDT7099S HIGH-SPEED 36K {4K x 9-BIT}
SYNCHRONOUS DUAL-PORT RAM
MILITARY f'ND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
Y
L.....IL.....JL.....JL-JL.....JL-JL.....IL..JIIL.....JL.....JL.....IL-JL....JL-JL.....IL......I
9
A6L
] 10
A7L
8
7
6
5
4 3
""-
2 I I 68 67 66 65 64 63 62 61
~
60[
A7R
] 11
5g[
A8R
A8L
] 12
58[
A9R
A9L
] 13
5n
Al0R
Al0L
] 14
5s[
AllR
AllL
] 15
55[
BYTE OER
BYTE OEL
] 16
IDT7099
54(
BIT OER
BIT OEL
] 17
J68-1
5i
GND
Vee
BYTE RIWL
] 18
] 19
68-Pin PLCC
Top View (3)
52[
51[
GND
BYTE RlWR
BIT RIWL
] 20
50[
BIT RlWR
21
4g[
N/C
CEL
] 22
48[
CER
GND
]~
4n
GND
N/C ]
1/08L
] 24
4s[
1/08R
1/07L
] 25
45[
1/07R
1/06L
] 26
44[
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1/06R
'"
".,.,r-lrr"".,rJrlr-1r-1I1r111111"1
3007 drw 03
51
53
A4L
49
52
A6L
A7L
46
A2L
47
45
AlL
A3L
44
AOL
42
40
CLKL pu-.......-
MILITARY AND COMMERCIAL TEMPERATURE RANGJ:S
«:11995 Integrated Device Technology. Inc.
RIWp3
2674 drw01
The lOT logo and FourPort are trademarks of Integrated Device Technology. Inc.
6.23
APRIL 1995
DSC-1269/4
1
IDT7052SJL
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
from all ports. An automatic power down feature, controlled by
CE, permits the on-chip circuitry of each port to enter a very
low power standby power mode.
Fabricated using lOT's CMOS high-performance technology, this four port RAM typically operates on only 750mW of
power. Low-power (L) versions offer battery backup data
retention capability, with each port typically consuming 50llW
from a 2V battery.
The I0T7052 is packaged in a ceramic 108-pin PGA, a
plastic 132-pin quad flatpack, and a 120-pin thin quad flatpack.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
PIN CONFIGURATIONS
81
74
77
80
RfiJ
NC
P2
84
83
P2
87
86
90
88
Pv
P2
P2
P2
P2
P3
P3
P3
P3
Al0
P2
P2
P1
P1
91
A4
P1
P1
P1
94
97
P3
66
62
58
P6
/>g
P2
P2
P2
P3
P3
P3
103
1/01
P1
P1
105
1/03
P1
P1
2
4
1/07
P1
P1
3
NC
A
B
P6
46
17
21
\te
\te
GND
25
Pe
Al0
P4
P4
P4
43
7
10
16
13
19
22
I/~
I/~
1/03
1/01
1/03
P2
P2
P2
P3
P3
11
9
1/01
1/03
P2
C
14
15
18
20
34
BUSY
P4
P4
1/03
29
03
P4
30
1/07
1/03
I/~
P3
P4
P4
26
02
27
P2
P3
P3
P3
I/OJ
P4
F
G
H
J
K
L
E
04
33
I/O>
P4
1/03
D
05
P4
1/07
I/~
P2
RfiJ
36
32
23
•
06
38
OE
P4
I/~
1/07
pg
P4
I/OJ
P3
I/O>
P2
07
41
37
24
I/O>
P3
Pe
P4
NC
I/~
OS
42
h
P4
40
28
\te
GND
45
A4
P4
I/OJ
P2
6
I/O>
P1
12
8
\te
09
47
P4
GND
I/O>
P1
10
PG
GND
GND
fie
P4
P4
31
5
I/~
49
P1
1
I/~
P4
Po
35
106
BUSY
50
CE
P4
1/00
OE
P1
11
P3
Al
GND
10S-Pin PGl,2,3)
Top View
BUSY
P4
39
CE
P1
12
53
OE
P3
CE
P3
44
IDT7052
G10S-1
RfiJ
P3
51
55
h
102
100
108
P3
98
P1
107
P3
/tJ.
\te
NC
P1
P3
/J6
54
NC
56
/>a
Pe
P1
RfiJ
59
AlO
93
Pv
/la
P1
104
71
61
M
48
P6
101
75
P2
84
A
89
AlO
99
~
52
P1
A9
67
70
Nt
P2
85
Po
96
73
/>a
A3
95
~
P6
P6
92
57
A3
79
P1
60
63
Po
CE
P2
Al
65
Po
82
fie
P1
68
A3
76
OE
P2
69
P6
78
BUSY
72
Pv
1/01
01
P4
M
2674 drw02
Index
NOTES:
1. All Vee pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.23
2
IDT7052S/L
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D.)
IDT7052
PQ132-1
132-Pin Plasti~1.2,3.)
Quad Flatpaek
Top View
2674 drw 03
NOTES:
1. All Vee pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.23
3
IDT7052S/L
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D.)
omOO~~~~~N~omOO~~~~MN~omOO~~~~MN~
N/C
NLG
OE
P2
BUSYP2
AOP1
A1P1
A2P1
A3P1
A4P1
ASP1
N~~~~~~~~~~oooooooooommmmmmmmm
1',... ,.... ,.... ,.... ,... ,.... .,.... ,... ,.... .,... ,.... ,.... .,.... .,.... ,.... ,....
N/C
N/C
2
3
4
5
6
BUSYP3
AOP4
A1P4
A2P4
A3P4
A4P4
ASP4
A6P4
A10P4
7
8
9
10
11
A6P1
A10P1
12
Vee
13
A7P1
ASP1
A9P1
14
78
77
15
76
N/C
CEp1
R!WP1
OEp1
BUSYP1
I/OoP1
I/01P1
I/02P1
I/03P1
GND
I/04P1
I/OsP1
N/C
N/C
GND
IDT7052
120-pin TQFP
16
17
18
19
20
21
22
120-Pin Thin Quad Flatpae~1,2,3)
Top View
N/C
CEp4
71
25
26
27
28
29
GND
69
I/07P4
I/06P4
I/OsP4
63
62
N
MM
~ ~ ~ ~
00 mOT"" N
~ ~ ~ ~ ~ 00
mOT"" N (t) '<:t
~ ~ ~
00 m 0
-~·,(t)MM~(t)'<:t~~'<:t~~~~~~~~~~~~~~~~~
R!WP4
OEp4
BUSYP4
70
68
67
66
65
64
24
30T""
75
74
73
72
23
A7P4
ASP4
A9P4
61
GND
I/04P4
I/03P4
I/02P4
N/C
N/C
2674 drw 04
NOTES:
1. All Vee pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.23
4
•
IDT7052S/L
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1,2)
Symbol
ABSOLUTE MAXIMUM RATINGS(1)
Ao P1 -Al0 P1
Address Lines - Port 1
Ao P2
A10P2
Arlrlrp.!,;!,; I inp.!,; - Port ?
Ao P3 -AlOP3
Address Lines - Port 3
AoP4-Al0P4
Address Lines - Port 4
lIDo P1
n;:!t;:! lIn
1/07 P1
Symbol
Pin Name
Port 1
lIDo P2 - 1/07 P2
Data lID - Port 2
lIDo P3 - 1/07 P3
Data 1/0 - Port 3
1/00 P4 - 1/07 P4
Data 1/0 - Port 4
RfijP1
Read/Write - Port 1
RiWP2
Read/Write - Port 2
RiWP3
Read/Write - Port 3
Rating
Commercial
Military
Unit
-0.5 to +7.0
V
o to +70
-55 to +125
°C
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
rnA
VTERM(2)
Terminal Voltage -0.5 to +7.0
with Respect
toGND
TA
Operating
Temperature
TSIAs
NOTE:
2674 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + O.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to:s; 20mA forthe period of VTERM ~ Vcc
+O.5V.
RiWP4
Read/Write - Port 4
GND
Ground
CEP1
Chip Enable - Port 1
CEP2
Chip Enable - Port 2
CEP3
Chip Enable - Port 3
CEP4
Chip Enable - Port 4
OEP1
Output Enable - Port 1
OEP2
Output Enable - Port 2
OEP3
Output Enable - Port 3
OEP4
Output Enable - Port 4
Symbol
Max_
Unit
BUSYP1
Write Disable - Port 1
CIN
Input Capacitance
VIN = OV
9
pF
BUSYP2
Write Disable - Port 2
COUT
Output Capacitance
VOUT=OV
10
pF
BUSYP3
Write Disable - Port 3
BUSYP4
Write Disable - Port 4
Vee
Power
NOTES:
1. All Vee pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
CAPACITANCE (TQFP Package Only)
TA
2674 tbl 01
=+25°C, f =1.0MHz)
Parameter(1)
Conditions
NOTE:
2674 tbl 03
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and the
output signals switch from OV to 3V or from 3V to OV.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
GND
Vee
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
2674 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Parameter
Min.
Typ.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
V
Input Low Voltage
-
6.0(2)
VIL
2.2
-0.5(1)
0.8
V
Symbol
NOTE:
1. VIL ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.5V.
6.23
Max. Unit
2674 tbl 05
5
IDT7052S/L
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(VCC=5.0V± 10%)
IDT7052S
Symbol
Parameter
Test Conditions
Min.
IDT7052L
Max.
Min.
Max.
Unit
5
j.LA
5
j.LA
0.4
V
0.4
-
-
2.4
-
1IL11
Input Leakage Current(l)
Vee = 5.5V, VIN = OV to Vee
-
10
IILOI
Output Leakage Current
CE = VIH, VOUT = OV to Vee
-
10
VOL
Output Low Voltage
IOL = 4mA
-
VOH
Output High Voltage
IOH = -4mA
2.4
V
2674 tbl 06
NOTES:
1. At VCC:5,2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1 ' 5)
Symbol
Parameter
lee1
Operating Power
Supply Current
CE= VIL
Outputs Open
(All Ports Active)
f = 0(4)
Dynamic Operating
Current
CE= VIL
Outputs Open
(All Ports Active)
f = fMAX(5)
Standby Current
(All Ports - TTL
CE= VIH
f = fMAX(5)
lee2
IS8
Condition
Version
MIL.
All Ports
CE ~ Vee - 0.2V
CMOS Level Inputs)
VIN ~ Vee - 0.2V or
VIN:S; 0.2V, f = 0'4)
360
300
150
150
·360
300
150
150
300
250
150
150
300
250
210
180
395
330
195
170
390
325
210
180
335
290
195
170
330
285
-
40
35
110
80
35
30
105
75
60
50
85
70
40
35
75
60
35
30
70
55
-
-
-
1.5
.3
30
4.5
1.5
.3
30
4.5
1.5
.3
15
1.5
1.5
.3
15
1.5
1.5
.3
15
1.5
COM'L.
S
L
150
150
MIL.
S
L
-
COM'L.
S
L
225
195
S
L
-
S
L
S
L
S
L
MIL.
COM'L.
-
150
150
-
COM'L.
Full Standby Current
(All Ports-All
-
S
L
MIL.
Level Inputs)
IS81
(VCC = 5.0V ± 10%)
IDT7052X25
IDT7052X35
IDT7052X45
COM'L. ONLY
TypJ2) Max. Typ,(2) Max. Typ:2) Max.
Unit
300
250
350
305
-
mA
mA
mA
mA
NOTES:
2674 tbl 07
1. "X" in part number indicates power rating (8 or L).
2. Vcc =5V, TA = +25°C and are not production tested.
3. f =0 means no address or control lines change.
4. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions"
of input levels of GND to 3V.
5. For the case of one port, divide the appropriate current above by four.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
Test Condition
VDR
Vee for Data Retention
Vee = 2V
leeDR
Data Retention Current
CE~VHe
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
VIN
~
VHe or :s; VLe
NOTES:
1. Vcc =2V, TA = +25°C
2. tRC =Read Cycle Time
3. This parameter is guaranteed but not production tested.
I
I
Min.
Typ.(1)
Max.
-
2.0
-
MIL.
-
25
1800
COM'L.
-
25
600
0
-
-
tRe(2)
-
-
Unit
V
j.LA
ns
ns
2674 tbl 08
6.23
6
IDT7052S/L
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VOR~
2V
VOR
2674 drw 05
5V
5V
AC TEST CONDITIONS
893n
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
)ATAoUT
DATAoUT
5pF*
34m
See Figure 1
2674 drw 06
2674 tbl 09
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
"Including scope and jig
Figure 1. Output Test Load
(for tLZ, tHZ, twz, tow)
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(3)
IDT7052X25
IDT7052X35
IDT7052X45
Commercial
Svmbol
Min.
Parameter
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
45
-
ns
tM
Address Access Time
25
ns
25
45
ns
tAOE
Output Enable Access Time
-
15
-
25
-
45
Chip Enable Access Time
-
35
tACE
-
30
ns
tOH
Output Hold from Address Change
0
0
-
0
Output Low-Z Time(1, 2)
5
5
-
5
-
ns
tLZ
-
tHZ
Output High-Z Time(l, 2)
-
15
-
15
20
ns
tpu
Chip Enable to Power Up Time(2)
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
25
-
35
-
45
35
NOTES:
1. Transition is measured ±200mV from low or high impedance voltage with the Output Test Load (Figures 1 and 2).
2. This parameter is guaranteed but is not production tested.
3. "X" in part number indicates power rating (8 or L).
-
ns
ns
2674 tbl10
TIMING WAVEFORM OF READ CYCLE NO.1, ANY PORT(1)
ADDRESS
DATAoUT
~~~~_-~~_-~~_-~~_-~~_--t~O-H--~=-_~=- _t-A=-A=~ t_R~C--------------.-I----~~-t-OH---------__
__
PREVIOUS DATA VALID
NOTE:
1. RNJ =VIH, OE =VIL, and CC
DATA VALID
2674 drw 07
=VIL.
6.23
7
IDT7052S/L
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, ANY PORT(1,3)
tACE
-----~~
tAOE-----~
t - - - - - tLl
---~
DATAoUT .....----.....~----------.....--------.....----~~~_<1
~-------- tLZ-----~·~~~~----------r-------------'1
tpu
Icc----------------~~------------------------------------------------~
50%
CURRENT
ISB ---------------'
2674 drw 08
NOTES:
1. RfJij =VIH for Read Cycles.
2. Addresses valid prior to or coincident with CE transition LOW.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
IDT7052X25
COM'L. ONLY
Min.
Max.
Parameter
Symbol
IDT7052X35
IDT7052X45
Min.
Min.
Max.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
25
tEW
Chip Enable to End-of-Write
20
tAW
Address Valid to End-of-Write
20
-
-
45
-
30
35
-
ns
30
-
35
-
ns
35
tAS
Address Set-up Time
0
-
0
twp
Write Pulse Widthl;j)
20
-
30
tWR
Write Recovery Time
0
-
0
tDW
Data Valid to End-of-Write
15
-
20
-
tHZ
Output High-Z Time(l, ~)
-
15
-
15
tDH
Data Hold Time
0
-
Write Enabled to Output in High-Z(l, 2)
0
-
-
twz
15
-
15
tow
Output Active from End-of-Write(l, k
ADDR"A"
READ(1,2,3)
twc
)K
MATCH
twp
~
K
/
V
tow
)K
DATAIN"A"
ADDR"B"
tDH
)K
VALID
MATCH
tWDD
)
DATA"B"
tODD
E
2674 drw 11
NOTES:
1. Assume BUSY input VIH and CE VIL for the writing port.
2. OE VIL for the reading ports.
3. All timing is the same for left and right ports. Port 'A' may be either of the four ports and Port 'B' is any other port.
=
=
=
TIMING WAVEFORM OF WRITE WITH BUSY INPUT
twp
---i~
RiW"A'
BUSY"B'
(2)
2674 drw 12
NOTES:
1. BUSY is aserted on Port 'B' blocking R/W'B' until BUSY'B' goes HIGH.
TABLE I - READIWRITE CONTROL
Any Port(1)
FUNCTIONAL DESCRIPTION
The IDT7052 provides four ports with separate control,
address, and I/O pins that permit independent access for
reads or writes to any location in memory. These devices have
an automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output
Enable control (OE). In the read mode, the port's OE turns on
the output drivers when set LOW. READIWRITE conditions
are illustrated in the table below.
6.23
RIW
X
CE
OE
H
X
Z
Port Deselected: Power-Down
X
H
X
Z
L
L
X
DATAIN
CEp1 = CEp2 = CEp3 = CEp4
=VIH
Power Down Mode ISB or ISB1
Data on
written into
memory 2. 3)
00-7
H
L
L
DATAoUT
X
X
H
Z
Function
B0rt
Data in memory output on pon
Outputs Disabled
NOTES:
2698 tbl12
1. "H" = VIH, "L" = VIL, "X" = Don't Care, "Z "= High Impedance
2. If BUSY VIL, write is blocked.
3. For valid write operation, no more than one port can write to the same
address location at the same time.
=
10
IDT7052S/L
HIGH-SPEED 2K x 8 FourPort™ STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Y:lank
l ~QF
L...--------i
I PF
25
' - - - - - - - - - - - - - - - i 35
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
108-Pin Pin Grid Array (G108-1)
132-Pin Plastic Quad FlatRack (PQ132-1)
120-Pin Thin Quad Plastic Flatpack (PN 120-1 )
Commercial OnlY}
Speed in nanoseconds
45
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~IL
IS
'----------------------------------------i17052
Low Power
Standard Power
16K (2K x 8) FourPort RAM
2674 drw 13
6.23
11
t;J
HIGH SPEED 64K (4K X 16 BIT)
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAMTM)
IDT70824S/L
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 4K X 16 Sequential Access Random Access Memory
(SARAMTM)
- Sequential Access from one port and standard Random
Access from the other port
- Separate upper-byte and lower-byte control of the
Random Access Port
• High speed operation
- 20ns tAA for random access port
- 20ns tCD for sequential port
- 25ns clock cycle time
• Architecture based on Dual-Port RAM cells
• Electrostatic discharge ~ 2001 V, Class II
• Compatible with Intel BMIC and 82430 PCI Set
• Width and Depth Expandable
• Sequential side
- Address based flags for buffer control
- Pointer logic supports up to two internal buffers
• Battery backup operation - 2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 80-pin TQFP and 84-pin PGA
• Military product compliant to MIL-STD-883.
• Industrial temperature range (-40°C to +85°C) is available,
tested to military electrical specifications.
The IDT70824 is a high-speed 4K x 16-bit Sequential
Access Random Access Memory (SARAM). The SARAM
offers a single-chip solution to buffer data sequentially on one
port, and be accessed randomly (asynchronously) through
the other port. The device has a Dual-Port RAM based
architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with
counter sequencing for the sequential (synchronous) access
port.
Fabricated using CMOS high-performance technology,
this memory device typically operates on less than 900mWof
power at maximum high-speed clock-to-data and Random
Access. An automatic power down feature, controlled by CE,
permits the on-chip cirCUitry of each port to enter a very low
standby power mode.
The IDT70824 is packaged in a 80-pin Thin Plastic Quad
Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
RST
SCLK
CNTEN
Random
Access
Port
Controls
SOE
SSTRT1
SSTRT2
SCE
4KX 16
Memory
Array
DOO-15 ......1+-. ...!j!.....+1~
sRiW
SLD
DataL
DataR
Addl1.
AddrR
.I+!~"'...
12
12
SDOO-15
RST
Pointerl
Counter
12
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
12
COMPARATOR
3099 drw 01
The lOT logo Is a registered trademark and SARAM Is a trademark of Integrated Device Technology, Inc.
APRIL 1995
MILITARY AND COMMERCIAL TEMPERATURE RANGE
1e1995 Integrated Device Technology, Inc.
DSC-129112
6.24
1
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
All
Al0
A9
AB
A7
A6
A5
A4
A3
A2.
Vee
Vee
Al
Ao
CMD
CE
LB
UB
IDT70824
PN80-1
TQFP(3)
TOP VIEW
RiW
OE
o~o8goooo~oo66g~~~~~
o (!) 0 0 > 0 0 0 0 (!) 0 0 0 0 >
(!) 3099 drw 02
gggg
63
DOl
61
Vee
64
66
D02 NC
4B
46
54
60
5B
55
51
EOBl GND eNTEN GND SSTRT2 SR/W NC
62
59
56
49
50
DOo EOB2 SOE RST "'Srn
67
65
D03 GND
44
43
40
47
SCE SDOo SDOl SD03
57
53
52
SCLK GND SSTRTl
IDT70824
G84-3
74
75
70
D09 D05 DOB
84-PIN PGA(3)
TOP VIEW
76
77
78
DOlO DOll Vee
11
7
CMD Vee
12
A2
82
1
2
D015 GND OE
5
14
A4
17
Ao
10
Vee
84
NC
6
A
Pin 1
Designator
3
4
RiW
UB
CE
Al
15
A5
B
C
D
E
F
8
LB
9
10
09
38
37
SD04 SD05
08
34
33
35
SD08 SD07 GND
07
32
31
36
SD09 SD01C SD06
06
28
29
30
SD012 Vee SDOl
05
79
BO
D012 D013
81
83
D014 NC
11
41
39
SD02 Vee
69
68
D04 Vee
73
72
71
D07 D06 GND
45
42
GND NC
26
27
SD015 SDOk
04
23
25
NC SD01<
03
22
A7
20
Al0
24
GND GND
02
13
A3
16
A6
18
A8
19
A9
01
G
H
J
K
21
All
L
3099 drw 03
NOTES:
1. All Vec pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.24
2
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS: RANDOM ACCESS PORT
SYMBOL
NAME
Ao-A11
Address Lines
UO
I
DESCRIPTION
Address inputs to access the 4096-word (16 bit) memory array.
000-0015 Inputs/Outputs
I
Random access data inputs/outputs for 16-bit wide data.
CE
Chip Enable
I
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access
port is disabled into power-down mode and the 00 outputs are in the high-impedance state. All
data is retained during CE = VIH, unless it is altered by the sequential port. CE and CMO may not
be LOW at the same time.
CMO
Control Register
Enable
I
When CMO is LOW, Address lines AO-A2, RIW, and inputs/outputs 000-0011, are used to
access the,control register, the flag register, and the start and end of buffer registers. CMO and
CE may not be LOW at the same time.
RIW
ReadlWrite Enable I
If CE is LOW and CMO is HIGH, data is written into the array when RIW is LOW and read out of the
array when RiW is HIGH. If CE is HIGH and CMO is LOW, RiW is used to access the buffer command registers. CE and CMO may not be LOW at the same time.
OE
Output Enable
I
When OE is LOW and RIW is HIGH, 000-0015 outputs are enabled. When OE is HIGH, the 00
outputs are in the high-impedance state.
LB,UB
Lower Byte, Upper I
Byte Enables
When LB is LOW, 000-007 are accessible for read and write operations. When LB is HIGH, 000007 are tri-stated and blocked during read and write operations. UB controls access for 0080015 in the same manner and is asynchronous from LB.
vee
Power Supply
Seven +5V power supply pins. All Vcc pins must be connected to the same +5V
GNO
Ground
Ten Ground pins. All Ground pins must be connected to the same Ground supply.
vee supply.
3099 tbl 01
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
SYMBOL
NAME
UO
DESCRIPTION
SOOOS0015
Inputs
I/O
Sequential data inputs/outputs for 16-bit wide data.
SCLK
Clock
I
SOOO-S0015, SCE, SRIW' and SLO are registered on the LOW-to-HIGH transition of SCLK.
Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH
transition of SCLK when CNTEN is LOW.
SCE
Chip Enable
I
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of
SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on
the LOW-to-HIGH transition of SCLK, and the SOO outputs are in the high-impedance state. All
data is retained, unless altered by the random access port.
CNTEN
Counter Enable
I
When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.
SRIW
ReadlWrite Enable
I
When SRIW and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of
SCLK. When SRiW is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the
LOW-to-HIGH transition of SCLK.
SLO
Address Pointer
Load Control
I
When SLO is sampled LOW, there is an internal delay of one cycle before the address pointer
changes. When SLO is LOW, data on the inputs SOOO-S0011 is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following SLO, the address pointer
changes to the address location contained in the data-in register. SSTRT1 and SSTRT2 may
not be LOW while SLO is LOW or during the cycle following SLO.
SSTRT1,
SSTRT2
Load Start of
Address Register
I
When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the
address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in
internal registers. SSTRT1 and SSTRT2 may not be LOW while SLO is LOW or during the cycle
following SLO.
EOB1,
EOB2
End of Buffer Flag
a
EOB1 or EOB2 is output LOW when the address pointer is incremented to match the address
stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or
by writing zero into bit 0 and/or bit 1 of the control register at address 101. EOB1 and EOB2 are
dependent on separate internal registers, and therefore separate match addresses.
SOE
Output Enable
I
SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers
and the sequentially addressed data is output. When SOE is HIGH, the SOO output bus is in
the high-impedance state. SOE is asynchronous to SCLK.
RST
Reset
I
When RST is LOW, all internal registers are set to their default state, the address pointer is set
to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
Note: "1/0" is bidirectional Input and Output "I" is Input and "0" is Output.
6.24
3
IDT70824S/L
HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Terminal Voltage -0.5 to +7.0
with Respect
toGND
Military
-0.5 to +7.0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Unit
Ambient
Temperature
GND
VCC
-55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
V
Grade
Military
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
Commercial
3099 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTES:
3099 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any oth:>r conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + O.SV for more than 2S% of the cycle time
or 1Ons maximum, and is limited to ::;,.20mA forthe period OfVTERM ~ Vcc
+O.SV.
Min.
Typ.
Max.
Unit
vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
-
6.0(2
V
0.8
V
NOTE:
1. VIL ~ -1 .SV for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.SV.
3099 tbl 05
CAPACITANCE (TA =+25°C, F = 1.0MHz, TQFP only)
Symbol
Paramete~1)
CIN
Input Capacitance
COUT
Output
Capacitance
Conditions(2)
Max.
=3dV
VOUT =3dV
VIN
Unit
9
pF
10
pF
NOTE:
3099 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vee
Symbol
Parameter
lIul
Input Leakage Current
IILOI
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
Test Conditions
vee = Max. VIN = GND to vee
vee = Max. CE and SCE = VIH
VOUT = GND to vee
IOL = 4mA, vee = Min.
IOH = -4mA, vee = Min.
=5.0V ± 10%)
IDT70824S
Min.
Max.
IDT70824L
Min.
Max.
Unit
-
1.0
I1A
1.0
I1A
0.4
-
0.4
V
-
2.4
-
-
5.0
2.4
5.0
V
3099 tbl 07
6.24
4
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE(1)
(vee = 5.0V ± 10%)
70824X20
Symbol
ICC
IS81
IS82
IS83
IS84
Test
Condition
Parameter
=
Dynamic Operating
Current
CE VIL, Outputs
Open, SCE VIL(5)
(Both Ports Active)
f
Standby Current
(Both Ports - TTL Level
=fMAX(3)
=
SCE and CEr>- VIH(7)
CMD VIH
__
=
=fMAX(3)
Version
MIL.
S
L
70824X45
-
-
-
-
-
160
160
400
340
155
155
400 mA
340
170
170
360
310
160
160
340
290
155
155
340
290
MIL.
-
-
-
-
-
20
20
85
65
16
16
85
65
COM'L. S
L
25
25
70
50
25
25
70
50
20
20
70
50
16
16
70
50
MIL.
-
--
-
-
-
95
95
290
250
90
90
290
250
COM'L. S
L
115
115
260
230
105
105
250
220
95
95
240
210
90
90
240
210
-
S
L
Standby Current
(One Port - TTL Level
CE or SCE = VIH
Active Port Outputs
Input)
Open, f
Full Standby Current
(Both Ports - CMOS
Both Ports CE and
SCE ~ VCC - 0.2V(6)
MIL.
Level Inputs)
VIN ~ VCC - 0.2V or
VIN ~ 0.2V, f 0(4)
COM'L. S
L
Full Standby Current
(One Port - CMOS
Level Inputs)
One PortCEor
MIL.
SCE ~ VCC - 0.2V(6.7)
Outputs Open
S
L
S
L
S
L
=
(Active port), f fMAX(3 COM'L. S
VIN ~ VCC - 0.2V or
VIN ~ 0.2V
L
380
330
-
-
180
180
f
=
70824X35
COM'L. S
L
Inputs)
=fMAX(3)
70824X25
COM'L ONLY COM'LONLY
Typ.!2) Max. Typ,(2) Max. Typ,(2) Max. Typ.(2) Max. Unit
-
-
-
-
-
-
-
-
-
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
-
-
-
-
-
-
-
90
90
260
215
85
85
260
215
110
240
100
230
90
220
85
220
110
200
100
190
90
180
85
180
mA
mA
mA
mA
NOTES:
1.
2.
3.
4.
5.
6.
7.
'X' in part number indicates power rating (S or L).
Vce =5V, Ta =+25°C; guaranteed by device characterization but not production tested.
At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
f = 0 means no address or control lines change.
SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
SCE may be ~ O.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
If one port is enabled (either CE or SCE = Low) then the other port is disabled (SCE or CE =High, respectively). CMOS High ~ Vcc - O.2V and
Low::: O.2V, and TTL High = VIH and Low =VIL.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY) (VLC -< 0.2V, VHC -> VCC - 0.2V)
Parameter
Symbol
Test Condition
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR(3)
Chip Deselect to Data Retention Time
=2V
CE =VHC
I MIL.
VIN =VHC or =VLC I COM'L.
SCE = VHC(4) when SCLK= f
tR(3)
Operation Recovery Time
CMD> VHC
VCC
Max.
2.0
-
-
V
-
100
4000
flA
100
1500
0
tRC(2)
-
-
Unit
ns
ns
3099 tbl 09
NOTES:
1.
2.
3.
4.
Typ.(1)
Min.
TA= +25°C, Vee = 2V; guaranteed by device characterization but not production tested.
tRe =Read Cycle Time
This parameter is guaranteed by device characterization, but is not production tested.
To initiate data retention, SCE = VIH must be clocked in.
6.24
5
IDT70824SIL
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION POWER DOWN/UP WAVEFORM (RANDOM AND SEQUENTIAL PORT)(1,2)
DATA RETENTION MODE
VDR~
Vee
2V
SCLK
lee
ISB
NOTES:
1. SCE is synchronized to the sequential clock input.
2. CMD ~ Vcc - O.2V.
ISB
3099 drw 04
5
DATAoUT
BUSY----~~--~-
INT
34712
DATAoUT------.----+--~
30pF
34712
3099 drw05
5pF
3099 drw06
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ,
tBHZ,tOHZ,twHZ, tCKHZ, and tCKLZ)
Including scope and jig.
Figure 1. AC Output Test Load
8
7
6
b. tAA/tCD/tEB 5
(Typical, ns) 4
3
2
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns Max.
1.5V
1.5V
-3
See Figures 1 & 2
3099 drw07
3099 tbrlO
Figure 1A. Lumped Capacitance Load Typical Derating Curve
6.24
6
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
TRUTH TABLE: RANDOM ACCESS READ AND WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1,2)
Inputs/Outputs
CE
CMO
RIW
OE
LB
MOOE
UB
OQO-OQ7
OQ8-0Q15
L
H
H
L
L
L
DATAOUT
DATAOUT
L
H
H
L
L
H
DATAOUT
High-Z
L
H
H
L
High-Z
DATAOUT
H
L
L
H(3)
H
L
L
L
DATAIN
DATAIN
Write to both Bytes.
L
H
L
H(3)
L
H
DATAIN
High-Z
Write to lower Byte only.
L
H
L
H(3)
H
L
High-Z
DATAIN
Write to upper Byte only.
H
H
X
X
High-Z
Both Bytes deselected and powered down.
H
H
H
X
X
High-Z -
L
X
X
High-Z
High-Z
Outputs disabled but not powered down.
L
H
X
X
H
H
High-Z
High-Z
H
L
L
H(3)
U4)
U4)
DATAIN
DATAIN
H
L
H
L
L(4)
L(4)
DATAOUT
DATAOUT
Read both Bytes.
Read lower Byte only.
Read upper Byte only.
Both Bytes deselected but not powered down.
Write DOO-D011 to the Buffer Command Register.
Read contents of the Buffer Command Register via DOO-D012.
NOTE:
3099 tbl11
1. H = VIH, L = VIL, X = Oon't Care, and High-Z = High-impedance.
2. RST, SCE, CNTEN, sR/W, SLO, SSTRT1, SSTRT2, SCLK, SOOO-S0015, EOB1, EOB2, and SOE are unrelated to the random access port control and
operation.
3. If OE = VIL during write, tWHZ must be added to the twp or tcw write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
TRUTH TABLE: SEQUENTIAL READ
(1,2,3,4,5)
Inputs/Outputs
SCLK
f
f
f
f
f
SCE
MOOE
CNTEN SRIW EOB.1
EOB2
SOE
SOQ
L
L
H
LOW
LAST
L
[EOB1]
L
H
H
LAST
LAST
L
[E081 - 1]
Counter Advanced Sequential Read with EOB1 reached.
Non-Counter Advanced Sequential Read, without E081 reached.
L
L
H
LAST
LOW
L
[E082]
Counter Advanced Sequential Read with E082 reached.
L
H
H
LAST
LAST
L
[E082 - 1]
Non-Counter Advanced Sequential Read without E082 reached.
L
L
H
LOW
LOW
H
HIGH-Z
Counter Advanced Sequential Non-Read with E081 and E082
reached.
NOTES:
3099 tbl12
1. H = VIH, L = VIL, X = Oon't Care, High-Z = High impedance, and LOW = VOL.
2. RST, SLO, SSTRT1, SSTRT2 are continuously HIGH during sequential access, other than pointer access operations.
3. '[X]' refers to the contents of address 'X'.
4. CE, OE, RflJ, CMO, [8, UB, and 000-0015 are unrelated to the sequential port control and operation e~tfor CMO which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMO should be HIGH (CMO = VIH) during sequential port access.
5. "LAST" refers to the previous value still being output, no change.
TRUTH TABLE: SEQUENTIAL WRITE (1,2,3,4,5,6)
MOOE
Inputs/Outputs
SCLK SCE CNTEN SRIW EOB1
f
f
f
EO 82 SOE
SOQ
L
H
L
LAST
LAST
H
SDQIN
L
L
L
LOW
LOW
H
SDQIN Counter Advanced Sequential Write with E081 and E082 reached.
Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached
H
X
X
LAST
LAST
X
High-Z No Write or Read due to Sequential port Deselect.
3099 tbl13
NOTES:
1. H = VIH, L = VIL, X = Oon't Care, and High-Z = High-impedance. LOW = VOL.
2. RST, SLO, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMO, [8, UB, and 000-0015 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMO should be HIGH (CMO = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising
edge of the clock during the cycle in which sR/W = VIL.
5. SOOIN refers to SOOO-S0015 inputs.
6. "LAST" refers to the previous value still being output, no change.
6.24
7
II
IDT70824S/L
HIGH·SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: SEQUENTIAL ADDRESS POINTER OPERATIONS (1,2,3,4,5)
Inputs/Outputs
SCLK SLD SSTRT1
f
f
f
H
H
L
SSTRT2 SOE
L
H
H
H
H
MODE
Start address for Buffer #1 loaded into Address Pointer.
Start address for Buffer #2 loaded into Address Pointer.
X
H(6) Data on SDOo·SD012 loaded into Address Pointer.
X
L
NOTES:
3099 tbl14
1. H VIH, L VIL, X Don't Care, and High·Z High·impedance.
2. RST..!!..con~uous!l.!'IGH. The conditions of SCE, CNTEN, and sRIW are unrelated to the sequential address pointer operations.
3. CE,OE, RIW, LB, UB, and DOo·D015 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pOinter changes. The state of CNTEN is ignored and the address
is not incremented during the two cycles.
6. SOE may be LOW with SCE deselect or in the write mode using SRm.
=
=
=
=
=
ADDRESS POINTER LOAD CONTROL (SLD)
In SLD mode, there is an internal delay of one cycle before
the address pointer changes in the cycle following SLD. When
SLD is LOW, data on the inputs SDQo·SDQ11 is loaded into a
data·in register on the LOW·to·HIGH transition of SCLK. On
the cycle following SLD, the address pointer changes to the
SLD MODE
address location contained in the data·in register. SSTRT1,
SSTRT2 may not be low while SLD is LOW, or during the cycle
following SLD. The SSTRT1 and SSTRT2 require only one
clock cycle, since these addresses are pre·loaded in the
registers already.
(1)
(1)
SCLK
SDOO-11
SSTRT1.2
-----------«
c
B
A
-------»--------«
ADDRIN
X>< >< >< >I
DATAoUT
>-
1><><
3099 drw08
NOTE:
1. At SCLK edge (A), SDOO-SD011 data is loaded into a data-in register. At edge (B), contents of the data·in register are loaded into the address pointer
(Le. address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be high to ensure for proper sequential address pOinter loading. At SCLK
edge (B), SLD and SSTRT1.2 must be high to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be
ready for edge (B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
SEQUENTIAL LOAD OF ADDRESS INTO POINTER/COUNTER
15
14
13
12
(1)
11 •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 0
MSBI~H__~_H__~_H__~_L~~__~__~____~__~A_d_d_re_s~~_L_o_a~de~d_i_n_to~p_O_in_t_e~r____~__~__~__~ILSBSDOBITS
3099 drw 09
NOTE:
1. "H" = VIH and "L" = VIL for the SDO intput state.
6.24
8
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
Reset (RSl)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Register
Address Pointer
EOB Flags
Buffer Flow Mode
Start Address Buffer #1
End Address Buffer #1
Start Address Buffer #2(1)
End Address Buffer #2(1)
Registered State
Setting RST LOW resets the control state of the SARAM.
RST functicinsasynchronously of SCLK (i.e. not registered).
The default states after a reset operation are displayed in the
adjacent chart.
Contents
0
Cleared to High state
BUFFER CHAINING
0
(1 )
4095
(4K)
Cleared (set at invalid points)
Cleared (set at invalid points)
SCE =VIH, SRIW =VIL
3099 tbl15
Notes:
1. Start address and End of address for Buffer #2 and the Flow Control for
both Buffer #1 and #2, must be programmed as described in the "Buffer
Command Mode" section.
BUFFER COMMAND MODE (CMD)
Buffer Command Mode (CMO) allows the random access
port to control the state of the two buffers. Address pins Ao-A2
and I/O pins 000-0011 are used to access the start of buffer
and the end of buffer addresses and to set the flow control
mode of each buffer. The Buffer Command Mode also allows
reading and clearing the status of the EOB flags. Seven
different CMO cases are available depending on the conditions of Ao-A2 and RIW. Address bits A3-A 11 and data I/O bits
0012-0015 are not used during this operation.
RANDOM ACCESS PORT CMD MODE(1)
Case #
A2-AO
RIW
1
000
0(1)
2
001
0(1)
3
010
0(1)
4
011
0(1)
5
100
0(1)
6
101
0
7
101
1
8
110/111
(X)
DESCRIPTIONS
Write (read) the start address of Buffer #1 through 000-0011.
Write (read) the end address of Buffer #1 through 000-0011.
Write (read) the start address of Buffer #2 through 000-0011.
Write (read) the end address of Buffer #2 through 000-0011.
Write (read) flow control register
Write only - clear EOB1 and/or EOB2 flag
Read only - flag status register
(Reserved)
3099 tbl16
NOTES:
1. RiW input "0(1)" indicates a write(O) or read(1) occurring with the same address input.
CASES 1 THROUGH 4: START AND END OF BUFFER REGISTER DESCRIPTION (1,2)
15
14
13
12
11 -------------------------------------------------------------------------------------------------- 0
MSB~I__H~__H__~_H__~_L~____~__~__~____~A_d_d_re~s_s_L_o_ad~e_d_i_nt~o~B_u_ffe_r~__~__~____~__~ILSBOOBITS
3099 drw 10
NOTES:
1. "H" =VOH for DO in the output state and "Don't Cares" for DO in the input state. "L" =VIL for DO in the input state.
2. A write into the buffer occurs when Rfij=VIL and a read when Rfij=VIH. EOB1/S0B1 and EOB2ISOB2 are chosen through address AO-A2 while CMD
=VIL and CE =VIH.
CASE 5: BUFFER FLOW MODES
Within the SARAM, the user can designate one of two
buffer flow modes for each buffer. Each buffer flow mode
defines a uniq ue set of actions for the sequential port address
pointer and EOB flags. In BUFFER CHAINI NG mode, after the
address pointer reaches the end of the buffer, it sets the
corresponding EOB flag and continues from the start address
of the other buffer. In STOP mode, the address pointer stops
incrementing after it reaches the end of the buffer. There is no
linear or mask mode available.
6.24
9
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW CONTROL REGISTER DESCRIPTION{1,2)
o
MSB
LSB DO BITS
Buffer #2 flow control
3099 drw 11
NOTES:
1. "H" =VOH for DO in the output state and "Don~ Cares'" for DO in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs
asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next riSing edge of SCLK that is enabled
by CNTEN. The pOinter is also released by RST, SLD, SSTRT1 and SSTRT2 operations.
FLOW CONTROL BITS(5)
Flow Control Bits
Bit 1 & Bit 0
Bit 3 & Bit 2)
Mode
00
BUFFER
CHAINING
01
STOP
Functional Description
EOB1 (EOB2) is asserted (Active Low output) when the pointer matches the end address of Buffer
#1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1 ).(1,3)
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address ( EOB address + 1), if
CNTEN is Low on the next clock's rising edge. Otherwise, the address pointer will stop incrementing
on EOB. Sequential write operations are inhibited after the address pointer is stopped. The pointer
can be released by bit 4 of the flow control register. (1,2,4)
NOTES:
30991bl17
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD Flow Control bits are unchanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If the counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK; otherwise
the flow control will remain in the stop mode.
5. Flow Control Bit settings of '10' and '11' are reserved.
6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command
Mode" section. RST conditions are not set to valid addresses.
CASES 6 AND 7: FLAG STATUS REGISTER BIT DESCRIPTION(1)
15
o
LSB DQ BITS
MSB
NOTE:
1. "H" =VOH for DO in the output state and
"Don~
Cares" for DO in the input state.
End of buffer flag for Buffer #2
3099 drw 12
CASES 6: FLAG STATUS REGISTER WRITE CONDITIONS(1)
Flag Status Bit 0, (Bit 1)
Functional Description
0
Clears Buffer Flag EOB1, (EOB2).
1
No change to the Buffer Flag.(2)
NOTE:
30991bl18
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone, or both may be cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
CASE 7: FLAG STATUS REGISTER READ CONDITIONS
Flag Status Bit 0, (Bit 1) Functional Description
0
EOB1 (EOB2) flag has not been set, the
Pointer has not reached the End of the
Buffer.
1
EOB1 (EOB2) flag has been set, the
Pointer has reached the End ofthe Buffer.
30991bl19
6.24
10
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the DQ bus during a READ.
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (2,3)
Symbol
Parameter
IDT70824X20
IDT70824X25
COM'LONLY
COM'LONLY
Min.
Max.
Min.
IDT70824X35
Max.
Min.
Max.
IDT70824X45
Min.
Max.
Unit
READ CYCLE
tAC
Read Cycle Time
20
-
25
-
35
-
45
-
ns
tAA
Address Access Time
20
-
25
-
.35
-
45
ns
45
ns
45
ns
20
ns
tACE
Chip Enable Access Time
tBE
Byte Enable Access Time
tOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
3
tCLZ
Chip Select Low-Z Time(l)
3
20
20
10
tBLZ
Byte Enable Low-Z Time(!)
3
tOLZ
Output Enable Low-Z Time(1)
2
-
tCHZ
Chip Select High-Z Time(1)
-
10
tBHZ
Byte Enable High-Z Time(!)
Output Enable High-Z Time(1)
-
10
tOHZ
tpu
Chip Select Power-Up Time
tPD
Chip Select Power-Down Time
0
-
9
20
25
25
10
3
3
3
2
-
-
35
35
15
-
3
3
3
2
ns
3
-
ns
15
ns
15
ns
15
ns
3
12
15
11
-
15
0
-
0
-
25
15
-
-
-
2
-
12
3
0
-
35
ns
ns
-
ns
45
ns
NOTES:
3099 tbl 20
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. CMD access follows standard timing listed for both read and write accesses, ( CE VIH when CMD VIL) or ( CMD VIH when CE VIL).
=
=
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Parameter
IDT70824X20
IDT70824X25
COM'LONLY
COM'L ONLY
Min.
Max.
Min.
Max.
=
=
(2,4)
IDT70824X35
IDT70824X45
Min.
Min.
Max.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
20
-
25
tcw
Chip Select to End-ot-Write
15
-
20
tAW
Address Valid to End-ot-Write(3)
15
-
20
tAS
Address Set-up Time
0
twp
Write Pulse Width(3)
13
tBP
Byte Enable Pulse Width(3)
15
tWR
Write Recovery Time
0
0
-
20
-
25
20
-
25
0
35
25
25
0
0
-
-
45
30
30
0
30
30
0
ns
ns
ns
ns
ns
ns
ns
Write Enable Output High-Z Time(!)
-
10
-
12
-
15
-
15
ns
tDW
Data Set-up Time
13
-
15
20
0
-
0
tow
Output Active from End-ot-Write
3
-
3
-
3
-
ns
Data Hold Time
-
25
tDH
-
tWHZ
0
0
3
ns
ns
NOTES:
3099 tbl2!
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE VIH. If during the Rfiii controlled write cycle the OE is LOW, twp must be greater or equal to tWHZ + tDW to allow the DO
drivers to tum off and on the data to be placed on the bus for the required tOW. If OE is HIGH during the RlW controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tcw timing.
4. CMD access follows standard timing listed for both read and write accesses, ( CE VIH when CMD VIL) or ( CMD VIH when CE VIL ).
=
=
6.24
=
=
=
11
•
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
WAVEFORM OF READ CYCLES: RANDOM ACCESS
ADDR
~
~A
IRe
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PORT(1,2,3,4,5)
1-t-OH_ _ __
,I
tCHZ
LB, UB
tBHZ
to
DQOUT ___________________________--{
HZ
Valid Data Out
3099 drw 13
NOTES:
1. Rflii is HIGH for Read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise t AA is the limiting parameter.
WAVEFORM OF READ CYCLES: BUFFER COMMAND MODE
ADDR
~~:~~~~~~~~~~~~~~----t-RC--~~~~~~~~~~~~~~~~~~------------__________________________
~.-~---------tAA----------~.~1
..
~
LB, UB
to
HZ
Valid Data Out
DQOUT
3099 drw 14
NOTES:
1. CE
=VIH when CMD =VIL.
6.24
12
IDT70824S/L
HIGH·SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF WRITE CYCLE NO.1 (RMICONTROLLED TIMING) RANDOM ACCESS PORT(1,6)
twc
ADDR
tAw
twp(2)
__
--'8~~~""T'"""T'"""T'"_1
CE, LB, UB
DQIN .....- -....................~..........-r..................................................--[
OE ____________~-----4----------------------------------~~-----'
tWHZ
DQOUT
Data Out (4)
3099 drw 15
WAVEFORM OF WRITE CYCLE NO.2 (CE, LB,AND/OR UB CONTROLLED TIMING) RANDOM
ACCESS PORT(1,6,7)
twc
ADDR
/1\.
tAw
_ _ - i8 )
~ ~(5)
CE, LB, UB
-:l~
/
tAS
tWR (3)
tcw (2)
tBP (2)
'\.'\.'\.'\.,,<'<\.
DQIN
II
'\v
\V
J
--------«E
////////
tow
• I •
tOH
Valid Data
3099 drw 16
NOTES:
1. RiW, CE, or [8 and UB must be inactive during all address transitions.
2. A write occurs during the overlap of RiW"=VIL, CE =VIL and LB =VIL and/or UB =VIL.
3. tWR is measured from the earlier of CE (and LB and/or UB) or RiW going HIGH to the end of the write cycle.
4. During this period, DO pins are in the output state and the input siQ!!.als must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the RIW LOW transition, the outputs remain in the high-impedance state.
6. OE is continuously HIGH, OE =VIH. If during the
controlled write cycle the OE is LOW, twp must be greater or equal to twHZ + tow to allow the DO
drivers to turn off and on the data to be placed on the bus forthe required tOW. If OE is HIGH during the RiW controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tew timing.
7. DOoUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD =VIL, then CE must =VIH or, when CE =VIL, CMD must =VIH.
Rm
6.24
13
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2}
Symbol
Parameter
IDT70824X20
IDT70824X25
COM'L ONLY
COM'LONLY
Min.
Max.
Min.
IDT70824X35
Max.
IDT70824X45
Min.
Max.
Min.
-
50
18
18
Max.
Unit
READ CYCLE
25
12
12
5
2
-
Output Enable Low-Z Time(1)
2
tOHZ
Output Enable High-Z Time(1)
Clock to Valid Data
tCKHZ
Clock High-Z Time(l)
-
9
tCD
20
12
tCKLZ
Clock Low-Z Time(1)
tEB
Clock to EOB
3
13
-
tCYC
Sequential Clock Cycle Time
tCH
Clock Pulse HIGH
tCl
Clock Pulse LOW
tE8
Count Enable and Address Pointer Set-up Time
tEH
Count Enable and Address Pointer Hold Time
t80E
Output Enable to Data Valid
tOLZ
-
30
12
12
5
2
-
40
15
15
2
-
8
-
10
-
-
2
-
-
11
25
14
2
-
3
-
-
ns
6
-
2
-
ns
15
-
20
ns
-
2
-
ns
15
35
17
-
-
15
45
20
ns
-
-
3
-
3
-
ns
15
-
18
-
23
ns
6
ns
ns
ns
ns
ns
NOTES:
3099 tbl 22
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test load (Figure 2) by device characterization, but is not
production tested.
2. "XU in part numbers indicates power rating (8 or l).
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1}
Symbol
Parameter
IDT70824X20
IDT70824X25
COM'LONLY
COM'LONLY
Min.
Max.
Min.
Max.
IDT70824X35
IDT70824X45
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tCYC
Sequential Clock Cycle Time
25
-
30
-
40
-
50
-
ns
tF8
Flow Restart Time
-
13
-
15
-
20
-
20
ns
tW8
Chip Select and Read/Write Set-up Time
Input Data Set-up Time
tDH
Input Data Hold Time
-
-
-
ns
tD8
5
2
5
2
6
Chip Select and Read/Write Hold Time
-
6
tWH
5
2
5
2
-
NOTE:
1. "XU in part numbers indicates power rating (8 or l).
2
6
2
2
6
2
ns
ns
ns
3099 tbl23
6.24
14
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
Parameter
Symbol
IDT70824X20
IDT70824X25
COM'LONLY
COM'L ONLY
Min.
Max.
Min.
Max.
IDT70824X35
IDT70824X45
Min.
Min.
Max.
Max.
Unit
RESET CYCLE
tRSPW
Reset Pulse Width
tWERS
Write Enable HIGH to Reset HIGH
tRSRC
Reset HIGH to Write Enable LOW
tRSFV
Reset HIGH to Flag Valid
13
10
10
15
-
15
10
10
20
-
20
10
10
25
-
NOTE:
1. "X" in part numbers indicates power rating (S or L).
20
10
10
25
-
ns
-
ns
-
ns
ns
3099 tbl24
SEQUENTIAL PORT: WRITE, POINTER LOAD NON-INCREMENTING READ
SCLK
CNTEN
•
SLD
SDQIN
sRIW
SCE
SOE
SDQOUT
NOTE:
See notes in Figure "Sequential Port; Write, Pointer Load, Burst Read".
6.24
15
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: WRITE, POINTER LOAD, BURST READ
SCLK
SDQIN
SRIW
SDQouT -------------------------------+--~~_V_~~I~~~~
NOTES:
1. If SLD VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
=
=
READ STRT/EOB FLAG TIMING - SEQUENTIAL PORT
SCLK
SSTRT1/2
SDQIN
SRIW
SDQOUT
EOB1/2
3099 drw19
NOTES:
See notes in Figure "STRT/EOB Sequential Port Write Cycle".
6.24
16
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF WRITE CYCLES: SEQUENTIAL PORT
SCLK
SDQIN
SRm
to HZ
HIGH IMPEDANCE
SDQOUT--------------------------------------------~~
3099 drw 20
WAVEFORM OF BURST WRITE CYCLES: SEQUENTIAL PORT
SCLK
SDQIN
SRm
SDQOUT ________~H~I~G~H~I~M~P~E~D~A~N~C~E________+_----------------------~--------------_K
3099 drw21
NOTES:
1. If SLD VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN =VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is Low.
4. If sRiW VIL, data would be written to DO again since CNTEN VIH.
5. SOE =VIL makes no difference at this point since the SRiW =VIL disables the output until
=
=
=
6.24
sRiW =VIH is clocked in on the next rising clock edge.
17
IDT70824S/L
HIGH~SPEED
4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF WRITE CYCLES: SEQUENTIAL PORT (STRT/EOB FLAG TIMING)
SCLK
SSTRT1/2
SDQIN
SRm
SDQOUT--------~H~IG~H~IM~P~E~D~A~N~C~E~------------------------------r-------______~
tEB
EOB1/2
3099 drw 22
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing")
=
1. If SSTRT1 or SSTRT2 VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be High on Power-Up. If SCE VIL and is clocked in while sRiW' VIH, the data addressed will be read out within
that cycle. If SCE VIL and Is clocked in while sRIW VIL, the data addressed will be written to if the last cycle was a Read. SOE may be used to control
=
=
=
=
=
the bus contention and permit a Write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If sRIW = VIL, data would be written to DO again since CNTEN = VIH.
6. SOE VIL makes no difference at this point since the sRfii VIL disables the output until
=
=
6.24
sRIW =VIH is clocked in on the next rising clock edge.
18
IDT70824S/L
HIGH-SPEED 4K
x 16 SEQUENTIAL ACCESS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS MEMORY
RANDOM ACCESS PORT - RESET TIMING
tRSPW
tRSRC
ANi
CMDor
(UB + LB)
EOB1/2
- -~Flag Valid
3099 drw23
RANDOM ACCESS PORT RESTART TIMING OF SEQUENTIAL PORT (1)
0.5 x tCYC
tFS
~~
-'r-
SCLK
1\
(2)
/
-~
I
--.
--.
6-7ns
CLR(3)
Block
2-5ns
f+-
. .J.
/
--,
\
(Internal Signal)
3099 drw24
NOTE:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - AO] 100, when CMD VIL and CE = VIH. The device is in the Buffer Command Mode
(see Case 5).
3. CLR is an internal signal only and is shown for reference only.
=
=
6.24
19
IDT70824S/L
HIGH~SPEED
4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
70824
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Y:lank
'-----------1 GPF
20
'--_ _ _ _ _ _ _ _ _ _--1 25
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class 8
84-pin PGA (G84-3)
80-pin TQFP (PNBd-1)
Commercial OnlY}
Speed in nanoseconds
35
45
'--_ _ _ _ _ _ _ _ _ _ _ _ _--; S
L
L----------------------t 70824
Standard Power
Low Power
64K (4K x 16) Sequential Access Random Access
Memory
3099 drw 25
6.24
20
G
IDT70825S/L
HIGH SPEED 128K (8K X 16 BIT)
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAMTM)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 8K X 16 Sequential Access Random Access Memory
(SARAMTM)
- Sequential Access from one port and standard Random
Access from the other port
- Separate upper-byte and lower-byte control of the
Random Access Port
• High-speed operation
- 20ns tAA for random access port
- 20ns tCD for sequential port
- 25ns clock cycle time
• Architecture based on Dual-Port RAM cells
• Electrostatic discharge ~ 2001 V, Class II
• Compatible with Intel BMIC and 82430 PCI Set
• Width and Depth Expandable
• Sequential side
- Address based flags for buffer control
- Pointer logic supports two internal buffers
• Battery backup operation-2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 80-pin TQFP and 84-pin PGA
• Military product compliant to MIL-STD-883.
• Industrial temperature range (-40°C to +85°C) is available,
tested to military electrical specifications.
The IDT70825 is a high-speed 8K x 16bit Sequential
Access Random Access Memory (SARAM). The SARAM
offers a single-chip solution to buffer data sequentially on one
port, and be accessed randomly (asynchronously) through
the other port. The device has a Dual-Port RAM based
architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with
counter sequencing for the sequential (synchronous) access
port.
Fabricated using CMOS high-performance technology,
this memory device typically operates on less than 900mW of
power at maximum high-speed clock-to-data and Random
Access. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
The IDT70825 is packaged in a 80-pin Thin Plastic Quad
Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
CE
OE
RIW
LB lSB
Random
Access
Port
Controls
Sequential
Access
Port
Controls
8KX 16
Memory
Array
CMO
DOO-15
SOOO-15
DataR
Datal
RST
SCLK
CNTEN
SOE
SSTRT1
SSTRT2
SCE
SRIW
SLO
Addm
13
RST
Pointer/
Counter
13
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
13
COMPARATOR
3016 drw01
The lOT logo is a registered trademark and SARAM is, a trademark of Integrated Device Technology, Inc,
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MARCH 1995
DSC-1281/2
@1995 Integrated Device Technology, Inc.
6.25
1
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
SDOl
18079 7877 76 75 747372 71 7069 68 67 66 6564 63 62
SDOo
GND
N/C
SCE
SRIW
6
6~0
5
AS
SLD
SSTRT2
SSTRTl
GND
GND
CNTEN
SOE
SCLK
GND
IDT70S25
PNSO-1
TOFP(3)
TOP VIEW
All
Al0
A9
A8
A7
A6
A5
A4
A3
A2
Vee
Vee
Al
Ao
CMD
CE
LS
UB
RIW
OE
o~8a8aooo~00568~~~~~
o
63
DOl
61
Vee
66
64
002 NC
(!)
0 0
>
0 0 0 0 (!) 0
0 0 0
>
gggg
54
48
46
60
58
55
51
EOB1 GND CNTEN GND SSTRT2 SR/W NC
62
49
59
56
50
DOo EOB2" SOE RST m5
67
65
003 GND
IDT7OS25
GS4-3
84-PIN PGA(3)
TOP VIEW
78
76
77
DOlO D011 Vee
09
08
33
35
34
SD08 SD07 GND
07
32
31
36
SD09 ~D01C SD06
06
28
29
30
SD012 Vee SDOl
05
26
81
83
D014 NC
82
1
2
D015 GND OE
A
Pin 1
Designator
5
23
25
NC SDOl
03
Ao
10
Vee
14
A4
17
A7
20
Al0
22
A12
24
GND
02
18
A8
19
A9
21
All
01
8
LS
CE
Al
15
A5
13
A3
16
A6
S
C
D
E
F
G
H
6
04
12
A2
US
4
27
~D01E ~D01;:
7
11
CMD Vee
R!W
3
10
38
37
SD04 SD05
79
80
0012 D013
84
NC
11
41
39
SD02 Vee
69
68
D04 Vcc
75
70
74
009 D05 D08
45
42
GND NC
47
44
43
40
SCE SDOo SDOl SD03
57
53
52
SCLK GND SSTRTl
72
71
73
007 D06 GND
(!) 3016 drw 02
9
J
K
L
3016 drw03
NOTES:
1. All Vce pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.25
2
IDT70825SIL
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS: RANDOM ACCESS PORT
SYMBOL
NAME
Ao-A12
Address Lines
UO
I
DESCRIPTION
Address inputs to access the 8192-word (16 bit) memory array.
DQO-DQ15 Inputs/Outputs
I
Random access data inputs/outputs for 16-bit wide data.
CE
I
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access
port is disabled into power-down mode and the DQ outputs are in the high-impedance state. All
data is retained during CE VIH, unless it is altered by the sequential port. CE and CMD may not
be LOW at the same time.
Chip Enable
=
CMD
Control Register
Enable
I
When CMD is LOW, Address lines AQ-A2, RIW, and inputs/outputs DQO-DQ12, are used to
access the.control register, the flag register, and the start and end of buffer registers. CMD and
CE may not be LOW at the same time.
RIW
ReadlWrite Enable I
If CE is LOW and CMD is HIGH, data is written into the array when RIW is LOW and read out of the
array when Rm is HIGH. If CE is HIGH and CMD is LOW, Rm is used to access the buffer command registers. CE and CMD may not be LOW at the same time.
OE
Output Enable
I
When OE is LOW and RIW is HIGH, DQO-DQ15 outputs are enabled. When OE is HIGH, the DQ
outputs are in the high-impedance state.
LB,UB
Lower Byte, Upper I
Byte Enables
When LB is LOW, DQO-DQ? are accessible for read and write operations. When LB is HIGH, DQoDQ7 are tri-stated and blocked during read and write operations. UB controls access for DQ8DQ15 in the same manner and is asynchronous from LB.
vee
Power Supply
Seven +5V power supply pins. All Vcc pins must be connected to the same +5V vee supply.
GND
Ground
Nine Ground pins. All Ground pins must be connected to the same Ground supply.
3016 tbl 01
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
SYMBOL
NAME
UO
DESCRIPTION
SDQOSDQ15
Inputs
I/O
SCLK
Clock
I
SDQO-SDQ15, SCE, SRIW, and SLD are registered on the LOW-to-HIGH transition of SCLK.
Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH transition
of SCLK when CNTEN is LOW.
SCE
Chip Enable
I
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK.
When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW
to-HIGH transition of SCLK, and the SDQ outputs are in the high-impedance state. All data is
retained, unless altered by the random access port.
CNTEN
Counter Enable
I
When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.
SRIW
ReadlWrite Enable
I
When SRIW and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK.
When SRm is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH
transition of SCLK.
SLD
Address Pointer
Load Control
I
When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer
changes. When SLD is LOW, data on the inputs SDQo-SDQ12 is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following SLD, the address pointer
changes to the address location contained in the data-in register. SSTRT1 and SSTRT2 may not
be LOW while SLD is LOW or during the cycle following SLD.
SSTRT1,
SSTRT2
Load Start of
Address Register
I
When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the
address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in
internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle
following SLD.
EOB1,
EOB2
End of Buffer Flag
a
EOB1 or EOB2 is output LOW when the address pointer is incremented to match the address
stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or
by writing zero into bit 0 and/or bit 1 of the control register at address 101. EOB1 and EOB2 are
dependent on separate internal registers, and therefore separate match addresses.
SOE
Output Enable
I
SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers
and the sequentially addressed data is output. When SOE is HIGH, the SDQ output bus is in
the high-impedance state. SOE is asynchronous to SCLK.
RST
Reset
I
When RST is LOW, all internal registers are set to their default state. The address pointer is set
to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
Sequential data inputs/outputs for 16-bit wide data.
Note: "1/0" is bidirectional Input and Output. "I" is Input and "0" is Output.
6.25
3016 tbl 02
3
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
ABSOLUTE MAXIMUM RATINGS(1}
Symbol
VTERM(2)
Commercial
Rating
Terminal Voltage -0.5 to +7.0
with Respect
toGND
Military
-0.5 to +7.0
Unit
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
V
GND
VCC
Military
-55°C to +125°C
OV
5.0V± 10%
Commercial
O°C to +70°C
OV
5.0V± 10%
Grade
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
3016 tbl 04
NOTES:
3016 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 1Ons maximum, and is limited to ~ 20mA forthe period of VTERM ~ Vcc
+0.5V.
RECOMMENDED DC OPERATING
CONDITIONS
Min.
Typ.
Max.
Unit
vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
V
VIH
Input High Voltage
2.2
0
6.0(2)
VIL
Input Low Voltage
-0.5(1)
0.8
V
Symbol
Parameter
-
NOTE:
1. VIL ~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
V
3016 tbl 05
CAPACITANCE (TA = +25°C F = 1 OMHz TQFP only)
Conditions(2)
Symbol
Parameter<1)
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
9
pF
COUT
Output
Capacitance
VOUT= 3dV
10
pF
NOTE:
3016 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE (Vee S.OV ± 10%)
=
Symbol
Parameter
1IL11
Input Leakage Current
IILOI
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
Test Conditions
vee = Max. VIN = GND to vce
vee = Max. CE and SCE = VIH
VOUT = GND to vee
IOL = 4mA, vee = Min.
IOH =.-4mA, vee = Min.
IDT70825S
Min.
Max.
-
5.0
-
5.0
2.4
IDT70825L
Max.
Min.
Unit
-
1.0
1.0
IlA
IlA
0.4
-
0.4
V
-
2.4
-
V
3016 tbl 07
6.25
4
IDT70825S/L
HIGH·SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE(1) (vee =S.OV +
- 10%)
Symbol
ICC
IS81
IS82
IS83
IS84
Test
Condition
Parameter
Version
70825X20
70825X25
70825X45
70825X35
COM'LONLY COM'LONLY
Typ.(2) Max.
Typ,(2)Max. Typ.(2) Max. Typ,(2) Max. Uni
-
-
Dynamic Operating
Current
CE = VIL, Outputs
Open, SCE = VIL(S)
MIL.
(Both Ports Active)
f = fMAX(3)
COM'L. S
L
180
180
Standby Current
(Both Ports· TTL Level
SCE and CE2. VIH(7)
CMD = VIH
MIL.
-
-
Inputs)
f = fMAX(3)
COM'L. S
L
25
25
Standby Current
(One Port • TTL Level
CE or SCE = VIH
Active Port Outputs
MIL.
-
Input)
Open, f = fMAX(3)
COM'L. S
L
Full Standby Current
(Both Ports • CMOS
MIL.
Both Ports CE and
SCE ~ VCC • 0.2V(6.7)
Level Inputs)
VIN ~ VCC • 0.2V or
VIN ~ 0.2V, f = 0(4)
Full Standby Current
(One Port • CMOS
Level Inputs)
One Port CEor
SCE ~ VCC • 0.2V(6)
Outputs Open
S
L
S
L
S
L
115
115
-
-
160
160
400
340
155
155
400
340
360
310
160
160
340
290
155
155
340
290
-
-
20
20
85
65
16
16
85
65
70
50
25
25
70
50
20
20
70
50
16
16
70
50
--
-
-
-
95
95
290
250
90
90
290
250
260
230
105
105
250
220
95
95
240
210
90
90
240
210
-
-
380
330
170
170
-
-
-
-
1.0
0.2
30
10
1.0
0.2
30
10
COM'L. S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
MIL.
-
-
-
-
90
90
260
215
85
85
260
215
S
L
S
L
(Active port), f = fMAX(3) COM'L. S
VIN ~ VCC • 0.2V or
VIN ~ 0.2V
L
110
240
100
230
90
220
85
220
110
200
100
190
90
180
85
180
mA
mA
mA
mA
mA
NOTES:
3016 tbl 08
1. 'X' in part number indicates power rating (S or L).
2. Vee = SV, Ta = +2SoC; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, eontrollines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
6. SCE may be $; O.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = Low) then the other port is disabled (SCE or CE = High, respectively). CMOS High ~ Vce • O.2V and
Low.$; O.2V, and TIL High = VIH and Low = VIL.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY) (VLC -< O.2V, VHC -> VCC ·O.2V)
Symbol
Parameter
Test Condition
VDR
VCC for Data Retention
ICCDR
Data Retention Current
-CE= VHC
tCDR(3)
Chip Deselect to Data Retention Time
SCE = VHC(4) when SCLK=
tR(3)
Operation Recovery Time
CMD=VHC
VCC =2V
VIN = VHC or = VLC
I MIL.
I COM'L.
NOTES:
1. TA = +2S oC, Vee = 2V; guaranteed by device characterization but not production tested.
2. tRe = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
6.25
Min.
f
Typ,(1)
Max.
2.0
-
-
100
4000
100
1500
0
tRC(2)
-
-
-
-
Unit
V
~A
ns
ns
3016 tbl 09
5
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION AND POWER DOWN/UP WAVEFORM (RANDOM AND SEQUENTIAL PORT11,2)
DATA RETENTION MODE
Vee
VOR~
2V
VOR
SCLK
Icc
ISB
ISB
NOTES:
1. SCE is synchronized to the sequential clock input.
2. CMD
~
3016 drw 04
Vcc - O.2V.
DATAoUT
BUSy-----.--~--1
INT
347Q
DATAoUT.....----+---~--_
30pF
347Q
5pF
3016 drw 06
3016 drw 05
Figure 2. Output Test Load (for tCLl, tBLl, tOLZ, tCHZ,
tBHz, tOHZ, tWHZ, tCKHZ, and tCKLZ)
Including scope and jig.
Figure 1. AC Output Test Load
8
7
6
A tAMCD/tEB 5
(Typical, ns) 4
3
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
2
GND to 3.0V
3ns Max.
1.SV
1.SV
See Figures 1 & 2
-3
3016 drw 07
3016 tbl10
Figure 1A. Lumped Capacitance Load Typical Derating Curve
6.25
6
IDT70825SIL
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
TRUTH TABLE: RANDOM ACCESS READ AND WRITE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1,2)
Inputs/Outputs
CE
CMO
ANI
OE
LB
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
MOOE
UB
000-007
008-0015
L
L
OATAOUT
OATAOUT
L
H
OATAOUT
High-Z
Read lower Byte only.
H
L
High-Z
OATAOUT
Read upper Byte only.
L
L
H(3)
L
L
OATAIN
OATAIN
Write to both Bytes.
L
H(3)
L
H
OATAIN
High-Z
Write to lower Byte only.
H
L
H(3)
H
L
High-Z
OATAIN
Write to upper Byte only.
H
H
X
X
High-Z
Both Bytes deselected and powered down.
H
H
H
X
X
High-Z'
L
X
X
High-Z
High-Z
Outputs disabled but not powered down.
Read both Bytes.
L
H
X
X
Both Bytes deselected but not powered down.
L
H(3)
H
L<4)
High-Z
L
H
L<4)
High-Z
H
OATAIN
OATAIN
Write 000-0012 to the Buffer Command Register.
H
L
H
L
L<4)
L(4)
OATAOUT
OATAOUT
Read contents of the Buffer Command Register via 000-0012.
3016tbl11
NOTE:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST, SCE, CNTEN, sR/W, SLD, SSTRT1, SSTRT2, SCLK, SDQO-SD015, EOB1, EOB2, and SOE are unrelated to the random access port control and
operation.
3. If OE = VIL during write, tWHZ must be added to the twp or tew write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
TRUTH TABLE: SEQUENTIAL READ
(1,2,3,4,5)
Inputs/Outputs
SCLK
SCE
CNTEN SRIW EOB1
.f
.f
.f
.f
f
L
L
H
L
H
H
L
L
H
L
H
L
L
MOOE
SOO
EOB2
SOE
LOW
LAST
L
[EOB1]
LAST
LAST
L
[EOB1 -1]
Non-Counter Advanced Sequential Read, without EOB1 reached.
LAST
LOW
L
[EOB2]
Counter Advanced Sequential Read with EOB2 reached.
H
LAST
LAST
L
[EOB2 - 1]
Non-Counter Advanced Sequential Read without EOB2 reached.
H
LOW
LOW
H
HIGH-Z
Counter Advanced Sequential Non-Read with EOB1 and EOB2
reached.
Counter Advanced Sequential Read with EOB1 reached.
3016tbl12
NOTES:
1. H = VIH, L = VIL, X = Don't Care, High-Z = High impedance, and Low = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during sequential access, other than pointer access operations.
3. '[X)' refers to the contents of address 'X'.
4. CE, OE, R/W, CMD, LB, UB, and DOO-D015 are unrelated to the sequential port control and operation exceptfor CMD which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
5. "LAST" refers to the previous value still being output, no change.
TRUTH TABLE: SEQUENTIAL WRITE (1,2,3,4,5,6)
MOOE
Inputs/Outputs
SCLK SCE CNTEN SRIW EOB1
.f
.f
.f
EOB2 SOE
SOO
L
H
L
LAST LAST
H
SOQIN Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached
L
L
L
LOW
LOW
H
SOOIN Counter Advanced Sequential Write with EOB1 and EOB2 reached.
H
X
X
LAST
LAST
X
High-Z No Write or Read due to Sequential port Deselect.
3016 tbl13
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and DOO-D015 are unrelated to the sequential port control and operation exceptfor CMD which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising
edge of the clock during the cycle in which sR/W = VIL.
5. SDOIN refers to SDOO-SD015 inputs.
6. "LAST" refers to the previous value still being output, no change.
6.25
7
IDT70825S/L
HIGH·SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: SEQUENTIAL ADDRESS POINTER OPERATIONS (1,2,3,4,5)
Inputs/Outputs
SLD SS1RT1
H
L
H
H
L
H
SCLK
./"
./"
./"
SS1RT2 SOE
MODE
X
Start address for Buffer #1 loaded into Address Pointer.
H
L
X
Start address for Buffer #2 loaded into Address Pointer.
H(6) Data on SDQo·SDQ12 loaded into Address Pointer.
H
NOTES:
3016 tbl14
1. H = VIH, L = VIL, X = Don't Care, and High·Z = High-impedance.
2. RST~con~uous!l..tiIGH. The conditions of SCE, CNTEN, and sRIW are unrelated to the sequential address pointer operations.
3. CE, OE, Am, LB, UB, and DOo-D015 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD =VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address
is not incremented durin~e two cycles.
_
6. SOE may be LOW with SCE deselect or in the write mode using SRIW.
ADDRESS POINTER LOAD CONTROL (SLD)
In SLD mode, there is an internal delay of one cycle before
the address pointer changes in the cycle following SLD. When
SLD is LOW, data on the inputs SDQo·SDQ12 is loaded into
a data·in register on the LOW·to·HIGH transition of SCLK. On
the cycle following SLD, the address pointer changes to the
address location contained in the data·in register. SSTRT1,
SSTRT2 may not be low while SLD is LOW, or during the cycle
following SLD. The SSTRT1 and SSTRT2 require only one
clock cycle, since these addresses are pre·loaded in the
registers already.
SLD MODE (1)
SOOO-12
c
B
A
-------------« ....__A_O_O_R_I_N_ _»---------«
SSTRT1,2 X > < > < > < > 3
OATAoUT
>-
1><><
3016 drw 08
NOTE:
1. At SCLK edge (A), SDOO-SD012 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer
(Le. address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be high to ensure for proper sequential address pointer loading. At SCLK
edge (B), SLD and SSTRT1,2 must be high to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be
ready for edge (B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
SEQUENTIAL LOAD OF ADDRESS INTO POINTER/COUNTER (1)
15
14
13
12 ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.••••••••••••••••••••••••••••• 0
MSB 1L--_H-.l._H_...I.-_H_.1.-_..I-_--L_ _.1.-_.....L..._A_d..J.1_re_s_s_LJ....10_ad_e_d....JiL....nt_o_p_0..J.in_t_er_.1.-_..I-_-.l._ _..I......_.....J1 LSB SOO BITS
3016 drw 09
NOTE:
1. "H" =VIH for the SDO intput state.
6.25
8
IDT70825S/L
HIGH-SPEED 8K
x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Reset (RSl)
Setting RST LOW resets the control state of the SARAM.
RST functions asynchronously of SCLK, (Le. not registered).
The default states after a reset operation are as follows:
Register
Contents
Address Pointer
EOB Flags
0
Cleared to High state
Buffer Flow Mode
BUFFER CHAINING
Start Address Buffer #1
0
(1 )
End Address Buffer #1
4095
(4K)
Start Address Buffer #2
4096
(4K+1)
End Address Buffer #2
8191
(8K)
SCE =VIH, SRIW =VIL
Registered State
3016tbl15
BUFFER COMMAND MODE (CMD)
Buffer Command Mode (CMO) allows the random access
port to control the state of the two buffers. Address pins Ao-A2
and I/O pins 000-0012 are used to access the start of buffer
and the end of buffer addresses and to set the flow control
mode of each buffer. The Buffer Command Mode also allows
reading and clearing the status of the EOB flags. Seven
different CMO cases are available depending on the conditions of Ao-A2 and RIW. Address bits A3-A12 and data I/O bits
0013-0015 are not used during this operation.
RANDOM ACCESS PORT CMD MODE(1)
Case #
A2-AO
RNi
1
000
0(1)
Write (read) the start address of Buffer #1 through 000-0012.
2
001
0(1)
Write (read) the end address of Buffer #1 through 000-0012.
3
010
0(1)
Write (read) the start address of Buffer #2 through 000-0012.
4
011
0(1)
Write (read) the end address of Buffer #2 through 000-0012.
5
100
0(1)
Write (read) flow control register
6
101
0
Write only - clear EOB1 and/or EOB2 flag
7
101
1
Read only - flag status register
8
110/111
(X)
DESCRIPTIONS
(Reserved)
NOTES:
1. RiW input "0(1)" indicates a write(O) or read(1) occurring with the same address input.
3016 tbl16
CASES 1 THROUGH 4: START AND END OF BUFFER REGISTER DESCRIPTION(1,2)
15
14
13
12 ------------------------------------------------------------------------------------------------------------ 0
MSB~I__H~__H__~_H__~__~__~__~____~_A_d_?~r_es_s_L~~_a_d_ed~in_to_B_u~ff_e_r__~__~__~____~__~ILSBOOBITS
NOTES:
3016 drw 10
1. "H" VOH for DO in the output state and "Don't Cares" for DO in the input state.
2. A write into the buffer occurs when RNT VIL and a read when RiW' VIH. EOB1/S0B1 and EOB2ISOB2 are chosen through address AO-A2 while CMD
VIL and CE VIH.
=
=
=
=
=
CASE 5: BUFFER FLOW MODES
Within the SARAM, the user can designate one of four
buffer flow modes for each buffer. Each buffer flow mode
defines a unique set of actions for the sequential port address
pointer and EOBflags.ln BUFFER CHAINING mode, after the
address pointer reaches the end of the buffer, it sets the
corresponding EOB flag and continues from the start address
of the other buffer. In STOP mode, the address pointer stops
incrementing after it reaches the end of the buffer. In LINEAR
mode, the address pointer ignores the end of buffer address
and increments past it, but sets the EOB flag. MASK mode is
the same as LINEAR mode except EOB flags are not set.
6.25
9
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW CONTROL REGISTER DESCRIPTION(1,2}
o
15
MSB
LSB DO BITS
NOTES:
Buffer #2 flow control
3016 drw 11
1. "H" VOH for DO in the output state and "Don't Cares'" for DO in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs
asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled
by CNTEN. The pointer is also released by RST, SLD, SSTRT1 and SSTRT2 operations.
=
FLOW CONTROL BITS
Flow Control Bits
Bit 1 & Bit 0
Bit 3 & Bit 2)
Mode
00
BUFFER
CHAINING
01
STOP
10
LINEAR
11
MASK
Functional Description
EOB1 (EOB2) is asserted (Active Low output) when the pointer matches the end address of Buffer
#1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1 ).(1,3)
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if
CNTEN is Low on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on
EOB. Sequential write operations are inhibited after the address pointer is stopped. The pointer can be
released by bit 4 of the flow control register. (1,2,4)
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The pointer keeps incrementing for further operations.!l)
EOB1 (EOB2) is not asserted when the pointer reaches the end address of Buffer #1 (Buffer #2),
although the flag status bits will be set. The pointer keeps incrementing for further operations.
NOTES:
3016 tbl17
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD Flow Control bits are unChanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK otherwise
the flow control will remain in the STOP mode.
CASES 6 AND 7: FLAG STATUS REGISTER BIT DESCRIPTION(1}
o
15
MSB~I_H__~_H~__H~__H~__H~__H~__H__~H__~_H~__H~__H~__H~__H__~_H~-'~~TO~I
NOTE:
1. "H"
IJ
End
=VOH for DO in the output state and "Don't Cares" for DO
in the input state.
LSBDOBITS
buffer flag for Buffer"
End of buffer flag for Buffer #2
3016 drw 12
CASES 6: FLAG STATUS REGISTER WRITE CONDITIONS(1}
Flag Status Bit 0, (Bit 1)
Functional Description
0
Clears Buffer Flag EOB1, (EOB2).
1
No change to the Buffer Flag.(2)
NOTE:
3016 tbl18
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone or cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
CASE 7: FLAG STATUS REGISTER READ CONDITIONS
Flag Status Bit 0, (Bit 1) Functional Description
0
EOB1 (EOB2) flag has not been set, the
Pointer has not reached the End of the
Buffer.
1
EOB1 (EOB2) flag has been set, the
Pointer has reached the End of the Buffer.
3016 tbl19
6.25
10
IDT70825S/L
HIGH-SPEED 8K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the DO bus during a READ.
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (2,3)
S~mbol
Parameter
IDT70825X20
IDT70825X25
COM'LONLY
COM'LONLY
Min.
Max.
Min.
IDT70825X35
Max.
IDT70825X45
Min.
Max.
Min.
Max.
Unit
35
35
35
15
45
ns
3
3
3
2
45
45
45
20
-
-
ns
-
ns
-
ns
-
ns
READ CYCLE
tRC
Read Cycle Time
20
-
25
-
35
tAA
Address Access Time
-
20
-
25
25
25
10
-
3
3
3
2
-
3
3
3
2
-
-
12
12
11
-
15
15
15
-
15
15
15
0
-
-
0
-
0
-
ns
25
-
35
-
45
ns
tACE
Chip Enable Access Time
tBE
Byte Enable Access Time
tOE
Output Enable Access Time
tOH
Output Hold from Address Change
tCLZ
Chip Select Low-Z Time(l)
tBLZ
Byte Enable Low-Z Time(l)
tOLZ
Output Enable Low-Z Time(l)
tCHZ
Chip Select High-Z Time(l)
tBHZ
Byte Enable High-Z Time(l)
tOHZ
Output Enable High-Z Time(l)
tpu
Chip Select Power-Up Time
tPD
Chip Select Power-Down Time
3
3
3
2
20
20
10
-
-
-
10
10
0
-
-
20
9
-
-
ns
ns
ns
ns
ns
ns
ns
NOTES:
3016 tbl 20
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. CMD access follows standard timing listed for both read and write accesses, ( CE VIH when CMD VIL ) or ( CMD VIH when CE VIL ).
=
=
=
=
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (2,4)
Symbol
Parameter
IDT70825X20
IDT70825X25
COM'LONLY
,COM'LONLY
Min.
Max.
Min.
Max.
IDT70825X35
IDT70825X45
Min.
Min.
Max.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
tcw
Chip Select to End-at-Write
tAW
Address Valid to End-ot-Write(3)
tAS
Address Set-up Time
twp
Write Pulse Width(3)
tBP
Byte Enable Pulse Width(3)
tWR
Write Recovery Time
tWHZ
Write Enable Output High-Z Time(l)
tDW
Data Set-up Time
tDH
Data Hold Time
tOw
Output Active from End-of-Write
20
15
15
0
13
15
0
13
0
3
10
-
-
25
20
20
0
20
20
0
-
-
12
15
0
3
-
35
25
25
0
25
25
0
20
0
3
-
-
-
-
-
45
30
30
0
30
30
0
-
ns
15
-
15
ns
-
25
0
3
-
ns
-
-
ns
-
ns
-
ns
-
ns
ns
ns
ns
ns
NOTES:
3016 tbl 21
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE VIH. If during the RiW controlled write cycle the OE is LOW, twp must be greater or equal 10 tWHZ + tDW to allow the DQ
drivers to tum off and on the data to be placed on the bus forthe required toW. If OE is HIGH during the RiW controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tcw timing.
4. CMD access follows standard timing listed for both read and write accesses, ( CE VIH when CMD VIL) or ( CMD = VIH when CE = VIL).
=
=
6.25
=
11
II
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
WAVEFORM OF READ CYCLES: RANDOM ACCESS
ADDR
={
tRC
PORT(1,2}
{
.1
tAA
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tOH
CE
tCHZ
LB, UB
tBHZ
OE
tOHZ
OQOUT
Valid Data Out
3016 drw 13
NOTES:
1. RIW is HIGH for Read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise t AA is the limiting parameter.
WAVEFORM OF READ CYCLES: BUFFER COMMAND MODE
ADDR
~::~_~~~~~~~~~~~~~t_AA~~~=~ tR=C==-_~=~~=-_~~.~1~~~~~~~~~:~~~-----tO-H-------------------------__ __
___
---11) --"""'t"""'t""", ....f - - - CMD
tCHZ
tBHZ
tOHZ
OQOUT
Valid Data Out
3016 drw 14
NOTES:
1. CE VIH when CMD
=
=VIL.
6.25
12
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF WRITE CYCLE NO.1 (R/W CONTROLLED TIMING) RANDOM ACCESS PORT(1,6)
twc
ADDR
tAW
Rm
twp(2)
__ .....
~8~~~~~~-
CE, LB, UB
DQIN ..............................~...............~..................................................-(
OE ____________+-____~--------------------------------~-----J
tWHZ
DQOUT
tow
Data Out (4)
3016 drw 15
WAVEFORM OF WRITE CYCLE NO.2 (CE, LB, ANDIOR UB CONTROLLED TIMING) RANDOM
ACCESS PORT(1,6,7)
twc
AD DR
\V
/1\
\/
/,
tAW
__ ..... -18)
~t..
~r- (5)
CE, LB, UB
/
1\
tAS
tWR (3)
tcw (2)
Rm
DQIN
tsp (2)
\..\..\..\..\..\..\..
--------«E
tDW
.1. IIIIIIII
tDH
Valid Data
33016 drw 16
NOTES:
1. RIW, CE, or LS and US must be inactive during all address transitions.
2. A write occurs during the overlap of Rfii VIL, CE VIL and IB VIL and/or US VIL.
3. tWR is measured from the earlier of CE (and LS and/or US) or RIW going HIGH to the end of the write cycle.
4. During this period, DO pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the RIW LOW transition, the outputs remain in the high-impedance state.
6. OE is continuously HIGH, OE VIH. If during the
controlled write cycle the OE is LOW, twp must be greater or equal to tWHZ + tow to allow the DO
drivers to turn off and on the data to be placed on the bus for the required tOW. If OE is HIGH during the RIW controlled write cycle, this requirement
does not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tew timing.
7. DOouT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD VIL, then CE must VIH or, when CE VIL, CMD must VIH.
=
=
=
=
=
Rm
=
6.25
=
=
=
13
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2)
Symbol
Parameter
IDT70825X20
IDT70825X25
COM'LONLY
COM'L ONLY
Min.
Min.
Max.
IDT70825X35
Max.
Min.
Max.
-
IDT70825X45
Min.
Max.
Unit
READ CYCLE
tCYC
Sequential Clock Cycle Time
tCH
Clock Pulse HIGH
-
25
12
12
5
2
-
40
15
15
-
6
-
30
12
12
5
2
-
8
-
-
-
50
18
18
-
ns
6
-
ns
2
-
2
-
ns
10
-
15
-
20
ns
ns
tCL
Clock Pulse LOW
tE8
Count Enable and Address Pointer Set-up Time
tEH
Count Enable and Address POinter Hold Time
t80E
Output Enable to Data Valid
tOLZ
Output Enable Low-Z Time(1)
2
-
2
-
2
-
2
-
ns
tOHZ
Output Enable High-Z Time (1 )
9
tCKHZ
Clock High-Z Time(1)
-
11
25
14
-
15
35
17
-
15
45
20
ns
Clock to Valid Data
-
-
tCD
-
tCKLZ
Clock Low-Z Time(1)
-
3
-
3
-
3
-
ns
tEB
Clock to EOB
-
-
15
-
18
-
23
ns
20
12
3
13
ns
ns
ns
NOTES:
3016 tbl22
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part numbers indicates power rating (8 or L).
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
Parameter
Symbol
IDT70825X20
IDT70825X25
COM'LONLY
COM'LONLY
Min.
Max.
Min.
Max.
IDT70825X35
IDT70825X45
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tCYC
Sequential Clock Cycle Time
25
-
30
-
40
-
50
-
ns
tF8
Flow Restart Time
-
13
-
15
-
20
-
20
ns
tW8
Chip Select and ReadIWrite Set-up Time
ns
2
-
2
-
Input Data Set-up Time
6
-
ns
Input Data Hold Time
-
6
tDH
-
6
tD8
5
2
5
2
-
Chip Select and ReadIWrite Hold Time
-
6
tWH
5
2
5
2
2
-
NOTE:
1. "X" in part numbers indicates power rating (8 or L).
2
ns
ns
3016 tbl23
6.25
14
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
Symbol
Parameter
IDT70825X20
IDT70825X25
COM'LONLY
COM'LONLY
Min.
Max.
Min.
Max.
IDT70825X35
IDT70825X45
Min.
Max.
Min.
Max.
Unit
20
10
10
25
-
20
10
10
25
-
ns
-
ns
RESET CYCLE
tRSPW
Reset Pulse Width
tWERS
Write Enable HIGH to Reset HIGH
tRSRC
Reset HIGH to Write Enable LOW
tRSFV
Reset HIGH to Flag Valid
13
10
10
15
-
15
10
10
20
-
-
NOTE:
1. "X" in part numbers indicates power rating (S or L).
ns
ns
3016 tbt 24
SEQUENTIAL PORT: WRITE, POINTER LOAD NON-INCREMENTING READ
SCLK
SDQIN
sRiW
SDQOUT ________________~----------_;--~
NOTE:
See notes in Figure "Sequential Port: Write, Pointer Load, Burst Read".
6.25
15
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: WRITE, POINTER LOAD, BURST READ
SCLK
SDQIN
SRm
SDQOUT ------------------------------~---K~~~I~
__
_J
NOTES:
1. If SLD VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
=
READ STRT/EOB FLAG TIMING - SEQUENTIAL PORT
3016 drw19
NOTES:
See notes in Figure "STRT/EOB Sequential Port Write Cycle".
6.25
16
IDT70825S/L
HIGH·SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF WRITE CYCLES: SEQUENTIAL PORT
SCLK
SDQIN
SRm
tOHZ
HIGH IMPEDANCE
SDQOUT--------------------------------------------~~
3016 drw 20
WAVEFORM OF BURST WRITE CYCLES: SEQUENTIAL PORT
SCLK
SDQIN
sRIW
+_----------------------+_------------_«
SDQOUT ________~H~IG~H~IM~P~E=D~A~N~C~E~______
3016 drw 21
NOTES:
1. If SLD VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is Low.
4. If SRIW = VIL, data would be written to DO again since CNTEN = VIH.
5. SOE =VIL makes no difference at this pOint since the sRfiJ =VIL disables the output until
=
=
6.25
sRfiJ =VIH is clocked in on the next rising clock edge.
17
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF WRITE CYCLES: SEQUENTIAL PORT (STRT/EOB FLAG TIMING)
SCLK
SSTRT1/2
SDQIN
SRm
SDQOUT--------~H~IG~H~IM~P~E~D~A~N~C~E~------------------------------~------______-«
tEB
EOB1/2
3016 drw 22
NOTES: (Also used in the Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN
VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be High on Power-Up. If SCE VIL and is clocked in while sRiifi[ VIH, the data addressed will be read out within
that cycle. If SCE = VIL and is clocked in while sRiW = VIL, the data addressed will be written to if the last cycle was a Read. SOE may be used to control
the bus contention and permit a Write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SRiW VIL, data would be written to DO again since CNTEN VIH.
6. SOE =VIL makes no difference at this point since the SRIW =VIL disables the output until sRiW =VIH is clocked in on the next rising clock edge.
=
=
=
=
=
=
6.25
18
IDT70825SIL
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT - RESET TIMING
tRSPW
tRSRC
RAN
~~-r'-~~~-r~~~~-r~~~~-r~~~~--------~--------~
CMDor
(UB + LB)
EOB112
- -~Flag Valid
3016 drw 23
RANDOM ACCESS PORT RESTART TIMING OF SEQUENTIAL PORT (1)
0.5 xtCYC
tFS
Rm
-~
I
Jf-
SCLK
f\
(2)
...:1_
I
-.
-----+ 2-5ns
6-7ns
CLR(3)
Block
~
-J.
J
~ ....
\
(Internal Signal)
3016 drw 24
NOTE:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - AD] 1~O, when CMD VIL and CE VIH. The device is in the Buffer Command Mode
(see Case 5).
3. CLR is an internal signal only and is shown for reference only.
=
=
6.25
=
19
IDT10825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
70825
X
XX
X
x
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Y:lank
G
~--------------~ PF
~
_________________
~
20
25
35
45
~
________________________-; S
~-----------------------------t
Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
84-pin PGA (G84-3)
80-pin TQFP (PNBd-1)
c,ommercial OnlY}
Commercial Only
Speed in nanoseconds
L
Standard Power
Low Power
70825
128K (8K x 16) Sequential Access Random Access
Memory
3016 drw 25
6.25
20
(;)®
PRELIMINARY
IDT71 V321 S/L
CMOS DUAL-PORT RAM
3.3V, 16K (2K x a-BIT)
WITH INTERRUPTS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
-Commercial: 25/35/55ns (max.)
• Low-power operation
-IDT71V321S
Active: 250mW (typ.)
Standby: 3.3mW (typ.)
-IDT71 V321 L
Active: 250mW (typ.)
Standby: 660llW (typ.)
• Two INTflags for port-to-port communications
• On-chip port arbitration logic
• BUSY output flag
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TTL-compatible, single 3.3V ±O.3V power supply
• Available in popular plastic packages
The IDT71 V321 is a high-speed 2K x a Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications. The IDT71V321 is designed to be used as a
stand-alone a-bit Dual-Port RAM.
The device provides two independent ports with separate control, address, and I/O pins that permit independent,
asynchronous access for reads or wri~s to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 250mW of
power. Low-power (L) versions offer battery backup data
retention capability, with each Dual-Port typically consuming 200llW from a 2V battery.
The IDT71 V321 devices are packaged in 52-pin PLCCs
and 64-pin TQFPs.
,....
FUNCTIONAL BLOCK DIAGRAM
-,
--...I
1I
1
\.
~
I/00l- 1/07l
I/O
Control
··
AOl
Address
Decoder
I
NOTE:
1.IDT71V32 1
(MASTER ):
BUSY and NT
are totem-po Ie
outputs.
r-
/1
--'"
~
v
/1
1
~
t.........
Control
+
MEMORY
ARRAY
BUSYR (1.2)
A
I\.
'I
V
"
"
ARBITRATION
and
INTERRUPT
LOGIC
CEl:
DEL!
RfNl~
)
I/OOR-I/07R
liD
_I\.
If
•
1.2)
Al0l
J
[
]
t
I I
/
Address
Decoder
.:
Al0R
AOR
I
.CER
.O~
IRIWR
i
INTR(2)
3026 drwOl
COMMERCIAL TEMPERATURE RANGES
CC1995 Integrated Device Technology. Inc.
APRIL 1995
6.26
DSC-1089/1
IDT71V321 S/L
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
NDEX
LJLJLJLJLJLJIILJLJLJLJLJLJ
] 8 7 6 5 4 3 2 L152515049484J6[
45[
]9
OER
AOR
Am
A2R
A3R
IDT71V321
J52-1
A4R
ASR
PLCC
TOP VIEW (1)
A6R
A7R
ASR
A9R
NC
]2~1
2223 2425 2627 2829 3031 32 3~4[
..,..,..,..,..,..,..,..,..,..,..,..,..,
I/07R
3026 drw02
NOTE: 1. This text does not indicate the orientation ofthe actusl part-marking .
II:
...I
a: 1-:: I~ II: II:
Q
Q ~ II- I~
=> I~
c::::: IW8 8 IW c::::: => IF ~ Q Q
ZZ«~IIla:O>::>Oa:IIl~«ZZ
...I
...I
...I
~Ct)C\lT""OCJ)
oa
LO LO LO LO LO ~ 48
Pill
A1l
A2l
Asl
Ml
Asl
A6l
47
46
IDT71V321
PN64-1
64-PIN TQFP
TOP VIEW (1)
N/C
A7l
Aal
A9l
OER
AOR
A1R
A2R
A3R
A4R
ASR
A6R
N/C
A7R
ABR
A9R
N/C
N/C
N/C
I/00l
1/01l
1/02l
1/07R
1/06R
-'0
(')_
...I
...I
...I
-'000
~U')(Or-...-ZZ
II:
0
II: II:
....
II:
0
(\1(')_
II:
II:
' Vee - 0.2V or
VIN ~ 0.2V, f = 0(4)
SEMR = SEML > Vee - 0.2V
Full Standby Current
(One Port-All
CE'A' < 0.2V and
CE'6' -; Vee - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML ~ Vee - 0.2V
VIN ~ Vee - 0.2V or VIN !5 0.2V
Active Port Outputs Open
f = fMAX(3)
NOTES:
2943 tbl 05
1. "X" in part numbers indicates power rating (S or L)
o
2. Vee =3.3V, TA =+2S C, and are not production tested. leeDe =BOmA (Typ.)
3. At f fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRe. and using "AC Test Conditions'
of input levels of GND to 3V.
4. f =0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
=
DATA RETENTION CHARACTERISTICS (LVersion Only)
Symbol
VDR
-ICCDR
tCDR(3)
Test Conditions
Parameter
VCC for Data Retention
Min.
I COM'L.
Data Retention Current
VCC = 2.0V, CE ~ VCC - 0.2V
Chip Deselect to Data
VIN ~.VCC - 0.2V or VIN!5 0.2V
71V321L
Typ.c1)
2.0
-
-
100
Max.
Unit
0
V
1500
~
0
-
-
ns
tRC(2)
-
-
ns
Retention Time
tR(3)
Operation Recovery
Time
NOTES:
1. Vee = 2V, TA = +2S o C, and is not production tested.
2. tRe =Read Cycle Time.
3. This parameter is guaranteed but not tested.
3026tbl06
6.26
4
IDT71V321S/L
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
DATA RETENTION WAVEFORM
GND to 3.OV
5ns
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA RETENTION MODE
1.5V
1.5V
Vee
See Figure 1
3026 tbl 07
d,eDR
VDR 2: 2.0V
3.0V
3.0V
VOR
'\~------------~~
CE
VIH
tRb
VIH
3026 drw 04
33[
~
'3
590,Q
590n
DATA OUT
DATA OUT
43S0YSPF
435,Q
1OOpF for 55 and 100ns versions
Figure 2. Output Test Load
(For tHZ, tLZ, twz and tow)
• Including scope and jig.
Figure 1. AC Output Test Load
3·11670
•
3026 drw 05
BUSYOrINT--+
1
-30pF
DO,F
t., 55 . .d 100. . . .",."'
Figure 3. BUSY and INT
AC Output Test Load
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
71V321X25
Min.
Parameter
Symbol
71V321X35
Max.
Min.
Max.
71V321X55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
55
-
ns
tAA
Address Access Time
Chip Enable Access Time(3)
tAOE
-
55
55
-
-
35
35
Output Enable Access Time
25
25
12
ns
tACE
-
25
ns
-
3
0
-
3
0
-
ns
-
ns
-
15
-
ns
0
-
0
30
-
-
50
-
50
ns
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1· 2)
tHZ
Output High-Z Time(l, 2)
tpu
Chip Enable to Power Up Time(2)
tpo
Chip Disable to Power Down Time(2)
3
0
0
-
-
12
50
NOTES:
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed b~vice characterization, but is not production tested.
3. To access RAM, CE ::: VIL and SEM::: VIH. To access semaphore, CE ::: VIH and SEM ::: VIL.
4. "X" in part numbers indicates power rating (S or L).
6.26
20
ns
ns
2943 tbl 08
5
I
IDT71V321 SIL
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1)
ADDRESS ______
~ ~
'/:==
~-tO-H------------------------
me
tOH
DATA VALID
DATAoUT
------------------------------~~~~
BUSyOUT----------~~~~~~~~~-----------------------------------------------3026 drw06
tBDDH (2,3)
NOTES:
1. Rfjij VIH, CE VIL, and is OE VIL. Address is valid prior to the coincidental with CE
transition Low.
2. tBOD delay is required only in case where the opposite is port is completing a write operation to
same the address location. For simultanious read operations BUSY has no relationship to valid
output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
=
=
=
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(3)
tACE
CE
~ ....
1\
,~
tAOE
I
(4)
tHz(2)
I
~[-
OE
LtHZ"L.
r\
tLl
(1)
..,f-//..,f-
DATAoUT
-'[-\~-''''''
tLl (1)
=t
I---tPU
CC
CURRENT ________________~- 50%
'.
VALID DATA
tPD(4)
-,'-
50%1_____
Iss
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is deaserted first, OE or CEo
3. Rfjij VIH, and the address is valid prior to other coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tM, and tBOD.
3026 drw07
=
6.26
6
IDT71V321S/L
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(S)
71V321X25
Symbol
Parameter
Min.
Max.
71V321X35
Min.
71V321X55
Max.
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
25
-
35
tEW
Chip Enable to End-of-Write(3)
20
30
tAW
Address Valid to End-of-Write
20
tAS
Address Set-up Time(3)
0
twp
Write Pulse Width
20
-
tWR
Write Recovery Time
0
-
0
-
30
0
30
55
40
40
0
40
J
0
-
ns
ns
ns
ns
ns
ns
tow
Data Valid to End-of-Write
12
-
20
-
20
-
ns
tHZ
Output High-Z Time(l, 2)
-
12
-
15
-
30
ns
tOH
Data Hold Time(4)
0
-
0
-
0
-
ns
twz
Write Enable to Output in High-Z(1, 2)
-
15
-
15
-
30
ns
tow
Output Active from End-of-Write(l, 2, 4)
0
-
0
-
0
-
ns
NOTES:
2943 tbl 09
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL and SEM VIH. To access semaphore, CE VIH and SEM VIL. Either condition must be valid for the entire tEW time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
=
=
=
6.26
=
7
IDT71V321SIL
CMOS DUAL·PORT RAM 16K (2K X 8-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 ,(RNI CONTROLLED TIMING) (1,5,8)
twc
ADDRESS
==>
jK
V
r'\.
tHZ (7)
}
tAW
~ r'\.
"'
RMI
~
./
(7)
tHZ
V
tWZ(7)
tow
~I
(4)
DATA OUT
~
tWI=I (3)
twp(2)
tA!=:(6)
1
lr
tnH
tow
I
DATA IN
(4)
)~
J
I
1
3026 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,5)
twc
ADDRESS
~
---../
)K
K
tAW
/V
CE
tAS")
}
tEW(2)
I
I
DATA IN
I
tWR(3)f.-
tow
tOH
_I
~
"I
3026 drw 09
NOTES:
1. RJW or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or twp) of CE = VIL and RJW= VIL.
3. tWR is measured from the earlier of CE or
going High to the end of the write cycle.
4. Durin[!lis period, the I/O pins are in the output state and input silElals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High impedance state.
6. Timing depends on which enable signal (CE or RNi) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- SOOmV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a RJW controlled write cycle, the write pulse width must be the larger of twp or (twz + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a RJW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twP.
Rm
6.26
8
IDT71V321S/L
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
71V321X25
Symbol
Parameter
71V321X35
Min.
Max.
-
20
20
20
20
Min.
71V321X55
Max.
Min.
Max.
Unit
-
30
30
30
30
ns
BUSY TIMING (MiS = VII!l
tBAA
BUSY Access Time from Address Match
-
tBDA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
-
tBDC
BUSY Disable Time from Chip Enable HIGH
-
20
20
20
20
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
5
-
ns
tBDD
BUSY Disable to Valid Data(3)
Write Pulse to Delay Data\ll
-
55
80
65
ns
tDDD
35
60
45
-
Write Pulse to Delay Data(l)
25
50
35
-
tWDD
-
-
-
ns
ns
ns
ns
ns
NOTES:
2943tbl10
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. taoo is a calculated parameter and is the greater of 0, twoo - twp (actual) or toDD - tow (actual).
4. To ensure that the write cycle is inhibited on port "S" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
TIMING WAVE FORM OF WRITE WITH PORT-TO-PORT READ WITH BUSY (1,2,3)
twc
ADDR'A
)K
)(
MATCH
twp
RIw 'A'
~,
//
)k:H
tDW
DATAIN'A'
ADDR'B'
)~
VALID
I-IAPS(l~
MATCH
)
BUSY'B'
tBDA-'
tBDD-.
\~
tWDD
DATAoUTB'
)K
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
=CEA =VIL
=
2. eEL
VALID
DDD
3026 drw 10
3. OE VIL for the reading port.
4. All-timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is opposite from port "A".
6.26
9
IDT71 V321 SIL
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSV(3)
NOTES:
1 . tWH must be met for BUSY.
2. BUSY is asserted on port 'B' blocking ANI·s·, until BUSY·s· goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is oppsite from port "A".
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CETIMING
AD DR
'A' AND 'B'
------v
~
- . / ' \ ' -_ _ _ _ _ _ _ _ _ _
A_DD_RE_S_S_E_S_M_A_T_C_H_ _ _ _ _ _ _ _ _ _ _~
_ 1~pj~ _
BUSY'A'
(1)
_~_mAc=q
__+_1--LtBDC=1_ _
3026 drw 12
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING
~-----tRC
ADDR'A'
(1)
OR twc -------I~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR'B'
BUSY'B'
3026 drw 13
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. If tAps is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be
asserted.
6.26
10
IDT71V321S/L
CMOS DUAL-PORT RAM 16K (2K x 8-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
71V321X25
Symbol
Parameter
Min.
Max.
71V321X35
Min.
Max.
71V321X55
Min.
Max.
Unit
-
0
-
ns
0
25
25
-
45
45
INTERRUPT TIMING
tAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
-
tlNR
Interrupt Reset Time
-
-
0
25
25
-
0
NOTE:
1. "X" in part numbers indicates power rating (S or L).
ns
ns
ns
2942 tbl11
TIMING WAVEFORM OF INTERRUPT MODE
INTSETS
~
M
JWRI~
x'----_
INTERRUP;:DDRESs'"
:J~s~
ADDR'A'
O
]-IINS
INT'B'
(
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
3026drw 14
INTCLEARS
ADDHB'
tRC
xxxxxxxxx~
INTERRUPT CLEAR ADDRESS
tAS
(3)
OE'B'
INT'A'
3026 drw 15
NOTES:.
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or RiW) is asserted last.
4. Timing depends on which enable signal (CE or RiW) is de-asserted first.
6.26
11
IDT71 V321 S/L
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I. NON-CONTENTION
READIWRITE CONTROL(4)
Left or Right Port(l)
RIW
CE
OE
00-7
X
H
X
Z
Port Disabled and in PowerDown Mode, IS82 or IS84
X
H
X
Z
CER CEl VIH, Power-Down
Mode IS81 or IS83
L
L
X
H
L
L
H
L
H
Function
=
DATAIN
=
Data on Port Written Into Memo10
2
DATAoUT Data in Memory Output on Port(3)
Z
High Impedance Outputs
NOTES:
2654 tbl12
1. Aol - A10l ¢ AoR - Al0R.
2. If BUSY L, data is not written.
3. If BUSY =L, data may not be valid, see twoo and tODD timing.
4. 'H' VIH, 'L' VIL, 'X' DON'T CARE, 'Z' HIGH IMPEDANCE
=
=
=
=
=
TABLE II. INTERRUPT FLAG(1,4)
Left Port
Right Port
RIWl
CEL
OEl
A10l- AOl
INTl
RIWA
CEA
OEA
A10l- AOA
L
L
3FF
X
INTA
L(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
3FF
H(3)
L(3)
L
L
3FE
L
L
3FE
H(2)
X
X
X
X
X
X
NOTES:
1.
2.
3.
4.
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTl Flag
Reset Left INTl Flag
2654 tbl13
=
=
Assumes BUSYL BUSYR VIH
If BUSYL = VIL, then No Change.
If BUSYR =VIL, then No Change.
'H' = HIGH,' L' = LOW,' X' = DON'T CARE
TABLE 111- ADDRESS BUSY ARBITRATION
Inputs
Outputs
CEL
CEA
AOl-A10l
AOA-A10A
BUSYl(1)
BUSYA(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibitl;j
Function
2654 tbl14
NOTE:
1. Pins BUSYL and BUSYR are both outputs for IDT71 V321 (master). BUSYx outputs on the IDT71 V321 are open drain, not push-pull outputs.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR =Low will result. BUSYL and BUSYR outputs can not be low
simultaneously.
6.26
12
IDT71V321 S/L
CMOS DUAL-PORT RAM 16K (2K x a-BIT) WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT71 V321 provides two ports with separate control,
address and 1/0 pins that permit independent access for
reads or writes to any location in memory. The IDT71 V321
has an automatic power down feature controlled by CEo The
CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (lNTL) is asserted when the
right port writes to memory location 7FE (H EX) where a write
is defined as the CE =RtW =VIL per the Truth Table. The left
port clears the interrupt by access address location 7FE
access when CER = OER =VIL.
is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FF (HEX) and to clear the
interrupt flag (INTR), the right port must access the memory
location 7FF. The message (8 bits) at 7FE or 7FF is userdefined, since it is an addressable SRAM location. If the
Rm
interrupt function is not used, address locations 7FE and 7FF
are not used as mail boxes, but as part of the random access
memory .. Refer to Table I for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location atthe same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is "Busy". The Busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
~ide that receives a busy indication, the write signal is gated
Internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation.
The Busy outputs on the IDT71 V321 RAM are open drain
type outputs and require open drain resistors to operate. If
these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.
ORDERING INFORMATION
lOT
XXXX
_A_~
Device Type Power Speed
A
A
Package
Processl
Temperature
Range
yBLANK
J
~----------~PF
I~~ }
. . . --------------11
SL
!....----------------1!71V321
Commercial (O°C to +70°C)
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
Speed in nanoseconds
Low Power
Standard Power
16K (2K x 8-Bit) MASTER Dual-Port RAM
wI Interrupt
3026drw 17
6.26
13
G
PRELIMINARY
IDT70V05SIL
HIGH-SPEED 3.3V
8K X 8 DUAL-PORT
STATIC RAM
Integrated Device Te,hnology, In"
FEATURES:
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001 V
electrostatic discharge
• Battery backup operation-2V data retention
• TTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA and PLCC, and a 64-pin TQFP
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Commercial: 25/35/55ns (max.)
• Low-power operation
- IDT70V05S
Active: 350mW (typ.)
Standby: 3.5mW (typ.)
- IDT70V05L
Active: 350mW (typ.)
Standby: 1mW (typ.)
• IDT70V05 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S =H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Interrupt Flag
DESCRIPTION:
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static
RAM. The IDT70V05 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 16-bit-or-more word systems. Using the
lOT MASTER/SLAVE Dual-Port RAM approach in 16-bit or
wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
FUNCTIONAL BLOCK DIAGRAM
- ,
I'-L,.
'--
---./
1
t
]
I/O
Control
1.2)
A12L
AOL
··
NOTES:
1. (MASTER):
SUSYis out put;
(SLAVE): USY
is input.
2. BUSY outpu ts
and INT out puts
are non-tristated push -pull.
-s-
~
4
1
I/OOL- 1/07L
V'
Address
Decoder
"-'I
I
~
"
+
'If
"
MEMORY
ARRAY
V
I/OOR-I/07R
~
A
I/O
Control
•
13/
BUSYR (1,2)
.A
"-
'I
v13~
/
CEL:
OEL:
R1WL.
.
2)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
tills I
Address
Decoder
·•
A12R
AOR
I
-:CER
:OER
:R/WR
t
The lOT logo Is a registered trademark of Integrated Device Technology. Inc.
APRIL 1995
COMMERCIAL TEMPERATURE RANGES
C1995 Integrated Device Technology. Inc.
6.27
DSC-128412
1
IDT70V05SIL
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
This device provides two independent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOS high-performance technology, these devices typically operate on only 350mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500~W from a 2V
battery.
The IOT70V05 is packaged in a ceramic 68-pin PGA and
PLCC and a 64-pin thin plastic quad flatpack (TOFP).
PIN CONFIGURATIONS
<5~ 8~ u IIIII!!:~I~
. .: IIII u u 0 ~N ~~ 0~ ~ ~ ~ ~
INDEX :::::::: zOo: ~ C,) z z g ..7i: ..7i:..7i: ~ ~
~
~~9~~~~~~~~~~~~
<
1/02
1/03
1/04
1/05
GN
1/06
1/07
Vc
GND
A5L
A4L
IDT70V05
J68-1
F68-1
PLCC I FLATPACK(1)
TOP VIEW
A3L
A2L
A1L
AOL
INTL
BUSYL
GND
MIS
BUSYA
INTA
AOA
A1A
A2A
A3A
A4A
70V05
PN-64
TOFP(1)
TOP VIEW
1/00
1/01
1/02
1/04
1105
A4l
A3l
A2l
All
AOl
INTL
BUSYl
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
NOTE:
1. This text does not indicate the actual part-marking
6.27
2
IDT70V05SIL
HIGH-SPEED BK x B DUAL-PORT STATIC RAM
51
11
A5l
COMMERCIAL TEMPERATURE RANGES
50
A4l
48
A2l
46
44
42
AOl BUSYl MIS
40
38
INTR A1R
36
A3R
49
A3l
47
A1l
37
45
43
41
39
INTL GND BUS'fA AOR A2R
35
A4R
34
A5R
53
A7l
52
10
55
A9l
54
09
ASl
32
A7R
33
A6R
08
57
56
A11l A10l
30
A9R
31
ASR
59
07
A6l
61
06
28
29
A11R A10R
58
Vee
IDT70V05
G68-1
A12l
60
N/C
N/C
68-PIN PGA
TOP VIEW (3)
63
62
05 SEMl
CEL
26
GND
27
A12R
24
25
N/C
N/C
04
65
64
OEl RtWl
22
23
SEMR CER
03
67
66
1I00l N/C
20
OER
02
1
3
68
1I01l 1I02l 1I04l
7
5
9
13
15
11
GND 1I07l GND 1I01R Vee 1I04R
18
19
1I07R
N/C
2
4
1I03l 1I05l
10
14
16
6
8
12
1I06l Vee 1I00R 1I02R 1I03R 1I05R
17
1I06R
•
/\
B
C
D
E
F
G
H
J
K
21
RtWR
L
INDEX
2941 drw 04
PIN NAMES
Left Port
Right Port
CEl
CER
Names
Chip Enable
[WVl
RIWR
ReadlWrite Enable
OEl
OER
Output Enable
AOl-A12l
AOR - A12R
Address
1I00l-1I07L
1I00R-1I07R
Data Input/Output
SEMl
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
2941 tbl 01
NOTES:
1. All Vee pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate oriention of the actual part-marking
6.27
3
IDT70V05S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(l)
Outputs
CE
RfW
OE
SEM
1/00-7
H
X
H
High-Z
Deselected: Power Down
Write to Memory
Mode
L
L
X
X
H
DATAIN
L
H
L
H
DATAoUT
X
X
H
X
High-Z
Read Memory
Outputs Disabled
NOTE:
1. AOL-A12L;o!AoR-A12R
2941 tbl 02
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
CE
RfW
OE
SEM
1/00-7
H
H
L
L
DATAoUT
Read Data in Semaphore Flag
X
X
L
DATAIN
Write DINO into Semaphore Flag
H
L
f
X
L
Mode
-
Not Allowed
2941 tbl 03
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
Operating
Temperature
oto +70
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
DC Output
Current
Ambient
Temperature
GND
Vee
Commercial
O°C to +70°C
OV
3.3V± 0.3V
2941 tbl 05
TA
lOUT
Grade
Commercial Unit
RECOMMENDED DC OPERATING
CONDITIONS
Min.
Typ.
Vee
Supply Voltage
3.0
3.3
3.6
V
GND
Supply Voltage
0
0
0
V
Vcc+0.3
V
0.8
V
Symbol
50
mA
NOTES:
2941 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + O.3V.
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
2.0
-0.3(1)
-
Max. Unit
NOTES:
1. VIl2 -1.5V for pulse width less than 10ns.
2941 tbl 06
CAPACITANCE (TA =+25°C, f =1.0MHz)
Symbol
Parameter 1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN= OV
11
pF
COUT
Output
Capacitance
VOUT= OV
11
pF
NOTE:
2941 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
6.27
4
IDT70V05S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc= 3.3V ±O.3V)
IDT70V05S
Symbol
Parameter
Test Conditions
Min.
IDT70V05L
Max.
Min.
Max.
Unit
IILII
Input Leakage Current(5)
Vee = 3.6V, VIN = OV to Vee
-
10
-
5
IlA
IILOI
Output Leakage Current
CE = VIH, VOUT = OV to Vee
-
10
-
5
IlA
VOL
Output Low Voltage
IOL = 4mA
-
0.4
-
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
-
V
2941 tbl08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc = 3.3V ± O.3V)
70V05X25
70V05X35
70V05X55
Test
Symbol
lee
Parameter
Dynamic Operating
Current
(Both Ports Active)
ISB1
Typ.(2) Max. Typ.(2) Max. Typ.<2) Max. Unit
Version
Condition
CE = VIL, Outputs Open
SEM=VIH
f = fMAX(3)
COM'L
S
L
80
80
140
120-::.
41;~
70
70
115
100
70
70
115
100
rnA
10
8
25
20
10
8
25
20
rnA
rnA
q::-~:::;:::
Standby Current
(Both Ports - TIL
Level Inputs)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L.
Standby Current
CEL or CER = VIH
COM'L.
(One Port-TIL
Active Port Outputs Open
Level Inputs)
f = fMAX(3)
S
L
12 J l~'~
'10 :'20
,,itl
$~',,::->:9'
ISB2
S
4~6
82
35
72
35
72
L
40
72
35
62
35
62
S
L
1.0
0.2
1.0
0.2
5
2.5
1.0
0.2
5
2.5
rnA
45
45
71
61
45
45
71
61
rnA
SEMR = SEML = VIH
ISB3
Full Standby Current
(Both Ports - All
Both Ports CEL and
CER ~ Vee - 0.2V
CMOS Level Inputs)
VIN ~ Vee - 0.2V or
VIN ::; 0.2V, f = 0(4)
SEMR = SEML ~ Vee - 0.2V
Full Standby Current
(One Port-All
One Port CEL or
CER ~ Vee - 0.2V
CMOS Level,lnputs)
SEMR = SEML ~ Vee - 0.2V
COM'L.
J
r~
..;:...
~;:;;~
ISB4
COM'L.
S
L
?R~
:[;50
81
71
VIN ~ Vee - 0.2V or VIN ::; 0.2V
Active Port Outputs Open
f = fMAX(3)
NOTES:
2941 tbl09
1. X in part numbers indicates power rating (8 or L)
2. VCC = 3.3V, TA +2SoC.
3. At f fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions'
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. At Vcc$.2.0V input leakages are undefined.
=
=
6.27
5
IDT70VOSSIL
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
DATAoUT
BUSY---~
INT
DATAoUT--.._--+--
30pF
43S!l
SpF
43S!l
See Figures 1 & 2
Output Load
29411bll0
2941 drw06
Figure 1. AC Output Test Load
Figure 2. Output Load
(For tLZ, tHZ, twz, tow)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V05X25
Symbol
Parameter
Min.
Max.
IDT70V05X35
Min.
Max.
IDT70V05X55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
tAA
Address Access Time
25
tACE
Chip Enable Access Time(3)
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(t, 2)
tHZ
Output High-Z Time(t, 2)
tpu
3
3
-
55
-
ns
-
55
55
30
ns
-
35
35
20
-
3
3
-
ns
-
3
3
-
25
ns
-
ns
50
ns
ns
/,25
';:1"15
i:t 'it
35
-
15
-
20
Chip Enable to Power Up Time(2)
- A!;!i
o il;C'
-
0
-
0
tPD
Chip Disable to Power Down Time(2)
-
25
-
35
-
tsop
Semaphore Flac Update Pulse (aE or SEM)
15
-
15
-
15
-
tSAA
Semaphore Address Access Time
-
35
-
45
-
65
NOTES:
1. Transition is measured ±200mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is~aranteed but not tested.
3. To access RAM, CE L, 8EM H.
4. X in part numbers indicates power rating (8 or L).
=
ns
ns
ns
ns
29411blll
=
TIMING OF POWER-UP POWER-DOWN
2941 drw 08
6.27
6
IDT70V05SIL
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
\V
ADDR
\I
J\.
Ir-..
tAA (4)
\ \ \ \1.- tACE (4)
J'III
I
14--- tAOE (4)
/111
\\\:
I
Rm
I
I
I . - - tLZ (1)
DATAoUT
I
--tX'
1\
~tOH
VALID DATA (4)
J\.
tHZ(2)
--1
~~
I
I
\\\\\\\~
BUSYOUT
__ tBDD (3, 4)
2941 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBoodelay is required only in cases where the opposite port is completing a write operation to the same address location. Forsimultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tM or tBOO.
5. SEM = H.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT70V05X25
Symbol
Parameter
Max.
Min.
IDT70V05X35
Min.
Max.
IDT70V05X55
Min.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
25
-
35
tEW
Chip Enable to End-of-Write(3)
20
-
30
-
45
tAW
Address Valid to End-of-Write
20
-
30
-
tAS
Address Set-up Time(3)
0
-
0
twp
Write Pulse Width
tWR
Write Recovery Time
0
tow
Data Valid to End-of-Write
15
tHZ
Output High-Z Time\l,~)
tOH
Data Hold Time(4)
twz
Write Enable to Output in High-Z(1, 2)
_
tow
Output Active from End-of-Write(l, 2, 4)
0
tSWRO
SEM Flag Write to Read Time
tsps
SEM Flag Contention Window
,');:'"
20
(:':"'?"
ns
45
-
-
0
-
ns
25
-
40
ns
0
0
-
30
-
ns5
55
ns
ns
-
20
-
- i:;;
15
-
20
-
25
ns
o,,:!;:'
-
-
0
-
ns
20
-
25
ns
ns
ns
.:;;/,;'i'
...•,'
15
0
0
-
0
5
-
5
5
-
5
-
5
-
5
-
ns
ns
NOTES:
2941 tbl12
1. Transition is measured ±200mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE L, SEM H. To access semaphore, CE Hand SEM L. Either condition must be valid for the entire tEW time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. X in part numbers indicates power rating (8 or L).
=
=
=
=
6.27
7
IDT70V05S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,3,5,8)
twc
~~
/r+..
ADDRESS
~~
Jf\
tHZ
(7)
,f
tAW
CEor SEM
I
(9)
J
tWp(2)
f4--tAS (6\
tWR(3)
~ ...
t-
r+..
~twz
(7)
tow
V
(4)
DATAoUT
~
~
\
J
------,lE
_ _lt----tow
DATAIN
(4)
.'11
tOH
2941 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,3,5,8)
twc
~~
ADDRESS
~~
Jf\
/f\
tAW
CEorSEM
(9)
f+-IAS(6)
J
""~
J
tWR(3) I+-
tEW(2)
\\\
DATAN
.1.
---------{E'---___J--(
)(
MATCH
twp
~
RfjJ'A'
/1,{'
K
tDW
)(
DATAIN'A'
tDH
)K
VALID
tAPS (1)
ADDR'B'
) (""
\
BUSY'B'
DATAOUT'B'
MATCH
f--
"--""
tBDA-
;;
-
twDD
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for-MIS = VIL (SLAVE).
2. CEL CER VIL
3. OE =ViL for the reading port.
4. If MIS = VIL(slave) then BUSY is input (BUSY'A' = VIH and BUSY's' = "don't care", for this example.
5. All timing is the same for left and right port. Port "A' may be either left or right port. Port "8" is the port opposite from Port "A".
=
tBDD
~
)E
2942 drw 12
=
6,28
10
IDT70V06S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SLAVE WRITE (MIS
=L)
~--- t w p - - - + !
RiW'A'
twri')
RiW's'
~
lw--
(2)
~
2942drw13
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1} (MIS
X
ADDR"A"
and "B"
=H)
X
ADDRESSES MATCH
CE"A"
tAps (2)
CE"B"
tBAC~
tBDC}
BUSY"B"
2942 drw 14
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDR"A")(
)K.
ADDRESS "N"
~----------------------------
tAPS (2)
ADDR"B"
_ _ _ _ _ _J
)K
MATCHING ADDRESS "N"
~tBAA~
~tBDA}
BUSY"B"
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
2942 drw 15
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1}
Symbol
INTERRUPT TIMING
IDT70V06X25
Min. Max.
Parameter
IDT70V06X35
Min. Max.
IDT70V06X55
Min
Max.
Unit
tAS
Address Set-up Time
0
-
0
-
-
0
0
ns
Write Recovery Time
0
0
-
tWR
-
ns
tiNS
Interrupt Set Time
25
-
30
-
40
ns
tlNR
Interrupt Reset Time
-
30
-
35
-
45
NOTE:
1. "x" in part numbers indicates power rating (S or L).
ns
2942 tbl14
6.28
11
IDT70V06S1L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~----------------------
twc .....------------------~
ADDR"A"
CE"A'
RiW"A"
INT"B'
2942 drw 16
~---------------------- tRC .....------------------~
INTERRUPT CLEAR ADDRESS
ADDR"B"
(2)
OE"B"
INT"B"
2942 drw 17
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal Is asserted last.
4. Timing depends on which enable signal is de-asserted first.
TRUTH TABLES
TRUTH TABLE I -INTERRUPT FLAG(1)
Right Port
Left Port
OEL AOL-A13L INTL
RlWL
CEL
RlWR
CER
L
L
X
3FFF
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L(3)
L
L
X
L
L
3FFE
H(;!)
X
X
OER AOR-A13R INTR
L(2)
L
3FFF
H(3)
X
X
3FFE
X
Set Left INTL Flag
X
X
Reset Left INTL Flag
NOTES:
1. Assumes BUSYL BUSYR H.
2. If BUSYL L, then no change.
3. If BUSYR L, then no change.
=
=
=
Function
X
X
Set Right INTR Flag
Reset Right INTR Flag
2942 tbl15
=
6.28
12
IDT70V06SJL
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
TRUTH TABLE II ARBITRATION
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
ADDRESS BUSY
Inputs
Outputs
CEl
CER
AOl-A13l
AOR-A13R
X
X
NO MATCH
H
H
Normal
Normal
BUSYl(1) BUSYR(1)
Function
H
X
MATCH
H
H
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
NOTES:
2942tbl16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDT70V06 are push pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If lAps is not met, either BUSYL or BUSYR Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
=
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(l)
Functions
Do - 07 Left
Status
Do - 07 Right
Semaphore free
No Action
1
1
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V06.
2942 tbl17
FUNCTIONAL DESCRIPTION
The IDT70V06 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V06 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is set when the right port
writes to memory location 3FFE (HEX). The left port clears the
interrupt by reading address location 3FFE. Likewise, the right
port interrupt flag (INTR) is set when the left port writes to
memory location 3FFF (HEX) and to clear the interrupt flag
(INTR), the right port must read the memory location 3FFF.
The message (8 bits) at 3FFE or 3FFF is user-defined. If the
interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random
access memory. Refer to Table I for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
6.28
13
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V06S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
~
T
I
MASTER
Dual Port
SLAVE
Dual Port
CE
BAM...
BAM...
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
1
MASTER
Dual Port
I
I
II:
0
C,)
w
Cl
"--
1
SLAVE
Dual Port
CE
CE
BAM...
BAM...
BUSY (L)
CE
- 0w
BUSY (L) BUSY(R)
BUSY (L) BUSY (R)
1
BUSY (R)
I
2942 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V06 RAMs.
SEMAPHORES
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the Mis pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 70V06 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V06 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V06 RAM the busy pin
is an output if the part is used as a master (MiS pin = H), and
the busy pin is an input if the part used as a slave (M/S pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with the RiW signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
data in the slave.
The IDT70V06 is an extremely fast Dual-Port 16K x 8
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT70V06 contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V06's hardware semaphores,
which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT70V06 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
6.28
14
IDT70V06SJL
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be a
major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT70V06 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RIW) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO-A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one; a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
proces~or which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
6.28
15
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V06S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers forthe IDT70V06's Dual-Port
RAM. Say the 16K x B RAM was to be divided into two BK x
B blocks which were to be dedicated at anyone time to
serv.icing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory.
To take a resource, in this example the lower BK of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower BK. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
O. At this point, the software could choose to try and gain
control of the second BKsection bywriting, then reading azero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap BK blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structu re,
thereby guaranteeing a consistent data structure.
RPORT
LPORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do-- -1 D a w a Dt Do
WRITE--.lL.._ _.
.L....-_--I
SEMAPHORE.
READ
WRITE
SEMAPHORE
READ
2942 drw 19
Figure 4. IDT70V06 Semaphore Logic
6.28
16
IDT70V06SJL
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process!
Temperature
Range
Y
Blank
IPF
'---------~IJG
'----------------1
1
~~}
IS
' - - - - - - - - - - - - - - - - - - - 11 L
'--_________________-1: 70V06
Commercial (O°C to +70°C)
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-i)
Speed in Nanoseconds
Standard Power
Low Power
128K (16K x 8) 3.3V Dual-Port RAM
2942 drw20
6.28
17
t;J
PRELIMINARY
IDT70V07S/L
HIGH-SPEED 3.3V
32K X 8 DUAL-PORT
STATIC RAM
Integrated Device Technology,lnc.
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Commercial: 25/35/55ns (max.)
• Low-power operation
- IDT70V07S
Active: 450mW (typ.)
Standby: 5mW (typ.)
- IDT70V07L
Active: 450mW (typ.)
Standby: 5mW (typ.)
• IDT70V07 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• Mis = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Interrupt Flag
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001 V
electrostatic discharge
• TTL-compatible, single 3.3V (to.3V) power supply
• Available in 6a-pin PGA and PLCC, and a 64-pin TQFP
DESCRIPTION:
The IDT70V07 is a high-speed 32K x a Dual-Port Static
RAM. The IDT70V07 is designed to be used as a stand-alone
256K-bit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 16-bit-or-more word systems.
Using the lOT MASTER/SLAVE Dual-Port RAM approach in
16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional
discrete logic.
FUNCTIONAL BLOCK DIAGRAM
r\.
"
1I
1
]
1/0
Control
(1 ,2)
+
BUSYl
A14l
AOl
··
Address
Decoder
I
"
.A
v
'I
f.-
~
.A
"
)
I/OOR-I/07R
1/0
Control
~r •
MEMORY
ARRAY
15
CEl:
OEl
RiWl
I
1
~
4
1
I/OOL-I/07 l
1
-r
j
_ _ (1,2)
BUSYR
"
.A
--v
""
15.-
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
··
A14R
AOR
-,
~CER
-:O~
IRIWR
ttlJsltt
2943 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGES
«:11995 Integrated Device Technology. Inc.
APRIL 1995
6.29
DSC-108412
1
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
This device provides two independent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 450mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA and
PLCC and a 80-pin thin plastic quad flatpack (TQFP).
PIN" CONFIGURATIONS
8
7
I/04L
I/OSL
GND
I/06L
I/07L
Vec
GND
I/OOR
I/01R
I/02R
Vee
I/03R
I/04R
I/OSR
I/06R
N/C
I/02L
I/03L
I/04L
I/OSL
GND
I/OSL
I/07L
VCC
N/C
GND
I/OOR
I/01R
I/02R
Vce
I/03R
I/04R
I/OSR
I/OSR
6
S
4
3
2
1
IDT70V07
J68-1
PLCC
TOP VIEW(1)
ASL
A4L
A3L
A2L
A1L
AOL
INTL
BUSYL
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
N/C
ASL
A4L
A3L
A2L
A1L
AOL
INTL
BUSYL
GND
7007
PN80-1
TQFP
TOP VIEW(1)
Mis
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
N/C
N/C
N/C
NOTE:
1. This text does not indicate orientation of the actual part-marking.
6.29
2
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
51
11
A5L
COMMERCIAL TEMPERATURE RANGES
50
A4L
48
A2L
42
44
46
AOL BUSYL Mis
40
38
INTR A1R
36
A3R
49
A3L
47
A1L
43
41
45
39
37
INn. GND BUSYF AOR A2R
35
A4R
34
A5R
53
A7L
52
10
55
A9L
54
09
ABL
32
A7R
33
A6R
08
57
56
A11L A10L
30
A9R
31
ABR
28
A11R
29
A10R
26
GND
27
A12R
59
07
vee
61
06
A6L
58
IDT70V07
G68-1
A12L
60
A14L
68-PIN PG.A!3)
A13L
TOP VIEW
24
25
A14R A13R
05
62
63
SEML CEL
04
64
65
OEL RIWt..
SEMR
23
CER
03
67
66
I/OOL
N/C
20
OER
21
RlWR
02
1
3
68
I/01L I/02L I/04L
19
N/C
•
/A
22
4
2
6
I/03L I/05L
B
7
9
5
GND I/07L GND
8
I/06L
vee
D
E
C
11
15
18
I/04R
I/07R
12
10
14
16
I/OOR I/02R I/03R I/05R
I/06R
F
13
I/01R
G
vee
H
17
K
L
INDEX
2943 drw 04
PIN NAMES (1,2)
Left Port
Right Port
GEL
CER
Names
Chip Enable
RlWL
RIWR
ReadlWrite Enable
OEL
OER
Output Enable
AOL-A14L
AOR - A14R
Address
I/OOL-II07L
I/OOR - I/07R
Data Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
2943 Ibl 01
NOTES:
1. All Vec pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.29
3
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
CE
RIW
X
Outputs
Mode
OE
SEM
1/00-7
H
High-Z
Deselected: Power-Down
Write to Memory
L
L
X
X
H
DATAIN
L
H
L
H
DATAoUT
X
X
H
X
High-Z
H
Read Memory
Outputs Disabled
NOTE:
1. AOL -
2943 tbl 02
A14L .. AOR -
A14R
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
CE
RIW
OE
SEM
1100-7
H
H
L
L
DATAoUT
Read Data in Semaphore Flag
H
f
DATAIN
Write 1/00 into Semaphore Flag
X
X
X
L
L
L
Mode
-
Not Allowed
2943 tbl 03
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
to GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1)
-0.5 to +4.6
V
Operating
Temperature
o to +70
°C
TSIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
DC Output
Current
Ambient
Temperature
GND
Vee
Commercial
O°C to +70°C
OV
3.3V± 0.3V
2943 tbl 05
TA
lOUT
Grade
Commercial Unit
50
RECOMMENDED DC OPERATING
CONDITIONS (2)
Symbol
rnA
NOTES:
2943 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time
or 1Ons maximum, and is limited to !> 20mA forthe period of VTERM ~ Vcc
+0.3V.
Parameter
Min.
Typ.
Vee
Supply Voltage
3.0
3.3
3.6
V
GND
Supply Voltage
0
a
a
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.0
-0.3(1)
-
Max. Unit
Vcc+0.3 V
0.8
NOTES:
1. VIL~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
V
2943 tbl 06
CAPACITANCE (TA =+25°C, f =1.0MHz)
Symbol
Parameter(1)
Conditions(2)
Max.
Unit
CIN
Input Capacitance
VIN =3dV
9
pF
COUT
Output
Capacitance
VOUT= 3dV
10
pF
NOTE:
2943 tbl 07
1. This parameter is determined by device characterization but is not
production tested. TQFP package only.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to av.
6.29
4
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vce = 3.3V + O.3V)
IVI
IL
Symbol
Parameter
LL IlJ
~
II
Test Conditions
Min.
Max.
Min.
Max.
Unit
5
~A
5
~A
0.4
V
-
V
lIul
Input Leakage Current
Vee = 3.6V, VIN = OV to Vee
-
10
IIlol
Output Leakage Current
CE = VIH, VOUT = OV to Vee
-
10
VOL
Output Low Voltage
IOl= 4mA
-
0.4
-
VOH
Output High Voltage
IOH = -4mA
2.4
-
2.4
2943 Ibl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc= 3.3V ± O.3V)
70V07X25
70V07X35
70V07X55
Test
Symbol
Parameter
Typ.(2)
Version
Condition
Max. Typ.(2)
Max. Typ.(2)
Max. Unit
lee
Dynamic Operating
Current
(Both Ports Active)
CE = Vll, Outputs Open
SEM =VIH
f = fMAX(3)
COM'L.
S
L
100
100
170
140
90
90
140
120
90
90
140
120
mA
18B1
Standby Current
(Both Ports - TTL
Level Inputs)
CER = CEl = VIH
SEMR = SEMl = VIH
f = fMAX(3)
COM'L.
S
L
14
12
30
24
12
10
30
24
12
10
30
24
mA
18B2
Standby Current
CE'A' = Vil and CE"B' = VIH(5)
COM'L.
S
50
95
45
87
45
87
mA
(One Port -
Active Port Outputs Open,
L
50
85
45
75
45
75
COM'L.
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
mA
COM'L.
S
L
60
60
90
80
55
55
85
74
55
55
85
74
mA
TTL
Level Inputs)
f = fMAX(3)
SEMR = SEMl = VIH
18B3
18B4
Full Standby Current
(Both Ports - All
Both Ports CEL and
CER ~ Vee - 0.2V
CMOS Level Inputs)
VIN > Vee - 0.2V or
VIN 0.2V, f = 0(4)
SEMR = SEMl ~ Vee - 0.2V
Full Standby Current
(One Port-All
CE'A' $. 0.2V and
CE"B" ~ Vee - 0.2V(5)
CMOS Level Inputs)
SEMR = SEMl ~ Vee - 0.2V
5
VIN ~ Vee - 0.2V or VIN $. 0.2V
Active Port Outputs Open
f = fMAX(3)
NOTES:
2943 Ibl 09
1. "X" in part numbers indicates power rating (8 or L)
o
2. Vee 3.3V, TA +2S C, and are not production tested. leeDe =BOmA (Typ.)
3. At f =fMAX, address and control lines (except Output Enable)"are cycling at the maximum frequency read cycle of 1/tRe. and using "AC Test Conditions'
of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
=
=
=
6.29
5
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
t893!l
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
DATAouT
BUSY
5ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
INT
See Figures 1 & 2
Output Load
~
3470
DATAOUT·--......--+-_
30pF
3470
5pF
2943 dlW 05
2943 tbl to
2943 dlW 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
• Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V07X25
Symbol
Parameter
Min.
Max.
IDT70V07X35
IDT70V07X55
Min.
Min.
Max.
Max.
Unit
ns
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
55
-
tAA
Address Access Time
25
-
55
ns
Chip Enable Access Time(3)
35
-
55
ns
tAOE
Output Enable Access Time
-
15
-
35
tACE
-
20
-
30
ns
tOH
Output Hold from Address Change
3
3
-
3
-
ns
tLZ
Output Low-Z Time(l, 2)
3
-
3
-
3
tHZ
Output High-Z Time(l, 2)
-
15
-
20
tpu
Chip Enable to Power Up Time(2)
-
0
-
tPD
Chip Disable to Power Down Time(2)
-
25
-
35
tsop
Semaphore Flag Update Pulse (bE or SEM)
15
-
15
tSAA
Semaphore Address Access Time
-
35
-
25
0
NOTES:
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL and 8EM VIH. To access semaphore, CE VIH and 8EM VIL.
4. "X" in part numbers indicates power rating (8 or L).
=
=
=
-
ns
25
ns
-
ns
-
50
ns
-
15
-
ns
45
-
65
ns
0
2943 tblll
=
TIMING OF POWER-UP POWER-DOWN
2943 drw 08
6.29
6
IDT70V07SIL
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
~--------------------- tRC ------------------------~
ADDR
RiW
I
I
I
I
:---tLZ(1)
DATAOUT---------------I--------------~
VALID DATA4)
tBOO(3,4)
2943 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CEo
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBOO delay is required only in cases where the opposite port is completing a write operation tothe same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tM or tBOO.
5. SEM =VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
Symbol
Parameter
IDT70V07X25
IDT70V07X35
IDT70V07X55
Min.
Max.
Min.
Min.
Max.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
25
-
35
-
55
-
ns
tEW
Chip Enable to End-of-Write(3)
20
30
-
45
Address Valid to End-of-Write
20
30
45
tAS
Address Set-up Time(3)
0
-
0
0
-
ns
twp
Write Pulse Width
20
-
25
40
Write Recovery Time
0
-
0
tow
Data Valid to End-of-Write
15
-
20
-
30
-
ns
tWR
-
-
ns
tAW
-
tHZ
Output High-Z Time(1, 2)
-
15
-
20
-
25
ns
tOH
Data Hold Time(4)
0
-
0
-
0
-
ns
twz
Write Enable to Output in High-Z(1, 2)
-
15
-
20
-
25
ns
-
ns
0
tow
Output Active from End-of-Write(1, 2, 4)
0
-
0
-
0
tSWRD
SEM Flag Write to Read Time
5
5
SEM Flag Contention Window
5
-
5
tsps
-
NOTES:
5
5
ns
ns
ns
ns
ns
2943 tbl12
1.
2.
3.
4.
Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
This parameter is~aranteed by device characterization, but is not production tested.
To access RAM, CE =VIL and SEM =VIH. To access semaphore, CE =VIH and SEM =VIL. Either condition must be valid for the entire tEW time.
The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
6.29
7
IDT70V07S/L
HIGH·SPEED 32K x 8 DUAL·PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,5,8)
twe
~~
~f-
ADDRESS
J\
J\
i
tAW
tHZ(l~
I
CE or SEM (9)
J
twp(2)
~tAS(61
tWR(3)
~t-
Rm
-¥
J
1\
~ tw:~ri
DATAoUT
tow~
(4)
(4)
,
~
.'.
DATAIN------------------------------~~~---------------~~~-------------------
J1
J
tow
tOH
2943 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,5)
twe
~~
Jr-..
ADDR ESS
~~
Jr-..
tAW
9
CEor SEM )
~ tA~6)
J
I
j'tWR(3) i+-
tEW(2)
\\\
Rm
DATAIN-------I~----~-]-----III •
tow
tOH
2943 drw 10
NOTES:
1. RJW or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a LOW CE and a LOW RJW for memory array writing cycle.
3. tWR is measured from the earlier of CE or Rm (or SEM or RiW) going HIGH to the end of write cycle.
4. During this period, the 1/0 pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the RiW LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE or RJW.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during RJW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tow. If OE is HIGH during an RJW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. To access RAM, CE VIL and SEM VIH. To access semaphore, CE VIH and SEM VIL tEW must be met for either condition.
=
=
=
6.29
=
8
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao-A2
VALID ADDRESS
DATAo----~----~~
ANi ------t----"""
---~-+i tADE
.....---Write Cycle
---~I-----Read Cycle---t~
2943 drw 11
NOTE:
1. CE VIH for the duration of the above timing (both write and read cycle).
=
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
X. . _______
AO"A"-A2"A"_ _ _M_AT_C_H_ _ _ _
SIDE(2) "A"
SEM"A"
-------'
AO"B"-A2"B"
SIDE(2) "8"
NOTES:
1. DOR =DOL Vll, CER CEl VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "8" is the opposite from port "A".
3. This parameter is measured from pjijii-A' or SEM'A' going HIGH to RlWB or SEM'B' going HIGH.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
=
6,29
9
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Parameter
Symbol
IDT70V07X25
IDT70V07X35
IDT70V07X55
Min.
Min.
Min.
Max.
Max.
Max.
Unit
ns
-
45
45
45
45
BUSY TIMING (MIS = VIH)
-
25
25
25
25
-
35
35
35
35
Arbitration Priority Set-up Timel~)
5
-
5
-
5
-
ns
BUSY Disable to Valid Datal;j)
-
25
-
35
-
55
ns
0
20
-
0
25
-
0
25
-
ns
-
ns
-
55
50
-
65
60
-
85
ns
-
80
ns
tBAA
BUSY Access Time from Address Match
tBOA
BUSY Disable Time from Address Not Matched
tBAC
BUSY Access Time from Chip Enable LOW
tBOC
BUSY Disable Time from Chip Enable HIGH
tAPS
tBOO
-
-
ns
ns
ns
BUSY TIMING (MIS = VIL)
tWB
BUSY Input to Write (4 )
tWH
Write Hold After BUSy(5)
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delaytl)
tODD
Write Data Valid to Read Data Delay(1)
NOTES:
2943 tbl13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD - twp (actual) or tDDD - tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (8 or L).
6.29
10
IDT70V07S/L
HIGH-SPEED 32Kx 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,5)
twc
ADDR'A'
)
K
)
MATCH
twp
~
RiW"A'
K
.7
<
tt'
tow
)
DATAIN'A'
K
tOH
)<:
VALID
tAPS (1)
) K~
ADDR"B'
BUSY"B'
MATCH
\.
~
'r--""
tBoO
tBOA
.7V
twoo
)
DATAoUT"B'
tODD (3)
E
2943 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for MIS =Vil (SLAVE).
2. CEl CER Vil
3. OE = Vil for the reading port.
4. If MIS = Vil (SLAVE), then BUSY is an input (BUSY'A' VIH and BUSY'B' "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
=
=
=
=
TIMING WAVEFORM OF WRITE WITH BUSY
twp
BUSY"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking RMi"B", until BUSY"B" goes High.
6.29
11
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CETIMING(1)
ADDR'A"=><
and "B'
><=
ADDRESSES MATCH
-----------------------------------------------
CE'A'
tBAC1_tBD:}
BUSY"B'
2943 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING(1)
ADDRESS "N"
MATCHING ADDRESS "N"
2943 drw 16
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Sj'mbol
Parameter
IDT70V07X25
IDT70V07X35
IDT70V07X55
Min.
Max.
Min.
Max.
Min.
-
0
-
0
25
-
30
-
Max.
Unit
INTERRUPT TIMING
lAS
Address Set-up Time
0
tWR
Write Recovery Time
0
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
-
NOTE:
1. "X" in part numbers indicates power rating (5 or L).
0
30
35
0
-
-
ns
40
45
ns
ns
ns
2942 tbl14
6.29
12
IDT70V07S/L
HIGH-SPEED 32K X 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
~-----------------------------------------------tWG---------------------------------------------~
2
INTERRUPT SET ADDRESS )
ADDR"A"
CE"A"
R/W"A"
INT"s"
2943 drw 17
~----------------------------------------------------tRC-----------------------------------------~
INTERRUPT CLEAR ADDRESS
ADOR"s"
(2)
..----i~ tAS (3)
CE"s"
OE"s"
INT"s"
2943 drw 18
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or RIW) is asserted last.
4. Timing depends on which enable signal (CE or RIW) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I -INTERRUPT FLAG(1)
Right Port
Left Port
RNt/L
GEL
OEL A14l-Aol
L
L
X
7FFF
X
X
X
X
X
X
X
X
X
L
L
7FFE
A14R-AoR INTR
L(2)
X
INTl
RIWR
CER
OER
X
X
X
X
X
X
L
L
7FFF
H(3)
Ll~)
L
L
X
7FFE
H(2)
X
X
X
X
X
X
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2942 tbl15
6.29
13
IDT70V07S/L
HIGH-SPEED 32K X 8 DUAL-PORT STATIC RAM
TRUTH TABLE I ARBITRATION
ADDRESS BUSY
Inputs
CEL
CER
X
H
X
X
X
H
L
L
AOL-A14L
AOR-A14R
NO MATCH
MATCH
MATCH
MATCH
COMMERCIAL TEMPERATURE RANGES
Outputs
BUSYL(1)
BUSYR(1)
H
H
Function
Normal
H
H
Normal
H
H
Normal
(2)
(2)
Write Inhibit(3)
NOTES:
2943tbl16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT7007 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR LOW will result. BUSYL and BUSYR outputs can not be LOW
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
=
TRUTH TABLE 11- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
No Action
Do - 07 Left
Do - 07 Right
Status
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V07.
FUNCTIONAL DESCRIPTION
The IDT70V07 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V07 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (I NTL) is asserted when the right port
writes to memory location 7FFE (HEX), where a write is
defined as CE =Rm =VIL per the Truth Table. The left port
clears the interrupt through access of address location 7FFE
when CER = OER = VIL, Rm is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
writes to memory location 7FFF (HEX) and to clear the
interrupt flag (INTR), the right port must read the memory
2943 tbl17
7FFF location 7FFF. The message (8 bits) at 7FFE or 7FFF
is user-defined since it is an addressable SRAM location. If
the interrupt function is not used, address locations 7FFE and
7FFF are not used as mail boxes, but as part of the random
access memory. Referto Table 1 forthe interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
6.29
14
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 70V07 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V07 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
-
MASTER
Dual Port
BAM..
I
CE
BUSY (L) BUSY (R)
i
SLAVE
Dual Port
BAM..
CE
MASTER
BUSY(L)
CE
w
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
1
SLAVE
Dual Port
BAM..
Cl
0
u
1
Dual Port
BAM..
a:
_w
Cl
-
CE
BUSY(L) BUSY(R)
BUSY(R)
I
2943 drw 19
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70V07 RAMs.
write inhibit signal. Thus on the IDT70V07 RAM the busy pin
is an output if the part is used as a master (MIS pin =H), and
the busy pin is an input if the part used as a slave (MIS pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a masterlslave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with the Rm signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
data in the slave.
SEMAPHORES
The IDT70V07 is an extremely fast Dual-Port 32K x 8
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT70V07 contain mUltiple processors or controllers and are typically very highspeed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V07's hardware semaphores,
which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT70V07 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resou rce. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
6.29
15
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT70V07 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low if'!put on the SEM
pin (which acts as a chip select for the semaphore..!,!ags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
OJ
OJ
WRITE
WRITE
SEMAPHORE~____~~
READ
~~____- .
SEMAPHORE
READ
2943 drw 20
Figure 4. IDT70V07 Semaphore Logic
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
the semaphore flag will force its side of the semaphore flag
low and the other side high. This condition will continue until
a one is written to the same semaphore request latch. Should
the other side's semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers forthe IDT70V07's Dual-Port
RAM. Say the 32K x 8 RAM was to be divided into two 16K
x 8 blocks which were to be dedicated at anyone time to
6.29
16
IDT70V07S/L
HIGH~SPEED 32K
x 8 DUAL-PORT STATIC RAM
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory.
To take a resource, in this example the lower 16K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower
16K. Meanwhile the right processor was attempting to gain
control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore O. At this point, the software could choose to try
and gain control of the second 16K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 16K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
COMMERCIAL TEMPERATURE RANGES
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
6.29
17
IDT70V07S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
ysrank
PF
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-i)
'--------------IG
J
'-----------------1
25
35
55
IS
'------------------1, L
'-----------------------1\
Commercial (ODC to +?ODC)
}
Speed in nanoseconds
Standard Power
Low Power
?OVO? 256K (32K x 8) 3.3V Dual-Port RAM
2943 drw22
6.29
18
G
PRELIMINARY
IDT10V24S/L
HIGH-SPEED 3.3V
4Kx 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• M/S = H for BUSY output flag on Master
Mis = L for BUSY input on Slave
• Interrupt Flag
• Devices are capable of withstanding greater than 2001 V
electrostatic charge.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• TTL-compatible, single 3.3V (±0.3V) power supply
• Available in 84-pin PGA, PLCC and 100-pin TQFP
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Commercial: 25/35/55ns (max.)
• Low-power operation
- IDT70V24S
Active: 230mW (typ.)
Standby: 3.3mW (typ.)
- IDT70V24L
Active: 230mW (typ.)
Standby: .66mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT70V24 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
DESCRIPTION:
The IDT70V24 is a high-speed 4K x 16 Dual-Port Static
RAM. The IDT70V24 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTERISLAVE
Dual-Port RAM for 32-bit-or-more word systems. Using the
FUNCTIONAL BLOCK DIAGRAM
RNJL
UBL
-
J
r-'\
~
ld
~
h
4<~
I/OSL-1/015L
1/0
Control
I/OOL-1/07L
•
1 2)
BUSyt •
··
A11L
AOL
NOTES:
1. (MASTER):
BUSY is outpu t·
(SLAVE): BUSy
is input.
2. BUSY outputs
and INT outputs
are non-tri-stat ed
push-pull.
Address
Decoder
A
"-
~
v
I
RNJR
UBR
r
\.--
"'
~
~
L:
~~
"-
A
~r
I/OOR-1/07R
•
12
BUSy~1,2)
A
"-
~
v
12
,
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
O"§L.
RlWL.
I
\
I/OsR-1/015R
1/0
Control
MEMORY
ARRAY
_.,
CEL •
1
tI
,_ It
MIS
Address
Decoder
··
A11R
AOR
I
:CER
!OER
!RtWR
I
SEMR
INT~2)
2911 drw 01
The lOT logo is a registered trademar\( of Integrated Device Technology. Inc.
COMMERCIAL TEMPERATURE RANGE
C1995 Integrated Device Technology, Inc.
APRIL 1995
6.30
DSC-129212
IDT70V24S1L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
lOT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOSTM high-performance technology, these devices typically operate on only 350mW of
power.
The IDT70V24 is packaged in a ceramic 84-pin PGA, an
84-Pin PLCC and a 1~O-pin Thin Quad Plastic Flatpack.
PIN CONFIGURATIONS
I/OaL
A7L
I/09L
A6L
'010L
ASL
'OllL
A4L
'012L
A3L
A2L
'013L
AIL
GND
IDT70V24
J84·1
F84·2
'014L
'OlSL
Vee
GND
T~~iE~~1)
I/OIR
1/010L
I/0llL
1/012L
1/013L
GND
1/014L
I/OISL
Vee
GND
I/CoR
I/OIR
1/02R
Vee
I/03R
1/04R
I/OSR
I/06R
N/C
N/C
N/C
N/C
INTL
• BUSYL
84·PIN PLCC I
I/OOR
N/C
N/C
N/C
N/C
AOL
GND
(1)
MIS
BUSYR
I/02R
INTR
Vee
AOR
I/03R
AIR
I/04R
A2R
I/OSR
A3R
I/06R
A4R
I/07R
ASR
I/OaR
A6R
II
N/C
N/C
N/C
N/C
ASL
A4L
A3L
A2L
AIL
AOL
INll
BUSYL
GND
IDT7024
PN100·1
100·PIN
To:~tlW(1)
MIS
(1)
BUSYR
INTR
AOR
AIR
A2R
A3R
A4R
N/C
N/C
N/C
N/C
6.30
NOTE:
1. This text does not indicate the actual part-marking.
2
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
63
11
61
I/07l
66
10
64
I/010l
67
09
69
72
75
76
79
81
82
53
CEl
45
A11l
44
N/C
43
52
84
I/08R
40
39
33
IDT7OV24
G84-3
GND
32
84-PIN PGA
TOPVIEW(3)
28
Vee
AOl
31
GND
36
A1l
30
INTR
26
BUSYR
27
A2R
I/04R
7
I/07R
I/09R
INTl
MIS
29
AOR
A2l
34
35
BUSYl
Vee
78
I/02R
A4l
37
A3l
74
GND
ASl
A6l
73
I/014l
A7L
A8l
41
RfiJl
Vee
42
A10l
A9l
I/012l
1
I/06R
01
47
50
UBl
GND
83
I/OSR
02
I/01l
46
uk
80
I/03R
03
49
56
I/03l
48
SEMl
38
77
I/01R
04
59
I/06l
51
OEl
57
70
I/OOR
05
I/OOl
I/09l
71
I/015l
06
62
I/08l
54
55
I/02l
68
I/013l
07
58
I/04l
65
I/011L
08
60
I/05l
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
11
GND
12
GND
2
5
8
I/010R
I/013R
I/01SR
10
3
4
6
9
I/011R I/012R I/014R
OER
23
SEMR
14
RfiJR
15
A5R
17
UBR
13
A1R
25
20
22
A3R
24
A11R
A8R
A6R
rnR
CER
16
N/C
18
A10R
19
A9R
F
G
H
J
K
A4R
21
A7R
Ii
A
B
C
D
E
L
2911 drw 04
Index
PIN NAMES(1.2)
Left Port
Right Port
CEl
Names
CER
Chip Enable
ReadtWrite Enable
RNJl
RtWR
OEl
OER
Output Enable
AOl-A11l
AOR - A11R
Address
I/OOl - I/015l
I/OOR -I/015R
Data Input/Output
SEMl
SEMR
Semaphore Enable
UBl
UBR
Upper Byte Select
LBl
LBR
Lower Byte Select
INTl
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
NOTES:
1. All Vce pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate the actual part-marking.
2911 tbl1
6.30
3
IDT70V24S1L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
Outputs
CE
ANI
OE
us
LB
SEM
UOS-15
UO~7
H
X
X
X
X
H
High-Z
High-Z
X
X
X
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAoUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
L
H
L
L
L
H
X
X
H
X
X
X
Mode
Deselected: Power Down
DATAoUT Read Lower Byte Only
DATAoUT DATAoUT Read Both Bytes
High-Z
HighZ
Outputs Disabled
NOTE:
1.
2911 tbJ 02
AOL-A11L~AoR-A11R
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
UO~7
CE
ANI
OE
US
LB
SEM
H
H
L
X
X
L
DATAoUT DATAoUT Read Data in Semaphore Flag
DATAoUT DATAoUT Read Data in Semaphore Flag
X
H
UOS-15
Mode
L
H
H
L
H
f
X
X
X
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
X
f
X
H
H
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
L
X
X
L
X
L
L
X
X
X
L
L
-
-
2911 tbJ 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
toGND
Not Allowed
Not Allowed
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Commercial Unit
-0.5 to +4.6
V
Grade
Ambient
Temperature
GND
Vee
O°C to +70°C
OV
3.3V±0.3
Military
TA
Operating
Temperature
o to +70
°c
TSIAS
Temperature
Under Bias
-55 to +125
°c
TSTG
Storage
Temperature
-55 to +125
°c
lOUT
DC Output
Current
50
mA
Commercial
2911 tbJ 05
RECOMMENDED DC OPERATING
CONDITIONS
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
3.0
3.3
3.6
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.0
Vcc+0.3
V
VIL
Input Low Voltage
-0.3(1)
0.8
V
Symbol
NOTE:
2911 tbJ 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc +0.5V for more than 25% of the cycle time or
10nsmaximum,andislimitedto s.20mafortheperiodover VTERM ~ Vcc
+0.5V.
-
NOTE:
1. VIl2 -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
2911 tbJ 06
CAPACITANCE (TA = +25°C, F = 1.0MHZ)
TQFP Pkg. Only
Symbol
Parameter(1)
CIN
Input Capacitance
COUT
Output
Capacitance
Conditions
Max.
=3dV
Your =3dV
9
pF
11
pF
VIN
Unit
NOTE.
2911 tbJ 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
6.30
4
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc =3.3V ± O.3V)
IDT70V24S
Symbol
Parameter
IDT70V24L
Test Conditions
Min.
Max.
lIul
Input Leakage Current(1)
Vee = 3.6V, VIN = OV to Vee
-
10
IILOI
Output Leakage Current
CE = VIH, VOUT = OV to Vee
10
VOL
Output Low Voltage
IOL= 4mA
-
VOH
Output High Voltage
IOH = -4mA
2.4
Min.
Max.
Unit
5
IlA
5
IlA
0.4
-
0.4
-
2.4
-
V
V
2911 tblOS
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc =3.3V + O.3V
70V24X25
Svmbol
lee
1881
1882
...
...
Test
-" .
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
(Both Ports Active)
f = fMAx(3)
Standby Current
(Both Ports - TTL
CER = CEL = VIH
SEMR = SEML = VIH
Level Inputs)
f = fMAX(3)
Standby Current
CE"A'=VIL and CE"8"=VIH(5)
(One Port -
Active Port Outputs Open
TTL
Level Inputs)
f = fMAX(3)
Full Standby Current
(Both Ports - All
Both Ports CEL and
CER ~Vee - 0.2V
CMOS Level Inputs)
VIN ~ Vee - 0.2V or
VIN ~ 0.2V, f = 0(4)
SEMR = SEML > Vee-0.2V
Full Standby Current
(One Port-All
CE"A· < 0.2 and
CE"8" ; Vee - 0.2V(5)
70V24X35
70V24X55
TVD.(2)
Max.
TVD. (2)
Max.
Uni1
COM
S
L
80
80
140
120
70
70
115
100
70
70
115
100
mA
COM
S
L
12
10
25
20
10
8
25
20
10
8
25
20
mA
COM
S
40
82
35
72
35
72
mA
L
40
72
35
62
35
62
COM
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
COM
S
L
50
50
81
71
45
45
71
61
45
45
71
61
mA
Versi :m
TVD.(2) Max.
SEMR = SEML = VIH
1883
1884
CMOS Level Inputs)
SEMR = SEML~ Vee-0.2V
VIN ~ Vee - 0.2V or
VIN ~ 0.2V, Active Port
Outputs Open,
f = fMAX(3)
NOTES:
2911
tbl09
1. 'X' in part numbers indicates power rating (S or L)
2. Vee =3.3V, TA =+2S o C, and are not production tested. Icc DC = 70mA (TYP.)
3. At f = fMAx, address and conlrollines (except Output Enable) are cycling at the maximum frequency read cycle of 1ltRC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "S" is the opposite from port "A".
6.30
5
ID170V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 & 2
2911 tbll0
3.3
589n
DATAoUT
BUSY----~--~~~
INT
434n
DATAoUT ...............~.....~.....~
30pF
434n
5pF
2911 drw05
Figure 1. Output Test Load
(for tu, tHZ, twz, tow)
Figure 2. Output Test Load
(for tLZ, tHz, twz, tow)
* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V24X25
Min.
Parameter
Symbol
Max.
IDT70V24X35
IDT70V24X55
Min.
Min.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
55
-
ns
tAA
Address Access Time
25
35
ns
Chip Enable Access Time(3)
35
55
ns
25
55
ns
15
-
20
-
55
tACE
-
30
ns
3
-
3
-
ns
3
-
3
-
ns
tABE
Byte Enable Access Time(3)
tAOE
Output Enable Access Time
-
tOH
Output Hold from Address Change
3
tLZ
Output Low-Z Time(l. 2)
3
-
tHZ
Output High-Z Time\l.~)
-
15
-
20
-
25
ns
tpu
Chip Enable to Power Up Time(2)
0
-
0
-
0
-
ns
tPD
Chip Disable to Power Down Time(2)
-
25
-
35
-
50
ns
tsoP
Semaphore Flag Update Pulse (DE or SEM)
15
-
15
-
15
-
ns
tSAA
Semaphore Address Access Time
-
35
-
45
-
65
25
35
NOTES:
1. Transition is measured ±200mV from low or high impedance voltage with load (figures 1 and 2).
2. This parameter is guaranteed by device characterization. but is not production tested.
3. To access RAM. CE = VIL. UB or LB = VIL, and SEM = VI. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
ns
2911 tblll
TIMING OF POWER-UP POWER-DOWN
2911 drw06
6.30
6
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
"
"
I
I
\\\\
tAA(4)
--tACE(4)
fill
--tAOE(4)
\\\\
)'111
-tABE(4)
UB, LB
\\\\
)'111
Rm
--tLZ(1)
----j"
DATAoUT
1\'XI
II\,
f4- tOH-1
VALID DATA(4)
tHZ(2)
\\\\\\\~
~
I
__ tBDD (3, 4)
2911 drwO
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, [8, or UB.
2. Timing depends on which signal is de-asserted firs CE, OE, LB, or UB.
3. tBOO delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last IABE, tAOE, tACE, tM or tBOO.
5. SEM =VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
Symbol
Parameter
IDT70V24X25
IDT70V24X35
IDT70V24X55
Min.
Min.
Min.
Max.
Max.
Max.
Unit
WRITE CYCLE
-
0
Write Enable to Output in High-Zll, &o}
-
tow
Output Active from End-of-Write\l", 4)
0
tSWRD
SEM Flag Write to Read Time
5
tsps
SEM Flag Contention Window
5
twc
Write Cycle Time
25
tEW
Chip Enable to End-of-Write(3)
20
tAW
Address Valid to End-of-Write
20
tAS
Address Set-up Time(3)
0
twp
Write Pulse Width
-tWR
Write Recovery Time
0
tDW
Data Valid to End-of-Write
15
tHZ
Output High-Z Time l ,~}
tDH
Data Hold Time l '!}
twz
20
-
35
-
55
30
45
30
-
0
-
0
25
40
0
-
ns
20
-
30
-
ns
15
-
20
-
25
ns
-
0
-
0
-
ns
15
-
20
-
25
ns
-
0
-
0
ns
5
-
5
5
-
5
-
0
45
ns
ns
ns
ns
ns
ns
ns
NOTES:
2911 tbl12
1. Transition is measured ±200mV from low or high impedance voltage with Output Test Load (Figure 2).
2. This parameter is~aranteed by device characterization, but is not production tested.
_
3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW
time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
6.30
7
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF WRITE CYCLE NO.1, RlWCONTROLLED TIMING(1,5,8)
twe
,~
~J-
ADDRESS
-I\.
jl\
IHZ(7)
j
tAW
GEar SEM
GEar SEM
(9)
-k:
(9)
-k:
(3)
twp(2)
i+--tAS (6\
tWR
II
\-1\
-~
j
I-tw~
DATAoUT
tow~
\I
If
'I
(4)
tow
(4)
.'.
tOH
,
3_J------
D A T A I N - - - - - - - - I_
F
_______
2911 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE, UB, LB CONTROLLED TIMING(1,S)
twe
~~
~~
ADDRESS
j
j
tAW
GE or SEM
~r
(9)
I+- tAS(6)
US or LS
RiW
DATAIN
-Il
j
1\
tWR(3)
tEW(2)
~t1\
(9)
I+-
-Il
j
\\\
------IF
tow
• III
tOH
3r--2911 drw 09
NOTES:
1. Rm or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a low UB or LB and a low CE and a low Rm for memory array writing cycle.
3. tWR is measured from the earlier of CE or Rm (or SEM or RiW) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last, CE, Rm or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ±200mV from low or high impedance voltage
with Output Test Load (Figure 2).
8. If OE is low during RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tDW) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tDW. If OE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
9. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire lEW
time.
6.30
8
IDT70V24S/L
HIGH-SPEED 4K
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(l)
14---tSAA
Ao - A2
VALID ADDRESS
DATA OUT
VALID
DATAo------~--------+-~
RAN-------+----------.~-~ ~OE
2911drwl0
NOTE:
1. CE
=VIH or UB & LB =VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
....JX'-_____________
AO"A"-A2"A'_'_____M_A_T_C_H
______
SIDE(2) "A"
SEM"A"
AO"B"-A2"B"
SIDE(2) "8"
NOTES:
=
=
=
=
=
1. DOR DOL VIL, CER CEL VIH, or Both UB & LB VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "8" is the opposite port from "A".
3. This parameter is measured from RiWA or SEMA going high to RiWB or SEMB going high.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is not guarantee which side will obtain the flag.
6.30
9
ID170V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Parameter
SXmbol
BUSY TIMINGJMlS =
IDT70V24X35
IDT70V24X55
Min,
Min,
Max,
Max,
Unit
ns
ns
Hl
tBAA
BUSY Access Time from Address Match
-
BUSY Disable Time from Address Not Matched
-
35
taDA
35
-
tBAC
BUSY Access Time from Chip Low
-
35
-
taDc
BUSY Disable Time from Chip High
-
35
-
45
45
45
45
tAPS
Arbitration Priority Set-up Time(2)
5
-
5
-
tBDD
BUSY Disable to Valid Data(3)
-
Note 3
-
ns
ns
ns
Note 3
ns
BUSY TIMING (MIS = L)
twa
BUSY Input to Write(4)
0
-
0
tWH
Write Hold After BUSY(5)
25
-
25
-
-
65
60
-
S5
80
ns
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(l)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With
BUSY (M is = H)" or "Timing Waveform of Write With Port-To-Port Delay (M is= L)".
2. To ensure that the earlier of the two ports wins.
3. !BOD is a calculated parameter and is the greater of Ons, twoo - twp (actual) or tODD - tow (actual).
4. To ensure that the write cycle is inhibited on port 'B' during contention with port 'A'.
5. To ensure that a write cycle is completed on port 'B' after contention with port 'A'.
6. "X" in part numbers indicates power rating (S or L).
TIMING WAVEFORM OF READ WITH BUSV(2) (MiS
ns
ns
2740 tbl13
=H)
twc
ADDR'A
)K
)
MATCH
K
twp
~
RfiJ"A
K
tow
)(
DATAIN'A
/
V
*"
VALID
tAps (1)
ADDR"B
) (~
MATCH
\
BUSY"B
+-
tBAA
tBOA
"r---~
twoo
I
tBOO
At
)
DATAoUT"B
tODD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Mis = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If Mis= VIL(slave) then BUSY is an input BUSY'A' =VIL and BUSY'B' =don't care, for this example.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from
port "A".
6.30
E
2911 drw 12
10
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SLAVE WRITE (MiS = L)
~------twP------~
BUSY"B"
(2)
Note:
1. tWH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" Blocking RIW'B", until BUSY"B" goes High.
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY GETIMING(1)(M/S
X
ADDR"A" _______- J
and "B"
=H)
,~
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
ADDRESSES MATCH
./'....
IAP,.;j:'""""----1------------------...J1
l:= lBAC:j
~
-b
IBDC --: ,_ _
A
2911drw14
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDR"A"
ADDRESS "N"
ADDR"B"
MATCHING ADDRESS "N"
1-
IBAA ~ _ _
'BDA
BUSY"B"
2911 drw 15
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. If tAPS is not satisfied, the busy Signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
6.30
11
IDT70V24S/L
HIGH-SPEED 4K
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
x 16 DUAL-PORT STATIC RAM
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT70V24X35
Symbol
Parameter
Min.
Max.
IDT70V24X55
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
0
0
-
0
-
ns
0
-
ns
-
30
35
-
40
45
ns
-
NOTE:
1. "X" in part numbers indicates power rating (S or L).
ns
2911 tbl14
WAVEFORM OF INTERRUPT TIMING(1)
~--------------------- twc--------------------~
INTERRUPT SET ADDRESS(2)
ADDR'A'
CE'A"
___________________
tIN_S_3_)~
INT"B"
.
--------------------------------------------------
2911 drw16
~---------------------
tRC ------------------~
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
IINR(3)
~
.......- - - - - - - - - - - - - - - - - - - - - - - - - - -
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal (c'E or Rm) is asserted last.
4. Timing depends on which enable signal (c'E or R/W) is de-asserted first.
2911 drw 17
TRUTH TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Left Port
RNll
CEL
L
L
X
X
X
Right Port
OEl A11l-Aol INTl
FFF
X
X
X
X
X
X
X
X
X
L(3)
L
L
FFE
H(2)
A11R-AoR INTR
L(2)
X
RIWR
CER
OER
X
X
X
X
L
L
FFF
H(3)
L
L
FFE
X
X
X
X
X
X
NOTES:
1. Assumes BUSYL =BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTl Flag
Reset Left INTL Flag
2911 tbl15
6.30
12
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
TRUTH TABLE II ARBITRATION
ADDRESS BUSY
Inputs
AOL-A11L
AOR-A11R
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
Outputs
BUSYl(1) BUSYR(1)
CEl
CER
X
NO MATCH
H
H
Normal
H
X
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
Function
NOTES:
29tt tblt6
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V24 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
=
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
No Action
Do - 015 Left
Do - 015 Right
1
Status
Semaphore free
1
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Right port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This lable denotes a sequence of events for only one of the eight semaphores on the IDT70V24.
2911 tblt7
FUNCTIONAL DESCRIPTION
The IDT70V24 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V24 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
memory location FFF (HEX) and to clear the interrupt flag
(INTR), the right port must read the memory location FFF. The
message (16 bits) at FFE or FFF is user-defined, since it is an
addressable SRAM location. If the interrupt function is not
used, address locations FFE and FFF are not used as mail
boxes, but as part of the random access memory. Refer to
Table I for the interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is asserted when the right port
writes to memory location FFE (HEX), where a write is defined
as the CE=RIW=VIL per the Truthe Table. The left port clears
the interrupt by accessing address location FFE when
CER=OER=VIL, RIW is a "don't care". Likewise, the right port
interrupt flag (lNTR) is asserted when the left port writes to
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.30
13
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V24SIL
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
roo-
I
MASTER
Dual Port
.BAM..
SLAVE
CE
Dual Port
.BAM..
I
I
I
I
MASTER
Dual Port
BAM..
BUSY (L)
W
Q
0
w
Q
""-
1
T
SLAVE
CE
Dual Port
BAM..
BUSY (L) BUSY (R)
1
cr:
..---
()
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
1
T
CE
CE
BUSY (L) BUSY (R)
I
I
BUSY(R)
1
I
2911 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V24 RAMs.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the Mis pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the lOT 70V24 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V24 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V24 RAM the busy pin
is an output if the part is used as a master (MIS pin = H), and
the busy pin is an input if the part used as a slave (MIS pin
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a masterlslave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
=
initiated with either the Rm signal or the byte enables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
SEMAPHORES
The IDT70V24 is an extremely fast Dual-Port 4K x 16
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT70V24 contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V24's hardware semaphores,
which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
6.30
14
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
to be allocated in varying configurations. The IDT70V24 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT70V24 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RiW) as they
would be used in accessing a standard Static RAM. Each of
t~e fla~s has a unique addr~ss which can be accessed by
either Side through address pins AO- A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that
the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
activ~. This ~erves to disallow the semaphore from changing
state In the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain.a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a s~quence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
I~oking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made the
logic guarantees that only one side receives the token. If'one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
6.30
15
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EX:AMPLES
Perhaps the simplest application of semaphores is their
application as resource markers forthe IDT70V24's Dual-Port
RAM. Say the 4K x 16 RAM was to be divided into two 2K x
16 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 2K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 2K. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
O. At this point, the software could choose to try and gain
control of the second 2K section bywriting, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 2K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
. Sem~aphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the 1/0 device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the 1/0 devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
UQ.BI
.B..E.QBI
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do
Do
WRITE
WRITE
SEMAPHORE~____~~
L----........._ _ _ _. .
READ
SEMAPHORE
READ
2911 drw 19
Figure 4. IDT70V24 Semaphore Logic
6.30
16
IDT70V24S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
~Blank
~----------------------------------------~
L...------~--------------------------------------------------__i
'---------------------------------------------------------------1
'-------------------~
PF
G
J
Commercial (O°C to +70°C)
100-pin TQFP (PN100-1)
84-pln PGA (G84-3)
84-pin PLCC (J84-i)
25}
35
Speed inn anoseconds
55
S
L
Standard Power
Low Powe r
70V24 64K (4K x 16) 3.3V Dual-Port RAM
2911 drw 20
6.30
17
(;)
PRELIMINARY
IDT70V25S/L
HIGH-SPEED 3.3V
8K X 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• M/S =H for BUSY output flag on Master
M/S =L for BUSY input on Slave
• Interrupt Flag
• Devices are capable of withstanding greater than 2001 V
electrostatic charge.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• TTL-compatible, single 3.3V (±0.3V) power supply
• Available in 84-pin PGA, PLCC and 100-pin TQFP
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Commercial: 25/35/55ns (max.)
• Low-power operation
- IDT70V25S
Active: 230mW (typ.)
Standby: 3.3mW (typ.)
- IDT70V25L
Active: 230mW (typ.)
Standby: .66mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT70V25 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
DESCRIPTION:
The IDT70V25 is a high-speed 8K x 16 Dual-Port Static
RAM. The I DT70V25 is designed to be used as a stand-alone
128K-bit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 32-bit-or-more word systems.
FUNCTIONAL BLOCK DIAGRAM
RlWl
RIWR
UBR
r'---....
'\
UBl
r
,--
'==
a=>---,
J
4<4 I:=-
I/OSl-1/015l
1/0
Control
2)
··
A12l
AOl
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE):
SY
is input.
2. BUSY output s
and INToutp uts
are non-tri-statad
push-pull.
Address
Decoder
A
I
"
'If
"
MEMORY
ARRAY
v
"
~
A
•
I/OOl-1/07 l
BUSy~1,
~
~~
I/00R-I/07R
•
BUSy~1,2)
A
'"
13
"
v
13
-,
so-
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEd
OEl:
RlWl;
I
1\
I/OSR-1/015R
1/0
Control
tI t I
Mis
Address
Decoder
--
··
A12R
AOR
I
.CER
--:OER
.RtWR
I
~
SEMR
INT~2)
2944 drw01
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
101995 Integrated Device Technology, Inc.
APRIL 1995
6.31
DSC-128712
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
Using the lOT MASTER/SLAVE Dual-Port RAM approach in
32-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate
control, address, and 110 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOS high-performance technology, these devices typically operate on only 35DmW of power.
The IDT7DV25 is packaged in a ceramic 84-pin PGA, an
84-Pin PLCC and a 1DD-pin Thin Quad Plastic Flatpack.
PIN CONFIGURATIONS
A7L
I/OSl
I/09l
A6L
I/010l
ASL
I/OllL
A4l
I/012L
A3L
I/013l
A2L
GND
AlL
AOL
I/01Sl
vee
GND
IDT70V25
J84-1
INTL
(1)
BUSYL
84-PIN PLCC
TOP VIEW
GND
MIS
BUSYR
INTR
AOR
A1R
A2R
A3R
A4R
ASR
A6R
2944 drw 02
N/C
N/C
N/C
1/013
GN
IDT70V25
PN100-l
100-PIN
TQFP
TOPVIEW(I)
N/C
ASl
A4l
A3l
A2l
All
AOl
INTL
BUSYl
GND
MIS
BUSYR
INTR
AoR
A1R
A2R
A3R
A4R
N/C
N/C
N/C
N/C
NOTE:
1. This text does not indicate orientation of the actual part- marking.
6.31
2
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
63
11
66
10
64
67
I/013l
75
I/Oll
47
50
53
GND
46
LBl
44
43
52
I/OlA
81
IDT7V025
G84-3
GND
78
I/02R
32
82
28
Vee
AOl
Mis
7
I/OlA
11
GND
5
8
I/06R
I/09R
2
I/010R
I/013R
I/015R
84
I/08R
3
I/OllR
4
I/012R
6
I/014R
9
B
C
D
12
GND
INTR
10
14
RtWR
15
OER
13
LBR
20
AllR
16
A1R
25
A5R
17
UBR
BUSYR
27
23
SEMR
All
30
A2R
I/04R
INTl
36
29
AOR
A2l
34
26
1
A4l
37
31
GND
84-PIN PGA
TOPVIEW(3)
83
I/05R
39
35
BUSYl
Vee
74
GND
A5l
A3l
33
80
I/03R
40
A6l
73
I/014l
A7l
A8l
41
RtWl
Vee
42
Al0l
A9l
A12l
CEL
45
Alll
38
77
79
02
SEMl
UBl
57
70
76
03
49
56
I/03l
48
51
OEL
I/012l
I/OOR
04
59
I/06l
I/09l
71
I/015l
05
62
54
I/OOl
68
72
06
55
I/02l
65
69
07
58
I/04l
I/08l
I/Olll
08
60
I/05l
I/010l
09
01
61
I/07l
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
22
A3R
24
A8R
A6R
A4R
19
A9R
21
AlA
K
CER
A12R
18
AlaR
G
H
J
II
II
A
E
F
L
2944 drw 04
Index
PIN NAMES(1,2)
Left Port
Right Port
CEl
CER
Names
Chip Enable
RlWl
RIWR
ReadlWrite Enable
OEl
OER
Output Enable
AOl- A12l
AOR - A12R
Address
IIOOl -II015l
IIOOR - II015R
Data Input/Output
SEMl
SEMR
Semaphore Enable
UBl
UBR
Upper Byte Select
LBl
LBR
Lower Byte Select
INTl
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
Power
GND
Ground
2944 tbl 01
NOTES:
1. All Vce pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part- marking.
6.31
3
IDT70V25S/L
HIGH-SPEED 8K
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
x 16 DUAL-PORT STATIC RAM
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
Outputs
CE
RIW
OE
UB
LB
SEM
1/08-15
1/00-7
H
X
H
High-Z
High-Z
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
L
X
X
X
X
X
X
X
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAoUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
L
H
L
L
L
H
X
X
H
X
X
X
Mode
Deselected: Power Down
DATAoUT Read Lower Byte Only
DATAoUT DATAoUT Read Both Bytes
High-Z
High-Z
Outputs Disabled
NOTE:
2944 tbl 02
1. AOL - A12L "# AOR -
A12R
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Inputs
Outputs
RIW
OE
UB
LB
SEM
H
H
L
X
X
L
DATAoUT DATAoUT Read Data in Semaphore Flag
X
H
DATAoUT DATAoUT Read Data in Semaphore Flag
H
X
L
L
1/08-15
Mode
CE
L
H
H
L
f
X
X
X
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
J
X
H
H
L
DATAIN
DATAIN
Write DINO into Semaphore Flag
X
X
L
X
L
X
L
L
X
X
-
VTERM(2)
Rating
Terminal Voltage
with Respect
toGND
-0.5 to +4.6
Not Allowed
V
Grade
Ambient
Temperature
GND
Vee
O°C to +70°C
OV
3.3V ±0.3
Military
Operating
Temperature
a to +70
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-55 to +125
°C
DC Output
Current
Not Allowed
-
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Commercial Unit
TA
lOUT
-
2944 tbl 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
1/00-7
50
Commercial
2944 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
mA
NOTE:
2944tbl04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to S. 20 mA for the period over VTERM
~ Vce + 0.5V.
Parameter
Max. Unit
Min.
Typ.
Vee
Supply Voltage
3.0
3.3
3.6
V
GND
Supply Voltage
a
a
a
V
VIH
Input High Voltage
2.0
-
Vcc+O.~
V
VIL
Input Low Voltage
-0.3(1)
-
0.8
V
Symbol
NOTE:
1. VILL: -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
2944 tbl 06
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)
Max.
Unit
CIN
Input Capacitance
VIN= 3dV
9
pF
COUT
Output
Capacitance
VOUT= 3dV
10
pF
Symbol
Conditions
NOTE:
2944 tbl 07
1. This parameter is determined by device characterization but is not
production tested (TQFP Package only).
2. 3dV references the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
6.31
4
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (vcc =3.3V ± O.3V)
IDT70V25S
Parameter
Symbol
Test Conditions
Min.
IOl =4mA
-
IOH = -4mA
2.4
IILlI
Input Leakage Current(l)
Vee = 3.6V, VIN = OV to Vee
IIlOI
Output Leakage Current
CE = VIH, VOUT = OV to Vee
VOL
Output Low Voltage
VOH
Output High Voltage
IDT70V25L
Max.
Min.
Max.
Unit
10
-
5
IlA
10
-
5
IlA
0.4
-
0.4
V
-
2.4
-
V
NOTE:
1. At Vee = 2.0V input leakages are undefined.
2944 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC =3.3V ± O.3V)
70V25X25
Test
Condition
70V25X35
70V25X55
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Dynamic Operating
Current
(Both Ports Active)
CE = Vll, Outputs Open
SEM =VIH
f = fMAX(3)
COM'L. S
L
80
80
170
120
70
70
115
100
70
70
~OO
ISB1
Standby Current
(Both Ports - TTL
CER = CEl = VIH
SEMR = SEMl= VIH
Levellnputs)f = fMAX(3)
COM'L. S
L
12
10
25
20
10
8
25
20
10
8
25
20
mA
18B2
Standby Current
(One Port - TTL
Level Inputs)
CEl or CER = VIH(5)
Active Port Outputs Open
f = fMAX(3)
SEMR = SEMl = VIH
COM'L. S
L
40
40
82
72
35
35
72
62
35
35
72
62
mA
18B3
Full Standby Current Both Ports CEl and
CER ;;:: Vee - 0.2V
(Both Ports - All
CMOS Level Inputs) VIN ~ Vee - 0.2V or
VIN ~ 0.2V, f = 0'4)
SEMR= SEMl;;:: Vee - 0.2V
COM'L. S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
18B4
Full Standby Current One Port CEl or
CER ;;:: Vee - 0.2V(5)
(One Port-All
CMOS Level Inputs) SEMR = SEMl;;:: Vee - 0.2V
VIN ;;:: Vee - 0.2V or
VIN ~0.2V
Active Port Outputs
Open, f = fMAX(3)
COM'L. S
L
50
50
81
71
45
45
71
61
45
45
71
61
mA
Symbol
lee
Parameter
Version
Max. Unit
115
mA
NOTES:
2683 tbl 09
1. 'X' in part numbers indicates power rating (S or L)
o
2. Vec SV, TA +2S C, and are not production tested. Icc de = 70mA (TYP)
3. At f fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 11 RC, and using "AC Test Conditions"
of input levels of GND to 3V.
4. f 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
=
=
=
=
6.31
5
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
589Q
DATAoUT
BUSy---.--+-.....
INT 434Q
30pF
DATAoUT--_-+--
434Q
5pF
See Figures 1 & 2
2944 drwOS
2944 tbt 11
Figure 1. AC Output Load
Figure 2. Output Test Load
(For tLZ, tHZ, twz, tow)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V25 x25
Symbol
Parameter
Min.
Max.
IDT70V25 x35
Min.
Max.
IDT70V25 x55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
55
-
ns
tM
Address Access Time
25
ns
55
ns
tABE
Byte Enable Access Time(3)
-
25
tAOE
Output Enable Access Time
-
-
55
Chip Enable Access Time(3)
-
35
tACE
-
tOH
Output Hold from Address Change
3
tLZ
3
-
3
Output Low-Z Time(l, 2)
20
-
-
tHZ
Output High-Z Time(1, 2)
tpu
Chip Enable to Power Up Time(2)
tPD
Chip Disable to Power Down Time(2)
-
tsop
Semaphore Flag Update Pulse (OE or SEM)
15
tSM
Semaphore Address Access Time
-
a
25
15
-
35
35
20
3
3
15
-
a
25
35
a
ns
30
ns
-
ns
25
ns
ns
-
ns
-
50
ns
-
15
-
ns
45
-
65
-
-
55
15
-
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with Output Test Load (Figure 2).
2. This parameter iSJl.!:!.arantee~ device characterazation, but is not production teste!!:...
_
_
3. To access RAM, CE =VIL, UB or LB =VIL, and SEM =VIH. To access semephore, CE =VIH or UB & LB
4. "X" in part numbers indicates power rating (S or L).
3
55
ns
2944 tbl12
=VIH,
_
and SEM
=VIL.
TIMING OF POWER-UP POWER-DOWN
2944 drw 06
6.31
6
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF READ CYCLES(5)
tRC
\I
I
ADDR
\I{
J~
tAA(4)
\\\\
~tACE(4)
/111
~tAOE(4)
\\\\
/111
-tABE(~)
\\\\
/111
RiW
i--tLZ(l)
DATAoUT
I - tOH--j
VX'
1\ ,,"'-
~1
VALID DATA(4)
tHZ(2)
I
I
\\\\\\\~
BUSYOUT
I- tBOO(3, 4)
2944 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBOO delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM =VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
Symbol
Parameter
IDT70V25X25
IDT70V25X35
IDT70V25X55
Min,
Min.
Max.
Min.
Max.
35
55
-
ns
45
-
ns
0
0
-
0
-
ns
25
-
20
-
30
-
ns
-
20
-
25
ns
Max.
Unit
WRITE CYCLE
15
-
-
15
twc
Write Cycle Time
25
tEW
Chip Enable to End-of-Write(3)
20
tAW
Address Valid to End-of-Write
20
tAS
Address Set-up Time(3)
twp
Write Pulse Width
20
tWR
Write Recovery Time
0
tow
Data Valid to End-of-Write
tHZ
Output High-Z Time\ I,
0
~)
30
30
0
45
40
ns
ns
ns
tOH
Data Hold Time(4)
0
-
0
-
0
-
ns
twz
Write Enable to Output in High-Z\ I, ~)
-
15
-
20
-
25
ns
tow
-
0
-
0
--
5
5
-
5
-
ns
5
Output Active from End-of-Write(J,~, 4)
0
tSWRO
SEM Flag Write to Read Time
5
tsps
SEM Flag Contention Window
5
-
ns
ns
NOTES:
2944 tbl13
1. Transition is measured ±SOOmV from low or high impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL, UB or LB VIL, SEM VIH. To access semaphore, CE = VIH or UB & LB VIH, and SEM VIL. Either condition must be
valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will
vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
=
=
=
=
6.31
=
7
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING(1,5,8)
twc
~~
ADDRESS
"
J\
J~
tHZ(7)
}
tAW
CEorSEM
CE orSEM
(9)
-.l
J
-.~
(9)
-tAS(6\
RiW
(3)
twp(2)
,
twR
I
J'-
-~
~twz~
DATAoUT
tow~
\I
(4)
~
(4)
1\
,
J
DATAIN----------------------------~~~---------------~~r------------------tow
tOH
.'11
2944 drw08
TIMING WAVEFORM OF WRITE CYCLE NO.2, GE, UB, LB CONTROLLED TIMING(1,5)
twc
~~
~~
ADDRESS
J~
1\
tAW
CEor SEM
I-+- tAs(6)
US or LS
,'-
~r-
(9)
twR(3)
tEW(2)
~
(9)
I+-
-.l
J
\~\
RiW
tow
tOH
---{F--~I-• J •
DATAIN
2944 drw09
NOTES:
1. R!W or CE or US & LS must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low US or [8 and a low CE and a low RiW for memory array writing cycle.
3. tWR is measured from the earlier of CE or RiW (or SEM or RfiJ) going high to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last, CE, RiW, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with Output
Test Load (Figure 2).
8. If OE is low during RIW controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tOW) to allow the I/O drivers to tum off and data
to be placed on the bus for the required tOW. If OE is high during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE VIL, US or LS = VIL, and SEM VIH. To access Semephore, CE VIH or US & LS = VIL. and SEM VIL. tEW must be met
for either condition.
=
=
=
6.31
=
8
IDT70V25SIL
HIGH-SPEED 8K
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
14---tSAA
Ao - A2
VALID ADDRESS
DATA OUT
VALID
DATAo------~--------+-c
RAN------~------,
---~.-~ ~OE
2944 drw 10
NOTE:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
---JX'-_____________
AO"A"-A2"A'_'_____M_A_T_C_H
______
SIDE(2) "A"
SEM"A"
AO"B"-A2"B"
SIDE(2) "B"
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from RiW'A' or SEM"A' going High to Rfii's' or SEM''s' going High.
4. If tsps is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6,31
9
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V25S/L
HIGH~SPEED
8K x 16 DUAL-PORT STATIC RAM
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
Parameter
~USY TIMING (MIS
IDT70V25X25
IDT70V25X35
IDT70V25X55
Min.
Min.
Min.
Max.
Max.
Max.
Unit
=H)
tBM
BUSY Access Time from Address Match
-
tBOA
BUSY Disable Time from Address Not Matched
-
BUSY Disable Time from Chip HIGH
-
35
35
35
35
-
45
45
45
45
ns
-
25
25
25
25
tBAC
BUSY Access Time from Chip LOW
tBOC
tAPS
Arbitration Priority Set-up Time\~)
5
-
5
-
5
-
ns
tBOD
BUSY Disable to Valid Datal;j)
-
25
-
35
-
55
ns
0
20
-
0
25
-
0
25
-
ns
55
50
-
60
55
-
80
75
ns
-
BUSY TIMING (MIS
ns
ns
ns
=L)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
ns
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delaytl)
-
tODD
Write Data Valid to Read Data Delay(1)
-
ns
2944 tbl14
NOTES:
1. Port·to-port delay through RAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE
PORT-TO-PORT READ AND BUSY (MIS VIH}".
2. To ensure that the earlier of the two ports wins.
3. tsoo is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tODD - tOW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. "x" is part numbers indicates power rating (S or L).
=
TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUS'«2,5) (MiS
=VIH)
twc
ADDR"A
)(
)
MATCH
twp
~
'"
toW
)(
DATAIN "A
/
<
V
tOH
)
VALID
tAps (1)
ADDR"s
) (~
MATCH
\
BUSY"s
<
tBAA
~
"- -~
tSOA
I
}
tsoo
twOD
DATAoUT"S
tODD (3)
)~
2944 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CEl= CER = L
3. OE = L for the reading port.
6.31
10
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF WRITE WITH BUSY
t . - - - - - twP-----I~
R/WOIA OI
BUSyllBoo
R/WOIB"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. Busy is asserted on port "B" Blocking R/W'B', until BUSY'B' goes High
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1) (MiS
-JX. . .__________
A~~~::~:: _ _
=H)
----"X""--__
A_D_D_R_E_S_S_E_S_M_A_T_C_H_ _ _ _ _ _ _ _ _ _
IAPS(:t----------------
l
-C=(BAC1-_ _
BUSY"s"
2944 drw 14
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH
TIMING(1)(M/S H)
=
ADDRESS "N"
ADDR'A'
1+-_--+-\ tAps (2)
ADDR's'
MATCHING ADDRESS "N"
BUSY's'
2944 drw 15
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. If tAps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
6,31
11
IDT70V25S/L
HIGH~SPEED
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
8K x 16 DUAL-PORT STATIC RAM
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Svmbol
INTERRUPT TIMING
IDT70V25X25
Min. Max.
Parameter
IDT70V25X35
Min. Max.
IDT70V25X55
Min. Max.
Unit
tAS
Address Set-up Time
0
--
0
--
0
Write Recovery Time
0
--
0
0
tiNS
Interrupt Set Time
--
--
---
ns
tWR
25
--
30
--
40
ns
tlNR
Interrupt Reset Time
--
30
--
35
--
45
ns
NOTE:
1. "X" in part numbers indicates power rating (S or L).
ns
2944 tbl15
WAVEFORM OF INTERRUPT TIMING(1)
~---------------------- twc--------------------~
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
~-------------------------
IINd'1
2944 drw 16
~---------------------- tRC--------------------~
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
1
~---------------------------------------------------
__________________t_IN_R_(3_
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A".
2. See Interrupt Flag truth table.
3. Timing depends on which enable signal ( CE or RfiiJ) is asserted last.
4. Timing depends on which enable signal ( CE or RfiiJ ) is de-asserted first.
2944 drw 17
TRUTH TABLES
TRUTH TABLE I--INTERRUPT FLAG(1)
Right Port
Left Port
RN-A
CEL
OEL A12L-AoL
L
L
X
1FFF
X
X
X
X
X
X
X
X
X
L
L
1FFE
RlWR
CER
OER
X
X
X
X
X
X
L
L
1FFF
H(3)
L(;;!)
L
L
1FFE
H(2)
X
X
X
X
X
X
NOTES:
1. Assumes BUSYL BUSYR VIH.
2. If BUSYL VIL, then no change.
3. If BUSYR VIL, then no change.
=
=
=
A12R-AoR INTR
L(2)
X
INTL
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2944 tbl16
=
6.31
12
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
TRUTH TABLE 11- ADDRESS BUSY
ARBITRATION
Outputs
Inputs
CEL
CER
AOL-A12L
AOR-A12R
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
BUSYL(1) BUSYR(1)
Function
NOTES:
2944 tbl17
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V25 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. l if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
Do - 015 Left
Status
Do - 015 Right
Semaphore free
No Action
1
1
Left Port Writes "0" to Semaphore
a
a
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
1
a
a
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
a
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
No change. Left port has no write access to semaphore
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
a
1
Right port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V25.
11
I
2944 tbl18
FUNCTIONAL DESCRIPTION
The IDT70V25 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V25 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
memory location 1FFF (HEX) and to clear the interrupt flag
(INTR), the right port must read the memory location 1FFF.
The message (16 bits) at 1FFE or 1FFF is user-defined, since
it is an addressable SRAM location. If the interrupt function is
not used, address locations 1FFE and 1 FFF are not used as
mail boxes, but as part of the random access memory. Refer
to Table I for the interrupt operation.
BUSY LOGIC
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (I NTl) is asserted when the right port
writes to memory location 1FFE (HEX), where a write is
defined as the CER RIWR VIL per the Truth Table. The left
port clears the interrupt by an address location 1FFE access
when CEl = OEl = VIL, RlWl is a "don't care". Likewise, the
right port interrupt flag (I NTR) is set when the left port writes to
=
=
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
6.31
13
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V25S/L
HIGH~SPEED
8K x 16 DUAL-PORT STATIC RAM
r--
I
MASTER
Dual Port
BAM..
SLAVE
CE
Dual Port
BAM..
J
I
I
I
MASTER
Dual Port
BAM..
BUSY (L)
CE
0
0
()
w
0
i...--
1
T
SLAVE
CE
Dual Port
BAM..
BUSY (L) BUSY (R)
1
a:
_w
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
1
T
CE
BUSY (L) BUSY (R)
I
I
BUSY (R)
J.
I
2944 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V25 RAMs.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as ~n
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the MIS pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 70V25 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V25 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V25 RAM the busy pin
is an output if the part is used as a master (MIS pin ~ H), and
the busy pin is an input if the part used as a slave (MIS pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a masterlslave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with either the Rm signal or the byte enables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
SEMAPHORES
The IDT70V25 is an extremely fast Dual-Port 8K x 16
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined by
the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT70V25 contain mUltiple processors or controllers and are typically very highspeed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V25's hardware semaphores,
which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be
6.31
14
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
allocated in varying configurations. The IDT70V25 does not
use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be a
major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
''Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthe shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT70V25 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and RiW) as they
would be used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communications. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason forthis is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
6.31
15
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V25SIL
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the I DT70V25's Dual-Port
RAM. Say the 8K x 16 RAM was to be divided into two 4K x 16
blocks which were to be dedicated at anyone time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of memory.
To take a resource, in this example the lower 4K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore O. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
O. At this point, tl:le software could choose to try and gain
control of the second 4K section by writing, then rel;lding a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 4K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the 1/0 device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the 1/0 devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory 'WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
1..f.QBI
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do
Do
WRITE
WRITE
SEMAPHORE~____~~
L - - - l -_ _~~
READ
SEMAPHORE
READ
2944 drw 19
Figure 4. IDT70V25 Semaphore Logic
6.31
16
IDT70V25S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process!
Temperature
Range
~Blank
~--------------~
'----------------i
PF
G
J
Commercial (O°C to +70°C)
100-pin TQFP (PN100-1)
84-pln PGA (G84-3)
84-pin PLCC (J84-i)
~~} Speed in Nanoseconds
55
S
Standard Power
Low Power
70V25
128K (8K x 16) 3.3V Dual-Port RAM
L-------------------i L
'----------------------l
2944 drw20
6.31
17
(;)
PRELIMINARY
IDT70V26S/L
HIGH-SPEED 3.3V
16K X 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• Mis =H for BUSY output flag on Master
Mis =L for BUSY input on Slave
• Devices are capable of withstanding greater than 2001 V
electrostatic charge.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• TTL-compatible, single 3.3V (±0.3V) power supply
• Available in 84-pin PGA, and PLCC
FEATURES:
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• High-speed access
- Commercial: 25/35/55ns (max.)
• Low-power operation
- IDT70V26S
Active: 450mW (typ.)
Standby: 5mW (typ.)
- IDT70V26L
Active: 450mW (typ.)
Standby: 5mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT70V26 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
DESCRIPTION:
The IDT70V26 is a high-speed 16K x 16 Dual-Port Static
RAM. The IDT70V26 is designed to be used as a stand-alone
256K-bit Dual-Port, RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 32-bit-or-more word systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in
FUNCTIONAL BLOCK DIAGRAM
,
I
~FI
~~
~
~.~
~Jj
~
I/OSl-1/015l
1/0
AOl
•
··
Address
Decoder
A
"-
'I
v
I
1
Control
I/OOR-I/07R
-.
MEMORY
ARRAY
14
BUSy~l,2)
A
"-
'I
V
14
ARBITRATION
SEMAPHORE
LOGIC
CEl,
I
t
t
I/OSR-I/015R
1/0
t-..
'If
I/OOl-1/07l
)
~
A
Control
A13l
UBR
,-
r-'\
BUSy[l,2
RlWR
/
\..........-
t
Address
Decoder
l.-
··
A13R
AOR
I
:CER
I
MIS
2945 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs are non-tri-stated push-pull.
The lOT logo Is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device Technology, Inc.
APRIL 1995
6_32
DSC-l08812
IDT10V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
32-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate
control, address, and 1/0 pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using lOT's CMOS high-performance technology, these devices typically operate on only 450mW of power.
The IOT70V26 is packaged in a ceramic 84-pin PGA and
84-Pin PLCC.
PIN CONFIGURATIONS
...J
""
~
...J
co
~
...J
LO
...J
~
0 0
::::: :::::
...J
C')
~
...J
C\J
0
0 Z
::::: (!J
() I~I~
~ ~omg ~I~
...J
...J
...J
...J
...J
o 1
...J
...J
I~ I~
...J ...J
...J
C')
C\J ;:! 0
~ ~ ~ ~
...J
CJ)
«
AaL
/1011 L
1/013L
GNO
IOT70V26
J84-1
1/01SL
Vee
84-PIN PLCC<1)
TOP VIEW
GNO
73
A7L
72
ABL
71
ASL
70
A4L
69
A3L
68
A2L
67
A1L
66
AOL
65
BUSYL
64
GNO
63
Mis
/l01R
62
BUSYR
1/02R
61
AOR
Vee
60
A1R
/l03R
59
A2R
1/04R
58
A3R
I/OSR
57
A4R
/lOBR
56
ASR
1/07R
55
I/OOR
I/0aR
II
ABR
A7R
a: a: a: a:
a: a:
0 a: a: a: o a: a: a: a: a: a: a: a: a: a:
~
0
C\J
z
zl~ W m 1m ~ ~ ~ ~
W
I~ I~ (!Jw():::>-J««««««
(!J
CJ)
0 <5 <5
::::: :::::
:::::
C')
~ ~ ~
I 1
6
--
2945 drw02
CJ)
CJ)
NOTE:
1. This text does not indicate orientation of the actual part-marking.
6.32
2
IDT70V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
63
11
61
I/07l
64
66
10
I/010l
67
09
50
UBl
57
47
eEL
45
A12l
76
GND
79
I/02R
33
81
IOT7V026
G84-3
32
84-PIN PGA(3)
TOP VIEW
GND
28
Vcc
34
36
A2l
30
AOR
26
BUSYR
27
A3R
11
7
I/07R
GND
12
GND
5
8
I/OSR
I/09R
I/010R
I/013R
I/015R
01
84
I/08R
3
I/011R
4
I/012R
S
9
I/014R
OER
B
e
23
RlWR
15
17
UBR
13
LBR
A2R
25
A4R
ASR
SEMR
14
10
2
O,?
1
AOl
Mis
29
A1R
83
82
A3l
A1l
31
GND
I/04R
I/05R
A5l
37
35
BUSYl
Vcc
80
I/03R
39
A7l
78
77
I/01R
A6l
A4l
74
70
I/OOR
40
41
73
I/014l
A8l
A9l
A10l
RtWl
Vcc
42
A11l
43
44
A13l
52
53
GND
46
LBl
38
71
75
03
49
I/01l
48
SEMl
I/012l
I/015l
04
OEl
56
I/03l
51
54
I/OOl
68
72
05
59
I/06l
I/09l
I/013l
06
62
55
I/02l
65
69
07
58
I/04l
I/08l
I/011l
08
60
I/05l
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
20
A12R
16
22
A9R
18
eER
A13R
G
H
24
A7R
19
A11R
A5R
21
A10R
A8R
~
A
D
E
F
PIN NAM ES
J
K
L
2945 drw03
Index
(1,2)
Left Port
Right Port
CEl
CER
Names
Chip Enable
RlWl
RIWR
ReadlWrite Enable
OEl
OER
Output Enable
AOl-A13l
AOR - A13R
Address
I/OOl -I/015l
I/OOR - I/015R
Data Input/Output
SEMl
SEMR
Semaphore Enable
UBl
UBR
Upper Byte Select
LBl
LBR
Lower Byte Select
BUSYl
BUSYR
MIS
Busy Flag
Master or Slave Select
Vee
Power
GND
Ground
2945 tbl 01
NOTES:
1. All Vec pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.32
3
IDT70V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READIWRITE CONTROL
Inputs(1)
CE
Outputs
OE
UB
LB
SEM
VOS-15
VOO-7
X
X
X
X
X
H
High-Z
High-Z
H
H
H
High-Z
High-Z
Both Bytes Deselected: Power-Down
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
X
RIW
X
X
L
L
L
L
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
X
X
H
L
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAoUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
L
H
L
L
L
H
X
X
H
X
X
X
H
NOTE:
1. AOL -
Mode
Deselected: Power-Down
DATAoUT Read Lower Byte Only
DATAoUT DATAoUT Read Both Bytes
High-Z
High-Z
Outputs Disabled
2945 tbl 02
AI3L;e AOR -
AI3R
TRUTH TABLE: SEMAPHORE READIWRITE CONTROL
Outputs
Inputs
CE
RIW
OE
UB
LB
SEM
H
H
L
X
X
L
DATAoUT DATAoUT Read Data in Semaphore Flag
X
H
L
H
H
L
DATAoUT DATAoUT Read Data in Semaphore Flag
f
.:/
X
X
L
DATAIN
DATAIN
Write 1/00 into Semaphore Flag
X
H
H
L
DATAIN
DATAIN
Write 1/00 into Semaphore Flag
L
X
X
X
X
L
X
L
L
X
X
X
L
L
-
-
H
VOS-15
6.32
VOO-7
Mode
Not Allowed
Not Allowed
4
IDT70V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VrERM(2)
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
Terminal Voltage
with Respect
toGND
V
-0.5 to +4.6
Grade
Operating
Temperature
o to +70
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
TsrG
Storage
Temperature
-55 to +125
°C
DC Output
Current
Ambient
Temperature
GND
Vee
O°C to +70°C
OV
3.3V± 0.3
Military
TA
lOUT
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1)
Commercial Unit
Rating
Commercial
2945 tbl 05
50
RECOMMENDED DC OPERATING
CONDITIONS (2)
Symbol
mA
NOTE:
2945 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + O.3V for more than 25% of the cycle time
or 1 Ons maximum, and is limited to S. 20mA forthe period of VTERM ~ Vcc
+O.3V.
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
3.0
3.3
3.6
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.0
-
Vcc+0.3
V
VIL
Input Low Voltage
-0.3(1)
-
0.8
V
NOTE:
1. VIL~ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + O.3V.
2945 tbl 06
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions(2)
Max.
Unit
CIN
Input Capacitance
9
pF
Cour
Output
Capacitance
=3dV
Your =3dV
10
pF
Symbol
VIN
NOTE:
2945 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from OV to 3V or from 3V to OV.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vee =3.3V +
- O.3V)
IDT70V26S
Symbol
Parameter
Test Conditions
Min.
Max.
Ilul
Input Leakage Current
Vee = 3.6V, VIN = OV to Vee
-
10
IILOI
Output Leakage Current
CE = VIH, Your = OV to Vee
-
10
VOL
Output Low Voltage
IOL = 4mA
-
VOH
Output High Voltage
IOH = -4mA
2.4
IDT70V26L
Min.
Max.
Unit
-
5
IlA
5
IlA
0.4
-
0.4
V
-
2.4
-
V
2945 tbl 08
6.32
5
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vcc = 3.3V ± O.3V)
70V26X25
Symbol
Test
Condition
Parameter
Typ.(2)
Version
70V26X35
Max. Typ.(2)
70V26X55
Max. Typ.(2)
Max. Unit
lee
Dynamic Operating
Current
(Both Ports Active)
CE = Vll, Outputs Open
SEM =VIH
f = fMAX(3)
COM'L.
S
L
100
100
170
140
90
90
140
120
90
90
140
120
rnA
ISBl
Standby Current
(Both Ports - TTL
Level Inputs)
CER = CEl = VIH
SEMR = SEMl VIH
f = fMAX(3)
COM'L.
S
L
14
12
30
24
12
10
30
24
12
10
30
24
rnA
COM'L.
S
50
95
45
87
45
87
rnA
L
50
85
45
75
45
75
COM'L.
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
rnA
COM'L.
S
L
60
60
90
80
55
55
85
74
55
55
85
74
rnA
ISB2
=
=VIH(b)
Standby Current
CE'A' = Vil and CE"B'
(One Port -
Active Port Outputs Open,
TTL
Level Inputs)
f
=fMAX(3)
=SEMl =VIH
SEMR
ISB3
ISB4
Full Standby Current
(Both Ports - All
Both Ports CEl and
CER ~ Vee - 0.2V
CMOS Level Inputs)
VIN > Vee - 0.2V or
VIN 0.2V, f = d 4)
SEMR SEMl ~ Vee - 0.2V
Full Standby Current
(One Port-All
CE'A' < 0.2V and
CE'B' ~ Vee - 0.2V(5)
CMOS Level Inputs)
S
SEMR
=
=SEMl ~ Vee - 0.2V
VIN ~ Vee - 0.2V or VIN !:: 0.2V
Active Port Outputs Open
f = fMAX(3)
NOTES:
2945 tbl 09
1. "X" in part numbers indicates power rating (8 or L)
2. Vcc = 3.3V, TA = +2SoC, and are not production tested. IccDc = BarnA (Typ.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 11 tRC. and using "AC Test Conditions"
of input levels of GND to 3V.
4. f =a means no address or control lines change.
S. Port "A" may be either left or right port. Port "8" is the opposite from port "A".
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
GND to 3.0V
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
DATAoUT
BUSy----.----t---.
INT
347n
30pF
DATAoUT'---........--+-_
347n
5pF
See Figures 1 & 2
2945 tbltt
294Sdrw 04
Figure 1. AC Output Test Load
6.32
294SdrwOS
Figure 2. Output Test Load
(for hz, tHZ, twz, tow)
* Including scope and jig.
6
~
_
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
IDT70V26SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V26X25
Parameter
Symbol
Min.
Max.
IDT70V26X35
IDT70V26X55
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRG
Read Cycle Time
25
-
35
tAA
Address Access Time
Chip Enable Access Time
(3)
25
25
tABE
Byte Enable Access Time
(3)
-
35
35
35
55
-
tAGE
tAOE
Output Enable Access Time
-
-
20
tOH
Output Hold from Address Change
-
tLZ
Output Low-Z Time(l, 2)
3
3
-
3
3
-
tHZ
Output High-Z Time(l, 2)
-
15
-
tpu
Chip Enable to Power Up Time(2)
0
-
0
tPD
Chip Disable to Power Down Time(2)
-
tsop
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access Time
15
-
25
35
15
15
-
ns
ns
-
55
55
55
30
3
-
ns
-
ns
20
3
-
25
ns
-
0
-
ns
-
35
-
50
ns
15
-
15
-
ns
-
45
-
65
NOTES:
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE VIL and SEM VIH. To access semaphore, CE VIH and SEM VIL.
4. "X" in part numbers indicates power rating (S or L).
=
=
=
-
ns
ns
ns
ns
2945 tbl 12
=
TIMING OF POWER-UP POWER-DOWN
2945 drw 07
6.32
7
IDT70V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(S)
tRC
ADDR
J\.
W
\I
\.
\\\\
tAA(4)
-tACE(4)
/111
-tAOE(4)
\\\\
/111
-tABE(4)
UB, LB
\\\\
J'III
-tOH
i--tLZ(1)-t
X"
DATAoUT
1\
~\.
--l
VALID DATA(4)
tHZ(2)
I
BUSYOUT
\\\\\\\~
~
I
.... tBOO(3.4)
2945 drw06
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB. or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBoodelay is required only in cases where the opposite port is completing a write operation to the same address location. Forsimultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBOO.
5. SEM =VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(S)
Symbol
Parameter
IDT70V26X25
IDT70V26X35
IDT70V26X55
Min.
Min.
Min.
Max.
Max.
Max.
Unit
WRITE CYCLE
twc
Write Cycle Time
25
Chip Enable to End-of-Write(3)
20
-
35
tEW
20
-
tAW
Address Valid to End-of-Write
20
-
30
tAS
Address Set-up Time(3)
0
0
twp
Write Pulse Width
tWR
Write Recovery Time
0
tow
Data Valid to End-of-Write
15
-
tHZ
Output High-Z Time(1· 2)
-
15
-
20
-
25
tOH
Data Hold Time(4)
ns
0
-
0
-
0
-
twz
ns
Write Enable to Output in High-Z(1. 2)
-
15
-
20
-
25
ns
tow
Output Active from End-of-Write(1. 2.4)
0
0
5
tsps
SEM Flag Contention Window
5
-
ns
SEM Flag Write to Read Time
-
0
tSWRO
-
20
30
25
0
5
5
55
-
ns
45
-
ns
45
ns
0
-
30
-
ns
0
40
5
5
ns
ns
ns
ns
ns
NOTES:
2945 tbl13
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization. but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature, the actual tOH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
6.32
8
IDT70V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIWCONTROLLED TIMING(1,5,8)
twc
~~
ADDRESS
~~
1\
/\
tHZ(7)
}
tAW
CEor SEM
CE or SEM
(9)
-,'t..
1
I
-,'1
(9)
i4--tAS (6 1
tWp(2)
,
Rm
I
j'-
-~
f4-tw~
tow~
\I
(4)
DATAoUT
(3)
tWR
(4)
~
DATAIN ________________________________
\
J
~~----t-o-W----~'-.----t-OH-~-~r-------------------2945 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE, UB, LB CONTROLLED TIMING(1,5)
twc
~~
ADDRESS
~~
J~
J~
tAW
CEorSEM
(9)
UB or LB
Rm
-,~
-'~
14-- tAs(6)
tW~(3) I--
tEW(2)
_'t..
~r
(9)
~
\\\
---{F
_ _~J--I-
tow
DATAIN
tOH
2945 drw09
NOTES:
1. RiW or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a LOW CE and a LOW RiW for memory array writing cycle.
3. tWA is measured from the earlier of CE or RiW (or SEM or RIW) going HIGH to the end of write cycle.
4. Durin~is period, the 1/0 pins are in the output state and input signals mu~ not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the ANI LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE or RiW.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tow. If OE is HIGH during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. To access RAM, CE VIL and SEM VIH. To access semaphore, CE VIH and SEM VIL. tEW must be met for either condition.
=
=
=
6.32
=
9
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V26S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
Ao-A2
VALID ADDRESS
DATAo-------+------~-<
RAN------~------,
------~.-~ ~OE
2945 drw 10
NOTE:
1. CE
=H or UB & LB =H for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
--JX'-__________
AO"A"-A2"A'_'_____M_A_T_C_H
____
SIDE(2) "A"
SEM"A"
AO"B"-A2"B"
SIDE(2) "8"
NOTES:
1. DOR DOL VIL, CER CEL VIH, or both UB & LB VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from Rfiii'A· or SEM"A· going HIGH to RJW"s. or SEM"s· going HIGH.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
=
=
=
6.32
10
IDT70V26SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
Parameter
BUSY TIMING (MIS
IDT70V26X35
IDT70V26X55
Min.
Min.
Max.
Min.
Max.
Unit
ns
Max.
=VIH)
tSM
BUSY Access Time from Address Match
tSDA
BUSY Disable Time from Address Not Matched
tSAC
BUSY Access Time from Chip Enable LOW
tSDC
BUSY Disable Time from Chip Enable HIGH
tAps
Arbitration Priority Set-up Time l Vee - 0.2V or
VIN:S 0.2V, f = 0(4)
SEMR = SEML > Vee - 0.2V
Full Standby Current
(One Port-All
CE'A'S 0.2V and
CE"B' ~ Vee - 0.2V(5)
S
50
95
45
87
45
87
L
50
85
45
75
45
75
COM'L.
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
rnA
COM'L.
S
L
60
60
90
80
55
55
85
74
55
55
85
74
rnA
SEMR = SEML = VIH
ISB3
iSB4
CMOS Level Inputs)
SEMR = SEML ~ Vee - 0.2V
VIN ~ Vee - 0.2V or VIN S 0.2V
Active Port Outputs Open
f = fMAX(3)
NOTES:
3040 tbl 09
1. "X" in part numbers indicates power rating (S or L)
2. Vcc =3.3V, TA =+25°C, and are not production tested. ICCDC =80mA (Typ.)
3. At f =fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC. and using "AC Test Conditions"
of input levels of GND to 3V.
4. f =0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "S" is the opposite from port "A".
6.33
4
IDT70V261 S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 & 2
3040 tblll
DATAoUT
8U8Y--_-~--~
INT
34m
DATAoUT--_---...--.
30pF
34m
5pF
3040 drw 03
3040 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, twz, tow)
* Including scope and jig.
TIMING OF POWER-UP POWER-DOWN
3040 drw06
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V261 X25
Symbol
Parameter
Min.
Max.
IDT70V261 X35
IDT70V261X55
Min.
Min.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
-
35
-
55
-
ns
tM
Address Access Time
-
25
-
35
55
ns
tACE
Chip Enable Access Time
(3)
-
25
-
35
55
ns
tABE
Byte Enable Access Time
(3)
15
-
35
tAOE
Output Enable Access Time
-
15
-
20
-
tOH
Output Hold from Address Change
3
-
3
-
3
tLZ
Output Low-Z Time(1, 2)
3
-
3
-
tHZ
Output High-Z Time(1, 2)
-
15
-
tpu
Chip Enable to Power Up Time(2)
0
-
tPD
Chip Disable to Power Down Time(2)
-
tsop
Semaphore Flag Update Pulse (OE or SEM)
tSM
Semaphore Address Access Time
55
ns
30
ns
-
ns
3
20
-
25
ns
0
-
0
-
ns
25
-
35
-
50
ns
15
-
15
-
15
-
ns
-
35
-
45
-
65
ns
NOTES:
ns
3040 tbl12
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE =VIL and 8EM =VIH. To access semaphore, CE =VIH and 8EM =VIL.
4. "X" in part numbers indicates power rating (8 or L).
6.33
5
IDT70V261 SIL
HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
\V
W
I\,
II\.
\\\\
tAA(4)
-tACE(4)
/111
)/11,
-tAOE(4)
\\\\
-tABE(4)
UB, LB
\~\
/111
RiW
I---- tLZ (1)
DATAoUT
--tX'V
I\.
JI\.
-tOH
-1
lX)('J
VALID DATA(4)
~
tHZ(2)
BUSYOUT
\\\\\\\~
I
I-- tBDD(3, 4)
3040 drw 05
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM =VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT70V261X25
Symbol
Parameter
Min.
Max.
IDT70V261X35
Min.
Max.
IDT70V261X55
Min.
Max.
Unit
WRITE CYCLE
-
35
-
55
30
-
45
20
-
30
0
20
-
45
0
30
-
-
20
-
25
ns
twc
Write Cycle Time
25
tEW
Chip Enable to End-of-Write(3)
20
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
twp
Write Pulse Width
tWR
Write Recovery Time
0
tDW
Data Valid to End-of-Write
15
-
tHZ
Output High-Z Time(1, 2)
-
15
20
25
0
0
40
0
ns
ns
ns
ns
ns
ns
ns
tDH
Data Hold Time(4)
0
-
0
-
0
-
ns
twz
Write Enable to Output in High-z(1, 2)
-
15
-
20
-
25
ns
tow
Output Active from End-of-Write(l, 2, 4)
0
0
5
5
5
tsps
SEM Flag Contention Window
5
-
5
-
5
-
ns
SEM Flag Write to Read Time
-
0
tSWRD
-
ns
ns
NOTES:
3040 tbl13
1. Transition is measured ±200mV from low- or high-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tow values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tow.
5. "X" in part numbers indicates power rating (S or L).
6.33
6
IDT70V261SJL
HIGH·SPEED 16Kx 16 DUAL·PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1, RIW CONTROLLED TIMING(1,5,8)
twc
~~
1'1\.
ADDRESS
~~
I~
tHZ(7)
i
tAW
CEor SEM
CEorSEM
,'I
(9)
(9)
-.l
I
twp(2)
~tAS(6\
(3)
twR
-.~
~rr\
J
~twz~
DATAoUT
(4)
tow
\I
V
.II
~
.',
(4)
,
J
DATAIN----------------------------~~----------------~---r-----------------tow
tOH
3040 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE, UB, LB CONTROLLED TIMING(1,5)
twc
~~
1'1\.
ADDRESS
~t-
J\
tAW
CEorSEM
~r-
(9)
UB or LB
-J
J
\
f-
twR(3) I+-
tEW(2)
tAs(6)
~r
(9)
-,~
J
\
\\\
tow
DATAIN
tOH
-----IF""-----_~r-------II I •
3040 drw 08
NOTES:
1. ANi or CE or US and LS must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a LOW CE and a LOW RiW for memory array writing cycle.
3. tWR is measured from the earlier of CE or RiW (or SEM or RiW) going HIGH to the end of write cycle.
4. Durin~is period, the I/O pins are in the output state and input signals mu~ not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the ANI LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE or RNi.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ± 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during ANi controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tow. If OE is HIGH during an RiW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. To access RAM, CE =VIL and SEM =VIH. To access semaphore, CE =VIH and SEM =VIL. tEW must be met for either condition.
6.33
7
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
IDT70V261SJL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1}
Ao-A2
VALID ADDRESS
DATAo------~~------~~
RAN------~------~
---------------~.-~ ~OE
3040 drw09
NOTE:
1. CE H or UB & LB
=
=H for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4}
..JX'-_____________
AO"A"-A2"A'_'_____M
__
AT_C
__
H______
SIDE(2) "An
SEM"A"
AO"B"-A2"B"
SIDE(2) "8"
RiW"B"
NOTES:
1. DOR = DOL = Vll, CER = CEl = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port "An may be either left or right port. Port "Bn is the opposite from port "An.
3. This parameter is measured from RiW'A' or SEM"A' going HIGH to Rfiil's' or SEM''s' going HIGH.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.33
8
IDT70V261SIL
HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT70V261X25
Symbol
Parameter
BUSY TIMING (MIS
IDT70V261X55
Min.
Max.
Min.
Max.
Min.
Max.
Unit
-
25
25
25
25
-
35
35
35
35
-
45
45
45
45
ns
5
-
5
-
5
ns
-
25
-
-
35
-
55
ns
0
20
-
0
25
-
0
25
-
ns
-
ns
55
50
-
65
60
-
85
80
ns
=VIH)
tSM
BUSY Access Time from Address Match
tSOA
BUSY Disable Time from Address Not Matched
tSAC
BUSY Access Time from Chip Enable LOW
tsoc
tAps
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Timel")
tsoo
BUSY Disable to Valid Datal;j)
BUSY TIMING (MIS
IDT70V261X35
-
-
ns
ns
ns
=VIL)
tws
BUSY Input to Write (4 )
tWH
Write Hold After BUSV(5)
PORT-TO-PORT DELAY TIMING
twoo
Write Pulse to Data Delay(l)
-
tO~~
Write Data Valid to Read Data Delay(l)
-
ns
NOTES:
3040tbl14
1. Port-to·port delay through RAM cells from writing port to reading port, refer to "TIming Waveform of Write with Port-to-Port Read and BUSY (MIS = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBOO Is a calculated parameter and Is the greater of 0, twoo - twp (actual) or tODD - tow (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. ·X" In part numbers indicates power rating (S or L).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,5)
twc
)(
) (
MATCH
twp
~
"-
tow
) (
DATAIN"A
/
/
tOH
) (
VALID
tAps (1)
ADDR"B
)
(,
\
BUSY"B
MATCH
tBM
.......
tBOO
tBOA
-
-~
/' ~
twoo
)
DATAOUT"B
toDD
(3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for MIS = Vil (SLAVE).
2. eEL = CER = Vil
3. DE = Vil for the reading port.
4. If MIS =Vll(SLAVE), then BUSY is an input (BUSY'A' = VIH and BUSY'B' = "don~ care", for this example).
5. All timing Is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
6,33
k
VALIO
3040drw 11
9
IDT70V261S/L
HIGH·SPEED 16K x 16 DUAL·PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY
~---twP------.t
Rfij'A'
BUSY's'
AfirB"
~
'"
.k""""""---------""""""f'~
3
3040400ddrwrw 112
NOTES:
1. twH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking RIW's', until BUSY'S' goes High.
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CETIMING(1)
X
X
ADDR"A" _______
ADDRESSES MATCH
and "B"
, ' " ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J',
CE"A"
BUSY"B"
,"._ __
~p~:t---~-----------
l:=WAC=t_
3040 drw 13
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING(1)
ADDR'A'
ADDRESS "N"
ADDR'B'
MATCHING ADDRESS "N"
BUSY'B'
3040 drw 14
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port lOB" is the port opposite from port "A".
2. If tAPS is not satisfied, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
6,33
10
IDT70V261 SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT70V261X25
Symbol
Parameter
Min.
Max.
IDT70V261X35
IDT70V261X55
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
-
0
-
ns
Write Recovery Time
0
-
0
-
0
tWA
0
-
ns
tiNS
Interrupt Set Time
-
25
-
30
-
40
ns
tiNA
Interrupt Reset Time
-
30
-
35
-
45
ns
NOTE:
1. "X" in part numbers indicates power rating (S or L).
304Otb115
WAVEFORM OF INTERRUPT TIMING(1)
~------------------ twc------------------~
________________tl_N~_3_)~
INT"B"
.
~------------------------------------------3040drw 15
~------------------tRC----------------~
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
OE"B"
"NR")
~.--_____________________________________
3040drw 16
NOTES:
1. All timing is the same for left and right ports. Port "An may be either the left or right port. Port "B" is the port opposite from "An.
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
TRUTH TABLES
TRUTH TABLE I-INTERRUPT FLAG(1)
Right Port
Left Port
RlWL
CEL
L
L
X
3FFF
X
X
X
X
X
X
X
X
X
L
L
3FFE
OEL A13L-AoL INTL
CER
OER
X
X
X
X
X
X
L
L
3FFF
H(3)
L(3)
L
L
3FFE
X
Set Left INTL Flag
H(2)
X
X
X
X
X
X
Reset Left INTL Flag
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
A13R-AoR INTR
L(2)
X
Function
RIWR
Set Right INTR Flag
Reset Right INTR Flag
3040tb116
6.33
11
IDT70V261 S/L
HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE II-ADDRESS BUSY ARBITRATION
Inputs
CEL
CER
AOL-A13L
AOR-A13R
X
X
NO MATCH
Outputs
BUSYL(1) BUSYR(1)
H
Function
Normal
H
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
NOTES:
3040 tbl16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the
IDT70V261 are push pull, not open drain outputs. On slaves the BUSYx input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
=
TRUTH TABLE 111- EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1)
Functions
Do - Dt5 Left
Do - 015 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Right port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V261.
3040 tbl17
FUNCTIONAL DESCRIPTION
The IDT70V261 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V261 has an
automatic power down feature controlled by CEo The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (iNTL) is asserted when the right port
writes to memory location 3FFE (HEX), where a write is
defined as CE = Rm = VIL per the Truth Table. The left port
clears the interrupt through access of address location 3FFE
when CER = OER = VIL, Rm is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
writes to memory location 3FFF (HEX) and to clear the 3FFF
location 3FFF. The message (8 bits) at 3FFE or 3FFF is user-
defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random
access memory. Refer to Table 1 for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is "busy". The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for a"
applications. In some cases it may be useful to logica"y OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an i"egal or i"ogical
operation.lfthe write inhibitfunction of busy logic is notin slave
desirable, the busy logic can be disabled by placing the part
6.33
12
IDTIOV261 SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
in slave mode with the Mis pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 70V261 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V261 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V261 RAM the busy pin
is an output if the part is used as a master (M/S pin = H), and
I
MASTER
Dual Port
BAM..
CE
BUSY (L) BUSY (R)
T
SLAVE
Dual Port
BAM..
CE
MASTER
BUSY(L)
CE
BUSY (L) BUSY (R)
BUSY(L) BUSY(R)
1
SLAVE
Dual Port
BAM..
Cl
-
CE
BUSY(L) BUSY(R)
I
0
()
w
1
Dual Port
BAM..
-a:
r-w
Cl
BUSY(R)
3040 drw 17
Figure 3. Busy and chip enable routing for both width and depth
the busy pin is an input if the part used as a slave (MiS pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibitthe write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an access
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with either the Rm signal or the byte enables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
SEMAPHORES
The IDT70V261 is an extremely fast Dual-Port 16K x 16
CMOS Static RAM with an additional 8 address locations
dedicated to binary semaphore flags. These flags allow either
processor on the left or right side of the Dual-Port RAM to claim
a privilege over the other processor for functions defined ~y
the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READIWRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT70V261 contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V261 's hardware semaphores,
which provide a lockout mechanism without requiring complex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT70V261
does not use its semaphore flags to control any resources
through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be a
major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
"Token Passing Allocation." In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor has set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore's status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
6.33
13
IDT70V261 S/L
HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM WITH INTERRUPT
PRELIMINARY
COMMERCIAL TEMPERATURE RANGES
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT70V261 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore..!!ags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through address pins AO - A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other side
(see Table III). That semaphore can now only be modified by
the side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that
the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is ~hat
makes semaphore flags useful in interprocessor communIcations. (A thorough discussing on the use of this feature follows
shortly.) A zero written into the same location from the ot~er
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side's output register when that side's
semaphore select (SEM) and output enable (OE) signals .go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read ~
semaphore in a test loop must cause either signal (SEM or OE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the se~a
phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If th.e
semaphore is already in use, the semaphore request latch Will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over.the
resource in question. Meanwhile, if a processor on the nght
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READIWRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
R PORT
J......EQBI
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Do
Do
WRITE
WRITE
SEMAPHORE~
READ
____~~
~~
____- . SEMAPHORE
READ
3040 drw 18
Figure 4. IDT70V261 Semaphore Logic
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side's semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's
request latch. The second side's flag will now stay low u.nti.l i~s
semaphore request latch is written to a one. From this It IS
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If ~ne
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT70V261 's Dual.Port RAM. Say the 16K x 16 RAM was to be divided into two
8K x 16 blocks which were to be dedicated at anyone time to
servicing either the left or right port. Semaphore 0 could .be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the
6.33
14
IDT70V261 SIL
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT
indicator for the upper section of memory.
To take a resource, in this example the lower SK of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore o. If this task were successfully completed (a zero was read back rather than a one), the
left processor would assume control of the lower SK. Meanwhile the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
O. At this point, the software could choose to try and gain
control of the second SK section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap SK blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was "off-limits" to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory "WAIT' state is available on one or both sides. Once
a semaphore handshake has been performed, both processors can access their aSSigned RAM segments at full speed.
Another application is in the area of complex data structures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
~Blank
~--------------~ PF
L...--------------i
L...-______________--\
L.....-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I
Commercial (O°C to +70°C)
100-pin TQFP (PN100-1)
25 }
35
55
Speed in nanoseconds
S
L
Standard Power
Low Power
70V261 256K (16K x 16) 3.3V Dual-Port RAM w/ Interrupt
3040 drw 20
6.33
15
I
SUBSYSTEMS PRODUCTS
I
SUBSYSTEMS PRODUCTS
IDT Subsystems Division has the resources and experience to deliver the highest quality RAM module products.
IDT's combination of advanced design, assembly, and test
capabilities give customers the highest levels of quality,
service and performance. Product offerings include a number
JEDEC standards as well as specialized and application
specific RAM modules, including the world's highest performance and densest SRAMs, Dual-Port RAMs, and FIFOs.
Custom capabilities allow our customers to enjoy the benefits
of modules for high performance caches for the leading
microprocessors, multi-processor board level products and
multi-chip modules (MCMs).
IDT modules products provide a number of benefits to the
high performance system designer:
For system designers of high performance systems, modules solve a number of major problems through the benefits
they provide. The biggest benefit of modules is that they save
significant amounts of space for designers packing ever more
performance in less area by utilizing double sided surface
mount technology. In addition, decoupling capacitors are
mounted next to or undemeath the active memory components on the module, thus eliminating the need to consider
them or the real estate they consume.
Numerous module packaging options are available which
allow designers to trade-off board area, height and mechanical stability. Vertical mount module options (modules in which
mounted components are oriented in a vertical fashion) such
as Zig-zag In-Line packages (ZIPs), Single In-line Memory
Modules (SIMMs) and Dual In-line Memory Modules (DIMMs)
are ideal packages for applications requiring the highest
density. Many of these vertical mount modules are maximum
0.65 inch tall, which is well within the board space requirements for card rack type systems. Horizontal mount module
options include dual in-line packages (DIPs), and pin grid
array packages (PGAs). These modules are ideal for those
applications requiring the most in mechanical stability and
those with many 1/0 pins.
Design, manufacturing, and marketing often disagree on
the size of me.mory that their high performance system will
offer. By allowing the decision to made at manufacturing time
by having module solutions with different memory sizes and
common pinouts, the module user lets the market dictate
memory requirements. JEDEC has defined standards for
memory pinouts including 256Kx 32 and 1M x 32 SRAM in the
same 72-lead package which are among the most common
industry standard SRAM modules.
Testing is both a design and manufacturing problem that is
often an afterthought. By providing a pretested higher level
block, modules simplify the test issue for both design and
manufacturing. Since the module is tested using full parametric AC/DC guardbanded test pattems, designers are guaranteed a level of performance for a larger block of their system
versus a spec for an individual component. System board test
is simplified because a major block of memory has been fully
tested at the module level, thus simplifying the test method
and debug cycle at the board level.
Time to market is always a very important issue. Studies
have shown that a major portion of profits are made in the early
part of the product life cycle before competition drives down
prices to a level based on manufacturing costs rather than a
unique level of value. Integrating the high performance memory
into an module shortens the design cycle by simplifying board
design by leveraging off the module manufacturer's design
expertise. System board layout and the design cycle are
simplified because the number of input/outputs (1/Os) are
reduced by combining common component address, data,
control and power pins.
Module solutions help reduce hidden costs that are not
often taken into account. Since active and passive components necessary to realize an module solution are combined
onto a single substrate, the module user reduces inventory
and handling costs by combining a number of diverse components into one single component.
IDT Subsystems products provide an ideal solution for
system designers to integrate high performance RAM in order
to maximize density, performance and cost-effectiveness for
both commercial and military applications.
7.0
II
TABLE OF CONTENTS
SUBSYSTEMS PRODUCTS
SUBSYSTEMS PRODUCTS
PAGE
IDT7MP1015
32K x 32 CMOS Dual-Port Static Ram Module ......................................................... 7.1
IDT7MP1016
64K x 32 CMOS Dual-Port Static RAM Module .............................. '" .................. ,. .... 7.1
IDT7M1002
16K x 32 CMOS Dual-Port Static RAM Module......................................................... 7.2
IDT7M1014
4K x 36 SiCMOS Dual-Port Static RAM Module ....................................................... 7.3
IDT7M1024
4K x 36 SiCMOS Synchronous Dual-Port Static RAM Module ................................. 7.4
IDT7M1001
128K x 8 CMOS Dual-Port Static RAM Module......................................................... 7.5
IDT7M1003
64K x 8 CMOS Dual-Port Static RAM Module ........................................................... 7.5
IDT7M208
64K x 9 CMOS Parallel In-Out FIFO Module .. ... ........ ... ... ...... .............. ... ..... ... ... ........ 7.6
IDT7M209
128K x 9 CMOS Parallel In-Out FIFO Module.. ... ................. ........ ............................. 7.6
IDT7MP4120
1M x 32 CMOS Static RAM Module .......................................................................... 7.7
IDT7MP4145
256K x 32 CMOS Static RAM Module ....................................................................... 7.8
IDT7MP4045
256K x 32 SiCMOS/CMOS Static RAM Module ........................................................ 7.9
IDT7MP4095
128K x 32 CMOS Static RAM Module ....................................................................... 7.10
IDT7M4084
2M x 8 CMOS Static RAM Module ....................................... '" ........ '" ... ... ... ..... ... ... ... 7.11
IDT7MS4048
512K x 8 CMOS Static RAM Module ......................................................................... 7.12
IDT7M4048
512K x 8 CMOS Static RAM Module ......................................................................... 7.13
FIFO MODULES
IDT7MP2009
IDT7MP2010
IDT7M208
IDT7M207
32K x 18 CMOS Parallel In-Out FIFO Module .................................................. ;........
16K x 18 CMOS Parallel In-Out FIFO Module ............................................. ..............
64K x 9 Parallel In-Out FIFO Module ........................................................................
32K x 9 Parallel In-Out FIFO Module ........................................................................
7.0
7.12
7.12
7.13
7.13
2
t;)®
PRELIMINARY
IDT7MP1015
IDT7MP1016
32K x 32/64K x 32
CMOS DUAL-PORT
STATIC RAM MODULES
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• Pin compatible 1Mb/2Mb CMOS Dual-Port static RAM
modules
The IDT7MP101S17MP1016 are 32K x 32164K x 32 highspeed CMOS Dual-Port Static RAM modules constructed on
a low cost, multilayer FR-4 substrate using four IDT7007/08
Dual-Port Static RAMs (in slave mode) using TQFPs. The
IDT7MP101S17MP1016 modules are designed to be used as
stand-alone Dual-Port RAM providing two independent ports
with separate control, address, and I/O pins that permit
independent and asynchronous access for reads or writes to
any location in memory. Performance is enhanced by facilitating port-to-port communication via semaphore controls.
The IDT7MP1 01S17MP1 016 modules are packaged in 64position dual read-out DIMMs (Dual In-line Memory Modules)
with 128 leads and dimensions of 1.3S"xO.1S"x 1.0" (LxWxH).
The module is available with access times as fast as 2Sns.
All inputs and outputs of the IDT7MP1 01S/7MP1 016 are
TTL-compatible and operate from a single SV power supply.
Multiple GND pins and on-board decoupling capacitors ensure
maximum immunity from noise.
•
•
•
•
•
•
•
•
•
Fast access times: 2Sns
Fully asynchronous read/write operation from either port
Separate byte read/write signals for byte control
Separate upper/lower chip select for 16-bit operation
Full on-chip hardware support of semaphore signaling
between ports
High density surface mounted TQFP packages on a low
cost, multilayer FR-4 substrate
64-position dual read-out DIMM (Dual In-line Memory
Module) with 128 leads (socket information please
reference AMP PIN: 6-382617-4)
Single SV (±10%) power supply
Multiple GND pins and on-board decoupling capacitors
for maximum noise immunity
• Inputs/outputs directly TTL-compatible
FUNCTIONAL BLOCK DIAGRAM
6
L_I/O(O-7)
L_CSL#
L_OE#
L_SEM#
,
~
.,
_8~
L_RlW#(O)
L_I/O(8-15)
_8..,
"
16/
IDT7007108
32K164K x 8
.
..
..
..
L_I/O(16-23)
L_CSU#
8..,
"
8..,
.,
".
..
...
..
....
•
4
.
•
IDT7007108
32K164K x 8
•
~
IDT7007108
32K164Kx 8
•
8
~ ..
' -
R_I/O(O-7)
R_CSL#
R_OE#
R_SEM#
~
,--
8
IDT7007108
32K164K x 8
..
..
--
-
--
---
R_RlW#(1)
,--
8
~
R_I/O(16-23)
R_CSU#
R_RlW#(2)
,
8
--
~
R_I/O(24-31 )
4
3197 drw 01
The lOT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 1995
"'1995 Integrated Device Technology. Inc.
DSC 7128{-
7.1
I
IDT7MP1 01SnMP1 016
32K x 32164K x 32 CMOS DUAL-PORT STATIC RAM MODULE
PIN CONFIGURATION
Vee
L_A(O)
L_A(1)
L_A(2)
L_A(3)
L_A(4)
L_A(5)
L_A(6)
L_A(7)
GND
L_A(8)
L_A(9)
L_A(10)
L_A(11)
L_A(12)
L_A(13)
L_A(14)
L_A(15)
GND
L_RIW#(O)
L_RIW#(1)
L_RIW#(2)
L_RIW#(3)
L_CSL#
L_CSU#
L_SEM#
L_OE#
Vee
U/O(O)
U/O(1)
U/O(2)
U/O(3)
U/O(4)
U/O(5)
U/O(6)
U/O(7)
GND
U/O(8)
U/O(9)
U/O(10)
U/O(11)
U/O(12)
U/O(13)
U/O(14)
U/O(15)
GND
U/O(16)
U/O(17)
U/O(18)
U/O(19)
L_1I0(20)
U/O(21)
U/O(22)
U/O(23)
Vee
U/O(24)
U/O(25)
U/O(26)
U/O(27)
U/O(28)
U/O(29)
U/O(30)
L_1I0(31)
GND
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
PIN NAMES
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65
66
67
68
69
70
71
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Vee
R_A(O)
R_A(1)
R_A(2)
R_A(3)
R_A(4)
R_A(5)
R_A(6)
R_A(7)
GND
R_A(8)
R_A(9)
R_A(10)
R_A(11)
R_A(12)
R_A(13)
R_A(14)
R_A(15)
GND
R_RlW#(O)
R_RIW#(1)
R_RlW#(2)
R_RlW#(3)
R_CSL#
R_CSU#
R_SEM#
R_OE#
Description
Left Port
Right Port
L_A (0-15)
R_A (0-15)
Address Inputs
L I/O (0-31)
R I/O (0-31)
Data Inputs/Outputs
L RIW# (0-3)
R RIW# (0-3)
ReadlWrite Enables
L CSL#
R CSL#
Chip Select, Lower 16-bits
L CSU#
R CSU#
Chip Select, Upper 16-bits
L OE#
R OE#
Output Enable
L_SEM#
R_SEM#
Semaphore Control
No Connect
N.C.
Vee
Power
GND
Ground
3197tbiOl
CAPACITANCE(1)
Vee
RJ/O(O)
R_I/O(1)
R_I/O(2)
R_I/O(3)
R_I/O(4)
R_I/O(5)
R_1I0(6)
R_I/O(7)
GND
R_I/O(8)
R_1I0(9)
RJ/O(10)
R_I/O(11)
R_I/O(12)
R_1I0(13)
RJ/O(14)
R_I/O(15)
GND
R_I/O(16)
R_I/O(17)
R_I/O(18)
R_1I0(19)
R_1I0(20)
R_I/O(21)
R_I/O(22)
R_I/O(23)
(TA
= +25°C, f = 1.0MHz)
Symbol
Parameter
Condition
Max.
Unit
CIN(1)
Input Capacitance
(CS, OE, SEM, Address)
VIN= OV
40
pF
CIN(2)
Input Capacitance
(Rm, I/O)
VIN= OV
12
pF
COUT
Output Capacitance
VOUT= OV
12
pF
(1/0)
NOTE:
3197tbl02
1. This parameter is guaranteed by design but not tested.
ABSOLUTE MAXIMUM RATINGS(l)
Symbol
Rating
Commerical Unit
VTERM
Terminal Voltage with Respect
to GND
TA
Operating Temperature
Vee
TSIAS
Temperature Under Bias
R_I/O(24)
R_I/O(25)
R_I/O(26)
R_I/O(27)
RJ/O(28)
R_I/O(29)
R_I/O(30)
R_I/O(31)
GND
TSTG
Storage Temperature
-55 to +125
DC
lOUT
DC Output Current
50
mA
DIMM
TOP VIEW
NOTE:
-0.5 to +7.0
V
o to +70
DC
-55 to +125
DC
3197tbl03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation ofthe device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
3197 drw 02
NOTE:
1. Pin numbers 18 and 82 are N.C. for the IDT7MP1015.
7.1
2
IDT7MP101snMP1016
32K x 32164K x 32 CMOS DUAL-PORT STATIC RAM MODULE
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Min.
Typ.
Vee
Supply Voltage
Parameter
4.5
5.0
Max. Unit
5.5
V
Grade
GND
Supply Voltage
0
0
0
V
Commercial
VIH
Input High Voltage
2.2
-
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
Ambient
Temperature
O°C to +70°C
GND
Vee
OV
5.0V± 10%
3197 tbl 05
3197 tbl 04
1. VIL ~ -3.0V for pulse width less than 20ns
DC ELECTRICAL CHARACTERISTICS
(Vee
=5V ± 10%, TA = O°C to +70°C)
Symbol
Parameter
Test Conditions
Min.
Max.
Units
lIul
Input Leakage
(Address & Control)
Vee = Max.
VIN = GND to Vee
-
40
IlA
Ilul
Input Leakage
(Data)
Vee =Max.
VIN = GND to Vee
-
10
JlA
IILOI
Output Leakage
(Data)
Vee = Max.
CS ~ VIH, VOUT
-
10
IlA
VOL
Output Low
Voltage
-
0.4
V
VOH
Output High
Voltage
Vee
2.4
-
V
lee2
Dynamic Operating Current
(Both Ports Active)
Vee = Max., CS ~ VIL, SEM
Outputs Open, f =fMAX
IS8
Standby Supply Current
(Both Ports Inactive)
IS81
IS82
=GND to Vee
Vee = Min. IOL =4mA
=Min, IOH =-4mA
= Don't Care
-
1720
mA
Vee =Max., L_CS and R_CS ~ VIH
Outputs Open, f =fMAX
-
340
mA
Standby Suppy Current
(One Port Inactive)
Vee = Max., L_CS or R_CS:2! VIH
Outputs Open, f =fMAX
-
1200
mA
Full Standby Supply Current
(Both Ports Inactive)
L_CS and R_CS ~ Vee - 0.2V
VIN > Vee - 0.2V or < 0.2V
L SEM and R SEM ~ Vee - 0.2V
-
72
mA
I
II
3197 tbl 06
+SV
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
1250Q
DATAouT
77SQ
See Figure 1
30pF*
3197 tbl 07
3197 drw 03
Figure 1. Output Load
(For tCHZ, tCll, tOHZ, tOLZ, tWHZ, toW)
*Including scope and jig capacitances.
7.1
3
IDT7MP1 01517MP1 016
32K x 32164K x 32 CMOS DUAL-PORT STATIC RAM MODULE
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Vce
=5V ± 10%, TA =O°C to +70°C)
-25
Symbol
Parameter
Min.
-30
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
25
-
30
-
ns
tM
Address Access Time
-
25
25
30
30
ns
15
-
17
ns
-
3
3
-
ns
-
ns
tACS(2)
tOE
Chip Select Access Time
Output Enable Access Time
ns
tOH
tLZ(l)
Output Hold from Address Change
Output to Low-Z
3
3
tHZ(l)
Output to High-Z
-
15
-
15
ns
tPU(l)
Chip Select to Power Up Time
0
-
0
-
ns
tpO(l)
Chip Deselect to Power Up Time
-
50
-
50
ns
tsop
Sem. Flag Update Pulse (OE or SEM)
15
-
15
-
ns
25
20
20
30
25
25
-
ns
-
ns
-
ns
ns
0
-
ns
ns
Write Cycle
tAW
Address Valid to End-of-Write
tAS
Address Set-Up Time
twp
Write Pulse Width
0
20
tWR
Write Recovery Time
0
tow
Data Valid to End-of-Write
18
tOH
Data Hold Time
0
-
tHZ(l)
Output to High-Z
-
15
-
15
tow(1)
Output Active from End-of-Write
tSWRO
SEM Flag Write to Read Time
-
SEM Flag Contention Window
-
0
10
tsps
0
10
10
10
-
twc
tcW(2)
Write Cycle Time
Chip Select to End-of-Write
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM, es::;; VIL and SEM ~ VIH. To access semaphore,
0
25
0
22
ns
ns
ns
ns
ns
ns
3197 tbl 08
es ~ VIH and SEM ::;; VIL.
7.1
4
IDT7MP101snMP1016
32K x 32164K x 32 CMOS DUAL-PORT STATIC RAM MODULE
TIMING WAVEFORM OF READ
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
CYCLES(1,3,S)
~------------------ tRC--------------------~
ADDR
I-tAOC<4) - - . . . - t
-----""T""""r"""~1
DATA OUT
VALID DATA
~-~r-t HZ(2)._ _~
BUSY OUT
tBDD(3,4)
3197dM04
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tsoo delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read
operations BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tsoo.
5. SEM HIGH.
=
TIMING WAVEFORM OF WRITE CYCLE NO.1 (RIWCONTROLLED TIMING)(1,2,4)
ADDRESS
't
twc
\.
J
I
!HZ
if
lAw
J
twp(2)
i-IAS(6
RNV
tWR(7)
.J
J
~
I---tow
I-twz-J
DATAoUT
DATAIN
(4)
"
~
V
(4)
1\
----------------rK. .________---..1J---------tow
III· ...
toH
3197dMl5
7.1
S
IDT7MP1 01SnMP1 016
32K x 32164K x 32 CMOS DUAL-PORT STATIC RAM MODULE
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 4)
twe
I
-J\
ADDRESS
J~
tAW
... tA~6)
Rm
DATAIN
\I
}'twR(7)..-
tEW(2)
\\ \
-----------------tE
tDW
.-1 ...
911----
to
319i1:JMl6
NOTES:
1. RiW must be HIGH during all address transitions.
2. A write occurs during the overlap (twp or tEW) of a LOW es and a LOW RiW for memory array writing cycle.
3. tWR is measured from the earlier of es or RiW (or SEM or RiW) going HIGH to the end of write cycle.
4. During this period, the 110 pins are in the output state and input signals must not be applied.
5. If the es or SEM low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable signal is asserted last, es, or RiW.
7. Timing depends on which enable signal is de-asserted first, es, or RiW.
8. If OE is LOW during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 110 drivers to
turn off and data to be placed on the bus for the required tow. If OE is HIGH during an RiW controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified twP.
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE, EITHER SIDE(1)
DATAo---;--~~
RiW
---+--.....
3197drw07
NOTE:
1. es
=H for the duration of the above timing (both write and read cycle).
7.1
6
IDT7MP1 01 5nMP1 016
32K x 32164K x 32 CMOS DUAL-PORT STATIC RAM MODULE
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1. 3. 4)
SIDE(2) "A"
{:~~~~~~_MA_T~C~H~
__
SEMA
SIDE(2) "S"
{A~:
SEMB
.JX______
__
-----
_______
------319i1:lMlB
NOTES:
1. DOR DOL L. (L_ CS R_ CS) H, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "S" is the opposite port from "A".
3. This parameter is measured from RlWA or SEMA going HIGH to RlWB or SEMB going HIGH.
4. If tsps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
=
=
TRUTH TABLE I: Non-Contention ReadlWrite Control(1)
Inputs
CS
RIW
H
L
Outputs
110
Mode
SEM
X
X
H
High-Z
L
X
H
Data_IN
Write
L
H
L
H
Data_OUT
Read
X
X
H
X
High-Z
NOTE:
II
Description
OE
Deselected or Power Down
I
Outputs Disabled
3197 tbl 09
*
1. The conditions for non-contention are L_A (0-13) R_A (0-13).
2.
denotes a LOW to HIGH waveform transition.
f
TRUTH TABLE II: Semaphore ReadlWrite Control
Inputs(2)
CS
RIW
H
H
L
H
f
X
Outputs
OE
SEM
110
L
L
Data OUT
X
L
Data IN
X
L
-
Mode
Description
Read Data IN Semaphore Flag
Write Data IN (0, 8,16,24)
NotAl/owed
3197 tbll0
DEPTHIWIDTH EXPANSION AND SEMAPHORES
For more details regarding depth/width expansion or semaphore operations, please consult the IDT7007 or IDT7008 data sheets.
7.1
7
IDT1MP1 01SnMP1 016
32K x 32164K x 32 CMOS DUAL-PORT STATIC RAM MODULE
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
It
+
1.0001
MAX~
.~
240
0.260
3.574
3.594
---------;-:~-:-~~
D BD
0.250
TYP.
tiN 1
~
~
I
0.397
00403
TYP.
0.070
0.090
0.045
0.055
SIDE VIEW
FRONT VIEW
o
o
0.060 R
0.064
BACK VIEW
3197 drw 09
ORDERING INFORMATION
IDT
XXXX
A
Device
Type
Power
999
Speed
A
A
Package
Process!
Temperature
Range
~B~NK
~----------~
~
M
_ _ _ _ _ _ _ _ _--I 25
30
~------------------~S
~
_______________________~ 7MP1015
7MP1016
Commercial (O°C to +70°C)
64-position dual read-out DIMM (Dual In-line
Memory Module)
}
Speed in Nanoseconds
Standard Power
32K x 32 CMOS Dual-Port Static RAM Module
64K x 32 CMOS Dual-Port Static RAM Module
3197 drw 10
7.1
8
G®
16Kx32 CMOS
DUAL-PORT STATIC RAM
MODULE
IDT7M1002
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High-density 512K CMOS Dual-Port RAM module
• Fast access times
-Commercial: 30, 35ns
-Military: 40, 45ns
• Fully asynchronous read/write operation from either port
• Easy to expand data bus width to 64 bits or more using
the Master/Slave function
• Separate byte read/write signals for byte control
• On-chip port arbitration logic
• INT flag for port-to-port communication
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted fine pitch (25 mil) LCC packages allow
through-hole module to fit into 121 pin PGA footprint
• Single 5V (±1 O%) power supply
• Inputs/outputs directly TTL-compatible
The IDT7M1 002 is a 16K x 32 high-speed CMOS Dual-Port
Static RAM Module constructed on a co-fired ceramic substrate using four 16K x 8 (IDT7006) Dual-Port Static RAMs in
surface-mounted LCC packages. The IDT7M1 002 module is
designed to be used as stand-alone 512K Dual-Port RAM or
as a combination Master/Slave Dual-Port RAM for 64-bit or
more word width systems. Using the IDT Master/Slave approach in such system applications results in full-speed, errorfree operation without the need for additional discrete logic.
The module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via additional control signals SEM
and INT.
The IDT7M1002 module is packaged in a ceramic 121 pin
PGA (Pin Grid Array}1.35 inches on a side. Maximum access
times as fast as 30ns are available over the commercial
temperature range and 40ns over the military temperature
range.
AIiIDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.
PIN CONFIGURATION
2
3
4
7
6
8
9
10
11
12
13
A
U/0(24)
U/0(2S)
L_1/0(28)
L_1/0(30)
u5§
U5E
U~iW(3)
Rj)E
R_CS
R_1/0(30)
R_I/O(28)
R_1/0(2S)
R_1/0(24)
B
U/0(23)
L_1/0(2S)
L_1/0(27)
U/0(29)
U/0(31)
L_A(O)
L_R/W(4)
R_A(O)
R_1/0(31)
R_1/0(29)
R_I/O(27)
R_1/0(2S)
R_1/0(23)
e
L_1/0(21)
U/0(22)
vec
L_A(3)
L_A(2)
L_A(l)
GND
R_A(l)
R_A(2)
R_A(3)
R_1/0(21)
D
L_I/O(19)
U/0(20)
L_A(4)
E
U/0(17)
U/0(18)
L_A(S)
F
L_SEM
L_I/O(lS)
L_A(S)
G
L_BUSY
L_INT
GND
GND
PGA
TOP VIEW
GND
R_1/0(22)
R_A(4)
R_1/0(20)
R_1/0(19)
R_A(S)
R_1/0(18)
R_I/O(17)
R_A(S)
R_I/O(lS)
R_SEM
GND
R_INT
R_BUSY
L RIW(l)
L_R!W(2)
L_A(7)
R_A(7)
R
ANi (2)
R_RJW(l)
L_I/O(lS)
U/0(14)
L_A(8)
R_A(8)
R_1/0(14)
R_1/0(1S)
L 1/0(13)
L 1/0(12)
L A(9)
R A(9)
R 1/0(12)
R 1/0(13)
K
U/O(ll)
MIS
GND
L_A(10)
GND
R_I/O(ll)
L
U/0(10)
U/0(8)
L_I/O(S)
L_1/0(4)
R_1/0(10)
M
U/0(9)
U/0(7)
U/O(S)
L_1/0(3)
H
R~(12)
R_A(ll)
R_A(10)
vee
R_ANi (4)
R_A(13)
R_1/0(2)
R_1/0(4)
R_I/O(S)
R_1/0(8)
R_RiW(3)
R_I/O(O)
R_I/O(l)
R_1/0(3)
R_I/O(S)
R_I/O(7)
L_A(12)
GND
L_1/0(2)
L_A(13)
U/O(l)
U/O(O)
L_A(11)
R_1/0(9)
2795 drwOl
The lOT logo is a registered trademark of Integraled Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101995 Integrated Device Technology, Inc.
MARCH 1995
DSC-706414
7.2
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
M/S
I
----:--
r---
L_I/0(0-7)
R_I/0(0-7)
IDTlO06
16Kx8
L_CS
L_OE
L-SEM
R_CS
R_OE
R-SEM
R-INT
(ARBITRATION
LOGIC)
L-INT
L-BUSY
L_RIW (0)
I
R-BUSY
R_RIW(O)
I
)
IDTlO06
16K x 8
~ I--
It)
(ARBITRATION
I-- r--<
LOGIC)
I
I
t-- ~
)
IDTlO06
16Kx 8
~ I--
~
)
(ARBITRATION
I-- ~It
LOGIC)
t--jt
I
I
)
IDT7006
16Kx8
' - - I-'--
(ARBITRATION I-- ~
LOGIC)
I-I
I
PIN NAMES
2795 drw 02
Left Port
Right Port
L A (0-13)
R A (0-13)
Address Inputs
L I/O (0-31)
R I/O (0-31)
Data Inputs/Outputs
L R/W(1-4)
R R/w(1-4)
ReadlWrite Enables
L CS
R CS
Chip Select
L_OE
R_OE
Output Enable
L BUSY
R BUSY
Busy Flag
LINT
R INT
Interrupt Flag
L SEM
R SEM
Semaphore Control
M/S
Description
Master/Slave Control
Vee
Power
GND
Ground
2795 tbl 01
7.2
2
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commerical
Military
Unit
VTERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
VCC
Military
-55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
Commercial
2795 tbl 03
RECOMMENDED DC
OPERATING CONDITIONS
Parameter
Min.
Typ.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
Symbol
2795 tbl 02
NOTE:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Max. Unit
V
2795 tbl 04
NOTE:
1. VIL ~ -3.0V for pulse width less than 20ns
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA
Symbol
=-55°C to +125°C or O°C to +70°C)
Parameter
Max.
Units
IIul
Input Leakage
(Address & Control)
Vee = Max.
VIN =GND to Vee
Test Conditions
Min.
-
40
IlA
IIul
Input Leakage
(Data)
Vee = Max.
VIN =GND to Vee
-
10
IlA
IILOI
Output Leakage
(Data)
Vee =Max.
CS ~ VIH, VOUT = GND to Vee
-
10
IlA
VOL
Output Low
Vee =Min. IOL =4mA
Voltage
-
0.4
V
VOH
Output High
Voltage
Vee
2.4
-
V
=Min, IOH =-4mA
II
2795 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, T A = -55°C to + 125°C or O°C to +70°C)
Commercial
Symbol
Parameter
Test Conditions
lee2
Dynamic Operating Current
(Both Ports Active)
Vee =Max., CS:::; VIL, SEM
Outputs Open, f =fMAX
19B
Standby Supply Current
(Both Ports Inactive)
ISB1
ISB2
=Don't Care
Min.
Max.
Military
Min.
Max.
Units
-
1360
-
1600
mA
Vee = Max., L_CS and R_CS ~ VIH
Outputs Open, f =fMAX
-
280
-
340
mA
Standby Suppy Current
(One Port Inactive)
Vee =Max., L_CS or R_CS ~ VIH
Outputs Open, f =fMAX
-
1000
-
1160
rnA
Full Standby Supply Current
(Both Ports Inactive)
L_CS and R_CS ~ Vee - 0.2V
VIN > Vee - 0.2V or < 0.2V
L_SEM and R_SEM ~ Vee - 0.2V
-
60
-
120
mA
2795 tbl 06
7.2
3
I
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
+5V
CAPACITANCE(l) (TA = +25°e, f = 1.0MHz)
Symbol
Parameter
Max.
Unit
CIN(1)
Input Capacitance
(CS, OE, SEM, Address)
VIN
=OV
40
pF
CIN(2)
Input Capacitance
(RiW, 1/0, INl)
VIN= OV
12
pF
CIN(3)
Input Capacitance
(BUSY, MiS)
VIN = OV
45
pF
COUT
Output Capacitance
(1/0)
VOUT= OV
12
pF
Condition
4800
30pF*
2550
"Including scope and jig capacitances.
2795 tbl 07
NOTE:
2795 drw 03
Figure 1. Output Load
1. This parameter is guaranteed by design but not tested.
+5V
AC TEST CONDITIONS
Input Pulse Levels
4800
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
DATAoUT
1.5V
5pF*
2550
See Figures 1 and 2
2795 tbl 08
*Including scope and jig capacitances.
2795 drw 04
Figure 2. Output Load
(For tCHz, tCLZ, tOHZ, tOLZ, tWHZ, toW)
AC ELECTRICAL CHARACTERISTICS
(Vcc
=5V ± 10%, TA =-55°C to +125°e or ooe to +70°C)
30
Symbol
Parameter
Min.
7M1002SxxG
-35
Max.
Min.
7M1002SxxGB
-45
-40
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
30
-
35
-
40
-
45
-
ns
tM
Address Access Time
30
-
45
ns
Chip Select Access Time
40
-
45
ns
Output Enable Access Time
-
40
tOE
-
35
tACS(2)
-
22
-
25
ns
tOH
tLZ(1)
Output Hold from Address Change
3
-
3
3
-
5
-
ns
3
-
3
Output to Low-Z
-
tHZ(1)
Output to High-Z
-
15
15
-
17
-
20
ns
tPU(l)
Chip Select to Power Up Time
0
-
0
-
0
-
0
-
ns
tPD(1)
Chip Deselect to Power Up Time
-
50
-
50
-
50
-
50
ns
tsop
Sem. Flag Update Pulse (OE or SEM)
15
-
15
-
15
-
15
-
ns
35
40
-
0
-
35
-
ns
0
-
45
35
30
-
30
17
3
3
-
35
20
ns
Write Cycle
twc
tcW(2)
Write Cycle Time
30
Chip Select to End-of-Write
25
tAW
Address Valid to End-of-Write
25
tAS
Address Set-Up Time
0
-
twp
Write Pulse Width
25
-
30
tWR
Write Recovery Time
0
-
0
(Continued on next page)
7.2
30
35
0
40
40
0
35
0
ns
ns
ns
ns
ns
2795 tbl 09
4
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc
=5V ± 10%, TA =55°C to +125°C or O°C to +70°C)
7M1002SxxG
30
Symbol
Parameter
Min.
7M1002SxxGB
-35
Max.
-40
Min.
Max.
Min.
-45
Max.
Min.
Max.
Unit
Write Cycle (continued)
tow
Data Valid to End-of-Write
22
-
25
-
ns
0
0
-
25
Data Hold Time
-
25
tOH
0
-
0
-
ns
tHZ(l)
Output to High-Z
-
15
-
15
-
17
-
20
ns
tow(1)
Output Active from End-of-Write
0
0
-
0
10
10
-
10
tsps
SEM Flag Contention Window
10
-
10
-
10
-
ns
SEM Flag Write to Read Time
-
0
tSWAO
-
35
ns
30
ns
10
10
ns
ns
Busy Cycle-Master Mode(3)
tSM
BUSY Access Time to Address
-
35
BUSY Disable Time to Address
-
30
tSOA
25
-
30
tSAC
BUSY Access Time to Chip Select
-
25
30
tsoe
twOO(5)
BUSY Disable Time to Chip Deselect
-
25
25
55
-
-
60
40
-
45
Write Pulse to Data Delay
tOOD
tAPS(6)
Write Data Valid to Read Data Delay
Arbitration Priority Set-Up Time
5
tsoo
BUSY Disable to Valid Time
-
NOTE 9
-
5
-
NOTE 9
30
ns
25
-
25
ns
-
65
-
70
ns
-
50
-
55
ns
-
ns
5
-
35
30
30
NOTE 9
5
-
NOTE 9
ns
Busy Cycle-Slave Mode (4)
tWs(7)
Write to BUSY Input
0
-
0
-
0
-
ns
Write Hold after BUSY
25
-
25
-
0
tWH(8)
25
-
25
-
ns
twOO(5)
Write Pulse to Data Delay
-
55
-
60
-
65
-
70
ns
-
ns
35
ns
Interrupt Timing
tAS
Address Set-Up Time
0
-
0
-
0
Write Recovery Time
0
-
0
tWA
0
-
0
-
0
tiNS
Interrupt Set Time
-
25
-
30
Interrupt Reset Time
-
25
-
30
-
32
tiNA
-
32
35
ns
ns
2795 tbl 10
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
This parameter is guaranteed by design but not tested.
To access RAM, CS::; VILand SEM 2: VIH. To access semaphore, CS 2: VIH and SEM::; VIL.
When the module is being used in the Master Mode (MIS 2: VIH).
When the module is being used in the Slave Mode (MIS::; VIL).
Port-to-Port delay through the RAM cells from the writing port to the reading port.
To ensure that the earlier of the two ports wins.
To ensure that the write cycle is inhibited during contention.
To ensure that a write cycle is completed after contention.
tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tODD - tWP (actual).
7.2
5
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE(1,2,4)
~---------------------tRC
ADDRESS
DATAoUT
DATA VALID
2795 drw 05
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1,3,5)
tACE
CS
tCHZ (6)
tsop
OE
toLZ
tOHZ
(6)
(6)
DATA VALID
DATAoUT
tClZ
tPD
(6)
(6)
Icc
50%
50%
CURRENT
IS8
I--tpu
(6)
2795 drw 06
NOTES:
1. RJW is HIGH for Read Cycles
2. Device is continuously enabled CS :::; VIL. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition LOW.
4. OE:::;VIL
5. To access RAM, CS:::; VIL and SEM ;?! VIH. To access semaphore, CS;?! VIH and SEM :::; VIL.
6. This parameter is guaranteed by design but not tested.
7.2
6
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (RIWCONTROLLED TIMING)(1,2,4)
II
ADDRESS
II
twe
.~ ~
~
-- tAs
~
RlW
"7
..
twp (2)
(6) - - ..
~
"7
L
~
/'
---tow
DATAIN
L
_tOW(9)_~
"
----------------------------~~ --(4)
~
tWR (7)
twHZ (9)
DATAoUT
~teH~
7
...
tAw
II
~
K
)
-tOH
-:>~I------------
____
DA_T_A_V_AL_ID____
2795 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2,4)
..
~~
..
ADDRESS
.~ ~
R/W
~
..
7'
~
..
twp (2)
-----------------------------~~
--tow
DATAIN
•
tAW
~
tAS (6)
..
twc
twR (7)
-tOH
-:>~I-----------
____
DA_T_A_V_AL_ID____
2795 drw 08
NOTES:
1. RiW must be HIGH during all address transitions.
2. A write occurs during the overlap (twp) of a LOW es and a LOW RI'iJ.
3. twR is measured from the earlier of CS or RiW (or SEM or RiW) going HIGH to the end of write cycle.
4. During this period, the 1/0 pins are in the output state and input signals must be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the pjiiJ low transition, the outputs remain in the high impedance state.
6. Timing depends on which enable Signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is LOW during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 1/0 drivers to
tum off and data to be placed on the bus for the required tow. If OE is HIGH during an RiW controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified twP.
7.2
7
I
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE, EITHER SIDE(1)
..
t-----tAA
tAW
Ao-A2
DATAo
R/W
- - - - . I - - tAOE
--
--
1......
----
WRITE CYCLE - - - - - ~---- READ CYCLE
2795 drw 09
NOTE:
1. CS;:: VIH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
AOA-A2A
MATCH
~~______________________________
SIDE(2) "A"
AOB-A2B
MATCH
(2)
SIDE
"8"
R/WB
2795 drw 10
NOTES:
1. DaR DOL:5 VIL. (L_ CS R_ CS) ;:: VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "8" is the opposite port from "A".
3. This parameter is measured from RfiiiiA or SEMA going HIGH to RlWB or SEMB going HIGH.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
7.2
8
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY(M/S~ VIH)(2)
twe
ADDRR
~E
~ fE
MATCH
twp
~
7 ~
'"
-tDW--
~~
DATAINR
tAPS (1)
VALID
I-
I
7 ~~
ADDRL
tDH
~ ~.
tSDA
--
MATCH
//
tSDD
l_ -
7
tDDD (3)
L
.
~
DATAoUTL
..
tWDD
I
E
2795 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins.
2. (L_ CS R_ CS) $; VIL
3. OE $; VIL for the reading port.
=
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY (M/S~ VIH)(1,2)
I
ADDRR
RlWR
*
twe
~E
MATCH
twp
~
s::I-tDW
~~
DATAINR
--
"7
L
VALID
tDH
~~
MATCH
ADDRL
tDDD
I
DATAoUTL
twDD
I
..
~
..
E
2795 drw 12
NOTES:
1. BUSY input equals HIGH for the writing port.
2. (L_ CS R_ CS) $; VIL
=
7.2
9
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (MIS::; VIL)
twp
DATAINR
2795 drw 13
TIMING WAVEFORM OF BUSY ARBITRATION (CS CONTROLLED TIMING)(1)
X
ADDR"A"~
AND "8" ~_ _ _ _ _ _ _ _ _
AD_D_R_E_S_S_M_AT_C_H_ _ _ _ _ _ _ _ _ _ _--".
CS"A"
~tAPS
(2)
......._ __
tBDC
CS "8"
tBAC
8USY"8"
2795 drw 14
TIMING WAVEFORM OF BUSY ARBITRATION (CONTROLLED BY ADDRESS MATCH TIMING(1)
ADDR "A"
ADDR"8"
ADDRESS "N"
MATCHING ADDRESS "N"
~_tBDA~
_--,---tBA_A
8USY"8"
2795 drw 15
NOTES:
1. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. If tAps is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
7.2
10
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT CYCLE(1)
~------------------------twc
INTERRUPT SET ADDRESS (2)
ADDR "A"
RIW 1"A"
IINS (3)
INT"S"
=t____________________________
2795 drw 16
ADDR"8"
~~~~~~~~~~~~~IN~T~E~R~R~U~P~T~~~~~A~R~A~DD~R~E~S~~2~)~~~~~~
~tAS(3)
CE"S"
OE "S"
IINR (3)
~---------------------
INT "S"
2795 drw 17
NOTES:
1. All timing IS the same for left and right ports. Port "A" may be either the left or right port. Port "8" is the port opposite from "A".
2. See Interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
II
TRUTH TABLE I: Non-Contention ReadlWrite Control(1)
Outputs
Inputs
CS
RIW
H
L
L
X
1/0
Mode
Description
OE
SEM
X
X
H
High-Z
Deselected or Power Down
L
X
H
Data In
Write
H
L
H
Data OUT
Read
X
H
X
High-Z
Outputs Disabled
2795 tbl 13
NOTE:
1. The conditions for non-contention are L_A (0-13) # R_A (0-13).
2. f
denotes a LOW to HIGH waveform transition.
TRUTH TABLE II: Semaphore ReadlWrite Control
Inputs(2)
Outputs
CS
RIW
OE
SEM
1/0
H
H
L
L
Data OUT
X
L
Data_IN
X
L
~
H
L
f
X
Mode
Description
Read Data in Semaphore Flag
Write Data_IN (0, 8, 16, 24)
Not Allowed
2795 tbl 14
7.2
11
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INTERRUPT/BUSY FLAGS, DEPTH & WIDTH EXPANSION, MASTER/SLAVE CONTROL,
SEMAPHORES
For more details regarding Interrupt/Busy flags, depth and/or width expansion, master/slave control, or semaphore
operations, please consult the IDT7006 data sheet.
PACKAGE DIMENSIONS
~
~:~~~m+l
1.- 1.325 --.l
r
~I
1.355
Ba
ll
n::u
~
]5
j4-1.200~
BSC
I
0000000000000
oo 00000000000
0000000000000
000
000
ggg
ggg
ggg
r
ggg
000
000
0000
000
0000000000000
0000000000000
po 00000 00000 0
0.100
BSC
t o.
1.355
J
~
016
0.020
0.040
P
~ ~O.175
~~~
TOP VIEW
I
0.125
0.200
r-
0.060
MAX.
1 .200
BSC
j
2795 drw 18
BOTTOM VIEW
Pin A1
ORDERING INFORMATION
IDT
xxxx
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
B
Commercial (O°C to +70°C)
Military (-55°C to +125°C)Semiconductor
Components compliant to MIL-STD-883, Class B
G
Ceramic PGA (Pin Grid Array)
30
35
40
45
(Commercial Only) }
(Commercial Only)
(Military Only)
(Military Only)
BLANK
--II
L....-_ _ _ _
I
I
I S
'------------------Il
7M1002
Speed in Nanoseconds
Standard Power
16K x 32 CMOS Dual-Port Static RAM Module
2795 drw 19
7.2
12
G®
4Kx36
BiCMOS DUAL-PORT
STATIC RAM MODULE
IDT7M1014
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High-density 4K x 36 SiCMOS Dual-Port Static RAM
module
• Fast access times .
Commercial: 15, 20ns
Military: 25, 30ns
• Fully asynchronous read/write operation from either port
• Surface mounted LCC packages allow through-hole
module to fit on a ceramic PGA footprint
• Single 5V (±1 0%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL-compatible
The IDT7M1014 is a 4K x 36 asynchronous high-speed
SiCMOS Dual-Port static RAM module constructed on a cofired ceramic substrate using 4 IDT7014 (4K x 9) asynchronous Dual-Port RAMs. The IDT7M1 014 module is designed
to be used as stand-alone 36-bit dual-port RAM.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory.
The IDT7M1 014 module is packaged in a 142-lead ceramic
PGA (Pin Grid Array). Maximum access times as fast as 15ns
and 25ns are available over the commercial and military
temperature ranges respectively.
AIiIDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class S making them ideally suited
to applications demanding the highest level of performance
and reliability.
FUNCTIONAL BLOCK DIAGRAM
L_Ao-11
-
.----- R_Ao-11
L_I/Oo-a
R_I/Oo-a
IDT7014
4Kx9
L_OEL
'-
R_OEL
II
IDT7014 I - 4Kx9
IDT7014
4Kx 9
R_RNih
R_1I027-35
L-
IDT7014
4Kx 9
f--
2819 drw 01
The lOT logo is a registered trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
"'1995 Integrated Device Technology. Inc.
MARCH 1995
DSC-709613
7.3
IDT7M1014 4K x 36 SICMOS
DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
3
4
7
9
10
11
12
13
A
GND
U/03
U/02
GND
U/01
L_I/OO
GND
R_I/OO
Rj/Ol
GND
R_I/02
R_I/03
GND
B
LJ/04
U/Os
L_I/06
L_A2
L_Al
L_AO
N.C.
R_AO
R_Al
R_A2
R_I/06
R_I/05
R_I/04
C
U/OB
Vee
L_I/07
GND
N.C.
N.C.
N.C.
N.C.
N.C.
GND
R_I/07
Vee
R_I/OB
o
LJ/09
U/010
U/Oll
L_A3
GND
R_A3
R_A4
R_I/Oll
Rj/Ol0
R_I/09
GND
E
U/012
N.C.
N.C.
L_A4
R_A5
N.C.
N.C.
R_I/012
F
LJ/013
L_OEl
L_OEH
L_A5
R_A6
R_OEH
R_OEl
R_I/013
G
GND
l_RlWo
L_RlWl
GND
GND
R_RlWl
R_RlWo
GND
H
LJ/014
L_RlW2
L_R/W3
L_A6
R_A7
R_RlW3
R_RlW2
R_I/014
R_AB
R_I/017
Rj/O16
R_I/015
GND
R_I/01B
Rj/O19
R_I/020
LJ/015
LJ/016
LJ/017
L_A7
K
LJ/020
U/019
LJ/01B
GND
L_AlO
L_All
L
LJ/02l
Vee
L_I/022
L_AB
L_A9
U/03l
M
LJ/023
LJ/024
LJ/025
U/029
L_I/030
N
GND
LJ/026
LJ/027
L_I/02B
GND
GND
R_All
R_AlO
R_I/035
R_I/034
R_I/030
R_A9
R_I/022
Vee
R_I/021
U/032
U/035
R_I/033
R_I/031
R_I/029
R_I/025
Rj/O24
R_I/023
U/033
L_I/034
R_I/032
GND
R_I/02B
R_I/027
R_I/026
GND
2819 drw 02
PIN NAMES
Left Port
Right Port
L_RIW 0-3
R_RIWo-3
Byte ReadIWrite Enables
Names
L OEL.H
R OEL. H
Word Output Enables
L_Ao-ll
R_Ao-ll
Address Inputs
L_I/O 0-35
R_I/O 0-35
Data Input/Outputs
Vee
Power
GND
Ground
2819 tbl 01
7.3
2
IDT7M1014 4K x 36 BiCMOS
DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
Commercial
Military
Unit
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature.
Under Bias
Storage
Temperature
-10 to +85
-65 to +135
°C
-55 to +125
-65 to +150
°C
50
50
mA
TSTG
lOUT
DC Output
Current
Symbol
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input HIGH Voltage
2.2
-
6.0
V
VIL
Input LOW Voltage
-0.5(1)
-
0.8
V
NOTE:
2819 tbl 03
1. VIL ~ -3.0V for pulse width less than 20ns.
NOTES:
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
2819 tbl 02
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Inputs and Vcc terminals only.
3. I/O terminals only.
Grade
Ambient
Temperature
GND
Vee
Military
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
Commercial
2819 tbl 04
CAPACITANCE TABLE (TA =+25°C, f =1.0MHz)
Conditions
Max.
Unit
C IN(1)
Input Capacitance (Address)
V IN =OV
50
pF
C IN(2)
Input Capacitance (Data, RIW)
V IN = OV
15
pF
C IN(3)
Input Capacitance (OE)
V IN =OV
25
pF
V_OUT = OV
15
pF
Symbol
COUT
Parameter
Output Capacitance (Data)
2819 tbl 05
NOTE:
1. This parameter is guaranteed by design but not tested.
7.3
3
II
I
IDT7M1014 4K x 36 BiCMOS
DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to +125°C or O°C to +70°C)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
IIL11
Input Leakage
VIN = GND to Vee
Vee = Max.
-
40
JlA
IILOI
Output Leakage
OE ~ VIH, VOUT = GND to Vee
Vee = Max.
-
10
JlA
VOL
Output LOW Voltage
Vee = Min. IOL = 4mA
-
0.4
V
VOH
Output HIGH Voltage
Vee = Min. IOH = -4mA
2.4
-
V
2819 IIbl 06
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to +125°C or O°C to +70°C)
Symbol
Icc
Parameter
Test Conditions
Operating Current
Min.
-
Vee = Max.,
Max.
Unit
1040
mA
Outputs Open, f = fMAX(1)
NOTE.
2819 tbl 07
1. At f=fMAX, address and data inputs (except OE) are cycling at the maximum frequency of read cycle of 1/tRC, and using "AC TEST CONDITIONS" of
input levels of GND to 3V.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1-3
2819 tbl 08
+5V
~
48011
7
DATAoUT---------.--------.
llTM
25511
5 pF*
(Typical, ns)
4
2819 drw 03
'Including scope and jig.
Figure 1. Output Load
(For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
20
40
60
80
100 120 140 160 180 200
CAPACITANCE (pF)
2819 drw 04b
DATA OUT
~.,....--Z-0-=-5-0-n----,'~ 50Q
Figure 3. Alternate Lumped Capacitive Load,
Typical Derating
1.5V
2819 drw 04a
Figure 2. Alternate Output Load
7.3
4
IDTIM1014 4K x 36 BiCMOS
DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vee =5V ± 10%, TA =-55°C to +125°C or O°C to +70°C)
7M1014SxxG
-15
Symbol
Parameter
Min.
7M1014SxxGB
-20
Max.
-25
Min.
Max.
Min.
-30
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
-
20
-
25
-
30
-
ns
tAA
Address Access Time
15
-
25
ns
8
10
-
12
-
30
Output Enable Access Time
-
20
tOE
-
15
ns
tOH
Output Hold from Address Change
3
-
3
-
3
-
3
-
ns
tOL.Z(1)
Output Enable to Output in Low-Z
0
-
0
-
0
-
0
-
ns
tOHZ(1)
Output Disable to Output in Hi-Z
-
7
-
-
11
-
13
ns
-
20
25
-
30
-
ns
0
-
15
-
20
2
-
2
-
12
-
15
9
Write Cycle
twc
Write Cycle Time
15
tAW
Address Valid to End of Write
14
15
-
tAS
Address Set-Up Time
0
twp
Write Pulse Width
12
tWR
Write Recovery Time
1
tow
Data Valid to End of Write
10
tOH
Data Hold Time
0
tWHZ(1)
Write Enable to Output in Hi-Z
-
7
-
tow(1)
Output Active from End of Write
0
-
0
-
twoo
Write Pulse to Data Delay
-
30
tooo(1)
Write Data Valid to Read Data Delay
-
25
-
0
20
0
-
25
0
ns
ns
-
20
-
0
-
ns
-
11
-
13
ns
0
-
0
-
ns
40
-
45
-
50
ns
30
-
35
-
40
0
9
NOTES:
1. This parameter is guaranteed by design but not tested.
2. Port-to-Port delay through the RAM cells from the writing port to the reading port.
25
2
ns
ns
ns
ns
2819 tbl 09
II
TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE)
(1,2)
ADDRESS
DATAoUT
2819 drw 05
NOTES:
1. RiW is HIGH for Read Cycles.
2. OE:5: VIL
7.3
5
IDT7M1014 4K x 36 BICMOS
DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE) (1,2)
DATAoUT
2819 drw 06
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY
I
ADDRR
_
(1)
RN/R
*
twc
)K
MATCH
twp
'\~
/V
tDW
)K
DATAIN R
VALID
ADDRL
MATCH
tWDD
)K
DATAoUTL
VALID
tDDD
NOTES:
1. Rfiii is HIGH for Read Cycles.
2. Adress valid prior to OE transition LOW.
3. This parameter is guaranteed by design but not tested.
2819 drw 07
7.3
6
IDT7M1014 4K x 36 BiCMOS
DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE (EITHER SIDE)
(1,2)
twc
ADDRESS
~------------------ tAW
tWR
R/W
tow
DATAoUT
tDW
DATAIN
- ; - - tDH
DATA VALID
NOTES:
1. Rm is HIGH during all address transitions.
2. If OE is LOW during the write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn
off and data to be placed on the bus for the required tow. If OE is HIGH, this requirement does not apply, and the write pulse
can be as short as the specified twP.
3. This parameter is guaranteed by design but not tested.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
2819 drw 08
II
I
7.3
7
IDTIM1014 4K x 36 BiCMOS
DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERqAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
TOP VIEW
1..--1.327
I~
1.353
SIDE VIEW
~
~I
TD~D
i
D
~O
~
0.125
0.135
!
PIN A1
\,..;..---.--~
0.195MAX
0.050 TYP
0000000000000
0000000000000
0000000000000
0000000000000
0000
0000
000
0000
000
0000
0000
0000
0000
0000
0000000000000
0000000000000
0000000000000
0000000000000
BOTTOM VIEW
2819 drw 10
ORDERING INFORMATION
IDT
XXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (O°C to +70°C)
Military (-55°C to + 125°C) Semiconductor
Components compliant to MIL-STD883, Class B
1G
L -_ _ _ _ _-l
I
I.-______________
~I
Ceramic PGA (Pin Grid Array)
15
20
25
30
(Commercial onlY}
(Commercial Only)
(Military Only)
Speed in Nanoseconds
(Military Only)
S
Standard Power
7M1014
4K x 36 BiCMOS Dual-Port static RAM Module
I
I.--------------------il
I
2819 drw 10
7.3
8
GOO
4K x 36 BiCMOS
SYNCHRONOUSDUA~PORT
STATIC RAM MODULE
IDT7M1024
Integrated Device Technology, Inc.
ramic substrate using four I DT7099 (4K x 9) Dual-Port RAMs.
The IDT7M1024 module is designed to be used as a standalone 36-bit Dual-Port Static RAM.
The IDT7M1024 provides a true synchronous Dual-Port
Static RAM interface. Registered inputs provide very short
set-up and hold times on address, data, and all critical control
inputs. All internal registers are clocked on the rising edge of
the clock signal. An asynchronous output enable is provided
to ease asynchronous bus interfacing.
The internal write pulse width is independent of the HIGH
and LOW periods of the clock. This allows the shortest
possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input
registers without introducing clock skew for very fast interleaved memory applications.
The data inputs are gated to control on-chip noise in bussed
applications. The user must guarantee that the RiW pins are
LOW for at least one clock cycle before any write is attempted.
A HIGH on the CE input for one clock cycle will power down the
internal circuitry to reduce static power consumption.
The IDT7M1 024 module is packaged in a 142-lead ceramic
FEATURES:
• High-density 4K x 36 Synchronous Dual-Port SRAM
module
• Architecture based on Dual-Port RAM cells
- Allows full simultaneous access from both ports
• Synchronous operation
- 4ns set-up to clock, 1ns hold on all control, data, and
address inputs
- Data input, address, and control registers
- Fast 20ns clock to data out
- Self-timed write allows fast write cycle
• Clock enable feature
• Single 5V (±1 0%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7M1 024 is a 4K x 36 bit high-speed synchronous
Dual-Port Static RAM module constructed on a co-fired ce-
FUNCTIONAL BLOCK DIAGRAM
R_CLK
L_CLK
L_CLKENL
L_CEL
L_OEL
R_CLKENL
-
r-
-
R_CEL
II
r-- R_OEL
R_Ao-11
L_Ao-11
IDT7099
4Kx 9
L_l/Oo-B
R_I/Oo-B
I
L_ RiWo
Tl
IDT7099
4Kx9
L_ RiW1
L_CEH
L_OEH
-
R_ RiW1
r-f-- R_CEH
11
-
r--
L_I/01B-26
R_OEH
R_I/01B-26
IDT7099
4K x 9
R_ RiW2
II
R_CLKENH
R_I/027-35
IDT7099
4K x 9
t--
L-
I---
'----
2809 drw 01
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MARCH 1995
DSC-7097/4
"'1995 Integrated Device Technology, Inc.
7.4
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PGA (Pin Grid Array).
AIiIDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.
PIN CONFIGURATION
2
3
4
GND
S
6
7
8
9
10
11
12
13
GND
R_I/02
R_I/03
GND
R_A2
R_II06
R_I/OS
R_I/04
GND
RJ/07
VCC
R_I/08
R_A4
R_I/Oll
R_I/010
R_I/09
U/Ol
U/OO
GND
R_I/OO
R_I/Ol
L_Al
L_AO
L_CLK
R_AO
R_Al
A
GND
U/03
U/02
B
L_I/04
U/OS
U/06
C
U/08
VCC
U/07
D
U/09
U/010
E
U/012
L_CEL
L_CEH
L_A4
R_AS
R_CEH
R_CE L
R_I/012
F
U/013
L_OEL
L_OEH
L_AS
R_A6
R_OEH
R_OEL
R_I/013
G
GND
L_R/WO
L_R/Wl
H
U/014
L_R/W2
L_R/W3
U/015
U/016
U/017
K
L_I/020
U/019
L_I/018
L
L_I/021
M
L_I/023
N
GND
U/Oll
L_A2
GND
R_CLK
L_CLKEN L L_CLKEN H
L_A3
GND
R_CLKEN H R_CLKEN L
GND
R_A3
GND
R_R/Wl
R_R/m
GND
L_A6
R_A7
R_R/iNs
R_R/W2
R_I/014
L_A7
R_A8
R_I/017
R_I/016
R_I/01S
GND
R_I/018
R_I/019
R_I/020
GND
GND
L_AlO
L_All
GND
R_All
R_AlO
U/022
L_A8
L_A9
U/031
R_I/03S
R_I/034
R_I/030
R_A9
R_I/022
VCC
R_I/021
U/024
L_I/02S
U/029
U/030
U/032
U/03S
R_I/033
R_I/031
R_I/029
R_I/02S
R_I/024
R_I/023
U/026
U/027
L_I/028
GND
U/033
U/034
R_I/032
GND
R_I/028
R_I/027
R_I/026
GND
VCC
2809 drw 02
PIN NAMES
Names
Left Port
Right Port
L RiViJ 0-3
R RIWo-3
Byte ReadIWrite Enables
L OEL, H
R OEL,H
Word Output Enables
L_CE L, H
R_CEL,H
Word Chip Enables
L CLKEN L, H
R CLKEN L,H
Word Clock Enables
L CLK
R CLK
Clock Inputs
L AO-l1
R AO-11
Address Inputs
L I/O 0-35
R
1/00-35
Data Input/Outputs
Vee
Power
GND
Ground
2809 tbl 01
7.4
2
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +7.0 -D.5 to +7.0
Terminal Voltage
-0.5 to Vee
-0.5 to Vee
V
o to +70
-55 to +125
°C
VTERM(3)
Commercial
Military
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Unit
V
TA
Operating
Temperature
TSIAS
Temperatur-e
Under Bias
-55 to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +150
°C
lOUT
DC Output Current
GND
VCC
Military
-55°C to +125°C
OV
5.0V± 10%
Commercial
DoC to +70°C
OV
5.0V± 10%
50
50
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
mA
Parameter
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input HIGH Voltage
-
6.0
V
VIL
Input LOW Voltage
-
0.8
2.2
-0.5(1)
V
NOTE:
periods may affect reliability.
2. Inputs and Vcc terminals only.
(TA
Ambient
Temperature
2809 tbl 03
NOTES:
2809 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
CAPACITANCE
Grade
2809 tbl 04
1. VIL = -3.0V for pulse width less than 20ns.
=+25°C, F =1.0MHz)
Symbol
Parameter(l)
Condition
CIN
Input Capacitance
COUT
Output Capacitance
= OV
VOUT =OV
Max. Unit
VIN
50
pF
15
pF
2809 tbl 05
TRUTH TABLES
II
TRUTH TABLE I: READIWRITE CONTROL(1)
Inputs
Synchronous
Asynchronous
Outputs
Clk
CE
R/W
OE
1/00-35
Mode
.I
.I
.I
.I
.I
h
h
X
High-Z
Deselected, Power Down, Data 1/0 Disabled
h
I
X
DATAIN
Deselected, Power Down, Data Input Enabled
I
I
X
DATAIN
Write
I
h
L
DATAoUT
Read
I
h
H
High-Z
I
Data I/O Disabled
'.
2809 tbl 06
TRUTH TABLE II:
CLOCK ENABLE FUNCTION TABLE (1)
Inputs
Register Inputs
Register Outputs
Operating Mode
Clk
CLKEN
ADDR
DATAIN
ADDR
DATAoUT
Load "1"
.I
.I
.I
I
h
h
H
H
I
I
I
L
L
h
X
X
N/C
N/C
X
H
X
X
N/C
N/C
Load "0"
Hold (do nothing)
NOTE:
2809 tbl 07
1. H = HIGH voltage level steady state, h = HIGH voltage level one set-up time priorto the LOW-to-HIGH clock transition, L =LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, X = Don't care, N/C = No change
7.4
3
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vcc = 5.0V ± 10%)
IDT7M1024
Symbol
Parameter
Test Condition
Min.
Max.
Unit
40
JlA
10
JlA
IOL= 4mA
-
0.4
V
IOH =-4mA
2.4
-
V
lIul
Input Leakage Current
Vee = 5.5V, VIN = OV to Vee
IILOI
Output Leakage Current
CE = VIH, VOUT = OV to Vee
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
2809 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(VcC=5V± 10%)
IDT7M1024SxxG, IDT7M1024SxxGB
-20
Symbol
lee
IS81
IS82
IS83
IS84
Parameter
Dynamic
Operating
Current (Both
Ports Active)
Test Condition
-25
Typ. Max.
Version
CE~VIL
Mil.
-
Outputs Open
f=fMAX(l)
Com'l.
-
Mil.
-
Com'l.
-
Mil.
-
Com'l.
-
1440
-
-30
Typ.
Max.
Typ.
-
1480
-
Max.
Unit
1440
mA
-
1360
-
-
-
680
-
560
-
640
-
-
-
1080
-
-
1000
-
-
Standby
Current (Both
Ports-TTL
Level Inputs)
L_CE and
R_CE;:::;VIH
f=fMAX(l)
Standby
Current (One
Port-TTL
Level Inputs)
L_CE or R_CE ;:::; VIH
Active Port
Outputs Open,
f=fMAX(l)
Full Standby
Current (Both
Ports-CMOS
Level Inputs)
Both Ports R_CE
and L_CE;:::; Vee - 0.2V
VIN ;:::; Vee - 0.2V
or VIN ~ 0.2V, f = 0(2)
Mil.
-
-
-
80
-
80
Com'l.
-
40
-
40
-
-
Full Standby
Current (One
Port-CMOS
Level Inputs)
One Port L_CE or R_CE ;:::;
Vee - 0.2V, VIN ;:::; Vee - 0.2V
or VIN ~ 0.2V, Active Port
Outputs Open, f = fMAX(l)
Mil.
-
-
-
1040
-
960
Com'l.
-
-
960
-
-
720
1080
1040
1000
mA
mA
mA
mA
NOTES:
2809 tbl 09
1.• At f =' fMAx, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, and using "AC TEST
CONDITIONS" of input levels of GND to 3V.
2. f =0 means no address, clock, or control lines change. Applies only to inputs at CMOS level standby.
7.4
4
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
DATAOUT~
....t:
Zo=50n
I
~
} son
1.5V
See Figures 1, 2 and 3
2809 drw 03
2909 tbl10
Figure 1. Output Load
5V
8
7
1250n
6
tJ.TAA
5
(Typical, ns)
DATAoUT--~~---4
775.0
4
3
5pF*
2
2809 drw 04
20 40 60 80 100 120140 160 180 200
Figure 2. Output Load (for tClZ, tCHZ, tOlZ, and tOHZ)
Capacitance (pF)
2809 drw 05
'Including scope and jig.
Figure J. Lumped Capacitive Load, Typical Derating
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE-(READ AND WRITE CYCLE TIMING)
(Commercial: Vee
=SV ± 10%, TA = ODC to +70 DC; Military:
Vee
=SV ± 10%, TA =-SSDC to +12SDC)
7M1024SxxG,7M1024SxxGB
Symbol
Parameter
-20
-25.
Min. Max.
Min. Max.
-30
Min.
Max.
Unit
tCLK
Clock Cycle Time
20
-
25
-
30
-
ns
tCLKH
Clock HIGH Time
8
10
-
12
-
ns
tCLKL
Clock LOW Time
8
-
10
-
12
-
ns
tCQV
Clock HIGH to Output Valid
-
20
-
25
-
30
ns
tRSU
Registered Signal Set-up Time
5
-
6
-
7
-
ns
tRHD
Registered Signal Hold Time
2
-
2
2
Data Output Hold After Clock HIGH
3
-
3
3
-
ns
tCOH
-
tCLl
Clock HIGH to Output Low-Z
2
-
2
-
2
-
ns
tCHZ
Clock HIGH to Output High-Z
2
9
2
12
2
15
ns
tOE
Output Enable to Output Valid
-
10
-
12
-
15
ns
tOll
Output Enable to Output Low-Z
tOHZ
Output Disable to Output High-Z
tcsu
Clock Enable, Disable Set-up Time
5
tCHD
Clock Enable, Disable Hold Time
3
0
-
-
ns
0
-
0
-
ns
-
11
-
14
ns
-
6
-
7
-
ns
-
3
-
3
-
ns
35
-
45
-
55
9
Port-to-Port Delay
tCWOD
-
Write Port Clock HIGH to Read Data Delay
ns
2809 tbl11
7.4
5
II
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE, EITHER SIDE(1,2)
CLOCK
ADDRESS
DATAoUT
-----------+---------{
OE ____________________________________________- J
2809 drw06
TIMING WAVEFORM OF READ CYCLE WITH PORT-TO-PORT DELAY
CLOCKR
ADDRR
pATA INR
CLOCKL
ADDRL
lewD"
"1
---JXXXXXXX:K
DATA OUTL _ _ _ _ _
NOTES:
1. L_CE R_CE L, L_CLKEN
2. OE L for the reading port.
=
=
=
VALID
'--------~--r-
--J
=R_CLKEN = L
7.4
ICQL~? .___________
~XX~
VALID
teOH
2809 drw 07
6
IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF REAO-TO-WRITE CYCLE No.1, CE HIGH(1)
tCLK
tCLK
CLOCK
CLKEN -----------+----------------_r----------------~----------------------------
RNV
ADDRESS
DATAIN
DATAoUT -----------+---------(
2809 drw 08
NOTE:
1. OE LOW throughout.
TIMING WAVEFORM OF REAO-TO-WRITE CYCLE NO.1, CE LOW(1,2)
tCLK
CLOCK
CLKEN ----------~-----------------+----------------_r-----------------------------
ADDRESS
DATAIN
DATAoUT
2809 drw 09
NOTES:
1. During dead cycle, if CE is LOW, data will be written into array.
2. OE LOW throughout.
7.4
7
fI
IDTIM1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
TOP VIEW
SIDE VIEW
~1.327~
I~
- - ' - - 0.045
~O.055
--I
1.353
TD~D
L,
,
0.015
,0.021
~O
=
~ 0.100TYP
T
~~
0.125
0.135
PIN A1
\~~~
0.195MAX
0.050 TYP
0000000000000
0000000000000
0000000000000
0000000000000
0000
0000
000
0000
000
0000
0000
0000
0000
0000
0000000000000
0000000000000
0000000000000
0000000000000
BOTTOM VIEW
2809 drw 10
ORDERING INFORMATION
IDT
XXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process!
Temperature
Range
Y:lank
L----------I G
20
L-------------t25
30
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _--I S
1--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ;
Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Ceramic Pin Grid Array
Commercial Only }
Speed in Nanoseconds
Military Only
Standard Power
7M1024 4K x 36-Bit Synchronous Dual-Port RAM Module
2809 drw 11
7.4
8
(;j
Integrated Device Technology, Inc.
128K x 8
64K x8
CMOS DUAL-PORT
STATIC RAM MODULE
IDT7M1001
IDT7M1003
FEATURES
DESCRIPTION:
• High-density 1M/S12K CMOS Dual-Port Static RAM
module
• Fast access times:
-Commercial 3S, 40ns
-Military 40, SOns
• Fully asynchronous read/write operation from either port
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted LCC (lead less chip carriers) components on a 64-pin sidebraze DIP (Dual In-line Package)
• Multiple Vcc and GND pins for maximum noise immunity
• Single SV (±1 0%) power supply
• Input/outputs directly TTL-compatible
The IDT7M1001/IDT7M1003 is a 128K x 8/64K x 8 highspeed CMOS Dual-Port Static RAM module constructed on a
multilayer ceramic substrate using eight IDT7006 (16K x 8)
Dual-Port RAMs and two lOT FCT138 decoders or depopulated using only four IDT7006s and two decoders.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via semaphore (SEM) "handshake" signaling. The IDT7M1 001/1 003 module is designed
to be used as stand-alone Dual-Port RAM where on-chip
hardware port arbitration is not needed. It is the users responsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.
The IDT7M1 001/1 003 module is packaged on a multilayer
co-fired ceramic 64-pin DIP (Dual In-line Package) with dimensions of only 3.2" x 0.62" x 0.38". Maximum access times
as fast as 3Sns over the commercial temperature range are
available.
All inputs and outputs of the IDT7M1001/1003 are TTLcompatible and operate from a single SV supply. Fully asynchronous circuitry is used, requiring no clocks or refreshing for
operation of the module.
All lOT military module semiconductor components are
manufacured in compliance with the latest revision of MILSTD-883, Class S, making them ideally suited to applications
demanding the highest level of performance and reliability.
PIN CONFIGURATION(1)
Vee
GND
RiWL
RiWR
OEL
GSL
SEML
AOL
AlL
GND
OER
GSR
SEMR
AOR
A1R
A2R
A2L
A3R
A4R
A5R
A6R
A3L
A4L
A5L
A6L
A7L
A7R
ABR
A9R
Al0R
AllR
A12R
A13R
A14R
A15R
A16R
GND
I/OOR
1/01R
1/02R
1/03R
1/04R
1/05R
1/06R
1/07R
ASL
A9L
A10L
AllL
A12L
A13L
A14L
A15L
A16L
(fOOL
1/01L
1/02L
1/03L
1/04L
1/05L
1/06L
1/07L
GND
Vee
PIN NAMES
2804 drw 01
Description
Left Port
Right Port
A (O-16)L
A (O-16)R
1/0 (O-7)L
1/0 (O-7)R
Data Inputs/Outputs
RIWL
RIWR
ReadIWrite Enables
GSL
GSR
Chip Select
OEL
OER
Output Enable
SEML
SEMR
Semaphore Control
Address Inputs
Vee
Power
GND
Ground
2804 tbl 01
DIP
TOP VIEW
NOTE:
1. Forthe IDT7M1 003 (64K x 8) version, Pins 23 and 43 must be connected
to GND for proper operation of the module.
The lOT logo is a registered trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology. Inc.
MARCH 1995
DSC-70661S
7.5
~
__
IDT7M100111003
12BKl64K x B CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
J
7M1001
r
~ ~ C~~ ~ C~~ ~ F=>
I
7006
I
7006
Cs, CS,
I
7006
Cs'
7006
Cs'
Cs' Cs'
L-
I
I
74FCT138
I
I
L_AO-13
L_OE
R_AO-13
I
I
II
I
L_RIW
R_RiW
R_OE
I
74FCT138
I
I
I
'"--,
~Cs' C,"~ ~Cs' C~~ ~Csc C~~ ~Cs'
7006
7006
I
7006
1
7006
Cs"r
1
2804 drw 02
.
7M1003
R_RiW
R_OE
I
R_AO-13
74FCT138
I
I
I
I
.
I
J
I
-,
CsL
Cs"~
7006
I
Cs'7006C~~
Csc7006~~
I
74FCT138
I
I
r
1J
csc 7006 C'"r
1
J
2804 drw 03
7.5
2
IDT1M1001/1003
128K164K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
VTERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
T81AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output
Current
50
50
mA
Grade
Ambient
Temperature
GND
Vee
Military
-55°C to + 125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
Commercial
2804 tbl 04
RECOMMENDED DC
CONDITIONS
2804 tbl 02
NOTE:
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE(1)
~ymbol
(TA
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
Parameter
Symbol
= +25°C, f = 1.0MHz)
NOTE:
Parameter
Test Conditions
Max.
CINl
Input Capacitance
(CSor SEM)
VIN = OV
15
pF
CIN2
Input Capacitance
(Data, Address,
All Other Controls)
VIN = OV
100
pF
COUT
Output Capacitance
(Data)
VOUT= OV
100
pF
1. VIL (min.)
Unit
O~ERATING
0.8
V
2804 tbl 05
=-3.0V for pulse width less than 20ns.
2804 tbl 03
NOTE:
II
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
I
(Vee = 5V ± 10%, T A = -55°C to + 125°C or O°C to + 70°e)
Military
Commercial
Test Conditions
Symbol
Parameter
lee2
Dynamic Operating
Current (Both Ports Active)
Vee = Max., CS ~ VIL, SEM ~ VIH
Outputs Open, f = fMAX
leel
Standby Supply
Current (One Port Active)
Vee Max., L_CS or R_CS ~ VIH
Outputs Open, f = fMAX
IS81
Standby Supply
Current (TTL Levels)
Vee Max., L_CS and R_CS ~ VIH
Outputs Open, f = fMAX
IS82
Full Standby Supply
Current (CMOS Levels)
Min. Max.(l) MaxP) Min. Max.(l MaxP) Unit
-
940
660
-
1130
790
mA
=
-
750
470
-
905
565
mA
=
-
565
285
-
685
345
mA
-
125
65
-
245
125
mA
L SEM and R SEM ~ Vee -0.2V
L_CS and R_CS ~ Vee -0.2V
VIN > Vee 0.2V or < 0.2V
L_SEM and R_SEM ~ Vee -O.2V
2804 tbl 06
NOTES:
1. IDT1M1001 (128K x 8) version only.
2. IDT7M1003 (64K x 8) version only.
7.5
3
IDT7M100111003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(VCC=5.0V ± 10%, TA= -55°C to +125°C and O°C to +70°C)
Symbol
Parameter
IDT7M1001
Max.
Min.
Test Conditions
IDT7M1003
Min.
Max.
Unit
IILlI
Input Leakage
(Address, Data & Other Controls)
Vee = Max.
VIN = GND to Vee
-
80
-
40
JlA
IILlI
Input Leakage
(CS and SEM)
Vee = Max.
VIN = GND to Vee
-
10
-
10
JlA
IILOI
Output Leakage
(Data)
Vee = Max.
CS ~ VIH. VOUT = GND to Vee
-
80
-
40
JlA
VOL
Output Low Voltage
Vee = Min.
IOL= 4mA
-
0.4
-
0.4
V
VOH
Output High Voltage
Vee = Min.
IOH =-4mA
2.4
-
2.4
-
V
2804 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2804 tbl 08
+5 V
+5 V
~
DATAoUT
--2-5-5n-~'T"'I---i-i
480n
480n
DATAoUT---------,--------~
30 pF*
1
255n
2804 drw 05
2804 drw 04
Figure 2. Output Load
(for tCLz, tCHz, tOLZ. to HZ, tWHZ, tow)
Figure 1. Output Load
'Including scope and jig.
7.5
4
IDT7M1 00111 003
128K164K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc =5.0V ± 10%, TA =-55 DC to +125DC and oDe to +70DC)
-35
-50
-40
Parameter
Min.
tRC
Read Cycle Time
35
-
40
-
50
-
ns
tAA
Address Access Time
-
35
-
40
-
50
ns
tACS(2)
Chip Select Access Time
-
35
-
40
-
50
ns
tOE
Output Enable Access Time
-
20
-
25
-
30
ns
tOH
Output Hold From Address Change
3
-
3
-
ns
Chip Select to Output in Low-Z
3
-
3
-
3
tCLZ(1)
3
-
ns
tCHZ(1)
Chip Deselect to Output in High-Z
-
20
-
20
-
25
ns
tOLZ(1)
Output Enable to Output in Low-Z
3
-
3
-
3
-
ns
tOHZ(1)
Output Disable to Output in High-Z
-
20
-
20
-
25
ns
tPU(1)
Chip Select to Power-Up Time
0
-
0
-
0
-
ns
tPO(1)
Chip Disable to Power-Down Time
-
50
-
50
-
50
ns
tsop
SEM Flag Update Pulse (OE or SEM)
15
-
15
-
15
-
ns
Symbol
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
Write Cycle
twc
Write Cycle Time
35
-
40
-
ns
Chip Select to End-of-Write
30
-
35
-
50
tcW(2)
40
-
ns
30
-
35
-
40
-
ns
5
tAW
Address Valid to End-of-Write
tAS1(3)
Address Set-up to Write Pulse Time
5
tAS2
Address Set-up to CS Time
0
-
0
twp
Write Pulse Width
30
-
35
tWR(4)
Write Recovery Time
0
-
0
-
tow
Data Valid to End-of-Write
25
-
30
-
tOH(4)
Data Hold Time
0
-
0
-
tOHZ(1)
Output Disable to Output in High-Z
-
20
-
20
5
-
ns
0
-
ns
40
-
ns
0
-
ns
35
-
ns
0
-
ns
-
25
ns
tWHZ(1)
Write Enable to Output in High-Z
-
20
-
20
-
25
ns
toW(1.4)
Output Active from End·of-Write
0
-
0
-
0
-
ns
tSWRO
SEM Flag Write to Read Time
15
-
15
-
15
-
ns
tsps
SEM Flag Contention Window
15
-
15
-
15
-
ns
Port-to-Port Delay Timing
twOO(5)
Write Pulse to Data Delay
-
60
-
65
-
70
ns
tooo(5)
Write Data Valid to Read Data Valid
-
45
-
50
-
55
ns
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM CS:O; VIL and SEM ~ VIH. To access semaphore, CS ~ VIH and SEM
3. tAS1= 0 if R/W is asserted LOW simultaneously with or after the CS LOW transition.
4. For CS controlled write cycles, tWR= 5ns, tOH= 5ns, tow= 5ns.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
7.5
2804 tbl 09
:0;
VIL.
5
II
I
IDT7M1001/1003
128K164K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE)(1,2,4)
I~--------------------- IRC--------------------~
ADDRESS
1M
-IOH
DATA OUT
DATA VALID
2804 drw 06
TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE)(1,3,S)
7
~
~
.
.
tACS
7
K
tOE
~
~
tCHZ(6)
__
/
"~tOLZ(6)_
.
DATA OUT
tCLZ (6)
7~""/ /
7f-
~<-"
~i<-
14- tPU(6)
____
}
'\:
C-
I.I
50%
ISB
NOTES:
1. RlW is HIGH for Read Cycles
2.' Device is continuously enabled. CS = LOW. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident wilh CS transition LOW.
4. OE= LOW.
5. To access RAM, CS = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.
6. This parameter is guaranteed by design but not tested.
7.S
~ tOHZ(6)_
DATA VALID
Icc
CURRENT
~
tPO(6)
50%~_
I
2804 drw 07
6
IDT7M1001/1003
128K164K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (RIWCONTROLLED
TIMING)(1,3,S,8)
twc
ADDRESS
~
"K
--.-/ (
~
/
,
/V
-
//
I - t WHZ(9)
DATA IN
tWR(7) I
tWp(2)
",
_tOW(9)_
--
/
"'
(4)
...
FIOHZ(9)-
tAW
_tAS(6)
Rm
DATA OUT
~
/
-----Kk=
tDW
~I ..
"
tDH
(4)
)-
DATA VALID
NOTES:
2804 drw 08
1. R/W is HIGH for Read Cycles
_
__
2. Device is continuously enabled. CS = LO~ US or LS = LOW. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE= LOW.
5. To access RAM, CS = LOW, US or LS = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on whic!:!..enable signal is de-asserted first.
8. If OE is LOW during a RIW controlled write cyf.!§., the write pulse width..must be larger of twp or (twz + tow) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tOW. If OE is HIGH during a RIW controlled write cycle, this requirement does not apply and the write pulse width
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED
twc
ADDRESS
~K
..
......
r--tAS(6) ~
UB
or
LB
RtW
,..
II
TIMING)(1,3,S,8)
~
)(
..
tAW
//
tWR(7)
twp(2)
,,~
/"
_ ______________________________________
DATA IN
I
-
~~-t-D-w----.--I-----t-DH_~~---------------~
..
DATA VALID
Jl-
2804 drw 09
NOTES:
1. R/V\! must be HIGH during all address transitions._ _
_
_
2. A write occurs during the overlap (t~ of a '=9W us or LS a.!!..d a LOW CS and a LOW RIW for memory array writing cycle.
3. tWR is measured from the earlier of CS or RIW (or SEM or RIW) going HIGH to the end of write cycle.
4. Durin9.Jt1is J:leriod, the I/O pins are in the output state and input signals mu~ not be applied.
5. If the CS or SEM LOW transition occurs simultaneously with or after the RIW LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on whic.b..enable signal is de-asserted first.
8. If OE is LOW during a RIW controlled write cyc~the write pulse width ~st be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tow. If OE is HIGH during an RIW controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.
7.S
7
IDT7M1 001/1 003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
~---
VALID ADDRESS
Ao - A2
tAW
t AA
tOH
---+I
VALID ADDRESS
tWR
DATA 0
Rm
2804 drw 10
NOTE:
1. CS HIGH for the duration of the above timing (both write and read cycle).
=
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
AOA -A2A
SIDE(2) "A"
MATCH
><=~
_____________
RIWA
SEMA
tsps
Aos -A2S
SIDE(2) "8"
RlWs - - - - - - - - - - - - '
SEMs
2804 drw 11
NOTES:
1. DOR DOL LOW, L_CS R_CS HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "8" is the opposite port from "A".
3. This parameter is measured from RfWA or SEMA going HIGH to R/WB or SEMB going HIGH.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
=
=
=
=
7.5
8
IDT7M1 001/1 003
128K164K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAy(1)
twc
) ,/
ADDR R
RIW
)(
MATCH
..
R
twp
~K
//
..
)K
DATAIN R
tDH
tDW
~
VALID
MATCH
ADDRL
tWDD
)~
DATA OUT L
tDDD
NOTE:
1. L_CS=
R_CS= LOW.
WRITE CYCLE LEFT PORT
READC YCLE
RIGHT PORT
2804 drw 12
TRUTH TABLES
TABLE I: NON-CONTENTION READIWRITE CONTROL(1)
Inputs(1)
cs
OE
SEM
1/00-1/07
Mode
X
H
High-Z
Deselected: Power Down
L
L
X
X
H
DATAIN
Write to Both Bytes
L
H
L
H
DATAoUT
Read Both Bytes
X
X
H
X
High-Z
Outputs Disabled
H
II
Outputs
RIW
I
2804 tbll0
NOTE:
1. AOL-A12;o!AoR-A12R
TABLE II: SEMAPHORE READIWRITE CONTROL(1)
Inputs
cs
H
X
L
NOTE:
1. AOL-
Outputs
RIW
OE
SEM
1/00-1/07
Mode
H
L
L
DATAoUT
Read Data in Semaphore Flag
X
X
L
DATAIN
Write DINO into Semaphore Flag
L
S
X
-
Not Allowed
2804 tblll
A12;O! AOR -A12R
SEMAPHORE OPERATION
For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.
7.5
9
IDT7M1 001/1 003
128K164K x 8 CMOS DUAL·PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
7M1001
I
3.190
3.210
III
~
I
g~~~ID:DD:DDI
'PIN~
TOP VIEW
0.010
0.330
0.380
MAX.
MAX.
0.050
*
•
=f~fm.~,
0.035
0.060
0.015
0.022
~
,
0.100
TYP.
0'615
0.635
0.007
0.013
SIDE VIEW
0.125
0.175
SIDE VIEW
IOOJgD~DI
BonOMVIEW
2804 dlW 13
7M1003
IIII
3.190
~
~
I
g~~~ID:DD:DDI
Jf
PIN1
TOP VIEW
0.310
0.380
MAX.
MAX.
t
0.010
0.070
~
'\
0.015
0.022
0.100
TYP.
0.007
0.013
t
~s:Rwnml~f:Ai'TIffNm;~imffl1~fmm~!!
~~fITITf:mf.,..
~!~----;'-----l
0.035
0.060
~.,
0'615
0.635
SIDE VIEW
0.125
0.175
SIDE VIEW
BonOMVIEW
2804 dlW 14
7.5
10
IDT7M100111003
128K164K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXX
Device
type
A
999
A
A
Power
Speed
Package
Process/
Temperature
range
11....-_ _ _ _ 1 BBLANK Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Semiconductor components compliant to
MIL-STD-883, Class B
L...-_________
C
J 35
Sidebraze DIP (Dual In-line Package)
(Commercial Only)
~--------------~140
50
~------------------------~II S
I 7M1001
L . . . - - - - - - - - - - - - - - - - - - - - - - - il
}
Nanoseconds
(Military Only)
Standard Power
128K x 8 Dual-Port Static RAM Module
7M1003 64K x 8 Dual-Port Static RAM Module
2804 drw 15
II
I
7.5
11
64K x 9/128K x 9
CMOS PARALLEL IN-OUT
FIFO MODULE
G
PRELIMINARY
IDT7M208
IDT7M209
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
device uses Full and Empty flags as warnings for data overflow and underflow conditions and expansion logic to allow for
unlimited expansion capability in both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the device
through the use of the WRITE ('N) and READ (R) pins. The
devices have a read/write cycle time of 20ns (min.) for commercial and 30ns (min.) for military temperature ranges.
The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user's option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking.
IDT's Military FIFO modules have semiconductor
components manufactued in compliance with the latest revision
of MIL-STD-883, Class B, making them ideally suited to
applications demanding the highest level of performance and
reliability.
First-In/First-Out memory module
64K x 9 (IDT7M208) or 128K x 9 (IDT7M209)
High speed: 20ns (max.) access time
Asynchronous and simultaneous read and write
Fully expandable: depth and/or width
MASTER/SLAVE multiprocessing applications
Bidirectional and rate buffer applications
Empty and Full warning-flags
Single 5V (±1 0%) power supply
DESCRIPTION:
IDT7M208 and IDT7M209 are FIFO memory modules
constructed on a multi-layered ceramic substrate using four
I DT7206 (16K x 9)or IDT7207 (32K x 9) FI FOs in leadless chip
carriers. Extremely high speeds are achieved in this fashion
due to the use of IDT7206/7s fabricated in IDT's high performance CMOS technology. These devices utilize an algorithm
that loads and empties data on a first-in/first-out basis. The
FUNCTIONAL BLOCK DIAGRAM
OcrOa
OcrOa
W
XO
R
r
RS
[
Xi-
PIN CONFIGURATION
1
T
I
W
I
04
I I
Oa
03
02
01
00
Os
Oe
xc
I
l-
IDT720en
Xi
FF
Xi
FF
FL
EF
IT
FL
:~
FL
EF
xo
xo
IDT720en
'-Xi
xcU
IDT720en
IDT720en
'-Xi
FF
Vc
c O~J
FF -f-cl
:~
-f-cO
OUAL 4-INPUT OR GATE
3162 drw01
Vee
07
FL
Xi
FF
RS
00
01
02
03
XO
Oe
Os
Oa
GNO
R
EF
07
04
DIP
TOP VIEW
3162 drw 02
The IDT logo Is a registered trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL T,EMPERATURE RANGES
MARCH 1995
DSC·712311
©1995 Integrated Device Technology, Inc.
7.6
IDT7M20B (64K x 9), IDT7M209 (12BK X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN NAMES
CAPACITANCE
W=
WRITE
FL=
FIRST LOAD
XI =
EXPANSION IN
EF=
EMPTY FLAG
R=
READ
D=
DATAIN
XO=
EXPANSION OUT
Vee =
5V
RS=
RESET
Q=
DATAoUT
FF=
FULL FLAG
GND=
GROUND
Symbol
CIN
COUT
(TA
=+25°e, f = 1.0 MHz)
Parameter(l)
Condition
Max.
Input Capacitance
VIN = OV
50
Output Capacitance
VOUT= OV
50
NOTE:
1. This parameter is guaranteed by design but not tested.
Unit
pF
pF
3162 tbl 03
3162 tbl 01
RECOMMENDED DC
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Com'l.
Mil.
Terminal Voltage
with Respect
toGND
-0.5 to +7.0 -0.5 to +7.0
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +150
°C
lOUT
DC Output
Current
50
50
Symbol
Unit
VTERM
V
Min.
Typ.
Max.
Unit
Military Supply
Voltage
4.5
5.0
5.5
V
Vcc
Commercial
Supply Voltage
4.5
5.0
5.5
V
0
V
GND
Supply Voltage
VIH(l)
Input High Voltage
Commercial
2.0
-
-
V
VIH(l)
Input High Voltage
Military
2.2
-
-
V
VIL(2)
Input Low Voltage
Commercial and
Military
-
-
O.S
V
mA
NOTE:
3162 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Parameter
VCCM
0
0
NOTES:
1. VIH 2.6V forXi' input (commercial)
VIH 2.BV forXi' input (military)
2. 1.5V undershoots are allowed for 10ns once per cycle.
3162 tbl 04
=
=
DC ELECTRICAL CHARACTERISTICS
I
(Vee =5 OV+10%
TA =ooe to +70 oe', and -55°e to +125°C)
Symbol
IU(l)
Commercial
Min.
Max.
Parameter
Military
Max.
Min.
Unit
Input Leakage Current (Any Input)
-5
5
-40
40
~
-40
40
-40
40
~
2.4
-
V
IOL(2)
Output Leakage Current
VOH
Output Logic "1" Voltage lOUT
-
2.4
VOL
Output Logic "0" Voltage lOUT = SmA
-
0.4
-
0.4
V
ICC1(3)
Vcc Power Supply Current
-
560
-
720
mA
ICC2(3)
Standby Current (R
mA
32
-
SO
Power Down Current (All Input = VCC - 0.2V)
-
60
ICC3(3)
4S
mA
=-2mA
=W =RS =FURT =VI H)
NOTES:
1. Measurements with 0.4 :s; VIN :s; Vec.
2. R ~ VIH, 0.4 :s; VOUT :s; Vee.
3. lee measurements are made with outputs open.
3162 tbl 05
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
See Figure 1 and 2
3162 tbl 06
7.6
2
fI
I
IDT7M20B (64K x 9), IDT7M209 (128K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
+5V
+5V
480Q
DATAoUT
DATAoUT
255Q
30pF*
255Q
3162 drw 03
3162 drw 04
Figure 2. Output Load
(for tRLZ, tWLZ, and tRHZ)
Figure 1. Output Load
* Includes scope and jig capacitances.
* Includes scope and jig capacitances.
AC ELECTRICAL CHARACTERISTICS
(Vee
=5.0V±10%, TA =oDe to +70De and -55 De to +125DC)
-20
-25
(Com'l Only) (Com'l Only)
Symbol
fs
Parameter
Min.
-
Shift Frequency
Max.
33.3
Min.
-
Max.
28.6
-30
-35
(Mil Only)
(Mil Only)
Min.
Min. Max.
-
Max.
25
-
22.5
Unit
MHz
tRC
Read Cycle Time
30
-
35
-
40
-
45
-
ns
tA
Access Time
-
20
-
25
-
30
-
35
ns
tRR
Read Recovery Time
10
10
-
10
-
ns
Read Pulse Width
20
25
30
-
35
-
ns
tRLZ(2)
5
-
5
5
-
5
-
ns
tWLZ(2)
Z
Write Pulse High to Data Bus at Low Z
5
-
5
5
5
-
5
-
ns
Data Valid from Read Pulse High
-
10
tov
-
10
tRPW(1)
-
tRHZ(2)
Read Pulse High to Data Bus at High
20
-
20
ns
twc
-
ns
twPW(1)
ns
Read Pulse Low to Data Bus at Low
5
5
-
16
-
20
-
Write Cycle Time
30
-
45
25
-
40
20
-
35
Write Pulse Width
30
35
tWR
Write Recovery Time
10
tos
Data Set-up Time
-
tOH
Data Hold Time
0
tRSC
-
Z
10
15
-
10
18
-
0
-
0
-
0
Reset Cycle Time
30
35
40
25
-
10
-
tRS(1)
Reset Pulse Width
20
tRSR
Reset Recovery Time
10
-
10
tEFL
Reset to Emtpy Flag Low
-
30
-
35
tREF
Read Low to Emtpy Flag Low
-
23
-
25
-
tRFF
Read High to Full Flag High
23
Write High to Empty Flag High
tWFF
Write Low to Full Flag Low
-
25
tWEF
-
23
23
25
25
18
30
-
10
20
ns
ns
ns
ns
ns
-
35
-
10
-
ns
40
-
45
ns
35
ns
35
ns
30
30
30
30
45
-
ns
35
ns
35
ns
3162 tbl 06
NOTES:
1. Pulse widths less than minimum value are not allowed.
2. Values guaranteed by design, not currently tested.
7.6
3
IDT7M208 (64K x 9), IDT7M209 (128K X 9)
CMOS PARALLEL IN·OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF RESET CYCLE(1,2)
tRS
------4~~
~r
\.
-.1{.
I
~~
EF
~'"---------'
~
~------------t-RS-R--~--------------
_ _ _ _ _ _ _ __ _ _ _t_EF_L___
3162 drw 05
NOTES:
1. tRse =tRS + tRSR
2. Wand R VIH during RESET.
=
TIMING WAVEFORM OF ASYNCHRONOUS WRITE AND READ OPERATION
Oo-Os
_ F
tNpw
----~-
____-oJ/
W~_ _ _ _ _ __
Do-Ds
---------{ . . _______.........----c(
DATAIN
VALID
)>-------3162 drw 06
TIMING WAVEFORM FOR THE FULL FLAG FROM LAST WRITE TO FIRST READ
FIRST READ
LAST WRITE
ADDITIONAL
READS
FIRST
WRITE
II
I
tRFF
3162 drw 07
TIMING WAVEFORM FOR THE EMPTY FLAG FROM LAST READ TO FIRST WRITE
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST
READ
W
DATAoUT
--+----{
3162 drwOB
NOTE:
1. This parameter is guaranteed by design but not tested.
7.6
4
IDT7M208 (64K x 9), IDT7M209 (128K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM FOR THE EMPTY FLAG CYCLE
EF
NOTE:
1. tRPE must be ;:: tRPW (min). Refer to Technical Note TN-DB for details on this boundary condition.
TIMING WAVEFORM FOR THE FULL FLAG CYCLE
FF
3162 drw 10
NOTE:
1. tWPF must be ;:: twpw (min). Refer to Technical Note TN-OB for details on this boundary condition.
TIMING WAVEFORM OF READ DATA FLOW-THROUGH MODE
\V'
DATA IN
3V
W
tRPE
R
EF
OV
OV
tWL
DATAoUT
VALID
3162 drw 11
7.6
5
IDT7M208 (64K x 9), IDT7M209 (128K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE DATA FLOW-THROUGH MODE
3V
R
W
OV
FF
OV
tRFF
tDH
DATAIN
DATAoUT
-@<
DATAoUT
VALID
)@~-------------3162 drw 12
DEPTHIWIDTH EXPANSION & DATA FLOW-THROUGH
MODES:
For more details on expanding FIFO modules in depth and!
or width, please refer to the I 0T7206 or I 0T7207 data sheets.
For more details on data flow-through modes (read data fall
through and write data fall-through), please refertothe 10T7206
or IOT7207 data sheets.
PACKAGE DIMENSIONS
rool·t--------
1.380
""fA25"
-t
-
g:~~g
t-l
TOP VIEW
Pin1/
0.007
0Jfi3
0210
[
0.220
O:260~*===0='3=1
SIDE VIEW
O==-..-...!L-L
j I'II
0.035
0.060
-I
I
'I
0.100
TYP.
-II
.Q,Q1Q.
0.050
Ij
0.015
0.022
0.125
0.175
3162 drw 13
7.6
6
II
IDT7M208 (64K x 9), IDT7M209 (128K X 9)
CMOS PARALLEL IN-OUT FIFO MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXX
A
999
A
A
Device Type
Power
Speed
Package
Process/
Temperature
Range
Y:lank
'--------1
Commercial (O°C to+ 70°C)
Military (-55°C to+ 125°C)
C
Sidebraze DIP
20
25
(Commercial Only) }
(Commercial Only)
(Military Only)
Speed in Nanoseconds
(Military Only)
L...------------I 30
35
L...-------------~S
Standard Power
--1 7M208 64K x 9 FIFO Module
1....-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
7M209 128K x 9 FIFO Module
7.6
3162 drw 14
7
~
IDT7MP4120
1M x 32
CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• High-density 4MB Static RAM module
• Low profile 72-pin ZIP (Zig-zag In-line vertical Package)
or 72-pin SIMM (Single In-line Memory Module)
• Fast access time: 20ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±1 0%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL-compatible
The IDT7MP4120 is a 1 M x 32 Static RAM module constructed on an epoxy laminate (FR-4) substrate using 81M x
4 Static RAMs in plastic packages. Availability of four chip
select lines (one for each group of two RAMs) provides byte
access. The I DT7M P4120 is available with access time as fast
as 20ns with minimal power consumption.
The IDT7MP4120 is packaged in a 72-pin FR-4 ZIP (Zigzag In-line vertical Package)or a 72-pin SIMM (Single In-line
Memory Module). The ZIP configuration allows 72 pins to be
placed on a package 4.05" long and 0.365" wide. At only 0.60"
high, this low-profile package is ideal for systems with minimum board spacing while the SIMM configuration allows use
of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4120 are TTL-compatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
Four identification pins (PDo, PD1, PD2 and PD3) are provided for applications in which different density versions of the
module are used. In this way, the target system can read the
respective levels of PDo, PD1, PD2 and PD3 to determine a 1M
depth.
PIN CONFIGURATION(1)
2
4
POO 6
1/00 8
1/01 10
1/02 12
1/03 14
Vee 16
A7 18
A8 20
A9 22
1/04 24
1/05 26
1/06 28
1/07 30
WE 32
A14 34
CS1 36
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD:3
CS3
A16
GND
1/016
1/017
1/018
1/019
A10
A11
A12
A13
1/020
1/021
1/022
1/023
GND
A19
NC
NC
PD2
GND
PD1
1/08
1/09
1/010
1/011
Ao
A1
A2
1/012
1/013
1/014
1/015
GND
A15
CS2
PDo-GND
PD1-NC
PD2-GND
PD3-NC
FUNCTIONAL BLOCK DIAGRAM
20
CS1
CS2
CS3
CS4
'
,
,
+
Ao -A19
3
PDo - PD3
CS4
A17
OE
1/024
1/025
1/026
1/027
A3
A4
A5
1/00-7
1108-15 11016-23 11024-31
3019 drw 02
Vee
PIN NAMES
A6
1/028
1/029
1/030
1/031
A18
NC
3019 drw 01
ZIP, SIMM
TOP VIEW
NOTE:
1. Pins 3, 4, 6 and 7 (PDo, PD1, PD2 and PD3 respectively) are read by the
userto determine the density ofthe module. If PDo reads GND, PD1 reads
NC, PD2 reads GND and PD3 reads NC, then the module has a 1M depth.
1/00-1/031
Data InputslOutputs
Ao-A19
Addresses
CS1-CS4
Chip Selects
WE
Write Enable
OE
Output Enable
PDo-PD3
Depth Identification
Vec
Power
GND
Ground
NC
No Connect
3019 tbl 01
The lOT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 1995
Cl.11995 Integrated Device Technology. Inc.
DSC-7104l4
7.7
II
IDT7MP4120
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA =+25°e, F =1.0MHz)
Parameter(l)
Symbol
ClIO
Data 1/0 Capacitance
CINl
Input Capacitance
(Address)
Conditions
TRUTH TABLE
Max.
Unit
15
pF
60
pF
=OV
V(lN) =OV
V(IN)
CIN2
Input Capacitance
(WE,OE)
V(IN)
=OV
75
pF
CIN3
Input Capacitance (CS)
V(IN)
=OV
20
pF
Mode
Standby
Parameter
Min.
Typ.
Supply Voltage
4.5
5.0
GND
Supply Voltage
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
NOTE:
1. VIL (min)
WE
X
Output
Power
X
High-Z
Standby
Active
Read
L
L
H
DATAoUT
Write
L
X
L
DATAIN
Active
Read
L
H
H
High-Z
Active
ABSOLUTE MAXIMUM RATINGS(1)
3019 tbl 02
Symbol
VTERM
RECOMMENDED DC OPERATING
CONDITIONS
Vee
OE
H
3019 tbt 05
NOTE:
1. This parameter is guaranteed by design but not tested.
Symbol
CS
0
Max.
Unit
5.5
V
0
-
0
V
6.0
V
O.S
Value
Unit
-0.5 to +7.0
V
°C
TA
Operating Temperature
o to +70
T81AS
Temperature Under Bias
-10 to +S5
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
NOTE:
3019 tbl06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
V
3019 tbl03
=-1.5V for pulse width less than 1Ons ..
Rating
Terminal Voltage with
Respect to GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Vee
5.0V ± 10%
3019 tbl 04
DC ELECTRICAL CHARACTERISTICS
(Vee
= 5.0V ±10%, TA = ooe to +70°C)
Symbol
lIul
Parameter
Test Conditions
=Max.; VIN =GND to Vee
Input Leakage
(Address and Control)
Vee
=Max.; VIN =GND to Vee
=Max.; CS =VIH, VOUT =GND to Vee
Vee =Min., IOL =SmA
Vee =Min., IOH =-4mA
lIul
Input Leakage (Data)
IILOI
Output Leakage
VOL
Output LOW
VOH
Output HIGH
Vee
Vee
Min.
Max.
Unit
-
SO
JlA
-
10
JlA
10
JlA
0:4
V
2.4
-
V
3019 tbl07
Symbol
Parameter
Test Conditions
=
lee
Dynamic Operating
Current·
f =fMAX; CS VIL
Vee Max.; Output Open
IS8
Standby Supply
Current
CS:2! VIH, Vee Max.
Outputs Open, f fMAX
IS81
Full Standby
Supply Current
CS:2! Vee - 0.2V; f 0
VIN> Vee - O.2V or < 0.2V
=
=
=
=
7MP4120
Max.
Unit
12S0
mA
4S0
mA
120
mA
3019 tbl 08
7.7
2
IDT7MP4120
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
See Figures 1 and 2
Output Load
2769 tbl 09
+5V
+5 V
4800
4800
DATAoUT
DATAoUT
2550
2550
30 pF*
_
5pF*
i
3019 drw04
3019 drw 03
'Includes scope and jig.
Figure 2. Output Load
Figure 1. Output Load
(for tOl2,tOHZ, tCHZ, tCl2, tWHZ, tow)
II
7.7
3
IDT7MP4120
1M x32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee
=5V ±10%, TA =O°C to +70°C)
7MP4120SxxZ/M
-20
Symbol
Parameter
-25
Min.
Max.
Min.
Max.
Unit
25
ns
-
25
25
Read Cycle
tRC
Read Cycle Time
20
tAA
Address Access Time
-
tACS
tCLZ(1)
Chip Select Access Time
-
20
20
Chip Select to Output in Low-Z
3
-
3
-
ns
tOE
tOLZ(1)
Output Enable to Output Valid
-
12
-
15
ns
Output Enable to Output in Low-Z
0
-
0
-
ns
tCHZ(1)
Chip Deselect to Output in High-Z
-
Output Disable to Output in High-Z
-
-
tOH
tPU(1)
Output Hold from Address Change
3
3
Chip Select to Power-Up Time
tPO(1)
Chip Deselect to Power-Down Time
0
-
-
12
12
25
ns
tOHZ(1)
10
10
-
ns
-
ns
20
-
0
-
ns
ns
ns
ns
ns
ns
Write Cycle
20
17
17
0
15
-
-
25
20
20
0
20
Write Recovery Time
3
-
3
-
ns
tWHZ(1)
Write Enable to Output in High-Z
-
-
15
ns
tow
Data to Write Time Overlap
Data Hold from Write Time
15
0
0
-
ns
tOH
toW(1)
12
0
0
10
-
twc
Write Cycle Time
tcw
Chip Select to End-of-Write
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
twp
Write Pulse Width
tWR
Output Active from End-of-Write
NOTE:
1. This parameter is guaranteed by design, but not tested.
-
ns
ns
ns
ns
ns
3019tbll0
7.7
4
IDT7MP4120
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
tRC
------------I~
ADDRESS
tACS --------+---~
tCLZ (5) ----------l~
DATA OUT
3019 drw 05
TIMING WAVEFORM OF READ CYCLE NO.
ADDRESS
DATAoUT
2(1,2,4)
~~~~~~~~~~~~~-tO-H-_-_-_-_-_--tA~A~~~t~R~C----------------.-I----~~-t-O-H----------PREVIOUS DATA VALID
DATA VALID
3019 drw 06
TIMING WAVEFORM OF READ CYCLE NO.
CS
-------1-
telz (5)
~Aes
II
3(1,3,4)
t
1
teHz (5)
=j
DATAOUT----------------------j--~<::><::><:~------------------------------------~
3019 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition LOW.
4. OE=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.7
5
IDT7MP4120
1M x32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED) (1,2,3,7)
twe
ADDRESS
~
----./
K
)K
/
/
tAW
~
twp (7)
~tAS
""
~
tWR_
/
(4)
/
tOHZ(6)
tWHZ(6)_
to HZ (6)
DATA OUT
I--
"
tOW(6)_
/
i'..
/
_tDW
/
DATA IN
"-
-
(4)
)
'-
tDH
DATA VALID
"
/
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)
ADDRESS
/
/
r'\.
3019 drwOB
(1,2,3,5)
twe
)
)
K
K
tAW
14-- tAS
~
/
E
tWR
tew
tDW
DATAIN - - - - - - - - - - - - - - - - - - - ( [
"I"
tDH
DATAVALID
3019 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (twp) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, 110 pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by deSign, but not tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of twp or (tWHZ + tDW) to allow the 110 drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
7.7
6
IDT7MP4120
1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
ZIP VERSION
FRONT VIEW
SIDE VIEW
0.365 MAX
~~
PIN 1
0.100 TYP
0.050 TYP
0.015
0.025
0.250 TYP
0.125
0.175
-t
0.100 TYP
PIN 1
REAR VIEW
3019 drw 10
SIMM VERSION
~
_____________ 4.260
4.240 ______________________
~_ _ _ _ 3.980
~
II
~
___
:
0.350
MAX.
3.988
0.640
0.660
SIDE VIEW
FRONT VIEW
IO~L".n •• ".,! ,~!" '"' "'" ~,I,,, "III"" "I.~,1, , 'n"""~
BACK VIEW
PIN 1
7.7
3019 drw 11
7
IDT7MP4120
1M x 32 CMOS STATIC RAM MODULE
ORDERING INFORMATION
X
X
lOT XXXXX
Device
Type
Power
Speed
COMMERCIAL TEMPERATURE RANGE
X
X
Package
Process/
Temperature
Range
I
' - - - - - - I Blank
Z
M
20
~-----------------------I 25
S
Commercial (O°C to +70°C)
FR-4 ZIP (Zig-Zag In-line vertical Package)
FR-4 SIMM (Single In-line Memory Module)
}
Speed in Nanoseconds
Standard Power
7MP4120 1 M x 32 Static RAM Module
3019drw 12
7.7
8
256K x 32
CMOS STATIC RAM
MODULE
(;)
IDT7MP4145
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 1 megabyte static RAM module
(upgradeable to 4 megabyte, IDT7MP4120)
1/011
The IDT7MP4145 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability of
four chip select lines (one for each group of two RAMs)
provides byte access. The IDT7MP4145 is available with
access time as fast as 15ns with minimal power consumption.
The IDT7MP4145 is packaged in a 72 lead SIMM (Single
In-line Memory Module). The SIMM configuration allows 72
leads to be placed on a package 4.25 inches long and 0.365
inches wide. At only 0.65 inches high, this low profile package
is ideal for systems with minimum board spacing; using
angled SIMM sockets can reduce the effective module height
even further.
All inputs and outputs of the I DT7MP4145 are TTL compatible and operate from a single 5V supply. Full asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
Four identification pins (PDO-3) are provided for applications
in which different density versions of the module are used. In
this way, the target system can read the respective levels of
PDO-3 to determine a 256K depth.
Ao
A1
A2
FUNCTIONAL BLOCK DIAGRAM
• Low profile 72 lead SIMM (Single In-line Memory Module)
• Very fast access time: 15ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL compatible
PIN CONFIGURATION(1)
NC 2
PD3 4
PDo 6
1/00
1/01
1/02
1/03
Vee
A7
A8
A9
1/04
1/05
1/06
1/07
WE
A14
CS1
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
cSa 38
A16 40
GND 42
1/016 44
1/017 46
1/018 48
1/019 50
AlO 52
An 54
A12 56
A13 58
1/020 60
1/021 62
1/022 64
1/023
GND
NC
NC
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD2
GND
PD1
PDo-GND
PD1-GND
PD2-0PEN
PD3-0PEN
1/08
1/09
1/010
1/012
1/013
1/014
1/015
GND
A15
CS2
ADDRESS
II
18
CS4
A17
OE
I
1/024
1/025
1/026
1/027
1/00-31
A3
A4
As
3148 drw 02
PIN NAMES
Vee
A6
1/028
1/00-31
Data InputslOutputs
1/029
1/030
A0-17
Addresses
1/031
NC
NC
CS1-4
Chip Selects
WE
Write Enable
OE
Output Enable
3148 drw 01
SIMM
TOP VIEW
NOTE:
1. Pins 3, 4, 6 and 7 (PDO-3) are read by the user to determine the density
of the module. If PDo, PD1 read GND and PD2, PD3 read OPEN, then the
module had a 256K depth.
PDO-1
Depth Identification
Vee
Power
GND
Ground
NC
No Connect
3148 tbl 01
The lOT logo is a registered trademark of Integrated Device Technology, Inc. All others are property of their respective companies.
COMMERCIAL TEMPERATURE RANGE
MARCH 1995
""995 Integrated Device Technology. Inc.
DSC-712111
7.B
IDT7MP4145
256Kx 32 CMOS STATIC RAM MODULE
CAPACITANCE
(TA
=+25°e, F = 1.0MHz)
Parameter(l)
Symbol
COMMERCIAL TEMPERATURE RANGE
Conditions
TRUTH TABLE
Max.
Unit
Mode
CS
OE
WE
Output
Power
H
X
X
High Z
Standby
L
L
H
DATAoUT
Active
L
X
L
DATAIN
Active
H
H
High-Z
Active
CIN(D)
Input Capacitance
(CS)
V(IN)
= OV
20
pF
Standby
Input Capacitance
(Address & Control)
V(IN)
= OV
Read
CIN(A)
70
pF
Write
Read
L
1/0 Capacitance
CliO
V(OUT)
=OV
12
pF
NOTE:
1. This parameter is guaranteed by design but not tested.
3148 tbl 05
3148 tbl 02
ABSOLUTE MAXIMUM RATINGS(1}
Symbol
RECOMMENDED DC OPERATING
CONDITIONS
VTERM
Rating
Terminal Voltage with
Respect to GND
Value
Unit
-0.5 to +7.0
V
°C
Min.
Typ.
Max.
Unit
TA
Operating Temperature
o to +70
Vee
Supply Voltage
4.5
5.0
5.5
V
T81AS
Temperature Under Bias
-10 to +B5
°C
GND
Supply Voltage
0
0
0
V
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
Symbol
Parameter
VIH
Input High Voltage
2.2
-
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
O.B
V
NOTE:
1. VIL (min) = -1.5V for pulse width less than 10ns.
NOTE:
3148 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
3148\b103
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Vee
5.0V ± 10%
3148 tbl 04
DC ELECTRICAL CHARACTERISTICS
(Vee
=5 OV +10%
, TA =ODe to +70°C)
-
Symbol
lIul
Parameter
Test Conditions
Max.
Unit
-
BO
Il A
Vee
-
10
IlA
Vee
-
10
IlA
-
0.4
V
2.4
-
Input Leakage
(Address and Control)
Vee
lIul
Input Leakage (Data)
IILOI
Output Leakage
VOL
Output Low
VOH
Output High
=Max.; VIN = GND to Vee
= Max.; VIN =GND to Vee
=Max.; CS =VIH, VOUT =GND to Vee
Vee = Min., IOL = BmA
Vee =Min., IOH =-4mA
Min.
V
3148 tbl 07
Symbol
Parameter
Test Conditions
=
Max.
=
lee
Dynamic Operating
Current
f fMAX; CS VIL
Vee Max.; Output Open
IS8
Standby Supply
Current
CS ~ VIH. Vee Max.
Outputs Open, f fMAX
Full Standby
Supply Current
CS ~ Vee - 0.2V; f 0
VIN> Vee - 0.2V or < 0.2V
IS81
=
=
=
=
Unit
1360
mA
4BO
mA
120
mA
3148 tbl 08
7.8
2
IDT7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1 and 2
Output Load
3148 tbl 09
+5V
+5V
4800
4800
DATAoUT-----------.---------;
DATAoUT-----------.---------;
2550
255Q
30 pF*
5pF*
3148 drw 03
3148 drw 04
Figure 1. Output Load
Figure 2. Output Load
(for tOlz,tOHZ, tCHZ, tCLZ, tWHZ, tow)
-Includes scope and jig capacitances.
AC ELECTRICAL CHARACTERISTICS
= 5V ±1 0%, TA = OCC to + 70 c C)
(VCC
-15
Symbol
Parameter
Read Cycle
Min.
-20
Max.
Min.
-25
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
15
-
20
-
25
-
ns
tAA
Address Access Time
15
-
20
ns
Chip Select Access Time
15
-
20
-
25
tACS
-
25
ns
tCLZ(l)
Chip Select to Output in Low-Z
3
-
5
-
5
-
ns
tOE
tOLZ(l)
Output Enable to Output Valid
-
8
-
10
-
12
ns
Output Enable to Output in Low-Z
0
-
0
-
0
-
ns
tCHZ(l)
Chip Deselect to Output in High-Z
-
8
10
ns
Output Disable to Output in High-Z
-
8
10
-
12
tOHZ(l)
-
tOH
Output Hold from Address Change
3
3
-
3
tPU(1)
Chip Select to Power-Up Time
0
-
0
-
tPO(l)
Chip Deselect to Power-Down Time
-
15
-
I
10
ns
ns
0
-
20
-
25
ns
-
25
-
ns
20
-
ns
ns
Write Cycle
twc
Write Cycle Time
15
-
20
tcw
Chip Select to End-of-Write
12
-
15
tAW
Address Valid to End-of-Write
12
-
15
-
20
tAS
Address Set-up Time
0
-
0
0
twp
Write Pulse Width
12
15
20
tWR
tWHZ(1)
Write Recovery Time
0
-
-
0
-
0
Write Enable to Output in High-Z
-
8
-
13
-
15
ns
tow
Data to Write Time Overlap
10
12
-
15
-
ns
tOH
Data Hold from Write Time
0
-
0
-
0
-
ns
toW(1)
Output Active from End-of-Write
0
-
0
-
0
-
ns
NOTE:
1. This parameter is guaranteed by design, but not tested.
ns
ns
ns
ns
3148 tbll0
7.8
II
3
IDT7MP4145
256Kx 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRG
----------~
ADDRESS
tAGS - - - - - - - l - - - + - i
tGLZ(5)
-----~
DATAOUT------------------------------------~
3148 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAoUT
~: ~- :~- :~- :~- :~ - -t-O-H~ - :~ - ~ -tA~-A~- - - t~R-G~- - - - - - - ~-I- - ~ -t-OH- - - - - PREVIOUS DATA VALID
DATA VALID
3148 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
----.~ ~Aes
leu (51
1_
t
leHZ (5)
=-j
DATAOUT--------------------j---K<::><::><:~~---------------------------------~
3148 drw 07
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
=
7.8
4
IDT7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED) (1,2,3, 7)
twc
ADDRESS
><:
) V~
/
V
tAW
"\
twp (7)
: . - tAS
tWR_
''\..
-
/
tWHZ(6) ___
(4)
V
tOHZ(6)
~ tOW(6)_
tOHZ (6)
DATA OUT
V
/
~
V
'"
/
"-
_tDW
V
DATA IN
"-
(4)
)-
tDH
'"
DATA VALID
/
3148 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED) (1,2,3,5)
twc
ADDRESS
)
<
~tAS
)
tAW
~
/'
II
<
Z'
I
tWR
tcw
DATAIN--------------------------------~~
tDW
.1.DATA VALID
tDH
3)f----3148 drw 09
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by deSign, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twP.
7.8
5
IDT7MP4145
256Kx 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
~
________________ 4.260 __________________________
4.240
~
_ _ _ _ _ _ _ _ _ _ _ _ 3.974
3.994
~
I
----------I:~~
0.350
MAX.
~~
_~+OM5
0.640
0.660
0.055
SIDE VIEW
FRONT VIEW
3148 drw 10
ORDERING INFORMATION
IDT
XXXXX
X
X
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
I'------;1 Blank
Commercial (O°C to +70°C)
72-lead FR-4 SIMM
(Single In-line Memory Module)
~--------------~ M
~
_________________
15
~20
}
Speed in Nanoseconds
25
~----------------------------~
S
~------------------------------------; 7MP4145
Standard Power
256K x 32 Static RAM Module
3148 drw 11
7.8
6
IDT7MP4045
256K x 32
BiCMOS/CMOS STATIC RAM
MODULE
t;)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 1 megabyte static RAM module
The IOT7MP4045 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability of
four chip select lines (one for each group of two RAMs)
provides byte access. The IOT7MP4045 is available with
access time as fast as 1Ons with minimal power consumption.
The IOT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zigzag In-line vertical Package)or a 64 pin SIMM (Single In-line
Memory Module). The ZIP configuration allows 64 pins to be
placed on a package 3.65 inches long and 0.365 inches wide.
At only 0.585 inches high, this low profile package is ideal for
systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the
module.
All inputs and outputs of the IOT7MP4045 are TTL-compatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
Two identification pins (POD and POl) are provided for
applications in which different density versions of the module
are used. In this way, the target system can read the respective levels of POD and POl to determine a 256K depth.
• Low profile 64 pin ZIP (Zig-zag In-line vertical Package)
or 64 pin SIMM (Single In-line Memory Module)
• Ultra fast access time: 10ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GNO pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL-compatible
PIN CONFIGURATION(l)
POD
1/00
1/01
1/02
1/03
Vcc
A7
A8
A9
1/04
1/05
1/06
1/07
WE
A14
CS1
CS3
A16
GND
1/016
1/017
1/018
1/019
A10
A11
A12
A13
1/020
1/021
1/022
1/023
GND
GND
PD1
1/08
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32 ZIP, SIMM
7
9
11
13
15
17
19
21
23
25
27
29
31
PDo- GND
PD1-GND
1/09
1/010
1/011
AD
A1
A2
1/012
1/013
FUNCTIONAL BLOCK DIAGRAM
1/014
1/015
GND
A15
CS2
fI
TOP VIEW
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
CS4
A17
OE
1/024
1/025
1/00-31
1/026
2703 dlW 02
1/027
A3
A4
A5
PIN NAMES
Vee
A6
1/028
1/00-31
Data InputslOutputs
Ao-17
Addresses
CS1-4
Chip Selects
1/029
WE
Write Enable
1/030
OE
Output Enable
PDo-1
Depth Identification
1/031
2703 dlW 01
NOTE:
Vcc
Power
1. Pins 2 and 3 (PDo and PD1) are read by the user to determine the density
GND
Ground
of the module. If PDo reads GND and PDl reads GND, then the module
had a 256K depth.
2703 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 1995
"l1995lntegraled Device Technology, Inc.
DSC-706113
7.9
IDT7MP4045
256Kx 32 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA =+25°C, F = 1.0MHz)
TRUTH TABLE
CS
OE
Power
Input Capacitance
(CS)
V(IN) = OV
20
pF
Standby
H
X
WE
X
Output
CIN(e)
High-Z
Standby
Read
L
L
H
DATAoUT
Active
CIN(A)
Input Capacitance
(Address & Control)
V(IN) = OV
70
pF
Write
L
X
L
DATAIN
Active
Read
L
H
H
High-Z
Active
Parameter(1)
Symbol
1/0 Capacitance
ClIO
Conditions
Max.
Unit
V(OUT) =OV
12
Mode
pF
NOTE:
1. This parameter is guaranteed by design but not tested.
2703 tbl 05
27031bl 02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
RECOMMENDED DC OPERATING
CONDITIONS
VTERM
Rating
Terminal Voltage with
Respect to GND
Value
Unit
-0.5 to +7.0
V
Min.
Typ.
Max.
Unit
TA
Operating Temperature
o to +70
°C
Vee
Supply Voltage
4.5
5.0
5.5
V
TSIAS
Temperature Under Bias
-10 to +B5
°C
GND
Supply Voltage
0
0
0
V
TSTG
Storage Temperature
-55 to +125
°C
VIH
Input High Voltage
2.2
6.0
V
lOUT
DC Output Current
50
mA
VIL
Input Low Voltage
-0.5(1)
O.B
V
Symbol
NOTE:
1. VIL (min)
Parameter
-
NOTE:
2703 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2703 tbl 03
=-1 .5V for pulse width less than 10ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
Vee
5.0V ± 10%
2703 Ibl 04
DC ELECTRICAL CHARACTERISTICS
(Vee = 5 OV +10%
TA = O°C to +70°C)
Symbol
lIul
Max.
Unit
Vee = Max.; VIN = GND to Vee
-
BO
IlA
10
IlA
10
IlA
0.4
V
-
V
Test Conditions
Parameter
Input Leakage
(Address and Control)
Min.
lIul
Input Leakage (Data)
Vee = Max.; VIN = GND to Vee
IILOI
Output Leakage
Vee = Max.; CS = VIH, VOUT = GND to Vee
VOL
Output LOW
Vee = Min., IOL = BmA
-
VOH
Output HIGH
Vee = Min., IOH = -4mA
2.4
2703 tbl 07
Symbol
Parameter
Test Conditions
15ns - 25ns
Max.
Unit
1600
1360
rnA
CS ~ VIH, Vee = Max.
Outputs Open, f = fMAX
4BO
4BO
rnA
CS ~ Vee - 0.2V; f = 0
VIN> Vee - 0.2V or < 0.2V
320
120
rnA
f = fMAX; CS = VIL
Dynamic Operating
Current
Vee = Max.; Output Open
ISB
Standby Supply
Current
ISB1
Full Standby
Supply Current
lee
10ns,12ns
Max.
2703 tbl
7.9
2
IDT7MP4045
256K x 32 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
See Figures 1-4
Output Load
2703 tbl 09
+5V
+5 V
480.Q
480.Q
DATAoUT
DATAoUT
255.Q
255.Q
30 pF*
5 pF*
2703 drw 03
2703 drw 04
'Includes scope and jig.
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ,tOHZ, tCHZ, tCLZ, tWHZ, tow)
I
II
L1TAA
(Typical, ns) 5
..:t:.._Y-------,.n
DATA OUT
Zo=50n
i son
1.5V
2703 drw05
20
40
60
80
100
120 140
160 180
200
CAPACITANCE (pF)
Figure 3. Alternate Output Load
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
7.9
3
IDT7MP4045
256Kx 32 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V -+10%, TA = O°C to +70°C)
7MP4045SAxxZ, 7MP4045SAxxM
-10
Symbol
Parameter
Min.
-12
Max.
Min.
Max.
Unit
ns
Read Cycle
tRC
Read Cycle Time
10
-
12
-
tAA
Address Access Time
-
10
12
ns
tACS
tCLZ(1)
Chip Select Access Time
-
10
-
12
ns
Chip Select to Output in Low Z
2
-
tOE
tOLZ(1)
Output Enable to Output Valid
-
5
Output Enable to Output in Low Z
0
tCHZ(1)
Chip Deselect to Output in High Z
-
tOHZ(1)
Output Disable to Output in High Z
-
6
tOH
Output Hold from Address Change
3
-
-
ns
-
7
ns
-
0
-
ns
6
-
7
ns
7
ns
3
-
ns
ns
2
Write Cycle
twc
Write Cycle Time
10
-
12
-
tcw
Chip Select to End of Write
8
-
10
tAW
Address Valid to End of Write
8
-
10
tAS
Address Set-up Time
0
twp
Write Pulse Width
8
10
tWR
Write Recovery Time
1
-
-
tWHZ(l)
Write Enable to Output in High Z
-
5
-
tDW
Data to Write Time Overlap
6
tDH
Data Hold from Write Time
1
toW(1)
Output Active from End of Write
1
-
NOTE:
1. This parameter is guaranteed by design but not tested.
0
1
7
1
1
ns
ns
ns
ns
ns
6
ns
-
ns
ns
ns
2703 tbll0
7.9
4
IDT7MP4045
256K x 32 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vce = 5V ±10%, TA = O°C to +70°C)
7MP4045SxxZ, 7MP4045SxxM
-15
Symbol
Parameter
Min.
-20
Max.
Min.
-25
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
-
20
-
25
-
ns
tAA
Address Access Time
-
15
20
-
25
ns
tACS
Chip Select Access Time
-
15
-
20
-
25
ns
tCLZ(1)
Chip Select to Output in Low-Z
3
-
5
-
5
-
ns
tOE
tOLZ(l)
Output Enable to Output Valid
-
8
-
10
-
12
ns
Output Enable to Output in Low-Z
0
-
0
-
0
-
ns
tCHZ(l)
Chip Deselect to Output in High-Z
8
-
12
ns
Output Disable to Output in High-Z
-
10
tOHZ(l)
-
10
-
10
ns
tOH
tPU(l)
Output Hold from Address Change
3
-
3
0
0
-
0
-
ns
Chip Select to Power-Up Time
-
3
tPO(l)
Chip Deselect to Power-Down Time
-
15
-
20
-
25
ns
25
ns
8
ns
Write Cycle
twc
Write Cycle Time
15
Chip Select to End-of-Write
12
-
20
tcw
tAW
Address Valid to End-of-Write
12
-
15
-
tAS
Address Set-up Time
0
-
0
-
0
-
twp
Write Pulse Width
12
15
-
20
-
ns
tWR
Write Recovery Time
0
-
0
-
0
-
ns
tWHZ(l)
Write Enable to Output in High-Z
-
8
-
13
-
15
ns
tow
Data to Write Time Overlap
10
12
Data Hold from Write Time
0
Output Active from End-of-Write
0
-
ns
tOW(l)
-
15
tOH
-
NOTE:
1. This parameter is guaranteed by design but not tested.
15
0
0
20
20
0
0
ns
ns
ns
ns
ns
2703 tblll
7.9
5
II
IDT7MP4045
256Kx 32 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
----------~
ADDRESS
tACS -------+-----~
tClZ (5) _____
--..j
DATAQUT
--------------------------------------<
2703 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAoUT
~: ~- :~- :~- :~- :~- :- t-O~H~:- - :- - :-t:-A :- ~ t~R:C- - - - - - - -.-I- - -~-t-O-H- - - - PREVIOUS DATA VALID
DATA VALID
2703 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
-~
==1
cs
t w (5)
t
1
tCHZ(S)?
DATAOUT~------I---+«XX*....--------------Jl
2703 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected. CS VIL.
3. Address valid prior to or coincident with CS transition lOW.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
=
7.9
6
IDT7MP4045
256K x 32 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED) (1,2,3,7)
twc
)K
)(
ADDRESS
/
V
tAW
""
tWp(7)
___ tAS
tWR _
"",
f4-
/
(4)
V
tOHZ(6)
tWHZ(6)_
to HZ (6)
DATA OUT
/
/
~
"
tOW(6)_
/
/
"f---
V
DATA IN
I'-
(4)
)
!--
tOH
tow
DATA VALID
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CSCONTROLLED)
"
/
2703 drw 10
(1,2,3,5)
twc
ADDRESS
)
K
)
tAW
~tAS
DATAIN
~
/
<
II
~
tcw
tWR
---------------------------------~r:_=
~ IDW
.!..
DATA VALID
tOH
3)1--2703 drw 11
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (twp) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of twp or (tWHZ + tDW) to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
7.9
7
IDT7MP4045
256Kx 32 BiCMOS/CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
ZIP VERSION
.
r..---------
~I
3.640
3.660
0.365
MAX.
-.,r-
PIN 1
0.100
TYP.
~
0.100
~~ T
TYP.
0.125
0.190
0.050
TYP.
SIDE VIEW
FRONT VIEW
I
I
I
~
COMPONENT AREA
L _____________________________
PIN 1
2703 drw 12
SIMM VERSION
I
~-------__ 3.840
3.860------------~
~------------3.580
_ _ _ _ _ _ _--1~~~
3.588
0.365
MAX.
I
:
COMPONENT AREA
PIN 1
FRONT VIEW
I
L _________________________________ I
0.240
0.260
SIDE VIEW
~---------------------------------,
o :L _________________________________
COMPONENT AREA
:0
I
I
~
BACK VIEW
PIN 1
2703 drw 13
7.9
8
IDT7MP4045 .
256K x 32 BiCMOS/CMOS STATIC RAM MODULE
ORDERING INFORMATION
XXXXX
X
X
lOT
Device
Type
Power
Speed
COMMERCIAL TEMPERATURE RANGE
X
X
Package
Process/
Temperature
Range
IL------11
Blank
L---------tl Z
1M
10
12
15
Commercial (O°C to +70°C) .
FR-4 ZIP (Zig-Zag In-line vertical Package)
FR-4 SIMM (Single In-line Memory Module)
}
Speed in Nanoseconds
~----------------------~20
25
Is
~--------------------~ISA
'----------------------f: 7MP4045
Standard Power
Standard Power (Alternate)
256K x 32 Static RAM Module
2703 drw 14
II
7.9
9
G
128K x 32
CMOS STATIC RAM
MODULE
IDT7MP4095
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 4 megabit static RAM module
• Low profile 64-pin ZIP (Zig-zag In-line vertical Package)
or 64-pin SIMM (Single In-line Memory Module)
• Fast access time: 20ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
The IDT7MP4095 is a 128K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using four
128K x 8 static RAMs in plastic SOJ packages. The
IDT7MP4095 is available with access times as fast as 20ns
with minimal power consumption.
The IDT7MP4095 is packaged in a 64-pin FR-4 ZIP (Zigzag In-line vertical Package) or a 64-pin SIMM (Single In-line
Memory Module). The ZIP configuration allows 64 pins to be
placed on a package 3.65 inches long and 0.21 inches thick.
At only 0.60 inches high, this low-profile package is ideal for
systems with minimum board spacing, while the SIMM configuration allows use of edge mounted sockets to secure the
module.
All inputs and outputs of the IDT7MP4095 are TTL compatible and operate from a single 5V supply. Full asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
• Single 5V (±1 0%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL compatible
PIN CONFIGURATION
PDo- GND
PDl - No Connect
PDo
1/00
1/01
1/02
1/03
Vee
A7
A8
A9
1/04
1/05
1/06
1/07
WE
A14
CSl
CS3
A16
GND
1/016
1/017
1/018
1/019
Al0
All
A12
A13
1/020
1/021
1/022
1/023
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
GND
PDl
1/08
1/09
1/010
1/011
Ao
FUNCTIONAL BLOCK DIAGRAM
Al
A2
1/012
1/013
1/014
1/015
GND
A15
CS2
CS4
NC
OE
1/024
1/025
1/026
1/027
A3
1/00-31
3147 drw 01
PIN NAMES
1/00-31
Data Inputs/Outputs
Ao-16
Addresses
As
CS1-4
Chip Selects
Vee
WE
Write Enable
OE
Output Enable
A4
A6
1/028
1/029
1/030
1/031
Vcc
Power
GND
Ground
NC
No Connect
3147 tbl 01
3147 drw 02
ZIP, SIMM
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology. Inc. All others are property of their respective companies.
COMMERCIAL TEMPERATURE RANGE
MARCH 1995
DSC-7120/1
©1995 Inlegrated Device Technology, Inc.
7.10
1
IDT7MP4095
128K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA =+25 C, F = 1.0MHz)
TRUTH TABLE
D
Parameter(1)
Symbol
Conditions
Max.
Unit
Mode
CS
OE
WE
Output
Power
H
X
X
High Z
Standby
L
L
H
DATAoUT
Active
L
X
L
DATAIN
Active
H
H
High-Z
Active
CIN(D)
Input Capacitance
(Data and CS)
V(IN) = OV
12
pF
Standby
Read
CIN(A)
Input Capacitance
(Address, WE, OE)
V(IN) = OV
40
pF
Write
COUT
Output Capacitance
V(OUT) = OV
12
pF
Read
L
NOTE:
3147 tbl 02
3147 tbl 04
1. This parameter is guaranteed by design but not tested.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
RECOMMENDED DC OPERATING
CONDITIONS
VTERM
Rating
Terminal Voltage with
Respect to GND
Value
Unit
-0.5 to +7.0
V
°C
Min.
Typ.
Max.
Unit
TA
Operating Temperature
o to +70
Vee
Supply Voltage
4.5
5.0
5.5
V
T81As
Temperature Under Bias
-10 to +85
°C
GND
Supply Voltage
0
0
0
V
TSTG
Storage Temperature
-55 to +125
°C
VIH
Input High Voltage
2.2
-
5.8
V
lOUT
DC Output Current
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
NOTES:
Parameter
Symbol
NOTE:
1. V,L (min)
3147 tbl 05
=-3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
O°C to +70°C
OV
50
mA
3147 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Vee
5.0V ± 10%
3147 tbl 06
DC ELECTRICAL CHARACTERISTICS
(Vce
=5.0V +10%,
TA = oDe to +70°C)
-
Symbol
Parameter
ilL/I
Input Leakage
ilL/I
Input Leakage
Test Conditions
=Max.; VIN
Min.
Max.
Unit
= GND to Vee
-
10
JlA
Vee = Max.; VIN = GND to Vee
-
40
JlA
10
JlA
Vee
(Data and CS)
(Address, WE, and OE)
IILOI
Output Leakage
Vee = Max.; CS = VIH, VOUT = GND to Vee
VOL
Output Low
Vee = Min., IOL = 8mA
-
0.4
V
VOH
Output High
Vee = Min., IOH = -4mA
2.4
-
V
Symbol
Parameter
Test Conditions
Max.
Unit
Icc
Dymanic Operating
f = fMAX; CS = VIL
680
mA
Current
Vee = Max.; Output Open
IS8
Standby Supply
Current
CS ~ VIH. Vee = Max.
Outputs Open, f = fMAX
160
mA
IS81
Full Standby
Supply Current
CS ~ Vee - 0.2V; f = 0
VIN> Vee - 0.2V or < 0.2V
60
mA
3147 tbl 07
7.10
2
II
I
IDT7MP4095
128K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 and 2
3147 tbl 08
+5 V
+5 V
4800
4800
DATA
DATA
OUT--------~------~
2550
OUT--------~------~
2550
30 pF*
5 pF*
3147drw03
* Includes scope and jig.
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ, tOHZ, tCHZ, tCLZ,
tWHZ, tOW)
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±1 0%, TA = ODC to +70DC)
-20
Symbol
Parameter
Read Cycle
Min.
-25
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
20
-
25
-
ns
tM
Address Access Time
20
-
25
ns
tACS
tCLZ(1)
Chip Select Access Time
-
20
-
25
ns
Chip Select to Output in Low Z
3
-
3
-
ns
tOE
Output Enable to Output Valid
-
10
-
12
ns
tOLZ(1)
Output Enable to Output in Low Z
0
-
0
-
ns
tCHZ(1)
Chip Deselect to Output in High Z
-
12
-
15
ns
tOHZ(1)
Output Disable to Output in High Z
-
12
-
15
ns
tOH
tPU(1)
Output Hold from Address Change
3
3
0
0
-
ns
Chip Select to Power-Up Timo
-
tPO(1)
Chip Deselect to Power-Down Time
-
20
-
25
ns
ns
Write Cycle
twc
Write Cycle Time
20
-
25
-
ns
tcw
Chip Select to End of Write
18
20
-
ns
tAW
Address Valid to End of Write
18
20
Address Set-up Time
0
twp
Write Pulse Width
18
20
-
ns
tAS
tWR
tWHZ(1)
Write Recovery Time
3
-
3
-
ns
Write Enable to Output in High Z
-
13
-
15
ns
tow
Data to Write Time Overlap
12
15
-
ns
tOH
toW(1)
Data Hold from Write Time
0
0
-
ns
Output Active from End of Write
0
-
0
-
NOTE:
1. This parameter is guaranteed by design, but not tested.
0
ns
ns
ns
3147 tbl10
7.10
3
IDT7MP4095
128K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
DATAoUT--------------------------------~
3147 drw 04
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~~~---------------tRC---------------4~~
ADDRESS
DATA OUT
t: -=-~=-=-~=-=-~=-=-~- t-O-=-H-=-~=-=-~ t-A-A~ - J=:- --------~--~~~~~.-I---: C-tO-H---DATA VALID
PREVIOUS DATA VALID
3147 drw 05
II
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
3147 drw 06
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.10
4
IDT7MP4095
128Kx 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2, 3, 7)
twc
ADDRESS
)K
=>K
/1{'
tAW
~K.
//
tWp(7)
-tAS
tWR'-'
~"
f.4- t WHZ (6)...
/~
tOHZ(6)
tOW(6)
tOHZ(6)
DATA OUT
(4)
V
"'/
tow--
DATA IN
f'
"
~
DATA VALID )
(4)
)~
3147 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS
=><
-tAS
)(
tAw
1
//
tcw
DATAIN __________________________--(~
tWR
tow
~I
I
..
tOH
DATA VALID
1»------
3147 drw08
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. tWA is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twHZ + tDW).
7.10
5
IDT7MP4095
128K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
SIMM VERSION
3.574
..
~:~~~~
r----
=1l
7
~
EJ EJ EJ EJ
3.594
1
0.250
TYP.
-.J I+-
0.050
TYP.
-.j
+
9
r-__ I
0.21°1
0.390
0.410
M:
5
0.055
1
11111111111111111111111111111111
~
11111111111111111111111111111111
,
BACK VIEW
•
0.060
0.064
II+-
SIDE VIEW
FRONT VIEW
0
1__
I
PI~
7'\
0.062 R
1
3147 dlW 09
ZIP VERSION
I...
~I
3.640
3.660
O.210~ ~
MAX.
0.100
TYP.
II
~
---.11..-["""I""""
SIDE VIEW
FRONT VIEW
BACK VIEW
3147 dlW 10
7.10
6
IDTIMP4095
128K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
XXXXX
x
x
x
x
Device
Type
Power
Speed
Package
Process/
Temperature
Range
YBlank
1 . -_ _ _ _ _ _ _
--11 M
IZ
-IJ 20
25
I . - -_ _ _ _ _ _ _ _ _ _
Commercial (O°C to +70°C)
FR-4 SIMM (Single In-line Memory Module)
FR-4 ZIP (Zig-zag In-line Package)
}speed in Nanoseconds
1
1.----------------1: S
' - - - - - - - - - - - - - - - - - - - - - - i · l 7MP4095
Standard Power
128K x 32 Static RAM Module
3147 drw 11
7.10
7
(;)®
PRELIMINARY
IDT7M4084
2M xB
CMOS STATIC RAM
MODULE
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
High-density 16 megabit (2M x 8) Static RAM module
Equivalent to the JEDEC standard for future monolithic
Fast access time: 55ns (max.)
Low power consumption
- Active: 110mA (max.)
- CMOS Standby: 450~ (max.)
- Data Retention: 250llA (max.) Vee =2V
• Surface mounted plastic packages on a 36-pin, 600 mil
FR-4 DIP (Dual-In-Line Package) substrate
• Single 5V (±1 0%) power supply
• Inputs/outputs directly TTL-compatible
The IDT7M4084 is a 16 megabit (2M x 8) Static RAM
module constructed on a co-fired ceramic substrate using
four 512K x 8 Static RAMs and a decoder. The IDT7M4084
is available with access times as fast as 55ns, and a data
retention current of 250~ and a standby current of 450JlA.
The IDT7M4084 is packaged in a 36-pin ceramic DIP
resulting in the same JEDEC footprint in a package 1.8
inches long and 0.6 inches wide.
All inputs and outputs of the7M4084 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
Ao
Al
A2
A3
A4
ADDRESS
CS--~
2M xB
RAM
es
1/00
1/01
WE
OE--~
1/0
A20
A19
AlB
A17
A16
OE
1/07
1/06
Vee
GND
GND
Vee
1/02
1/03
1/05
1/04
WE
As
A6
A7
AB
A9
A1S
A14
A13
A12
All
Ala
2794 drw 01
II
2794 drw 02
DIP
TOP VIEW
PIN NAMES
1/00·7
Data Inputs/Outputs
AO-20
Addresses
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vcc
Power
GND
Ground
2794 tbl 01
The lOT logo Is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
APRIL 1995
101995 Integrated Device Technology, Inc.
Dse-7095/1
7.11
IDT7M40B4
2M xB CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE
CS
OE
WE
Output
Power
Symbol
Standby
H
X
X
High-Z
Standby
VTERM
Read
L
L
H
DOUT
Active
Read
L
H
H
High-Z
Active
Terminal Voltage
with Respect
to GND
L
X
TA
Write
L
DIN
Active
Mode
2794 tbl 02
CAPACITANCE(1) (TA =+25 C, f =1 OMHz)
D
Symbol
CIN
Parameter
Conditions
Typ.
Unit
=OV
VIN = OV
VOUT = OV
35
pF
8
pF
35
pF
Input Capacitance
VIN
CIN(e)
Input Capacitance (CS)
COUT
Output Capacitance
NOTE:
1. This parameter is guaranteed by design, but not tested.
Parameter
2794 tbl 03
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
Commercial
Unit
-0.5 to +7.0
V
Operating
Temperature
o to +70
°C
TBIAS
Temperature
Under Bias
-10 to +85
°C
TSTG
Storage
Temperature
-55 to +125
DC
lOUT
DC Output Current
50
mA
NOTE:
2794 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Rating
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
GND
Vee
DoC to +70°C
OV
5V± 10%
2794 tbl 06
NOTE:
1. VIL = -2.0V for pulse width less than 10ns.
2794 tbl 04
DC ELECTRICAL CHARACTERISTICS
(VCC
=5V ± 10%, TA =oDe to +70DC)
7M4084LxxN
Symbol
Parameter
Ilul
Input Leakage
IILol
Output Leakage
VOL
Output Low Voltage
VOH
Output High Voltage
lee
Dynamic Operating Current
ISB
Standby Supply Current
(TIL Levels)
ISB1
Full Standby Supply Current
(CMOS Levels)
Test Conditions
= Max., VIN = GND to Vee
Vee = Max., CS =VIH,
VOUT = GND to Vee
Vee = Min., 10L = 2mA
Vee = Min., 10H = -1 mA
Vee = Max., CS ~ VIL; f =fMAX,
CS ~ VIH, Vee =Max., f = fMAX,
Vee
Min.
Max.
Unit
-
20
Il A
20
IlA
V
-
0.4
2.4
-
-
110
mA
12
mA
-
450
IlA
V
Outputs Open
CS ~ Vee - 0.2V, VIN ~ Vee - 0.2V
or ~ 0.2V
2794 tbl 07
7.11
2
IDT7M4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS
(TA =ooe to +70°C)
Symbol
Parameter
Min.
Test Condition
-
VDR
Vee for Data Retention
leeDR
Data Retention Current
CS ~ Vec - 0.2V
tCDR(2)
Chip Deselect to Data Retention Time
VIN::::; Vcc - 0.2V or
tR(2)
Operation Recovery Time
VIN
~
Unit
2.0
-
V
-
250
IlA
-
ns
0
tRC(1)
0.2V
Max.
Vee @ 2.0V
ns
NOTES:
1. tAC = Read Cycle Time.
2. This parameter is guaranteed by design, but not tested.
2794 tbt 08
DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VOR~
2V
VOR
2794 drw 03
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
II
1.5V
See Figures 1 and 2
2794 tbl 09
+5V
+5V
~
~
480Q
DATAoUT--------~------~
DATAoUT--------~------~
255Q
.I
480Q
255Q
30W
5 pF*
/.
2794 drw05
2794 drw 04
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ, tCHZ, tOHZ, tWHZ, tow and teLZ)
7.11
3
IDT7M4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Vee
=5V ± 10%, TA =O°C to +70°C)
7M4084LxxN
-55
Symbol
Parameter
Min.
-85
-70
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
55
-
70
-
85
-
tAA
Address Access Time
55
-
70
ns
Chip Select Access Time
55
-
70
-
85
tACS
85
ns
tOE
tOHZ(1)
Output Enable to Output Valid
30
-
45
-
48
ns
Output Disable to Output in High-Z
-
20
-
30
-
33
ns
tOLZ(1)
Output Enable to Output in Low-Z
5
-
5
Chip Select to Output in Low-Z
5
-
5
-
ns
tCLZ(1)
-
tCHZ(1)
Chip Deselect to Output in High-Z
-
20
-
40
43
ns
tOH
Output Hold from Address Change
5
Chip Select to Power-Up Time
0
-
5
tPU(1)
0
-
-
ns
tPO(1)
Chip Deselect to Power-Down Time
-
55
-
70
-
85
ns
ns
0
-
-
33
ns
0
5
5
0
ns
ns
ns
Write Cycle
twc
Write Cycle Time
55
-
85
Write Pulse Width
55
-
70
twp
55
65
tAS
Address Set-up Time
5
-
0
tAW
Address Valid to End-of-Write
50
65
tcw
Chip Select to End-of-Write
50
tow
Data to Write Time Overlap
20
0
-
-
30
tOH
Data Hold Time
0
tWR
tWHZ(1)
Write Recovery Time
0
-
Write Enable to Output in High-Z
-
20
tOW(1)
Output Active from End-of-Write
5
-
NOTE:
1. This parameter is guaranteed by design, but not tested.
65
35
0
0
-
2
82
80
38
0
0
-
ns
ns
ns
ns
ns
ns
ns
ns
2794 tbll0
7.11
4
IDT7M4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
tRC
---------~~
ADDRESS
DATAoUT
-----------------------------------~
2794 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC - - - - - - - - - - - . . j
ADDRESS
tAA--------~
tOH ------I~
tOH
DATAoUT
I
2794 drw 07
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
CS---...
----Ll-----~
::~~~~~~~~_- (_5)_-_-_-_-_-_-_-_-_-_-_-_~_.~~------------t-CH-Z-(-5)-9_
tACS
DATAoUT _______
__tC_LZ
__
2794 drw 08
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
=
7.11
5
II
IDT7M4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING}(1, 2, 3, 7)
twc
ADDRESS
)/
)(
" k"
/'
~
,
4-
tAW
/'
twp
tAS
(7)
tWR-
~'\..
_
/'
tWHZ(6) .....
(4)
~
tOHZ (6)
tow (6)
tOHZ (6)
DATAoUT
/
"-
(4)
/
tOH
)-
"-- tow-
'/'
DATAIN
r'\.
"
DATA VALID
/
2794 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING}(1, 2, 3, 5)
wc
ADDRESS
)K
)(
tAW
/
_tAS
"}
/
tcw
DATAIN __________________________________
tWR
~~
tow
~!
..
DATA VALID
2794 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (twp) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, 1/0 pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater of twp or tWHZ + tDW to allow the 1/0 drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
7.11
6
IDT7M4084
2M x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
I
1.790
I..
0.580
0.600
1.810
--I~~I
;-R'l
LI:::I~
L:::::::::===-===:::::!I
TOP VIEW
0.385
MAX.
Li
0.005
0.015
Pin1
00405
MAX.
SIDE VIEW
Yr~!I,llI+!+'
~IIII WIIII~
~
~
, I
0.035
0.065
0.590
0.620
I"
0.007
0.Q13
0.175
0.015
0.025
~
I-I
0.100
TYP.
-.1+-
~I
BonOMVIEW
2794 drw 11
ORDERING INFORMATION
lOT
XXXX
A
999
A
Device
Type
Power
Speed
Package
- - - --- --- - - -
- -A- Process/
Temperature
Range
-------il
1,-
Blank
Commercial (O°C to +70°C)
N
SOs mounted on an ceramic DIP
70
55
85
}
II
I
L . -_ _ _ _ _ _ _ _----j
L . -_ _ _ _ _ _ _ _ _ _ _----j
--I L
L . -_ _ _ _ _ _ _ _ _ _ _ _ _ _
L...-----_____________- l
Speed in Nanoseconds
Low Power
7M4084 2M x 8 Static RAM Module
2794 drw 12
7.11
7
G®
IDT7MB4048
512K x 8
CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-density 4-megabit (S12K x 8) Static RAM module
• Fast access time: 2Sns (max.)
Surface mounted plastic packages on a 32-pin, 600 mil
FR-4 DIP substrate
• Single SV (±1 0%) power supply
• Inputs/outputs directly TTL-compatible
The IDT7MB4048 is a 4-megabit (S12K x 8) Static RAM
module constructed on a multilayer epoxy laminate (FR-4)
substrate using four 1 megabit SRAMs and a decoder. The
I DT7MB4048 is available with access times as fast as 2Sns.
The IDT7MB4048 is packaged in a 32-pin FR-4 DIP resulting
in the JEDEC footprint in a package 1.6 inches long and 0.6
inches wide.
All inputs and outputs of the IDT7MB4048 are TTL-compatible and operate from a single SV supply. Fully asynchronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
A18
A16
A11
A12
A7
A6
As
A4
A3
A2
A1
Vcc
A1S
A17
WE
A13
A8
A9
A11
OE
A10
CS
1/07
1/06
I/Os
1/04
1/03
Ao
1/00
1/01
1/02
GND
ADDRESS
19
512K X 8
RAM
CS
WE
OE
8
I/O
2675 dew 02
2675 drw 01
DIP
TOP VIEW
PIN NAMES
1/00-7
Data Inputs/Outputs
AO-18
Addresses
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vcc
Power
GND
Ground
2675 tbl 01
The IDT logo Is a registered trademark of Integrated Device Technology Inc.
MARCH 1995
COMMERCIAL TEMPERATURE RANGE
DSC-7047/5
©1995 Integrated Device Technology. Inc.
7.12
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE
Output
Power
Symbol
X
WE
X
High-Z
Standby
VTERM
L
L
H
DOUT
Active
Terminal Voltage
with Respect
to GND
Read
L
H
H
High-Z
Active
TA
Write
L
X
L
DIN
Active
Mode
CS
OE
Standby
H
Read
2675 tbl 02
CAPACITANCE (1} (TA =+25°C, f = 1.0MHz
Symbol
CIN
Parameter
Conditions
Typ.
Unit
VIN = OV
35
pF
Input Capacitance
«;8)
CIN(e)
Input Capacitance
COUT
Output Capacitance
VIN = OV
B
VOUT= OV
35
NOTE:
1. This parameter is guaranteed by design, but not tested.
pF
pF
2675 tbl 03
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Vee
Supply Voltage
GND
Supply Voltage
Min.
Typ.
Max.
Unit
4.5
5
5.5
V
0
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
0
-
0
Commercial
Unit
-0.5 to +7.0
V
Operating
Temperature
o to +70
°C
TBIAS
Temperature
Under Bias
-10 to +B5
°C
TSTG
Storage
Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
NOTE:
2675 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation ofthe device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
V
6
V
O.B
V
Rating
Commercial
Ambient
Temperature
GND
Vee
O°C to +70°C
OV
5V± 10%
2675 tbl 06
NOTE:
1. VIL =-2.0V for pulse width less than 10ns.
2675 tbl 04
II
DC ELECTRICAL CHARACTERISTICS
(Vec =5V ± 10%, TA =O°C to +70°C)
7MB4048SxxP
Symbol
Parameter
Max.
Unit
-
B
JlA
B
JlA
Vee = Min., IOL = BmA
-
0.4
V
Vee = Min., IOH =-1mA
2.4
-
V
Dynamic Operating Current
Vee = Max., CS ~ VIL; f = fMAX,
Outputs Open
-
4BO
rnA
ISB
Standby Supply Current
(TIL Levels)
CS ~ VIH, Vee = Max., f = fMAX,
Outputs Open
-
250
mA
IS81
Full Standby Supply Current
(CMOS Levels)
CS ~ Vee - 0.2V, VIN
or~ 0.2
-
170
rnA
Test Conditions
lIul
Input Leakage
Vee = Max., VIN = GND to Vee
IlLOI
Output Leakage
Vee = Max., CS = VIH,
VOUT = GND to Vee
VOL
Output Low Voltage
VOH
Output High Voltage
lee
~
Vee - 0.2V
Min.
2675 tbl 07
7.12
2
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2
2675 tbl 09
+5 V
+5 V
~
~
480(2
DATAouT--------.-------~
DATAoUT--------.-------~
255(2
2550
4800
5 pF*
2675 drw 05
2675 drw 04
Figure 2. Output Load
(for tOLZ, tCHZ, tOHZ, tWHZ, tow and tcLZ)
Figure 1. Output Load
AC ELECTRICAL CHARACTERISTICS
(Vee =5V ± 10%, TA =ooe to +70°C)
7MB4048
-25
Symbol
Read Cycle
Parameter
-30
Min. Max.
Min.
-35
Max.
Min. Max. Unit
tRC
Read Cycle Time
25
-
30
-
35
-
ns
tAA
Address Access Time
25
-
35
ns
Chip Select Access Time
30
-
35
ns
tOE
Output Enable to Output Valid
-
12
15
-
15
ns
tOHZ(1)
Output Disable to Output in High-Z
-
12
-
30
tACS
-
12
-
15
ns
tOLZ(1)
Output Enable to Output in Low-Z
0
0
-
0
Chip Select to Output in Low-Z
5
5
-
5
-
ns
tCLZ(1)
-
tCHZ(1)
Chip Deselect to Output in High-Z
-
14
-
16
-
20
ns
tOH
tPU(1)
Output Hold from Address Change
3
-
3
3
-
ns
Chip Select to Power-Up Time
0
-
0
-
0
-
ns
tpo(1)
Chip Deselect to Power-Down Time
-
25
-
30
-
35
ns
35
ns
0
-
25
ns
Write Cycle
twc
Write Cycle Time
25
-
30
twp
Write Pulse Width
17
-
20
-
25
tAS(2)
Address Set-up Time
3
-
0
-
0
tAW
Address Valid to End-of-Write
20
-
25
30
tcw
Chip Select to End-of-Write
20
-
25
tow
tOH(2)
Data to Write Time Overlap
15
17
Data Hold Time
0
tWR(2)
Write Recovery Time
0
-
0
-
0
-
ns
tWHZ(1)
Write Enable to Output in High-Z
-
15
-
15
-
15
ns
toW(1)
Output Active from End-of-Write
2
-
5
-
5
-
ns
NOTES
1. This parameter is guaranteed by design, but not tested.
2. tAS=Ons for
controlled write cycles. tDH, tWR= 3ns for
es
0
30
20
ns
ns
ns
ns
ns
ns
2675 tbll0
es controlled write cycles.
7.12
3
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
~----------
tRC
----------i~
ADDRESS
DATAoUT
2675 drw 06
TIMING WAVEFORM OF READ CYCLE NO.
2(1,2,4)
tRC
ADDRESS
tAA
~-----
tOH -
tOH--~
_ _ _ _-..1
DATAoUT
2675 drw07
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
l
~cs
: ==========_tC_L_Z_(5_)_-_-_-_-_-_-_-_-_-_-_-_-I":Kxx~-----_tC-H-Z-(-5)-5-
DATAoUT _ _ _ _
2675 drw 08
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition LOW.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.12
4
II
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2,3,7)
twc
ADDRESS
K
)
)(
/
~
tAW
~
/'
i'..
r---
twp
tAS
~,
_
(7)
tWR...:.....
/' ~
tWHZ(6) __
tOHZ (6)
tow (6)
tOHZ (6)
DATAoUT
(4)
~
l
"'
/
r
tOH
(4)
) I-
tow-
DATAIN
f'.
"/'
DATA VALID
2675 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS
)K
/
) i'\..
tAw
~tAS
/
"}
tWR
tcw
tow
DATAIN
/
-------«
•
I •
DATA VALID
tOH
3)1----2675 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (twp) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must bethe larger oftwp or (tWHZ+toW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tow. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified twP.
7.12
5
IDT7MB4048
512Kx 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
r-
1.590
1.610
----.j
I
g::~g II e:::::~::::::J I
TOP VIEW
SIDE VIEW
0.590
0.620
BOTTOM VIEW
2675 drw 11
ORDERING INFORMATION(1)
lOT
XXXX
999
- -A- - -ADevice Power Speed Package
Type
A
Process/
Temperature
Range
IL.-___~I Blank
L...-_ _ _ _ _ _~ P
25
L...----------f 30
Commercial (DOC to +70°C)
SOJs mounted on an FR-4 DIP
}
Speed in Nanoseconds
35
L...-------------IS
Standard Power
L . . . - - - - - - - - - - - - - - - - I 7 M B 4 0 4 8 512K x 8 Static RAM Module (FR-4 substrate)
2675 drw 12
7.12
6
G®
512K x 8
CMOS STATIC RAM MODULE
IDT7M4048
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-density 4 megabit CMOS Static RAM module
• Equivalent to the JEDEC standard for future monolithic
512K x 8 StaticRAMs
• Fast access time: 25ns (max.)
• Surface mounted LCCs (lead less chip carriers) on a 32pin, 600 mil ceramic DIP substrate
• Single 5V (±1 0%) power supply
• Inputs/outputs directly TTL-compatible
The IDT7M4048 is a 4 megabit (512K x 8) CMOS Static
RAM module constructed on a co-fired ceramic substrate
using four 1 Megabit Static RAMs and a decoder. The
I DT7M4048 is available with access times as fast as 25ns.
The IDT7M4048 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 4 megabits into the JEDEC DIP footprint.
All inputs and outputs of the IDT7M4048 are TTL-compatible and operate from a single 5V supply. Fully asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
All IDT military module semiconductor components are
manufactured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
19
CS
512K x 8
RAM
WE
OE
va
I/O
2822 drw 01
The lOT logo is a registered trademark of Integrated Device Technology Inc.
MARCH 1995
MILITARY TEMPERATURE RANGE
DSC-707413
©1995 Integrated Device Technology. Inc.
7.13
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
PIN CONFIGURATION
PIN NAMES
A1S
A16
A14
A12
VCC
A7
A6
As
A4
A3
A2
A1
Ao
1/00-7
Data InputslOutputs
AO-18
Addresses
A1S
GS
Chip Select
A17
WE
Write Enable
WE
A13
As
OE
Output Enable
Vee
Power
A9
GND
Ground
A11
OE
A10
CS
2822 tbl 04
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
1/00
1/06
VTERM
-0.5 to +7.0
V
1/01
1/05
1/04
1/03
Terminal Voltage
with Respect
to GND
TA
Operating
Temperature
-55 to +125
°C
TBIAS
Temperature
Under Bias
-65 to +135
°C
TSTG
Storage
Temperature
-65 to +160
°C
lOUT
DC Output Current
1/02
GND
2822 drw 02
DIP
TOP VIEW
TRUTH TABLE
CS
OE
Standby
H
X
WE
X
Read
L
L
Read
L
H
Write
L
X
Mode
Unit·
1/07
Rating
Military
mA
50
NOTE:
Output
Power
High-Z
Standby
H
DOUT
Active
H
High-Z
Active
L
DIN
Active
2822 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation ofthe device atthese or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2822 tbl 01
CAPACITANCE (1)
Symbol
CIN
(TA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
=+25°C f = 1.0MHz
Conditions
Parameter
VIN = OV
IrlPut Capacitance
CIN(C)
Input Capacitance (CS)
GOUT
Output Capacitance
Typ.
50
Unit
pF
VIN = OV
10
pF
VOUT= OV
40
pF
NOTE:
Grade
Military
Ambient
Temperature
GND
Vee
-55°G to + 125°C
OV
5V± 10%
2822 tbl 06
2822 tbl 02
1. This parameter is guaranteed by design, but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Unit
Min.
Typ.
Max.
Vee
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
NOTE:
-
6
V
0.8
V
2822 tbl 03
1. VIL= -1.5V for pulse width less than 10ns.
7.13
2
•
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
Vce
=5V ± 10%, TA =-55°C to +125°C)
7M4048SxxCB
Symbol
Parameter
Test Conditions
lIul
Input Leakage
IILOI
Output Leakage
=Max., VIN =GND to Vee
Vee =Max., CS =VIH,
VOUT =GND to Vee
Vee =Min., IOL =8mA
Vee =Min., IOH =-4mA
Vee =Max., CS :0; VIL; f =fMAX,
VOL
Output Low Voltage
VOH
Output High Voltage
lee
Dynamic Operating Current
Min.
Vee
Max.
Unit
-
20
IlA
-
20
IlA
-
0.4
V
2.4
-
V
-
300
mA
-
160
mA
-
85
mA
Outputs Open
=Max., f =fMAX,
ISB
Standby Supply Current
(TTL Levels)
CS;?: VIH, Vee
Outputs Open
ISB1
Full Standby Supply Current
(CMOS Levels)
CS;?: Vee - 0.2V, VIN ;?: Vee - 0.2V
or:o; 0.2V, Vee Max., f 0, Outputs Open
=
.
=
2822 tbl 07
AC TEST CONDITIONS
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
See Figures 1 and 2
Output Load
2822 tbl 08
+5V
+5V
48011
48011
DATA OUT------tJ-------..
25511
DATAOUT-----4~------.
30pF'
25511
5pF
2822 drw 03
2822 drw 04
• Including scope and jig capacitances
Figure 2. Output Load
(for tOLZ, tCHZ, tOHZ, tWHZ, tow and tCLl)
Figure 1. Output Load
7.13
3
IDT7M4048
S12K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Vee = 5V ± 10%, TA = -55°C to +125°C)
-2S(;Jj
Symbol
Read Cycle
Parameter
Min.
Max.
7M4048SxxCB
-30
Min.
-35
Max.
Min.
Max. Unit
tRC
Read Cycle Time
25
-
30
-
35
-
tAA
Address A~cess Time
-
25
-
30
35
ns
tACS
Chip Select Access Time
-
25
-
30
-
35
ns
tOE
Output Enable to Output Valid
-
15
-
15
ns
Output Disable to Output in High-Z
-
12
tOHZ(l)
12
-
12
-
15
ns
tOLZ(1)
Output Enable to Output in Low-Z
0
0
5
5
5
-
ns
Chip Select to Output in Low-Z
-
0
tCLZ(l)
-
tCHZ(l)
Chip Deselect to Output in High-Z
-
14
-
16
-
20
ns
tOH
tpu(1)
Output Hold from Address Change
3
3
0
0
-
3
Chip Select to Power-Up Time
-
0
-
ns
tpo(1)
Chip Deselect to Power-Down Time
-
25
-
30
-
35
ns
30
35
25
-
30
25
30
0
-
0
-
ns
25
3
-
ns
ns
ns
ns
Write Cycle
twc
Write Cycle Time
25
twp
Write Pulse Width
17
tAS(2)
Address Set-up Time
3
tAW
Address Valid to End-of-Write
20
tcw
Chip Select to End-of-Write
20
tow
tOH(2)
Data to Write Time Overlap
15
Data Hold Time
0
tWR(2)
Write Recovery Time
0
-
tWHZ(l)
Write Enable to Output in High-Z
-
15
-
15
-
15
tow(1)
Output Active from End-of-Write
3
-
3
-
3
-
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. tAS Ons for es controlled write cycles. tDH , tWR 3ns for es controlled write cycles.
3. Preliminary specifications only.
=
20
17
0
3
20
0
ns
ns
ns
ns
ns
ns
ns
ns
2822 tbl 09
=
7.13
4
II
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
~---------------tRC--------------~
ADDRESS
DATAoUT
---------------------------<
TIMING WAVEFORM OF READ CYCLE NO.
2822 drw 05
2(1,2,4)
~----------------tRC----------------~
ADDRESS
~------------- tAA --------------~
~-------tOH--------~
DATA OUT
2822 drw 06
TIMING WAVEFORM OF READ CYCLE NO.
CS1"'"------_
3(1,3,4)
-------+1
(5) ________
r:-----~~-------tCLZ
tACS
~
DATAoUT---------------~
-------
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE= VIL.
5. Transition is measured ±200mV from steady state. This parameter is guranateed by design, but not tested.
=
7.13
5
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2,3, 7)
twc
ADDRESS
~K
)K
/
It'
tAW
~
/It'
~
tWp(7)
~tAS
tWR--
~,
/V
~tWHZ(6) ...
tOHZ(6)
tOW(6)
tOHZ(6)
DATA OUT
(4)
l
"
/
r
tOH
tow _ _ ~
DATA IN
['\
DATA VALID
(4)
)~
)
2822 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS
)K
~K
tAW
/
I+-'AS " }
V
tcw
II
tWR
I
DATAIN ____________________________
~~
tow
~I
..
tOH
DATA VALID
])1-----
2822 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (twp) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, the write pulse width must be the larger of twp or (tWHZ + tow) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tow. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified twP.
7.13
6
IDT7M4048
512K x 8 CMOS STATIC RAM MODULE
MILITARY TEMPERATURE RANGE
PACKAGE DIMENSIONS
'"""1----
1.680
1.720
~1
- - - - - t..
TOP VIEW
PIN 1
0005
0.040
~
I.. _I
0.035
0.065
0.015
0.025
0.007
0.013
0.100
TYP.
-+
0.590
0.620
END VIEW
SIDE VIEW
BOTTOM VIEW
2822 drw 10
ORDERING INFORMATION
IDT
XXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
1L....--------i!B
!
l...-------------i C
' - - - - - - - - - - - - - - - - - i 25
30
Military (-55°C to +125°C)
Semiconductor component compliant
to MIL-STD-883, Class B
Sidebrazed DIP (Dual In-line Package)
} Speed in Nanoseconds
35
l...--------------------i S
' - - - - - - - - - - - - - - - - - - - - - - - 1 7M4048
Standard Power
512K x 8 CMOS Static RAM Module
2822 drw 11
7.13
7
One 800# does it all!
Dial 1-800-345-7015 to contact either your local sales office or corporate
headquarters. Dial the 800 number above, then follow the instructions to be
routed to your local sales office or corporate headquarters, and an operator will
assist you in contacting technical support or customer service.
DOMESTIC SALES REPRESENTATIVES
ALABAMA
/DT
555 Sparkman Drive
Suite 1238
Huntsville, AL 35816
ALASKA
Thorson Pacific, Inc.
14575 Bel-Red Road
Ste.102
Bellevue, WA 98005
ARIZONA
Western High Tech Mktg.
9414 E. San Salvador
Suite 206
Scottsdale, AZ. 85258
ARKANSAS
IDT
(S. Cen. Regional Office)
15851 Dallas Pkwy.,
Suite 1100
Dallas, TX 75248
CALIFORNIA
lOT
(Corporate Headquarters)
2975 Stender Way
P.O. Box 58015
Sa.nta Clara, CA 95052
/DT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
lOT
(SW Regional Office)
6 Jenner Drive
Suite 100
Irvine, CA 92718
/DT
(SW Regional Office)
17609 Ventura Blvd.
Suite 300
Encino, CA 91316
Quest-Rep
6494 Weathers Place
Suite 200
San Diego, CA 92121
CANADA
(EASTERN)
Dynasty Components
110-1140 Morrison Drive
Ottawa, Ontario
Canada K2H 8S9
Dynasty Components
2339 Otami Trail
Mississauga, Ontario
Canada L5H 3N2
Dynasty Components
1870 Sources Boulevard
Suite 202
Pointe Claire, Quebec
Canada H9R 5N4
CANADA
(WESTERN)
Thorson Co. Northwest
4170 Still Creek Drive
Ste.200
Burnaby, British Columbia
Canada V5C 6C6
Dynasty Components
2 Mtn. River Estates
Ste 17, R.P. #2
P.O. Box 14
Calgary, Alberta
Canada T2P 2G5
Dynasty Components
1502-2041 Bellwood Ave
Burnaby, BC Canada
V5B 4V5
COLORADO
lOT
5299 DTC Blvd., Ste 350
Inglewood, CO 80111
Thorson Rocky Mountain
7108 "D" S. Alton Way
Suite A
Englewood, CO 80112
CONNECTICUT
SJ New England
10 Copper Ridge Circle
Guilford, CT 06437
SJ New England
15 Coventry Lane
Naugatuck, CT 06770
DELAWARE
/DT
(SE Regional Office)
Horn Point Harbor
105 Eastern Avenue
Suite 201
Annapolis, MO 21403
S-J Mid Atlantic, Inc.
131-D Gaither Drive
Mt. Laurel, NJ 08054
FLORIDA
INDIANA
MARYLAND
lOT
(SE Headquarters)
1413 S. Patrick Drive
Suite 10
Indian Harbor Beach, FL
32937
Arete Sales
2260 Lake Avenue
Suite 250
Ft. Wayne, IN 46805
/DT
(SE Regional Office)
Horn Point Harbor
105 Eastern Avenue
Suite201
Annapolis, MO 21403
/DT
18167 U.S. 19 North
Suite 455
Clearwater, FL 34624
lOT
1500 N. W. 49th Street
Suite 500
Ft. Lauderdale, FL 33309
Arete Sales
P.O. Box 24796
Indianapolis, IN 46224
IOWA
Rep Associates
4905 Lakeside Drive N.E.
Suite 107
Cedar Rapids, IA 52402
GEORGIA
Rush and West Assoc.
4537 Brandy St.
Davenport, IA 52807
lOT
(SE Regional Office)
18167 U.S. 19 North
Suite 455
Clearwater, FL 34624
Rush & West Associates
333 E. Poplar Street
Olathe, KS 66061
HAWAII
KANSAS
KENTUCKY
(EASTERN)
/DT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
Norm Case Associates
21010 Center Ridge Road
Rocky River, OH 44116
IDAHO
(NORTHERN)
KENTUCKY
(WESTERN)
Anderson Associates
270 S. Main Street
Suite 108
Bountiful, UT 84010
Arete Sales
P.O. Box 24796
IndianapOlis, IN 46224
IDAHO
(SOUTHERN)
Thorson Rocky Mountain
5505 South 900 East,
Ste.140
Salt Lake City, UT 84117
ILLINOIS
lOT
(Central Regional Office)
1375 E. Woodfield Road
Suite 380
Schaumburg,lL 60173
TEQ Sales
820 Davis Road
Suite 304
Elgin,lL 60123
Norm Case Associates
303 Uhl Road
Melbourne, KY 41059
LOUISIANA
/DT
(S. Cen. Regional Office)
14285 Midway Road
Suite100
Dallas, TX 75244
MASSACHUSETTS
/DT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg PkWay,
Suite 4002
Westboro, MA 01581
SJ New England
11 Waterman Street
Worcester, MA 01603
MICHIGAN
Bergin-Milan Group, Ltd.
33900 W. Eight Mile Rd.
Suite 181
Farmington Hills, MI
48335
MINNESOTA
lOT
(N. Cen. Regional Office)
1650 W. 82nd Street
Suite 1040
Minneapolis, MN 55431
OHMS Technology Inc.
5780 Lincoln Drive
Suite 400
Edina, MN 55436
MISSISSIPPI
lOT
555 Sparkman Drive
Suite 1238
Huntsville, AL 35816
MISSOURI
MAINE
Rush & West Associates
2170 Mason Road
st. Louis, MO 63131
lOT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg Pkwy,
Suite 4002
Westboro, MA 01581
Thorson Rocky Mountain
7108 "D" S. Alton Way
Suite A
Englewood, CO 80112
MONTANA
NEBRASKA
NEW MEXICO
OHIO
SOUTH CAROLINA
VIRGINIA
Rush & West Associates
333 E. Poplar Street
Ste.C-3
Olathe, KS 66061
Western High Tech Mktg.
9414 E. San Salvador
Suite 206
Scottsdale, AZ 85258
Norm Case Associates
21010 Center Ridge Road
Rocky River, OH 44116
Tingen Technical Sales
304A W. Millbrook Road
Raleigh, NC 27609
OKLAHOMA
SOUTH DAKOTA
NEVADA
(NORTHERN)
NEW YORK
lOT (SE Regional Office)
Horn Point Harbor
105 Eastern Avenue
Suite201
Annapolis, MO 21403
lOT
(S. Cen. Regional Office)
14285 Midway Road
Suite 100
Dallas, TX 75244
OHMS Technology Inc.
5780 Lincoln Drive
Suite 400
Edina, MN 55436
lOT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052
lOT
(NE Regional Office)
1160 Pittsford Victor Rd.
Bldg. E
Pittsford, NY 14534
NEVADA
(SOUTHERN)
Quality Components
3343 Harlem Road
Buffalo, NY 14225
Western High Tech Mktg.
9414 E. San Salvador,
Suite 206
Scottsdale, AZ 85258
Quality Components
116 E. Fayette Street
Manlius, NY 13104
NEW HAMPSHIRE
lOT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg Pkwy,
Suite 4002
Westboro, MA 01581
NEW JERSEY
lOT
(SE Regional Office)
One Greentree Centre,
Suite 202
Marlton, NJ 08053
SJ Mid-Atlantic, Inc.
1331-D Gaither Drive
Mt. Laurel, NJ 08054
NEW JERSEY
(NORTHERN)
SJ Associates
265 Sunrise HWay, #20
Rockville Centre, NY
11570
Quality Components
451 Brookwood Dr.
Webster, NY 14622
Quality Components
RD #2, Box 31 E
Glassfactory Road
Holland Patent, NY 13354
SJ Associates
265 Sunrise HWay, #20
Rockville Centre, NY
11570
OREGON
lOT
(NW RegionalOffice)
15455 NW Greenbriar
PkWay
Suite 210
Beaverton, OR 97006
Thorson Pacific, Inc.
9600 S.w. Oak Street
Suite 320
Portland, OR 97223
PENNSYLVANIA
(WESTERN)
Norm Case Associates
21010 Center Ridge Road
Rocky River, OH 44116
NORTH CAROLINA
PENNSYLVANIA
{EASTERN}
lOT
213 Townsend Ct.
Cary, NC 27511
S-J Mid-Atlantic
131-D Gaither Drive
Mt. Laurel, NJ 08054
Tingen Technical Sales
304A W. Millbrook Road
Raleigh, NC 27609
RHODE ISLAND
NORTH DAKOTA
OHMS Technology Inc.
5780 Lincoln Drive
Suite 400
Edina, MN 55436
lOT
,(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg PkWay,
Suite 4002
Westboro, MA 01581
TENNESSEE
lOT
555 Sparkman Drive
Suite 1200-0
Huntsville, AL 35816
WASHINGTON
Thorson Pacific, Inc.
12340 N.E. 8th St., #201
Bellevue, WA 98005
WEST VIRGINIA
Norm Case Associates
21010 Center Ridge Road
Rocky River, OH 44116
TEXAS
WISCONSIN
lOT
(S. Cen. Regional Office)
14285 Midway Road
Suite 100
Dallas, TX 75244
TEQ Sales
20720 W. Watertown Rd.
Suite 201
Waukesha, WI 53186
lOT
6034 W. Courtyard Dr.
Ste.305-60
Austin, TX 78730
WYOMING
Thorson Rocky Mountain
7108 "D" S. Alton Way
Suite A
Englewood, CO 80112
UTAH
Anderson Associates
270 S. Main Street
Suite 108
Bountiful, UT 84010
Thorson Rocky Mountain
1831 E. Fort Union Blvd.
Suite 103
Salt Lake City, UT 84121
VERMONT
lOT (NE Headquarters)
#2 Westboro Business Pk.
200 Friberg Pkwy,
Suite 4002
Westboro, MA 01581
AUTHORIZED DISTRIBUTORS (U.S. and Canada)
Future
Electronics
Hamilton Hallmark
Insight
Electronics
Port
Electronics
WYLE
Contact your local office.
INTERNATIONAL SALES REPRESENTATIVES
AFRICA
Prime Source (PTY) Ltd.
Oraange Grove, So. Africa
Tel.: 2711-444-7237
AUSTRALIA
GEC Electronics Division
Rydalmere,NSW,
Australia
Tel.: 612-638-1999/1888
GEC Electronics Division
Adelaide, SA, Australia
Tel.: 618-223-1222
GEC Electronics Division
Burwood, Australia
Tel.: 613-245-3230
GEC Electronics Division
Perth, WA, Australia
Tel.: 613-381-4040
GEC Electronics Division
Bowen Hills, Australia
Tel.: 619-252-5801
AUSTRIA
Elbatex GmbH
Vienna, Austria
Tel.: 43-186-32110
BELGIUM
ACALN.V.
Betea Components
Zaventem, Belgium
Tel.: 322-725-1080
CHINA
FINLAND
Lestina International, Ltd.
Beijing, China
Tel.: 86-1-849-9430
AVNET Nortec OY
Helsinki, Finland
Tel.: 358-0670-277
Lestina International, Ltd.
Guang Zhou
Tel.: 86-20-885-0613
FRANCE
Exatec AlS
Skovlunde, Denmark
Tel.: 45-44-927-000
lOT
(So. Europe Reg. Office)
15 Rue du Buisson aux
Fraises
91300 Massy, France
Tel.: 33-1-69-30-89-00
AVNET Nortec AlS
Herlev, Denmark
Tel.: 45-42-842-000
A2M
Brignolles, France
Tel.: 33-1-94-59-2293
DENMARK
A2M
Bron, France
Tel.: 33-1-72-37-0414
A2M
Buc, France
Tel.: 33-1-39-56-8181
A2M
Cesson-Sevigne, France
Tel.: 33-1-99-63-3232
A2M
Le Chesnay Cedex,
France
Tel.: 33-1-39-54-9113
A2M
Merignac, France
Tel.: 33-1-56-34-1097
COMPRESS
Rungis Cedex, France
Tel.: 331-4687-8020
Jermyn GmbH
Herrenberg, Germany
Tel.: 49-70321203-01
AVNETEMG
Cesson-Sevigne, France
Tel.: 33-99-83-9898
Jermyn GmbH
Pinneberg, Germany
Tel.: 49-40/5282041
AVNET EMG
Chantillon, France
Tel.: 33-149-652-2750
Jermyn GmbH
Nornberg, Germany
Tel.: 49-911425095
AVNET EMG
Rognes, France
Tel.: 33-42-50-1805
Jermyn GmbH
Hermsdorf, Germany
Tel.: 49-3660142374
AVNETEMG
Saint-Etienne, France
Tel.: 33-77-79-7970
Scantec GmbH
Plan egg, Gerrnany
Tel.: 49-898598021
AVNET EMG
SchwerwilJer, France
Tel.: 33-88-82-5514
Scantec GmbH
Kirchheim, Germany
Tel.: 49-702183094
GERMANY
Scantec GmbH
Ruckersdorf, Germany
Tel.: 49-91-157-9529
/DT
(Cen. Europe Reg. Office)
GottfriedVonCramm-Str.1
8056 Neufahrn, Germany
Tel.: 49-8165-5024
Topas Electronic GmbH
Hannover, Germany
Tel.: 49-51-113-1217
AVNET E2000
Munich, Germany
Tel.: 089-45110-01
Topas Electronic GmbH
Quickborn, Germany
Tel.: 49-4106-73097
AVNET E2000
Berlin, Germany
Tel.: 030-2110761/0764
GREECE
AVNET E2000
Dusseldorf, Germany
Tel.: 0211-92003-0
AVNET E2000
Frankfurt, Germany
Tel.: 069-973804-0
AVNET E2000
Hamburg, Germany
Tel.: 040-645570-0
AVNET E2000
Nurnberg, Germany
Tel.: 0911-995161-0
AVNET E2000
Gerlingen, Germany
Tel.: 07156-356-0
Jermyn GmbH
Limburg, Germany
Tel.: 49-6431/508-0
Jermyn GmbH
Berlin, Germany
Tel.: 49-30/2142056
Jermyn GmbH
Dusseldorf, Germany
Tel.: 49-211/25001-0
Jermyn GmbH
Heimstetten, Germany
49-89/909903-0
ISRAEL
Active Technologies
New Hyde Park, NY
Tel.: (516) 488-1226
Vectronics, Ltd.
Herzlia, Israel
Tel.: 972-9-55-60-70
ITALY
lOT (lOT Italia S.r.L.)
Central Direzionale
Colfeoni
Palazzo Astolabia
Via Cardano 2
20041 Agrate Brianza,
Milan,ltaly
Tel.: 39-39-68-99-987
AVNET De Mico
Cassina De Pecchi (MI)
Tel.: 02-95-34-36-00
AVNET De Mico
Torino,ltaly
Tel.: 011-31-81-481/500
AVNET De Mico
Rome,ltaly
Tel.: 06-33-32-283/284
AVNET DeMico
Bologna, Italy
Tel.: 051-55-56-14/00-64
Digital Electronics
Athens, Greece
Tel.: 30-1-533-5754
AVNET De Mico
Rubano (Padova), Italy
Tel.: 049-63-35-55/36-00
HONG KONG
AVNET De Mico
Campi Briseno, Italy
Tel.: 055-89-41-05/15
lOT ASIA LTD.
Unit 1003
China Hong Kong City
Tower 6, 33 Canton Road
Tsimshatsui, Hong Kong
Tel.: 852-736-0122
Lestina International Ltd.
Kowloon, Hong Kong
Tel.: 852-735-1736
INDIA
Techno Trends
San Jose, CA
Tel.: (408) 294-2833
Sritech Information
Technology, Inc
Javanagar, Bangalore
0812-643608
Las; Electronica
Bologna, Italy
Tel.: 3951-353815/374556
Lasi Electronica
Firenze, Italy
Tel.: 3955-582627
Lasi Electronica
Milano, Italy
Tel.: 39-266-1431
Lasi Electronica
Roma, Italy
Tel.: 396-5405301/
5409614
Lasi Electronica
Torino, Italy
Tel.: 3911-328588/359277
IRELAND
JAPAN
Bloomer Electronics
Craigavon, County
Armagh, N. Ireland
Tel: 762-3398181
IDTKK
(Japan Headquarters)
Sumitomo Fudosan
Sanbacho Bldg.
6-26 Sanbacho
Chiyoda-Ku
Tokyo 102, Japan
Tel.: 813-3221-9821
Dia Semicon Systems
Yokohama, Japan
Tel.: 045-476-7410
Kanematsu Semiconductor Corp.
Tokyo, Japan
Tel.: 813-3551-7791
Tachibana Tectron Co. Ltd
Tokyo, Japan
Tel.: 813-3793-1171
KOREA
Uniquest Korea
Seoul, Korea
Tel.: 822-562-8805
Uniquest Corporation
San Jose, CA
Tel.: 408-432-8805
NETHERLANDS
ACAL Auriema
Eindhoven, Netherlands
Tel.: 040-502-602
NEW ZEALAND
GEC Electronics Division
Auckland, New Zealand
Tel.: 649-526-0107
NORWAY
AVNET Nortec AlS
Hvalstad, Norway
Tel.: 47-66-84-62-10
PORTUGAL
Anatronic SA
Odivelas, Portugal
Tel.: 351-19376267/6287
SINGAPORE!
FAR EAST
Serial System PTE LTD
Singapore
Tel.: 65-280-0200
SPAIN
Anatronic, SA
Madrid, Spain
Tel.: 34-1-542-5566
Anatronic, SA
Barcelona, Spain
Tel.: 34-3-458-1906/7
SWEDEN
/DT (/DTAB)
Veddestavagen 13
S-175 62 Jarfalla, Sweden
Tel. :468-761-1130
AVNET Nortec AB
Vinthundsvagen, Sweden
Tel.: 46-8629-1400
AVNET Nortec AB
Solna, Sweden
Tel.: 46-8629-1400
AVNET Nortec OY
Helsinki, Sweden
Tel.: 358-0613-181
SWITZERLAND
Eljapex
Wettingen, Switzerland
Tel.: 011-41-56275-777
TAIWAN
Johnson Trading &
Engineering Co.
Taipei, Taiwan ROC
Tel.: 886-273-31211
Synnex Technology
International Corp.
Taipei, Taiwan ROC
Tel.: 886-2-506-3320
World Peace Industrial
Co., Ltd.
Nankang, Taipei,
Taiwan ROC
Tel: 886-2-788-5200
UNITED KINGDOM
lOT
(European Headquarters/
No. Europe Reg. Office)
Prime House
Barnett Wood Lane
Surrey, UK KT227DG
Tel.: 44-372-363-339/734
Avnet Access, Ltd.
Letchworth, Herfordshire,
UK
Tel.: 0462-480888
MicroCalJ, Ltd.
Thame Oxon, UK
Tel.: 44-844-261-939
M.M.D. Ltd
Reading, Berkshire
Tel.: 44-734-313232
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:08:11 09:45:54-08:00 Modify Date : 2017:08:11 10:53:10-07:00 Metadata Date : 2017:08:11 10:53:10-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:2b488e56-89c2-8847-85cb-32ff64e0ec44 Instance ID : uuid:a74a086b-e830-9948-ba5c-91f941928bb1 Page Layout : SinglePage Page Mode : UseNone Page Count : 1276EXIF Metadata provided by EXIF.tools