1995_Integrated_Circuit_Systems_Data_Book 1995 Integrated Circuit Systems Data Book

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les Product Data Book

Ies reserves the right to make changes in the device data identified in this publication without further notice. IeS advises its
customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is
current and accurate.

Ies does not assume any liability arising out of or associated with the application or use of any product or integrated circuit
or component described herein. Ies does not convey any license under its patent rights or the patent rights of others described
herein. In the absence of a written or prior stated agreement to the contrary, the terma and conditions stated on the back of
the IeS order acknowledgment obtain.
ICS makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.

IeS products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any nuclear facility application, or for any other application
in which the failure of the IeS product(s) could create a situation where personal injury or death may occur. IeS will not
knowingly sell its products for use in such applications, and the buyer shall indemnify and hold harmless IeS and its officers,
employees, subsidiaries, affiliates, representatives and distributors against all claims, costs, damages, expenses, tort and
attorney fees arising out of directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that IeS was negligent regarding the design or manufacture of the part.

Copyright Ii:) 1995 Integrated Circuit Systems, Inc.

Using the ICS Data Book
The ICS Spring 1995 Data Book includes all of ICS's standard products in each of the follOllVing product
lines: frequency timing generators, GENDACs, ™ data and telecommunications, multimedia audio and
video and QuickSaver@ battery charge controllers. The manual is organized by product lines, which are
further subdivided into product categories. Each product section includes an introduction, a product
selection guide with applications information, data classification definitions and the pertinent data sheets
for the ICS standard products within those categories.
Application notes for ICS's products are incorporated within the appropriate sections. General applications
notes stand alone at the end of the chapter, while the more product-specific are located at the end of their
respective data sheets. You can fmd the general application notes easily in the Alpha Numeric Index located
on page A-3.
The individual data sheets include block diagrams with a package designation, pin descriptions, electrical
characteristics, absolute maximum ratings and ordering information. Package dimensions are located in
a separate section at the back of the book (Section K). The block diagram data notes the page on which
the actual package drawing is located.
Other sections in the 1995 edition of the Data Book include a Table of Contents, Alpha Numeric Index,
Ordering Information and Master Selection Guide (Section A), a description of our ASIC capabilities and
Quality Assurance procedures (Section J) and a complete list of ICS's sales reps and distributors
(Section L).
Product samples or demo boards can be obtained by contacting any of the sales reps or distributors. For
further information, contact ICS Customer Service.

Integrated Circuit Systems, Inc.
2435 Boulevard of the Generals
P.G. Box 968 Valley Forge PA 19482-0968
(610) 630-5300 • fax (610) 630-5399

Any errors in content can be directed to MarCom at the above address.

GENDAC is 8 trademark of Integrated Circuit Systems, Inc.
QUickSaver i•• registered trademark of Integrated CirCUIt Systems, Inc.

About ICS
Integrated Circuit Systems, Inc. designs, develops and markets standard and application specific integrated
circuits utilizing mixed analog/digital technology. Founded in 1976 to provide custom IC designs and
product sourcing services to OEMs, ICS created its own sophisticated design tools, analog and digital cell
libraries and quality assurance testing methods. In 1988, these unique tools and mixed signal design
capabilities enabled ICS to create the first commercially viable video timing generator using advanced
frequency synthesis technology. The ICS1394 pioneered the transition from multiple crystal oscillators to
a single IC and emerged as the industry standard for producing the high frequency video dot timing
function in ffiM-compatible personal computers.
ICS has extended its knowledge of frequency timing into new products for PC multimedia sound and
video. These include products that synchronize PC video images with live or recorded television video,
and products that create real, digitized sound. To expand on the capabilities of its PC sound/video design
expertise, ICS formed the Multimedia Components Division in July, 1993 and merged with Thrtle Beach
Systems, Inc., a provider of PC-based hardware and software products for professional-quality sound
generation and editing in multimedia applications.
Additionally ICS has leveraged its core technology into the communications arena, designing a Bellcorecompliant clock generation and recovery circuit and parlaying its technology to create a mmily of higbly
integrated, physical layer transceivers for Fast EthemetlFDDI, ATM and SONET data rates.
ICS is meeting the increasing demand for controlled, rapid NiCd or NiMH battery recharging for laptop
and notebook computers with a mmily of power management integrated circuits. Using inflection point
termination technology to mst charge batteries prolongs battery life and eliminates the memory effect. In
fact, NASA has judged ICS's battery charging IC the safest of the new rapid-charge products.

Our goal at ICS is to produce and deliver products of
exceptional quality and reliability. To achieve that goal, we
control every phase of manumcturing and quality assurance at all locations. We dedicate our efforts to meeting
your technical expectations, your delivery deadlines and
your competitive pricing needs. We strive to achieve a total
quality process that provides customers with products and
services that meet or exceed specification and performance
requirements, quality expectations and support needs before and after delivery.
Our unique partnerships with international experts in
wafer fabrication and assembly provide our customers
with the highest quality and performance in each integrated
circuit chip. We routinely produce both application specific integrated circuits (ASICs) and customized versions
of our standard masks.
We are confident that ICS can provide you with the
optimum IC solutions, outstanding customer service and
dedication to quality to suit your needs.

Dr. David Sear, President and CEO

Integrated Circuit Systems . .• Where the Digital World Meets the ReallWJrld.

_____ Table of Contents, Alpha Numeric Index,
Ordering Information, Master Selection Guide

SECTION

A

_ _ _ _ _ _ _ _ _ _ _ Video Timing Generators

SECTION

B

______ Motherboard Video Timing Generators

SECTION

C

_______ Special Purpose Timing Generators

SECTION

D

____ High-Performance Video Timing Generators

SECTION

E

_ _ _ _ _ _ _ _ LANIWAN Communications ICs

SECTION

F

_ _ _ _ _ _ _ _ Multimedia Video and Audio ICs

SECTION

G

_ _ _ _ GENDACTM - Integrated Clock-LUT-DACs
for Advanced VGA Controllers

SECTION

H

___ NiCd and NiMH Battery Charge Controller ICs

SECTION

I

_ _ _ _ ASIC Capabilities and Quality Assurance

SECTION

J

_ _ _ _ _ _ _ _ _ Standard Package Information

SECTION

_ _ _ _ _ _ _ _ _ Sales Reps and Distributors

SECTION

L

Contents
Page
Alpha Numeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-3

Ordering Infonnation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-5

Master Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A-7

Video Timing Generator Products .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

B-1
B-3
B-ll
B-21
B-29
B-37
B-47
B-61
B-71
B-S1
B-S9
B-103

ICS1494IFrequency Pattern . . . . . . . . . . . . . . . . . . . . . . . .
ICS249412494A/Frequency Pattern . . . . . . . . . . . . . . . . . . .
ICS24951Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . . .
ICS2496/Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . . .
ICS25951Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . . .
ICSS2C404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9OC61A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9OC64A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS90C65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9161A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Video Timing Generator Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Motherboard Timing Generator Products . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS2407/ICS2409I1CS2419/ICS2439 . . . . . . . . . . . . . . . . . .
ICS2492/Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . . .
ICS2694/Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . . .
AV9107C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS910S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9120-0S/-09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9133X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9134-06/-07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV9154A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV9154A-06/-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV9155A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS915S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9159-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9160-03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS917S-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN05 Pentium Application Note . . . . . . . . . . . . . . . .

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Special Purpose ICs (Disk Drive, Low Skew (PentiumTII » .............. .
ICSl694A1Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . .
AV9110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9111-01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV9170 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV9170 Application Note . . . . . . . . . . . . . . . . . . . . .
AV9172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV9173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS9177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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High-Perfonnance Video Timing Generator Products ................. .
ICS1522 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS1522 Application Note . . . . . . . . . . . . . . . . . . . . .
ICS1561A/Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . .
ICS1562A with Application Information . . . . . . . . . . . . . . . .
ICS1567/Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . . .
ICSI572 with Application Information . . . . . . . . . . . . . . . . .
Pentium

IS 8

trademark of Intel Corporation.

A-I

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C-l
C-3
C-l1
C-17
C-23
C-29
C-35
C-41
C-49
C-55
C-61
C-71
C-77
C-89
C-95
C-99
C-I03
C-109
D-l
D-3
D-7
D-17
D-19
D-21
D-29
D-37
D-45
D-51
D-57
D-63
E-l
E-3
E-17
E-23
E-31
E-Sl
E-61

I

Contents

(continued)
Page
ICS1574... .. ..•... . ... .. .. .• .• . . .. . ... .. .. . . •
ICS1577 with Application Information. . . . . . . . . . . . . . . . . •
ICS25721Frequency Pattern . . . . . . . . . . . . . . . . . . . . . . . . .

Communications Products. . . . . . . . . . . . . . . . . . .
ICSl660. . . . . . . . . . • . . . . . . . . .
ICSl660 Demonstration Board.
ICS1884... .... ..... ..... ...
ICS1885. . . . . . . . . . . . . . . . . . . .
ICS1886. . . . . . . . . . . . . . . . . . . .
ICS1887. . . . . . . . . . . . . . . . . . . .
ICS1888. . . . . . . . . . . . . . . . . . . .
ICS1889. . . . . . . . . . . . . . . . . . . .
ICS1890. . . . . . . . . . . . . . . . . . . .
ICS1891. . . . . . . . . . . . . . . . . . . .

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F-l
F-3
F-13
F-15
F-27
F-33
F-39
F-45
F-47
F-49
F-51

Multimedia Products ........... . . . . . . . .
GSP500 ... . . .. .... . .... .
AN501 Application Note.
AN502 Application Note .
AN503 Application Note .
OSP600 . . . . . . . . . . . . . . . . .
AN602 Application Note. .
AN603 Application Note. .
ICS2002. . . . . . . . . . . . . . . . .
ICS2008A. . . . . . . . . . . . . . . .
ICS2101. . . . . . . . . . . . . . . . .
ICS2102. . . . . . . . . . . . . . . . .
ICS2115. . . . . . . . . . . . . . . . .
ICS2115 Application Note.
ICS2116. . . . . . . . . . . . . . . . .
ICS2122. . . . . . . . . . . . . . . . .
ICS2124-001l-002 . . . . . . . . . .
ICS2125. . . . . . . . . . . . . . . . .

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G-l
G-3
0-17
0-29
0-37
0-49
0-63
0-71
0-85
0-105
0-123
G-131
0-141
0-159
0-171
0-185
0-189
0-193

GENDAC Products. .. . .
ICS5300.
ICS5301.
ICS5340.
ICS5341.
ICS5342.

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H-l
H-3
H-33
H-63
H-97
H-I01

Power Management Products. . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS1700A. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS1700A Evaluation Board Application Note.
ICS1702. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS1702 Evaluation Board Application Note. .
ICS1712. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICS1722. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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1-1
1-3
1-21
1-27
I-51
I-57
1-79

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E-79
E-91
E-99

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ICS ASIC Capabilities .......................................

J-l

Quality and Reliability Infonnation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J-7

Standard Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

K-1

ICS Sales Offices and Sales Representatives. . . . . . . . . . . . . . . . . . . . . . . . .

L-1

A-2

Alpha Numeric Index of les Products
AN01
AN02
AN03
AN04
AN05
AN501

Designing with Video Dot Clocks ................. .
Understanding ICS Jitter Specifications .......... .
Clock Output Frequency Accuracy ............... .
Clock Reference Guidelines ........................ .
Clocking Intel Pentium-Based Systems ........... .

B-I05
B-l11
B-l13
B-121
C-109

~~7~~ln~~c'j~~ ~.~~.~~........................ .

G-17

AN502

Theory for GSP500 Operating VGA Display
at 2XNTSC Frequency .............................. .
Using Flicker Reduction Circuit with GSP500 .. .

G-29
G-37

AN503

~t~p1frF~!i.:oc~:.~~~~.:'~~.?~~:'l.~:

AN602
.... .
Using Flicker Reduction Circuit with GSP600 .. .
AN603
CPU Frequency Generator ......................... .
AV9107C
AV9110
Serially Programmable Frequency Generator ... .
AV9154A
Low-Cost 16-Pin Frequency Generator .......... .
AV9154A-06/ OFTi Notebook Frequency Generator
AV9154A-60 .......................................................... .
Low-Cost 20-Pin Frequency Generator .......... .
AV9155A
AV9170
Clock Synchronizer and Multiplier ............... .
AV9170
Applications Note .................................... .
AV9172
Low Skew Output Buffer ........................... .
Video Genlock PLL ................................. .
AV9173
VGAlNTSC Video Genlock Processor
GSP500
with Overlay .......................................... .
VGAlPAL Video Genlock Processor
GSP600
with Overlay .......................................... .
lCS82C404 Dual Programmable Graphics
Frequency Generator ................................ .
ICS90C61A Dual Video/Memory Clock Generator ........... .
ICS90C64A Dual Video/Memory Clock Generator ........... .
Dual Voltage Video/Memory Clock Generator .. .
lCS90C65
Enhanced Video Dot Clock Generator ........... .
ICS1494
Mini-Motherboard Clock Generator .............. .
ICS1694A
lCS1522
Line-Lock Clock Regenerator ..................... .
lCS1522
Applications Note .................................... .
ICS1561A
Differential Output PLL Generator ............... .
User-Programmable Differential Output
ICS1562A
PLL Generator ....................................... .
lCS1567
Differential Output Video Dot Clock Generator ... .
User-Programmable Differential Output
ICS1572
Clock Generator ..................................... .
ICS1574
User-Programmable Laser Engine Pixel
Clock Generator ..................................... .
High-Performance DEC AJpha™ CPU Clock .. .
ICS1577
Incoming Call Line Identification (I CLIO)
ICSl660
Receiver with Ring Detection ...................... .
Demonstration Board ................................ .
ICSI660
QuickSave~ Charge Controller for
ICS1700A
NiCdlNiMH Batteries ............................... .
Evaluation Board ..................................... .
ICSI700A
ICS1702
QuickSave~ Charge Controller for
NiCdlNiMH Batteries ............................... .
Evaluation Board ..................................... .
lCS1702
ICSI712
QuickSavet» Charge Controller for
NiCdlNiMH Batteries ............................... .
ICSI722
QuickSave~ Charge Controller for
NiCdlNiMH Batteries ............................... .
ICS1884
Sonet!ATM TeleclockTl" Recovery/
Generator Unit ....................................... .
lCS1885
............... .

~;r~~~~!~ill'~~. ~~~~.~~.i~.~~.~~.s

G-63
G-71
C-23
0-7
C-61
C-71
C-77
0-21
0-29
0-37
0-45
G-3
G-49
B-47
B-61
B-71
B-81
B-3
0-3
E-3
E-17
E-23
E-31
E-51
E-61
E-79
E-91
F-3
F-13
1-3
1-21
1-27
I-51
I-57
1-79
F-15
F-27

ICSI886

~if~~~i!!~~~~ ~~~~.~.i~~~~.~ .............. .

ICS1887
ICS1888

POD! Fast Ethernet PHYceiver ................... .
High-Performance Twisted Pair
Communication PHYceiver ........................ .
ICS1889
100Base-FX Integrated PHYceiver ............... .
10Base-T/100Base-TX Integrated PHYceiver .. .
ICS1890
100Base-TX Integrated PHYceiver
ICS1891
for Repeaters ......................................... .
Wavedec™ Digital Audio Codec .................. .
ICS2002
SMPTE Time Code Receiver/Generator ......... .
ICS2008A
ICS2101
Digitally Controlled Audio Mixer ................. .
ICS2102
Sound Blaster™ Compatible Mixer ............... .
ICS2115
WaveFront Synthesizer ............................. .
ICS2115
Applications Note .................................... .
ICS2116
WaveFront Interface ................................ .
ICS2122
WaveFront Sounds
(16M Bit CMOS Mask ROM) ..................... .
ICS2124-001l WaveFront Sounds
ICS2124-002 (16M Bit CMOS Mask ROM) ..................... .
ICS2125
WaveFront Sounds
(4M bit CMOS Mask ROM) ....................... .
Dual PLL Motherboard
ICS2407/
Frequency Generator
ICS2409/
ICS2419/
ICS2439
......................................................... .
ICS2492
CPU Clock Generator ............................... .
ICS2494/94A Dual Video/Memory Clock Generator ........... .
ICS2495
Dual Video/Memory Clock Generator ........... .
ICS2496
Dual Voltage Video/Memory Clock Generator .. .
ICS2572
User-Programmable Dual High-Performance
Clock Generator ..................................... .
User-Programmable Dual High-Performance
ICS2595
Clock Generator ..................................... .
Motherboard Clock Generator ..................... .
ICS2694
8-Bit Integrated Clock LUT DAC ................ .
ICS5300
ICS5301
8-Bit Integrated Clock LUT DAC ................ .
ICS5340
16-Bit Integrated Clock LUT DAC ............... .
ICS5341
16-Bit Integrated Clock LUT DAC ............... .
ICS5342
16-Bit Integrated Clock, Palette RAM
andDACs ............................................. .
ICS9108
CPU Frequency Generator ......................... .
ICS9111-01 250 MHz Clock Generator for
RAMBUSTM Systems ............................... .
I CS9120-08/
............. .
ICS9120-09
High Resolution Frequency Generator ........... .
ICS9123
32 kHz Motherboard Frequency Generator ..... .
ICS9131
32 kHz Motherboard Frequency Generator ..... .
ICS9133X
ICS9134-06/ 32 kHz Motherboard Frequency Generator
ICS9134-07
Integrated Buffer and Motherboard
ICS9158
Frequency Generator ................................ .
ICS9159-02

~~~S~~t~:~~~~~ .f~~. ~~~~~~~

ICS9160-03

}~~e~:~~!T'W~~ .~~.~ .::~~~~.~? .~~~.~~:~.~ ..... .
r~;p~~~ip~~~~~:~~ .~~.~ .~~:~~~:~ .~~~~~.~ ..... .

F-33
F-39
F-45
F-47
F-49
F-51
G-85
G-I05
G-l23
G-131
G-141
G-159
G-l71
G-185
G-189
G-193

C-3
C-11
B-11
B-21
B-29
E-99
B-37
C-17
H-3
H-33
H-63
H-97
H-101
C-29
0-17
C-35
0-19
C-41
C-49
C-55
C-89
C-95

C-99
Dual Programmable Graphics
B-89
Frequency Generator ................................ .
Low Skew Output Buffer ........................... .
0-51
ICS9175
Low Skew Output Buffer. .......................... .
0-57
ICS9176
High Frequency Systems Clock Generator ...... .
ICS9177
0-63
ICS9178-02 240 MHz Clock Generator and Integrated Buffer
for PowerPC .......................................... . C-103
ICS9161A

PHYcelVer & QUlckSaver are registered trademark. of Integrated Circuit Systems, Inc.
Alpha IS 8 trademark of Digital EqUipment Corporation.
Teleclock IS a trademark of Integrated CIrcuIt Systems, Inc.

Wavedec and WaveFront are trademarks of Integrated CIrCUIt Systems, Inc.
Sound Blaster i8 • trademark of CreatIve TechnologIes, Inc.; RAM BUS 18 a trademark of
Rambua. Inc.; PentIum 18 a trademark of Intel CorporatIon; PowerPC 10 a trademark of
Motorola CorporatIon.

A-3

11

A4

ICS Ordering Information

Device Identification
All res standard circuits are marked as shown in the following example:

Ordering Information
ICS
-

xxxx-ppp
M' x#w 2
- - --

L

Lead Count & Package Width
Lead Count = 1, 2 or 3 digits
W=.3" SOIC or .6" DIP
None = Standard Width

Package Type
N = DIP ~astic)
M=SOIC

V = PLCC
F = SSOP
Y=OFP;TOFP;MOFP

" - - - - - - - - - Pattem Number
(2 or 3 digit number for parts with
ROM code patterns)

' - - - - - - - - - - - Device Type
(Consists of 3 or 4 digits)
(Example: ICS 1702)

" - - - - - - - - - - - - - - Prefix
leS, AV = Standard Device;
GSP=Genlock Device

Package Type
Specific dimensions for each package can be found in the Standard Package
Dimensions (section K) section of this catalog.
Each data sheet references the respective package type and page number where
it can be located within section K.
1 In some cases the Package Type may appear before the Pattern Number.
2 Note: TillS SECTION IS ONLY INCLUDED ON OLDER AV OR ICS PARI'S.

A-5

A·6

les Product Selection Guide

V"d
I eo

r Imlng Generator Prod ucts

PRODUCT
APPUCATION

ICS
DEVICE TYPE

DESCRIPTION

MAX
FREQUENCY

CWCK
OUTPUTS

PACKAGE
TYPES

ICSI494

Buffered XTAL Out, Lock: Deleet Output.

135 MHz

I ITL

20-Pin
DIP, SOIC

B-3

ICS24941

Buffered XTAL Out, Lock Deleet Output.

135 MHz

2ITL

20-Pin
DIP, SOIC

B-1I

ICS2495

SmaIl Footprint, Narrow Body
SOIC Package.

135 MHz

2ITL

16-Pin
DIP, SOIC

B-21

ICS2496

Low Voltage, 3/5 Volt Operation for
Laptop/Notebook: Applications.
Power-down Mode.

85/135 MHz

2ITL

16-Pin
DIP, SOIC

B-29

ICS2595

Programmable Dual
ICS2494 Pin compatible.

135 MHz

2ITL

20-Pin
DIP, SOIC

B-37

ICS82C404

Dual Programmable Graphics Clock:
Generator. ICD82C404 compatible.

120 MHz

2ITL

16-Pin
DIP, SOIC

B-47

ICS9161A

Dual Programmable Graphics
Clock: Generator. ICD2061 compatible.

135 MHz

3ITL

16-Pin
DIP, SOIC

B-89

ICS9OC6IA

Drop-in upgrade for the WD9OC61.
Integral Loop Filters.

80 MHz

2ITL

20-Pin
DIP, SOIC
PLCC

B-61

ICS9OC64A

WD9OC31 VGA Controller compatible.
Enhanced Version. Integral Loop Filter.
(Replaces ICS9OC63, ICS9OC64.)

80 MHz

2ITL

20-Pin
DIP, SOIC
PLCC

B-71

ICS90C65

Low Voltage, 3/5 Volt. Power-down Mode.
WD9OC26 VGA Controller compatible.

80 MHz

2ITL

20-Pin
DIP, SOIC
PLCC

B-81

ICS2494A

PC Graphics Clock
Generators

Western Digital
Compab"ble
Graphics
Clock Generators

PAGE

Motherboard Timing Generator Products
PRODUCT
APPUCATION

ICS
DEVICE TYPE

DESCRIPTION

NUMBER
OF
OUTPUTS

NUMBER
OF
PLL's

PA£XA£lE
TYPES

IMI407, IMI409 aod
IMI439 compatible.

6
9
10
9

2
2
2
2

ICS2492

Buffered XTAL Out.
Tristate PLL Outputs.

3

2

2O-Pin
DIP, SOIC

C-lI

ICS2494-244
ICS2494A-317

Buffered XTAL Out.
Note: See Video Dot Clock Section for
Data.

3

2

20-Pin
DIP, SOIC

B-ll

ICS2694

9 Fixed, CPU-CPUl2 Selectable
Provides CPU, Co-Processor, Hard
and Floppy Disk:, Kbd, Ser. Port,
Bus CLK Function.

11

2

24-Pin
DIP, SOIC

C-17

AV9107C

CPU Clock: Generator.

2

I

8-Pin DIP, SOIC
14-Pin DIP, SOIC

C-23

ICS9108

3 Volt CPU Clock: Generator.

2

I

8 or 14-Pin
DIP, SOIC

C-29

Audio

ICS9120-081

I

8-Pin
SOIC

C-35

ICS9120-09

3 Volt Multimedia Audio Synthesizer
Clock: Generator.

4

Synthesis

Motherboard

A-7

18-Pin DIP,
24-Pin DIP,
24-Pin DIP,
24-Pin DIP,

SOIC
SSOP
SSOP
SSOP

PAGE

ICS2407
ICS2409
ICS2419
ICS2439

C-3

M oth erboardT"ImlnQ Generator Pro d ucts
PRODUCT
APPUCATION

Notebook

Sub-Notebook

ICS
DBVICETYPE

DESCRIPI'ION

NUMBER
OF
OUTPUTS

NUMBER
OF
PLL's

ICS9131

32 kHz Input Generates CPU Clocb.

3

2

16-Pin
SOIC, PDIP

C-41

ICS9133X

32 kHz Input Generates CPU Clock
and
System Clock and Two Fixed Clocb.

6

3

2O-Pin
SOIC,PDIP

C-49

ICS9134-06
ICS9134-07

32 kHz Motherboard
Frequenoy Generator.
Generated CPU, Reference and
One Fixed Clock.

6

3

16-Pin
SOIC

C-55

AV9154A

Low Cost 16-Pin Clock Generator.
Generates CPU Clock,
Keyboard Clock,
System Clock and 110 Clock.

7

2

16-Pin
DIP, SOIC

C-61

AV9154A-06
AV9154A-060

Clock Generator Designed for
OPTi Chip set.

5

2

16-Pin PDIP
16-Pin Narrow
SOIC

C-7l

AV9155A

Motherboard Clock Generator.
Produces CPU Clock,
Keyboard Clock,
System Clock and 110 Clock.

8

2

2O-Pin
DIP, SOIC

C-77

Pentium and G.-- PC
Systems

om

Notebook
Motherboard
DesktoP/Notebook
Pentium Systems
PowerPC
Systems

(continued)
PACKA£lIl
TYPES

PAGE

ICS9158

Clock Generator wiIh Ittegrated Buffers.

11

2

24-PinSOIC

C-89

ICS9159-02

Clock Generator and Integrated Bnffers.

14

2

28-PinSOIC

C-95

ICS916~3

Clock Generator for PowerPC
603 Systems.

IS

2

32-PinSOIC

C-99

ICS9178-02

Clock Generator for PowerPC
6011601 + Systems.

14

1

44-PinPQFP

C-I03

Special Purpose les (Disk Drive, Low Skew (Pentium)
ICS
DEVICE TYPE

DESCRIPI'ION

NUMBER
OF
OurPurs

NUMBER

PRODUCT
APPLICATION

OF
PLL's

PACKA£lIl
TYPES

Motherlloanl

ICS1694A

Single Crystal Generates Three Low-litter Clocks.

3

1

8-Pin
DIP, SOIC

0-3

Disk Drive or

AV9110

User-Programmable "On-the-Fly"; Low-litter makes it
ideal for Disk Drive or Video Applications.

1

I

14-Pin
DIP, SOIC

D-7

RAMBUS

ICS9111-01

High Frequency Clock for RAMBUS Systems.

8-PinSOIC

0-17

Modem
Ethernet
ADl848

ICS9123

High Resolution Clock Generator; One Channel has
Accuracy to within 50 PPM.

6

3

16- or 2O-Pin
DIP, SOIC

0-19

TeIeccJm

AV9170

Clock Synohronizer and Multiplier.

2

I

8-Pin
DIP, SOIC

0-21

Radio
Video
Motherlloanl
Pentium

AV9172

Low Skew Output Buffer. Low Skew and litter make it
ideal for Pentium Applications.

6

1

16-Pin
DIP,SOIC

0-37

Video GEnlock

AV9173

Lost Cost Video Genlock PLL.

2

I

8-Pin
DIP,SOIC

0-45

Pentium PCs or
Worl= Vss and <=Voo.

DC Characteristics (0 DC to 70 DC)
BOL
Vdd
Vii
Vih
lIh
Vol
Voh
lctda
Idda
Iddd
Iddd
Rup *
Cin
COUI

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
Output High Voltage
Analog Supply Current
Analog Supply Current
Digital Supply Current
Digital Supply Current
Internal Pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance

MIN
4.0
Vss
2.0

MAX
5.5
0.8
Vdd

UNITS
V
V
V

-

10

uA

0.4

2.4

-

-

5
7
12
25
200
8
12

V
V
rnA
rnA
rnA
rnA
KOhm
pF
pF

50
-

-

* The following inputs have pull-ups: FSO-4, STROBE, EXTFREQ, VERTBLANK.

B-6

CONDITIONS
Vdd = 5V
Vdd = 5V
Vin= Vee
Iol =4.0mA
Ioh =4.0mA
V dd = 5.0V, FOUT =
Vdd = 5.0V, FOUT =
Vdd = 5.0V, FOUT =
Vdd = 5.0V, FOUT =
Vdd = 5V, V m = OV
Fe = I MHz
Fe= I MHz

25 MHz
110 MHz
25 MHz
110 MHz

ICS1494
AC Timing Characteristics
The following notes apply to all parameters presented in this section:
1.
2.
3.
4.
5.
6.
7.

Xtal Frequency = 14.31818 MHz
All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC.
Output pin loading = 15pF
Duty cycle is measured at 1.4V.
Supply Voltage Range =4.75 to 5.25 Volts
Temperature Range = 0 °C to 70°C

SYMBOL

PARAMETER

Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr
Tf

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency
Duty Cycle

-

-

MIN
STROBE TIMING
20
10
10
FOUTTIMING
-

FSO- FS]

!
I

I

-

-

%
MHz
ns

40%

60%

,110 MHz or less

!

~

/
:+<
t-

Tsu

-+-

Figure 3

B·7

NOTES

3
3
0.5
135
15

-

Tpw

STROBE

MAX

Thd

:+<
-!

II

ICS1494
Ordering Information
ICS1494AN-XXX

or ICS1494AM-XXX

Example:

ICS XXXX M -XXX

11 """""

N,m""

Package Type

(2", 3

~gl"'n_ fu"",,,,

N=DIP (Elastic)
M=SOIC

Device Type (consists of 3 or 4 digit nnmbers)

L------------------- Prefix

ICS, AV=Standard Device; GSP=Genlock DeVIce

B-8

with ROM"'" ...""""

ICS1494A
ICS1494 Pattern Request Form
ICS produces a selection of standard pattern ICS1494's pre-programmed for compatibility with many popular VGA
chip sets. Custom patterns are also available, although a significant volume commitment and/or one-time mask charge will
apply. Contact ICS sales for details.

ICS Part
Number
Compatible
VGA
ChIDsets
Video Clock
Address
(HEX)
0
I
2
3
4
5
6
7
8
9
A
B
C
D
E
F
\0
11
12
13
14
15
16
17
18
19
IA
1B
IC
1D

IE
IF

ICSI494523
Tseng Labs
ET4000

ICS 1494·
527
CIrrus LOgIC
GD5320
GD6410

ICS1494530
NCR
77C22E

ICS1494535
AT!

ICS 1494539
Tseng Labs
ET4000
(2X Frea.)

ICS1494540
RadIUs

ICS1494
543
Supermac

ICS1494
544
Setko-Epson

Frequency
(MHz)
25.175
28.322
32.514
36.000
40.000
44.900
65.000
84.000
25.175
28.322
40.000
44.900
32.514
28.322
36.000
65.000
25.175
28.322
32.514
36.000
40.000
44.900
56.000
65.000
25.175
28.322
32.514
40.000
44.900
60.000
80.000
84.000

Frequency
(MHz)
XTAL
16.257
EXTFREQ
32.514
25.175
28.322
24.000
40.000
XTAL
16.257
EXTFREQ
36.000
25.175
28.332
24.000
40.000
XTAL
65.028
EXTFREO
36.000
25.175
28.332
24.000
40.000
44.900
50.344
16.257
32.514
56.644
20.000
50.000
80.000

Frequency
(MHz)
XTAL
16.257
EXTFREQ
32.514
25.175
28322
24000
40.000
25.175
28.322
36.000
65.000
44.900
50.000
56.000
75.000
25.175
28.322
40.000
65.000
44.900
50.000
56.000
75.000
25.175
28.322
EXTFRBQ
EXTFREQ
60.000
80.000
EXTFREO
EXTFREO

Frequency
(MHz)
42950
48.770
92400
36.000
50350
56.644
EXT
44.900
30.240
32.000
110.000
80.000
39.910
44.900
75.000
65.000
42.950
48.770
92.400
36.000
50.350
56.644
EXT
44.900
30.240
32.000
1\0.000
80.000
39.910
44.900
75.000
65.000

Frequency
(MHz)
25.175
28332
32.514
36.000
40.000
44900
50.350
65.000
33400
37.575
31.480
41.750
55.110
74160
77.250
80.000
50.350
56.664
65.028
72.000
80.000
89.800
75.000
108.000
70.000
75.000
85.000
90.000
95.000
110.000
115.000
120.000

Frequency
(MHz)
57.283
12.273
14.500
15667
112000
126.000
30240
91.200
120.000
48.000
50.675
55.300
64.000
68.750
88.500
51.270
100.000
95.200
55.000
60.000
63.000
99.522
130.000
80.000
25.175
28322
48.000
76.800
38400
43.200
61.440
EXT

Frequency
(MHz)
14318
EXT
12.273
15667
17734
25175
30240
13.500
14.750
14.187
55.000
57283
64.000
80.000
100000
130.480
28.322
36.000
40.000
40.900
44.900
50.000
62.000
65.000
75.000
89.211
99.522
103140
107.350
111.518
113.484
122320

Frequency
(MHz)
28636
42105
47.846
78431
XTAL
21053
50.350
25175
EXT
3.000
6.000
8.000
10.000
12.000
16.000
20000
25.000
30000
32.000
33.000
40000
44.000
46.000
50000
60.000
66.000
70.000
80.000
90.000
100000
110.000
120.000

I

Standard frequency patterns are available and are included as an example.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
If the internal frequency to which the ICS1494 remains locked when EXTFREQ is selected is critical, it should be specified.
Order info: ICSI494M-XXX or ICSI494N-XXX (M= SOIC pkg., N= DIP pkg., XXX = Pattern number)

B·9

El-.

B·l0

II

ICS2494
ICS2494A

Integrated
Circuit
Systems, Inc.

Dual Video/Memory Clock Generator
Features

New Features

•

•
•
•

•
•
•
•
•
•
•

World standard ICS2494A has been reconfigured
to allow 8 memory frequencies.
Mask-programmable frequencies
Pre-programmed versions for Industry Standard
VGAchips
Glitch-free frequency transitions
Provision for external frequency input
Internal clock remains locked when the external
frequency input is selected
Low power CMOS device technology
Small footprint - 20-pin DIP or sorc

•
•
•

•

Buffered XTAL Out
Integral loop filter components
Fast acquisition of selected frequencies, strobed or nonstrobed
Guaranteed performance up to 135 MHz
Excellent power supply rejection
Advanced PLL for low phase-jitter
Frequency change detection circuitry which enhances
new frequency acquisition and eliminates problems
caused by programs that rewrite frequency information.
Improved pinout - easier board layout.

Applications
•

VGA-Super VGA-XGA video adapters

•
•
•

Workstations
8514A-TMS3401O-TMS34020
Motherboard

Pin Configuration

XTAL1

Description
The Dot Clock Generator is an integrated circuit dual phaselocked loop frequency synthesizer capable of generating sixteen video dot clock frequencies and eight memory clock
frequencies for use with high performance video display systems. Utilizing CMOS technology to implement all linear,
digital and memory functions, the ICS2494/94A provides a
low-power, small-footprint, low-cost solution to the generation
of video dot clocks. Outputs are compatible with XGA, VGA,
EGA, MCGA, CGA, MDA, as well as the higher frequencies
needed for advanced applications in desktop publishing and
workstation graphics. Provision is made via a single-level
custom mask to implement customer-specific frequency sets.
Phase-locked loop circuitry permits rapid glitch-free transitions between clock frequencies.

20

DVDD

19

VCLK

XTAL

2

EXTFREQ

3

18

XTALOUT

FSO

4

17

VSS

FS1

5

16

VSS

STROBE

6

15

AVDD

FS2

7

14

VSS

FS3

8

13

DVDD

MSO

9

12

MCLK

MSO

10

11

MS1

20-Pin DIP or sOle
K-4, K-7
Notes:
1. In applicatIons where the external frequency mput IS not speCIfIed,
EXTFREQ must be tIed to V ss.
2. ICS2494/94AM(SOIC) PInout is Idenlical to ICS2494/94AN(DIP)

I2494/94ARevA090694
B-11

II

ICS2494
ICS2494A
Power Supply Conditioning

Circuit and Application Options
The ICS2494/94A will typically derive its frequency reference
from a series-resonant crystal connected between pins I and 2.
Where a high quality reference signal is available, such as in
an application where the graphics subsystem is resident on the
motherboard, this reference may directly replace the crystal.
This signal should be coupled to pin 1. If the reference signal
amplitude is less than 3.5 volts, a .047 microfarad capacitor
should be used to couple the reference signal into XTAL1. Pin
2 must be left open.

The ICS2494/94A is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free
power supply is available, no external components are required. However, in most applications it is judicious to decouple the power supply as shown in Figures 1 or 2. Figure 1 is the
normal configuration for 5 volt only applications. Which of the
two provides superior performance depends on the noise content of the power supplies. In general, the configuration of
Figure 1 is satisfactory. Figure 2 is the more conventional if a
12 volt analog supply is available, although the improved
performance comes at a cost of an extra component. The cost
of the discretes used in Figure 2, however, are less than the cost
of Figure 1's discrete components.
The number and differentiation of the analog and digital supply
pins are intended for maximum performance products. In most
applications, all VDDs may be tied together. The function of
the multiple pins is to allow the user to realize the maximum
performance from the silicon with a minimum degradation due
to the package and PCB. At the frequencies of interest, the
effects of the inductance of the bond wires and package lead
frame are non-trivial. By using the multiple pins, rcs minimized the effect of packaging and minimized the interaction of
the digital and analog supply currents.

Figure 1

-~3~2

d_1R

18

4

17

5

~

MSO

19

~
FSO v
FS1 r.
STROBE
FS2 ().

FS3

20

6

(}

ICS2494
ICS2494A

22
v

¥2

Rl

() VCLK
-0

XTALOU T

16

15

7

14

8

13

9

12

10

11

,..,

~

~

-'-

B-12

5.0V

MCLK
MS1

ICS2494
ICS2494A
Applications
Layout Considerations
Utilizing the ICS2494194A in video graphics adapter cards or
on PS2 motherboards is simple but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised in ensuring that components
not related to the ICS2494194A do not share its ground. In
applications utilizing a multi-layer board, VSS should be directly connected to the ground plane. Multiple pins are utilized
for all analog and digital VSS and VDD connections to permit
extended frequency VCLK operation to 135 MHz. However,
in all cases, all VSS and VDD pins should be connected.

Figure 2

Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2494/94A provide the bus clock for the rest of the system.
This eliminates the need for an additional 14.31818 MHz
crystal oscillator in the system, saving money as well as board
space. To do this, the XTALOUT (18) output should be buffered with a CMOS driver.

Output Circuit Considerations
5.0V

~I

rllH

~

rso

4

F"SI
STROBE
rS2
rS3

:5

VCLK
XTALOU T

IS
17

ICS2494

6
7

1

19

,.....1

MSO

The ICS2494194A is not sensitive to the duty cycle of the bus
clock; however, the quality of this signal varies considerably
with different motherboard designs. As the quality of this
signal is typically outside of the control of the graphics adapter
card manufacturer, it is suggested that this signal be buffered
on the graphics adapter board. XTAL2 (2) must be left open in
this configuration.

1CS2494A

S
9

....-!!l..

16
15
14

flL12
11

47D

"kC2 f7
1

RI

-'"

12.0V

=47V

MCLK
MSl

As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EMI.
To miniruize problems with meeting FCC EMI requirements,
the trace which connects VCLK (19) or MCLK (12) and other
components in the system should be kept as short as possible.
The ICS2494194A outputs have been designed to minimize
overshoot. In addition it may be helpful to place a ferrite bead
in these signal paths to liruit the propagation of high order
harmonics of this signal. A suitable device would be a Ferroxcube 56-590-65/4B or equivalent. This device should be placed
physically close to the ICS2494194A. A 33 to 47 Ohm series
resistor, sometimes called source termination, in this path may
be necessary to reduce ringing and reflection of the signal and
may reduce phase-jitter as well as EMI.

Digital Inputs
Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between XTALl (1) and XTAL2 (2). In
ffiM-compatible applications this will typically be a 14.31818
MHz crystal, but fundamental mode crystals between 10 MHz
and 25 MHz have been tested. Maintain short lead lengths
between the crystal and the ICS2494194A. In some applications, it may be desirable to utilize the bus clock. If the signal
amplitude is equal to or greater than 3.5 volts, it may be
connected directly to XTALl (1). If the signal amplitude is less
than 3.5 volts, connect the clock through a .047 ruicrofarad
capacitor to XTALI (1), and keep the lead length of the
capacitor to XTALI (1) to a minimum to reduce noise susceptibility. This input is internally biased at VDD/2. Since TTL
compatible clocks typically exhibit a VOH of 3.5V, capacitively coupling the input restores noise immunity.

FSO (4), FSI (5), FS2 (7), and FS3 (8) are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired. STROBE (6), when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 3. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all zeros input state. MSO (9), MSI (11) and MS2 (3) are the
correspopding memory select inputs and are not strobed.

B-13

II

ICS2494
ICS2494A
Absolute Maximum Ratings
Supply Voltage ................
Input Voltage ..................
Output Voltage ................
Clamp Diode Current ...........
Output Current per Pin ..........
Operating Temperature ..........
Storage Temperature ............
Power Dissipation ..............

Voo ............ -O.SV to +7V
VIN ............. -O.SV to Voo+O.5V
VOUT ........... -O.5V to VDD+O.SV
VIK & 10K ....... ±30mA
lOUT ............ ±SOmA
To . . . . . . . . . . . . .. 0 °C to 70°C
Ts . . . . . . . . . . . . .. -85°C to + ISO °C
Po .............. SOOmW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation it is recommended that VIN and VOUT be constrained
to >= Vss and <=Voo.

DC Characteristics (0 °C to 70°C)
SYMBOL
Voo
VIL
VIH
IIH
VOL
VOH
100

Rup •
Cm
COUI

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
Output High Voltage
Supply Current
Internal Pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance

MIN
4.0
Vss
2.0
2.4

MAX
S.S
0.8
Vdd

UNITS
V
V
V

10

uA

0.4

-

35
200
8
12

V
V
rnA
KOhm
pF
pF

-

SO

-

* The following inputs have pull-ups: FSO-3, MSO-l, STROBE.

Frequency Pattern Availability
ICS offers the largest variety of standard frequency patterns in
the industry, supporting all popular VGA controller devices.
The attached listing provides the selection as of this publication
date. Contact your local ICS sales office for latest frequency
pattern availability.

B-14

CONDITIONS
Vdd=5V
Vdd=SV
Yin = Vee
IoJ=4.0mA
Ioh=4.0mA
Vdd = 5Y. VCLK = 80 MHz
Vdd = Sy. Vin=OV
Fe= 1 MHz
Fe= 1 MHz

ICS2494
ICS2494A
AC Timing Characteristics
The following notes apply to all parameters presented in this section:
I. Xtal Frequency = 14.31818 MHz

2. Tc= lIFc
3.
4.
5.
6.
7.
8.

All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC.
Output pin loading = 25pF
Duty cycle is measured at IAV.
Supply Voltage Range = 4.0 to 5.5 Volts
Temperature Range = 0 °c to 70°C
SYMBOL

PARAMETER

Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr
Tf
-

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency

-

MIN
STROBE TIMING
20
10
10
MCLK AND VCLK TIMINGS

MAX

NOTES

-

-

3
3
0.5
135
15

-

Duty Cycle 40% min. to
60% max.
%
MHz
ns

Tpw

STROBE

/

~
!

:

*

FSO-FSJ

I-

Tsu

-+-

Thd

>K
-I

Figure 3

Ordering Information
ICS2494AN-XXX or ICS2494AM-XXX
Example:

ICS XXXX M -XXX

TL'--__

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
N=DIP (Baslic)
M=SOIC

' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - Prefix

rcs, AV=Standard Device; GSP=Geniock Device

B·1S

-'-,-~

II

ICS2494/2494A
ICS2494 Standard Patterns

ICS produces a selection of standard pattern ICS2494's pre-programmed for compatibility with many popular VGA
chip sets. Custom patterns are also available, although a significant volume commitment and/or one-time mash charge will
apply. Contact ICS sales for details.

ICS Part
Number

Compatible
. VOA
ChIpsets
Video Clock
Address
!HEX)
0
I
2
3
4
5
6
7
8

9
A
B
C
D
E
F
Memory
Clock
Address
!HEX)
0
1
2
3

ICS2494-

ICS2494·

ICS2494-

240

244

245/307

Texas. Instr.
TMS34010
TMS34020

ICS2494A
317*3
Motherboard
Applications
(CPU Clocks)

Frequency
(MHz)
50.350
56.644
65.000
72.000
80.000
89.800
63.000
75.000
25.175
28.322
31.500
36.000
40.000
44.900
50.000
65.000

Frequency
(MHz)
25.175
28.332
28.636
36.000
40.000
42.954
44.900
57.272
60.000
63.960
75.000
80.000
85.000
99.000
102.000
108.000

Frequency
(MHz)
20.000
24.000
32.000
40.000
50.000
66.667
80.000
100.000
54.000
70.000
90.000
110.000
25.000
33.333
40.000
50.000

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

32.900
35.600
43.900
49.100

40.000
41.612
44.744
50.000

64.000
40.000
48.000
60.000

ICS2494236
ICS2494A·
310*1
Cirrus Logic
OD641O

ICS 9294237
ICS2494A304*2
Tseng Labs
ET4000
ET400-W32
AcerM3125

Frequency
(MHz)
XTAL
65.028
EXTFREO
36.000
25.175
28.322
24.000
40.000
44.900
50.350
16.257
32.514
56.644
20.000
41.539
80.000

ICS2494247

ICS2494253

ICS2494256

Cirrus Logic
OD5320

NCR
77C22E

S3
86C911
86C924

Frequency
(MHz)
50.350
56.644
65.000
72.000
80.000
89.800
63.000
75.000
25.175
28.322
31.500
36.000
40.000
44.900
50.000
77.500

Frequency
(MHz)
XTAL
16.257
EXTFREO
32.514
25.175
28.322
24.000
40.000
XTAL
16.257
EXTFREO
36.000
25.175
28.322
24.000
40.000

Frequency
(MHz)
25.175
28.322
40.000
65.000
44.900
50.000
130.000
75.000
25.175
28.322
EXTFREO
EXTFREO
60.000
80.000
EXTFREO
EXTFREO

Frequency
(MHz)
25.175
28.322
40.000
EXTFREO
50.000
77.000
36.000
44.889
130.000
120.000
80.000
31.500
110.000
65.000
75.000
72.000

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

16.000
24.000
50.000
66.667

40.000
41.612
44.744
50.000

31.000
36.400
43.900
49.100

50.000
60.000
65.000
75.000

55.000
75.000
70.000
80.000

*1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-317 directly replaces ICS2494-244.
*4 ICS2494A-318 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)

B-16

Ie S2494/2494A
ICS Part
Number

ICS2494260

ICS2494263

Compatible
VGA
Chipsets

Weltek
W5086
W5186

Video Clock
Address
!HEX)
0
I
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Memory
Clock
Address

ICS2494273

ICS2494275

ICS2494277

ICS2494280

ICS2494281

Headland
HT216
HT216-32

S3
86C801
86C805
86C928

NCR
77C22E+

S3
86C801
86C805

Tseng

Frequency
(MHz)
25.175
28.322
EXT
44.900
41.539
78.000
79.200
80.000
31.469
35.402
EXTFREO
56.125
51.924
91.000
87.406
36.000

Frequency
(MHz)
25.175
28.322
40.000
32.500
50.350
65.000
38.000
44.900
31.500
36.000
80.000
63.000
50.000
100.00
76.000
110.000

Frequency
(MHz)
25.175
28.322
40.000
EXTFREO
50.000
77.000
36.000
44.889
130.000
120.000
80.000
31.500
110.000
65.000
75.000
94.500

Frequency
(MHz)
25.175
28.322
36.000
65.000
44.900
50.000
80.000
75.000
56.644
63.000
72.000
130.000
90.000
100.000
110.000
120.000

Frequency
(MHz)
25.175
28.322
40.000
EXT
50.000
77.000
36.000
44.889
130.000
120.000
80.000
31.500
110.000
65.000
75.000
94.500

Frequency
(MHz)
50.350
56.644
65.000
72.000
80.000
89.800
63.000
75.000
83.078
93.463
100.000
104.000
108.000
120.000
130.000
134.700

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

36.000
44.000
49.000
40.000

51.924
41.539
44.900
56.125

70.000
63.830
60.000
81.000

45.000
38.000
52.000
50.000

50.000
60.000
65.000
75.000

55.000
60.000
70.000
65.000

50.000
55.000
60.000
65.000

ICS2494271/321

NCR
77C22E

ICS2494
266
ICS2494318*4
CIrrus Logic
GD5410

Frequency
(MHz)
50.350
56.644
33.250
52.000
80.000
63.000
EXTFREQ_
75.000
25.175
28.322
.31.500
36.000
40.000
44.900
50.000
65.000

Frequency
(MHz)
25.175
28.322
36.000
65.000
44.900
50.000
80.000
75.000
25.175
28.322
EXTFREO
EXTFREO
60.000
80.000
EXTFREO
EXTFREO

Frequency
(MHz)
30.250
65.000
85.000
36.000
25.175
283.322
34.000
40.000
44.900
50.350
31.500
32.500
63.000
72.000
75.000
80.000

Frequency
(MHz)

Frequency
(MHz)

40.000
33.333
45.000
50.000

50.000
40.000
65.000
75.000

·-·-c··c •..

_ ..

,..•..

Y:'cc-;': .

,..

,tt ,'0:;:c,:;

.: :..,·:cc.;;'~.',·

!HEX)
0
I
2
3

*1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-317 directly replaces ICS2494-244.
*4 ICS2494A-318 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)

B·17

I CS2494/2494A
ICS Part
Number
Compatible
VGA
Chin sets
Video Clock
Address
(HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Memory
Clock
Address
(HEX)
0
1
2
3

ICS2494A305
S3
86C924

ICS2494306
Cirrus Logic
GD6410
GD6412

ICS2494314
Texas
Instruments

ICS2494A319

ICS2494A320
AdvanceLogic
ALG2101
ALG2201

ICS2494A322

ICS2494A324
Tseng Labs
ET4000
ET4000W32

Frequency
(MHz)
25.175
28.322
40.000
EXTFREO
50.000
77.000
36.000
44.889
130.000
120.000
80.000
31.500
110.000
65.000
75.000
94.500

Frequency
(MHz)
XTAL
65.000
EXTFREO
36.000
25.175
28.322
24.000
40.000
44.900
50.350
16.257
32.514
56.644
20.000
41.539
80.000

Frequency
(MHz)
12.273
13.500
14.750
25.175
28.322
36.000
40.000
44.900
50.000
64.000
75.000
80.000
100.000
108.000
120.000
135.000

Frequency
(MHz)
25.175
28.322
40.000
72.000
50.000
77.500
36.000
44.900
63.000
100.000
80.000
31.500
110.000
65.000
75.000
94.500

Frequency
(MHz)
50.350
56.644
89.800
72.000
75.000
65.000
63.000
80.000
57.272
85.000
94.000
96.000
100.000
108.000
110.000
77.000

Frequency
(MHz)
20.000
20.480
24.576
24.704
25.216
25.248
25.600
26.000
28.800
29.491
30.720
32.768
33.6000
44.736
9.600
20.500

Frequency
(MHz)
50.000
56.644
65.000
72.000
80.000
89.800
63.000
75.000
83.078
93.463
100.000
104.000
108.000
120.000
130.000
134.700

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

55.000
75.000
70.000
80.000

32.900
35.600
43.900
39.900

32.000
40.000
48.000
60.000

48.000
52.500
55.000
50.000

76.000
80.000
85.000
90.000

15.360
13.947
13.947
24.000

50.000
56.000
60.000
65.000

*1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-317 directly replaces ICS2494-244.
*4 ICS2494A-318 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)

B·18

II
ICS Part
Number
Compatible
VGA
Chinsets
Video Clock
Address
(HEX)
0
I

2
3
4
5
6
7
8
9
A
B
C
D
E
F
Memory
Clock
Address
IHEX)
0
1
2
3

Ie S2494/2494A
ICS2494325
Maxtek

ICS2494326

ICS2494330

ICS2494334

ICS2494-

ICS2494

ICS2494-

Frequency
(MHz)
25.175
28.322
31.500
36.000
40.000
44.900
50.350
65.000
56.644
72.00
75.000
77.000
80.000
94.500
120.000
108.000

Frequency
(MHz)
66.000
62.000
61.236
61.000
60.500
60.000
59.300
59.000
58.968
57.200
56.200
55.500
40.000
38.200
32.500
30.500

Frequency
(MHz)
18.432
31.470
50.000
EXTFREO
48.000
54.000
59.200
75500
96.000
108.778
73.410
50.490
110.439
100.000
125.000
135.000

Frequency
(MHz)
25.175
28.322
31500
36.000
40,000
44.900
50000
65.000
75.000
77500
80.000
90.000
100.000
1l0.OOO
126.000
13S.000

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

45.000
SO.OOO
6S.000
70.000

48.000
50.000
40.000
60.000

47.720
4S.000
40.000
50.000

60.000
SO.OOO
5S.000
50.000

*1 ICS2494A-31O directly replaces ICS2494-236.
*2 ICS2494A-304 directly replaces ICS2494-237.
*3 ICS2494A-3l7 directly replaces ICS2494-244.
*4 ICS2494A-318 directly replaces ICS2494-266.
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info:
ICS2494M-XXX or ICS2494N-XXX (M= SOIC pkg., N= DIP pkg .• XXX= Pattern number)
ICS2494AM-XXX or ICS2494AN-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)

8-19

B·20

II

ICS2495

Integrated
Circuit
Systems, Inc.

Dual Video/Memory Clock Generator
Features
•
•
•
•
•
•
•

Low cost - eliminates need for multiple crystal clock
oscillators in video display subsystems
Mask-programmable frequencies
Pre-programmed versions for Industry Standard VGA
chips
Glitch-free frequency transitions
Internal clock remains locked when the external frequency input is selected
Low power CMOS device technology
SmaIl footprint - 16-pin DIP or SOIC

•
•
•
•
•
•
•

Buffered Xtal Out
Integral Loop Filter components
Fast acquisition of selected frequencies, strobed or nonstrobed
Guaranteed performance up to 135 MHz
Excellent power supply rejection
Advanced PLL for low phase-jitter
Frequency change detection circuitry enhances new frequency acquisition and eliminates problems caused by
programs that rewrite frequency information

Pin Configuration

Description
The ICS2495 Clock Generator is an integrated circuit dual
phase-locked loop frequency synthesizer capable of generating
16 video frequencies and 4 memory clock frequencies for use
with high performance video display systems. Utilizing CMOS
technology to implement all linear, digital and memory functions, the ICS2495 provides a low-power, small-footprint,
low-cost solution to the generation of video dotcIocks. Outputs
are compatible with XGA, VGA, EGA, MCGA, CGA, MDA,
as well as the higher frequencies needed for advanced applications in desktop publishing and workstation graphics. Provision is made via a single level custom mask to implement
customer specific frequency sets. Phase-locked loop circuitry
permits rapid glitch-free transitions between clock frequencies.

XTAL2

In addition to providing 16 clock rates, the ICS2495 has
provisions to multiplex an externally-generated signal source
into the VCLK signal path. Internal phase-locked frequencies
continue to remain locked at their preset values when this mode
is selected. This feature permits instantaneous transition from
an external frequency to an internally-generated frequency.
Printed circuit board testing is simplified by the use of these modes
as an external clock generated by the ATE tester can be fed
through, permitting synchronous testing of the entire system.

16

XTAL1

EXTFREQ

2

15

VCLK

FSO

3

14

XTALOUT

FS1

4

13

VSS

STROBE

5

12

VDD

FS2

6

11

N/C

FS3

7

10

MCLK

MSO

8

9

MS1

16-Pin DIP or sOle
K-4, K·6
Notes:
1. ICS2495M(SOIC) pinout IS identical to ICS2495N(DIP).

IICS2595RevA090694

B-21

ICS2495
Reference Oscillator & Crystal Selection

Layout Considerations

In cases where the on-chip crystal oscillator is used to generate
the reference frequency, the accuracy of the crystal oscillation
frequency will have a very small effect on output accuracy.

Utilizing the ICS2495 in video graphics adapter cards or on
PS2 motherboards is simple, but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised to ensure that components
not related to the ICS2495 do not share its ground. In applications utilizing a multi-layer board, Vss should be directly
connected to the ground plane.

The external crystal and the on-chip circuit implement a Pierce
oscillator. In a Pierce oscillator, the crystal is operated in its
parallel-resonant (also called anti-resonant mode). This means
that its actual frequency of oscillation depends on the effective
capacitance that appears across the terminals of the quartz
crystal. Use of a crystal that is characterized for use in a
series-resonant circuit is fine, although the actual oscillation
frequency will be slightly higher than the value stamped on the
crystal can (typically 0.025%-0.05% or so). Normally, this
error is not significant in video graphics applications, which is
why the ICS2495 will typically derive its frequency reference
from a series resonant crystal connected between pins 1 and
16.
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, the crystal should be
mounted as close as possible to the package. Avoid routing
digital signals or the ICS2495 outputs underneath or near these
traces. It is also desirable to ground the crystal can to the
ground plane, if possible.

Power Supply Conditioning
The ICS2495 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free
power supply is available, no external components are required. However, in most applications it is judicious to decouple the power supply as shown in Figure 1.

Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate crystal should be connected between XTALI (16) and XTAL2 (1). In IBM compatible applications this will typically be a 14.31818 MHz crystal,
but fundamental mode crystals between 10 MHz and 25 MHz
have been tested. Maintain short lead lengths between the
crystal and the ICS2495. In some applications, it may be
desirable to utilize the bus clock. If the signal amplitude is
equal to or greater than 3.5 volts, it may be connected directly
to XTALI (16). If the signal amplitude is less than 3.5 volts,
connect the clock through a .047 microfarad capacitor to
XTALI (16), and keep the lead length of the capacitor to
XTALI (16) to a minimum to reduce noise susceptibility. This
input is internally biased at VDDI 2. Since TTL compatible
clocks typically guarantee a VOH of only 2.8Y, capacitively
coupling the input restores noise immunity. The ICS2495 is
not sensitive to the duty cycle of the bus clock; however, the
quality of this signal varies considerably with different motherboard designs. As the quality of this signal is typically outside
of the control of the graphics adapter card manufacturer, it is
suggested that this signal be buffered on the graphics adapter
board. XTAL2 (1) must be left open in this configuration.

10
5.0V

15

EXTFREQ
FSO
FS1
STROBE
FS2
FS3
MSO

NOTES:

14

3
4
5

VCLK
XTALOUT

13

ICS2495

12

6

11

N/C

7

10

MCLK

8

9

MS1

FS3-FSO, MSl-MSO, EXTFREQ, and STROBE mputs are all equipped with pull-ups and need not be bed hIgh.
Mount decoupling capacitors as close as possible to the deVIce and connect devlCe ground to the ground plane where avaIlable.
Mount crystal and Its circUlt traces away from SWItching digital hnes and the VCLK, MCLK and XTALOUT lines.

Figure 1
B-22

II

ICS2495

Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2495 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
Depending on the load, it may be judicious to buffer XTALOUT when using it to provide the system clock.

Output Circuit Considerations
As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EM!.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK or MCLK and other components in the system should be kept as short as possible. The
ICS2495 outputs have been designed to minimize overshoot.
In addition, it may be helpful to place a ferrite bead in these
signal paths to limit the propagation of high-order harmonics
of this signal. A suitable device would be a Ferroxcube 56-59065/4B or equivalent. This device should be placed physically
close to the ICS2495. A 33 to 47 Ohm series resistor, sometimes called source termination, in this path may be necessary
to reduce ringing and reflection of the signal and may thereby
reduce phase jitter as well as EM!.

External Frequency Sources
EXTFREQ on versions so equipped by the programming, is
an input to a digital multiplexer. When this input is enabled by
the FSO-3 selection, the signal driving pin 2 will appear at
VCLK (IS) instead of the PLL output. Internally, the PLL will
remain in lock at the frequency selected by the ROM code.
The programming option also exists to output the crystal oscillator output on VCLK. In the case where XTALI is being
driven by an external oscillator, then this frequency would
appear on VCLK if so programmed.

Digital Inputs
FSO (3), FSI (4), FS2 (6), and FS3 (7), are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired. STROBE (5) when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 2. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all zeros input state. MSO (8) and MSI (9) are the corresponding memory select inputs and are not strobed.

B-23

ICS2495
Pin Descriptions
The following table provides the pin description for the 16-pin ICS2495 packages.
PIN SYMBOL
XTAL2
EXTFREQ
PSO
PSI
STROBE
PS2
PS3
MSO
MSI
MCLK

TYPE
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT

11

N/C

-

12

VDD
VSS
XTALOUT
VCLK
XTALI

PIN NUMBER
1
2
3
4
5
6
7
8

9
10

13
14
15
16

-

OUT
OUT
IN

DESCRIPTION
Crystal interface
External clock input (if so programmed)
Control input for VCLK selection
Control input for VCLK selection
Strobe for latching PS (0-3) (High enable)
Control input for VCLK selection
Control input for VCLK selection
Select input for MCLK selection
Select input for MCLK selection
Memory Clock Output
Not Connected
Power
Ground
Buffered Crystal Output
Video Clock Output
Reference input clock from system

Absolute Maximum Ratings
Ambient Temperature
under bias
Storage temperature
Voltage on all inputs
and outputs with
respect to Vss

Standard Test Conditions
The characteristics below apply for the following standard test
conditions, unless otherwise noted. All voltages are referenced
to V ss (OV Ground). Positive current flows into the referenced
pin.

o°C to 70°C
-40 °C to 125°C
0.3 to 7 Volts

Operating Temperature
range
Power supply voltage

Note: Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.

B·24

o°C to 70 °C
4.75 to 5.25 Volts

ICS2495
DC Characteristics at 5 Volts Voo
SYMBOL
VDD
VIL
Vm
1m
VOL
VOH
IDD
Rup
Cm
CoUI

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
VCLK,MCLK
Output Low Voltage:
XTALOUT
VCLK,MCLK
Output High Voltage:
XTALOUT
Supply Current
Internal Pullup Resistors
Input Pin Capacitance
Output Pin Capacitance

MIN
4.75
Vss
2.0

MAX
5.25
0.8
VDD
10

-

-

UNITS
V
V
V
I1A
V
V
V
V
rnA
Kohms
pF
pF

0.4
0.4

-

-

2.4
2.4
50
-

-

30
-

8
12

-

CONDITIONS
VDD=5V
VDD=5V
Vm = Vee
IOL= 8.0 rnA
IOL=4.0mA
IOH= 8.0 rnA
IOH=4.0mA
VDD=5V
VIN= O.OV
Fe= 1 MHz
Fe= 1 MHz

AC Timing Characteristics
The following notes apply to all of the parameters presented in this section.
1.
2.
3.
4.
5.
6.
7.

REFCLK = 14.318 MHz
Te = lIFe
All units are in nanoseconds (ns).
Maximum jitter within a range of 30 Jls after triggering on a 400 MHz scope.
Rise and fall time between 0.8 and 2.0 VDC unless otherwise stated.
Output pin loading = 15pF.
Duty cycle measured at 1.4 volts.
SYMBOL

PARAMETER

MIN
STROBE TIMING
20
10
10
MCLK and VCLK TIMINGS
-

Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr
If

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for Pass Through
Frequency
Output Enable to Tristate
(into and out of) time

-

-

-

8-25

MAX

NOTES

-

2
2
0.5
135
20

Duty Cycle 40% min. to
60% max.
%
MHz
ns

15

ns

ICS2495

Tpw

STROBE

-------"*"--~-----'>K"----

FSO-FS3

t-

Tsu

--1-

Thd

-t

Figure 2

Ordering Information
ICS2495N-XXX or ICS2495M-XXX
Example:

ICS XXXX M -XXX

T

IT

I

OM_,.""""

",_N=b«"o''';';'.=""foc""",wI...
Package Type
N=DIP (!'last!c)
M=SOIC

Device Type (consists of3 or 4 digit nnmbers)
"----------Prefix

rcs, AV=Standard DevICe; GSP=Genlock Device

B-26

ICS2495
ICS2495 Pattern Request Form
Custom patterns are also available, although a significant volume commitment and/or one-time mask charge will apply.
Contact rcs sales for details.
rcs Part
Number

rCS2495-

ICS2495-

Compatible
VGA
Chip sets

Custom
Pattern # 1

Custom
Pattern # 2

Video Clock
Address (HEX)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

0
1
2
3
4
5

6
7
8
9
A
B

C
D

E
F
Memory Clock
Address (HEX)
0
1
2
3

Custom pattern # 1 reference frequency =
Custom pattern # 2 reference frequency =
Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
If the internal frequency to which the rCS2495 remains locked to is critical when EXTFREQ is selected, it should be
specified.
Order info: rCS2495M-XXX or rCS2495N-XXX (M= SOlC pkg., N= DIP pkg., XXX= Pattern number)

B-27

~

~

B-28

II

ICS2496

Integrated
Circuit
Systems, Inc.

Dual Voltage Video/Memory Clock Generator
•

Features
•
•
•
•
•
•
•
•
•

Specified for dual voltage operation (VDD =3.3V or 5V)
but operates continuously from 3.OV to 5.25V
Power-down input for extended battery life in portable
applications
Guaranteed performance up to 110 MHz (at 3.3V)
or 135 MHz (at 5V)
Advanced PLL for low phase-jitter
Low power CMOS device technology
Excellent power supply rejection
Integral Loop Filter components
Mask-programmable frequencies
Small footprint - 16-pin DIP or SOIC

•
•

•
•
•
•

Generates 16 video clock frequencies derived from a
14.318 MHz system clock reference frequency
Provision for external frequency input
Video clock is selectable among the 16 internally generated clocks, one external clock, or the buffered crystal
oscillator
Internal clock remains locked when the external frequency
input is selected
On-chip generation of four memory clock frequencies
Patented technique eliminates cross-interference between
video and memory clocks
Fast acquisition of selected frequencies, strobed or nonstrobed

Pin Configuration

Description
The ICS2496 has been specifically designed to serve the
portable PC market with operation at either 3.3V or 5V with a
comprehensive power-saving shut down mode.
The ICS2496 Clock Generator is a dual phase-locked loop
frequency synthesizer capable of generating 16 video frequencies and four memory clock frequencies for use with high
performance video display systems. Utilizing CMOS technology to implement all linear, digital and memory functions, the
ICS2496 provides a low power, small footprint, low cost
solution to the generation of video dot clocks. Provision is
made via a single level custom mask to implement customer
specific frequency sets. Phase-locked loop circuitry permits
rapid glitch-free transitions between clock frequencies.

XTAL2

XTAL1

EXTFREQ

VCLK

FSO

XTALOUT

FS1

VSS

STROBE

VDD

In addition to providing 16 clock rates, the ICS2496 has
provisions to multiplex an externally-generated signal source
into the VCLK signal path. Internal phase-locked frequencies
continue to remain locked at their preset values when this mode
is selected. This feature permits instantaneous transition from
an external frequency to an internally-generated frequency.
Printed circuit board testing is simplified by the use of these
modes, as an external clock generated by the ATE tester can be
fed through, permitting synchronous testing of the entire system.

FS2

PWRDN

FS3

MCLK

MSO

8

9

MS1

16-Pin DIP or sOle
K-4, K·6

Notes:
1. ICS2496M(SOIC) pmout IS Idenbcai to ICS2496N(DIP).

B·29

II

ICS2496

Reference Oscillator and Crystal Selection

Circuit Function and Application
"Power-down"
The ICS2496 has been optimized for use in battery operated
portables. It can be placed in a power-down mode which drops
its supply current requirement below 1 microamp. When
placed in this mode, the digital inputs FSO-3, STROBE, MSOI, and EXTFREQ may be either high or low or floating without
causing an increase in the ICS2496 supply current.
The PWRDN pin must be low (It has an internal pull-down.)
in order to place the device in its low power state. The output
pins (VCLK and MCLK) are driven high and XTALOUT is
driven low by the ICS2496 when it is in its low power state.
If a crystal is being used, nothing needs to be done to achieve
low power. If XTAL 1 is being driven by an external source, it
may be driven low or high without a power penalty. If XTALl
is at an intermediate voltage (Vss +0.5V < VIN < VDD -0.5),
there will be a small increase in supply current. If XTALI is
driven at 14.318 MHz while the chip is in power-down, the
ICS2496 supply current will increase to approximately
1.2 rnA.
The STROBE (pin 5) may be used to guard against inadvertent frequency changes during power-downlpower-up sequences. By holding the STROBE low during power-down and
power-up sequences, the ICS2496 will retain the most recent
video frequency selection.

In cases where the on-chip crystal oscillator is used to generate
the reference frequency, the accuracy of the crystal oscillation
frequency will have a very small effect on output accuracy.
The external crystal and the on-chip circuit implement a Pierce
oscillator. In a Pierce oscillator, the crystal is operated in its
parallel-resonant (also called anti-resonant) mode. This means
that its actual frequency of oscillation depends on the effective
capacitance that appears across the terminals of the quartz
crystal. Use of a crystal that is characterized for use in a
series-resonant circuit is fine, although the actual oscillation
frequency will be slightly higher than the value stamped on the
crystal can (typically 0.025%-0.05% or so). Normally, this
error is not significant in video graphics applications, which is
why the ICS2496 will typically derive its frequency reference
from a series-resonant crystal connected between pins 1 and 16.
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, the crystal should be
mounted as close as possible to the package. Avoid routing
digital signals or the ICS2496 outputs underneath or near these
traces. It is also desirable to ground the crystal can to the
ground plane, if possible.

Power Supply Conditioning
The ICS2496 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free
power supply is available, no external components are required. However, in most applications it is judicious to decouple the power supply as shown in Figure 1.

10

Jf3JP2

I
1

,/I.

-c

T~T22

16

EXTFREQ

2

15

VSO
VS1

3

14

STROBE

5

VS2

6

11

PWRDN

VS3

7

10

MSO

8

9

MCLK
MS1

lL

4

S.OV

VCLK
XTALOUT

ICS2496 R-

NOTES:

FS3-FSO, MS l-MSO, EXTFREQ, and STROBE mputs are all eqUIpped WIth pull-ups and need not be tIed hIgh.
PWRDN mput has an internal pull-down and must be driven or ned high for full deVIce functlOn
Mount decouphng capacitors as close as possible to the deYlce and connect deVIce ground to the ground plane where aVll1lable.
Mount crystal and Its CtrCUlt traces away from sWltclung dtgital hnes and the VCLK, MeLK, and XTALOUT hnes.

Figure 1
B-30

II

ICS2496

Layout Considerations

Output Circuit Considerations

Utilizing the ICS2496 in video graphics adapter cards or on
PS2 motherboards is simple, but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised in ensuring that components
not related to the ICS2496 do not share its ground. In applications utilizing a multi-layer board, V ss should be connected
directly to the ground plane.

As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EMI.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK or MCLK and other components in the system should be kept as short as possible. The
ICS2496 outputs have been designed to minimize overshoot.
In addition, it may be helpful to place a ferrite bead in these
signal paths to limit the propagation of high order harmonics
of this signal. A suitable device would be a Ferroxcube 56-5906514B or equivalent. This device should be placed physically
close to the ICS2496. A 33 to 47 Ohm series resistor, sometimes called source termination, in this path may be necessary
to reduce ringing and reflection of the signal and may thereby
reduce phase-jitter as well as EMI.

Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate crystal should be connected between XTALl (16) and XTAL2 (1). In IBM-compatible applications this will typically be a 14.31818 MHz crystal,
but fundamental mode crystals between 10 MHz and 25 MHz
have been tested. Maintain short lead lengths between the
crystal and the ICS2496. In some applications, it may be
desirable to utilize the bus clock. If the signal amplitude is
equal to or greater than 3.5 volts, it may be connected directly
to XTALI (16). If the signal amplitude is less than 3.5 volts,
connect the clock through a .047 microfarad capacitor to
XTALI (16), and keep the lead length of the capacitor to
XTALI (16) to a minimum to reduce noise susceptibility. This
input is internally biased at VDDI 2. Since TTL compatible
clocks typically guarantee a VOH of only 2.8Y, capacitively
coupling the input restores noise immunity. The ICS2496 is
not sensitive to the duty cycle of the bus clock; however, the
quality of this signal varies considerably with different motherboard designs. As the quality of this signal is typically outside
of the control of the graphics adapter card manufacturer, it is
suggested that this signal be buffered on the graphics adapter
board. XTAL2 (1) must be left open in this configuration.

Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2496 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
Depending on the load, it may be judicious to buffer XTALOUT when using it to provide the system clock.

External Frequency Sources
EXTFREQ on versions so equipped by the programming, is
an input to a digital multiplexer. When this input is enabled by
the FSO-3 selection, the signal driving pin 2 will appear at
VCLK (15) instead of the PLL output. Internally, the PLL will
remain in lock at the frequency selected by the ROM code.
The programming option also exists to output the crystal
oscillator output on VCLK. In the case where XTALI is being
driven by an external oscillator, then this frequency would
appear on VCLK if so programmed.

Digital Inputs
FSO (3), FSI (4), FS2 (6), and FS3 (7), are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired. STROBE (5), when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 2. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all-zeros input state. MSO (8) and MSI (9) are the corresponding memory select inputs and are not strobed.

B-31

ICS2496
Pin Descriptions
The following table provides the pin description for the 16-pin ICS2496 packages:
PIN NUMBER
I
2
3
4
5
6
7
8

9
10

11
12
13
14
15
16

PIN SYMBOL
XTAL2
EXTFREQ
FSO
FSI
STROBE
FS2
FS3
MSO
MSI
MCLK
PWRDN
VDD
VSS
XTALOUT
VCLK
XTALl

TYPE
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
IN

DESCRIPTION
Crystal interface
External clock input (if so programmed)
Control input for VCLK selection
Control input for VCLK selection
Strobe for latching FS (0-3) (High enable)
Control input for VCLK selection
Control input for VCLK selection
Select input for MCLK selection
Select input for MCLK selection
Memory Clock Output
Power-down Control (low for power-down)
Power
Ground
Buffered Crystal Output
Video Clock Output
Reference input clock from system

Absolute Maximum Ratings
Ambient Temperature
under bias
Storage temperature
Voltage on all inputs
and outputs with
re~ct to VSS

Standard Test Conditions
The characteristics below apply for the following standard test
conditions, unless otherwise noted. All voltages are referenced
to GND. Positive current flows into the referenced pin.

o°C to 70 °C
-40 °C to 125 °C
0.3 to 7 Volts

Operating Temperature
range
Power supply voltage

Note: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

B-32

o °C to 70 °C
3.0 to 5.25 Volts

II

ICS2496

DC Characteristics at 5 Volts Voo
SYMBOL
VDD
VIL
VIR
IIH
VOL
VOH
IDD
Rup
Cm
Cout
IpN
RDN

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
VCLK,MCLK
Output Low Voltage:
XTALOUT
VCLK,MCLK
Output High Voltage:
XTALOUT
Supply Current
Internal Pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance
Power-down Supply Current
Internal Pull-down Equivalent

MIN
4.75
Vss
2.0
-

MAX
5.25
0.8
VDD
10

UNITS
V
V
V

0.4
0.4

V
V
V
V
rnA
Kohms
pF
pF

CONDITIONS
VDD=5V
VDD = 5V
Vm = Vee

~A

~A

IOL = 8.0 rnA
IOL = 4.0 rnA
IOH= 8.0 rnA
IOH =4.0 rnA
VDD=5V
VIN= O.OV
Fe = I MHz
Fe= I MHz
VDD=3.3V

-

Kohms

VIN=VDD=5V

UNITS
V
V
V

CONDITIONS

-

MAX
3.6
0.8
VDD
10

-

0.4
0.4

2.4
2.4
100
-

-

V
V
V
V
rnA
Kohms
pF
pF

-

2.4
2.4
50
-

20

-

30
-

8
12
1.0

DC Characteristics at 3.3 Volts VOO
SYMBOL
VDD
VIL
VIH
IIH
VOL
VOH
IDD
Rup
Cm
Cout
IPN
RDN

PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
VCLK,MCLK
Output Low Voltage:
XTALOUT
VCLK,MCLK
Output High Voltage:
XTALOUT
Supply Current
Internal Pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance
Power-down Supply Current
Internal Pulled-down Equivalent

MIN
3.0
Vss
2.0

-

20
-

-

8
12
1.0

50

-

AC Timing Characteristics
The following notes apply to all of the parameters presented in this section:

I.
2.
3.
4.
5.
6.
7.

REFCLK = 14.318 MHz
Te= lIFe
All units are in nanoseconds (ns).
Maximum jitter is within a range of 30 ~s after triggering on a 400 MHz scope.
Rise and fall time is between 0.8 and 2.0 VDC unless otherwise stated.
Output pin loading = 15pF
Duty cycle is measured at VDDI2 unless otherwise stated.

B-33

\

I;

VDD= 3.3V
VDD = 3.3V
Vm = VDD

~A

~A

IOL= 3.0 rnA
IOL = 1.5 rnA
IOH = 3.0mA
IOL = 1.5 rnA
VDD= 3.3V
VIN=O.OV
Fe= I MHz
Fe = I MHz
VDD=3.3V

Kohms

VIN =VDD =3.3V

,

ICS2496

r SYMH_O_L_·····~_ _ _ _ _.P_~_R_A_M_ET~E:.c.R=-----_ _ 1_-.:M=IN"----.l_-.-:.Mco,-A.:.oX"--___-=--=--_-_-'_N:..c_""'-OTES_.....

.Tp'w ------.
Tsu

~----

i

II

L

i

Strobe Pulse Width

STROBEl'

TIMI~~

~e.~~I..i : e~~~at~os~~~~~e

II

....

~~

-

~~~~~:i Error

120

MCLK and VCLKTIMINGS
··_· __

_ •.1

......
I

@

S.OV

I·__-=-.c~-,--

___

'--i

..... _. __.
__ .__ .,!
Duty Cycle 40% min. to
;
I 60% max.

%

Maximum Frequency
I Propagation Delay for Pass Through
I Frequency
i Output Enable to Tristate
I (mto and out 00 time
Tr

I

,MHz

I
I

1:: ________

--11

-.----1 Rise Time

Duty Cycle 40% min. to
60% max.

3
3

1

Tf

Fall Time
I Frequency Error
! Maximum Frequency
I:
I Propagation Delay for Pass Through
I
: Frequency
!I
: Output Enable to Tristate
~ ______LiirltK'-----+-

FSO- FS3

t-

Tsu

Thd

--;

Figure 2
Ordering Information
ICS2496N-XXX or ICS2496M-XXX
Example:

--1-

ICS XXXX M -XXX

I

I

"""""
N=b" (2." "¢' oom,""."<...'" Package Type
N=DIP (£laslIc)
M=SOIC

Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - Prefix
ICS, AV=Standard DeVIce; GSP=Genlock DeVIce

B-34

ROM

ood"''''''''i

ICS2496
ICS2496 Pattern Request Form
ICS produces a selection of standard pattern ICS2496's pre-programmed for compatibility with many popular VGA
chip sets, Custom patterns are also available, although a significant volume commitment and/or one-time mask charge will
apply. Contact ICS sales for details.

ICS Part
Number
Compatible
VGA
Chipsets
Video Clock
Address (HEX)
0
I
I

1

2

I

I

,

,

i

II

ICS2496- I ICS2496454
.
456

ICS2496452

Cirrus Logic Cirrus Logic Motherboard
GD6410
GD6412 Applications
(CPU Clocks)
Frequency Frequency
, (MHz)
(MHz)
XTAL

Frequency
(MHz)

XTAL

65.000
65.000
EXTFREQ EX'fFREQ

20.000
I

24.000
32.000

3

36.000

36.000

40.000

4

25.175

25.175

50.000

5

28.322

28.322

66.667

6

24.000

24.000

80.000

7

40.000

40.000

100.000

8

44.900

44.900

54.000

9

50.350

A

16.257

I

,
i

50.350

70.000

16.257

90.000

B

32.514

32.514

110.000

C

56.644

56.444

25.000

D

20.000

20.000

33.333

E

41.539

41.539

40.000

F

80.000

80.000

50.000

Memory
Clock
Address(HEX)

Frequency
(MHz)

Frequency
(MHz)

Frequency
(MHz)

0

32.900

32.900

1

35.600

35.600

16.000
24.000

2

43.900

43.900

3

49.100

39.900

50.000
66.667

I

Standard frequencies shown have been specified by and are supported by the respective VGA manufacturer.
All standard patterns shown above use 14.31818 MHz as the input reference frequency.
Order info: ICS2496M-XXX or ICS2496N-XXX (M= SOIC pkg., N= DIP pkg., XXX= Pattern number)

B-35

B

B-36

ICS2595

Integrated
Circuit
Systems, Inc.

•

Advance Information

User-Programmable Dual High-Performance Clock Generator
Description

Features

The ICS2595 is a dual-PLL (phase-locked loop) clock generator specifically designed for high-resolution, high-refresh
rate, video applications. The video PLL generates any of 16
pre-programmed frequencies through selection of the address
lines FSO-FS3. Similarly, the auxiliary PLL can generate any
one of four pre-programmed frequencies via the MSO & MSI
lines.

•

A umque feature of the ICS2595 is the ability to redefine
frequency selections in both the VCLK and MCLK synthesizers after power-up. This permits complete set-up of the frequency table upon system initialization.

•
•
•
•
•

Advanced rcs monolithic phase-locked loop
technology for extremely low jitter
Supports high-resolution graphics - VCLK output to
145 MHz
Completely integrated - requires only external crystal
(or reference frequency and decoupling)
Powerdown modes support portable computing
Sixteen selectable VCLK frequencies (all user reprogrammable)
Four selectable MCLK frequencies (all user reprogrammable)

Applications
•
•

PC Graphics
VGNSuper VGNXGA Applications

Block Diagram
XTALl
XTAL2

Crystal
Oscillator

PhaseFrequency
Comparator

Reference
Divider

Charge
Pump

EXTFREQ

VCO
VCLK

MCLK PLL (as above)
STROBE

FSO
FSl
FS2

FS3
MSO
MSl

VCLK Set &
Program
Mode
Interface

MCLK

MCLKSet

IICS2595RevA090794

B-37

ICS2595
Pin Configuration
XTAL1
XTAL2
EXTREFQ
FSO
FS1
STROBE
FS2
FS3
MSO
VSS

2
3
4
5
6
7
8
9
10

VDD
VCLK
XTALOUT
RESERVED
VSS
VAA
VSS
VDD
MCLK
MS1

19
18
17
16
15
14
13
12
11

20-Pin DIP or sOle
K-4, K-7

Pin Descriptions
PIN NUMBER

I

PIN NAME

DESCRIPTION

TYPE

XTALl

,
,

A

Quartz crystal connection lIReference Frequency Input.

A

Quartz crystal connection 2.

I

Extemal Frequency Input

2

XTAL2

3

EXTFREQ

4

FSO

I

VCLK PLL Frequency Select LSB.

5

FSI

I

VCLK PLL Frequency Select Bit.

7

FS2

I

VCLK PLL Frequency Select Bit.

8

FS3

I

VCLK PLL Frequency Select MSB.

6

STROBE

I

Control for Latch of VCLK Select Bits (FSO-FS3).

9

MSO

I

MCLK PLL Frequency Select LSB.

11

MSI

I

MCLK PLL Frequency Select MSB.

19

VCLK

18
12

XTALOUT

Buffered Referenced Clock Output

MCLK

0
0
0

MCLK Frequency Output

RESERVED

-

Must Be Connected to VSS.

VSS

P

Device Ground. All pins must be connected.

VDD

P

Output Stage V dd. All pins must be connected.

VAA

P

Synthesizer V dd.

17
10, 14, 16
13,20
15

VCLK Frequency Output

B-38

...

~

II

ICS2595

Digital Inputs
The FSO-FS3 pins and the STROBE pin are used to select the
desired operating frequency of the VCLK output from the 16
pre-programmed/user-programmed selections in the ICS2595.
These pins are also used to load new frequency data into the
registers.
The standard mterface for the ICS2595 matches the interface
ofthe industry standard ICS2494. That is, the FSO-FS3 inputs
access the device internals transparently when the STROBE
pin is high.
Optional configurations of the STROBE input mclude: positive-edge triggered, negative-edge triggered, and low-level
transparent (See Ordering Information).

VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the
appropriate data to the ICS2595 FS inputs. Do not perform any
further writes to the device for at least 50 milliseconds (assumes a 14.318 MHz reference). The synthesizer will output
the new frequency programmed into that location after a brief
delay (see time-out specifications).
Upon device power-up, the selected frequency will be the
frequency pre-programmed into address 0 until a deVIce write
is performed.

MCLK Output Frequency Selection
The MSO-MSI pins are used to directly select the desired
operating frequency of the MCLK output from the four preprogrammed/user-programmed selections in the ICS2595.
These inputs are not latched, nor are they involved with memory programming operations.

Programming Mode Selection
A programming sequence is defined as a period of at least 50
milliseconds (assumes 14.318 MHz reference) of no data
writes to the ICS2595 (to clear the shift register) followed by
a series of data writes (a, ,hown here):

B-39

FSO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

FSI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

FS2
START bit (must be "0")
"

RIW* control
"

LO (location LSB)

"
L1
"

L2

"
L3
"

L4 (location MSB)
"

NO (feedback LSB)
"

Nl

"
N2

"
N3
"

N4
"

N5

"
N6

"
N7 (feedback MSB)

"
EXTFREQ bit (selected if "1")
"

DO (post-divider LSB)
"

D1 (post-divider MSB)
"

STOPI bit (must be "1")
"

STOP2 bit (must be "1")

"

FS3
0
1
0

1
0
1
0
1
0
1
0

1
0

1
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

II

ICS2595
Observe that the internal shift register is "clocked" by a transition of FS3 data from "0" to "I." If an extended sequence of
register loading is to be performed (such as a power-on initialization sequence), note that it is not necessary to implement the
50 millisecond delay between them. Simply repeat the sequence above as many times as desired. Writes to the FS port
will not be treated as frequency select data until up to 50
milliseconds have transpired since the last write. Note that FSO
and FSI inputs are "don't care."

Feedback Set Bits (NO-N7)

These bits control the feedback divider setting for the location
specified. The modulus of the feedback divider will be equal
to the value of these bits + 257. The least significant bit (NO)
is sent first.
Post-Divider Set Bits (00-01)

These bits control the post-divider setting for the location
specified according to this table. The least significant bit (DO)
is sent first.

Data Description
Table 2 - Post-Divider Programming

Location Bits (LO-L4)

The first five bits after the start bit control the frequency
location to be re-programmed according to this table. The
rightmost bit (the LSB) of the five shown in each selection of
the table is the first one sent.

D[1-0]
00
01
10
11

Table 1 - Location Bit Programming
L[4-0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011

LOCATION
VCLK Address 0
VCLK Address 1
VCLK Address 2
VCLK Address 3
VCLK Address 4
VCLK Address 5
VCLK Address 6
VCLK Address 7
VCLK Address 8
VCLK Address 9
VCLK Address 10
VCLK Address 11
VCLK Address 12
VCLK Address 13
VCLK Address 14
VCLKAddress 15
MCLK Address 0
MCLK Address 1
MCLK Address 2
MCLK Address 3

POST-DIVIDER

8
4
2
1

ReadlWrite* Control Bit

When set to a "0," the ICS2595 shift register will transfer its
contents to the selected memory register at the completion of
the programming sequence outlined above.
When this bit is a "1," the selected memory location will be
transferred to the shift register to permit a subsequent readback
of data. No modification of device memory will be performed.
To readback any location of memory, perform a "dummy"
write of data (complete with start and stop bits) to that location
but set the RIW* control bit (make it "1"). At the end of the
sequence (i.e. after the stop bits have been "clocked"), "clocking" of the FS3 input 11 more times will output the data bits
only in the same sequence as above on the FSO pin.
EXTFREQ Input

The EXTFREQ input allows an externally generated frequency to be routed to the VCLK or MCLK output pins under
device programming controL If the EXTFREQ bit is set (logic
"1") at the selected address location, the frequency applied to
the EXTFREQ input will be routed to the output instead of
the frequency generated by the VCLK (or MCLK) PLL.
When setting the EXTFREQ bit to a "1," be sure that the DO
and D 1 bits are not both set to "1" also, unless it is intended
that the phase-locked loop be shutdown as well.

B-40

II

ICS2595

Power Conservation

Programming Example

The ICS2595 supports power conservation by permitting
either or both of the phase-locked loops to be disabled. This
can be done by programming a particular address to have
EXTFREQ, DO, & Dl bits set to a logic "1." Any frequency
applied to the EXTFREQ pin will still be passed through the
output multiplexer and appear at the respective output.The
crystal oscillator is not affected by this power-down function
and will continue to operate normally.

Frequency Synthesizer Description

Suppose that we want differential CLK output to be 45.723 MHz.
We will assume the reference frequency to be 14.31818 MHz.
The VCO frequency range will be 85.565 MHz to 170.486
MHz (5.976 * 14.31818 to 11.906 * 14.31818). We will need
to set the post-divider to two to get an output of 45.723 MHz.
The VCO will then need to be programmed to two times 45.723
MHz, or 91.446 MHz. To calculate the required feedback
divider modulus we divide the VCO frequency by the reference
frequency and mUltiply by the reference divider:

Refer to Figure 1 for a block diagram of the ICS2595.

91.446 *43 27462
= .
14.31818

The ICS2595 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL. The phase-frequency detector shown in the
block diagram drives the VCO to a frequency that will cause
the two inputs to the phase-frequency detector to be matched
in frequency and phase. This occurs when:

FvCO=FxTALl

which we round off to 275. The exact output frequency will be:

W*14.31818* ~

The value of the N programming bits may be calculated by
subtracting 257 from the desired feedback divider modulus.
Thus, the N value will be set to 18 (275-257) or 000100102.
The D bit programming is 102 (from Table 2).

* ~

where N is the effective modulus of the feedback divider chain
and R is the modulus of the reference divider chain.

Reference Oscillator & Crystal
Selection

The feedback divider on the ICS2595 may be set to any integer
value from 257 to 512. This is done by the setting of the NO-N7
bits. The standard reference divider on the ICS2595 is fixed to
a value of 43 (this may be set to a different value via ROM
programming; contact factory). The ICS2595 is equipped with
a post-divider and multiplexer that allows the output frequency
range to be scaled down from that of the VCO by a factor of 2,
4,or8.
Therefore, the YCQ frequency range will be from 5.976 to
11.906 (257/43 to 512143) of the reference frequency. The
QlltpJ.J1 frequency range will be from 0.747 to 11.906 times the
reference frequency. Worst case accuracy for any desired frequency within that range will be 0.2%.

If a 14.31818 MHz reference is used, the output frequency
range would be from 10.697 MHz to 170.486 MHz (but the
upper end is first limited to 145 MHz by the ICS2595 output
driver).

=45.784 MHz

The ICS2595 has on-board circuitry to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in parallelresonant (also called anti-resonant mode). See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.
Crystals characterized for their series-resonant frequency may
also be used with the ICS2595. Be aware that the oscillation
frequency in circuit will be slightly higher than the frequency
that is stamped on the can (typically 0.025-0.05%).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS2595 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.

8·41

II

ICS2595
External Reference Sources
An external frequency source may be used as the reference for
the VCLK and MCLK PLLs. To implement this, simply connect the reference frequency source to the XTALI pin of the
ICS2595. For best results, insure that the clock edges are as
clean and fast as possible and that the input voltage thresholds
are not violated.

Power Supply
The ICS2595 has three VSS pins to reduce the effects of
package inductance. All pins are connected to the same potential on the die (the ground bus). ALL of these pins should
connect to the ground plane of the video board as close to the
package as is possible.
The ICS2595 has two VDD pins which supply of +5 volt
power to the output stages. These pins should be connected to
the power plane (or bus) using standard high-frequency decoupiing practice. That is, use low-capacitors should have low
series inductance and be mounted close to the ICS2595.
The VAA pin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend that
RC decoupling or zener regulation be provided for this pin (as
shown in the recommended application circuitry). This will
allow the PLL to "track" through power supply fluctuations
without visible effects.

B-42

ICS2595
Absolute Maximum Ratings
Supply voltage .............................. -.5V to +7V
Logic inputs ................................. 5V to VDD +.SV
Ambient operating temp ....................... 0 to 70 a C
Storage temperature .......................... -85 to + 150a C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

DC Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

TTL-Compatible Inputs
(VSO-3, MSO-l, STROBE):

I

Input High Voltage

Vlh

2.0

VDD=0.5

V

Input Low Voltage

VII

VSS-0.5

0.8

V

Input High Current

Ilh

10

uA

Input Low Current

III

200

uA

Input Capacitance

Cn

8

pF

XTAL1:
Input High Voltage

Vxh

VDD*0.75

VDD+0.5

V

Input Low Voltage

Vxl

VSS-0.5

VDD*0.25

V

Voh

2.4

VCLK, MCLK Outputs:
Output High Voltage

V

@Ioh=O.4mA
Output Low Voltage

Vol

0.4

@Iol=8.0mA

B-43

V

II

ICS2595
AC Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

185

MHz

Phase-Locked Loop:
VCLK, MCLK VCO
Frequency

Fvco

PLL Acquire Time

Tlock

60
500

uSee

Crystal Oscillator
Crystal Frequency Range

25

5

Fxtal

Parallel Loading
Capacitance

20

MHz
pf

XTALl Minimum High
Time

Txhi

8

nSec

XTALl Minimum low
Time

Txlo

8

nSec

Power Supplies:
VDD Supply Current

idd

35

rnA

VAA Supply Current

Iaa

10

rnA

VCLK,MCLK,
XTALOUT Rise Time
@Cload=20pf

Tr

2

nSec

VCLK,MCLK,
STALOUT Fall Time
@Cload=20pf

Tf

2

nSec

Digital Outputs:

B·44

II

ICS2595

PAITERN

ICS2595-01

Reference Divider

43

VCLKADDR

FbkDivIPostDiv - FVCLK(MHz)

0

300/1- 99.89

1

378/1 - 125.87

2

277/1 - 92.24

3

43214 - 35.96

4

30212 - 50.28

5

340/2 - 56.61

6

EXTFREQ-

7

270/2 - 44.95

8

405/1 - 134.86

9

384/4 - 31.97

A

33011 - 109.88

B

48112 - 80.08

C

479/4 - 39.87

D

270/2 - 44.95

E

450/2 - 74.92

F

39012 - 64.93

MCLKADDR

FbkDivIPostDiv - FMCLK

0

48114 - 40.04

1

270/2 - 44.95

2

396/4 - 32.97

3

300/2 - 49.95

Ordering Information
ICS2595N-SXX or ICS2595M-SXX (0.300" DIP or sOle Package)
Example:

TTT

ICS XXXX N -SXX
_

T' - - - - S=Strobe Option!XX=Default Frequencies
Package Type
N=D1P (£Jasl1c)
M=SOIC

Device Type (consists of 3 or 4 digit numbers)
PrefIX
ICS, AV=Standard Device; GSP=Genlock DeYlce

Where:
"s" denotes strobe option:
"xx" denotes default frequencies:

A - positive level transparent (i.e., 2494 interface compatible)
B - negative level transparent
C - positive edge triggered
D - negative edge triggered

B-45

8·46

II

ICS82C404

Integrated
Circuit
Systems, Inc.

Advance Information

Dual Programmable Graphics Frequency Generator
Features

General Description

•

The ICS82C404 is a fully programmable graphics clock
generator. It can generate user specified clock frequencies using an externally generated input reference or a
single crystal. The output frequency is programmed by
entering a 24 bit digital word through the serial port.

•
•
•
•
•
•
•
•
•
•
•

Pin for pin and function compatible with lCD's
version of the 82C404
Dual programmable graphics clock generator
Memory and video clocks are individually
programmable on-the-fly
Ideal for designs where multiple or varying
frequencies are required
Increased frequency resolution from optional
pre-divide by 2 on the M counter
Output enable feature available for tri-stating
outputs
Independent clock outputs range from 390 kHz
to 120 MHz
Operation up to 140 MHz available
Power-down capabilities
Low power, high speed 0.8 Jl CMOS technology
Glitch-free transitions
Available in 16 pin PDIP or SOIC package

Two fully user-programmable phase-locked loops are
offered in a single package. One PLL is designed to drive
the memory clock, while the second drives the video
clock. The outputs may be changed on-the-fly to any
desired frequency between 390 kHz and 120 MHz. The
ICS82C404 is ideally suited for any design where multiple or varying frequencies are required.
This part is ideal for graphics applications. It generates
low jitter, high speed pixel clocks. It can be used to
replace multiple, expensive high speed crystal oscillators. The flexibility of the device allows it to generate
non-standard graphics clocks.
The leader in the area of multiple output clocks on a
single chip, ICS has been shipping graphics frequency
generators since October, 1990, and is constantly improving the phase locked loop. The ICS82C404 incorporates a patented fourth generation PLL that offers the
best jitter performance available.

Block Dia ram

,--------------------------

r-------

I
~

~:~---------------------------------------n~

.-==_.....J

/IlRl
T<:o'
To
PDISS

SUDDlv voltal!e relative to GND
Input voltage with respect to GND
Operating temperature
Storage temperature
Max soldering temperature (10 sec)
Junction temperature
Package power dissipation

-0.5
-0.5
0
-65

7.0
VDD+0.5
+70
+150
+260
+125
350

Volts
Volts
°C
°C
°C
°C
mWatts

DC Characteristics
Name
Description
VTU
VIL
Vou
VOL
1m
IlL
Ioz
100
InnTVP
IAOO
Ipn1
IpD2

CIN

High level input voltage
Low level input voltage
High level CMOS ouput voltage
Low level output voltage
Input high current
Input low current
Output leakage current
Power supply current
Power supply current (typical)
Analog power supply current
Power-down current (Mode 1)
Power-down current (Mode 2)
Input capacitance

Min

Typ

Max

2.0
0.8

3.84
0.4
100
-250
10
65

15
35

6
25

8-54

10
7.5
50
10

Units
V
V
V
V
~
~
~

rna
rna
rna
rna
~

pf

Conditions

IoH=-4rna
In,=4rna
Vm = 5.25 V
VIL =OV
(tri-state)
@6OMHz

ICS82C404
AC Characteristics
~vmhnl

fRE!'

Nl'IIm",
Reference

n"'!I;:I'1'1nt1nn
Reference oscillator value

Min
1

Tvn
14.31818

Ml'IIY

Units

60

Mhz

1000

ns

75%
2564
(390 MHz)

ns

(nn..,1\

t"""
~
~

ta
t4
ts
t.

t.,.-:
tA

~meout

t8

t6

tj

ts
~

tID
~1

J"'~I"

t.:n

tun
t1dcmd

Reference period 1/f"""
16.6
Input duty cycle Duty cycle for the input oscillator
25%
defined as t,/tR""
putputctock
Output oscillator values
8.33
(120 MHz
loeriods
Output duty
Duty cycle for the output
oscillators (note 2)
45%
Icycle
Rise times
Rise time for the output oscillators
into a 25 of load
Fall times
Fall time for the output oscillator
into a 25 of load
Old L_
fn>nl outnut
'outnut
Ifreci2 outout
New freauencv outout
Time clock output remains high whil
fREF mux time
0.5 tREF
output muxes to reference frequency
Timeout internal Interval for serial programming and for VCO changes to
settle (note 3)
2
Time clock ouput remains high
tfreq2 muxtime
while output muxes to new
05 tRE!'
freauencv value
Tri-state
Time for the ouput oscillators to go
into trl-state mode after OUTDIS signal assertion
0
CLKvalid
Time for the output oscillators to
recover from trl-state mode after
OUTDIS -silmal Iroes hil!'h
0
Power-Down
Time for power-down mode of
oneratinn to take effect
Power-Up
Time for recovery from power-down
mode of ooeration
MCLKOUT
Time for MCLK to go high
after PWRDWN is asserted hil!h
0
hicll
MCLKOUT
Delay of MCLK prior to fMo,K
delay
signal at output
o5t....rr "
Clock period of serial clock
2· t"""
Setup time
20
Hold time
10
Load command
0

55%

5

1. For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally.
2. Duty cycle is measured at CMOS threshold levels. At 5 vollS, Vrn 2.5 vollS).
3. If the interval is too short, see the timeout interval section in the control register definition.

B-55

ns

3

ns

I.StREF

ns

10

ns

1.5tREF

NOTES

=

3

ns

12

ns

12

n~

12

ns

12

ns

tPWRDWN

ns

15 tMrT.K
2

msec

t 1+3O

ns
ns
ns

ns

ICS82C404

-

tREF

~

t1

\
XTALIN

I

I

fREF

~g~~ __t4_jl""';;·90-%--:C-~·
10%

10%

ffi

T~ 1----

Rise and Fall Times

auTO IS·

VCLK
MCLK

tri-stated out

ut

Tri-Stated Timing

8·56

II

ICS82C404

SELa
SEL1

VCO Settle time

Selection Recognition Time

I
I
I

New Frequency State

~imeout
Internal
Timeout
I

I

VCLK

W
~req1

~
tA

~
~I- : ·1- ~ I
I~req2
I

tREF

ts

Selection Timing

I
I
I

VCO Settle time

Stop

New Frequency State

Sit

(Internal
Timeout)

---------+--,,-1"

VCLK
MCLK

H

~req1

I

H ItA

tREF

~I- ; ~ 1 W
ts

tfreq2

Or t MCLK if bit set
in Control Register

MClK & Active VClK Register Programming Timing

B-57

ICS82C404

IPD---,
This is when VClK directiy
muxes to VClK PLl
/ ( m ay glitch)
~------------------------TI

forced high

VCLK
fVClK

MCLK

fpWRDWN
(value from PWRDWN register)
1)It takes 2-10 msec after soft
power-down to guarantee lock
of VClK & MCLK Plls

Soft Power-Down Timing (Mode 2)

t

1

Start Bit

Unlock Sequence

2 1IIserclk'3

1

41

ClK

DATA
I

I

Valid Data Sequence (24 bits)
ClK

DATA

Serial Programming Timing

B-58

I

Stop Bit I

ICS82C404
ORDERING INFORMATION
Part Number
ICS82C404-xxCWI6
ICS82C404-xxCNI6

Temperature Range
O'C to +70'C
O'C to +70'C

Package Type
16 lead Plastic SOIC
16 lead Plastic DIP

B·59

B-60

ICS90C61A

Integrated
Circuit
Systems, Inc.

•

Dual Video/Memory Clock Generator
Introduction

Features

The Integrated Circuit Systems ICS90C61A is a dual clock
generator for VGA applications. It simultaneously generates
two clocks. One clock is for the video memory, and the other
is the video dot clock.

•

This data sheet supplies sales order information, a functional
overview, signal pin details, a block diagram, AC/DC characteristics, timing diagrams, and package mechanical information.

•

•
•
•

•

•

Description

•

The Integrated Circuit Systems Video Graphics Array Clock
Generator (ICS90C61A) is capable of producing different
output frequencies under firmware control. The video output
frequency is derived from a 14.318 MHz system clock available in IBM PCIXT/AT and Personal Systeml2 computers. It
is designed to work with Western Digital Imaging Video
Graphics Array and 8514/A devices to optimize video subsystem performance.

Dual Clock generator for the IBM-compatible Western
Digital Imaging Video Graphics Array (VGA) LSI devices, and 85141A chip sets
Integral loop filter components
Generates seven video clock frequencies derived from a
14.318 MHz system clock reference frequency
Video clock which is selectable among the seven internally generated clocks and two external clocks
On-chip generation of four memory clock frequencies
CMOS technology
Available in 20-pin PLCC, SOlC, and DIP packages
Extended frequency capabilities to 80 MHz in custom
frequency patterns

Pin Configuration

•
•
•
•

SELO
SELl
VGATTL
FCLKSEL

~

S ""

'"

...,

SELO

4

SELl

5

The ICS90C61A is capable of extended frequency output up
to 80 MHz in custom applications. See page 5 for details.

!90C61ARevAl00494

B-61

N

~

u
u
>
co

'"

..J

()

>

0

'"
ICS90C61AV

18

VCLKE

17

N.C

16

AGND

SELEN

6

VGATTL

7

15

AVCC

FCLKSEL

8

14

MCLKE

0>

0

..J

w

Ul

"

The input and truth table have been designed to allow a direct
connection to one of the many Western Digital Imaging VGA
controllers or 85141A chip sets.

The VCLKE and MCLKE input can tristate the VCLK and
MCLK outputs to facilitate board level testing.

'" bu
..J

U

SELO and SELl are latched by the SELEN signal. VGATTL
and FCLKSEL are used as direct inputs to the VCLK selection.
Table 1-1 is the truth table for VCLK selection.

The MCLK output is one of four internally-generated frequencies as shown in Table 1-2. The various VCLK and MCLK
frequencies are derived from the 14.318 MHz input frequency.

'"

~

OJ

The video dot clock output may be one of seven internallygenerated frequencies or two external inputs. The selection of
the video dot clock frequency is done through four inputs.

REFCLCK
FCLKIN
EXTCLK
SELO
SELl
SELEN
VGATTL
FCLKSEL

D

~

~

~

0
Z
lJ
0

..J

w

if)

:>

~

::'

OJ

0

U

:>

i

DVCC
VCLK
VCLKE
N.C.
AGND
AVCC
MCLKE
N.C.
MCLK

ICS90C61A
ICS90C61 A VGA Interface
The ICS90C61A has two system interfaces: System Bus and
VGA Controller, and six user-programmable inputs. Figure
2-1 shows how the Integrated Circuit Systems VGA Clock
ICS90C61A is connected to a VGA controller. Western Digital Imaging VGA controllers normally have a status bit that

vcca

indicates to the VGA controller that it is working with a clock
chip. When working with a clock chip the VGA controller
changes two of its clock inputs, VCLKI and VCLK2, to
outputs. These outputs are used to select the required video
frequency.

10
/\'V

R1

lC1

dJ;2

}2~F I1~F

asc

I
DVCC

AVCC

~=

FCLKIN
EXTCLK
MSELO
MSEL1

DGND
AGND

~=

VCLKE
MCLKE

f-J-

FCLKSEL

I

asc

-=
CLK
D2
D3
r--

Fl

MCLK r-VCLK

ICS90C61A
REFCLK
SEL1
SELO
VGATTL

S B
Y U
S S
T
E
M

~

L--

'----

VCLK1
VCLK2
D2
D3

VCLKO
MCLK

-

VGA

Figure 2-1 ICS90C61 A Interface
Note:
C2 should be placed as close as possible to the ICS90C61A AVCC pin.

B·62

II

ICS90C61A

System Bus Inputs

Analog Filters

The system bus inputs are:

The analog filters are integral to the ICS90C61A device. No
external components are required. This feature reduces PC
board space requirements and component costs. Phase jitter is
reduced as externally-generated noise cannot easily influence
the phase-locked loop filter.

•
•
•

REFCLK
SELO
SELl

The ICS90C61A uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clocks. Data lines D2 and D3 are commonly used as
inputs to VSELO and VSELl for video frequency selection.

User-Definable Inputs
The user-definable inputs are:
•
•
•
•
•

Inputs from VGA Controller
The VGA controller input to the ICS90C61A is:
•

EXTCLK
FCLKIN
VLCKE, MCLKE
MSELO-l
VGATTL, FCLKSEL

SELEN

The ICS90C61A is programmed to generate different video
clock frequencies using the inputs of SELO, SELl, VGA TTL,
and FCLKSEL. The signals VGATTL and FCLKSEL may be
supplied by the VGA controller as is the case in Western
Digital Imaging VGA controllers. The inputs SELO-l are
latched with the signal SELEN. The SELEN input should be
an active low pulse. This active low pulse is generated in
Western Digital Imaging VGA controllers during-Va writes to
internal register 3C2h.

EXTCLK and FCLKIN are additional inputs that may be
internally routed to the VCLK output. The additional inputs
are useful for supporting modes that require frequencies not
provided by the ICS90C61A.
VCLKE and MCLKE are the output enable signals for VCLK
and MCLK.When low, the respective output is tristated.
MSELO-l are the memory clock (MCLK) select lines. Table
1-2 shows how MCLK frequencies are selected. All signals in
this group have internal pull-up resistors.

Note: Only SELO and SELl are latched with signal SELEN.
VGA TTL and FCLKSEL are video clock (VCLK) select lines
that can select additional VCLK frequencies. See Table 1-1.

Outputs to VGA Controller
The outputs from the ICS90C61A to the VGA controller are:
•
•

MCLK
VCLK

MCLK and VCLK are the two clock outputs to the VGA
controller.

8-63

ICS90C61A
Power Considerations
The ICS90C61A product requires an A Vcc supply free of fast
rise time transients. This requirement may be met in several
ways and is highly dependent on the characteristics of the host
system. A VGA adapter card is unique in that it must function
in an unknown environment. +5 Volt power quality is dependent not only on the quality of the power supply resident in the
host system. but also on the other cards plugged into the host's
backplane. Power supply noise ranges from fair to terrible. As
the VGA adapter manufacturer has no control over this, he
must assume the worst. The best solution is to create a clean
+5 Volts by deriving it from the +12 Volt supply by using a
zener diode and dropping resister. A 470 Ohm resistor and 4.7
Volt Zener diode are the least costly way to accomplish this.
A .047 to .1 microfarad bypass capacitor tied from AVec to
AGND insures good high-frequency decoupling of this point.
Laptop and notebook computers have entirely different problems with power. Typically they have no +12 Volt supply;
however, they are much quieter electrically. Because the designer has complete control of the system architecture, he can
place sensitive components and systems such as the RAMDAC
and Dual Video/Memory Clock away from DRAM and other
noise-generating components. Most systems provide power
that is clean enough to allow for jitter-free Dual Video/Memory Clock performance if the +5 Volt supply is decoupled with
a resistor and 22 microfarad Tantalum capacitor. Digital inputs
that are desired to be held at static logical high level should not
be tied to +5 Volts as this will result in excessive current drain
through the ESD protection diode. The internal pull-up resistors will adequately keep these inputs high.

+5V
DVCC
470
+12V

o-----~~--~---.--~AVCC

R1

D1

C1

-=4.7V I1UF

10
+5V

R1

C2

C3

AVCC

DVCC

!2UF lUF

18
+5V

AVCC

R1
1·1UF

!2UF 11UF
DGND

B-64

DVCC

AGND

II

ICS90C61A
Table 1-1 VCLK SELECTION
VCLK FREQUENCY (MHz)
VGAITL

SELO

SELl

ICS90C6IA-PR2**

I
I
I
I

0
0
0
0

0
0
I
I

0
I
0
I

REFCLK
16.108
32.216
44.744

I
I
I
I

I
I
I
I

0
0
I
I

0
1
0
I

25.057
28.089
EXTCLK*
36.242

0

X

X

X

FCLKIN*

FCLKSEL
---"

Table 1-2 MCLK SELECTION
MCLK FR.E~QUENCIES (MHz)
MSELl

MSELO

ICS90C6IA-PR2**

0
0
I
I

0
I
0
1

41.612
37.585
36.242
44.744

*Note: FCLKIN and EXTCLK may be programmed to output custom frequencies up to 80 MHz in applications which require
this capability. Custom frequencies in these addresses require a significant volume committment and/or one-time mask charge.
Contact ICS Sales for details.
**Note: If no "dash number" is specified, then the "-PR2" will be supplied since this version is completely compatible with
the original WD90C6I frequency set.

B-65

ICS90C61A

EXTCLK
FCLKIN

~

REFCLK
SELEN

SELO
SEll
VGATTL
FCLKSEL
VCLKE

PLL
lJIVIDER

I

MUX

r----t(

I

I

I
I
I

PLL
lJIVIDER
MSELO
MSELl

I

L.-

I

MCLKE

Figure 2-2

VCLK

ICS90C61 A Functional Block Diagram

B·66

MCLK

ICS90C61A
Pin Descriptions
The following table provides the pin descriptions for the 20-pin ICS90C61A packages:

PIN
NUMBER

PIN
SYMBOL

!I

TYPE

I

IN

Reference input clock from system

IN

Feature clock input pin

1

REFCLK

2

FCLKIN

3

EXTCLK

4

SELO

5

SELl

6
7
I

I

!

I

IN

External clock input for an additional frequency

IN

Control input for VCLK selection

IN

Control input for VCLK selection

SELEN

IN

Strobe for latching VSEL(O,I) (Low enable)

VGATTL

IN

Control input for VCLK selection

8

FCLKSEL

9

MSELO

!

I
I

IN

Control input for FCLK selection

IN

Select input for MCLK selection

I
I

10

DGND

-

I

11

MSELl

IN

12

MCLK

OUT

13

N.C.

-

14

MCLKE

IN

r
I

DESCRIPTION

I

Ground for Digital Circuit
I Select input for MCLK selection

I

Memory Clock Output
No Connection
Enable input for MCLK output (hiRh enables output)

15

AVCC

-

Power supply for analog circuit

16

AGND

-

Ground for analog circuit

17

N.C.

-

18

VCLKE

IN

19

VCLK

OUT

20

DVCC

i

-

No Connection
Enable input for VCLK output (hiRh enables output)
Video Clock Output
Power supply for Digital Circuit

NOTE:
CLK1, EXTCLK, FCLKIN, SELO, SELl,VGATTL, FCLKSEL, SELEN, MSELO, MSELl, VCLKE, and MCLKE - input pins
have internal pull-up resistors.

B-67

ICS90C61A
Standard Test Conditions

Absolute Maximum Ratings
Ambient temperature
under bias

The characteristics below apply for the following standard test
conditions, unless otherwise noted. All voltages are referenced
to V ss (OV Ground). Positive current flows into the referenced
pin.

o °c to 70 °c

Storage temperature

_40°C to 125 °c

Voltage on all inputs
and outputs with
respect to Vss

0.5 to 7 Volts

Note: Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.

Operating temperature
range

o°c to 70°C

Power supply voltage

4.75 to 5.25 Volts

DC Characteristics
PARAMETER
~Q~~Input Low Voltage
VIL

VIH

Input High Voltage

MIN

MAX

UNITS

Vss

0.8

V

Vee = 5V

SELO-I, SELEN,
VGATTL,
MSELO-l,
FCLKSEL,
VCLKE,
MCLKE,
EXTCLK

2.0

Vee

V

Vee=5V

SELO-l, SELEN,
VGATTL,
MSELO-l,
FCLKSEL,
VCLKE,
MCLKE,
EXTCLK

CONDITIONS

PINS

VIL

Input Low Voltage

Vss

1.5

V

Vee = 5V

FCLKIN

VIH

Input High Voltage

Vee-1.5

Vee

V

Vee = 5V

FCLKIN

1m

Input Leakage Current

-

20

uA

Vin = Vee

VOL

Output Low Voltage

-

0.4

V

IOL-6.0mA

VOH

Output High Voltage

2.4

-

V

IOH=4.0mA

IceD

Digital Supply Current

-

35

rnA

Vee = 5V, CL = 15pF

IceA
Rup

Analog Supply Current

-

10

rnA

Vee = 5V

25

-

Fe= 1 MHz
Fe=IMHz

Internal pull-up Resistors

Cn

Input Pin Capacitance

-

8

Kohms
pF

Cout

Output Pin Capacitance

-

12

pF

B-68

Vee - 5V

II

ICS90C61A

AC Timing Characteristics
The following notes apply to all of the parameters presented in this section.
I. REFCLK= 14.318 MHz

2.
3.
4.
5.
6.
7.

Te = lIFe
All units are in nanoseconds (ns).
Maximum jitter is within a range of 30 f.l s after triggering on a 400 MHz scope.
Rise and fall time between 0.8 and 2.0 VDC.
Output pin loading = 15pF
Duty cycle is measured at I.4V

SYMBOL

MIN

PARAMETER

MAX

NOTES

SELEN TIMING
Tpwen
Tsuen
Thden

Enable Pulse Width
Setup Time Data to Enable
Hold Time Data to Enable

20
20
10

-

-

REFERENCE INPUT CLOCK
Tr
Tf

Rise Time
Fall Time

Tr
Tf

Rise Time
Fall Time

-

Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency
Output Enable to Tristate
(into and out of) time

10
10

Phase-Jitter I ns max.
Duty Cycle 42.5% min.
to 57.5% max.

-

3
3

-

1.0
80
20

Phase-Jitter 3 ns max.
Duty Cycle 40%min. to
60% max.
%
MHz
ns

IS

ns

-

MCLK and VCLK TIMINGS

-

-

B-69

II

ICS90C61A
ENABLE TIMING
SELO
SEL 1

>--

--<

SELEN

I
tpwen

l

thden

I
tsuen

CLOCK WAVEFORM
tc= 1Ifc
tf

2.0V
O,BV

Ordering Information
ICS90C61A-XXXN or ICS90C61A-XXXM or ICS90C61A-XXXV
Example:

ICS XXXX-XXX N

I T

-'g.N=DlP (PlastIc)

V=PLCC

M=SOIC

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Note' Unless a specific pattern is ordered, PR2 will be shipped.

" - - - - - - - - Device Type (consists of 3·6 digit numbers)
" - - - - - - - - - - Prefix

rcs, AV=Standard Device; GSP=Genlock DeVice

B·70

ICS90C64A

Integrated
Circuit
Systems, Inc.

•

Dual Video/Memory Clock Generator
Introduction

Features

The Integrated Circuit Systems ICS90C64A is a dual clock
generator for VGA applications. It simultaneously generates
two clocks. One clock is for the video memory, and the other
is the video dot clock.

•
•
•

This data sheet supplies sales order information, a functional
overview, signal pin details, a block diagram, ACIDC characteristics, timing diagrams, and package mechanical information.

•
•

Description

•
•

The Integrated Circuit Systems Video Graphics Array Clock
Generator (ICS90C64A) is capable of producing different
output frequencies under firmware control. The video output
frequency is derived from a 14.318 MHz system clock available in mM PCIXT/AT and Personal Systeml2 computers. It
is designed to work with Western Digital Imaging Video
Graphics Array and 85141A devices to optimize video subsystem performance.

•
•

VSEL1

" '"IJj
.., '"
'"
4-

18

VCLKE

VSELD

5

17

N.C.

SELEN

6

ICS90C64A 16

AGND

VSE1.2

7

15

AVCC

VSE1.3

8

14

MCLKE

...J

~
~

The video dot clock output may be one of fifteen internallygenerated frequencies or one external input. The selection of
the video dot clock frequency is done through four inputs.
•
•
•
•

Improved compatibility with Western Digital Controllers
100% backward compatible with ICS90C63 and
ICS9OC64
Dual Clock generator for the mM compatible Western
Digital Imaging Video Graphics Array (VGA) LSI devices,
and 85141A chip sets
Integrailoop fIlter components. Reduce cost and phase-jitter
Generates 15 video clock frequencies (including 25.175
and 28.322 MHz) derived from a 14.318 MHz system clock
reference frequency
On-chip generation of eight memory clock frequencies.
Video clock is selectable among the fifteen internally generated clocks and one external clock
CMOS technology
Available in 20-pin PLCC, SOIC, and DIP packages

VSELO
VSELI
VSEL2
VSEL3

'"

9

VSELO and VSELI are latched by the SELEN signal. VSEL2
and VSEL3 are used as direct inputs to the VCLK selection.
Table I-I is the truth table for VCLK selection.

Iij
::s

The input and truth table have been designed to allow a direct
connection to one of the many Western Digital Imaging VGA
controllers or 85141A chip sets.

CLKI
MSE1.2
EXTCU<
VSELI
VSELO
SELEN
VSEL2
VSELJ
MSELO
DCND

The MCLK output is one of eight internally-generated frequencies as shown in Table 1-2. The various VCLK and
MCLK frequencies are derived from the 14.318 MHz Input
frequency.

[
[
[
[
[

...J

:=

0
0

~

'">
1; d

~

:

~

~

~

..,'"'" "' ~
'" '"

4z

;:
~

III

0

DVCC
VCLK
VCLKE
N,C.
ACNe
AVCC
[
MCLK E
[
N,C.
[
MCU<
["'-_ _ _-'" MSEL1

[ICS90C64A

20-Pin PLCC, SOIC,DIP
The VCLKE and MCLKE input can tristate the VCLK and
MCLK outputs to facilitate board level testing.

K-10, K-7, K-4
Note:ICS90C64AN (DIP) pmout IS Identical to ICS9OC64AM (SOIC) pmout.

19OC64-ARevA100494

B·71

ICS90C64A
ICS90C64A VGA Interface
The ICS90C64A has two system interfaces: System Bus and
VGA Controller, as well as analog filters and seven user
programmable inputs. Figure 2-1 shows how the Integrated
Circuit Systems VGA Clock ICS90C64A is connected to a
VGA controller. Western Digital Imaging VGA controllers

vee

normally have a status bit that indicates to the VGA controller
that it is working with a clock chip. When working with a clock
chip the VGA controller changes two of its clock inputs,
VCLKI and VCLK2, to outputs. These outputs are used to
select the required video frequency.

10

"v

~l

Rl

!2UF

lf~

fur

I

DVDD
DSC

AVDD

EXTClK

I

~=
J_

MSElO
MSELl
MSEl2

~=

VCLKE
MClKE

~5t~ -

-"- VSEl3

-===-

ICS90C64A
ClK!
VSElO

ClK
D2
D3

VSELl

r-

VSEL2
SELEN

2::
W
lV) V)

>-:::::J
v)r:r:l

'--

'---L--

VCLKI
VCLK2
D2

D3

VClKO r-MClK

VGA
Figure 2-1

ICS90C64A Interface

Note:
C2 should be placed as close as possible to the ICS90C64A AVDD pin.

B-72

r--

II

ICS90C64A

System Bus Inputs

Analog Filters

The system bus inputs are:

The analog filters are integral to the ICS90C64A device. No
external components are required. This feature reduces PC
board space requirements and component costs. Phase-jitter is
reduced as externally-generated noise cannot easily influence
the phase-locked loop filter.

•
•
•

CLKI
VSELO
VSELl

The ICS90C64A uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clocks. Data lines D2 and D3 are commonly used as
inputs to VSELO and VSELl for video frequency selection.

User-Definable Inputs
The user-definable inputs are:
•
•
•
•

Inputs from VGA Controller

EXTCLK
VLCKE, MCLKE
MSELO-2
VSEL2, VSEL3

The VGA controller input to the ICS90C64A is:
•

SELEN

The ICS90C64A is programmed to generate different video
clock frequencies using the inputs of VSELO, VSEL I, VSEL2,
and VSEL3. The signals VSEL2 and VSEL3 may be supplied
by the VGA controller as is the case in Western Digital
Imaging VGA controllers. The inputs VSELO-I are latched
with the signal SELEN. The SELEN input should be an active
low pulse. This active low pulse is generated in Western Digital
Imaging VGA controllers during VO writes to internal register
3C2h.
Note: Only VSELO and VSELl are latched with signal SELEN.

EXTCLK is an additional input that may be internally routed
to the VCLK output. This additional input is useful for supporting modes that require frequencies not provided by the
ICS90C64A.
VCLKE and MCLKE are the output enable signals for VCLK
and MCLK. When low, the respective output is tristated.
MSELO-2 are the memory clock (MCLK) select lines. Table
1-2 shows how MCLK frequencies are selected. All signals in
this group have internal pull-up resistors.
VSEL2 and VSEL3 are video clock (VCLK) select lines that
can select additional VCLK frequencies. See Table I-I.
VSEL2 and VSEL3 have internal pull-ups.

Outputs to VGA Controller
The outputs from the ICS90C64A to the VGA controller are:
•
•

MCLK
VCLK

MCLK and VCLK are the two clock outputs to the VGA
controller.

B-73

ICS90C64A
+5V

Power Considerations

o-------------~~C~1----------'

DVDD

The ICS90C64A product requires an A VDD supply free offast
rise time transients. This requirement may be met in several
ways and is highly dependent on the characteristics of the host
system. A VGA adapter card is unique in that it must function
in an unknown environment. +5 Volt power quality is dependent not only on the quality of the power supply resident in the
host system, but also on the other cards plugged into the host's
backplane. Power supply noise ranges from fair to terrible. As
the VGA adapter manufacturer has no control over this, he
must assume the worst. The best solution is to create a clean
+5 Volts by deriving it from the +12 Volt supply by using a
zener diode and dropping resistor. A 470 Ohm resistor and 5.1
Volt Zener diode are the least costly way to accomplish this.
A .047 to .1 microfarad bypass capacitor tied from AVDD to
AV ss insures good high-frequency decoupling of this point.
Laptop and notebook computers have entirely different problems with power. Typically they have no +12 Volt supply;
however, they are much quieter electrically. Because the designer has complete control of the system architecture, he can
place sensitive components and systems such as the RAMDAC
and Dual VideolMemory Clock away from DRAM and other
noise-generating components. Most systems provide power
that is clean enough to allow for jitter- free Dual VideolMemory Clock performance if the +5 Volt supply is decoupled with
a resistor and 22 microfarad Tantalum capacitor. Digital inputs
that are desired to be held at a static logical high level should
not be tied to +5 Volts as this will result in excessive current
drain through the ESD protection diode. The internal pull-up
resistors will adequately keep these inputs high.

11!lF

470
+12V o------,NV~R-1--D-1"""c-2
---i AVDD

AVSS
4.71· 1!lF

+5V

10

DVDD

DVDD

B-74

ICS90C64A
Table 1-1 VCLK Selection
I

VCLK Frequency (MHz)
1

0

ICS90C64A

ICS90C64A-903

ICS90C64A-907

0
0
1
1

0
1
0
1

30.0
77.25
EXTCLK
80.0

30.0
77.25
EXTCLK
80.0

30.250
77.25
EXTCLK
80.0

1
1
1

0
0
1
1

0
1
0
1

31.5
36.0
75.0
50.0

31.5
36.0
75.0
50.0

31.5
35.5
75.0
72.0

31.5
36.0
75.0
50.0

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0

1

40.0
50.0
32.0
44.9

40.0
50.0
32.0
44.9

40.0
50.0
32.0
44.9

1
1

1
1
1
1

0
0
1
1

0
1
0
1

25.175
28.322
65.0
36.0

25.175
28.322
65.0
36.0

25.175
28.322
65.0
36.0

3

2

0
0
0
0

0
0
0
0

0
0
0
0

1

1
1

I

iI

!

i

I

I

I

I

I
i

40.0
50.0
32.0
44.9

I

i

Ii

25.175
28.322
65.0
36.0

ICS90C64A-909

I

30.0
77.25
EXTCLK
80.0

Table 1-2 MCLK Selection
MCLK Frequencies (MHz)

I:
II

2

1

0

ICS90C64A

ICS90C64A-903

ICS90C64A-907

ICS90C64A-909

0
0
0
0

0
0
1
1

0
I
0
1

33.0
49.218
60.0
30.5

33.0
49.218
60.0
30.5

65.0
49.218
60.0
62.5

75.0
40.0
45.0
50.0

0
0
1
1

0
1
0
1

41.612
37.5
36.0
44.296

41.612
37.5
55.0
44.296

55.0
60.0
65.0
70.0

LL

I
I

I

I

I

41.612
37.5
36.0
44.296

i

I

B-75

I

I

I
!

II

ICS90C64A

EXTCLK
CLKl
SELEN

r

MUX

PLL
DlVIDER

'--

VCAP

I

VSELO
VSELl
VSEL2
VSEL3
VCLKE

I

MSELO
MSELl
MSEL2
MCLKE

Figure 2-2

VCLK

I

I

PLL
DlVIDER

MCAP

------t?

I

~

I

ICS90C64A Functional Block Diagram

B·76

MCLK

II

ICS90C64A

Pin Descriptions
The following table provides the pin descriptions for the 20-pin ICS90C64A packages.
PIN
NUMBER

PIN
SYMBOL

TYPE

DESCRIPTION

1

CLKI

IN

Reference input clock from system

2

MSEL2

IN

Select input for MCLK selection
External clock input for an additional frequency_

3

EXTCLK

IN

4

VSELI

IN

Control input for VCLK selection

5

VSELO

IN

Control input for VCLK selection

6

SELEN

IN

Strobe for latching VSEL(O,l) (Low enable)

7

VSEL2

IN

Control input for VCLK selection

8

VSEL3

IN

Control input for VCLK selection
Select input for MCLK selection

9

MSELO

IN

10

DGND

-

11

MSELI

IN

12

MCLK

OUT

13

N.C.

-

14

MCLKE

IN

15

AVDD

-

Power supply for analog circuit

16

AGND

-

Ground for analog circuit
No connection

17

N.C.

-

18

VCLKE

IN

19

VCLK

OUT

20

DVDD

-

Ground for Digital Circuit
Select input for MCLK selection
Memory Clock Output
No connection

,-,

Enable input for MCLK output (hiRh enables output)

Enable input for VCLK output (hi{?h enables output)
Video Clock Output
Power supply for Digital Circuit

Note:
CLKl, EXTCLK, VSELO, VSELI ,VSEL2, VSEL3, SELEN, MSELO, MSELl, MSEL2, VCLKE, and MCLKE - input pins have
internal pull-up resistors.

B-77

II

ICS90C64A
Absolute Maximum Ratings

Standard Test Conditions
The characteristics below apply for the following standard test
conditions, unless otherwise noted. All voltages are referenced
to V ss (OV Ground). Positive current flows into the referenced
pin.

o°C to 70°C

Ambient Temperature
under bias
Storage temperature

-40°C to 125 °C

Voltage on all inputs
and outputs with
re~ect to Vss

0.5 to 7 Volts
Operating Temperature
~~.Power supply voltage
..

o °C to 70°C
--~----------------~I

4.75 to 5.25 Volts

Note: Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.

DC Characteristics
SYMBOL
__ PARAMETER
---

MAX

UNITS

VIL

Input Low Voltage

MIN
Vss

0.8

V

VIH

Input High Voltage

2.0

VDD

V

IIH

Input Leakage Current

-

10

-

0.4

llA
V

-

V

28

rnA

No load
VCLK=28MHz
MCLK=40MHz

35

rnA

No load
VCLK=80MHz
MCLK=40MHz

-

kohms

8

pF

Fe= I MHz

pF

IFc= 1 MHz

----

Vol~

VOL

Output Low

VOH

Output High Voltage

VDD-.4

VOH

Output High Voltage

2.4

Ice

Icc

Supply Current
I

I

Supply Current

1--

I

TYP

-

20

27
I

Rup

Internal Pull-uQ. Resistors

Cm

Input Pin Capacitance

-

Cout

Output Pin Capacitance

-

50

I

12
-

.

8·78

Vin= VDD
IOL= 8.0 rnA
IOH=4.0mA

I
-

CONDITIONS

I

IOH= 8.0 rnA

VDD-5V
I
II

II

ICS90C64A

AC Timing Characteristics
The following notes apply to all of the parameters presented in this section:
1. REFCLK= 14.318 MHz
2. Tc= IlFc
3. All units are in nanoseconds (ns), unless labeled otherwise.
4. Output pin loading = 15pF

PARAMETER

SYMBOL

MIN

TYP

NOTES

MAX

SELEN TIMING
Tpwen
Tsuen
Thden

Enable Pulse Width
Setup Time Data to Enable
Hold Time Data to Enable

Tr
Tf

Rise Time
Fall Time

Tr
Tf
Tr
Tf
ThIgh
Thigh

Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle
Duty Cycle
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency
Output Enable to Tri-State
(into and out of) time

20
20
10
Reference Input Clock
10
10

Phase-Jitter I ns max.
Duty Cycle 42.5% min.
to 57.5% max.

MCLK and VCLK TIMINGS
.9
.9
1.2
1.2

50%
45%

1.5
1.5
2.0
2.0
60%
55%
0.5
135
20
15

.8V-2.0V*
2.0V-.8V
.3 VDD-.7 VDD
.7 VDD-.3 VDD
1.4V Switch Point
VDD/2 Switch Point
%
MHz
ns
ns

* WD90CII VIdeo Controller IS desIgned WIth TfL level Input thresholds on the inputs dnven by the ICS9OC64A VCLK and MCLK outputs.
The later controllers (WD9OC20. WD90C22. WD9OC26. WD90C30. and WD90C31) are deSIgned WIth Input sWItch pOints ofVCCl2 (CMOS)

B-79

II

ICS90C64A
ENABLE TIMING

VSELO
VSEL 1

" '>-

--<

SELEN

I
I
I

tpwen

thden

tsuen

CLOCK WAVEFORM
tc=1/fc
tr

tf

2.av
O.BV

O.8V ' - - - - - - - - - - - - . /

Figure 5-1

ICS90C64A Timing

Ordering Information
ICS90C64A-XXXN or ICS90C64A-XXXM or ICS90C64A-XXXV
Example:

ICS XXXX- XXX N

I T

h""'T~

N=DIP (Plastic)
M=SOIC

V=PLCC

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - Device Type (consists of 3-6 digit numbers)
'---------Prefix
lCS. AV=Standard Device; GSP=Genlock DeVice

B-80

ICS90C65

Integrated

~ Circuit

•

Systems, Inc.

Dual Voltage Video/Memory Clock Generator
Introduction

Features

The Integrated Circuit Systems ICS90C65 is a dual clock
generator for VGA applications. It simultaneously generates
two clocks. One clock is for the video memory. and the other
is the video dot clock.

•

The ICS90C65 has been specifically designed to serve the
portable PC market with operation at either 3.3V or 5V with a
comprehensive power-saving shut-down mode.
This data sheet supplies sales order information. a functional
overview, signal pin details, a block diagram, ACIDC characteristics, timing diagrams, and package mechanical information.

Description
The Integrated Circuit Systems Video Graphics Array Clock
Generator (ICS90C65) is capable of producing different output frequencies under firmware control. The video output
frequency is derived from a 14.318 MHz system clock available in IBM PCIXT/AT and Personal Systeml2 computers. It
is designed to work with Western Digital Imaging Video
Graphics Array and 8514/A devices to optimize video subsystem performance.

•
•
•

•
•

•
•
•
•

,
u

The video dot clock output may be one of 15 internallygenerated frequencies or one external input. The selection of
the video dot clock frequency is done through four inputs.
•
•
•
•

Specified for dual voltage operation (VDD=3.3V or 5V), but
operates continuously from 3.0V to 5.25V
Designed to be powered-down for extended battery life
Backward compatibility to the ICS90C64 and ICS90C63
Dual Clock generator for the IBM-compatible Western
Digital Imaging Video Graphics Array (VGA) LSI devices,
and 85141 A chip sets
Integral loop filter components, reduce cost and phase jitter
Generates fifteen video clock frequencies (including
25.175 and 28.322 MHz) derived from a 14.318 MHz
system clock reference frequency
On-chip generation of eight memory clock frequencies
Video clock is selectable among the 15 internally generated
clocks and one external clock
CMOS technology
Available in 20-pin PLCC, SOIC and DIP packages

VSELO
VSELl
VSEL2
VSEL3

VSEL1

4

VSELO

5

SELEN

6

VSEl2

7

VSEL3

8

CJ

~ §

"

~

The input and truth table have been designed to allow a direct
connection to one of the many Western Digital Imaging VGA
controllers or 8514/A chip sets.

VSELl
VSELO
SElEN
VSEL2

The MCLK output is one of eight internally-generated frequencies as shown in Table 1-2. The various VCLK and
MCLK frequencies are derived from the 14.318 MHz input
frequency.
The VCLKE and MCLKE input can tristate the VCLK and
MCLK outputs to facilitate board level testing.

~

"
~

18

ICS90C65V

~ '"~
eLKI
MSEL2
EXTCLK

>

0

c:

~

VSELO and VSELl are latched by the SELEN signal. VSEL2
and VSEL3 are used as direct inputs to the VCLK selection.
Table 1-1 is the truth table for VCLK selection.

0
0

~

~

w

,

if)

u

0

VCLKE

17

NC

16

AVSS

15

AVDD

14

MCLKE

"

II

DVDD
VCLK
VCLKE

NC

ICS90C65M

AVS5

AVOD
MCLKE

VSEL3

PWRDN

MSELO
DVSS

MCLK
MSEL1

20-Pin PLCC, SOIC,DIP
K-10, K-7, K-4
Note:ICS90C65N (DIP) pmout lS 1dentical to ICS90C65M (SOIC) pmout

190C64AReVA100494

B·81

II

ICS90C65
ICS90C65 VGA Interface
The ICS90C65 has two system interfaces: System Bus and
VGA Controller, as well as other programmable inputs. Figure
J shows how the Integrated Circuit Systems' VGA Clock
ICS90C65 is connected to a VGA controller. Western Digital
Imaging VGA controllers normally have a status bit that indicates to the VGA controller that it is working with a clock chip.
When working with a clock chip the VGA controller changes
two of its clock inputs to outputs. They are
theVCLKINCSLDNCSEL and VCLK2NCSEU VCSELH
outputs and they are used to select the required video frequency.

pull-up at reset
and PR15(5)=O

J

When thejl()wer-down capabilities are used, the control signal
for PWRDN is normally held in one of a group of latches. If
the power-down function is not to be used, PWRDN must be
tied to VDD, otherwise the internal pull-down will place the
chip in the power-down mode.

WD90C26

AMD(3)

lATCH

VCKIN
MClK

VCS

r---

VCS

r-

ICS90C65
~~~

SD2

VSElO

SD3

VSEl1

PWRDN
VClK r - - -

L--.. VSEl2

SElEN
14.318 MHz

MC

ClKI

Figure 1

B-82

r-

ICS90C65
System Bus Inputs

User-Definable Inputs

The system bus inputs are:

The user definable inputs are:

•
•
•

The ICS90C65 uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clocks. Data lines D2 and D3 are commonly used as
inputs to VSELO and VSELI for video frequency selection.

Inputs from VGA Controller
SELEN

The ICS90C65 is programmed to generate different video
clock frequencies using the inputs ofVSELO, VSELl, VSEL2,
and VSEL3. The signals VSEL2 and VSEL3 may be supplied
by the VGA controller as is the case in Western Digital
Imaging VGA controllers. The inputs VSELO-I are latched
with the signal SELEN. The SELEN input should be an active
low pulse. This active low pulse is generated in Western Digital
Imaging VGA controllers during I/O writes to internal register
3C2h.
Note: Only VSELO and VSELI are latched with signal SELEN.

EXTCLK is an additional input that may be internally routed
to the VCLK output. This additional input is useful for supporting modes that require frequencies not provided by the
ICS90C65 or for use during board test.

MSELO-2 are the memory clock (MCLK) select lines. Table
1-2 shows how MCLK frequencies are selected. All signals in
this group have internal pull-up resistors.
VSEL2 and VSEL3 are video clock (VCLK) select lines that
can select additional VCLK frequencies. See Table I-I.
VSEL2 and VSEL3 have internal pull-ups.
PWRDN can place the ICS90C65 in a power-down mode
which drops its supply current requirement below 1 microamp.
When placed in this mode, the digital inputs may be either high
or low or floatingwithout causing an increase in the ICS90C65
supply current.
The PWRDN pin must be low (It has an internal pull-down.)
in order to place the device in its low power state. The output
pins (VCLK and MCLK) are driven high by the ICS90C65
when it is in its low power state.

Outputs to VGA Controller
The outputs from the ICS90C65 to the VGA controller are:
•
•

EXTCLK
VLCKE, MCLKE
MSELO-2
VSEL2, VSEL3
PWRDN

VCLKE and MCLKE are the output enable signals for VCLK
and MCLK. When low the respective output is tristated.

The VGA controller input to the ICS90C65 is:
•

•
•
•
•
•

CLKI
VSELO
VSELI

MCLK
VCLK

MCLK and VCLK are the two clock outputs to the VGA
controller.

Analog Filters
The analog filters are integral to the ICS90C65 device. No
external components are required. This feature reduces PC
board space requirements and component costs. Phase-jitter is
reduced as externally-generated noise cannot easily influence
the phase-locked loop filter.

If CLKI is being driven by an external source, it may be driven
low or high without a power penalty. If CLKI is at an intermediate voltage (Vss+O.5 < VIN -/

SELEN

I
I
I

tpwen

thden

tsuen

CLOCK WAVEFORM
tc=1/fc
tr

tf

2JJV

2.OV

O.8V

O.BV '-----------------'

ICS90C65 Timing

Ordering Information
ICS90C65-XXXN or ICS90C65-XXXM or ICS90C65-XXXV
Example:

ICS XXXX-XXX

N

L=

Package Type
N=DIP ({,lashe)
M=SOIC

V=PLCC

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - Device Type (consists of 3-6 digit numbers)
' - - - - - - - - - - - - Prefix
ICS. AV=Standard Device; GSP=Genlock DevICe

B-88

II

ICS9161 A

Integrated
Circuit
Systems, Inc.

Dual Programmable Graphics Frequency Generator
General Description

Features

The ICS9161 is a fully programmable graphics clock generator. It can generate user-specified clock frequencies using an
externally generated input reference or a single crystal. The
output frequency is programmed by entering a 24-bit digital
word through the serial port. Two fully user-programmable
phase-locked loops are offered in a single package. One PLL
is designed to drive the memory clock, while the second drives
the video clock. The outputs may be changed on-the-fly to any
desired frequency between 390 kHz and 120 MHz. The
ICS9161 is ideally suited for any design where multiple or
varying frequencies are required.

•
•
•

This part is ideal for graphics applications. It generates low
jitter, high speed pixel clocks. It can be used to replace multiple,
expensive high speed crystal oscillators. The flexibility of the
device allows it to generate non-standard graphics clocks.
The ICS9161 is also ideal in disk drives. It can generate zone
clocks for constant density recording schemes. The low profile,
16-pin SOIC or PDIP package and low jitter outputs are
especially attractive in board space critical disk drives.

•
•
•
•
•
•
•
•
•

Pin-for-pin and function compatible with ICD2061A
Dual programmable graphics clock generator
Memory and video clocks are individually programmable
on-the-fly
Ideal for designs where multiple or varying frequencies
are required
Increased frequency resolution from optional pre-divide
by 2 on the M counter
Output enable feature available for tristating outputs
Independent clock outputs range from 390 kHz to
120 MHz
Operation up to 140 MHz available
Power-down capabilities
Low power, high speed 0.8!! CMOS technology
Glitch-free transitions
Available in 16-pin SOIC orPDIP package

The leader in the area of multiple output clocks on a single
chip, ICS has been shipping graphics frequency generators
since October, 1990, and is constantly improving the phaselocked loop. The ICS9161 incorporates a patented fourth generation PLL that offers the best jitter performance available.

Block Diagram
1------

I
I
X1

X2+4~~----------------------------------------------~~

SELO-ClK

VCLK

...:....---+.....~~I

SEL1-DATA ..,....--..........::~~I

IERROUT .,...._ _ _ _ _ _ _ _ _ _---1

:~:~; ..!.I------__-----------,l~

MCLK

I

'-

~I

IICS9161 RevA092794

B-89

ICS9161 A
Pin Configuration
SELO-CLK
SEL1-DATA
VDD
OE
GND
X1
X2
MCLK

IPD

2
3
4
5

Il

F

470

+12V

R1

C2

Dot Clock
Generator
AVDD
VSS,

AVSS

FIGURE A
OPTIMUM DESKTOP POWER CIRCUITRY

10
+5V O----,J\J'V'-;R'<":1,..-1>-:C=<;2::---C><:3;:--! AVDD

DVDD

Dot Clock
Generator

Summary
ICS dot clock generators have revolutionized the personal
computer and workstation graphics function.The capability to
generate virtually any desired frequency at less cost than a
single crystal oscilator has expanded the versatility of today's
graphics systems for the PC beyond where high end workstation performance was a few years ago. Size, PC board real
estate, and power requirements have shrunk to the point where
today's laptop and notebook computers have graphics performance nearly as good as desktop machines. Systems design
of a high-performance graphics system has been simplified so
that with a few design precautions outlined above high-performance graphics can be implemented in any system.

VSS,

AVSS

FIGURE B
LAPTOP/NOTEBOOK COMPUTER POWER CIRCUITS

18

+5V

o-+-~~~~~~~~~AVDD

1·1

R1

1lF

DVDD

Dot Clock
Generator
VSS,

AVSS

FIGUREC
LAPTOP/NOTEBOOK COMPUTER POWER CIRCUITS

B-108

Clock Generators Application Note

Common VGA Board Layout Mistakes

O.

E.

Suggestions for a better layout:
A. Keep loop filter components (where required) close to dot clock generator and away from high speed DRAM circuitry.
B. Keep by-pass capacitor close to AVDD pin.
C. Move XTAL close to pins XTALl and XTAL2. Keep fast logic signals away from this area.
D. Move oscillator can up between RAM and dot clock passive components.

E. Break ground plane level to create unipotential ground connection for dot clock circuitry.

B-109

B·110

AN02

Integrated
Circuit
Systems, Inc.

Clock Generators Application Note

Understanding ICS Data Sheet Jitter Specifications
Jitter, Absolute is the maximum deviation that would be expected (plus or minus) from a mean clock period.

Introduction
ICS clock generator devices utilize frequency synthesis based
on phase locked loop (PLL) technology. Unless carefully
designed, PLL-based clock generators are subject to excessive
period variation, or "jitter." This applications brief will help
in tbe understanding of ICS jitter specifications.
In most processor and time keeping applications, an excess of
clock jitter does not affect operation. However, in other applications such as video, data acquisition or data recovery, clock
jitter characteristics can be an important system design consideration. ICS is tbe most experienced manufacturer of video
and processor clock devices and has perfected PLL based clock
design. ICS produces clock devices exhibiting the lowest jitter
and the least susceptibility to power supply noise.

Understanding ICS Jitter
Specifications
Many of tbe ICS clock generator data sheets list output clock
jitter specifications in the AC Characteristics section. ICS
defines ciockjitter as the difference in time of any given clock
period as compared to the mean clock period, which is defined
as Ilfrequency. This can be expressed as time (psec) or as a
percentage of the clock period.

Jitter, 1 Sigma is similar to an average deviation that would be
expected (plus or minus).from a mean clock period. This
specification assumes that, statistically, a sample of clock cycle
periods follow a normal probability function, which indeed it
typically does. Jitter, 1 Sigma is the jitter value at one standard
deviation (one sigma) of tbe jitter measurement population.
This specification is useful in graphics applications.

How ICS Clock Jitter is Measured
ICS characterizes output clockjitter using a Stanford Research
SR620 Time Interval Analyzer. This instrument is set up to
take 10,000 clock period samples over a several second period,
therefore, random noncontiguous clock periods are sampled.
The measure data provided by the instrument is the typical
value listed in the data sheet (the SR620 provides both 1 Sigma
and Absolute measurements). The maximum value listed is
tbe worst case measurement expected over the output frequency range, changes in operating conditions such as supply
voltage and temperature, and changes in the semiconductor
process.

IClckGenApRevA 100594
B-l11

8-112

II

AN03

Integrated
Circuit
Systems, Inc.

Clock Generators Application Note

Clock Output Frequency Accuracy and Input Reference Topics
This application note addresses output frequency accuracy
of ICS Clock Synthesizers. Output frequency accuracy is
determined both by the programmable set size of the PLL
and input reference frequency accuracy. Input reference
circuits are also discussed, with emphasis on using a
discrete quartz crystal device.

Determining Your Frequency
Accuracy Needs
ICS clock synthesizer devices are used in a diversity of
applicatious all of which have different clock accuracy requirements. For example, in VGA graphics applications, the
pixel clock frequency can easily tolerate an inaccuracy of
0.5% (5,000 ppm or part-per-million) or more since CRT
timing is uncritical. This is also true for the CPU and other
system clocks in motherboard applications, as long as maximum clock rates are not taken too literally. There are,
however, motherboard applications that must have greater
accuracy. Floppy disk drive control chips typically require a
24 MHz reference clock that is accurate to 0.1 % (1,000 ppm).
Modem and SCSI chips typically specify 0.002-0.005% (2050 ppm) accuracy. Clocks used on the motherboard for time
keeping purposes will create a 1 minute-per-month inaccuracy
for every 0.0023 % (23 ppm) deviation from ideal frequency.
Musical instrument synthesis demands highly accurate clocks
since even a small error can produce audible beating with
another instrument.

Clock Synthesizer Multiplication
Ratio Granularity
ICS frequency generator ICs use the common PLL (phaseLocked-Loop) technique for clock generation. Figure 1 shows
a simplified block diagram of a PLL based clock generator
which is applicable to all ICS clock generators. This approach
to clock generation uses an input reference frequency that is
multiplied by an integer ratio to obtain the desired output
frequency. Once the PLL is "in lock" (typically, several
milli-secondsafterpower-up), the output frequency of the chip
is related to the reference frequency exactly by this programmed multiplication ratio.

fiN

(INPUT REFERENCE FREQUENcy)

Figure 1: Simplified Diagram of PLL-Based
Clock Generator Circuit

With improved clock frequency accuracy comes increased
component cost and design complexity. System clock
accuracy requirements should, therefore, be approached
realistically.

Referring to the PLL circuit in Figure 1.

N

JOUT =jIN M·

IAN03Rev030896 I
8-113

ICS Clock Synthesizer App Note

error in the reference frequency will result in a +0.1 %
error in the output frequency (deviation from actual
frequency where applicable).

Thus, a desired output frequency (the target frequency) may
not be hit exactly with a given reference frequency. The
size of the minimum frequency steps will be determined by
the devices N and M range. As an example, in the
AV9107, N can be assigned integer values from 2 to 128
and M from 2 to 32. Using a 14.31818 MHz reference, if
an output frequency of SO MHz is desired, the closest
output frequencies achievable are 49.88 MHz (N/M =
108/31) or SO.11 MHz (N/M = 7/2). In general, the
AV9107 will have an approximate frequency error of
0.25 % due to the programming granularity.

When choosing a reference frequency generator, precision
is associated with cost. The most accurate and costly
reference is a crystsl oscillator module. The more common
and less expensive approach is to use a discrete external
quartz device (most ICS clock chips have built in crystsl
oscillator circuitry).
Any stsble and continuous clock signal (within the specified
frequency range) can be used as a reference clock for ICS
clock chips. Special circuit considerations are advised
when a clock signal, such a system clock or crystsl
oscillator module output, is used to drive an ICS clock
generator that contsins an integrated crystsl oscillator
circuit. Please refer to the device dats sheet or contact ICS
Applications Engineering.

Some of the ICS clock synthesizer dats sheets list both
target and actual frequencies of the device. The target
frequency is the typical value required for the intended
application. For example, for proceasor clock devices,
target frequencies are typically round numbers such as 20,
25, 33.3 or SO MHz relating to the rated CPU speed.
However, because the typical processor clock IC uses a
14.31818 MHz reference frequency/ these exact target
frequencies cannot be obtsined within practical limits of N
and M values. (The reference frequency of 14.31818 MHz
is chosen because it is a common system clock frequency
and quartz crystsls at this frequency are readily available.)
Furthermore, there is no reason for a processor clock to be
extremely accurate (although it should be stsble with little
jitter and maintsin a good duty cycle).

Use of the Crystal Oscillator Module
A crystsl oscillator module is a hybrid device that contsins
a quartz crystsl, an oscillator circuit and an output buffer
for the clock output. Since the internal circuit is trimmed
during manufacturing, very good frequency accuracy and
stsbility are achieVed. These devices commonly yield
accuracy's of +\- 20 ppm and exhibit excellent stsbility
over time, temperature, and power supply voltsge. The
device requires a power supply and typically outputs a
CMOS TIL-compatible output clock signal.

The actual frequency listed in the dats sheet represents the
output frequency of the device as determined by multiplying
the ideal reference frequency of the device (exactly
14.31818 MHz) by the preprogrammed PLL ratio. Again,
the PLL ratio is programmed to obtsin an actual frequency
as close to the target frequency as possible, within the
limitstion of the device's Nand M integer ranges.

Use of the Discrete Quartz Crystal
Device
INPUT REFERENCE CLOCKS

Most ICS frequency generators contsin an integral crystsl
oscillator circuit. With such devices, an external quartz
crystsl is connected between two specified device pins.
This forms a complete parallel-resonant crystsl oscillator
circuit (also known as a Pierce oscillator). In most cases

Again by nature of the PLL technique, there will be a direct
correlation between the accuracy of the input reference
frequency and that of the output frequency. A +0.1 %.

B-114

•

ICS Clock Synthesizer App Note

the only external component required is the quartz crystal,
since the required load capacitors and feedback resistor are
integrated onto the chip as well. The complete oscillator
circuit is shown in Figure 2. With careful design, accuracy
to within + /- 1()() ppm can be achieved.

This is also used when no internal load capacitors are
provided (refer to device data sheet).

ICS DEVICE

LOAD CAPACITANCE
TO CRYSTAL

AV91 07
AV9110
AV9128
AV9129
AV9154
AV9155
ICS1494
ICS1562
ICS1567
ICS1694
ICS2407
ICS2409
ICS2439
ICS2494
ICS2595
ICS2655
ICS5300
ICS9132

12 pf
12 pf
12 pf
12 pf
12 pf
12 pf
15 pf
11 pf
15 pf
15 pf
15 pf
15 pf
15 pf
15 pf
15 pf
15 pf
12 pf
7.5 pf

XTAL

P!l
REFERENCE

FREQUENCY

i

i

I

III-=-

CRYSTAL OSCILlATOR
CIRCUITRY

I-=- II

~

,

CLOCK GENERATOR CHIP

Figure 2
ICS Clock Generator
Crystal Oscillator Circuit

Table 1
ICS Clock Generator
Capacitive Load to Crystal

Quartz crystal devices can be specified by the crystal
manufacturer for either series or parallel resonant operation.
All ICS clock generator devices use parallel resonant
operation, sometime referred to as "parallel mode" .
Parallel resonant crystals specify a load capacitance value
which must be observed to ensure an accurate oscillation
frequency.
Table 1 lists the load capacitance applied to the external
crystal by various ICS clock generators. This is the total
measured load capacitance which accounts for stray
capacitance in the device package and printed circuit traces
(short lead length used).
The load capacitance on the crystal can be increased by
applying external load capacitors as shown in Figure 3.
This is useful when the crystal's specified load capacitance
is above that provided the provided by the clock generator.

B-115

II

ICS Clock Synthesizer App Note

MC~

Ec~1

XTAL

CLl

T

- ------- ----

Figure 4
Electrical Model of Quartz Crystal
CLOCK SENEI?ATOR
CHIP

In a paraJlel resonant crystal oscillator circuit, such as used
in ICS clock synthesizer devices, an LC tank circuit is
created as illustrated in Figure 5. CEFF is the lump
capacitance consisting of CM' Cp, and extemaJ Cv

Figure 3
Connection of External
Load Capacitors
to Clock Generator Chip
The load presented to the crystal in Figure 3 is

The resonant frequency can then be calculated as:

1

f RESONANCE =2P'V~M"'EFF
rz:c-'
CLl and CL2 should be equivalent values.

The resistance RS in the crystal has no effect on resonance
frequency. However, the active circuitry of the oscillator,
represented by the inverter in Figure 5, must have enough
"negative resistance" to overcome the loss imposed by RS'
This allows the LS tank voltage amplitude to increase and
maintain a fuJI oscillation voltage swing. Most crystal
manufactures recommend a negative resistance magnitude of
at least five times the RS (or ESR) value to ensure oscillator
start up; ICS crystal oscillator circuits have a negative
resistance magnitude above 250 ohms.

Calculating Crystal Oscillation
Frequency Accuracy
When a quartz crystal is operated in a series resonant
oscillator, the crystal oscillates at it's series resonant
frequency determined by LM and CM (the crystal's
motional inductance and capacitance) as shown in Figure 4.

B·116

II

ICS Clock Synthesizer App Note

C

we assume that total CL variation can be +1- 3 pf, then
oscillation frequency error will be from -166.7 ppm to
+ 277.8 ppm. Even if assuming that external circuit
capacitance can be controlled, just considering the variation
of the AV9155's internal load capacitors, which vary -110% or + 1- 1 pf, would account for a oscillation frequency
error of -166 ppm to +75 ppm. Remember that oscillator
error due to CL deviation is in addition to other errors such
as the rated crystal frequency tolerance and the effects of
crystal temperature and aging (consult the crystal's data
sheet).

EFF

XTAL OSC

Crystal Power Dissipation

Figure 5
Electrical Model of Parallel Resonant
Quartz Crystal Oscillator Circuit
The parallel resonant frequency of the crystal oscillator is
higher than the series resonant frequency of the crystal.
The fractional frequency "pulling" or the fractional amount
that the parallel resonant frequency will be above the series
resonate frequency can be calculated as

If we know is, the series resonant frequency of the crystal,
we can then calculate /p, the parallel resonant frequency as

fp =(1 +P)fs·
Let's take the example of a series 14.31818 MHz crystal
used with the AV9155. A typical value of CM is 20xl0- 15
farad (the crystal manufacturer can give you this
information). From Table 1, we find that CL presented by
the AV9155 is 12 pf. In this case, P is calculated to be
0.0008333 and/p is calculated to be 14.33011 MHz which
is 833 ppm (parts per million) above the series resonant
frequency.
We can also use the above equations to determine
oscillation error caused by total CL error. In the example
of using the AV9155 where typical circuit CL is 12 pf, if

B-117

Crystal manufactures typically specify a suggested crystal
power dissipation range. This is the range within which the
crystal's temperature will not rise to the point of causing
excessive oscillation frequency drift. Maximum crystal
power dissipation is also typically listed. Well above the
suggested dissipation range, this is the limit above which
crystal damage can occur (it will stop working), over a
period of time.
Most through-hole mount crystals specify a suggested
power dissipation of about 1 mW, well suited for ICS clock
generstors. This is also true for the standard larger-sized
surface mount crystals.
Problems can arise with some smaller types of surface
mount crystals. A typical 14.318 MHz surface mount
crystal used with an ICS clock generator will dissipate
about 200 to 500 micro watts, depending on which clock
generator is used. Maximum crystal power ratings of ouly
100 micro watts or lower are not uncommon, however most
crystal manufactures will admit that this figure can be
exceeded by 5-10 times. For maximum power dissipation it
is best to consult directly with the crystal manufacturer.

Calculating Crystal Power Dissipation
Power dissipation within the quartz crystal is caused by
oscillation current flowing through the crystal's effective
series resistance, shown as RS in Figure 4. This is
commonly listed as 'ESR' (Effective Series Resistance) in
the crystal data sheet. Power dissipation can be calculated
as

•

ICS Clock Synthesizer App Note

where ILC is the oscillation current in the LC tank circuit
shown in Figure 5. It is difficult to measure ILC during
oscillation, therefore we measure differential voltage across
the crystal and make the following substitution:

where/is the frequency of oscillation and VpK is the peak
voltage across the crystal. Our final simplified equation is
now

Using the final equation it is easy to calculate approximate
power dissipation with readily obtainable values. VpK can
be measured with a high speed differential oscilloscope (low
capacitance probes must be used), or the curves of Figures
6 or 7 can be used for the following list of devices:
AV9107, AV9110, AV9128, AV9129, AV9154, AV9155.

Where VXTAL is the RMS voltage across the crystal.
ZXTAL consists of both the reactance of the inductor shown
in Figure 5 and resistance RS not shown. However, at
oscillation the inductive reactive is much larger than RS and
so the contribution of RS to ZXTAL can be ignored.
Therefore we can make the approximation that

As an example, lets say that we are operating an AV9155
with a VDD of 5 volts using a 14.318 MHz crystal with an
RS (or ESR) rating of 35 ohms. From Table 1 we find that
CL = 12 pf and from Figure 6 we find that VpK = 2.5
volts. Substituting values in the final equation above we
determine that crystal power dissipation is approximately
127 micro-watts.

Substituting in the earlier equation we get

By definition of a resonant circuit, the reactance's of the
crystal's inductance and the external load capacitance are
equal. This can be stated as

Again through substitution we now get

or

B-118

•
V pK

ICS Clock Synthesizer App Note

5

5

4

4
V pK

3

E

3
2

2

5

10

15

20

25

5

30

10

15

20

25

Frequency (MHz)

Frequency (MHz)

Figure 6
Peak Voltage Across Crystal
With VDD = 5.0 Volts

Figure 7
Peak Voltage Across Crystal
With VDD = 3.0 Volts

B·119

30

B-120

•

~

AN04

Integrated
Circuit
Systems, Inc.

Clock Generators Application Note

Clock Reference Guidelines for ICS Clock Generators
Most ICS Clock Generator ICs are designed to use an external
quartz crystal to establish the needed reference frequency. This
application note discusses crystal selection and use. Occasionally, it is desirable to instead use an external clock reference;
design considerations for this approach are also discussed.

ICS Crystal Oscillator Circuitry
Figure 1 shows a schematic of the ICS crystal oscillator circuitry. Combined with the external crystal, this implements a
Pierce oscillator circuit. Figure 2 shows the oscillator inverter
circuit in further detail. This inverter is unlike the CMOS
inverter commonly used by other clock generator devices. The
advantage of the ICS inverter is that it provides higher circuit
gain, which guarantees crystal start-up and provides a wider
frequency range. It also provides a TTL level input threshold
voltage at pin Xl (approximately 1.4 volts), which provides
compatibility with an external TTL reference clock. Typically
duty cycle of REFOUT is 43% (High)/57% (Low) when a
14.318 MHz crystal is used.

Guidelines for Crystal Selection
The ICS crystal oscillator circuitry operates the crystal in
parallel-resonant mode. Although most oscillator circuits are
designed to use parallel-resonant crystals, the least expensive
crystals are series-resonant devices. Using a series-resonant
crystal with an ICS clock generator will give excellent results
but will usually result in reference frequency that is about 0.1 %
too fast. Normally, this error is not significant for most CPU
or graphics applications.
If a higher clock accuracy is required, then a parallel-resonant
crystal must be used; a load capacitance value of 1O-2Opf
should be specified when ordering the crystal.

To further improve clock frequency accuracy, an external
capacitor can be connected between pin Xl and ground. The
capacitance value is typically between 10 and 2Opf. The actual
value will vary depending on the crystal manufacturer and is
found experimentally, using the crystal type intended for volume production.

VDD

4mAnominai
Buffer
~~YW~--~~-[~--+-~REFOUT

....- - - X 2

X 1 - - -....

I C.2:.sta~sc~to~irc.!
To PLUVCO Circuitry

ICS Clock Generator IC

Figure 1
Simplified Schematic of
ICS Crystal Oscillator Circuitry

Figure 2
ICS Crystal Oscillator Inverter Schematic

IAppNtGdlnesRevA100594
8-121

Clock Generators Application Note

The guidelines for RI value selection are as follows:

Guidelines for Using an External
Reference Clock
The recommended method of driving an ICS clock generator
with an external clock is shown in Figure 3, along with the
resulting wavefonns. The positive-going ramp of the X2 output is caused by the charging of capacitor C2 by the current
source when the N-channel PET is off (refer to Figure 2). VTH,
the input threshold of the REFOUT buffer, is approximately
1.4 volts. External resistor RI aids the inverter's current source
in charging C2 and accordingly improves the duty cycle of
REFOUT.
The use of an appropriate RI value will result in a near 50%
duty cycle from REFOUT. This also ensures reliable operation of the VCO/PLL circuitry and further maintains good
clock jitter perfonnance, which can be degraded by poor
duty cycle.

1. If reference clock duty cycle is greater than 50% (high
time), RI should be between 1 and 2 kohm. Actual value
should be detennined experimentally; the value should be
adjusted for nominal duty cycle of 50% from REFOUT. An
RI value of 1 kohm should cover most instances.
2. If reference clock duty cycle is less than 50% (high time),
RI may still be used but is not required. For example,
REFOUT from one ICS clock generator (duty cycle 43%)
can drive Xl of a second ICS clock generator without the
use ofR!.

External
Resistor

X1

(1 -2kO)

-I

Buffer
r-~~~~--~~-t~----~REFOUT
C2 1

X2

1
1.

Crystal Oscillator Circuit

________

.11

To PLLNCO CircUitry

REFOUT
ICS Clock Generator IC

Figure 3
Driving an ICS Clock Generator
with an External Clock

Figure 4
Waveforms of Figure 3

B·122

les
Motherboard Timing Generator
Products

In this latest issue of the ICS Data Book, ICS continues to lead the market by offering
the industry's widest selection of advanced motherboard and CPU clock generators
found anywhere. New products include designs to address a wide variety of uses,
including disk drive, modem, advanced Pentium and PowerPC clocking applications. This is all in addition to the widest choice of advanced desktop and laptop
motherboard and CPU systems clock generators in the industry.
As a market-oriented company, ICS designs products with and for you, our
customers, and we welcome inquiries concerning new product ideas for any of the
above applications.

C-l

E

ICS Timing Generator Selection Guide
Motherboard Clock Products
Product
Application

ICS
Device Type

Description

Number Number
of
of
Outputs PLL's

Package
Types

Page
C-3

ICS2407
ICS2409
ICS2419
ICS2439

IMI407, 1M1409 and IMI439
Compatible.

6
9
10
9

2
2
2
2

18-PinDIP, SOIC

ICS2492

Buffered XTAL Out.
Tristate PLL Outputs.

3

2

20-Pin
DIP, SOIC

C-lI

ICS2494-244
ICS2494A-317

Buffered XTAL Out. Note: See Video
Dot Clock Section for Data.

3

2

20-Pin
DIP,SOIC

B-ll

ICS2694

9 Fixed, CPU-CPU/2 Selectable Provides
CPU, Co-Processor, Hard and Floppy
Disk, Kbd, Ser. Port, Bus Clk. Function.

11

2

24-Pin
DIP, SOIC

C-17

AV9107C

CPU Clock Generator.

2

1

8 or 14-Pin
DIP, SOIC

C-23

ICS9108

3 Volt CPU Clock Generator.

2

1

8 or 14-Pin
DIP, SOIC

C-29

ICS9120-08
ICS9120-09

3 Volt Multimedia Audio
Synthesizer Clock Generator.

4

1

8-Pin
SOIC

C-35

ICS9131

32 kHz Input Generates CPU Clocks.

3

2

16-Pin
DIP, PDIP

C-41

ICS9133X

32 kHz Input Generates CPU Clock and
System Clock and Two Fixed Clocks.

6

3

20-Pin
SOIC, PDIP

C-49

Sub-Notebook

ICS9134-06
ICS9134-07

32 kHz Motherboard Frequency Generator.
Generated CPU, Reference and
One Fixed Clock.

6

3

16-Pin
SOIC

C-55

Pentium and
Green PC
Systems

AV9154A

Low Cost 16-Pin Clock Generator.
Generates CPU Clock, Keyboard Clock,
System Clock and 1/0 Clock.

7

2

16-Pin
DIP, SOIC

C-61

Laptopl
Notebook

AV9154-06
AV9154A-60

Clock Generator for OPTi Chip Set.

5

2

16-Pin
SOIC

C-71

AV9155A

Motherboard Clock Generator.
Produces CPU Clock, Keyboard Clock,
System Clock and 1/0 Clock.

8

2

20-Pin
DIP,SOIC

C-77

DesidopINItebook

ICS9158

Clock Generator with Integrated Buffers.

11

2

24-Pin SOIC

C-89

Pentium Systems

ICS9159-02

Clock Generator for Pentium Systems.

14

2

28-Pin SOIC

C-95

ICS9160-03

Clock Generator for PowerPC
603 Systems.

15

2

32-Pin SOIC

C-99

ICS9178-02

Clock Generator for PowerPC
6011601 + Systems.

14

1

44-PinPQFP

C-103

Motherboard

Audio
Synthesis

Notebook

Motherboard

PowerPC
Systems

24-PinDIP, SSOP
24-Pin DIP, SSOP
24-Pin DIP, SSOP

ADVANCE INFORMATION documents contsin infonnation on new products in the sampling or preproduction phase of development. Characteristic data
and other specifications are subject to change without notice.
PRODUCT PREVIEW documents contsin infonnation on products in the formative or design phase of development. Characteristic data and other specifications
are design gosls. ICS reserves the right to change or discontinue these products without notice.

C-2

ICS2407
ICS2409
ICS2419
ICS2439

Integrated

Circuit

•

Systems, Inc.

Dual-PLL Motherboard Frequency Generator
Description

Features

This ICS fiunily of motherboard frequency generators all stem
from the same basic design. They are dual-Pll. (phase-Iocked

•

loop) clock generators specifically designed for motherboard
applications. Metal layer and assembly options are used to
generate the three separate device types in order to optimize
the functionality for specific applications. All frequencies are
synthesized from a single reference clock which may be
generated by the on-chip crystal oscillator or an external
reference clock.

•

The CPU clock Pll. is ROM-programmed to generate any of
seven customer specified frequencies through selection of the
address lines SCLKO-SCLK2. In the ICS2409, ICS2419 and
ICS2439 versions the SCLK3 input selects those frequencies
directly or divided by two for the CPUX2 output. The CPUXl
output is then divided by two to generate the CPUCLK output.
A power-down mode may be selected with the SCLK inputs
to reduce standby current consumption to a few microamperes.

Supports 286, 386, & 486 desktop and notebook: mother-

board designs
Advanced ICS monolithic phase-locked loop technology
for low short-term and "cumulative" jitter
Completely integrated - no external loop filter capacitors

•

required
•

Dual-modulus presca1er permits high-speed operation
with no sacrifice in accuracy
Power-down mode for low standby power consumption
Low-skew between CPUXl and CPUCLK outputs
«Insec)
3-volt supply capability to 85 MHz (CPUX2 output)
Output enable (OE-) pin for tristate of device outputs
ICS2409, ICS2419 and ICS2439 offer 24-pin PDIP
(0.3") and 24-pin SSOP (5.3mm) package options
ICS2407 offers I8-pin PDIP (0.3") and I8-pin SOIC
(0.3") package options

•
•
•
•
•
•

The auxiliary (AUX) Pll. generates the fixed frequencies
shown in Thble 1 for other system u~es. A buffered reference
frequency output is available on the REFOUT pin. 1\vo
non-dedicated buffers are p1"O\':ided on the ICS2409, ICS2419
and ICS2439 for additional drive capability without adding
external buffers and their board space.

ICS2407 Simplified Block Diagram
XTAL1
XTAL2

>------~ REFOUTI

~----------~~

CPUCLK

: __

~

••• '._0 __ "_0_0_ •• " _ _ _ 0_ _ _ ._•• ' ___ ._. _ _ ._. _ •• _ . _ - ,

ii___ .___ .. 0_0AUXPlL(uaboYe)
14
2411HZ
__ 0_._••• ___•__••_•• ___•___._._ ••••• __~:
!
~
SCLKO
SCLKI
SCLK2

18

~

I2407109/19/39RoYB022394I
C-3

1611HZ

E

ICS2407
ICS2409
ICS2419
ICS2439

II
ICS2409 Simplified Block Diagram

XTALl
XTAL2

7. l59MHZ

SCLK3

,

:.~_~_.~

1

CPUPLL
.... _____, _,__ .__._..... __ ._._._______
._.__._ ...JI

1:~.:::~~:::·~:.:~~~~~~~~:~::~~:::::~~~~·-~=~:::::::.~;
scum
SCLKl
SCLK2

BUN

13

32MHZ

14

24MHZ

16

16MHZ

{ :
ROM ]

-----------1[»------~) Bl_OUT

----------1[>

)

B2_OUT

ICS2419 Simplified Block Diagram
,------.
XTALl
XTAL2

>-------4 REFOUT
r-·. ·--· . .-.. .--------_....--.--..-----.....----.-.-.. '''''''-j

SCLK23

,
CPUX2

. __._._._ . . _.____._ . ._.__.___._.__. . . ___.__ . __I
:--

..._-.-- ..... _...._--_....._._......

_--_ .._._-_..._

CPUCLK
32MHZ

..............

AUX PLl (as above)

•... . ........_.......... _, _. _H..__._..•_..•• ___._ •.. _, ........... _.... _H. ____.I

24MHZ
16MHZ

SCLKO
SCLKl
SCLK2

12MHZ

----------1[»------4) Bl_OUT

C·4

ICS2407
ICS2409
ICS2419
ICS2439

ICS2439 Simplified Block Diagram
XTAl1
XTAl2

> - - - - - - - 4 REFOUT
SCLK3

CPUX2

CPUCLK

AUX Pll (as above)

....
SClKO

SCLK1
SCLK2

BUN

~~:::
~12MHZ

-----------IC»-------~)

B1_0UT

--------------------[:»--------------~) ~_OUT

c-s

ICS2407
ICS2409
ICS2419
ICS2439
Circuit Function and Application

Pin Description

Fixed Frequencies

Input Pins

The ICS motherboard family supplies "fixed" frequencies normally used to provide several system functions:

Frequency Reference

•
•
•
•
•

The internal reference oscillator contains all of the passive
components required. An appropriate crystal should be connected between XTALl (1) and XTAL2 (2). In IBM compatible
applications this will typically be a 14.31818 MHz crystal.

32 MHz - ISA Bus Clock
24 MHz - Floppy Drives
16 MHz - AT Bus Clock Output
12 MHz - Keyboard Clock
7.149 MHz - Keyboard Clock

Digital Inputs
SCLKO, SCLKl, SCLK2 and SCLK3 (ICS2409, ICS2419 and
ICS2439 only) are the TTL compatible frequency select inputs
for the binary code corresponding to the desired frequency. All
select pins have internal pull-up devices built in (See Table 2
for a complete list of available frequencies).

Selectable CPU Clock Frequencies
The ICS2407, ICS2409, ICS2419 and ICS2439 are designed
to generate CPU clock options ranging from 24 MHz, to
88 MHz. For added flexibility, the ICS2409, ICS2419 and
ICS2439 allow the user to select each of these frequencies
divided by 2.

Buffer Inputs (ICS2409, ICS2419 & lCS2439)
B I_IN and B2_IN (3, 7) provide additional buffering needed
on a typical board design without the added cost of external
components.

Buffered Output Pins
In addition, the ICS2409, ICS2419 and ICS2439 provide 2
non-dedicated buffers for additional flexibility. This allows for
extra drive capability without sacrificing the extra board space
required for external buffers.

Output Enable
An output enable pin OE-allows the user to tristate the device
outputs. When this pin is high, all outputs are in tristate mode.
When low, all outputs are enabled. This pin has an internal
pull-down to enable all outputs when the pin is N/C.

Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2439 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator on the system, saving money as well as board space.
Depending on the load, it may be judicious to buffer REFOUT
when using it to provide the system clock. On the ICS2407,
there are two identical outputs, REFOUTl and REFOUT2.

Power-Down Mode
All three devices have been optimized for use in battery operated
portables. It can be placed in a power-down mode which drops its
supply current requirement below I11A(typical).
ICS2407 Pinout

ICS2409 Pinout

XTALl

REFoun

18

XTAL2

VDD

17

Nle

16

BUN

REFOUT2

16MHZ

15

vss

SCLKO

24MHZ

14

vss

13

CPUX2

"

vss

Nle
VDD

SCLKl
CPUCLK

SCLK2

OE-

23

XTAL2

B1_0UT

VDD

22

BUN

Nle

21

vss

16MHZ

20

SCLKO

24MHZ

13

SCLKO

B2_IN

32MHZ

18

B2_IN

B2_DUT

17

Nle

vss

16

VDD

SClKl

CPUX2

15

SCLK3

SCLK2
OE-

Nle

10

11

CPUCLK

ICS2419 Pinout

ICS2439 Pinout
REFOUT

B1_0UT

11

18-Pin PDIP or SOIC
K-4, K-7

REFOUT

XTALl

XTAL1

"

"

23

XTALl

REFOUT

XTAL2

B1_0UT

VDD

22

81 IN

Nle

21

vss

16MHZ

20

24MHZ

13

RESERVED

18

B2_0UT

17

vss

16

SCLKl

CPUX2

15

14

SCLK3

SCLK2

14

"

CPUCLK

OE-

13

24-Pin PDIP or SSOP 24-Pin PDIP or SSOP
K-S, K-9
K-S, K-9

C-6

"

23

VDD

22

Nle

21

16MHZ

20

SCLKO

24MHZ

13

B2_IN

32MHZ

18

B2_0UT

17

vss

16

Nle
VDD
10

SCLKl

CPUX2

15

11

SCLK3

SCLK2

14

12

CPUCLK

OE-

13

24-Pin PDIP or SSOP
K-S, K-9

ICS2407
ICS2409
ICS2419
ICS2439

II
Absolute Maximum Ratings
Supply Voltage .............
Input Voltage ..............
Output Voltage .............
Clamp Diode Current ........
Output Current per Pin .......
Operating Temperature .......
Storage temperature .........
Power Dissipation ...........

Voo ............
VIN........ . .....
VOUT ...........
VIK & 10K .......
lOUT ............
To ..............
TS ..............
Po ..............

-O.SV to +7V
-O.SV to Voo + O.SV
-O.5V to Voo + O.SV
±30mA

±SOmA
O°C to 70°
-85°C to 150°
SOOmW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than themaximum rated voltages. For proper operation it is recommended that Yin and Vout be constrained
to >=Vss and <=Voo.

DC Characteristics at 5 Volts VDD
MIN

MAX

UNITS

4.5

5.5

V

Voo=SV

Vss

0.8

V

VIH

Voo=SV

2.0

Voo

V

IIH

VIN=VOO

-

10
0.4

IlA
V

PARAMETER

SYMBOL

Operating Voltage Range

Voo

Input Low Voltage

VIL

Input High Voltage
Input Leakage Current

CONDITIONS

Output Low Voltage

VOL

IOL=1.20mA

-

Output High Voltage

VOH

IOH=1.20mA

2.4

0

V

Supply Current

100

VCLK=40MHz

40

rnA

Supply Current

100

VCLK=88MHz

-

50

rnA

Internal Pull-up Current

Rup

VIN=O.OV

30

100

IlA

Internal Pull-down Current

ROOWN

VIN=O.OV

30

100

Input Pin Capacitance

CIN

Fc=IMHz

-

8

IlA
pF

Output Pin Capacitance

COUT

Fc=IMHz

-

12

pF

Voo=3.3V

-

1

IlA

Power-down Supply Cument

IPN

C-7

ICS2407
ICS2409
ICS2419
ICS2439

II

DC Characteristics at 3.3 Volts VDD
PARAMETER

SYMBOL

Operating Voltage Range

CONDITIONS

VDD

MIN

MAX

3.0

3.6

UNITS
V
V

Input Low Voltage

VIL

VDD=3.3V

Vss

0.8

Input High Voltage

VIH

VDD=3.3V

2.0

VDD

V

10

/lA
V

-~--

Input Leakage Current

1m

VIN=VDD

-

Output Low Voltage

VOL

IOL=8.0mA

-

0.4

Output High Voltage

VOH

IOH=8.0mA

2.4

0

V

Supply Current

IDD

CPUX2=40MHz

35

rnA

25

rnA

Supply Current

IDD

CPUX2=88MHz

-

Internal Pull-up Current

Rup

VIN=O.OV

20

70

/lA

Internal Pull-down Current

RDOWN

VIN=O.OV

20

70

Input Pin Capacitance

CIN

Fc=IMHz

-

8

/lA
pF

Output Pin Capacitance

COUT

Fc=IMHz

-

12

pF

Power-down Supply Currrent

IpN

VDD=3.3V

-

I

/lA

AC Timing Characteristics
The following notes apply to all ofthe parameters presented in this section.
1. REFCLK = 14.31818 MHz
2. te = life
3. All units are in nanoseconds (ns)
4. Rise and fall time between .8 and 2.0 VDX unless otherwise stated.
5. Output pin loading = 15pF
6. Duty cycle measured at VDDI2 unless otherwise stated.

SYMBOL

PARAMETER

MIN

MAX

NOTES

OUTPUT TIMING @Sv
Tr

Rise Time

-

Tf

Fall Time

-

2

-

Frequency Error

0.5

%

Tak

Clock Skew (CPUCLK & CPUX2)

-

1.0

nSec

Duty Cycle

45

55

%

Output Enable to Tristate
(into and out of) time

-

15

nSec

-

2

OUTPUT TIMING @3.3v
Tr

Rise Time

-

3

Tf

Fall Time

-

3

-

Frequency Error

-

0.5

%

Tak

Clock Skew (CPUCLK & CPUX2)

-

1.5

nSec

Duty Cycle

45

55

%

"

20

nSec

-

Output Enable to Tristate
(into and out of) time

C-s

ICS2407
ICS2409
ICS2419
ICS2439
Table 1: Fixed Output Frequencies
ICS2439

ICS2419

ICS2409

ICS2407

24 MHz

32 MHz

32 MHz

24 MHz

16 MHz

24 MHz

24 MHz

16 MHz

12 MHz

16 MHz

16 MHz

12MHz

7.159 MHz

!

Table 2: CPU Clock Frequency Selection
ICS2409

ICS2407

SCLKO

ICS2439
Pattern 001

ICS2419

SCLKI

Pattern 001

Pattern 409

Pattern 407

0

0

0

12 MHz

12 MHz

12 MHz

12 MHz

0
1

1

16

16

0

0
0

0

20

20

16
20

20

SCLK3

SCLK2

0
0

16

0

0

1

1

25

25

25

25

0

1

0

0

33.33

33.33

0

1

0

1

33.33
40

40

40

33.33
40

0

1

0

1

1

30
Power-down

30
Power-down

44

0

1
1

Power-down

1

0

0

0

24

24

24

1

0

0

1

32

32

32

0

40

40

40

1

0
0

1
1

1

50

50

50

1

1

0

0

66.66

66.66

66.66

1

1

0

1

80

80

80

1

1

1

0

60

60

88

1

1

1

1

TEST

TEST

TEST

1

~

44
Power-down

Ordering Information
ICS2407-XXXN,ICS2407-XXXM; ICS2409-XXXN,ICS2409-XXXF
ICS2419-XXXN, ICS2419-XXXF; ICS2439-XXXN, ICS2439-XXXF

T
----'
-C=
T

Example:

ICS XXXX-XXX M

Package Type

N=DIP (E'lastlc)
M=SOIC (SOP)

F=SSOP

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - Prefix
~

rcs. AV=Standard Device; GSP=Genlock Device
~~a~~~fJe~~~~~;~t d~~~:g:r:~t~~t~~~~~i'~~r ~~~~~~~:~~ ~r~ fg~~~~v~O~I~e~~g
reserves the n ht to chan e or dlscontmue these roducts without notice

C·9

C·IO

•

ICS2492

Integrated
Circuit
Systems, Inc.

CPU Clock Generator
Description

The ICS2492 CPU Clock Generator is an integrated circuit
dual phase locked loop frequency synthesizer capable of generating 16 CPU frequencies and two other clock frequencies
for use with high performance personal computer motherboards. Utilizing CMOS technology to implement all linear,
digital and memory functions, the ICS2492 provides a lowpower, small footprint, low-cost solution to the generation of
CPU clocks. Provision is made via a single level custom mask
to implement customer-specific frequency sets. Phase-locked
loop circuitry permits rapid glitch-free transitions between
clock frequencies.
The ICS2492 is fully pin and function compatible with rcs's
industry-standard ICS2494 dual clock generator except that an
output enable function has been added to pin II. A pre-programmed version with a full selection of CPU clocks is available as part number ICS2492-453. The frequencies in this
pattern are essentially identical to those in the ICS2494-244
standard pattern.

Features
• Low cost -

•

•
•
•

•
•

•
•

•
•
•
•
•
•

eliminates need for multiple crystal clock
oscillators in motherboard applications
Mask-programmable frequencies
Pre-programmed versions for a selection of CPU clocks
Glitch-free frequency transitions
Provision for external frequency input
Internal clock remains locked when the external
frequency input is selected
Low power CMOS device technology
Small footprint - 20-pin DIP or SOIC
Buffered XTAL Out
Integral Loop Filter components
Fast acquisition of selected frequencies, strobed or nonstrobed
Guaranteed performance up to 135 MHz
Excellent power supply rejection
Advanced PLL for low phase-jitter
Output Enable function for tristate control of the two clock
outputs.

Pin Configuration

XTAL1
XTAL2
EXTFREQ
FSO
FS1
STROBE
FS2
FS3
MSO
VSS

2

3
4
5

6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

DVDD
CPUCLK
XTALOUT
VSS
VSS
AVDD
VSS
DVDD
BCLK
OUTEN

20-Pin DIP or sOle
K-4. K-7
Notes:
I. In apphcatJOns where the external frequency input is not specified,
EXTFREQ must be lIed to Vss.
2. ICS2492M(SOIC) pmout is idenlIcai to ICS2492N(DIP).
IICS2492ReVA100694

C-l!

II

ICS2492
Power Supply Conditioning

Circuit and Application Options
The ICS2492 will typically derive its frequency reference
from a series· resonant crystal connected between pins 1 and 2.
Where a high quality reference signal is available, such as in
an application where the graphics subsystem is resident on the
motherboard, this reference may directly replace the crystal.
This signal should be coupled to pin 1. If the reference signal
amplitude is less than 3.5 volts, a .047 microfarad capacitor
shoUld be used to couple the reference signal into XTALI. Pin
2 must be left open.
The ICS2492 is capable of multiplexing an externally gener·
ated frequency source ofVCLK via a mask option, in addition
to its internally·generated clock.
This is input via EXTFREQ (3). When an external source is
selected, the PLL remains locked to the value specified in the
selected address. This provision facilitates the ability to rapidly
change frequencies. When this option is not specified in the
ROM pattern, pin 3 is internally tied to V ss and should be
connected to Vss on the PCB.

The ICS2492 is a member of the second generation of dot clock
products. By incorporating the loop filter on chip and upgrad·
ing the VCO, the ease of application has been substantially
improved over earlier products. If a stable and noise·free power
supply is available, no external components are required. How·
ever, in most applications it is judicious to decouple the power
supply as shown in Figures 1 or 2. Figure 1 is the normal
configuration for 5 Volt only applications. Which of the two
provides superior performance depends on the noise content of
the power supplies. In general, the configuration of Figure 1 is
satisfactory. Figure 2 is the more conventional if a 12 Volt
analog supply is available, although the improved performance
comes at a cost of an extra component; however, the cost of the
discretes used in Figure 2 is less than the cost of Figure l' s
discrete components.
The number and differentiation of the analog and digital supply
pins are intended for maximum performance products. In most
applications, all VDDS may be tied together. The function of the
multiple pins is to allow the user to realize the maximum
performance from the silicon with a minimum degradation due
to the package and PCB. At the frequencies of interest, the
effects of the inductance of the bond wires and package lead
frame are non·trivial. By using the multiple pins, ICS has
minimized the effect of packaging and has minimized the
interaction of the digital and analog supply currents.

22

Jg3 ~2

rilH
Fsa

20

19
18

~

17

4

'"

¥e

v

Rl

..(') VCLK

'"' XTALOU T

~

FS1

5

N

STROBE

6

-=t

7

FS2
FS3 '"
MSO

0')

16

N

15

~

14

en

8

13

9

12

]0

11

-::.::-

Figure 1

C-12

5.0V

..(') MCLK
-0 MS1

II

ICS2492
The ICS2492 is not sensitive to the duty cycle of the bus clock;
however, the quality of this signal varies considerably with
different motherboard designs. As the quality of this signal is
typically outside of the control of the graphics adapter card
manufacturer, it is suggested that this signal be buffered on the
graphics adapter board. XTAL2 (2) must be left open in this
configuration.

Applications
Layout Considerations
Utilizing the ICS2492 in video graphics adapter cards or on
PS2 motherboards is simple, but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised in ensuring that components
not related to the ICS2492 do not share its ground. In applications utilizing a multi-layer board, Vss should be directly
connected to the ground plane. Multiple pins are utilized for
all analog and digital Vss and Vdd connections to permit
extended frequency VCLK operation to 135 MHz. However,
in all cases, all Vss and Voo pins should be connected.

5.0V

gl

19

,--2.

18

-4

17

5

6

1

~

r-11f--;
F"51
STROBE
f52
FS3
MSO

In motherboard applications it may be desirable to have the
ICS2492 provide the bus clock for the rest of the system. This
eliminates the need for an additional 14.31818 MHz crystal
oscillator in the system, saving money as well as board space.
To do this, the XTALOUT (18) output should be buffered
with a CMOS driver.

Output Circuit Considerations

Figure 2

rso

Buffered XTALOUT

ICS24

7
8

VCLK
XTALOU T

16
470

15
14

11-

9

12

~

11

.~2!7

1

RI

12.0V

':7V
MCLK
MS1

As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EMI.
To minimize problems with meeting FCC EMI requirements,
the trace which connects VCLK (19) or MCLK (12) and
other components in the system should be kept as short as
possible. The ICS2492 outputs have been designed to minimize overshoot. In addition, it may be helpful to place a ferrite
bead in these signal paths to limit the propagation of high order
harmonics of this signal. A suitable device would be a Ferroxcube 56-590-65/4B or equivalent. This device should be placed
physically close to the ICS2492. A 33 to 47 Ohm series
resistor, sometimes called source termination, in this path may
be necessary to reduce ringing and reflection of the signal and
may reduce phase-jitter as well as EM!.

External Frequency Sources
Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between XTALl (1) and XTAL2 (2). In
IBM-compatible applications this will typically be a 14.31818
MHz crystal, but fundamental mode crystals between 10 MHz
and 25 MHz have been tested. Maintain short lead lengths
between the crystal and the ICS2492. In some applications, it
may be desirable to utilize the bus clock. If the signal amplitude
is equal to or greater than 3.5 volts, it may be connected directly
to XTALl (1). If the signal amplitude is less than 3.5 volts,
connect the clock through a .047 microfarad capacitor to
XTALl (1), and keep the lead length of the capacitor to
XTALI (1) to a minimum to reduce noise susceptibility. This
input is internally biased at Voot 2. Since TIL compatible
clocks typically exhibit a VOH of 3.5V, capacitively coupling
the input restores noise immunity.

EXTFREQ (3) on versions so equipped by the programming,
is an input to a digital multiplexer. When this input is enabled,
signals driving the input will appear at VCLK (19) instead of
the PLL output. Internally, the PLL will remain in lock at the
frequency selected by the ROM code.

Digital Inputs
FSO (4), FSI (5), FS2 (7), and FS3 (8), are the TIL compatible frequency select inputs for the binary code corresponding
to the frequency desired. STROBE (6), when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 3. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all-zeros input state. MSO (9) andMSl (11) are the corresponding memory select inputs and are not strobed.

C-13

ICS2492
Absolute Maximum Ratings
Supply Voltage .
Input Voltage . .
Output Voltage .
Clamp Diode Current
Output Current per Pin .
Operating Temperature.
Storage Temperature . .
Power Dissipation . . .

VDD
VIN .
VOUT
VIK & 10K

lOUT
To.
Ts

PD.

-O.SVto +7V
-O.SV to VDD+O.SV
-O.SV to VDD+O.SV
+/ -30mA
+/ -SOmA
O°C to 70°C
-8S °C to + ISO°C
SOOmW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation it is recommended that VIN and VOUT be constrained
to >= Vss and <=VDD.

DC Characteristics (O°C to 70°C)
PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage

SYMBOL

MIN

MAX

UNITS

4.0

S.S

V

VDD=SV

Vss

0.8

V

VDD=SV

2.0

VDD

V

CONDITIONS

VDD
VIL
VIH

VIN=Vee

-

10

uA

Output Low Voltage

VOL

IOL=4.0mA

-

0.4

V

Output High Voltage

VOH

IOH=4.0mA

2.4

-

V

Supply Current

IDD

VDD = SV, VCLK = 80 MHz

-

27

rnA

SO

200

kohm

-

8

pf

12

pf

Input Leakage Current

Internal Pull-up Resistors

IIH

Rup

*

Vdd = SV, Vin= OV

Input Pin Capacitance

Cn

Fe= I MHz

Output Pin Capacitance

Cout

Fe= I MHz

* The following inputs have pull-ups: FSO-3, MSO-I, STROBE.

C-14

II

ICS2492

AC Timing Characteristics
The following notes apply to all parameters presented in this section:
I. Xtal Frequency = 14.31818 MHz
2. Te = liFe
3. All units are in nanoseconds (ns).
4. Rise and fall time is between 0.8 and 2.0 VDC.
5. Output pin loading = 25pF
6. Duty cycle is measured at I.4V.
7. Supply Voltage Range = 4.0 to 5.5 Volts
8. Temperature Range =0 °C to 70°C

SYMBOL

E

PARAMETER

MIN

MAX

NOTES

STROBE TIMING
Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

-

20
10
10

-

i

I

I

MCLK AND VCLK TIMINGS
Tr
Tf

~

I

-

Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency

-

Tpw

STROBE
FSO- FSJ

3
3
0.5
135
15

-

!

~

'}
X
t--

Tsu

-+-

Figure 3

C-1S

Thd

>K
--I

Duty Cycle 40% min. to
60% max.
%
MHz
ns

I

i
t

ICS2492
ICS2492 Pattern Request Form
In addition to the pattern below, custom patterns are also available, although a significant volume commitment and/or one-time
mask charge will apply. Contact ICS sales for details.

ICS
Part Number
Address FS3-0
(Hex)

ICS2492-453
Application
Frequency
(MHz)

0
I
2
3

20
24

4
5

50
66.6

6
7
8

80
100
54

9

70

0

90
110
25

C
D

Frequency
(MHz)

286-10
-12
386-16

32
40

t--------------_ B __ "

ICS2492Custom
Pattern #1

-20
-25

Custom pattern #1 reference frequency =
The standard frequency shown has been specified by and is supported by the respective VGA
manufacturer.
The standard pattern shown above uses
_ _ MHz as the input reference frequency.
Order Information: ICS2492M-XXX or
ICS2492N-XXX (XXX=Pattern number)

-33
-40
-50
TURBO-27
-35
-45
-55
486-25
-33

E

33.3
40

F

50

Address MSO
(Hex)

Frequency
(MHz)

Application

0
I

16

AT-BUS

24

FDC

-40
-50
Frequency
(MHz)

Ordering Information
ICS2492N-XXX or ICS2492M-XXX
Example:

ICS XXXX N -XXX

T-r'---_
_

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
N=DIP Cl'lastlC)
M=SOIC

' - - - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
L...----------Prefix
ICS, AV=Standard Device; GSP=Genlock DeVice

C·16

ICS2694

Integrated
Circuit
Systems, Inc.

•

Motherboard Clock Generator
Description

Features

The ICS2694 Motherboard Clock Generator is an integrated
circuit using PLL and VCO technology to generate virtually all
the clock signals required in a Pc. The use of the device can be
generalized to satisfy the timing needs of most digital systems
by reprogramming the VCO or reconfiguring the counter stages
which derive the output frequencies from the VCO's.

•

The primary VCO is customarily used to generate the CPU
clock and is so labeled on the ICS2694. Pre-programmed
frequency sets are listed on page 6. These choices were made
to match the major microprocessor families. CPUSEL (0-3)
allow the user to select the appropriate frequency for the
application.

•

Due to the filter in the phase-locked loop, the CPUCLK will
move in a linear fashion from one frequency to a newlyselected frequency without glitches. If a fixed CPUCLK value
is desired, CPUSEL (0-3) may be hard wired to the desired
address with STROBE tied high. (It has a pull-up.) For board
test and debug, pulling OUTPUTE to Ground will tristate all
the outputs.

•

•
•
•
•
•
•

Low cost - eliminates multiple oscillators and Count
Down Logic
Primary VCO has 16 Mask Programmable frequencies
(normally CPU clock)
Secondary VCO has I Mask Programmable frequency
(usually 96 MHz)
Pre-programmed versions for typical PC applications
10 Outputs in addition to the primary CPU clock
Capability to reconfigure counter stages to change the
frequencies of the outputs via mask options
Advanced PLL design
On-chip PLL filters
Very Flexible Architecture

Applications
•
•
•
•
•

CPU clock and Co-processor clock
Hard Disk and Floppy Disk clock
Keyboard clock
Serial Port clock
Bus clock
System counting or timing functions

Pin Configuration

OUT2
OUT1
OUTO
OUT9
CPUCLK
VSS
DVDD
STROBE
CPUSELO
CPUSEL 1
CPUSEL2
CPUSEL3

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

24-Pin DIP or sOle
K-5, K-7

IICS2694RevA1094

I
C-17

OUT3
OUT4
OUT5
OUT6
OUT7 (CPUClK/2)
OUT8
AVDD
XTAL2
XTAL1
AVSS
OUTPUTE
ClKIN

Ii

ICS2694
Pin Description
PIN NUMBER
1
2
3
4
5

NAME
OUT2
OUTl
OUTO
OUT9
CPUCLK

6
7
8

VSS
DVDD
STROBE

9
10
11
12
13

CPUSELO
CPUSELl
CPUSEL2
CPUSEL3
CLKIN

14
15
16
17

OUTPUTE
AVSS
XTALl
XTAL2

18
19
20
21
22
23
24

AVDD
OUT8
OUT7
OUT6
OUTS
OUT4
OUT3

DESCRIPTION
4mAOutput
4mAOutput
4mAOutput
4mAOutput
4mA Output driven by Voltage Controlled Oscillator 1 (VCOl). VCOI is controlled
by a 16 word ROM.
Ground for digital portion of chip
Plus supply for digital portion of chip
Input control for transparent latches associated with CPU (0-3) which select one of
16 values for CPUCLK. Holding STROBE high causes the latches to be transparent.
LSB CPUCLK address bit
CPUCLK address bit
CPUCLK address bit
MSB CPUCLK address bit
An alternative input for the reference clock. The crystal oscillator output and CLKIN
are gated together to generate the reference clock for the VCO's. If CLKIN is used,
XTALl should be held high and XTAL2 left open. If the internal oscillator is used,
hold CLKIN high.
Pulling this line low tristates all outputs.
Ground for analog portion of chip
Input of internal crystal oscillator stage
Output of internal crystal oscillator stage. This pin should have nothing connected
to it but one ofthe quartz crystal terminals.
Positive su~for analog portion of chip.
4mAOutput
4mA Output (Usually assigned as CPUCLKJ2 for co-processor use)
4mAOutput
4mAOutput
4mAOutput
4mAOutput

~~--

C·lS

II

ICS2694

Frequency Reference

Power Supply Conditioning

The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between XTALl (I) and XTAL2 (2). In
IBM-compatible applications, this will typically be a
14.31818 MHz crystal, but fundamental mode crystals between 10 MHz and 25 MHz have been tested. Maintain short
lead lengths between the crystal and the ICS2694. In order to
optimize the quality of the quartz crystal oscillator, the input
switching threshold of XTALl is VDD12 rather than the conventional 1.4 V of TTL. Therefore, XTALl may not respond
properly to a legal TTL signal since TTL is not required to
exceed VDD12. Therefore, another clock input CLKIN (pin 13)
has been added to the chip which is sized to have an input
switching point of 1.4 V. Inside the chip, these two inputs are
AND ED. Therefore, when using the XTALl and XTAL2,
CLKIN should be held high. (It has a pull-up.) When using
CLKIN, XTALl should be held high. (It does not have a
pull-up because a pull-up would interfere with the oscillator
bias.)

The ICS2694 is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free
power supply is available, no external components are required. However, in some applications it may be judicious to
decouple the power supply as shown in Figures I or 2. Figure
I is the normal configuration for 5 Volt only applications.
Which of the two provides superior performance depends on
the noise content of the power supplies. In general, the configuration of Figure I is satisfactory. Figure 2 is the more
conventional if a 12 Volt analog supply is available, although
the improved performance comes at a cost of an extra component; however, the cost of the discretes used in Figure 2 are less
than the cost of Figure 1's discrete components.

It is anticipated that some applications will use both clock

Since the ICS2694 outputs a large number of high-frequency
clocks, conservative design practices are recommended. Care
should be exercised in the board layout of supply and ground
traces, and adequate power supply decoupling capacitors consistent with the application should be used.

inputs, properly gated, for either board test or unique system
functions. By generating all the system clocks from one reference input, the phase and delay relationships between the
various outputs will remain relatively fixed, thereby eliminating problems arising from totally unsynchronized clocks interacting in a system.

+5

,lCl

+50

DVDD

Cl

llJ.lF
33

+5

R1 ,lC2 ~3
12J.lF!J.lF

DVDD

I1J.lF
470

AVDD

AVDD

+120
R1

VSS.AVSS

VSS,AVSS

1
Figure 2

Figure 1

C-19

Ii

II

ICS2694
Absolute Maximum Ratings
Supply Voltage ................
Input Voltage ..................
Output Voltage ................
Clamp Diode Current ...........
Output Current per Pin ..........
Operating Temperature ..........
Storage Temperature ............
Power Dissipation ..............

Voo. . . . . . . . . . ..
VIN . . . . . . . . . . ..
VOUT. . . . . . . . ..
VIK & 10K. . . . . ..
lOUT . . . . . . . . . ..
To .............
Ts .............

-0.5V to +7V
-0.5V to VDD +O.5V
-0.5V to VDD +0.5V
±30mA
±SOmA
O°C to + 150°C
-S5°C to + 150°C
Po ............. 500mW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that VIN and VOUT be
constrained to > = Vss and < = Voo.

DC Characteristics (OCC to 70 CC)
PARAMETER

IOperating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
Output High Voltage
Supply Current
Internal pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance

SYMBOL
Voo
VIL
VIH
IIH
VOL
VOH
100

Rup *
Cin
COU!

* The following inputs have pull-ups:

CONDITIONS
Voo=5V
Voo=5V
VIN = Vee
IOL = 4.0 mA
IOH = 4.0 mA
Voo = 5V, CPUCLK = SO MHz
Voo = 5V, Yin = OV
Fe= I MHz
Fe= I MHz

MIN
4.0
VSS
2.0
2.4

MAX
5.5
O.S
Voo
10
0.4

-

55
S
12

50
-

OUTPUTE, STROBE, CPUSEL (0-3), CLKIN.

C·20

-

-

UNITS
V
V
V

uA
V
V
mA
kohm
pf
pf

ICS2694
AC Timing Characteristics
The following notes apply to all parameters presented in this section:
1.
2.
3.
4.
5.
6.
7.

Xtal Frequency = 14.31818 MHz
All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC.
Output pin loading = l5pF
Duty cycle is measured at 1.4Y.
Supply Voltage Range = 4.5 to 5.5 Volts
Temperature Range =0 °C to 70°C

SYMBOL

PARAMETER

Tpw
Tsu
Thd

Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe

Tr
Tf
-

Rise Time
Fall Time
Frequency Error
Maximum Frequency

-

MIN
STROBE TIMING
20
10
10
FOUTTIMING

MAX
-

-

Duty Cycle 40% min. to 60% max.
at 80 MHz
%
MHz

3
3
0.5
135

-

NOTES

Note:
Pattern -004 has rising edges of CPUCLK and CPUCLKl2 matched to ± 2 ns.

i

Tpw

STROBE

/
CPUSEL (0-3)

X
I-

Tsu

C-21

---+-

Thd

X
-I

II

ICS2694
ICS2694 Standard
32 MHz
.846 MHz
24 MHz
6MHz
CPUCLK
VSS
DVDD
STROBE
CPUSELO
CPUSEl1
CPUSEl2
CPUSEL3

CPUSELO-3
(Hex)
0

Another alternative for CPU CLOCK generation is the
ICS2494-244 if the additional functions of the ICS2694 are
not needed in the application.

Patt~rns
16MHz
8 MHz
9.6 MHz
14.318 MHz
CPUCLKl2
1.19 MHz
AVDD
XTAl2
XTAL1
AVSS
OUTPUTE
CLKIN

ICS
Part Number
Address FS3-0
(Hex)
0
1
2
3
4
5
6
7
8
9
0

CPUCLK OUTPUT (Pin 5)
(MHz)
2

1
2
3
4
5
6
7
8
9

10

B
C
D
E

20
24
25

32
33.33

F

40

Address MS 1-0
(Hex)
0
1
2
3

48
50
54
66.67
68
80
100
16

10

11
12
13

14
15

ICS2494244
Frequency

Note: Pattern -004 has rising edges of CPUCLK and
CPUCLKl2 matched to ± 2 ns.

Ordering Information
ICS2694N-XXX or ICS2694M-XXX
Example:

ICS XXXX M-XXX

TTL...___

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
N=DIP (Elashc)
M=SOIC

' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)

' - - - - - - - - - - PrerlX

-

ICS, AV=Standard Device; GSP=Genlock Device

C-22

(MHz)

20
24
32
40
50
66.6
80
100
54
70
90
110
25
33.3
40
50
Frequency
(MHz)

16
24
50
66.6

AV9107C

Integrated
Circuit
Systems, Inc.

CPU Frequency Generator
General Description

Features

The AV9107C offers a tiny footprint solution for generating
two simultaneous clocks. One clock, the REFCLK, is a fixed
output frequency which is the same as the input reference
crystal (or clock). The other clock, CLK I, can vary between 2
and 120 MHz, with up to 16 selectable preprogrammed frequencies stored in internal ROM (frequency range depends on
design option).

•
•
•

The device has advanced features which include on-chip loop
filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and
an optional ferrite bead - are all that are required for jitter-free
operation. Standard versions for computer motherboard applications are the AV9107C-03, and AV9107C-OS. Custom
masked versions, with customized frequencies and features,
are available in 6-8 weeks for a small NRE.

•
•
•
•

•
•

Patented on-chip Phase-Locked Loop with VCO for clock
generation
Provides reference clock and synthesized clock
Generates frequencies from 2 to 120 MHz (depending on
option)
8-pin DIP or SOP package or l4-pin DIP or SOP package
2 to 32 MHz input reference frequency (depending on
option)
On-chip loop filter
Up to 16 frequencies stored internally
Low power CMOS technology
Single +3.3 or +5 volt power supply

Applications
Graphics: The AV9107C is the easiest to use, lowest cost, and
smallest footprint frequency generator for graphics applications. It can generate up to 16 different frequencies, including all
frequencies necessary for VGA standards. It should be used in
place of the AV9105/6 when the reference clock is also needed.
Computer: The AV9107C is the ideal solution for replacing
high speed oscillators and for reducing clock speeds to save
power in computers. The device provides smooth, glitch-free
frequency transitions so that the CPU can continue to operate
during slow down or speed up. The rate of frequency change
makes the AV9107C compatible with all 386DX, 386SX,
486DX, 486DX2, and 486SX devices. Standard versions include the AV9107C-03, -05, -10, -11.

Disk Drives: Smaller than a single crystal or an oscillator, the
tiny SOIC package can be used for any general purpose frequency generation in disk drives. The most popular application
is for Constant Density Recording, where its low jitter output
clock provides the necessary frequencies for reading and recording. Another popular application is for slowing the disk
drive CPU to save power.
High Speed Systems: The AV9107C can be used as a proximity
oscillator - using a low frequency (down to 2 MHz) input to
generate a high frequency clock (up to 120 MHz) near the
device requiring the high frequency (depending on option).
This avoids the need to route high speed traces over a long
distance.

Block Diagram

r
POWER ..... I
DOWN
I

CLK1 or
2XCPUCLK

1--_....

OE

FSO -...,..---1~

FREQUENCY STORE/
FS1 _-+_--1~
PHASE LOCK LOOP
CONTROL LOGIC
FS2 --.----1~
FS3 __~__~~~________________~
X1/ICLK
X2

--+--i.~r--""'----1______________""1
+-t--t-===~

IAV91 07CRevAOl12294SJ
C-23

OE

REFCLKor
CPUCLK

II

AV9107C
Pin Configuration
FSO

GND

2

8

REFCLK

7

VDD

X1/1CLK

3

6

CLK1

X2

4

5

FS1

FS1

AV91 07C-05/-1 0
8-Pin DIP, SOIC
K-3, K-6

14

FSO

FS2

2

13

REFCLK

FS3

3

12

VDD

AGND

4

11

CLK1

GND

5

10

PD

6

9

OE (REFCLK)

X1/1CLK

7

8

X2

OE (CLK1)

AV9107C-03/-11
14-Pin DIP, SOIC
K-3, K-6

Pin Descriptions for AV9107C-03, AV9107C-05 and AV9107C-10
PIN NUMBER

f--

PIN
NAME

TYPE

DESCRIPTION

-05/-10

-03

1

14

FSO

Input

Frequency Select 0 for CLKI (-03 has pull-up).

5

1

FSI

Input

Frequency Select I for CLKI (-03 has pull-up).

2

FS2

Input

Frequency Select 2 for CLKI (-03 has pull-up).

3

FS3

Input

Frequency Select 3 for CLKI (-03 has pull-up).

4

AGND

-

Analog GROUND.

2

5

GMD

-

Digital GROUND.

6

PD

Input

POWER-DOWN. Shuts off chip when low. Internal pull-up.

3

7

XllICLK

Input

CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 14.318 MHz system
clock.

4

8

X2

9

OE(REFCLK)

10

OE(CLKI)

6

11

CLKI

7

12

VDD

8

13

REFCLK

Output
Input
Input
Output

Output

CRYSTAL OUTPUT (No Connect when clock used.).
OUTPUT ENABLE. Tristates REFCLK when low. Pull-up.
OUTPUT ENABLE. Tristates CLKI when low. Pull-up.
CLOCKI Output (see decoding tables).
Digital power supply (+5V DC).
REFERENCE CLOCK output. Produces a buffered version of the input clock or
crystal frequency (typically 14.318 MHz).

C-24

AV9107C
Frequency Accuracy and Calculation
The accuracy of the frequencies produced by the AV9107C
depends on the input frequency and the desired actual output
frequency. The formula for calculating the exact frequency is
as follows:
Output Frequency = Input Frequency x

A

Allowable Input and Output Frequencies
for Possible Options
The input frequency should be between 2 and 32 MHz, depending on options, and the AlB ratio should not exceed 24. The
output should fall in the range of 2-120 MHz, depending on
options.

B

Output Enable

where A=2, 3, 4 ... 128, and
B=2, 3, 4 ... 32.
For example, to calculate the actual output frequency for a
video monitor expecting a 44.900 MHz clock and using a
14.318 MHz input clock, the closest AlB ratio is 69/22, which
gives an output of 44.906 MHz (within 0.02% of the target
frequency). Generally, the AV9107C can produce frequencies
within 0.1 % of the desired output.

The Output Enable feature tristates the specified output clock
pins. This places the selected output pins in a high impedance
state to allow for system level diagnostic testing.

Power-Down
If equipped, the power-down shuts off the specified PLL or
entire chip to save current. A few milliseconds are required to
reach full functioning speed from a power-down state.

Frequency Transitions
A key AV9107C feature is the ability to provide glitch-free frequency transitions across its output frequency range. The
AV9107C-03 provides smooth transitions between any of the two groups of eight frequencies (when FS3=0 or FS3=1), so that
the device will switch glitch-free between 4-100 MHz and 2-50 MHz.

C-2S

AV9107C
Absolute Maximum Ratings
A VDD, VDD referenced to GND ...............
Operating temperature under bias ...............
Storage temperature ..........................
Voltage on I/O pins referenced to GND ...........
Power dissipation ............................

7V
O°C to + 70°C
-65°C to + 150°C
GND -0.5V to VDD +O.5V
0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics at 5V
Operating VDD = +4.5V to +5.5V; TA =O°C to 70°C unless otherwise stated

J;.tC Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Input Low Voltage

VIL

-

-

0.8

V

Input High Voltage

VIH

2.0

-

V

Input Low Current

IIL
IIH

6.0

16.0

~A

-

VIN=OV

-

2.0

~A

VOL

VIN=VDD
IOL=1 OrnA

-2.0

Output Low Voltage, Note 1

-

0.15

0040

V

Output High Voltage, Note 1

VOH

IOH=-30rnA

3.25

-

V

Output Low Current, Note 1

IOL

VOL=D.8V

204
22.0

35.0

-

rnA

VOH=2.0V
Unload, 50 MHz

-50.0

-35.0

rnA

18.0

42.0

rnA

38.0

100.0

~A

Input High Current

Output High Current, Note 1

IOH

Supply Current

Icc

Supply Current

Icc
(PDlow)

Unload, Logic Inputs 000

-

Supply Current

Icc
(PDlow)

Unload, Logic Inputs 111

-

14.0

40.0

~A

-

380.0

700.0

kohms

0.60
0040

lAO

ns

1.00

ns

2.0

3.5

ns

1.0

2.5

ns

Pull-up Resistor, Note 1

Rpu

AC Characteristics
Rise Time 0.8 to 2.0Y, Note 1

Tr

15pfload

Fall Time 2.0 to 0.8V, Note 1

Tr

15pfload

Rise Time 20% to 80%, Note 1

Tr

15pfload

-

Fall Time 80% to 20%, Note I

Tr

15pfload

-

Duty Cycle, Note 1

From 20 to 100 MHz

Jitter, One Sigma, Note 1

Dt
TJ1s
TJ1S

Jitter, One Sigma, Note 1

TJis

From 14 to Below

Jitter, Absolute, Note 1

Tjab

From 20 to 100 MHz

-250.0

Jitter, Absolute, Note 1

TJab

From 14 to 16 MHz

-500.0

Jitter, Absolute, Note 1

Tjab

From 14 to Below

Input Frequency, Note 1

11.0

Output Frequency

Fl
Fo

Power-up Time, Note 1

Tpu

Transition Time, Note 1

Tft

Jitter, One Sigma, Note 1

15pfload

@

lAV

45.0

50.0

55.0

%

-

50.0

150.0

ps

100.0

200.0

ps

0.2

1.0

%

250.0

ps

From 14 to 16 MHz

8t066.6MHz

500.0

ps

1.0

3.0

14.3

19.0

%
MHz

2.0

-

120.0

MHz

-

7.58

18.0

ms

-

6.0

13.0

ms

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

C-26

II

AV9107C

Electrical Characteristics at 3.3V
Operating VDD = +3.0V to +3.7V; TA =O°C to 70°C unless otherwise stated

PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage, Note 1
Output High Voltage, Note 1
Output Low Current, Note 1
Output High Current, Note 1
Supply Current
Supply Current

SYMBOL
Vn..
Vm
In..
1m
VOL
VOH
10L
IOH
Icc
Icc
(PO low)

Supply Current

Icc
(PO low)

Pull-up Resistor

Rpu

Rise Time 20% to 80%, Note 1
Fall Time 80% to 20%, Note 1
Duty Cycle, Note 1
Jitter, Oue Sigma, Note 1
Jitter, Oue Sigma, Note 1
Jitter, One Sigma, Note 1
Jitter, Absolute, Note 1
Jitter, Absolute, Note 1
Jitter, Absolute, Note 1
Input Frequency, Note 1
Output Frequency, Note 1
Power-up Time, Note 1
Transition Tune, Note 1

Tr
Tf
Ot
TJIS
TJ1s
TJ1s
TJab
TJab
Tjab
FI
Fo
Tpu
Tft

DC CbaraeteristI.e
TEST CONDITIONS

MIN

TYP

MAX

UNITS

0.7Voo

0.20Voo

V
V

VIN=OV
VIN=Voo
IOL=6rnA
IOH=-5rnA
VOL=O.2Voo
VOL=O.7Voo
Unloaded, 50 MHz
Unload, Logic Inputs ()()()

0.85
15.0
-

2.5
0.15
0.92
22.0
-17.0
22.0
13.0

Unload, Logic Inputs III

-

4.0

12.0

!LA

-

550.0

900.0

kohms

-

2.2
1.2
46.0
50.0
100.0
0.4

3.5
2.5
53.0
150.0
200.0
1.0
250.0
500.0
3.0
15.3
66.6
18.0
13.0

ns
ns
%
ps
ps
%
ps
ps
%
MHz
MHz
ms
ms

AC CbaraeteristI.e
15pfload
15pfload
15pfload @ 50%
From 25 to 85 MHz
From 14 to 20 MHz
From 14 to Below
From 25 to 85 MHz
From 14 to 20 MHz
From 14 to Below

-2.0

40.0
-

-250.0
-500.0
13.3
2.0

-

-

8 to 66.6 MHz

1.0
14.3

7.58
6.0

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

C·27

7.0
2.0
0.1

-

-10.0
40.0
40.0

!LA
!LA
V
V
rnA
rnA
rnA

!LA

II

AV9107C
Decoding Table for AV9107C-11 (in MHz)

Actual Frequencies
Decoding Table for AV9107C-OS, 14.318 input
FSI

FSO

0
0
I
I

0
I
0
I

eLKI
40.01
50.11
66.61
80.01

MHz
MHz
MHz
MHz

*5Vonly
Decoding Table for AV9107C-03, 14.318 input
FS3

FS2

FSI

FSO

eLKI

0
0
0
I
0
0
0
0
I
I
I
1
I
I
I
I

0
0
0
0
I
I
I
I
0
0
0
0
I
I
I
I

0
0
I
I
0
0
1
I
0
0
I
I
0
0
I
I

0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I

16.00 MHz
39.99 MHz
50.11 MHz
80m MHz
66.58 MHz
100.23 MHz
8.02 MHz
4.01 MHz
8.02 MHz
20.00 MHz
25.06 MHz
40.01 MHz
33.29 MHz
50.11 MHz
4.01 MHz
2.05 MHz

FS3

FS2

FSI

FSO

eLKI

0
0
0
I
0
0
0
0
I
I
I
I
I

0
0
0
0
I
I
I
I
0
0
0
0
I
I
I
1

0
0
I
I
0
0
I

0
I
0
I
0
I
0
I
0
I
0
1
0
1
0
1

16.00 MHz
33.99 MHz
50.11 MHz
80.01 MHz
66.58 MHz
100.23 MHz
60.00 MHz
4.01 MHz
8.02 MHz
20.00 MHz
25.06 MHz
39.99 MHz
33.25 MHz
50.11 MHz
30.00 MHz
4.01 MHz

1
1
I

1
0
0
1

1
0
0
1
I

*5Vonly
Decoding Table for AV9107C-10, 14.318 Input
FSI

FSO

eLKI

0
0
I
I

0
I
0
I

25.057 MHz
33.289 MHz
40.006 MHz
50.113 MHz

*5Vonly

*5Vonly

Ordering Information
AV9107C-05CN8, AV9107C-10CN8, AV9107C-03CN14, AV9107C-11CN14 or
AV9107C-05CS8, AV9107C-10CS8, AV9107C-03CS14, AV9107C-11CS14

Example:

xxx XXXX-PPP M x#w
L ....
coo"t&P~_m
..h
Lead
2 or 3 digtts

11

Count~ I.

W~.3"

SOIC or .6" DIP; None=Standard W,dth

Package Type
N=DIP (J'Jasuc)
S~SOP

Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable)
" - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
"-----------Prer~

ICS, AV=Standard Device; GSP=GenJock DeVIce

C-2S

ICS9108

Integrated
Circuit
Systems, Inc.

•

CPU Frequency Generator
General Description

Features

The AV9108 offers a tiny footprint solution for generating two
simultaneous clocks. One clock, the REFCLK, is a fixed output
frequency which is the same as the input reference crystal (or
clock). The other clock, CLKl, can vary between 2 and 120
MHz, with up to 16 selectable preprogrammed frequencies
stored in internal ROM.

•
•
•
•
•

The ICS9108 is ideal for use in a 3.3V system. It can generate
a 66.66 MHz clock at 3.3V. In addition, the ICS9108 provides
a symmetrical wave form with a worst case duty cycle of 45155.
The ICS9108 has very tight edge control between the CPU
clock and 2XCPU clock outputs, with a worst case skew of
25Ops.

•

•
•
•

•
•

Runs up to 80 MHz at 3.3V
50150 typical duty cycle at 5V
±250ps absolute jitter
Generates frequencies from 2 to 140 MHz
2 to 32 MHz input reference frequency
Up to 16 frequencies stored internally
Patented on-chip Phase Locked Loop with VCO for clock
generation
Provides reference clock and synthesized clock
On-chip loop filter
Low power 0.811 CMOS technology
8-pin or l4-pin DIP or SOIC package

The device has advanced features which include on-chip loop
filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and
an optional ferrite bead - are all that are required for jitter-free
operation. Standard versions for computer motherboard applications are the AV9108-03, AV9108-05 and the ICS9108-10.
Custom masked versions, with customized frequencies and
features, are available in 6-8 weeks for a small NRE fee.

Block Diagram

r
POWER-.I
DOWN
1

CLK10r
2XCPUCLK

FREQUENCY STORE!
PHASE LOCK LOOP
--+---.J
CONTROL LOGIC
-...,.---.J
F~--~--~~~----------------J
FSO
FS1

FS3 __+-~~
X1/1CLK
X2

OE

r----+---

OE

__~-:__-,

1---------+1

IAV91 OBRevA082594
C·2!)

REFCLK or
CPUCLK

II

II

ICS9108
Pin Configuration
FSO

8

REFCLK

GNO

2

7

VOO

X1/1CLK

3

6

CLK1

X2

4

5

FS1

FS1

AV91 08-05/-10
8-Pin DIP, SOIC
K-3, K·6

FSO

FS2

2

13

REFCLK

FS3

3

12

VOO

AGNO
GNO
PO

4

11

CLK1

5

10

OE (CLK1)

6

9

OE (REFCLK)

X1/1CLK

7

8

X2

AV9108-03/-11
14-Pin DIP, SOIC
K-3, K-6

Pin Descriptions for AV91 08-03, AV91 08-05 and AV91 08-1 0
PIN NUMBER

PIN
NAME

TYPE

DESCRIPTION

FSO
FSI
FS2
FS3
AGND
GMD

Input
Input
Input
Input

PD

Input
Input

Frequency Select 0 for CLKI (-03 has pull-up).
Frequency Select I for CLKI (-03 has pull-up).
Frequency Select 2 for CLKI (-03 has pull-up).
Frequency Select 3 for CLKI (-03 has pull-up).
Analog GROUND.
Digital GROUND.
POWER-DOWN. Shuts off chip when low. Internal pull-up.
CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 14.318 MHz
system clock.
CRYSTAL OUTPUT (No Connect when clock used.).
OUTPUT ENABLE. Tristates REFCLK when low. Pull-up.
OUTPUT ENABLE. Tristates CLKI when low. Pull-up.
CLOCKI Output (see decoding tables).
Digital power supply (+3V DC).
REFERENCE CLOCK output. Produces a buffered version of the input clock or
crystal frequency (typically 14.318 MHz).

-05/-10/-13

-03

I
5

14
I
2
3
4
5
6
7

4

8
9
10

6
7
8

11
12
13

X2
OE(REFCLK)
OE(CLKI)
CLKI
VDD
REFCLK

2
3

XIIICLK

-

Output
Input
Input
Output
-

Output

C-30

II

ICS9108
Decoding Table for AV91 08-11 (in MHz)

Actual Frequencies
Decoding Table for AV9108-QS, 14.318 input
FSI

FSO

0
0
I
I

0
I
0
I

eLKI
40.01
50.11
66.61
80.01

MHz
MHz
MHz
MHz

Decoding Table for AV91 08-03, 14.318 input
FS3

FS2

FSI

FSO

eLKI

0
0
0
I
0
0
0
0
I
I
I
I
I
I
I
I

0
0
0
0
I
I
I
I
0
0
0
0
I
I
I
I

0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I

0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I

16.00 MHz
39.99 MHz
50.11 MHz
80.01 MHz
66.58 MHz
100.23 MHz
8.02 MHz
4.01 MHz
8.02 MHz
20.00 MHz
25.06 MHz
40.01 MHz
33.29 MHz
50.11 MHz
4.01 MHz
2.05 MHz

FS3

FS2

FSI

FSO

eLKI

0
0
0
1
0
0
0
0
1
1
1
1
1
I
1
1

0
0
0
0
I
I
I
I
0
0
0
0
1
I
1
1

0
0
1
1
0
0
1
I
0
0
1
1
0
0
1
I

0
I
0
1
0
1
0
I
0
I
0
1
0
I
0
I

16.00 MHz
33.39 MHz
50.11 MHz
80.01 MHz
66.58 MHz
100.23 MHz
60.00 MHz
4.01 MHz
8.02 MHz
20.05 MHz
25.06 MHz
39.99 MHz
33.25 MHz
50.11 MHz
30.00 MHz
4.01 MHz

Decoding Table for AV91 08-10, 14.318 input
FSI

FSO

eLKI

0
0
I
I

0
I
0
I

25.057 MHz
33.289 MHz
40.006 MHz
50.113 MHz

Note: The dash number following ICS9108 must be included when ordering product since it specifies the frequency decoding
table being ordered. Decoding options can be created by a simple metal mask change.

C-31

Ii

II

ICS9108
Frequency Accuracy and Calculation

Allowable Input and Output Frequencies

The accuracy of the frequencies produced by the ICS9108
depends on the input frequency and the desired actual output
frequency. The formula for calculating the exact frequency is
as follows:

The input frequency should be between 2 and 32 MHz and the
AlB ratio should not exceed 24. The output should fall in the
range of 2-120 MHz.

A
Output Frequency = Input Frequency x B

Output Enable
The Output Enable feature tristates the specified output clock
pins. This places the selected output pins in a high impedance
state to allow for system level diagnostic testing.

where A=2, 3, 4 '" 128, and
B=2, 3, 4 ... 32.
For example, to calculate the actual output frequency for a
video monitor expecting a 44.900 MHz clock and using a
14.318 MHz input clock, the closest AlB ratio is 69122, which
gives an output of 44.906 MHz (within 0.02% of the target
frequency). Generally, the ICS9108 can produce frequencies
within 0.1 % of the desired output.

Power-Down
If equipped, the power-down shuts off the specified PLL or
entire chip to save current. A few milliseconds are required to
reach full functioning speed from a power-down state.

Frequency Transitions
A key ICS9108 feature is the ability to provide glitch-free frequency transitions across its output frequency range. The ICS9108
provides smooth transitions between any of the two groups of eight frequencies (when FS3=0 or FS3= I), so that the device will
switch glitch-free between 4-100 MHz and 2-50 MHz.

C·32

II

ICS9108

Absolute Maximum Ratings
AVDD, VDD referenced to GND ............... 7V
Operating temperature under bias ............... O°C to +70°C
Storage temperature .......................... -65°C to +150°C
Voltage on I/O pins referenced to GND ........... GND -0.5V to VDD +O.5V
Power dissipation ............................ 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics at 5V
(Operating VDD = +4.5V to +5.5V; TA =O°C to 70°C unless otherwise stated)

DC~
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage, Note I
Output Low Current, Note 1
Output High Current, Note 1
Supply Current
Supply Current

SYMBOL
VIL
VIH
IlL
IIH
VOL
VOH
IOL
IOH

Icc
Icc

TEST CONDmONS

Pull-up Resistor, Note 1
Rise Time 0.8 to 2.0Y, Note 1
Fall Time 2.0 to 0.8Y, Note 1
Rise Time 20% to 80%, Note 1
Fall Time 80% to 20%, Note 1
Duty Cycle, Note 1
Jitter, Oue Sil!;D1ll, Note 1
Jitter, Oue Sigma, Note 1
Jitter, Oue Sigma, Note 1
Jitter Absolute. Note 1
Jitter. Absolute. Note 1
Jitter. Absolute, Note 1
Input Frequency, Note 1
Output Frequency
Power-up Time, Note 1
Transition Time, Note 1

Icc

MAX

UNITS

2.0

6.0

0.8

V
V

-

-

0.15
3.25
35.0
-50.0
18.0
38.0

-

14.0

40.0

uA

-

380.0

700.0

kohms

-

0.60
0.40
2.0
1.0
50.0
50.0
100.0
0.2

1.40
1.00
3.5
2.5
55.0
150.0
200.0
1.0
250.0
500.0
3.0
19.0
120.0
18.0
13.0

ns
ns
ns
ns
%
ps

Unload, Logic Inputs 111

AC CbimK:terIstks
15pfload
15pfload
15pfload
15pfload
15pfload @ I.4V
From 20 to 100 MHz
From 14 to 16 MHz
From 14 to Below
From 20 to 100 MHz
From 14 to 16 MHz
From 14 to Below

-2.0

-

-

45.0
-

-

-250.0
-500.0
11.0
2.0

-

-

8t066.6MHz

1.0
14.3

7.58
6.0

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

C·33

16
2.0
0.40
-35.0
42.0
100.0

2.4
22.0

(PDlow)
Rvu
Tr
Tf
Tr
Tf
Dt
TIS
T'IS
TIS
Tab
Tab
Tab
Fi
Fo
Too
Tft

TYP

VIN=OV
VIN=VDD
IOL=IOmA
IOH=-30mA
VOL=O.8V
VOH=2.0V
Unload, 50 MHz
Unload, Logic Inputs 000

(PDlow)
Supply Current

,
MIN

uA

uA
V
V
rnA
rnA
rnA

uA

DS

%
ps
ps
%
MHz
MHz
ms
ms

C

II

ICS9108
Electrical Characteristics at 3.3V
(Operating VDD = +3.0V to +3.7V; TA =O°C to 70°C unless otherwise stated)

DC Characteristics
PARAMETER

SYMBOL

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Supply Current
Supply Current

VIL
VIH
IIL
IIH
VOL
VOH
IOL
IOH
Icc
Icc
(PDlow)

Supply Current

Icc
(PDlow)

Pull-up Resistor

ROll

:'

,

TEST CONDITIONS

MIN

TYP

MAX

UNITS

-

0.20VDD

0.7VDD

-

7.0
2.0
0.1

V
V
IlA

-

-

2.5

-2.0

-

-

-

0.15
0.92
22.0
-17.0
22.0
13.0

-10.0
40.0
40.0

-

4.0

12.0

JlA

-

550.0

900.0

kohms

-

2.2
1.2
46.0
50.0
100.0
0.4

3.5
2.5
60.0
150.0
200.0
1.0
250.0
500.0
3.0
15.3
90.0
18.0
13.0

VIN=OV
VIN=VDD
IOL=6rnA
IOH=-5rnA
VOL=0.2VDD
VOL=0.7VDD
Unloaded, 50 MHz
Unload, Logic Inputs 000

0.85
15.0

Unload, Logic Inputs III

-

-

Tr
Tf
Dt
TIS
TIS
TIS
Tab
Tab
Tab
FI
Fo
TOll
Tft

15pfload
15pfioad
15pfioad @ 50%
From 25 to 85 MHz
From 14 to 20 MHz
From 14 to Below
From 25 to 85 MHz
From 14 to 20 MHz
From 14 to Below

-

40.0

-250.0
-500.0
13.3
2.0

-

8t066.6MHz

1.0
14.3

7.58
6.0

Ordering Information
ICS9108-05CN8, ICS9108-05CS8j ICS91 08-1 OCN8, ICS91808-1 OCS8j
ICS9108-03CN14, ICS9108-03CS14j ICS91 08-11 CN14, ICS9108-11CS14

11

xxx XXXX -XX

M x#w

L

L~ eo.m & ....... ffidlli

Lead Count= 1, 2 or 3 digits
W=.3" SOIC or .6" DIP; None=Standard Width

Package Type
N=DIP (Elastic); S=SOIC

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
L....._ _ _ _ _ _ _ Device Type (consists of 3 or 4 digit numbers)
'-----------Prefix
ICS, AV=Standard Device; GSP=Genlock Device

C-34

J.lA

."

Parameter is guaranteed by design and characterization.

Example:

V
V
rnA
rnA
rnA

-

AC CluiradqristiCs '.
Rise Time 20% to 80%, Note I
Fall Time 80% to 20%
Duty Cycle
Jitter, One Sigma
Jitter, One Sigma
Jitter, One Sigma
Jitter, Absolute
Jitter, Absolute
Jitter, Absolute
Input Frequency
Output Frequency
Power-up Time, Note 1
Transition Time, Note 1

IlA

ns
ns
%
ps
ps
%
ps
ps
%
MHz
MHz
ms

ms

II

ICS9120-08
ICS9120-09
Product Preview

Integrated
Circuit
Systems, Inc.

Frequency Generator for Multimedia Audio Synthesis
General Description

Features

The ICS9120-08 and ICS9120-09 are high performance frequency generators designed to support stereo audio codec
systems. They offer both clock frequencies required by stereo
codecs such as the CS4231 and the ADI848 plus the clock
needed for the OPL4 FM synthesizer. These frequencies can
be synthesized from the existing 14.318 MHz system clock
or from the on-chip oscillator using a 14.318 MHz crystal
(-08 only).

•

High accuracy, low jitter PLLs meet the 0.10% frequency
tolerance and -96dB signal-to-noise ratios required by 16-bit
audio systems. Fast output clock edge rates minimize board
induced jitter.
Unlike competitive devices, the ICS9120-08 and ICS9120-09
operate over the entire 3.0-S.SV range, with the -09 providing
power-down to minimize energy consumption.

•
•
•
•
•
•
•
•

Generates 16.9344 MHz and 24.S76 MHz stereo codec
clocks plus the 33.868 MHz OPL4 clock
Single 14.318 MHz crystal or system clock reference
Buffered REFCLK output
0.10% frequency accuracy meets OPL4 specifications
8Sps one sigma jitter maintains 16-bit performance
Output rise/fall times less than 2.0ns
On-chip loop filter components
3.3V-SV supply range
8-pin, ISO-mil SOlC

Applications
•

Specifically designed to support the high performance
requirements of multimedia audio systems

Block Diagram

----------,

l--r-- x1

T•

XTALOSC~----~

~ X2 (-08) ---t~-L

___J

+

External
Crystal
PD (-09)--••~1
Load Caps

"'>--"'-14.3 MHz

>--.....-24.6 MHz
PLL
CLOCK

">--.....-33.9 MHz

GEN

">-...-16.9 MHz
L

__________

IICS9120RevAll2294

C-3S

_

II

II

ICS9120-08
ICS9120-09
Pin Configuration
X1

1

VDD

2

GND

3

~!
....
en en

Functionality (ICS9120-08, ICS9120-09)
8

X2 (PO)(09)

7

14.3 MHz

6

33.9 MHz

5

24.6 MHz

VDD=3 0-5 5Y. TEMP=O-70°C
Xl,X2 (-09 only)
33.9
16.9
(MHz)
(MHz) (MHz)
PD\
14.318

0
1

Low
33.868

Low
16.934

24.6
(MHz)

14.3
(MHz)

Low
24.576

Low
14.318

NN

1/)1/)

~H~

16.9 MHz

4

Note: PD (Pin 8) is internally pulled-up to VDD and therefore
may be left disconnected or driven by open collector logic.

a-Pin sOle
K-6

Pin Descriptions for ICS9120-08
PIN
NUMBER
1
2
3
4
5
6
7
8

PIN
NAME
Xl
VDD
GND
CLK3
CLKI
CLK2
REF
X2

TYPE
Input
Power
Power
Output
Output
Output
Output
Output

DESCRIPTION
Crystal or external clock source
+Power supply input
Ground return for Pin 2
16.9 MHz clock o~ut
24.6 MHz clock output
33.9 MHz clock o~ut
14.318 MHz reference clock output
Crystal output drive

Pin Descriptions for ICS9120-09
PIN
NUMBER
1
2
3
4
5
6
7
8

PIN
NAME
Xl
VDD
GND
CLK3
CLKI
CLK2
REF

'Pi'5

TYPE
Input
Power
Power
Output
Output
Output
Output
Input

DESCRIPTION
Crystal or external clock source
+Power supply il!I'llt
Ground return for Pin 2
16.9 MHz clock output
24.6 MHz clock output
33.9 MHz clock output
14.318 MHz reference clock output
Power-down input powers down entire device when low' has pull-up

C-36

ICS9120-08
ICS9120-09
Absolute Maximum Ratings
A VDD, VDD referenced to GND ...............
Operating temperature under bias ...............
Storage temperature ..........................
Voltage on I/O pins referenced to GND ...........
Power dissipation ............................

7V
O°C to + 70°C
-65°C to + 150°C
GND -0.5V to VDD +0.5V
0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics at 5V
Operating VDD = +4.5V to +5.5V; TA =O°C to 70°C unless otherwise stated

DC Characteristics
PARAMETER

SYMBOL

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Supply Current
Supply Current
Pull-up Resistor Value

VIL
VIR
IlL
IIR
VOL*
VOH*
IOL*
IOH*

TEST CONDITIONS

Icc
Icc

VIN=OV (For -09 only)
VIN=VDD (For -09 only)
IOL=+IOmA
IOH=-30rnA
VOL=0.8V
VOH=2.4V
Unloaded
Unloaded (For -09 only)

Rpu*

(For -09 only)

Rise Time 0.8 to 2.0V
Fall Time 2.0 to 0.8V
Rise Time 20% to 80%
Fall Time 80% to 20%
Duty Cycle

Tr*
Tf*
Tr*
Tf*
Dt*

Duty Cycle

Dt*

Jitter, One Sigma

TjlS*

Jitter, Absolute

Tjab

Jitter, One Sigma
Jitter, Absolute
Input Frequency
Output Frequency
Power-up Time
Crystal Input Capacitance

T IS*

15pfload
l5pfload
15pfload
l5pfload
l5pf load @ 50% of VDD;
Except REFCLK
l5pf load @ 50% of VDD;
REFCLKonly
For all frequencies except
REFCLK
For all frequencies except
REFCLK
REFCLKonly
REFCLKonly

~~--

MIN

TYP

MAX

UNITS

-

-

0.8

2.0

-

-

V
V

-

-8.3

-18.0

-

5.0
0.4

!J.A
!J.A
V
V
rnA
rnA
rnA

0.15
3.7
45.0
-53.0
22.0
180.0
400.0

-35.0
50.0
500.0
800.0

!J.A
kohm

45.0

0.9
0.7
1.8
1.4
50.0

2.0
1.5
3.25
2.5
55.0

ns
ns
ns
ns
%

40.0

50.0

60.0

%

-

85.0

-

ps

-700.0

380.0

700.0

ps

-

266.0
380.0
14.0

600.0
1.5
17.0
42.0
12.0

ps
ns
MHz
MHz
ms
pf

2.4
25.0

-

-

-

AC Characteristics

TJab
Fl*
Fo*
Tpu*
Cinx*

Oto 33.8 MHz
Xl (Pin 1),
X2 (Pin 8; -08 only)

* Parameter guaranteed by design and characterization. Not 100% tested in production.
C-37

-

-1.5
11.0
11.0

-

5.5
5

-

Ii

ICS9120-08
ICS9120-09
Electrical Characteristics at 3.3V
Operating VDD = +3.0V to +3.7V; TA =O°C to 70°C unless otherwise stated

DC Characteristics
PARAMETER

SYMBOL

Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Supply Current
Supply Current
Pull-up Resistor Value

VIL
VIH
IlL
IIH
VOL*
VOH*
IOL*
IOH*
Icc
Icc(PD)
Rpu*

Rise Time O.S to 2.OV
Fall Time 2.0 to O.SV
Rise Time 20% to SO%
Fall Time SO% to 20%
Duty Cycle

Tr*
Tr*
Tr*
Dt*

Duty Cycle

Dt*

Jitter, One Sigma

TJis*

Jitter, Absolute

TJab

Jitter, One Sigma
Jitter, Absolute
Input Frequency
Output Frequency
Power-up Time
Crystal Input Capacitance

TlS*
Tab
Fi*
Fo*
Tpu*
Cinx*

MIN

TYP

MAX

UNITS

-

0.2VDD

0.7VDD

-

V
V

-

-3.6

-

-

-

0.05VDD
0.94VDD
24.0
-13.0
13.0
50.0
620.0

-S.O
5.0
0.1

TEST CONDITIONS

VIN=OV (For -09 only)
VIN=VDD (For -09 only)
IOL=6mA
IOH=-4.0mA
VOL=0.2VDD
VOH=0.7VDD
Unloaded
Unloaded (For -09 onb'l
(For -09 only)

0.S5VDD
15.0

-

-

-

IlA
IlA
V
V
rnA
rnA
rnA

-S.O
32.0
110.0
900.0

IlA
kohm

45.0

1.5
1.0
2.2
1.5
50.0

4.0
3.0
4.0
3.0
55.0

ns
ns
ns
ns
%

40.0

45.0

60.0

%

-

100.0

-

ps

-900.0

3S0.0

900.0

ps

-

266.0
3S0.0
14.3

600.0
1.5
15.0
3S.0
12.0

ps
ns
MHz
MHz
ms
pf

-

-

-~,--

AC Ckaracterlstl£s

Tr*

15pfload
15Qfload
15pfload
15pfload
15pfload @ 50% ofVDD;
Except REFCLK
15pfload @ 50% ofVDD;
REFCLKonly
For all frequencies except
REFCLK
For all frequencies except
REFCLK
REFCLKonly
REFCLKonly

Oto 33.S MHz
Xl (Pin I),
X2 (Pin S; -OS only)

* Parameter guaranteed by design and characterization. Not 100% tested in production.

C·38

-

-

-1.5
11.0
11.0

-

-

5.5
5

-

II

ICS9120-08
ICS9120-09

Ordering Information
ICS9120M-08, ICS9120M-09
Example:

xxx

XXXX M-PPP

I

TI

.......

_ ( 2 M 3 _ _.... 'M _ _ ROMmd..........'
Package 1Ype
M=SOIC

Device 'JYpe (consists of 3 or 4 digit numbers)

L------------------Pnfix
ICS, AV=Standard DeVIce; GSP=Genlock DevIce

~~~l~fJ:v~I~~~~t~h~r:c:r,~~~~t~n~nd~~~r ~~~~f~~~~ t~~fd~~~~g~~e~~~
reserves the nght to change or discontinue these products Without notice

C-39

C-40

ICS9131

Integrated
Circuit
Systems, Inc.

•

Advance Information

32 kHz Motherboard Frequency Generator
General Description

Features

The ICS9131 offers a tiny footprint solution for generating a
selectable CPU clock from a 32.768 kHz crystal. The device
allows a variety of microprocessors to be clocked by changing
the state of address lines FSO, FS1, and FS2. The ICS9131 is
the ideal solution for replacing high speed oscillators and for
reducing clock speeds to save power in computers. The device
provides smooth, glitch-free frequency transitions so that the
CPU can continue to operate during slow down or speed up.
The rate of frequency change makes the ICS9131 compatible
with all 386DX, 386SX, 486DX, 486DXZ, 486SX and Pentium™ microprocessors.

•

The ICS9131 is driven from a single 32.768 kHz crystal. The
only external components required are the crystal and a
10M ohm resistor. The device generates the 14.318 MHz system clock, eliminating the need for a 14.318 MHz crystal.
High-Performance applications may require high speed clock
termination components.

VDD32 Supply
The ICS9131 has a separate power supply for the 32.768 kHz
oscillator circuitry. This allows the 32 kHz clock to run from a
battery or other source while the main power to the chip is
disconnected. The VDD32 supply is guaranteed to operate
down to +2.0V, with the clock consuming less than 10IlA at
+3.3V and the main VDD at Ov.

•
•
•
•
•
•
•
•

Single 32.768 kHz crystal generates system clock and
selectable CPU clock
Generates CPU clocks from 8 MHz to 100 MHz.
Operates from 3.3V or 5.0V supply
Operates up to 66 MHz at 3.3V
Separate VDD for 32 kHz clock enables it to run from
battery
STOPCLK feature allows for a glitch-free on and tum-off
of the CPU clock to static processors
Output enable tristates outputs
16-pin POlP or sorc package
Frequency selects allow for a smooth transition of the
CPUCLK

Applications
NotebooklPalmtop Computers: The ICS9131 works with + 3V
and +5V and a single 32.768 kHz crystal, making it the ideal
solution for generating clocks in portables with minimum
board space. The user can save power by using this single part
instead of oscillators or other frequency generators. The
ICS9131 further reduces the current consumption by having
the ability to completely shut down the individual clocks when
not in use, while still maintaining the separately powered
32.768 kHz clock.

The frequencies and power-down options in the ICS9131 are
mask programmable. Customer specific masks can be made
and prototypes delivered within 6-8 weeks from receipt of
order. rcs also offers standard versions, such as those described in this data sheet.

Block Diagram
32.768 kHz c
crystal
32.768 kHz
crystal

14.318MHz

"""'l"-........_ _ _...

DE

t----. CPUCLK
FS[O:2] _ _ _ _ _ _ _ _....1

Pentium

IS

1....._ _ _ _ _ _

a trademark of Intel

IIcs9131 RevB092794

C-41

STOPCLK

II

ICS9131

Decoding Table for CPU Clock

Pin Configuration
32kHz

FSO

X2

FS1

X1

CPUCLK

VDD32

VCC
ICS9131

VCC
VSS

VSS

FS2

FSI

FSO

CPUCLK

ACTUALS

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

16
25
33.3
40
50
60
66.6
80

16.004
25.059
33.412
40.095
50.119
60.142
66.484
80.190

STOPCLK
REFCLK

AGND
OE

FS2
16-Pln PDIP or SOIC

K-4, K·&

Pin Descriptions
PIN NUMBER

PIN NAME

TYPE

1

32kHz

OUTPUT

DESCRIPTION
32.768 kHz output

2

X2

OUTPUT

Connect 32 kHz crystal

3

Xl

INPUT

Connect 32 kHz crystal

4

VDD32

Power Supply for 32 kHz oscillator

5

VCC

Power Supply (+3.3V - 5.0V)

6

VSS

Ground

7

AGND

Analog Ground

g

OE

INPUT

OE tristates outputs when low

9

FS2

INPUT

CPU clock frequency select 2

10

REFCLK

11
12

STOPCLK
VSS

Ground

13

VCC

Power supply (+3.3V - 5.0V)

14

CPUCLK

15

FSI

INPUT

CPU clock frequency select 1

16

FSO

INPUT

CPU clock frequency select 0

OUTPUT
INPUT

OUTPUT

14.318 MHz output
Stops CPU clock when low

CPU clock output (see Decoding table)

C-42

ICS9131
Recommended External Circuit

Notes:
1) The external components shown should be placed as close to the device as possible.
2) Pins 5 and 13 should be connected together externally. One decoupling capacitor may suffice for both pins.

C-43

ICS9131
Absolute Maximum Ratings
VDD referenced to GND ...................... 7V
Operating temperature under bias ............... O°C to +70°C
Storage temperature .......................... -40°C to + 150°C
Voltage on lJO pins referenced to GND ........... GND -0.5V to VDD+0.5V
Power dissipation ............................ 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics at 5V
Operating VDD = +4.5V to +5.5V; TA =O°C to 70°C unless otherwise stated

.

'

DC Cbaracteristk$

"

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Input Low Voltage

VlL

-

-

0.8

V

Input High Voltage

Vrn

2.0

-

-

V

Input Low Current

IlL

VlN=OV

-

6.0

15.0

JlA

Input High Current

Irn

VIN=VDD

-2.0

-

2.0

JlA

Pull-up Resistor

Rpu

VlN=VDD-IV, Note I

-

400

700

kohms

Output Low Current

IOL

VOUT=0.8V, Note I

25

45

-

rnA

Output High Current

IOH

VOUT=2.0V, Note I

-

-53

-35

rnA

Output Low Voltage

VOL

IOL=lOrnA

-

0.15

0.4

V

Output High Voltage

VOH

IOH=-30rnA, Note I

2.4

3.7

-

V

Supply Current

IDD

No load, at 50 MHz

-

18

35

rnA

With respect to typical
frequency, Note 1

-

0.002

0.05

%

-

12

25

JlA

Output Frequency Change
over Supply and Temperature
Standby Supply Current

Fd

IDDSTDBY Note 2, unloaded

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Note 2: With the STOPCLK pin low (active).
Note 3: Absolute Jitter measured as the shortest and longest period difference to the mean period of the sample set.

C-44

ICS9131
Electrical Characteristics at

sv

Operating Voo =+4.5V to +5.5V; TA =O°C to 70°C unless otherwise stated

ACCharaeteristies
Output Frequency

fo

Clockl, Note I

Input Frequency

fi

Note I

Output Rise time, O.S to 2.0V

tr

15 pf load, Note I

Rise time, 20% to SO% Voo

tr

15 pfload, Note I

c

12.0

-

100

MHz

2.0

32

3S

kHz

0.60

1.4

ns

1.6

3.0

ns

Output Fall time, 2.0V to O.SV

tf

15 pfload, Note I

Fall time, SO% to 20% Voo

tf

15 pf load, Note 1

-

Duty cycle

dt

15 pf load, Note 1

45

50

55

%

-

50

150

ps

-250

-

250

ps

60

150

ps

1.2

ns

0.9

2.5

ns

Jitter, I sigma from
33-S0 MHz

Tjis

Jitter, Absolute from
33-S0MHz

Tjabs

Jitter, 1 sigma from
16-25 MHz

TJis

Jitter, Absolute from
16-25 MHz

Tjabs

-600

-

600

ps

Jitter, 1 sigma from
14 to below

TJ,s

-

1

3

%

Jitter, Absolute from
14 to below

Tjabs

-

2%

5

%

2.0

5.0

10.0

mS

3.0

7.5

15

mS

Frequency Transition time

tft

Power-up time

tpu

10,000 samples, Note 1

0.50

10,000 samples, Notes 1,3

Note 1

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Note 2: With the STOPCLK pin low (active).
Note 3: Absolute Jitter measured as the shortest and longest period difference to the mean period of the sample set.

C-45

ICS9131
Electrical Characteristics at 3.3V
oJperatinjl; v00 = + . to+ . ; A- to
un ess 0 therwlse stated
..

. .:
,

:

,

'

"

,

".

,l

"

n.¢~ ..
'

..

..

',:'.

.>. , ' .

,«

"

MIN

TYP

MAX

UNITS

Input Low Voltage

VIL

-

-

0.2Vdd

V

Input High Voltage

Vm

0.7Vdd

-

-

V

Input Low Current

IlL

VIN=OV

-

2.5

7.0

Input High Current

1m

VIN=Voo

-2.0

-

2.0

J.LA
J.LA

Pull-up Resistor

Rpu

VIN=Voo-lY, Note 1

-

600

IOL

Vour=0.2V, Note I

15

24

Output High Current

IOH

VOUT=D.7V, Note 1

-

-13

900
-8

kohms

Output Low Current
Output Low Voltage

VOL

IOL=60rnA

-

0.05 Vdd

0.1 Vdd

V

Output High Voltage

VOH

IOH=-4.0rnA, Note 1

6.85Vdd

0.94 Vdd

-

V

Supply Current

100

No load, at 50 MHz

-

13

25

rnA

With respect to typical
frequency, Note 1

-

0.002

0.05

%

-

8

PARAMETER

Output Frequency Change
over Supply and Temperature
Standby Supply Current

SYMBOL

Fd

IOOSTDBY Note 2, No load
fo
f,

rnA
rnA

15
;

kC Cbiimcterlsdcs

p

Output Frequency

TEST CONDmONS

,

;

Clockl, Note 1

12.0

Note 1

-

'

rnA
'.
"

"

100

MHz

2.0

32

38

kHz

15 pfload, Note 1

-

2.2

3.5

ns

Fall time, 80% to 20% Voo

tr
tf

15 pfload, Note 1

-

1.2

2.5

ns

Duty cycle

dt

15 pfload, Note 1

43

-

53

%

-

50

150

ps

Input Frequency
Rise time, 20% to 80% Voo

Jitter, 1 sigma

Tjis

10,000 samples, Note 1

Jitter, Absolute

Tjabs

10,000 samples, Notes 1, 3

250

ps

Jitter, 1 sigma from
16-25 MHz

Tjis

-

60

150

ps

Jitter, Absolute from
16-25 MHz

Tjabs

-600

-

600

ps

Jitter, 1 sigma from
14 to below

Tjis

-

1

3

%

Jitter, Absolute from
14 to below

Tjabs

-

2

5

%

6.7

14.0

mS

-

8.55

17.0

mS

Frequency Transition time

tft

Power-up time

tpu

Note 1

-250

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Note 2: With the STOPCLK pin low (active).
Note 3: Absolute Jitter measured as the shortest and longest period difference to the mean period of the sample set.

C-46

"•

II

ICS9131

Stop Clock Feature
The ICS9131 incorporates a unique stop clock feature compatible with static logic processors. When the stop clock pin goes
low, the CPUCLK will go low after the next occuring falling
edge. When STOPCLK again goes high, CPUCLK resumes on
the next rising edge of the internal clock. This feature enables
fast, glitch-free starts and stops of the CPUCLK and is useful
in Energy Star motherboard applications.

E

CPUCLK
STOPC

32 kHz Supply Current
14

c.. =2SpF
c.. == ISpF
c.. =OpF

12
10
JlA

8

}
(pin 1)

6
4

2

o

o

1

2

4

3

5

6

Vdd
(pin 4)

Ordering Information
ICS9131 N16 or ICS9131 M16
Example:

ICSXXXXM

L __ _
N=DIP (f1astic)
M=SOIC

' - - - - - - - - Device 'JYpe (consists of 3 or 4 digit numbers)

'-----------Preflx
rcs, AV=Standard Device; GSP=Genlock Device
ADVANCE INFORMATION documents contain Information on new products In the sampling
or preproducbon phase of development CharactenstlC data and other speclflcatlons are
subject to change Without notICe

C-47

C·48

ICS9133X

Integrated
Circuit
Systems, Inc.

Advance Information

32 kHz Motherboard Frequency Generator
General Description

Features

The ICS9133X is designed to generate clocks for all 286, 386,
486, Pentium and RISC-based motherboards, including laptops and notebook computers. The only external components
required are a 32.768 kHz crystal and decoupling capacitors.
The device generates the 14.318 MHz system clock, eliminating the need for a 14.318 MHz crystal. High performance
applications may require high speed clock termination components. The chip includes three independent clock generators
plus the 32.768 kHz reference clock to produce all necessary
frequencies, including real time clocklDRAM refresh, master
clock, CPU clock, twice CPU clock frequency, keyboard
clock, floppy disk controller clock, serial communications
clock and bus clocks. Different frequencies from clocks #2 and
#3 can be selected using the frequency select pins, but clock
#1 will be at 14.318 MHz for all standard versions.

•
•
•
•
•
•
•
•
•

•
•
•

Single 32.768 kHz crystal generates all PC motherboard
clocks
Cost-reduced version of popular ICS9132
3 independent clock generators
Generates CPU clocks from 12.5 to 100 MHz
Up to 7 output clocks
Separate VDD for 32 kHz clock
Output enable tristates outputs
Power-down options available
Operates from 3.3V or 5.0V supply
Operates up to 66 MHz at 3.3V
Skew controlled 2x and 2x CPU clocks
20-pin PDIP or SOIC package

VDD32 Supply

Applications

The ICS9133X has a separate power supply for the 32.768 kHz
oscillator circuitry. This allows the 32 kHz clock to run from a
battery or other source while the main power to the chip is
disconnected. The VDD32 supply is guaranteed to operate
down to +2.0V, with the clock consuming less than lOll-A at
+3.3V with the main VDD at OV.

NotebookIPalmtop Computers: The ICS9133X works with
+3V and +5V and a single 32.768 kHz crystal, making it the
ideal solution for generating clocks in portables with minimum
board space. The user can save power by using this single part
instead of oscillators or other frequency generators. The
ICS9133X further reduces the current consumption by having
the ability to completely shut down the individual clocks when
not in use, while still maintaining the separately powered
32.768 kHz clock.

The frequencies and power-down options in the ICS9133X are
mask programmable. Customer specific masks can be made
and prototypes delivered within 6-8 weeks from receipt of
order. Integrated Circuit Systems also offers standard versions,
such as that described in this data sheet.

Block Diagram
32.768 kHz
crystal
32.768 kHz

{:

...

+

I

Clock
Generator

Reference
Clock

..
~

1

..

.J

14.318 MHz ......

r

Ilcs9133XRevA092794

C·49

Clock
Generator
2

Clock
Generator
3

.... CPUCLK

~

....
-~

...

~

2XCPUCLK

Peripheral
Clocks

E

II

ICS9133X
Pin Configuration

Decoding Table for CPU Clock

32 kHz

SCLKO

X2

2

19

SCLK1

X1

3

18

SCLK2

17

CPU

16

2XCPU

VDD32

4

VDD

5

GND

6

16MHz

7

24 MHz

><
,...
0)
en
('I)
('I)

15

VDD

14

GND

8

13

14.318 MHz

12MHz

9

12

VDD (VCCA)

GND

10

11

OE

20-Pin PDIP or
K-4, K-7

sOle

~

SCLK22

SCLK21

SCLK20

2XCPU

CPU

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

8
16
32
40
50
66.6
80*
100*

4
8
16
20
25
33.3
40*
50*

* Only at 5V supply voltage

Pin Descriptions
PIN NUMBER

PIN NAME

I

32kHz

2

X2
Xl

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

19
20

VDD32
VDD
GND
16 MHz
24 MHz
12 MHz
GND
OE
VDD
14.318 MHz
GND
VDD
2XCPU
CPU
SCLK2
SCLKI
SCLKO

TYPE

DESCRIPTION

Output
Output

32.768 kHz output
Connect 32 kHz crystal

Input

Connect 32 kHz crystal

Output
Output
Output
Input

-

Power supply for 32 kHz oscillator only
Power supply (+3.3 to +5.0V)
GROUND
16 MHz clock output
24 MHz clock output
12 MHz clock output
GROUND
OE tristate outputs when low. Has internal pull-up.
Power supply (+3.3 to +5.0V)
14.318 MHz clock output

Output
Output

GROUND
Power supply (+3.3 to +5.0V)
2XCPU clock output (see decoding table)

Output
Input
Input

CPU clock output (see decoding table)
CPU clock frequency SELECT2. Has internal pull-up.
CPU clock frequency SELECT!. Has internal pull-up.

Input

CPU clock frequency SELECTO. Has internal pull-up.

c·so

II

ICS9133X

Block Diagram for ICS9133X
32.768 kHz
crystal
32.768 kHz

Reference
Clock

..-+---- Frequency Select
Output
Buffers

14.318 MHz
Clock

2XCPU

L..G_e_n_er_a_to_r.J----t----i~1 CPU Clock

CPU
14.318 ~------------------~--------------------.-------OE
MHz
16MHz
12MHz
24 MHz

Peripheral
Clocks

Recommended External Circuit

VDDX------~~r-~

0.1#

NOTES:
I.
2.
3.

The external components shown should be placed as close to the device as possible.
Pins 5 and IS should be connected together externally. One decoupling capacitor may suffice for both pins.
May be part of system decoupling.

C·Sl

II

ICS9133X
Absolute Maximum Ratings
VDD referenced to GND ...................... 7V
Operating temperature under bias ............... O°C to + 70°C
Storage temperature .......................... -40°C to150°C
Voltage on 110 pins referenced to GND ........... GND -O.5V to VDD +0.5V
Power dissipation ............................ 0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics
VIDD=+ 3 .0 to 3 7V T.A=O°C to 70°C un ess otherWlse state d

DC Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

Input Low Voltage
Input High Voltage
Input Low Current

VIL
VIH
IIL

VIN=OV (Pull-up)

Input High Current

IIH

VIN=VDD

Output Low Voltage
Output High Voltage
Output High Current
Output High Current
Output Frequency Change
over Supply and
Temperature
Short circuit current
Supply Current
Pull-up resistor value

VOL
VOH
VOH
VOH
FD

Isc
Icc
Rpu

IOL=4mA
IOH=-lmA
IOH=-4mA
IOH=-8rnA
With respect to typical
frequencyl
Each output clock
No load, 40 MHz

MIN

TYP

MAX

UNITS

0.7VDD

-

V
V

-

-

0.2VDD
12

-

2*

VDD-.IV

-

.005

0.1
0.05

-

15
10
620

-

-

2.4

-

-

IlA
j.tA
V
V
V
V
%

rnA
rnA
kQ

AC Characteristics
Input Clock Rise Time

tICr

-

-

5

Its

Input Clock Fall Time

tIcf

-

-

5

-

43/57
40/60
25
-

1.5
2.5
1.5
2.5
48/52
43/57
I
2
32.768
100

2
4
2
4
57143
60/40
3
5
40
500

IlS
ns
ns
ns
ns
%
%
%
%
kHz
ps

-

1,000

-

ms

Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% VDD
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Input Frequency
Clock skew between any
Clock #2 outputs
Power-up time

tr
tf
tf

tr
dt
dt
tab

15 pfload
15 pfload
15 pfload
15 pf load
15 pfload
15 pfload, Note I
As compared with
clock period.

fi
Tsk
tpu

From off to 40 MHz

NOTE I: 32 kHz output duty cycle is dependent on crystal used.

C·S2

-

-

II

ICS9133X

Electrical Characteristics
VDD - +5V+1O% TA-O°C
to 70°C unless otherwise stated
-

DC Characteristics
PARAMETER

SYMBOL

Input Low Voltage
Input High Voltage
Input Low Current

VIL
VIH
IlL

Input High Current

IIH

Output Low Voltage
Output High Voltage
Output High Voltage
Output High Voltage
Output Frequency Change over
Supply and Temperature
Short circuit current
Supply Current
Pull-up resistor value

VOL
VOH
VOH
VOH
FD
Isc
Icc
Rpu

TEST CONDITIONS

MIN

TYP

MAX

UNITS

-

-

0.7VDD

-

V
V

VIN=OV (Pull-up)

-

-

0.2VDD
15

VIN=VDD

-

-

2*

VDD-.IV
2.4

-

0.1
-

-

-

-

.005

0.05

-

-

rnA
rnA

-

33
17
380

-

ill

IOL=4mA
IOH=-lmA
IOH=-4rnA
IOH=-8rnA
With respect to typical
frequency
Each output clock
No load, 40 MHz
Note 1

-

-

IlA
IlA
V
V
V
V
%

AC Charac:teristics
Input Clock Rise Time

tlCr

-

-

5

IlS

Input Clock Fall Time

tICf

-

-

5

-

-

1
2
1
2
48/52
43/57
I
2
32.768
100

1.5
3
1.5
3
57/43
60/40
3
5
40
500

Il s
ns
ns
ns
ns
%
%
%
%
kHz
ps

-

10

-

ms

Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% VDD
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Duty cycle
Duty cycle, reference clocks
Jitter, one sigma
Jitter, absolute
Input Frequency
Clock skew between any
Clock #2 outputs
Power-up time

tr
tr
tf
If
dt
dt
tjIs
tab
fi
Tsk
tou

15 pfload
15 pfload
15 pfload
15 pfload
15 pfload
15 pfioad, Note I
As compared with clock
period

43/57
40/60

25

From off to 40 MHz

NOTE 1: 32 kHz output duty cycle is dependent on crystal used.

C-53

E

ICS9133X
32 kHz Supply Current
14
12
10

c.. -2SpF
c.. = lSpF
c.. =OpF

J.LA8
6
4
2

o

o

1

2

3

4

Vdd

Ordering Information
ICS9133XN20 (DIP) or ICS9133XM20 (SOIC)
Example:

ICSXXXX M

L~_

N=DIP (I'lastic)
M=SOIC

" - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - Prefix
ICS=Standard Device

C·S4

5

6

ICS9134-06
ICS9134-07

Integrated
Circuit
Systems, Inc.

Advance Information

32 kHz Motherboard Frequency Generator
General Description

Features

The ICS9134-06 and ICS9134-07 are designed to generate
clocks for all 286, 386, 486, Pentium and RISC-based motherboards, including laptops and notebook computers. The only
external components required are a 32.768 kHz crystal and
decoupling capacitors. The device generates the 14.318 MHz
system clock, eliminating the need for a 14.318 MHz crystal.
High performance applications may require high speed clock
termination components. The chip includes three independent
clock generators plus the 32.768 kHz reference clock to produce all necessary frequencies, including real time
clockIDRAM refresh, master clock, CPU clock, keyboard
clock, floppy disk controller clock, serial communications
clock and bus clocks. Different frequencies from clocks #2 can
be selected using the frequency select pins, but clock #1 will
be at 14.318 MHz for all standard versions.

•
•

VDD32 Supply
The ICS9134-06 and ICS9134-07 have a separate power
supply for the 32.768 kHz oscillator circuitry. This allows the
32 kHz clock to run from a battery or other source while the
main power to the chip is disconnected. The VDD32 supply is
guaranteed to operate down to +2.0V, with the clock consuming
less than IOfJA at +3.3V with the main VDD at Ov.
The frequencies and power-down options in the ICS9134-06
and ICS9134-07 are mask programmable. Customer specific
masks can be made and prototypes delivered within 6-8 weeks
from receipt of order. Integrated Circuit Systems also offers
standard versions, such as that described in this data sheet.

•
•
•
•
•
•
•
•
•

<10 IlA when 32 kHz is running
Single 32.768 kHz crystal generates all PC motherboard
clocks
3 independent clock generators
Generates CPU clocks from 4.0 to 80 MHz
Up to 5 output clocks
Separate VDD for 32 kHz clock
Power-down options available
Operates from 3.3V or 5.0V supply
Operates up to 66 MHz at 3.3V
Supports OPTi 8OC463/5 and FirTM chipsets
16-pin, 300 mil, SOIC package
IDD

Applications
Notebook/Palmtop Computers: The ICS9134-06 and
ICS9134-07 work with +3.3V and +5V and a single 32.768
kHz crystal, making it the ideal solution for generating clocks
in portables with minimum board space. The user can save
power by using this single part instead of oscillators or other
frequency generators. The ICS9134-06 and ICS9134-07 further reduce the current consumption by having the ability to
completely shutdown the individual clocks when not in use, while
still maintaining the separately powered 32.768 kHz clock.

Block Diagram
VDD32

32.788 kHz

CLOCK
CLOCK
GENERATOR 1-"""4........... GENERATOR

crystal

1

32.768 kHz

1--+ CPUCLK

2

14.318 MHz
CLOCK
'--....... GENERATOR
3
IICS9134-06RevB092794

PERIPHERAL
CLOCKS
Fir

C-ss

IS

a trademark of Plcopower Corporation

E

II

ICS9134-06
ICS9134-07

Decoding Table for CPU Clock

Pin Configuration
CPUS2

16

CPUS1

X2

2

15

CPUSO

X1

3

14

CPUCLK

VDD32

4

VDD

5

CDr-.

0
0
I
I
'1:1"'1:1"

13

CPUS2

CPUSI

CPUSO

CPUCLK (MHz)

0

0

0

Off+14M off

0

0

I

80.00

0

I

0

25.00

I

I

66.66

0

1

VDD

I

0

0

20.00

I

0

I

50.00

MM
,...
,... 12

GND

I

1

0

33.33

OOOO

11

14.3M

I

I

1

4.00

PD24+KDB*

CJ)CJ)

GND

6

24M

7

10

32K

8

9

gg

--

ICS9134 Option

KBOUT

KEYBOARD CLOCK

-06

KBOUT

16 MHz

16-Pin sOle
K-6

Pin Descriptions
PIN NUMBER

PIN NAME

DESCRIPTION

TYPE

1

CPUS2

I

Select 2 for 2XCPU and CPU frequencies. See Table above.

2

X2

0

Crystal connection. Connect to 32.768 kHz crystal.

3

Xl

I

Crystal connection. Connect to 32.768 kHz crystal.

4

VDD32

P

Separate power supply connection for 32.768 kHz clock. Will operate
to 2.0y'

5

VDD

P

Connect to +3.3V or +5Y.

6

GND

P

Connect to ground.

7

24M

0

24 MHz floppy (or super 110) clock output.

8

32K

0

32.768 kHz square wave clock output.

9

KBOUT

0

Keyboard clock output, fixed 16 MHz (-06) or 12 MHz (-07).

10

PD24+KBD*

I

Power-down 24M+keyboard. Shuts off both clock outputs, pins 7 & 9
when low.

11

14.3M

0

14.318 MHz system clock output.

12

GND

P

Connect to ground.

13

VDD

P

Connect to +3.3V or +5V.

14

CPUCLK

0

CPUCLK output. See Table above.

15

CPUSO

I

Select 0 for 2XCPU and CPU frequencies. See Table above.

16

CPUSI

I

Select I for 2XCPU and CPU frequencies. See Table above.

C-56

ICS9134-06
ICS9134-07
Absolute Maximum Ratings
VDD referenced to GND ......................
Operating temperature under bias ...............
Storage temperature ..........................
Voltage on I/O pins referenced to GND ... , .......
Power dissipation ............................

7V
O°C to 70°C
-40°C to + 150°C
GND -0.5V to VDD +0.5V
0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics
VDD - +3 0 to 3 7V TA-O°C
to 70°C unless otherwise stated
-

.

DC Charaeteristics .
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Input Low Voltage

VIL

-

-

0.2VDD

V

Input High Voltage

Vrn

0.7VDD

-

-

V

Input Low Current

IIL

VIN=OV

-

-7

-15

J..lA

Input High Current

IJH

VIN=VDD

-2

2

Output Low Voltage

VOL

Iov=6rnA, Note I

-

-

0.1

J..lA
V

Output High Voltage

VOH

IOH=-4rnA, Note I

0.S5VDD

0.9VDD

Output Low Current

IOL

VOL=O.2VDD, Note I

15

24

-

rnA

Output High Current

IOH

-

-13

-S

rnA

Supply Current

Icc
Icc

VOH=0.7VDD, Note I
No load @ 33 MHz

9

17

rnA

12

24

rnA

4.6

12

530

650

J..lA
kohm

VDD32 Supply Current

IDD32

No load

-

Pull-up Resistor Value

Rpu

Note 1

370

Supply Current

:>.

....,

.. ,

No load

,.

@

66.6 MHz

.Ac~.,

'.

.

'.

V

.

Rise Time O.S to 2.0V

tf

15pf load, Note I .

-

1.5

2

ns

Fall Time 2.0 to O.SV

tf

15 pfload, Note 1

-

1.5

2

ns

Rise to 20% to SO%

tf

15pfload, Note 1

2

2.5

3.5

ns

Fall Time SO% to 20%

tf

15pfload, Note 1

2

2.5

3.5

ns

40

50

55

%

-

I

2

%

2

5.5

%

25

32.76S

40

kHz

-

4

S

ms

-

4.S

ms

Duty Cycle

dt

15pf load, Note I

Jitter, One Sigma

tjis

As compared with
clock period. Note I

Jitter, Absolute

tjab

Input Frequency

fi

Power-up Time

tpu

Off to 33.3 MHz, Note I

Transition Time

tft

4 to 66.6 MHz, Note I

Note I

NOTE I: Parameter guaranteed by design and characterization. Not 100% tested in production.

C-S7

ICS9134-06
ICS9134-07
Electrical Characteristics
v~ to
un ess otherwlse stated

:'

,l':: ,':: ",: '?~;l;,":!:;: ;/\;;i',:·i,,; 'if;:;;";::,:~j:h::

:,!i ,::::,!;;~~;''::'';''f

MIN

TYP

MAX

UNITS

VIL

-

0.8

V

Input High Voltage

VIH

2

-

-

V

Input Low Current

IlL

VIN=OV

-

-10

-22

IlA

Input High Current

IIH

VIN=Voo

-2

-

2

Output Low Voltage

VOL

IOL=10rnA, Note 1

-

0.15

0.4

IlA
V

PARAMETER

SYMBOL

Input Low Voltage

TEST CONDITIONS

Output High Voltage

VOH

IOH=-30mA, Note 1

2.4

3.7

-

V

Output Low Current

IOL

VOL=0.8V, Note 1

25

45

-

rnA

Output High Current

IOH

VOH=2.0V, Note 1

-

-58

-35

rnA

Supply Current

Icc
Icc

No load

@

33 MHz

15

28

rnA

No load

@

80 MHz

Voo32 Supply Current

10032

No load

Pull-up Resistor Value

Note 1
:,",,',':;r!t:c3 ii 'Tf

Supply Current

;'/;i, '~';~Z~;'f

Rpu

ii'.",::,

,!

380

550

680

IlA
kohm

: ",:" ,;i\,;,,~HFi,!i

.;:<;

1.5

15 pf load, Note 1

1

1.5

ns

tr

15pf load, Note 1

-

2

3

ns

tf

15pfload, Note 1

-

2

3

ns

dt

15pfload, Note 1

48

52

58

%

tjis

As compared with
clock period. Note 1

-

1

2

%

2

5

%

25

32.768

40

kHz

-

7

14

ms

-

5

ms

tr
tf

Rise to 20% to 80%
Fall Time 80% to 20%

Input Frequency

rnA

20

1

Fall Time 2.0 to 0.8V

Jitter, Absolute

35

-

15pfload, Note 1

Jitter, One Sigma

22
7.5

,A.(::·~~~es, , "'Ii,

Rise Time 0.8 to 2.0V

Duty Cycle

-

tjab
fi

Note 1

Power-up Time

tpu

Off to 80 MHz, Note 1

Transition Time

tft

4 to 80 MHz, Note 1

NOTE 1: Parameter guaranteed by design and characterization. Not 100% tested in production.

C-58

ns

II

ICS9134-06
ICS9134-07

Recommended External Circuit
1
2
3
4
5
6

32.768 kHz D
crystal
VDD

O.1~F

*

VDD
2.2~F* O.1~F *
(Note 3)

16
15
14
co .....
00
13
~~
('1)('1)
.,....
.,.... 12
(7)(7)

Notes:

I

I

*

en en 11
S:H~

7

10
9

8

1)

The external components shown should be
placed as close to the device as possible.

2)

Pins 5 and 13 should be connected together
externally. One decoupling capacitor may
suffice for both pins.

3)

May be part of system decoupling.

O.1~F

32 kHz Supply Current
14
12

~

=25pF

10

Cr.

=

p.A

8
6

15pF

CL =OpF

4
2

o

o

1

2

3
Vdd

4

5

6

Ordering Information
ICS9134-06M or ICS9134-07M
Example:

ICS XXXX-PPP M

TI"

TC1

Package Type
M=SOIC

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
"
' - - - - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
L -_ _ _ _ _ _ _ _ _ Prer.x

rcs. AV=Standard Device; GSP=Genlock Device
ADVANCE INFORMATION documents contain mformatlon on new products In the sampling
or preproduction phase of development Charactenstlc data and other specifications are
sub ect to chan e without notice

C-S9

C-60

•

AV9154A

Integrated
Circuit
Systems, Inc.

Low-Cost 16-Pin Frequency Generator
General Description

Features

The AV915.4A is a 0.8J.l version of the industry leading
AV9154. Like the AV9154, the AV9154A is a low-cost frequency generator designed for general purpose PC and disk
drive applications. However, because the AV9154A uses 0.8!l
technology and the latest phase-locked loop architecture, it
offers performance advantages that enable the device to be sold
into Pentium™ systems.

•
•
•
•
•
•
•

The AV9154A guarantees a 45/55 duty cycle over all frequencies.
In addition, a worst case jitter of ±250ps is specified at Pentium
frequencies.

•
•
•
•

The CPU clock offers the unique feature of smooth, glitch-free
transitions from one frequency to the next, making this the
ideal device to use when slowing the CPU speed. The
AV9154A makes a gradual transition between frequencies so
that it obeys the Intel cycle-to-cycle timing specifications for
486 and Pentium systems.
The AV9154A .. 42 and AV9154A-43 devices offer features
specifically for green PCs. The AV9154A-42 and -43 have a
single pin that, when pulled low, will smoothly slow the
2XCPU clock to 8 MHz. This is ideal for dynamic DX
microprocessors. The AV9154A-43 not only has the slow
clock feature, but also offers a glitch-free stop clock for static
SX microprocessors. The STOPCLK pin, when pulled low,
enables the 2XCPU clock to go low only after completing its
last full cycle. The clock continues to run internally, and will
be output again on the first full cycle immediately following
stop clock disable.

Applications
Computer motherboards: The AV9154A replaces crystals and
oscillators, saving board space, component cost, part count and
inventory costs. It produces a switchable CPU clock and up to
four fixed clocks to drive floppy disk, communications, super
I/O, Bus, and/or keyboard devices. The small package and
3.3V operation is perfect for handheld computers.
For specific applications of AV9154A devices, consult the
following table:

The simultaneous 2X and IX CPU clocks offer controlled
skew to within 500ps of each other (-42 only).
ICS has been shipping motherboard frequency generators since
April 1990, and is the leader in the area of multiple output clocks
on a single chip. Consult ICS for all your clock generation needs.

Block Diagram

Compatible with 386, 486 and Pentium CPUs
45/55 Duty cycle
Runs up to 66 MHz at 3.3V
Single pin can slow clock to 8 MHz (on -42 and .. 43)
Single pin can stop the CPU clock glitch-free (on -43)
Very low jitter, ±25Ops for Pentium frequencies
IX and 2X CPU clocks skew controlled to ±250ps
(-42 only)
Smooth transitions between all CPU frequencies
Slow frequency ramp at power-on avoids CPU lock-up
16-pin PDIP or 150 mil skinny sorc packages
0.8J.l CMOS technology

DEVICE
AV9154A-27
AV9154A-42
AV9154A-43

...... __. . . ._._~[. . . . . Gr
[-43)-1
_+-__
-.f----1

SLOWCLK* [42. -43)---+.
STOPCLK*
FSO.2

APPLICATION
Pentium and 486 systems
Pentium and 486 systems
Dynamic green PC systems
Pentium and 486 systems
Dynamic or static green PC systems

Ar

D

.....................-..-......................................................- •.-.....-..-...-............,

...;3~(_ _ _
I

2XCPU

CPU
CLOCK

CPU [·42aiy)
KBCLK
FDCLK
COMMCLK [-27 aiy)

l.. . .___. . . . . . _. . _. . . . .__._. ___. _. .---.. . -.. . . . .-.. . . . . . . .-.. .-.----.---..·----r-······. ·. . · ·. · · ·
OE[·27aiy)

IAV9154ARevB092894

Pentium

C-61

IS

a trademark of Intel Corporation

E

II

AV9154A
Pin Configuration
1.84 MHz
X2

X1
VDD
GND
24 MHz
12MHz
AGND

2
3
4
5
6
7

.....
ClI

,..
==
1;(

II)

0)

8

16
15
14
13
12
11
10
9

FSO
FS1
2XCPUCLK
VDD
GND
14.318 MHz
FS2
OE

X2
X1
VDD
GND
24 MHz
8MHz
AGND

2
3
4
5
6
7

8

g
.(
~
II)

,..
1;(
0)

16
15
14
13
12
11
10
9

2
3
4
5
6

X2

X1
VDD
GND
24 MHz
8MHz
AGND

7

16
15,
14
13
12
11
10

N

~

.(
~
II)

,..
0)

1;(

8

9

FSO
X2

X1
VDD
GND
24 MHz
8MHz
AGND

l

~
II)

,..
1;(

0)

8

FS1
SLOWCLK
2XCPUCLK
VDD
GND
14.318 MHz
FS2
STOPCLK

9

16-Pin PDIP or sOle
AV9154A-43
K-4, K-6

SLOWCLK
forces
2XCPUCLK output to
ramp smoothly to 8
MHz and CPUCLKoutput to 4 MHz when
pulled low.

SWWCLK forces 2XCPUCLK
output to ramp smoothly to 8 MHz
when pulled low. STOPCLK provides glitch-free stop of the
2XCPUCLK output when pulled
low. When raised back high, the
2XCPUCLK output clock resumes
full speed operation (no clock frequency ramp up since the internal
VCO is not stopped).

2
3
4
5
6
7

0
,..

.(
~
II)

,..
1;(
0)

16
15
14
13
12
11
10

8

9

* Active Low
FOO

X1
VDD
GND
24 MHz
12MHz
AGND

7

(I)

16
15
14
13
12
11
10

Description of new pins:

8 MHz
X2
X1
VDD
GND
16MHz
1.84 MHz
AGND

X2

2
3
4
5
6

Description of new pin:

FS1
2XCPUCLK
CPUCLK
VDD
GND
14.318 MHz
FS2
PD

16-Pin PDIP or sOle
AV9154A-04
K-4, K-6

FS1
SLOWCLK
2XCPUCLK
VDD
GND
CPUCLK
14.318 MHz
FS2

16-Pin PDIP or sOle
AV9154A-42
K-4, K-6

16-Pin PDIP or sOle
AV9154A-27
K-4, K-6

FOO

FSO

2
3
4
5
6
7

8

co
ClI

,..
==
1;(
II)

0)

16
15
14
13
12
11
10
9

FSO
FS1
CPUCLK
VDD
GND
24 MHz
14.318 MHz
PDFCLK

16-Pin PDIP or

sOle

K-4. K-6
C-62

sOle

FS1
AV9154A-10
K-4, K-6
2XCPUCLK
CPUCLK
VDD
GND
14.318 MHz
FS2
16-Pin PDIP or
OE
AV9154A-26

II

AV9154A

Stop Clock Feature
The ICS9154A-43 incorporates a unique stop clock feature
compatible with static logic processors. When the stop clock
pin goes low, the 2XCPUCLK will go low after the next
occurring fulling edge. When STOPCLK again goes high,
2XCPUCLK resumes on the next rising edge of the internal
clock. This feature enables fast, glitch-free starts and stops of
the 2XCPUCLK and is guaranteed that the CPU does not
receive any short period clocks.

2XCPUCLK

STOPCLK*

C-63

AV9154A
Pin Descriptions
(Frequencies based on 14.318 MHz input)
PIN NUMBER
-4

-10

-26

-27

-42

PIN
NAME

-43

TYPE

4

4

4

4

4

4

VDD

P

Digital power (+3.3 or +5V)

13

13

13

13

13

13

VDD

P

Digital power (+3.3 or +5V)

5

5

5

5

5

5

GND

P

Digital ground

12

12

12

12

12

12

GDD

P

Digital ground

8

8

8

8

8

8

AGND

P

Analog ground

1

16

1

16

1

1

FSO

I

16

15

16

15

16

16

FSI

I

10

-

10

10

9

10

FS2

I

-

-

-

OE

I

-

9
-

-

-

9
-

Frequency select 0 for CPU clock
(has internal pull-up)*
Frequency select 1 for CPU clock
(has internal pull-up)*
Frequency select 2 for CPU clock
(has internal pull-up)*
Tristates outputs when low (has internal pull-up)*

15

15

SLOWCLK

I

-

-

-

-

-

9

STOPCLK

I

**

Slows 2XCPU clock to 8 MHz (active low)
(has internal pull-up)
Stops 2XCPU clock glitch-free (active low)
(has internal pull-up)
Crystal In

3

3

3

3

3

3

Xl

I

2

2

2

2

2

2

X2

Crystal Out

11

10

11

II

10

11

14.318 MHz

-

7

1

-

-

1.84 MHz

6

11

6

6

6

24 MHz

-

6

-

-

16 MHz

-

7

7

-

-

-

-

12 MHz

7

1

-

-

7

7

8 MHz

14

14

14

-

11

-

CPUCLK

15

-

15

14

14

14

2XCPUCLK

0
0
0
0
0
0
0
0
0

9
-

-

-

-

-

PD

I

Power-Down All (active low) (has internal pull-up)

9

-

-

-

-

PDFCLK

I

Power-Down Fixed Clock (1.84, 8, 16,24)
(active low)**

6

Internal Pull-up Resistors

*

DESCRIPTION

-04 and -10 have no pull-ups or frequency select pins
-10 has no pull-up or Pin 9 PDFCLK

C-64

14.318 MHz reference clock output
1.84 MHz (comm) clock output
24 MHz (floppy disk) clock output
16 MHz clock output
12 MHz keyboard clock output
8 MHz keyboard clock output
CPU clock output
2X CPU clock output

AV9154A
I!

Clock Tables

II

l

I

(using 14.318 MHz input, all frequencies in MHz)

i

FS2

FSI

-27
2XCPUCLK

FSO

-42
2XCPUCLK

-43
CPUCLK

! 2XCPUCLK

0

0

0

75*

16

8

16

0

0

I

32

40

20

40

0

I

0

60

33.33

16.67

33.33

0

I

1

40

25

12.50

25

1

0

0

50

60

30

60

1

0

I

66.66

20

10

20

I

I

0

80*

66.66

33.33

66.66

I

I

I

52

50

25

50

CPUCLK

2XCPUCLK

Actual Frequencies
(using 14.318 MHz input, all frequencies in MHz)
-27
FS2

II

-43

-42

FSI

FSO

2CPUCLK

0

0

0

75.17*

16.00

8.00

16.00

0

0

1

31.94

40.09

20.05

40.09

0

1

0

60.14

33.41

16.71

33.41

0

1

1

40.09

25.06

12.55

25.06

1

0

0

50.11

60.14

30.07

60.14

1

0

1

66.48

20.05

10.03

20.05

1

1

0

80.18*

66.48

33.24

66.48

1

1

1

51.90

50.11

25.06

50.11

I

2XCPUCLK

* (5Vonly)
Fixed Clock
Output Actual
Frequencies

(operating at 3V)

I (using 14.318 MHz input,

-04

-10

all frequencies in MHz)

FS(3:0)

14.318

0

100*

50*

PDCPU

1.84

1

80*

40*

40

24.0

2

66.6*

33.3*

50

12.0

3

50

25

66.6*

4

40

20

-

5

32

16

-

6

24

12

-

7

16

8

-

II

E

8.0

Clock Table for AV9154A-26

Clock Tables in MHz
for -04 and -10

I

*These selections will only operate at 5Y.

2XCPU CPU CPUCLK

C-65

i

I

FS(2:0)

2XCPU
(MHz)

CPUCLK
(MHz)

0
1
2
3
4
5
6
7

100.23*
80.18*
66.48*
50.11
40.09
32.22
24.23
15.75

50.11
40.09
33.24
25.06
20.05
16.11
12.12
7.88

I

E

AV9154A
Absolute Maximum Ratings
VDD referenced to GND ......................
Voltage on 110 pins referenced to GND ...........
Operating temperature under bias ...............
Power dissipation ............................
Storage temperature ..........................

7V
GND -O.SV to VDD +O.SV
O°C to +70°C
O.S Watts
-40° to + ISO°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics at 3.3V

-

Voo - +3 3V+1O% , TA-O°C
to 70°C unless otherwise stated
-

DC Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

0.2Voo

V

Input Low Voltage

VlL

Input High Voltage

VIH

Input Low Current

IlL

VIN=OV (pull-up pin)

Input High Current

IIH

-S.O

Output Low Voltage

VOL

VIN=Voo
IOL=6mA

Output High Voltage!

VOH

IOH=-4mA

O.SSVoo

0.94 VDD

V

Output Low Current l

IOL

VOL=0.2Voo

IS.O

24

rnA

Output High Current!

IOH

VOH=0.7Voo

-13

-S.O

rnA

Supply Current

100

Unloaded, 60 MHz

16

34

rnA

Output Frequency Change
over Supply and Temperature!
Short circuit current!

Fo

0.002

0.01

%

Isc

With respect to typical
frequency
Each output clock

Input Capacitance!

CI

Except Xl, X2

Load Capacitance!

CL

Pins Xl, X2

20

Pull-up Resistor!

Rpu

atVoo -O.SV

620

V

0.7Voo
2.S
O.OS Voo

NOTES:
I Parameter is guaranteed by design and characterization.

C-66

20

7.0

/lA

S.O

/lA
V

0.1 Voo

rnA

30
10

pF

900

kohm

pF

II

AV9154A

Electrical Characteristics at 3.3V
VDD = +3 3V+1O%
, TA=O°C to 70°C unless otherwise stated
' .. ': . :.::" .
AC{l.lut~teJ.1stkos

.......

..'

.

MAX

UNITS

Input Clock Rise Time!

tICr

20

ns

Input Clock Fall Time!

tICf

20

ns

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

Rise time, 20% to 80% VDD!

tr

l5pfload

-

2.2

3.5

ns

Fall time, 80% to 20% VDD!

tf

15pfload

-

1.2

2.5

ns
%

Duty cycle at 50% VDD!

dt

15pfload

40/60

48/52

60/40

Duty cycle, reference clocks!

dt

15pfload

50/65

43/57

65/50

%

Jitter, one sigma, 20-66 MHz
clocks!
Jitter, one sigma, clocks
below 20 MHz!
Jitter, absolute, 20-66 MHz
clocks!

tj!s

10,000 cycles

100

200

ps

tJ!s

10,000 cycles

1.0

2.0

%

tjab

10,000 cycles

350

ps

Jitter, absolute,
clocks below 20 MHz!
Input Frequency!

tjab

10,000 cycles

1.5

4.0

%

fin

2

14.318

32

MHz

Maximum Output Frequency!

fout

70

Clock skew between CPU and
2XCPU outputs!
Power-up Time!

Tsk

220

500

ps

6

12

ms

4.5

10

ms

Frequency Transition Time!

ttpo
tft

-350

AV9154A-42

MHz

off to 50 MHz
from 8 to 50 MHz

NOTES:
1 Parameter is guaranteed by design and characterization, not subject to production testing.

C-67

E

II

AV9154A
Electrical Characteristics at 5V

-

VDD - +5V+1O%
, TA-O°C
to 70°C unless otherwise stated
.1

DC Characteristics

.....

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

0.8

V

,I

Input Low Voltage

VIL

VDD=5V

Input High Voltage

Vm
IlL

VDD=5V
VIN=OV (pull-up pin)

2.0

Input Low Current
Input High Current

1m

VIN=VDD

-5

Output Low Voltage

VOL

IOL=lOrnA

Output High Voltage!

VOH

IOH=-30rnA

2.4

3.7

V

Output Low Current!

IOL

VOL=0.8

25

45

rnA

V
6
0.15

15

IlA

5

!1A

0.4

V

Output High Current!

IOH

VOH=2.4V

-53

-35

rnA

Supply Current

IDD

Unloaded, 66 MHz

25

50

rnA

Output Frequency Change
over Supply and Temperature!
Short circuit current!

FD

0.002

0.01

%

Isc

With respect to typical
frequency
Each output clock

Input Capacitance!

CI

Except Xl, X2

Load Capacitance!

CL

Pins Xl, X2

20

Pull-up Resistor!

Rpu

A+VDD -IV

400

25

40

NOTES:
I Parameter is guaranteed by design and characterization, not subject to production testing.

C-68

rnA

10

pF

700

kohrn

pF

II

AV9154A

Electrical Characteristics at 5V
VDD = +5V+1O%
TA=O°C to 70°C unless otherwise stated
-

AC Characteristics
PARAMETER

SYMBOL

Input Clock Rise Time!
Input Clock Fall Time!

TEST CONDITIONS

MIN

TYP

MAX

UNITS

tICr

20

ns

tICf

20

ns

Output Rise time, 0.8 to 2.0V!

tr

l5pfload

-

1.5

2

ns

Rise time, 20% to 80% VDD!

tr

15pfload

-

2.0

3

ns

Output Fall time, 2.0 to 0.8V!

tf

15pfload

-

0.5

1.5

ns

Fall time, 80% to 20% VDD!

tt

15pfload

-

2.0

3.0

ns

Duty cycle at 1.4V!

dt

45/55

48/52

55/45

%

Duty cycle, reference clocks!

dt

15pfload, VDD=5V±5%
15 pfload

40/65

43/57

65/40

%

Jitter, one sigma, 20 MHz80 MHz clocks!
Jitter, one sigma,
clocks below 20 MHz!
Jitter, absolute, 20 MHz80 MHz clocks!
Jitter, absolute,
clocks below 20 MHz!
Input Frequency

tJls

10,000 cycles

70

140

ps

tjls

10,000 cycles

0.8

2.0

%

tjab

10,000 cycles

250

ps

tjab

10,000 cycles

1.0

3.0

%

14.318

32

-250

fin

2

Maximum Output Frequency!

fout

140

Clock skew between CPU and
2XCPU outputs!
Power-up Time!

Tsk
ttpo

Frequency Transition Time!

tft

AV9154A-42

140

400

ps

8

15

ms

6.5

12

ms

to 80 MHz
from 8 to 66.66 MHz

NOTES:
1 Parameter is guaranteed by design and characterization, not subject to production testing.

Ordering Information
AV9154A-42CN16
AV9154A-43CN16
AV9154A-27CN16

AV9154A-26CN16
AV9154A-10CN16
AV9154A-04CN16

AV9154A-42CM16
AV9154A-43CM16
AV9154A-27CM16

-1 1

AV9154A-26CM16
AV9154A-10CM16
AV9154A-04CM16

Example:

ICS XXXX-PPP M x#w

L~dC'_&~~WM~
Lead Count=!, 2 or 3 dtgits

W=.3" sorc or .6" DIP; None=Standard Width
Package Type
N=DIP (l'lastic)
M=SorC
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - Prertx
rcs, AV=Standard Device; GSP=Genlock Device

C-69

MHz
MHz

C-70

AV91S4A-06
AV91S4A-60

Integrated
Circuit
Systems, Inc.

•

OPTi Notebook Frequency Generator
General Description

Features

The AV9154A-06/60 is a low cost frequency generator designed for general purpose PC and disk drive applications. Its
CPU clocks provide all necessary frequencies for 286, 386 and
486 systems, including support for the latest speeds of processors. The standard devices use a 14.318 MHz crystal to generate the CPU and peripheral clocks for integrated desktop and
notebook motherboards.

•
•
•
•
•
•

The AV9154A-06 and AV9154A-60 are specifically designed
for use with OPTi core logic chip sets. The only noticeable
difference between the two parts is in their CPU clock selection
tables as shown on page three.

Applications

The AV9154A-06 and AV9154A-60 can operate at S.OV±lO%
or 3.3V±1O%, but the CPU frequencies are limited (see the
asterisks on the selection tables on page three) during 3.3V
operation. The parts have two power-down pins. One shuts off
the CPU clock to a low state when the power-down pin is taken
high, and the other turns off the 14.318 MHz output in the same
manner.

Compatible with 286, 386, and 486 CPUs
Up to 66.6 MHz (-60) or 80 MHz (-06) CPU clocks
All loop filter components internal
3V and SV operation
16-pin ISO mil SOlC
Power-down control of CPU clock

Computer Mqtherboards: The AV9154A-06/60 replaces crystals and oscillators, saving board space, component cost, part
count and inventory costs. It produces switchable CPU clock
and up to four fixed clocks to drive floppy disk, communications, super I/O, bus and/or keyboard devices. The small package and 3V operation is perfect for handheld computers.

Block Diagram

• •

VDD

GND

r---------------------FSO-2

I

;;;3<

..
)P

PDCPUCLK --+I--------....,.~I

1,..------.
I

CPU
CLOCK

REFERENCE
CLOCK

OUTPUT
BUFFER

t-"T'"" CPUCLK

OUTPUT
BUFFER

t-......... 24 MHz

OUTPUT
BUFFER

J-_....... 128 kHz

....._ . , PERIPHERAL
CLOCKS

IAV9154A·06l60RevA092794
C-71

II

AV9154A-06
AV9154A-60
Pin Configuration

Clock Tables for AV9154A-06/60
(in MHz)
-06

-60

FS1

FS(2:0)

CPUCLK

CPUCLK

X2

FS2

X1

CPUCLK
VDD
GND

0
1
2
3
4
5
6
7

16
20
25
33.33
40
50
66.66
80*

8
16
20
25
33.33
40*
50*
66.66*

FSO

VDD
GND
24 MHz

14.318 MHz

128 kHz

PDCPUCLK
PD14

AGND

Actual Output Frequencies
16-Pin sOle
K-6

(in MHz)
-06

-60

FS(2:0)

CPUCLK

CPUCLK

0
1
2
3
4
5
6
7

16.11
20.05
25.06
33.24
40.09
50.11
66.48
80.18*

8.182
16.11
20.05
25.06
33.24
40.09*
50.11 *
66.48*

Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PIN NAME
FSO
X2
Xl
VDD
GND
24 MHz
128 kHz
AGND
PD14
PDCPUCLK
14.318 MHz
GND
VDD
CPUCLK
FS2
FSI

TYPE
I
0
I
P
P
0
0
P
I
I
0
P
P
0
I
I

DESCRIPTION
Frequency Select 0 for CPUCLK
Crystal out. Connect a 14.318 MHz crystal to this pin.
Crystal in. Connect a 14.318 MHz crystal to this pin.
Digital Power (+3.3V or +5V)
Digital Ground
24 MHz clock output
128 kHz clock output
Analog Ground
Power-down 14.318 MHz output (active hil:h)
Power-down CPU clock.(active high)
14.318 MHz reference clock output
Digital Ground
Digital Power (+3.3V or +5V)
CPU Clock output determined by status of FSO - FS2
Frequency Select 2 for CPUCLK
Frequency Select 1 for CPUCLK

NOTE:

No internal pull-ups on any Inputs.

C·72

AV91S4-06
AV91S4-60
Absolute Maximum Ratings
VDD referenced to GND ...................... 7V
Operating temperature under bias ............... O°C to + 70°C
Storage temperature .......................... -40°C to + 150°C
Voltage on I/O pins referenced to GND ........... GND -0.5V to VDD +0.5V
Power dissipation ............................ 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. TIlls is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics at 5V
VDD =+5V±IO%, TA=O°C to 70°C unless otherwise stated

DC Ctlaracteristks
PARAMETER

SYMBOL

TEST CONDITIONS

Input Low Voltage

VIL

VDD=5V

Input High Voltage

VIH

VDD=5V

I

MIN

TYP

MAX
0.8

2.0

UNITS
V
V

Input Low Current

IlL

VIN=OV

-5

!-LA

Input High Current

IIH

VIN=VDD

5

Output Low Voltage

VOL

IOL=4mA

0.4

!-LA
V

Output High Voltage

VOH

IOH=-lrnA

VDD-.4V

V

Output High Voltage

VOH

IOH=-4rnA

VDD-.8V

V

Output High Voltage

VOH

2.4

Supply Current

IDD

IOH=-8mA
No load I

Output Frequency Change
over Supply and Temperature
Short circuit current

FD
Isc

With respect to typical
frequency
Each output clock

Input Capacitance

Ci

Except Xl, X2

Load Capacitance

CL

Pins Xl, X2

20

pF

When powered-down

20

rnA

Supply Current, lowest

IDDSTBY

25

V
25

40

rnA

0.002

0.01

%

40

rnA

10

NOTE:
1 All clocks on AV9154A-06 or -60 running at highest possible frequencies.

C·73

pF

-

II

AV9154A-06
AV9154A-60
Electrical Characteristics at 5V
VDD =+5V±1O%, TA=O°C to 70°C unless otherwise stated
',y<:", ~:: : : : , ' '

,:::,::

,,'

PARAMETER

,:,:"'~'>

SYMBOL

'Ace Oi,~e~~ ,',
TEST CONDITIONS

',:,',

MIN

TYP

'

,",

'

MAX

UNITS

Input Clock Rise Time

tICr

20

ns

Input Clock Fall Time

tICf

20

ns

Output Rise time, 0.8 to 2.0V

tr

15pfload

Rise time, 20% to 80% VDD

tr

15pfload

Output Fall time, 2.0 to 0.8V

tt

15pfload

Fall time, 80% to 20% VDD

tf

15pfload

-

1

2

ns

2

4

ns

1

2

ns

2

4

ns
%

Duty cycle

dt

15pfload

40/60

48/52

60/40

Duty cycle, reference clock

dt

15pfload

40/60

43/57

60/40

%

Duty cycle, CPU clock -06

dt

15pfload

40/60

42/58

60/40

%

±0.8

±2.5

%

±2

±5

%

700

ps

Jitter, one sigma

Tjls

Jitter, absolute

Tab

Jitter, absolute

Tjab

As compared with
clock period
16-80 MHz clocks

Input Frequency

fi

Frequency Transition time

tft

from 16
to 80 MHz
..

15

Power-up time

tpu

from off to 50 MHz

15

14.318

MHz
20

ms

-~"

NOTE:
1 All clocks on AV9154A-06 or -60 running at highest possible frequencies.

C·74

ms

II

AV9154-06
AV9154-60

Electrical Characteristics at 3.3V
Operating VDD =+3.0V to +3.7V, TA=O°C to 70°C unless otherwise stated

DC Cbaraeterist1es
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS
V

Input Low Voltage

VIL

-

-

0.15VDD

Input High Voltage

VIH

0.7VDD

-

-

V

Input Low Current

IlL

VIN=OV

-5

-

5

IlA

Input High Current

IIH

VIN=VDD

-5

-

5

J.LA

Output Low Voltage

VOL

IOL=8rnA

-

-

0.1

V

Output High Voltage

VOH

IOH=-4rnA

VDD-.1V

-

-

Supply Current

IDD

Note 1

-

15

Output Frequency Change
over Supply and Temperature
Input Capacitance

Fd

-

0.002

Ci

With respect to typical
frequency
Except Xl, X2

Load Capacitance

CL

Pins Xl, X2

20

pF

When powered-down

14

rnA

30

rnA

Supply Current, lowest
Short Circuit Current

IDDL
Isc

V
rnA

0.01

%

10

pF

Note 1: AV9154A with no load, with 14.318 MHz crystal input, and CPUCLK running at 33 MHz. Power supply current
varies with frequency. Consult ICS for actual current at different frequencies.

Electrical Characteristics at 3.3V
(Operating VDD =+3.0V to +3.7V, TA=O°C to 70°C unless otherwise stated)
"

PARAMETER
Input Clock Rise Time
Input Clock Fall Time
Rise time

SYMBOL

>

>,

AC~

TEST CONDmONS

"

:'~

MIN

TYP

',.,

MAX

UNITS

tICr

20

ns

tICf
tr

20

ns

15 pfload

-

-

4

ns
ns

tf

15 pfload

-

-

4

Duty cycle, fixed clocks

dt

15 pfload

40/60

48/52

60/40

%

Duty cycle, CPU clock -06

dt

15 pfload

40/60

42158

60/40

%

Duty cycle, reference clock

dt

15 pfload

40/60

43/57

%

Fall time

Jitter, one sigma

TjJs

All frequencies

±D.5

60/40
±2

Jitter, absolute

Tabs

All frequencies

±3

±5

%

20

ms

33

MHz

Frequency Transition time

tft

from 8 to 33 MHz

Power-up time

tpu

from off to 50 MHz

Output Frequency

fo

Will operate up to
50 MHz for -06 version

Input Frequency

fi

ms

15

2
14.318

%

MHz

Note 1: AV9154A with no load, with 14.318 MHz crystal input, and CPUCLK running at 33 MHz. Power supply current
varies with frequency. Consult ICS for actual current at different frequencies.

C-7S

Ii

II

AV91S4A-06
AV91S4A-60
Ordering Information
AV9154A-06CS16 or
Example:

11

ICS XXXX-PPP M

AV9154A-60CS16

x#w

Luooc~'&~~W'~

Lead Count= I, 2 or 3 dlglts
W=,3" SOIC or ,6" DIP; None=Standard Width

Package Type
S=SOIC

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
" - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
L-----------Prefix
ICS, AV=Standard DeVIce; GSP=Genlock DeVIce

C-76

AV9155A

Integrated
Circuit
Systems, Inc.

•

Low Cost 20-Pin Frequency Generator
General Description

Features

The AV9155A is a low cost frequency generator designed
specifically for desktop and notebook PC applications. Its CPU
clocks provide all necessary CPU frequencies for 286, 386 and
486 systems, including support for the latest speeds of processors. The device uses a 14.318 MHz crystal to generate the CU
and all peripheral clocks for integrated desktop motherboards.

•
•

•

•
•

The dual 14.318 MHz clock outputs allows one output for the
system and one to be the input to an ICS graphics frequency
generator such as the AV9194.

•
•
•

The CPU clock offers the unique feature of smooth, glitch-free
transitions from one frequency to the next, making this ideal
device to use whenever slowing the CPU speed. The AV9155A
makes a gradual transition between frequencies, so that it
obeys the Intel cycle-to-cycle timing specification for 486
systems. The simultaneous 2X and IX CPU clocks offer controlled skew to within 1.5ns (max) of each other.

•

ICS has been shipping motherboard frequency generators
since April 1990, and is the leader in the area of multiple output
clocks on a single chip. The AV9155A is a third generation
device, and uses ICS's patented analog CMOS phase-locked
loop technology for low phase jitter. ICS offers a broad family
of frequency generators for motherboards, graphics and other
applications, including cost-effective versions with only one
or two output clocks. Consult ICS for all of your clock generation needs.

ICS offers several versions of the AV9155A. The different
devices are shown below:
PART
AV9155A-OI

DESCRIPTION
Motherboard clock generator with 16 MHz BUS CLK

AV9155A-02

Motherboard clock generator with 32 MHz BUS CLK

AV9155A-03

Special frequencIes for both 386 and 486 CPUs

AV9155A-23

Includes Pentium™ frequencies

AV9155A-36

Features a SjlOcial 40 MHz SCSI clock

Compatible with 286,386, and 486 CPUs
Supports turbo modes
Generates communications clock, keyboard clock, floppy
disk clock, system reference clock, bus clock and CPU
clock
Output enable tristates outputs
Up to 100 MHz at 5V, 66.6 MHz at 3.3V
20-pin DIP or SOIC
All loop filter components internal
Skew-controlled 2X and IX CPU clocks
Power-down option

Block Diagram
3-4
SCLK20-23-.-----I-f('------~

t

L...------....I

14.318 MHz
crystal

CPU
CLOCK

REFERENCE
CLOCK

t

t

GND

1...--.,-----1

2XCPU
CPU

r-------------------------~--------~OE

PERIPHERAL
CLOCK

VDD

OUTPUT
BUFFERS

t

POWER-DOWN

OUTPUT
BUFFERS

KBCLK
BUSCLK
FDCLK
COMMCLK

t

AGND
Pentium IS a trademark at Intel Corporation

IAV9155ARevA092794
C-77

Ii

II

AV9155A
Pin Configuration

1.843 MHz
X2
X1
VDD
GND
16 MHz
24 MHz
12 MHz
AGND
OE

2
3
4
5
6
7
8
9

20
19
,.... 18
917
~ 16
~ 15
0) 14
>
iCC 13
12

SCLK20
SCLK21
CPU
2XCPU
VDD
GND
14.318 MHz
14.318 MHz
PD
SCLK22

1.843 MHz
X2
X1
VDD
GND
32 MHz
24 MHz
12 MHz
AGND
OE

20-Pin DIP or SOIC
K-4, K-7

2
3
4
5
6
7
8
9

20
19
N 18
917
~ 16
~ 15
14
oCt 13
12

g!

SCLK20
SCLK21
CPU
2XCPU
VDD
GND
14.318 MHz
14.318 MHz
PD
SCLK22

20-Pin DIP or SOIC
K-4, K-7

Pin Descriptions for AV9155A-01, -02
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
12
13
14
15
16
17
18
19
20

PIN NAME
1.843 MHz
X2
Xl
VDD
GND
16 MHz/32 MHz
24 MHz
12 MHz
AGND
OE
SCLK22
AVDD
PD
14.318 MHz
14.318 MHz
GND
VDD
2XCPU
CPU
SCLK21
SCLK20

DESCRIPTION

TYPE
Output
Output
Input
Output
Output
Output
Input
Input

Input
Output
Output
Output
Output
Input
Input

1.84 MHz clock output
CRYSTAL connection
CRYSTAL connection
DIGITAL POWER SUPPLY (+5V)
Digital GROUND
16 MHz (AV9155-0l) or 32 MHz (AV9155-02) clock output
24 MHz floppy disk/combination I/O clock output
12 MHz keyboard clock output
ANALOG GROUND (original version)
OUTPUT ENABLE. Tristates all outputs when low. (Has internal pull-up.)
CPU CLOCK frequency SELECT #2. (Has internal pull-up.)
ANALOG POWER SUPPLY (+5V)
POWER-DOWN. Shuts off entire chip when low. (Has internal pull-up.)
14.318 MHz reference clock output
14.318 MHz reference clock output
Digital GROUND
DIGITAL POWER SUPPLY (+5V)
2X CPU clock output
IX CPU clock output
CPU CLOCK frequency SELECT #1. (Has internal pull-up.)
CPU CLOCK frequency SELECT #0. (Has internal pull-up)

C-78

AV9155A
PERIPHERAL CLOCKS
COMMCLK
BUSCLK
(Pin 1)
(Pin 6)

Decoding and Clock Tables AV9155A-01
(using 14.318 MHz input. All frequencies in MHz.)

CLOCK#2 CPU and 2XCPU
SCLK22 SCLK21 SCLK20
(Pin 11)
(Pin 19)
(Pin 20)
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1.843
2XCPU
(Pin 17)

CPU
(Pin 18)

8
16
32
40
50
66.66
80*
100*

4
8
16
20
25
33.33
40*
50*

16

FDCLK
(Pin 7)

KBCLK
(Pin 8)

24

12

REFERENCE CLOCKS
REFCLKI
(Pin 13)

It

REFCLK2
(Pin 14)

14.318

14.318

* 5Vonly

Decoding and Clock Tables AV9155A-02
(using 14.318 MHz input. All frequencies in MHz.)

CLOCK#2 CPU and 2XCPU
SCLK22 SCLK21 SCLK20
(pin 11)
(Pin 19)
(Pin 20)
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

PERIPHERAL CLOCKS
COMMCLK
BUSCLK
(Pin I)
(Pin 6)
1.843

2XCPU
(Pin 17)

CPU
(Pin 18)

8
16
32
40
50
66.66
80*
100*

4
8
16
20
25
33.33
40*
50*

32

REFERENCE CLOCKS
REFCLKI
(Pin 13)
14.318

FDCLK
(Pin 7)

KBCLK
(Pin 8)

24

12

REFCLK2
(Pin 14)
14.318

* 5Vonly

Frequency Transitions

Using an Input Clock as Reference

A key feature of the AV9155A is its ability to provide smooth,
glitch-free frequency transitions on the CPU and 2XCPU
clocks when the frequency select pins are changed. These
frequency transitions do not violate the Intel 486 specification
of less than 0.1 % frequency change per clock period.

The AV9155A is designed to accept a 14.318 MHz crystal as
the input reference. With some external changes, it is possible
to use a crystal oscillator or clock input. Please see application
note AAN04 for details on driving the AV9155A with a clock.

C·79

AV9155A
Pin Configuration

6 MHz

X2
X1
VDD
GND
24 MHz
16MHz
8MHz
AGND

2
3
4
5
6

7
8

C')

18

917
~ 16
~
~

c:c

OE

15
14
13

SCLK20
SCLK21
SCLK22
CPU
VDD
GND
14.318 MHz
14.318 MHz
PD
SCLK23

20-Pln DIP or sOle
K-4, K-7

Pin Descriptions for AV9155A-03
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PIN NAME
6 MHz
X2
Xl
VDD
GND
24 MHz
16 MHz
8 MHz
AGND
OE
SCLK23

PO
14.318 MHz
14.318 MHz
GND
VDD
CPU
SCLK22
SCLK21
SCLK20

DESCRIPTION

TYPE
Output
Output
Input

Output
Output
Output

Input
Input
Input
Output
Output

Output
Input
Input
Input

6 MHz clock output
CRYSTAL connection
CRYSTAL connection
DIGITAL POWER SUPPLY (+5V)
Digital GROUND
24 MHz (-03) floppy disk
16 MHz (-03) bus clock output
8 MHz (-23) keyboard clock output
ANALOG GROUND
OUTPUT ENABLE. Tristates all outputs when low. (Has internal pUll-Up.)
CPU CLOCK frequency. (Has internal pull-up.)
POWER-DOWN. Shuts off entire chip when low. (Has internal pull-up.)
14.318 MHz reference clock output
14.318 MHz reference clock output
Digital GROUND
DIGITAL POWER SUPPLY (+5V)
CPU clock outputl2XCPU clock output
CPU CLOCK frequency SELECT #2. (Has internal pull-up.)
CPU CLOCK frequency SELECT #1. (Has internal pull-up.)
CPU CLOCK frequency SELECT #0. (Has internal pull-up.)

C-80

AV9155A
Decoding and Clock Tables AV9155A-03
(using 14.318 MHz input. All frequencies in MHz.)
CLOCK#2CPU
SCLK23 SCLK22
(Pin 11)
(Pin 18)

SCLK21
(Pin 19)

SCLK20
(Pin 20)

CPU
(Pin 17)

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

16
40
50
80*
66.66
100*
8
4

486

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

8
20
25
40
33.3
50
4
2

386

* 5Vonly
Smooth, glitch-free frequency transitions are guaranteed if the
state of SCLK23 (pin 11) is not changed (smooth transitions
are guaranteed in either the top or bottom half of the frequency
decode table).
PERIPHERAL CLOCKS
COMMCLK
BUSCLK
(Pin 7)
(Pin 1)
6 MHz

16 MHz

REFERENCE CLOCKS
REFCLKI
(Pin 13)
14.318

FDCLK
(Pin 6)

KBCLK
(Pin 8)

24 MHz

8 MHz

REFCLK2
(Pin 14)
14.318

e-S1

AV9155A
Pin Configuration

1.843 MHz
X2
Xl
VCC
GND
16MHz
24 MHz
12MHz
GND
OE

2
3
4
5
6
7
8
9
10

20
19
C') 18
C}I 17


~

VDD

16

GND

15
14

14.318 MHz ':;:'

8

13

14.318 MHz

9

12

PD

10

11

SCLK22

7

0.1,uF

-

NOTES:

1. ICS recommends the use of an isolated ground plane for the AV9155A. All grounds shown on this drawing should be
connected to this ground plane. This ground plane should be connected to the system ground plane at a single point.
Please refer to AV9155A Board Layout Diagram.
2. A single power supply connection for all VDD lines at the 2.21lF decoupling capacitor is recommended to reduce
interaction of analog and digital circuits. The O.lIlF decoupling capacitors should be located as close to each VDD
pin as possible.
3. A 330 series termination resistor should be used on any clock output which drives more than one load or drives a
long trace (more than about two inches), especially when using high frequencies (>50 MHz). This termination
resistor is put in series with the clock output line close to the clock output. It helps improve jitter performance
and reduce EMI by damping standing waves caused by impedance mismatches in the output clock circuit trace.
4. The ferrite bead does not enhance the performance of the AV9155A, but will reduce EMI radiation from the VDD line.

C-86

AV9155A
AV9155A Recommended Board Layout
PIN 1

Ii

---c::::J
XTAL

FB

Gap

In

Ground Plane

AV9155 Ground

- System Ground -

-8

To
~ System

®
QO

VDD

= connectIon to

ground plane

This is the recommended layout for the AV9155A to maximize clock performance. Shown are the power and ground connections,
the ground plane, and the input/output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise
from propagating through the device. When compared to using the system ground and power planes, this technique will minimize
output clock jitter. The isolated ground plane should be connected to the system ground plane at one point, near the 2.21lF
decoupling cap. For lowest jitter performance, this isolated ground plane should be kept away from clock output pins and traces.
Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between the isolated
ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line optional, but will help reduce
EM!.
The traces to distribute the output clocks should be over a system ground or power supply plane. The trace width should be about
two times the thickness of the PC board between the trace and the underlying plane. These guidelines help minimize clock jitter
and EMI radiation. The traces to distribute power should be as wide as possible.

C-S7

AV9155A
Ordering Information
AV9155A-01 CN20, AV9155A-02CN20, AV9155A-03CN20,
AV9155A-23CN20, AV9155A-36CN20
Example:

ICS XXXX-PPP M x#w

11

L L~~&P_~Wwili

Lead Count=l, 2 or 3 digits
W=.3" SOIC or .6" DIP; None=Standard Width

Package 1Ype
N=DIP (Elastic)

T&R=Tape and Reel

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - - Device 1Ype (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - - Prefix
ICS, AV=Standard Device; GSP=Genlock Device

AV9155A-01 CW20, AV9155A-02CM20, AV9155A-03CM20,
AV9155A-23CM20, AV9155A-36CM20
Example:

ICS XXXX-PPP M X#W

TrCUOO~~'~WDili

Lead Count= I, 2 or 3 digits
•
W=.3" SOIC or .6" DIP; None=Standard Width

Package 1YPe
W=SOIC

T&R=Tape and Reel

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
L......._ _ _ _ _ _ Device 1Ype (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - - Prefix
ICS, AV=Standard Device; GSP=Genlock Device

NOTES:
Tape and reel packaging should be ordered with the suffix T&R. For instance, if the -01 in DIP and tape & reel is required, order
the part as AV9155-OlCN20T&R.

C-88

ICS9158

Integrated
Circuit
Systems, Inc.

•

Integrated Buffer and Motherboard Frequency Generator
General Description

Features

The ICS9158 is a low cost frequency generator designed
specifically for desktop and notebook PC applications. Eight
high drive, skew-controlled copies of the CPU clock are available, eliminating the need for an external buffer.

•
•
•
•
•
•
•
•
•

Each high drive (SOmA) output is capable of driving a 30pf
load and has a typical duty cycle of 50/50. The CPU clock
outputs are skew-controlled to within ±250ps. The CPU clocks
provide all necessary frequencies for 286, 386, 486 and Pentium systems, including support for the latest speeds of processors.
The CPU clock offers the unique feature of smooth, glitch-free
transitions from one frequency to the next, making this the
ideal device to use whenever slowing the CPU speeds. The
ICS9158 makes a gradual transition between frequencies so
that it meets the Intel cycle-to-cycle timing specification for
486 systems.
ICS has been shipping Motherboard Frequency Generators
since April 1990, and is the leader in the area of multiple output
clocks on a single chip. The ICS9158 is a third generation
device, and uses ICS's patented analog CMOS Phase-Locked
Loop technology for low phase jitter. ICS offers a broad family
of frequency generators for motherboards, graphics and other
applications, including cost effective versions with only one or
two output clocks. Consult rcs for all of your clock generation
needs.

•
•
•

Eight skew-free, high drive CPU clock outputs
Up to 100 MHz output at 5V
±250ps skew between CPU and 2XCPU outputs
Outputs can drive up to 30pfload
SOmA output drivers
Typical 50/50 duty cycle
Compatible with 486 and Pentium CPUs
Glitch-free start and stop clock option
Optional power-down mode supports Energy Star
("green") PCs
On-chip loop filter components
Low power, high speed 0.8~ CMOS technology
24-pin PDIP or SOIC package

Clock Table (in MHz)
Clock

ICS9158-01

BUSCLK
FDCLK
14.318

16
24
14.318

CPUCLK
2XCPUCLK

4,8,30,20,25,33.3,40, or 50
8,16,60,40,50,66.6,80, or 100

Block Diagram

r----~----------------

I
SO-S2

14.318 MHz
Crystal D
14.318 MHz

I
I
I
I
I
I
I

CPU
CLOCK
REFERENCE
CLOCK

I

2XCPU

t---f-. CPU 1,2,3,4,5,6,7

r---------------------~------~--OE

PERIPHERAL
CLOCKS

I
I

OUTPUT
BUFFER

I

OUTPUT
BUFFERS

1--1-+ BUSCLK

I
I----If-+ FOCLK

~-f-f--------------f--VOO

GNO

AGNO

IICS9158-01 RevA112294

C-89

I

Ii

ICS9158
Pin Configuration
CPU2
X140UT
X141N
VDD
GND
16MHz
24 MHz
CPU3
AGND

80
81

CPU1
2XCPU
VDD
GND
14.318 MHz
CPU4
AVDD
82

OE

CPU5
GND

CPU6
CPU?

24-Pin PDIP or
K-5, K-7

sOle

Pin Descriptions for ICS9158-01
PIN NUMBER

PIN NAME

DESCRIPTION

TYPE

1

CPU2

Output

CPU clock output

2

X 140UT

-

Crystal connection

3

X14IN

-

Crystal connection

4

VDD

-

Digital POWER SUPPLY (+5V)

5

GND

-

Digital GROUND

6

16 MHz

Output

16 MHz clock output

7

24 MHz

Output

24 MHz floppy disk/combination I/O clock output
CPU clock output

8

CPU3

Output

9

AGND

-

10

OE

Input

ANALOG GROUND
OUTPUT ENABLE. Tristates all outputs when low.

11

CPU5

Output

12

GND

-

Digital GROUND

13

CPU7

Output

CPU clock output

14

CPU6

Output

CPU clock output

15

S2

16

AVDD

-

17

CPU4

Output

18

14.318 MHz

Output

19

GND

20

VDD

21

2XCPU

Output

2X CPU clock output

22

CPU!

Output

CPU clock output

23
24

Sl

Input

CPU clock frequency select #1

SO

Input

CPU clock frequency select #0

Input

CPU clock output

CPU clock frequency select 2
ANALOG power supply (+5V)
CPU clock output
14.318 MHz clock output

-

Digital GROUND

-

Digital POWER SUPPLY (+5V)

C·90

II

ICS9158

Absolute Maximum Ratings
A VDD, VDD referenced to GND ...............
Operating temperature under bias ...............
Storage temperature ..........................
Voltage on 110 pins referenced to GND ...........
Power dissipation ............................

7V
O°C to + 70°C
-40°C to + 150°C
GND -0.5V to VDD +0.5V
0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics at 5V
VDD = +5V±10%, TA=O°C to 70°C unless otherwise stated

, ... _-" -

DC Cbaracterlstics

_

PARAMETER

SYMBOL

Input Low Voltage

Vn..

Input High Voltage

VIH

TEST CONDITIONS

-----------

MIN

TYP

MAX
0.8

2.0

In..

VIN=OV

-5

5

Input High Current

IIH

VIN=VDD

-5

5

Output Low Voltage

VOL

IOL=20.0mA

VOH

IOH=-30rnA

2.4

Output Low Current (Note 1)

IOL

VOL=0.8V

45

Output High Current (Note 1)

IOH

Supply Current

IDD

Output Frequency Change over
Supply and Temperature (Note 1)
Short circuit current (Note 1)
Pull-up resistor value (Note 1)

FD
Isc
Rpu

0.25

With respect to typical
frequency
Each output clock
Input pin

25

0.4

3.5

Ci

Except Xl, X2

Load Capacitance (Note 1)

CL

PinsXl,X2

rnA
rnA

43

65

rnA

0.002

0.01

%
rnA

56

ill
8

20

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

C-91

V

-35

680

Input Capacitance (Note 1)

J.IA
J.IA
V

65
-55

VOH=2.0V
No load, 80 MHz

V
V

Input Low Current

Output High Voltage (Note 1)

UNITS

pf
pf

ICS9158
Electrical Characteristics

(continued)

Voo = +5V±IO%, TA=O°C to 70°C unless otherwise stated

AC Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output Rise time, 0.8 to 2.0V
(Note I)

tr

30pfload

-

I

2

ns

Rise time, 20% to 80% Voo
(Note I)

tr

30pfload

-

2.5

3

ns

Output Fall time, 2.0 to 0.8V
(Note 1)

tf

30pfload

-

0.5

I

ns

Fall time, 80% to 20% Voo
(Note I)

tf

30pfload

-

1.5

2

ns

40/60

48/52

60/40

%

0.5

2.0

%

2

5

%

500

ps

Duty cycle (Note I)

dt

3Opfload

Jitter, one sigma (Note I)

tjls

Jitter, absolute

tJab

As compared with
clock period

Jitter, absolute

tJab
fi

Input Frequency
Clock skew between CPU and
2XCPU outputs
Frequency Transition time
(Note I)

16-100 MHz clocks
14.318

Tsk
tft

From 4 to 50 MHz

250

ps

13

20

ms

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

C-92

MHz

100

ICS9158
ICS91S8-01 CPU Clock Decoding Table
(using 14.318 MHz input. All frequencies in MHz)
Peripheral Clocks

CLOCK#2 CPU and 2XCPU
S2
SI
SO
(Pin 15) (Pin 23) (Pin 24)

2XCPU
(Pin 21)

CPU

0
0
1
1
0
0
1
1

7.580
15.511
59.875
40.090
50.113
66.476
79.772*
100.226*

3.790
7.756
29.938
20.045
25.057
33.238
39.886*
50.113*

0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1

BUSCLK
(Pin 6)

FDCLK
(Pin 7)

16.002

24.003

Reference Clock
REFCLKI
(Pin 18)
14.318

*5Vonly

Frequency Transitions

Stop Clock Feature (Optional Mask Version)

A key feature of the ICS9158 is its ability to provide smooth,
glitch-free frequency transitions on the CPU and 2XCPU
clocks when the frequency select pins are changed. The frequency transition rate does not violate the Intel 486 or Pentium
specification of less than 0.1 % frequency change per clock
period.

The ICS9158 incorporates a unique stop clock feature compatible with static logic processors. When the stop clock pin goes
low, the CPUCLK will go low after the next occurring falling
edge. When STOPCLK again goes high, CPUCLK resumes on
the next rising edge of the internal clock. This feature enables
fast, glitch-free starts and stops of the CPUCLK and is useful
in Energy Start motherboard applications.

Using an Input Clock as a Reference
The ICS9158 is designed to accept a 14.318 MHz crystal as the
input reference. With some external changes, it is possible to
use a crystal oscillator or other clock sources. Please see
application note AAN04 for details on driving the ICS9158
with a clock.

CPUCLK

STOPCLK

C-93

ICS9158
Ordering Information
ICS9158-01 N
Example:

ICS XXXX-PPP M

11

~~)

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - - Prefix
ICS, AV=Standard Device; GSP=Genlock Device

ICS9158-01 M
Example:

ICS XXXX-PPP M

11

~=,~

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - - Prefix
ICS, AV=Standard Device; GSP=Genlock Device

C-94

ICS91S9-02

Integrated
Circuit
Systems, Inc.

•

Product Preview

Frequency Generator and Integrated Buffer for PENTIUMTM
General Description

Features

The ICS9159-02 generates all clocks required for high speed
RISC or CISC microprocessor systems such as 486, Pentium,
PowerPC,TM etc. Four different reference frequency multiplying factors are externally selectable with smooth frequency
transitions. These multiplying factors can be customized for
specific applications. A test mode is provided to drive all clocks
directly.

•

High drive BCLK outputs provide greater than 1VIns slew rate
into 30pf loads. PCLK outputs provide better than 1VIns slew
rate into 20pf loads while maintaining ±S% duty cycle.

•
•
•
•
•
•
•
•

Generates up to four processor and six bus clocks, plus
disk, keyboard and reference clocks
Synchronous clocks skew matched to ±2SOps
Output frequency ranges to 100 MHz
Test clock mode eases system design
Selectable multiplying and processor/bus ratios
Stop clock control stops clocks glitch-free
Custom configurations available
3.0V - S.SV supply range
28-pin SOIC package

Applications
•

Ideal for high-speed RISC or CISC systems such as 486,
Pentium, PowerPC, etc.

Block Diagram

1------------------PLL

DISK

CLOCK

KEYBD
GEN

X2~======~~~}---------4
X1 -:-

REF(O,1)
OEN\

FSO~----------~~

PLL

1---+. SYNC I - - - - - t

PCLK(O,3)

1---+.

BCLK(O,6)

CLOCK
FS1~----------~~

REG

GEN

Pentium IS a trademark of Intel Corporation
PowerPC IS a trademark of Motorola Corporation
IICS0159.02evA 122194

C-95

II

ICS91S9-02
Pin Configuration

ICS9159-02 Functionality
T

VOOX

REFO
REF1

X1
X2

VDDF
KEYBD
DISK
VSSF

VSSX
OEN

PClKO
PClK1

BClK5
BClK4

VODP

VDDB

PClK2
PClK3

FSO

*VCO

0
0
-I
I

0
I
0
I

230/33x XI
l76/21x Xl

VSSB

FS1

FSO
VODB

212123x XI
Test mode

XI, REF
(MHz)

PCLK(0,3)
(MHz)

14.31818
14.31818
14.31818
TCLK

50
60
66
TCLKl2

*VCO range is limited from 60 - 200 MHz.

BClK3
BClK2

VSSP

FSI

BClK1
BClKO

28-Pin sOle
K-7

PCLK(0,3)

BCLK(O,S)

DISK

KEYBD

VCO/2
TCLKl2

PCLKl2
TCLKl4

24 MHz
TCLKl4

12MHz
TCLKl8

Pin Descriptions
PIN NUMBER

I PINNAME

TYPE

DESCRIPTION
-~

2

XI

IN

i

X2

OUT
PWR

i

PCLK(0,3)

OUT

VDDP
VSSP

PWR

~-

3
I
4
6.7.9, 10

-r~DDX
VSSX
I

8
II
-----13,12
-15,16,18
19,21.22

I
i
I

17
14.20
5
24
25
23
26
28,27

FS(O.l)
BCLK(0,5)

IN
OUT

XTAL or external reference frequency mput. ThIs mput mcludes XTAL load capacitance and
feedback bIas for a 10 . 30 MHz XTAL
-XTAL output whIch mcludes XTAL load capacItance.
XTAL oscIllator circUIt power supplIes.
Processor clock outputs whIch are a multIple of the mput reference frequency as shown in the
table below. Duty cycle IS 50/50±5% WIth a maxImum frequency of 100 MHz. Custom
multIplymg configuratIOns are aVailable
PCLK power supplIes. VSSP and VDDP power PCLK(0.3) outputs and the mternal PCLK PLL.
Frequency multIplIer select pms See table below. These mputs have mtemal pull-up deVIces.
Bus clock outputs are fIxed at

V2 the PCLK frequency. In all cases, the duty cycle IS 50/50±5%.

VSSB
PWR
IBCLK power supplIes VSSB and VDDB power BCLK(0,5) outputs. Output levels can be
VDDB
.
- - r---------+""stomlzed by connectmg VDDB to voltages less than VDDF
IN
OEN tnstates all outputs when low. ThIs input has an mtemal pull-up deVICe.
OEN
The DISK controller clock IS fixed at 12 MHz_
DISK
OUT
KEYBD
VSSF
VDDF

OUT
PWR

The KEYBD clock IS fixed at 12 MHz.

REF(O,I)

OUT

REF IS a buffered copy of the crystal OSCIllator or reference mput clock,
nominally 14.31818 MHz

I

--

Fixed clock (DISK and KEYBD) output and PLL power supplIes.

Timing Specifications
3.3V ±5% or 5.0V ±5% VOO, 0-70°C, measured at 1.5V, Cload=20pf

PIN
PCLK(0,3)
BCLK(0,5)

1

JITTER cyclecycle

SKEWtoPCLK

SKEW to BCLK

SLEW, LOAD

DUTY CYCLE

<±200ps
<±300ps

<±250ps
<±750ps

<±750ps
<±500ps

>1.0V/ns,20pf
>1.0V/ns,30pf

<±5%
<±5%
-

C-96

I

ICS91S9-02
Absolute Maximum Ratings
Supply voltage .............................. 7.0 V
Logic inputs ................................ GND -O.SV to Voo +O.SV
Ambient operating temp ....................... 0 to +70°C
Storage temperature .......................... -6SoC to +ISO°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics at 3V
Voo=30- 37V
DC Characterlst:ks

PARAMETER

SYMBOL

Input Low Voltage
Input High Voltage
II1put Low Current
Input High Current
Output Low Current

VIL
VIH
IlL
IIH
IOL

Output High Current

IOH

Output Low Current

IOL

Output High Current

IOH

Output Low Voltage

VOL

Output High Voltage

VOH

Output Low Voltage

VOL

Output High Voltage

VOH

Supply Current

Icc

TEST CONDITIONS

VIN=OV
VIN=Voo
VOL=0.8V;
for PCLKS & BCLKS
VOL=2.0V;
for PCLKS & BCLKS
VOL=0.8V;
for fixed CLKs
VOL=2.0V;
for fixed CLKs
IOL=15rnA;
for PCLKS & BCLKS
IOH=-30rnA;
for PCLKS & BCLKS
IOL=12.5rnA;
for fixed CLKs
IOH=-2OmA;
for fixed CLKs
@66.66MHz;
all outputs unloaded

C-97

MIN

TYP

MAX

UNITS
V
V

-

-

0.2Voo

0.7Voo

-

-

-

1O.S
-

28.0
S.O

IlA

-S.O
30.0

47.0

-

rnA

-

-66.0

-42.0

rnA

2S.0

38.0

-

rnA

-

-47.0

-30.0

rnA

-

0.3

0.4

V

2.4

2.8

-

V

-

0.3

0.4

V

2.4

2.8

-

V

-

55

110

rnA

~A

II

ICS9159-02
Electrical Characteristics at 3V

Jitter, Absolute

Tjab

Jitter, One Sigma

Tjis

Jitter, Absolute

Clock Skew

Tsk

Clock Skew

Tsk

250

ps

3

%

2

5

%

50

250

ps

90

500

ps

2.6

5

DB

-250

1

Ordering Information
ICS9159-02M
Example:

les

XXXXTl ~~,
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - Deriee Type (consists of 3 or 4 digit numbers)

' - - - - - - - - - - - PrefIX
Ies, AV =Standard Device; GSP=Genlock Device
PRODUCT PREVIEW documents contain information on product8 in the formative or
deelg" phae of development. Characteristic data and other speclfic.tlor'll are d••lgn
goala. ICS reaervel the right to change or dllcontUlUe thaI product8 without notice.

C·!)S

ICS9160-03

Integrated
Circuit
Systems, Inc.

Product Preview

Frequency Generator and Integrated Buffer for PowerPCTM
General Description

Features

The ICS9160 generates all clocks required for high speed
RISC microprocessor systems based on the PowerPC 603 and
604. Five different frequency multiplying factors are selectable
and offer smooth frequency transitions. BCLK signals are
synchronous to PCLK and operate at PCLKl2 for optimum
synchronous PCI bus performance. The multiplying and ratio
factors can be customed for specific applications.

•

Both individual and group glitch-free stop and start of the clock
signals are provided, as well as a power-down mode to minimize power consumption. The individual stop and start is
provided through a serial interface control.
A global output enable pin simplifies production board testing,
and a test mode is available to aid in system design and
diagnostics.

•
•
•
•
•
•
•
•

Generates four processor and seven synchronous bus
clocks plus graphic, floppy, keyboard and reference clocks
Selectable 33.3/50/60/66.6/80 MHz PCLKs
±l5Ops maximum PowerPC PLL in-band jitter
All synchronous clocks skew matched to ±200ps
Individual or group stop-clock control
Power-down modes minimize standby current
Custom configurations available
3.0V - 5.5 supply range
32-pin SOIC package

Applications
•

Ideal for RISC systems based on the PowerPC 603 and
604 microprocessors.

Block Diagram

~:;~::::::=iiJX~T~A~L~O~S~C[}----------------~

FSO

FS1
FS2

•
"""T----.I
•
•
•
•

>---+- GRAPHIC

..,..----.1

~--------""~I

PLL

1 - - - - - - - - - - 1 JI-.....- FLOPPY

CLOCK

~--------------~ >---~- KEYBD

GEN

~-~

STOPO~----~I

SDATA

>---.....- REFCLK

.>-,r--I.- PCLK{O,3)
>-t~......

BCLK{O,6)

,..----i.~II~s~H~IF;;:T~R:'FE{;'G11-----.1

PowerPC IS a trademark of Motorola Corporabon
IICS9160-03RevB011295

C-99

ICS9160-03
Pin Configuration

VDOX
X1
X2
VSSX
FSO
FS1
FS2
PClKO
PClK1
VDDP
PClK2
PClK3
VSSP
SDATA
STOPO
STOP1

32

1
2
3
4

GRAPHIC
KEYBD
FLOPPY
VDDF
BClK6
BClK5
VSSF
BClK4'
BClK3
VDDB
BClK2
BClK1
VSSB
BClKO
REF
VDDP

31
30
29
28
27
26
25
24

5
6
7
8
9

23
22

10
11
12
13
14
15
16

21
20
19
18
17

32·Pin SOP
K·7

Pin Descriptions
,

PIN
NUMBER

PIN
NAME

TYPE

2

XI

IN

3
I
4
8,9,11

X2
VDDX
VSSX
PCLK(0,3)

OUT
PWR

10,17
13

VDDp,
VSSP

IN

14

SDATA
(First inREFCLK,
PCLK(0,4)
BCLK(0,5)
FLOPPY, KEYBD,
GRAPHIC - last in)

IN

15,16

STOP(O,l)

IN

18
19,21,22,
24, 25, 27, 28
20
23
26
29
30
31
32

REFCLK
BCLK(0,6)

OUT
OUT

VSSB
VDDB
VSSF
VDDF
FLOPPY
KEYBD
GRAPHIC

PWR

OUT

PWR
OUT
OUT
OUT

DESCRlPTION
XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback
bias for a 10-30 MHz XTAL.
XTAL output which mcludes XTAL load capacitance.
XTAL oscillator circuit and REFCLK output power supplies.
Processor clock outputs which are a multiple of the input reference frequency as shown in the table
below. Duty cycle is 50% with a maximum frequency of 100 MHz. Custom multiplying configurations
are aVaIlable.
PCLK power supplies. VDDP powers the internal PCLK PLL and the PCLK(0,3) outputs. Operation at
5.0V±10% or 3.3V±IO% is possible with a maximum PCLK speed of 150 MHz and 100 MHz,
respectively.
Serial stop clock data is clocked in on the rising edge of BCLK. A total of IS hits must be clocked in
using the following protocol. SDATA is sampled on the rising edge of BCLK, so the data generator
should change data on the nsing edge of BCLK to ensure proper communication. SDATA must be low
for one BCLK period as a start bit. The next IS rising edges of SCLK will clock data in serially. The
16th clock enables the serial data to take effect. Outputs associated with serial data bits that are a one
will conlinue without intermption. Clocks associated with serial data bits that are a zero Will be
stopped in the low state glitch-free, that is, no short clocks with the exception of REFCLK which is
asynchronously forced low. This input has an intern'll pull-up device.
Stop clock ~ontrol pins used for glitch-free start and stop of the clock outputs as described in the table
on the next page. These inputs have mternal pull-up devices.
Buffered copy of the crystal reference frequency.
Busplock outputs having selectable frequency based on the FS(0,2) inputs (see table on next page). In
all cases, the duty cycle IS 50%.
BCLK power supplies. VSSB and VDDB power BCLK(0,6).
FIXed clock power supplIes. VSSF and VDDF power GRAPHIC, FLOPPY and KEYBD outputs plus
the fixed clock PLL.
The floppy clock output operates at 24 MHz.
The keyboard clock output operates at 12 MHz.
The graphics system clock output operates at 40 MHz.

C-l00

ICS9160-03
Timing Specifications
3.3V±5%VDD, 0-70°C, measured at 1.5V, Cload=20pf
PIN

JITIERmax*

SKEWtoPCLK

SKEW to BCLK

SLEW, LOAD

DUTY CYCLE

PCLK(0,5)
BCLK(0,3)
FLOPPY
GRAPHIC

<±200ps
<±200ps
<±250ps
<±300ps

<±150ps
<±200ps
nla
nla

<±200ps
<±150ps
nla
nla

>l.OV/ns,20pf
> l.OVIns, 30pf
>0.8V/ns,20pf
>0.8VIns, 20pf

<±500ps
<±500ps
<±5%
<±5%

* Jitter spectrum meets PowerPC PLL natural frequency in band requirements of less than ±15Ops.
5.0V±5%VDD, 0-70°C, measured at 1.5V, Cload=20pf
PIN

JITIERmax*

SKEWtoPCLK

SKEW to BCLK

SLEW, LOAD

DUTY CYCLE

PCLK(0,5)
BCLK(0,3)
FLOPPY
GRAPHIC

<±250ps
<±250ps
<±300ps
<±35Ops

<±15Ops
<±200ps
nla
nla

<±20Ops
<±150ps
nla
nla

>l.OV/ns,20pf
>0.8V/ns,30pf
>0.8V/ns,20pf
>0.8V/ns,20pf

<±500ps
<±500ps
<±5%
<±5%

* Jitter spectrum meets PowerPC PLL natural frequency in band requirements of less than ±150ps.

Functionality
FS2
0*
0*
0
0
1
1
I
I

FSI
0*
0*
1
1
0
0
I
I

FSO
0*
1*
0
I
0
1
0
I

XI,REFCLK
(MHz)
Tristate
14.318
14.318
14.318
14.318
14.318
14.318
TCLK**

PCLK(O,4)
(MHz)
Tristate
Off
33.3
50.0
60.0
66.6
80.0
IfCLKl2

BCLK(0,5)
(MHz)
Tristate
Off
16.6
25.0·
30.0
33.3
40.0
TCLKl4

GRAPHIC
(MHz)
Tristate
40.0
40.0
40.0
40.0
40.0
40.0
TCLKl3

FLOPPY
(MHz)
Off
24.0
24.0
24.0
24.0
24.0
24.0
TCLKl5

KEYBD
(MHz
Tristate
12.0
12.0
12.0
12.0
12.0
12.0
TCLKllO

* The oscillator and all PLLs are stopped to minimIze power consumptIOn in modes '000' and '001.' All outputs mamtain their last stable value in mode
'001.' Control signals STOPO and STOPI can be used to ensure glitch-free sart and stop when entering mode '001,' provided mode '001' is entered after the
clocks have stopped and exited 10ms (maximum PLL lock time) pnor to starting clocks.

** XI is externally driven wtth TCLK in mode' 111.'

Group Clock Control
STOP I

STOPO

SDATA

+
0
0
I
I

+
0
1
0
I

*
I
1
I
I

PCLK(O,1)
Low
Low
Low
Running

PCLK(2,4)
Low
Low
Running
Running

BCLK(0,5)
Low
Runninf(
Running
Running

GRAPHIC,
FLOPPY
Low
Running
Running
Running

Outputs stop and start glitch-free within on clock penod. Outputs will not change state if the PLLs are off.
* Each output can be stopped and started glItch-free as described in the SDATA pin description above.
+SDATA control and STOP(O,!) control are logically ORed for each mdividual clock.

C-lOl

I KEYBD,
REFCLK
Running
Runnin~

Running
Running

ICS9160-03
Ordering Information
ICS9160-03M
Example:

ICS XXXX-PPP M

11
L -_ _ _ _ _ _ _ _
L -_ _ _ _ _ _ _ _ _ _

~~,~

Pattern Nnmber (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV;Standard DeVIce

~~~~~f~:V~r~~~~td~hu::~~rl~gt~l~t!n~~d~~~~r o;P~~~f~cua~~~ t~~ef~~:~~g~l~e~~~
reserves the nght to change or discontinue these products without notice

C-I02

ICS9178-02

Integrated
Circuit
Systems, Inc.

•

240 MHz Clock Generator and Integrated Buffer
for PowerPCTM
General Description

Features

The ICS9178-02 generates all clocks required for high speed
PowerPC RISC microprocessor systems. Generating clocks in
phase with an external reference frequency allows the
ICS9178-02 to be used as a multiplying zero delay buffer.
Three different mUltiplying factors are externally selectable.
These factors can be customized for specific applications. An
external frequency can be directly applied to aid system testing. With 2X processor clock speeds up to 240 MHz, PECL
outputs are provided. User selectable frequency ratios are
available for PCLKlBCLK and PCLKlXCLK. Each pair of
clocks outputs have separate supply pins to minimize output
jitter and allow them to operate at SV, 3.3V or custom
voltage levels.

•
•
•
•
•
•
•
•
•
•

Generates 2 PECL 2x processor, 2 TIL/CMOS Ix processor and 10 selectable bus clocks
2XPCLK ranges from 7S MHz to 240 MHz (SV or
SV/3.3V mixed supply) or 60 to ISO MHz (3.3V only)
Asymmetric duty cycle bus clock for PowerPC
Bus to processor clock skews less than ±2SOps
2XPCLK to PCLK skew controlled at 7S0 ±SOOps
Selectable reference multiplying factors
Selectable PCLKlBCLK and PCLKlXCLK ratios
Separate supplies allow SV and 3.3V output mix
3.0V - S.SV supply range
44-pin PQFP package

Applications
•

Ideal for high-speed systems based on PowerPC

Block Diagram

FBCLK
REFCLK
TCLK

- -~- - - - - - - - - - - - - - - - - - - - - ..... 1

I
I
I

I

TEN\

I

MS(O,1)

I

RESEn
XAS(O,1)
XBS(O,1)
XCS(O,1)

~

PLL

~

CLOCK

~

GEN

~

I
I
I

...

I
I

::.....

.,"'

.....

.

.
I

~

REG

l"

CLOCK
SELECT

I

TRISTATE

- -------- I - -

I
I
I
I

".....

SYNC

I

I
I

;:

-L

-

r:-l

I

"'

- - - - f- -

I
I
I

2XPCLK(O,1 )
PCLK(O,1)
ABCLK
BCLK(O,1)
DCLK

XCLKA(O,1)
XCLKB(O,1)
XCLKC(O,1)

PowerPC IS a trademark of Motorola Corporation
IICS9178.02orgRevA120894

C-I03

a

II

ICS9178-02
Pin Configuration

*VCo range is limited from 75- 240 MHz at 5V ±5% and 60
- 150 MHz at 3.3V ±5%. Divide ratios assume BCLK is
externally feedback to FBCLK.

44 43 42 41 40 39 38 37 36 35 34
VDDXBA
XClKB1
XClKBO
VSSXBA
XCLKA1

o I
2

33

3

31

XCLKAO

6
7
8

VDDP
VSSP
RESE1\
PCLK1
PCLKO

~

4

~

5

29
2B
ZT
26
25

ICS9178-02

9

24
23
12 13 14 15 16 17 18 19 20 21 22

VDD
XASO
XAS1
XBSO
XBS1
XCSO

Rising edge of ABCLK is coincident with rising edges of
2XPCLK, PCLK and other BCLKs.
X_Sl

X_SO

XCLK_(O,I)

0
0

0

1
1

0
1

PCLK
BCLK
DCLK
Tristate

XCS1

AVSS
AVDD
EVDO
EVSS

1

_=A,B,C

44-Pin PQFP
K-11

ICS917S-Q2 Functionality
MSI
-~

0
0
1
1
X

0
0
1
1

I

MSO

RS1\

TEN

*vco

2XPCLK

PCLK

ABCLK (H/L%)

BCLK

DCLK

!

0

1
1
1
1

0
0
0
0
X
1
1
1
1

6xXl
8xXl
12xXl
X
X
TCLK
TCLK
TCLK
TCLK

VCO
VCO
VCO
1
0
TCLK
TCLK
TCLK
TCLK

VCO/2
VCO/2
VCO/2
1
0
TCLKl2
TCLKl2
TCLKl2
TCLKl2

VCO/6 (66/33)
VCO/8 (75125)
VC0l12 (66/33)
1
0
TCLKl6 (66/33)
TCLKl8 (75/25)
TCLKl12 (66/33)
TCLKl2

VCO/6
VCO/8
VCO/12
1
0
TCLKl6
TCLKl8
TCLKl12
TCLKl2

VCOl12
VCOl16
VCO/24
1
0
TCLKl12
TCLKl16
TCLKl24
TCLKl2

1

0
1
X
0
1
0
1

0
1
1
1
1

C·104

II

ICS9178-02

Pin Descriptions
PIN NUMBER
32
31
6
5
30
29
3
2
1
4
44
43
42
41
2S
27
11
10
S
7
22
21
24
23
20
3S*
37*
36
35
25
26
19
16
17
15
14
13
12
IS
40
39
9
33
34

PIN NAME
XASO
XASI
XCLKAO
XCLKAI
XBSO
XBSI
XCLKBO
XCLKBI
VDDXBA
VSSXBA
VSSXC
XCLKCO
XCLKCl
VDDXC
XCSO
XCSI
PCLKO
PCLKI
VSSP
VDDP
2XPCLKO
2XPCLKI
EVDD
EVSS
EVSS
MSO
MSI
FBCLK
REFCLK
AVDD
AVSS
DCLK
VDDD
VSSD
BCLKO
BCLKI
VSSBAB
VDDBAB

-~

ABCLI<
TCLK
TEN
RESE1\
VDD
VSS

TYPE
Input
Input
Output
Output
Input
Input
Output
Output
-

Output
Output
-

Input
Input
Output
Output
-

Output
Output
-

-

Input
Input
Input
Input
-

Output
-

Output
Output
-

Output
Input
Input
Input
-

DESCRIPTION
LSB Programmable Group A frequency selector
MSB Programmable Group A frequency selector
TIUCMOS group A programmable clock output
TIL/CMOS group A programmable clock output
LSB Programmable Group B frequency selector
MSB Programmable Group B frequency selector
TIUCMOS Group B programmable clock output
TTUCMOS Group B programmable clock output
Power for programmable Group A and B buffers (Pins 2, 3, 5, 6)
Ground for programmable Group A and B buffers (Pins 2 3 5 6)
Ground for the programmable Group C buffers (Pins 42 and 43)
TTUCMOS Group C programmable clock output
TTUCMOS Group C programmable clock output
Power for the XC signal output buffers (Pins 42 and 4:3)
LSB Programmable Group C frequency selector
MSB Programmable Group C frequency selector
TIL/CMOS IX Processor clock output
TTUCMOS IX Processor clock output
Ground for PCLK output buffers (Pins 11 and 10)
Power for PCLK~output buffers (Pins 11 and 10)
PECL 2X Processor clock output
PECL 2X Processor clock output
Power for PECL buffers (Pins 21 and 22)
Ground for PECL buffers (Pins 21 and 22)
Ground for PECL buffers (Pins 21 and 22)
LSB frequency select PLL (divider mode control)
MSB frequency select PLL (divider mode control)
External PLL feedback path from one of the BCLK outputs
External reference clock mput
Power for the analog PLL circuitry
Ground for the analog PLL circUltrv
TILlCMOS D clock output
Power for D output buffers (Pin 19)
Ground for D output buffer (Pin 19)
TTUCMOS B (Bus) clock output
TTUCMOS B (Bus) clock output
Ground for output buffers AB and B clocks (Pins 14, 15 & IS)
Power for output buffers AB and B clocks (Pins 14 15 & IS)
TILlCMOS AB Bus clock (has Asymmetric w leve~rECL output voltage
VOLP
2XPCLK
InDut high current
Vrn=VDD
IIH
Input low current (MSX pins. pull-up)
VIL=OV
hLl
Input low current (other inputs)
VIL=OV
IIL2
I(tristate)
Output leakal!:e current (XCLKs)
Ioz
Power supply current
@240MHzon
IDD
2XPCLK
IDD-TYP @75MHzon
rN~er Is)upply current (typical)
ote I
2XPCLK
Input capacitance (Note I)
CIN

MIN
2.0

TYP

0.8
2.4
0.4
2.2

2.5
0.3

-10

UNITS
V
V
V
V
V

0.6

V

10
-150

lUI

~a

10

ua
~a

145

10
165

rna

80

90

rna

8

pf

-10
-10

Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.

C·I06

MAX

II

ICS9178-02

AC Characteristics
VDD --+5V -+5% , O°C -< TAMBIENT -< +70°C unless otherwise stated
PARAMETER

SYMBOL

TEST CONDITIONS

Input Frequency (Note 1)
Input Clock Rise time (Note 1)
Input Clock Fall time (Note 1)
Output Frequency (2XPCLK)

f,
ICLKr
ICLKf
f o2XPCLK

6Xmode

Output Frequency (2XPCLK)
Output Frequency (2XPCLK)
OU,Jrut Rise time, O.S to 2.0V
20 0 to SO% (Note 1)
Fall Time 2.0 to O.S
SO% to 20% (Note I)
Output Rise time 80% to 20% (Note I)
Output Fall time SO% to 20% (Note I)
Duty cycle 2XPCLK (Note 1)

f o2XPCLK
f o2XPCLK
tr2XPCLK

SXmode
12Xmode
15pfload

tf2XPCLK

15pfload

t(TIL)r
I(TILlf
dtl

Duty cycle 2XPCLK (Note I)

dt2

Duty cycle ABCLK (Note 1)

dt3

Duty cycle ABCLK (Note I)

dt4

Duty clcle TTL (other clocks)
(Note )
Jitter I Sigma 2XPCLK
I (10,000 samples) (Note 1)
Jitter I Sigma IXPCLK B & D
(10,000 samples) (Note 1)
Jitter I Sigma AB clock
(10,000 samples) (Note 1)
Jitter Absolute 2XPCLK (Note 1)

dts

Jitter AbSolute IXPCLK, B,
D clocks Note I)
Jitter Absolute AB clock (Note 1)

Tjlsl
Tjls2
Tjls3
Tjabsl
Tjabs2
Tjabs3

MIN

TYP

MAX

UNITS

S

40.0

-

-

-

-

50.0
3
3
240
(I50@3.3V)

MHz
ns
ns
MHz

-

MHz
MHz
ns
ns
ns
ns
ns
ns
%

(60@;t
75

VDD
75
75

-

-

-

-

42.5

50

1.2
2.0
1.2
2.0
3.0
3.0
57.5

40

50

60

%

70

75

SO

%

61

66

71

%

45

50

55

%

240 MHz on

-

40

-

ps

240 MHz on

-

50

-

ps

240 MHz on

-

60

-

ps

240 MHz on

-150

SO

+150

ps

240 MHz on

-200

110

+200

ps

240 MHz on

-250

120

+250

ps

-

15pfload
15pfload
200 to 240 MHz @ IAV
110 ohm, 15pfload
160 to 200 MHz @ IAV
100 ohm, 15pfload
15Ji,fload @ IAV
S mode)
15Ji,f load @ IAV
(6 and 12X mode)
15pfload @ IAV
for 200 to
2XPCLK
for 200 to
2XPCLK
for 200 to
2XPCLK
for 200 to
2XPCLK
for 200 to
2XPCLK
for 200 to
2XPCLK

C-107

-

-

II

ICS9178-02
AC Characteristics (continued)
VDD =+5V +5%
<
- +70°C unless otherwise stated
- , DoC = Vss and <=VDD.

D-4

II

ICS1694A

DC Characteristics (O°C to 70°C)
SYMBOL

PARAMETER

MIN

MAX

UNITS

CONDITIONS

S.OV±S% OPERATION
VDD

Operating Voltage Range

4.75

5.25

V

VIL

Input Low Voltage

Vss

0.8

V

VDD-5V

VlH

Input High Voltage

2.0

VDD

V

VDD=5V

ILH

Input Leakage Current

--

10

IlA

VIN=Vee

VOL

Output Low Voltage

--

0.4

V

IOL=4.0mA

VOH

Output High Voltage

2.4

--

V

IOH =4.0 rnA

IDD

Digital Supply Current

--

30

rnA

IAA

Analog Supply Current

8

rnA

VDD = 5V, VCO = 120 MHz

Cm

Input Pin Capacitance

--

8

pF

Fe = I MHz

COUI

Output Pin Capacitance

--

12

pF

Fe= I MHz

VDD = 5V, VCO = 120 MHz

3.3V + 10% OPERATION
IDD

Digital Supply Current

-

20

rnA

VDD = 3.3V, VCO = 120 MHz

IAA

Analog Supply Current

-

6

rnA

VDD = 3.3V, VCO = 120 MHz

If the OE option is used, !DD will be the sum of both the digital and analog supply currents.

AC Timing Characteristics
The following notes apply to all ofthe parameters presented in this section:

I.
2.
3.
4.
5.

Xtal Frequency = 14.318 MHz, unless otherwise noted.
All units are in nanoseconds (ns).
Rise and fall time is between 0.8 and 2.0 VDC at 5.0V.
Output pin loading = 15pF
Duty cycle is measured at I.4V at 5.0V.
6. Temperature Range = 0 °C to 70°C

S.OV±S% OPERATION
SYMBOL

PARAMETER

MIN

MAX

NOTES

MCLK AND VCLK TIMING
Tr
Tf
Dc
Fm

--

Rise Time
Fall Time
Duty Cycle
Maximum Frequency

-45

2
2
55
180

%

MHz

3.0V ± 10% OPERATION
SYMBOL

PARAMETER

MIN

MAX

NOTES

MCLK AND VCLK TIMING
Tr
Tf
Dc
Fm

--

Rise Time
Fall Time
Duty Cycle
Maximum Frequency

--

45

D-S

3
3
55
120

%
MHz

ICS1694A
Standard Frequency Patterns (MHz)
Table 1
PINS

FUNCTION

PATTERNS
010

011

012

013

014

015

016

017

8

OUTl

24

25

12

6

24

24

XTAL

XTAL

7

OUT2

40

40

40

60

40

XTAL

16

12

6

OUT3

30

30

30

20

20

40

24

24

25

25

25

25

14.318

14.318

14.318

14.318

5

VSS

4

XTAL2

3

XTAL1

2

AVDD/OE

1

VDD

PINS

FUNCTION

8
7
6

!

OUTl

I

OUT2
OUT3

5

VSS

4

XTAL2

3

XTALl

2

AVDD/OE

1

VDD

E

PATTERNS

-

8

Ordering Information
ICS1694AN-XXX

or ICS1694AM-XXX

Example:

T
T
1

ICS XXXX M -XXX

~ Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
N;DIP (I'lastic)
M;SOIC

' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - Prefix
ICS, AV;Standard Device; GSP;Genlock Device

PRODUCT PREVIEW documents contain mfonnauon on products III the fannatlve or deSIgn phase
of development Charactenstlc data and other specIficatIOns are deSign goals ICS reserves the nght to
change or d,scontmue these products without notice

D-6

•

AV9110

Integrated
Circuit
Systems, Inc.

Serially Programmable Frequency Generator
General Description

Features

The AV9110 generates user specified clock frequencies using
an externally generated input reference, such as 14.318 MHz
or 10.00 MHz crystal connected between pins I and 2. Alternately, a TTL input reference clock signal can be used. The
output frequency is determined by a 24-bit digital word entered
through the serial port. The serial port enables the user to
change the output frequency on-the-fly.

•
•
•
•
•
•
•
•
•

The clock outputs utilize CMOS level output buffers that
operate up to 130 MHz.

Complete user programmability of output frequency
through serial input data port
On-chip Phase-Locked Loop for clock generation
Generates accurate frequencies up to 130 MHz
Tristate CMOS outputs
5 volt power supply
Low power CMOS technology
14-pin DIP or 150 mil sorc
Very low jitter
Wide operating range VCO

Applications
Graphics: The AV9110 generates low jitter, high speed pixel
(or dot) clocks. It can be used to replace multiple expensive
high speed crystal oscillators. The flexibility of this device
allows it to generate non-standard graphics clocks, allowing
the user to program frequencies on-the-fly.

Block Diagram
D7-D13
D17, D1B

VCO
OUTPUT
DIVIDER

R =1, 2, 4or8

D22

ClKIX

OE __________________________________~~----~

IAV9110RevA111594

D·7

AV9110
Pin Configuration
Clock Reference Implementations:
X1
AVDD

AGND
VDD
GND

2
3
4
5

DATA

6

SClK

7

X2

AV9110-01 vs. AV911 0-02

13

OE

12

ClK

11
9

VDD
GND
ClKlX

8

CE

The AV91l0 requires a stable reference clock (5 to 32 MHz) to
generate a stable, low-jitter output clock. The AV91l0-01 is
optimized to use an external quartz crystal as a frequency
reference, without the need of additional external components.
The AV91l0-02 is optimized to accept an TTL clock reference.
Either device can be used with an external crystal or accept a
TTL clock reference, although extra components may be required. The various combinations implied are summarized in
Figure 2 (see page 7).

,...(\1

~~
,...
,... ,...
,...
0)0)

~~

10

14-Pin DIP, sOle
K-3, K-6

Pin Descriptions
PIN
NUMBER
I
2
3
4
5

6
7

8
9
10
11
12
13
14

PIN
NAME
XI
AVDD
AGND
VDD
GND
DATA
SCLK
CE
CLKIX
GND
VDD
CLK
OE
X2

PIN
TYPE
Input
Power
Power
Power
Power
Input
Input
Input
Input
Power
Power
Output
Input
Input

DESCRIPTION
Crystal input or TTL reference clock
ANALOG power supply. Connect to +5V
ANALOG GROUND
Digital power supply. Connect to +5V
Digital GROUND
Serial DATA pin
SERIAL CLOCK. Clocks shift register
CHIP ENABLE. Active low, controls data transfer
CMOS CLOCK divided by X output
Digital GROUND
Digital power supply. Connect to +5V
CMOS CLOCK output
OUTPUT ENABLE. Tristates both outputs when low
Crystal input or TTL reference clock

D-8

II

AV9110

Absolute Maximum Ratings
AVDD, VDD referenced to GND ............... 7V
Operating temperature under bias ............... O°C to +70°C
Voltage on 110 pins referenced to GND ........... GND -0.5V to VDD + 0.5V
Power dissipation ............................ 0.8 Watts
Storage temperature .......................... -65°C to + 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics
ViDD=+

-

0

un ess 0 therwlse stated

to

·A=

! .• ::'••;"~j;'~";'.'

i'"

PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Input Clock Rise Time
Input Clock Fall Time
Supply Current
..
'.'
..:.
'

....

'

SYMBOL
VIL
Vm

IlL

::

....

1m
VOL
VOH
ICLKr
ICLKf
IDD

~lC~·
. .. ""
'.
'"
TEST
CONDITIONS
MIN
..

'

VDD=5V
VDD=5V
VIN=OV
VIN= VDD
IOL= 8mA
IOH= 8mA

Output frequency range
Rise time, 20-80%
Fall time, 80-20%
Duty cycle
Jitter, 1 sigma
Jitter, absolute
Input reference freq.; AV9110-01
Input reference freq.; AV9110-02
Input DATA or SCLK frequency

fa
tr
tf
dt

fREF
fREF
fDATA

Crystal input
TTL input

D-9

.:.: ...•

TYP

MAX

UNITS

-

0.8

V
V

-

-

-

25

-5
5
0.4
20
20

2.4
-

No load

25pFIoad
25pFIoad
25pFIoad

~;:;

2.0

-

.: .... ..•••.. .A~~IC..
••••

..

.'

-

.,~

.0

-

0.78
-

-

-

-

40

5
0.6

±40
±125
14.318
14.318

'.

...
130
3
3
60
32
32
32

IJA
IlA
V
V
ns
ns
mA
.0

MHz
ns
ns
%
ps
ps
MHz
MHz
MHz

II

AV9110
Serial Programming
The AV9110 is programmed to generate clock frequencies by
entering data through the shift register. Figure I displ~ the
proper timing sequence. On the negative going edge of CE, the
shift register is enabled and the data at the DATA pin is loaded
into the shift register on the rising edge of the SCLK. Bit DO is
loaded first, followed by D I, D2, etc. This data consists of the
24 bits shown in the Shift Register Bit Assignment in Table I,
and therefore takes 24 clock cycles to load.

An internal counter then disables the input and transfers the data
to internal latches on the rising edge of the 24th cycle of the
SCLK. Any data entered after the 24th cycle is ignored until CE
must remain low for a minimum of 24 SLCK clock cycles. If
CE is taken high before 24 clock cycles have elapsed, the data
is ignored (no frequency change occurs) and the counteris reset.
Tables I and 2 display the bit location for generating the output
clock frequency and the output divider circuitry, respectively.

Table 1: Shift Register Bit Assignment
ASSIGNMENT

BIT
0
1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

I

EQUATION
VARIABLE

VCO frequency divider (LSB)

..

N
Integer

"
"
"

"
VCO frequency divider MSB)
Reference frequency divider

-M
Integer

"
"
"

"

"
Reference frequency divider
VCO pre-scale divide (O=divide by I, 1= divide by 8
CLKlX output divide CODO (see Table 2)
CLKlX output divide CODO (see Table 2)
VCO output divide VODO (see Table 2)
VCO output divide VODO (see Table 2)
Output enable CLK (O=tristate)
Output enable CLKlX (O=tristate)
Reserved. Should be programmed low (0)
Reference clock select on CLK (1 = reference frequency)
Reserved. Should be programmed high (I)

D·lO

-

=:J

V

]

X

]

R

DEFAULT
-01
-02
1
1
1
1
1
1
1
0
I
0
0
1
0
0
0
0
1
0
1
I
1
1
0
1

1
1
1
1
1
1
1
0
I
0
0
1
0
0
0
1
0
0
1
I
1
1
0
1

BIT
0
1
2
3
4
5
6
7
8
9
10
11

12
13
14
15
16
17
18
19
20
21
22
23

II

AV9110

Output Divider Truth Tables

Table 3

Table 2
CLKIX
Output Divide
COD1

CODO

(X)

VOD1

VODO

0
0
1
1

0
1
0
1

1
2
4
8

0
0
1
1

0
1
0
1

VCO
Output Divide
(R)
1
2
4

8

Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
fREF =Input reference frequency

2 MHz < fREF < 32 MHz
fREF

200kHz <

~5MHz

M

50 MHz < fvco < 250 MHz

=Reference divide, 3 to 127

fvco

=VCO output frequency

fCLK =CLK or CLKIX output frequency

fvco < 250 MHz

The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
N. V. fREF
fvco -----=-0--M

where

N

=VCO divided, 3 to 127

M = Reference divide, 3 to 127
V = Pre scale, 1 or 8

The 2 output drivers then give the following frequencies:
fvco

fCLK =

fCLKIX

or fREF (output muxable by bit 17)

R

=

fvco

fVCLK

R.X

X

Where R, X

=output dividers 1,2,4 or 8

Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater.
This will give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.

D·ll

AV9110

---I.~ t. u11 ........I - - -

===

==X.....,;D;:2;::,3--,X DON'T CARE

Figure 1 - Serial Programming

ACTiming

Jitter

Parameter

Minimum time (ns)

tsul
tsu2
thl
th2

10
10
10
10

For high performance applications, the AV9110 offers extremely low jitter and excellent power supply rejection. The one
sigma jitter distribution is typically less than ±125ps. For
optimum performance, the device should be decoupled with
both a 2.21lF and a O.IIlF capacitor. Refer to Recommended
Board Layout diagram on page 8.

Frequency Acquisition Time

Output Enable

Frequency acquisition (or "lock") time is the time that it takes
to change from one frequency to another, and is a function of
the difference between the old and, new frequencies. The
AV9110 can typically lock to within 1% of a new frequency in
less than 200lls. This is also true with power-on.

The AV9110 outputs can be disabled with either the OE pin or
through serial programming. Setting the OE pin low tristates
CLK and CLK/X. Alternatively, setting bits D19 and D20 low
in the serial word will tristate the two outputs. Both the OE pin
and D 19 or D20 must be high to enable an output.

Power-On Reset

Frequency Transition Glitches

Upon power-up the internal latches are preset to provide the
following output clock frequencies (14.318 MHz reference
assumed):

The AV9110 starts changing frequency on the rising edge of the
24th serial clock. If the programming of any output divider is
changed, the output clock may glitch before locking to the new
frequency in less than 200ils with no output glitches (no partial
clock cycles).

AV9110-0l
AV9110-02

CLK output

CLK/X output

25.175 MHz
25.175 MHz

6.29 MHz
12.59 MHz

These preset default frequencies can be changed with a custom
metal mask, as can other attributes.

D·l2

II

AV9110
Toyocom

AV9110 Quartz Crystal Selection
When an external quartz crystal will be used as a frequency
reference for the AV91l0, attention needs to be given to crystal
selection if accurate reference frequency and output frequency
is desired. The AV91l0 uses a Pierce oscillator design which
operates the quartz crystal in parallel-resonant mode. It requires
a quartz crystal cut for parallel-resonant operation to ensure an
accurate frequency of oscillation (a less expensive series-resonant crystal can be used with the device but it will oscillate
approximately 0.1% too fast). The AV91l0-0l has internal
crystal load capacitors which result in a total crystal load
capacitance of approximately 12pF±1 0%. The AV91l0-02 does
not have internal load capacitors, but contributes about 3pF
load capacitance to the crystal.

Part Number
TN4-30374 .......
TN4-30375 .......
TN4-30376 .......
TN4-30377 .......

14.318 MHz surface mount crystal
20 MHz surface mount crystal
14.318 MHz through-hole crystal
20 MHz through-hole crystal

Epson

Part Number
MA-505 or ...... Surface mount crystal
MA-506
CA-301. ......... Through-hole crystal

Following is a list of recommended crystal devices for the
AV91l0. They have been tested by the crystal manufacturer to
operate suitably with the AV91xx-series crystal oscillator design, having load capacitance characteristics that are compatible with the AV91l0-0l.

X2

TTL
REFERENCE
SOURCE

AV911 0-01
X1

01 ~F

-l:

X2

~~ J:"""
2000 ~~ -=

AV911 0-01
Xl

-=-Using AV911 0-01 with a crystal

c::I :f:
_
::L
T -

Using AV911 0-01 with an external clock

X2

TTL

AV911 0-02

NC

X2

REFERENCE
SOURCE

X1

AV9110-02

Xl

Using AV911 0-02 with a crystal

USing AV911 0-02 with an external clock

Figure 2 - Clock Reference Combinations

0-13

II

AV9110
AV911 0 Recommended Board Layout

/GaPin
/'
ground plane

To

(

('--_--')t----~)

)

~

W

-SYSTEM GROUND

= connection to
ground plane

This is the recommended layout for the AV9110 to maximize clock performance. Shown are the power and ground connections,
the ground plane, and the input/output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise
from coupling to the AV9110. As when compared to using the system ground and power planes, this technique will lessen output
clock jitter. The isolated ground plane should be connected to the system ground plane at one point near the 2.2f.tF decoupling
cap. For lowest jitter performance, the isolated ground plane should be kept away from clock output pins and traces. Keeping the
isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between the isolated ground
plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line is optional, but will help reduce EM!.
The traces to distribute the output clocks should be over an unbroken system ground or power supply plane. The trace width
should be about two times the thickness of the PC board between the trace and the underlying plane. These guidelines help
minimize clock jitter and EM! radiation. The traces to distribute power should be as wide as possible.

D-14

II

AV9110

60.00

AV911 0 Typical Duty Cycle
VCO Output Divide, R = 1
Duty Cycle will improve if R > 1

58.00
56.00
54.00
52.00
0~

50.00
48.00
46.00
44.00
42.00
40.00
0

20

40.00

40

60

MHz

80

100

120

140

AV911 0 Idd
CL=OpF,R=1

35.00
30.00
25.00

80
<200,<800
<100,>267
<10
<10
<150
< 150 cyc-to-cyc

%VDD
kOhm
MHz
ms
Ohm
ps
ps
%

PinOE
PinOE
Pin RCLK
To 0.1%
Pin RCLK
I Equal load
Pin RCLK
Vptp/2

rnA

Unloaded

IDD

50±5
<40

Functionality
VDD=3.3V±10%, TEMP=O-70°C

Option

RCLK
Ratio

Xl,X2
(MHz)

OE

RCLK
(MHz)

PCLK
(MHz)

-01

56/3

14.31818
14.31818
10-20

1
0
1

267.27
Tristate
nlm*xl

-

-xx

nlm

-

RCLKIN
RAMBUS IS a trademark of Rambus, tnc.

IICS9111. 10 MHz
For CLKI <10 MHz
Note I
AV9170-0I -04
AV9170-0I - OS
Note 2,4.
Input rise time <5us
Note 2,4.
Input rise time -"IrM.......- r - - - - - I

2

7 1---+----'
AV9170

REFERENCE
CLOCK

....----l 3

4

33Q

6 I - - -.........-'Y\NI,-...
5

I
I

-=
Figure 10: AV9170 Recommended Circuit Configuration
(arbitrary configuration of CLK! feedback and pin 4, 5 logic states)

0-34

Application Note

AV9170

(

PIN 1

)

(

)

(

~

(

)

@

.
O.1.uF~

~

)~

(

)

(

)

)

:;:: connection to
ground plane

Figure 11: AV9170 Board Layout
Summary
The AV9170 is extremely flexible and provides utility in a wide
range of system clock and other applications, not limited to
those discussed in this application note. A related product is the
AV9l73, which is designed for video genlock (clock recovery)
applications. Please refer to the AV9l73 data sheet. The
AV9170 may have applications in similar circuits as well. If
this application note does not answer all of your AV9170
questions, please call ICS's applications department.

D-35

To System
VDD

D-36

•

AV9172

Integrated
Circuit
Systems, Inc.

Advance Information

Low Skew Output Buffer
General Description

Features

The AV9172 is designed to generate low skew clocks for clock
distribution in high-performance PCs and workstations. It uses
phase-locked loop technology to align the phase and frequency
of the output clocks with an input reference clock. Because the
input to output skew is guaranteed to ±500ps, the part acts as
a "zero delay" buffer.

•

The AV9172 has six configurable outputs. The AV9172-01
version has one output that runs at the same phase and frequency as the reference clock. A second output runs at the same
frequency as the reference, but can either be in phase or 1800
out of phase from the input clock. Two outputs are provided
that are at twice the reference frequency and in phase with the
reference clock. The final outputs can be programmed to be
replicas of the 2x clocks or non-overlapping two phase clocks
at twice the reference frequency. The AV9172-01 operates with
input clocks from 25 MHz to 50 MHz while producing outputs
from 25 MHz to 100 MHz.
The use of a phase-locked loop (PLL) allows the output clocks
to run at multiples of the input clock. This permits routing of
a lower speed clock and local generation of a required high
speed clock. Synchronization of the phase relationship between the input clock and the output clocks is accomplished
when one output clock is connected to the input pin FBIN. The
PLL circuitry matches rising edges of the input clock and
output clocks.

•
•
•
•
•

•
•
•
•
•
•

AV9172-07 input is 66 MHz with 66 and 33 MHz output
buffers
AV9172-01 is pin compatible with Gazelle GA1210E
±250ps skew (max) between outputs
±500ps skew (max) between input and outputs
Input frequency range from 25 Mhz to 50 MHz
Output frequency range from 25 MHz to 100 MHz
Special mode for two-phase clock generation
Inputs and outputs are fully TTL-compatible
CMOS process results in low power supply current
High drive, 25mA outputs
Low cost
l6-pin SOlC (300 mil) or l6-pin PDIP package

The AV9172 is fabricated using CMOS technology which results
in much lower power consumption and cost compared with the
gallium arsenide-based GA12IOE. The typical operating current
for the AV9172 is 50mA versus l20mAfor the GA12IOE.
ICS offers several versions of the AV9172. The different devices are shown below:
PART
AV9l72-0l
AV9l72-03
AV9 172-07

DESCRIPTION
Second source ofGAl210E
Clock doubler and buffer
Clock buffer for 66 MHz input

Block Diagram

h:+.... OO
hr--.... 0 1
FBIN
ClKIN
DIVide

I

INV'~
I

EN2~

I

1--11--+02

logic

1--=1--+03
Control

logic

'--------'

1--it--+05

IAV9172RevA093094
D-37

ID

II

AV9172
Pin Configuration
GND
GND
INV1
EN2
FBIN
elKIN
VDD
VDD

2
3
4
5
6
7

Configuration Table for AV9172-01

....

0

I

....N
....
0)

~

8

16-Pin

14
13
12
11
10
9

VDD
05
04
03
02
01
00
GND

sOle or 16-Pin PDIP
K-6, K-4

EN2

INV

QO

QI

Q2

Q3

Q4

Q5

0
0
I
I

0
I
0
I

IX
IX
IX
IX

IX
IX
IX
IX

2X
2X
2X
2X

2X
2X
2X
2X

2X
2X
01
01

2X
2X
02
02

NOTES:
1. IX designates that the output is a replica of CLKIN
2. 2X designates that the output is twice the frequency of
CLKIN. and in phase
3. IX means that the output is at the same frequency and
180°C out of phase (inverted) from CLKIN
4. 01 will produce a 1/4 duty cycle clock of CLKIN
5. 02 will produce a 1/4 duty cycle clock delayed 180°
fromCLKIN

Pin Description for AV9172-01
PIN NUMBER
I
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16

PIN NAME
GND
GND
INV
EN
FBIN
CLKIN
VDD
VDD
GND
QO
QI
Q2
Q3
Q4
Q5
VDD

DESCRIPTION

TYPE

Input
Input
Input
Input

Output
Output
Output
Output
Output
Output

-

GROUND
GROUND
INV Inverts QI when low
EN converts Q4 and Q5 to~hase clocks when high
FEEDBACK INPUT from output QO
INPUT for reference clock
Power supply (+5V)
Power supply (+5V)
GROUND
QO phase and frequency same as input (IX). Feed back to pin 5.
Q I is a Ix clock in phase or 180° out of~hase with input
Q2 twice the frequency of QO (2x)
Q3 twice the frequency of QO (2x)
Q4 is either a 2X clock or a two-phase clock - see configuration table
Q5 is either a 2X clock or a two-phase clock - see configuration table
Power supply (+5V)

D-38

AV9172
Timing Diagrams for AV9172-01
INPUT . . . r - L r l . J

EN2 = 0 INV1 = 0
FBIN =00

lOW

INV1

LOW

EN2

INPUT - - - . elKIN

05
04
03
02

00...r-Lrl.J

01
00

02 n . r l . f " U l . . r

FBIN

01"""'L-..n..JL

03n.rl.f"Ul..r
04n.rl.f"Ul..r
05n.rl.f"Ul..r

INPUT . . . r - L r l . J

EN2 =0 INV1 = 1
FBIN =00

05
04
03
02
01

00...r-Lrl.J
01...r-Lrl.J

02 n . r l . f " U l . . r

00
FBIN

03 n . r l . f " U l . . r
04n.rl.f"Ul..r
05n.rl.f"Ul..r

EN2 = 1 INV1 =0
FBIN =00

INPUT . . . r - L r l . J

05
04
03
02
01

00...r-Lrl.J

01"""'L-..n..JL
02 n . r l . f " U l . . r

00

03 n . r l . f " U l . . r

04~
05~

=

EN2 1 INV1
FBIN =00

INPUT . . . r - L r l . J

=1
05
04
03
02
01

00...r-Lrl.J
01...r-Lrl.J

02 n . r l . f " U l . . r

00

03 n . r l . f " U l . . r

04~
05~

D-39

II

AV9172
Pin Configuration

Configuration Table for AV9172-03
(33 MHz input, all frequencies in MHz.)

GND
GND
INV1
EN2
FBIN
elKIN
VDD
VDD

2
3
4
5
6
7

C")

0
I
N

....
,..
0)
;(

8

EN2 INV*

VDD
05
04
03
02
01
00
GND

15
14
13
12
11
10
9

0
1
0
1

0
0
1
1

16-Pin sOle or 16-Pin PDIP
K-6, K-4

Timing Diagram for AV9172-03

EN2

05
04
03
02
01
00

INV1

INPUT
33 MHz

00-05

FBIN

03-05
(If 33 MHz modes selected)

D-40

QO
66
66
66
66

Ql
66
66
66
66

Q2
66
66
66
66

Q3
66
66
33
33

Q4
66
66
33
33

Q5
66
33
66
33

II

AV9172
Configuration Table for AV9172-07

Pin Configuration

(66 MHz input, all frequencies in MHz.)

GND
GND
INV1
EN2
FBIN
elKIN
VDD
VDD
16-Pin

2
3
4
5
6
7

8

....
....
.....

0I
N

Q)

~

16
15
14
13
12
11
10
9

EN2 INV*

VDD
05
04
03
02
01
00
GND

0
0
1
1

0
1
0
1

QO
66
66
66
66

Ql
66
66
66
66

Q2
66
66
66
66

Q3
66
66
33
33

sOle or 16-Pin PDIP
K-6, K-4

Timing Diagram for AV9172-07

05
04
03
02
01
00

INPUT
66 MHz

00· 05

.Jl..fl..f1...r
.Jl..fl..f1...r

03·05
(If 33 MHz modes selected)

D·41

Q4
66
66
33
33

Q5
66
33
66
33

II

AV9172
Absolute Maximum Ratings
VDD referenced to GND ......................
Operating temperature under bias ...............
Storage temperature ..........................
Voltage on I/O pins referenced to GND ...........
Power dissipation ............................

7V
O°C to 70°C
-65°C to + 150°C
GND -0.5V to VDD +n.5V
0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics
VDD =+5V±5%, TA=O°C to 70°C unless otherwise stated

DC Cbaraeterisdes
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Supply Current

SYMBOL
VIL
VIH
IlL
IIH
VOL
VOH
IDD

TEST CONDmONS
VDD=5V
VDD=5V
VIN=OV
VIN=V
IOL=25rnA
IOH=-25rnA
Unloaded

MIN

TYP

MAX

UNITS

2.0
-5
-5
-

-

O.S
5
5
O.S

V
V

204

-

-

0.5
35

60

J,IA
J,IA
V
V
rnA

AC Characteristics
Input Clock Rise Time
Input Clock Fall Time
Output Rise time, O.S to 2.0V
Rise time, 20% to SO% VDD
Output Fall time, 2.0 to O.SV
Fall time, SO% to 20% VDD
Output Duty cycle
Jitter, 1 sigma
Jitter, absolute
Input Frequency (-0 1,-03)
Output Frequency (-01,-03)
FBIN to IN skew

ICLKr
ICLKf
tr
tr
tf
tf
dt
Tis
Tabs
fi
fo
tskewl

FBIN to IN skew

tskewl

Skew between any 2 outputs
at same frequency
Skew between any 2 outputs
at different frequencies

tskew2

15 pfload
15 pfload
15 pfload
15 pfload
15 pfload

-

-

-

-

-300

50
100
500

ns
ns
ns
ns
ns
ns
%
ps
ps
MHz
MHz
ps

1000

-500

1000

ps

-250

±50

250

ps

500

ps

45

Note 1
Note 2, 4. Input rise
time < 3ns
Note 2, 4. Input rise
time < IOns
Note 2,4
Note 2, 4

25
25
-500

0.7
1.2
0.7
1.2
49/51
60
+200

10
10
1
2
1
2
55

NOTES:
1. It may be possible to operate the AV9172 outside of these ranges. Consult ICS for your specific application.
2. All skew specifications are measured with a son transmission line,load terminated with son to lAY.
3. Duty cycle measured at lAY.
4. Skew measured at lAVon rising edges. Loading must be equal on outputs.

D·42

AV9172
Typical Performance Characteristics
120
AV9172 Power Supply Current

100
80

~ 60
40

20

o

20

25

30

35

45

40

50

Input Frequency (MHz)

250
150
50
en
"0 -50

AV9172 Typical channel-to-channel skew

-150
-250
20

30

40

50

Input Frequency (MHz)

Ordering Information
AV9172-01CN16, AV9172-03CN16, AV9172-Q7CN16 or
AV9172-01 CS16, AV9172-03CS16, AV9172-07CS16
Example:

ICS XXXX-PPP M

11

x#w
L

UOOC

'_& _ _

Lead Count=l, 2 or 3 digits
W=.3" SOIC or 6" DIP; None=Standard Width

Package Type
N=DIP~lastic)

M=SOlC

S=SOP

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
Prefix
lCS, AV=Standard Device
ADVANCE INFORMATION documents contain mfonnatlon on new products In the sampling
or preproduction phase of development Charactenstic data and other specifications are
subject to change without notICe

D·43

D-44

II

AV9173

Integrated
Circuit
Systems, Inc.

Video Genlock PLL
General Description

Features

The AV9173 provides the analog circuit blocks required for
implementing a video genlock dot (pixel) clock generator. It
contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). By grouping these critical
analog blocks into one IC and utilizing external digital functions, performance and design flexibility are optimized as are
development time and system cost.

•
•
•
•
•
•
•
•

When used with an external clock divider, the AV9173 forms
a Phase-Locked Loop configured as a frequency synthesizer.
The AV9173 is designed to accept video horizontal synchronization (h-sync) pulses and produce a video dot clock. A separated, negative-going sync input reference pulse is required at
pin2 (IN).

Phase-detectorNCO circuit block
Ideal for genlock system
Reference clock range 25 kHz to 1 MHz
Output clock range 1.25 to 50 MHz
On-chip loop filter
Single 5 volt power supply
Low power CMOS technology
Small 8-pin DIP or SOP package

The AV9173 is also suited for other clock recovery applications
in such areas as data communications.

Block Diagram
FSO

CLK1
FBIN
IN
CLK2

DE

IAV9173RevA01 00194
D·45

II

AV9173
Pin Configuration

FBIN
IN

2

GND

3

FSO

4

~
,..
0)

~

8

CLK2

7

VDD

6

CLK1

5

DE

S-Pin DIP or SOP

K-3, K-6

Pin Descriptions
PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

FBIN

Input

2

IN

Input

3

GND

-

4

FSO

Input

5

OE

Input

Output Enable

6

CLK1

Output

Clock output 1

7

VDD

-

8

CLK2

Output

Feedback Input
Input for reference sync pulse
Ground
Frequency Select 0 input

Power supply (+5V)
Clock output 2 (Divided-by-2 from Clock 1)

D·46

II

AV9173

Using the AV9173
Most video sources, such as video cameras, are asynchronous,
free-running devices. To digitize video or synchronize one
video source to another free-running reference video source, a
video "genlock" (generator lock) circuit is required. The
AV9173 integrates the analog blocks which make the task
much easier.
In the complete video genlock circuit, the primary function of
the AV9173 is to provide the analog circuitry required to
generate the video dot clock within a PLL. This application is
illustrated in Figure I. The input reference signal for this circuit
is the horizontal synchronization (h-sync) signal. If a composite video reference source is being used, the h-sync pulses must
be separated from the composite signal. A video sync separator
circuit, such as the national Semiconductor LM1881, can be
used for this purpose.
The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference frequency. Its divide ratio establishes how many video dot clock
cycles occur per h-sync pulse. For example, if 880 pixel clocks
are desired per h-sync pulse, then the divider ratio is set to 880.
Hence, together the h-sync frequency and external divider ratio
establish the dot clock frequency:
fOUT= fIN. N

where N is external divide ratio

Both AV9173 input pins IN and FBIN respond only to negative-going clock edges of the input signal. The h-sync signal
must be constant frequency in the 25 kHz to 1 MHz range and
stable (low clock jitter) for creation of a stable output clock.

The output hook-up of the AV9173 is dictated by the desired
dot clock frequency. The primary consideration is the internal
VCO which operates over a frequency range of 10 MHz to 50
MHz. Because of the selectable VCO output divider and the
additional divider on output CLK2, four distinct output frequency ranges can be achieved. The following table lists these
ranges and the corresponding device configuration.
FSO State

Output Used

Frequency Range

0
0
1
1

CLKI
CLK2
CLKI
CLK2

10- 50 MHz
5-25MHz
2.5 - 12.5 MHz
1.25 - 6.25 MHz

Note that both outputs, CLKI nd CLK2, are available during
operation even though only one is fed back via the external
clock divider.
Pin 5, OE, tristates both CLKI and CLK2 upon logic low input.
This feature can be used to revert dot clock control to the
system clock when not in genlock mode (hence, when in
genlock mode the system dot clock must be tristated).
When unused, inputs FSO and OE must be tied to either GND
(logic low) or VDD (logic high).
For further discussion of VCOIPLL operation as it applies to
the AV9173, please refer to the AV9170 application note. The
AV9170 is a similar device with fixed feedback dividers for
skew control applications.

CLK1 or 2 ...........- - - - - - . DOT CLOCK

AV9173

tOUT

tiN

H-SYNC SIGNAL

(25 kHz to 1 MHz)

Figure 1: Typical Application of AV9173 in a Video Genlock System

D·47

II

AV9173
Absolute Maximum Ratings
VDD referenced to GND ...................... 7V
Operating temperature under bias ............... O°C to +70°C
Storage temperature .......................... -65°C to + 150°C
Voltage on I/O pins referenced to GND ........... GND -0.5V to VDD +0.5V
Power dissipation ............................ 0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics
Voo =+5V+
to 70°C unless otherwise stated
- 5% , TA-O°C

DC Characteristics
PARAMETER

MIN

TYP

MAX

Input Low Voltage

VIL

Voo=5V

-

-

0.8

V

Input High Voltage

VIH

Voo=5V

2.0

-

-

V

Input Low Current

IIL

VIN=OV

-5

-

-

JlA

IIH

VIN=Voo

-5

-

5

Input High Current

SYMBOL

TEST CONDITIONS

UNITS

Output Low Voltage

VOL

IOL=8mA

-

-

OA

itA
V

Output High Voltage

VOH

IOH=-lmA, Voo=5.0V

Voo-AV

-

-

V

Output High Voltage

VOH

IOH=-4mA, Voo=5.0V

Voo-.8V

-

-

V

Output High Voltage

VOH

IOH=-8mA

2A

-

-

V

Supply Current

100

Unloaded, 50 MHz

-

20

50

rnA
ns

AC Characteristics
Input Clock Rise Time

ICLKr

Note I

-

-

10

Input Clock Fall Time

ICLKf

Note 1

-

-

10

ns

tr

15 pfload

-

1

2

ns

Output Rise Time,
0.8 to 2.0V
Rise time, 20% to 80%Voo

tr

15 pfload

-

2

4

ns

Output Fall time, 2.0 to 0.8V

If

15 pfload

-

1

2

ns

Fall time, 80% to 20% Voo

tf

15 pfload

-

2

4

ns

Output Duty Cycle

dt

15 pfload. Note 1

40

48/52

60

%

Cycle-to-cycle jitter, 1 sigma

Tis

-

120

300

ps

Cycle-to-cycle jitter, absolute

Tabs

-500

±250

500

ps

-±4

-

ns

Line-to-line jitter, absolute
Input Frequency, IN or FBIN
VCO clock speed

TLabs

Note 2

fi

25

-

1000

kHz

fveo

10

-

50

MHz

NOTES:

1.
2.

Duty cycle measured at lAY.
Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz.

D·48

II

AV9173

Ordering Information
AV9173-01 N8 or AV9173-01 S8
Example:

r

xxx XXXX-PPP M X#W
I

C uoo Coom & ~~ Wodili

Lead Count=l, 2 or 3 mgits
W=,3" SOIC or ,6" DIP; None=Standard Width

Package Type
N=DIP (!'lasllc)
S=SOP

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - - Prefix

rcs, AV=Standard Device; GSP=Genlock DeVIce

D-49

D-50

ICS9175

Integrated
Circuit
Systems, Inc.

Low Skew Output Buffer
General Description

Features

The ICS9175 is designed to generate low skew clocks for clock
distribution in high performance PCs and workstations. Using
a 14.318 MHz crystal and phase-locked loop technology, six
output clocks are produced at a master frequency or one half
of the master frequency. The rising edges of the output clocks
are guaranteed to be within 250ps of one another.

•

There are three versions of the ICS9175, each designed to
support a different Pentium CPU frequency.
Part Number

CPU Frequency

ICS9175-04
ICS9175-05
ICS9175-06

66.6
60
52

•
•
•
•
•
•
•
•

Generates low skew clocks for Pentium™ microprocessor
One 14.318 MHz crystal produces six output clocks
52 MHz, 60 MHz, and 66 MHz versions available
±250ps skew (max) between outputs
16-pin SOIC (300 mil) or 16-pin PDIP package
Inputs and outputs are fully TTL-compatible
CMOS process results in low power supply current
High drive, 25mA outputs
Low cost

The ICS9175 is ideal for generating multiple, high-drive CPU
clocks for Pentium applications. It meets the typical system
specification for maximum skew between outputs (250ps) and
clock stability (±250ps).

The ICS9175 is capable of producing half speed CPU clocks.
Up to three of the six outputs can be configured as half speed
CPU clocks. The skew matched circuitry matches rising edges
of all CPU clocks and half speed clocks, guaranteeing low
skew between outputs.

The use of a phase-locked loop allows the output clocks to run
at multiples of the input crystal. The patented VCO design is
capable of achieving internal frequencies of greater than
150 MHz operation. In the design of the ICS9175, the PLL is
programmed to produce internal clocks at twice the desired
frequency. The output is divided in half at the output to produce
symmetric waveforms. Typical duty cycle is 50% ± 1%.

The ICS9175 is fabricated using CMOS technology which
results in much lower power consumption and cost compared
with similar devices based on Gallium arsenide or BiCMOS
technology. The typical operating current for the ICS9175 is
35mA.
The frequencies in the ICS9175 are mask programmable.
Customer specific masks can be made and prototypes delivered within 6-8 weeks from receipt of order. ICS also offers
standard versions such as those offered in this data sheet.

Block Diagram

,-----------------1
1

1
00

•

14318MH Z LX1

crystal

T. .

.;.;;X2'-----II.. 1

•

01

PLL
Frequency
Generator

02

DIVide
LogiC

03

SCLK1---++

1
SCLKO~,--

04

_ _--,

1
05

Pentium IS a trademark of Intel CorporatIon

IICS9175RevA092794

D-51

ICS9175
Configuration Table - ICS917S-04

Pin Configuration

(using 14.318 MHz input)

GND
GND
SCLK1
SCLKO
X1
X2

VDD
VDD

SCLKI SCLKO

VDD
2
3
4
5

I'.,...

6

0)
C/)

7

~

o:t

0

I

II)

15
14
13
12
11
10
9

8

05
04
03
02
01
00

0
0

0

1
1

0

1
1

QO

QI

Q2

Q3

Q4

Q5

66
66
66
66

66
66
66
66

66
66
66
66

66
66
33
33

66
66
33
33

66
33
66
33

GND

16-Pin sOle or PDIP
K-6, K-4

Pin Descriptions
PIN NUMBER

PIN NAME

DESCRIPTION

TYPE

-

-

GROUND
GROUND

1
2
3

GND
GND
SCLKI

Input

SCLKI selects number of '/2 speed clocks

4

SCLKO

Input

5
6

Xl
X2
VDD
VDD
GND
QO
Ql
Q2
Q3
Q4
Q6
VDD

Input
Input

SCLKO selects number of '/2 speed clocks
Xl crystal output
X2 crystal output
Power supply (+5V)
Power supply (+5V)
GROUND
QO is a 66 MHz clock
QI is a 66 MHz clock
Q2 is a 66 MHz clock
Q3 can be 66 MHz or 33 MHz clock
Q4 can be 66 MHz or 33 MHz clock
Q5 can be 66 MHz or 33 MHz clock
Power supply (+5V)

7
8
9
10
11
12
13
14
15
16

Output
Output
Output
Output
Output
Output

-

D-S2

II

ICS9175

Pin Configuration

Configuration Table - ICS917S-0S
(using 14.318 MHz input)

GND
GND
SClK1
SClKO
X1
X2

VDD
VDD

SCLKI SCLKO

VDD

5

....

6

(J)

(7)

g

7

8

11

10
9

16-Pin

0
0
I
I

05
04
03
02
01
00

0
I
0
I

QO

QI

Q2

Q3

Q4

Q5

60
60
60
60

60
60
60
60

60
60
60
60

60
60
30
30

60
60
30
30

60
30
60
30

GND

sOle or PDIP
K-6, K-4

Pin Descriptions
PIN NUMBER

PIN NAME

TYPE

-

DESCRIPTION
GROUND
GROUND

I
2
3

GND
GND
SCLKI

Input

SCLKI selects number of 1/2 speed clocks

4

SCLKO

Input

5
6
7
8

XI
X2
VDD
VDD
GND
QO
QI
Q2
Q3
Q4
Q6
VDD

Input
Input

SCLKO selects number of iJ2 speed clocks
XI crystal output
X2 crystal output
Power supply (+5V)
Power supply (+5V)
GROUND
QO is a 60 MHz clock
QI is a 60 MHz clock
Q2 is a 60 MHz clock
Q3 can be 60 MHz or 30 MHz clock
Q4 can be 60 MHz or 30 MHz clock
Q5 can be 60 MHz or 30 MHz clock
Power supply (+5V)

9
10
11
12
13
14
IS
16

Output
Output
Output
Output
Output
Output

-

D·53

II

ICS9175

Configuration Table - ICS917S-06

Pin Configuration

(using 14.318 MHz input)

GND
GND
SCLK1
SCLKO
X1
X2
VDD
VDD

4
5
6
7
8

16-Pin

co
0I

It)

,..
"'"

0)

CJ)

~

13
12
11
10
9

SCLKI SCLKO

VDD
05
04
03
02
01
00
GND

0
0
I
I

0
I
0
I

QO

QI

Q2

Q3

Q4

Q5

52
52
52
52

52
52
52
52

52
52
52
52

52
52
26
26

52
52
26
26

52
26
52
26

sOle or PDIP
K-6, K-4

Pin Descriptions
PIN NUMBER

PIN NAME

TYPE

-

DESCRIPTION
GROUND
GROUND

I
2
3

GND
GND
SCLKI

Input

4

SCLKO

Input

SCLKO selects number of 1/2 speed clocks

5
6
7
8

Xl
X2
VDD
VDD
GND
QO
Ql
Q2
Q3
Q4
Q5
VDD

Input
Input

XI crystal output
X2 crystal output
Power supply (+5V)
Power supply (+5V)
GROUND
QO is a 52 MHz clock
Q I is a 52 MHz clock
Q2 is a 52 MHz clock
Q3 can be 52 MHz or 26 MHz clock
Q4 can be 52 MHz or 26 MHz clock
Q5 can be 52 MHz or 26 MHz clock
Power supply (+5V)

9
10

11
12
13
14
15
16

-

Output
Output
Output
Output
Output
Output

-

SCLKI selects number of 1/2 speed clocks

D·54

II

ICS9175

Absolute Maximum Ratings
VDD referenced to GND ......................
Operating temperature under bias ...............
Storage temperature ..........................
Voltage on I/O pins referenced to GND ...........
Power dissipation ............................

7V
O°C to 70°C
-6SoC to IS0°C
GND -O.SV to VDD +O.SV
O.S Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics
VDD = +SV+S%
TA=O°C to 70°C unless otherwise stated
-

DC Characteristics
~.

PARAMETER

Input Low Voltage
Input High Voltage
Input Low Current

SYMBOL
VIL
Vm

TEST CONDITIONS

MIN

TYP

MAX

UNITS

-

0.8

V
V

-S
-S

-

-

O.S-

2.4

-

-

-

3S

60

-

0.7
1.2
0.7
1.2

1
2
1
2

4S

SS

-

491S1
60
±200
14.318

-

-

100

Note 2, 4

-2S0

±SO

2S0

MHz
MHz
ps

Note 2, 4

-

-

SOO

ps

VDD=SV
VDD=SV
VIN=OV

2.0

Input High Current

hL
1m

Output Low Voltage
Output High Voltage
Supply Current

VOL
VOH
IDD

IOL=2SmA
IOH=-2SmA
Unloaded, SCLK=OO

tr
tr
tf
If
dt
TIs
Tabs
f,

IS
IS
IS
IS
IS

VIN=VDD

--

S
S
0.8

I1A
I1A
V
V
rnA

AC Characteristics
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% V
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Output Duty cycle
Jitter, 1 sigma
Jitter, absolute
Input Frequency
Output Frequency
Skew between any 2 outputs
at same frequency
Skew between any 2 outputs
at different frequencies

pfload
pfload
pfload
pfload
pfload

-

Note 1

fo
tskew2

-

NOTES:
1. It may be possible to operate the ICS9175 outside of these ranges. Consult rcs for your specific application.
2. All skew specifications are measured with a SO£1 transmission line, load terminated with SO£1 to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at I.4V on rising edges. Loading must be equal on outputs.

D-55

ns
ns
ns
ns
%
ps
ps

II

ICS9175
Ordering Information
ICS9175-04CS16 or ICS9175-05CS16 or ICS9175-06CS16 (SOIC)
ICS9175-04CN16 or ICS9175-05CN16 or ICS9175-06CN16 (DIP)
Example:

r

ICS XXXX-PPP M X#W

I

C ~ Coo.' & ~ W.d~

Lead Count=!, 2 or 3 digits
W=.3" SOIC or .6" DIP; None=Standard Width

Package Type
S=SOIC
N=DIP (flastic)

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - D e v i c e Type (consists of 3 or 4 digit numbers)
'----------Prefix
ICS, AV=Standard Device; GSP=Genlock Device

D-56

•

ICS9176

Integrated
Circuit
Systems, Inc.

Low Skew Output Buffer
General Description

Features

The ICS9176 is designed specifically to support the tight
timing requirements of high-performance microprocessors and
chip sets. Because the jitter of the device is limited to ±250ps,
the ICS9176 is ideal for clocking Pentium™ systems. The 10
high drive (40mA), low-skew (±250ps) outputs make the
ICS9176 a perfect fit for PCI clocking requirements.
The ICS9176 has 10 outputs synchronized in phase and frequency to an input clock. The internal phase locked loop (PLL)
acts either as a IX clock multiplier or a 1I2X clock multiplier
depending on the state of the input control pins TO and Tl. With
metal mask options, any type of ratio between the input clock
and output clock can be achieved, including 2X.
The PLL maintains the phase and frequency relationship between the input clock and the outputs by externally feeding
back FBOUT to FBIN. Any change in the input will be tracked
by all 10 outputs. However, the change at the outputs will
happen smoothly so no glitches will be present on any driven
input. The PLL circuitry matches rising edges of the input clock
and the output clock. Since the input to FBIN skew is guaranteed to ±50Ops, the part acts as a "zero delay" buffer.
The ICS9176 has a total of eleven outputs. Of these, FBOUT
is dedicated as the feedback into the PLL and another, Q/2, has
an output frequency half that of the remaining nine. These nine
outputs can either be running at the same speed as the input, or
at half the frequency of the input. With Q/2 as the feedback to
FBIN, the nine 'Q' outputs will be running at twice the input
frequency in the normal divide-by-I mode. In this case, the
output can go to 120 MHz with a 60 MHz input clock. The
maximum rise and fall time of an output is 14ns and each is
TTL-compatible with a 40mA symmetric drive.
The ICS9176 is fabricated using CMOS technology which
results in much lower power consumption and cost compared
with the gallium arsenide based 1086E. The typical operating
current for the ICS9176 is 60mA versus 115mA for the
GAI086E.

•

ICS9176-01 is pin compatible with Triquint GAI086

•
•
•
•
•
•
•
•
•

±500ps skew (max) between input and outputs
±250ps skew (max) between outputs
10 symmetric, TLL-compatible outputs
28-pin PLCC surface mount package
High drive, 40mA outputs
Power-down option
Output frequency range 20 MHz to 120 MHz
Input frequency range 20 MHz to 100 MHz
Ideal for PCI bus applications

Selection Table
DESCRIPTION

TJ

To

0

0

Power-down

0

1

Test Mode (PLL Off CLK=outputs)

1

0

Normal (PLL On)

1

1

Divide by 2 Mode

Block Diagram

FBOUT

FBOUT
01

FBIN

02

ClK

03
DIVIDE
lOGIC

TO
T1

04
05
06
07
08
09
Q/2

Penbum IS a trademark of Intel Corporation
IICS9176RevB092794

D-S7

II

ICS9176
Pin Configuration

VDD

TO
VDD

09
08

0/2

ICS9176

GND

GND (Pin 1)

01

07
06

VDD

VDD

FBOUT

28-Pin PLCC
K-10

Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

PIN NAME
GND
Q8
Q9
VDD
GND
NC
NC
VDD
CLK
T1
FBIN
TO
VDD
Q/2
GND
FBOUT
Q1
VDD
GND
Q2
Q3
VDD
Q4
QS
GND
VDD
Q6
Q7

TYPE
Output
Output
-

Input
Input
Input
Input

Output
Output
Output
Output
Output

Output
Output

Output
Output

DESCRIPTION
GROUND.
Output clock 8.
Output clock 9.
Power supply (+ 5V).
GROUND.
No Connect.
No Connect.
Power supply (+5V).
Input for reference clock.
T1 selects normal operation, power-down, or test mode.
FEEDBACK INPUT from output FBOUT.
TO selects normal operation, power-down, or test mode.
Power Supply (+SV).
Half-clock output.
GROUND.
FEEDBACK OUTPUT to Input FBIN.
Output clock 1.
Power Supply (+5V).
GROUND.
Output clock 2.
Output clock 3.
Power supply (+5V).
Output clock 4.
Output clock 5.
GROUND.
Power Supply (+5V).
Output clock 6.
Output clock 7.

D·SS

ICS9176
Timing Diagrams

INPUT CLOCK - -...

01-09--'"

QJ2--"

Timing in Divide by 1 Mode

____. . .1
""'--_. . . 1
.
1

INPUT CLOCK - - - '

01-09 - - - '

1....-_ _ _ _......

0/2 - - - '

Timing in Divide by 2 Mode

INPUT CLOCK

01 -09

0/2

Timing in Eliminate by Test Mode
Note:

In test mode, the veos are bypassed. The test clock input is simply buffered, then output. The part is transparent.
Damage to the device may occur if an output is shorted or forced to ground or VDD.

INPUT CLOCK - _...

01-09 - - - - - - - - - - - - - - - - - - - - - - - -

QJ2 - - - - - - - - - - - - - - - - - - - - - - - Timing in Power-down Mode

D-59

II

ICS9176
Absolute Maximum Ratings
VDD referenced to GND ......................
Operating Temperature under bias ...............
Storage Temperature ..........................
Voltage on I/O pins referenced to GND ...........
Power Dissipation ............................

7V
O°C to +70°C
-65°C to + 150°C
GND -0.5V to VDD +0.5V
0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics
DC Characteristics
VDD - +5V+5%
TA-O°C
to 70°C unless otherwise stated)
TEST CONDITIONS
PARAMETER
SYMBOL

MIN

TYP

MAX

UNITS

Input Low Voltage

VIL

VDD=5V

-

0.8

V

Input High Voltage

VIH

VDD=5V

2.0

-

-

V

VIN=OV,5V

-5

-

5

[.LA

0.4

Input Current

I,

V

Output Low Voltage

VOL

@IOL=14mA

-

0.25

Output Low Current

IOL

@VoL=0.8V

33

42

Output High Voltage

VOH

@IOH=-38mA

2.4

-

-

V

Output High Current

IOH

@VoH=2.0V

-

-59

-41

rnA

D-60

rnA

II

ICS9176

AC Characteristics
PARAMETER

SYMBOL

Input Clock Pulse Width*

CLKw

TEST CONDITIONS
Vdd=4.5Y, fCLK=I00 MHz

MIN

TYP

MAX

2.5

-

UNITS

7.5

ns

0.7

I

ns

1.5

2

ns

Output Rise time, O.S to
2.0V*

If

15 pf load

Rise lime, 20% to SO%
VDD*

If

15 pf load

Output Fall time, 2.0V to
O.SV*

If

15 pfload

-

0.7

I

ns

Fall time, SO% to 20%
VDD*
Output Duty cycle*

If

15 pfload

-

1.2

2

ns

d,

15 pfload

45

49/51

Jitter, 1 sigma*

Tis

60

55
I

%

ps

Jitter, absolute*

Tabs

-250

250

ps

Input Frequency

f1

20

100

MHz

Output Frequency
(Q outputs)

fo

20

120

MHz

FEIN to IN skew

tskewl

Skew between any 2
outputs at same
frequency

tskew2

Note 1, 3. Input rise time
<3ns
Note 1,3.

Skew between any 1
output and Q/2

±IOO

-500

250

0

ps

-250

50

250

ps

3

ns

NOTES:
1. All skew specifications are measured with a 50n transmission line, load terminated with 50n to 1.4Y.
2. Duty cycle measured at 1.4Y.
3. Skew measured at I.4V on rising edges. Loading must be equal on outputs.

* Guaranteed by design and characterization. Not subject to 100% test.

D·61

II

ICS9176
Applications
FBOUT is normally connected to FEIN to facilitate input to
output skew control. However, there is no requirement that the
external feedback connection be a direct hardwire from an
output pin to the FBIN pin. As long as the signal at FBIN is
derived directly from the FBOUT pin and maintains its frequency, additional delays can be accommodated. The clock
phase of the outputs (rising edge) will be adjusted so that the
phase of FBIN and the input clock will be the same. See Figure
I for an example.

The ICS9176 is also ideal for clocking multi-processor systems. The 10 outputs can be used to synchronize the operation
of CPU cache and memory banks operating at different speeds.
Figure 2 depicts a 2-CPU system in which processors and
associated peripherals are operating at 66 MHz. Each of the
nine outputs operating at 66 MHz are fully utilized to drive the
appropriate CPU, cache and memory control logic. The
33 MHz output is used to synchronize the operation of the
slower memory bank to the restart of the system.

FBIN

FBIN
ICS9176

66 MHz

GND~
VDD~

Figure 1
In Figure I, the propagation delay through the divide by 2
circuit is eliminated. The internal phase-locked loop will adjust
the output clock on the ICS9176 to ensure zero phase delay
between the FBIN and CLK signals, as a result, the rising edge
at the output of the divide by two circuit will be aligned with
the rising edge of the 66 MHz input clock. This type of
configuration can be used to eliminate propagation delay as
long as the signal at FBIN is continuous and is not gated or
conditional.

Ordering Information
ICS9176-01 CQ28
Example:

r

ICS XXXX-PPP M X#W

I

L ~ Cooo' ~
&

mdili

Lead Count=l. 2 or 3 digIts
W=.3" SOIC or 06" DIP; None=Standard Width

Package Type
Q=PLCC

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - - Prefix
ICS, AV=Standard DeVIce; GSP=Genlock DeVIce

D-62

II

ICS9177

Integrated
Circuit
Systems, Inc.

Advance Information

High Frequency System Clock Generator
General Description

Features

The ICS9177 is a multiple output clock generator ideal for high
speed processor system applications. A single high-speed internal VCO is utilized to derive up to four simultaneous clock
output frequencies. This enables output clock skew matching
and the minimization of clock jitter. The internal VCO operates
up to 350 MHz providing edge skew matched output clocks.
One differential PECL (Positive ECL) output pair provides a
high speed processor clock. 12 TTL clock outputs are also
provided for other system functions, such as bus clocks. Input
selection pins are used to select the TTL output clock frequencies.

•
•
•
•
•
•
•

Provides output frequencies up to 175 MHz
Internal VCO is divided into four skew-matched output
frequencies (Out A, B, c, D)
External clock feedback provides input to output skew
matching
Differential PECL clock output pair provided for high
speed output (Out A)
12 TTL clock outputs (for Out B, C, D)
Single 5 volt power supply voltage
Internal loop filters
52-pin QFP package

For information about ICS9177 customization optics, please
contact ICS.

Block Diagram

J

Pha~~-/--~

REFCLK--- , Detector/Charge
1 Pump
FBCLK -------I

!---l
;

,------ AOUTO

1---------' AOUTl

TCLK
TESTEN

I

-

BOUTO

~--BOUTl

DSELO
DSELl
TRSTL
PASELO
PASELl
PBSELO
PBSELl
PCSELO
PCSELl

-I

. -----------:I[

DIVIDE
and
MUX

LOGIC

COUTO
~
---COUTl
--+COUT2
1---_______ DOUTO

L-: ~~gm:1
"PBOUTO
PBOUTl

----__

L________

-I'

1--·

'---------'

IICS91 nRevA092794

D·63

PCOUTO
-----. PCOUTl

E

II

ICS9177
Pin Configuration
52-Pin QFP
K-11

13

SQUARE

14

62

26

40

Pin Descriptions
PINNUMBER

PIN
NAME

TYPE

DESCRIPTION

PINNUMBER

PIN
NAME

I

GND

2

REFCLK

INPUT

3

FBCLK

INPUT

4

DSELI

INPUT

PLL divider mode control

33
34

GND

OUTPUT

from external oscIllator

29

COUTI

OUTPUT

external PLL Feedback path from
one of the OutC outputs

30

VCC

31

GND

32

COUTO

TTL - 25 MHz output clock

DOUTO

TTL - 12.5 MHz output clock

5

DSELO

INPUT

6

TESTEN

INPUT

Test mode ENABLE pm

7

TSTCLK

INPUT

External Test Clk

8

NC

9

VCC

10

GND

11
12
13
14
15
16

PCOUTI

OUTPUT

PCOUTO

OUTPUT

TTL - Group 2 Programmable
clock outputs

35

NC

36

AOUTI

OUTPUT

37

AOUTO

OUTPUT

38

NC

39

GND

40

ECL+5V
(same as
VCC)

41

NC

GND
VCC
OUTPUT

PBOUTO

OUTPUT

17

VCC

DESCRIPTION

COUT2

(ContaIns .ntemal pull-up res.stors)

PBOUTI

TYPE

28

TTL - Group I Programmable
clock outputs

42

NC

43

ANALOG
+5V

44

ANALOG
+5V

TTL - 25 MHz output clock

ECL-lOOMHz,75MHzor50
MHz based on DSEL(I :0) pm.

18

GND

19

PAOUTI

OUTPUT

20

PAOUTO

OUTPUT

45

AGND

21

VCC

46

PCSELI

INPUT

Programmable clock Group C

22

GND

47

PCSELO

INPUT

select

23

RESETL

INPUT

48

PBSELI

INPUT

24

BOUTI

OUTPUT

49

PBSELO

INPUT

Programmable clock Group B
select

25

BOUTO

OUTPUT

50

PASELI

INPUT

26

VCC

51

PASELO

INPUT

27

GND

52

VC

TTL - Group 0 Programmable
clock outputs

Low true divider reset pin
TTL - 50 MHz output clock

• Internal pull-up resistor

D-64

Programmable clock Group A
select

ICS9177
Typical System Usage

Example of System Block Diagram - Clocking
Function Tables
Table 1: Primary Function Table
REF IN
(MHx)

DSEL
1

DSEL
0

RSTL

TEST

25

0

0

1

25

0

1

1

33

1

1

I

I

0

I

OUT
B

OUT
C

OUT
D

fl

OUT
A

0

200 MHz

f/4

f/4

f/8

f/16

Mode 0 - 111

0

300 MHz

f/4

f/6

fl12

f/24

Mode 1 - 3/2

0

2001264

f12

f/4

f/8

f/16

Mode 2 - 211
Mode 3 - All 1

DESCD

MHz
25

1

1

1

0

X

1

1

1

1

-

X

X

0

X

X

0

0

0

0

Reset Mode

0

0

1

1

TCLK

f12

f12

f/4

f/8

Test Mode 0

-

0

1

1

1

TCLK

f12

f/3

f/6

f/12

Test Mode 1

-

1

0

1

1

TCLK

f/l

f12

f/4

f/8

TcstModc 2

1

1

1

1

TCLK

f/2

f12

f/2

f/2

Test Mode 3

Table 2: CLOCK SELECT Blocks Function Table

I

PxSEL
1

PxSEL
0

0

0

Both outputs at the same frequency as Out B.

0

1

Both outputs at the same frequency as Out C.

1

0

Both outputs at the same frequency as Out D.

1

1

Both outputs disabled in the high state.

Function of CLOCK SELECT Blocks

Note: x=A, B, or C. (See Figure 1.)

D-65

I

II

ICS9177
Clock Output Timing Diagrams

1: 1 frequency .ratio - Mode 0
y

f

ilIlnrulJUUUUUlflJlJ1JUlJ1J1IU1JlJ1JU1JL

OutAIL~~~~
OutB~·

Oute I
OutD

I,--~-----"

1

3:2 frequency ratio - Mode 1
f

OutA
OutBI,.--~.-------J
Oute
OutD
1

~--------;

1

2: 1 frequency ratio - Mode 2
f

OutA
OutB I L 5 I
Oute
~-----"
OutD
L---I

1

Note: The arrow indicates the point where the clock sequence starts to repeat.

D-66

II

ICS9177

Absolute Maximum Ratings
Supply voltage .............................. 7.0 V
Logic inputs ................................ GND -.05V to VDD +.05V
Ambient operating temp ....................... 0 to 70°C
Storage temperature .......................... -65°C to l50°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Power Supply Specifications (Total Power consumption: approximately 750 mw)
Table 3: DC Specifications

AC/DC Input Specification

Table 4: AC Specification of Inputs
Pin Type

Vil(max)

tr

tf

All

0.8V

3

3

Note: tr and tf are typical values for input

ACIDC Characteristics
Table 5: AC Specification type Out A.peel Pins (CPUCLK)
MAX

UNITS

Output High Voltage J

Voh

3.87

4.67

volts

Output Low Voltage I

Vol

2.63

3.19

volts

Output High Current

Ioh

38.7

46.7

rna

Output Low Current

101

26.3

31.9

rna

Rise Time 10-90%

tr

1

ns

Fall Time 10-90%
Duty cycle at 100 MHz2• 3

tf

1

ns

55

%

PARAMETER

SYMBOL

TEST CONDITIONS

dcyc

MIN

45

TYP

Test Load Conditions: lOOQ, 15 pf.
Note 1: The pecllevels are standard 10 kH positive ECL values as shown in the table above.
Note 2: Pin skew and Duty cycle are measured at the signal swing mid-point.
Note 3: The skew and duty cycle numbers reflect the recommended clock distribution method shown in Figure 2.

D·67

[I

ICS9177
Table 6: AC Specification type Out B.ttl Pins (50 Mhz)
MIN

TYP

MAX

Output High Voltage

Voh

2.4

3.2

5

volts

Output Low Voltage

Vol

0

0.3

0.8

volts

Output High Current

loh

16

Output Low Current

101

24

rna

PARAMETER

SYMBOL

TEST CONDITIONS

UNITS

rna

Rise Time 10-90%

tr

I

2

3

ns

Fall Time 10-90%

tf

I

2

3

ns

Pin skew to other OutB.ttl signals l

tsk

250

500

ps

Duty cycle at 1.5V

dcyc

Delay from OutA.pecl
signals 2

tdly

Skew associated with above
delal

45

55

%

.5

ns

±0.5

ns

.2

tdlyskw

Test Load Conditions: 500n, 15 pf.
Note I: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured
from the OutA.pecl signal at the signal swing mid-point to max output of the OutB.ttl signal's rising edge.

Table 7: AC Specification type Out C.ttl Pins (25 Mhz)
MIN

TYP

MAX

UNITS

Output High Voltage

Voh

2.4

3.2

5

volts

Output Low Voltage

Vol

0

0.3

0.8

volts

Output High Current

Ioh

16

Output Low Current

101

Rise Time 10-90%

tr

1

Fall Time 10-90%

tf

1

Pin skew to other OutC.ttl signals!

tsk

PARAMETER

SYMBOL

Duty cycle at 1.5V

dcyc

Spread to OutB.ttl signals2

tspb

TEST CONDITIONS

45

rna
24

rna

2

3

ns

2

3

ns

250

500

ps

55

%

500

ps

Test Load Conditions: 500n, 15 pf.
Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Spread is the absolute difference between the rising edge of any OutC.ttl signal and the rising edge of any
OutB.ttl signal.

D·68

ICS9177
Table 8: AC Specification type Out D.ttl Pins (12.5 Mhz)
I SYMBOL

MIN

TYP

MAX

UNITS

Output High Voltage

Voh

2.4

5

3.2

volts

Output Low Voltage

Vol

0

0.8

0.3

volts

Output High Current

loh

16

Output Low Current

101

PARAMETER

TEST CONDITIONS

rna
24

!

rna

Rise Time 10-90%

tr

I

3

2

ns

Fall Time 10-90%

tf

I

3

2

ns

Pin skew to other OutD.ttl signals

tsk

500

250

ps

Duty cyele at 1.5V

dcyc

Delay from OutA.peei
signals!

tdly

Skew associated with above
delal

I
45

tdlyskw

55

%

.5

ns

±1.3

ns

i

Test Load Conditions: 500Q, 15 pf.
Note 1: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured
from the OutA.peei signal at the signal swing mid-point to max output of the OutD.ttl signal's rising edge.

Ordering Information
ICS9177-01 CF52
Example:

ICS XXXX-PPP M X#W

- 11

L

'_d C","" & P""g, mdfu

Lead Count=I. 2 or 3 dIgIts
W=.3" SOIC or .6" DIP; None=Standard WIdth

Package Type
F=QFP

Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable)
' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - Prefix
ICS. AV=Standard DeVIce; GSP=Gen!ock Device

ADVANCE INFORMATION documents contain Information on new products In the sampling
or preproduction phase of development CharactenstlC data and other speCifications are
sub ect to chan e without notice

D-69

D·70

les
High-Performance
Products

ICS continues to lead the marketplace in advanced high speed frequency synthesis
technology. This issue of the ICS databook includes the addition of high speed PLL
clock products for laser engine (ICSI574), and high speed CPU applications
(ICSI577), offering system performance to 466 MHz. These products allow the
system designer to achieve new levels of pixel resolution with the lowest jitter
performance available. Other ICS products address advanced video, multimedia,
imaging, and workstation graphics.
As always, ICS High Performance Products offer the designer:
• User Programmable, designer friendly interface feature set.
• Extremely low jitter performance with full device integration.
• Advanced CMOS technology offering the highest speed VCO/PLL performance in the industry.
• Full applications evaluation kits and technical support.
ICS High Performance Products are designed with and for you, the customer, in
mind. Our customer dialog is continuous, and we welcome the opportunity to
discuss how ICS advanced frequency synthesis capability can solve your high speed
system requirements.

E·!

les High-Performance Product Selection Guide
Product
Applications

ICS
Device Type

Description

Package Types

Page

Projection LCD
Large-Panel LCD
Medial Imaging Systans
Virtual Reality Systems

ICS1522

User-Programmable Frequencies,
'Line Lock' Capability.
15 kHz to 1 MHz reference to
230 MHz output.

24-Pin
SOIC

E-3

Mask Programmed
Workstation

ICS1561A

+2, 4, 8 TTL Out. Integral Loop Filter.
Replaces ICS1561 to 230 MHz,
ROM-based.

20-Pin
DIP, SOIC

E-23

High-Performance
Workstation

ICS1562A

User-Programmable Frequencies.
RAMDAC Reset Logic
(Brooktree compatible) to 400 MHz.

16-Pin
Narrow
SOIC

E-31

Workstation Clock
Generators

ICS1567

32 Frequency ROM-based RAMDAC
Reset Logic (Brooktree compatible)
to 180 MHz.

20-Pin
DIP, SOIC

E-51

Mid-Range
Workstation

ICSI572

User-Programmable Frequencies.
RAMDAC Reset Logic
(Brooktree compatible) to 180 MHz

20-Pin
SOIC

E-61

Laser Printers

ICS1574

Laser Engine Pixel Clock
to 400 MHz.

16-Pin
Narrow SOIC

E-79

Motherboard

ICS1577

DEC AlphaTil CPU Clock
to 466 MHz.

14-Pin
DIP

E-91

Mid-Range
Workstation

ICS2572

User-Programmable Dual PLL.
16V +4M Locations.

20-Pin
DIP, SOIC

E-99

Notes:
1. All products have internal loop filters except as noted.
2. All products operate at 5V typo except as noted.
Alpha is a trademark of Digital Equipment Corporation.

ADVANCE INFORMATION documents contsin infonnation on new products in the sampling or preproduction phase of development. Characteristic data
and other specifications are subject to change without notice.
PRODUCT PREVIEW documents contain infonnation on products in the formative or design phase of development. Characteristic data and other specifications
are design goals. ICS reserves the right to change or discontinue these products without notice.

E-2

•

~

ICS1522

Integrated
Circuit
Systems, Inc.

User-Programmable Video Clock Generator/
Line-Locked Clock Regenerator
Description

Features

The ICSlS22 is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer. Utilizing ICS's
advanced CMOS mixed-mode technology, the ICSlS22 provides a low-cost solution for high-end video clock generation
where synchronization to an external video source is required.

•

The ICSl522 has differential video clock outputs (CLK+ and
CLK-) that are compatible with industry standard video DAC.
Operating frequencies are fully programmable with direct
control provided for reference divider, feedback divider and
post-scaler.

•
•
•
•
•

•
•

Serial programming: Feedback and reference divisors,
VCO gain, phase comparator gain, relative phase and test
modes
Supports high-resolution graphics - Differential CLK
outputs to 230 MHz
Eliminates need for multiple ECL output voltage controlled crystal oscillators and external components
Fully-programmable synthesizer capability - not just a
clock multiplier
Line-locked clock generation capability; 15 - 100 kHz
External feedback loop capability allows graphics system
to be used as the feedback divisor with synchronous
switchover to internal feedback
Small footprint 24-pin SOP
Coarse and fine phase adjustment permits precise clocking in video recovery application

Applications
•
•
•

Block Diagram
POEN

FINE

LCD Projector Systems
Multimedia video line locking
Genlock applications

I-fUAP

V-VCO

EXT\CO

xrAll/EXTREf
XfAl2

aK+
aK-

SDATA

saK
OJn
SEln

OJT2

0WX2
OJT3

OJT4

IICS1622RevFl00B94

E-3

II

ICS1522
Overview

Output Post-scaler

The ICS1522 is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully programmable feedback and reference divider capability
allow virtually any frequency to be generated, not just simple
multiples of the reference frequency. The ICS1522 uses the
latest generation of frequency synthesis techniques developed
by ICS and is completely suitable for the most demanding
video applications.

A programmable post-scaler may be inserted between the VCO
and the CLK+ and CLK- outputs of the ICS1522. This is useful
in generating of lower frequencies, as the VCO has been
optimized for high-frequency operation.

PLL Synthesizer Description Ratiometric Mode
The ICS1522 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL (see Block Diagram). The reference frequency is generated by an on-chip crystal oscillator or the
reference frequency may be applied to the ICS1522 from an
external frequency source, typically horizontal sync from another display system.
The phase-frequency detector shown in the Block Diagram
drives the voltage-controlled oscillator, or VCO, to a frequency
that will cause the two inputs to the phase-frequency detector
to be matched in frequency and phase. This occurs when:
F(vco : = F(XTALl)' Feedb~c~ Divider
)
Reference DIvIder
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided
to the part (assuming correctly programmed dividers).
The VCO gain is programmable, which permits the ICS1522
to be optimized for best performance at all operating frequencies.
The feedback divider may be programmed for any modulus
from 64 to 2048 in steps of one followed by a divide by I, 2,
4 or 8 feedback post -scaler.
The reference divider may be programmed for any modulus
from 1 to 1024 in steps of one.

The post-scaler allows the selection of dividing the VCO
frequency by either 1, 2, 4 or 8.

Load Clock Divider
The ICS1522 has an additional programmable divider (referred to in the Block Diagram as the load counter) that is used
to generate the LOAD clock frequency for the video DAC. The
modulus of this divider may be set to 3, 4, 5, 6, 8, or 10 under
register control. The design of this divider permits the output
duty factor to be 50/50, even when odd modulus is selected.
The input frequency to this divider is the output of the output
post -scaler described above.

Digital Inputs - ICS1522
The programming of the ICS1522 is performed serially by
using the SDATA, SCLK, and SELn pins to load the 7, 11 bit
internal memory locations.
Single bit changes are accomplished by addressing the appropriate memory location and writing only 11 bits of data, not by
writing all 77 data bits.
For proper programming of the ICS1522, it is important that
all transitions of the SELn input occur during the same state
of the SCLK input.
SDATA is shifted into a 15 bit serial register on the rising edge
of SCLK while SELn is low. The first bit loaded is RlWn
followed by a 3 bit address and 11 bit data (both address & data
are LSB first). When a rising edge of SCLK occurs while
SELn is high (SDATA ignored), the contents of the serial
register are loaded into the addressed 11 bit memory location
ifRlWn is low. IfRlWn is high upon the above condition, the
data from the addressed memory location is loaded into the
serial shift register and SDATA is set as an output. The 3 bit
address and 11 bit data will be serially shifted out of the
ICS1522 on the SDATA pin on the rising edge ofSCLK while
SELn is low (see Timing Diagram).
An additional control pin on the ICS1522, PDEN can be used
to disable the phase-frequency detector in line-locked applications. When disabled, the phase detector will ignore any inputs
and allow the VCO to coast. This feature is useful in systems
using composite sync.

E-4

ICS1522
Output Description
The differential output drivers, CLK+ and CLK-, are currentmode and are designed to drive resistive terminations in a
complementary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRG
pin. The sink current, which is steered to either CLK+ or
CLK-, is four times the current supplied to the IPRG pin. For
most applications, a resistor from VDDO to IPRG will set the
current to the necessary precision.

Series-resonant crystals may also be used with the ICS1522.
Be aware that the oscillation frequency will be slightly higher
than the frequency that is stamped on the can (typically 0.0250.05%).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1522 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
If an external reference frequency source is to be used with the
ICS1522, it is important that it be jitter-free. The rising and
falling edges of that signal should be fast and free of noise for
best results. The loop phase is locked to the rising edge of the
XTALlfEXTREF input signal, if REF_POL is set to logic O.
Additionally, the EXTREF bit should be set to logic I to switch
in a TTL-compatible buffer at this input.

24-Pin SOP
K-7
24
23
22
21
20
19
18
17
16
15
14
13

II

Rl

V AA

RI'

,------;;0J(;;;:.:ra--"'---t---t---l

,---=:'-""""",----+-+--1

.,

ClockClock

R2'

RAMDAC

Typical Output Circuitry Configuration

The ICS1522 has circuitry on-board to implement a Pierce
oscillator with the addition of a quartz crystal and two external
loading capacitors (EXTREF bit must be set to logic 0). Pierce
oscillators operate the crystal in anti- (also called parallel-)
resonant mode.

2
3
4
5
6
7
8
9
10
11
12

!pig

- - - - - - - - - - - - - " , Rt

GND

Reference Oscillator and
Crystal Selection

IPUMP
SDATA
SCLK
SELn
AVDD
XTAL 1/EXTREF
XTAL2
FINE
VSS
VSS
OUT4
OUT3

"d

VVCO
EXTVCO
EXTFBK
PDEN
VDD
CLK+
CLKIPRG
VSS
OUT1
OUT2
VDDO

Line-Locked Operation
Some video applications require a clock to be generated that is
a multiple of horizontal sync. The ICS1522 supports this mode
of operation. The reference divider should he scI to di vide hy
one and the desired polarity (rising or falllllg) of lock cdgl'
should be selected. By using the phase dctcctol halliw;uc
disable mode (PDEN), the PLL can he made to rfel:'fUIl at the
beginning of the vertical interval of the external video, and can
be reactivated at its completion.

External Feedback Operation
The ICS1522 option also supports the inclusion of an external
counter as the feedback divider of the PLL. This mode is useful
in graphic systems that must be "genlocked" to external video
sources.
When the FBK_SEL bit is set to logic 0, the phase-frequency
detector will use the EXTFBK pin as its feedback input. The
loop phase will be locked to the rising edges of the signal
applied to the EXTFBK input if FBK_POL is set to logic 0
Synchronous switchover to the internal feedback can be accomplished by setting the FBK-SEL bit to logic 1 while an
active feedback source exists on the EXTFBK pin.

Fine Phase Adjustment
The ICS1522 has the capability of adjusting the pixel clock
phase relative to the input reference phase. Entire pixels can
be added or removed under register control with sub-pixel
adjustment accomplished by a control voltage on the FINE
input pin. By utilizing the fine phase adjust, after first synchronously switching from external feedback to internal feedback,
the graphics system phase can be precisely controlled relative
to the input horizontal sync.

E-5

ICS1522
Power-On Initialization

Power Supplies and Decoupling

The ICS1522 has an internal power-on reset circuit that sets
the frequency of the CLK+and CLK- outputs to be half the
crystal or reference frequency assuming that they are between
10 MHz and 25 MHz (refer to default settings in Register
Definition). Because the power-on reset circuit is on the VDD
supply, and because that supply is filtered, care must be taken
to allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD supply
reaches four volts.

The ICS1522 has three VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). These pins should connect to the ground plane of the video board as close to the
package as is possible.

Board Test Support
It is often desirable to statically control the levels of the output
pins for circuit board test. The ICS1522 supports this through
a register programmable mode, AUXEN. When this mode is
set, AUXCLK will directly control the logic levels of the
CLK+ and CLK- pins while OMUXI, OMUX2, OMUX3, and
OMUX4 will control OUT!, OUT2, OUT3 and OUT4, respectively.

The ICS1522 has a VDDO pin which is the supply of +5 volt
power to all output drivers. This pin should be connected to the
power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have low series inductance and be mounted close to the ICS1522.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for
this pin (as shown in the recommended application circuitry).
This will allow the PLL to "track" through power supply
fluctuations without visible effects.

Pin Descriptions
PIN NUMBER
I

PIN NAME

TYPE

DESCRIPTION

!PUMP

OUT

Charge Pump Output (External loop filter applications)
Serial Data Input/Output

2

SDATA

IN/OUT

3

SCLK

IN

Serial Clock Input

4

SELn

IN

Senal Port Enable (ActIve Low)

5

AVDD

PWR

Analog +5 Volt Supply

6

XTALIIEXTREF

IN

External Reference Input / Xtal Oscillator Input

7

XTAL2

OUT

Xtal OscIllator Output

8

FINE

IN

Fme Phase Adjust Input

9

VSS

PWR

Ground

10

VSS

PWR

Ground

11

OUT4

OUT

Output 4

12

OUT3

OUT

Output 3

13

VDDO

PWR

Output Driver +5 Volt Supply

14

OUT2

OUT

Output 2

15

OUT!

OUT

Output I

16

VSS

PWR

Ground

17
18

IPRG

IN

Output Driver Current Programming Input

CLK-

OUT

DIfferential CLK- Output

19

CLK+

OUT

Differential CLK+ Output

20

VDD

PWR

Digital +5 Volt Supply

21

PDEN

IN

Phase Detector Enable (Active High)

22

EXTFBK

IN

External Feedback Input

23

EXTVCO

IN

External VCO Input

24

VVCO

IN

VCO Control Voltage Input (External loop filter applications)

E·6

II

ICS1522

ICS1522 Register Definition
REG#

BIT(S)

BIT REF.

o

0-10

F[O:IO]

Feedback Divider (Default=04F, Modulus=80)
Divides the veo by the set modulus
Modulus Range=64 to 2048; Modulus=Value+ 1

0-7

LO[0:7]

Feedback Sync Pulse La (Default=03)
Feedback Divider output, but with programmable phase;
LO[0:7] ~F[3: 10].

2

0-7

HI[0:7]

Feedback Sync Pulse HI (Default=06)
Feedback Divider output, but with programmable phase;
HI[0:7] ~[3:10].

3

0-9

R[0:9]

Reference Divider (Default=013, Modulus=20)
Divides the XTAIlEXTREF by the set modulus
Modulus Range= 1 to 1024; Modulus=Value+ 1

3

10

REF_POL

External Reference Polarity (Default=O)
O=Positive Edge; l=Negative Edge

4

0-2

VeO[0:2]

veo Gain (Default=4)

DESCRIPTION

.-

VCO[2]

VeO[l]

VeO[O]

VeOGAIN

0

0

0

0

0
1

15MHzIV

0

1

0

20MHzIV

0

1

I

25MHzIV

I
1
1

0

0

45MHzIV

0
1

I
0

60MHzIV
75MHzIV

1

1

1

90MHzIV

E·7

lOMHzIV

-.-

ICS1522
REG#

4

BIT(S)

BIT REF.

3-5

PFD[0:2)

DESCRIPTION
Phase Frequency Detector Gain (Default=3)
PFD[2)

PFD[l)

PFD[O)

PFDGAIN

FINE PHASE
ADJ.

0

0

0

.2344uAl2nrad

3nsN

0

0

1

.9375uAl2nrad

3nsN

0

1

0

3.750uAl2nrad

3nsN

0

1

1

15.00uAl2nrad

3nsN

1

0

0

1. 875uA12nrad

6nsN

1

0

1

7.500uAl2nrad

6nsN

1

1

0

30.00uA/2nrad

1.5nsN

1

1

1

120.0uAl2nrad

.375nsN

4

6

PDEN

Phase Frequency Detector Enable (Default= 1)
O=PFD Disable; l=PFD Enable

4

7

INT_FLT

Loop Filter Select (Default= I)
O=External Loop Filter (IPUMP & VVCO active)
l=Internal Loop Filter

4

8

INT_VCO

VCO Select (Default=!)
O=External VCO (EXTVCO active)
l=Internal VCO

4

9

CLK_SEL

Feedback Divider Clock Input Select (Default=O)
O=VCO; l=OUTl

4

10

RESERVED

Must be set to one.

5

0

FBK_SEL

Feedback Select (Default= 1)
O=External Feedback (EXTFBK active)
l=Internal Feedback
An active external feedback signal at EXTFBK is necessary to
synchronously switch to internal.

FBK_POL

External Feedback Polarity (Default=O)
O=Positive Edge; l=Negative Edge

5

5

2

ADD

Addition of 1 VCO Cycle (Default=O)
Toggle (0 to 1 to 0) to add 1 VCO cycle.

5

3

SWLW

Removal of 1 VCO Cycle (Default=O)
Toggle (0 to 1 to 0) to remove 1 VCO cycle.

E-8

ICS1522
REG#

5

5

BIT(S)

BIT REF.

4-5

PDA[O:l]

6-7

PDB[O:l]

DESCRIPTION
Output Post-scaler (Default=O)
Input=VCO; Output=Differential Output
PDA[l]

PDA[O]

DIVIDE BY

0

0

8

0

1

4

1

0

2

1

I

1

Feedback Post-scaler (Default=3)
Input=Feedback Divider; Output=PFD
PDB[I]

PDB[O]

0

0

8

0

I

4

1

0

2

1

1

-

5

8

LD_LG

Fine Phase Adjust LeadlLag (Default=!)
l=FBK will lag REF at input to PFD
O=FBK will lead REF at input to PFD

5

9

F_EN

Fine Phase Adjust Enable (Default=O)
O=Disable; l=Enable

5

10

RESERVED

Must be set to one.

6

0-2

L[0:2]

Load Counter (Default=7)
L[2]

L[l]

L[O]

0
0
0
0
1

0
0
1

0
1
0
1
0
1
0
1

1
1
1

E·'

1
0
0
1
1

DIVIDE BY

--

I
~--

-

DIVIDE BY
3 I-pos, O-neg
4 posedge
4 neg edge
5 I-neg, O-pos
6 posedge
8 pos edge
8 neg edge
10 neg edge

!'

"

II

II

ICS1522
BIT(S)

BIT REF.

6

3

OMUXI

OUTl Select (Default=O)
O=Load Counter Output
I=Diff. Output Divided by 4 at 0 Degrees
OUTl will track OMUXI when AUXEN=1

6

4

OMUX2

OUT2 Select (Default=O)
O=Internal Feedback Pulse
I=Diff. Output Divided by 4 at 90 Degrees
OUT2 will track OMUX2 when AUXEN=l

6

5

OMUX3

OUT3 Select (Defau!t=O)
O=Feedback Sync Pulse LO
!=Diff. Output Divided by 4 at 180 Degrees
OUT3 will track OMUX3 when AUXEN=1

6

6

OMUX4

OUT4 Select (Default=!)
O=Feedback Sync Pulse HI
!=Diff. Output Divided by 4 at 270 Degrees
OUT4 will track OMUX4 when AUXEN=1

6

7

DACRST

Output Reset (Default=O)
When set to one, the CLK+ output is kept high and the CLKoutput is kept low. When returned to zero, the CLK+ and CLKoutputs will resume toggling on a rising edge of the OUT! output
(programmed for Load Counter) within +/- 1 clock period.

6

8

AUXEN

Output Test Mode (Default=O)
O=Nonnal Output Operation
l=Output Test Mode (see OMUXI-4 and AUXCLK)

6

9

AUXCLK

Output Clock when in Test Mode (Default=O)
CLK+ and CLK- will track AUXCLK when AUXEN=1

6

10

EXTREF

XTALlEXTREF Input Buffer (Defau!t=O)
O=Crysta! Input Operation
!=External Reference Input Operation

REG#

DESCRIPTION

E·I0

II

ICS1522

Serial Programming Timing Diagram

C14

C16

1.J1J1JL

SCLK
SELn

C15

~~------------------_"------~I

SDATA
WRITE CYCLE

L..--J"-----I"--_D1

;;~/O//I/

SDATA
READ 1ST CYCLEJ.I.I..J.I..jUJI
(SDATA INPUT)

Hlfuum

SDATA
READ 2ND CYCLE.I.I.I""''''-............I...._..J _ _...I
(SDATA OUTPUT)

t

Data loaded
into memory

NOTES:

1. RlWn, READ=l and WRITE=O
2. Address and data transmitted least significant bit first
3. 16 Positive-edge clocks required for complete data read/write
(l-RlWn, 3-Address, ll-Data, and 1 load data W/SELn HIGH)
4. SELn's positive and negative transitions must occur on the same state of SCLK
5. An ICS1522 read consists of two consecutive cycles
(lst cycle - SDATA is an input, 2nd cycle - SDATA is an output)

E·ll

II

ICS1522
Absolute Maximum Ratings
VDD, VDDO (measured to Vss) ................
Digitaiinputs ...............................
Digital Outputs ..............................
Ambient operating temp .......................
Storage temperature ..........................
Junction temperature ..........................
Soldering temperature .........................

7.0V
Vss -0.5 to VDD to 0.5V
Vss -0.5 to VDDO to +0.5V
-55 to 125°C
-65 to ISO ° C
175° C
260°C

Recommended Operating Conditions
VDD, VDDO (measured to Vss) ................ 4.75 to 5.25V
Operating Temperature (Ambient) ............... 0 to 70°C

DC Characteristics
TTL-Compatible Inputs
"

"

~

E

=

__

'

PDEN, EXTFBK, SDATA, SClK, SEln, and XTAl1/EXTREF (when EXTREF bit set to 1)
PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Input High Voltage

Vih

2.0

VDD+0.5

V

Input Low Voltage

Vii

Vss - 0.5

0.8

V

.20

.60

V

10
200
8

uA

Input Hysteresis
Input High Current

Iih

V,h= VDD

-

Input Low Current

Iii

Vii =0.0

-

Input Capacitance

Cin

-

uA
pf

EXTVCO Input
PARAMETER

MIN

MAX

UNITS

Input High Voltage

Vxh

3.75

V

Input Low Voltage

Vxl

Vss - 0.5

VDD+0.5
1.25

MIN

MAX

SYMBOL

CONDITIONS

ClK+, ClK- Outputs
PARAMETER

SYMBOL

CONDITIONS

Differential Output Voltage

0.6

OUT1, OUT2, OUT3, OUT4 Outputs
PARAMETER

SYMBOL

CONDITIONS

Output High Voltage (Ioh=4.0mA)
Output Low Voltage
(Iol=8.0mA)

E-12

MIN

MAX

UNITS

2.4

-

V

-

0.4

V

II

ICS1522

AC Characteristics
SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

Fvco

VCO Frequency

14

230

MHz

Fxtal
Cpar

Crystal Frequency

5

20

MHz

100

kHz

Crystal Oscillator Loading Capacitance

20

Horizontal Sync Rate

15

Txlu

XTALl High Time (when driven externally)

8

Txlo

XTALl Low Time (when driven externally)

8

TnT

Phase Jitter (see Note 1)

FHSYNC

Tlock

pF
ns
ns
1

PLL Acquire Time (to within 1%)

500

ns
~s

Idd

VDD Supply Current

15

rnA

Iddo

VDDO Supply Current (excluding CLK+/termination)

20

rnA

ANALOG INPUTS
TFINE

Fine Phase Adjustment Range

0

15

VFINE

Control Voltage for FINE

0

5

VDC

FINE Input Bias Current

20

nA

Capacitance of FINE Input

100

pf

1.5

kHz

Bandwidth of FINE Input (3dB)

0.5

--

ns

--

-----

DIGITAL INPUT
SELn, SDATA Setup Time

10

ns

SELn, SDATA Hold Time

10

ns

SCLK Pulse Width (Thi or Tlo)

20

ns

SCLK Frequency

20

MHz

Phase-frequency detector enable time

50

ns

Phase-frequency detector disable time

50

ns

DIGITAL OUTPUTS
TSKEW

Time Skew between CLK+, CLK-

500

ps

FCLK

CLK+ and CLK- Clock Rate

230

MHz

GAINS
VCO

VCO Gain, VCO(0:2)

10

90

MHzIV

PFD

Phase Detector Gain, PFD (0:2)

.23

120

~Al21trad

Note 1: TnT is the total uncertainty of the phase measured at the start of a video line on a 350 MHz oscilloscope under these
conditions: HSYNC pin driven with crystal oscillator at 48.363 kHz; Fvco = 65.000 MHz; M =0
(divide by 1 on the output; and N = 1343 (1344 clocks per line).

E-13

ICS1522
Memory Definition
ICS1522 memory is loaded serially with the least significant bit clocked into the device first. After the RlWn bit, the next three
bits of the programming word (15 bits) hold the memory location to be loaded. The least significant 11 bits are the data to be
loaded (see Timing Diagram).

-

DATA BITS

DEFAULT
VALUES
(HEX)

NAME

0-10

04F

F(O:lO)

001

0-7

03

LO(0:7)

001

8-10

0

MEMORY
ADDRESS
000

DESCRIPTION
Feedback Divider Modulus (Modulus = Value + 1)
M Counter Lo Sync State
Don't Care

010

0-7

06

010

8-10

0

HI(0:7)

011

0-9

013

R(0:9)

011

10

0

REF POL

External Reference Polarity (1 =Invert)

100

0-2

4

VCO(0:2)

VCOGain

100

3-5

3

PFD(0:2)

Phase Detector Gain

100

6

1

PDEN

100

7

1

!NT FLT

Internal Loop Filter (1 = Internal)

M Counter Hi Sync State
Don't Care
Reference Divider Modulus (Modulus = Value + 1)

Phase Detector Enable (1 =Enable)

100

8

1

INT3CO

Internal VCO (1 = Internal)

100

9

0

CLK SEL

Internal feedback input clock select (0 = VCO Output)

100

10

1

Reserved

Reserved - Set to One

101

0

1

FBK SEL

Feedback Select (1 =Internal)

WI

I

0

FBK POL

External Feedback Polarity (1 =Invert)

WI

2

0

ADD

WI

3

0

SWLW

WI

4-5

0

PDA(O:I)

WI

6-7

3

PDB(O:I)

101

8

I

LD LG

WI

9

0

F_EN

WI

10

I

Reserved

Addition of 1 VCO Cycle (0 to 1 = Add)
Removal of I VCO Cycle (0 to I = Swallow)
Output Post-Scaler
Feedback Post-Scaler
Fine Phase Adj. LeadlLag (I=Lead)
Fine Phase Adj. Enable (1=Enable)
Reserved - Set to One

110

0-2

7

L(0:2)

110

3

0

OMUXI

OUT! Select (0 = Load Cntr, I = Div By 4 ODeg)

110

4

0

OMUX2

OUT2 Select (0 = Int Fbk, 1 = Div By 4 90Deg)
OUT3 Select (0 = Sync Lo, 1 = Div By 4 180Deg)

Load Counter

110

5

0

OMUX3

110

6

1

OMUX4

OUT4 Select (0 = Sync Hi, 1 = Div By 4 270Deg)

110

7

0

DACRST

Output Reset (CLK+ = I, CLK- = 0)

110

8

0

AUXEN

110

9

0

AUXCLK

Output Clock When in Test Mode

110

10

0

EXTREF

XTAIJEXTREF Input Buffer (I=EXTREF)

E·14

Output Test Mode (1 = Test, See Board Test Support)

ICS1522
Pixel-by-Pixel Adjustment of
Genlocking Phase (ICS1522 Application)
To understand the operation of the pixel-by-pixel phase adjustment feature, imagine that the modulus of the on-chip divider
is equivalent to the graphics system overall divide. Also
imagine that the overflow of the internal divider occurs at th~
same time as the overflow of the graphics system line counter.
Initial synchronization is accomplished by switching from the
external feedback source (graphics system HSYNC) to the
internal feedback. Let us assume that we are now using the
internal divider.

Now, imagin.e t.hat the programmed value of the divider (really
a prescaler) IS Increased by one for a single pass-through that
pr.escaler (think of this as "swallowing" a feedback pulse). We
will lose exactly one CLK period of phase in the feedback path.
The VCO will speed up momentarily to compensate for that,
and re-lock the loop.
In doing so, the graphics system will receive exactly one extra
CLK cycle, advancing the phase of the graphics system
HSYNC by one CLK period relative to the reference HSYNC.
In a similar fashion, we can decrease the programmed value of
the prescaler ("adding" a pulse) to retard the phase of the
graphics system. Additionally, sub-pixel phase adjustment is
provided through varying the voltage at the FINE input pin.

Ordering Information
ICS1522M
Example:

ICS XXXX M

L~_
M=SOIC

L

__________

Device Type (consists of 3 or 4 digit numbers)
PrefIX
ICS, AV=Standard Device; GSP=Genlock DeVIce

PRODUCT PREVIEW documents contain informatIOn on products In the formabve or design

phase of development CharactenstlC data and other specificatIOns are design goals
reserves the right to change or discontinue these products without notICe

E-lS

les

E-16

ICS1522

Integrated
Circuit
Systems, Inc.

•

Application Note

Line-Locked Applications Design Supplement
Line-Locked Applications
The term "Line-Locked" refers to ICS1522 applications where
one of the outputs of the ICS1522 will be locked to some
multiple of a reference frequency provided to it. A typical
application of the ICS1522 is generation of a sampling clock
for an AID converter that is digitizing the video output of a PC.
Normally, this sampling clock should be of the same frequency
as the clock which generated the video for best performance
(fewest artifacts in the reproduction). Such a clock can be
generated by the ICS1522 by using the PC's HSYNC signal
as the reference for the ICS1522 and programming it to multiply that frequency.
A step-by-step procedure for determining loop filter values and
other programmable parameters follows.

Selection of External Components for
Line-Locked Applications
ICS generally recommends use of an external loop filter with
the ICS1522 for line-locked applications. The fixed internal
loop filter cannot achieve a good compromise over the full
range ofline-Iocked applications that the ICS1522 can handle.
Hence, the tuning of the filter values was skewed for normal
clock synthesis (similar to ICSl562 "loop tuning"). Much
better phase margin and loop damping will be achieved with
an external loop filter. This document should help designers
quickly arrive at the correct component values for the external
loop filter and the correct programming of the device it~elf.
Calculation for Section I is normally done once for a gIven
application, calculation of Sections II & ill should be done for
all expected cases (or the calculation should be imbedded
within the application firmware).

ICS1522 External Loop Filter
Recommended Power Distribution and Filter Configuration

VDD~~---------------------------------------------------,

10

Possible External
Component Values

Approx. Internal
Component Values

R1=51k
C1=.01IlF
C2= 0011lF

R1=120k
C1=110pF
C2=11pF

(Reg. 4, Bit 7=0)

(Reg 4, Bit 7=1)

PFD & VCO Gains, In addition to the External Loop Filter values,
might require adjustment to achieve the desired PLL performance.

1522AppRevA111794

E·17

II

Application Note

ICS1522
I.

Calculation of External loop Filter Component
Values

II.

Enter the lowest reference frequency that will be used in the
application (usually 15 kHz for TV, 31.5 kHz for VGA):
Freference =15 kHz
We next set the modulus of the Reference Divider. This should
always be set to one for a line-locked application:
Nreference =1
Select the phase detector gain to be used. We recommend that
the higher gain settings be used to minimize the resulting
impedances of the loop filter components. Normally, set:

From the data sheet, we enter the actual value at a setting of 6
into a variable:
GainpFD =

30J.lA
2nrad

R =69.l15k.Q

... we substitute the nearest 5% value:

The value of the capacitor in series with the resistor sets the
damping of the loop. Again, a good compromise will be
achieved when:
50
21tFreferenceR

Next, the Feedback Divider Modulus, LOAD CounterlDivider
Modulus (or the modulus of the Divide-by-4, if used instead),
Output Post Scaler, and VCO Gain must be selected. First,
determine if the line-locked clock frequency is to be taken from
the differential CLK outputs of the ICS1522, or the OUTI pin
of the ICS1522.

If the output is to be taken from the differential CLK outputs,
the product of the LOAD Divider Modulus, Feedback Divider
Modulus, and Feedback Post-Scaler (=1) must be set equal to
the desired number of cycles of the CLK output per reference
period. For this example, we assume that 1000 CLK cycles per
reference clock is desired, and the RAMDAC used requires the
LOAD CounterlDivider Modulus to be 8 .
First, we set the modulus of the feedback divider post scaler:

R=68K.Q

Cl =

As stated above, the Reference Divider modulus will be set to
divided-by-l in a line-locked application. The Feedback Divider Post-Scaler is also normally set to divide-by-1. The
selection of the input source for the Feedback Divider will
normally also be set to OUT1. When these options have been
set, the phase of one of the OUTI edges will be aligned with
the reference clock. This is normally what is desired. This
allows for correct alignment of the pixel boundaries in multiple-byte-per-pixel applications, such as true-color. It also allows for proper alignment of multi-byte interface RAMDACTM s
in line-locked applications, (i.e., the RAMDAC LOAD clock
will be consistently aligned with the reference clock).

lI(a). Line-locked Output Taken from ClK Outputs

We next calculate the value of the resistor in the loop filter as
a function of that gain. A good compromise is obtained when:
R _ 0.33 volt
- GainpFD

Calculation of Divider Parameters within the
ICS1522

Nfeedback_poscscaler =1
Then, we set the number of clocks desired per reference period
Nciocks_perJeference =1000

Cl=7.802nF

Next, we set the modulus of the LOAD CounterlDivider (or
the modulus of the separate multi-phase divide-by-4, if used):

... we substitute the nearest 10% value.

NLOAD=8

Cl=8.2nF
Next, we calculate the value of the capacitor connected in
parallel with the series R & Cl combination:

This capacitor gives improved high-frequency noise rejection,
but is not necessary for loop stability.

RAMDAC IS a trademark of Brooldree Corporabon

E-18

Application Note

ICS1522
We calculate the required modulus of the feedback divider as:
Nfeedback =

Once again, that frequency is relatively low for the vco.
Therefore, we will set the Output Post-Scaler to divide-by-4.

NclocksJler_reference
Nfeedback =125
NLOADNfeedbackJXlst_scaler

NoutputJlOst_scaler =4

The frequency of the CLK output will then be the product of
those dividers times the reference frequency:
FCLK =FreterenceNfeedbackNfeedbackJXlst_sca1erNLOAD

The VCO frequency (for this case) will be:

III. Calculation of VCO Gain Required:

FCLK=lSMHz

That frequency is relatively low for the VCO. We reco=end
that the VCO be operated at the highest frequency within its
range. Therefore, we will set the Output Post-Scaler to divideby-8.

We establish the minimum VCO gain needed as the following
function of the VCO frequency (using the Fvco calculation of
II(b). above):
gainvco minimum = Fvco gainvco minimum =41.143 MHz
3.s volt
volt

NoutputJlOSt_scaler = 8

From the data sheet we see that a VCO gain of 4 is the lowest
setting that will meet the requirement, and we set the programmingva1ue:

The VCO frequency can then be calculated:
Fvco =FCLKNoutputJlOSt_scaler

Fvco = 120 MHz

... which is within the VCO maximum frequency limit.
We also make a variable that contains that VCO gain value:

Il(b). Line-Locked Output Taken from OUT1 output.
Once again:

Gainvco =

N feedbackJlOst_scaler = 1

If the pixel clock is to be taken from the OUTI output, the
product of the Feedback Divider and Feedback Post-Scaler
(= 1) must be equal to the desired number of OUT 1 clocks per
line. Suppose that we want 800 OUTI cycles per reference
clock. We simply then set the Feedback Divider Modulus to
be:
Nfeedback =800
Perhaps we would like the frequency of the CLK outputs to be
three times the OUTI frequency (as ina true-color, three-bytes
per pixel, application). We would set the LOAD Counter/
Divider Modulus:
NLOAD =3
and then the frequency of the CLK outputs will be ...
FCLK =FreferatceNfeedbackNfeedbackJXlst_ scalerNLOAD
FCLK=36 MHz

E-19

45 MHz

--wit

Application Note

ICS1522
IV.

Programming Summary

SWLW=O

We now have all of the infonnation that we need to program
the ICS1522. Summarizing all of the above calculations and
using the example shown in lIb above:

< --- "0" for external feedback,
"1" for internal feedback
< --- "0" causes reference to lag
feedback, "1" causes reference to
lead feedback when Fine Phase
Adjust is enabled

Nfeedback=800

< --- "0" disables, "1" enables
Fine Phase Adjust

Nreference= 1
VCO_Gain_Setting=4
OMUX1 =0

< --- "0" for LOAD Divider/
Counter, "1" for multi-phase
divide-by-four (0 0 phase)

OMUX2=0

< --- "0" for output of internal
feedback divider chain, "1" for
multi-phase divide-by-four
(90 0 phase)

OMUX3=0

< --- "0" for feedback sync
pulse LO, "1" for multi-phase
divide-by-four (1800 phase)

OMUX4=0

< --- "0" for feedback sync
pulse HI, "1" for mUlti-phase
divide-by-four (270 0 phase)

DACRST=O

< --- "0" for normal operation,
"1" to reset pipeline delay of
Brooktree RAMDACs

< --- sets phase of auxiliary (HI)
feedback divider output

AUXEN=O

< --- "0" for normal operation,
"1" for output test mode

< --- "0" for positive edge locking, "1" for negative edge

AUXCLK=O

< --- selects level on CLK outputs
when AUXEN ="1"

PDEN=1

< --- "0" to disable PLL locking,
"1" to enable it

EXTREF=1

< --- "0" for crystal oscillator,
"1" for external reference

INT_FLT=O

< --- selects external loop filter

INLVCO=1

< --- "0" to substitute external

PFD_Gain_Setting=6
We convert the modulus of the Output Post-Scaler, Feedback
Post-Scaler, and LOAD Divider/Counter to programming of
the PDA, PDB, and L bits respectively by looking it up from
the data sheet:
Noutpucposcscaler =4

--- >

PDA=1

Nfeedback_poscscaler =1

--- >

PDB=8

NLOAD=3

--- >

L=O

Other parameters that must be set are (some of these will vary
depending on the specifics of the application):
LO=O

< --- sets phase of auxiliary (LO)
feedback divider output

HI =0

RESERVED =1

VCO, "1" for internal VCO

< --- "0" for locking CLK to
reference, "1" for locking OUT!
to reference

< --- "0" for external feedback,
"1" for internal feedback

< --- "0" for locking to reference
positive edge; "1" for internal
feedback
ADD =0

< --- toggle "0" to "1" to "0"
to add increment

E·20

Application Note

ICS1522
V.

Calculate Register Values
RO =Nfeedback - 1
RI=LO
R2=HI
R3 =(Nreference - I) + REF]OL 2 10
R4 =(VCO_Gain_Setting 2°) + (PFD_Gain_Setting 2 3) + (PDEN 26 )
+ (INT]LT 27) + (INT_VCO 28) + (CLK_SEL 29 ) ...
+ (RESERVED 2 10)

...

RS =FBK_SEL + (FBK_POL 21) + (ADD 22) + (SWLW 2 3) + (PDA 24) ...
+ (PDB 26 ) + (LD_LG 28 ) + (F_EN 29 ) + (RESERVED 2 10)
R6 =(L 2°) + (OMUXI 2 3) + (OMUX2 24) + (OMUX3 25) + (OMUX4 26) ...
+ (DACRST 27) + (AUXEN 28) + (AUXCLK 29 ) + (EXTREF 2 10)

With the above values:
RO =799

or:

Rl =0

or:

RI =1

R2=0

or:

R2=0

RO=3Ifh

R3 =1024

or:

R3 =400h

R4 =1908

or:

R4=774h

RS =ISS3

or:

RS =61lh

R6 =1024

or:

R6 =400h

E·21

E·22

•

ICS1561 A

Integrated
Circuit
Systems, Inc.

Product Preview

Differential Output PLL Clock Generator
Description

Features

The ICS1561A is a very high perfonnance monolithic PLL
frequency synthesizer. Utilizing ICS's advanced CMOS mixed
mode technology, the ICS1561A provides a low cost solution
for high-end video clock or Teleciock™ generation.

•

The ICS1561A has differential clock outputs (CLK and
CLK*) that are compatible with industry standard video DACs
& RAMDACsTM. Additional clock outputs, FDIY2, FDIY4
and FDIY8, provide frequencies which are 112, 114 and 118 the
main clock frequency.
Operating frequencies are selectable from a preprogrammed
(customer defined) table. An on-chip crystal oscillator for
generating the reference frequency is provided on the
ICS1561A.

•
•
•
•
•
•
•
•

High Frequency operation for extended video modes - up
to 230 MHz
Compatible with Brooktree high perfonnance RAMDACs
Low Cost - Eliminates need for multiple ECL crystal clock
oscillators in video display subsystems
Advanced PLL for low phase-jitter
Dynamic control of YCO sensitivity provides optimized
loop gain over entire frequency range
StrobedlTransparent frequency select options
Small footprint - 20-pin DIP or SOIC packages available
Fully backward compatible to ICS156l
-728 option capable of STS-3/STM-I communication
clock generation

The ICS1561A-728 is an excellent low-jitter 155.52 MHz
Teleclock source for communications systems. When addressed at 1910 (13 hex) with a 19.44 MHz reference, the
ICS1561A-728 provides an STS-3 (STM-l) differential clock
that is compatible with SONET and ATM transmitters.

Block Diagram

IR

FSO ....
FS1 ....
FS2 ....

ROM

FS3 ....
FS4 ....

STROBE ....

1.-_-1

I

r-------~~------------..
DRIVER

~FDIV2

DIFF
OUTPUT

t

ClK

+
ClK-

FDIV8

RAMDAC IS a trademark of Brooktree Corporation
Teleclock IS a trademark of Integrated CirCUit Systems, Inc
IICS1561ARevB081694

E-23

II

ICS1561A
Pin Configuration
FS1
FSO
STROBE
VDD
XTAl1
XTAl2
FOUT
VSS

2
3
4
5
6
7
8
9
10

Reserved

AVDD

=Vss and <=VDD.

DC Characteristics
(Power Supply Voltage 4.75-5.25 Volts)
--

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

--,----_.

UNITS

Input Low Voltage

VIL

VDD=5V

Vss

0.8

V

Input High Voltage

VIH

VDD=5V

2.0

VDD

V

Input Leakage Current

IIH

VIN=VDD

-

10

/.LA

Output Low Voltage

VOL

IOL=8.0mA

-

0.4

V

Output High Voltage

VOH

IOH=4.0mA

2.4

-

V

Supply Current

IDD
Rup

VDD=5V

-

30

rnA

Internal Pull-up Current

VDD=5V

25

100

Input Pin Capacitance

CIN

Fc=IMHz

8

/.LA
pf

COUT

Fc=IMHz

-

12

pf

Output Pin Capacitance

E·25

II

ICS1561A
Frequency Synthesizer Description

Circuit Description
Overview
The ICS1561A is designed to provide the graphics system
clock signals required by industry standard RAMDACs. One
of 32 pre-programmed (user definable) frequencies may be
selected under digital control. Fully programmable feedback
and reference divider capability allow virtually any frequency
to be generated, not just simple multiples of the reference
frequency. The ICS1561A uses the latest generation of frequency synthesis techniques developed by ICS and is completely suitable for the most demanding video applications.

The reference frequency is generated by an on-chip crystal
oscillator, or the reference frequency may be applied to the
ICS1561A from an external frequency source.
The ICS1561A generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL. The phase-frequency detector shown in the
block diagram drives the VCO to a frequency that will cause
the two inputs to the phase frequency detector to be matched
in frequency and phase. This occurs when:

Digital Inputs
The FSO-FS4 pins and the STROBE pin are used to select the
desired operating frequency from the 32 pre-programmed frequencies in the ROM table of the ICS1561A. The FSO-FS4
and STROBE pins are each equipped with a pull-up and will
be at a logic HIGH level when not connected.
Transparent Mode - When the STROBE pin is held HIGH, the
FSO through FS4 inputs are transparent; that is, they directly
access the ROM table. The synthesizer will output the frequency programmed into the location addressed by the FSOFS4 pins.
Latched Mode - When the STROBE pin is held LOW, the
FSO-FS4 pins are ignored. The synthesizer will output the
frequency corresponding to the state ofthe FSO-FS4 pins when
the STROBE pin was last HIGH. In the event that the
ICS1561A is powered-up with the STROBE pin held LOW,
the synthesizer will output the frequency programmed into
address 0 (i.e., the one selected with FSO through FS4 at a logic
LOW level).

Divided Dot clock Outputs

F

_ F(XTALl) * Feedback Divider
Reference Divider

(VCO)-

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided
to the part (assuming correctly programmed dividers). The
divider programming is one of the functions performed by the
ROM lookup table in the ICS1561A. The VCO gain is also
ROM programmable which permits the ICS1561A to be optimized for best performance at each frequency in the table.
The feedback divider makes use of a dual modulus prescaler
technique that allows construction of a programmable counter
to operate at high speeds while still allowing the feedback
divider to be programmed in steps of 1. This is an improvement
over conventional fixed prescaler architectures that typically
impose a factor-of-four penalty (or larger) in this respect.
A post divider may be inserted between the VCO and the CLK
and CLK outputs of the ICS1561A. This is useful in generation
of lower frequencies, as the VCO has been optimized for high
frequency operation. Different post divider settings may be
used for each frequency in the table.

The ICS1561A has additional outputs which provide a 12, /4
and /8 of the main frequency.

Output Stage Description
The CLK and CLK outputs are each connected to the drains of
P-Channel MOSFET devices. The source of each of these
devices is connected to VDDO. Typical on resistance of each
device is 15 Ohms. These outputs will drive the clock and
clock* of a RAMDAC device when a resistive network is
utilized.
The divided outputs are high current CMOS type drives.

E-26

ICS1561 A
Bus Clock Interface

Application Information
Power Supplies
The ICS1561A has a VDDO pin which is the supply of +S volt
power to all output stages. This pin should be connected to the
power plane (or bus) using standard high frequency decoupling
practice. This decoupling consists of a low series inductance
bypass capacitor, using the shortest leads possible, mounted
close to the ICS1561A.
The AVDD pin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend that
RC decoupling or zener regulation be provided for this pin (as
shown in the recommended application circuitry). This will
allow the PLL to "track" through power supply fluctuations
without visible effects.
Crystal Oscillator and Crystal Selection

The ICS1561A has circuitry onboard to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti (also
called parallel) resonant mode. See the AC Characteristics for
the effective capacitive loading to specify when ordering crystals.

In some applications, it may be desirable to utilize the bus
clock. To do this, connect the clock through a .047uF capacitor
to XTALl (S) and keep the lead length of the capacitor to
XTALl (5) to a minimum to reduce noise susceptibility. This
input is internally biased at VDD/2. Since TTL compatible
clocks typically exhibit a VOH of 3.SY, capacitively coupling
the input restores noise immunity. The ICS1561A is not sensitive to the duty cycle of the bus clock; however, the quality
of this signal varies considerably with different motherboard
designs. As the quality of the bus clock is typically outside the
control of the graphics adapter card manufacturer, it is suggested that this signal be buffered on the graphics adapter
board. XTAL2 (6) must be left open in this configuration.
ICS1561 A Interface

The ICS1561A should be located as close as possible to the
video DAC or RAMDAC. The differential output CLOCK
drivers are current sourcing only and are designed to drive
resistive terminations in a complementary fashion. CLK and
CLK connections should follow good ECL interconnection
practice. Terminating resistors should be as close as possible
to the RAMDAC.

So-called series resonant crystals may also be used with the
ICS1561A. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the can
(typically O.OOSO.OI %).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1561A outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.

E-27

II

ICS1561A
ICS1561 A Standard Patterns

ICS produces standard frequency patterns for the ICS1561A. These patterns include the majority of frequencies most customers
require. Custom patterns are also available. although a significant volume commitment and/or one-time mask charge will apply.
Contact ICS sales for details.
ICSI561AICS Part
706
Number
Video Clock Frequency
(MHz)
Address
(HEX)
12.273
0
14.560
1
2
15.619
25.199
3
4
27.862
30.320
5
31.500
6
38.571
7
43.388
8
50.400
9
50.664
A
51.244
B
54.981
C
57.272
D
E
62.999
64.010
F
10
68.727
11
75.170
12
88.111
99.272
13
14
99.272
100.227
15
16
111.531
17
125.999
18
139.999
19
160.363
lA
179.999
1B
200.454
lC
216.363
59.999
1D
IE
249.917
IF
7.860
Reference
14.31818
Frequency
MHz

ICSI561A707
Frequency
(MHz)

ICSI561A723
Frequency
(MHz)

ICSI561A724
Frequency
(MHz)

ICSI561A725
Frequency
(MHz)

ICSI561A726
Frequency
(MHz)

ICSI561A727
Frequency
(MHz)

ICSI561A728
Frequency
(MHz)

25.144
28.188
32.454
36.060
37.447
39.841
44.822
57.272
64.145
65.082
72.344
74.454
76.363
80.181
84.401
98.181
100.227
107.386
107.807
110.139
111.449
129.818
134.759
139.999
160.363
169.328
179.999
200.454
126.602
128.021
132.631
136.636
14.31818
MHz

100.227
104.999
109.963
115.387
119.999
124.958
130.024
135.104
139.999
145.090
149.999
154.636
160.363
164.945
169.970
174.832
179.999
184.704
190.431
194.727
200.454
204.976
209.999
214.772
219.927
225.511
230.775
235.119
239.999
245.454
249.917
255.123
14.31818
MHz

100.227
101.911
104.132
106.123
108.181
109.963
111.860
113.703
115.847
117.914
120.000
122.255
124.090
125.999
128.021
130.024
132.167
133.917
136.022
137.975
140.000
141.880
144.000
146.197
147.954
150.340
151.772
154.285
155.590
158.454
160.363
162.272
14.31818
MHz

150.340
151.772
154.285
155.590
158.454
160.363
162.272
163.636
165.893
167.999
169.970
171.818
173.553
175.909
178.181
179.999
182.045
183.933
186.136
188.181
190.431
191.505
193.772
196.363
198.545
200.454
202.140
203.823
206.181
208.264
209.999
212.245
14.31818
MHz

87.954
80.181
66.818
60.000
49.943
10.090
32.005
24.080
43.977
40.090
33.409
30.000
24.971
20.045
150.000
160.363
169.970
180.000
190.431
200.454
209.999
219.927
230.775
240.000
249.917
259.930
269.999
279.999
289.943
299.580
309.793
PwrDwn
14.31818
MHz

119.999
124.090
132.167
136.Q22
139.999
143.999
147.954
151.772
155.590
160.363
163.636
168.000
171.818
175.909
179.999
183.933
188.181
191.505
196.363
199.772
203.823
208.264
212.245
216.363
219.927
223.721
227.406
231.694
235.828
239.999
248.181
PwrDwn
14.31818
MHz

20.045
24.971
30.000
35.000
40.090
44.999
49.943
54.981
59.999
64.982
69.999
74.895
80.181
84.985
89.999
95.215
99.886
104.999
109.963
114.545
119.999
124.958
129.965
134.999
139.999
144.971
149.790

Note: All frequencies above 180 MHz m the standard patterns shown above are experimental and are not guaranteed.

Order info: ICSI561AM-XXX or ICSI561AN-XXX (M =SOlC pkg., N

E-28

=DIP pkg., XXX =Pattern number)

154.8~
160.363
164.945
169.970
174.832
19.44
MHz

'

II

ICS1561A

Ordering Information
ICS 1561 AN-XXX

PRODUCT PREVIEW documents contain Information on products In
the formative or design phase of development.

or

ICS 1561 AM-XXX

Example:

ICS XXXX M -XXX

TL'--___
-

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
N=DIP (Elastic)
M=SOIC

' - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)

' - - - - - - - - - - - - - Pref"1X
ICS, AV=Standard Device; GSP=Genlock Device

E·29

CharacterIstic data

and other specifications are deSign gosls. lCS reserves the right to
change or discontinue these products without notice.

E·30

II

ICS1562A

Integrated
Circuit
Systems, Inc.

User Programmable Differential Output Graphics Clock Generator
Description

Features

The ICS1562A is a very high perfonnance monolithic phaselocked loop (PLL) frequency synthesizer. Utilizing ICS's advanced CMOS mixed-mode technology, the ICS1562A
provides a low cost solution for high-end video clock generation.

•

Two programming options:
ICS1562A-OOI (parallel Programming)
ICS1562A-201 (Serial Programming)

•

The ICS1562A has differential video clock outputs (CLK+ and
CLK-) that are compatible with industry standard video DAC.
Another clock output, LOAD, is provided whose frequency is
derived from the main clock by a programmable divider. An
additional clock output is available, LDIN2, which is derived
from the LOAD frequency and whose modulus may also be
programmed.

•
•

Operating frequencies are fully programmable with direct
control provided for reference divider, prescaler, feedback
divider and post-scaler.

•
•
•

Supports high-resolution graphics - CLK output to
260 MHz, with 400 MHz options available
Eliminates need for multiple ECL output crystal oscillators
Fully programmable synthesizer capability - not just a
clock multiplier
Circuitry included for reset of Brooktree RAMDAC pipeline delay
VRAM shift clock generation capability
( -20 1 option only)
Line-locked clock generation capability
External feedback loop capability (-201 option only)
Compact - l6-pin 0.150" skinny SOlC package

Reset of the pipeline delay on Brooktree RAMDACTM s may
be perfonned under register control. Outputs may also be set
to desired states to facilitate circuit board testing.

•

Fully backward compatible to ICS 1562

•

•

ICS1562A - 001 Pinout

Simplified Block Diagram -ICS1562A

ADO
XTAL1

1
r
J

EXTFBK
BLANK

2

16

AD1

15

AD2

XTAL2

3

14

AD3

STROBE

4

13

VDD
VDDO

VSS

5

12

(.201 only)

VSS

11

IPRG

----7

6

LOAD

7

10

CLK+

LD/N2

8

9

CLK·

PROGRAMMING
INTERFACE

16-Pin SOIC
K-6

FEEDBACK DIVIDER

MUX

CLK+
CLK-

ICS1562A - 201 Pinout
EXTFBK
LOAD

LDIN2

RAMDAC

IS

16

DATA

2

15

HOID

XTAL2

3

14

BLANK

DATCLK

4

13

VDD

VSS

5

12

VDDO

VSS

6

11

IPRG

LOAD

7

10

CLK+

8

9

CLK·

LDIN2

Figure 1

16-Pin SOIC
K-6

a trademark of Brooktree Corporation

IICS1562ARev8091294

XTAL1

I

E-31

II

ICS1562A
Overview

PLL Post-Scaler

The ICS1562A is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully programmable feedback and reference divider capability
allow virtually any frequency to be generated, not just simple
multiples of the reference frequency. The ICS1562A uses the
latest generation of frequency synthesis techniques developed
by ICS and is completely suitable for the most demanding
video applications.

A programmable post-scaler may be inserted between the YCO
and the CLK+ and CLK- outputs of the ICS1562A. This is
useful in generating lower frequencies, as the YCO has been
optimized for high-frequency operation.
The post-scaler allows the selection of:
• YCO frequency
• YCO frequency divided by 2

PLL Synthesizer Description Ratiometric Mode

• YCO frequency divided by 4
• Internal register bit (AUXCLK) value

The ICS1562A generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference
frequency may be applied to the ICS1562A from an external
frequency source.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or YCO, to a frequency
that will cause the two inputs to the phase-frequency detector
to be matched in frequency and phase. This occurs when:
F(

. _ F(XTALl)' Feedback Divider
veo). Reference Divider

Load Clock Divider
The ICS1562A has an additional programmable divider (referred to in Figure 1 as the N1 divider) that is used to generate
the LOAD clock frequency for the video DAC. The modulus
of this divider may be setto 3, 4, 5, 6, 8,10,12,16 or 20 under
register control. The design of this divider permits the output
duty factor to be 50/50, even when an odd modulus is selected.
The input frequency to this divider is the output of the PLL
post-scaler described above. Additionally, this divider can be
disabled under register control.

Digital Inputs - ICS1562A-001 Option

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided
to the part (assuming correctly programmed dividers).
The YCO gain is programmable, which permits the ICS1562A
to be optimized for best performance at all operating frequencies.
The reference divider may be programmed for any modulus
from I to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 448 in steps of one. Any even modulus from
448 through 896 can also be achieved by setting the "double"
bit which doubles the feedback divider modulus. The feedback
divider makes use of a dual-modulus prescaler technique that
allows the programmable counters to operate at low speed
without sacrificing resolution. This is an improvement over
conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or larger) in this respect.

The ADO-AD3 pins and the STROBE pin are used to load all
control registers of the ICS1562A (-001 option). The ADOAD3 and STROBE pins are each equipped with a pull-up and
will be at a logic HIGH level when not connected. They may
be driven with standard TTL or CMOS logic families.
The address of the register to be loaded is latched from the
ADO-AD3 pins by a negative edge on the STROBE pin. The
data for that register is latched from the ADO-AD3 pins by a
positive edge on the STROBE pin. See Figure 2 for a timing
diagram. After power-up, the ICS1562A-OOl requires 32 register writes for new programming to become effective. Since
only 13 registers are used at present, the programming system
can perform 19 "dummy" writes to address 13 or 14 to complete the sequence.

Table I permits the derivator of "A" & "M" converter programming directly from desired modulus.

E·32

ICS1562A
ICS1562A-201 Register Loading

This allows the synthesizer to be completely programmed for
the desired frequency before it is made active. Once the part
has been "unlocked" by the 32 writes, programming becomes
effective immediately.
ALL registers identified in the data sheet (0-9, 11, 12 & 15)
MUST be written upon initial programming. The programming registers are not initialized upon power-up, but the
latched outputs of those registers are. The latch is made transparent after 32 register writes. If any register has not been
written, the state upon power-up (random) will become effective. Registers 13 & 14 physically do not exist. Register 10
does exist, but is reserved for future expansion. To insure
compatibility with possible future modifications to the database, ICS recommends that all three unused locations be written with zero.
ICS 1562A-OO 1 Register Loading

STROBE

IEADO·AD3

:::x

1

=G6~3£

ADDRESS VALID

'0

DATA VALID

x=

~
B

DATCLK

~~r

______
DATA~
HOLD

3

r

n

Figure 3
An additional control pin on the ICS1562A-201, BLANK can
perform either of two functions. It may be used to disable the
phase-frequency detector in line-locked applications. Alternatively, the BLANK pin may be used as a synchronous enable
for VRAM shift clock generation. See sections on Line-Locked
Operations and VRAM shift clock generation for details.

Output Description

Figure 2

Digital Inputs - ICS1562A-201 Option
The programming of the ICS1562A-201 is performed serially
by using the DATCLK, DATA, and HOLD-pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD-pin is latched at the
same time. When HOLD- is low, the shift register may be
loaded without disturbing the operation of the ICS1562A.
When high, the shift register outputs are transferred to the
control registers, and the new programming information becomes active. Ordinarily, a high level should be placed on the
HOLD- pin when the last data bit is presented. See Figure 3
for the programming sequence.

The differential output drivers, CLK+ and CLK, are currentmode and are designed to drive resistive terminations in a
complementary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRO
pin. The sink current, which is steered to either CLK+or CLK-,
is four times the current supplied to the IPRG pin. For most
applications, a resistor from VDDO to IPRO will set the current
to the necessary precision. Additionally, minor adjustment to
the duty factor can be achieved under register control.
The LOAD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may
be selected for a modulus of 3,4,5,6,8, 10, 12, 16 or 20. It
may also be suppressed under register control. The load output
may be programmed to output the VCO frequency divided by
2 (see AUX_Nl description in Register Mapping section),
independent of the differential output and Nl divider modulus.
The LDIN2 output is high-current CMOS type drive whose
frequency is derived from the LOAD output. The programmable modulus may range from 1 to 512 in steps of one.

E·33

ICS1562A
Pipeline Delay Reset Function
The ICS1562A implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs when the
LOAD output is programmed for a modulus of either 3, 4, 5,
6, 8 or 10. This sequence can be generated by setting the
appropriate register bit (DACRST) to a logic 1 and then
resetting to logic O.
When changing frequencies, it is advisable to allow 500 microseconds after the new frequency is selected to activate the
reset function. The output frequency of the synthesizer should
be stable enough at that point for the video DAC to correctly
execute its reset sequence. See Figure 4 for a diagram of the
pipeline delay reset sequence.

If an external reference frequency source is to be used with the
ICS1562A, it is important that it be jitter-free. The rising and
falling edges of that signal should be fast and free of noise for
best results.
The loop phase is locked to the falling edges of the XTALl
input signals if the REFPOL bit is set to logic O.

Line-Locked Operation
The ICS1562A supports line-locked clock applications by
allowing the LOAD (Nl) and N2 divider chains to aet as the
feedback divider for the PLL.
The Nl and N2 divider chains allow a much larger modulus to
be achieved than the PLL's own feedback divider. Additionally,
the output of the N2 counter is accessible off-chip for performing horizontal reset of the graphics system, where necessary.
This mode is set under register control (ALTLOOP bit). The
reference divider (R counter) will ordinarily be set to divide by
I in this mode, and the HSYNC signal of the external video
will be supplied to the XTALl input. The output frequency of
the synthesizer will then be:

Pipeline Delay Reset Timing

STROBE

or
DATCLK

ClK+

LOAD

F(CLK) : =F (XTALl)' Nl . N2.

Figure 4

By using the phase-detector hardware disable mode, the PLL
can be made to free-run at the beginning of the vertical interval
of the external video, and can be reactivated at its completion.

Reference Oscillator and Crystal
Selection
The ICS1562A has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.
Series-resonant crystals may also be used with the ICS1562A.
Be aware that the oscillation frequency will be slightly higher
than the frequency that is stamped on the can (typically 0.0250.05%).

ICS1562A-OOl The ICS1562A-OOl supports phase detector
disable via a special control mode. When the
PDRSTEN (phase detector reset enable) bit is
set and the last address latched is IS (OFh), a
high level on AD3 will disable PLL locking.
ICS1562A-201 The ICS1562A-201 supports phase detector
disable via the BLANK pin. When the
PDRSTEN bit is set, a high level on the
BLANK input will disable PLL locking.

As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1562A outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.

E-34

II

ICS1562A

External Feedback Operation

Power-On Initialization

The ICS1562A-201 option also supports the inclusion of an
external counter as the feedback divider of the PLL. This mode
is useful in graphic systems that must be "genlocked" to
external video sources.

The ICS1562A has an internal power-on reset circuit that
performs the following functions:

When the EXTFBEN bit is set to logic I, the phase-frequency
detector will use the EXTFBK pin as its feedback input. The
loop phase will be locked to the rising edges of the signal applied
to the EXTFBK input if the FBKPOL bit is set to logic O.

I)

Sets the multiplexer to pass the reference frequency
to the CLK+ and CLK- outputs.

2)

Selects the modulus of the NI divider (for the
LOAD clock) to be four.

These functions should allow initialization of most graphics
systems that cannot immediately provide for register programming upon system power-up.

VRAM Shift Clock Generation
The ICS1562A-201 option supports VRAM shift clock generation and interruption. By programming the N2 counter to
divide by I, the LDIN2 output becomes a duplicate of the
WAD output. When the SCEN bit is set, the LDIN2 output
may be synchronously started and stopped via the blank pin.
When BLANK is high, the LDIN2 will be free-running and in
phase with LOAD. When BLANK is taken low, the LDIN2
output is stopped at a low level. See Figure 5 for a diagram of
the sequence. Note that this use of the BLANK pin precludes its
use for phase comparator disable (see Line-Locked Operation).

Because the power-on reset circuit is on the VDD supply, and
because that supply is filtered, care must be taken to allow the
reset to de-assert before programming. A safe guideline is to
allow 20 microseconds after the VDD supply reaches 4 volts.

Programming Notes
•

VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.

•

Divider Range: For best results in normal situations (i.e,
pixel clock generation for hi-res displays), keep the reference divider modulus as short as possible (for a frequency
at the output of the reference divider in the few hundred
kHz to several MHz range). If you need to go to a lower
phase comparator reference frequency (usually required
for increased frequency accuracy), that is acceptable, but
jitter performance will suffer somewhat.

•

VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as shown
on the following page:

VRAM Shift Clock Control

FigureS

E-35

II

ICS1562A
VCOGAIN
4
5
6

MAX FREQUENCY
120 MHz
200 MHz
260 MHz

7

*

Power Supplies and Decoupling
The ICS1562A has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as close
to the package as is possible.

'SPECIAL APPLICATION. Contact factory for custom product above
260 MHz.

•

Phase Detector Gain: For most graphics applications and
divider ranges, set P[1, 0] = 10 and set P[2] = 1. Under
some circumstances, setting the P[2] bit "on" can reduce
jitter. During 1562 operation at exact multiples of the
crystal frequency, P[2] bit =0 may provide the best jitter
performance.

Board Test Support
It is often desirable to statically control the levels of the output
pins for circuit board test. The ICS1562A supports this through
a register programmable mode, AUXEN. When this mode is
set, two register bits directly control the logic levels of the
CLK+/CLK- pins and the LOAD pin. This mode is activated
when the S[O] and S[l] bits are both set to logic 1. See Register
Mapping for details.

The ICS1562A has a VDDO pin which is the supply of +5 volt
power to all output drivers. This pin should be connected to the
power plane (or bus) using standard high-frequency decoupiing practice. That is, capacitors should have low series inductance and be mounted close to the ICS1562A.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for
this pin (as shown in the recommended application circuitry).
This will allow the PLL to "track" through power supply
fluctuations without visible effects. See Figure 6 for typical
external circuitry.

DIFFERENTIAL CLOCK OUTPUT SINK CURRENT

;40r-----------~======~====~~~~

':'35

...z 30

......

~ 25

330

a 20
'"~
:!:

510
-e680

15

........

10 ...

-'
u

1.5 K

-:;:- 5

d o~--~--~--~--~--~--~--~__4
o 0.5 1 1.5 2 2.5 3 3.5 4
CLK+/CLK- OUTPUT VOLTAGE (Volts)

Figure 6

E·36

II

ICS1562A

a)

M"~"

ICS1562A.(J01 Typical Interface

j
+SV

SV

SELECT LOGIC

82

82

10

}
+5V
510

o llJF

TO
RAMDAC

820

820

J;:

b)
ICS1562A-201 Typical Interface

GRAPHICS
{
CONTROllER

II±,
~~ Tr
o llJF

PROGRAMMING {
INTERFACE

-

r-"D

=±

+~

EXTFBK
XTALl
XTAl2
DATCLK
VSS
VSS
LOAD
lDIN2

11

BLANK
VDD
VDOO
IPRG
ClKCLK+

+sy

"

~OlI1F

V
10

82

82

I

~

+5V
510

}

820

<

820

011JF -~

~

Figure 7

E-37

-+

,

TO
RAMDAC

II

II

ICS1562A
Register Mapping -ICS1562A-001 (Parallel Programming Option)

NOTE: IT IS NOT NECESSARY TO UNDERSTAND TIlE FUNCTION OF TIlESE BITS TO USE TIlE ICS1562A. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.

BIT(S)

o

BIT REF.

DESCRIPTION

0-3
0-2

R[O] .. R[3]
R[4] .. R[6]

Reference divider modulus control bits
Modulus = value + 1

3

REFPOL

PLL locks to the rising edge of XTALI input when REFPOL=1 and
to the falling edge ofXTALl when REFPOL=O.

2

0-3

A[0] .. A[3]

Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for "value" underflows of the prescaler, and modulus=6
thereafter until M counter underflows.

3
4

0-3
0-1

M[0] .. M[3]
M[4] .. M[5]

M counter control bits
Modulus = value + 1

4

2

FBKPOL

External feedback polarity control bit The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of
EXTFBK when FBKPOL=O.

4

3

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 6n to 12114).

5

0-3

Nl[0] .. Nl[3]

Sets Nl modulus according to this table. These bits are set to implement a divide-by-four on power-up.

1

NI[3]
0
0
0
0
0
0
0
0
1
1
1
1
X=Don't Care

E-38

NI[2]
0
0
0
0
1
1
1
1
X
X
X
X

NI[I]
0
0
1
1
0
0
1
1
0
0
1
1

Nl[O]
0
1
0
1
0
1
0
1
0
1
0
1

RATIO
3
4
4
5
6

8
8
10
12
16
16
20

II

ICS1562A

REG#

BIT(S)

6
7

0-3
0-3

N2[0]..N2[3]
N2[4]..N2[7]

8

3

N2[8]

8

0-2

V[O] .. V[I]

9

0-1

DESCRIPTION

BIT REF.

P[O] ..P[I]

Sets the modulus of the N2 divider.
The input of the N2 divider is the output of the Nl divider in all clock
modes except AUXEN.

Sets the gain of the VCO.
V[2]

V[I]

V[O]

I
1
1
1

0
0
1
1

0
1
0
1

Sets the gain of the phase detector according to this table.

P[I]
0
0
I
I

9

3

10

VCOGAIN
(MHzlVOLT)
30
45
60
80

prO]
0
I

GAIN (uNradian)
0.05
0.15
0.5
1.5

0
1

[P2]

Phase detector tuning bit. Normally should be set to one.

LOADEN-

Load clock divider enable (active low). When set to logic I, the
LOAD and LDIN2 outputs will cease toggling.
Differential output duty factor adjust.

10

2

SKEW-

10

3

SKEW+

SKEW+
0
0

SKEW0
1

Default
Reduces TmGH by approximately

I

0

I

I

Increases TmGH by approximately
lOOps
Do not use

100~s

E·39

II

ICS1562A

11

0-1

BIT REF

DESCRIPTION

S[O] .. S[I]

PLL post-scaler/test mode select bits
S[I] S[O]
DESCRIPTION
0 Post-scaler= 1. F(CLK)=F(PLL). The output of the Nl divider
0
drives the LOAD output which, in turn drives the N2 divider.
0
1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the Nl divider
drives the LOAD output which in turn, drives the N2 divider.
1
0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the Nl divider
drives the LOAD output which, in turn, drives the N2 divider.
1
1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXNl bit drives the LOAD
output which, in turn, drives the N2 divider.

11

2

AUX_CLK

When in the AUXEN clock mode, this bit controls the differential
outputs.

11

3

AUX_Nl

When in the AUXEN clock mode, this bit controls the LOAD output
(and consequently the N2 output according to its programming).
When not in the AUXEN clock mode, this bit, if set to one, will override the Nl divider modulus and output the VCO frequency divided
by two [F(PLL)/2] at the LOAD output.

12

0

RESERVED

Must be set to zero.

JAMPLL

Tristates phase detector outputs; resets phase detector logic, and
resets R, A, M, and N2 counters.

12
12

2

DACRST

Set to zero for nonnal operation. When set to one, the CLK+output
is kept high and the CLK- output is kept low. (All other device functions are unaffected.) When returned to zero, the CLK+ and CLKoutputs will resume toggling on a rising edge of the LD output
(+/- 1 CLK period). To initiate a RAMDAC reset sequence,
simply write a one to this register bit followed by a zero.

12

3

SELXTAL

When set to logic 1, passes the reference frequency to the post-scaler.

15

0

ALTLOOP

Controls substitution of Nl and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the Nl and N2 dividers are used.

15

3

PDRSTEN

Phase-detector reset enable control bit. When this bit is set, the AD3
pin becomes a transparent reset input to the phase detector.
See LINE-LOCKED CLOCK GENERATION section for more
details on the operation of this function.

E-40

II

ICS1562A

Register Mapping - ICS1562A-201 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS 1562A. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS

BIT(S)

BIT REF.

1-4

NI[0] .. NI[3]

DESCRIPTION
Sets NI modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
NI[3]

NI[2]

NI[I]

NI[O]

0
0
0
0
0
0
0
0
I
I
I
I

0
0
0
0
I
I
I
I
X
X
X
X

0
0
I
I
0

0
I
0
I
0
I
0
I

-

0
I
I
0
0
I
I

0
I
0
I

RATIO
3
--4
4
5
6
8
8
10
12
16
16
20

5

RESERVED

Must be set to zero.

6

JAMPLL

Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.

7

DACRST

Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/-1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.

8

SELXTAL

When set to logic 1, passes the reference frequency to the post-scaler.

9

ALTLOOP

Controls substitution of NI and N2 dividers into feedback loop of PLL.
When this bit is a logic I, the NI and N2 dividers are used.

10

SCEN

VRAM shift clock enable bit. When logic I, the BLANK pin can be used
to disable the LDIN2 output.

11

EXTFBKEN

External PLL feedback select. When logic I, the EXTFBK pin is used for
the phase-frequency detector feedback input.

12

PDRSTEN

Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See LINE-LOCKED
CLOCK GENERATION section for more details on the operation of
this function.

E-41

ICS1562A
BIT(S)

BIT REF.

13-14

S[O) .. S[ll

DESCRIPTION
PLL post-scaler/test mode select bits.
DESCRIPTION
Sell S[O)
0
0 Post -scaler= 1. F(CLK)=F(PLL). The output of the Nl divider
drives the LOAD oU!put which, in tum, drives the N2 divider.
0
1 Post -scaler=2. F(CLK)=F(PLL)l2. The output of the Nl divider
drives the LOAD outrmt which, in tum, drives the N2 divider.
0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the Nl divder
1
drives the LOAD output which, in tum, drives the N2 divider.
1
1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXNl bit drives the LOAD
output which, in turn, drives the N2 divider.

15

When in the AUXEN clock mode, this bit controls the differential outputs.

16

When in the AUXEN clock mode, this bit controls the Nl output (and
consequently the N2 output according to its programming). When not in
the AUXEN clock mode, this bit, if set to one, will override the Nl divider
modulus and output the VCO frequency divided by two [F(PLL)/2) at the
LOAD output.

17-24
28

N2(0) .. N2[7)
N2(8)

25-27

V(0)..Y[2)

29-30

P[O) .. P[1)

} Sets the modulus of the N2 divider. The input of the N2 divider is the
output of the Nl divider in all clock modes except AUXEN.
Sets the gain of VCO according to this table.

V(2)

V[l)

V[O)

VCOGAIN
(MHzIVOLT)

1
1
1
1

0
0
1
1

0
1
0
1

30
45
60
80

Sets the gain of the phase detector according to this table.
prO)

P[I)
0
0
1
1

0
1
0
1

GAIN (uAiradian)
0.05
0.15
0.5
1.5

31

RESERVED

Set to zero.

32

P(2)

Phase detector tuning bit. Should normally be set to one.

E-42

II

ICS1562A

BIT(S)

BIT REF.

33-38

M[0] .. M[5]

M counter control bits
Modulus = value + 1

39

FBKPOL

External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of EXTFBK
when FBKPOL=O.

40

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 617 to 12/14).

41-44

A[0] .. A[3]

Controls A counter. When set to zero, modulus= 7. Otherwise,
modulus=7 for "value" underflows ofthe prescaler, and modulus=6
thereafter until M counter underflows.

45

RESERVED

Set to zero.

46

LOADEN-

Load clock divider enable (active low). When set to logic 1, the LOAD
and LDIN2 outputs will cease toggling.

47
48

SKEWSKEW+

Differential output duty factor adjust.

DESCRIPTION

SKEW+
0
0

SKEW-

1

0

1

1

0
1

Default
Reduces THIGH by approximately
100 ps
Increases THIGH by approximately
lOOps
Do not use

49-55

R[0] .. R[6]

Reference divider modulus control bits
Modulus = value + 1

56

REFPOL

PLL locks to the rising edge of XTALl input when REFPOL= 1 and to
the falling edge of XTALl when REFPOL=O.

E-43

II

ICS1562A
Table 1 • "A" & "M" Divider Programming
Feedback Divider Modulus Table
A[2j ••A[Oj·
M[5j .. M[Oj
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111

001

13
19
25
31
37
43
49
55
61
67
73
79
85
91
97
103
109
115
121
127
133
139
145
151
157
163
169
175
181
187
193

010

20
26
32
38
44
50
56
62
68
74
80
86
92
98
104
110
116
122
128
134
140
146
152
158
164
170
176
182
188
194

011

27
33
39
45
51
57
63
69
75
81
87
93
99
105
111
117
123
129
135
141
147
153
159
165
171
177
183
189
195

100

34
40
46
52
58
64
70
76
82
88
94
100
106
112
118
124
130
136
142
148
154
160
166
172
178
184
190
196

101

41
47
53
59
65
71
77
83
89
95
101
107
113
119
125
131
137
143
149
155
161
167
173
179
185
191
197

110

48
54

60
66
72
78
84
90
96
102
108
114
120
126
132
138
144
150
156
162
168
174
180
186
192
198

111

55
61
67
73
79
85
91
97
103
109
115
121
127
133
139
145
151
157
163
169
175
181
187
193
199

A[2j ••A[Oj-

000

M[5J .. M[Oj
100000
100001
100010
100011
100100
100101

7
14
21
28
35
42
49
56
63
70
77
84
91
98
105
112
119
126
133
140
147
154
161
168
175
182
189
196
203
210
217
224

100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
IlOilO
110111
111000
lllOOI
111010
111011
111100
Illl01
111110
111111

001

010

011

100

101

110

111

000

199
205
211
217

200
206
212
218
224
230
236
242
248
254
260
266
272
278
284
290
296
302

201
207
213
219

202
208
214
220
226
232

237
243
249
255
261
267
273
279
285
291
297
303

238
244
250
256
262
268
274
280

204
210
216
222
228
234
240
246
252
258
264
270

205
211
217
223
229
235
241
247
253
259
265
271

231
238
245
252

225
231

203
209
215
221
227
233
239
245
251
257

308
314

309
315
321
327
333
339
345
351
357
363
369
375
381
387

310
316
322

276
282
288
294
300
306
312
318
324
330
336
342
348
354
360

277
283
289
295
301
307
313
319
325
331
337
343
349
355
361
367
373
379
385
391

223
229
235
241
247
253
259
265
271
277
283
289
295
301
307
313
319
325
331
337
343
349
355
361
367
373
379
385

320
326
332
338
344
350
356
362
368
374
380
386

286
292
298
304

328
334
340
346
352
358
364
370
376
382
388

263
269
275
281
287
293
299
305
311
317
323
329
335
341
347
353
359
365
371
377
383
389

366
372
378
384
390

Notes:
To use this tabje. find the desired modulus in the table. Follow the column up to find the A divider programming values.
Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three
combinations of divider settings. Any are acceptable for use.
The formula for the effective feedback modulus is:

N =[(M +1)·6] +A

except when A=O, then:

N=(M+l)' 7

Under all circumstances:

A5:M

E·44

259
266
273
280
287
294
301
308
315
322
329
336
343
350
357
364
371
378
385
392
399
406
413
420
427
434
441
448

ICS1562A
Pin Descriptions - ICS1562A-001
PIN#

NAME

10

CLK+

Clock out (non-inverted)

9

CLK-

7

LOAD
XTALl
XTAL2
ADO
ADI
AD2
AD3
LDIN2
STROBE
VDD
VDDO
IPRG
VSS

Clock out (inverted)
Load output. This output is normally at the CLK frequency divided by Nl.
Quartz crystal connection lIexternal reference frequency input
Quartz crystal connection 2
AddresslData Bit 0 (LSB)
AddresslData Bit 1
AddresslData Bit 2
AddresslData Bit 3 (MSB)

2
3
1
16
15
14
8
4
13
12
11
5,6

DESCRIPTION

Divided LOAD output. See text.
Control for address/data latch
PLL system power (+5Y. See application diagram.)
Output stage power (+5V)
Output stage current set
Device ground. Both pins must be connected to the same ground potential.

Pin Descriptions - ICS1562A-201
PIN#

DESCRIPTION

NAME

10

CLK+

Clock out (non-inverted)

9
7
2
3
4
16
15
14
8

CLK-

Clock out (inverted)

LOAD
XTALl
XTAL2
DATCLK
DATA
HOLDBLANK
LDIN2
EXTFBK
VDD
VDDO
IPRG
VSS

Load output. This output is normally at the CLK frequency divided by Nl.
Quartz crystal connection l/external reference frequency input
Quartz crystal connection 2
Data Clock (Input)
Serial Register Data (Input)
HOLD (Input)
Blanking (Input). See Text.
Divided LOAD output/shift clock. See text.
External feedback connection for PLL (input), See text.
PLL system power (+5Y. See application diagram.)
Output stage power (+5V)
Output stage current set
Device ground. Both pins must be connected.

13
12

11
5,6

E·45

II

ICS1562A
Absolute Maximum Ratings
VDD, VDDO (measured to V ss). . . . . . . . . . . . . . . . . . . . . ..
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Digital Outputs .....................................
Ambient Operating Temperature .......................
Storage Temperature ................................
Junction Temperature ................................
Soldering Temperature ...............................

7.0 V
V ss-0.5 to VDD + 0.5 V
Vss-0.5 to VDDO + +0.5 V
-55 to 125°C
-65 to 150°C
175°C
260°C

Recommended Operating Conditions
VDD, VDDO (measured to Vss) ....................... 4.75 to 5.25 V
Operating Temperature (Ambient) . . . . . . . . . . . . . . . . . . . .. 0 to 70°C

DC Characteristics
TTL-Compatible Inputs
001 Option - (ADO-AD3, STRO~
201 Option - (DATClK, DATA, HOLD, BLANK, EXTFBK)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
Hysteresis (STROBEIDATCLK)

SYMBOL

CONDITIONS

Vih
Vii
lih
Iii

Vss-O.5

MAX
VDD+0.5
0.8

UNITS
V
V
uA
uA
pf

Vih=VDD
ViI=O.O

-

VDD=5V

.20

200
8
.60

MIN
3.75
Vss-0.5

MAX
VDD+0.5
1.25

UNITS
V

MIN
2.4

MAX

-

0.4

UNITS
V
V

Cn
Vhys

MIN
2.0

10

V

XTAL11nput
PARAMETER
Input High Voltage
Input Low Voltage

SYMBOL

CONDITIONS

Vxh
Vxl

ClK+, ClK- Outputs
PARAMETER
Differential Output Voltage

CONDITIONS

lOAD, lD/N2 Outputs
PARAMETER
Output High Voltage (Ioh = 4.0mA)
Output Low Voltage (101 = 8.0mA)

SYMBOL

CONDITIONS

E-46

-

ICS1562A
AC Characteristics
SYMBOL
Fvco

PARAMETER
VCO Frequency (see Note 1)

MIN
40

Fxtal
Cpar

Crystal Frequency
Crystal Oscillator Loading Capacitance

Fload
Txlu
TxIo

LOAD Frequency
XTALl High Time (when driven externally)
XTALl Low Time (when driven externally)

Tiock

PLL Acquire Time (to within 1%)

TYP

5

MAX
260

UNITS

20

MHz
pf

80

MHz

20
8
8

MHz

ns
ns
500

Idd

VDD Supply Current

15

t.b.d.

I1s
rnA

Iddo

VDDO Supply Current (excluding CLK+/tennination)
Differential Clock Output Duty Cycle
45
(see Note 2)
Differential Clock Output Cumulative Jitter
(see Note 3)
DIGITAL INPUTS - ICSI 562A-00I
10
Address Setup Time

20

t.b.d.

rnA

55

%

Thigh
Jclk

1
2

Address Hold Time

10

3
4

Data Setup Time
Data Hold Time

10

5

10
STROBE Pulse Width (Thi or TIo)
20
DIGITAL INPUTS - ICS 1562A-201

6

DATAlHOLD- Setup Time

7

DATAlHOLD- Hold Time

8

DATCLK Pulse Width (Thi or TIo)

<0.06

pixel

ns
ns
ns
ns
ns

10
10

ns
ns

20

ns

PIPELINE DELAY RESET

9

Reset Activation Time

10
11

Reset Duration
Restart Delay

12

Restart Matching

2*Tclk
4*Tload
-I *Tclk

ns
ns
ns

2*Tload
+ 1.5 *Tclk

ns

260

MHz

+2

ns

DIGITAL OUTPUTS
13
14

CLK+/CLK- Clock Rate
LOAD To LDIN2 Skew (Shift Clock Mode)

-2

0

Note 1: Use of the post-divideris required for frequencies lower than 40 MHz on CLK+ & CLK- outputs. Use of the post-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the domain) if any CLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.

E-47

II

ICS1562A
Ordering Information
ICS1562AM-001 or ICS1562AM-201
Example:

ICS XXXX M -XXX

T1,-__

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC

' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - Prefix
ICS, AV=Standard DevIce; GSP=Genlock DevIce

E-48

II

ICS1562A Application Information

Output Circuit Considerations for the ICS1562A
Output Circuitry
The dot clock signals CLK and CLK- are typically the highest
frequency signals present in the workstation. To minimize
problems with EMI, crosstalk, and capacitive loading extra
care should be taken in laying out this area of the PC board.
The ICS1562A is packaged in a 0.2"-wide l6-pin SOlC package. This permits the clock generator, crystal, and related
components to be laid out in an area the size of a postage stamp.
The ICS1562A should be placed as close as possible to the
RAMDAC. The CLK and CLK- pins are running at VHF
frequencies; one should minimize the length of PCB trace
connecting them to the RAMDAC so that they don't become
radiators of RF energy.

Stripline is the other form a PCB transmission line can take. A
buried trace between ground planes (or between a power plane
and a ground plane) is common in multi-layer boards. Attempting to create a workstation design without the use of
multi-layer boards would be adventurous to say the least, the
issue would more likely be whether to place the interconnect
on the surface or between layers. The between layer approach
would work better from an EMI standpoint, but would be more
difficult to layout. A stripline is shown below:

At the frequencies that the ICS1562A is capable of, PC board
traces may be long enough to be a significant portion of a
wavelength of that frequency. PC traces for CLK and CLKshould be treated as transmission lines, not just interconnecting
wires. These lines can take two forms: microstrip and stripline.
A microstrip line is shown below:

Zo=

Kin (0.067,,':(0.8 +~»)
Dimensions In Inches

Stripline
Using I oz. copper (0.0015" thick) and 0.040" thickness G 10,
a 0.010" trace will exhibit a characteristic impedance of75Q
in a stripline configuration.

87

Typically, RAMDACs require a Vih of VAA-1.0 Volts as a
guaranteed logical "I" and a Vii of VAA-l.6 as a guaranteed
logical "0." Worst case input capacitance is 10 pf.

(5.98h)

Zo=Ye r +l.41 In O.8w+t

Dimensions In Inches

Microstrip Line
Essentially, the microstrip is a copper trace on a PCB over a
ground plane. Typically, the dielectric is G 10 glass epoxy. It
differs from a standard PCB trace in that its width is calculated
to have a characteristic impedance. To calculate the characteristic impedance of a microstrip line one must know the width
and thickness of the trace, and the thickness and dielectric
constant of the dielectric. For G 10 glass epoxy, the dielectric
constant (er) is about 5. Propagation delay is strictly a function
of dielectric constant. For G 10 propagation, delay is calculated to be l. 77 ns/ft.

Output circuitry for the ICS1562A is shown in the following
diagram. It consists of a 4/1 current mirror, and two open drain
output FETs along with inverting buffers to alternately enable
each current-sinking driver. Both CLK and CLK- outputs are
connected to the respective CLOCK and CLOCK inputs of the
RAMDAC with transmission lines and terminated in their
equivalent impedances by the Thevenin equivalent impedances
ofRI and R2 or RI' and R2'.

E-49

ICS1562A Application Information

The ICS1562A is incapable of sourcing current, so Vih must
be set by the ratios of these resistors for each of these lines. RI
and R2 are electrically in parallel from an AC standpoint
because Vdd is bypassed to ground through bypass-capacitor
network Cb. If we picked a target impedance of 750. for our
transmission line impedance, a value of 910. for RI and RI'
and a value of 4300. for R2 and R2' would yield a Thevinin
equivalent characteristic impedance of 75.10. and a Vih value
of VAA-.873 Volts, a margin of 0.127 Volts. This may be
adequate; however, at higher frequencies one must contend
with the 10 pf input capacitance of the RAMDAC. Values of
820. for RI and RI' and 8200. for R2 and R2' would give us a
characteristic impedance of74.50. and a Vih value of V AA-.45.
With a .55 Volt margin on V ih, this voltage level might be safer.

Cb is shown as multiple capacitors. Typically, a 2211f tantalum
should be used with separate .1 JlF and 220pf capacitors placed
as close to the pins as possible. This provides low series
inductance capacitors right at the source of high frequency
energy. Rd is used to isolate the circuitry from external
sources of noise. Five to ten ohms should be adequate.

....

"- - - - - - - . ,

At

r--:::::-"""".,---+---+--l

ClockClock

To set a value for Vii, we must determine a value for Iprg that
will cause the output PET's to sink an appropriate current. We
desire Vii to be V AA-1.6 or greater. VAA-2 would seem to be a
safe value. Setting up a sink current of 25 milliamperes would
guarantee this through our 820. pull-up resistors. As this is
controlled by a 4/1 current mirror, 7 rnA into Iprg should set this
current properly. A5too. resistor from V dd to Iprg should work
fine.

ICS1562A Output Circuitry

Resistors Rt and Rt' are shown as series terminating resistors
at the ICSlS62A end of the transmission lines. These are not
required for operation, but may be useful for meeting EM!
requirements. Their intent is to interact with the input capacitance of the RAMDAC and the distributed capacitance of the
transmission line to soften up rise and fall times and consequently cut some of the high-order harmonic content that is
more likely to radiate RF energy. In actual usage they would
most likely be 10 to 200. resistors or possibly ferrite beads.

Great care must be used when evaluating high frequency
circuits to achieve meaningful results. The 10 pf input capacitance and long ground lead of an ordinary scope probe will
make any measurements made with it meaningless. A low
capacitance PET probe with a ground connection directly connected to the shield at the tip will be required. A lGHz bandwidth scope will be barely adequate, try to find a faster unit.

..

E-SO

...

RAM>AC

ICS1567

Integrated
Circuit
Systems, Inc.

•

Differential Output Video Dot Clock Generator
General Description

Features

The ICS1567 is a very high performance monolithic PLL
frequency synthesizer. Utilizing ICS's advanced CMOS
mixed-mode technology, the ICS1567 provides a low cost
solution for high-end video clock generation, and for telecom
system clock generation.

•

The ICS1567 has differential video clock outputs (CLK and
CLK) that are compatible with industry standard video DACs
& RAMDACs. An additional clock output, LD, is provided,
whose frequency is divided down from the main clock by a
programmable divider.
Operating frequencies are selectable from a pre-programmed
(customer-defined) table. An on-chip crystal oscillator for
generating the reference frequency is provided on the
ICS1567.
Programming of the ICS1567 is accomplished via frequency
select pins on the package. The ICS1567 has five lines plus a
STROBE pin which permits selection of32 frequencies. Reset
of the pipeline delay on Brooktree RAMDACs is automatically
performed on a rising edge of the STROBE line.

Applications
•
•
•
•
•

•

•
•

•
•

•

•
•

High frequency operation for extended video modes - up
to 180 MHz
Compatible with Brooktree high performance RAMDACs
a) Differential output clocks with ECL logic levels
b) Programmable divider modulus for load clock
c) Circuitry included for automatic reset of Brooktree
RAMDAC pipeline delay
Low cost - eliminates need for multiple ECL crystal clock
oscillators in video display systems
Strobedffransparent frequency select options
32-user selected mask-programmable frequencies
Fast acquisition of selected frequencies, strobed or nonstrobed
Advanced PLL for low phase-jitter
Dynamic control of VCO sensitivity providing optimized
loop gain over entire frequency range
Small footprint - 16-pin wide body (300 mil) SOIC

Pin Configuration

Workstations
High-resolution PC and MAC displays
8514A - TMS340XO systems
EGA - VGA - Super VGA video
Telecom reference clock generation - suitable for Sonet,
ATM and other data rates up to 155.52Mb.

FSO
XTAl1
XTAL2
STROBE
VSS
VSS
lD
FS4

1
2
3
4

II)

5

(/)

6
7

8

,...
CD

.,....

~

16
15
14
13
12
11
10
9

16-Pin sOle
K-6

IICS1587RevB09Q894

E·51

FS1
FS2
FS3
VDD
VDDO
VDDO
ClK
ClK

ICS1567
Block Diagram
X1
X2

ClK+
ClK-

FSO
FS1
FS2
FS3
FS4

lOAD

STROBE

Figure 1

System Schematic

FSO

1

XTAlr1D~

STROBE
Vss

4
5
6
7
8

lOAD
FS4

ICS1567

16
15
14
13
12

FS1
FS2
FS3
p.

Voo

10

r.!!10
9

~-~+
--

Figure 2

E·52

Vooo

ClK
ClK

II

ICS1567

Typical Output Configuration
+5VoHs

r D1

.-

110

ICSl567
47
CLK+ WJJ..,

RAMDAC

[:

Oock
160
110

47

CLK- WJJ..,

Oock
-

---

Load

160

LD

Notes:
CLK & CLK outputs are pseudo-ECL. Logic low level is set by the ratio of the resistors stacked across the power supply
VLO =(V supply. 160)/(110 +160) in the example shown above.
The above values are a good starting point for RAMDAC or clock generator interface.

Figure 3
Pin Description
PIN NUMBER
1
2

3

4
5
6
7
8
9
10

II

12
13

14
15
16

PIN SYMBOL
• FSO
XTALI
XTAL2
• STROBE
VSS
VSS
LD
• FS4
CLK
CLK
VDDO
VDDO
VDD
• FS3
• FS2
• FSI

TYPE

IN
IN
OUT
IN
--

-OUT
IN
OUT
OUT
---

-IN
IN
IN

DESCRIPTION
Frequency Select LSB
Crystal InterfacelExternal Oscillator Input
Crystal Interface
Control For Frequency Select Latch, also performs automatic
RAMDAC reset
Device Ground (Both~ns must be connected.).
Device Ground (Both~ns must be connected.)
Load Output. This outRut is at CLK frequency divided by Nl.
Frequency Select MSB
Clock Output Inverted
Clock Output Non-Inverted
Output Stage Power (Both pins must be connected)
Output Stage Power (Both pins must be connected)
PLL System Power
Frequency Select
Frequency Select
Frequency Select

• =inputs with internal pull-up resistor

E-53

II

ICS1567
Circuit Description

Frequency Synthesizer Description

Overview

Refer to Figure 1 for a block diagram of the ICS1567. The
reference frequency is generated by an on-chip crystal oscillator, or the reference frequency may be applied to the ICS1567
from an external frequency source.

The ICS1567 is designed to provide the graphics system clock
signals required by industry standard RAMDACs. One of 32
pre-programmed (user-definable) frequencies may be selected
under digital control. Fully programmable feedback and reference divider capability allow virtually any frequency to be
generated, not just simple multiples of the reference frequenc~.
The ICS1567 uses the latest generation of frequency synthesIs
techniques developed by ICS and is completely suitable for the
most demanding video applications.

Digital Inputs
The FSO-FS4 pins and the STROBE pin are used to select the
desired operating frequency from the 32 pre-programmed fr~­
quencies in the ROM table of the ICS1567. The STROBE pm
also controls activation of the pipeline delay RESET function
included in the ICS1567 (see PIPELINE DELAY RESET
section for details). The FSO-FS4 and STROBE pins are each
equipped with a pull-up and will be at a logic HIGH level when
not connected.
Transparent Mode - When the STROBE pin is h.eld HIG~,
the FSO through FS4 inputs are transparent; that IS, they directly access the ROM table. The synthesizer will output the
frequency programmed into the location addressed by the
FSO-FS4 pins.
Latched Mode - When the STROBE pin is held LOW, the
FSO-FS4 pins are ignored. The synthesizer will o~tput the
frequency corresponding to the state of the FSO-FS4 pms when
the STROBE pin was last HIGH. In the event that the ICS1567
is powered-up with the STROBE pin held .LOW, the syn~e­
sizer will output the frequency programmed mto address 0 (I.e.,
the one selected with FSO through FS4 at a logic LOW level).

The ICS1567 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL. The phase-frequency detector shown in the
block diagram drives the VCO to a frequency that will cause
the two inputs to the phase-frequency detector to be matched
in frequency and phase. This occurs when:

F(vco) =

F(XTALl). Feedback Divider
Reference Divider

This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequ~n.cy provided
to the part (assuming correctly-programmed divIders). The
divider programming is one of the functions perform~d .by the
ROM look-up table in the ICS1567. The VCO gam IS als~
ROM programmable which permits the ICS1567 to be OptImized for best performance at each frequency in the table.
The feedback divider makes use of a dual-modulus prescaler
technique that allows construction of a programmable counter
to operate at high speeds while still allowing the feedback
divider to be programmed in steps of 1. This is an improvement
over conventional fixed prescaler architectures that typically
impose a factor-of-four penalty (or larger) in this respect.
A post-divider may be inserted between the VCO and the CLK
and CLK outputs of the ICS1567. This is useful in generation
of lower frequencies, as the VCO has been optimized for
high-frequency operation. Different post-divider settings may
be used for each frequency in the table.

E·54

ICS1567
Application Information

Load Clock Divider
The ICS1567 has an additional programmable divider that is
used to generate the LOAD frequency. The modulus of this
divider may be set to 3, 4, 5, 6, 8, or 10. The design of this
divider permits the output duty factor to be 50/50, even when
an odd modulus is selected.
The selection of the modulus is done by the ROM look-up
table. A different modulus may, therefore, be selected for each
frequency address.

Pipeline Delay Reset Function
The ICS1567 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This sequence is automatically generated by the ICS1567 upon any
rising edge of the STROBE line.
When the frequency select inputs (FSO-FS4) are used in a
transparent mode, simply lower and raise the STROBE line to
activate the function. When the frequency select inputs are
latched, simply load the same frequency into the ICS1567
twice.
When changing frequencies, it is advisable to allow 500uSec
after the new frequency is selected to activate the reset function. The output frequency of the synthesizer should be stable
enough at that point for the RAMDAC to correctly execute its
reset sequence.
See Figure 4 for a diagram of the clock sequencing.

Output Stage Description

Power Supplies
The ICS1567 has two VSS pins to reduce the effects of package
inductance. Both pins are connected to the same potential on
the die (the ground bus). BOTH of these pins should connect
to the ground plane of the video board as close to the package
as is possible.
The ICS1567 has two VDDO pins which are the supply of +5
volt power to all output stages. Again, both VDDO pins connect
to the same point on the die. BOTH of these pins should be
connected to the power plane (or bus) using standard high-frequency decoupling practice. This decoupling consists of a low
series inductance bypass capacitor, using the shortest leads
possible, mounted close to the ICS1567.
The VDD pin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend that
RC decoupling or zener regulation be provided for this pin (as
shown in the recommended application circuitry). This will
allow the PLL to "track" through power supply fluctuations
without visible effects.

Crystal Oscillator and Crystal Selection
The ICS1567 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.

The CLK and CLK outputs are each connected to the drains of
P-Channel MOSFET devices. The source of each of these
devices is connected to VDDO. Typical on resistance of each
device is 15 Ohms. These outputs will drive the clock and clock
of a RAMDAC device when a resistive network equivalent to
Figure 3 is utilized.

So-called series-resonant crystals may also be used with the
ICS1567. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the can
(typically 0.005-0.01 %).

The LD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may
be selected for a modulus of 3, 4, 5, 6, 8, or 10. Under control
of the ROM, this output may also be suppressed (logic low
level) at any frequency select address, if desired.

As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1567 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.

E-55

II

ICS1567
Application Notes (continued)

ICS1567 Interface

Bus Clock Interface

The ICS1567 should be located as close as possible to the video
DAC or RAMDAC. Figure 3 illustrates interfacing the
ICS1567 to a RAMDAC. The differential output CLOCK
drivers are current sourcing only and are designed to drive
resistive terminations in a complementary fashion CLK and
CLK connections should follow good ECL interconnection
practice. Tenninating resistors should be as close as possible to
theRAMDAC.

In some applications, it may be desirable to utilize the bus
clock. To do this, connect the clock through a .047uF capacitor
to XTALI (2) and keep the lead length of the capacitor to
XTALl (2) to a minimum to reduce noise susceptibility. This
input is internally biased at VDD/2. Since TTL compatible
clocks typically exhibit a VOH of 3.5V, capacitively coupling
the input restores noise immunity. The ICS1567 is not sensitive
to the duty cycle of the bus clock; however, the quality of this
signal varies considerably with different motherboard designs.
As the quality of the bus clock is typically outside the control
of the graphics adapter card manufacturer, it is suggested that
this signal be buffered on the graphics adapter board. XTAL2
(3) must be left open in this configuration.

Absolute Maximum Ratings
Ambient Temeperature under bias .....
Supply Voltage ....................
Input Voltage ......................
Output Voltage .....................
Clamp Diode Current ................
Output Current per Pin. . . . . . . . . . . . . ..
Storage Temperature ................
Power Dissipation ..................

To .............
Voo ...........
VIN ............
VOUT ..........
VIK & 10K. . . . ..
lOUT...........
Ts .............

O°C to 70°C
-O.5Vto+7V
-O.5V to Voo + O.5V
-O.5V to Voo + O.5V
±30mA
±50mA
-85°C to + 150°C
Po ............. 500mW

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that nonnal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that VIN and VOUT be
constrained to > = Vss and < = Voo.

Standard Test Conditions
The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced
to VSS (OV Ground). Positive current flows into the referenced pin.

4.75 to 5.25 Volts

E·56

II

ICS1567

DC Characteristics
SYMBOL

MIN

MAX

UNITS

Input High Voltage

VIH

2.0

VDD+0.5

V

Input Low Voltage

VIL

Vss -0.5

0.8

V

Input High Current

IIH

10

uA

VIN = VDD

Input Low Current

lIL

-200

uA

VIN= Vss

PARAMETER

CONDITIONS

LOADOUTPUf
Output High Voltage

VOH

2.4

Output Low Voltage

VOL

Differential Output Voltage
(CLK-CLK)

Vo~

1.2

Input High Voltage

VXH

3.75

VDo+0.5

V

Input Low Voltage

VXL

VSS -0.5

1.25

V

Operating Current

100

50

rnA

Outputs Unloaded

Input Pin Capacitance

CIN

8

pF

Fe= 1 MHz

COUT

12

pF

Fe= 1 MHz

0.4

V

IOH=-4.0rnA

V

IOL=6.0mA

V

See Figure 4

CLOCK OurPurS

XTALlINPUf

Output Pin Capacitance

E·S7

ICS1567
AC Characteristics
PARAMETER
Duty Cycle
Frequency Error
Rise Time
Fall Time
VCO Frequency
PLL Acquire Time
Duty Cycle
Load Frequency
Rise Time
Fall Time
Crystal Frequency
Crystal Oscillator
Loading Capacitance
XTALI High Time
XTALI Low Time
Rise Time
Fall Time

SYMBOL

MIN

TYP

CLK and CLK TIMING
40
THIGH
Tr
Tf
Fvco
TLOCK

20

UNITS

NOTES

60
0.5
2
2
180

%
%

3,4,9

ns
ns

5,9
5,9
1

500
LD*TIMING
40

THIGH
FLOAD
Tr
Tf
REFERENCE INPUT CLOCK
5
FXTAL
20
CPAR
TXHI
TXLO
Tr
Tf

MAX

MHz

uS
60
60
2
2

%
MHz

6

ns
ns

7,8
7,8

20

MHz

pF

8
8
10
10

ns
ns
ns
ns

2
2
2, 7
2, 7

ns
ns
ns

10

ns
ns
ns

10

DIGITAL INPUTS
Frequency Select Setup Time
Frequency Select Hold Time
Strobe Pulse Width

1
2
3

Reset Activation
Reset Duration
Restart Delay

4
5
6

10
10

20
PIPELINE DELAY RESET
2*TcLK
4*TcLK
-1 *TCLK

+1.5*TcLK

Notes:
L Use of the post-divider is required for frequencies lower than 20 MHz on CLK and CLK outputs. Use of the
post-divider is recommended for output frequencies lower than 65 MHz.
2. Values for XTALI driven by an external clock
3. Duty Cycle for Differential Output (CLK- CLK)
4. Duty cycle measured at VOD12 for Differential CLK Output
5. Rise and fall time between 20% and 80% ofVOD
6. Duty cycle measured at I.4V for TTL I/O
7. Rise and fall time between 0.8 and 2.0 VDC for TTL I/O
8. Output pin loading = 15 pf
9. See Figure 3.
10. See Figure 4.

E-58

10
10

10

10

II

ICS1567
LATCHED INPUTS:
STROBE
FSO-FS4

~

----~/

3

~

f-1

-------,X

\~-----

x:=

~2----7

PIPELINE DELAY RESET:

STROBE
DIFF eLK
LD

Figure 4

E·59

II

ICS1567
ICS Part
Number
Video Clock
Address (HEX)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

ICS1567 Pattern Request Form
Custom patterns are also available, although a significant
volume commitment and/or one-time mask charge will apply.
Contact ICS Sales for details.

ICS1567742
Frequency

ICS1567Custom Pattern #1
Frequency

(MHz)

(MHz)

112.000
148.000
OFF

135.000
31.500
IOS.500
78.000
86.000
108.000
120.000
128.000
93.000
112.000
148.000
135.000
89.210
105.500
112.000
25.000
4S.000
64.000
7S.000
78.000
86.000
103.000
108.000
120.000
127.000
128.000
13S.000
112.000
148.000

Custom pattern #1 reference frequency = _ _ __
Standard pattern shown above uses 16.000 MHz as the mput reference frequency.

Ordering Information
ICS1567M-XXX
Example:

1T

ICS XXXX M -XXX

1 ~ Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - Package Type

L--_ _ _ _ _ _

M=SOIC

Device lYpe (consists of 3 or 4 digit numbers)

~--------------~
ICS. AV=Standard DeVIce; GSP=Genlock Device

E-60

ICS1572

Integrated
Circuit
Systems, Inc.

•

User Programmable Differential Output Graphics Clock Generator
Features

Description
The ICS1572 is a high performance monolithic phase-locked
loop (PLL) frequency synthesizer. Utilizing rcs's advanced
CMOS mixed-mode technology, the ICS1572 provides a low
cost solution for high-end video clock generation in workstations and high-end PC applications.
The ICS1572 has differential video clock outputs (CLK+ and
CLK-) that are compatible with industry standard video DACs.
Another clock output, LOAD, is provided whose frequency is
derived from the main clock by a programmable divider. An
additional clock output is available, LDIN2, which is derived
from the LOAD frequency and whose modulus may also be
programmed.
Operating frequencies are fully programmable with direct
control provided for reference divider, pre-scaler, feedback
divider and post-scaler.
Reset of the pipeline delay on Brooktree RAMDACsTM may
be performed under register control. Outputs may also be set
to desired states to facilitate circuit board testing.

•
•
•
•
•

Supports high-resolution graphics - CLK output to
180 MHz
Eliminates need for multiple EeL output crystal oscillators
Fully programmable synthesizer capability - not just a
clock multiplier
Available in 20-pin 300 mil wide body sorc package
Available in both parallel (10 I) and serial (30 I)
programming versions
Circuit included for reset of Brooktree RAMDAC pipeline
delay

Applications
•
•

•

Workstations
AutoCad Accelerators
High-end PC graphics systems

ICS1572-101 Pinout
K-7
N.C.
ADO
XTAL1

XTAL1

XTAL2
STROBE
VSS
VSS
LOAD
LD/N2
N.C

XTAL2

1

EXTfBK

BLANK

~

(-301 only)

---7

2
3
4

20
19
18
17

5
6
7

16
15
14

8
9
10

13
12
11

N.C.
AD1
AD2
VDD
VDD
VDDO
IPRG
CLK+
CLKN.C.

PROGRAMMING
INTERFACE

ICS1572-301 Pinout
K-7
CLK+
CLK-

N.C.
ADO
XTAL1

LOAD

XTAL2
STROBE
VSS

LDJN2

VSS
LOAD
LD/N2
N.C.

2
3
4
5
6
7
8
9
10

19
18
17
16
15
14
13
12
11

N.C.
AD1
AD2
VDD
VDD
VDDO
IPRG
CLK+
CLKN.C

Figure 1
I'CS1572RevC0994

RAMDAC

E-61

IS

a trademark of Brooktree Corporation.

ICS1572
Overview

PLL Post-Scaler

The ICS1572 is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully programmable feedback and reference divider capability
allow virtually any frequency to be generated, not just simple
multiples of the reference frequency. The ICS1572 uses the
latest generation of frequency synthesis techniques developed
by ICS and is completely suitable for the most demanding
video applications.

A programmable post-scaler may be inserted between !be YCO
and the CLK+ and CLK- outputs of the ICS1572. This is useful
in generating of lower frequencies, as !be YCO has been
optimized for high-frequency operation.
The post-scaler allows the selection of:
• YCO frequency
• YCO frequency divided by 2

PLL Synthesizer Description Ratiometric Mode

• YCO frequency divided by 4
• Internal register bit (AUXCLK) value

The ICS1572 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to !be reference frequency provided to the PLL (see Figure I). The reference frequency is
generated by an on-chip crystal oscillator or the reference
frequency may be applied to the ICS1572 from an external
frequency source.
The phase-frequency detector shown in the block diagram
drives !be voltage-controlled oscillator, or YCO, to a frequency
!bat will cause the two inputs to the phase-frequency detector
to be matched in frequency and phase. This occurs when:
F(

Load Clock Divider
The ICS1572 has an additional programmable divider
(referred to in Figure 1 as the NI divider) !bat is used to
generate !be LOAD clock frequency for the video DAC. The
modulus of this divider may be set to 3, 4, 5, 6, 8, or 10 under
register control. The design of !bis divider permits !be output
duty factor to be 50/50, even when an odd modulus is selected.
The input frequency to this divider is !be output of the PLL
post-scaler described above.

Digital Inputs - ICS1572-1 01 Option

. _ F(XTALl)· Feedback Divider
Reference Divider

veo). -

This expression is exact; that is, !be accuracy of !be output
frequency depends solely on the reference frequency provided
to the part (assuming correctly programmed dividers).
The YCO gain is programmable, which permits !be ICS1572 to
be optimized for best performance at all operating frequencies.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 391 in steps of one. Any even modulus from
392 through 782 can also be achieved by setting the "double"
bit which doubles !be feedback divider modulus. The feedback
divider makes use of a dual-modulus prescaler technique that
allows the programmable counters to operate at low speed
without sacrificing resolution. This is an improvement over
conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or larger) in this respect.

The ADO-AD3 pins and !be STROBE pin are used to load all
control registers of the ICS1572 (-101 option). The ADO-AD3
and STROBE pins are each equipped with a pull-up and will
be at a logic HIGH level when not connected. They may be
driven with standard TTL or CMOS logic families.
The address of the register to be loaded is latched from !be
ADO-AD3 pins by a negative edge on the STROBE pin. The
data for that register is latched from !be ADO-AD3 pins by a
positive edge on !be STROBE pin. See Figure 2 for a timing
diagram. After power-up, the ICS1572-101 requires 32 register writes for new programming to become effective. Since
only 13 registers are used at present, the programming system
can perform 19 "dummy" writes to address 13 or 14 to complete !be sequence.

Table 1 permits the derivation of "A" & "M" counter programming directly from desired modulus.

E-62

ICS1572
This allows the synthesizer to be completely programmed for
the desired frequency before it is made active. Once the part
has been "unlocked" by the 32 writes, programming becomes
effective immediately.
ALL registers identified in the data sheet (0-9, 11, 12 & 15)
MUST be written upon initial programming. The programming registers are not initialized upon power-up, but the
latched outputs of those registers are. The latch is made transparent after 32 register writes. If any register has not been
written, the state upon power-up (random) will become effective. Registers 13 & 14 physically do not exist. Register 10
does exist, but is reserved for future expansion. To insure
compatibility with possible future modifications to the database, ICS recommends that all three unused locations be written with zero.
ICS1572·101 Register Loading

STROBE

ADQ.AD3

1

~ =L2~X2D<6~3=t-XI:

JX

ADDRESS VALID

An additional control pin on the ICS1572·301, BLANK can
perform either of two functions. It may be used to disable the
phase-frequency detector in line-locked applications. Alternatively, the BLANK pin may be used as a synchronous enable
for VRAM shift clock generation. See sections on LineLocked Operations and VRAM shift clock generation for
details.

Output Description
The differential output drivers, CLK+ and CLK, are currentmode and are designed to drive resistive terminations in a
complementary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRO
pin. The sink current, which is steered to either CLK+ or CLK-,
is approximately four times the current supplied to the IPRG
pin. For most applications, a resistor from VDDO to IPRO will
set the current to the necessary precision. See Figure 6 for
output characteristics.
The LOAD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may
be selected for a modulus of 3, 4, 5, 6, 8, or 10. It may also be
suppressed under register controL

DATA VALID

The LDIN2 output is high-current CMOS type drive whose
frequency is derived from the LOAD output. The programmable modulus may range from 1 to 512 in steps of one.

Figure 2
Digital Inputs - ICS1572-301 Option
The programming of the ICS1572·301 is performed serially
by using the DATCLK, DATA, and HOLD-pins to load an
internal shift register.
DATA is shifted into the register on the nSIng edge of
DATCLK. The logic value on the HOLD- pin is latched at the
same time. When HOLD- is low, the shift register may be
loaded without disturbing the operation of the ICS1572. When
high, the shift register outputs are transferred to the control
registers, and the new programming information becomes
active. Ordinarily, a high level should be placed on the HOLDpin when the last data bit is presented. See Figure 3 for the
programming sequence.

Pipeline Delay Reset Function
The ICS1572 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This sequence can be generated by setting the appropriate register bit
(DACRST) to a logic 1 and then resetting to logic O.
When changing frequencies, it is advisable to allow 500 microseconds after the new frequency is selected to activate the
reset function. The output frequency of the synthesizer should
be stable enough at that point for the video DAC to correctly
execute its reset sequence. See Figure 4 for a diagram of the
pipeline delay reset sequence.
Pipeline DeiII'( Reset Timing

ICS1572·301 Register Loading

~
8

DATClK

~~ ~:...)~ ""-' ;t.-r·;':"':J'- -=-~C'I:. : ' ' -:

STROBE
or
DATCLK

CLK+

LOAD

Figure 3

Figure 4
E·63

ICS1572
ICS1572-101

The ICS1572 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.

The ICS1572-101 supports phase detector
disable via a special control mode. When the
PDRSTEN (phase detector reset enable) bit is
set, a high level on AD3 will disable PLL
locking.

ICSlS72-301

The ICSlS72-301 supports phase detector
disable via the BLANK pin. When the
PDRSTEN bit is set, a high level on the
BLANK input will disable PLL locking.

Series-resonant crystals may also be used with the ICS1572.
Be aware that the oscillation frequency will be slightly higher
than the frequency that is stamped on the can (typically 0.0250.05%).

External Feedback Operation

Reference Oscillator and Crystal
Selection

As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1572 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
If an external reference frequency source is to be used with the
ICS1572, it is important that it be jitter-free. The rising and
falling edges of that signal should be fast and free of noise for
best results.
The loop phase is locked to the falling edges of the XTALl
input signals.

Line-Locked Operation
The ICS1572 supports line-locked clock applications by allowing the LOAD (N!) and N2 divider chains to act as the
feedback divider for the PLL.

The ICS1572-301 option also supports the inclusion of an
external counter as the feedback divider of the PLL. This mode
is useful in graphic systems that must be "genlocked" to
external video sources.
When the EXTFBEN bit is set to logic I, the phase-frequency
detector will use the EXTFBK pin as its feedback input. The
loop phase will be locked to the rising edges of the signal
applied to the EXTFBK input.

VRAM Shift Clock Generation
The ICS1572-301 option supports VRAM shift clock generation and interruption. By programming the N2 counter to
divide by I, the LDIN2 output becomes a duplicate of the
LOAD output. When the SCEN bit is set, the LDIN2 output
may be synchronously started and stopped via the blank pin.
When BLANK is high, the LDIN2 will be free-running and in
phase with LOAD. When BLANK is taken low, the LDIN2
output is stopped at a low level. See Figure 5 for a diagram of
the sequence. Note that this use of the BLANK pin precludes its
use for phase comparator disable (see Line-Locked Operation).

The NI and N2 divider chains allow a much larger modulus to
be achieved than the PLL's own feedback divider. Additionally,
the output of the N2 counter is accessible off-chip for performing horizontal reset of the graphics system, where necessary.
This mode is set under register control (ALTLOOP bit). The
reference divider (R counter) is set to divide by I in this mode,
and the HSYNC signal of the external video will be supplied
to the XTALl input. The output frequency of the synthesizer
will then be:
F(CLK):

=F

VRAM Shift Clock Control

BLANK

\~~\\\\~~

~

~~

~

(XTALl)· NI . N2.

By using the phase-detector hardware disable mode the PLL
can be made to free-run at the beginning of the vertic;U interval
of the external video, and can be reactivated at its completion.

E-64

/l1I!!/1!!1!!l

FigureS

r-

II

ICS1572
•

Power-On Initialization
The ICS1572 has an internal power-on reset circuit that perfonns the following functions:
I)

Sets the multiplexer to pass the reference frequency
to the CLK+ and CLK- outputs.

2)

Selects the modulus of the NI divider (for the
LOAD clock) to be four.

Phase Detector Gain: For most graphics applications and
divider ranges, set P[l,O] = 10 and set P[2] = I. Under
some circumstances, setting the P[2] bit "on" can reduce
jitter. During 1572 operation at exact multiples of the
crystal frequency, P[2] bit = 0 may provide the best jitter
perfonnance.

Board Test Support

These functions should allow initialization of most graphics
systems that cannot immediately provide for register programming upon system power-up.
Because the power-on reset circuit is on the VDD supply, and
because that supply is filtered, care must be taken to allow the
reset to de-assert before programming. A safe guideline is to
allow 20 microseconds after the VDD supply reaches 4 volts.

It is often desirable to statically control the levels of the output
pins for circuit board test. The ICS1572 supports this through
a register programmable mode, AUXEN. When this mode is
set, two register bits directly control the logic levels of the
CLK+/CLK- pins and the LOAD pin. This mode is activated
when the S[O] and S[I] bits are both set to logic I. See Register
Mapping for details.

Power Supplies and Oecoupling
Programming Notes
•

•

•

VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
Divider Range: For best results in nonnal situations (i.e.,
pixel clock generation for hi-res displays), keep the reference divider modulus as short as possible (for a frequency
at the output of the reference divider in the few hundred
kHz to several MHz range). If you need to go to a lower
phase comparator reference frequency (usually required
for increased frequency accuracy), that is acceptable, but
jitter perfonnance will suffer somewhat.
VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as shown
here:
VCOGAIN
4
5
6

MAX FREQUENCY
120 MHz
200 MHz
230 MHz

7

*

The ICS1572 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as close
to the package as is possible.
The ICS1572 has a VDDO pin which is the supply of +5 volt
power to all output drivers. This pin should be connected to the
power plane (or bus) using standard high-frequency decoupiing practice. That is, capacitors should have low series inductance and be mounted close to the ICS1572.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for
this pin (as shown in the recommended application circuitry).
This will allow the PLL to "track" through power supply
fluctuations without visible effects. See Figure 7 for typical
external circuitry.
DIFFERENTIAL CLOCK OUTPUT SINK CURRENT
'-"40

!35

• SPECIAL APPLICATION. Contact factory for custom product above
230 MHz.

~~

!PRG RES
(Oh"", )

30

_I

25·

,30

20--NC~~~~=='===='i
15

,:1
~I
1"

5·

o~--~~-~~-~~­

o

05

1

15

2

25

3
3~
ClKt!CU(- OUTPUT VOLTAGE (Volts)

Figure 6

E-65

ICS1572
ICS1572 Typical Interface

DATA BUS

{

+5V

SELECT

120

120

TO
RAMDAC

390

I
Figure 3

E-66

390

II

ICS1572

Register Mapping -ICS1572-101 (Parallel Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND TIlE FUNCTION OF TIlESE BITS TO USE TIlE ICS 1572. PC SOFfWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.

REG#

BIT(S)

0
I

0-3
0-2

R[0] .. R[3]
R[4] .. R[6]

Reference divider modulus conirol bits
Modulus = value + I

2

0-3

A[0] .. A[3]

Conirols A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for "value" underflows of the prescaler, and modulus=6
thereafter until M counter underflows.

3
4

0-3
0-1

M[0] .. M[3]
M[4] .. M[5]

M counter conirol bits
Modulus = value + I

4

3

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 6n to 12/14).

5

0-2

Nl[0] .. NI[2]

Sets NI modulus according to this table. These bits are set to implement a divide-by-four on power-up.

BIT REF.

DESCRIPTION

Nl[2]

Nl[l]
0
0
I
I
0
0
I
I

0
0
0
0
1
1
1
1
6
7

0-3
0-3

N2[0] ..N2[3]
N2[4] .. N2[7]

8

3

N2[8]

8

0-2

V[O] .. V[l]

NI[O]
0
1
0
1
0
1
0
I

RATIO
3
4
4
5
6
8
8
10

Sets the modulus of the N2 divider. Modulus = value + 1
The input of the N2 divider is the output of the NI divider in all clock
modes except AUXEN.

Sets the gain of the VCO.

V[2]

V[l]

V[O]

VCOGAIN
(MHzlVOLT)

1
1
1
1

0
0

0
1
0
1

30
45
60
80

E-67

1
1

ICS1572
BIT(S)

9

0-1

DESCRIPTION

BIT REF.

Sets the gain of the phase detector according to this table.

P[O] ..P[1]

P[I]

prO]

GAIN (uNradian)

0
0
1
1

0
1

0.05
0.15
0.5
1.5

0
1

9

3

[P2]

Phase detector tuning bit. Normally should be set to one.

11

0-1

S[O] .. S[1]

PLL post-scaler/test mode select bits
S[I] S[O]
0

0

0

1

1

0

1

1

DESCRIPTION
Post-scaler=1. F(CLK)=F(PLL). The output of the Nl divider drives
the LOAD output which in turn drives the N2 divider.
Post-scaler=2. F(CLK)=F(PLL)/2. The output of the Nl divider
drives the LOAD output which in turn drives the N2 divider.
Post-scaler=4. F(CLK)=F(PLL)/4. The output of the Nl divider
drives the LOAD output which in turn drives the N2 divider.
AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXNI bit drives the LOAD
output which in turn, drives the N2 divider.

11

2

AUX_CLK

When in the AUXEN clock mode, this bit controls the differential
outputs.

11

3

AUX_Nl

When in the AUXEN clock mode, this bit controls the LOAD output
(and consequently the N2 output according to its programming).

12

0

RESERVED

Must be set to zero.

JAMPLL

Tristates phase detector outputs; resets phase detector logic, and
resets R, A, M, and N2 counters.

12
12

2

DACRST

Set to zero for normal operation. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/- 1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to
this register bit followed by a zero.

12

3

SELXTAL

When set to logic 1, passes the reference frequency to the post-scaler.

15

0

ALTLOOP

Controls substitution of Nl and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the Nl and N2 dividers are used.

15

3

PDRSTEN

Phase-detector reset enable control bit. When this bit is set, the AD3
pin becomes a transparent reset input to the phase detector.
See LINE-LOCKED CLOCK GENERATION section for more
details on the operation of this function.

E-6S

ICS1572
Register Mapping - ICS1572-301 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS 1572. PC SOFrWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.

BIT(S)

BIT REF.

1-3

Nl[O]..Nl[2]

DESCRIPTION
Sets Nl modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
Nl[2]

0
0
0
0
1
1
1

Nl[l]
0
0
1
1

0
0
1

Nl[O]
0
1

0
1
0
1
0

RATIO
3
4
4

5
6
8
8

4

RESERVED

Set to zero.

5

RESERVED

MUST be set to zero.lf this bit is ever programmed for a logic one, device
operation will cease and further serial data load into the registers will be
inhibited until a power-off/power-on sequence.

6

JAMPLL

Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.

7

DACRST

Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+1-1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.

8

SELXTAL

When set to logic 1, passes the reference frequency to the post-scaler.

9

ALTLOOP

Controls substitution of Nl and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the Nl and N2 dividers are used.

10

SCEN

VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LDIN2 output.

11

EXTFBKEN

External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.

12

PDRSTEN

Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See LINE-LOCKED
CLOCK GENERATION section for more details on the operation of
this function.

E·69

ICS1572
BIT(S)

BIT REF.

13-14

S[O] ..s[1]

DESCRIPTION
PLL post-scaler/test mode select bits.
S[I] S[O]
DESCRIPTION
0
0 Post-scaler=1. F(CLK)=F(PLL). The output of the Nl divider drives
the LOAD output which, in tum, drives the N2 divider.
1 Post-scaler=2. F(CLK)=F(PLL)l2. The output of the NI divider
0
drives the LOAD ou_tput which, in tum, drives the N2 divider.
0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the Nl divider
I
drives the LOAD output which, in tum, drives the N2 divider.
1
1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXNl bit drives the LOAD
output which, in tum, drives the N2 divider.

IS

When in the AUXEN clock mode, this bit controls the differential outputs.

16

When in the AUXEN clock mode, this bit controls the Nl output (and
consequently the N2 output according to its programming).

17-24
28
25-27

29-30

.

~~[gl N2[7]
V[0] .. V[2]

P[O] .. P[I]

}

Sets the modulus of the N2 divider. The input of the N2 divider is the
output of the Nl divider in all clock modes except AUXEN.
Sets the gain ofVCO.

V[2]

V[I]

V[O]

1
I
I
1

0
0
1
1

0
I
0
I

VCOGAIN
(MHzNOLT)
30
45
60
80

Sets the gain of the phase detector according to this table.
P[I]
0
0
I
I

prO]
0
1

0
1

GAIN (uA/radian)
0.05
0.15
0.5
1.5

31

RESERVED

Set to zero.

32

P[2]

Phase detector tuning bit. Should normally be set to one.

E·70

ICS1572
BIT(S)

BIT REF.

DESCRIPTION

33-38

M[0) .. M[5)

M counter control bits
Modulus = value + 1

39

RESERVED

Set to zero.

40

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 617 to 12/14).

41-44

A[0) .. A[3)

Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for "value" underflows of the prescaler, and modulus=6
thereafter until M counter underflows.

45-48

RESERVED

Set to zero.

49-55

R[0) .. R[6)

Reference divider modulus control bits
Modulus = value + 1

56

RESERVED

Set to zero.

E-71

ICS1572
Table 1 • "A" & "M" Divider Programming
Feedback Divider Modulus Table
A[2j •• A[Oj-

001

010

011

100

101

110

111

A[2] ••A[Oj-

000

M[5]..M[O]
000000
000001

001

010

011

100

101

110

111

000

199
205

200
206

201
207

202

203
209
215

204
210

205
211

231
238

M[5]..M[O]
13

000010

19

20

000011

25

26

27

000100

31

32

33

34

000101

37

38

40

41

000110
000111

43
49

44
50

39
45
51

46
52

47
53

56
62

57
63

58
64

68
74

69
75

80
86

7
14

100000
100001

21

100010

211

212

213

208
214

216

217

245

28

100011

217

218

219

220

221

222

223

252

35

100100

223

224

225

226

227

228

229

259

42

100101

229

230

231

232

233

234

235

266

100110
100111

235
241

236

237
243

238
244

239
245

240
246

241
247

273
280

248
254

249

250

251

252

253

287

255

256

257

258

259

294

48
54

55

49
56

59

60

61

63

101000

247

65

66

67

70

101001

253

70

71

72

73

77

101010

263

264

265

301

78

79

84

101011

266

261
267

262

77

259
265

260

76

268

269

270

271

81
87

82
88

83
89

84
90

85
91

91

101100

271

273
279

274
280

275
281

276
282

277

308
315

96
102

97

001000

55

001001

61

001010

67

001011

73

001100
001101

79
85

001110
001111

91
97

92

93

94

98

99

100

95
101

010000

103

104

105

106

107

010001

109

110

111

112

010010
010011

115
121

116
122

117
123

010100

127
133

128

129

134

010111

139
145

011000

151

011001
011010

242

98

101101

277

272
278

283

322

101110

283

284

285

286

287

288

289

329

103

105
112

101111

289

290

291

292

293

294

295

336

108

109

119

110000

295

296

297

299

300

301

343

113

114

115

126

110001

301

302

303

298
304

350

119
125

120
126

121
127

133
140

110010
110011

307
313

308
314

309
315

310
316

306
312

307

118
124

305
311
317

357
364

131
137

132

133

319

322

323

325

371

139

110101

325

320
326

321
327

328

329

330

331

378

140

141

142

143

138
144

147
154

110100

135

130
136

318
324

313
319

161

110110

331

334

335

385

147

148

149

340

343

392

152

153

154

155

157
163

158
164

159
165

160

346
352

341
347

336
342

337

146

333
339

353

348
354

349
355

399
406

011011

169

170

171

011100

175

177

011101

181

176
182

011110

187
193

010101
010110

011111

150

145
151

168

110111

337

332
338

157
163

175
182

111000
111001

343

344

349

350

345
351

166

161
167

156
162
168

169

189

111010

357

358

359

360

361

413

173

174

175

196

111011

355
361

356

172

362

363

364

365

366

367

420

179

180

181

203

368

369

370

371

372

373

427

185

186

187

210

111100
111101

367

183

178
184

373

374

375

376

377

378

379

434

188

189

190

191

192

193

217

111110

380

381

382

383

384

195

196

197

198

199

224

111111

386

387

388

389

390

385
391

441

194

379
385

Notes:
To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values.
Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three
combinations of divider settings. Any are acceptable for use.
The formula for the effective feedback modulus is:

N =[(M +1)·6] +A

except when A=O, then:

N=(M +1)' 7

Under all circumstances:

AS;M

E·72

448

II

ICS1572

Pin Descriptions - ICS1572-101
PIN#

NAME

13
12
8
3
4
2
19
18
17

CLK+
CLK-

9
5
16
15
14
6,7
1,10,11,20

LOAD
XTALl
XTAL2
ADO
ADI
AD2
AD3
LDIN2
STROBE
VDD
VDDO
IPRO
VSS
NC

DESCRIPTION
Clock out (non-inverted)
Clock out (inverted)
Load output. This output is nonnally at the CLK frequency divided by Nl.
Quartz crystal connection lIexternal reference frequency input
Quartz crystal connection 2
AddresslData Bit 0 (LSB)
AddresslData Bit I
AddresslData Bit 2
AddresslData Bit 3 (MSB)
Divided LOAD output. See text.
Control for address/data latch
PLL system power (+5V. See application diagram.)
Output stage power (+5V)
Output stage current set
Device ground. Both pins must be connected to the same ground potential.
Not connected

Pin Descriptions - ICS1572-301
PIN#

NAME

13
12
8
3
4

CLK+
CLK-

5
19
18
17
9
2
16
15
14
6,7
1,10,11,20

LOAD
XTALl
XTAL2
DATCLK
DATA
HOLDBLANK
LDIN2
EXTFBK
VDD
VDDO
IPRO
VSS
NC

DESCRIPTION
Clock out (non-inverted)
Clock out (inverted)
Load output. This output is nonnally at the CLK frequency divided by Nl.
Quartz crystal connection lIexternal reference frequency input
Quartz crystal connection 2
Data Clock (Input)
Serial Register Data (Input)
HOLD (Input)
Blanking (Input). See Text.
Divided LOAD output/shift clock. See text.
External feedback connection for PLL (input). See text.
PLL system power (+5V. See application diagram.)
Output stage power (+5V)
Output stage current set
Device ground. Both pins must be connected.
Not connected

£..73

II

ICS1572
Absolute Maximum Ratings
VDD, VDDO (measured to VSS) . . . . . . . . . . . . . . . . . . . . ..
Digital Inputs ......................................
Digital Outputs .....................................
Ambient Operating Temperature .......................
Storage Temperature ................................
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Soldering Temperature ...............................

7.0V
Vss-0.5 to VDD + 0.5V
Vss-0.5 to VDDO + 0.5V
-55 to 125°C
-65 to 150°C
175°C
260°C

Recommended Operating Conditions
VDD, VDDO (measured to VSS) ...................... 4.75 to 5.25V
Operating Temperature (Ambient) ..................... 0 to 70°C

DC Characteristics
TTL-Compatible Inputs
101 Option - (ADO-AD3, STRO~
301 Option - (DATClK, DATA, HOLD, BLANK, EXTFBK)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance

SYMBOL
V,h
ViI
Iih
Iii

CONDITIONS

---

MIN
2.0
Vss-0.5

Vih=VDD
ViI =0.0

Cin

-

MAX
VDD+0.5
0.8

10
150
8

UNITS
V
V
uA
uA
pf

XTAl11nput
PARAMETER
Input High Voltage
Input Low Voltage

SYMBOL

CONDITIONS

Vxh
Vxl

MIN
3.75
Vss-0.5

MAX
VDD+0.5
1.25

UNITS
V

ClK+, ClK- Outputs
PARAMETER
Differential Output Voltage

CONDITIONS

lOAD, lD/N2 Outputs
PARAMETER
Output High Voltage (Ioh=4.OmA)
Output Low Voltage (Iol=8.0mA)

SYMBOL

CONDITIONS

E-74

MIN
2.4

MAX

-

0.4

-

UNITS
V
V

II

ICS1572

AC Characteristics
SYMBOL
Fvco
Fxtal
Cpar
FJoad
Txhl
Txlo
Thigh
Jclk
Tlock
Idd
Iddo

I
2
3
4
5
6
7
8

9
10
11
12
13
14

PARAMETER
VCO Frequency (see Note 1)
Crystal Frequency
Crystal Oscillator Loading Capacitance
LOAD Frequency
XTALl High Time (when driven externally)
XTALl Low TIme (when driven externally)
Differential Clock Output Duty Cycle
I (see Note 2)
Differential Clock Output Cumulative
Jitter (see Note 3)
PLL Acquire Time (to within 1%)

MIN
20
5

MAX
160
20

20
80
8
8
45

55
<0.06

-2

15
20

UNITS
MHz
MHz
pf
MHz
ns
ns
%
pixel

500

VDD Supply Current
VDDO Supply Current (excluding CLK+/tenninatio~ )
DIGITALINPUTS - ICS1572-101
Address Setup Time
10
Address Hold Time
10
Data Setup Time
10
10
Data Hold Time
STROBE Pulse Width (Tin or Tlo)
20
DIGITAL OUTPUTS - ICS1572-301
DATAlHOLD-Setup Time
10
DATAlHOLD-Hold Time
10
20
DATCLK Pulse Width (Thi or Tlo)
PIPELINE DELAY RESET
Reset Activation Time
Reset Duration
4*Tload
Restart Delay
Restart Matching
-!*Tclk
DIGITAL OUTPUTS
CLK+/CLK- Clock Rate
LOAD To LDIN2 Skew (Shift Clock Mode)

TYP

Ils
t.b.d.
t.b.d.

rnA
rnA

ns
ns
ns
ns
ns
ns
ns
ns
2*Tclk

0

2*Tload
+1.5*Tclk

ns
ns
ns
ns

180
+2

MHz
ns

Note 1: Use of the post-divider is required for frequencies lower than 20 MHz on CLK+ & CLK- outputs. Use of the post-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the time domain) of any CLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.

Eo7S

II

ICS1572
Ordering Information
ICS1572M-101 or ICS1572M-301
Example:

ICS XXXX M -XXX

T~

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC

' - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - Prefix
ICS, AV=Standard Device; GSP=Gen!ock Devic

E-76

ICS1572 Application Information

Output Circuit Considerations for the ICS1572
Output Circuitry
The dot clock signals CLK and CLK- are typically the highest
frequency signals present in the workstation. To minimize
problems with EMI, crosstalk, and capacitive loading extra
care should be taken in laying out this area of the PC board.
The ICS1572 is packaged in a 0.3"-wide 20-pin SOIC package. This permits the clock generator, crystal, and related
components to be laid out in an area the size of a postage stamp.
The ICS1572 should be placed as close as possible to the
RAMDAC. The CLK and CLK- pins are running at VHF
frequencies; one should minimize the length of PCB trace
connecting them to the RAMDAC so that they don't become
radiators of RF energy.

Stripline is the other form a PCB transmission line can take. A
buried trace between ground planes (or between a power plane
and a ground plane) is common in multi-layer boards.
Attempting to create a workstation design without the use of
multi-layer boards would be adventurous to say the least, the
issue would more likely be whether to place the interconnect
on the surface or between layers. The between layer approach
would work better from an EMI standpoint, but would be more
difficult to layout. A stripline is shown below:

~=

At the frequencies that the ICS1572 is capable of, PC board
traces may be long enough to be a significant portion of a
wavelength of that frequency. PC traces for CLK and CLKshould be treated as transmission lines, not just interconnecting
wires. These lines can take two forms: microstrip and stripline.
A microstrip line is shown below:

vfr n (iuJ67.:(o~ +~))
_hlnchM

Stripline
Using loz. copper (0.0015" thick) and 0.040" thickness G 10,
a 0.010" trace will exhibit a characteristic impedance of 75Q
in a stripline configuration.

I~t
87

zo·

Typically, RAMDACS require a V,h of VAA-l.O Volts as a
guaranteed logical "I" and a VII of VAA-1.6 as a guaranteed
logical "0." Worst case input capacitance is 10 pf.

(5.9811)

Zo·Ver+1.41 In O.Bw+t
DImenIIor4 ., IneheI

Microstrip Line
Essentially, the micros trip is a copper trace on a PCB over a
ground plane. Typically, the dielectric is G 10 glass epoxy. It
differs from a standard PCB trace in that its width is calculated
to have a characteristic impedance. To calculate the characteristic impedance of a microstrip line one must know the width
and thickness of the trace, and the thickness and dielectric
constant of the dielectric. For G 10 glass epoxy, the dielectric
constant (er) is about 5. Propagation delay is strictly a function
of dielectric constant. For G 10 propagation, delay is calculated to be 1. 77 ns/ft.

Output circuitry for the ICS1572 is shown in the following
diagram. It consists of a 4/1 current mirror, and two open drain
output PETs along with inverting buffers to alternately enable
each current-sinking driver. Both CLK and CLK- outputs are
connected to the respective CLOCK and CLOCK* inputs of
the RAMDAC with transmission lines and terminated in their
equivalent impedances by the Thevenin equivalent impedances
ofRl and R2 or Rl' and R2'.

E-77

ICS1572 Application Note

The ICS1572 is incapable of sourcing current, so Vih must be
set by the ratios of these resistors for each of these lines. R I
and R2 are electrically in parallel from an AC standpoint
because V dd is bypassed to ground through bypass-capacitor
network Cb. If we picked a target impedance of 750 for our
transmission line impedance, a value of 910 for RI and RI'
and a value of 4300 for R2 and R2' would yield a Thevinin
equivalent characteristic impedance of75.IW and a Vih value
of VAA-.873 Volts, a margin of 0.1 27Volts. This may be
adequate; however, at higher frequencies one must contend
with the 10 pF input capacitance of the RAMDAC. Values of
820 for RI and RI' and 8200 for R2 and R2' would give us a
characteristic impedance of74.50 and a Vih value of V AA-.45.
With a .55 Volt margin on Vih, this voltage level might be safer.

Cb is shown as multiple capacitors. Typically, a 221lF tantalum
should be used with separate .IIlF and 220pf capacitors placed
as close to the pins as possible. This provides low series
inductance capacitors right at the source of high frequency
energy. Rd is used to isolate the circuitry from external sources
of noise. Five to ten ohms should be adequate.

v..,
R.

....

-------,

RI

RI'

VM

It

Clock-

'---=:~"l!...:r---t---1H Clock

To set a value for ViI, we must determine a value for Iprg that
will cause the output PET's to sink an appropriate current. We
desire ViI to be VAA-1.6 or greater. VAA-2 would seem to be a
safe value. Setting up a sink current of 25 milliamperes would
guarantee this through our 820 pull-up resistors. As this is
controlled by a 4/1 current mirror, 7 rnA into Iprg should set this
current properly. A 51 00 resistor from V dd to Iprg should work
fine.
Resistors Rt and Rt' are shown as series terminating resistors
at the ICS1572 end of the transmission lines. These are not
required for operation, but may be useful for meeting EMI
requirements. Their intent is to interact with the input capacitance of the RAMDAC and the distributed capacitance of the
transmission line to soften up rise and fall times and consequently cut some of the high-order harmonic content that is
more likely to radiate RF energy. In actual usage they would
most likely be 10 to 200 resistors or possibly ferrite beads.

..

n

R2

ICS1572

...

RAMDAC

GND

ICS1572 Output Circuitry
Great care must be used when evaluating high frequency circuits to achieve meaningful results. The I Opf input capacitance
and long ground lead of an ordinary scope probe will make any
measurements made with it meaningless. A low capacitance
PET probe with a ground connection directly connected to the
shield at the tip will be required. A I GHz bandwidth scope will
be barely adequate, try to find a faster unit.

E·7S

ICS1574

Integrated
Circuit
Systems, Inc.

User Programmable Laser Engine Pixel Clock Generator
Description

Features

The ICS1574 is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer designed for laser
engine applications. Utilizing ICS's advanced CMOS mixedmode technology, the ICS1574 provides a low cost solution
for high-end pixel clock generation for a variety oflaser engine
product applications.

•

The pixel clock output (PCLK) frequency is derived from the
main clock by a programmable resettable divider.

•

Operating frequencies are fully programmable with direct
control provided for reference divider, feedback divider and
post-scaler.

Block Diagram

•

•
•
•
•
•
•
•

Supports high resolution laser graphics. PLLIVCO
frequency re-programmable through serial interface
port to 400 MHz; allows less than ±1.5ns pixel clock
resolution.
Laser pixel clock output is synchronized with conditioned
beam detect input
Ideal for laser printer, copier and FAX pixel clock applications
On-chip PLL with intemalloop filter
On-chip XTAL oscillator frequency reference
Resettable, programmable counter gives glitch-free
clock alignment
Single 5 volt power supply
Low power CMOS technology
Compact - 16-pin 0.150" skinny SOIC package
User re-programmable clock frequency supports
zoom and gray scale functions

XTALl
XTAL2

,
,,
J
i
!
!

L ___ ~ ____________________________________________________

PROGRAMMING
1NlERFACE

DATA

PCLK

DATCLK

PCLKEN

Figure 1
IICS1574RevB1094

E·79

II

ICS1574
Pin Configuration

PCLKEN
XTAL1
XTAL2
DATCLK
VSS
VSS
PCLK
(Do Not Connect) Reserved

1

2
3
4
5
6
7

16
15
14
~
13
II)
..... 12

~

8

11
10

9

DATA
HOLD
Test (Connect to VSS)
VDD
VDDO
Reserved (Do Not Connect)
Reserved (Do Not Connect)
Reserved (Do Not Connect)

16-Pin skinny sOle
K·6

Pin Descriptions
PIN NUMBER

7
1
2
3
4
16
15
14
8,9,10,11
13
12
5,6

PIN NAME
PCLK
PCLKEN
XTALI
XTAL2
DATCLK
DATA

IIDID
Test
Reserved
VDD
VDDO
VSS

DESCRIPTION
Pixel clock output.
PCLK Enable (Input).
Quartz crystal connection II external reference frequency input.
Quartz crystal connection 2.
Data Clock (Input).
Serial Register Data (Input).
JIOI:U (Input).
Test. (Must be connected to VSS.)
Reserved. (Do Not Connect.)
PLL system power (+5V. See application diagram).
Output stage power (+5V).
Device ground. (Both pins must be connected.)

E-80

II

ICS1574

PCLK Programmable Divider
The ICS1574 has a programmable divider (referred to in
Figure 1 as the PCLK divider) that is used to generate the
PCLK clock frequency for the pixel clock output. The modulus
of this divider may be set to 3, 4, 5, 6, 8,10,12,16 or 20 under
register control. The design of this divider permits the output
duty factor to be 50150, even when an odd modulus is selected.
The input frequency to this divider is the output of the PLL
post-scaler described below:

FVCO~"
PCLK~N
(Active
Low)

{/.

I.

Ton

r- +

Tk

Td

\

r-

'I~

'I

Tveo

TK=K.Tvco
Td=LOGIC PROP.DELAY TIME
(typically 9ns with a 10pF load on PCLK)
Tvco=llFvco

When PCLKEN is deasserted, the PCLK output will complete
its current cycle and remain at VDD until the next PCLKEN
pulse. The minimum time PCLKEN must be disabled
(TpULSE) is lIFpcLK.
See Figure 2a for an example of PCLKEN enable (negative
polarity) vs. PCLK timing sequences.

I

,;----------

PCLK

The phase of the PCLK output is aligned with the internal high
frequency PLL clock (Fvco) immediately after the assertion
of the PCLKEN input pulse (active low if PCLKEN]OL bit
is 0 or active high if PCLKEN_POL bit is 1).

~Tvco

Figure2b
The resolution of Ton is one VCO cycle.

The time required for a PCLK cycle start following a
PCLKEN enable is described by Figure 2b and the following table:
PCLKEN

(Active Low)

--,

. . - -/ / - - - - ,
//---1
L..--

'-:_ _ _ _ _

+rolf'"

+.:

Ton

......
Tr

.. rt'+

KValues
PCLK Divider
3
4a
4b
5
6
8a
8b
10
12
16a
16b
20

"'--TPULSE----+

Toff < TpCLK, TpCLK=IIFPCLK
TpULSE > TpCLK

Figure2a

K
2
3.5
3
4.5
3.5
5.5
5
7

6.5
9.5
9
12

Typical values for Tr and Tf with a IOpF load on PCLK
are Ins.

E·81

ICS1574
PLL Post-Scaler

Digital Inputs

A programmable post-scaler may be inserted between the YCO
and the PCLK divider of the ICS1574. This is useful in
generating lower frequencies, as the YCO has been optimized
for high-frequency operation. The post-scaler is not affected
by the PCLKEN input.

The programming of the ICS1574 is performed serially by
using the DATCLK, DATA, and HOLD pins to load an internal
shift register.

The post-scaler allows the selection of:
• YCO frequency
• YCO frequency divided by 2
• YCO frequency divided by 4
• AUX-EN Test Mode

PLL Synthesizer Description Ratiometric Mode

DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD pin is latched at the
same time. When HOLD is low, the shift register may be loaded
without disturbing the operation of the ICS1574. When high,
the shift register outputs are transferred to the control registers,
and the new programming information becomes active. Ordinarily, a high level should be placed on the HOLD pin when
the last data bit is presented. See Figure 3 for the programming
sequence.
The PCLKEN input polarity may be programmed under register control via Bit 39.

The ICS1574 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference
frequency may be applied to the ICS1574 from an external
frequency source.

ICS1574 Register loading

DATCLK~
~DM~~ DM~2 >C~~\~~~,~.~.

:::
HOLD

The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or YCO, to a frequency
that will cause the two inputs to the phase-frequency detector
to be matched in frequency and phase. This occurs when:

JD\

fII\

r

C

Figure 3
Output Description

F(vco : = F(XTALl)' Feedb~c~ Divider
)
Reference DIVider
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency provided
to the part (assuming correctly programmed dividers).
The YCO gain is programmable, which permits the ICS1574
to be optimized for best performance at all operating frequencies.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 392 in steps of one. Any even modulus from
392 through 784 can also be achieved by setting the "double"
bit which doubles the feedback divider modulus. The feedback
divider makes use of a dual-modulus prescaler technique that
allows the programmable counters to operate at low speed
without sacrificing resolution. This is an improvement over
conventional fixed prescaler architectures that typically impose a factor-of-four (or larger) penalty in this respect.
Table 1 permits the derivation of "A" & "M" converter programming directly from desired modulus.

The PCLK output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may
be selected for a modulus of 3,4, 5, 6, 8, 10, 12, 16 or 20. It
may also be suppressed under register control via Bit 46.

Reference Oscillator and Crystal
Selection
The ICS1574 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.
Series-resonant crystals may also be used with the ICS1574.
Be aware that the oscillation freque~cy will be slightly higher
than the frequency that is stamped on the can (typically 0.0250.05%).

E-82

ICS1574
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1574 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.

•

VCOGAIN
4
5
6

If an external reference frequency source is to be used with the
ICS1574, it is important that it be jitter-free. The rising and
falling edges of that signal should be fast and free of noise for
best results.
The loop phase can be locked to either the rising or falling
edges of the XTALl input signals, and is controlled by Bit 56.

VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as shown
here:

7

•

Power-On Initialization

MAX FREQUENCY
100 MHz
200 MHz
300 MHz
400 MHz

Phase Detector Gain: For most applications and divider
ranges, set P[I,O] = 10 and set P[2] = 1. Under some
circumstances, setting the P[2] bit "on" can reduce jitter.
During operation at exact multiples of the crystal frequency,
P[2] bit =0 may provide the best jitter performance.

The ICS1574 has an internal power-on reset circuit that performs the following functions:
1)

2)

Board Test Support

Selects the modulus of the PCLK divider
to be four (4).
Sets the multiplexer to pass the reference frequency to
PCLK divider input.

These functions should allow initialization for most applications that cannot immediately provide for register programming upon system power-up.
Because the power-on reset circuit is on the VDD supply, and
because that supply is filtered, care must be taken to allow the
reset to de-assert before programming. A safe guideline is to
allow 20 microseconds after the VDD supply reaches 4 volts.

Programming Notes
•
•

VCO Frequency Range: Use the post-divider to keep the VCO
frequency as high as possible within its operating range.
Divider Range: For best results in normal situations keep
the reference divider modulus as short as possible (for a
frequency at the output of the reference divider in the few
hundred kHz to several MHz range). If you need to go to
a lower phase comparator reference frequency (usually
required for increased frequency accuracy), that is acceptable, but jitter performance will suffer somewhat.

It is often desirable to statically control the levels of the output
pins for circuit board test. The ICS1574 supports this through
a register programmable mode, AUX-EN. When this mode is
set, a register bit directly controls the logic level of the PCLK
pin. This mode is activated when the S[O] and S[1] bits are both
set to logic 1. See Register Mapping for details.

Power Supplies and Oecoupling
The ICS1574 has two VSS pins to reduce the effects of package
inductance. Both pins are connected to the same potential on
the die (the ground bus). BOTH of these pins should connect
to the ground plane of the PCB as close to the package as is
possible.
The ICS1574 has a VDDO pin which is the supply of +5 volt
power to the output driver. This pin should be connected to the
power plane (or bus) using standard high-frequency decoupIing practice. That is, capacitors should have low series inductance and be mounted close to the ICS1574.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for
this pin (as shown in the recommended application circuitry).
This will allow the PLL to "track" through power supply
fluctuations without visible effects. See Figure 4 for typical
external circuitry.

E-83

II

ICS1574
a)

PCLKEN
(Condttloned Beam
Detect Input)

O.luF

PROGRAMMING {
INTERFACE

__~===:=j

PCLKEN

XlALl
XlAL2
~_ _-I~CLK

VSS

PCLK
RES

DATA
HOLD
TEST

10

VDvggF~~=~===~~::::r_·+5V
RES
RES

NC
NC

RES

NC-",.-

*

' - - - - - - - - - - - - - - - - - - - - - PCLK

Figure 4

E-84

II

ICS1574

Register Mapping - ICS1574
NOTE: rr IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE Brrs TO USE THE ICS1574. PC SOFrWARE IS AV All..ABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTFR VALUES BASED ON REQUIREMENfS. CONTACT FACTORY FOR DErAILS.

BIT REF.

1-4

PCLK[O]. .PCLK[3]

DESCRIPTION
Sets PCLK divider modulus according to this table. These bits are set to
implement a divide-by-four on power-up.

PCLK[3]
0
0
0
0
0
0
0
0
1
1
1
1

PCLK[2]
0
0
0
0
1
1
1
1
X
X
X
X

PCLK[l]
0
0
1
1
0
0
1
1
0
0
1
1

PCLK[O]
0
1
0
1
0
1
0
1
0
1
0
1

MODULUS
3
4(a)
4(b)
5
6
8(a)
8(b)
10
12
16(a)
16(b)
20

X=Don't care

5,6

Reserved

Must be set to O.

7

Reserved

Must be set to 1.

8

SELXTAL

Normally set to O. When set to logic 1, passes the reference frequency to the
post-scaler instead of the PLL output (defuults to 1 on power-up).

9

Reserved

Must be set to O.

10

Reserved

Must be set to 1.

11,12

Reserved

Must be set to O.

13-14

S[O] .. S[I]

PLL post-scaler/test mode select bits.
S[I] S[O]
DESCRIPTION
0
0 Post-scaler= 1. F(CLK) = F(PLL). The output of the PCLK divider
drives the PCLK output.
1 Post-scaler =2. F(CLK)=F(PLL)/2. The output of the PCLK
0
divider drives the PCLK output.
0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the PCLK
1
divder drives the PCLK output.
1
1 AUX-EN TEST MODE. The AUX PCLK bit dirves the PCLK
output.

E·85

II

ICS1574
BIT(S)

BIT REF.

DESCRIPTION

15

Reserved

Must be set to O.

16

AUX]CLK

Must be set to 0 except when in the AUX-EN test mode. When in the
AUX-EN test mode, this bit controls the PCLK output.

17-24

Reserved

Must be set to O.

25-27

V[0] .. V[2]

Sets the gain of VCO.

V[2]

V[I]

V[O]

VCOGAIN
(MHz/VOLT)

1
1
1
1

0
0
1
1

0
1
0
1

30
45
60
80

28

Reserved

Must be set to 1.

29-30

P[O] .. P[1]

Sets the gain of the phase detector according to this table.
P[I]
0
0
1
1

prO]
0
1
0
1

GAIN (uNradian)
0.05
0.15
0.5
1.5

31

Reserved

Must be set to O.

32

P[2]

Phase detector tuning bit. Should normally be set to one. See text.

33-38

M[0] .. M[5]

M counter control bits
Modulus = value + 1
When=O, PCLK output enabled when PCLKEN input is low.
When=l, PCLK output enabled when PCLKEN input is high.

39
40

DBLFREQ

Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).

41-44

A[0] .. A[3]

Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for "value" underflows of the prescaler, and modulus=6
thereafter until M counter underflows.

E·86

II

ICS1574

BIT(S)

BIT REF.

45

Reserved

Must be set to 1.

46

PCLK_EN

Must be set to O.
Disables the PCLK divider when set to 1 regardless of PCLKEN input state.

47,48

Reserved

Must be set to O.

49-55

R[O] .. R[6]

Reference divider modulus control bits
Modulus = value + 1

56

REF_POL

PLL locks to rising edge of XTALl input when REFPOL=l,
falling edge of XTALl when REFPOL=O

DESCRIPTION

E-87

ICS1574
Table 1 - "A" & "M" Divider Programming
Feedback Divider Modulus Table
A[2j •.A[Oj·
M[5] ..M[O]
000000
000001
000010
000011
000100
000101
000110
0001ll
001000
001001
001010
001011
001100
001101
001110
OOllll
010000
010001
010010
010011
010100
010101
010110
olOm
011000
011001
011010
011011
OlllOO
01ll0i
011110
011m

001

13
19
25
31
37
43
49
55
61
67
73
79
85
91
97
103
109
115
121
127
133
139
145
151
157
163
169
175
181
187
193

010

20
26
32
38
44
50
56
62
68
74
80
86
92
98
104
110
116
122
128
134
140
146
152
158
164
170
176
182
188
194

011

27
33
39
45
51
57
63
69
75
81
87
93
99
105

III
117
123
129
135
141
147
153
159
165
171
177
183
189
195

100

101

110

111

000

A[2] ..A[OjM[5] .. M[O]

001

010

011

100

101

110

111

000

7
14

100000
100001
100010
100011

199
205
211
217
223
229
235
241
247

200
206
212
218
224
230
236
242

201
207
213
219

202
208
214
220
226
232
238
244

203
209

204
210

205
211

215
221

216
222

227
233

228
234
240
246
252
258
264
270
276
282
288
294
300
306
312
318
324

217
223
229
235
241
247
253
259
265
271
277
283
289
295
301
307
313
319
325

231
238
245
252
259
266

330
336
342
348
354
360
366
372
378
384
390

331
337
343
349
355
361
367
373
379
385
391

21
28
34
40
46
52
58
64
70
76
82
88
94
100
106
112
118
124
130
136
142
148
154
160
166
172
178
184
190
196

41
47
53
59
65
71
77
83
89

48
54
60
66
72
78
84
90

95
101
107
113
119
125
131

96
102

55
61
67
73
79
85
91
97
103

108
114
120
126
132

109
115
121
127
133

137
143
149
155
161
167
173
179
185
191
197

138
144
150
156
162
168
174
180
186
192
198

139
145
151
157
163
169
175
181
187
193
199

100100
100101

35
42
49
56
63
70
77
84
91
98

100110
100lll
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010

105
112
119
126
133
140
147
154
161
168
175
182
189
196
203
210
217
224

111011
111100
III 101
111110
111111

253
259
265
271
277
283
289
295
301
307
313
319
325
331
337
343
349
355
361
367
373
379
385

248
254
260
266
272
278
284
290
296
302
308
314
320
326
332
338
344
350
356
362
368
374
380
386

225
231
237
243
249
255
261
267
273
279
285
291
297
303
309
315
321
327
333
339
345
351
357
363
369
375
381
387

250
256
262
268
274
280
286
292
298
304
310
316
322
328
334
340
346
352
358
364
370
376
382
388

239
245
251
257
263
269
275
281
287
293
299
305
311
317
323
329
335
341
347
353
359
365
371
377
383
389

Notes:
To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values.
Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three
combinations of divider settings. Any are acceptable for use.
The formula for the effective feedback modulus is:

N =[(M +1)·6] +A

except when A=O, then:

N=(M +1)' 7

Under all circumstances:

A:::;M

E-88

273
280
287
294
301
308
315
322
329
336
343
350
357
364
371
378
385
392
399
406
413
420
427
434
441
448

II

ICS1574

Absolute Maximum Ratings
VDD, VDDO (measured to Vss) .......................
Digital Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Digital Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ambient Operating Temperature .......................
Storage Temperature ................................
Junction Temperature ................................
Soldering Temperature ...............................

7.0 V
V ss-0.5 to VDD + 0.5 V
V ss-0.5 to VDDO + +0.5 V
-55 to 125°C
-65 to 150°C
175°C
260°C

Recommended Operating Conditions
VDD, VDDO (measured to Vss) .................. " .. , 4.75 to 5.25 V
Operating Temperature (Ambient) . . . . . . . . . . . . . . . . . . . .. 0 to 70°C

DC Characteristics
TTL-Compatible Inputs
(DATCLK, DATA, HOLD, PCLKEN)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
Hysterisis (DATCLK input)

SYMBOL
Vih
ViI
lih
IiI
Cin
VHYS

CONDITIONS

MIN
2.0
Vss-0.5

MAX
VDD+0.5
0.8

V,h=VDD
V,I=O.O

-

VDD=5V

.20

200
8
.60

MIN
3.75
Vss-0.5

VDD+0.5
1.25

10

UNITS
V
V
uA
uA
pF
V

XTAL1 Input (External Reference Frequency)
PARAMETER
Input High Voltage
Input Low Voltage

SYMBOL
Vxh
Vxl

CONDITIONS

MAX

UNITS
V

PCLK
PARAMETER
Output High Voltage (Ioh = 4.0mA)
Output Low Voltage (101 = 8.0mA)

SYMBOL

CONDITIONS
--

E-89

MIN
2.4

MAX

-

0.4

-

UNITS
V
V

ICS1574
AC Characteristics
PARAMETER
VCO Frequency
Crystal Frequency_
Crystal Oscillator Loading Capacitance
XTALI High Time (when driven externally)
XTALI Low Time (when driven externally)
PLL Acquire Time (to within 1 %)
VDD Supply Current
VDDO Supply Current

SYMBOL
Fvco
Fml
C par
Txhi
Txlo
Tlock

MIN

TYP

40
5

500
15
20

J.I.S
t.b.d.
t.b.d.

10
10
20
DIGITAL OUTPUT
FPCLOCK

Ordering Information
ICS1574M IICS1574EB
Example:

ICS XXXX M

_Package Type
M=SOIC
EB=Evaluation Board
Device Type (consists of 3 or 4 digit numbers)
Pref"1X
leS, AV=Standard Device; GSP=Genlock Device

E·90

UNITS
MHz
MHz
pF

ns
ns

8
8

16-Pin Skinny SOIC Package

TT~_T

20
20

Ltd
Iddo
DIGITAL INPUTS

DATA/HOLD- Setup Time
DATA/HOLD- Hold Time
DATCLK Pulse Width (Thi or Tlo)
PCLK output rate

MAX
400

rnA
rnA
ns
ns
ns

130

MHz

•

ICS1577

Integrated
Circuit
Systems, Inc.

Advance Information

High Performance DEC Alpha™ CPU Clock
Description

Features

The ICSIS77 is a high performance monolithic phase locked
loop (PLL) frequency synthesizer. Utilizing ICS's advanced
CMOS mixed mode technology, the ICSIS77 provides a low
cost solution for high-end DEC Alpha CPU clock generation.

•
•
•
•

The ICSIS77 has differential CPU clock outputs (CLK+ and
CLK-) that are compatible with the DEC Alpha CPU operating
up to 466 MHz. The differential output frequency on this
version of the ICSIS77 is set to an exact multiple (28 times)
of the crystal oscillator or reference frequency.

•

•
•
•

CLK operation to 466 MHz
Operates from a single crystal or reference frequency
User-programmable output voltage levels
Independent PLL synthesizer and output driver power
.supply inputs - provides voltage isolation for improved
high frequency operation
Fully user-programmable version available - allows "onthe-fly" output frequency changes useful for 'powerdown' modes or 'low power' applications. Contact factory
for information.
lOOps max cycle-to-cycle jitter
Low power consumption CMOS technology
14-pin DIP package

Simplified Block Diagram -ICS1577

NC
NC
1 - - - 7 1 MUX

XTAL1
cuc+
cuc-

XTAL2
VSS
VSS
CLK-

NC
NC
3
4

12

VDD

11

VDDO

5
6
7

10

IPRG

9

NC

8

CLK+

14·Pln DIP package
K-3

Figure 1

Alpha IS a trademark of Digital EqUipment Corporatlon

IICSl SllAevB090294
E-91

II

ICS1577
Overview

Power-On Initialization

The ICS1577 is ideally suited to provide the CPU clock signals
required by high-performance Alpha processors. The ICS1577
provides up to a 466 MHz (Fxtal x 28) low jitter clock.

The ICS1577 version has a fixed internal power-on reset
circuit that performs the following function:
Sets the multiplexer to pass the VCO frequency
(Fxtal x 28).

Output Description
The differential output drivers, CLK+ and CLK, are currentmode and are designed to drive resistive terminations in a
complementary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRG
pin. The sink current, which is steered to either CLK+ or CLK-.
is approximately four times the current supplied to the IPRG
pin. For most applications, a resistor from VDDO to IPRG will
set the current to the necessary precision. See Figure 2 for
output characteristics.

Reference Oscillator and Crystal
Selection
The ICS1577 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.

Power Supplies and Decoupling
The ICS1577 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the CPU board as close
to the package as is possible.
The ICS1577 has a VDDO pin which is the supply of +5 volt
power to all output drivers. This pin shOUld be connected to the
power plane (or bus) using standard high-frequency decoupiing practice. That is, capacitors should have low series inductance and be mounted close to the ICS1577.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for
this pin (as shown in the recommended application circuitry).
This will allow the PLL to "track" through power supply
fluctuations without visible effects. See Figure 3 for typical
external circuitry.

Series-resonant crystals may also be used with the ICS1577.
Be aware that the oscillation frequency will be slightly higher
than the frequency that is stamped on the can (typically 0.0250.05%).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1577 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
If an external reference frequency source is to be used with the
ICS1577, it is important that it be jitter-free. The rising and
falling edges of that signal should be fast and free of noise for
best results.

DIFFERENTIAL CLOCK OUTPUT SINK CURRENT

~40r-------------~:======;======~

~35
-

30

---

to-

~

25

330

~ 20

-+Sf 0

'~" f5

-e680

--

:!: fO
d
.....

The loop phase is locked to the falling edges of the XTALl
input signals.

E·92

1.5 K

+

d

IAW~S.
(Ohms)

0.5

f

1.5

2

2.5

3

CLK+/ClK- OUTPUT VOlTAGE (Volts)

Figure 2

3.5

4

ICS1577
ICS1577 Typical Interface

N.C.

N.C.

N.C.

N.C.

XTAl1

VDD

VDD

16.643 MHz
XTAl2

VSS
VSS

10

""'"

VDDO

(f)

IPRG

LO
""'"
,....

RIPRG

()

N.C.

ll..
::l

ll..
::l

c:i

c:i

~

ClK-

ClK=

82

510

82

22J.1F

ClK+
466.004 MHz

":'

":'

ClK820

":'

Figure 3

I

fXTAL

11.786 MHz
14.318 MHz
16.643 MHz

fOUT

330.000 MHz
400.904 MHz
466.004 MHz

E-93

820

":'

E

ICS1577
Pin Description
PIN NUMBER
3
4
5,6
7

8
10

11
12
1,2,9, 13, 14

NAME
XTALl
XTAL2
Vss
CLKCLK+
IPRG
VDDO
VDD
N.C.

DESCRIPTION
Quartz crystal connection lIextemal reference frequency input
Quartz crystal connection 2INo connect for EXT REF
Device Ground. Both pins must be connected.
Clock Out (inverted)
Clock Out
Output stage current/voltage set.
Output stage power (+5.0V)
PLL system power (+5V. See application diagram.)
No connection.

Absolute Maximum Ratings
VDD, VDDO (measured to Vss) .......................
Digital Inputs ......................................
Digital Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ambient Operating Temperature. . . . . . . . . . . . . . . . . . . . . ..
Storage Temperature ................................
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Soldering Temperature ...............................

7.0 V
Vss-0.5 to VDD + 0.5 V
V ss-O.5 to VDDO + +0.5 V
-55 to 125°C
-65 to 150°C
175°C
260°C

Recommended Operating Conditions
VDD, VDDO (measured to Vss) ....................... 4.75 to 5.25 V
Operating Temperature (Ambient) ..................... 0 to 50°C
The JCSlS77 can be operated at 3.3V with reduced operating performance. Contact factory for information.

DC Characteristics
XTAl1 Input (External reference)
PARAMETER
Input High Voltage
Input Low Voltage

SYMBOL

CONDITIONS

Vxh
Vxl

ClK+, ClK- Outputs
PARAMETER
Differential Output Voltage

CONDITIONS

E-94

MIN
3.75
Vss-0.5

MAX
VDD+0.5
1.25

UNITS
V

ICS1577
AC Characteristics
SYMBOL

@

25°C

PARAMETER

MIN

MAX

UNITS

140

TYP

500

MHz

5

18

MHz

Fvco

VCO Frequency

Fxtal
Cpar

Crystal Frequency

Txhl

XTALl High Time (when driven externally)

8

ns

Txlo

XTALl Low Time (when driven externally)

8

ns

ThIgh
JC\k

Jp
Tlock
Idd

Crystal Oscillator Loading Capacitance

20

Differential Clock Output Duty Cycle

40

pF

60

%

.075

VCO cycle

375

ps
peak to peak

100

ps
peak to peak

50

rnA

I(see Note 1)
Differential Clock Output Cumulative
Jitter (see Note 2)
Differential Clock Output Cumulative Jitter
@466MHz

<.06

Differential Clock Output Cycle-to-Cycle Jitter
PLL Acquire Time (to within 1%)

500

VDD Supply Current (excluding external
CLK+/- output termination), 466 MHz.

Il s

Note 1: Using load circuit of Figure 3. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 2: Cumulative jitter is defined as the maximum error (in the domain) if any CLK edge, at any point in time, compared
with the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.

Ordering Information
ICS1577N
Example:

ICSXXXX M

~ .......

",.
N=DIP(£lastIC)

' - - - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
L-____________
Prefix

res, AV=Standard Device; GSP=Genlock Device

ADVANCE INFORMATION documents contain mformatlon on new products In the sampling
or preproduction phase of development Charactenstlc data and other speCificatIOns are
subject to change Without notice

E-95

E·96

ICS1577 Application Information

Output Circuit Considerations for the ICS1577
Output Circuitry
The dot clock signals CLK and CLK- are typically the highest
frequency signals present in the workstation. To minimize
problems with EMI, crosstalk, and capacitive loading extra
care should be taken in laying out this area of the PC board.
The IeS1S77 is packaged in a 0.2"-wide 16-pin SOIC package. This pennits the clock generator, crystal, and related
components to be laid out in an area the size of a postage stamp.
The IeS1S77 should be placed as close as possible to the CPU.
The CLK and CLK- pins are running at VHF frequencies; one
should minimize the length of PCB trace connecting them to
the termination so that they don't become radiators of RF
energy.

Stripline is the other form a PCB transmission line can take. A
buried trace between ground planes (or between a power plane
and a ground plane) is common in multi-layer boards. Attempting to create a workstation design without the use of multilayer boards would be adventurous to say the least, the issue
would more likely be whether to place the interconnect on the
surface or between layers. The between layer approach would
work better from an EMI standpoint, but would be more
difficult to layout. A strip line is shown below:

--..-...+-StJ'p line
~~L~~~~~~~~p~

At the frequencies that the IeS1S77 is capable of, PC board
traces may be long enough to be a significant portion of a
wavelength of that frequency. PC traces for CLK and CLKshould be treated as transmission lines, not just interconnecting
wires. These lines can take two forms: microstrip and strip line.
A microstrip line is shown below:

Zo·

~ In (0.067.:(0.8 +~))
DmensIons In Inches

Stripline
Using loz. copper (0.0015" thick) and 0.040" thickness G1O,
a 0.010" trace will exhibit a characteristic impedance of 750
in a strip line configuration.

87

Output circuitry for the IeS1S77 is shown in the following
diagram. It consists of a 4/1 current mirror, and two open drain
output PETs along with inverting buffers to alternately enable
each current-sinking driver. Both CLK and CLK- outputs are
connected to the respective CLOCK and CLOCK* inputs of
the termination with transmission lines and terminated in their
equivalent impedances by the Thevenin equivalent impedances
ofRI and R2 or Rl' and R2'.

(s.98h)

zo·Ver+1A1 In O.Bw+t

Dimensions In Inches

Microstrip Line
Essentially, the microstrip is a copper trace on a PCB over a
ground plane. Typically, the dielectric is G 10 glass epoxy. It
differs from a standard PCB trace in that its width is calculated
to have a characteristic impedance. To calculate the characteristic impedance of a micros trip line one must know the width
and thickness of the trace, and the thickness and dielectric
constant of the dielectric. For G I 0 glass epoxy, the dielectric
constant (er) is about 5. Propagation delay is strictly a function
of dielectric constant. For G 10 propagation, delay is calculated
to be 1.77 ns/ft.

E-97

II

ICS1577 Application Note

The ICS1577 is incapable of sourcing current, so Vih must be
set by the ratios of these resistors for each of these lines. R I
and R2 are electrically in parallel from an AC standpoint
because Vdd is bypassed to ground through bypass-capacitor
network Cb. If we picked a target impedance of 75Q for our
transmission line impedance, a value of 91Q for Rl and Rl'
and a value of 430Q for R2 and R2' would yield a Thevinin
equivalent characteristic impedance of 75.1 Wand a Vih value
of VAA-.873 Volts, a margin of 0.127 Volts. This may be
adequate; however, at higher frequencies one must contend
with the input capacitance of the termination. Values of 82Q
for Rl and RI' and 820Q for R2 and R2' would give us a
characteristic impedance of74.5Q and a Vih value of VAA-.45.
With a .55 Volt margin on Vih, this voltage level might be safer.

Cb is shown as multiple capacitors. Typically, a 221lF tantalum
should be used with separate .IIlF and 220pF capacitors placed
as close to the pins as possible. This provides low series
inductance capacitors right at the source of high frequency
energy. Rct is used to isolate the circuitry from external sources
of noise. Five to ten ohms should be adequate.

V""
Rd

....

c. ;

"

~

Rl

Clock-

...
To set a value for ViI, we must determine a value for Iprg that
will cause the output FET's to sink an appropriate current. We
desire Vii to be VAA-1.6 or greater. VAA-2 would seem to be
a safe value. Setting up a sink current of 25 milliamperes would
guarantee this through our 82Q pull-up resistors. As this is
controlled by a 411 current mirror, 7 rnA into Iprg should set this
current properly. A510Q resistor from Vdd to Iprg should work
fine.
Resistors Rt and Rt' are shown as series terminating resistors
at the ICS1577 end of the transmission lines. These are not
required for operation, but may be useful for meeting EMI
requirements. Their intent is to interact with the input capacitance of the termination and the distributed capacitance of the
transmission line to soften up rise and fall times and consequently cut some of the high-order harmonic content that is
more likely to radiate RF energy. In actual usage they would
most likely be 10 to 20Q resistors or possibly ferrite beads.

v AA

Rl'

Rt

Clock
R2

R2"

Alpha

ICS1577

GND

ICS1577 Output Circuitry
Great care must be used when evaluating high frequency
circuits to achieve meaningful results. The 10 pF input capacitance and long ground lead of an ordinary scope probe will
make any measurements made with it meaningless. A low
capacitance FET probe with a ground connection directly
connected to the shield at the tip will be required. A 1 GHz
bandwidth scope will be barely adequate, try to find a faster
unit.

E·98

ICS2572

Integrated
Circuit
Systems, Inc.

User-Programmable Dual High-Performance Clock Generator
Description

Features

The ICS2572 is a dual-PLL (phase-locked loop) clock generator with differential video outputs specifically designed for
high-resolution, high-refresh rate, video applications. The
video PLL generates any of 16 pre-programmed frequencies
through selection of the address lines FSO-FS3. Similarly, the
auxiliary PLL can generate anyone of four pre-programmed
frequencies via the MSO & MSllines.

•

A unique feature of the ICS2572 is the ability to redefine
frequency selections after power-up. This permits complete
set-up of the frequency table upon system initialization.

•
•
•
•
•
•

Advanced rcs monolithic phase-locked loop
technology
Supports high-resolution graphics - differential CLK output to 185 MHz
Divided dotclock output (LOAD) available
Simplified device programming
Sixteen selectable VCLK frequencies (all user
re-programmable)
Four selectable MCLK frequencies (all user
re-programmable)
Windows NT compatible

Applications
•
•

High end PC/low end workstation graphics designs
requiring differential output
X Terminal graphics

Block Diagram
XTALl
LOAD

XTAL2

CLK+
CLK-

MCLK PLL (as above)

STROBE

FSO
FSl
FS2
FS3

VCLK Set &
Program
Mode
Interface

MSO

MCLKSet

MSl

MCLK

IICS2572RevC090894 I

E-99

II

ICS2572
Pin Configuration

XTAl1
XTAl2
XTFREQ

VDD
ClK+
ClK-

FSO

VSS

FS1
STROBE

lOAD
VAA

FS2

VSS

FS3
MSO

VDD
MClK

VSS

MS1

20-Pin DIP or sOle
K-4, K-7

Pin Descriptions
PIN NUMBER
1
2
3
4
5
7
8
6
9

11
19
18
16
12
17
10,14
13,20
15

PIN NAME
XTALl
XTAL2
EXTFREQ
FSO
FSI
FS2
FS3
STROBE
MSO
MSI
CLK+
CLKLOAD
MCLK
RESERVED
VSS
VDD
VAA

TYPE
A
A
I
I
I
I
I
I
I
I
0
0
0
0
-

P
P
P

DESCRIPTION
Quartz crystal connection llReference Frequencv Input.
•Quartz crystal connection 2.
External Frequencv Input
VCLK PLL Frequencv Select LSB.
VCLK PLL Frequencv Select Bit.
VCLK PLL Frequencv Select Bit.
VCLK PLL Frequencv Select MSB.
Control for Latch ofVCLK Select Bits (FSO-FS3).
MCLK PLL Frequencv Select LSB.
MCLK PLL Frequencv Select MSB.
Pixel Clock Output (not inverted)
Pixel Clock Output (inverted)
Divided Dotclock (/4, 5, or 8)
MCLK Frequencv Output
Must Be Connected to VSS.
Device Ground. All pins must be connected.
Output Stage Vdd. All pins must be connected.
Svnthesizer V dd.
!

E-lOO

II

II

ICS2572

Digital Inputs
The FSO-FS3 pins and the STROBE pin are used to select the
desired operating frequency of the VCLK output from the 16
pre-programmed/user-programmed selections in the ICS2572.
These pins are also used to load new frequency data into the
registers.
Available configurations for the STROBE input include: positive-edge triggered, negatIve-edge triggered, high-level transparent, and low-level transparent (see Ordering Information).

VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the
appropriate data to the ICS2572 FS inputs. Do not perform any
further writes to the device for 50 milliseconds (assumes a
14.318 MHz reference). The synthesizer will output the new
frequency programmed into that location after a brief delay
(see timeout specifications).

MCLK Output Frequency Selection
The MSO-MSI pins are used to directly select the desired
operating frequency of the MCLK output from the four preprogrammed/user-programmed selections in the ICS2572.
These inputs are not latched, nor are they involved with memory programming operations.

Programming Mode Selection
A programming sequence is defined as a period of at least 50
milliseconds of no data writes to the ICS2572 (to clear the shift
register) followed by a series of data writes (as shown here):

FSO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

----

E-lOl

FSI
FS2
START bit (must be "0")
X
"
X
X
R1W* control
"
X
X
LO (location LSB)
"
X
X
L1
"
X
X
L2
X
"
X
L3
"
X
X
L4 (location MSB)
"
X
N()ifeedback LSB)
X
X
"
X
Nl
X
"
X
N2
X
"
X
N3
"
X
X
N4
"
X
X
N5
X
"
X
N6
"
X
N7 (feedback MSB)
X
X
"
EXTFREQ bit (selected if',!")
X
"
X
X
DO (post-divider LSB)
"
X
X
Dl (post-divider MSB)
X
"
STOPI bit (must be "1"
X
"
X
X. - ~TOP2 bitjrl1us,~ be "1"L_
_
X

FS3
0
I

0
1
0
1
0
1
0
1
0
1
0
I

0
1
0
1
0
I

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
I

0

----

-

I

_~I
I

II

II

ICS2572
Observe that the internal shift register is "clocked" by a transition of FS3 data from "0" to "I." If an extended sequence of
register loading is to be performed (such as a power-on initialization sequence), note that it is not necessary to implement the
50 millisecond delay between them. Simply repeat the sequence above as many times as desired. Writes to the FS port
will not be treated as frequency select data until up to 50
milliseconds have transpired since the last write. Note that FSO
and FSI inputs are "don't care."

DrJ-O]
00
01
10
11

POST-DIVIDER
9
4
2
1

ReadlWrite* Control Bit

Data Description
Location Bits (LO-L4)
The first five bits after the start bit control the frequency
location to be re-programmed according to this table. The
rightmost bit (the LSB) of the five shown in each selection of
the table is the first one sent.

Table 1 - Location Bit Programming
L[4-0]
01100
01101
01110
01111
10010
10011

Table 2 - Post-Divider Programming

When set to a "0," the ICS2572 shift register will transfer its
contents to the selected memory register at the completion of
the programming sequence outlined above.
When this bit is a "1," the selected memory location will be
transferred to the shift register to permit a subsequent readback
of data. No modification of device memory will be performed.
To readback any location of memory, perform a "dummy"
write of data (complete with start and stop bits) to that location
but set the RIW* control bit (make it "I"). At the end of the
sequence (i.e., after the stop bits have been "clocked"), "clocking" of the FS3 input 11 more times will output the data bits
only in the same sequence as above on the FSO pin.

LOCATION
VCLK Address 12
VCLKAddress 13
VCLKAddress 14
VCLK Address 15
MCLK Address 2
MCLK Address 3

EXTFREQ Input

Feedback Set Bits (NO-N7)
These bits control the feedback divider setting for the location
specified. The modulus of the feedback divider will be equal
to the value of these bits + 257. The least significant bit (NO)
is sent first.

The EXTFREQ input allows an externally generated frequency to be routed to the VCLK output pin under device
programming control. If the EXTFREQ bit is set (logic" 1") at
the selected address location (VCLK addresses only), the frequency applied to the EXTFREQ input will be routed to the
VCLKoutput.

Post-Divider Set Bits (00-01)
These bits control the post -divider setting for the location
specified according to this table. The least significant bit (DO)
is sent first.

E-I02

II

ICS2572
The VCO will then need to be programmed to two times 45.723
MHz, or 91.446 MHz. To calculate the required feedback
divider modulus we divide the VCO frequency by the reference
frequency and multiply by the reference divider:

Frequency Synthesizer Description
Refer to Figure 1 for a block diagram of the ICS2572.
The ICS2572 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL. The phase-frequency detector shown in the
block diagram drives the VCO to a frequency that will cause
the two inputs to the phase-frequency detector to be matched
in frequency and phase. This occurs when:

~

91.446 *43-27462
14.31818
.
which we round off to 275. The exact output frequency will
be:

211 *14.31818* ~ =45.784 MHz

where N is the effective modulus of the feedback divider chain
and R is the modulus of the reference divider chain.

The value of the N programming bits may be calculated by
subtracting 257 from the desired feedback divider modulus.
Thus, the N value will be set to 18 (275-257) or 000100102.
The D bit programming is 102 (from Table 2).

The feedback divider on the ICS2572 may be set to any integer
value from 257 to 512. This is done by the setting of the NO-N7
bits. The standard reference divider on the ICS2572 is fixed to
a value of 43 (this may be set to a different value via ROM
programming; contact factory). The ICS2572 is equipped with
a post-divider and multiplexer that allows the output frequency
range to be scaled down from that ofthe VCO by a factor of 2,
4,or8.

The LOAD (or divided dotclock) output frequency will be the
CLK+/CLK- frequency divided by 1,4,5, or 8. The choice of
modulus is a factory option, and is specified along with the
ROM frequencies in the VCLK and MCLK tables by way of
the two-digit suffix of the part number.

Fveo=FxTALl*

Therefore, the veo frequency range will be from 5.976 to
11.906 (257143 to 512/43) of the reference frequency. The
output frequency range will be from 0.747 to 11.906 times the
reference frequency. Worst case accuracy for any desired frequency within that range will be 0.2%.
If a 14.31818 MHz reference is used, the output frequency
range would be from 10.697 MHz to 170.486 MHz.

Programming Example
Suppose that we want differential CLK output to be 45.723
MHz. We will assume the reference frequency to be 14.31818
MHz.
The VCO frequency range will be 85.565 MHz to 170.486
MHz (5.976 * 14.31818 to 11.906 * 14.31818). We will need
to set the post-divider to two to get an output of 45.723 MHz.

LOAD Frequency Selection

Reference Oscillator & Crystal
Selection
The ICS2572 has on-board circuitry to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in parallelresonant (also called anti-resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
ordering crystals.
Crystals characterized for their series-resonant frequency may
also be used with the ICS2572. Be aware that the oscillation
frequency in circuit will be slightly higher than the frequency
that is stamped on the can (typically 0.025-0.05%).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS2572 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.

E-I03

(I

ICS2572
External Reference Sources
An external frequency source may be used as the reference for
the VCLK and MCLK PLLs. To implement this, simply connect the reference frequency source to the XTALI pin of the
ICS2572. For best results, insure that the clock edges are as
clean and fast as possible and that the input voltage thresholds
are not violated.

Power Supply
The ICS2572 has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as close
to the package as is possible.
The ICS2572 has a VOO pin which is the supply of +5 volt
power to all output stages. This pin should be connected to the
power plane (or bus) using standard high-frequency decoupiing practice. That is, use low-capacitors should have low
series inductance and be mounted close to the ICS2572.
The VAA pin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend that
RC decoupling or zener regulation be provided for this pin (as
shown in the recommended application circuitry). This will
allow the PLL to "track" through power supply fluctuations
without visible effects.

E-I04

ICS2572
Absolute Maximum Ratings
Supply voltage .............................. -.5V to + 7V
Logic inputs ................................. -.5V to Voo +.5V
Ambient operating temp ....................... 0 to 70°C
Storage temperature .......................... -85 to + ISO°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

DC Characteristics
PARAMETER
TTL-Compatible Inputs
ICPSO-3, MSO-l STROBE}:
Input High Volta~e
Ini>ut Low Voltage
Input High Current
Input Low Current
Input Capacitance
XTAL1:
Ini>ut High Voltage
Input Low Voltage
CLK+/CLK- Output
Sink Current
High Voltage (Other
Outputs)
@loh=O.4rnA
Low Voltage (Other
Outputs)
@lol=8.0mA

SYMBOL

TEST CONDmONS

MIN

TYP

MAX

UNITS

Vlh
Vil
Ilh
Iii
Cin

2.0
VSS-0.5

VDD+0.5
0.8
10
200
8

V
V
uA
uA
pf

Vxh
Vxl
Isink

VDD*0.75
VSS-O.S

VDD+D.5
VDD*0.25

V
V
rnA

Voh

4

Vol

V

0.4

E-I05

V

ICS2572
AC Characteristics
PARAMETER
Phase-Locked Loop:
VCLK, MCLK VCO
Frequency
PLL Acquire Time
Crystal Oscillator
Crystal Frequency
Ran2e
Parallel Loading
Capacitance
XTALI Minimum High
Time
XTALI Minimum Low
Time
Power SUj>plies:
VDD Supply Current
VAASupply Current
Di2ital Outputs:
CLK+/CLKRecommended
Termination
Other Outputs Rise
Time @ Cload=20pf
Other Outputs Fall Time
@ Cload=20pf

SYMBOL

TEST CONDmONS

Fvco

MIN

TYP

100

Tlock

MAX

UNITS

235

MHz

500

Fxtal

5

uSec
25

20

MHz
pf

Txhi

8

nSec

Txlo

8

nSec

idd
Iaa
50

Tf
Tf

35
10

rnA
rnA

2

ohms

2

nSec
nSec

E·I06

II

!

ICS2572

PATTERN
Reference Divider
VCLKADDR
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MCLKADDR
0
1
2
3

ICS2572-01
43
FbkDivlPostDiv - FVCLK(MHz)
300/1- 99.89
37811 - 125.87
277/1 - 92.24
432/4 - 35.96
30212 - 50.28
340/2 - 56.61
EXTFREQ270/2 - 44.95
40511 - 134.86
38414 - 31.97
330/1 - 109.88
48112 - 80.08
479/4 - 39.87
27012 - 44.95
450/2 - 74.92
39012 - 64.93
FbkDivlPostDiv - FMCLK
48114 - 40.04
270/2 - 44.95
396/4 - 32.97
30012 - 49.95

Ordering Information
ICS2572N-SXX or ICS2572M-SXX (0.300" DIP or sOle Package)
Example:

11

ICS XXXX N-SXX

11'----

S=Strobe OptionIXX=Default Frequencies
Package Type
N=DIP (!'Iasue)
M=SOIC

Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard DeVIce; GSP=Genlock DeVIce

Where:
"s" denotes strobe option:
"xx" denotes default frequencies:

A - positive level transparent (i.e., 2494 interface compatible)
B - negative level transparent
C - positive edge triggered
D - negative edge triggered

E-I07

E-I08

ICS
Communications
Products

This issue of the ICS data book introduces an exciting new family of advanced
physical layer clock recovery and transceiver High Speed Communications products
designed for ATM, SONET, FDDI, Fast Ethernet, and similar local and wide area
network applications.
These new products span both domestic and international transmission frequencies
from 25Mb to 155Mb data rates, offer the advantages of low power CMOS
technology, and bring many innovative features to the designer not found in
competitive solutions. Examples of various product features of this family (ICS1884
through ICS1891) include:
• Integrated on-chip, VCXO, Full Bellcore jitter compliance
• Fully independent, duplex transmit and receive operation
• Selectable clock generation from either recovered or independent source
• Integrated crystal oscillator multiple data rate capability
These innovative features offer the designer a new level of system integration,
performance, and cost effectiveness. ICS has made a significant commitment to this
growing marketplace, and will continue to introduce additional highly integrated
solutions in the months ahead. Look for fully integrated physical layer solutions for
ATM UTP, Fast Ethernet, FDDI, and other applications. Please contact one of our
sales offices for advance information on these exciting, system level integration
products, all using advanced CMOS technology.

F-l

ICS Communications Product Selection Guide
Product
Applications

ICS
Device Type

Description

Package Types

Page

Caller I.D.

ICS1660

Caller I.D. Receiver with
Ring Detect.

18-PinDIP
20-Pin SOIC

F-3

ICS1884

SONET/SDH Clock Recovery
On-Chip VCXO, 511155Mb,
Bellcore compliance.

28-Pin
SOIC

F-15

ICS1885

LANIWAN Transceiver
26, 44, 51, 155Mb.

28-Pin

F-27

ICS1886

LANIWAN Transceiver
32, 34, 97, 139Mb.

28-Pin
SOIC

F-33

ICS1887

FDDIlFast ENET Transceiver
100Mb, Full duplex.

28-Pin
SOIC

F-39

ICS1888

High-Performance Twisted Pair
Communication PHYceiver.

to be
detennined

F-45

ICS1889

l00Base-FX Integrated PHYceiver.

52-PinMQFP

F-47

ICS1890

10Base-T/100Base-TX
Integrated PHYceiver.

52-PinMQFP

F-49

ICSI891

l00Base-TX Integrated PHYceiver
for Repeaters.

52-PinMQFP

F-51

LANIWAN
Communications
Systems

sorc

ADVANCE INFORMATION documents contain information on new products in the sampling or preproduction phase of development. Characteristic data
and other specifications are subject to change without notice.
PRODUCT PREVIEW documents contain information onproducta in the formative or design phase of development. Characteristic data and other specifications
are design goals. les reserves the right to change or discontinue these products without notice.

F-2

•

ICS1660

Integrated
Circuit
Systems, Inc.

Incoming Call Line Identification (ICLID) Receiver
with Ring Detection
Description

Features

The ICS1660 "ICUD" circuit is a monolithic CMOS VLSI
device that decodes and detects the Erequency ~hift Keymg
(FSK) signals used in caller idenufication telephone service.
The ICS1660, when used m conjunction with some external
components, amplifies, filters and demodulates the FSK
data transmitted from the central office to the telephone
subscriber.

•

Ring Detection

•
•

Low Battery DetectIOn
Internal 5V Regulator - can externally source 25mA

•
•
•

FSK Demodulation
Power-down in Standby Mode
Direct Interface to Host Microprocessor or
Microcomputer

The ICS1660 detects the first power ring signal and demodulates the 1200 baud FSK data transmitted during the silent
interval between the first and second power ring. The FSK data
is transmitted from the central office switch to the subscriber
line as part ofthe CLASS service of <;;alling Number Qelivery
(CND). This data is then demodulated, amplified and filtered
by the ICS1660 and digitally transmitted to the host controller/processor.

Applications

The ICS1660 is designed to be powered by any off-the-shelf
9.0 volt battery. The on-chip 5.0 voltage regulator powers the
host microprocessor and any external circuitry supported by
the ICS1660. This portion of the circuit can be overridden by
connecting the VIN pin (18) to the VDD pin (1) for a common
power supply. A low battery detection circuit is also provided
on-chip and signals the microprocessor on the FSKIBAT pin
(17) when the PWR pin (16) input is pulled low.

•

Telephones

•
•

Facsimile Machines
Modems

•
•

Telephone Interface Equipment
Stand-alone ICUD products

ICLID Block Diagram
TO LINE

TO PHONE

Rno Detect
FSK Demodulation
Signal Condltlonmg
Low Battery Detect

Power·down
Standby

Voltage
Regulation

IlCS1660RevA100694

F-3

MicroController

~mpAD
~
~o

Extemal
Memory

{RAM/EPROM{

ICS1660
Block Diagram

.022flF

I

Fl
r--------------------------I

I
I 5

,

- ~--~

--------------"1

15
_ _ _ _ _ _ _-"''+---+--'1,,0_---+"'13'-_

21 RING

3 I POSTF

T

lOW

i'OOQPF

I
I
I
I
PWR 116

: I=
I

~----~-----------------

'~-'--17:

l

~-r---------I

I

I

IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I
~

F-4

FSKBAT"

01flF

500k

ICS1660
Differential Front End

Function Description
Power Supply
The ICS1660 is designed to be powered by a standard 9.0 volt
battery. The chip contains a voltage regulator that powers
external circuitry and provides the supply voltage for all digital
110 on the circuit. This allows easy interface between the
ICS1660 and other standard logic working at 5.OV. This regulator has short circuit protection and requires an external filter/compensation capacitor with a minimum value of lOuf.
In the event that an external regulated 5.OV supply is available,
the VIN and VDD pins can be shorted to permit the entire system
to work from a common supply.
A low battery detection circuit is provided. This circuit is
designed for a typical trip point of 6.0V with hysteresis of about
200mV above the trip point. This signal is low active and is
multiplexed to the FSKBAT output pin when the PWR input
is low.
In an effort to keep power dissipation to a minimum and extend
battery life, most of the analog circuits are turned off when the
circuit is at rest waiting for a ring detect, (PWR pin low).
During this time only the regulator, low battery detect, reference generator, and ring detect circuits are active. When the
PWR pin is high, all circuits are active.

Ring Detect
As shown in the attached block diagram, the LINEA and
LlNEB inputs should be connected to the telephone line
through external 82kQ resistors and 0.1 uf capacitors. This
provides DC isolation and sets up a voltage divider with internal resistors that will detect 35.0V RMS typically. This voltage
is applied across the LINEA and LlNEB inputs. The design
value of the internal resistors is 8.1 KQ ± 20% with relative
accuracy of 2%. The RING output is high active.

As shown in the attached block diagram, the LINEA and
LlNEB inputs go into a differential amplifier which in tum
drives a filter. All resistors are internal to the chip while
capacitors are connected as shown in the block diagram. After
filtering, the signal is AC coupled into a high gain amplifier
that converts the signal to digital. This digital signal in tum acts
as the reference frequency for the phase comparator section of
the phase locked loop.

FSK Demodulation
After the signal from the telephone line has been filtered,
amplified and converted to digital, it acts as an input to a phase
locked loop. This PLL does FSK demodulation. The summing
amplifier shown in the block diagram provides a signal to the
VCO that should be about 0.5V for MARK frequency
(1200 HZ), and 2.0V for SPACE frequency (2200 HZ).
As shown in the block diagram, the LFILTER (loop filter)
output has a post filter attached to it. This POSTF signal is sent
to a comparator. The other side of the comparator is set to
approximately 2.5V. This comparator has a small amount (200
mV) of hysteresis and its output is the demodulated FSK data.
The FSK output is high for MARK frequency and low for
SPACE frequency. FSK data is multiplexed out of the
FSKBAT pin when the PWR input is high.
The VCO frequency is set with one external resistor with a
value in the range of 300K for a center frequency of 1700 HZ.
The lock range will be 660 HZ to 2630 HZ typical. The center
frequency reproducibility will be ±15%. The center frequency
can be adjusted in the system by connecting AMPIN to VSS,
PWR to VDD, and adjusting the external resistor for 1700 HZ.
This frequency can be observed at the LFILTER output or the
FSKIBAT output.

F·5

II

ICS1660
Typical Application

10
TIP

MOV

RING

82k

82k

O.Oll'f
250V

+6V

1

CAL JUMPER
0---

.022l'f

A

8

1-"-----------

1000

FILTER
OUT

POSTF
VRl

6

18

AMP IN

VCOSET

11

12

VDD I-"--~---~----VOUT

VIN
VSS

6V

0.1l'f
300

9.1V
lOOl'f
-

9Voc

F·6

MICRO
CONTROLLER

+/-10%

II

ICS1660

Pin Descriptions
PIN NUMBER
DIP SO

NAME

DESCRIPTION

VDD

Supply voltage pin to external circuits. Output of 5.0 volt regulator.

2

2

RING

Ring detect output signal to the host microprocessor.

3

3

POSTF

Post loop filter signal used by demodulator.

4

4

LFILTER

Loop filter for PLL.

5

5

LINEAFILTER

Filter input from line "A."

6

6

VCOSET

Center frequency adjustment pin.

7

7

LINEA

"Tip" input from telephone line.

8

8

LINEB

"Ring" input from telephone line.

9

9

VSS

Ground.

10

11

FILTER2

Active filter pin.

11

12

FILTEROUT

Active filter pin.

12

13

AMPIN

Input from active filter.

13

14

FILTER3

Active filter pin.

14

15

LINEBFILTER

Filter input from line "B."

15

16

FILTER 1

Active filter pin.

16

17

PWR

Logic input signal to switch from low current standby mode.

17

18

FSKIBAT

Multiplexed output signal controlled by PWR pin. In standby mode, this is a
low battery (active low) signal. During FSK demodulation, this is the data line
to the IJP (mark =high).

18

19

VIN

Input power supply pin.

10

20

NCon SOIC
VDD
RING

2

18

VIN

17

FSICIBAT

POSTF

3

16

PWR

LmTER

4

15

FILTERI

VDD

20
19

NC

RING

2

POSTF

3

18

FSKIBAT

LmTER

4

17

PWR

LlNEAFILTER

5

16

FlLTERI

VCOSET

6

15

L1NEBFlLTER

VIN

LlNEAFILTER

S

14

LINEBFILTER

VCOSET

6

13

FILTER3

LINEA

7

12

AMPIN

LINEA

7

14

FlLTER3

L1NEB

8

11

FILTEROUT

L1NEB

8

13

AMPIN

VSS

9

10

FILTER2

9
10

12

FlLTEROUT

11

FlLTER2

VSS

NC

18 PIN
DIP

20 PIN

K-4

K·'

sOle

F·'

II

ICS1660
Analog

Input/Output Specifications
Digital
RING and FSKBAT outputs are standard CMOS outputs with
voltage swings between Vss and Voo.
PWR is a logic input. A level converter circuit is on chip to
allow the logic signal that swing between Vss and Voo to be
internally converted to signals that swing between V ss and
VIN. It should be noted that to minimize power consumption
caused by through current in logic gates, the PWR input should
always swing to within 100 mV of Vss or Voo. The PWR
input signal is low when the ICSl660 is in lower power mode
waiting for an incoming call.
The LFILTER output is a standard CMOS output powered
from VDD. This output has an internal resistor with a typical
value of 30kQ. This is used in conjunction with the external
capacitor shown in the block diagram to form the loop filter for
thePLL.

The value of the ring detect is as previously discussed 3S.0V
RMS typical. The actual value is set by the choice of the
external resistors that are connected to the LINEA and LINEB
inputs. The matching of these resistors to the internal 8.1kQ
resistors is also a factor. The signal level at the chip that will
cause a ring is the bandgap voltage, (1.2SV) or below.
The chip is designed for an input signal level of -12.Sdbm to
-28.Sdbm into 900 ohms. This translates to a Signal that is
between 100 mV and 636 mV peak to peak.
The filter section should be connected as shown in the block
diagram. Using the external capacitors as shown, and assuming
nominal values on the internal resistors, the comer frequencies
are 900 HZ and 3860 HZ.
An external resistor with a value of approximately 330kQ is
connected between the LFILTER and POSTF pads. This resistor along with the external capacitor shown in the block diagram form the post filter. This post filter is used in conjunction
with the comparator to do the FSK demodulation.

Absolute Maximum Ratings*
(VoJtages referenced to Vss)

Supply Voltage . . . . . . . . VIN
Voltage at any Input . . . . .
Operation Temperature Range
Storage Temperature Range . .

*

-O.SV to + lOV
-O.5V to Voo + O.SV
-SsoC to +12SoC
-SO°C to lS0°C

Absolute maximum ratings are those values beyond which the safety of this device cannot be guaranteed.
These values are NOT RECOMMENDED operating conditions.

F-8

II

ICS1660

DC Characteristics
VIN = 4.5V - 1O.0V; TA = 0 DC - 70 DC, Recommended Operating Range
PARAMETER

MIN

TYP

MAX

UNITS

Standby Current

SYMBOL
lIN

PWR LOW, VIN =9.0V,
IDD=2UA

-

20

30

uA

Active Current

lIN

PWR HIGH, VIN=9.0V
VCOSET=300k

-

-

10

rnA

4.5

5.0

5.5

Volts

Regulator Output Voltage

VDD

Regulator Output Current

IDD

Regulator Dropout

VIN

Low

CONDITIONS

Output Current

2.0
0.5

Batte~ Detect

Low Battery Detect - Hysteresis

Low Battery Detect
Hysteresis

25.0

rnA

1.0

Volts

6.0

Volts

200

mV

OUTPUT CURRENTSINKISOURCE
Ring Source Current

lOUT

YOUTH = VDD - 0.5V

-500

-

-

uA

FSKBAT and Ring Sink
Current

lOUT

VOUTL = Vss + OAV

-

-

500

uA

F-9

II

ICS1660
ICLID Process Flowchart
(for Microprocessor and ASIC (lCS1660) Interface)

MICROCONTROLLER
IN STANDBY/SLEEP
MODE

YES

YES

MICROCONTROLLER
WAKES UP
TURNS ON POWER
TO
ASIC (PWR) AT END
OF RING

MICROCONTROLLER
LOOKS FOR
CHANNEL SEIZURE
FROM ASIC (FSK)
DURING SILENT
PERIOD

YES

MICROCONTROLLER
WAKES UP
AND PROCESSES
KEYPAD INTERRUPT
NO

MICROCONTROLLER
PROCESSES DATA
AND TURNS OFF
(PWR)

DISPLAYS
INFORMATION
AND TIMES OUT

NO

YES

DISPLAYS
ERROR MESSAGE
AND THEN TIMES OUT

F·I0

DISPLAYS
INFORMATION
AND STORES DATA
AND THEN TIMES OUT

II

ICS1660

Ordering Information
ICS1660N or ICS1660M
Example:

ICSXXXX M

TL-____

Package Type
N=DIP (I'lastlc)
M=SOIC

L-______
L-_________

Device Type (consists of 3 or 4 digit nnmbers)
Prefix
ICS, A V=Standard DevIce, GSP=Genlock DevIce

F·ll

F-12

Integrated
Circuit
Systems, Inc.

DB1660

ICS1660 ICLID Demonstration Board
Overview

Features

The DB1660 ICLID demonstration board is intended to be
used to demonstrate the function of the ICS1660 Incoming
Call Line Identification Receiver IC.It provides a full-function
incoming call display unit to verify the proper function of the
ICS1660 ICLID device.

• Fully functional system permits verification of results
obtained in a product application.
• Displays ICLID function without extensive design effort.

NOTE: The only device that Integrated Circnit Systems
Inc. is able to supply is the ICS1660. The other semicon·
ductor devices and the display used on this board are
proprietary designs and are not available from ICS.

Operation
To use the ICS1660 ICLID demo board, install a 9 volt alkaline
battery in the battery clip on the board, and attach the battery
connector. Facing the connector end of the board with the
board "battery side up," the RJ 11 connector on the right should
be connected to a standard modular phone jack. The connector
at the center of the board may be connected to the telephone
instrument removed from the modular connector. Tum the
board over so that the display is facing up and the two push
buttons are toward you. Assuming that caller ID is available in
your area, when your telephone begins ringing, the display will
show the telephone number of your caller. After 20 seconds
the display will return to its normal (blank) mode and the
number will be stored in memory as the most recent call. When
someone calls you from an area where the telephone company
is not offering caller ID service or an area that is not yet
providing caller ID information via the long distance network,
the display will say "OUT-OF-AREA." In some areas, the
calling party may be able to block their number from appearing
on your call display. In this case, the display will say "PRIV ATE." If the DB1660 receives garbled data, a "?" will appear
in every digit location that has unrecognized numbers. If all
digits are garbled, the display will read "ERROR" but will not
be stored in memory. In some areas, the local phone company
will send a long-distance indicator which will show as an "L"
on the display either with or without the incoming number.

Pushbutton Functions
Two pushbuttons exist on the DB 1660 board. The button to the
left when facing the board, display up and buttons toward you
is the TIME button. The button to your right is the REVIEW
button. When the REVIEW button is pressed the phone number of the most recent call will be displayed. Each additional
time the REVIEW button is pressed (within 20 seconds) the
next most recent call is displayed. When the last call stored in
memory has been reviewed, the next press of the REVIEW
button will display "END."

If REVIEW is pressed again within 20 seconds, it will bring

you back to the start of the memory list and the most recent call
will be displayed. If more than 20 seconds have elapsed before
the REVIEW button is pressed, the display will blank and the
next time REVIEW is pressed the most recent call will be
displayed.
The time and date of an incoming call can be viewed by first
pressing the REVIEW button until the selected number is
displayed, and then pressing the TIME button. If the TIME
button is pressed again within 20 seconds, the telephone number will again be displayed. This allows the TIME button to
be used as a toggle between the telephone number and the
date/time of the particular call.
NOTE: The REVIEW and TIME buttons are not operative
during the interval when a new incoming phone number is
being received.
When the ten call memory of the DB1660 is full, the oldest call
will automatically be epsed to make room for the next call that
comes in. To manually remove all calls, press the TIME button
while the REVIEW button is pressed. This will also cause all
the segments of the LCD display to be visible for as long as
both of these buttons are pressed.

IDB1660RevA091294

F·13

F-14

ICS1884

Integrated
Circuit
Systems, Inc.

•

Advance Information

SONET/ATM TeleclockTM Recovery/Generator Unit
General Description

Features

The ICS1884 Teleclock is designed to provide high perfonnance clock recovery and generation for either 51.84 Mbitls
OC/STS-l or 155.52 Mbitls OC/STS-3/STM-l SONET/SOH
and ATM applications. The ICS1884 meets Bellcore TR-

•
•

NWT-000253 requirements for jitter tolerance and jitter
transfer and is ideal for loop timing applications.

•

In the clock recovery mode, the ICS1884 receives the
51.84 Mbitls or 155.52 Mbitls, NRZ or NRZI data stream and
extracts the bit clock from this data. The chip uses differential
PECL to output the regenerated data along with two bit clocks.
A 6.48 MHz or 19.44 MHz reference byte clock is also available on a TTL output. System clock generation (loop timing)
can be achieved simultaneously by utilizing the second pair of
clock outputs. Using this method, the incoming data clock
frequency is utilized as the transmit clock.

•
•
•
•
•
•

Internal VCXO
Supports clock generation for either 51.84 Mbit/s
OC/STS-l or 155.52Mbit/s OC/STS-3/STM-l
SONET/SOH and ATM applications
Provides continuous clock output if loss of input data
stream
Bellcore jitter compliance (tolerance and transfer)
Supports clock recovery for 51.84 Mbitls or 155.52 Mbitls
NRZINRZI data
Complies with ANSI, Bellcore, and CCITT specifications
Lowest power CMOS technology: Pd=250mW typical at
155 MHz
Lock detect output monitors transition density and run
length
Available in space-saving 28-pin SOIC

The ICS1884 can also be used as a high performance
51.84 MHz or 155.52 MHz system clock generator by utilizing
the VCXO free run mode.

Applications

The ICS1884 utilizes advanced CMOS phase-locked loop
technology which combines high perfonnance and low power
at a greatly reduced cost.

•

•

•
•
•
•

Block Diagram

SONET and ATM applications which require loop timing
operation
Wide area network (WAN) Bellcore compliant applications such as SONET STS-3 and SOH STM-l
51.84 Mbitls or 155.52 Mbitls ATM UNI
SONET AddIDrop Multiplexers, Tenninal Multiplexers,
and Regenerators
Line timing, loop timing and through-timing applications
Consult ICS for other bit rate application (e.g., 25.6Mb,
100Mb, etc.)

r------------------~
I
r-_ _ _ _

-II .........---..l-1/......- ; - -

I

MSELO
MSEL1

PWRDWN

DATA OUT-

r - - - - - - 1 "",..--,-----a ACLK OUT+

1.......' - -........-.., ACLK OUTr-____r~---:---30pf
Fundamental
350
10-20 ppm
0-70°C

Suggested Crystal Manufacturers
•
•

MIN
2.0

Fox Crystal, Ft. Myers, FL (813) 693-0099
Pletronics, Lynnwood, WA (206) 776-1880

F·19

II

II

ICS1884
AC Characteristics
(VDD = VMIN to VMAX, Vss = OV, TA = TMIN to TMAX)
PARAMETER
Nominal Center Frequency
Tracking Range
Capture Range
Acquisition Time
Bit Error Rate, BER
Output Jitter Generation

Jitter Tolerance *see plot

Jitter Transfer *see plot
Peaking
Bandwidth
Recovered Clock Output
Duty Cycle
DT=1I2
If EXT VCXO REF is used:
Reference Clock Input
Frequency Tolerance
Reference Clock Input
Jitter Tolerance
If EXT VCXO REF is used:
Reference Clock Input
RiselFall Time
Reference Clock Input
Duty Cycle
If EXT VCXO REF is used:
TTL Output Rise Time
TTL Output Fall Time
Transitionless Data Run
(Loss of Data)

CONDITIONS
OC/STS-1
OC/STS-3
Minimum Data Transition
Density, DT = 115
Minimum DT = 115
From loss of signal or no
signal to DT = 112
Minimum UI of 30% of
data bit time
D,= 112
2231 PRBS
2 -lPRBS
f= 10Hz
f= 30Hz
f= 300 Hz
f= 6.5 kHz (OC-3), 2kHz (OC-I)
f = 65 kHz (OC-3), 20kHz (OC-I)

MAX

UNIT
MHz

-100

100

ppm

-100

100

ppm

1 x 10- 12

/..ls
BER

MIN

TYP
51.84
155.52

20

0.01
0.01
0.01
15
15
1.5
1.5
0.15

dB

0.1
130
40

kHz
kHz

48

52

%

-100
-20
14

100
20

p~m

OC-3
OC-1

Clock Recovery Mode
Clock Synthesis Mode
Clock Synthesis Mode,
Input Jitter from 12 kHz to
1 MHz

UIrms
UIrms
UIrms
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p

ppm
psrms

10%-90%

CLOAn=2Opf,10%-90%
CLOAD=20pf, 90%-10%

2.0

ns

45

55

%

2.0
2.0

6.0
6.0

ns
ns
bit periods

244

Note: Consult ICS for external VCXO operation.

F·2D

II

ICS1884
ICS1884 OC/STS-3 JITTER TRANSFER

01 dB
BELLCClRE

¥

TR-NWT-000253

JITTER XFER
LIMIT
ICS1884 JITTER TRANSFER (ENLARGED SCALE)
01dB~----~--~----------~

-19 9 dB
-04dB

o

o
o

o

""

""

.::<:

.::<:

.::<:

l!)

""

o(X)

o

N

FREQUENCY (Hz)

' 15

I-

:::i 10

a..

::2:

«

BELLCORE TR-NWT-000253
JITTER TOLERANCE LIMIT

06

015

J

BAUD=51 84 Mb/s

o

'"

o
o

'"o
N

FREQUENCY (Hz)

F-22

""0

'"
N

""

'"
ID

::;;::;;
~

M

ICS1884
Jitter Transfer Test Setup

EXT REi

Microwave
Logic
SJ-300
Jitter Generator

,

SOI+ ..
Microwave
Logic

,

SOI-

ICS1884

,...

SOO+..

,

SOO- ...

,

..

ACLK+

gigaBERT-1400T,

Microwave
Logic
SJ-300
Jitter Analyzer

,

ACLK..

,

Jitter Tolerance Test Setup

EXTRE[

Microwave
Logic
SJ-300
Jitter Generator

,

Microwave
Logic

SOI+

.,

SOI-

,.

..

ICS1884

SDO+
SDO-

,~
..

,.

ACLK+ ..

gigaBERT-1400T,

,

ACLK- ..

,.

F-23

Microwave
Logic
gigaBERT -1400-DR,

II

ICS1884
Outputs

Functional Description
Clock Recovery Mode
In the clock recovery mode, the ICS1884 supports clock and
data recovery for either OC/STS-I or OC/STS-3/STM-Iline
rate. ECL differential NRZ serial data is input to the ICS1884
at either 51.84 Mb/s or 155.52 Mb/s rate. Clock and data
recovery is performed on this incoming data stream. Regenerated serial data and recovered clock are output from the
ICS1884 as differential ECL. A 10.53 MHz crystal is required
to properly operate the internal VCXO for this mode of operation.

Pin Descriptions
Inputs
Serial Data Differential ECL (SOI+ and SOI-)
In the clock recovery mode, input from which recei ve bit clock
is recovered and receive data is regenerated when MSELI is
high or unconnected. In the clock synthesis mode, one input
should be connected to VDD with the other input connected to
VSS.
Serial Loop Differential ECL (SDL+ and SDL-)
In the clock recovery mode, input from which transmit bit clock
is recovered and transmit data is regenerated when MSELI is
low. In the clock synthesis mode, one input should be connected
to VDD with the other input connected to VSS.
External Crystal or Reference Clock (XTALI and XTAL2)
In the clock recovery mode, a 10.53 MHz crystal with associated capacitors should be connected to these pins. In the clock
synthesis mode, either a 10.53 MHz input reference frequency
or crystal should be connected to these pins. The reference
signal can use either PECL or TTL-compatible levels. For
PECL levels, the differential signal is simply connected to
XTALl and XTAL2. A TTL type reference is input at XTALl
with XTAL2 left open.
Mode Select (MSELO and MSELl)
Selects the operating mode and frequency. See Table 1. Internal pull-ups set both inputs high when unconnected.

Serial Data Differential ECL (SDO+ and SDO-)
In the clock recovery mode, this is the regenerated data derived
from the serial data input which is phase-aligned with the clock
output.
A Clock Differential ECL (ACLK+ and ACLK-)
In the clock recovery mode, this is the 51.84 MHz or
155.52 MHz clock which is phase-aligned with the serial data
output. In the clock synthesis mode, this is the 51.84 MHz or
155.52 MHz clock derived from the reference clock input.
B Clock Differential ECL (BCLK+ and BCLK-)
In the clock recovery mode, this is the 51.84 MHz or
155.52 MHz bit clock which is phase-aligned with the serial
data output (typically used for loop timing applications). In the
clock synthesis mode, this is the 51.84 MHz or 155.52 MHz
clock derived from the reference clock input.
Reference Clock (REFCLK)
This output will be either a 6.48 MHz or 19.44 MHz clock
derived from the 51.84 MHz or 155.52 MHz bit clock.
LockILoss Detect (LOCK)
Set high when the clock recovery has locked onto the incoming
data. Set low when there is no incoming data, which in turn
causes the VCXO to free run. This signal can be used to indicate
or 'alarm' the next receive stage that the incoming serial data
at SDI± has stopped (Loss Detect).

Output Description
The differential output drivers are current mode and are designed to drive resistive terminations in a complementary fashion. The outputs are current-sinking only, with the amount of
sink current programmable via the IPRG pin. The sink current,
which is steered to SDO, ACLK and BCLK is four times the
current supplied to the IPRG pin. For most applications, a
resistor from OVDD to IPRG will set the current of the necessary precision.

VCXO Free Run (FREEn)
Active low input which, when in the clock recovery mode,
forces the internal VCXO to free run. For clock synthesis mode
operation, this input should be connected to VSS.
Power Down (PWRDNn)
Active low input which stops all operations and puts the
ICS1884 into a low power sleep mode.
VCXO External Loop Filter (FVCXO)
External VCXO loop filter connection.
VCO External Loop Filter (FVCO)
External VCO loop filter connection.

F-24

II

ICS1884

Definition of Terms
Tracking Range
The range of input data rates over which the PLL will remain
in lock.
Capture Range
The range of input data rates over which the PLL can acquire
lock.

Jitter Transfer
The PLL exhibits a low-pass filter response to jitter applied to
its input data.
Bandwidth
The frequency at which the PLL attenuates sinusoidal input
jitter by 3dB.
Peaking
The maximum jitter gain of the PLL in dB.

Acquisition Time
The transient time required for the PLL to lock on input data
from its free-running state.
Static Phase Error
The steady-state phase difference between the recovered clock
sampling edge and the optimum sampling instant. This optimum instant is assumed to be halfway between the rising and
falling edges of data bit.

XTAL1
XTAL2

Data Transition Density
The ratio of data transitions (i.e. 0 to I, 1 to 0) to clock periods.
O:S:DT:S: 1

V
CO
CO

Jitter
The dynamic displacement of digital signal edges from their
long-term average positions.

~

en

FVCXO

19

17

I

•

V DD

•

V DD

C1

()

Output Jitter
This is the jitter on the re-timed data due to a specific or some
pseudo-random input data sequence PRBS.

22pF

20

FVCO

27
C2

W(;

R1

Jitter Tolerance
The measure of the PLL's ability to track a jittered input data
signal.

Ordering Information

Suggested Crystal & Loop Filter
Component Values

ICS1884M
Example:

MODE
OC/STS-l
OC/STS-3

ICSXXXX M

1~1~,~~

Device lYpe (consists of 3 or 4 digit numbers)
'-----Prefix
ICS, AV=Standard Device; GSP=Genlock Device
ADVANCE INFORMATION documents contain Information on new products In the sampling
or preproduction phase of development CharactenstlC data and other specifications are
sub eet to chan e without notice

F-25

CI
470pF
150pF

C2
4.7uF

RI
IkQ

.681lF

1.8kQ

Ii

F·26

•

ICS1885

Integrated
Circuit
Systems, Inc.

Product Preview

High-Performance Communications PHYceiver™
General Description

Features

The ICS1885 is designed to provide high performance clock
recovery and generation fur either 25.92 MHz, 44.736 MHz,
51.84 MHz, or 155.52 MHz NRZ or NRZI serial data
streams. The ICS1885 is ideally suited fur LAN transceiver
applications in either SONET, ATM, FDDI or Fast Ethernet
environments.

•

Clock and data recovery is performed on an input serial data
stream or the buffured transmit data depending upon the state
of the loopback input A continuous clock source will continue
to be present even in the absence of input data. All internal
timing is derived from either a low cost crystal, differential or
single-ended source.

The ICS1885 utilizes advanced CMOS phase-locked loop
technology which combines high performance and low power
at a gteatly reduced cost.

Block Diagram

Data and clock recovery for:

25.92 MHz (OC)n)
44.736 MHz (T3 & DSJ)
51.84 MHz (OC-l & SI'S-1)
155.52 MHz (OC-3 & STS-3)
•
•
•
•
•
•
•
•

Clock multiplication from either a crystal, differential or
single-ended timing source
Continuous clock in the absence of data
no external PLL components
Lock/Loss status indicator output
Loopback mode for system diagnostics
Selectable loop timing or independent timing modes
PECL drivers with settable sink current
Meets Bellcore TR-NWT-000253 jitter tolerance requirements

Pin Configuration
REF< REF·

LT-

TC+

VSS
LTCDTX+
TXVSS
IPRGl
RXRX+
LBLOCK
CSl
CSO
VSS

TC-

lX< (J}-"'7'1

TO+

lX.(J)-~

TO-

RcRCRX+

RO+

RX-

RI).

LB_m-----...I
CD-(f)o---------'

LOCK

TD+
TDTC+
TCVDD
REFREF+
VDD
RCRC+
RDRD+
VSS
IPRG2

28-Pin sOle
K-7

ICS1885

IICS1BB6RevAI20284

PHYcoiver ... trademark of Integrlted Clrcut Systenw. Inc.

F-27

Ii

II

ICS1885
Table 1 - Device Clock Selection

CSI

CSO

LOOP

VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD

VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD

VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD

CLOCK
RECOVERY
INPUT
Tx Data
Tx Data
ITx Data
Tx Data
Rx Data
Rx Data
Rx Data
RxData

CLOCKFREQ
25.92 MHz
44.736 MHz
51.84 MHz
155.52 MHz
25.92 MHz
44.736 MHz
51.84 MHz
155.52 MHz

REFFREQor
CRYSTAL

MODE
OC-l/2
T3IDS3
OC-lISTS-l
OC-3/STS-3
OC-l/2
T3IDS3
OC-lISTS-I
OC-3/STS-3

I

3.24 MHz
5.592 MHz
6.48 MHz
19.44 MHz
3.24 MHz
5.592 MHz
6.48 MHz
19.44 MHz

Pin Descriptions
PIN NUMBER
I
2
3
4
5
6
7
8
9
10

11

----.

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

PIN NAME
VSS
LTCDTX+
TXVSS
IPRGl
RXRX+
LBLOCK
CSI
CSO
VSS
IPRG2
VSS
RD+
RDRC+
RCVDD
REF+
REFVDD
TCTC+
TDTD+

TYPE

DESCRIPTION
Negative supply voltage
Loop Timing mode select*
Carrier Detect input*
Positive Transmit serial data output
Negative Transmit serial data output
Negative supply voltage
PECL Output stage current set (TX)
Negative Receive serial data input
Positive Receive serial data input
Loop Back mode select*
Lock detect output
Clock select I input
Clock select 0 input
Negative supply voltage
PECL Output stage current set (TC. RC and RD)
Negative supply voltage
Positive recovered data output
Negative recovered data output
Positive recovered clock output
Negative recovered clock output
Positive supply voltage
Positi ve reference clock/crystal input
Negative reference clock/crystal input
.Positive supply voltage
Negative Transmit clock output
Positive Transmit clock output
.Negative Transmit data input
Positive Transmit data input

* Active Low Input.

F·28

II

ICS1885

Absolute Maximum Ratings
VDD (measured to Vss) .......................
Ambient Operating Temperature ................
Storage Temperature ..........................
Junction Temperature .........................
Soldering Temperature ........................

7.0V
-55 to 125°C
-65 to 150°C
175°C
260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in tbe operational sections of
tbe specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Recommended Operating Conditions
PARAMETER

SYMBOL

Ambient Operating Temp.
Using a Negative Supply

TEST CONDITIONS

TA
Vss
VDD
Vss
VDD

Using a Positive Supply

MIN

MAX

UNITS

0
-4.95
0.0
0.0
+4.75

+70
-5.45
0.0
0.0
+5.25

°C
V
V
V
V

ICS1885 SONET/SOH to ATM Interface (Example)

LOOPTIMED OR
INDEPENDENT
TxCLOCK ..

[
[

FIBER OR COPPER
MEDIA INTERFACE

FIBER OR COPPER
MEDIA INTERFACE

..

.....

,

BUFFERED
Tx DATA

ICS1885

RxDATA ..

SONET/SDH
Transceiver

..

CARRIER'
DETECT ....

TxDATA

RECOVERED
RxCLOCK ...
RECOVERED'
RxDATA

,...

,

LOCK

~[]~

CRYSTAL OR
EXTERNAL REFERENCE

F-29

SONET/SOH
toATM UNI
Processor

..
IgTWAG-013
PMG-Slerra PM5345
or NEG IPD98402

~

ICS1885
DC Characteristics
(Voo = VMIN to VMAX, VSS = OV, TA = TMIN to TMAX)
CONDITIONS

PARAMETER

Voo=+5.0V, Vss=o.OV
EeL Input/Output

PARAMETER
ECL Input High Voltage
ECL Input Low Voltage
ECL Output High Voltage
ECL Output Low Voltage

SYMBOL

CONDITIONS

VIH
VIL
VOH
VOL

MIN

MAX

UNITS

Voo -1.16
Voo - 1.81
Voo - 1.02

Voo - 0.88
VOD - 1.47
VOD-1.62

V
V
V
V

MAX

UNITS

TTL Input/Output
PARAMETER
TTL Input High Voltage
TTL Input Low Voltage
TTL Output High Voltage
TTL Output Low Voltage
TTL Driving CMOS,
Output High Voltage
TTL Driving CMOS,
Output Low Voltage
TTIlCMOS Output
Sink Current
TTUCMOS Output
Source Current

SYMBOL

CONDITIONS

MIN

VIH
VIL
VOH
VOL
VOH

VDD=5V, VSS=OV
VDD=5Y, VSS=OV
VDD=5V, VSS=OV
VDD=5V, VSS=OV
VDD=5V, VSS=OV

VOL

VDD=5Y, VSS=OV

0.4

V

IOL

VDD=5V, VSS=OV

8

rnA

IOH

VDD=5V, VSS=OV

-0.4

rnA

F·30

2.0
0.8
2.7
0.5
3.68

V
V
V
V
V

II

ICS1885

Input Pin Descriptions

Output Pin Descriptions

Transmit Data Input (TD+ and TD-)
For normal operation this differential input is transferred to the
TX± output through a PECL buffer. In loopback testing mode,
this input is multiplexed to the input of the device clock
recovery section.

Transmit Data Differential ECL (TX+ and TX-)
This differential output is buffered TD± data. This output
remains active during loopback mode.

Receive Data Input (RX+ and RX-)
The clock recovery and data regenerator from the receive
buffer are driven from this PECL input. During loopback
testing mode this input is ignored.

Transmit Clock Differential ECL (TC+ and TC-)
Differential output clock used by the SONET/SDH-ATM processor for clocking out transmit data. This clock can be derived
from either an independent clock source or from the recovered
data clock (system loop time mode).

Clock Select (CSO and CSl)
Selects the operating frequency according to Table I. Internal
pull-up resistors set both inputs high when left unconnected.

Receive Data Differential ECL (RD+ and RD-)
The regenerated differential data derived from the serial data
input. In loopback mode this data is regenerated from the
transmit data input (TD±). This data is phase-aligned with the
negative edge of the RC clock output.

Carrier Detect (CD-)
Active low input which forces the VCO to free run. Upon
receipt of a loss of input signal (such as from an optical-to-electrical transducer), the internal phase-lock loop will free-run at
the selected operating frequency. Also, when asserted, CD will
set the lock output low.

Receive Clock Differential ECL (RC+ and RC-)
The differential clock recovered with the internal clock recovery PLL. In loopback mode this clock is recovered from the
transmit data (TD±) input.

Loop Timing Mode (LT -)
Active low input which routes the recovered receive clock to
the TC± outputs as well as the RC± outputs. Forces the transmit
clock to be 'loop-timed' to the system clock derived from the
incoming data.
Loopback Mode (LB-)
Active low input which causes the clock recovery PLL to
operate using the transmit TD± input data and ignore the
receive RX± data. Utilized for system loopback testing.
External Crystal or Reference Clock (REF + and REF -)
This oscillator input can be driven from either a fundamental
mode crystal or a stable reference. For either method, the
reference frequency is l/g the operating frequency.

LockILoss Detect (LOCK)
Set high when the clock recovery PLL has locked onto the
incoming data. Set low when there is no incoming data, which
in tum causes the PLL to free-run. This signal can be used to
indicate or 'alarm' the next receive stage that the incoming
serial data has stopped.

Output Description
The differential output drivers are current mode and are designed to drive resistive terminations in a complementary fashion. The outputs are current-sinking only, with the amount of
sink current programmable via the IPRGx pins. The amount
of sink current is equal to four times IPRGx current. For most
applications, a resistor from VDD to IPRGx will set the current
to the necessary precision. IPRG 1 supplies the current minor
for the TX± output. IPRG2 supplies the current mirrors for the
RD±, RC± and TC± outputs.

F-31

II

ICS1885
Ordering Information
ICS1885M
Example:

ICSXXXX M

-[L,~~
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard DevIce; GSP=Genlock Device
PRODUCT PREVIEW documents contam mformatlon on products In the formative or design
phase of development Characteristic data and other specifications are design goals. ICS
reserves the right to change or discontinue these products without notice

F·32

II

ICS1886

Integrated
Circuit
Systems, Inc.

Product Preview

High-Performance Communications PHY ceiver™
General Description

Features

The ICS1886 is designed to provide high performance clock
recovery and generation fur either 32.064 MHz, 34.368 MHz,
97.728 MHz or 139.264 MHz NRZ or NRZI serial data
streams. The ICS1886 is ideally suited fur LAN transceiver
applicatioos in either European or Japanese communication

•

environments.

•

Clock and data recovery is perfurmed on an input serial data
stream or the buffered transmit data depending upon the state
of the loopback input. A continuous clock source will continue
to be present even in the absence of input data. All internal
timing is derived from either a low cost crystal, differential or
single-ended source.

The ICS1886 utilizes advanced CMOS phase-locked loop
technology which combines high perrormance and low power
at a greatly reduced cost.

Block Diagram
CSO

CSI

Data and clock recovery for:
32.064 MHz (Japan)
34.368 MHz (Europe - FJ)
'J7.728 MHz (Japan)

139.264 MHz (Europe - E4)
•
•
•
•
•
•

Clock multiplication from either a crystal, differential or
single-ended timing source
Continuous clock in the absence of data
No external PLL components
Lock/Loss status indicator output
Loopback mode for system diagnostics
Selectable loop timing mode
PECL drivers with settable sink current

II
Pin Configuration

REF+

REF·

LT-

Te+

VSS
LTCDTX+
TXVSS
IPRG1
RXRX+
LBLOCK
CS1
CSO
VSS

TC-

TX+(J)--'71

lO+

TX.(J)--~

Tl).

RC+

RC-

RX+tn.-.........
RD+

RXR[)'

LS-ffi------....

~-fi}------~

LOCK

TD+
TO·
TC+
TCVDD
REFREF+
VDD
RC·
RC+
RD·
RD+
VSS
IPRG2

28-Pin sOle
K-7

ICS1886

PHYcolvor I•• trademark of Integrated Circuit Systems, Inc.

IICSI888RevAI20284

F-33

II

ICS1886
Table 1 - Device Clock Selection
CS1

CSO

LOOP

VSS
VSS
VDD
VDD

VSS
VDD
VSS
VDD

VSS
VSS
VDD
VDD

VSS
VDD
VSS
VDD

VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD

INPUT
RxData
RxData
RxData
RxData
TxData
TxData
TxData
TxData

CLOCKFREQ
32.064 MHz
34.368 MHz
97.728 MHz
139.264 MHz
32.064 MHz
34.368 MHz
97.728 MHz
139.264 MHz

MODE
Japan
Europe -E3
Japan
Europe-E4
Japan
Europe - E3
Japan
Europe -E4

REFFREQor
CRYSTAL
4.008 MHz
4.296 MHz
12.216 MHz
17.408 MHz
4.008 MHz
4.296 MHz
12.216 MHz
17.408 MHz

Pin Descriptions
PIN NUMBER
1

2
3
4

PIN NAME
VSS
LTCD-

DESCRIPTION

TYPE

Negative supply voltage
Loop Timing mode select*
Carrier Detect input*
Positive Transmit serial data output
Negative Transmit serial data output
Negative supply voltage
PECL Output stage current set (TX)

7
8

TX+
TXVSS
IPRGl
RX-

9
10
11

RX+
LBLOCK

12
13
14
15
16
17

CS1
CSO
VSS

Clock select 1 input

IPRG2
VSS
RD+
RD-

PECL Output stage current set (TC, RC and RD)
Negative supply voltage

5
6

18
19
20
21
22
23

24
25
26
27
28

RC+
RCVDD
REF+
REFVDD
TCTC+
TDTD+

Negative Receive serial data input
Positive Receive serial data input
Loop Back mode select*
Lock detect output
Clock select 0 input
Negative supply voltage

Positive recovered data output
Ne~ative recovered data output
Positive recovered clock output
Negative recovered clock output
Positive supply voltage
Positive reference clock/crystal input
Negative reference clock/crystal input

Positive supply voltage
Negative Transmit clock output
Positive Transmit clock output
Negative Transmit data input
Positive Transmit data input

* Active Low Input.

F-34

ICS1886
Absolute Maximum Ratings
Voo (measured to Vss) .......................
Ambient Operating Temperature ................
Storage Temperature ..........................
Junction Temperature .........................
Soldering Temperature ........................

7.0V
-55 to 125°C
-65 to 150°C
175°C
260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Recommended Operating Conditions
PARAMETER

SYMBOL

Ambient Operating Temp.
Using a Negative Supply
Using a Positive Supply

TEST CONDITIONS

TA
Vss
Voo
Vss
Voo

MIN

MAX

UNITS

0
-4.95
0.0
0.0
+4.75

+70
-5.45
0.0
0.0
+5.25

°C
V
V
V
V

ICS1886 SONETISDH to ATM Interface (Example)

LOOPTIMED OR
INDEPENDENT
TxCLOCK

[

FIBER OR COPPER
MEDIA INTERFACE

•
.....

BUFFERED
TxDATA

.

ICS1886

,

TxDATA

~

PDH to
RECOVERED
RxCLOCK

PDH
RxDATA ...

[

FIBER OR COPPER
MEDIA INTERFACE

Transceiver

CARRIER ,.
DETECT ...

RECOVERED'
RxDATA

...,.

,.
LOCK

~[]~

CRYSTAL OR
EXTERNAL REFERENCE

F·35

ATM UNI

..,.

Processor

~

ICS1886
DC Characteristics
(Voo = VMIN to VMAX, VSS = Ov, TA = TMIN to TMAX)
PARAMETER

CONDITIONS

Supply current

VDo=+5,OV, VSS=O,OV

ECL Input/Output
PARAMETER
ECL Input High Voltage
ECL Input Low Voltage
ECL Output High Voltage
ECL Output Low Voltage

SYMBOL

CONDITIONS

VIH
VIL
VOH
VOL

MIN

MAX

UNITS

Voo - 1.16
Voo - 1.81
Voo -1.02

Voo - 0,88
Voo - 1.47
Voo - 1.62

V
V
V
V

MAX

UNITS

TTL Input/Output
PARAMETER
TTL Input High Voltage
TTL Input Low Voltage
ITTL Output High VoltaEe
ITTL Output Low Voltage
TTL Driving CMOS,
Output High Voltage
TTL Driving CMOS,
OutJJUt Low Voltage
TTUCMOS Output
Sink Current
TTUCMOS Output
Source Current

SYMBOL

CONDITIONS
VSS=oV
VSS=OV
VSS=OV
VSS=OV
VSS=OV

MIN
2,0

VIH
VIL
VOH
VOL
VOH

VDD=5V,
VDD=5V,
VDD=5V,
VDD=5V,
VDD=5V,

VOL

VDD=5V, VSS=OV

0,4

V

IOL

VDD=5V, VSS=OV

8

rnA

IOH

VDD=5V, VSS=OV

-0,4

rnA

F·36

0,8
2,7
0,5
3,68

V
V
V
V
V

ICS1886
Input Pin Descriptions

Output Pin Descriptions

Transmit Data Input (TD+ and TD-)
For normal operation this differential input is transferred to the
TX± output through a PECL buffer. In loopback testing mode,
this input is multiplexed to the input of the device clock
recovery section.

Transmit Data Differential ECL (TX+ and TX-)
This differential output is buffered TD± data. This output
remains active during loopback mode.

Receive Data Input (RX+ and RX-)
The clock recovery and data regenerator from the receive
buffer are driven from this PECL input. During loopback
testing mode this input is ignored.
Clock Select (CSO and CSl)
Selects the operating frequency according to Table 1. Internal
pull-up resistors set both inputs high when left unconnected.
Carrier Detect (CD-)
Active low input which forces the VCO to free run. Upon
receipt of a loss ofinput signal (such as from an optical-to-electrical transducer), the internal phase-lock loop will free-run at
the selected operating frequency. Also, when asserted, CD will
set the lock output low.
Loop Timing Mode (LT-)
Active low input which routes the recovered receive clock to
the TC± outputs as well as the RC± outputs. Forces the transmit
clock to be 'loop-timed' to the system clock derived from the
incoming data.
Loopback Mode (LB-)
Active low input which causes the clock recovery PLL to
operate using the transmit TD± input data and ignore the
receive RX± data. Utilized for system loopback testing.
External Crystal or Reference Clock (REF+ and REF-)
This oscillator input can be driven from either a fundamental
mode crystal or a stable reference. For either method, the
reference frequency is 1;8 the operating frequency. See Table I
for more information.

Transmit Clock Differential ECL (TC+ and TC-)
Differential output clock used by the PDH/ATM processor for
clocking out transmit data. This clock can be derived from
either an independent clock source or from the recovered data
clock (system loop time mode).
Receive Data Differential ECL (RD+ and RD-)
The regenerated differential data derived from the serial data
input. In loopback mode this data is regenerated from the
transmit data input (TD±). This data is phase-aligned with the
negative edge of the RC clock output.
Receive Clock Differential ECL (RC+ and RC-)
The differential clock recovered with the internal clock recovery PLL. In loopback mode this clock is recovered from the
transmit data (TD±) input. This clock is phase-aligned with the
RD data output.
Lock/Loss Detect (LOCK)
Set high when the clock recovery PLL has locked onto the
incoming data. Set low when there is no incoming data, which
in tum causes the PLL to free-run. This signal can be used to
indicate or 'alarm' the next receive stage that the incoming
serial data has stopped.

Output Description
The differential output drivers are current mode and are designed to drive resistive terminations in a complementary fashion. The outputs are current-sinking only, with the amount of
sink current programmable via the IPRGx pins. The sink
current is equal to four times the IPRGx current. For most
applications, a resistor from VDD to IPRGx will set the current
to the necessary precision. IPRGl supplies the current minor
for the TX± output. IPRG2 supplies the current mirrors for the
RD±, RC± and TC± outputs.

F-37

ICS1886
Ordering Information
ICS1886M
Example:

'CSll~
Device Type (consists of 3 or 4 digit numbers)
PrefIX
ICS, AV=Standard Device; GSP=Genlock DevIce

~~a~~fl:v~,~:;~d~chua=:n~g~~t~n~n~~~~ro~p~~~c~~~ ~~f~:~h~~~~I~~~8
reserves the right to change or discontinue these products Without notice

F-38

•

ICS1887

Integrated
Circuit
Systems, Inc.

Product Preview

FOOl/Fast Ethernet PHY ceiver™
General Description

Features

The ICS1887 is designed to provide high performance clock
recovery and generation fur 125 MHz serial data streams. The
ICS1887 is ideslly suited for LAN transceiver applications in
either POD! or Fast Ethernet environments. The ICSl887
converts NRZ to/from NRZI data in addition to providing a
S-bit parallel digital data transmit and receive intermce.

•
•
•

Single IC solution to existing designs requiring
multiple devices
Data and clock recovery for 125 MBaud PODI or Fast
Ethernet applications
Clock multiplication from either a crystal, differential or
single-ended timing source
Continuous clock in the absence of data
No external PLL components
LocklLoss status indicator output
Loopback mode for system diagnostics
Selectable loop timing mode
PECL driver with settable sink current
Parallel digital transmit and receive data interface
NRZ to/from NRZI data conversion
Consult ICS for optional configurations and data rates

The ICS1887 utilizes advanced CMOS phase-locked loop
technology which combines high performance and low power
at a greatly reduced cost.

•
•
•
•
•
•
•
•
•

Block Diagram

Pin Configuration

Clock and data recovery is perfurmed on an input serial data
stream or the buffered transmit data depending upon the state
of the loopback input. A continuous clock source will continue
to be present even in the absence of input data. All internal
timing is derived from either a low cost crystal, differential or
single-ended source.

REF- REF·

VSS
LTCOTX+
TXVSS
IPRGl
RXRX+
LBLOCK
R04
R03
VSS

TX.(J)--~

RX+

~-~-----------'

1
2
3
4
5
6
7
8
9
10
11
12
13
14

I'

co
co
.....

U)

2

28
27
26
25
24
23
22
21
20
19
18
17
16
15

T04
TD3
T02
TOl
TOO
TCLK
VOO
REFREF+
VOO
RCLK
ROO
ROl
R02

28-Pin SOIC
K-7

CD- (1)---------------1

ICS1887

PHYc81Yer Is. trademark of Integrated CirCUIt Systen'8,lnc.

IICS1887RovA1201114

F·39

II

ICS1887
Pin Descriptions
PIN NUMBER

1---

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

PIN NAME
VSS
LTCDTX+
TXVSS
IPRGI
RXRX+
LBLOCK
RD4
RD3
VSS
RD2
RDI
RDO
RCLK
VDD
REF+
REFVDD
TCLK
IDO
TDI
TD2
TD3
TD4

TYPE

DESCRIPTION
Negative supply voltage
Loop Timing mode select*
Carrier Detect input*
Positive Transmit serial data output
Negative Transmit serial data output
Negative sUllply voltage
PECL Output stage current set (TX)
Negative Receive serial data input
Positive Receive serial data input
LOOQBack mode select*
Lock detect output
Recovered data output 4
Recovered data output 3
Negative supply voltage
Recovered data output 2
Recovered data output 1
Recovered data output 0
Recovered Receive clock output
Positive supply voltage
Positive reference clock/crystal input
Negative reference clock/crystal input
Positive supply voltage
Transmit clock output
Transmit data input 0
Transmit data input 1
Transmit data input 2
Transmit data input 3
Transmit data input 4

* Active Low Input.

F-40

II

ICS1887

Absolute Maximum Ratings
Voo (measured to Vss) .......................
Ambient Operating Temperature ................
Storage Temperature ..........................
Junction Temperature .........................
Soldering Temperature ........................

7.0V
-55 to 125°C
-65 to 150°C
175°C
260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Recommended Operating Conditions
I

SYMBOL

I

TA
Vss
VDO
Vss
VDD

PARAMETER
Ambient Operating Temp.
i, Using a Negative Supply
)1

Using a Positive Supply

TEST CONDITIONS

MIN

MAX

0
-4.95
0.0
0.0
+4.75

+70
-5.45
0.0
0.0
+5.25

I

I

UNIT~
°C
V
V
V
V

II

ICS1887 FDDVFast Ethernet
LOOPTIMED OR
INDEPENDENT
TCLK
'"

[

FIBER OR COPPER
MEDIA INTERFACE

~

....

SERIAL
TxDATA

[

TO[O 4] DATA

...

SERIAL
RxDATA ..
FIBER OR COPPER
MEDIA INTERFACE

,

ICS1887

Physical Layer
Transceiver

CARRIER
DETECT

RECOVERED
RCLK

LOCK

~[]~

25 MHz
CRYSTAL OR
EXTERNAL REFERENCE

F·41

'"

RECOVERED'
RD[O 4] DATA ....

..

,

125 MBaud FDDI
or Fast Ethernet
Parallel Interface
100 Mbps

~

ICS1887
DC Characteristics
(VDD = VMIN to VMAX, VSS = OV, TA = TMIN to TMAX)
PARAMETER

CONDITIONS

Supply current

Voo=+5.0V, Vss=O.OV

ECL InpuUOutput
PARAMETER
ECL Input High Voltage
ECL Input Low Voltage
ECL Output High Voltage
ECL Output Low Voltage

SYMBOL

CONDITIONS

MIN

MAX

UNITS

VIH
VIL

Voo - 1.16
Voo - 1.81

Voo - 0.88
Voo - 1.47

VOH
VOL

Voo - 1.02
Voo - 1.62

V
V
V
V

MAX

UNITS

0.8

V
V

-----

TTL InpuUOutput
PARAMETER

SYMBOL

CONDITIONS

TTL Input High Voltage

VIH

TTL Input Low Voltage
TTL Output High Voltage
TTL Output Low Voltage
TTL Driving CMOS,
Output High Voltage
TTL Driving CMOS,
Output Low Voltage

VIL
VOH
VOL
VOH

VDD=SY,
VDD=SY,
VDD=SV,
VDD SV
VDD=SV,

VOL

VDD=SV, VSS=OV

TTL/CMOS Output
Sink Current
TTL/CMOS Output
Source Current

IOL

VDD=SV, VSS=OV

IOH

MIN

VSS=OV
VSS=OV
VSS=OV
VSS OV
VSS=OV

2.0
2.7
O.S
3.68

V

I
I

VDD=SV, VSS=OV

!

F-42

V

I

0.4

V

8

rnA

-0.4

rnA

ICS1887
Input Pin Descriptions

Output Pin Descriptions

Parallel Transmit Data (TDO .. TD4)
Five bit TIL compatible digital input, which is received by the
ICS1887 on the positive edge of TCLK. High impedance input
drivers routed to the serial NRZ to NRZI converter. In loopback
testing mode, this NRZI data is multiplexed to the input of the
device clock recovery section.

Differential ECL Transmit Data (TX+ and TX-)
This differential output is converted TD[O ..4J serial data. This
output remains active during loopback mode.

Differential ECL Receive Data Input (RX+ and RX-)
The clock recovery and data regenerator from the receive
buffer are driven from this PECL input. During loopback
testing mode this input is ignored.
Carrier Detect (CD-)
Active low input which forces the VCO to free run. Upon
receipt of a loss of input signal (such as from an optical-to-electrical transducer), the internal phase-lock loop will free-run at
the selected operating frequency. Also, when asserted, CD will
set the lock output low.
Loop Timing Mode (LT-)
Active low input which routes the recovered receive clock to
the TCLK output as well as the RCLK output. Forces the
transmit clock to be 'loop-timed' to the system clock derived
from the incoming data.
Loopback Mode (LB-)
Active low input which causes the clock recovery PLL to
operate using the transmit input data reference and ignore the
receive RX± data. Utilized for system loopback testing.
External Crystal or Reference Clock (REF + and REF-)
This oscillator input can be driven from either a fundamental
mode crystal or a stable reference. For either method, the
reference frequency is 25.00 MHz.

Transmit Clock (TCLK)
TTL compatible 25 MHz clock used by the parallel processor
transmitter for clocking out transmit data. This clock can be
derived from either an independent clock source or from the
recovered data clock (system loop time mode).
Parallel Receive Data (RDO .. RD4)
The regenerated five bit parallel data derived from the serial
data input. In loopback mode this data is regenerated from the
transmit data. This data is phase-aligned with the negative edge
of RCLK clock output.
Receive Clock (RCLK)
A 25 MHz digital clock recovered with the internal clock
recovery PLL. In loopback mode this clock is recovered from
the transmit data.
LockILoss Detect (LOCK)
Set high when the clock recovery PLL has locked onto the
incoming data. Set low when there is no incoming data, which
in tum causes the PLL to free-run. This signal can be used to
indicate or 'alarm' the next receive stage that the incoming
serial data has stopped.

Output Description
The differential driver for the TX± is current mode and is
designed to drive resistive terminations in a complementary
fashion. The output is current-sinking only, with the amount of
sink current programmable via the IPRG 1 pin. The sink current
is equal to four times the IPRGx current. For most applications,
a resistor from VDD to IPRG I will set the current to the
necessary precision.

F-43

II

ICS1887
Ordering Information
ICS1887M
Example:

ICSXXXX M

1L,~

Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device

~~a~~~fJ:V:'~~~~t d~~Uar:c~:n~~~~t~n~~~~~~r°snp~~~~~~~~ ~~~::~~:I~e~~~

reserves the nght to change or dlscontmue these products wrthout notice

F-44

•

ICS1888

Integrated
Circuit
Systems, Inc.

Product Preview

High Performance Twisted Pair Communication PHYceiver™

Description

Features

The ICS1888 is an integrated PHY interface solution
providing a complete UTP/STP to UN! (User Network
Interface) solution for SONET, A1M and B-ISDN like
communication over CAT-5 type cable. The ICS1888 is
designed to provide high performance adaptive
equalization, clock recovery and data regeneration for
155.52 Mb/s serial NRZ data streams.

•

Adaptive equalization with clock recovery

•
•

Interfaces to Category 5 STP/UTP cables

The ICS1888 is capable ofreceiving and transmitting
155.52 Mb/s NRZ data rates over Category 5 UTP/STP
(Unshielded Twisted PairlShieldedTP) cables at up to
distances of 100 meters. The internal adaptive equalizer
corrects for any phase or amplitude distortion.
A continuous clock source will continue to be present
even in the absence of input data. AIl internal timing is
derived from a low cost crystal or either a differential or
single-ended timing source.
The ICS1888 utilizes advan~ CMOS phase-locked
loop technology which combines high performance and
low power at a greatly reduced cost.

Data regeneration and clock recovery for:
155.52 MHz (STS-3/0C-3)

•

Clock multiplication from either a crystal,
differential or singIe-ended timing source

•
•
•
•

Loopback mode for system diagnostics

•

Selectable looptiming mode

•

PECL Drivers with settable sink current

•

Low power CMOS technology

•

Consult ICS for optional data rates and coding

Continuous clock in the absence of data
No external PLL components required
LocklLoss status indicator output

Block Diagram
19.44 MHz XTAL

_

/

INDEPENDENT OR
LOOPTIMED Tx CLOCK

LT¥

r---------~~~------~~--~

--.

TC+
TCTXUTP

DRIVER

TD-

RC+

--.

RC·
ADAPTIVE

RD+

EQUALIZER

--.

RD-

--.

CARRIER
DETECT

LOCKILOSS
DETECT

F-45

F-46

ICS1889

Integrated
Circuit
Systems, Inc.

•

Product Preview

1008ase-FX Integrated PHYceiver™
General Description

Features

The ICS1889 is a fully integrated physical layer device
supporting 100 Megabits per second CSMA/CD Ethernet
fiber optic applications. It is designed to support the requirements of DTEs (adapter cards), and hub or router ports. It
is compliant with the ISO/IEC 8802 Fast Ethernet standard
for 1ooBase-FX. It provides a Media Independent Interface
allowing direct chip-to-chip connection, motherboard-todaughter board connection or connection via a cable in a
similar manner to the AU! approach used with 10Base-T
systems. A station management interface is provided to
enable it to receive command information and send status
information. It transmits and receives NRZI data and interfaces directly to the optical transceiver. It can operate in
either half duplex or full duplex.

•

•
•
•

•

•
•
•
•

•
•

One chip integrated physical layer
ISO/IEC 8802-3 CSMA/CD compliant
100 Base-FX Half & Full Duplex
Far end fault detection
Media Independent Interface (MIl)
Station management interface
Extended register set
Transmit clock synthesis
Receive clock and data recovery
Detailed receive error reporting
Extended Test Modes

Block Diagram

TX

~----I1 008ase-FX

To/From
MAC

NRZI data
to
optical
transceivers

Mil

RX

MGMT

PHYceiver i, • trademark of Integrated Circuit System•• Inc.

Control
Status

PRODUCT PREVIEW dOCLmenta contain Information on products In the formative or
deSign phaBe of development. Ch....cteristlc data and other .paedication. are design
goals. ICS reserves the nght to change or discontinue these products without notice.

ItCS1889RevA021696

F-47

F.48

ICS1890

Integrated
Circuit
Systems, Inc.

Product Preview

1 OBase-T /1 OOBase-TX Integrated PHY ceiver™
General Description

Features

The ICS1890 is a fully integrated physical layer device supporting 10 and 100 Megabits per second CSMA/CD Ethernet
applications. It is designed to support the requirements of
DTEs (adapter cards or motherboards), switching hubs, concentrators (repeaters) and router ports. It is compliant with the
ISO/lEC 8802-3 Ethernet standard. It provides a Media Independent Interfuce allowing direct chip-to-chip connection,
motherhoard-to-daughter board connection or connection via
a cable in a similar manner to the AUI approach used with
10Base-T systems. A station management interfuce is provided
to enable it to receive command information and send status
information. It internces directly to a single transmit and
receive isolation transformers and can support shielded twisted
pair (STP) and unshielded twisted pair (UTP) category 5
cables up to 105 meters. It can operate in half duplex or full
duplex at either 10 or 100 Mbps and electronically switch
between the two modes. By employing auto-negotiation and
sense logic it is able to determine the technology capabilities
of it's remote partner and then adjust its operating mode to
match the highest performance co=on operating mode.

•
•
•
•
•
•

•

•
•
•
•

•

One chip integrated physical layer
ISO/lEC 8802-3 CSMA/CD compliant
100 Base-TX Half & Full Duplex
10 Base-T Half & Full Duplex
Stream Cipher ScramblerlDescrambler
MLT-3 Encoder/Decoder
Adaptive Equalization & DC Restoration
Auto Sense & Negotiation (N-Way)
Integrated 10/100 switch
Enhanced Status & Configuration
Media Independent Interface (MIl)
Station management interface

Block Diagram

1008ase-TX
switch

Cable
108ase-T
Mil

N-WAY
Registers
MGMT

PHYcalVe( 18 a trademark. of Integrated Circuit Systems, Inc.

PRODUCT PREVIEW documents contain Information on product. In the formative or
deSign phase of development. Charactenstlc data and other apeclficatlonl are design
goal8. ICS reserves the nght to change or discontinue these product. Without notice.

IICS1890RovA021696

F-49

F·SO

ICS1891

Integrated
Circuit
Systems, Inc.

•

Product Preview

1 OOBase-TX Integrated PHV ceiver™ for Repeaters
General Description

Features

The IeS1S'1 is a fully integmted physical layer device supporting 100 Megabits per second CSMAlCD Ethernet Repeater applications. It is designed to meet the specific
requirements of repeater applications such as small PCB
footprint and law power. It is compliant with the ISOIIEC
8802-3 Ethernet standard. It provides a Media Independent
Inter1ilce allowing direct chip-to-chip connection, motherbosrd-to-daughter bosrd connection, or connection via a cable
in a similar manner to the AU! approach used with 10Base-T
systems. A Stream Inter1ilce may also be used to enable class 2
repeater designs. A station management intemce is provided
to enable it to receive command information and send status
information. It interfuces directly to a single transmit and
receive isolation transfurmers and can support shielded twisted
pair (STP) and unshielded twisted pair (UTP) category 5
cables up to 105 meters. Auto-negotiation and sense logic
allows repeater management to determine the technology
capabilities of its remote partner and ensure a proper connection at 100 Megabits per second.

•
•
•
•
•

•
•
•
•
•

•
•
•

One chip integrated physica1layer
ISOIIEC 8802-3 CSMAlCD compliant
Small14mm x 14mm QFP package
Low Power Consumption
5-bit Stream Interface
Full 100 Base-TX support
Stream Cipher ScramblerlDescrambler
MLT-3 EncoderlDecoder
Adaptive Equalization & DC Restoration
Auto Sense & Negotiation (N-Way)
Enhanced Status & Configuration
Media Independent Interface (MlI)
Station management interfuce

Block Diagram
~-----------------------

Mil TX&RX ..
OR

100Base-TX

5-bit Stream

Repeater
Core

~

~

MLT-3

-

l
Mil
Registers f--...Management

I
I

~
Switch

NWay

--+
+-

Magnetics

;~

..

RJ-45

4

RXlt
I
I

PROOUcr PREVIEW docLl'YMlf1W contain inforrMtion on product. in the formmive or
dnign pha.. of d ......opment. Ch••cteriltic date and other epecificltione
_ign
goel.. les rnervee the right to chenge or discontinue theM producta without notice.

.re

PHYcelvw iI • tradem..k of Integrated Circuit Syatenw, Inc.

IICS1891 RovA022296

F-51

F-52

les
Multimedia
Products

At ICS, the digital world meets the real world with multimedia products for adding
audio and motion video to computer and consumer electronics products. We
combine our experience in phase-locked loop, digital signal processing, and
mixed-signal design to produce multimedia ICs for OEMs around the world. Our
solutions in audio and video are matched to OEM requirements for cost-effective products.
In video, ICS offers the GSP and 2008 product lines. The GSP family offers
Genlocking to enable full-motion, computer-generated text and graphics to be

overlayed on any standard video signal, such as TV, camcorder, VCR, or video
disc. It also supports easy recording of the enhanced video image onto videotape.
The ICS2oo8A line implements VITC and LTC read and write of the standard
SMPTE Time Code data, synchronized with MTC (MIDI time code) output.
In audio, ICS offers Wavedec and WaveFront. Wavedec, our digital audio codec
for computer and consumer electronics products, records and plays 16-bit compatible fIles for applications running in MS DOS or MS Windows platforms. WaveFront, our wavetable synthesizer, creates the audio subsystem required for
producing the full General MIDI patch set on next-generation, 16 bit sound cards
and consumer electronics products.
Most importantly, we understand the systems-integration challenges of adding
multimedia capabilities to your products. Our applications engineering team includes engineers responsible for the Multisound product from our Turtle Beach
Systems division and for the Jazz 16™ multimedia audio chipset from Media Vision.
ICS views our multimedia IC business as a systems business and we can assist you
with your systems-integration needs. We look forward to partnering with you and
making you and your new products succeed in the marketplace.

Jazz 16 i. a trademark of Media Vision.

G·1

les Multimedia Product Selection Guide
Product
Applications
Video Grapbics

ICS
Device Type

Description

Package Types

Page

GSPSOO

NTSC Genlock.

68-PinPLCC

G-3
G-49

GSP600

PAL Genlock.

68-PinPLCC

Codecs

ICS2002

Business Audio Codec.

44-PinPLCC

G-85

SoundlVideo
Synchronization

ICS2008A

Improved SMPTE-MIDI
Peripheral.

44-PinPLCC

G-1OS

ICS2101

5 Channel Digitally
Controlled Audio Mixer.

28-Pin
DIP, SOIC

G-l23

ICS2102

Sound Blaster Compatible
Mixer.

28-Pin
SOIC

G-131

ICS2115

WaveFront MIDI
Synthesizer.

84-PinPLCC
100-Pin TQFP

G-141

Audio Mixers

Wavetab1e
Synthesis

Audio Synthesis
Clock Generator

ICS2116

WaveFront ISA Interface.

lOO-Pin PQFP

G-l71

ICS2122

WaveFront Sounds
2Mb General MIDI.

44-PinSOIC

G-185

ICS2124

WaveFront Sounds
512kb General MIDI ROM.

44-PinSOIC

G-189

ICS2125

WaveFront Sounds
4Mb General MIDI ROM.

32-PinSOIC

G-193

ICS9120-08!
ICS9120-09

Clock for
Audio Systems.

8-PinSOIC

C-35

ADVANCE INFORMATION documents contsin information on new products in the sampling or preproduction phase of development. Characteristic dats
and other specifications are subject to change without notice.
PRODUCT PREVIEW documents contsin information on products in the formativeor design phase of development. Characteriatic dats and other specifications
are design goals. ICS reserves the right to change or discontinue these products without notice.

G-2

II

GSP500

Integrated
Circuit
Systems, Inc.

VGA/NTSC Video Genlock Processor with Overlay
Overview

Features

The GSP500 allows the text and graphic images of VGA and
Super VGA controllers to be displayed on standard NTSC
televisions or recorded on a VCR. Additionally, the GSP500
accepts external vIdeo input from a camcorder or a VCR and
will synchronize (genlock) the VGA or Super VGA controller
to the external video. The GSP500 also allows VGA and video
images to be overlaid on the same television screen. The
GSP500 meets or exceeds all RS-170A broadcast standards for
timing accuracy and allows the VGA controller to maintain true
NTSC compatibility at all times. The GSP500 is compatible
with virtually all VGA controllers. Tseng Labs, Oak Technology, Trident Microsystems, S3, and NCR already have full
BIOS support available for the GSP500.

•
•

9

10

§

CI
CI
CI
CI
CI
CI

•
•
•

CI
CI
CI
CI
CI

G~H"OO!l

•

•

61

~.oEODDODODDDODDDOOO§ 60
CI
CI
CI
CI
CI

26

1

•

•

§

CI
CI
CI
CI
CI
CI

Direct inputofNTSC or S-Video (S-VHS and Hi-8 video).
On board NTSC/S-Video sync and black burst generation
for local video operation. Video chroma burst separate
with 3.579545 MHz and 14.31818 MHz phase locked
outputs.
Meets or exceeds alltiming specifications for studio and
broadcast television.
High efficiency NTSC/S-Video conversion that maintains
VGA performance.
Dynamic overscan and underscan adjustment ofNTSC/SVideo modes under BIOS and/or software control.
Software selection between all VGA and NTSC/S-Video
modes.
NTSC/S-Video conversion support for all VGA and Extended VGA modes with 480 or fewer lines.
Built-in dot clock circuitry to eliminate crystal oscillators
for VGA, plus extended VGA operation up to 135 MHz.
Low power consumption, ideal for laptop computers.

E1

§OODDOOOOOOOOOOOOO§ <14
'0

43

68-Pln PLCC
K-l0

=
VIdeo

GS~500

SIgnals

RGB-to-NTSC
encoder
(BA7230LS)

p=

Dot

::: 0-15

".:

Select

PC Bus

Sync

RGB

VGIA

Contro~ll9r

c:G:

IGSPSOORevA0994 I
G·3

RAMDAC

GSP500
Internal Block Diagram
¥IDEO II'IIT 1

~----------------------------~ ~

VIDEO ItI'UT 2

Theory of Operation
The GSP500 can be thought of as an extremely sophisticated
dot clock generator. In its simplest form, the GSP500 will
generate all of the dot clock frequencies necessary to drive
VGA and Super VGA controllers. The different frequencies
are selected with the MODE SELECT LOGIC from the VGA
chip. Selection is similar to selecting frequencies on any ~f the
ICS dot clock generators (Le., ICS1394, ICS1494, ICS1561,
ICS2494, etc.). Additionally, there are four reserved frequency
addresses. These are labeled GL (genlock), OV (overlay), va
(video only), and GO (graphics only). Choosing any of these
addresses will switch the GSP500 from VGA mode to NTSC
mode. Under NTSC mode, the GSP500 accepts vertical and
horizontal VGA SYNC from the VGA controller and uses the
sync to generate and adjust the VGA DOT CLOCK. The
GSP500 will automatically vary the frequency of the dot clock
in order to synchronize the VGA sync signals with an NTSC
reference signal. This reference signal can be derived from a
video device (such as a camcorder) connected to VIDEO
INPUT 1 or VIDEO INPUT 2. The GSP500 provides an
RGB-to-NTSC encoder with the VIDEO OUTPUT signal
which is either VIDEO INPUT I, VIDEO INPUT 2, or an
internally generated black burst signal. All of the necessary
ENCODER LOGIC signals to properly drive the encoder are
provided by the GSPSOO.

During NTSC modes the GSPSOO also creates the D·IS SYNC
OUTPUT for the monitor connection to allow for TV projection output of the VGA images. The PIXEL SWITCH information derived from external CKEY INPUT tells the encoder
whether to display the VGA image or external video for each
pixel. Assuming the images are genlocked, this creates the
overlay effect.

Block definition
Video Input Switch
The Video Input Switch selects whether the GSP500 uses
VIDEO INPUT I or VIDEO INPUT 2 as the external video
source. It is controlled by an external pin of the GSPSOO.

NTSC Sync Separator
The GSPSOO contains a high quality sync separator to allow
direct input of NTSC, S-VHS, or HI-8 video signals from
camcorders, VCRs, and other video products. The GSPSOO
utilizes a differential video input circuitry for maximum noise
immunity. It also employs digital noise filtering and enhanced
digital signal tracking technology to ensure maximum compatibihty with consumer, industrial, and broadcast video signals. Although low cost video sync separator products are
commonly available, they are primarily designed for television
and video monitor use. The simple diode clamping circuit used
in these devices does not have the accuracy or noise immunity
required for genlocking.

G·4

GSPSOO
Sync Correction

RS-170A Sync and Black Burst Generator
RS170A Sync Generator
The studio quality bUilt -in vIdeo sync generator allows the
GSPSOO to operate without an external video input and still
maintain broadcast vIdeo timing. This assures NTSC compatibility at all tImes. When external video is present, the sync
generator works in conjunction with the sync separator to
isolate sync from noisy vIdeo sIgnals.

Black Burst Generation
Most RGB-to-NTSC encoders synchronize a crystal oscillator
to the chroma burst sIgnal of the external video signal. ThIs
provides the color reference portion of the video signal. If an
external vIdeo signal is not available, the crystal oscillator will
free run, creating screen artifacts such as 45 degree moving
lines in constant color portions of the screen. To eliminate this
problem, the GSPSOO generates a black burst video signal.
Black burst video is an analog sIgnal containing both sync and
a correctly phased chroma burst signal. This ensures proper
color reference generatIOn at all times. The GSPSOO provides
black burst output to the encoder when external video is either
missing or not selected (non-genlock mode).

The Sync Correction clfcUitry looks for missing sync pulses,
block sync, single field video, and phase shift errors caused by
the head switching zone of a VCR. It assures proper genlock
during all of these problems common in consumer video
products.

Genlock Timing Control and Clock Regulation
The GSPSOO looks at the IDput sync from the VGA controller
and determines how to alter the dot clock to create RS-170A
timing. Both the frequency and the method can change with
different VGA modes. The GSPSOO enables vIrtually any
VGA controller capable of IDterlacIDg to create RS-170A
timing. The GSPSOO' s unique architecture provides ultra-high
efficiency and flexibility and allows the frequency of the dot
clock to be controlled totally under BIOS or software control.
Screen attributes such as horizontal width and position can be
individually programmed for each mode while maintaining
genlock integrity. This circuit will modify the timing of virtually any mode, with 480 or fewer lines, to meet RS-170A
NTSC specifications. The GSPSOO genlock timing control and
clock regulation design is awaiting patent approval.

INT/EXT Video Switch

Precision Dot Clock Generator

The Internal/External Video Switch determines whether the
encoder uses external video or the black burst signal. If external
video is chosen, the GSPSOO will simply pass the external
video signal through to the encoder, unaffected. Black burst is
used when external video is not present. The switch is controlled by the Video Signal Processing and Sync Correction circuitry.

The GSPSOO uses the same state-of-the-art dot clock technology that has made ICS the premier supplier of VGA dot clock
generators. ICS offers the highest accuracy and lowest jitter
products available.

Video Signal Processing and Correction
Video Signal Processing
The Video Signal Processing circuitry of the GSPSOO measures the incoming video signal for basic timing accuracy and
signal noise. It contains intelligent circuitry to remove extraneous portions of the video signal that would normally be
incorrectly categorized as sync. This is extremely important
when using a VCR as a video input. If there is an interruption
of the external video signal, this circuit will automatically
switch inputs from the external video signal to the internal sync
generator. When the external video signal resumes, the circuit
will automatically switch back to the external video. The
Video Signal Processing accepts the MODE SELECT LOGIC
from the VGA chip. This logic chooses either VGA or NTSC
operation and selects whether genlock to external video is to
be enabled.

G·S

CKEY
The ckey (or color-key) circuitry creates the pixel switch for
the encoder. This signal determines whether the VGA image
or external video is displayed for each pixel. Ckey is modified
by the GSPSOO to ensure that the pixel switch signal is delayed
(to make up for delays in the RAMDAC) and that it has proper
levels during sync and blanking. If the VGA and external signals
are genlocked, this pixel switch will create an overlay effect.

II

GSP500
PIN
NUMBER

NAME
VLE

DESCRIPTION
VERTICAL LOCK ENABLE. HIGH for VGA controllers.
LOW disables vertical lock feature, may be ~seful for Non-VGA Operation.
ODDIEVEN FIELD IDENTIFICATION. HIGH indicates odd numbered
field, LOW indicates even numbered field.

2

ODDIEVEN

3

BP

BACK PORCH PULSE. Negative polarity TTL level signal used by some
RGB-to-NTSC encoders.

4

5

DATAIN
CB

6

CS

Data input for inserting SMPTE time code in video signal.
COMPOSITE BLANKING OUTPUT. Indicates non-screen data portions
of NTSC signal.
COMPOSITE SYNC. NTSC Composite sync output for RGB-to-NTSC
encoders. Gated off during VGA modes.

7

CKEY

8
9

TEST

COLOR KEY. Resultant input from the 8-bit compare of digital RGB
(PO-P7) and a software selectable byte. This color key determines which pixels
display VGA and which display external video in overlay mode. See Hardware
Interface Manual for more details.
For IC'S use only.

VSYNCOUT

VERTICAL SYNC OUTPUT. Vsync output for DB-15 connector.

10

DATAFRAME

11

OVENABLE

12

lIES

TTL level framing signal active during lines 10-20. For use in time code
applications.
OVERLAY ENABLE. Fast pixel rate switch. HIGH displays NTSC output,
LOW display RGB output. Used for overlay encoders. See Application
Notes for wiring details.
INT.IEXT. SYNC. Determines sync selection in OVENABLE signal.
Tie LOW normally.

13

LOC/REM

14
15
16

BRSTACT

17
18
19

HRSTOUT

20

VDD

21

VDD

22

VSS

23

FS5

FRTSTOUT
HS

HSYNCOUT
VSS

LOCAUREMOTE. A LOW output state signifies REMOTE status indicating
that external video is present and a genlock mode has been selected. If external
video goes away or a non-genlock mode is selected, LOCAUREMOTE will
go HIGH.
For ICS use only.
For ICS use only, wire to pin 37.
HORIZONTAL SYNC. For some RGB-to-NTSC encoders.
Gated off during VGA modes.
For ICS use only.
HORIZONTAL SYNC OUTPUT. Hsync output for DB-15 connector.
Digital ground. We strongly recommend the use of a multilayer board and a
ground plane.
5 Volt digital power. We strongly recommend the use of a multilayer board
and a power plane.
5 Volt digital power. We strongly recommend the use of a multilayer board
and a power plane.
Digital ground. We strongly recommend the use of a multilayer board and a
ground plane.
Frequency Select 5. Selects between multiple VGA Dot Clock frequencies,
Genlock modes and NTSC frequencies. See Dot Clock Generation and
NTSC Mode Selection sections for a more detailed description.
Also see Application Notes for wiring diagrams and BIOS Interface Manual
for details.

G-6

II
PIN
NUMBER

GSP500
DESCRIPTION

NAME

24

FS4

25

FS3

26

FS2

27

FSI

28

FSO

29
30
31

EXTSYNC
VCRI
CLAMPLEV

32

Y2

33

Yl

34
35
36

C2
Cl
3.58SC

37
38

FRSTIN
AVDD

39
40

GFF
VCOLF

41
42

SYNCTHRS
VGAOIE

43
44

COUT
RST

45

YOUT

46
47

HALIGNOUT
SYSLF

48

XTALI

49

XTALO

Frequency Select 4. Selects between VGA Dot Clock frequencies and
NTSC modes.
Frequency Select 3. Selects between VGA Dot Clock frequencies and
NTSC modes.
Frequency Select 2. Selection between VGA Dot Clock frequencies and
NTSCmodes.
Frequency Select I. Selects between VGA Dot Clock frequencies and
NTSC modes.
Frequency Select O. Selects between VGA Dot Clock frequencies and
NTSCmodes.
For ICS use only.
HIGH permits using VCRs as an input.
Clamping level adjustment for video input. See Application Notes for
more details.
NTSC video input number 2. Note: This is also the Y (luminance) input for
S-Video systems.
NTSC video input number 1. Note: This is also the Y (luminance) input for
S-Video systems.
C (Chrominance) input number 2 for S-Video systems.
C (Chrominance) input number I for S-Video systems.
3.579545 MHz SUB CARRIER OUTPUT. Phase-locked to the chroma burst
signal to allow encoders to maintain proper SCH phasing.
For ICS use only, wire to pin 15.
5 Volt analog power. We strongly recommend the use of a multilayer board
and a power plane.
Inverts field 1 and field 2 of VGA sync. Normally tied HIGH.
VCO LOOP FILTER CIRCUIT. External RC circuit used in VCO circuitry.
See Application Notes for component values.
Sync threshold adjustment for video input. See Application Notes schematic.
VGA ODDIEVEN FIELD IDENTIFICATION. HIGH indicates odd
numbered field, LOW indicates even numbered field.
C (Chrominance) OUTPUT. C output for S-Video systems.
Chip reset pulse. This to be tied high through a resistor.
Do not tie to the computer reset line.
Y (Luminance) OUTPUT. NTSC video output when the NTSC/SVID
input is in the HIGH state. Y output for S-Video systems when the
NTSC/SVID input is in the LOW state.
For ICS use only, wire to pin 62.
SYSTEM CLOCK LOOP FILTER CIRCUIT. External RC circuit used in
the chroma burst phase locking circuit. See Application Notes for
component values.
14.31818 MHz crystal circuit. See Application Notes for parts specifications
and wiring diagrams.
14.31818 MHz crystal circuit. See Application Notes for parts specifications
and wiring diagrams.

G-7

II

GSP500
PIN
NUMBER

NAME

DESCRIPTION

50

AVSS

51
52
53
54
55
56
57

VID1I2
VCOOUT
F1LTSEL
DOTCLOCK
VFF
VCR2
VGAlNTSC

58

BG

59
60

LOC/REMIN
VGAHSYNC

61

VGAVSYNC

62
63

HALIGNIN
NTSC/SVID

64

VS

65

4XSC

66
67

PCLK
DATAOUT

68

SCH

Analog ground. We strongly recommend the use of a multilayer board and a
ground plane.
Input selector. High for YlICl, Low for Y2/C2.
For ICS use only, do not wire.
For ICS use only, wire to pin 57.
Clock signal input for VGA chip.
Inverts field 1 and field 2 of NTSC sync. Normally tied HIGH.
LOW modifies sync characteristics to permit operation with VCR input.
Mode identification output signal. HIGH indicates a VGA mode, LOW
indicates an NTSC mode.
BURST GATE PULSE. Negative polarity TTL level signal used by
RGB-to-NTSC encoders.
For ICS use only, wire to pin 13.
VGA HORIZONTAL SYNC. HSYNC signal from VGA chip.
See BIOS Interface Manual for programming details.
VGA VERTICAL SYNC. VSYNC signal from VGA chip.
See BIOS Interface Manual for programming details.
For ICS use only, wire to pin 46.
NTSC/S-VIDEO. Selects between NTSC and S-Video output. HIGH=NTSC;
Low=S-Video.
VERTICAL SYNc. NTSC Vsync output for RGB-to-NTSC encoders.
Gated off during VGA modes.
4 TIMES SUB CARRIER OUTPUT. 14.31818 MHz signal phase-locked to
the chroma burst signal.
PCLK from VGA chip.
TTL level output. This reads data during lines 10-20 and outputs it as a
digital signal. For use in time code applications.
SCH PULSE. Positive polarity TTL level signal to distinguish between
fields 1 and 3 or 2 and 4. Not necessary for most encoders.

G·S

II

GSP500

810S Programming Example
BIOS support is currently available from Tseng Labs, Oak Technology, Trident Microsystems, S3, and NCR. Other VGA
manufacturers have support programs underway. If you use one of these VGA controllers that have completed BIOS support,
you can ignore this section. The following information may be helpful to VGA manufacturers and software developers. These
tables represent register settings one particular VGA controller. Others are listed in the BIOS Interface Manual. This particular
controller does not interlace text modes and uses an 8 x 8 font for modes 0, 1, 2 , 3, and 7. The horizontal registers are adjusted
to produce underscan for text modes and overscan for graphics modes.

Horizontal CRTC Registers
-

I

CRTC

II

INDEX
00
01

,r-------\1

I,

02

I

03
04

I

05

1

CRTC
REGISTER

Modes:
00,01,04, OS, OD

Modes:
02,03,06,07,OE, OF, 10

Modes:
11, 12, 13

I

HT

35

6B

66

I

HDE

27

4F

4F
52

2A

53

EHB

SHB

96

-- 8B

87

I

SHR

30

5B

58

I

EHR

92

83

80

CRTC
REGISTER

200 Line Modes:
(Non-Interlaced)
00,01,02,03,07,04,
05,06, OD, OE, 13

350 Line Modes:
(Interlaced)
OF,1O

480 Line Modes:
(Interlaced)
12,13
05

I

!

Vertical CRTC Registers

I

CRTC
INDEX

06

VT

05

05

Ii

07

OVERFLOW

11

11

II

10

VRS

EO

D3

Ii

,

i

11

---~

F4

11

VRE

84

87

88

12

VDE

C7

AE

EF

15

SVB

DC

CF

FO

16

EVB

F2

E5

06

Note: The MSB of the MSL register (INDEX 09) must be turned OFF in 200 line NTSC modes. When using an 8 x 8 font for
text (modes 00, 01, 02, 03, 07) the 4 LSB of this register will change from F to 7.

Miscellaneous Output Register
II

I

NTSC mode

I

Genlock (GL)
Overlay (OV)
II

-

Video OnlY~VO)
Graghics Onl_ (GO)

I
I
I

Color Modes:
00,01,02,03,04,05,06,
OD,OE, 10, II, 12, 13

Monochrome Modes:
07, OF

23

22

27

26

2B

2A

2F

2E

Extended Registers
Tum OFF all DOTCLOCKl2 bits.

G.9

GSP500
NTSC vs VGA Horizontal Timing
f - - - - - - Safe Actl!)n Area - - - - 1
f , - - - - Safe Tltle Area - - - - - - - ')1

)1

~_fll
f----1
4.7uS

10.9uS

1J

II

=

I!

0r11Ont.1

OlSplay

I

I

U

[nd----1I,~

,I

Blanklng
Horlzontal T o t a l - - - - - - - j

NTSC vs VGA Vertical Timing (200 line mode)
.20

219

...

'"

I'II1'SC sync

'"

... ... ...

'"

...

'"

'"

.,

'"

'44

\lGA Hsyne
\lGA \lsync

... ...

... ...

..,

NTSC sync

..0

'"

...

m

'"

'"

\lGA Hsync

'"
".

'"

'"

'"

'"

'"

'58

'30

'"

'"

'"

\lGA \lSjll1C

260

261

262

263

~

21

22

~

~

25

H

U

\lGA Hsync
\lGA\lsync _ _ _ _ _ _ _ _ _ _ _~I---------------------------

G·I0

II

GSP500

Electrical Specifications
Operating temperature range O°C to 70°C

Electrical Characteristics
PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

AVDD

4.5

5.0

5.5

Volts

5.0

5.5

Volts

Operating Current - VGA Mode

DVDD
IDD (VGA)

4.5

Operating Current - NTSC Mode

IDD (NTSC)

Analog Supplv
Digital Supply

35

rnA

I

50

rnA

Input Signals
OPERATING CONDITIONS
75 Ohm load

32

IVp-p
IVp_p

C2

34

lVp_p

VIDlI2

51

TTL/CMOS

High = YI ,CI; Low = Y2,C2

NTSC/SVID

63

TTL/CMOS

High = NTSC; Low = S-Video
Positive polarity

PIN #

Yl

33

CI

35

Y2

75 Ohm load
75 Ohm load

;

75 Ohm load

VGAVSYNC

61

TTL/CMOS

VGAHSYNC

60

TTL/CMOS

FSO-5

28-23

TTL/CMOS

CKEY

7

TTL/CMOS

PCLK

66

TTL/CMOS

Pixel (DAC) Clock from VGA

liES

12

TTL/CMOS

High = Internal sync
Low = External sync
Active during DAT AFRAME

-~---~

--

TYPICAL VALUE
1 Vp_p

SIGNAL TITLE

I

II

Positive polarity
Address/mode select
High = RGB; Low

= NTSC

DATAIN

4

TTL/CMOS

CLAMPLEV

31

1-1.5 V

SYNCTHRS

41

CLAMPLEV +0.1 V

VLE

1

TTL/CMOS

Tie to VDD through resistor

RSTI

44

TTL/CMOS

Tie to V DD through resistor

G-ll

I

. -

II

GSP500
Output Signals

-~

~~

-~

..

~IN#

VSYNCOUT

9

TTL

18
64

lVp~p

16

IVp~p

6
54

lVp~p

YOUT
COUT

45

IVp~p

43

IVp~p

75 Ohm load

3.58SC

36

TTL
TTL

3.579545 MHz
14.31818 MHz

HSYNCOUT
VS

i
i

HS

!

CS

,
I

.~

..

65

LOCIREM
OVENABLE

13

VGAINTSC

57
25

CB
ODDIEVEN

r----~

I

DOTCLOCK

4XSC

f--~

'U UE

SIGNAL TITLE

VGAOIE
BG/

58

FP/

3
68
10
67

OPERATING

Jl~.Jl

Jl~::'

Positive polarity during NTSC modes

TTL
~.-

Composite sync during NTSC modes
Positive polarity

~~

~--

..

Positive polarity

~

..

--

Positive polarity

TTL

-L--

11

2
42

SCH
DATAFRAME
DATAOUT

'T'VDTr' • T \T

75 Ohm load

=remote - =NTSC; Low = ROB
.
High =VGA- Low =NT~

TTL
TTL

High = local; Low

~h

TTL
TTL
TTL
TTL
I

I

Positive polarity

I

t===

. ~. ~ TTL - - - -

TIL
TTL

I

TTL
TTL

I

G-12

High =odd field; Low =even fi~JQ."_~--1
High =VGA odd field
Low = VGA even field
Negative polarity
,I

Neg"'"p"'''''''

3

J

~ . __ PositivejlQi~ _ _ _

duri~g DATAFRAME
Lines 10-20

Active

I

II

GSP500

Dot Clock Selection
The following charts represent two of the many dot clock frequency selection tables supported by GSP500. See the BIOS manual
or contact ICS applications engineering for additional information.

FREQUENCY (MHz)

FS5

FS4 FS3 FS2

FSI

FSO

50.350

0

I

0

0

56.644

0

0

1

65.028

0

I

0

72.000

0

75.000
80.000

1
1

1
1
I
0
0

0

1

89.800

1

0

0

I

1

0

0

110.000

1

0

GenLock

1

1

OVerlay

1

Graphics Only

1
I
I

1

1
I
0
0
1
I

FREQUENCY (MHz)

FS5 FS3

FS4 FS2

FSI

FSO

25.175

0

1

0

0

28.322

0

1

0

1

40.000

0

1

1

0

Video Only

1

1
0

1
0
I

44.900

0

1

I

I

GenLock

1

1

0

0

OVerlay

1

1

0

1

Video Only

1

1

1

1

1
I

0

Graphics Only

Ordering Information
GSP500V
Example:

ICSXXXXV

L __~Tfl"
V=PLCC

' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
L---------Prefix
ICS, AV=Standard DeVice, GSP=Gen!ock DeVice

G-13

I

II

GSP500 Frequently Asked Technical Questions.
1. What will the GSPSOO do for me?
The GSP500 adjusts the timing of a VGA controller to conform to RS-170A NTSC (television) specifications. The
GSP500 accepts direct video input from video cameras, videodisc players or other video sources and will synchronize
(genlock) a VGA controller to either the external video input or an internal NTSC sync generator. The GSPSOO also
contains a dot clock generator to eliminate the need for crystal oscillators or other dot clock generators.

2. How does the GSPSOO differ from other genlock devices?
Other genlock devices, such as the Motorola MC1378, are very effective at genlocking two NTSC signals together
and are generally used in consumer electronics products such as video window-in-a-window devices. The GSPSOO
is specifically designed to genlock a computer graphics controller to NTSC video and overcomes all of the
incompatibilities between VGA and NTSC. Additionally, the GSP500 contains an NTSC sync generator and maintains
chrominance phase lock in local modes. This allows the GSPSOO to maintain RS-170A NTSC timing without an external
video input. Furthermore, the sync separator circuit of the GSP500 is designed to satisfy the low jitter tolerances
demanded by discriminating VGA customers.

3. Isn't genlock simply a phased-lock loop?
Phase locking two similar Signals is fairly straightforward as long as phase jitter is not critical. As an example, ICS is
one of the few companies able to successfully build phase-locked loop dot clock generators with low enough phase
jitter for computer graphics display. Additionally, the differences between VGA and NTSC signals further complicate
the genlock procedure. The GSPSOO has patents applied forforthe most advanced computer video genlock methods
in the industry. These methods assure you ofthe highest possible quality product.

4.

Most Genlock and Overlay products have a lot of discrete components with trimmer
capacitors and potentiometers. All these adjustments can become very expensive in
a mass production environment. How much external circuitry does the GSPSOO
require?

Although the GSPSOO can be run with no trimmer capacitors or potentiometers, one trimmer capacitor should be used
to meet the NTSC frequency tolerance of the chroma burst. This is a free running frequency and is very simple (and
fast) to adjust. Additionally, the GSPSOO uses high speed digital circuitry to eliminate virtually all discrete components.
Only a few external components are needed for full operation.

S. Do I need an RGB-to-NTSC encoder with the GSPSOO?
Yes, an external RG8-to-NTSC encoder is needed. The encoder must be matched to the target audience. The GSPSOO
can be used under broadcast television scrutiny and most broadcast video equipment perform the encoding entirely
with discrete components. As this may prove too costly and/or may use too much board space, the GSPSOO contains
all of the necessary signals to drive virtually any encoder. The GSPSOO's generous supply oftiming Signals will also
drive external circuitry to tum off the encoder for laptop applications.

6. Why do I need the GSPSOO. Can't I program a VGA controller for NTSC sync and just
drive an RGB-to-NTSC encoder?
NTSC sync contains equalizing pulses, blanking signals and pulse widths that are impossible to create under normal
VGA control. Although marginal display quality is achievable on a television without adhering to the RS-170A standard,
compatibility with other NTSC equipment is compromised. As an example, depending on which edge of horizontal
sync the monitor triggers on will determine how far an incorrect width horizontal sync pulse will skew the screen.
Additionally, it becomes virtually impossible to assure proper chroma burst (SCH) phasing. The GSPSOO sync
generator meets or exceeds all NTSC RS-170A broadcast standards for timing accuracy assuring you of maximum
compatibility and ultimate quality.

G-14

7. National sells a sync separator for less than $2 while the Brooktree part costs over
$50. What is the difference and how does the sync separator in the GSP500 compare?
The sync separation circuitry in the National part is a simple diode clamp. Although this may be adequate for driving
a picture tube, the lack of noise and jitter immunity make it unsuitable for genlock applications. Additionally, the analog
vertical sync detection circuit of these type of devices will not accurately track a VCR signal. The Brooktree device
represents a mixed-mode approach to sync separation. By utilizing a fast analog circuitry coupled with high speed
digital logic, noise and jitter immunity can be optimized. The GSP500 also uses a mixed mode approach specifically
optimized for genlock operation yet the incorporation of a sync generator allows signal analysis not possible with
other devices.

8. Is the GSP500 compatible with any VGA controller?
VGA controllers need to have two features to work with the GSP500. First, they need to be able to interlace - if your
controller can display 1024 x 768 resolution, then it can probably interlace (the additional 256K memory is not
necessary). Second, the controller must have at least three clock select lines for extemal dot clock generator support.
Virtually all current VGA controllers have this feature. Check with your VGA controller manufacturer or ICS if you are
unsure.

9. How do I tum the NTSC on and off and control it?
The GSP500 uses the three clock select lines to support 4 VGA clocks and 4 NTSC modes. The VGA clocks are
available in 7 different pattems (I.e. 25.175, 28.322, 40.000, 65.000 is one pattem). The 4 NTSC modes are Genlock,
Overlay, Graphics Only, and Video Only. The selection between any NTSC mode or between NTSC and VGA is done
entirely under BIOS or software control.

10. Why did you incorporate a dot clock generator in the GSP500?
The GSP500 works by modifying the dot clock input for the VGA controller. It essentially is a dot clock generator
designed for NTSC genlock. The dot clock generator is not so much of an extra feature as it is a subset ofthe genlock
deSign. Consequently, this unity design assures you of a reliable glitch-free solution.

11. When the GSP500 displays an Overlay. how do I determine which part of the screen
displays graphics and which is VGA?
The GSP500 uses a technique called Color-Key to determine where to display the extemal video. This Color-Key color
is based on the VGA color number. Therefore, no colors are actually lost. As an example, the background color is
always Color O. Wlen Color-Keying on Color 0, the screen will appear to have a background ofthe external video.
The actual color that the VGA assigns to Color 0 does not matter. Any of the 256 color numbers can be assigned to
be a Color-Key. Although the GSP500 modifies the Color-Key input, the Color-Key selection is done by an extemal 8
bit digital compare.

12. Why is the Color-Key selection external to the GSP500?
Color-Key selection is done with an 8 bit compare ofthe digital RGB signals with a preassigned byte. The digital RGB
data comes from the VGA controller and the preassigned byte normally comes from the IBM bus via a port selection.
The output ofthis comparison is fed into the CKEY (Color-Key) input ofthe GSP500. Although this Color-Key method
will satisfy 95% of all customers, the external design allows other schemes with multiple or different comparison
options. Additionally, since all ofthese signals are already available inside the VGA controller, many manufacturers
have announced plans to incorporate the Color-Key function inside the VGA controller.

13. What about PAL and/or SECAM compatibility?
ICS is presently working on a PAL version ofthe GSP500. In its current implementation, it will be pin compatible with
the GSP500 but require different values for the discrete components and will also need a different crystal oscillator.
Although a SECAM version is technically possible, due to the uncertain market potential product development is not
currently underway.

14. Can I look forward to a combination PAL and NTSC product?
Unfortunately, the amount of circuitry common to both a PAL and an NTSC version is minimal. Separate versions are
currently the lowest cost solution. Although the crystal frequency, some discrete components and the Bios would
have to change, the same board layout could support both standards by simply changing the parts list.

G-15

G

15. Does the GSP500 accept multiple video inputs? What about an S-Video input?
The GSPSOO has two independent video inputs. Either input can be used or they can both be disabled. Either input
can be wired to accept either S-Video or NTSC. Selection between the two inputs is performed under hardware control.

16. Why doesn't the GSP500 incorporate audio?
The NTSC and S-Video baseband signals do not have a provision for audio. This means that the video and audio
signals are completely separate signals at all times. ICS offers audio products for the multimedia market that can be
incorporated into the design but allows the designer maximum flexibility by keeping them separate products.

17. Can I use the GSP500 with an RF modulator?
Yes, but the quality of the image may suffer. Wlen NTSC is modulated up to RF frequencies, audio is modulated onto
a 4.S MHz carrier and the video is limited to a maximum frequency of 4.2 MHz. Although 4.2 MHz may be sufficient
for moving images it can be limiting for high resolution computer graphics. This problem is magnified because the
majority of RF modulators are very low quality devices. Additionally, even if a high quality RF modUlation is obtained,
the signal may still be degraded by the RF demodulator inside the television set. ICS does recognize the these
limitations may be outweighed by the user-friendliness and compatibility of the RF standard. High quality RF
modulators are available and the GSPSOO does have the necessary signals for support but these issues should be
carefully weighed before implementation.

18. Can the GSP500 display NTSC video on my VGA screen?
No, in order to display NTSC video at 31.S KHz, it is necessary to convert NTSC into component form, digitize it in
real time, and store at least one frame of video. Although technology exists to accomplish this, the price-to-performance ratio of these products is too high for mass market acceptance at this time.

19. Is there any question that I forgot to ask?
Yes, when I use a graphics program, I find the borders very distracting yet I need the borders in text modes to
insure that I can read the DOS prompt. Can the GSP500 help me with this problem? The GSP500 has the ability
to adjust the width of the screen totally under Bios control. This means that you can have limited overscan in
mode 13, minor underscan in mode 3 and generous overscan In mode 12. Software drivers can even be written
to dynamically change the screen width with the cursor keys.

20. Does this mean I can change the height of the screen also?
NTSC has a fIXed number of lines. In order to change the vertical size, the screen data must be compressed or
expanded into fewer or greater lines. This can be accomplished in a text mode by changing the font size or in a
graphics mode with linear interpolation. The GSPSOO always maintains an exact one-to- one correlation between the
NTSC and VGA line position and therefore does not support vertical sizing.

21. Where do I get a development kit for the GSP500?
Call ICS at (800) 220-3366 for more information. We will put you in touch with a local rep. who will be more than happy
to supply you with a full GSPSOO development kit. The ICS full service support organization is always ready to help
you with the latest in Multimedia solutions.

G-16

AN501

Integrated
Circuit
Systems, Inc.

•

Application Note

Using the GSP500 with a Rohm BA7230LS Encoder
Contents
Page

Schematics
GSP500

G-18

BA7230LS . .

G-19

Port Selection

G-20

PAL equations - expanded product terms

G-21

PAL equations - symbol table.

G-22

Critical layout areas .

G-23

GSP500 pin names

. . . . . .

G-24

BA7230LS pin names . . . . .

G-24

Suggested layout for BA7230LS

G-25

GSP500 and BA 7230LS Physical Specifications

G-26

<.

Y1 IN

=
~

GSiIP5i1))1))
<.

Y2 IN

~":'

-

~

~

~

Signals

~
n
PC Bus

~

RGiB-to-NTSC
encoder

f-<.

(BA7230lS)

~sc

~

Il

@0-15

~

:ott
VlG/A

Sync

C«Jili'ltr«Ji~~®r

"'AGe"

Dig -c-------,

!AN601RevA0994 !

G-17

RM.IIDAC

GSP500 Schematic, page 1 of 3: GSP500 Wiring
VDD
AVDD
CSEl4....-..--'

~
~
~

III

~

I

~

IL 0 1uF
VIOl/2

II 01uF

75

25

1431818MHz

FS5
FS4
FS3
FS2
FS1
FSO
VGAHSYNC
VGAVSYNC

SLF

49
47

FDURXS
THREE58S
DOTCLOC

65
36
54

XTAL

veo OU
13
1
35
CI
~ VID1/2

~C2
31

QC)

STILFRM

75

vee
1
1
3
4
5
6

vee

,-----

12
II

10
9

8
I

~

II iII

2

7

CKEY

66

PCLK

41
3,

SYNCTHRES

8
56

EST/A
YNCSLP
NTSCISV

55
39
1
62
46
44

VFF
FF

40

LOOPFILT

VGAlNTS

LFSELEC
HSYNCOU
VSYNCOU

VGAO/
YOU

C

LE
HALIGNIN
HALIGNOUT

RST

VSS

B
B

12K

1000pF

e

=

J

330pF

1000pF

5pF

1-5pF

1
TPI
~

-

VCLK

33

~

5]
18

HSYNCOUT

9

--"---45

46

VSYNCOUT

·1 i

(

'10uF

58
]

QATAOU

67

~
E~~~~~~ r+!BRSTAC
c-!:lSCI
r-BFRSTOU
HRSTOU

t-%P¥-

SYNCTO 30
FRSTI N 37

GSP500

SYNCTOL

VIDEO INI

'----!lJ

4--+II
13
59

AVDD

100

/~

T

r-1l57

UA ou
UR I

OVENABL

33K

Not, ~ Vldref connects
10 ground at ground
end of connector

6

~; --#-ODDIEV~~

ClAMPLEV

?~~~
50

48

VDO

----'---- DATAIN

Y2 Input

VIORfF

13
24

XTAL1

VDo

cou

~

~

20
38

~I/ES
~

.:..

6 =218 1
VOD

26
17
18
68
61

~

Y1 Input

I

VDD

I

Il

c:-CBl
CBGl
~
OVENABLE

::-LRl

GSP 500 Schematic, page 2 of 3: BA7230LS Wiring

~----------------------------------------,
14ALS04

I.2K

~~

~.o:c

10K

~

~

2.71<

"~t""

I
I
.'---;;;

1.0uF

~

~~~,

I 7

~

I
I

I~ I

1

,:i ~
g
C

YOUj,,
~

~ENABLe
!"lEO IN

AEEN
•• ~'O
_ WE

I

VIDEO

q
'S<01'
YNC

Illr

w

1.21(

III

...

"

~

,

~I'O

"

,~

~

mar:s

wc:)--------------------------~

1.0K

10K

vee

r,~·J

1.0uF -'.

~
3.OK

..~ 1
...J... 20pF

300

33pF . .

9

~

m

GSP500 Schematic, page 3 of 3: Port Selection Wiring
I
I

SA"

••
~
18
• 18no
7
8

...

10

"I.IS

SAl

SA 0 •• 11

......

23

",

I

~

~

11

I
•• 14

10

SAl

111
112
113
114

01
CI!

"

22
~

IS "
17

~
I -¥.-

.......,
....,..

~
SYlIC11Il

~

~

C£illD

PAL2Ol.8

sa

$I 0 .. 7

3

51

•

..
7

I

I.
17
18

5
0 •• 7

VID1I2

"

" '••• 71

-L.:

Dl

5U

Il« I
II

••
•
"..

~

r-+-mlll
..

15

"
It

p

SY

L

C ..

CI..K

11.1
11.2

tvl
lV1

18
I.
I.

21.1
2A2

2Y1
2Y2
2V3
2Y4

"•
••

8

l~

I.
17

M3

t~

2M

W 18

Cl.R

vee

74l.S244

74LS273
PO
PI
PI
p
P.

~

I

P

P •• 7

DI

51.
7

0 •• 7
S'ISI5T

' . '•.. 71

••

•

..
7

D1
D2

~

DIS

I.
7
I.

I

"I

CI..K

Ql

Q2

I

Cl.R

..

'--.mLJ

8

IS
17
3

~
PI

."

.." E

11111111

"0 •• 7]

......
...

7

z

3
5
7

•••

•
"

II
15
I.
I.

12
I.

I.

ff
II
I
~

~~

74AL.S522

74LS273

••
I

l~

11.3
1M
21.1

" HI
2M

I
I.
17
I

lG

L--.!L( 2G

741l..S244

SD 0 •• 7

lV1 18
lV1
lV3 "
tv4 12
2Y1

"

m ••
7

S

2Y4

PAL Equations - Expanded Product terms
HOLD1 =

SAil
# SA 10
# !SA9
# !SA8
#SA7
#SA6
#SA5

HOLD2=

SA4
#SA3
# !SA2

R306=

AEN & HOLDI & HOLD2 & lOR & !IOW & !SAO & SAl

R307=

AEN & HOLD I & HOLD2 & lOR & !lOW & SAO & SAl

W306=

AEN & HOLDl & HOLD2 & !lOR & lOW & !SAO & SAl

W307=

AEN & HOLDl & HOLD2 & !lOR & lOW & SAO & SAl

AEN.oe=

o

HOLD1.oe= I
HOLD2.oe= I

E

R306.oe =
R307.oe =
W306.oe=
W307.oe=

G-21

PAL Equations - Symbol Table
Pin
Polarity

Variable
Name

!

Ext

Pin

Type

Pterms
used

MaxPterms

Min Level

-

AEN

21

V

HOLD I

18

V

7

7

1

HOLD2

19

V

3

7

1

!

lOR

23

V

-

-

!

lOW

14

V

-

-

!

R306

22

V

-

-

I

7

.~-----

!

R307

IS

V

SAO

13

V

SAl

11

V

SA2

10

V

-

SA3

9

V

-

SA4

8

V

SA5

7

1

----

I

7

1

-

-

-

-

-

-

V

-

-

-

-

-

SA6

6

V

-

SA7

5

V

-

SA8

4

V

-

-

SA9

3

V

-

-

SAIO

2

V

-

-

-

SAil

I

V

-

-

-

!

W306

17

V

1

7

!

W307

-

I

16

V

I

7

I

21

D

I

1

0

oe

18

D

I

I

0

oe

19

D

I

I

0

R306

oe

22

D

I

I

0

R307

oe

IS

D

I

I

0

W306

oe

17

D

I

1

0

oe

16

D

I

I

0

AEN

oe

HOLDI
HOLD2

W307

LEGEND F: field
N: node
V: variable

D: default variable
I: intermediate variable
X: - extended variable

G-22

M: extended node
T: function
U: undefined

Critical Layout Areas
A)

GSP500 VCXO input (pins 48 and 49 of GSP500)
Keep etches as short as possible. Keep all etches. especially high speed digital, away from circuit area.

B)

GSP500 VCXO loop filter (pin 47 of GSP500)
Try to keep components near GSP500. Keep all etches, especially high speed digital, away from circuit area.

C)

VCLK dotclock connection (pin 54 of GSP500)
Keep etch as short as possible. Keep all etches, especially high speed digital, away from connection.

D)

GSP500 VCO loop filter (pin 40 of GSP500)
Try to keep components near GSP500. Keep all etches, especially high speed digital, away from circuit area.

E)

GSP500 Video input ground connection
Connect one of the video input jack pins to the ground plane. Connect all VIDREF connections to this point with at
least a 20 mil etch. Keep 75 Ohm resistors close to the connectors.

F)

GSP500 Video inputs (pins 32 and 33 of GSP500)
Try to guard band video inputs to GSP500. Signal etches should be at least 20 mil thick.

G)

Encoder VCXO loop filter (pin 12 ofBA7230LS)
Try to keep components near encoder. Keep all etches, especially high speed digital, away from circuit area.

H)

Luminance delay (pins 16 and 3 of BA7230LS)
Keep etches as short as possible. Keep all etches, especially high speed digital, away from circuit area.

1)

Encoder VCXO crystal (pins 7 and 8 of BA7230LS)
Keep etches as short as possible. Keep all etches, especially high speed digital, away from circuit area.

J)

Power supply and loop filter pull·up voltage for GSP500 and encoder (pins 20, 21, 38, 40, and 47 of GSP500,
pins 12 and 24 of BA7230LS)
Regulate all power supply and loop filter voltages.

G·23

E

GSP500 Pin Names
1

VLE

2
3
4
5
6

ODDIEVEN

7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

FPI

DATAIN
CB
CS
CIillY
TEST
VSYNCOUT
DATAFRAME
OVENABLE
lIES
LlROUT
BRSTACT
FRTSTOUTI

HS
HRSTOUTI

HSYNCOUT
VSS
VDD
VDD
VSS

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

FSO
FSI
FS2
FS3
FS4
FSS
EXTSYNC
SYNCTOL
CLAMPLEV
Y2
YI
C2
CI
3.S8SC
FRSTIN
AVDD
GFF
VCOLF
SYNCTHRS
VGAOIE
COUT
RSTI

YOUT
HALIGNOUTI
SYSLF
XTALI
XTALO
AVSS
VID1I2
VCOOUT
FlLTSEL
DOTCLOCK
VFF
STILLFRAME
VGAlNTSC
BGI

LlRIN
VGAHSYNC
VGAVSYNC
HALIGNINI
NTSC/SVID

VS
4XSC
PCLK

BA7230LS Pin Names

YIN
B-YIN

13
14
15
16

R-YIN

17

BURST LEVEL ADJ.

18
19
20
21
22
23
24

VIDEO OUT

2
3
4
5
6
7
8
9
10
11
12

SYNC IN

VC
VB
VA
BPFIN (BGt)
APCPHASEADJ.
PD

G-24

RED
GREEN
BLUE
YOUT
B-YOUT
R-YOUT
GND
VIDEO IN
PCP IN (FPI)
HDPIN
YS IN (OVENABLEI)
VCC

•

•

0

BA7230LS Test Layout
Component Side

E
o
_VIDEOOUT

o

•
•
•

• •
BA7230LS Test Layout

Solder Side

G-2S

004 X

ITT

<4:;

950 985

ill

it"

~70

100
172

025

rOle

1

r=r

t

tWlJOOll!JOOll!l1JllIl(JmtT,~ 010

, '5

GSP500 Physical Specifications
(All dimensions are in inches)

28

~---220

055

09&9

BA7230LS Physical Specifications
(All dimensions are in millimeters)

G·26

Adjustment Features
GSP500

BA7230LS

Set the GSP500 for non-NTSC operation(any
VGA mode). Adjust the variable capacitor (between pins 48 and 49 of the GSP500) until pin 65
of the GSP500 reads 14.31818 MHz. If you are
unable to adjust it far enough, you may have to
increase or decrease the size of the capacitor parallel to the variable capacitor.

Step 1
Adjust the variable resistor (pin 11 of the
BA7230LS) until pin 11 reads 3.9 volts DC.

Step 2
Place GSP500 in genlock mode. Attach a vectorscope to the video output connector. Create a colorbar pattern on the computer screen (available
from ICS). Adjust the variable capacitor until the
vectorscope displays the proper phase.

Sources for Specialized Components
Encoders:

Phono Connectors:

BA7230LS
ROHM Corporation
USA Headquarters
8 Watney
Irvine CA 92718
(714)855-2131 FAX:(714)855-1669

901
Keystone Manufacturers
31-07 20th Road
Astoria, NY 11105-2017
(718)956-8900 FAX:(718)956-9040

Delay Lines:
H321LNP-1436PBAB (400nsec)
TOKO America, Inc.
Corporate Headquarters
1250 Feehanville Drive
Mount Prospect, IL 60056
(708)297-0070 FAX:(708)699-7864

Inductors:
RC-875/122J-50 (1.2mH)
Sumida Electric Co., Ltd.
USA Head Office
637 East Golf Road
Suite 209
Arlington Heights, IL 60005
(708)956-0666 FAX:(708)956-0702
B230-52 (22uH)
lW. Miller
306 E. Alondra Blvd.
Gardena, CA 90247-1059
(213)515-1720 FAX:(213)515-1962

Crystals:
143-20 (14.31818 MHz), 036S (3.579545 MHz)
Fox Electronics
5570 Enterprise Parkway
Fort Myers, FL 33905
(813)693-0099 FAX:(813)693-1554

Variable Capacitors:
GKG7R011 (2-5pf)
Sprague/Goodman
134 Fulton Ave.
Garden City Pk, NY 11040
(516)746-1385 FAX:(516)746-1396

Potentiometers:
3321 +R (10K)
Murata-Erie
2200 Lake Park
Smyrna, GA 30080
(404)436-1300 FAX:(404)436-3030
EVM-SOGA01B14 (10K)
Panasonic
Box511
Secaucus, NJ 07096
(201)348-5266 FAX:(201)392-4782

Distributors:
Digi-Key
70 I Brook Ave South
Thief River Falls, MN 56701
(800)344-4539

G-27

G·28

AN502

Integrated
Circuit
Systems, Inc.

•

Application Note

Theory of Operation for a GSP500 Circuit Operating
the VGA display at 2xNTSC Frequency
Introduction

In its minimal configuration the GSP500 with a VGA controller chip puts out both RGB to a VGA monitor and composite
video in the NTSC fonnat. However, due to the fact that NTSC
video is interlaced, the minimal configuration requires that the
VGA controller be programmed for interlaced operation; this
allows the same RAMDAC to be used for both the VGA and
the NTSC outputs (of course the NTSC output also must be
encoded). Unfortunately, the VGA picture IS somewhat degraded by interlacing - and even worse, some VGA monitors
won't lock up to the interlaced signal. If this situation is not
acceptable, a solution is available that only requires a few
additional parts at minimal cost.

The solution is to run the VGA circuitry at exactly twice the
NTSC rate and in a non-interlaced mode. This preserves the
full quality of the VGA display while the VGA is still being
gen-Iocked to an external NTSC signal. Of course, now that
the VGA RAMDAC is running at a higher speed, another
RAMD AC will be required which runs at the NTSC rate. Also,
some means will be required to accept the fast data rate VGA
output and put out the slower rate NTSC data. Under these
circumstances, the VGA circuitry will be producing twice as
much data as can be displayed in NTSC and therefore some of
it will have to be discarded. All ofthe VGA lines are used in
the NTSC frame, but each line is only used for every other
NTSC field. In other words all the odd numbered VGA lines
may be output to NTSC field I and all the even numbered VGA
lines may be output to NTSC field 2 while both odd and even
numbered lines are put out to the VGA display in every vertical
period. The VGA frame rate is then the same as the NTSC field
rate; the NTSC field simply has half as many horizontal lines.

Block Diagram
r-----t-------------~R
I------------'~ G

B
L-------r-------------~TOVGA
monitor

8
8
Read Clock

Video
Data

R
A
M
D
A
C

GSP500

NTSC
Rate
HSYNC
(15.734 kHz)

RIW

L _ _ _+----j-------,

Cont.

3

Dot Clock

2X
VGA

NTSC

VGAHSYNC
31.468 kHz

Logic

Controller

IAN502RevA 1093 I
G·29

Composite
Video
Output

E1

II

AN502
Application Circuit

Further Enhancement

One possible implementation of this idea is shown in the
accompanying schematic. Only the additional circuitry required for the 2xNTSC enhancement is shown. Following is a
detailed description of the operation of the circuit; please refer
to the schematic as you read it.

Although the VGA at 2xNTSC enhancement is better than the
minimal GSP500 configuration, it is still less than ideal with
respect to the NTSC picture quality. It is probably intuitively
obvious to most people that throwing away half the VGA data
will result in a loss of picture quality on the NTSC output. The
practically observed result of this is what is generally known
as "flicker," and it should be noted that this problem plagues
all scan converters and VGA-to-NTSC boards. It is worst when
there is a lot of detail along the vertical axis of the VGA image.
The most annoying example is probably a thin, bright white
horizontal line made up of a single line on the VGA display.
For an example case, imagine that line 100 of the VGA display
contains the white line and the rest of the display is black. Then
the white line would appear somewhere around line 50 of field
2 in the NTSC output, but not at allan field 1. The result will
be a flashing of the line with a period of33.33 ms (due to 30Hz
frame rate). This is visually very noticeable and irritating.
Because of this, many scan converters and VGA-to-NTSC
boards have a "flicker filter." Interestingly, most flicker filters
can be turned off, indicating that they are less than desirable in
some situations.

U5B divides the frequency of the VGA HSync signal VHS by
two, producing a 50% duty cycle square wave with a frequency
of 15.734 kHz. This signal essentially becomes the Write
Enable signal at U4 pin 22 and is also sent to the GSP500 pin
60 as the Horizontal Sync signal. Note that the addition of a
divide by 2 in the overall loop which the GSP500 controls
forces the VGA chip to clock at twice the rate that it otherwise
would, producing a VGA HSync frequency of 31.468 kHz.
U7 is a line buffer memory which can hold up to 910 pixels
with a width of 8 bits; it has individual write and read clocks
with associated address pointers. Programmable logic device
U4 provides a write enable and pointer reset signals to the line
memory. Note that the write clock to U7 (pin 17) is the same
rate as the VGA pixel clock; therefore every VGA pixel will
be written in to the memory when write enable (pin 20) is active
(low). The write enable is only active for every other line,
however, since it is frequency divided by 2 from the VGA
HSync as previously noted. This essentially discards half the
VGA lines each NTSC field, by virtue of the fact that they are
not written into memory. The time to write a complete line into
memory is 1 VGA line time or 31.778I1s. The read clock for
U7 is simply the write clock frequency divided by 2 by U5A.
Thus to read all the pixels out of the memory will require twice
as long as to write them, or 63.557I1s. This is the length of an
NTSC line. Therefore, over the span of 2 VGA lines, I VGA
line is written and 1 NTSC line is read, although the writing
takes place at twice the NTSC rate.

A discussion of flicker filtering and how to implement it with
the GSP500 will be the subject of another application note.

Data read out from U7 at NTSC rate is fed to RAMDAC Ul,
which has its control lines paralleled across the main VGA
RAMDAC, except that the active low read enable (pin 6) is
permanently disabled by tying it to +5V. In this way anything
written to the VGA RAMDAC (such as changes to the palette)
will also be written to Ul, but any reads will not cause a conflict
with the main VGA RAMDAC. The analog RGB outputs of
Ul are sent to the NTSC encoder to produce a composite video
output. U3 provides a reference for the RAMDAC. Instead of
a reference for each RAMDAC, it may be possible to use 1
voltage reference for both RAMDACs in the system if they can
be configured to use a voltage reference as shown in the
schematic.

G-30

To Ckay Campara
DATOO To VGA Chip
Palata Da10

RAMO[OO 07]

DAT07

'1
U7
+5V

UP042101

~02

U3

W317
OAT[OO 07]

74HC04

U58
74HC74
U5D

~:~~:~~:' c~~~~
0..0..0..0..0..0..0..0..

U1
B1476

C'l

.:..
....

oc

SC11483CV

To

GSP600

RAM-OAC

Pin 24 VCC
P,n 12 GNO

Pin 60

't

:gUI
5

OPA 130

U5A
74HC74

+5V

C4

~UF

oiL
74HC04

U6E

U6F

~JL
74HC04
Pin 14 vec
Pin 7 GND

74HC04
To Data Bus
+80B<0> Thru +808<7>

epU[OO 12J
---

~~~

II

II

VREFF-+---i

I

I

I

I

To Eoood"c

AN502
CRTC Registers
I

VIDEO MODES

INDEX

REGISTER

~

HT

~~ 02

I

00

01

02

03

04

05

06

07

OD

OE

OF

10

II

12

13

**

35

35

6B

6B

35

35

62

6C

35

62

62

62

62

62

62

62

4F

4F

04

4F

50

50

50

50

HDE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

SHB

i 2A

28

57

57

2A

2A

50

54

2A

50

50

03

EHB

95

96

8B

8B

96

96

85

8;T9;i

85

85

85

~

85

84

04

SHR

2E

2E

5D

5D

2F

2F

58

5D

58

58

58

54 I 57

58

57

AO

AO

8C

8C

80

80

9B

83

82

k

I

EHR

I

2F
I

80

I

9B

06

VT

OB

OB

OB

OB

OB

OB

OB

OB

OB

°ll_

07

OVERFLOW

3E--

3E

3E

3E

3E

3E

3E

3E

3E

3E

08

PRS

00

00

00

00

00

00

00

00

00

00

09

MSL

4F

4F

4F

4F

CI

CI

CI

4F

CO

CO

INDEX
~

-

I
-~C-S~--+-O=D- I
cr

OC

SAH

!

m

~
_OB

82

9B

OB

OB

3E . 3E

3E

3E

~

00

00

00

00

00

40

40

I 40

I 40

CO

OB

OB

1

~:

II

~i
40

I

~~lll·

---,~~---'~~r-~'---~-'---~'--~'---~,-~'--~'--~'--~'--~-'-~'-~-'--

I
I

**

03' 04 i os
00
00
00

06
00

07
OD

OD
00

DE
00

OF
00

10
00

II
00

12
00

13
00

00

00

00100

00

00

00

00

00

00

00

00

~-,0""0-+-,0"0,-+-,0"."0-+-,0""0,--+---,0,,,0,--+~0.,,-,0,--+1--,,,00,--+_-,,,00'--j--"00'--j~00''--j_-,,00,,-+ 00

00

00

00

00

@

50

VIDEO MODES

REGISTER

OA

I

4F

i

01
02
DODD

00100

00

1

00100

II

I
II---'O~D,--II--~~-",S,-,A,=-L~~~++--~-"o",o-+.
-,0""0-+-,0"."0-+-,0""0,-+-,0",0,-+~0",0,--+~0,,,0,--+'1--,,,00,--+--"00'--j--"00'--j~00"---j~00,,---f--"0'"-0-+--"O:".O-+-",OL~L
iI OE I
CLH
0°
000
0 I 0°0 I 0000
00
00
00 I 00
00
00
00
00
000
00
oo_~
00
0
0
I

Lo~

I

CLL

I'

_.

00000010000

00

00

00

000000

VIDEO MODES

INDEX

-

REGISTER
VRS

10

00

01

02

03

04

05

06

07

OD

OE

OF

10

II

12

13

**

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

EF

87

88

I

II

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

12

VDE

SF

8F

SF

8F

8F

SF

SF

8F

8F

8F

5D

5D

DF

I DL
~

13

OFFSET

14

14

28

28

14

14

28

2S

14

2S

28

28

28

14

UNDERLINE

IF

IF I IF

IF

00

00

00

IF

00

00

OF

OF

00

B8

C2

C2

B8

C2

C2

9F

9F

EO

EO

05

05

E3

05

05

CA

CA

OC

OC

05

-~f---

28

28

50

00

40

6()_

c2TEO

SVB

B8

B8

B8

C2

16

EVB

E3

E3

E3

E3

05

17

MC _ _ ~...L ~~3
LC
FF
FF i FF

A3

A2

A2

C2

A3

E3

E3

E3

E3

E3

E3

A3

FF

FF

FF

FF i FF

FF

FF

FF

FF

FF

FF

FF

18

INTERLACE

L-*-

I

i

,

S7
DF

OC

I

AB

I

FF

I

I

* =Interlace Bit must be turned off for all modes

General Register

'b~:r-

VIDEO MODES

t~~- RE~G~I~S~T~ER~__-+-_~-+-~-+_=-+~-+~-+~-+~'-+~-+~'--+~'--+~'--+~'--+~'--+~~~"---I--~I
00

MISCOUT

#
23 = GenLock (GL)
27 = OVerlay (OV)
2B =Video Only (VO)
2F = Graphics Only (GO)

@

22 =GenLock (GL)
26 = OVerlay (OV)
2A =Video Only (VO)
2E = Graphics Only (GO)

G·32

AN502
Sequence Registers
I

VIDEO MODES

INDEX I
00

REGISTER
CLKMODE

I

00

I

01

09

I

09

I

02

I

03

I

04

L 01 J 01 L 09

I

05

I

06

I

07

I

OD

I

OE

I

09

I

01

I

00

I

09

I

01

I

OF I 10 I 11

!

** = 640 x 480 x 256 colors

Source Code for PLD U4 (GAL20V8) in CUPLTM Language
2ntsc;

Name
Partno
Date
Revision
Designer
Company
Assembly
Location

XXXXX;
12/07/92 02:12pm;
02;
Todd K. Moyer;
Integrated Circuit Systems;

XXXXX;
XXXXX;

j***************************************************** ******************/

1*
1* VGA

@

*1
*1
*1
*1

2xNTSC rate controller

/*
/*
j***************************************************** ******************/

*1

/*
/* Allowable Target Device Types: g20v8
/*

*1
*1

/*********************************************************************** /

/** Inputs **1

Pin 1
Pin 2

clock

Pin 12
Pin 13
Pin 24

GND
!OE
VCC

,

h~sync~NTSC

;

1* VGA p-clock
1*

*1
*1

1*
1*
1*
1*
1*

*1
*1
*1
*1
*1

/** Outputs **1

Pin
Pin
Pin
Pin
Pin

[15 .. 18]
19
20
21
22

[HSN~SO .. 3];
!line~start;
!write~enable~B;
!write~enable~A;
Iwrite~enable;

used by state machine
pointer reset line mem, act 10
not used by 2xNTSC
not used by 2xNTSC

/** Declarations and Intermediate Variable Definitions **1

Field

State~HSync

= [HSN~SO .. 3];

1** Logic Equations **1

G-33

12 I 13

L 01 I 01 L 01 I 01 J

01

I

**

I 01

AN502
1** State machine definition **j
Sequence State_HSync
{
present 0
if h_sync_NTSC next 1
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_NTSC next 0
out write_enable;
present 1
if h_sync_NTSC next 2
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_NTSC next 0;
present 2
if h_sync_NTSC next 3
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_synch_NTSC next 0;
present 3
if !h_sync_NTSC next 4;
/* out write_enable; *j
if h_sync_NTSC next 3
out write_enable_A;
present 4
if !h_sync_NTSC next A;
if h_sync_NTSC next 3;
present A
if !h_sync_NTSC next 5;
if h_sync_NTSC next 3;
present 5
if h_sync_NTSC next 6
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5
out write_enable;
present 6
if h_sync_NTSC next 7
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 7
if h_sync_NTSC next 8
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 8
if !h_sync_NTSC next 9;
/* out write_enable; *j
if h_sync_NTSC next 8
out write_enable_B;

G-34

II

AN502

present 9

if !h_sync_NTSC next B;
if h_sync_NTSC next 8;
present B

if !h_sync_NTSC next 0;
if h_sync_NTSC next 8;
present C
next 0;
present D
next 0;
present E
next 0;
present F
next 0;

Bill of Materials for 2xNTSC
Item

Qty

1

1

74HC04

Description

Part Name

Manufacturer

HEX INVERTER

Motorola

2

1

74HC74

DUAL D FLIP FLOP

Motorola

3

I

SC11483CV

RAM-DAC

Sierra

4

1

GAL20V8

PLD

Lattice

5

1

LM317

Adjustable Regulator

National

6

1

UPD42101

9lOx8 FIFO

NEC

7

7

CAP

.11lF Cap
240 ohm

8

1

R1I4W

9

1

R1I4W

150 ohm

10

3

R1I4W

24 ohm

G·35

-

--

II

G·36

•

AN503

Integrated
Circuit
Systems, Inc.

Application Note

Flicker Reduction Circuit for use with the GSP500

Introduction
Although a minimal confIguration GSP500 VGAINTSC system uses all of the lines of the graphics image to generate the
NTSC picture, the resulting NTSC display is not (and cannot
be) as good as the original VGA display. Despite the fact that
all the lines are used, on the standard non-interlaced VGA
display every line is used for every vertical period of about 16.7
ms, while it takes twice as long to put out all the lines to the
NTSC picture (33.33 ms). This is accomplished in practice by
one of two ways: I) InterlacIng the VGA (slowing it down to
NTSC rates), or 2) using odd numbered lines for odd NTSC
fields and even numbered lines for even fields, essentially
discarding half the lines that are output from the VGA (see the
Application Note, AN502: Theory of Operation for a GSP500
Circuit Operating the VGA Display at 2 x NTSC Frequency).

It is probably intuitively ObVIOUS that either slowing the VGA
down or throwing away half the VGA data will result in the
NTSC output looking less pleasing than the standard VGA
display. The practically observed result of this is what is
generally known as "flicker," and it should be noted that this
problem plagues all scan converters and VGA-to-NTSC
boards; it is a fundamental limitation of the NTSC standard. It
is worst when there is a lot of detail along the vertical axis of
the VGA image. The most annoying example is a thin, bright
white horizontal line made up of a single line on the VGA
display. For an example case, imagine that line 100 of the VGA
display contains the white line and the rest of the display is
black. Then the white line would appear somewhere around
line 50 of field 2 in the NTSC output, but not at all on field I.
The result will be a flashing of the line with a period of 33.33
ms (reciprocal of the 30 Hz frame rate). This is very noticeable
and quite irritating to the eye.
Knowing that displaying a VGA image on an NTSC monitor
is at best a compromise, we would at least like to achieve the
best possible performance from the conversion. Because of
this, most scan converters and VGA-to-NTSC boards have a
"flicker filter." It is enlightening to note that most flicker filters
can be turned off, indicating that they are less than desirable in
some situations. In fact, they reduce the spatial "bandwidth"
in the vertical direction, or in other words reduce the vertical
resolution. A particularly simple and effective flicker reduction scheme (which can be implemented in software) is to
repeat every other VGA line in both fields of the NTSC signal.
This method, however, requires that half the VGA lines never
get to the NTSC display; in other words the vertical resolution
is cut in half.

A single honzontal line in the VGA image has only a 50/50
chance of being displayed in NTSC, depending on which line
number it appears on. Obviously, this method leaves a lot to
be desired, since some details in the VGA image can be
completely absent from the NTSC signal; most people would
judge it unacceptable.
You can get a feel for how a better typical flicker filter works
by thinking about the example above of a single white horizontal line on scan line 50 of field 2. Imagine "spreading" the line
so that some of it spills into the scan lines adjacent to the
original line. In an interlaced system such as NTSC this means
redUCIng the brightness ofline 50 of field 2 (thereby makIng it
gray), and putting some darker shade of gray into lines 50 and
51 of field 1, which are above and below line 50 of field 2,
respectively, once the complete frame has been scanned. If
done properly, in the right proportions, and viewed from a
sufficient distance, the new wide line looks to be of the same
brightness as the original single white line. This can significantly reduce the flicker, since there is no longer the situation
of black on field I and white on field 2 rapidly alternating.
However, as you can imagine, any rapid vertical transitions
would also become smeared or blurred with such a scheme.
The typical complaint is that when trying to display text on an
NTSC display, a flicker filter will make the text less readable
(if it remains readable at all). This type of flicker reduction
works best if only the luminance portion of the signal is
filtered, since the mixing of several VGA lines to make one
NTSC line can significantly change the saturation and hue of
the color displayed, seriously altering the picture when compared with the VGA display. It is primarily changes in luminance level that cause flicker, so that leaving the chrominance
portion of the signal unchanged does not seriously degrade the
flicker reduction that is achieved, while it does tend to preserve
the look of the image.
To boil all this down, there is a trade-off between flicker
reduction and vertical resolution, and it bears repeating that it
is a practical impossibility to make an NTSC image look just
as good as a high resolution VGA image. To try and work
around this trade-off, some sophisticated flicker filters are
"adaptive," which essentially means that they will dynamically
turn themselves on when especially needed to reduce flicker
and off when the loss of vertical resolution is especially detrimental. Predictably, this approach is rather expensive and
takes up a lot of circuit board space, at least until the time when
this function is incorporated into a monolithic integrated circuit. At any rate, a flicker filter of the more basic variety is
presented here for use with GSP500 applications.

IAN503RevB0994
G-37

E1

II

AN503
Application Circuit
In the accompanying schematic and block diagram an implementation of a simple luminance-only flicker filter which
works with the GSP500 in a VGA-to-NTSC system is shown.
The schematic details only the portion of the system specific
to the flicker filter function, since the VGA portion will vary
depending on the VGA chip used. Please refer to the schematic
when reading the following detailed circuit description.

V8B divides the frequency of the VGA_HSYNC signal VHS
by two, producing a 50% duty cycle square wave with a
frequency of 15.734 kHz. This signal essentially becomes the
Write Enable signal at V5 pin 22 and is also sent to the GSP500
pin 60 as the Horizontal Sync signal NTSC_RA TE_HS. Note
that the addition of a divide by 2 in the overall loop which the
GSP500 controls forces the VGA chip to clock at twice the rate
that it otherwise would, producing a VGA HSync frequency
of 31.468 kHz.
V2 is a line buffer memory which can hold up to 9lD pixels
with a width of 8 bits; it has individual write and read clocks
with associated address pointers. Programmable logic device
V5 provides a write enable and pointer reset signals to the line
memory. Note that the write clock to V2 (pin 17) is the same
rate as the VGA pixel clock; therefore, every VGA pixel will
be written in to the memory when write enable (pin 20) is active
(low). The write enable is only active for every other line,
however, since it is frequency divided by 2 from the VGA
HSync as previously noted. This essentially discards half the
VGA lines each NTSC field, by virtue of the fact that they are
not written into memory. The time to write a complete line into
memory is I VGA line time or 31.778J.lS. The read clock for
V2 is simply the write clock frequency divided by 2 by V8A.
Thus, to read all the pixels out of the memory will require twice
as long as to write them, or 63.557I!s. This is the length of an
NTSC line. Therefore, over the span of 2 VGA lines, I VGA
line is written and I NTSC line is read, although the writing
takes place at twice the rate.

Data read out from V2 at NTSC rate is fed to RAMDAC V9,
which has its control lines paralleled across the main VGA
RAMDAC, except that the active low read enable (pin 6) is
permanently disabled by tying it to +5V. In this way anything
written to the VGA RAMDAC (such as changes to the palette)
will also be written to V9, but any reads will not cause a conflict
with the main VGA RAMDAC. The analog RGB outputs of
V9 are sent to the NTSC encoder to produce the chrominance
component of the composite video output. V6 provides the
required voltage reference to V9. Also, the RGB outputs from
V9 are combined by resistor matrix in the right proportions to
create a luminance signal which can be summed with the
adjacent lines' luminance signals, thereby spatially lowpass
filtering the luminance signal in the vertical dimension.
Vp to this point the circuitry described is basically the same as
is required to make the VGA run at 2 x NTSC rates (see the
Application Note AN502: Theory of Operation for a GSP500
Circuit Operating the VGA Display at 2 x NTSC Frequency).
Note that there are an additional 2 line buffers (V3 and V4), 2
RAMDACs (VlDand VI), and 2 current references (V7A, QI,
and Q2). The additional 2 line buffers store the VGA lines
before and after the current line being output via V2 and V9.
The RGB current outputs from the RAMDACs VlD and VI
are connected together, summing the two sets ofRGB currents
together. The combined RGB signals from VlD and VI are
then matrixed together in the proper proportions to produce an
adjacent-lines luminance signal. This signal amplitude is independent of the main luminance signal so that the ratio of
adjacent line to main line luminance can be set to any desired
value, primarily by adjusting Rl, which controls the reference
currents into VIO and VI.

G·38

II

AN503
-----l

'
I

VGAHORlZsvC

VGA
NTR

VGARATE

i---'--l .-

_-+I"

I-V;,;;IO;;;'O;";O;,;;AT;,;;A_";;',:,,I
)

O:1

---------Joo

RAMDAC :____

H"_ -

...

RGB TO VGA MONITOR

r{-----,,:--------.

~~ 1"':~'
-~REAO
DIV .
i
~BY2

\

CLOCK

L -__

Figure 1
The two luminance signals are connected together, summing
them at the input to amplifier VII. Vll then makes up for the
resistive losses in the RGB matrices and drives the luminance
delay line, whose output is the luminance component of the
encoded composite signal. Most encoders have a luminance
output and input which allows for an external delay line; not using
the output provided while driving the input with an alternate
luminance signal of the right amplitude, delay, and polarity allows
convenient summing with the chrominance signal generated by
the encoder to create the composite video signal.

L

l'-----_J

WE-U3
WE-U4

Programmable logic chip VS controls the writing ofVGA lines
into the line buffers such that V2 receives every other line, V3
receives every fourth line, and V4 receives every fourth line,
as shown by the timing diagram in Figure 2. Note that only one
line buffer is write enabled at a time and every line is written
to a line buffer. With this scheme V2 always contains the main
VGA line which is going out to the NTSC encoder, while V3
and V4 contain the lines adjacent to the main line. The
CVPLTM language source code for PLD VS is included later in
this note.

l__ J

-L~

31.778uS
1 VGA LINE
63.556 uS
1 NTSC LINE

Figure 2
G-39

II

AN503
All ofthe line buffers are continuously read enabled, such that
the RGB signal output to the encoder is a combination of the
main line and the 2 adjacent line signals. V7A, QI, and Q2
make up a dual matched current reference for RAMDACs V I 0
and VI. The amplitude of the adjacent line video signals
summed in with the main line is adjustable with RI; the
optimum value could be determined so that R I could be replaced with a fixed divider to save the cost of the trimmer. The
amplitude of the main line video signal is controllable by the
value ofR6 if it is necessary to adjust the proportion of the main
line signal that gets summed into the final output. The relative
weight of the 2 adjacent line signals in the output is the same
due to the matching of the current references into V I 0 and V I ;
this should be best for most applications since it is symmetrical
about the main line.

BIOS
The video BIOS for the circuit presented here will have to be
modified from the typical GSP500 VGA/NTSC system; therefore, register setups for various video modes are given in
several tables later in this note.

The luminance amplitude is controllable by varying the gain of
VII (set by the value of R22); this should normally be set so
that luminance levels on any given line are somewhat lower
than they would be without filtering. An optional feature shown
in the schematic is the ability to switch off the flicker filtering
with an I/O bit. Switches Q3 and Q4 turn on when the filter is
disabled. In this state Q3 cuts the reference current into V 10
and VI, thereby turning off the adjacent line luminance; while
Q4 boosts the gain of VII (by an amount set by R23) to what
it should normally be without flicker reduction.
Since when a large area of high luminance level occurs, the
video output could exceed the maximum allowed voltage, Q5
and Q6 are used as a positive luminance peak clipper. R27 can
be set so that the peak luminance level at the final video output
is 714 mY.

G-40

II
RGB TO ENCODER ~ TO PRODUCE CHROMINANCE SIGNAL

~

GREEN

~~
LINE BUFFERING/RAMDACS

~

FROM vGA

VGA HSYNC

,

8 BIT VIDEO OAT,
FROMVGA

~

GREEN

VGAHSVNC

VG~VID{O 7 » ) -

8 BIT COLOR NUMBER TO
COLOR KEY(D 7)
COLOR COMPARE CIRCUIT TO GENERATE KEY SIGNAl

RED

PClK

>--

ANALOG PROCESSING

BLUE

RED
GREEN
BLUE

l

FllT_lUM

-_Lu~l ~~~~~OL~~I~:7r?pEU~GNAL

VGA....V1D(O 7)

> - j--COLOR-KEY(O 7)

PARAllEL ACROSS MAl N RAMDAC(O 1 1 ) - RAMDACro 11)
VGA-RATE RAMDAC
NTSC-RATE H SYNC {HALF VGA RA 1:) NTSC RATE HS>--

NTSC_RATE_HS

TO GSP500 PIN 60

FLICKER FILTER ENABLE
/FFEN
BIT FROM OUTPUT PORT
(LO = FLICKER FLiTER ENABLE )

RED_ADJAC

RED_ADJAC

GRN_ADJAC
BLU_ADJAC

GRN_ADJAC

BLU_ADJAC

II

/FFEN

ffl

I

'

Flicker Filter Circuit for GSP500

~

Figure 3 - Flicker Filter Top Level Schematic

Z

C1I

o

W

II

II

ANS03

IRAIIDAC I [} •• 111

."
COLOR

"
,
"~~ ~ ~ ,~
:
"
,
":' ~ !
"" ~ ~
"" "'"'
"" "
"'

IALtOYS

:~
,:"

'

Q

[}

8

UPD42101

QU

02

,
"

'"

7 411(7 4

""

0 •. 1

'j:

"

rt-b
'd'"

12

'"

Yf----y--!'l.l'-fvc It

RC l

"" P

'-t-f+-t---rl--"-,<91

I

, :':

RSTli

2

Q2
Q3

6

RSTR

~: ~ ~

lEU
KEO

'"

~~ ~ ~

ICEY7

+-,'<---,
~~

~
2

I', 1--'-'--++---+-++------t
if

(}

~

-

6

,.','0'"

vee

~;

"

.

22

"'
"'

"~ ;

"g:

~ ~ g~

"
"

f-'L

r

n.

.

I~

~I!

Q3

VN2222

!-----

"'

."

..

RSTII

"

,11

1

"

UP042101

:
"'" ,

." "·

Q2
Q3

3

Q'

g

" ,
'" o-L! " ,
RSTR

,

I.
Q2
--------r:J 2113904

"
'"

':,
"

"23 "'
"'

""

"'
"'

.

~

~

2

~!

"'

"'
"~ : "us

L1L

f-----'-L

'"

RSTII

2L liE

II

"
! '"" :,
"
""" :~
,
, '" tr-<.-" "
,
UP042101

Q2
Q3
Q'

·

. ·
RSTR

Figure 4G·42

AN503

RRRRRRRR
DOPOODCD

01234567

111111

I

8901234511

"

SC1148lCY

COM P

.......!..Q...

Y REF

RB

R9

41

47

~: 0

.-!..L-

OPA~

pelt:

R1

47

'REF

1-""-'-+----+

RRRRRRRR
DOCDODeD

01234567

111111

I

6901234511

RIO

Rll

R12

33

33

33

--..!..Q..... pelt:
0000

LLLL

0123

RRRRRRRR
DODOODDD

01234567

--.!..L

pelf(

Ir: 1 l'lr

-11111!

==~: =~:'

T

l..LU-_-'--~----'

Flicker Filter Line Buffering/Ramdacs
G-43

EI

AN503

.23

I~

".

FE.

1K

1K

...

Q'

Y 112222

...

-*-

.., ...

'""
+ 12 y

•
.N
PROPER
fOR DELAY

Cll

f--1~

---t •

8.21C

RI'

Cl.

H~
-12'

-4. lit:

Rl7
l

•

Ull
ADall

.2K

L III E OL1

.25

Del.y L f n •
F I LT

1. 21C

T

...

l . 211:

4-

RIO

RI.
C.31e

"0

'2K

...

• 00

LUNIIUIICE
THRESHOLD

0"

CLIP

"T

-K

.00

Q,
2113906
I~

~

Q'

2113tU

.1

CI'I

."

o4.7iC

-OY

Figure 5 - Flicker Filter Analog Processing

G-44

INPED".C!

400 n s

8.2IC

+5Y

DEPEIO

TERIlIIATIO_

OL1

7
• IS

VALUES

lO.

ANS03
CRTC Registers
VIDEO MODES
REGISTER

INDEX

00

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

**

35

35

6B

6B

35

35

62

6C

35

62

62

62

62

62

62

62
4F

00

HT

01

HDE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

4F

4F

4F

04

02

SHB

2A

28

57

57

2A

2A

50

54

2A

50

50

50

50

50

50

50

03

EHB

95

96

8B

8B

96

96

85

8B

96

85

85

85

84

84

85

84

i

I

04

SHR

2E

2E

5D

5D

2F

2F

58

5D

2F

58

58

58

54 I 57

58

57

05

EHR

AO

AD

8C

8C

80

80

9B

83

80

9B

9B

9B

82

82

9B

82

06

VT

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

OB

DB

DB

OB

DB

OB

07

OVERFLOW

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

08

PRS

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

09

MSL

4F

4F

4F

4F

CI

CI

CI

4F

CO

CO

40

40

40

40

CO

40

INDEX

REGISTER

00

01

02

03

04

05

06

07

OD

OE

OF

10

II

12

13

**

OA

CS

OD

OD

OD

OD

00

00

00

OD

00

00

00

00

00

00

00

00
00

i

I
I

il

VIDEO MODES

OB

CE

OE

OE

DE

OE

00

00

00

OE

00

00

00

00

00

00

00

oc

SAH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OD

SAL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OE

CLH

00

00

00

00

00

00

00

00

00

00

00

00

00

00

OF

CLL

00

00

00

00

00

00

00

00

00

00

00

00

00

00

INDEX

REGISTER
00

01

02

03

04

05

06

07

aD

DE

OF

10

II

12

13

**

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

EF

I

;Wo~00

00

II

VIDEO MODES

10

VRS

11

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

87

88

87

12

VDE

8F

8F

8F

8F

8F

8F

8F

8F

8F

8F

5D

5D

DF

DF

8F

DF

13

14

I

OFFSET

14

14

28

28

14

14

28

28

14

28

28

28

28

28

28

50

UNDERLINE

IF

IF

IF

IF

00

00

00

IF

00

00

OF

OF

00

00

40

60

B8

C2

C2

9F

9F

EO

EO

C2

EO

E3

05

05

CA

CA

OC

OC

05

OC

E3

A3

AB

FF

FF

FF

15

SVB

B8

B8

B8

B8

C2

C2

C2

16

EVB

E3

E3

E3

E3

05

05

05

17

MC

A3

A3

A3

A3

AZ

AZ

C2

A3

E3

E3

i E3

E3

E3

18

LC

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

*

INTERLACE

I

i

* = Interlace Bit must be turned off for all modes

General Register
I

REGISTER

I

MISCOUT

00

I

VIDEO MODES

INDEX I

r---,---,---,---,---,---,---,---,---,---,---,---,---,---,----,--~Il
00
#

#
23 = GenLock (GL)
27 =OVerlay (OV)
2B =Video Only (VO)
2F =Graphics Only (GO)

I
I

OIl
#

I

ozi

03

I

#

#

I

I

04

J

05

J

06

#

I

#

I

#

@

22 =GenLock (GL)
26 = OVerlay (OV)
2A =Video Only (VO)
2E = Graphics Only (GO)

G-45

1 07
I

@

l

I

OD
#

I
I

OE
#

I
I

OF
@

I
I

10
#

I
I

11

#

I
I

12
#

I
I

13
#

I ** I
I # I

AN503
Sequence Registers
VIDEO MODES

INDEX

REGISTER
00

00

CLKMODE

09

I
I

01
09

I
I

02
01

I
I

03
01

I
I

04
09

I
I

05
09

I
I

06
01

I
I

07
00

I
I

OD
09

I
I

OE
01

I
I

OF
01

I
I

10
01

I
I

11
01

I
I

12
01

** =640 x 480 x 256 colors

Source Code for PlD US (GAl20V8) in CUPlTM language
Name
Partno
Date
Revision
Designer
Company
Assembly
Location

ff;
ff01 ;

1/20/93;
01 ;
Todd K. Moyer;
Integrated Circuit Systems;
Flicker Filter;
U5;

/***********************************************************************/

*1

1*

1* VGA @ 2xNTSC rate controller with basic line flicker filtering
1*
1*

*1
*1
*1

/***********************************************************************/

1*
1* Allowable Target Device Types: g20v8
1*

*1
.. 1
*/

/***********************************************************************/

/** Inputs **1
Pin
Pin
Pin
Pin
Pin

1
2
12
13
24

clock
,
h_sync_NTSC ;
GND
!OE
VCC

/* VGA PCLK signal
/*

*1
*1

/* used by state machine

/** Outputs **1
Pin [15 .. 18]
Pin 19

[HSN_SO .. 3];
!line_start;

1* pointer reset line mem, act 10

*1
*1

Pin 20
Pin 21
Pin 22

!write_enable_B;
!write_enable_A;
!write_enable;

/*
/*
/*

*1
*1
*1

/** Declarations and Intermediate Variable Definitions **1
Field

= [HSN_SO .. 3];

1** Logic Equations **1

G·46

I
I

13
OJ

I **
I 01

II

AN503

/** State machine definition **/
Sequence State_HSync
{

present 0
if h_sync_NTSC next 1
out line start out line startAS
out write_enable out write_enable_A;
if !h_sync_NTSC next 0
out write_enable;
present 1
if h_sync_NTSC next 2
out line_start out line_startAS
out write_enable out write_enable_A;
if !h_sync_NTSC next 0;
present 2
if h_sync_NTSC next 3
out line_start out line_startAS
out write_enable out write_enable_A;
if !h_synch_NTSC next 0;
present 3
if !h_sync_NTSC next 4;
/* out write_enable; */
if h_sync_NTSC next 3
out write_enable_A;
present 4
if !h_sync_NTSC next A;
if h_sync_NTSC next 3;

II

present A
if !h_sync_NTSC next 5;
if h_sync_NTSC next 3;
present 5
if h_sync_NTSC next 6
out line_start out line_startAS
out write_enable out write_enable_B;
if !h_sync_NTSC next 5
out write_enable;
present 6
if h_sync_NTSC next 7
out line start out line startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 7
if h_sync_NTSC next 8
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_NTSC next 5;
present 8
if Ih_sync_NTSC next 9;
/* out write_enable; */
if h_sync_NTSC next 8
out write_enable_B;

G-47

AN503
present 9

if !h_sync_NTSC next B;
if h_sync_NTSC next 8;
present B

if !h_sync_NTSC next 0;
if h_sync_NTSC next 8;
present C
next 0;
present 0
next 0;
present E
next 0;
present F
next 0;

Bill of Materials
Item

Qty

1

15

Reference

Part

C1, C2, C3, C5, C6, C7,
C8, C9, ClO, Cll, C12,
C13, C14, C15, C16

.1!!F

lOUF

2

1

C4

3

1

DLl

4

2

Q1,Q2

2N3904

5

2

Q3,04

VN2222

6

2

05,06

2N3906

7

5

R1, R14, R21, R23, R24

1K

8

1

R2

120

9

1

R3

100

10

2

R4,R5

121

400ns

11

1

R6

150

12

3

R7, R8, R9

47

13

3

RIO, Rll, R12

33

14

3

R13, R27, R28

200

G·48

Item

Qty

Reference

Part

15

2

R15, R18

8.2K

16

2

R16, R19

4.3K

17

2

R17,R20

22K

18

1

R22

680

19

2

R25,R26

l.2K

20

1

R29

21

3

Ul, U9, UlO

SC1l483CV

22

3

U2, U3, U4

UPD42101

23

1

U5

GAL20V8

24

1

U6

LM317

25

1

U7

TL072

26

1

U8

74HC74

27

1

Ul1

AD8ll

4.7K

GSP600

Integrated
Circuit
Systems, Inc.

VGA/PAL Video Genlock Processor with Overlay
Overview

Features

The GSP600 allows the text and graphic images of VGA and
Super VGA controllers to be displayed on standard PAL
televisions or recorded on a VCR. Additionally, the GSP600
accepts external video input from a camcorder or a VCR and
will synchronize (genlock) the VGA or Super VGA controller
to the external video. The GSP600 also allows VGA and video
images to be overlaid on the same television screen. The
GSP600 meets or exceeds all PAL broadcast standards for
timing accuracy and allows the VGA controller to maintain
true PAL compatibility at all times. The GSP600 is compatible
with virtually all VGA controllers. Tseng Labs, Oak Technology, Trident Microsystems, S3, and NCR have BIOS support
available for the GSP family of products.

•
•

9

1

•
•
•
•
•

61

•

"11"""":::::000011
"
g
g
26

Cl

g

g

Cl

Cl

•

Direct input of PAL or S-Video (S-VHS and Hi-8 video).
On board PALlS-Video sync and black burst generation
for local video operation. Video chroma burst separate
with 4.433618 MHz and 17.734475 MHz phase locked
outputs.
Meets or exceeds all timing specifications for studio and
broadcast television.
High efficiency PALlS-Video conversion that maintains
VGA perfonnance.
Dynamic overscan and underscan adjustment of PALlSVideo modes under BIOS and/or software control.
Software selection between all VGA and PALlS-Video
modes.
PALlS-Video conversion support for all VGA and Extended VGA modes with 600 or fewer lines.
Built-in dot clock circuitry to eliminate crystal oscillators
for VGA,plus extended VGA operation up to 135 MHz.
Low power consumption, ideal for laptop computers.

Cl

II

E:OOOOOOOOOOOOOOOOOE: 44
27

43

S8-Pin PLCC
K-10
<> YIPN.

=

<> C

IIldtto

GSP600

I-----'

Signals

~> YIPAL

~e C

~
=
-

'-->

~

Y/PN. ~I

RGB-to-PAL
encoder

7

°-'1

VGM'N.

Dot
Clock

sync

II

f8I D-15
~

Uodo
Select

VIlA

sync
"ROO'll

VGA
Controller

~

I-----'

IGSP600RevB0994
G-49

RAMDAC

GSP600
Internal Block Diagram
VIDEO INPUT I

~----------------------------~ ~

VIDEO INPUT 2

TI_

VIDEO
8IGNAI.
PROCE88ING
AND

CONTROl.
AND

SYNC

MODE
SElECT

\lOA

LOOIC

The GSP600 can be thought of as an extremely sophisticated
dot clock generator. In its simplest form, the GSP600 will
generate all of the dot clock frequencies necessary to drive
VGA and Super VGA controllers. The different frequencies
are selected with the MODE SELECT LOGIC from the VGA
chip. Selection is similar to selecting frequencies on any of the
ICS dot clock generators (i.e., ICS1394, ICS1494, ICS1561,
ICS2494, etc.). Additionally, there are fourreserved frequency
addresses. These are labeled GL (genlock), OV (overlay), va
(video only), and GO (graphics only). Choosing any of these
addresses will switch the GSP600 from VGA mode to PAL
mode. Under PAL mode, the GSP600 accepts vertical and
horizontal VGA SYNC from the VGA controller and uses the
sync to generate and adjust the VGA DOT CLOCK. The
GSP600 will automatically vary the frequency of the dot clock
in order to synchronize the VGA sync signals with a PAL
reference signal. This reference signal can be derived from a
video device (such as a camcorder) connected to VIDEO
INPUT 1 or VIDEO INPUT 2. The GSP600 provides an
RGB-to-PAL encoder with the VIDEO OUTPUT signal
which is either VIDEO INPUT 1, VIDEO INPUT 2, or an
internally generated black burst signal. All of the necessary
ENCODER LOGIC signals to properly drive the encoder are
provided by the GSP600.

~R
PIXEL

ClOCK
REalAATIDN

CORRECTION

Theory of Operation

If============>

GENlOCK

SYNC

\lOA
DOT
ClOCK

SWITCH

(OVENAIIlE)

1).15

SYNC CI43

?44

PAL sync
VGA Hsync
VGA Vsync

624

10

625

11

12

13

PAL sync
238

VGA Hsync
VGA Vsync

260

261

262

263

20

PAL sync
VGA Hsync
VGA Vsync

G·56

21

22

23

24

25

26

27

II

GSP600

Electrical Specifications
Operating temperature range O°C to 70°C

Electrical Characteristics
PARAMETER

SYMBOL

MIN

TYP

MAX

Analog Supply

Avoo

4.5

5.0

5.5

Volts

Digital Supply

4.5

5.0

5.5

Volts

Operating Current - VGA Mode

Dvoo
100 (VGA)

Operating Current - PAL Mode

Ino (PAL)

UNITS

35

rnA

50

rnA

Input Signals
SIGNAL TITLE

PIN #
33

TYPICAL VALUE
I Vp_p

OPERATING CONDITIONS

Y1
CI

35

IVp_p

75 Ohm load

Y2

32

IVp_p

75 Ohm load

C2

34

IVp-p

75 Ohm load

VID1I2

51

TTUCMOS
TTUCMOS

High =Yl,Cl; Low = Y2,C2

PAUSVID

63

VGAVSYNC

61

VGAHSYNC

60

FSO-5

28-23

CIillY

7

PCLK

66

lIES

12

DATAIN

4

CLAMPLEV

31

SYNCTHRS

41

VLE

1

RST/

44

TTUCMOS
TTUCMOS
TTUCMOS
TTUCMOS
TTUCMOS
TTUCMOS

75 Ohm load

High =PAL; Low = S-Video
Positive polarity
Positive polarity
Address/mode select
High =RGB; Low =PAL
Pixel (DAC) Clock from VGA
High =Internal sync
Low =External sync

TTUCMOS
1-1.5 V
CLAMPLEV +0.1 V

Active during DATAFRAME

TTUCMOS
TTUCMOS

Tie to Voo through resistor

G-57

Tie to Von through resistor

II

GSP600
Output Signals
SIGNAL TITLE

PIN#

TYPICAL VALUE

OPERATING CONDITIONS

VSYNCOUT

9

TTL

Positive polaritv during PAL modes

HSYNCOUT

18
64

TTL
IVp_p

Composite sync durinll; PAL modes

VS
HS

16

IVp_p

Positive ~olarity

CS

6

IVp_p

Positive polarity

DOTCLOCK

54

TTL

YOUT

45

IVp-p
IVp_p

75 Ohm load

COUT

43

4.43SC

36

TTL

4.433618 MHz

4XSC

65

TTL

17.734475 MHz

LOCIREM

TTL

High =local' Low =remote

OVENABLE

13
11

TTL

Hill;h =PAL' Low =RGB

VGAlPAL

57

TTL

Positive polarity

75 Ohm load

CB

25

TTL

High =VGk Low =PAL
Positive polarity

ODDIEVEN

2

TTL

High =odd field' Low =even field

VGAOIE

42

TTL

BGt

58

TTL

High =VGA odd field
Low =VGA even field
Negative polarity

FPt

3

TTL

Nell;ative polarity

SCH

68

TTL

Positive polarity

DATAFRAME

10
67

TTL

Lines 10-20

TTL

Active durinll; DATAFRAME

DATAOUT

G-S8

II

GSP600

Dot Clock Selection
The following charts represent two of the many dot clock frequency selection tables supported by GSP600. See the BIOS manual
or contact ICS applications engineering for additional information.

FREOUENCY (MHz)

FS5

FS4 FS3 FS2

FSI

FSO

50.350

0

I

0

0

56.644

0

I

0

I

65.028

0

I

I

0

72.000

0

I

I

I

75.000

I

0

0

0

80.000

I

0

0

I

89.800

I

0

I

0

110.000

I

0

I

I

GenLock

I

I

0

0

OVerlay

I

I

0

I

Video Only

I

I

1

0

Graphics Only

I

1

I

1

FREQUENCY (MHz)

FS5 FS3

FS4 FS2

FSI

FSO

25.175

0

1

0

0

28.322

0

I

0

I

40.000

0

I

1

0

44.900

0

I

I

I

GenLock

I

I

0

0

OVerlay

1

I

0

I

Video Only

I

1

I

0

Graphics Only

1

1

1

1

Ordering Information
GSP600V
Example:

ICSXXXXV

L __
V=PLCC

' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
L---------~a~

rcs, AV=Standard DevlCe, GSP=Genlock DeVice

G-59

E1

GSP600 Frequently Asked Technical Questions.
1. What will the GSP600 do for me?
The GSP600 adjusts the timing of a VGA controller to conform to PAL (television) specifications. The GSP600 accepts
direct video input from video cameras, videodisc players or other video sources and will synchronize (genlock) a VGA
controller to either the external video input or an internal PAL sync generator. The GSP600 also contains a dot clock
generator to eliminate the need for crystal oscillators or other dot clock generators.

2.

How does the GSP600 differ from other genlock devices?

Other genlock devices, such as the Motorola MC1378, are very effective at genlocking two PAL signals together and
are generally used in consumer electronics products such as video window-in-a-window devices. The GSP600 is
specifically designed to genlock a computer graphics controller to PAL video and overcomes all of the incompatibilities
between VGA and PAL. Additionally, the GSP600 contains an PAL sync generator and maintains chrominance phase
lock in local modes. This allows the GSP600 to maintain PAL timing without an external video input. Furthermore, the
sync separator circuit of the GSP600 is designed to satisfy the low jitter tolerances demanded by discriminating VGA
customers.

3.

Isn't genlock simply a phased-lock loop?

Phase locking two similar signals is fairly straightforward as long as phase jitter is not critical. As an example, ICS is
one of the few companies able to successfully build phase-locked loop dot clock generators with low enough phase
jitter for computer graphics display. Additionally, the differences between VGA and PAL signals further complicate the
genlock procedure. The GSP600 has patents applied for for the most advanced computer video genlock methods in
the industry. These methods assure you of the highest possible quality product.

4.

Most Genlock and Overlay products have a lot of discrete components with trimmer
capacitors and potentiometers. All these adjustments can become very expensive in
a mass production environment. How much external Circuitry does the GSP600
require?

Although the GSP600 can be run with no trimmer capacitors or potentiometers, one trimmer capacitor should be used
to meet the PAL frequency tolerance of the chroma burst. This is a free running frequency and is very simple (and
fast) to adjust. Additionally, the GSP600 uses high speed digital Circuitry to eliminate virtually all discrete components.
Only a few external components are needed for full operation.

5.

Do I need an RGB-to-PAL encoder with the GSP600?

Yes, an external RGB-to-PAL encoder is needed. The encoder must be matched to the target audience. The GSP600
can be used under broadcast television scrutiny and most broadcast video equipment perform the encoding entirely
with discrete components. As this may prove too costly and/or may use too much board space, the GSP600 contains
all of the necessary Signals to drive virtually any encoder. The GSP600's generous supply of timing signals will also
drive external circuitry to turn off the encoder for laptop applications.

6. Why do I need the GSP600. Can't I program a VGA controller for PAL sync and just
drive an RGB-to-PAL encoder?
PAL sync contains equalizing pulses, blanking signals and pulse widths that are impossible to create under normal
VGA control. Although marginal display quality is achievable on a television without adhering to the PAL standard,
compatibility with other PAL equipment is compromised. As an example, depending on which edge of horizontal sync
the monitor triggers on will determine how far an incorrect width horizontal sync pulse will skew the screen. Additionally,
it becomes virtually impossible to assure proper chroma burst (SCH) phasing. The GSP600 sync generator meets or
exceeds all PAL broadcast standards for timing accuracy assuring you of maximum compatibility and ultimate quality.

G-60

7. National sells a sync separator for less than $2 while the Brooktree part costs over
$50. What is the difference and how does the sync separator in the GSP600 compare?
The sync separation circuitry in the National part is a simple diode clamp. Although this may be adequate for driving
a picture tube, the lack of noise and jitter immunity make it unsuitable for genlock applications. Additionally, the analog
vertical sync detection circuit of these type of devices will not accurately track a VCR signal. The Brooktree device
represents a mixed-mode approach to sync separation. By utilizing a fast analog circuitry coupled with high speed
digital logic, noise and jitter immunity can be optimized. The GSP600 also uses a mixed mode approach specifically
optimized for genlock operation yet the incorporation of a sync generator allows signal analysis not possible with
other devices.

8.

Is the GSP600 compatible with any VGA controller?

VGA controllers need to have two features to work with the GSP600. First, they need to be able to interlace - If your
controller can display 1024 x 768 resolution, then it can probably interlace (the additional 256K memory is not
necessary). Second, the controller must have at least three clock select lines for external dot clock generator support.
Virtually all current VGA controllers have this feature. Check with your VGA controller manufacturer or ICS if you are
unsure.

9. How do I turn the PAL on and off and control it?
The GSP600 uses the three clock select lines to support 4 VGA clocks and 4 PAL modes. The VGA clocks are available
in 7 different patterns (Le. 25.175, 28.322, 40.000, 65.000 is one pattern). The 4 PAL modes are Genlock, Overlay,
Graphics Only, and Video Only. The selection between any PAL mode or between PAL and VGA is done entirely under
BIOS or software control.

10. Why did you incorporate a dot clock generator in the GSP600?
The GSP600 works by modifying the dot clock input for the VGA controller. It essentially is a dot clock generator
designed for PAL genlock. The dot clock generator is not so much of an extra feature as it is a subset of the genlock
design. Consequently, this unity design assures you of a reliable glitch-free solution.

11. When the GSP600 displays an Overlay, how do I determine which part of the screen
displays graphics and which is VGA?
The GSP600 uses a technique called Color-Key to determine where to display the external video. This Color-Key color
is based on the VGA color number. Therefore, no colors are actually lost. As an example, the background color is
always Color O. When Color-Keying on Color 0, the screen will appear to have a background of the external video.
The actual color that the VGA assigns to Color 0 does not matter. Any of the 256 color numbers can be assigned to
be a Color-Key. Although the GSP600 modifies the Color-Key input, the Color-Key selection is done by an external 8
bit digital compare.

12. Why is the Color-Key selection external to the GSP600?
Color-Key selection is done with an 8 bit compare of the digital RGB signals with a preassigned byte. The digital RGB
data comes from the VGA controller and the preassigned byte normally comes from the IBM bus via a port selection.
The output of this comparison is fed into the CKEY (Color-Key) input of the GSP600. Although this Color-Key method
will satisfy 95% of all customers, the external design allows other schemes with multiple or different comparison
options. Additionally, since all of these signals are already available inside the VGA controller, many manufacturers
have announced plans to incorporate the Color-Key function inside the VGA controller.

13. What about NTSC and/or SECAM compatibility?
ICS has an NTSC version of the GSP600 (the GSP500). In its current implementation, it is pin compatible with the
GSP600 but require different values for the discrete components and will also need a different crystal oscillator.
Although a SECAM version is technically possible, due to the uncertain market potential product development is not
currently underway.

14. Can I look forward to a combination PAL and NTSC product?
Unfortunately, the amount of Circuitry common to both a PAL and an NTSC version is minimal. Separate versions are
currently the lowest cost solution. Although the crystal frequency, some discrete components and the Bios would
have to change, the same board layout could support both standards by simply changing the parts list.

G-61

G

15. Does the GSP600 accept multiple video inputs? What about an S-Video input?
The GSP600 has two independent video inputs. Either input can be used or they can both be disabled. Either input
can be wired to accept either S-Video or PAL. Selection between the two inputs is performed under hardware control.

16. Why doesn't the GSP600 incorporate audio?
The PAL and S-Video baseband signals do not have a provision for audio. This means that the video and audio signals
are completely separate signals at all times. ICS offers audio products for the multimedia market that can be
incorporated into the design but allows the designer maximum flexibility by keeping them separate products.

17. Can I use the GSP600 with an RF modulator?
Yes, but the quality of the image may suffer. When PAL is modulated up to RF frequencies, audio is modulated onto
a 4.5 MHz carrier and the video is limited to a maximum frequency of 4.2 MHz. Although 4.2 MHz may be sufficient
for moving images it can be limiting for high resolution computer graphics. This problem is magnified because the
majority of RF modulators are very low quality devices. Additionally, even if a high quality RF modulation is obtained,
the signal may still be degraded by the RF demodulator inside the television set. ICS does recognize that these
limitations may be outweighed by the user-friendliness and compatibility of the RF standard. High quality RF
modulators are available and the GSP600 does have the necessary signals for support but these issues should be
carefully weighed before implementation.

18. Can the GSP600 display PAL video on my VGA screen?
No, in order to display PAL video at 31.25 KHz, it is necessary to convert PAL into component form, digitize it in real
time, and store at least one frame of video. Although technology exists to accomplish this, the price-to-performance
ratio of these products is too high for mass market acceptance at this time.

19. Is there any question that I forgot to ask?
Yes, when I use a graphics program, I find the borders very distracting yet I need the borders in text modes to
insure that I can read the DOS prompt. Can the GSP600 help me with this problem? The GSP600 has the ability
to adjust the width of the screen totally under Bios control. This means that you can have limited overscan in
mode 13, minor underscan in mode 3 and generous overscan in mode 12. Software drivers can even be written
to dynamically change the screen width with the cursor keys.

20. Does this mean I can change the height of the screen also?
PAL has a fixed number of lines. In order to change the vertical size, the screen data must be compressed or expanded
into fewer or greater lines. This can be accomplished in a text mode by changing the font size or in a graphics mode
with linear interpolation. The GSP600 always maintains an exact one-to- one correlation between the PAL and VGA
line position and therefore does not support vertical sizing.

21. Where do I get a development kit for the GSP600?
Call1CS at (800) 220-3366 for more information. We will put you in touch with a local rep. who will be more than happy
to supply you with a full GSP600 development kit. The ICS full service support organization is always ready to help
you with the latest in Multimedia solutions.

G-62

AN602

Integrated
Circuit
Systems, Inc.

•

Application Note

Theory of Operation for a GSP600 Circuit Operating
the VGA Display at 2xPAL Frequency
The solution is to run the VGA circuitry at exactly twice the
PAL rate and in a non-interlaced mode. This preserves the full
quality of the VGA display while the VGA is still being
gen-locked to an external PAL signal. Of course, now that the
VGA RAMDAC is running at a higher speed, another RAMDAC will be required which runs at the PAL rate. Also, some
means will be required to accept the fast data rate VGA output
and put out the slower rate PAL data. Under these circumstances, the VGA circuitry will be producing twice as much
data as can be displayed in PAL and therefore some of it will
have to be discarded. All of the VGA lines are used in the PAL
frame, but each line is only used for every other PAL field. In
other words all the odd numbered VGA lines may be output to
PAL field 1 and all the even numbered VGA lines may be
output to PAL field 2 while both odd and even numbered lines
are put out to the VGA display in every vertical period. The
VGA frame rate is then the same as the PAL field rate; the PAL
field simply has half as many horizontal lines.

Introduction
In its minimal configuration the GSP600 with a VGA controller chip puts out both RGB to a VGA monitor and composite
video in the PAL format. However, due to the fact that PAL
video is interlaced, the minimal configuration requires that the
VGA controller be programmed for interlaced operation; this
allows the same RAMDACTM to be used for both the VGA and
the PAL outputs (of course the PAL output also must be
encoded). Unfortunately, the VGA picture is somewhat degraded by interlacing - and even worse, some VGA monitors
won't lock up to the interlaced signal. If this situation is not
acceptable, a solution is available that only requires a few
additional parts at minimal cost.

Block Diagram

_v_}-

VClAHSYNC

JWm.\C

~

UNBBUI'PE

B
~HZ

1
0SF600

rG

MONIfOR

BUlB

IIBD

8

DAT

DATA
IN

VClA V SYNC

-

TOVOA

IIBD

VIDEODATA

LWIlAC

our

COtoII'OSITI!
VIDEO OUT
I!NCOOBR ~

BUlB

1

I

L--

3
DOTC1OCX

VOA

IVGA

J2

~

RIW OONTIIOL
2xPAL

r..oarc

~

31.250

1

l'ClJC:

• SYNC

RAMDAC

IAN602RevA0994

G·63

IS

a trademark of Brooktree Corporation

II

AN602
Application Circuit

Further Enhancement

One possible implementation of this idea is shown in the
accompanying schematic. Only the additional circuitry required for the 2xPAL enhancement is shown. Following is a
detailed description of the operation of the circuit; please refer
to the schematic as you read it.

Although the VGA at 2xPAL enhancement is better than the
minimal GSP600 configuration, it is still less than ideal with
respect to the PAL picture quality. It is probably intuitively
obvious to most people that throwing away half the VGA data
will result in a loss of picture quality on the PAL output. The
practically observed result of this is what is generally known
as "flicker," and it should be noted that this problem plagues
all scan converters and VGA-to-PAL boards. It is worst when
there is a lot of detail along the vertical axis of the VGA image.
The most annoying example is probably a thin, bright white
horizontal line made up of a single line on the VGA display.
For an example case, imagine that line 100 of the VGA display
contains the white line and the rest of the display is black. Then
the white line would appear somewhere around line 50 of field
2 in the PAL output, but not at all on field 1. The result will be
a flashing of the line with a period of 40.0 ms (due to 25 Hz
frame rate). This is visually very noticeable and irritating.
Because of this, many scan converters and VGA-to-PAL
boards have a "flicker filter." Interestingly, most flicker filters
can be turned off, indicating that they are less than desirable in
some situations.

V5B divides the frequency of the VGA HSync signal VHS by
two, producing a 50% duty cycle square wave with a frequency
of 15.625 kHz. This signal essentially becomes the Write
Enable signal at V4 pin 22 and is also sent to the GSP600 pin
60 as the Horizontal Sync signal. Note that the addition of a
divide by 2 in the overall loop which the GSP600 controls
forces the VGA chip to clock at twice the rate that it otherwise
would, producing a VGA HSync frequency of 31.650 kHz.

V7 is a line buffer memory which can hold up to 910 pixels
with a width of 8 bits; it has individual write and read clocks
with associated address pointers. Programmable logic device
V4 provides a write enable and pointer reset signals to the line
memory. Note that the write clock to V7 (pin 17) is the same
rate as the VGA pixel clock; therefore, every VGA pixel will
be written in to the memory when write enable (pin 20) is active
(low). The write enable is only active for every other line,
however, since it is frequency divided by 2 from the VGA
HSync as previously noted. This essentially discards half the
VGA lines each PAL field, by virtue of the fact that they are
not written into memory. The time to write a complete line into
memory is 1 VGA line time or 32.0~s. The read clock for V7
is simply the write clock frequency divided by 2 by V5A. Thus
to read all the pixels out of the memory will require twice as
long as to write them, or 64.0~s. This is the length of a PAL
line. Therefore, over the span of 2 VGA lines, 1 VGA line is
written and 1 PAL line is rel!d, although the writing takes place
at twice the PAL rate.

A discussion of flicker filtering and how to implement it with
the GSP600 is the subject of Application Note AN603.

Data read out from V7 at PAL rate is fed to RAMDAC VI,
which has its control lines paralleled across the main VGA
RAMDAC, except that the active low read enable (pin 6) is
permanently disabled by tying it to +5V. In this way anything
written to the VGA RAMDAC (such as changes to the palette)
will also be written to VI, but any reads will not cause a conflict
with the main VGA RAMDAC. The analog RGB outputs of
VI are sent to the PAL encoder to produce a composite video
output. V3 provides a reference for the RAMDAC. Instead of
a reference for each RAMDAC, it may be possible to use 1
voltage referencefor both RAMDACs in the system if they can
be configured to use a voltage reference as shown in the
schematic.

G·64

ToCk.y Compor"
O"TOO - OAT07

To VGA Chip
Potot .. 00 to

RAIoIO[00:07J

U7

+5V

UPD42101

U6A

VeA HO"1 Sync
rrom VCA Chip

~

~

:gg\ H

!

\ \

To GSPCOO

-:-

D
-:-

+sv

" ,r
r1
-:I

U6B

-:-

usc

-:-

Pin 7 CNO

74HCO'

Pin 14 vee
P'li 7 GND

74HCO.
To Ooto Bu,
+808<0> Th," ... 80B<7> ----==="-~

II

To Encod-,

AN602
CRTC Registers
VIDEO MODES

INDEX

REGISTER
()()

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

••

35

35

6B

6B

35

35

62

6C

35

62

62

62

62

62

62

62

00

HT

01

HDE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

4F

4F

4F

04

4F

02

SHB

2A

28

57

57

2A

2A

50

54

2A

50

50

50

50

50

50

50

03

EHB

95

96

8B

8B

96

96

85

8B

96

85

85

85

84

84

85

84

04

SHR

2E

2E

5D

5D

2F

2F

58

5D

2F

58

58

58

54

57

58

57

05

EHR

AO

AO

8C

8C

80

80

9B

83

80

9B

9B

9B

82

82

9B

82

06

VT

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

07

OVERFLOW

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

08

PRS

()()

00

00

00

00

()()

00

()()

()()

00

()()

00

00

00

()()

00

09

MSL

4F

4F

4F

4F

CI

CI

CI

4F

CO

CO

40

40

40

40

CO

40

INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

_.

VIDEO MODES

OA

CS

OD

OD

OD

OD

00

()()

00

OD

()()

00

00

00

00

00

()()

()()

OB

CE

OE

OE

OE

OE

()()

00

()()

OE

00

()()

()()

()()

00

00

00

00
00

OC

SAH

00

00

00

()()

00

()()

()()

00

()()

00

()()

00

00

00

00

OD

SAL

00

00

()()

00

00

()()

00

()()

()()

00

00

00

00

00

()()

()()

OE

CLH

00

()()

00

()()

()()

00

()()

00

00

()()

()()

()()

()()

()()

00

00

OF

CLL

()()

00

00

()()

00

00

()()

()()

()()

00

()()

00

00

00

00

()()

INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

VIDEO MODES

10

VRS

.EF

11

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

87

88

87

12

VDE

8F

8F

8F

8F

8F

8F

8F

8F

8F

8F

5D

5D

DF

DF

8F

DF
50

13

OFFSET

14

14

28

28

14

14

28

28

14

28

28

28

28

28

28

14

UNDERLINE

IF

IF

IF

IF

00

00

00

IF

()()

00

OF

OF

00

()()

40

60

15

SVB

B8

B8

B8

B8

C2

C2

C2

B8

C2

C2

9F

9F

EO

EO

C2

EO

16

EVB

E3

E3

E3

E3

05

05

05

E3

05

05

CA

CA

oc

OC

05

OC

17

MC

A3

A3

A3

A3

A2

A2

C2

A3

E3

E3

E3

E3

E3

E3

A3

AB

18

LC

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

-

INTERLACE

* = Interlace Bit must be turned off for all modes

General Register
VIDEO MODES

INDEX

REGISTER
00

00

MISCOUT

#

#
23 = OenLock (OL)
27 = OVerlay (OV)
2B Video Only (VO)
2F = Graphics Only (00)

=

I
I

01

#

I
I

02

#

I
I

03

#

I
I

04

#

I
I

05

#

I
I

@

=

22 OenLock (OL)
26 = OVerlay (OV)
2A = Video Only (VO)
2E = Oraphics Only (00)

G·66

06

#

I
I

07

@

I OD I
I # I

OE

#

I
I

OF

@

I
I

10

#

I
I

II

#

I
I

12

#

I
I

13

#

I
I

_.
#

II

AN602

Sequence Registers
VIDEO MODES
INDEX

REGISTER

00

CLKMODE

** =

00

I

01

I

02

I

03

I

04

I

05

I

06

I rn I OD I

OE

I

OF

I

10

I

11

I

12

640 x 480 x 256 colors

Source Code for PLD U4 (GAL20V8) in CUPL'IV Language
Name
Partno
Date
Revision
Designer
Company
Assembly
Location

2 PAL;

XXXXX;
12/07/92 02:12pm;
02;
Todd K. Moyer;
Integrated Circuit Systems;

XXXXX;
XXXXX;

/*****************************************************.**** ••• ****** ••• */

/*

*'

/* VGA @ 2xPAL rate controller
/*

*/
*/
*/

/*

/************* •••••••••••• ****** •••••• ******************************* •• */

*'

/*
/* Allowable Target Device Types: g20v8
/*

*/
*/

/************** •••• ********** ••• ***** ••• ** •• ************* ••• ******** •• **/

/** Inputs **/
Pin 1
Pin 2

clock
h_sync_PAL;

Pin 12
Pin 13
Pin 24

GND
IOE
VCC

/* VGA p-clock
/*

*/
*/

/*
/*
/*
/*
/*

*/
*/
*/
*/
*/

/* * Outputs * */
Pin
Pin
Pin
Pin
Pin

[15 .. 18]
19
20
21
22

I

13

I ••

ooloolmlmlooloolmlooloolmlmlmlmlm\m\m

[HSN 50 .. 3];
!line_start;
Iwrite enable 8;
I write-enable-A;
Iwrite=enable;

used by state machine
pointer reset line mem, act 10
not used by 2xPAL
not used by 2xPAL

/** Declarations and Intermediate Variable Definitions

**'

Field

/* * Logic Equations * */

G-67

II

AN602
/** State machine definition **j
Sequence State_HSync
{
present 0
if h_sync_PAL next 1
out line_start out line_startAS
out write_enable out write_enable_A;
if !h_sync_PAL next 0
out write_enable;
present 1
if h_sync_PAL next 2
out line_start out line_startAS
out write_enable out write_enable_A;
if !h_sync_PAL next 0;
present 2
if h_sync_PAL next 3
out line_start out line_startAS
out write_enable out write_enable_A;
if !h_synch_PAL next 0;
present 3
if !h_sync_PAL next 4;
/* out write_enable; *j
if h_sync_PAL next 3
out write_enable_A;
present 4
if !h_sync_PAL next A;
if h_sync_PAL next 3;
present A
if !h_sync_PAL next 5;
if h_sync_PAL next 3;
present 5
if h_sync_PAL next 6
out line_start out line_startAS
out write_enable out write_enable_S;
if !h_sync_PAL next 5
out write_enable;
present 6
if h_sync_PAL next 7
out line start out line startAS
out write_enable out write_enable_S;
if !h_sync_PAL next 5;
present 7
if h_sync_PAL next 8
out line_start out line_startAS
out write_enable out write_enable_S;
if !h_sync_PAL next 5;
present 8
if !h_sync_PAL next 9;
/* out write_enable; *j
if h_sync_PAL next 8
out write_enable_S;

G-68

AN602
present 9

if !h_sync_PAL next B;
if h_sync_PAL next 8;
present B

if !h_sync_PAL next 0;
if h_sync_PAL next 8;
present C
next 0;
present D
next 0;
present E
next 0;
present F
next 0;

Bill of Materials
Item

Qty

1

1

74HC04

HEX INVERTER

Description

Motorola

2

1

74HC74

DUAL D FLIP FLOP

Motorola

3

1

SCl1483CV

RAM-DAC

Sierra

4

1

GAL20V8

PLD

Lattice

5

1

LM317

Adjustable Regulator

National

6

1

UPD42101

910x8 FIFO

NEC

7

7

CAP

l!!ECap
240 ohm

Part Name

8

1

R1I4W

9

1

R1I4W

150 ohm

10

3

R1I4W

24 ohm

G-69

Manufacturer

E1

G-70

•

AN603

Integrated
Circuit
Systems, Inc.

Application Note

Flicker Reduction Circuit for use with the GSP600

Introduction
Although a minimal configuration GSP600 VGAIPAL system
uses all of the lines of the graphics image to generate the PAL
picture, the resulting PAL display is not (and cannot be) as
good as the original VGA display. Despite the fact that all the
lines are used, on the standard non-interlaced VGA display
every line is used for every vertical period of about 20.0 ms,
while it takes twice as long to put out all the lines to the PAL
picture (40 ms). This is accomplished in practice by one of two
ways: 1) interlacing the VGA (slowing it down to PAL rates),
or 2) using odd numbered lines for odd PAL fields and even
numbered lines for even fields, essentially discarding half the
lines that are output from the VGA (see the Application Note
AN602, Theory of Operation for a GSP600 Circuit Operating
the VGA Display at 2 x PAL Frequency). It is probably intuitively obvious that either slowing the VGA down or throwing
away halfthe VGA data will result in the PAL output looking
less pleasing than the standard VGA display. The practically
observed result of this is what is generally known as "flicker,"
and it should be noted that this problem plagues all scan
converters and VGA-to-PAL boards; it is a fundamentallimitation of the PAL standard. It is worst when there is a lot of
detail along the vertical axis of the VGA image. The most
annoying example is a thin, bright white horizontal line made
up of a single line on the VGA display. For an example case,
imagine that line 100 of the VGA display contains the white
line and the rest of the display is black. Then the white line
would appear somewhere around line 50 of field 2 in the PAL
output, but not at all on field 1. The result will be a flashing of
the line with a period of 40.0 ms (reciprocal of the 25 Hz frame
rate). This is very noticeable and quite irritating to the eye.
Knowing that displaying a VGA image on an PAL monitor is
at best a compromise, we would at least like to achieve the best
possible performance from the conversion. Because of this,
most scan converters and VGA-to-PAL boards have a "flicker
filter." It is enlightening to note that most flicker filters can be
turned off, indicating that they are less than desirable in some
situations. In fact they reduce the spatial "bandwidth" in the
vertical direction, or in other words reduce the vertical resolution. A particularly simple and effective flicker reduction
scheme (which can be implemented in software) is to repeat
every other VGA line in both fields of the PAL signal. This
method, however, requires that half the VGA lines never get
to the PAL display; in other words, the vertical resolution is
cut in half.

A single horizontal line in the VGA image has only a 50/50
chance of being displayed in PAL, depending on which line
number it appears on. Obviously, this method leaves a lot to
be desired, since some details in the VGA image can be
completely absent from the PAL signal; most people would
judge it unacceptable.
You can get a feel for how a better typical flicker filter works
by thinking about the example above of a single white horizontal line on scan line 50 of field 2. Imagine "spreading" the line
so that some of it spills into the scan lines adjacent to the
original line. In an interlaced system such as PAL this means
reducing the brightness of line 50 offield 2 (thereby making it
gray), and putting some darker shade of gray into lines 50 and
51 of field 1, which are above and below line 50 of field 2,
respectively, once the complete frame has been scanned. If
done properly, in the right proportions, and viewed from a
sufficient distance, the new wide line looks to be of the same
brightness as the original single white line. This can significantly reduce the flicker, since there is no longer the situation
of black on field 1 and white on field 2 rapidly alternating.
However, as you can imagine, any rapid vertical transitions
would also become smeared or blurred with such a scheme.
The typical complaint is that when trying to display text on an
PAL display, a flicker filter will make the text less readable (if
it remains readable at all). This type of flicker reduction works
best if only the luminance portion of the signal is filtered, since
the mixing of several VGA lines to make one PAL line can
significantly change the saturation and hue of the color displayed, seriously altering the picture when compared with the
VGA display. It is primarily changes in luminance level that
cause flicker, so that leaving the chrominance portion of the
signal unchanged does not seriously degrade the flicker reduction that is achieved, while it does tend to preserve the look of
the image.
To boil all this down, there is a trade-off between flicker
reduction and vertical resolution, and it bears repeating that it
is a practical impossibility to make an PAL image look just as
good as a high resolution VGA image. To try and work around
this trade-off, some sophisticated flicker filters are "adaptive,"
which essentially means that they will dynamically turn themselves on when especially needed to reduce flicker and off
when the loss of vertical resolution is especially detrimental.
Predictably, this approach is rather expensive and takes up a
lot of circuit board space, at least until the time when this
function is incorporated into a monolithic integrated circuit. At
any rate, a flicker filter of the more basic variety is presented
here for use with GSP600 applications.

IAN603RevAl01993I

G·71

E1

II

AN603
Application Circuit
In the accompanying schematic and block diagram an implementation of a simple luminance-only flicker filter which
works with the GSP600 in a VGA-to-PAL system is shown.
The schematic details only the portion of the system specific
to the flicker filter function, since the VGA portion will vary
depending on the VGA chip used. Please refer to the schematic
when reading the following detailed circuit description.
V8B divides the frequency of the VGA_HSYNC signal VHS
by two, producing a 50% duty cycle square wave with a
frequency of 15.625 kHz. This signal essentially becomes the
Write Enable signal at V5 pin 22 and is also sentto the GSP600
pin 60 as the Horizontal Sync signal PAL_RATE_HS. Note
that the addition of a divide by 2 in the overall loop which the
GSP600 controls forces the VGA chip to clock at twice the rate
that it otherwise would, producing a VGA HSync frequency
of 31.25 kHz.

V2 is a line buffer memory which can hold up to 910 pixels
with a width of 8 bits; it has individual write and read clocks
with associated address pointers. Programmable logic device
US provides a write enable and pointer reset signals to the line
memory. Note that the write clock to V2 (pin 17) is the same
rate as the VGA pixel clock; therefore, every VGA pixel will
be written in to the memory when write enable (pin 20) is active
(low). The write enable is only active for every other line,
however, since it is frequency divided by 2 from the VGA
HSync as previously noted. This essentially discards half the
VGA lines each PAL field, by virtue of the fact that they are
not written into memory. The time to write a complete line into
memory is I VGA line time or 32.0 I1s. The read clock for V2
is simply the write clock frequency divided by 2 by V8A. Thus,
to read all the pixels out of the memory will require twice as
long as to write them, or 64.11S. This is the length of a PAL
line. Therefore, over the span of 2 VGA lines, 1 VGA line is
written and 1 PAL line is read, although the writing takes place
at twice the rate.

Data read out from V2 at PAL rate is fed to RAMDAC V9,
which has its control lines paralleled across the main VGA
RAMDAC, except that the active low read enable (pin 6) is
permanently disabled by tying it to +5V. In this way anything
written to the VGA RAMDAC (such as changes to the palette)
will also be written to V9, but any reads will not cause a conflict
with the main VGA RAMDAC. The analog RGB outputs of
V9 are sent to the PAL encader to produce the chrominance
component of the composite video output. V6 provides the
required voltage reference to V9. Also, the RGB outputs from
V9 are combined by resistor matrix in the right proportions to
create a luminance signal which can be summed with the adjacent
lines' luminance signals, thereby spatially lowpass fIltering the
luminance signal in the vertical dimension.
Vp to this point the circuitry described is basically the same as
is required to make the VGA run at 2 x PAL rates (see the
Application Note AN602,Theory of Operation for a GSP600
Circuit Operating the VGA Display at 2 x PAL Frequency).
Note that there are an additional 2 line buffers (U3 and V4), 2
RAMDACs (U1O and VI), and 2 current references (V7 A, Ql,
and Q2). The additional 2 line buffers store the VGA lines
before and after the current line being output via V2 and V9.
The RGB current outputs from the RAMDACs UlO and VI
are connected together, summing the two sets of RGB currents
together. The combined RGB signals from VlO and VI are
then matrixed together in the proper proportions to produce an
adjacent-lines luminance signal. This signal amplitude is independent of the main luminance signal so that the ratio of
adjacent line to main line luminance can be set to any desired
value, primarily by adjusting Rl, which controls the reference
currents into VlO and VI.

G·72

AN603

Figure 1
The two luminance signals are connected together, summing
them at the input to amplifier UII. UII then makes up for the
resistive losses in the RGB matrices and drives the luminance
delay line, whose output is the luminance component of the
encoded composite signal. Most encoders have a luminance
output and input which allows for an external delay line; not using
the output provided while driving the input with an alternate
luminance signal of the right amplitude, delay, and polarity allows
convenient summing with the chrominance signal generated by
the encoder to create the composite video signal.

WE-U2

Programmable logic chip U5 controls the writing ofVGA lines
into the line buffers such that U2 receives every other line, U3
receives every fourth line, and U4 receives every fourth line,
as shown by the timing diagram in Figure 2. Note that only one
line buffer is write enabled at a time and every line is written
to a line buffer. With this scheme U2 always contains the main
VGA line which is going out to the PAL encoder, while U3
and U4 contain the lines adjacent to the main line. The
CUPUM language source code for PLD U 5 is included later in
this note.

~

I

L

WE-U3
WE-U4

I

32.0 uS
1 VGA LINE
64.0 uS
1 PAL LINE

~

1

~
Figure 2

G-73

E1

AN603
All of the line buffers are continuously read enabled, such that
the ROB signal output to the encoder is a combination of the
main line and the 2 adjacent line signals. V7A, Ql, and Q2
make up a dual matched current reference for RAMDACs V I 0
and V 1. The amplitude of the adjacent line video signals
summed in with the main line is adjustable with Rl; the
optimum value could be determined so that Rl could be replaced with a fixed divider to save the cost ofthe trimmer. The
amplitude of the main line video signal is controllable by the
value ofR6 ifitis necessary to adjust the proportion of the main
line signal that gets summed into the final output. The relative
weight of the 2 adjacent line signals in the output is the same
due to the matching of the current references into V 10 and VI;
this should be best for most applications since it is symmetrical
about the main line.

BIOS
The video BIOS for the circuit presented here will have to be
modified from the typical GSP600 VOAIPAL system; therefore, register setups for various video modes are given in
several tables later in this note.

The luminance amplitude is controllable by varying the gain of
VII (set by the value of R22); this should normally be set so
that luminance levels on any given line are somewhat lower
than they would be without filtering. An optional feature shown
in the schematic is the ability to switch off the flicker filtering
with an 110 bit. Switches Q3 and Q4 turn on when the filter is
disabled. In this state Q3 cuts the reference current into V 10
and VI, thereby turning off the adjacent line luminance; while
Q4 boosts the gain of V 11 (by an amount set by R23) to what
it should normally be without flicker reduction.
Since when a large area of high luminance level occurs, the
video output could exceed the maximum allowed voltage, Q5
and Q6 are used as a positive luminance peak clipper. R27 can
be set so that the peak luminance level at the final video output
is 714 mY.

G-74

............. g

,~·

...... .-I-- VGAHS\'NC

881TVIOEODATj ,
FROMVGA

9
til

vGA...VlDIO••7)

ANALOG PROCESSING

RED

RED

GREEN

EN
BlUE

.......

RLT..l1JM

IlGA..IIID(O..7)

• BIT ca.ORNUM8ERTO
COlOlU- COlORJAlUlfl>-

ILi!E:

PAl,.RATC..IIG

G/lN.ADJAC

au,Jd)JAC

BLU..ADJAC

.---

JFFEN

iFFEN

Flicker Filter Circuit for GSP 600

Figure 3 - Flicker Filter Top Level Schema1ic

II

Fl.TEm!D LIJWoWIC£ SIGNAL

TO ENCODER V N'UT

II

AN503

IRAMOAC

to

11j

l

, ,

o ,

"i"O,~'1
~
12

D

if

"
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n
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UPD42101

,

,, ~n~
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RSTR

0

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Figure 4G-76

II

AN503

.

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nnnn

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.

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Flicker Filter Line Buffering/Ramdacs

G-"

."

ADJAC
ADJA

AN603

...
......
II

.

12'

Q'

,.1112

+

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II

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H~
7

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117

I I I • U. YALUES DE'EI.
01 PIOPER TIIIII .. TIOI IMPEDAICE
FOR DILA' LIIE DLI

ell

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THRESHOLD SET

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1.21

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'IV

FI LT L

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4.71

-n

Figure 5 - Flicker Filter Analog Processing
G·7S

AN603
CRTC Registers
VIDEO MODES

INDEX

REGISTER
()()

35

01

02

35

6B

03

04

05

06

07

OD

OE

OF

10

II

12

13

••

6B

35

35

62

6C

35

62

62

62

62

62

62

62

()()

HT

01

HDE

27

27

4F

4F

27

27

4F

4F

27

4F

4F

4F

4F

4F

04

4F

02

SHB

2A

28

57

57

2A

2A

50

54

2A

50

50

50

50

50

50

50

03

EHB

95

96

8B

8B

96

96

85

8B

96

85

85

85

84

84

85

84

04

SHR

2E

2E

5D

5D

2F

2F

58

5D

2F

58

58

58

54

57

58

57

05

EHR

AO

AO

8C

8C

80

80

9B

83

80

9B

9B

9B

82

82

9B

82

06

VT

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

OB

07

OVERFLOW

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

3E

08

PRS

()()

()()

()()

()()

00

00

()()

00

()()

()()

()()

00

()()

00

()()

00

09

MSL

4F

4F

4F

4F

CI

CI

CI

4F

CO

CO

40

40

40

40

CO

40

INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

••

OA

CS

OD

OD

OD

OD

()()

00

()()

OD

()()

()()

()()

00

00

()()

00

00

OB

CE

OE

OE

OE

OE

00

00

()()

OE

()()

()()

()()

00

00

()()

00

00

OC

SAH

00

()()

00

00

00

00

00

()()

()()

()()

()()

00

00

()()

00

00

OD

SAL

00

00

()()

00

()()

00

()()

()()

()()

()()

()()

()()

()()

()()

00

00

OE

CLH

00

()()

00

00

00

00

00

00

00

00

00

()()

()()

00

()()

()()

OF

CLL

()()

00

()()

()()

()()

00

00

()()

00

00

00

00

00

00

()()

()()

INDEX

REGISTER
00

01

02

03

04

05

06

07

OD

OE

OF

10

11

12

13

••

BE

BE

BE

BE

C5

C5

C5

BE

C5

C5

A7

A7

F4

F4

C5

EF

VIDEO MODES

VIDEO MODES

10

VRS

11

VRE

22

22

22

22

88

88

88

82

88

88

8B

8B

87

87

88

87

12

VDE

8F

8F

8F

8F

8F

8F

8F

8F

8F

8F

5D

5D

DF

DF

8F

DF
50

l3

OFFSET

14

14

28

28

14

14

28

28

14

28

28

28

28

28

28

14

UNDERLINE

IF

IF

IF

IF

()()

()()

00

IF

00

()()

OF

OF

()()

00

40

60

15

SVB

B8

B8

B8

B8

C2

C2

C2

B8

C2

C2

9F

9F

EO

EO

C2

EO

16

EVB

E3

E3

E3

E3

05

05

05

E3

05

05

CA

CA

OC

OC

05

oc

17

MC

A3

A3

A3

A3

A2

A2

C2

A3

E3

E3

E3

E3

E3

E3

A3

AB

18

LC

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

•

INTERLACE

* = Interlace Bit must be turned off for all modes

General Register
VIDEO MODES

INDEX

REGISTER

()()

MlSCOUT

()() I 01 I 02 I 03 I 04 I 05 I 06 I 07 I OD I OE I OF I 10 I 11 I 12 I 13 I ••
#I#I#I#I#I#I#I@I#I#I@I#I#I#I#I#

#
23 = GenLock (GL)
27 = OVerlay (OV)
2B = Video Only (VO)
2F = Graphics Only (GO)

@

22 = GenLock (GL)
26 OVerlay (OV)
2A = Video Only (VO)
2E = Graphics Only (GO)

=

G·79

II

AN603
Sequence Registers
VIDEO MODES
INDEX

REGISTER

00

CLKMOD:8

00

I

01

I

02

J

03

L04 J 05 1 06

I

07

I OD I

0:8

J OF J

10

I 11 J

12

•• = 640 x 480 x 256 colors

Source Code for PLD US (GAL20V8) in CUPLTM Language
Name
Partno
Date
Revision
Designer
Company
Assembly
Location

ff;
ff01 ;
1/20/93;
01;
Todd K. Moyer;
Integrated Circuit Systems;
Flicker Filter;
U5;

/ ••••••••• ** •• ** ••••••••••••••••••••••••••••••••••••••••••••• ** ••••••••• ,
1*
*1
1* VGA @ 2xPAL rate controller with basic line flicker filtering
*1
1*
*1
~

~

/*** ••• *** •••••• **.** ••••••••• **.**.** ••• ** ••••• *** •••••• * ••• ** •••• * ••• */

1*

*1
*1
1*
*1
/********* •• ***********.******* •• ****** •••••••••• **** ••• ****** ••• *.*.***/
/* Allowable Target Device Types: g20v8

1** Inputs **1
Pin
Pin
Pin
Pin
Pin

1
2
12
13
24

L 13 I ..

~1~lmJmL~I~lmlooJ~lmJmlmlmlmlmlm

clock
h_sync]AL;
GND
tOE
VCC

~

VGA PCLK signal

1*

*1
*1

1* * Outputs * * 1
Pin [15 .. 181
Pin 19

[HSN_SO .. 31;
lline_start;

1* used by state machine

*1

~

*/

Pin 20
Pin 21
Pin 22

!write_enable_B;
!write enable A;
Iwrite:=enable;

1*
1*

pointer reset line mem, act 10

*1
*1
*1

~

1* * Declarations and Intermediate Variable Definitions * * 1
Field

1** Logic Equations * * 1

G·80

II

AN603

/** State machine definition **/
Sequence State_HSync
{

present 0
if h_sync_PAL next 1
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_PAL next 0
out write_enable;
present 1
if h_sync_PAL next 2
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_sync_PAL next 0;
present 2
if h_sync_PAL next 3
out line_start out line_startAB
out write_enable out write_enable_A;
if !h_synch_PAL next 0;
present 3
if !h_sync_PAL next 4;
/* out write_enable; */
if h_sync_PAL next 3
out write_enable_A;
present 4
if !h_sync_PAL next A;
if h_sync_PAL next 3;
present A
if !h_sync_PAL next 5;
if h_sync_PAL next 3;
present 5
if h_sync_PAL next 6
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5
out write_enable;
present 6
if h_sync_PAL next 7
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5;
present 7
if h_sync_PAL next 8
out line_start out line_startAB
out write_enable out write_enable_B;
if !h_sync_PAL next 5;
present 8
if !h_sync_PAL next 9;
/* out write_enable; */
if h_sync_PAL next 8
out write_enable_B;

G·S1

II

AN603
present 9

if !h_sync_PAL next B;
if h_sync_PAL next 8;
present B

if !h_sync_PAL next 0;
if h_sync_PAL next 8;
present C
next 0;
present D
next 0;
present E
next 0;
present F
next 0;

Bill of Materials
Item

Qty

1

15

Reference
Cl, C2, C3, C5, C6, C7,
C8, C9, CIO, Cll, C12,
C13, C14, CIS, C16

Part

Item

Qty

.1J.LF

15

2

R15, R18

8.2K

16

2

R16, R19

17

2

R17, R20

4.3K
22K

18

1

19

2

R22
R25,R26

I.2K

20

1

R29

21

3

22

3

VI, U9, VIO
U2, U3, U4

23

1

US

GAL20V8

24

1

U6

LM317

25

1

U7

26

1

U8

TL072
74HC74

27

1

Ull

AD8ll

2

1

C4

3

1

DLl

4

2
2

Ql,m

2N3904

03,04

VN2222

2

2N3906

5
6

Reference

Part

IOJ,lF
400ns

7

5

05.06
Rl, R14, R21, R23, R24

8

1

R2

120

9

1

R3

100

10

2

R4 R5

121
150

lK

11

1

12

3

R6
R7,R8, R9

13

3

RIO, Rll, R12

33

14

3

R13. R27. R28

200

47

G-82

680
4.7K
SC11483CV
UPD42101

II

ICS2001

Integrated
Circuit
Systems, Inc.

Sound Output Circuit
General Description

Features

The ICS2001 is a CMOS integrated circuit containing an 8-bit
digital to analog converter fed by a 16-byte FIFO memory
array. This device is intended to form the nucleus of a low-cost
audio-output subsystem for personal computers, workstations,
games, and talking books. The ICS2001 is the core of the
Disney Sound Source. TM

•
•

•
•

•
•

8-bit DIA converter
16-byte FIFO
SV and 9V operation
TIL-level inputs with hysteresis
RC clock oscillator
Software drivers for DOS and Windows

Block Diagram

SELECT

~---0-----+-------1

SHiff IN

r-r---I-----i RESET
'---J-----j

DATA READY

Sound Source ita trldemark of Walt Disney Computer Software Incorporated.

IICS2001RovB083084 I

G-83

V REF
GEN

DAC
OUT

G-84

•

ICS2002

Integrated
Circuit
Systems, Inc.

Wavedec™ Digital Audio Codec
Description

Features

The ICS2002 is a mixed-signal integrated circuit providing a
low-cost recording and playback solution for multimedia audio
applications. These applications include document annotation,
voice mail, interactive games, multimedia sound record/playback, and Windows™ sound production. The ICS2002 supports the record and playback of l6-bit audio data, and provides
a Sl16-bit parallel interface to the industry standard PC bus.

•
•

Digital audio Sl16-bit record/playback
Fully programmable sample rates including industry
standards:
- 44.1 kHz
22.050 kHz
11.025 kHz
S.OO kHz
5.513 kHz

•

DAC output oversampled to simplify external filtering.

•

Four data formats:
- 16 bit linear
- S bit linear
- 8 bit u-Iaw
- 8 bit a-law

•
•

16 step analog output level control, -1.5dB/step
8-bit log scale digital volume control

•
•

Oversampling ADC with input filter.
Programmable IIR filters for mput anti -aliasing and output
reconstruction.

•
•

ISA bus interface
8/16-bit DMA and I/O transfer modes

•
•
•

Input/output FIFO buffer
Power-down mode
44-pin PLCC package

E1

Block Diagram
Audio
In

G
A
I
N

DSP

ADC

(Filters,
11 Law,
A Law)

DAC
Out

DAC

But In

ADCIN.-----'
XTU
XTLO

But

Select

Out

PWRDN

ISA INTERFACE

gO Iv!::
0.

C§
Wavedec

/ICS2002RevF093094

G-85

IS

a trademark of Integrated CirCUit Systems, Inc

ICS2002
Pin Descriptions
PIN
SD15 - SDO
SAl - SAO
CS
lOW

~

SBHE
IOCS16
DRQP
DRQR
DACKP
DACKR
TC
IRQ
RESET
XTLI
XTLO
PWRDN
AUDIOIN
ADCIN
DACOUT
BUFIN
BUFOUT
VDD
VDDA
VDDP
VSS
VSSA
VSSP

TYPE
I/O
I
1
I
I
I
OC

0
0
I
I
I
0
I
I
0
I
AI
AO
AO
AI
AO
P
P
P
P
P
P

DESCRIPTION
Data bus
Address
Chip select (active low)
Write strobe (active low)
Read strobe (active low)
-System High Byte Enable (active low)
Indicates that the access register can support 16 bit transfer.
DMA Request (play channel)
DMA Request (record channel)
DMA Acknowledge (play channel)
DMA Acknowledge (record channel)
DMA terminal count
Interrupt request (active high. open drain)
Reset (active high)
Crystal oscillator
Crystal oscillator
Power-down (active low)
Audio buffer input
Audio buffer output/input to ADC
DAC audio output
Uncommitted audio buffer input
Uncommitted audio buffer output
Digital +5V supply_
Analog +5V supply
Digital +5V supply
Digital GND
Analog GND
Digital GND

G·86

--

--

II

ICS2002
~
~ >~ C15~81~~~~
~I <>6<
>

Package Pinout

lOW
lOR
IOCS16
IRQ
DRQR
DRQP
SOlS
S0I4
SOB
S012
SOli

7
8
9
10
11

ICS2002V

12
13

14
15
16
17

35
34
33
32
31
30
29

OACOUT
BUFIN
BUFOUT
RESET
VSS
S07
SD6
SOS
S04
SD3
S02

18 19 20 21 22 23 24 25 26 27 28

'OOocc"'»o
" '" '" "'I < '" '" < QI '"00'"
o\Ooo~5@o-~

0_

44-Pin PLCC
K-10

~
< ~I C§ § <
~ ~ ri5~81~~~~

»

loW
lOR
IOCS16
IRQ
DRQR
DRQP
S0l5
SD14
SOl 3
S0I2

10

SOU

11

ICS2002Y

33
32
31
30
29
28

25

12 13 14 IS 16 17 18 19 20 21 22

'OOOCC",»»o",Oo
" '" '" "'I < '" '" < QI '" '"

o..ooo~~o-~

44-PinTQFP
K-12
G-87

0_

DACOUT
BUFIN
BUFOUT
RESET
VSS
SD7
SD6
S05
S04
S03
SD2

ICS2002
Absolute Maximum Ratings
Supply Voltage ...................... -O.5V to 7.0V
Logic Inputs. . . . . . . . . . . . . . . . . .. -O.SV to Voo + O.SV
Ambient Operating Temperature .......... ODC to 70 DC
Storage Temperature ................. -6S DC to IS0 DC
Stresses above tbose listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of tbe device at these or any otber conditions above those indicated in the operational sections of
tbe specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

Electrical Characteristics
Voo =S.OV ± 10%; GND =OV; TA =ODC to +70 DC

DC/STATIC
PARAMETER
Digital Inputs
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Digital Outputs
Output Low Voltage (IOL =4.0mA)
Output High Voltage (IOH =O.4mA)
Tristate Current
Output Capacitance
Bi -directional Capacitance
Analog Inputs
Audio Input Voltage
Audio Input Impedance
Buffer Input Impedance
Audio Outputs
Audio Output Voltage
DACOUT, BUFOUT Output Impedance
Digital Supply Current
Analog Supply Current
Power-Down Mode
Play Only Mode
Record Mode

SYMBOL

MIN

VIL
VIH
ILl
CIN

-0.3
2.0

VOL
VOH
Ioz

TYP

MAX

UNITS

0.8
Voo+0.3
1
7

V
V

V
V

10
10
10

~A

0.7

0.7
lk
1
3S
1
IS
30

G-88

pF
pF
Vrms
ohm
ohm

SOOk
SOOk

IcC!

pF

0.4
2.4

IOD2

~A

Vrms
ohm
rnA
rnA
rnA
rnA
rnA

ICS2002
Electrical Characteristics
VOO = 5.0V ± 10%; GND =OV; TA = O°C to +70°C

ACIDYNAMIC
PARAMETER
Address setup to command
Address hold from command
Command cycle time
Address valid to /laCS 16 delay
laCS 16 hold from address invalid
Data valid to /lOW
/lOR active to valid data
Data hold after /lOR
Data hold after /lOW
IDACK setup to /lOR
IDACK setup to /lOW
IDACK hold from command
ICS setup to command
ICS hold from command
TC setup to command inactive
I

TC hold from command

SYMBOL

MIN

tAS

10

TYP

MAX

UNITS
ns

tAR
tCCY

10
100

ns
ns

tAID
tIH

0

50

tos
tOAC

50

tORR
tOHW
tOAR

0
10
30

tOAW

50
50

60

tOAR
tcs
tcR
tTS
tTR

G-89

ns
ns
ns
ns
ns
ns
ns
ns

10

ns
ns

10
25

ns
ns

0

ns

II

ICS2002

.
z

z
c

I

...
-'

l~
.--x

...c
::

-'

<

>

..
~

.
C

D

I

I

.."
c

I

I

en

<0

(I)

C

C,.I

.....

z:

.....

<

(I)

C,.I

IIJ

IIJ

0

::c

::Ii:
::Ii:
0

r.:

IX!

C,.I

....

C

<

.....

(I)

E

.....

A
0

01

A
0

In

..
CO
CO

is
01

C

"e

v
<

r.:

:z
A
0

.....

In

0

c

v

.....

IIJ

I-

(I)

.....
V

(I)

(I)

1=

G·90

II

ICS2002

T

-'--

LL
..J

L_ --- ---- ~

-r

0
..J

~

a

a::
0

""u

'"
.....
0

Ul

a::

3

0

0

.....

.....

VI

U

.....

0

'"

UJ

a::

..

'"

CO

0

E
CO

en

is
C)

A

v

c

VI

c:::

E
t=

G-91

'"

>

UJ
I-

a::
3

A

'"
.....
0

v
0
VI

U

....

II

ICS2002
Digital Audio Playback
To play digital audio files, the chip is programmed for the
desired sample rate, data type, DMA channel width, and output
volume.
For DMA mode playback, DRQ generation is programmable
for servicing the FIFO at several levels. This allows optimal
performance with a variety of hosts. When TC is received, the
chip will optionally generate an interrupt to the host to indicate
the need to service the DMA controller.
For I/O Mode playback, data is written to the FIFO until it is
full. This is determined by polling the "DIR" bit of the status
register. Once the FIFO is full, an interrupt will be generated
optionally at one of several selectable points: 114, 112, or 3/4
full. The host can then burst a predetermined amount of data to
the FIFO and wait for the next interrupt.
Digital Audio Recording:
Audio recording operates in a DMA or I/O mode similarly to
audio playback with the audio input programmable as a line or
microphone level input. Simultaneous record and playback is
supported and permits the recorded file to be synchronized to
an existing file. The new and existing file can then be mixed
digitally for high quality results.

Power Management:
The PWRDN input can be programmed to act as an immediate
hardware power control, or as an interrupt source for a software
driven power management routine. The software driven option
allows the driver to cleanly shut down to chip, thus preventing
unwanted noise. When active, the power-down function disables all analog components including the oscillator, and
causes the chip to enter a low power mode.
Miscellaneous Functions:
The chip has a full complement of status and control functions.
All significant functions are capable of generating interrupts
and/or being polled.

The DMA can be run in single or demand mode (for bursts of
data in programmed sizes).
The FIFO has programmable interrupt and DMA request capacities, and also indicates when overflow or underflow conditions occur.
The processor interface is designed for simple connection to
the ISA bus. For best noise performance, isolating the data lines
from the ISA bus is recommended. In general, feed through of
digital noise is reduced by minimizing the load which the
digital outputs are driving.

Data Processing:
To simplify the external circuitry associated with the analog
input and output signals of the chip, input and output sample
rates are oversampled. This allows simple RC filters to be used.

For playback, the output data is oversampled, interpolated,
filtered and scaled. Since the DSP is fully programmable,
various sample rates and filter shapes can be implemented. The
processed data is then output to the DAC. The DAC output
passes through an analog volume control (4 bits, 1.5dB steps)
before being passed to the analog filter stage.
For recording, the input data is first filtered, removing most of
the frequency content above the Nyquist frequency. The resulting data stream is then undersampled to the desired sample rate
and fed into the FIFO for transfer to the host.

G-92

II

ICS2002

Direct Register Descriptions
The base address is determined externally by an address decoder which selects the chip via the CS input.

Note that this register can only be read in STAND ALONE
mode. Hence, indirect access to this register has been provided
at RA=83h for use in COMPANION mode.
Register Address (RA) (Base + 1)
76543210

IIIIIIIII~

Status (Base + 0 read)
76543210

I IIIIIII I

This register is the indirect pointer to direct data transfers to
and from the data registers. It is a read/write register. Note that
this register can only be read if the chip is in STAND ALONE
mode.

II ~~L::
'-= g:::;~~{~r~~RQ

reserved
Power-Down Mode IRQ
FIFO Overflow/Underflow IRQ
Sample Rate IRQ
FIFO Ready
IRQ (same as pin)

Data Low Byte/Word (DLW)
76543210

I IIIIIII I

IRQ Reset (Base + 0 write)
Data High Byte (DH) (Base + 3)

76543210

I IIIIIII I

'-=
~~~

76543210

L::g:::~~~YI~g

I IIIIIII I

reserved
Clear PDM IRQ
Clear FOU IRQ
ClearSR IRQ
reserved
reserved

These two addresses are used to accomplish all internal register
reading and writing. Most internal registers are 8-bit or less.
These are accessed by first writing the appropriate value to the
DW, then writing (reading) the data byte to (from) DLW.

This register provides the driver software easy access to the
interrupt source when read. Note that bit 7 indicates the state
of the IRQ pin, and hence will be zero when the MIE bit is zero
(see "Interrupt Enable" register).

I/O Mode FIFO data (RA=OBh), Algorithm RAM, and Coefficient RAM are always treated as 16-bit entities, and can be
transferred in two ways:

A write to the register is performed to clear interrupts. Writing
a one to a given bit will cause the associated interrupt to be
cleared. To release the clear interrupt bit and allow further
interrupts to occur, a zero must be written back to the bit of
interest (some bits have alternate methods of clearing described
later). This feature ensures that if the interrupt condition still
exists, an edge will be generated on the IRQ pin, thus ensuring
recognition on platforms that are edge sensitive. This also
allows for a return from interrupt instruction to be executed on
the platform while the IRQ line is inactive.
Bit 6 is a special case. There IS no IRQ associated with this bit.
It is located here for use in Sound Source Emulation Mode, and
represents the BUSY status of a Sound Source. When the
STATUS is read and tested with 40h, a zero result indicates that
the play FIFO is full.

G-93

- a single operation to/from DLW with SBHE = 0
- two successive operations, low byte to/from DLW
with SBHE = 1, then high byte to/from DH.

G

II

ICS2002
Indirect Register Map
Indirect
Address
4E

Companion Select Register (write only)

80
81
82
83

Chip Control
Interrupt Enables
reserved
Interrupt status

84
85
86
_87

Indirect
Address

Register

Sample Rate Low 8 bits
Sample Rate High 4 bits
Sample Rate Control/Status
reserved

88
89
8A
8B

Play DMA Control
Play DMA Burst Count
Play DMA Mode
DMA 10 Mode Data Port

8C
8D
8E
8F

FIFO Enable/Status
FIFO IRQ Mode
reserved
reserved

90
91
92
93

Power Enable/Status
Power Mode
reserved
reserved

94
95
96
97

DSP Control/Status
DSP RAM Address Latch
Code RAM Data Port (8/l6-bit)
Data RAM Data Port (8/l6-bit)

98
99
9A
9B

Record DMA Control
Record DMA Burst Count
Record DMA Mode
reserved

G·94

Register

9C
9D
9E
9F

Record FIFO Enable/Status
Record FIFO IRQ Mode
reserved
reserved

AD
Al
A2
A3

Digital Master Volume
DAC Deglitcher Control
reserved
reserved

A4
AS
A6
A7

ADC Control
Analog VolumelMute
ADC Timing Control
reserved

II

ICS2002

Indirect Register Definitions
All write able bits/registers are also readable. In addition, there
are some read only bits/registers, which are noted where appropriate.
Reserved bits should be written to zero, and read back zeros.
Reserved registers should not be written or read.

Bit I - Chip STAND ALONE Mode
This bit sets the chip to operate in STAND ALONE
mode. In STAND ALONE mode, the STATUS and RA
registers are accessible at BASE+O and BASE+ I. This
mode should be used to speed register access when the
ICS2002 is being used by itself, without other ICS
chips sharing resources (such as address decodes, interrupts, DMA channels, bus buffers, etc.).
When bit I is zero, the ICS2002 will operate in COMPANION mode. In this mode, the STATUS register is
mapped only to indirect address 83h. This is done to
avoid conflict with other ICS chips that will provide
STATUS and RA read back at the first two base addresses.

Except where noted, registers should be accessed as 8 bit
registers via address BASE+2.

General Purpose Registers
IR4E Register Access Mode Select
This register must be written to Olh for any other
indirect (or direct) accesses to occur, except for RA
writes, which always occur based on chip select. This
indirect address allows multiple companion chips to
share resources in a system (such as bus buffers, address
decodes, interrupts, and DMA channels).
This register is cleared only by hardware reset, and in
unaffected by MCR (see below).

IR80 Chip Control
Bits 7:3 - reserved
Bit 2 - Sound Source Emulation Mode (SSMODE)
This bit sets the chip to operate in Sound Source Emulation mode. In Sound Source Emulation Mode, the two
address pins (SAl, SAO) are mapped to match the PC
parallel port as used by the Sound Source as follows:
Chip Address
0
1

2
3

Sound Source
Data
Status
Control
unused

In addition, STAND ALONE mode configures the
DRQP, DRQR, and IRQ pins to operate as outputs, with
both one and zero levels being actively driven. When
in COMPANION mode, these pins have a strong source
for the high state and a weak sink for the low state to
allow wire-and connections to other ICS chips.
This bit is reset by hardware reset only, not by MCR.
Bit 0 - Master Chip Reset (MCR)
o - Hold chip in reset
1 - Remove reset
This bit is cleared to zero by a hardware reset. Thus,
any functions reset by MCR are also reset by the
RESET pin.

IC2002
DH
Status
DL
RA

To use this mode, the chip must be configured before
the Sound Source compatible application is run (VO
Mode DMA, DSP loaded and running, SR running,
etc.). Then, the IC2002 is put in SSMODE and RA
(now at address 3) is written to 8Bh. In the PC, the BIOS
pointer to the parallel port is changed to the base
address of the IC2002 chip, and the application can
then be started.
This bit is reset by MCR. Hence, it must be set after
MCR is set, on a second write to this register.

G-95

II

ICS2002
IR81 Interrupt Enables
Bit 7 - Master Interrupt Enable (MIE)
In the zero state, this bit prevents the IRQ pin from
going active (high) regardless of the state of any of the
individual interrupt sources. It is cleared to zero by
MCR. A zero in this bit does not prevent an individual
interrupt source from being active in the STATUS register. This allows interrupts to be masked while allowing their status to be polled.
Bit 6 - reserved

Sample Rate Generator Registers
IR84 Sample Rate Low 8 bits (SRL)
Bits 7:0 - Sample Rate Bits 7:0
IR85 Sample Rate High 4 bits (SRH)
Bits 3:0 - Sample Rate Bits 11:8
Together, these two registers define the record and
playback sample rate. Based on the crystal frequency
FXtal, and a 12 bit value SR (the concatenation of the
two registers), the sample rate will be:

Bit 5 - Sample Rate Interrupt Enable (SRIE)
Sample Rate = FXtal

Bit 4 - FIFO OverflowlUnderflow Interrupt
Enable (FOUlE)

* SR / 524288

These registers are not initialized by any of the reset
mechanisms. Note that the Sample Rate Counter should
always be stopped via SRCS bit 0 when these two
registers are changed.

Bit 3 - Power-down Mode Change Interrupt
Enable (PMCIE)
Bit 2 - reserved
Bit 1 - Record FIFO Interrupt Enable (RFIE)
Bit 0 - Play FIFO Interrupt Enable (PFIE)
Each of these bits individually enables, one, or disables,
zero, their respective interrupt sources from being active in the STATUS register. In addition, there will be
no IRQ generated if MIE is one when an individual
enable bit is zero. The state of this bit does not affect
the source of these interrupts in any way, and they may
be polled for activity in the appropriate register for each
interrupt type. These bits are all cleared to zero by
MCR.

IR83 Status
This register is the same as the direct access status register,
except that it can be read in COMPANION mode.

IR86 Sample Rate Control/Status (SRCS)
Bits 7:2 - reserved
Bit 1 - Sample Rate Interrupt (SRIRQ) - Read Only
This is set by the hardware whenever the sample rate
counter overflows, indicating that a new sample is
being input or generated. This bit is cleared by any of
the following actions:
- Master Chip Reset
- Sample Rate Run = 0 (SRR bit 0)
- a write to STATUS with bit 5 = 1
- any write to SRCS
Bit 0 - Sample Rate Run (SRR)
This bit resets the Sample Rate Counter, the SRIRQ bit,
and shuts down the sampling and playback pro-cesses
when written to a zero. When written to a one, the
sample rate generator runs at the programmed rate.
SRR is internally synchronized to the master clock to
provide clean starts and stops of the counter. MCR
clears this bit.

G-96

II

ICS2002

Play DMA Control and Status Registers
IRSS Play DMA Control (DMACTL)
Bits 7 - reserved
Bit 6 - TC Reset Mask
When set to I, this bit masks the 'DMA Run' bit reset
upon receipt ofTC, terminal count, signal from the ISA
bus, When reset to 0, the 'DMA Run' bit will be reset
upon receipt of TC.
Bits 5: I - reserved
Bit 0 - DMA Run
This bit enables the DMA hardware to begin transferring data when set to one. It is cleared by either MCR
or receipt of a TC when 'TC Reset Mask' is a zero (see
the DMAMODE register for details).
IRS9 Play DMA Burst Count (DMABC)
Bits 7:6 - reserved
Bits 5:0 - DMA Burst Count
This value determines the number of DMA transfers
that take place for each DMArequest issued to the host.
The actual number of transfers will be DMABC+1.
Thus, for single transfer mode, program this register to
zero. The burst counter is automatically preset to the
burst count whenever the DACKP input is high. Thus,
there is no need to reprogram the count value after TC,
since the next transfer will use the full programmed
count value. This register has no affect on I/O Mode
data transfers, since its only influence is over the DRQP
output. This register is not initialized by any means
other than a direct write, and hence must be written to
before DMA is enabled.

Bit 4 - va Mode Transfer (IOXFER)
When this bit is a one, the DMA hardware (DRQP and
TCIRQ) is disabled. Data transfers take place via IR8Bh,
and are required to be treated as 16-bit transfers. Thus, data
should be written to DLW (with SBHE =low, 16-bit data)
or to DLW (with SBHE = high, 8-bit data low byte)
followed by DH (8-bit data, high byte). It is also the
programmers responsibility to ensure that DMAMODE
bit 2 (DMAI6) is set to a one for all va mode transfers.
Bit 3 - Unsigned Data (USIGN)
When set to a one, this bit expects to receive (and will
generate) unsigned data. The native data format is
Signed Binary Twos Complement. This bit will invert
the most significant bit of each data byte (or word,
depending on the state of DATATYPE). Note that this
bit should be zero when the DATATYPE indicates
u-Iaw or A-law data formats.
Bit 2 - 16 Bit Data (DMAI6)
When set to a one, this bit causes the hardware to expect
data to be sent in 16-bit words. When low, the hardware
expects 8-bit bytes. This bit must be set to one when
performing va mode transfers, as all I/O transfers are
treated as 16 bit values.
Bit 1:0 - Data Type (DATATYPE)
These bits direct the hardware how to interpret the
outgoing data. This is independent of the DMA or I/O
data width. It effects how data is signed and how data
is packed to and unpacked from the Play FIFO. The
DATATYPE field selects the format of data for playback.
Value
00
01
10

IRSA Play DMA Mode (DMAMODE)
All bits in this register are cleared by MCR.

II

Data Type
8-bit linear
16-bit linear
8-bit f..l256 Law
8-bitA-Law

Bits 7:6 - reserved
Bit 5 - Terminal Count Interrupt (TCIRQ) - (read only)
This bit indicates that a Terminal Count has been received on the last DMA operation. If the PFIE and
PLAYIRQ bits have been programmed to a one, an
interrupt will be generated at the end of the last DMA
operation. This bit is cleared by MCR or a write to
STATUS with bit 0 = one. The reset state is then
removed by either writing the STATUS bit 0 to zero.

IRSB DMA 1/0 Mode Data Port (DMADATA) (S/16-bit)
This register address is used to trap I/O mode data to
and from the FIFOs. It is only used in I/O mode. See
the description of the IOXFER bits for more details.

G-97

When DMA16 is one, this register MUST be accessed
as a sixteen bit value. Note that this can be done from
either an eight or sixteen bit ISA slot, since the chip used
SBHE to determine the proper byte swapping.

E1

II

ICS2002
FIFO Control/Status Registers
IRSC FIFO Enable/Status (FES)
Bit 0 - FIFO Enable (FE)
This bit holds the FIFO in a reset state when low, and
enables the FIFO to operate when high. This bit is reset
by MCR. This bit, when low, also resets all FIFO related
conditions (see the following bits) and prevents DMA
start requests from being issued. It does not reset the
FIFO IRQ Mode register.
Bit I - FIFO Overllow (read only)
This bit is set when a FIFO shift in command is generated (by either DMA, I/O, or the DSP) with the FIFO
full, and indicates an error condition. This bit will cause
the FOUIRQ bit to go active, generating an IRQ if
enabled. This bit is reset by writing to STATUS with bit
4 = I, and re-enabled by writing to STATUS with bit 4
= O. FE low also resets this bit.
Bit 2 - FIFO Underllow (read only)
This bit is set when a FIFO shift out command is
generated (by either DMA, I/O, or the DSP) with the
FIFO empty, and indicates an error condition. This bit
will cause the FOUIRQ bit to go active, generating an
IRQ if enabled. This bit is reset by writing to STATUS
with bit 4 = I, and re-enabled by writing to STATUS
with bit 4 = O. FE low also resets this bit.

IRSD FIFO IRQ Mode
This register must never be written to when the FIFO is enabled.
Invalid interrupts and DMA requests could be generated as a
result.
Bits 7:4 - reserved
Bit 3 - FIFO IRQ Enable (FIE)
This bit enables the various FIFO capacity thresholds
to generate interrupts (as PLAYIRQ) when one. When
zero, this bit prevents FIFO capacity IRQ generation
when operating in DMA mode, which only needs
TCIRQ.
Bits 2:0 - FIFO Ready IRQ Mode Selection
This field defines FIFO utilization for both DMA and
I/O mode data transfers. In I/O mode, it is used to
generate interrupts (FRDYIRQ) when the FIFO capacity reaches a predefined point. For DMA transfers, it
signals the DMA logic to request a transfer at those
same predefined points. By programming the DMA
Burst Count appropriately, the FIFO may be easily kept
near the desired capacity.
The following table describes the selections available:

Bit 3 - FIFO 25% Full (read only)
This bit goes high after 4 words (or 8 bytes) have been
loaded into the FIFO, and low again when 13 words (or
26 bytes) may be loaded into the FIFO. There is no
interrupt associated with this bit directly.
Bit 4 - FIFO 50% Full (read only)
This bit goes high after 8 words (or 16 bytes) have been
loaded into the FIFO, and low again when 9 words (or
18 bytes) may be loaded into the FIFO. There is no
interrupt associated with this bit directly.
Bit 5 - FIFO 75% Full (read only)
This bit goes high after 12 words (or 24 bytes) have
been loaded into the FIFO, and low again when 5 words
(or 10 bytes) may be loaded into the FIFO. There is no
interrupt associated with this bit directly.
Bit 6 - FIFO DIR (read only)
This bit goes high when a single word (or two bytes)
may be written to the FIFO. There is no interrupt
associated with this bit directly. Note that this bit resets
to a one because when the FIFO is reset it is forced to
be empty, and hence is ready to accept data.

I

Bits
2:0

IRQIDRQ
Source

000
001

DIR
EMPTY 75%

010
011
100
101
110
III

EMPTY 50%
EMPTY 25%
DOR
FULL 25%
FULL 50%
FULL 75%

Notes
Ready to take I word from HOST
Ready to take 13 words from
HOST
Ready to take 9 words from HOST
Ready to take 5 words from HOST
Ready to provide I word to DSP
Ready to provide 4 words to DSP
Ready to provide 8 words to DSP
Ready to provide 12 words to DSP

Note that for byte transfers (DMAI6=0), the numbers listed
above should be doubled.
This must be programmed before the FIFO is enabled. It may
be changed while the FIFO is enabled, if necessary. This
register is cleared by MCR, but not by FE low.

Bit 7 - FIFO DOR (read only)
This bit goes high when a single word (or two bytes)
may be read from the FIFO. There is no interrupt
associated with this bit directly.

G-98

II

ICS2002

IR8E reserved
IR8F Play FIFO Output Data Read Back (8116 bit)
This register is provided for test use only, although it may find
system level use as a diagnostic tool.

Bit I - RISEIRQ (read only)
This bit is set when the PWRDN pin makes a transition
from low to high. IfPWRMODE bit I (RISEIE) is one,
this will cause PWRIRQ to go high as well. This bit is
reset by one of the following:
-MCR
- any write to PEST
- a write to STATUS with bit 3 set to one. This will
hold the bit reset until released by a write to STATUS
with bit 3 cleared to zero.

Power Control and Status
IR90 Power Enable/Status (PEST)
Bit 7 - PWRIRQ (read only)
This bit is a one when either edge has occurred on the
PWRDN pin, and the edge enable in the Power Mode
register is set. If bit 3 of the MIE is one, this will also
generate an external interrupt. In any case, this bit is
also visible as STATUS register bit 3. PWRIRQ is reset
by disabling both edge enable bits or resetting the edge
interrupts (see below).
Bits 6:5 - reserved
Bit 4 - ADCPWR Disable
This bit controls the power state of the ADC analog
circuitry. When 0, ADC analog power is controlled by
the SOFTPWR bit the same as the DAC analog power
is. When this bit is set to a 1, the ADC analog power is
turned off independent of the state of SOFfPWR.
This feature is included for advanced power management routines, as chip power dissipation can be reduced
by almost half by turning ADC power off when not in
use. Note, however, that several milliseconds of settling
time is required after power is turned on before the ADC
functions properly.
Bit 3 - PWRDN Pin Value (read only)
This bit indicates the state of the PWRDN pin.
Bit 2 - FALLIRQ (read only)
This bit is set when the PWRDN pin makes a transition
from high to low. IfPWRMODE bit 2 (FALLIE) is one,
this will cause PWRIRQ to go high as well. This bit is
reset by one of the following:
-MCR
- any write to PEST
- a write to STATUS with bit 3 set to one. This will hold
the bit reset until released by a write to STATUS with
bit 3 cleared to zero.
Note that FALLIE does not mask this bit, allowing
polling to be performed.

Note that RISEIE does not mask this bit, allowing
polling to be performed.
Bit 0 - Soft Power (SOFfPWR)
The function of this bit depends on the status of the
"SWMODE" bit (bit 0 of PWRMODE). When
SWMODE is zero, writes to this bit have no affect.
Reads will return the state of the PWRDN* pin, which
is also the state of the on chip PWRON control signal.
When SWMODE is a one, a write of one to this bit turns
on power to the chip analog circuitry, while a zero clears
this bit and puts the chip in a low power mode. Reads
will return the last value written.

IR91 Power Mode (PWRMODE)
All bits in this register are cleared by MCR.
Bits 7:3 - reserved
Bit 2 - Fall IRQ Enable (FALLIE)
When set to one, this bit allows a falling edge on
PWRDN to cause PWRIRQ to go high. It does not mask
PEST bit 2.
Bit I - Rise IRQ Enable (RISEIE)
When set to one, this bit allows a rising edge on
PWRDN to cause PWRIRQ to go high. It does not mask
PEST bit 1.
Bit 0 - Software Mode (SWMODE)
When cleared to zero, this bit causes the chip to operate
in a "hardware driven" mode; that is, the PWRDN pin
directly controls the chip analog power (for low power
consumption). In this mode, a low on PWRDN puts the
chip in low power mode, while a high enables normal
operation. When set to a one, this bit causes the chip to
operate in a "software driven" mode. In this mode,
changes on the PWRDN pin only generate interrupts.
The hardware low power mode is then controlled (via
software) by SOFfPWR (bit 0 of PEST). This function
allows "clean" software controlled turn on and off of
the analog circuitry power.

G-99

II

(I

ICS2002

ICS will provide algorithm and constants data supporting filtering functions for various sample rates.

IR92 reserved
IR93 reserved
IR94 DSP Control/Status (DSPCS)
Bits 7:4 - Index Counter Value (Read Only)
This value indicates the current contents of the DSP
address Index Counter, and is provided as a code debug
aid for use in Step Mode. In normal operation it should
be ignored. It is reset to zero when the DSP is not
running, and increments by one at the completion of
each "pass" of the DSP engine.
Bit 3 - DSP Sequence Complete (Read only)
This bit is set each time the DSP completes its sequence
and restarts. It is reset to zero when the DSPRUN bit is
zero or after a read of this register.
Bit 2 - DSP Output Saturation Detect
This bit is set to one whenever the DSP output value
written to any output destination (DATA RAM, DAC,
or Record FIFO) exceeds a sixteen bit signed range. In
these cases, the DSP output saturates to $7FFF or $8000
(for positive or negative values) rather than overflowing. It is reset to zero when the DSPRUN bit is zero or
after a read of this register.
Bit 1 - DSP Step Mode
This bit is intended as a DSP code debug aid only.
When set to a one, this bit halts the DSP microcode
sequencer at the end of each "pass" of code. This
enables the host to read the DATA RAM contents to
check the results of the previous calculations. Note that
writes to the Record FIFO and DAC will be captured
by the DATA RAM "under" them to aid with debug
efforts. For normal operation, this bit MUST be set to
a zero.
Bit 0 - DSP Run
When written to one, this bit starts the DSP engine
running. A zero stops and resets the DSP engine execution. This bit is reset by MCR.
Before running the DSP, the Code and Data RAMs must be
loaded. To do this, perform the following:
1) write 95h (DSPRA) to the desired address
2) write 96h (Code Ram data) or 97h (Data RAM data) to the
desired l6-bit value.
3) repeat 1 and 2 for all RAM locations of both RAMs.
4) when done, write any data to DSPRA to resetthe load logic.

Note that when the DSP is running, it is forbidden to read or
write either the Code or Data RAMs (except when halted in
STEP mode, see above). Also, after writing to the Code or Data
RAMs to load them, and before starting the DSP, you must reset
the RAM load hardware by writing to the DSPRA register (the
value written is ignored).

IR9S DSP RAM Address Latch (DSPRA) (write only)
Bit 7 - Read
When one, this bit indicates that the next DSP RAM
operation is a read. Zero indicates a write operation.
Bits 5:0 - DSPRAM Address
These bits are the address for the next DSP RAM data
transfer. Note that the Code RAM address can be $00
through $3f, and the Data RAM address can be $00
through $1 F.

IR96 Code RAM Data Port (8/16-bit)
Bits B:O - Code RAM Data
This 81l6-bit port is data to be read from/written to the
DSP Code RAM. The data is the low 12 bits of the word.
IR97 Data RAM Data Port (8/16-bit)
Bits F:O - Data RAM Data
This 81l6-bit port is the data to be read from/written to
the DSP Data RAM. The data is a full 16-bit word.

Record DMA Control and Status Registers
IR98 Record DMA Control (DMACTL)
Bits 7 - reserved
Bit 6 - TC Reset Mask
When set to 1, this bit masks the 'DMA Run' bit reset
upon receipt ofTC, terminal count, signal from the ISA
bus. When reset to 0, the 'DMA Run' bit will be reset
upon receipt of TC.
Bits 5: 1 - reserved
Bit 0 - DMA Run
This bit enables the DMA hardware to begin transferring data when set to one. It is cleared by either MCR
or receipt of a TC when 'TC Reset Mask' is a zero (see
the DMAMODE register for details).

G-IOO

II

ICS2002

IR99 Record DMA Burst Count (RDMABC)
Bits 7:6 - reserved
Bits 5:0 - Record DMA Burst Count
This value determines the number of DMA transfers
that take place for each DMArequest issued to the host.
The actual number of transfers will be RDMABC + 1.
Thus, for single transfer mode, program this register to
zero. The burst counter is automatically preset to the
burst count whenever the DACKR input is high. Thus,
there is no need to reprogram the count value after TC,
since the next transfer will use the full programmed
count value. This register has no affect on 110 Mode
data transfers, since its only influence is over the DRQR
output. This register is not initialized by any means
other than a direct write, and hence must be written to
before DMA is enabled.

Bit 2 - 16-Bit DMA (RDMAI6)
When set to a one, this bit causes the hardware to expect
data to be sent in 16-bit words. When low, the hardware
expects 8-bit bytes. This bit must be set to one when
performing 110 mode transfers, as all 110 transfers are
treated as 16-bit entities.
Bits 1:0 - Record Data Type (RDATATYPE)
These bits direct the hardware how to interpret the
incoming data. Note that this is independent of the
DMA or 110 data width. It effects how data is "signed"
and how data is packed to/unpacked from the Record
FIFO.
Value
00
01

10
11

IR9A Record DMA Mode (RDMAMODE)
All bits in this register are cleared by MCR.
Bits 7:6 - reserved

DataT~

8-bit linear
16-bit linear
reserved
reserved

IR9B reserved

Bit 5 - Terminal Count Interrupt (RTCIRQ) (read only)
This bit indicates that a Terminal Count has been received on the last DMA operation. If the RECIE bit has
been programmed to a one, an interrupt will be generated at the end of the last DMA operation. This bit is
cleared by MCR or a write to STATUS with bit 1 = 1.
The reset state is then removed by either writing the
STATUS bit 0 to 0, or by the next DMA operation.
Hence, there is no need to "remove" this reset as there
is for other IRQ reset operations.
Bit 4 - Record 110 Mode Transfer (RIOXFER)
When this bit is a one, the DMA hardware (DRQR and
RTCIRQ) is disabled. Data transfers take place via RA
$8B (NOT $9B), and are required to be treated as 16-bit
transfers. Thus, data should be read from DLW (with
SBHE = 0, 16-bit data) or from DLW (with SBHE = 1,
8-bit data low byte) followed by DH (8-bit data, high
byte). It is also the programmers responsibility to ensure that RDMAMODE bit 1 (RDMAI6) is set to a one
for all 110 mode transfers.
Bit 3 - Unsigned Data (RUSIGN)
When set to a one, the record FIFO will generate
unsigned data. The native data format is Signed Binary
Twos Complement. ThiS bit Will invert the most sigmficant bit of each data byte (or word, depending on the
state of RDATATYPE).

Record FIFO Control/Status Registers
IR9C Record FIFO Enable/Status (RFES)
Bit 0 - Record FIFO Enable (RFE)
This bit holds the record FIFO in a reset state when low,
and enables the FIFO to operate when high. This bit is
reset by MCR. This bit, when low, also resets all FIFO
related conditions (see the following bits) and prevents
DMA start requests from being issued. It does not reset
the Record FIFO IRQ Mode register.
Bit 1 - FIFO Overflow (read only)
This bit is set when a FIFO shift in command is generated (by either DMA, 110, or the DSP) with the FIFO
full, and indicates an error condition. This bit will cause
the FOUIRQ bit to go active, generating an IRQ if
enabled. This bit is reset by writing to STATUS with bit
4 = 1, and re-enabled by writing to STATUS with bit 4
= o. FE low also resets this bit.
Bit 2 - FIFO Underflow (read only)
This bit is set when a FIFO shift out command is
generated (by either DMA, 110, or the DSP) with the
FIFO empty, and indicates an error condition. This bit
will cause the FOUIRQ bit to go active, generating an
IRQ if enabled. This bit is reset by writing to STATUS
with bit 4 = 1, and re-enabled by writing to STATUS
with bit 4 = o. FE low also resets this bit.

G·IOl

E1

II

ICS2002
Bit 3 - FIFO 25% Full (read only)
This bit goes high after 4 words (or 8 bytes) have been
loaded into the FIFO, and low again when 5 words (or
10 bytes) may be loaded into the FIFO. There is no
interrupt associated with this bit directly.

The following table describes the selections available:

Bits
2:0
000
001
010
011
100
101
110
111

Bit 4 - FIFO 50% Full (read only)
This bit goes high after 8 words (or 16 bytes) have been
loaded into the FIFO, and low again when 9 words (or
18 bytes) may be loaded into the FIFO. There is no
interrupt associated with this bit directly.
Bit 5 - FIFO 75% Full (read only)
This bit goes high after 12 words (or 24 bytes) have
been loaded into the FIFO, and low again when 13
words (or 26 bytes) may be loaded into the FIFO. There
is no interrupt associated with this bit directly.
Bit 6 - FIFO DIR (read only)
This bit goes high when a single word (or two bytes)
may be written to the FIFO. There is no interrupt
associated with this bit directly. Note that this bit resets
to a one because when the FIFO is reset it is forced to
be "empty," and hence is ready to accept data.
Bit 7 - FIFO DOR (read only)
This bit goes high when a single word (or two bytes)
may be read from the FIFO. There is no interrupt
associated with this bit directly.

IR9D Record FIFO IRQ Mode
Bits 7:4 - reserved
Bit 3 - FIFO IRQ Enable (RFlE)
This bit enables the various FIFO capacity thresholds
to generate interrupts (as RECIRQ) when one. When
zero, this bit prevents FIFO capacity IRQ generation
when operating in DMA mode, which only needs
RTCIRQ.

Source
DIR
EMPTY 75%
EMPTY 50%
EMPTY 25%
DOR
FULL 25%
FULL 50%
FULL 75%

Notes
Ready to take 1 word from DSP
Ready to take 13 words from DSP
Ready to take 9 words from DSP
Ready to take 5 words from DSP
Ready to provide 1 word to HOST
Ready to provide 4 words to HOST
Ready to provide 8 words to HOST
Ready to provide 12 words

Note that for byte transfers (RDMAI6=0), the numbers listed
above should be doubled.
This must be programmed before the FIFO is enabled. It may
be changed while the FIFO is enabled if necessary. This register
is cleared by MCR, but not by RFE low.

IR9E reserved
IR9F reserved

Miscellaneous Registers
IRAO Digital Master Volume
Bits 7:0 - Volume
This value is used to scale all values that are output from
the DSP to the DAC. It may be written while the DSP
is running.

Bits 2:0 - FIFO Ready IRQ Mode Selection
This register defines FIFO utilization for both DMA
and YO mode data transfers. In YO mode, it is used to
generate interrupts (RECIRQ) when the FIFO capacity
reaches a predefined point. For DMA transfers, it signals the DMA logic to request a transfer at those same
predefined points. By programming the Record DMA
Burst Count appropriately, the FIFO may be easily kept
near the desired capacity.

G·I02

The value written is interpreted as to give a log scale
output response of 0.1 875dB per step. The value for
nominal (OdB attenuation) is EOh. A value ofFFh gives
5.8125dB of gain. Note that any value above EOh may
result in digital saturation of the internal 16 bit data
value.

ICS2002
IRA 1 DAC De-glitcher Control

Note that this bit, when 0, shuts down the successive
approximation logic, the dynamic comparators and
various logic functions. When the ADC is not being
used, disabling it via this bit reduces background noise
in the playback section and power consumption, and
thus is recommended.

Bits 7:3 - Volume bits 7:3 (read only)
Bit 2 - DAC Enable Bit (read only, for test)
Bits 1:0 - DAC De-glitch Width

IRA5 Analog Volume/Mute
Code
00
01
10
II

Bits 7:5 - reserved

Notes
De-glitcher disabled
Minimum de-glitch width
Nominal de-glitch width
Maximum de-glitch width

Bits 4: I - Analog Volume
These bits set the analog output level, in 1.5dB steps.
All bits one gives OdB attenuation of the DAC output
signal, and all bits zero gives full attenuation. These bits
are unaffected by any reset mechanism.

This value is determined by the clock rate at which the
chip is run. ICS will provide the proper value for an
application. This register is also used for test purposes.
This register is not initialized in any way and should be
programmed before muting is removed.

Bit 0 - Audio Enable
This bit disconnects the audio output of the output
butfer amp and sets the BUFOUT pin to the nominal
bias voltage when cleared to zero. When set to one, it
passes the output of the output buffer amp to the
BUFOUTpin.
The main function of this bit is to prevent sudden DC
offset changes on the BUFOUT pin when entering and
leaving power-down mode. By proper software procedure, noiseless transitions can be made.

IRA2 reserved'
IRA3 reserved

ADC and Analog Control Registers

This bit is cleared to zero by MCR.

IRA4 ADC Control
Bits 7:3 - reserved
Bit 2 - ADC Test Mode
This bit is for factory testing use only, and must always
be programmed to zero by an application. It is reset to
zero by a zero in ADCRUN, and hence takes two writes
of $05 to this register to activate for safety.
Bit I - reserved
Bit 0 - ADC Run
When written to a one, this bit enables the ADC hardware to run. Note that the ADC Timing Control register
should be programmed appropriately first. Also note
that the DSP must be running (and programmed properly) for the conversion results to be retrieved. The
Sample Rate Generator determines the rate at which the
conversion data is loaded into the Record FIFO.

IRA6 ADC Timing Control
This register is used to control the ADC internal operation timing.
Bits 7:4 - Comparator Timing Control
These bits control the time of comparator input switching. Bits 7:5 are the count, and bit 4 is 0 for half cycle
and I full cycle delays.
Bits 3: I - Cycle Timing Control
These bits control the number of clocks used for each
step of the successive approximation process. For the
full 64 step DSP cycle, the value of these bits should be
7. For a 40 step cycle, the value should be 4.
Bit 0 - reserved

This bit is cleared to zero by MCR.

G-I03

II

ICS2002
Ordering Information
ICS2002V or ICS2002V
Example:

ICSXXXXM

L-...".

V=PLCC; Q=QFP

" - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
" - - - - - - - - - - Prefix
ICS, AV=Standard Device; GSP=Gen!ock DevICe

G-I04

II

ICS2008A

Integrated
Circuit
Systems, Inc.

Advance Information

SMPTE Time Code Receiver/Generator

General Description

Features

The ICS2008A, SMPTE Time Code Receiver/Generator chip,
is a VLSI device designed in a low power CMOS process, This
device provides the timing coordination for Multimedia sight
and sound events, Although it is aimed at a PC Multimedia
environment, the ICS2008A is easily integrated into products
requiring SMPTE time code generation and/or reception in
LTC (Longitudinal Time Code) and/or VITC (Vertical Interval
Time Code) formats and MTC (MIDI Time Code) translation,

•

•

The ICS2008A is an improved version of the ICS2008. with
additional features and capabilities.

LTC and VITC Generators
Real Time SMPTE Rates: 30 Hz, 29.97 Hz, 25 Hz,
24Hz
Time Code Modes: Drop Frame and Color Frame
VITC can be inserted on two lines from 10-40
(SMPTE specifies lines 10-20)
- Jam Sync, freewheeling, error bypass/correction,
and plus-one-frame capability

Taking its input from composite video, S-Video, or an audio
track, the ICS2008A can read SMPTE time code in VITC and
LTC formats. Time code output formats are LTC and VITC.
All are available simultaneously. A U ART is provided for the
user to support MTC or tape transport control.
The processor interface is compatible with the IBM PC and
ISA bus compatible computers and is easily interfaced to other
processors.

Internal and external sync sources
- Genlock to video or house sync inputs
- Internally generated timing from oscillator input
- External click input

•

LTC Receiver
- Meets SMPTE and EBU LTC specifications
Synchronize bit rates from 1/30th nominal to 80X
nominal playback speed.

•

VITC reader
- Reads code from any or all selected scan lines.
- Meets SMPTE VITC specifications

New, Improved Features

Block Diagram
Video
Inputs
Video

Output
LTC
Input

Processor
Bus

Processor
Interface

Video
Output

LTC
Output

TxD, RxD

•

Time Code Bum-in Window with programmable
position, size and character attributes

•

Internal Timer, allows 1/4 Frame MIDI Time Code
Messages

•

LTC edge rate control, conforms to EB U Tr and Tf specification

•

Improved video timing lock during VCR pause and shuttle
modes

•

VITC search mode, will search through VBI lines until
VITC is found

•

New UART frequency of 38.4 K baud for tape transport
control

•

Improved video output performance

CTS, RTS

IICS200BAAevC061694

G-I05

ICS2008A
Package Pinout

z+ z ~~tu
I

U U
~ ~

LTCOUT
LFC
XTAL2
XTAL1
AVOO
AVSS
COUT
YOUT
C2
Y2
C1

7
8
9
10
11
12
13
14
15
16
17

0i?(/)

0::

::J
W f-r-OlL.O:: ~o

8(3~8

6 5 4 3 2 o 44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
29

ICS2008A

..- I I I 0 *
>- (/)(/)(/)
WWW ~
0::0::0::

0

~P

*(/)

~

~

.....J
.....J

III

f-f-f-

(/)00

44-Pin PLCC
K-10

G-106

Wf-

t;:::l
0 (,90
0::

~g
5>

02
01
DO
IOW*
VOO
VSS
IOR*
UARTSC*
SMPTECS*
A1
AO

ICS2008A
Pin Description
PIN

TYPE

DESCRIPTION

YI, Y2

AI

Video inputs from camera or other source. NOTE: This is also the Y (Luma)
input for S-VHS and HI-8 systems.

CI,C

AI

C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this pin should be
tied to its respective Y input.

DTHRESH
STHRESH
CTHRESH

AI
AI
AI

Data Threshold bypass input.
SYNC Threshold bypass input.
Clamp Threshold bypass input.

YOUT
COUT

AO
AO

Video output. This is also the Y (Luma) output in S-Video mode.
C (Chroma) output for S-VHS and HI-8 systems.

FRAME
CLICK
LTCIN+
LTC INLTCOUT

AI
AI
AI
AI
AO

Color Frame AlB input. This input is self biased. (See Applications section.)
LTC SYNC input. This input is self biased. (See Applications section.)
SMPTE LTC input+. This input is self biased. (See Applications section.)
SMPTE LTC input-. This input is self biased. (See Applications section.)
SMPTE LTC output.

LRCLK

0

SMPTE LTC receive clock output.

VITC
VITCGATE

0
0

SMPTE VITC output to video mixer circuit.
VITC gate indicates VITC code is being output for video overlay.

TxD
RxD
CTS*
RTS*

0
I
I
0

UART Transmit Data.
UART Receive Data.
Clear to Send.
Ready to Send.

XTALI
XTAL2
LFC

I
0
AI

AI-AD

IOR*
IOW*
SMPTEC*
UARTCS*
RESET
D7-DD
INTR
AVDD
AGND
VDD
GND
A - Analog
P - Power

I
I
I
I/O
0
P
P
P
P

14.318 MHz crystal input. This pin may be driven directly from a TTL 14.318 MHz source.
14.318 MHz crystal oscillator output.
External RC circuit.
Address bus
Read Enable (active low)
Write Enable (active low)
SMPTE port chip select (active low)
UART chip select (active low)
Master reset (active high)
Bi-directional data bus
Interrupt Request (active high)
Analog VDD
Analog Ground
Digital VDD
Digital Ground

I - Input
0 - Output

G-I07

II

ICS2008A
Functional Description
The following is a functional description of the hardware
registers in the ICS2008A chip. It also describes how those
registers can be utilized by the software to facilitate specific
application services.
Hardware Environments
The ICS2008A operates as a peripheral to a processor such as
a PC or a single chip microprocessor. Many of the real time
requirements are satisfied by double buffering both incoming
and outgoing time codes.
LTC Input
LTCIN is a differential analog input feeding a comparator with
hysteresis. It requires capacitive coupling to the LTC source.
The output of the comparator goes to the LTC receiver, which
is capable of receiving LTC in a forward or backward direction
at a rate from 1/30th to 80x nominal frame rates. The incoming
LTC data is sampled with a phase-locked clock and loaded into
the receive buffer following the receipt of a valid LTC SYNC
pattern. When a complete frame has been received, an interrupt
is generated.
LTC Output
The LTC output can be analog or digital. When set up as an
analog output, it can drive a high impedance load.

The LTC generator outputs a LTC frame at the selected frame
rate, such as 24 Hz, 25 Hz, 29.97 Hz or 30 Hz, and starts the
frame based on a start time generated by the selected LTC
SYNC source.
The output edge rate is programmable for SMPTE code
(25Ilsec) and EBU code (50llsec) rise and fall times.
Video Inputs
There are two sets of video inputs. In a composite NTSC or
PAL system, the Y input is the only one used. It is capacitively
coupled to the source. In S-Video systems, capacitively couple
Y and C to their respective sources. Proper termination of the
source should be observed. One of the two video sources is
selected by the VIDSEL bit in the SMPTE control registers as
the video SYNC source. Internal timers are synchronized with
the incoming video to extract timing information used to
receive and generate VITC.

Video Output
The video output combines the selected video input with the
outputs from the VITC generator and the character generator.
It can be a composite or an S-Video output as selected by the
SVID bit in the SMPTE control registers.

VITC code is generated from data in the VITC generator buffer
and output during the selected line time(s). The CRC and
synchronizing bits are automatically generated by the VITC
generator, but all of the data fields are sent directly from the
buffer with no modification.
A character generator is provided to insert the time code in a
bum-in window which overlays the incoming video. The vertical and horizontal position of the bum-in window is programmable.
SMPTE SYNC Sources
A time code generator must have a SYNC input from a stable
source in order to position the LTC code properly on a audio
track of video tape or film. Three SYNC sources, video, click
input, and free running, are available. In the case of a video
tape, LTC code must start within plus or minus one line of the
beginning of line 5. This requires "Genlocking" to the incoming video. The video timing section locks to the video's horizontal and vertical SYNC signal and generates a SMPTE
SYNC. If some external SYNC source is available it can be
input on the CLICK input. Otherwise, a free running SMPTE
SYNC is generated from the oscillator at the selected frame
rate.
Video Timing Generator
The video timing generator is "Genlocked" to the video input's
SYNC separator. It extracts NTSC or PAL timing information
from the video input and generates line and pixel rate timing
for the VITC receiver, VITC generator, LTC generator and
character generator. If no video input is present, it generates
free running timing.
Overlay Character Generator
It is sometimes desirable to display the time code on a video

display along with the picture. A character generator is provided for that purpose. The time code display, or bum-in
window, can be positioned anywhere on the screen. It can be
displayed in two sizes with white or black characters on a
black, white or live video background.

The VITC receiver samples the incoming video looking for a
valid VITC code on selected scan lines. When a valid code is
received it is written to a VITC receive buffer. More than one
line can contain VITC code, and the codes can be different.
For this reason, VITC codes from selected lines of a frame are
written to separate VITC buffers.

G-I08

II

ICS2008A

UART
A general purpose UART is provided for MIDI, video transport
control, etc. Most serial interface transport controls use 9600
and 38.4K BAUD. The CTS and RTS modern controls are
needed in these applications. MIDI ports use 31.25K BAUD,
but they do not require modern controls. The receiver includes
a four byte FIFO to reduce the real time interrupt servicing
requirements. This is particularly important in MIDI applications because of the high data rate and the fact that many MIDI
messages are three bytes long. The transmitter is doubled
buffered. Interrupts can be generated on both receiver data
available and/or transmit buffer empty.

The SMPTEO Register contains the SMPTE interrupt controls
and status and the VITC read status. The four interrupt bits,
LRI, LXI, VLI and TMI reflect the status of the potential
interrupt sources to the processor. When a bit is set to one and
the corresponding enable bIt, LRIEN, LXIEN or VLIEN, is
also set, the INTR output will be activated. Interrupts are
cleared by reading SMPTEO.
7 6 5 4 3 2 1 0

I ~~~L- ~~~r(~6~~~~~~t~~~)

LXI (LTC XMT Interrupt)
VLI (Video line Interrupt)
LRIEN (1-enable, O-dlsable)
LXIEN (1-enable, O-dlsable)
VLI EN (1-enable, O-dlsable)
TMI (Timer Interrupt)
TMIEN (1-enable, O-dlsable)

Interrupt Timer
The interrupt timer is a general purpose 10 bit timer with three
clock sources (100 kHz, the LTC receive clock and the LTC
transmit clock). Although the timer is general purpose in
nature, its main purpose is to facilitate the timed generation of
MIDI time code messages.

Processor Interface
The ICS2008A supports standard microprocessor interfaces
and busses, such as the PC bus, to allow access to six control/status and data registers. These six registers are organized
into two groups, one set of four for SMPTE control and the
other set of two for direct UART port control. Each set of
registers is selected with its own chip select, SMPTECS* and
UARTCS*.
SMPTE Registers
The SMPTE register set allows access to four direct and 64
indirect registers. The first two direct access registers addressed at locations 0 and I are for status and interrupt control.
The 64 indirect registers are accessed by writing an indirect
address into SMPTE2 and reading from or writing to SMPTE3.
If the AUTOINC bit in SMPTE2 is setto I, the indirect register
address is automatically incremented after an access to
SMPTE3. This eases the task of reading or writing sequential
indirect locations.

SMPTECS*
0

Al
0

0
0

0
I

0

I

AO
REGISTER
0 SMPTEO Interrupt
Control/Status
I SMPTEI SMPTE Status
0 SMPTE2 Indirect Register
Address
I SMPTE3 Indirect Register
Data

SMPTEO

I I I I I I I I I

LRI - This bit indicates that a LTC receive interrupt has
occurred. In order for an actual processor interrupt to occur,
the LRIEN bit must also be set. An LRI interrupt occurs upon
reception of the last byte of LTC receive data which was
preceded by a valid LTC SYNC pattern. That is after the 64th
LTC receive bit time in the forward direction. At normal frame
rates, if the LTC transmitter is synchronized with the LTC
receiver, there is about 3 milliseconds after this interrupt before
the LTC transmit data for the next output frame is transferred
to the output buffer.
LXI - This bit indicates that a LTC transmit interrupt has
occurred. When this bit is set, and the corresponding LXIEN
bit has been set, the INTR output will be activated. The LTC
transmit interrupt is activated after the transfer of LTC transmit
data to the output buffer. This occurs after LTXEN is set to one
and after the nod LTC transmits bit time of the current frame,
"N." Data loaded after this interrupt will appear in output frame
"N+2" since the transmitter is double buffered.
VLI - This is a status bit that indicates that the video line
selected via the Video Interrupt Line Register, VR9, has
passed. When the VLIEN bit is also set, the processor will be
interrupted. This interrupt can be used by the processor to
determine when to sample the VITC time code when time
locked to a video source. It will also be used to facilitate
detection of LTC time code dropout and off speed LTC code,
e.g. shuttling operations.
TMI - This bit indicates that a timer interrupt has occurred.
When the TMIEN bit is also set to a one, the INTR output will
be activated. This interrupt is intended to facilitate timing
MIDI clocks and MIDI Quarter Frame messages.

G-I09

ICS2008A
The SMPTE Status Register is a read only register which
contains video and LTC status.
7 6 5 4 3 2 1 0

I I I I I I I I I

I ~~~'-

SMPTE1
SMPTE Status Register

The SMPTE2 register is the register which points to the 57
indirect registers. When reading or writing an indirect register,
the value in the ADDRESS pointer, SMPTE2 bits 5 to 0, is the
address of the register accessed through SMPTE3. If the
AUTOINC bit is set to one, at the end of an access cycle to
SMPTE3, ADDRESS will automatically increment. Otherwise, ADDRESS holds its value.

FRAMEIN(input=l-high,O-low)
L - CLICK
(input = 1-hlgh, O-Iow)
LTCLOCK (l-locked, O-not locked)
CODEDIR (l-bkwd, O-fwd)
reserved
VLOCK (Hocked, O-not locked)
FIELD
FRAME (PAL only)

FRAMEIN - This bit indicates the state of the FRAME input
pin. It is used as an alternate source for BIA frame status. This
is useful when the quality of the video signal is not good
enough to extract the BIA frame status.
CLICK - This bit indicates the state of the CLICK input pin.
It can be used as a synchronization source for the LTC transmitter.
LTCLOCK - When a valid forward or backward LTC sync
pattern is detected, this bit is set to one. It is reset to zero when
an expected LTC sync pattern is missed or an invalid LTC bit
is detected.
CODEDIR - The code direction bit works in conjunction with
the LTCLOCK bit. When the LTCLOCK bit is set to one, the
CODEDIR bit is valid. Otherwise, it is not. See the table below.

LTCLOCK

0
I
I

FRAME & FIELD - The hardware SYNC separator detects the
field and frame from the selected video input. The even/odd
fields are identified by a 110 in bit 6. Bit. 7, FRAME, is valid
for PAL video after line 6. Bit 6, FIELD, is valid after line 5 in
NTSC mode or line 2 in PAL mode.

76543210

I I I I I I I I I

II

~

SMPTE2
Indirect Address Register
ADDRESS
reserved
AUTOINC (l-increment, O-hold)

SMPTE3 is the data register through which all of the indirect
registers are accessed. The address for a given register must
first be set in SMPTE2 before accessing that register.
7 6 5 4 3 2 1 0

I I I I I I I I I

CODEDIR
LTC RECEIVER STATUS
X
Looking for SYNC pattern
receiving LTC (FORWARD)
0
receiving LTC (BACKWARD)
I

VLOCK - This is a hardware driven bit which indicates that
genlock has been achieved with the selected video SYNC
source.

G·110

SMPTE3
Indirect Address Register

II

ICS2008A

Indirect Registers
The following describes the functions controlled by the indirect registers. A map of the indirect registers follows this
section.

IR29 selects the video line which starts the SMPTE video
display window in the video output. When this register is set
to zero, there will be no Burn-In Window displayed in the video
output.

LTC Read Registers IRO-IR7 (read-only)
These read only registers contain the LTC data as received.
Both forward and backward frames are stored with LTC bit 0
in the LSB ofIRO and LTC bit 63 in the MSB of IR7.

CIT I I I I I I Burn-In Window LI"~

LTC Write Registers IR8-IRF
These registers contain the data to be sent by the LTC transmitter. The LSB of IRS is sent as LTC bit 0, and the MSB of
IRF is sent as LTC bit 63. The data is transmitted as it is stored
in IRS-IRF.
VITC Read 1 Registers IRIO-IR17 (read-only)
These read only registers contain the VITC data as received
from the video line selected in IR30. The frame is stored with
VITC bit 2 in the LSB ofIRIO and VITC bit SO in the MSB of
IR 17. Note that a binary 10 sync pattern precedes every eight
data bits of the VITC frame. The 10 sync pattern is not stored.
The CRC is checked by the VITC receiver, and the result is
reported in IR30.
VITC Read 2 Registers IR18-IRIF (read-only)
As with the VITC Read I registers, these read only registers
contain the VITC data as received from the video line selected
in IR31. The frame is stored with VITC bit 2 in the LSB of
IRIS and VITC bit SO in the MSB of IRIF. The result of the
CRC check is reported in IR31.
VITC Write Registers IR20-IR27
These registers contain the data to be output by the VITC
generator. The VITC frame is output with the LSB of IR20 in
VITC bit 2 and the MSB ofIR27 in VITC bit SO. Note that the
binary 10 sync pattern which precedes every eight data bits of
the VITC frame is automatically generated by the VITC generator. The CRC is also automatically generated by the VITC
generator.
BI Window Registers IR28 & 29
The next two registers control the position of the SMPTE video
display, burn-in, window within the video raster. IR2S selects
the video column (horizontal position) in which the burn-in
window starts.
7 6 5 4

I I

3 2 1 0

I I I I I I

7 6 5 4

Column

IR29

line (00 - disable)

BI Character Registers IR2A-IR2D
These registers contain the character codes used for the
SMPTE time code in the burn-in window which overlays the
source in the video output. An internal character generator
converts the BCD nibbles to display characters.
7 6 5 4 3 2 1 0 IR2A (Frame),

O I I I I I I II'R2B (Seconds),
D
(Minutes),
~~~~~~d·IR2C

'----r-'
Tens

CODE
0

'----r-'
Ones

IR2D (Hours)
Burn-In Window Registers

CHARACTER
0

I

I

2
3
4
5
6

2
3
4
5
6

CODE
S
9
A
B
C
D
E

CHARACTER
S
9
Do Not Use
?

-

0

•

VITC Write Line Select Registers IR2E & IR2F
VITC code is normally output on two separate video lines in
each field for redundancy. These two registers allow the individual line selection and output enables for the two VITC lines.
7 6 5 4

3 2 1 0

IR2E

I I I I I I I I I VITC Wnte LI!l~l
~
I LTIl..______
7 6 5 4 3 2 1 0

Wnte Line #10-40 (N+ 10)
reserved
VITC Write Enable (I-enable)
IR2F

lIT I I I I I I I VITC Wnte Line 2

It

IR28

Burn-In Window Column

3 2 1 0

~

Wnte Line #10-40 (N+ 10)
reserved
VITC Write Enable (I-enable)

Write Line - Selects the video line on which the VITC code
will be output. The video line on which the code is output will
be the number in this register plus 10; e.g. writing a one to this
register will cause the code to be output on line 11.
VITC Write Enable - Enables the output of VITC code on the
specified line.

G-lH

II

ICS2008A

GENLOCK ENABLE - When set to one, this bit enables the
genlock circuits to sync to the selected video input signal.
When reset to 0, the video sync will "freewheel," generating
video timing from the internal oscillator. The freewheel mode
would be selected when striping LTC to allow synchronization
with a MIDI sequencer or other strictly timed audio source.

VITC Read Line Select Registers IR30 & IR31
76543210

ITJ I I I I I I

III'

=--

76543210

IUlIIIIIII

I I I =--

IR30
VITC Read Line 1

Read line 10-40 (N+ 10)
CRCERR (1-error, O-OK) (r/o)
NOCODE (1-no code, O-code) (r/o)
VITC Read Enable (1-enable)

VTRES - When set to one, this bit clears the video timing
counters to dot zero ofline I of field 1. This is useful when the
video is free running, not genlocked and LTC sync needs to be
synchronized to an event such as the CLICK input.

IR31
VITC Read line 2

Read Line 10-40 (N+10)
CRCERR (1-error, O-OK) (r/o)
NOCODE (1-no code, O-code) (r/o)
VITC Read Enable (1-enable)

As with the VITC Write Line Register, these registers allow
control of the individual redundant VITC read lines. The
processor can also reprogram these dynamically to allow for
scanning of VITC code when the source lines are unknown.
Read Line - Selects the line from which VITC code is to be
read within each field. It works identically to the Write Line in
that the video line selected is the number in this register plus
10.
Auto line scanning is enabled by writing a I Fh to the Read Line
field. This causes the VITC reader to search for time code. If
VITC Read Line 1 is set to search, it starts with line 10 and
quits when it finds a valid time code or when it reaches line 41.
Searching with VITC Read Line 2 starts after VITC Read Line
1. In the case of searching for both VITC Read Lines 1 and 2,
VITC Read Line 2 starts searching after the first valid time
code has been found. However, if VITC Read Line 1 is set to
a specific line, VITC Read Line 2 starts after that specified line
regardless of whether valid time code was received. In any
case, the search terminates after line 41.
CRCERR - This bit is reset to zero when a valid VITC code
has been received. It is valid from the eud of the selected video
line until the end of the selected line in the next field.
NOCODE - This bit is set when a framing error occurs in the
VITC code, i.e. not all the bits of the code were received by
the time the end of the video line occurred. Both CRCERR and
NOCODE must be zero to qUalifY a VITC code.
Video Control Register IR32
7 6 5 4 3 2 1 0

LIlli

VITCSEL - When set to one, this bit selects the video input
source from Vide02 (Y2) to be the VITC time code source for
the VITC receiver. Otherwise, when reset to zero, Videol (YI)
is selected.
VOUTSEL - When set to one, this bit selects the video input
source from Vide02 (Y2, C2) to be output on the video outputs
(YOUT, COUT). When reset to zero, Videol (YI, CI) are
selected.
VID LS - When set to one, this bit causes the Video I source
to be treated as S-Video. Otherwise, when cleared to zero, the
Video I source is treated as composite video.
VID2_S - When set to one, this bit causes the Vide02 source
to be treated as S-Video. Otherwise, when cleared to zero, the
Vide02 source is treated as composite video.
PALINTSC - When set to one, this bit causes the video to be
synchronized with PAL timing. Otherwise, when cleared to
zero, video is synchronized with NTSC timing.
Video Interrupt Line Register IR33
This register selects the video line after which the Video Line
Interrupt will occur. The actual video line number is the number in the register plus one.

76543210

I I I I I I I I I

L

IR32 Video Control Register

I I IJ

~

VSYNCSEL - When set to one, this bit selects the video input
source from Vide02 (Y2) to be the SYNC source for the
internal video timing. Otherwise, when reset to zero, Video I
(Y I) is selected.

GENLOCK ENABLE (1-lock, O-freewheel)
VTRES - Video Timing Reset (1-reset)
VSYNCEL - Video SYNC Source Select
VITCSEL - VITC Source Select
VOUTSEL - Video Output Select
VID1_S - Vlde01 S-vldeo Select
VID2_S - V,de02 S-Video Select
PAUNTSC (1-PAL, O-NTSC)

G-112

--,==:~

<---I

IR33
Video Interrupt Line Register
Video Interrupt Line (1 to 64)
reserved

ICS2008A
LTC Control Registers IR34-IR37
7 6 S 4

I

I

i

I

3 2 1 0

I

I

I

I

~

7 6 S 4

IR34

I LTC Control Register 1
EDGERATE -(O-2Susec., 1-S0usec.)
LXTFREE - (O-LTCYNC start)
(1-free start)
reserved (set to zero)
LXCLKSEL - (O-Internal clock)
(1-LTC receive clock)
LTXEN - LTC Transmit Enable
LTC SYNC - (OO-vldeo,01-CLlCK)
(10-LTC RCV, 11-Software)
LTCOUTSEL -(1-dlgltal, O-analog)

EDGERATE - This bit selects the LTC output edge rate.
SMPTE specifies 25 ~sec rise and fall times while EBU
specifies 50 ~sec.
LTXFREE - This bit controls the LTC frame start of the LTC
transmitter. When reset to zero, the start of a LTC output frame
is triggered by the selected LTC SYNC source. Otherwise,
when set to one, the end of a LTC frame will trigger the start
of the next. The first LTC transmit frame must be triggered by
one ofthe SYNC sources.
LXCLKSEL - This bit controls the source for the LTC transmit
clock divider input. A 0 selects the internal 14.318 MHz clock
and a I selects the LTC receive clock. When the LTC receive
clock is selected as the source to the LTC transmit clock
divider, the clock rate is first doubled before being input to the
divider so that loading a divider value of 001 will result in the
LTC transmit clock running at the exact same rate as the LTC
receive clock.
LTXEN - This bit, when set to 1, enables output of LTC code
on the LTCOUT output pin. LTXEN is synchronized with the
selected LTC SYNC source to ensure that only complete LTC
frames are transmitted. The data to be sent by the LTC transmitter should be loaded into the associated RAM buffer before
the LTCEN bit is set.

3 2 1 0

1:

IL I

I

I

I

I

1

I

I

I

IR35

I LTC Control Register 2

1

.

LTCGAIN _ LTC Output Gain
O' off
4. -24dB 8. -12dB
1
5 -21 dB 9' -9dB
2:
6 -18dB A -6dB
7. -1SdB B -3dB
3
reserved

C'
D.
E:
F:

OdB
3dB
6dB
9dB

LTCGAIN - This bit sets the signal gain on the LTC audio
output. The output gain is selectable in 3dB increments from
-24dB to +9dB referenced to OVU = -1 Odb V. When this register
is set to zero, there is no LTC audio output.
These next two write only registers, IR36 and IR37, control the
LTC transmit bit rate. The transmit clock generator is a 12-bit
divider. The upper four bits of IR37 are not used. Each bit
requires two clocks. Therefore, the LTC transmit bit rate is the
input clock divided by the divider value + I, then divided by
two. Since there are 80 bit times for each LTC frame, the LTC
frame rate is the bit rate divided by 80.
LTC Tx Clock = 14.318 MHz/(Divider Value + I)
LTC Bit Rate =LTC Tx Clockl2
LTC Frame Rate = LTC Bit Rate/80
The table below shows the divider values for some of the most
commonly used LTC frame rates.
LTC FRAME RATE
30 Hz
29.97 Hz
25 Hz
24 Hz

7 6 S 4 3 2 1 0
I

LTC SYNC - These bits select the LTC transmit sync source.
Values 00,01,10 and 11 select start of video line 5, rising edge
of CLICK, LTC receive sync pattern detect and write to IR3F
respectively as the sync event. Care should be taken to disable
LTXEN before changing the LTC SYNC select. Otherwise, an
erroneous sync may be generated.
LTCOUTSEL - This bit, when set to I, causes the LTCOUT
pin to be a digital output. When cleared to 0, the LTCOUT pin
is an analog output with gain control.

G-113

I

I

I

I

I

DIVIDER VALUE
BA6h
BA9h
DFBh
E90h

IR36 [low byte]

IlJl,~~_~~g~~~t~QIlly)

II

ICS2008A
Timer Control Registers IR3C & IR3D
These two registers control the interrupt timer. It should be
noted that IR3C is a write only register, while IR3D is a
read/write register.
7 6 5 4 3 2 I 0

[I I I I I I I

76543210

o

IR3e
Timer Valu(3jw/o)
TMRVAL[7:0]

7 6 5 4 3 2 I 0

r 'L

W
I

ll:

IR3E
Burn-In Window Attribut~
BLINK [I-blink, O-stable]
WINATTR
(~O-white on black, Ol-black on white)
(IO-white on bkgd, II-black on bkgd)
WINSIZE (I-large, O-normal)
HSF [I-enable, O-disable]
reserved

BLINK - This bit controls the upper dot of the right-most colon
in the burn-in-window. When set to zero, the upper dot is on.
When set to one, it is off. This feature can be used to indicate
odd and even fields in the time code display window.

IR3D

I I I I I I Timer Control (r/w)

'I'

I I I I I I]

'MRVAC!",
reserved

WINATTR - These two bits control the color of the characters
and the background in the burn-in window. When the most
significant bit of this field is a one, the background is the
incoming video.

CLKSEL
(OO-LXCLK, Ol-LRCLK)
(IO-reserved, 11-100 kHz)
RUN (I-run, O-stop)

TMRVAL - These ten bits set the divder value for the interrupt
timer. The interrupt rate is the input clock rate divided by the
value plus one.
Interrupt Rate = CLOCKI(TMRVAL+ I)
CLKSEL - This 2 bit field selects the clock source for the
interrupt timer. The 100 kHz input is actually 100.126 kHz. It
is the crystal frequency divided by 143.
RUN - This bit starts and stops the timer. When set to one, the
timer is running. When set to zero, the timer is stopped.

WINSIZ - This bit controls the size of the burn-in window. The
difference in size between a large and a normal-sized window
is 32 scan lines high, while a large window is 64 scan lines
high.
HSF (Head Switch Filter) - When set to one, this bit causes the
clamp circuit to ignore head switch transients and horizontal
sync during the last six to seven lines before the vertical front
porch. Otherwise, the clamp circuit responds always.
LTC Soft Sync IR3F
IR3f is not a register at all. It is simply an address which, when
written and the LTC SYNC select is set for Soft SYNC,
generates LTC SYNC for the LTC transmitter.
76543210

ILl I I I I I I I

G-U4

IR3F

1,TC Soft SYI\!Q (w/o, no data)

II
7
LTC
Read

LTC
Write
VITC
READ1

VITC
Read2

00
01
02
03
04
05
06
07
08

OF
10
11
12
13
14
15
16
17
18
1F
20

Regs

27
28

I
I

2
1
0
I
I
FRAME UNITS
FRAMES TENS
COLR FRAME I DROP FRAME I
SECONDS UNITS
PHASECORRI
SECONDS TENS
MINUTES UNITS
MINUTES TENS
BG FLAG 55 I
HOURS UNITS
BG FLAG 75 I UNASSIGNED I
HOURS TENS

4

3

I
I

I
I

I
SAME BIT DEFINITION

I
I

I
I

I
SAME BI DEFINITION

is
isI

I
I

I
VITC READ11 BUFFER

I
I

I
I

I
VITC READ11 BUFFER

I
I

I
I

BURN·IN WINDOW COLUMN

29

•••••••••••••••••••••••••••••••••

BURN·IN WINDOW LINE

•••••••••••••••••••••••••••••••••

FRAMES

2B

•••••••••••••••••••••••••••••••••

SECONDS

2C

•••••••••••••••••••••••••••••••••

MINUTES

2D

•••••••••••••••••••••••••••••••••

HOURS

::

I
I

FRAME UNITS
COLR FRAME I DROP FRAME I
FRAMES TENS
SECONDS UNITS
SECONDS TENS
FIELD MARK I
MINUTES UNITS
BG FLAG 55 I
MINUTES TENS
HOURS UNITS
BG FLAG 75 I UNASSIGNEDl
HOURS TENS

2A

2E
2F
30
31
32
33

I

I
I
SAME BiT DEFINITION AS LTC READ iUFFER

BINARY GROUP 1
BINARY GROUP 2
BINARY GROUP 3
BINARY GROUP 4
BINARY GROUP 5
BINARY GROUP 6
BINARY GROUP 7
BINARY GROUP 8

...

...

6
5
BINARY GROUP 1
BINARY GROUP 2
BINARY GROUP 3
BINARY GROUP 4
BINARY GROUP 5
BINARY GROUP 6
BINARY GROUP 7
BINARY GROUP 8
I
I

...

VITC
Write

ICS2008A

Indirect Register Map

VITC1WE
VITC2WE
VITC1RE
VITC2RE
PAL
0

o
o
NOCODE1
NOCODE2
VID2_S
0

0-··········
0-··········

VITC WRITE LINE 1
VITC WRITE LINE 2
CRCERR1 •••••••••••
VITC WRITE LINE 1
CRCERR2- • • • • • • • • • •
VITC READ LINE 2
•••••••••••
VID1_S
VOUTSEL I VITCSEL I VSYNCSEL I VTRES
I GEN_EN
•••••••••••••••••••••• VIDEO LINE INTERRUPT {LlNE#} •••••••••••••••••

LTCO~TSEL ····OLTCSYiCSEL~ ••• I

LTXEN

I ~~~~~~~~.I••••• ~•• LTCIG~;:~.~~~ ••I.~~~.~~~~~

36
••••••••••••••••••••••••••••••• FRAME RATE (low byte, write only) •••••••••••••••••••••••••••••••
37
II
I
0
I
III
0
FRAME RATE (high byte, write onlv)· ••••• 38
reserved
reserved
39
3A
reserved
3B
reserved
3C •••••••••••••••••••••••••••••••• TIMER VALUE (lOW byte, write only) •••••••••••••••••••••••••••••••

1 .......

3D
3E
3F

RUN
I
CLKSEL
I
0
I
0
I
0
I
TIMER VALUE {hi!lh}
0
0
0
HSF
WIN SIZE I
WINDOW ATTRIBUTE
I
BLINK
• • • • • • • • • • • • • • • SOFT LTC SYNC (write only, no data) • • • • • • • • • • • • • • • •

G-115

E1

II

ICS2008A
UART Registers
The UART emulates a 6850. Since the UART is tailored to
MIDI applications, some of the generic 6850 functions have
been omitted. The registers described below reflect that.
The two UART registers, Command/Status and Data, are accessible to the processor as shown in the following map.

UARTCS*

Al

AO

0

X

0

0

X

1

FE - Bit 4, Framing Error, when set to 1, indicates that the
receive character was improperly framed by the start and stop
bits. It is detected by the absence of the first stop bit. This
indicator is valid as long as the character data is valid.

UARTO (write)

OV - Bit 5, Receiver Overrun, is an error flag indicating that
one or more characters in the data stream has been lost. It is set
to I when a new character overwrites an old character which
has not been read. The overrun error is cleared to 0 when a
character is read from the UART data register.

I I I I I I I I I UART Command Register

TI
I

I

~

TBE - Bit I, Transmit Buffer Empty, is cleared to 0 when data
is written to the UART data register. It is set to I when the
UART transfers that data to its output shift register.
CTS - Bit 3, Clear-to-Send, is an active low status bit indicating
the state of the CTS* input pin. A 0 in this bit position indicates
that the modem or receiving device is ready to receive characters. A I indicates not ready. When CTS is inactive, I, TBE is
held at 0, the not-empty state.

REGISTER
UART Command/Status
Register
UART Data Register

UART Command/Status Register
7 6 5 4 3 2 1 0

RBF - Bit 0, Receive Buffer Full, is set to I when read data is
available in the UART data register. It is cleared to 0 when the
UART data register is read.

Bit Rate

(00 - 9600, 10 - 38.4K)
(01 - 31.25K, 11 - Reset)

reserved
TC1, TCO - Transmit Control
00 - RTS' - low, Tx IRQ disabled
01 - RTS' - low, Tx IRQ enabled
10 - RTS' - high, Tx IRQ disabled
11 - RTS' -low, Transmit BREAK,
Tx IRQ disabled
RIE - Receive Interrupt Enable

IRQ - Bit 7, Interrupt Request, is a status bit which reflects the
state of the interrupt request from tbe U ART to the processor.
When IRQ is I, an interrupt is pending. Otherwise, no interrupt is pending.

Bit Rate - This field selects tbe bit rate for data transmit and
receive. After a master reset, its value is II. One of tbe tbree
bit rates must be selected in order to start the UART's operation. Writing a II will reset the UART.
TCI,TCO - Bits 6 and 5, Transmit Control, provide control for
transmit interrupt (when TBE is true), RTS control, and transmit BREAK level.

The UART data register is actually two registers, a transmit
buffer and a receive buffer. Writing to the data register causes
the transmit buffer to be written. Reading from the data register
causes the receive buffer to be read.
76543210

I I I I I I I I I

RIE - Bit 7, Receive interrupt enable, when set to one, enables
tbe UART to interrupt the processor when the receive buffer is
full or a receive overrun has occurred.
76543210

I I I I II I I I

~

UARTO (read)
UART2 Status Register
RBF - Receive Buffer Full (l-Full)
TBE - Transmit Buffer Empty (l-Empty)
reserved
CTS - Clear-to-Send (O-Actlve)
FE - Framing Error (l-Error)
OV - Receiver Overrun (1-0verrun)
reserved
IRQ - Interrupt Request (l-Active)

G-116

UART1
UART....Q."!.'!.Register

II

ICS2008A

Absolute Maximum Ratings

q,

Operating Temperature ............... °c to +70:C
Storage Temperature .............. -65 C to +150 C
Voltage on any pin to GND ....... -0.5V to Voo + 0.5V
Voltage on Voo to GND . . . . . . . . . . . .. -0.5V to +7.0V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 watt

DC Characteristics

TA=O °c to +70 °C; Voo = 5V±IO%; GND = OV

PARAMETER
Digital Inputs
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Digital Outputs
Output Low Voltage (lOL = 4.0rnA)
Output High Voltage (IOH = O.4rnA)
Tri-State Current
Output Capacitance
Bi-Directional Capacitance
Analog Inputs
Video Input Voltage (Y I, Y2, C I, C2)
LTC Differential Input Voltage
LTCIN+, LTCIN-, CLICK, FRAME input voltage
CLICK and FRAME bias voltage
Analog Outputs
Video output Voltage (YOUT, COUT)
LTC Output Voltage (Volume set at max.; lout = 35mA)
LTC Output Voltage Amplitude Control Step
LTC Output Voltage Amplitude Range
Analog Voo Supply Current
Digital Voo Supply Current

AC Characteristics

Note: Stress above that listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only. Operating the device at these levels is not
recommended, and specifications are not implied.

SYMBOL

MIN

VIL
VIR
ILl
CIN

-0.5
2.0

VOL
VOH

TYP

MAX

UNITS

0.8
Voo+O.5
10
7

V
V
uA
pF

0.4

V
V
uA
pF
pF

2.4

loz

10
10
10
1.0
0.1
-0.3

Voo+O.3
Voo/3
1.0
2.0
3
33
50
5

IODl
IOD2

V p_p
V p-p
V
V
V p-p
V p-p
dB
dB
rnA
rnA

TA=O °c to +70 °C; Voo = 5V±IO%; GND = OV

PARAMETER
Address setup to IOR* or IOW* command
Address hold from IOR* or IOW* command
Read pulse width
Access time
Output enable access time
Data hold from lOR * high
Read command inactive time
Write pulse width
Write data setup to IOW* high
Write data hold from IOW* high
Write command inactive time
CS * inactive time (Note I)
UART Port Bit Rate (Command Register [1:0]=00)
(Command Register [1:0]=01)
(Command Register [1:0]=10)

SYMBOL
tACS
tAH
tRD
tACC

MIN
20
10
150

TYP

150
50

toE

tRDH
tRHRL
tWR
twos
twOH
twHWL
tcHCL

MAX

10
70
150
20
10
70
20
9.6
31.25
38.4

Note 1: This timing parameter must be met for proper operation of indirect register access using auto-increment.

G-117

UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

kHz
kHz
kHz

ICS2008A

A1-A0

D7-D0ZlOO~~x::::tt=~~~~;tt~~-t~
SMPTECS*

IOR*
IOW*

Figure 3 - Host Processor Bus Timing

G-llS

ICS2008A
Applications
Crystal Oscillator
This oscillator will operate proper! y with either a
serial or parallel resonant
crystal. If frequency accuracy is critical, a parallel
resonant crystal is recommended.

r

10 XTAL1

9

+5V
L -_ _

r

XTAL2

....::8~ LFC

Threshold Bypass Pins
These pins provide access to the internal references for clamp
level (CTHRESH), SYNC slicer (STHRESH), and data slicer
(DTHRESH). In general, these pins are left open, and the levels
are output. However, should the user want to set other levels,
these pins can be over-driven with the desired threshold
level(s).

CTHRESH is the threshold to which the input video sync tips
are clamped. The CTHRESH level is nominally l.3V. With the
incoming video riding on this 1.3V DC level, the internal
SYNC separator sizes the video at 20 IRE up from the SYNC
tips. This level, STHRESH, is nominally 0.14V above
CTHRESH. The SYNC separator ignores short pulses which
fall below the STHRESH level such as these that come from
the chroma component of the video. DTHRESH is the data
slicer reference. It is nominally 0.57V above CTHRESH.

Video Inputs
Yl, Y2, Cl and C2 pins
must be capacitively cou-

pled to the terminated
video source( s). These inputs are clamped to the
CTHRESHlevel.Atypical
coupling capacitance is
.IuF.

18

COMPOSITE IN

T'~
:~

Yl

.1 uF

17 Cl

Bias
YIN

18 Yl

"

. 1uF

~

..

C IN

17

Video Outputs
YOUT and COUT are outputs of analog multiplex70
ers which select the video
sourcefrom Y 1, C I or Y2,
C2. These outputs are not
buffered. This minimizes
signal distortion. It is,
70
therefore, important to
keep the capacitive and resistive load on the YOUT
and COUT pins to a miniutput
mum. A video output buffer
is shown in Figure 7. If DC coupling is desired, the plus input
of the opamp should be high impedance with a low bias current,
and its output should be able to drive a 75 ohm load with an
appropriate video bandwidth. In general, composite NTSC and
S-video signals have a bandwidth of 4.2 MHz. A minimum
output buffer bandwidth of 10 MHz is recommended.Care
should be taken in board layout to minimize stray capacitance
on the YOUT and COUT pins. Otherwise, there could be high
frequency roll-off which could result in a loss of chrominance
amplitude.

C1

.1 uF

...'"

Self Biased Inputs
The CLICK and FRAME
inputs are biased to 112
VDD and connected to
plus inputs of two comparators. The minus inputs
are internally biased to 112
VDD. When CLICK or
FRAME sources are analog, they should be capaciti vely coupled to the input
pin. However, if the
sources are digital, they
may be tied to the pins directi y. It is important to
make sure that the digital
levels into these pins swing
above and below the 112
VDD threshold of the comparators. This is not a problem with
digital CMOS sources, but it could be with TTL sources.

LTCIN+ and LTCIN- are comparator inputs for the LTC input.
This differential input is provided to maximize noise immunity.
If the LTC source is single ended, the LTCIN- should be
capacitively coupled to the ground reference of that source. If
the LTC source is digital, set the LTCIN- to the desired threshold, and connect the digital source to LTCIN+.

Figure-6 - S-Video Input

G-119

II

ICS2008A

The ICS2008A is a SMPTE time code input/output device with
a UART which can be used as a MIDI UART or transport
control UART. All of the time critical functions to read and
generate time code are performed by the chip's hardware, but
all of the intelligence for processing time codes and generating
the time code values are performed via an external processor.
This makes the ICS2008A flexible enough for a broad range
of applications without making the processing requirements on
the host system too great.

Reading LTC
When LTC data is received, it is placed into a temporary buffer
and transferred into the LTC read register (IRO to IR7) when
the last bit of LTC data has been received. It should be noted
that the data is transferred before the SYNC pattern has been
received. Once the data is in the LTC receive buffer, the LRI
bit is set to one in the SMPTEO register. If the LRIEN bit
(SMPTEO) is set to a one, an interrupt will be generated. The
interrupt is cleared when the SMPTEO register is read. The data
in the LTC receive buffer remains valid until the next LTC
frame has been completely received.

Indirect Register Access
Indirect registers are accessed via the SMPTE2 (address) and
SMPTE3 (data) registers. To read an indirect register, the
program must first write its address to SMPTE2. Then the data
is read from SMPTE3. Writing to an indirect register is similar.
First, the address is written to SMPTE2. Then the data is
written to SMPTE3.

LTC input data is available in the LTC Read registers after the
last LTC data bit has been received. It is not necessary to wait
for the LTC SYNC pattern to be complete. When LTC read data
is available the LRI bit in SMPTEO is set to one. IfLRIEN is
also set to one, an interrupt is generated. LRI and the interrupt
are cleared by reading SMPTEO. Data will remain valid until
the last LTC data bit of the next frame has been received.

In order to minimize the number of accesses required to read
or write a block of registers, an auto-increment function is
provided. If the MSB of SMPTE2 is written to a one with the
address, the address is incremented after each read or write
access to SMPTE3. For example, if one wants to read the LTC
Read registers, IRO to IR7, SMPTE2 is written to a 80h. Then
read SMPTE3 eight times. The first byte read is from IRO
followed by IRl, etc.

The SMPTEI register contains two status bits which indicate
whether LTC data is being received and if so which direction.
LTCLOCK is set to one when the LTC receiver has received a
valid LTC SYNC pattern and data is still coming in. CODEDIR indicates the direction of the LTC SYNC pattern. This
is useful to tell whether a tape with LTC is shuttling forwards
or backwards.

Programming

Interrupt Processing
Interrupts can be generated from five sources, LTC receiver,
LTC generator, video line count, timer and UART. The interrupt status of the first four interrupts, LRI, LXI, VLI and TMI
are in the SMPTEO register. After this register is read, all four
interrupts are cleared. It is, therefore, necessary to save the state
of the interrupt status and process all active interrupts.
The UART interrupt status is in the UARTO register. The
receive interrupt is cleared by reading the receive data register,
UART!. The transmit interrupt is cleared by writing data to the
transmit data register, U ART 1.

Generating LTC
The LTC generator transfers data from the LTC Write registers
(IR8 to IRF) to the output buffer when the LTC generator is
enabled; LTCEN is set to one. Data transfers for subsequent
LTC frames occur eight bit times before the end of the LTC
frame being output. Remember that a LTC frame ends with a
16 bit SYNC pattern. The LXI interrupt bit in SMPTEO is set
to one when LTC Write register data is transferred to the output
buffer.
A typical program for generating LTC output would first setup
the LTC control registers and the LTC bit time registers. Then
time code data would be written to the LTC Write register.
Once this setup is done the LTC output would be enabled by
setting LTCEN to a one. LTC output starts when a LTC SYNC
is received. The LTC SYNC source is selected as part of the
setup. While the LTC generator is waiting for SYNC, the data
in the LTC Write register is transferred to the output buffer.
When the transfer is complete the LXI status but is set to a one.
The data for the next LTC output frame can then be loaded.
The LXI status bit will be set to a one after the data transfer at
the end of the first LTC output frame. At this point the LTC
Write register is ready to receive data for a third LTC output
frame.

G-120

ICS2008A
Reading VITC
To read VITC code one must first setup IR30 thru IR33. The
VITC Read Line registers, IR30 and IR31, select the video line
from which VITC code is to be read. The MSB is the enable
for VITC reading. The Read Line field, bits 4 to 0, should be
programmed with the desired line number minus ten. So, if line
15 is desired, a 5 should be programmed in the Read Line field.
If the read line field is set to I Ph, this puts the VITC receiver
into a scan mode. In scan mode, the VITC receiver looks for a
valid time code starting at line 10 for VITC I or VITC Read
Line I for VITC2. The scan terminates when a valid time code
is received or the line count reads line 41.

Burn-in Window
The bum-in window can be placed anywhere on the video
display. The position of the upper left comer of the window is
selected by the values written in IR28 and IR29. IR28 controls
the horizontal position. Values from OOh to 7lh put the comer
in the first half of a video line (starting from the falling edge
of HSYNC). Values from 80h to Flh put the comer in the
second half of a video line. Any other values will not display
the window. Care should be taken not to choose values which
put the window in any part of the blanking area. IR29 controls
the vertical position. The value written here is the video line
number divided by 2.

IR32 selects the source and type of video. The GENLOCK
ENABLE bit must be set to a one, and the VTRES bit must be
set to a zero. The Video Interrupt Line register, IR33 should be
set to a line after all VITC read and write lines. This allows all
of the VITC receive and generate operations to be complete
before processing VITe.

IR3E controls the bum-in window character attributes. It controls the size, normal and large, and the color of the characters
and background.

The VLOCK bit in the SMPTE I register indicates whether the
ICS2008A is genlocked to the selected video source. Without
the VLOCK status set to one, no VITC read will occur.

UART
The UART is accessed via two directly addressable registers,
the command/status register and the data register. On reset, the
UART is not operational. The command register must be
initialized before the UART will function.

When VLOCK is set to one and the control registers are
properly initialized, VITC data are received a byte at a time
from the video signal and written to the VITC Read registers.
At the end of the VITC data frame the CRC byte is checked,
and the result reported in bit 5 ofIR30 and IR31. In addition
to the CRC check, if a full VITC data frame is not received,
the NOCODE bit, bit 6, is set to a one.
Generating VITC
Like reading VITC, IR2E, IR2F, IR32 and IR33 must be setup
in order to generate VITe. The VITC Write Line registers,
IR2E and IR2F, select the video line to which VITC code is to
be written. The MSB is the enable for VITC generation. The
Write Line field, bits 4 to 0, should be programmed with the
desired line number minus ten. So, if line 12 is desired, a 2
should be programmed in the Write Line field. IR32 selects the
source and type of video. The GENLOCK ENABLE bit must
be set to a one, and the VTRES bit must be set to a zero. The
Video Interrupt Line register, IR33 should be set to a line after
all VITC read and write lines. This allows all of the VITC
receive and generate operations to be complete before processing VITC.

IR2A to IR2D, are the registers which control the characters
displayed in the bum-in window.

Band rates are controlled in UARTO bits I and O. 31.25 kHz
supports MIDI communications. 9600 Hz and 38.4 kHz support most serial VTR transport controls.
The UART has a four deep FIFO for its receive buffer. This
allows for relaxed interrupt latency requirements. In the case
of MIDI bit rates, the receiver will not overflow even if the
interrupt response delay is lmsec.
The UART's transmitter has a buffer in front of the output shift
register so that a byte can be loaded and waiting for the output
shifter to be empty.

With the VITC generator setup properly, when the selected video
line starts, the VITC data in the VITC Write buffer, IR20 to IR27,
is output. The video line interrupt, VLI in SMPTEO, is provided
to allow ample processing time for VITC generation.

G-121

II

ICS2008A
Ordering Information
ICS2008AV
Example:

ICS XXXX M

TTL---T_

Package Type
V=PLCC

Device Type (consists of3 or 4 digit numbers)
Prefix
ICS,AV=Standard DeVIce; GSP=Gen]ock DeVIce

G·122

ICS2101

Integrated
Circuit
Systems, Inc.

•

Digitally Controlled Audio Mixer
Description

Features

The ICS2101 is a CMOS digitally controlled multi-channel
line-level stereo audio mixer for use in multimedia applications. High performance attenuators provide precision gain
control in -O.5dB increments. The ten input channels may be
used as mono inputs, pairs of stereo inputs, or any combination
of mono and stereo inputs appropriate for the application.
Stereo balance and mono panning functions are fully supported. The ICS2101 is compatible with the ISA industry
standard bus.

•
•
•
•

1L1R-

Data Bu s
00-06

~

L...t>

lOW

CS
RESET

A

Data
Register

Address
Register

..
......

Control
Registers

•
•
•
•
•

Five stereo input pairs
One stereo output pair
Precision gain control in -O.5dB steps
Separate attenuation and balance control for each input
pair
Mono input mode with panning capability
Master attenuation and balance control for output
Low noise, low distortion
ISA compatible
28-pin DIP or sorc package

Attenuator
Pair 1

-

I--

·
·
·

-

-

ML

~

MR

f--

Control Signals
5L--

Attenuator
Palr5

5R-

-

f--

Figure 1 - Block Diagram

IICS2101 Rev8093094

G-123

Attenuator
Master
Pair

f-I> Lout
f-I> Rout

ICS2101

1L
1R
CSVOOO
IOW00
01
02
03
04
05
06
VSSO
A

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

C;

..-

C\I
C/)

2

2R
2L
3R
3L
VSSA
VREF
LOUT
ROUT
4R
4L
VOOA
5R
5L
RESET

28-Pin DIP
28-Pin SOP
K-5, K-8

Pin Descriptions
PIN NUMBER
1,2,16,17,19,
20, 2S, 26, 27,28

PIN NAME
IL-SL,IR-SR

TYPE

DESCRIPTION

AI

Audio inputs (left and right) for attenuators 1 through S. An
external coupling capacitor should be connected to each input.

3

CS-

I

Chip select, active low.

S

IOW-

I

Input/output write, active low. Data is latched on the rising
edge.

6,7,8,9, 10,
II, 12

DO-D6

I

Data bus, active high.

14

A

I

Address/data select. Low input selects the data register, high
input selects the address register.

IS

RESET

-

21,22

I

Rout, Lout

23

VREF

AO

Resets all registers to OOH, active high.
Line level audio outputs.

P

Reference voltage of0.44VoOA. A 1000 pf capacitor should be
connected between VODA and VSSA.

P

Digital power.

4

VDDD

18

VDDA

P

Analog power.

13

VSSD

P

Digital ground.

24

VSSA

P

Analog ground.

-

I=Input; O=Output; P=Power; A=Analog

G-124

(I

ICS2101

Absolute Maximum Ratings
Storage Temperature. . . . . . . . ..
Voltage on any pin with
respect to ground. . . . . . . . . ..
Maximum VDDD .............
Power Dissipation. . . . . . . . . . ..

-65°C to 150°C
-0.3V to VDDD+0.3V
7V
IW

Standard Test Conditions
Operating Temperature Range.. O°C to 70°C
Power Supply Voltage ........ 4.75 to 5.25 Volts

DC Characteristics
VDDD = 5V ± 5%, VSSD = OV
SYMBOL
VlH

PARAMETER
Logical 1 Input Voltage

MIN

MAX

UNITS

2.4

TYP

VDDD

V

Logical a Input Voltage

a

0.8

IIL
f----

Input Leakage Current

1

lOR

Output Source Current

-1
-100

IOL

Output Sink Current

VREF

Internal Reference V

IADD

Analog Supply Current

IDDD

Digital Supply Current

VIL
~-

V
uA

O-'- - -

CE

CE

I
RD

~ D~, tid

r--

TCS

)>-!- - -

~i'" TC~

E
Ordering Information
ICS2102M
Example:

ICSXXXX M

~,...."",.
M=SOIC

Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - Prefix
L -_ _ _ _ _ _

ICS. AV=Standard Device; GSP=Genlock DeVIce

G-139

G·140

ICS2115

Integrated
Circuit
Systems, Inc.

WaveFrontTM Synthesizer
General Description

Features

The WaveFront Synthesizer, ICS2115, is an audio synthesis
chip which utilizes wavetable lookup to produce l6-bit, CD
quality sound. The internal memory management unit allows
both ROM, for standard samples, and low cost DRAM, for soft
loadable samples, to be connected directly to the ICS2115. The
WaveFront Synthesizer presents the audio output in l6-bit
linear form for conversion by a low cost CD-type DAC.

•

Capable of addressing up to 32 MB of wavetable ROM
and up to 16 MB of wavetable DRAM
Variable Polyphony Rates: 24 voices at 44.1 kHz through
32 voices at 33.8 kHz
Uses 16 bit linear, 8 bit linear, and 8 bit u-Law wavetable
data.
Serial output for a CD player-type DAC
Capable of using either a 68ECOOO (with the ICS2116) or
an ISA-based host for software control
Part of a complete design package that includes software
drivers for Windows and DOS

•
•
•
•
•

Applications
•
•
•

ISA based sound cards
Wavetable synthesizer daughter cards
External sound modules that connect to a PC's serial or
parallel port
Any system requiring a self contained unit that provides
high quality music synthesis of General MIDI sounds, in
a low cost design

•

Block Diagram r·------------------------------------------------------------------------------------------------------.---

RaMA<17:9>
f - - - - - - - - - i - _ + MA<10:0>

RAMREQ*--+--------_

Wave Table
Mel110lY
Interface

00<7:0>+-+--------_

f-------------~--~ RaMEN
f---------------~__. ~
f----------------r--~ ~CK

f - - - - - - - - - i - - + ~*
f - - - - - - - - - i - _ + CAS*<3:0>

f-----------1---. WE*

f-+---. SERDATA

SO<15:0>_--+~

Synthesis
Engine

SA<1:0>_-+~
IOR*--+~

1011*---+-+1
CS*---!--+I

DAC
Interface

Host
Interface

1--+---.
1--+--.

f-+---.

I.RClK
BCK
WDCLK

CSMM*--+~
DAC~---+~

r-----~-----------+--.

TC---+~

r-----~-----------+_-.

IOCH16*

RESET*---+~

r-----~-----------+_-.

SBHE*---+~

f------t------------+--.

MMIRQ
IRQ

ORQ

L-______j---------t-----------------~---.IOCHOOY

J

1 - - - - - - - + - + XlLO
X T U - + - - - - - - - - - + l ,.1 aOCKt--

i

L _____________________________________________________________________________________ . _____________________ j i
WaveFront IS a trademark of Integrated CircUit Systems, Inc
IICS2115fuIlRevB072694

G·141

G

ICS2115
Pin Configuration

MAS

121110J., 6" S" 3:2

o

1413 12 11 10 7971 77767}04

lWMAl..

MM
MAl

13
14

1

13
71
7.

lUJMA13
llOMAl2
ROMAI1

.....

10

RDMAIO

17

....
..
..
.

VIU
RAMA£K

RAMIUQ'
SIllS
BDl'
SIlI3
SIlIl
V8SP

ICS2115

SIll.
SD9

81)1

DD6

os

DDS
DO<

34 lS 36 37 31 39 40 41 42 43 +C 4S 46 47 .g 49 50 51 52

DD3

63
62

DD2
DOl

61

DDO
BCK

59

=

51
57

~l

DOT

67

WIXX

SIlRDATA

56

IRQ

os

IdMlRQ

sf'

lOCHl6·

~~~~§~~EE;~~~q~~~~~;~
84-Pin PLCC
K-10

NIC
NIC
ROMA14
ROMA13
ROMA12
ROMA11

NlC
NIC
MA5

MA4

MAl
MA2
MAl

R0MA10
R0MA9

MAO
VDOP

007
DDS
DDS
0D4

RAMACK

RAMREQ"
5015
5014
5013
5012

'"

NIC

ICS2115

VS5
VS5

003
002

001

000

5011

BCK

5010

WDCK

509
50S

LRCK

5EROATA
IRQ
MMIRQ

500

501

NIC

NlC
NlC

NIC

G-142

II

ICS2115

Pin Descriptions
PIN NUMBER

I
!

6-10,12-17
69-77
1-3,84
61-68
4
5
78
79
20
19
27-32,34-39
40-41
44
45
42
54
47
48
53
49
50
52
56
55
46
57
58
59
60
81
82
11,51
18,83
33,80
25,26,43

PIN NAME
MA
ROMA<17:9>
ICAS<3:0>
DD<7:0>
!RAS
/WE
ROMEN
BYTE
!RAMREQ
RAMACK
'SD<15:0>
SA<1:0>
IIOR
IIOW
ISBHE
IIOCSI6
ICS
ICSMM
DRQ
IDACK
TC
IOCHRDY
IRQ
MMIRQ
!RESET
SERDATA
LRCK
WDCK
BCK
XTLO
XTLI
VDD
VDDP
VSS
VSSP

TYPE
TPUP2
0
02
B
02
TPUP
0
0
IPUP
0
B
I
I
I
IPUP
SINK
I
I
SOURCE
I
I
SINK
B2
SOURCE
IPUPS
0
0
0
0
o (special)
I (special)
PWR
PWR
GND
GND

DESCRIPTION
Wavetable Muxed Address Bus
Wavetable ROM Address
Wavetable DRAM Column Address Strobe
Wavetable Data Bus
Wavetable DRAM Row Address Strobe
Wavetable DRAM Write Enable
Wavetable ROM Enable/Byte Enable
Wavetable ROM Byte Mode
Wavetable DRAM cycle request
Wavetable DRAM cycle acknowledge
Host Interface Data Bus
Host Interface Address Bus
Host Interface Read Strobe (Active Low)
Host Interface Write Strobe (Active Low)
Host Interface Sixteen Bit Hardware Enable
Host Interface I/O Channel Sixteen Wide
Host Interface Synthesizer Chip Enable
Host Interface Chip Select for MIDI Interface Emulation
Host Interface DMA Request
Host Interface DMA Acknowledge
Host Interface DMA Terminal Count
Host Interface I/O Channel Ready
Host Interface Synthesizer IRQ
Host Interface MIDI IRQ
Hardware Reset (Active Low)
Serial Data Output
LeftlRight Clock
Word Clock
Bit Clock
Crystal or N/C
i Crystal or Clock Input
IPower for chip core
Power for pad ring
Ground for chip core
Ground for pad ring

G-143

II

ICS2115
Pin Type Descriptions
PIN
TYPE

~--.

I
IPUP
IPUPS
0
02
B
B2
TPUP
TPUP2
SINK
SOURCE
PWR
GND

INPUT
TYPE

DRIVE

PULLUP
R

PULLDOWNR

nla

none
none
none
standard
high
standard
standard
standard
medium

none
yes
yes
none
none
none
none
yes
yes

none
none
none
none
none
none
yes
none
none

nla
nla
nla
nla

standard
standard
nla
nla

yes
none
none
none

none
yes
none
none

TTL
TTL
SCHMIDT
I
i
nla
nla
TTL
SCHMIDT
nla
I

I

I

NOTES

I

TTL Input
TTL Input with pull-up
SCHMIDT Input with pull-up
Output
High Drive Output (200pf max load)
TTL Bi-directional
Drive only with pull-up
Tristate with pull-up
Tristate (medium drive) with pull-up
(l2SpF max load)
Drive low only with pull-up
Drive high only with pull-down
Power terminal
Ground terminal

Absolute Maximum Ratings
Supply Voltage ..............................
Logic inputs ................................
Ambient operating temp .......................
Storage temperature ..........................

-O.SV to 7.0V
-O.SV to VDD + O.SV
ODC to 70 DC
-6S D C to ISODC

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

G·144

II

ICS2115

DC Electrical Characteristics
Vee = 5.0V ± 10%; GND = OV; TA = O°C to 70°C
PARAMETER
Supply Voltage
TTL Input Voltage Low
TTL Input Voltage High
Schmidt Input Voltage Low
Schmidt Input Voltage High
XTLI Input Voltage Low
XTLI In~ut Voltage High
Output Low Current
Standard Drive
Output High Current
Standard Drive
Output Low Current
Medium Drive
Output High Current
Medium Drive
Output Low Current
High Drive
Output High Current
High Drive
Input Leakage Current
Standard Inputs
pull-up Current
pull-down Current
XTLI Input!
Output Capacitance

SYMBOL

TEST CONDITIONS

VDD
VIL
VIH
VILS
VIHS
VILX
VIHX
IOL
IOH

i

MIN

TYP

MAX

UNITS

4.75
-0.30
2.20
-0.30
3.00
-0.30

5.00

5.25
0.80
VDD+0.30
1.50
VDD+0.30
1.50
VDD+0.30

V
V
V
V
V
V
V
rnA

3.50
4.0

VOL=O.4V

i

6.0
-6.0

VOH=2.8V

1
!

-4.0

rnA

I
IOL2

6.0

VOH=O.4V

9.0

rnA

I
IOH2

-6.0

-9.0

VOH=2.8V

rnA

:
IOL3
IOH3
lIN
Ipup
IPDN
CXTL

9.0

VOH=O.4V

I
I

VOH=2.8V

12.0

rnA
I

-12.0

VSS < VIN < VDD

-1.0

VIN=VSS
VIN=VDD

15.0
50.0

I

30.0
90.0
20.0

I

Note: All pins have a maximum capacitive load of 50pf unless noted otherwise.

G-145

-9.0

rnA

1.0

uA

50.0
150.0

uA
uA
pf

I

II

II

ICS2115
AC Electrical Characteristics
Please reference the timing diagram titled Host Interface Timing, below.

HOST INTERFACE AC TIMING PARAMETERS
PARAMETER
Address setup to command

SYMBOL

FROM

TO

MIN

MAX

UNITS

tAS
tcs

3

1
I

10

nS

nS
nS

6
2
7

10
100

-

0

50

0
50

50

14

8
2

2
1

15
12

10
0

tDHR

2

tDAS
tDAH

16
2

13
1

0
20

tTS
tTH
tTW

18
2
18

17
2
19
19

50
25

-

n/a

-

nS
nS

20

-

nS

Chip select setup to command
Address hold from command

tAH

Chip select hold from command
Command width

tCH
tcw

Address valid to IIOCSI6 delay
IIOCS16 hold from address invalid

tAID
tIH

Write data setup
Write data hold
Read data delay (ready access)

tDS
tDHW
tDD

Read data hold
IDACK setup to command
IDACK hold after command
TC setup to command
TC hold after command
TC width

5
2
2
1
3,5
4,6

G·146

4

10
10

60
20

nS
nS
nS
ns

nS
nS
nS
nS
nS
nS

ICS2115
Timing Diagrams
SA,SBHE"

CS",CSMM"

lOW, lOW"

IOCS16"

IOCHRDY

SD (Read)

SD(Wnte)

DACK"

18

TC

19

Host Interface Timing

II
24

•0

32

.

BCK
SERDATA~-+______________~~~~-L~~~~-L~~~______

WDCK
LRCK
Notes:
- BCK is XTLI frequency divided by four
- 'Extra' cycles are appended as needed for the number of voices
- BCK continues to run for all 'extra' cycles

DAC Output Timing
G·147

II

ICS2115

XTLU2

lS SLrlS1S ~

w--u--u--uuu- SL

RAS*

\.

-

--

T\
T\

MA<10:0>

-

J

WE"

-

CASn"
CAS3"

/

'--

/

'--

DO (out)
ROMA<17:9>
ROMEN

BYTE

-

(ON.Y ONE AC'nVEJ

Refresh

~

'---

'---

'---

Synth 1

Synth2

8 Bitlu-Law Access of Wavetable ROM

XTUI2
RAS*
CASn*
CAS3*
MA<10:0>
WE*

DO (out)
ROMA
ROMEN

BYTE

r-------t--------..
r------t--'L~BYTE

Refresh

IIGHBYTE

r - - - - - _____ _

r----I------,.

Synth 1

_BYTE

Synth2

16 Bit Access of Wavetable ROM

G-l48

BYTE

ICS2115

XTLII2

ru- w-u--uu-w-u--uu- Jl.JL.JlS ~ W1~

RAS'
CASn'
CAS3'
MA<10:0>

iii-

f

! ~

V\
f.-.- V\

i-

h

l\V\L

HIGHIt&'EOANCE

f-!

1>,

HIGHI~

WE

DO (out)
ROMA<17:0>

-

ROMEN

-

BYTE

iRefresh

Synth 1

Utility

Synth2

8 Bltlu-Law Access of Wavetable DRAM

SYNTH 16 Bit DRAM Access

II

XTLl/2
RAS'
CASn'
CAS3'
MA<10:0>

WE

DO (out)
ROMA<17:0>
ROMEN

BYTE

Refresh

Synth 1

Utility

Synth 2

16 Bit Access of Wavetable DRAM

G-149

ICS2115
ICSMM

Miscellaneous Pins
VDD, VDDP
These are the chip power supply pins. VDD pins power the core
logic, while VDDP pins power the pad ring. This arrangement
helps prevent switching spikes due to output transitions from
disturbing the internal operation of the chip. These pins MUST
be at the same potential externally.

VSS, VSSP
These are the chip ground pins. VSS pins ground the core logic,
while VSSP pins ground the pad ring. This arrangement helps
prevent switching spikes due to output transitions from disturbing the internal operation of the chip. These pins MUST be at
the same potential externally.

XTLI, XTLO
These pins comprise a self-contained oscillator circuit for
primary chip clock generation. No external components (other
than the crystal itself) are required for fundamental mode
operation. There is approximately 20pF of capacitance at each
pin, and a DC bias feedback between the pins for startup and
biasing.The standard crystal frequency is 33.868800 MHz (for
24 oscillators at 44.1 kHz or 32 oscillators at 33.8 kHz). Due
to the expense of fundamental mode crystals of this frequency,
the oscillator can be operated in 3rd overtone mode with the
addition to the XTLO pin of a series network to ground of a
1.0H inductor and a O.OOIF capacitor. In this case, the crystal
fundamental frequency will be 11.2896 MHz.
When an external clock is supplied, XTLO should be left
floating. XTLI should be connected to the clock source via a
series capacitor (O.OOluF is recommended). Duty factor is not
critical, since the clock is internally divided by two.

This input pin selects read/write access to the Media Master
and MIDI interface emulation registers, as selected by
SAd :0>. This signal must be stable before, during, and after
fIOR or flOW strobes.

SA
These address input pins select one of four direct mapped
registers as determined by the fCS and fCSMM pins. These
signals must be stable before, during, and after fIOR or flOW
strobes.

ISBHE
This input pin determines the access width for even addresses,
and is ignored for odd addresses. It should be connected directly to the ISA bus for a l6-bit card. For 8-bit cards, it should
be tied high.

lIOCS16
This output pin indicates to the host that the current address is
accessible as a word-wide (sixteen bit) data entity. It is based
on the current value of the indirect register address, SA,
and fCS selecting a word-wide internal register. Under these
conditions, fIOCS 16 drives low; otherwise, it is a resistive high.
This output pin is unused with systems that contain the
ICS2116.IIOCSI6 requires an external pull-up of 3.3K.

SD
This is the bi-directional data bus used for all register data
transfers.

lIOR
This input pin is used to read registers when low. SA< 1:0>, fCS,
fCSMM, and fSBHE must be stable before, during, and after
the active low pulse on lIaR.

Host Interface

lIOW

The ICS2115 can interface with the ISA bus or directly with
the ICS2116. For more information, refer to the WaveFront
Application Notes. (Please reference the timing diagram titled
Host lnteiface Timing, above.)

This input pin is used to write registers when low. SAd :0>,
fCS, fCSMM, and fSBHE must be stable before, during, and

after the active low pulse on flOW. SDd5:0> must be stable
before, during, and after the trailing (rising) edge of IIOW.

ICS

IOCHRDY

This input pin selects read/write access to the internal indirect
registers, as selected by SA. This signal must be stable
before, during, and after /lOR or flOW strobes.

This output pin is normally in a resistive pull-Up state. During
lIaR or IIOWlow times, this pin can become active (drive low)
to indicate to the host that the requested data transfer is not
ready, and that lIaR or flOW should be held (stretched) until
ready is signaled by IOCHRDY deactivating (resistive high).
IOCHRDY requires an external pull-up of 3.3K.

G·150

II

ICS2115

IDACK
This input, when low, identifies the current 10 operation as a
DMA acknowledge operation, The current 10 operation will
interact with the DMA control logic in the ICS2115 as programmed, and cause DRQ to be de-asserted. This input must
be held before, during, and after the 10 command signal (lIaR
or flOW low).

TC
This input (along with IDACK being low) signals that the
current DMAoperation is the last transfer, and that the ICS2115
should shutdown its DMA logic after the current transfer is
complete.

DAC Output
The ICS2115 is designed to directly interface with consumer CD player type digital to analog converters. The
interface is a 48 clock, MSB first, left/right multiplexed
data stream. Depending on the number of oscillators enabled, there will be additional idle clocks generated after
the data is output. (Please reference the timing diagram
titled DAC Output Timing, above.)
Some DACs that may be used are:
•
•

Phillips TDA1545
NEC UDP6376

DRQ
This output pin is normally in a resistive low state. When DMA
operation has been programmed and the proper status exists,
the DRQ pin will drive high to indicate that the ICS2115 is
ready to accept a DMA data transfer. Upon receipt of a low on
the IDACK input, DRQ will return to the resistive low state.
When the ICS2115 is ready to continue DMA transfers, DRQ
will again be asserted. This sequence repeats until DMA is
terminated by either TC or a register write. DRQ requires an
external pull-down of I K.

MMIRQ
This output is normally in a resistive low state. Whenever an
active Media Master interrupt occurs, it will drive high. When
the interrupt condition is cleared, the pin returns to a resistive
low state. MMIRQ requires an external pull-down of IK.

IRQ
This output is normally in a resistive low state. Whenever an
active internal interrupt occurs, it will drive high. When the
interrupt condition is cleared, the pin returns to a resistive low
state. IRQ requires an external pull-down of lK.

IRESET
This input is the active low hardware reset for the ICS2115.

BCK
This output pin is the bit clock for the DAC. The frequency
of BCK is the frequency of XTLI divided by four. It
always runs, even when the system has not initialized
itself. The other DAC interface signals change on the
falling edge of BCK, and are stable on the rising edge of
BCK.

SERDATA
This output is the accumulated data of all ICS2115 oscillators, presented as signed binary two's complement data,
MSB first. The internal 16 bit data is sign-extended to 24
bits, and presented left then right.

LRCK
LRCK indicates the stereo channel of the data just shifted
out. It will transition high to low after bit 0 of the left data
has been output, and transition low to high after bit 0 of
the right data has been output.

WDCK
WDCK indicates the framing of the data being shifted out.
It will transition low to high between bits 12 and 11 of
both the left and right data words. It transitions high to low
after bit 0 of both the left and right data words.

G-151

E1

II

ICS2115
Wavetable Memory Interface

lRAS

(Please reference the timing diagrams that show the wavetable
memory access cycles, above.) The ICS2115 is designed to
directly interface to the following memory components:

This output connects to the /RAS pin of all wavetable DRAM
chips IRAS is generated for all DRAM access and refresh
cycles, and remains high for all ROM cycles so that the ICAS
pins can be used as ROM addresses.

•

/WE

dynamic RAM meeting the following parameters:
80nS access time
Fast Page mode operations
CAS-before-RAS auto-refresh
256K (9 addresses) to 4M (11 addresses) by I or 4
(configured as byte wide)

•
•
•
•

SIMM's with an access time better than 80ns can also be used.
•

ROM meeting the following parameters:
•
150nS address access time
•
70nS output enable access times
•
byte-wide output

This tristate output connects to the /WE pin of all wavetable
DRAM. It is normally in a driven (or resistive) high state. It
toggles low only for DMA write cycles.

ROMA<17:9>
This bus provides addresses for ROM based oscillators. During
refresh and DRAM cycles, these pins are driven high. The
MA and CAS<3:0> multiplex to provide the other
address bits for the wavetable ROM. The table below shows
the exact relation.

The ICS2122-00I, ICS2124-00I and ICS2I24-002 comprise
the ICS 2 MB and 4 MB patch sets respectively. Users of the
WaveFront chipset can either buy ROMs directly from ICS or
purchase the mask and produce the wavetable ROMs independently.
Pin descriptions follow.

DD<7:0>
This bus is a bi-directional data bus for the wavetable data. It
functions as an input under all operations except for DMA
writes to DRAM. This bus connects directly to the data pins of
all wavetable DRAM and ROM.

MA<10:0>
This output bus drives addresses to both DRAM and ROM
wavetable memory.

ICAS<3:0>
These outputs function as both ICAS inputs to up to four banks
of DRAM and as addresses to ROM. For a DRAM cycle, only
one of these four outputs will toggle active (low) at a time. For
a refresh cycle, they all toggle low to refresh all DRAM
simultaneously.

G-152

Wavetable ROM address

ICS2115 Signal

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AlO
All
AI2
A13
AI4
AI5
AI6
AI7
AI8
AI9
A20
A2I
A22
A23

MA
MA<1>
MA<2>
MA<3>
MA<4>
MA<5>
MA<6>
MA<7>
MA<8>
RA<9>
RA<10>
RA
RA<12>
RA<13>
RA<14>
RA<15>
RA<16>
RA<17>

ICAS<3>
MA<9>
MA<10>

ICAS
ICAS
ICAS<2>

II

ICS2115

BYTE
BYTE functions as Low Byte fOE for the low byte ROM of a
l6-bit ROM pair. When using the ICS2l22-001, this connects
to the output enable on the ROM. When using the 4 MB patch
set, BYTE connects to the fOE on the ICS2 I 24-001.

6850 Mode Control (Emulation Base + 0) (Write Only)
The host can access this MIDI control register by writing to this
address. The control register is mapped as follows.

I I I I I I 1[hL

ROMEN

II

ROMEN functions as High Byte fOE for the high byte ROM
of a 16-bit ROM pair. For systems using the ICS2122-001, this
pin is unused. When using the 4 MB patch set, ROMEN
connects to the fOE on the ICS2124-002.

lRAMREQ
This input pin is used to request an external memory cycle. Its
function is unused in the present design.IRAMREQ should be
tied high.

RAMACK
This output pin provides acknowledgment of an external memory cycle. It is unused in the current design.

MPU-401/6850 Emulation Registers
These 4 registers will be mapped at an offset determined by the
fCSMM input. The WaveFront Synthesizer only decodes the
least significant 2 address bits. For identification purposes, this
document refers to these registers as Emulation Base + 0
through Emulation Base + 3.

MIDI Emulation Control/Status Register
The MIDI Control Status register can be configured as
either a 6850 compatible or an MPU-401 compatible
UART. The WaveFront Operating System writes to the IndEmulMode Register to indicate the mode of emulation.

I I I I I

,

~~~et (11-reset, else soft)
Transmit Interrupt Control
Receive Interrupt Enable

MIDI (6850) Control Register

1:0 - Reset - Resets the MIDI Port
II = Reset (Resets Receive Interrupt and Receive
Interrupt Enable)
00,01 and 10 = No Reset
4:2 - Soft - Software controlled functions
6:5 - Transmit Buffer Empty Interrupt Control
01 = Interrupts are enabled
00, 10 and II = Interrupts disabled
7: - Receive Buffer Full Interrupt Enable
I = Interrupts enabled
o= Interrupts disabled
6850 Mode Status (Emulation Base + 0) (Read Only)
The host can access this MIDI status register by reading this
address. The status register is mapped as follows.

I I I I I I I]J

Receive Buffer Full (RBF)
Transmit Buffer Empty (TBE)
'-----'----'---'---'----- Soft

II I I I I
.

L:=

' - - - - - - - - - - - Interrupt Request (IRQ)

MIDI (6850) Status Register

0: - Receive Buffer Full
1 =full
0= empty
I: - Transmit Buffer Empty
I = empty
0= full
6:2 - Soft
7: - Interrupt Request
I = Interrupt pending
o = Interrupt not pending

G-153

E1

ICS2115
MPU-401 Mode Control (Emulation Base + 1) (Write Only)
The host can access this MIDI control register by writing to this
address. The control register mapping is software dependent.

I I II II I I

II II III I

80ft

MIDI (MPU-401) Control Register

7:0 - Soft - Software controlled functions

MPU-401 Mode Status (Emulation Base + 1) (Read Only)
The host can access this MIDI status register by reading this
address. The status register is mapped as follows.

I II I I I II I I I
II
. 1

_ _ _ _

L -_ _ _ _ _ _ _ _

Synthesizer Registers
In the ICS2115, the Synthesis and General Purpose registers
are accessed indirectly via the Indirect 110 Registers. These 4
registers will be mapped at an offset determined by the /CS
input. For identification, this document refers to these registers
as Synthesizer Base + 0 through Synthesizer Base + 3.
Synthesizer Base + 0 R
IRQ/Status
Synthesizer Base + 1 RIW Register Address
Synthesizer Base + 2 RIW Data Low ByteIWord
Synthesizer Base + 3 RIW Data High BytelByte

Interrupt status (Synthesizer Base + 0) Read Only

I I I I I I I I I

IL=

80ft
Transmit Buffer Full (TBF)
Receive Buffer Empty (RBE)

MIDI (MPU-401) Status Register

5:0 - Soft
6: - Transmit Buffer Full
1 = full
0= empty
7: - Receive Buffer Empty
1 = empty
0= full

MIDI Emulation Data Register
This register is the MIDI data port for writing and reading MIDI data. The host can transfer MIDI data between itself and the WaveFront Operating System via
this register.

6850 Mode Data (Emulation Base + 1) (ReacJIWrite)
Eight bit data.

MPU-401 Mode Data (Emulation Base + 0) (Read/Write)
Eight Bit data

Registers Emulation Base + 2 and
Emulation Base + 3
These registers are reserved when the ICS2115 is in the
host configuration

Timer Interrupt
Oscillator Interrupt
DMA Interrupt
Emulation Interrupt
Reserved
Busy
Interrupt

Interrupt Status Register

Note: Reading this Register does NOT clear any of the bits.
0: - Timer Interrupt
This indicates that one or both of the 2 internal
WaveFront timers has expired.
I: - Oscillator Interrupt
When this interrupt occurs the WaveFront Operating
Systems reads the Oscillator Interrupt Address register
to determine the oscillator that needs servicing.
2: - DMA Interrupt
The DMA channel has completed a transfer.
3: - Emulation Interrupt
When this occurs it indicates that a read or write has
occurred with one of the High Level Emulation Control or Data registers
4: - Reserved
5: - Reserved
6: - Busy
Status bit which indicates that the previous write operation to an internal register has not yet completed and
thus a new write should not be initiated.
7: - Interrupt
This is the Operating System interrupt from the
ICS2115.

G-154

II

ICS2115

Indirect Register Access
There are two types of indirect registers in the chips; Synthesizer and General Purpose. Due to the timing restrictions on
access to the internal indirect registers, access to the two types
of registers are handled differently. In ICS2115, register addresses $00 through $3F are Synthesizer registers (for both read
and write), and all others are for General Purpose use.
General Purpose registers are immediately available for access.
Synthesizer registers are internally buffered so that the chip
hardware completes the data transfers at the required times.
The WaveFront Operating System can read and write internal
Synthesizer registers using 8 or 16 bit reads and writes. Access
is accomplished via the 3 indirect registers:
Indirect Address (Synthesizer Base + 1)
This will contain the address of the internal Synthesizer
register.
Indirect Data Lo (Synthesizer Base + 2)
Contains the Least significant 8 bits of the data to be
written to or read from the internal Synthesizer register
addressed by the Indirect Address register.
Indirect Data Hi (Synthesizer Base + 3)
Contains the Most significant 8 bits of the data to be
written to or read from the internal Synthesizer register
addressed by the Indirect Address register.

G·155

ICS2115
Register Map
The following list includes all the internal registers of the ICS2115 chip and their associated "indirect" addresses. All registers
can be read and written unless otherwise indicated.

·ll

Synthesizer Register Definitions
Indirect
Address

c-------

,

RdlWr

I

Size

00

RIW

8

Mnemonic

I

Description

OscConf

Oscillator Configuration

01

RIW

16

OscFC

Wavesample Frequency (6 Integer, 9 Fraction)

02

RIW

16

OscStrtH

Wavesample Loop Start Address (16 Integer)

03

RIW

8

OscStrtL

Waves ample Loop Start Address (4 Integer, 4 Fraction)

04

RIW

16

OscEndH

Wavesample Loop End Address (16 Integer)

05

RIW

8

OscEndL

Wavesample Loop End Address (4 Integer, 4 Fraction)

06

RIW

8

VIncr

Volume Increment

07

RIW

8

VStart

Volume Start Value

08

RIW

8

VEnd

Volume End Value

09

RIW

16

VolAcc

Volume Accumulator

OA

RIW

16

OscAccH

Wavesample Address (16 Integer)

OB

RIW

16

OscAccL

OC

RIW

8

OscPan

Pan Value (Note - 10 Bits on 2210)

OD

RIW

8

VCtI

Volume Envelope Control

OE

RIW

8

ActiveOsc

Active Voices

OF

Rd

8

IRQV

Interrupt Source/Oscillator
Oscillator Control

[--.

I

Wavesample Address (4 Integer, 9 Fraction)

- -- - - - -

10

RIW

8

OscCti

11

RIW

8

OscSAddr

Static Address Bits 27-20

12

RIW

8

VMode

Reserved (Write 0)

X

RESERVED

Do Not Access

13-3F

-

G-156

II

ICS2115
General Purpose Register Definitions

Indirect
Address
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58-7F

RdIWr
Wr
Wr
Wr
RfW
Wr
Wr
Wr
RIW
Rd
Rd
RIW
Rd
RIW
RIW

Size

8
8
8
8
8
8
8
8
8
16
8
8
8
8

-

X

RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW

8
8
8
8
8
8
8
8
8

-

X

Mnemonic
Timerl
Timer2
TimerlPreS
Tuner2PreS S
DMAddrLo
DMAddrMd
DMAddrHi/Data
DMACS
AccMonS
AccMonData
DOCIntCS
IntOscAddr
MemCfg Rev
SysCtrl
RESERVED
OscNumber
IndMIDIData
IndMIDICS
IndHostData
IndHostCS
IndMIDIIntC
IndHostIntC
IndIntStatus
IndEmulMode
RESERVED

Description
Timer Preset 1
Timer Preset 2
Prescaler 1
Prescaler 2 (wr) and Timer Status (Rd)
DMA Start Address Low [11:4]
DMA Start Address Medium [19:12]
DMA Start Address high [21:20]
DMA Control/Status
Accumulator Monitor Status
Accumulator Monitor Data
DOC Interrupt (Read) Int Enable (Write)
Address of interrupting Oscillator
Memory Config. (WR) & Chip Rev. # (Rd)
System Control
Do Not Access
Oscillator Address being programmed
MIDI Data Register
MIDI Control/Status Register
Host Data Register
Host Control/Status Register
MIDI Emulation interrupt Control
Host Emulation Interrupt Control
HostIMIDI Emulation Int. Status (Rd)
Emulation Mode
Do Not Access

Ordering Information
ICS2115V or

ICS2115Y

Example:

iCSXXXX M

TL-____

Package Type
V=PLCC

Y=TQFP

'--_ _ _ _ _ _ Device Type (consists of 3 or 4 digit numbers)
'--_ _ _ _ _ _ _ _ Prti"1X
ICS, AV =Standard Device; GSP=Genlock Device

G-157

G·158

ICS2115

Integrated
Circuit
Systems, Inc.

•

Application Information

Application Note for WaveFront Lite™
A Host Assisted Wavetable Synthesizer
General Description

Features

Applications for wavetable synthesizers come in many shapes
and sizes. For low cost systems that reside on a ISA card or
daughter card, the designer can remove significant expense by
controlling the wavetable synthesizer using the host CPU. This
configuration is easily implemented with the WaveFront Synthesizer, ICS2115. The purpose of this application note is to
provide full descriptions of the WaveFront Lite design. This
configuration uses an ICS2115 with either the ICS2122 (2 MB
patch set) or the ICS2125 (512 KB patch set).

•
•
•
•
•

Supplied with both Windows 3.1 and DOS drivers
MPU-401 compatible
MT-32 compatible
Complete General MIDI sound set
Reduces part count and expense of conventional designs

Applications
•
•
•

ISA-based sound cards
Wavetable daughter card upgrades
Motherboard wavetable systems

Block Diagram

WaveFront
Sounds
2MBor
512 KB

t
MPU-401 ISA
Interface

-

"'"

.

ICS2115
WaveFront
Synthesizer

f----+-

16 Bit
Stereo DAC

Stereo

,. Audio

-.lo.

Output

WaveFront lite IS a trademark of Integrated CirCUit Systems, Inc

I2115ApNtRevA101294
G-lS9

II

WaveFront Lite Application Note

Suggested Circuit Design
The following sections detail the specific implementations of the WaveFront Lite design.

ISA Interface-Inputs and Data bus
Please reference Figure I.

Generating Chip Selects and Enable Data Bus Buffers
Signals CS*. CSMM* and GATE* can easily be generated by a 16V8 PAL device. Inputs PAl and PAO allows the user to
select four different port addresses using two jumpers. CS* designates the location of the synthesizer registers. CSMM*
selects the location for the MPU-401 registers. Together. the ICS2115 requires eight address locations. Adding AEN to the
decode prevents the system from reacting to DMA operations. The equations for the PAL device follow:
/* Intermediate variable for address 210H */
ADDRO=SA9 & !SA8 & !SA7 & !SA6 & !SA5 & SA4 & !SA3 & !PAI & !PAO;
/* Intermediate variable for address 230H */
ADDRl=SA9 !SA8 & !SA7 & !SA6 & SA5 & SA4 & !SA3 & !PAI & PAO;
/* Intermediate variable for address 260H */
ADDR2=SA9 & !SA8 & !SA7 & SA6 & SA5 & !SA4 & !SA3 & PAl & !PAO;
/* Intermediate variable for address 330H */
ADDR3=SA9 & SA8 & !SA7 & !SA6 & SA5 & SA4 & !SA3 & PA I & PAO;
/** Logic Equations **/
CSn=!((ADDRO # ADDRI # ADDR2 # ADDR3) & !AEN & SA2);
CSMMn=!((ADDRO # ADDRI # ADDR2 # ADDR3) & !AEN & !SA2);
GATEn=!((ADDRO # ADDRI # ADDR2 # ADDR3) & !AEN);

SBHE*
For eight bit operation, tie SBHE* pin high on the ICS2115.

SD<7,O>
Since the ICS2115 is only capable of driving a maximum of 4mA on each data pin, a bus buffer is required. A 74LS245 is
a suitable candidate.

RESET*
The ICS2l15 RESET* input is active low compared with the ISA signal that is active high.

RAMREQ*
This input pin is used to request an external memory cycle. Its function is unused in the present design. RAMREQ* should
be tied high.

DACK*& TC
These pins are used to transfer sample data to and from the wavetable DRAM. For designs that do not support this capabilitiy,
DACK* should be tied high and TC should be tied low. For designs that use wavetable RAM, contact ICS for more
information.

G·160

II

Q)

o

Z

r::
o

C'II

CJ

Q.
Q.

«

Q)

-...

. .J

r::

J1

*33

~

~

%rtr-

'>9~
T,-

o

Ffr-

LL

~

Q)

>

C'II

3:

r.-

#~
~

~

-'ttti-

'fr~
fr-

..-

fj~

'>9~
T,-

%t=

GND

·IOCHCK

RESOOV

D7

+SV
I11Q9
-SV
DREQ2
-12V

D6
OS
04

-WIS
+12V

GNO
-SMEMW

-:MM.
-ICIN
-lOll
-DAC1(3
DREQ3
-DACI

'"

3:

R£SOO\I

+5V

-'>v
OREQ2

·12V
.(HIS

+12V
GND
.Q.EMW
.Q.EOMl

D5~

Al.

OREQ3
-OAO, MA<10,0>, and CAS3 outputs to form the ROM
address bus. On the wavetable ROM, ICS2l22, the OE* pin connects directly to the ROMEN* on the ICS2115, and the CE*
should be tied low. With the BYTE* pin tied low, the ROM is in 2 MB x 8 mode. Therefore, the D<7,0> pins on the ICS2115,
and the D<15,0> pins are unused. Figure 5 shows this graphically.

~

-#-

~
~
~
~

4~
Taijit¥it-

5015
5014
5013
5012
5011
5010
SD9

MAlO
MA9

SD8

MA3
MA2

507
SD6

SD5

MAS

MA7
MA6
MAS
MA4

MAl

MA.O

1t=

S04
503
502
501

CAS2
CASl

SOD

CASO

~
-"--

SAl
SAO

RAS
WE

~
~

lOR

-¥.-<:
~

cs

CSMM

~
~

DACK
TC

007
006
005
004
003
002
001
DOD

~

RESET

~

SBHE

~

RAMREQ

f2--

lOW

CAS3

ROMA17
ROMA16
ROMA15
ROMA14
ROMA13
ROMA12
ROMAll
ROMAI0
ROMA9
IlOMEN

lRCI(

WDCK

~

BCK
X1l1
X1l0

RA20
RA19
RA8
RA7
RM
RAS
RA4
RA3
RA2
RAl
RAO

3

RA18

~

~

~
~
68

7

RA2
RAl

8
9
10
11

AAO

31

RAJ

65
64
63
62
61

77
76
75
74
73
72
71
70
69

RA17
RA16
RA15
RA14
AA13
RA12
RAll
RAI0
RAQ

66

RA5
RA4

RA8

007
DD6
005
004
003
002
001
DOD

67

RA7
AM

43
2
3
34
35
36
37
38
39
40
41
42
4
5
6

RA20
RA19
RA18
RA17
RA16
RA15
RA14
RA13
RA12
RAll
RAI0
RA9

NC

~

014
013
012
011
010

*

NC
A19
A18
A17
A16
A15
A14
A13
A12
All
AI0
A9
AS
A7

D9
08
07
D6

os

04
03
02
01
DO

A6
AS

A4
A3
A2

CE

OE

Al

AD
BYTE

ORQ
1OCH16
MMIRQ
IRQ
IOCHADY

~
~

*
+

28
26
24
21
19
17
15

007
006
005
004
003
002
001
DOD

12
14
33

OllilA-l

~
ICS2122M'(x)1

78

8m ~

RAMACK

SERDATA

~

6
7
8
9
10
12
13
14
15
16
17

~

--¥.-

+
~
+
~
56

~

1CS2115V

Figure 5: 2 MB Wavetable Memory Interface

G·167

II

WaveFront Lite Application Note

512 KB Sound Set
To accommodate the ROM memory space, the ICS2115 uses its RA<17,1O>, MA<8,O>, and CAS3 outputs to form the ROM
address bus. On the wavetable ROM, ICS2125, the OE* pin connects directly to the ROMEN* on the ICS2115, and the CE*
should be tied low. Figure 6 shows this graphically.

U2
MAlO
MA9
MAS
MA7
MA6

MAS
MA4
MA3

MA2
MAl
MAO
CAS3
CAS2
CASl
CASO
RAS

WE
007
006
D05
004
DD3
002
DOl
DDO
ROMA17
ROMA16
ROMA15
ROMA14
ROMA13
ROMA12
ROMAll

R0MA10
ROMA9
ROMEN
BYTE
RAMACK
SERDATA
lRCK
WDCK
BCK
OOQ
IOCH16
MMIRQ
IRQ
IOCHRDV

~

+8
9
10
12
13
14
15
16
17

RAB
RA7
RA6
RAS
RA4
RA3
RA2
RAl
RAO

3

RA18

RA18
RA17
RA16
RA15
RA14
RA13

RA12
RAll
RA10
RA9
RA8
RA7
RA6
RAS
RA4
RAJ
RA2
RAl
RAO

~

~
~
68
67
66
65
64
63
62
61

DD7
006
DD5
DD4
DD3
DD2
DDl
000

77

RAl7
RA16
RA15
RA14
RA13
RA12

76
75
74

73
72
71
70
69

-h30
2
3
29
28
4
25
23
26
27
5
6
7
8
9
10
11

12
24
22

~

N.C.
A18
A17
A16
A15
AU
A13
A12
All
A10
A9
A8
A7
A6
AS

A4
AJ
A2
Al

AO
DE
CE

D7
D6
D5
D4
D3
D2
Dl
DO

21
20
19
18
17
15
14
13

ICS2125M

RAll

RAlO
RA9

78

~

f-1Lx
~
58

~
~

-{}--x
~

~
~
-=--

ICS2115

Figure 6: 512 KB Wavetable Memory Interface

G-168

DD7
DD6
DD5
DD4
DD3
DD2
DDl
DDO

II

WaveFront Lite Application Note

CAC Outputs
Figure 7 shows how to connect an inexpensive DAC from NEC to operate with the ICS2115.

VCC +5V

From 1he ICS2115

4 7 8
13
14
15
16

LRCK
SERDATA
BCK

1
10
9

I~

I~

LRCK/WDCK
LRSElIIlSI
SVLSI
CLK

V A A
OVV
ODD
DO

4/8 SEL
LREF
RREF
UPD6376

-==-

AA

LOUT
ROUT

GGG
NNN
000

1
2 5 2

=-

Figure 7: CAC Configuration

G-169

11
6

To

R~er

for Left Channel

To Filler for RighI Channel

>

WaveFront Lite Application Note

Analog Filtering
The circuit in Figure 8 is a 2-pole Chebyshev filter with a 3-dB cut-off of approximately 15 kHz. The cut-off value represents
half the output sampling rate of 33.8 kHz. The Chebyshev configuration provides a slight treble boost of about 2 dB for brightness
in the sound. The 75 Ohm resistor in series with the output serves as disaster protection. Dead shorts of the output will not damage
the amplifier.

+5'1

Connect
R2
R3
to DAC -----"v'V"-,.--"v"'V"~_---".___1
3.3K
Audio Output
3.3K

8
UTA

C2

C3

J

R4
ALOIO OUTPUT

MC34072

.OOluF

CT

lOuF

75

.5'1

.00uF

Figure 8: Analog Anti-Aliasing Filter for the DAC Outputs

G-170

ICS2116

Integrated
Circuit
Systems, Inc.

•

WaveFront™ Interface
General Description

Features

The ICS2116 is the interface component of the WaveFront
wavetable synthesis chip set. The interface chip monitors and
controls the activities of the 68ECOOO processor and 256K x 4
DRAM including address decoding and data buffering to and
from the input source. The input can be serial, parallel, MIDI
or the ISA bus emulating the MPU-401 or 6850 UART.

•
•

For systems not using the ISA bus, the WaveFront Interface
can convert the serial output of the synthesizer into a form that
the optional Motorola 56001 DSP can read. This option provides global digital effects like chorus and reverb to enhance
the audio signal.

•
•
•
•

WaveFront interface to serial, parallel, MIDI and ISA bus
Provides the majority of system "glue" logic, keeping
parts count down and cost low
Uses a single inexpensive 256K x 4 DRAM as system
memory
Contains small code ROM, which eliminates the code
ROM in an ISA design
Soft select of 4 different IRQs
Part of a complete design package that includes software
drivers for Windows and DOS

Applications
•
•
•
•

ISA based sound cards
Wavetable synthesizer daughter cards
External sound modules that connect to a PC's serial or
parallel port
Any system requiring a self contained unit that provides
high quality music synthesis of General MIDI sounds, in
a low cost design

Block Diagram
A(17:1)
UDS
UDS

I'S
RW

BG

CLKIN

SD(7:0)
SA(2:0)
lOR"
lOW"
CS"
RESET
ICIRQ
ICDRQ
ICIOCHRDY

MIDIINI
MIDIIN2

:

68ECOOO
Interface
& BootROM

:
:

±:::t:

-1

ISA
Interface

~

:

Address
Decode

L ~-

~.

I

~.

ROMCS"
DSPCS"

MA(8:0)
DRD{3:0)
RI'S"

Memory
Interface

Internal
Registers
& Core
Logic

CAS"
CLKOUl
RESEl'

!

±:
!

D(15:0)
DTACK"
SR"
IPL(2:1)

WaveFront
Synthesizer
Interface

:
:
:

:

~

UART Controls
I
I
:
L_____________________________________________________________________________________________________ ._____ .J

IOCHRDY
IRQ(3:0)
ICIOR"
ICIOW
ICCS"
ICDACK"
ICTC
MIDIOUl

WaveFront IS a trademark of Integrated CirCUit Systems, Inc
IICS2116fullRevC072694

G·l71

E

II

ICS2116
Pin Configuration

RESET*

WE"
ROMCS"
RAS"
CAS"
MA8

DIS
014
Dl3
012

Dll
DlO

MA7

D9

MAS

08

MA4
MAl
MA2
MAl
MAO
DRD3
ORD2
DRDI

D7

TJ6

DS
D4
D3

MA6

ICS2116

m
DI
DO
UKIN
ICIOW'
ICIOR"

31

100-Pin PQFP
K-11

G-l72

DRDO
MIDIIN2
MIDI IN I
MIDlOlJTl

II

ICS2116

Pin Descriptions

1~~P~I~N~N~U~M~B~ER~~~P~IN~N~A~M~E~r-T~Y~P~E~I~~___ ~~_~~~D~E~S~C~R~IP~T~I_O_N~~~~~___
12, 13, 14
22-29
16

18

82-97
77

.SA<:2:0>
SD<7:0>

I
1/0

I
I

ICS
'/IOR

D<15:0>
IUDS

I

1/0

I

1/

Host Port Address Bits A2 through AO**
!Host Bi-directional Dccatc:.:a.c:Bccu-"S___________________ .~ _ _ 1
Host port ChIp Select (Active Low)
I
Host Read Enable (Active Low)**

68ECOOO Bi-directional Data Bus
68ECOOO Upper Data Strobe (Active Low)

I

1~-----7~8~----~~IL=D~S~------4_--~I~~~6~8E~C~00~0~L~ow~er-D--atc:.:a~S~tr~o~b_e~(A~ct_iv_e_L_o~w~)~_________________1

79
80
55
51,52

IRW
lAS
IDTACK
IPL<2:1>

I
I
0
0

1~-------=5:.::3~----~~IB::..:R:.:..-------__I---0

68EC{)()() R,_nk (A,,;vo Low)
68ECOOO Address Strobe (Active Low)
68ECOOO Data Acknowledge (Active Low)
68ECOOO Interrupt Priority level (Active High)

I
.

----I

68ECOOO Bus Request (Active Low)
II'
54
IBG
I
68ECOOO Bus Grant (Active Low)
56
CLKOUT
0
CLKIN/2 for the 68ECOOO
__ I
81
IRESET
0
Conditioned RESET input for the 68ECOOO and ICS2115 (Active Low)
I
I/ICCS
0
ICS2115 Chip Select (Active Low)
.
_~_.
_
100
IICIOR
0
ICS2115 Read Enable (Active Low)
99
IICIOW
0
ICS2115 Write Enable (Active Low)
5
ICIRQ
I
I
ICS2115 Interrupt Request (Active High)
6
ICIOCHRDY I
I
ICS2115 I/O Channel Ready (Active High)
ICS2115 DMA Request (Active HighL
2
ICDRQ
I
3
IICDACK
O ! ICS2115 DMA Acknowledge (Active Low)
4
IeTe
I
0
ICS2115 Terminal Count (Active High)
38-46
MA<8:0>
0
Operating System DRAM Muxed Address Bus
I/O
Operating System DRAM Data Bus
34-37
DRD<3:0>
11-______4'-'7______~'-'IC=A~S~------4_--~0~~~0.L.C.Pler=ac:.:ti=nQ..gSystem DRAM Column Address Strobe (Active Low)
48
fRAS
0
Operating System DRAM Row Address Strobe (Active Low)
fROMCS
0
Operating System ROM Chip Select (Active Low)
49
7
DSPCS
0
Chip Sclect for a Digital Signal Processor (Active Low)
32
MIDI IN I
I
Serial MIDI Input #1
33
MIDI IN 2
I~erial MIDI Input #2
31
MIDI OUT I
o Serial MIDI Output
I
Clock Input
98
CLKIN
64,15,17
VDD
P
Power Supply
66,68, 19
VSS
P
Ground

G-173

II

ICS2116
Absolute Maximum Ratings
Supply Voltage ..............................
Logic inputs ................................
Ambient operating temp. . .....................
Storage temperature ..........................

-0.5 to 7.0V
-0.5 to VDD+O.5V
O°C to 70°C
-65°C to 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

DC Electrical Characteristics
Vcc-5
T A--O°C to 70°C
- .OV -+ 5%' GND-OVPARAMETER
Supply Voltage
TTL Input Voltage Low
TTL Input Voltage High
Schmidt Input Voltage Low
Schmidt Input Voltage High
XTLI Input Voltage Low
XTLI Input Voltage High
Output Low Current=
Standard Drive
Output High Current
Standard Drive
Output Low Current
Medium Drive
Output High Current
Medium Drive
Output Low Current
High Drive
Output High Current
High Drive
Input Leakage Current
Standard Inputs
Pull-up Current
Pull-down Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

4.75
-0.30
2.20
-0.30
3.00
-0.30
3.50
4.0

5.00

5.25
0.80
VDD+0.30
1.50
VDD+0.30
1.50
VDD+0.30

V
V
V
V
V
V
V
mA

-4.0

rnA

VDD
VIL
VIH
VILS
VIHS
VILX
VIHX
IOL

VOL=O.4V

IOH

VOH=2.8V

IOLZ

VOH=O.4V

IOH2

VOH=2.8V

IOL3

VOH=O.4V

IOH3

VOH=2.8V

lIN

VIN=Vss

-1.0

Ipup

VIN=VDD

15.0
50.0

6.0
-6.0

6.0

9.0
-9.0

9.0

Note: All pins have a maximum capacitive load of 50pfunless noted otherwise.

G·174

-6.0

12.0
-12.0

IPDN

rnA

30.0
90.0

rnA

mA
-9.0

rnA

1.0

uA

50.0
150.0

uA
uA

ICS2116
AC Electrical Characteristics
Please reference the timing diagram titled Host Interface Timing. below.

HOST INTERFACE AC TIMING PARAMETERS
PARAMETER
Address setup to command
Chip select setup to command
Address hold from command
Chip select hold from command
Command width
Write data setup
Write data hold
Read data delay (ready access)
Read data hold
DACK* setup to command
DACK* hold after command
TC setup to command
TC hold after command
TCwidth

SYMBOL

FROM

TO

MIN

MAX

UNITS

tAS

3

5
2
2
1
14
2
1
2
16
2
18
2
18

10
10
10

-

tcs
tAH

1
1
4
6
2
2
15
12

nS
nS
nS
nS
ns
nS
nS
nS
nS
nS
nS
nS
nS
nS

tcH
tcw
tos
tOHW
too
tOHR
tOAS
toAH
ITS
tTH

trw

10
100
50
10
0
0
20
50
25

13

1
17
2
19
19

-

-

60
20
-

-

nJa

-

20

-

E1
SA.SBHE"
CS*.CSMM"

IOR".IOW'
IOCS16"
IOCHROY
SD(Read)
SO (Wnte)

DACK"
TC

18

19

Host Interface Timing

G"l7S

II

ICS2116
/lOW

Miscellaneous Pins
VDD, VDDP
These are the chip power supply pins. VDD pins power the core
logic, while VDDP pins power the pad ring. This arrangement
helps prevent switching spikes due to output transitions from
disturbing the internal operation of the chip by confining large
switching currents to bond wires for pad supplies. These pins
MUST be at the same potential externally.

VSS, VSSP
These are the chip ground pins. VSS pins ground the core logic,
while VSSP pins ground the pad ring. This arrangement helps
prevent switching spikes due to output transitions from disturbing the internal operation of the chip by confining large switching currents to bond wires for pad supplies. These pins MUST
be at the same potential externally.

CLKIN

This input pin is used to write registers when low. SA<2:0> and
/CS must be stable before, during, and after the active low pulse
on /lOw. SD<7 :0> must be stable before, during, and after the
trailing (rising) edge of /lOw.

IOCHRDY
This output pin is normally in a resistive pull-up state. During
/lOR or /lOW low times, this pin can be driven low to indicate
to the host that the requested data transfer is not ready, and that
/lOR or /lOW should be held low until IOCHRDY goes high.

IRQ<3:0>
These outputs allow the host to choose which of four IRQs the
ICS2116 should use. Immediately following power-up, these
pins are all in the high-impedance state. Software on the host
side will then write to the Board Hardware Initialization Register to select one of the four IRQs. The selected IRQ will then
operate as a standard TTL output, while the other IRQs remain
in the high impedance-state.

This input requires a 20 MHz clock source. Internally, the
ICS2116 divides this signal by two and sends it to the 68ECOOO
through the CLKOUT output.

RESET

ISA Host Interface

This input is the active high input for the synthesizer system.
When the input goes high, the /RESET output is latched low
(reset state).

Note: This section applies to PC Mode and not Stand-Alone
Mode. If /lOR is low when the /RESET input goes low, the chip
enters Stand-Alone Mode, otherwise it remains in PC Mode.
Stand-Alone Mode is covered in the following section. Pin
descriptions for PC mode follow:

/CS
This input pin selects read/write access to emulation registers
for the MIDI interface, the Media Master Interface, and the
DMA transfer registers. This signal must be stable before,
during, and after /lOR or /lOW strobes.

SA<2:0>
These address input pins select one of eight direct mapped
registers as determined by the /CS pin. These signals must be
stable before, during, and after /lOR or /lOW strobes.

SD<7:0>
This is the bi-directional data bus used for all register data
transfers.

/IOR
This input pin is used to read registers when low. SA<2:0> and
/CS must be stable before, during, and after the active low pulse
on /lOR. If this signal is low when the !RESET input goes low,
the ICS2116 enters stand-alone mode. See the Stand-Alone
Mode section for more information.

G·!76

ICS2116
Address Definitions

68ECOOO Interface
The 68ECOOO microprocessor communicates with the PC
through the Media Master registers, located in the ICS2116.
The ICS2116 buffers the registers so that both the PC and the
68ECOOO can access them at the same time.
To transfer blocks of data, the ICS2116 performs a DMA-type
operation. The host platform writes the desired byte or word to
the Sample Transfer port, which the ICS2116 transfers to the
ICS2ll5 as a DMA cycle. During this operation, the ICS2116
takes control of the data bus by requesting and receiving data
from the 68ECOOO (using signals fBR and lEG).
The ICS2116 decodes the 68ECOOO's address lines to connect
it to all of the other devices, both internal and external. Since
the compact memory map is only l28K x 16, the ICS2116 does
not decode address bits 18 through 23. As a result, the map
images 64 times in the 16 MB address space. The ICS2116 does
not decode AO bec2Jse address bit 0 is invalid for the 68ECOOO
processor in 16-bit mode.
The fixed Hardware vector, mapped in the lowest 8 bytes,
points to the BootROM. This allows the 68ECOOO to initialize
itself with the BootROM in the ICS2116. Afterwards, it must
load the Synthesizer operating system into OSRAM from one
of three sources: the O.S. Code ROM, wavetable ROM, or from
the PC via the Media Master Port.
The address space of the ICS2116 is as follows (listed as byte
addresses):

Size

Address
3FFFF
3FC30
3FC2F
3FC20
3FCIF
3FCl8
3FC17
3FClO

488 Words
8 Words
14 Words
14 Words

i
13FCOF
3FC08

[4 Words

I
3FC07
3FCOO

4 Words

3FBFF
20000
IFFFF
00008

63KWords

,00007
00000

64KWords
minus 4
Words
4 Words

Content

~

1488 x l6-bit BootROM
(Internal)
DSP Subsystem (Asserts
IDSPCS with special timing
External I/O - IDSPCS with
address timing
6850 MIDI UART
Configuration, Baud Rate
Generator and Misc Status
(Internal)
MPU-401l6850 & Media
Master Interface Registers
(Internal)
ICS2115 Indirect Registers
(Drives /ICCS, fICIOR, &
/ICIOW)
Optional O.S. Code ROM
(Asserts IROMCS)**
64K x l6-bit OSRAM
(Externally a 256K x 4
DRAM)
Fixed HIW Vector to
BootROM Address
0003FC30 (Internal)

**When disable BootROM is set, the upper 488 words of the
optional external 64K OS ROM replace the on chip ROM.

A
This is the local address bus for the wavetable synthesis system.

D
This is the local data bus for the wavetable synthesis system.

IUDS
This input connects directly to the 68ECOOO's Upper Data
Strobe.

ILDS
This input connects directly to the 68ECOOO's Lower Data
Strobe.

IRW
This input connects directly to the 68ECOOO's ReadlWrite
Strobe.

G-177

II

ICS2116
lAS

ICIOCHRDY

This input connects directly to the 68ECOOO's Address Strobe.

This input receives the 110 Channel Ready input from the
ICS2115.

IDTACK
This output connects directly to the 68ECOOO's Data Acknowledge.

ICDRQ

IPL<2:1>

IICDACK & TC

These outputs connect directly to the 68ECOOO's Interrupt
Priority Levels 2 and I.

These outputs operate during a DMA transfer to and from the
ICS2115. /lCDACK indicates that the /lCIOR or /lCIOW is a
DMA transfer. TC connects with the Terminal Count input on
the ICS2115.

IBG

This input receives DMA Requests from the ICS2115.

This output connects directly to the 68ECOOO's Bus Grant.

System DRAM Interface

IBR
This output connects directly to the 68ECOOO's Bus Receive.

This output provides a 10 MHz clock source for the 68ECOOO.

The ICS2116 interfaces with a 256K x 4 DRAM in such a way
that it appears as 64K x 16 RAM to the microprocessor. The
BootROM contains the code to load the synth operating system
into this DRAM.

IRESET

MA<8:0>

CLKOUT

!RESET is a conditioned version of the reset input from the
host. When the RESET input goes high, the !RESET output is
latched low (reset state). The host software changes the !RESET output to the non-reset state, by writing the appropriate
data to the Hardware Initialization Register.

MA<8:0> are the multiplexed address lines.

DRD<3:0>
This is the four bit data bus.

ICAS

ICS2115 Interface

Column address Strobe for the System DRAM.

Based on the address decoding and the 68ECOOO signals IUDS
and ILDS, the ICS2116 drives the /lOR and/lOW inputs on the
ICS2115. The 68ECOOO signals Al and A2 tie directly to the
ICS2ll5 SAO and SAl inputs respectively. The host interface
can pass sample data to the ICS2115 through a DMA-type
operation.

lRAS
Row address Strobe for the System DRAM.

Serial MIDI Interface
MIDI IN I & MIDI IN 2

IICCS

These two serial MIDI inputs are switched internally, to use
only one UART. The initialization register determines which
MIDI input controls the synthesizer.

This output is the active low chip select for the ICS2115.

IICIOR
MIDI OUT I

This output is the active low read strobe for the ICS2115.

MIDI OUT 1 is a serial MIDI output.

IICIOW
This output is the active low write strobe for the ICS2115.

ICIRQ
This input accepts the hardware interrupt requests from the
ICS2115.

G-178

II

ICS2116

ROM and DSP Interface

Serial DSP Interface

fROMCS

SA

This output enables the Operating System ROM. Upon initialization, the code in the BootROM transfers the operating system
from the ROM to the system RAM. Afterwards, it begins
execution from RAM and never accesses the Operating System
ROM.

This input receives the bit clock from the ICS2115.

SA
This input receives the left/right clock from the ICS2115.

SA<2>

/DSPCS

This input receives the serial audio data from the ICS2115.

This output is an address decode for a Motorola DSP.

IOCHRDY
This output is the bit clock for the serial DAC when the optional
DSPis used.

Stand-Alone Mode
When the ICS2116 enters Stand-Alone Mode, some of the ISA
interface pins assume different functions. This is illustrated
below. The chip detects this mode by checking the lOR signal
when reset goes low. If lOR is low at that instant, the ICS2116
enters "Stand-Alone Mode" and remains that way until reset or
power-down occurs.

IRQ
This output is the bit clock for the DSP.

IRQ<2>
This output is the left/right clock for the DSP.

nOR

IRQ <3 >

IIOR should be tied low to signify stand-alone mode.

This output is the serial audio data for the DSP.

fEG
This input selects which baud rate the operating system will
receive data on the MIDI IN I input. The high state indicates
the standard MIDI baud rate, 31.25K. A low level indicates a
rate suitable for the serial port on the PC, 38400 baud.

MIDI IN I
This is the only usable serial input in stand-alone mode.

MIDIIN2
MIDI IN 2 is not available in stand-alone mode.

Parallel Port Interface
flOW
This serves as a /STROBE input for the parallel port. The ICS2116
latches the data on SD<7:O> when the rising edge occurs.

IRQ
This output serves as a Transmit Data Ready indicator for the
parallel port BUSY input.

SD<7:0>
This serves a unidirectional data bus for parallel input.

fCS
This input still serves as a chip select for the parallel port. To enable
the parallel interface, tie this pin low. Otherwise, tie it high.

G·179

II

ICS2116

ICS2115
BCK
lRCK
SERDATA

CSP

ICS2116
~
~
~

SAO

IRao

SA1

IRa1

SA2

IRQ2

CAC

TDRF

---

IRQ3

OSClK

--"

~

OlRCK

BCK

/

ODATA

~

SERIN

--"

BCK

--"/

SERDATA

~

lRCK
SEROUT

lRCK

IOCHRDY

Hardware Initialization Register

Host Interface Register Descriptions

Following power-on or a hard reboot of the host PC, the
ICS2116 resets its !RESET output which will hold the
68000 and ICS2115 in the reset state. An initialization
program, running in the PC, writes to the Initialization
Register. This sets the !RESET output and removes the
Hardware Initialization Register from the register set.
Then, the Base+O register becomes the MPU-401l6850
Port. The format of this register is as follows:

ICS provides a program named SETUPSND.EXE that initializes the ICS2116 and downloads the Operating System to the
system RAM. Using command line parameters, the user can
specify the options that are contained in the Hardware Initialization Register.
The /CS input enables the Host Interface for I/O transfers.
Using three address lines, the ICS2116 has the following
registers:
Base Address
Offset
7

6
5
4

3
2
I
0

~

~~r±=lIW
I
Disable Boot ROM

Function
Sample Data Transfer with Terminal
Count (High Byte)
Sample Data Transfer with Terminal
Count (Low Byte)
Sample Data Transfer (High Byte)
Sample Data Transfer (Low Byte)
Media Master Control
Media Master Data
MPU-401l6850 Port
MPU-401l6850 Port (Hardware
Initialization Register, see below)

L--'--'-_ _ _~

Reserved
IRQ Selection

---~ MIDI Interface Select
' - - - - - - - - - - - - - Enable IRQ Driver

Board HIW Initialization Register: (Base+O)

Bit 7 - Enable IRQ Driver
o- Tristate the ICS2116 IRQ outputs 3-0.
I - Enable IRQ selected by bits 5:3 to be driven onto
the PC Bus.
Bit 6 - MIDI Interface Select
0- Use the MIDI Input I
I - Use the MIDI Input 2
Bits 5:3 - IRQ Selection
000 - IRQO
OOI-IRQI
010 - IRQ2
01 1 - IRQ3
1 X X - All IRQs Disabled
Bits 2: I - Reserved
Bit 0 - Disable Boot ROM. When set to 1, the ICS2116
selects the external ROM instead of the internal Boot
ROM mapped at 03FC30-03FFFFH.

G·180

ICS2116
MIDI Emulation Control/Status Register
The MIDI Control Status register can be configured as
either a 6850 compatible or an MPU-401 compatible sets.
The MIDI Emulation Mode bit in the Media Master
Emulation Mode Register will indicate which emulation
mode is used. Using SETUPSND.EXE, the user can
change the emulation mode.

6850 Mode Control (Base + 0) (Write Only)
The PC host application program can access this MIDI control
register by writing to this address. The control register is
mapped as follows.

IIIIIIIIU
I I

I I I

~~~et (11-reset, else soft)

I

.
Transmit Interrupt Control
' - - - - - - - - - - Receive Interrupt Enable

MIDI (6850) Control Register

1:0 - Reset - Resets the MIDI Port
11 = Reset (Resets Receive Buffer Full Interrupt
(to the Host) and Receive Interrupt Enable)
00,01 and 10 = No Reset
4:2 - Soft - Software controlled functions
6:5 - Transmit Buffer Empty Interrupt Control
01 = Interrupts are enabled
00, 10 and 11 = Interrupts disabled
7: - Receive Buffer Full Interrupt Enable
1 = Interrupts enabled
o = Interrupts disabled

6850 Mode Status (Base + 0) (Read Only)
The PC host application program can access this MIDI status
register by reading this address. The status register is mapped
as follows.
MIDI (6850) Status Register

~I~II~II~I~II~II~II~~=';I

Receive Buffer Full (RBF)
Transmit Buffer Empty (TBE)
Soft
Interrupt Request

,

0: - Receive Buffer Full
1 = full
0= empty
1: - Transmit Buffer Empty
1 = empty
0= full
6:2 - Soft
7: - Interrupt Request
1 = Interrupt pending
o = Interrupt not pending

MPU-401 Mode Control (Base + 1) (Write Only)
The PC host application program can access this MIDI control
register by writing to this address. The control register mapping
is software dependent.

IIIII
Soft

MIDI (MPU-401) Control Register

7:0 - Soft - Software controlled functions

MPU-401 Mode Status (Base + 1) (Read Only)
The PC host application program can access this MIDI status
register by reading this address. The status register is mapped
as follows.
MIDI (MPU-401) Status Register

~Ir==1r==1~I~IIF==,I~II
!

I_I_I_ _ _ Soft
Transmit Buffer Full (TBF)
L-_ _ _ _ _ _ _ _ Receive Buffer Empty (RBE)

I.

L I_ _

5:0 - Soft
6: - Transmit Buffer Full
1 = full
o = empty
7: - Receive Buffer Empty
1 = empty
0= full

G-181

ICS2116
6: - Host Data Master Interrupt enable
This bit enables or disables all interrupts from the
WaveFront subsystem to the PC host application program. Note that this includes the MIDI emulation
mode interrupts from the MIDI Emulation Status
register. It does not affect the interrupts for the
WaveFront Operating System.
I =enable
0= disable
7: - Master Reset
This bit will cause a Soft Reset to occur which resets
the WaveFront chip.

MIDI Emulation Data Register
This register is the MIDI data port for writing and reading
MIDI data. The PC host application program can transfer
MIDI data between itself and the WaveFront Operating
System via this register.
6850 Mode Data (Base + 1) (ReadIWrite)
Eight bit data.
MPU-401 Mode Data (Base + 0) (ReadIWrite)
Eight bit data.

I

The Media Master interface provides access to the more
sophisticated features of the operating system. Host programs use these registers to download wavetable data.
The descriptions follow:

Host ControlJStatus (Base + 3) (Read Only)
The Host Control/Status register will have the following bit
meanings when read by the PC host.

Host Data (Base + 2) (ReadIWrite)
Eight bit data register. The PC host application program can
write and read this register to exchange commands and data
with the WaveFront.

I I I I I I I I I
Rx Interrupt Enable
II L - Host
Host Rx Register Full
Host Rx Interrupt Pending
Reserved (Soft)
Host Tx Interrupt Enable
Host Tx Register Empty
Host Tx Interrupt Pending
Reserved (Soft)

Host Control/Status (Base + 3) (Write Only)
The Host Control/Status register will have the following bit
meanings when written to by the PC host application program.

I I I I I I I I I

IL

=run

o =reset (WaveFront chip soft reset)

Media Master Registers

Host Status Register
Host Rx Interrupt Enable
DMA Page Address Bit 0 (Soft)
DMA Page Address Bit 1 (Soft)
Reserved (Soft)
Host Tx Interrupt Enable
Play/Mute (Soft)
Master Interrupt Enable
Master Reset (O=Reset, 1=Run)

Host Control Register

0: - Host Data Receive Interrupt Enable
I =enable
0= disable
2: I - DMA Page Address (2 bits) (Soft)
3: - Reserved (Soft)
4: - Host Data Transmit Interrupt Enable
I =enable
0= disable
5: - PlaylMute (Soft)
I =play
0= mute

0: - Host Data Receive Interrupt Enabled
I =enabled
0= disabled
I: - Host Data Receive Register Full
I = full
0= empty
2: - Host Data Receive Interrupt Pending
I =Pending
0= Not Pending
3: - Reserved (Soft)
4: - Host Data Transmit Interrupt Enabled
I = enabled
0= disabled
5: - Host Data Transmit Register Empty
I =empty
0= full
6: - Host data Transmit Interrupt Pending
I =Pending
o =Not Pending
7: - Reserved (Soft)

G-182

ICS2116
Ordering Information
ICS2116Y
Example:

ICS XXXX M

L~_
Y=QFP

L...._ _ _ _ _ _
L -_ _ _ _ _ _ _ _

Device Type (consists of 3 or 4 digit numbers)
Pref'1X
ICS, AV =Standard Device; GSP=Genlock Device

G-l83

G-184

,,
•
.

ICS2122

Integrated
Circuit
Systems, Inc.

WaveFront™ Sounds (16M Bit CMOS Mask ROM)
Description

Features

WaveFront Sounds are masked ROMs that serve as the
wavetable for the ICS2115 WaveFront Synthesizer. Each
sound set, 4 MB, 2 MB and 512 KB, contains the musical data
needed to synthesize the instruments from the General MIDI
specification. The 4 MB sound set consists of two 2 MB ROMs,
the ICS2124M·OOl and ICS2124M·002. The 2 MB sound set
consists of one 2 MB ROM, the ICS2122M·OOl. The 512 KB
sound set consists of one 512 KB ROM, the ICS2125M·OOl.

•
•

•

•

Complete set of General MIDI sounds, which contains
128 instruments and 69 drum sounds.
Available in three sizes, 4 MB, 2 MB & 512 KB, to
provide the optimal balance between price and performance for many applications.
l6-bit linear wavetable (ICS2l24-001l-002), compressed
wavetable (ICS2122-00l), or full-featured wavetable
(ICS2l25-001).
Uses 2M x 8 MROMs in 44-pin SOP packages.

Block Diagram

II

2 MB Patch Set

Address

""
"'21

ICS2115

Data

L'

8

ICS2122

Output Enable

WaveFront IS a trademark of Integrated CircUit Systems, Inc
IICS21228eyAo92294

G·185

ICS2122
Pin Configuration
NC

A18
A17
A7
A6

A5

1
2
3
4
5
6

A4

7

A3
A2

8
9
10
11

Ai

AO
CE

GNO
OE
00
08
01

12
13

44
43

A19

42

AS

41

A9

40
39
38
37
36
35

Al0
All

34

A16

33
32

31

14
15

NC

30

29
28
27

A12
A13
A14
A15

BYTE

GNO

015/A-l

07

02
010
03

20

21

24

014
06
013
05
012
04

Oil

22

23

VOO

09

16

17
18
19

26
25

44-Pin SOP
K·8

Pin Descriptions
PIN NUMBER

PIN NAME

DESCRIPTION

TYPE
Address Inputs

2-11,34-43

AO-A19

I

15-22, 24-30

DO-D14

0

Data Outputs

12

CE

I

Chip Enable Input

14

OE

I

Output Enable Input

31

D15/A-1

33

BYTE

I

I/O

Data Output!Address Input
Word, Byte selection Input tied low for byte operation

23

VDD

P

Power Supply

13,32

GND

P

Ground

1,44

NC

-

No Connection

G-l86

ICS2122
Absolute Maximum Ratings
SYMBOL

ITEM

VDD

Power Supply Voltage

VIN

Input Voltage

VOUT
PD

Output Voltage
Power Dissipation

TSTG

Storage Temperature

TOPR

Operating Temperature

TSOLDER

Soldering Temperature' Time

RATING

UNIT

-0.5-7.0

V

-0.5-VDD

V

O-VDD

V

1.0/0.6

W

-55-150

DC

0-70

DC

260' IO

DC, sec

AC Characteristics
TA = 0-70DC, VDD=5±1O%
SYMBOL

MIN

TYP

MAX

UNITS

tCYC

150

-

-

ns

tACC

-

-

150

ns

tCE

-

-

150

ns

Output Enable Access Time

toE

-

-

70

ns

Output Disable Time from CE

tCED

-

40

ns

Output Disable Time from OE

tOED

-

40

ns

Output Hold Time

tOH

5

-

-

ns

PARAMETER
Cycle Time
Address Access Time
Chip Enable Access Time

AC Test Conditions
Output Load: 100pf + !TTL
Input Levels: 0.6V, 2.4V
Timing Measurement Reference LevelslInput: O.SV, 2.2V
Timing Measurement Reference Levels/Output: O.SV, 2.0V
Input Rise and Fall Time: 5ns

G·187

E

ICS2122
Timing Waveform
BYTE-WIDE READ MODE
tCYC

Valid

... tOE.
tACC

•

DO-07

Valid

Ordering Information
ICS2122-001 M
Example:

ICS XXXX-PPP M

i

1 ~p~'

Pattern Number (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - Prefix

res, AV=Standard DeVIce; GSP=Gen1ock DeVIce

G-188

•

ICS2124-001
ICS2124-002

Integrated
Circuit
Systems, Inc.

WaveFrontTM Sounds (16M Bit CMOS Mask ROM)
Description

Features

WaveFront Sounds are masked ROMs that serve as the
wavetable for the ICS2115 WaveFront Synthesizer. Each
sound set, 4 MB, 2 MB and 512 KB, contains the musical data
needed to synthesize the instruments from the General MIDI
specification. The 4 MB sound set consists of two 2 MB ROMs,
the ICS2124M-OOl and ICS2124M-002. The 2 MB sound set
consists of one 2 MB ROM, the ICS2122M-OOl. The 512 KB
sound set consists of one 512 KB ROM, the ICS2125M-OOl.

•
•

•

•

Complete set of General MIDI sounds, which contains
128 instruments and 69 drum sounds.
Available in three sizes, 4 MB, 2 MB & 512 KB, to
provide the optimal balance between price and performance for many applications.
16-bit linear wavetable (ICS2124-001l-002), compressed
wavetable (ICS2122-001), or full-featured wavetable
(ICS2125-001).
Uses 2M x 8 MROMs in 44-pin SOP packages.

Block Diagram

E1
ICS21 24-001

Output
Enable

ICS2115

Address
Data

21
~ 8

rt

++

Output Enable

ICS21 24-002

4 MB Patch Set

WaveFront

!'CS 21 24B e IlAQ92294

G-189

IS

a trademark of Integrated CirCUit Systems, Inc

ICS2124-001
ICS2124-002
Pin Configuration
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
AO
CE
GNO
OE
00
08
01
09
02
010
03
011

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

o::r

,...

N
N

CIJ

~

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
A19
AS

A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GNO
015/A-1
07
014
06
013
05
012
04
VOO

44-Pin SOP
K-8

Pin Descriptions
PIN NUMBER

PIN NAME

DESCRIPTION

TYPE

2-11,34-43

AO-AI9

I

Address Inputs

15-22,24-30

DO-DI4

0

Data Outputs

12

CE

I

Chip Enable Input

14

OE

I

Output Enable Input

31

DJ5/A-J

33

BYTE

I

110

Data Output!Address Input
Word, Byte selection Input tied low for byte operation

23

VDD

P

Power Supply

13,32

GND

P

Ground

1,44

NC

-

No Connection

G-190

II

ICS2124-001
ICS2124-002

Absolute Maximum Ratings
SYMBOL

ITEM

VDD

Power Supply Voltage

VIN

Input Voltage

VOUT
PD
TSTG
TOPR
TSOLDER

Output Voltage
Power Dissipation
Storage Temperature
Operating Temperature
-

Soldering Temperature' Time

RATING

UNIT

-0.S-7.0

V

-O.S-VDD

V

O-VDD

V

1.0/0.6

W

-SS-ISO

°C

0-70

°C

260' 10

°C . sec

AC Characteristics
TA = 0-70°C, VDD=S±IO%
SYMBOL

MIN

TYP

MAX

UNITS

Cycle Time

!eYC

ISO

-

-

ns

Address Access Time

tACC

-

-

ISO

ns

Chip Enable Access Time

tCE

-

-

ISO

ns

Output Enable Access Time

tOE

-

-

70

ns

Output Disable Time from CE

tCED

-

40

ns

Output Disable Time from OE

tOED

-

-

40

ns

Output Hold Time

tOH

S

-

-

PARAMETER

I

I

AC Test Conditions
Output Load: 100pf + 1TTL
Input Levels: 0.6V,2.4V
Timing Measurement Reference LevelslInput: 0.8V, 2.2V
Timing Measurement Reference Levels/Output: 0.8V,2.0V
Input Rise and Fall Time: Sns

G-191

I

I

I

ns

I

II

ICS2124-001
ICS2124-002
Timing Waveform
BYTE-WIDE READ MODE

!eye
Valid

... tOE.

tAee

Valid

00-07

Ordering Information
ICS2124-001 M or ICS2124-002M
Example:

ICS XXXX-PPP M

11

p.=,np,

Pattern Nnmber (2 or 3 digit number for parts with ROM code patterns)
' - - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - - Prefix
ICS, AV ~Standard DeVIce;

GSP~Genlock

G-192

Device

•

ICS2125

Integrated
Circuit
Systems, Inc.

Product Preview

WaveFront™ Sounds (4M bit CMOS Mask ROM)
General Description

Features

WaveFront Sounds are masked ROMs that serve as the
wavetable for the ICS2115 WaveFront Synthesizer. Three different sounds sets are available: 4 MB (ICS2124-001 and
ICS2124-002), 2 MB (ICS2122) and 512 KB (ICS2125). Each
sound set contains the musical data needed to synthesize
instruments from the General MIDI specification. The 512 KB
sound set consists of one 512 KB ROM.

•
•

Full featured set of General MIDI sounds.
Available in three sizes, 4 MB, 2 MB, and 512 KB to
provide the optimal balance between price and performance for many applications.
Uses 512K Word X 8 bit ROM in a 32-pin SOP package.

•

Block Diagram

E
Address
./

19 ......

ICS2115

Data

./

'8
Output Enable

512K Patch Set

kS2125RevA092294

G·193

ICS2125

ICS2125
Pin Configuration

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

N.C.

A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
DO
01
02
GNO

Lt)

C\I
'I"'"

C\I

en

0

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VDD

A18
Ail
A14
A13
A8
A9
A11
DE
A10
CEICE

07
06
05
04
03

32-Pin SOP
K-8

Pin Descriptions
PIN NUMBER

PIN NAME

2-12, 23, 25-31

AO through A18

TYPE
I

DO through D7

22

CE

32
16

VDD
GND

0
I
I
P
P

1

N.C.

-

13-15,17-21
24

OE

DESCRIPTION
Address Inputs
Data Outputs
Output Enable Input
Chip Enable Input
Power Supply
Ground
No Connection

G·194

II

ICS2125

Absolute Maximum Ratings
SYMBOL

ITEM

VDD

Power Supply Voltage

VIN

Input Voltage

VOUT

Po

UNIT

-0.S-7.0

V

-O.S-VOD

V

Output Voltage

0- VOD

V

Power Dissipation

1.0/0.6
-SStoISO

W
DC

0-70

DC

260 - 10

DC - sec

TSTG

Storage Temperature

TOPR

Operating Temperature

TSOLDER

I

RATING

Soldering Temperature - Time

--

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.

AC Characteristics
TA = 0-70 DC, VDD=S±IO%
PARAMETER

SYMBOL

I

MIN

I

TYP

I

MAX

I

UNITS

Cycle Time

tcYC

ISO

-

-

ns

Address Access Time

tACC

-

150

ns

-

150

ns

-

70

ns

40

ns

Output Enable Access Time

tOE

-

Output Disable Time from CE

tCED

-

Output Disable Time from OE

tOED

-

-

Output Hold Time

tOH

5

-

Chip Enable Access Time

tCE

AC Test Conditions
Output Load: 100pf + I TTL
Input Levels: 0.6V,2AV
Timing Measurement Reference LevelslInput: 0.8V, 2.2V
Timing Measurement Reference Levels/Output: 0.8V, 2.0V
Input Rise and Fall Time: 5ns

G-19S

I

40

ns
ns

--

I

E1

ICS2125
Timing Diagram
BYTE-WIDE READ MODE
tCYC

Valid
tCE

OIl(

tOE.

tACC

00-07 __________~H~i~~____~

Valid

Ordering Information
ICS2125M
Example:

ICSXXXX M

L_..~
M=SOP

L -_ _ _ _ _ _
L -_ _ _ _ _ _ _ _

Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard DevIce; GSP=Genlock DevIce

G-196

ICS

GENDAC
Products

ICS GENDACs provide highly integrated mixed-signal solutions for advanced
VGA controllers. These products have been designed utilizing ICS's proven
technology for exceptionally low-jitter video clock synthesizers and high-accuracy video DACs. The definitions for these products were written with the close
cooperation ofVGA controller manufacturers to ensure our customers maximum
design flexibility. Our 16-bit pixel path devices are leading-edge components
for video systems and establish the industry standard with 70 hertz refresh
requirements at resolutions of 1280 x 1024 pixels.

H-l

ICS GENDAC Products Selection Guide
Product
Applications

Personal Computer and
Engineering Work
Station Computer Graphics

ICS
Device Type

Description

Package Types

Page

ICS5300

8-bit Pixel Port, Triple 8-bit Video
DACs, Operation to 135 MHz.
8 Selectable P-Clock Frequencies
(6 Programmable).

44-PinPLCC

H-3

ICS5301

Tseng Compatibility, 8-bit Pixel Port,
Triple 8-bit Video DACs, Operation to
135 MHz. 8 Selectable P-Clock
Frequencies (6 Programmable).

44-PinPLCC

H-33

ICS5340

16-bit Pixel Port, Triple 8-bit Video
DACs, Operation to 135 MHz.
2: 1 Pixel Multiplexing. 8 Selectable
P-Clock Frequencies (6 Programmable).
2 Selectable and Programmable
M-Clock Frequencies.

68-PinPLCC

H-63

ICS5341

Tseng Compatibility, 16-bit Pixel Port,
Triple 8-bit Video DACs,
Operation to 135 MHz.
2: 1 Pixel Multiplexing. 8 Selectable
P-Clock Frequencies (6 Programmable).
2 Selectable and Programmable
M-Clock Frequencies.

68-PinPLCC

H-97

ICS5342

S3 SDAC compatible, 16-bit Pixel Port,
Triple 8-bit video DACs,
Operation to 135 MHz.
2: 1 Pixel Clock Doubler. 8 Selectable
P clock frequencies (8 Programmable).
2 Selectable and Programmable
M-Clock Frequencies.
24-bit Packed Pixel Support.
On-the-Fly mode Select Pin Allows
Pixel Color Depth Switching.

68-PinPLCC

H-lOl

ADVANCE INFORMATION documents contsin information on new products in !he sampling or preproduction phase of development. Characteristic dats
and other specifications are subject to change without notice.

PRODUCT PREVIEW documents contsin information on products in !he formative or design phase of development. Characteristic dats and other specifications
are design goals. ICS reserves the right to change or discontinue !hese products without notice.

H-2

ICS5300
GENDAC

Integrated
Circuit
Systems, Inc.

•

8-bit Integrated Clock-LUT-DAC
General Description

Features

The ICS5300 GENDAC is a combination of dual programmable clock generators, a 256 x 18-bit RAM, and a triple
8-bit video DAC. The GENDAC supports 8-bit pseudo
color applications, as well as IS-bit, 16-bit and 24-bit True
Color bypass for high speed, direct access to the DACs.

• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, 15, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixel) clock
frequencies (CLKO)
• One programmable memory (controlled clock
frequency (CLKl)
• DAC power down in blanking mode
• Low power operation
• Anti-sparkle circuitry
• On-chip loop filters reduce external components
• Standard CPU interface
• Single external crystal (typically 14.318 MHz)
• Monitor Sense
• Internal voltage reference
• 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1)
versions
• Very low clock jitter

The RAM makes it possible to display 256 colors selected
from a possible 262, 144 colors. The dual clock generators
use Phase Locked Loop (PLL) technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains 8 frequencies, 6 of
which are programmable by the user. The memory clock
has one programmable frequency location.
The three 8-bit DACs on the ICS5300 are capable of
driving singly or doubly-terminated 750 loads to nominalO - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather
than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock)
generation for graphicS, using patented techniques to
produce low jitter video timing.

Block Diagram
SENSE'

~8:ERED
1=
GREEN

PO-P7

L..~~---~~~iT
VREF

~PCLK

DO-D7

~-

i I t - - - - - - - - - - - - - - - - - - - - - -....

CLKO

" 1 - - - - - - - - - - - - - - - - - - - - - -....

CLK!

B-3

ICS5300
GENDAC

Pin Configuration
RO*

00
01

7

~tn'

Pin Description (68 pin PlCC) K-10
Symbol

Pin #

Type

Description

CSI

1

Input

CS2

2

Input

CGND
SENSE*

3
4

Output

CVDD
WR*

5

-

6

Input

RD*

7

Input

8 -15

I/O

Clock select 1. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.
Clock select 2. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.
Ground for clock circuits. Connect to ground.
Monitor Sense, active low. This pin is low when any of the red, green,
or blue outputs have exceeded 335mV. The chip has on-board comparators and an internal 335mV voltage reference. This is used to detect
monitor type.
Clock Power Supply. Connect to DVDD
RAM/PLL Write Enable, active low. This signal controls the timing of the
write operation on the microprocessor interface inputs, DO-D7.
RAM/PLL Read Enable, active low. This is the READ bus control signal.
When active, any information present on the internal data bus is available
on the Data I/O lines, DO-D7.
System data bus I/O. These bidirectional Data I/O lines are used by the
host microprocessor to write (using active low WR*) information into,
and read (using active low RD*) information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR* latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD* determines the end of the read
cycle. When RD* is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tri-state mode.

DO-D7

-

H·4

ICS5300
GENDAC

•
Pin Description (continued)
Symbol

Pin #

Type

RSO
RSI
RS2
CGND
CVDD
RED
GREEN
BLUE

16
17
18
19
20
21
22
23

Input
Input
Input

Output
Output
Output

AVDD
RSET

24
25

Input

AGND
DGND
VREF

26
27
28

Input

DVDD
PO-P7

29
30 -37

Input

PCLK

38

Input

BLANK"

39

Input

XIN
XOUT
CLKO

40
41
42

Input
Output
Output

CLKI
CSO

43
44

Output
Input

-

-

-

-

Description
Register Address Select O. These inputs control the selection of one of the
six internal registers. They are sampled on the falling edge of the active
enable signal (RD" or WR").
Ground for clock circuits. Connect to ground
Clock Power Supply. Connect to AVDD
Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value. These
outputs are typically used to drive a CRT monitor.
Analog power supply. Connect to AVDD
Resistor Set. This pin is used to set the current level in the analog outputs.
It is usually connected through a 140Q, 1% resistor to ground.
Analog Ground. Connect to ground
Digital Ground. Connect to ground
Internal Reference Voltage. Normally connects to a O.lI1F cap to
ground. To use an external Vref, connect a 1.235V reference to this pin.
Digital power supply.
Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
should be grounded if they are not used.
Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address Anding inputs. This clock also controls the progress of these
values through the three-stage pipeline of the Color Palette RAM,
DAC and outputs.
Composite BLANK" Signal, active low. When BLANK" is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette may still be updated through DO-D7 during blanking.
Crystal input. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
Memory clock output. Used to time the video memory.
Clock select o. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output.

H-5

ICS5300
GENDAC

II
Internal Registers
RS2 RSI

RSO

Register
Name

Description
(all registers can be written to and read from)

There is a single Pixel Address register within the GENDAC. This register
can be accessed through either register address 0,0,0 or register address
0,1,1. A read from address 0,0,0 is identical to a read from address 0,1,1.
Writing a value to address 0,0,0 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Initializes the Color Value register.
Writing a value to address 0,1,1 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Loads the Color Value register with the contents of the location in the
addressed RAM palette and then increments the Pixel Address register.
Pixel Address
WRITE

Writing to this 8-bit register is performed prior to writing one or more
color values to the color palette RAM.

1

Pixel Address
READ

Writing to this B-bit register is performed prior to reading one or more
color values from the color palette RAM.

1

Color Value

° ° °
°
° °
1

The 18-bit Color Value register acts as a buffer between the microprocessor
interface and the color palette. Using a three bytes transfer sequence allows
a value to be read from or written to this register. When a byte is read, the
color value is contained in the least significant 6 bits, DO-DS (the most
significant 2 bits are set to zero). When writing a byte, the same 6 bits are
used. When reading or writing, data is transferred in the same order - the
red byte first, then green, then blue. Each transfer between the Color Value
register and the color palette replaces the normal pixel mapping operations
of the GENDAC for a single pixel.
After writing three definitions to this register, its contents are written to the
location in the color palette RAM specified by the Pixel Address register,
and the Pixel Address register increments.
After reading three definitions from this register, the contents of the location
in the color palette RAM specified by the Pixel Address registers are copied
into the Color Value register, and the Pixel Address register increments.

°

1

°

Pixel Mask

The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel
Address value applied to the Pixel Address inputs (PO-P7). A one in a
position in the mask register leaves the corresponding bit in the Pixel
Address unaltered, while a zero sets that bit to zero. The Pixel Mask register
does not affect the Pixel Address generated by the microprocessor interface
when the palette RAM is being accessed.

H-6

ICS5300
GENDAC

•
Internal Registers (continued)
RS2

RSl

RSO

Register
Name

Description
(all registers can be written to and read from)

1

0

0

PLLAddress
WRITE

Writing to this 8-bit register is performed prior to writing one or more
PLL programming values to the PLL Parameter register.

1

1

1

PLLAddress
READ

Writing to this 8-bit register is performed prior to reading one or more
PLL programming values from the PLL Parameter register.

1

1

0

Command

This8-bit register selects the color mode, for instance 8-bit Pseudo Color, HiColor, True Color, or XGA, and DAC power down. The registers are reset
to pseudo color mode on power up.

1

0

1

PLL
Parameter

There are sixteen parameter registers as indexed by PLL Address Write/
Readregisters. Parameter registers OO-OD and OF are two bytes long and OE
is one byte long. This register set contains one control register. The bits of this
register include clock select and enable functions, the rest contain PLL
frequency parameters. After writing the start index address in the PLL
address register, these registers can be accessed in successive two (or one)
bytes. The address register auto increments after one or two bytes to access
the en tire register set.

II

H-7

ICS5300
GENDAC

•
Absolute Maximum Ratings
Power Supply Voltage .................................................. 7 V

DC Digital Output Current .................................... 25 rnA

Voltage on any other pin ...... GND - O.5V to VDD + 0.5V

Analog Output Current ......................................... .45 rnA

Temperature under bias .......................... - 40° C to 85° C

Reference Current .................................................. -15 rnA

Storage Temperature ............................. - 65° C to 150° C

Power Dissipation ..................................................... 1.0 W

Note

Stresses above those listed under Absolute MaxImum Ratings may cause permanent damage to the device. ThIS IS a stress ratmg only and
functional operation of the device at these or any other cond,tIOns above those mdicated m the operational sechons of thIS speCIficahon
is not Implied. Exposure to absolute maximum rating conditIOns for extended pen ods may affect devIce reliability.

Electrical Characteristics
Symbol

Parameter

Conditions

Min

Max

Units

DC CHARACTERISTICS (note: J)
VDD

Positive supply voltage

4.75

5.25

V

VIH

Input logic ''}'' voltage

2.0

V

VIL

Input logic "0" voltage
Reference current

-0.5

VDD + 0.5
0.8

-7.0

-10

rnA

Reference voltage

1.10

1.35

V

±1O

IlA

VDD=max,
GND::;VIN::;V DD

±50

IlA

10 = max,

250

rnA

50

rnA

IREF
VREF
lIN

Digital input current

Ioz

Off-state digital output current

IDD

Average power supply current

VDD = max,

V

GND::;VIN::;V DD

Digital outputs unloaded

IDACOFF
VOH

DACs in power down mode

No palette access
2.4

Output logic "1"

10 = -3.2mA, note K

VOL
ICLKr

Output logic "0"

10 = -3.2mA, note K

0.4

V
V

Input Clock Rise Time

TTL levels

15

ns

ICLKf

Input Clock Fall Time

TTL levels

15

ns

FD

Frequency Change of CLKO and
CLKI over supply and temperature

With respect to
typical frequency

0.05

%

H-8

ICS5300
GENDAC

II
Electrical Characteristics (continued)
Symbol

Parameter

Conditions

Min

Max

Units

DAC CHARACTERISTICS (note: J)
Vo (max) Maximum output voltage
10 (max) Maximum output current
Full scale error
DAC to DAC correlation
Integral Linearity, 6-bit
Integral Linearity, 8-bit
Full scale settling time*, 6-bit
Full scale settling time*, 8-bit
Rise time (10% to 90%)*
Glitch energy*

1.5
21

10 :::; 10 rnA

Vo :::;IV
note A, B
note B
note B
note B
noteC
noteC
noteC
noteC

±5
±2
±0.5
±1
28
20
6
200

V
rnA
%
%
LSB
LSB
ns
ns
ns
pVsec

, Charactenzed values only

Symbol

Parameter

Conditions

Min

Max

Units

25
25

135
135
1.5
1.5
60/40
130 ps
300ps
25

MHz
MHz
ns
ns
%

PLL AC CHARACTERISTICS
fO

h
tr
tr
dt
hs
jabs
fref

Clock 0 operating range
Clock 1 operating range
Output clocks rise time
Output clocks fall time
Duty Cycle
Jitter, one sigma
Jitter, absolute
Input reference frequency

25 pf load, TTL levels
25 pf load, TTL levels
40/60

Typically 14.318 MHz

H-9

-300 ps
5

ps
ps
MHz

ICS5300
GENDAC

AC Electrical Characteristics (note: J)

Symbol

Parameter

tWHDX
tRLQX
tRLQV
tRHQX
tRHQZ
tWHWLl
tWHRLl
tRHRLl
tRHWLl
tWHWL2
tWHRL2
tRHRL2
tRHWL2
tWHRL3

PCLKperiod
PCLK jitter
PCLK width low
PCLK width high
Pixel word setup time
Pixel word hold time
BLANK* setup time
BLANK* hold time
PCLK to valid DAC output
Differential output delay
WR* pulse width low
RD* pulse width low
Register select setup time
Register select setup time
Register select hold time
Register select hold time
WR* data setup time
WR* data hold time
Output turn-on delay
RD* enable access time
Output hold time
Output turn-off delay
Successive write interval
WR* followed by read interval
Successive read interval
RD* followed by write interval
WR* after color write
RD* after color write
RD* after color read
WR* after color read
RD* after read address write

tSOD

SENSE* output delay

tCHCH
MCHCH
tCLCH
tCHCL
t pVCH
tCHPX
tBVCH
tCHBX
tCHAV
MCHAV
tWLWH
tRLRH
tsvwL
tsvRL
t WLSX
t RLSx
t DVWH

Condition

80 MHz
Min Max

110 MHz
Min Max

l35MHz
Min Max Units

12.5

9.09

7.4

±2.5

noteD

5
5
noteE
noteE
noteE
noteE
noteF
noteG

3.6
3.6
3

3
3
3
3

Write cycle
Read cycle
Write cycle
Read cycle

2

10
10
10
10
5
40
5

noteH
note I
note I
note I
note I
note I
note I
note I
note I
note I

1

H·lO

40
5

20

20
4 (tCHCH
4 (tCHCH
4 (tCHCH
4 (tCHCH
4 (tCHCH
4 (tCHCH

4 (tCHCH)
4 (tCHCH)
8 (tCHCH)
8 (tcHCH)
8 (tCHCH)

8 (tCHCH
8 (tCHCH
8 (tCHCH

Il s

10
5

4 (tCHCH)
4 (tCHCH)
4 (tCHCH)
4 (tCHCH)

4 (tCHCH
4 (tCHCH
·'4 (tCHCH

1

10
10
10
10
10

40

20

'* (tCHCH

20
2
50
50

5

14 (tCHCH
14 (tCHCH

8 (tCHCH
8 (tCHCH
8 (tCHCH

20
2
50
50
10
10
10
10
10
10
5

10

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle

2
1
2
1

3

20
2

%

3
3

2

50
50
10

ns

+2.5

1

ICS5300
GENDAC

•
General Operation

NOTES
A.

Full scale error 15 denved from desIgn equahon
{[(F.5.1 ouT) RL - 2.1 (I REF ) RL l/[2.1(JREF)RLli 100%
VBLACK LEVEL =OV F.S.l OUT = Actual full scale measured output

B

R= 37 5Q, IREF = - 8 88mA

C.

Z, = 37.5Q + 30 pF, IREF = - 8 88mA

D.

ThIs parameter 15 the allowed PIxel Clock frequency vanation. It
does not permIt the Pixel Clock penod to vary outside the mimmum
values for PIxel Clock (tCHCH ) period.

E

It 15 reqmred that the color palette's pIxel address be a vahd logIC

level with theappropnate setup and hold hmes at each rising edge
of PCLK (thIs reqmrement includes the blanking penod).
F.

The output delay 15 measured from the 50% pomt of the rismg edge
of CLOCK to the vahd analog output. A valid analog output is
defmed when the analog sIgnal 15 halfway between its successive
values

G.

ThIs applies to dIfferent analog outputs on the same devIce

H

Measured at ± 200 mV from steady state output voltage.

I.

ThIs parameter allows synchrOnization between operations on the
mIcroprocessor interface and the pixel stream being processed by

J.

The followmg speCli1cahons apply for V00= +5V± O.5V, GND=O.
Operatmg Temperature = DOC to 70°C.

K.

Except for SENSE pm.

the color palette.

AC Test Conditions
Input pulse levels ................................................. VDD to 3V
Input rise and fall times 00% to 90%) .......................... 3ns
Digital input timing reference leveL.. ........................ 1.5V
Digital output timing reference leveL.. ..... O.8V and 2.4V

Capacitance
C 1 Digital input. .............................................................. 7pF
Co Digital output.. ......................................................... .7pF
COA Analog output. ...................................................... l0pF
200£2

1.4V

I/O~

I

50 pF (including scope and jig)

DIGITAL OUTPUT LOAD

The ICS5300 GENDAC is intended for use as the analog
output stage of raster scan video systems. It contains a
high-speed Random Access Memory of 256 x 18-bit words,
three 6/8-bit high-speed DACs, a microprocessor / graphic
controller interface, a pixel word mask, on-chip comparators, and two user programmable frequency generators.
An externally generated BLANK* signal can be applied to
pin 39 of the ICS5300. This signal acts on all three of the
analog outputs. The BLANK* signal is delayed internally
so that it appears with the correct relationship to the pixel
bit stream at the analog outputs.
A pixel word mask is included to allow the incoming
pixel address to be masked. This permits rapid changes to
the effective contents of the color palette RAM to facilitate
such operations as animation and flashing objects.
Operations on the contents of the mask register can also
be totally asynchronous to the pixel stream.
The ICS5300 also includes dualPLL frequency generators
providing a video clock (CLKO) and a memory clock
(CLKl), both generated from a single 14.318 MHz crystaL
There are eight selectable CLKO frequencies of which six
are programmable, and a single programmable CLKI
frequency. Default values (Table 1 and Table 2) are
loaded into the appropriate registers on power up.

Video Path
The GENDAC supports four different video modes and
is determined by bits 5-7 of the command register. The
default mode is the 6-bit Pseudo Color mode. The other
modes are the bypass IS-bit, 16-bit and 24 bit True Color.

Pseudo color
In this mode, Pixel Address and BLANK* inputs are
sampled on the rising edge of the clock (PCLK) and any
change appears at the analog outputs after three succeeding rising edges of the clock. The DAC outputs depends
on the data in the color palette RAM.

H-ll

ID

ICS5300
GENDAC

Bypass Modes
The GENDAC supports three different bypass modes; ISbit (S,S,S) mode, 16-bit (S,6,S) mode and the 24-bit True
Color 8-bit DAC mode. In these modes, the pixel address
pins PO-P7 represent the Color Data that is applied directly to the DAC. The internal RAM is bypassed. In the
IS/16-bit mode two consecutive bytes contain the IS/16
bits of color data. Two consecutive rising edges of the
PCLK latch the data on the PO-P7 pins into registers and
the byte framing is internally synchronized with the
rising edge of BLANK*. The internal pipe line delay from
the "first byte" to the DAC is four PCLK rising edges. In
the 24-bit True Color mode, three bytes contains the 24-bit
color data. Three consecutive rising edges of the PCLK
latch the data. The framing is the same as the lS/16-bit
mode. The internal pipe line delay from the "first byte" to
the DAC is five PCLK rising edges.

DAC Outputs
The outputs of the DACs are designed to be capable of
producing 0.7 volt peak white amplitude with an IREF of
8.88 mA when driving a doubly terminated 7S12 load.
This corresponds to an effective DAC output load
(REFFECTIVE) of 37.512.
The formula for calculating IREF with various peak white
voltage/output loading combinations is given below:
VpEAKWHITE
2.1

X

REFFECTIVE

Note that for all values of IREF and output loading:
VBLACK LEVEL = 0
The reference current IREF is determined by the reference
voltage VREF and the value of the resistor connected to
RsET pin. VREF can be the internal band gap reference
voltage or can be overridden by an external voltage. In
both cases IREF =VREF /RsET .

Figure 4 - DAC Set up
The BLANK*inputto the GENDAC acts on all three ofthe
DAC outputs. When the BLANK* input is low, the DACs
are powered down.
The connection between the DAC outputs of the ICSS300
and the RGB inputs of the monitor should be regarded as
a transmission line. Impedance changes along the transmission line will result in the reflection of part of the video
signal back along the transmission line. These reflections
may result in a degradation of the picture displayed by
the monitor.
RF techniques should be observed to ensure good fidelity. The PCB trace connecting the GENDAC to the offboard connector should be sized to form a transmission
line of the correct impedance. Correctly matched RF
connectors should be used for connection from the PCB to
the coaxial cable leading to the monitor and from the
cable to the monitor.
There are two recommended methods of DAC termination: double termination and buffered signal. Each is
described below with its relative merits:
Double Termination (Figure 1)
For this termination scheme, a load resistor is placed at
both the DAC output and the monitor input. The resistor
values should be equal to the characteristic impedance of
the line. Double termination of the DAC output allows
both ends of the transmission line between the DAC
outputs and the monitor inputs to be correctly matched.
The result should be an ideal reflection free system. This
arrangement is relatively tolerant to variations in
transmission line impedance (e.g. a mismatched
connector) since no reflections occur from either end of
the line.

H·12

ICS5300
GENDAC

•
A doubly terminated DAC output will rise faster than any
singly terminated output because the rise time of the
DAC outputs is dependent on the RC time constant of the
load.

)-

ICS5300

MONITOR
R LOAD

R LOAD
GND

T

I

Buffered Signal (Figure 2)
If the GENDAC drives large capacitive loads (for instance
long cable runs), it may be necessary to buffer the DAC
?utputs. The buffer will have a relatively high input
Impedance. The connection between the DAC outputs
and the buffer inputs should also be considered as a
tran~mission line. The buffer output will have a relatively
low Impedance. It should be matched to the transmission
lin~ between it and the monitor with a series terminating
resIstor. The transmission line should be terminated at
the monitor.

GND

1

~
R LOAD

-I-

The ICS5300 has dual PLL frequency generators for generating the video clock (CLKO) and memory clock (CLK1)
needed for graphics subsystems. Both these clocks are
generated from a single 14.318 MHz crystal or can be
driven by an external clock source. The chip includes the
capacitors for the crystal and all the components needed
for the PLL loop filters, minimizing board component
count.

GND

Figure 1 - Double Termination

ICS5300

PLL Clock

There are eight possible video clock, CLKO, frequencies
(fO-f7) which can be selected by the external pins CSOCS2. Pins are software selectable by setting a bit in the PLL
control register. Two of these frequencies (fO-fl) are fixed
and the other six (f2-£7) can be programmed for any
frequency by writing appropriate parameter values to the
PLL parameterregisters. The default frequencies on power
up are commonly used video frequencies (table 1). At
power up, the frequencies can be selected by pins CSOCS2. There is only a single programmable memory clock
frequency (CLK1 ). On power up this frequency defaults
to the frequency given in table 2. The memory clock
transition between frequencies is smooth and glitch free
if the transition is kept between the limits 45-65 MHz.

fn

(MHz)

fO
f1

25.175
28.322

f2
f3
f4
f5

31.500
36.00
40.00
44.889

f6

65.00

£7

75.00

VLCK
Comments

MONITOR

RT
GND

Figure 2 - Buffered Signal

SENSE Output
The GENDAC contains three comparators, one each for
the DAC output (R, G and B) lines. The reference voltage
to the comparators is proportional to the VREF (internal or
external) and is typically 0.33 for VREF =1.23 Volts. When
the voltage on any of these pins go higher than the
reference voltage to the comparators, the SENSE* pin is
driven low. This signal is used to detect the type of(orlack
of) monitor connected to the system.

H-13

VGAO (VGA Color monitor) (fixed)
VGA1 (VGA Monochrome monitor)
(fixed)
VESA 640 x 480 @72 Hz (programmable)
VESA 800 x 600 @56 Hz (programmable)
VESA 800 x 600 @60 Hz (programmable)
1024 x 768 @43 Hz Interlaced
(programmable)
1024 x 768 @ 60 Hz,
640 x 480 Hi-Color @ 72 Hz
(programmable)
VESA 1024 x 768 @ 70 Hz,
True Color 640 x 480 (programmable)

Table 1- Video clock (CLKO) default frequency
register (with a 14.318 MHz input)

III

ICS5300
GENDAC

•
fn

MHz

Writing to the color palette RAM
To set a new color definition, a value specifying a location
in the color palette RAM is first written to the Write mode
Pixel Address register. The values for the red, green and
blue intensities are then written in succession to the Color
Value register. After the blue data is written to the Color
Value register, the new color definition is transferred to
the RAM, and the Pixel Address register is automatically
incremented.

Comments

45.00 MHz Memory and CUI subsystem clock

fA

Table 2 - Memory Clock (CLKl) default frequency
register

Microprocessor Interface
Below are listed the six microprocessor interface registers
within the ICS5300, and the register addresses through
which they can be accessed.

RS2

RSI

RSO

a
a
a
a

a

a

1

1
1

a
1

1

1
1
1
O/HF

a
a
1
1
1

a
a
1

a
1

a

Register Name
Pixel Address (write mode)
Pixel Address (read mode)
Color Value
Pixel Mask
PLL Address (write mode)
PLL Parameter
Command
PLL Address (read mode)
Command Register
accessed by (hidden) flag after
special sequence of events

Writing new color definitions to a set of consecutive
locations in the RAM is made easy by this autoincrementing feature. First, the start address of the set of
locations is written to the write mode Pixel Address
register, followed by the color definition of that location.
Since the address is incremented after each color definition
is written, the color definition for the next location can be
written immediately. Thus, the color definitions for
consecutive locations can be written sequentially to the
Color Value register without re-writing to the Pixel
Address register each time.
Reading from the RAM
To read a color definition, a value specifying the location
in the palette RAM to be read is written to the read mode
Pixel Address register. After this value has been written,
the contents of the location specified are copied to the
Color Value register, and the Pixel Address register
automatically increments.

Table 3 - Microprocessor Interface Registers
Asynchronous Access to Microprocessor Interface
Accesses to all registers may occur without reference to
the high speed timing of the pixel bit stream being
processed by the CENDAC. Data transfers between the
color palette RAM and the Color Value register, as well as
modifications to the Pixel Mask register, are synchronized
to the Pixel Clock by internal logic. This is done in the
period between microprocessor interface accesses. Thus,
various minimum periods are specified between
microprocessor interface accesses to allow the appropriate
transfers or modifications to take place. Access to PLL
address, PLL parameter and to the command register are
asynchronous to the pixel clock.
The contents of the palette RAM can be accessed via the
Color Value register and the Pixel Address registers.

The red, green and blue intensity values can be read by a
sequence of three reads from the Color Value register.
After the blue value has been read, the location in the
RAM currently specified by the Pixel Address register is
copied to the Color Value register and the Pixel Address
again automatically increments. A set of color values in
consecutive locations can be read simply by writing the
start address of the set to the read mode Pixel Address
register and then sequentially reading the color values for
each location in the set. Whenever the Pixel Address
register is updated, any unfinished color definition read
or write is aborted and a new one may begin.

The Pixel Mask Register
The pixel address used to access the RAM through the
pixel interface is the result of the bitwise ANDing of the

H-14

ICS5300
GENDAC

•
incoming pixel address and of the contents of the Pixel
Mask register. This pixel masking process can be used to
alter the displayed colors without altering the video
memory or the RAM contents. By partitioning the color
definitions by one or more bits in the pixel address, such
effects as rapid animation, overlays, and flashing objects
can be produced.
The Pixel Mask register is independent of the Pixel Address
and Color Value registers.

The Command Register
The Command register is used to select the various GENDAC color modes and to set the power down mode. On
power up this register defaults to an 6-bit Pseudo Color
mode. This register can be accessed by control pins RS2RSO, or by a special sequence of events for graphics
subsystems that do not have the control signal RS2. For
graphic systems that do not have RS2, this pin is tied low
and an internal flag (HF; Hidden Flag) is set when the
pixel mask register is read four times consecutively. Once
the flag is set, the following Read or Write to the pixel
mask register is directed to the command register. The
flag is reset for Read or Write to any register other than the
pixel mask register. The sequence has to be repeated for
any subsequent access to the command register.

The PLL Parameter Register
The CLKO and CLKI of the ICS5300 can be programmed
for different frequencies by writing different values to the
PLL parameter register bank. There are eight registers in
the parameter register; seven are two bytes long and one
(OE) is one byte long.

Writing to the PLL parameter register
To write the PLL parameter data, the corresponding
address location is first written to the PLL address register. For software compatibility with other chips, two
address registers are defined; the Write mode PLL address register and the Read mode PLL address register.
They are actually a single Read/Write register in the
ICS5300. The next PLL parameter write will be directed to
the first byte of the address location specified by the PLL
address register. The next Write to the parameter register

will automatically be to the second byte of this register. At
the end of the second Write the address is automatically
incremented. For the one byte "OE" register the address
location is incremented after the first byte Write. If this
frequency is selected while programming, the output
frequency will change at the end of the second Write.
Reading the PLL parameter register
To read one of the registers of the PLL parameter register
the address value corresponding to the location is first
written to the PLL address register. The next PLL parameter read will be directed to the first byte of the address
location pointed by this index register. A next Read of the
parameter register will automatically be the second byte
of this register. At the end of the second Read, the address
location is automatically incremented. The address register (OE) is incremented after the first byte Read.

Power Down Mode
When bit 0 in the Command register is high (set to 1) , the
GENDAC enters the DAC power down mode. The DACs
are turned off, and the data is retained in the RAM. It is
possible to access the RAM, in which case the current will
temporarily increase. While the RAM is being accessed,
the current consumption will be proportional to the speed
of the clock. There is no effect on either clock generator
while in this mode.

Power Supply
As a high speed CMOS device, the ICS5300 may draw
large transient currents from the power supply, it is
necessary to adopt high frequency board layout and
power distribution techniques to ensure proper operation of the GENDAC. Please refer to the suggested layout
on page 29.
To supply the transient currents required by the ICS5300,
the impedance in the decoupling path should be kept to
a minimum between the power supply pins VDD and
GND. It is recommended that the decoupling capacitance
between VDD and GND should be a O.lJ..lF high frequency
capacitor, in parallel with a large tantalum capacitor with

H-15

III

ICS5300
GENDAC

•
a value between 221lF and 471lF. A ferrite bead may be
added in series with the positive supply to form a low
pass filter and further improve the power supply local to
the GENDAC. It will also reduce EM!.
The combination of series impedance in the ground supply
to the GENDAC, and transients in the current drawn by
the device will appear as differences in the GND voltages
to the GENDAC and to the digital devices driving it. To
minimize this differential ground noise, the impedance in
the ground supply between the GENDAC and the digital
devices driving it should be minimized.

Digital Output Information
The PCB trace lines between the outputs of the TTL
devices driving the GENDAC and the input to the
GENDAC behave like low impedance transmission lines
driven from a low impedance transmission source and
terminated with a high impedance. In accordance with
transmission line principles, signal transitions will be
reflected from the high impedance input to the device.
Similarly, signal transitions will be inverted and reflected
from the low impedance TTL output. Line termination is
recommended to reduce or eliminate the ringing, particularly the undershoot caused by reflections. The termination may either be series or parallel.
Series termination is the recommended technique to use.
It has the advantages of drawing no DC current and of
using fewer components. Series termination is accomplished by placing a resistor in series with the signal at the
output of the TTL driver. This matches the TTL output
impedance to that of the transmission line and ensures
that any signal incident on the TTL output is not reflected.
To minimize reflections, some experimentation will have
to be done to find the proper value to use for the series
termination. Generally, a value around lOOn will be
required. Since each design will result ina different signal
impedance, a resistor of a predetermined value may not
properly match the signal path impedance. Therefore, the
proper value of resistance should be found empirically.

H-16

ICS5300
GENDAC

•
Functional Description

Power Down Mode of RAMDAC
When this bit is set to 0 (default is 0), the device
operates normally. If this bit is set to 1, the
power and clock to the Color Palette RAM and
DACs are turned off. The data in the Color
Palette RAM are still preserved. The CPU can
access without loss of data by internal automatic clock start/stop control. The DAC outputs become the same as BLANK* (sync) level
output during power down mode. This bit
does not effect the PLL clock synthesizer function.

Bit 0

This section describes the register address and bit definition for RAMDAC and the Frequency Synthesizer sections.

Color Palette
Command Register
(RSO-RS2 = 011)
(RSO-RS1 = 01 with hidden flag)

By setting bits in the command register the ICSS300 can be
programmed for different color modes and can be powered down for low power operation.
S
7
6
Color Mode
1
2
0

4

3
2
1
Reserved
Should all =0

0
Snooze

Table 3 - Command Registers
Bit 7-5

Color Mode Select
These three bits select the Color Mode of
RAMDAC operation as shown in the following
table 4 (default is 0 at power up):

Color Modes
The four selectable color modes are described here.
Mode 0: 8-bit Pseudo Color (one clock per pixel). This
mode is the 8-bit per pixel Pseudo Color mode. In this
mode. inputs PO-P7 are the pixel address for the color
palette RAM and are latched on the rising edge of every
PCLK. This is the default mode on power up and it is
selected by setting bits CR7-CRS to 000. There are three
clock cycles pipe line delays from input to DAC output.
8-bit Pseudo Color mode

Bit 4 - 1 (Reserved)

7

6

S

DATA BYTE
2
4
3

o

7

6

S

PIXEL ACCESS
4
3
2

o

CM2
(CR7)

CMl
(CR6)

CMO
(CR5)

0
0
0
0

0
0
1
1

0
1
0
1

6-Bit Pseudo Color with Palette (Default)
IS-Bit Direct Color with Bypass (Hi-Color)
24-Bit True Color with Bypass (True Color)
16-Bit Direct Color with Bypass (XGA)

1
2
3
2

1
1
1
1

0
0
1
1

0
1
0
1

IS-Bit Direct Color with Bypass (Hi-Color)
IS-Bit Direct Color with Bypass (Hi-Color)
16-Bit Direct Color with Bypass (XGA)
24-Bit True Color with Bypass (True Color)

2
2
2
3

Color Mode

Table 4 - Color Mode Select

H-17

Clock Cycles!
Pixel Bits

II

ICS5300
GENDAC

Mode 1: (IS-bit per color bypassHi-Color mode).
This mode is the IS-bit per pixel bypass mode. In this
mode, inputs PO-P7 are the color DATA and are input
directly to the DAC, bypassing the color palette. The two
bytes of data is latched in two successive PCLK rising
edges. ICSS300 supports only the two clock mode and
does not support the mode where the data are latched on
the rising and the falling edges. For compatibility, the IS /
16 one clock modes are selected as two clock modes in this
chip. The low-byte, high byte synchronization is internally
done by the rising edge of BLANK*. Each color is S-bit
wide and is packed into two bytes as shown below. The
mode is selected by setting bits CR7-CRS to 001, 100 or
101.

Mode 3: (24-bit per pixel True Color Mode).
This mode is the 24-bit per pixel bypass mode. The three
bytes of data are latched on three successive PCLK edges
and the first byte is synchronized by the rising edge of
BLANK*. In this mode, each of the colors are 8-bit wide
and the DAC is an 8-bit wide DAC. The first byte is blue
followed by green and red. This mode can be selected by
setting bits CR7-CRS to 010 or 111. The DAC outputs
changes every three cycles and the pipeline delay from
the first byte to output is five cycles.
24-bit color mode
THIRD BYTE

IS-Bit Color Mode
3LSB = set to zero

BLUE

Frequency Generators

xl7 6 54 13 7 6 5 4 317 6 5 4 3
GREEN

BLUE

Mode 2: (16-bit per pixel bypass XGA mode).
This mode is the 16-bit per pixel bypass mode and the POP7 inputs to go to the DAC directly, bypassing the color
palette. The 2 bytes data is latched on two successive
rising edges and the low-byte, high-byte synchronization
is internally done by the rising edge of BLANK*. In this
mode, blue and red colors are 6 bits wide and green is S
bits wide. The 2 bytes of data is packed as shown below.
The mode is selected by setting bits CR7-CRS to Ollar
110.

The ICSS300 clock synthesizer can be reprogrammed
through the microprocessor interface for any set of
frequencies. This is done by writing appropriate values to
the PLL Parameter Register Bank (table S).

PLL Address Registers
The address of the parameter register is written to the
PLL address registers before accessing the parameter
register. This register is accessed oy register select pins
RS2-RSO = 100 or 111.
6 S 4 3 2 1 0
PLL REGISTER ADDRESS
7 6 S 4 3 2 1 0

7

16-Bit color mode
2LSB = set to zero (green)
3LSB = set to zero (blue, red)
SECOND BYTE

FlRSTBYTE

pppppppp pppppppp
76543210 7 6 5 4 321 0

765 4317 6 543
RED

GREEN

FIRST BYTE

pppppppp PPPPPPPP
7 6 5 432 1 0 7 6 543 2 1 0
RED

FIRST BYTE

7 6 5 4 3 210 7 6 5 4 3 2 1 0 7 6 543 2 1 0
RED

SECOND BYTE

SECOND BYTE

pppppppp pppppppp PPPPPPPP
7 6 5 4 321 0 7 6 5 4 3 2 1 o 7 6 5 4 3 2 1 0

GREEN

2~

6 5 4 3
BLUE

PLL Parameter Register
There are sixteen registers in the PLL parameter register
(table S). Registers 00 to 07 are for the CLKO selectable
frequency list, Register OA for CLK1 programmable frequency and register OE is the PLL CLKO control register.

H-18

ICS5300
GENDAC

•
Index

RIW

Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

R/R/R/W
R/W
R/W
R/W
R/W
R/W
R/R/R/W
R/R/R/R/W
R/-

CLKO fO PLL Parameters
CLKO fl PLL Parameters
CLKO f2 PLL Parameters
CLKO f3 PLL Parameters
CLKO f4 PLL Parameters
CLKO f5 PLL Parameters
CLKO f6 PLL Parameters
CLKO f7 PLL Parameters
(Reserved) = 0
(Reserved) = 0
CLKlfAPLL
(Reserved) = 0
(Reserved) = 0
(Reserved) = 0
PLL Control Register
(Reserved) = 0

PLL Data Registers
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(1-byte)
(2-byte)

The CLKO and CLKI input frequency is deternimed by
the parameter values in this register. These are two bytes
registers; the first byte is the M-byte and the second is the
N-byte.
M-Byte PLL Parameter Input
The M-byte has a 7-bit value (1-127) which is the feedback
divider of the PLL.
7
6
Reserved
=0
X

432
M-Divider Value
X X X X
X

o
X

N-Byte PLL Parameter Input
The N-byte has two values. Nl sets a 5-bit value (1-31) for
the input pre scalar and N2 is a 2-bit code for selecting 1,
2,4, or 8 post divide clock output.

Table 5 - PLL Parameter Registers

7
5
6
Reserved N2-Code
X X
=0

PLL Control Register
Bits in this register determine internal or external CLKO
select.
7
5
3
2
0

N2 code
00
01
10
11

Enable Internal Clock Select CINCS) for CLKO.
When this bit is set to 1, the CLKO output
frequency is selected by bit 2 - 0 in this register.
External pins CSO - CS2 are ignored.

Bit 4 - 3 (Reserved).
Bit 2 - 0 Internal Clock Select for CLKO CINCS).
These three bits selects the CLKO output frequency if bit 5 of this register is on. They are
interpreted as an octal number, n, that selects
fn. Default selects fo.

4

3
2
1 0
NI-Divider Value
X X X X X

N2 Post Divide Code

Bit 7 - 6 Reserved.
Bit 5

5

Divider
1
2
4
8

The block diagram of the PLL clock synthesizer is given
in following figure 3.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
(M+2) x Fref
Fout ~---(Nl+2) X2N2
M and N values should be programmed such that the
frequency of the VCO is within the optimum range for
duty cycle, jitter and glitch free transition. Optimum duty
cycle is achieved by programming N2 for values greater
than one. See the following page for programming example.

H-19

III

ICS5300
GENDAC

•
3. 60 MHz S; (M+2)fREF
(Nl+2)

Programming Example
Suppose an output frequency of 25.175 MHz is desired.
The reference crystal is 14.318 MHz. The VCO should be
targeted to run in the 100 to 180 MHz range, so choosing
a post divide of 4 gives a VCO frequency of :
4 X 25.175=101.021 MHz

S;

270 MHz

This is the VCO frequency. In general, the VCO
should run as fast as possible, because it has lower jitter
at higher frequencies. Also, running the VCO at multiples of the desired frequency allows the use of output
divides, which tends to improve the duty cycle.

From the table on page 17, we find N2 = 2
Substituting F,ef = 14.318 and 2N2 = 4 into the equation on
page 17:

4. fCLKO and feLK! S; 135 MHz
This is the output frequency.

( 25.175).4= (M+2)
14.318
(Nl + 2)

These rules lead to the following procedure for determining the PLL parameters, assuming rules 1 and 4 are
satisfied.

by trial and error:
( 25.175) . 4 ~
14.318
so

A. Determine the value of N2 (either 1, 2, 4 or 8) by
selecting the highest value of N2, which satisfies the
condition
N2* fCLK S; 270 MHz

127
18

M + 2 = 127
Nl + 2 = 18

M = 125
Nl = 16

so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = 0 & N2 code & Nl = 0 & 1 0 & 1 0 0 0 0
N=01010000b

Additional Information on Programming the
Frequency Generator section of the GENDAC
When programming the GENDAC PLL parameter registers, there are many possible combinations of parameters
which will give the correct output frequency. Some
combinations are better than others, however. Here is a
method to determine how the registers need to be set:
The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
1. 2 MHz < fREF < 32 MHz
This refers to the input reference frequency. Most
users simply connect a 14.318 MHz crystal to the crystal
inputs, so this is not a problem.
2. 600 kHz < fREF S; 8 MHz
(N1+2)
This is the frequency input to the phase detector.

B. Calculate

(M2+)
2N2fout
(Nl+2) =
fref

C. Now (M+2) and (Nl+2) must be found by trial and

error. With a 14.318 MHz reference frequency, there will
generally be a small output frequency error due to the
resolution limit of (M+2) and (Nl +2). For a given frequency tolerance, several different (M+2) and (Nl+2)
combinations can usually be found. Usually, a few
minutes trying out numbers with a calculator will produce a workable combination. Multiplying possible
values of (Nl +2) by the desiredratio will indicate approximately the value of M. This method is shown in the
example below. A program could be written to try all
possible combinations of (M+2) and (Nl +2) (3937 possible combinations), discard those outside error band
and select from those remaining by giving preference t~
ratios which use lower values of (M+2). Lower values of
(M+2) and (Nl+2) provide better noise rejection in the
phase locked loop.
Example: Suppose we are using a 14.318 MHz reference
crystal and wish to output a frequency of 66 MHz with an
error of no greater than 0.5%. What are the values of the
PLL data registers?

H·20

ICS5300
GENDAC

II
A. 66*8 = 528 > 250 VCO speed too high
66*4 = 264 > 250 VCO speed too high
66*2 = 132 < 250 VCO speed OK, N2 = 2, N2 code =
01 from table on page 17 of the data sheet.

B. 132/14.31818 = 9.219
This is the desired frequency multiplication ratio.
C. Setting (Nl+2) = 3, 4,. .. 12, 13 and performing some

simple calculations yields the following table:
(Note that Nl cannot be 0)

(Nl+2)

(Nl+2)*9.219

rounded (=M+2)

Actual Ratio

Percent Error

3
4
5
6
7
8
9
10
11
12
13

27.657
36.876
46.095
55.314
64.533
73.752
82.971
92.19
101.409
110.628
119.847

28
37
46
55
65
74
83
92
101
111
120

9.33
9.25
9.20
9.17
9.29
9.25
9.22
9.20
9.18
9.25
9.23

-1.23
-0.34
0.21
0.57
-0.72
-0.34
-0.03
0.21
0.40
-0.34
-0.13

The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2)
= 83; M = 81. The M-byte PLL parameter word is simply
81 in binary, plus bit 7 (which must be set to 0), or
01010001. The N-byte PLL parameter word is N2 code
(01) concatenated with 5 bits of N2 in binary (00111), or
00100111. Once again, bit 7 must be zero.

We have chosen the combination with the least frequency
error, but several other combinations are within the 0.5%
tolerance. Because the lowest value of (M+2) offers the
best damping, the 37/4 combination will have the best
power supply rejection. This results in lower jitter due to
external noise.

N2
CNTR

IF

r--!
Oll

Figure 3 - PLL Clock Synthesizer Block Diagram

CS2
0
0
0
0
1
1
1
1

External Select
CSI
0
0
1
1
0
0
1
1

(Internal Select PLL Control Register)
CSO
BIT 2
BIT 1
0
0
0
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
Video Clock Selection Table

H-21

BIT 0
0
1
0
1
0
1
0
1

CLK 0 Frequency
fO
f1
f2
f3
f4
f5
f6
f7

ICS5300
GENDAC

II
PLCK
Poop?

BLUE

System Timing - Pseudo Color, Mode 0

PLCK

PooP?

BLANK'

RED

GREEN

BLUE

c

~BLANK---BLANKJ

C~BLANK---BLANKJ
C

LBLANK---BLANK~

Detailed Timing Specifications - Pseudo Color, Mode 0

H·22

ICS5300
GENDAC

II
PCLK

BLANK

PO-P7

~___A-----J~B--

DAC-RD

DAC-GR
DAC-BL

________________________________~~A~B__________________________________________-4-J~A~---J~B­
System Timing Bypass - 15 (5/5/5) and 16 (5/615) Modes 1, 2

Ons

25ns

°DAC-BL _____________________________/

\..'-______

~r

DAC-GR-----------------------------f----------~--------'~
DAC-RD _____________________________/r---AA.----"'----....
B,.---..J~

System Timing Bypass True Color 24 (8,8,8) Mode 3

H·23

ICS5300
GENDAC

•
,---tWLWH-

WR*

RSO-RS1

00-07

I tWLSX

t SVWl. 1

I

X
'I

I

..

,

.~

"

tDvw~l,

I

JtWHDX

I: ,

X
1

I

Basic Write Cycle Timing

RO*

RSO-RS1

00-07

Basic Read Cycle Timing

tWHWl1

\

1'------

WR*

RD*

'-'nL

RSO

n

I' X

XJ

n

I;>X

XJ

RS1

LJ

c=J

XJ

LJ.

\iZJ

(]

"

"

Write to Pixel Mask Register Followed by Read

Write to Pixel Mask Register Followed by Write

t RHRl1

WR*

\

\

I~

RD*

'""~'rt=

Read from Pixel or Pixel Address Register
(Read or Write) followed by Write

Read from Pixel or Pixel Address Register
(Read or Write) followed by Read

H-24

•

ICS5300
GENDAC

WR*

RD*

~"·-'t=

RSO

RS1

RS2

DO-D7

V
V

'\

7
7

~

/

\

'\

'\
'\
/

- - - \ ADDRESS 'j-------\ADDRESS +1 )}-~~~~~~~~~~~~-

WR*

RD*

RSO

RS1

~

.~

L
L
L

~

RS2

~

DO-D7

~

ADDRESS

~

\

H

L
L
L

I
I

ADDRESS

)}-~~~~~~~~~~~~­

Write and Read Back Pixel Address Register (Write Mode)

WR*

RD*

RSO

RS1
RS2

/
/
\

/ '\
c=J c=J \
'\ .. ~ / . \ l \ L 7 '\
/ . \ ~ ~ I ./ \
\

/

DO-D7

Read Color Value then Pixel Address Register (Read Mode)

H-25

:

ICS5300
GENDAC

•
WR'

-U' ,~, 'U' '-' LJ '-'1 "~
•

IWHRL2

L

RO'

\;

V

RSO

~

L~,;:

RS1

~

~

F

RS2

~

L,',:\

/

00-07

"

cc/

,

"
'c

ADDRESS

7

\'

\

/

\

I

RED

,
"

,

"

,

/

\

\

l

\

L

GREEN

'X=:=XJ

"

,

'X:=:X=J
x=x:J

BLUE

Color Value Write followed by any Read

WR'~'

IWHWL1

U

.-

-.

U

I W HWL1

"-

-.

IWHWL1
h

U

IWHWL2
-.

L

0-

RO'

\' 7

RSO

~

RS1

~

k:, 'f:\

~

It! :;~:'1

RS2

00-07

/,

',' , i i '

\

A/ ' j \

ADDRESS )------{

RED

\ '/
k\

\,CJC]

fA, "', , ',-\'.

[>;:~

-:,.;'

"

/

) - - - - - \ GREEN ) - - - - - \

Color Value Write followed by any Write

H-26

<",,"EJC]

BLUE

ICS5300
GENDAC

•
WR*

RO*

RSO

V

'\

7

'\

/

\

RS1

V

'\

\

t

\

/:

~

L

\

L

:\

RS2

00-07

ADDRESS

"r

"
'0

:

c~

RED

\

\

I

\

L ::;;'~~

"

L..~~

,

1!

"

GREEN

>;~:"~
"

'!"',,'~

BLUE

Color Value Read followed by any Read

III

WR*

RO*

RSO

V

'\

RS1

V

\:

RS2

~

L

00-07

"

ADDRESS

7

'\

\

t

~\

\

L

\

7

RED

\

:

/:

l

'/

\/Al

:

\

//:~~:~

\

L

GREEN

Color Value Read followed by any Write

H-27

,"

:,

':,,~

;J ;:~

BLUE

ICS5300
GENDAC

•
WR*

RO*

L-f"

t WHRL3

t=

l
l

/

\

/

\

RS2

V

'\ ~

7

00-07

- - - \ ADDRESS

RSO

RS1

)------<.,

/

I
\',' ~
ADDRESS ) } - - - - - - - - - - - - - -

Write and Read back Pll Address Register (Write Mode)

WR*

L-{"

t WHRL3

t=

RO*

RSO

V

'\

7

\

RS1

V

'\

)

\

RS2

V

\

7

\

00-07

- - - \ ADDRESS)------<" ADDRESS ) } - - - - - - - - - - - - - -

,','

"

I
I

Write and Read back PlL Address Register (Read Mode)

H-28

ICS5300
GENDAC

•
WR'

RO'

~"'-=

RSO

u

RS1

u

RS2

u

00-07 _ _-{

\

"lFLFLtl------

\

PLL ADDRESS

Read Two bytes PLL Register then PLL Address Register

WR'

~" '-"lAJ1I----+--H---+--L

RO'

RSO

LJ \

/

RS1

LJ \
LJ \

\ ~ ~

RS2

00-07 -----\

/

"----------J "----------J
"----------J

ADDRESS~
Read One Byte PLL Register then PLL Address Register

H-29

-

III

ICS5300
GENDAC

II

The ground plane is continuous, but the power plane is separated into analog and digital sections as shown. Power is
supplied to the analog power plane through the ferrite bead,
and bypassed at the power entry point by C3, a 10 JlF tantalum
capacitor. These high current connections should have multiple vias to the ground and power planes, if possible. Power
connections should be connected to the analog or digital power
plane, as shown in the diagram. Power pins 5 and 29 should be
connected to digital power, power pins 20 and 24 to analog
power. Decoupling capacitors (indicated by CI) should be
placed as close to the GENDAC as possible.

Monitor SENSE Signal
RED,
GREEN,
BLUE

/

/

335V

'soD
SENSE

"'The high performance of which the ICS5300 GENDAC is
capable is dependent on careful PC board layout. The use of
a four layer board (internal power and ground planes, signals
on the two surface layers) is recommended. The layout below
shows a suggested configuration.

The analog and digital I/O lines are not shown. Analog signals
(DAC outputs, Vref, Rset) should only be routed above the
analog power plane. Digital signals should only be routed
above the digital power plane.

Recommended Layout

c::x>c:J
Cl

DIGITAL Power
Plane

Cl
+

Yl

100 mil Separation

40
41
42

43
44

c:::::J-OC:J
Cl

Cl

0

+

0_

0+
CI
C2
C3

FBI
RI

Yl

1
2
3
4
5
6

ICS5300

VIA to ground plane
VIA to power plane

,01 uf chip capacitor
,1uf chip capacitor

C2

lOuf tantulum capacitor
Ferrite Bead
140 ohm 1% resistor
14.318 Mhz parallel resonant crysal cut for C L=12

B-30

C3

ICS5300
GENDAC

Ordering Information
ICS5300V
Example:

TT~'----Pae~~
ICS

_
L..-_ _ _ _ _ Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - Pref"1X

ICS, AV =Standard Device; GSP=Genlock Device

H-31

H·32

ICS5301
GENDAC

Integrated
Circuit
Systems, Inc.

•

8-Bit Integrated Clock-LUT-DAC
General Description

Features

The ICSS301 GENDAC is a combination of dual programmable clock generators, a 256 x IS-bit RAM, and a triple
S-bit video DAC. The GENDAC supports S-bit pseudo
color applications, as well as IS-bit, 16-bit and 24-bit True
Color bypass for high speed, direct access to the DACs.

• Designed for compatibility with Tseng Labs VGA
controllers
• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, 15, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixel) clock
frequencies (CLKO)
• One programmable memory (controller) clock
frequency (CLK1)

The RAM makes it possible to display 256 colors selected
from a possible 262, 144 colors. The dual clock generators
use Phase Locked Loop (PLL) technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains S frequencies, 6 of
which are programmable by the user. The memory clock
has one programmable frequency location.
The three S-bit DACs on the ICS5301 are capable of
driving singly or doubly-terminated 750 loads to nominalO - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather
than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock)
generation for graphics, using patented techniques to
produce low jitter video timing.

•
•
•
•
•
•

DAC power down in blanking mode
Low power operation
Anti-sparkle circuitry
On-chip loop filters reduce external components
Standard CPU interface
Single external crystal (typically 14.318 MHz)

• Monitor Sense
• Internal voltage reference
• 135 MHz (-3),110 MHz (-2) & 80 MHz (-1)
versions
• Very low clock jitter

Block Diagram

SENSE'
RED
GREEN

PO-P7

BLUE

L...._J"O<""--RESET

VREF

~PCLK

DO-D7

~-

RSO

+-----------------------------------------~CLKO

·~----------------------------------------~CLKl

H-33

ICS5301
GENDAC

Pin Configuration
"'l!)"d

RS

R LOAD
GND

PLL Clock
The ICS5301 has dual PLL frequency generators for generating the video clock (CLKO) and memory clock (CLK})
needed for graphics subsystems. Both these clocks are
generated from a single 14.318 MHz crystal or can be
driven by an external clock source. The chip includes the
capacitors for the crystal and all the components needed
for the PLL loop mters, minimizing board component
count.
There are eight possible video clock, CLKO, frequencies
(fO-£7) which can be selected by the external pins CSOCS2. Pins are software selectable by setting a bit in the PLL
control register. Two of these frequencies (fO-fl) are fixed
and the other six (f2-£7) can be programmed for any
frequency by writing appropriate parameter values to the
PLL parameter registers. The default frequencies on power
up are commonly used video frequencies (table 1). At
power up, the frequencies can be selected by pins CSOCS2. There is only a single programmable memory clock
frequency (CLK1 ). On power up this frequency defaults
to the frequency given in table 2. The memory clock
transition between frequencies is smooth and glitch free
if the transition is kept between the limits 45-65 MHz.

MONlTOR

fn

(MHz)

fO
f1

50.350
56.644

f2
f3
f4
f5

31.500
36.00
40.00
44.889

f6

65.00

f7

75.00

Rr

1

GND

Figure 2 - Buffered Signal

SENSE Output
The GENDAC contains three comparators, one each for
the DAC output (R, G and B) lines. The reference voltage
to the comparators is proportional to the VREF (internal or
external) and is typically 0.33 for VREF = 1.23 Volts. When
the voltage on any of these pins go higher than the
reference voltage to the comparators, the SENSE* pin is
driven low. This signalis used to detectthe type of (or lack
of) monitor connected to the system.

H-43

VLCK
Comments

VGAO (VGA Color monitor) (fixed)
VGA1 (VGA Monochrome monitor)
(fixed)
VESA 640 x 480 @72 Hz (programmable)
VESA 800 x 600 @56 Hz (programmable)
VESA 800 x 600 @60 Hz (programmable)
1024 x 768 @43 Hz Interlaced
(programmable)
1024 x 768@60Hz,
640 x 480 Hi-Color @ 72 Hz
(programmable)
VESA 1024 x 768@ 70 Hz,
True Color 640 x 480 (programmable)

Table 1 - Video clock (CLKO) default frequency
register (with a 14.318 MHz input)

III

ICS5301
GENDAC

MCLK(fA}

Comments

45.00 MHz

Memory and CUI subsystem clock
Smooth transition between 45-65 MHz

Writing to the color palette RAM
To set a new color definition, a value specifying a location
in the color palette RAM is first written to the Write mode
Pixel Address register. The values for the red, green and
blue intensities are then written in succession to the Color
Value register. After the blue data is written to the Color
Value register, the new color definition is transferred to
the RAM, and the Pixel Address register is automatically
incremented.

Table 2 - Memory Clock (CLKl) Default Frequency
Register

Microprocessor Interface
Below are listed the six microprocessor interface registers
within the ICS5301, and the register addresses through
which they can be accessed.
RS2

RSI

RSO

0
0
0
0
1
1
1
1
O/HF

0
1
0
1
0
0
1
1
1

0
1
1
0
0
1
0
1
0

Register Name
Pixel Address (write mode)
Pixel Address (read mode)
Color Value
Pixel Mask
PLL Address (write mode)
PLL Parameter
Command
PLL Address (read mode)
Command Register
accessed by (hidden) flag after
special sequence of events

Writing new color definitions to a set of consecutive
locations in the RAM is made easy by this autoincrementing feature. First, the start address of the set of
locations is written to the write mode Pixel Address
register, followed by the color definition of that location.
Since the address is incremented after each color definition
is written, the color definition for the next location can be
written immediately. Thus, the color definitions for
consecutive locations can be written sequentially to the
Color Value register without re-writing to the Pixel
Address register each time.
Reading from the RAM
To read a color definition, a value specifying the location
in the palette RAM to be read is written to the read mode
Pixel Address register. After this value has been written,
the contents of the location specified are copied to the
Color Value register, and the Pixel Address register
automatically increments.

Table 3 - Microprocessor Interface Registers
Asynchronous Access to Microprocessor Interface
Accesses to all registers may occur without reference to
the high speed timing of the pixel bit stream being
processed by the GENDAC. Data transfers between the
color palette RAM and the Color Value register, as well as
modifications to the Pixel Mask register, are synchronized
to the Pixel Clock by internal logic. This is done in the
period between microprocessor interface accesses. Thus,
various minimum periods are specified between
microprocessor interface accesses to allow the appropriate
transfers or modifications to take place. Access to PLL
address, PLL parameter and to the command register are
asynchronous to the pixel clock.
The contents of the palette RAM can be accessed via the
Color Value register and the Pixel Address registers.

The red, green and blue intensity values can be read by a
sequence of three reads from the Color Value register.
After the blue value has been read, the location in the
RAM currently specified by the Pixel Address register is
copied to the Color Value register and the Pixel Address
again automatically increments. A set of color values in
consecutive locations can be read simply by writing the
start address of the set to the read mode Pixel Address
register and then sequentially reading the color values for
each location in the set. Whenever the Pixel Address
register is updated, any unfinished color definition read
or write is aborted and a new one may begin.

The Pixel Mask Register
The pixel address used to access the RAM through the
pixel interface is the result of the bitwise ANDing of the

H-44

ICS5301
GENDAC

•
incoming pixel address and of the contents of the Pixel
Mask register. This pixel masking process can be used to
alter the displayed colors without altering the video
memory or the RAM contents. By partitioning the color
definitions by one or more bits in the pixel address, such
effects as rapid animation, overlays, and flashing objects
can be produced.
The Pixel Mask register is independent of the Pixel Address
and Color Value registers.

The Command Register
The Command register is used to select the various GENDAC color modes and to set the power down mode. On
power up this register defaults to an 6-bit Pseudo Color
mode. This register can be accessed by control pins RS2RSO, or by a special sequence of events for graphics
subsystems that do not have the control signal RS2. For
graphic systems that do not have RS2, this pin is tied low
and an internal flag (HF; Hidden Flag) is set when the
pixel mask register is read four times consecutively. Once
the flag is set, the following Read or Write to the pixel
mask register is directed to the command register. The
flag is resetfor Read or Write to any register other than the
pixel mask register. The sequence has to be repeated for
any subsequent access to the command register.

The PLL Parameter Register
The CLKO and CLKI of the ICS5301 can be programmed
for different frequencies by writing different values to the
PLL parameter register bank. There are eight registers in
the parameter register; seven are two bytes long and one
(OE) is one byte long.

Writing to the PLL parameter register
To write the PLL parameter data, the corresponding
address location is first written to the PLL address register. For software compatibility with other chips, two
address registers are defined; the Write mode PLL address register and the Read mode PLL address register.
They are actually a single Read/Write register in the
ICS5301. The next PLL parameter write will be directed to
the first byte of the address location specified by the PLL
address register. The next Write to the parameter register

will automatically be to the second byte of this register. At
the end of the second Write the address is automatically
incremented. For the one byte "OE" register the address
location is incremented after the first byte Write. If this
frequency is selected while programming, the output
frequency will change at the end of the second Write.
Reading the PLL parameter register
To read one of the registers of the PLL parameter register
the address value corresponding to the location is first
written to the PLL address register. The next PLL parameter read will be directed to the first byte of the address
location pointed by this index register. A next Read of the
parameter register will automatically be the second byte
of this register. Atthe end of the second Read, the address
location is automatically incremented. The address register (DE) is incremented after the first byte Read.

Power Down Mode
When bit ain the Command register is high (set to 1) , the
GENDAC enters the DAC power down mode. The DACs
are turned off, and the data is retained in the RAM. It is
possible to access the RAM, in which case the current will
temporarily increase. While the RAM is being accessed,
the current consumption will be proportional to the speed
of the clock. There is no effect on either clock generator
while in this mode.

Power Supply
As a high speed CMOS device, the ICS5301 may draw
large transient currents from the power supply, it is
necessary to adopt high frequency board layout and
power distribution techniques to ensure proper operation of the GENDAC. Please refer to the suggested layout
on page 29.
To supply the transient currents required by the ICS5301,
the impedance in the decoupling path should be kept to
a minimum between the power supply pins VDD and
GND. It is recommended that the decoupling capacitance
between VDD and GND should be a O.lIlF high frequency
capacitor, in parallel with a large tantalum capacitor with

H-45

ID

ICS5301
GENDAC

a value between 221lF and 471lF. A ferrite bead may be
added in series with the positive supply to form a low
pass filter and further improve the power supply local to
the GENDAC. It will also reduce EM!.
The combination of series impedance in the ground supply
to the GENDAC, and transients in the current drawn by
the device will appear as differences in the GND voltages
to the GENDAC and to the digital devices driving it. To
minimize this differential ground noise, the impedance in
the ground supply between the GENDAC and the digital
devices driving it should be minimized.

Digital Output Information
The PCB trace lines between the outputs of the TTL
devices driving the GENDAC and the input to the
GENDAC behave like low impedance transmission lines
driven from a low impedance transmission source and
terminated with a high impedance. In accordance with
transmission line principles, signal transitions will be
reflected from the high impedance input to the device.
Similarly, signal transitions will be inverted and reflected
from the low impedance TTL output. Line termination is
recommended to reduce or eliminate the ringing, particularly the undershoot caused by reflections. The termination may either be series or parallel.
Series termination is the recommended technique to use.
It has the advantages of drawing no DC current and of

using fewer components. Series termination is accomplished by placing a resistor in series with the signal at the
output of the TTL driver. This matches the TTL output
impedance to that of the transmission line and ensures
that any signal incident on the TTL output is not reflected.
To minimize reflections, some experimentation will have
to be done to find the proper value to use for the series
termination. Generally, a value around lOon will be
required. Since each design will result in a different signal
impedance, a resistor of a predetermined value may not
properly match the signal path impedance. Therefore, the
proper value of resistance should be found empirically.

H-46

ICS5301
GENDAC

•
Functional Description

Power Down Mode of RAMDAC
When this bit is set to 0 (default is 0), the device
operates normally. If this bit is set to 1, the
power and clock to the Color Palette RAM and
DACs are turned off. The data in the Color
Palette RAM are still preserved. The CPU can
access without loss of data by internal automatic clock start/stop control. The DAC outputs become the same as BLANK* (sync) level
output during power down mode. This bit
does not effect the PLL clock synthesizer function.

Bit 0

This section describes the register address and bit definition for RAMDAC and the Frequency Synthesizer sections.

Color Palette
Command Register
(RSO-RS2 = 011)
(RSO-RS1 01 with hidden flag)

=

By setting bits in the command register the ICSS30I can be
programmed for different color modes and can be powered down for low power operation.
7
S
6
Color Mode
2
1
0

1
3
2
Reserved
Should all =0

4

0
Snooze

Table 3 - Command Registers
Color Mode Select
These three bits select the Color Mode of
RAMDAC operation as shown in the following
table 4 (default is 0 at power up):

Bit 7-5

Color Modes
The four selectable color modes are described here.
Mode 0: 8-bit Pseudo Color (one clock per pixel). This
mode is the 8-bit per pixel Pseudo Color mode. In this
mode. inputs PO-P7 are the pixel address for the color
palette RAM and are latched on the rising edge of every
PCLK. This is the default mode on power up and it is
selected by setting bits CR7-CRS to 000. There are three
clock cycles pipe line delays from input to DAC output.
8-bit Pseudo Color mode
DATA BYTE
4
3
2

o

PIXEL ACCESS
76S4
3
2

0

7

Bit 4 - 1 (Reserved)

6

S

CM2
(CR7)

CMl
(CR6)

CMO
(CR5)

0
0
0
0

0
0

0
1
0
1

6-Bit Pseudo Color with Palette (Default)
IS-Bit Direct Color with Bypass (Hi-Color)
24-Bit True Color with Bypass (True Color)
I6-Bit Direct Color with Bypass (XGA)

2
3
2

1
1
1

0
0
1
1

0

IS-Bit Direct Color with Bypass (Hi-Color)
1S-Bit Direct Color with Bypass (Hi-Color)
I6-Bit Direct Color with Bypass (XGA)
24-Bit True Color with Bypass (True Color)

2
2
2
3

1

1

1

1

0
1

Clock Cycles!
Pixel Bits

Color Mode

Table 4 - Color Mode Select

H-47

1

III

ICS5301
GENDAC

•
Mode 1: (IS-bit per color bypassHi-Color mode).
This mode is the IS-bit per pixel bypass mode. In this
mode, inputs PO-P7 are the color DATA and are input
directly to the DAC, bypassing the color palette. The two
bytes of data is latched in two successive PCLK rising
edges. ICSS301 supports only the two clock mode and
does not support the mode where the data are latched on
the rising and the falling edges. For compatibility, the IS /
16 one clock modes are selected as two clock modes in this
chip. The low-byte, high byte synchronization is internally
done by the rising edge of BLANK*. Each color is S-bit
wide and is packed into two bytes as shown below. The
mode is selected by setting bits CR7-CRS to 001, 100 or
101.

Mode 3: (24-bit per pixel True Color Mode).
This mode is the 24-bit per pixel bypass mode. The three
bytes of data are latched on three successive PCLK edges
and the first byte is synchronized by the rising edge of
BLANK*. In this mode, each of the colors are 8-bit wide
and the DAC is an 8-bit wide DAC. The first byte is blue
followed by green and red. This mode can be selected by
setting bits CR7-CRS to 010 or 111. The DAC outputs
changes every three cycles and the pipeline delay from
the first byte to output is five cycles.
24-bit color mode
THIRD BYTE

IS-Bit Color Mode
3LSB = set to zero

GREEN

Frequency Generators

xl76 54 13 7 6 5 4 3/7 6 5 4 3
GREEN

BLUE

Mode 2: (16-bit per pixel bypass XGA mode).
This mode is the 16-bit per pixel bypass mode and the POP7 inputs to go to the DAC directly, bypassing the color
palette. The 2 bytes data is latched on two successive
rising edges and the low-byte, high-byte synchronization
is internally done by the rising edge of BLANK*. In this
mode, blue and red colors are 6 bits wide and green is S
bits wide. The 2 bytes of data is packed as shown below.
The mode is selected by setting bits CR7-CRS to 011 or
110.

The ICSS301 clock synthesizer can be reprogrammed
through the microprocessor interface for any set of
frequencies. This is done by writing appropriate values to
the PLL Parameter Register Bank (table S).

PLL Address Registers
The address of the parameter register is written to the
PLL address registers before accessing the parameter
register. This register is accessed by register select pins
RS2-RSO = 100 or 111.
6 S 4 3 2 1 0
PLL REGISTER ADDRESS
7 6 S 4 3 2 1 0

7

16-Bit color mode
2LSB = set to zero (green)
3LSB = set to zero (blue, red)
SECOND BYTE

FIRST BYTE

pppppppp pppppppp
7 6 543 2 1 a 7 6 5 4 3 2 1 a

7 6 5 4317 6 5 4 3 217 6 543
RED

BLUE

FIRST BYTE

pppppppp pppppppp
7 6 5 432 1 a 7 6 5 4 3 2 1 a
RED

FIRST BYTE

7 6 5 4 3 2 1 a 765 4 3 2 1 a 7 6 5 4 3 2 1 a
RED

SECOND BYTE

SECOND BYTE

pppppppp pppppppp pppppppp
7 654 3 2 1 a 765 4 3 2 1 a 765 4 3 2 1 a

GREEN

BLUE

PLL Parameter Register
There are sixteen registers in the PLL parameter register
(table S). Registers 00 to 07 are for the CLKO selectable
frequency list, Register OA for CLK1 programmable frequency and register OE is the PLL CLKO control register.

H-48

ICS5301
GENDAC

•
Index

RIW

Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

R/R/R/W
R/W
R/W
R/W
R/W
R/W
R/R/R/W
R/R/R/R/W
R/-

CLKO fO PLL Parameters
CLKO f1 PLL Parameters
CLKO f2 PLL Parameters
CLKO f3 PLL Parameters
CLKO f4 PLL Parameters
CLKO f5 PLL Parameters
CLKO f6 PLL Parameters
CLKO f7 PLL Parameters
(Reserved) = 0
(Reserved) = 0
CLKlfAPLL
(Reserved) = 0
(Reserved) = 0
(Reserved) = 0
PLL Control Register
(Reserved) = 0

PLL Data Registers
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(1-byte)
(2-byte)

The CLKO and CLK1 input frequency is deternimed by
the parameter values in this register. These are two bytes
registers; the first byte is the M-byte and the second is the
N-byte.
M-Byte PLL Parameter Input
The M-byte has a 7-bit value (1-127) which is the feedback
divider of the PLL.
7
6
Reserved
=0
X

X

X

X

X

X

X

N-Byte PLL Parameter Input
The N-byte has two values. N1 sets a 5-bit value (1-31) for
the input pre scalar and N2 is a 2-bit code for selecting 1,
2,4, or 8 post divide clock output.

Table 5 - PLL Parameter Registers

7
6
5
Reserved N2-Code
X X
=0

PLL Control Register
Bits in this register determine internal or external CLKO
select.
7
2
0

N2 code
00
01
10
11

Enable Internal Clock Select (INCS) for CLKO.
When this bit is set to 1, the CLKO output
frequency is selected by bit 2 - 0 in this register.
External pins CSO - CS2 are ignored.

Bit 4 - 3 (Reserved).
Bit 2 - 0 Internal Clock Select for CLKO (INCS).
These three bits selects the CLKO output frequency if bit 5 of this register is on. They are
interpreted as an octal number, n, that selects
fn. Default selects £0.

4

X

2
3
1
0
N1-Divider Value

X

X

X

X

N2 Post Divide Code

Bit 7 - 6 Reserved.
Bit 5

o

543
2
M-Divider Value

Divider
1
2
4
8

The block diagram of the PLL clock synthesizer is given
in following figure 3.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
,
(M+2) x Fref
Fout = - - - (N1+2) X2 N2
M and N values should be programmed such that the
frequency of the VCO is within the optimum range for
duty cycle, jitter and glitch free transition. Optimum duty
cycle is achieved by programming N2 for values greater
than one. See the following page for programming example.

H-49

ICS5301
GENDAC

II
3. 60 MHz .s. (M+2) fREF
(Nl+2)

Programming Example
Suppose an output frequency of 25.175 MHz is desired.
The reference crystal is 14.318 MHz. The VCO should be
targeted to run in the 100 to 180 MHz range, so choosing
a post divide of 4 gives a VCO frequency of :
4 X 25.175=101.021 MHz

.s. 270 MHz

This is the VCO frequency. In general, the VCO
should run as fast as possible, because it has lower jitter
at higher frequencies. Also, running the VCO at multiples of the desired frequency allows the use of output
divides, which tends to improve the duty cycle.

From the table on page 17, we find N2 = 2
Substituting Feef = 14.318 and 2N2 = 4 into the equation on
page 17:

4. fClKO and fClK1 .s. 135 MHz
This is the output frequency.

( 25.175).4 = (M + 2)
14.318
(Nl + 2)

These rules lead to the following procedure for determining the PLL parameters, assuming rules 1 and 4 are
satisfied.

by trial and error:
( 25.175).4'"
14.318
so

A. Determine the value of N2 (either 1, 2, 4 or 8) by
selecting the highest value of N2, which satisfies the
condition
N2* fClK .s. 270 MHz

127
18

M +2 = 127
Nl + 2 =18

M= 125
Nl = 16

so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = 0 & N2 code & Nl = 0 & 1 0 & 1 0 0 0 0
N=01010000b

Additional Information on Programming the
Frequency Generator section of the GENDAC
When programming the GENDAC PLL parameter registers, there are many possible combinations of parameters
which will give the correct output frequency. Some
combinations are better than others, however. Here is a
method to determine how the registers need to be set:
The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
1. 2 MHz < fREF < 32 MHz
This refers to the input reference frequency. Most
users simply connect a 14.318 MHz crystal to the crystal
inputs, so this is not a problem.
2. 600 kHz < fREF .s. 8 MHz
(Nl+2)
This is the frequency input to the phase detector.

B. Calculate

(M2+)
(Nl+2)

=

2N2f out
fref

C. Now (M+2) and (Nl+2) must be found by trial and

error. With a 14.318 MHz reference frequency, there will
generally be a small output frequency error due to the
resolution limit of (M+2) and (Nl+2). For a given frequency tolerance, several different (M +2) and (Nl +2)
combinations can usually be found. Usually, a few
minutes trying out numbers with a calculator will produce a workable combination. Multiplying possible
values of (Nl+2) by the desiredratio will indicate approximately the value of M. This method is shown in the
example below. A program could be written to try all
possible combinations of (M+2) and (Nl+2) (3937 possible combinations), discard those outside error band
and select from those remaining by giving preference t~
ratios which use lower values of (M+2). Lower values of
(M+2) and (Nl+2) provide better noise rejection in the
phase locked loop.
Example: Suppose we are using a 14.318 MHz reference
crystal and wish to output a frequency of 66 MHz with an
error of no greater than 0.5%. What are the values of the
PLL data registers?

H·50

ICS5301
GENDAC

•
A. 66*8 = 528 > 250 VCO speed too high
66*4 = 264 > 250 VCO speed too high
66*2 = 132 < 250 VCO speed OK, N2 = 2, N2 code =
01 from table on page 17 of the data sheet.

B. 132/14.31818 = 9.219
This is the desired frequency multiplication ratio.
C. Setting (N1+2) = 3, 4, ... 12, 13 and performing some
simple calculations yields the following table:
(Note that N1 cannot be 0)

(N1+2)

(N1 +2)*9.219

rounded (=M+2)

Actual Ratio

Percent Error

3
4
5
6
7
8
9
10
11
12
13

27.657
36.876
46.095
55.314
64.533
73.752
82.971
92.19
101.409
110.628
119.847

28
37
46
55
65
74
83
92
101
111
120

9.33
9.25
9.20
9.17
9.29
9.25
9.22
9.20
9.18
9.25
9.23

-1.23
-0.34
0.21
0.57
-0.72
-0.34
-0.03
0.21
0.40
-0.34
-0.13

The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2)
= 83; M = 81. The M-byte PLL parameter word is simply
81 in binary, plus bit 7 (which must be set to 0), or
01010001. The N-byte PLL parameter word is N2 code
(01) concatenated with 5 bits of N2 in binary (00111), or
00100111. Once again, bit 7 must be zero.

We have chosen the combination with the least frequency
error, but several other combinations are within the 0.5%
tolerance. Because the lowest value of (M+2) offers the
best damping, the 37/4 combination will have the best
power supply rejection. This results in lower jitter due to
external noise.

N2
CNTR

I Fou~

r--

Figure 3 - PLL Clock Synthesizer Block Diagram

CS2
0
0
0
0
1
1
1
1

External Select
CS1
0
0
1
1
0
0
1
1

(Internal Select PLL Control Register)
BIT 2
BIT 1
CSO
0
0
0
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
1
Video Clock Selection Table
H-51

BIT 0
0
1
0
1
0
1
0
1

CLK 0 Frequency
fO
f1
f2
f3
f4
f5
f6
f7

ICS5301
GENDAC

PLCK

PO-P7

BLANK*

RED

GREEN

BLUE

[j

\IJ \IJ \ \ A I 7 \IJ \IJ \IJ \IJ \IJ \J

L[_'-'-':_-'--_ _'__'__'__'____'__'__~}--A~B~

I .'

C

~BLANK-BLANK~F~G~

B

~

L._ _

LA~ ~

~_~I

_ __'__'_ _ _

1

1 - 1_ _ _ _ _ _ _ _ _ _ _ _

A

~F~G~

C--------BLANK-BLANKJ

~B~C~BLANK-BLANK~F------G~

System Timing - Pseudo Color, Mode 0

PLCK

PO-P7

BLANK*

RED

GREEN

BLUE

c

~BLANK---BLANKJ

C~BLANK---BLANKJ
C

~BLANK---BLANK~

Detailed Timing Specifications - Pseudo Color, Mode 0

H-52

ICS5301
GENDAC

•
PCLK

BLANK

PO-P7

A______/ B DAC-RD

_-+__________________-+-'

DAC-GR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,--J/r--A~B-

DAC-BL

r--A- - - - - - /B-

--------------------------------------~

System Timing Bypass - 15 (5/5/5) and 16 (5/615) Modes 1, 2

Ons

25ns

DAC-BL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _/

,'-______----J/

DAC~R-----------------~-------rl--------~~
DAC-RD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _/----7.Ar--""'---B...----~

System Timing Bypass True Color 24 (8,8,8) Mode 3

H-S3

ICS5301
GENDAC

WR"
RSO-RS1
..- >'; l'J
'.. ..

. ~ , '-:. ,~.

'..

00-07

~

/,

Basic Write Cycle Timing

RO"
RSO-RS1
00-07

Basic Read Cycle Timing

WR"
RO"
RSO
RS1

Write to Pixel Mask Register Followed by Write

WR"

Write to Pixel Mask Register Followed by Read

t RHRU 1-----1

RO"

Read from Pixel or Pixel Address Register
(Read or Write) followed by Read

Read from Pixel or Pixel Address Register
(Read or Write) followed by Write

H-54

•

ICS5301
GENDAC

WR*

RD'

RSO

v

RS1

\

RS2
DO-D7

----<

/ ..

.

ADDRESS I------
--------------

WR*

RD'

RSO

~

{

RS1

h

r

~

.........

\

RS2
DO-D7

--------<.

ADDRESS

~

ADDRESS

}>---------------

Write and Read Back Pixel Address Register (Write Mode)

WR*

RD*

RSO

/

\I.23

~

\2J3

RS1

/

\:>;~>\

r:::f2\

~

RS2

\'------L--F70,~.'.
;.~:;."'------L-~__':-;
:~:;;;........>•.. -----<:....;.;.jJ!T[\_,
' '"' -':'."'-----'"'[,''--'-' -;:';-=-:.1'::4

DO-D7

Read Color Value then Pixel Address Register (Read Mode)

H-55

ICS5301
GENDAC

WR'
RD'

RSO

~

t

RS1

~

C3

L

\

I"

RS2

~

/.,:\

l

\

I

'

"

~ , ~,

\~" ~

7

ADDRESS

00-07

\" '.;j

)

RED

\

': <.>
'\,
,

..

."

I>;

'

GREEN

, c::xJ

:,,~,~

"

l>

'\

·XEIJ

.~

~'.','x==:xJ

BLUE

Color Value Write followed by any Read

WR'~'

U

!WHWLl

0-

!WHWLl
-.

U

!WHWLl

.-

-.

U

"-

!WHWL2
••

L

.-

RD*

RSO

b

/

7

'\

RS1

~

I

\

I

~

I

\

/

RS2

00-07

ADDRESS

..

;
~.

",

7

\

\

I

\

t

RED

..

..
,,"c

I
\

I

:'\

/,

GREEN

Color Value Write followed by any Write

H-56

x=:J(J

\
',',:

BLUE

x:=JCJ
LJO

ICS5301
GENDAC

•
WR*

RO*

RSO

V

\

7

\

7

\

7

\

.x==xJ

RS1

V

\

\

L

\

L

\

L

x==xJ

~

L

\

L

\

L

\

L

x==xJ

RS2

00-07

ADDRESS

RED

GREEN

BLUE

Color Value Read followed by any Read

WR*

~.

t WHRL3

RO*

t RHRLl

t RHRLl

'U' 'U 'U'

tRHw~

.}-

RSO

V

\

/

\

7

\

7

\

RS1

V

\

~

L

~

L

~

/

x==xJ
x==xJ

RS2

~

L

~

t

\

L

\

L

CXJ

00-07

ADDRESS

RED

GREEN

Color Value Read followed by any Write

H·57

BLUE

III

ICS5301
GENDAC

•
WR*

t

. .~

~

tWHRL3

RO*

~~~~~~---------------------

RS1

RS2

00-07

V

--<

ADDRESS

'r-------<

ADDRESS

)>-----------------------------

Write and Read back PLL Address Register (Write Mode)

WR*

t

. .~

~

t

W
HRL3

,--------------------------------

RO*

RSO

v

RS1
RS2

00-07

--<

ADDRES~

ADDRESS

)>----------------------------

Write and Read back PLL Address Register (Read Mode)

H-58

ICS5301
GENDAC

•
WR*

RO*

RSO

RS1

RS2

u
u

\

\

u

00-07 _-----{

PLL ADDRESS

Read Two bytes PLL Register then PLL Address Register

WR*

~f '-~ tArI------t-R---+-tRHRL_

RO*

RSO

RS1

RS2

LJ \

/

"-------------

"-------------

LJ \
LJ \

\

~

~

/

"-------------

00-07--\

ADDRESS

~

Read One Byte PLL Register then PLL Address Register

H·59

III

ICS5301
GENDAC

II
Monitor SENSE Signal
RED,
GREEN,
BLUE

/
335V

/
tSOD

SENSE

"Recommended Layout
tiple vias to the ground and power planes, if possible. Power
connections should be connected to the analog or digital power
plane, as shown in the diagram. Power pins 5 and 29 should be
connected to digital power, power pins 20 and 24 to analog
power. Decoupling capacitors (indicated by CI) should be
placed as close to the GENDAC as possible.

The high performance of which the ICS5301 GENDAC is
capable is dependent on careful PC board layout. The use of
a four layer board (internal power and ground planes, signals
on the two surface layers) is recommended. The layout below
shows a suggested configuration.
The ground plane is continuous, but the power plane is
separated into analog and digital sections as shown. Power is
supplied to the analog power plane through the ferrite bead,
and bypassed at the power entry point by C3, a 10 IlF tantalum
capacitor. These high current connections should have mul-

The analog and digital 110 lines are not shown. Analog signals
(DAC outputs, Vref, Rset) should only be routed above the
analog power plane. Digital signals should only be routed
above the digital power plane.

Cl

DIGITAL Power
Plane

Cl

+
100 mil Separation

ICS5301

c:::KX::::J
Cl

Analog Power
Plane Island

Cl

a

+

o_
o+
CI
C2
C3
FBI
Rl
Y1

VIA to ground plane
VIA to power plane
,01 uf chip capacitor
,1 uf ChIp capacitor
lOuf tantulum capacitor
Ferrite Bead
140 ohm 1 % reSIstor
14.318 Mhz parallel resonant crysal cut for C L =12

H-60

C2

C3

II

ICS5301
GENDAC

Ordering Information
ICS5301V
Example:

T

ICS TXXXX

T'-___

Package Type
V=PLCC

L - -_ _ _ _ _

Device Type (consists of 3 or 4 digit numbers)
PrefIX
ICS, AV=Standard Device; GSP=GenlockDevice

H·61

H-62

ICS5340
GENDAC

Integrated
Circuit
Systems, Inc.

•

16-Bit Integrated Clock-LUT-DAC
General Description

Features

The ICS5340 GENDAC is a combination of dual programmable clock generators, a 256 x IS-bit RAM, and a
triple S-bit video DAC. The GENDAC supports S-bit
pseudo color applications, as well as I5-bit, I6-bit and 24bit True Color bypass for high speed, direct access to the
DACs.

• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, IS, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixeD clock
frequencies (CLKO)
• Two programmable memory (controller) clock
frequency (CLKl)
• DAC power down in blanking mode
• Anti-sparkle circuitry
• On-chip loop filters reduce external components
• Standard CPU interface
• Single external crystal (typically 14.318 MHz)
• Monitor Sense
• Internal voltage reference
• 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions

The RAM makes it possible to display 256 colors selected
from a possible 262,144 colors. The dual clock generators
use Phase Locked Loop (PLL) technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains S frequencies, 6 of
which are programmable by the user. The memory clock
has two programmable frequency locations.
The three S-bit DACs on the ICS5340 are capable of
driving singly or doubly-terminated 75Q loads to nominalO - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows
displayed colors to be changed in a single write cycle
rather than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock)
generation for graphics, using patented techniques to
produce low jitter video timing.

• Very low clock jitter
• Latched frequency control pin

Block Diagram
PCLK-------...,~

PO-PIS

DO-D7

PCLK

WR'RD'-

~P-INTERFACE

RSO-2~
STROBE

--.-.!'::::::==t=F=::::;-i!
~------~------------~~CLKO

XOUT

"1---------------------.

H-63

CLK!

II

ICS5340
GENDAC

Pin Configuration
N/C
N/C
N/C

N/C
N/C

WR'
RS2
RSI
RSO

CVDD

GENDACII
ICS5340

XIN
XOUT

CGND
CLKI
CGND
N/C
N'/C
N/C
N/C

Pl2
Pll
PIO
P9
P8
P7
P6

DVDD
P5

AGND
P4
P3
P2

N/C
N/C

Rev 1.0

Pin Description (68 pin PlCC) K-10
Symbol
07-00

Pin #
68,1-7

Type
I/O

RD*

8

Input

WR*

13

Input

RS2
RSI
RSO
CVDD
XIN
XOUT
CGNO

14
15
16
17
18
19
20

Input
Input
Input
-

Input
Output
-

Description
System data bus I/O. These bidirectional Data I/O lines are used by the
host microprocessor to write (using active low WR*) information into,
and read (using active low RD*) information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR* latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD* determines the end of the read
cycle. When RD* is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tri-state mode.
RAM/PLL Read Enable, active low. This is the READ bus control signaL
When active, any information present on the internal data bus is available
on the Data I/O lines, DO-D7.
RAM/PLL Write Enable, active low. This signal controls the timing of the
write operation on the microprocessor interface il1£uts, DO-D7.
Register Address Select O. These inputs control the selection of one of the
six internal registers. They are sampled on the falling edge of the active
enable signal (RD* or WR*).
Crystal oscillator and CLKO power supply connect to A VOD.
Crystal input. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
VSS for CLKO. Connect to ground.

H-64

ICS5340
GENDAC

•
Pin Description (continued)
Symbol

Pin #

Type

CLKI
CGND
CLKO

21
22
28

Output
Output

CVDD
CSO

29
30

Input

CSI

31

Input

CS2

32

Input

VREF

33

I/O

RSET

34

Input

SENSE*

35

Output

AVDD
BLUE
GREEN
RED

37
36
38
39

Output
Output
Output

STROBE
PO -P15

40
41-42
46-48,50

Input
Input

49
51
65
52-58,
62-64

Input

BLANK*

66

Input

DGND

67

-

AGND
DVDD
PCLK

-

-

-

-

Description

Memory clock output. Used to time the video memory.
VSS for CLKl. Connect to ground.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
CLKI Power Supply. Connect to A VDD.
Clock select O. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 1. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 2. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Internal Reference Voltage. Normally connects to a 0.1~ cap to ground.
To use an external Vref, connect a l.235V reference to this pin.
Resistor Set. This pin is used to set the current level in the analog outputs.
It is usually connected through a 140Q 1% resistor to ground.
Monitor Sense, active low. This pin is low when any of the red, green,
or blue outputs have exceeded 335mV. The chip has on-board comparators and an internal 335mV voltage reference. This is used to detect
monitor type.
DAC power supply. Connect to AVDD.
Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value.
These outputs are typically used to drive a CRT monitor.
Latches the input clock select signals CSO - CS2.
Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
should be grounded if thev are not used.
DAC Ground. Connect to ground.
Digital power supply.
Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address and BLANK* inputs. This clock also controls the progress of
these values through the three-stage pipeline of the Color Palette RAM,
DAC and outputs.
Composite BLANK* Signal, active low. When BLANK* is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette may still be updated through DO-D7 during blanking.
Digital Ground. Connect to ground.

H-65

ICS5340
GENDAC

Internal Registers
RS2 RSl

RSO

Register
Name

Description
(all registers can be written to and read from)

There is a single Pixel Address register within the GENDAC. This register
can be accessed through either register address 0,0,0 or register address
0,1,1. A read from address 0,0,0 is identical to a read from address 0,1,1.
Writing a value to address 0,0,0 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Initializes the Color Value register.
Writing a value to address 0,1,1 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Loads the Color Value register with the contents of the location in the
addressed RAM palette and then increments the Pixel Address register.

°
°
°

0

°

Pixel Address
WRITE

Writing to this 8-bit register is performed prior to writing one or more
color values to the color palette RAM.

1

1

Pixel Address
READ

Writing to this 8-bit register is performed prior to reading one or more
color values from the color palette RAM.

0

1

Color Value

The 18-bit Color Value register acts as a buffer between the microprocessor
interface and the color palette. Using a three bytes transfer sequence allows
a value to be read from or written to this register. When a byte is read, the
color value is contained in the least significant 6 bits, DO-OS (the most
significant 2 bits are set to zero). When writing a byte, the same 6 bits are
used. When reading or writing, data is transferred in the same order - the
red byte first, then green, then blue. Each transfer between the Color Value
register and the color palette replaces the normal pixel mapping operations
of the GENOAC for a single pixel.
After writing three definitions to this register, its contents are written to the
location in the color palette RAM specified by the Pixel Address register,
and the Pixel Address register increments.
After reading three definitions from this register, the contents of the location
in the color palette RAM specified by the Pixel Address registers are copied
into the Color Value register, and the Pixel Address register increments.

0

1

°

Pixel Mask

The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel
Address value applied to the Pixel Address inputs (PO-P7). A one in a
position in the mask register leaves the corresponding bit in the Pixel
Address unaltered, while a zero sets that bit to zero. The Pixel Mask register
does not affect the Pixel Address generated by the microprocessor interface
when the palette RAM is being accessed.

H-66

ICS5340
GENDAC

•
Internal Registers (continued)
RS2

RSI

RSO

Register
Name

Description
(all registers can be written to and read from)

1

0

0

PLLAddress
WRITE

Writing to this 8-bit register is performed prior to writing one or more
PLL programming values to the PLL Parameter register.

1

1

1

PLLAddress
READ

Writing to this 8-bit register is performed prior to reading one or more
PLL programming values from the PLL Parameter register.

1

1

0

Command

This 8-bitregister selects the color mode, for instance 8-bit Pseudo Color, HiColor, True Color, or XGA, and DAC power down. The registers are reset
to pseudo color mode on power up.

1

0

1

PLL
Parameter

There are sixteen parameter registers as indexed by PLL Address Write/
Read registers. Parameter registers OO-OD and OF are two bytes long and OE*
is one byte long. This register set contains one control register. The bits of this
register include clock select and enable functions, the rest contain PLL
frequency parameters. After writing the start index address in the PLL
address register, these registers can be accessed in successive two (or one)
bytes. The address register auto increments after one or two bytes to access
the entire register set.

H-67

ICS5340
GENDAC

II
Absolute Maximum Ratings
Power Supply Voltage .................................................. 7 V

DC Digital Output Current .................................... 25 rnA

Voltage on any other pin ...... GND- O.5V to VDD + O.5V

Analog Output Current ......................................... .45 rnA

Temperature under bias .......................... - 40° C to 85° C

Reference Current .................................................. -15 rnA

Storage Temperature ............................. - 65° C to 150° C

Power Dissipation ..................................................... 1.0 W

Note:

Stresses above those listed under Absolute Maxunum Ratings may cause permanent damage to the deVIce. This is a stress rahng only and
functional operation of the deVice at these or any other conditions above those indicated in the operational sections of this specification
IS not implied. Exposure to absolute maXimum rating conditions for extended periods may affect device reliability.

Electrical Characteristics
Symbol

Parameter

Conditions

Min

Max

Units

5.25

V
V
V
rnA
V

DC CHARACTERISTICS (note: J)
Voo
V1H
V1L
lREF
VREF
lIN

Positive supply voltage
Input logic ''}'' voltage
Input logic "0" voltage
Reference current
Reference voltage
Digital input current

loz

Off-state digital output current

100

Average power supply current

4.75
2.0
-0.5
-7.0
1.10
Voo = max,
GND:'> VIN :,> Voo

Voo + 0.5
0.8
-10
1.35
±1O

~A

Voo=max,
GND:,>VIN:,>Voo

±50

~

10 = max,

250

rnA

50

0.4
15
15

rnA
V
V
V
V
V
V
ns
ns

0.05

%

Digital outputs unloaded

IOACOFF
VOHS
VOLS
VOHC
VOLC
VOH
VOL
ICLKr *
ICLKf*
Fo

DACs in power down mode
Sense logic ''}''
Sense logic "0"
Clock logic "1"
Clock logic "0"
logic "1"
logic "0"
Input Clock Rise Time
Input Clock Fall Time
Frequency Change of CLKO and
CLK1 over supply and temperature

No palette access
10= .4mA
10= .4rnA
10 = TBD
10=TBD
10 = -3.2rnA, note K
10 = 3.2rnA, note K
TIL levels
TIL levels
With respect to
typical frequency

H-68

2.4
0.4
2.4
0.4
2.4

ICS5340
GENDAC

•
Electrical Characteristics (continued)
Symbol

Parameter

Conditions

Min

Max

Units

DAC CHARACTERISTICS (note: J)
Vo (max) Maximum output voltage
10 (max) Maximum output current
Full scale error
DAC to DAC correlation
Integral Linearity, 6-bit
Integral Linearity, 8-bit
Full scale settling time* 6-bit
Full scale settling time*, 8-bit
Rise time 00% to 90%)*
Glitch energy*

1.5
21
±5
±2
±0.5
±1
28
20
6
200

10 :s; lOrnA

Vo :S;1V
note A, B
note B
note B
note B
noteC
noteC
noteC
noteC

V
rnA
%
%
LSB
LSB
ns
ns
ns
pVsec

* Characterized values only

Symbol

Parameter

Conditions

Min

Max

Units

25
25

135
135
3
3
60/40
130ps
300 ps
25

MHz
MHz
ns
ns

PLL AC CHARACTERISTICS
fO
fl
tr
tr
dt
hs
jabs
f ref

Clock 0 operating range*
Clock 1 operating range*
Output clocks rise time*
Output clocks fall time*
DutyCycle*
Jitter, one sigma*
Jitter, absolute*
Input reference frequency*

25 pf load, TTL levels
25 pf load, TTL levels
40/60

Typically 14.318 MHz

H-69

-300 ps
5

%

ps
ps
MHz

II

ICS5340
GENDAC

AC Electrical Characteristics (note: J)

Symbol
tCHCH
MCHCH*
tCLcH
t CHCL
tpVCH
t CHPX
t BVCH

Parameter

tWHRLI
tRHRLl
tRHWLI
tWHWL2
tWHRL2
tRHRL2
tRHWL2
t WHRL3

PCLKperiod
PCLK jitter
PCLK width low
PCLK width high
Pixel word setup time
Pixel word hold time
BLANK* setup time
BLANK* hold time
PCLK to valid DAC output
Differential output delay
WR* pulse width low
RD* pulse width low
Register select setup time
Register select setup time
Register select hold time
Register select hold time
WR* data setup time
WR* data hold time
Output turn-on delay
RD* enable access time
Output hold time
Output turn-off delay
Successive write interval
WR* followed by read interval
Successive read interval
RD* followed by write interval
WR* after color write
RD* after color write
RD* after color read
WR* after color read
RD* after read address write

tsoo

SENSE* output delay

tCHBX
tCHAV *
~tcHAV

tWLwH
tRLRH
tSVWL
tsvRL
t wLSX
t RLSX
tOVWH
tWHDX
tRLQX
tRLQV
tRHQX
tRHQZ
t WHWLI

Condition

80 MHz
Min Max

110 MHz
Min Max

135 MHz
Min Max Units

12.5

9.09

7.4

±2.5

noteD

5
5
noteE
noteE
noteE
noteE
noteF
noteG

3.6
3.6
3

3
3
3
3

4 (tCHCH )
4 (tCHCH )
4 (tCHCH)
4 (tCHCH)
4 (tCHCH)
4 (tCHCH )

4 (tCHCH)
4 (tCHCH)
4 (tCHCH )
4 (tCHCH )
4 (tCHCH )
4 (tCHCH)

8 (tCHCH)
8 (tCHCH)
8 (tCHCH )

8 (tCHCH)
8 (tCHCH)
8 (tCHCH)

1

Il s

2
1
2
1

3

2
20
2

20
2

50
50
10
10

50
50

50
50

10
10

10
10

10

10

10
10

10

10
10
10
10

10
10
5
40

5

5

40
5

20
4 (tCHCH )

~ (tCHCH)
~ (tCHCH)
~ (tCHCH)

~ (tCHCH)
~ (tCHCH )

8 (tCHCH )
8 (tCHCH)
8 (tCHCH)

1

H-70

3
3

2

10
5

noteH
note I
note I
note I
note I
note I
note I
note I
note I
note I

%

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle

20
2

Write cycle
Read cycle
Write cycle
Read cycle

ns

+2.5

40
5

20

1

20

ICS5340'
GENDAC

General Operation

NOTES:
A.

Full scale error is derived from design equation
{[(F.S.lOUT) Rc - 2.1 (IREF) Rcl/[2.l(IREF)RLlI 100%
VBLACK LEVEL ;OV F.S·lQUT; Actual full scale measured output

B.

R; 37.50, IREF ;

C.

~;

D.

This parameter is the allowed Pixel Clock frequency variation. It
does not penrut the PIXel Clockpenod to vary outside thenunimum
values for P,xel Clock (tCHCH) period

E.

It is required that the color palette's pIxel address be a valid logic

-

8.88mA

37.50 + 30 pF, IREF ;

-

8 88mA

level WIth the appropriate setup and hold times at each rising edge
of PeLK (th,s requirement mcludes the blanking period).
F.

The output delay IS measured from the 50% pomt of the rising edge
of CLOCK to the valid analog output. A valid analog output is
defmed when the analog signal IS halfway between ItS successive
values.

G.

This applies to different analog outputs on the same device.

H.

Measured at ± 200 m V from steady state output voltage

1.

This parameter allows synchronizahon between operations on the

microprocessor interface and the pixel stream being processed by
the color palette.

J.

The following specifications apply for VDD ; +5V± O.5V, GND;O.
Operating Temperature; O°C to 70°C.

K.

Except for SENSE pm.

AC Test Conditions
Input pulse levels................................................. VDD to 3V
Input rise and fall times (10% to 90%) ..........................3ns
Digital input timing reference level... ........................1.5V
Digital output timing reference level... .....O.8V and 2.4V

An externally generated BlANK* signal can be applied to
pin 66 of the ICS5340. This signal acts on all three of the
analog outputs. The BlANK* signal is delayed internally
so that it appears with the correct relationship to the pixel
bit stream at the analog outputs.
A pixel word mask is included to allow the incoming
pixel address to be masked. This permits rapid changes to
the effective contents of the color palette RAM to facilitate
such operations as animation and flashing objects.
Operations on the contents of the mask register can also
be totally asynchronous to the pixel stream.
The ICS5340 also includes dualPll frequency generators
providing a video clock (ClKO) and a memory clock
(ClKl), both generated from a single 14.318 MHz crystal.
There are eight selectable ClKO frequencies. Six are
programmable, and two are fixed. There are two selectable and programmable ClKl frequencies (fA, fB). Default values (Table 1 and Table 2) are loaded into the
appropriate registers on power up.

Video Path

Capacitance
C1 Digital input. .............................................................. 7pF
Co Digital output. ...........................................................7pF
COA Analog output....................................................... 1OpF
2000

1.4V

I/O~

I

The ICS5340 GENDAC is intended for use as the analog
output stage of raster scan video systems. It contains a
high-speed Random Access Memory of 256 x 18-bitwords,
three 6/8-bit high-speed DACs,amicroprocessor/graphic
controller interface, a pixel word mask, on-chip comparators, and two user programmable frequency generators.

50 pF

The GENDAC supports nine different video modes and
is determined by bits 4-7 of the command register. The
default mode is the 8-bit Pseudo Color mode. The other
modes are the bypass 15-bit, 16-bit and 24 bit True Color
modes in 8-bit and 16-bit interface, and the 16-bit Pseudo
Color (2:1) mode with 2X Clock.. The 16-bit True Color
has sparse and packed modes.

(including scope and jig)

DIGITAL OUTPUT LOAD

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ICS5340
GENDAC

•
Pseudo Color
8-bit Interface
In this mode, Pixel Address, PO-P7 and BLANK* inputs
are sampled on the rising edge of the clock (PCLK) and
any change appears at the analog outputs after three
succeeding rising edges of the PCLK. The DAC outputs
depends on the data in the color palette RAM.

The reference current IREF is determined by the reference
voltage VREF and the value of the resistor connected to
RsET pin. V REF can be the internal band gap reference
voltage or can be overridden by an external voltage. In
both cases IREF =VREF/RsET .

16-bit Interface
In this mode, Pixel Address, PO-P15 and BLANK* inputs
are sampled on the rising edge of the clock (PCLK) and
any change appears at the analog outputs after three
succeeding rising edges of the 2 x ICLK. The DAC outputs
depends on the data in the color palette RAM.

Figure 4 - DAC Set up

The BLANK* inputto the GENDAC acts on all three ofthe
DAC outputs. When the BLANK* input is low, the DACs
are powered down.

Bypass Mode

The GENDAC supports seven different bypass modes:
three for byte transfers and four for word transfers. In The connection between the DAC outputs of the ICS5340
these modes, the address pins PO-P15 represent Color and the RGB inputs of the monitor should be regarded as
Data that is applied directly to the DAC . The internal a transmission line. Impedance changes along the translook-up table RAM is ignored. During byte transfers, the mission line will result in the reflection of part of the video
P8-P15 inputs are Don't Care. Data is always latched on signal back along the transmission line. These reflections
the rising edge of PCLK. Byte or Word framing is inter- may result in a degradation of the picture displayed by
the monitor.
nally synchronized with the rising edge of BLANK*.

Oac Outputs
The outputs of the DACs are designed to be capable of
producing 0.7 volt peak white amplitude with an IREF of
8.88 rnA when driving a doubly terminated 75Q load.
This corresponds to an effective DAC output load
(REFFECTIVE) of 37.5Q. The formula for calculating IREF
with various peak white voltage/output loading
combinations is given below:
IREF =

V

PEAK WHITE

2.1 X REFFECTNE

Note that for all values of IREF and output loading:
VBLACKLEVEL

=0

RF techniques should be observed to ensure good fidelity. The PCB trace connecting the GENDAC to the offboard connector should be sized to form a transmission
line of the correct impedance. Correctly matched RF
connectors should be used for connection from the PCB to
the coaxial cable leading to the monitor and from the
cable to the monitor.
There are two recommended methods of DAC termination: double termination and buffered signal. Each is
described below with its relative merits:
Double Termination (Figure 1)
For this termination scheme, a load resistor is placed at
both the DAC output and the monitor input. The resistor
values should be equal to the characteristic impedance of
the line. Double termination of the DAC output allows
both ends of the transmission line between the DAC

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ICS5340
GENDAC

•
outputs and the monitor inputs to be correctly matched.
The result should be an ideal reflection free system. This
arrangement is relatively tolerant to variations in
transmission line impedance (e.g. a mismatched
connector) since no reflections occur from either end of
the line.
A doubly terminated DAC output will rise faster than any
singly terminated output because the rise time of the
DAC outputs is dependent on the RC time constant of the
load.

)-

ICS5340

MONITOR

reference voltage to the comparators, the SENSE* pin is
driven low. This signalis used to detect the type of (or lack
of) monitor connected to the system.

PLL Clock
The ICS5340 has dual PLL frequency generators for generating the video clock (CLKO) and memory clock (CLK1)
needed for graphics subsystems. Both these clocks are
generated from a single 14.318 MHz crystal or can be
driven by an external clock source. The chip includes the
capacitors for the crystal and all the components needed
for the PLL loop filters, minimizing board component
count.

RLOAD
GND

RLOAD

I

GND

Figure 1 - Double Termination

Buffered Signal (Figure 2)
If the GENDAC drives large capacitive loads (for instance
long cable runs), it may be necessary to buffer the DAC
outputs. The buffer will have a relatively high input
impedance. The connection between the DAC outputs
and the buffer inputs should also be considered as a
transmission line. The buffer output will have a relatively
low impedance. It should be matched to the transmission
line between it and the monitor with a series terminating
resistor. The transmission line should be terminated at
the monitor.

j>Rs

There are eight possible video clock, CLKO, frequencies
(fO-f7) which can be selected by the external pins CSOCS2. Pins are software selectable by setting a bit in the PLL
control register. Two of these frequencies (fO-fl) are fixed
and the other six (f2-£7) can be programmed for any
frequency by writing appropriate parameter values to the
PLL parameterregisters. The defaultfrequencies on power
up are commonly used video frequencies (table 1). At
power up, the frequencies can be selected by pins CSOCS2. There are two programmable memory clock frequencies (fA, fB). On power up this frequency defaults to
the frequency given in table 2. The memory clock transition between frequencies is smooth and glitch free if the
transition is kept between the limits 45-65 MHz.

MONITOR

ICS5340
RLOAD
GND

RT

l

GND

fA

(MHz)

fO
f1
f2
f3
14
f5

25.175
28.322
31.500
36.00
40.00
44.889

f6

65.00

f7

75.00

Figure 2 - Buffered Signal

SENSE Output
The GENDAC contains three comparators, one each for
the DAC output (R, G and B) lines. The reference voltage
to the comparators is proportional to the VREF (internal or
external) and is typically 0.33 for VREF = 1.23 Volts. When
the voltage on any of these pins go higher than the

VLCK
Comments
VGAO (VGA Graphics) (fixed)
VGA1 (VGA Text) (fixed)
VESA 640 x 480 @72 Hz (programmable)
VESA 800 x 600 @56 Hz (programmable)
VESA 800 x 600 @60 Hz (programmable)
1024 x 768 @43 Hz Interlaced
(programmable)
1024 x 768 @ 60 Hz,
640 x 480 Hi-Color @ 72 Hz
(programmable)
VESA 1024 x 768 @ 70 Hz,
True Color 640 x 480 (programmable)

Table 1- Video clock (CLKO) default frequency register
(with a 14.318 MHz input)

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Writing to the color palette RAM
fn

Comments

MHz

fA

45.00 MHz Memory and GUI subsystem clock

fB

55.00 MHz Memory and GUI subsystem clock

To set a new color definition, a value specifying a location
in the color palette RAM is first written to the Write mode
Pixel Address register. The values for the red, green and
blue intensities are then written in succession to the Color
Value register. After the blue data is written to the Color
Value register, the new color definition is transferred to
the RAM, and the Pixel Address register is automatically
incremented.

Table 2 - Memory Clock (CLKl) default frequency
register

Microprocessor Interface
Below are listed the six microprocessor interface registers
within the ICS5340, and the register addresses through
which they can be accessed.
RS2

RSl

RSO

0
0
0
0
1
1
1
1
OjHF

0
1
0
1
0
0
1
1
1

0
1
1
0
0
1
0
1
0

Register Name
Pixel Address (write mode)
Pixel Address (read mode)
Color Value
Pixel Mask
PLL Address (write mode)
PLL Parameter
Command
PLL Address (read mode)
Command Re&ister
accessed by (hldden) flag after
special sequence of events

Table 3 - Microprocessor Interface Registers
Asynchronous Access to Microprocessor Interface
Accesses to all registers may occur without reference to
the high speed timing of the pixel bit stream being
processed by the GENDAC. Data transfers between the
color palette RAM and the Color Value register, as well as
modifications to the Pixel Mask register, are synchronized
to the Pixel Clock by internal logic. This is done in the
period between microprocessor interface accesses. Thus,
various minimum periods are specified between
microprocessor interface accesses to allow the appropriate
transfers or modifications to take place. Access to PLL
address, PLL parameter and to the command register are
asynchronous to the pixel clock.
The contents of the palette RAM can be accessed via the
Color Value register and the Pixel Address registers.

Writing new color definitions to a set of consecutive
locations in the RAM is made easy by this autoincrementing feature. First, the start address of the set of
locations is written to the write mode Pixel Address
register, followed by the color definition of that location.
Since the address is incremented after each color definition
is written, the color definition for the next location can be
written immediately. Thus, the color definitions for
consecutive locations can be written sequentially to the
Color Value register without re-writing to the Pixel
Address register each time.
Reading from the RAM
To read a color definition, a value specifying the location
in the palette RAM to be read is written to the read mode
Pixel Address register. After this value has been written,
the contents of the location specified are copied to the
Color Value register, and the Pixel Address register
automatically increments.
The red, green and blue intensity values can be read by a
sequence of three reads from the Color Value register.
After the blue value has been read, the location in the
RAM currently specified by the Pixel Address register is
copied to the Color Value register and the Pixel Address
again automatically increments. A set of color values in
consecutive locations can be read simply by writing the
start address of the set to the read mode Pixel Address
register and then sequentially reading the color values for
each location in the set. Whenever the Pixel Address
register is updated, any unfinished color definition read
or write is aborted and a new one may begin.

The Pixel Mask Register
The pixel address used to access the RAM through the
pixel interface is the result of the bitwise ANDing of the

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ICS5340
GENDAC

II
incoming pixel address and of the contents of the Pixel
Mask register. This pixel masking process can be used to
alter the displayed colors without altering the video
memory or the RAM contents. By partitioning the color
definitions by one or more bits in the pixel address, such
effects as rapid animation, overlays, and flashing objects
can be produced.
The Pixel Mask register is independent of the Pixel Address
and Color Value registers.

The Command Register
The Command register is used to select the various GENDAC color modes and to set the power down mode. On
power up this register defaults to an 6-bit Pseudo Color
mode. This register can be accessed by control pins RS2RSO, or by a special sequence of events for graphics
subsystems that do not have the control signal RS2. For
graphic systems that do not have RS2, this pin is tied low
and an internal flag (HF; Hidden Flag) is set when the
pixel mask register is read four times consecutively. Once
the flag is set, the following Read or Write to the pixel
mask register is directed to the command register. The
flag is reset for Read or Write to any register other than the
pixel mask register. The sequence has to be repeated for
any subsequent access to the command register.

The PLL Parameter Register
The CLKO and CLKI of the ICS5340 can be programmed
for different frequencies by writing different values to the
PLL parameter register bank. There are eight registers in
the parameter register; seven are two bytes long and one
(OE) is one byte long.

Writing to the PLL parameter register
To write the PLL parameter data, the corresponding
address location is first written to the PLL address register. For software compatibility with other chips, two
address registers are defined; the Write mode PLL address register and the Read mode PLL address register.
They are actually a single Read/Write register in the
ICS5340. The next PLL parameter write will be directed to
the first byte of the address location specified by the PLL
address register. The next Write to the parameter register

will automatically be to the second byte of this register. At
the end of the second Write the address is automatically
incremented. For the one byte "OE" register the address
location is incremented after the first byte Write. If this
frequency is selected while programming, the output
frequency will change at the end of the second Write.
Reading the PLL parameter register
To read one of the registers of the PLL parameter register
the address value corresponding to the location is first
written to the PLL address register. The next PLL parameter read will be directed to the first byte of the address
location pointed by this index register. A next Read of the
parameter register will automatically be the second byte
of this register. At the end of the second Read, the address
location is automatically incremented. The address register (OE) is incremented after the first byte Read.

Power Down Mode
When bit 0 in the Command register is high (set to 1) , the
GENDAC enters the DAC power down mode. The DACs
are turned off, and the data is retained in the RAM. It is
possible to access the RAM, in which case the current will
temporarily increase. While the RAM is being accessed,
the current consumption will be proportional to the speed
of the clock. There is no effect on either clock generator
while in this mode.

Power Supply
As a high speed CMOS device, the ICS5340 may draw
large transient currents from the power supply, it is
necessary to adopt high frequency board layout and
power distribution techniques to ensure proper operation of the GENDAC. Please refer to the suggested layout
on page 27.
To supply the transient currents required by the ICS5340,
the impedance in the decoupling path should be kept to
a minimum between the power supply pins VDD and
GND. It is recommended that the decoupling capacitance
between VDD and GND should be a O.ll1F high frequency
capacitor, in parallel with a large tantalum capacitor with

H-75

III

II

ICS5340
GENDAC

a value between 221lF and 471lF. A ferrite bead may be
added in series with the positive supply to form a low
pass filter and further improve the power supply local to
the GENDAC. It will also reduce EMI.
The combination of series impedance in the ground supply
to the GENDAC, and transients in the current drawn by
the device will appear as differences in the GND voltages
to the GENDAC and to the digital devices driving it. To
minimize this differential ground noise, the impedance in
the ground supply between the GENDAC and the digital
devices driving it should be minimized.

Digital Output Information
The PCB trace lines between the outputs of the TTL
devices driving the GENDAC and the input to the GENDAC behave like low impedance transmission lines driven
from a low impedance transmission source and terminated with a high impedance. In accordance with transmission line principles, signal transitions will be reflected
from the high impedance input to the device. Similarly,
signal transitions will be inverted and reflected from the
low impedance TTL output. Line termination is recommended to reduce or eliminate the ringing, particularly
the undershoot caused by reflections. The termination
may either be series or parallel.
Series termination is the recommended technique to use.
It has the advantages of drawing no DC current and of
using fewer components. Series termination is accomplished by placing a resistor in series with the signal afthe
output of the TTL driver. This matches the TTL output
impedance to that of the transmission line and ensures
that any signal incident on the TTL output is not reflected.
To minimize reflections, some experimentation will have
to be done to find the proper value to use for the series
termination. Generally, a value around lOOn will be
required. Since each design will result in a different signal
impedance, a resistor of a predetermined value may not
properly match the signal path impedance. Therefore, the
proper value of resistance should be found empirically.

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GENDAC

•
Functional Description

Bit 7-4

This section describes the register address and bit definition
for RAMDAC and the Frequency Synthesizer sections.

Bit 3 - 1 (Reserved)

Color Palette
Command Register
(RSO-RS2
(RSO-RS1

Bit 0

=011)
=01 with hidden flag)

By setting bits in the command register the ICSS340 can
be programmed for different color modes and can be
powered down for low power operation.
7
6
S
Color Mode
2
1
0

I

4

Color Mode Select
These three bits select the Color Mode of
RAMDAC operation as shown in the following
table 4 (default is 0 at power up):

3
2
1
Reserved = 0

0
Snooze

3

Power Down Mode of RAMDAC
When this bit is set to 0 (default is O), the device
operates normally. If this bit is set to 1, the
power and clock to the Color Palette RAM and
DACs are turned off. The data in the Color
Palette RAM are still preserved. The CPU can
access without loss of data by internal automatic clock start/stop control. The DAC outputs become the same as BLANK* (sync) level
output during power down mode. This bit
does not effect the PLL clock synthesizer function.

Table 3 - Command Registers

8-BIT INTERFACE
Mode
CM3 CM2 CMl CMO
Nwnber (CR4) (CR7) (CR6) (CR5)
0
1
3
2
1
1
2
3

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

l6-BIT INTERFACE
Mode CM3 CM2 CMl CMO
Number (CR4) (CR7) (CR6) (CR5)
4
S
6
7
8

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Clock Cycles!
Pixel Bits

Color Mode
8-Bit Pseudo Color with Palette (Default)
IS-Bit Direct Color with Bypass (Hi-Color)
24-Bit True Color with Bypass (True Color)
16-Bit Direct Color with Bypass (XGA)
IS-Bit Direct Color with Bypass (Hi-Color)
IS-Bit Direct Color with Bypass (Hi-Color)
16-Bit Direct Color with Bypass (XGA)
24-Bit True Color with Bypass (True Color)

1
2
3
2
2
2
2
3
Clock Cycles!
Pixel Bits

Color Mode
Muxed 16-Bit Pseudo Color with Palette
IS-Bit Direct Color with Bypass (Hi-Color)
16-Bit Direct Color with Bypass (XGA)
24-Bit Direct Color with Bypass (True-Color)
24-Bit Packed Direct Color with Bypass (True-Color)
Reserved
Reserved
Reserved
Table 4 - Color Mode Select
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ICS5340
GENDAC

Mode 2: 06-bit per pixel bypass XGA mode).
This mode is the 16-bit per pixel bypass mode and the POThe nine selectable color modes are described here. Modes P7 inputs to go to the DAC directly, bypassing the color
0-3 are 8-bit interfaces with PO-P7 bits, P8-P15 are Don't palette. The 2 bytes data is latched on two successive
rising edges and the low-byte, high-byte synchronization
Care bits.
is internally done by the rising edge of BLANK*. In this
mode, blue and red colors are 5 bits wide and green is 6
Mode 0: 8-bit Pseudo Color (one clock per pixel). This bits wide. The 2 bytes of data is packed as shown below.
mode is the 8-bit per pixel Pseudo Color mode. In this This mode can be selected by setting bits CR7-CR4 to 0110
mode, inputs PO-P7 are the pixel address for the color or 1100.
palette RAM and are latched on the rising edge of every
PCLK. This is the default mode on power up and it is I6-Bit Color Mode 2 Pixel Description
selected by setting bits CR7-CR4 to 0000. There are three
2LSB = set to zero (green)
clock cycles pipe line delays from input to DAC output.
3LSB = set to zero (blue, red)

Color Modes

8-bit Pseudo Color Mode
7 6 5 4 3 2 1 076 5 4 321 0

PIXEL BYTE
PPPPPPPP
7 6 S 4 3 2 1 0

7 6 543
RED

Mode 3: (24-bit per pixel True Color Mode).
This mode is the 24-bit per pixel bypass mode. The three
bytes of data are latched on three successive PCLK edges
and the first byte is synchronized by the rising edge of
Mode 1: 05-bit per color bypassHi-Color mode).
BLANK*. In this mode, each of the colors are 8-bit wide
This mode is the 15-bit per pixel bypass mode. In this and the DAC is an 8-bit wide DAC. The first byte is blue
mode, inputs PO-P7 are the color DATA and are input followed by green and red. This mode can be selected by
directly to the DAC, bypassing the color palette. The two setting bits CR7-CR4 to 0100 or 1110. The DAC outputs
bytes of data is latched in two successive PCLK rising changes every three cycles and the pipeline delay from
edges. ICS5340 supports only the two clock mode and the first byte to output is five cycles.
does not support the mode where the data are latched on
the rising and the falling edges. For compatibility, the 15/ 24-bit Color Mode 3 Pixel Description
16 one clock modes are selected as two clock modes in this
THIRD BYTE
SECOND BYTE
FIRST BYTE
chip. The low-byte, high byte synchronization is internally PPPPPPPP PPPPPPPP PPPPPPPP
done by the rising edge of BLANK*. Each color is 5-bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 o 7 6 5 432 1 0
wide and is packed into two bytes as shown below. This
mode can be selected by setting bits CR7-CR4 to 0010, 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 076 5 432 1 0
GREEN
BLUE
RED
1000 or 1010.
7 6 S 432 1 0
PIXEL ADDRESS

IS-Bit Color Mode 1 Pixel Description
3LSB = set to zero
SECOND BYTE
FIRST BYTE
PPPPPPPP PPPPPPPP
7 6 S 432 1 0 7 6 5 4 3 2 1 0
X\76 S 4 3\7 6 5 4 3\7 6 543
RED
GREEN
BLUE

Modes 4 - 8 use the 16-bit pixel interface.
Mode4: (8-bitPseudo Color two pixels per clock) In this mode,
inputs PO-P15 are latched ontherising edge of every PCLK. PO7 and P8-P15 are used for successive addresses for the palette
RAM using an internal clock that runs at twice the PCLK
frequency. TheDACoutputschangetwiceforeveryPCLKand
the pipeline delay from the first word to output is one and a one
half cycles. This mode can be selected by setting bits CR7-CR4
to 0001.

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GENDAC

•

Multiplexed 8-bit Pseudo Color Word Mode 4 Pixel
Mode 7: (16-bit pixel interface, 24-bit per color bypass
Description
TRUE color mode) In this mode inputs PO-PIS are the
color Data and are input directly to the DAC bypassing the
PIXEL WORD
color Palette. Two words are latched on two successive
PPPPPPPPPPPPPPPP
rising edge of PCLK to form the 24-bit DAC input. The
51413121110 9 8 7 6 5 4 3 2 1 0
first word and the lower byte of the second word form the
7 6 5 4 3 2 1
6 5 4 3 2 2 0
24-bit pixel input to the DAC. The higher byte of the
7
2nd PIXEL 01
1st PIXEL
second word is ignored. The low and high word synchroADDRESS
ADDRESS
nization is internally done by the rising edge of the
BLANK*. The pipeline delay from latching of first word to
Mode 5: (16-bit pixelinterface, IS-bit per color bypass Hi- DAC output is 4 cycles and each pixel is 2 pixel clocks
Color Mode) In this mode inputs PO-PIS are the color Data wide. In this mode, each of the colors are 8-bits wide and
and are input directly to the DAC, bypassing the color the DAC is 8-bit wide DAC. The first byte is Blue followed
palette. The Data is latched by the rising edge ofPCLK and by Green and Red. This mode is selected by setting bits
is pipelined to the DAC. The pipeline delay from input to CR7-CR4 to 0111.
DAC output is 3 PCLK cycles. Each color is S-bit wide as
shown below. This mode is selected by setting bits CR7- 24-Bit Direct Color Word Mode 7 Pixel Description
CR4 to 0011.
FIRST WORD
PPPPPPPPPPPPPPPP
51413121110 9 8 7 6 5 4 3 2 1 0

I5-Bit Color Word Mode 5 Pixel Description
3L5B = set to zero

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
GREEN
1
BLUE

PPPPPPPPPPPPPPPP
51413121110 9 8 7 6 5 4 3 2 1 0

SECOND WORD
PPPPPPPPPPPPPPPP
51413121110 9 8 76 543 2 1 0

XI7 6 5 4 317 6 5 4 317 6 5 4 3
1 RED
1 GREEN 1 BLUE

Mode 6: (16-bit pixel interface, 16-bit per color bypass
XGA mode) In this mode input PO-PIS are the color Data
and are input directly to the DAC bypassing the color
Palette. The Data is latched by the rising edge ofPCLK and
is pipelined to the DAC. The pipeline delay, from input to
DAC output, is 3 PCLK cycles. In this mode Blue and Red
colors are S bits wide, and Green is 6 bits wide. This mode
is selected by selecting bits CR7-CR4 to 0101.
I6-Bit Color Word Mode 6 Pixel Description
2L5B = set to zero (GREEN)
3L5B = set to zero (BLUE, RED)
PPPPPPPPPPPPPPPP
514131211109876543210
7 6 5 4 317 6 5 4 3 217 6 5 4 3
RED
1 GREEN
BLUE

J

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
RED

Mode 8: (16-bit pixel interface packed 24-bit per color
bypass TRUE color mode) In this mode inputs PO-PIS are
the color Data and are input directly to the DAC bypassing
the color Palette. Three words are latched on three successive rising edge of PCLK to form two successive 24-bit
DAC inputs. The 16-bit first word and the lower byte of
the second word from the first 24-bit pixel input and the
second byte ofthe second word with the 16 bits of the third
word from the second 24-bit pixel input. This cycle repeats
every 3 cycles. The three word synchronization is internally done by the rising edge of BLANK*. The pipeline
delay from latching of first word to DAC output is 3 1/2
cycles and each of the colors are 8-bits wide and DAC is 8bit wide DAC. The first byte is Blue followed by Green and
Red. Repeats. This mode is selected by setting bits CR7CR4 to 1001.

H-79

ID

ICS5340
GENDAC

Packed 24-bit Word Mode 8 Pixel Description
1st DAC Cycle
SECOND WORD

Index

RIW

Register

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

R/R/R/W
R/W
R/W
R/W
R/W
R/W
R/R/R/W
R/W
R/R/R/W
R/-

CLKO fO PLL Parameters
CLKO f1 PLL Parameters
CLKO f2 PLL Parameters
CLKO f3 PLL Parameters
CLKO f4 PLL Parameters
CLKO f5 PLL Parameters
CLKO f6 PLL Parameters
CLKO f7 PLL Parameters
(Reserved) = 0
(Reserved) = 0
CLK1 fAPLL
CLK1 fB PLL
(Reserved) = 0
(Reserved) = 0
PLL Control Register
(Reserved) = 0

FIRST WORD

PPPPPPPP PPPPPPPPPPPPPPPP
7 6 543 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
7 6 543 2 1 0 7 6 5 4 3 2 1 0\7 6 5 4 3 2 1 0
RED
GREEN
BLUE

2nd DAC Cycle
THIRD WORD

SECOND WORD

PPPPPPPPPPPPPPPP PPPPPPPP
151413121110 9 8 7 6 5 4 3 2 1 0 1514131211109 8
7 6 543 2 1 017 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RED
GREEN
BLUE

(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(l-byte)
(2-byte)

Table 5 - PLL Parameter Registers

Frequency Generators

PLL CONTROL REGISTER
The ICS5340 clock synthesizer can be reprogrammed
through the microprocessor interface for any set of
frequencies. This is done by writing appropriate values
to the PLL Parameter Register Bank (table 5).

Bits in this register determine internal or external CLKO
select.
7
6
4
3
2
1
5
0
(RV) (RV) ENBL CLK1 (RV) INTERNAL SELEC1
-0
-0 INCS SEL -0
X
X
X

PLL Address Registers
The address of the parameter register is written to the
PLL address registers before accessing the parameter
register. This register is accessed by register select pins
RS2-RSO = 100 or 111.
6 5 4 3
2 1 0
PLL REGISTER ADDRESS
7 6 5 4 3 2 1 0

Bit 7,6, 3 Reserved.
Bit 5

Enable Internal Clock Select (INCS) for CLKO.
When this bit is set to 1, the CLKO output
frequency is selected by bit 2 - 0 in this register.
External pins CSO - CS2 are ignored.

Bit 4

Clk1 Select
When this bit is set to 0, fA is selected. When it
is set to 1, fB is selected. Default isO, fA selected,
at power up.

7

PLL Parameters Registers
There are sixteen registers in the PLL parameter register
(table 5). Registers 00 to 07 are for the CLKO selectable
frequency list, Register OA for CLK1 programmable frequency and register OE is the PLL CLKO control register.

Bit 2 - 0 Internal Clock Select for CLKO (INCS).
These three bits selects the CLKO output frequency if bit 5 of this register is on. They are
interpreted as an octal number, n, that selects
fn. Default selects £0.

H-80

ICS5340
GENDAC

•
PLL Data Registers

Programming Example

The CLKO and CLKI input frequency is determined by
the parameter values in this register. These are two bytes
registers; the first byte is the M-byte and the second is the
N-byte.

Suppose an output frequency of 25.175 MHz is desired.
The reference crystal is 14.318 MHz. The VCO should be
targeted to run in the 100 to 180 MHz range, so choosing
a post divide of 4 gives a VCO frequency of :
4 X 25.175=101.021 MHz

M-Byte PLL Parameter Input
The M-byte has a 7-bit value (1-127) which is the feedback
divider of the PLL.

7
6
Reserved
=0
X

5

4
3
2
1
M-Divider Value
X
X
X
X
X

o
( 25.175).4= (M+2)
14.318
(Nl + 2)

X

N-Byte PLL Parameter Input
The N -byte has two values. N1 sets a 5-bit value (1-31) for
the input pre scalar and N2 is a 2-bit code for selecting 1,
2,4, or 8 post divide clock output.
7
6
5
4
3
2
1 0
Reserved N2-Code
N1-Divider Value
X
X
X
X
X
X X
=0

by trial and error:
( 25.175) . 4 ~ 127
14.318
18
so
M + 2 = 127
Nl + 2 = 18

M=125
Nl = 16

so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = 0 & N2 code & N1 = 0 & 1 0 & 1 0 0 0 0
N=01010000b

N2 Post Divide Code
If mode 4 is set in the command register, CR7-CR4 equal
0001, N2 code must be 10.

N2code
00
01
10
11

From the table in the previous section, we find N2 = 2
Substituting FREF = 14.318 and 2N2 = 4 into the equation on
page 17:

Divider
1
2
4
8

Additional Information on Programming the
Frequency Generator section of the GENDAC
When programming the GENDAC PLL parameter registers, there are many possible combinations of parameters
which will give the correct output frequency. Some
combinations are better than others, however. Here is a
method to determine how the registers need to be set:

The block diagram of the PLL clock synthesizer is shown
in figure 3.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
(M+2) x Fref
Fout = - - - - (Nl+2) x2N2
M and N values should be programmed such that the
frequency of the VCO is within the optimum range for
duty cycle, jitter and glitch free transition. Optimum duty
cycle is achieved by programming N2 for values greater
than one. See the next section for programming example.

The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
1. 2 MHz < fREF < 32 MHz
This refers to the input reference frequency. Most
users simply connect a 14.318 MHz crystal to the
crystal inputs, so this is not a problem.
2. 600 kHz < fREF .'S. 8 MHz
(Nl+2)
This is the frequency input to the phase detector.

H-81

ICS5340
GENDAC

•

and (Nl +2) combinations can usually be found.
Usually, a few minutes trying out numbers with a
calculator will produce a workable combination.
Multiplying possible values of (Nl +2) by the desired
ratio will indicate approximately the value of M. This
method is shown in the example below. A program
could be written to try all possible combinations of
(M+2) and (Nl +2) (3937 possible combinations), discard those outside error band, and select from those
remaining by giving preference to ratios which use
lower values of (M+2). Lower values of (M+2) and
(Nl +2) provide better noise rejection in the phase
locked loop.

3. 60 MHz .'S. (M+2) fref .'S. 270 MHz
(Nl+2)
This is the VCO frequency. In general, the VCO
should run as fast as possible, because it has lower
jitter at higher frequencies. Also, running the VCO at
multiples of the desired frequency allows the use of
output divides, which tends to improve the duty
cycle.
4. fCLKO and fCLK! .'S. 135 MHz
This is the output frequency.
These rules lead to the following procedure for determining the PLL parameters, assuming rules 1 and 4 are
satisfied.

A. Determine the value of N2 (either 1, 2, 4 or 8) by
selecting the highest value of N2, which satisfies the
condition N2* fCLK .'S. 270 MHz
B. Calculate

(M+2)
(Nl+2)

=

2N2fout
fref

C. Now (M+2) and (Nl+2) must be found by trial and
error. With a 14.318 MHz reference frequency, there
will generally be a small output frequency error due
to the resolution limit of (M+2) and (Nl+2). For a
given frequency tolerance, several different (M+2)

Example: Suppose we are using a 14.318 MHz reference
crystal and wish to output a frequency of 66 MHz with an
error of no greater than 0.5%. What are the values of the
PLL data registers?

A. 66*8 = 528 > 250
VCO speed too high
66*4 = 264 > 250
VCO speed too high
66*2 = 132 < 250
VCO speed OK, N2 = 2, N2 code
= 01 from table on page 17 of the data sheet.
B. 132/14.31818 = 9.219
This is the desired frequency multiplication ratio.
C. Setting (Nl+2) = 3,4,. .. 12, 13 and performing some
simple calculations yields the following table:
(Note that Nl cannot be 0).

(Nl+2)

(Nl +2)*9.219

rounded (=M+2)

Actual Ratio

Percent Error

3
4
5
6
7
8
9
10
11
12
13

27.657
36.876
46.095
55.314
64.533
73.752
82.971
92.19
101.409
110.628
119.847

28
37
46
55
65
74
83
92
101
111
120

9.33
9.25
9.20
9.17
9.29
9.25
9.22
9.20
9.18
9.25
9.23

-1.23
-0.34
0.21
0.57
-0.72
-0.34
-0.03
0.21
0.40
-0.34
-0.13

H-S2

ICS5340
GENDAC

•
The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2)
= 83; M = 81. The M-byte PLL parameter word is simply
81 in binary, plus bit 7 (which must be set to 0), or
01010001. The N-byte PLL parameter word is N2 code
(01) concatenated with 5 bits of N2 in binary (00111), or
00100111. Once again, bit 7 must be zero.
We have chosen the combination with the least frequency
error, but several other combinations are within the 0.5%
tolerance. Because the lowest value of (M+2) offers the
best damping, the 37/4 combination will have the best
power supply rejection. This results in lower jitter due to
external noise.

N2
CNTR

IF

r--!
Oll

Figure 3 - PLL Clock Synthesizer Block Diagram

eS2
0
0
0
0
1
1
1
1

External Select
eSl
0
0
1
1
0
0
1
1

(Internal Select PLL Control Register)
eso

BIT 2

BIT 1

BIT 0

eLK 0 Frequency

0
1
0
1
0
1
0
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

fO
f1
f2
f3
f4
f5
f6
f7

I

Video Clock Selection Table

H-83

ICS5340
GENDAC

•
PLCK

PooP?

BLANK*

U \]jJ

\]jJ \<\ ['7\

!i1

\]jJ \]jJ \]jJ \3J \]jJ \]

RED

System Timing - Pseudo Color, Mode 0

PLCK

PooP?

BLANK*

c

RED

GREEN

BLUE

~BLANK---BLANKJ

C~BLANK---BLANKJ
-A~B

C

LBLANK---BLANK~

Detailed Timing Specifications - Pseudo Color, Mode 0

H-84

ICS5340
GENDAC

•
PCLK

BLANK

PO-P7

DAC-RD
DAC~R

A._ _~/B-

--t---------------------'--/

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+-J/r--A~B-

~A._ _~/B-

DAC-BL

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~--J

System Timing Bypass· 15 (51515) and 16 (5/615) Modes 1, 2

Ons

25ns

50ns

75ns

lOOns

l25ns

l50ns

PLCK
BLANK*

PO-P7

DAC-BL

---------------------------~/

DAGGR _______________________~-------~,r------~~
DAC-RD _ _ _ _ _ _ _ _ _ _ _ _ _ _---J;-----A---""'--~-

System Timing Bypass True Color 24 (8,8,8) Mode 3

H·SS

III

II

ICS5340
GENDAC

PCLK
ICLK
PO-P7
P8-PIS
BLANK"

System Timing - Multiplexed 8-bit Pseudo Color, Mode 4

PCLK

PO-PIS

BLANK"

RED

GREEN

I

l '/ \lJ \;3 \S7
~

"','

,

' ,

ki\'>;:;/ (:;~:,L;",.;:,:, : ' "~," "';; ~}-A~B~,---,B:::L::.:A=-N:::;K,---

, '

_ __

h;:,i;;\·<:'j';':,':Z:::\\",. \":,::,:/"~:~,;~~·',rA-.r-Bl'----'Bw.I.u;:;.A,",,N""K~_ __

BLUE
System Timing -16-bit Color, Mode 5 (5,5,5) and 6 (5,6,5)

H-86

ICS5340
GENDAC

II
PCLK

PO-PI 5

BLANK"

I

\J \ .\ r \ / 7 \J \J 'CJ

RED

GREEN

BLUE

System Timing -16-bit Direct True Color, Mode 7

III

PCLK

PO-P15

BLANK'/

GREEN

BLUE

fL"_ '

V V \ '\ 0 0 (',7 V D \5J \5J/ L
-'-'-----------1)--A~B---BLANK---BLANK~

I _______
'"
~,

. \r--A~B

',_,_'_~'~__~~_J/

System Timing - 24-bit Packed Color, Mode 8

H·87

r--

~B~-----BUNK~

ICS5340
GENDAC

WR'
RSO-RS1

00-07

Basic Write Cycle Timing

RD'
RSO-RS1

00-07

Basic Read Cycle Timing

\,--_tw~-'HWR'
RD'
RSO

RS1

Write to Pixel Mask Register Followed by Write

Write to Pixel Mask Register Followed by Read

WR'
RD'

Read from Pixel or Pixel Address Register
(Read or Write) followed by Write

Read from Pixel or Pixel Address Register
(Read or Write) followed by Read

H-88

ICS5340
GENDAC

II

t=

~. .~
tWHAl3

WR*

RO*

~-------------------------------

RSO

V

RS1

V

RS2

00-07

'\
'\
/ ...

~
~

ADDRESS

~

ADDRESS

7
7

\

\
'!--------<

t

... j

\
ADDRESS +1

)f----------------------------

ADDRESS

)f----------------------------

WR*

RO*

RSO

RS1
RS2

00-07

'r----J"

Write and Read Back Pixel Address Register (Write Mode)

WR*

RO*

Read Color Value then Pixel Address Register (Read Mode)

H·89

II

ICS5340
GENDAC

•
WR"

D" '-' "U" '-' "U" ,-, t~
,

tWHRL2

RO"

'L

RSO

RS1

RS2
ADDRESS ~~

00-07

RED

~--(

GREEN

~--(

BLUE

Color Value Write followed by any Read

WFr

---u ,-, U

'-, U ,-, U ,- L

RO"

RSO

RS1

RS2

00-07

~
ADDRESS } - - - {

RED

} - - - - - - { GREEN } - - - - - - {

Color Value Write followed by any Write

H-90

BLUE

ICS5340
GENDAC

II
WR'

RO'

RSO

RS1

v

v

WMB'
;;,yt~'<'".\
1:''''W-~,,~:}::\/L'~:':'''115J';;\
f:e.'~~
\<2,',}:~~1f~,'",,-~':,.f'-L--------'_""'"
'~""-,~,,-'''~,-,,,.;,,-,~,'(,"-}3-'---_L~__'.':~·_'_'y:~'_:'"",lli!,,--,:"~l...l.}_---L.f",,",',))C!l!;l!jtjW~"~

RS2

00-07

ADDRESS }-----{

RED

} - - - - - { GREEN ) - - - - {

BLUE

}--~f-"fl!f!;'lr"l

Color Value Read followed by any Read

WR'

RO'

RSO

RS1

v

'i.~~
V,-",~;""")J-"",'~",,,-~;',,--------,-"{='~f...:;,l;=,'t.:.;';;i,,",A _--1,/fft"""";';;='G,"",~....
,;,.....
$~"-------,,,,~~,,,,,,~

RS2

00-07

Color Value Read followed by any Write

H·91

ICS5340
GENDAC

•
WR'

C

. .~

~

tWHRL3

RO'

~--------------------------------

RSO

RS1

"'--~_--1./-,,(~-,,('-,,:::'-,,'o;--"\_~!"-;-:.""~'~~~~-,,:-,,~.,. .'. .~~~-'"'-"/'~,",--,I
\;;~ ;:;)

RS2

00-07

----<

\::~ .'

ADDRESS )-----\ ADDRESS

",;,

'I

",,;' '>; .,'

;,

)1-----------------------------

Write and Read back PLL Address Register (Write Mode)

WR'

RO'

RSO

RS1

RS2

00-07

----<

ADDRESS)-----\ ADDRESS

)>-------------------------------

Write and Read back PLL Address Register (Read Mode)

H-92

ICS5340
GENDAC

•
WR'
RO"

RSO

RS1

RS2

-yo ,.~" "lAFLrl-~

~

U

\

/

U
U

\

\ c=\ c=\

\

/ ~ ~

00-07

PLLADDRESS

Read Two bytes PLL Register then PLL Address Register

WR'

RO'

RSO

LJ

RS1

LJ \
LJ

RS2

00-07 -----{

\

ADDRESS

~------------

Read One Byte PLL Register then PLL Address Register

H-93

II

ICS5340
GENDAC

Monitor SENSE Signal
RED,
GREEN,
BLUE

/
.335V

V
'soD

SENSE

"----The high performance of which the ICS5340 GENDAC is
capable is dependent on careful PC board layout. The use of a four layer
board (internal power and ground planes, Signals on the two surface

layers) is recommended. The layout below shows a suggested
configuration.
The ground plane is continuous, but the power plane is
separated into analog and digital sections as shown Power is
supplied to the analog power plane through the ferrite bead, and
bypassed at the power entry point by C3, a 10 I1F tantalum capacitor.
These high current connections should have multiple vias to the
ground and power planes, if possible. Power connections should be
connected to the analog or digital power plane, as shown in the
diagram. Power pins 5 and 29 should be connected to digital power,
power pins 20 and 24 to analog power. Decoupling capacitors
(indicated by C1 and C2) should be placed as close to the GENDAC
as possible.
The analog and digitall! 0 lines are not shown. Analog
signals (DAC outputs, Vref, Rset) should only be routed above the
analog power plane. Digital signals should only be routed above the
digital power plane.

Recommended Layout
c:::JOCJ
Cl -

C2

ooooooooo~oo

DIGITAL
Power Plane

~~~~~~~~~~~t~~~~t

0
0
0
0
0
0
0

0-0

-0
0
0
0
0
0
0
0
0

43

61
62
63

0

64

65

~-

65
66

67

ICS5340

68

35
34
33
32
31
30

2
3
4

5

0+
Cl
C2

C3
FBl
Rl
R2
Y1

0
0
0

c::JoOC:J
D-C::J ~u
C2
0
Analog Power
0
Plane Island
0
o--c:::::J-C:J~+

7
8

Cl

0_

0
0

C2
VIA to ground plane
VIA to power plane
,Oluf chip capacitor
,1u£ chip capacitor
10uf tantulum capacitor
Ferrite Bead
140 ohm 1% resistor
100 ohm 5% resistor
parallel resonant crysal cut for C L = 12 pf

H-94

0
0
0
0

0
0
0

0
0
0
0
0

ICS5340
GENDAC

Ordering Information
ICS5340V
Example:

T

ICS TXXXX
_

TL--___

Package Type
V=PLCC

' - - - - - - - Device Type (consists of 3 or 4 digit numbers)
PrefIX
lCS, AV =Standard Device; GSP=Genlock Device

III

0-95

H-96

II

ICS5341
GENDAC

Integrated
Circuit
Systems, Inc.

Advance Information

16-Bit Integrated Clock-LUT-DAC
General Description

Features

The ICS5341 GENDAC is a combination of dual programmable clock generators, a 256 x 18-bit RAM, and a triple
8-bit video DAC. The GENDAC supports 8-bit pseudo
color applications, as well as IS-bit, 16-bit and 24-bit True
Color bypass for high speed, direct access to the DACs.

• Designed for compatibility with Tseng Labs VGA
controllers
• Triple video DAC, dual clock generator, and a
color palette
• 24, 16, 15, or 8-bit pseudo color pixel mode
supports True Color, Hi-Color, and VGA modes
• High speed 256 x 18 color palette (135 MHz) with
bypass mode and 8-bit DACs
• Two fixed, six programmable video (pixel) clock
frequencies (CLKO)
• Two programmable memory (controller) clock
frequency (CLKl)
• DAC power down in blanking mode
• Anti-sparkle circuitry
• On-chip loop filters reduce external components
• Standard CPU interface
• Single external crystal (typically 14.318 MHz)
• Monitor Sense
• Internal voltage reference
• 135 MHz (-3),110 MHz (-2) & 80 MHz (-1) versions
• Very low clock jitter
• Latched frequency control pin

The RAM makes it possible to display 256 colors selected
from a possible 262,144 colors. The dual clock generators
use Phase Locked Loop (PLL) technology to provide
programmable frequencies for use in the graphics subsystem. The video clock contains 8 frequencies, 6 of
which are programmable by the user. The memory clock
has two programmable frequency locations.
The three 8-bit DACs on the ICS5341 are capable of
driving singly or doubly-terminated 75Q loads to nominal 0 - 0.7 volts at pixel rates up to 135 MHz. Differential
and integral linearity errors are less than 1 LSB over full
temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather
than by modifying the color palette.
ICS is the world leader in all aspects of frequency (clock)
generation for graphics, using patented techniques to
produce low jitter video timing.

Block Diagram

t

KLK---------------

DO-D7

PCLK

RD*-+-

IlP - INTERFACE

RSU-2~
STROBE

-!:===Ff==;-t
I----------------'-------------------------+- CLKO

XOUT

Rf---------------------------------------_

ICS5341RevA1193

H-97

CLK1

ID

ICS5341
GENDAC

•

Advance Information

Pin Configuration

N/C
N/C
N/C
WR*
RS2
RSI
RSO
CVDD
XIN
XOUT
CGND
CLKI
CGND
N/C
N/C
N/C
N/C

GENDAC II
ICS5341

N/C
N/C
Pl2
Pll
PIO
P9
P8
P7
P6
DVDD
P5
AGND
P4
P3
P2
N/C
N/C

Rev 1.0

Pin #
68,1-7

Type
I/O

RD*

8

Input

WR*

13

Input

RS2
RSI
RSO
CVDD
XIN
XOUT
CGND

14
15
16
17
18
19
20

Input
Input
Input

Symbol
D7-DO

-

Input
Output
-

Description
System data bus I/O. These bidirectional Data I/O lines are used by the
host microprocessor to write (using active low WR*) information into,
and read (using active low RD*) information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR* latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD* determines the end of the read
cycle. When RD* is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tri-state mode.
RAM/PLL Read Enable, active low. This is the READ bus control signal.
When active, any information present on the internal data bus is available
on the Data I/O lines, 00-07.
RAM/PLL Write Enable, active low. This signal controls the timing of the
write operation on the microprocessor interface inputs, 00-07.
Register Address Select O. These inputs control the selection of one of the
six internal registers. They are sampled on the falling edge of the active
enable signal (RD* or WR*).
Crystal oscillator and CLKO power supply connect to AVDD.
Crystal input. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
VSS for CLKO. Connect to ground.

H-98

ICS5341
GENDAC

•

Advance Information

Pin Description (continued)
Symbol

Pin #

Type

CLKI
CGND
CLKO

21
22
28

Output

CVDD
CSO

29
30

Input

CSI

31

Input

CS2

32

Input

VREF

33

I/O

RSET

34

Input

SENSE*

35

Output

AVDD
BLUE
GREEN
RED

37
36
38
39

Output
Output
Output

STROBE
PO - PIS

40
41- 42
46-48,50

Input
Input

49
51
65
52-58,
62-64

-

Input

BLANK*

66

Input

DGND

67

-

-

Output

-

-

Description
Memory clock output. Used to time the video memory.
VSS for CLKI. Connect to ground.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
CLKI Power Supplv. Connect to AVDD.
Clock select O. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 1. The status of CSO-2 determine which frequency is selected
on the CLKO (video) output. Latched by STB.
Clock select 2. The status of CSO-2 determine which frequency is selected
on the CLKO(video) output. Latched bv STB.
Internal Reference Voltage. Normally connects to a 0.1J.! cap to ground.
To use an external Vref connect a 1.235V reference to this pin.
Resistor Set. This pin is used to set the current level in the analog outputs.
Tt is usuallv connected throu!!h a 140Q 1% resistor to ground.
Monitor Sense, active low. This pin is low when any of the red, green,
or blue outputs have exceeded 335mV. The chip has on-board comparators and an internal 335mV voltage reference. This is used to detect
monitor type.
DAC power supply. Connect to AVDD.
Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value.
These outputs are typically used to drive a CRT monitor.
Latches the input clock select signals CSO - CS2.
Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
"ho1lkl hp "Tmmcl~cI i{thp\i "TP not 1I"pcI

AGND
DVDD
PCLK

DAC Ground. Connect to Q:round.
Digital power supply.
Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address and BLANK* inputs. This clock also controls the progress of
these values through the three-stage pipeline of the Color Palette RAM,
DAC and outputs.
Composite BLANK* Signal, active low. When BLANK* is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette mav still be updated throuQ:h DO-D7 durinQ: blankinQ:.
Digital Ground. Connect to ground.

H-99

III

ICS5341
GENDAC

Ordering Information
ICS5341V
Example:

TT ¥'-----Pa~::.c~
ICS

' - - - - - - - Deriee Type (consists of 3 or 4 digit numbers)
Pref"1X
ICS, AV=Standanl Device; GSP=GenIock Device

H·I00

~
~

ICS5342
Integrated
Circuit
Systems, Inc.

Advance Information

16 bit integrated Clock, Palette Ram and DACs

Sense

P7-PO
(A-b)

Blue

Reset

VREF
()O. 07
v.R •

PClJ(

RO'

RSO-2

CSO-l
Xlalln
XlaIOu1

CtKl ClKO

Features:
•

Triple 8 bit video DAC, dual clock generators, 256x6x3 palette, 16 bit pixel port

•

Dynamic mode switch allows switching of color depth on a pixel by pixel basis. Ideal for
multimedia video in a window applications

•

Supports 8 bit pseudo, 15 bit, 16 bit hi-color and 24 bit true color (packed and sparse) modes

•

On-chip loop filters reduce external

•

Eight programmable pixel clock frequency locations.

•

Two programmable memory clock frequency locations

•

II

compon~nts

DAC power down during blanking.

•

Internal voltage reference

•

Anti-sparkle circuitry

..

Standard CPU interface, single external crystal (typically 14.318 MHz)

•

Very low clock jitter

Revision Bl

06/08194
H-lOl

ICS5342

Color Modes:
8 bit interface
Mode CM3 CM2 CM1 CMO COLOR MODE
number

CLOCK
CYCLES!
PIXEL
BITS

0

0

0

0

0

8 bit pseudo color with palette

1

1

0

0

0

1

15 bit direct color with bypass

2

3

0

0

1

0

24 bit true color with bypass

3

2

0

0

1

1

16 bit direct color with bypass

2

1

0

1

0

0

15 bit direct color with bypass

2

1

1

0

1

15 bit direct color with bypass

2

2

0
0

1

1

0

16 bit direct color with bypass

2

3

0

1

1

1

24 bit true color with bypass

3

Mode CM
number
3

CM
2

CM
1

CM
0

16 bit interface
COLOR MODE

Muxed 16 bit pseudo color with
palette

CLOCK
CYCLES!
PIXEL
BITS

4

1

0

0

0

5

1

0

0

1

15 bit direct color with bypass

1

6

1

0

1

0

16 bit direct color with bypass

1

7

1

0

1

24 bit true color with bypass

2

8

1

1

1
0

1

24 bit packed true color with bypass

Revision B

1/2

3/2

06108/94
H·102

ICS5342
Mode Select Operation:
The mode select pin MSW will toggle the chip between the primary mode and the
secondary mode when "mode Enable Bit, " bit 2 of the Control Register is set MSW will
switch between two modes- 8 bit pseudo color (mode 0 ) and 16 bit pixel interface 16 bit
direct color bypass mode ( mode 6 ). If mode 0 is selected MSW = 0 will select the
primary mode 0 and MSW =1 will select the secondary mode as mode 6 and MSW =1
will select the secondary mode as mode o. By connecting the MSW pin to Vss the
primary color mode is always selected.
Pin Configuration:

CGND
CLKI
PI4
PIS
DO
Dl
D2
D3

GND
PCLK

P7
P6
PS
P4
P3
P2
PI

D4
D5
D6
D7

PO
XVDD
XOUT

WRo
RSO
RSI

XIN
DGND

VREF
N/C
DGND

MSW
DGND

S8-Pin PLCC
K-10

06/08194

Revision B
H-I03

ICS5342
Pin Description (68 pin PLCC)
Pin #

Type

14-21

I/O

Systems data bus I/O. These bi-directional Data I/O lines are used by
the host microprocessor to write (using active low WR*) information
into, and read (using active low RD") information from the six internal
registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL
Parameter, and Command). During the write cycle, the rising edge of
WR" latches the data into the selected register (set by the status of the
three RS pins). The rising edge of RD" determines the end of the read
cycle. When RD" is a logical high, the Data I/O lines no longer contain
information from the selected register and will go into a tn-state mode.

RD"

5

Input

RAM/PLL Read Enable, active low. This is the READ bus control Signal.
When active, any information present on the internal data bus is
available on the Data I/O lines, 00-07.

WR"

22

Input

RAM/PLL Write Enable, active low. This signal controls the timing of
the write operation on the microprocessor interface inputs, 00-07.

RS2
RS1

63

Input
Input
Input

Register Address Select O. These inputs control the selection of one of
the six internal registers. They are sampled on the falling edge of the
active enable Signal (RD" or WR").

Symbol
D7-DO

RSO
CVDD

24
23
27

-

XIN
XOUT

48

Input

49

Output

XVDD
MSW

50
25

Input

Description

Crystal oscillator and CLKO power supply connect to AVDD.
Crystal input. A 14.318 MHz crystal should be connected to this pin.
Crystal output. A 14.318 MHz crystal should be connected to this pin.
Crystal oscillator power supply. Connect to AVDD.
Mode switch. digital control for selecting primary and secondary pixel
color modes. Low selects primary mode. connect to ground if not used.

CGND

26

-

CLK1

11

Output

CGND

10

-

CLKO

8

Output

CVDD

9

-

CSO

2

Input

Oock select O. The status of CSO-1 determine which frequency is
selected on the CLKO (video) output.

CS1

3

Input

Oock select 1. The status of CSO-1 determine which frequency is
selected on the CLKO (video) output.

DGND

47

-

VREF

46

I/O

VSS for CLKO. Connect to ground.
Memory clock output. Used to time the video memory.
VSS for CLK1. Connect to ground.
Video clock output. Provides a CMOS level pixel or dot clock frequency
to the graphics controller. The output frequency is determined by the
values of the PLL registers.
CLK1 Power Supply. Connect to AVDD.

Vss for XTAL oscillator.
Inte~al Reference Voltage. Normally connects to a O.11l cap to ground.
To use an external Vref, connect a 1.235V reference to this pin.

Revision B

06/08194
H-I04

ICS5342
Pin Description (continued)
Symbol
RSET

Pin #
42

Input

SENSE·

68

Output

Type

Description
Resistor Set. This pin is used to set the current level in the analog
outputs. It is usually connected through a 1400, 1% resistor to ground.
Monitor Sense, active low. This pin is low when any of the red, green, or
blue outputs have exceeded 335mV. The chip has on-board comparators
and an internal 335mV voltage reference. This is used to detect monitor
type.

AVDD

41

-

BLUE
GREEN
RED

40
38
37

Output
Output
Output

Color Signals. These three signals are the DACs' analog outputs. Each
DAC is composed of several current sources. The outputs of each of the
sources are added together according to the applied binary value. These
outputs are typically used to drive a CRT monitor.

PO-P15

51-58,
64067,
1-4,
12,13

Input

Pixel Address Lines. This byte-wide information is latched by the rising
edge of PCLK when using the Color Palette, and is masked by the Pixel
Mask register. These values are used to specify the RAM word address
in the default mode (accessing RAM). In the Hi-Color XGA, and True
Color modes, they represent color data for the DACs. These inputs
should be grounded if they are not used.

DAC power supply. Connect to AVDD.

AGND

36

DVDD

43

-

PCLK

59

Input

Pixel Clock. The rising edge of PCLK controls the latching of the Pixel
Address and BLANK· inputs. This clock also controls the progress of
these values through the three-stage pipeline of the Color Palette RAM,
DAC, and outputs.

STROBE
BLANK·

6

Input

Latches the input clock select signals CSO-CSl.

7

Input

Composite BLANK· Signal, active low. When BLANK· is asserted, the
outputs of the DACs are zero and the screen becomes black. The DACs
are automatically powered down to save current during blanking. The
color palette may still be updated through DO-D7 during blanking.

DGND

44

-

DAC Ground. Connect to ground.
Digital power supply.

Digital Ground. Connect to ground.

Revision B

06108194
H-IOS

ICS5342
Internal Registers
RS2

RSl

RSO

Register
Name

Description
(all registers can be written to and read from)

There is a single Pixel Address register within the GENDAC. This
register can be accessed through either register address 0,0,0 or register
address 0,1,1. A read from address 0,0,0 is identical to a read from
address 0,1,1.
Writing a value to address 0,0,0 performs the following operations:
a) Specifies an address within the color palette RAM.
b) Initializes the Color Value register.
Writing a value to address 0,1,1 performs the follOWing operations:
a) Specifies an address within the color palette RAM.
b) Loads the Color Value register with the contents of the location in the
addressed RAM palette and then increments the Pixel Address register.

o

o

o

Pixel Address
WRITE

Writing to this 8-bit register is performed prior to writing one or molY
color values to the color palette RAM.

o

1

1

Pixel Address
READ

Writing to this 8-bit register is performed prior to reading one or more
color values from the color palette RAM.

o

o

1

Color Value

The 18-bit Color Value register acts as a buffer between the
microprocessor interface and the color palette. Using a three bytes
transfer sequence allows a value to be read from or written to this
register. When a byte is read, the color value is contained in the least
Significant 6 bits, DO-D5 (the most Significant 2 bits are set to zero). When
writing a byte, the same 6 bits are used. When reading or writing, data is
transferred in the same order - the red byte first, then green, then blue.
Each transfer between the Color Value register and the color palette
replaces the normal pixel mapping operations of the GENDAC for a single
pixel.
After writing three definitions to this register, its contents are written tot
he location in the color palette RAM specified by the Pixel Address
register, and the Pixel Address register increments.
After reading three definitions from this register, the contents of the
location in the color palette RAM specified by the Pixel Address registers
are copied into the Color Value register, and the Pixel Address register
increments.

Revision B

06/08/94

H-I06

ICS5342
Internal Registers (continued)
RS2

RSl

RSO

1

0

0

Register
Name
Pixel Mask

Description
(all registers can be written to and read from)
The 8-bid Pixel Mask register can be used to mask selected bits of the Pixel
Address value applied to the Pixel Address inputs (PO-P7). A one in a
poSition in the mask register leaves the corresponding bit in the Pixel
Address unaltered, while a zero sets that bit to zero. The Pixel Mask
register does not affect the Pixel Address generated by the microprocessor
interface when the palette RAM is being accessed. The I.D. register will
be read on the forth consecutive read of the mask register. I.D. for this
part is 10110001.

Revision B

06/08194
H-107

ICS5342
Functional Description
Bit 7-4

Color Mode Select
These three bits select the Color Mode of
RAMDAC operation as shown in the ICS5340
data sheet {default is 0 at power Up)i

This section describes the register address and bit

definition for RAMDAC and the Frequency Synthesizer
sections.

Color Palette
Command Register
(RSO-RS2 = 011)
(RSO-RS1 = 01 with hidden flag)

Bit 3,1

(Resewed)

Bit 2

Mode enable ME
When this bit is set to 0 (default is 0), mode
switch is disabled. If this bit is set to 1, the
MSW pin will be enabled.

By setting bits in the command register the IC55340 can
be programmed for different color modes and can be
powered down for low power operations.

Bit 0

Power Down Mode of RAMDAC
When this bit is set to 0 (default is 0), the
device operates normally. If this bit is set to
1, the power and dock to the Color Palette
RAM and DACs are turned off. The data in
the Color Paiette RAM are still preserved
The CPU can access without loss of data by
internal automatic dock start/stop controL
The DAC outputs become the same as
BLANK· (sync) level output during power
down mode. This bit does not effect the PLL
clock synthesizer function.

7

6

5

Color Mode
2

1

0

1

4

3

2

1

3

=0

ME

=0

0
Snooze

Table 3 - Command Registers

Ordering Information
ICS5342V
Example:

TTxx~x_x_T
ICS

____

Package Type
V=PLCC

Device Type (consists oC 3 or 4 digit numbers)
PreC"1X
ICS, AV";Standard Device; GSP=Genlock Device

06/08194

Revision B
H-108

les
Power Management
Products

rcs has a full line of intelligent NiCd and NiMH battery charge controllers for
portable consumer electronic, power tool, audio/video and communications equipment. Each controller provides multiple charge termination methods and charge
rates that provide a successful, cost effective battery charging solution.
The features available in the rcs controller line satisfy charging system requirements whether simple or complex, standard or custom. rcs has the analog and
digital blocks to create custom solutions for battery gauging and monitoring, charge
controllers for new or special battery chemistries, and controllers for sequential
battery charging.

II

1-1

ICS Power Management Products
NiCd and NiMH Battery Charge Controller
Selection Guide
Charge Termination
Methods

ICS
Device Type

Charge
Rates

Description

Package
Types

Voltage Slope
Maximum Temperature
Charge Timer

ICS1700A

Four Rates
(CI2 to 4C)

Hot Battery Shutdown.
Cold Battery Charge.

16-PinDIP
2O-PinSOIC

1-3

Voltage Slope
Temperature Slope
Maximum Temperature
Charge Timers

ICS1702

Nine Rates
(Cf4 to 4C)

Six Auxiliary Modes.
Hot Battery Shutdown.
Cold Battery Charge.
Adjustable Battery Detection.

20-PinDIP
2O-PinSOIC

1-27

Four Rates
(CI2 to 4C)

Hot Battery Shutdown.
Cold Battery Charge.

16-PinDIP
16-PinSOIC

I-57

Nine Rates
(Cf4 to 4C)

Six Auxiliary Modes.
Adjustable Battery Detection.

16-PinDIP
16-PinSOIC

1-79

Voltage Slope
Temperature Slope
Maximum Temperature
Charge Timer
Voltage Slope
Charge Timers

ICSl712

ICSl722

Page

Note: C=Amperelhour capacity of battery.

Integrated Circuit Systems, Inc. (lCS) shall be held harmless for any misapplication of this device such as: exceeding the rated
specifications of the battery manufacturer; charging batteries other than nickel-cadmium and/or nickel metal hydride type;
personal or product damage caused by the charging device, circuit, or system itself; unsafe use, application, and/or manufacture
of a charging system using this device.

ADVANCE INFORMATION documents contain infonnation on new products in the sampling or preproduction phase of development. Characteriatic data
and other apecificationa are subject to change without notice.
PRODUCT PREVIEW documenta contain infonnation on products in the formative or design phase of development. Characteriatic data and other specifications
are design gosls. ICS reserves the right to change or discontinue these producta without notice.

1-2

ICS1700A

Integrated
Circuit
Systems, Inc.

•

QuickSaver@ Charge Controller for Nickel-Cadmium
and Nickel-Metal Hydride Batteries
General Description

Features

The ICS1700A is a CMOS device designed for the intelligent
charge control of either nickel-cadmium (NiCd) or nickel-metal hydride (NiMH) batteries. The controller uses a pulsed-current charging technique together with voltage slope
termination. The ICS1700A employs a four stage charge sequence that provides a complete recharge without overcharging. The controller has four user-selectable charge rates
available for customized charging systems. The ICS1700A is
a pin-for-pin replacement for the original ICS 1700 controller.

•

The ICS1700A monitors for the presence of a battery and
begins charging if a battery is installed within the first 10
seconds after a reset. Voltage and temperature are measured to
ensure a battery is within fast charge conditions before charge
is initiated.

•

•
•
•

•
•

Applications

Multiple charge termination methods include:
- Voltage slope
- Maximum temperature
- Charge timer
Four stage charge sequence:
- Soft start charge
- Fast charge
- Topping charge
- Maintenance charge
Reverse-pulse charging available in all charge stages
Four programmable charge rates between 15 minutes (4C)
and two hours (C/2)
Out-of-temperature range detection
- Hot battery: charger shutdown
- Cold battery: low current charge
Ten second polling mode for battery detection
Battery fault with shutdown protection

Battery charging systems for:
-

Portable consumer electronics
Power tools
Audio/video equipment
Communications equipment

Block Diagram
CHARGE ________________________,
SELECT
VOLTAGE
SENSE
2.0V

TEMPERATURE
SENSE
RESET
RC

~

r--------------,

.IT >------.

PROCESSOR

____~

POLLING/
FAULT LED
CHARGE
MODE LED
TEMPERATURE
STATUS LED
CHARGE
CONTROL
DISCHARGE
CONTROL

----------------------~

QUlckSaver IS a registered trademark of Integrated CircUit Systems, Inc

IICS1700A B94R.v01 00694

1·3

II

ICS1700A
Pin Configuration
VDD
unused

CHG
DCHG
PFN

VDD
unused

CHG
DCHG
PFN
CMN
OTN
SELO

VIN
VREF
THERM
RC

VSS
AVSS

VIN
ne

ne

CMN

VREF

ne

ne
THERM

OTN
SELO

MRN

RC

VSS
AVSS

SEL1

16-Pin DIP
K-4

MRN
SEL1

20-Pin sOle
K-7

Pin Definitions
Pin Number
DIP

SOIC

Pin
Name

Type

Definition

1

1

CHG

OUT

ActIve hIgh TTL compatIble sIgnal used to tum on an external current source to provIde current to

2

2

DCHG

OUT

ActIve lngh TIL compatIble SIgnal avmlable to tum on a dIschmge CirCllit

3

3

PFN

OUT

Pollmg fault indicator. An active low turns on an external mdIcator to show the controller IS eIther pollmg
for the presence of the battery or has determmed the battery has been removed

4

5

CMN

OUT

Charge mode mdlcator A contmuous low shows the controller is

charge the battery

III

a soft start or fast charge. The

mdICator flashes dunng the toppmg and mamtenance charges.
Out-of-temperature range mdICator An active low turns on an external indicator showing the battery IS
out of the normal fast charge temperature range

5

7

OTN

OUT

6

8

SELO

IN

7
8
9
10
11
12
13
14
15
16

9

VSS

10

AVSS

11

SELl

IN

12

MRN

IN

Master reset signal. A logic low pulse greater than 700 ms inItiates a devIce reset

13

RC

IN

An external resistor and capacItor sets the frequency of the lllternal clock.

14

THERM

IN

ThermIstor or thermal switch input for temperature sensmg

16

VREF

18

VIN

IN

Battery voltage normalIzed to one cell with an external resIstor diVIder.

19

unttsed

20

VDD

Note:

Input used WIth the SELl pm to program the deVIce for the deSIred charge rate.
---

IGround.
Ground.
Input used wIth the SELO pm to program the device for the deSIred charge rate.
-~

1.26V voltage reference.

Ground.
Device supply =+5 0 VDC

(DIP/SOIC)
Pin 6/8 has an mternal pull-up.
Pin 9/11 has an mternal pull-up.
Pm 10112 has an mternal pull-up.
Pm 12114 has an internal pull-up.

1·4

--

~

II

ICS1700A
Soft Start Charge

Controller Operation

Some batteries may exhibit an unusual high impedance condition while accepting the initial charging current, as shown in
Figure 2. Unless dealt with, this high impedance condition can
cause a voltage peak at the beginning of the charge cycle that
would be misinterpreted as a fully charged battery by the
voltage termination methods.

Charging Stages
The charging sequence consists of four stages. The application
of current is shown graphically in Figure I. The soft start stage
gradually increases current levels up to the user selected fast
charge rate during the first two minutes. The soft start stage is
followed by the fast charge stage, which continues until termination. After termination, a two hour CliO topping charge is
applied. The topping charge is followed by a C/40 maintenance
charge.

Average
Current
(not to scale)

I

Soft-Start

Fast Charge

Stage 1

o

Topping Charge

Stage 2

2 min

The soft start charge eases batteries into the fast charge stage
by gradually increasing the current to the selected fast charge
rate. The gradual increase in current alleviates the voltage
peak. During this stage, only positive current pulses are applied
to the battery. The duty cycle of the applied current is increased
to the selected fast charge rate, as shown in Figure 3, by
extending the current pulse on every cycle until the pulse is
about one second in duration. The initial current pulse is
approximately 200ms. The CMN indicator is activated continuously during this stage

Maintenance Charge

Stage 3

Stage 4
termination + 2 hours

termination

Time (not to scale)

"

Figure 1: Graphical representation of average current levels during the four charging stages

II

155
154
153

a;

~
.:::.

0

152
151
150

Q)

Cl

$

0

>

149
148

High Impedance
Voltage Spike

~

147
146
145
Time (Samples)

Figure 2: High impedance voltage spike at the beginning of charge
1-5

ICS1700A
Initial Pulse
Width

Initial Pulse
Width

Initial Pulse
Width

~

~
I
I

~ jE-- time
i~crement

~

I

/

~CYCletime

~IE

I

jE--2 x increment
time

/~

7/

'*

cycle time

/~

7/

cycle time

~I

Figure 3: Cycle-to-cycle increase of the soft-start current pulse widths

Fast Charge
In the second stage, the ICS1700A applies the charging current
in a series of charge and discharge pulses. The technique
consists of a positive current charging pulse followed by a high
current, short duration discharge pulse. The cycle, shown with
charge, discharge, rest and data acquisition periods in Figure 4,
repeats every second until the batteries are fully charged.

7

The amplitude of the current pulse is determined by system
parameters such as the current capability of the charging
system, the desired charge rate, the cell capacity and the ability
of that cell to accept the charge current. The ICS1700A can be
set for four user-selectable fast charge rates from 15 minutes
(4C) to two hours (C/2). Charge pulses occur approximately
every second. The CMN indicator is activated continuously
during this stage.

rest
time

/

voltage
acquisition time

)

fast charge pulse width

discharge pulse width

1E:1(;------------- cycle time--------------~)I
Figure 4: Charge cycle showing charge and discharge current pulses

1-6

ICS1700A
The discharge current pulse amplitude is typically set to about
2.5 times the amplitude of the charging current based on
1.4VIcell. For example, if the charge current is 4 amps, then
the discharge current is set at about 10 amps. The energy
removed during the discharge pulse is a fixed ratio to the
positive charge rate. The amplitude of the discharge pulse does
not affect the operation of the part as described in this section.

Topping Charge
The third stage is a topping charge that applies current at a rate
low enough to prevent cell heating but high enough to ensure
a full charge.
The topping charge applies a CIlO charging current for two
hours. The current consists of the same pulse technique used
during the fast charge stage; however, the duty cycle of the
pulse sequence has been extended as shown in Figure 5.
Extending the time between charge pulses allows the same
charging current used in the fast charge stage so that no changes
to the current source are necessary. For example, the same
charge pulse that occurs every second at a 2C fast charge rate
will occur every 20 seconds for a topping charge rate of ClIO.
The CMN indicator flashes at a one second rate during this
stage.

A voltage acquisition window immediately follows a brief rest
time after the discharge pulse. No charge is applied during the
rest time or during the acquisition window to allow the cell
chemistry to settle. Since no current is flowing, the measured
cell voltage is not obscured by any internal or external IR drops
or distortions caused by excess plate surface charge. The
ICS1700A makes one continuous reading of the no-load battery voltage during the entire acquisition window. The voltage
that is measured during this window contains less noise and is
a more accurate representation of the true state of charge of the
battery.

~
~

cycle
time

Maintenance Charge
The maintenance charge is intended to offset the natural selfdischarge of NiCd or NiMH batteries by keeping the cells
primed at peak charge. After the topping charge ends, the
1CS1700A begins this charge stage by extending the duty cycle
of the applied current pulses to a C/40 rate. The maintenance
charge will last for as long as the battery voltage is greater than
O.5V at the VIN pin. The CMN indicator flashes at a one second
rate during this stage.

cycle

-LrI-_~>_II<6-(~~~_-_-_-_-_-_-_-:_-_-_d_e_la_y_t_im_e_ _ _ _ _ _ _----'>r-i--ti-m-e---,~

I

I

Figure 5: Representative timing diagram for topping and maintenance charge

1-7

II

ICS1700A
Charge Termination Methods

Maximum Temperature Termination
Maximum temperature can be sensed using either a NTC thermistor or a thermal switch. Maximum temperature termination
can also be bypassed if desired, although it is strongly recommended that some form of temperature termination be used.

Several charge termination schemes, including voltage slope,
maximum temperature and a fast charge timer are available.
The voltage slope method may be used with or without the
maximum temperature method. Maximum temperature and
the fast charge timer are available as backup methods.

If an NTC thermistor is used, an internal voltage threshold
determines when the battery is too hot to charge. As temperature increases, the voltage across the thermistor will drop. This
voltage is continually compared to the internal voltage threshold. If the thermistor voltage drops below the internal threshold the OTN indicator is activated and the controller shuts
do~n. The controller must be reset once the hot battery fault
condition has cleared to restart the charge sequence.

Voltage Slope Termination
The most distinctive point on the voltage curve of a charging
battery in response to a constant current is the voltage peak that
occurs as the cell approaches full charge. By mathematically
calculating the first derivative of the voltage, a second curve
can be generated showing the change in voltage with respect
to time as shown in Figure 6. The slope will reach a maximum
just before the actual peak in the cell voltage. Using the voltage
slope data, the ICS 1700A calculates the point of full charge
and accurately terminates the applied current as the battery
reaches that point. The actual termination point depends on the
charging characteristics of the particular battery.

If a thermal switch is used, a 4SOC open circuit switch is
recommended. When the thermal switch opens, an internal
pull-up at the THERM pin results in a logic high which shuts
down the controller and activates the OTN indicator. The
controller must be reset once the hot battery fault condition has
cleared to restart the charge sequence.

Cells that are not thoroughly conditioned or possess an unusual
cell construction may not have a normal voltage profile. The
ICS1700A uses an alternate method of charge termination
based on a slight decrease in the voltage slope to stop charge
to cells whose voltage profile is very shallow. This method
looks for a flattening of the voltage slope which may indicate
a shallow peak in the voltage profile. The zero slope point occurs
slightly beyond the peak voltage and is shown on the voltage curve
graph.

Maximum temperature termination can be disabled by grounding the THERM pin. See the section on Temperature Sensing
for more information.
~

Fast Charge Timer Termination
The controller uses a timer to limit the fast charge duration.
These times are pre-programmed, and are automatically adjusted in time duration according to the charge rate selected.
Fast charge timer termination is best suitcd as a safety backup
feature to limit the duration of the fast charge stage. The fast
charge timer is always enabled and cannot be disabled. See
Table 2 for more information.

18
17

a;ID

16

2:-

15

~0

Q.

E

~'"
(5

Voltage

"

2:-

0)

l!!

(5

>

14

"0

0.

Voltage Slope

Zero Slol"'e

en

13
12

Time (Samples)

Figure 6: Voltage and slope curves showing inflection and zero slope points

1·8

II

ICS1700A

Battery Polling

Battery Fault Detection

Upon power-up or after a reset is issued, any excess charge
from filter capacitors at the charging system terminals is removed with a series of discharge pulses. After the discharge
pulse series is complete, the voltage at VIN must be greater
than O.5V when a battery is present. If the voltage at VIN is
less than O.5V, the ICS1700A assumes no battery is attached
and initiates a polling sequence.

The ICS1700A will turn on the PFN fault indicator and shut
down if the battery is removed or if an open circuit occurs in
the current path anytime after fast charge has been initiated.
When in the topping charge or maintenance charge stages, a
charge pulse may not occur for several seconds. During the
period between charge pulses, the voltage at VIN should be
greater than O.5V if a battery is attached. If the voltage at VIN
is less than O.5V, the ICS1700A assumes the battery has been
removed, a fault condition is indicated by the PFN fault indicator, and the controller shuts down.

The ICS1700A then applies a lOOms charge pulse. During the
pulse, the ICS1700A monitors the VIN pin to determine if the
divided down terminal voltage is greater than the internal2.0V
reference. If the battery is present, the voltage is clamped
below the 2.0V reference when the current pulse is applied and
the fast charge stage begins immediately. If a battery is not
present, the voltage at VIN rises above the 2.0V reference and
the PFN fault indicator is activated.
The charge pulses repeat for 10 seconds. If the battery is
installed within 10 seconds, the ICS1700A will turn off the
PFN fault indicator and enter the soft start stage. If the battery
is not installed within 10 seconds, the PFN fault indicator
remains active and the ICS1700A shuts down. A reset must be
issued to restart the controller after installing the battery.

Cold Battery Charging
Cold battery charging is activated if a voltage at the THERM
pin is in the cold battery voltage range, as shown in Figure 7.
The ICS1700A checks for a cold battery before initiating fast
charge. If a cold battery is present before fast charging begins,
the ICS1700A begins a two hour ClIO topping charge (the
pulsed duty cycle is based on the selected charge rate). If the
battery is still cold after the two hour topping charge is complete, the ICS1700A begins a C/40 maintenance charge. The
maintenance charge will continue for as long as the battery
remains cold. The thermistor voltage at the THERM pin is
checked every second to see if the battery has warmed up. If
so, the ICS1700A stops the topping charge or maintenance
charge and begins a fast charge at a rate selected by the SELO
and SELl inputs. See the section on Temperature Sensing for
more information.
The CMN will flash at a one second rate, and the OTN
indicator will be active, indicating that a low current charge
is being applied to a battery that is outside the specified
temperature range for fast charging.

II

1-9

II

ICS1700A
Indicators: CMN, PFN, OTN Pins

Pin Descriptions
The ICS1700A requires some external components to control
the clock rate, sense temperature and provide an indicator
display. The controller must be interfaced to an external power
source that will provide the current required to charge a battery
pack and, if desired, a circuit that will sink discharge current.

Output Logic Signals: CHG, DCHG Pins
The CHG and DCHG pins are active high, TIL compatible
outputs. In addition to being TIL compatible, the CMOS
outputs are capable of sourcing current which adds flexibility
when interfacing to other circuitry. A logic high on the CHG
pin indicates that the charging current supply should be activated. If applicable, a logic high on the DCHG pin indicates
that the discharge circuit should be activated.
Care must be taken to control wiring resistance and inductance.
The load resistor must be capable of handling this short duration high-amplitude pulse.

The controller has three outputs for driving external indicators.
These pins are active low. The three indicator outputs have
open drains and are designed to be used with LEDs. Each
output can sink over 20mA which requires the use of an
external current limiting resistor. The three indicator signals
denote fast charge stage, topping and maintenance stages, and the
polling detect or battery fault and out-of-temperature range modes
as shown in Table I.
The charge mode (CMN) indicator is activated continuously
during the soft start and fast charge stages. The CMN indicator
flashes at a one second rate when the ICS1700A is applying
a topping or maintenance charge.
The polling fault (PFN) indicator is on when the ICS1700A
polls for a battery for the first 10 seconds. The controller
applies periodic charge pulses to detect the presence of a
battery. The indicator is a warning that these charge pulses are
appearing at the charging system terminals at regular intervals.
When a battery is detected, the indicator is turned off. The
indicator is also active if the battery is removed from the
system, warning that a fault has occured.
The out-of-temperature range (OTN) indicator is active whenever the voltage at the temperature sense (THERM) input
enters a range that indicates that the attached battery is too hot
to charge. The OTN indicator is also activated with the CMN
indicator if the controller is initialized with the battery in the
cold battery charge region.

Table 1: Indicator Description List
PFN

CMN

Polling mode or battery fault
Maintenance and topping charge

flash

Fast charge

on

on

Description

OTN

on

Hot battery shutdown

flash

on
on

on

on

see Applications Information

one flash

Cold battery charge
see Applications Information

1·10

[I~

ICS1700A
Charge Rate Selection: SELO, SELl Pins
The SELO and SELl inputs must be programmed by the user
to inform the ICS1700A of the desired charge rate. When a
low level is required, the pin must be grounded. When a high
level is required, no connection is required since each pin has
an internal 75kQ pull-up to VDD. The voltage ranges for low
(L) and high (H) are listed in Table 6, DC Characteristics. To
program the SELO and SEL I inputs, refer to the Charge Rate List
in Table 2.

The ICS1700A does not control the current flowing into the
battery in any way other than turning it on and off. The required
current for the selected charge rate must be provided by the
user's power source. The external charging circuitry should
provide current at the selected charge rate. For example, to
charge a 1.2 ampere hour battery in 30 minutes (2C), approximately 2.4 amperes of current is required.

Table 2: Charge Rate List
I

Maintenance Charge
Pulse Rate

Fast Charge
Timer Duration
(after reset)

SELO

SELl

L

L

4C (15 min)

one every 40 sec

one every 160 sec

30 min

L

H

2C (30 min)

one every 20 sec

one every 80 sec

60 min

H

L

IC (60 min)

one every 10 sec

one every 40 sec

90 min

H

CI2 (120 min)

one every 5 sec

one every 20 sec

210 min

H

Charge Rate

Topping Charge
Pulse Rate

See the section on Controller Operation for additional mfonnation on the toppmg charge and maintenance charge. See the section on Charge Termination
Methods for addItional mformatIOn on the charge tImer.

II

1·11

II

ICS1700A
Master Reset: MRN Pin
The MRN pin is provided to re-program the controller for a
new charging sequence. This pin has an internal pull-up of
about 75kn. A logic low on the MRN pin must be present for
more than 700ms for a reset to occur. As long as the pin is low,
the controller is held in a reset condition. A master reset is
required to change charge rates or clear a temperature fault
condition. Upon power-up, the controller automatically resets itself.

Clock Input: RC Pin
The RC pin is used to set the frequency of the internal clock
when an external 1 MHz clock is not available. An external
resistor must be connected between this pin and VDD. An
external capacitor must be connected between this pin and
ground. The frequency of the internal clock will be about I
MHz with a 16kn resistor and a 1OOpF capacitor. All time durations
noted in this document are based on a 1 MHz clock. Operating the
clock at a lower frequency will proportionally change all time
durations. Operating the clock at a frequency significantly
lower than 1 MHz, without adjusting the charge current accordingly, will lessen the effectiveness of the fast charge timer
and lower the accuracy of the controller. Operating the clock
at a frequency greater than 1 MHz will also change all time
durations and, without adjusting the charge current accordingly, may cause termination to occur due to the fast charge
timer expiring rather than by the battery reaching full charge.
The clock may be driven by a 1 MHz external 0 to 5V pulse
provided the duty cycle is between 10% and 60%. The clock
input impedance is about lkn.

• Using an NTC thermistor for hot and cold battery detection:

Thermal SWitch Temperature (OC)
Temperature> 45"C

Temperature < 45"C

50 ,

"I

:;

~

i~"

40

No charging permitted
L-~~

____________

~

35'
24V

25
20 :

Fast charge allowed

uSing a thermistor

15
05
00

due to a "hot" opened thermal SWitch
~

Cold battery charge
due to a "cold" thermistor

30 :

10

__

42V

" ' ' ' ' ' 93 V
~----I---~~-"----t----~
NocharglnQ permitted
------t----t--'=<"=o:::-~ due to a "hot" thermistor
o 5V
Fast charge allowed

due 10 a closed thermal SWitch

o

10 20 30 40 50

ThermlstorTemperature

Ie)

Figure 7: Voltage levels for temperature
senSing with a thermistor or thermal switch
The THERM pin requires some thought if a thermistor is going
to be used for hot and cold battery detection. The example
below works for a typical 10kn @ 25°C NTC thennistor.
Consider using the controller to prevent charging above 4SOC and
reducing the current below lO°e. At lOoC the resistance of the
thermistor is 18k[.!. At 45°C, the resistance drops to 4.7kn. The
ICS1700A has an internal voltage threshold at 10°C at 2.4Y, and an
internal voltage at 45°C at 0.93V as shown in Figure 7. At 25°C the
voltage at the THERM pin is set at the midpoint of the thresholds:

Temperature Sensing: THERM Pin
The THERM pin is provided for hot and cold battery detection
and for maximum temperature termination of fast charge when
used in conjunction with an NTC thermistor. The THERM pin
also provides for hot battery and maximum temperature termination when used in conjunction with a normally closed thermal switch. Several internal voltage thresholds are used by the
controller depending on whether a thermistor or a thermal
switch is used. Figure 7 shows the internal thresholds over laid
on a typical thermistor curve.

The THERM pin has a 75kn internal pull-up (Rpu). Using a
resistor divider with lOkn for the thermistor (Rth) and a
external fixed resistor (Rflx), the divider looks like Figure 8 at
25°C:

Voo

+5V

'V

Figure 8: Voltage divider at the THERM pin
at 25°C

1-12

ICS1700A
Table 3: Thermistor Voltage Thresholds

To set the voltage at the THERM pin for 1.67V at 2SoC, the
equivalent divider looks like Figure 9,

Voltage

Battery
Temperature

Cold Battery Thermistor
Voltage

>2.4

<10°C

Hot Battery Thermistor

<0.93

>4SoC

I

+5V

RII

Parameter

I

I Voltage

1.67V

THERM pin

• Using a thermal switch for hot battery detection:
A thermal switch that opens at about 4SoC is recommended.
The thermal switch must be connected between the THERM
pin and ground. When the thermal switch is closed, the voltage
at the THERM pin must be below O.SV for normal operation.
When the thermal switch opens (see Figure 10), the internal
pull-up at the THERM pin will raise the voltage above 4.2V
and the ICS1700A will shut down and will not restart unless
reset. Table 4 contains the internal voltage thresholds used with
a thermal switch.

Figure 9: Equivalent voltage divider
The parallel resistance RII is calculated:
S.OV - 1.67V
RII = _ _ _ _ _~= 20kQ.
1.67VIlOkQ
The internal pull-up resistance Rpu and the parallel resistance
RII are known so the external fixed resistor can be calculated
from:

Voo

RpuRll
Rfix= _ _ _ __
Rpu - RII

normally closed thermal switch
opens at 45 Q C

Substituting in known values: RflX = 27.27kQ. A 27kQ standard value is used for Rfix.
Since the thermistor resistance Rth is specified by manufacturers at a particular temperature, the voltage across the thermistor
Vth at that temperature can be calculated from:

Figure 10: Thermal switch to connection to
ground at the THERM pin

II

Rth
_ _ _ (5V),

Table 4: Thermal Switch Voltage Thresholds

RII +Rth

with the drop across the resistor divider equal to SY. For this
example, the calculated voltage with Rth= 18kQ at 10°C is
2.37V and with Rth=4.7kQ at 4SoC the voltage is 0.9SY. Table
3 lists the internal thresholds for hot and cold battery detection.
If the voltage across the thermistor (at the THERM pin) drops
below 0.93V, the ICS1700A will shut down due to a hot battery
fault condition and will not restart unless reset. If the voltage
dropped across the thermistor is above 2.4 V before fast charge
is initiated, the ICS1700A will begin a reduced current charge.
See the Cold Battery Charging section for more information.

1·13

Voltage

Battery
Temperature

Opened Thermal Switch
Voltage

>4.2

>4SoC

Closed Thermal Switch
Voltage

 IMQ) is required. The reference can only be used if
it is buffered with a high impedance device having an input
impedance greater than IMQ. Buffering is essentia.l to ensure
that the internal voltage thresholds and analog/dIgItal converter range and resolution are not altered.

R2

J

There are two ground pins. Both pins must be connected
together at the device. This point must have a direct connection
to a solid ground plane.

Figure 11: Resistor divider network
at the VIN pin

1-14

II

ICS1700A

Data Tables
Table 5: Absolute Maximum Ratings
Supply Voltage
Logic Input Levels

6.5

V

-0.5 to Voo + 0.5

V

o to 70

°C

-55 to 150

°C

Ambient Operating Temperature
Storage Temperature

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only. Functional operation of the device at the Absolute Maximum Ratings or other conditions not consistent with the
characteristics shown in this document is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.

Table 6: DC Characteristics
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

4.5

5.0

5.5

UNITS

Supply Voltage

Voo

Supply Current

100

High Level Input Voltage
SELO, SELl

VIH

3.6

4.1

4.5

V

Low Level Input Voltage
SELO, SELl

VIL

0.73

0.75

0.8

V

Low Level Input Current, pull-up
THERM,MRN

hL

V=OAV

74

IlA

High Level Source Current
CHG,DCHG

IOH

V=Voo-0.4V

28

rnA

Low Level Sink Current
CHG,DCHG

IOL

V=OAV

25

rnA

Low Level Sink Current, indicator
PFN,CMN

IOL

V=OAV

40

rnA

Low Level Sink Current, indicator
OTN

IOL

V=OAV

28

rnA

V
rnA

7.3

-

-

Input Impedance

MQ

1.0

AnaloglDigital Converter Range
Voltage Reference

VREF

0-2.2

0-2.7

0-2.7

V

1.20

1.26

1.31

V

Table 7: DC Voltage Thresholds
TAMB=25°C
I

TYP

UNITS

Minimum Battery Voltage

0.5

V

Maximum Battery Voltage

2.0

V

Thermistor - Cold Temperature

2.4

V

Thermistor - Hot Temperature

0.93

V

Thermal Switch - Open

4.2

V

Thermal Switch - Closed

0.5

V

PARAMETER

1-15

II

II

ICS1700A
Table 8: TIming Characteristics

R~16kn, C~100pF

PARAMETER

SYMBOL

REFERENCE

Clock Frequency

TYP

UNITS

1.0

MHz

700

ms

Reset Pulse Duration

tRESET

see Figure B

Charge Pulse Width

tCHG

see Figure A

1048

ms

Discharge Pulse Width

tDCHG

see Figure A

5.0

ms

tR

see Figure A

4.0

ms

tDA

see Figure A

16.4

ms

tCYCLE

see Figure A

1077

ms

Capacitor Discharge Pulse Width

5.0

ms

Capacitor Discharge Pulse Period

100

ms

Polling Detect Pulse Width

100

ms

Polling Detect Pulse Period

524

ms

Soft Start Initial Pulse Width

200

ms

Soft Start Incremental Pulse Width

7.0

ms

1160

ms

Rest Time
Data Acquisition Time
Cycle Time

RESET to SEL Dynamic Reprogram Period

see Figure B

tRSA

Timing Diagrams

tR

tCHG

Figure A:

CHG

-/

\

/

1\

DCHG

. . .t
OCHG
tCYCLE

Figure B:
RESET
SELO
SEL1

1-16

voltage

....

....

....

". 't ".,
R

tOA

ICS1700A
Voltage Slope Termination

Applications Information

In general, the voltage slope termination method works best
for equipment where the battery is fast charged with the
equipment off or the battery is removed from the equipment
for fast charge. The voltage slope termination method works
best with a constant current flow into the battery during fast
charge. If equipment draws a known constant current while the
battery is charging, this current should be added to the fast
charge current. Equipment that randomly or periodically requires current from the battery during fast charge needs evaluation to ensure it does not interfere with the proper operation
of the voltage slope termination method.

To ensure proper operation of the ICS1700A, external components must be properly selected. The external current source
used must meet several important criteria to ensure optimal
performance of the charging system.

VIN Divider Resistors
Figure 12 shows a typical application using the ICS1700A. RI
and R2 must be carefully selected to ensure that battery detection and voltage termination methods operate properly. Rl and
R2 are selected to scale the battery voltage down to the voltage
of one cell. The following table shows some typical values.
Additional information is available in the Voltage Input
section.

II

I

Cells

Rl

1

Short

Open

2

2.0k

2.0k

3

2.0k

l.Ok

4

3.0k

l.Ok

5

12k

3.0k

6

10k

2.0k

7

12k

2.0k

8

9.1k

l.3k

R2

I

PC Board Design Considerations
It is very important that care be taken to mmnlllze noise
coupling and ground bounce. In addition, wires and connectors
can add significant resistance and inductance to the charge and
discharge circuits.

Charging sources that produce decreasing current as fast
charge progresses may cause a voltage inflection that may
result in termination before full charge. For example, if the
charge current is supplied through a resistor or if the charging
source is a constant current type that has insufficient input
voltage, the current will decrease and may cause a termination
before full charge. Other current source characteristics that can
cause a voltage inflection that is characteristic of a fully
charged battery are inadequate ripple and noise attenuation
capability or charge current decreasing due to thermal drift.
Charging sources that have any of the above characteristics
need evaluation to access their suitability for the application.
The controller soft start stage, built-in noise filtering, and
fast charge timer operate optimally when the constant current source charges the battery at the rate selected. If the
actual charge current is significantly less than the rate selected, the conditioning effect of the soft start stage and the
controller noise immunity are lessened. Also, the fast charge
timer may cause termination based on time duration rather
than by the battery reaching full charge due to inadequate
charge current.

When designing the printed circuit board, make sure ground
and power traces are wide and bypass capacitors are used right
at the controller. Use separate grounds for the signal, charge
and discharge circuits. Separate ground planes on the component side of the PC board are recommended. Be sure to connect
these grounds together at the negative lead ofthe battery only.
For the discharge circuit, keep the physical separation between
power and return (ground) to a minimum to minimize field
radiation effects. This precaution is also applicable to the
constant current source, particularly if it is a switch mode type.
Keep the ICS1700A and the constant current source control
circuits outside the power and return loop described above.
These precautions will prevent high circulating currents and
coupled noise from disturbing normal operation.

II

1-17

II

ICS1700A
Maximum Temperature Termination

Charging System Status by Indicator

Maximum temperature termination is best suited as a safety
back-up feature. Maximum temperature termination requires
that the thermal sensor be in intimate contact with the battery.
A low thermal impedance contact area is required for accurate
temperature sensing. The area and quality of the contact surface between the sensor and the battery directly affects the
accuracy of temperature sensing. Thermally conductive adhesives may have to be considered in some applications to ensure
good thermal transfer from the battery case to the sensor.

The Indicator Description List in Table I contains displays that
are caused by charging system abnormalities. At power-up or
after a reset is issued, one flash of the CMN indicator followed
by a continuous PFN indication results from a voltage present
at the battery terminals with the current source off and no
battery. Check the current source and ensure that it produces
no more than the equivalent of 350mVfcell when turned off
with no battery. If the VIN divider resistors were not properly
selected, an open circuit voltage that is actually less than the
equivalent of 350mVfcell with the charger off and no battery
will not divide down this open circuit voltage properly and
produce a PFN fault indication. Check the VIN divider and
ensure that it properly normalizes the battery voltage to the
electrochemical potential of about 1.2V cell. If the PFN fault
indicator is active immediately after power-up or after a reset
is issued with the battery installed, then the constant current
source is producing more than the equivalent of 350mVfcell
when off and there is an open connection between the charger
terminals and the battery. Check wires, connections, battery
terminals, and the battery itself for an open circuit condition.

The thermal sensor should be placed on the largest surface of
the battery for the best accuracy. The size of the battery is also
a consideration when using temperature termination. The
larger the battery, lower the surface area to volume ratio.
Because of this, larger batteries are less capable in dissipating
internal heat.
Additional considerations beyond the basics mentioned above
may be involved when using maximum temperature termination where sudden changes in ambient temperature occur or
where forced air cooling is used For these applications, the
surface area of the thermal sensor in contact with the battery
compared to the surface area of the thermal sensor in contact
with the ambient air may be significant. Forexample, bead type
thermistors are relatively small devices which have far less
thermal capacity compared to most batteries. Insulating the
surface of the thermistor that is in contact with the ambient air
should help minimize heat loss by the thermistor and maintain
accuracy.

If the CMN and OTN indicators are active together, this is an

indication that the battery temperature has dropped to below
lOoC after a fast charge was initiated with the battery temperature normal. If this condition is observed and the battery
temperature did not drop after fast charge was initiated, check
the thermistor circuit mechanically for poor contact and electrically for excessive noise.

Enhanced Performance Characteristics
The ICS1700A is an enhanced performance, pin-for-pin replacement for the original ICS 1700. Improved internal features
provide additional capabilities. The charge sequence, voltage
slope termination method, and analog-to-digital converter
resolution allow the ICS1700A to charge either NiMH or NiCd
batteries. The ICSI700A accepts either a thermal switch or
thermistor input for temperature sensing. The polling mode for
battery detection responds quickly to the removal of the battery
throughout the charge sequence. The reset input debounce
eliminates sensitivity to field effects and ground bounce when
the PC board design recommendations cited in this document
are employed. The temperature sense input debounce eliminates sensitivity to shock and vibration associated with the use
of a thermal switch.

1-18

ICS1700A

CONSTANT
CURRENT
SOURCE
R3 (note 1)
+ 5 V (note 5)
+5V
VDD
CHG
DCHG unused
PFN
VIN
VREF
CMN
THERM
OTN
RC
SELO
MRN
VSS
AVSS
SELl

15
14
13
12
11
.10
9

Tm,,,,,,)

Rl

- - ...

+5V

1

R2

~l00PF

. i

. temperature !
.
sense
;

~J ~'~
'f!.~. 2!"~ \jJ@

(note 6)

-=Notes:
1) Value of R3 determined by discharge current and capacity of battery pack.
2) Discharge FET Is logic-level compatible in this application.
3) DC return of discharge FET must be connected close to negative battery terminal.
4) Resistor Is needed only if a thermistor is used. Value may change depending on thermistor.
5) Regulated supply
6) Power ground; others are signal ground. Connect signal ground to powell ground
at negative battery terminal only.

.

45"C

V

Figure 12: Functional Diagram

II

Ordering Information
ICS1700AN, ICS1700AM, or ICS1700AMT
Example:

ICS XXXXA M

L __
N=DIP (Elastic)
M=SOIC
MT=SOIC Tape and Reel

L-_ _ _ _ _ _ _
L -_ _ _ _ _ _ _ _ _ _

Device Type (consists of 3-5 digit numbers)
PnC~

ICS=Standard Device

1-19

1·20

II

ICS1700A

Integrated
Circuit
Systems, Inc.

Application Note

ICS1700A Evaluation Board
Table 1

General Description
The ICS1700A Evaluation Board allows quick evaluation of
the rcs 1700A Charge Controller for Nickel-Cadmium and
Nickel-Metal Hydride Batteries. The evaluation board provides the designer an opportunity to both test the rcs 1700A
and a fast charge battery charger. The board is self-contained
and has provisions for interfacing with an external constant
current source to charge a battery.

The board includes resistors that are user-installed to customize operation for the desired charge rate, discharge pulse current, and number of cells in the battery pack. The board has a
SV regulator that provides power to the rcs 1700A and the
LED display. The board also has a breadboarding area consisting of a matrix of holes for user added components.
Before using the ICS1700A Evaluation Board, rcs recommends the user review the rcs 1700A data sheet to become
familiar with the operation of the controller. This data sheet
should be included with the board; if not, please contact your
local representative.

Customizing the Board for your
Application
Refer to the evaluation board schematic diagram. The
rcs 1700Arequires that the battery voltage is normalized to the
voltage of one cell, or about 1.2Y. To do this, resistors must be
installed in the locations marked R6 and RS. The appropriate
values can be selected from Table I. An assortment of resistors
is provided with the board.

Cells

R6

RS

I

Open
2.0k
I.Ok
I.Ok
3.0k
2.0k
2.0k
l.3k

Short
2.0k
2.0k
3.0k
12k
10k
12k
9.lk

2
3
4
5
6
7
S

rf the evaluation board is used with battery packs containing
more than eight cells, the resistors can be determined by
counting the number of cells to be charged in series. Then
choose either R6 or RS and solve for the other resistor using:

=R6 x (# of cells -I)

or R6 _. ____R_S_ _
(# of cells - I)
Current flow through the divider should be O.4mA or greater
for noise immunity.
RS

The rcs 1700A controller has an internal 2.0V reference used
to detect the removal of the battery from the charging system.
For most batteries, the maximum normalized battery voltage
at the VIN pin at full charge IS 1.7 to I.Sy' The voltage at VrN
is compared to the 2.0V reference voltage when the current
source is turned on. If the voltage at VIN is greater than the
2.0V reference, the ICSI700A assumes the battery has been
removed and the ICS 1700A indicates a fault condition by
turning on the BF LED, and shuts down.
When power is applied to the board, the controller will start a
charge sequence unless a logic low is applied to the RESET
terminal. When RESET is removed by a logic high or open, a
charge sequence will begin.

I1700AEvBrdRevD102X94
1·21

II

II

Application Note

ICS1700A Evaluation Board
The board provides several low value resistors that may be
used to set the amplitude of the discharge pulse. The resistors
can be installed in any or all of the locations labeled Rl, R2,
or R3. The resistor value is calculated by setting the amplitude
of the discharge pulse. The discharge pulse amplitude is typically 2.5 times the charge current based on 1.4V/cell. The
resistor locations Rl, R2, and R3 are connected in series. The
unused locations must have a jumper to complete the circuit.
Not using the discharge pulse feature will not affect the performance of the ICS 1700A.
The ICS 1700A is capable of operating at four different charge
rates; 4C (15 minutes), 2C (30 minutes), lC (60 minutes) and
C/2 (120 minutes). The charge rate is selected by SWI dip
switch settings. Table 2 shows the proper settings to use for the
desired charge rate.

Power Requirements
The evaluation board uses a regulator to provide +5 volts for
the controller. The regulator allows operation from a DC
supply of 8 to 32 volts when the supply is connected to the +V
terminal. The board may also be operated from an external 5
volt supply by removing the regulator (VRl), wiring ajumper
between regulator pins I and 3, and by connecting 5 volts
directly to the +5V terminal.

Conne~tions

To External Circuitry

A normally closed thermal switch or a thermistor should be
connected to the TS terminal. If a thermal protection device is
not used, the TS terminal must be grounded.
Connect the battery between the +BAT and GND terminals.
Connect the external charging current source and its return
between the +CUR and GND terminals.
Two charge signals are provided to control external charging
circuitry. CHARGE is high when the charging current is on. The
other signal CHARGE is low when the charging current is on.
The charging circuitry should provide a current at an amplitude
that is equal to the product of the battery capacity and the
desired charge rate. For example, to charge a 1.2 ampere hour
battery in 30 minutes, the current required would be 2.4 amps
or 2C where 'C' is the battery capacity.
It is important to note that the ICS 1700A does not control the
current flowing into the battery in any way other than turning it
on and off. The charging source should be a constant current type.

Table 2: Charge Rate List
Charge
Rate

SWI-I
(SO)

SWI-2
(Sl)

Topping Charge
Pulse Rate

Maintenance Charge
Pulse Rate

Fast Charge
Timer Duration
(after reset)

4C (15 min)
2C (30 min)
IC (60 min)
C/2 (120 min)

ON
ON
OFF
OFF

ON
OFF
ON
OFF

one every 40 sec
one every 20 sec
one every 10 sec
one every 5 sec

one every 160 sec
one every 80 sec
one every 40 sec
one every 20 sec

30 min
60 min
90 min
210 min

1·22

Application Note

ICS1700A Evaluation Board

Operation
Before applying power to the board, ensure that the board is
properly initialized.
•
•

•

Set SWI-I and SWI-2 for the correct charge rate.
Check to make sure the divider resistors R6 and R8 are of
the correct value to normalize the battery pack voltage to
one cell.
If applicable, choose resistors RI, R2 and R3 to obtain the
required discharge current.

After applying power to the board:
•

Set the external charging current source for the amplitude
required by SWI settings.

Push and hold the reset switch SW2 for at least 700ms. All
LEDs should turn off while the switch is depressed. The green
CM LED will light and will remain lit until full charge is
detected by the ICS 1700A. At that moment, the CM LED will
start flashing at a 1 Hz rate, indicating that the topping charge
stage has begun. The CM LED will flash until a reset is issued
either by interrupting the power, removing the batteries or depressing the reset switch SW2.

Battery POlling
Upon power-up or after a reset is issued, any excess charge
from filter capacitors at the +BAT and +CUR terminals is
removed with a series of discharge pulses. After the discharge
pulse series is complete, the voltage at VIN must be greater
than 0.5V when a battery is present. If the voltage at VIN is less
than 0.5V, the ICS 1700A assumes no battery is attached and
initiates a polling sequence.
The ICS 1700A then applies a lOOms charge pulse. During the
pulse, the ICS 1700A monitors the VIN pin to determine if the
divided down terminal voltage is greater than the internal 2.0V
reference. If the battery is present, the voltage is clamped below
the 2.0V reference when the current pulse is applied and the
fast charge stage begins immediately. If a battery is not present,
the voltage at VIN rises above the 2.0V reference and the BF
LED lights immediately.

The charge pulses repeat for 10 seconds. If the battery is
installed within 10 seconds, the ICS1700A will turn off the BF
LED and enter the fast charge stage. If the battery is not
installed within 10 seconds, the BF LED remains on and the
ICS l700A shuts down. A reset must be issued to restart the
controller after installing the battery.

Battery Fault Detection
The ICS l700A will turn on the BF LED and shut down if the
battery is removed or if an open circuit occurs in the current
path anytime after fast charge has been initiated. When in the
topping charge or maintenance charge stages, a charge pulse
may not occur for several seconds. During the period between
charge pulses, the voltage at VIN should be greater than 0.5V
if a battery is attached. If the voltage at VIN is less than 0.5V,
the ICS 1700A assumes the battery has been removed, a fault
condition is indicated by the BF LED, and the controller shuts
down.

Out-of-Temperature Range
The OT LED activates if the battery is either too hot or too cold
to fast charge. If a thermistor is used, the ICS 1700A employs
internal voltage references to determine if a battery is hot or
cold. Note: Remove R9 and replace with a jumper when using
a thermistor. A 10kn @ 25°C thermistor with an external
pull-up resistor is typically used. See the ICS 1700A data sheet
for additional information.

If a thermal switch is used, choose a switch that opens at 45°C
or lower. If a thermal protection device is not used, the TS
terminal must be grounded.
ICS strongly recommends the use of a thermal safety device in
the battery pack. One source of thermal switches is Portage
Electric Products, Inc., in North Canton, Ohio; (216) 499-2727.
A source of thermistors is Semetic USA (lshizuka Electronics
Corp.), Babylon, NY; (516) 587-4086.

1·23

II

II

Application Note

ICS1700A Evaluation Board
Design Considerations
When designing external current source circuitry for use with
the ICS l700A, there are several important considerations to
make before starting the design and the PC board layout.
For the 2C and 4C charge rates, consideration has to be given
to the use of a pulse-width modulated switch mode current
source in order to reduce size and power dissipation. Switch
mode current sources can provide the ability to charge battery
packs that require voltages higher than the primary supply. For
instance, to charge a 24 volt battery from a 12 volt vehicle
battery, a switch mode boosl con verter could be used.
In general, linear chargers are less complex and more cost
effecti ve, but less efficient than switch mode chargers. For the
I C and CI2 charge rates, consideration should be given to using
a linear charger unless the size and ability to dissipate heat are
not available.
It is very important that care be taken to minImize noise

When designing the printed circuit board, make sure ground
and power traces are wide and bypass capacitors are used right
at the controller pins. Use separate grounds for the signal,
charge, and discharge circuits. Separate ground planes on the
component side of the PC board are recommended. Be sure to
connect these grounds together at the negative lead of the
battery only.
For the discharge circuit, keep the physical separation between
power and return (ground) to a minimum to minimize field
radiation effects. This precaution is also applicable to the
constant current source, particularly if it is a switch mode type.
Keep the ICS 1700A and the constant current source control
circuits outside the power and return loops described above.
These precautions prevent high circulating currents and coupled noise from disturbing proper operation.
Integrated Circuit Systems wants to help create a successful
battery charging solution using the ICS 1700A. If you need
technical advice or applications information, call the Power
Management Products Applications department at (610) 630-5300.

coupling and ground bounce. In addition, wires and connectors
can add significant resistance and inductance to the charge and
discharge circuits.

Ordering Information
ICS1700AEB

I

Device Type
ICS 1700A EvaluatIOn Board

1-24

II

(note 3)

+V~
C3
047~F

+5V~

El. CHARGE

--r--.-=====~
Rl

2~'"
G::

{~

~
(note 1)
+5V

....

~

,

+5V

R4S
lk

, ' V " R8
V'
(note 1)

I

r

R12

390

III

DSl
DS3
S
7
8

VDD
CHG
DCHG unused
PFN
VIN
VREF
CMN
THERM
OTN
RC
SELO
MRN
VSS
Sl
AVSS

•

----"

15
14

.'V"V'+~
R7

13
12

(not used)

+5V

-->

CS

R9
• 'V"V'.

E9. TS

lk

-0

[
C5

0-

(note 2)

047~F

,..£1l!e

GND

~

(not used)

+.2::!
'V

ES. +CUR
E4. +BAT

~VR2

.047~Fl

C7
100pF I

•

III

CRl
(not used)

~ ~
•

(")

-

Ell. RESET

---~:ttcEC81
SW2
___

0

0

~l~F

~

E12. GND

...
fn

""-I

0
0

l>

m

Notes.
1) Values are determined by number of cells andlor charge current, see text for details
2) Resistor R9 must be removed and replaced With a Jumper when uSing a thermistor. Use of a thermistor
reqUires an extemal pull-up resistor
3) 8 Vdc minimum Input
4) Logic level compatible FET
5) LM340, AN7805 or eqUivalent

les 1700A Evaluation Board

•

al

c

»

m

"C

0

C:;"
I»

..

....
CD

=

~

::s d:.
0
to :::l
0
m 0Z

Q.

1-26

II

ICS1702

Integrated
Circuit
Systems, Inc.

QuickSaver® Charge Controller for Nickel-Cadmium
and Nickel-Metal Hydride Batteries
General Description

Features

The ICS1702 is a CMOS device designed for the intelligent
charge control of either nickel-cadmium (NiCd) or nickel-metal hydride (NiMH) batteries. The controller uses a pulsed-current charging technique together with voltage slope and/or
temperature slope termination. The ICS1702 employs a four
stage charge sequence that provides a complete recharge without overcharging. The controller has nine user-selectable
charge rates and six user-selectable auxiliary modes available
for customized charging systems.

•

The ICS1702 monitors for the presence of a battery and begins
charging when a battery is installed. Voltage and temperature
are measured to ensure a battery is within fast charge conditions before charge is initiated.

•
•

Applications

•
•

•

•

Battery charging systems for:
Portable consumer electronics
Power tools
Audio/video equipment
- Communications equipment

•

Multiple charge termination methods include:
Voltage slope
Temperature slope
Maximum temperature
Charge timer
Four stage charge sequence:
- Soft start charge
- Fast charge
- Topping charge
- Maintenance charge
Reverse-pulse charging available in all charge stages
Nine programmable charge rates between 15 minutes (4C)
and four hours (C/4)
Out-of-temperature range detection
- Hot battery: charger shutdown
- Cold battery: low current charge
Continuous polling mode for battery detection
Six auxiliary modes include:
- Discharge-before-charge
- Ten hour CliO conditioning charge
- Direct to C/40 maintenance charge
- Charging system test provided through controller
Adjustable open circuit (no battery) voltage reference

Block Diagram
CHARGE
SELECT

POLLING
MODE LED

OPEN CIRCUIT
REFERENCE

CHARGE
MODE LED

VOLTAGE
SENSE
OUTPUT
CONTROL

PROCESSOR

TERMINATION
SELECT

MAINTENANCE
MODE LED
TEMPERATURE
STATUS LED
CHARGE
CONTROL

TEMPERATURE
SENSE

DISCHARGE
CONTROL

MODE SELECT
RESET
RC --------------------------~ OSCILLATOR
QwckSaver

Ilcs1702 694RevFl 00694

1-27

IS

a registered trademark of Integrated CirCUit Systems, Inc

II

ICS1702
Pin Configuration

VDD

CHG
DCHG
PFN
MMN
CMN
OTN

unused

VIN
OPREF
THERM
AUX1
AUXO

SELO
VSS
AVSS

DTSEL
RC
MRN

SEL1

20-Pin DIP or sOle
K-4, K·7

Pin Definitions
Pm Number

Pm Name

Type

DefInItIOn

1

CHG

OUT

ActIve hIgh TTL compatible signal used to turn on an external current source to provIde current to charge

2

DCHG

OUT

ActIve hIgh TTL compatIble SIgnal avrulable to turn on a illschruge mcUlt.

3

PFN

OUT

Polling detect mdICator. An actIve low turns on an external Indicator to show the controller IS polling for

4

MMN

OUT

Maintenance mode indIcator. An active low turns on an external Indicator showmg the battery ]s either in

the battery.

c---

the presence of the battery.
the toppmg charge, mruntenance charge or auxilIary condItIOn mode. ThIS sIgnal IS also apphed with the
out-of-temperature range mdicator when the controller IS In a cold battery charge mode The mdlcator
flashes during the auxIlIary discharge mode.

I
5

CMN

OUT

6

OTN

OUT
IN

Charge mode mdicator. An actIve low turns on an external indIcator to show the controller is either III a
soft stru1 charge or fast charge.

Out-of-temperature range indIcator. An actIve low turns on an external IndIcator showing the battery IS
out of the normal fast charge temperature range.
Tn-Ieveltnput used with the SELl ptn to program the deVIce for the deSlfed charge rate.

7

SELO

8

VSS

Ground.

9

AVSS

Ground.

10

SELl

IN

Tn-level mput used with the SELO ptn to program the device for the deslfed charge rate.

II

MRN

IN

Master reset sIgnal. A logIC low pulse greater than 700 ms 100tlates a device reset.

12

RC

IN

An external resIstor and capacitor sets the frequency of the mternal clock.

13

DTSEL

IN

Selects temperature slope and/or voltage slope terrmnatlOn

AUXO

IN

Tn-Ievelmput used wIth the AUXI pm to program the deVIce for an auxihary operating mode.

14
1-------

15

AUXI

IN

Tn-level input used with the AUXO ptn to program the deVIce for an auxilIary operating mode.

16

THERM

IN

Therlll1stor or thermal sWItch input for temperature sensmg.

17

OPREF

IN

Open CIrcuit (no battery) voltage reference An external resIstor dIVIder on thIS pm sets the open circuit

18

VIN

IN

Battery voltage normahzed to one cell wIth an external resIstor dIVIder.

19

unused

20

VDD

voltage reference used to detect the presence of a battery.

Note:

Ground.
Device supply ;+5.0 VDC

Pm 11 has an mteroal pull-up.
Pm 16 has an internal pull-up.
Pm 13 has an tnternal pull-down.
Pms 7,10, 14, 15 float to 2.3V when unconnected.

1·28

II

ICS1702
Soft Start Charge

Controller Operation
Charging Stages
The charging sequence consists of four stages. The application
of current is shown graphically in Figure 1. The soft start stage
gradually increases current levels up to the user selected fast
charge rate during the first two minutes. The soft start stage is
followed by the fast charge stage, which continues until termination. After termination, a two hour CII 0 topping charge is
applied. The tOpping charge is followed by a C/40 maintenance
charge.

Average
Current
(not to scale)

I

Soft-Start

Fast Charge

Stage 1

o

The soft start charge eases batteries into the fast charge stage
by gradually increasing the current to the selected fast charge
rate. The gradual increase in current alleviates the voltage
peak. During this stage, only positive current pulses are applied
to the battery. The duty cycle of the applied current is increased
to the selected fast charge rate, as shown in Figure 3, by
extending the current pulse on every cycle until the pulse is
about one second in duration. The initial current pulse is
approximately 200ms. The CMN indicator is activated continuously during this stage.

Topping Charge

Stage 2

2 min

Some batteries may exhibit an unusual high impedance condition while accepting the initial charging current, as shown in
Figure 2. Unless dealt with, this high impedance condition can
cause a voltage peak at the beginning of the charge cycle that
would be misinterpreted as a fully charged battery by the
voltage termination methods.

Maintenance Charge

Stage 3

Stage 4
termination + 2 hours

termination

Time (not to scale)

...

Figure 1: Graphical representation of average current levels during the four charging stages

II

155
154
1 53
Qj

.!2
!l
0

2:-

152
151
1 50

"'"
Jg

1 49

>

148

0

High Impedance
Voltage Spike

/

147
146
145
Time (Samples)

Figure 2: High impedance voltage spike at the beginning of charge

1-29

II

ICS1702
Initial Pulse
Width

Initial Pulse
Width

Initial Pulse
Width

~ r--~ time
i~crement

~

r-I~._/__~I

I

~CYCletime

~
.
~

~I__~/~/
__~I
7/-

~2

x increment

r--- time

LI------7~~~/~------

------~)oIoI!IE~----- cycle time ----~)IE_IE----cycie time ---~)I

Figure 3: Cycle-to-cycle increase of the soft-start current pulse widths

Fast Charge
In the second stage, the ICS1702 applies the charging current
in a series of charge and discharge pulses. The technique
consists of a positive current charging pulse followed by a high
current, short duration discharge pulse. The cycle, shown with
charge, discharge, rest and data acquisition periods in Figure 4,
repeats every second until the batteries are fully charged.

7

The amplitude of the current pulse is determined by system
parameters such as the current capability of the charging
system, the desired charge rate, the cell capacity and the ability
of that cell to accept the charge current. The ICS1702 can be
set for nine user-selectable fast charge rates from 15 minutes
(4C) to four hours (Cf4). Charge pulses occur approximately
every second. The CMN indicator is activated continuously
during this stage.

rest
time

/

fast charge pulse width

)

temperature
voltage
acquisition time
acquisition time
;., __

...--______________...J

rest
time

discharge pulse width
tEK:------------------------ cycle time------------------------~)I

Figure 4: Charge cycle showing charge and discharge current pulses

1-30

ICS1702
The discharge current pulse amplitude is typically set to about
2.5 times the amplitude of the charging current based on
1.4V/cell. For example, if the charge current is 4 amps, then
the discharge current is set at about 10 amps. The energy
removed during the discharge pulse is a fixed ratio to the
positive charge rate. The amplitude of the discharge pulse does
not affect the operation of the part as described in this section.
A voltage acquisition window immediately follows a brief rest
time after the discharge pulse. No charge is applied during the
rest time or during the acquisition window to allow the cell
chemistry to settle. Since no current is flowing, the measured
cell voltage is not obscured by any internal or external IR drops
or distortions caused by excess plate surface charge. The
ICS1702 makes one continuous reading of the no-load battery
voltage during the entire acquisition window. The voltage that
is measured during this window contains less noise and is a
more accurate representation of the true state of charge of the
battery. If temperature termination is selected, the thermistor
voltage is sampled after a brief rest time once the current
supply to the battery is turned on.

Topping Charge
The third stage is a topping charge that applies current at a rate
low enough to prevent cell heating but high enough to ensure
a full charge.
The topping charge applies a C/lO charging current for two
hours. The current consists of the same pulse technique used
during the fast charge stage; however, the duty cycle of the
pulse sequence has been extended as shown in Figure 5.
Extending the time between charge pulses allows the same
charging current used in the fast charge stage so that no changes
to the current source are necessary. For example, the same
charge pulse that occurs every second at a 2C fast charge rate
will occur every 20 seconds for a topping charge rate of CII O.
The· MMN indicator is activated continuously during this
stage.

Maintenance Charge
The maintenance charge is intended to offset the natural selfdischarge of NiCd or NiMH batteries by keeping the cells
primed at peak charge. After the topping charge ends, the
ICS1702 begins this charge stage by extending the duty cycle
of the applied current pulses to a C/40 rate. The maintenance
charge will last for as long as the battery voltage is greater than
0.5V at the VIN pin, or, if the ten hour timer mode is enabled,
until the timer stops the controller. The MMN indicator is
activated continuously during this stage.

'-"-- cycle
~ time -~3tI~<------- delay time

-1

----------33t-tEI<=--

cycle
time

I

Figure 5: Representative timing diagram for topping and maintenance charge

1-31

~II

r

II

ICS1702
Charge Termination Methods
Several charge tennination schemes, including voltage slope,
temperature slope, maximum temperature and two overall
charge timers are available. The voltage slope and negative
voltage slope methods may be used with or without the temperature slope and the maximum temperature method. Maximum temperature and the fast charge timer are available as
backup methods.

Cells that are not thoroughly conditioned or possess an unusual
cell construction may not have a normal voltage profIle. The
ICS1702 uses an alternate method of charge tennination based
on a slight decrease in the voltage slope to stop charge to cells
whose voltage profIle is very shallow. This method looks for a
flattening of the voltage slope which may indicate a shallow
peak in the voltage profile. The zero slope point occurs slightly
beyond the peak voltage and is shown on the voltage curve graph.

Voltage Slope Termination
The most distinctive point on the voltage curve of a charging
battery in response to a constant current is the voltage peak that
occurs as the cell approaches full charge. By mathematically
calculating the fIrst derivative of the voltage, a second curve
can be generated showing the change in voltage with respect
to time as shown in Figure 6. The slope will reach a maximum
just before the actual peak in the cell voltage. Using the voltage
slope data, the ICS1702 calculates the point of full charge and
accurately terminates the applied current as the battery reaches
that point. The actual termination point depends on the charging
characteristics of the particular battery.

1.8
1.7
Inflection Point

Q)

a.

1.6

E
til
.!!1
.l!.!

1.5
1.4

!

8.
o

Voltage Slope
Zero Slope

1.3

o

1i.i

1.2

Time (Samples)

Figure 6: Voltage and slope curves showing inflection and zero slope points

1·32

II

ICS1702

Temperature Slope Termination
Temperature slope termination is based on the battery producing an accelerated rate of heating as the amount of readily
chargeable material dimishes at full charge. An increase in
battery (cell) heating due to the charging reaction will occur at
a much faster rate than a change due to a warming ambient
temperature. Note the effect of 0.5°C fluctuations in ambient
temperatures resulting in slight variations in the temperature
slope as shown in Figure 7. However, the increase in cell
temperature near the end of charge causes a much larger
change in the temperature slope that can be easily detected and
used as a trigger for fast charge termination.

.... ....
1.1.
1.76

1.7.

,
I

~.I

....
I
t
IA.)
J
....
-I
....
.... .....
1.1•

20

1.

20

30
T1me(mIn)

30

E

26

03

~

:!!.

Figure 8: Cell temperature and
thermistor voltage slope

04
Cell Temperature

E

.
,

50

05

28

E
!!

..

~

I

III

24

02

,!!

!!

Table 1 shows the decrease in thermistor voltage the last
minute before full charge required by the ICS1702 at various
charge rates. The thermistor voltage slope should exceed the
listed value to ensure charge termination. Note that changes in
thermistor location, cell size or large ambient temperature
fluctuations can affect the slope to some degree. Refer to the
Applications Information section and Temperature Slope and
Maximum Temperature section for more information on thermistor mounting.

~

!!.
E

22

01

20

,!!

00
10

20

30

40

50

60

Time {min )

Figure 7: Cell temperature and
temperature slope

Table 1: Slope vs. Charge Rate

The rate of change in cell temperature can be determined by
measuring the change in voltage across a negative temperature
coefficient thermistor as shown in Figure 8. The resistance of
an NTC thermistor changes in proportion in the change in
temperature of the thermistor. The ICS1702 measures the
decreasing resistance as a drop in voltage and calculates the
thermistor voltage slope, shown in Figure 8. The controller
terminates fast charge based on the selected charge rate and the
calculated slope.

1-33

Charge Rate

Thermistor Voltage Slope
(-V/min.)

>C/2

0.040

CI2 to C/3

0.028
0.018

 4SOC

_-"'*,--______-+_-----'
i5.

35

ffi
i!:

25

:

20

i

The RC pin is used to set the frequency of the internal clock
when an external I MHz clock is not available. An external
resistor must be connected between this pin and VDD. An
external capacitor must be connected between this pin and
ground. The frequency of the internal clock will be about I
MHz with a 16kn resistor and a lOOpF capacitor. All timedurations
noted in this document are based on a I MHz clock. Operating the
clock at a lower frequency will proportionally change all time
durations. Operating the clock at a frequency significantly
lower than I MHz, without adjusting the charge current accordingly, will lessen the effectiveness of the fast charge timer
and lower the accuracy of the controller. Operating the clock
at a frequency greater than I MHz will also change all time
durations and, without adjusting the charge current accordingly, may cause termination to occur due to the fast charge
timer expiring rather than by the battery reaching full charge.
The clock may be driven by a I MHz external 0 to 5V pulse
provided the duty cycle is between 10% and 60%. The clock
input impedance is about lkn.

~

15

10

The THERM pin is provided for hot and cold battery detection
and for temperature slope termination of fast charge when used
in conjunction with an NTC thermistor. The THERM pin also
provides for hot battery and maximum temperature termination when used in conjunction with a normally closed thermal
switch. Several internal voltage thresholds are used by the
controller depending on whether a thermistor or a thermal
switch is used. Figure 9 shows the internal thresholds over laid
on a typical thermistor curve.

No charging permdt8d
duetoa"hol"openedthermalswrtch
Cold battery charge

due to a ~coId" themustor

30
4V

Fast chargeallawed
USIng a themuslor

____-+_ _~oo~V-+-_.~~~~~~

05

- Fastchargeallowed
due to a closed thermal SWItch

05V

00

I

I

I

I

I

o 10 20 30 40 50
ThermlSlot Temperature ("C)

Figure 9: Voltage levels for temperature
sensing with a thermistor or thermal switch
The THERM pin requires some thought if a thermistor is going
to be used for hot and cold battery detection. The example
below works for a typical 10kn @ 25°C NTC thermistor.
Consider nsing the controller to prevent charging above 450C and
reducing the current below lOoc. At lOoC the resistance of the
thermistor is 18kn. At 45°C, the resistance drops to 4.7kn. The
ICS1702 has an internal voltage threshold at lOoC at 2.4V, and an
internal voltage at 45°C at 0.93V as shown in Figure 9. At 25°C the
voltage at the THERM pin is set at the midpoint of the thresholds:

0.93V +

Temperature Sensing: THERM Pin

Temperature <4S"C

2.40V - 0.93V
2

= 1.67Y.

The THERM pin has a 75kn internal pull-up (Rpu). Using a
resistor divider with 10kn for the thermistor (Rth) and a
external fixed resistor (Rflx), the divider looks like Figure 10
at 25°C:
Voo

f\u= 75k

+5V

Rnx
1.67V

Ru, =1Ok @ 25"C

Figure 10: Voltage divider at the THERM pin
at 25°C

1-39

II

ICS1702
Table 6: Thermistor Voltage Thresholds

To set the voltage at the THERM pin for 1.67V at 25°C, the
equivalent divider looks like Figure II.

Voltage

Battery
Temperature

Cold Battery Thermistor
Voltage

>2.4

4SoC

Parameter

+5V

RII
1.67V

THERM pin

• Using an NTC thermistor for temperature slope
termination:

Figure 11: Equivalent voltage divider
The parallel resistance RII is calculated:
RII -

SV - 1.67V
-20kQ
1.67V/IOkQ -

The internal pull-up resistance Rpu and the parallel resistance
RII are known so the external fixed resistor can be calculated
from:

As a battery approaches full charge, its accelerated rate of
heating can be used to terminate fast charge by detecting the
large change in the temperature slope. The large change in
temperature slope is proportional to the thermistor voltage
change per unit of time. If the DTSEL pin is programmed for
temperature slope termination, the controller will calculate the
thermistor voltage slope and terminate based on internally set
thresholds as listed in Table I. The threshold is 40mV per
minute for selected charge rates greater than CI2, 28mV per
minute for charge rates selected at or between C/2 and C/3, and
18mV per minute for selected charge rates less than C/3. The
voltage across the thermistor must change at these rates or
greater to terminate the selected charge rate.

RpuRll

Rfix-_~~~

Rpu-RII
Substituting in known values: Rfix = 27.27kQ. A 27kQ standard value is used for Rflx.
Since the thermistor resistance Rth is specified by manufacturers at a particular temperature, the voltage across the thermistor
V th at that temperature can be calculated from:
Vth=

Rth

(5V),

These thresholds correspond to a set change in thermistor
resistance when an external pull-up to SV is used as shown in
Figure 11. Using the values calculated from the hot and cold
battery detection example, the percent change in the thermistor
resistance per minute for selected charge rates are provided.
For selected charge rates greater than CI2, the thermistor
resistance must decrease 4%/min. to terminate charge. For
selected charge rates at or between C/2 and C/3, the thermistor
resistance must decrease 3%/min. to terminate charge. For
selected charge rates less than C/3, the thermistor must decrease 2%/min. to terminate charge.

RII+Rth
with the drop across the resistor divider equal to SY. For this
example, the calculated voltage with Rth=18kQ at lOoC is
2.37V and with Rth=4.7kQ at 45°C the voltage is 0.9SY. Table
6 lists the internal thresholds for hot and cold battery detection.
If the voltage across the thermistor (at the THERM pin) drops
below 0.93V, the ICS1702 will shut down due to a hot battery
fault condition and will not restart unless reset. If the voltage
dropped across the thermistor is above 2.4V before fast charge
is initiated. the ICS1702 will begin a reduced current charge.
See the Cold Battery Charging section for more information.

1-40

II

ICS1702

For example, a battery was monitored as it charged at a lC rate
in 25°C ambient. In the final minute of charge, the battery
temperature rose from 29.8°C to 31°C where full charge was
detected. With this data, the typical 10kO @ 25°C thermistor
used in the example above is checked to determine if its
characteristics satisfy the 4% decrease in resistance required
for the last minute of charge. The thermistor measures 8.37kO
@ 29.8°C and 8.01kO at 31°C. For a lC charge rate, the
resistance must decrease at least 4%/min. or more between
29.8°C and 31°C. The percent decrease in resistance for the
thermistor is calculated as:
8.37kO - 8.01kO
8.37kO

•
•

•

(100) = 4.30%.

This thermistor meets the 4%/min. requirement and will result
in termination at full charge at 31°C. The thermistor must be
checked for a 4%/min. decrease in resistance for tbe last minute
of charge near the hot and cold battery thresholds.
The battery in the example above was charged in a 25°C
ambient with its temperature rising 31°C - 25°C or 6°C. The
temperature rise was 31 °C - 29.8°C or 1.2°C in the last minute
before full charge occurred. This information is used to check
the tbermistor characteristics at the ambient extremes. If the
selected lC charge rate is initiated at 12°C, the thermistor
resistance change must decrease 4%/min. between 16.8°C and
18°C. The thermistor resistance at 16.8°C is 13.68kO and at
18°C the thermistor resistance is 13.06kO.
13.68kO - 13.06kO
13.68kO

The 4%/min., 3%/min. and 2%/min. decrease in thermistor
resistance for the last minute of charge for the selected charge
rate are applicable for NTC thermistors other than IOkO @
25°C provided that the following requirements are met:

• Using a thermal switch for hot battery detection:
A tbermal switch that opens at about 45°C is recommended.
The thermal switch must be connected between tbe THERM
pin and ground. When tbe thermal switch is closed, the voltage
at the THERM pin must be below 0.5V for normal operation.
When the thermal switch opens (see Figure 12), the internal
pull-up at the THERM pin will raise tbe voltage above 4.2V
and the ICS1702 will shut down and will not restart unless
reset. Table 7 contains the internal voltage thresholds used with
a thermal switch.

(100) = 4.53%

The thermistor meets tbe 4%/min. requirement and will result
in termination of fast charge at 18°C. If the selected lC charge
rate is initiated at 37°C, the thermistor resistance change must
decrease 4%/min. between 41.8°C and 43°C. The thermistor
resistance at 41.8°C is 5.48kO and at 43°C the thermistor
resistance is 5.25kO.
5.48kO - 5.25kO
5.48kO

An external pull-up resistor to 5V is used to provide a
tbermistor voltage of 1.67V @ 25°C.
The thermistor resistance at 25°C does not exceed 20kO
so that accuracy and adequate noise immunity are maintained.
The thermistor resistance increases by a factor of about
1.8 from 25°C to 10°C and the thermistor resistance
decreases by a factor of about 2.1 from 25°C to 45°C.

(100)

normally closed thermal switch
opens at 45 Q C

Figure 12: Thermal switch to connection to
ground at the THERM pin

=4.19%

The thermistor meets the 4%/min. requirement and will result
in termination of fast charge at 43°C.

Table 7: Thermal Switch Voltage Thresholds
I
Voltage

Battery
Temperature

Opened Thermal Switch
Voltage

>4.2

>45°C

Closed Thermal Switch
Voltage

<0.5

<45°C

Parameter

1-41

II

II

ICS1702
• Using no temperature sensor:
If a temperature sensor is not used, the THERM pin must be
grounded.

VIN pin

Termination Selection: DTSEL Pin
The ICS1702 has the capability of either temperature slope
termination, voltage slope termination or both methods simultaneously. The DTSEL pin has an internal 75kQ pull-down
resistor that enables voltage slope termination as the primary
method and is the default condition. Tying the pin high enables
both temperature slope and voltage slope termination methods.
Temperature slope termination as the primary method is enabled by tying the DTSEL pin to the CMN output (pin 5). CMN
must have an external 15kQ or lower value pull-up resistor to
VDD for proper activation of temperature slope termination.
The ICS1702 must be reset if a new termination method is
desired. Table 8 summarizes the DTSEL pin settings. NOTE:
Maximum temperature and fast charge timer termination
methods are always enabled when using temperature slope
termination. Refer to the sections on Fast Charge Timer
Termination and Maximum Temperature Termination for more
information.

Table 8: Termination Select List
TieDTSEL
Pin to ...
Low
(No Connect)

Result
Voltage slope termination only

High

Voltage slope and temperature slope
termination

CMN

Temperature slope termination only
(CMN with external pull-up to VDD)

Voltage Input: VIN Pin
The battery voltage must be normalized by an external resistor
divider network to one cell. The electrochemical potential of
one cell is about 1.2V. For example, if the battery consists of
six cells in series, the voltage at the VIN pin must be equal to
the total battery voltage divided by six. This can be accomplished with two resistors, as shown in Figure 13. To determine
the correct resistor values, count the number of cells to be
charged in series. Then choose either RI or R2 and solve for
the other resistor using:
RI = R2 x (# of cells -I) or R2 =

R2

Figure 13: Resistor divider network
at the VIN pin
Open Circuit Voltage Reference: OPREF Pin
The OPREF pin requires an external resistor divider to establish the open circuit (no battery) voltage reference. The purpose of this voltage reference is to detect the removal of the
battery from the charging system. The voltage at this pin is
compared to the voltage at the VIN pin when the current source
is turned on. If the voltage at VIN is greater than the voltage at
OPREF, the ICS1702 assumes the battery has been removed
and the ICS1702 enters the polling detect mode.
For proper operation, the voltage at OPREF must be set between the (divided down) open circuit voltage produced by the
current source and the maximum normalized battery voltage.
An example is shown in Figure 14.
Suppose that a current source has an open circuit voltage of
12Y. The maximum expected battery voltage of a six-cell pack
is determined to be 9.6y' The voltage at OPREF should be set
at a point between 1.6V (9.6V/6 cells=1.6V) and 2V
(l2V/6=2V). This is accomplished with a resistor divider
network. In this example, R4 and R3 are referred to VDD. Refer
to the VIN and OPREF divider resistor tables in the Applications Information section. From the VIN table, the divider
resistors are lOkQ and 2kQ for RI and R2. From the OPREF
table, the divider resistors are 2.2kQ and 1.3kQ for R3 and R4.
IfR3 is 2.2kQ andR4 is 1.3kQ, the voltage atOPREF is 1.86y'

RI
(# of cells - I)

1-42

ICS1702

+5V

+
R3

= 2.2k

_ - 0 OPREF
R4

VIN

= 1.86V

= {1.60V

(battery present)
2.00V (no battery)

= 1.3k

Resistor divider at the OPREF pin

Resistor divider at the VIN pin

Figure 14: Open Circuit Reference Example

Power: VDD Pin

Grounding: VSS, AVSS Pins

The power supply for the device must be connected to the VDD
pin. The voltage should be +5 VDC and should be supplied to
the part through a regulator that has good noise rejection and
an adequate current rating. The controller requires up to a
maximum of limA with VDD=5.00V.

There are two ground pins. Both pins must be connected
together at the device. This point must have a direct connection
to a solid ground plane.

Data Tables

II

Table 9: Absolute Maximum Ratings
Supply Voltage
Logic Input Levels
f------=--- . - - -

6.5

V

-0.5 to VDD + 0.5

V
°C

o to 70
-55 to 150

Ambient Operating Temperature
Storage Temperature

°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only. Functional operation of the device at the Absolute Maximum Ratings or other conditions not consistent with the
characteristics shown in this document is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.

1-43

II

ICS1702
Table 10: DC Characteristics
Tamb=25°C. All values given are typical at specified VDD.
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

4.5

5.0

5.5

UNITS

Supply Voltage

VDD

Supply Current

IDD

High Level Input Voltage
SELO, SEll, AUXO, AUXI

VIR

3.6

4.1

4.5

V

Low Level Input Voltage
SELO, SEll, AUXO, AUXI

VIL

0.73

0.75

0.8

V

V

7.3

Open Input Voltage
SELO, SEll, AUXO, AUXI

rnA

open

2.3

V

Low Level Input Current, pull-up
THERM,MRN

IIL

V=O.4V

74

I1A

High Level Input Current. pull-down
DTSEL

IIR

V=VDD-O.4V

75

I1A

High Level Source Current
CHG,DCHG

IOH

V=VDD-O.4V

28

rnA

Low Level Sink Current
CHG,DCHG

IOL

V=O.4V

25

rnA

Low Level Sink Current, indicator
PFN, CMN, MMN

IOL

V=0.4V

40

rnA

Low Level Sink Current, indicator
OTN

IOL

V=O.4V

28

rnA

Input Impedance
I AnaloglDigital

MQ

1.0

Converter Range

I

I

I

0-2.2

I

0-2.7

0-2.7

Table 11: DC Voltage Thresholds
TAMB=2SOC
PARAMETER

TYP

UNITS

Minimum Battery Voltage

0.5

V

~istor

2.4

V

- Cold Temperature

Thermistor - Hot Temperature

0.93

V

Thermal Switch - Open

4.2

V

Thermal Switch - Closed

0.5

V

1-44

V

ICS1702
Table 12: Timing Characteristics
PARAMETER

SYMBOL

REFERENCE

Clock Frequency

TYP

UNITS

1.0

MHz
ms

Reset Pulse Duration

tRESET

see Figure B

700

Charge Pulse Width

tcHG

see Figure A

1048

ms

tDCHG

see Figure A

5.0

ms

Discharge Pulse Width

tR

see Figure A

4.0

ms

tDA

see Figure A

16.4

ms

tcYCLE

see Figure A

1077

ms

Capacitor Discharge Pulse Width

5.0

ms

Capacitor Discharge Pulse Period

100

ms

Polling Detect Pulse Width

100

ms

Polling Detect Pulse Period

524

ms

Soft Start Initial Pulse Width

200

ms

Rest Time
Data Acquisition Time
Cycle Time

Soft Start Incremental Pulse Width

7.0

ms

Discharge Mode Pulse Width

400

ms

Discharge Mode Pulse Period

1050

ms

RESET to SEL Dynamic Reprogram Period

tRSA

see Figure B

1160

ms

RESET to AUX Dynamic Reprogram Period

tRSA

see Figure B

1160

ms

Timing Diagrams
Figure A:

t CHG

tR

CHG
DCHG

voltage
tR

tDA

tCYCLE

Figure B:

tRESET

RESET
SELO
SEL1
AUXO
AUX1
t RSA

1-45

II

ICS1702
Applications Information
To ensure proper operation of the ICS1702, external components must be properly selected. The external current source
used must meet several important criteria to ensure optimal
performance of the charging system. The charging current
should be constant when using voltage slope termination. The
current may vary when using temperature slope termination.

With the batteries removed, the current source must be capable
of raising the voltage at the VIN pin above the voltage at the
OPREF pin to ensure proper polling. With the batteries installed, the current source overshoot characteristics when
turned on and off must not cause the voltage at the VIN pin to
exceed the voltage at the OPREF pin. If the voltage at OPREF
exceeds the voltage at VIN when a charge pulse is applied or
removed, the polling feature will be activated.

VIN and OPREF Divider Resistors

PC Board Design Considerations

Figure 15 shows a typical application using the ICS1702. Rl
through R4 must be carefully selected to ensure that battery
detection and voltage termination methods operate properly.
R 1 and R2 are selected to scale the battery voltage down to the
voltage of one cell. The following table shows some typical
values. Additional information is available in the Voltage Input
section.

It is very important that care be taken to minimize noise

Cells

Rl

R2

1

Short

Open

2

2.0k

2.0k

3

2.0k

1.0k

4

3.0k

1.0k

5

12k

3.0k

6

10k

2.0k

7

12k

2.0k

8

9.lk

l.3k

coupling and ground bounce. In addition, wires and connectors
can add significant resistance and inductance to the charge and
discharge circuits.
When designing the printed circuit board, make sure ground
and power traces are wide and bypass capacitors are used right
at the controller. Use separate grounds for the signal, charge
and discharge circuits. Separate ground planes on the component side of the PC board are recommended. Be sure to connect
these grounds together at the negative lead of the battery only.
For the discharge circuit, keep the physical separation between
power and return (ground) to a minimum to minimize field
radiation effects. This precaution is also applicable to the
constant current source, particularly if it is a switch mode type.
Keep the ICS1702 and the constant current source control
circuits outside the power and return loop described above.
These precautions will prevent high circulating currents and
coupled noise from disturbing normal operation.

Selecting the Appropriate Termination Method
If using voltage slope termination, the current source should
prevent ripple voltage from appearing on the battery. The
effects of ripple on the battery voltage may interfere with
proper operation when using the voltage slope method.
R3 and R4 are used to set the open circuit (no battery) reference
voltage on the OPREF pin. The function of this pin is discussed
in the Open Circuit Reference section.
VOPREF

R3

R4

1.86 V

2.2k

l.3k

1.92 V

2.4k

1.5k

1.97 V

2.0k

1.3k

2.00 V

3.0k

2.0k

2.03 V

2.2k

1.5k

2.10 V

1.8k

l.3k

2.14 V

2.4k

1.8k

2.22 V

3.0k

2.4k

In general, the voltage slope termination method works best
for equipment where the battery is fast charged with the
equipment off or the battery is removed from the equipment
for fast charge. The temperature slope and maximum temperature termination methods are for equipment that must remain
operative while the battery is fast charged.

1-46

II

ICS1702

• Voltage Slope Termination

• Temperature Slope and Maximum Temperature

The voltage slope termination method used by the ICS1702
requires a nearly constant current flow into the battery during
fast charge. Equipment that draws a known constant current
while the battery is charging may use the voltage slope termination method. This constant current draw must be added to
the fast charge current. Using the voltage slope termination
method for equipment that randomly or periodically requires
moderate current from the battery during fast charge needs
evaluation. Equipment that randomly or periodically requires
high current from the battery during fast charge may cause a
voltage inflection that results in termination before full charge.
A voltage inflection can occur due to the charge current decreasing or fluctuating as the load changes rather than by the
battery reaching full charge. The voltage slope method will
terminate charge based on voltage inflections that are characteristic of a fully charged battery.

Temperature slope and/or maximum temperature termination
may have to be used for equipment that has high dynamic
current demands while operating from the battery during fast
charge. Also, users who do not have a well regulated constant
current source available may have to use temperature termination. In general, utilizing temperature slope as the primary
termination method with maximum temperature termination
as a safety back-up feature is the best approach. When using
temperature slope termination, the actual current should not be
appreciably lower than the selected rate in order that termination of fast charge occurs due to the battery reaching full charge
rather than by the timer expiring.

Charging sources that produce decreasing current as fast
charge progresses may also cause a voltage inflection that may
result in termination before full charge. For example, if the
charge current is supplied through a resistor or if the charging
source is a constant current type that has insufficient input
voltage, the current will decrease and may cause a termination
before full charge. Other current source abnormalities that may
cause a voltage inflection that is characteristic of a fully
charged battery are inadequate ripple and noise attentuation
capability or charge current decreasing due to thermal drift.
Charging sources that have any of the above characteristics
need evaluation to access their suitability for the application if
the use of the voltage slope termination is desired.
When using voltage slope termination, the controller soft start
stage, built-in noise filtering, and fast charge timer operate
optimally when the constant current source charges the battery
at the rate selected. If the actual charge current is significantly
less than the rate selected, the conditioning effect of the soft
start stage and the controller noise immunity are lessened.
Also, the fast charge timer may cause termination based on
time duration rather than by the battery reaching full charge
due to inadequate charge current.

Temperature termination methods require that the thermal
sensor be in intimate contact with the battery. A low thermal
impedance contact area is required for accurate temperature
sensing. The area and quality of the contact surface between
the sensor and the battery directly affects the accuracy of
temperature sensing. Thermally conductive adhesives may
have to be considered in some applications to ensure good
thermal transfer from the battery case to the sensor.
The thermal sensor should be placed on the largest surface of
the battery for the best accuracy. The size of the battery is also
a consideration when using temperature termination. The
larger the battery the lower the surface area to volume ratio.
Because of this, larger batteries are less capable in dissipating
internal heat.
Additional considerations beyond the basics mentioned above
may be involved when using temperature slope termination
where sudden changes in ambient temperature occur or where
forced air cooling is used. For these applications, the surface
area of the thermal sensor in contact with the battery compared
to the surface area of the thermal sensor in contact with the
ambient air may be significant. For example, bead type thermistors are relatively small devices which have far less thermal
capacity compared to most batteries. Insulating the surface of
the thermistor that is in contact with the ambient air should
help minimize heat loss by the thermistor and maintain
accuracy.

1-47

II

ICS1702
Charging System Status by Indicator
The Indicator Description List in Table 3 contains displays that
are caused by charging system abnormalities. When the CMN
indicator is flashing with no other indicator active, there is
voltage present at the battery terminals with the current source
off and no battery. Check the current source and ensure that it
produces no more than the equivalent of 350mVtcell when
turned off with no battery. If the VIN divider resistors were not
properly selected, an open circuit voltage that is actually less
than the equivalent of 350mVtcell with the charger off and no
battery will not divide down this open circuit voltage properly
and produce the CMN flash indication. Check the VIN divider
and ensure that it properly normalizes the battery voltage to the
electrochemical potential of about 1.2V cell. If the CMN flash
indication occurs with the battery installed, then the constant
current source is producing more than the equivalent of
350mVtcell when off and there is an open connection between
the charger terminals and the battery. Check wires, connections, battery terminals, and the battery itself for an open circuit
condition.
If the CMN and OTN indicators are active together, this is an
indication that the battery temperature has dropped to below
10°C after a fast charge was initiated with the battery temperature normal. If this condition is observed and the battery
temperature did not drop after high charge was initiated, check
the thermistor circuit mechanically for poor contact and electrically for excessive noise.
If the MMN and CMN indicators are alternately flashing, the
likely cause is no battery with the ICS1702 programmed in the
discharge-to-charge auxiliary mode. If the battery is present,
check wires, connectors, battery terminals, and the battery
itself for an open circuit condition.
If the MMN indicator is flashing with the OTN indicator
active, this is an indication that the battery is cold while in
either the discharge portion of the discharge-to-charge mode
or the discharge only mode. When in the discharge-to-charge
mode, if the battery does not warm-up into the normal temperature range after the discharge is complete, the ICS1702 will
enter the maintenance charge stage. When the battery warmsup, the discharge-to-charge mode will repeat.

1-48

ICS1702
CONSTANT
CURRENT
SOURCE
R5

(note

1)

+ 5 V(note 5)

1k

1
2
POLL 3
MAINT 4

CHG
VDD
DCHG unused
PFN
VIN
MMN OPREF
CMN THERM
AUX1
OTN
AUXO
SELO
DTSEL
VSS
RC
AVSS
SEL1
MRN

+5V
R1

19

R3

i temperature

R2

I

se~se

R4
.

-J~',: 0''''''
@25'C

(note 6)

-=Notes:
1) Value of R5 determined by discharge current and capacity of battery pack
2) Discharge FET IS logic-level compatible In this application
3) DC return of discharge FET must be connected close to negative battery terminal.
4) ReSistor IS needed only If a thermistor IS used Value may change depending on thermistor.
5) Regulated supply
6) Power ground; others are signal ground Connect signal ground to power ground
at negative battery terminal only

@45'C

---- ,,---

'Q'

Figure 15: Functional Diagram

II

Ordering Information
ICS1702N, ICS1702M, or ICS1702MT
Example:

ICSXXXX M

'L

""""g.

Ty",

N=DIP (£lastlc)
M=SOIC
MT=SOIC Tape and Reel

" - - - - - - - - - - Device Type (consists of 3 or 4 digit numbers)

"---_ _ _ _ _ _ _ _ _ _ Prefix

ICS=Standard DeVIce

1-49

I-SO

II

ICS1702

Integrated
Circuit
Systems, Inc.

Application Note

ICS1702 Linear Regulator Evaluation Board
Table 1

General Description
The ICS1702 Linear Regulator Evaluation Board allows
quick evaluation of the ICS 1702 Charge Controller for NickelCadmium and Nickel-Metal Hydride Batteries. The evaluation
board provides the designer an opportunity to both test the
ICS 1702 and a fast charge battery charger. The board is selfcontained and can provide a constant current to charge a battery
when optional components are installed.
The board includes resistors that are user-installed to customize operation for the desired charge rate, discharge pulse current, and number of cells in the battery pack. The board has a
5V regulator that provides power to the ICS 1702 and the LED
display. The board also has a breadboarding area consisting of
a matrix of holes for user added components.
Before using the ICS1702 Linear Regulator Evaluation
Board, ICS recommends the user review the ICSI702 data
sheet to become familiar with the operation of the controller.
This data sheet should be included with the board; if not, please
contact your local representative.
The ICS1702EB can be purchased two ways: ICS1702EB or
ICSI702EBNR. The difference between these boards is a
constant current linear supply as shown in the board schematic.
The ICS1702EB has an area on the board reserved for these
components. The ICS1702EBNR contains a kit which includes an LM317 and associated parts needed to build a
constant current supply of up to 1.5A.

Customizing the Board for your
Application
Refer to the evaluation board schematic diagram. The ICS 1702
requires that the battery voltage is normalized to the voltage of
one cell, or about 1.2V. To do this, resistors must be installed
in the locations marked R6 and R8. The appropriate values can
be selected from Table I. An assortment of resistors is provided
with the board.

Cells

R6

R8

I
2

Open
2.0k

Short
2.0k

3

1.0k
1.0k
3.0k

2.0k
3.0k
12k

2.0k
2.0k

10k
12k

l.3k

9.lk

4
5
6
7
8

If the evaluation board is used with battery packs containing
more than eight cells, the resistors can be determined by
counting the number of cells to be charged in series. Then
choose either R6 or R8 and solve for the other resistor using:

R8_ _
R8=R6x(#ofcells-l) or R6-_ _ __
(# of cells - I)
Current flow through the divider should be OAmA or greater
for noise immunity.
R7 sets the open circuit (no battery) reference voltage at the
OPREF pin voltage. The purpose of this voltage reference is
to detect the removal of the battery from the charging system.
The voltage at this pin is compared to the voltage at the VIN
pin when the current source is turned on. If the voltage at VIN
is greater than the voltage at OPREF, the ICS 1702 assumes the
battery has been removed and the ICS 1702 enters the polling
detect mode. For proper operation, the voltage at OPREF must
be set between the (divided down) open circuit voltage produced by the current source and the maximum normalized
battery. As a guide, set the voltage at OPREF (TPI) to be
200mV to 300mV higher than the maximum normalized battery voltage. For most batteries, the maximum normalized
battery voltage at full charge is 1.7 to 1.8V, so OPREF (TPl)
should be set at about 2Y.
When power is applied to the board, the controller will start a
charge sequence unless a logic low is applied to the RESET
terminal. When RESET is removed by a logic high or open, a
charge sequence will begin.

I1702EvalBrdRevC100694
1·51

II

Application Note

ICS1702 Linear Regulator Evaluation Board
The board provides several low value resistors that may be
used to set the amplitude of the discharge pulse. The resistors
can be installed in any or all of the locations labeled R I. R2,
or R3. The resistor value is calculated by setting the amplitude
of the discharge pulse. The discharge pulse amplitude is typically 2.5 times the charge current based on l.4Vfcell. The
required power rating of the resistor is highest when the
Discharge-to-Charge and Discharge-Only Auxiliary Modes
are used. See the rcs 1702 data sheet for additional information. The resistor locations RI, R2, and R3 are connected in
series. The unused locations must have a jumper to complete
the circuit. Not using the discharge pulse feature will not affect
the performance of the rcs 1702.
The ICS 1702 is capable of operating at nine different charge
rates between 4C (15 minutes) and Cf4 (four hours). The
charge rate is selected by installing jumpers in the appropriate
locations. Table 2 shows the proper settings to use for the
desired charge rate.

Table 2: Charge Rate List

'I

Charge
Rate

Jumper
SO

Jumper
SI

Topping Charge
Pulse Rate

Maintenance Charge
Pulse Rate

Fast Charge
Timer Duration
(after reset)

4C (15 min)
2C (30 min)
l.3C (45 min)
IC (60 min)
C/l.5 (90 min)
C/2 (120 min)
C/2.5 (ISO min)
Cf3 (180 min)
Cf4 (240 min)

1&2
1&2
1&2
2&3
2&3
2&3
None
None
None

1&2
2&3
None
1&2
None
2&3
1&2
None
2&3

one every 40 sec
one every 20 sec
one every 13 sec
one every 10 sec
one every 7 sec
one every 5 sec
one every 4 sec
one every 3 sec
one every 2 sec

one every 160 sec
one every 80 sec
one every 53 sec
one every 40 sec
one every 27 sec
one every 20 sec
one every 16 sec
one every 13 sec
one every 10 sec

21 min
39 min
57 min
75 min
110 min
144 min
212 min
244 min
275 min

The ICS1702 has several auxiliary modes available. Table 3
shows the jumper configurations for the auxiliary modes.

Table 3: Mode Select List
Auxiliary Mode

Jumper
AUXO

Jumper
AUXI

Direct Maintenance
Charging System Test
Ten Hour Timer
Discharge-to-Charge
Condition
Fast Charge
Discharge-Only

2&3
2&3
1&2
1&2
1&2
None
None

1&2
2&3
1&2
2&3
None
None
2&3

Mode Operation
Indefinite Cf40 maintenance mode
Charging system test for embedded applications
Limits total charge including the maintenance charge to 10 hours
Battery discharge to I Vfcell followed by the selected charge mode
Timed CIlO topping charge followed by Cf40 maintenance charge
Default
Battery discharge to IVfcell

1·52

II

Application Note

ICS1702 Linear Regulator Evaluation Board

The ICS 1702 has the capability to use either temperature slope
termination, voltage slope termination or both methods simultaneously. Table 4 shows the termination method and the
jumper settings. Refer to the ICS 1702 data sheet for more
information on charge termination methods.

Current Source (VR option)
The ICS1702EBNR contains an LM317 regulator. The
LM317 is configured as a constant current source. The amplitude of the current is determined by the value of R 15 and the
setting of R16. As an example, with a 2 ohm resistor for R15,
the current can be adjusted with R16 from 0.625A to 1.25A.
The LM317 will regulate a voltage difference of 1.25 volts
between the OUT and ADJ pins.

Table 4: Termination Select List
Termination Method
Voltage slope termination only
Voltage slope and temperature
slope termination
Temperature slope termination only

Jumper DTSEL
None
1&2

Operation

2&3

Before applying power to the board, ensure that the board is
properly initialized.

•
Power Requirements

•

The evaluation board uses a regulator to provide +5 volts for
the controller. The regulator allows operation from a DC supply
of S to 32 volts when the supply is connected to the +V terminal.
The board may also be operated from an external 5 volt supply
by removing the regulator (U2), wiring a jumper between
regulator pins 1 and 3, and by connecting 5 volts directly to the
+5V terminal.

•
•
•
•

Connections To External Circuitry
A normally closed thermal switch or a thermistor should be
connected to the TS terminal. If a thermal protection device is
not used, the TS terminal must be grounded.
Connect the battery between the +BAT and GND terminals. If
using an external current source, connect the charging current
source and its return between the +CUR and GND terminals.
If the on board current source is used, no connection to the
+CUR terminal is required.
Two charge signals are provided to control external charging
circuitry. CRG is high when the charging current is on. The
other signal CRG is low when the charging current is on.
The charging circuitry should provide a current at an amplitude
that is equal to the product of the battery capacity and the
desired charge rate. For example, to charge a 1.2 ampere hour
battery in 30 minutes, the current required would be 2.4 amps
or 2C where 'C' is the battery capacity.
It is important to note that the ICS 1702 does not control the
current flowing into the battery in any way other than turning
it on and off. The charging current should be constant when
using voltage slope termination. The current may vary when
using temperature slope termination.

Set the AUXO and AUX1 jumpers for the desired mode of
operation.
Set the SO and S 1 jumpers for the correct charge rate.
If needed, set the DTSEL jumper for the desired termination method.
Check to make sure the divider resistors R6 and RS are of
the correct value to normalize the battery pack voltage to
one cell.
If applicable, choose a value for R15 (see the section on
Current Source).
If applicable, choose resistors R1, R2 and R3 to obtain the
required discharge current.

After applying power to the board, set the following:
•
•

Adjust the potentiometer R7 for the desired open circuit
reference voltage at the OPREF pin.
If applicable, set the LM317 charging current by adjusting
the potentiometer R16.

Push and hold the reset switch SW1 for at least 700ms. All
LEDs should turn off while the switch is depressed. If fast
charge is selected, the green CRG LED will light. The LED
will remain lit until full charge is detected by the ICS 1702. At
that moment, the CRG LED will tum off and the MAINT LED
will light, indicating that the topping charge stage has begun.
The MAINT LED will remain on until a reset is issued either
by interrupting the power, removing the batteries or depressing
the reset switch SW1.
If the ten hour timer mode is selected, the LED sequence is the
same as the fast charge sequence explained above. After a
maximum of 10 hours has elapsed (from the time the ICS 1702
was reset), the controller will shut down and the MAINT LED
will turn off.

I-53

II

Application Note

ICS1702 Linear Regulator Evaluation Board
If either direct maintenance or the condition mode is selected,
the MAINT LED will turn on. The LED will remain on until a
reset is issued either by interrupting the power, removing the
batteries or depressing the reset switch SW 1.
If the discharge-only mode is selected, the MAINT LED will
flash at a one second rate until the battery has been discharged.
When the battery is discharged, the controller will shut down
and the MAINT LED will turn off.
If the discharge-to-charge mode is selected, the MAINT LED
will flash at a one second rate until the battery has been
discharged. When the battery is discharged, the appropriate
charge indicator will turn on. See the data sheet for more
detailed information on this auxiliary mode of operation.

Polling for a Battery
Upon power-up or after a reset is issued, any excess charge
from filter capacitors at the +BAT and +CUR terminals is
removed with a series of discharge pulses. After the discharge
pulse series is complete, the voltage at VIN must be greater
than 0.5V when a battery is present. If the voltage at the pin is
less than 0.5Y, the ICS 1702 assumes no battery is attached, and
the polling detect mode is initiated.
The ICS1702 then applies a lOOms charge pulse. During the
pulse, the ICSl702 monitors the VIN pin to determine if the
divided down terminal voltage is above OPREF. If the battery
is present, the voltage will be clamped below the reference on
OPREF when the current pulse is applied. If a battery is not
present, the voltage at VIN will rise above the reference at
OPREF. The POLL LED lights immediately.
Charge pulses will repeat at one second intervals until the
battery is reinstalled. The POLL LED is active as long as the
ICS 1702 is in the polling detect mode. Once a battery is
installed, the ICS 1702 will turn off the POLL LED and enter
the soft start stage. The ICS 1702 will automi\tically re-enter the
polling detect mode if the battery is removed during the fast
charge, topping charge, or maintenance charge stages. Any
open circuit in the current path to the battery will initiate the
polling detect mode.

II

When in the topping charge or maintenance charge stages, a
charge pulse may not occur for several seconds. During the
period between charge pulses, the voltage at VIN should be
greater than 0.5V if a battery is attached. If the voltage at VIN
is less than 0.5Y, the ICS 1702 assumes the battery has been
removed, and the polling detect mode is initiated.

Out-of-Temperature Range
The TEMP LED activates if the battery is either too hot or too
cold to fast charge. If a thermistor is used, the ICS 1702 employs
internal voltage references to determine if a battery is hot or
cold. Note: Remove R9 and replace with a jumper when using
a thermistor. A lOkf.! @ 25°C thermistor with an external
pull-up resistor is typically used. See the ICS 1702 data sheet
for additional information.
If a thermal switch is used, choose a switch that opens at 45°C
or lower. If a thermal protection device is not used, the TS
terminal must be grounded.
ICS strongly recommends the use of a thermal safety device in
the battery pack. One source of thermal switches is Portage
Electric Products, Inc., in North Canton, Ohio; (216) 499-2727.
A source of thermistors is Semetic USA (Ishizuka Electronics
Corp.), Babylon, NY; (516) 587-4086.

Design Considerations
When designing external current source circuitry for use with
the ICS 1702, there are several important considerations to
make before starting the design and the PC board layout.
For fast charge rates (l C through 4C), consideration has to be
given to the use of a pulse-width modulated switch mode
current source in order to reduce size and power dissipation.
Switch mode current sources can provide the ability to charge
battery packs that require voltages higher than the primary
supply. For instance, to charge a 24 volt battery from a 12 volt
vehicle battery, a switch mode boost converter could be used.
In general, linear chargers are less complex and more cost
effective, but less efficient than switch mode chargers. For
lower charge rates (C/1.5 through C/4), consideration should
be given to using a linear charger unless the size and ability to
dissipate heat are not available.
It is very important that care be taken to minimize noise
coupling and ground bounce. In addition, wires and connectors
can add significant resistance and inductance to the charge and
discharge circuits.

I-54

II

Application Note

ICS1702 Linear Regulator Evaluation Board

When designing the printed circuit board, make sure ground
and power traces are wide and bypass capacitors are used right
at the controller pins. Use separate grounds for the signal,
charge, and discharge circuits. Separate ground planes on the
component side of the PC board are recommended. Be sure to
connect these grounds together at the negative lead of the
battery only.
For the discharge circuit, keep the physical separation between
power and return (ground) to a minimum to minimize field
radiation effects. This precaution is also applicable to the
constant current source, particularly if it is a switch mode type.
Keep the ICS 1702 and the constant current source control
circuits outside the power and return loops described above.
These precautions prevent high circulating currents and coupled noise from disturbing proper operation.
Integrated Circuit Systems wants to help create a successful
battery charging solution using the ICS 1702. If you need technical advice or applications information, call the Power Management Products Applications department at (610) 630-5300.

Ordering Information

II

ICS1702EB NR

.

T

L......._ _ _ _

Ordering Option
blank=populated board
IVR=populated board WIth hnear regulator kIt

' - - - - - - - - - - - Device Type

lCSl702 Lmear Regulator EvaluatIOn Board

I-55

o
en
......

....
o

r---------------------------------------------------------------e

(note 4)

+V.

C3

.'

I

TP2

N

CHG
CHG

r:l

/+V

(J)
Q)

047~F

D5
+CUR

""I

:xJ

+5V'.~---------------~

(J)
(Q

R1

s:::

POLLOUT··~----------------l

Q)

(notused)~

o

""I

R8

(note 1)

+5 V

-

R5

+5V

+5 V

+BAT

,R12

m
<
Q)
s:::
Q)

390 /390

-----,

1) Values are determmed by number of cells and/or charge current, see text for details

~

2) Components wlthm dotted lines can be supplied for user-Installation when ordered, see ordenng Information
3) Resistor R9 must be removed and replaced with a Jumper when uSing a thermistor Use of a thermistor
requires an external pull-up resistor
4) 8 Vdc minimum Input
5) Logic level compatible FET
6) LM340, AN7805 or equivalent

ICS1702 Evaluation Board

II

ICS1712

Integrated
Circuit
Systems, Inc.

•

QuickSaver@ Charge Controller for Nickel-Cadmium
and Nickel-Metal Hydride Batteries
General Description

Features

The ICSl712 is a CMOS device designed for the intelligent
charge control of either nickel-cadmium (NiCd) or nickel-metal hydride (NiMH) batteries. The controller uses a pulsed-current charging technique together with voltage slope and/or
temperature slope termination. The ICSl712 employs a four
stage charge sequence that provides a complete recharge without overcharging. The controller has four user-selectable
charge rates available for customized charging systems.

•

•

The ICSl712 monitors for the presence ofa battery and begins
charging if a battery is installed within the first 10 seconds after
a reset. Voltage and temperature are measured to ensure a
battery is within fast charge conditions before charge is initiated.

•
•

Applications

•
•

•

Multiple charge termination methods include:
Voltage slope
Temperature slope
- Maximum temperature
- Charge timer
Four stage charge sequence:
- Soft start charge
Fast charge
- Topping charge
- Maintenance charge
Reverse-pulse charging available in all charge stages
Four programmable charge rates between 15 minutes (4C)
and two hours (C/2)
Out-of-temperature range detection
- Hot battery: charger shutdown
- Cold battery: low current charge
Ten second polling mode for battery detection
Battery fault with shutdown protection

Battery charging systems for:
Portable consumer electronics
Power tools
Audio/video equipment
- Communications equipment

Block Diagram
CHARGE
SELECT

POLLING/
FAULT LED
CHARGE
MODE LED

VOLTAGE
SENSE
OUTPUT
CONTROL

TERMINATION
SELECT
TEMPERATURE
SENSE

TEMPERATURE
STATUS LED

CHARGE
CONTROL
DISCHARGE
CONTROL

RESET _ _ _ _ _ _ _ _ _ _ _---1
RC

OSCILLATOR

QUlckSaver
IICS1712RevA100694

1·57

IS

a registered trademark of Integrated CirCUIt Systems, Inc

II

ICS1712
Pin Configuration

CHG
DCHG
PFN
CMN
OTN
SELO
VSS
AVSS

16
15
14
13
ICS1712
12
11
10
9

VDD
unused

VIN
THERM
DTSEL
RC
MRN
SEL1

16-Pin DIP or sOle
K-4, K-6

Pin Definitions
Pin
Number

Pin
Name

Type

1

CHG

OUT

2

DCHG

OUT

Active high TIL compatible signal available to tum on a dIscharge circuit.

3

PFN

OUT

Polling fault indicator. An active low turns on an external indicator to show the controller is either polling
for the presence of the battery or has determined the battery has been removed.

4

CMN

OUT

Charge mode indicator. A continuous low shows the controller is in a soft start or fast charge. The indicator
flashes during the topping and maintenance charges.

5

OTN

OUT

Out-of-temperature range indicator. An active low turns on an external indicator showing the battery is out
of the normal fast charge temperature range.

6

SELO

IN

7

VSS

Note:

Definition
Active high TTL compatible signal used to tum on an external current source to provide current to charge
the battery.

Input used with the SELl pin to program the device for the desired charge rate.
-------

Ground.
Ground.

8

AVSS

9

SELl

IN

Input used with the SELO pin to program the devICe for the desired charge rate.

10

MRN

IN

Master reset signal. A logic low pulse greater than 700 ms initiates a device reset.

11

RC

IN

An external resistor and capacitor sets the frequency of the internal clock.

12

DTSEL

IN

Selects temperature slope andlor voltage slope termination.

13

THERM

IN

Thermistor or thermal sWItch Input for temperature sensing.

14

VIN

IN

15

unused

16

VDD

Battery voltage nonnahzed to one cell with an external resistor divider.
Ground.
Device supply =+5.0 VDC

Pins 6, 9,10 and 13 have an internal pull-up.
Pin 12 has an internal pull-down

I-58

ICS1712
Soft Start Charge

Controller Operation

Some batteries may exhibit an unusual high impedance condition while accepting the initial charging current, as shown in
Figure 2. Unless dealt with, this high impedance condition can
cause a voltage peak at the beginning of the charge cycle that
would be misinterpreted as a fully charged battery by the
voltage termination methods.

Charging Stages
The charging sequence consists of four stages. The application
of current is shown graphically in Figure 1. The soft start stage
gradually increases current levels up to the user selected fast
charge rate during the first two minutes. The soft start stage is
followed by the fast charge stage, which continues until termination. After termination, a two hour CIlO topping charge is
applied. The topping charge is followed by a C/40 maintenance charge.

Average
Current
(not to scale)

I

Soft-Start

Fast Charge

Stage 1

o

Topping Charge

Stage 2

2min

The soft start charge eases batteries into the fast charge stage
by gradually increasing the current to the selected fast charge
rate. The gradual increase in current alleviates the voltage
peak. During this stage, only positive current pulses are applied
to the battery. The duty cycle of the applied current is increased
to the selected fast charge rate, as shown in Figure 3, by
extending the current pulse on every cycle until the pulse is
about one second in duration. The initial current pulse is
approximately 200ms. The CMN indicator is activated continuously during this stage

Maintenance Charge

Stage 3

Stage 4
termination + 2 hours

termination

Time (not to scale)
'!II

Figure 1: Graphical representation of average current levels during the four charging stages

II

155
154
153
iii

~

~
G>

OJ

J)1

~

152
151
150
149
148

High Impedance
Voltage Spike

/

147
146
145
Time (Samples)

Figure 2: High impedance voltage spike at the beginning of charge
1·59

II

ICS1712
Initial Pulse
Width

Initial Pulse
Width

Initial Pulse
Width

~ jE- time
i~crement

~

~~/----~I

~CYCletime

~
~

.

~I----~7~r/----~1

I.....- 2 x increment
r-time

~I------7~~~/--------

------~)+EIEi------- cycle time ------~)IIE-E-------cYcie time ------~)I

Figure 3: Cycle-to-cycle increase of the soft-start current pulse widths

Fast Charge
In the second stage, the ICS1712 applies the charging current
in a series of charge and discharge pulses. The technique
consists of a positive current charging pulse followed by a high
current, short duration discharge pulse. The cycle, shown with
charge, discharge, rest and data acquisition periods in Figure 4,
repeats every second until the batteries are fully charged.

7

The amplitude of the current pulse is determined by system
parameters such as the current capability of the charging
system, the desired charge rate, the cell capacity and the ability
of that cell to accept the charge current. The ICS1712 can be
set for four user-selectable fast charge rates from 15 minutes
(4C) to two hours (C/2). Charge pulses occur approximately
every second. The CMN indicator is activated continuously
during this stage.

rest
time

/

voltage
acquisition time

)

fast charge pulse width

discharge pulse width

1<

cycle t i m e - - - - - - - - - - - - - - - 4 I > I

Figure 4: Charge cycle showing charge and discharge current pulses

1·60

ICS1712
The discharge current pulse amplitude is typically set to about
2.5 times the amplitude of the charging current based on
1.4V/cell. For example, if the charge current is 4 amps, then
the discharge current is set at about 10 amps. The energy
removed during the discharge pulse is a fixed ratio to the
positive charge rate. The amplitude of the discharge pulse does
not affect the operation of the part as described in this section.
A voltage acquisition window immediately follows a brief rest
time after the discharge pulse. No charge is applied during the
rest time or during the acquisition window to allow the cell
chemistry to settle. Since no current is flowing, the measured
cell voltage is not obscured by any internal or external IR drops
or distortions caused by excess plate surface charge. The
ICS1712 makes one continuous reading of the no-load battery
voltage during the entire acquisition window. The voltage that
is measured during this window contains less noise and is a
more accurate representation of the true state of charge of
the battery.

Topping Charge
The third stage is a topping charge that applies current at a rate
low enough to prevent cell heating but high enough to ensure
a full charge.
The topping charge applies a CliO charging current for two
hours. The current consists of the same pulse technique used
during the fast charge stage; however, the duty cycle of the
pulse sequence has been extended as shown in Figure 5.
Extending the time between charge pulses allows the same
charging current used in the fast charge stage so that no changes
to the current source are necessary. For example, the same
charge pulse that occurs every second at a 2C fast charge rate
will occur every 20 seconds for a topping charge rate of ClIO.
The CMN indicator flashes at a one second rate during this
stage.

Maintenance Charge
The maintenance charge is intended to offset the natural selfdischarge of NiCd or NiMH batteries by keeping the cells
primed at peak charge. After the topping charge ends, the
ICS1712 begins this charge stage by extending the duty cycle
of the applied current pulses to a C/40 rate. The maintenance
charge will last for as long as the battery voltage is greater than
0.5V at the VIN pin. The CMN indicator flashes at a one second
rate during this stage.

cycle
'""-- cycle
~ time -~>IEEI(------- delay time ------~>'lEIE:-­ time

I

Figure 5: Representative timing diagram for topping and maintenance charge

1·61

~II

r

II

ICS1712

Cells that are not thoroughly conditioned or possess an unusual
cell construction may not have a normal voltage profile. The
ICSl712 uses an alternate method of charge termination based
on a slight decrease in the voltage slope to stop charge to cells
whose voltage profile is very shallow. This method looks for a
flattening of the voltage slope which may indicate a shallow
peak in the voltage profile. The zero slope point occurs slightly
beyond the peak voltage and is shown on the voltage curve graph.

Charge Termination Methods
Several charge termination schemes, including voltage slope,
temperature slope, maximum temperature and two overall
charge timers are available. The voltage slope and negative
voltage slope methods may be used with or without the temperature slope and the maximum temperature method. Maximum temperature and the fast charge timer are available as
backup methods.

Voltage Slope Termination
The most distinctive point on the voltage curve of a charging
battery in response to a constant current is the voltage peak that
occurs as the cell approaches full charge. By mathematically
calculating the first derivative of the voltage, a second curve
can be generated showing the change in voltage with respect
to time as shown in Figure 6. The slope will reach a maximum
just before the actual peak in the cell voltage. Using the voltage
slope data, the ICSl712 calculates the point of full charge and
accurately terminates the applied current as the battery reaches
that point. The actual termination point depends on the charging
characteristics of the particular battery.

1.8
1.7
.......
W
()

Inflection Point

Q)

0..

1.6

E

]i

ro

(5

2:-

1.5

~

Voltage

(5

0)

>

2:-

OJ
ClI

(5

0)

1.4

c..

Voltage Slope

o

Zero Slope

1.3
1.2

Time (Samples)

Figure 6: Voltage and slope curves showing inflection and zero slope pOints

1·62

o

U5

II

ICS1712

Temperature Slope Termination
Temperature slope termination is based on the battery producing an accelerated rate of heating as the amount of readily
chargeable material dimishes at full charge. An increase in
battery (cell) heating due to the charging reaction will occur at
a much faster rate than a change due to a warming ambient
temperature. Note the effect of O.soC fluctuations in ambient
temperatures resulting in slight variations in the temperature
slope as shown in Figure 7. However, the increase in cell
temperature near the end of charge causes a much larger
change in the temperature slope that can be easily detected and
used as a trigger for fast charge termination.

..

'.10
1.71

1.70

,.55
u.

,

1.

,
20

.. .
,

....(lNn.)

05

04

28

26

03

~

~

~

24

02

,!!.

i

'AO

,
50

.. I."
,

.."..

Table 1 shows the decrease in thermistor voltage the last
minute before full charge required by the ICSl712 at various
charge rates. The thermistor voltage slope should exceed the
listed value to ensure charge termination. Note that changes in
thermistor location, cell size or large ambient temperature
fluctuations can affect the slope to some degree. Refer to the
Applications Information section and Temperature Slope and
Maximum Temperature section for more information on thermistor mounting.

i
~

00

20
30

-I

c

E

01

22

20

f

Figure 8: Cell temperature and
thermistor voltage slope

'"

10

,

!

g

Cell Temperature

U

1 ~II

I'..101. '
20

30

....

....

40

50

60

Tlme(mln)

Table 1: Slope vs. Charge Rate
Figure 7: Cell temperature and
temperature slope

Charge Rate
>CI2

The rate of change in cell temperature can be determined by
measuring the change in voltage across a negative temperature
coefficient thermistor as shown in Figure 8. The resistance of
an NTC thermistor changes in proportion in the change in
temperature of the thermistor. The ICSl712 measures the
decreasing resistance as a drop in voltage and calculates the
thermistor voltage slope, shown in Figure 8. The controller
terminates fast charge based on the selected charge rate and the
calculated slope.

1·63

C/2

Thermistor Voltage Slope
(-V/min.)
0.040
0.028

II

II

ICS1712
To determine the required thermistor characteristics for
proper temperature slope termination, the battery temperature
rise must be known or determined for the last minute prior to
full charge.
Maximum temperature termination is also enabled when temperature slope termination is used. Care must be taken to keep
voltage levels at the THERM pin within the fast charge range
(between 2AV and O.93V), as shown in Figure 9.

If a thermal switch is used, a 45°C open circuit switch is
recommended. When the thermal switch opens, an internal
pull-up at the THERM pin results in a logic high which shuts
down the controller and activates the OTN indicator. The
controller must be reset once the hot battery fault condition has
cleared to restart the charge sequence.
Maximum temperature termination can be disabled by grounding the THERM pin. See the section on Temperature Sensing
for more information.

Maximum Temperature Termination
Maximum temperature can be sensed using either a NTC thermistor or a thermal switch. Maximum temperature termination
can also be bypassed if desired, although it is strongly recommended that some form of temperature termination be used.
If an NTC thermistor is used, an internal voltage threshold
determines when the battery is too hot to charge. As temperature increases, the voltage across the thermistor will drop. This
voltage is continually compared to the internal voltage threshold. If the thermistor voltage drops below the internal threshold, the OTN indicator is activated and the controller shuts
down. The controller must be reset once the hot battery fault
condition has cleared to restart the charge sequence.

Fast Charge Timer Termination
The controller uses a timer to limit the fast charge duration.
These times are pre-programmed, and are automatically adjusted in time duration according to the charge rate selected.
Fast charge timer termination is best suited as a safety backup
feature to limit the duration of the fast charge stage. The fast
charge timer is always enabled and cannot be disabled. See
Table 3 in the section Charge Rate Selection for more
information.

1-64

ICS1712
Battery Polling

Battery Fault Detection

Upon power-up or after a reset is issued, any excess charge
from filter capacitors at the charging system terminals is removed with a series of discharge pulses. After the discharge
pulse series is complete, the voltage at VIN must be greater
than 0.5V when a battery is present. If the voltage at VIN is
less than 0.5V, the ICSl712 assumes no battery is attached and
initiates a polling sequence.

The ICSl712 will tum on the PFN fault indicator and shut
down if the battery is removed or if an open circuit occurs in
the current path anytime after fast charge has been initiated.
When in the topping charge or maintenance charge stages, a
charge pulse may not occur for several seconds. During the
period between charge pulses, the voltage at VIN should be
greater than 0.5V if a battery is attached. If the voltage at VIN
is less than 0.5V, the ICSl712 assumes the battery has been
removed, a fault condition is indicated by the PFN fault indicator, and the controller shuts down.

The ICSl712 then applies a lOOms charge pUlse. During the
pulse, the ICSl712 monitors the VIN pin to determine if the
divided down terminal voltage is greater than the intemal2.0V
reference. If the battery is present, the voltage is clamped
below the 2.0V reference when the current pulse is applied and
the fast charge stage begins immediately. If a battery is not
present, the voltage at VIN rises above the 2.0V reference and
the PFN fault indicator is activated.
The charge pulses repeat for 10 seconds. If the battery is
installed within 10 seconds, the ICS1712 will tum off the PFN
fault indicator and enter the soft start stage. If the battery is not
installed within 10 seconds, the PFN fault indicator remains
active and the ICSl712 shuts down. A reset must be issued to
restart the controller after installing the battery.

Cold Battery Charging
Cold battery charging is activated if a voltage at the THERM
pin is in the cold battery voltage range, as shown in Figure 7.
The ICSl712 checks for a cold battery before initiating fast
charge. If a cold battery is present before fast charging begins,
the ICSl712 begins a two hour CliO topping charge (the
pulsed duty cycle is based on the selected charge rate). If the
battery is still cold after the two hour topping charge is complete, the ICS1712 begins a C/40 maintenance charge. The
maintenance charge will continue for as long as the battery
remains cold. The thermistor voltage at the THERM pin is
checked every second to see if the battery has warmed up. If
so, the ICSl712 stops the topping charge or maintenance
charge and begins a fast charge at a rate selected by the SELO
and SELl inputs. See the section on Temperature Sensing for
more information.
The CMN will flash at a one second rate, and the OTN
indicator will be active, indicating that a low current charge
is being applied to a battery that is outside the specified
temperature range for fast charging.

II

1·65

ICS1712
Indicators: CMN, PFN, OTN Pins

Pin Descriptions
The ICSl712 requires some external components to control
the clock rate, sense temperature and provide an indicator
display. The controller must be interfaced to an external power
source that will provide the current required to charge a battery
pack and, if desired, a circuit that will sink discharge current.

Output Logic Signals: CHG, DCHG Pins
The CHG and DCHG pins are active high, TTL compatible
outputs. In addition to being TTL compatible, the CMOS
outputs are capable of sourcing current which adds flexibility
when interfacing to other circuitry. A logic high on the CHG
pin indicates that the charging current supply should be activated. If applicable, a logic high on the DCHG pin indicates
that the discharge circuit should be activated.
Care must be taken to control wiring resistance and inductance.
The load resistor must be capable of handling this short duration high-amplitude pulse.

The controller has three outputs for driving external indicators.
These pins are active low. The three indicator outputs have
open drains and are designed to be used with LEDs. Each
output can sink over 20mA which requires the use of an
external current limiting resistor. The three indicator signals
denote fast charge stage, topping and maintenance stages, and the
polling detect or battery fault and out-of-temperature range modes
as shown in Table 2.
The charge mode (CMN) indicator is activated continuously
during the soft start and fast charge stages. The CMN indicator
flashes at a one second rate when the ICS1712 is applying a
topping or maintenance charge.
The polling fault (PFN) indicator is on when the ICSl712 polls
for a battery for the first 10 seconds. The controller applies
periodic charge pulses to detect the presence of a battery. The
indicator is a warning that these charge pulses are appearing at
the charging system terminals at regular intervals. When a
battery is detected, the indicator is turned off. The indicator is
also active if the battery is removed from the system, warning
that a fault has occured.
The out-of-temperature range (OTN) indicator is active whenever the voltage at the temperature sense (THERM) input
enters a range that indicates that the attached battery is too hot
to charge. The OTN indicator is also activated with the CMN
indicator if the controller is initialized with the battery in the
cold battery charge region.

Table 2: Indicator Description List
PFN

CMN

OTN

flash

Maintenance and topping charge

on

on

Description
Polling mode or battery fault

on

Fast charge
on

Hot battery shutdown

flash

on

Cold battery charge

on

on

one flash

see Applications Information
see Applications Information

1-66

II

ICS1712

Charge Rate Selection: SELO, SELl Pins
The SELO and SELl inputs must be programmed by the user
to infonn the ICSl712 of the desired charge rate. When a low
level is required, the pin must be grounded. When a high level
is required, no connection is required since each pin has an
internal 75kQ pull-up to VDD. The voltage ranges for low (L)
and high (H) are listed in Table 8, DC Characteristics. To
program the SELO and SELl inputs, refer to the Charge Rate List
in Table 3.

The ICSl712 does not control the current flowing into the
battery in any way other than turning it on and off. The required
current for the selected charge rate must be provided by the
user's power source. The external charging circuitry should
provide current at the selected charge rate. For example, to
charge a 1.2 ampere hour battery in 30 minutes (2C), approximately 2.4 amperes of current is required.

Table 3: Charge Rate List
Maintenance Charge
Pulse Rate

Fast Charge
Timer Duration
(after reset)

SELO

SELl

Charge Rate

Topping Charge
Pulse Rate

L

L

4C (15 min)

one every 40 sec

one every 160 sec

30 min

L

H

2C (30 min)

one every 20 sec

one every 80 sec

60 min

H

L

lC (60 min)

one every 10 sec

one every 40 sec

90 min

H

H

C/2 (120 min)

one every 5 sec

one every 20 sec

210 min

See the section on Controller Operation for additional informatIOn on the topping charge and mamtenance charge. See the section on Charge TermmatlOn
Metlwds for additional informatIOn on the charge timer.

II

1·67

II

ICS1712
Master Reset: MRN Pin
The MRN pin is provided to re-program the controller for a
new mode or charging sequence. This pin has an internal
pull-up of about 75kO. A logic low on the MRN pin must be
present for more than 700ms for a reset to occur. As long as the
pin is low, the controller is held in a reset condition. A master
reset is required to clear a temperature fault condition, clear
the charging system test, reset the ten hour timer or change
charge rates or auxiliary modes. Upon power-up, the controller
automatically resets itself.

Clock Input: RC Pin
The RC pin is used to set the frequency of the internal clock
when an external I MHz clock is not available. An external
resistor must be connected between this pin and VDD. An
external capacitor must be connected between this pin and
ground. The frequency of the internal clock will be about I
MHz with a 16kO resistor and a lOOpF capacitor. All time durations
noted in this document are based on a 1 MHz clock. Operating the
clock at a lower frequency will proportiollally change all time
durations. Operating the clock at a frequency significantly
lower than 1 MHz, without adjusting the charge current accordingly, will lessen the effectiveness of the fast charge timer
and lower the accuracy of the controller. Operating the clock
at a frequency greater than 1 MHz will also change all time
durations and, without adjusting the charge current accordingly, may cause termination to occur due to the fast charge
timer expiring rather than by the battery reaching full charge.
The clock may be driven by a I MHz external 0 to 5V pulse
provided the duty cycle is between 10% and 60%. The clock
input impedance is about IkO.

• Using an NTC thermistor for hot and cold battery detection:

Thermal SWItch Temperature ("C)
Temperature < 4S"C

Temperature:>45"C

50
45

~

No chargmg pem'lltted

L~k-------t-_..J duetoa"hoi"openedthennalswrtch
42V

35,

30

i

i=

25

~

-:

20

ffi

Cold battery charge

due to a ·cold" thennlStor

----1:'-'4v'-----t--Fast charge allowed

f ~ ~ I ~====t==~9~3V~t:;:J :::::~~:Itted
L

due to a "her' thenmslor

05 I
00 I

0 5V
I

I

I

Fast charge allowed
due to a closed thermal &WItch

o

10 20 30 40 50
Themllstor Temperature ("C)

Figure 9: Voltage levels for temperature
sensing with a thermistor or thermal switch
The THERM pin requires some thought if a thermistor is going
to be used for hot and cold battery detection. The example
below works for a typical IOkO @ 25°C NTC thermistor.
Consider usipg the controller to prevent charging above 45°C and
reducing the current below lO°C. At 10°C the resistance of the
thermistor is 18kO. At 45°C, the resistance drops to 4.7kn. The
ICS1712 has an internal voltage threshold at 10°C at 2.4V, and an
internal voltage at 45°C at 0.93V as shown in Figure 9. At 25°C the
voltage at the THERM pin is set at the midpoint of the thresholds:

O.93V +

Temperature Sensing: THERM Pin
The THERM pin is provided for hot and cold battery detection
and for temperature slope termination of fast charge when used
in conjunction with an NTC thermistor. The THERM pin also
provides for hot battery and maximum temperature termination when used in conjunction with a normally closed thermal
switch. Several internal voltage thresholds are used by the
controller depending on whether a thermistor or a thermal
switch is used. Figure 9 shows the internal thresholds over laid
on a typical thermistor curve.

I

40

2.40V - O.93V

= 1.67V.

2
The THERM pin has a 75kO internal pull-up (Rpu). Using a
resistor divider with IOkO for the thermistor (Rth) and a
external fixed resistor (Rflx), the divider looks like Figure 10
at 25°C:

VDD

+5V

1.67V

"V

Figure 10: Voltage divider at the THERM pin

at 25°C
1-68

II

ICS1712
Table 4: Thermistor Voltage Thresholds

To set the voltage at the THERM pin for 1.67V at 25°C, the
equivalent divider looks like Figure II.

Voltage

Battery
Temperature

Cold Battery Thermistor
Voltage

>2.4

45°C

Parameter

+5V

RII
167V
THERM pin

• Using an NTC thermistor for temperature slope
termination:
As a battery approaches full charge, its accelerated rate of
heating can be used to terminate fast charge by detecting the
large change in the temperature slope. The large change in
temperature slope is proportional to the thermistor voltage
change per unit of time. If the DTSEL pin is programmed for
temperature slope termination, the controller will calculate the
thermistor voltage slope and terminate based on internally set
thresholds as listed in Table 1. The threshold is 40mV per
minute for selected charge rates greater than C/2 and 28mV per
minute for selected charge rate C/2. The voltage across the
thermistor must change at these rates or greater to terminate
the selected charge rate.

Figure 11: Equivalent voltage divider
The parallel resistance RII is calculated:
RII = 5V - 1.67V
1.67VIlOkn

= 20kn

The internal pull-up resistance Rpu and the parallel resistance
RII are known so the external fixed resistor can be calculated
from:
RpuRll
Rftx= _ _ __
Rpu -RII

Substituting in known values: RfJx = 27.27kn. A27kQ standard value is used for Rfix.
Since the thermistor resistance Rth is specified by manufacturers at a particular temperature, the voltage across the thermistor
Vth at that temperature can be calculated from:

These thresholds correspond to a set change in thermistor
resistance when an external pull-up to 5V is used as shown in
Figure 11. Using the values calculated from the hot and cold
battery detection example, the percent change in the thermistor
resistance per minute for selected charge rates are provided.
For selected charge rates greater than C/2, the thermistor
resistance must decrease 4%/min. to terminate charge. For
selected charge rate C/2, the thermistor resistance must decrease 3%/min. to terminate charge.

II

Rth

Vth = _ _ _ (5V),
RII +Rth
with the drop across the resistor divider equal to 5V. For this
example, the calculated voltage with Rth=I8kQ at lOoC is
2.37V and with Rth=4.7kn at 45°C the voltage is 0.95Y. Table
6 lists the internal thresholds for hot and cold battery detection.
If the voltage across the thermistor (at the THERM pin) drops
below 0.93Y, the ICS1712 will shut down due to a hot battery
fault condition and will not restart unless reset. If the voltage
dropped across the thermistor is above 2.4V before fast charge
is initiated, the ICS1712 will begin a reduced current charge.
See the Cold Battery Charging section for more information.

1·69

ICS1712
For example, a battery was monitored as it charged at a I Crate
in 25°C ambient. In the final minute of charge, the battery
temperature rose from 29.SoC to 31°C where full charge was
detected. With this data, the typical IOkn @ 25°C thermistor
used in the example above is checked to determine if its
characteristics satisfy the 4% decrease in resistance required
for the last minute of charge. The thermistor measures S.37kn
@ 29.8°C and 8.01kn at 31°C. For a IC charge rate, the
resistance must decrease at least 4%/min. or more between
29.8°C and 31°C. The percent decrease in resistance for the
thermistor is calculated as:
8.37kn - S.Olkn
8.37kn

•

An external pull-up resistor to 5V is used to provide a
thermistor voltage of 1.67V @ 25°C.
The thermistor resistal\ce at 25°C does not exceed 20kn
so that accuracy and adequate noise immunity are maintained.
The thermistor resistance increases by a factor of about
I.S from 25°C to 10°C and the thermistor resistance
decreases by a factor of about 2.1 from 25°C to 45°C.

•

•

(100) =4.30%.

This thermistor meets the 4%/min. requirement and will result
in termination at full charge at 31°C. The thermistor must be
checked for a 4%/min. decrease in resistance for the last minute
of charge near the hot and cold battery thresholds.
The battery in the example above was charged in a 25°C
ambient with its temperature rising 31°C - 25°C or 6°C. The
temperature rise was 31 °C - 29.SoC or 1.2°C in the last minute
before full charge occurred. This information is used to check
the thermistor characteristics at the ambient extremes. If the
selected I C charge rate is initiated at 12°C, the thermistor
resistance change must decrease 4%/min. between 16.8°C and
18°C. The thermistor resistance at 16.8°C is 13.6Skn and at
ISoC the thermistor resistance is 13.06kn.
13.68kn - 13.06kn
13.6Skn

The 4%/min. and 3%/min. decrease in thermistor resistance for
the last minute of charge for the selected charge rate are
applicable for NTC thermistors other than IOkn @ 25°C
provided that the following requirements are met:

• Using a thennal switch for hot battery detection:
A thermal switch that opens at about 45°C is recommended.
The thermal switch must be connected between the THERM
pin and ground. When the thermal switch is closed, the voltage
at the THERM pin must be below 0.5V for normal operation.
When the thermal switch opens (see Figure 12), the internal
pull-up at the THERM pin will raise the voltage above 4.2V
and the ICSl712 will shut down and will not restart unless
reset. Table 5 contains the internal voltage thresholds used with
a thermal switch.

(100) = 4.53%

The thermistor meets the 4%/min. requirement and will result
in termination of fast charge at ISoC. If the selected lC charge
rate is initiated at 37°C, the thermistor resistance change must
decrease 4%/min. between 41.8°C and 43°C. The thermistor
resistance at 41.SoC is 5.48kn and at 43°C the thermistor
resistance is 5.25kn.
5.4Skn - 5.25kn
5.48kn

(100)

normally closed thermal switch
opens at 45Q C

Figure 12: Thermal switch to connection to
ground at the THERM pin

=4.19%

The thermistor meets the 4%/min. requirement and will result
in termination of fast charge at 43°C.

Table 5: Thermal Switch Voltage Thresholds
Parameter
Opened Thermal Switch
Voltage
Closed Thermal Switch
Voltage

1-70

Voltage

Battery
Temperature

>4.2

>45°C

<0.5

<45°C

II

ICS1712

• Using no temperature sensor:
If a temperature sensor is not used, the THERM pin must be
grounded.

VIN pin

Termination Selection: DTSEL Pin
The ICS1712 has the capability of either temperature slope
termination, voltage slope termination or both methods simultaneously. The DTSEL pin has an internal 75kQ pull-down
resistor that enables voltage slope termination as the primary
method and is the default condition. Tying the pin high enables
both temperature slope and voltage slope termination methods.
Temperature slope termination as the primary method is enabled by tying the DTSEL pin to the CMN output (pin 4). CMN
must have an external 15kQ or lower value pull-up resistor to
VDD for proper activation of temperature slope termination.
The ICSl712 must be reset if a new termination method is
desired. Table 6 summarizes the DTSEL pin settings. NOTE:
Maximum temperature and fast charge timer termination
methods are always enabled when using temperature slope
termination. Refer to the sections on Fast Charge Timer
Termination and Maximum Temperature Termination for more
information.

# of cells

Figure 13: Resistor divider network
at the VIN pin
Power: VDD Pin
The power supply for the device must be connected to the VDD
pin. The voltage should be +5 VDC and should be supplied to
the part through a regulator that has good noise rejection and
an adequate current rating. The controller requires up to a
maximum of 11 rnA with VDD=5.00V.

Grounding: VSS, AVSS Pins

Table 6: Termination Select List
TieDTSEL
Pin to ...
Low
(No Connect)

There are two ground pins. Both pins must be connected
together at the device. This point must have a direct connection
to a solid ground plane.

Result
Voltage slope termination only

High

Voltage slope and temperature slope
termination

CMN

Temperature slope termination only
(CMN with external pull-up to VDD)

Voltage Input: VIN Pin
The battery voltage must be normalized by an external resistor
divider network to one cell. The electrochemical potential of
one cell is about 1.2V. For example, if the battery consists of
six cells in series, the voltage at the VIN pin must be equal to
the total battery voltage divided by six. This can be accomplished with two resistors, as shown in Figure 13. Todetermine
the correct resistor values, count the number of cells to be
charged in series. Then choose either RI or R2 and solve for
the other resistor using:
Rl = R2 x (# of cells -1) or R2 =_----:c--:-R_1::--:c(# of cells - 1)

1·71

II

ICS1712
Data Tables
Table 7: Absolute Maximum Ratings
Supply Voltage

6.5

Logic Input Levels

V

Oto 70

°C

-55 to 150

°C

Ambient Operating Temperature
Storage Temperature

V

-0.5 to Voo + 0.5

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only. Functional operation of the device at the Absolute Maximum Ratings or other conditions not consistent with the
characteristics shown in this document is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.

Table 8: DC Characteristics
PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX

4.5

5.0

5.5

UNITS

Supply Voltage

Voo

Supply Current

100

High Level Input Voltage
SELO,SELl

VIH

3.6

4.1

4.5

V

Low Level Input Voltage
SELO, SELl

VIL

0.73

0.75

0.8

V

Low Level Input Current, pull-up
THERM,MRN

IlL

V=O.4V

74

J.lA

High Level Input Current, pull-down
DTSEL

IIH

V=Voo-O.4V

75

J.lA

High Level Source Current
CHG,DCHG

IOH

V=Voo-O.4V

28

rnA

Low Level Sink Current
CHG,DCHG

IOL

V=O.4V

25

rnA

Low Level Sink Current, indicator
PFN,CMN

IOL

V=O.4V

40

rnA

Low Level Sink Current, indicator
OTN

IOL

V=O.4V

28

rnA

V
rnA

7.3

Input Impedance

MQ

1.0

Analog/Digital Converter Range

0-2.2

0-2.7

0-2.7

Table 9: DC Voltage Thresholds
TYP

UNITS

Minimum Battery Voltage

PARAMETER

0.5

V

Maximum Battery Voltage

2.0

V

Thermistor - Cold Temperature

2.4

V

Thermistor - Hot Temperature

0.93

V

Thermal Switch - Open

4.2

V

Thermal Switch - Closed

0.5

V

1-72

V

II

ICS1712
Table 10: Timing Characteristics

PARAMETER
Clock Frequency
Reset Pulse Duration
Charge Pulse Width
Discharge Pulse Width
Rest Time
Data Acquisition Tune
Cycle Time
Capacitor Discharge Pulse Width
Capacitor Discharge Pulse Period
Polling Detect Pulse Width
Polling Detect Pulse Period
Soft Start Initial Pulse Width
Soft Start Incremental Pulse Width
RESET to SEL Dynamic Reprogram Period

SYMBOL

REFERENCE

tREsET

see Figure B
see Figure A
see Figure A
see Figure A
see Figure A
see Figure A

tcHG
tncHG

tR
toA
tcYCLE

TYP
1.0
700
1048
5.0
4.0
16.4
1077
5.0
100
100
624
200
7.0
1160

seeFigureB

tRSA

UNITS
MHz
IllS
IllS
IllS
IllS
IllS
IllS
IllS
IllS
IllS
IllS
IllS
IllS
IllS

Timing Diagrams

tCHG

Figure A:

CHG

_V

... tR

\

(

V\

DCHG

voltage
~,

t DCHG

tR

'
tDA

tCYCLE

Figure B:

RESET
SELO
SEL1
~SA

1-73

II

II

ICS1712
PC Board Design Considerations

Applications Information
To ensure proper operation of the ICS1712, external components must be properly selected. The external current source
used must meet several important criteria to ensure optimal
performance of the charging system. The charging current
should be constant when using voltage slope termination. The
current may vary when using temperature slope termination.

VIN Divider Resistors
Figure 14 shows a typical application using the ICSl712. RI
and R2 must be carefully selected to ensure that battery detection and voltage tennination methods operate properly. R 1 and
R2 are selected to scale the battery voltage down to the voltage
of one cell. The following table shows some typical values.
Additional information is available in the Voltage Input
section.
Cells

Rl

R2

It is very important that care be taken to minimize noise
coupling and ground bounce. In addition, wires and connectors
can add significant resistance and inductance to the charge and
discharge circuits.

When designing the printed circuit board, make sure ground
and power traces are wide and bypass capacitors are used right
at the controller. Use separate grounds for the signal, charge
and discharge circuits. Separate ground planes on the component side of the PC board are recommended. Be sure to connect
these grounds together at the negative lead of the battery only.
For the discharge circuit, keep the physical separation between
power and return (ground) to a minimum to minimize field
radiation effects. This precaution is also applicable to the
constant current source, particularly if it is a switch mode type.
Keep the ICS1712 and the constant current source control
circuits outside the power and return loop described above.
These precautions will prevent high circulating currents and
coupled noise from disturbing normal operation.

1

Short

Open

2

2.0k

2.0k

Selecting the Appropriate Termination Method

3

2.0k

l.Ok

4

3.0k
12k

l.Ok
3.0k

10k

2.0k

12k

2.0k

In general, the voltage slope termination method works best
for equipment where the battery is fast charged with the
equipment off or the battery is removed from the equipment
for fast charge. The temperature slope and maximum temperature termination methods are for equipment that must remain
operative while the battery is fast charged.

9.1k

l.3k

5

6
7
8

If using voltage slope termination, the current source should
prevent ripple voltage from appearing on the battery. The
effects of ripple on the battery voltage may interfere with
proper operation when using the voltage slope method.

1-74

II

ICS1712

• Voltage Slope Termination

• Temperature Slope and Maximum Temperature

The voltage slope termination method used by the ICSl712
requires a nearly constant current flow into the battery during
fast charge. Equipment that draws a known constant current
while the battery is charging may use the voltage slope termination method. This constant current draw must be added to
the fast charge current. Using the voltage slope termination
method for equipment that randomly or periodically requires
moderate current from the battery during fast charge needs
evaluation. Equipment that randomly or periodically requires
high current from the battery during fast charge may cause a
voltage inflection that results in termination before full charge.
A voltage inflection can occur due to the charge current decreasing or fluctuating as the load changes rather than by the
battery reaching full charge. The voltage slope method will
terminate charge based on voltage inflections that are characteristic of a fully charged battery.

Temperature slope and/or maximum temperature termination
may have to be used for equipment that has high dynamic
current demands while operating from the battery during fast
charge. Also, users who do not have a well regulated constant
current source available may have to use temperature termination. In general, utilizing temperature slope as the primary
termination method with maximum temperature termination
as a safety back-up feature is the best approach. When using
temperature slope termination, the actual current should not be
appreciably lower than the selected rate in order that termination of fast charge occurs due to the battery reaching full charge
rather than by the timer expiring.

Charging sources that produce decreasing current as fast
charge progresses may also cause a voltage inflection that may
result in termination before full charge. For example, if the
charge current is supplied through a resistor or if the charging
source is a constant current type that has insufficient input
voltage, the current will decrease and may cause a termination
before full charge. Other current source abnormalities that may
cause a voltage inflection that is characteristic of a fully
charged battery are inadequate ripple and noise attentuation
capability or charge current decreasing due to thermal drift.
Charging sources that have any of the above characteristics
need evaluation to access their suitability for the application if
the use of the voltage slope termination is desired.
When using voltage slope termination, the controller soft start
stage, built-in noise filtering, and fast charge timer operate
optimally when the constant current source charges the battery
at the rate selected. Ifthe actual charge current is significantly
less than the rate selected, the conditioning effect of the soft
start stage and the controller noise immunity are lessened.
Also, the fast charge timer may cause termination based on
time duration rather than by the battery reaching full charge
due to inadequate charge current.

Temperature termination methods require that the thermal
sensor be in intimate contact with the battery. A low thermal
impedance contact area is required for accurate temperature
sensing. The area and quality of the contact surface between
the sensor and the battery directly affects the accuracy of
temperature sensing. Thermally conductive adhesives may
have to be considered in some applications to ensure good
thermal transfer from the battery case to the sensor.
The thermal sensor should be placed on the largest surface of
the battery for the best accuracy. The size of the battery is also
a consideration when using temperature termination. The
larger the battery the lower the surface area to volume ratio.
Because of this, larger batteries are less capable in dissipating
internal heat.
Additional considerations beyond the basics mentioned above
may be involved when using temperature slope termination
where sudden changes in ambient temperature occur or where
forced air cooling is used. For these applications, the surface
area of the thermal sensor in contact with the battery compared
to the surface area of the thermal sensor in contact with the
ambient air may be significant. For example, bead type thermistors are relatively small devices which have far less thermal
capacity compared to most batteries. Insulating the surface of
the thermistor that is in contact with the ambient air should help
minimize heat loss by the thermistor and maintain accuracy.

1-75

II

ICS1712
Maximum Temperature Termination

Charging System Status by Indicator

Maximum temperature termination is best suited as a safety
back-up feature. Maximum temperature termination requires
that the thermal sensor be in intimate contact with the battery.
A low thermal impedance contact area is required for accurate
temperature sensing. The area and quality of the contact surface between the sensor and the battery directly affects the
accuracy of temperature sensing. Thermally conductive adhesives may have to be considered in some applications to ensure
good thermal transfer from the battery case to the sensor.

The Indicator Description List in Table 2 contains displays that
are caused by charging system abnormalities. At power-up or
after a reset is issued, one flash of the CMN indicator followed
by a continuous PFN indication results from a voltage present
at the battery terminals with the current source off and no
battery. Check the current source and ensure that it produces
no more than the equivalent of 350mV/cell when turned off
with no battery. If the VIN divider resistors were not properly
selected, an open circuit voltage that is actually less than the
equivalent of 350m VIcell with the charger off and no battery
will not divide down this open circuit voltage properly and
produce a PFN fault indication. Check the VIN divider and
ensure that it properly normalizes the battery voltage to the
electrochemical potential of about 1.2V cell. If the PFN fault
indicator is active immediately after power-up or after a reset
is issued with the battery installed, then the constant current
source is producing more than the equivalent of 350mVIcell
when off and there is an open connection between the charger
terminals and the battery. Check wires, connections, battery
terminals, and the battery itself for an open circuit condition.

The thermal sensor should be placed on the largest surface of
the battery for the best accuracy. The size of the battery is also
a consideration when using temperature termination. The
larger the battery, lower the surface area to volume ratio.
Because of this, larger batteries are less capable in dissipating
internal heat.
Additional considerations beyond the basics mentioned above
may be involved when using maximum temperature termination where sudden changes in ambient temperature occur or
where forced air cooling is used. For these applications, the
surface area of the thermal sensor in contact with the battery
compared to the surface area of the thermal sensor in contact
with the ambient air may be significant. For example, bead type
thermistors are relatively small devices which have far less
thermal capacity compared to most batteries. Insulating the
surface of the thermistor that is in contact with the ambient air
should help minimize heat loss by the thermistor and maintain
accuracy.

If the CMN and OTN indicators are active together, this is an
indication that the battery temperature has dropped to below
10°C after a fast charge was initiated with the battery temperature normal. If this condition is observed and the battery
temperature did not drop after fast charge was initiated, check
the thermistor circuit mechanically for poor contact and electrically for excessive noise.

1-76

II

ICS1712

CONSTANT
CURRENT
SOURCE
R3 (note 1)

+ 5V(note5)
390

1k

2
FAULT 3
CHG 4

VDD
CHG
DCHG unused
PFN
V1N
THERM
CMN
DTSEL
OTN
RC
SElO
VSS
MRN
AVSS
SEL1

15

~100PF
Notes:
1) Value of R3 determined by discharge current and capacity of battery pack.
2) Discharge FET is Iogic-level compatible in this application.
3) DC return of discharge FET must be connected close to negative battery terminal.
4) Resistor is needed only If a thermistor Is used. Value may change depending on thermistor.
5) Regulated supply
6) Power ground; others are signal ground. Connect signal ground to power ground
at negative battery terminal only.

Figure 14: Functional Diagram

11

Ordering Information
ICS1712N, ICS1712M, or ICS1712MT
Example:

ICS XXXX M

L __

N=DIP (Elastic)
M=SOIC
MT=SOIC'Thpe and Reel
' - - - - - - - - - Device Type (consists of 3-5 digit numbers)

' - - - - - - - - - - - - Pref"1X
ICS=Standani Device

1·77

1·78

II

ICS1722

Integrated
Circuit
Systems, Inc.

QuickSaver@ Charge Controller for Nickel-Cadmium
and Nickel-Metal Hydride Batteries
General Description

Features

The ICSl722 is a CMOS device designed for the intelligent
charge control of either nickel-cadmium (NiCd) or nickel-metal hydride (NiMH) batteries. The controller uses a pulsed-current charging technique together with voltage slope
termination. The ICSl722 employs a four stage charge sequence that provides a complete recharge without overcharging. The controller has nine user-selectable charge rates and
six user-selectable auxiliary modes available for customized
charging systems.

•

The ICSl722 monitors for the presence of a battery and begins
charging when a battery is installed. The ICSl722 is for
applications where temperature sensing is not required by the
charge controller.

Applications

•

•
•
•
•

•

Charge termination methods include:
- Voltage slope
- Charge timers
Four stage charge sequence:
Soft start charge
Fast charge
- Topping charge
- Maintenance charge
Reverse-pulse charging available in all charge stages
Nine programmable charge rates between 15 minutes (4C)
and four hours (C/4)
Continuous polling mode for battery detection
Six auxiliary modes include:
- Discharge-before-charge
- Ten hour C/IO conditioning charge
Direct to C/40 maintenance charge
Charging system test provided through controller
Adjustable open circuit (no battery) voltage reference

Battery charging systems for:
- Portable consumer electronics
- Power tools
- Audio/video equipment
Communications equipment

Block Diagram
RESET
OPEN CIRCUIT
REFERENCE

POLLING
MODE LED
CHARGE
MODE LED

O.5V

VOLTAGE
SENSE

ADC

PROCESSOR

MODE SELECT
CHARGE
SELECT
RC ----------------------------~

OUTPUT
CONTROL

MAINTENANCE
MODE LED
CHARGE
CONTROL
DISCHARGE
CONTROL

QUickSaver IS a registered trademark of Integrated CirCUit Systems, Inc
IICS1722RevA 100694

1-79

II

ICS1722
Pin Configuration

VDD

CHG
DCHG

unused

PFN

VIN

MMN

OPREF

CMN

AUX1

SELO

AUXO

VSS

RC

SEL1

MRN

16-Pin DIP or sOle
K-4, K-6

Pin Definitions
Pin Number
I

Pin Name
CHG

Type

Definition

OUT

ActIve high TTL compatIble sIgnal used to turn on an external current source to proVIde current to charge

2

DCHG

OUT

Active htgh TIL compallble SIgnal available to turn 00 a discharge Cll'Cuit

3

PFN

OUT

PollIng detect mdlcator An active low turns on an external mdicator to show the controller is polhng for

4

MMN

OUT

Mamtenaoce mode indicator. An active low turns on ao external indIcator showmg the battery is eIther in
the topping charge, mamtenaoce charge or auxIlIary condillon mode The indIcator flashes dunng the
auxIlIary discharge mode.

5

CMN

OUT

Charge mode mdlcator. An active low turns on ao external mdlcator to show the controller IS either in a
soft start charge or fast charge

6

SELO

IN

7
S
9

VSS
SELl

IN

Tri-level input used with the SELO pin to program the device for the deSIred charge rate

MRN

IN

Master reset SIgnal. A logIC low pulse greater thao 700 ms mlllates a devIce reset.

10

RC

IN

An external resIstor aod capacItor sets the frequency of the mternal clock.

11

AUXO

IN

Tn-level mput used WIth the AUXI pm to program the deVIce for an auxilIary operatmg mode

12

AUXI

IN

Tn-level mput used WIth the AUXO pm to program the deVIce for an auxIlIary operaung mode.

13

OPREF

IN

Open Clfcuit (no battery) voltage reference. An external pull-down resistor on this pm sets the open ClrcUlt
voltage reference used to detect the presence of a battery.

14

VIN

IN

15

unused

16

VDD

the battery.

the presence of the battery

Note:

Tn-level input used WIth the SELl pin to program the deVIce for the deSIred charge rate.
Ground.

Battery voltage normalized to one cell WIth an external resIstor dlVlder.
Ground.
DeVICe supply =+5.0 VDC

Pins 9 aod 13 have ao mternal pull-up.
Pins 6, 8, II, 12 float to 2 3V when unconnected.

1-80

II

ICS1722
Soft Start Charge

Controller Operation
Charging Stages
The charging sequence consists of four stages. The application
of current is shown graphically in Figure 1. The soft start stage
gradually increases current levels up to the user selected fast
charge rate during the first two minutes. The soft start stage is
followed by the fast charge stage, which continues until termination. After termination, a two hour ClIO topping charge is
applied. The topping charge is followed by a C/40 maintenance
charge.

Average
Current
(not to scale)

I

Soft-Start

Fast Charge

o

2 min

The soft start charge eases batteries into the fast charge stage
by gradually increasing the current to the selected fast charge
rate. The gradual increase in current alleviates the voltage
peak. During this stage, only positive current pulses are applied
to the battery. The duty cycle of the applied current is increased
to the selected fast charge rate, as shown in Figure 3, by
extending the current pulse on every cycle until the pulse is
about one second in duration. The initial current pulse is
approximately 200ms. The CMN indicator is activated continuously during this stage.

Topping Charge

Stage 2

Stage 1

Some batteries may exhibit an unusual high impedance condition while accepting the initial charging current, as shown in
Figure 2. Unless dealt with, this high impedance condition can
cause a voltage peak at the beginning of the charge cycle that
would be misinterpreted as a fully charged battery by the
voltage termination methods.

Maintenance Charge

Stage 3

Stage 4
termination + 2 hours

termination

Time (not to scale)
:310

Figure 1: Graphical representation of average current levels during the four charging stages

II

155
154
153

"'a"

1 52

2-

150

co

CD

149

0

148

go

~

<

1 51

147

High Impedance
Voltage Spike

/-

146
145
Time (Samples)

Figure 2: High impedance voltage spike at the beginning of charge
1·81

II

ICS1722
Initial Pulse
Width

Initial Pulse
Width

~ ~ time
i~crement

~

1
1 /.,,--/_--,I
I
~

l--

Initial Pulse
Width

cycle time

~
~

.

I

1,--_//

//,&._ _ _---'

"'---- 2 x increment
r-time

/~~,&./_ _ ___

L I_ _ _

---~)IE-E- - - cycle time ---+I)I~E----cycle time

Figure 3: Cycle-to-cycle increase of the soft-start current pulse widths
Fast Charge
In the second stage, the ICSl722 applies the charging current
in a series of charge and discharge pulses. The technique
consists of a positive current charging pulse followed by a high
current, short duration discharge pulse. The cycle, shown with
charge, discharge, rest and data acquisition periods in Figure 4,
repeats every second until the batteries are fully charged.

7

<

The amplitude of the current pulse is determined by system
parameters such as the current capability of the charging
system, the desired charge rate, the cell capacity and the ability
of that cell to accept the charge current. The ICSl722 can be
set for nine user-selectable fast charge rates from 15 minutes
(4C) to four hours (Cf4). Charge pulses occur approximately
every second. The CMN indicator is activated continuously
during this stage.

rest
time

/

voltage
acquisition time

)

fast charge pulse width

discharge pulse width

1<

cycle time---------------~)I
Figure 4: Charge cycle showing charge and discharge current pulses

1-82

II

ICS1722

The discharge current pulse amplitude is typically set to about
2.5 times the amplitude of the charging current based on
1.4VIcell. For example, if the charge current is 4 amps, then
the discharge current is set at about 10 amps. The energy
removed during the discharge pulse is a fixed ratio to the
positive charge rate. The amplitude of the discharge pulse does
not affect the operation of the part as described in this section.
A voltage acquisition window immediately follows a brief rest
time after the discharge pulse. No charge is applied during the
rest time or during the acquisition window to allow the cell
chemistry to settle. Since no current is flowing, the measured
cell voltage is not obscured by any internal or external IR drops
or distortions caused by excess plate surface charge. The
ICSl722 makes Dne continuous reading of the no-load battery
voltage during the entire acquisition window. The voltage that
is measured during this window contains less noise and is a
more accurate representation of the true state of charge of the
battery.

Topping Charge
The third stage is a topping charge that applies current at a rate
low enough to prevent cell heating but high enough to ensure
a full charge.
The topping charge applies a ClIO charging current for two
hours. The current consists of the same pulse technique used
during the fast charge stage; however, the duty cycle of the
pulse sequence has been extended as shown in Figure 5.
Extending the time between charge pulses allows the same
charging current used in the fast charge stage so that no changes
to the current source are necessary. For example, the same
charge pulse that occurs every second at a 2C fast charge rate
will occur every 20 seconds for a topping charge rate of ClIO.
The MMN indicator is activated continuously during this
stage.

Maintenance Charge
The maintenance charge is intended to offset the natural selfdischarge of NiCd or NiMH batteries by keeping the cells
primed at peak charge. After the topping charge ends, the
ICSl722 begins this charge stage by extending the duty cycle
of the applied current pulses to a C/40 rate. The maintenance
charge will last for as long as the battery voltage is greater than
0.5V at the VIN pin, or, if the ten hour timer mode is enabled,
until the timer stops the controller. The MMN indicator is
activated continuously during this stage.

~ cycle
....---- time -~)I~(------- delay time

)olE

---'r

cycle
time

I~I----~I

Figure 5: Representative timing diagram for topping and maintenance charge

1-83

-->I

II

ICS1722
Cells that are not thoroughly conditioned or possess an unusual
cell construction may not have a normal voltage profile. The
ICSl722 uses an alternate method of charge termination based
on a slight decrease in the voltage slope to stop charge to cells
whose voltage profile is very shallow. This method looks for a
flattening of the voltage slope which may indicate a shallow
peak in the voltage profile.The zero slope point occurs slightly
beyond the peak voltage and is shown on the voltage curve graph.

Charge Termination Methods
Charge termination schemes include voltage slope, fast charge
timer and, if desired, a ten hour timer to limit total charge time.

Voltage Slope Termination
The most distinctive point on the voltage curve of a charging
battery in response to a constant current is the voltage peak that
occurs as the cell approaches full charge. By mathematically
calculating the first derivative of the voltage, a second curve
can be generated showing the change in voltage with respect
to time as shown in Figure 6. The slope will reach a maximum
just before the actual peak in the cell voltage. Using the voltage
slope data, the ICSl722 calculates the point of full charge and
accurately terminates the applied current as the battery reaches
that point. The actual termination point depends on the charging
characteristics of the particular battery.

Charge Timer Termination
The controller uses a timer to limit the fast charge duration.
These times are pre-programmed, and are automatically adjusted in time duration according to the charge rate selected.
Fast charge timer termination is a safety backup feature to limit
the duration of the fast charge stage. The fast charge timer is
always enabled and cannot be disabled. See Table 3 in the
section Charge Rate Selection for more information. To limit
the total charge time to ten hours, refer to the section Ten Hour
Timer Mode for more information.

1.8
1.7
Inflection Point

~

W

~0

~

Q)
i5..
E

1.6

III

1.5

~

Voltage

£

Q)

OJ

:!)l
0

>

Q)

1.4

a.
o

Voltage Slope
Zero Slope

1.3

o

1ii

1.2

Time (Samples)

Figure 6: Voltage and slope curves showing inflection and zero slope pOints

1-84

II

ICS1722

Battery Detection

Discharge-fa-Charge Mode

Upon power-up or after a master reset, excess charge from
output filter capacitors at the charging system terminals is
removed with a series of discharge pulses. After the discharge
pulse sequence is complete, the voltage at VIN must be greater
than O.SV when a battery is present. If the voltage at the pin is
less than O.SV, the ICSl722 assumes no battery is present, and
the pollmg detect mode is initiated. No indicator is active
during the discharge pulses.

The time required for discharge depends· on the energy in the
bat.tery and ~he discharge rate. The discharge is not limited by
a tImer. This allows the user to set the discharge rate. ~
battery is drained to 1 volt/cell as read at the VIN pin under
load and then the controller enters soft start at a charge rate set
by the SELO and SELl inputs. The discharge load is activated
by the DCHG pin which goes low for about 400ms every
second. A resIstor value selected for a 2.SC discharge based on
1.4VIcell results in about a I C discharge rate.

The ICSl722 enters the polling detect mode and applies a
lOOms charge pulse. During the pulse, the ICSl722 monitors
~e VIN pin to determine if the divided down terminal voltage
IS above OPREF. If the battery is present, the voltage will be
clamped below the reference on OPREF while the current
pulse is applied. If a battery is not present, the voltage at VIN
will rise above the reference at OPREF.
The charge pulse will repeat at one second intervals until the
battery is reinstalled. The polling detect indicator (PFN) is the
only indicator active as long as the ICSl722 is in the polling
detect mode. Once a battery is installed, the ICSl722 will tum
off the PFN indicator and enter the soft start stage. The
ICSl722 will automatically re-enter the polling detect mode
if the battery is removed.

Battery Removal
During the application of a charge pulse, the voltage at the VIN
pin is compared to the voltage at the OPREF pin. If the voltage
at ~IN is greater than the voltage at OPREF during the applicatIon of the current pulse, then the battery is assumed to have
been removed and the ICSl722 enters the polling detect mode.
If th~ voltage at VIN is below the voltage at OPREF, charging
contmues.
When in the topping charge or maintenance charge stages, a
charge pulse may not occur for several seconds. During the
period between charge pulses, the voltage at VIN must be
greater than O.SV if a battery is attached. If the voltage at VIN
is less than O.SV, the ICSl722 assumes the battery has been
removed, and the polling detect mode is initiated.

Auxiliary Modes of Operation
The ICSl722 allows six alternate modes of operation to help
custollllze the chargmg system for certain applications. The
tri-level AUXO and AUXI pins are used to select the operating
mode. The AUXO and AUXI pins default the ICSl722 into
fast charge operation. Except for the discharge-to-charge
mode, another mode can only be selected by re-programming
and resetting the controller.

1-85

The disc~ar~e-to-charge mode can be entered by placing the
AUXO pm hIgh (H) and the AUXI pin low (L) with the SELO
and SELl inputs set for the desired fast charge rate. This setting
initializes the discharge sequence. The ICSl722 enters the
discharge-to-charge mode at initial power-up or with a master
reset. The discharge mode occurs first, to be followed by the
selected fast charge mode. During discharge, the MMN indicator flashes at a one second rate, while during the soft start
and fast charge stages the CMN indicator is activated continuously.
Four charge modes are available after the discharge portion is
complete by changing the state of the AUX inputs during the
discharge portion of this mode. The available charge modes are:
• Fast Charge: Leave the AUX inputs open (Z).
• Direct Maintenance Mode: Set the AUXO low (L)
and AUXI high (H).
• Condition Mode: Set AUXO high (H) and AUXI
open (Z).
• Ten-Hour Timer Mode: Set AUXO high (H) and
AUXI high (H).
If the battery is removed while in the discharge-to-charge
~od~, the ICSl722 will continually reset itself until the battery
IS remstalled. See Application Information for more information.

Discharge-Only Mode
The time required for discharge depends on the energy in the
bat~ery and ~he discharge rate. The discharge is not limited by
a tImer. This allows the user to set the discharge rate. The
battery is drained to I volt/cell as read at the VIN pin under
load. The ICSl722 shuts down after the discharge sequence is
finished and a master reset must be performed to reactivate the
device. The discharge load is activated by the DCHG pin which
goes low for about 400ms every second. A resistor value
selected for a 2.SC discharge based on 1.4VIcell results in
about a IC discharge rate. The discharge-only mode can be
entered by placing the AUXO pin open (Z) and the AUXI pin
10:-" (L). The ICSl722 enters this mode at initial power-up or
WIth a master reset. During the discharge portion the MMN
indicator flashes at a one second rate.
'

II

ICS1722
Direct Maintenance Mode

Ten Hour Timer Mode

The ICSl722 can enter directly into the C/40 maintenance
mode for cells that require a maintenance charge only. The
direct maintenance mode is activated by setting the AUXO pin
low (L) and the AUXI pin high (H), and resetting the device.
The SELO and SELl pins must be set based on the charging
current and the battery capacity. The formula

Placing the AUXO and AUXI pins both high (H) enables a ten
hour timer. This timer limits the total charge, including the
maintenance charge, to approximately ten hours for a battery
that is completely discharged before fast charge is initiated.
The ten hour limit is based on the assumption that the charge
terminates due to the fast charge timer as shown in Table 1.

Charging Current (Amps)
Battery Capacity (Amp. hr)

Charging System Test

gives the charge rate. Use Table 3 to find the correct SELO and
SELl settings. The maintenance charge is applied until the
battery is removed, upon which the ICSl722 will enter the
polling detect mode. The ICSl722 will enter the direct maintenance mode upon initial power-up or after a master reset. The MMN
indicator will be active during this mode.

The system test mode is intended for use in applications where
the charging system functionality needs to be tested. The system
test sequence consists of a one second activation of the CMN,
MMN and PFN indicator pins as well as the CHG and DCHG
lines. The system test mode is entered by placing both the AUXO
and AUXI pins low (L). The ICSl722 shuts down after the test
sequence is finished and a master reset must be performed to
reactivate the device.

Conditioning Mode
The ICSl722 can enter a conditioning mode which applies a
ClIO charge for a timed 10 hour period, followed by an indefinite
C/40 maintenance charge until the batteries are removed.
The conditioning mode can be entered by setting the AUXO
pin high (H) and the AUXI pin open (Z). The SELO and SELl
pins must be set based on the charging current and the battery
capacity. The formula
Charging Current (Amps)
Battery Capacity (Amp. hr)
gives the charge rate. Use Table 3 to find the correct SELO and
SELl settings. The MMN indicator will be active during the
10 hour conditioning charge and the maintenance charge that
follows. The ICSl722 enters the polling detect mode if the
battery is removed.

Table 1: Ten Hour Timer Information
Charge Rate

Fast Charge
Timer Cutoff

Maintenance Timer Cutoff
(after fast charge termination)

Charge Time Limit
(from reset)

4C

0.3 hrs

9.7 hrs

10 hrs

2C

0.6 hrs

9.4 hrs

10 hrs

l.3C

0.9 hrs

9.1 hrs

10 hrs

IC

1.2 hrs

8.8 hrs

10 hrs

C/l.5
C/2

l.8 hrs

8.2 hrs

10 hrs

2.4 hrs

7.6 hrs

10 hrs

C/2.5

3.5 hrs

6.5 hrs

10 hrs

C/3

4.0 hrs

6.0 hrs

lOhrs

C/4

4.6 hrs

5.4 hrs

10 hrs

1-86

ICS1722
Pin Descriptions
The ICSl722 requires some external components to control
the clock rate and provide an indicator display. The controller
must be interlaced to an external power source that will provide
the current required to charge a battery pack and, if desired, a
circuit that will sink discharge current.

Output Logic Signals: CHG, DCHG Pins
The CHG and DCHG pins are active high, TTL compatible
outputs. In addition to being TTL compatible, the CMOS
outputs are capable of sourcing current which adds flexibility
when interlacing to other circuitry. A logic high on the CHG
pin indicates that the charging current supply should be activated. If applicable, a logic high on the DCHG pin indicates
that the discharge circuit should be activated.
Care must be taken to control wiring resistance and inductance.
The load resistor must be capable of handling this short duration high-amplitude pulse. If the auxiliary discharge-to-charge
mode is selected, the power dissipation of the load resistor must
be properly selected to accept the extended length of the
discharge pulse.

Indicators: CMN, MMN, PFN Pins
The controller has three outputs for driving external indicators.
These pins are active low. The three indicator outputs have
open drains and are designed to be used with LEDs. Each
output can sink over 20mA which requires the use of an
external current limiting resistor. The three indicator signals
denote fast charge stage, topping and maintenance stages, and the
polling detect mode as shown in Table 2.

The maintenance mode (MMN) indicator is on when the
ICSl722 is either in the topping charge, maintenance charge,
direct maintenance mode, or the condition mode. The maintenance mode indicator flashes at a one second rate when the
ICS1702 is controlling the discharge portion of the discharge-tocharge or the discharge-only mode.
The polling detect (PFN) indicator is on when the ICSl722
polls for a battery. The controller applies periodic charge pulses
to detect the presence of a battery. The indicator is a warning
that these charge pulses are appearing at the charging system
terminals at regular intervals. When a battery is detected, the
indicator is turned off.

Charge Rate Selection: SELO, SELl Pins
The SELO and SELl inputs must be programmed by the user
to inform the ICSl722 of the desired charge rate. When left
unconnected (open), these tri-level pins will float to about
2.3y' When a low level is required, the pin must be grounded.
When a high level is required, the pin must be tied to VDD. The
voltage ranges for low (L), open (Z) and high (H) are listed in
Table 6, DC Characteristics. To program the SELO and SELl
inputs, refer to the Charge Rate List in Table 3.
The ICSl722 does not control the current flowing into the
battery in any way other than turning it on and off. The required
current for the selected charge rate must be provided by the
user's power source. The external charging circuitry should
provide current at the selected charge rate. For example, to
charge a 1.2 ampere hour battery in 30 minutes (2C), approximately 2.4 amperes of current is required.

The charge mode (CMN) indicator is activated continuously
during the soft start and fast charge stages. When the controller
enters the topping charge stage, the output goes high and the
indicator turns off.

Table 2: Indicator Description List
PFN

MMN

CMN

Description
Polling detect mode

on
on

Maintenance or topping charge, direct maintenance or condition mode
on

flash
flash
flash
on

flash

Fast charge
Discharge portion of the discharge-to-charge or discharge-only mode
see Applications Information
see Applications Information
Fast charge (see Applications Information)

1-87

II

II

ICS1722
Table 3: Charge Rate List
Maintenance Charge
Pulse Rate

Fast Charge
Timer Duration
(after reset)
21 min

SELO

SELl

Charge Rate

Topping Charge
Pulse Rate

L

L

4C (15 min)

one every 40 sec

one every 160 sec

L

H

2C (30 min)

one every 20 sec

one every 80 sec

39 min

L

Z

1.3C (45 min)

one every 13 sec

one every 53 sec

57 min

H

L

IC (60 min)

one every 10 sec

one every 40 sec

75 min

H

Z

C/1.5 (90 min)

one every 7 sec

one every 27 sec

110 min

H

H

C/2 (120 min)

one every 5 sec

one every 20 sec

144 min

Z

L

CI2.5 (150 min)

one every 4 sec

one every 16 sec

212 min

Z

Z

C/3 (180 min)

one every 3 sec

one every 13 sec

244 min

Z

H

C/4 (240 min)

one every 2 sec

one every 10 sec

275 min

See the section on Controller Operation for additional infonnation on the topping charge and maintenance charge. See the section on Charge Termination
Methods for additional infonnation on the charge timer.

When a high level is required, the pin must be tied to V DO. The
voltage ranges for low (L), open (Z) and high (H) are listed in
Table 6, DC Characteristics. To program the AUXO and AUXI
inputs, refer to the Mode Select List in Table 4. See the section
on Auxiliary Modes of Operation for additional information.

Mode Selection: AUXO, AUXl Pins
The AUXO and AUXI inputs must be programmed by the user
to inform the ICSl722 of the desired auxiliary mode. When
left unconnected (open) these tri-level pins will float to about
2.3V. When a low level is required, the pin must be grounded.

Table 4: Mode Select List
AUXO

AUXI

L

L

Charging System Test

Charging system test for embedded applications

L

H

Direct Maintenance

Indefinite C/40 maintenance charge

Z

Z

Fast Charge

Default

Z

L

Discharge-Only

Battery discharge to IVIcell

H

L

Discharge-to-Charge

Battery discharge to I V!cell followed by the selected charge mode

H

Z

Condition

Timed ClIO topping charge followed by a C/40 maintenance charge

H

H

Ten Hour Timer

Limits total charge including the maintenance charge to 10 hours

Mode Operation

Mode Selected

1-88

II

ICS1722

Master Reset: MRN Pin
The MRN pin is provided to re-program the controller for a
new mode or charging sequence. This pin has an internal
pull-up of about 7Skn. A logic low on the MRN pin must be
present for more than 700ms for a reset to occur. As long as the
pin is loiv, the controller is held in a reset condition. A master
reset is required to clear the charging system test, reset the ten
hour timer, change charge rates or auxiliary modes. Upon
~ power-up, the controller automatically resets itself.

# of cells

Clock Input: RC Pin
The RC pin is used to set the frequency of the internal clock
when an external 1 MHz clock is not available. An external
resistor must be cpnnected between this pin and Voo. An
external capacitor must be connected between this pin and
ground. The frequency of the internal clock will be about 1
MHz with a 16kn resistor and a l00pF capacitor. All timedurations
noted in this document are based on a 1 MHz clock. Operating the
clock at a lower frequency will proportionally change all time
durations. Operating the clock at a frequency significantly
lower than 1 MHz, without adjusting the charge current accordingly, will lessen the effectiveness of the fast charge timer
and lower the accuracy of the controller. Operating the clock
at a frequency greater than 1 MHz will also change all time
?urations and, without adjusting the charge current accordmgly, may cause termination to occur due to the fast charge
timer expiring rather than by the battery reaching full charge.
The clock may be driven by a 1 MHz external 0 to SV pulse
provided the duty cycle is between 10% and 60%. The clock
input impedance is about lkn.

Voltage Input: VIN Pin
The battery voltage must be normalized by an external resistor
divider network to one cell. The electrochemical potential of
one cell is abOut 1.2Y. For example, if the battery consists of
six cells in series, the voltage at the VIN pin must be equal to
the total battery voltage divided by six. This can be accomplished with two resistors, as shown in Figure 7. To determine
the correct resistor values, count the number of cells to be
charged in series. Then choose either Rl or R2 and solve for
the other resistor using:

Rl=R2x(#ofcells-l)orR2=

Rl

Figure 7: Resistor divider network
at the VIN pin
Open Circuit Voltage Reference: OPREF Pin
The OPREF pin has an internal 7SkQ pull-up resistor to Voo.
OPREF requires an external pull-down resistor to establish the
open circuit (no battery) voltage reference. The purpose of this
voltage reference is to detect the removal of the battery from
the charging system. The voltage at this pin is compared to the
voltage at the VIN pin when the current source is turned on. If
the voltage at YIN is greater than the voltage at OPREF, the
ICSl722 assumes the battery has been removed and the
ICS1722 enters the polling detect mode.
For proper operation, the voltage at OPREF must be set below
the (divided down) open circuit voltage produced by the current source and above the maximum normalized battery voltage. The OPREF pin voltage must not exceed 2.3V or it will
prevent the start of fast charge. If the voltage on OPREF
exceeds 4V, the controller will shutdown and must be reset.
~s ~ example, suppose that a current source has an open
ClrcUIt voltage of 12V as shown in Figure 8. The maxiIilum
expected battery voltage of a six-cell pack is determined to be
9.6y' The voltage at OPREF should be set at a point between
1.6V (9.6V/6 cells=1.6V) and 2V (12V/6=2V). This is accomplished with a pull-down resistor. Refer to the VIN and OPREF
resistor tables in the Applications Information section. From
the YIN table, the divider resistors are IOkn and 2kn for Rl
and R2. From the OPREF table, the pull-down resistor is 43kn
for R3. If R3 is 43kn, the voltage at OPREF is 1.82V since the
internal pull-up at the OPREF pin is 7Skn..

(# of cells - 1)

1·89

II

II

ICS1722

VDD

+
Rpu=75k

'--0 OPREF = 1.B2V
R3

6 cells
(9.6 V)

-=-=-

R1 = 10k

II-----to VIN = { 1.60V (battery present)
2.00V (no battery)

=43k

R2=2k

Resistor divider at the OPREF pin

Resistor divider at the VIN pin

Figure 8: Open Circuit Reference Example

Power: VDD Pin

Grounding: VSS Pin

The power supply for the device must be connected to the VDD
pin. The voltage should be +5 VDC and should be supplied to
the part through a regulator that has good noise rejection and
an adequate current rating. The controller requires up to a
maximum of limA with VDD=5.00V.

This pin must have a direct connection to a solid ground plane.

Data Tables
Table 5: Absolute Maximum Ratings
Supply Voltage
Logic Input Levels
Ambient Operating Temperature
Storage Temperature

6.5

V

-0.5 to VDD + 0.5
Oto 70
-55 to 150

°C

V
°C

Stresses above those listed under Abso!ute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only. Functional operation of the device at the Absolute Maximum Ratings or other conditions not consistent with the
characteristics shown in this document is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.

1-90

ICS1722
Table 6: DC Characteristics
Tamb=25°C. All values given are typical at specified VDD.
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

4.5

5.0

5.5

Supply Voltage

VDD

Supply Current

IDD

High Level Input Voltage
SELO, SELl, AUXO, AUXI

VIH

3.6

4.1

Low Level Input Voltage
SELO, SELl, AUXO, AUXI

VIL

0.73

0.75

UNITS
V

rnA

7.34.5

V

0.8

V

~--~

Open Input Voltage
SELO, SELl, AUXO, AUXI

open

2.3

V

Low Level Input Current, pull-up
MRN,OPREF

IlL

V=OAV

74

/-lA

High Level Source Current
CHG,DCHG

IOH

V=VDD-OAV

28

rnA

Low Level Sink Current
CHG,DCHG

IOL

V=OAV

25

rnA

Low Level Sink Current, indicator
PFN, CMN, MMN

IOL

V=OAV

40

rnA

Input Impedance

MQ

1.0

AnaloglDigital Converter Range

0-2.2

Minimum Battery Threshold

0-2.7
0.5

0-2.7

V
V

II

1-91

II

ICS1722
Table 7: Timing Characteristics
R~16kn. C~I00pF

PARAMETER
Clock Frequency
Reset Pulse Duration
Charge Pulse Width
Discharge Pulse Width
Rest Time
Data Acquisition Time
Cycle Time
Capacitor Discharge Pulse Width
Capacitor Discharge Pulse Period
Polling Detect Pulse Width
Polling Detect Pulse Period
Soft Start Initial Pulse Width
Soft Start Incremental Pulse Width
Discharge Mode Pulse Width
Discharge Mode Pulse Period
RESET to SEL Dynamic Reprogram Period
RESET to AUX Dynamic Reprogram Period

SYMBOL

lREsET
tcHG
locHG
tR
loA
tcYCLE

tRSA
tRSA

REFERENCE
see Figure B
see Figure A
see Figure A
see Figure A
see Figure A
see Figure A

seeFigureB
see Figure B

Timing Diagrams
Figure A:

!cHG

CHG
DCHG

yottage

!cYCLE

Figure B:

tREsET
RESET
SELO
SEL1
AUXO
AUX1

1·92

TYP

UNITS

1.0
700
1048

MHz

5.0

IDS

4.0
16.4
1077
5.0
100
100
624
200
7.0
400
1050
1160
1160

IDS

IDS
IDS

IDS
IDS
IDS
IDS
IDS
IDS
IDS
IDS
IDS
IDS
IDS
IDS

II

ICS1722

Applications Information
To ensure proper operation of the ICSl722, external components must be properly selected, The external current source
used must meet several important criteria to ensure optimal
performance of the charging system. The charging current
should be constant when using voltage slope termination.

With the batteries removed, the current source must be capable
of raising the voltage at the VIN pin above the voltage at the
OPREF pin to ensure proper polling. With the batteries installed, the current source overshoot characteristics when
turned on and off must not cause the voltage at the VIN pin to
exceed the voltage at the OPREF pin. If the voltage at OPREF
exceeds the voltage at VIN when a charge pulse is applied or
removed, the polling feature will be activated.

VIN and OPREF Divider Resistors
Figure 9 shows a typical application using the ICSl722. Rl
through R3 must be carefully selected to ensure that battery
detection and voltage termination methods operate properly.
Rl and R2 are selected to scale the battery voltage down to the
voltage of one cell. The following table shows some typical
values. Additional information is available in the Voltage Input
section.
Cells

Rl

R2

1

Short

Open
2.0k

2

2.0k

3

2.0k

1.0k

4

3.0k

1.0k

5

12k

3.0k

6

10k

2.0k

7

12k

2.0k

8

9.1k

1.3k

The current source should prevent ripple voltage from appearing on the battery. The effects of ripple on the battery voltage
may interfere with proper operation.
R3 is used to set the open circuit (no battery) reference voltage
on the OPREF pin. The function of this pin is discussed in the
Open Circuit Reference section.
VOPREF

R3

1.82 V

43k

1.93 V
2.02 V

47k

2.14 V

56k

PC Board Design Considerations
It is very important that care be taken to minimize noise
coupling and ground bounce. In addition, wires and connectors
can add significant resistance and inductance to the charge and
discharge circuits.
When designing the printed circuit board, make sure ground
and power traces are wide and bypass capacitors are used right
at the controller. Use separate grounds for the signal, charge
and discharge circuits. Separate ground planes on the component side of the PC board are recommended. Be sure to connect
these grounds together at the negative lead of the battery only.
For the discharge circuit, keep the physical separation between
power and return (ground) to a minimum to minimize field
radiation effects. This precaution is also applicable to the
constant current source, particularly if it is a switch mode type.
Keep the ICSl722 and the constant current source control
circuits outside the power and return loop described above.
These precautions will prevent high circulating currents and
coupled noise from disturbing normal operation.

Using the Voltage Slope Termination Method
In general, the voltage slope termination method works best
for equipment where the battery is fast charged with the
equipment off or the battery is removed from the equipment
for fast charge.

51k

1-93

II

ICS1722
The voltage slope termination method used by the ICSl722
requires a nearly constant current flow into the battery during
fast charge. Charging the battery in equipment that draws a
known constant current while the battery is charging should
have this current draw added to the fast charge current. Using
the ICSl722 for charging the batteries in equipment that
randomly or periodically requires moderate current from the
battery during fast charge needs evaluation. Equipment that
randomly or periodically requires high current from the battery
during fast charge may cause a voltage inflection that results
in termination before full charge. A voltage inflection can occur
due to the charge current decreasing or fluctuating as the load
changes rather than by the battery reaching full charge. The
voltage slope method will terminate charge based on voltage
inflections that are characteristic of a fully charged battery. The
ICS1702 and ICS1712 charge controllers have temperature
termination methods for equipment that randomly or periodically draws significant current from the battery during fast
charge.
Charging sources that produce decreasing current as fast
charge progresses may also cause a voltage inflection that may
result in termination before full charge. For example. if the
charge current is supplied through a resistor or if the charging
source is a constant current type that has insufficient input
voltage, the current will decrease and may cause a termination
before full charge. Other current source abnormalities that may
cause a voltage inflection that is characteristic of a fully
charged battery are inadequate ripple and noise attenuation
capability or charge current decreasing due to thermal drift.
Charging sources that have any of the above characteristics
need evaluation to access their suitability for the application if
the use of the voltage slope termination is desired.

Charging System Status by Indicator
The Indicator Description List in Table 2 contains displays that
are caused by charging system abnormalities. When the CMN
indicator is flashing with no other indicator active, there is
voltage present at the battery terminals with the current source
off and no battery. Check the current source and ensure that it
produces no more than the equivalent of 350mY/cell when
turned off with no battery. If the YIN divider resistors were not
properly selected, an open circuit voltage that is actually less
than the equivalent of 350mY!cell with the charger off and no
battery will not divide down this open circuit voltage properly
and produce the CMN flash indication. Check the YIN divider
and ensure that it properly normalizes the battery voltage to the
electrochemical potential of about 1.2Y cell. If the CMN flash
indication occurs with the battery installed, then the constant
current source is producing more than the equivalent of
350mYIcell when off and there is an open connection between
the charger terminals and the battery. Check wires, connections, battery terminals, and the battery itself for an open circuit
condition.
If the MMN and CMN indicators are alternately flashing, the
likely cause is no battery with the ICSl722 programmed in the
discharge-to-charge auxiliary mode. If the battery is present,
check wires, connectors, battery terminals, and the battery
itself for an open circuit condition.
If the MMN indicator is active at the initiation of fast charge,
check the external pull-down resistor from OPREF to ground.
A voltage at OPREF that exceeds 2.3Y will prevent the start of
fast charge.

The controller soft start stage, built-in noise filtering, and fast
charge timer operate optimally when the constant current
source charges the battery at the rate selected. If the actual
charge current is significantly less than the rate selected, the
conditioning effect of the soft start stage and the controller
noise immunity are lessened. Also, the fast charge timer may
cause termination based on time duration rather than by the
battery reaching full charge due to inadequate charge current.

1-94

II
V in

ICS1722

---7.

CONSTANT
CURRENT
SOURCE
R4 (note 1)

+5V +5V
+5 V (note 5)

1k

CHG

2

DCHG

VDD
unused
VIN

FAULT 3

PFN

MAl NT 4

MMN

CHG 5

CMN

AUX1

6

SELO

AUXO

7

OPREF

VSS

RC

SEL1

MRN

open
@45°C

Notes:
1) Value of R4 determined by discharge current and capacity of battery pack.
2) Discharge FET is logic-level compatible in this application.
3) DC return of discharge FET must be connected close to negative battery terminal.
4) Regulated supply
5) Power ground; others are signal ground. Connect signal ground to power ground
at negative battery terminal only.

Figure 9: Functional Diagram

II

Ordering Information
ICS1722N, ICS1722M, or ICS1722MT
Example:

ICSXXXX M

L~_

N=DIP (£Iasne)
M=SOIC
MT=SOIC Tape and Reel

' - - - - - - - - Device Type (consists of 3 or 4 digit numbers)
' - - - - - - - - - - - Prefix
ICS=Standard Device

1-95

1-96

ICS
ASIC Capabilities

Il

J-1

J-2

Mixed Analog/Digital Technology
ICS's capability in mixed analog/digital (mixed mode) technology is a direct outgrowth of 16 years experience providing
tum-key designs. We have found that few mixed-mode applications lend themselves to a high level of integration with
standard cells only. Customization is critical to bridge the gap between standard cells and the application.
ICS's confidence and success in mixed-mode design is due to our custom cell approach and our focus on understanding
the systems in which the IC must perform. We firmly believe the development of any mixed-signal IC can be completed
quickly and accurately by our team of skilled, experienced analog designers.
At ICS we use a custom cell based design methodology for our analog designs. We have developed the tools and expertise
that allow us to customize analog cells reliably and inexpensively. This approach combines the ease of design and low
risk of standard cells with the flexibility of full custom.
Of course, developing a functioning analog circuit is not as easy as connecting a few cells. An analog designer must
view the circuit function as a whole to ensure correct and accurate performance. Below is a representative list of analog
functions which we have designed and produced.

Power ConversionlRegulation

Op-Amps

Bandgap Voltage Reference
Linear Voltage Regulator
Charge-Pump Voltage Booster
Charge-Pump Voltage Inverter
Microprocessor Reset/Clock Supervisor
Low Battery Detect
Power Switching Circuits

Low-Quiescent Current (uA)
Wide Input/Output Common Mode
High Speed (6 MHz)
High Output Current

AID Converters
Successive Approximation
Dual-Slope
Sample/Track & Hold
VIF Converters

Control!Actuator Drive
Stepper Motor Driver
Air-Core Meter Movement Driver
Pulse-Width Modulated Motor Driver
Solenoid Driver
SCRlTriac DriveIPhase Control
x- Y Sensor Grid Drive
4-20mA 2-Wire Current Loop
LVDT DemodulatorlDriver

DIA Converters
R-2R
Weighted

Signal Conditioning
Active Filters
Balanced Synchronous Demodulator
Digital Sine Wave Synthesis
Fixed & Variable Gain AC Amplification

Miscellaneous
LEDILCD Display Drive
Crystal & Ceramic Resonator Oscillators
Timers/Oscillators
Precision Matched Current Sources
High-Frequency VCOIPLL (230 MHz)

II

J-3

ASICS At ICS
ICS has been a leader in providing state-of-the-art mixed
signal and complex digital ASIC designs since 1976. The
company was founded by assembling an unequaled engineering and design team to supply the electronics industry
with the best in technical solutions and customer service
in the ASIC marketplace. ICS has developed over 400
circuits since its beginning, and its success in standard
products can be attributed to the same attention to detail
applied to ASIC contract designs. ASIC projects are an
important part of our business, and we can provide our
customers with the best, most cost-effective solution to
their ASIC needs.

ICS has focused its resources on providing the very best
technical design expertise in both analog and digital technology. The cornerstone of this expertise is a custom/cell
based approach where ICS assumes responsibility for the
design, simulation, layout and verification of each circuit.
We use standard cell libraries together with custom
cells/functions where needed, a fully integrated CAD
system, and proven CMOS processes. In addition, we
develop the test hardware and programs necessary for
each device we design. Our goal is to supply a high quality
product. We remain committed to every product through
on-time delivery, inventory management and ongoing
product engineering.

•

A Technical Engineering Focus - - The ICS engineering design team assigned to your ASIC product
is involved from concept through characterization.
Test development is considered part of this design
task, thereby assuring that all critical parameters
are adequately tested. Our engineers develop a full
understanding of the engineering application for
each ASIC device which allows ICS to critically
evaluate the planned approach.

•

Design Flexibility - - ICS advanced design technology makes changes and modifications affordable and fast at any stage of design or production.
Simple modifications can often be corrected in one
or two mask levels, saving time and money when
changes are needed.

•

Process Flexibility - - To bring the very best technology to your application, our suppliers include
many of the leading semiconductor foundries and
packaging houses. This allows for multi-sourcing,
various packaging alternatives, and optimal utilization of semiconductor process technology. The
large volume of standard product business we do
with our suppliers assures us of competitive pricing. This permits ICS to extend large-volume pricing advantages to our ASIC customers.

•

Complete Production Support - - rcs' s approach
is to outsource mask tooling, wafer fab and assembly
while maintaining in-house control over production
control, testing, QC and product engineering.

Our business philosophy is to form a partnership with any
customer whose business and technical requirements fit
our guidelines and capabilities. We provide our ASIC
customers with product management, development and
production sourcing capabilities, by acting as an extension of your own engineering force. Through this partnership we are able to provide the most cost-effective
solution to meet your requirements. We have developed
unique relationships with software design companies,
silicon foundries, photomask houses, and assembly operations, both domestic and international. These relationships provide ICS with the flexibility to select from many
particular methodologies, processes or techniques. Our
high volume of standard product business insures competitive pricing and service that's second to none.

J-4

ICS Application Specific Standard Product
ICS has the capability to customize any of the standard
products we offer to better suit the needs of its customers.
Customized Standard Products permit an OEM customer
to optimize his system design and minimize the amount
of "glue" logic (or "glue linear") required to implement
his end product. This can result in significant size, power,
and cost savings in most OEM products.
Customization of ICS standard products can entail various degrees of complexity. A simple example might be to
change the sense of logic levels input or output from a
standard product. Frequency Timing Generator products
often require specific output frequencies, power-down
capabilities, or control capabilities not available from our
standard product listings. A more complex example
would be the addition oflatches to input or output signals.
Perhaps the addition of a microphone preamplifier to one
of the inputs of the ICS210l audio mixer IC would
simplify your design, packaging, and manufacturing task.

Since ICS standard products are a logical outgrowth of
our ASIC experience they utilize the same wafer fabs,
semiconductor processes, standard cell libraries and
building blocks used in our ASIC designs. This allows
ICS to use most of our standard products as super cells in
ASIC designs. The inclusion of standard product designs
in your large-scale ASIC design permits fully characterizcd building blocks to be incorporated into your ASIC
with minimum risk when compared to designed-fromscratch implementations of a complex function. Design
cost, risk, and time-to-market are also improved as we
do not have to reinvent the wheel each time the function
is needed.

Obviously the investment in many of these alterations can
be substantial in tooling and inventory costs. Therefore,
the projected volume must justify the investment. In some
cases ICS may be willing to share the cost if other markets
can be found for the new product.
The growth of laptop and notebook personal computers
in the marketplace has placed a severe demand on manufacturers in the area of packaging, power consumption,
performance and cost. ASIC devices may be the only
practical way to satisfy these needs.
The standard for computers since the first integrated
circuits made their appearance in the marketplace has
been 5 volt logic levels. Power consumption, size (due to
the size of battery packs), and performance requirements
are rapidly moving this standard towards 3 volt logic
levels. ICS ASIC capabilities permit many standard products to be redesigned to work at 3 volt levels.

Il

J-5

Foundry Selection
The chart below shows the qualified CMOS processes used by ICS for ASIC and standard products. This chart is
constantly changing, as ICS is always negotiating for the latest proven manufacturing technology. This allows us to
offer the most competitive costs to our ASIC customers, while at the same time providing qualified, proven manufacturing processes. Please contact your ICS representative for the latest list of available processes applicable to your
particular need.

les Technologies
SEMICONDUCTOR
TECHNOLOGY

CMOS 3!1 Single Metal

Principal Features

SPEED

..

Medium
25 MHz

DENSITY

LSI
CELLS

MULTI
SOURCE

STD
CELLS

GATE
ARRAY

VOLTS

ANALOG
FULL
CELLS CUSTOM

Medium

Some

YES

YES

NO

3-10

YES

YES
YES
YES

Medium

Medium

NO

YES

YES

NO

10

Switched
Cap.

High

OK Gates

Some

YES

YES

NO

5

YES

CMOS Metal Gate

Low 10 MHz

Low

NO

YES

YES

NO

5-18

YES

YES

CMOS High Voltage

Low 10 MHz

Low

NO

NO

YES

NO

30

YES

YES

CMOS 3u Double Poly
CMOS 1.5!1 Double Metal

CMOS 1.0!l

High

High

Many

YES

YES

NO

5

YES

YES

CMOS .8u

High

Very High

Many

NO

YES

NO

5

YES

YES

CMOS .6u

High

Very High

Many

NO

YES

NO

5

YES

YES

J-6

ICS

Quality and Reliability Information

IJ

J-7

J-8

ICS: Reliability Through Design
Right from the start, we concentrate on the ultimate quality of the product. rcs product reliability is designed in to meet
the necessary controls that are imposed during production and testing. All rcs designs utilize a variety of "design-process-rule checks" to insure that product performance is consistent with our quality and reliability goals. Design
simulations and wafer data base file verifications playa prominent role throughout the prototype and are production
stages of the design to eliminate test correlation problems after the design is completed.
rn a continuing effort to improve reliability as new devices are being developed, we review the data acquired from
previous device designs to determine if any changes are necessary to improve performance and/or enhance the new
device's operation. We evaluate all aspects of packaging technology, including leadframe vs. die-size compatibility,
packaging materials and methods. rcs develops test programs to isolate problems during wafer probe and final testing
to assure the quality of our products.
An extremely important phase of the product development cycle is the characterization of devices to insure their
functional performance and establish margins of performance relative to device specifications. Samples of prototype
units are initially measured to ascertain their performance characteristics and to verify that the transition from design
and simulation to production processes has not had any deleterious effects.

GENERAL PROCESS FLOW

Production Flow
The production flow for rcs products is shown in
the adjacent diagram, which provides some detail
of the basic controls that are exercised through the
various process stages. The processes of Wafer
Fabrication, Assembly and Taping and Reeling
are performed by outside facilities, with a process
control- and electrical-data review for each lot of
material before being routed for processing by
these subcontractors. Wafer and package testing
are performed at rcs.

•

WAFER FAB

(Sub-contractor)

1
MATERIAL
RECEIPT

•

SPC PROCESS MONITORING

•

WAFER PROBE PROCESS
CONTROLS

•

PROCESS RELIABILITY
MONITORING

•

INITIATE WAFER TRAVELER
AND TRACEABILITY RECORDING

•

MAINTAIN RECORDS OF EACH
LOT FROM RECEIPT THROUGH
PROBING, INSPECTION,
STOCKING AND SHIPMENT TO
ASSEMBLER

1

A set of electrical characteristics data is provided
for each wafer lot rcs receives. Every lot gets a
parametric evaluation to determine the uniformity
of the process and to serve as a quality control gate
for wafer acceptance from manufacturing. SPC
controls are maintained through the use of the
accumulated profile parameters to serve as a
source of electrical data feedback in support of
process control and improvement programs. This
data is also monitored by rcs to assess wafer fab
performance and establish acceptance criteria for
wafer fab lots. Environmental test monitoring including, HTOL, Temperature Cycling, Autoclave
and TemperaturelHumidity tests are performed to
monitor the reliability of wafers produced.

100%
WAFER PROBE

1
ISSUE TO
STOCKROOM

!

The introduction of wafers into rcs from the wafer
fab source initiates the traceability recording that
tracks every part shipped from rcs. Wafer lot
numbers assigned at the wafer fab source are recorded and are tracked through all stages of test,
assembly, taping and ultimate shipment. At the rcs
facility, all wafers are probed on a 100% basis
before being shipped for assembly.

SHIP TO
ASSEMBLY
SOURCE

J-9

Il

!

GENERAL PROCESS FLOW (continued)

Assembly suppliers are responsible to rcs for the
processing of probed wafers into finished package configurations in accordance with ICS-supplied assembly specifications and bonding
diagrams. Each assembly lot is supplied with a
process traveler, which delineates the results of
each process step and process monitor inspection. SPC data is maintained and reviewed on a
periodic basis to assess such characteristics as:
die shear, bond pull, solderability, marking permanence and process control elements pertinent
to the assembly operations.

•

APPROVED ASSEMBLY
SOURCES WITH MONITORS
OF PROCESS STEPS THROUGH
ESTABLISHED SPC TRACKING
AND PROCESS CONTROLS

~

•

CONTROLLED ENVIRONMENT
FOR TEMPERATURE/HUMIDITY/
ESD

TEST

•

l

AQL SAMPLING OF ASSEMBLED
PARTS AND REVIEW OF
ASSEMBLY PROCESS LOT
TRAVELERS

III ASSEMBLY
OPERATION
(Sub-contractor)

-1
ASSEMBLY LOT
RECEIPT

Processing at ICS includes incoming inspection
examination of finished packages. Then we initiate test travelers to record test and inspection
results and to allow for control of material into
the stockroom. All parts are tested on a 100%
basis in established test programs, and are
checked on an AQL sampling basis for electrical
and mechanical characteristics before acceptance to stock.
If customer requirements call for parts to be on
tape & reel, the parts are packaged to ICS control
specs for the implementation of this operation.
The basic spec for this operation is per EIA
Standard RS-48 1.

•

MATERIAL
CONTROL

100% TEST OF ALL RECEIVED
MATERIAL

•

AQL SAMPLING FOR TEST AND
AND MECHANICAL CHARACTERISTICS

~

•

CONTROLLED STOCKROOM
PENDING SHIPMENT

ISSUE TO
STOCKROOM

~
~

IF REQUIR ED BY CUSTOMER

SHIPTO
TAPE/REEL
SUPPLIER

~
TAPE & REEL

•

TAPE & REEL OPERATIONS
CONFORMING TO EIA
STANDARDS RS-481

•

INCOMING VISUAL EXAMINATION AND ISSUE STOCK FOR
SHIPMENT

•

FINAL PACKAGING AND
SHIPMENT

•

OUTGOING QUALITY AUDITS

ASSEMBLY
(Sub-contractor)

~
MATERIAL
RECEIPT &
ISSUE TO
STOCKROOM

~
STOCKROOM

~
SHIPPING

J·10

Traceability
At ICS, traceability of products is a critical attribute of the entire production process. Tracking is initiated at the wafer
fabrication process and is maintained through all successive processing steps through final shipment. Records of
traceability are retained to allow for tracking of product delivered to a specific customer so that its source may be
determined if the need arises. Records are also available for communicating with suppliers the identification and
isolation of any problems.

Electrostatic Protection
The phenomenon ofESD (Electrostatic Discharge) can be a source of damage to sensitive semiconductor devices. In
order to address this potential for damage a dual approach is initiated. It is first addressed in the design stage where
the design guidelines provide fur electrostatic protection of the input/output stages of the device. ESD susceptibility
of each device is verified to ensure the design is robust enough to be handled in the customers' environment using
normal handling precautions. A minimum level of 2kV is the standard for design; however, product currently under
test is equal to or exceeds 4kV susceptibility levels. Tests are performed in accordance with MIL STD 883
method 3015.7.
Second, we protect against damage throughout the inspection, test and subsequent handling of parts. All personnel are
aware of the effects of ESD and are trained in proper handling techniques. Work stations are ESD controlled with
ground straps, ESD dissipative table tops and floor mats and air ionizers. Work in process is transported in conductive
tubs and discharged before handling on the dissipative work tables. Parts are shipped in ESD protective tubes or reels
which are further protected by electrostatic protective bags.

Product Qualification and Monitoring
The Quality Assurance Department is responsible for the qualification and monitoring of all devices manufactured by
ICS. This activity is designed to evaluate all wafer processes and package configurations and to maintain a proactive
corrective program to prevent the shipment of unreliable product.

In the qualification process, we apply the following tests and stresses:

High Temperature Operating Life
High temperature operating life (H1DL or HWB) testing is perfurmed to accelerate failure mechanisms which are
thermally activated through the application of extreme temperatures and the use of biased operating conditions. The
temperature and voltage conditions used in the stress will vary with the product being tested. However, the typical
stress ambient is 125°C with the bias applied equal to or greater than the data sheet nominal value. All devices used
in the HWL test are sampled directly after final electrical test with no prior burn-in or other prescreening unless
called out in the normal production flow. Testing can either be perfurmed with dynamic signals applied to the device
or in static bias configuration fur a typical test duration of 1000 hours.

J-ll

Il

Temperature Humidity Bias
Temperature humidity bias (THB) is an environmental test performed at a temperature of 85°C and a relative humidity
of 85 %. The test is designed to measure the moisture resistance of plastic encapsulated circuits. A nominal static bias
is applied to the device to create the electrolytic cells necessary to accelerate corrosion of the metalization. Most groups
are tested to lOOO hours.

Autoclave
Autoclave is an environmental test which measures device resistance to moisture penetration and the resultant effects
of galvanic corrosion. Autoclave is a highly accelerated and destructive test. Conditions employed during the test
include 121°C, 100% relative humidity, and 15 psig. Corrosion of the die is the expected failure mechanism. Groups
of parts are normally tested for a 96 hour duration.

High Temperature Storage
High temperature storage is performed to measure the stability of semiconductor devices during storage at elevated
temperatures with no electrical stress applied. The devices are typically exposed to an ambient of 150°C. An acceleration
of charge loss from the storage cell or threshold changes are the expected results. All groups are typically tested to
lOoohours.

Temperature Cycle
Temperature cycle testing accelerates the effects of thermal expansion mismatch among the different components within
a specific die and packaging system. This test is typically perfurmed per MIL STD 883 or MIL STD 750 with the
minimum and maximum temperatures being -65°C and + 150°C. During temperature cycle testing, devices are inserted
into a cycling system and held at the cold dwell temperature for at least ten minutes. Following this cold dwell, the
devices are heated to the hot dwell where they remain for another ten minute minimum time period. The system employs
a circulating air environment to assure rapid stabilization at the specified temperature. The dwell at each extreme, plus
the two transition times of five minutes each (one up to the hot dwell temperature, another down to the cold dwell
temperature), constitute one cycle. Test duration for this test will vary with the device and packaging system employed.
A typical test consists of 300 cycles, however some tests are extended to look for longer term efrects.

Thermal Shock
The objective of thermal shock testing is the same as that for temperature cycle testing - to emphasize differences in
expansion coefficients for components of the packaging system. However, thermal shock provides the additional stress
of sudden temperature change. This sudden change is due to the shorter transrer time, 10 seconds maximum, and the
increased thermal conductivity of a liquid ambient. This test is typically performed per MIL STD 883 or MIL SID
750 with minimum and maximum temperatures being -65°C to + 150°C. Devices are placed in a fluorocarbon bath
and cooled to minimum specified temperature. After being held in the cold chamber for five minutes minimum, the
devices are transfurred to an adjacent chamber fIlled with fluorocarbon at the maximum specified temperature for an
equivalent time. Two five-minute dwells plus two ten-second transitions constitute one cycle.

J-12

Reliability Data Analysis
Reliability is the probability that a semiconductor device will perform its specified function in a given environment
for a specified period of time. The most frequently used reliability measure is the device failure rate. The failure rate
is obtained by dividing the number of failures observed by the product of the number of total device on test and the
test time interval. This is normally expressed in failures per billion device hours (FITS), which is a point estimate
because it is obtained from observations on a portion, or sample, of the population of devices.
To project the failure rate of devices being tested to a total population, chi-square distribution statistics are applied at
established confidence intervals. These are nominally calculated at 60% and 90% confidence levels to express a level
of confidence that the sample failure rate approximates that of the entire population. In addition, since the failure rate
of semiconductor devices is inherently low, the application of acceleration factors is applied to the data. Commonly
used Arrhenius equations are applied which provide relationships between test stress levels and normal use operation.
In applying this assessment tool an activation energy (Ea) of 0.7Ea is normally used to determine the Acceleration
factor. This Ea level is chosen in lieu of establishing individual Ea values for each of the failure mechanisms applicable
to the technology and circuit under evaluation, particularly since the failure mechanism database is so limited.
To determine the failure rate of ICS products, the HTOL data for individual as well as families of devices is utilized.
HTOL testing provides an adequate thermal stress with the devices being biased at greater than nominal value and
operated in a dynamic mode in this environment. Utilization of these techniques will provide a realistic, conservative
estimation of the product failure rate.

I

J-13

J·14

ICS
Standard
Package Dimensions

K-l

K-2

II

DIP Packages
.......

r-

0260

-,11'-

.......11,--,°.....
30_0

O1"J J
0018.......

0100

8-Pin DIP Package

-+
-+

0.1 30

0260
0.300

...
...

JJ
0.029

0.060 ..........
0.018-+ . . .

.,
0.100

14-Pin DIP Package

I
See individual data sheets for more specific ordering information.

K·3

DIP Packages

.. ..I-+-

~

~I

0.750

~

0.260

-+-

0.300

-+-

\

.....

o130 J

j

0.029

bumnnnniO
---±lMlll¥¥¥~-

o 060~

0018~

t o.130

-+-+-

~

~OO

\

0-5°~

I
-+-

-+-0.010

~

1

~

1-+-0.355

16-Pin DIP Package

. 1+

-'1

1.025

-.

0.260

-.

0.300
....

013O.t--;: bmnnnnnnnril-.l
TMYYY~ ~ ~ TYT
~
0.029

0.060-'

+

-..,

0.018-' +

0.130

0.100

20-Pin DIP Package

See individual data sheets for more specific ordering information.

K-4

+

,

+

J

0-50

-.\

-.1

+

- . +0.010

1+0.355

DIP Packages

+-

o

1..-

-.1

1 250

-.

0260

..-

-.

0300

..-

130J-jlnnnnnnnnnnniil
~
IMIIIIIIIIII~
0029
0050-'

j

..-

-.......,
0018-' . . -

........ 0.010

0.130

1.... 0355

0100

24-Pin DIP Package
,,,

r+----

36lHJtJJ2flA~ _ _ _
~

IS"BOlHENDS

4-~~1HENDS
Q..'il(REF)

Dimensions in millimeters

28-Pin DIP Package

See individual data sheets for more specific ordering information.

K-5

sOle

II

Packages

..

. - 1~ ·190
0.031."
+

----=t

0.024

..t

0.238

+

rO.063

I.. 0.154 +1

_ ..

t

+..,

0050

0.016+ . .

0008

1= UI'-----')11\,; t

-+II~

t

0.006

0015
r

0.025

8-Pin

sOle

Package

em:i
J
~0063
.==
t

+-

003'1

==t

0. 024

1

1..- 0.154 -.1

--

fI=!=====t=\
1=U'-----t

0.008

t1

r+ +- +116150

0.006 ± 0.004

0.016

~

0.238

0.015

14-Pin

0. 031 1
t

.==
==-t

0.024

tr

~
.... 0.390"

t ..II..., -'1
0.016

r

sOle

-t=•

50

16-Pin

Package

.... 0.238 . .

0.063

t o.

006

sOle

See individual data sheets for more specific ordering information.

K-6

I

I tr

0.015

"'0.154.

0. 008

1UI
t

=

Package

)t
II

1 . . . . - .- - - - ' -

\,;

"II..,
0025

II

sOle
L ± .008

.-

Packages

---.

. . . . . 0.029

0.018

Typ.

....~+ 5 Deg. Typ

±5

~

t

JI'

0289 ± 0 005

~ilTYPi

t

o 047R

0.294 ± 0.005
0.328 ± O. 010
0406 ± 0.010

0.289 ± 0.005

! -+t
0.015 x 45 Deg.

., ! ! !

Pin 1

"5 DegTyp.
0.041 ± 0.003--,

.0.101 ±0.010
im--.-0-.0-'-08 ± 0.006

....t....0-01~0~0}

o 092 ± 0.005 ~ '1.1-1.1-1.........-1.1-1

~II.

t t

0.050
Pitch Typ.

sOle Package (wide body)
LEAD COUNT

14L

16L

18L

20L

24L

28L

32L

DIMENSIONL

0.354

0.404

0.454

0.504

0.604

0.704

0.804

See individual data sheets for more specific ordering information.

K-7

II

SOP Package

....-.

1.122± 0.008

-+-

~O.O29

0.018

Typ.

Typ.

+1r-°.008
J

t

i

0.500 ± 0.005

0.631 ± 0012

t
0500 ± 0 005

II

.,
Pin 1

0.031 ± 0.008

mIDm
r+1 1+

0.050
Pitch Typ

SOP Package

See individual data sheets for more specific ordering information.

K·8

-----.£0.008 ± 0.004

f i.0112 ±0010

+
j

1

SSOP Packages
238
DIAPIN

TOP VIEW

BOTTOM VIEW

'4
~'

SEE • . • •
DETAlLt

SIDE VIEW

••

ENOVIEW

PARTING L l N E - - M

8'J~-~.L&..
DETAIL 'A"

SSOP Package
SYMBOL

MIN.

NOM.

4

NOTE

COMMON
DIMENSIONS

6

D
MAX.

NOTE

VARIATIONS

N

MIN.

NOM.

MAX.

A

0.68

0.73

0.78

AA

0.239

0.244

0.249

14

Al

0.002

0.005

0.008

AB

0.239

0.244

0.249

16

A2

0.066

0.068

0.070

AC

0.278

0.284

0.289

20

B

0.010

0.012

0.015

AD

0.318

0.323

0.328

24

AE

0.397

0.402

0.407

28

AF

0.397

0.402

0.407

30

C

0.005
0.205

e

0.209

4
0.212

4

O.026BSC

H

0.301

L

0.022

0.307

0.311

0.030

0.037

0°

4°

5
6

See Variations

N

oc

0.008

See Variations

D
E

0.006

8°

This table in inches.
See individual data sheets for more specific ordering information.

K·9

PLCC Packages

..- Ws --+0045 x45 Deg
Corner

-t

Chamber

Pin 1 Ident

0045 x45 Deg

a 070 Dla x a 025 DP

Corner
Chamber

-~

... • a 050 ± a 002

...

1

t

...

-±-

Tp

fa 030 ± a 005

f0020 Min
.7±2Deg

0035 ± a 005

0015Ref

t

.

t=TF

0029 ± a 005

a 010 Min

J"-Wc--+-J
PLCC Package

Ii

I
I

LEAD
COUNT

FRAME
THICKNESS
TF
±.0003

PKG.
THICKNESS
Tp
±.004

20L

0.010

0.152

0.350

28L

0.010

0.152

0.450

44L

0.010

0.152

0.650

0.010

0.152

68L

0.008

84L

0.008

52L

I

PKG. WIDTH I PKG. WIDTH
TOP
BOTTOM
WT
WB
I
±.066
±.004

OVERALL
PKG. WIDTH
Wo
±-.005

CONTACT
WIDTH
Wo
±.01O/-.030

t

0.323

0.390

0.320

0.423

0.490

0.420

0.623

0.690

0.620

0.750

0.723

0.790

0.720

0.150

0.950

0.923

0.990

0.920

0.150

1.160

1.123

1.190

1.120

See individual data sheets for more specific ordering information.

K-IO

II

QFP Packages

~D--~

10'

*
tt
A,

A,

l'IP.

fA

~""Ii"iiiiiliiiliijitJ
10'

+
•

~t~~~~~~~~~~~

l'IP.

QFP Package
LEAD COUNT

44L

I

64L

BODY TIIICKNESS

SOL

I

TOLERANCE

A

MAX.

0.25 MIN.

2.0

2.70

D

±D.25

13.20

17.20

±D.I0

10.0

14.00

E

iO.25

13.20

23.20

EI

±D. 10

10.0

20.00

L

±D. 15/0.10

0.70

O.SS

O.SO

BASIC
+0.05

ccc

MAX.

ddd

1

0.25 MAX.

DI

e

SOL

100L

3.40

2.45

2.35

±D. 10

b

I

3.20

Al
A2

64L

2.70

FOOTPRINT (BODY+)
DIMENSIONS

100L

2.0

1.00

I

0.35

o.so

1 0.65
I

0.30

1.00

I

o.so

0.35

1

0.65

I

0.30

I

0.12
NOM.

0.10.
0.20 NOM.

I

0.12
NOM.
0 0 _7 0

0
See individual data sheets for more specific ordering information.

K·ll

0.20 NOM.

TQFP Packages

Q,17MAJ(.J

TQFP Package
LEAD COUNT

32L

BODY THICKNESS

1.00

1.40
2,00

FOOTPRINT (BODY+)
DIMENSIONS

TOLERANCE

A

MAX,

1.20

A2

±O,5

1.00

D

±O,25

9,00

DI

±0,1O

7.00

E

±0.25

9,00

EI

±0.1O

7.00

L

±O, 15/-0. 10

0.60

0,05 MINJO, lO MAX,

Al

1.40

e

BASIC

O.SO

0,50

b

+0.05

0.35

0.22

ccc

MAX,

ddd
I

1.60

0

0.10

O.OS

0.20 MAX,

O,OSMAX,
0° - 7°

See individual data sheets for more specific ordering information.

K-12

,I

ICS

Sales Offices
and
Sales Representatives

I
L-l

L-2

Integrated Circuit Systems, Inc.
ICS Salt's Offict's

Eastern & Central Area

Northern Area

Western Area

Headquarters
Integrated Circuit Systems, Inc.
2435 Boulevard of the Geoerals, P.O. Box 968
Valley Forge, PA 19482-0968
Phone: (610) 630-5300
Fax: (610) 630-5399
Toll-Free: 1-800-220-3366

Integrated Circuit Systems, Inc.
Suite 30
8330 Madison Street
Borr Ridge, IL 60521
Phone: (708) 323-1397
Fax: (708) 323-0741

Integrated Circuit Systems. Inc.
1271 Parkmoor Avenue
San Joae, CA 95126
Phone: (408) 297-1201
Fax: (408) 925-9460

DOJ11t'sti(·

ICS Salt's Rt'prt'st'ntativt's

Alabama

Florida

Maryland

Eleam
Suite 145K
4960 Corporate Drive
Huntsville, AL 35805
Phone: (205) 830-4001
Fax: (205) 830-4058

Semtronic Associates
657 Maitland Avenue
A1taJnodc Springs, PI. 32701
Phone: (407) 831-8233
Fax: (407) 831-2844

(pleaae call rcs headquar- (Nol1hem)
ten for rep in this area.)
Astrorep, Inc.
103 Cooper Street
Babylon, NY 11702
Massachusetts
(pleaae call rcs headquar- Phone: (516) 422-2500
ters for rep in this area.)
Fax: (516) 422-2504

Florida

New Jersey

(consinued)

(llt-Slem)

Michigan

_~Associates

1467 S. Missouri Avenue

Suite 2
4520 E. lodian School Rd.
Phoenix, AZ 85018
Phone: (602) 955-3193
Fax: (602) 955-3224

Clearwater, PI. 34616
Phone: (813) 461-4675
Fax: (813) 442-2234

C.B. Jensen & Associates
Ste. 201, 2145 Croolcs Rd.
Troy, Mr 48084-5318
Phone: (810) 643-0506
Fax: (810) 643-4735

Arizona

(Southem)
3471 N.W. 55th Street
Ft. Lauderdale, PI. 33309
Arkansas
Phone: (305) 731-2484
Impaq Sales
Ste. 140, 100 Decker Court Fax: (305) 731-1019
Irving,"IX 75062
Georgia
Phone: (214) 650-0000
Elcom
Fax: (214) 650-1953
3060C Business Park Dr.
Norcross, GA 30071
California
Phone: (404) 447-8200
(Nol1hem)
Fax: (404) 447-8340
(please call rcs headquarters for rep in this area.)
Idaho
Waugaman Associates, Inc.
876 E. Vine Street
(SoU/hem)
Salt Lake City, UT 84107
TNT & Associates, Inc.
Phone: (SOl) 261-0802
Suite 19
Fax: (801) 261-0830
22865 Lake Forest Drive
Lake Forest, CA 92630
Dlinois
Phone: (714) 830-6096
KMASales
Fax: (714) 830-0154
1040 S. ArIingtonHeigbtsRd.
Arlington Heights, IL 6
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