1995_Linear_Databook 1995 Linear Databook

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1995
Linear
Databook
Volume IV

1995 Linear Databook
Volun1e IV

..

Data Conversion
References
Amplifiers
Power Products
Filters
Interface

--- -..

..

QUICK REFEREnCE InDEX
LF155 ...................
LF156 ...................
LF198 ...................
LF355 ...................
LF356 ...................
LF398 ...................
LF398S8 ...............
LF412A .................
LH0070 .................
LH2108A ..............
LM10 ....................
LM101A ................
LM107 ..................
LM108 ..................
LM1 08A ................
LM111 ..................
LM117 ..................
LM117HV .............
LM118 ..................
LM119 ..................
LM123 ..................
LM129 ..................
LM134 Series .......
LM136-2.5 ............
LM137 ..................
LM137HV .............
LM138 ..................
LM150 ..................
LM185-1.2 ............
LM185-2.5 ............
LM199 ..................
LM199A ................
LM301A ................
LM307 ..................
LM308 ..................
LM308A ................
LM311 ..................
LM317 ..................
LM317HV .............
LM318 ..................
LM318S8 ..............
LM319 ..................
LM323 ..................
LM329 ..................

'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B
'900B

2-271
2-271
9-97
2-271
2-271
9-97
9-113
2-275
.3-65
2-279
2-281
2-297
2-297
2-303
2-303
6-85
4-137
4-145
2-311
6-93
4-149
3-83
3-87
3-101
4-157
4-165
4-169
4-177
3-105
3-109
3-115
3-115
2-297
2-297
2-303
2-303
6-85
4-137
4-145
2-311
2-319
6-93
4-149
3-83

LM334S8 .............. '900B
LM336-2.5 ............ '900B
LM337 .................. '900B
LM337HV ............. '900B
LM338 .................. '900B
LM350 .................. '900B
LM385-1.2 ............ '900 B
LM385-2.5 ............ '900B
LM385S8-1.2 ....... '900B
LM385S8-2.5 ....... '900B
LM399 .................. '900B
LM399A ................ '900B
LT111A ................. '900B
LT117A ................. '900B
LT117AHV ............ '900B
LT118A ................. '900B
LT119A ................. '900B
LT123A ................. '900B
LT137A ................. '900B
LT137AHV ............ '900B
LT138A ................. '900B
LT150A ................. '900B
LTC201A ............... '920B
LTC202 ................. '920B
LTC203 ................. '920B
LTC221 ................. '920B
LTC222 ................. '920B
LT311A ................. '900B
LT317A ................. '900B
LT317AHV ............ '900B
LT318A ................. '900B
LT319A ................. '900B
LT323A ................. '900B
LT337A ................. '900B
LT337AHV ............ '900B
LT338A ................. '900B
LT350A ................. '900B
LTC485 ................. '920B
LTC486 ................. '920B
LTC487 ................. '920B
LTC488 ................. '940B
LTC489 ................. '940B
LTC490 ................. '920B
LTC491 ................. '920B

3-99
3-101
4-157
4-165
4-169
4-177
3-105
3-109
3-113
3-113
3-115
3-115
6-85
4-137
4-145
2-311
6e93
4-149
4-157
4-165
4-169
4-177
11-4
11-4
11-4
11-15
11-15
6-85
4-137
4-145
2-311
6-93
4-149
4-157
4-165
4-169
4-177
5-6
5-16
5-24
5-158
5-158
5-32
5-40

LT574A ........................ 6-48
LT580 ................... '900B 3-121
LT581 ................... '900B 3-121
LTC660 ........................ 4-53
LT685 ................... '900B
6-5
9-4
LTC690 ................. '92DB
9-4
LTC691 ................. '920B
LTC692 ................. '940B
9-4
9-4
LTC693 ................. '940B
9-4
LTC694 ................. '920B
LTC694-3.3 ........... '940B 9-19
9-4
LTC695 ................. '920B
LTC695-3.3 ........... '940B 9-19
LTC699 ................. '920B 9-18
LT1 001 ................. '900B 2-11
LT1 001 CS8 ........... '900B 2-23
LT1 002 ................. '900B 2-25
LT1 003 ................. '900B
4-9
LT1 004 ................. '900B 3-17
LT1 004CS8-1.2 .... '900B 3-25
LT1 004CS8-2.5 .... '900B 3-25
LT1 005 ................. '900B 4-17
LT1 006 ................. '900B 2-41
LT1 006S8 ............. '900B 2-53
LT1007 ................. '900B 2-57
LT1 007CS ............. '900B 2-69
LT1 007CS8 ........... '920B 2-16
LT1 008 ................. '900B 2-73
LT1 009 Series ...... '900B 3-27
LT1 009S8 ............. '900B 3-31
LT1010 ................. '900B 2-85
LT1011 ................. '900B
6-9
LT1012 ................. '900B 2-105
LT1 012S8 ............. '900B 2-117
LT1013 ................. '920B 2-19
LT1014 ................. '920B 2-19
LT1015 ................. '920B 10-4
LT1016 ................. '900B 6-25
LT1 016CS8 ........... '900B 6-41
LT1017 ................. '940B 10-4
LT1018 ................. '940B 10-4
LT1019 ................. '900B 3-33
LT1020 ................. '900B 4-29
LT1 020CS ............. '900B 4-45

Note: Atl products in BOLD are in this Oatabook, others appear in LTC's 1990. 1992 and 1994 Oatabooks ('9008 =LTC's 1990 Oatabook. '9208 =LTC's 1992 Oatabook Supplement
and '9408 = LTC's 1994 Oatabook). Quick Reference Index continued on inside back pages.

"FRom YOUR minD TO YOUR mARKET••• AnD
EVERYTHinG In BETWEEn
fI

This is Volume IV of LTC's four volume series of databooks. This issue contains device data sheets and
applications circuits for the products introduced since Volume 11/ was printed in June of 1994.
Extraordinary growth in the high performance linear market has continued to drive the design efforts for
these products. The result is increased complexity, higher efficiency, lower power and more cost-effective
solutions. Included within the four book set are high performance products targeted to suit diverse
applications within the Industrial, Test and Measurement, Telecom, Computer, Automotive and Military
market segments.
In this edition, you will find a significant number of new products such as; A-to-D and D-to-A Converters,
Multiplexers, High Performance Voltage References, High Speed Amplifiers, Ultralow Power Comparators,
Low Power Advanced Interface Circuits for RS232 through 11.35 protocols, Infrared Receivers, High
Frequency Switching Regulators, Fast Response Linear Regulators, PCMCIA devices and other advanced
Power Control products.
For acomplete set of information consult Volume I (1990), Volume" (1992), Volume 11/ (1994) and this issue,
Volume III.
The Table of Contents and alphanumeric index in this volume provide guides to locate each LTC product
within the four volume set. Use this guide to find the correct page in the appropriate volume.
LTC offers the latest in high performance wafer processing including bipolar, LTCMOS, micropower, high
speed, complementary bipolar and BiCMOS technologies. These processes are used in two wafer
fabrication facilities located in Milpitas, California with a third facility under construction in Camas,
Washington at the time this data book went to print. A new assembly plant is located in Penang, Malaysia
and our new Far East Headquarters is located in Singapore. The wafer fabrication and test facilities are
certified to ISO 9001 by TDv Rheinland and certified by DESC for JAN Band JAN S level microcircuits. These
certifications are part of LTC's Quality and Reliability program in support of military/aerospace and radiation
hardened requirements.
LTC appreciates your continued support and remains dedicated to providing the highest quality products,
applications assistance and manufacturing knowledge to service your high performance analog requirements.

1

Linear "Technology Corporation

1995 Linear Databook
Volume IV

Note: The 1995 Linear Databook is the fourth volume in our series of databooks to date totaling approximately 5800 pages
of product and applications information for approximately 3000 individual products, presented in a four volume set of
databooks. The 1990 Linear Databook is Volume I; the 1992 Linear Databook Supplement when reprinted will become Volume
II. The 1994 Linear Databook Volume 1/1 Table of Contents references device types included in Volumes 1-3. Volume 4 Table
of Contents references data in Volumes 1-4.
.L"T, LTC and LT are registered trademarks of Linear Technology Corporation.

LIFE SUPPORT POLICY
LINEAR'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT
THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF LINEAR TECHNOLOGY CORPORATION. As used herein:

a. Life support devices or systems are devices or systems which (1) are intended for surgical implant into the body, or (2) support or sustain
life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in a significant injury to the user.
b. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness.
Information furnished herein by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed
for its use. LinearTechnology Corporation makes no representation thatthe interconnection of its circuits, as described herein, will not infringe
on existing patent rights.

Linear Technology Corporation -1630 McCarthy Blvd. - Milpitas, CA 95035 - (408) 432-1900 © Linear Technology Corporation 1995 Printed in USA

3

1995
Linear
Databook
Volume IV

II

GEnERAL InFORmATion

EI
II

AmPLIFIERS
InSTRumEnTATion AmPLIFIERS

II

POWER PRODUCTS

11

InTERFACE

•IIII

DATA conVERSion
VOLTAGE REFEREnCES
monoLITHIC FILTERS

a

miCROPROCESSOR SUPERVISORY CIRCUITS

1m

comPARATORS

m
m

SPECIAL FunCTions
miLITARY PRODUCTS

lEI
II

nEW PRODUCTS
PACKAGE DimEnSions

1m

APPEnDICES

L7~J!J~

5

TABLE OF CONTENTS
SECTION 1-GENERAL INFORMATION
INDEX ........................................................................................................................................ 1-2
GENERAL ORDERING INFORMATION .................................................................................................... 1-3
ALTERNATE SOURCE CROSS REFERENCE GUIDE ..................................................................................... 1-4

SECTION 2-AMPLIFIERS
INDEX ........................................................................................................................................ 2-2
SELECTION GUIDES ........................................................................................................................ 2-3
PROPRIETARY PRODUCTS
PRECISION OPERATIONAL AMPLIFIERS ............................................................................................. 2-13
LTt001, Precision OpAmp ................................................................................................................................ '90DB 2-11
LTt001CSB, Precision Op Amp ......................................................................................................................... '90DB 2-23
LT1002, Dual, Matched Precision Op Amp ........................................................................................................ '90DB 2-25
LTt006, Precision, Single Supply Op Amp ........................................................................................................ '90DB 2-41
LTl006SB, Precision, Single Supply Op Amp .................................................................................................... '90DB 2-53
LTt007, Low Noise, High Speed Precision Op Amp .......................................................................................... '90DB 2-57
LTt007CS/L Tt037CS, Low Noise, High Speed Precision Op Amps .................................................................. '90DB 2-69
LTt007CSB/L Tl037CSB, Low Noise, High Speed Precision Operational Amplifiers .......................................... '92DB 2-16
LTtOOB, Picoamp Input Current, Microvolt Offset, Low Noise Op Amp ............................................................. '90DB 2-73
LTtOl0, Fast±150mA Power Buffer .................................................................................................................. '90DB 2-85
LTl012, Picoamp Input Current, Microvolt Offset, Low Noise Op Amp ............................................................. '90DB 2-105
LTtOI2SB, Picoamp Input Current, Microvolt Offset, Low Noise Op Amp ......................................................... '90DB 2-117
LTt 013/L Tt 014, Dual/Quad Precision Operational Amplifiers ........................................................................... '92DB 2-19
LTt022, High Speed, Precision JFET Input Op Amp .......................................................................................... '90DB 2-145
LTl024, Dual, Matched Picoampere, Microvolt Input, Low Noise Op Amp ........................................................ '90DB 2-153
LTt02B, Ultra-Low Noise Precision High Speed Op Amp .................................................................................. '94DB 2-12
LTt037, Low Noise, High Speed Precision Op Amp .......................................................................................... '90DB 2-57
LT1055, Precision, High Speed, JFET Input Op Amp ......................................................................................... '90DB 2-219
LTt056, Precision, High Speed, JFET Input Op Amp ......................................................................................... '90DB 2-219
LTt055SB/LTt056SB, Precision, High Speed, JFET Input Op Amps .................................................................. '90DB 2-231
LTt057, Dual JFET Input Precision, High Speed Op Amp .................................................................................. '90DB 2-235
LTl057S/LT1057IS, LTl05BS/LT105BIS, Dual/Quad JFET Input Precision High Speed Op Amps .................... '92DB 2-41
LTt057SB/L Tt0571SB, Dual JFET Input Precision High Speed Op Amps .......................................................... '92DB 2-44
LTt05B, Quad JFET Input Precision, High Speed Op Amp ................................................................................. '90DB 2-235
LTt071, Micropower, Single Supply, Precision Operational Amplifier ............................................................... '92DB 2-45
LTt 07B/L Tt 079, Micropower, Dual/Quad, Single Supply, Precision Operational Amplifiers .............................~ '92DB 2-56
LTl097, Low Cost, Low Power Precision Operational Amplifier ........................................................................ '92DB 2-74
LTIII21LTtI14, Dual/Quad Low Power Precision, Picoamp Input Op Amps .................................................... '94DB 2-29
LTt113, Dual Low Noise, Precision, JFET Input Op Amps ................................................................................. '94DB 2-40
LT1115, Ultra-Low Noise, Low Distortion, Audio Operational Amplifier ............................................................ '92DB 2-82
LT1124/L Tt125, Dual/Quad Low Noise, High Speed Precision Operational Amplifiers ..................................... '92DB 2-94
LTI126/LTI127, Dual/Quad Decompensated Low Noise, High Speed Precision Operational Amplifiers ........... '92DB 2-105
LTtI2B, Unity Gain Stable Ultra-Low Noise Precision High Speed Op Amp ...................................................... '94DB 2-12
LT1169, Dual Low Noise, Picoampere Bias Current, JFET Input Op Amp .......................................................... '94DB 2-55
Note: All products in BOLD are in this Oatabook. others appear in LTC's 1990, 1992 and 1994 Oatabooks ('900B = LTC's 1990 Oatabook, '920B = LTC's 1992 Oatabook Supplement
and '9408 = LTC's 1994 Oatabook) .

.L7lJ!J~

7

TABLE OF CONTENTS
LTt178/L Tt179, 17pA Max, Dual/Quad, Single Supply, Precision Operational Amplifiers ................................. '9208 2-112
LT1178S8, 20pA Max, Dual SO-8 Package, Single Supply Precision Op Amp ................................................... '9408 2-67
LT1366/L T1367/L T1368/L T1369, Dual and Quad Precision Rail-to-Raillnput and Output Op Amps •••.••.•...•...•..•. 2-14
LT1413, Single Supply, Dual Precision Op Amp ................................................................................................ '9408 2-68
LT145?, Dual, Precision JFET Input Op Amp ..................................................................................................... '9408 2-76
PRECISION OPERATIONAL AMPLIFIERS, ENHANCED AND SECOND SOURCE
LF155/LF355, JFET Input Op Amp, Low Supply Current .................................................................................... '9008 2-271
LF155A1LF355A, JFET Input Op Amp, Low Supply Current ............................................................................... '9008 2-271
LF156/LF356, JFET Input Op Amp, High Speed ................................................................................................. '9008 2-271
LF156A1LF356A, JFET Input Op Amp, High Speed .......................................................~ ..................................... '9008 2-271
LF412A, Dual Precision JFET Input Op Amp ...................................................................................................... '9008 2~275
LH2108A, Dual LM108 Op Amp ...................................................................................................,..................... '9008 2-279
LM10/8(L)/C(L), Low Power Op Amp and Reference ........................................................................................ '9008 2-281
LM1 01A1LM301 A, Uncompensated General Purpose Op Amp .......................................................................... '9008 2-297
LM107/LM307, Compensated General Purpose Op Amp ................................................................................... '9008 2-297
LM108/LM308, Super Gain Op Amp ..................................................................................................................'9008 2-303
LM108A1LM308A, Super Gain Op Amp ............................................................................................................. '9008 2-303
LM118/LM318, High Slew Rate Op Amp .........................................................................,................................. '9008 2-311
LM318S8, High Speed Op Amp ...............................................................................,......................................... '9008 2-319
LT118A1LT318A, Improved LM118 Op Amp ...................................................................................................... '9008 2-311
OP-05, Internally Compensated Op Amp ........................................................................................................... '9008 2-321
OP-07, Precision·Op Amp ................................................... :.............................................................................. '9008 2-329
OP-07CS8, Precision Op Amp ........................................................................................................................... '9008 2-337
OP-15, Precision, High Speed JFET Input Op Amp ............................................................................................ '9008 2-341
OP-16, Precision, High Speed JFET Input Op Amp .............................................................................................'9008 2-341
OP-27, Low Noise, Precision Op Amp ............................................................................................................... '9008 2-345
OP-37, Low Noise, High Speed Op Amp ....................................... ,..................................................................... '9008 2-345
OP-215, Dual Precision JFET Input Op Amp ...................................................................:.................................. '9008 2-275
OP-227, Dual Matched, Low Noise Op Amp ...................................................................................................... '9008 2-357
OP-237; Dual High Speed, Low Noise Op Amp .................................................................................................. '9008 2-357
OP-270/0P-470, Dual/Quad Low Noise, Precision Operational Amplifiers .........................................................'9208 2-120
HIGH SPEED AMPLIFIERS .............................................................................................................. 2-33
LTt122, Fast Settling, JFET Input Operational Amplifier .................................................................................... '9408 2-84
LTt18?, Low Power Video Difference Amplifier................................................................................................. '9408 2-92
LTt189, Low Power Video Difference Amplifier................................................................................................. '9408 2-104
LTt190, Ultra High Speed Operational Amplifier (Av:? 1) ...........................................................................:...... '9208 2-126
[Tti91, Ultra High Speed Operational Amplifier (Av:? 1) .................................................................................. '9208 2-137
LTti92, Ultra High Speed Operational Amplifier (Av :?5) .................................................................................. '9208 .2-148
LT119'S, Video Difference Amplifier, Adjustable Gain ................... :..................................................................... '9208 2-159
LTt194, Video Difference Amplifier, Gain of 10 ................................................................................................. '9208 2-171
LTt19S, Low Power, High Speed Operational Amplifier ...................................................................:................ '9408 2-116
LTt2QO, Low Power High Speed Operational Amplifier ...................................................:................................. '9208 2-182
LTt201/LTt202, Dual and Quad lmA, 12MHz, 50VljlS Op Amps .......................... :: .......................................... '9408 2-127
LTt206, 250mAl60MHz Current Feedback Amplifier ......................................................................................... '9408 2-137
LTt208/L T1209, Dual and Quad 45MHz, 400V/jlS Op Amps ............................................................................. '9408 2-150
Note: All products in BOLD are in this Databook, others appear in LTC's 1990, 1992 and 1994 Databooks (,90DB. LTC's 1990 Databook, '92DB. LTC's 1992 Databook Supplement
and '94DB. LTC's 1994 Databook).

8

TABLE OF CONTENTS
LT1211ILTI212, 14MHz, 7V1f1S, Single Supply Dual and Quad Precision Op Amps ......................................... .'940B 2-160
LTI213ILTI214,28MHz, 12V1JiS, Single Supply Dual and Quad Precision Op Amps ........................................ '940B 2-176
LT1215ILTI216, 23MHz, 50VlJiS, Single Supply Dual and Quad Precision Op Amps ........................................ '940B 2-192
LT121 7, Low Power High Speed Current Feedback Amplifier ............................................................................ '920B 2-190
LT1220, Vel}' High Speed Operational Amplifier (Av 2 1) ..................................................................................'920B 2-198
LT1221, Vel}' High Speed Operational Amplifier (Av 2 4) .................................................................................. '920B 2-210
LT1222, Low Noise, Vel}' High Speed Operational Amplifier (Av 2 10) ............................................................. '920B 2-218
LT1223, 100MHz Current Feedback Amplifier.................................................................................................... '920B 2-226
LT1224, Vel}' High Speed Operational Amplifier (Av 2 1) .................................................................................. '920B 2-237
LT1225, Vel}' High Speed Operational Amplifier (Av 2 5) .................................................................................. '920B 2-245
LT1226, Low Noise Vel}' High Speed Operational Amplifier (Av 2 25) .............................................................. '920B 2-253
LT1227, 140MHz Video Current Feedback Amplifier .......................................................................................... '940B 2-208
LT1228, 100MHz Current Feedback Amplifier with DC Gain Control .................................................................. '920B 2-261
LT12291LT1230, Dual and Quad 100MHz Current Feedback Amplifiers ............................................................. '920B 2-280
LT1251ILT1256, 40MHz Video Fader and DC Gain Controlled Amplifiers .......................................................... '940B 2-219
LT1252, Low Cost Video Amplifier .................................................................................................................... '940B 2-242
LT12531L T1254, Low Cost Dual and Quad Video Amplifiers ............................................................................. '940B 2-249
LT12591LT1260, Low Cost Dual and Triple 130MHz Current Feedback Amplifiers with Shutdown .................. .'940B 2-256
LT1311, Quad 12MHz, 145ns Settling Precision Current-to-Voltage Converter for Optical Disk Drives ................ 2-34
LT1354, 12MHz, 400Vlf1S Op Amp .................................................................................................................... '940B 2-267
LT13551L T1356, Dual and Quad 12MHz, 400Vlf1S Op Amps ............................................................................. '940B 2-278
LT1357, 25MHz, 600Vlf1S Op Amp .................................................................................................................... '940B 2-289
LT13581L T1359, Dual and Quad 25MHz, 600Vlf1S Op Amps ............................................................................. '940B 2-300
LT1360, 50MHz, 800Vlf1S Op Amp ....................................................................................................................'940B 2-311
LT13611L T1362, Dual and Quad 50MHz, 800Vlf1S Op Amps ............................................................................. '940B 2-322
LT1363,70MHz, 1000Vlf1S OpAmp .................................................................................................................. '940B 2-333
LT1364ILT1365, Dual and Quad 70MHz, 1000Vlf1S Op Amps ........................................................................... '940B 2-344
ZERO-DRIFT OPERATIONAL AMPLIFIERS ........................................................................................... 2-41
LTC1047, Dual Micropower Zero-Drift Operational Amplifier with Internal CapaCitors ...................................... '920B 2-292
LTCI 049, Low Power Zero-Drift Operational Amplifier with Internal Capacitors ................................................ '920B 2-299
LTCI 050, Precision Zero-Drift Op Amp with Internal Capacitors ....................................................................... '900B 2-181
LTCt0511LTC1053, DuallQuad Precision Zero-Drift Operational Amplifiers with Internal Capacitors ................ '920B 2-306
LTC1052, Zero-Drift Op Amp ............................................................................................................................. '900B 2-197
LTC1052CS, Zero-Drift Op Amp ........................................................................................................................ '900B 2-217
LTC1150, ±15V Zero-Drift Operational Amplifier with Internal CapaCitors ......................................................... '920B 2-321
LTC1151, Dual ±15V Zero-Drift Operational Amplifier ....................................................................................... '940B 2-356
LTC1152, Rail-to-Raillnput Rail-to-Rail Output Zero-Drift Op Amp ... ...................................................... 2-42
LTC1250, Vel}' Low Noise Zero-Drift Bridge Amplifier ....................................................................................... '940B 2-364
ZERO-DRIFT OPERATIONAL AMPLIFIERS, ENHANCED AND SECOND SOURCE
LTC7652, Chopper Stabilized Op Amp ............................................................................................................... '900B 2-197
MULTIPLEXERS
LT12031L T1205, 150MHz Video Multiplexers .................................................................................................... '940B 2-374
LT1204, 4-lnput Video Multiplexer with 75MHz Current Feedback Amplifier ..................................................... '940B 2-389

Note: All products in BOLO are in this Databook, others appear in LTC's 1990. 1992 and 1994 Databooks (,90D8 =LTC's 1990 Databook, '92D8 =LTC's 1992 Databook Supplement
and '94D8 = LTC's 1994 Databook).

9

TABLE OF CONTENTS
SECTION 3-INSTRUMENTATION AMPLIFIERS
INDEX .••...••.••••...••.....•••••....••••.••••••••.•••.•••••..•.•••.••••..••••••.•..•••.....•..••••...••....•.••••••....•••••....••..••••.•.. 3-2
SELECTION GUIDE .................................................................................................:....................... 3-3
PROPRIETARY PRODUCTS
LTC1043, Dual Instrumentation Switched Capacitor Building Block .................................................................. '9008 11-15
LTC1100, Precision, Zero Drift Instrumentation Amplifier ................................................................................. '9208
3-4
LTt101, Precision, Micropower, Single Supply Instrumentation Amplifier (Fixed Gain = 10 or 100) ................ '9208 3-11
LTt102, High Speed, Precision, JFET Input Instrumentation Amplifier (Fixed Gain =10 or 100) ...................... '9208 3-23
LT1193, Video Difference Amplifier, Adjustable Gain ......................................................................................... '9208 2-159
LTt194, Video Difference Amplifier, Gain of 10 ................................................................................................. '9208 2-171

SECTION 4-POWER PRODUCTS
INDEX .•••........••.........•.........•.•...•...•.........•......••......••.......••......••.•...••••••..••..•••.••••••.•.....••••....•••••.. 4-2
SELECTION GUiDES ........................................................................................................................ 4-4
PROPRIETARY PRODUCTS
INDUCTORLESS DC TO DC CONVERTERS ........................................................................................... 4-19
LTt 026, Voltage Converter ................................................................................................................................'9008
5-3
LTC104417660, Switched Capacitor Voltage Converter ...................................................................................... '9008
5-9
LTC1044A, 12V CMOS Voltage Converter .......................................................................................................... '9408 4-16
LTC1044CS8, Switched Capacitor Voltage Converter ........................................................................................ '9008 5-21
LTC1046, 50mA Switched Capacitor Voltage Converter ....................................................................................'9208 4-16
LTt 054, Switched-CapaCitor Voltage Converter with Regulator ......................................................................... '9408 4-26
LTC1144, Switched-Capacitor Wide Input Range Voltage Converter with Shutdown ........................................ '9408 4-38
LTC1261, Switched CapaCitor Regulated Voltage Inverter ........................................ ,........................... 4-20
LTC1262, 12V, 30mA Flash Memory Programming Supply ................................................................... 4-34
LTC1429, Clock-Synchronized Switched Capacitor-Regulated Voltage Inverter ........................................... 4-41
LTC1550/LTC1551, Low Noise, Switched Capacitor-Regulated Voltage Inverters ..................................... 13-142
INDUCTORLESS DC/DC CONVERTERS, ENHANCED AND SECOND SOURCE
LTC66D, 1DDmA CMOS Voltage Converter ........................................................................................ 4-53
HIGH SIDE SWITCHES
LTt 089, High Side Switch ..................................................................................................................................'9008 11-45
LTC1155, Dual High Side Micropower N-Channel MOSFET Driver with Internal Charge Pump ........................ .'9208 4-26
LTC1156, Quad High Side Micropower N-Channel MOSFET Driver with Internal Charge Pump ....................... .'9208 4-41
LTt188, 1.5A High Side Switch .........................................................................................................................'9208 4-48
LINEAR REGULATORS .................................................................................................................. 4-63
LT1003, 5 Volt, 5 Amp Voltage Regulator .......................................................................................................... '9008
4-9
LTt 005, Logic Controlled Regulator .................................................................................................................. '9008 4-17
LTt 020, Micropower Regulator and Comparator ............................................................................................... '9008 4-29
LTt 020CS, Micropower Regulator and Comparator .......................................................................................... '9008 4-45
LTt 033, 3A Negative Adjustable Regulator ........................................................................................................ '9008 4-49
LT1035, Logic Controlled Regulator ..................................................................................................................'9008 4-57
LTt 036, Logic Controlled Regulator ..................................................................................................................'9008 4-69
LTt 038, 10 Amp Positive Adjustable Voltage Regulator .................................................................................... '9008 4-77
LTt0831LT10841L Tt085, 7.5A, 5A, 3A Low Dropout Positive Adjustable Regulators ........................................ '9408 4-48
Nate: All products in BOLD are in this Databaak, athers appear in LTC's 1990, 1992 and 1994 Databaaks (,90DB = LTC's 1990 Databaak. '92DB = LTC's 1992 Databaak Supplement
and '94DB =LTC's 1994 Databaak).

10

TABLE OF CONTENTS
LT1083/LT1084/LT1085, 7.5A, 5A, 3A Low Dropout Positive Fixed Output Regulators .................................... '940B 4-61
LT10B6 Series, 1.5A Low Dropout Positive Regulators Adjustable and 2. 85 V, 3.3V, 3.6V, 5V, l2V .................. '940B 4-72
LTl OB7, Adjustable Low Dropout Regulator with Kelvin-Sense Inputs .............................................................. '920B 4-56
LT1ll7/L T1ll7-2.85/L T1ll7-3.3/LTll17-5, BOOmA Low Dropout Positive Regulators Adjustable and
Fixed 2. 85 V, 3.3V, 5V ........................................................................................................................................ '940B 4-85
LT1118-2.5/LT1118-2.85/LT1118-5, Low la, Low Dropout, 800mA Source and Sink Regulators
Fixed 2.5V, 2.85V, 5V Output ....................................................................................................... 4-64
LTl120, Micropower Regulator with Comparator and Shutdown ...................................................................... '940B 4-96
LTl120A, Micropower Regulator with Comparator and Shutdown .................................................................... '940B 4-107
LT1l2l/L T1l2l-3.3/L T1l2l-5, Micropower Low Dropout Regulators with Shutdown ..................................... '940B 4-114
LT1l23, 5V Low Dropout Regulator Driver ........................................................................................................ '920B 4-75
LTl129/L T1l29-3.3/L Tl129-5, Micropower Low Dropout Regulators with Shutdown ..................................... '940B 4-125
LT1175, 500mA Negative Low Dropout Micropower Regulator ............................ ................................... 4-68
LTl185, Low Dropout Regulator with Adjustable Current Limit ......................................................................... '920B 4-86
LT1521/L T1521-3/L T1521-3.3/LT1521-5, 300mA Low Dropout Regulators with Micropower
Quiescent Current and Shutdown .................................................................................................. 4-79
LT1528, 3A Low Dropout Regulator for Microprocessor Applications ....................................................... 4-91
LT1529/LT1529-3.3/LT1529-5, 3A Low Dropout Regulators with Micropower Quiescent Current and Shutdown ... 4-101
LT1580/LT1580-2.5, 7A, Very Low Dropout Regulators .................................................................... 13-148
LT1584/LT1585/LT1587, 7A, 4.6A, 3A Low Dropout Fast Response Positive Regulators Adjustable and Fixed ..... 4-112
LINEAR REGULATORS, ENHANCED AND SECOND SOURCE
LM117/LM317, Positive Adjustable Regulator ................................................................................................... '900B 4-137
LTl17A1LT3l7A, Improved LMl17 .................................................................................................................... '900B 4-137
LM117HVI LM317HV, High Voltage Positive Adjustable Regulator ................................................................... '900B 4-145
LT1l7AHV/LT3l7AHV, Improved LMl17HV...................................................................................................... '900B 4-145
LM123/LM323, 5 Volt, 3 Amp Regulator ...........................................................................................................'9OOB 4-149
LT123A1LT323A, Improved LM123 .................................................................................................................... '900B 4-149
LM137/LM337, Negative Adjustable Regulator .................................................................................................. '900B 4-157
LT137A,ILT337A, Improved LM137 ................................................................................................................... '900B 4-157
LM137HV/LM337HV, High Voltage Negative Adjustable Regulator ................................................................... '900B 4-165
LT137AHVlLT337AHV, Improved LM137HV. ..................................................................................................... '900B 4-165
LM138/LM338, 5 Amp Positive Adjustable Regulator ....................................................................................... '900B 4-169
LT13BAlLT33BA, Improved LM13B .................................................................................................................... '900B 4-169
LM150/LM350, 3 Amp Positive Adjustable Regulator ....................................................................................... '900B 4-177
LT150AlLT350A, Improved LM150 .................................................................................................................... '900B 4-177
POWER AND MOTOR CONTROL ..................................................................................................... 4-125
LTCl153, Auto-Reset Electronic Circuit Breaker ................................................................................................ '940B 4-138
LTCl154, High-Side Micropower MOSFET Driver .............................................................................................. '940B 4-152
LTCl157, 3.3V Dual Micropower High-Side/Low-Side MOSFET Driver ............................................................. '940B 4-167
LTl15B, Half Bridge N-Channel Power MOSFET Driver ..................................................................................... '920B 4-102
LT1160/LT1162, Half-/Ful/-Bridge N-Channel Power MOSFET Drivers ...................................................... 13-3
LTll6l, Quad Protected High-Side MOSFET Driver .......................................................................................... '940B 4-175
LTCl163/L TCl165, Triple 1.BV to 6V High-Side MOSFET Drivers ..................................................................... '940B 4-186
LTC1177-5/LTC1177-12, Isolated MOSFET Drivers ............................................................................ 13-16
LT124l-45, High Speed Current Mode Pulse Width Modulators ....................................................................... '920B 4-122
ote: All products in BOLD are in this Databook, others appear in LTC's 1990, 1992 and 1994 Databooks (,90D8 = LTC's 1990 Databook, '92D8 = LTC's 1992 Databook Supplement
nd '94D8 = LTC's 1994 Databook).

11

TABLE OF CONTENTS
LT1246/LT1247, 1MHz Off-Line Current Mode PWM ..••....••......•....••• ,.••.••......• ; .....•.•...•. , .•• :.,•...•...••..••.• 4-126
LT1248, Power Factor Controller ...................................;........................................................;.......................... '940B 4-194
LT1249, Power Factor Controller ................................:........................................................................................ '940B 4-205
LTCI2SS. Dual24V High-Side MOSFET Driver ,................................................................................................. '940B 4-215
LTt432, SVHigh EfficiencyStep-Down Switching Regulator Controller ............................................................ ·920B 4-145
LT1432-3.3, 3.3V High Efficiency Step-Down Switching Regulator Controller ..•••.......•.....•....•..•......•......... 4-137
LTC1477/LTC1478, Single and Dual Protected High-Side Switches .•....••......••.....•..••....••.....•.•..•...•.•..... 13-112
POWER AND MOTOR CONTROL, ENHANCED AND SECOND SOURCE
SG1524/SG3524. Reguiating Pulse Width Modulators ...................................................................................... '900B 5-85
SG3524S. Regulating Pulse Width Modulator ...... ;............................................................................................ '900B 5-93
LTt524/LT3524, Regulating Pulse Width Modulators ..................................................................,.................... ·900B 5-85
SG1525A1SG3525A. Regulating Pulse Width Modulators .................................................................................. ·900B 5-97
LTt52SAlLT3S2SA, Regulating Pulse Width Modulators ...................................................................................'900B 5-97
LTt526/LT3S26, Regulating Pulse Width Modulators ....................................................................................... ·900B 5-105
SG1527A1SG3527A. Regulating Pulse Width Modulators .................................................................................. '900B 5-97
LTtS21A1LT3S21A, Regulating Pulse Width Modulators ...................................................................................'900B 5-97
LTt846/LTt841, Current Mode PWM Controller ...............................................................................................'900B 5-113
LT3846/L T3841, Current Mode PWM Controller ...............................................................................................'900B 5-113
SWITCHING REGULATORS .......................................................................................................... 4-145
LTtOl0, SA High Efficiency Switching Regulator ........................................,...................................................... '900B 5-37
LTl0l1, 2.5A High Efficiency Switching Regulator ............................................................................................ '900B 5-37
LTt 012, 1.2SA High Efficiency Switching Regulator ..........................................................................................'940B 4-232
LTt 013, Micropower DC-DC Converter Adjustable and Fixed 5V, 12V............................................................... '920B 4-174
LTt 014/L Tt 016, Step-Down Switching Regulator ............................................................................................. '940B 4-243
LTt016-S, SV Step-Down Switching Regulator .................................................................................................'920B 4-208
LT1082, lA High Voltage, High Efficiency Switching Voltage Regulator ............................................................ '940B 4-257
LTtl 03/L Ttl as, Offline Switching Regulator '940B .......................................................................................... '940B 4-267
LT1106, Micropower Step-Up DC/DC Converter for PCMCIA Card Flash Memory ........................................ 4-146
LT1107, Micropower DC/DC Converter Adjustable and Fixed Sv, 12V............................................................... '940B 4-294
LTtl 08, Micropower DC/DC Converter Adjustable and Fixed Sv, 12V............................................................... '940B 4-306
LTtl09, Micropower Low Cost DC/DC Converter Adjustable and Fixed Sv, 12V............................................... '940B 4-318
LTtl 09A, Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed Sv, 12V ............. '940B 4-325
LTtll 0, Micropower DC-DC Converter Adjustable and Fixed Sv, 12V, High Frequency .................................... '920B 4-245
LTtl11, Micropower DC/DC Converter Adjustable and Fixed Sv, 12V............................................................... '940B 4-331
LTtlll, Micropower DC-to-DC Converter Adjustable and Fixed Sv, 12V, High Frequency ................................ '920B 4-260
LTCI1421L TCI142-ADJ, Dual High Efficiency Synchronous Step-Down Switching Regulators ........................ '940B 4-346
LTC1143, Dual High Efficiency Step-Down Switching Regulator Controller....................................................... '940B 4-365
LTCI141-3.3/LTCI141-S, High Efficiency Step-Down Switching Regulator Controllers .................................... '940B 4-380
LTCI148/LTC1148-3.3/LTC1148-S, High Efficiency Synchronous Step-Down Switching Regulators ............... '940B 4-395
LTC1149/LTC1149-3.3/LTC1149-S, High Efficiency Synchronous Step-Down Switching Regulators ............... '940B 4-414
LTC1159/LTC1159-3.3/LTC1159-5, High Efficiency Synchronous Step-Down Switching Regulators .................. 4-154
LTtll0/LTtll1/LTtI12, 100kHz, SA, 2.SA, and 1.2SA High Efficiency Switching Regulators .......................... ·940B 4-433
LTt113, Micropower DC-DC Converter Adjustable and Fixed Sv, 12V............................................................... '920B 4-275
LTC1114/L TCI114-3.3/L TCII14-S, High Efficiency Step-Down and Inverting DC/DC Converter ...................... '940B . 4-447

Note: All products In BOLD are in this Oatabook, others appear in LTC's 1990, 1992 and 1994 Oatabooks ('9008 = LTC's 1990 Oatabook, '9208 = LTC's 1992 Oatabook Supplement
and '9408 = LTC's 1994 Oatabook).

12

TABLE OF CONTENTS
LTt176/L Tt176-S, Step-Down Switching Regulator ......................................................................................... '94DB 4-462
LT1182/LTt183/LT1184/LT1184F, CCFL/LCD Contrast Switching Regulators ............................................. 4-172
LT1186, DAC Programmable CCFL Switching Regulator (Bits-to-Nits™) .................................................. 4-196
LTC1265/LTC1265-3.3/LTC1265-5, 1.2A, High Efficiency Step-Down DC/DC Converters ................................ 4-212
LTC1266/L TC1266-3.3/L TC1266-5, Synchronous Regulator Controllers for N- or P-Channel MOSFETs .............. 4-228
LTC1267/LTC1267-ADJ/LTC1267-AOJ5, Dual High Efficiency Synchronous Step-Down Switching Regulators ...... 4-248
LTt2688/L Tt268, 7.SA, 1S0kHz Switching Regulators ..................................................................................... '94DB 4-466
LTt270/L Tt270A, 8A and 10A High Efficiency Switching Regulators ................................................................ '94DB 4-470
LTt271/L Tt269, 4A High Efficiency Switching Regulators ................................................................................ '94DB 4-474
LTt300, Micropower High Efficiency 3.3/SV Step-Up DC/DC Converter ............................................................ '94DB 4-478
LTt301, Micropower High Efficiency Sv/12V Step-Up DC/DC Converter with Flash Memory ............................ '94DB 4-486
LT1302/L T1302-5, Micropower High Output Current Step-Up Adjustable and Fixed 5V DC/DC Converters ........... 4-264
LT1303/LT1303-5, Micropower High Efficiency DC/DC Converters with Low-Battery Detector
Adjustable and Fixed 5V ........................................................................................................... 4-279
LT1304/LTt304-3.3/LT1304-5, Micropower DC/DC Converters with Low-Battery Detector Active in Shutdown ..... 13-37
LT1305, Micropower High Power DC/DC Converter with Low-Battery Detector ........................................... 4-290
LT1309, 500kHz Micropower DC/DC Converter for Flash Memory .......................................................... 13-41
LT1371, 500kHz High Efficiency 3A Switching Regulator ... ................................................................. 4-298
LT1372/LTt377, 500kHz and 1MHz High Efficiency 1.5A Switching Regulators .......................................... 4-310
LT1373, 250kHz Low Supply Current High EUiciency 1.5A Switching Regulator .......................................... 4-322
LT1375/LTt376, 1.5A, 500kHz Step-Down Switching Regulators ........................................................... 4-334
LTC1430, High Power Step-Down Switching Regulator Controller .......................................................... 4-360
LT1572, 100kHz, 1.25A Switching Regulator with Catch Diode ............................................................. 4-374
LTC1574/LTC1574-3.3/LTC1574-5, High Efficiency Step-Down DC/DC Converters with Internal Schottky Diode ... 4-385
PCMCIA HOST AND CARD POWER MANAGEMENT DEViCES .................................................................... 4-393
LT1106, Micropower Step-Up DC/DC Converter for PCMCIA Card Flash Memory ........................................ 4-146
LTC1262, 12V, 30mA Flash Memory Programming Supply ................................................................... 4-34
LT13l2, Single PCMCIA VPP Driver/Regulator ................................................................................ 4-394
LT1313, Dual PCMCIA VPP Driver/Regulator ................................................................................... 4-405
LTC1314/LTC1315, PCMCIA Switching Matrix with Built-In N-Channel Vee Switch Drivers ............................. 4-415
LTC1470/LTC1471, Single and Dual PCMCIA Protected 3.3V!5V Vee Switches ........................................... 4-426
LTC1472, Protected PCMCIA Vee and VPP Switching Matrix ................................................................ 4-437
BATTERY MANAGEMENT CIRCUITS ................................................................................................ 4-453
LT1239, Backup Battery Management Circuit .................................................................................. 4-454
LTC1325, Microprocessor-Controlled Battery Management System ........................................................ 4-466
LT1510, Constant-Voltage/Constant-Current Battery Charger ............................................................. 13-120
LT1512, SEPIC Constant-CurrenVConstant-Voltage Battery Charger ............ ,........................................ 13-130

iECTION 5-INTERFACE
INDEX ..•••.•.•...•..••....•.••••••.••••.......•...••.•.....••••••••.....•...........•........•••••.........••••.•....•.••.•••..••••••••..••.• 5-2
SELECTION GUiDES •••..•..•...•..••••............•..•..•.••••••••.........••...•••.......•.••..........••••..•...•..•..••••••...••..•••.•• 5-3
PROPRIETARY PRODUCTS
RS232/562 ..•.•••••••••....•.....••.•..••..........•••••.....••••.•••...........••.•...........•..•......••••••....••••.•.••••..•...•••.••• 5-9
LT1 030, Quad Low Power Line Driver ...............................................................................................................'90DB 10-5
LTt030CS, Quad Low Power Line Driver ........................................................................................................... '90DB 10-9
Jle: All products in BOLD are in this oatabook, others appear in LTC's 1990, 1992 and 1994 oatabooks (,90oB = LTC's 1990 oatabook, '92oB = LTC's 1992 oatabook Supplement
Id '94oB = LTC's 1994 oatabook).

13

TABLE OF CONTENTS
LTt032, Quad Low Power Line Driver ...............................................................................................~ ......... ,..... '90DB 10-11
LTt039, RS232 Driver/Receiver with Shutdown ........................................................................... :........•........... '90DB 10-19
LTt080, Advanced Low Power 5V RS232 Dual Driver/Receiver .: ......................................................;.............. .'90DB 10-43
LTt081, Advanced Low Power5V RS232 Dual Driver/Receiver ........................................................................ '90DB 10-43
LTt 080CS/L T1 081 CS, 5V Powered RS232 Driver/Receiver with Shutdown ...................................................... '90DB 10-51
LT1130A; Advanced 5-Driver/5-Receiver RS232 Transceiver .................................................:: ......................... '94DB 5-10
LT1131A, Advanced 5-Driver/4-Receiver RS232 Transceiver with Shutdown .................................................. .'94DB 5-10
LTt132A, Advanced 5-Driver/3-Receiver RS232 Transceiver ............................................................................ '94DB 5-10
LTt133A, Advanced 3-Driver/5-Receiver RS232 Transceiver ............................................................................ '94DB 5-10
LTt134A, Advanced 4-Driver/4-Receiver RS232 Transceiver ............................................................................ '94DB 5-10
LT1135A, Advanced 5-Driver/3-Receiver RS232 Transceiver without Charge Pump ......................................... '94DB 5-10
LTt136A, Advanced 4-Driver/5-Receiver RS232 Transceiver with Shutdown ;.................................................. '94DB 5-10
LT1137A, Advanced Low Power 5V RS232 Transceiver with Small Capacitors .................................................'94DB 5-20
LT1138A, Advanced 5-Driver/3-Receiver RS232 Transceiver with Shutdown .................................................. .'94DB 5-10
LTt139A, Advanced 4-Driver/4-Receiver RS232 Transceiver with Shutdown ................................................... '94DB 5-10
LT1140A, Advanced 5-Driver/3-Receiver RS232 Transceiver without Charge Pump ......................................... '94DB 5-10
LTt141A, Advanced 3-Driver/5-Receiver RS232 Transceiver without Charge Pump .................................:....... '94DB 5-10
LT1180A, Low Power 5V RS232 Dual Driver/Receiver with 0.11JF Capacitors ........... ;............. :......................... '94DB 5-27
LTt181A, Low Power 5V RS232 Dual Driver/Receiver with 0.11JF Capacitors ...................................................'94DB 5-27
LTt237, 5V RS232 Transceiver with Advanced Power Management and One Receiver Active in SHUTDOWN. '94DB 5-34
LT1280A, Low Power 5V RS232 Dual Driver/Receivefwith 0.11JF Capacitors ................................................... '94DB 5-41
LT1281A, Low Power 5V RS232 Dual Driver/Receiver with 0.11JF Capacitors ...................................................'94DB 5-41
LTC1327, 3.3VMicropowerElAITIA-562 Transceiver ........................................................................................ '94DB· 5-48
LT1330, 5V RS232 Transceiver with 3V Logic Interface and One Receiver Active in SHUTDOWN .................... '94DB 5-54
LT1331, 3V RS232 or 5V/3V RS232 Transceiver with One Receiver Active in SHUTDOWN ...................... :.: ..... '94DB 5-61
LT1332, Wide Supply Range Low Power RS232 Transceiver with 12V VPP Output for Flash Memory ............. '94DB 5-68
LTC1337, 5V Low Power RS232 3-Driver/5-Receiver Transceiver ...................................... :............................. '94DB 5-76
LTC1338, 5V Low Power RS232 5-Driver/3-Receiver Transceiver .................................................................... '94DB 5-82
LT1341, 5V RS232 Transceiver with One Receiver Active in SHUTDOWN ........................................................ .'94DB 5-88
LT1342, 5V RS232 Transceiver with 3V Logic Interface .................................................................................... '94DB 5-95
LTC1347, 5V Low Power RS232 3-Driver/5-Receiver Transceiver with 5 Receivers Active in SHUTDOWN ...... '94DB 5-102
LTC1348, 3.3V Low Power RS232 3-0river!5-Receiver Transceiver ......................................................... 5-10
LTC1349, 5V Low Power RS232 3-Driver/5-Receiver Transceiver with 2 Receivers Active in SHUTDOWN ...... '94DB 5-108
LTC1350, 3.3V LowPower EIAlTIA-562 3-Driver/5-Receiver Transceiver ......................................................... '94DB 5-114
LTt381, Low Power 5V RS232 Dual Driver/Receiver with 0.11JF Capacitors ..... :: .............................................. '94DB 5c120
LTC1382, 5V Low Power RS232 Transceiver with Shutdown ............................................................................ '94DB 5-127
LTC1383, 5V Low Power RS232 Transceiver ......................................................................c............................. '94DB 5-133
LTC1384, 5VLow Power RS232 Transceiver with 2 Receivers Active in SHUTDOWN ...................................... '94DB 5-139
LTC1385, 3.3V Low Power ElAlTIA-562 Transceiver ......................................................................................... '94DB 5-145
LTC1386, 3.3V Low Power ElAlTIA-562 Transceiver ........ ., ............................................................................... '94DB 5-151
LT1537, Advanced Low Power 5V RS232 Transceiver with Small Capacitors .............................................. 5-18
RS485 ............................................................................................, ............ ............................ 5-25
LTC485, Low Power RS485 Interface Transceiver ............................................................................................ '92DB
5-6
LTC486, Quad Low Power RS485 Driver .....................................................................................c..................... '92DB 5-16
L TC487, Quad Low Power RS485 Driver .......................................................................................................... '92DB 5-24
Note: All products in BOLO. are in this Databook, others appear in LTC's 1990, 1992 and 1994 Databooks ('90DB= LTC's 1990 Databook, '92DB = LTC's 1992 Databook Supplement
and '94DB = LTC's 1994 Databook).

14

TABLE OF CONTENTS
LTC488/L TC489, Quad RS485 Line Receiver ..................................................................................................... '94DB 5-158
LTC490, Low Power RS485 Interface Transceiver ............................................................................................ '92DB 5-32
LTC491, Low Power RS485 Interface Transceiver ............................................................................................ '92DB 5-40
LTC1480, 3.3V Ultra-Low Power RS485 Transceiver .......................................................................... 5-26
LTC1481, Ultra-Low Power RS485 Transceiver with Shutdown .............................................................. 5-34
LTC1483, Ultra-Low Power RS485 Low EMI Transceiver with Shutdown ................................................... 5-41
LTC1485, Differential Bus Transceiver ............................................................................................................... '94DB 5-166
LTC1487, Ultra-Low Power RS485 with Low EMI, Shutdown and High Input Impedance ................................ 5-49
V.35 ....................................................................................................................................... 5-57
LTC1345, Single Supply V.35 Transceiver ........................................................................................5-58
LTC1346, 10Mbps oCE/DTE V.35 Transceiver ................................................................................. 13-65
AppleTalk® ............................................................................................................................... 5-69
LTC1318, Single 5V RS232/RS422/AppleTa/~ Transceiver .................................................................. 5-70
LTC1320, AppleTalifiY Transceiver .....................................................................................................................'94DB 5-178
LTC1323, Single 5VAppleTa/~ Transceiver .................................................................................... 5-77
LTC1324, Single Supply LocalTa/~ Transceiver ............................................................................. 13-45
LT1389, AppleTa/~ Peripheral Interface Transceiver ....................................................................... 13-73
INFRARED ................ ................................................................................................................ 5-89
LT1319, Multiple Modulation Standard Infrared Receiver .................................................................... 5-90
DIGITAL ISOLATORS
LTC1145IL TC1146, Low Power Digital Isolator ................................................................................................. '94DB 5-186
MIXED PROTOCOL .................................................................................................................... 5-101
LTC1321/L TC1322/L TC1335, RS2321E1A5621RS485 Transceivers .................................................................... '94DB 5-198
LTC1334, Single 5V RS232/RS485 Multi-Protocol Transceiver ............................................................. 13-53
LEVEL TRANSLATOR
LTC1045, Programmable Micropower Hex Level Translator/Receiver/Driver .................................................... '90DB 10-27

SECTION 6-DATA CONVERSION
INDEX ........................................................................................................................................ 6-2
SELECTION GUIDES ........................................................................................................................ 6·3
PROPRIETARY PRODUCTS
ANALOG·TO·DIGITAL CONVERTERS ................................................................................................... 6·7
LTC1 090, Single Chip 10-Bit Data Acquisition System ...................................................................................... '90DB
9-5
LTC1 091, 1-Channel, 10-Bit Serial I/O Data Acquisition System ........................................................................ '90DB 9-29
LTC1092,2-Channel, 10-Bit Serial I/O Data Acquisition System ........................................................................ '90DB 9-29
LTC1093,6-Channel, 10-Bit Serial I/O Data Acquisition System ........................................................................ '90DB 9-29
LTC1094, 8·Channel, 10-Bit Serial I/O Data Acquisition System ........................................................................ '90DB 9-29
LTC1095, Complete 10-Bit Data Acquisition System with On Board Reference ................................................. '90DB 9-57
LTC1096/LTC1098, Micropower Sampling 8-Bit Serial I/O AID Converters ....................................................... '94DB
6-8
LTC1099, High Speed 8-Bit AID Converter with Built-In Sample-and-Hold ........................................................ '90DB 9-81
LTC1196/LTC1198, 8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options ................................................... '94DB 6-32
LTC1272, 12-Bit, 3f.ls, 250kHz Sampling AID Converter ................................................................................... '92DB
6-6
LTC1273/L TC1275/L TC1276, 12-Bit, 300ksps Sampling AID Converters with Reference ................................. '94DB 6-58
LTC1274/L TC1277, 12·8it, 10mW, 100ksps AoCs with 11lA Shutdown .. ................................................... 13·22
LTC1278, 12-Bit, 500ksps Samplng AID Converter with Shutdown .................................................................. '94DB 6-80
~ote: All products in BOLD are in this Oatabook, others appear in LTC's t990, 1992 and 1994 Oatabooks ('9008 =LTC's 1990 Oatabook, '9208 =LTC's 1992 Oatabook Supplement
md '9408 = LTC's 1994 Oatabook).

15

TABLE OF CONTENTS
LTC1279, 12-8it, 600ksps Sampling AID Converter with Shutdown ........................................................... 6-8
LTC1282, 3V 140ksps 12-Bit Sampling AID Converter with Reference .............................................................. '9408 6-95
LTC1283, 3V Single Chip la-Bit Data Acquisition System .............................................................. ;..... ;............ '9408 6-117
LTC1285/L TC1288, 3V Micropower Sampling 12-8it AID Converters in SO-8 Packages .................................. 6-24
LTC12861LTC1298, Micropower Sampling 12-Bit AID Converters in SO-8 Packages ........................................ '9408 6-140
LTC1287, 3V Single Chip 12-Bit Data Acquisition System ................................................................................ '9208 6-25
LTC1289, 3V Single Chip 12-Bit Data Acquisition System ................................................................................ '9208 6-40
LTC1290, Single Chip 12-Bit Data Acquisition System ..................................................................................... '9208 6-67
LTC1291, Single Chip 12-Bit Data Acquisition System ...................................................................................... '9408 6-163
LTC12921L TC1297, Single Chip 12-Bit Data Acquisition Systems ..................................................................... '9408 6-182
LTC12931L TC12941L TC1296, Single Chip 12-Bit Data Acquisition System ....................................................... '9208 6-113
LTC1392, Micropower Temperature, Power Supply and Differential Voltage Monitor ................................... 13-77
LTC1400, Complete SO-8, 12-8it, 400ksps AID Converter with Shutdown ................................................. 13-86
LTC1410, 12-8it, 1.25Msps Sampling AID qonverter with Shutdown ...................................................... 13-97
LTC1522, 4-Channel, 3V Micropower Sampling 12-8it Serial 110 AID Converter ....................................... 13-134
ANALOG-TO-DIGITAL CONVERTERS, ENHANCED AND SECOND SOURCE
LT574A, Complete 12-8it AID Converter .......................................................................................... 6-48
DIGITAL-TO-ANALOG CONVERTERS .................................................................................................. 6-57
LTC1257, Complete Single Supply 12-Bit Voltage Output DAC in SO-8 ............................................................. '9408 6-210
LTCI451/LTCI452/LTCI453, 12-8it Rai/-to-Rai/ Micropower DACs in SO-8 ............................................... 6-58
DlGITAL-TO-ANALOG CONVERTERS, ENHANCED AND SECOND SOURCE
LTC7541A, Improved Industry Standard CMOS 12-8it Multiplying DAC ..................................................... 6-69
LTC7543/L TC8143, Improved Industry Standard Serial 12-Bit Multiplying OACs .......................................... 6-73
LTC8043, Serial 12-8it Multiplying DAC in SO-8 ............................................................................... 6-80
MULTIPLEXERS .......................................................................................................................... 6-85
LTC1390, 8-Channel Analog Multiplexer with Seriallnlerface ............................................................... 6-86
SECOND SOURCE PRODUCTS (SAMPLE/HOLD CIRCUITS)
LF198A1LF398A, Precision Sample and Hold Amplifier ..................................................................................... '9008 9-97
LF198/LF398, Precision Sample and Hold Amplifier ........................................................................................... '9008 9-97
LF398S8, Precision Sample and Hold Amplifier ................................................................................................. '9008 9-113

SECTION 7-VOLTAGE REFERENCES
INDEX ........................................................................................................................................ 7-2
SELECTION GUiDES ....... ................................................................................................................. 7-3
PROPRIETARY PRODUCTS
LTZ1000, Ultra Precision Reference .................................................................................................................. '9008
3-9
LTZ1000A, Ultra Precision Reference ................................................................................................................ '9008
3-9
LT1 004, Micropower Voltage Reference ............................................................................................................'9008 3-17
LT1 004CS8-1.2IL T1 004CS8-2.5, Micropower Voltage References ................................................................... '9008 3-25
LT1 009 Series, 2.5 Volt Reference .....................................................................................................................'9008 3-27
LT1 00958, 2.5 Volt Reference ........................................................................................................................... '9008 3-31
LTl019, 2.5V, 4.5V, 5.0V, 10.0V, Precision References ....................................................................................'9008 3-33

Note: All products in BOLD are in this Databook. others appear in LTC's 1990, 1992 and 1994 Databooks (,90DB = LTC's 1990 Databook, '92DB = LTC's 1992 Databook Supplement
and '94DB = LTC's 1994 Databook).

16

TABLE OF CONTENTS
LTl021, 5.0V, 7.0V, 10.0V, Precision References ............................................................................................. '90DB 3-41
LTt 021 DCS8, 5.0V, 7.0V, to.OV, Precision References ..................................................................................... '90DB 3-57
LTt 027, Precision 5V Reference ........................................................................................................................ '92DB
7-6
LTt029, 5V Bandgap Reference ......................................................................................................................... '90DB 3-61
LTt 031, Precision 1OV Reference ...................................................................................................................... '90DB 3-65
LTt 034-1.2IL T1 034-2.5, Micropower Dual Reference ....................................................................................... '94DB
7-5
LT1236, Precision Reference ........................................................................................................ 7-5
LTt431, Programmable Reference .................................................................................................................... '92DB 7-13
SECOND SOURCE PRODUCTS
LH0070, Precision 10V Reference ..................................................................................................................... '90DB 3-65
LM129/LM329, 6.9V Precision Voltage Reference ............................................................................................. '90DB 3-83
LM134 Series, Constant Current Source and Temperature Sensor .................................................................... '90DB 3-87
LM334S8, Constant Current Source and Temperature Sensor .......................................................................... '90DB 3-99
LM136-2.5/LM336-2.5, 2.5 Volt Reference ....................................................................................................... '90DB 3-101
LM185-1.2/LM385-1.2, Micropower Voltage Reference .................................................................................... '90DB 3-105
LM185-2.5/LM385-2.5, Micropower Voltage Reference .................................................................................... '90DB 3-109
LM385S8-1.2/LM385S8-2.5, Micropower Voltage Reference ........................................................................... '90DB 3-113
LM199/LM399/LM199A1LM399A, Precision Reference ..................................................................................... '90DB 3-115
LT580, Precision Reference ............................................................................................................................... '90DB 3-121
LT581, Precision Reference ............................................................................................................................... '90DB 3-121
REF-01/REF-02, Precision Voltage References .................................................................................................. '90DB 3-125

SECTION 8-MONOLITHIC FILTERS
INDEX ........................................................................................................................................ 8-2
SELECTION GUIDES ........................................................................................................................ 8-3
PROPRIETARY PRODUCTS
LTCI 059, High Peformance Switched CapaCitor Universal Filter ....................................................................... '90DB
7-3
LTCI 059CS, High Performance Switched Capacitor Universal Filter ................................................................. '90DB 7-11
LTCto60, Universal Dual Filter Building Block ................................................................................................... '90DB 7-15
LTC1060CS, Universal Dual Filter Building Block ............................................................................................... '90DB 7-35
LTC1061, High Performance Triple Universal Filter Building Block .................................................................... '90DB 7-39
LTC1061CS, High Performance Triple Universal Filter Building Block ............................................................... '90DB 7-55
LTCto62, 5th Order Lowpass Filter ................................................................................................................... '94DB
8-5
LTCI 063, DC Accurate, Clock-Tunable 5th Order Butterworth Lowpass Filter ................................................... '94DB 8-16
LTCto64, Low Noise, Fast, Quad Universal Filter Building Block ....................................................................... '90DB 7-73
LTC1064-1, Low Noise, 8th Order, Clock Sweepable Elliptic Lowpass Filter ..................................................... '90DB 7-89
LTCI 064-2, Low Noise, High Frequency, 8th Order Butterworth Lowpass Filter ............................................... '92DB
8-5
LTC1064-3, Low Noise, High Frequency, 8th Order Linear Phase Lowpass Filter ............................................. .'92DB 8-13
LTC1064-4, Low Noise, 8th Order, Clock Sweepable Cauer Lowpass Filter ....................................................... '92DB 8-21
LTC1064-l, Linear Phase, 8th Order Lowpass Filter .......................................................................................... '94DB 8-28
LTC1065, DC Accurate, Clock-Tunable Linear Phase 5th Order Bessel Lowpass Filter ...................................... '94DB 8-39
LTCI 066-1, 14-Bit DC Accurate Clock-Tunable, 8th Order Elliptic or Linear Phase Lowpass Filter ................... '94DB 8-51
LTC1164, Low Power, Low Noise, Quad Universal Filter Building Block ............................................................ '92DB 8-29
LTCI164-5, Low Power 8th Order Pin Selectable Butterworth or Bessel Lowpass Filter ................................... '94DB 8-67
LTCI164-6, Low Power 8th Order Pin Selectable Elliptic or Linear Phase Lowpass Filter ................................. '94DB 8-78
ote: All products in BOLD are in this Databook, others appear in LTC's 1990,1992 and 1994 Databooks (,90DB =LTC's 1990 Databook. '92DB =LTC's 1992 Databook Supplement
1d '94DB = LTC's 1994 Databook).

L7lJO~

17

TABLE OF CONTENTS
LTC1164-7, Low Power, Linear Phase 8th Order Lowpass Filter .........................................;............................. '940B 8-89
LTC1164-8, Ultra-Selective, Low Power 8th Order Elliptic Bandpass Filtsr with Adjustable Gain •••••••••••••••••••••••• 8-5
LTC1264, High Speed, Quad Universal Filter Building Block .............................................................................. '940B 8-100
LTC1264-7, Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter .................................................... '940B 8-115

SECTION 9-MICROPROCESSOR SUPERVISORY CIRCUITS
INDEX •••••.•..••.••..•.•••••••.••..••••.•.•••••.•••...•••••••••.•••••.••.•...••••••.••..•••••.• ; ••.••••..•.•••.••.••••..••••.•••••...•.•••.•• 9-2
SELECTION GUIDE ••••...•..••..•••..•••.•••••••..••••••....•••••..••.•••••••••••••.••••..•••.•••••.•••••.••.••....••••..••••..•••...••••.• 9-3
PROPRIETARY PRODUCTS
LTC690lL TC6911LTC6941LTC695, Microprocessor Supervisory Circuits ......................................................... '920B
9-4
LTC6921L TC693, Microprocessor Supervisory Circuits ..................................................................................... '940B
9-4
LTC694-3.3ILTC695-3.3, 3.3V Microprocessor Supervisory Circuits ................................................................ '940B 9-19
LTC699, Microprocessor Supervisory Circuit ................................................................................................... '920B 9-18
LTC1232, Microprocessor Supervisory Circuit ................................................................................................. '920B 9-22
LTC1235, Microprocessor Supervisory Circuit with Conditional Battery Backup .............................................. '920B 9-29

SECTION 10-COMPARATORS
INDEX •••••..•••••....•••...•..••.•.•••••••.••.•.••.•••••..•••••••...••.•••••.••..•••.•••.••••.••••..•••....•••..•.•••••..••..•.••••..••..•.• 10-2
SELECTION GUIDE ••.•.•.••••.•••..•••..•••••.•••••..••••••••.•••••.•••........... ; •..•..........•.....••..•.•••.•..•••..•••••••.••••••.•• 10-3
PROPRIETARY PRODUCTS
LTt011, Voltage Comparator ............................................................................................................................. '900B
6-9
LTt015, High Speed Dual Line Receiver .....................................................................•...................................... '920B 10-4
LTt016, Ultra Fast Precision Comparator .......................................................................................................... '900B 6-25
LT1 016CS8,. Ultra Fast Precision Comparator.................................................................................................... '900B 6-41
LT1 0171L Tt 018, Micropower Dual Comparator .......................................................................•......................... '940B 10-4
LTC1040, Dual MicropowerComparator ...........................................................................................................'900B 6-57
LTC1041, BANG-BANG Controller...................................................................................................................... '900B 6-69
LTC1042, Window Comparator............................................................. ,............................................................ '900B 6-77
LTt116, 12ns, Single Supply Ground-Sensing Comparator .............................................................................. '920B 10-7
LTC1443/LTC1444/LTC1445, Low Power Quad Comparators .............................................................. 13-108
ENHANCED AND SECOND SOURCE PRODUCTS
LM111/LM311, Voltage Comparator ..................................................................................................................'900B 6-85
LTt11A1LT311A, Improved LM111 ..................................................................................................;................. '900B 6-85
LM119/LM319, Oual Comparator ...................................................................................................................... '900B 6-93
LTt19A1LT319A, ImprovedLM119 .................................................................................................................... '900B 6-93
LT685, High Speed Comparator ......................................................................................................................... '900B
6-5

SECTION 11-8PECIAL FUNCTIONS
INDEX •••.•..•••••...••••...•••••••••••••..•••••..••...••••....•••••..••.•••••••.•.•••.••.•.••..••.....•...........•............•..•..••..••. 11-2
SELECTION GUIDE ........................................................................................................................ 11-3
PROPRIETARY PRODUCTS
LTK001, Thermocouple Cold Junction Compensator and Matched Amplifier .................................................... '900B 11-3
LTC201AIL TC202lL TC203, Micropower, Low Charge Injection, Quad CMOS Analog Switches ......................... '920B 11-4
LTC2211L TC222, Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches ........... '920B 11-15
LT1025, Micropower Thermocouple Cold Junction Compensator ..................................................................... '900B 11-7
Note: All products in BOLD are in this Oatabook, others appear in LTC's 1990, 1992 and 1994 Oatabooks (,900B = LTC's 1990 Oatabook, '920B = LTC's 1992 Oatabook Supplement
and '940B =LTC's 1994 Oatabook).

18

TABLE OF CONTENTS
LTC1043, Dual Precision Instrumentation Switched Capacitor Building Block .................................................. '90oB 11-15
LTC1043CS, Dual Precision Instrumentation Switched Capacitor Building Block .............................................. '90oB 11-31
LT1 088, Wideband RMS-DC Converter Building Block ...................................................................................... '90oB 11-33

SECTION l2-MILITARY PRODUCTS
INDEX ..................•••..••••............••..•.•.••••••.........••••••.••••......•.......•••..••...............••••...•...............••• 12-2
MILITARY PRODUCTS/PROGRAMS ..................................................................................................... 12-3
JAN ..............•...•....................•....•.......•...........•••....................••......................................•..••.. 12-3
MIL·M-38510 Class B Flow (Figure 1) ..........................................................................................12-4
MIL·M-38510 Class S Flow (Figure 2) ..........................................................................................12-5
Standard Military Drawings ..........................................................................................................12-4
SMD Preparation Flowchart (Figure 3) .........................................................................................12-6
SMDs Get a New Part Numbering System .........................................................................................12-6
MIL·STD·883 Product .................•......................••....•••....•..........•...................••.......................•... 12-7
883 Group A Sampling Plan (Table 1) .......................................................................................... 12-7
Hi·Rel (SCDs) .......................................................................................................................... 12-7
Radiation Hardness Program ..........••..•....•...............••....................••...................•.....................•... 12-7
Representative "RH" Product Manufacturing Flow (Figure 4) ............................................................. 12-8
Military Market Commitment ........................................................................................................ 12-7
883 Certificate of Conformance ..................................................................................................... 12-9
MIL·STD-883 Test Methods ........................................................................................................ 12-10
Military Parts List ................................................................................................................... 12-14

SECTION l3-NEW PRODUCTS
INDEX ...••......•.............................••..•.•...............•..•••..•••.•..........••••.............•.•...•.•..................••... 13-2
PROPRIETARY PRODUCTS
LT1160/LT1162, Half·/Fu/l-Bridge N·Channel Power MOSFET Drivers ...................................................... 13-3
LTC1177-5/LT1177-12, Isolated MOSFET Drivers ............................................................................. 13-16
LT1186, DAC Programmable CCFL Switching Regulator (Bits·to·Nits™) .................................................. 4-196
LT1236, Precision Reference ........................................................................................................ 7-5
LT1239, Backup Battery Management Circuit .................................................................................. 4-454
LTC1274/LTC1277, 12-Bit, 10mW, 100ksps AID Converters with 1pA Shutdown ......................................... 13-22
LT1304/LT1304-3.3/LT1304-5, Micropower DCIDC Converters with Low·Battery Detector Active in Shutdown ..... 13-37
LT1309, 500kHz Micropower DCIDC Converter for Flash Memory .......................................................... 13-41
LT1311, Quad 12MHz, 145ns Settling Precision Current·to·Voltage Converter for Optical Disk Drives ................ 2-34
LTC1324, Single Supply LocalTaltllP Transceiver ............................................................................. 13-45
LTC1334, Single 5V RS232/RS485 Multi·Protocol Transceiver ............................................................. 13-53
LTC1346, 10Mbps DCE/DTE V.35 Transceiver ................................................................................. 13-65
LT1373, 250kHz Low Supply Current High Efficiency 1.5A Switching Regulator .......................................... 4-322
LT1375/LT1376, 1.5A, 500kHz Step·Down Switching Regulators ........................................................... 4-334
LT1389, AppleTaltllP Peripheral Interface Transceiver ....................................................................... 13-73
LTC1392, Micropower Temperature, Power Supply and DiUerential Voltage Monitor ................................... 13-77
LTC1400, Complete SO-8, 12-Bit, 400ksps AID Converter with Shutdown ................................................. 13-86
LTC1410, 12-Bit, 1.25Msps Sampling AID Converter with Shutdown ...................................................... 13-97
LTC1429, Clock·Synchronized Switched Capacitor·Regulated Voltage Inverter ........................................... 4-41
Ole: All products in BDLD are in this Databook, others appear in LTC's 1990, 1992 and 1994 Databooks (,90DB; LTC's 1990 Databook, '92DB; LTC's 1992 Databook Supplement
nd '94DB; LTC's 1994 Databook).

L7lJ!J~

19

TABLE OF CONTENTS
LTC1430, High Power Step-Down Switching Regulator Control/er .......................................................... 4-360
LTC1443/LTC1444/LTC1445, Low Power Quad Comparators .............................................................. 13-108
LTC1477/LTC1478, Single and Dual Protected High-Side Switches ...................................................... 13-112
LT1510, Constant- Voltage/Constant-Current Battery Charger ......................................•.................•.•.. 13-120
LT1512, SEPIC Constant-Current/Constant-Voltage Battery Charger ......•............................................•• 13-130
LT1521/LT1521-3/LT1521-3.3/LT1521-5, 300mA Low Dropout Regulators with Micropower
Quiescent Current and Shutdown .........................................................................................•........ 4-79
LTC1522, 4-Channel, 3V Micropower Sampling 12-Bit Serial//O AID Converter ....................................... 13-134
LT1528, 3A Low Dropout Regulator for Microprocessor Applications ....................................................... 4-91
LT1529/LT1529-3.3/LT1529-5, 3A Low Dropout Regulators with Micropower Quiescent Current and Shutdown ... 4-101
LTC1550/LTC1551, Low Noise, Switched Capacitor-Regulated Voltage Inverters ..................................... 13-142
LT1572, 100kHz, 1.25A Switching Regulator with Catch Diode ............•................................................ 4-374
LT1580/LT1580-2.5, 7A, Very Low Dropout Regulator ...................................................................... 13-148

SECTION 14-PACKAGE INFORMATION
INDEX ....................................................................................................................................... 14-2
PACKAGE CROSS REFERENCE .......................................................................................................... 14-3
PACKAGE DIMENSIONS .................................................................................................................. 14-5
SURFACE MOUNT PRODUCTS ........................................................................................................ 14-36
TAPE AND REEL ......................................................................................................................... 14-47
TO-220 LEAD BEND OPTIONS ......................................................................................................... 14-54

SECTION 15-APPENDICES
INDEX ....................................................................................................................................... 15-2
INTRODUCTION TO QUALITY AND RELIABILITY ASSURANCE PROGRAMS ...................................................... 15-3
ISO 9001 QUALITY MANUAL ............................................................................................................. 15-5
RELIABILITY ASSURANCE PROGRAM ........................................................ , ....................................... 15-30
QUALITY ASSURANCE PROGRAM .................................................................................................... 15-46
Waler Fabrication Flowchart ...........................................................•........................................... 15-52
Assembly Flowchart ................................................................................................................. 15-61
Test and End-ol-Line Flowchart ................................................................................................... 15-65
R-FLOW ................................................................................................................................... 15-66
ESD PROTECTION PROGRAM .......................................•..........................•...................................... 15-67
STATISTICAL PROCESS CONTROL ................................................................................................... 15-78
DICE PRODUCTS ........................................................................................................................ 15-81
DESIGN TOOLS ................................................................................................................•......... 15-83
Application Notes .................................................................................. ; ................................. 15-83
Design Notes ......................................................................................................................... 15-87
Applications on Disk ................................................................................................................ 15-90
Technical Publications ............................................................................................................. 15-90

Bits·to·Nits is a trademark of Linear Technology Corporation.
AppleTalk and LocalTalk are registered trademarks of Apple Computer, Inc.
Note: All products in BOLD are in this Databook, others appear in LTC's 1990, 1992 and 1994 Databooks (,90DB =LTC's 1990 Databook, '92DB =LTC's 1992 Databook Supplement
and '94DB = LTC's 1994 Databook).

20

ALPHANUMERIC INDEX
LF155, JFET Input Op Amp, Low Supply Current ..................................................................................................... '9008
LF155A, JFET Input Op Amp, Low Supply Current .................................................................................................. '9008
LF156, JFET Input Op Amp, High Speed .................................................................................................................. '9008
LF156A, JFET Input Op Amp, High Speed ................................................................................................................ '9008
LF198, Precision Sample and Hold Amplifier ........................................................................................................... '9008
LF198A, Precision Sample and Hold Amplifier ...........................................................................•............................. '9008
LF355, JFET Input Op Amp, Low Supply Current ..................................................................................................... '9008
LF355A, JFET Input Op Amp, Low Supply Current .................................................................................................. '9008
LF356, JFET Input Op Amp, High Speed .................................................................................................................. '9008
LF356A, JFET Input Op Amp, High Speed ................................................................................................................ '9008
LF398, Precision Sample and Hold Amplifier ........................................................................................................... '9008
LF398A, Precision Sample and Hold Amplifier .........................................................................................................'9008
LF398S8, Precision Sample and Hold Amplifier ....................................................................................................... '9008
LF412A, Dual Precision JFET Input Op Amp ............................................................................................................ '9008
LH0070, Precision 10V Reference ........................................................................................................................... '9008
LH2108A, Dual LM108 Op Amp ............................................................................................................................... '9008
LM10, Low Power Op Amp and Reference .............................................................................................................. '9008
LM108, Low Power Op Amp and Reference ............................................................................................................'9008
LM108L, Low Power Op Amp and Reference .......................................................................................................... '9008
LM10C, Low Power Op Amp and Reference ............................................................................................................ '9008
LM10CL, Low Power Op Amp and Reference .......................................................................................................... '9008
LM1 01 A, Uncompensated General Purpose Op Amp ............................................................................................... '9008
LM107, Compensated General Purpose Op Amp ..................................................................................................... '9008
LM108, Super Gain Op Amp .................................................................................................................................... '9008
LM108A, Super Gain Op Amp .................................................................................................................................. '9008
LM111, Voltage Comparator .................................................................................................................................... '9008
LM117, Positive Adjustable Regulator ..................................................................................................................... '9008
LM117HV, High Voltage Positive Adjustable Regulator ........................................................................................... '9008
LM118, High Slew Rate Op Amp ............................................................................................................................. '9008
LM119, Dual Comparator ........................................................................................................................................ '9008
LM123, 5 Volt, 3 Amp Regulator ............................................................................................................................. '9008
LM129, 6.9V Precision Voltage Reference ............................................................................................................... '9008
LM134 Series, Constant Current Source and Temperature Sensor .......................................................................... '9008
LM136-2.5, 2.5 Volt Reference ................................................................................................................................ '9008
LM137, Negative Adjustable Regulator .................................................................................................................... '9008
LM137HV, High Voltage Negative Adjustable Regulator .......................................................................................... '9008
LM138, 5 Amp Positive Adjustable Regulator .......................................................................................................... '9008
LM150, 3 Amp Positive Adjustable Regulator .......................................................................................................... '9008
LM185-1.2, Micropower Voltage Reference ............................................................................................................ '9008
LM185-2.5, Micropower Voltage Reference ............................................................................................................ '9008
LM199, Precision Reference .................................................................................................................................... '9008
LM199A, Precision Reference .................................................................................................................................. '9008
LM301 A, Uncompensated General Purpose Op Amp ............................................................................................... '9008
LM307, Compensated General Purpose Op Amp ..................................................................................................... '9008

2-271
2-271
2-271
2-271
9-97
9-97
2-271
2-271
2-271
2-271
9-97
9-97
9-113
2-275
3-65
2-279
2-281
2-281
2-281
2-281
2-281
2-297
2-297
2-303
2-303
6-85
4-137
4-145
2-311
6-93
4-149
3-83
3-87
3-101
4-157
4-165
4-169
4-177
3-105
3-109
3-115
3-115
2-297
2-297

lole: All products in BOLO are in this Databook, others appear in LTC's 1990,1992 and 1994 Databooks ("90DB =LTC's 1990 Databook, '92DB =LTC's 1992 Databook Supplement
nd '94DB = LTC's 1994 Databook).

L7lJ!J~

21

ALPHANUMERIC INDEX
LM308, Super Gain Op Amp .................................................................................................................................... '900B 2~303
LM308A, Super Gain Op Amp .................................................................................................................................. '900B 2-303
LM311, Voltage Comparator ....................................................................................................................:............... '900B6-85
LM317, Positive Adjustable Regulator ..................................................................................................................... '900B 4-137
LM317HV, High Voltage Positive Adjustable Regulator ........................................................................................... '900B 4-145
LM318, High Slew Rate Op Amp ............................................................................................................................. '900B 2-311
LM318S8, High Speed Op Amp ............................................................................................................................... '900B 2-319
LM319, Oual Comparator ........................................................................................................................................ '900B 6-93
LM323, 5 Volt, 3 Amp Regulator ............................................................................................................................. '900B 4-149
LM329, 6.9V Precision Voltage Reference ............................................................................................................... '900B 3-83
LM334S8, Constant Current Source and Temperature Sensor ................................................................................ '900B 3-99
LM336-2.5, 2.5 Volt Reference ................................................................................................................................ '900B 3-101
LM337, Negative Adjustable Regulator .................................................................................................................... '900B 4-157
LM337HV, High Voltage Negative Adjustable Regulator .......................................................................................... '900B 4-165
LM338, 5 Amp Positive Adjustable Regulator .......................................................................................................... '900B 4-169
LM350, 3 Amp Positive Adjustable Regulator .......................................................................................................... '900B 4-177
LM385-1.2, Micropower Voltage Reference ............................................................................................................'900B 3-105
LM385-2.5, Micropower Voltage Reference ............................................................................................................'900B3-1 09
LM385S8-1.2, Micropower Voltage Reference ........................................................................................................ '900B 3-113
LM385S8-2.5, Micropower Voltage Reference ........................................................................................................ '900B 3-113
LM399, Precision Reference .................................................................................................................................... '900B 3-115
LM399A, Precision Reference .................................................................................................................................. '900B3-115
LT111A, Improved LMlll ....................................................................................................................................... '900B 6-85
LTI17A, Improved LMI17 ....................................................................................................................................... '900B 4-137
LT117AHV, Improved LMI17HV.............................................................................................................................. '900B 4-145
LT118A, Improved LM118 Op Amp ......................................................................................................................... '900B 2-311
LTI19A, Improved LMI19 ....................................................................................................................................... '900B 6-93
LTI23A,lmprovedLMI23 ....................................................................................................................................... '900B 4-149
LT137A, Improved LMI37 ....................................................................................................................................... '900B 4-157
LT137AHV, Improved LMI37HV.............................................................................................................................. '900B 4-165
LTI38A, Improved LM138 .......................................................................................................................................'900B 4-169
LT150A, Improved LMI50 ....................................................................................................................................... '900B 4-177
LTC201A, Micropower, Low Charge Injection, Quad CMOS Analog Switch ............................................................. '920B 11-4
LTC202, Micropower, Low Charge Injection, Quad CMOS Analog Switch ............................................................... '920B 11-4
LTC203, Micropower, Low Charge Injection, Quad CMOS Analog Switch ............................................:.................. '920B 11-4
LTC221, Micropower, Low Charge Injection, Quad CMOS Analog Switch with Data Latches .................................. '920B 11-15
LTC222, Micropower, Low Charge Injection, Quad CMOS Analog Switch with Data Latches .................................. '920B 11-15
LT311A, Improved LMlll ....................................................................................................................................... '900B 6-85
LT317A, Improved LMI17 ....................................................................................................................................... '900B 4-137
LT317AHV, Improved LMI17HV.............................................................................................................................. '900B 4-145
LT318A, Improved LM118 Op Amp .........................................................................................................................'900B 2-311
LT319A, Improved LM119 .......................................................................................................................................'900B 6-93
LT323A,lmproved LM123 .......................................................................................................................................'900B 4-149
LT337A, Improved LMI37 ....................................................................................................................................... '900B 4-157
LT337AHV,lmproved LMI37HV.......................................................................................................................;...... '900B 4-165
Note: All products in BOLD are in this Databook, others appear in LTC's 1990,1992 and 1994 Databooks (,90D8 = LTC's 1990 Databook, '92D8 = LTC's 1992 Databook Supplement
and '94D8 =LTC's 1994 Databook).

22

ALPHANUMERIC INDEX
LT338A, Improved LM138 .......................................................................................................................................'9008 4-169
LT350A, Improved LM150 ....................................................................................................................................... '9008 4-177
LTC485, Low Power RS485 Interface Transceiver ................................................................................................... '9208
5-6
LTC486, Quad Low Power RS485 Driver ................................................................................................................. '9208 5-16
LTC481, Quad Low Power RS485 Driver ................................................................................................................. '9208 5-24
LTC488, Quad RS485 Line Receiver ........................................................................................................................ '9408 5-158
LTC489, Quad RS485 Line Receiver ........................................................................................................................ '9408 5-158
LTC490, Low Power RS485 Interface Transceiver ................................................................................................... '9208 5-32
LTC491, Low Power RS485 Interface Transceiver ................................................................................................... '9208 5-40
LT574A, Complete 12-8it AID Converter ...............•.................................•..........................•..................6-48
LT580, Precision Reference .....................................................................................................................................'9008 3-121
LT581 , Precision Reference .....................................................................................................................................'9008 3-121
LTC660, 100mA CMOS Voltage Converter ............................................................................................. 4-53
LT685, High Speed Comparator ............................................................................................................................... '9008
6-5
LTC690, Microprocessor Supervisory Circuit .......................................................................................................... '9208
9-4
LTC691, Microprocessor Supervisory Circuit ..........................................................................................................'9208
9-4
LTC692, Microprocessor Supervisory Circuit .......................................................................................................... '9408
9-4
LTC693, Microprocessor SuperviSOry Circuit .......................................................................................................... '9408
9-4
LTC694, Microprocessor SuperviSOry Circuit .......................................................................................................... '9208
9-4
LTC694-3.3, 3.3V Microprocessor Supervisory Circuit ............................................................................................ '9408 9-19
LTC695, Microprocessor Supervisory Circuit .......................................................................................................... '9208
9-4
LTC695-3.3, 3.3V Microprocessor Supervisory Circuit ............................................................................................ '9408 9-19
LTC699, Microprocessor Supervisory Circuit .......................................................................................................... '9208 9-18
LTt001, Precision Op Amp ......................................................................................................................................'9008 2-11
LTt001CS8, Precision OpAmp ...............................................................................................................................'9008 2-23
LTt002, Dual, Matched Precision Op Amp ..............................................................................................................'9008 2-25
LT1003, 5 Volt, 5 Amp Voltage Regulator ................................................................................................................ '9008
4-9
LTt004, Micropower Voltage Reference ..................................................................................................................'9008 3-17
LTt004CS8-1.2, Micropower Voltage Reference ..................................................................................................... '9008 3-25
LTt 004CS8-2.5, Micropower Voltage Reference .•................................................................................................... '9008 3-25
LTt005, Logic Control/ed Regulator ........................................................................................................................'9008 4-17
LTt006, Precision, Single Supply Op Amp .............................................................................................................. '9008 2-41
LTt006S8, Precision, Single Supply Op Amp .......................................................................................................... '9008 2-53
LT100?, Low Noise, High Speed PreciSion Op Amp ................................................................................................ '9008 2-57
LTt001CS, Low Noise, High Speed Precision Op Amp ............................................................................................ '9008 2-69
LTt 001CS8, Low Noise, High Speed Precision Operational Amplifier ..................................................................... '9208 2-16
LTt008, Picoamp Input Current, Microvolt Offset, Low Noise Op Amp ................................................................... '9008 2-73
LT1009 Series, 2.5 Volt Reference ..........................................................................................................................;'9008 3"27
LTt 009S8, 2.5 Volt Reference ................................................................................................................................. '9008 3-31
LTt010, Fast±150mA Power Buffer ........................................................................................................................ '9008 2-85
LTt011, Voltage Comparator ................................................................................................................................... '9008
6-9
LT1012, Picoamp Input Current, Microvolt Offset, Low Noise Op Amp ......... ,......................................................... '9008 2-105
LT1012S8, Picoamp Input Current, Microvolt Offset, Low Noise Op Amp ............................................................... '9008 2-117
LTt 013, Dual Precision Operational Amplifier .........................................................................................................'9208 2-19
LTt014, Quad Precision Operational Amplifier ......................................................................................................... '9208 2-19
ote: All products in BOLD are in this Databook. others appear in LTC's 1990.1992 and 1994 Oatabooks ('9008 = LTC's 1990 Oatabook. '9208 = LTC's 1992 Oatabook Supplement
ld '94D8 = LTC's 1994 Oatabook).

L7lJ!J£OO

23

ALPHANUMERIC INDEX
LTt015, High Speed Dual Line Receiver ................................................................................................................;.'9208
LT1016, Ultra Fast Precision Comparator ..............................................................................................................;. '9008
LTt 016CS8, Ultra Fast Precision Comparator.......................................................................................................... '9008
LTt 017, Micropower Dual Comparator ...............................................................................,................'..................... '9408
LTt 018, Micropower Dual Comparator .............................................................................................................;...... '9408
LTt019, 2.5V. 4.5V. 5.0V. 10.0V. Precision References .......................................................................................... '9008
LTt020, Micropower Regulator and Comparator ..................................................................................................... '9008
LTt020CS, Micropower Regulator and Comparator .................................................................;.............................. '9008
LTt021, 5.0V. 1.0V. 10.0V. Precision References ................................................................................................... '9008
LTt021DCS8, 5.0V. 7.0V. 10.0V. Precision References ...............................................................•........................... '9008
LT1022, High Speed, Precision JFET Input Op Amp ................................................................................................'9008
LT1024, Dual, Matched Picoampere, Microvolt Input, Low Noise Op Amp ..............................................................'9008
LT1025, Micropower Thermocouple Cold Junction Compensator ........................................................................... '9008
LT1026, Voltage Converter ......................................................................................................................................'9008
LT1027, Precision 5V Reference ..........................................................................................................................•.•.'9208
LTt 028, Ultra-Low Noise Precision High Speed Op Amp ........................................................................................ '9408
LT1 029, 5V Bandgap Reference ............................................................................................................................... '9008
LT1 030, Quad Low Power Line Driver .....................................................................................................................'9008
LT1030CS, Quad Low Power Line Driver .........................................................................................•....................... '9008
LT1031, Precision 10V Reference ............................................................................................................................'9008'
LTt 032, Quad Low Power Line Driver ......................................................................................................•..............'9008
LTt 033, 3A Negative Adjustable Regulator ..............................................................................................................'9008
LTt 034-1.2, Micropower Dual Reference .....................................................................•..........................................'9408
LTl034-2.5, Micropower Dual Reference ................................................................................................................'9408
LTt 035, Logic Controlled Regulator .................................................................•......................................................'9008
LT1036, ,Logic Controlled Regulator ........................................................................................................................ '9008
LTt037, Low Noise, High Speed Precision Op Amp ................................................................................................ '9008
LTt 037CS, Low Noise, High Speed Precision Op Amp ............................................................................................ '9008
LTt037CS8, Low Noise, High Speed Precision Operational Amplifier .....................................................................'9208
LT1038, 10 Amp Positive Adjustable Voltage Regulator .......................................................................................... '9008
LTt 039, RS232 Driver/Receiver with Shutdown ...................................................................................................... '9008
LTCI 040, Dual Micropower Comparator ............................................................•..........•.........................................'9008
LTC1041, BANG-BANG Controller ............................................................................................................................'9008
LTCI 042, Window Comparator................................................................................................................................ '9008
LTCI 043, Dual Precision Instrumentation Switched Capacitor Building Block ........................................................ '9008
LTC1043CS, Dual Precision Instrumentation Switched Capacitor Building Block .................................................... '9008
LTC1044,' Switched Capacitor Voltage Converter .........................•..........................................;................................ '9008
LTC1 044A, 12V CMOS Voltage Converter................................................................................................................ '9408
LTCI 044CS8, Switched Capacitor Voltage Converter .......................................................................................;...... '9008
LTC1045, Programmable Micropower Hex Translator/Receiver/Driver .................................................................... '9008
LTC1 046, SOmA Switched Capacitor Voltage Converter .......................................................................................... '9208
LTC1047, Dual Micropower Zero Drift Operational Amplifier with Internal Capacitors ............................................. '9208
LTCI 049, Low Power Zero Drift Operational Amplifier with Internal Capacitors .................................................•.... '9208
LTC1050, Precisionlero Drift Op Amp with Internal Capacitors ............................................................................. '9008
LTC1051, Dual Precision Zero Drift Operational Amplifier with1nternal Capacitors ................................................. '9208

10-4
6-25
6-41
10-4
10-4
3-33
4-29
4-45
3-41
3-57
2-145
2-153
11-7
5-3
7-6
2-12
3-61
10-5
10-9
3-65
10-11
4-49
7-5
7-5
4-57
4-69
2-57
2-69
2-16
4-77
10-19
6-57
6-69
6-77
11-15
11-31
5-9
4-16
5-21
10-27
4-16
2-292
2-299
2-181
2-306

Note: All products in BOLD are in this Oatabook, others appear In LTC's 1990,1992 and 1994 Oatabooks ('9008 = LTC's 1990 Oatabook, '9208 = LTC's 1992 Oatabook Supplement
and '9408 = LTC's 1994 Oatabook).

24

ALPHANUMERIC INDEX
LTCI 052, Zero Drift Op Amp ................................................................................................................................... '900B
LTC1052CS, Zero Drift Op Amp ............................................................................................................................... '900B
LTC1053, Quad Precision Zero Drift Operational Amplifier with Internal Capacitors ................................................ '920B
LTt054, Switched-Capacitor Voltage Converter with Regulator ............................................................................... '940B
LTl055, Precision, High Speed, JFET Input Op Amp ............................................................................................... '900B
LTt055S8, Precision, High Speed, JFET Input Op Amp ........................................................................................... '900B
LTt 056, Precision, High Speed, JFET Input Op Amp ............................................................................................... '900B
LTt056S8, Precision, High Speed, JFET Input Op Amp ........................................................................................... '900B
LTt 057, Dual JFET Input Precision, High Speed Op Amp ........................................................................................ '900B
LTt 0571S, Dual JFET Input Precision High Speed Op Amp ...................................................................................... '920B
LTl0571S8, Dual JFET Input Precision High Speed Op Amp .................................................................................... '920B
LTl057S, Dual JFET Input Precision High Speed Op Amp ....................................................................................... '920B
LTt 057S8, Dual JFET Input Precision High Speed Op Amp .....................................................................................'920B
LTl058, Quad JFET Input Precision, High Speed Op Amp .......................................................................................'900B
LTl0581S, Quad JFET Input Precision High Speed Op Amp .................................................................................... '920B
LTt058S, Quad JFET Input Precision High Speed Op Amp ...................................................................................... '920B
LTC1059, High Peformance Switched Capacitor Universal Filter ............................................................................. '900B
LTC1059CS, High Performance Switched Capacitor Universal Filter .......................................................................'900B
LTC1060, Universal Dual Filter Building Block .........................................................................................................'900B
LTC1060CS, Universal Dual Filter Building Block ..................................................................................................... '9OOB
LTC1061, High Performance Triple Universal Filter Building Block .......................................................................... '900B
LTCI 061 CS, High Performance Triple Universal Filter Building Block ..................................................................... '900B
LTC1062, 5th Order Lowpass Filter .........................................................................................................................'940B
LTC1063, DC Accurate, Clock-Tunable 5th Order Butterworth Lowpass Filter .......................................................... '940B
LTCI 064, Low Noise, Fast, Quad Universal Filter Building Block ............................................................................. '900B
LTC1064-1, Low Noise, 8th Order, Clock Sweepable Elliptic Lowpass Filter ........................................................... '900B
LTC1064-2, Low Noise, High Frequency, 8th Order Butterworth Lowpass Filter ..................................................... '920B
LTC1064-3, Low Noise, High Frequency, 8th Order Linear Phase Lowpass Filter .................................................... '920B
LTC1064-4, Low Noise, 8th Order, Clock Sweepable Cauer Lowpass Filter ............................................................ .'920B
LTC1064-7, Linear Phase, 8th Order Lowpass Filter ................................................................................................ '940B
LTC1065, DC Accurate, Clock-Tunable Linear Phase 5th Order Bessel Lowpass Filter ............................................ '940B
LTC1066-1, 14-Bit DC Accurate Clock-Tunable, 8th Order Elliptic or Linear Phase Lowpass Filter ......................... '940B
LTt070, 5A High Efficiency SWitching Regulator ..................................................................................................... '900B
LTt071, 2.5A High Efficiency Switching Regulator .................................................................................................. '900B
LT1072, 1.25A High Efficiency Switching Regulator ................................................................................................ '94OB
LTt 073, Micropower DC-DC Converter Adjustable and Fixed 511, 12V..................................................................... '920B
LTt074, Step-Down Switching Regulator ................................................................................................................ '940B
LTt076, Step-Down Switching Regulator ................................................................................................................ '940B
LTt076-5, 5V Step-Down Switching Regulator .......................................................................................................'920B
LTt077, Micropower, Single Supply, Precision Operational Amplifier ..................................................................... '920B
LTt 078, Micropower, Dual, Single Supply, Precision Operational Amplifier ............................................................ '920B
LTl079, Micropower, Quad, Single Supply, Precision Operational Amplifier...........................................................'920B
LTt 080, Advanced Low Power 5V RS232 Dual Driver/Receiver ..............................................................................'900B
LTt080CS, 5VPowered RS232 Driver/Receiver with Shutdown ............................................................................. '900B
LTt 081, Advanced Low Power 5V RS232 Dual Driver/Receiver .............................................................................. '900B

2-197
2-217
2-306
4-26
2-219
2-231
2-219
2-231
2-235
2-41
2-44
2-41
2-44
2-235
2-41
2-41
7-3
7-11
7-15
7-35
7-39
7-55
8-5
8-16
7-73
7-89
8-5
8-13
8-21
8-28
8-39
8-51
5-37
5-37
4-232
4-174
4-243
4-243
4-208
2-45
2-56
2-56
10-43
10-51
10-43

: All products in BOLD are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oatabooks ('9008 = LTC's 1990 Oatabook, '9208 = LTC's 1992 Oatabook Supplement
'9408 = LTC's 1994 Oatabook).

25

ALPHANUMERIC INDEX
LTt 08t CS, 5V Powered RS232 DriverfReceiver with Shutdown ............................................................................. '900B1 0-51
LTt082, lA High Voltage, High Efficiency Switching Voltage Regulator .................................................................. '940B 4-257
LTt083, 1.5A Low Dropout Positive AdjustableRegulator ...................................................................................... '940B 4-48
LTt083, ?5A Low Dropout Positive Fixed Output Regulator .............................................................................•..... '940B 4-61
LTt084, 5A Low Dropout Positive Adjustable Regulator ...................................•.........•.....•..................................... '940B 4-48
LTt 084, 5A Low Dropout Positive Fixed Output Regulator .................................
'940B 4-61
LTt085, 3A Low Dropout Positive Adjustable Regulator ......................................................................................... '940B 4-48
LTl085, 3A Low Dropout Positive Fixed Output Regulator ...................•........................................:~........................ '940B 4-61
LTt086 Series, 1.5A Low Dropout Positive 2.8511, 3.311, 3.611, 511, 12V and Adjustable Regulators ........................ '940B 4-72
LTt08?, Adjustable Low Dropout Regulator with Kelvin-Sense Inputs .................................................................... '920B 4-56
LTt088, Wideband RMS-DC Converter Building Block ............................................................................................ '900B 11-33
LTt089, High Side Switch ............................................................................................-. ......................................... '900B 11-45
LTC1090, Single Chip to-Bit Data Acquisition System ............................................................................................ '90DB
9-5
LTG1091, I-Channel, la-Bit Serial IfaData Acquisition System .............................................................................. '900B 9-29
LTC1092,2-Channel, to-Bit Serial If0 Data Acquisition System ..........................................................•...................'900B 9-29
LTCt093,6-Channel, to-Bit Serial If0 Data Acquisition System ....................................•......................................... '900B 9-29
LTCt094,8-Channel, to-Bit Serial If0 Data Acquisition System .............................................................................. '900B 9-29
LTCt 095, Complete to-Bit Data Acquisition System with On Board Reference ................ ;...................................... '900B 9-57
LTCt096, Micropower Sampling 8-Bit Serial IfaAID Converter ..............................................:............................... '940B
6-8
LTt09?, Low Cost, Low Power Precision Operational Amplifier .............................................................................. '920B 2-74
LTCt098, Micropower Sampling 8-Bit Serial If0 AID Converter .............................................................................. '940B
6-8
LTCt099, High Speed 8-Bit AID Conve.rter with Built-In Sample-and-Hold .............................................................. '900B 9-81
LTGttOO, Precision, Zero Drift Instrumentation Amplifier ....................................................................................... '920B
3-4
LTtl at, Precision, Micropower, Single Supply Instrumentation Amplifier (Fixed Gain = to or tOO) ...................... '920B 3-11
LTtt02, High Speed, Precision, JFET Input Instrumentation Amplifier (Fixed Gain = to or tOO) ............................ '920B 3-23
LTtt 03, Offline Switching Regulator ....................................................................................................................... '940B 4-267
LTtt 05, Offline Switching Regulator ....................................................................................................................... '940B4-267 .
LT1106, Micropower Step-Up DC/DC Converter for PCMCIA Card Flash Memory .......•................................•.... 4-146
LH10?, Micropower DCfDC Converter Adjustable and Fixed 511, t2V ..................................................................... '940B 4-294
LTtl08, Micropower DCfDC Converter Adjustable and Fixed 511, t2V ..................................................................... '940B 4-306
LTtl09, Micropower Low Cost DCfDC Converter Adjustable and Fixed 511, t2V ..................................................... '940B 4-318
LTtt09A, Micropower DC/DC Converter Flash Memory VPP Generator Adjustable and Fixed 511, 12V .................. .'940B 4-325
LTtttO, Micropower DC-DC Converter Adjustable and Fixed 511, t211, High Frequency ..........................................'920B 4-245
LTttll, Micropower DCfDC Converter Adjustable and Fixed 511, 12V ............................................•........................ '940B .4-331
LTttt2, Dual Low Power Precision, Picoamp Input Op Amp .................................................................................. '940B 2-29
LTttt3, Dual Low Noise, Precision, JFET Input Op Amps .................. ~ ............................•....................................... '940B 2-40
LTttt4, Quad Low Power Precision, Picoamp Input Op Amp ................................................................................. '940B 2-29
LTtt15, Ultra-Low Noise, Low Distortion, Audio Operational Amplifier ...............................................................;.. '920B 2-82
LTtt16, t2ns, Single Supply Ground-Sensing Comparator .........................................................................,......•... '920B 10-7
LTttl?, 800mA Low Dropout Positive Regulator Adjustable and Fixed 2.8511, 3.311, 5V......................................... '940B 4-85
LT111B-2.5, Low la, Low Dropout, BOOmA Source and Sink Regulator Fixed2.5V Output ................................... 4-64
LT111B-2.B5, Low la, Low Dropoul, BOOmA Source and Sink Regulator Fixed 2.B5V Output ................................ 4-64
LT1tlB-5, Low la, Low Dropout, BOOmA Source and Sink Regulator Fixed 5V Output ....................•................... 4-64
LTt120, Micropower Regulator with Comparator and Shutdown ............................................................................ '940B 4-96
LTtt20A; Micropower Regulator with Comparator and Shutdown .................... :..................................................... '940B 4-107
0 •••••••••••••••••••••••• 0 •••••••••••••••••••••••••••

Note: All products in BOLD are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oalabooks (,900B = LTC's 1990 Oatabook, '920B = LTC's 1992 Oatabook Supplement
and '940B = LTC's 1994 Oalabook).

26

ALPHANUMERIC INDEX
LT1121, Micropower Low Dropout Regulator with Shutdown ................................................................................. '940B 4-114
LT1121-3.3, Micropower Low Dropout Regulator with Shutdown ........................................................................... '940B 4-114
LT1121-5, Micropower Low Dropout Regulator with Shutdown .............................................................................. '940B 4-114
LT1122, Fast Settling, JFET Input Operational Amplifier .......................................................................................... '940B 2-84
LT1123, 5V Low Dropout Regulator Driver .............................................................................................................. '920B 4-75
LT1124, Dual Low Noise, High Speed Precision Operational Amplifier .................................................................... '920B 2-94
LT1125, Quad Low Noise, High Speed Precision Operational Amplifier................................................................... '920B 2-94
LT1126, Dual Decompensated Low Noise, High Speed Precision Operational Amplifier ......................................... '920B 2-105
LT1127, Quad Decompensated Low Noise, High Speed Precision Operational Amplifier ........................................'920B 2-105
LT1128, Unity Gain Stable Ultra-Low Noise Precision High Speed Op Amp ............................................................ '940B 2-12
LT1129, Micropower Low Dropout Regulator with Shutdown ................................................................................. '940B 4-125
LT1129-3.3, Micropower Low Dropout Regulator with Shutdown ........................................................................... '940B 4-125
LT1129-5, Micropower Low Dropout Regulator with Shutdown .............................................................................. '940B 4-125
LT1130, 5-DriverI5-Receiver RS232 Transceiver .............................................................................................. Refer to LT1130A
LT1130A, Advanced 5-DriverI5-Receiver RS232 Transceiver .................................................................................. '940B 5-10
LT1131, 5-DriverI4-Receiver RS232 Transceiver with Shutdown ..................................................................... Refer to LT1131 A
LT1131 A, Advanced 5-DriverI4-Receiver RS232 Transceiver with Shutdown ......................................................... '940B 5-10
LT1132, 5-DriverI3-Receiver RS232 Transceiver .............................................................................................. Refer to LT1132A
LT1132A, Advanced 5-DriverI3-Receiver RS232 Transceiver .................................................................................. '940B 5-10
LT1133, 3-DriverI5-Receiver RS232 Transceiver .............................................................................................. Refer to LT1133A
LT1133A, Advanced 3-DriverI5-Receiver RS232 Transceiver .................................................................................. '940B 5-10
LT1134, 4-DriverI4-Receiver RS232 Transceiver .............................................................................................. Refer to LT1134A
LT1134A, Advanced 4-DriverI4-Receiver RS232 Transceiver .................................................................................. '940B 5-10
LT1135, 5-DriverI3-Receiver RS232 Transceiver without Charge Pump .......................................................... Refer to LT1135A
LT1135A, Advanced 5-DriverI3-Receiver RS232 Transceiver without Charge Pump ............................................... '940B 5-10
LT1136, 4-DriverI5-Receiver RS232 Transceiver with Shutdown ..................................................................... Refer to LT1136A
LT1136A, Advanced 4-DriverI5-Receiver RS232 Transceiver with Shutdown ......................................................... '940B 5-10
LT1137, 3-DriverI5-Receiver RS232 Transceiver with Shutdown ..................................................................... Refer to LT1137A
LT1137A, Advanced 3-DriverI5-Receiver Low Power 5V RS232 Transceiver with Small Capacitors ....................... '940B 5-20
LT1138, 5-DriverI3-Receiver RS232 Transceiver with Shutdown ..................................................................... Refer to LT1138A
LT1138A, Advanced 5-DriverI3-Receiver RS232 Transceiver with Shutdown ......................................................... '940B 5-10
LT1139, 4-DriverI4-Receiver RS232 Transceiver with Shutdown ..................................................................... Refer to LT1139A
LT1139A, Advanced 4-DriverI4-Receiver RS232 Transceiver with Shutdown ......................................................... '940B 5-10
LT1140, 5-DriverI3-Receiver RS232 Transceiver without Charge Pump .......................................................... Refer to LT1140A
LT1140A; Advanced 5-DriverI3-Receiver RS232 Transceiver without Charge Pump ............................................... '940B 5-10
LT1141, 3-DriverI5-Receiver RS232 Transceiver without Charge Pump .......................................................... Refer to LT1141 A
LT1141A, Advanced 3-DriverI5-Receiver RS232 Transceiver without Charge Pump ............................................... '940B 5-10
LTC1142, Dual High Efficiency Synchronous Step-Down SWitching Regulator .......................................................'940B 4-346
LTC1142-ADJ, Dual High Efficiency Synchronous Step-Down Switching Regulator ............................................... '940B 4-346
LTC1143, Dual High Efficiency Step-Down Switching Regulator Controller ............................................................. '940B 4-365
LTC1144, Switched-Capacitor Wide Input Range Voltage Converter with Shutdown .............................................. '940B 4-38
LTC1145, Low Power Digital Isolator ......................................................................................................................'940B 5-186
LTC1146, Low Power Digital Isolator ...................................................................................................................... '940B 5-186
LTC1147-3.3, High Efficiency Step-Down Switching Regulator Controller .............................................................. '940B 4-380
LTC1147-5, High Efficiency Step-Down Switching Regulator Controller ................................................................. '940B 4-380
Ite: All products in BOLO are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oatabooks (,900B = LTC's 1990 Oatabook, '920B = LTC's 1992 Oatabook Supplement
d '940B = LTC's 1994 Oatabook).

L7lJ!J~

27

ALPHANUMERIC INDEX
LTC1148, High Efficiency Synchronous Step-Down Switching Regulator ............................................................... '940B 4-395
LTC1148-3.3, High Efficiency Synchronous Step-Down Switching Regulator ............................ ;........... ;................ '940B 4-395
LTC1148-5, High Efficiency Synchronous Step-Down Switching Regulator ............................................................ '940B 4-395
LTC1149, High Efficiency Synchronous Step-Down Switching Regulator ............................................................... '940B 4-414
LTC1149-3.3, High Efficiency Synchronous Step-Down Switching Regulator ..•...................................................... '940B 4-414
LTC1149-5, High Efficiency Synchronous Step-Down Switching Regulator ........................................................... .'940B 4-414
LTC1150, ±15V Zero Drift Operational Amplifier with Internal CapacitorSc. ..................................... ,...................... .'920B 2-321
LTC1151, Dual ±15V Zero-Drift Operational Amplifier ............................................................................................. '940B 2-356
LTC1152, Rail-to-Raillnput Rail-to-Rail Output ZerO-Drift Op Amp ..•......•.........•......• ;.....•...•...•..••.......••......• 2-42
LTC1153, Auto-Reset Electronic Circuit Breaker ....................................................................................;................. '940B 4-138
LTC1154, High-Side Micropower MOSFET Driver .................................................................................................... '940B 4-152
LTC1155, Dual High Side Micropower N-Channel MOSFET Driver with Internal Charge Pump ............................... '920B 4-26
LTC1156, Quad High Side Micropower N-Channel MOSFET Driver with Internal Charge Pump ............................. .'92DB 4-41
LTC1157, 3.3V Dual Micropower High-Side/Low-Side MOSFET Driver ................................................................... '940B 4-167
LT1158, Half Bridge N-Channel Power MOSFET Driver ........................................................................................... '920B 4-102
LTC1159, High Efficiency Synchronous Step-Down Switching Regulator •...........•.................•..•...•.....•........•. 4-154
LTCI159-3.3, High Efficiency Synchronous Step-Down Switching Regulator •...••....•....•......••..•...•....•............. 4-154
LTCllS9-5, High Efficiency Synchronous Step·Down Switching Regulator .................................................... 4-154
LT1160, Half-Bridge N-Channel Power MOSFET Drivers ........................................................................... 13-3
LT1161, Quad Protected High-Side MOSFET Driver .......................................................................~ ........................ '94DB 4-175
LT1162, Full-Bridge N-Channel Power MOSFET Drivers ........................................................................... 13-3
LTC1163, Triple 1.8Vto 6V High-Side MOSFET Driver ............................................................................................ '940B 4-186
LTC1164, Low Power, Low Noise, Quad Universal Filter Building Block ..................................................................'920B 8-29
LTC1164-5, Low Power 8th Order Pin Selectable Butterworth or Bessel Lowpass Filter ......................................... '940B 8-67
LTC1164-6, Low Power 8th Order Pin Selectable Elliptic or Linear Phase Lowpass Filter ....................................... '940B 8-78
LTC1164-7, Low Power, Linear Phase 8th Order Lowpass Filter ............................................................................. '94DB 8-89
LTC1164-8, Ultra-Selective, Low Power 8th Order Elliptic Bandpass Filter with Adjustable Gain ............................ 8-5
LTC1165, Triple 1.8Vto 6V High-Side MOSFET Driver ............................................................................................ '940B 4-186
LT1169, Dual Low Noise, Picoampere Bias Current, JFET Input Op Amp ................................................................ '940B 2-55
LT11l0, 100kHz, 5A High Efficiency Switching Regulator ....................................................................................... '940B 4-433
LT11l1, 100kHz, 2.5A High Efficiency Switching Regulator .................................................................................... '940B 4-433
LT11l2, 100kHz, 1.25A High Efficiency Switching Regulator .................................................................................. '940B 4-433
LT11l3, Micropower DC-DC Converter Adjustable and Fixed 5V, 12V..................................................................... '920B 4-275
LTC11l4, High Efficiency Step-Down and Inverting DC/DC Converter ..................................................................... '940B 4-447
LTC11l4-3.3, High Efficiency Step-Down and Inverting DC/DC Converter ..............................................................'940B 4-447
LTC11l4-5, High Efficiency Step-Down and Inverting DC/DC Converter .................................................................'940B 4-447
LT1175, 500mA Negative Low Dropout Micropower Regulator ................................................................... 4-68
LT11l6, Step-Down Switching Regulator ................................................................................................................'940B 4-462
LT11l6-5, Step-Down Switching Regulator ............................................................................................................. '940B 4-462
LTC1177-5, Isolated MOSFET Driver .............................. ,'; ................................................................. 13-16
LTC1177-12, Isolated MOSFET Driver ................................................................................................ 13-16
LT11l8, 1ltJA Max, Dual, Single Supply, Precision Operational Amplifier ..................................;............................ '920B 2-112
LT11l8S8, 20tJA Max, Dual SO-8 Package, Single Supply Precision Op Amp ......................................................... '940B 2-67
LT11l9, 1ltJA Max, Quad, Single Supply, Precision Operational Amplifier .............................................................. '920B 2-112
LT1180, Advanced Low Power 5V RS232 Dual Driver/Receiver with Small CapaCitors .................................... Refer to LT1180A
Note: All products in BOLD are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oatabooks (,900B =LTC's 1990 Oatabook, '920B =LTC's 1992 Oatabook Supplement
and '940B = LTC's 1994 Oatabook).

28

ALPHANUMERIC INDEX
LT1180A, Low Power 5V RS232 Dual Driver/Receiver with 0.1pF Capacitors ......................................................... '9408 5-27
LT1181, Advanced Low Power 5V RS232 Dual Driver/Receiver with Small Capacitors .................................... Refer to LT1181A
LT1181A, Low Power 5V RS232 Dual Driver/Receiver with 0.1pF CapaCitors ......................................................... '9408 5-27
LT1182, CCFL/LCO Contrast Switching Regulator .................................................................................. 4-172
LT1183, CCFL/LCO Contrast Switching Regulator .................................................................................. 4-172
LT1184, CCFL Switching Regulator .................................................................................................. 4-172
LT1184F, CCFL Switching Regulator ................................................................................................. 4-172
LT1185, Low Dropout Regulator with Adjustable Current Limit.. ............................................................................. '9208 4-86
LT1186, OAC Programmable CCFL Switching Regulator (Bits-to-Nits™j ...................................................... 4-196
LT1187, Low Power Video Difference Amplifier....................................................................................................... '9408 2-92
LT1188, 1.5AHighSideSwitch ............................................................................................................................... '9208 4-48
LT1189, Low Power Video Difference Amplifier ....................................................................................................... '9408 2-104
LT1190, Ultra High Speed Operational Amplifier (Av;? 1) ........................................................................................ '9208 2-126
LT1191, Ultra High Speed Operational Amplifier (Av;? 1) ........................................................................................ '9208 2-137
LT1192, Ultra High Speed Operational Amplifier (Av;? 5) ........................................................................................ '9208 2-148
LT1193, Video Difference Amplifier, Adjustable Gain ............................................................................................... '9208 2-159
LT1194, Video Difference Amplifier, Gain of 10 ....................................................................................................... '9208 2-171
LT1195, Low Power, High Speed Operational Amplifier .......................................................................................... '9408 2-116
LTC1196, 8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options ......................................................................... '9408 6-32
LTC1198, 8-Bit, SO-8, 750ksps ADCs with Auto-Shutdown Options ....................................................................... '9408 6-32
LT1200, Low Power High Speed Operational Amplifier ........................................................................................... '9208 2-182
LT1201, Dual1mA, 12MHz, 50Vlps OpAmp ........................................................................................................... '9408 2-127
LT1202, Quad 1mA, 12MHz, 50Vlps OpAmp .......................................................................................................... '9408 2-127
LT1203, 150MHz Video Multiplexer ......................................................................................................................... '9408 2-374
LT1204, 4-lnput Video Multiplexer with 75MHz Current Feedback Amplifier ........................................................... '9408 2-389
LT1205, 150MHz Video Multiplexer ......................................................................................................................... '9408 2-374
LT1206, 250mAl60MHz Current Feedback Amplifier ......................................... c..................................................... '9408 2-137
LT1208, Dual 45MHz, 400Vlps OpAmp .................................................................................................................. '9408 2-150
LT1209, Quad 45MHz, 400V/ps OpAmp ................................................................................................................. '9408 2-150
LT1211, 14MHz, 7V1ps, Single Supply Dual Precision Op Amp ............................................................................... '9408 2-160
LT1212, 14MHz, 7V1ps, Single Supply Quad Precision Op Amp .............................................................................. '9408 2-160
LT1213, 28MHz, 12V1ps, Single Supply Dual Precision Op Amp ................... ;......................................................... '9408 2-176
LT1214, 28MHz, 12V1ps, Single Supply Quad Precision Op Amp .............................. ;............................................. '9408 2-176
LT1215, 23MHz, 50Vlps, Single Supply Dual Precision Op Amp ............................................................................. '9408 2-192
LT1216,23MHz, 50Vlps, Single Supply Quad Precision Op Amp ............................................................................ '9408 2-192
LT1217, Low Power High Speed Current Feedback Amplifier .............,.................................................................... '9208 2-190
LT1220, Vel}' High Speed Operational Amplifier (Av;? 1) ........................................................................................ '9208 2-198
LT1221, Vel}' High Speed Operational Amplifier (Av;? 4) ....................... ;.... ;.c ......................................................... '9208 2-210
LT1222, Low Noise, Vel}' High Speed Operational Amplifier (Av;? 10) ................................................................... '9208 2-218
LT1223, 100MHz Current Feedback Amplifier.......................................................................................................... '9208 2-226
LT1224, Vel}' High Speed Operational Amplifier (Av;? 1) ........................................................................................ '9208 2-237
LT1225, Vel}' High Speed Operational Amplifier (Av;? 5) ........................................................................................ '9208 2-245
LT1226, Low Noise Vel}' High Speed Operational Amplifier (Av;? 25) .................................................................... '9208 2-253
LT1227,140MHz Video Current Feedback Amplifier ................................................................................................ '9408 2-208
~ote: All products in BOLD are in this Oatabook. others appear in LTC's 1990.1992 and 1994 Oatabooks ('9008 =LTC's 1990 Oatabook, '9208 =LTC's 1992 Oatabook Supplement
md '9408 = LTC's 1994 Oatabook).

29

ALPHANUMERIC INDEX
LT1228, 100MHz Current Feedback Amplifier with DC Gain Control ........................................................................ '920B 2-261
LT1229, Dual 1OOMHz Current Feedback Amplifier ................................................................................................. '920B 2-280
LT1230, Quad 100MHz Current Feedback Amplifier .....................................,.......................................................... '920B 2-280
LTC1232, Microprocessor Supervisory Circuit ..........................................................................,............................. '920B 9-22
LTC1235, Microprocessor Supervisory Circuit with Conditional Battery Backup ..................................................... '920B 9-29
LT1236, Precision Reference •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.•••••••••••••••••••••••••••••••••• 7-5
LT1237, 5V RS232 Transceiver with Advanced Power Management and One Receiver Active in SHUTDOWN ...... .'940B 5-34
L.11239, Backup Battery Management Circuit •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4-454
LT1241, High Speed Current Mode Pulse Width Modulator .................... ;............................................................... '920B 4-122
LT1242, High Speed Current Mode Pulse Width Modulator .................................................................................... '920B 4-122
LT1243, High Speed Current Mode Pulse Width Modulator .................................................................................... '920B· 4-122
LT1244, High Speed Current Mode Pulse Width Modulator .................................................................................... '920B 4-122
LT1245, High Speed Current Mode Pulse Width Modulator .................................................................................... '920B 4-122
L11246, 1MHz Off-Line Current Mode PWM •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4-126
L11247, 1MHz Off-Line Current Mode PWM •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4-126
LT1248, Power Factor Controller .............................................................................................................................'940B 4-194
LT1249, Power Factor Controller .............................................................................................................................'940B 4-205
LTC1250, Very Low Noise Zero-Drift Bridge Amplifier...................;......................................................................... '940B 2-364
LT1251, 40MHz Video Fader.................................................................................................................................... '940B 2-219
LT1252, Low Cost Video Amplifier ..........................................................................................................................'940B 2-242
LT1253, Low Cost Dual Video Amplifier ..................................................................................................................'940B 2-249
LT1254, Low Cost Quad Video Amplifier .................................................................................................................'940B 2-249
LTC1255, Dual24V High-Side MOSFET Driver ...........................................................................;............................ '940B 4-215
LT1256, 40MHz DC Gain Controlled Amplifier .........................................................................................................:940B 2-219
LTC1257, Complete Single Supply 12-Bit Voltage Output DAC in SO-8 ................................................................... '940B 6-210
LT1259, Low Cost Dual 130MHz Current Feedback Amplifier with Shutdown ......................................................... '940B 2-256
LT1260, Low Cost Triple 130MHz Current Feedback Amplifier with Shutdown ....................................................... '940B 2-256
LTC1261, Switched CapaCitor Regulated Voltage Inverter •••••••••••••••••••••••••••••••••••••••••• ; ••••••••••••••••••••••••••••• 4-20
LTC1262, 12V, 30mA Flash Memory Programming Supply •••••••••..••••••••••••••••••••••••••••••••••••••••••••••••.••.•••••••• 4-34
LTC1264, High Speed, Quad Universal Filter Building Block .................................................................................... '940B 8-100
LTC1264-7, Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter .......................................................... '940B 8-115
LTC1265, 1.2A, High EUiciency Step-Down DC/DC Converter •••••••.•.••••••••••••••••••••••••••••••••.•••••••••••••••••..•••••• 4-212
LTC1265-3.3, 1.2A, High EUiciency Step-Down DC/DC Converter ••••••••••••••••••••••••••••••.•••••••••••••••••••••••••••••.•• 4-212
LTC1265-5, 1.2A, High EUiciency Step-Down DC/DC Converter •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.••• 4-212
LTC1266, Synchronous Regulator Controller for N- or P-Channel MOSFETs •••••••••••••••••••••••••••••••••••••••••••••••• ••• 4-228
LTC1266-3.3, Synchronous Regulator Controller for N- or P-Channel MOSFETs •••••••••••••••••••••••••••••••••••••••••••••• 4-228
LTC1266-5, Synchronous Regulator Controller for N- or P-Channel MOSFETs ••• ,............................................ 4-228
LTC1267, Dual High EUiciency Synchronous Step-Down Switching Regulator •••••••••••••••••••••••••••••••••••••••••••••••• 4-248
LTC1267-ADJ, Dual High Efficiency Synchronous Step-Down Switching Regulator .......................................... 4-248
LTC1267-ADJ5, Dual High Efficiency Synchronous Step-Down Switching Regulator •••••••••.•••.•••..•••••••••••••••••••••• 4-248
LT1268, 7.5A, 150kHz Switching Regulator ............................................................................................................'940B 4-466
LT1268B, 7.5A, 150kHz Switching Regulator .............................................;............................................................ '940B 4-466
LT1269, 4A High Efficiency Switching Regulator ..................................................................................................... '940B 4-474
LT1210, 8A High Efficiency Switching Regulator ..................................................................................................... '940B 4-470
Note: All products in BOLD are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oatabooks (,900B = LTC's 1990 Oatabook, '920B = LTC's 1992 Oatabook Supplement
and '940B = LTC's 1994 Oatabook).

30

ALPHANUMERIC INDEX
LT1270A, lOA High Efficiency Switching Regulator................................................................................................. '940B 4-470
LT1271, 4A High Efficiency Switching Regulator ..................................................................................................... '940B 4-474
LTC1272, 12-8it, 3~, 250kHz Sampling AID Converter .......................................................................................... '920B
6-6
LTC1273, 12-8it, 300ksps Sampling AID Converter with Reference ........................................................................ '940B 6-58
LTC1274, 12-Bit, 10mW, 100ksps AID Converter with 1JJA Shutdown .......................................................... 13-22
LTC1275, 12-8it, 300ksps Sampling AID Converter with Reference ........................................................................ '940B 6-58
LTC1276, 12-8it, 300ksps Sampling AID Converter with Reference ........................................................................ '940B 6-58
LTC1277, 12-Bit, 10mW, 100ksps AID Converter with 1JJA Shutdown ...... .................................................... 13-22
LTC1278, 12-8it, 500ksps Samplng AID Converter with Shutdown ........................................................................ '940B 6-80
LTC1279, 12-Bit, 600ksps Sampling AID Converter with Shutdown ................................................................ 6-8
LT1280, Advanced Low Power 5V RS232 Dual Driver/Receiver ....................................................................... Refer to LT1280A
LT1280A, Low Power 5V RS232 Dual Driver/Receiver with O.lpF Capacitors ......................................................... '940B 5-41
LT1281, Advanced Low Power 5V RS232 Dual Driver/Receiver ....................................................................... Refer to LT1281A
LT1281A, Low Power 5V RS232 Dual Driver/Receiver with O.lpF Capacitors ......................................................... '940B 5-41
LTC1282, 3V 140ksps 12-8it Sampling AID Converter with Reference .................................................................... '940B 6-95
LTC1283, 3V Single Chip 10-8it Data Acquisition System ....................................................................................... '940B 6-117
LTC1285, 3V Micropower Sampling 12-Bit AID Converter in SO-8 Package .................................................... 6-24
LTC1286, Micropower Sampling 12-8it AID Converter in SO-8 Package ................................................................. '940B 6-140
LTC1287, 3V Single Chip 12-8it Data Acquisition System ....................................................................................... '920B 6-25
LTC1288, 3V Micropower Sampling 12-Bit AID Converter in SO-8 Package .................................................... 6-24
LTC1289, 3V Single Chip 12-8it Data Acquisition System ....................................................................................... '920B 6-40
LTC1290, Single Chip 12-8it Data Acquisition System .................................................................,.......................... '920B 6-67
LTC1291, Single Chip 12-8it Data Acquisition System ............................................................................................ '940B 6-163
LTC1292, Single Chip 12-8it Data Acquisition System ............................................................................................ '940B 6-182
LTC1293, Single Chip 12-8it Data Acquisition System ............................................................................................'920B 6-113
LTC1294, Single Chip 12-8it Data Acquisition System ............................................................................................ '920B 6-113
LTC1296, Single Chip 12-8it Data Acquisition System ............................................................................................ '920B 6-113
LTC1297, Single Chip 12-8it Data Acquisition System ............................................................................................ '940B 6-182
LTC1298, Micropower Sampling 12-8it AID Converter in SO-8 Package ................................................................. '940B 6-140
LT1300, Micropower High Efficiency 3.3/5V Step-Up DC/DC Converter .................................................................. '940B 4-478
LT1301, Micropower High Efficiency 5V12V Step-Up DC/DC Converter with Flash Memory ................................... '940B 4-486
LT1302, Micropower High Output Current Step-Up Adjustable DCIDC Converter ............................................. 4-264
LT1302-5, Micropower High Output Current Step·Up Fixed 5V DCIDC Converter ............................................. 4-264
LT1303, Micropower High Efficiency DCIDC Converter with Low·Battety Detector, Adjustable ............................. 4-279
LT1303-5, Micropower High Efficiency DCIDC Converter with Low·Battery Detector, Fixed 5V............................. 4-279
LT1304, Micropower DCIDC Converter with Low·Battety Detector Active in Shutdown ...................................... 13-37
LT1304-3.3, Micropower DCIDC Converter with Low·Battety Detector Active in Shutdown ................................. 13-37
LT1304-5, Micropower DCIDC Converter with Low·Battety Detector Active in Shutdown .................................... 13-37
LT1305, Micropower High Power DCIDC Converter with Low·Battety Detector .. ............................................. 4-290
LT1309, 500kHz Micropower DCIDC Converter for Flash Memoty ............................................................... 13-41
LT1311, Quad 12MHz, 145ns Settling Precision Current·to·Voltage Converter for Optical Disk Drives .................... 2-34
LT1312, Single PCMCIA VPP Driver/Regulator ..................................................................................... 4-394
LT1313, Dual PCMCIA VPP Driver/Regulator ....................................................................................... 4-405
LTC1314, PCMCIA Switching Matrix with Built·ln N·Channel Vce Switch Drivers ............................................. 4-415
Die: All products in BOLD are in this Databook, others appear in LTC's 1990,1992 and 1994 Databooks (,90D8 =LTC's 1990 Databook, '92D8 =LTC's 1992 Databook Supplement
Id '94D8 = LTC's 1994 Databook).

L7lJJJ~

31

ALPHANUMERIC INDEX
LTC131S, PCMCIA Switching Matrix with Built-In N-Channel Vee Switch Drivers ........................................... ,.4-415
LTC1318, Single SV RS232/RS422/AppleTalfIIP DCE Transceiver ................................................................ 5-70
LT1319, Mulliple Modulation Standard Infrared Receiver ............................ ;........................................~ ... 5-90
LTC1320, AppleTalfIIP Transceiver ........................................................................................................................... '940B 5-178
LTC1321, 2-EIAS62!RS232 Transceiversl2-RS48S Transceivers .................. :.............. ;........................................... '940B ··5-198
LTC1322; 4-ElAS62!RS232 Transceiversl2-RS48S Transceivers ............................................................................. '940B 5-198
LTC1323, Single SVAppleTalfIIP Transceiver .................................................................................,....... 5-77
LTC1324, Single Supply LocalTalfIIP Transceiver ............................................•..................................... 13-45
LTC132S, Microprocessor-Controlled Battery Management System .............................•.......•...................... 4-466
LTC1321, 3.3V Micropower ElAlTIA-S62 Transceiver .............................................................................................. '940B 5-48
LT1330, SV RS232 Transceiver with 3V Logic Interlace and One Receiver Active in SHUTDOWN .......................... '940B 5-54
LT1331, 3V RS232 or SVI3V RS232 Transceiver with One Receiver Active in SHUTDOWN .................................... '940B 5-61
LT1332, Wide Supply Range Low Power RS232 Transceiver with 12VVPP Output forF/ash Memory .................. .'940B 5-68
LTC1334, Single SV RS232/RS48S Multi-ProtOCOl Transceiver .................................................................. 13-53
LTC133S, 4-EIAS62 Transceiversl2-RS48S Transceivers with Output Enable ......................•.................................. .'9408 5-198
LTC1337, SV Low Power RS232 3-DriverIS-Receiver Transceiver .......................................................................... '940B 5-76
LTC1338, SV Low Power RS232 S-DriverI3-Receiver Transceiver .•............................. ,.. ;............... :....................... '940B 5-82
LT1341, SV RS232 Transceiver with One Receiver Active in SHUTDOWN ............................................................... '940B 5-88
LT1342, SV RS232 Transceiver with 3V Logic Interlace ..........................................................................................'940B 5-95
LTC134S, Single Supply V.3S Transceiver ........ ;........................................ ,., ....................... ~ ................ 5-58
LTC1346; 10Mbps DCE/DTE V.3S Transceiver ............ " ......................................................................... 13-65
LTC1347, SV Low Power RS232 3-DriverIS-Receiver Transceiver with S Receivers Active in SHUTDOWN ............ '940B 5-102
LTC1348, 3.3V Low Power RS232 3-Driverl5-Receiver Transceiver .................. ;.......................................... 5-10
LTC1349, SV Low Power RS232 3-DriverIS-Receiver Transceiver with 2 Receivers Active in SHUTDOWN ........... .'940B 5-108
LTC13S0, 3.3V Low Power ElAlTIA-S62 3-DriverIS-Receiver Transceiver ............................................................... '940B 5-114
LT13S4, 12MHz, 400Vlps Op Amp ..........................................................................................................................'940B 2-267
LT13SS, Dual 12MHz, 400Vlps Op Amp ..................................................................................................................'940B 2-278
LT13S6, Quad 12MHz, 400Vlps Op Amp ......................................................................•;." ...................................... '9408 2~278
LT13S1,2SMHz, 600Vlps Op Amp ................................................:.............................;..........................................;'940B 2-289
LT13S8, DuaI2SMHz, 600VlpsOpAmp .................................................................................................................. '940B 2-300
LT13S9, Quad 2SMHz, 600Vlps Op Amp ........................... :................................... " ..........•...;.. ;..;............................ '940B 2c300
LT1360, SOMHz, 800Vlps OpAmp .................................................::....................................................................... '940B 2-311
LT1361, DuaISOMHz, 800VlfJS Op Amp ...................................;.................................... ,~ ......... !.......•...................... '940B 2-322
LT1362, Quad SOMHz, 800Vlps Op Amp ..................................................................;.............................................. '940B 2-322
LT1363,lOMHz, 1000Vlps OpAmp .............. :................................ :: ..........................................................;..;.......... '940B 2-333
LT1364, DuallOMHz, 1000Vlps Op Amp ......................................................................;.............. :.......................... '940B 2-344
LT136S, Quad lOMHz, 1000Vlps Op Amp ...............................:.......................................•...:... :........... :................... '940B 2-344
LT1366, Dual Precision Rail-Io-Raillnpul and Output Dp Amp ................................................................... 2-14
LT1367, Quad Precision Rail-to-Raillnput and Output Op Amp .................................................................. 2-14
lT1368, Dual Precision Raif-to-Raillnput and Output Dp Amp ................................................................... 2-14
LT1369, Quad Precision Raif-to-Raillnput and Output Op Amp ................. ~ .................... ,........................... 2-14
LT1371, SOOkHz High Efficiency 3A Switching Regulalor .............................. " ......................................... 4-298
LT13!2, SOOkHz High Efficiency 1.SA Switching Regulator ........................... :: ......................................... 4-310
LT1373, 250kHz Low Supply Current High Efficiency 1.SA Switching Regulator ........ :............................. ;....... 4-322
Note: All products in BOLD are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oatabooks (,900B ~ LTC's 1990 Oatabook, '920B = LTC's 1992 Oatabook Supplement
and '940B = LTC's 1994 Databook).

32

ALPHANUMERIC INDEX
LT1375, 1.5A, 500kHz Step-Down Switching Regulator .. ........•............................................•....•......•...... 4-334
LT1376, 1.5A, 500kHz Step-Down Switching Regulator .. .........•.........•......................................•............. 4-334
LT1377, 1MHz High Efficiency 1.5A Switching Regulator ........................................................................ 4-310
LT1381, Low Power 5V RS232 Dual Driver/Receiver with O.lpF Capacitors ..............................................;............ '9408 5-120
LTC1382, 5V Low Power RS232 Transceiver with Shutdown .................................................................................. '9408 5-127
LTC1383, 5V Low Power RS232 Transceiver .......................................................................................................... '9408 5-133
LTC1384, 5V Low Power RS232 Transceiver with 2 Receivers Active in SHUTDOWN ............................................ '9408 5-139
LTC1385, 3.3V Low Power E/AlTIA-562 Transceiver ............................................................................................... ·9408 5-145
LTC1386, 3.3V Low Power E/AlTIA-562 Transceiver ............................................................................................... '9408 5-151
LT1389, AppleTa/~ Peripherallnteriace Transceiver ..............................•........................•...•..•......•...... 13-73
LTC1390, 8-Channel Analog Multiplexer with Seriallnteriace ...............................................•...•......•..•....•. 6-86
LTC1392, Micropower Temperature, Power Supply and Differential Voltage Monitor ..............•..........•...••.......• 13-77
LTC1400, Complete SO-8, 12-8it, 400ksps AID Converter with Shutdown .........................•........................... 13-86
LTC1410, 12-8it, 1.25Msps Sampling AID Converter with Shutdown ........................................................... 13-97
LT1413, Single Supply, Dual Precision Op Amp ...................................................................................................... '9408 2-68
LTC1429, Clock-Synchronized Switched Capacitor-Regulated Voltage Inverter ................................................ 4-41
LTC1430, High Power Step-Down Switching Regulator Controller ... ........................................................... 4-360
LT1431, Programmable Reference .......................................................................................................................... ·9208 7-13
LT1432, 5V High Efficiency Step-Down Switching Regulator Controller .................................................................. '9208 4-145
LT1432-3.3, 3.3V High Efficiency Step-Down Switching Regulator Controller ................................................ 4-137
LTC1443, Low Power Quad Comparator and Reference .....................•..........................................•....... 13-108
LTC1444, Low Power Quad Comparator and Reference ......................................................•................. 13-108
LTC1445, Low Power Quad Comparator and Reference .................................................................•...... 13-108
LTC1451, 12-8it Rail-to-Rail Micropower DAC in SO-8 ............•...................•....................................•...... 6-58
LTC1452, 12-8it Rail-to-Rail Micropower DAC in SO-8 ............•...........................•........................•.......•.. 6-58
LTC1453, 12-8it Rail-to-Rail Micropower DAC in SO-8 ..•..................................................................•...... 6-58
LT1457, Dual, Precision JFET Input Op Amp ........................................................................................................... '9408 2-76
LTC1470, PCMCIA Protected 3.3V!5V Vee Switches ............................................................................... 4-426
LTC1471, Dual PCMCIA Protected 3.3V!5V Vee Switches ................•..........................•............................. 4-426
LTC1472, Protected PCMCIA Vee and VPP Switching Matrix ......... ..............................•............................. 4-437
LTC1477, Protected High-Side Switch ...............................•.............................•....•....•..........•........... 13-112
LTC1478, Dual Protected High-Side Switch ........•.................•.......................•.........................•........... 13-112
LTC1480, 3.3V Ultra-Low Power RS485 Transceiver ...............................•..........................•.................... 5-26
LTC1481, Ultra-Low Power RS485 Transceiver with Shutdown ................................................................... 5-34
LTC1483, Ultra-Low Power RS485 Low EMI Transceiver with Shutdown .........................•............•................. 5-41
LTC1485, Differential BusTransceiver ...................................................................................................................... ·9408 5-166
LTC1487, Ultra-Low Power RS485 with Low EMI, Shutdown and High Input Impedance ......................••.....•....... 5-49
LT1510, Constant-Voltage/Constant-Current 8anery Charger ..............•.....................................•..•...•..•... 13-120
LT1512, SEPIC Constant-Current/Constant-Voltage 8anery Charger .......................................................... 13-130
LT1521, 300mA Low Dropout Regulator with Micropower Quiescent Current and Shutdown ............................•... 4-79
LT1521-3, 300mA Low Dropout Regulator with Micropower Quiescent Current and Shutdown ......•........••..........•.. 4-79
LT1521-3.3, 300mA Low Dropout Regulator with Micropower Quiescent Current and Shutdown ....•........•............. 4-79
LT1521-5, 300mA Low Dropout Regulator with Micropower Quiescent Current and Shutdown ...•....•.......•............. 4-79
LTC1522, 4-Channel, 3V Micropower Sampling 12-8it Serial If0 AID Converter ...................•.............•........•. 13-134
~ote: All products in BOLD are in this Oatabook. others appear in LTC's 1990,1992 and 1994 Oatabooks (,900B = LTC's 1990 Oatabook, '920B = LTC's 1992 Oatabook Supplement
md '940B = LTC's 1994 Oatabook) .

.L7lJ!J~

33

ALPHANUMERIC INDEX
LT1524, Regulating Pulse Width Modulator ......................................;....... ;; ............................................................ '90DB 5-85
LT1525A, Regulating Pulse Width Modulator ..........................................................................................................'90DB . 5-97
LT1526, Regulating Pulse Width Modulator ............................................................................................................'90DB 5-105
LT1527A, Regulating Pulse Width Modulator ..........................................'................................................................ '90DB 5-97
L11528, 3A LQW Dropout Regulator for Microprocessor Applications ........................................................... 4·91
LT1529, 3A Low Dropout Regulator with Micropower Quiescent Current and Shutdown .................................... 4·101
L11529·3.3, 3A Low Dropout Regulator with Micropower Quiescent Current and Shutdown ................................ 4·101
L11529·5, 3A Low Dropout Regulator with Micropower Quiescent Current and Shutdown .................................. 4·101
L11537, Advanced Low Power 5V RS232 Transceiver with Small Capacitors .................................................. 5·18
LTC1550, Low Noise, Switched Capacitor·Rsgulated Voltage Inverter ....................................................... 13·142
LTC1551, Low Noise, Switched Capacitor·Regulated Voltage Inverter ....................................................... 13·142
L11572, 100kHz, 1.25A Switching Regulator with Catch Diode .................................................................. 4·374
LTC1574, High EUiciency Step·Down DC/OC Converl8rwith Internal Schottky Diode ........................................ 4·385
LTC1574·3.3, High EUiciency Step·Down DC/OC Converl8r with Internal Scho"ky Diode ................................... 4·385
LTC1574-5, High EUiciency Step·Down DC/OC Converter with Internal Scho"ky Diode ...................................... 4·385
LT1S80, 7A, Very Low Dropout Regulator ........................... ;.............................................................. 13·148
LT1580·2.5, 7A, Very Low Dropout Regulator .....................................................................................13·148
L11584, 7A Low Dropout Fast Response Positive Regulator Adjustable and Fixed ........................................... 4·112
LT1585, 4.6A Low Dropout Fast Response Positive Regulator Adjustable and Fixed ........................................ 4·112
L11587, 3A Low Dropout Fast Response Positive Regulator Adjustable and Fixed ........................................... 4·112
LT1846, Current Mode PWM Controller .......................................;.......................................................................... '90DB 5-113
LT1847, Current Mode PWM Controller ..................................................................................................................'90DB 5-113
LT3524, Regulating Pulse Width Modulator ............................................................................................................'90DB 5-85
LT3525A, Regulating Pulse Width Modulator ..........................................................................................................'90DB 5-97
LT3526, Regulating Pulse Width Modulator ............................................................................................................'90DB 5-105
LT3527A, Regulating Pulse Width Modulator ..........................................................................................................'90DB 5~97
LT3846, Current Mode PWM Controller .................................................................................................................. '90DB 5-113
LT3847, Current Mode PWM Controller ................................................................;................................................. '90DB 5-113
LTC7541A, Improved Industry Standard CMOS 12-Bit Multiplying DAC ......................................................... 6-69
LTC7543, Improved Industry Standard SBrial12-Bit Multiplying DAC ........................................................... 6-73
LTC7652, Chopper Stabilized Op Amp .....................................................................................................................'90DB 2-197
LTC7660, Switched Capacitor Voltage Converter ..................................................................................................... '90DB
5-9
LTC8043, SBrial12-Bit Multiplying DAC in SO-8 ..................................................................................... 6-80
LTC8143, Improved Industry Standard SBrial12·Bit Multiplying DAC ........................................................... 6-73
LTKOOt, Thermocouple Cold Junction Compensator and Matched Amplifier .......................................................... '90DB 11-3
LTZt 000, Ultra Precision Reference ........................................................................................................................'90DB
3-9
LTZt GaGA, Ultra PreciSion Reference ......................................................................................................................'90DB
3-9
OP-05, Internally Compensated Op Amp .................................................................................................................'90DB 2-321
OP-07, Precision Op Amp .........................................................................................................................................'90DB 2-329
OP-07CS8, Precision Op Amp .................................................................................................................................'90DB 2-337
OP-15, Precision, High Speed JFET Input Op Amp .................................................................................................. '90DB 2-341
OP-16, Precision, High Speed JFET Input Op Amp .................................................................................................. '90DB 2-341
OP-27, Low Noise, Precision Op Amp .....................................................................................................................'90DB 2-345
OP-37, Low Noise, High Speed Op Amp ..................................................................................................................'90DB 2-345
Note: All products in BOLD are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oatabooks ('9008 = LTC's 1990 Oatabook, '9208 = LTC's 1992 Oatabook Supplement

34

ALPHANUMERIC INDEX
OP-215. Dual Precision JFET Input Op Amp ............................................................................................................'900B
OP-227. Dual Matched. Low Noise Op Amp ............................................................................................................'900B
OP-237. Dual High Speed. Low Noise Op Amp ........................................................................................................ '900B
OP-270. Dual Low NOise. Precision Operational Amplifier ....................................................................................... ·920B
OP-470. Quad Low Noise. Precision Operational Amplifier ...................................................................................... ·920B
REF-01. Precision Voltage Reference ....................................................................................................................... '900B
REF-02. Precision Voltage Reference ....................................................................................................................... '900B
SG1524. Regulating Pulse Width Modulator ............................................................................................................ '900B
SG1525A. Regulating Pulse Width Modulator ..........................................................................................................900B
SG1527A. Regulating Pulse Width Modulator ..........................................................................................................900B
SG3524. Regulating Pulse Width Modulator ............................................................................................................ '900B
SG3524S. Regulating Pulse Width Modulator .........................................................................................................'900B
SG3525A. Regulating Pulse Width Modulator ......................................................................................................... '900B
SG3527A. Regulating Pulse Width Modulator ......................................................................................................... '900B

2-275
2-357
2-357
2-120
2-120
3-125
3-125
5-85
5-97
5-97
5-85
5-93
5-97
5-97

Note: All products in BOLD are in this Oatabook, others appear in LTC's 1990,1992 and 1994 Oatabooks ('9008 =LTC's 1990 Oatabook, '9208 =LTC's 1992 Oatabook Supplement
and '9408 = LTC's 1994 Oatabook).

35

NOTES

36

SECTion l-GEnERAl
InFoRmATion

II

1-1

INDEX
SECTION 1-GENERAL INFORMATION
INDEX •...••...•.•••.•..•.••...•••••.••..••..••..••..•••.••....•.•••..••.••.....••..•...•...•..•••.....•••.••..••.••.•.•...•...•...••....•.••. 1·2
GENERAL ORDERING INFORMATION ...•..••••..••...•.••..•...••.•.•.••..•••..•...•.................••..••..•.......•...........••..•.. 1·3
ALTERNATE SOURCE CROSS REFERENCE GUIDE .•••.•..••••...•.••••.•...•••••••..•••.•.••••..••.•••.••••••..•••••....•••••••.•••..• 1·4

1-2

..L7lJ!l~

~7~JDfJl~~~
I.

___G_E_N_ER_~_~_g_~_~_~_~:_~G_N

ORDER ENTRY
Orders for products contained herein should be directed to: LINEAR TECHNOLOGY CORPORATION,
1630 McCarthy Boulevard, Milpitas, California 95035. Phone: 408-432-1900.

II. ORDERING INFORMATION
Minimum order value is $2000.00 per order; minimum value per line item is $1000.00.
Each item must be ordered using the complete part number exactly as listed on the data sheet.
F.O.B.: Milpitas, California.

III. RELIABILITY PROGRAMS
Linear Technology Corporation currently offers the following Reliability Programs:
A. JAN QPL devices.
B. DESC drawings.
C. MIL-STD-883, Level B, latest revision for all military temperature range devices.
D. "R-Flow" Burn-In Program for commercial temperature range devices. Consult Factory regarding burn-in program.

E. Radiation Hardened (RH) products.

IV. PART NUMBER EXPLANATION

XXX

XXXX

X

X

[

J/883B

I

I

s,~;"" to M"-SID-88a, ...'" B, '''''''1 ~;,;"
Package Suffix (see Cross Reference on Page 14-3)
Temperature Range
M for Military
I for Industrial
C for Commercial
X for 200°C Extended Range"

' - - - - - - - - - - - - - Letter indicates electrical grade of part
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Generic or Product Part Number
Designator
LF, LM, OP, REF, and SG are second source devices
LT are improved or proprietary devices
LTC indicates proprietary CMOS devices
RH indicates LTC's radiation hardened devices

V. PACKAGE SUFFIX EXPLANATION
SUFFIX
DESIGNATOR

GENERIC
PACKAGE

PACKAGE DESCRIPTION

D8

SIDE BRAZED

8-Lead Side Brazed Package (Hermetic)

D

SIDE BRAZED

14-,16-,18- and 2D-Lead Side Brazed Package (Hermetic)

F

TSSOP

20-Lead TSSOP, Thin Shrink Small Outline Plastic Package (0.173) Notes 6,7,8

G

SSOP

16-,20-,24- and 28-Lead SSOP, Shrink Small Outline Plastic Package (0.209) Notes 5,6,7,8

GN

SSOP

16-,20- and 24-Lead SSOP, Narrow Body, Shrink Small Outline Plastic Package «1150)

GW

SSOP

36- and 44-Lead SSOP, Wide Body, Shrink Small Outline Plastic Package (0.300) Notes 5, 6, 7, 8

Notes 5, 6, 7, 8
H

"H" is used for Multiple Styles of Metal Cans, as follows:
METAL CAN
METAL CAN
METAL CAN
METAL CAN

8- or 10-Lead TO-5 Metal Can Package

3- or 4-Lead TO-39 Metal Can Package
2-,3- or 4-Lead T0-46 Metal Can Standard Package or in Thermal Caps
3-Lead TO-52 Metal Can Package

1-3

GENERAL ORDERING INFORMATION
SUFFIX
GENERIC
DESIGNATOR PACKAGE

PACKAGE DESCRIPTION

J8

CERDIP

8-Lead CERDIP, Narrow Body, Dual-In-Line Ceramic Package (0.150 Hermetic)

J

CERDIP

14-,16-,18-,20- and 24-Lead CERDIP, Narrow Body, Dual-In-Line Ceramic Package
(0.300 Hermetic)

JW

CERDIP

28-Lead CERDIP, Wide Body, Dual-In-Line Ceramic Package (0.600 Hermetic)

K

TO-3

3-Lead TO-3, Transistor Outline Metal Can Package

L

LCC

20-Pin LCC, Rectangular Shaped, Leadless Chip Carrier Package (Hermetic)

LS

LCC

20-Pin LCC, Square Shaped, Leadless Chip Carrier Package (Hermetic)

M

DD Pak

3-Lead DD Pak, Plastic Package Notes 6, 7, 8

N8

PDIP

8-Lead PDIP, Narrow Body, Dual-In-Line Plastic Package (0.300) Notes 6, 7,8

N

PDIP

14-,16-,18-,20- and 24-Lead PDIP, Narrow Body, Dual-In-Line Plastic Package
(0.300) Notes 6, 7, 8

NW

PDIP

28-Lead PDIP, Wide Body, Dual-In-Line Plastic Package (0.600) Notes 6, 7,8

P

TO-3P

3-Lead TO-3P, Transistor Outline Plastic Package (Similar to a TO-247) Notes 6, 7,8

Q

DDPak

5-Lead DD Pak, Plastic Package Notes 6, 7, 8

R

DDPak

7-Lead DD Pak, Plastic Package Notes 6, 7, 8

S8

SO

8-Lead SO, Narrow Body, Small Outline Plastic Package (0.150) Notes 3, 6, 7, 8

S

SO

14- and 16-Lead SO, Narrow Body, Small Outline Plastic Package (0.150)
Notes 1,2,6,7,8

SW

SO

16-, 18-, 20-, 24-, and 28-Lead SO, Wide Body, Small Outline Plastic Package (0.300)
Notes 1,2,6,7,8

ST

SOT-223

3-Lead SOT-223, Small Outline Transistor Plastic Package Notes 6,7,8

T

TO-220

3- or 5-Lead TO-220, Transistor Outline Plastic Package Notes 4, 6, 7, 8

T7

TO-220

7-Lead TO-220, Transistor Outline Plastic Package (Formerly "Y" Pkg.) Notes 4, 6, 7, 8

W

FLATPAK

10-Lead FLATPAK, Glass Sealed Package (Hermetic)

WB

FLATPAK

10- or 14-Lead FLATPAK, Metal Sealed, Bottom Brazed Package (Hermetic)

Z

TO-92

3-Lead TO-92, Transistor Outline Plastic Package Notes 6, 7, 8

(All Dimensions Shown In Inches)
Note 1: 16-Lead SO (Small Outline) package is delivered in either narrow (0.150) or wide body (0.300) package styles depending on the device die size.
See specific data sheet for pin counts and package dimensions.
Note 2: lB-, 20-,24- and 2B-Lead SO (Small Outline) packages are wide body styles (0.300).
Note 3: Pinout and electrical specifications on SB (B-Lead Small Outline) package may differ from a standard commercial grade NB package.
See SO (Small Outline) data sheets for specific information.
Note 4: SPECIAL FLOW Lead Form Configurations (trimmed andlor formed) are available for TO-220 packages. See "1'0-220 Lead Bend Options" in the
back of Section 14 or consutt Factory for details.
Note 5: SSOP Shrink Small Outline Packages vary in lead pitch. G =0.0256, GN =0.0250, GW =0.03150.
Note 6: FLAMMABILITY RATING: All plastic packages supplied by LTC have obtained Underwriters Laboratories'
Flame Retardancy Certification Rating of UL94V-0.
Note 7: TOXIC MATERIALS: Molding compounds used by our assembly subcontractors do not contain toxic materials known as; Polybrominated
Biphenyls (PBB), Polybrorninated Biphenyl Ether (PBBE) or Polybrominated Biphenyl Oxide (PBBO).
Note 8: OXYGEN INDEX: All plastic packages supplied by LTC have an oxygen index of 2B% minimum.

1-4

£.YLlnfJ\

.r\

ALTERNATE SOURCE CROSS
REFERENCE GUIDE
TECHNOLO.,.....GY--.............................................
~

PIN

LTC DIRECT REPL PIN

LTC DIRECT REPL PIN

AD101A
AD232
AD23S
AD237
AD238
AD239
AD241
AD381
ADS10
ADS17
ADS18

LM101A
LT1081'
LTl130A"
LTl138A"
LTl139A"
LTl137A"
LTl137A"
LT1022"
LT100l'
LT100l"
LMl18"
LTl18A"
LTll0l"
LT1088"
LT580
LT581
LT1031"
LT1027'
LT1034"
LT1088"
LT1088"
LT105?"
LT105?"
LTll14'
LT1097
LTll12'
LT1097
LT1056"
LT1057"
LT1058"
LT1088"
LT108S"
LTll13'
LTl122
LT1016"
LT12S2"
LT1252"
LT1260"
LT1360'
LT1363
LT1006"
LTl169'
LT1014"
LT1361'
LT1229"
LT1364'
LT1222"
LT1220"
LT1221"
LT1223"
LTl122
LT1223"
LT1360
LTl192"
LT1226
LTl192
LTC1410"
LT1318"
LTC7S41A'
LTC7S41A'
LTC7S43'
LTC1272"
LTC109l"
LTC1092"
LTC1099'
LTC1096!
LTC109S"
LTC1275"
LTC1273"
LTC1276"
LTC1282"
LTC1290"
LTC1278-S"

LTC1279"
LTC14S3"
LT1223
LT1223
LT1016"
LTC1099'
LTC1098'
LTCl198"
LTCl196
LTC1091"
LTC1093"
LTC1094"
LTC1410"
LTC201A
LTC202
LTC221
LTC222
LTC1276"
LTC1293"
LTC1272-8"
LTC1410"
LTC1410"
LTC1279"
LT122?"
LT1252
LT1230
LT122?"
LT1228"
LT1203"
LT10ll"
LT10ll"
LTC8043'
LTC8143'
LTC1451"
LTC201
LTC202
LTC1390"
LTC1232
LT1331"
LTC485'
LT1229'
LT1223'
LT1220
LT1221
LT1223
LT1222
LT1222
LT1222
LT1220
LT12S2"
LT1363'
LT1228"
LT1228"
LT1206"
LTl191"
LT1223"
LT1227"
LT122?"
LT1361'
LT1364'
LT1229"
LT120S"
LT1229"
LT1229"
LT135S'
LT1361'
LT1364'
LT1229
LT1362'
LT1365'
LT1362
LT12S4"
LT1230
LT1228"

ADS24
AD536
AD580
AD581
AD586
AD589
AD636
AD637
AD642
AD647
AD704
AD705
AD706
AD707
AD711
AD712
AD713
AD736
AD737
AD743
AD744
AD790
AD810
AD811
AD813
AD817
A0818
A0821
A0822
A0824
AD826
AD827
A0828
AD840
A0841
AD842
AD844
AD845
AD846
AD847
AD848
AD849
AD1671
AD7306
AD7S41
AD7S41A
AD7543
AD7S72
AD7S79
AD7580
AD7820
AD7821
AD7870
AD7875
AD7876
AD7883
AD7890
AD7892-l,2

AD7892-3
AD8300
AD9617
AD9618
AD9686
ADC0820
ADC0832
ADC08061
ADC08231
ADC1031
ADC1034
ADC1038
ADC12062
ADG201A
ADG202
ADG221
ADG222
ADS7800
ADS7803
ADS7804
ADS7810
ADS7819
BT8920
CLC406
CLC414
CLC415
CLC430
CLC520
CLC532
CMPOl
CMP02
DAC8043
DAC8143
DAC8512
DG201A
DG202
DGS08-X
DS1232
OS14C33S
OS369S
EL1224
EL2020
EL2028
EL2029
EL2030
EL2038
EL2039
EL2040
EL2041
EL2044
EL204S
EL2082
EL2090
EL2099
EL2120
EL2l30
EL2210
EL22ll
EL2224
EL2232
EL2242
EL2244
EL224S
EL2260
EL2410
EL24ll
EL2444
EL244S
EL2460
EL4089

EL4393
EL4441
EL4094!S
GT4123
GY41 02
GX4314
HA2S00
HA2S02
HA2S0S
HA2S10
HA2S12
HA2515
HA2S20
HA2S41
HA2S44
HA5004
HA5130-2
HA5130-5
HAS135-2
HA5135-5
HAOP07
HAOP07A
HAOP07C
HAOP07E
HIS08-X
HIS810
ICL232
ICL76S0
ICL7652
ICL7660
ICL7662
ICL8069C
ICL8069M
IS0150
LF400
LF400A
LHOO02
LH0044
LH0070
LH2l08
LH2l08A
LM10
LM10B
LM10C
LM399
LM399A
LM399A-20
LM399A-50
LM2S74
LM2S75
LM2S75N
LM2S76
LM2S77
LM2S87
LM2935

LTC DIRECT REPL PIN
LT1260"
LT1204"
LT12S6"
LT12S6"
LT1203"
LT120S"
LT1220
LT1220
LT1220
LTl18A"
LMl18"
LTl18A"
LMl18A"
LT318A"
LM318"
LT1220
LT1220
LT1224
LT1223
OP07A
LT1001AM'
OP07E
LT1001C'
OP07
LT1001M'
OP07C
LT1001C'
OP07
LT1001M'
OP07A
LT1001AM'
OP07C
LT1001C'
OP07E
LT1001C'
LTC1390"
LTC1272-8
LT1081
LTC 1050'
LTC1052"
LTC7652
LTC10S2'
LTC1044'
LTC 1054"
LTCl144'
LM385-1.2
LTl 004C-1.2'
LM18S-1.2
LTl004M-1.2'
LTCl145"
LTl122DC
LTl122CC
LTl122BC
LTl122AC
LT1010M"
LT1001M'
LH0070
LT1031M'
LH2l08
LH2108A
LM10
LM10B
LM10C
LM399
LM399A
LM399A-20
LM399A-SO
LTl176
LT1076"
LTl176
LT1074"
LT107l"
LTl170
LT1005"

LM2940
LM6181
LM6218
LM6361
LP29S0-S
LP29S1
IlA96172
IlA96174
IlA96176
MAX120
MAX122
MAX1S3
MAX162
MAX163
MAX164
MAX165
MAX167
MAX172
MAX202
MAX207
MAX211
MAX212
MAX213
MAX220
MAX222
MAX223
MAX232A
MAX235A
MAX237A
MAX238A
MAX239A
MAX241A
MAX242
MAX280
MAX281
MAX400
MAX420
MAX422
MAX430
MAX432
MAX441
MAX442
MAX4S4
MAX467
MAX478
MAX479
MAX480
MAX481
MAX48S
MAX487
MAX492
MAXS38
MAXS39
MAXS43
MAXS60
MAXS61
MAXS63
MAX603
MAX604
MAX6l3
MAX6l4
MAX630
MAX631
MAX632
MAX633
MAX634
MAX63S
MAX636
MAX637
MAX638
MAX639

LTC DIRECT REPL
LT1086"
LT1227"
LT1203"
LTl19S"
LTll17-S"
LTl121"
LTC486
LTC487
LTC48S
LT1278-S"
LTC1276"
LTCl198"
LTC1273'
LTC1273'
LTC1275'
LTCl198"
LTC127S"
LTC1272'
LT1381'
LTl138A"
LTC133?"
LTC1348"
LTC1349"
LT1281A"
LT1280A'
LT1237
LT1281A'
LTl130A"
LTl138A"
LTl139A"
LTl137A"
LTl136A"
LTl137A"
LTC1384'
LTC1062
LTC1065"
LT100l
LTCllS0'
LTCllS0"
LTCllS0
LTCllS0"
LT1204"
LT120S"
LT1204"
LT1260"
LTl178
LTl179
LT1077'
LTC1481
LTC48S
LTC148r
LT1366"
LTC1452
LTC1452
LTC8043'
LT1331"
LTC1327"
LTC1386'
LTll29-S"
LTl129-3.3"
LT1313"
LT131S"
LT13l2"
LT13l4"
LTll73"
LTl173-5"
LTl173-l2"
LTl173"
LTll73"
LTl173-S"
LTl173-l2"
LTl173"
LTl173-S"
LTCl174'

•

*LTC Improved Replacement: 100% Pin-for-pin compatible with better electrical specifications.
**Similar Device: Please consult the data sheet to determine the suitability of the replacement for specific applications.

1-5

ALTERNATE SOURCE CROSS REFERENCE GUIDE
PIN

LTC DIRECT REPL PIN

LTC DIRECT REPL PIN

LTC DIRECT REPL PIN

MAX640
MAX641
MAX642
MAX643
MAX649
MAX6S1
MAX652
MAX654
MAX65S
MAX656
MAX6S7
MAX6S8
MAX6S9
MAX660
MAX662
MAX667
MAX680
MAX690
MAX691
MAX692
MAX693
MAX694
MAX69S
MAX699
MAX724
MAX726
MAX741D
MAX741U
MAX7S6
MAX757
MAX761
MAX786
MAX8S0
MAX8Sl
MAX852
MAX853
MAX8S6
MAX873
MAX87S

LTCl174-3.3
LT1173-S"
LTl173-12"
LTCl147
LTCl147-S"
LTCl147-3.3"
LTCl147"
LT1073-S
LTl173-S"
LT1073-S"
LT1073"
LT1108-S"
LT1108-S"
LTC660
LTC1262'
LTl129"
LT1026
LTC690
LTC691
LTC692'
LTC693'
LTC694
LTC69S
LTC699
LT1074
LT1076
LTCl147"
LTCl266"
LT1304"
LT1304"
LTl309"
LTC1267"
LTC1SS0"
LTCl55l"
LTC1SS0/Sl"
LTC1SS0"
LT1303"
LT1019-2.S
LT10l9-S
LT102l-S
LT1027
LT10l9-l0
LT102l-l0
LT1S2l-3.3"
LT1S2l-S"
LT1S2l-3.3"
LTC1044A
LTC1232
LTCl147-S"
LTCll47-3.3"
LTl17017l"
LT1016
LM323T
LT323AT'
LT1019CN8-2.5"
LT1 019CN8-S"
LTl019CN8-l0"
LT1019CN8-2.S'
LTl019CN8-S'
LT10l9CN8-l0'
LT10l3M'
LTC488'
LTC487'
LT1039-l6'
LT1074
LTC10S9'
LTC 1060
LTC1060'
LT1312"
LT1313"
LTC1472"
LT1073"
LT1110"

LTl182"
LTl183"
LT1182"
LTl183"
LTC7S41A'
LTC7S41A'
LTC1272'
LTC1099'
LT1001A
LT1097
LT1216"
LT1252
LT1227"
LT1013
LT1211
LT1169"
LTl169"
LTl124"
LTll22'
LT1001
LT1097'
LT1012
LT1097'
LT1001
LT1002
OP21S
LT10S7
LT1078'
LT1013'
OP227
OP270
LTl124'
LT1078"
LT1366"
LTll12'
LT10l4'
LTlll4'
LT1079'
LT1014'
LT13S9'
OP470
LT1l2S'
LT1079"
LTlll4'
LT1008
LT1012
LT1013M'
LH2l08
LH2l08A
REFOl
LT10l9-l0'
LT102l-l0"
REF02
LT10l9-S'
LT102l-S"
LT1019-2.S'
LT1 019A-2.S'
LT1019-l0
LTl 021-1 0
LT10l9-l0
LTl 021-1 0
LT10l9-2.S"
LT1236"
LTll17-2.8S
SG1S24
LT1S24'
SG1S2SA
LT1S2SA'
SG1S27A
LT1S27A'
LTC1470"
LTC1471"
LT1313"

LTC131S"
LTC1472"
LTC1314"
LTC131S"
LTC1472"
LTC1472"

MAX876
MAX882
MAX883
MAX884
MAX1044
MAX1232
MAX1649
MAX16Sl
MAXl77l
MAX9686
MC78TOS
MC1400AU2
MC1400AUS
MC1400AU10
MC1400U2
MCl400US
MC1400Ul0
MC1SS8
MC3486
MC3487
MC145406
MC34166
MFS
MF10
MIC2SS7
MIC2SS8
MIC2S60
ML4861

ML4864
ML4876
MX7S41
MX7541 A
MX7S72
MX7820
OPAl77
OPA404
OPA603
OPA620
OPA1013
OPA2107
OPA2111
OPA2604
OP42
OP77
OP97
OP177
OP207
OP21S
OP220
OP221
OP227
OP270
OP290
OP291
OP297
OP400
OP420
OP421
OP467
OP470
OP490
OP497
PM1008
PM1012
PM1SS8
PM2l08
PM2l08A
REFOl
REF02
REF03
REF43
REF10l
REF102
REF192
REF19S
REGll17
SG1S24
SG1S2SA
SG1S27A
Si9706
Si9707
Si9710

Si9711
SI9712
SN7S172
SN7S173
SN7S174
SNS717S
SN7S176
SN7S179B
SN7SALS/80
SN7S186
SP301
SP302
TL431 A
LT1431A
TLC2S43
TPS2010
TPS2011
TPS2012
TPS2013
TSC04
TSCOS
TSC170
TSCl71
TSC232
TSC911
TSC913
TSC9l4
TSC9l8
TSC962
TSC76S0
TSC76S2
TSC7660
TSC9491
TSC949S
TSC9496
UCll7
UC137
UC1S0
UC3l7
UC337
UC3S0
UC1S24
UC1S2SA
UC1S27A
UC1846
UCl847
XRT3S88/89

LTC DIRECT REPL

LTC486'
LTC488"
LTC487'
LTC489"
LTC48S'
LTC490'
LTC491,
LTl134"
LTC1321,
LTC1322'
LT1431,
LTl431
LTC1296
LTC1477"
LTC1477"
LTC1477"
LTC1477"
LT1004-1.2
LT1004-2.S
LT3846"
LT3847"
LT1080"
LT1081"
LTC10S0'
LT1078"
LTC10S1'
LT1079"
LTC10S3'
LTC76S2"
LTC 1046"
LTC10S0'
LTC76S2
LTC10S2
LTC 1044'
LT1004-l.2
REF02
LT1019M-S
LT102l-S"
REFOl
LT102l-l0"
LMl17
LTll7A'
LM137
LT137A'
LT1033M"
LM1S0
LT1S0A'
LM3l7
LT317A'
LM337
LT337A'
LT1033C"
LM3S0
LT3S0A'
SG1S24
LT1S24'
SG1S2SA
LT1S2SA'
SG1S27A
LT1S27A'
LT1846
LTl847
LTC1345"

, LTC Improved Replacement: 100% Pin-lor-pin compatible with better electrical specifications.
"Similar Device: Please consuft the data sheet to detennine the suitability of the replacement lor specific applications.

1-6

~7lJn~

SECTion 2-AmPLIFIERS

II

2-1

INDEX
SECTION 2-AMPLIFIERS
INDEX .•••.....•..•....•.•...•...•••..••...•.....••...•...••....•.•......•....•.......••.............••.......•...•.•...••...••.•....•.•....•. 2-2
SELECTION GUIDES .••...••....•...•....••.........•....•........•....•...•........•.....•.......•....•...••....••..•••...•.......•....•••. 2-3
PROPRIETARY PRODUCTS
PRECISION OPERATIONAL AMPLIFIERS .•••••••••.••••.•••...••••••...••.....•.•...........•.••••.•.........•...••...•.........•.... 2-13
LT1366/LT1367/LT1368/LT1369, Dual and Quad Precision Rail-to-Raillnput and Output Op Amps ....•............••. 2-14
HIGH SPEED OPERATIONAL AMPLIFIERS ............................................................................................ 2-33
LT1311, Quad 12MHz, 145ns Settling Precision Current-to-Voltage Converterfor Optical Disk Drives ................ 2~34
ZERO-DRIFT OPERATIONAL AMPLIFIERS ..••..••......................••....••..••••..••.•••.••••.••.•••••••..••.••.....•.••....••• 2-41
LTC1152, Rail-to-Raillnput Rail-to-Rail Output Zero-Orin Op Amp ......................................................... 2-42

2-2

I

I

OPAMPS

HPrecision

I~Dual Supply~ I

I
LowlB

Low Vas I

H Zero Drift J

--t Zero Drift J

LTC1047 (0, 10~V)
LTC1049 (5, lO~V)
LTC1050 (5, 5~V)
LTC1051 (0, 5~V)
LTC1052 (5, 5~V)
LTC1053 (a, 5~V)
LTC1150 (5, 5~V)
LTC1151 (0, 5~V)
LTC1152 (5, 10~V)
LTC1250 (5, 10~V)

LTC1047 (0, 50pA)
LTC1049 (5, 50pA)
LTC1050 (5, 30pA)
LTC1051 (0,50pA)
LTC1052 (5, 30pA)
LTC1053 (a, 50pA)
LTCl150 (5, 100pA)
LTCl151 (0, 100pA)
LTC1152 (5, 100pA)

Y

Bipolar

LTl001 (5, 25~V)
LTl002 (0, 60~V)
LT1 006 (5, 50~V)
LT1007 (5, 25~V)
LT1008 (5, 120~V)
LT1012 (5, 25~V)
LT1024 (0, 50~V)
LTl028 (5, 40~V)

-1

I

LTlOn(S,40~V)

I

Single or Duall
Supplies

LT1 006 (5, 520~)
LTl013 (0, 1mA)
LTl014 (a, 2mA)
LTC1047 (S, 55~)
LTC1049 (5, 300~)
LT1 on (5, 60~)

I

LT1078 (0, 1oo~)
LT1079 (a, 200~A)
LTl178 (0, 36~)
LTl179 (0.72~)
LT1413 (0, 330~)

Low Vas
Low Power

I

Fast Slew Rate
Fast Settling

LT1122 (5, 80VliJ.S)
LT1187 (5, 165V1iJ.S)
LT1189 (5, 165V1iJ.S)
LT1190 (5, 450VliJ.S)
LT1191 (5, 450Vl~s)
LTl192 (5, 450VliJ.S)
LTl193 (5, 5OOVliJ.S)
LTll94 (5, 5OOVl~s)
LT1195 (5, 165V1~s)
LT1200 (5, 50Vl~s)
LTl201 (0,50VliJ.S)
LT1202 (a, 50VliJ.S)
LT1204 (5, 1000VliJ.S)·
LTl206 (5, 900Vl~s)'
LT1208 (0, 400VliJ.S)
LTl209 (a, 400VliJ.S)
LT1215 (0, 5OVliJ.S)
LT1216 (a, 50VliJ.S)
LT1217 (5, 500VliJ.S)·
LTl220 (5, 250VliJ.S)
LT1221 (5, 250Vl~s)
LT1222 (5, 200Vl~s)
LT1223 (5, 100OV/iJ.Sl'

I

LT1224 (5, 400Vl~s)
LT1225 (5, 400VliJ.S)
LT1226 (5, 400VliJ.S)
LT1227 (5, llooVliJ.S)·
LT1229 (0, 1000VliJ.S)·
LT1230 (a, 1000VliJ.S)·
LTl252 (5, 250VliJ.Sl'
LTl253 (0, 250Vl~s)'
LT1254 (a, 250VliJ.S)·
LT1259 (0, 160OV/iJ.S)·
LT1260 (T, 1600VliJ.S)·
LT1354 (5, 400VliJ.S)
LT13S5 (0, 400Vl~s)
LTl3S6 (a, 4OOVI~s)
LTl3S7 (5, 600VliJ.S)
LT13S8 (0, 6ooVliJ.S)
LTl3S9 (a, 600VliJ.S)
LTl360 (5, 800Vl~s)
LTl361 (0,8ooVliJ.S)
LT1362 (a, 8ooVliJ.S)
LTl363 (5, 10ooVliJ.S)
LTl364 (0, 1000Vl~s)
LT1365 (a, 1000Vl~s)

Ylnstrumentation ~

I

I

I

I Low Noise I

I Large AVOL I

LT1007 (S, 3.8nVl'I'Hz)
LT1028 (5, 1.lnVl'I'Hz)
LT1 037 (5, 3.8nVl'I'Hz)
LTll13 (0, 6nVl4llz
LT1115 (5, 1.lnVl~
LT1124 (0, 4.2nVl Hz)
LTl125 (a, 4.2nVl~
LT1126 (0, 4.2nVl~
LT1127 (a, 4.2nVl Hz)
LTl128 (5, 1.lnVl'I'Hz)

LT1006 (S, 1M)
LT1 007 (5, 7M)
LT1 012 (5, 3OOk)
LT1013 (0, 1.5M)
LTl 014 (a, 1.5M)
LTl 028 (5, 7M)
LT1037 (5, 7M)
LTC1049 (5, 3M)
LTC1050 (5, 3M)
LTC1051 (0, 1M)
LTC1052 (5, 3M)
LTC1053 (a, 1M)
LT1
(5, 1M)
LT1078 (0, 1M)

on

I

I

Low Vas
Micropower

II
I I

LTC1047 (0, l~V, 55~)
LT10n (5, 40~V,60~)
LTl078 (0, 70~V, 100~)
LT1079 (a, 100~V, 200~)
LT1178 (0, 70~V,36~)
LT1179 (a, 100~V, 72~)

I
LowSpeed
Vas
High

II

LTl211 (0, 150~V, 14MHz)
LTl212 (a, 275~V, 14MHz)
LTl213 (0, 15~V, 28MHz)
LTl214 (a, 275~V, 28MHz)
LT1215 (0, 300~V, 23MHz)
LT1216 (a, 450~V, 23MHz)

I

I

I

Video

I Non-Video I

I Low Power I

LT1220 (5, 45MHz)
LT1221 (5, 37MHz)
LT1222 (5, 50MHz)
LTl224 (5, 45MHz)
LT1225 (5, 30MHz)
LT1226 (5, 40MHz)
LT1208 (0, 45MHz)
LTl209 (a, 45MHz)
LT1358 (0, 25M Hz)
LT1359 (a, 25M Hz)

LT1200 (5, lmA. 10MHz)
LT1201 (0, lmA, l1MHz)
LTl202 (a, 1mA, llMHz)
LT1217 (5, lmA, 10MHz)'
LT1354 (5, lmA, 12MHz)
LTl355 (0, lmA.12MHz)
LTl356 (a, lmA, 12MHz)

LT1187 (5, 5OMHz)
LT1189 (5, 35MHz)
LT1190 (5, 50MHz)
LT1191 (S,90MHz)
LT1192 (5, 40MHz)
LT1193 (5, 70MHz)
LT1194 (5, 40MHz)
LT1195 (5, 5OMHz)
LT1204 (5, 70MHz)'
LT1206 (5, 60MHz)'
LTl223 (5, l00MHz)'
LTl227 (5, 140MHz)'
LT1229 (0, 100MHz)'

LT1079 (a, 1M)
LT1 097 (5, 700k)
LT1112 (0, 5M)
LT1113 (0, 1.2M)
LT1114 (a, 5M)
LTll15 (5, 7M)
LTl124 (0, 5M)
LTl125 (a, 5M)
LTl126 (0, 5M)
LTl127 (0, 5M)
LTl128 (5, 7M)
LTCl152 (5, 3M)
LT1169 (0, 1.2M)
LT1413 (0, 1.5M)

LTl097 (5, 250pA)
LT1112 (0, 180pA)
LT1113 (0, 320pA)
LTll14 (a, 180pA)
LT1122 (5, 75pA)
LTl169 (5, 20pA)
LT1457 (0, 75pA)

I I

LT1006 (5, 50~V, 520~)
LTl013 (0, 150~V,lmA)
LT1014 (a, 180~V, 2mA)
LTC1049 (S, 10~V, 300~)
LT1112 (0, 60~V, 800~A)
LT1114 (a, 60~V, 1.6mA)
LTC1152 (5, 10~V, 2.2mA)
LT1413 (0, 280~V, 0.9~)

c.jLow powefrl Wide Bandwidth

Bipolar

LT1008 (5, 100pA)
LTl012 (5, 100pA)
LT1 022 (5, 50pA)
LTl024 (0, 120pA)
LTl055 (5, 50pA)
LT1 056 (5, 50pA)
LT1057 (0, 50pA)
LTl058 (a, 50pA)

LTl078 (5, 40~V)
LT1079 (0.70~V)
LT1097 (5, 50~V)
LT1112 (0, 60~V)
LT1114 (a, 60~V)
LTl124 (0, 70~V)
LT1125 (a, 100~V)
LT1413 (0, 60~V)

~ Single Supply
c.jLowPower

I

I

LT1230 (a, looMHz),
LT1252 (5, 100MHz),
LTl253 (0, 9OMHz)'
LTl254 (a, 90MHz)'
LT1259 (0, 130MHz),
LT1260 (T, 130MHz)'
Lm60 (5, 50MHz)
LTl361 (0,50MHz)
LT1362 (a, 50MHz)
LT1363 (5, 70MHz)
LT1364 (0, 70MHz)
LT1365 (a, 70MHz)

I
Rail-to-Rail
In/Out
Precision
LTCl152
LT136617
LTl36819

I

*Current feedback ampltfier

I

I

I

IMlcropower I

I Zero Drift I

High Speed I

LTll01

LTClloo

LT1102

2-3

HIGH SPEED AMPLIFIERS

HIGH SPEED

•
Color, WW Video and Multimedia

Instrumentation and Data Acquisition
• Fast DAC Amplifiers
• Signal Processing
• RF Amplification

r-

•
•
•
•

• RADAR
• Fiber-Optic Systems
• Copiers/Laser Printers

Frame Grabbers
Video Cable Drivers
Video MUXs
Cable Tappers

Dual Supplies,
Largest Bandwidth

LOWEs! ollsets,.
Fastest Slew Rate,
Lowest Bias Current - - - Fastest Settling ~

•
•
•
•

~

±5V, or Single 5V
Supplies, Lowest Cost

Single Supply, DC Precision

NEW AMPLIFIER ARCHITECTURE!

• Low Vas with High Bandwidth/Slew Rate
(150ILV Max, A-Grades)
• Single Supply 3.3V, 5Vor Dual ±15V
Operation
• Low Power (1.3mAlAmp): LT1211!12
• Fast Settling to 0.01 %, 250ns, 2V Step:
LT1215/16
• SO-8 (Duals) and 0.150" SO-16 (Ouads)

Voltage Feedback Op Amps with
Current Feedback Speed

LT1211 (0)
LT1212 (0)
LT1213 (0)
LT1214 (0)
LT1215 (0)
LT1216 (0)

GBW
(Typ)
MHz
14
14
28
28
23
23

SR
Vos
(Typ) (Max)
V/ILS
ILV
7 150/275
7
275
12 150/275
12
275
50 300/450
50
450

I
Voltage Feedback Op Amps
• 12-BitAccurate: LT1220/21/22
• 1o-Bit Accurate: LT1224/25/26
• C-Load: Drives Unlimited Capacitive
Loads

LT1220
LT1221
LT1222
L11224
LT1225
L11226

Av
(Min)
VN
1
4
10
1
5
25

0.1%
GBW Settling SR Vos
(Typ) Time (Typ) (Max)
MHz ns
V/1iS mV
45
75
250 1.0
150
65
250 0.6
200 0.3
500
75
400 2.0
45
90
150
90
400 1.0
1000 100 400 1.0

(D) = Dual, (0) = Ouad
C-Load is atrademark of Linear Technology Corporation

2-4

Video Gain Blocks
Building Security
Image Recognition
Video Keyer/Fader

• Low Supply CurrenVAmplifier (1 mAl: LT1355/6
• Very High Slew Rate (1000VlIiS): LT1363
• Low Vas (0.6mV Maximum): LT1358/9
• Low Power (6mAlAmplifier for 1000VlliS Slew Rate)
• Fast Settling (80ns to 0.01%, 50ns to 0.1%, lOV Step)
• C-Load™: Drives Unlimited Capacitive Loads
Single
LT1354
LT1357
LT1360
LT1363

Dual
LT1355
LT1358
LT1361
LT1364

Ouad
LT1356
LT1359
LT1362
LT1365

GBW
MHz
12
25
50
70

SR
VIliS
400
600
800
1000

Is/Amp
(mA)
1
2
4
6

i i
Current Feedback Amps
• Bandwidth Independent of Gain
• "Shutdown" Feature: lT1217, LT1223,
lT1227.
• Single Supply Operation/Best for Video:
lT1227, lT1229, LT1230.
.~ 12-BitAccurate: lT1223
• low Power (Is = 1mAl: LT1217
• lowest Cost: l T1252/3/4
• Operates on ±2V to ±15V Supplies'

Low Cost Video Op Amps
• Specified Ope ratio n with ±5V and Single
5V Supplies
• Color Video Perto rmance
• "Shutdown" Featu re: LT1190/1/2
• Directly Drives Ca bles: 50mA lOUT
• 450VlliS Slew Rate
• low Power: l T11 95

• LT1223 & LT1217 Min Supply Vol1age = ±5V

L11227
l11223
LT1229 (D)
lT1230 (0)
LT1217
L11252
L11253 (D)
L11254 (0)

BW
(Typ)
MHz
140
100
100
100
10
100
90
90

SR
(Typ)
VIliS
1100
1300
1000
1000
500
250
250
250

Vos
(Max)
mV
10
3
10
10
3
15
15
15

LT1190
lT1191
lT1192
lT1195

GBW
. (Typ)
MHz
50
90
350
50

SR
(Typ)
VlfJS
450
450
450
165

Av
(Min)
VN
1
1
5
1

VIDEO AND MULTIMEDIA PRODUCTS
Video Products
In addition to high speed amplifiers, LTC offers the following products tailored to video, multimedia and computer graphics applications.

Low Cost Dual/Triple 130MHz
CFAs with Shutdown
• LT1260: Triple CFA for RGB Video
• LT1259: Dual CFA with Shutdown
• 90MHz Bandwidth on ±5V
• 0.1dB Gain Flatness, 30MHz: Good for HDTV
• 1600Vl!JS Slew Rate
• ±2V to ±15V Supply Range
• 100ns/40ns Turn On/Off Times
• Makes 2 or 3 Input MUX Amp
• Low Supply Current (5mNAmp)
• Narrow SO Packages

±5V Video Difference Amps
• 50dB CMRR@ 10MHz
• Input Voltage Range: (-2.5V to 3.5V)
• ±4V Output Voltage Swing
• Color Video Performance
• "Shutdown" Feature
• Can Directly Drive Cables
• 500Vl!JS Slew Rate: LT11 93/LT1194
• Low Power: LT1187/LT1189
BW
Av
(Min)
(Typ)
VN
Gain
MHz
Adj.
LT1187
2
50
Adj.
LT1189
10
35
Adj.
LT1193
2
70
LT1194
Fixed
10
350

Video Distribution Amplifier
• LT1206: 250mA Minimum Output Current

4:1 Video Multiplexer with 75MHz
Current Feedback Amplifier

• 60MHz, 900V/!JS Current Feedback Amplifier
• Drives Ten 150n Video Cables
• Drives Low Impedances and High
Capacitances
• Color Video Performance
• Low Current "Shutdown" Mode Available

•
•
•
•
•
•
•

LT1204: 4:1 MUX w/ Current Feedback Amp
0.1dB Gain Flatness to >30MHz: for HDTV
1000V/!JS Slew Rate
75MHz, -3dB Bandwidth (Av = 2)
90dB Channel Separation
Expandable
16-Pin PDIP and SW Packages

2:1 and 4:1 Video Multiplexers
Very Fast for Pixel Switching
•
•
•
•
•
•
•
•
•

LT1203 (2:1), LT1205 (2 x 2:1 or 4:1)
150MHz, -3dB Bandwidth
90dB Channel Separation
30M Hz, 0.1dB Gain Flatness (HDTV)
25ns Channel Switching Time
50mV Switching Transient
1OMn Disabled Output Impedance
Expandable
8- and 16-Pin Narrow SO Packages

Current Feedback Amp with
DC Gain Control
• LT1228: 75MHz Transconductance Amp
with 1OOMHz Current Feedback Amplifier
• Color Video Performance
• Differential Input
• Operates on ±2V to ±15V Supplies
• For Auto-Gain, Tunable Filters, and
Specialized Video Circuits.

Video Fader/Gain-Controlled
Amplifier
• LT1251: 40MHz Video Fader
• LT1256: 40MHz Gain-Controlled Amplifier
• Accurate 1% Linear Gain Control
• Low Differential Gain/Phase, 0.1 %/0.1 0
• 14-Pin PDIP and SO Packages

Multimedia
Multimedia systems combine audio, composite video (broadcast quality TV) and high resolution computer graphics.
Typical requirements are'

Video: NTse or PAL need minimum 50MHz, -3dB bandwidth
HDTV needs 0.1 dB flatness to 30MHz
Suggested Products (Refer to above and reverse side):
General Purpose
LT1360/61 /62/63/64/65: Single/Dual/Quad Voltage
Gain BlocksNideo
Feedback Op Amps with Current Feedback Speed
AID Bullers
LT1227/29/30: Single/Dual/Quad Current
Feedback Amplifiers
LT1252/3/4: Low Cost Current Feedback Amplifiers
Multiplexer
LT1204: 4:1 Video MUX with CFA
Video Distribution
LT1206: 250mA Output Current CFA
DC Restoration
LT1228: CFA with Gain Control
Gain Control
COAX Loopthrough/
Twisted-Pair Receiver

LT1228: CFA with Gain Control, LT1256: 40MHz
Amplifier with DC Gain Control
LT1187/89/93/94: Video Difference Amplifiers

Graphics: VGA needs

>50MHz, 19" monitors need >100MHz

RGB, YUV, YC, Amps

LT1259/60: DuallTriple, 130MHz, 1800Vl!JS
Current Feedback Amplifiers with Shutdown

Pixel Switching

LT1203/05: 2:1 and 4:1 Video Multiplexers

Audio: For 8x Oversampling, 200kHz Bandwidth is Required
Gain Blocks

LT1115: Low Noise Preamplifier
LT1124/26: Dual Low Noise Preamplifier
LT1211!12: High Slew Rate, Single Supply
Dual/Quad Op Amps
LT1122: Ultra-Low Distortion Op Amp with
Symmetric Slew Rates.
LT1354/55/56: Ultra-High Slew Rate,
Low Supply Current Op Amps

CD-ROM LT1311: Quad Precision I-to-V Converter for Optical Drivers

2-5

OPAMP SELECTION GUIDE
Commercial Precision Op Amps
ELECTRICAL ·CHARACTERISTfCS
Vos

PART
NUMBER

MAX

TC
Vas

I.
MAX
(nA)

(V/mv)

AVOl
MIN

SLEW RATE
MIN
(V/J.lS)

NO!SE
MAX 10Hz
(nVrJiiZ)

PACKAGES
AVAILABLE

MllJ
IND
TEMP

.(J,lV)

().lvrc)

SINGLE
LTI001 AC

25

0.6

2.0

450

0.15

18

H, J8, N8

M

LTtoolC
LTl006AC

60
50

1.0
1.3

3.8
15

400

18
24t

H, J8, N8, 58

80
400

1.8
3.5

25
25

0.25
0.25

24t

H, J8
H, J8, N8

M
M

LT1OO6C
LT1006S8

1000
700
700

0.15
0.25

LT1007AC
LT1007C

25
60

0.6
1.0

35
55

7000
5000

1.7
1.7

25
4.5
4.5

58
H, J8, N8
H, J8, N8, 58

LT1008C
LT1012C

120
25

1.5
0.6

0.1

200

50
60

1.5
1.7

300
200
200

0.1
0.1

LT1012AC
LT1012D

0.1
0.15
0.15

30
30
30
30

H, N8
H, N8
H, N8
H, N8

LT1012S8

120
250

1.8
5.0

0.28
0.05

200
150

0.1
23

600

9.0
15.0

0.05
0.05

120
100

.0.8
1.0

90
180

7000
5000

18
18
11
11

60
1.7
1.9

H
N8
H, J8, N8
H, J8, N8, 58

0.6
1.0

35
55

7000
5000

11
11

4.5
4.5

H, J8, N8
H, J8, N8, 58

M
M,I

4

0.05
0.05

150
120
120
120

10
7.5
7.5
7.5

50
60
60
70

H
H
N8
58

M
M

150
120
120
120
250

12
9
9
9.0
0.12

50
60
60
70

H
H
N8

M
M

200

0.12

40
29t

240
700

0.05
0.1

360

700
2000

0.1

90
180
0.050

7000
5000
3162

0.035
0.050
0.03

3162
1000
1000

LT1022AC
LTt022C
LT1022CN8
LT1028AC
LT1028C
LT1037AC
LTt037C
LTt055AC
LT1055C

1000
40
80
25
60
150

LT1056S8
LT1077AC

180
450
800
1500
40

8
12
15
4
8
12
15
0.4

LT1077C

60

0.4

LT1077S8
LT1097C

150
50

3.0
1.0

LT1097S8
LT1115C

60
280

1.4
0.5 (Typ)

LTI128AC
LT1128C

40
80
10

1.0
1.0

LTt055CN8
LT105558
LT1056AC
LT1056C
LT1056CN8

LTC1049C
LTC1050AC

400
700
1500

5

0.05
0.1
0.05
0.05
0.05
0.1
9
11
11
0.25
0;35

0.1
0.1

30
50
60 .

58
H

M

IMPORTANT FEATURES
EX1remely Low Offset Voltage, Low Noise,
Low Drift
Single Supply Operation, Fully Specified for
5VSupply

M
M,I

EX1remely Low NOise, Low Drift

M,I
M,I

Low Bias Current, Low Power
Low Vos, Low Power, C-Load lM Stable

M

M

Very High Speed JFET Input Op Amp with
Very Good DC Specs

M

Lowest Noise, High Speed, Low Drift

M

M
EX1remely Low NOise, High Speed
Lowest Offset, JFET Input Op Amp Combines
High Speed and Precision

58
H,J8, N8

M,I

H,J8, N8

M,I

28t
16t

58
N8

I

0.1
10

16t
1.8

58
N8,S

I

5.0
4.5
0.8t
4t
4t

1.7
1.9

J8, N8, 58
J8, N8, 58

M,I
M,I

Lowest Noise, High Speed, Precision

1.0I1Vp..p"

J8, N8
H, J8, N8, 58

M,I
M,I

Auto Zeroed Precision Op Amp, No EX1ernal
Capac~ors Required

H, J8, N8, S8
H, N8,N

M,I
M,I

Low Noise, Auto Zeroed Precision Op Amp

0.5I1VP_P"
0.6J,lVp_p"

H, N8
H, J8, N8, 58

M,I
M,I

LTC1050C
LTC1052C

5
5

0.05
0.05
0.05

LTC7852C
LTC1150C

5
5

0.05
0.05

0.03
0.03

1000
10000

3t
3t
3t

LTC1152C

10

0.1

0.1

316

It

0.5I1Vp_P

N8,S8

LTC1250C

10

0.05

0.02

10000

lOt

0.3mVp.p"

J8, N8, S8

0.6I1VP_P"
0.6J,lVp-p··
. 0.5J,lVp-p··

Micropower, Single Supply, PreCision,
Low Noise
Low Cost, Low Power PreCision, C-Load Op Amp
Lowest Noise, Ultra Low Distortion Audio
Optimized Op Amp

M

Auto Zeroed Precision O~ Amp That Operates
on Standard ±15V Supp ies. No EX1ernal
Capacitors Required
Rail-to-Railln~ut and Output, Auto Zeroed
Precision Op mp. C-Load Stable.
Low Noise, Auto Zeroed Precision Op Amp

tTYPICal spec
• 100Hz noise
•• DC to 1Hz nOise
C-Load is a trademark of Linear Technology Corporation
NOTE: See page 4-3 for DESC cross reference numbers. Check data sheet for specrrications on industrial and military temperature produced and surface mount.

2-6

OP AMP SELECTION GUIDE
Commercial Precision Op Amps
ELECTRICAL CHARACTERISTICS
SLEW RATE
NOISE
AVOL
MIN
MIN
MAX 10Hz
(V/mV)
(nVNHz)
(V/J.lS)

Vos
MAX
(J.lV)

TC
Vos
(J.lV/"C)

LF355A

2000

5

0.05

75

LF356A

2000

0.05

75

LM10B

2000

5
2t

20

120

LM10BL

2000

2t

20

60

LM10C

4000

SO

4000

5t
5t

30

LM10CL

30

LM30SA

500

5

LT31 SA

1000

LM31S
OP-05C

10000
1300

4.5

PART
NUMBER

18
MAX
(nA)

PACKAGES
AVAILABLE

Mill
IND
TEMP

IMPORTANT FEATURES

SINGLE
5
10

25 t •
15t •

H, NS
H, NS

50t
50t

H, JS

50t
50t

H, JS, NS

SO

-

7

60

0.1

250

200

50

30t
42t

500
7

25
120

50
0.1

42t
20

JFET Inputs, Low IB, No Phase Reversal
M

H, JS

On-Chip Reference Operates with +1.2V
Single Battery

H, JS, NS
H, NS

M

Low Bias, Supply Current

H, JS, NS

M

High Speed, 15MHz

H, JS, NS, SB
H, JB, NB

M
M

High Speed, 15MHz
Low Noise, Low Offset Drift with Time

M
M

Low Initial Offset, Low Noise, Low Drift

OP-05E

500

2.0

4

200

0.1

1B

H, JB, NB

OP-07C

150

1.B

7

120

0.1

20

H, JB, NB, SB

OP-07E

75

1.3

4

200

0.1

500

5

0.05

100

10

H, JB, NB
H, NB

M

OP-15E

1B
20t •

OP-15F
OP-15G

1000
3000

10
15

0.1
0.2

75

7.5
5

H, NB

M
M

OP-16E

500

1B

1000

0.05
0.1

100

OP-16F

5
10

20t •
20t •
20t •

H, NB

50
75

12

OP-16G

3000

15

0.2

50

OP-27E

25

0.6

40

1000

OP-27G
OP-37E

100
25

1.B
0.6

BO
40

OP-37G

100

1.B

OP-97E

25

M

EI

Precision JFET Input, Low Bias Current,
No Phase Reversal

H, NB

M

H, NB

M

9

20t •
20t •

Precision JFET Input, High Speed,
No Phase Reversal

H, NB

M

1.7

5.5

H, JB, NB

I

700
1000

1.7
11

B.O

H, NB

I

5.5

H, JB, NB

I

BO

700

11

B.O

H, NB

I

0.6

±0.1

300

0.1

30

H, NB

M

Low Power, Low IB' Precision

Very Low Noise, Unity Gain Stable
Very Low NOise, Stable for Gains 2: 5

DUAL
LT1002AC

60

0.9

3.0

400

0.15

20

J, N

M

LT1002C

100

1.3

4.5

350

0.15

J, N

M

Dual, Matched LT1 001 High CMRR,
PSRR Matching

LT1013AC

150

2.0

20

1500

0.2

20
24t

H, JB

M

Precision Dual Op Amp in B-Pin Package

LT1013C

300

2.5

30

1200

0.2

24t

H, JB, NB

M,I

LT1013D

BOO

5.0

30

1200

0.2

24t

NB, SB

LT1024AC

1.5

0.12

250

0.1

33

N

M

LT1024C

50
100

2.0

0.20

1BO

33

N

M

LTC1047C

10

0.01

0.02

1000

LTC1051C

5

0.05

0.05

1000

0.1
0.2t
4t

O.SmVp-p"

NB, S
JB, NB, S

M,I

H, JB

M

NB

LT1057AC

450

7

0.05

150

10

0.4flVP-P"
26t

LT1057ACNB

450

10

0.05

150

10

26t

Low Vas, Low Power, Matching Specs
No External Capacitors Required
Dual, Precision Auto Zeroed Op Amp
Low Offset JFET Input Multiple Op Amps
Combine High Speed and Excellent DC Specs

LT1057C

BOO

12

0.075

100

B

26t

H, JB

LT1057CNB

BOO

16

0.075

100

26t

NB, SB

I

LT107BAC

70

2.0

B

250

M

120

2.5

10

200

40
29t

H, J8, N8

LT1078C

B
O.Q7t
O.Q7t

H, JB, N8, SB

M,I

LT1112A

60

0.50

0.25

1000

0.16

15t

JB, NB, S8

M,I

LT1112C

75

0.75

0.2B

0.16

15'

J8, N8, S8

M,I

Low Power, Precision, Matching Specs,
C-Load Op Amp

LT1113AC

1500

15

0.45

SOO
1200

2.5

17t

NB, J8, S8

M,I

Dual Low Noise, Precision JFET Input

LT1113C
LT1124AC
LT1124C

1800
70
100

20
1
1.5

0.48
55
70

1000
2000
1500

2.5
3
2.7

17t

N8, J8, S8
N
J, N, S

M,I
M,I
M,I

Dual Precision Op Amp,
Low Noise, High Speed

t Typical spec

• 100Hz noise

•• DC to 1Hz noise

5.5
5.5

M,I
Micropower, Precision,
Single Supply, Low Noise Dual

NOTE: See page 4-3 for DESC cross reference numbers

2-7

OP AMP SELECTION GUIDE
Commercial Precision Op Amps
ELECTRICAL CHARACTERISTICS
NOISE
SLEW RATE
AVOL
MIN
MIN
MAX 10Hz
(V/mV)
(nVNHz)
(V/~s)

(~V)

TC
Vos

(~V/oC)

18
MAX
(nA)

70
100
1500
lBOO
70
120
275
150
275
150
450
300
475
475
150
2BO
380
450
BOO
1000
1000
3000
80
180
80
lBO
75
250

1.0
1.5
15
20
2.2
3.0
0.6
0.5
0.6
0.5
1.0
O.B
6
6
2
2.5
2.5
10
16
10
10
20
1.0
1.8
1.0
I.B
1
3

20
30
0.003
0.005
5
6
125
100
200
160
600
500
35
35
15
lB
18
0.05
0.075
0.1
0.1
0.2
40
80
40
BO
20
60

2000
1500
1200
1000
140
110
250
250
250
250
150
150
500
500
400
350
350
150
100
100
150
50
3000
2000
3000
2000
750
350

B
B
2.4
2.4
0.013
0.013
4
4
B.5
B.5
30
30
0.12'

LT1014AC
LT1014C
LT1014D
LT105BAC
LT105BC
LT1079AC
LT1079C
LT1114AC
LT1114C
LT1125AC
LT1125C
LT1127AC
LT1127C
LT1179AC
LT1179C
LT1212C
LT1214C
LT1216C
LT1367C

lBO
300
BOO
600
1000
120
150
60
75
90
140
90
140
100
150
275
275
450
800

2.0
2.5
5.0
10
15
2.0
2.5
0.50
0.75
1
1.5
1.0
1.5
2.2
3.0
6
6
to
6

20
30
30
0.05
0.075
B
10
0.25
0.2B
20
30
20
30
5
6
125
200
600
35

LT1369C

800

6

LTC1053C

5

OP-470A
OP-470C

400
1000

PART
NUMBER
DUAL
LT1126AC
LT1126C
LT1169A
LT1169C
LT117BAC
LT117BC
LT1211C
LT1211AC
LT1213C
LT1213AC
LT1215C
LT1215AC
LT1366C
LT136BC
LT1413AC
LT1413C
LT1413S8
LT1457AC
LT1457C
LF412AC
OP-215E
OP-215G
OP-227E
OP-227G
OP-237E
OP-237G
OP-270A
OP-270C

Vos
MAX

PACKAGES
AVAILABLE

MILl
INO
TEMP

IMPORTANT FEATURES

NB
JB, NB, SB
JB, NB, SB
JB, NB, SB
H, JB, NB
H, JB, NB
JB, NB, SB
JB, NB, SB
JB, NB, SB
JB, NB, SB
JB, NB, SB
JB, NB, SB
NB, SB
NB, SB
NB
NB, SB
SB
NB
N8, S8
H, J8, N8
H, J8, N8
H, J8, N8
J, N
J, N
J, N
J, N
J
N, S

M,I
M,I

0.2
0.2
0.2
2
2
10
10
8
1.7
1.7
10
10
1.7
1.7

5.5
5.5
17'
17'
75
50'
12.5
12.5
10
10
15
15
29''''
29""
24'
24'
24'
26'
28'
20"
20"
20"
6
9
6
9
6.5
3.6'

Dual Precision Op Amp, Low Noise, High Speed

1500
1200
1200
150
100
250
200
1000
800
2000
1500
2000
1500
140
110
250
250
t50
500

0.2
0.2
0.2
10
8
0.07'
0.07'
0.16
0.16
3
2.7
B
8
0.013
0.013
4
B.5
30
0.12'

24'
24'
24'
26'
26'
40
29'
15'
15'
5.5
5.5
5.5
5.5
75
50'
12.5'
10'
15'
29""

J
J, N
N, S
J
J, N, S
J, N
J, N, S
J8, NB, S8
J8, NB, SB
N
J, N, S
N
N, J, S
J, N
J, N
N, S
N, S
N, S
NB, S8

M
M,I

Precision Quad Op Amp in 14-Pin Package

M
M,I
M
M,I
M, I
M, I
M
M,I
M
M,I

Low Offset JFET Input Multiple Op Amps
Combine High Speed and Excellent DC Specs

35

500

-

29""

N, S

I

0.05

0.05

1000

4'

O.4~Vp-p"

N, S

I

2
2'

25
60

500
400

1.4
1.4

6.5
6.5

J
N, S

M

Dual Low Noise, Picoampere Bias Current
JFET Input Op Amp
17~

I
M,I
M,I
M,I
M,I
M,I
M, I
I
I
I
I
I
I
I
M
M
M
M
M
M
M
M
M

Max, Single Supply, Precision Dual

Fast, Precise, Single Supply Op Amps.
Industrial Temperature (-40'C to B5'C)
Specs Included with Commercial Temperature
Devices

Rail-to-Raillnput and Output, Precision
Rail-to-Raillnput and Output, Precision
Dual Single Supply Precision Op Amp
Optimized for 5V and GND
Dual Precision JFET Input Op Amp.
C-Load Stable
High Performance Dual JFET Input Op Amp

Dual Matched OP-27
Dual Matched OP-37
Dual Op Amp, Low Noise

QUAD

t Typical spec

• 1DDHz noise
.. DC to 1Hz noise
NOTE: See page 4-3 for DESC cross reference numbers

... 1kHz noise

Micropower, Precision, Single Supply,
Low Noise Quad
Low Power, Precision, Matching Specs
Precision Quad Op Amp,
Low Noise, High Speed

17~

I
I
I
I
I

Max, Single Supply, Precision Quad

Fast, Precise, Single Supply Op Amps.
Industrial Temperature (-40'C to 85°C)
Specs Included with Commercial Temperature Devices
Rail-to-Raillnput and Output,
Precision Can Handle 0.11JF C-Load
Rail-to-Raillnput and Output,
Precision Can Handle O.tlJF C-Load
Quad, Precision Auto Zeroed Op Amp.
No External Capacitors Required
Quad Op Amp, Low Noise

OP AMP SELECTION GUIDE
High Speed Op Amps
ELECTRICAL CHARACTERISTICS

PART
NUMBER
SINGLE
LM118
LT118A
LT318A
LT1028AC
LTl028C
LTl037AC
LTl037C
LT1115C
LT1122AC

MIN
SLEW
RATE

TYP
SETTLING TIME

(V/IlS)

(ns)

50
50
50
11
11
11
11
10
60

LT1122BC
LT1122CC

60
50

LTl122DC
LTl128AC
LTl128C
LTl187C
LT1189C
LT1190C
LT1191C
LT1192C
LTl193C
LT1194C
LT1195C
LT1200C
LT1206C
LT1217C
LTl220C
LT1221C
LTl222C
LT1223C
LT1224C
LT1225C
LTl226C
LT1227C
LT1228C
LT1252C
LT1354C
LT1357C
LTl360C
LTl363C
DUAL
LT1124AC
LT1124C
LT1126AC
LTl126C
LTl201C
LT1208C

50
5
4.5
130
175
450 t
450 t
450t
450t
4sot
140
30
600
100
200
200
200
800
250
250
250
500
300
250
200
300
600
750
3
2.7
8
8
30
250

TYPICAL GAIN
BANDWIDTH
PRODUCT
(MHz)

MIN
AvoL
(V/mV)

MAX
Vos
(mV)

MAX

(j.tA)

PACKAGES
AVAILABLE

15
15
15
75

50
100
100
7000

75
60
60
70
14

5000
7000
5000
2000
180

4
1
1
0.04
0.08
0.025
0.06
0.2
0.6

0.25
0.25
0.25
0.09
0.18
0.035
0.055
0.38
75pA

H, J8
H, J8
H, J8, N8
H, J8, N8
H, J8, N8, 58
H, J8, N8
H, J8, N8, 58
N8,SWI6
J8, N8

14
13

180
150

0.6
0.9

75pA
100pA

J8, N8
J8, N8, 58

M
M

150
7000
5000

0.5
4
0.6
3.2
20
50
100
3.2
3.3
12.5
50
0.6
0.6
0.56
12
20
4.5
4.5

0.9
0.04
0.08
10
3
10
5
2.5
12
6
8
1
15
3
1
0.6
0.3
3
2
1
1
10
10
15
0.8
0.6
1
1.5

100pA
0.09
0.18
2
2
2.5
2.5
2.5
3.5
3.5
2
1
5
0.5
0.3
0.3
0.3
3
8
8
8
3
3
15
0.3
0.5
1
2

J8, N8, 58
N8
N8,S8
N8,S8
N8,S8
J8, N8, 58
J8, N8, 58
J8, N8, 58
J8, N8, 58
J8, N8, 58
J8, N8, 58
N8,S8
N8, R, Y, 58
N8,S8
H, J8, N8, 58
H, J8, N8, 58
H, J8, N8, 58
J8, N8, 58
J8, N8, 58
J8, N8, 58
J8, N8, 58
,J8, N8, 58
J8, N8, 58
N8,S8
N8,S8
N8,S8
N8,S8
N8,S8

M

230
115
60
50

13
20
20
50 (Av= 2)
35 (Av= 10)
50
90
400 (Av > 5)
70
40
50
11.0
50
10.0
45
150 (Av <: 4)
500 (Av > 10)
100
45
150 (Av <: 5)
1000 (Av <: 25)
140.0
100
100
12
25
50
70

330
90

12.5
12.5
45
45
12
45

5000
3000
5000
3000
4
3.3

0.07
0.1
0.07
0.1
2
3

0.025
0.03
0.02
0.03
1
8

J8, N8
J8, N8, 58
J8, N8
J8, N8, 58
N8,S8
N8,S8

TO 0.1 %

340'
540"
350'
350'
590"
360'

100'"
1000'"
100
100
100
100
100
220'"
430
280
75
65
75
75
90
70
75
50
45

3.5
6
16

18

tTypical value '10V step, to 1mV at sum node. "Maximum value, 10V step, to 1mV at sum node.
NOTE: See page 4-3 for DESC cross reference numbers

~7lJD~

Mill
IND
TEMP
M
M
M
M
M
M
M

IMPORTANT FEATURES
Industry Standard
Improvement Over LM118
Commercial Temp Version of LT118A
Ultra-Low Noise, Precision, Low Drift
Ultra-Low Noise, Precision, Low Drift
Av = 5, Low Noise, Precision
Av = 5, Low Noise, Precision
Ultra-Low Noise, Low Distortion, Audio
JFET l'¥lUt. Faster and Better DC
Specs han OP-42. A and C Have
Grades 100% Tested Settling Time

Ultra-Low NOise, Precision, Unity-Gain Stable
Ultra-Low Noise, Precision, Unity-Gain Stable
Low Power Video Difference Amplifier
M
M
M
M
M
M

M
M
M
M
M
M
M

M
M
M
M

±5V Supply Color Video Op Amps

Color Video Differential Amplifier
Low Power, High Speed
Low Supply Current Op Amp
250mA Current Feedback Amplifier
Low Power Current Feedback Amplifier
Ultra High Speed, Good DC Specs, C-Load
Driving
Current Feedback Amplifier with Good DC Specs
High Speed, DC Precision, Stable While Driving
Unlimited Capacitive Load (C-Load)
Current Feedback Amplifier
Electronic DC Gain Control
Low Cost Video Amplifier
lmA, 12MHz, 400v/j.lS C-Load
2mA, 25M Hz, 600V/j.lS C-Load
4mA, 50MHz, 800V/j.lS C-Load
6mA, 70MHz, 1000v/j.lS C-Load
Dual, Low Noise, Precision
Dual, Low Noise, Precision
Av = 10, Dual, Low Noise, Precision
Av = 10, Dual, Low Noise, Precision
lmA, 12MHz, 50V/j.lS Dual C-Load
45MHz, 450VIj.lS Dual C-Load

"'3V Step

2-9

OP AMP SELECTION GUIDE
High Speed Op Amps
ELECTRICAL CHARACTERISTICS

PART
NUMBER
DUAL
LT1211C
LT1211AC
LT1213C
LT1213AC
LT1215C
LT1215AC
LT1229C
LT1253C
LT1259C
LT1355C
LT135BC
LT1361C
LTI364C
TRIPLE
LT1260C
QUAD
LT1125AC
LT1125
LT1127AC
LT1127C
LT1202C
LT1209C
LT1212C
LT1214C
LT1216C
LT1230C
LT1254C
LT1356C
LT1359C
LT1362C
LT1365C

MIN
SLEW
RATE
(V/IlS)

TYP
SmLlNGTIME
TO 0.1 %
(ns)

TYPICAL GAIN
BANDWIDTH
PRODUCT
(MHz)

5
5
10
10
40
40
300
250
900

2200
2200
1100
1100
480
4BO
45

14
14
2B
2B
23
23
100

75

200
300
600
750
900

3
2.7
B
B
30
250
5
10
40
300
250
200
300
600
750

MIN
AVOL
(V/mV)

MAX
Vos
(IlV)

MAX
(!!A)

PACKAGES
AVAILABLE

130

1200
1200
1200
1200
1000
1000
0.6
0.560
0.71

0.55
0.4
0.55
0.4
0.65
0.5
10
15
10

0.12
0.095
0.19
0.15
0.55
0.5
3
15
3

JB, NB, SB
JB, N8, SB
J8, NB, SB
JB, N8, 58
JB, NB, 58
JB, NB, 58
JB, NB, 58
NB,SB
N14,S14

230
115
60
50

12
25
50
70

12
20
4.5
4.5

O.B
0.6
1
1.5

0.3
0.5
1
2

NB,SB
NB,SB
NB,SB
NB,S8

75

130

0.71

10

3

N16,S16

12.5
12.5
45
45
12
45
14
2B
23
100
90
12
25
50
70

5000
3000
5000
3000
4
3.3
1200
1200
1000
0.6
0.560
12
20
4.5
4.5

0.09
0.14
0.09
0.14
2
3
0.55
0.55
0.65
10
15
O.B
0.6
1
1.5

0.02
0.03
0.02
0.03
1
8
0.12
0.19
0.55
3
15
0.3
0.5
1
2

J14, N14
J14, N14, 516
J14, N14
J14, N14, 516
N14,S16
N14,S16
N14,S16
N14,S16
N14,S16
J14, N14, 514
N14,S14
N14,S16
N14,S16
N14,S16
N14,S16

90

330
90
2200
1100
4BO
45
230
115
60
50

la

'lypical value '10V step, to 1mV at sum node. "Maximum value, 10V step, to 1mV at sum node.
NOTE: See page 4-3 for DESC cross reference numbers

2-10

Mill
IND
TEMP
M
M
M
M
M
M
M

IMPORTANT FEATURES
14MHz, 7VIJl$ Single Supply Precision
2BMHz, 12V1Jl$, Single Supply Precision
23MHz, 50VlJl$, Single Supply Precision
Fast Slew Rate, Current Feedback Architecture
Low Cost Video Amplifier
Low Cost 130MHz Dual CFAs with
Individual Shutdowns
1mA, 12MHz, 400VlJl$ Dual C-Load
2mA, 25M Hz, 600VlJl$ Dual C-Load
4mA, 50MHz, 800VlJl$ Dual C-Load
6mA, 70MHz, 1000VlJl$ Dual C-Load
Low Cost Triple 130MHz CFAs
with Individual Shutdowns

M
M
M
M

M

Quad, Low NOise, Precision
Quad, Low Noise, Precision
Av = 10, Quad, Low Noise, Precision
Av = 10, Quad, Low Noise, Precision
1rnA, 12MHz, 50VlJl$ Quad C-Load
45MHz, 450VlJl$ Quad C-Load
14MHz, 7VIJl$ Single Supply Precision
2BMHz, 12V1Jl$, Single Supply Precision
23M Hz, 50VlJl$, Single Supply Precision
Fast Slew Rate, Current Feedback Architecture
Low Cost Video Amplifier
lmA, 12MHz, 400VlJl$ Quad C-Load
2mA, 25M Hz, 600VlJl$ Quad C-Load
4mA, 50MHz, BOOVlJl$ Quad C-Load
6mA, 70MHz, 1000VlJl$ Quad C-Load

'''3V Step

~7lJD~

OP AMP SELECTION GUIDE
C-Load ™Stable Op Amps
# OF AMPS
MINAv
Single
1
Single
1
Dual
1
Quad
1
Single
1
Single
1
Dual
1
Quad
1
Single
1
Dual
1
Quad
1
Single
1
Single
4
Single
10
Single
1
Single
5
Single
25
Single
1
Dual
1
Quad
1
Single
1
Dual
1
Quad
1
Single
1
Dual
1
Quad
LT1362
1
Single
LT1363
1
LT1364
Dual
1
LT1365
Quad
1
LT136B
Dual
1
LT1369
Quad
1
LT1457
Dual
1
C-Load IS a trademark of Linear Technology Corporation
PART NUMBER
LT1097
LT1012
LT1112
LT1114
LTCl152
LT1200
LT1201
LT1202
LT1206
LT120B
LT1209
LT1220
LT1221
LT1222
LT1224
LT1225
LT1226
LT1354
LT1355
LT1356
LT1357
LT135B
LT1359
LT1360
LT1361

C-Load Operational Amplifiers Are Stable with Any Capacitve Load.

MAXVos
60~V
50~V

75~V
75~V

1OI1V
lmV
2mV
2mV
10mV
3mV
3mV
lmV
0.6mV
0.3mV
2mV
1mV
lmV
BOO~V
BOO~V
BOO~V
600~V
600~V

600~V

1mV
lmV
lmV
1.5mV
1.5mV
1.5mV
450~V

45Ol1V
BOO~V

MAXIB
350pA
150pA
230pA
230pA
100pA
1~
1~
1~
5~
B~
B~

300nA
300nA
300nA
B~

B~
B~

300nA
300nA
300nA
500nA
500nA
500nA
1~
1~
1~
2~
2~

2~

35nA
35nA
75pA

MIN lOUT
5.7mA
5.7mA
5.7mA
5.7mA
4mA
6mA
6mA
6mA
250mA
24mA
24mA
24mA
24mA
24mA
20mA
20mA
20mA
30mA
30mA
30mA
30mA
30mA
30mA
40mA
40mA
40mA
70mA
70mA
70mA
30mA
30mA
10mA

BANDWIDTH
700kHz
700kHz
750kHz
750kHz
lMHz
llMHz
12MHz
12MHz
60MHz
45MHz
45MHz
45MHz
150MHz
500MHz
45MHz
150MHz
lGHz
12MHz
12MHz
12MHz
25MHz
25MHz
25MHz
50MHz
50MHz
50MHz
70MHz
70MHz
70MHz
450kHz
450kHz
I.7MHz

SLEW RATE

Is/AMP

O.2V1~

3BO~

O.2V1~

3BO~

0.3V1~

350~

0.3V/~

350~

1V/~

500~

50V/~

1000V/~

lmA
lmA
lmA
5mAto22mA
7mA
7mA
BmA
BmA
BmA
7mA
7mA
7mA
lmA
lmA
lmA
2mA
2mA
2mA
4mA
4mA
4mA
6mA
6mA
6mA

0.15V/~

375~

O.15V/~

375~

4V1~

I.BmA

50Vl~
50V/~
900Vl~

400Vl~
400V/~
250Vl~

250V/~
200V/~
400V/~
400V/~

400Vl~
400Vl~
400Vl~
400Vl~
600Vl~
600Vl~
600V/~
BOOV/~
BOOV/~
BOOV/~
1000v/~
1000V/~

Ell

2-11

NOTES

2-12

INDEX
SECTION 2-AMPLIFIERS
PRECISION OPERATIONAL AMPLIFIERS
LT1366/LT1367/LT1368/LT1369, Dual and Quad Precision Rai/-to-Rai/lnput and Output Op Amps .................... 2-14

Ell

2-13

.f=Af\
L1n
£7 U \K

LT1366/LT1367
LTl368/LT1369
TECHNOLOGY~--D-u-o-I-o-n-d-Q--u-o-d--P-re-c-i-si-a-n
Roil-ta-Roil Input and Output
OpAmps

FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•
•
•
•

The LT®1366/L T1367/LT1368/L T1369 are dual and quad
bipolar op amps which combine rail-to-rail input and
output operation with precision specifications. These op
amps maintain their characteristics over a supply range of
1.8V to 36V. Operation is specified for 3V, 5V and ±15V
supplies, Input offset voltage is typically 150IlV, with a
minimum open-loop gain AVOL of 1 million while driving a
2k load. Common-mode rejection is typically 90dB overthe
full rail-to-rail input range, and supply rejection is 11 OdB.

Input Common-Mode Range Includes Both Rails
Output Swings Rail-to-Rail
low Input Offset Voltage: 150llV
High Common-Mode Rejection Ratio: 90dB
High AVOL: 1V/IlV Minimum Driving 2kQ Load
Low Input Bias Current: 10nA
Wide Supply Range: 1.8V to ±15V
Low Supply Current: 375!lA per Amplifier
High Output Drive: 30mA
400kHz Gain-Bandwidth Product
Slew Rate: O.13V/IlS
Stable for Capacitive Loads up to 1000pF

APPLICATions
•
•
•
•

Rail-to-Rail Buffer Amplifiers
Low Voltage Signal Processing
Supply Current Sensing at Either Rail
Driving AID Converters

The LT1366/LT1367 have conventional compensation
which assures stability for capacitive loads of 1OOOpF or
less. The LT1368/LT1369 have compensation that requires a O.1W output capacitor, which improves the
amplifier's supply rejection and reduces output impedance at high frequencies. The output capacitor's filtering
action reduces high frequency noise, which is beneficial
when driving AID converters.
The LT1366/LT1368areavaiiabie in plastic 8-pin PDIP and
8-lead SO packages with the standard dual op amp pinout.
The LT1367/LT1369 feature the standard quad pinout,
which is available in a plastic 16-lead SO package. These
devices can be used as plug-in replacements for many
standard op amps to improve input/output range and
precision.

LT, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn

Output Saturation Voltage vs Load Current

Positive Supply Rail Current Sense
Vee

1000

R1

200n

s>w

~­
~~

100

0,

NEGATIVE
RAIL

>>z~

~~
R2

20k

VD=ILDADXRS(~)

C?

10

:::J

!;,:
en

= ILDAD x 20n

1
0.001

2-14

POSITIVE
RAIL

0.01
0.1
LOAD CURRENT (mA)

10

LT1366/LT1367
LT1368/LT1369
ABSOLUTE mAXimum RATinGS
Total Supply Voltage (V+ to V-) ............................. 36V
Input Current ..................................................... ±15mA
Output Short-Circuit Duration (Note 1) ........ Continuous
Operating Temperature Range .............. -40°C to 85°C

Junction Temperature .......................................... 150°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
TOP VIEW

N8 PACKAGE
8·LEAD PDIP
S8 PACKAGE
B-LEAD PLASTIC SO

ORDER PART
NUMBER

ORDER PART
NUMBER

LT1366CN8
LT1366CS8
LT1368CN8
LT1368CS8

LT1367CS
LT1369CS

S8 PART MARKING

TJMAX =150'C, 8JA =131l"C/W (N8)
TJMAX = 150'C, 8JA = 190'C/W (S8)

1366
1368

S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 150'C, 8JA = 150'C/W

Consult factory for Industrial and Military parts.
Available Options

PRODUCT NUMBER
LT1366
LT1367
LT1368
LT1369

ORDER PART NUMBER
PLASTIC (N)
SURFACE MoUNT(S)

NUMBER OF OP AMPS
2

LOAD CAPACITANCE

MAX Vas (25°C)
AT Vs = 5V, OV

OpF < CL < 1000pF

47511V

LT1366CN8

4
2
4

OpF < CL < 1000pF
CL=O.ll1f

800llV
47511V

LT1368CN8

CL = 0.111f

800llV

LT1366CS8
LT1367CS
LT1368CS8
LT1369CS

ELECTRICAL CHARACTERISTICS
=

TA 25°C, Vs

=5V, av, VCM =2.5V, Vo =2.5V, unless otherwise noted.

SYMBOL PARAMETER
Input Offset Voltage (LT1366/LT1368)

Vas

Input Offset Voltage (LT1367/LT1369)

IB

Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
Input Bias Current

/!J.IB

Input Bias Current Shift

/!J.VOS

CONDITIONS

MIN

VCM = Vcc
VCM = VEE
VCM = Vcc
VCM = VEE
VCM = VEE to Vcc
VCM = VEE, VCC (Notes 4,5)
VCM = VEE to Vcc
VCM = VEE, VCC (Notes 4, 5)
VCM = Vcc
VCM = VEE
VCM = VEE to VCC

0
-35

TYP
150
150
150
150
150
250
150
250
10
-10
20

MAX
475
475
800
700
400
700
650
1600
35
0
70

UNITS
IIV
IIV
IIV
IIV
IIV
IIV
IIV
IIV
nA
nA
nA

2-15

LT1366/LT1367
LT1368/LT1369

ELECTRICAL CHARACTERISTICS
TA = 25°C, Vs = 5V, DV, VCM = 2.5V, Vo = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
Input Offset Current
los
Alas

en
in
CIN
AVOL
CMRR

Input Offset Current Shift
Input Bias Current Match (Channel to Channel)
Input Noise Voltage Density
Input Noise Current Density
Input Capacitance
Large-Signal Voltage Gain

VOL

Common-Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
Power Supply Rejection Ratio
PSRR Match (Channel to Channel) (Note 4)
Output Voltage Swing LOW

VOH

Output Voltage Swing HIGH

Isc
Is
GBW

Short-Circuit Current
Supply Current per Amplifier
Gain-Bandwidth Product (LT1366/LT1367)
Gain-Bandwidth Product (LT1368/LT1369)
Settling Time (LT1366/LT1367)

PSRR

ts

CONDITIONS

MIN

VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc (Note 4)
VCM =VEE (Note 4)
f =1kHz
f =1kHz

0
0

Va =50mV to 4.8V, RL =10k

500
81
75
77
71
90
84

VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
VCM =VEE to Vcc
VCM =VEE to VCC (Note 4)
Vs =2.0V to 12V, VCM =Va =0.5V
Vs =2.0V to 12V, VCM =Va =0.5V
No Load
ISINK =0.5mA
ISINK =2.5mA
No Load
ISOURCE =0.5mA
ISOURCE =2.5mA
(Note 1)

TYP
1
0.3
1
1
1
29
0.07
12
2000
90
90
90
90
105
100
6
40
110

Vcc - 0.008 Vcc - 0.004
Vcc- 0.100 Vcc- 0.050
Vcc-0.250 Vcc-O.150
±15
±30
375
0.4
0.16
30

Av =1000
Av =1000
Av =1, VSTEP =4V to 0.1%

MAX
6
6
6
12
12

12
70
200

520

UNITS
nA
nA
nA
nA
nA
nVl.,[Hz
pA/.,[Hz
pF
VlmV
dB
dB
dB
dB
dB
dB
mV
mV
mV
V
V
V
mA
~
MHz
MHz

IJS

DOC < TA < 70°C, Vs = 5V, DV, VCM = 2.5V, Vo = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
Input Offset Voltage (LT1366/LT1368)

Vas

Input Offset Voltage (LT1367/LT1369)

18

Input Offset Voltage Drift
Input Offset Voltage Shift (LT1366/LT1368)
Input .offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
Input Bias Current

AlB

Input Bias Current Shift

los

Input Offset Curre~t

Alas

Input Offset Current Shift
Input Bias Current Match (Channel to Channel)

Vas TC
AVos

2-16

CONDITIONS
VCM =Vcc
VCM =VEE
VCM =Vcc
VCM =VEE
(Note 2)
VCM =VEE to Vcc
VCM =VEE, VCC (Notes 4, 5)
VCM =VEE to Vcc
VCM =VEE, VCC (Notes 4, 5)
VCM =VCC
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc (Note 4)
VCM =VEE (Note 4)

MIN

••
••
•
••
•
•
••
•

0
-45

•
••

0
0

••

TYP
200
200
200
200
2
200
250
200
250
15
-10
25
2
1
2
2
1

MAX
575
575
950
900
6
425
900
675
1900
45
0
90
15
15
15
15
15

UNITS
/LV
/LV
/LV
/LV
/LVloC
/LV
/LV
/LV
/LV
nA
nA
nA
nA
nA
nA
nA
nA

LT1366/LT1367
LT1368/LT1369
ELECTRICAL CHARAOERISTICS
DOC < TA < 7DOC, Vs

=SV, OV, VCM =2.SV, Vo =2.SV, unless otherwise noted.

SYMBOL PARAMETER
AVOL
CMRR

Large-Signal Voltage Gain
Common-Mode Rejection Ratio (LT1366/L T1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)

PSRR

Power Supply Rejection Ratio
PSRR Match (Channel to Channel) (Note 4)

VOL

Output Voltage Swing LOW

VOH

Output Voltage Swing HIGH

Isc
Is

Short-Circuit Current

MIN

CONDITIONS

=50mV to 4.8V, RL =10k
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
Vs =2.3V to 12V, VCM =Va =0.5V
Vs =2.3V to 12V, VCM =Va =0.5V
Va

No Load
ISINK =0.5mA
ISINK =2.5mA
No Load
ISOURCE =0.5mA
ISOURCE =2.5mA
(Note 1)

•

MAX

UNITS
V/mV
dB
dB
dB
dB
dB
dB

14
80
230

mV
mV
mV
V
V
V

±15

•

Supply Current per Amplifier

TYP

• 50080 2000
87
•• 74
87
87
• 7771
87
• 88
105
•• 82
100
9
45
•••
120
Vcc - 0.010 Vcc - 0.005
• Vcc- 0.110 Vcc- 0.055
•• Vcc - 0.300 Vcc - 0.180

mA
360

540

JJA

TYP
250
200

MAX

UNITS

900
750

~V
~V

250
200

1150
1000

~V
~V

-4Doe < TA < 8Soe (Note 3), Vs =SV, OV, VCM = 2.SV, Vo =2.SV, unless otherwise noted.
SYMBOL PARAMETER
Input Offset Voltage (LT1366/L T1368)

VOS

Input Offset Voltage (LT1367/LT1369)
Vas TC

Input Offset Voltage Drift

I'.Vos

Input Offset Voltage Shift (L T1366/L T1368)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (L T1367/LT1369)
Input Offset Voltage Match (Channel to Channel)

IB

Input Bias Current

I'.IB

Input Bias Current Shift

los

Input Offset Current

I'.los

Input Offset Current Shift
Input Bias Current Match (Channel to Channel)

AVOL
CMRR

Large Signal Voltage Gain
Common-Mode Rejection Ratio (L T1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)

PSRR

Power Supply Rejection Ratio
PSRR Match (Channel to Channel) (Note 4)

VOL

Output Voltage Swing LOW

MIN

CONOITIONS
VCM =Vcc
VCM =VEE
VCM =Vcc
VCM =VEE
(Note 2)

=VEE to Vcc
=VEE, VCC (Notes 4, 5)
VCM =VEE to Vcc
VCM =VEE, VCC (Notes 4, 5)
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc (Note 4)
VCM =VEE (Note 4)
Va =50mV to 4.8V, RL =10k
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
Vs =2.3V to 12V, VCM =Va =0.5V
Vs =2.3V to 12V, VCM =Va =0.5V
VCM
VCM

No Load
ISINK =0.5mA
ISINK =2.5mA

•
•
•

•
•
••
••

•
•
•
•
•
•
••
•
••
••
••
••
•

0
-45

~V/oC

2

6

200
250

650
1800

~V
~V

200
250

725
2300

~V

45
-10

80

a

nA
nA

55

125

nA

4
1

30
20

nA
nA

~V

4

30

nA

0
0

4
1

30
20

nA
nA

400

2000

77
71

87
87

dB
dB

76
70

87
87

dB
dB

88
82

105
100

dB
dB

9
45
130

V/mV

20
80
230

mV
mV
mV

2-17

LTl 366/LTl 367
LT1368/LT1369
ELEORICAL CHARAOERISTICS
-40°C < TA < 85°C (Note 3), Vs = 5V, OV, VCM = 2.5V, Vo = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
Output Voltage Swing HIGH

VOH

Isc
Is

Short-Circuit Current
Supply Current per Amplifier

CONDITIONS
No Load
ISOURCE = 0.5mA
ISOURCE = 2:5mA
(Note 1)

MIN

TYP

• Vcc- 0.015 Vcc- 0.006
• Vcc-0.110 Vcc-0.055
• Vcc - 0.300 Vcc - 0.190
±12
375

•
•

MAX

UNITS
V
V
V
mA

575

!iii

MAX
475
475
850
750
400
700
650
1700
35
0
70
6
6
6
12
12

UNITS

TA = 25°C, Vs = 3V, OV, VCM = 1.5V, Vo = 1.5V, unless otherwise noted.
SYMBOL PARAMETER
Input Offset Voltage (LT1366/LT1368)
Vos
Input Offset Voltage (LT1367/LT1369)
1!.Vos

Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)

IB

Input Bias Current

1!.IB

Input Bias Current Shift
Input Offset Current

los
1!.los

Input Offset Current Shift
Input Bias Current Match (Channel to Channel)

VOL

VOH

Output Voltage Swing HIGH

Isc
Is

Short-Circuit Current
Supply Current per Amplifier

DOC < TA < 70°C, Vs = 3V, OV,

0
-35

VCM =VCC
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc (Note 4)
VCM =VEE (Note 4)
Vo =50mV to 2.8V, RL =10k

0
0
500
77
71
73
67

VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
No Load
ISINK =0.5mA
ISINK =2.5mA
No Load
ISOURCE =0.5mA
ISOURCE =2.5mA
(Note 1)

TYP
150
150
150
150
150
250
150
250
10
-10
20
1.0
0.3
1
1
1
1500
86
86
86
86
6
40
110

Vcc - 0.008 VCC - 0.004
Vcc-0.100 Vcc-0.050
Vcc - 0.250 Vcc - 0.150
±20
±10
350

12
70
200

!LV
!LV
!LV
!LV
!LV
!LV
!LV
!LV
nA
nA
nA
nA
nA
nA
nA
nA
VlmV
dB
dB
dB
dB
mV
mV
mV
V
V
V
mA

500

!iii

MAX

UNITS

575
575
950
900

!LV
!LV
!LV
!LV

ItM = 1.5V, I4J = 1.5V, unless otherwise noted.

SYMBOL PARAMETER
Input Offset Voltage (LT1366/LT1368)
Vos
Input Offset Voltage (LT1367/LT1369)

2-18

VCM =VEE to Vcc
VCM =VEE, VCC (Notes 4, 5)
VCM =VCC
VCM =VEE
VCM =VEE to Vcc

Large-Signal Voltage Gain
Common-Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
Output Voltage Swing LOW

AVOL
CMRR

MIN

CONDITIONS
VCM =Vcc
VCM =VEE
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =VEE, VCC (Notes 4, 5)

MIN

CONDITIONS
VCM =Vcc
VCM =VEE
VCM =Vcc
VCM =VEE

••
••

TYP
200
200
200
200

LTl366/LT1367
LTl368/LT1369
ELEORICAL CHARACTERISTICS
DOC < TA < 7DOC, Vs =3V, DV,

~M

=1.5V, 141 =1.5V unless otherwise noted.

SYMBOL PARAMETER
Input Offset Voltage Shift (LT1366/LT1368)
~Vos
Input Offset Voltage Match (Channel to Channel)

Vos TC
IB
~IB

los

Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Shift
Input Offset Current

~Ios

Input Offset Current Shift
Input Bias Current Match (Channel to Channel)

1\VOL
GMRR

VOL

Large-Signal Voltage Gain
Common-Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367 /LT1369)
CMRR Match (Channel to Channel)
Output Voltage Swing LOW

IfOH

Output Voltage Swing HIGH

Isc
Is

Short-Circuit Current
Supply Current per Amplifier

-4DOC < TA < 85°C (Note 3), Vs =3V, DV,

~M

SYMBOL PARAMETER
Input Offset Voltage (LT1366/LT1368)
Input Offset Voltage (LT1367/LT1369)

los TC
B
~IB

os
~Ios

VCM =VEE to Vcc
VCM =VEE. VCC (Notes 4. 5)
(Note 2)
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc (Note 4)
VCM =VEE (Note 4)
Vo =50mV to 2.8V. RL =10k
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
No Load
ISINK =0.5mA
ISINK =2.5mA
No Load
ISOURCE =0.5mA
ISOURCE =2.5mA
(Note 1)

MIN

••

••

TYP
200
250
200
250

2
• 0
• -45 -1015
•
25
•
2
•
1
•
2
• 0
2
• 0
• 300 15001
• 76
83
•
83
• 7072
83
• 66
83
•
9
••
45
•• Vcc - 0.010 Vcc 120
- 0.005
• Vcc- 0.110 Vcc- 0.055
• Vcc - 0.300 Vcc - 0.180
±10
350

•
•

MAX
425
900
675
1900
6
45
0
90
15
15
15
15
15

14
80
230

UNITS
IlV
IlV
IlV
IlV
IlV/oC
nA
nA
nA
nA
nA
nA
nA
nA
V/mV
dB
dB
dB
dB
mV
mV
mV
V
V
V
rnA

520

!!A

MAX
900
750
1200
1000
650
1800
775
2400

UNITS

=1.5V, ~ =1.5V, unless otherwise noted.

'os

Wos

CONOITIONS
VCM =VEE to Vcc
VCM =VEE. Vcc (Notes 4. 5)

Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Shift
Input Offset Current
Input Offset Current Shift
Input Bias Current Match (Channel to Channel)

MIN

CONDITIONS
VCM =Vcc
VCM =VEE
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VXCM =VEE. VCC (Notes 4. 5)
VCM =VEE to Vcc
VCM =VEE. VCC (Notes 4. 5)
(Note 2)
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =Vcc (Note 4)
VCM =VEE (Note 4)

0
-45

TYP
250
200
250
200
200
250
200
250
2
45
-10

0
0

55
4
1
4
4
1

•
•

••
•
•
••
•

•
•
•
••
•

••

6
80
0
125
30
20
30
30
20

IlV
IlV
IlV
IlV
IlV
IlV
IlV
IlV
llV/oC
nA
nA
nA
nA
nA
nA
nA
nA

2-19

LT1366/LT1367
LT1368/LT1369

ElEORICAl CHARACTERISTICS
-40°C < TA < 85°C (Note 3), Vs = 3V, OV,

'4:M = 1.5V, ~ = 1.5V, unless otherwise noted.

SYMBOL PARAMETER

VOL

Large-Signal Voltage Gain
Common-Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
Output Voltage Swing LOW

VOH

Output Voltage Swing HIGH

AVOL
CMRR

Isc
Is

Short-Circuit Current
Supply Current per Amplifier

CONOITIONS
Vo = 50mV to 2.8V; RL = 10k
VCM = VEE to Vcc
VCM = VEE to Vcc (Note 4)
VCM = VEE to Vcc
VCM = VEE to Vcc (Note 4)
No Load
ISINK = 0.5mA
ISINK = 2.5mA
No Load
ISOURCE = 0.5mA
ISOURCE = 2.5mA
(Note 1)

MIN

TYP

•
••
••
••
•• Vcc - 0.015 Vcc - 0.006
250
73
67
71
65

1000
83
83
83
83
9
45
130

• Vcc- 0.110 Vcc- 0.055
• Vcc-0.300 Vcc-0.190
±10
350

•
•

MAX

UNITS
V/mV
dB
dB

20
80
230

550

dB
dB
mV
mV
mV
V
V
V
rnA

IJA

TA = 25°C, Vs = ±15V, VCM = OV, Vo = OV, unless otherwise noted.
SYMBOL PARAMETER
Vos

Input Offset Voltage (LT1366/LT1368)
Input Offset Voltage (LT1367/LT1369)

fNos

IB
LiIB
los
Lilos

Input Offset Voltage Shift (LT1366/L T1368)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
Input Bias Current
Input Bias Current Shift
Input Offset Current
Input Offset Current Shift
Input Bias Current Match (Channel to Channel)

CIN
AVOL

Input Capacitance
Large-Signal Voltage Gain

SR

Channel Separation
Slew Rate (LT1366/L T1367)
Slew Rate (LT1368/L T1369)

CMRR

PSRR

2-20

Common-Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
Power Supply Rejection Ratio
PSRR Match (Channel to Channel)

CONOITIONS

MIN

VCM = Vcc
VCM = VEE
VCM = Vcc
VCM = VEE
VCM = VEE to Vcc
VCM = VEE, VCC (Notes 4, 5)
VCM = VEE to Vcc
VCM = VEE, VCC (Notes 4, 5)
VCM = Vcc
VCM = VEE
VCM = VEE to Vcc
VCM = Vcc
VCM = VEE
VCM = VEE to Vcc
VCM = Vcc (Note 4)
VCM = VEE (Note 4)

0
-35

Va = -14.7V to 14.7V, RL = 10k
Va = -10Vto 10V, RL = 2k
Va = -10V to 10V, RL = 2k
Av = -1, RL = Open, Va =±10V,
Measured at Va = ±5V
Av = -1, RL = Open, Va = ±10V,
Measured at Va = ±5V

2000
1000
120

VCM = VEE to Vcc
VCM = VEE to Vcc (Note 4)
VCM = VEE to Vcc
VCM = VEE to Vcc (Note 4)
Vs = ±5V to ±15V
Vs = ±5V to ±15V (Note 4)

0
0

95
89
93
87
90
84

TYP

MAX

UNITS

200
200

700
700
1000
900
500
1300
650
2000
35
0
70
6
6
6
12
12

IlV
IlV
IlV
IlV
IlV
IlV
IlV
IlV
nA
nA
nA
nA
nA
nA
nA
nA
pF
V/mV
V/mV
dB

200
200
150
300
150
300
10
-10
20
1.0
0.3
1
1
1
7.1
10000
10000
135
0.13

V/JlS

0.065

V/JlS

106
106
106
106
110
105

dB
dB
dB
dB
dB
dB

LT1366/LT1367
LT1368/LT1369
ELEnRICAL CHARAOERISTICS
rA =25°C, Vs =±15V, VCM =OV, Vo =OV, unless otherwise noted.
;YMBOL PARAMETER
Output Voltage Swing LOW

10l

10H

Output Voltage Swing HIGH

sc
S

Short·Circuit Current
Supply Current per Amplifier

TYP
MAX
UNITS
V
VEE + 0.006 VEE + 0.012
V
VEE + 0.040 VEE + 0.070
V
VEE + 0.240 VEE + 0.500
V
Vcc - 0.008 Vcc - 0.004
V
Vcc - 0.100 Vcc - 0.050
V
Vcc - 0.800 Vcc - 00400
mA
±30
±75
385
550
IJA

CONDITIONS
No Load
ISINK = 0.5mA
ISINK = 10mA
No Load
ISOURCE = 0.5mA
ISOURCE = 10mA
(Note 1)

MIN

1°C < TA < 70°C, Vs =±15V, VCM =OV, Vo =OV, unless otherwise noted.
;YMBOL PARAMETER
Input Oflset Voltage (LT1366/LT1368)
los

Input Offset Voltage (LT1367/LT1369)

los TC

Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
Input Oflset Voltage Drift

B

Input Bias Current

~IB

Input Bias Current Shift
Input Offset Current

Wos

os
~Ios

'VOL

Input Offset Current Shift
Input Bias Current Match (Channel to Channel)
Large-Signal Voltage Gain

'Ol

Channel Separation
Common-Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
Power Supply Rejection Ratio
PSRR Match (Channel to Channel)
Output Voltage Swing LOW

'OH

Output Voltage Swing HIGH

,C

Short-Circuit Current
Supply Current per Amplifier

:MRR

'SRR

,

L7lJD~

CONDITIONS

VCM = Vcc
VCM = VEE
VCM = Vcc
VCM = VEE
VCM = VEE to Vcc
VCM = VEE, Vcc (Notes 4, 5)
VCM = VEE to Vcc
VCM = VEE, VCC (Note 4, 5)
(Note 2)
VCM = VCC
VCM = VEE
VCM = VEE to Vcc
VCM = Vcc
VCM = VEE
VCM = VEE to Vcc
VCM = Vcc (Note 4)
VCM = VEE (Note 4)
Vo = -14.7Vto 14.7V, Rl = 10k
Vo=-10Vt010V, Rl=2k
Vo = -10Vto 10V, Rl = 2k
VCM = VEE to Vcc
VCM = VEE to Vcc (Note 4)
VCM = VEE to Vcc
VCM = VEE to Vcc (Note 4)
Vs = ±5V to ±15V
Vs = ±5V to ±15V (Note 4)
No Load
ISINK = 0.5mA
ISINK = 10mA
No Load
ISOURCE = 0.5mA
ISOURCE = 10mA
(Note 1)

MIN

••
•
•
•
•

••

•
••
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
••
•
••
•

0
-45

0
0
1500
1000
110
95
89
92
86
80
75

TYP
250
250

MAX
850
850

250
250
200
300
200
300
2
15
-10
25
2
1
2
2
1
6000
6000
135
103
103
103
103
105
100

1150
1000
525
1500
750
2300
8
45
0
90
15
15
15
15
15

UNITS

IlV
IlV
IlV
IlV
IlV
IlV
IlV
IlV
llV/oC

VEE + 0.009 VEE + 0.014
VEE + 0.045 VEE + 0.080
VEE + 0.300 VEE + 0.600
Vcc- 0.01 Vcc- 0.005
Vcc-0.11 Vcc- 0.055
Vcc- 0.95 Vcc- 0.500
±30
360
575

nA
nA
nA
nA
nA
nA
nA
nA
V/mV
V/mV
dB
dB
dB
dB
dB
dB
dB
V
V
V
V
V
V
mA

IJA

2-21

•

LT1366/LT1367
LT1368/LT1369
ELEORICAL CHARACTERISTICS
-40°C < TA < 85°C (Note 3), Vs = ±15V, VCM = OV, Vo = OV, unless otherwise noted.
SYMBOL PARAMETER
Input Offset Voltage (LT1366/LT1368)

Vas

Input Offset Voltage (LT1367/LT1369)

tNos

Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)

MIN

CONDITIONS

=VCC
=VEE
VCM =Vcc
VCM =VEE
VCM =VEE to Vcc
VCM =VEE, VCC (Notes 4,5)
VCM =VEE to Vcc
VCM =VEE, VCC (Notes 4,5)
VCM
VCM

Vas TC

Input Offset Voltage Drift

(Note 2)

IB

Input Bias Current

AlB

Input Bias Current Shift

VCM =Vcc
VCM =VEE
VCM =VEE to Vcc

los

Input Offset Current

VCM =Vcc
VCM =VEE

Alas

Input Offset Current Shift

VCM
VCM
VCM

Input Bias Current Match (Channel to Channel)
AVOL

Large-Signal Voltage Gain
Channel Separation

CMRR

Common-Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
Common-Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)

PSRR

Power Supply Rejection Ratio
PSRR Match (Channel to Channel)

VOL

Output Voltage Swing LOW

VOH

Output Voltage Swing HIGH

Ise

Short-Circuit Current

Is

Supply Current per Amplifier

=VEE to VCC
=Vcc (Note 4)
=VEE (Note 4)
Va =-14.7V to 14.7V, RL =10k
Va =-1 OV to 10V, RL =2k
Va =-1 OV to 10V, RL =2k
VCM =VEE to Vcc
VeM =VEE to Vee (Note 4)
VCM =VEE to Vcc
VCM =VEE to Vcc (Note 4)
Vs =±5Vto ±15V
Vs =±5V to ±15V (Note 4)
No Load
ISINK =0.5mA
ISINK =10mA
No Load
ISOURCE =0.5mA
ISOURCE =10mA
(Note 1)

The. denotes specifications that apply over the full operating temperature
range.
Nole 1: Applies to short circuits to ground for all split supplies and for
Single supplies less than 20V. Short circuits to either supply for supplies
greater than 20V total may permanently damage the part. A heat sink may
be required to keep the junction temperature below the absolute maximum
rating when the output is shorted indefinitely.
Nole 2: This parameter is not 100% tested.

2-22

••
••
••
•
•
•
•
•
•
•
•
•
••
•
•
•
••
•
•
•
•

••
•
•

0
-45

TYP

MAX

UNITS

250
250

1000
1000

I·N
/lV

250
250

1350
1200

/lV
/lV

200
300

700
2000

/lV
/lV

200
300

800
2700

2

8

/lV
/lV
/lV/oC

45
-10

80
0

nA
nA

55

125

nA

4
1

30
20

nA
nA

4

30

nA

0
0

4
1

30
20

nA
nA

1000
800

6000
6000

V/mV
V/mV

110

130

dB

92
86

103
103

dB
dB

91
85

103
103

dB
dB

80
75

105
100

dB
dB

VEE + 0.009 VEE + 0.020
VEE + 0.045 VEE + 0.080
VEE + 0.300 VEE + 0.600

V
V
V

Vcc - 0.015 Vce - 0.006

0.110 Vcc- 0.055
• VCC- 1.100 Vcc - 0.550
• VCC ±30
385

V
V
V

mA
600

JlA

Note 3: At -40°C and 85°C, the LT1366, LT1367, LT1368, and LT1369 are
neither tested nor quality assurance sampled. The specifications indicated
are guaranteed by design; correlated, and/or inferred from the O°C, 25°C,
and 70°C tests.
Nole 4: Matching parameters are the difference between amplifiers A and
D and between Band Con the LT1367/LT1369; between the two amplifiers
on the LT1366/LT1368.
Nole 5: Input offset voltage match is the difference in offset voltage
between amplifiers measured at both VCM =VEE and VCM =Vcc.

LTl366/LT1367
LTl368/LT1369
rYPICAl PERFORmAnCE CHARAOERISTICS
:The data presented here applies to the lT1366/LT1367/lT1368/LT1369 unless otherwise noted.)
PNP Stage Vos Distribution
(lT1366/lT1368)

NPN Stage Vos Distribution
(lT1366/lT1368)

AVos-Shill Between PNP and NPN
Stages (lT1366/lT1368)

25

~

25

~

20 f-+--+-+--l-++

Z

15 H-++-+-+

:s

10 f-+--+-+-+

ffi
ffi

::>

:s

15 H-++-+-+

-350 -250 -150 -50 50 150 250
INPUT OFFSET VOLTAGE (~V)

10

iii

ffi

1-++-1-+

o

350

-350 -250 -150 -50 50 150 250
INPUT OFFSET VOLTAGE (~V)

Supply Current vs Temperature

~

c
J

~
~

1

vs~±1L
Vs = 5V, ov

300

-350 -250 -150 -50 50 150 250
INPUT OFFSET VOLTAGE (~V)

ffi

u::

400 ' - - I-- r-J=-5L

~
ffi

300

LJc

VS=5V,OV

~
~

TA-125°C

"'-

~ 200

:5!

~

200

,,c

::>
u

~ 100

~ 100

cc

m

5

A

\},m!._.-+-----1

-5

: ~

J u!

TA = 125 ~........,.

................1
I--+-->F"-t-+--I"'H--+---l

Ji -- -- - ,}

-15 I---+'M=-I--+_-+--I--+_--I

::>

o

-50-35 -20 -5 10 25 40 55 70 85 100
TEMPERATURE (OC)

I

TA =,25 0 C

Hi



11111

II

0.01
0.1
1
LOAD CURRENT (mA)

10

LT1366TPC07

L7lJ!J~

2-23

•

LT1366/LT1367
LT1368/LT1369
TYPICAL PERFORmAnCE CHARAOERISTICS
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted;)
O.1Hz to 10Hz
Output Voltage Noise

Minimum Supply Voltage
200

~

L. . TA1=WC

100

t;;

~

o

~

VS=5V,OV
60

TA = 70°C

w

§;

V~ =i.2.5J
-VCM=OV

jl

:;;d 150 r--

w

!Ir,f

'I~ 11 "

I

= 25°C

co

~

.

50

~

~~ ~MI I'll .AA lib I~h ,~ ~U
., lMI II~Ir

rl
t'~ /-L J

50

~
'-'

Noise Voltage Spectrum
70

w

co 40

~

I' I'

0

r-~

30

>
w
en
is
z

~M=4V

VCM - 2.5V

20

NONrurt;!ION~L TAI- 5r

10
10
100
FREQUENCY (Hz)

TIME (1 S/DlV)
TOTAL SUPPLY VOLTAGE (V)

1000

LT1366TPC11

Gain and Phase Shift vs
Frequency (LT1366/LT1367)

Noise Current Spectrum
0.8

70
V =5V,OV

0.7

@'

0.6

;

0.5

w

1\

50

\

~

0.3

~ 0.2

r--... ....

o

1

~

90
80

z

SlLa

II:

~

o

liml

i11t

10
100
FREQUENCY (Hz)

1000

-30

-40

\
10k

-60
10M

lOOk
1M
FREQUENCY (Hz)

I'-

11l1li
I 11111\

.... ,

~

a.
a.

"'

:::l

~
II:
Z

0

-ZOSITIVE SUPPLY
60

........

~

............

ex:

~ 20

1M

;:;J

-nGiliIilISUTi

o

lk

:::l

.m

-20

r\.

1\ POSITIVE SUPPLY

60

\

.......

40

1\

II:

~ 20

r-.....~

10k
lOOk
FREQUENCY (Hz)

Vs=±2.5V

en
~

1M
LT1368TPC17

2-24

80

II:

40

~

10k
lOOk
FREQUENCY (Hz)

&3

.....

a.
a.

en

30

="

~

-40
-60
10M

lOOk
1M
FREQUENCY (Hz)

"

;; 100

80

@

60

20
0

120

~

~

lk

10k

lk

iE"

II:

Z
0

40

PSRR vs Frequency
(LT1368/LT1369)
Vr±2.5V

iE"

;; 100

........

00

~-

f-+++tttttt-+++tttttt\..-"t-~I~II~,Iu.--,-,-\.I-J.UUI
f-+++++fltt-Htl+tttt--+~+Ul'llnltttt-llt\t+ttIHI

-30
-40
-50

r--.

r-

120

:;

Iii

~

0

PSRR vs Frequency
(LT1366/LT1367)

70

20

-20

I\,
lk

140

1'<+
\++++HlI-++1+HH1-+++++1IlI 80 ~
10 H-f++fIIlI---N-++HHl-H++HHl-++tHflHI 60

§;-20

-20

~~=±2.5V

~ 20 f-

i'
<

~-10

-10

---r"TTTTrm-T"TlTTll1T---r"TTTTlm

~

-++tH1HI-+++tt CL = O.lI'F
120
30 H+fIi.H*--H-++HHl-H++HHl-++tHflHI 100

100

-

co
~ 10
§; 0

Vs =±2.5V

~ 50
~ 40

8

50 r40

~

120

Q

140
120

GAIN

CMRR vs Frequency
(LT1366 and LT1367)
~110
52 100

'V~ =±2.5V

~ 20

VC~,~ 2.5V

0.1 I--

IIII'

i'
30
;;;:

z

II:
II:

PHASE

~40

\

en
is 0.4

11111 I
11111 I

60

Gain and Phase Shift vs
Frequency (LT1368/LT1369)

NEGATIVE SUPPLt{-

o

lk

V

10k
lOOk
FREQUENCY (Hz)

1M

LT1366/LT1367
LT1368/LT1369
rYPICAL PERFORmAnCE CHARACTERISTICS
The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)
Gain-Bandwidth and Phase
Margin vs Supply Voltage
(LT1366/LT1367)
500
450

-r

. . . rr

400
350 -

Channel Separation vs Frequency

GBW

60

-50

54

-60

l>

;;;:

30 ~

200

uj-l10
z

150

24 Z
C
18m

100

12

"'-130

'"

50

6

-140

o

0

-150

10
15
20
SUPPLY VOLTAGE (V)

25

30

0

Y.J-~T13rIWlr

~-120

II
100
lk
FREQUENCY (Hz)

10

RL = 2k

L t:"".. . /

!:::;
>

I A'

CJ)

10

;l!

LT1368/LT1369

fri-100

250

o

~
w

~ -90
a::

36 ~

Vs = 5V:'OV

RL = 10k

r\

N

~

-10
-15

II II

-20
-20 -15 -10 -5 0
5 10
OUTPUT VOLTAGE (V)

10k

15

20

Overshoot vs Load Current
(LT1368/LT1369)

60.---,---,--,---,
Vs =±2.5V
50 Av=l

80
70

"l'

!::i
-5
a.

Overshoot vs Load Current
(LT1368/LT1369)

Capacitive Load Handling
(LT1366/LT1367)

Vs = ±15V

15

i'o -80

42 ~

300

VS=±15V""
VOUF ±1Vp_p
RL = 2k

iii' -70

48

I- PHASE MARGIN

Open-Loop Gain
20

60.---,---,--,---,
Vs = ±15V
Av= 1
50

60
~

50
40

40 1----t-+-t+tr-1t-=--,--'---I

g 30

Av= 1

:I:

~

Av=V

30

-

20
10

~ 201----t-r~~~~~---I

V
1/

o

10

AWII

100
lk
10k
CAPACITIVE LOAD (pF)

0""----'--"----'--'-----"--"------'

lOOk

-10

-5
LOAD CURRENT (mA)

10

-5
0
5
LOAD CURRENT (mA)

LT136STPC22

LT1366TPC24

Slew Rate vs Supply Voltage

l

~0.16

80

1--+-+-+-1---+-+-+--1--1

~

w

40

o

20

~
>

CJ)

i 0.14 f-+-+-+-I--+-+-+-I--I
,
0.10

f-+--+--+-f-+-+-+-I--f
'--..L..-'---'-_'---'---'--'-----'--'

o

4

8 12 16 20 24 28 32 36
TOTAL SUPPLY VOLTAGE (V)

10

60

~

0.12

THD + Noise vs
Peak-to-Peak Voltage

Warm-Up Drift vs Time

Av=-l
0.18 1--+-+-+-1---+-+-+--1--1

10

58 JACJAGE
Vs=±l~

'V. S

'"

t::

~ -20

w
~ -40

~
'" -60

-80

V

V

-

N8 PACKAGE
Vs = ±15V

-I 1

o

-

RL -10k
(ALL CURVES)

S8 PACKAGE_
Vs= ±2.5V

I- -J.. J

i'

f -1kHz

I

N8 PACKAGEVs = ±2.5V

't-i+-

15 30 45 60 75 90 105120 135150
TIME AFTER POWER-UP (SEC)
Ln300TPC26

~

w

CJ)

1'z5 0.1
+

CI
:I:
f-

0.01

0.001

~ VS-+l.5V

~
,;'

----r-""""

Av=l VS-+l.5V
Av- 1

"-I.

J

f::Vs =±2.5V)
Av=l
Vs -±2.5V
Av=-l

o
VIN(P-P)
LT1366TPC27

2-25

LT1366/LT1367
LT1368/LT1369
TYPICAL PERFORmAnCE CHARAOERISTICS
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)

THD + Noise vs Frequency

Large-Signal Response
(LT1366/LT1367)

Small-Signal Response
(LT1366/LT1367)

VS=±15V
UNITY-GAIN

Vs = ±15V
UNITY-GAIN

1
VS-±1.5V
VIN - 2Vp_p
RL = 10k
~ 0.1
w

en

oz

/

+

c

i'" 0.01

Av= 1
Av--1

TInT
0.001
0.001

111111

111111
0.1
1
FREQUENCY (kHz)

IrnT

100JlS/DIV

2JlS/DIV

10

APPLICATions InFORmATion
Rail-Io-Rail Operalion
The LT1366 family differs from conventional op amps in
the design of both the input and output stages. Figure 1
shows a simplified schematic of the amplifier. The input
stage consists of two differential amplifiers, a PNP stage
01/02 and an NPN stage 03/04, which are active over

different portions of the input common-mode range. Lateral devices are used in both input stages, eliminating the
need for clamps across the input pins. Each input stage is
trimmed for offset voltage. Acomplementary output configuration (023 through 026) is employed to create an
output stage with rail-to-rail swing. The amplifier is fabri-

IW

V+

-300mV

Figure 1. LT1366 Simplified Schematic Diagram

2-26

LT1366/LT1367
LT1368/LT1369
~PPLICATlons

InFORmATion

Hed on Linear Technology's proprietary complementary
ipolar process, which ensures very similar DC and AC
macteristics for the output devices 024 and 026.
simple comparator 05 steers current from current
Jurce 11 between the two input stages. When the input
Jmmon-mode voltage VCM is near the negative supply,
5 is reverse biased, and 11 becomes the tail current for
Ie PNP differential pair 01/02. At the other extreme,
hen VCM is within about 1.3V from the positive supply,
5 diverts 11 to the current mirror D3/06, which furnishes
Ie tail current for the NPN differential pair 03/04.
he collector currents of the two input pairs are combined
I the second stage, consisting of 07 through 011. Most
r the voltage gain in the amplifier is contained in this
:age. Differential amplifier 014/015 buffers the output of
Ie second stage, converting the output voltage to differ1tial currents. The differential currents pass through
ment mirrors D4/017 and D5/016, and are converted to
ifferential voltages by 018 and 019. These voltages are
so buffered and applied to the output Darlington pairs
23/024 and 025/026. Capacitors C1 and C2 form local
edback loops around the output devices, lowering the
Jtput impedance at high frequencies.

When overdriven, the amplifier draws input current that
exceeds the normal input bias current. Figures 2 and 3
show some typical overdrive currents as a function of
input voltage. The input current must be less than 1mA of
positive overdrive or less than 7mA of negative overdrive,
for the phase reversal protection to work properly. When
the amplifier is severely overdriven, an external resistor
should be used to limit the overdrive current. In addition
to overdrive protection, the amplifier is protected against
ESD strokes up to 4kV on all pins.
110
100

90
:[ 80

....
rE

70

~

60

a::

f- JEASLREb AS 'A

r--

:~

50

~ 40

~ 30
-

,

...rrT =25°C

I I
I T=85°C

<.>

~

I

FOLLOWER

I--I-- T

20

~ 70o~
I

I ',/

10

o

IT =-55°C
I

I I

-500

-300
-100 Vs 100
300
500
COMMON-MODE VOLTAGE RELATIVE TO
POSITIVE SUPPLY (mV)
LT1366f02

Figure 2. Input Bias Current vs Common-Mode Voltage

Iput Offset Voltage
ince the amplifier has two input stages, the input offset
Jltage changes depending upon which stage is active.
1e input offsets are random, but bounded voltages.
'hen the amplifier switches between stages, offset voltles may go up, down, or remain flat; but will not exceed
e guaranteed limits. This behavior is illustrated in three
stribution plots of input offset voltage in the Typical
~rformance Characteristics section.
Iferdrive Protection

"'0 circuits prevent the output from reversing polarity
hen the input voltage exceeds the common-mode range.
'hen the noninverting input exceeds the positive supply
I approximately 300mV, the clamp transistor 012 (Fig·e 1) turns on, pulling the output of the second stage low,
hich forces the output high. For inputs below the negaIe supply, diodes D1 and D2 turn on, overcoming the
Ituration of the input pair 01/02.

o
-10
-20

[-30
f-

iE

-40

.aa::

MEASURED AS A FOLLOWER

~

~ r- l -

/"

./

I

T =-55°C T = 25°C

o?--T = 70°C

50

en -60

T = 85°C

m -70

~ -80

I

;;;;

-90
-100
-110
-800

-600

-400

-200

Vs

200

COMMON·MODE VOLTAGE RELATIVE TO
NEGATIVE SUPPLY (mV)

Figure 3. Input Bias Current vs Common-Mode Voltage

2-27

LT1366/LT1367
LT1368/LT1369
APPLICATions InFoRmATion
Improved Supply Rejection in the LT1368/LT1369
The LT1368/LT1369 are variations of the LT1366/LT1367
offering greater supply rejection and lower high frequency
output impedance. The LT1368/LT1369 require a O.1J.IF
load capacitance for compensation. The output capacitance forms afilter, which reduces pickup from the supply
and lowers the output impedance. This additional filtering
is helpful in mixed analog/digital systems with common
supplies, orsystems employing switching supplies. Filtering also reduces high frequency noise, which may be
beneficial when driving AID converters.

Figure 4 shows the outputs of the LT1366/LT1368 per·
turbed by a 200mVp_p 50kHz square wave added to the
positive supply. The LT1368's power supply rejection i~
about ten times greater than that of the LT1366 at 50kHz
Note the 5-to-1 scale change in the output voltage traces
The tolerance of the external compensation capacitor i~
not critical. The plots of Overshoot vs Load Current in the
Typical Performance Characteristics section illustrate the
effect of a capacitive load.

>

~

v+

V+
(AC)

E VOUT

VOUT

§ (AC)

;,,:

:>
'"

§

2fJS1DIV

Figure 4a. LT1366 Power Supply Rejection Tesl

Figure 4b. LT1368 Power Supply Rejection Tesl

TYPICAL APPLICATiOnS
Buffering AID Converters

Vee

Figure 5 shows the LT1368 driving an LTC@1288 twochannel micropower AID Converter (ADC). The LTC1288
can accommodate voltage references and input signals
equal to the supply rails. The sampling nature of this ADC
eliminates the need for an external sample-and-hold, but
may call for a drive amplifier because of the ADC's 12~
settling requirement. The LT1368's rail-to-rail operation
and low input offset voltage make it well-suited for low
power, low frequency AID applications. Either the LT1366
or LT1368 could be used forthis application. However, for
low frequencies (f < 1kHz) the LT1368 provides better
supply rejection.

TO Jlf

LT136SFO

Figure 5. Two-Channel Low Power AID Converter

2-28

LT1366/LT1367
LT1368/LT1369
'PICAl APPLICATions
ecision Low Dropout Regulator
croprocessors and complex digital circuits frequently
ecify tight control of power supply characteristics. The
cuit shown in Figure 6 provides a precise 3.6V, 1A
tput from a minimum 3.8V input voltage. The circuit's
minal operating voltage is 4.75V ±5%. The voltage
erence and resistor ratios determine output voltage
~uracy, while the LT1366's high gain enforces 0.2% line
d load regulation. Quiescent current is about 1mA and
es not change appreciably with supply or load. All
mponents are available in surface mount packages.
e regulator's main loop consists of A1 and a logic level

T, Q1. The output is fed back to the op amp's positive
lut because of the phase inversion through Q1. The
julator's frequency response is limited by Q1's roll-off
d the phase lead introduced by the output capacitor's
ective series resistance (ESR). Two pole-zero networks
mpensate for these effects. The pole formed with R5
d C2 rolls off the gain set with the feedback network,
lile the pole formed with R7 and C3 rolls off A1's gain
ectly, which is the dominant influence on settling time.
ezeros formed with R6 and C2, and R8 and C3 provide
ase boost near the unity-gain crossover, which in-

creases the regulator's phase margin. Although not directly part of the compensation, R9 decouples the op
amp's output from Q1's large gate capacitance.
A second loop provides a fold back current limit. A2
compares the sense voltage across R1 with 50mV referenced to the positive rail. When the sense voltage exceeds
the reference, A2's output drives 01's gate positive via A1.
In current limit, the output voltage collapses and the
current limit LED (D1) turns on causing about 30mV to
drop across R3. A2 regulates Q1's drain current so thatthe
deficit between the 50mV reference and the voltage across
R3 is made up across the sense resistor. The reduced
sense voltage is 20mV, which sets the current limit to
about 400mA. As the supply voltage increases, the voltage
across R3 increases, and the current limit folds back to a
lower level. The current limit loop deactivates when the
load current drops below the regulated output current.
When the supply turns on rapidly, C1 bypasses the fold
back circuit allowing the regulatorto start-up into a heavy
load.
01 does not require a heat sink. When mounted on atype
FR4 PC board, Q1 has athermal resistance of 50°CIW. At
1.4W worst case dissipation, Q1 can operate up to 80°C.

VIN = 4.75V ±5%
10k
R7
13k

02
1N4148
5k

+-_~3..,.8·tv5k"-._ _+ - _ X~~\= 3.6V

LT1004·1.2

R5'
20k

23.2k

4.75V TO 3.6V LDO AT 1A
"1% METAL FILM
"SET RMIN BASED ON LOAD CHARACTERISTICS

Figure 6. Precision 3.6V, 1A Low Dropout Regulator

2-29

LTl 366/LTl 367
LT1368/LT1369
TYPICAL APPLICATions
High-Side Current Source
The wide-compliance current source shown in Figure 7
takes advantage of the LT1366's ability to measure small
signals near the positive supply rail. The LT1366 adjusts
01 's gate voltage to force the voltage across the sense
resistor (RSENSE) to equal the voltage from the supply to
the potentiometer's wip~r. A rail-to-rail op amp is needed
because the voltage across the sense resistor must drop
to zero when the divided reference voltage is set to zero.
02 acts as aconstant current sink to minimize error in the
reference voltage when the supply voltage varies.
Vee

voltage, circuit operation is limited by the LT1366's absc
lute maximum ratings and the output power require
ments.
'.
The circuit delivers 1Aat 200mV of sense voltage. With
5V input supply, the power dissipation is 5W. For opera
tion at 70°C ambienttemperature, the MOSFET's heat sin
must have a thermal resistance of:
8HS = 8JA SYSTEM - 8JC FET
=(125°C - 70°C)/5W -1.25°C/W
=11 °C/W -1.25°C/W
= 9.75°C/W
which is easily achievable with a small heat sink. InpL
voltages greater than 5V require the use of a larger hec
sink or a reduction of the output current.

LT1004-1.2
Q1

MTP23P06

5V < Vee < 30V
OA < ILOAD < 1A AT Vee = 5V
OmA < ILOAD < 160mA AT Vee = 30V

LT1366F07

Figure 7. High-Side Current Source

The circuit can operate over awide supply range (5V 
u

a:
U
~
a:

'"

:I:

'"

'~ '1IN=750~

60
50

¥

-

Vs=±15V

_.vs~ t'--..
..........
IINt50j

40

e

16

...

'"~

14

'"z
u

100

1311G02

1311601

Shorl-Circuit Current
vs Temperature
80

25°C

WC

TOTAL SUPPLY VOLTAGE (V)

«
.§.

1~~Ob

/

/

/

R'N-~

lill
'" V~'~~5V

g

10

~

~
~
~

'"

~

Vs =±5V
1
Vs =±15Vf-

-

1.&

'" 0.1

R'N =,l~Ok
30
-50 -25

0

25

50

TEMPERATURE

2-36

75
(OC)

100

125

6
100

lk

LOAD RESISTANCE (0)

10k

10k

lOOk

FREQUENCY (Hz)

1M

10M

LTl311
TYPICAL PERFORmAnCE CHARACTERISTICS
10

V
/1

I

0.1%/ 1mV

10mV/

350
Vs=±15V
RIN = 20k
RL = 1k
Av=-1

_

>:::>

0

-2

10mv\

-4
-6
-10

'"z
~

\0.1~

1mV

o

100

250

-

200

en

.......

--

.\
\

-8

I

f=

......

:::>
0..

~

V

/

ti>-

Vs=~5V

200
300
400
SETTLING TIME (ns)

100

500

V

L

/

230

V'

220

g 210

o

10

_V~=~~VIIIIi
VOUT = 2V STEP
RIN = 100k
_ RL = 1k

~ 200

I
1/

~ 190
z
~ 180
~ 170

,/

150

.......

/

/

240

/'

VOur= 2V STEP
300 -RIN = 100k
_ RL = 1k

~
0..

0.1% Settling Time vs
Capacitive Load

0.1% Settling Time vs
Input Capacitance

Settling Time to 0.1%, 1mV,10mV
vs Output Step

160
150

30
40
20
INPUT CAPACITANCE (pF)

140

50

1

1000

10
100
CAPACITIVE LOAD (pF)

1311 GOO

Frequency Response for
Various Input Capacitance

Gain and Phase vs Frequency
70
60

Vs

50

RL 121

40

~

30

z

20

'"

10

«

!±~V

Av = 0.2

Av= 100,}-]

11111

t.,\.

Av= 10

180

,,~

Av= 10, RIN = 2k

~

90

0 ~
en
::t:

'!i

~

I II 11111

B

'" 1\

-10

I I Iii 1111

1M
10M
FREQUENCY (Hz)

-11
iD-12

70

'"z
0

f=

til

40M

-18
100k

1M
10M
FREQUENCY (Hz)

~L = 5hoJF

CL = 1OOpF i>(

./I

'" -14

I
CLI = 10~FI

-15
-16

kr-

I CL = OpF
I 1111

-17
40M

-18
100k

Total Harmonic Distortion
vs Frequency

1M
10M
FREQUENCY (Hz)

40M

Noise Spectrum

Vs =±5V
Av= 1
RL = ()Q

1\

t-.....
......

50
:-..... NEGATIVE
30 I--

0..
0..

:::>

en

'"?i!

IINI IIII

iD-12

~ -13

CIN = 5pF
GIN',' 1pF

d I=IJJJ,

I I

CL = 200pF

«

'" -14
-15

III

0.1

Ul

'"
::;

CIN = 10pF

~

-17

90

~

-11

C,N=20PFl

«

Power Supply Rejection Ratio
vs Frequency

"'"0

-10
CIN = 50pF

~ -13

Vs =±5V
RIN = 100k
RL=2k I

-9

-16

........ ~

Av = 0.2, RIN = 100k

-8

-9 r-Ys = ±5V
RIN = 100k
-10 r-RL=2k

,.

I 111'fllll

-30
100k

-8

135

45 ~

~

Av = 100, RIN = 200nr-

Av-1, RIN-20k
-20

I

Av- 1

Frequency Response for Various
Capacitive Loads

POSI~

=

=
-

.........
.........

10

-

0

0..

-10
10k

I\.

Vs=±15V
VOUT - 6.5VRMS
Av- 1

10M

10

100

1k
10k
FREQUENCY (Hz)

I"
en

Vs =±5V
Vour= 2VRMS
Av=-1

0.001
100k
1M
FREQUENCY (Hz)

in

"-

100k

3

10

100
1k
FREQUENCY (Hz)

10k

2-37

LTl311
TYPICAL PERFORmAnCE CHARAOERISTICS
Small-Signal Response

Large-Signal Response

VS=±5V
Av=-l
RL=2k

Vs =±15V
Av=-l
Rl =2k

SimPLIFIED SCHEmATIC

. . . .-_-_-VCC

r - - -......- _ -.......--+--_--_--_----_~-

R22

10n

+

ISlAS

PTAT

BIAS

~---_++_-++-~~--~----~-~OUT

R23

10n

R16
4.5k

R19
1.5k

R20
1.5k

'---.....- ......- ......--+----...--......- -......- - - - -......--+---+--......... VEE

2-38

LT1311
APPLICATions InFoRmATion
Description

Input Characteristics

The LT1311 contains four identical current feedback amplifiers with their non inverting inputs tied together at pin
4. An external bias voltage is applied to this pin to set the
quiescent output voltage of each amplifier. Each amplifier
has an internal 20k feedback resistor between the output
and the inverting input. The amplifiers are packaged in a
14-pin SO (small outline) package with all four inverting
inputs on one side and the outputs on the other. None of
the inputs (or the outputs) are on adjacent pins for
excellent channel separation.

The inputs of the LT1311 are low impedance summing
nodes. The currentfeedbackamplifiers in the LT1311 have
an open-loop input impedance of only a few hundred
ohms and therefore the closed-loop response is fairly
independent of stray capacitance on the inputs. This is a
significant advantage over voltage feedback amplifiers
that have to be set up for a particular input capacitance.
The LT1311 settles cleanly with any input capacitance
from zero to SOpF as shown in the characteristic curves.
When the LT1311 is used to convert photo diode currents
to signal voltages, the LT1311 does not have to be located
close to the diodes.
•

The feedback resistors in the LT1311 are laser-trimmed at
wafer sortto set the current-to-voltage gain. The gain is set
to 20mV/~; the change with temperature is typically
-70ppm/o C. The gain matching of the four amplifiers is
ten times better. The input offset voltage and bias current
are trimmed as well. The trimming also minimizes the
resulting output offset drift. For more detailed circuit
information, please see the May 1995 (Volume S, Number
2) issue of Linear Technology magazine.

Supply Voltages
The LT1311 can be operated on single or split supplies.
The total supply voltage must be greater than 4V and less
than 36V. The bias voltage applied to pin 4can beanyvalue
from 2V above the negative supply to 2V below the positive
supply. The outputs can swing to within 1V of either
supply.
The LT1311 is trimmed while operating on a single 10V
supply with a bias voltage of SV; this is the equivalent of
±SV supplies with the bias at ground. Operation on a
single SV supply with a bias voltage of 2.SV results in very
similar performance. Operation on ±1SV supplies results
in Slightly more bandwidth and offset (see the electrical
tables and the characteristic curves).
Bypassing the supplies and bias voltage pins requires no
special care. For accurate settling, aO.1~capacitorwithin
an inch or two of the package works well.

L7lJIJ~

Output Characteristics
The outputs of the LT1311 are complementary emitter
followers. The outputs will swing to within 1V of the
supplies with no load, 1.2V delivering 1OmA. The outputs
are short-circuit protected with a SSmA current limit.

Voltage Gain Applications
When the LT1311 is used with external input resistors to
make an inverting voltage gain amplifier, the bandwidth
remains fairly constant for gains of 10 or less. At high
gains the bandwidth is limited by a gain bandwidth product of about 2S0MHz. See the characteristic curves for
details.
The bandwidth is also influenced by any stray capacitance
in parallel with the input resistor. The parallel stray capacitance results in azero that pushes out the bandwidth. This
is particularly noticeable with large input resistors that
give gains less than one. For example, a single 1OOk input
resistor results in a bandwidth of 14MHz but two SOk
resistors in series result in only 10MHz bandwidth.

Overload Recovery
When one or more of the outputs is driven into the rail it
will not affect the other amplifiers. However, the output
that hit the rail will generate a glitch and take one to two
microseconds to recover. Supply current will increase
2mA to 3mA for each amplifier while it is driven into
the rail.

2-39

LTl311
TYPICAL APPLICATions
Basic Optical System Focus and Tracking Signal Generation

VCC_......_
10V

.................._...;..

TRACKING
SIGNAL
(A+B)-(C+D)

2k
5V

2k

FOCUS
SIGNAL
(A+ C)- (B + D)

WORST-CASE OUTPUT DRIFT IS 120llVioC
BANDWIDTH IS 7MHz
0.1% SETTLING IS LESS THAN 250n8

8pF

1311TA04

Wide Common-Mode Range Instrumentation Amplifier

-IN

100k

1

12

R2
2k

OUT
R2'
2k
+IN .......M.........;-I
Vs =±5V VCM d18V
Vs = ±15V VCM = ±68V
BW = 5MHz, Av = 20klR2 = 10

1131TA03

RELATED PARTS
PART NUMBER

DESCRIPTION

LT1113

Dual Low Noise, Precision, JFET Input Dp Amp

LTl169

Dual Low Noise, Picoampere Bias Current,
JFET Input Op Amp

5pA Input Bias Current

LT1213/LT1214

28M Hz, 12V1J.1S, Single Supply, Dual and Quad
Precision Op Amps

Highest Bandwidth, Precision Single Supply Op Amps

LT1215/L T1216

23M Hz, 50VlJ.lS Single Supply, Dual and Quad
Precision Op Amps

Fastest Settling, Precision Single Supply Op Amps

LT1222

Low Noise, Very High Speed Op Amp

External Compensation and Output Clamping

2-40

COMMENTS
Lowest Voltage Noise FET Op Amp

INDEX
SECTION 2-AMPLIFIERS
ZERO-DRIFT OPERATIONAL AMPLIFIERS
LTC1152, Rail-to-Rai/lnput Rail-to-Rail Output Zero-Orm Op Amp ......................................................... 2-42

2-41

.~,..
J'''''-LlneJ\~D______

LTC_,.1152

TECHNOLOGY

Rail-:-to-:-Rail Input
Rail-to~Roil Output
Zero-Drift OpAmp

FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•
•
•

The LTC®1152 is ahigh performance, low power zero-drift
op amp featuring an input stage that common modes to
both power supply rails and an output stage that provides
rail-to-rail swing, even into heavy loads. The wide input
common-mode range is achieved with a high frequency
on-board charge pump. This technique eliminates the
crossover distortion and limited CMRR imposed by competing technologies. The LTC1152 is a C-Load™ of amp,
enabling it to drive any capacitive load.

Input Common-Mode Range Includes Both Rails
Output Swings Rail to Rail
Output Will Drive 1kQ Load
No External Components Required
Input Offset Voltage: 10J.lV Max
Input Offset Drift: 100nV/oC Max
Minimum CMRR: 115dB
Supply Current: 3.0mA Max
Shutdown Pin Drops Supply Current to 5~ Max
Output Configurable to Drive Any Capacitive Load
Operates from 2.7V to 14V Total Supply Voltage

APPLICATions
•
•
•
•
•
•

Rail-to-Rail Amplifiers and Buffers
High Resolution Data Acquisition Systems
Supply Current Sensing in Either Rail
Low Supply Voltage Transducer Amplifiers
High Accuracy Instrumentation
Single Negative Supply Operation

The LTC1152 shares the excellent DC performance specs
of LTC's other zero-drift amplifiers. Typical offset voltage
is 1J.lV and typical offset drift is 1OnV/oC. CMRR and PSRR
are 130dB and 120dB and open-loop gain is 130dB. Input
noise voltage is 2J.lVp_p from 0.1 Hz to 10Hz. Gain-band"
width product is 0.7MHz and slew rate is 0.5V/J.lS, all with
supply current of 3.0mA max over temperature. The
LTC1152 also includes a shutdown feature which drops
supply current to 1~ and puts the output stage in a high
impedance state.
The LTC1152 is available in 8-pin PDIP and 8-pin SO
packages and uses the standard op amp pinout, allowing
it to be aplug-in replacement for many standard op amps.
£T, LTC and LT are registered trademarks of Linear Technology Corporation.
C-Load is trademark of Linear Technology Corporation.

TYPICAL APPLICATiOn
Input and Output Waveforms
Rail-to-Rail Buffer
5V

Your
2V101V
~+--OUT

IN

OV
5V

Y,N
2V101V
1152TA01

2-42

OV

LTCl152
ABSOLUTE mAXimum RATinGS
Total Supply Voltage (V+ to V-) ............................. 14V
Input Voltage ............................ V+ + 0.3V to V- - 0.3V
Output Short-Circuit Duration (Pin 6) ............. Indefinite
Operating Temperature Range
LTC1152C ............................................... O°C to 70°C
LTC11521.......................................... -40°C to 85°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

TOP VIEW

'"""0"
-IN 2
+IN 3
V- 4

LTC1152CN8
LTC1152CS8
LTC11521N8
LTC11521S8

V+
OUT
5 CaMP
7

6

N8 PACKAGE
HEAD PDIP
S8 PACKAGE
HEAD PLASTIC so
TJMAX = 110°C. 8JA = 130°C/W (N8)
TJMAX = 110°C. 8JA = 200°CIW (S8)

S8 PART MARKING
1152
11521

Consult factory for Military grade parts.

-------------.
ELECTRICAL CHARACTERISTICS
VS = 5V, TA = operating temperature range, unless otherwise specified.

SYMBOL PARAMETER
Input Offset Voltage
~os
Average
Input Offset Drift
Was
Long-Term Offset Drift
Input Bias Current
B

CONDITIONS
TA = 25°C (Note 1)
(Note 1)
TA = 25°C (Note 2)

'os

Input Offset Current

TA = 25°C (Note 2)

In

Input Noise Voltage (Note 3)

n

'SRR

Input Noise Current
Common-Mode Rejection Ratio
Power Supply Rejection Ratio

Rs = lOOn, O.lHz to 10Hz
Rs = loon, 0.1 Hz to 1Hz
f= 10Hz
VCM = OVto 5V
Vs=3Vto12V

\VOL
JOUT

Large-Signal Voltage Gain
Maximum Output Voltage Swing (Note 4)

)R

Slew Rate
Gain-Bandwidth Product
Supply Current

~MRR

lBW
s
OSD
Icp
IlL
IIH
IN
CP
SMPL

Output Leakage Current
Charge Pump Output Voltage
Shutdown Pin Input Low Voltage
Shutdown Pin Input High Voltage
Shutdown Pin Input Current
Internal Charge Pump Frequency
Internal Sampling Frequency

RL = 10k, VOUT = 0.5V to 4.5V
RL = 1k, Vs = Single 5V
RL = lk, Vs =±2.5V
RL = lOOk, Vs = ±2.5V
RL = 10k, CL = 50pF, Vs = ±2.5V
RL = 10k, CL = 50pF, Vs = ±2.5V
No Load
Shutdown = OV
Shutdown = OV
Icp= 0

VSHDN = OV
TA = 25°C
TA = 25°C

MIN

•
•
•

•
•
•
•
•
••
•
•

TYP
±1
±10
±50
±10
±20

115
110
105
110
4.0
±2.0

2
0.5
0.6
130
120
130
4.4
2.2
±2.49
0.5
0.7
2.2
1
±10
7.3
2.5
4
-1
4.7
2.3

MAX
±10
±100
±100
±1000
±200
±500
3
1

UNITS
!LV
nV/oC
nV/..JMO
pA
pA
pA
pA
!LVp-p
!LVP-P

fN-vHz
dB
dB
dB
dB
V
V
V

3.0
5
±100

-5

V/JJfl
MHz
mA
~

nA
V
V
V
~

MHz
kHz

2-43

LTC 1152

ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
Input Offset Voltage
Vas
Average Input Offset Drift
I:Nos
Input Bias Current
18

VS = 3V, TA = operating temperature range, unless otherwise specified.

CONDITIONS
TA = 25°C (Note 1)
(Note 1)
TA = 25°C (Note 2)

MIN

los

Input Offset Current

TA = 25°C (Note 2)

en

Input Noise Voltage (Note 3)

in
CMRR

Input Noise Current
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
Maximum Output Voltage Swing (Note 4)

Rs = lOOn, O.lHzto 10Hz
Rs = loon, O.lHzto 1Hz
f= 10Hz
VCM = OVto 3V
RL = 10k, VOUT = 0.5Vto 2.5V
RL = 1k, Vs = Single 3V
RL = lOOk, Vs = ±l.SV
RL = 10k, CL = SOpF, Vs = ±l.SV
RL = 10k, CL = SOpF, Vs = ±l.SV
No Load
Shutdown = OV
Shutdown = OV
Icp=O

AVOL
VOUT
SR
GBW
Is
loso
Vcp
V1L
VIH
liN
fcp
fSMPL

Slew Rate
Gain-Bandwidth Product
Supply Current
Output Leakage Current
Charge Pump Output Voltage
Shutdown Pin Input Low Voltage
Shutdown Pin Input High Voltage
Shutdown Pin Input Current
Internal Charge Pump Frequency
Internal Sampling Frequency

VSHDN = OV
TA = 25°C
TA = 25°C

The. denotes specifications which apply over the full operating
temperature range.
Note 1: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels during automated testing.
Note 2: At T::; O°C these parameters are guaranteed by design and not
tested.
Note 3: 0.1 Hz to 10Hz noise is specified DC coupled in a 10-sec window;
0.1 Hz to 1Hz noise is specified in a 100-sec window with an RC highpass

2-44

•
•
•
•
•

•

••
•

TYP
±1
±10
±5
±10

106
2.0

2
0.75
0.6
130
130
2.S
±1.48
0.4
O.S
1.8
1
±10
4.S
1.2
2.3
-1
4.2
2.1

MAX
±10
±100
±100
±1000
±200
±500

UNITS
ltV
nVloC
pA
pA
pA
pA
ItVp-p
ItVp-p
fAl'i'HZ
dB
dB
V
V

2.5
5

VlIlS
MHz
mA

IJA
nA
V
V
V

IJA
MHz
kHz

filter at 0.1 Hz. Contact LTC factory for sample tested or 100% tested noise
parts.
Note 4: All output swing measurements are taken with the load resistor
connected from output to ground. For single supply tests, only the positive
swing is specified (negative swing will be OV due to the pull-down effect of
the load resistor). For dual supply operation, both positive and negative
swing are specified.

LTCl152
TYPICAL PERFORmAnCE CHARACTERISTICS
Common-Mode Range vs
Supply Voltage

.................

Supply Current vs Supply Voltage

..V

V

Z

:;( 2.5

"'

........

-4

~
a:

y

'-'
~

r--......

-6
-8

1

2

3

c.
c.

=>

--r-4

U)

........
5

r--

tli
a: 1.8
a:
=>
'-'
~ 1.7

/

o

2

/'

.........

...........

r--- ./

c.
c.

=>
U)
a: 1.6

~

V

POWER SUPPLY VOLTAGE (±V)

J

I-

/

1.5

1.0

6

.s

,,-/ r--

.s

§ 2.0
-2

Vs=5V
:;( 1.9

=>

::>
:;;
:;;
::>

2.0
TA = 25°C

.u

::>
:;;

Supply Current vs Temperature

3.0

0

c. 1.5

4
6
8
10 12
TOTAL SUPPLY VOLTAGE (V)

1.4
-50

14

o 25 50
TEMPERATURE (0G)

-25

75

100..1152G03

Output Short-Circuit Current vs
Supply Voltage

Output Swing vs Load Resistance
TA'= 25 lC

;

""
~

/'

4

'-

V-

3

2

40

~ SIN~LE 5~

Vr±j'5V

~

Vs =±1.5V

0.2 0.5

1

IV

'-'

r-

~

20

=>
C.

10

=>

0

TA = 25°C

'-'

:'i!
t;;

250

[Ii

\
\

\

a:

~ 200

\

=>
o

[\

c.

o

g 150

~V

l-

300

9:
w

l-

ff

:I:



JSIN~LE 3~
I

TA = 25°C

:;(

.s
I-

I I

Vs

::J
::J
::J

Vs

Open-Loop Output Resistance vs
Supply Voltage

"- .........

ffi

c.

o

17"
4
6
8
10
12
TOTAL SUPPLY VOLTAGE (V)

2 5 10 20 50 100 200
LOAD RESISTANCE (kQ)

14

r---

4
6
8
10
12
TOTAL SUPPLY VOLTAGE (V)

14
1152 GOO

Charge Pump Voltage vs
Supply Voltage

Charge Pump Voltage vs
Load Current

Input Bias Current vs Temperature
1000

Tp25°C

,.

V

I

~
i.!

..;

2

:::;

,.
::J

/

'-

~

'-

1

u

I"

-

/

VS-5V

fA = 2hoc
Vs=5V _

'~

"r-...
",-

I'

""2

/

.>

o

2

4
6
8
10
12
TOTAL SUPPLY VOLTAGE (V)

14
1152607

o0

20

40 60 80 100 120 140 160
LOAD CURRENT (~)

10
-50

-25

----

V

0
25
50
TEMPERATURE eC)

75

100

1152608

2-45

___

LTC 1152
TYPICAL PERFORmAnCE CHARACTERISTICS.
Gain and Phase Shift vs
Frequency

Common-Mode Rejection Ratio vs
Frequency

70
60

f':

50

~

~100

40 ~

30

20

"

10

Si'"

-a

.§

\

-10
-20

10k

lk

lOOk
1M
FREQUENCY (Hz)

80

I\,~ = 25°C

~

Vs =±2.5V

0

en

co 20
0

110

100

60 ~

j'\GAIN

w

>

120

80

II



150

TA~I~50C

f- Vs = ±2.5V
50 ~:ttI::t:m'JCCOMP = 1000pF

z

60 >
en
m
40

'"

\

j'\

20

\

10

lk

10k

B

.........L.J.LJ.WJ..-I....L.J.U.WL

\

50

~
0

-1

60

o

1

Gain and Phase Shift vs
Frequency
TA = 25°C
Vs =±2.5V
= O.IIlF

~

20
10

100
lk
FREQUENCY (Hz)

10k

4
6
TIME (SEC)

10
1152GI8

Small-Signal Transient Response

Large-Signal Transient Response

Vs = ±2.5V
Av=1

Vs =±2.5V
Av=1

160

CCOMP

40

z
«
co
w
co

10

180

50

30

r-+-~-r-+~--r-+-~-r-;

1162GI5

1152Gl1



40

lOOk
1M
FREQUENCY (Hz)

100

w

75

-20

II

-20

1

'" '"
'"Si 5zw

~

GAIN
-10

O.1Hz to 10Hz Input Noise

Voltage Noise vs Frequency

ro""mm-'TnTIW-rTTI~-rncnm 120

140
120 ~

"'

PH~p

t-

~

§! -10
-20
-30

0.1

80

III

~~IN
rm:
III ~
III
1

~

60 ~
40 B
20

-20
10

FREQUENCY (kHz)
1152G12

2-46

?:l
en

0

-40
0.Q1

100

1152G17

LTC 1152
APPLICATions InFoRmATion
Rail-to-Rail Operation
The LTC1152 is a rail-to-rail input common-mode range,
rail-to-rail output swing op amp. Most CMOS op amps,
including the entire LTC zero-drift amplifier line, and even
afew bipolar op amps, can and do, claim rail-to-rail output
swing. One obvious use for such a device is to provide a
unity-gain bufferforOVt05V signals running from asingle
5V power supply. This is not possible with the vast
majority of so-called "rail-to-rail" op amps; although the
output can swing to both rails, the negative input (which
is connected to the output) will exceed the common-mode
input range of the device at some point (generally about
1.5V below the positive supply), opening the feedback
loop and causing unpredictable and sometimes bizarre
behavior.
The LTC1152 is an exception to this rule. It features both
rail-to-rail output swing and rail-to-rail input commonmode range (CMR); the input CMR actually extends beyond either rail by about 0.3V. This allows unity-gain
buffer circuits to operate with any input signal within the
powersupply rails; input signal swing is limited only by the
output stage swing into the load. Additionally, signals
occurring at either rail (power supply current sensing, for
example) can be amplified without any special circuitry.

Internal Charge Pump
The LTC1152 achieves its rail-to-rail input CMR by using
a charge pump to generate an internal voltage approximately 2V higher than vt. The input stages of the op amp
are run from this higher voltage, making signals at Vt
appearto be 2V below the front end's powersupply (Figure
1). The charge pump is contained entirely within the
LTC1152; no external components are required.
About 100I1Vp-p of residual charge pump switching noise
will be present on the output of the LTC1152. This
feedthrough is at 4.7MHz, higher than the gain-bandwidth
of the LTC1152, and will generally not cause any problems. Very sensitive applications can reduce this
feedthrough by connecting a capacitor from the CP pin
(pin 8) to Vt{pin 7); a 0.1 Wcapacitor will reduce charge
pump feedthrough to negligible levels. The LTC1152 includes an internal diode from pin 8 to pin 7 to prevent
external parasitic capacitance from lengthening start-up

,

,- - - CP (PIN 8) ......::~.......-I
::;:::::O.1~F·

-:!:-IN
OUTPUT
RAIL TO RAIL
tiN
'OPTIONAL EXTERNAL
CAPACITOR TO REDUCE
CHARGE PUMP FEEDTHROUGH

Figure 1. LTC1152 Internal Block Diagram

time. This diode can stand short-term peak currents of . , .
about 50mA, allowing it to quickly charge external capaci- ~
tanceto ground orV-. Large capacitors (> 1w) should not
be connected between pin 8 and ground or V- to prevent
excessive diode current from flowing at start-up. The
LTC1152 can withstand continuous short circuits between pin 8 and Vt; however, short circuiting pin 8 to
ground or V- will cause large amounts of current to flow
through the diode, destroying the LTC1152. Don't do it.

Output Drive
The LTC1152 features an enhanced output stage that can
sink and source 10mA with a single 5V supply while
maintaining rail-to-rail output swing under most loading
conditions. The output stage can be modeled as a perfect
rail-to-rail voltage source with a resistor in series with it;
this open-loop output resistance limits the output swing
by creating a resistor divider with the output load.
The output resistance drops as total power supply voltage
increases, as shown in the typical performance curves. It
is typically 1400 with a single 5V supply, allowing a 4.4V
output swing into a 1k resistor with a single 5V supply.
Vee (PIN 7)

,

OUT (PIN 6)- -.

~RLOAD
~

...I...

~-~

Figure 2. LTC1152 Output Resistance Model

2-47

LTC 1152
APPLICATions InFoRmATion
Compensation/Bandwidth Limiting
The LTC1152 is unity-gain stable with capacitive loads up
to 1000pF. Larger capacitive loads can be driven by
externally compensating the LTC1152. Adding 1000pF
between CaMP (pin 5) and OUT (pin 6) allows capacitive
loading of upto 1~; 0.1 ~ between pins 5and 6allows the
LTC1152 to drive infinite capacitive load (Figure 3).

"::"-_-1--- OUTPUT
1N414S"

"OPTIONAL DIODES TO PREVENT
LATCH-UP WITH Cc > 1jlF

1152FOS

Figure 3. Output Compensation Connection

Large compensation capacitors can also be used to limit
bandwidth of the LTC1152. With 0.1 ~ from pin 5 to
pm 6, the LTC1152's gain-bandwidth product is reduced
from 700kHz to around 200Hz. Note that compensation
capacitors greater than 1~. can cause latch-up under
severe output fault conditions; this can be prevented by
clamping pin 5to each supply with standard signal diodes
as shown in Figure 3.
'
t~e

Shutdown
The LTC1152 includes ashutdown pin (pin 1). When this
pin is at V+, the LTC1152 operates normally. An internal
1~ pull-up keeps the pin high if it is left floating. When pin
1 is pulled low, the part enters shutdown mode; supply
current drops to 1~, all internal clocking stops and the
output enters a high impedance state. During shutdown
the voltage at the CP pin (pin 8) will drop to 0.5V belowV+.
When pin 1 is brought high again, about 1O~ will elapse
before the charge pump regains full voltage. During this
timethe LTC1152 will operate normally, butthe input CMR
may not include V+. Pin 1 is compatible with CMOS logic
running from the same supply as the LTC1152. Additionally, the input trip levels allow ground referenced CMOS
logic signals to interface directly to pin 1when the LTC1152

2-48

is running from ±5V or ±3V supplies. The internal1~
pull-up also allows pin 1 to interface with open-collectorl
open-drain devices or discrete transistors.
The high impedance output in shutdown allows several
LTC1152s to be connected together as a MUX, with their
outputs tied in parallel and the active channel selected by
using the shutdown pins. Deselected (shutdown) channels will go to high impedance at the outputs, preventing
them from fighting with the active channel. This works
best when the individual LTC1152s are connected in
noninverting feedback configurations to prevent the feedback resistors from passing signals through deselected
channels. See the Typical Applications section for acircuit
example.
Zero-Drift Operation
The LTC1152 is a zero-drift op amp. Like other LTC zero·
drift op amps, it features virtually error-free DC performance,. very little drift overtime and temperature, and very
low nOise at low frequencies. The internal nulling clock
runs at about 2.3kHz (the charge pump frequency of·
4.7MHz divided by 2048) and is synchronized to the
internal charge pump to prevent beat frequencies from
appearing atthe output. The self-nulling circuit constantly
corrects the input offset voltage, keeping it typically below
±1 J!V over the entire input common-mode range. This has
the added benefit of providing exceptional CMRR and
PSRR at low frequencies-far better than competing railto-rail op amps.
Because it uses a silmpling front end, the LTC1152 will
exhibit aliasing behavior and clock noise at frequencies
near the internal2.3kHz sampling frequency. The LTC1152
includes an internal anti-aliasing circuitto keep these error
terms to a minimum. As a rule, alias frequencies will be
down by (80dB - ACLG) in most standard amplifier configurations, where ACLG is the closed-loop gain of the
LTC1152 circuit. Clock noise is also dependent on closedloop gain; it will generally consist of spikes of about 100J!V
in amplitude, input referred. In general, these error terms
are too small to affect most applications. For a more
detailed explanation of zero-drift amplifier behavior, see
the LTC1 051/LTC1 053 data sheet.

LTCl152
APPLICATions InFoRmATion
High Precision Three-Input MUX

High Gain Amplifier with ±1.5V Supplies

...---t-- SEL1
."......-+-- OUT
Av = 10k
= BOdS

rl,.,.,........-ItA,..,..---1~- OUT

-1.5V

...-----1-- SEl2

High Side Power Supply Current Sensing
5V --.-ItAIIr1>---......- -........- - - - - -.....-

TO
MEASURED
CIRCUIT

.----+-- SEl3

OUT

>'"+-+- ~~~g~~~RENT IN

MEASUREO CIRCUIT

SELECT INPUTS ARE CMOS lOGIC COMPATlSlE.
SELECT ONLY ONE CHANNEL AT ONCE!

GND -----1~--+--------- GND

2-49

II

NOTES

2-50

.L7lJD~

SECTion 3-lnSTRumEnTATlon
AmPLIFIERS

II

3-1

INDEX
SECTION 3-INSTRUMENTATION AMPLIFIERS
INDEX ........................................................................................................................................ 3-2
SELECTION GUIDE ......................................................................................................................... 3-3
PROPRIETARY PRODUCTS
LTCI 043, Dual Instrumentation Switched Capacitor Building Block .................................................................. '9008 11-15
LTCll00, Precision, Zero Drift Instrumentation Amplifier ............................................................................,.... '9208
3-4
LT1101, Precision, Micropower, Single Supply Instrumentation Amplifier (Fixed Gain = 10 or 100) ................ '9208 3-11
LTll02, High Speed, Precision, JFET Input Instrumentation Amplifier (Fixed Gain =10 or 100) ...................... '9208 3-23
LT1193, Video Difference Amplifier, Adjustable Gain ......................................................................................... '9208 2-159
LT1194, Video Difference Amplifier, Gain of 10 ................................................................................................. '9208 2-171

3-2

INSTRUMENTATION AMPLIFIERS
Complete Instrumentation Amplifiers in 8-Pin Packages
TC11 00: Zero Offset, Drift; Gain of 100
• LLT11
01: Micropower, Single Supply; Gain of 10 or 100

• LT1102: High Speed JFET Input; Gain of 10 or 100
•
LTC1100A
Vs=±5V

PARAMETER
Offset (Max)
Offset Drift (Max)
Bias Current (Max)
Noise (0.1 Hz to 10Hz)
Gain
Gain Error (Max)
Gain Drift
Gain Nonlinearity (Max)
CMRR (G = 100)(Min)
Power Supply (Max)
Supply Current (Max)
Slew Rate
Bandwidth (G =10)

LT1101A
Vs=5V

10"V
100nVioC
50pA
1.9"Vp.p Typ
100/10 (SOL PKG)
0.05%
4ppmfOCTyp
Sppm
l04dB
Single, Dual, lBV
2.SmA
1.5V/1lS Typ
1BkHz Typ

1BO"V
211VioC
BnA
0.9"Vp.p Typ
10/100
0.05%
4ppm/oC Max
Sppm
95dB
Single, Dual, 44V
1301lA
O.OBViIlS Min
22kHz Min

Differential Voltage Amplification from a
Resistance Bridge (Single 5V Powered)
v+

LT1102A
Vs=±15V

LTC1100

BOO"V
S"VioC
40pA
2.S"Vp.p Typ
10/100
0.05%
1SppmfOC Max
14ppm
S4dB
Dual,44V
SmA
21VillS Min (B:10)
2MHzMin

LT1101/LT1102
TOP VIEW
GROUND 1
(REF)
7 OUT
G=10

R=9.2k(LT1101)
R=1.Bk(LT1102)
NB PACKAGE
JB PACKAGE
B·LEAD PDIP
B·LEAD CEROIP

JB PACKAGE
B·LEAD CERDIP

NB PACKAGE
B·LEAD PDIP

Wideband Instrumentation Amplifier
with ±150mA Output Current

II

LTC1100CS

V+= 15V _ _-I===::;;::::~-I

TOP VIEW
NC

NC

GND REF
G = 10
+CMRR 4

OUT
\

\
I
I
I

\

,

I
I
I

\

,

NC

-=-

NC

-VIN
V-

V- =-15V
MINIMUM VOLTAGE ACROSS BRIDGE = 20mV
MINIMUM SUPPLY VOLTAGE = 1.BV

VOUT
G= 10
COMP
+VIN
V+

NC

OUTPUT = ,10V INTO 750 TO 330kHz (R = 500)
,10V INTO 2000 TO 330kHz (R = 2000)
DRIVES 2.2nF CAP LOAD
GAl N= 10, DEGRADED 0.01 % DUE TO LT1 01 0

NC

Dual Precision Instrumentation Switched Capacitor Building Block: LTC1043
• Up to 120dB CMRR
• Adjustable Gain-Set by Output Op Amp
• Offset and Offset Drift as Low as Output Amp Specs
LTC1043
(USING LTC1050 AMPLIFIER)

PARAMETER
Offset
Offset Drift
Bias Current
Noise (0.1 Hzk to 10Hz)
Gain
Gain Error
Gain Drift
Gain Nonlinearity
CMRR
Power Supply
Supply Current
Slew Rate
Bandwidth

O.S"V
SOnVioC
10pA
1.B"V
Resistor Programmable
Resistor Limited 0.001% Possible
Resistor Limited <1ppm/oC Possible
Resistor Limited 1ppm Possible
120dB
Single, Dual (1SV, ±9V Max)
2mA
1mVims
10Hz

.L7lJD~

• Precise, Charge-Balanced SWitching
• Up to 5MHz Clock Rate
• Internal or External Clock
Instrumentation Amplifier

CMRR vs Frequency

5V

Your

100

I

80

60
'::"

CMRR > 120dB AT DC
CMRR > 120dB AT 60Hz
DUAlSUPPLYORSrNGlE 5V
Vas = 150I!V, GAIN" 1 + R2IR1
tNos/I:J.T,.2I!VI"C
COMMON·MODE INPUT VOLTAGE

H-+tttttlH-++fttttf-+-t+t-ttttl

H-+tttttlH-++ftttIt-+-t+t-Httl

2010LO--'--''-'.il"",L,-'--'-'-ill"'lO-:-,..L...L.LLW.11
100k
FREQUENCY OF COMMON-MODE SIGNAL (Hz)

(lTC1043 wlLT1013)

INCLUDES THE SUPPLIES

3-3

NOTES

3-4

SECTion 4-POWER PRODUCTS

II

4-1

INDEX
SECTION 4-POWER PRODUCTS
INDEX •....••••...••.....•.••...•..•...••..••..•....••••.•••••..•.••..•••..•••.••.•••..•.•.................................................... 4-2
SELECTION GUIDES ........................................................................................................................ 4-4
PROPRIETARY PRODUCTS
INDUCTORLESS DC/DC CONVERTERS .••....••.....••.....•..••••••••.•••.••...••.•••.........•..................................... 4-19
LTC1261, Switched Capacitor Regulated Voltage Inverter .................................................................... 4-20
LTC1262, 12V, 30mA Flash Memory Programming Supply ................................................................... 4-34
LTC1429, Clock-Synchronized Switched Capacitor Regulated Voltage Inverter ........................................... 4-41
LTC1550/LTC1551, Low Noise, Switched Capacitor-Regulated Voltage Inverters ..................................... 13-142
INDUCTORLESS DC/DC CONVERTERS, ENHANCED AND SECOND SOURCE
LTC660, 100mA CMOS Voltage Converter ........................................................................................ 4-53
LINEAR REGULATORS .................................................................................................................. 4-63
LT1118-2.5/L T1118-2.85/L T1118-5, Low la, Low Dropout, 800mA Source and Sink Regulators
Fixed 2.5V, 2.85V, 5V Output ....................................................................................................... 4-64
LT1175, 500mA Negative Low Oropout Micropower Regulator ............................................................... 4-68
LT1521/LT1521-3/LT1521-3.3/LT1521-5, 300mA Low Oropout Regulators with Micropower
Quiescent Current and Shutdown ...•...•.......................•...........•........................................•............. 4-79
LT1528, 3A Low Dropout Regulator for Microprocessor Applications ....................................................... 4-91
LT1529/L T1529-3.3/L T1529-5, 3A Low Dropout Regulators with Micropower Quiescent Current and Shutdown ... 4-101
LT1580/LT1580-2.5, 7A, Very Low Dropout Regulators .................................................................... 13-148
LT1584/L T1585/L T1587, 7A, 4.6A, 3A Low Dropout Fast Response Positive Regulators Adjustable and Fixed ..... 4-112
POWER AND MOTOR CONTROL ..................................................................................................... 4-125
LT1160/LT1162, Half-/Full-Bridge N-Channel Power MOSFET Drivers ...................................................... 13-3
LTC1177-5/L TC1177-12, Isolated MOSFET Drivers ............................................................................ 13-16
LT1246/LT1247, 1MHz Off-Line Current Mode PWM .......................................................................... 4-126
LT1432-3.3, 3.3V High Efficiency Step-Oown Switching Regulator Controller ........................................... 4-137
LTC1477/LTC1478, Single and Dual Protected High-Side Switches ...................................................... 13-112
SWITCHING REGULATORS ........................................................................................................... 4-145
LT1106, Micropower Step-Up DCIDC Converter for PCMCIA Card Flash Memory ........................................ 4-146
LTC1159/L TC1159-3.3/L TC1159-5, High Efficiency Synchronous Step-Down Switching Regulators .................. 4-154
LT1182/LT1183/LT1184/LT1184F, CCFL/LCD Contrast Switching Regulators ............................................. 4-172
LT1186, DAC Programmable CCFL Switching Regulator (Bits-to-NiIs™) .................................................. 4-196
LTC1265/LTC1265-3.3/LTC1265-5, 1.2A, High Efficiency Step-Down DCIDC Converters ................................ 4-212
LTC1266/L TC1266-3.3/L TC1266-5, Synchronous Regulator Controllers for N- or P-Channel MOSFETs .............. 4-228
LTC1267/LTC1267-ADJ/LTC1267-ADJ5, Dual High Efficiency Synchronous Step-Down Switching Regulators ...... 4-248
LT1302/LT1302-5, Micropower High Output Current Step-Up Adjustable and Fixed 5V DCIDC Converters ........... 4-264
LT1303/LT1303-5, Micropower High Efficiency DCIDC Converters with Low-Banery Detector
Adjustable and Fixed 5V ........................................................................................................... 4-279
LT1304/LT1304-3.3/LT1304-5, Micropower DCIDC Converters with Low-Banery Detector Active in Shutdown ..... 13-37
LT1305, Micropower High Power DCIDC Converter with Low-Banery Detector ........................................... 4-290
LT1309, 500kHz Micropower DCIDC Converter for Flash Memory .......................................................... 13-41
LT1371, 500kHz High Efficiency 3A Switching Regulator .................................................................... 4-298
LT1372/LT1377, 500kHz and 1MHz High Efficiency 1.5A Switching Regulators .......................................... 4-310
LT1373, 250kHz Low Supply Current High Efficiency 1.5A Switching Regulator .......................................... 4-322

4-2

INDEX
LT1375/LT1376, 1.5A, 500kHz Step-Down Switching Regulators ........................................................... 4-334
LTC1430, High Power Step-Down Switching Regulator Controller .......................................................... 4-360
LT1572, 100kHz, 1.25A Switching Regulator with Catch Diode ............................................................. 4-374
LTC1574/L TC1574-3. 3/L TC1574-5, High Efficiency Step-Down DC/OC Converters with Internal Schottky Diode ... 4-385
PCMCIA HOST AND CARD POWER MANAGEMENT DEViCES .................................................................... 4-393
LT1106, Micropower Step-Up DC/DC Converter lor PCMCIA Card Flash Memory ........................................ 4-146
LTC1262, 12V, 30mA Flash Memory Programming Supply ..... .............................................................. 4-34
LT1312, Single PCMCIA VPP Driver/Regulator ................................................................................ 4-394
LT1313, Dual PCMCIA VPP Driver/Regulator ................................................................................... 4-405
LTC1314/L TC1315, PCMCIA Switching Matrix with Built-In N-Channel Vce Switch Drivers ..... ................ ........ 4-415
LTC1470/LTC1471, Single and Dual PCMCIA Protected 3.3V!5V Vee Switches ........................................... 4-426
LTC1472, Protected PCMCIA Vee and VPP Switching Matrix ................................................................ 4-437
BATTERY MANAGEMENT AND CHARGING CIRCUITS ............................................................................ 4-453
LT1239, Backup Battery Management Circuit ... ............................................................................... 4-454
LTC1325, Microprocessor-Controlled Battery Management System ........................................................ 4-466
LT1510, Constant-Voltage/Constant-Current Battery Charger ............................................................. 13-120
LT1512, SEPIC Constant-CurrenVConstant-Voltage Battery Charger ..................................................... 13-130

•

4-3

I

LINEAR REGULATORS

-l

Positive

h--1

Low Dropout

I

I Adjustable I
LT1020 (0.125A)
LT1083 (7.5A)
LT1084 (5A)
LT1085 (3A)
LT1086 (1.5A)'
LT1117 (0.8A)'· "
LT1120 (0.125A)
LT1120A (0.125A)
LT1121 (0.150A)
LT1129 (0.700A) " "
LT1521 (0.3A)
LT1529 (3A)
LT1580 (7A)
LT1584 (7A)
LT1585 (4.6A)'
LT1587 (3A)'

H

I

I IFixed 2.8SV I

LT1084-3.3 (5A)
LT1085-3.3 (3A)'
LT1086-3.3 (1.5A)*
LT1117-3.3 (0.8A)"
LT1121-3.3 (0.15A)
LT1129-3.3 (0.7A)"
LT1521-3.3 (0.3A)
LT1528-3.3 (3A)
LT1529-3.3 (3A)
LT1584-3.3 (7A)
LT1585-3.3 (4.6A)'
LT1587-3.3 (3A)'

LT1086-2.85 (1.5A)
l.T1117-2.85 (0.8A)
LT1118-2.85 (0.8N-0.4A)

I

LT1584-3.45 (7A)
LT1585-3.45 (4A)'
LT1587-3.45 (3A)

LT1118 (0.8N-0.4A)
LT1580-2.5(7 A)

LT1521-3

I
I

LT1584-3.38 (7A)
LT1585-3.38 (4A)'

I

I

I

I

I
I

I

l%VREF

I

I

I

4% VREF

LM138/338 (5V)
LM150/350 (3A)
LM117/317 (1.5A)

LT117N317A (1.5)
LT138N338A (5A)
LT1083 (10A)

LT1085-3.6 (3A)'
LT1086-3.6 (1.5A)'
LT1584-3.6 (7A)
LT1585-3.6 (4A)'
LT1587-3.6 (3A)

LT123N323A (3A)
LM123/323 (3A)
LT1003 (5A)

I ILogic Controiled I
LT1005 (5V. 1A)
LT1035 (5V. 3A)
LT1036 (12V. 3A)

, Available in surface mount DO package
** Available in surface mount SOT223 package

LT1087 (3A)

Low Dropout

I

3VDropout

I
I

I
I
I Adjustable I I Fixed-SV I

I
Adjustable

I

LT1185 (3A)
LT1175 (500mA)

I
I

I

I

l%VREF

I

LT137N337A (1.5A)
LT1033 (3A)

4-4

I

4% VREF

LM1371337 (1.5A)

LT1083-12 (7.5A)
LT1084-12 (5A)
LT1085-12 (3A)
LT1 086-12 (1.5A)

I

Fixed SV

Yw /Remote
Low Dropout .1
Sense
Negative

I

LT1 083-5 (7.5A)
LT1 084-5 (5A)
LT1085-5 (3A)
LT1086-5 (1.5A)
LT1117-5 (0.8A)"
LT1118-5 (0.8N-0.4A)
LT1121-5 (0.15A)*'
LT1123 (pnp Driver)"
LT1129-5 (0.7A)"
LT1521-5 (0.3A)
LT1529-5 (3A)

I Fixed 3.0V I IFixed 3.38V I I Fixed 3.6V I I Fixed 12V I

Adjustable

-l

FixedSV

I Fixed 2.SV I

3VDropout

I

I

I Fixed 3.3V I IFixed 3.4SV I I

I

LT1175-5 (500mA)

LINEAR VOLTAGE REGULATOR SELECTION GUIDE
Positive Regulators
lOUT
125mA

PART DROPOUT MICRO- AOJUSTFIXED OUTPUT
REMOTE
NUMBER VOLTAGE POWER
ABLE VOLTAGES AVAILABLE SENSE SHUTDOWN

.JJ

..JJ
..JJ
..JJ

LT1020
LT1120

0.4V
O.4V

LT1120A

O.4V

150mA

LT1121

0.42V

300mA
500mA

LT1521

0.5V

LT317AH

3V

LT1086
LT1129

0.95V

800mA

LT1117

1.1V
2V

..JJ

..JJ
..JJ
..JJ
..JJ

.JJ
..JJ
..JJ
..JJ

3,3.3,5

..JJ

SW
S8
S8
S8, SOT223

.JJ

58, DO, SOT223
SOT223, DO

.JJ

..JJ

LT317A

3V

.JJ

LT1086

1.3V

..JJ

LT323A

2.5V

LT350A
LT1035

2.2V

5V/3A,5Vf75mA

.JJ

.JJ

LT1036

2.4V

5V175mA, 12V/3A

LT

..JJ

3.3,5

..JJ
..JJ

5

(LT317AHVK)
2.85,3.3,3.6,5,12

DO

5

..JJ

3V

..JJ
..JJ
..JJ
..JJ
..JJ
..JJ

1.3V

LT1529

0.6V
0.5V

LT1587

1.1V

LT1585
LT338A

1.1V

LT1003
LT1084

2.5V

LT1087

1.3V

7A

LT1580
LT1584

0.5V

7.5A

LT1083

1.1V
1.3V

lOA
1-400/800

LT1038
LT1118

3V
IV

5A

..JJ
..JJ
..JJ

S8, SOT223

1.5A

4A14.6A

SURFACE
MOUNT PACKAGE

.JJ

LT1005

LT1085
LT1528

LOW BATT
DETECTOR

..JJ
..JJ
..JJ
..JJ

lA

3A

HIGH
VOLTAGE

(LT317AHVH)

.JJ

.JJ

0.4V

..JJ
..JJ
..JJ

DUAL
OUTPUT

..JJ

.JJ

3V

DO (-3.3, -3.6 Only)
DO
DO

3.3, 3.45, 3.6

DO
DO ( Also 3.38, 3.45V)

3.3, 3.38', 3.45" 3.6'
5

..JJ
..JJ
..JJ
..JJ
..JJ
..JJ
..JJ

1.3V

3.3,5,12
2.5

..JJ
..JJ

3.3, 3.38, 3.45, 3.6
5,12

.JJ (S8)

2.5,2.85,5

S8, SOT-223

Negative Regulators
500mA

LT337A
LT1175

3V
O.5V

1.5A

LT337A

3V

3A

LT1033

3V

LT1185

0.8V

..JJ
..JJ
..JJ
..JJ
..JJ

..JJ

(LT337AHVH)
-5

..JJ

..JJ

S8, DO
(LT337AHVK)

..JJ

..JJ

Discrete PNP Pass Element Driver and Regulators
I

I LT1123 I O.45V I
I
I
I..JJ I
No1 all output voltage variations are available in the indicated sunace mount packages. Please consult factory for availability.
'The adjustable and fixed output 3.3V versions of the LTI585 are 4.SA rated, the rest are 4.0A.

LT1120AILT1521: Lowest Quiescent
Current, Best Efficiency

Easy 5V to Vee for New Microprocessors
LOWDrop:eg~

5V~ -+Vccforl1P

10000

(--'
8000

ILOAD = 0
VOUT =5V

r

I--- I---

I

lour

BR~NDI"M'

50

o
o

\T1~'

1.5A
3A
4A14.6A
7A
7.5A
lOA

LT1521

~
I

2

3

4

S0T223

2.5V

LT1580-2.5

-

3.3V
LTI086-3.3
LTI587-3.3
LT1585-3.3
LTI584-3.3
LT1083
2 x LT1087

3.38V

LT1585-3.38
LT1584-3.38

-

-

3.45V
LT1086
LTI587-3.45
LTI585-3.45
LTI584-3.45
LT1083
2 x LT1087

3.6V
LT1086-3.6
LT1587-3.6
LT1585-3.6
LT1584-3.6
LTI083
2 x LT1087

• Perfect for Pentlum~ Processors
5

6

7

INPUT VOLTAGE IV)

8

9 10

• SMT Packages up to 4.6A
• Three Terminal Regulators; No Design Required
• LT1580 Recommended For Up to 7A Applications; 540mV Dropout

4-5

SWITCHING REGULATOR SELECTION GUIDE
OPTIMIZEO FOR
STEP-DOWN OR
INVERTING APPLICATIONS

OPTIMIZEO FOR STEP-UP
OR FLYBACK CONFIGURATIONS

OFF-LINE
AND/OR
PWM CONTROLLERS

OSCILLATOR FREQUENCY

40kHz

60kHz
LT1270A
LT1270

lOA
8A
7.5A
5A LT1070
z
4A
LT1271
Ie
Ie
3A
::>
....
2.5A LT107l
::c
....
2A
ii
1.5A
1.25A LT1072
lA
LT1082
External
*LT1572 has built-In Schotlky diode.

100kHz

......
...

LT1171

4-6

500kHz

1MHz

100kHz

500kHz

200kHz 500kHz

1MHz

LT1074
LT137l
LT1076*
LT1373

LT1372

LTl172*

LT1l03

LT1377
LT1176*

LT1375/6

LT1l05 LT124x LT1246/47

INPUT VOLTAGE (V)
MIN
MAX

LT1070
3
LT1070HV
3
LT1071
3
LT1071HV
3
LT1072
3
LT1072HV
3
LT1074
8
LT1074HV
8
LT1076*
8
LT1076HV
8
LT1082
3
LT1170
3
LT1170HV
3
LT1171
3
LT1l71HV
3
LT1172
3
LT1172HV
3
LT1176*
8
LT1268
3
LT1269
3
LT1270A
3
LT1270
3
LT1271
3
LT1371
2.7
LT1372
2.7
LT1373
2.7
LT1375
4.7
LT1376
4.7
LT1377
2.7
*Flxed 5V output version available

250kHz

LT1268
LTl170
LT1269

'"

150kHz

40
60
40
60
40
60
40
60
40
60
75
40
60
40
60
40
60
38
30
30
30
30
30
30
30
30
25
25
30

MAX RATED

MAXIMUM
SWITCH VOLTAGE (V)

SWITCH CURRENT (A)

PACKAGES
AVAILABLE

65
75
65
75
65
75
65
75
65
75
100
65
75
65
75
65
75
38
60
60
60
60
60
35
35
35
25
25
35

5
5
2.5
2.5
1.25
1.25
5
5
2
2
1
5
5
2.5
2.5
1.25
1.25
1.25
7.5
4
10
8
4
3
1.5
1.5
2
2
1.5

K, T
K, T
K, T
K, T
K, T, N8, S8, SW16
K, T
K,Q, T
K, T
K, R, T,Y
K,R, T, Y
J8,N8,Q, T
K, T
K, T
K,Q, T
K, T
K, T,N8,S8,SW16,Q
K, T
N,SW
T,Q
SW,T
T
T
T,Q
R,SW
N8,S8
N8,S8
N8,S8
N8,S8
S8

POWER SUPPLY PRODUCTS SELECTION GUIDE
Commercial Temperature
CURRENT
(AMPS)
10.0
8.0
7.5

POS OR NEG
OUTPUT
PosAdj
Switching
Switching
Pas Fixed

Pos Adj
Switching
7.0

Pos Fixed

5.0

PosAdj
Pas Fixed

PosAdj

Switching

4.6

Pas Fixed
PosAdj

4.0

Pos Fixed

Switching

3.0

Pos"Fixed

PART NUMBER
LT1038CK
LT1270ACT
LT1270CT
LT1083CK-5
LT1083CP-5
LT1 083CK-12
LT1083CP-12
LT1083CK
LT1083CP
LT1268Ca
LT1268CT
LT1584CT-3.3
LT1584CT-3.38
LTI584CT-3.45
LT1584CT-3.6
LT1584CT
LT1003CK
LT1003CP
LTl 084CT-3.3
LT1084CK-5
LT1084CP-5
LT1084CT-5
LT1 084CK-12
LT1 084CP-12
LT1084CT-12
LT338AK LM338K
LT338AP LM338P
LT1084CK
LT1084CP
LT1084CT
LT1087GT
LT1070CK
LT1070CT
LT1070HVCK
LT1070HVCT
LT1074CK
LT1074CT
LT1074CY
LT1074HVCK
LT1074HVCT
LT1074HVCY
LT1170CK
LT1170Ca
LT1170CT
LT1170HVCT
LT1585CM-3.3
LT1585CT-3.3
LT1585CM
LT1585CT
LT1585CM-3.38
LT1585GT-3.38
LT1585CM-3.45
LT1585GT-3.45
LT1585CM-3.6
LT1585CT-3.6
LT1269Ca
LT1269CT
LT1269CS
LT1271Ca
LT1271CT
LT1587CM-3.3
LT1587CT-3.3
LT1587CM-3.45
LT1587CT-3.45
LT1587CM-3.6
LT1587CT-3.6
LT1528CT
LT1528Ca
LT1529CT
LT1529-3.3
LTf529-5
LT1529Ca
LT1529-3.3
LT1529-5
LT323AK LM323K
LT323AT
LT1085CT-3.3
LTl085CM-3.3
LT1 085CM-3.6
LT1085CT-3.6
LT1085CK-5

PACKAGE
TYPE
Sleel TO-3
TO-220
TO-220
SteelTO-3
Plastic TO-3P
Steel TO-3
Plastic TO-3P
Steel TO-3
Plastic TO-3P
Plastic DO
TO-220
Plastic TO-220
Plastic TO-220
Plastic TO-220
Plastic TO-220
Plastic TO-220
Steel TO-3
Plastic TO-3P
TO-220
Steel TO-3
Plastic TO-3P
TO-220
Steel TO-3
Plastic TO-3P
TO-220
Steel TO-3
Plastic TO-3P
Steel TO-3
Plastic TO-3P
TO-220
TO-220
Steel TO-3
TO-220
Steel TO-3
TO-220
Steel TO-3
TO-220
Head TO-220
Stee1T0-3
TO-220
Head TO-220
Steel TO-3
Plastic DO
TO-220
TO-220
Plastic DD
Plastic TO-220
PlastiC DD
Plastic TO-220
Plastic DO
Plastic TO-220
Plastic DO
Plastic TO-220
Plastic DO
Plastic TO-220
Plastic DD

TO-220
20-Lead SO
Plastic DO
TO-220
Plastic DO
PlastiC TO-220
Plastic DD
PlastiC TO-220
Plastic DO
TO-220
Head TO-220
Head DD
Head TO-220
5-Lead TO-220
Head TO-220
Head DO
Head DO
Head DO
Steel TO-3
TO-220
TO-220
Plastic DO
Plastic DO
TO-220
Steel TO-3

V,NiVDIFF
MAX
(V)

VDNOMINAL
REGULATED
OUTPUT (V)

MIU
IND
TEMP

35
30
30
30
30
30
30
30
30
30
30
7
7
7
7
7
20
20
30
30
30
30
30
30
30
35
35
30
30
30
30
40
40
60
60
45
45
45
64
64
64
40
30
40
60
7
7
7
7
7
7
7
7
7
7
30
30
30
30
30
7
7
7
7
7
7
15

1.2t033

M

2% Your Tol, Plug In Compatible wilh 317, 350, 338 Types

Adjustable

Self-Contained 60kHz PWM and 10 Amp Switch in a 5-Pin Package

Adjustable
5
5
12
12
1.2t029
1.2t029
Adjustable
Adjustable
3.3
3.38
3.45
3.3
Adjustable
5
5
3.3
5
5
5
12
12
12
1.2 to 32
1.2 to 32
1.2to 29
1.2to 29
Adjustable
1.2to 29
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable

M

Sell-Contained 60kHz PWM and 8 Amp Switch in a 5-Pin Package
Low Dropout (1.2V), 1% VOUT Tol

15
15
20
20
30
30
30
30
30

M
M,I

Low Dropout (1.2V), Pin Compatible with 317, 350, 338 Types
Self-Contained 150kHz PWM and 7.5A Switch in 5-Pin Package
Low Dropout, Fast Transient Response for Microprocessor Applications

M
M

2% VOUT Tal
Low Dropout (1.2V), 1% Your Tol

M
M
M,I

M,I
I
M
I
M
I

LT338A Has 1% VREF Tol
Low Dropout (1.2V), Pin Compatible with 317, 350, 338 Types
Low Dropout (1.2V) with Kelvin Sense
Self-Contained 40kHz PWM and 5A Switch in a5-Pin Package

Self-Contained 100kHz PWM and 5A Switch in a5-Pin Package, Step-Down
Self-Contained 100kHz PWM and 5A Switch in a 7-Pin Package, Step-Down

Adjustable

Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
3.3
3.3
Adjustable
Adjustable
3.38
3.38
3.45
3.45
3.6
3.6
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
3.3
3.3
3.45
3.45
3.3
3.3
Adjustable
Adjustable
Adjustable
3.3V
5V
Adjustable
3.3V
5V
5
5
3.3
3.3
3.6
3.6
5

FEATURE/COMMENTS

Self-Contained 100kHz PWM and 5A Switch in a5-Pin Package, Step-Down
I
M

Self-Contained 100kHz PWM and 5A Switch in a7-Pin Package, Step-Down
Self-Contained 100kHz PWM and 5A Switch in a5-Pin Package, Step-Uplflyback

I
Low Dropout, Fast Transient Response for Microprocessor Applications

low Dropout, Fast Transient Response for Microprocessor Applications

Self-Contained 100kHz PWM and 4A Switch in 5-Pin Package
Self-Contained 100kHz PWM and 4A Switch in 2D-Lead SO Pkg
Self-Contained 60kHz PWM and 4A Switch in 5-Pin Package
Low Dropout, Fast Transient Response for Microprocessor Applications

Low Dropout (O.6V at 3A), Fast Transient Response for Microprocessor
Applications
Micropower (501lA auiescent Current) Ultra Low Dropout (0.5V at 3A)

M

M,I

LT323A Has 1% Your Tol
LT323A Has 1% Your Tol
Low Dropout (1.2V), 1% VOUT Tol
Low Dropout (1.2V), 1% VOUT Tol3-Pin Suriace Mount Package
Low Dropout (1.2V), 1% Your Tol

4-7

POWER SUPPLY PRODUCTS SELECTION GUIDE
Commercial Temperature
CURRENT
(AMPS)
3.0

POS OR NEG
OUTPUT
PosFixed
PosAdj

NegAdj

Dual Pos

F~ed

Positive
Switching
2.5

2.0

Switching

Switching

1.5

Pos F~ed
Switching

0.5tul.5

PosF~ed

PosAdj

NegAdj

1.25

4-8

PosAdj
High Voltage
NegAdJ
High Voltage
Swnching

PACKAGE
PART NUMBER

lYPE

LT10B5CT-5
LT1085CK-12
LTt085CT-12
LT15B7CM
LT15B7CT
LT350AK LM350K
LT350AT LM350T
LT350AP LM350P
LT10B5CK
LT10B5CT
LTt033CK
LT1033CP
m033CT
LT11B5CT
LTt035CK
LTt035CT
LTt03SCK
LTt03SCT
LT1371CR
LTt371CS
LTt071CK
LTt071CT
LTt071 HVCK
LTI 071 HVCT
LT1171CK
LTt171CT
LTI17tHVCT
LTt17tCa
LT107SCK
LT107SCR
LT1076CT
LT107SHVCK
LT107SHVCT
LTt07SCY-5
LT107SHVCY-5
LTt07SCR-5
LT107SCY
LT107SHVCY
LTlt03CY

TO-220
TO-220
Plastic DO
TO-220
SloeITO-3
TO-220
Plastic TO-3P
Steel TO-3
TO-220
Sloe1TO-3
Plastic TO~3P
TO-220
TO-220
Sloe1T0-3
TO-220
Steel TO-3
TO-220
7-Lead DO
20-Lead SW
St..ITO-3
TO-220
St..ITO-3
TO-220
Steel TO-3
TO-220
TO-220
Plastic DO
Steel TO-3
Plastic DO
TO-220
SIeaITO-3
TO-220
Head TO-220
Head TO-220
Plastic 00
Head TO-220
Head TO-220
Head TO-220

LTI302CNB
LT1302CSB
LTI302CNB-5
LTI302CSB-5
LT10BSCT-2.85
LTt372CNB
LTt372CSB
LTt372CNB-12
LTI372CSB-12
LTt OBSCH.3
LTl0BSCM-3.3
LTlO86CT-3.S
LT10BSCM-3.S
LT10BSCK-5
LT1086CT-5
LTl086CK-12
LT108SCT-12
LT317AK LM317K
LT317AH LM317H
LT317AT LM317T
LT10BSCK
LT1086CT
LT1086CH
LT10BSCM
LT337AK LM337K
LT337AH LM337H
LT337AT LM337H
LT317AHVK LM317HVK
LT317AHVH LM317HVH
LT337AHVK LM337HVK
LT337AHVH LM337HVH
LTlO72CK
LTt072CT
LTlO72HVCK
LTt072HVCT
LT1072CJ8
LT1072CNB
LTt072CSB
LTtI72CK
LTII72CT
LTt172HVCT

B-Pin PDIP
B-Pin Plastic SO
B-PinPDIP
B-Pin Plastic SO
TO-220
B-Pln POIP
B-Pin Plastic SO
B-Pln POIP
B-Pln Plastic SO
T0-220
Plastic 00
TO-220
Plastic DO
SloeITO-3
TO-220
SI..ITO-3
TO-220
SloelTO-3
TO-39
TO-220
Sloe1TO-3
TO-22O
TO-39
Plastic DO
St..ITO-3
TO-39
T0-220
SloeITO-3
T0-39
SIo.ITO-3
TO-39
SteelTO-3
TO-220
St..ITO-3
TO-220
B-Pln CEROIP
B-Pin PDIP
B-Pin Plastic SO
St..ITO-3
T0-220
TO-220

Ste~TO-3

VlltIVOlff
MAX
(V)

VoNOMINAL
REGULATED
OUTPUT (V)

MIL!
IND
TEMP

30
30
30
7
7
35
35
35
30
30
35
35
35
35
20
20
30
30
40
40
40
40
SO
SO
40
40
SO
40
45
45
45
S4

5
12
12
Adjustable
Adjustable
1.2t033
1.2to33
t.2to33
1.2tu29
t.2t029
-1.2to-32
-1.2to-32
-1.2to-32
-2.5to-25
Two 5V Outputs
Two SVOutputs
12,5
12,5
Adjustable
Adjustable
Adjustable
Adiustable
Adlustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
5
5
5
Adjustable
Adjustable
Adjustable

I
M,I
I

64
45
S4
45
45
S4
30
10
10
5
5
30
30
30
30
30
30
30
30
30
30
30
30
30
40
40
40
30
30
30
30
40
40
40
SO
SO
50
50
40
40
60
SO
40
40
40
40
40
SO

Adiustable
Adjustable
5
5
2.B5
Adiustabl.
AdJustable
t2
12
3.3
3.3
3.S
3.S
5
5
12
12
1.2tu37
1.2tu37
1.2to37
1.2 to 29
1.2tu29
1.2tu29
1.2tu29
-1.2to-37
-1.2 tu-37
-1.2to-37
1.2t057
1.2t057
-1.2to-47
-1.2to-47
Adiustable
AdJustable
Adjustable
Adjustable
Adiustable
Adlustable
AdJustable
Adiustable

~~I~:~::

FEATURE/COMMENTS
Low Dropout (1.2V), 1% VOUT Tolerance

Low Dropout, Fast Transient Response for Microprocessor Applications
M

LT350A Has t% V", Tol

M,I
I
M

Low Dropout (t.2V), Pin Compatible with 317, 350 Types

M,I
M

Low Dropout (0.75V) with Prog Current Limn and Shutdown
Logic Controlled Main Output Voltage, 75mA Auxiliary Output

M

Logic Controlled ·12V, 3A Output, 5V, 75mA Auxiliary Output

2%VREFTOI

Sell-Contained 500kHz PWM and 3A Switch
M
I
M
I
M
I

M
I

$elf·Contained 40kHz PWM and 2.5A Switch in a 5-Pin Package

Sell-Contained 100kHz PWM and 2.5A Swnch in a 5-Pin Package
Sell-Contained 100kHz PWM and 2.5A Switch in a 5-Pln Sur MI Pack
Sen-Contained 100kHz PWM and 2A Switch
Self-Contained 100kHz PWM and 2A Switch in a 7-Pin Sur Mt Pack
Self-Contained 100kHz PWM and 2A Switch

I

Self-Contained 100kHz PWM and 2A Switch in a 5-Pin Package
100kHz PWM and 2A Switch in 7-Pin Package with Shutdown
and Fixed 5V Output
Self-Contained 100kHz PWM and 2A Switch in a 7-Pin Sur MI Pack
Self-Contained 100kHz PWM and 2A Switch in a 7-Pin Package

I

Designed for AC Una Powered Applications, Minimum External
Components Required for 75W Isolated Power Supply
Micropower Swnching Regulator Works Oown 10 2V Input and
Produces 5Vat 600mA
Micropower Switching Regulator Works Down to 2V Input and
Produces 5Vat SoomA
Intended for SCSI-2 Active Termination
Self-Contained 500kHz PWM and 1.5A Swnch in a B-Pin Package
Se~-Contained

500kHz PWM and 1.5A Switch in a B-Pin Package

Low Dropout (1.2V), t% VOUT Tol
Low Dropout (1.2V) 1% VOUT Tol
M,I
I
M,I
I
M
M

Low Dropout (1.2V), 1% VOUT Tol

M,I
I
M

Low Dropout (1.2V), 1% VR" Tol Pin-Compatible with 317 Types

M
M
M
M
M
M
M,I
I
M,I
I
M
I
M

LT317A Has 1% VR" Tol

Low Dropout (1.2V), 1% V", Tol3-Pin Suoace Mount Package
LT337A Has 1% VR" Tol
LT317AHV Has 1% VR" Tol
LT337AHV Has 1% VR" Tol
SeH-COniained 40kHz PWM and 1.25A Switch in a 5-Pin Package

Self-Contained 40kHz PWM and 1.25A SWnch
Self-Contained 100kHz PWM and 1.25A Swnch

POWER SUPPLY PRODUCTS SELECTION GUIDE
Commercial Temperature
CURRENT POS OR NEG
(AMPS)
OUTPUT
1.25

1.0

Switching

Dual Pas
Fixed
Switching

Switching

(positive Boost)
Switching
800mA

PosFixed

lOOmA

Pos

PART NUMBER
LT1172CJ8
lT1172CN8
lT1112Ca
lT1172CS8
lTf176CN8
lT1116CN8-5
LT1176CS
lT1116CS-5
LTC1265CN
LTC1265CS
LTC1265CN-3.3
l TC1265CS-3.3
l TC1265CN-5
l TC1265CS-5
LT1512CS
LT1005CK
LT1005CT
LT1013CN8
LTfOl3CS8
LTfOI3CN8-5
l T1073CS8-5
LT1013CN8-12
LT1013CS8-12
LTf082CN8
LT1082CT
LTf10lCN8
LT110ICS8
LT110ICN8-5
LT110ICS8-5
LT1107CN8-12
LT110ICS8-12
LTf108CN8
LT1108CS8
LT1108CN8-5
LT1108CS8-5
LT1108CN8-12
LT1108CS8-12
LT1109CZ-5
LT1109CZ-12
LT11 09CN8-5
LT1109CS8-12
LTf1 09CN8-5
LT1109CS8-12
LT1109ACN8
LTf1 09ACS8
LTf1 09ACN8-5
LT1109ACS8-5
LT1109ACN8-12
LT11 09ACS8-12
LT1110CN8
LT11fOCS8
LT1110CN8-5
LTf110CS8-5
LT1110CN8-12
LT11tOCS8-12
LTf111CN8
LT1111CS8
LTf111CN8-5
LT1111CSB-5
LTf111CN8-12
LTf111CS8-12
LTf1 13CN8
LT1113CS8
LTf113CN8-5
LT1113CS8-5
LT1173CN8-12
LTf173CS8-12
LT1303CN8-5
LT1303CS8-5
LT1304CN8-5
LT1304CS8-5
LT1304CN8
LT1304CS8
LT1304CN8-3.3
LTf304CS8-3.3
LT1300CN8
LTf300CS8
LTf301CN8
LT1301CS8
LT1303CN8
LT1303CS8
LT111ICST
LTf11ICST-2.85
LT1117CST-3.3
LT1117CST-5
LT1129CS8
LT1129CS8-3.3
LT1129CS8-5

PACKAGE
TYPE
8-Pin CERDIP
8-Pin PDlP
Plastic DO
a-Pin Plastic SO
8-Pin PDIP
8-Pin PDlP
20-lead SO
20-Lead SO
14-Pin PDIP
1Hin PDIP
1Hin PDlP
1Hin PDIP
14-Pin PDIP
14-Pin PDIP
16-PinSO
Steel TO-3
TO-220
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDlP
a-Pin Plastic SO
8-Pin PDIP
TO-220
8-Pin PDlP
8-Pin Plastic SO
8-Pin PDlP
8-Pin Plastic SO
8-Pin PDlP
8-Pin Plastic SO
8-Pin PDlP
8-Pin Plastic SO
8-Pin PDIP
B-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
3-Pin TO-92
3-Pin TO-92
8-Pin PDIP
B-Pin Plastic SO
8-Pin PDIP
B-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDlP
B-Pin Plastic SO
8-Pin PDlP
B-Pin Plastic SO
8-Pin PDlP
B-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDlP
B-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDlP
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
B-Pin Plastic SO
8-Pin PDlP
B-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
B-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDlP
8-Pin Plastic SO
8-Pin PDIP
8~Pin Plastic SO
3-Pin SOT-223
3-Pin SOT-223
3-Pin SOT-223
3-Pin SOT-223
8-Pin SO
8-Pin SO
8-Pin SO

VINNolFF
MAX
(V)
40
40
40
40
38
38
38
38
13
13
13
13
13
13
40
20
20
15
15
15
15
15
15
15
15
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
15
15
15
15
15
15
36
36
36
36
36
36
36
36
36
36
36
36
I
I
I
I
I
I
I
I
I
I
10
10
I
7
15
12
10
10
30
30
30

VoNOMINAL
REGULATED
OUTPUT (V)

MIL!
IND
TEMP

Adjustable

M
I

Adjustable

AdjuS1able
Adjustable
Adjustable
5
Adjustable
5
Adjustable
Adjustable
3.3
3.3
5
5
Adjus1able
Two 5V Outputs
Two 5V Outputs
Adjustable
Adjus1able
5
5
12
12
Adju!1able
Adjus1able
Adjustable
5
5
12
12
Adjustable
Adjustable
5
5
12
12
5
12
5
5
12
12
Adiustable
Adlustable
5
5
12
12
Adjustable
Adjustable
5
5
12
12
Adiustable
Adlus1able
5
5
12
12
Adjustable
Adjustable
5
5
12
12
5V
5V
5V
5V
Adiustable
Adlustable
12V
12V
3.315
3.315
5/12
5/12
Adiustable
Adjustable
Adjustable
2.85
3.3
5
Adjustable
3.3
5

FEATURE/COMMENTS
Self-Con1ained 100kHz PWM and 1.25A Sw.ch

I
Self-Con1ained 100kHz PWM and 1.2A Sw.ch in 8-Pin DIP Package
Self-Con1ained 100kHz PWM and 1.2A Swi1ch in 20-Lead SO
Micropower 1A Step-Down Switching Regulator Achieves 90% Efficiency

M

Built-In 1A Schottky Diode, otherwise similar to LT1172
logic Controlled Main Output Voltage
Micropower Switching Regulator Works Down to 1V Input. Requires
Only 3 External Components (- 5, -12 Versions)

I
I
M
M

60kHz PWM and 1A, 100VSwitch
60kHz PWM and 1A, 100VSwitch
Micropower Switching Regulator Works Down to 2V Input. Requires
Only 3 External Components (-5, -12 Versions). Optimized
forV IN ;?: 2V, Allows Use of Surface Mount Inductors.

M
Micropower Switching Regulator Works Down to 2V Input. Requires
Only 3 External Components (-5, -12 Versions) Optimized
forVIN;?:2V

Micropower Switching Regulator Works Down to 2V Input. Requires

81~y~32~~:~~fI~~~~~~~~rntsTb-~2-P~~~~~.i~n:}s~e~~i~~~ ~I~O

Offer Shutdown Feature. 12V Version Ideal for Flash Memory Vpp
Pulse Generation from 5V or 3V

Micropower Switching Regulator Works Down to 2V Input. Requires

81~~;?:32~~f2~n~~rt.,°~~~~f~~~ia~~ 2M~~~~~P~~~~!Z~~~~~tion

from 5V or 2V. Includes Shutdown Feature.

Micropower Switching Regulator Works Down to 1V Input. Requires
Only 3 External Components (-5, -12 Versions). 60kHz Oscillator
Allows Use of Surface Mount Inductors

M
I
M

Micropower Switching Regulator Works Down to 2V Input. Requires

~~I~! ~~~~~~~~~8~~irl~~~~i~~~ ~~~~n~~if~~!i~i~~~
Inductors

M
Micropower Switching Regulator Works Down to 2V Input. Requires
Only 3 External Components (-5, -12 Versions). Optimized
forVIN2:2V

Micropower Switching Regulator Works Down to 1.8V Input.
Includes low-Battery Detector

~~~~~~~~w~~~~~~~::e~~artor Works Down to 1.BV Input.

I
I

Micropower Switching Regulator Works Down to 1.BV Input. Includes
Selectable 3.3V or 5V Output and Shutdown
Micropower Switching Regulator Works Down to 1.BV Input.
Optimized for Flash Memory VPP Generation from 5V or 2V

~~~~~~~~~;~~~~~~e~~artor Works Down ot 1.BV Input.

~~I~~tas~~I:~~2~rn~~~~~~+~W;3 ~~I~~~ Package
I
I

3.3 Low Dropout Regulator, S0T-223 Package
5V Low Dropout Regulator, S0T-223 Package
Micropower Regulator With Shutdown, Dropout Voltage =O.4V,
Reverse Battery Protection in low Thermal Resistance SO-B Package

4-9

POWER SUPPLY PRODUCTS SELECTION GUIDE
Commercial Temperature
NOMINAL Mill
REGULATED
IND
OUTPUT (V) TEMP

VINIVDlFF Vo

CURRENT POS OR NEG
(AMPS)
OUTPUT
700mA

Pos

500mA

Negative

Swoching
(Positive Boost)
Switching
(Posoive Boost)
400mA

Switching

~~~~~~ewn)

300mA

Pos

150mA

Pos

125mA

PosAdj

l00mA

PosAdj

20mA 10
100mA

Swoched
Capacitor

PART NUMBER

PACKAGE
TYPE

MAX
(V)

LTII29CT
LT1129CQ
LTI129CT-3.3
LTtt29CST-3.3
LTI129CQ-3.3
LT1129CT-5
LTI129CST-5
LTI129CQ-5
LT1175CS8
LTI175CN8
LTt17SCQ
LTt175CT
LTt175CS8-5
LT1175CN8-5
LTt175CQ-5
LTt175CT-5
LTtt06CF

5-Pin TO-220
PlasticDD
5-Pin TO-220
3-Pin SOT-223
5-Pin DO
5-Pin TO-220
3-Pin SOT-223
5-Pin DO
8-Pin Plastic SO
8-Pin PDIP
5-Pln DO
5-Pin TO-220
8-Pin Plastic SO
8-Pin PDIP
5-Pin DO
5-Pin TO-220
20-Pin TSSOP

30
30
30
30
30
30
30
30
-25
-25
-25
-25
-25
-25
-25
-25
7

LT1309CS8

8-Pin Plastic SO

7

12V

LTClf74CN8
LTC1174CN8-3.3
LTC1174CN8-5
LTC1174CS8
LTC1174CS8-3.3
LTC1174CS8-5
LTClf74HVCN8
LTC1174HVCN8
LTC1174HVCN8-3.3
LTC1174HVCS8-3.3
LTC1174HVCN8-5
LTC1174HVCS8-5
LTCf574CS
LTCI574CS-3.3
LTC1574CS-5
LTC1521CS8
LTC1521 CS8-3
LTC1521 CS8-3.3
LTC1521CSB-5
LTC1521CST-3
LTC1521 CST-3.3
LTCI521CST-5
LTt121ACS8
LTtt21ACS8-3.3
LTtt21ACS8-5
LT1121CN8
LT1121CS8
LTt I 21 CN8-3.3
LTtt21 CS8-3.3
LT1121CST-3.3
LT1121CN8-5
LT1121CS8-5
LTtI21CST-5
LTt020CJ
LT1020CN
LT1020CS
LTt120CJ8
LTt120CN8
LTt120CH
LTt120ACN8
LTtt20ACS8
LT1431CJ8
LTt431CN8
LTt 431 CS8
LT1431CZ
LTt026CJ8
LTt026CN8
LTt026CH
LTt026CS8
LTC1044CJ8
LTC1044CN8
LTC1044CH
LTC1044CS8
LTC1044ACN8
LTC1044ACS8
LTC1046CN8
LTC1046CSB
LTt054CJ8
LTt054CN8
LTt054CH
LT1054CS8
LTC1144CN8
LTC1144CS8

8-Pin DIP
8-Pin DIP
8-Pin DIP
8-Pin SO
8-Pln SO
8-Pin SO
8-Pin PDlP
8-Pin PlastiC SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
16-Pin Plastic SO
16-Pin Plastic SO
16-Pin Plastic SO
8-Pin Plastic SO
8-Pin Plastic SO
8-Pin Plastic SO
8-Pin Plastic SO
3-Lead SOT-223
3-Lead SOT-223
3-Lead SOT-223
8-Lead SO
8-Lead SO
Head SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
8-Pln Plastic SO
3-Pin SOT-223
8-Pin PDIP
8-Pin PlastiC SO
3-Pin SOT-223
lHin CERDIP
lHln PDlP
16-Pln Plastic SW
8-Pin CERDIP
8-Pin PDlP
8-Pin TO-5
8-Pin PDIP
8-Pln PDIP
8-Pin CERDIP
8-Pin PDIP
8-Pin Plastic SO
TO-92
8-Pin CERDIP
8-Pin PDIP
8-Pin TO-5 Can
8-Pin SO
8-Pin CERDIP
8-Pin PDIP
8-Pin TO-5 Can
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO
8-Pin CERDIP
8-Pin PDIP
8-Pin TO-5 Can
8-Pin Plastic SO
8-Pin PDIP
8-Pin Plastic SO

13.5
13.5
13.5
13.5
13.5
13.5
f8.5
18.5
18.5
18.5
18.5
18.5
18.5
18.5
18.5
20
20
20
20
20
20
20
30
30
30
30
30
30
30
30
30
30
30
36
36
36
36
36
36
36
36
36
36
36
36

Adjustable
3.3
5
Adjustable
3.3
5
Adjustable
Adjustable
3.3
3.3
5
5
Adjustable
3.3
5
Adjustable
3
3.3
5
3
3.3
5
Adjustable
3.3
5
Adjustable
AdJustable
3.3
3.3
3.3
5
5
5
4t030
4t030
41030
4t030
4t030
4t030
4t030
4t030
2.5 to 36
2.5 to 36
2.5 to 36
2.5 to 36

10
10
10
9.5
9.5
9.5
9.5
13
13
6
6
16
16
16
16
20
20

• These devices are nonregulating converters.

I
I
I
I
I
I
I
I

FEATURE/COMMENTS
Micropower Regulator With Shutdown, Dropout Voltage = O.4V,
Reverse Battery Protection

Negative Low Dropout has low Quiescent Current, Adjustable Current Limit

Adjustable

Negative Low Dropout has Low Quiescent Current, Adiustabie Current Limit

-5
-5
-5
-5
12Vor5V

10

t The available output voltage range is dependent upon the mode of operation selected.

4-10

Adjustable
Adjustable
3.3
3.3
3.3
5
5
5
Adjustable
Adjustable
Adjustable

Thin Package and 500kHz Operation Allows use in Type I PCMCIA Cards
500kHz Operation Allows Use of Smallest Inductors! Capacitors
I

Micropower Step-Down Switching Regulator With 90% Efficiency.
Selectable 200mA or 400mA Current Limit. Intended for 6V-9V
Battery Applications

I
Micropower Step-Down Switching Regulator with
90% Efficiency and High Input Voltage Capability

Micropower Step-Down Switching Regulator with On-Chip Schottky Diode
and 90% Efficiency
Micropower Regulator With SHutdown: Ultra·Low Dropout (O.SV) and Quiescent
Current (121lA). 3-Pin Versions Have Shutdown

I
I
I

Micropower Regulator With Shutdown, Dropout Voltage = O.4V,
Reverse Battery Protection in Low Thermal Resistance SOM8 Package

:

Micropower Regulator With Shutdown, Dropout Voltage = 0.4V,
Reverse Battery Protection

i
M,I
I
I
M
I

Oropout Voltage = O.4V, 401lA 10, Reference and Comparator
Dropout Voltage = O.4V, 401lA la, Reference, Comparator, Shutdown,
8-Pin Package
g:~Pn0~~~~~~~ge = 0.4V, 201lA la, Reference, Comparator, Shutdown,

M
I
I
I
M

0.4% Initial Tolerance, 1% OVer Temperature

Dual Voltag. Converter, 10mA Output, 5V'N, ±10VouT

M
M

Voltage Converter, 20mA Output

M

t
t
t
t

I
I
I
I
M
I
M
I
I

50mA Output Current, 1651lA Supply Current, 3511 Max Output
Impedance
Voltage Converter and Regulator, l00mA Output,
25kHz Switching Rate
Voltage Converter, 20mA Output, Up to 18V Operation

POWER SUPPLY PRODUCTS SELECTION GUIDE
Battery Management and Charging
PART NUMBER
LTC1325

~rocessor

DESCRIPTION
Controlled Battery Management System

LT1510

Constant-Voltage, Constant-Current Battery Charger

LT1512

SEPIC Constant CurrenWoltage Battery Charger

PACKAGE OPTIONS
N18, SW18
S8, N16, S16
N8, S8

FEATURES
Fast Charge NiCd, NiMH, Li-Ion, or Pb-Acid Batteries Under ~ Control.
Also Provides Full Charge/Discharge Management
Charges NiCd, NiMH and Li-Ion Batteries, 1 Resistor Required to Program
Charge Current. Step-Down Topology, 200kHz Switching
SEPIC Topology Means Charger VIN can be Higher or Lower than Battery Voltage

Power Factor Correction Controllers
PART NUMBER
LT124B

DESCRIPTION
Average Current-Mode Power Factor Corrector

PACKAGE OPTIONS
N16, S16

LT1249

Average Current-Mode Power Factor Corrector

NB, SB

FEATURES
Low Line Current Distortion, >0.99 Power Factor, Synchronization,
Overvoltage Protection
Low Parts Count, Full Feature Power Factor Correction

Regulating Pulse-Width Modulators
PART NUMBER

DESCRIPTION
Off-Line Regulating Pulse Width Modulator
500kHz Regulating Pulse Width Modulators
1MHz Regulating Pulse Width Modulators
Regulating Pulse Width Modulator
Regulating Pulse Width Modulator

LTll05
LT1241 Series
LTI2461LT1247
LT15241LT3524
LT1525NLT3525A
LT1527NLT3527A
SG1524/SG3524
SG1525NSG3525A
SG1527NSG3527A
LT184613846
LT1847/3847

PACKAGE OPTIONS
N8, N14
JB, N8, S8
N8, SB
J, N, S
J, N

Regulating Pulse Width Modulator
Regulating Pulse Width Modulator
Regulating Pulse Width Modulator
Current Mode Regulating Pulse Width Modulator

J, N
J, N
J, N
J, N

FEATURES
Designed for AC Line Powered Applications
Improved Replacements for UC1842, 1843, 1844, 1845
1MHz Current Mode PWM, 1.5% VREF, 30ns Current Sense
Improved SG1524, 2% VREF, Guaranteed Oscillator Accuracy
Improved SG1525N1527A Switching Regulator with Undervoltage
Lockout, Guaranteed Long Term Stability
Industry Standard Switching Power Supply Control Circuit
More Features Than 1524 Series, 1OOmA Source/Sink Outputs
Same as SG1525A with Inverted Output Logic
Current Mode PWM with UV Lockout, Soft Start, 1% VREF, 500kHz
Operation, 200mA Totem Pole Outputs

Ultra-High Efficiency Switching Regulator Controllers
PART NUMBER
LTC1142
LTC1142HV

DESCRIPTION
Dual Step-Down Switching Regulator Controller
Dual Step-Down Switching Regulator Controller

PACKAGE OPTIONS
SSOP
SSOP

LTC1143

Dual Step-Down Switching Regulator Controller

SW16

LTC1147, LTC1147L
LTC1148, LTC1148L

Step-Down Switching Regulator Controller
Step-Down Switching Regulator Controller

N8, S8
N, S

LTC114BHV

Step-Down Switching Regulator Controller

N,S

LTC1149

Step-Down Switching Regulator Controller

N, S

LTC1159

Step-Down Switching Regulator Controller

G, N, S

LTC1266

Step-Down Switching Regulator Controller

S

LTC1267

Dual Step-Down Switching Regulator Controller

LTC1430

Step-Down Switching Regulator Controller for PCs

SSOP
S8, S16

FEATURES
Dual Synchronous Switching Regulator Controllers with both 3.3V and 5V Outputs
20V Max Input Voltage DuaI3.3V15V or Adjustable Output
Synchronous Switching Regulator
Dual Switching Regulator Controller with Low Parts Count and
both 3.3V and 5V Outputs
Low Parts Count, 90% Efficiency Using a Single External P-Channel MOSFET
Synchronized Switching Regulator Controller Using Two External
MOSFETs for 95% Efficiency. Up to 16V Inputs
Synchronized Switching Regulator Controller Using Two External
MOSFETs for 95% Efficiency. Up to 20V Inputs
Synchronized Switching Regulator Controller Using Two External
MOSFETs for 95% Efficiency. Up to 4BV Inputs
Synchronized Switching Regulator Controller Using Two External
MOSFETs for 95% Efficiency. Operation to 5V Min, 40V Max Inputs
Synchronized Switching Regulator Using Two External N-Channel
MOSFETs for 95% Efficiency. Ideal for 5V to 3.3V Applications
40V Max Input Voltage Dual 3.3V, 5V or Adjustable Output
Synchronous Switching Regulator Controller
High Current Synchronous Switching Regulator for High Current,
5V to 3.XX or 2.XX Supplies

CCFL Backlight Inverters and LCD Contrast Switching Regulator
Part
Number
LT1182
LT1183
LT11B4F
LT1184
LT1186

Package
S016
S016
S016
S016
S016

CCFL Supply?
Floating Bulb
Grounded Bulb

Y
Y
Y

Y
Y
Y

y

y
y

Brightness
Control
I,V,PWM
I,V,PWM
I,V,PWM
I,V,PWM
Digital

Regulator Drivers
BASE
DRIVE
CURRENT

PART
NUMBER

PACKAGE
TYPE

150mA

LT1123CZ

TO-92

VoNOMINAL
VIN REGULATED
MAX
OUTPUT
(V)
VOLTAGE
30

5.0

FEATURESI
COMMENTS
Requires External PNP,
1% Output Tolerance,
600jJA auiescent Current

LT110311105 Off-Line Switching Regulators
APPLICATION
Universal Off-Line
Battery Charger, Isolated Off-Line
Telecom, -48V Input Isolated
Low Voltage Isolated DC/DC (~24V)
High Voltage Isolated DC/DC

LT1105
lOW to Over 100W
OK
OK
Requires External
MOSFET
OK

LTll 03
(Internal Sense Resistor)
10Wt050W
OK
OK
Needs No
MOSFET
OK

4-11

LTC BATTERY-POWERED DC/DC CONVERSION SOLUTIONS
Inductor and Capacitor Part Numbers/Manufacturers
INDUCTOR
VALUE(~)

COILTRONICS'

COILCRAFT'

SUMIDA'

15
18
20
22
27
33
47
68
82
100
120
180
220
470

-

OT3316-153

CTX20-1
CTX20-1
CTX20-1

-

C054-150LC
C054-180LC

OT3316-223

-

-

-

OT3316-473
OT3316-683
OT3316-104
OT3316-154

CTX50-1

CTX82-1
CTX100-l
CTX100-l
CTX250-4
CTX250-4

C054-220LC
C054-270LC
C054-330LC
C074-470LC
C074-680LC
C074-820LC
CD105-101MC
C0105-121MC
COR125-181 MC
COR125-221 MC
COR125-471MC

-

-

Inductor Manufacturers
Gowanda, NY, USA
Boca Raton, FL, USA
Arlington Heights, IL, USA
Cary, IL, USA

Gowanda Elect.
Coiltronics IntI.
Sumida
Coilcraft

716-532-2234
407-241-7876
708-956-0666
800-322-2645

FAX: 716-532-2702
FAX: 407-241-9335
FAX: 708-956-0702
FAX: 708-639-1469

Capacitor Manufacturers
AVX

Myrtle Beach, SC,USA

803-946-0690

Better: OS-CON Series

Sanyo Video

San Diego, CA, USA

619-661-6322

Good: PL Series

Nichicon America Schaumberg, IL, USA

TPS Series

Best:

708-843-7500

tSurface mount mductors

Device Pinouts (DIP and SO Packages)
1 LBoUT

o

VOUdVFB*)

'LT1109AONLY

'-5,-12VERSIONS

TDRIVE 1

Linear Technology Micropower DC/DC Converter Family
DEVICE
LT1073
LT1107
LTll08
LT1109
LT1109A
LT1110
LT1111
LTC1142
LTC1142HV
LTC1143
LTC1147
LTC1148
LTC1148HV
LTC1149
LTC1159
LT1173
LTC1174
LTC1265
LTC1266
LTC1267
LT1300
LT1301
LT1302
LT1303
LT1304
LT1305
LT1309
LTC1574

4-12

(~I~) (~JIlc) I~~I
1
2
2
2
2
1
2
6
6
6
6
6
6
7
5
2
3,5
3.5
3.5
4
2
2
2
2
2
2
3,3
4

15
30
30
30
20
15
30
16
20
16
16
16
20
48
40
30
13,5
13.5
20
40
6
6
10
6
6
6
5
16

1
1
1
0.5
1
1
1
Ext.
Ext.
Ext.
Ext.
Ext,
Ext.
Ext.
Ext,
1
0.6
1
Ext.
Ext.
1
1
2
1
1
2
0,5
0.6

STEp· STEp·
UP
DOWN
X
X
X
X
X
X
X

X
X
X

X

X
X
X
X

X

X
X
X
X
X
X
X
X
X
X

X
X
X
X

X
X
X
X

(~)
95
300
110
320
320
350
300
320
320
320
160
160
160
600
300
110
450
160
170
300
120
120
200
120
120
120
500
450

LOW
BATT

SID DETECT

DROPOUT
VOLTAGE
(V)

3.3V

OUT

X
X
X

X
X
X

X

X
X
X
X

X
X
X
X
X
X

X

0
0
0
0
0
0
2
0

X
X
X
X
X

X
X
X

X
X
X

0.5
0,5
0
0

X
X

X
X
X
X

X

X
X

X
X
X

X

X

X
X

X
X

X

X
X
X
X
X
X
X
X
X

5V
OUT
X
X

X
X
X

X
X

X
X
X
X
X

X

X
X

X

X

# OF
12V
OUT ADJ PINS
X
X
8
X
X
8
X
X
8
3,8
X
X
X
X
8
X
X
8
X
8
X
16
28
28
8
X
14
X
14
16
X
16
X
X
X
X
8
X
8
X
14
16
X
X
28
8
X
8
X
8
X
8
X
8
X
B
X
8
X
16

SO
PACK
X
X
X
X

X
X
X
X
X

X
X
X
X
X
X
X
X
X

X
X
X

X
X
X

X
X
X
X

APPLICATION EXAMPLE
1 Cell 10 5V, 40mA
2 Cells 10 5V, 150mA
2 Cells 10 5V, 150mA
5V to 12VVPP, 60mA (Flash Memory)
5V to 12V VPP, 120mA (Flash Memory)
1 Cell to 5V, 40mA
2 Cells to 5V, 90mA
6-8 Cells to both 5V and 3.3V
8-10 Cells NiCad to 5V and 3,3V or ADJ
6·8 Cells to both 5V and 3,3V
6-8 Cells NiCd to 5V or 3,3V or ADJ at 1At
6·8 Cells NiCd to 5V or 3.3V at 2A
8·10 Cells NiCd to 5V or 3,3V at 2A
>8 Cells NiCd to 5V or 3,3V at 2A
,6 Cells NiCd to 5V or 3,3V at 2A
2 Cells to 5V, 90mA
9V to 5V at up to 400mA5
9V to 5V at 800mA
5V to 3.3V at lOA
>8 Cells NiCad to 5V and 3,3V or ADJ
2 Cells to 3,3V or 5V at 250mA
2 Cells to 5V or 12V at 220mA or 50mA
2 Cells to 5V at 600mA
2 Cells to 5V at 220mA
2 Cells to 5V at 220mA, LBO Active in Shutdown
Ideal for EL panel supply
3.3V or 5V to 12V VPP (PCMCIA)
9V to 5V at up to 400mA, No External Schottky
Diode Needed.

LTC BATTERY-POWERED DC/DC CONVERSION SOLUTIONS
ULTRA-HIGH EFFICIENCY REGULATORS WITH Burst Mode™ OPERATION
• Very High Efficiency: Over 95% Possible
• Current-Mode Operation for Excellent
Line and Load Transient Response
• High Efficiency Maintained Over 3 Decades of Output Current

• Short-Circuit Protection
• Very Low Dropout Operation (100% Duty Cycle)
• Dual3.3Vand 5V Outputs (LTCl142 and LTCl143)
Burst Mode is a trademark of Linear Technology Corporation.

LTC1147: Up to 95% Efficient Step-Down Regulator in 8-Pin SO
LTC1143: Dual Output (3.3V/5V), Up to 95% Efficiency Step-Down Regulator in 16-Pin SO
V,. (5.2V TO 12V)

100

~~A

OV. NORMAL
>1.5V = SHUTDOWN

'ii

90

~

85

• Low 1601JA Standby Current at Light
Loads
• Logic Controlled Micropower
Shutdown (10 < 201JA)
• Wide VIN Range: 4V to 16V
• Low Number of External Parts
• Output Can Be Externally Held High
in Shutdown
• LTCl147 Available in 8-Pin Narrow SO
Package
• LTCl147L for Low Dropout
3.3V Applications
• LTC1265 for 1.25A Internal PFET

II

95

VIN",6V

V

f-"
VIN'" 10V

13

!

80

75

II

70
0.001

0.01

0.1

LOAD CURRENT (Al

LTC1148: 95% Efficient 3.3V or 5V Battery-Powered Regulator (Synchronous Rectifier)
LTC1142: Dual Output (3.3V/5V), 95% Efficient Regulator in SSOP Package
100

VIN (5VTO 12V)

+

-:;r '.'

95
......_..rt"YVI-"'_____ VOUT
5V12A

I--r-

•
•
•
•
•
•
•

IV:~=6V

~!~~

I--~

85

80

20mA

0.2A
LOAD CURRENT

For High Current 5V to 3.3V, See LTC1266 All N-Channel Solution

2A

1601JA Standby Current at Light Loads
Micropower Shutdown: 10 < 201JA
Wide VIN Range: 4V to 18V
Short-Circuit Protection
Very Low Dropout Operation
Adaptive Non-Overlap Gate Drives
Output Can be Externally Held High
in Shutdown
• LTCl148 Available in 14-Pin Narrow
SO Package
• LTCl148L for Low Dropout
3.3V Applications

LTC1159: Highest Efficiency for V,N Up to 40V, 3.3V or 5V Output (Synchronous Rectifier)
LTC1267: Dual Output (3.3V/5V or Adjustable) in SSOP Package
V,.
100

FIGURE 1 CIRCUIT
VINJOV

90

~

,...,....,...-.AJ""""'_ 5Vf2A
VOUT

--IW-.......

>-

~

U

80

./

~

~
70

+

T

COUT

220
.'

60

0.02

• Wide VIN Range: 4V to 40V
• Logic-Controlled Micropower
Shutdown
• Adaptive Non-Overlap Gate Drives
• Available in 16-Lead Narrow
SO Package
• 2501JA Operating Current
• 201JA Shutdown Current

0.2
LOAD CURRENT (A)

4-13

LTC BATIERY-POWERED DC/DC CONVERSION SOLUTIONS
The following tables form a shortform component selection guide for a collection of commonly used batterypowered DC/DC conversion applications. No design is required since inductor, capacitor and resistor values are
completely specified. Choose the appropriate LTC DC/DC converter for your application from the following tables.
The LT1 073, LT11 07, LT11 08, LT1110, LT1111, LT1173, LTC1174, LT1303, and LT1304 all have low-battery
detection capability.

Step-Up From One Cell (1 V)
VOUT lOUT
(V) (rnA) DEVICE

Basic Step-Up Converters

L
C R
10
(!IA) (~) (~) (0) FIG COMMENTS

40 LT1073-5
95
82
100
0
40 LT1110-5
350 27
33
0
12
15 LT1073-12 95
82
100
0
15 LTlll0-12 350 27
33
0
Adjustable versions also available for VOUT up to 50V
5

1
1
1
1

1N5818

Lowest 10
Best For Surface Mount
Lowest 10
Best For Surface Mount

Step-Up From Two Cells (2V)
VOUT lOUT
(V) (rnA) DEVICE

L
C R
10
(fJA) (~) (~) (0) FIG COMMENTS

LT1300** 120 10
2 Selectable 3.3V/5V Out
100
LTl173-5
110 47
100 47
1 Lowest 10
LTllll-5
300 18
33
47
1 Surface Mount
150 LTll07-5
47
1 Surface Mount
300 33
33
LTll08-5
110 100 100 47
1 Lowest 10
2 Selectable 3.3V/5V Out
220 LT1300** 120 10
100
LT1301 ** 120 10
2 Selectable 5V!12V Out
100
*
600 LT1302
200. 10
100
Highest Power Output
12
20 LTl173-12 110 47
47
47
1 Lowest 10
LTlll1-12 300 18
22
47
1 Surface Mount
40 LTll 07-12 300 27
33
47
1 Surface Mount
LTll 08-12 110 82
100 47
1 Lowest 10
50 LT1301** 120 10
100
2 Selectable 5V/12V Out
*
120 LT1302
200 3.3
66
Highest Power Output
LT1305
120 10
100
2 High Power Output
OSee LT1302 data sheet * *For low-battery detection use LT1303 or LT1304
3.3
5

Figure 1
1N5817

400
90

90

0
0
0
0

1 Lowest 10
1 Surface Mount
1 Surface Mount
1 Lowest 10
- 2 True Shutdown
*** Fixed Frequency
*** See data sheet

Flash Memory VPP (12V) Generation
VIN
(V)

VOUT lOUT
(V) (rnA) DEVICE

L

10
(!IA) (~)

60 LTll09-12
320
33
120 LT1109A-12 320
27
200 LT1301 **
120
27
2 Cells
12
10
60 LT1109A-12 320
120
80 LT1301**
10
* * For low-battery detection use LT1303 or LT1304
5

4-14

12

1N4933

L
C R
10
(fJA) (~) (~) (0) FIG COMMENTS

LTl173-12 110 120 100
LTllll-12 300 47
33
175 LTll07-12 300 60
32
LT1108-12 110 180 100
200 LT1301** 120 33
47
250 LT1373
1000 22
47
**For low-battery detection use LT1303 or LT1304
12

Figure 2

Flash Memory VPP Generator

Step-Up From 5V To 12V
VOUT lOUT
(V) (rnA) DEVICE

*SEE TABLES FOR RECOMMENDED PART.
INDUCTOR. CAPACITOR. AND RESISTOR VALUES

3
3
2
1
2

'SEE TABLE FOR RECOMMENDED INDUCTOR
AND CAPACITOR VALUES

Figure 3

C
(Ilf) FIG COMMENTS
22
47
47
22
47

PGM

Small, SMT
Small, SMT
True Shutdown
All Surface Mount
True Shutdown

LTC BATTERY-POWERED DC/DC CONVERSION SOLUTIONS
Step-Down Conversion to 3.3V
VIN
(V)
4.5 to
12.5
4.5to
12.5
5 to
16
12 to
60

lOUT
(rnA)
200
425
200
425
2A
2A

Step-Down Converters

L
C
10
DEVICE
(1lA) (!!H) (IJF) IpGM Fig COMMENTS
LTC1174-3.3 450 50 2 x33 ToGND 5 Low Dropout,
450 50 2 x33 To VIN 5 Surface Mount
LTC1574-3.3 450 50 2 x33 ToGND 5 Low Dropout, SMT
450 50 2 x33 To VIN 5 No External Diode
- See Ultra-High
LTC1148-3.3 160 Efficiency Regs - Pg 4
- See Ultra-High
LTC1149-3.3 600 Efficiency Regs - Pg 4

'SEE TABLES FOR RECOMMENDED PART,
INDUCTOR, CAPACITOR, AND RESISTOR VALUES

Figure 4

Step-Down Conversion to 5V
VIN
(Max)

lOUT
(rnA) DEVICE

L
(j.lH)

5.5 to
12
5.5 to
16
12 to
20
20 to
30
6to
16
12to
60

200
400
200
400
300
300
300
300
2A+

100
100
100
100
60
180
470
180

C
(IJF)
2 x33
2 x33
2 x33
2 x33
100
330
470
220

-

-

-

-

10
(1lA)
LTC1174-5
450
450
LTC1574-5
450
450
LT1107-5
300
LT1108-5
110
LT1173-5
110
LT1111-5
300
LTC1147/8-5 160

2A+ LTC1149-5

600

R/
IpGM Fig COMMENTS
To GND 5 Low Dropout,
To VIN 5 Surface Mount
To GND 5 Low Dropout, SMT
To VIN 5 No External Diode
4 Surface Mount
100
100
4 Lowest 10
100
4 Lowest 10
4 Surface Mount
100
- See Ultra-High
Efficiency Regs - Pg 4
- See Ultra-High
Efficiency Regs - Pg 4

LBIN VIN
LOW 2
BATIERY LBoUT
SEE 7 IpGM
SW ,-,,5---rvv""'-"~VOUT
TABLE
LTC1174
C
LTC1574
GND

Figure 5

\djustable output voltages up to 6.2V can be obtained With the adjustable versions of
.T1173, LT1111, LT1107, LT1108, or LT1110.

~ositive-to-Negative
VIN
(V)
5

VOUT
(V)
-5

12

-5

4
8
12.5

-5

lOUT
(rnA)
75
150
250
250
110
170
235

DEVICE
LT1108-5
LT1107-5
LTC1174-5
LT1173-5
LT1111-5
LTC1574-5

Positive-to-Negative Converters

Voltage Conversion
10
(1lA)
110
300
450
110
300
450

L
C
(!!H) (IJF)
100
100
33
33
50 2 x33
470
220
180
82
50
100

R
(0)

100
100

100
100

-

Fig COMMENTS
6 Lowest 10
6
7
6
6
7

Surface Mount
Surface Mount
Lowest 10
Surface Mount
SMT, No Ext.
Schottky Diode
Required

'SEE TABLES FOR RECOMMENDED PART,
INDUCTOR, CAPACITOR, AND RESISTOR VALUES

Figure 6

280k . - - - - . . - - - . - - - . - - - - - - . - - . - - - - - - ,
(-5V)
4.7k
220k
LOW
(-3.3V)
BATIERY
INDICATOR

43k

Figure 7

L7lJn~

4-15

PCMCIA, POWER AND MOTOR CONTROL CIRCUITS

H

High Side Switch Dri ~ •.
LTC1153 - Electronic Circuit Breaker w/ Programmable Trip, Reset, Current Level
LTC1154 - Single N-Ch FET Switch Driver w/ Short-Circuit Protection
LTC1155 - Dual N-Ch FET Switch Drivers w/ Short-Circuit Protection
LTC1156 - Quad N-Ch FET Switch Drivers w/ Short-Circuit Protection
LTC1157 - Dual N-Ch FET Switch Drivers for 3.3V Operation (Also for Low Cost 5V Applications)
LT1161 - Quad High Voltage N-Channel FET Switch Drivers with Reset and Short-Circuit Portection
LTC1163 - Triple N-Ch FET Switch Drivers for 1.8V Operation (and up to 5V Applications)
LTC1165 - Triple N-Ch FET Switch Drivers for 1.8V Operation (and up to 5V Applications)
LTC1177 - UL Recognized Isolated MOSFET Driver
LTC1255 - Dual N-Ch FET Switch Drivers w/ Short Circuit Protection, 24V Operation

H

Integrated High Side Switches

I

LT1188 -1.5A HSS, Output Protected Against Inductive Kickback Controlled Slew Rate/Low RF Noise STATUS Line for Diagnostics
Protected Against Overtemp, Load Faults
LT1 089 - 7.5A HSS Low Loss, Only 1.5V at 7.5A Protected Against Overtemp, Overcurrent Low Quiescent Current
LTC1477178 - Single/Dual Protected 1.5A HSS. Low o.om ON ReSistance, Operates From 2.7V to 5.5V, No Parasitic Body Diode

y

Half-/Full-Bridge N-Ch MOSFET Drivers

I

LT1158 - 5V to 30V Operation, Drives DC Motors and Switching Power Supply N-Ch MOSFET Switch Gates, On-Chip
Charge Pump, Adaptive Anti-Shoot-Through, Fully Protected, 150ns Transition Times Driving 3000pF
LT1160 -1 OV to 60V Operation, Drives DC Motors and Switching Power Supply N-CH MOSFET Switch Gates, Adaptive Anti-Shoot
Through, 180ns Transition Times Driving 10,000pF
LT1162 - Full-Bridge Version ofLT1160
MIN
PRODUCT
lT1089
lT1106
lTC1153
lTC1154
lTC1155
lTC1156
lTC1157
lT1158
lT1160
lT1161
lT1162
lTC1163
lTC1165
lTC1177
lT1188
lTC1255
lT1312
lT1313
lTC1314
lTC1315
lTC1470
lTC1471
lTC1472

PACKAGES
TO-22O, TO-3
20-Pin TSSOP
8-Pin DIP, SO
8-Pin DIP, SO
8-Pin DIP, SO
16-Pin DIP, SO
8-Pin DIP, SO
16-Pin DIP, SO
14-Pin DIP, SO
20-Pin DIP, SO
24-Pin DIP, SO
8-Pin DIP, SO
8-Pin DIP, SO
18-Pin SO Wide
TO-220, TO-3
8-Pin DIP, SO
8-Pin SO
16-Pin SO
14-Pin SO
24-Pin SSOP
8-Pin SO
16-Pin SO
16-Pin SO

SafeSlot IS alrademark of Linear Technology Corporallon

4-16

FUNCTION
7.5A High-Side Switch
VPP Flash MemOlY Supply
Electronic Circuit Breaker
Single High Side Driver
Dual High Side Driver
Quad High Side Driver
Dua13.3V High Side Driver
Half-Bridge Driver
Half-Bridge Driver
Quad High Side Driver
Full-Bridge Driver
Triple High Side Driver
Triple High Side Driver
Isolated MOSFET Driver
1.5A High Side Switch
Dual High Side Driver
Single VPP Regulator
Dual VPP Regulator
Single VPP SwitchNee Driver
Dual VPP SwitchNee Driver
Protected Vee 5V/3V Switch
Dual Protected Vee Switch
Single VPPNee Switch

MAX

VSUPPLY

VIN

4V
5V
4.5V
4.5V
4.5V
4.5V
2.7V
4.5V
10V
8V
10V
1.8V
1.8V
5/12
5V
9V
13V
13V
5V
5V
5V
5V
5V

20V
7V
22V
22V
22V
22V
7V
36V
60V
60V
60V
6V
6V

30V
30V
20V
20V
13.2V
13.2V

-

COMMENTS
low loss, low 10
500kHz Operation, 1.1 mm Component Height
Has Adjustable Reset Time
Single Version of l TC1155
Good for Power Management
Good for Multiple Supply Switching
Good for 3.3V Power Management
Synchronous Switching Regulators Too
Dual N-Channel MOSFET Driver
Good for Industrial (24V) Applications
Dual Version of l T1160
Good for 2-Cell Power Management
Inverted logic Version of lTC1163
No Secondal)l Power Required. Ul Recognized
Good for Automotive
Good fOllndustrial (24V) Applications
SafeSlot™ Protection, low 10
SafeSlot Protection, low 10
Drives low Cost N-Channels, low 0.11JA 10
Drives low Cost N-Channels, low 0.11JA 10
Internal1A MOSFET Switches
Internal1A MOSFET Switches
Internal VPP and Vee MOSFET Switches

PCMCIA HOST AND CARD POWER SOLUTIONS
Cards

'-lost

PCMCIA Power Switching Solutions
Vee: 3.3V or 5V
VPP: ov, Vee, 12V, High-Z

On-Card OC/OC Conversion Solutions
(See pages 3-23 to 3-26)

~C Card Host Power Interface
.inear Technology PCMCIA Product Family

PCMCIA

DEVICE

DESCRIPTION

PACKAGE

LT1312
LT1313
LTC1314
LTC1315

Single PCMCIA VPP Driver/Regulator
Dual PCMCIA VPP Driver/Regulator
Single PCMCIA Switch Matrix
Dual PCMCIA Switch Matrix

8-Pin SO
16-Pin SO'
14-Pin SO
24-Pin SSOP
8-Pin SO
16-Pin SO'
16-Pin SO'

LTC1470 Protected Vee 5V/3.3V Switch Matrix
LTC1471 Dual Protected Vee 5V/3.3V Switch Matrix
LTC1472 Protected Vee and VPP Switch Matrix
Narrow Body

~TC1472

~

MEMBER COMPANY

16-Lead SO
(Narrow Body)

8-Lead SO

~14-LeadSO
(Packages Enlarged for Clarity)

Protected PCMCIA Vee and VPP SWitching Matrix

Both Vee and VPP Switching in a
Single Package
Built-In SafeSlot™ Current Limit and
VCC(OUT) 1
Thermal Shutdown
16-Pin (Narrow) SO Package
Inrush Current Limited (Drives 150J.tF
Loads)
Continuous 12V Power Not Required
Extremely Low ROS(ON) NMOS
VPP ENO 7
Switches
Guaranteed lA Vee Current and 120mA
S PACKAGE
16-LEAD PLASTIC SO
VPP Current
1!lA Quiescent Current in Standby
No External Components Required
Compatible with Industry Standard Controllers
Break-Before-Make Switching
Controlled Rise and Fall Times
Compatible with Cirrus Logic CL-PD6720, Intel 365-type and
Other PCMCIA Host Adaptor Chips
IleSlot is a trademark 01 Linear Technology Corporation.

L7lJD~

3.3V----,

5V

PCMCIA
CARD SLOT
PCMCIA
CARD SLOT
CONTROLLER

VCC EN1
GND

Vee Switch Truth Table
Vec END

Vee EN1

0

0

1

VPP Switch Truth Table

Vee(OUT)

VPPEND

VPPENl

Off

0

0

ov

0

5V

0

1

Vee IN

0

1

3.3V

1

0

VPPIN

1

1

Off

1

1

Hi-Z

VPPOUT

4-17

•

PCMCIA HOST AND CARD POWER SOLUTIONS
LTC1470/LTC1471 Single/Dual PCMCIA Protected 5V/3.3V Vee Switch
• 3.3V/5V Switching in B-Pin SO
TOP VIEW
Package
• Built-In SafeSlot Current Limit
and Thermal Shutdown
• Extremely Low ROS(ON) MOSFET
Switches
S8 PACKAGE
• 1A Output Current Capability
HEAD PLASTIC SO
• 1IlA Quiescent Current in Standby
• Built-In Charge Pump (No 12V Required)
• Compatible with Industry Standard Controllers
• Break-Belore-Make Switching
• Controlled Rise and Fall Times
• Logic Compatible with Standard PCMCIA Controllers
• LTC1470 (Single) and LTC1471 (Dual)

5V-P_---,

,....--_-3.3V

PCMCIA
PCMCIA
CARD SLOT
CONTROLLER

I--'-P_-t'-~'-l CARD SLOT

S PACKAGE
16-lEAD NARROW PlASTIC SO

LTC1314/LTC1315 Single/Dual PCMCIA Switching Matrix with Built-In
N-Channel MOSFET Vee Switch Drivers
• Output Current Capability:
120mA
• 12V Regulator Can Be Shut
Down
• Built-In N-Channel Vee
Switch Drive rs
• Digital Selection of OV.
-_ _ _ _rVCCl
Vee(IN), VPPIN or Hi-Z
S PACKAGE
• 3.3V or 5V Vee Supply
1HEAD PLASTIC SO
• Break-Before-Make Switching
• O.11lA Quiescent Current in Hi-Z or OV Mode
• No VPPOUT Overshoot
• Logic Compatible with Standard PCMCIA Controllers
• LTC1314 (Single) and LTC1315 (Dual)

AVPPIN

1

ASHDN
AENO

5V

PCMCIA
CARD SLOT
CONTROLLER

VDD

ENO
EN1

PCMCIA
CARD SLOT

I--'-t-_--IV"

G PACKAGE
2HEAD PLASTIC SSOP

3.3V

LT13121LT1313 Single/Dual PCMCIA Vee Driver/Regulator
• Digital Selection of OV, Vee.
12Vor Hi-Z
• Output Current Capability: 120mA
• Internal Current Limiting and
Thermal Shutdown
• Automatic Switching from
N8 PACKAGE
3.3Vto 5V
HEAD PDIP
S8 PACKAGE
• Powered from Unregulated
HEAD PLASTIC SO
13V to 20V Supply
• Logic Compatible with Standard PCMCIA Controllers
• Output Capacitors: 1!If
• Quiescent Current in Hi-Zor OV Mode: 601lA
• Independent VPP Valid Status Feedback Signals
No VPP Overshoot

4-18

TOP VIEW

13VTO 2DV--.--.......- - ,

DUAL PCMCIA
CARD SLOT
CONTROLLER

S PACKAGE
16-lEAD NARROW PlASTIC SO

3.3VI5V

INDEX
SECTION 4-POWER PRODUCTS
INDUCTORLESS DC/DC CONVERTERS ............................................................................................... 4-19
LTC1261, Switched Capacitor Regulated Voltage Inverter .................................................................... 4-20
LTC1262, 12V, 30mA Flash Memory Programming Supply ... ................................................................ 4-34
LTC1429, Clock·Synchronized Switched Capacitor Regulated Voltage Inverter ........................................... 4-41
LTC1550/LTC1551, Low Noise, Switched Capacitor·Regulated Voltage Inverters ..................................... 13-142
INDUCTORLESS DC/DC CONVERTERS, ENHANCED AND SECOND SOURCE
LTC660, 100mA CMOS Voltage Converter ........................................................................................ 4-53

•

L7lJn~

4-19

f""""-unt1\Q
~~ TECHNOLOG~~~-------S-W-i-tc-h-e-d-c-a-p-a-C-i-to-r
LTC 1261

Regulated Voltage Inverter
FEATURES

DESCRIPTion

• Regulated Negative Voltage from a
Single Positive Supply
• Can Provide Regulated -5V from a 3V Supply
• REG Pin Indicates Output is in Regulation
• Low Output Ripple: 5mV Typ
• Supply Current: 6001!A Typ
• Shutdown Mode Drops Supply Current to SI!A
• Up to 1SmA Output Current
• Adjustable or Fixed Output Voltages
• Requires Only Three or Four External Capacitors
• Available in SO-8 Packages

The LTC®1261 is a switched-capacitor voltage inverter
designed to provide a regulated negative voltage from a
single positive supply. The LTC1261 CS operates from a
single 3V to 8V supply and provides an adjustable output
voltage from -1.25V to -8V. An on-chip resistor string
allows the LTC1261 CS to be configured for output voltages of -3.SV, -4V, -4.SV or -5V with no external
components. The LTC1261 CS8 is optimized for applications which use aSVor higher supply orwhich require low
output voltages. It requires asingle external 0.1 J.tf capacitor and provides adjustable and fixed output voltage options in 8-pin SO packages. The LTC1261 CS requires one
or two external 0.1 J.tf capacitors, depending on input
voltage. Both versions require additional external input
and output bypass capacitors. An optional compensation
capacitor at ADJ/COMP can be used to reduce the output
voltage ripple.

APPLICATions
•
•
•
•

GaAs FET Bias Generators
Negative Supply Generators
Battery-Powered Systems
Single Supply Applications

Each version of the LTC1261 will supply up to 1SmA output
current with guaranteed output regulation of 5%. The
LTC1261 includes an open-drain REG output which pulls
low when the output is within 5% of the set value. Output
ripple is typically as low as SmV. Quiescent current is
typically 6001!A when operating and 51!A in shutdown.
The LTC1261 is available in a 14-pin narrow body SO
package and an 8-pin SO package.
£T, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn

Waveforms for -4V Generator with Power Valid

-4V Generator with Power Valid
OV
5V
5V-.---"":"

C1

C2

"~r~
'OPTIONAL

4-20

OUT

-4V
..:.....-.__-- POWER VALID

- " - - - - - p - - - ~PV6~A4V

5V
SHDN
OV
""PO=WE"'"'RV=AL~ID'5V
OV
O.2ms/DIV

LTC1261-TA02

LTC1261
~BSOLUTE
~ote

mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

1)

:upply Voltage (Note 2) ................... ......................... 9V
lutput Voltage (Note 5) .............................. 0.3V to -9V
'otal Voltage, Vee to VOUT (Note 2) ...................•.•.. 12V
lPut Voltage
SHDN Pin ................................. -0.3V to Vee + 0.3V
REG Pin ............................................... -0.3V to 12V
ADJ, Ro, R1, RADJ ............... VO UT - 0.3V to Vee + 0.3V
lutput Short-Circuit Duration ......................... Indefinite
Iperating Temperature Range .................... O°C to 70°C
:torage Temperature Range ................ -65°C to 150°C
,ead Temperature (Soldering, 10 sec) ................. 300°C

TOP VIEW

··o'~"

C1+ 2 '
cr3
GND 4 ,

REG
6 OUT
5 ADJ (COMP")
7

ORDER PART
NUMBER
LTC1261CS8
LTC1261 CS8-4
LTC1261 CS8-4.5
S8 PART MARKING

S8 PACKAGE
8·LEAD PLASTIC SO
"FOR FIXED VERSIONS

1261
12614
126145

TJMAX =150'C, 9JA= 150'C/W

TOP VIEW

~ Vee

NC IT
C1+ IT
C1-@: ,
C2+ [i
C2- IT'
GND [§:
RO IT

~
~
~
j!QJ

[!l

PJ

ORDER PART
NUMBER

SHDN
REG
OUT
ADJ
RADJ
R1

LTC1261CS

SPACKAGE
14-LEAD PLASTIC SO
TJMAX =150'C, 9JA= 110'C/W
"
Consult factory for Industrial or Military
grade parts,

:LECTRICAL CHARACTERISTICS

Vee =3V to 6.5V, TA =25°C unless otherwise specified.
DOC ::;;TA ::;;70°C

YMBOL
REF

ISC
,FF
)L
EG
OJ
H
L
~

N

PARAMETER
Reference Voltage
Supply Current

CONDITIONS
No Load, SHDN Floating
No Load, VSHDN = Vcc

Internal Oscillator Frequency
Power Efficiency
REG Output Low Voltage
IREG=lmA
REG Sink Current
VREG = 0.8V, Vee = 3,3V
VREG = 0,8V, Vce = 5.0V
Adjust Pin Current
VADJ = 1.24V
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
VSHDN = Vcc
Turn-On Time
lour: 15mA

L7lJD~

•
••
•
••
•
•

•
•

MIN
1.20

5
8

TYP
1.24
600
5
550
65
0.1
8
15
0.01

MAX
1.28
1000
20

0,8

1

2
5
500

0.8
20

-40°C ::;;TA ::;;85OC
(Nole 7)
TYP
MAX
MIN
1,20
1,24
1.28
1500
600
5
20
550
65
0.1
0.8
5
8
15
8
0,01
1
2
0.8
5
25
500

UNITS
V

!lA
!lA
kHz
%
V
rnA
rnA

!lA
V
V

!lA
IJS

4-21

LTC 1261

ELECTRICAL CHARACTERISTICS
Doubler Mode. Vee =5V ±1D%, C1 =D.1JJf, C2 =0 (Note 4), COUT = 3.3JJf unless otherwise specified.
DOC::; TA::; 7DoC
SYMBOL PARAMETER
Output Regulation
AVOUT

VOUT

Isc
VRI?

Output Voltage
(Note 6)

Output Short-Circuit Current
Output Ripple Voltage

CONOITIONS (Nole 2)
-1.24V;:,VOUT;:,-4V, O~ IOUT~ 10mA
-4V;:, VOUT;:' -5V, 0 ~ lOUT ~ 10mA (Note 6)
-1.24V;:, VOUT;:' -4V, 0 ~ lOUT ~ 8mA
-4V;:, VOUT;:' -5V, 0 ~ lOUT ~ 8mA (Note 6)
VOUT Set to -3.5V, 0 ~ lOUT ~ 15mA
VOUT Set to -4V, 0 ~ lOUT ~ 10mA
VOUT Set to -4.5V, 0 ~ lOUT ~ 10mA
VOUT Set to -5V, 0 ~ lOUT ~ 10mA
VOUT Set to -4V, 0 ~ lOUT ~ 8mA
VOUT Set to -4.5V, 0 ~ lOUT ~ 8mA
VOUT Set to -5V, 0 ~ lOUT ~ 8mA
VOUT =OV
lOUT =5mA, VOUT =-4V

MIN

•
•
••

•
••
•

-3.33
-3.80
-3.80
-3.80

TYP
1
2

-3.5
-4.0
-4.5
-5.0

60
10

MAX
5

-40°C ::;TA::; 85°C
(Nole 7)
MIN TYP
MAX

-3.68 -3.33
-4.20
-4.73
-5.25
-3.80
-3.80
-3.80
125

1
2
-3.5

-4.0
-4.5
-5.0
60
10

5
-3.68

-4.20
-4.73
-5.25
125

UNITS
%
%
%
%
V
V
V
V
V
V
V
mA
mV

LTC1261CS Only. Tripier Mode. Vee = 2.7V, C1 = C2 = D.1JJf (Note 4), COUT = 3.3JJf unless otherwise specified.
DOC ::;TA ::;7DoC
SYMBOL PARAMETER
Output Regulation
AVOUT
Output Voltage
VOUT
Isc
VRI?

CONDITIONS (Nole 2)
-1.24V;:, VOUT;:' -4V, 0 ~ lOUT ~ 5mA
VOUT Set to -3.5V, 0 ~ lOUT ~ 6mA
VOUT Set to -4V, 0 ~ lOUT ~ 5mA
Output Short-Circuit Current VOUT =OV
Output Ripple Voltage
lOUT =5mA, VOUT =-4V

MIN

•
••

-3.33
-3.80

•

TYP
1
-3.5
-4.0
25
5

-4DoC::; TA::; 85°C
(Nole 7)
MAX
MIN TYP
MAX
5
1
5
-3.68 -3.33 -3.5 -3.68
-4.20 -3.80 -4.0 -4.20
75
25
75
5

UNITS
%
V
V
mA
mV

LTC1261CS Only. Tripier Mode. Vee = 3.3V ±1D%, C1 = C2 = D.1JJf (Note 4), COUT = 3.3JJf unless otherwise specified.
DOC ::;TA::;7DoC
SYMBOL PARAMETER
Output Regulation
AVOUT
VOUT

Isc
VRI?

CONDITIONS (Nole 2)
-1.24V;:, VOUT;:' -4V, 0 ~ louT ~ 12mA
-4V;:, VOUT;:' -5V, 0 ~ lOUT ~ 8mA
Output Voltage
VOUT Set to -3.5V, 0 ~ lOUT ~ 15mA
VOUT Set to -4V, 0 ~ lOUT ~ 12mA
VOUT Set to -4.5V, 0 ~ lOUT ~ 10mA
VOUT Set to -5V, 0 ~ lOUT ~ 8mA
VOUT Set to -5V, 0 ~ lOUT ~ 6mA
Output Short-Circuit Current VOUT = OV
Output Ripple Voltage
lOUT = 5mA, VOUT = -4V

MIN

••
••

••
•
•

-3.33
-3.80
-4.28
-4.75

TYP
1
2
-3.5
-4.0
-4.5
-5.0
35
5

-4DoC ::;TA::; 85°C
(Nole 7)
MAX
MIN TYP MAX
5
1
5
5
2
-3.68 -3.33 -3.5 -3.68
-4.20 -3.80 -4.0 -4.20
-4.73 -4.28 -4.5 -4.73
-5.25
-4.75 -5.0 -5.25
75
35
75
5

UNITS
%
%
V
V

V
V
V
mA
mV

LTC1261CS Only. Tripier Mode. Vee = 5V ±1D%, C1 = C2 = D.1JJf (Note 4), COUT = 3.3JJf unless otherwise specified.
DOC ::;TA ::;7DOC
SYMBOL PARAMETER
Output Regulation

AVOUT
VOUT

Isc
VRI?

4-22

CONDITIONS (Nole 2)
-1.24V;:, VOUT;:' -4V, 0 ~ lOUT ~ 12mA
-4V;:, VOUT;:' -5V, 0 ~ lOUT ~ 10mA
Output Voltage
VOUT Set to -3.5V, 0 ~ lOUT ~ 15mA
VOUT Set to -4V, 0 ~ lOUT ~ 12mA
VOUT Set to -4.5V, 0 ~ lOUT ~ 10mA
VOUT Set to -5V, 0 ~ lOUT ~ 10mA
Output Short-Circuit Current VOUT = OV
Output Ripple Voltage
lOUT = 5mA, VOUT = -4V

MIN

••
••
••
•

-3.33
-3.80
-4.28
-4.75

TYP
1
2
-3.5
-4.0
-4.5
-5.0
70
7

MAX
5
5
-3.68
-4.20
-4.73
-5.25
125

-4DoC::; TA::; 85°C
(Nole 7)
MIN TYP MAX
1
5
2
5
-3.33 -3.5 -3.68
-3.80 -4.0 -4.20
-4.28 -4.5 -4.73
-4.75 -5.0 -5.25
70
125
7

UNITS
%
%
V
V
V
V
mA
mV

LTC 1261
LECTRICAL CHARACTERISTICS

3.

denotes specifications which apply over the full operating
1perature range.
Ie 1: The absolute maximum ratings are those values beyond which the
of a device may be impaired.
Ie 2: All currents into device pins are positive; all currents out of device
s are negative. All voltages are referenced to ground unless otherwise
lcified.
Ie 3: All typicals are given at TA= 25°C.
Ie 4: C1 = C2 = 0.1 !If means the specifications apply to tripler mode
ere Vee - VOUT = 3Vee (LTC1261CS only; the LTC1261CS8 cannot be
mected in tripler mode) with C1 connected between C1+ and C1- and
connected between C2+ and C2-. C2 = 0 implies doubler mode where

~PICAL

PERFORmAnCE CHARACTERISTICS

Output Voltage
vs Output Current
3.5
_I.!
3.6 _ TA=25°e
3.7
3.B
3.9
4.0
4.1
4.2
4.3
4.4
4.5

vee =5V
DOUBLER MODE

-3.7

-3.7

~-3.B

~ -3.9

==

vee =3.3V
TRIPLER MODE

f-

~

10

f-

f-

-4.3
-4.4
-4.5

V

. /~

V

V

VDOUBLER MODE

1000

a
~

!l:
700
:::>

en

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)
LTCl261·TPC04

l7lJfJ~

1200
VOUT=-4V
TA =25°C

:1900
fiE
a::
BOO

500

TRIPLER MODY
I-- f-

5

6

Supply Current
vs Temperature

1200

I

4

3

SUPPLY VOLTAGE (V)

Supply Current
vs Supply Voltage

600
10

a: -4.1

TA =-40 o e

-4.4
-4.5
5.0 5.2 5.4 5.6 5.B 6.0 6.2 6.4 6.6 6.B 7.0
SUPPLY VOLTAGE (V)

B 9 10

7

~A=B5°C

TA - 25°C
~TA=-40OC
i5 -4.2

TA-25°C

-4.1

-4.3

//

/

::;

§; -4.0

i5 -4.2

+RIPL~RMO~

30

~ -3.9

TA - B5°C

::;

§; -4.0
f-

VOUT =-4V ±5%
TA =25 C

10

-3.5
-3.6

~-3.B

Maximum Output Current
vs Supply Voltage

1

Output Voltage (Tripier Mode)
vs Supply Voltage

-3.5
-3.6

o 1 2 3 4 5 6

0

(See Test Circuits)

Output Voltage (Doubler Mode)
vs Supply Voltage

OUTPUT CURRENT (rnA)

50

Vee - VOUT = 2Vee; for the LTC1261CS this means C1 connects from C1+
to C2- with C1- and C2 +floating. For the LTC1261 CS8 in doubler mode,
C1 connects from C1+ to C1-; there are no C2 pins.
Nole 5: Setting output to <-7V will exceed the absolute voltage maximum
rating with a 5V supply. With supplies higher than 5V, the output should
never be set to exceed Vee -12V.
Nole 6: For output voltages below -4.5V the LTC1261 may reach 50%
duty cycle and fall out of regulation with heavy load or low input voltages.
Beyond this point, the output will follow the input with no regulation.
Note 7: This data is guaranteed by correlation and not tested over the
-45°C to +85°C temperature range.

/

/

/

DOUBLER MODE
~ ~--

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
SUPPLY VOLTAGE (V)

VOU~=-4J

1000
:1 900
fiE
a::
a::
BOO
:::>

Vee =5V /
DOUBLER MODEJ

'-'

~

""-

:::>

700

en

600

- - ---

~=3.3V

VTRtLEyE

-- -n

500 I---40 -20

/

0 20 40 60
TEMPERATURE ee)

80

100

lTC1Wl-TI't06

4-23

LTC1261
TEST CIRCUITS

Tripier Mode
VIN

Doubler Mode

=

3.3V

o.
,::"--,,,--V'OUT =-4V ±5%

o.
,:":""",,,p---_ VOUT = -4V ±5%
3.3J.lF

Pin FunCTions
Pin numbers are shown as (LTC1261 CS/LTC1261 CS8).
NC (Pin 1/NA): No Internal Connection.
C1+ (Pin 2/Pin 2): C1 Positive Input. Connect a 0.1W
capacitor between C1 +and C1-. With the LTC1261 CS in
doubler mode, connect a 0.11lF capacitor from C1 + to
C2-.
C1- (Pin 3/Pin 3): C1 Negative Input. Connect a 0.1W
capacitor from C1+ to C1-. With the LTC1261CS in
doubler mode only, C1- should float.
C2+ (Pin 4/NA): C2 Positive Input. In tripler mode connect a 0.1 Wcapacitor from C2 +to C2 -. This pin is used
with the LTC1261 CS in tripler mode only; in doubler
mode this pin should float.
C2- (Pin 5/NA): C2 Negative Input. In tripler mode
connect a 0.1 Wcapacitor from C2 +to C2-. In doubler
mode connect a 0.1 Wcapacitor from C1 +to C2-.
GND (Pin 6/Pin 4): Ground. Connectto a low impedance
ground. A ground plane will help to minimize regulation
errors.
RO (Pin 7/NA): Internal Resistor String, 1st Tap. See
Table 2 in the Applications Information section for information on internal resistor string pin connections vs
output voltage.
R1 (Pin 8/NA): Internal Resistor String, 2nd Tap.
RADJ (Pin 9/NA): Internal Resistor String Output. Connect this pin to ADJ to use the internal resistor divider.

4-24

See Table 2 in the Applications Information section fo
information on internal resistor string pin connections v:
output voltage.
ADJ (CaMP for fixed versions) (Pin 10/Pin 5): Outpu
AdjusVCompensation Pin. For adjustable parts this pin i
used to set the output voltage. The output voltage shoull
be divided down with a resistor divider and fed back tl
this pin to set the regulated output voltage. The resisto
divider can be external or the internal divider string cal
be used if it can provide the required output voltage
Typically the resistor string should draw 21 01lA from thl
output to minimize errors due to the bias current at th
adjust pin. Fixed output parts have the internal resisto
string connected to this pin inside the package. The pil
can be used to trim the output voltage if desired. It cal
also be used as an optional feedback compensation pil
to reduce output ripple on both adjustable and fixel
output voltage parts. See Applications Information sec
tion for more information on compensation and outpu
ripple.
OUT (Pin 11/Pin 6): Negative Voltage Output. This pil
must be bypassed to ground with a 11lF or larger capaci
tor; it must be at least 3.3W to provide specified outpu
ripple. The size of the output capacitor has astrong effec
on output ripple. See the Applications Information sec
tion for more details.
REG (Pin 12/pin 7): This is an open drain outputthat pull
low when the output voltage is within 5% of the set valuE

LTC 1261
'In FunOlons
will sink 8mA to ground with a SV supply. The external
rcuitry must provide a pull-up or REG will not swing
gh. The voltage at REG may exceed Vee and can be
Illed up to 12V above ground without damage.
iDN (Pin 13/Pin 8): Shutdown. When this pin is at
'ound the LTC1261 operates normally. An internalS~
III-down keeps SHDN low if it is left floating. When
iON is pulled high, the LTC1261 enters shutdown
ode. In shutdown the charge pump stops, the output

collapses to OV and the quiescent current drops to S~
typically.
Vcc (Pin 14/Pin 1): Power Supply. This requires an input
voltage between 3V and 6.SV. Certain combinations of
output voltage and operating mode may place additional
restrictions on the input voltage. Vee must be bypassed
to ground with at least a O.1~ capacitor placed in close
proximity to the chip. See the Applications Information
section for details.

IPPLICATlons InFORmATiOn
ODES OF OPERATION

Ie LTC1261 uses a charge pump to generate a negative
Itput voltage that can be regulated to a value either
gher or lower than the original input voltage. It has two
odes of operation: a "doubler" inverting mode, which
n provide a negative output equal to or less than the
Isitive power supply and a "tripler" inverting mode,
lich can provide negative output voltages either larger or
nailer in magnitude than the original positive supply. The
pier offers greater versatility and wider input range but
quires four external capacitors and a 14-pin package.
Ie doubler offers the SO-8 package and requires only
ree external capacitors.
IUbler Mode

)ubler mode allows the LTC1261 to generate negative
Itputvoltage magnitudes up to that ofthe supply voltage,
eating avoltage between Vee and OUT of up to two times
,. In doubler mode the LT1261 uses a single flying
pacitorto invert the input supply voltage, and the output
Itage is stored on the output bypass capacitor between
fitch cycles. The LTC1261 CS8 is always configured in
,ubler mode and has only one pair of flying capacitor
lS (Figure 1a). The LTC1261 CS can be configured in
,ubler mode by connecting a single flying capacitor
tween the C1+ and C2- pins. C1- and C2+ should be left
,ating (Figure 1b).
ipler Mode

e LTC1261 CS can be used in a tripler mode which can
nerate negative output voltages up to twice the supply

l7lJ!J~

voltage. The total voltage between the Vee and OUT pins
can be up to three times Vs. For example, tripler mode can
be used to generate -SV from a single positive 3.3V
supply. Tripier mode requires two external flying capacitors. The first connects between C1+ and C1- and the
second between C2+ and C2- (Figure 1c). Because of the
relatively high voltages that can be generated in this mode,
care must be taken to ensure that the total input-to-output
voltage never exceeds 12V or the LTC1261 may be damaged. In most applications the output voltage will be kept
in check by the regulation loop. Damage is possible
however, with supply voltages above 4V in tripler mode
and above 6V in doubler mode. As the input supply voltage
rises the allowable output voltage drops, finally reaching
-4V with an 8.SV supply. To avoid this problem use
doubler mode whenever possible with high input supply
voltages.

•• ) LTC1261CS8

b.) LTC1261CS

c.) LTC1261CS

DOUBLER MODE

DOUBLER MODE

TRIPLER MODE
lTCl261'FQl

Figure 1. Flying Capacitor Connections

THEORY OF OPERATION

Ablock diagram of the LTC1261 is shown in Figure 2. The
heart ofthe LTC1261 is the charge pump core shown in the
dashed box. It generates anegative output voltage by first

4-25

LTC 1261
APPLICATions InFoRmATion
Vee

------~-------:
Sl

S5

01----1

S6

R

226k Rl"
I
I

lOOk RO"

I
I
I

--------

I

--------------~

INTERNALLY
CONNECTED FOR
FIXED OUTPUT
VOLTAGE PARTS

50k
"!:'

ADJ/COMP
REG

~261CS140NLY
Figure 2. Block Diagram

charging the flying capacitors between Vee and ground. It
then stacks the flying capacitors on top of each other and
connects the top ofthe stack to ground forcing the bottom
of the stack to anegative voltage. The charge on the flying
capacitors is transferred to the output bypass capacitor,
leaving it charged to the negative output voltage. This
process is driven by the internal clock.
Figure 2 shows the charge pump configured in tripler
mode. With the clock low, C1 and C2 are charged to Vee
by S1, S3, S5 and S7. Atthe next rising clock edge, S1, S3,
S5 and S7 open and S2, S4 and S6 close, stacking C1 and
C2 on top of each other. S2 connects C1+ to ground, S4
connects C1- to C2+ and C2 - is connected to the output by
S6. The charge in C1 and C2 is transferred to COUT, setting
it to anegative voltage. Doubler mode works the same way
except that the single flying capacitor (C1) is connected
between C1+ and C2-. S3, S4 and S5 don't do anything
useful in doubler mode. C1 is charged initially by S1 and
S7 and connected to the output by S2 and S6.
The output voltage is monitored by COMP1 which compares a divided replica of the output at ADJ (COMP for

4-26

fixed output parts) to the internal reference. At the beginning of a cycle the clock is low, forcing the output of thE
AND gate low and charging the flying capacitors. The nex
rising clock edge sets the RS latch, setting the chargE
pump to transfer charge from the flying capacitors to thE
output capacitor. As long as the output is below the se
pOint, COMP1 stays low, the latch stays set and the chargE
pump runs at the full 50% duty cycle of the clock gate(
through the AND gate. As the output approaches the se
voltage, COMP1 will trip whenever the divided signa
exceeds the internal1.24V reference relative to OUT. Thil
resets the RS latch and truncates the clock pulses, reduc
ing the amount of charge transferred to the output capaci
tor and regulating the output voltage. If the output exceedl
the set point, COMP1 stays high, inhibiting the RS latct
and disabling the charge pump.
COMP2 also monitors the divided signal at ADJ but it il
connected to a 1.1BV reference, 5% below the mair
reference voltage. When the divided output exceeds thil
lower reference voltage indicating that the output is withir
5% of the set value, COMP2 goes high turning on the REC
output transistor. This is an open drain N-channel devic!

LTC 1261
~PPLICATlons

InFORmATion

:apable of sinking SmA with a3.3V Vee and BmA with aSV
Icc. When in the "off" state (divided output more than S%
Jelow VREF) the drain can be pulled above Vee without
lamage up to a maximum of 12V above ground. Note that
he REG output only indicates if the magnitude of the
Jutput is belowthe magnitude of the set point by S% (Le.,
lour> -4.7SVfora-SV set point). If the magnitude ofthe
Jutput is forced higher than the magnitude ofthe set point
Le., to -6V when the output is set for -SV) the REG
Jutput will stay low.
lUTPUT RIPPLE
)utput ripple in the LTC1261 comes from two sources;
roltage droop at the output capacitor between clocks and
requency response ofthe regulation loop. Voltage droop
s easy to calculate. With a typical clock frequency of
iSOkHz, the charge on the output capacitor is refreshed
!nce every 1.BJ..IS. With a 1SmA load and a 3.3~ output
:apacitor, the output will droop by:

happens the comparator will allow afew complete pulses
through, then overcorrect and disable the charge pump
until the output drops below the set point. Under these
conditions the output will remain in regulation but the
output ripple will increase as the comparator "hunts" for
the correct value.
To preventthis from happening, an external capacitor can
be connected from ADJ (or COMP for fixed output parts)
to ground to compensate for external parasitics and increase the regulation loop bandwidth (Figure 3). This
sounds counterintuitive until we remember that the internal reference is generated with respectto OUT, notground.

.-------......,------,,
TO CHARGE
PUMP

,,
, RESISTORS ARE
, INTERNAL FOR

,: FIXEO OUTPUT PARTS
,,
,

-LCe

,

- , 100pF

-:

--,

ADJ/COMP

11t ) = 1SmA x (1.B/lS)
ILOAD x (COUT
3.3/lF = B.2mV
'his can be a significant ripple component when the
)utput is heavily loaded, especially if the output capacitor
ssmall. If absolute minimum output ripple is required, a
O~ or greater output capacitor should be used.
!egulation loop frequency response is the other major
:ontributor to output ripple. The LTC1261 regulates the
)utput voltage by limiting the amount of charge transerred to the output capacitor on a cycle-by-cycle basis.
'he output voltage is sensed at the ADJ pin (COMP for
ixed output versions) through an internal or external
esistor divider from the OUT pin to ground. As the flying
apacitors are first connected to the output, the output
oltage begins to change quite rapidly. As soon as it
xceeds the set point COMP1 trips, switching the state of
he charge pump and stopping the charge transfer. Beause the RC time constant of the capacitors and the
witches is quite short, the ADJ pin must have a wide AC
@dwidth to be able to respond to the output in time.
xternal parasitic capacitance at the ADJ pin can reduce
le bandwidth to the point where the comparator cannot
espond by the time the clock pulse finishes. When this

L7lJ!J~

VOUT
LTC1261'F03

Figure 3. Regulator Loop Compensation

The feedback loop actually sees ground as its "output,"
thus the compensation capacitor should be connected
across the "top" of the resistor divider, from ADJ (or
COMP) to ground. By the same token, avoid adding
capacitance between ADJ (or COMP) and VOUT. This will
slow down the feedback loop and increase output ripple.
A 100pF capacitor from ADJ or COMP to ground will
compensate the loop properly under most conditions.
OUTPUT FILTERING
If extremely low output ripple «SmV) is required, additional output filtering is required. Because the LTC1261
uses a high SSOkHz switching frequency, fairly low value
RC or LC networks can be used at the output to effectively
filter the output ripple. A 1on series output resistor and a
3.3~ capacitor will cut output ripple to below 3mV (Figure
4). Further reductions can be obtained with larger filter
capacitors or by using an LC output filter.

4-27

•

LTC1261
APPLICATions InFoRmATion
5V

supply. Table 1 shows recommended values of flying
capacitor vs maximum load capacity.
Table 1. Typical Max Load (rnA) vs Flying Capacitor Value at
""""------.-'I1V'v-.-- VOUT = -4V

TA = 25°C, VOUT = -4V
FLYING
CAPACITOR
VALUE (!d')

Figure 4. Output Filter Cuts Ripple Below 3mV

CAPACITOR SELECTION
Capacitor Sizing
The performance of the LTC1261 can be affected by the
capacitors it is connected to. The LTC1261 requires bypass capacitors to ground for both the Vee and OUT pins.
The input capacitor provides most of LTC1261 's supply
current while it is charging the flying capacitors. This
capacitor should be mounted as close to the package as
possible and its value should be equal to or larger than the
flying capacitor in doubling mode and at least twice the
value of the flying capacitors in tripling mode. Ceramic
capacitors generally provide adequate performance but
avoid using a tantalum capacitor as the input bypass
unless there is at least a 0.1 J,Jf ceramic capacitor in
parallel with it. The charge pump capacitors are somewhat less critical since their peak currents are limited by
the switches inside the LTC1261. Most applications
should use 0.1 J,Jf as the flying capacitor value. Conveniently, ceramic capacitors are the most common type of
0.1 J,Jf capacitor and they work well here. Usually the
easiest solution is to use the same capacitor type for both
the input bypass and the flying capacitors.
In applications where the maximum load current is welldefined and output ripple is critical or input peak currents
need to be minimized, the flying capacitor values can be
tailored to the application. Reducing the value of the
flying capacitors reduces the amount of charge transferred with each clock cycle. This limits maximum output
current, but also cuts the size of the voltage step at the
output with each clock cycle. The smaller capacitors
draw smaller pulses of current out of Vee as well, limiting
peak currents and reducing the demands on the input

4-28

0.1
0.047
0.033
0.022
0.01

MAX LOAD (mA)
MAX LOAD (mA)
Vee = 5V DOUBLER MODE Vee =3.3V TRIPLER MODE
22
20

16
8
4
1

15
11
5
3

The output capacitor performs two functions: it provides
output current to the load during half of the charge pump
cycle and its value helps to set the output ripple voltage.
For applications that are insensitive to output ripple, the
output bypass capacitor can be as small as 1J,Jf. To achieve
specified output ripple with 0.1 J,Jf flying capacitors, the
output capacitor should be at least 3.3J,Jf. Larger output
capacitors will reduce output ripple further at the expense
of turn-on time.

Capacitor ESR
Output capacitor Equivalent Series Resistance (ESR) is
another factor to consider. Excessive ESR in the output
capacitor can fool the regulation loop into keeping the
output artificially low by prematurely terminating the charging cycle. As the charge pump switches to recharge the
output a brief surge of current flows from the flying
capacitors to the output capacitor. This current surge can
be as high as 100mA under full load conditions. Atypical
3.3J,Jf tantalum capacitor has 10 or 20 of ESR; 1OOmA x
20 = 200mV.lf the output is within 200mV of the set point
this additional 200mV surge will trip the feedback comparator and terminate the charging cycle. The pulse dissipates quickly and the comparator returns to the correct
state, but the RS latch will not allow the charge pump to
respond until the next clock edge. This prevents the charge
pump from going into very high frequency oscillation
under such conditions but it also creates an output error
as the feedback loop regulates based on the top of the
spike, not the average value of the output (Figure 5). The
resulting output voltage behaves as if a resistor of value
CESR x {lpl(lIAVdO was placed in series with the output. To

LTC 1261
~PPLICATlons

InFORmATion

lvoid this nasty sequence of events connect a O.111f
:eramic capacitor in parallel with the larger output capacior. The ceramic capacitor will "eat" the high frequency
,pike, preventing it from fooling the feedback loop, while
he larger butslowertantalum or aluminum output capacior supplies output current to the load between charge
:ycles.

signal at the output to give 1.24V at the ADJ pin with
respectto Vour(Figure 6). The LTC1261 uses a positive
reference with respect to VOUT, not a negative reference
with respect to ground (Figure 2 shows the reference
connection). Be sure to keep this in mind when connecting
the resistors! Ifthe initial output is not what you expected,
try swapping the two resistors.

CLOCK
I

oui~J:~~~ {==i=n-V~~Tn _~__ n_: __ ~e~iAGE
I

HIGH ESR
OUTPUTCAP

!

,. . .---,--

g~~:JT

--:-----------k=-----~-- ~SET
r A$~~AGE

~
{nlnI nVOUT-n n --I----I
I
n
I

I

Figure 6. External Resistor Connections

I
I

COMP1

I

OUTPUT

Figure 5. Output Ripple with Low and High ESR Capacitors

Jote that ESR in the flying capacitors will not cause the
:ame condition; in fact, it may actually improve the situaion by cutting the peak current and lowering the ampliude of the spike. However, more flying capacitor ESR is
lot necessarily better. As soon as the RC time constant
lpproaches half of a clock period (the time the capacitors
lave to share charge at full duty cycle) the output current
:apability of the LTC1261 will begin to diminish. For O.111f
lying capacitors, this gives a maximum total series resisance of:
1 (550kHz
1 ) / O.1J.LF =9.H1
"21 (tCLK)
CFLY ="2

The 14-pin adjustable parts include a built-in resistor
string which can provide an assortment of output voltages •
by using different pin-strapping options at the RO, R1, and
RADJ pins (Table 2). The internal resistors are roughly
124k, 226k, 100k, and 50k (see Figure 2) giving output
options of-3.5V, -4V, -4.5V, and -5V. The resistors are
carefully matched to provide accurate divider ratios, but
the absolute values can vary substantially from part to
part. It is not a good idea to create a divider using an
external resistor and one of the internal resistors unless
the output voltage accuracy is not critical.
Table 2. Output Voltages Using the Internal Resistor Divider
PIN CONNECTIONS
ADJ to RAOJ
ADJ to RADJ, RO to GND
ADJ to RADJ, Rl to RO
ADJ to RAOJ, Rl to GND

Aost of this resistance is already provided by the internal
witches in the LTC1261 (especially in tripler mode). More
han 10 or 20 of ESR on the flying capacitors will start to
Iffect the regulation at maximum load.
IESISTOR SELECTION
\esistor selection is easy with the fixed output versions of
he LTC1261- no resistors are needed! Selecting the
ight resistors for the adjustable parts is only a little more
lifficult. A resistor divider should be used to divide the

L7lJ!J~

ADJ to Rl
ADJ to RO
ADJ to GND

OUTPUT VOLTAGE
-5V

-4.5V
-4V
-3.5V
-1.77V
-1.38V
-1.24V

There are some oddball output voltages available by
connecting ADJ to RO or R1 and shorting out some of the
internal resistors. If one of these combinations gives you
the output voltage you want, by all means use it!
The internal resistor values are the same for the fixed
output versions of the LTC1261 as they are for the adjust-

4-29

LTC1261
APPLICATions InFoRmATion
able. The output voltage can be trimmed, if desired, by
connecting external resistance from the CaMP pin to OUT
or ground to alter the divider ratio. As in the adjustable
parts, the absolute value of the internal resistors may vary
significantly from unit to unit. As a result, the further the
trim shifts the output voltage the less accurate the output
voltage will be. If a precise output voltage other than one
ofthe available fixed voltages is required, itis better to use

an adjustable LTC1261 and use precision external resistors. The internal reference is trimmed at the factory to
within 3.5% of 1.24V; with 1% external resistors the
output will be within 5.5% of the nominal value, even
under worst case conditions.
The LTC1261 can be internally configured with nonstandard fixed output voltages. Contact the Linear Technology
Marketing Department for details.

TYPICAL APPLICATiOnS
3.3V Input, -4.5V Output GaAs FET Bias Generator
P-CHANNEL
POWER SWITCH
VSAT --------~....... . - - - - - - ,

3.3V - . . - - - - ,

GaAs
TRANSMITIER

5V Input, -4V Output GaAs FET Bias Generator
P-CHANNEL
POWER SWITCH

5V .......- - - - ! . .

GaAs
TRANSMITIER

4-30

LTC1261
TYPICAL APPLICATions
7 Cells to -1.24V Output GaAs FET Bias Generator
P·CHANNEL
VSAT = 8.4V _ _---1r-_ _ _ _ _ _ _ _ _......_PO_W..
ER-::a.SWrl_TC_H_--,
(7 NiCd CELLS)

GaAs
TRANSMITIER

1mV Ripple, 5V Input, -4V Output GaAs FET Bias Generator
P·CHANNEL
POWER SWITCH

0.1
GaAs
TRANSMITIER

LTG1261 "TA06

High Supply Voltage, -5V Output GaAs FET Bias Generator
P-CHANNEL
POWER SWITCH

GaAs
TRANSMITIER

L7lJD~

4-31

LTC 1261
TYPICAL APPLICATions
5V Input. -O.5V Output GaAs FET Bias Generator
P·CHANNEL
POWER SWITCH
VMT----------------------------~--_1~r------~

SHUTDOWN

------+======:;-1

5V ....----+--'-

O.
GaAs
TRANSMITTER
lTCl261·TAOB

-5V Supply Generator

Low Output Voltage Generator
5V

. : . . . .....----+-- VOUT = Vee -10~ (Rs
3.3"F

Minimum Parts Count -4V Generator
5V ....------...:..

4-32

t 124k)
= -O.5V (Rs = 426k)
=-lV(Rs=476k)

LTC 1261
rYPICAL APPLICATions
rhis circuit uses the LTG1261 GS8 to generate a -1.24V
)utput at 20mA. Attached to this output is a3120 resistor
:0 make the currenVvoltage conversion. 4mA through
3120 generates 1.24V, giving a net OV output. 20mA
hrough 3120 gives 6.24Vacross the resistor, giving anet
iV output. If the 4mA to 20mA source requires an operatng voltage greater than 8V, it should be powered from a

separate supply; the LTG1261 can then be powered from
any convenient supply, 3V ::;; Vs ::;; 8V. The Schottky diode
prevents the external voltage from damaging the LTG1261
in shutdown or under fault conditions. The LTG1261 's
reference is trimmed to 3.5% and the resistor adds 1%
uncertainty, giving 4.5% total output error.

-1.24V Generator for 4mA-20mA to OV-5V Conversion
OPTIONAL
INPUT
PROTECTION
DIODES

8V

+
4mA
TO 20mA
SENSOR

•

t---i-+-t-----+----t-:--- OVTO 5V
±5%

lTC12ti1-TA11

AELATED PARTS
~ART

NUMBER

_TC1550/LTC1551

DESCRIPTION
. Low Noise Switched Capacitor Regulated Voltage Inverter

COMMENTS
GaAs FET Bias with Linear Regulator 1mV Ripple

_TC1429

Clock Synchronized Switched Capacitor Regulated Voltage Inverter

GaAs FET Bias

_T1121

Micropower Low Dropout Regulators with Shutdown

O.4V Dropout Voltage at 150mA, Low Noise,
Switched Capacitor Regulated Voltage Inverter

L7lJ!J~

4-33

' ' ' '-TLElcnHN'CAO'~O'·_G~Q....--_____
L_TC_12_62
12V. 30mA Flash Memory

~,

IT

Programming Supply

FEATURES

DESCRIPTion

•
•
•
•
•
•
•

The LTC®1262 is a regulated 12V, 30mA output DC/DC
converter. It is designed to provide the 12V ±5% output
necessary to program byte-wide flash memories. The
output will provide up to 30mA from input voltages as low
as 4.75V without using any inductors. Only four external
capacitors are required to complete an extremely small
surface mountable circuit.

Regulated 12V ±5% Output Voltage
No Inductors
Supply Voltage Range: 4.75V to 5.5V
Guaranteed 30mA Output
Low Power: Icc =500~
Icc in Shutdown: O.51JA
8-Pin PDIP or SO-8 Package

The TTL compatible shutdown pin can be directly connected to a microprocessor and reduces the supply current to less than O.51JA. The LTC1262 offers improved
shutdown current performance and requires fewer external components than competing solutions.

APPLICATions
• 12V Flash Memory Programming Supplies
• Compact 12V Op Amp Supplies
• Battery-Powered Systems

The LTC1262 is available in an 8-pin POI P or SO-8
package.
£T, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
In/Oul of Shutdown

FLASH

MEMORY

SHDN 5V
5v/DIV OV

.::....-.....-+----IVPp
12V

"'----+-----1 Vee
Vee

4.75VTO 5.5V

VOUT
LTC1262'TAOl

5v/DIV 5V
OV
1mS/DIV

4-34

LTC 1262
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

(Note 1)

Supply Voltage (Vee) ................................................ 6V
Input Voltage (SHDN) ................... -O.3V to Vee + O.3V
Output Current (lOUT) ........................................... 50mA
Operating Temperature Range .................... O°C to 70°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER

TOP VIEW

"0'"""
Cl+ 2

7 GND

C2- 3

6 vour

C2+ 4

5 vcc

N8 PACKAGE
8-LEAD PDIP

S8 PACKAGE
8-LEAD PLASTIC SO

LTC1262CN8
LTC1262CS8
S8 PART MARKING

TJMAX =l50"C, BJA =100"C/W (N8)
TJMAX =l50"C, BJA = l50"C/W (58)

1262

Consult factory for Industrial and Military grade parts.

ELEORICAL CHARACTERISTICS
SYMBOL
VOUT

Icc
ISHDN
losc
Rsw
VIH
VIL

tON
tOFF

PARAMETER
Output Voltage
Supply Current
Shutdown Supply Current
Oscillator Frequency
Power Efficiency
Vcc to Your Switch Impedance
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
Turn-On Time
Turn-Off Time

Vee =4.75V to 5.5V, TA =DoC to 70°C, (Notes 2, 3), unless otherwise noted.

CONDITIONS
OmA::;; lOUT::;; 30mA, VSHDN = OV
No Load, VSHON = OV
No Load, VSHON = VCC
Vcc = 5V, lOUT = 30mA
Vcc = 5V, lOUT = 30mA
Vcc = VSHDN = 5V, lOUT = OmA

Vcc = 5V, VSHDN = OV
Vcc = 5V, VSHDN = 5V
C1 = C2 = 0.22W, CIN = COUT =4.7W, (Figures 1,2)
C1 =C2 =0.22W, CIN = COUT = 4.7W, (Figures 1, 2)

rhe • denotes specifications which apply over the full operating
:emperature range.
~ole 1: Absolute maximum ratings are those values beyond which the life
)f the device may be impaired.

.L7lJ!J£OO

•
•
•

•
•
•
••

MIN
11.4

TYP
0.5
0.5
300

MAX
12.6
1
10

74
0.18

2

-10
0.06
500
3.3

-5

2.4
0.8
-20

10

UNITS
V
rnA
~
kHz
%
kQ
V
V
~
~
~

ms

Nole 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Nole 3: All typicals are given at Vcc = 5V, TA = 25°C .

4-35

•

LTC 1262
TYPICAL PERFORmAnCE CHAAAOEAISTICS
Shutdown Supply Current
vs Temperature

Efficiency vs Output Current
85

3.6

I

Vee = 5V

Vee =4.75V

r;

80

~ 75

1:;

15

70

W

65

~

~

~

Vee =5V

~

..........

rt

Vee

~5.5V

\.

~ 2.4
<>
~

ll::

60

'"~

1.2

~

0.6

:J:

'"
o

10

20
30
40
OUTPUT CURRENT (rnA)

1.8

/

::>

o

55

j

::>

'"

I

3.0

---

o

-50

50

-25

V

0
25
50
TEMPERATURE (OC)

75

LTCl262G01

LTCl262G02

Supply Current vs Supply Voltage
600
580

r-......

~ 560

12.0

Vee = 4.75V\

11.8

TA= WC

V

~11.6

Vee =5.5V \

~ ::::

~
a:

f§ 540
<>
~

ll::
iil

Output Voltage vs Output Current
12.2

lo~=O

"-

~ee ~5V

~ 11.0

I-

520
500

-

5

TA=2~

4.5

4.75

5.0
5.25
5.5
SUPPLY VOLTAGE (V)

10.8

6.0

LTCl282GOS

10.2 0

~

/ \

r\

r-

\

10.4
5.75

1-'"

1\

10.6

-rAtC

480

100

5

10 15 20 25 30 35 40 45 50
OUTPUT CURRENT (rnA)
1262604

Pin FuncTions
C1-(Pin 1): C1 Negative Input. Connecta O.22~ capacitor C1 between C1+ and C1-.
C1 +(Pin 2): C1 Positive Input. Connect a O.22~ capacitor C1 between C1+ and C1-.
C2 - (Pin 3): C2 Negative Input. Connect aO.22~ capacitor C2 between C2+ and C2-.
C2+ (Pin 4): C2 Positive Input. Connect a O.22~ capacitor C2 between C2+ and C2-.
Vce (Pin 5): Positive Supply Input Where 4.7SV ::; Vee
::; S.SV. Connect a 4. 7~ bypass capacitor CIN to ground.

4-36

VOUT (Pin 6): 12V Output. Connect a4.7~ bypass capacitor COUTtO ground. When in the shutdown mode VOUT =
Vee·
GND (Pin 7): Ground.
SHDN (Pin 8): Logic Level Shutdown Pin. Application of a
logic low at SHDN pin will place the regulator in normal
operation. With no external connection, or with SHDN tied
to Vee, the device will be put into shutdown mode. Connect
to GND for normal operation. In shutdown mode the
charge pump is turned off and VOUT = Vee.

LTC 1262
BLOCK DIAGRAm

1

: Vee
~CIN

R1

........._-'1'-- SHDN
1VOUT
R2

~COUT

1--------t--+VDlV
R3
S2
1

1
1
1
1
1

CHARGE
PUMP

1

1______ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ____ ~

S1 AND S2 SHOWN WITH SHDN PIN LOW.
S3A, S38, S3C, S3D, S4A AND S48 SHOWN WITH OSCILLATOR OUTPUT LOW AND VDlV < VSGAP - VHYST.
COMPARATOR HYSTERISIS IS ±VHYST.

TmlflG DIAGRAmS
-tOFF

C1
O.22I'F
5.W

';""--1I-'---t--::---

VOUT

r-----------------------~+-------Vee

'----ov
LTCl262·TAIl2

Vee

lTCf262·FQ2

4.75VTD 5V

Figure 1. LTC1262 Timing Diagram

Figure 2. LTC1262 Timing Circuit

4-37

LTC 1262
APPLICATions InFoRmATion
Operation

Choice of Capacitors

The LTC1262 uses a charge pump tripler to generate 12V
from aVee of SV. The charge pump operates when clocked
by a300kHz oscillator. When the oscillator output is low,
C1 and C2 are connected between Vee and GND, charging
them to Vee. When the oscillator output goes high, C1 and
C2 are stacked in series with the bottom plate of C1 pulled
to Vee. The top plate of C2 is switched to charge COUT and
VOUT rises. VOUT is regulated to within S% of 12V by an
oscillator pulse gating scheme. A resistor divider senses
VOUT. When the output ofthe divider (VDlV) is less than the
output of a bandgap (VBGAP) by the hysteresis voltage
(VHYST) ofthe comparator, oscillator pulses are applied to
the charge pump to raise VOUT. When VDlV is above VB GAP
by VHYST, the oscillator pulses are prevented from clocking the charge pump. VOUT drops until VDlV is belowVBGAP
by VHYST again. The gates of all internal switches are
driven between VOUT and GND. An internal diode ensures
thatthe LTC1262 will start up under load by charging COUT
to one diode drop below Vee.

The LTC1262 is tested with the capacitors shown in
Figure 2. C1 and C2 are O.22~ ceramic capacitors and
CIN and COUT are 4.7~ tantalum capacitors. Refer to
Table 1 if other choices are desired.

To reduce supply current the LTC1262 may be put into
shutdown mode by floating the SHDN pin or taking it to
Vee. Inthis mode the bandgap, comparator, oscillator and
resistor divider are switched off to reduce supply current
to typically O.SJ.tA. At the same time an internal switch
shorts VOUT to Vee; VOUT takes 3.3ms to reach S.1 V (see
tOFF in Figure 1). When the SHDN pin is low, the LTC1262
exits shutdown and the charge pump operates to raise
VOUT to 12V. VOUT takes SOOJ..lS to reach the lower regulation limit of 11.4V (see tON in Figure 1).

4-38

Table 1. Recommended Capacitor Types and Values
CAPACITOR

CERAMIC

TANTALUM

ALUMINUM

e1,e2

O.221li' to V

Not
Recommended

Not
Recommended

COUT

21li'(Min)

4.71li' (Min)

10Ili'(Min)

V

4.71li' (Min)

10Ili'(Min)

CIN

(Min)

C1 and C2 should be ceramic capacitors with values in the
range of O.22~ to 1~. Higher values provide better load
regulation. Tantalum capacitors are not recommended as
the higher ESR of these capacitors degrades performance
when the load current is above 2SmA with Vee = 4.7SV.
CIN and COUT can be ceramic, tantalum or electrolytic
capaCitors. The ESR of COUT introduces steps in the VOUT
waveform whenever the charge pump charges COUT. This
tends to increase VOUT ripple. Ceramic ortantalum capacitors are recommended for COUT if minimum ripple is
desired. The LTC1262 does not require a O.1~ capaCitor
between Vee and VOUT for stability.

Maximum Load Current
The LTC1262wili source uptoSOmAcontinuouslywithout
any damage to itself. Do not short the VOUT pin to ground.
If the VOUT pin is shorted to ground, irreversible damage
to the device will result.

LTC 1262
TYPICAL APPLICATions
5V to 3.3V/10A Converter

C7
O.22~F

C8
0.22~F

t - - - - -....- - - - - 1....."4r-..--- V1N
C4

1

~00~F

+

L-_"-_"
U1
LTC1148-3.3
C6
10~F

+.....-+-----::; VIN

-:c-

10 SHON
25V ':"
SHUTDOWN _ _...._ _..J

PORIVE

R4
0.01Q

L2

x3
PANASONIC
ECGCOKB220R

':"

t-____+-J3...,~...,H/r10rA'-....."'VI2Wtv_.....-

1-'--....- ,

SENSE+ ~-""---+-.I\I\"""'-+-----+------'
C3
1000pF
SENSE-I-'--.....--+..J.W\r-t------;'----------'

5V

.....-

.....-

+

+

VOUT
3.3V
10A
C5
330~F

6.3V

r---""';,CT
C1
3300pF

SGND

NDRIVE
PGND

1-'"14:...-+-__-+__-1

x2

01
MBRS120T3

OS-CON

12

--------------1
:
1
1

R6
1
22k Burst ModeT• DEFEAT; 1
USE IF REQUIRED :

LTCl262'TA112

: ':"
1
- - - - - - - - - - ______ 1

Output Voltage vs Oulput Current for
Two Paralleled Devices

Paralleling Devices

12.4

Vee =5V

12.2

Y.r.. ~ r"Irs

12.0
~+--I--+'---+--- 12V OUTPUT

~11.8

~ 11.6

I

~11.4
>-

i5:
Vee
4.75VTO
5.5V

t-

Vee =5.5V

w

,l '

Vee =4.75V

11.2

>-

511.0

~

10.8

\

10.6
10.4

o

10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (rnA)

SEE FIGURE AT LEFT.

NOTE: KEEP DEVICES CLOSE TOGETHER OR
USE SEPARATE 4.7~F TANTALUM
CAPACITORS IF THIS IS NOT POSSBILE.

j---

t\,

Burst Mode is atrademark of Linear Technology Corporation.

LTC 1262

RELATED PAATS
PART NUMBER

COMMENTS

LT1106*

DESCRIPTION
Micropower Step-Up DC/DC Converter for PCMCIA Card Flash Memory

LT1109-12

Micropower Low Cost DC/DC Converter Adjustable and Fixed 12V

Three-Lead Z Package, Requires External Inductor

LT1109A-12

Micropower DC/DC Converter Flash Memory VPP Generator
Adjustable and Fixed 12V

Requires External Inductor

LT1301

Micropower High Efficiency 5V112V Step-Up DC/DC
Converter for Flash Memory

7J.tA ISHDN, SMT Inductor and Capacitors

LT1309

500kHz Micropower DC/DC Converter for Flash Memory

Small SMT Inductor and Capacitors, 6J.tA ISHDN

PCMCIA Card Power Control, 9J.tA ISHDN, Small SMT
Components, Requires External Inductor

* See also LT13121LT1313 PCMCIA VPP drivers/regulators, LT1314/LT1315 PCMCIA switch matrix and the LTC1470/LTC1471/LTC1472 Protected Vce
and VPP switching matrices

4-40

L7~JD~~k>~---C-lo-c-k---sY-n-c-h-r-~-~-i~4-:-~

Switched Capacitor
Regulated Voltage Inverter

FEATURES

DESCRIPTiOn

• Regulated Negative Voltage from a Single
Positive Supply
• External Clock for Synchronization in Noise
Sensitive Systems
• REG Output Indicates Output is in Regulation
• Low Output Ripple: 5mV Typ
• Can Provide Regulated -5V from a 3V Supply
• Supply Current: 600J,1A Typ
• Shutdown Mode Orops Supply Current to O.2J,1A
• Up to 12mA Output Current
• Adjustable or Fixed Output Voltages
• Requires Only Three or Four External Caps
• Output Regulation: 5%
• Available in SO-8 Packages

The LTC®1429 is a switched-capacitor voltage inverter designed to provide a regulated negative voltage from a single
positive supply and permits clock synchronization in noise
sensitive systems. The LTC1429CS operates from aSingle 3V
to 8V supply and provides an adjustable output voltage from
-1.25V to -8V. An on-Chip resistor string allows the
LTC1429CS to be configured for output voltages of -3.5V,
-4V, -4.5V or -5V. The LTC1429CS8 is optimized for
applications which require a fixed -4V output from a 5V
supply and requires only a single external O.11JF flying
capacitor. The LTC1429CS requires one or two external
O.11JF capacitors, depending on input voltage. Both versions
require additional external input and output bypass capacitors. An optional compensation capacitor at AOJ/COMP can
be used to reduce the output voltage ripple.

APPLICATions

Each version of the LTC1429 guarantees output regulation of
5%. The LTC1429 includes an open-drain REG output which
pulls low when the output is within 5% ofthe set value. Output
ripple is typically as low as 5mV. The LTC1429 requires an
external clock applied to the SYNC/SO for normal operation
.and consumes atypical quiescent current of 600J,1A. Holding
the SYNC/SO either high or low brings the device into
shutdown and the supply current drops to O.2J,1A. For applications which don'thaveaclocksignal available, the LTC1261
provides the same functionality with an internal oscillator. For
applications which require output ripple below 1mV, see the
LTC1550/LTC1551. The LTC1429CS is available in a 14-pin
SO package and the LTC1429CS8 is available in an 8-pin SO
package.

•
•
•
•

GaAs FET Bias Generators
Negative Supply Generators
Battery Powered Systems
Single Supply Applications

D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn

Waveforms for -4V Generator with Power Valid

-4V Generator with Power Valid
OV

5V .......- - . . . : . .

Your
-4V
..::......--~,....Vm

=-4VAT10mA

=PO=WE""RV=AL"'ID 5V
OV
SYNCISD 5V
OV

LTCl429·TAOl

'OPTIONAL

4-41

II

LTC1429
ABSOLUTE mAxmum RATinGS
(Note 1)
Supply Voltage (Note 2) .............................................. 9V
Output Voltage ............................................. O.3V to -9V
Total Voltage, Vee to VOUT (Note 2) ......................... 12V
Input Voltage (SYNC/SO Pin) ...... -O.3V to (Vee + O.3V)
Input Voltage (REG Pin) ............................. -O.3V to 12V

Input Voltage (ADJ, RO-1, RADJ)
..................................... (VOUT- O.3V) to (Vee + O.3V)
Output Short Circuit Duration .......................... Indefinite
Operating Temperature Range ..................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

TOP VIEW

~O-"

C1+ 2
C1- 3
GND 4

REG
6 OUT
5 CaMP

LTC1429CS8-4 *

7

S8 PART MARKING

S8 PACKAGE
8·LEAD PLASTIC SO

14294

ORDER PART
NUMBER

TOP VIEW

u:

~

NC
C1+ IT:
C1- [I
C2+ IT
C2- [[
GND [I
RO II

Vee

~ SYNCISD
~ REG
~ OUT
~ ADJ
~ RADJ

LTC1429CS

~R1

SPACKAGE
14-LEAD PLASTIC SO
TJMAX = 150'C, 9JA = 110'C/W

TJMAX = 150'C, 9JA = 150'C/W

Consult factory for Industrial and Military grade parts.• Contact factory for other output voltages or 8-pin adjustable parts.

ELEORICAL CHARAOERISTICS

Vec = 3V to 6.5V. C1 = C2 = 0.111f (Note 4), COUT = 3.311f, FSYNC = 700kHz with 50% duty cycle square wave, unless otherwise noted.
SYMBOL
VREf
Is

PARAMETER
Reference Voltage
Supply Current

FSYNC

Synchronous Clock Frequency (Note 8)

PEFf
VOL
IREG

"

IADJ
VIH
VIL
liN
TON

4-42

Power Efficiency
REG Output Low Voltage
REG Sink Current
Adjust Pin Current
SYNC/SO Input High Voltage
SYNC/SO Input Low Voltage
SYNC/SO Input Current
Turn On Time

CONDITIONS

•

Vcc = 3.3V
Vcc = 5V
VSYNC/SD = Vcc or GNO
Vcc';; 5V
Vcc = 6.5V

••

IREG = 1rnA
VREG = o.av. Vcc = 3.3V
VREG = o.av. Vee = 5V
VADJ = 1.24V (Note 5)
Vee = 5V
Vee = 5V
VSYNCISD = Vee or GNO
lour: 10rnA

•
••
•
•
•
•

•

LTC1429CSB/LTC1429CS
MIN
TYP
MAX
1.20
1.24
1.28
600
1500
600
1500
0.2
5
60
700
2000
100
700
2000
65
0.1
0.8
5
8
8
15
0.01
1
2.0

200

UNITS
V

!lA
!lA
!lA
kHz
kHz
%
V
rnA
rnA

!lA

o.a

V
V

±1

!lA
J.IS

LTC1429
ELECTRICAL CHARAOERISTICS

Tripier Mode,Vcc = 3.3V, C1 = C2 = 0.1!lf (Note 4), COUT = 3.3!lf,
FSYNC = 700kHz with 50% duty cycle square wave, unless otherwise noted.
SYMBOL
LWOUT

PARAMETER
Output Regulation

Isc
VRIP

Output Short Circuit Current
Output Ripple Voltage

CONDITIONS
-1.24V ~ VOUT ~ -4V, 0 ~ lOUT ~ 12mA
-4V ~ VOUT ~ -5V, 0 ~ lOUT ~ 8mA
VOUT = OV
lOUT = 5mA, VOUT = -4V

LTC1429CS
TYP
1
2
35
S

MIN

•
•
•

MAX
5
5
75

UNITS
%
%
mA
mV

Doubler Mode, Vcc = 5V, C1 = O.1!lf, C2 = 0 (Note 4), COUT = 3.3!lf, FSYNC =700kHz with 50% duty cycle, unless otherwise noted.
SYMBOL
tiVOUT

PARAMETER
Output Regulation

VOUT
Isc
VRIP

Output Voltage
Output Short Circuit Current
Output Ripple Voltage

CONDITIONS
-1.24V ~ VOUT ~-4V, 0 ~ 10UT~ 10mA
-4V ~ VOUT ~ -4.SV, 0 ~ lOUT ~ 1OmA (Note 6)
VOUTSet to-4V, 0 ~ lOUT ~ 10mA
VOUT = OV
lOUT = SmA, VOUT = -4V

••
•
•

LTC1429CSB/LTC1429CS
MIN
TYP
MAX
1
5
2
S
-3.80
-4.00
-4.20
80
125
10

UNITS
%
%
V
mA
mV

connected in tripler mode), with C1 connected between C1+ and C1- and
C2 connected between C2+ and C2-. C2 = 0 implies doubler mode where
Vee - VOUT = 2Vee; for the LTC1429CS, this means C1 connects from C1+
to C2- with C1- and C2+ floating. For the LTC1429CS8 in doubler mode,
C1 connects from C1 +to C1- ; there are no C2 pins.
Nole 5: Adjustable output parts only; does not apply to fixed output parts.
Nole 6: For output voltages below -4.5V, the LTC1429 may reach 50%
duty cycle and fall out of regulation with heavy load or low input voltages.
Beyond this point, the output will follow the input with no regulation.
Nole 7: LTC1429 will operate with square wave of 40% to 60% duty cycle.
For best performance, use a square wave with 50% duty cycle.
Nole B: Maximum frequency is not tested. Typical part can be used
beyond 2MHz.

The. denotes specifications which apply over the full operating
temperature range.
Nole 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Nole 2: Setting output to < - 7V will exceed the total voltage maximum
rating with a 5V supply. With supplies higher than 4V the output should
never be set to exceed (Vcc -12V).
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground, unless otherwise
specified. All typicals are given at TA = 25°C.
Nole 4: C1 = C2 = 0.1 pi' means the specifications apply to tripler mode
where Vcc - VOUT = 3.3Vcc (LTC1429CS only; the LTC1429CS8 cannot be

TYPICAL PERFORmAnCE CHARAOERISTICS
(See Test Circuits; Figure 1 for Doubler Mode, Figure 2 for Tripier Mode)
Output Voltage vs Output Current
-4.10
-4.08

o

-4.07

-4.06
~ -4.04
vee =3.3V
-4.02
TRIPlER MODE
i -4.00 f--- f--- vee - 5V
~ -3.98 I--I-- DOUBLER MODE

!
l

2:
-

~

!5
~
:::>

-3.96

o

o

1

2

3

4

5

6

7

8

9 10

OUTPUT CURRENT (rnA)
lTCl429'TPCOl

I

-4.06

DOUBlE~ :::::::

IL=5mA

-4.04
-4.03

V
./

-4.02

-4.01

-3.92

_ TAI= 25JC

~ -4.05
!:;

-3.94
-3.90

45

-4.08

f-i =i5 e
A

Maximum Output Current vs
Supply Voltage

Output Voltage vs Supply Voltage

/'

V

/r
TRIPlER MODE

I

.1

I.

_VOUT=-4V±5%
« 40 TA =25°C

S
>-- 35
1E
c:: 30
c::
:::>

'-'

>--

:::>
D..

>--

:::>
0

IL =5mA

:;;
:::>
:;;

I I

::;;

~

""V

L

25

./

. / "/
/

/

/~OUBlER MOOE

20 PRIPlER MODE
15
10

f"'"

-4.00
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)

o

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)

lTC1429.TPC02

4-43

II

LTC1429
TYPICAL PERFORmAnCE CHARAOERISTICS
(See Test Circuits: Figure 1 for Doubler Mode, Figure 2 for Tripier Mode)
Supply Current vs Supply Voltage
1000
900
800

r
r

.1

1700

15
a:
gs
to

600
500

-

......

1.7......
J--

I-""

DOUBLER MODE-

Q.



-

600

I

DOUBLERM~I-'"

I--

-

-

Vee=3.3V
TRIPLER MODE

750

~

r--

gs

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
SUPPLY VOLTAGE (V)

600

TRIPLER MODE
VCC=3.3V ~

-I

to

~

:t
=>

550

-4.7SV for a-SV set point). If
the magnitude of the output is forced higherthan the magnitude of the set point (Le., to -6V when the output is set forSV) the REG output will stay low.
OUTPUT RIPPLE

Output ripple in the LTC1429 comes from two sources:
voltage droop at the output capacitor between clocks and
frequency response of the regulation loop. Voltage droop
is easy to calculate. With a typical external input clock
frequency of 700kHz, the charge on the output capacitor
is refreshed once every 1.43J.1S. With a 1SmA load and a . .
3.3/lf output capacitor, the output will droop by:
..
ILOAD x

(C~~T) = 1SmA x (j~~s) = 6.SmV

There can be a significant ripple component when the
output is heavily loaded, especially if the output capacitor
is small or the external input clock frequency is low. If
absolute minimum output ripple is reqUired, a 10/lf or
greater output capacitor, high input clock rate (FSYNc) and
lower value « O.1/lf) of flying capacitor should be used.
Regulation loop frequency response is the other major
contributor to output ripple. The LTC1429 regulates the
output voltage by limiting the amount of charge transferred to the output capacitor on a cycle-by-cycle basis.
The output voltage is sensed at the ADJ pin (COMP for
fixed output versions) through an internal or external
resistor divider from the OUT pin to ground. As the flying
caps are first connected to the output, the output voltage
begins to change quite rapidly. As soon as it exceeds the
set pOint, COMP1 trips, switching the state of the charge
pump and stopping the charge transfer. Because the RC
time constant of the capacitors and the switches is quite
short, the ADJ pin must have a wide AC bandwidth to be
able to respond to the output in time. External parasitiC
capacitance atthe ADJ pin can reduce the bandwidth to the
point where the comparator cannot respond by the time

4-47

LTC1429
APPLICATions InFoRmATion
the clock pulse finishes. When this happens, the comparator will allow a few complete pulses through, then overcorrect and disable the charge pump until the output
drops below the set point. Under these conditions, the
output will remain in regulation, but the output ripple will
increase as the comparator "hunts" for the correct value.
To help preventthis from happening, an external capacitor
can be connected from AOJ (or COMP for fixed output
parts) to ground to compensate for external parasitics and
increase the regulation loop bandwidth (Figure 5). This
sounds counter-intuitive until we rememberthatthe internal reference is generated with respectto OUT, not ground.
The feedback loop actually sees ground as its "output";
thus the compensation capacitor should be connected
across the "top" of the resistor divider from AOJ (or
COMP) to ground. By the same token, avoid adding
capacitance between AOJ (or COMP) and VOUT; this will
slow down the feedback loop and increase output ripple.
A 1000pF capacitor from AOJ or COMP to ground will
compensate the loop properly under most conditions.
TO CHARGE
PUMP

current. The clock signal should have aduty cycle between
40% and 60% for proper regulation loop performance.
The LTC 1429 can be shut down by stopping the clock. An
internal circuit monitors the time between clock edges at
the SYNC/SO pin. If a1OJ.lS period elapses without arising
or falling edge, LTC1429 assumes the clock has stopped
and goes into shutdown mode and the quiescent current
drops to below 1JlA. The next clock edge at the SYNC/SO
pin will reawaken the LTC1429. At clock frequencies
below 50kHz (50% duty cycle) the LTC1429 may enter
shutdown mode briefly during each clock cycle causing
erratic operation. Minimum operating frequency should
be kept above 60kHz (above 100kHz with Vee> 5) to
prevent this from happening.
Radiation from the clock signal at the SYNC/SO pin can
interfere with the feedback node at the AOJ/COMP pin
causing errors in the output voltage. The clock line should
be routed away from the circuitry at the AOJ/COMP pin
and should be shielded with aground plane orwith coaxial
cable. Acompensation capacitor from the AOJ/COMP pin
to ground can also help to reduce this effect: 0.001~ is
adequate for most applications.
OUTPUT FILTERING

-L-Cc

"::"

-,-1000pF

--,

ADJ/COMP

--r--'

VOUT

RESISTORS ARE INTERNAL
FOR FIXED OUTPUT PARTS

111""'·'"

Figure 5. Regulator Loop Compensation

If extremely low output ripple « 1OmV) is required, additional output filtering is required. Because the LTC1429
uses a high, external control switching frequency, fairly
low value RC or LC networks can be used at the output to
effectively filter the output ripple. With FSYNe = 700kHz, a
10n series output resistor and a 3.3~ capacitor will cut
output ripple to below 3mV (see Figure 6). Further reduc5V

EXTERNAL CLOCK

The LTC1429 requires an external clock to operate. This
clock signal should be TTL or CMOS compatible and
should be applied to the SYNC/SO pin. The external clock
allows the user to control the frequency at which the
LTC1429 operates, preventing it from interfering with
other frequency-sensitive circuitry. The LTC1429 can be
synchronized to any frequency between 60kHz (100kHz
for Vee> 5) and 2MHz. Higher clock frequencies can help
reduce output ripple at the cost of additional quiescent

4-48

-=-----...-¥.,.,......~- VOUT = -4V

Figure 6. Output Filter Cuts Ripple Below 3mV

LTC1429
APPLICATions InFoRmATion
tions can be obtained with larger filter capacitors or by
using an LC output filter or higher FSYNC clock rate with a
lower value «0.1~) of flying capacitor. Also see the
section on Output Capacitor ESR. For applications requiring ripple below 1mV, see the LTC1550/LTC1551 data
sheet.

CAPACITOR SELECTION
Capacitor Sizing
The performance is dependent on the type of capacitors
used. The LTC1429 requires bypass caps to ground for
both the Vcc and OUT pins. The input cap provides most
of the LTC1429's supply current while it is charging the
flying caps. It should be mounted as close to the package
as possible, its value should be equal to or larger than the
flying cap in doubling mode and at leasttwice the value of
the flying caps in tripling mode. Ceramic capacitors
generally provide adequate performance; avoid using a
tantalum capacitor as the input bypass unless there is at
least a 0.1 ~ ceramic cap in parallel with it. The charge
pump caps are somewhat less critical, since their peak
currents are limited by the switches inside the LTC1429.
Most applications should use 0.1 ~ as the flying cap
value; conveniently, ceramic caps are the most common
type of 0.1 ~ cap and they work well here. Usually the
easiest solution is to use the same type of capacitor for
both the input bypass and flying caps.
The output cap performs two functions; it provides output
current to the load during half of the charge pump cycle
and its value helps to set the output ripple voltage. For
applications that are insensitive to output ripple, the
output bypass cap can be as small as 1~. To achieve
specified low output ripple, a 3.3~ or greater output
capacitor, high input clock rate (FSYNc) and lower value
« 0.1~) of flying capacitor should be used. Larger output
caps will reduce output ripple further, at the expense of
turn on time.
In an application where the maximum load current is welldefined and output ripple is critical or input peak currents
need to be minimized, the flying capacitor values can be
tailored to the application. Reducing the value of the flying
capacitors reduces the amount of charge transferred with

each clock cycle. The smaller capacitors draw smaller
pulses of current out ofVcc as well, limiting peak currents
and reducing the demands on the input supply. Tables 1
and 2 show recommended values of flying capacitors vs
maximum load capacity at FSYNC = 400kHz and 700kHz
respectively.
Table 1. Typical Max Load (rnA) vs Flying Capacitor Value at
TA =25°C, VOUT =-4V, FSYNe =400kHz
MAX LOAD (rnA)
MAX LOAD (rnA)
FLYING CAPACITOR
Vee =3.3V
Vee =5V
DOUBLER MODE
TRIPLER MODE
VALUE (!If)
20
0.1
22
0.047
16
15
0.033
8
11
4
5
0.022
0.01
1
3
Table 2. Typical Max Load (rnA) vs Flying Capacitor Value at
TA =25°C, VOUT =-4V, FSYNe =700kHz
MAX LOAD (rnA)
MAX LOAD (rnA)
FLYING CAPACITOR
Vee =3.3V
Vee =5V
DOUBLER MODE
TRIPLER MODE
VALUE (!If)
18
25
0.1
0.047
17
22
14
20
0.033
17
0.022
12
9
0.01
3

Output Capacitor ESR
Output capacitor the Equivalent Series Resistance (ESR)
is another factor to consider. Excessive ESR in the output
capacitor can fool the regulation loop into keeping the
output artificially low by prematurely terminating the charging cycle. As the charge pump switches to recharge the
output, a brief surge of current flows from the flying caps
to the output cap. This current surge can be as high as
1OOmA under full load conditions. AtypicaI3.3~tantalum
capacitor has 10 or 20 of ESR; 1OOmA x 20 =200mV. If
the output is within 200mV of the set pOint, this additional
200mV surge will trip the feedback comparator and terminate the charging cycle. The pulse dissipates quickly and
the comparator returns to the correct state, but the RS
latch will not allow the charge pump to respond until the
next clock edge. This prevents the charge pump from

4-49

LTC1429
APPLICATions InFoRmATion
going into very high frequency oscillation under such conditions. It also creates an output error as the feedback loop
regulates based on the top ofthe spike, not the average value
ofthe output (Figure 7). The resulting output voltage behaves
as if aresistor of value CESR x (lpI(lIAVE)Q was placed in series
with the output. To minimize this effect, output capacitor ESR
should be as low as possible or smaller value high frequency
bypass (typically a0.1 /If ceramic) should be added in parallel
with the output capacitor.
I
I

CLOCK

I
I

"~~~{ ri~''''h r~'
--:-----------~--,uuuui-- ~SET

HIGH ESR
OUTPUT CAP

{

-------------. - - I
VOUT

I
I

n

I.

I

I
I

OUT
AVERAGE
COMpl
OUTPUT
LTC1429-F07

Figure 7. Output Ripple with Low and High ESR Caps
Note that ESR in the flying caps will not cause the same
condition; in fact, it may actually improve the situation by
cutting the peak currents and lowering the amplitude of
the spike. More flying cap ESR is not necessarily better,
however; as soon as the RC time constant approaches half
of a clock period (the time the capacitors have to share
charge at full duty cycle) the output current capability of
the LTC1429 will begin to diminish. For 0.1/lf flying
capacitors and typical 700kHz external clock, this gives a
maximum total series resistance of:

t(~~~~) =t(70~kHZ) / 0.1~F = 7.14Q
Most of this resistance is already provided by the internal
switches in the LTC1429 (especially in tripler mode). More
than 1Q or 2Q of ESR on the flying caps will start to affect
the regulation at maximum load.

RESISTOR SELECTION
Resistor selection is easy with the fixed output versions of
the LTC1429; no resistors are needed! Selecting the right
resistors for the adjustable parts is only a little more

4-50

difficult. A resistor divider should be used to divide the
signal at the output to give 1.24V· at the ADJ pin with
respect to Vour(Figure 8). The LTC1429 uses a positive
reference with respect to VOUT, not a negative reference
with respect to ground (Figure 4 shows reference connection). Be sure to keep this in mind when connecting the
resistors! If the initial output is not what you expected, try
swapping the two resistors.

~~.......-

VOUT = -1.24V (Rl:2R2)
LTC1429-FQ7

Figure 8. External Resistor Connections
The 14-pin adjustable parts include a built-in resistor
string which can provide an assortment of output voltages
by using different pin-strapping options at the RO, R1 and
RADJ pins (Table 3). The internal resistors are roughly
124k, 226k, 100k and 50k (see Figure 4) giving output
options of -3.5V, -4V, -4.5V and -5V. The resistors are
carefully matched to provide accurate divider ratios, but
the absolute values can vary substantially from part to
part. It's not a good idea to create a divider using an
external resistor and one of the internal resistors unless
the output voltage accuracy is not critical.
Table 3. Output Voltages Using the Internal Resistor Divider
PIN CONNECTIONS
OUTPUT VOLTAGE
-5.0V
ADJ -RADJ
ADJ -RADJ, RO -GND
-4.5V
-4.0V
ADJ -RADJ, R1 -RO
ADJ -RADJ, R1-GND
-3.5V
ADJ -R1
-1.77V
ADJ -RO
-1.38V
ADJ -GND
-1.24V
There are some oddball output voltages available as well.
They are obtained by connecting ADJ to RO or R1 and
shorting out some of the internal resistors. If one of them
gives you the output voltage you want, by all means use it!

LTC1429
APPLICATions InFoRmATion
The internal resistor values are the same for the fixed
output versions of the LTC1429 as they are for the adjustable parts. The output voltage can be trimmed, if desired,
by connecting external resistance from the CaMP pin to
OUT or ground to alter the divider ratio. As in the adjustable
parts, the absolute value of the internal resistors may vary
significantly from unit to unit. As a result, the further the
trim shifts the output voltage, the less accurate the output
voltage will be. If a precise output voltage other than one

of the available fixed voltages is required, it's better to use
an adjustable LTC1429 and use precision external resistors. The internal reference is trimmed at the factory to
within 3.5% of 1.24V. With 1% external resistors, the
output will be within 5.5% of the nominal value, even
under worst case conditions.
The LTC1429 can be internally configured with nonstandard fixed output voltages. For details, contact the Linear
Technology Marketing Department.

TYPICAL APPLICATiOnS
3.3V In, -4.5V Out GaAs FET Bias Generator

5V In, -4V Out GaAs FET Bias Generator

P-CHANNEL
POWER SWITCH

VBAT

P-CHANNEL
POWER SWITCH

-------t-........

3.3V-.---,
5V.....----'-

GaAs
TRANSMITTER

-5V Supply Generator
3V",VCC",7V

Minimum Paris Count-4V Generator
5V.....----'-

=-4V

o.
.;.:.......-_ ~¥~TO~A5V ±5%
3.3!1F

4-51

LTC1429
TYPICAL APPLICATions
1mV Ripple, 5V In, -4V Out GaAs FET Bias Generator
P-CHANNEL
POWER SWITCH
VSAT - - - - - -......- -...... . . . . - - - - - - - ,

.Jl..JL _ _ _----.
5V-...--"":'"

GaAs
TRANSMITIER

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1121

Micropower Low Dropout Regulators with Shutdown

OAV Dropout Voltage at 150mA, Low Noise, Switched
Capacitor Regulated Voltage Inverter

LTC1261

Switched Capacitor Regulated Voltage Inverter

Selectable Fixed Output Voltage

LTC1550/LTC1551

Low Noise Switched Capacitor Regulated Voltage Inverter

GaAs FET Bias with Linear Regulator 1mV Ripple

4-52

I'''''''-Llnt1\~D_ _LT_C660

~,

lOOmA CMOS
Voltage Converter

TECHNOLOGY

FEATURES

DESCRIPTiOn

• Simple Conversion of 5V to -5V Supply
• Output Drive: 100mA
• ROUT: 6.5Q (O.65V Loss at 100mA)
• Boost Pin (Pin 1) for Higher Switching Frequency
• Inverting and Doubling Modes
• Minimum Open Circuit Voltage Conversion
Efficiency: 99%
• Typical Power Conversion Efficiency
with a 100mA Load: 88%
• Easy to Use

The LTC®660 is a monolithic CMOS switched-capacitor
voltage converter. It performs supply voltage conversion
from positive to negative from an input range of 1.SV to
S.SV, resulting in complementary output voltages of
-1.SV to -S.SV. It also performs a doubling at an input
voltage range of 2.SV to S.SV, resulting in a doubled
output voltage of SV to 11V. Only two external capacitors
are needed for the charge pump and charge reservoir
functions.

APPLICAnons
•
•
•
•

Conversion of SV to ±SV Supplies
Inexpensive Negative Supplies
Data Acquisition Systems
High Current Upgrade to LTC1044 or 7660

The converter has an internal oscillator that can be
overdriven by an external clock or slowed down when
connected to a capacitor. The oscillator runs at a 10kHz
frequency when unloaded. Ahigher frequency outside the •
audio band can also be obtained if the Boost pin is tied
to V+.
The LTC660 contains an internal oscillator, divide-by-two,
voltage level shifter and four power MOSFETs.
ff, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Generating -5V from 5V

Output Voltage vs Load Current
for V+ =5V
-s.O

~

-4.8

~

~
w

~ -4.5

':i
§;
~-4.4

5o

TA =2SOC
ROUT =5.sn

.......

" '"

..........

-4.2
-4.0

o

20

40

50

80

100

LOAD CURRENT (rnA)

L7lJ!J~

4-53

LTC660
ABSOLUTE mAxmum RATinGS

PACKAGE/ORDER InFORmATion

(Note 1)
ORDER PART
NUMBER

TOP VIEW

Supply Voltage (V+) .................................................. 6V
Input Voltage on Pins 1, 6, 7
(Note 2) ............................ -0.3V < VIN .( (V+ + 0.3V)
Output Short-Circuit Duration to GND
(Note 5) ......•.................................•....•.•............. 1 sec
Power Dissipation ..............................•...•........... 500mW
Operating Temperature Range ....•..•...•........ O°C to 70°C
Storage Temperature Range .......•......•.. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

~~o~
CApt 2
GND 3
CAP- 4

7

6
5

osc
LV
VOUT

LTC660CN8
LTC660CS8

N8 PACKAGE
HEAD PDIP
58 PACKAGE
HEAD PLASTIC SO

S8 PART MARKING
660

TJMAX = 100°C, BJA = 100°C/W (N8)
TJMAX = 100'C, BJA = 151l"C/W (58)
Consult Factory for Industrial and Military grade parts,

ELEORICAL CHARACTERISTICS
v+ =5V, C1 and C2 =1501lf, Boost =Open, Cose =DpF,TA =25°C, unless otherwise noted.
SYMBOL PARAMETER

MIN

CONDITIONS

Supply Voltage

RL =lk

Inverter, LV =Open
Inverter, LV =GND
Doubler, LV =VOUT

Is

Supply Current

No Load

Boost =Open
Boost =V+

lOUT

Output Current

VOUT More Negative Than -4V

ROUT

Output Resistance

IL =1OOmA (Note 3)

fosc

Oscillator Frequency

Boost =Open
Boost =V+ (Note 4)

Power Efficiency

RL =lk Connected Between V+ and VOUT
RL =5000 Connected Between VOUT and GND
IL =1OOmA to GND

Voltage Conversion Efficiency

No Load

Oscillator Sink or Source Current

Boost =Open
Boost =V+

The. denotes specifications which apply over the full operating
temperature range; all other limits and typicals are at TA = 25°C.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Connecting any input terminal to voltages greater than V+ or less
than ground may cause destructive latch-up, It is recommended that no
inputs from source operating from external supplies be applied prior to
power-up of the LTC660.
Note 3: The output resistance is a ,combination of internal switch
resistance and external capacitor ESR. To maximize output voltage and
efficiency, keep external capacitor ESR < 0,20.

4-54

••
•
••
•
•

100

•

•

TYP

3
1.5
2,5

MAX
5,5
5.5
5,5

0,08
0,23

0.5
3

6.5

10

UNITS
V
V
V
rnA
rnA
rnA
0

10
45

kHz
kHz

96
92

98
96
88

%
%
%

99

99,96

%

±1,1
±5,O

j.IA
j.IA

Note 4: fose is tested with Case = 1OOpF to minimize the effects of test
fixture capacitance loading. The OpF frequency is correlated to this 100pF
test point, and is intended to simulate the capacitance at pin 7 when the
device is plugged into a test socket and no external capacitor is used.
Note 5: OUT may be shorted to GND for 1 sec without damage, but
shorting OUT to V+ may damage the device and should be avoided, Also,
for temperatures above 85°C, OUT must not be shorted to GND or V+,
even instantaneously, or device damage may result.

LTC660
TYPICAL PERFORmAnCE CHARACTERISTICS

1000

300

/

250

;:c
""
r-

200

tf:

a:

/

~ 150

:J
it
::>

BOOST =
100



\

\

I'" r-- F=:

\

70

,/

-

'"'" ", ~
N

65
0

IX

90

EFFICIENCY

C

85

~

80

~

75

I

'"

\

>-

U

\

\

70

10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (mA)

65

o

-4.6

0

J.-n

l-e-

-5.0
0

-

m

80

i'5

76

~

-<

72

V

68
64

60
10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (mA)

10

V+=3.5V

""

10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (mA)

TF 25°C
BOOST IOPfN

0.9

5.5V

V::4~~

~N

LTC660
OUTPUT VOLTAGE

Q

Output Voltage Drop
vs Load Current

v+

r---..
"

m

~

r-- r--

::>

v+ = 5V

V+ = 25V"'-

\

60

88
84

Ei: -4.2

f-

III

92

r-- r-

o
>

--v-

v+ = 1.5V

\

--

96

~

TA = 25°C
BOOST - V+

r--...

1/ \

100

100
TA = 25°C
BOOST = OPEN

~ -3.8

95 11>-

V+=25Y'\

\

10
OSCILLATOR FREQUENCY (kHz)

w

100

~5.5V

"" ........

v+ = 15V\

r-....

L~C6ra-

~

Efficiency vs Load Current

TA = 25°C
BOOST = OPEN

22~F

Output Voltage and Efficiency
vs Load Current, V+ = 5V

o
-60 -40 -20 0 20 40 60 80 100120 140
TEMPERATURE (OC)

v+ = 3.5V

U

C1 = C2 =

f-

0-

o

fA" ,

~

I--

~

-3.4

v+=v /"

10

o

85

60

V

III

:-jlr "f,~,~ '~"r:

o

1000

V
./

i V
V

r-

~:--..

III

'\ ~C1 =C2=150~F

-3.0
BOOST = OPiN

\

90

75

0.1
1
10
100
OSCILLATOR FREQUENCY (kHz)

20

""

IltoOS[JJiEN

\

20 I--

J+ = 5V

95

~

30

Output Resistance vs Temperature

~

\

10 ~

HI

100

80

40

f0

Efficiency vs Load Current

~

w

f-

5:'

SUPPLY VOLTAGE (V)

~
>-

50

a:

25

iB
a:
t::;

60

::>

TA = 25°C
BOOST = OPEN

r-

o

z
«

'!!

f-

r--

2.5 3 3.5
4 4.5
SUPPLY VOLTAGE (V)

10

5:'

70

TA =25°C
V+ = 5V

\
\

80

9:
w



35

15
::>

30

'-'

/

~

50
0.1

~

U
en
0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)

1
10
OSCILLATOR FREQUENCY (kHz)

1/

/

"'

~ 10
~

iii
::>
o

FE

/

6

a:
o

~

15

U
en

o

o

o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)

V+=5V
BOOST = OPEN
= OPEN

ose

-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE ('C)

lTC66lIoTPC13

Oscillator Frequency
vs Temperature

Oscillator Frequency
vs External Capacitance
100

50
'N

~

40

>

'-'

15
::>
S

30

e:
a:

~

20

...J

U

en
0

10 V+=5V
BOOST = v+
OSC = OPEN

o

-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE ('C)

~

10

~

@
e:a:

~

~ 0.1

o
00.1

L....l...J..J..JWlJJ.-..L.LJJJIlllL...l....I..L.LU.llL...LLlliillJ

1

10

100
1000
CAPACITANCE (pF)

10000

LTC6600TPC17

4-56

100

12

.,,-

10

o

TA = 25'C
V+=5V
BOOST = OPEN

Oscillator Frequency
vs Temperature

/

25
a: 20
0

/

\

IL=1mA

65

55

100

V

j

60

Oscillator Frequency
vs Supply Voltage

TA= 25'C
BOOST = OPEN
OSC = OPEN

o

~

U

IL=10mA j1L=80mA

80

iii

\

V

I

85
75

TA =25'C
V+=5V
BOOST = OPEN

Oscillator Frequency
vs Supply Voltage

o

e:.
>
'-'

-3.0

5V

o 10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (mA)

12

V

I

-

.....

90

{~11IJ~~

~
./

95

IL=1!S
-4.5

/

EHiciency vs Oscillator Frequency
100

-5.0

LTC660

Pin FunOlons
PIN

NAME

INVERTER

DOUBLER

1

BOOST

Internal Oscillator Frequency Control Pin.
Boost = Open, fose = 10kHz typ;
Boost = V+, fose = 45kHz typ; when OSC is driven
externally Boost has no effect.

Same

Same

2

CAP+

Positive Terminal for Charge Pump Capacitor

3

GNO

Power Supply Ground Input

Positive Voltage Input

4

CAP-

Negative Terminal for Charge Pump Capacitor

Same

5

VOUT

Negative Voltage Output

Power Supply Ground Input

6

LV

Tie LV to GND when the input voltage is less than 3V.
LV may be connected to GND or left open for input
voltages above 3V. Connect LV to GND when
overdriving OSC.

LV must be tied to VouTfor all input voltages.

7

OSC

An external capacitor can be connected to this pin to
slow the oscillator frequency. Keep stray capacitance
to a minimum. An external oscillator can be applied
to this pin to overdrive the internal oscillator.

Same except standard logic levels will not be able to
overdrive OSC pin.

8

V+

Positive Voltage Input

Positive Voltage Output

_____________________________ 11
TEST CIRCUIT

'---'--:e:':'"1-----41-- VOUT

T+ 150I'F
Figure 1. Test Circuit

4-57

LTC 660
APPLICATions InFoRmATion
Theory of Operation
To understand the theory of operation for the LTC660, a
review of a basic sWitched-capacitor building block is
helpful. In Figure 2, when the switch is in the left position,
capacitor C1 will charge to voltage V1. The total charge on
C1 will be q1 = C1V1. The switch then moves to the right,
discharging C1 to voltage V2. After this discharging time,
the charge on C1 is q2 = C1 V2. Note that charge has been
transferred from the sou rce V1 to the output V2. The
amount of charge transferred is:

CLOSED WHEN
V' > 3.0V

f1q = q1 - q2 = C1 (V1 - V2)
If the switch is cycled "f" times per second, the charge
transfer per unit time (Le., current) is:
I = f x f1q = f x C1 (V1 - V2)
Rewriting in terms of voltage and impedance equivalence,
I = V1- V2
1/fC1

= V1- V2
REQUIV

A new variable REQUIV has been defined such that
REQUlv= 1/fC1. Thus, the equivalentcircuitforthe switchedcapacitor network is as shown in Figure 3.
Figure 4 shows that the LTC660 has the same switching
action as the basic switched-capacitor building block.

Figure 4. LTC660 Switched-Capacitor Voltage Converter
Block Diagram

This simplified circuit does not include finite on-resistance
of the switches and output voltage ripple, however, it does
give an intuitive feel for how the device works. For example, if you examine power conversion efficiency as a
function of frequency this simple theory will explain how
the LTC660 behaves. The loss and hence the efficiency is
set by the output impedance. As frequency is decreased,
the output impedance will eventually be dominated by the
1/fC1 term and voltage losses will rise decreasing the
efficiency. As the frequency increases the quiescent current increases. At high frequency this current loss becomes significant and the power efficiency starts to decrease.
The LTC660 oscillator frequency is designed to run where
the voltage loss is a minimum. With the external150~
capacitors the effective output impedance is determined
by the internal switch resistances and the capacitor ESRs.

Figure 2. Switched-Capacitor Building Block

LV (Pin 6)
The internal logic of the LTC660 runs between V+ and LV
(pin 6). ForV+23V, an internal switch shorts LVto ground
(pin 3). For V+ < 3V, the LV pin should be tied to ground.
ForV+23V, the LV pin can be tied to ground or leftfloating.
OSC (Pin 7) and Boost (Pin 1)

Figure 3. Switched-Capacitor Equivalent Circuit

4-58

The switching frequency can be raised, lowered or driven
from an external source. Figure 5 shows a functional
diagram of the oscillator circuit.

LTC660
APPLICATions InFoRmATion
v+

OSC INPUT

Figure 6. External Clocking

Capacitor Selection
Figure 5. Oscillator

By connecting the Boost pin (pin 1) to V+, the charge and
discharge current is increased and, hence, the frequency
is increased by approximately four and a half times.
Increasing the frequency will decrease output impedance
and ripple for high load currents.
Loading pin 7 with more capacitance will lower the frequency. Using the Boost (pin 1) in conjunction with
external capacitance on pin 7 allows user selection of the
frequency over a wide range.
Driving the LTC660 from an external frequency source can
be easily achieved by driving pin 7 and leaving the Boost
pin open, as shown in Figure 6. The output current from
pin 7 is small, typically 1.11JA to 51JA, so a logic gate is
capable of driving this current. (A CMOS logic gate can be
used to drive the OSC pin.) For5V applications, aTIL logic
gate can be used by simply adding an external pull-up
resistor (see Figure 6) .

.L7lJD~

While the exact values of C1 and C2 are noncritical, good
quality, low ESR capacitors are necessary to minimize
voltage losses at high currents. ForC1 the effect ofthe ESR
of the capacitor will be multiplied by four, due to the fact
the switch currents are approximately two times higher . , . .
than the output current and losses will occur on both the . .
charge and discharge cycle. This means using acapacitor
with 10 of ESR for C1 will have the same effect as
increasing the output impedance of the LTC660 by 40.
This represents asignificant increase in the voltage losses.
For C2 the effect of ESR is less dramatic. A C2 with 10 of
ESR will increase the output impedance by 10. The size
of C2 and the load current will determine the output
voltage ripple. It is alternately charged and discharged at
a current approximately equal to the output current. This
will cause a step function to occur in the output voltage at
the switch transitions. For example, for a switching frequency of 5kHz (one-half the nominal 10kHz oscillator
frequency) and C2 = 150~ with an ESR of 0.20, ripple is
approximately 90mV with a 1OOmA load current.

4-59

LTC660
TYPICAL APPLICATions
Negative Voltage Converter

Voltage Doubling

Figure 7 shows a typical connection which will provide a
negative supply from an available positive supply. This
circuit operates over full temperature and power supply
ranges without the need of any external diodes. The LV pin
(pin 6) is shown grounded, but for V+ ~ 3V, it may be
floated, since LV is internally switched to ground (pin 3)
for V+ ~ 3V.

Figure 8 shows the LTC660 operating in the voltage
doubling mode. The external Schottky (1 N5817) diode is
for start-up only. The output voltage is 2 x VIN without a
load. The diode has no effect on the output voltage.
1N5817'

VIN
1.5VTO 5.5V

VOUT =-VIN

C1
VIN
150llF
2.5V --4o----t---'
TO 5.5V

"'---+--VOUr= 2VIN
C2
150llF

• SCHOTTKY DlOOE IS FOR START-UP ONLY

Figure 8. Voltage Doubler
Figure 7. Voltage Inverter

Ultra-Precision Voltage Divider
The output voltage (pin 5) characteristics ofthe circuit are
those of anearly ideal voltage source in series with a6.50
resistor. The 6.50 output impedance is composed of two
terms: 1) the equivalent switched-capacitor resistance
(see Theory of Operation), and 2)a term related to the onresistance of the MOS switches.

An ultra-precision voltage divider is shown in Figure 9. To
achieve the 0.002% accuracy indicated, the load current
should be kept below 100nA. However, with a Slight loss
in accuracy, the load current can be increased.
V+
3VTO 11V

At an oscillator frequency of 10kHz and C1 = 150!!F, the
first term is:

1
REQUIV = (fosc/ 2) x C1 =

1
3
6 =1.3Q.
5 x 10 x 150 x 10Notice that the equation for REQUIV is not a capacitive
reactance equation (Xc = 1/roC) and does not contain a
21t term.
The exact expression for output impedance is complex,
butthe dominant effect ofthe capacitor is clearly shown on
the typical curves of output impedance and power efficiency versus frequency. For C1 =C2 =150!!F, the output
impedance goes from 6.50 at fosc = 10kHz to 1100 at
fosc = 100Hz. As the 1/fC term becomes large compared
to the switch on-resistance term, the output resistance is
determined by 1lfC only.

4-60

LTC660 0 F09

Figure 9. Ultra-Precision Voltage Divider

Battery Splitter
Acommon need in many systems is to obtain positive and
negative supplies from a Single battery or single power
supply system. Where current requirements are small, the
circuit shown in Figure 10 is asimple solution. It provides
symmetrical positive or negative output voltages, both
equal to one-halfthe input voltage. The output voltages are
both referenced to pin 3 (Output Common).

L7lJ!J~

LTC 660
TYPICAL APPLICATions
Paralleling for Lower Output Resistance
-=------+Vpj2 (4.SV)

Additional flexibility of the LTC660 is shown in Figures 11
and 12. Figure 11 shows two LTC660s connected in
parallel to provide a lower effective output resistance. If,
however, the output resistance is dominated by 1/fC1,
increasing the capacitor size (C1) or increasing the frequency will be of more benefit than the paralleling circuit
shown.

"::";---t- -Vpj2 (-4.5V)

OUTPUT COMMON

Stacking for Higher Voltage

Figure 10. Ballery Splitter

Figure 12 makes use of "stacking" two LTC660s to provide
even higher voltages. In Figure 12, a negative voltage
doublerortriplercan be achieved depending upon how pin
8 ofthe second LTC660 is connected, as shown schematically by the switch.

•

r-------------.- V

+

~----1~ VOUT = -v+
I
I

I

I

________

I

:--~---~\~L----j

1

C2
"I+ 150l'F

&------------------------------------~'l~1
1 ______ -,

OPTIONAL SYNCHRONIZATION
CIRCUIT TO MINIMIZE RIPPLE

Figure 11. Paralleling for 200mA Load Current

FORVOUT=-3V+--

v+-t--------------o

- - FORVOUT=-2V+

-"---+-.. -v+

Figure 12. Stacking for High Voltage

4-61

LTC660

RELATED PARTS
COMMENTS
Unregulated Output Voltage
LTC660

100mA

6V

LTC1046

SOmA

6V

Highest Current

LTC1044

20mA

9.SV

LTC1044A

20mA

13V

LTC1144

20mA

20V

Highest Voltage
Adjustable Output

Lowest Cost

Regulated Output Voltage
LT10S4

100mA

16V

LTC1262

30mA

6V

12V Fixed Output

LTC1261

10mA

9V

-4V, -4.SV and Adjustable
Outputs

All devices are available in plastic 8-lead SO and PDIP packages

4-62

INDEX
SECTION 4-POWER PRODUCTS
LINEAR REGULATORS .................................................................................................................. 4-63
LT1118-2.5/LT1118-2.85/LT1118-5, Low la, Low Dropout, 800mA Source and Sink Regulators
Fixed 2.5V, 2.85V, 5V Output ....................................................................................................... 4-64
LT1175, 500mA Negative Low Dropout Micropower Regulator ............................................................... 4-68
LT1521/LT1521-3/LT1521-3.3/LT1521-5, 300mA Low Dropout Regulators with Micropower
Quiescent Current and Shutdown .................................................................................................. 4-79
LT1528, 3A Low Dropout Regulator for Microprocessor Applications .. ..................................................... 4-91
LT1529/LT1529-3.3/LT1529-5, 3A Low Dropout Regulators with Micropower Quiescent Current and Shutdown ... 4-101
LT1580/LT1580-2.5, 7A, Very Low Dropout Regulators .................................................................... 13-148
LT1584/L T1585/L T1587, 7A, 4.6A, 3A Low Dropout Fast Response Positive Regulators Adjustable and Fixed ..... 4-112

4-63

.f=Af\
L1n
£7 U \K

LTl1l8-2.5
LT11 18-2.85/LTl 118-5
TECHNOLOGY~Lo-w-IQ-,-L-o-w-D-ro-p-o-u-t-,-80-0-m-ASource and Sink Regulators
Fixed 2.5V 2.85V, 5V Output

FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•

The LT®1118 family of low dropout regulators has the
unique capability of maintaining output regulation while
sourcing or sinking load current. The 2.85Voutputvoltage
regulator is ideal for use as a Boulay termination of up to
27 SCSI data lines. The regulator maintains regulation
while both sourcing and sinking current, enabling the use
of active negation drivers for improved noise immunity on
the data lines. Regulation of output voltage is maintained
for TERMPWR voltages as low as 4.0V. When unloaded,
quiescent supply current is alow600~, allowing continuous connection to the TERMPWR lines. An ultra-low
power shutdown mode is also available on the SO-8
version. In Shutdown the output is high impedance and
supply current drops to less than 1O~.

Regulates While Sourcing or Sinking Current
Provides Termination for up to 27 SCSI Lines
6DDIlA Quiescent Current
Ultra-Low Power Shutdown Mode
Current Limit and Thermal Shutdown Protection
Stable for Any CLOAD ;::: O.22!JF
Fast Settling Time
1V Dropout Voltage

APPLICATions
•
•
•
•
•

Active Negation SCSI Terminations
Computers
Disk Drives
CD-ROM
Supply Splitter

Current limits in both sourcing and sinking modes, plus
on-chip thermal shutdown make the circuit tolerant of
output fault conditions.
The LT1118 is available in 3-lead SOT-223 and 8-lead SO
packages .
.LT, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Load Transient Response

4-64

LTll18-2.5
LTll18-2.85/LTll18-5
~8S0LUTE

mAxmum RATinGS

Note 1)

)upply Voltage (Vee) ............................................... 15V
nput Voltage (Enable) ............................... -O.2V to lV
)utput Voltage ............................... -O.2V to Vee + O.5V

Short-Circuit Duration .................................... Indefinite
Operating Temperature Range .................... O°C to lO°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
TOP VIEW

'"0·

OUT 2 .
GND 3
IN 4

GND
6 GND
5 NC
7

S8 PACKAGE
HEAD PLASTIC SO

TJMAX = 125°C, 8JC = WC/

ORDER PART
NUMBER
LT1118CS8-2.5
LT1118CS8-2.85
LT1118CS8-5

TAB IS
GND

S8 PART MARKING

w

ORDER PART
NUMBER

FRONT VIEW

111825
111828
11185

0"

LT1118CST-2.5
LT1118CST-2.85
LT1118CST-5

2 GND
1 OUT

ST PACKAGE
3-LEAD PLASTIC S01-223

TJMAX = 125°C, 8JC = WCI W

:onsult factory for Industrial and Military grade parts.

ELEORICAL CHARACTERISTICS
'ARAMETER
luiescent Current (VIN)
luiescent Current in Shutdown (VIN)
:nable InputThresholds
:nable Input Current
Jutput Voltage

.ine Regulation (Note 4)

.oad Regulation (Note 4)

LT1118-2.5

No Load (25°C)
All Operating Conditions (Note 3)

LT1118-5

No Load (25°C)
All Operating Conditions (Note 3)

LT1118-2.5
LT1118-2.85
LT1118-5
LT1118-2.5

IL = OmA, 4.2V ~ VIN ~ 15V
IL = OmA, 4.75V ~ VIN~ 15V
IL = OmA, 6.5V ~ VIN ~ 15V
OmA ~ IL ~ 800mA
-400mA ~ IL ~ OmA
OmA ~ IL ~ 800mA
-400mA ~ IL ~ OmA
OmA ~ IL ~ 800mA
-400mA ~ IL ~ OmA
IL = 100mA
IL = 800mA

LT1118-5

iipple Rejection

L7lJn~

CONDITIONS
VEN = 5V
VEN = OV
Input Low Level
Input High Level
OV ~VEN ~5V
No Load (25°C)
All Operating Conditions (Note 3)

LT1118-2.85

LT1118-2.85

lropout Voltage (Note 5)

(Note 2)

fRIPPLE = 120Hz, VIN - VOUT = 2V
VRIPPLE = 0.5Vp_p

MIN

•
•
••
•
•

•
•
••
•
••

0.8

TYP
0.6
1
1.4
1.4

-1
2.47
2.45
2.82
2.79
4.95
4.90

2.85
2.85
5.0
5.0

60

0.85
1.0
80

••
••

2.5
2.5

MAX
1
10
2.0
25
2.53
2.55
2.88
2.91
5.05
5.10
6
6
10
10
10
10
10
20
20
1.1
1.3

UNITS
rnA

I!A
V
V

I!A
V
V
V
V
V
V
mV
mV
mV
mV
mV
mV
mV
mV
mV
V
V
dB

4-65

LTll18-2.5
LT11 18-2. 85/LTl 118-5
ELECTRICAL CHARAOERISTICS

(Note 2)

PARAMETER
Load Transient Settling Time, I'N =1%

CONDITIONS
OmA $ Il $ 800mA, CLOAD =1!If
-400mA $Il $ OmA, CLOAD =1!If

MIN

Output Short-Circuit Current, Ise+
IseThermal Shutdown Junction Temperature
Enable Turn-On Delay

VOUT =OV
VOUT =VIN
No Load
No Load

800

TYP
5
5
1200
-700

MAX

UNITS
~
~

-400

170
50

mA
mA
°C
~

Note 3: All operating conditions include the combined effects of load
current, input voltage, and temperature over each parameter's full range.
Note 4: Load and line regulation are tested at a constant junction
temperature by low duty cycle pulse testing.
Note 5: Dropout voltage is defined as the minimum input to output voltage
measured while sourcing the specified current.

The. denotes specifications which apply over the operating temperature
range (O°C $ TA $ 70°C for commercial grade).
Note 1: Absolute maximum ratings are those values beyond which the life
of the device may be impaired.
Note 2: Unless otherwide specified, testing done at Vee = 5V
(LT1118-2.5, LT1118-2.85) or Vee = 7V (LT1118-5). VEN = Vee. Output
ClOAD = 1!1f, ILOAD = O.

TYPICAL PERFORmAnCE CHARAOERISTICS
Input Current vs
Output Sink Current

Dropout Voltage vs Output Current
2000

1.4
1.2

1.0
~

0.8

1750

T~=75!e~
;:~f--

~
~

Ground Pin Current vs
Output Source Current

~

:, 0.6

;>

-

--:

v

~ 1500

!z 1250

TJ _125°C -

,/'

~ 1000

!;::; 750
"-

;;;

500
250

o

800

a:

~

o

\.

400

0::

§i;l 300
:::J

~ 200

'"

o

200
400
600
OUTPUT CURRENT (rnA)

fZ

li! 500
:::J

~

0.2

o

V

/

u

0.4

;,;"

700

~ 600

50 100 150 200 250 300 350 400
OUTPUT SINK CURRENT (rnA)

100

OUTPUT SOURCING CURRENT (rnA)

LT111S0TPCOl

Pin FunOlons
IN: Input Supply Pin. This pin should be decoupled with a
1Jlf or larger low ESR capacitor. The two IN pins on the
SO-8 package must be directly connected on the printed
circuit board to prevent voltage drops between the two
inputs. When used as a SCSI active termination, IN connects to term power. When used as a supply splitter, IN is
also the positive supply output.
GND: Ground Pin. The three GND pins on the SO-8
package are internally connected, but lowest load regulation errors will result if these pins are tightly connected on
the printed circuit board. This will also aid heat dissipation
at high power levels.

4-66

EN: TTUCMOS Logic Input. A high level allows normal
operation. Alow level reduces supply current to zero. This
pin is internally connected to VIN on 3-lead ST packaged
devices.
OUT: Regulated Output Voltage. Output can source or sink
current. Current limit for sourcing and sinking current is
provided to protect the device from fault conditons. The
output must have a low ESR output filter capacitor. COUT
:?: 0.22Jlf to guarantee stability. A0.1 Jlf ceramic capacitor
may be needed if the ESR of the main COUT:?: 0.22Jlf is too
high.

LTll18-2.5
LTll18-2.85/LTll18-5
'YPICAL APPLICATions
SCSI Active Terminator

.....I-'\,...._ _ _....:T.:;.ER;;;;M;...:.PW;;.;.

e1

Power Supply Splitter
~~---.--.-------------5V

-

-..._~:~\llr-127 LINES

ANALOG
.......- - - COMMON

2.5V

: 110n

__ 5V

T

of

1!lF

-wv-

IELATED PAATS
IRTNUMBER
'1005

Logic Controlled Regulator

DESCRIPTION

COMMENTS
5V, 1A Main Output Plus 35mA Auxilliary Output

'1117

800mA Low Dropout Regulator

Fixed 2.85V, 3.3V, 5V or Adjustable Outputs

'1120A

Micropower Regulator with Comparator and Shutdown

201JA Supply Current, 2.5V Reference Output

'1121

Micropower Low Dropout Regulator with Shutdown

Reverse Voltage and Reverse Current Protection

4-67

~7~J!1mG~~~----50-0-m-A-N-e-g-~-~-i~-!

Low Dropout Micropower
Regulator

FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•

The LT®1175 is a negative micropower low dropout regulator.ltfeatures 45~ quiescent current, dropping to 1O~
in shutdown. A new reference amplifier topology gives
precision DC characteristics along with the ability to
maintain good loop stability with an extremely wide range
of output capacitors. Very low dropout voltage and high
efficiency are obtained with aunique power transistor antisaturation design. Adjustable and fixed 5V versions are
available.

Stable with Wide Range of Output Capacitors
Operating Current: 45~
Shutdown Current: 1O~
Adjustable Current Limit
Positive or Negative Shutdown Logic
Low Voltage Linear Dropout Characteristics
Fixed 5V and Adjustable Versions
Tolerates Reverse Output Voltage

APPLICATions
•
•
•
•
•
•

Analog Systems
Modems
Instrumentation
AID and D/A Converters
Interface Drivers
Battery-Powered Systems

LT, LTC and LT are registered trademarks of Linear Technology Corporation.

Several new features make the LT1175 very user-friendly.
The shutdown pin can interface directly to either positive
or negative logic levels. Current limit is user-selectable at
200mA, 400mA, 600mA and 800mA. The output can be
forced to reverse voltage without damage or latch-up.
Unlike some earlier designs, the increase in quiescent
current during a dropout condition is actively limited.
The LT1175 has complete blowout protection with current
limiting, power limiting, and thermal shutdown. Special
attention was given to the problem of high temperature
operation with micropower operating currents, preventing
output voltage rise under no-load conditions. The LT1175
is available in 8-pin CERDIP, plastic DIP and SO packages,
as well as 5-pin surface mount DO and through-hole TO220 packages. The 8-pin SO package is specially constructed for low thermal resistance.

TYPICAL APPLICATion

Minimum Input-Io-Output Voltage

Typical LT1175 Connection

1.0

~

TJ = 25°C
IUM2. IUM4 TO VIN

08

~

§; 0.6
f::J
0..
f::J

~

0.4

..........

::J

~

'CIN IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM
INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION
SECTION FOR DETAILS

4-68

0.2

o

.......... V

.......... ' /

V~

o

0.1

0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)

0.6

0.7

LTl175
IBSOLUTE mAXimum RATinGS
IPUt Voltage (Transient 1 sec, Note 10) ................ 25V
IPUt Voltage (Continuous) ..................................... 20V
IPUt-to-Output Differential Voltage ........................ 20V
VSense Pin (with Respect to GND Pin) ........ 2V, -1 OV
DJ Sense Pin
(with Respect to Output Pin) ................... 20V, -0.5V
VSense Pin
(with Respect to Output Pin) ..................... 20V, - 7V
utput Reverse Voltage.... ................ .......... .............. 2V
HDN Pin to GND Pin Voltage ...................... 15V, -20V

SHDN Pin to VIN Pin Voltage .......................... 30V, -5V
Operating Junction Temperature Range
LT1175C .............................................. O°C to 125°C
LT1175M ........................................ -55°C to 150°C
Ambient Operating Temperature Range
LT1175C ................................................ O°C to 70°C
LT1175M ........................................ -55°C to 125°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

'ACKAGEIORDER InFORmATiOn
TOP VIEW

'·0'"

IUM2 2
OUTPUT 3
SENSE 4

7 IUM4
6 SHDN
5 GND

J8 PACKAGE
B-LEAD CERDIP
N8 PACKAGE
8-LEAD PDIP

ORDER
PART NUMBER
LT1175CN8
LT1175CN8-5
LT1175MJ8

=90·CIWTO 120·C/w (J8)
=BO·CIW TO 120·C/w DEPENDING
ON PC BOARD LAYOUT (NB)

BJA
BJA

FRONT VIEW
TAB
IS
INPUT

[I'""'

4
GND
3
INPUT
2
SENSE
1
OUTPUT
Q PACKAGE
5-LEAD PLASTIC DO
9JA =27·CIW TO 60·C/w DEPENDING
ON PC MOUNTING. SEE APPLICATIONS
INFORMATION FOR DETAILS

TOP VIEW

'·0'"

IUM2 2 .
OUTPUT 3
SENSE 4

LT1175CQ
LT1175CQ-5

7 IUM4
6 SHDN
5 GND

LT1175CS8
LT1175CS8-5

S8 PACKAGE
B-LEAD PLASTIC SO
BJA =120·CIW TO 170·C/w DEPENDING
ON PC BOARD LAYOUT.
PINS 1. 8ARE INTERNALLY CONNECTED TO DIE ATTACH
PADDLE FOR HEAT SINKING. ELECTRICAL CONTACT CAN BE
MADE TO EITHER PIN. FOR BEST THERMAL RESISTANCE,
PINS 1, BSHOULD BE CONNECTED TO AN EXPANDED LAND
THAT IS OVER AN INTERNAL OR BACKSIDE PLANE. SEE
APPLICATIONS INFORMATION
FRONT VIEW
5

ORDER
PART NUMBER

0

ORDER
PART NUMBER

1175
11755
ORDER
PART NUMBER

SHDN
GND
INPUT
SENSE
OUTPUT

4

0

S8 PART MARKING

3

2
1

LT1175CT
LT1175CT-5

TAB IS
INPUT

TPACKAGE
5-lEAD PLASTIC TO-220
BJA =50·CIW, BJC =5·CIW

Insult factory for Industrial grade parts.

LEaRICAL CHARACTERISTICS
IUT = 5V; VIN = 7V, lOUT = 0, VSHDN = 3V, IUM2 and IUM4tied to VIN, TJ = 25°C, unless otherwise noted. To avoid confusion with
nin" and "max" as applied to negative voltages, all voltages are shown as absolute values except where polarity is not obvious.
IRAMETER

edback Sense Voltage
Itput Voltage Initial Accuracy
Itput Voltage Accuracy (All Conditions)

L7lJ!J~

CONDITIONS
Adjustable Part
Fixed 5V Part
Adjustable, Measured at 3.8V Sense
Fixed 5V
VIN - VOUT =1V to VIN =25V, lOUT =OA to 500mA
P=0to PMAX , TJ =TMIN to TMAX (Note 2)

MIN
3.743
4,93

•

TYP

MAX

3.8
5.0
0.5
0.5
1.5

3.857
5.075
1.5
1.5
2.5

UNITS
V
V
%
%
%

4-69

•

LTl175

ElEORICAl CHARACTERISTICS

VOUT =5V; VIN =7V, lOUT =0, VSHON =3V, ILlM2 and ILlM4 tied to VIN, TJ =25°&, unless otherwise noted. To avoid confusion with
"min" and "max" as applied to negative voltages, all voltages are shown as absolute values except where polarity is not obvious.
PARAMETER

CONDITIONS

Quiescent Input Supply Current

VIN - VOUTUp to 12V

GND Pin Current Increase with Load (Note 3)
Input Supply Current in Shutdown

VSHDN = OV

Shutdown Thresholds (Note 8)
Shutdown Pin Current (Note 1)
Output Bleed Current in Shutdown (Note 5)
Sense Pin Input Current
Dropout Voltage (Note 6)

Current Limit (Note 10)

Line Regulation (Note 9)
Load Regulation (Note 4. 9)
Thermal Regulation
Output Voltage Temperature Drift

(Adjustable Part Only. Current Flows Out of Pin)
(Fixed Voltage Only. Current Flows Out of Pin)
lOUT = 25mA
lOUT = 100mA
lOUT = 500mA
IUM2 Open. lOUT = 300mA
IUM4 Open. lOUT = 200mA
IUM2. IUM4 Open. lOUT = 100mA
VIN - VOUT = lV to 12V
IUM2 Open
IUM4 Open
IUM2. IUM4 Open
VIN - VOUT = lV to VIN = 25V
lOUT = 0 to 500mA
5-Pin Packages
P= 0 to PMAX (Notes 2. 7)
8-Pin Packages
TJ = 25°C to TJMIN. or 25°C to TJMAX

•
•
•

10
10
0.8

•
•
•

••
••
•
•
•
••
•
•
•

TYP
45

•
•

Either Polarity on Shutdown Pin
VSHDN = OV to 10V (Flows Into Pin)
VSHDN =-15Vto OV (Flows Into Pin)
VOUT = OV. VIN = 15V

The. denotes specifications which apply over the operating temperature
range.
Note 1: Shutdown pin maximum positive voltage is 30V with respect to
-VIN and 15V with respect to GND. Maximum negative voltage is -20V
with respect to ground and -5V with respect to -VIN.
Note 2: PMAX = 1.5W for 8-pin packages. and 6W for 5-pin packages. This
power level holds only for input-to-output voltages up to 12V. beyond
which internal power limiting may reduce power. See Guaranteed Current
Limit curve in Typical Performance Characteristics section. Note that all
conditions must be met.
Note 3: Ground pin current increases because of power transistor base
drive. At low input-to-output voltages « 1V) where the power transistor is
in saturation. Ground pin current will be slightly higher. See Typical
Performance Characteristics.
Note 4: With ILOAD = O. at TJ > 125°C. power transistor leakage could
increase higher than the 1O~ to 25~ drawn by the output divider or fixed
voltage Sense pin. causing the output to rise above the regulated value. To
prevent this condition. an internal active pull-up will automatically turn on.
but supply current will increase.
Note 5: This is the current required to pull the output voltage to within 1V
of ground during shutdown.

4-70

MIN

520
390
260
130

4
1
0.1
1
75
12
0.1
0.18
0.5
0.33
0.3
0.26
800
600
400
200
0.003
0.1
0.04
0.1
0.25

MAX
65
80
20
20
25
2.5
8
4
1
5
150
20
0.2
0.26
0.7
0.5
0.45
0.4

0.015
0.25
0.1
0.2
1.25

UNITS

W
W
~mJ

W
W
\

W
W
W
W
nJ

W
\
\
\
\
\
\
mJ
mJ
mJ
mJ

%/\
o/c

'ioN.
%/'11
o/c

Note 6: Dropout voltage is measured by setting the input voltage equal to
the normal regulated output voltage and measuring the difference between
VIN and VOUT. For currents between 100mA and 500mA. with both IUM
pins tied to VIN. maximum dropout can be calculated from
VOO = 0.15 + un (loUT).
Note 7: Thermal regulation is a change in the output voltage caused by die
temperature gradients. so it is proportional to chip power dissipation.
Temperature gradients reach final value in less than lOOms. Output
voltage changes after lOOms are due to absolute die temperature changes
and reference voltage temperature coefficient.
Note 8: The lower limit of 0.8V is guaranteed to keep the regulator in
shutdown. The upper limit of 2.5V is guaranteed to keep the regulator
active. Either polarity may be used. referenced to Ground pin.
Note 9: Load and line regulation are measured on a pulse basis with pulse
width of 20ms or less to keep chip temperature constant. DC regulation
will be affected by thermal regulation (Note 7) and chip temperature
changes. Load regulation specification also holds for currents up to the
specified current limit when IUM2 or IUM4 are left open.
Note 10: Current limit is reduced for input-to-output voltage above 12V.
See the graph in Typical Performance Characteristics for guaranteed limits
above 12V.

LTl175
rYPICAL PERFORmAnCE CHARAOERISTICS
Typical Current Limit
Characteristics
1.0

CURRENT LIMIT CHANGES ONLY SLIGHTLY
WITH TEMPERATURE SO CURVES ARE
REPRESENTATIVE OF ALL TEMPERATURES

O.S

Output Voltage Temperature Drift

Guaranteed Current Limit
0.6 ,...--,----,----,--,----,

>-

'":::>

<.:>

~

0L-__L-__L -_ _

~_J-_~

~

__

~

__

3.S0

~

o

15
10
20
25
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)

o
10
15
20
25
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)

Minimum Input-to-Output Voltage

Minimum Input-to-Output Voltage

1.0 ,----,-,--,--,--,--,----,
TJ = 25"C
VIN REDUCED

~~~i~g~TPUT-+---t--+--+---1

O.S

§; 0.6 1----+-+-1----+-+,-£1----1
!:;
c.
!:;
o

~

0.4

f---+-+----:Y"'-t--;;;;..t:;::1.""'f----l

FEEDBACK VOLTAGE
ADJUSTABLE PART

f-"""

r~~

r-

3.76
-50 -25
25 50
75 100
JUNCTION TEMPERATURE ("C)

125

Sense Bias Current
(Adjustable Part)

1.0 . - - , - , - - , - - - , - , - - , - - - ,
VIN REDUCED UNTIL OUTPUT
VOLTAGE DROPS 1%.
~ O.S IUM2, IUM4 TIED TO VIN

'"~

DROPS 1%
0.6 1--+-+----,1--+

~

§; 3.S4
0.2 I---+---+---~:-'rl....::--I

----

-r--

~

0.1 1--+---+----"'1""""=---'''I--=:--I
__

V

~4.95

~ 0.3

1t--+---+--IT~"-

il5

'"'":::>

<.:>

:::>

~ 0.2 1-7"f'-:z~'-

40

20
__-L~
0
25 50
75 100 125
TEMPERATURE ("C)

OL--L_L-~_~~

0.1

0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)

0.6

0.7

0.1

Shutdown Input Current

0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)

0.6

-50 -25

0.7

Shutdown Pin Characteristics

Shutdown Thresholds

25

2.5

20

15

2.0

~

9

15
TJ 125"C
10

~

J'

o
o

~

TJ = 25"C
LI

10
;;(

.;;

1.5

>-

il5

0

'"'":::>
<.:>

:I:

ffl

'">-

:I:

TJ = WC

1.0

z

0::

0.5
DEVICE IS OFF
BELOW THRESHOLD
OL--L__L--L__L--L__L---"

10
15
INPUT VOLTAGE (V)

LllJ!J~

20

25

-50 -25

0
25 50
75
TEMPERATURE ("C)

100

125

VIN = 25V
CHARACTERISTICS DO NOT
CHANGE SIGNIFICANTLY WITH
TEMPERATURE, SO A SINGLE
CURVE IS SHOWN. POSITIVE

g~rpi~ FiOWj INJr
~ ~HD~

I

N~GA~IVE

IF
PIN1IS
WITH
RESPECTTO INPUT VOLTAGE AND
-5 - - INPUT VOLTAGE IS LESS THAN 15V, NEGATIVE BREAKOVER POINT WILL
BE ABOUT SV BELOW -VIN
-10
-25 -20 -15 -10 -5 0 5 10 15 20 25
SHUTDOWN TO GROUND VOLTAGE (V)

4-71

LTl175
TYPICAL PERFORmAnCE CHARAOERISTICS
Ripple Rejection

Ground Pin Current
100

VOUT~'12V

80
..("'_OU_T_-_3._BV-,-) (S·Imp Ie formu Ia)
R2 -_ _
3.BV
R2 __
R1->-(_VO_UT_-_3-,.-,BV.2-) (Taking Sense pin bias)
- 3.BV + R1(IFB)
current into account
IDiv = Desired divider current

[TlJlJ~

Figure 1. Typical L11175 Adjustable Connection

Setting Current Limit
The LT1175 uses two ILiM pins to set current limit (typical)
at 200mA, 400mA, 600mA or BOO rnA. The corresponding
minimum guaranteed currents are 130mA, 260mA, 390mA
and 520mA. This allows the user to select a current limit
tailored to his specific application and prevents the situation where short-circuit current is many times higher than
full-load current. Problems with input supply overload or
excessive power dissipation in a faulted load are prevented. Power limiting in the form offoldback current limit
is built-in and reduces current limit as afunction of inputto-output voltage differential for differentials exceeding
14V. See the graph in Typical Performance Characteristics.
The LT1175 is guaranteed to be blowout-proof regardless
of current limit setting. The power limiting combined with
thermal shutdown protects the device from destructive
junction temperatures under all load conditions.
Shutdown
In shutdown, the LT1175 draws only about 10/lA. Special
Circuitry is used to minimize increases in shutdown current at high temperatures, but a slight increase is seen
above 125°C. One option not taken was to actively pull
down on the output during shutdown. This means that the
output will fall slowly after shutdown is initiated, at a rate
determined by load current plus the 12/lA internal load,
and the size of the output capacitor. Active pull-down is

4-73

LTl175
APPLICATions InFoRmATion
normally agood thing when the regulator is used by itself,
but it prevents the user from shutting down the regulator
when a second power source is connected to the LT1175
output. If active output pull-down is needed in shutdown,
it can be added externally with a depletion mode PFET as
shown in Figure 2. Note that the maximum pinch-off
voltage of the PFET must be less than the positive logic
high level to ensure that the device is completely off when
the regulator is active. The Motorola J177 device has
300n on resistance for zero gate source voltage.
3VT05V

• MOTOROLA J177
PINCH-OFF VOLTAGE MUST BE LESS THAN
POSITIVE LOGIC HIGH VOLTAGE

"'SF"

Figure 2. Active Output Pull-Down During Shutdown

Minimum Dropout Voltage
Dropoutvoltage is the minimum voltage required between
input and output to maintain proper output regulation. For
older three-terminal regulator deSigns, dropout voltage
was typically 1.5V to 3V. The LT1175 uses a saturating
power transistor design which gives much lower dropout
voltage, typically 1OOmV at light loads and 450mV at full
load. Special precautions were taken to ensure that this
technique does not cause quiescent supply current to be
high under light load conditions. When the regulator input
voltage is too low to maintain a regulated output, the pass
transistor is driven hard by the error amplifier as it tries to
maintain regulation. The current drawn by the driver
transistor could be tens of milliamperes even with little or
no load on the output. This indeed was the case for older
IC designs that did not actively limit driver current when
the power transistor saturated. The LT1175 uses a new
anti-saturation technique that prevents high driver cur-

4-74

rent, yet allows the power transistor to approach it:
theoretical saturation limit.

Output Capacitor
Several new regulator design techniques are used to makl
the LT1175 extremely tolerant of output capacitor selec
tion. Like most low dropout designs which use acollecto
or drain of the power transistor to drive the output node
the LT1175 uses the output capacitor as part of the overal
loop compensation. Older regulators generally requirel
the output capacitor to have a minimum value of 1J,1f tl
100J,lf, a maximum ESR (Effective Series ReSistance) 0
0.1 Qto 1nand aminimum ESR in the range of 0.03QtI
0.3n. These restrictions usually could be met only witl
good quality solid tantalum capacitors. Aluminum capaci
tors have problems with high ESR unless much highe
values of capacitance are used (physically large). The ESI
of ceramic or film capacitors was too low, which made thl
capacitance/ESR zero frequency too high to maintail
phase margin in the regulator. Even with optimum capaci
tors, loop phase margin was very low in previous design:
when output current was low. These problems led to ane~
design technique forthe LT1175 error amplifier and inter
nal frequency compensation as shown in Figure 3.
A conventional regulator loop consists of error amplifie
A1, driver transistor 02 and power transistor 01. Added tl
this basic loop are secondary loops generated by 03 ani
CF. A DC negative feedback current fed into the erro
amplifier through 03 and RN causes overall loop curren
gain to be very low at light load currents. This is not,
problem because very little gain is needed at light loads. II
addition to low gain, the parasitic pole frequency at 0:
base is extended by the DC feedback. The combination 0
these two effects dramatically improves loop phase mar
gin at light loads and makes the loop tolerant of large ESI
in the output capacitor. With heavy loads; loop phase ani
gain are not nearly as troublesome and large negativ
feedback could degrade regulation. The logarithmiC behav
ior of the base emitter voltage of 01 reduces 03 negativ
feedback at heavy loads to prevent poor regulation.
In a conventional design, even with the nonlinear feed
back, poor loop phase margin would occur at medium tl
heavy loads if the ESR of the output capacitor fell belm

LTl175
APPLICATions InFoRmATion

----I
COUT :
ESR

•

:

•

___ .J

1----4---~t--

OUTPUT

III
CURRENT LIMIT
SENSE RESISTOR

1175FD:!

Figure 3.

D.3Q. This condition can occur with ceramic or film
capacitors which often have an ESR under 0.1 Q. With
previous designs, the user was forced to add areal resistor
in series with the capacitor to guarantee loop stability. The
LT1175 uses a unique AC feedforward technique to eliminate this problem. CF is a conventional feedforward capacitor often used in regulators to cancel the pole formed
lJy the output capacitor. It would normally be connected
from the regulated output node to the feedback node atthe
R1/R2 junction or to an internal node on the amplifier as
shown. In this case, however, the capacitor is connected
to the internal structure of the power transistor. Rc is the
unavoidable parasitic collector resistance of the power
transistor. Access to the node at the bottom of Rc is
~vailable only in monolithic structures where Kelvin con1ections can be made to the NPN buried collector layer.
rhe loop now responds as if Rc were in series with the

.L7lJ!J~

output capacitor and good loop stability is achieved even
with extremely low ESR in the output capacitor.
The end result of all this attention to loop stability is that
the output capacitor used with the LT1175 can range in
value from 0.1 Wto hundreds of microfarads, with an ESR
from OQ to 10Q. This range allows the use of ceramic,
solid tantalum, aluminum and film capacitors over awide
range of values.
The optimum output capacitor type for the LT1175 is still
solid tantalum, but there is considerable leeway in selecting the exact unit. If large load current transients are
expected, larger capacitors with lower ESR may be needed
to control worst case output variation during transients. If
transients are not an issue, the capacitor can be chosen for
small physical size, low price, etc. Concerns about surge
currents in tantalum capacitors are not an issue for the

4-75

LT1l75
APPLICATions InFoRmATion
output capacitor because the LT1175 limits inrush current
to well below the level which can cause capacitor damage.
Surges caused by shorting the regulator output are also
not a problem because tantalum capacitors do not fail
during a "shorting out" surge, only during a "charge up"
surge.
The output capacitor should be located within several
inches of the regulator. If remote sensing is used, the
output capacitor can be located at the remote sense node,
but the ground pin of the regulator should also be connected to the remote site. The basic rule is to keep Sense
and Ground pins close to the output capacitor, regardless
of where it is.
Input Capacitor
The LT1175 requires a separate input bypass capacitor
only if the regulator is located more than six inches from
the raw supply output capacitor. A 1~ or larger tantalum
capacitor is suggested for all applications, but if low ESR
capacitors such as ceramic or film are used for the output
andinput capacitors, the input capacitor should be at least
three times the value of the output capacitor. If a solid
tantalum or aluminum electrolytic output capacitor is
used, the input capacitor is very noncritical.
High Temperature Operation
The LT1175 is a micropower design with only 45~
quiescent current. This could make it perform poorly at
high temperatures (> 125°C), where power transistor leakage might exceed the output node loading current (5~ to
15~). To avoid acondition where the output voltage drifts
uncontrolled high during a high temperature no-load
condition, the LT1175 has an active load which turns on
when the output is pulled above the nominal regulated
voltage. This load absorbs power transistor leakage and
maintains good regulation. There is one downside to this
feature, however. If the output is pulled high deliberately,
as it might be when the LT1175 is used as a backup to a
slightly higheroutputfrom aprimary regulator, the LT1175
will act as an unwanted load on the primary regulator.
Because ofthis, the active pull"down is deliberately "weak."
It can be modeled as a2k resistor in series with an internal
clamp voltage when the regulator output is being pulled

4-76

high. If a4.aVoutput is pulled to 5V, for instance, the load
on the primary regulator would be (5V - 4.aV)/2kQ =
1OO~. This also means that if the internal pass transistor
leaks 50~, the output voltage will be (50~)(2kQ) =
100mV high. This condition will not occur under normal
operating conditions, but could occur immediately after
an output short circuit had overheated the chip.
Thermal Considerations
The LT1175 is available in a special a-pin surface mount
package which has pins 1and aconnected to the die attach
paddle. This reduces thermal resistance when pins 1 and
a are connected to expanded copper lands on the PC
board. Table 2 shows thermal resistance for various
combinations of copper lands and backside or internal
planes. Table 2also shows thermal resistanceforthe 5-pin
DD surface mount package and the a-pin DIP and CERDIP
packages.
Table 2. Package Thermal Resistance (OC/W)
DIP

CERDIP

SO

Q

140

120

170

60

Minimum with
Backplane

110

100

150

50

1cm 2 Top Plane
with Backplane

100

90

135

35

10cm 2 Top Plane
with Backplane

80

90

120

27

LAND AREA
Minimum

To calculate die temperature, maximum power dissipation
or maximum input voltage, use the following formulas
with correctthermal resistance numbers from Table 2. For
through-hole TO-220 applications use 8JA = 50°C/W
without a heat sink and 8JA =5°C/W + heat sink thermal
resistance when using a heat sink.
Die Temp = TA + 8JA (VIN - VOUT )(1 LOAD)

·
Power D····
TMAX - TA
MaXlmum
Isslpatlon = --""'-'''---'-'8JA
Maximum Input Voltage
TMAX - TA \I
=
for Thermal Considerations
8JA(ILOAD) + VOUT

.L7lJD~

LTl175
~PPLICATlons

InFORmATion

rA = Maximum ambient temperature
rMAX = Maximum LT1175 die temperature (125°C for
commercial and industrial, 150°C for military)
IJA

= LT1175 thermal resistance, junction to ambient

fiN

= Maximum continuous input voltage at maximum
load current

LOAD = Maximum load current
:xample: LT1175SS with ILOAD = 200mA, VOUT =5V,
fiN = 7V, TA= 60°C. Maximum die temperature for the
.T1175SS is 125°C. Thermal resistance from Table 2 is
ound to be SO°C/W.
Die Temperature =60 + SO (0.2A)(S - 5) =10SoC
Maximum Power Dissipation = 125 - 60 = 0.S1W
·
C'
SO
MaXlmum
ontmuous
125 - 60
Input Voltage
=
+ 5 = 9V
(for Thermal Considerations)
SO(0.2)

NPN power transistor structure that has aparasitic diode
between the input and output of the regulator. Reverse
voltages between input and output above 1Vwill damage
the regulator if large currents are allowed to flow. Simply
disconnecting the inputsource with the output held up will
not cause damage even though the input-to-output voltage will become slightly reversed.
High Frequency Ripple Rejection

The LT1175 will sometimes be powered from switching
regulators that generate the unregulated or Quasi-regulated input voltage. This voltage will contain high freQuency ripple that must be rejected by the linear regulator.
Special care was taken with the LT1175 to maximize high
frequency ripple rejection, but as with any micropower
deSign, rejection is strongly affected by ripple frequency.
The graph in the Typical Performance Characteristics
section shows 60dB rejection at 1kHz, but only 15dB •
rejection at 1OOkHzforthe 5V part. Photographs in Figures
4a and 4b show actual output ripple waveforms with
square wave and tri-wave input ripple.

lutput Voltage Reversal

'he LT1175 is designed to tolerate an output voltage
eversal of up to 2V. Reversal might occur, for instance, if
he output was shorted to apositive 5V supply. This would
.lmostsurely destroy IC devices connected to the negative
IUtpUt. Reversal could also occur during start-up if the
lositive supply came up first and loads were connected
letween the positive and negative supplies. For these
easons, it is always good design practice to add a reverse
'iased diode from each regulator output to ground to limit
,utput voltage reversal. The diode should be rated to
landle full negative load currentfor start-up situations, or
he short-circuit current ofthe positive supply ifsupply-toupply shorts must be tolerated.
~put

GOUT = 4.7¢' TANT

OUTPUT
20mVlDlV

Gour=I¢,TANT

INPUT
RIPPLE
100mV/DIV

f = 50kHz

5~OIV

Figure 4a.

GOUT = 4.7¢' TANT

OUTPUT
100mVlOIV

GOUT = I¢' TANT

Voltage Lower Than Output

.inear Technology's positive low dropout regulators
T1121 and LT1129, will not draw large currents if the
lPUt voltage is less than the output. These devices use a
Iteral PN Ppower transistor structure that has 40V emitter
ase breakdown voltage. The LT11l5, however, uses an

L7lJ!J~

INPUT
RIPPLE
100mVlOIV

f = 100kHz

2~IV

1\75f04

Figure 4b.

4-77

LTl175
APPLICATions InFoRmATion
To estimate regulator output ripple under different conditions, the following general comments should be helpful:
1. Output ripple at high frequency isonly weakly affected
by load current or output capacitor size for medium to
heavy loads. At very light loads (dOmA), higher frequency ripple may be reduced by using larger output
capacitors.
2. A feedforward capacitor across the resistor divider
used with the adjustable part is effective in reducing
ripple onlyforoutputvoltages greater than 5Vandonly
for frequencies less than 100kHz.
3. Input-to-output voltage differential has little effect on
ripple rejection until the regulator actually enters a
dropout condition of 0.2V to 0.6V.
If ripple rejection needs to be improved, an input filter can
be added. This filter can be a simple RC filter using a 10
to 100 resistor. A 3.30 resistor for instance, combined
with a 0.30 ESR solid tantalum capacitor, will give an
additional 20dB ripple rejection. The size of the resistor
will be dictated by maximum load current. Ifthe maximum
voltage drop allowable across the resistor is "VR," and
maximum load current is ILOAD, R = VRiILOAD. At light
loads, larger resistors and smaller capacitors can be used

RELATED PARTS
LT1121

150mA Positive Micropower Low Dropout
Regulator with Shutdown

LT1129

700mA Positive Micropower Low Dropout
Regulator with Shutdown

LT1185

3A Negative Low Dropout Regulator

LT1521

300mA Positive Micropower Low Dropout
Regulator with Shutdown

LT1529

3A Positive Micropower Low Dropout
Regulator with Shutdown

4-78

to save space. At heavier loads an inductor may have to be
used in place of the resistor. The value of the inductor can
be calculated from:
L

_

ESR

FIL - 21r(f)(10 rr 120)

ESR = Effective series resistance of filter capacitor. This
assumes that the capacitive reactance is small
compared to ESR, a reasonable assumption for
solid tantalum capacitors above 2.2!1f and 50kHz.

= Ripple frequency
rr = Ripple rejection ratio of filter in dB
Example: ESR = 1.20, f = 100kHz, rr = - 25dB.
LFIL =

1.2

6.3(10'5 )(10-25/2°)

=

34.uH

Solid tantalum capacitors are suggested for the filter to
keep filter Qfairly low. This prevents unwanted ringing at
the resonant frequency of the filter and oscillation problems with the filteriregulator combination.

f=AD
L1n
£.7 TECHN

LT1521/LT1521-3
~O'O"-G~v~--------l_Jl_m_l~_._3/_LT_15_~_~
300mA Low Dropout
Regulators with Micropower
Quiescent Current and Shutdown
~

:EATURES
I
I
I

I
I
I
I
I
I

I
I
I

DESCRIPTiOn

Dropout Voltage: O.5V
Output Current: 300mA
Quiescent Current: 12J.lA
No Protection Diodes Needed
Adjustable Output from 3.8V to 20V
Fixed Output Voltages: 3V, 3.3V, 5V
Controlled Quiescent Current in Dropout
Shutdown 10 =61JA
51JA Quiescent Current in Shutdown
Reverse Battery Protection
No Reverse Current
Thermal Limiting

IPPLICATlons
I
I
I

IT

Low Current Regulator
Regulator for Battery-Powered Systems
Post Regulator for Switching Supplies

The LT®1521/LT1521-3/LT1521-3.3/LT1521-5 are low
dropout regulators with micropower quiescent current
and shutdown. These devices are capable of supplying
300mA of output current with a dropout voltage of O.5V.
Designed for use in battery-powered systems, the low
quiescent current, 12~ operating and 6~ in
shutdown, makes them an ideal choice. The quiescent
current is well controlled; it does not rise in dropout as it
does with many other low dropout PNP regulators.
Other features of the LT1521 /LT1521-3/LT1521-3.3/
LT1521-5 include the ability to operate with very small
output capacitors. They are stable with only 1.5W on the
output while most older devices require between 1Ow and
1OOW for stability. Small ceramic capacitors can be used,
enhancing manufacturability. Also, the input may be connected to voltages lower than the output voltage, including
negative voltages, without reverse current flow from outputto input. This makes the LT1521 series ideal for backup
power situations where the output is held high and the
input is low or reversed. Under these conditions only 5~
will flow from the output pin to ground.
D, LTC and LT are registered trademarks of Linear Technology Corporation.

rYPICAL APPLICATiOn
5V Battery-Powered Supply with Shutdown

Dropout Voltage
0.6
0.5

;/'"

~
~

..:

0.4

~

;/'"

~ 0.3

>-

::>

/"

o

~ 0.2
VSHDN (PIN 5) OUTPUT
<0.25
OFF
>2.80
ON
NC
ON

'"

0.1

o

V

V

V

/
o

50

100
150
200
250
OUTPUT CURRENT (mA)

300

LT152i·TAQ2

L7lJ!J~

4-79

LT1521 /LT1521-3
LT1521-3.3/LT1521-5
ABSOLUTE mAxmum RATinGS
Input Voltage ...................................................... ±20V*
Output Pin Reverse Current .................................. 10mA
Adjust Pin Current ................................................ 10mA
Shutdown Pin Input Voltage (Note 1) .......... 6.5V, -O.6V
Shutdown Pin Input Current (Note 1) ..................... 5mA
Output Short-Circuit Duration .......................... Indefinite

Storage Temperature Range ................. -65°C to 150°C
Operating Junction Temperature Range (Note 2)
Commercial ........................................... O°C to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
'For applications requiring input voltage ratings greater than 20V, contact
the factory.

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

MO'"

LT1521CS8
LT1521 CS8-3
LT1521 CS8-3.3
LT1521 CS8-5

S8 PACKAGE
HEAD PLASTIC SO

S8 PART MARKING

"PIN 2=SENSE FOR LT1521-3/LT152H.3ILT1521-5
=ADJFOR LT1521

1521
15213
152133
15215

TOP VIEW

SENSE/ADJ" 2
GND 3
NC 4

7 GNO
6 GND
5 SHDN

TJMAX =125·C. 9JA =70·C/W
SEE THE APPLICATIONS INFORMATION SECTION

ORDER PART
NUMBER

Gom
FRONT VIEW

TAB IS
GND

LT1521 CST-3
LT1521 CST-3.3
LT1521CST-5

2 GND

3 IN
ST PACKAGE
HEAD PLASTIC SOT-223

ST PART MARKING
15213
152133
15215

TJMAX =125·C, 9JA =5O"C/W
SEE THE APPLICATIONS INFORMATION SECTION

Consult factory for Industrial and Military grade parts,

ELECTRICAL CHARAOERISTICS
PARAMETER
Regulated Output Voltage
(Note 3)

CONDITIONS
L11521-3
LT1521-3.3
L11521-5
L11521 (Note 4)

Line Regulation

Load Regulation

4-80

L11521-3
LT1521-3.3
LT1521-5
L11521 (Note 4)
L11521-3
LT1521-3.3
LT1521-5
L11521 (Note 4)

VIN = 3,5V, lOUT = 1rnA, TJ = 25°C
4V < VIN < 20V, 1rnA < lOUT < 300rnA
VIN = 3.8V, lOUT = 1rnA, TJ = 25°C
4.3V < VIN < 20V, 1rnA < lOUT < 300rnA
VIN = 5.5V, lOUT = 1rnA, TJ = 25°C
6V < VIN < 20V, 1rnA < lOUT < 300rnA
VIN = 4.3V, lOUT = 1rnA, TJ = 25°C
4.8V < VIN < 20V, 1rnA  110°C and lOUT < 1mA, output voltage
ay increase by 1%.
lie 3: Operating conditions are limited by maximum junction
mperature. The regulated output voltage specification will not apply for
possible combinations of input voltage and output current. When
lerating at maximum input voltage, the output current range must be
nited. When operating at maximum output current, the input voltage
nge must be limited.

L7lJ!J~

MIN

•

290

•
•
•
•
•
•
•
•
•
•
•
••
•
•
•
•

TYP
130

350
400
500

50

12
65
300
0.8
1.4
2.2
6.5
50
1.20
0.75
2.0
6
58

320

400
400

0.25

5
5
5
5

MAX
170
250
350
450
420
550
470
600
600
750
20
100
450
1.5
2.5
4.0
12.0
100
2.80
5.0
12

UNITS
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV

IJA
IJA
IJA
mA
mA
mA
mA
nA
V
V

IJA
IJA
dB

800
1.0
10
10
10
10

mA
mA
mA

IJA
IJA
IJA
IJA

Note 4: The LT1521 (adjustable version) is tested and specified with the
adjust pin connected to the output pin.
Nole 5: Dropout voltage is the minimum inpuVoutput voltage required to
maintain regulation at the specified output current. In dropout the output
voltage will be equal to: (VIN - VDROPOUT)
Nole 6: Ground pin current is tested with VIN = VOUT (nominal) and a
current source load. This means the device is tested while operating in its
dropout region. This is the worst-case ground pin current. The ground pin
current will decrease slightly at higher input voltages.
Note 7: Adjust pin bias current flows into the adjust pin.
Note 8: Shutdown pin current at VSHDN = OV flows out of the shutdown
pin.
Nole 9: Quiescent current in shutdown is equal to the total sum of the
shutdown pin current (21JA) and the ground pin current (41JA).
Nole 10: Reverse output current is tested with the input pin grounded and
the output pin forced to the rated output voltage. This current flows into
the output pin and out of the ground pin.

4-81

LT1 521/LT1 521-3
LT1521-3.3/LT1521-5
TYPICAL PERFORmAnCE CHARAaERISTICS
Guaranteed Dropout Voltage

Dropout Voltage

o = TEST POINTS
0.7

12~oC

V
./'"

IT ,;
?!: 0.6 -J~
w
./
OJ
0.5
~
K,;25°C
0
> 0.4

V

/./

f-

::::>

0

"-

0.3

a::
c

0.2

0

Quiescent Current

0.8

0.8

15.0

/

-

1"/ ;P

w

OJ

~ 10.0

0.5

>

0.4

'-' 7.5

0.3

i'l'i

a:
a::

::::>

f-

f-

::::>

"-

ffl:0

0

a::
c 0.2

c

0.1

0.1

o
o

50

100
150
200
250
OUTPUT CURRENT (rnA)

= OPEl-

-"';"';"--r--..,

~

0

0

If

IvsJ

12.5

1

?!:

-25

300

25
50
75
TEMPERATURE (OC)

100

-

V,N = 6V
2.5 I- RL=oo
ILOAD = 0

o

125

-

VSFiliN =OV

5.0

"j.

I

-50 -25

0
25 50
75
TEMPERATURE (OC)

100

12

100

12

LT1521'Tf>{:Ol

lT1521-3
Output Voltage

lT1521-3.3
Output Voltage

3.08

3.38

3.06

3.36

3.04

?!:3.34

OJ

3.02

w

0

3.00

?!:
w

~

>

f-

::::>
0-

f-

,,- f-"

r--

~

w

--

3.30

!;:;
::::>
0

2.96
2.94

5.06
?!:

g: 3.26

2.98

5.08

.l

_Iour= lmA

~ 3.32

::::>

0

I

lT1521-5
Output Voltage

~

0

f-

r--

3.26

::::>

4.96

"f::::>
0

4.96

3.24

2.92
-50 -25

0
25
50
75
TEMPERATURE (OC)

100

4.94

3.22
-50 -25

125

-.... t'-.....

5.00

>

............ r-..

5.04
5.02

OJ

0
25
50
75
TEMPERATURE (OC)

100

4.92
-50 -25

125

0
25
50
75
TEMPERATURE (OC)

LT1521'TPC06

lT1521
Adjust Pin Voltage

lT1521-3
Quiescent Current

3.83 r--,,-,'-...,-,--,--,----,
ILOAD = lmA
3.81 f--'=f--r--t--+--t--t--I

50

1--+-+---+-'-+--1-+--1

40
35
30

i'l'i
a::

b~=4---+--+~,*,,=j=~

::::>

'-'

25

::::>

3.73 f--+--t--t--+--t--t--I

15
'-'
ffl

20

c

10

f-

3.75

::::>

o 3.71 f--+--t--t--+--t--t--I

a::

f-

:0

f-

35

a::
'-'

25

i'l'i
ffl
t.:)

15

3.69 f--+--t--t--+--t--t--I

5

o
o

4-82

40

30

1\

RL=oo

\

\
\

f-

3.67 '---'-_-'-_J.....-'-_-'-_'---'
-50 -25
0
25
50
75 100 125
TEMPERATURE (OC)
LT1521'TPC07

TJ~25oL

45

RL=oo

i'l'i
a::

C

~ 3.77

g:

50
TJ = 25°C

45

1

w

!;:;

lT1521-3.3
Quiescent Current

1

_ 3.79

~

LT1521'TPC06

VSHDN = OPEN VSHDN = OV

l -I -

c

I

3 4 5 6 7
INPUT VOLTAGE (V)

:0

6

9 10

20
15
10

o I
o 1

3

4

5

6

7

INPUT VOLTAGE (V)
LT1521'TPC08

6

9 l'

LT1521 /LT1521-3
LT1 521-3.3/LTl 521-5
rYPICAL PERFORmAnCE CHARACTERISTICS
LT1521-5
Quiescent Current
50

50

45

...1D~

40

...1D

25

a:
a:
=>
'-'
'-'

IL

TJ = 25'C
RL = 00

\

\
\

30

I \

40

10

~ 600

...1D

25

'-' 500

ffl

15

::;

a

oo

2

... 700

z

z

8

10

~

300

a:
'" 200

VSHDN = OV

o
o

9 10

VSHDN = OPEN l -

\.

5

3 4 5 6 7
INPUT VOLTAGE (V)

"Ft-rRLOAD = 1200
....... r-ILOAD = 25mA'- l -

V
.....

~ 400

\

1

1J

RLOAD = 600
ILOAD = 50mA'

V

=>

20

1

,I

. . . . 1"--.

.;,

30

VSHDN = OV

5

<" 800

\

35

'-'

VSHDN = OPEN -

TJ = 25'C
'FOR VDUT =)..V

900

RL = 00

...1D

a:
a:
=>
'-'

20

1000
TJ = 25'C

45

<"
.;,

1\

35

ffl 15
::;

a

LT1521-3
Ground Pin Current

LT1521
Quiescent Current

RLDAD -3000
IOAO 10mA' -

II,~

RLOAD = 3k
ILOAD -1mA'

100

o
3 4 5 6 7
INPUT VOLTAGE (V)

1

8

o

9 10

2

3

4

5

6

7

8

9 10

INPUT VOLTAGE (V)
LT1521·TPC12

LT1521-3
Ground Pin Currenl

LT1521-3.3
Ground Pin Current

,...

II

'lOiD=

~~

J~

o

o

1

r

2

I

RlOAD~

I

II

1000

TJ ~ 25'b 1
'FOR VOUT = 3V

r-.... -......L.I

r-

loort

I
I
I
RLOAD = 200
ILDAD = 150mA'

900

!z
=>

/

'-' 500

z

~

400
300

z

a:
'" 200
100

8

ILDAD = 50mA I

~ 600

5

I

lJ

RLOAD = 132ri ILOAD - 25mA'_

I;...

/

[

...1D
a:
a:

RLDAD = 3300
ILDAD -10mA'-

["..

/'

RLDAD - 3.3k
ILOAD = 1mA'

I1 I

Cl

z

3 4 5 6 7
INPUT VOLTAGE (V)

8

o
a:

'"

I

..".-

o

9 10

l'1il"- ~

·1

1

1

~

/'" ~=150mA'

=>

I

RlO~D

lRLDADI = 1.220 I-

1/

z

TJ = 25'C
'FOR VDUT = 3.3V

~N i l

=
ILDAD = 300mA'-

/

=>
'-'

a:

o
o

9 10

TJ = 25'C
'FOR VOUT = 3.3V

/~LOAD = 6 6 0 : - t - l l

700

I I

3 4 5 6 7
INPUT VOLTAGE (V)

YN

~ 800

RlOAD=300 ILOAD = 100mA'

1--

LT1521-3.3
Ground Pin Current

o

J
1

1

1

1

RLDAD -330 ILDAD = 100mA'

3 4 5 6 7
INPUT VOLTAGE (V)

2

8

~

9 10

LT1521'TPC15

LT1521-5
Ground Pin Current

LT1521-5
Ground Pin Voltage

1000
900

TJ = 25'C
'FOR VOUT = 5V

'[ 800

600

,/

::>

'"'
z 500

~ 400

z
~ 300
:!l

~D=150~A'

Il'k..

RLDAD =~
5000
/' k'
ILDAD = 1OmA'

I
RLOAD = 5k
ILOAD-1mA'

100

1

T;=2~'C

1

RLDAD = 2000

/

200

00

/'

1

RLDAD = 1000

/

=-z 700
~

1

8

9 10

LT1521'TPC16

I I

1

- 'FORVOUT = 5V- I -

r

...1D~
a:
a:

z

/

a:
Cl

z
=>
o
a:

-'- ,/'

'"
o

J
1

~

2

1000

1.

~AD=300mA'

......... .......

~ 800
... 700
z

~

13
z

r..

RLDAD = 33.30
~OAD=150mA'

--

I--.
RLDAD - 500
ILOAD = 100mA'

3 4 5 6 7
INPUT VOLTAGE (V)

TJ = 25'C

900

RLOAO = 16.70

V

=>
'-'

o
3 4 5 6 7
INPUT VOLTAGE (V)

1

LT1521
Ground Pin Current

500

~

400

5a:

300

z

/

600

9 10

V

'" 200

o

VOUr=VADJ
'FOR VOUT = 3.75V

VRLOAD = 750 ~
ILDAD= 50mA .1
1

J

V
I-'

RLDAD = 1500
ILDAD - 25mA'

R~OADI= 3~0

10mA'

ILOAD

.1

1

1.

3 4 5 6 7
INPUT VOLTAGE (V)

8

9 10

RLDAD = 3.8k
ILDAD -1mA'

100
8

~

o

1

2

LT1521'TPC17

4-83

LT1521/LT1521-3
LTl 521-3.3/LTl 521-5
TYPICAL PERFORmAnCE CHARAOERISTICS
LT1521
Ground Pin Current
TJ = 25'C
VOUPVADJ
"FOR VOUT = 3.7~vj

!

I

1ia:5

r--.ll I
RL~AD~
......
ILDAD .aOOmA"

V

a:
:::>
<>

z

J

a:
o

II

z
o
a:

:::>

tV

'"
o

o

V

2

!

,

<>

TJ = 25'C

z

RLbAD! 25ri
ILOAD =150mA"
t- ~.I

a:

-

2.0

z
:::>
o
a:

I

~ 1.6

9

~ 1.4

~ 1.2 ........ ............

F
z

1.0

z

0.8

15

0.6

~

I'-...........

5 0.4
en

0.2

o

O~-~~~~-~--~--~

o

9 10

50

100
150
200
250
OUTPUT CURRENT (rnA)

-50 -25

300

0
25 50
75
TEMPERATURE ('C)

Shutdown Pin Threshold
(Off-to-On)
1.8

~

1.6

~

1.4

9

~
F
z

1.0

z

0.8

a:

~
o

5::t:

en

1.2

-

........

t---....

ILOAD = 300mA_

..........

~

r-....

~
I-

-

iii
a:

.............

r--- _ILOAD=1~"

a:
<>

25

VS~N=Ot

~

2.5

-

2.0

:::>

...........

z

a:
........

1.5

z

;;:

0

0.6

C
I-

S
iii
a:

I-

20

a:
:::>
<>

15

I-

.,

:::>

"-

z

a:

1.0

10

z

;;:

:::>
::t:

0.4

0

0
I-

en 0.5

:::>
::t:

0.2

1/

en

o

-50 -25

0
25 50
75
TEMPERATURE ('C)

100

o

125

125

Shutdown Pin Input Current

Shutdown Pin Current
3.0

100

LT1521·TPC21

LT1521·TPC20

2.0

.......

::t:

'"

8

I

1.8 -ILOAD= 1mA

a:

o

1 , ,

3 4 5 6 7
INPUT VOLTAGE (V)

10.--,--,,--,--.--,--,
VIN = 3V (LT1521-3)
9 VIN = 3.3V (LT1521-3.3)
VIN = 5V (LT1521-5)
_ TJ = 125'C
VIN = 3.75V (LT1521)
DEVICE IS OPERATING
!Z
IN DROPOUT
~
a:
:::>

RLOAD = 37.50
ILOAD =100mA"

I
1

III

.-

Shutdown Pin Threshold
(On-to-Olt)

Ground Pin Current

--- 150
iii

~ 125
:::>
<>
~ 100

a;
~

t;;
:::>

~

75

50

Current Limit
0,6

50r-~~~~-.--rr-.-,,~on

~

'" '"
"'-

o

1i5 35

-
<>
!:: 0.3
:::>
<>
a:
13
o.!. 0.2
a:

10r-+-~-+-~~~~~~-r-4

en

W~
a::

I

I

/

LT1521:j~,,'"

~~

131521-5 _ _

o ~1..iII!!"""~""""::""..L.-'--'----L'i_·-'----J,..'·-l

o

3 4 5 6 7 8
OUTPUT VOLTAGE (V)

9 10

I---

0.4

25

ILT1i21-3.3.~...-!-I-~76-1-tl

.!.

I-

5

I

.1

VoupOV
0.5

30

5

. . . r-- t--

TJ = 25'C
LT1521
VIN= OV
CURRENT FLOWS -t-tt-t--+tIH-tl
INTO OUTPUT PIN I
VOUP VSENSE
-it--I-ttlf-H
(LT1521-3ILT1521-3.3_-tt--+--t-ttt-ti
LT1521-5)
VOUP VADJ (LT1521)
./

~

a

i'..

25

45
40

,....- ~

I

0
::t:

0.1

o

-

o

J

INPUT VOLTAGE (V)
LT1521·TPC27

LT1521 /LTl521-3
LT1521-3.3/LTl521-5
TYPICAL PERFORmAnCE CHARAOERISTICS
Current Limit

Reverse Output Current

O.B

g

1
1
V'N = 7V
0.5 r- VOUT=OV

15a:

0.4

a:

B

§
Ii

~

1

-

.-

0.3

1

1

Ripple Rejection
66

t--

V'N'= Vou~ (NOJINAL) '+ lV +'O.5Vp_~
64 I- RIPPLE AT f = 120Hz
ILOAD = 150mA

1

Y'N = OY
I- YOUT = 3Y (LTC1521-3)
YOUT = 3.3Y (LTC1521-3.3)
~ YOUT = 5V (LT1521-5)
,=VOUT = 3.75V (LT1521)

I

)


.s
z

"8'OUT = 33"F
~D~~~TALUM

Ul 50

a:

-5

'1 1 I
!I I I



III.~

20

-10

II
I
1_
_ Ll.ILOAD = 1mA TO 300mA

1M

...........

~
"""

100

125

lT1521'TPC31

LT1521-5
Transient Response

..' 1. I
0.2 -V,N=6V
C'N = O.l"F
c5~ 0.1 -COUT = 1.5"

LT1521-5
Transient Response

~_

;5e:.

~~ 0
5~-O.1

~> 0.2

;0-

.A

I

~~

II

<>-G;
~Q-O.l
o

o

-0.2

15a:
~

9

-0.2

15

150

13:[100
50

I

A

c5~ 0.1

300
a:
13:[200
o
100

I

g

50 100 150 200 250 300 350 400 450 500
TIME (JiS)
LT1521'TPC33

1/\

V'N = BV
C'N = O.l"F
COUT = 331'F

\I

U

I
I

I
I

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TIME (ms)
tT1521'TPC34

4-85

LT1521/LT1521-3
LT1521-3.3/LT1521-5
Pin FunOlons
OUT (Pin 1): The output pin supplies power to the load. A
minimum output capacitor of 1.5JlF is required to prevent
oscillations, but larger values of output capacitor will be
necessary to deal with larger load transients. See the
Applications Information section for more on output capacitance and reverse output characteristics.
SENSE (Pin 2): For fixed voltage versions of the LT1521
(LT1521-3, LT1521-3.3, LT1521-5), the sense pin is the
input to the error amplifier. Optimum regulation will be
obtained at the pOint where the sense pin is connected to
the output pin of the regulator. In critical applications
small voltage drops caused by the resistance (Rp) of PC
traces between the regulator and the load, which would
normally degrade regulation, may be eliminated by connecting the sense pin to the output at the load as shown
in Figure 1 (Kelvin Sense Connection). Note that the
voltage drop across the external PC traces will add to the
dropout voltage of the regulator. The sense pin bias
current is 5!!A at the nominal regulated output voltage.
This pin is internally clamped to -O.6V (one VBE).

ADJ (Pin 2): For adjustable LT1521, the adjust pin is the
input to the error amplifier. This pin is internally clamped
to 6V and -O.6V (one VBE). It has a bias current of 50nA
which flows into the pin. See Adjust Pin Bias Current vs
Temperature in the Typical Performance Characteristics
section. The adjust pin reference voltage is 3.75V referenced to ground. The output voltage range that can be
produced by this device is 3.75V to 20V.
SHDN (Pin 5): The shutdown pin is used to putthe device
into shutdown. In shutdown the output of the device is
turned off. This pin is active low. The device will be shut
down ifthe shutdown pin is pulled low. The shutdown pin
current with the pin pulled to ground will be 1.7!!A. The
shutdown pin is internally clamped to 7V and-O.6V (one

VBE). This allows the shutdown pin to be driven directly by
5V logic or by open collector logic with a pull-up resistor.
The pull-up resistor is only required to supply the leakage
current ofthe open collector gate, normally several microamperes. Pull-up current must be limited to amaximum of
5mA. A curve of the shutdown pin input current as a
function of voltage appears in the Typical Performance
Characteristics. If the shutdown pin is not used it can be
left open circuit. The device will be active (output on) ifthe
shutdown pin is not connected.
IN (Pin 8): Power is supplied to the device through the
input pin. The input pin should be bypassed to ground if
the device is more than six inches away from the main
input filter capacitor. In general, the output impedance of
battery rises with frequency, so it is advisable to include a
bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1JlF to 10JlF is sufficient. The
LT1521 is designed to withstand reverse voltages on the
input pin with respectto ground and the output pin. In the
case of reversed input, which can happen if a battery is
plugged in backwards, the LT1521 will act as if there is a
diode in series with its input. There will be no reverse
current flow into the LT1521 and no reverse voltage will
appear at the load. The device will protect both itself and
the load.

LT1521·FOl

Figure 1. Kelvin Sense Connection

APPLICATions InFORmATion
The LT1521 is a 300mA low dropout regulator with
micropower quiescent current and shutdown. The device
is capable of supplying 300mA at a dropout of O.5V and
operates with very low quiescent current (12!!A). In shutdown, the quiescent current drops to only 6!!A.ln addition
to the low quiescent current, the LT1521 incorporates

4-86

several protection features which make it ideal for use in
battery-powered systems. The device is protected against
both reverse input voltages and reverse output voltages.
In battery backup applications where the output can be
held up by a backup battery when the input is pulled to

LT1521 /LTl521-3
LT1521-3.3/LT1521-5
FlPPLICATlons InFORmATion
lround, the LT1521 acts like it has a diode in series with
ts output and prevents reverse current flow.
ldjustable Operation

'he adjustable version of the LT1521 has an output
roltage range of 3. 75V to 20V. The output voltage is set by
he ratio of two external resistors as shown in Figure 2. The
levice servos the output voltage to maintain the voltage at
he adjust pin at 3.75V. The current in R1 is then equal to
i.75v/R1. The current in R2 is equal to the sum of the
:urrent in R1 and the adjust pin bias current. The adjust pin
lias current, 50nA at 25°C, flows through R2 into the
ldjust pin. The output voltage can be calculated using the
ormula in Figure 2. The value of R1 should be less than
lOOk to minimize errors in the output voltage caused by
he adjust pin bias current. Note that in shutdown the
IUtPUt is turned off and the divider current will be zero.
:urves of Adjust Pin Voltage vs Temperature and Adjust
lin Bias Current vs Temperature appear in the Typical
lerformance Characteristics. The reference voltage at the
djust pin has a positive temperature coefficient of aplroximately 15ppm/oC. The adjust pin bias current has a
legative temperature coefficient. These effects will tend to
ancel each other.
---...--....- VOUT

VOUT = 3.75V (1
VADJ

=

+~)+ (IADJ +R2)

3.75V

IADJ = 50nA AT 25°C
OUTPUT RANGE = 3.75V TO 20V

Figure 2. Adjustable Operation

'he adjustable device is specified with the adjust pin tied
J the output pin. This sets the output voltage to 3.75V.
,pecifications for output voltages greater than 3.75V will
eproportional to the ratio of the desired output voltage to
.75V; (VouT/3.75V). For example: load regulation for an
utput current change of 1rnA to 300mA is -20mV typical
t VOUT = 3.75V. At VOUT = 12V, load regulation would be:
(12V/3.75V) x (-20mV) =-64mV

L7lJ[J~

Thermal Considerations

The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components:
1. Output current multiplied by the inpuVoutput voltage
differential: lOUT x (VIN - VOUT), and
2. Ground pin current multiplied by the input voltage:
IGND x VIN
The ground pin current can be found by examining the
Ground Pin Current curves in the Typical Performance
Characteristics. Power diSSipation will be equal to the sum
of the two components listed above.
The LT1521 series regulators have internal thermal limiting designed to protect the device during overload conditions. For continuous normal load conditions the maxi- . .
mum junction temperature rating of 125°C must not be . .
exceeded. It is important to give careful consideration to
all sources ofthermal resistance from ju nction to ambient.
Additional heat sources mounted nearby must also be
considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat generated by power devices.
The following tables list thermal resistance for each package. Measured values of thermal resistance for several
different board sizes and copper areas are listed for each
package. All measurements were taken in still air on
3/32" FR-4 board with one ounce copper. All NC leads were
connected to the ground plane.
Table 1. 88 Package*
COPPER AREA
TOPSIDE"
BACKSIDE
2500 sq mm 2500 sq mm

1000 sq mm 2500 sq mm
225 sq mm 2500 sq mm
100 sq mm 2500 sq mm

..

BOARD AREA
2500 sq mm
2500 sq mm

2500 sq mm
2500 sq mm

THERMAL RESISTANCE
(JUNCTION·TO·AMBIENT)

60°CIW
60°CIW
68°CIW
WCIW

. .

Pins 3, 6, 7 are ground .•• DeVice IS mounted on topside .

4-87

LT1521 /LT1521-3
LT1521-3.3/LT1521-5
APPLICATions InFoRmATion
Table 2. 80T-223 Package
(Thermal Resistance Junction-Io-Tab 2DoC/W)
COPPER AREA
TOPSIDE'

2500 sq mm
1000 sq mm
225 sq mm
100 sq mm
1000 sq mm
1000 sq mm

BACKSIDE

2500 sq
2500 sq
2500 sq
2500 sq
1000 sq
0

mm
mm
mm
mm
mm

BOARD AREA

2500 sq
2500 sq
2500 sq
2500 sq
1000 sq
1000 sq

mm
mm
mm
mm
mm
mm

THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)

50°C/W
50°C/W
58°C/W
WC/W
5rC/W
60°C/W

Tab of device attached to topSide copper.

Calculating Junction Temperature
Example: Given an output voltage of 3.3V, an input voltage
range of 4.5V to 7V, an output current range of OmA to
150mA and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be?
The power dissipated by the device will be equal to:
IOUT(MAX) x (VIN(MAX) - VOUT) + (lGND x VIN(MAX))
Where,
10UT(MAX) = 150mA
VIN(MAX) = 7V
IGND at (lOUT =150mA, VIN

=7V) =2.1 mA

So,
P = 150mA x (7V - 3.3V) + (2.1 mA x 7V) = O.57W
If we use a SOT-223 package, then the thermal resistance
will be in the range of 50°C/W to 65°C/W depending on the
copper area. So the junction temperature rise above
ambient will be approximately equal to:
O.57W x 60°C/W = 34.2°C
The maximum junction temperature will then be equal to the
maximum junction temperature rise above ambient plus the
maximum ambient temperature or:
TJMAX =50°C + 34.2°C =84.2°C
Output Capacitance and Transient Performance
The LT1521 is designed to be stable with a wide range of
output capacitors. A minimum output capacitor of 1.5!lf
is required to prevent oscillations. The LT1521 is a
micropower device and output transient response will be
a function of output capacitance. See the Transient Re-

4-88

sponse curves in the Typical Performance Characteristics. Larger values of output capacitance will decrease the
peak deviations and provide improved output transient
response for larger load current deltas. Bypass capacitors, used to decouple individual components powered by
the LT1521 , will increase the effective value of the output
capacitor.
Protection Features
The LT1521 incorporates several protection features which
make it ideal for use in battery-powered circuits. In
addition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse input
voltages, reverse output voltages and reverse voltages
from output to input.
Current limit protection and thermal overload protection
are intended to protectthe device against current overload
conditions at the output of the device. For normal operation, the junction temperatures should not exceed 125°C.
The input of the device will withstand reverse voltages of
20V. Current flow into the device will be limited to less
than 1mA (typically less than 1OO~) and no negative
voltage will appear at the output. The device will protect
both itself and the load. This provides protection against
batteries that can be plugged in backward.
For fixed voltage versions of the device, the output can be
pulled below ground without damaging the device. If the
input is left open circuit or grounded, the output can be
pulled below ground by 20V. The output will act like an
open circuit, no current will flow out of the pin. If the input
is powered by voltage source, the output will source the
short-circuit current of the device and will protect itself by
thermal limiting. For the adjustable version of the device,
the output pin is internally clamped at one diode drop
below ground. Reverse current for the adjustable device
must be limited to 5mA.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage or is left open
circuit. Current flow back into the output will vary depending on the conditions. Many battery-powered circuits

LT1521 /LT1521-3
LT1 521-3.3/LTl 521-5
rlPPLICATlons InFORmATion
ncorporate some form of power management. The folowing information will help optimize battery life. Table 3
;ummarizes the following information.

pin is left open. The state of the shutdown pin will have no
effect on the reverse output current when the input pin is
floating.

rhe reverse output current will follow the curve in Figure
~ when the input is pulled to ground. This current flows
hrough the output pin to ground. The state of the shutlown pin will have no effect on output current when the
nput pin is pulled to ground.

When the input of the LT1521 is forced to avoltage below
its nominal output voltage and its output is held high, the
output current will follow the curve shown in Figure 3. This
can happen if the input of the LT1521 is connected to a
discharged (low voltage) battery and the output is held up
by either a backup battery or by second regulator circuit.
When the input pin is forced below the output pin or the
output pin is pulled above the input pin, the input current
will typically dropto less than 2~ (see Figure4). The state
of the shutdown pin will have no effect on the reverse
output current when the output is pulled above the input.

nsome applications it may be necessary to leave the input
mthe LT1521 unconnected when the output is held high.
rhis can happen when the LT1521 is powered from a
'ectified AC source. If the AC source is removed, then the
nput of the LT1521 is effectively left floating. The reverse
lUtputcurrentalsofoliowsthe curve in Figure3 if the input
50

r::-'~~~-'-"-r--r"TTT"

!;

30
25

TJ = 25°C
LT1521
VIN=OV
CURRENT FLOWS --+----tI--t--Htt-H
INTO OUTPUT PIN I
VOUT = VSENSE
---1t--f--+lt+---tl
(LT1521-31LT1521-3.3_-it--1--+tt+-+I
LT1521-5)
VOUT = VADJ (LT1521)
./

~

20

ILT1'21-3.3"-l1--+~--...I!:J-+--+I

00

15~-+~4-~~r-+-+~

~

10~-+~~~~~~~

45
~ 40
>15 35
~

G

!3

I

I

I

LT1521-3.3

V

LT1521-3~

ffi

LT1521-3
~T1521-5

......... ~

~~"lT1521-5_1-

rr

~~

o
o

1

2

•

VOUT = 3V (LT1521-3)
VOUT = 3.3V (LT1521-3.3)
VOUT = 5V (LT1521-5)

'i'I'

3 4 5 6 7 8
OUTPUT VOLTAGE (V)

o

o

9 10

.L~
INPUT VOLTAGE (V)

Figure 3. Reverse Output Current

Figure 4. Input Current

'able 3. Fault Conditions
< VOUT (Nominal)

INPUT PIN

SHDN PIN
Open (High)

Forced to VOUT (Nominal)

< VOUT (Nominal)

Grounded

Forced to VOUT (Nominal)

Open

Open (High)

>1V

Open

Grounded
Open (High)

>1V

Reverse Output Current ~ 5!lA (See Figure 3)

sOV

Output Current =0
Output Current =0
Output Current =Short-Circuit Current
Output Current =0

sO.8V
sO.8V
> 1.5V
-20V < VIN

< 20V

L7lJD~

Grounded
Open (High)
Grounded

OUTPUT/SENSE PINS

sOV
sOV
sOV

RESULTING CONDITIONS
Reverse Output Current ~ 5!lA (See Figure 3)
Input Current ~ 1!lA (See Figure 4)
Reverse Output Current ~ 5!lA (See Figure 3)
Input Current ~ 1!lA (See Figure 4)
Reverse Output Current ~ 5!lA (See Figure 3)

4-89

LT1521/LT1521-3
LT1521-3.3/LT1521-5
RELATED PARTS
PART NUMBER
LT(;®1174

DESCRIPTION
425mA High Efficiency Step-Down Switching Regulator

COMMENTS
' >90% Efficiency, SO-8 Package

LT1175

500mA Micropower Low Dropout Negative Linear Regulator

Selectable Current Limit

LT1120A

125mA Micropower Low Dropout Linear Regulator

201lA Quiescent Current, Includes Comparator

LT1304

Micropower Step-Up DC/DC Converter

151lA Quiescent Current, 1.5 Minimum Input

LT1529

3A Micropower Low Dropout Regulator

501lA Quiescent Current

4-90

'~TLElcnHNt1\O"O-G~~~----------U_15_28
~,
~
3A Low Dropout Regulator
II

for Microprocessor Applications
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•

DESCRIPTiOn

Dropout Voltage: O.6V at loUT =3A
Fast Transient Response
Output Current: 3A
Quiescent Current: 400~
No Protection Diodes Needed
Fixed Output Voltage: 3.3V
Controlled Quiescent Current in Dropout
Shutdown 10 = 125~
Stable with 3.3JlF Output Capacitor
Reverse Battery Protection
No Reverse Output Current
Thermal Limiting

The LT®1528 is a 3A low dropout regulator optimized to
handle the large load current transients associated with
the current generation of microprocessors. This device
has the fastest transient response of currently available
PNP regulators and is very tolerant of variations in capacitor ESR. Dropout voltage is 75mV at 10mA, rising to
300mVat 1Aand 600mVat 3A. The device has aquiescent
current of 400~. Quiescent current is well controlled; it
does not increase significantly as the device enters dropout. The regulator can operate with output capacitors as
small as 3.3JlF, although larger capacitors will be needed
to achieve the performance required in most microprocessor applications. The LT1528 is available with a fixed . , .
output voltage of 3.3V. An external Sense pin allows . .
adjustment to output voltages greater than 3.3V, using a
simple resistive divider. This allows the device to be
adjusted over a wide range of output voltages, including
the 3.3V to 4.2V range required by avariety of processors
from Intel, IBM, AMD, and Cyrix.

APPLICATions
• Microprocessor Applications
• Post Regulator for Switching Supplies
• 5V to 3.3V Logic Regulator

The LT1528 has both reverse input and reverse output
protection and includes a shutdown feature. Quiescent
current drops to 125~ in shutdown. The LT1528 is
available in 5-lead TO-220 and 5-lead DO packages.
LT, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Dropout Voltage

Microprocessor Supply with Shutdown
0.6
...!..-_ _- _ -.... VOUT

681l

T

0.5

4 x4hlF'
SOLID TANTALUM

/

~
~

0.4

V

~

./

~ 0.3

>-

:::l

":"

~a:

":"

0.2

Cl

VSHON (PIN 4)
<0.25
>2.80
NC

OUTPUT
OFF
ON
ON

..L7lJ!J~

SHORTING
J1
J2
J3

VOUT
3.30
3.45
4.00

'CHOOSE CAPACITORS
TO MEET PROCESSOR
REQUIREMENTS

0.1

o

/

/
o

V
0.5

1.0
1.5
2.0
2.5
OUTPUT CURRENT (rnA)

3.0

4-91

LT1528
ABSOLUTE mAxmum RATinGS
Input Voltage ....................................................... ±15V*
Output Pin Reverse Current .................................. 10mA
Sense Pin Current ................................................. 10mA
Shutdown Pin Input Voltage (Note 1) .......... 6.5V, -0.6V
Shutdown Pin Input Current (Note 1) ..................... 5mA

Output Short-Circuit Duration .......................... Indefinite
Storage Temperature Range ................. -65°C to 150°C
Operating Junction Temperature Range
LT1528C ............................................... O°C to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
'For applications requiring input voltage ratings greater than 15V, contact
the factory.

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

FRONT VIEW

Elir

TAB
ISO
GND

4

3
2
1

SRDN
GND
SENSE
OUTPUT

LT1528CQ

a PACKAGE
HEAD PLASTIC DD PAK

TAB IS
GND

ORDER PART
NUMBER

FRONT VIEW

0

5

VIN

4
3

GND

2
1

SENSE
OUTPUT

SHDN

LT1528CT

TPACKAGE
HEAD PLASTIC TO·220
TJMAX =125'C, OJA =50'C/W

TJMAX =125'C, OJA =30'C/W
Consult factory for Industrial and Military grade parts.

ElEORICAl CHARAOERISTICS
PARAMETER
Regulated Output Voltages (Notes 2, 3)
Line Regulation (Note 3)
Load Regulation (Note 3)
Dropout Voltage (Note 4)

4-92

CONDITIONS
VIN= 3.8V, lOUT = 1rnA, TJ = 25°C
4.3V < VIN < 15V, lmA < lOUT < 3A
,WIN = 3.8V to 15V, lOUT = 1rnA
AILOAD = 1rnA to 3A, VIN = 4.3V,TJ = 25°C
AILOAD = 1rnA to 3A, VIN = 4.3V
ILOAD = lOrnA, TJ = 25°C
ILOAD = lOrnA
ILOAD = 100mA, TJ = 25°C
ILOAD = 100mA
ILOAD = 700mA, TJ = 25°C
ILOAD = 700mA
ILOAD = 1.5A, TJ = 25°C
ILOAD = 1.5A
ILOAD = 3A, TJ = 25°C
ILOAD = 3A

•
•
•
•

•
•
•
•

MIN
3.250
3.200

TYP

MAX

3.300
3.300
1.5
12
15
70

3.350
3.400
10
20
30
110
150
200
250
320
420
450
600
670
850

150
280
390
570

UNITS
V
V
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV

LTl528

ELEORICAL CHARACTERISTICS
PARAMETER
Ground Pin Current (Note 5)

Sense Pin Current (Notes 3, 7)
Shutdown Threshold
Shutdown Pin Current (Note 8)
Quiescent Current in Shutdown (Note 9)
Ripple Rejection
Current Limit
Input Reverse Leakage Current
Reverse Output Current (Note 10)

CONDITIONS
ILOAD =OmA, TJ =25°C
ILOAD =OmA, TJ =125°C (Note 6)
ILOAD =100mA, TJ =25°C
ILOAD =100mA, TJ =125°C (Note 6)
ILOAD =300mA, TJ =25°C
ILOAD =300mA, TJ =125°C (Note 6)
ILOAD =700mA, TJ =25°C
ILOAD =700mA, TJ =125°C (Note 6)
ILOAD =1.5A
ILOAD =3A
TJ =25°C
VOUT =Off-to-On
VOUT =On-to-Off
VSHDN =OV
VIN =6V, VSHDN =OV
VIN - VOUT =lV(Avg), VRIPPLE =0.5Vp_p,
fRIPPLE =120Hz, ILOAD =1.5A
VIN - VOUT =7V, TJ =25°C
VIN =4.3V, AVOUT =-0.1V
VIN =-15V, VOUT =OV
VOUT =3.3V, VIN =OV

The. denotes specifications which apply over the full operating
temperature range.
Nole 1: The Shutdown pin input voltage rating is required for a low
impedance source. Internal protection devices connected to the Shutdown
pin will turn on and clamp the pin to approximately 7V or -0.6V. This
range allows the use of 5V logic devices to drive the pin directly. For high
impedance sources or logic running on supply voltages greater than 5.5V,
the maximum current driven into the Shutdown pin must be less than
5mA.
Nole 2: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current must be limited.
When operating at maximum output current, the input voltage range
must be limited.
Nole 3: The LT1528 is tested and specified with the Sense pin connected
to the Output pin.

50

TYP
450
1.9
1.2
2.7
2.6
4.1
7.3
8.8
22
85
130
1.20
0.75
37
110
67

3.2

4.5
4.0

MIN

•
•

••
•
•

•
•

90
0.25

120

MAX
750
2.5
4.0
12.0
40
140
250
2.80
100
220

UNITS
~

rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
~
V
V
~
~

dB

1.0
250

A
A
rnA
~

Nole 4: Dropout voltage is the minimum input/output voltage required to
maintain regulation at the specified output current. In dropout the output
voltage will be equal to: (VIN - VDROPOUT).
Note 5: Ground pin current is tested with VIN = VOUT (nominal) and a
current source load. This means that the device is tested while operating in
its dropout region. This is the worst-case Ground pin current. The Ground
pin current will decrease slightly at higher input voltages.
Nole 6: Ground pin current will rise at TJ > 75°C. This is due to internal
Circuitry designed to compensate for leakage currents in the output
transistor at high temperatures. This allows quiescent current to be
minimized at lower temperatures, yet maintain output regulation at high
temperatures with light loads. See quiescent current curve in typical
performance characteristics section.
Note 7: Sense pin current flows into the Sense pin.
Note 8: Shutdown pin current at VSHDN = OV flows out of the Shutdown pin.
Note 9: Quiescent current in shutdown is equal to the total sum of the
Shutdown pin current (40~) and the Ground pin current (70~).
Nole 10: Reverse output current is tested with the input pin grounded and
the Output pin forced to the rated output voltage. This current flows into
the Output pin and out of the Ground pin.

4-93

LT1528
TYPICAL PERFORmAnCE CHARAOERISTICS
Guaranteed Dropout Voltage
1.0
0.9 _0 =

~EST P~INTS

I

0.8

§ 0.7
;::
'" 0.6

I.

§; 0.5
!;

/'

It

0.4
~ 0.3

Cl

0.2

,/

./

./"

V

/"

./

J""lj,,25°C_ ' - -

.cr

/

~

,/

I- TJ'; 125°C

-

Dropout Voltage

Quiescent Current

0.8

r----r--,----,-,-----,---,---,

2.00

0.7

f--+-t--t-+-'-I-+-=-I

1.75

! 1.50

0.6 I--+--j---

w

ffi

~ 0.5

§; 0.4
!;

It
Cl
0::
Cl

0.3

0::
0::

0.21--"'F-+-:::=I-'"I:""-'

!2
~

[jJ

0.5

1.0
1.5
2.0
OUTPUT CURRENT (A)

2.5

-60 -25

3.0

0
25
50
75
TEMPERATURE (OC)

0.75

el 0.50 I--- -

VSHDN - OPEN

0.25 f--- -

~I=OV

,...-

..o

OL--L_L--L_L--L_L-~

o

/
/
/

1.25

13 1.00

i:;;..-1'=-+--''t:;,.,j.'''''''''''f--f---::;i

0.1

o

I
l
VIN =4.3v

r- RL = =

100

125

I
./

-

1

-60 -25

0
25
50
75
TEMPERATURE (OC)

100

125

LT15~'TP(;Ol

Quiescent Current

Sense Pin Voltage

1750

I
I
3.375 rJLOAD= lmA

ILOAD = 0
RLOAD = 00

1\

1>- 1500

«

~3.350

I--

w

~3.325

iii
1250
0::
0::

131000

§; 3.300

!2

a:

2:

~ 750

~3.275

[jJ

el

Ground Pin Current

3.400

2000

2:

500

~ 3.250

VSHDN = OPEN (HIGH)

250

I

VSHDN = OV

o
o

3

4

5

6

7

8

./

V

.....- / "

1\

5

ffi

\ .....

k.

0::
0::

13
z

RL=11Q - ILOAD = 300mA'

a:
z

\~

Cl
0::

\I\!LOAO = 100mA'

Cl

V

=>

'"

3.225
3.200
-60 -25

9 10

oS

TJ = 25°C
VOUT = VSENSE "FOR VOUT = 3.3V
I
I I
RL= 6.60
ILOAD = 500mA"

INPUT VOLTAGE (V)

25
50
75
TEMPERATURE (OC)

100

o

125

---

-

RL = 330Q: ILOAD = 1OmA'

o

1

2

3 4 5 6 7
INPUT VOLTAGE (V)

8

9 10

lT1528·TPC06

Ground Pin Current
100

Tj=2~OC I

90

«

oS
>iii
0::
0::

=>

80

50

a:
Cl

40

=>

30 -

'"

20

z

Cl
0::

......

60

u

z

I

70

10

o
o

RL=2.2Q

-~lr
y
t

t--;

I

VOUT = VSENSE
'FOR IVOUl = 3. 3V
1

r'{...J I
RL=1.1ilILOAO= 3A' -1- I I

I

Shutdown Pin Threshold
(On-to-Off)

Ground Pin Current

RLI=4)Q I
ILOAD = 700mA'

J

3 4 5 6 7
INPUT VOLTAGE (V)

!
ffi

0::
0::

~
a:
~

~

100 ,..---,-----,----,----,----,-......,
VIN =1 3.3V I
I
90 r- DEVICE IS OPERATING -+-1-+-1j-fl,
80 r-INDROPOUT
70
60 1---1--+-

40
30

9 10

-~J=12~oC7lJ

I
TJ = 25°C

50

V§
h if
'Y/

....:~J=-50°C

1

~ 1.6

9

~
F!:
z
a:

1.2

......
............

1.0

z 0.8

~

Cl

r-.......

........... .......
............

0.6

!;
20
10

:r: 0.4
en

"

_ .........
o

0.5

./

1.0
1.5
2.0
OUTPUT CURRENT (A)

0.2
2.5

3.0

LT1528"TPC08

4-94

1

1.8 -ILOAD= lmA

~ 1.4

f--f--tr--t--1~/~J.V+-~

o

8

1

2.0

o

-50 -25

0
25 50
75
TEMPERATURE (OC)

100

125

LTl528
TYPICAL PERFORmAnCE CHARAOERISTICS
Shutdown Pin Threshold
(Off-to-On)
100

1.8

~ 1.6
9
§'! 1.4 I"-....
~

'" 1.2

l"- t-.

I'--

I
ILOAO = 3A_

-- t-I..
...........

:J:

~ 1.0

a::

90 r-

r--

r-

:;(

.:;

80

iE

70

....

20

15

iE

'"
'"
u

...........

z

a::

50

::J
0.

t-....

i"'-.

::J

....

z 40
S:
<::>

<::>
....
::J
:J:
U)

U)

;;;
z
a:: 10

f.-- r--

30

z

S:
<::>
<::>

....

20

::J

0.2
-50 -25

0
25 50
75
TEMPERATURE (OC)

100

o

125

-50 -25

Sense Pin Current
200
175

~ 150

'E

125

:J

100

~~

---

100

o

125

~

....

- --

150

50

50

25

o

125

-I f.-- ~

-50 -25

V

V

~

~ 100

<::>

100

I
VOUT= OV

I

as

'"ug5

2
4 5 6
SHUTDOWN PIN VOLTAGE (V)

Current Limit

1 200

::J

0
25
50
75
TEMPERATURE (OC)

o

I
I
VIN = OV
250 - VOUT = VSENSE

r-

75

-25

25 50
75
TEMPERATURE (OC)

300

"I>

o-50

o

Reverse Output Current

f-- CU~RENTIFLOW~ INTOISENS~ PIN

I

1)5

10

o

~

:;(

.s
....

60

::J
U

~ 0.4

'"I>E

VS~DN = ~V

'"'"

g 0.6

";:z

25

ILOAD = 1mA

~ 0.8

""

Shutdown Pin Input Current

Shutdown Pin Current

2.0

/

II

0
25
50
75
TEMPERATURE (OC)

100

o

o

125

2
3
4
5
INPUT VOLTAGE (V)

LT1528·TP<.:14

Current Limit

v

800
1700

....

'"ug5

70

T~ = 2k ~IN =IOV
VOUT =VSENSE
CURRENT FLOWS
INTO DEVICE

900

....iE

VIN(AVG) = 4.3V
68 - VRIPPLE = 0.5Vp.p AT f = 120Hz
IL = 1.5A

aJ

:e
z
<::>
....
c::;

600

Ul

/'

0.

t::; 300

"

<::>

::>

I:

200

r-VIN = 7V
VOUT= OV

o

OJ

-50 -25

0
25 50
75
TEMPERATURE (OC)

/'

100

I
100

125

66
64

w

500

t::; 400

"

Ripple Rejection

Reverse Output Current
1000

o

o

V

4

62

a:

60

0.
0.

I"- r-.

r- r---...

58

1/
3

'"~

5

6

7

OUTPUT VOLTAGE (V)

8

9 10

56
-50 -25

25 50
75
TEMPERATURE (OC)

100

125

LT1528-TP{:16

4-95

LTl528

TYPICAL PERFORmAnCE CHARAOERISTICS
Ripple Rejection

Load Regulation

80
VINI=

~

~

70

-5

~ 60

is

:[ -10
50

r-

t5

~ 40
~

30

o:

20

cc-

- r-- r-r---..

l!.ILOAo = lmA TO 3A_

.......

is
>=

COUT = 4 x 47"F
SOLID TANTALUM

~
ffi
IX:

""'" Co~;'~'47"F

IiO'lii Dm,mLUi

""r-..

-15

~ -20

IOUP1.5AIIIIII" 111111111 I

10

Vo~(NOM\NAL) ~ 1V

"

-25

VIN = 6V + 50mVRMS RIPPLE

o

'"'"

10

100

'"'"

-30
--50 -25

1111111

lk
10k
FREQUENCY (Hz)

lOOk

1M

0
25 50
75
TEMPERATURE (OC)

100

125

LT152S'TPC19

Transient Response
w_

<.0>

.I L

100

1\

;'!:.§. 50

152
>Q

0

~~

-50

>-!;(

::::>0

o

-100

Transient Response

"\

11\

I
VIN=5V
CIN = 3.3"F
COUP 47"F-

II

l'2

::::>

"

~

o

n

I

i\.

0

\v

N

-100

g
~

3
2

l'2

I

u

~

I I
CIN = 3.3"F
CouP 4 x 47"F

~ -50

g
~

VI~ = 5~

_ 100
>
.§. 50
z

0

I

o 20 40 60 80 100 120140160 180200
TIME(JlS)

3

2 I

I

I

I

13
o

9

0

o

w

~

60

601001Wl~160160WO

TIME (1'8)
LT152a'TPC2Z

Pin FunOlons
OUTPUT (Pin 1): The Output pin supplies power to the
load. A minimum output capacitor of 3.3W is required to
prevent oscillations. Largervalues will be needed to achieve
the transient performance required by high speed microprocessors. See the Applications Information section for
more on output capacitance and reverse output characteristics.
SENSE (Pin 2): The Sense pin is the input to the error
amplifier. Optimum regulation will be obtained at the point
where the Sense pin is connected to the Output pin. For
most applications the Sense pin is connected directly to
the Output pin atthe regulator. In critical applications small
voltage drops caused by the resistance (Rp) of PC traces

4-96

between the regulator and the load, which would normally
degrade regulation, may be eliminated by connecting the
Sense pin to the Output pin at the load as shown in Figure
1 (Kelvin Sense Connection). Note that the voltage drop
across the external PC traces will add to the dropout
voltage of the regulator. The Sense pin bias current is
150j.IA atthe nominal regulated output voltage. See Sense
Pin Current vs Temperature in the Typical Performance
Characteristics section. This pin is internally clamped to
-O.6V (one VBE).
The Sense pin can also be used with a resistor divider to
achieve output voltages above 3.3V. See the Applications
Information section for information on adjustable operation.

LTl528

Pin FunCTions
)HDN (Pin 4): This pin is used to put the device into
;hutdown.ln shutdown the output of the device is turned
)ff. This pin is active low. The device will be shut down if
he Shutdown pin is actively pulled low. The Shutdown pin
:urrent with the pin pulled to ground will be 60~. The
,hutdown pin is internally clamped to 7V and -O.6V (one
'BE). This allows the Shu~down pin to be driven directly by
;V logic or by open collector logic with a pull-up resistor.
rhe pull-up resistor is only required to supply the leakage
:urrent ofthe open collector gate, normally several microImperes. Pull-up current must be limited to a maximum
)f 5mA. A curve of Shutdown pin input current as a
unction of voltage appears in the Typical Performance
;haracteristics section. Ifthe Shutdown pin is not used it
:an be left open circuit. The device will be active output on
f the Shutdown pin is not connected.

the device is more than six inches away from the main
input filter capacitor. The LT1528 is designed to withstand
reverse voltages on the input pin with respect to ground
and the Output pin. In the case of reversed input, the
LT1528 will act as if there is adiode in series with its input.
There will be no reverse current flow into the LT1528 and
no reverse voltage will appear at the load. The device will
protect both itself and the load.

(Pin 5): Power is supplied to the device through the
nput pin. The input pin should be bypassed to ground if

Figure 1. Kelvin Sense Connection

'IN

~PPLICATlons

LT1528·FQl

InFORmATiOn

[he LT1528 is a 3A low dropout regulator optimized for
nicroprocessor applications. Dropout voltage is only O.6V
It 3A output current. With the Sense pin shorted to the
)utput pin, the output voltage is set to 3.3V. The device
)perates with a quiescent current of 400~. In shutdown,
he quiescent current drops to only 125~. The LT1528
ncorporates several protection features, including protecion against reverse input voltages. If the output is held at
he rated output voltage when the input is pulled to ground,
he LT1528 acts like it has a diode in series with its output
Ind prevents reverse current flow.

formula in Figure 2. The value of R1 should be less than
330Q to minimize errors in the output voltage caused by
the Sense pin current. Note that in shutdown the output is
turned off and the divider current will be zero. Curves of
Sense Pin Voltage vs Temperature and Sense Pin Current
vs Temperature appear in the Typical Performance Characteristics section.
"'-t----....- VOUT

Ldjustable Operation
'he LT1528 can be used as an adjustable regulator with an
lutput voltage range of 3.3V to 14V. The output voltage is
:et by the ratio of two external resistors as shown in
:igure 2. The device servos the output voltage to maintain
he voltage at the Sense pin at 3.3V. The current in R1 is
hen equalto 3.3V/R1. The current in R2 isequaltothesum
If the current in R1 and the Sense pin current. The Sense
lin current, 130~ at 25°C, flows through R2 into the
;ense pin. The output voltage can be calculated using the

L7lJ!J~

VOUP 3.3V(1

+~)+ ([SENSE +R2)

VSENSE = 3.3V
ISENSE = 1301lA AT 25°C

OUTPUT RANGE = 3.3VTO 14V

Figure 2. Adjustable Operation

4-97

LT1528
APPLICATions InFoRmATion
The LT1S28 is specified with the Sense pin tied to the
Output pin. This sets the output voltage to 3.3V. Specifications for output voltage greater than 3.3V will be proportional to the ratio of the desired output voltage to 3.3V
(VouT/3.3V). For example, load regulation for an output
current change of 1mA to 1.SA is -SmV (typical) at VOUT
= 3.3V. At VOUT= 12V, load regulation would be:
(12V/3.3V) x (-SmV) = (-18mV)
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components:
1. Output current multiplied by the input/output voltage
differential, lOUT x (VIN - VOUT) , and
2. Ground pin current multiplied by the input voltage,
IGND XVIN.
The Ground pin current can be found by examining the
Ground Pin Current curves in the Typical Performance
Characteristics. Power dissipation will be equal tothe sum
of the two components listed above.
The LT1S28 has internal thermal limiting designed to
protect the device during overload conditions. For
continuous normal load conditions the maximum junction
temperature rating of 12SoC must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction-to-ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Experiments have shown that the
heat spreading copper layer does not have to be electrically connected to the tab of the device. The PC material
can be very effective at transmitting heat between the pad
area, attached to the tab of the device, and a ground or
power plane either inside or on the opposite side of the
board. Although the actual thermal resistance of the PC
material is high, the length/area ratio of the thermal
resistor between layers is small. Copper board stiffeners
and plated through holes can also be used to spread the
heat generated by power devices.

4-98

Table 1alists thermal resistance for the DO package. For the
TO-220 package (Table 1b) thermal resistance is given for
junction-to-case only since this package is usually mounted
to a heat sink. Measured values of thermal resistance for
several different copper areas are listed for the DO package.
All measurements were taken in still air on 3/32" FR-4 board
with one ounce copper. This data can be used as a rough
guideline in estimating thermal resistance. The thermal
resistance for each application will be affected by thermal
interactions with other components as well as board size and
shape. Some experimentation will be necessary to determine
the actual value.
Table 1a. Q-Package, 5-Lead DD
COPPER AREA
TOPSIDE"

BACKSIDE

THERMAL RESISTANCE
BOARD AREA (JUNCTION·TO·AMBIENT)

2500 sq mm 2500sq mm
1000 sq mm 2500sq mm

2500 sq mm
2500 sq mm

23°C/W

125 sq mm 2500sq mm

2500 sq mm

33°C/W

25°C/W

'Device is mounted on topside.

Table 1b. T Package, 5-Lead TO-220
Thermal Resistance (Junction-to:Case)

2.5°CNoI

Calculating Junction Temperature
Example: Given an output voltage of 3.3V, an inputvoltage
range of 4.SV to S.SV, an output current range of OmA to
SOOmA and a maximum ambient temperature of SO°C,
what will the maximum junction temperature. be?
The power dissipated by the device will be equal to:
IOUT(MAX) x (VIN(MAX) - VOUT) + [IGND x VIN(MAX)l
where,
IOUT(MAX) = SOOmA
VIN(MAX) = S.SV
IGND at (lOUT = SOOmA, VIN = S.SV) = 4mA
so,
P= SOOmA x (S.SV - 3.3V) + (4mA x S.SV) = 1.12W
If we use a DD package, the thermal resistance will be in
the range of 23°C/W to 33°C/W depending on the copper
area. So the junction temperatLire rise above ambient will
be approximately equal to:
1.12W x 28°C/W = 31.4°C

LTl528

APPLICATions InFoRmATion
The maximum junction temperature will be equal to the
maximum junction temperature rise above ambient plus
the maximum ambient temperature or:

different processors. This application allows the output
voltage to be jumper selectable.
Protection Features

TJMAX = 50°C + 31.4°C = 81.4°C
Output Capacitance and Transient Performance
The L11528 is designed to be stable with a wide range of
output capacitors. The minimum recommended value is
3.3W with an ESR of 2Q or less. The LT1528 output
transient response will be a function of output capacitance. See the Transient Response curves in the Typical
Performance Characteristics. Larger values of output capacitance will decrease the peak deviations and provide
improved output transient response for larger load transients. Bypass capacitors, used to decouple individual
components powered by the L11528, will increase the
effective value of the output capacitor.
Microprocessor Applications
The LT1528 has been optimized for microprocessor
applications, with the fastest transient response of current
PNP low dropout regulators. In orderto deal with the large
load transients associated with current generation
microprocessors, output capacitance must be increased.
fo meet worst-case voltage specifications for many popular
processors, four 47W solid tantalum surface mount
~apacitors are recommended for decoupling at the
microprocessor. These capaCitors should have an ESR of
:lpproximatelyO.1 Qto O.2Qto minimize transient response
under worst-case load deltas. The Typical Application
:;hows connections needed to supply power for several

The LT1528 incorporates several protection features, such
as current limiting and thermal limiting, in addition to the
normal protection features associated with monolithic
regulators. The device is protected against reverse input
voltages and reverse voltages from output to input.
Current limit protection and thermal overload protection
are intended to protect the device against overload conditions. For normal operation the junction temperatures
should not exceed 125°C.
The input of the device will withstand reverse voltages of
15V. Currentflow into the device will be limited to less than
1mA (typically less than 1OO~) and no negative voltage
will appear at the output. The device will protect both itself . .
and the load.
..
The Sense pin is internally clamped to one diode drop
below ground.lfthe Sense pin is pulled below ground, with
the input open or grounded, current must be limited to less
than 5mA.
Several different input/output conditions can occur in
regulator circuits. The output voltage may be held up while
the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. Current flow back
into the output will vary depending on the conditions.
Many circuits incorporate some form of power management. The following information summarized in Table 2
will help optimize power usage.

rable 2. Fault Conditions
INPUT PIN

SHDN PIN

OUTPUT/SENSE PINS

< VOUT (Nominal)

Open (High)

Forced to VOUT (Nominal)

< VOUT (Nominal)

Grounded

Forced to VOUT (Nominal)

Open
Open
::; O.BV
::;O.BV

Open (High)
Grounded
Open (High)
Grounded

> 1.5V

Open (High)
Grounded

>1V
>1V
::;OV
::;OV
::;OV

-15Vffi 600
a::
~ 500

'"5

400

5

300

0..

o

When the input ofthe LT1528 is forced to avoltage below
its nominal output voltage and its output is held high, the
output current will follow the curve shown in Figure3. This
can happen ifthe input ofthe LT1528 is connected to alow
voltage and the output is held up by a second regulator
circuit. When the input pin is forced below the Output pin
or the Output pin is pulled above the input pin, the input
current will typically drop to less than 2j.iA (see Figure 4).
The state of the Shutdown pin will have no effect on the
reverse output current when the output is pulled above the
input.

~IN

VOU~= 3.3~

T1 = 2J o C.
=IOV
VOUT =VSENSE
CURRENT FLOWS
I TO EVI E

,/

200
100

o ./
o 1 2

V

1/

3 4 5 6 7 8
OUTPUT VOLTAGE (V)

9 10

o

-

V

o

0.5

--

I)
,/

1.0 1.5 2.0
2.5
INPUT VOLTAGE (V)

LT152a·FOS

Figure 3. Reverse Output Current

3.0

3.5

LT1528·f04

Figure 4. Input Current

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC'"1265

High Efficiency Step-Down Switching Regulator

LTC1266
LT1521

Synchronous Switching Controller

>90% Efficient 1A, 5V to 3.3V Conversion
>90% Efficient High Current Microprocessor Supply

300mA Micropower Low Dropout Regulator

151JA Quiescent Current

LT1584

7A Low Dropout Fast Transient Response Regulator

For High Performance Microprocessors

LT1585

4.6A Low Dropout Fast Transient Response Regulator

For High Performance Microprocessors

4-100

f=Ar\
L1n
U \II(.
£7TECHNOLOG~~---3A--L-o-w--D-ro-p-o-u-t-R-e-g-U-I-a-to-r-s
LT1529
LT 1529-3.3/LT 1529-5

with Micropower
Quiescent Current
and Shutdown
FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•
•
•
•

The LT®1529/LT1529-3.3/LT1529-5 are 3A low dropout
regulators with micropower quiescent current and shutdown. The devices are capable of supplying 3A of output
current with a dropout voltage of O.6V. Designed for use
in battery-powered systems, the low quiescent current,
50J.IA operating and 16J.IA in shutdown, make them an
ideal choice. The quiescent current is well controlled; it
does not rise in dropout as it does with many other low
dropout PNP regulators.

Dropout Voltage: O.6V at lOUT = 3A
Output Current: 3A
Quiescent Current: 50~
No Protection Diodes Needed
Adjustable Output from 3.BV to 14V
3.3V and 5V Fixed Output Voltages
Controlled Quiescent Current in Dropout
Shutdown IQ =16J.IA
Stable with 3.3J.1f Output Capacitor
Reverse Battery Protection
No Reverse Current
Thermal Limiting

APPLICATions
•
•
•
•

High Efficiency Regulator
Regulator for Battery-Powered Systems
Post Regulator for Switching Supplies
5V to 3.3V Logic Regulator

Other features of the LT1529 /LT1529-3.3/L T1529-5 include the ability to operate with small output capacitors.
They are stable with only 3.3J.1f on the output while most . .
older devices require between 1OJ.lf and 1OOJ.lf for stabil- . .
ity. Small ceramic capacitors can be used, enhancing
manufacturabiltiy. Also the input may be connected to
voltages lower than the output voltage, including negative
voltages, without reverse current flow from output to
input. This makes the LT1529/LT1529-3.3/LT1529-5 ideal
for backup power situations where the output is held high
and the input is at ground or reversed. Under these
conditions, only 16J.IA will flow from the output pin to
ground. The devices are available in 5-lead TO-220 and
5-lead DO packages.
D; LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn

Dropout Voltage
0.6

5V Supply with Shutdown

0.5

V

0.4

//

~

§; 0.3
f-

:::J

~

0::
Cl

VSJiijjj (PIN 4)

OUTPUT

<0.25
>2.8
NC

OFF
ON
ON

0.2

V

./

~

~

L

/

V

If

0.1

o0

0.5

1.0
1.5
2.0
OUTPUT CURRENT (A)

2.5

3.0

4-101

LT1529
LT 1529-3.3/LT 1529-5
ABSOLUTE mAXimum RATinGS
Input Voltage ...................................................... ±15V*
Output Pin Reverse Current .............. ,.................. 10mA
Sense Pin Current.. .............................................. 10mA
Adjust Pin Current ............................................... 10mA
Shutdown Pin Input Voltage (Note 1) ........ 6.5V, - 0.6V

Shutdown Pin Input Current (Note 1) .................... 5mA
Output Short-Circuit Duration ......................... Indefinite
Storage Temperature Range ................ -65°C to 150°C
Operating Junction Temperature Range ... O°C to 125°C
Lead Temperature (Soldering, 10 sec) .... ,............. 300°C
'For applications requiring input voltage ratings greater than 15V. contact
the factory.

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

FRONT VIEW

TAB IS
GND

fIr
o

4

3
2
1

Q PACKAGE

SHDN
GND
SEN.SElADJ'
OUTPUT

LT1529CQ
LT1529CQ-3.3
LT1529CQ-5

5-LEAD PLASTIC DD PAK
'PIN 2=SENSE FOR LT1529-3.3/LT1529-5
=ADJ FOR LT1529
9JA= 30'C/W

ORDER PART
NUMBER

FRONT VIEW

'~:,IO

VIN
: SHDN

II

11

:

~~~SElADJ'

OUTPUT

TPACKAGE
5-LEAD PLASTIC TO-220
'PIN 2=SENSE FOR LT1529-3.3/LT1529-5
=ADJ FOR LT1529

LT1529CT
LT1529CT-3.3
LT1529CT-5

9JA= 50'C/W

Consult factory for Industrial or Military grade parts.

ELECTRICAL CHARACTERISTICS
PARAMETER
Regulated Output Voltage
(Note 2)

Line Regulation

Load Regulation

Dropout Voltage
(Note 4)

4-102

CONDITIONS
LT1529-3.3

VIN = 3.8V. lOUT = 1rnA. TJ = 25°C
4.3V < VIN < 15V. lmA < lOUT < 3A
LT1529-5
VIN = 5.5V. lOUT = 1rnA. TJ = 25°C
6V  75°C. This is due to internal
circuitry designed to compensate for leakage currents in the output
transistor at high temperatures. This allows quiescent current to be
minimized at lower temperatures, yet maintain output regulation at high
temperatures with light loads. See quiescent current curve in typical
performance characteristics.
Note 7: Adjust pin bias current flows into the adjust pin.
Note 8: Shutdown pin current at VSHDN = OV flows out of the shutdown pin.
Note 9: Quiescent current in shutdown is equal to the sum total of the
shutdown pin current (5W1) and the ground pin current (1 OflA).
Note 10: Reverse output current is tested with the input pin grounded and
the output pin forced to the rated output voltage. This current flows into
the output pin and out of the ground pin.

4-103

LT1529
LT 1529-3.3/LT 1529-5
TYPICAL PERFORmAnCE CHARACTERISTICS
Guaranteed Dropout Voltage

Dropout Voltage
0.8

1.0

",-

0.9
0.8

~

0]

'"~

0.6

> 0.5

{'

>-

"-

0.4

rr

0

c:: 0.3
0

./

V

p

0

:::J
0

0.7

./

E: ILOAD = 100mA
A: ILOAD = 3A
B: ILOAD = 1.5A
F: ILOAD = 10mA
C: ILOAD = 700mA
0: ILOAD = 300mA

VIN = 6V
RL = 00

0.6

'"~

0.5

>

0.4

13

0.3

c.J

z>-

w

V

0

Y

~

c::

>-

:::J
0

"0

f2

o

o

0.5

OL-~

1.0
1.5
2.0
OUTPUT CURRENT (A)

2.5

__

-50 -25

3.0

~

__

o

_ _~_ _L-~

100

125

-50 -25

LT1529-5
Quiescent Current

250
ILOAD = 0
RL:= 00

\

~~ ~~~
c::

11\

13

~ 100

1\

~ 100

c.J

75

~

75

d

50

d

50

o

o

1

2

3 4 5 6 7
INPUT VOLTAGE (V)

8

9

\

o
o

10

~

75

d

50

2

3 4 5 6 7
INPUT VOLTAGE (V)

\

\

_ VSHDN -OV

25 -

./
1

\

~ 100

c.J

25 - - --i ~ VSHDN-OV

VSHDN - OV

25

VSHDN = OPEN (HIGH)

125

>-

\

c.J

~

8

9

o
o

10

I I

\

0:

13

00

VOUT= VADJ

\

~ 150

VSHDN = OPEN (HIGH)

125

>-

RL:=

~

~~ ~~~

I \

c::

VSHDN = OPEN (HIGH)

125

125

ILOAD = 0

225

~ 150

>-

100

250
ILOAD = 0
RL==

225

~~ ~~~

~ 150

-

0
25
50
75
TEMPERATURE ('C)

LT1529
Quiescent Current

250

225

VSHDN = OV

......
L-~

0
25
50
75
TEMPERATURE (0C)

./

50

d

0.1
0= TEST POINT

LT1529-3.3
Quiescent Current

13

VSHDN = OPEN

::;

0.2

0.2
0.1

I
I

150

>~ 100

0

c::

1

~ 200

~

......-

/
/

Quiescent Current
250

1

2

3 4 5 6 7
INPUT VOLTAGE (V)

8

9 10

LT1529·C;05

LT1529-3.3
Output Voltage

LT1529-5
Output Voltage

LT1529
Adjust Pin Voltage

5.100 r---,---.--,---,---,----,---,

3.400

3.850 r---,--.--,--.----,----,---,
ILOAD = lmA
3.825 t---+--+--+---+---f---t----j

ILOAD = lmA
_

3.375

5.075

t---+---+---+---+---t---t----j

3.350

_ 5.050

t---+---+---+---+---t---t----j

2:-

~ 3.325
§; 3.300
>-

~ 3.275

w

~ 5.025

_f..-- f.--

§; 5.000

V

~

F=t=+-t-4=~::::t::~

~

4.975

t---+---+---+---+---t---t----j

6

4.950

t---+---+---+---+---t---t----j

3.225

4.925

t---+---+---+---+---t---t----j

3.200
-50 -25

4.900 L--'-__-'-__L-~_ _~_ _L--...J
-50 -25
25
50
75 100 125
TEMPERATURE eC)

:::J

o

--

2:-

3.250

4-104

25
50
75
TEMPERATURE (OC)

1--+--+-+---+--+---1---1
~ 3.775 t---+---+---+---+---f---t----i
~ 3.750 b~---..j..-f_-+"""F=F"":1
~ 3.800

ii:

t;;

3.725

t---+---+--+---+--f---t----j

3.700

t---+--+---+---+---f---t----j

3.675

t---+--+--+---+---f--t----j

:::J

100

125

~

3.650 '----'-_-'-__-'---'-__-'-_'----...J
-50 -25
25
50
75 100 125
TEMPERATURE ('C)

LT1529
LT 1529-3.3/LT 1529-5
rYPICAl PERFORmAnCE CHARACTERISTICS
LT1529-5
Ground Pin Current

LT1529-3.3
Ground Pin Current
5.0

5.0

TJ = 25°C
VOUT = VSENSE
'FORVOUT=~ -

4.5

§

4.0
, 3.5

2.5

I

2.0
1.5

/

--

f" 1-

0.5

o

/ RLOAD = 3300
ILOAD = 10mA'
T II
RLOAD = 11n
-ILOAD = 300mA'
RLOAD - 330
lLOAD = 1OOmA'

1

L1'

1.0

.l

I
I
RLOAD = 6.60
lLOAD = 500mA'

r- r-

I

3.0

TJ = 25'C
4.5 VOUT = VSENSE
;;;: 4.0 'FOR VOUF 5V I-.§.
I- 3.5
t5
R:OAD 50bo
a:: 3.0

I I I

1

'"a:
c

'"
:::>

'"
'"
0:

8

2.0
1.5
1.0

o

o

9 10

5.0

lLOAD = 500mA'

lL ""-

2

3

4

5

I'-..

:::>

u

z

a:

RLOAD = 16.60
lLOAD = 300mA'
I
I
RLOAD = 500
ILOAD = 100mA'

c

z

:::>

1'-.::1"

r

1

TJ = 25'C
4.5 VOUF VADJ
;;;: 4.0 'FOR VOUT=
3.75V
.§.
I- 3.5
z
l:l!
3.0
0:

RL~AD =11Ori

~

"~:'~~i
t_-

2.5

0.5
3 4 5 6 7
INPUT VOLTAGE (V)

2

~

0:

:::>
u

II
o

LT1529
Ground Pin Current

6

7

8

'"
'"
a::

/

2.5

I

2.0
1.5

/f

0.5

o

o

9 10

1

"

RL~AD ~ 7.511l

ILOAD = 500mA'

RLOAD = 3750l'-t-l
/ILOAO = 10mA'i
RLOAO = 12.5U
ILOAD = 300mA'

I

RLOAD = 380
ILOAD = 100mA'

.........

"""'"

2

3 4 5 6 7
INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

J.

--~J.

V

1'/

1.0

I I J

J io-...

8

10

9

LT1529-Gll

LT1529-3.3
Ground Pin Current

LT1529-5
Ground Pin Current

100

TJ = 25°C
'FOR VOUT = 3.3V
90 VOUT = VSENSE

......

80
70

I

60

r-....

1/

50

100

I I

RL6AD~1.1L

ILOAD = 3A'

Ii-+I 11

40

1/ILOAD=700mA~

J

RL~AD ~ 2.2h ILOAD -1.5A' _

/

20
10

o

o

.t:..-1

2

/11

3 4 5 6 7
INPUT VOLTAGE (V)

TJ = 25'C
90 Vour= VSENSE I-;;;: 80 'FOR VOUF 5V
.§.
70
II ,I
t5
RLOAO = 7.1n
0:
60
a::
ILOAO = 700mA'
:::>
u
50

I I I

1

'"a:c
'":::>

'"
'"
0:

I

40

/

30
20

I

10

o
o

9 10

8

r-

~

RL~AD l1.7~ -

~AD=3A'

_

r--- r-

/

t-:::
1

2

TJ = 25'C
90 VOUF VADJ
;;;: 80 'FOR Vour= 3.75~

S
I-

t5
0:

:::>

'-'

z

1\

a:
c

-i'"'"'"

100

0:

f/..

RLOAD = 4.7n

30

LT1529
Ground Pin Currenl

.\

RLOAD = 3.30 lLOAD = 1.5A' _

3 4 5 6 7
INPUT VOLTAGE (V)

'":::>
'"
'"
0::

70
60

/

50

II

40
30

l ....... V

10
8

9

o

10

~OAD=3A'

'" 1I"""t-t-=
1J
RLOAD = 5.30
-ILOAD = 700mA~

I RL~AD ~ 2.5Q -

V

20

I I I
RLOAO = 1.250

1/

lLOAO=1.5A' _

I

j.t,.o

1

2

3 4 5 6 7
INPUT VOLTAGE (V)

8

10

9

lT1529·Q13

Shuldown Pin Threshold
(On-Io-OII)

Ground Pin Current
2.0

100

VIN = 3.75V (LT1529)
VIN = 3.3V (LT1529-3.3)
VIN = 5V (LT1529-5)
DEVICE IS OPERATING
IN DROPOUT

90
80
70

I/,

~J=25OC)t

50
TJ = 125°C

40

h

30
20

o

-

0.5

W

~

L7lJ!J~

~ 1.6

~ 1.6

c

--' 1.4

'"ffl
:I:

0:
:I:
I-

1.2

..........

:--...

1.0

'":::>c

0.6



:I:


<.:>

,....

l-

s:

a:

<.:>
~

c::

0

:::>

~

«

.........

2l 100

o

125

"r-....

ti; 150

o

-- r--

50

/

U)

100

r-...

z 200

0

0
25 50
75
TEMPERATURE (0C)

I'..

250

Ol

:I:

-50 -25

350

~ 300

15

;;;
z
c:: 10
z
3:

o

VADJ = VOUr= 3.75V

450



75

~

I

1

~
50

25

!/

/I

o

-50 -25

25 50
75
TEMPERATURE (OC)

100

f-- f--

1

/

o

----

VIN = 7V
VOUT = OV

o
o

125

J

oL--L__L - - L__L - - L__L---"

-50 -25

5
INPUT VOLTAGE (V)

25 50
75
TEMPERATURE (OC)

100

12

LTl52Q'G24

Reverse Output Current

Ripple Rejection

100
TJ = 25°C, VIN = OV
Vour = VSENSE
(LTI529-3.3ILT1529-5)
VOUT = VADJ (LT1529)
CURRENT FLOWS
INTO DEVICE

90
80

~

70

Z

60

I-

tl!
a:

:::>
<.:>

50

I-

40

:::>
:::>
0

60

~

>=

~

Ul
a:
w

~~

30

LTI529-3.3

20

&- .....

~

"-

a:

./

A9 ...... VLTI529-5

10

o

o

2

3 4 5 6 7 8
OUTPUT VOLTAGE (V)

910
lTl529'G25

4-106

56
54

(VIN - VOUT)AVG = 1V
VRIPPLE = 0.5Vp_p
ILOAD = 1.5A
f = 120Hz

.......

80

~

70

0

60

~

50

>=

r-.....

Ul
a:

w
--'
""-

I'\.

52

lour = 1.5A
VIN = VOUT (NOMINAL) + 1
+ 50mVRMS RIPPLE

90

z

I"r-....

a:

CouT=47~F

~LI~TANT

IIIII"\{

40

CouT=3.3~F

30

Isr~ml[ANL

20
50

.#"~
1

58

r- -....

z

0

LT1529

"-

I-

Ripple Rejection
100

62

48
-50 -25

0
25 50
75
TEMPERATURE (OC)

100

125

10

11111111

I

o

11111111

I

10

100

Ik
10k
FREQUENCY (Hz)

10(
LT1529'Q27

LT1529
LT 1529-3.3/LT 1529-5
rYPICAL PERFORmAnCE CHARACTERISTICS
load Regulation

--

l T1529-5 Transient Response

N T1529-5
r-:t::-..
LT15J;:S
LT1529

;::.-,l'-..

i -10
!

K

w

0.2

~~

0.1
0

"'~2:.
~~

l T1529-5 Transient Response

VIN = 6V
l
GIN = 3.3~F TANT
GOUT = 47~FTANT

.11

1\

w

"'~~

Jv

§;Q

~~

0.1

VIN = 6V
GIN = 1Ol'FTANT
GOUT = 4.71'F TANT

0

IIAI
IV

~ CE;-O.1

~~-O.1

:::>c

'"

'"

-0.2

-0.2

J\

1l'..

g

! -15

i
-20

0.2

-25
-50 -25

0255075
TEMPERATURE (0C)

ffi

I
I

VIN = VOUT (NOMINAL) + 1V
AI LOAD = 1OOmA to 3A
VADJ =VOUT
100

125

o

a:
a:

:::>
u

I

c

«

9

100 200 300 400 500 600 700 800 9001000
TIME (I's)

o

I

20 40 60 80 100 120 140160180200
TIME (I's)

LT15290G29

tin FunCTions
lOUT (Pin 1): Output Pin. The output pin supplies powerto
le load. Aminimum output capacitor of 3.31JF is required
) prevent oscillations. Larger values will be required to
ptimize transient response for large load current deltas.
;ee the Applications Information section for further inforlation on output capacitance and reverse output characlristics.

;ENSE (Pin 2): Sense Pin. For fixed voltage versions ofthe
T1529 (LT1529-3.3, LT1529-5) the sense pin is the input
) the error amplifier. Optimum regulation will be obtained
t the point where the sense pin is connected to the output
in. For most applications the sense pin is connected
irectly to the output pin at the regulator. In critical
pplications small voltage drops caused by the resistance
Rp) of PC traces between the regulator and the load,
,hich would normally degrade regulation, may be elimiated by connecting the sense pin to the output pin at the
lad as shown in Figure 1 (Kelvin Sense Connection). Note
latthe voltage drop across the external PC traces will add
I the dropout voltage of the regulator. The sense pin bias
urrent is 15~ at the nominal regulated output voltage.
his pin is internally clamped to -O.6V (one VBE).

.DJ (Pin 2): Adjust Pin. For the LT1529 (adjustable
ersion) the adjust pin is the input to the error amplifier.
his pin is internally clamped to 6V and -O.6V (one VBE).

Figure 1. Kelvin Sense Connection

This pin has a bias current of 150nA which flows into the
pin. See Bias Current curve in the Typical Performance
Characteristics. The adjust pin reference voltage is equal
to 3.75V referenced to ground.
SHDN (Pin 4): Shutdown Pin. This pin is used to put the
device into shutdown. In shutdown the output of the
device is turned off. This pin is active low. The device will
be shut down if the shutdown pin is actively pulled low.
The shutdown pin current with the pin pulled to ground will
be 6~. The shutdown pin is internally clamped to 7V and
- O.6V (one VBE). This allows the shutdown pin to be driven
directly by 5V logic or by open-collector logic with a pullup resistor. The pull-up resistor is only required to supply
the leakage current of the open-collector gate, normally
several microamperes. Pull-up current must be limited to
amaximum of 5mA. Acurve of shutdown pin inputcurrent
as a function of voltage appears in the Typical Perfor-

4-107

LI Ib2Y

LT1529-3.3/LT 1529-5
Pin FunCTions
mance Characteristics. If the shutdown pin is not used it
can be left open circuit. The device will be active, output on,
if the shutdown pin is not connected.
VIN (Pin 5): Input Pin. Power is supplied to the device
through the input pin. The input pin should be bypassed to
ground if the device is more than six inches away from the
main input filter capacitor. In general, the output impedance of a battery rises with frequency so it is advisable to
include a bypass capacitor in battery-powered circuits. A

bypass capacitor in the range of 1~ to 1O~ is sufficient
The LT1529 is designed to withstand reverse voltages or
the input pin with respect to ground and output pin. In the
case of a reversed input, which can happen if a battery i~
plugged in backwards, the LT1529 will act as if there is (
diode in series with its input. There will be no reverse
current flow into the LT1529 and no reverse voltage wil
appear at the load. The device will protect both itself anc
the load.

APPLICATions InFoRmATion
The LT1529 is a 3A low dropout regulator with micropower quiescent current and shutdown capable of
supplying 3A of output current at a dropout voltage of
O.6V. The device operates with very low quiescent current
(50~). In shutdown the quiescent current drops to only
16~. In addition to the low quiescent current the LT1529
incorporates several protection features which make it
ideal for use in battery-powered systems. The device is
protected against reverse input voltages. In battery backup
applications where the output can be held up by a backup
battery when the input is pulled to ground, the LT1529 acts
like it has a diode in series with its output and prevents
reverse current flow.
Adjustable Operation
The adjustable version of the LT1529 has an output
voltage range of 3.75Vto 14V. The output voltage is set by
the ratio of two external resistors as shown in Figure 2. The
device servos the output voltage to maintain the voltage at
the adjust pin at 3.75V. The current in R1 is then equal to
3.75V/R1. The current in R2 is equal to the sum of the
current in R1 and the adjust pin bias current. Theadjust pin
bias current, 150nA at 25°C, flows through R2 into the
adjust pin. The output voltage can be calculated according
to the formula in Figure 2. The value of R1 should be less
than 400k to minimize errors in the output voltage caused
by the adjust pin bias current. Note that in shutdown the
output is turned off and the divider current will be zero.
Curves of Adjust Pin Voltage vs Temperature and Adjust

4-108

VOUP3.75V(1

+1*)+ (lAOJ x R2)

VADJ = 3.75V
IAOJ = 150nA AT 25'C
OUTPUT RANGE = 3.3V TO 14V

Figure 2. Adjustable Operation

Pin Bias Current vs Temperature appear in the Typica
Performance Characteristics. The reference voltage at thE
adjust pin has a positive temperature coefficient of ap·
proximately 15ppm/oC. The adjust pin bias current has (
negative temperature coefficient. These effects will tend tc
cancel each other.
The adjustable device is specified with the adjust pin tiec
to the output pin. This sets the output voltage to 3.75V
Specifications for output voltage greaterthan 3. 75V will be
proportional to the ratio of the desired output voltage tc
3.75V (Vour/3.75V). For example: load regulation for ar
output current change of 1mA to 3A is -O.5mV typical al
Your =3.75V. At Your =12Vj load regulation would be:
12V )
( 3.75V
x (-O.5mv) = (-1.6mV)

LT1529
LT 1529-3.3/ LT 1529-5
APPLICATions InFoRmATion
rhermal Considerations

tance. The thermal resistance for each application will be
affected by thermal interactions with other components as
well as board size and shape. Some experimentation will
be necessary to determine the actual value.

rhe power handling capability of the device will be limited
lY the maximum rated junction temperature (12S0C). The
lower dissipated by the device will be made up of two
:omponents:

Table 1. 0 Package, 5-Lead DO

I. Output current multiplied by the inpuVoutput voltage
differential: lOUT x (VIN - VOUT), and

TOPSIDE'

) Ground pin current multiplied by the input voltage:
IGND x VIN·
-he ground pin current can be found by examining the
iround Pin Current curves in the Typical Performance
;haracteristics. Power dissipation will be equal to the sum
)f the two components listed above.
·he LT1S29 series regulators have internal thermal limitng designed to protect the device during overload condiions. For continuous normal load conditions the maxinum junction temperature rating of 12SoC must not be
ixceeded. It is important to give careful consideration to
III sources of thermal resistance from junction to ambient.
Idditional heat sources mounted nearby must also be
:onsidered.
:or surface mount devices heat sinking is accomplished
Iy using the heat spreading capabilities of the PC board
Ind its copper traces. Experiments have shown that the
leat spreading copper layer does not need to be electri:ally connected to the tab of the device. The PC material
:an be very effective at transmitting heat between the pad
.rea, attached to the tab of the device, and a ground or
lower plane layer either inside or on the opposite side of
he board. Althoughthe actual thermal resistance ofthe PC
naterial is high, the length/area ratio of the thermal
esistor between layers is small. Copper board stiffeners
.nd plated through-holes can also be used to spread the
leatgenerated by power devices.
'he following tables list thermal resistances for each
lackage. For the TO-220 package, thermal resistance is
iven for junction-to-case only since this package is
sually mounted to a heat sink. Measured values of
lermal resistance for several different copper areas are
sted forthe DD package. All measurements were taken in
till air on 3/32" FR-4 board with 1-oz copper. This data can
e used as a rough guideline in estimating thermal resis-

COPPER AREA
BACKSIDE

2500 sq. mm 2500 sq. mm

THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
2500 sq. mm

1000 sq. mm 2500 sq. mm 2500 sq. mm
125 sq. mm

2500 sq. mm

2500 sq. mm

23°C/W
25°C/W
33°C/W

• Device is mounted on topside.

T Package, 5-Lead TO-220
Thermal Resistance (Junction-to-Case) = 2.5°CIW

Calculating Junction Temperature
Example: Given an output voltage of 3.3V, an input voltage
range of 4.SV to S.SV, an output current range of OmA to . , .
SOOmA, and a maximum ambient temperature of SO°C, . .
what will the maximum junction temperature be?
The power dissipated by the device will be equal to:
IOUT(MAX) x (VIN(MAX) - VOUT) + (IGND x VIN(MAX))
where, IOUT(MAX) = SOOmA
VIN(MAX) = S.SV
IGND at (lOUT = SOOmA, VIN = S.SV) = 3.6mA
so,

P = SOOmA x (S.SV - 3.3V) + (3.6mA x S.SV)
= 1.12W

If we use aDD package, then the thermal resistance will be
in the range of 23°C/W to 33°C/W depending on copper
area. So the junction temperature rise above ambient will
be approximately equal to:
1.12W x 28°C/W =31.4°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
TJMAX =SO°C + 31.4°C =81.4°C
Output Capacitance and Transient Performance
The LT1S29 is designed to be stable with a wide range of
output capaCitors. The minimum recommended value is
3.3~ with an ESR of 20 or less. The LT1S29 is a

4-109

LT1529

LT 1529-3.3/LT 1529-5
APPLICATions InFoRmATion
micro power device and output transient response will be
a function of output capacitance. See the Transient Response curves in the Typical Performance Characteristics.
Larger values of output capacitance will decrease the peak
deviations and provide improved output transient response for larter load current deltas. Bypass capacitors,
used to decouple individual components powered by the
LT1529, will increase the effective value of the output
capacitor.

Protection Features
The LT1529 incorporates several protection features which
make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse input
voltages, and reverse voltages from output to input.
Current limit protection and thermal overload protection
are intended to protect the device against current overload
conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C.

output pin of an adjustable device, or the sense pin of a
fixed voltage device, is pulled below ground, with the input
open or grounded, current must be limited to less than
5mA.
In circuits where a backup battery is required, several
different inpuVoutput conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage, or is left
open circuit. Current flow back into the output will vary
depending on the conditions. Many battery-powered circuits incorporate some form of power management. The
following information will help optimize battery life. Table
2 summarizes the following information.
The reverse output current will follow the curve in Figure
3 when the input is pulled to ground. This current flows
through the device to ground. The state ·of the shutdown
pin will have no effect on output current when the input pin
is pulled to ground.
100
90
80

The input of the device will withstand reverse voltages of
15V. Currentflow into the device will be limited to less than
1rnA (typically less than 1DDIlA) and no negative voltage
will appear at the output. The device will protect both itself
and the load. This provides protection against batteries
that can be plugged in backwards.
For fixed voltage versions of the device, the sense pin is
internally clamped to one diode drop below ground. For
the adjustable version of the device, the output pin is
internally clamped at one diode drop below ground. If the

1
~
~
is

5
<>5o

70
60

TJ =25°C, Y,N =OV
VOUT =VSENSE
(LT1529-3.3JLT1529-5)
VOUT =VADJ (LT1529)
CURRENT FLOWS
INTO DEVICE
LT1529

50
40
30

20
10

LT1529-3.3

£

b

~I'"
/"

"

...... ' "LT1529-5

o ~
o 1 2 3 4

I

5 6 7 8
OUTPUT VOLTAGE (V)

9 10

Figure 3. Reverse Output Current

Table 2. Fault Conditions
SHUN PIN

OUTPUT/SENSE PINS

1V

Open

Reverse Output Current ~ 15~ Peak (See Figure 3)

Open

Grounded

>1V

Reverse Output Current ~ 15~ (See Figure 3)

::;;0.8V

Open (High)

::;;ov

Output Current = 0

::;;0.8V

Grounded

::;;OV

Output Current =0

>1.5V

Open (High)

::;;OV

Output Current = Short-Circuit Current

-15V < V,N < 15V

Grounded

::;;OV

Output Current = 0

4-110

1~

(See Figure 4)

LT1529
LT 1529-3.3/ LT 1529-5
~PPLICATlOnS

InFORmATion

I some applications it may be necessary to leave the input

the LT1529 unconnected when the output is held high.
1is can happen when the LT1529 is powered from a
ictified AC source. If the AC source is removed, then the
put of the LT1529 is effectively left floating. The reverse
Jtput current also follows the curve in Figure 3 ifthe input
n is left open. The state of the shutdown pin will have no
fect on the reverse output current when the input pin is
Jating.
I

'hen the input of the LT1529 is forced to avoltage below
) nominal output voltage and its output is held high, the
Jtput currentwill follow the curve shown in Figure 3. This
In happen if the input of the LT1529 is connected to a
scharged (low voltage) battery and the output is held up
I either abackup battery or by asecond regulator circuit.
'hen the input pin is forced below the output pin or the
Jtput pin is pulled above the input pin, the input current

will typically drop to less than 2~ (see Figure 4). The state
of the shutdown pin will have no effect on the reverse
output current when the output is pulled above the input.
VOUT = 3.3V (LT1529·3.3)
VOUT = 5V (LT1529-5)

I
LT1529·3.3

I
LT1529·5

J

a

a

---

~

~

2
INPUT VOLTAGE (V)

Figure 4. Input Current

,ELATED PARTS
IRTNUMBER

DESCRIPTION

1120A
C®1174

125mA Low Dropout Regulator with

COMMENTS

1303

Micropower Step-Up DC/DC Converter

Includes Comparator, Good for EL Displays

1376

500kHz 1.25A Step-Down DC/DC Converter

Uses Extremely Small External Components

1521

300~

Lowest 10 Low Dropout Regulator

20~

10

High Efficiency 425mA Step-Down DC/DC Converter

(7lJ!J~

Low Dropout Regulator with

15~

10

Includes 2.5V Reference and Comparator
Over 90% Efficiency, Includes Comparator

4-111

l-r
LlnL1\12
LTl 584/LTl 585/LTl 58;
~, . TECHNOLOG~fY'~-7A-,-4-,-6A-.,-3-A-....Lo-w-D-r-o-p-o-Ui
Fast Response
Positive Regulator~
Adjustable and Fixec
FEATURES

DESCRIPTiOn

•
•
•
•
•
•

The LT®1584/LT1585/LT1587 are low dropout three
terminal regulators with 7A, 4.6A and 3A output curren
capability, respectively. Design has been optimized for lov
voltage applications where transient response and mini
mum input voltage are critical. Similar to the LT1083/4/!
family, it has lower dropout voltage and faster transien
response. These improvements make it ideal for low volt
age microprocessor applications requiring a regulate!
2.5V to 3.6V output with an input supply below 7V.

Fast Transient Response
Guaranteed Dropout Voltage at Multiple Currents
Load Regulation: 0.05% Typ
Trimmed Current Limit
On-Chip Thermal Limiting
Standard 3-Pin Power Package

APPLICATions
•
•
•
•
•
•

Pentium™ Processor Supplies
PowerPC™ Supplies
Other 2.5V to 3.6V Microprocessor Supplies
Low Voltage Logic Supplies
Battery-Powered Circuitry
Post Regulator for Switching Supply

Current limit is trimmed to ensure specified output curren
and controlled short-circuit current. On-chip thermal lim
iting provides protection against any combination of over
load that would create excessive junction temperatures.

LT158517CM, LT1584/5I7CT

Adjustable

LT1585/7CM-3.3, LT1584/517CT -3.3

3.3V Fixed

LT1585CM-3.38, LT1584/5CT-3.38

3.38V Fixed

LT1585I7CM-3.45, LT1584/5/7CT -3.45

3.45V Fixed

LT1585I7CM-3.6, LT1584/517CT -3.6

3.6V Fixed

The LT1585/LT1587 are available in both the through-holl
and surface mount versions of the industry standard 3-pir
TO-220 power package. The LT1584 is available in thl
through-hole 3-pin TO-220 power package.
CT, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation.

TYPICAL APPLICATiOn

Dropout Voltage vs Output Current
1.5

3.3V, 7A, 4.6A, 3A Regulator
VIN"4.75V

-+--

1.4

_ _ _-3.3V
7A, 4.6A, 3A

~ 13
:;;!
.
~ 1.2

ffi

1.1

~

1.0

~

0.9

-

~

I--

v

I--

I-

• REQUIRED FOR STABILITY
LT1584: C2 = 221'F,
LT1585/LT1587: C2 = 10l'F
NOTE: MICROPROCESSOR APPLICATIONS WITH LOAD TRANSIENTS OF 3.8A REQUIRE
OUTPUT DECOUPLING CAPACITANCE> 1300jlfON FIXED VOLTAGE PARTS TO ACHIEVE
< 50mV OF DEVIATION FROM NOMINAL OUTPUT. CONSULT FACTORY FOR DETAILS

g;:;, O.B

~ 0.7

;;;

0.6
0.5

o

IFULL LOAD

OUTPUT CURRENT (A)
15B5TA02

4-112

LT1584/LT1585/LT1587
BSOlUTE mAXimum RATinGS
N............................................................................. 7V

Jerating Junction Temperature Range
Control Section .................................... O°C to 125°C
Power Transistor ................................. O°C to 150°C

Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

PRECOnDITiOninG
100% Thermal Limit Functional Test

ACKAGEIORDER InFORmATiOn
FRONT VIEW

[JS'"
o

2

VOUT

1

AOJ

ORDER PART
NUMBER
LT1585CM
LT1587CM

M PACKAGE
HEAD PLASTIC DO PAK

FRONT VIEW

loll

:1

: VIN
VOUT

LT1584CT
LT1585CT
LT1587CT

ADJ

T PACKAGE
HEAD PLASTIC TO-220

9JA = 30'C/W'

9JA=

FRONT VIEW

[JS'"
o

ORDER PART
NUMBER

2

VOUT

1

GND

M PACKAGE
HEAD PLASTIC DO PAK
9JA = 30'C/W'

LT1585CM-3.3
LT1585CM-3.38
LT1585CM-3.45
LT1585CM-3.6
LT1587CM-3.3
LT1587CM-3.45
LT1587CM-3.6

50'C/W

FRONT VIEW

loll

:I

: VIN

~~~T

T PACKAGE
HEAD PLASTIC TO-220

LT1584CT-3.3
LT1585CT-3.3
LT1587CT-3.3
LT1584CT-3.38
LT1585CT-3.38

LT1584CT-3.45
LT1585CT-3.45
LT1587CT-3.45
LT1584CT-3.6
LT1585CT-3.6
LT1587CT-3.6

9JA = 50'C/W

lith package soldered to 0.5 square inch copper area over backside
round plane or internal power plane. 8JA can vary from 20°C/W to
40°C/W with other mounting techniques.

Consult factory for Industrial and Military grade parts.

LEaRICAl CHAAAaERISTICS
~AMETER

erence Voltage LT1584
LT1585

:put Voltage.

LT1587
LT1584-3.3
LT1585-3.3
LT1587-3.3
LT1584-3.38
LT1585-3.38
LT1584-3.45
LT1585-3.45
LT1587-3.45
LT1584-3.6
LT1584-3.6
LT1584-3.6
LT1584-3.6

CONDITIONS
1.5V s; (VIN - VOUT) s; 3V, lOrnA S; lOUT S; 7A
1.5V S; (VIN - VOUT) S; 5.75V, 10mA S; lOUT S; 4.6A, TJ ~ 25°C
1.5V S; (VIN - VOUT) S; 5.75V, 10mA S; lOUT S; 4A, TJ < 25°C
1.5V S; (VIN - VOUT) S; 5.75V, 1OmA S; lOUT S; 3A
4.75V S; VIN S; 6.3V, OmA S; lOUT S; 7A
4.75V S; VIN S; 7V, OmA S; lOUT S; 4.6A, TJ ~ 25°C
4.75V S; VIN S; 7V, OmA S; lOUT S; 4A, TJ < 25°C
4.75V s; VIN S; 7V, OmA s; lOUT s; 3A
4.75V s; VIN s; 6.38V, OmA s; lOUT s; 7A
4.75V s; VIN s; 7V, OmA s; lOUT s; 4A
4.75V VIN 6.45V, OmA s; lOUT s; 7A
4.75V VIN 7V, OmA s; lOUT s; 4A
4.75V VIN 7V, OmA s; lOUT s; 3A
4.75V VIN 7V, OmA s; lOUT s; 6A
4.80V VIN 7V, OmA s; lOUT s; 6A
4.80V VIN 6.6V, OmA s; lOUT s; 7A
4.85V VIN 6.6V, OmA s; lOUT s; 7A

MIN

TYP

MAX

UNITS

•

1.225(-2%)

1.250

1.275 (+2%)

V

•
•

3.235 (-2%)

3.300

3.365 (+2%)

V

3.313 (-2%)

3.380 3.465 (+ 2.5%)

V

•
•••
•

3.381 (-2%)
3.400 (- 5.5%)
3.450 (-4%)
3.431 (- 4.7%)
3.481 (- 3.3%)

3.450
3.600
3.600
3.600
3.600

V
V
V
V
V

3.519 (+2%)
3.672 (+2%)
3.672 (+2%)
3.672 (+2%)
3.672 (+2%)

4-113

LT1584/LT1585/LT1587
ELEORICAL CHARAOERISTICS
PARAMETER
Output Voltage

Line Regulation
(Notes 1, 2)

Load Regulation
(Notes 1, 2, 3)

Dropout Voltage

CONDITIONS
LT158517 -3.6
LT1585/7 -3.6
LT1585-3.6
LT1585-3.6

LT1584/517
2.75V::; VIN::; 7V, lOUT = 10mA
LT1584/517 -3.3 4.75V::; VIN ::; 7V, lOUT = OmA
LT1584/5-3.38
4.75V::; VIN ::; 7V, lOUT = OmA
LT1584/517 -3.45 4.75V::; VIN ::; 7V, lOUT = OmA
LT1584/517 -3.6 4.75V::; VIN ::; lV, lOUT = OmA
LT1584/517
(VN - VOUT) = 3V, TJ = 25°C, 1OmA::; lOUT::; IFULL LOAD
LT1584/5/7 -3.3 VIN = 5V, TJ = 25°C, OmA::; lOUT::; IFULL LOAD
LT1584/5-3.38
VIN = 5V, TJ = 25°C, OmA::; lOUT::; IFULL LOAO
LT1584/517 -3.45 VIN = 5V, TJ = 25°C, OmA::; lOUT::; IFULL LOAD
LT1584/5/7 -3.6 VIN = 5.25V, TJ = 25°C, OmA ::; lOUT::; IFULL LOAD
LT158517
LT158517 -3.3
LT1585-3.38
LT158517 -3.45
LT158517-3.6
LT1585
LT1585-3.3
LT1585-3.38
LT1585-3.45
LT1585-3.6
LT1584
LT1584-3.3
LT1584-3.38
LT1584-3.45
LT1584-3.6

Current Limit
(Note 3)

LT1584
LT1584-3.3
LT1584-3.38
LT1584-3.45
LT1584-3.6
LT1584
LT1584-3.3
LT1584-3.38
LT1584-3.45
LT1584-3.6
LT1585
LT1585-3.3

LT1585-3.38
LT1585-3.45
LT1585-3.6
LT1587
LT1587-3.3
LT1587 -3.45
LT1587-3.6

4-114

4.75V::; VIN ::; 7V, OmA::; lOUT::; 3A
4.80V::; VIN ::; 7V, OmA ::; lOUT::; 3A
4.80V::; VIN ::; 7V, OmA::; lOUT::; 4A
4.85V::; VIN ::; 7V, OmA::; lOUT::; 4A

AVREF = 1%, lOUT = 3A
AVOUT = 1%, lOUT = 3A
AVour= 1%, lOUT = 3A
AVOUT = 1%, lOUT = 3A
AVOUT = 1%, lOUT = 3A
AVREF = 1%, lOUT = 4.6A, TJ ~ 25°C
AVREF = 1%, lOUT = 4A, TJ < 25°C
AVOUT = 1%, lOUT = 4.6A, TJ ~ 25°C
AVOUT = 1%, lOUT = 4A, TJ < 25°C
AVOUT = 1%, lOUT = 4A
AVOUT = 1%, lOUT = 4A
AVOUT = 1%, lOUT = 4A
AVREF = 1%, lOUT = 6A
AVOUT = 1%, lOUT = 6A
AVOUT = 1%, lOUT = 6A
AVOUT = 1%, lOUT = 6A
AVOUT = 1%, lOUT = 6A
TJ ~ 25°C
TJ < 25°C
AVREF = 1%, lOUT = 7A
AVOUT = 1%, lOUT = 7A
AVOUT = 1%, lOUT = 7A
AVOUT = 1%, lOUT = 7A
AVOUT = 1%, lOUT = 7A
(VIN - VOUT) = 3V
(VIN - VOUT) = 3V
(VIN - VOUT) = 3V
(VIN - VOUT) = 3V
(VIN - VOUT) = 3V
(VIN - VOUT) = 5.5V
(VIN - VOUT) = 5.5V
TJ ~ 25°C
TJ < 25°C
(VIN (VIN (VIN (VIN (VIN (VIN (VIN -

VOUT) = 5.5V
VOUT) = 5.5V
VOUT) = 5.5V
VOUT) = 5.5V
VOUT) = 5.5V
VO UT) = 5.5V
VOUT) = 5.5V

UNIT:

MIN

TYP

MAX

3.474 (- 3.5%)
3.528 (-2%)
3.450 (-4%)
3.492 (-3%)

3.600
3.600
3.600
3.600

3.672 (+2%)
3.672 (+2%)
3.672 (+2%)
3.672 (+2%)

0.005

0.2

~

0.05
0.05

0.3
0.5

~
~

•

1.150

1.300

•

1.200

1.400

••

1.200
1.200

1.300
1.350

•

1.250

1.400

•••
•
•
•

•

7.100

8.250

••

4.600
4.100

5.25
5.25

•

4.100

4.750

•

3.100

3.750

I
I
I
I

,

I

LTl 584/LTl 585/LT1587
ELECTRICAL CHARAOERISTICS
~ARAMETER
~djust

Pin Current
~djust Pin Current
~hange (Note 3)
lIIinimum
_oad Current
)uiescent Current

~ipple

Rejection

rhermal Regulation

CONDITIONS
LT1584/5/7
LT1584
LT1585/7
LT1584/5/7

1.5V::; (VIN- VOUT)::; 3V, 10mA::; lOUT::; IFULLLOAD
1.5V::; (VIN - VOUT)::; 5.75V, 10mA::; lOUT::; IFULL LOAD
1.5V::; (VIN - VOUT) ::; 5.75V

LT1584/5/7 -3.3
LT1584/5-3.38
LT1584/5/7-3.45
LT1584/5/7 -3.6
LT1584
LT1584-3.3
LT1584-3.38
LT1584-3.45
LT1584-3.6
LT1585

VIN = 5V
VIN = 5V
VIN = 5V
VIN= 5V
I = 120Hz, COUT = 25~ Tan!., (VIN - VOUT) = 2.5V, loup 7A
I = 120Hz, COUT= 25~ Tan!., VIN = 5.8V, IOUF 7A
I = 120Hz, COUT = 25~ Tan!., VIN = 5.88V, lOUT = 7A
I = 120Hz, COUT = 25~ Tan!., VIN = 5.95V, lOUT = 7A
I = 120Hz, Coup 25~Tan!., V1N = 6.1V, loup 7A
I = 120Hz, COUT = 25~ Tan!., (VIN - VOUT) = 3V,
lOUT = 4.6A, TJ ~ 25°C
I = 120Hz, COUT = 25~ Tan!., (VIN - VOUT) =3V,
lOUT =4A, TJ< 25°C
LT1585-3.3
I =120Hz, COUT =25~ Tan!., VIN =6.3V,
lOUT = 4.6A, TJ ~ 25°C
I =120Hz, COUT =25~ Tant., VIN =6.3V,
lOUT =4A, TJ < 25°C
LT1585-3.38
I =120Hz, COUT =25~ Tan!., VIN =6.38V, lOUT =4A
LT1585-3.45
I =120Hz, COUT =25~ Tan!., VIN =6.45V, lOUT =4A
LT1585-3.6
I =120Hz, COUT =25~ Tan!., VIN =6.6V, lOUT =4A
LT1587
I =120Hz, COUT = 25~ Tan!., (VIN - VOUT) =3V, lOUT =3A
LT1587-3.3
f =120Hz, COUT =25~ Tan!., VIN =6.3V, lOUT =3A
LT1587-3.45
1= 120Hz, COUT = 25~ Tan!., VIN = 6.45V, lOUT =3A
LT1587-3.6
1=120Hz, CouT =25~ Tan!., VIN =6.6V, lOUT =3A
LT1584/5/7
TA =25°C, 30ms pulse
LT1584/5/7 -3.3 TA =25°C, 30ms pulse
LT1584/5-3.38 TA = 25°C, 30ms pulse
LT1584/5/7 -3.45 TA= 25°C, 30ms pulse
LT1584/5/7 -3.6 TA=25°C, 30ms pulse

remperature Stability
_ong-Term Stability
~MS Output Noise
% OIVOUT)
rhermal Resistance
LT1584
lunction to Case
LT1585
LT1585
LT1587
LT1587

TA= 125°C, 1000 Hrs.
TA = 25°C, 10Hz ::;1::; 10kHz
T Package: Control Circuitry/Power Transistor
T Package: Control Circuitry/Power Transistor
M Package: Control Circuitry/Power Transistor
T Package: Control Circuitry/Power Transistor
M Package: Control Circuitry/Power Transistor

'he • denotes spec iIi cations which apply over the specilied operating
emperature range.
lole 1: See thermal regulation specifications for changes in oulpul voltage
lue 10 healing effects. Load and line regulation are measured at a constant
unction temperature by low duty cycle pulse testing.
lole 2: Line and load regulation are guaranteed up to the maximum power
lissipation (25W for the LT1584 in T package, 26.5W for the LT1585 in T
lackage, 18W for the LT1587 in T package). Power dissipation is
letermined by input/output differential and the output curren!. Guaranteed
naximum output power will not be available over the full input/output
'oltage range.

L7lJ!J~

TYP

UNITS

•

55

MAX
120

•

0.2
2

5
10

mA

•

8

13

rnA

MIN

•

•

•

60

72

0.004
0.5
0.03
0.003

!lA
!lA

dB

0.02
1.0

0.65/2.7
0.7/3.0
0.7/3.0
0.7/3.0
0.7/3.0

%/W
%
%
%
°C/W
°C/W
°C/W
°C/W
°C/W

Nole 3: IFULL LOAD is deli ned as the maximum value of output load current
as alunction of input-to-output voltage. IFULL LOAD is equal to 7A lor the
LT1584, 4.6A atTJ ~ 25°C and 4A atTJ < 25°C lor the LT1585/LT1585-3.3
and 3A lor the LT1587. The remaining LT1585 lixed voltage versions are
4A. The LT1585 and LT1587 have constant current limit with changes in
input-to-output voltage. The LT1584 has variable current limit which
decreases about 4A as input-to-output voltage increases lrom 3V to 7V.

4-115

•

LT1584/LT1585/LT 1587
TYPICAL PERFORmAnCE CHARAOERISTICS
LT1584 Dropout Voltage
vs Output Current

LT1584 Shorl-Circuit Current
vs Input/Output Differential
10

1.5
OGUARANTEED
TEST POINTS

1.4
1.3

§1.2
~

1.1
~ 1.0

5~

0.9

LT1584 Load Regulation
vs Temperature

---

.......... r-:;·~-5'C

.;P"" r-o-



1.0

0

0.9

I:::J

"0

LT1585 Load Regulation
vs Temperature

6.0

1.5

1.3
~ 1.2
w

L11585 Shorl-Circuit Current
vs Temperature

TEST POINTS

I,..--

V
:;;..

-

I-"'"

a:: 0.8

c

-

III =4.SA

.-r-

,.

g

T =-5'C

7-"

I-

15
a::

:.....+

~~t:

I--

0.10

5.5

a::

:::J

T= 125'C_

T = 25'C

'-'
l:: 5.0
:::J
'-'
a:

..-..-..-

'-"

~

I--

,......

0

:t:

0.7

0.05

o

~
~

c

~ -0.05

'-

~

(3

Ii:

..

C

~

:=

en

"

t'-..

-0.10

:::J

4.5

........

15 -0.15

0.6
0.5

o
OUTPUT CURRENT (A)

"

-0.20
-75-50-25 0 25 50 75100125150175
TEMPERATURE (OC)

4.0
-75 -50 -25 0 25 50 75 100 125 150 175
TEMPERATURE (OC)

LT1584'TPC{13

LTl58S'TPC04

LT1587 Dropout Voltage
vs Output Current
1.5

o GUARANTEED

1.4

~

1.1

~ 1.0
I-

~ 0.9

~ 0.8

V >--

0.10

4.5

~ 0.05
z
o

~----l-M-Hz-O--ff--Li-nE

~,

Current Mode PW~
and DC/DC Convertel
FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•
•
•

The LT®1246/LT1247 are 8-pin, fixed frequency, curren'
mode, pulse width modulators. These devices are de·
signed to be improved plug compatible versions of thE
industry standard UC1842 PWM circuit. The LT1246,
LT1247 are optimized for off-line and DC/DC convertel
applications. They contain a temperature compensatec
reference, high gain error amplifier, current sensing comparator, and ahigh current totem pole output stage ideall)
suited to driving power MOSFETs. Start-up current ha~
been reduced to less than 250~. Cross-conduction cur·
rent spikes in the totem pole output stage have beer
eliminated, making 1MHz operation practical. Several nelll
features have been incorporated. Leading edge blankin~
has been added to the current sense comparator. Thi~
minimizes or eliminates the filter that is normally required
Eliminating this filter allows the current sense loop tc
operate with minimum delays. Trims have been added tc
the oscillator circuit for both frequency and sink current
and both of these parameters are tightly specified. ThE
output stage is clamped to a maximum VOUT of 18V in thE
on state. The output and the reference output are activel)
pulled low during under-voltage lockout.

Current Mode Operation to 1MHz
30ns Current Sense Delay
< 2501lA Low Start-Up Current
Current Sense Leading Edge Blanking
Pin Compatible with UC1842
Undervoltage Lockout with Hysteresis
No Cross-Conduction Current
Trimmed Bandgap Reference
1A Totem Pole Output
Trimmed Oscillator Frequency and Sink Current
Active Pull-Down on Reference and Output During
Undervoltage Lockout
• 18V High Level Output Clamp

APPLICATions
• Off-Line Converters
• DC/DC Converters
Start-Up
Threshold
16V
8.4V

Device
LT1246
LT1247

Minimum
Operating
Voltage
10V
7.6V

Maximum
Duty Cycle
100%
100%

Replaces
UC1842
UC1843

D'; LTC and LT are registered trademarks of Linear Technology Corporation.

BLOCK DIAGRAm

J---------~~OS~CI~LLA~TO§Rr=J1JL~~r--_=~~

Rr/Cr 4

t-----.. . .

-{+1mA

5.6V

2R

R

ISENSE 3

t-----------..------'
LTl246·BDOl

4-126

LT1246/LT1247
~BSOLUTE

mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

Supply Voltage ....................................................... 25V
Output Current ...................................................... ±1A*
Output Energy (Capacitive Load per Cycle) .............. 51lJ
I\nalog Inputs (Pins 2, 3) .............................. -0.3 to 6V
Error Amplifier Output Sink Current..................... 10mA
Power Dissipation at TA::; 25°C ............................... 1W
Operating Junction Temperature Range
LT1246C/LT1247C ............................. aoc to 1aaoc
Storage Temperature Range ................ - 65°C to 15aoC
Lead Temperature (Soldering, 1a sec) ................. 30aoC

ORDER PART
NUMBER

TOP VIEW

'""'o'~
FB

2

7 Vee

ISENSE 3

6 OUTPUT

RT/CT 4

5 GND

N8 PACKAGE
B-LEAD PDIP
S8 PACKAGE
HEAD PLASTIC

LT1246CN8
LT1246CS8
LT1247CN8
LT1247CS8
S8 PART MARKING

so

1246
1247

TJMAX =100'C, 6JA =130'C/W (N8)
TJMAX =100'C, 6JA =150'C/W (S8)

'The lA rating for output current is based on transient switching
requirements.

ELECTRICAL CHARACTERISTICS

Consult factory for Industrial and Military grade parts.

(Notes 1,2)

•

-M-R-AM-E-H-R------------~I-c-O-N-Dl-Tl-ON-S----------------~---M-IN------T-y-P-----M-AA----.---UN-IT-S

Reference Section
Output Voltage

10 =lmA, TJ =25°C

Line Regulation

12V < Vcc < 25V

Load Regulation

1mA < IREF < 20mA

remperature Stability
r otal Output Variation

Line, Load, Temperature

Output Noise Voltage

10Hz < F< 10kHz, TJ =25°C

Long-Term Stability

TA =125°C, 1000 Hrs.

Output Short-Circuit Current
Oscillator SectIon
Initial Accuracy
~oltage

Stability

remperature Stability

•

•

5.000

5.075

3
-6

20

mV

-25

mV
mV/oC

0.1
4.87
5

25

ILV
mV

•

-30

-90

-180

mA

47.5
465

50
500

52.5
535

kHz
kHz

1

%
%/oC
mA

5.13
50

12V < Vcc < 25V, TJ =25°C

~mplitude
~Iock

Vosc (Pin 4) =2V, TJ =25°C

Error Amplifier Section
:eedback Pin Input Voltage

VPIN 1 =2.5V

nput Bias Current

VFB =2.5V

Jpen-Loop Voltage Gain

2 < Vo < 4V

Jnity-Gain Bandwidth
'ower Supply Rejection Ratio

TJ =25°C
12V < VCC < 25V

Jutput Sink Current

VPIN 2 =2.7V, VPIN 1 =1.1V

Jutput Source Current

VPIN 2 =2.3V, VPIN 1 =5V

V

•

Rr =10k, Cr =3.3nF, TJ =25°C
Rr =6.2k, Cr =500pF, TJ =25°C
TMIN < TJ < TMAX
Pin 4

Ramp Reset Current

4.925

-0.05

1.7

•
•
•
•
•
•

V

V

7.9

8.2

8.5

2.42

2.50

2.58
-2

V

IJ.A

65

90

dB

1

2

MHz
dB

6
-0.75

mA

60
2
-0.5

mA

4-127

LT1246/LT1247
ELECTRICAL CHARACTERISTICS
PARAMETER
I CONOITIONS

(Notes 1,2)

Error Amplifier Section
Output Voltage High Level

VPIN 2= 2.3V, RL = 15k to GND

Output Voltage Low Level

VPIN 2 = 2.7V, RL = 15k to Pin 8

MIN

TYP

5

5.6

MAX

UNITS

v

0.2

1.1

V

3.00

3.15
1.10

VN
V

-10

~
ns

Current Sense Section
Gain
Maximum Current Sense Input Threshold

VPIN3<1.1V

Power Supply Rejection Ratio

•

•

2.85
0.90

70

•

Input Bias Current
Delay to Output

1.00
-1

dB

30

Blanking Time

ns

60
1.5

Blanking Override Voltage

V

Output Section
Output Low Level

lour = 20mA
lour = 200mA

Output High Level
Rise Time

lour = 20mA
lour = 200mA
CL = 1nF, TJ = 25°C

Fall Time

CL = 1nF, TJ = 25°C

Output Clamp Voltage

lo=1mA

Undervoltage Lockout
Start-Up Threshold

LT1246
LT1247

Minimum Operating Voltage

LT1246
LT1247

Hysteresis

LT1246
LT1247

PWM
Maximum Duty Cycle

TJ = 25°C

Minimum Duty Cycle

TJ = 25°C

Total Device
Start-Up Current
Operating Current
The. denotes those specifications which apply over the full operating
temperature range.
Note 1: Unless otherwise specified, Vce = 15V, RT = 10k, CT = 3.3nF.

4-128

••
••

0.25
0.75
12.0
11.75

V
V
30

70

ns

20

60

ns

18

19

V

15
7.8

16
8.4

17
9.0

V
V

9.0
7.0

10
7.6

11
8.2

V
V

5.5
0.4

6.0
0.8

•
••
••
••

V
V

0.4
2.2

94

V
V
100

0

%
%

170

250

13

20

~
rnA

Nole 2: Low duty cycle pulse techniques are used during test to maintain
junction temperature close to ambient.

LT1246/LT1247
'YPICAl PERFORmAnCE CHARACTERISTICS
Starl-Up Current

LT1247 Undervollage Lockout

LT1246 Undervollage Lockout
17

200 ,------,--,---,------,--,---r--,

11

-

START-UP THRESHOLD

16 I-

10

;;(

180
160

~1=$:=~;t;;t=~~
~

,..~140r__-+-~-r__-+-~-r__~

~ 120 r__-+-~-r__-+-~-r__~

15

0:

B 100r__-+-~-r__-+-~-r__~

START-UP THRESHOLD

I

11

80r__-+-~-r__-+-~-r__~

§

~

MINIMUM OPERATING VOLTAGE
MINIMUM OPERATING VOLTAGE

10

60
40
20

9

-50 -25

25

50

75

100

6
-50 -25

125

TEMPERATURE (OC)

25

50

75

100

0
-50 -25

125

25

50

75

100

125

TEMPERATURE (0C)

TEMPERATURE (0C)

lTl246.TPC'-'
a:l -2

............

::J

...........

fil -4

Y

-I

8

10

1

12 14 16

10
-50 -25

18

s:

Vee = 15V
Rr=10k Cr = 3300pF _

11
TJ = 25°C

o

r-........

:I:

oS

/

..........

'"
~2.50

~2.49

V

High Level Output
Saturation Voltage

Current Sense Clamp Voltage

Feedback Pin Input Voltage

...-

4.0

--- --

I'--

>

-.....

~1.01

.........

dl.00

\1l 0.99

~0.9S
:2

~2.4S

'"5l2.47

~ 3.5
w

50

75

100

0.95
-50 -25

125

TJ = 125°C

~

1.5

50..

1.0

o

0.5

!:;

130.96

25

T = 25°C

a:

~ 2.0

~0.97

2.45
-50 -25

TJ= 55°C

~ 2.5
o
z

a:

~2.46

~ 3.0

25

50

75

100

o

125

o

TEMPERATURE (OC)

TEMPERATURE (oG)

100

201

OUTPUT SOURCE CURRENT (rnA)

LT1246.TPC10

Low Level Output
Saturation Voltage

Supply Current vs
Oscillator Frequency

Low Level Output Saturation Voltage
During Undervoltage Lockout

1.0

4.0

14

~ 3.5

~
w
co

w


~
en
l=> .
c..

!:;

A~

0

o

~ 3.0

~

!:;

~ ~P'"
~",.
TJ =-55°G
"I 1
~ P"" TJ = 25°C

l-

=>

0

rr
o

100

-

0

> 2.5
z
0
~ 2.0
a:
=>
~ 1.5
en
!:; 1.0
0..

~WC

,;-

/

::::-~ tt::= -

o

o

10

~

SO

:;;:

co
w 60

~

0

>

0..

40

0

9
zW

"

"

~

"'

I'\.

"

"- I'\.

'\

'\

100

lk

10k

lOOk

1M

90 ~

'"~

45

-45
10M

FREQUENCY (Hz)

1.0

m

ffl
a:

:x: O.S

lI-

~
;;; 0.6
w
en
z 0.4

t:::

I-

:z
w
a: 0.2
a:
=>
'-'

0
0
ERROR AMP OUTPUT VOLTAGE(V)

LT124e'TPCt6

4-130

..J

135 j!

\.. PHASE

0

10

r---r--,---r-..,---,--.

0

20

-20

'":x:

lS0

0

il

1.2

~

0..

~

lOOk

Current Sense Input Threshold

IGAIN

~

10k

LT1248'TPCt4

225

",

9

OSCILLATOR FREQUENCY (Hz)

OUTPUT SINK CURRENT (rnA)

Error Amplifier Open-Loop Gain
and Phase

:z

=>
en

10

LT124&·TPC13

- ~

11

0..
0..

1I

OUTPUT SINK CURRENT (rnA)

100

=>
'-'
~

~;:725OC
~

0.5

200

...-:

-

13
-I Vsw

V,N

Efliciency

LT1271

70

<0.3V = NORMAL MODE
>2.5V = SHUTDOWN
OPEN = Burst Mode
OPERATION

'R2IS MADE FROM PC BOARD
COPPER TRACES.
"OPTIONAL CONNECTION FOR 02.
tFOR CIRCUITS WHICH DO NOT USE
EFFICIENCY IS HIGHER. BUT MINIMUM
Burst Mode OPERATION. C5 MAY
V,N INCREASES. SEE APPLICATION
BE PARALLEL WITH A6BOQ, O.I~F
INFORMATION SECTION.
IN SERIES TO GIVE WIDE PHASE MARGIN '''MAXIMUM CURRENT IS DETERMINED
WITH DIFFERENT SWITCHING IC,AND
BYTHE CHOICE OF LT1071 FAMILY MAIN SWITCHER IC.
OUTPUT CAPACITORS
SEE APPLICATION INFORMATI,?'~~~J,ION.

60

f--+----¥-'-----'---'--~-~-'-~

o
o

lA
20mA

2A
40mA

3A
BOmA

Figure 1. High Efficiency 5V Buck Converter

4-137

LT1432-3.3
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

VIN Pin .................................................................... 30V
V+ Pin ........................................................... ~ ......... 40V
Vc ........................................................................... 35V

TOP VIEW

ORDER PART
NUMBER

'~O""~

VOUT 2

VUM and VOUT Pins ................................................... 7V
Diode Pin Voltage .............................................. ..... 30V
Mode Pin Current (Note 2) ..................................... 1 mA
Operating Temperature Range .................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

VIN 3

V+ 4

N8 PACKAGE
B-LEAD PDIP

GND
Vc
5 DIODE
7

LT1432CN8-3.3
LT1432CS8-3.3

6

S8 PACKAGE
8-LEAD PLASTIC SO

TJMAX = 100°C, 9JA = 150°CIW (N8)
TJMAX = 100°C, 9JA = 17O°CIW (S8)
Consult factory for Military and Industrial grade parts.

ELECTRICAL CHARACTERISTICS
VC =4V, VIN =4V, V+ =BV, VDIODE =Open, VLlM =Your, VMODE =OV, TJ =25°C
Device is in standard test loop unless otherwise noted.
PARAMETER

CONDITIONS

Regulated Output Voltage
Output Voltage Line Regulation
Input Supply Current (Note 1)
Quiescent Output Load Current
Mode Pin Current

Vc Current = 220!1A
VIN = 4V to 30V
VIN = 4V to 30V, V+ = VIN + 5V, Vc = VIN + 1V

Mode Pin Threshold Voltage
(Normal to Burst)
Vc Pin Saturation Voltage
Vc Pin Maximum Sink Current
Vc Pin Source Current
Current Limit Sense Voltage (Note 3)
VUM Pin Current
Supply Current in Shutdown
Burst Mode Operation Output Ripple
Burst Mode Operation Average Output Voltage
Clamp Diode Forward Voltage
Start-up Drive Current
Restart Time Delay
Transconductance, Output to Vc Pin

4-138

VMODE = OV (Current Is Out of Pin)
VMODE = 3.3V (Shutdown)
IMODE = 10!!A (Out of Pin)
VOUT = 3.6V (Forced)
VOUT = 3.6V (Forced)
VOUT =3.0V (Forced)
Device in Current Limit Loop
Device in Current Limit Loop
(Current Is Out of Pin)
VMODE > 3V, VIN < 30V, Vc and V+ = OV
Device in Burst Test Circuit
Device in Burst Test Circuit
IF = 1rnA, All Other Pins Open
V~UT = 1.5V (Forced),

VIN = 4V to 26V,
V =VIN-1V,VC=VIN-1.5V
(Note 4)
Ic = 150!1A to 250!!A

•
•
•

••
•
•
•

•
•

•
•
•

•

MIN

TYP

MAX

UNITS

3.24

3.36
20
0.5
1.2
50
30
1.5

V
mV
rnA
rnA

0.6

3.30
5
0.3
0.9
30
15
0.9

0.45
35
56
30

0.25
0.8
60
60
45

0.45
1.5
100
64
70

V
rnA

60

30

15
100
3.30
0.5
45

0.7
2700

1.2
3600

3.15

3.45
0.65

10
5000

!!A
!!A
V

!!A
mV
!!A
!!A
mV p_p
V
V
rnA
ms
!1mho

LTl432-3.3

ELECTRICAL CHARACTERISTICS
Operating parameters in standard circuit configuration.
VIN = 7V, lOUT = 0, unless otherwise noted. These parameters guaranteed where indicated, but not tested.
PARAMETER

MIN

CONDITIONS

Burst Mode Operation Quiescent Input Supply Current
Burst Mode Operation Output Ripple Voltage
Normal Mode Equivalent Input Supply Current
Normal Mode Minimum Operating Input Voltage
Burst Mode Operation Minimum Operating Input Voltage
Efficiency
Load Regulation

lOUT = 0
lOUT = 50mA
Extrapolated from lOUT = 20mA
1OOmA < lOUT < 1.5A
5mA < lOUT < 50mA
Normal Mode
lOUT = O.5A
Burst Mode Operation lOUT = 25mA
Normal Mode
50mA < 10~T < 2A
Burst Mode Operation 0 < lOUT < OmA

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Does not include current drawn by the power IC. See operating
parameters in standard circuit.
Note 2: Breakdown voltage on the Mode pin is 7V. External current must
be limited to value shown.

TYP

MAX

UNITS

1.6
80
120
3.0
4.5

2.2

rnA
mVp_p
mV p_p

4.1

rnA
V
V

86
70
5
30

15

%
%
mV
mV

Note 3: Current limit sense voltage temperature coefficient is +O.33%/oC
to match TC of copper trace material.
Note 4: VOUT pin switched from 3.6V to 3.0V.

----------------------------mi
EQUIVALEnT SCHEmATIC
02
VIN -+-----t---I Vsw
LT1271
Vc

VINt---+----~. . ----· OPTIONAL
: CONNECTION
FB
I OF 02
I
GND
....rrrr'-_"-"'.....-----_3.3V

-------- 3

• S31S CLOSED ONLY DURING START-UP.
.. S1 AND S2 ARE SHOWN IN NORMAL
MODE. REVERSE FOR Burst Mode
OPERATION.

Figure 2

4-139

LT1432-3.3
TYPICAL PERFORmAnCE CHARACTERISTICS
Efficiency vs Input Voltage

Minimum Input Voltage to Start Normal Mode (Diode to Input)

Efficiency vs Load Current

100

6.5

95
TJ=25·C
LT1271, L = 50ltH

TJ = 2~oC

TJ = 25°C
VIN = 7V
6.0

90

~

>
<.:>

zw

I"---.

80

90

-.....::::t--~E TO OUTPUT
-

DIODE TO

<3

IN~

r-

C

::::

lOUT" 1A

~

>
<.:>
~
<3

60

85

~

70

80

o

10
15
20
INPUT VOLTAGE (V)

25

75

30

- r::::::: ~
/
-.!;!,1270

LT1~

o

~

-..........

w

~

5.5

>a..

5.0

DIODE
TO INPUT

~

;;;,

;;;

LT127y
LTJ171

4.5

4.0
0.5

1.0
1.5
2.0
LOAD CURRENT (A)

2.5

3.0

o

---

~~

/'

2
OUTPUT CURRENT (A)
LT1432-3.3G03

lT1432-3.SG02

Minimum Running Voltage Normal Mode*

Minimum Input VoltageNormal Mode (Diode to Output)
5.5

9.0

Burst Mode Operation Minimum
Input Voltage

r---.,---...,---,---,---,

5.5

r---.,---...,---,---,----,

TJ = 25°C
5.0 I--+---+-----,I--+-----{

8.0

~

w

'"~

I

7.0

a..

5.0

4.0

ttl

~

LT117/ /LT1271 .

~
!:; 6.0
;;;

~
~

4.5 I--+---.lf-'--::"""'I-~"'F-----{

!:; 4.0

./ /
~

a..

DIODE
TO INPUT

5.0 f--+---+--f--+-----{

~

h..s~"--+--f--+-----{

w

~

~

!:; 4.5

~

;;;
3.5 1 - - - + - - + - - + - - 1 - - 1

o

OUTPUT CURRENT (A)

OUTPUT CURRENT (A)

4.0

.......

3.5 '--_..L-_-'--_-'-_----'_---'
o
10
20
30
40
50
LOAD CURRENT (rnA)

3.0 ' - - - - ' - - - ' - - - ' - - - - ' - - - - - '

o

"
1

LT1432-3.3GOS

lT1432-3.3G06

'SEE MINIMUM INPUT VOLTAGE TO START

Shutdown Current vs Input
Voltage

Current Limit Sense Voltage*

Battery Current in Shutdown*

50

40r---,---,---.---,

80

301--~~---+--1---I

:;- 70

TJ = 25·C

40

~

30

~

a::

/"

~ 20

<.:>

10

o

/

V

-

~
~

10
15
20
INPUT VOLTAGE (V)

w

20f---I---I-~~__~~

0

>

<.:>

'"~
'"

25

30

60

w

O'---~'---~--~-----'

o

25

50
75
TEMPERATURE (OC)

100
LTl432-a.3GOB

'DOES NOT INCLUDE LT1271 SWITCH LEAKAGE.

4-140

'"~

a::

;;;,

V

o

.§.

/'"

V

V

/

50

40

o

50
75
100
25
JUNCTION TEMPERATURE (OC) Lm',",G9

, TEMPERATURE COEFFICIENT OF SENSE VOLTAGE IS
DESIGNED TO TRACK COPPER RESISTANCE.

LT1432-3.3
TYPICAL PERFORmAnCE CHARACTERISTICS
Incremental Battery Current * in
Burst Mode Operation

No Load Battery Current in Burst
Mode Operation

Transconductance - VOUT to Vc
Current

2.0

5000

TJ = 25°C

TJ = 25°C

Gm = l\1(Vc PIN)
l\VOUT

-

::l: 1.0

~

~

1i'i

a50::

u

I---

:i!

0.5

;;;;

o
o

g3000
o

~

r--- r---r-10

15

20

o

25

o

'"uoen

'--

g2000

10
15
20
BATTERY VOLTAGE (V)

LT'''''''''''

BATTERY VOLTAGE (V)
• TO CALCULATE TOTAL BATTERY CURRENT IN Burst
Mode OPERATION, MULTIPLY LOAD CURRENT BY
INCREMENTAL FACTOR AND ADD NO-LOAD CURRENT.

---

1000

25

o

25
50
75
JUNCTION TEMPERATURE (OC)

100

LT1432-3.3G12

Burst Mode Operation Load
Regulation

Line Regulation

Mode Pin Current

25

40

60

TJ =25°C
VIN =7V

TJ = 25°C

TJ = 25°C
40

~
w
'":i!::z::

20

[
w
'"~

NORMAL MODE

'S;;;;M~N

u

~

!3o -20

u

~

o

..............

..............

-25

-

.............

i'--.

1i'0::i

.......

0::
:::l

-50

-75

o

5

10
15
INPUT VOLTAGE (V)

20

V

.....V

I

u

-20

-40

,/

o

20

-40
40
60
80
LOAD CURRENT (rnA)

100

~ ,MODE DRIVE MUST
SINK =301lA AT ov

o

4
MODE PIN VOLTAGE (V)

10

LT1432-3.3G14

Restart Load Current
40

Restart Time Delay

Start-up Switch Characteristics

.1.
VOUT =4.5V

TJ = 25°C

30

1i'
i
0::

20

1

-

ffi

0::
0::
:::l

/
~

0::
:::l
U

10

-20

~ -40

c::
oJ;

-60

O'------'-----'--......J..----'

o

25
50
75
JUNCTION TEMPERATURE (OC)

100

o
o

-80
50
75
25
JUNCTION TEMPERATURE (OC)

100

lT1432-3.3G16

f.-.-'"
-2

/

~

/

/

I,.... NOTE ~ERTICAl ANDHORIZONTAL SCALE
CHANGES AT 0,0

10
V+ TO VIN VOLTAGE

~

30

LT1432-3.3G16

4-141

LT1432-3.3
APPLICATions InFoRmATion
More applications information on the LT1432-3.3 is available
in the LT1432 data sheet.
Basic Circuit Description
The LT1432-3.3 is a dedicated 3.3V buck converter driver
chip intended to be used with an IC switcher from the LT1171/
LT1271 family. This family of current mode switchers includes current ratings from 1.25A to 10A, and switching
frequencies from 40kHz to 100kHz as shown in the table
below.
DEVICE

SWITCH
CURRENT

FREQUENCY

OUTPUT CURRENT IN
BUCK CONVERTER

LT1270A
LT1270
LT1170
LT1070
LT1269
LT1271
LT1171
LT1071
LT1172
LT1072

10A
8A
5A
5A
4A
4A
2.5A
2.5A
1.25A
1.25A

60kHz
60kHz
100kHz
40kHz
100kHz
60kHz
100kHz
40kHz
100kHz
40kHz

7.5A
6A
3.75A
3.75A
3A
3A
1.8A
1.8A
O.9A
O.9A

The maximum load current which can be delivered by these
chips in a buck converter is approximately 75% of their
switch current rating. This is partly due to the fact that buck
converters must operate at very high duty cycles when input
voltage is low. The current mode nature ofthe LT1271 family
requires an internal reduction of peak current limit at high
duty cycles, so these devices are rated at only 80% ofthei rfull
current rating when duty cycle is 80%. A second factor is
inductor ripple current, half of which subtracts from maximum available load current. The LT1271 family was originally
intended for topologies which have the negative side of the
switch grounded, such as boost converters. It has an extremely efficient quasi-saturating NPN switch which mimics
the linear resistive nature of a MOSFET but consumes much
less die area. Driver losses are kept to a minimum with a
patented adaptive antisat drive that maintains aforced beta of
40 over a wide range of switch currents. This family is
attractive for high efficiency buck converters because of the
low switch loss, but to operate as a positive buck converter,
the GND pin of the IC must be floated to act as the switch
output node. This requires a floating power supply for the
chip and some means for level shifting the feedback signal.
The LT1432-3.3 periorms these functions as well as adding

4-142

current limiting, micropower shutdown, and dual mode
operation for high conversion efficiency with both heavy and
very light loads.
The circuit in Figure 1 is a basic 3.3V positive buck
converterwhich can operate with input voltage from 4.5V
to 30V. The power switch is located between the Vsw pin
and GND pin on the LT1271. Its current and duty cycle are
controlled by the voltage on the Vc pin with respect to the
GND pin. This voltage ranges from 1V to 2V as switch
current increases from zero to full-scale. Correct output
voltage is maintained by the LT1432-3.3 which has an
internal reference and error amplifier (see Equivalent
Schematic in Figure 2). The amplifier output is level
shifted with an internal open collector NPN to drive the Vc
pin of the switcher. The normal resistor divider feedback
to the switcher feedback pin cannot be used because the
feedback pin is referenced to the GND pin, which is
switching up and down. The Feedback pin (FB) is simply
bypassed with acapacitor. This forces the switcher Vc pin
to swing high with about 200JlA sourcing capability. The
LT1432-3.3 Vc pin then sinks this current to control the
loop. Transconductance from the regulator output to the
Vc pin current is controlled to approximately 3600llmhos
by local feedback around the LT1432-3.3 error amplifier
(S2 closed in Figure 2). This is done to simplify frequency
compensation of the overall loop. Aword of caution about
the FB pin bypass capacitor (C6): this capacitor value is
very non-critical, but the capacitor must be connected
directly to the GND pin or tab of the switcher to avoid
differential spikes created by fast switch currents flowing in the external PCB traces. This is also true for the
frequency compensation capacitor C5. C5 forms the
dominant loop pole.
Afloating power supply for the switcher is generated by D2
and C3 which peak detect the input voltage during switch off
time. This is differentthan the 5Vversion ofthe LT1432 which
connects the anode of the diode to the output rather than the
input. The output connection is more efficient because the
floating voltage is a constant 5V (or 3.3V), independent of
input voltage, but in the case of the 3.3V circuit, minimum
required input voltage for starting is several volts higher (see
the Typical Periormance Characteristics curves). When the
diode is connected to the input, the suggested type is a

LT1432-3.3
APPLICATions InFoRmATion
Schottky 1N5818. Diode type is more critical for the output
connection because the high capacitance of Schottky diodes
creates narrow output spikes. These spikes will be eliminated
if asecondary outputfilter is used or ifthere is sufficient lead
length between the regulator output and the load bypass
capacitors. Low capacitance diodes like the 1N4148 do not
create large spikes, buttheir high forward resistance requires
even higher input voltage to start.
01, L1 and C2 act as the conventional catch diode and
output filter of the buck converter. These components
should be selected carefully to maintain high efficiency
and acceptable output ripple. See the original LT1432 (5V)
data sheet for detailed discussions of these parts.
Current limiting is performed by R2. Sense voltage is only
60mV to maintain high efficiency. This also reduces the
value of the sense resistor enough to utilize a printed
circuit board trace as the sense resistor. The sense voltage
has a positive temperature coefficient of 0.33%/oC to
match the temperature coefficient of copper.
The basic regulator has three different operating modes,
defined by the Mode pin drive. Normal operation occurs when
the Mode pin is grounded. A low quiescent current Burst
Mode operation can be initiated by floating the Mode pin.
Input supply current is typically 1.3mA in this mode, and
output ripple voltage is 100mVp_p. Pulling the Mode pin
above 2.5V forces the entire regulator into micropower
shutdown where it typically draws less than 201JA.

pulses. This maximizes efficiency at light load by eliminating
quiescent current in the switching IC during the period
between bursts.
The result of pulsating currents into the output capacitor
is that output ripple amplitude increases and ripple frequency becomes a function of load current. The typical
output ripple in Burst Mode operation is 100mVp-p, and
ripple frequency can vary from 50Hz to 2kHz. This is not
normally a problem for the logic circuits which are kept
alive during sleep mode.
Some thought must be given to proper sequencing between normal mode and Burst Mode operation. A heavy
(> 1OOmA) load in Burst Mode operation can cause excessive output ripple, and an abnormally light load (1 OmA to
30mA, see Figure 3) in normal mode can cause the
regulator to revert to a quasi-Burst Mode operation that
also has higher output ripple. The worst condition is a _
sudden, large increase in load current (>1 OOmA) during . .
this quasi-Burst Mode operation or just after a switch
from Burst Mode operation to normal mode. This can
cause the output to sag badly while the regulator is
establishing normal mode operation (",100,...,s). To avoid
problems, it is suggested that the power-down sequence
consist of reducing load current to below 1OOmA, but
greater than the minimum for normal mode, then switching to Burst Mode operation, followed by a reduction of
load current to the final sleep value. Power-up would
consist of increasing the load currentto the minimum for

Burst Mode Operation

50
NORMAL MODE
TJ = 25°C

~

Burst Mode operation is initiated by allowing the Mode pin to
float, where it will assume aDC voltage of approximately 1V.
If AC pickup from surrounding logic lines is likely, the Mode
pin should be bypassed with a200pF capacitor. Burst Mode
operation is used to reduce quiescent operating current when
the regulator output current is very low, as in sleep mode in
a lap-top computer. In this mode, hysteresis is added to the
error amplifier to make it switch on and off, rather than
maintain aconstant amplifier output. This forces the switching IC to either provide a rapidly increasing current or to go
into full micropower shutdown. Current is delivered to the
output capacitor in pulses of higher amplitude and low duty
cycle rather than a continuous stream of low amplitude

c
o

:;;

40

~

a:

~ 30

~

I

as

20

~ ~":IOIE TO INPUT (1N58,8)

a:
a:

::J

u

~

10

1t::?IODE TO OUTPUT (1 N5818)-

o

4
INPUT VOLTAGE (V)

Figure 3. Minimum Normal Mode Load Current

4-143

LT1432-3.3
APPLICATions InFoRmATion
normal mode, then switching to normal mode, pausing for
1ms, followed by return to full load.
If this sequence is not possible, an alternative is to
increase the output capacitor to > 680/lF. This modification will often allow the power-down sequence to consist
of simultaneous turn-off of load current and switch to
Burst Mode operation. Power-up is accomplished by
switching to normal mode and simultaneously increasing
load currenttothe lowest possible value (30mA t0500mA),
followed by a short pause and return to full load current.

Full Shutdown
When the Mode pin is driven high, full shutdown of the
regulator occurs. Regulator input current will then consist
of the LT1432 shutdown current (",15!lA) plus the switch
leakage of the switching Ie H!lA to 25/lA). Mode input
current H 5/lA at 5V) must also be considered. Start-up
from shutdown can be in either normal or Burst Mode
operation, but one should always check start-up overshoot, especially if the output capacitor or frequency
compensation components have been changed.

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTCl148

High Efficiency Step-Down Switching Regulator Controller

5V Regulated Output Voltage

LT1432

High Efficiency Synchronous Step-Down Switching Regulator

Adjustable and Fixed 5V or 3.3V Outputs

LT1507

1.5A, 500kHz Step-Down Switching Regulator

Fixed Frequency PWM for Low Input Voltages from 4.5V to 12V

4-144

INDEX
SECTION 4-POWER PRODUCTS
SWITCHING REGULATORS ........................................................................................................... 4-145
LT1106, Micropower Step-Up DC/DC Converter for PCMCIA Card Flash Memory ........................................ 4-146
LTC1159/L TC1159-3.3/L TC1159-5, High Efficiency Synchronous Step-Down Switching Regulators .•...•.........•.. 4-154
LT1182/LT1183/LT1184/LT1184F, CCFL/LCD Contrast Switching Regulators •............................................ 4-172
LT1186, DAC Programmable CCFL Switching Regulator (Bits-to-Nits™) .................................................. 4-196
LTC1265/L TC1265-3.3/L TC1265-5, 1.2A, High Efficiency Step-Down DC/DC Converters ................................ 4-212
LTC1266/L TC1266-3.3/L TC1266-5, Synchronous Regulator Control/ers for N- or P-Channel MOSFETs ...•.......... 4-228
LTC1267/L TC1267-ADJ/L TC1267-ADJ5, Dual High Efficiency Synchronous Step-Down Switching Regulators .•••.. 4-248
LT1302/L T1302-5, Micropower High Output Current Step-Up Adjustable and Fixed 5V DC/DC Converters .••.....•.. 4-264
LT1303/L T1303-5, Micropower High Efficiency DC/DC Converters with Low-Baffery Detector
Adjustable and Fixed 5V .•......•.................................................•.•......................•..•••.....••........... 4-279
LT1304/L T1304-3.3/L T1304-5, Micropower DC/DC Converters with Low-Baffery Detector Active in Shutdown .. •.. 13-37
LT1305, Micropower High Power DC/DC Converter with Low-Baffery Detector ........................................... 4-290
LT1309, 500kHz Micropower DC/DC Converter for Flash Memory ................................•.....•••....•............ 13-41
LT1371, 500kHz High Efficiency 3A Switching Regulator •............................••..................................... 4-298
LT1372/LT1377, 500kHz and 1MHz High Efficiency 1.5A Switching Regulators .......................................... 4-310
LT1373, 250kHz Low Supply Current High Efficiency 1.5A Switching Regulator ................•........•............••.. 4-322
LT1375/LT1376, 1.5A, 500kHz Step-Down Switching Regulators .............•..........................•.........•........ 4-334
LTC1430, High Power Step-Down Switching Regulator Control/er ..........•..............•....•......•......•••....•..••.. 4-360
LT1572, 100kHz, 1.25A Switching Regulator with Catch Diode .............................•....••....•••.....••.......•••. 4-374
LTC1574/LTC1574-3.3/LTC1574-5, High Efficiency Step-Down DC/DC Converters with Internal Schoff/cy Diode ... 4-385

4-145

III

f"""-unm

~~

LTl106

TECHNOLOG~~~-----M-.-ic-ro-p-o-w-e-r-S-te-p---u-p
DC/DC Converter for
PCMCIA Card Flash Memory

FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•

The LT®1106 is the industry's first DCfDC converter
designed for use on Type I and Type II PCMCIA cards. The
device senses the VPP1 and VPP2 lines at the PCMCIA
socket and generates a regulated 12V, 60mA programming supply ifthe socket does not provide it. Internal logic
simplifies the interface to PCMCIA card microcontrollers.
One input selects a 12V or SV regulated output, while
another input controls micropower shutdown. Two logic
outputs indicate when the selected programming voltage
is valid and whether the input supply is 3.3V or SV.
The regulatorfeatures Burst Mode™ operation with aO.SA,
300mV switch for efficiency up to 8S%. High frequency
SOOkHz switching permits the use of small value, flat
inductors that fit neatly on PCMCIA cards. The device
requires just 1~ of output capacitance.
Quiescent current is 7S01JA which drops to 3S01JA when
the card runs off the socket supply. The shutdown pin
reduces supply current to only 101JA. The device includes
a soft start feature which limits supply current transients
when the card is inserted into a hot socket.

60mA Output Current at 12V from 3V Supply
Shutdown to 10J,IA
Programmable 12V or SV Output
Up to 8S% Efficiency
Quiescent Current: 7S01JA
Low VCESAT Switch: 300mV at O.SA Typical
Uses Low Value, Thin, Surface Mount Inductors
Ultra-Thin 20-Lead TSSOP Package

APPLICATions
•
•
•
•

PCMCIA Card Flash Memory VPP Generator
Portable Computers
Portable Instruments
DCfDC Converter Module Replacements

LT. LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.

TYPICAL APPLICATiOn
12V, 60mA Flash Memory Programming Supply

12V Output Efficiency
86

Ll'

01 = MBR0530
- - 01 = 4 BAT54Cs
IN PARALLEL

84
82
12V!60mA

C

80

15

78

~

76

~

3/5

... ~,;~3~j

74

70
L-.--=_~-=----:;:"--";=-----'

~

/'" Io-"'VIN = 3.3V

j~

72
'DALE ILS-3B25-01 OR
COILTRONICS CTX02-11238-3
"MOTOROLA MBR0530

hv

V,N=5V
... ...

(3

VPPVALID

VI'N =

.L:t

1

"

10
LOAD CURRENT (rnA)

100
LT1106·TA02.

4-146

LTl106
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

Vee Voltage ............................................................... 7V
Vsw Voltage ............................................................ 20V
AVPP Voltage ......................................................... 20V
VPP1, VPP2 Voltage ................................ '" ..... '" .... 20V
G1, G2 Voltage ....................................................... 20V
VON/OFF Voltage ......................................................... 7V
VSEL Voltage ............................................................. 7V
ILiM Voltage .............................................................. 7V
Maximum Power Dissipation ............................ 500mW
Operating Temperature Range ..................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER PART
NUMBER

SELECT 12/5
SOFT START

LT1106CF

FPACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 100'C, 9JA = 90'C/W

Consult factory for Industrial and Military grade parts

ELECTRICAL CHARACTERISTICS
SYMBOL
10

PARAMETER
Quiescent Current
Quiescent Current, Shutdown
"Doze" Mode Current

MIN

CONDITIONS
VSEL = 0.2V, AVPP = 12V

tON
VCESAT

VSEL = 3V, VPP1 and VPP2 Floating
VSEL = 0.2V, VPP1 and VPP2 Floating

Output Referred
Comparator Hysteresis

VSEL = 3V
VSEL = 0.2V
Current Limit Not Asserted

UNITS

900
15

IJA
IJA
IJA

320

••
•

Maximum Duty Cycle
Switch On-Time
Reference Line Regulation

MAX

750

2

Output Sense Voltage

Oscillator Frequency

TYP
9

VON/OFF = 0.2V
VSEL = 0.2V, VPP1 or VPP2 = 12V

Input Voltage Range

fosc
DC

Ell

TA =25°C, Vee =5V, VON/OFF =3V, unless otherwise noted.

4.75
11.50

5
12

6

V

5.25
12.60

V
V

15
35

mV
mV

400

500

700

kHz

80

85

92

%

1.7

2V < VIN < SV

0.06

0.15

!IS
'ioN

Switch Saturation Voltage

Isw= 0.5A

230

350

mV

Switch Leakage Current

Vsw = 12V, Switch Off

0.1

10

IJA

Switch Current Limit

VIN = 5V, Soft Start Floating
VIN = 3V, Soft Start Floating
Soft Start Grounded

600
650

900
950

mA
mA

80

120

IJA

0.8

V

0.8

V

Soft Start Pin Current

450
500

Select Input Voltage Low
Select Input Voltage High

V

1.6

ON/OFF Input Voltage Low
ON/OFF Input Voltage High
ON/OFF Bias Current

1.6
VON/OFF = 5V
VON/OFF = 3V
VON/OFF = OV

V
1S.0
8.0
0.1

24.0
14.0
1.1

IJA
IJA
IJA

LTl106
ELECTRICAL CHARACTERISTICS
SYMBOL

TA =25°C, Vee =5V, VONIOFF =3V, unless otherwise noted.

PARAMETER

CONDITIONS

Select Pin Bias Current

OV < VSEL < 5V

MIN

VPP1NPP2 Input Sense Threshold

11.0

AVPP Pin Input Current
VON/OFF = 0.2V
VPP1NPP2 Pin Input Current
VPP VALID Threshold

VON/OFF = 0.2V
AVPP Rising (High to Low Transition)

VPP VALID Output Voltage Low

ISINK= 100~

VPP VALID Output Voltage High

ISOURCE = 2.5~

3/5 Comparator Threshold
3/5 Comparator Output High
3/5 Comparator Output Low
Off State Current at G1/G2

•

MAX

0.1

1

~

11.5

11.9

V

50
0.1

90
1

~
~

50
0.1

90
1

~
~

12

V

0.13

0.3

11.4

•

ILOAD = 50~

TYP

4

4.5

3.6

3.75

3.65

3.8

ILOAD= 50~
VPP1 = 10V, VG1 = 12V or VPP2 = 10V,
VG2 = 12V or VON/OFF = OV

UNITS

V
V

4.2

V

0.75

0.9

V

0.1

1

~

V

The. denotes specifications which apply over the full operating
temperature range ..

TYPICAL PERFORmAnCE CHARACTERISTICS
Oscillator Frequency

Switch CurrenlLimit

BOO

1000

~ 700

900

Switch Saturation Voltage
250
ISW=500mA

:;;-

~ 600

5:1

IE

g;

~
U

500

gJ 400

w

«

t:z

--

300
-50

...--

-25

/'
.."

V

/'

.§. 225
~

.§. BOO

.....

a:

...............

~
!5
c..>

700

:<:
c..>

t::: 600

;r;

h:'

~ 200

§!

~c=3V

vcc=~ t' ............

0

25

50

TEMPERATURE (OC)

75

100

~

-25

25

50

~

75

100

~ 150

:<:
c..>

;r;t::: 125

I--

100
-50

--

-25

,,/

V

V

V
25

50

75

100

TEMPERATURE (OC)

TEMPERATURE (OC)
LT110S·TPC02

4-148

175

:::J

...............

500
400
-50

'"2

lT1100-TPCoa

LTl106
TYPICAL PERFORmAnCE CHARAOERISTICS
3/5 Comparator Threshold

AVPP Sense Voltage

4.00

AVPP Sense Voltage
5.10

12.20

12/5 SELECT = 0

--

12.15

3.95

~

~ 12.10

~ 3.90

~

c;
o

;; 3.B5
..J
o
:t:

./'

if.l3.BO
:x:

...-

v

\

~

12.05

~

12.00

en

iii
en

12/5 SELECT = 1
5.05

r--

- -,

~ 5.00
~

~4.95

3.75

11.95
11.90

-25

0
25
50
TEMPERATURE (OC)

75

~

4.B5

11.BO
-50

100

/

~4.90

11.B5

3.70
-50

V

V

en

iii

00-

:;c

:t:

-- \

~

-25

25
50
TEMPERATURE (OC)

75

4.80
-50

100

-25

0
25
50
TEMPERATURE (OC)

Supply Current in Shutdown

Supply Current

~

I

-

Vee =5V

10

:i:c
:c

"
:;'"

---

'-

'n

"
0
-50

Maximum Duty Cycle

BOO

12

-25

I
Vee =3V

95

700

iii

~

Vee =5V

~
,...

a:
a:

Vee =3V

600

--'"

::; 500

:::>

~

00-

BO

/'

•

,/'"

~
~

400

100

85

~

en

75

~
~
c

:::>

u

90

~
u

:::>

:::>

50
25
TEMPERATURE (oG)

100

LTll06-TPCQ6

LT110B-TPC05

14

75

300
-50

-25

25
50
TEMPERATURE (oG)

75

75
70
-50

100

-25

25
0
50
TEMPERATURE (OC)

75

100

LT11OS'TPcca

Start-Up Waveforms with Soft
Start, ILOAD = 1DmA

Start-Up Waveforms, ILOAD = 1mA
12V

IL
500mNDIV

,PPVALID
10V/DIV
ON/OFF
10V/DIV

ILOAD

~~~~

VON/OFF
10VlDIV
50JlS/DIV

.L7lJ!1~

12V OUTPUT
1V1DIV
AC COUPLED

VOUT
5V1DIV

VAVPP
2V/DIV

Load Transient Response,
COUT = 11lf

50/lS/DIV

50JlS/DIV

4-149

LTl106

Pin FunCTions
SELECT 12/5 (Pin 1): Tie to VIN or logic 1 for 5V output;
tie to GND or logic 0 for 12V output.
SOFT START (Pin 2): A0.1 W/1 MQ parallel RC from this
pin to GND provides a Soft Start function upon device
turn-on. Initially about aOJ,1A will flow from the pin into the
capacitor. When the voltage at the pin reaches approximately O.4V, current ceases flowing out of the pin. See
Applications Information section.
Vee (Pins 3, 4): Input Supply. Both pins should be tied
together. At least 1W input bypass capacitance is required. More capacitance reduces ringing on the supply
line.
3/5 (Pin 5): Supply Comparator Output. This pin provides
logic output indicating the value of the input supply. High
when Vee =5V; low when Vee =3.3V.
PGND (Pins 6,7): Power Ground. Connectto ground plane.
Vsw (Pins 9,10,11): Collector of Power Switch. High dV/
dt present on this pin. To minimize radiated noise keep
layout short and direct.
GND (Pin 13): Signal Ground. Connect of ground plane.
VPP VALID (Pin 14): This pin provides a logic signal
indicating that ouput voltage is greater than 11.4V. Active
low with internal 200k pull-up resistor.

4-150

G1, G2 (Pins16, 15): External MOSFETGate Drives. When
VPP1 orVPP2 is greaterthan 11.7V, G1 orG2 is driven to
about o.av. When VPP1 or VPP2 is less than 11.7V, the
drives assume a high impedance state pulled up to the
AVPP pin through an internal100k resistor.
VPP1, VPP2 (Pins 18, 17): Programming Power Inputs.
The LT11 06 senses both VPP1 and VPP2 supplies at the
PCMCIA card socket. IfVPP1 or VPP2 is greater than 11 V,
the LT1106 operates in "Doze" Mode-the switching
regulator turns off and the drive to external P-channel
MOSFETs turns on. Supply current in Doze Mode is about
350J,1A. Input current into VPP1 and VPP2 is about 1J,1A
when the device is shut down.
AVPP (Pin 19): Output Sense Pin. This pin connects to a
1MQ resistive divider that sets the output voltage. In
shutdown, the resistor string is disconnected and current
into this pin is reduced to <1J,1A.
ON/OFF (Pin 20): Shutdown Control. When pulled below
1.5V, this pin disables the LT11 06 and reduces supply
current to 10J,1A. All circuitry except the 3/5 comparator
is disabled in shutdown. The part is enabled when
ON/OFF is greater than 1.5V.

LTl106
BLOCK DIAGRAm
12/5
SELECT

AVPP

VPP2

299k

•

4k

100k

*1m

GND

PGND
LT1106·BD

~PPLICATlons

InFORmATion

:unctional Description

[he LT11 06 is a micropower, step-up DC/DC converter
.pecifically configured for PCMCIA flash memory card
IPP generation. Th!..device generates a 5V or 12V output
.electable via the 12/5 Select pin. If 12V is present on
~ither the VPP1 or VPP2 pins, gate drive outputs G1 and
]2 are driven low, turning on external PMOS devices. The
.witching regulator inside the LT11 06 is idled when 12V
s present on VPP1 or VPP2.
"he VPP VAll Doutput goes low when the voltage at AVPP
~xceeds 11.4V This signal can be used to indicate pres~nce of avalid programming voltage. The 3/5 comparator
ndicates whether the input voltage is 3.3V or 5V .

.L7lJ!1~

The Soft Start pin can be used to limit inrush current upon
start-up. A0.1!1f capacitor in parallel with a1M resistor is
connected between this pin and ground to limit peak
inductor current at start-up.
Switching Regulator Operation

When 12V is not present on the VPP1 or VPP2 pins and the
device is enabled (ON/OFF = 1), the LT11 06 generates a
regulated voltage at the AVPP pin. This voltage is programmable between 5Vor 12V depending on the state of
the 12/5 Select pin. Referring to the block diagram, hysteretic comparator C1 monitors AVPP via the resistor divider.
When the negative input of C2 falls below 1.24V, C1 's

4-151

LTl106
APPLICATions InFoRmATion
output goes high, enabling the oscillator. Switch 01
alternately turns on causing current build-up in the inductor; then turns off allowing the built-up currentto flow into
the output capacitor via the catch diode. As the output
voltage increases, so does the voltage at C1 's negative
input. When it exceeds the reference voltage plus C1 's
hysteresis, C1 turns the oscillator off.
Switch current is limited to approximately 600mA by 02,
R1 and C3. Two percent of 01 's collector current flows in
02; this current flows through R1 causing a voltage drop
in R1 proportional to 01 's collector current. When R1 's
drop equals 36mV, comparator C3 forces the oscillator
off. This action results in varying on-time, fixed off-time
operation that keeps peak switch current controlled. By
connecting a 0.1 ~ capacitor from the Soft Start pin to
ground, acurrentwill flow in 03 upon start-up. The current
flows through 700n resistor R2, reducing the amount of
current needed from 02 to force the oscillator off. As
current flows into the 0.1 ~ capacitor, the voltage at pin 2
increases and eventually current ceases to flow in 03.

Inductor Selection
All components for use in PCMCIA Type I cards must be
less than 1.1 mm high. This somewhat limits the selection
of appropriate inductors. Dale Electronics (60S-66S-9301)
manufactures the ILS-382S-01, amonolithic ferrite inductor that meets Type I height requirements. Generally,
inductors used with the LT11 06 must fulfill several requirements. It must be able to carry 0.9SA (the maximum
switch current) without saturation. DCR should be kept
low to maintain efficiency. The switching frequency of the
LT11 06 is quite high, over SOOkHz so magnetic material is
important. Ferrite core material works well in this frequency range. Avoid low cost iron powder cores which

4-152

have substantial AC loss at the LT1106's switching frequency. Inductance value need not be over 10J.lH.

Capacitor Selection
The LT11 06 will operate with 1J.IF of output capacitance.
Output ripple voltage is approximately 400mV with this
value and can be reduced significantly by increasing
output capacitance. The ripple voltage, although on the
high side, poses no problems for programming flash
memory. If operating the device in SV ouput mode the
capacitance should be increased. Ceramic capacitors are
suitable for the output. Distributed capacitance, i.e.,
0.1 J.IF or 0.2J.IF units next to individual flash memory
chips, is acceptable. The input capaCitor should have at
least some tantalum capaCitance (low Q) to minimize
resonance on the input. Flash memory cards are typically
several inches away from a solid low impedance supply
due to sockets, connectors, etc. If just ceramic capacitors are used at the supply pin of the LT11 06, switching
currents will resonate the supply line causing ringing that
can exceed SOOmVp_p. The high Q, low ESR nature of
ceramic capacitors causes this. Afew microfarad's worth
of tantalum capacitors with moderate ESR and low Q
characteristics will reduce or eliminate the problem.

Diode Selection
As with inductors, most good power Schottky diodes are
in packages that exceed the 1.1 mm height limit of the
Type I PCMCIAcard. Motorola manufactures the MBROS30
Schottky diode, ideal for use with the LT1106. This
diode's maximum height however, is 1.3Smm, making it
difficult to use in Type 1 cards. Philips Components
manufactures the BATS4C. Four units in parallel make an
adequate diode.

LTl106
TYPICAL APPLICATion
Alternative Scheme Allows 12V from VPP1NPP2to Provide Power When LT11D6 is in Shutdown
0"
VPP1 - - .

0"
VPP2--'

0"

1---+---

12V/60mA

'DALE ILS-3824-01
"MBR0530 OR 4 BAT54s IN PARALLEL

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1109

5V to 12V/60mA VPP Generator

300~

LT1109A

5V to 12V/120mA VPP Generator

300~

10, 120kHz Oscillator

LT1301

5V to 12V/200mA VPP Generator

120~

10, 155kHz Oscillator

LT1309

5V to 12V/60mA VPP Generator

650~

10, 650kHz Oscillator

10, 120kHz Oscillator

4-153

'~LlnCI\D

~,

LTCl159/LTCl159-3.3/LTCl159-5

TECHNOLOG~~~-H-i-g-h-E-ff-ic-ie-n-C-y-s-y-n-C-h-ro-n-o-u-s

Step-Down Switching Regulators
FEATURES

DESCRIPTion

•
•
•
•
•

The LTC®1159 series is afamily of synchronous step-down
switching regulator controllers featuring automatic Burst
Mode™ operation to maintain high efficiencies at low
output currents. These devices drive external complementary power MOSFETs at switching frequencies up to 250kHz
using a constant off-time current-mode architecture.

•
•
•
•
•

Operation from 4V to 40V Input Voltage
Ultra-High Efficiency: Up to 95%
20~ Supply Current in Shutdown
High Efficiency Maintained Over Wide Current Range
Current Mode Operation for Excellent Line and Load
Transient Response
Very Low Dropout Operation: 100% Duty Cycle
Short-Circuit Protection
Synchronous FET Switching for High Efficiency
Adaptive Non-Overlap Gate Drives
Available in SSOP and SO Packages

APPLICATions
•
•
•
•
•
•
•

Step-Down and Inverting Regulators
Notebook and Palmtop Computers
Portable Instruments
Battery-Operated Digital Devices
Industrial Power Distribution
Avionics Systems
Telecom Power Supplies

A separate pin and on-board switch allow the MOSFET
driver power to be derived from the regulated output
voltage providing significant efficiency improvement when
operating at high input voltages. The constant off-time
current-mode architecture maintains constant ripple current in the inductor and provides excellent line and load
transient response. The output current level is user programmable via an external current sense resistor.
The LTC1159 automatically switches to power saving
Burst Mode operation when load current drops below
approximately 15% of maximum current. Standby current
is only 300IJA while still regulating the output and shutdown current is a low 201JA .
£T, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.

TYPICAL APPLICATiOn
CIN

l TC1159-5 Efficiency

1OOl'F
T100V

100

FIGURE 1 CIRCUIT
VIN =

90

r-....._

RSENSE
0.050
........"YYY'-......-w.~- VOUT

5V12A

>-

~ 80 . /

~!--

lov

~

C3

~

70

T
'COILTRONICS CTX33-4-MP

COUT

220l'F

60
0.02

0.2
LOAD CURRENT (A)
LTC11S9·TA01

Figure 1. High Efficiency Step-Down Regulator

4-154

LTC1159/LTCl159-3.3/LTCl159-5
~BSOLUTE

mAXimum RATinGS

nput Supply Voltage (Pin 2) ...................... -15V to 60V
Icc Output Current (Pin 3) .................................. 50mA
:ontinuous Pin Currents (Any Pin) ...................... 50mA
;ense Voltages ......................................... -O.3V to 13V
;hutdown Voltages ................................................... 7V
:XTVcc Input Voltage ............................................. 15V

~ACKAGE/ORDER

Operating Temperature Range .................... O°C to 70°C
Extended Commercial
Temperature Range ............................... -40°C to 85°C
Junction Temperature (Note 1) ............................ 125°C
Storage Temperature Range ................ - 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

InFORmATiOn

TOP VIEW

ORDER PART
NUMBER

ORDER PART
NUMBER

TOP VIEW

LTC1159CG
LTC1159CG-3.3
LTC1159CG-5

P-DRIVE
Vee

LTC1159CN
LTC1159CN-3.3
LTC1159CN-5
LTC1159CS
LTC1159CS-3.3
LTC1159CS-5

...
..

NPACKAGE
SPACKAGE
16-LEAD PDIP
16-LEAD PLASTIC SO
'FIXED OUTPUT VERSIONS
TJMAX = 125'C, 9JA = 80'C/W (N)
TJMAX = 125'C, 9JA = 110'C/W (S)

GPACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 125'C, 9JA = 135'C/W
;onsult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS

TA =25°C, VIN =12V, VSHDN1 =OV (Note 2), unless otherwise noted.

;YMBOL

PARAMETER

'FB

Feedback Voltage (LTC1159 Only)

'B

'OUT

Feedback Current (LTC1159 Only)
Regulated Output Voltage
LTC11 59-3.3
LTC1159-5

,VOUT

Output Voltage Line Regulation

VIN =9V
ILOAD =700mA
ILOAD =700mA
VIN =9V to 40V

Output Voltage Load Regulation
LTC11 59-3.3
LTC1159-5

5mA < ILOAD < 2A
5mA < ILOAD < 2A

Burst Mode Output Ripple

ILOAD =OA

N

VIN Pin Current (Note 3)
Normal Mode
Shutdown

'XTVee
ec
liN - Vee

EXTVee Pin Current (Note 3)
Internal Regulator Voltage
Vee Dropout Voltage

L7lJ!J~

CONDITIONS

•
•
••

MIN

TYP

MAX

1.21

1.25

1.29

••

V
~

0.2
3.23
4.90
-40

UNITS

3.33
5.05

3.43
5.20

V
V

0

40

mV

40
60
50

65
100

mV
mV
mVp_p

VIN =12V, EXTVee =5V
VIN =40V, EXTVee =5V

200
300

~
~

VIN =12V, VSHDN2 =2V
VIN =40V, VSHDN2 =2V
EXTVee =5V, Sleep Mode

15
25

~
~

VIN =12Vto 40V, EXTVcc =OV, Icc =10mA
VIN =4V, EXTVee =Open, Icc =10mA

•

4.25

250
4.5

4.75

~
V

300

400

mV

4-155

LTC1lS9/LTCl 1S9-3.3/LTCllS9-S

ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

EXTVcc Switch Drop
VEXT- Vcc
Vp·GATE - VIN P-Gate to Source Voltage (Off)
VSENSE+ VSENSC

Current Sense Threshold Voltage
LTC1159
LTCI159-3.3
LTC1159-5

VSHDN2
ISHDN2
ICT

SHDNI Threshold
LTCI159CG, LTCI159-3.3, LTC1159-5
SHDN2 Threshold
Shutdown 2 Input Current
CT Pin Discharge Current

tOFF
tr,tf

Off-Time (Note 4)
Driver Output Transition Times

VSNDN1

TA = 25°&, VIN = 12V, VSHDN1 = OV (NDle 2), unless Dlherwise noled.

CONDITIONS

MIN

VIN =12V, EXTVcc =5V, ISWITCH =lOrnA
VIN =12V
VIN =40V

-0.2
-0.2

VSENSE- =5V, VFB =1.32V (Forced)
VSENSC =5V, VFB =1.15V (Forced)
VSENSC =3.4V (Forced)
VSENSC =3.1V (Forced)
VSENSC =5.2V (Forced)
VSENSE- =4.7V (Forced)

•
•

130

•

130

130

0.6
0.8
VSHDN2 =5V
VOUT in Regulation
VOUT =OV
CT =390pF, ILOAD =700mA, VIN =10V
CL =3000pF (Pins P-Drive and N-Gate), VIN =6V

TYP
250
0
0
25
150
25
150
25
150

MAX
350

170
170
170

UNITS
mV
V
V
mV
mV
mV
mV
mV
mV

0.8
1.4
12
70
2
5
100

2
2
20
90
10
6
200

~
~
~

MIN
1.2

TYP
1.25

MAX
1.3

UNITS
V

3.17
4.85

3.30
5.05

3.43
5.25

V
V

50
4

V
V

!JS
ns

-40°& :0; TA :0; 85°& (Nole 5)
SYMBOL
VFB
VOUT

liN

PARAMETER
Feedback Voltage (LTC1159 Only)
Regulated Output Voltage
LTCI159-3.3
LTC1159-5
VIN Pin Current (Note 3)
Normal
Shutdown

IEXTvce
Vec

EXTVee Pin Current (Note 3)
Internal Regulator Voltage

VSENSE+ VSENSC
VSHON2
tOFF

Current Sense Threshold Voltage
SHDN2 Threshold
Off-Time (Note 4)

CONDITIONS
VIN =9V
ILOAD =700mA
ILOAO =700mA
VIN =12V, EXTVcc =5V
VIN =40V, EXTVcc =5V
VIN =12V, VSHON2 =2V
VIN =40V, VSHON2 =2V
EXTVec =5V, Sleep Mode
VIN =12V to 40V, EXTVee =OV, Icc =lOrnA
Low Threshold (Forced)
High Threshold (Forced)
CT =390pF, ILOAO =700mA, VIN =10V

The. denotes specifications which apply over the full operating
temperature range.
Note 1: TJ is calculated from the ambient temperature TA and power
dissipation Po according to the following formulas:
LTCI159CG, LTCI159CG-3.3, LTCI159CG-5: TJ = TA + (PD x 135°C/W)
LTCI159CN, LTCI159CN-3.3, LTCI159CN-5: TJ = TA + (Po x 80°C/W)
LTCI159CS, LTCI159CS-3.3, LTCI159CS-5: TJ = TA + (Po x 11Q°C/W)
Note 2: On LTC1159 versions which have a SHDNI pin, it must be at
ground potential for testing.
Note 3: The LTC1159 VIN and EXTVce current measurements exclude
MOSFET driver currents. When Vcc power is derived from the output via

4-156

~
~

200
300
15
25
250
4.5

125
0.8
3.5

25
150
1.4
5

~
~

~

V

175
2
6.5

mV
mV
V
!JS

EXTVee, the input current increases by (lGATECHG x Duty Cycle)/(Efficiency).
See Typical Performance Characteristics and Applications Information.
Note 4: In applications where RSENSE is placed at ground potential, the offtime increases approximately 40%.
Note 5: The LTC1159, LTCI159-3.3, and LTC1159-5 are not tested and
not quality assurance sampled at -40°C and 85°C. These specifications
are guaranteed by design and/or correlation.
Note 6: The logic-level power MOSFETs shown in Figure 1 are rated for
VOS(MAX) = 30V. For operation at VIN > 30V, use standard threshold
MOSFETs with EXTVee powered from a 12V supply. See Applications
Information.

LTC1159/LTC1 159-3.3/LTC1 159-5
YPICAl PERFORmAnCE CHARACTERISTICS
100

Load Regulation

Line Regulation

Efficiency vs Input Voltage

20

FIGURE 1 CIRCUIT
ILOAD = 1A

FIGURE 1 CIRCUIT
VIN = 24V

-20

~

\

~-40

~
-40

I---II---j-+--+-+-----f%~~

10

15 20 25 30
INPUT VOLTAGE (V)

35

40

10

15 20 25 30
INPUT VOLTAGE (V)

35

-60

............

i'--....

"""

-80

80L-~~--L--k~--~~~

o

"' ~

-100

40

o

0.5

1.0
1.5
2.0
LOAD CURRENT (A)

2.5

LTC1159-rpCOl

EXTVcc Pin Current

Operating Frequency
vs (VIN - VOUT)

VIN Pin Current
2.0

~--'----r--'----'---'

t;

i'E
6'l
~

fE
fil 1.0 1--,/b20Vthetransition losses rapidly
inc~ease ~o the point that the use of ~ high~r ROS(ON)
device with lower CRSS actually provides higher efficiency. The N-channel MOSFET losses are the greatest at
high input voltage or during a short circuit when the Nchannel duty cycle is nearly 100%.
The term (1 +a) is generally given for aMOSFET in the form
of a normalized ROS(ON) vs Temperature curve, but
a = O.OO7/a C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specified in the MOSFET
electrical characteristics. The constant k= 5can be used for
the LTC1159 to estimate the relative contributions of the
two terms in the P-channel dissipation equation:
The Schottky diode 01 shown in Figure 1 only conducts
during the dead time between the conduction of the two
power MOSFETs. 01 prevents the body diode of the
N-channel MOSFET from turning on and storing charge
during the dead time, which could cost as much as 1% in
efficiency (although there are no other harmful effects if
01 is omitted). Therefore, 01 should be selected for a
forward voltage of less than 0.6V when conducting IMAX.

and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VouTiVIN.
To prevent large voltage transients, a low ESR input
capaCitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:
CIN

CIN Required IRMS '" IMAX [VOUT(V IN - VO UT )]1/2
VIN

4-162

This formula has a maximum at VIN = 2VOUT, where
IRMS =IMAx/2. This simple worst case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capaCitor manufacturer's
ripple current ratings are often baSed on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. An additional D. 1~ ceramic capacitor may also be
required on VIN for high frequency decoupling.
The selection of COUT is driven by the required effective
series resistance (ESR). The ESR of COUT must be less than
twice the value of RSENSE for proper operation of the
LTC1159:
COUT Required ESR < 2RsENSE
Optimum efficiency is obtained by making the ESR equal to
RSENSE. Manufacturers such as Nichicon, Chemicon, and
Sprague should be considered for high performance capacitors. The OS-CON semiconductor dielectric capaCitor
available from Sanyo has the lowest ESR for its size at a
somewhat higher price. Once the ESR requirement for
COUT has been met, the RMS current rating generally far
exceeds the IRIPPLE(P-P) requirement.
In surface mount applications multiple capaCitors may
have to be paralleled to meet the capacitance, ESR, or RMS
current handling requirements of the application. Aluminum electrolytic and dry tantalum capaCitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capaCitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. For example,
if 200~/1 OV is called for in an application requiring 3mm
height, two AVX 100~/1 OV (PIN TPS01 07K01 0) could be
used. Consult the manufacturer for other specific recommendations.
At low supply voltages, a minimum value of COUT is
suggested to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is too small, the
output ripple at low frequencies will be large enough to
trip the voltage comparator. This causes the Burst Mode
operation to be activated when the LTC1159 would
normally be in continuous operation. The effect is most

LTC 1159/LTCl159-3, 3/LTCl159-5
~PPLICATlons

InFORmATion
Line Transient Response

800 I-I--++-~f----+-++-+-l

The LTC1159 has better than SOdB line rejection and is
generally impervious to large positive or negative line
voltage transients. However, one rarely occurring condition can cause the output voltage to overshoot if the proper
precautions are not observed. This condition is a negative
VIN transition of several volts followed within 100j.lS by a
positive transition of greater than 0.5V/j.lS slew rate.

'onounced with low values of RSENSE and can be
lproved by operating at higher frequencies with lower
dues of L. The output remains in regulation at all times.

The reason this condition rarely occurs is because it takes
tens of amps to slew the regulator input capacitor at this
rate! The solution is to add adiode between the cap and VIN
pins of the LTC1159 as shown in several of the typical
application circuits. If you think your system could have
this problem, add the diode. Note that in surface mount
applications it can be combined with the p-gate diode by
using a low cost common cathode dual diode.

lad Transient Response

EXTVcc Pin Connection

Nitching regulators take several cycles to respond to a
ep in DC (resistive) load current. When a load step
;curs, VOUT shifts by an amount equal to L\ILOAD x ESR,
here ESR is the effective series resistance of COUTo
ILOAD also begins to charge or discharge COUT until the
gulator loop adapts to the current change and returns
JUT to its steady state value. During this recovery time
JUT can be monitored for overshoot or ringing which
ould indicate a stability problem. The ITH external
lmponents shown in the Figure 1 circuit will provide
lequate compensation for most applications.

The LTC1159 contains an internal PNP switch connected
between the EXTVee and Vee pins. The switch closes and
supplies the Vec power whenever the EXTVee pin is higher
in voltage than the 4.5V internal regulator. This allows the
MOSFET driver and control power to be derived from the
output during normal operation and from the internal
regulator when the output is out of regulation (start-up,
short circuit).

O~-L~~~-L~~

o

4
(VIN - VOUT) VOLTAGE (V)

Figure 4. Minimum Suggested COUT

second, more severe transient is caused by switching in
ads with large (> 1~) supply bypass capacitors. The
scharged bypass capacitors are effectively put in parallel
ith COUT, causing a rapid drop in VOUT. No regulator can
iliver enough current to prevent this problem if the load
vitch resistance is low and it is driven quickly. The only
Ilution is to limit the rise time of the switch drive so that
e load rise time is limited to approximately 25 x CLOAD.
IUS a 1O~ capacitor would require a 250j.lS rise time,
niting the charging current to about 200mA.

L7lJ!J~

Significant efficiency gains can be realized by powering Vee
from the output, since the VIN current resulting from the
driver and control currents will be scaled by a factor of
(Duty Cycle)/(Efficiency). For 5V regulators this simply
means connecting the EXTVcc pin directly to VOUT. However, for 3.3V and other low voltage regulators, additional
circuitry is required to derive Vec power from the output.
The following list summarizes the four possible connections for EXTVee:
1. EXTVee Left Open. This will cause Vee to be powered
only from the internal 4.5V regulator resulting in reduced MOSFET gate drive levels and an efficiency penalty of up to 10% at high input voltages.

4-163

LTCllS9/LTCllS9-3.3/LTCllS9-S
APPLICATions InFoRmATion
2. EXTVee Connected Directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTVee Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVee
to an output-derived voltage which has been boosted to
greater than 4.5V. This can be done either with the
inductive boost winding shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics and generally provides the highest efficiency at the expense of a
slightly higher parts count.
4. EXTVce Connected to an External Supply. If an external
supply is available in the 5V to 12V range, it may be used

to power EXTVee providing it is compatible with the
MOSFET gate drive requirements. There are no restric·
tions on the EXTVee voltage relative to VIN. EXTVee ma~
be higher than VIN providing EXTVce does not exceeo
the 15V absolute maximum rating.
When driving standard threshold MOSFETs, the external supply must always be present during operation tc
prevent MOSFET failure due to insufficient gate drive,
The LTC1149 family should also be considered fOi
applications which require the use of standard threshold
MOSFETs.
Important Information About LTC1159 Adjustable
Applications

When an output voltage other than 3.3V or 5V is required,
the LTC1159 adjustable version is used with an externa'
resistive divider from VOUT to the VFB pin (Figure 6). The
regulated voltage is determined by:
VOUT = (1 +

Figure Sa. Inductive Boost Circuit for EXTVcc

Figure 5b. Capacitive Charge Pump for EXTVcc

4-164

~~) 1.25V

The VFB pin is extremely sensitive to pickup from thl
inductor switching node. Care should be taken to isolate
the feedback network from the inductor, and the 100pF
capacitor should be connected between the VFB and S-GND
pins next to the package.
In LTC1159N and LTC1159S applications with VOUT :::
5.5V, the Vee pin may self-power through the Sense pins
when SHDN2 is taken high, preventing shutdown. In these
applications, apull-down must be added to the Sense- pin
as shown in Figure 6. This pull-down effectively takes the
place of the SHDN1 pin, ensuring complete shutdown,
Note: For versions in which both the SHDN1 and SHDN2
pins are available (LTC1159G and all fixed output ver·
sions), the two pins are simply connected to each other and
driven together to guarantee complete shutdown.
The Figure6circuitcannot be used to regulate aVOUTwhict
is greater than the maximum voltage allowed on the
LTC1159 Sense pins (13V). In applications with VOUT : :
13V, RSENSE must be moved to the ground side' of the
output capacitor and load. This operates the current sense

LTC1159/LTCl159-3. 3/LTCl159-5
IPPLICATlons InFORmATion

RSENSE
0.0390

150~F

16V
OS-CON

LTC115g o F06

VaUT = (1 +

~) 1.25

VALUES SHOWN FOR VaUT = 12V12.5A

Figure 6. High Efficiency Adjustable Regulator with 5.5V < VOUT < 13V

mparator at OV common mode, increasing the off-time
proximately 40% and requiring the use of a smaller
ling capacitor CT.
rerting Regular Applications
e LTC1159 can also be used to obtain negative output
Itages from positive inputs. In these inverting applicans, the current sense resistor connects to ground while
I LTC1159 and N-channel MOSFET connections, which
luld normally go to ground, instead ride on the negative
tput. This allows the negative output voltage to be set by
I same process as in conventional applications, using
her the internal divider (LTC1159-3.3, LTC1159-5) or an
:ernal divider with the adjustable version.
ure 15 in the Typical Applications shows asynchronous
Vto -12V converter which can supply up to 1A with
tterthan 85% efficiency. By grounding the EXTVee pin in
i Figure 15 circuit, the entire 12Voutputvoltage is placed
·oss the driver and control circuits since the LTC1159
lund pins are at -12V. During start-up or short-circuit
lditions, operating power is supplied by the internal
iV regulator. The shutdown signal is level-shifted to the
Jative output rail by 03, and 04 ensures that 01 and 02
nain off during the entire shutdown sequence.

Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency =100 - (L1 + L2 + L3 + ... )
where L1, L2, etc., are the individual losses as apercentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1159 circuits: 1) LTC1159 VIN current, 2}
LTC1159 Vee current, 3) 12R losses, and 4) P-channel
transition losses.
1. LTC1159 VIN current is the DC supply current given in
the electrical characteristics which excludes MOSFET
driver and control currents. VIN current results in asmall
« 1%) loss which increases with VIN.
2. LTC1159 Vee current is the sum of the MOSFET driver
and control circuit currents. The MOSFET driver current
results from switching the gate capacitance ofthe power
MOSFETs. Each time a MOSFET gate is switched from

4-165

LTCllS9 /LTCllS9-3. 3/LTCl1 S9-S
APPLICATions InFoRmATion
. low to high to low again, a packet of charge dO moves
from Vce to ground. The resulting dQ/dt is acurrent out
of Vee which is typically much larger than the control
circuit current. In continuous mode, IGATEeHG "" f (Op +
ON), where Op and ON are the gate charges of the two
MOSFETs.
By powering EXTVee from an output-derived source, the
additional VIN current resulting from the driver and
control currents will be scaled by a factor of
(Duty Gycle)/(Efficiency). For example in a 20V to 5V
application, 10mA of Vee current results in approximately 3mAofVIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered
directly from VIN) to only afew percent.
3. 12R losses are easily predicted from the DG resistances
of the MOSFET, inductor, and current shunt. In continuous mode all of the output current flows through L
and RSENSE, but is "chopped" between the P-channel
and N-channel MOSFETs. If the two MOSFETs have
approximately the same ROS(ON), then the resistance of
one MOSFET can simply be summed with the resistances of Land RSENSE to obtain 12R losses. For
example, if each ROS(ON) = 0.10, RL = 0.150, and
RSENSE = 0.050, then the total resistance is 0.30. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A.12R losses cause the
efficiency to roll-off at high output currents.
4. Transition losses apply only to the P-channel MOSFET,
and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from:

windings. With synchronous switching, auxiliary ou
puts may be loaded without regard to the primary OUtPI
load, providing that the loop remains in continuol
mode operation.
Burst Mode operation can be suppressed at low OUtPI
currents with a simple external network which cancels tt
0.025V minimum current comparatorthreshold. This tecl
nique is also useful for eliminating audible noise frol
certain types of inductors in high current (lOUT> 5J
applications when they are lightly loaded.
An external offset is put in series with the Sense- pin j
subtractfrom the built-in 0.025Voffset. An example ofth
technique is shown in Figure 7. Two 1000 resistors al
inserted in series with the leads from the sense resisto
With the addition of R3, acurrent is generated through R
causing an offset of:
VOFFSET = VOUT (R1

~1 R3)

If VOFFSET > 0.025V, the minimum threshold will t
cancelled and Burst Mode operation is prevented frol
occurring. Since VOFFSET is constant, the maximum loa
current is also decreased by the same offset. Thus, to gl
back to the same IMAX, the value ofthe sense resistor mu:
be reduced:

75 mil
RSENSE"" _1
MAX
To prevent noise spikes from erroneously tripping tt
current comparator, a 1OOOpF capacitor is needed acro~
the Sense- and Sense+ pins.

Transition Loss"" 5(VIN)2(IMAX)(GRSS)(f)
Other losses including GIN and GOUT ESR dissipative losses,
Schottky conduction losses during dead time, and inductor
core losses, generally account for less than 2% total
additional loss.
Auxiliary Windings - Suppressing Burst Mode
Operation
The LTC1159 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in orderto extract power from auxiliary

4-166

Figure 7. Suppressing Burst Mode Operation

LTCl159/LTCl159-3.3/LTCl159-5
PPLICAnons InFORmATion
ard Layout Checklist

len laying out the printed circuit board, the following
ecklist should be used to ensure proper operation of the
C1159. These items are also illustrated graphically in
llayout diagram of Figure 8. Check the following in your
'out:
Are the signal and power grounds segregated? The
LTC1159 signal ground must connect separately to the
(-) plate OfCOUT. The other ground pin(s) should return
to the source of the N-channel MOSFET, anode of the
Schottky diode, and (-) plate of CIN, which should have
as short lead lengths as possible.
Does the LTC1159 Sense- pin connect to a point close
to RSENSE and the (+) plate of COUT? In adjustable
applications, the resistive divider R1, R2 must be connected between the (+) plate of CouTand signal ground.
Are the Sense - and Sense + leads routed together with
minimum PC trace spacing? The differential decoupling
capacitor between the two Sense pins should be as

close as possible to the LTC1159. Up to 100n may be
placed in series with each sense lead to help decouple
the Sense pins. However, when these resistors are
used, the capacitor should be no larger than 1000pF.
4) Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? An additional 0.1 JlF ceramic capacitor between VIN and power
ground may be required in some applications.
5) Is the Vee decoupling capacitor connected closely between the Vee pins of the LTC1159 and power ground?
This capacitor carries the MOSFET driver peak currents.
6) In adjustable versions, the feedback pin is very sensitive
to pickup from the switch node. Care must be taken to
isolate VFB from possible capacitive coupling of the
inductor switch signal.
7) Is the SHDN1 pin actively pulled to ground during
normal operation? SHDN1 is a high impedance pin and
must not be allowed to float.

BOLD LINES INDICATE HIGH CURRENT PATHS - - - 1N4148

+

i

~_'i

OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
VERSION ONLY

I

_. . . ++-T

L--_ _ _...:...:.._ _ _ _ _ _ _ _ _ _..--...J

LTC1159.FOB

Figure 8. LTC1159 Layout Diagram (N and S Packages)

4-167

LTCllS9/LTCllS9-3.3/LTCllS9-S

APPLICATions InFoRmATion
Troubleshooting Hints

3.3\

Since efficiency is critical to LTC1159 applications it isvery
important to verify that the circuit is functioning correctly
in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the CT pin. .

--------------------------------------------~
(a) CONTINUOUS MODE OPERATION
3.3\

In continuous mode (ILOAD >IBURST) the voltage should be
asawtooth with aO.9Vp_p swing. This voltage should never
dip below 2V as shown in Figure 9a. When the load current
is low (I LOAD < IBURST), Burst Mode operation should occur
with the CT waveform periodically falling to ground as
shown in Figure 9b.

OV
(b) Burst Mode OPERATION

LTC1159°ro

Figure 9. CT Pin 6 Waveforms

If the CT pin is observed falling to ground at high output
currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.

TYPICAL APPLICATiOnS
5V

VIN
BVTO 20V

.....---'rrt'Y'----......."'f!I"¥......-..--- VOUT

2.5V/5A

+ 330~F
6.3Vx 3
AVX

L..--------------------+-----------"""I'v---------------------'
*MAGNETICS 77120-A7 CORE, 16T 18GA. WIRE
**KRL SL-1-R020J

Figure 1D. High Efficiency BV 10 2DV InpuI2.5/5A Oulput Regulator

4-168

LTC1159'Fl0

LTCllS9 /LTCllS9-3. 3/LTCllS9-S
YPICAL APPLICATions
VIN
4VTO 20V

~ 1N4148

....- - - - - -__---''VY"''''---.-IV~~+__ VOUT

3.3v!2.5A

+ 330!,F
6.3Vx2
AVX

' - -_ _ _ _ _ _ _......._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'LTC1159.Fl1

"COl LTRON ICS CTX20-4
""KRL SL-1/2-R040J

Figure 11. 5:1 Input Range (4V to 20V) High Efficiency 3.3V/2.5A Regulator

12V

N4148

VIN
15VTO 40V

1N4148

RSENSE""

...._~'VY'-___~o.oN1a~--~-~~~A
220!,F
10Vx3
OS-CON

I~

-

10!,F

T

750pF

1:

L4--

470a

'--_ _ _ _ _ _ _ _

.------'\~----------'LTC1159.F12

"HURRICANE LAB HL-KK122T/BB
""DALE LVR-3-0.01

Figure 12. High Current, High Efficiency 15V to 40V Input 5V/10A Output Regulator

4-169

LTC,' 159ILTCl159-3. 3/LTCl159 .. 5
TYPICAL APPLICATions
VIN

15VTO 40V

150l!F
16Vx2
OS-CON

'COllTRONICS CTX50-5-KM
"IRC LO-3-0,02 ±5%

Figure 13. High Efficiency 15V to 40V Input 12V15A Output Regulator
VIN

5,5VT024V

,...t--------------t- 5VOUTPI

220l!F

Si9410DY

10Vx~

AVX

1k

RSENSE"

BAS16

-+__....__...._ 3.3V

L-_ _ _ _ _ _ _....._ _-ItJVv-_ _ _ _ _......O,02f.l
_ _ _ _ _....._ _

OUTP
....._ _ _ _ _ _ _ _"--_ _ _ _ _ _ _ _ _-.1

'HURRICANE LAB HL-8700
"KRL Sl-1-R020J

Figure 14. 17W Dual Output High Efficiency 5Vand 3.3V Regulator

4-170

LTC1159-F14

LTC1159/LTCl159-3. 3/LTCl159-5
rYPICAL APPLICATions
VIN 12V
+30%-10%
330llF
35V

T NICHICON

1N4148

MBRS140

150llF
16Vx2
OS-CON

'DALE TJ4-1 00-1 11
"IRC LR2512-01-R050-J

Figure 15. High Efficiency 12V 10 -12V 1A Converter

IELATED PARTS
ART NUMBER
rC1142

DESCRIPTION
Dual High Efficiency Synchronous Step-Down Switching Regulator

COMMENTS
Dual Version of LTC1148
Dual Version of LTC1147

rC1143

Dual High Efficiency Step-Down Switching Regulator Controller

rC1147

High Efficiency Step-Down Switching Regulator Controller

Nonsynchronous, 8-Lead, VIN ~ 16V

rC1148

High Efficiency Step-Down Switching Regulator Controller

Synchronous, VIN ~ 20V

rC1149
rC1174

High Efficiency Step-Down Switching Regulator
High Efficiency Step-Down and Inverting DC/DC Converter

Synchronous, VIN ~ 48V, for Standard Threshold FETs
O_5A SWitch, VIN ~ 18_5V, Comparator

rC1265

High Efficiency Step-Down DC/DC Converter

1.2A Switch, VIN ~ 13V, Comparator

rC1267

Dual High Efficiency Synchronous Step-Down Switching Regulators

Dual Version of LTC1159

L7lJDYJB

4-171

l-r TLE1CnH.Nf!\OI
'O-G~QIII!-.. _LT_'_'8_2_/L_T'_'_83_I_LT_'_'8_4_/L_T'_'_84_F
~
CCFL/LCD Contrast

~,

IT

Switching Regulators
FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•

The LJ®1182JLT1183 are dual current mode switching
regulators that provide the control function for Cold Cathode Fluorescent Lighting (CCFL) and Liquid Crystal Display
(LCD) Contrast. The LT1184/LT1184F provide only the
CCFL function. The ICs include high current, high efficiency
switches, an oscillator, a reference, output drive logic,
control blocks and protection circuitry. The LT1182 permits positive or negative voltage LCD contrast operation.
The LT1183 permits unipolar contrast operation and pins
out an internal reference. The LT1182/LT1183 support
grounded and floating lamp configurations. The LT1184F
supports grounded and floating lamp configurations. The
LT1184 supports only grounded lamp configurations. The

Wide Input Voltage Range: 3V to 30V
Low Quiescent Current
High Switching Frequency: 200kHz
CCFL Switch: 1.25A, LCD Switch: 625mA
Grounded or Floating Lamp Configurations
Open-Lamp Protection
Positive or Negative Contrast Capability

APPLICATions
•
•
•
•

Notebook and Palmtop Computers
Portable Instruments
Automotive Displays
Retail Terminals

D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
90% Efficient Floating CCFL Configuration with Dual Polarity LCD Contrast
UPT06mA
ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3B WITH AN
ESR > 0.50 TO PREVENT DAMAGE TO THE LT1182 HIGH-SIDE
SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON.
Cl MUST BE A LOW LOSS CAPACITOR, Cl = WIMA MKP-20
Ql, Q2 = ZETEX ZTX849 OR ROHM 2SC5001
Ll = COILTRONICS CTX21 0605
r - - -......--F--:-4~,-4r---::-I-t
L2 = COILTRONICS CTX100-4
L3 = COILTRONICS CTX02-12403
'DO NOT SUBSTITUTE COMPONENTS
COILTRONICS (407) 241-7876
01lA TO 451lA ICCFL
CURRENT GIVES
OmAT06mA
BULB CURRENT.
THIS IS EQUAL TO
0% TO 90% DUTY
CYCLE FOR THE
PWMSIGNAL.

V (PWM)
OV TO SV
1kHz PWM

R4
46.4k
1%

"'WH.........jf-"""IArv----=.

CCFL BACKLIGHT APPLICATION CIRCUITS CONTAINED IN THIS
DATA SHEET ARE COVERED BY U,S, PATENT NUMBER 5408162
AND OTHER PATENTS PENDING

.--..-......-

.....- - - - - - :C~028V
EITHER NEGCON OR POSCON
MUST BE GROUNDED.
GROUNDING NEGCON GIVES
VARIABLE POSITIVE CONTRAST
FROM 10V TO 30V.
GROUNDING POSCON GIVES
VARIABLE NEGATIVE CONTRAST
FROM -1 OV TO -30V.

r - - -...........-

'-+_......-t-....... NEGCON

C6
2.2~F

R13
BASk
1%
R14
1.21k
1%

4-172

POSCON

LTl182/LTl183/LTl184/LTl184F
)ESCRIPTIOn
_T1184/LT1184F pin out the reference for simplified proIramming of lamp current.
-he LT1182/LT1183/LT1184/LT1184F operate with input
;upply voltages from 3V to 30V. The ICs also have a
lattery supply voltage pin that operates from 4.5V to 30V.
-he LT1182/LT1183 draw 9mA typical quiescent current
vhile the LT1184/L T1184F draw 6mA typical quiescent

current. An active low shutdown pin typically reduces total
supply current to 351lA for standby operation. A 200kHz
switching frequency minimizes the size of required magnetic components. The use of current mode switching
techniques with cycle-by-cycle limiting gives high reliability and simple loop frequency compensation. The LT11821
LT1183/LT1184/LT1184F are all available in 16-pin narrow SO packages.

ABSOLUTE mAXimUm RATinGS
liN, BAT, Royer, Bulb ..............................................
~CFL Vsw, LCD Vsw ...............................................

30V
60V
,hutdown ................................................................. 6V
CCFL Input Current .............................................. 10mA
)10 Input Current (Peak, < 100ms) .................... 100mA
_T1182: FBP, FBN, LT1183: FB Pin Current.. ....... ±2mA

LT1183/LT1184/1184F: REF Pin Source Current.. .. 1mA
Junction Temperature (Note 1) ............................ 100DC
Operating Ambient Temperature Range ..... ODC to 100DC
Storage Temperature Range ................. -65 DCto 150DC
Lead Temperature (Soldering, 10 sec) .................. 300 DC

-------------.
tACKAGElORDER InFORmATiOn
TOP VIEW

ORDER PART
NUMBER

TOP VIEW
CCFL PGND

LT1182CS

CCFL Ve

ORDER PART
NUMBER
LT1183CS

AGND

AGND

SHUTDOWN

SHUTDOWN

LCDVe
LCD PGND
S PACKAGE
l6-LEAD PLASTIC SO
TJMAX =100'C. 9Jp 100'CIW
TOP VIEW
CCFL PGND

1

CCFL Ve

4

S PACKAGE
l6-LEAD PLASTIC SD
TJMAX = 100'C, 9Jp 100'CIW

ORDER PART
NUMBER

TOP VIEW

ORDER PART
NUMBER
LT1184FCS

LT1184CS

AGND
SHUTDOWN

S PACKAGE
l6-LEAD PLASTIC SO
TJMAX = 100'C, 9JA = 100'CIW

S PACKAGE
l6-LEAD PLASTIC SO
TJMAX =100'C, 9JA =100'CIW

onsult factory for Industrial and Military grade parts

L7lJ!1~

4-173

LTl182/LTl183/LTl 184/LTl 184F
ELEnRICAL CHARAOERISTICS
TA =25°C, VIN =5V, BAT =Royer =Bulb =12V, ICCFL =SHUTDOWN =CCFL VSw =Open, DlO =GND, CCFL Vc =O.5V,
(LT1182/LT1183) LCD Vc =O.5V, LCD Vsw =Open, (LT1182) FBN =FBP =GND, (LT1183) FB =GND,
(LT1183/LT1184/LT1184F) REF = Open, unless otherwise specified.
SYMBOL

PARAMETER

CONDITIONS

IQ

Supply Current

LT11821LT1183: 3V s VIN S 30V
LT1184/LT1184F: 3V SVIN S 30V

ISHDN

SHUTDOWN Supply Current

SHUTDOWN - OV, CCFL Vc - LCD Vc - Open (Note '2)
SHUTDOWN = OV, CCFL Vc = LCD Vc = Open

SHUTDOWN Input Bias Current
SHUTDOWN Threshold Voltage
f

Switching Frequency

Measured at CCFL Vswand LCD Vsw, Isw = 50mA,
ICCFL = 1001JA, CCFL Vc = Open, (LT1182) FBN = FBP =
1V, (LT1183) FB = 1V, (LT11821LT1183) LCD Vc = Open

DC(MAX)

Maximum Switch Duty Cycle

Measured at CCFL Vsw and LCD Vsw

BV

Switch Breakdown Voltage

Measured at CCFL Vsw and LCD Vsw

Switch Leakage Cu rrent

Vsw = 12V, Measured at CCFL Vsw and LCD Vsw
Vsw = 30V, Measured at CCFL Vsw and LCD Vsw

ICCFL Summing Voltage

3V SVIN S 30V, Measured on LT11821LT1183
3V SVIN S 30V, Measured on LT1184/LT1184F

t1ICCFL Summing Voltage for
t1lnput Programming Current

ICCFL = OIJA to 100IJA

CCFL Vc Offset Sink Current

CCFL Vc = 1.5V, Positive Current Measured into Pin

t1CCFL Vc Source Current for
t1ICCFL Programming Current

ICCFL = 251JA, 501JA, 751JA, 1001JA,
CCFL Vc = 1.5V

CCFL Vc to 010 Current Servo Ratio

010 = 5mA out of Pin, Measure Ivc at CCFL Vc = 1.5V

CCFL Vc Low Clamp Voltage

VSAT- VSULS = Bulb Protect Servo Voltage

CCFL Vc High Clamp Voltage
CCFL Vc Switching Threshold

ICCFL = 100IJA
CCFL Vsw DC = 0%

CCFL High-Side Sense Servo Current

ICCFL = 1OO~, Ivc = O~ at CCFL Vc = 1.5V

CCFL High-Side Sense Servo Current
Line Regulation

BAT = 5V to 30V, ICCFL = 100~,
Ivc = O~ at CCFL Vc = 1.5V
Current Measured into BAT and Royer Pins

CCFL High-Side Sense Supply Current
Bulb Protect Servo Voltage

ICCFL = 1OO~, Ivc = O~ at CCFL Vc = 1.5V,
Servo Voltage Measured Between BAT and Bulb Pins

Bulb Input Bias Current
IUM1

CCFL Switch Current Limit

ICCFL = .100~, Ivc = O~ at CCFL Vc = 1.5V
Duty Cycle = 50%
Duty Cycle = 75% (Note 3)

VSAT1
t1IQ
t1ISW1

CCFL Switch On-Resistance

CCFL Isw= 1A

Supply Current Increase During
CCFL Switch On-Time

CCFL Isw = 1A

VREF

Reference Voltage

Measured at REF (Pin 11) on LT1183/LT1184/LT1184F

Reference Output Impedance

Measured at REF (Pin 11) on LT1183
Measured at REF (Pin 11) on LT1184/LT1184F

4-174

TYP

MAX

9
6

14
9.5

mA
mA

35

70

IJA

3

6

0.6

0.85

1.2

IJA
V

175

200

225

kHz

160

200
85
85

240

kHz

80
75
60

70

MIN

••
•
•
•

%
%
V
20
40

•
•
•
•
•
•
•
•
•
•

••

0.41
0.37

0.45
0.45

0.49
0.54

IJA
IJA
V
V

0.425
0.385

0.465
0.465

0.505
0.555

V
V

5

15

mV
IJA
IJA/IJA

-5

5

15

4.70

4.95

5.20

99

104

0.1

0.3
2.4

lJA/mA
V
V

94
1.7

2.1

0.6

0.95

1.3

V

0.93

1.00

1.07

0.1

0.16

A
%/V

50

100

150

6.5

7.0

7.5

IJA
V

5

9

~

1.25
0.9

1.9
1.6

3.0
2.6

A
A

0.6

1.0

n

20

30

mAlA

1.244
1.244

1.264
1.274

V
V

45
15

70
30

n
n

•

•
••

UNITS

1.224
1.214
20
5

LTl182/LTl183/LTl184/LTl184F
5LEORICAL CHARAOERISTICS
=25°C, VIN = 5V, BAT = Royer = Bulb = 12V, ICCFL = SHUTDOWN = CCFl Vsw = Open, DIO = GND, CCFL Vc = O.5V,
_T1182/LT1183) LCD Vc = O.5V, LCD Vsw = Open, (lT1182) FBN = FBP = GND, (lT1183) FB = GND,
_T1183/LT1184/lT1184F) REF = Open, unless otherwise specified.

A

YMBOL

EFI

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VREF -ICCFL Summing Voltage

Measured on LT1183

0.760
0.725

0.795
0.795

0.830
0.865

V
V

VREF -ICCFL Summing Voltage

Measured on LT1184/LT1184F

0.775
0.775

0.810
0.845

V
V

LCD FBP/FB Reference Voltage

LT1182: Measured at FBP Pin, FBN =IV, LCD Vc =0.8V
LT1183: Measured at FB Pin, LCD Vc =0.8V

1.244
1.244

1.264
1.274

V
V

REFI Voltage Line Regulation

3V ~ VIN ~ 30V, LCD Vc =0.8V
LT1182: FBP =REF1, FBN =1V, LCD Vc =0.8V
LT1183: FB =REF1, LCD Vc =0.8V

0.01

0.03

'ioN

0.35
-12
-12

1.0
-4
-1

J,1A
mV
mV

0.01

0.2

'ioN

FBP/FB Input Bias Current
LCD FBN/FB Offset Voltage

LT1182: Measured at FBN Pin, FBP =OV, LCD Vc =0.8V
LT1183: Measured at FB Pin, LCD Vc =0.8V

Offset Voltage Line Regulation

3V ~ VIN ~ 30V, LCD Vc =0.8V

FBN/FB Input Bias Current

LT1182: FBN =Offset Voltage, FBP =OV, LCD Vc =0.8V
LT1183: FB =Offset Voltage, LCD Vc =0.8V

FBP/FB to LCD Vc Transconductance

LT1182: dlvc =±25J,1A, FBN = 1V
LT1183: dlvc = ±25J,1A

FBN/FB to LCD Vc Transconductance

LT1182: dlvc =±25J,1A, FBP = GND
LT1183: dlvc =±25J,1A

LCD Error Amplifier Source Current

LT1182: FBP =FBN = IV or 0.25V,
LT1183: FB = lVorO.25V

LCD Error Amplifier Sink Current

LT1182: FBP = FBN = 1.5Vor-0.25V,
LT1183: FB =1.5Vor-0.25V

LCD Vc Low Clamp Voltage

LT1182: FBP =FBN =1.5V, LT1183: FB = 1.5V

LCD Vc High Clamp Voltage

LT1182: FBP =FBN =1V, LT1183: FB =IV

LCD Vc Switching Threshold

LT1182: FBP = FBN =IV, LT1183: FB =IV, Vsw DC = 0%

LCD Switch Current Limit

Duty Cycle = 50%
Duty Cycle =75% (Note 3)

;AT2

LCD Switch On-Resistance

LCD Isw =0.5A

~IQ

Supply Current Increase During
LCD Switch On-Time

LCD Isw = 0.5A

Switch Minimum On-Time

Measured at CCFL Vsw and LCD Vsw

n

1M2

ISW2

Ie • denotes specifications which apply over the specified operating
mperature range.
lie 1: TJ is calculated from the ambient temperature TA and power
ssipation PD according to the following formula:
'1182CS/LTI183CS/LT1184CS/LTI184FCS: TJ = TA + (PD x 100°C/W)

L7lJ!J~

• 0.740
• 0.705
1.224
• 1.214
•
• -20
• -27
•
• -3.0
650
• 500
550
400
• 50
•
• 35
•
•
•

1.7
0.6
0.625
0.400

-1.0
900
900

1150
1300

J,1A
J.IIT1hos
J.IIT1hos

800
800

1050
1200

J.IIT1hos
J.IIT1hos

100

175

J,1A

100

175

J,1A

0.01

0.3

V

2.0

2.4

V

0.95

1.3

V

1.00
0.85

1.5
1.3

A
A

1.0

1.65

20

30

0.45

Q

mAlA

J.IS

Nole 2: Does not include switch leakage.
Nole 3: For duty cycles (DC) between 50% and 75%, minimum
guaranteed switch current is given by IUM = 1.4(1.393 - DC) for the CCFL
regulator and IUM = 0.7(1.393 - DC ) for the LCD contrast regulator due to
internal slope compensation circuitry.

4-175

LTl182/LTl183/LTl 184/LTl 184F
TYPICAL PERFORmAnCE CHARAOERISTICS
10

14



u

"::i
0..

100

13

90

12

80

1....

11
9

,VIN=30V

p-

8

:::>

u

VIN=3V

r-

VIN=3V

I I
I I

I\.
"

70

z

I I

50

r-.

;: 40
0

....:::>0

0..

:::>

:c
 1,0

:3
o

~

~

~

........

0.9

z

'"

~ 0,7

'" ........ ........

95

93

230

93

220

~ 89

91

91
N"

~ 89

u

~

87
83

:::>

0 25 50 75 100125150175
TEMPERATURE (OC)

LCD Duly Cycle vs Temperature

LCD Frequency vs Temperature
240

'"~

1"""0

LT1182GOS

CCFL Duly Cycle vs Temperature

~

'"

VIN = 3V

160
-75 -50-25

95

85

~

170

LT1t82G04

~
u
>u

r-VIN =30V

rC
u
'-' 180

0.6
-75 -50-25 0 25 50 75 100125150175
TEMPERATURE (oG)

-75-50-25 0 25 50 75100125150175
TEMPERATURE (OC)

-

IE 190

:c
u

~

""'"

-

5
0
0

87
85
83

:l 81
79

~

~

...... ......

,/

77

0 25 50 75 100125 150175
TEMPERATURE (oG)

75
-75 -50 -25 0 25 50 75 100 125150170
TEMPERATURE (OC)
LTI182·Gt19

4-176

LTl182/LTl183/LTl184/LTl184F
rYPICAL PERFORmAnCE CHARACTERISTICS
ICCFl Summing Voltage
vs Temperature
0.53
0.52
0.51
0.50
0.49

~
w

CCFL Vc Offset Sink Current
vs Temperature

5
4
3

~ 0048

§; 0.47 l -I - f-VIN=30~
'" 0.46
~

ICCFL Summing Voltage
Load Regulation

A

'"

A
,/
~. VIN = 5V
A

:[

2

w

1

:;;:

-

T ~-5~oC
r-.. -.
r-.. ...... T =1 250C'::':' ~ r-

V

~ a "011:: t::-..
.....

~ =~
'" -3

0.45

.......

Z

~VIN=3V
0.44
~
~ 0.43
V 1.#
~ 0.42
l;'
u
0.41
0.40
0.39
0.38
-75-50-250 25 50 75100125150175
TEMPERATURE (OC)

~

:;;

-4
~ -5
~ -6
.9 -7
-

iE
a::
a::

~
~

=>
'-'

tw

i'-. l""-

'"

r-....

........ ,...,..

-'
~

'-'

'-'

Wl00lml~l~lwmo

h

1. 5V I-- I--

/I

CCFl Vc = 1.0V

i"'-.

It
z
in
-f;?

vr

I

III.

71
/,1/

........

0

~

.......
o m

10
9

-

/
/

CfFl YC = ~.5V

0
-1

-2
-3

I

-75 -50

-~5

ICCfL PROGRAMMING CURRENT (fLA)

I I
I

0 25 50 75 100 125150175
TEMPERATURE (OC)
LT1182·G12

~CCFL Vc Source Current for
~ICCFL Programming Current

Positive DID Voltage
vs Temperature

vs Temperature

Negative 010 Voltage
vs Temperature

1.2

5.10

1.6

'1

i~ 5.05

1.0

;!Z

~~
iB

!~

4.95

:~
~ffi

r--.

-V

w

ICCfL - lOOfLA

5.00 I--I-~

~

;'"

r-

ICCfL - 50fLA

>
0.6
0
Ci
';!;
;:: 0.4
in

ICCfL = 10fLA
4.90

:~

i

0.8

0

r--...

~

1(010) = lmA

I(DI0)=5mA-

~:::--

....... .........

.........

~ 102
~ 100 1--1(010) = 1~

~
g;;

_i---'"

". I'"'"

~
I(DlO) = 5mA

98

=>
'-'

:!::

2.4

~ 0.25

~ 2.3
w

~

~

0.20

~
Co.

:5

0.15

:s:
g

0.10

~

'-'

l- I -I -

-'
~

'-' 0.05

0 25 50 75 100125 150175
TEMPERATURE (OC)

2.2

2.1

~ 2.0

'-'

96
95
-75 -50-25

>

o

0 25 50 75 100125150175
TEMPERATURE (OC)

CCFL Vc High Clamp Voltage
vs Temperature

0.30

-f;?

o 97
Ci

-75 -50-25

CCFL Vc Low Clamp Voltage
vs Temperature

0

-

r......

o

-75-50-25 0 25 50 75 100125150175
TEMPERATURE (OC)

'"c:;

t'-r--..

~

0.2



0.2

4.80
-75 -50 -25 0 25 50 75 100 125 150 175
TEMPERATURE (OC)

(/J

;'"
Ci

0

~4.85

- :at
r-- r-.. ""':(010) = 10mA

~ 1.2
w

0-



>

0.02 r--+--I-1--I-+--+-T--I

0.1~

9

t:t;d;;±=t::t:r::rJ

25 50 75 100125 150175
TEMPERATURE (OC)

t--...

2.1

.......

r-....
........

1.9

:--..

1.8

1.7
-75 -50-25 0 25 50 75 100 125 150175
TEMPERATURE (OC)

-75 -50 -25 a 25 50 75 100 125
TEMPERATURE (OC)

a

2.2

~ 2.0

1-+--1-+--+-+--+-+--1

8
...J

0.6
-75-50-25

~

'"=::,

>

........

0..

-z, 0.03 r--+--I-1--I-+--+-T--I

o

2.3

...J

0.05 1--+--I-1--I-+--+-+--I

~

<.>
<.>

2.4
~
w

§ O.OS 1--+--I-1--I-+--+-+--1
'"i3 0.07 1--+--I-1--I-+--+-+--I
~

........

'"
z 0.9
:;:
1:' O.S

~

LCD Vc High Clamp Voltage
vs Temperature

0.09 r--r-l-1--I-+--+-T--1

:I:

-J:

LCD Vc Low Clamp Voltage
vs Temperature

LT1182·Q19

LT1182·S21

LCD Vc Switching Threshold
Voltage vs Temperature
~

1.3

w

~ 1.2

o

:I:

ffl 1.0

a:
~
'" 0.9
z

~

0.8

-J:

0.7

~

is 0.140

iIi
1.040
a:

~

a:

::>

1\

~ 1.020

'I\.

::>

z

~ 1.000

"-

e'" 0.980
~

"

:I:

'"

-

/

,/

V
,/

~ 0.100

z

r-""

~ 0.080

/

'"~z
w

a

~

V

........

/

0.060
0.040

:I:

'"

:;: 0.020

~

0.6
-75-50 -25 0 25 50 75 100 125 150175
TEMPERATURE (OC)

0.120

ffi

:;: 0.960

<.>

9

>" 0.160

I-

~

...J

CCFL High-Side Sense Null Current
Line Regulation vs Temperature

1.060

g

I\.

9~ 1.1

~

CCFL High-Side Sense Null
Current vs Temperature

~

S

0.940
-75 -50 -25

a

25 50 75 100 125 150 175
TEMPERATURE (OC)

S 0.000

-75 -50-25 0 25 50 75 100125 150
TEMPERATURE (OC)

m

LT1182·G23

CCFL High-Side Sense Supply
Current vs Temperature

Bulb Protect Servo Voltage
vs Temperature

~150r-~.-.--.-r-.-'-.--~

7.5

~140r-+-+-1--r-r-+-I~--~

~

7.4
7.3

~ 120 1-+-1-+-+-1-1-+-1-+-1

'"i3

~~ 100
110 t=l~:::~E:Ell~=tl

>
7.1
~
Eli 7.0

w

~

130 1-+-1-+-+-1-1-+-1-+-1

::>

'"~

901-+-1-+-+-1-1-+-1-+-1

~

SOr-T-1--r-+-+-r-T-1--r-1

~

G

:;:
~

S

701-+-1-+-+-1-1-+-1-+-1
601-+-1-+-+-1-1-+-1-+-1
50~~~~-L-L~~~--~

-75 -50 -25 0 25 50 75 100 125 150 175
TEMPERATURE (OC)
LT1182·G2fj

4-178

w

0

'"
~
0

I-

6.9

5 6.7
::>
co

10

6.6

~

1/

7.2

6.S
a:
0..

Bulb Input Bias Current
vs Temperature

ICCFL = 1001lA

........ r-

/'
ICCFL = 501lA

-

-+-

vV

I-

iIi
a:

V

a:

::>
<.>

-

!!i!
as

~

I-

i--'"

,/

V

::>
0..

~

5::>

ICC~L .\ 01lA

co

6.5
-75 -50 -25 0 25 50 75 100 125 150 175
TEMPERATURE (OC)
LT1182·G26

o

-75 -50 -25 0 25 50 75 100 125 150
TEMPERATURE (0C)

m

LT11B2·G27

LTl 182/LTl 183/LTl 184/LTl 184F
rYPICAL PERFORmAnCE CHARACTERISTICS
LCD FBP Reference
vs Temperature

FBP Reference Voltage Line
Regulation vs Temperature

1.274

~ 0.03

1.0

z

0.9

~

~ 1.264

'"~

~
~ 1.254

:::>

w

,/

~

51.244

~
E 1.234

,...- ,.-

0.025



u

::J

~ 0.015

V~

'"
«
OJ

I-

:::>

~ 0.010

,
31.224

w
u

"

i
z

0.005

~

-9
I"....
':; -11
........
~ -13
II"--..
~ -15
....... t-..
~ -17
~ -19
~ -21
u
-' -23
-25
-27
-75-50-25 0 25 50 75100125150175
TEMPERATURE (OC)

0.3

~

0.2

-

-

-I--

o

-75-50-25 0 25 50 75100125150175
TEMPERATURE (OC)

LCD FBN Offset Voltage
vs Temperature
-

~

-.

f--

0.4

"-

o

1.214
-75-50-25 0 25 50 75 100125150175
TEMPERATURE (0C)

-1
-3
-5
-7

-

0.6

0.5

0.1

a:

§.

FBP Input Bias Current
vs Temperature

-75 -50 -25 0 25 50 75 100 125 150175
TEMPERATURE (0C)

FBN Input Bias Current
vs Temperature

FBP to LCD Vc Transconductance
vs Temperature

3.0

~

1300



z

w

~
a: 2.0
a:

~ 1000

u

8

« 1.5

'"OJ
I-

:::>

"-

1.0

~

I -I-

z

IE 0.5

'"
~I-

---

~

900

700

~
"-

600

IE

-75 -50-25 0 25 50 75 100125150175
TEMPERATURE (0C)

.......

800

'"

:oJ

o

I--

500
-75 -50-25

-

0 25 50 75 100125 150175
TEMPERATURE (OC)

lT1182'G32

FBN to LCD Vc Transconductance
vs Temperature

LT1182'G33

LT1184/84F REF Output
Impedance vs Temperature

LT1183 REF Output Impedance
vs Temperature

~ 1200

70

~ 1100

65

9:
w

u

60

«

«

55

9:

w

z

1000

Ea

900

--

800

'-

700

"

600

:::>

"I:::>
0

w

0 25 50 75 100125150175
TEMPERATURE eC)

u

z

~

50

40

I-

V

20

:::>

~

...... V

:::>

./

'"a:w
~

,.- V

a:

35

'"
'"

30

..~

25

'3

15

~

20
-75 -50 -25 0 25 50 75 100 125150 175
TEMPERATURE (OC)
LT1182'G35

L7lJ!J~

25

'"~

45

~

'3

500
400
-75 -50-25

"~
I-

30

10

I--

,...- V
:,....-

5

-75 -50 -25 0 25 50 75 100 125150175
TEMPERATURE (OC)
LT1182·G36

4-179

•

LTl 182/LTl 183/LTl 184/LTl 184F
TYPICAL PERFORmAnCE CHARAOERISTICS
LCD Vsw Sat Voltage
vs Switch Current

CCFL Vsw Sat Voltage
vs Switch Current

CCFL Vsw Current Limit
vs Duty Cycle

2.0 , . - - . , - - - - r - - , - - - - . - - - - - .

1.0

2.5

0.9
~

0.8

T=25"C

! ~::

T=125"C~T=-5"C

>

!;;c 0.5
--

w

C!l

«

l:i:i

CD

70
60

~ 50

12 40
30
20

\

\
\

\

"-

D.

I'
I"""'- '-

,....

10
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CCFL Isw (A)

o

o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LCD Isw (A)

LTl182/LTl183/LTl184/LTl184F

Pin FunOlons
LT1182/LT1183/L T1184/LT1184F
CCFL PGNO (Pin 1): This pin is the emitter of an internal
NPN power switch. CCFL switch current flows through
this pin and permits internal, switch-current sensing. The
regulators provide a separate analog ground and power
ground(s) to isolate high current ground paths from low
current signal paths. Linear Technology recommends the
use of star-ground layout techniques.
ICCFL (Pin 2):This pin isthe inputto the CCFL lamp current
programming circuit. This pin internally reguiatest0450mV
(LT1182/LT1183) or 465mV (LT1184/LT1184F). The pin
accepts a DC input current signal of OIJA to 100IJA full
scale. This input signal is converted to a OIJA to 500IJA
source current at the CCFL Vc pin. By shunt regulating the
ICCFL pin, the input programming current can be set with
DAC, PWM or potentiometer control. As input programming current increases, the regulated lamp current increases. For a typical 6mA lamp, the range of input
programming current is about OIJA to 501JA.

010 (Pin 3): This pin is the common connection between
the cathode and anode of two internal diodes. The remaining terminals of the two diodes connect to ground. In a
grounded lamp configuration, 010 connects to the low
voltage side of the lamp. Bidirectional lamp current flows
in the 010 pin and thus the diodes conduct alternately on
half cycles. Lamp current is controlled by monitoring onehalf ofthe average lamp current. The diode conducting on
negative half cycles has one-tenth of its current diverted to
the CCFL Vc pin. This current nulls against the source
current provided by the lamp-current programmer circuit.
1\ single capacitor on the CCFL Vc pin provides both stable
loop compensation and an averaging function to the halfNave-rectified sinusoidal lamp current. Therefore, input
programming current relates to one-half of average lamp
~urrent. This scheme reduces the number of loop compensation components and permits faster loop transient
response in comparison to previously published circuits.
If a floating-lamp configuration is used, ground the 010
pin.
CeFL Vc (Pin 4): This pin is the output of the lamp current
orogrammer circuit and the input ofthe current com para-

tor for the CCFL regulator. Its uses include frequency
compensation, lamp-current averaging for grounded lamp
circuits, and current limiting. The voltage on the CCFL Vc
pin determines the current trip level for switch turnoff.
During normal operation this pin sits at avoltage between
0.95V (zero switch current) and 2.0V (maximum switch
current) with respect to analog ground (AGND). This pin
has a high impedance output and permits external voltage
clamping to adjust current limit. A single capacitor to
ground provides stable loop compensation. This simplified loop compensation method permits the CCFL regulator to exhibit single-pole transient response behavior and
virtually eliminates transformer output overshoot.
AGNO (Pin 5): This pin is the low current analog ground.
It is the negative sense terminal for the internal 1.24V
reference and the ICCFL summing voltage in the LT1182/
LT1183/LT1184/LT1184F. It is also a sense terminal for
the LCD dual input error amplifier in the LT1182/LT1183 . . , .
Connect external feedback divider networks thatterminate . .
to ground and frequency compensation components that
terminate to ground directly to this pin for best regulation
and performance.
SHUTDOWN (Pin 6): Pulling this pin low causes complete
regulator shutdown with quiescent current typically reduced to 351JA. The nominal threshold voltage for this pin
is 0.85V. If the pin is not used, it can float high or be pulled
to a logic high level (maximum of 6V). Carefully evaluate
active operation when allowing the pin to float high.
Capacitive coupling into the pin from switching transients
could cause erratic operation.
CCFL Vsw (Pin 16): This pin is the collector of the internal
NPN power switch for the CCFL regulator. The power
switch provides a minimum of 1.25A. Maximum switch
current is a function of duty cycle as internal slope compensation ensures stability with duty cycles greater than
50%. Using adriver loop to automatically adapt base drive
current to the minimum required to keep the switch in a
quasi-saturation state yields fast switching times and high
efficiency operation. The ratio of switch current to driver
current is about 50:1.

4-181

LTl182/LTl183/LTl 184/LTl 184F

Pin FunCTions
Bulb (Pin 15): This pin connects to the low side of a 7V
threshold comparator between the BAT and Bulb pins.
This circuit sets the maximum voltage level across the
primary side of the Royer converter under all operating
conditions and limits the maximum secondary output
under start-up conditions or open lamp conditions. This
eases transformer voltage rating requirements. Set the
voltage limitto insure lamp start-up with worst-case, lamp
start voltages and cold-temperature system operating
conditions. The Bulb pin connects to the junction of an
external divider network. The divider network connects
from the center tap of the Royer transformer or the actual
battery supply voltage to the top side ofthe current source
"tail inductor". A capacitor across the top of the divider
network filters switching ripple and sets a time constant
that determines how quickly the clamp activates. When
the comparator activates, sink current is generated to pull
the CCFL Vc pin down. This action transfers the entire
regulator loop from current mode operation into voltage
mode operation.

BAT (Pin 14): This pin connects to the battery or battery
charger voltage from which the CCFL Royer converter and
LCD contrast converter operate. This voltage is typically
higher than the VIN supply voltage but can be equal or less
than VIN. However, the BAT voltage must be at least 2.1 V
greater than the internal2.4V regulator or 4.5V minimum
up to 30V maximum. This pin provides biasing for the
lamp current programming block, is used with the Royer
pin for floating lamp configurations, and connects to one
input for the open lamp protection circuitry. For floating
lamp configurations, this pin is the non inverting terminal
of a high-side current sense amplifier. The typical quiescent current is 50J.IA into the pin. The BAT and Royer pins
monitor the primary side Royer converter current through
an internal 0.1 n top side current sense resistor. AOA to 1A
primary side, center tap converter current is translated to
an input signal range of OmV to 100mV for the current
sense amplifier. This input range translates to a OJ.IA to
500J.IAsink current at the CCFL Vc pin that nulls againstthe
source current provided by the programmer circuit. The
BAT pin also connects to the top side of an internal clamp
between the BAT and Bulb pins.

4-182

Royer (Pin 13): This pin connects to the center-tapped
primary of the Royer converter and is used with the BAT
pin in afloating lamp configuration where lamp current is
controlled by sensing Royer primary side converter current. This pin is the inverting terminal of a high-side
current sense amplifier. The typical quiescent current is
50J.IA into the pin. If the CCFL regulator is not used in a
floating lamp configuration, tie the Royer and BAT pins
together. This pin is only available on the LT1182/LT11831
LT1184F.
(Pin 12): This pin is the supply pin for the LT11821
LT1183/LT1184/LT1184F. The les accept an input voltage
range of 3V minimum to 30V maximum with little change
in quiescent current (zero switch current). An internal,
low dropout regulator provides a 2.4V supply for most of
the internal circuitry. Supply current increases as switch
current increases at a rate approximately 1/50 of switch
current. This corresponds to aforced Beta of 50 for each
switch. The ICs incorporate undervoltage lockout by sensing regulator dropout and lockout switching for input
voltages below 2.5V. Hysteresis is not used to maximize
the useful range of input voltage. The typical input voltage
is a 3.3V or 5V logic supply.
VIN

LT1182/LT1183
LCD Vc (Pin 7): This pin is the output of the LCD contrast
error amplifier and the input of the current comparator for
the LCD contrast regulator. Its uses include frequency
compensation and current limiting. The voltage on the
LCD Vc pin determines the current trip level for switch
turnoff. During normal operation, this pin sits at avoltage
between 0.95V (zero switch current) and 2.0V (maximum
switch current). The LCD Vc pin has a high impedance
output and permits external voltage clamping to adjust
current limit. A series RIC network to ground provides
stable loop compensation.
LCD PGND (Pin 8): This pin is the emitter of an internal
NPN power switch. LCD contrast switch current flows
through this pin and permits internal, switch-current
sensing. The regulators provide aseparate analog ground
and powerground(s} to isolate high current ground paths
from low current signal paths. Linear Technology recommends star-ground layout techniques.

LTl182/LTl183/LTl184/LTl184F
.CD Vsw (Pin 9): This pin is the collector of the internal
JPN power switch for the LCD contrast regulator. The
lower switch provides a minimum of 625mA. Maximum
.witch current is afunction of duty cycle as internal slope
:ompensation ensures stability with duty cycles greater
han 50%. Using adriver loop to automatically adapt base
Irive current to the minimum required to keep the switch
na quasi-saturation state yields fast switching times and
ligh efficiency operation. The ratio of switch current to
Iriver current is about 50:1.

.T1182
:ON (Pin 10): This pin is the noninverting terminal for the
legative contrast control error amplifier. The inverting
erminal is offset from ground by -12mV and defines the
irror amplifier output state under start-up conditions. The
BN pin acts as a summing junction for a resistor divider
letwork. Input bias current for this pin is typically 1~
lowing out of the pin. If this pin is not used, force FBN to
lreater than 0.5V to deactivate the negative contrast
:ontrol input stage. The proximity of FBN to the LCD Vsw
lin makes it sensitive to ringing on the switch pin. Asmall
:apacitor (0.01!lf) from FBN to ground filters switching
ipple.
:OP (Pin 11): This pin is the inverting terminal for the
lositive contrast control error amplifier. The noninverting
erminal is tied to an internal1.244V reference. Input bias
urrent for this pin is typically 0.5~ flowing into the pin.
fthis pin is not used, ground FBPto deactivate the positive
ontrast control input stage. The proximity of FBP to the
.CD Vsw pin makes it sensitive to ringing on the switch
lin. Asmall capacitor (0.01!lf) from FBP to ground filters
witching ripple.

.T1183

amplifier and the inverting terminal for the positive-contrasterroramplifier.ln comparison to the LT1182, the FBN
and the FBP pins tie together and come outas one pin. This
scheme permits one polarity of contrast to be regulated.
The proximity of FB to the LCD Vsw pin makes it sensitive
to ringing on the switch pin. A small capacitor (0.01!lf)
from FB to ground filters switching ripple.
The FB pin requires attention to start-up conditions when
generating negative contrast voltages. The pin has two
stable operating points; regulating to 1.244V for positive
contrast voltages or regulating to -12mV for negative
contrast voltages. Under start-up conditions, the FB pin
heads to a positive voltage. If negative contrast voltages
are generated, tie a diode from the FB pin to ground. This
ensures that the FB pin will clamp before reaching the
positive reference voltage. Switching action then pulls the
FB pin back to its normal servo voltage.

l T1183/lT1184/lT1184F
REF (Pin 11): This pin brings outthe 1.244V reference. Its
functions include the programming of negative contrast
voltages with an external resistor divider network (LT1183
only) and the programming of lamp current for the ICCFL
pin. LTC does not recommend using the REF pin for both
functions at once. The REF pin has a typical output
impedance of 450 on the LT1183 and a typical output
impedance of 150 on the LT1184/LT1184F. Reference
load current should be limited to afew hundred microamperes, otherwise reference regulation will be degraded.
REF is used to generate the maximum programming
current for the ICCFL pin by placing a resistor between the
pins. PWM or DAC control subtracts from the maximum
programming current. Asmall decoupling capacitor (0.1 uF)
is recommended to filter switching transients .

:0 (Pin 10): This pin is the common connection between
he non inverting terminal for the negative contrast error

4-183

LTl 182/LTl 183/LTl 184/LTl 184F
BLOCK DIAGRAm
lT1182/lT1183 CCFl/lCD Contrast Regulator Top level810ck Diagram
BAT
14

ROYER
13

GAIN =4.4

LCD LCD
PGND Vc

FBP

FBN

ICCFL

LT1183: FBP AND FBN ARE TIED TOGETHER TO CREATE FB
AT PIN 10. THE REFERENCE IS BROUGHT OUT TO PIN 11.

4-184

AGND

010

BULB

CCFL
Vc

1
CCFL
PGND
1182B001

LTl182/LTl183/LTl184/LTl184F
BLOCK DIAGRAm
LT1184/LT1184F CCFL Regulator Top Level Block Diagram
ROYER
13
LT1184: HIGH·SIDE SENSE RESISTOR
R4 AND GM AMPLIFIER ARE REMOVED.
PIN 131S NO CONNECT.

•

GAIN =4.4

11
REF

010

LTl184/LT1184F: REFERENCE IS BROUGHT ouno PIN 1.
PINS 7,8,9,10 ARE NO CONNECT.

BULB

4
CCFL
Vc

1
CCFL
PGND
11846002

APPLICATions InFORmATion
Introduction
~urrent generation portable computers and instruments
Jse backlit Liquid Crystal Displays (LCOs), These displays
llso appear in applications extending to medical equipnent, automobiles, gas pumps, and retail terminals, Cold
~athode Fluorescent Lamps (CCFLs) provide the highest
iVailable ~fficiency in backlighting the display, Providing
:he most light outforthe least amount of input power is the
nost important goal. These lamps require high voltage AC
:0 operate, mandating an efficient high voltage OC/AC

.L7lJ!J~

converter. The lamps operate from DC, but migration
effects damage the lamp and shorten its lifetime, Lamp
drive should contain zero OC component In addition to
g~od ,efficiency, the converter should deliver the lamp
dnve mthe form of a sine wave, This minimizes EMI and
RF emissions. Such emissions can interfere with other
devices and can also degrade overall operating efficiency.
Sinusoidal CCFL drive maximizes current-to-light conver~ion i~ the lamp. The circuit should also permit lamp
mtenslty control from zero to full brightness with no
hysteresis or "pop-on" .

4-185

LTl182/LTl183/LTl184/LTl184F
APPLICATions InFoRmATion
Manufacturers offer a wide array of monochrome and
color displays. LCD display types include passive matrix
and active matrix. These displays differ in operating voltage polarity (positive and negative contrast voltage displays), operating voltage range, contrast adjust range, and
power consumption. LCD contrast supplies must regulate, provide output adjustment over a significant range,
operate over a wide input voltage range, and provide load
currents from milliamps to tens of milliamps.
The small size and battery-powered operation associated
with LCD equipped apparatus dictate low component
count a'ld high efficiency for these circuits. Size constraints place severe limitations on circuit architecture and
long battery life is apriority. Laptop and handheld portable
computers offer an excellent example. The CCFL and its
power supply are responsible for almost 50% of the
battery drain. Displays found in newer color machines can
have acontrast powersupply battery drain as high as 20%.
Additionally, all components including PC board and hardware, usually must fit within the LCD enclosure with a
height restriction of 5mm to 10mm.
The CCFL switching regulator in the LT1182/LT11831
LT1184/LT1184F typically drives an inductor that acts as
aswitched mode current source fora current driven Royer
class converter with efficiencies as high as 90%. The
control loop forces the regulatorto pulse-width modulate
the inductor's average current to maintain constant current in the lamp. The constant current's value, and thus
lamp intensity is programmable. This drive technique
provides a wide range of intensity control. A unique lamp
current programming block permits either groundedlamp or floating-lamp configurations. Grounded-lamp circuits directly control one-half of actual lamp current.
Floating-lamp circuits directly control the Royer's primary
side converter current. Floating-lamp circuits provide
differential drive to the lamp and reduce the loss from stray
lamp-to-framecapacitance, extending illumination range.
The LCD contrast switching regulator in the LT11821
LT1183 is typically configured as afly back converter and
generates a bias supply for contrast control. Other topology choices for generating the bias supply include aboost
converter or aboost/charge pump converter. The supply's
variable output permits adjustment of contrast for the

4-186

majority of available displays. Some newer types of displays require afairly constant supply voltage and provide
contrastadjustmentthrough adigital control pin. Aunique,
dual polarity, error amplifier and the selection of aflyback
converter topology allow either positive or negative LCD
contrast voltages to be generated with minor circuit
changes. The difference between the LT1182 and LT1183
is found in the pinout for the inputs of the LCD contrast
error amplifier. The LT1182 brings out the error amplifier
inputs individually for setting up positive and negative
polarity contrast capability. This feature allows an output
connector to determine the choice of contrast operating
polarity by aground connection. The LT1183 ties the error
amplifier inputs together and brings out an internal reference. The reference may be used in generating negative
contrast voltages or in programming lamp current.
Block Diagram Operation

The LT1182/LT1183/LT1184/LT1184F are fixed frequency,
current mode switching regulators. Fixed frequency, current mode switchers control switch duty cycle directly by
switch current rather than by output voltage. Referring to
the block diagram for the LT1182/LT1183, the switch for
each regulatorturns ON atthe start of each oscillator cycle.
The switches turn OFF when switch current reaches a
predetermined level. The operation of the CCFL regulator
in the LT1184/LT1184F is identical to that in the LT11821
LT1183. The control of output lamp current is obtained by
using the output of a unique programming block to set
current trip level. The contrast voltage is controlled by the
output of a dual-input-stage error amplifier, which sets
current trip level. The current mode switching technique
has several advantages. First, it provides excellent rejection of input voltage variations. Second, it reduces the 90°
phase shift at mid-frequencies in the energy storage
inductor. This simplifies closed-loop frequency compensation under widely varying input voltage or output load
conditions. Finally, it allows simple pulse-by-pulse current limiting to provide maximum switch protection under
output overload or short-circuit conditions.
The LT1182/L T1183/LT1184/L T1184F incorporate a low
dropout internal regulator that provides a 2.4V supply for
most of the internal circuitry. This low dropout design
allows input voltage to vary from 3V to 30V with little

LTl 182/LTl 183/LTl 184/LTl 184F
APPLICATions InFoRmATion
change in quiescent current. An active low shutdown pin
typically reduces total supply current to 35~ by shutting
off the 2.4V regulator and locking out switching action for
standby operation. The ICs incorporate undervoltage lockout by sensing regulator dropout and locking out switching below about 2.5V. The regulators also provide thermal
shutdown protection that locks out switching in the presence of excessive junction temperatures.
A200kHz oscillator is the basic clock for all internal timing.
The oscillator turns on an output via its own logic and
driver circuitry. Adaptive anti-sat circuitry detects the
onset of saturation in a power switch and adjusts base
drive current instantaneously to limit switch saturation.
This minimizes driver dissipation and provides rapid turnoff of the switch. The CCFL power switch is guaranteed to
provide a minimum of 1.25A in the LT1182/LT11831
LT1184/LT1184F and the LCD power switch is guaranteed
to provide a minimum of 0.625A in the LT1182/LT1183.
The anti-sat circuitry provides a ratio of switch current to
driver current of about 50:1.
Simplified lamp Current Programming

A programming block in the LT1182/LT1183/LT11841
LT1184F controls lamp current, permitting either groundedlamp or floating-lamp configurations. Grounded configurations control lamp current by directly controlling onehalf of actual lamp current and converting it to afeedback
signal to close a control loop. Floating configurations
control lamp current by directly controlling the Royer's
primary side converter current and generating afeedback
signal to close a control loop.
Previous backlighting solutions have used a traditional
error amplifier in the control loop to regulate lamp current.
This approach converted an RMS current into aDC voltage
for the input of the error amplifier. This approach used
several time constants in order to provide stable loop
frequency compensation. This compensation scheme
meant that the loop had to be fairly slow and that output
overshoot with startup or overload conditions had to be
carefully evaluated in terms of transformer stress and
breakdown voltage requirements.
The LT1182/LT1183/L T1184/LT1184F eliminate the error
amplifier concept entirely and replace it with a lamp

current programming block. This block provides an easyto-use interface to program lamp current. The programmer circuit also reduces the number of time constants in
the control loop by combining the error signal conversion
scheme and frequency compensation into asingle capacitor. The control loop thus exhibits the response of asingle
pole system, allows for faster loop transient response and
virtually eliminates overshoot under startup or overload
conditions.
Lamp current is programmed at the input of the programmer block, the ICCFL pin. This pin is the input of a shunt
regulator and accepts a DC input current signal of O~ to
1OO~. This input signal is converted to a O~ to 500uA
source currentatthe CCFL Vc pin. The programmer circuit
is simply acurrent-to-current converter with again of five.
By regulating the ICCFL pin, the input programming current
can be set with DAC, PWM or potentiometer control. The
typical input current programming range for OmA to 6mA . .
lamp current is O~ to 50~.
..
The ICCFL pin is sensitive to capacitive loading and will
oscillate with capacitance greater than 1OpF. For example,
loading the ICCFL pin with a 1x or 1Ox scope probe causes
oscillation and erratic CCFL regulator operation because
of the probe's respective input capacitance. A current
meter in series with the ICCFL pin will also produce oscillation due to its shunt capacitance. Use a decoupling
resistor of several kilo-ohms between the ICCFL pin and the
control circuitry if excessive stray capacitance exists. This
is basically free with potentiometer or PWM control as
these control schemes use resistors. A current output
DAC should use an isolating resistor as the DAC can have
significant output capacitance that changes as a function
of input code.
Grounded-lamp Configuration

In agrounded-lamp configuration, the low voltage side of
the lamp connects directly to the LT1182/L T1183/LT11841
LT1184F 010 pin. This pin is the common connection
between the cathode and anode of two internal diodes. In
previous grounded-lamp solutions, these diodes were
discrete units and are now integrated onto the IC, saving
cost and board space. Bi-directionallamp current flows in
the 010 pin and thus, the diodes conduct alternately on half

4-187

LTl182/LTl183/LTl 184/LTl 184F
APPLICATions InFoRmATion
cycles. Lamp current is controlled by monitoring one-half
of the average lamp current. The diode conducting on
negative half cycles has one-tenth of its current diverted to
the CCFL pin and nulls againstthe source current provided
by the lamp current programmer circuit. The compensation capacitor on the CCFL Vc pin provides stable loop
compensation and an averaging function to the rectified
sinusoidal lamp current. Therefore, input programming
current relates to one-half of average lamp current.
The transfer function between lamp current and input
programming current must be empirically determined and
is dependent on the particular lamp/display housing combination used. The lamp and display housing are adistributed loss structure due to parasitic lamp-to-frame capacitance. This means that the current flowing at the high
voltage side of the lamp is higher than what is flowing at
the 010 pin side of the lamp. The input programming
current is set to control lamp current at the high voltage
side of the lamp, even though the feedback signal is the
lamp current at the bottom of the lamp. This insures that
the lamp is not overdriven which can degrade the lamp's
operating lifetime.

Floating-Lamp Configuration
In a floating-lamp configuration, the lamp is fully floating
with no galvanic connection to ground. This allows the
transformer to provide symmetric, differential drive to the
lamp. Balanced drive eliminates the field imbalance associated with parasitic lamp-to-frame capacitance and reduces "thermo metering" (uneven lamp intensity along the
lamp length) at low lamp currents.
Carefully evaluate display designs in relation to the physical layout of the lamp, it leads and the construction of the
display housing. Parasitic capacitance from any high
voltage point to DC or AC ground creates paths for
unwanted current flow. This parasitic current flow degrades electrical efficiency and losses up to 25% have
been observed in practice. As an example, at a Royer
operating frequency of 60kHz, 1pF of stray capacitance
represents an impedance of 2.65MQ. With an operating
lamp voltage of 400V and an operating lamp current of
6mA, the parasitic cu rrent is 150f,lA. The efficiency loss is
2.5%. Layout techniques that increase parasitic capaci-

4-188

tance include long high voltage lamp leads, reflective
metal foil around the lamp, and displays supplied in metal
enclosures. Losses for a good display are under 5%
whereas losses for a bad display range from 5% to 25%.
Lossy displays are the primary reason to use a floatinglamp configuration. Providing symmetric, differential drive
to the lamp reduces the total parasitic loss by one-half.
Maintaining closed-loop control of lamp current in a
floating lamp configuration now necessitates deriving a
feedback signal from the primary side of the Royer transformer. Previous solutions have used an external precision shunt and high side sense amplifier configuration.
This approach has been integrated onto the LT1182/
LT1183/LT1184F for simplicity of design and ease of use.
An internal 0.1 W resistor monitors the Royer converter
current and connects between the input terminals of a
high-side sense amplifier. A OA to 1A Royer primary side,
center tap current is translated to a 0f,lA to 500uA sink
current at the CCFL Vc pin to null against the source
current provided by the lamp current programmer circuit.
The compensation capacitor on the CCFL Vc pin provides
stable loop compensation and an averaging function tothe
error sink current. Therefore, input programming current
is related to average Royer converter current. Floatinglamp circuits operate similarly to grounded-lamp circuits,
except for the derivation of the feedback signal.
The transfer function between primary side converter
current and input programming current must be empirically determined and is dependent upon a myriad of
factors including lamp characteristics, display construction, transformer turns ratio, and the tuning of the Royer
oscillator. Once again, lamp current will be slightly higher
at one end of the lamp and input programming current
should be set for this higher level to insure that the lamp
is not overdriven.
The internal 0.1 Q high-side sense resistor on the LT1182/
LT1183/LT1184F is rated fora maximum DC currentof 1A.
However, this resistor can be damaged by extremely high
surge currents at start-up. The Royer converter typically
uses afew microfarads of bypass capacitance atthe center
tap ofthe transformer. This capacitor charges up when the
system is first powered by the battery pack or an AC wall
adapter. The amount of current delivered at start-up can be

LTl 182/LTl 183/LTl 184/LTl 184F
APPLICATions InFoRmATion
very large if the total impedance in this path is small and
the voltage source has high current capability. Linear
Technology recommends the use of an aluminum electrolytiC for the transformer center tap bypass capacitor with
an ESR greater than or equal to 0.5Q. This lowers the peak
surge currents to an acceptable level. In general, the wire
and trace inductance in this path also help reduce the di/
dt of the surge current. This issue only exists with floating
lamp circuits as grounded-lamp circuits do not make use
of the high-side sense resistor.
Optimizing Optical Efficiency vs Electrical Efficiency

Evaluating the performance of an LCD backlight requires
the measurement of both electrical and photometriC efficiencies. The best optical efficiency operating point does
not necessarily correspond to the best electrical efficiency. However, these two operating points are generally
close. The desired goal is to maximize the amount of light
out for the least amount of input power. It is possible to
construct backlight circuits that operate with over 90%
electrical efficiency, but produce significantly less light
output than circuits that operate at 80% electrical efficiency.
The best electrical efficiency typically occur's just as the
CCFL's transformer drive waveforms begin to exhibit
artifacts of higher order harmonics reflected back from the
Royer transformer secondary. Maximizing electrical efficiency equates to smaller values for the Royer primary
side, resonating capacitor and larger values for the Royer
secondary side ballast capaCitor. The best optical efficiency occurs with nearly ideal sinusoidal drive to the
lamp. Maximizing optical efficiency equates to larger
values forthe Royer primary side resonating capacitor and
smaller values forthe Royer secondary side ballastcapacitor. The preferred operating point for the CCFL converter
is somewhere in between the best electrical efficiency and
the best optical efficiency. This operating point maximizes
photometric output per watt of input power.
Making accurate and repeatable measurements of electrical and optical efficiency is difficult under the best circumstances. Requirements include high voltage measurements and equipment specified forthis operation, special-

ized calibrated voltage and current probes, wideband RMS
voltmeters, a photometer, and a calorimeter (for the
backlight enthUSiast). Linear Technology's Application
Note 55 and Design Note 101 contain detailed information
regarding equipment needs.
Input Supply Voltage Operating Range

The backlighVLCD contrast control circuits must operate
over a wide range of input supply voltage and provide
excellent line regulation for the lamp current and the
contrast output voltage. This range includes the normal
range of the battery pack itself as well as the AC wall
adapter voltage, which is normally much higher than the
maximum battery voltage. Atypical input supply is 7V to
28V; a 4 to 1 supply range.
Operation of the CCFL control circuitry from the AC wall
adapter generates the worst-case stress for the CCFL
transformer. Evaluations of loop compensation for over- . , .
shoot on startup transients and overload conditions are . .
essential to avoid destructive arcing, overheating, and
transformer failure. Open-lamp conditions force the Royer
converter to operate open-loop. Component stress is
again worst-case with maximum input voltage conditions.
The LT1182/LT1183/LT1184/LT1184F open-lamp protection clamps the maximum transformer secondary voltage to safe levels and transfers the regulator loop from
current mode operation into voltage mode operation.
Other fault conditions include board shorts and component failures. These fault conditions can increase primary
side currents to very high levels, especially at maximum
input voltage conditions. Solutions to these fault conditions include electrical and thermal fuses in the supply
voltage trace.
Improvements in battery technology are increasing battery lifetimes and decreasing battery voltages required by
the portable systems. However, operation at reduced
battery voltages requires higher, turns-ratio transformers
forthe CCFL to generate equivalent output drive capability.
The penalty incurred with high ratio transformers is higher,
circulating currents acting on the same primary side
components. Loss terms increase and electrical efficiency
often decreases.

4-189

LTl182/LTl183/LTl 184/LTl 184F
APPLICATions InFoRmATion
Size Constraints

Applications Support

Tighter length, width, and height constraints for CCFL and
LCD contrast control circuitry are the result of LCD display
enclosure sizes remaining fairly constant while display
screen sizes have increased. Space requirements for
connector hardware include the input power supply and
control signal connector, the lamp connector, and the
contrast output voltage connector.

Linear Technology invests an enormous amount of time,
resources, and technical expertise in understanding, deSigning and evaluating backlight/LCD contrast solutions
for system designers. The design of an efficient and
compact LCD backlight system is a study of compromise
in a transduced electronic system. Every aspect of the
design is interrelated and any design change requires
complete re-evaluation for all other critical design parameters. Linear Technology has engineered one of the most
complete test and evaluation setups for backlight designs
and understands the issues and tradeoffs in achieving a
compact, effficient and economical customer solution.
LinearTechnology welcomes the opportunity to discuss,
design, evaluate, and optimize any backlight/LCD contrast
system with a customer. For further information on backlight/LCD contrast designs, consult the references listed
below.

Even though size requirements are shrinking, the high
voltage AC required to drive the lamp has not decreased.
In some cases, the use of longer bulbs for color, portable
equipment has increased the high voltage requirement.
Accommodating the high voltage on the circuit board
dictates certain layout spacings and routings, involves
providing creepages and clearances in the transformer
design, and most importantly, involves routing a hole
underneath the CCFL transformer. Routing this hole minimizes high voltage leakage paths and prevents moisture
buildup that can result in destructive arcing. In addition to
high voltage layout techniques, use appropriate layout
techniques for isolating high current paths from lowcurrent signal paths.
This leaves the remaining space for control circuitry at a
premium. Minimum component count is required and
minimum size for the components used is required. This
squeeze on component size is often in direct conflict with
the goals of maximizing battery life and efficiency. Compromise is often the only remaining choice.

LCD Contrast Circuits
The LCD contrast switching regulator on the LT1182/
LT1183 operates in many standard switching configurations and is used as a classic DC/DC converter. The dualinput-stage error amplifier easily regulates either positive
or negative contrast voltages. Topology choices for the
converter include single inductor and transformer-based
solutions. The switching regulator operates equally well
either in continuous mode or discontinuous mode. Efficiencies for LCD contrast circuits range from 75% to 85%
and depend on the total power drain of the particular
display. Adjustment control of the LCD contrast voltage is
provided by either potentiometer, PWM, or DAC control.

4-190

References
1. Williams, Jim. August 1992. Illumination Circuitry for
Uquid Crystal Displays. Linear Technology Corporation,
Application Note 49.
2. Williams, Jim. August 1993. Techniques for 92% Efficient LCD Illumination. Linear Technology Corporation,
Application Note 55.
3. Bonte, Anthony. March 1995. LT1182 Floating CCFL
with Dual Polarity Contrast. Linear Technology Corporation, Design Note 99.
4. Williams, Jim. April 1995. A Precision Wideband Current Probe for LCD Backlight Meaasurement. Linear Technology Corporation, Design Note 101.

LTl 182/LTl 183/LTl 184/LTl 184F
TYPICAL APPLICATions
90% Efficient Grounded CCFL Configuration with Negative Polarity LCD Contrast
UP TO 6mA
C1 MUST BE A LOW LOSS CAPACITOR,
C1 = WIMA MKP-20
01, 02 = ZETEX ZTX849 OR ROHM 2SC5001

L1 = COILTRONICS CTX210605
L2 = COILTRONICS CTX100-4
L3 = COILTRONICS CTX02-12403
'~O NOT SUBSTITUTE COMPONENTS
COILTRONICS (407) 241-7876

THE ICCFL CURRENT REQUIRED FOR AN
RMS BULB CURRENT IS:
ICCFL (9 x 10-3) (IBULB).
0% TO 90% DUTY CYCLE FOR THE PWM
SIGNAL CORRESPONDS TO 0 TO 6mA.

V (PWM)
OV TO 5V
1kHz PWM

-'lM......-+--'l/I/v---Ir.:.

1%

SHUTDOWN

----+-::-::-=-==-:--...:;.

R1
7500
C12

VARYING THE V(CONTRAST)
VOLTAGE FROM OVTO 5V GIVES
VARIABLE NEGATIVE CONTRAST
FROM -1 OV TO -30V

T2.2~F

':" 35V

'----1'--"- NEG CON
04
1N914

.,.
..

R11
40.2k
1%

4-191

LTl182/LTl183/LTl184/LTl184F
TYPICAL APPLICATions
LT1184F Floating CCFL with Po.tentiometer Control of Lamp Current
UP T06mA
ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3B WITH AN
ESR" 0.50 TO PREVENT DAMAGE TO THE LT1184F HIGH-SIDE
SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON.
C1 MUST BE A LOW LOSS CAPACITOR, C1 = WIMA MKP-20
01, 02 = ZETEX ZTX849 OR ROHM 2SC5001
L1 = COILTRONICS CTX21 0605
r - - -....---F--~~__~~--=-+.,
L2 = COILTRONICS CTX1 00-4
"DO NOT SUBSTITUTE COMPONENTS
C5
1000pF
COILTRONICS (407) 241-7876

..- .....- + - - - R1
7500

OIlA TO 4511A leCFL CURRENT GIVES
OmA TO 6mA LAMP CURRENT FOR A
TYPICAL DISPLAY.

. ; . ; ; . . , - - - - - - - - - - -....- -

4-192

~I~V

:C~O 28V

LTl182/LTl183/LTl 184/LTl 184F
rYPICAL APPLICATions
LT1182/LT1183ICCFL PWM Programming

LT11831CCFL PWM Programming with VREF

V (PWM)
Rl
R2
OV TO 5V
40.5k
40.5k
1kHz PWM ~ TO ICCfL PIN
0%t090%DC=
+
O~ to 50llA
Cl
Rl AND R2 ARE IDEAL VALUES.
2.21lF
USE NEAREST 1% VALUE.

T

--

~

FROM VREf
V (PWM)
OV TO 5V

Rl
330Q

lkHZPWM~

0% to 90% DC =
OIlA to 50llA

01
VN2222L
R2
7.15k

R3
7.15k

......---'w,...-- TO ICCfL PIN

+ Cl
T~ 221l F

LT1184/LT1184F ICCFL PWM Programming
V (PWM)
Rl
R2
OV TO 5V 40.35k
40.35k
lkHzPWM ~TOICCfLPIN
0% to 90% DC =
OflA to 50flA
+ Cl
Rl AND R2 ARE IDEAL VALUES.
2.2flF
USE NEAREST 1% VALUE.

T
":'"

J

Rl PREVENTS OSCILLATION.
R2 AND R3 ARE IDEAL VALUES.
USE NEAREST 1% VALUE.

LT1184/lT1184F ICCFl PWM Programming with VREF

,,82TA05

FROMVREf
V (PWM)
OV TO 5V
1kHz PWM
0% to 90% DC =
OIlA to 50llA

LT1183ICCFL Programming
with Potentiometer Control
Rl
15.9k

VREf

Rl
330Q

~

01
VN2222L
R2

R2
50k

~

J

R3
6.98k

6.98k

t---'VV\-- TO ICCfl PIN

+

TO ICCfL PIN

Cl

1;22"F

Rl AND R2 ARE IDEAL VALUES.
USE NEAREST 1% VALUE.
ICCfL = 12~ TO 50~.

Rl PREVENTS OSCILLATION.
R2 AND R3 ARE IDEAL VALUES.
USE NEAREST 1% VALUE.

r

1182TA09

LT1184/LT1184F ICCFl Programming
with Potentiometer Control
Rl
15.5k

VREf

LT1183ICCFl PWM Programming with VREF

R2
50k

~

FROM VREf
TO ICCfL PIN

Rl AND R2 ARE IDEAL VALUES.
USE NEAREST 1% VALUE.
ICCfL = 12~ TO 50flA.

LT1182/LT1183/L T1184/lT1184F
ICCFl Programming with DAC Control

R3
7.15k

""""

......---'W..-......WI..- TO ICCfL PIN

V (PWM)

l~~zT~~~lQlVN2222L
10 to 100% DC = ---,

T

Cl
221lF

50llA TOO~

~

Rl, R2 AND R3 ARE IDEAL VALUES.
USE NEAREST 1% VALUE.
l1B2TAlO

LT1184/LT1184F ICCFl PWM Programming with VREF
FROM VREf
Rl
3.48k
V (PWM)

R3
6.98k

......---'W..-......WI..-

1~~zT~~~~101VN2222L

10 to 100% DC = - ,
50llA TOO~

3~~k

+

T
~

TO ICCfL PIN

Cl
221lF
Rl, R2 AND R3 ARE IDEAL VALUES.
USE NEAREST 1% VALUE.
1182TAl1

L7lJ!J~

4-193

•

LTl182/LTl183/LTl184/LTl184F
TYPICAL APPLICATions
L11182 LCD Contrast Positive Boost Converter

r----..--------:c~O 2BV
L3
SOJ.lH
COILTRONICS CTXSO-4

POSCON
....-ID~SI----C1-1--VOUT<:VIN

1N914

...,.... 22J.1F
.J.. 3SV
R12
20k
R13
B.4Sk
1%

R14
1.21k
1%
1182TA12

L11182 LCD Contrast Positive Boost/Charge Pump Converter

...----..----------:C~02BV

POSCON
t--......--I·I--"""""-..-VOUT<: VIN

R12
20k
R13
B.4Sk
1%

~-~----~---1------~ R14

1.21k
1%
1182TA13

4-194

LTl182/LTl183/LTl184/LTl184F
TYPICAL APPLICATions
LT1182 LCD Contrast Positive to Negative/Charge Pump Converter

'---C1-3-

T

2.2f1F
35V

.....
L3----------

~C~o 28V

CTX50-4
COILTRONICS CTX50-4
05
1N914

1--......-1<4....-...--......-

R9
4.99k
1%

R10
10k
1%

NEGCON
1VOUTI;, VIN

R11
20k
1%

5V ---'W.~~-'\Nv--''JM,......----------'

118ZTA14

RELATED PARTS
FREQUENCY

SWITCH CURRENT

LT1107

PART NUMBER

63kHz
Hysteretic

1A

DESCRIPTION

LT1172

100kHz

1.25A

LT1173

24kHZ
Hysteretic

1A

LT1186

200kHz

1.25A

CCFL Switching Regulator with DAC for "Bits to
Brightness Control"

LT1372

500kHz

1.5A

Current Mode Switching Regulator for CCFL or LCD
Contrast Control

Micropower DC/DC Converter for LCD Contrast Control
Current Mode Switching Regulator for CCFL or LCD
Contrast Control
Micropower DC/DC Converter for LCD Contrast Control

4-195

f~TLElcnH'Nt1\O'IO-G~Q~----------U_1l_86
....,L,
~
DAC Programmable
IT

CCFL Switching Regulator
(Bits-to-Nits™)
face modes including standard SPI mode and pulse mode.
On power-up, the DAC counter resets to half-scale and the
Wide Battery Input Range: 4.SV to 30V
DAC configures to SPI or pulse mode depending on the CS
Grounded Lamp or Floating Lamp Configurations
signal level. In SPI mode, the system microprocessor
Open Lamp Protection
serially transfers the present 8-bit data and reads back the
Precision 50~ Full-Scale OAC Programming Current previous 8-bit data. In pulse mode, the upper six bits of the
Standard SPI Mode or Pulse Mode
DAC configure as increment-only (single-wire interface)
OAC Setting Is Retained in Shutdown
or increment/decrement (two-wire interface) operation
depending on the DIN signal level.

FEATURES
•
•
•
•
•
•

APPLICATions

• Notebook and Palmtop Computers
• Portable Instruments
• Retail Terminals

DESCRIPTiOn
The LT®1186 is a fixed frequency, current mode, switching regulator that provides the control function for Cold
Cathode Fluorescent Lighting (CCFL). The IC includes an
efficient high current switch, an oscillator, output drive
logic, control circuitry and a micropower 8-bit SO~ fullscale current output DAC. The DAC provides simple "bitsto-lamp current control" and communicates in two inter-

The LT1186 control circuitry operates from alogic supply
voltage of 3.3V or SV. The IC also has a battery supply
voltage pin that operates from 4.SV to 30V. The LT1186
draws 6mA typical quiescent current. An active low shutdown pin reduces total supply current to 3S~ for standby
operation and the DAC retains its last setting. A 200kHz
switching frequency minimizes magnetic component size.
Current mode switching techniques with cycle-by-cycle
limiting gives high reliability and simple loop frequency
compensation. The LT1186 is available in a16-pin narrow
SO package.
.£T, LTC and LT are registered trademarks of Linear Technology Corporation,
Bits-to-Nits is a trademark of Linear Technology Corporation, 1 Nit = 1 Candelalmeter2

TYPICAL APPLICATiOn
90% Efficient Floating CCFL with Single-Wire (Increment Only) Pulse Mode Control 01 Lamp Current
01
BAT85

CCFL BACKLIGHT APPLICATION CIRCUITS
CONTAINED IN THIS DATA SHEET ARE COVERED
BY U,S, PAllONT NUMBER 5408162
AND OTHER PATENTS PENDING

UP TO BmA

~~~;:;;=;ffi~ Ll

P---.,....---HH

1-..--f--,+'--==:1-t..::.-...::.t,

L1 = COILTRONICS CTJ(210B05
L2 =CQlLTRONICS CTX10o-4
'00 NOT SUBSTITUTE COMPONENTS
COILTRONICS (407) 241-787B

r--.......-- :C~028V
Rl
7500

ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3A AND C3B,
MAKE 3CB ESR >0,50 TO PREVENT DAMAGE TO THE LTII86 HIGH-SIDE
SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON
Cl MUST BE A LOW LOSS CAPACITOR. Cl =WIMA MKP-20
IljJA TO 50JIA ICGFL CURRENT GIVES
OmA TO BmA LAMP CURRENT
01, 02 = ZETEX ZTX849 OR AOHM 2SC5001
FOR ATYPICAL DISPLAY,

4-196

FOR ADDITIONAL CCFULCD CONTRAST APPLICATION CIRCUITS,
REFER TO THE LTI182183184/84F DATA SHEET

LTl186
ABSOLUTE mAXimum RATinGS
Vcc ........................................................................... 7V
BAT, Royer, Bulb .................................................... 30V
CCFL Vsw ............................................................... 60V
Shutdown ....... ................ ......... ..... ............................ 6V
ICCFL Input Current .............................................. 10mA
010 Input Current (Peak, <100ms) .................... 100mA
Digital Inputs ................................ -O.3V to Vcc + O.3V
Digital Outputs .............................. -O.3V to Vcc + O.3V
DAC Output Voltage ....................... -20V to Vcc + O.3V
Junction Temperature (Note 1) ........................... 100°C
Operating Ambient Temperature Range ... O°C to 100°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER
LT1186CS

S PACKAGE
16-lEAD PLASTIC SO
TJMAX =100°C, 9JA =100°C/W

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARAOERISTICS
TA = 25°C, Vcc = SHUTDOWN =DIN = CS =3.3V, BAT = Royer =Bulb = 12V, ICCFL = CCFl Vsw =Open, DOUT =Three-State, DlO =lOUT = . .
ClK =GND, CCFl Vc = O.5V, unless otherwise specified.
..
SYMBOL

PARAMETER

CONDITIONS

10
ISHDN

Supply Current

3V:s; Vee:S; 6.5V, 1/2 Full-Scale DAC Output Current

SHUTDOWN Supply Current

SHUTDOWN =OV, CCFL Vc Open (Note 2)

SHUTDOWN Input Bias Current

SHUTDOWN =OV, CCFL Vc =Open

SHUTDOWN Threshold Voltage

I

Switching Frequency

DC(MAX)

Maximum Switch Duty Cycle

3V

Measured at CCFL Vsw, Isw =50mA,
ICCFl =1001lA, CCFL Vc =Open
Measured at CCFL Vsw

Switch Breakdown Voltage

Measured at CCFL Vsw

Switch Leakage Current

Vsw =12V, Measured at CCFL Vsw
Vsw =30V, Measured at CCFL Vsw

ICCFl Summing Voltage

3V:s; Vcc:S; 6.5V

dlecFl Summing Voltage for
dlnput Programming Current

ICCFl =01lA to 1001lA

CCFL Vc Offset Sink Current

CCFL Vc =1.5V, Positive Current Measured into Pin

dCCFL Vc Source Current for
dlcCFL Programming Current

ICCFL =251lA, 501lA, 751lA, 1001lA,
CCFL Vc =1.5V

CCFL Vc to 010 Current Servo Ratio

010 =5mA out of Pin, Measure I(Vc) at CCFL Vc =1.5V

CCFL Vc Low Clamp Voltage

VSAT - VSuib =Bulb Protect Servo Voltage

CCFL Vc High Clamp Voltage

ICCFl =1001lA

CCFL Vc Switching Threshold

CCFL Vsw DC =0%

CCFL High-Side Sense Servo Current

ICCFl =1001lA, I(Vc) =01lA at CCFL Vc =1.5V

CCFL High-Side Sense Servo Current
Line Regulation

BAT =5V to 30V, ICCFl =1001lA,
I(Vc) =01lA at CCFL Vc =1.5V

MIN

•

TYP

MAX

6

9.5

mA

35

70

5

10

IlA
IlA

UNITS

•

0.45

0.85

1.2

V

•

175
160

200
200

225
240

kHz
kHz

80
75

85
85

60

70

•

•

0.425
0.385

%
%
V
20
40

IlA
IlA

0.465
0.465

0.505
0.555

V
V

5

15

mV

IlA

-5

5

15

•

4.70

4.95

5.20

IlA/llA

•

94

99

104

0.1

0.3

!lAImA
V

•
•

•
•

1.7

2.1

2.4

V

0.6

0.95

1.3

V

0.93

1.00

1.07

A

0.1

0.16

%N

4-197

LTl186

ELEaRICAL CHARAaERISTICS
TA =25°C, Vcc =SHUTDOWN =DIN =CS =3.3V, BAT =Royer =Bulb =12V, ICCFL =CCFl Vsw =Open, DOUT =Three-State, DID =lOUT =
ClK = GND, CCFl Vc = O.5V, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

CCFl High-Side Sense Supply Current Current Measured into BAT and Royer Pins
Bulb Protect Servo Voltage

IceFl = 100llA, I(Vc) = 01lA at CCFl Vc = 1.5V,
Servo Voltage Measured between BAT and Bulb Pins

Bulb Input Bias Current
ILiM

CCFl Switch Current Limit

ICCFl = 100llA, I(Vc) = 01lA at CCFL Vc = 1.5V
Duty. Cycle = 50%
Duty Cycle = 75% (Note 3)

VSAT
.dla
.dlsw

CCFl Switch On Resistance
Supply Current Increase During
CCFl Switch On Time

CCFl Isw = 1A

CCFL Isw = 1A

DAC Resolution
DAC Full-Scale Current

V(IOUT) = 0.465V, Measured in SPI Mode

DAC Zero Scale Current

V(IOUT) = 0.465V, Measured in SPI Mode

DAC Differential Nonlinearity
DAC Supply Voltage Rejection
logic Input Current

3V:5: Vce:5: 6.5V, lOUT = Full Scale, V(lOUT) = 0.465V
0:5: VIN:5: Vce
Vcc= 3.3V
Vce= 5V

High level Input Voltage

Vil

low level Input Voltage

Vee = 3.3V
Vee = 5V

VOH

High level Output Voltage

VOL

low level Output Voltage

Vee = 3.3V, 10 = 40011A
Vee = 5V, 10 = 40011A
Vec = 3.3V, 10 = 1rnA
Vce = 5V, 10 = 2mA

felK

Clock Frequency

teKs

Setup Time, ClK! Before CS!

tess
tov

Setup Time, CS! Before ClKi

tos

CS! to DOUT Valid
Data in Setup Time Before ClKi

tOH

Data in Hold Time After ClKi

too
tCKHI

ClK! to DOUT Valid
ClK High Time

Vcs= Vee

See Test Circuits

See Test Circuits

teKLO

ClK low Time

tesH

ClK! Before cSi

tOl

cSi to DOUT In Hi-Z
CSi Before ClKi

See Test Circuits

CS low Time
CSHigh Time

fClK= 2M Hz

tCKH
tesLO
tesHI

4-198

TYP

MAX

UNIT

50

100

150

•

IIA

6.5

7.0

7.5

V

5

9

•
•
•

IIA

1.25
0.9

1.9
1.6

3.0
2.6

A
A

0.6

1.0

n

20

30

mAlA

•

8

VIH

Three-State Output leakage
loz
SERIAL INTERFACE (Noles 4, 5)

MIN

•
•
•
•
••
••
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•

•

48.75
47.50

50
50

2

Bits
51.25
52.50

IIA
IIA

200

nA

±2.0

LSB

4

lSB

±1

IIA

1.9
2

V
V
0.45
0.80

2.1
2.4

V
V
V
V

0.4
0.4

V
V

±5

IIA

2

MHz

150

ns

400

ns

150

ns

150

ns

150

ns

150

ns

200

ns
ns

250
150

ns
400
400

ns
ns

4550

ns

400

ns

LTl186
:lEORICAl CHARACTERISTICS
Ie • denotes specifications which apply over the specified operating
mperature range.
~te1: TJ is calculated from the ambient temperature TA and power
ssipation Po according to the following formula:
LT1186CS: TJ = TA + (Po x 100°C/W)
~te 2: Does not include switch leakage.

Note 3: For duty cycles (DC) between 50% and 80%, minimum
guaranteed switch current is given by ILiM = 1.4(1.393 - DC) for the
LT1186 due to internal slope compensation circuitry.
Note 4: Timings for all input signals are measured at 0.8V for a High-toLow transition and 2.0V for a Low-to-High transition.
Note 5: Timings are guaranteed but not tested.

'YPICAl PERFORmAnCE CHARACTERISTICS
Supply Current
vs Temperature

Shutdown Current
vs Temperature

10

Shutdown Input Bias Current
vs Temperature

100
90

:;c 80
.=;
f-

2i'i

a:
a:
=>
u

r--

z

70

60
50

;;: 40

'"=>
C
f-

:c



30

-

Vee = 5V
Vee =5V

--

~

Vee = 3V

Vee =3V

20
10

o

o

o

-75-50 -25 0 25 50 75 100125150175
TEMPERATURE (0G)

-75 -50 -25 0 25 50 75 100125 150 175
TEMPERATURE (0C)

-75 -50 -25 0 25 50 75 100125 150175
TEMPERATURE (OC)
lT1181i.G02

Shutdown Threshold Voltage
vs Temperature

Maximum Duty Cycle
vs Temperature

Frequency vs Temperature

1.2

240

95
93

230

1.1
'N

220

ii'z" 210

1.0
.~

0.9

LT1186'G03

........

~ 200

........

0.8

0.7

iIl

........

.......

fE 190

;i

.........

~

u
u

180
170

0.6
-75 -50-25 0 25 50 75 100125150175
TEMPERATURE (OC)
LT1186'G04

(7lJ!J~

--

160
-75 -50-25

......... 1'-..

-

~ 91
':J
u 89
>u
~ 87
=>
c
85

,;

::;;

=>
::;;

83

~ 81

.....

.....

. /V

V

::;;

;i
u
u

79
77

0 25 50 75 100125 150175
TEMPERATURE (OC)

75
-75 -50 -25 0 25 50 75 100 125150 175
TEMPERATURE (0C)

LT1186·G05

4-199

LTl186
TYPICAL PERFORmAnCE CHARAOERISTICS
ICCFL Summing Voltage
vs Temperature

ICCFL Summing Voltage
Load Regulation

0.53
0.52
0.51
0.50
0.49
0.48
./
0.47
./
0.46
0.45
0.44
0.43
V
0.42
0.41
0.40
0.39
0.38
-75-50-250255075100125150175
TEMPERATURE (OC)

~
w

"

~

§;
C!l

~

:;
~

'"

~

Vc Sink OHset Current
vs Temperature

5
4
3

[

2

w

1

~

.......

a
-1 ~~

...I

~

.......

-2

......

~ -3

:; -4
~ -5
~ -6
2 -7

0.6
0
15

ICCFL = 101lA

r:::i:P

1(010)=1mA

t: 0.4

>0

1(010) = 5mA-

-::::-.......

~

~ffi 4.90

....... .......



""

'"c;;z

W ~ 50 501001W1~150150WO
ICCFL PROGRAMMING CURRENT (1lA)

LT1188'G07

gsu .~- 5.05
~~

...... ........

t;:;

if
o
...I

.........

I
CCll Vr 1.5V,

8

ffi

-;§;?

........

10
9

o

-75-50-250255075100125150175
TEMPERATURE (0G)

LT1186·Gl0

-75 -50-25

0 25 50 75 100125 150 17!
TEMPERATURE (OC)

Ll'1186'Gl1

Vc to DID Current Servo
Ratio vs Temperature

lT1186'G12

Vc Low Clamp Voltage
vs Temperature

<" 103

Vc High Clamp Voltage
vs Temperature

0.30

2.4

E

1o

102

~ 0.25

ffi

~

0::
:J

99
98

-~

.""'"

I

:_

~

0

~

1(010) = 5mA

<>

95
-75 -50-25

4-200

>

":;

0.20

S

0.15

s:
g

0.10

to

0 25 50 75 100 125 150 175
TEMPERATURE (OC)

~

to

ri
to

2.2

§;
a.. 2.1

~ 2.0

-;§;?

o 97
15
-;§;? 96

~
<>

~

C!l

1(010) = 10mA\

0::

§; 100 r-1(DlO) = 1~

2.3

w

w

~ 101

en

~

C!l

l-

f- Jo-

0.05

o

-75 -50 -25 0 25 50 75 100125 150 175
TEMPERATURE (OC)

:;:
-;§;? 1.9

~

r.... .......

..........

""

r....

1.8
1.7
-75-50-25 0 25 50 75 100125 150 17!
TEMPERATURE (OC)

LTl186
rYPICAl PERFORmAnCE CHARACTERISTICS
Vc Switching Threshold
vs Temperature
~

1.3

"'~

1.2

§;
1.1

~

w

\

~

:fl 1.0

'"

"-

'"
z 0.9
'E

>
0
>

7.1

'"

I-

<.:>

"'-

0.8

~

"~

7.3
7.2

ffi 7.0

"'-

~

6.9

0
a: 6.8
a.

"'-

0.7

"3 6.7
=>

'"

i
~ 0.6

10

7.4

!3'"
0

:t:

:.:>

6.6

ICCFL = 1OO~A

....... ,....

V

t 150

<.:>

~

05

ICCFL=50~

-+-

l-

i.--- .......

=>
a.

;0;

"3

I !
ICCFL= 10~

'"
o

-75 -50 -25 0 25 50 75 100 125150175
TEMPERATURE (OC)
LT1186-G18

High-Side Sense Null Current Line
Regulation vs Temperature
:> 0.160

a:
=>
<.:>

::l 1.020

-

=>
z

~ 1.000

'"
9 0.980
'"±

70

'"
:c

",

50
-75 -50 -25 a 25 50 75 100125150175
TEMPERATURE (OC)

8

C
15

0.140

~

0.120

'"~

vV

z

'"z~
w

:c

0.940
-75 -50 -25 0 25 50 75 100125 150 175
TEMPERATURE (OC)

8

u:

- 0.7

,,

0.6

~

0.4

T=25°C

~~

ff

0.1

Forced Beta vs Isw on Vsw

2.0

100
90

T=2~

~
::::;

!z
ll!
a:

1.5

T = 125°C

~-ooc

~INI~U"'M' .....

-'

~

8

'"6l

i"--..

fZ 40

r--..

0.5

tj
<.:>

a:

1'-

80
70
60

~~
r-

......... r-

-f{}

I"
0.3

I-

~ 1.0

~

o
o

0.000
-75 -50-25 0 25 50 75 100125 150175
TEMPERATURE (OC)

110

=>

A"

0.3
0.2

/.~

T=125OC~T=-5OC

0.5

0.020

2.5

0.9

g

",

0.060

Vsw Current Limit vs Duty Cycle

0.8

V

o

:c
'"

1.0

....... .......

if 0.040

0.960

Vsw Sat Voltage
vs Switch Current

_

0.100

~ 0.080

VI-V

-'
~

60

V

=>

15
1.040
a:

90
80

- I-v

«
'"

I-

,§ 130
g

!:§

1.060

; 140

3 100

.//

High-Side Sense Null
Current vs Temperature

;;

110

15
a:

LT1186-G17

High-Side Sense Supply Current
vs Temperature

,"t:

/

I-

/"

LT11IJ6'G16

120

1

V

6.5
-75 -50 -25 0 25 50 75 100 125150175
TEMPERATURE (OC)

-75-50-25 0 25 50 75 100125 150175
TEMPERATURE (OC)

~

Bulb Input Bias Current
vs Temperature

7.5

,

-'

'3

Bulb Protect Servo Voltage
vs Temperature

50
30
20

r\

\

'"

I"-.

............

1'. . . .

-

10
0.6
0.9
1.2
SWITCH CURRENT (A)

1.5

o

o 10 20 30 40 50 60
DUTY CYCLE (%)

70 80 90

o
o

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CCFL Isw (A)

LT118S 0 G23

4-201

•

LTl186

TYPICAL PERFORmAnCE CHARACTERISTICS
DAC lOUT vs Temperature

DAC lOUT vs Supply Voltage

52

53

1

VOUT = OV

VO~T=~

I

52

~ 51

ffi
a:

§

<.>

~
o

50

~~
~~

l..-=

Vee = 3:3V

50

§

49

~

48

o

47

<.>

49

52

TJ=25°C

-

~ 51

f5a:

V

-25

0
25
50
TEMPERATURE (OC)

75

100

45

./

TJ J5°C

~ 51

. a5

Vee = 5V

50

a:

§ 49
<.>
.....

1C

Vee = 3.3V

48

!:;
o

47
46

46
48
-50

DAC lOUT VS lOUT Bias Voltage
53

o

4
SUPPLY VOLTAGE (V)

45
-20

-15

-10
-5
0
5
OUTPUT BIAS VOLTAGE (V)

10

LT111l6·G27

Pin FunOlons
CCFl PGND (Pin 1): This pin is the emitter of an internal
NPN power switch. CCFL switch current flows through
this pin and permits internal, switch-current sensing. The
regulator provides a separate analog ground and power
ground to isolate high current ground paths from low
current signal paths. Linear Technology recommends the
use of star-ground layout techniques.
ICCFL (Pin 2): This pin isthe inputtothe CCFL lamp current

programming circuit. This pin internally regulates to
465mV. The pin accepts a DC input current signal of O~
to 50~ full scale from the DAC. This input signal is
converted to aOIlA to 2501lA sou rce cu rrent at the CCFL Vc
pin. As input programming current increases, the regulated lamp current increases. For atypical 6mA lamp, the
range of input programming current is about O~ to 501JA.

DIO (Pin 3): This pin is the common connection between
the cathode and anode of two internal diodes. The remaining terminals of the two diodes connect to ground. In a
grounded-lamp configuration, 010 connects to the low
voltage side of the lamp. Bidirectional lamp current flows
in the 010 pin and thus the diodes conduct alternately on
half cycles. Lamp current is controlled by monitoring onehalf of the average lamp current. The diode conducting on
negative half cycles has one-tenth of its current diverted to
the CCFL Vc pin. This current nulls against the source

4-202

current provided by the lamp-current programmer circuit.
Asingle capacitor on the CCFL Vc pin provides both stable
loop compensation and an averaging function to the halfwave-rectified sinusoidal lamp current. Therefore, input
programming current relates to one-half of average lamp
current. This scheme reduces the number of loop compensation components and permits faster loop transient
response in comparison to previously published circuits.
If a floating lamp configuration is used, ground the 010
pin.

CCFl Vc (Pin 4): This pin is the output of the lamp current
programmer circuit and the input of the current comparator for the CCFL regulator. Its uses include frequency
compensation, lamp-current averaging for grounded-lamp
circuits and current limiting. The voltage on the CCFL Vc
pin determines the current trip level for switch turn-off.
During normal operation this pin sits at avoltage between
O.95V (zero switch current) and 2.0V (maximum switch
current) with respect to analog ground (AGND). This pin
has ahigh impedance output and permits external voltage
clamping to adjust current limit. A single capaCitor to
ground provides stable loop compensation. This simplified loop compensation method permits the CCFL regulator to exhibit single-pole transient response behavior and
virtually eliminates transformer output overshoot.

LTl186

Pin FunCTions
AGND (Pin 5): This is the low current analog ground. It is
the negative sense terminal for the internal 1.24V reference and the ICCFL summing voltage in the LT1186.
Connect low current signal paths that terminate to ground
and frequency compensation components that terminate
to ground directly to this pin for best regulation and
performance.
SHDN (Pin 6): Pulling this pin low causes complete
regulator shutdown with quiescent current typically reduced to 3S~. Ifthe pin is not used, use apull-up resistor
to force a logic high level (maximum of 6V) or tie directly
to VCC. In a shutdown condition, the DAC retains its last
output current setting and returns to this level when the
logic-low signal at the shutdown pin is removed.
ClK (Pin 7): This pin is the shift clock for the DAC. This
clock synchronizes the serial data and is a Schmitt
trigger input. In standard SPI mode, the clock shifts data
into DIN and out of DOUT on the rising and falling edges
of the clock respectively. In pulse mode, the rising edge
of the clock either increments or decrements the counter.
This action depends on the choice of a single-wire
interface (increment only) or atwo-wire interface (increment/decrement) .
CS (Pin 8): This pin is the chip select input for the DAC. In
SPI mode, a logic low on the CS pin enables the DAC to
receive and transfer 8-bit serial data. After the serial input
data is shifted in, a rising edge of CS transfers the data into
the counter, the DAC assumes the new lOUT value and the
DOUT pin returns to the high impedance state. On power
up, alogic high places the DAC into pulse mode. Pulling CS
low after this places the DAC into SPI mode until Vcc
resets.
DIN or UP/DN (Pin 9): This pin is the digital input for the
DAC. In SPI mode, the 8-bit serial data is shifted into the
DIN input on each rising edge of the clock signal. In pulse
mode, on power up, a logic high at DIN transfers the pin
function from DIN to UP/DN, puts the counter into increment-only mode and the pin function shifts to up or down
increment control of DAC output current. If UP/DN receives a logic-low signal, the counter configures to increment/decrement mode until Vcc resets.

DOUT (Pin 10): This pin isthe digital outputforthe DAC.ln
SPI mode, DOUT is in three-state until CS falls low. The
DOUT pin then serially transfers the previous 8-bit data on
every falling edge of the clock. When CS rises high again,
DOUT returns to a three-state condition. In pulse mode,
DOUT is always three-stated.
lOUT (Pin 11): This pin is the analog current output for the
DAC and provides an output current of SO ±2.S~ over
temperature. This pin can be biased from - 20V to 2V for
a 3.3V Vcc supply voltage or from -20V to 2.SV for a SV
Vccsupplyvoltage. However, this pin istiedtothe ICCFL pin
and provides the programming current which sets operating lamp current. The lOUT pin has very little bias voltage
change when it is tied to the ICCFL pin as ICCFL is regulated.
The programming current is sourced from the lOUT pin and
sunk by the ICCFL pin.
Vee (Pin 12): This is the supply pin forthe LT1186. The IC . , .
accepts an input voltage range of 3V minimum to 6.SV . .
maximum with little change in quiescent current (zero
switch current). An internal, low-dropout regulator provides a 2.4V supply for most of the internal circuitry.
Supply current increases as switch current increases at a
rate approximately 1/S0 of switch current. This corresponds to aforced Beta of SO for the power switch. The IC
incorporates undervoltage lockout by sensing regulator
dropout and locking out switching for input voltages
below 2.SV. Hysteresis is not used to maximize the useful
range of input voltage. The typical input voltage is a 3.3V
or SV logic supply.
ROYER (Pin 13): This pin connects to the center-tapped
primary of the Royer converter and is used with the BAT
pin in afloating-lamp configuration where lamp current is
controlled by senSing Royer primary-side converter current. This pin is the inverting terminal of a high-side
current sense amplifier. The typical quiescent current is
SOI1A into the pin. If the CCFL regulator is not used in a
floating-lamp configuration, tie the Royer and BAT pins
together.

4-203

LTl186

Pin FunOlons
BAT (Pin 14): This pin connects to the battery or AC wall
adapter voltage from which theCCFL Royer converter
operates. This voltage is typically higher than the Vce
supply voltage but can equal Vee if Vee isa SV logic supply.
The BAT voltage must be at least 2.1 V greater than the
internal 2.4V regulator or 4.SV. This pin provides biasing
for the lamp-current programming block, is used with the
Royer pin for floating-lamp configurations and connects
to one input for the open-lamp protection circuitry. For
floating-lamp configurations, this pin is the non inverting
terminal of ahigh-side current sense amplifier. The typical
quiescent current is 50~ into the pin. The BAT and Royer
pins monitor the primary-side Royer converter current
through an internal 0.1 Q topside current sense resistor. A
OA t01A primary-side, center tap converter current is
translated to an input signal range of OmVto 1OOmVforthe
current sense amplifier. This input range translates to a
O~ to 500~ sink current at the CCFL Ve pin that nulls
against the source current provided by the programmer
circuit. The BAT pin also connects to the top side of the
internal clamp between the BAT and Bulb pins that is used
for open-lamp protection.
BULB (Pin 15): This pin connects to the low side of a 7V
threshold comparator between the BAT and Bulb pins.
This circuit sets the maximum voltage level across the
primary side of the Royer converter under all operating

conditions and limits the maximum secondary output
under start-up conditions or open-lamp conditions. This
eases transformer voltage rating requirements. Set the
voltage limit to ensure lamp start-up with worst-case,
lamp start voltages and cold temperature, system operating conditions. The Bulb pin connects to the junction of an
external divider network. The divider network connects
from the center tap of the Royer transformer or the actual
battery supply voltage to the top side of the current source
"tail inductor." A capacitor across the top of the divider
network filters switching ripple and sets a time constant
that determines how quickly the clamp activates. When
the comparator activates, sink current is generated to pull
the CCFL Ve pin down. This action transfers the entire
regulator loop from current mode operation into voltage
mode operation.
CCFL Vsw (Pin 16): This pin is the collector of the internal
NPN power switch for the CCFL regulator. The power
switch provides a minimum of 1.25A. Maximum switch
current is a function of duty cycle as internal slope compensation ensures stability with duty cycles greater than
50%. Using adriver loop to automatically adapt base drive
current to the minimum required to keep the switch in a
quasi-saturation state yields fast switching times and high
efficiency operation. The ratio of switch current to driver
current is about 50:1.

TEST CIRCUITS
Load Circuit for too

Voltage Waveforms for toz, tov

Voltage Waveforms for too

I.4V

CLK~I
O.8V~r-_ _ _ __

1,}J3k
~IOOPF

I-- toO]

Dour

______
..J

2.4V

r - - O.4V

Dour
WAVEFORM 1
(SEE NOTE I)

--+-'

LT1186° TC03

Dour - - - - .
WAVEFORM 2
(SEE NOTE 2)

Load Circuit for toz, tov

3k

0 - 5V

DOUT I - -__.l\llfy-O-,~

1'IOOPF

toz WAVEFORM 2, tov

ltoz WAVEFORM 1
LT1186·TC02

4-204

NOTE I: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS
DISABLED BY CS
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS
DISABLED BY CS
.

LTl186
BLOCK DIAGRAm
LT1186 OAC Programmable CCFL Switching Regulator
BAT

ROYER

14

13

R1
0.1250

~r--------'

ICCFl

AGND

DID

BULB

CCFL

1
CCFL

Vc

PGND

I--t-f-t-+llf
CONTROL

LOGIC

Dour

L7lJD~

4-205

LTl186
APPLICATions InFoRmATion
Introduction
Current generation portable computers and instruments
use backlit Liquid Crystal Displays (LCDs). Cold Cathode
Fluorescent Lamps (CCFLs) provide the highest available
efficiency in back lighting the display. Providing the most
light out for the least amount of input power is the most
important goal. These lamps require high voltage AC to
operate, mandating an efficient high voltage DC/AC converter. The lamps operate from DC, but migration effects
damage the lamp and shorten its lifetime. Lamp drive
should contain zero DC component. In addition to good
efficiency, the converter should deliver the lamp drive in
the form of a sine wave. This minimizes EMI and RF
emissions. Such emissions can interfere with other devices and can also degrade overall operating efficiency.
Sinusoidal CCFL drive maximizes current-to-light conversion in the lamp. The circuit should also permit lamp
intensity cO,ntrol from zero to full brightness with no
hysteresis or "pop-on."
The small size and battery-powered operation associated
with LCD equipped apparatus dictate low component
count and high efficiency for these circuits. Size constraints place severe limitations on circuit architecture and
long battery life is apriority. Laptop and handheld portable
computers offer an excellent example. The CCFL and its
power supply are responsible for almost 50% of the
battery drain. Additionally, all components, including PC
board and hardware, usually must fit within the LCD
enclosure with a height restriction of 5mm to 10mm.
The CCFL regulator drives an inductor that acts as a
switched-mode current source fora current-driven Royerclass converter with efficiencies as high as 90%. The
control loop forces the CCFL PWM to modulate the average inductor current to maintain constant current in the
lamp. The constant current value, and thus lamp intensity,
is programmable. This drive technique provides a wide
range of intensity control. A unique lamp-current programming block permits either grounded lamp or floating
lamp configurations. Grounded lamp circuits directly sense
one-half of average lamp current. Floating lamp circuits
directly sense the Royer's primary-side converter current.
Floating-lamp circuits provide symmetric differential drive

4-206

to the lamp and reduce the parasitic loss from stray lampto-frame capacitance, extending illumination range.

Block Diagram Operation
The LT1186 is a fixed frequency, current mode switching
regulator. Afixed frequency, current mode switcher controls switch duty cycle directly by switch current rather
than by output voltage. Referring to the block diagram for
the LT1186, the switch turns ON at the start of each
oscillator cycle. The switch turns OFF when switch current
reaches apredetermined level. The control of output lamp
current is obtained by using the output of a unique
programming block to set current trip level. The current
mode switching technique has several advantages. First,
it provides excellent rejection of input voltage variations.
Second, it reduces the 90° phase shift at mid-frequencies
in the energy storage inductor. This simplifies closed-loop
frequency compensation under widely varying input voltage or output load conditions. Finally, it allows simple
pulse-by-pulse current limiting to provide maximum switch
protection under output overload or short-circuit conditions.
The LT1186 incorporates alow dropout internal regulator
that provides a 2.4V supply for most of the internal
circuitry. This low dropout design allows input voltage to
vary from 3V to 6.5V with little change in quiescent
current. An active low shutdown pin typically reduces total
supply current to 35pA by shutting off the 2.4V regulator
and locks out switching action for standby operation. The
IC incorporates undervoltage lockout by sensing regulator
dropout and locking out switching below about 2.5V. The
regulator also provides thermal shutdown protection that
locks out switching in the presence of excessive junction
temperatures.
A200kHz oscillator is the basic clock for all internal timing.
The oscillator turns on the output switch via its own logic
and driver circuitry. Adaptive anti-sat circuitry detects the
onset of saturation in the power switch and adjusts base
drive current instantaneously to limit switch saturation.
This minimizes driver diSSipation and provides rapid turnoff of the switch. The CCFL power switch is guaranteed to
provide a minimum of 1.25A in the LT1186. The anti-sat

LTl186
IPPLICATlons InFORmATion
rcuitry provides aratio of switch currentto driver current

POWER ON

f about 50:1.

1iIi~~t ................................................... Vee

-Bit Current Output OAC

B~I~JiII ................................................... CS ALWAYS HIGH

he 8-bit current output DAC is guaranteed monotonic and
digitally adjustable by the 8-bit counter in 256 equal
:eps. On power up, the counter resets to 80H and the DAC
;sumes its mid-range value. The current output lOUT
rives the leeFL pin and sets control current for the lamp
ment programming block. The DAC has its own 1.24V
mdgap reference and avoltage to current converter that
trimmed at wafer sort to provide the precision full-scale
ment reference. Overtemperature, the current output of
Ie DAC is 50~ ±5%.

1.4181 . . . . . . . . . . . . . . . . . . . . . . . . . .

igitallnterface

SINGLE DAC

cs.~~! /

Figure 1c. Pulse Mode Setup (Increment Only)
POWER ON

IItIItlilll ................................................... Vee
_ _ ................................................... CS ALWAYS HIGH

~_

. . . . . . . . u". . . . . . . . . . . .

UP/ON

UP/ON EVER GOES LOW

n power-up, a logic high at CS configures the DAC into
jlse mode. If CS is ever pulled low, the chip configures
to SPI mode until Vee resets. On power-up in pulse
lode, a logic high at DIN puts the counter into incrementlly mode. If UP/DN (DIN) is ever pulled low, the counter
lnfigures into increment/decrement mode until Vee reltS. These modes are illustrated in Figure 1.

GOES?

DIN ALWAYS HIGH

"- ~G~TAYS
~

SPI MODE

PULSE MODE

"-~I~~TAYS
INCREMENT/
DECREMENT

~

INCREMENT·
ONLY

Figure 1a. Tree Diagram (LT1186 DAC Operating Modes)
POWER ON

....................................................... Vee
CS
CS EVER GOES LOW

Figure 1b. SPI Mode Setup

,""6'"''

lT1186·FOld

Figure 1d. Pulse Mode Setup (Increment/Decrement)

Standard SPI Mode
Refer to the serial interface operating sequence in Figure
2. A falling edge at CS initiates the data transfer. After the
falling CS is recognized, DOUT comes out of three-state.
The clock (ClK) synchronizes the data transfer. Each input
bit shifts into DIN beginning with the MSB on the rising ClK
edge and each previous data bit shifts out of DOUT beginning with the MSB on the falling ClK edge. After the 8-bit
serial input data is shifted in, a rising edge at CS transfers
the data into the counter, the DAC assumes the new value
lOUT = (8-bit serial input data) x 50~255 and the DOUT pin
returns to a high impedance state.
Single-Wire Interface (Pulse Mode)
In increment-only pulse mode, each rising edge of ClK
increments the upper six bits of the counter by one count.
When incremented beyond 111111 OOB, the counter rolls
over and sets the DAC to the minimum value OOOOOOOOB.
Therefore, a single pulse applied to ClK increases the
upper 6-bit counter by one-step, and 63 pulse applied to
ClK decreases the counter by one-step. The last two lSBs
are always zero in this mode. lOUT = (B7B6B5B4B3B2B1 Bo)
x 50~255. The upper 6-bit counter = B7B6B5B4B3B2 and
B1 =Bo =O. To configure the lT1186 into increment-only
mode, tie CS and DIN to Vee.

4-207

LTl186

APPLICATions InFoRmATion

Figure 2. SPllnlerface Timing Specification

Two-Wire Interface (Pulse Mode)
In increment!decrement pulse mode, a logic high at UP/
ON programs the counter into increment mode and each
rising edge of ClK increments the upper six bits of the
counter by one. The counteutops incrementing at
111111 OOB. A logic low at UP/ON programs the counter
into decrement mode and each rising edge of ClK decrements the upper six bits ofthe counter by one. The counter
stops decrementing at OOOOOOOOB. The last two lSBs are
always zero in this mode. lOUT = (B7BsB5B4B3B2B1Bo) x
50J,lA/255. The. upper 6-bit counter = B7BsB5B4B3B2 and
B1 = Bo = O. To configure the lT1186 into increment!
decrement mode, tie CS to Vcc and pulse the UP/ON pin
once on power-up.
Simplified Lamp Current Programming
A programming block in the lT1186 controls lamp current, permitting either grounded lamp or floating lamp
configurations. Grounded configurations control lamp
current by directly controlling one-half of actual lamp
current and converting it to a feedback signal to close a
control loop. Floating configurations control lamp current
by directly controlling the Royer's primary-side converter
current and generating afeedback signal to close acontrol
loop.
Previous backlighting solutions have used a traditional
error amplifier inthe control loop to regulate lamp current.
This approach converted an RMS current into aOC voltage
for the input of the error amplifier. This approach used
several time constants in order to provide stable loop

4-208

frequency compensation. This compensation scheme
meant that the loop had to be fairly slow and that outpu1
overshoot with start-up or overload conditions had to be
carefully evaluated in terms of transformer stress and
breakdown voltage requirements.
The lT1186 eliminates the error amplifier concept entirely
and replaces it with a lamp current programming block.
This block provides an easy-to-use interface to program
lamp current. The programmer circuit also reduces the
number oftime constants in the control loop by combining
the error signal conversion scheme and frequency compensation into a single capacitor. The control loop thus
exhibits the response of a single pole system, allows for
faster loop transient response and virtually eliminates
overshoot under start-up or overload conditions.
lamp current is programmed at the input of the programmer block, the ICCFL pin. This pin is the input of a shunt
regulator and accepts a DC input current signal of OIJA to
501JA from the OAC. This input signal is converted to aO~
to 2501JA source current atthe CCFl Vc pin. The programmer circuit is simply acurrent-to-current converter with a
gain of five. The typical input current programming range
for OmA to 6mA lamp current is OIJA to 501JA.
The ICCFL pin is sensitive to capacitive loading and will
oscillate with capacitance greater than 1OpF. For example,
loading the ICCFLpin with a1x or 1Ox scope probe causes
oscillation and erratic CCFl regulator operation because
of the probe's respective'input capacitance. A curren1
meter in series with the ICCFL pin will also produce oscillation due to its shunt capacitance. Use a decoupling

LTl186
PPLICAllons InFORmAllon
iistor of several kilohms between the ICCFL pin and the
IT pin if excessive trace stray capacitance exists. NorIlly, this resistor is not required.
some applications, the maximum programming current
luired at the ICCFL pin for a maximum lamp current will
less than the full-scale output current ofthe OAC, which
50pA. The system designer can either limit the maxi1m programming current through software built into the
)tem, or use a current splitter which shunts a percenteof the full-scale current from the ICCFL pin. A splitter
cuit is illustrated in Figure 3. A divider string is used
m a reference voltage to set up a voltage level equal to
I ICCFL summing voltage, or 465mV. The main current
wing in the divider string should be chosen to swamp
t the effects of the shunted current into the divider
ing.
TFULL-SCALE

-

R1

50~A

I

V(ICCFLl
465mV

V1

-

VREF

XI

R2

-

(1-X)1

11

~

R3
V(lcCFL)
R4

I =50~A
0<.:>

15

85

G

$

--

90

80
75

"./'
"./'

IIII

11111

~V

v

96

t;

15

VIN=~

U

~

LTC1265-3.3
VOUT= 3.3V
RSENSE = 0.10
Cr= 130pF
COIL = CTX33·4

f.-"

70
0.01

0.10
LOAD CURRENT (A)

N

92

86

i

~

4

5

I I

~ RLOAD = 250mA

90

88

l"""k

.l ~
r--- ILOADI= 800mA

84

12

80

13

........

......;: ~

I I
I I

82

7 8 9 10 11
INPUTVOLTAGE (V)

6

92

86

LTC1265-5
RSENSE = 0.10
Cr= 130pF
COIL = CTX33-4

82
80

94

C
t;
15

r""o ::;::..

1
1

84

1.00

96

.......

ILOAD = 800mA :

90
BB

LTC1265-3.3
RSENSE = 0.10
Cr= 130pF
COIL = CTX33-4

98

' ...... ILOAO = 250mA

94

il

100

I
I

98

-

VIN = 5V

I-

Efficiency vs Input Voltage
(Vour = 3.3V)

4

5

6

7 8 9 10 11
INPUT VOLTAGE (V)

lTC1265-TPC02

Operating Frequency
vs (VIN - Vour)
1.2
1.0

l:< fi
o,l . .-: I-'
~~;:c

1"25'C

IA

,
~

'"~

\

0.7

\1\..

0.6

~0.5

270

"

'\

r-...

~0.4
a:
0.3

r-....

0.2

1

2

3 4 5 6 7 8
(VIN- VOUT) VOLTAGE (V)

9

10

lTCl265TP004

4-214

o3

.... ~
~

--

r-

TJ=O'C

~

210

15

180

5

I
II

I-

a:

§5 150
<.>

~ 120

~

1/

90

30

4

.I.

60

'I j

0.1

o

~~'C

r-.... I"""- ..:!::!.=70'C

is

". ~

.1

VIN = 12V

240

0.2

o

Switch Leakage Current
300

0.8

13

lTCl265-TPC03

Switch Resistance
0.9

12

6 7 8 9 10 11 12 13
INPUT VOLTAGE (V)
LT1265·rPC05

:..,..... ......

o I-20
o

1/I-'

V

V

40
60
TEMPERATURE ('C)

80

100

LTC 1265/LTCl 265-3.3/LTCl 265-5
'PICAl PERFORmAnCE CHARAOERISTICS
DC Supply Current
2.1

Supply Current in Shutdown

DOES NOT INCLUDE
GATE CHARGE
I
I
/,,1"-.
ACTIVE MODE_ r -

1.8

1.5

SHUTDOWN = SV
TA = 25C

V

%6
asa:

1.2
0.9

a:
'-'

0.6

::::>

::::>

~

V

3

w

o

SLEEP MODE-

o

2

4
6
8
10
INPUT VOLTAGE (V)

2

V

4.5
-

o

Vrr

/

i:D 3.5
a:
§§ 3.0

0.5

a

/I

;; 2.5
z
2.0

/'

~

12

/

//

0..

O.S

Gate Charge Losses
5.5
5.0

8

e
o

V,N =9V

~N=JV-

~ /'
200

400
600
FREQUENCY (kHz)

800

1000

LTCl2&G09

In FunCTIons
~RVIN

(Pins 1, 13):Supply for the Power MOSFETand
Driver. Must decouple this pin properly to ground. Must
~ays tie pins 1 and 13 together.

SENSE+ (Pin 8): The (+) Pin to the Current Comparator. A
built-in offset between pins 7 and 8 in conjunction with
RSENSE sets the current trip threshold.

I (Pin 2):

Nle, VFB (Pin 9): For the LTC1265 adjustable version, this
pin serves as the feedback pin from an external resistive
divider used to set the output voltage. On the LTC1265-3.3
and LTC1265-5 versions, this pin is not used.

Main Supply for all the control circuitry in the

C1265.
(Pin 3): Open Drain Output of the Low-Battery
mparator. This pin will sink current when pin 4 (LBIN)
es below 1.25V. During shutdown, this pin is high
pedance.
OUT

IN (Pin 4): The (-) Input ofthe Low-Battery Comparator.
e(+) Input is connected to areference voltage of 1.25V.

(Pin 5): External capacitor CTfrom pin 5 to ground sets
off-time. The operating frequency is dependent
the input voltage and CT.

i switch

(Pin 6): Feedback Amplifier Decoupling Point. The
'rent comparator threshold is proportional to pin 6
tage.
NSE- (Pin 7): Connect to the (-) Input of the current
nparator. For LTC1265-3.3 and LTC1265-5, it also
mects to an internal resistive divider which sets the
tput voltage.

Shutdown (Pin 10): Pulling this pin HIGH keeps the
internal switch off and puts the LTC1265 in micro power
shutdown. De not float this pin.
SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (-) terminal of COUT.
PGND (Pin 12): Switch Driver Ground. Connects to the
(-) terminal of CIN. Anode of the Schottky diode must be
connected close to this pin.
SW (Pin 14): Drain of the P-Channel MOSFET Switch.
Cathode of the Schottky diode must be connected close to
this pin.

4-215

LTC 1265/LTCl 265-3.3/LTC1265-5
FunOlonAL DIAGRAm

(Pin 9 connection shown for LTC1265-3.3 and LTC1265-5; change create LTC1265)

SENSE+
8

rnl VFB
1 - - - - + - - - -.... - -L!..J
ADJUSTABLE
VERSION

Q

5pF

VTH2

5

CT

LTC12i15R12

OPERATion

(Refer to Functional Diagram)

The LTC1265 uses a constant off-time architecture to
switch its internal P-channel power MOSFET. The off-time
is set by an external timing capacitor at CT (pin 5). The
operating frequency is then determined by the off-time
and the difference between VIN and VOUT.
The output voltage is set by an internal resistive divider
(LTC1265-3.3 and LTC1265-5) connected to Sense- (pin
7) or an external divider returned to VFS (pin 9for LTC1265).
Avoltage comparator V, and a gain block G, compare the
divided output voltage with a reference voltage of 1.25V.
To optimize efficiency, the LTC1265 automatically switches
between continuous and Burst Mode operation. The voltage comparator is the primary control element when the
device is in Burst Mode operation, while the gain block
controls the output voltage in continuous mode.
When the load is heavy, the LTC1265 is in continuous
operation. During the switch ON time, current comparator
C monitors the voltage between pins 7 and 8 connected
across an external shunt in series with the inductor. When
the voltage across the shunt reaches the comparator's

4-216

threshold value, its output signal will change state, settin!
the flip flop and turning the internal P-channel MOSFET of!
The timing capaCitor connected to pin 5 is now allowed tl
discharge at a rate determined by the off-time controller
When the voltage on the timing capaCitor has dischargel
past VTH1, comparator Ttrips, sets the flip flop and cause
the switch to turn on. Also, the timing capacitor is re
charged. The inductor current will again ramp up until th
current comparator Ctrips. The cycle then repeats.
When the load current increases, the output voltage de
creases Slightly. This causes the output of the gain stag
(pin 6) to increase the current comparator threshold, thu
tracking the load current.
When the load is relatively light, the LTC1265 auto mati
cally goes into Burst Mode operation. The current loop i
interrupted when the output voltage exceeds the desire,
regulated value. The hysteretic voltage comparatorV trip
when VOUT is above the desired output voltage, shuttin,
off the switch and causing the capaCitor to discharge. Thi
capaCitor discharges past VTH1 until its voltage drop

LTC 1265/LTCl 265-3.3/LTCl 265-5
IPERATlon

(ReIer to Functional Diagram)

:Iow VTH2. Comparator Sthen trips and a sleep signal is
:nerated. The circuit now enters into sleep mode with the
Iwer MOSFETturned off. In sleep mode, the LTC1265 is
standby and the load current is supplied by the output
pacitor. All unused circuitry is shut off, reducing quiesnt current from 2mA to 160~. When the output capacir discharges by the amount of the hysteresis of the
Imparator V, the P-channel switch tu rns on again and the
ocess repeats itself. During Burst Mode operation the
:ak inductor current is set at 25mV/RsENSE.

in the gain stage. This prevents the current from increasing until the output voltage has dropped below aminimum
threshold.
Using constant off-time architecture, the operating frequency is a function of the voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the discharge current as VIN drops
below VOUT + 2V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle) providing low
dropout operation with VOUT == VIN.

I avoid the operation of the current loop interfering with
Irst Mode operation, abuilt-in offset VOS is incorporated

PPLICATlons InFORmATiOn
e basic LTC1265 application circuit is shown in Figure
External component selection is driven by the load
luirement, and begins with the selection of RSENSE.
ce RSENSE is known, CT and L can be chosen. Next, the
hottky diode D1 is selected followed by CIN and COUT.
ENSE

Selection for Output Current

ENSE is chosen based on the required output current.
th the current comparator monitoring the voltage develed across RSENSE, the threshold of the comparator
termines the peak inductor current. Depending on the
!d current condition, the threshold of the comparator
; between 25mV/RsENSE and 150mV/RsENSE. The maxi1m output current of the LTC1265 is:
IOUT(MAX) = 150mV _ IRIPPLE (A)
RSENSE
2

IOUT(MAX) = 150mV _ 25mV (A)
RSENSE
2 x RSENSE
= 137.5mV (A)

RSENSE
Solving for RSENSE and allowing a margin of variations in
the LTC1265 and extended component values yields:
RSENSE = 100mV (0) (1)
IOUTIMAXl
The LTC1265 is rated with a capability to supply a maximum of 1.2A of output current. Therefore, the minimum
value of RSENSE that can be used is 0.083Q. A graph for
selecting RSENSE versus maximum output is given in
Figure 2.
0.5

a relatively light load, the LTC1265 is in Burst Mode
3ration. In this mode the peak inductor current is set at
mVlRsENSE. To fully benefitfrom Burst Mode operation,
: inductor current should be continuous during burst
·iods. Hence, the peak-to-peak inductor ripple current
1st not exceed 25mV/RsENSE.
accountfor light and heavy load conditions, the IOUT(MAX)
hen given by:

i\
\

0.4

ere IRIPPLE is the peak-to-peak inductor ripple current.
9:

0.3

~
a:

0.2

"-

\

1,,\
I"

0.1

o

o

........ r-.

0.2
0.4
0.6
0.8
MAXIMUM OUTPUT CURRENT (A)

Figure 2. Selecting RSENSE

4-217

LTC 1265/LTCl 265-3.3/LTCl 265-5
APPLICATions InFoRmATion
Under short-circuit condition, the peak inductor current is
determined by:
ISC(PK) = 150mV (A)
RSENSE
In this condition, the LTC1265 automatically extends the
off-time of the P-channel MOSFET to allow the inductor
current to decayfar enough to prevent any current buildup. The resulting ripple current causes the average shortcircuit current to be approximately IOUT(MAX).
CT and L Selection for Operating Frequency
The LTC1265 uses a constant off-time architecture with
tOFF determined by an external capacitor CT. Each time the
P-channel MOSFET turns on, the voltage on CT is reset to
approximately 3.3V. During the off-time, CT is discharged
by acurrent which is proportional to VOUT. The voltage on
CT is analogous to the current in inductor L, which likewise, decays at a rate proportional to VOUT. Thus the
inductor value must track the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency:
C 1
( VIN - VOUT ) (F) (2)
T - 1.3 x 104 x f VIN + Vo
where Vo is the drop across the Schottky diode.
As the operating frequency is increased the gate charge
losses will reduce efficiency. The complete expression for
operating frequency is given by:
f'" _1_ (VIN - VOUT) (Hz)
tOFF VIN + Vo
where:
tOFF = 1.3 x 104 x CT x (~~~;) (sec)
VREG is the desired output voltage (Le. 5V, 3.3V). VOUT is
the measured output voltage. Thus VREGNOUT = 1
in regulation.
Note that as VIN decreases, the frequency decreases.
When the input-to-outputvoltage differential drops below

4-218

2V, the LTC1265 reduces tOFF by increasing the dischargl
current in CT. This prevents audible operation prior tt
dropout. (See shelving effect shown in the Operatin!
Frequency curve under Typical Performance Characteris
tics.)
To maintain continuous inductor current at light load, thl
inductor must be chosen to provide no more than 25mV
RSENSE of peak-to-peak ripple current. This results in thl
following expression for L:
L ~ 5.2 x 105 x RSENSE x CT x VREG (3)
Using an inductance smaller than the above value wil
result in the inductor current being discontinuous. I
consequence ofthis is thatthe LTC1265 will delay enterin!
Burst Mode operation and efficiency will be degraded a
low currents.
Inductor Core Selection
With the value of L selected, the type of inductor must bl
chosen. Basically, there are two kinds of losses in al
inductor; core and copper losses.
Core losses are dependent on the peak-to-peak rippll
current and core material. However it is independent ofthl
physical size ofthe core. By increasing the inductance, thl
peak-to-peak inductor ripple current will decrease, there
fore reducing core loss. Utilizing low core loss material
such as molypermalloy or Kool MIl® will allow user tt
concentrate on reducing copper loss and preventing satu
ration.
Although higher inductance reduces core loss, it increase:
copper loss as it requires more windings. When space i:
not at a premium, larger wire can be used to reduce thl
wire resistance. This also prevents excessive heat dissipa
tion.
CATCH DIODE SELECTION
Losses in the catch diode depend on forward drop ant
switching times. Therefore Schottky diodes are a gOOt
choice for low drop and fast switching times.
The catch diode carries load current during the off-time
The average diode current is therefore dependent on thl
Kool M~ is a registered trademark 01 Magnetics. Inc.

LTC1265/LTC1265-3.3/LTC1265-5
IPPLICATlons InFORmATion
-channel switch duty cycle. At high input voltages, the
iode conducts most of the time. As VIN approaches VOUT,
Ie diode conducts only a small fraction of the time. The
lost stressful condition for the diode is when the output
short circuited. Under this condition, the diode must
Ifely handle ISC(PK) at close to 100% duty cycle. Most
rC1265 circuits will be well served by either a1N5818 or
MBRS130LT3 Schottky diode. An MBRS0520 is agood
lOice for IOUT(MAX) ::; 500mA.
IN
I continuous

mode, the input current of the converter is
square wave of duty cycle VouTIVIN. To prevent large
Jltage transients, a low ESR input capacitor must be
)ed. In addition, the capacitor must handle a high RMS
ment. The CIN RMS current is given by:

I
[V
(V - V )]112
IMS "" OUT OUT VI~N OUT
(ARMS)

(4)

lis formula has a maximum at VIN = 2VOUT, where IRMS
IOUT/2. This simple worst case is commonly used for
lsign because even significant deviations do not offer
luch relief. Note that capacitor manufacturer's ripple
ment ratings are often based on only 2000 hours lifene. This makes it advisable to further derate the capaci'r, orto choose acapacitor rated at a higher temperature
an required. Do not underspecify this component. An
Iditional 0.1 J.tf ceramic capacitor is also required on
NR VIN for high frequency decoupling.
JUT

1e selection of COUT is based upon the effective series
sistance (ESR) for proper operation of the LTC1265.
1e required ESR of COUT is:
ESRcOUT < 50mV/IRIPPLE
here IRIPPLE is the ripple current of the inductor. For the
lse where the IRIPPLE is 25mVlRSENSE, theJequired ESR
COUT is:
ESRcOUT < 2RsENSE

(5)

) avoid overheating, the output capacitor must be sized
handle the ripple current generated by the inductor. The

worst case RMS ripple current in the output capacitor is
given by:
IRMS "" 2 :5~:~SE (ARMS)
Generally, once the ESR requirement for COUT has been
met, the RMS current rating far exceeds the IRIPPLE(P-P)
requirement.
ESR is a direct function of the volume of the capacitor.
Manufacturers such as Nichicon, AVXand Sprague should
be considered for high performance capacitors. The OSCON semiconductor dielectric capacitor available from
Sanyo has the lowest ESR for its size at asomewhat higher
price.
In surface mount applications, multiple capacitors may
have to be paralleled to meetthe capacitance, ESR or RMS
current handling requirement of the application. Aluminum electrolyte and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are both available
in surface mount configuration and are surge tested for
use in switching power supplies. An excellent choice is the
AVX TPS series of surface mount tantalums, available in
case heights ranging from 2mm to 4mm. Consult the
manufacturer for other specific recommendations.
When the capacitance of COUT is made too small, the
outp~t ripple at low frequencies will be large enough to trip
the voltage comparator. This causes Burst Mode operation to be activated when the LTC1265 would normally be
in continuous operation. The effect will be most pronounced with low value of RSENSE and can be improved at
higher frequencies with lower values of L.

Low-Battery Detection
The low-battery comparator senses the input voltage
through an external resistive divider. This divided voltage
connects to the (-) input of a voltage comparator (pin 4)
which is compared with a 1.25V reference voltage. Neglecting pin 4 bias current, the following expression is
used for setting the trip limit:
VLB_TRIP = 1.25 (1 +

~~)
4-219

LTC 1265/LTCl 265-3.3/LTCl 265-5
APPLICATions InFoRmATion
The output, pin 3, is an N-channel open drain which goes
low when the battery voltage is below the threshold set by
R3 and R4. In shutdown, the comparator is disabled and
pin 3 is in a high impedance state.

LTCl2fi!i1'03

Figure 3. Low-Ballery Comparator

THERMAL CONSIDERATIONS

In a majority of applications, the LTC1265 does not
dissipate much heat due to its high efficiency. However, in
applications where the switching regulator is running at
high duty cycles or the part is in dropout with the switch
turned on continuously (DC), the userwill need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power disSipated by the regulator
exceeds the maximum junction temperature of the part.
The temperature rise is given by:
TR = Px eJA
where Pis the power disSipated by the regulator and eJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature is simply given by:

LTC1265 ADJUSTABLE APPLICATIONS

The LTC1265 develops a1.25V reference voltage between
the· feedback (pin 9) terminal and signal ground (see
Figure 4). By selecting resistor R1, a constant current is
caused to flow through R1 and R2 to set overall output
voltage. The regulated output voltage is determined by:
VOUT = 1.25 (1 +

P = 12 x ROSON = 0.1375W

.~~ )

For the SO package, the eJA is 11 O°CIW.

For most applications a 30k resistor is suggested for R1.
To prevent stray pickup, a 100pF capacitor is suggested
across Rl located close to the LTC1265.
VOUT

R2

100pF

R1

LTC1265F04

Figure 4. LTC1265 Adjustable Configuration

4""220

TJ=TR+TA
As an example, consider the LTC1265 is in dropout at an
input voltage of 4V with a load current of O.SA. From the
Typical Performance Characteristics graph of Switch Resistance, the ON resistance of the P-channel is 0.55Q.
Therefore power dissipated by the part is:

Therefore the junction temperature of the regulator when
it is operating in ambient temperature of 25°C is:
. TJ= 0.1375 x 110 + 25 = 40.1 °C
Remembering that the above junction temperature is
obtained from a ROSON at 25°C, we need to recalculate the
junction temperature based on a higher ROSON since it
increases with temperature. However, we can safely assume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Now consider the case of a1A regulator with VIN = 4Vand
TA= 65°C. Starting with the same O.55Q assumption for
ROSON, the TJ calculation will yield 125°C. But from the
graph, this will increase the ROSON to 0.76Q, which when
used in the above calculation yields an actual TJ > 148°C.
Therefore the LTC1265 would be unsuitable for a4V input,
1A output regulator operating at TA = 65°C.

LTC 1265/LTCl 265-3.3/LTCl 265-5
PPLICATlons InFORmATion
lard Layout Checklist
hen laying out the printed circuit board, the following
ecklist should be used to ensure proper operation of the
'C1265. These items are also illustrated graphically in
~ layout diagram of Figure 5. Check the following in your
'out:
Are the signal and power grounds segregated? The
LTC1265 Signal ground (pin 11) must return to the (-)
plate of COUT. The power ground (pin 12) returns to the
anode of the Schottky diode, and the H plate of CIN,
whose leads should be as short as possible.

4. Is the Schottky diode closely connected between the
power ground (pin 12) and switch (pin 14)?
5. Does the LTC1265 Sense- (pin 7) connect to a point
close to RSENSE and the (+) plate of COUT? In adjustable
applications, the resistive divider, R1 and R2, must be
connected between the (+) plate of COUT and signal
ground.
6. Are the Sense- and Sense+ leads routed together with
minimum PC trace spacing? The 1000pF capacitor
between pins 7 and 8 should be as close as possible to
the LTC1265.

Does the (+) plate of the CIN connect to the power VIN
(pins 1,13) as close as possible? This capacitor provides the AC current to the internal P-channel MOSFET
and its driver.

7. Is Shutdown (pin 10) actively pulled to ground during
normal operation? The Shutdown pin is high impedance and must not be allowed to float.

Is the input decoupling capacitor (0.1 j.If) connected
closely between power VIN (pins 1,13) and power
ground (pin 12)? This capacitor carries the high frequency peak currents.

1k

I

RSENSE

I

I
I

'---+-......--+--.-- Your
.. _------

I
I

OUTPUT DIVIDER REQUIRED
WITH ADJUSTABLE VERSION ONLY

BOLD LINES INDICATE
HIGH PATH CURRENTS

Figure 5. LTC1265 Layout Diagram (See Board Layout Checklist)

4-221

LTC1265ILTC1265-3.3/LTC1265~5

APPLICATions InFoRmATion
Troubleshooting Hints
Since efficiency is critical to LTC1265 applications, it is
very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation. As
the LTG1265is highly tolerant of poor layout, the output
voltage will still be regulated. Therefore, monitoring the
output voltage will not tell you whether you have agood or
bad layout. The waveform to monitor is the voltage on the
timing capacitor pin 5.
In continuous mode the voltage on the CT pin is asawtooth
with approximately O.9Vp_p swing. This voltage should
never dip below 2V as shown in Figure 6a.

When the load currents are low (lLOAD < IBURST) Bur:
Mode operation occurs. The voltage on CT pin now falls 1
ground for periods of time as shown in Figure 6b. Durin
this time the LTC1265 is in sleep mode with quiescel
current reduced to 1601!A.
The inductor current should also be monitored. If tt
circuit is poorly decoupled, the peak inductor current w,
be haphazard as in Figure 7a. A well decoupled LTC126
has a clean inductor current as in Figure 7b.

I'
on
z

on

3.3V

z
~

~

SLEEP MODE

_I

3.3V

<:; 2.4V

I----->-.---'--'I---------~--->-.---'-­

!;;:

w~---------------------TIME
(a) CONTINUOUS MODE OPERATION
LTC1265F07

ovL-------~-----L------TIME
(b) Burst Mode OPERATION

Figure 6. CT Waveforms

(a) POORLY DECOUPLED LTC1265

(b) WELL DECOUPLED LTC1265

Figure 7. Inductor Waveforms

4-222

LTC 1265/LTCl 265-3.3/LTCl 265-5
~PPLICATlons

InFORmATion

lesign Example
\s a design example, assume VIN =5V, VOUT =3.3V, IMAX
: 0.8A and f = 250kHz. With this information we can easily
:alculate all the important components.
:rom (1),
RSENSE =100mVlO.8 =0.1250
rom (2) and assuming VD = O.4V,
CT= 100pF
Ising (3), the value of the inductor is:
LTC126!1-F06

Figure 8. Design Example Circuit

.25.2 x 105 x 0.125 x 100pF x 3.3V = 221lH
or the catch diode, a MBRS130LT3 or 1N5818 will be
ufficient in this application.
:IN will require an RMS current rating of at least O.4A at
emperature, and COUT will require an ESR of (from 5):
ESRCOUT < 0.250

•

100
L = DALE LPT4545-220
VOUT= 3.3V
Cp 100pF

95
-

C

90

(22~H)

I-"

>-

~ 85

'he inductor ripple current is given by:
IRIPPLE =

(Vour VD) tOFF = 0.22A

.t light loads the peak inductor current is at:
IpEAK

=25mVlO.125 =0.2A

herefore, at load current less than 0.1 Athe LTC1265 will
e in Burst Mode operation. Figure 8 shows the complete
ircuit and Figure 9 shows the efficiency curve with the
bove calculated component values.

L7lJ!J~

<3

~

80
75
70

0.01

0.1
LOAD CURRENT (mA)

1.0

Figure 9. Design Example Efficiency Curve

4-223

LTC 1265/LTC 1265~3,3/LTC 1265-5
TYPICAL APPLICAnOnS

High Efficiency 5V 10 3.3V Converter
VIN -1~--'::---'-:--::--""'--,
5V
VOUT

...;..;..+---+-:<.........rY"YY"\-.--'\M.......~....."'-_-3.3V
lA

'AVX TPSD107K010
"AVX TPSE227K010
tCOILCRAFT D03316·473
ttDALE WSL201 0·0.1-1 %

L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

LTCl265f15

Positive-Io-Negative (-5V) Converter
'AVX TPSD226K025
"AVX TPSD107K010
tL1 SELECTION
PART NO.
MANUFACTURER
003316-473
COILCRAFT
CTX50-4
COILTRONICS
LPT4545-500LA
OALE
C074-470
SUMIDA
ttlRC LRC2010-01-Rl00-J
01= MBRS130LT3

3.5
4.0
5.0
6.0
7.0
7.5

IOUT(MAXI (mA)
360
430
540
630
720
740

3.5VT07~~-1~-"""--1~---""'-===----'--"'"

..;.;;..---11-.....----+6--.......,,...- ~~W

COUTO'
100llF

+ 10V
RSENSEtt
O.la

LTCl265F16

4-224

LTC 1265/LTCl 265-3.3/LTC1265-5
rYPICAl APPLICATions

5V Buck-Boost Converter
VIN (V)
3.5
4.0
5.0
6.0
7.0
7.5

IOUT(MAJ() (rnA)
240
275
365
490
610
665

35V TO 7~u

. . . p---1~--1~~-....--.....,
L1Att
33J.lH

VOUT 5V
2

75k
,
COUT
100J.lF,10V

+

,SANYO OS-CON CAPACITOR
.. IRC LRC2010-01-R162-J
tL 1A, L2A SELECTION

100pF

25k

MANUFACTURER
PART NO,
""CcccOI'"'LT=Rccc
ONccIC=-CS:--+-"'CT=X33-4
DALE
LPT4545-330LA

9V to 12V and -12V Outputs
MBRS130LT3
'IN (V)
1.0

i.O
i.0
'.0
1.0
1.0
0.0
1.0
2.0

IOUT(MAXI (rnA)
40
60
80
100
115
130
150
165
180

VIN
4VT012V

r----~I_----.....- - - ~f~v

.,;",;,.-+-.....-+-....... ,..-+-1

L1Att
50J,lH

1-'-....--o1r;:.'rY-v;2~--....-

301k

L1stt
50J.lH

'AVX TPSE686K020
'AVX TPSE336K025
tlRC LRC2010-01-R162-J
tL 1A,L2A SELECTION
~ANUFACTURER

PART NO,

;OILTRONICS
lALE

CTX50-4
LPT4545-500LA

¥g~T

MBRS130LT3

RSENSE'
0.162Q

+

100pF

COUT'
68J.lF
20V

34k

4-225

LTC 1265/LTCl 265-3.3/LTC1265-5
TYPICAL APPLICATions
2.Smm Max Height SY-to-3.3Y (SDDmA)
3.5V TO

12~~ ~~--+,....-.,....,.,..-.....--..,

-AVXTAJB156K010
--AVX TAJB226K06
tl RC LRC2010-01-R200-J
ttSUMIDA CLS62-180

COUT-22~F

+ 6.3Vx2

VOUT
.....------------------4.....--_- 3.3V
500mA

Logic Selectable DV/3.3VI5V 7DDmA Regulator
'DALE 593D68X0020E2W
"DALE 593Dl 07XOOI OD2W
tlRC LRC2010-01-R15-J
ttL1 SELECTION

3.5V TO

12~~ ----.::---'9':'''':'':''-.....- - . ,

MANUFACTURER
COILCRAFT
CDILTRONICS
DALE
SUMIDA

PART NO.
D03316-333
CTX33-4
LPT4545-330LA
CD74-330

tt1VSHDN =OV: VOUT =3.3V/5V
= 5V: VOUT = OV

45.3k
COUT-100~F

10V
56.2k
VOUT
.....-----------------4---t--....--4.... OV/3.3V/5V
700mA

4-226

LTC 1265/LTCl 265-3.3/LTCl 265-5
'YPICAL APPLICATions
4-NiCad Battery Charger

8VTO 12~~ -

....-t--1~::--1r--...,

'DALE 5930226X0025D2W
"DALE 59301 07X0016E2W
tDALE WSL2010-0.10-1%
ttL1 SELECTION

MANUFACTURER

PART NO.
003316-104
CTX100-4P
C01 05-1 01

COILCRAFT
COILTRONICS
SUMIDA

510

L1tt

:AST CHARGE: = OV
IICKLE CHARGE: >

100~H

y

30k

+

COUT"
100~F,

10V

138k
MBRS130LT3

VOUT

L - - - - - - - - - - - - - - - -....- -....- .....--1M--- i:~~~~CHARGE
O.1A TRICKLE CHARGE

IELATED PARTS
IRT NUMBER
·C1142

DESCRIPTION
Dual Step-Down Switching Regulator Controller

COMMENTS
Dual Version of LTC1148
Dual Version of LTC1147

·C1143

Dual Step-Down Switching Regulator Controller

·C1147

Step-Down Switching Regulator Controller

Nonsynchronous, 8-Pin, VIN ~ 16V

·C1148

Step-Down Switching Regulator Controller

Synchronous, VIN ~ 20V

·C1149

Step-Down Switching Regulator Controller

Synchronous, VIN ~ 48V, for Standard Threshold FETs

·C1159

Step-Down Switching Regulator Controller

Synchronous, VIN ~ 40V, for Logic Level FETs

"C1174

Step-Down Switching Regulator with Internal O.5A Switch

VIN ~ 18.5V, Comparator/Low Battery Detector

C1266

Step-Up/Down Switching Regulator Controller

Synchronous N- or P-Channel FETs, Comparator/Low Battery Detector

C1574

Step-Down Switching Regulator with Internal O.5A Switch
and Schottky Diode

VIN ~ 18.5V, Comparator

4-227

.a=Ar\
L1n
£7. U \K
FEATURES

LTC126c
LTC1266-3.3/LTCl 266-E
. TECHNOLOG~f{~---Sy-n-C-h-ro-n-o-u-s-R-e-g-u-la-t-ol
Controller fOI
N- or P-Channel MOSFET~
DESCRIPTiOn

• Ultra-High Efficiency: Over 95% Possible
• Drives N-Channel MOSFET for High Current or
P-Channel MOSFET for Low Dropout
• Pin Selectable Burst Mode Operation
• 1% Output Accuracy (LTC1266A)
• Pin Selectable Phase of Topside Driver for Boost
or Step-Down Operation
• Wide VIN Range: 3.SV to 20V
• On-Chip Low-Battery Detector
• High Efficiency Maintained over Large Current Range
• Low 170~ Standby Current at Light Loads
• Current Mode Operation for Excellent Line and Load
Transient Response
• Logic Controlled Micropower Shutdown: 10 < 40~
• Short Circuit Protection
• Synchronous Switching with Nonoverlaping Gate Drives
• Available in 16-Pin Narrow SO Package

APPLICATions
•
•
•
•
•

Notebook and Palmtop Computers
Portable Instruments
Cellular Telephones
DC Power Distribution Systems
GPS Systems

TYPICAL APPLICATiOn

The LTC@1266series is afamily of synchronous switchin~
regulator controllers featuring automatic Burst Moden
operation to maintain high efficiencies at low outpul
currents. These devices drive external power MOSFETs al
switching frequencies up to 400kHz using aconstant off·
time current mode architecture providing constant ripple
current in the inductor. They can drive either an N-channe
or a P-channel topside MOSFET.
The operating current level is user-programmable via ar
external current sense resistor. Wide input supply range
allows operation from 3.SV to 18V (20V maximum).
Constant off-time architecture provides low dropout regu·
lation limited only by the RDS(DN) of the topside MOSFEl
(when using the P-channel) and the resistance of the
inductor and current sense resistor.
The LTC1266 series combines synchronous switching fOI
maximum efficiency at high currents with an automatic
low current operating mode, called Burst Mode operation.
which reduces switching losses. Standby power is reo
duced to only 1mW at VIN = SV (at lOUT = 0). Load currents
in Burst Mode operation are typically OmA to SOOmA.
D', LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.

02

LTC1266-3.3 Efficiency

MBR0530T1
100

VIN = 5V

95

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1.5
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LOAD CURRENT (A)

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~ [""'Iiii;;,OPERATI10N INHiBITED)

50

ACTIVE MODE

15

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VIN = 12V (Burst Mode
OPERATION ENABLED)

Supply Current in Shutdown

Power VIN DC Supply Current
25

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INPUT VOLTAGE (V)

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INPUT VOLTAGE (V)

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16

Operating Frequency
vs (VIN - VOUT) Voltage

Off·Time vs Output Voltage
100

PWRVIN

SLEEP MODE

o
o

20

20

10
15
INPUT VOLTAGE (V)

LTC1266'TI'{;08

LTCl266·TPC09

Current Sense Threshold Voltage
200

Vour= 3.3V

MAX THRESHOLD
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OUTPUT VOLTAGE (V)

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4-232

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40
60
TEMPERATURE (OC)

80

10(

LTCl266·TPC12

LTC 1266
LTC 1266-3 ,3/LTC1266-5

Pin FunCTions
TDrive (Pin 1): High Current Drive for Topside MOSFET.
This MOSFET can be either P-channel or N-channel, user
selectable by Pin 3. Voltage swing at this pin is from PWR
VIN to ground.
PWR VIN (Pin 2): Power Suppy for Drive Signals. Must be
closely decoupled to power ground (Pin 15).
PINV (Pin 3): Phase Invert. Sets the phase of the topside
driverto drive either aP-channel or an N-channel MOSFET
as follows:

P-channel: Pin 3 = OV
N-channel: Pin 3 = PWR VIN
BINH (Pin 4): Burst Mode Operation Inhibit. ACMOS logic
high on this pin will disable the Burst Mode operation
feature forcing continuous operation down to zero load.
VIN (Pin 5): Main Supply Pin.
el (Pin 6): External Capacitor. Clfrom Pin 4to ground sets
the operating frequency. The actual frequency is also
dependent on the input voltage.

hH (Pin 7): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 7 voltage.
Sense- (Pin 8): Connects to internal resistive divider
which sets the output voltage in LTC1266-3.3 and
LTC1266-5 versions. Pin 8 is also the (-) input for the
current comparator.

Sense+ (Pin 9): The (t) Input to the Current Comparator.
A built-in offset between Pins 8 and 9 in conjunction with
RSENSE sets the current trip threshold.
VFB (Pin 10): For the LTC1266 adjustable version, Pin 10
serves as the feedback pin from an external resistive
divider used to set the output voltage. On LTC1266-3.3
and LTC1266-5 versions this pin is not used.
SHDN (Pin 11): When grounded, the LTC1266 series
operates normally. Pulling Pin 11 high holds both MOSFETs
off and puts the LTC1266 in micropower shutdown mode.
Requires CMOS logic signal with tr, tf < 1J.IS. Should not be
left floating.
SGND (Pin 12): Small-Signal Ground. Must be routed
separately from other grounds to the (-) terminal of COUTo
LBIN (Pin 13): Input to the Low-Battery Comparator. This
input is compared to an internal1.25V reference.
LBoUl (Pin 14): Open Drain Output of the Low-Battery
Comparator. This pin will sink current when Pin 13 is
below 1.25V.
PGND (Pin 15): Driver Power Ground. Connects to source
of N-channel MOSFET and the (-) terminal of CIN.
BDrive (Pin 16): High Current Drive for Bottom N-Channel MOSFET. Voltage swing at Pin 16 is from ground to
PWR VIN.

4-233

III

LTC 1266
LTC 1266-3.3/LTCl 266-5
FunCTionAL DIAGRAm

Pin 10 Connection Shown for LTC1266-3.3 and LTC1266-5; Changes Create LTC1266

1 TDRIVE
SENSE+

SIGNAL
GROUND

SENSE-

9

~

ADJUSTABLE
VERSION
VFB

I§l

5pF

MAX
ON-TIME
CONTROL
ENABLE

+- -

PINV

OPERATion
The LTC1266 series uses a current mode, constant offtime architecture to synchronously switch an external pair
of power MOSFETs. Operating frequency is set by an
external capacitor at the timing capacitor Pin 6.
The output voltage is sensed by an internal voltage divider
connected to Sense -, Pin 8, (LTC1266-3.3 and LTC12665) or external divider returned to VFB, Pin 10, (LTC1266).
A voltage comparator V, and a gain block G, cornpare the
divided output voltage with a reference voltage of 1.25V.
To optimize efficiency, the LTC1266 automatically switches
between two modes of operation, burst and continuous.
The voltage comparator is the primary control element
when the device is in Burst Mode operation, while the gain
block controls the output voltage in continuous mode.

4-234

During the switch ON cycle in continuous mode, current
comparator Cmonitors the voltage between Pins 8 and 9
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the topside driver output is switched to
turn off the topside MOFSET (Power VIN for P-channel or
ground for N-channel). The timing capacitor connected to
Pin 6 is now allowed to discharge at a rate determined by
the off-time controller. The discharge current is made
proportional to the output voltage (measured by Pin 8) to
model the inductor current, which decays at a rate which
is also proportional to the output voltage. While the timing
capacitor is discharging, the bottom-side drive output is
switched to power VIN to turn on the bottom-side
N-channel MOSFET.

LTC1266
LTC 1266-3.3/LTCl 266-5
)PERATlon
Vhen the voltage on the timing capacitor has discharged
last VTH1, comparator T trips, setting the flip-flop. This
:auses the bottom-side output to switch off and the
opside output to switch on (ground for P-channel and
lower VIN for N-channel). The cycle then repeats.
Isthe load current increases, the output voltage decreases
,lightly. This causes the output of the gain stage (Pin 7) to
ncrease the current comparator threshold, thus tracking
he load cu rrent.
'he sequence of events for Burst Mode operation is very
,imilarto continuous operation with the cycle interrupted
Iy the voltage comparator. When the output voltage is at
Irabovethe desired regulated value, the topside MOSFET
s held off by comparator V and the timing capacitor
:ontinues to discharge below VTH1. When the timing
:apacitor discharges past VTH2, voltage comparator S
rips, causing the internal sleep line to go low and the
lottom-side MOSFET to turn off.
'he circuit now enters sleep mode with both power
nOSFETs turned off. In sleep mode, a majority of the
:ircuitry is turned off, dropping the quiescent current
rom 2.1 mA to 170JlA. The load current is now being
upplied from the output capacitor. When the output
'oltage has dropped by the amount of hysteresis in
omparator V, the topside MOSFET is again turned on
.nd this process repeats.
'0 avoid the operation of the current loop interfering with
lurst Mode operation, abuilt-in offset Vas is incorporated
1 the gain stage. This prevents the current comparator
hreshold from increasing until the output voltage has
lropped below a minimum threshold.

To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the
bottom-side drive output can turn on, the topside output
must be off. Likewise, the topside output is prevented
from turning on while the bottom-side drive output is
still on.
The LTC1266 has two select pins which provide the user
with choice of topside switch and with the option of
inhibiting Burst Mode operation. The phase select pin
allows the user to choose whether the topside MOSFET
is aP-channel or an N-channel. The phase select pin does
two things: sets the proper phase of the drive signal (ON
=Power VIN for N-channel and ON =OV for P-channel)
and also sets an upper limit for the on-time (60!JS) when
set to the N-channel. The on-time limit ensures proper
start-up when used in a single supply bootstrap circuit
configuration (see Applications Information). In P-channel •
mode there is no on-time limit and thus, in dropout, the
P-channel MOSFET is turned on continuously (100%
duty cycle).
The Burst Mode operation inhibit (BINH, Pin 4) allows the
Burst Mode operation to be disabled by applying a CMOS
logic high to this pin. With Burst Mode operation disabled,
the LTC1266 will remain in continuous mode down to zero
load. Burst Mode operation is disabled by allowing the
lower current threshold limit to go below zero so that the
voltage comparatorwill never trip. Thevoltage comparator
trip point is also raised up so that it will not be tripped by
transients. It is still active to provide a voltage clamp to
prevent the output from overshooting.

IPPLICATlons InFORmATiOn
)ne of the three basic LTC1266 application circuits is
hown in Figure 1. This circuit uses an N-channel
:>pside driver and a single supply. The other two circuit
onfigurations (see Typical Applications) use an
I-channel topside driver and dual supply, and a
I-channel topside driver. Selections of other external
omponents are driven by the load requirement and are
1e same for all three circuit configurations. The first

L7lJ!J~

step is the selection of RSENSE. Once RSENSE is known,
CT and L can be chosen. Next, the power MOSFETs and
D1 are selected. Finally, CIN and COUT are selected and
the loop is compensated. Using an N-channel topside
switch, input voltages are limited to a maximum of
about 15V. With a P-channel, the input voltage may be
as high as 20V.

4-235

LTC1266
LTCl 266-3.3/LTCl 266-5
APPLICATions InFoRmATion
RSENSE Selection for Output Current

RSENSE is chosen based on the required output current.
The LTC1266 series current comparator has a threshold
range which extends from a minimum of 25mVlRsENSE
(when Burst Mode operation is enabled) to amaximum of
155mVlRsENSE. The current comparator threshold sets
the peak of the inductor ripple current, yielding a maximum output current IMAX equal to the peak value less half
the peak-to-peak ripple current. For proper Burst Mode
operation, IRIPPLE(P-P) must be less than or equal to the
minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, Le.,
IRIPPLE(P-P) = 25mV/RsENSE (see CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing
a margin for variations in the LTC1266 series and
external component values yields:
RSENSE = 101 OmV
MAX

A graph for selecting RSENSE vs maximum output
current is given in Figure 2.
100

1\

75

The LTC1266 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short circuit current
ISC(AVG) to be reduced to approximately IMAX.
Land CT Selection for Operating Frequency
The LTC1266 series uses aconstant off-time architecture
with tOFF determined by an external timing capacitor CT.
Each time the topside MOSFET switch turns on, the
voltage on CT is reset to approximately 3.3V. During the
off-time, CT is discharged by a current which is proportional to VOUT. The voltage on CT is analogous to the
current in inductor L, which likewise decays at a rate
proportional to VOUT. Thus the inductor value must track
the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency, f:

,

1

T - 2.6 x 104 x f

assumes VIN = 2VOUT, (Figure 1 circuit).

Agraph for selecting CT vs frequency including the effects
of input voltage is given in Figure 3.

1\

a

155mV
ISC(PK)= - RSENSE

C -

\

~

25

15mV
IBURST"" -.-RSENSE

i""- t-

a

800

10

I

600

MAXIMUM OUTPUT CURRENT (A)

1\

1\
\

\ 1\

Figure 2. Selecting RSENSE

The load current, below which Burst Mode operation
commences, (IBURST), and the peak short circuit current, (ISC(PK)), both track IMAX. Once RSENSE has been
chosen, IBURST and ISC(PK) can be predicted from the
following:

Vour=3.3V

f\.

200

VIN = 5V

a

~

VIN=12V

" -.......

t-

a

100

200
300
FREQUENCY (kHz)

400

500

Figure 3. Timing Capacitor Value

4-236

LTC1266
LTC 1266-3 .3/LTC1266-5
APPLICATions InFoRmATion
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
f = _1_ (1 _ VOUT)
tOFF
VIN
where:
tOFF = 1.3 x 104 x CT x (VREG)
VOUT
VREG is the desired output voltage (Le., 5V, 3.3V). VOUT isthe
measured output voltage. Thus VREGNOUT =1 in regulation.
Once the frequency has been set by CT, the inductor L
must be chosen to provide no more than 25mV/RSENSE
of peak-to-peak inductor ripple current. This results in
a minimum required inductor value of:
LMIN

=5.1 x 105 x RSENSE x CT x VREG

As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor
are eased at the expense of efficiency. If too small an
inductor is used, the inductor current will decrease past
zero and change polarity. A consequence of this is that
the LTC1266 series may not enter Burst Mode operation
and efficiency will be slightly degraded at low currents.

Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. The highest efficiency will be
obtained using ferrite, Kool MIl® on molypermalloy (MPP)
cores. Lower cost powdered iron cores provide suitable
performance but cut efficiency by 3% to 7%. Actual core
loss is independent of core size for afixed inductor value,
but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates "hard," which means that
inductance collapses abruptly when the peak design curKool M~ is a regisiered trademark of Magnetics, Inc.

rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode operation to be falsely
triggered. Do not allow the core to saturate!
Kool Mllis avery good, low loss core material fortoroids,
with a "soft" saturation characteristic. Molypermalloy is
slightly more efficient at high (>200kHz) switching frequency. Toroids are very space efficient, especially when
you can use several layers of wire. Because they generally
lack a bobbin, mounting is more difficult. However, new
designs for surface mount are available from Coiltronics
and Beckman Industrial Corp. which do not increase the
height significantly.

Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1266 series: either aP-channel MOSFET or an . .
N-channel MOSFET for the main switch and an N-channel . .
MOSFET for the synchronous switch. The main selection
criteria forthe power MOSFETs are the type of MOSFET,
threshold voltage VGS(TH) and on-resistance RDS(ON).
The cost and maximum output current determine the type
of MOSFET for the topside switch. N-channel MOSFETs
have the advantage of lower cost and lower RDS(ON) at the
expense of slightly increased circuitcomplexity. For lower
current applications where the losses due to ROS(ON) are
small, a P-channel MOSFET is recommended due to the
lower circuit complexity. However, at load currents in
excess of 3A where the ROS(ON) becomes a Significant
portion of the total power loss, an N-channel is strongly
recommended to maximize efficiency.
The maximum output current IMAX determines the ROS(ON)
requirement for the two MOSFETs. When the LTC1266
series is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the average load current. The duty
cycles for the two MOSFETs are given by:
TopSide Duty Cycle = VVOUT
IN
Bottom-Side Duty Cycle = VIN - VOUT
VIN

4-237

LTC1266
LTC1266-3.3/LTC1266-5
APPLICATions InFoRmATion
From the duty cycles, the required ROS(ON) for each
MOSFET can be derived:
TS ROS(ON) =

VIN x PT
VOUT x IMAX2 x (1 + Or)

BS ROS(ON) =

VIN x PB
(VIN - VOUT) x IMAX2 x (1 + 0B)

where PTand PB are the allowable power dissipations and
oTand OB are the temperature dependencies of ROS(ON)' PT
and PB will be determined by efficiency and/or thermal
requirements (see EfficiencyGonsiderations). Fora MOSFET,
(1 + 0) is generally given in the form of a normalized
ROS(ON) vs temperature curve, but OPCH = 0.007/oGand
ONCH = O.OOS/oG can be used as an approximation for low
voltage MOSFETs.
The minimum input voltage determines whether standard
threshold or logic-level threshold MOSFETs must be used.
For VIN > 8V, standard threshold MOSFETs (VGS(TH) <4V)
may be used. If VIN is expected to drop below 8V, logiclevel threshold MOSFETs (VGS(TH) < 2.SV) are strongly
recommended. The LTG1266 series Power VIN must always be less than the absolute maximum VGS ratings for
the MOSFETs.
The Schottky diode 01 shown in Figure 1 only conducts
during the deadtime between the conduction of the two
power MOSFETs. 01 's sole purpose in life is to preventthe
body diode of the bottom-side MOSFET from turning on
and storing charge during the deadtime, which could cost
as much as 1% in efficiency (although there are no other
harmful effects if 01 is omitted). Therefore, 01 should be
selected for a forward voltage of less than 0.7Vwhen
conducting IMAX.
GIN and GOUT Selection

In continuous mode, the current through the topside
MOSFET is a square wave of duty cycle VouTIVIN. To
prevent large voltage transients, a low ESR (Effective
Series ReSistance) input capacitor sized forthe maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
GIN Required IRMS "" IMAX [VOUT(VIN - VOUT)] 1/2
VIN

4-238

This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor
manufacturer's ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question. An additional 0.1 ~
to 1~ ceramic capacitor is also required on Power VIN
(Pin 2) for high frequency decoupling.
The selection of GOUT is driven by the required ESR. The
ESR of COUT must be less than twice the value of RSENSE
for proper operation of the LTC1266 series:
GOUT Required ESR < 2RsENSE
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RsENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RsENSE, the voltage ripple on the output capacitor
will prematurely trigger Burst Modeoperation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent. If Burst Mode operation is disabled, the ESR requirement can be relaxed and is limited
only by the allowable output voltage ripple.
Manufacturers such as Nichicon and United Ghemicon
should be considered for high performance capacitors.
The OS-GON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR/size ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for GOUT has been met, the RMS current
rating generally far exceeds the IRIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
have tobe paralleled to meetthe capaCitance, ESR or RMS
current handling requirements of the application. An
excellent choice is the AVX TPS series of surface mount
tantalums.
At low supply voltages, aminimum capaCitance at GOUT
is needed to prevent an abnormal low frequency operating mode (see Figure 4). When GOUT is made too
small, the output ripple at low frequencies will be large
enough to trip the voltage comparator. This causes
Burst Modeoperation to be activated when the LTG1266

LTC1266
LTC 1266-3.3/LTCl 266-5
APPLICATions InFoRmATion
1000

f'..

800

Jl'kt

r-.... .......
~SENSE = 0.020

~ 600

....

5
CJ

r-.. ......

400

200

........

..................

........

.........

.........

.........

.........

L=50~H"""
RSENSE = 0.050

o
o

Driving N-Channel Topside MOSFETs

L = 50~H

........ ~ENSIE = 0i02~

I· T i l

r-..

r-.. r-..
r-.. r-..

(VIN - VOUT) VOLTAGE (V)

Figure 4. Minimum Value of COUT

series would normally be in continuous operation. The
output remains in regulation at all times. This minimum
capacitance requirement may be relaxed if Burst Mode
operation is disabled.
N-Channel vs P-Channel MOSFETs
The LTC1266 has the capability to drive either an
N-channel or a P-channel topside switch to give the user
more flexibility. N-channel MOSFETs are superior in performance to P-channel due to their lower ROS(ON) and
lower gate capacitance and are typically less expensive;
however, they do have a slightly more complicated gate
drive requirement and a more limited input voltage range
(see following sections).
Driving P-Channel Topside MOSFETs
The P-channel topside switch circuit configuration is the
most straightforward due to the requirement of only one
supply voltage level. This is due to the negative gate
threshold of the P-channel MOSFET which allows the
MOSFET to be switched on and off by swinging the gate
between VIN and ground. The phase invert (Pin 3) is tied
to ground to choose this operating mode. Normally, the
converter input (VIN) is connected to the LTC1266 supply
Pins 2and 5 and can go as high as 20V. Pin 2 supplies the
high frequency current pulses to switch the MOSFETs and
should be decoupled with a0.1 J.Jf to 1J.Jf ceramic capacitor. Pin 5 supplies most of the quiescent power to the rest
of the chip.

Driving an N-channel topside MOSFET (PINV, Pin 3, tied to
PWR VIN) is a little trickier than driving a P-channel since
the gate voltage must be positive with respect to the
source to turn it on, which means that the gate voltage
must be higher than VIN. This requires either a second
supply at leastVGS(ON) above VIN ora bootstrapping circuit
to boost the VIN to the proper level. The easiest method is
using a higher supply (see Figure 14) but if one is not
available, the bootstrap method can be used at the expense of an additional diode (see Figure 1). The bootstrap
works by charging the bootstrap capacitor to VIN during
the off-time. During the on-time, the bottom plate of the
capacitor is pulled up to VIN so that the voltage at Pin 2 is
now twice VIN (plus any ringing on the switch node).
Since the maximum allowable voltage at Pin 2 is 20V, the
Figure 1 bootstrap circuit limits VIN to less than 10V. A _
higher VIN can be achieved if the bootstrap capacitor is . .
charged to a voltage less than VIN, in which case
VIN(MAX) =20 - VCAP·
N-channel mode, internal Circuitry limits the maximum
on-time to 60flS to guarantee start-up of the bootstrap
circuit. This maximum on-time reduces the maximum
duty cycle to:
Max Duty Cycle = 60 60,...,~
,...,S + OFF
which slightly increases the minimum input voltage at
which dropout occurs. However, because of the superior
on-conductance of the N-channel, the dropout performance of an all N-channel regulator is still better (see
Figure 5) even with the duty cycle limitation, except at light
loads.
Low-Battery Comparator
The LTC1266 has an on-chip low-battery comparator
which can be used to sense a low-battery condition when
implemented as shown in Figure 6. The resistor divider
R1, R2 sets the comparator trip point as follows:
VTRIP = 1.25 (1 +

~~)

4-239

LTC1266
LTC 1266-3.3/LTCl 266-5
APPLICATions InFORmATion
600

5
IE

~

c

500

VOUT ~ 3.3V

I I

~I

T6pSIbE
400 I--P-CHANNE,/

v

!;;:

'> 300
g
....

t/"

2l 200

t
;>

100

......

/

A

/ ...... "

',4
I
o

100

iOP~IDE

1

Burst Mode OPERATION
ENABLED

/N-CHANNEL WITH
CHARGE PUMP

v

90

v "

......

/

L

/

II Burst Mode OPERATION

/

INHIBITED

...... f"""

......

TOPSIOE N-CHANNEL ~ITH IPO~ER ~IN =112V I--

70

60
0.01

o

LOAD CURRENT

0.1
1
LOAD CURRENT (Al

Figure 5. Comparison of Dropout Performance

Figure 7. Effect of Disabling Burst Mode Operation on Efficiency

LBOUT

LTC12El6-F06

Figure 6. Low-Battery Comparator

The divided down voltage atthe "-" inputto the comparator
is compared to an internal1.25V reference. This reference
is separate from the 1.25V reference used by the voltage
comparator and current comparator for regulation and is
not disabled by the shutdown pin, therefore the low-battery
detection is operational even when the rest of the chip is
shut down. The comparator is functional down to an input
voltage of 2.5V. Thus, the output will provide avalid state
even when the rest of the chip does not have sufficient
voltage to operate. For best performance, the value of the
pull-up resistor should be high enough that the output is
pulled down to ground when sinking 200~ or less.

Suppressing Burst Mode Operation
Normally, enabling Burst Mode operation is desired due to
its superior efficiency at low load currents (see Figure 7).
However, in certain applications it may be desirable to
inhibit this feature. Some reasons for dOing so are:
1. To eliminate audible noise from certain types of inductors at light loads.

4-240

2. If the load is never expected to drop low enough to
benefit from the efficiency advantages of Burst Mode
operation, the output capacitor ESR and minimum
capacitance requirements (which may falsely trigger
Burst Mode operation if not met) can be relaxed if Burst
Mode operation is disabled.
3. If an auxiliary winding is used. Disabling Burst Mode
operation guarantees switching independent of the
load on the primary. This allows powerto be taken from
the auxiliary winding independently.
4. Tighter load regulation « 1%).
Burst Mode operation is disabled by applying a CMOS
logic high voltage (>2.1V) to Pin4. When it isdisabled, the
voltage comparator limit is raised high enough so that it no
longer is involved in regulation; however it is still active
and is useful as a voltage clamp to keep the output from
overshooting.
Note that since the inductor current must reverse to
regulate the output at zero load when Burst Mode operation is disabled, the minimum inductance (LMIN) specified
during Inductor Core Selection is no longer applicable.

Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT shifts by an
amount equal to dlLOAD (ESR), where ESR is the effective
series resistance of COUTo dlLOAD also begins to charge or

LTC 1266
LTC 1266-3.3/LTCl 266-5
APPLICATions InFoRmATion
discharge COUT until the regulator loop adapts to the
current change and returns VOUTto its steady-state value.
During this recovery time VOUT can be monitored for
overshoot or ringing which would indicate a stability
problem. The Pin 7 external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.

Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
% Efficiency = 100% - (L1 + L2 + L3 + ... )
where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits, only small
errors are incurred by expressing losses as a percentage
of output power).
Although all dissipative elements in the circuit produce
losses, three main sources usually accountfor most ofthe
losses in LTC1266 series circuits: 1) LTC1266 DC bias
current, 2) MOSFET gate charge current and 3) 12R losses.
1. The DC supply current is the current which flows into
VIN (Pin 2). For VIN = 10V the LTC1266 DC supply
current is 170~ for no load, and increases proportionally with load up to aconstant 2.1 mA after the LTC1266
series has entered continuous mode. Because the DC
bias current is drawn from VIN, the resulting loss
increases with input voltage. For VIN = 5V the DC bias
losses are generally less than 1%for load currents over
30mA. However, at very low load currents the DC bias
current accounts for nearly all of the loss.

2. MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
apacket of charge dQ moves from PowerVIN to ground.
The resulting dQ/dt is a current flowing into Power VIN
(Pin 5) which is typically much larger than the DC
supply current. In continuous mode, IGATECHG = f (QN +
Qp). The typical gate charge for a 0.0511 N-channel

power MOSFET is 15nC. This results in IGATECHG = 6mA
in 200kHz continuous operation for a 2% to 3% typical
mid-current loss with VIN =5V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it argues against using larger MOSFETs than necessary to
control1 2Rlosses, since overkill can cost efficiency as
well as money!
3. 12R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continuous mode the average output current flows through L
and RSENSE, but is "chopped" between the topside and
bottom-side MOSFETs. If the two MOSFETs have approximately the same ROS(ON), then the resistance of
one MOSFET can simply be summed with the resis- . , .
tances of Land RSENSE to obtain 12R losses. For . .
example, if each ROS(ON) = 0.0511, RL = 0.0511 and
RSENSE = 0.0211, then the total resistance is 0.1211. This
results in losses ranging from 3.5% to 15% as the
output current increases from 1A to 5A. 12R losses
cause the efficiency to roll off at high output currents.
Figure 8 shows how the efficiency losses in a typical
LTC1266 series regulator end up being apportioned. The
gate charge loss is responsible for the majority of the
efficiency lost in the mid-current region. If Burst Mode
operation was not employed at low currents, the gate
charge loss alone would cause efficiency to drop to
100

80 '------'---'-------'----'------'
0.Q1

0.03

0.1
0.3
lour (A)

Figure 8. Efficiency Loss

4-241

LTC 1266
LTC1266-3.3/LTC1266-5
APPLICATions InFoRmATion
unacceptable levels (see Figure 7). With Burst Mode
operation, the DC supply current represents the lone (and
unavoidable) loss componentwhich continues to become
a higher percentage as output current is reduced. As
expected the 12Rlosses dominate at high load currents.
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, generally account for less than 2% total additional loss.

Design Example
As a design example, assume VIN = SV (nominal),
VOUT = 3.3V, IMAx = SA and f = 200kHz; RSENSE, CT and L
can immediately be calculated:
RSENSE = 100mV/S = 0.02n
tOFF = (1/200kHz) x [1 - (3.3/S)] = 1.7JlS
CT = 1. 7JlS/(1.3 x 104) = 130pF
LMIN = S.1 x10 5 x 0.02n x 130pF x 3.3V = SJlH
Assume that the MOSFET dissipations are to be limited to
PT= PB = 2W.
If TA= 40°C and the thermal resistance of each MOSFET
is SO°C/W, then the junction temperatures will be 140°C
and OT =OB =0.60. The required RDS(ON) for each MOSFET
can now be calculated:
S(2)
TS ROS(ON) = 3.3(S)2 (1.60) = 0.076n
S(2)
BS ROS(ON) = 1.7(S)2 (1.60) = 0.147n
The topside FET requirement can be met by an N-channel
Si9410DY which has an RDS(ON) of about 0.04n at
VGS = SV. The bottom-side FET requirement is exceeded
by an Si941 ODY. Note thatthe most stringent requirement
for the bottom-side MOSFET is with VOUT = 0 (Le., short
circuit). During a continuous short circuit, the worst-case
dissipation rises to:
PB = ISC(AVG)2 x RDS(ON) x (1 + 0B)
With the 0.02n sense resistor, ISC(AVG) '" 6A will result,
increasing the 0.04n bottom-side FET disSipation to 2.3W.

4-242

CIN will requirean RMS current rating of at least 2.SA at
temperature and COUT will require an ESR of 0.02n for
optimum efficiency.
Now allowVIN to dropto its minimum value. The minimum
VIN can be calculated from the maximum duty cycle and
voltage drop across the topside FET,
VMIN =

VOUT + ILOAD x (RDS(ON) + RL + RSENSE)
= 4.0V
DMAX

At this lower input voltage, the operating frequency decreases and the topside FET will be conducting most ofthe
time, causing the power dissipation to increase.
At dropout,
fMIN =

1
= 16kHz
tON (MAX) + tOFF

PT = 12LOAD x RDS(ON) x (1 + OT) x DMAX
This last step is necessary to assure that the power
dissipation and junction temperature of the topside FET
are not exceeded.

These last calculations assume that Power V/N is high
enough to keep the topside FEr fully turned on at dropout,
as would be the case with the Figure 11circuit.lfthis isn't
true (as with the Figure 1circuit) the ROS(ON) will increase
which in turn increases VMIN and Pr.

Adjustable Applications
When an output voltage other than 3.3V or SV is required,
the LTC1266 adjustable version is used with an external
resistive divider from VOUT to VFB, Pin 10. The regulated
voltage is determined by:
VOUT =1.2S (1 +

=~)

To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1266.
For Figure 1 applications with VOUT below 2V, or when
RSENSE is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, .the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor CT.

LTC 1266
LTC 1266-3.3/LTCl 266-5
APPLICATions InFoRmATion
Troubleshooting Hints
Since efficiency is critical to LTC1266 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor, Pin 6.
In continuous mode (I LOAD > IBURST) the voltage on the CT
pin should be a sawtooth with a O.9Vp_p swing. This
voltage should never dip below 2V as shown in Figure 9a.
When load currents are low (ILOAD < IBURST) Burst Mode
operation should occur with the CT pin waveform periodically falling to ground for periods of time as shown in
Figure 9b.

ov
(a) Continuous Mode Operation

(b) Burst Mode Operation

If Pin 6 is observed falling to ground at high output
currents, it indicates poordecoupling or improper grounding. Refer to the Board Layout Checklist.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation ofthe
LTC1266 series. These items are also illustrated graphically in the layout diagram of Figure 10. Check the following in your layout:
1. Are the signal and power grounds segregated? The
LTC1266 signal ground (Pin 12) must return to the
(-) plate of COUT. The power ground returns to the
source of the bottom-side MOSFET, anode of the
Schottky diode and (-) plate of CIN, which should
have as short lead lengths as possible.
2. Does the LTC1266 Sense- (Pin 8) connect to a point . .
close to RSENSE and the (+) plate of COUT? In adjust- . .
able applications, the resistive divider R1 and R2 must
be connected between the (+) plate of CouTand signal
ground.

Figure 9. CT Waveforms

r4~------~1----------------------------+
BOLD LINES INDICATE
HIGH CURRENT PATHS

VOUT

'-IH--":"+

Figure 10. LTC1266 Layout Diagram (See Layout Checklist)

4-243

LTC 1266

LTC 1266-3.3/LTCl 266-q
APPLICATions InFoRmATion
3. Are the Sense- and Sense+ leads routed together with
minimum PC trace spacing? The 1000pF capacitor
between Pins 8 and 9 should be as close as possible to
the LTC1266.
4. Does the (+) plate of CIN connect to the source of the
topside MOSFET as closely as possible? This capacitor
provides the AC current to the topside MOSFET.

times helpful in eliminating instabilities at high input
voltage and high output loads.
6. Is the Shutdown (Pin 11) actively pulled to ground
during normal operation? The Shutdown pin is high
impedance and must not be allowed to float. The Select
(Pins 3 and 4) are also high impedance and must be tied
high or low depending on the application.

5. A 0.1 ~ to 1~ decoupling capacitor connected between VIN (Pin 5) and ground is optional, but is some-

TYPICAL APPLICATiOnS (Layout Assist Schematics)
VIN
~3.9VTO 18V
(VIN(MIN) = 3.5V IF ILOAD < 0.8A)

01
MBRS140T3

BINH -t----....:.

L'
10J!H

1"
-

CT

Cc
220pF 'f:300PF
lk

COUT
220J!F
10V
2x

RSENSE
0.0330

• DALE LPT4545-AOOl
COILTRONICS CTX10-4

VOUT
3.3V
3A

Figure 11. Low Dropout, 3.3V/3A High Efficiency Regulator

4-244

LTC1266'Fl1

LTC1266
LTC1266-3.3/LTCl 266-5
TYPICAL APPLICATions

(Layout Assist Schematics)

COUT

100~F

20V

SINH

1"
-

CT
Cc
200pF ~C3300PF

tk

lN4l48

'--+-+__.....1-- SHUTDOWN

'DALE LPT4545-A002
COILTRONICS CTX20-4
"MMST2222ALTl

LTC1200°F12

Figure 12_ 5V to 12V/500mA High Efficiency Boost Regulator

VIN
4V TO PWR VIN -4.5V
(VIN(MIN) = 3.5V IF ILOAD < 2.5A)

PWRVIN
VIN + 4.5V TO l8V

-+-....----"-

SINH

-+-----'-

COUT

220~F

+

'COILTRONICS CTX02l280l

10V

2x

VOUT
' - - - - - - - - - - - - - -.....--_-3.3V
5A

Figure 13_ All N-Channel5V to 3_3V/5A Converter with Drivers Powered from External PWR VIN Supply

4-245

L1C I '2.66

LTC1266-3.3/LTCl 266-5
TYPICAL APPLICATions

(Layout Assist Schematics)
VIN
4VTO 9V

Si44100Y

47J.1F
10V
OS-CON
3x
01
MBRS340T3

Si44100Y

BINH-+---"";;:'

SHUTDOWN

T

L"
SJ.lH

CT

Cc
220pF fc3300PF

-

4700

COUT
330J.lF
10V
3x

RSENSE
0.010
VOUT
3.3V
lOA

"MAGNETICS Kool MJ.l77120-A7

LTC126l1·F14

Figure 14. All N-Channel5V to 3.3V/10A High Efficiency Regulator
VIN
4VTO 9V
(VIN(MIN) = 3.SV IF ILOAD < lA)

+

BINH

-+----.;:.
100pF

SHUTDOWN

RSENSE
0.020

lOOk
1%

lOOk
1%

+

COUT
330J.lF
10V
2x

VOUT
2.SV
SA

"COILTRONICS CTX0212801

Figure 15. All N-Channel5V to 2.5V/5A High Efficiency Regulator

4-246

lOOI'F
10V
OS-CON
2x

LTCl26f.1·F15

LTC 1266
LTC1266-3.3/LTCl 266-5
RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTCl142

Dual High Efficiency Synchronous Step-Down Switching Regulator

Dual Version of LTCl148

LTCl143
LTCl147

Dual High Efficiency Step-Down Switching Regulator Controller

Dual Version of LTCl147

High Efficiency Step-Down Switching Regulator Controller

Nonsynchronous, 8-Lead, VIN s l6V

LTCl148

High Efficiency Step-Down Switching Regulator Controller

Synchronous, VIN S 20V

LTCl149

High Efficiency Step-Down Switching Regulator

Synchronous, VIN S 48V, for Standard Threshold FETs

LTCl159

High Efficiency Synchronous Step-Down Switching Regulator

VIN S 40V, for Logic Level FETs

LTCl174

High Efficiency Step-Down and Inverting DC/DC Converter

O.5A Switch, VIN ::; l8.5V, Comparator

LTC1265

High Efficiency Step-Down DC/DC Converter

1.2A Switch, VIN S l3V, Comparator

LTC1267

Dual High Efficiency Synchronous Step-Down Switching Regulators

Dual Version of LTCl159

II

4-247

.J=AD
£.YLln
...
.. U

UCI261

\~~_LT_Cl_26_7-_AD....J/_LTC_12_67_~A_DJ_5
Dual High Efficiency
Synchronous Step-Down
Switching Regulators

. TECHNOLOGY

FEATURES

DESCRIPTiOn

• Dual Outputs: 3.3V and 5V, Two Adjustables or
Adjustable and 5V
• Wide VIN Range: 4V to 40V
• Ultra-High Efficiency: Up to 95%
• Low Supply Current in Shutdown: 20~
• Current Mode Operation for Excellent Line and Load
Transient Response
• High Efficiency Maintained Over a Wide Output
Current Range
• Independent Micropower Shutdown
• Very Low Dropout Operation: 100% Duty Cycle
• Synchronous FET Switching for High Efficiency
• Available in Standard 28-Pin SSOP

The LTC@1267 series are dual synchronous step-down
switching regulator controllers featuring automatic Burst
Mode™ operation to maintain high efficiencies at low
output currents. The LTC1267 is composed of two separate regulator blocks, each driving apair of external complementary power MOSFETs at switching frequencies up to
400kHz. The LTC1267 uses a constant off-time currentmode architecture to provide constant ripple current in the
inductor and provide excellent line and load transient
response.

APPLICATions
•
•
•
•

A separate pin and on-board switch allow the MOSFET
driver power to be derived from the regulated output
voltage, providing significant efficiency improvement when
operating at high input voltage. The output current level is
user-programmable via an external current sense resistor.
The LTC1267 series is ideal for applications requiring dual
output voltages with high conversion efficiencies over a
wide load current range in a small amount of board space.

Notebook and Palmtop Computers
Battery-Operated Digital Devices
Portable Instruments
DC Power Distribution Systems

D, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.

TYPICAL APPLICATiOn
VI.
5.4Vto 25V

RSENSE5

0.05<>

VOUT5

.......rrt~~. . . . . 5V

2A

COUTS

220~F

tOV
x2
RSENSE3: KRL SL-1R05OJ
L3: COILTRONICS CTX20-4

RSENSE5: KRL SL-t R050J
L5: COILTRONles CTX33-4
SHDN3, SHDN5, MSHDN
OV = NORMAL, >2V = SHDN

Figure 1. High Efficiency Dual 3.3V, 5V

4-248

LTC1267
LTC1267-ADJ/LTC1267-ADJ5
ABSOLUTE mAXimum RATinGS
Input Supply Voltage (Pin 2) ..................... -0.3V to 40V
Vee Output Current (Pin 1) .................................. 50mA
EXT Vee Input Voltage (Pin 28) .............................. 10V
Continuous Output Current (Pins 5, 6, 23, 24) .... 50mA
Sense Voltages
LTC1267 (Pins 13,14,17,18) ............. Vee to -0.3V
LTC1267-ADJ (Pins 12, 13, 17, 18) ..... Veeto-0.3V
LTC1267-ADJ5 (Pins 12,13,17,18) ... Vee to -0.3V
Shutdown Voltages
LTC1267 (Pins 12, 19, 27) ................................... 7V
LTC1267-ADJ (Pins 11,27) ................................. 7V
LTC1267-ADJ5 (Pins 11, 19,27) ......................... 7V
Operating Ambient Temperature Range ...... O°C to 70°C
Extended Commercial
Temperature Range ........................... -40°C to 85°C
Junction Temperature (Note 1) ............................ 125°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
TOP VIEW

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER
LTC1267CG

G PACKAGE
2HEAD PLASTIC SSOP
TJMAX =125°C. 6JA =95"C/W

ORDER PART
NUMBER

ORDER PART
NUMBER

LTC1267CG-ADJ

LTC1267CG-ADJ5

G PACKAGE
2HEAD PLASTIC SSOP

G PACKAGE
28-LEAD PLASTIC SSOP

TJMAX = 125°C. 6JA = 95°C/W

TJMAX = 125°C. 6JA = 95°C/W

~onsult factory for Industrial and Military grade parts.
rhe LTC1267 demo circuit board is now available. Consult factory.

4-249

LTC1267

LTC1267-ADJ/LTCl 267-ADJ5

ELECTRICAL CHARACTERISTICS
TA =25°C, VIN =12V, VMSHDN, VSHDN1,3,5 =OV (Note 2), unless othelWise noted.
SYMBOL

PARAMETER

CONDITIONS

VFB1,2

Feedback Voltage

LTC1267-ADJ, LTC1267-ADJ5: V,N =9V

IFB1,2

Feedback Current
Regulated Output Voltage
3.3V Output
5V Output
Output Voltage Line Regulation

LTC1267-ADJ, LTC1267-ADJ5

VOUT

,iVOUT

Vcc
V,N - Vcc
IEXlVCC
liN

Output Voltage Load Regulation
3.3V Output
5V Output

LTC1267: V,N = 9V,ILOAD = 700mA
LTC1267, LTC1267-ADJ5: V,N = 9V,ILOAD = 700mA
V,N = 9V to 40V
Figure 1 Circuit
5mA < ILOAD < 2.0A
5mA < ILOAD < 2.0A

Burst Mode Output Ripple
Internal Regulator Voltage

ILOAD = OA
V,N = 12V to 40V, EXT Vcc = OV, Icc = 10mA

Vcc Dropout Voltage

V,N = 4V, EXT Vcc = Open, Icc = 10mA
EXT Vcc = 5V, Sleep Mode

EXT Vcc Pin Current (Note 3)
V,N Pin Current (Note 3)
Normal
Shutdown

VEXTVCCVcc
VPGATEV,N

EXT Vcc Switch Drop
PGate to Source Voltage (Off)

VSENSE\2- Current Sense Threshold Voltage
VSENSE -1,2
VSENSE +3,5- Current Sense Threshold Voltage
VSENSE -3,5
VSHDN

V,N = 12V
V,N =40V
LTC1267-ADJ, LTC1267-ADJ5
VSENSE -1,2 = 5.1V, VFB1, 2= VOUT/4 + 25mV (Forced)
VSENSE -1,2 = 4.9V, VFB1, 2= VOUT/4 - 25mV (Forced)
LTC1267
VSENSE - 3,5 = VOUT + 100mV (Forced)
VSENSE - 3 5 = VOUT -1 OOmV (Forced)

IMSHDN
ICT

CT Pin Discharge Current

tOFF
tr,tf

Off-Time (Note 4)

VMSHDN = 5V
VOUT in Regulation
VOUT = OV
CT = 390pF, ILOAD = 700mA, V,N = 10V

Driver Output Transition Times

CL = 3000pF (PDrive and NGate Pins), V,N = BV

4-250

•
••

TYP
1.25

MAX
1.29

0.2

1

!lA

3.33
5.05
0

3.43
5.20
40

V
V
mV

40
60

65
100

50
4.5

mV
mV
mVp_p

4.75

200

300

V
mV

3.23
4.90
-40

••
•

4.25

V,N = 12V, EXT Vcc = 5V
V,N = 40V, EXT Vcc = 5V
V,N = 12V, VMSHDN = 2V
V,N = 40V, VMSHDN = 2V
V,N = 12V, EXT Vcc = 5V, ISWITCH = 10mA

Shutdown Threshold
MSHDN
SHDN1, 3, 5
MSHDN Input Current

•

MIN
1.21

•
•

UNITS
V

360

!lA

320
550
15
25
200

!lA
!lA
!lA
!lA
300

mV

-0.2
-0.2

0
0

135

25
160

180

mV
mV

135

25
160

180

mV
mV

0.8
O.B

1.4
0.8

2.0
2.0

V
V

12

20

50

70
2

90
10

!lA
!lA
!lA

4

V
V

5

6

100

200

IJS
ns

LTC1267
LTC1267-ADJ/LTC1267-ADJ5
ELECTRICAL CHARACTERISTICS
-40°C ~ TA ~ 85°C, VIN = 12V, VMSHDN, VSHDN1,3,5 = OV (Notes 2,5), unless otherwise noted.
SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VFB1,2

Feedback Voltage

LTC1267·ADJ, LTC1267-ADJ5: VIN =9V

1.2

1.25

1.3

V

VOUT

Regulated Output Voltage
3.3V Output
5V Output

VIN =9V
ILOAD =700mA
ILOAD =700mA

3.17
4.85

3.30
5.05

3.48
5.25

V
V

VIN Pin Current (Note 3)
Normal

liN

VIN =12V, EXT Vee =5V
VIN =40V, EXT Vee =5V
VIN =12V, VMSHDN =2V
VIN =40V, VMSHDN =2V
EXT Vee =5V, Sleep Mode

Shutdown
IEXTvee
Vee
VSENSE+ VSENSE

EXT Vee Pin Current (Note 3)
Internal Regulator Voltage
Current Sense Threshold Voltage

VMSHDN

Shutdown Threshold MSHDN

tOFF

Off-Time (Note 4)

VIN =12V to 40V, EXT Vee =OV, Icc =20mA
Low Threshold (Forced)
High Threshold (Forced)
CT =390pF, ILOAD =700mA, VIN =10V

The. denotes specifications which apply over the full operating
temperature range.
Note 1: TJ is calculated from the ambient temperature TA and power
dissipation Po according to the following formula:
LTC1267/LTC1267-ADJ/LTC1267ADJ5: TJ= TAt (Po x 95°C/W)
Note 2: On LTC1267 versions which have MSHDN and SHDN1, 3, 5 pins,
they must be at ground potential for testing.
Note 3: The LTC1267 VIN and EXT Vee current measurements exclude
MOSFET driver currents. When Vee power is derived from the output via
EXT Vee, the input current increases by (lGATEeHG x Duty Cycle)/Efficiency.
See Typical Performance Characteristics and Applications Information.

320
550
15
25

~
~
~
~
~

130

360
4.5
25
160

185

V
mV
mV

0.8

1.4

2.0

V

3

5

7

J.IS

Note 4: In applications where RSENSE is placed at ground potential, the
off-time increases approximately 40%.
Note 5: The LTC1267/LTC1267 ·ADJ/LTC1267-ADJ5 are not tested and
quality-assurance sampled at -40°C to 85°C. These specifications are
guaranteed by design and/or correlation.
Note 6: The logic level power MOSFETs shown in Figure 1 are rated for
VDS(MAX) = 30V. For operation at VIN > 30V, use standard threshold
MOSFETs with EXT Vee powered from a 9V supply. See applications
information.
Nole 7: LTC1267-ADJ and LTC1267-ADJ5 are tested at an output of 3.3V

TYPICAL PERFORmAnCE CHARACTERISTICS
5V Output Efficiency
vs Load Currenl
100

100

II

95

VIN =10V

3.3V Output Efficiency
vs Load Current

1-- ....

90

C

85

VIN =20V

15

80

~

75

u

C

85

15

80

tb

75

>u

u

/

70

/

70

65
60
0.01

60
0.01

0.1

1

10

20 I----N'r\-'\-+---+---+--J

V

l

r-.....

VIN =20V

'> 10 ~YH--\\~+­
~ 0 i'--\-,,,,,,p....:

"

~ -10
o
~ -20

I---+--"~"k""",

13 -30

/

V
65
LOAD CURRENT (A)

I

IIVI~ =10V

90

/

>-

u

IIIII

95

1"--,

Load Regulation
30 , - - - , - - , - - - . , - - - , - - ,

o
'" -40

-50 I---+--+---+---+---""-'l
0.1

1

10

LOAD CURRENT (A)

0.5

1.0

1.5

2.0

2.5

LOAD CURRENT
LTC1267·G02

4-251

LTC1267
LTC 1267-ADJ/LTC1267-ADJ5
TYPICAL PERFORmAnCE CHARAOERISTICS
5V Output Efficiency
vs Line Voltage

3.3V Output Efficiency
vs Line Voltage

Line Regulation

100 r---.---.----,---.--,--r;;777F=
95f-~...t;:----+

40 f--+-+-_j_-I--+-I5777f>m

90 f-+----P-~:"!"".....t---f7%f~

il
~

~ 201--t-+--+-~-+--f7~

85 f--+---f"oo.--+-...""k----"""~~~

~

~

ili 80

>

~ 75

!::; -201-4+-+--+--1--+-

C3

0

~

Sl

70

-40 1-4+-+--+--1--+-

65 f - t - + - - + TliRESIHOL

-60
5

10

15 20 25 30
INPUT VOLTAGE (V)

35

40

5

10

15 20 25 30
INPUT VOLTAGE (V)

35

40

'---LL--.L-....l..-.-L---'---.JLL.~"'"

o

5

10

15 20 25 30
INPUT VOLTAGE (V)

35

LTl267'G06

LTC1267'G05

Operating Frequency
vs (VIN - VOUT)

Off-Timevs Output Voltage

2.0 .-----r---,---,-----,---,
VOUT = 5V
ILOAD" 700mA

¥

O'C

>=" 1.5 1---+----b6"'q...--F7n.
ili
:::>

Current Sense Threshold Voltage

160

180

140

160
140

120

'-'

8
fE 1.0

I-------E,~_j_-t-_+---l

~

15

~ 80

~
~

0.5 I-I_+--+-_j_-+-----l

25

o

o

~

-

=

80

40

- -

MINIMUM THRESHOLD

-

I--

20

~

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)

o

o

10 20 30 40 50 60 70 80 90 100
TEMPERATURE ('C)
LTC1267·009

(Applies to both regulator sections)

VIN: Main Supply Input Pin.
EXT Vee: External Vee Supply for the Regulators. See EXT
Vee Pin Connection.
Vee: Output ofthe Internal4.5V Linear Regulator, EXT Vee
Switch, and Supply Inputs for Driver and Control Circuits.
The driver and control circuits are powered from the
higher of the 4.5V regulator or EXT Vee voltage. Must be
closely decoupled to the power ground.
PGND: Power Ground. Connectto the source of N-channel
MOSFET and the H terminal of CIN.

4-252

100

~

~

OUTPUT REGULATOR

LTCl261'F08

Pin FunCTions

M~IIJ;;;ESHOLD

w

I'\:

20
10
15
20
(VIN - VOUT) VOLTAGE (V)

- -

~ 60

\k'3.3V OUTPUT REGULATOR

40

~

:;

l\

60

z

5

~

'[ 120

~ 100

o

40

SGND: Small-Signal Ground. Must be routed separately
from other grounds to the (-) terminal of COUTo
PGATE: Level Shifted Gate Drive for the Top P-channel
MOSFET~ The voltage swing at the PGate pin is from VIN to
(VIN - Vee)·
PDRIVE: High Current Gate Drive forthe Top P-channel
MOSFET. The PDrive pin swings from Vee to GND.
NGATE: High Current Drive for the Bottom N-channel
MOSFET. The NGate pin swings from GND to Vee.

LTC1267
LTC1267-ADJ/LTCl 267-ADJ5
~In

FunCTions

~AP: Charge Compensation Pin. A capacitor to Vce profides charge required by the PGate level shift capacitor
juring supply transitions. The charge compensation caJacitor must be larger than the gate drive capacitor.
~T:

External Capacitor. From this pin to ground sets the
Jperating frequency. (The frequency is also dependent
JPon the ratio VouTIVIN).
TH : Gain Amplifier Decoupling Point. The regulator cur'ent comparator threshold increases with the ITH pin
foltage.
)ENSE- : Connects to internal resistive divider which sets
he output voltage. The Sense- pin is also the (-) input of
:he current comparator.

SENSE+: The (+) Input for the Current Comparator. A
built-in offset between the Sense+ and Sense- pins, in
conjunction with RSENSE, sets the current trip threshold.
VFB1, 2: These pins receive the feedback voltage from an
external resistive divider used to set the output voltage of
the adjustable section.

MSHDN: Master Shutdown Pin. Taking MSHDN high
shuts down Vee and all control circuitry.
SHDN1, 3, 5: These pins shut down the individual regulator control circuitry (Vee is not affected). Taking SHDN1 ,
3, 5 pins high turns off the control circuitry of adjustable
1, 3.3V, 5V sections and holds both MOSFETs off. Must be
at ground potential for normal operation.

•

FunCTionAL DIAGRAm
Internal divider broken at VFB1,2 for adjustable versions. Only one regulator block shown.)

MSHDN

EXT Vee

L7lJ[J~

4-253

LTC1267
LTC1267-ADJ/LTC1267-ADJ5
OPERATion

(Refer to Functional Diagram)

The LTC1267 series consists of two individual regulator
blocks each using current mode, constant off-time architectur~s to synchronously switch an external pair of
complementary power MOSFETs. The two regulators are
internally setto provide output voltages of 3.3V and 5V for
the LTC1267. The LTC1267-ADJ is configured to provide
two adjustable output voltages, each set by their individual external resistor dividers. The LTC1267 -ADJ5 has
adjustable and 5Voutput voltages. Operating frequen?y is
individually set on each section by the external capacitors
attached to the Cr pin.
The output voltage is sensed by an internal voltage divider
connected to the Sense- pin or external divider returned
to the VFB pin (LTC1267-ADJ, LTC1267-ADJ5). Avoltage
comparator V and a gain block G compare the divided
output voltage with a reference voltage of 1.25V. To
optimize efficiency, the LTC1267 series automatically
switches between two modes of operation, Burst Mode
and continuous mode. The voltage comparator is the
primary control element when the device is in Burst Mode
operation, while the gain block controls the output voltage
in continuous mode.
A low dropout 4.5V regulator provides the operating
voltage Vee for the MOSFET drivers and control circuitry
during start-up. During normal operation, the LTC1267
family powers the drivers and control from the outpu.t v!a
the EXT Vee pin to improve efficency. The NGate pm IS
referenced to ground and drives the N-channel MOSFET
gate directly. The P-channel gate drive must be referenced
to the main supply input VIN, which is accomplished by
level-shifting the PDrive signal via an internal 550k resistor and an external capaCitor.'
During the switch "ON" cycle in continuous mode, current
comparator C monitors the voltage between Sense+ and
Sense- pins connected across an external shunt in series
with the inductor. When the voltage across the shunt
reaches its threshold value, the PGate output is switched
to VIN, turning off the P-channel MOSFET. The timing
capaCitor Cr is now allowed to discharge at a rate determined by the off-time controller. The discharge current is
made proportional to the output voltage to model the
inductor current, which decays at a rate that is also

4-254

proportional to the output voltage. While the timing capacitor is discharging, the NGate output is high, turning
on the N-channel MOSFET.
When the voltage on the timing capacitor has discharged
past VTH1, comparator T trips, setting the flip-flop. This
causes the NGate output to go low (turning off the
N-channel MOSFET) and the PGate output to also go low
(turning the P-channel MOSFET back on). The cycle then
repeats. As the load current increases, the output volta~e
decreases slightly. This causes the output of the gam
stage to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode operation is very
similarto continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel
MOSFET is held off by comparator V and the timing
capacitor continues to discharge below VTH1. When the
timing capacitor discharges past VTH2, voltage comparator Strips, causing the internal SLEEP line to go low and
the N-channel MOSFET to turn off.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode a majority of the
cirCUitry is turned off, dropping the quiescent current
from several mA (with the MOSFETs switching) to 360~.
The load current is now being supplied by the output
capacitor. When the output voltage has dropped by the
amount of hysteresis in comparator V, the P-channel
MOSFET is again turned on and this process repeats.
To avoid the operation of the current loop interfering with
Burst Mode operation, abuilt-in offset Vas is incorporated
in the gain stage. This prevents the current comparator
threshold from increasing until the output voltage has
dropped below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the
NGate output can go high, the PDrive output must also be
high. Likewise, the PDrive output is prevented from going
low while the NGate output is high.

LTC1267
LTC 1267-AOJ/LTC1267-AOJ5
~PPLICATlons

InFORmATion

rhe LTC1267 Compared to the LTC1159, LTC1149 and
.TC1142 Family
rhe LTC1267 family is a dual LTC1159. Identical to the
.TC1159, the LTC1267 can reduce the quiescent and
;hutdown currents by making use of an internal switch
IVhich allows the driver and control sections to be
lowered from an external source to improve efficiency.
rhe basic LTC1267 application circuit shown in Figure
I is limited to a maximum input voltage of 30V due to
lxternal MOSFET breakdown. If the application does
lot require greater than 18Voperation the LTC1142HV
;hould be used.
:omponent Selection
rhe basic LTC1267 application circuit is shown in Figure
I. External component selection is driven by the load
equirement and begins with the selection of RSENSE.
)nce RSENSE is known, CT and L can be chosen. Next, the
lower MOSFETs and diode are selected. Finally, CIN and
:OUT are selected and the loop is compensated. Since the
Idjustable, 3.3V and 5V sections in the LTC1267 are
~entical, the process of component selection is the same
or both sections.
'SENSE Selection for Output Current

\SENSE is chosen based on the required output current.
'he LTC1267 current comparators have athreshold range
vhich extends from a minimum of 25mV/RsENSE to a
naximum of 150mVlRSENSE. The current comparator
hreshold sets the peak of the inductor ripple current,
'ielding amaximum output current IMAX equal to the peak
'alue less half the peak·to·peak ripple current. For proper
lurst Mode operation, IRIPPLE(P-P) must be less than or
!qual to the minimum current comparator threshold.
iince efficiency generally increases with ripple current,
he maximum allowable ripple current is assumed, i.e.,
~IPPLE(P-P) = 25mVlRsENSE (see CT and L Selection for
)perating Frequency). Solving for RSENSE and allowing a
~argin for variations in the LTC1267 and external compoient values yields:
100mV
RSENSE= -1MAX

The LTC1267 works well with values of RSENSE from
0.02n to 0.2n. Figure 2 shows the selection of RSENSE vs
maximum output current.
0.20

0.15

§:
~O.10
~

a:

\

\
1\
~

0.05

o
o

......

r-

-

-

1
3
MAXIMUM OUTPUT CURRENT (A)
LTCl2(;r·F02

Figure 2. Selecting RSENSE

The load current below which Burst Mode operation commences, IBURST and the peak short·circuit current ISG(PK) •
both track IMAX. Once RSENSE has been chosen, IBURSTand
ISG(PK) can be predicted from the following:
15mV
IBURST"" RSENSE
150mV
ISC(PK)= - RSENSE
The LTC1267 automatically extends tOFF during a short
circuit to allow sufficient time for the inductor current to
decay between switch cycles. The resulting ripple current
causes the average short-circuit current ISG(AVG) to be
reduced to approximately IMAX.
CT and L Selection for Operating Frequency
Each regulator section of the LTC1267 uses aconstant offtime architecture with tOFF determined by an external
timing capacitor CT. The value of CT is calculated from the
desired continuous mode operating frequency (fo):
C = 7.8 x 10-5 (1 _ VOUT)
T
fo
VIN
Agraph for selecting CTVS frequency including the effects
of input voltage is given in Figure 3.

4-255

LTC1267
LTC1267-ADJ/LTC1267-ADJ5
APPLICATions InFoRmATion
1400

value, but it is very dependent on inductance selected. As
inductance increases, core losses go down but copper 12R
losses increase. For additional information regarding inductor selection, please refer to the LTC1159 data sheet.

Vour= 5V
1200

1\

!L

~1000

'z"'

\.\VIN= 24V

;:!: 800

~

\\

'"~

VIN= 12V'\

5 600

;::

400

Power MOSFET and Diode Selection

~

""""" ~

200

o
o

50

100
150
FREQUENCY (kHz)

200

250

Figure 3. Timing Capacitor Value

As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency is given by:
fo:::: _1_ (1 _ VOUT)
tOFF
VIN
where:
tOFF:::: 1.3 x 104 x CT
Once the frequency has been set by CT, the inductor Lmust
be chosen to provide no more than 0.025V1RsENSE of
peak-to-peak inductor ripple current. This results in a
minimum required inductor value of:
LMIN:::: 5.1 x 105 x RSENSE x CT x VOUT
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor are
eased at the expense of efficiency. If too small an inductor
is used, the LTC1267 may not enter Burst Mode operation
and efficiency will be severely degraded at low currents.

Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy (MPP), or Kool MJl® cores. Actual
core loss is independent of core size for a fixed inductor
Kool M~ is a registered trademark of Magnetics, Inc.

4-256

Two external power MOSFETs must be selected for use
with each section of the LTC1267: a P-channel MOSFET
for the main switch, and an N-channel MOSFET for the
synchronous switch.
The peak-to-peak gate drive levels are set by the Vee
voltage on the LTC1267. This voltage is typically 4.5V
during start-up and 5Vto 7V during normal operation (see
EXT Vee Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most LTC1267 family
applications. The only exceptions are applications in
which EXT Vee is powered from an external supply greater
than 8V, in which standard threshold MOSFETs (VGS(TH)
> 4V) may be used. Pay close attention to the BVoss
specification for the MOSFETs as well; many of the logiclevel MOSFETs are limited to 30V.
Selection criteria for the power MOSFETs include the onresistance ROS(ON), reverse transfer capaCitance CRSS,
input voltage, and maximum output current. When the
LTC1267 is operating in continuous mode, the duty cycles
for the two MOSFETs are given by:
Duty Cycle:::: VOUT
VIN
N-Channel Duty Cycle == VIN - VOUT
VIN
The MOSFET dissipations at maximum output current are
given by:
P-Ch Po:::: VVOUT (lMAX)2 (1 + 8p) ROS(ON)
IN
+ k (VIN)2 (IMAX) (CRSS) fo
N-Ch Po:::: VIN ~ VOUT (lMAX)2 (1 + 8N) ROS(ON)
IN

LTC1267
LTC1267-ADJ/LTCl 267-ADJ5
IPPLICATlons InFORmATion
Vhere 3 is the temperature dependency of ROS(ON) and k
; a constant inversely related to the gate drive current.
:oth MOSFETs have 12R losses, while the P-channel
quation includes an additional term for transition losses,
Ihich are highestat high input voltages. ForVIN <20V, the
igh current efficiency generally improves with larger
mSFETs, while forVIN >20V, the transition losses rapidly
lcrease to the pointthatthe use of ahigher ROS(ON) device
lith lower CRSS actually provides higher efficiency. The
I-channel MOSFET losses are the greatest at high input
oltage or during a short circuit when the N-channel duty
ycle is nearly 100%.
he term (1 + 0) is generally given for a MOSFET in the
lrm of a normalized ROS(ON) vs temperature curve, but 0
O.OO7/°C can be used as an approximation for low
oltage MOSFETs. CRSS is usually specified inthe MOSFET
lectrical characteristics. The constant k =5 can be used
lr the LTC1267 to estimate the relative contributions of
Ie two terms in the P-channel dissipation equation.
he Schottky diodes 03 and 05 shown in Figure 1 only
onduct during the dead-time between the conduction of
Ie respective power MOSFETs. The sole purpose of 03
nd 05 is to prevent the body diode of the N-channel
IOSFETfrom turning on and storing charge during the
ead-time, which could cost as much as 1% in efficiency
IIthough there are no other harmful effects if 03 and 05
re omitted). Therefore, 03 and 05 should be selected for
forward voltage of less than 0.6V when conducting IMAX.
IN

and

COUT Selection

1continuous mode, the source current of the

P-channel
IOSFET is a square wave of duty cycle VouTIVIN. To
revent large voltage transients, a low ESR input capaciIrsized forthe maximum RMS current must be used. The
laximum RMS capacitor current is given by:
[V (V - V )]1/2
OUT It OUT
IN
his formula has a maximum at VIN =2VOUT where IRMS =
IUT/2. This simple worst-case condition is commonly
sed for design because even significant deviations do not
[fer much relief. Note that capacitor manufacturer's
pple current ratings are often based on only 2000 hours
CIN Required IRMS '" IMAX

L71'!J~

of life. This makes it advisable to further derate the
capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question. An additional 0.1 Wceramic capacitor is also
required on VIN for high frequency decoupling.
The selection of COUT is driven by the required Effective
Series Resistance (ESR). The ESR of GOUT must be less
than twice the value of RSENSE for proper operation of the
LTG 1267:
GOUT Required ESR < 2RsENSE
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RsENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RsENSE, the voltage ripple on the output capacitor
will prematurely trigger Burst Modeoperation, resulting in •
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon, United Chemicon, and
Sprague should be considered for high performance capacitors. In surface mount applications multiple capacitors may have to be paralleled to meet the capacitance,
ESR, or RMS current handling requirements of the application. For additional information regarding capacitor
selection, please refer to the LTC1159 data sheet.
At low supply voltages, a minimum capacitance at GOUT is
needed to prevent an abnormal low frequency operating
mode (see Figure 4). When GOUT is made too small, the
output ripple at low frequencies will be large enough to trip

r;:: 800 t-t-----t-----t---f"'oo<;I:---t-t-----t---t---1

-"
w
<.>

~ 600 t-t-----t-~__+_t-t-t-~:-t-i

~

C3
~

13

400 t-t-t-~d__t-+~-+--t----i

o 200

I-t-+-+-+-t-+-t-=""k;:+--I

O~-L~~~-L~~

o

1

2

3

4

(VIN - VouTI VOLTAGE (VI
LTC1267·f04

Figure 4. Minimum Suggested COUT

4-257

LTC1267
LTC1267-ADJ/LTC1267-ADJ5
APPLICATions InFoRmATion
the voltage comparator. This causes· Burst Mode operation to be activated when the LTC1267 would normally be
in continuous operation. The effect is most pronounced
with low values of RSENSE and can be improved byoperating at higher frequencies with lower values of L. The
output remains in regulation at all times.

~--f'--+---.+

1N4148
,±,CIN . . . - -......- 4 .

-rem

EXT Vcc Pin Connection
The LTC1267 contains an internal PNP switch connected
between the EXT Vee and Vee pins. The switch closes and
supplies the Vee power whenever the EXT Vee pin is higher
in voltage than the 4.5V internal regulator. This allows the
MOSFET driver and control power to be derived from the
output during normal operation and from the internal
regulator when the output is out of regulation (start-up,
short circuit).
Significant efficiency gain can be realized by powering Vee
from the output, since the VIN current resulting from the
driver and control currents will be scaled by a factor of
Duty Cycle/Efficiency. For LTC1267, LTC1267-ADJ or
LTC1267 -ADJ5 this Simply means connecting the EXT
Vee pin directly to VOUT of the 5V regulator.
The following list summarizes the four possible connections for EXT Vee:
1. EXT Vee left open. This will cause Vee to be powered
only from the internal 4.5V regulator, resulting in reduced MOSFET gate drive levels and an efficiency
penalty of up to 10% at high input voltages.
2. EXT Vee connected directly to highest VOUT of the two
regulators. This is the normal connection for LTC1267/
LTC1267-ADJ/LTC1267-ADJ5 and provides the highest efficiency.
3. EXT Vee connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXT Vee
to an output-derived voltage which has been boosted to
greater than 4.5V. This can be done either with the
inductive boost winding shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics and
generally provides the highest efficiency atthe expense
of a Slightly higher parts count.

4-258

LTCl267-F05A

":'

Figure 5a. Inductive Boost Circuit lor EXT Vee

Figure 5b. Capacitive Charge Pump lor EXT Vee

4. EXT Vee connected to an external supply. If an external
supply is available in the 5Vto 10Vrange it may be used
to power EXT Vee providing it is compatible with the
MOSFET gate drive requirements. When driving standard threshold MOSFETs, the external supply must
always be present during operation to prevent MOSFET
failure due to insufficient gate drive.
Under the condition that EXT Vee is connected to VOUT1
which is greater than 5.5V, to power down the whole
regulator, both the pins MSHDN and SHDN1 have to be
pulled high. If SHDN1 is left floating or grounded the
EXT Vee may self-power froin VOUT1, preventing complete shutdown.
LTC1267 Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1267-ADJ and LTC1267-ADJ5 adjustable versions are used with an external resistive divider from VOUT
to the VFB1, 2 pins. This is shown in Figure 6. The regulated
voltage is determined by:
VOUT = (1 +

~~) 1.25V

LTC1267
LTC1267-ADJ/LTCl 267-ADJ5
APPLICATions InFoRmATion
The VFB1, 2 pin is extremely sensitive to pickup from the
inductor switching node. Care should be taken to isolate
the feedback network from the inductor and a 100pF
capacitor should be connected between the VFB1 2 and
SGND pins next to the package.
'
The circuit in Figure 6 cannot be used to regulate a VOUT
which is greater than the maximum voltage allowed on the
LTC1267 EXT Vee pin (10V). In applications with
VOUT> 10V, RSENSE must be moved to the ground side of
the output capacitor and load. This operates the current
sense comparator at OV common mode, increasing the
off-time approximately 40% and requiring the use of a
smaller timing capacitor CT.
RSENSE

VfBl,2 -~-_~w.,.~- VOUT
COUT

SGND

----+------t
-=-

LTC1267-F06

Figure 6. LTC1267-ADJ/LTC1267-ADJ5
External Feedback Network

Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
% Efficiency = 100% - (L1 + L2 + L3 + ... )
where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits, only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1267 circuits:
1.
2.
3.
4.

LTC1267 VIN current
LTC1267 Vee current
12R losses
P-channel transition losses

1. LTC1267 VIN current is the DC supply current given in
the electrical characteristics which excludes MOSFET
driver and control currents. VIN currents results in a
small «1%) loss which increases with VIN.
2. LTC1267 Vee current is the sum of the MOSFET driver
and control circuits currents. The MOSFET driver current results from switching the gate capacitance of the
power MOSFETs. Each time aMOSFET gate is switched
from low to high to low again, a packet of charge dO
moves from Vee to ground. The resulting dQJdt is a
current out of Vee which is typically much larger than
the control circuit current. In continuous mode IGATEeHG
"" fo(Op +ON}, where Op and ON are the gate charges of
the two MOSFETs.
By powering EXT Vee from an output-derived source,
the additional VIN current resulting from the driver and
control currents will be scaled by afactor of Duty Cycle/ . , .
Efficiency. For example, in a 20V to 5V application, . .
10mA of Vee current results in approximately 3mA of
VIN current. This reduces the mid-current loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. 12R losses are easily predicted from the DC resistances
ofthe MOSFET, inductor, and current shunt. In continuous mode all the output current flows through Land
RSENSE, but is "chopped" between the P-channel and Nchannel MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of
Land RSENSE to obtain 12R losses. For example, if each
RDS(ON) = 0.1 n, RL = 0.15n, and RSENSE = 0.05n, then
the total resistance is 0.3n. This results in losses
ranging from 3% to 12% as the output current increases
from 0.5A to 2A. 12R losses cause the efficiency to roll
off at high output currents.
4. Transition losses apply only to the P-channel MOSFET
and only when operating athigh input voltages (typically
20V or greater). Transition losses can be estimated
from:
Transition Loss"" 5 x VIN 2x IMAX x CRSS x fo
Other losses including CIN and COUT ESR dissipative
losses, Schottky conduction losses during dead-time,

4-259

LTC1267
LTCl 267-ADJ/LTCl 267-ADJ5
APPLICATions InFoRmATion
and inductor core losses, generally account for less
than 2% total additional loss.

Auxiliary Windings-Suppressing Burst Mode
Operation
The LTC1267 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.
Burst Mode operation can be suppressed at low output
currents with asimple external network which cancels the
25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from
certain types of inductors in high current (lOUT> 5A)
applications when they are lightly loaded.
An external offset is put in series with the Sense- pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 7. Two 100n resistors are
inserted in series with the sense leads from the sense
resistor.
RSENSE

Figure 7. Suppressing Burst Mode Operation

With the addition of R3 acurrent is generated through R1
causing an offset of:
VOFFSET = VOUT (R1 ~1 R3)
IfVOFFSET> 25mV, the built-in offset will be cancelled and
Burst Mode operation is prevented from occurring. Since
VOFFSET is constant, the maximum load current is also
decreased by the same offset. Thus, to get back to the
same IMAX, the value of the sense resistor must be
reduced:

4-260

RSENSE "" _751 mn
MAX

To prevent noise spikes from erroneously tripping the
current comparator, a 1OOOpF capaCitor is needed across
Sense+ and Sense- pins.

Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1267. These items are also illustrated graphically in
the layout diagram of Figure 8. In general each block
should be self-contained with little cross coupling for best
performance. Check the following in your layout:
1. Are the signal and power grounds segregated? The
LTC1267 Signal ground must return to the (-) plate of
COUT. The power ground returns to the source of the
N-channel MOSFET, anode of the Schottky diode,
and (-) plate of CIN, which should have as short lead
lengths as possible.
2. Does the LTC1267 Sense - pin connectto a point close
to RSENSE and the (+) plate of COUT? In adjustable
applications the resistive divider R1 and R2 must be
connected between the (+) plate of COUT and signal
ground.
3. Are the Sense - and Sense +leads routed together with'
minimum PC trace spacing? The 1000pF capacitor
between the two Sense pins should be as close as
possible to the LTC1267. Up to 100n may be placed in
series with each Sense lead to help decouple the Sense
pins. However, when these resistors are used the
capacitor should be no larger than 1000pF.
4. Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? An additional 0.1 J.IF ceramic capaCitor between VIN and power
ground may be required in some applications.
5. Is the Vee decoupling capaCitor connected closely
between the Vee pins of the LTC1267 and power
ground? This capacitor carries the MOSFETdriver peak
currents.

LTC1267
LTC1267-ADJ/LTC1267-ADJ5
APPLICATions InFoRmATion

D5
L5
L3

RSENSE5

...:.:....-+--t--+---4t-------4- VOUT5
BOLD LINES INDICATE HIGH CURRENT PATHS

I--JllV't.-....I

LTC1267-f08

Yours

Figure 8. LTC1267 Layout Diagram

6. In adjustable versions, the feedback pin is very sensitive to pickup from the switch node. Care must be taken
to isolate VFB1 2 from possible capacitive coupling of
the inductor switch signal.
7. Are MSHDN and SHDN1, 3, 5 actively pulled to ground
during normal operation? These shutdown pins are
high impedance and must not be allowed to float.

If the CT is observed falling to ground at high output
currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.
Inductor current should also be monitored. Look to verify
that the peak-to-peak ripple current in continuous mode
operation is approximately the same as in Burst Mode
operation.

Troubleshooting Hints
Since efficiency is critical to LTC1267 applications, it is
{ery important to verify that the circuit is functioning
~orrectly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the CT pin.
In continuous mode (ILOAD > IBURST) the voltage on the CT
oin should be a sawtooth with a O.9Vp_p swing. This
{oltage should never dip below 2V as shown in Figure 9a.

ov
(a) CONTINUOUS MODE OPERATION

(b) Burst Mode OPERATION

LTC1267·F09

Figure 9. CT Waveforms

Nhen load currents are low (lLOAD < IBURST) Burst Mode
Jperation occurs. The voltage on the CT pin now falls to
Jround for periods of time as shown in Figure 9b .

.L7lJ!l~

4-261

UL,ILO/

LTC1267-ADJ/LTC1267-ADJ5
TYPICAL APPLICATions
LTC1267-ADJ Dual Regulator with 3.6V/2.5A and 5V/2A Outputs
VIN
5.4Vto 25V

CINl

--r- 100fLF
...1.. 50V

RSENSEl
0.04Q
VOUT1
3.6V _>-'IJV\,-~'Y"I'Y""""'"
2.5A

COUT1
220l1F
10V

COUT2
220l1F
10V

R2
100k
1%

x2

x2

R1
52.3k
1%
RSENSEl' KRL SL·1 R040J
L1: COILTRONICS CTX20-4

MSHDN. SHDN1
OV =NORMAL. >2V =SHDN

RSENSE2: KRL SL-1R050J
L2: COILTRONICS CTX33-4

LTC1267-ADJ5 Dual Regulator with 3.45V/2.5A and 5V/2A Outputs
VIN
5.4Vto 25V
CINl

--r- 100l1F
...1.. 50V

VOUT1
3.45V _~I/Ir~"""'f'V"~"""
2.5A

COUT2
220l1F
10V

COUT1
220l1F
10V

x2

x2

RSENSEl' KRL SL-1 R040J
L1: COILTRONICS CTX20-4

4-262

RSENSE2: KRL SL-1 R050J
L2: COILTRONICS CTX33-4

LTC1267
LTC1267-ADJ/LTC1267-ADJ5
~ElATED

PARTS

IARTNUMBER

DESCRIPTION

COMMENTS

.TCl142

Dual Step-Down Switching Regulator Controller

Dual Version of LTCl148

.TCl143

Dual Step-Down Switching Regulator Controller

Dual Version of LTCl147

.TCl147

Step-Down Switching Regulator Controller

Nonsynchronous, 8-Pin, VIN ~ 16V

.TC1148

Step-Down Switching Regulator Controller

Synchronous, VIN

.TCl149

Step-Down Switching Regulator Controller

Synchronous, VIN ~ 48V, for Standard Threshold FETs

.TCl159

Step·Down Switching Regulator Controller

Synchronous, VIN ~ 40V, for Logic Level FETs

.TCl174

Step·Down Switching Regulator with Internal O.5A Switch

VIN ~ 18.5V, Comparator/Low Battery Detector

.TC1265

Step-Down Switching Regulator with InternallA Switch

VIN ~ 13V, Comparator/Low Battery Detector

.TC1266

Step-Up/Down Switching Regulator Controller

Synchronous N- or P-Channel FETs, Comparator/Low Battery Detector

.TC1574

Step-Down Switching Regulator with Internal O.SA Switch
and Schottky Diode

VIN ~ 18.SV, Comparator

L7lJD~

~

20V

4-263

~7~JDmG~~~--___L:_Jl_~_~~_~_~p_l~-~-2e--~
High Output Current
Step-Up Adjustable and
Fixed 5V DC/DC Converters
FEATURES

DESCRIPTion

•
•
•
•
•
•

The L"J'"I1302fLT1302-5 are micropower step-up DCfDC
converters that maintain high efficiency over a wide
range of output current. They operate from a supply
voltage as low as 2V and feature automatic shifting
between Burst Mode operation at light load, and current
mode operation at heavy load.

5V at 600mA or 12V at 120mA from 2-Cell Supply
200~ Quiescent Current
Logic Controlled Shutdown to 15J.IA
Low VCESATSwitch: 31 OmV at 2A Typical
Burst Mode™ Operation at Light Load
Current Mode Operation for Excellent
Line and Load Transient Response
• Available in 8-Lead SO or PDIP
• Operates with Supply Voltage as Low as 2V

APPLICATions
•
•
•
•
•

Notebook and Palmtop Computers
Portable Instruments
Personal Digital Assistants
Cellular Telephones
Flash Memory

The internal low loss NPN power switch can handle
current in excess of 2A and switch at frequencies up to
400kHz. Quiescent current is just 2001JA and can be
further reduced to 15J.IA in shutdown.
Available in 8-pin PDIP or 8-pin SO packaging, the LT1302f
LT1302-5 have the highest switch current rating of any
similarly packaged switching regulators presently on the
market.
D. LTC and LT are registered trademarks of Unear Technology Corporation.
Burst Mode is a trademark of Unear Technology Corporation.

TYPICAL APPLICATiOn
2-Celllo 5V Converter Efficiency
90
111111

88
86 I-2 CELLS

Cl
100j!F

~

>Cj

iD
u

~

84
82
80
78
76

I

/1
'J

74
OUTPUT
5V _ _. . -_ _ _ _ _ _ _ _ _ _----1
600mA

1
Cl =C2 =SANYO OS·CON
Ll = COILTRONICS CTX10·3
COILCRAFT D03316-103

Dl

=MOTOROLA MBRSI30LT3

Figure 1. 2-Celllo 5V/600mA DC/DC Converter

4-264

72
70
10
100
LOAD CURRENT (mA)

1000

LT1302/LTl302-5
IBSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

Voltage .... ........ ......... ..... ........... ............. ... .... .... 10V
WVoltage ............................. ... ... ... .......... ... ... ....... 25V
3 Voltage ....... .... .............. ..... ......... ...... .... ... ... ....... 10V
HDN Voltage ......................................................... 10V
c Voltage ................................................................ 4V
Voltage .................................................................. 4V
laximum Power Dissipation ............................ 700mW
perating Temperature Range .................... O°C to 70°C
torage Temperature Range ............... - 65°C to 150°C
~ad Temperature (Soldering, 10 sec) ................. 300°C
IN

TOP VIEW

ORDER PART
NUMBER

'"'0"""

VC 2
SHDN 3
(SENSE')fB 4

7

6

5

sw
VIN
IT

SB PACKAGE
NB PACKAGE
HEAD PDIP
HEAD PLASTIC SO
"fiXED VERSION
PINS 1AND BARE INTERNALLY
CONNECTED IN SOIC PACKAGE
TJMAX = 125'C. 9JA = 100'CIW (N8)
TJMAX = 125'C, 9JA = 80'CIW (S8)

LT1302CN8
LT1302CS8
LT1302CN8-5
LT1302CS8-5
S8 PART MARKING
1302
13025

Consult factory for Industrial and Military grade parts.

~C

ELECTRICAL CHARACTERISTICS

'MBOL

~

B

IS

:
~

:F
ESAT

PARAMETER
Quiescent Current

=25°C, VIN =2.5V, unless otherwise noted.

Input Voltage Range
Feedback Voltage (LT1302)
Feedback Pin Bias Current (LT1302)
Output Sense Voltage (LT1302-5)
Output Ripple Voltage (LT1302-5)
Sense Pin Resistance to Ground (LT1302-5)
Offset Voltage
Comparator Hysteresis
Oscillator Frequency
Maximum Duty Cycle
Switch On Time
Switch Off Time
Output Line Regulation
Switch Saturation Voltage
Switch Leakage Current
Switch Current Limit

HDNH
HDNL
ION

TA

CONDITIONS
VSHDN = 0.5V, VFB = 1.3V
VSHDN = 1.8V

Error Amplifier Voltage Gain
Shutdown Pin High
Shutdown Pin Low
Shutdown Pin Bias Current

Vc = OAV
VFB = 1V
Vc = OAV
Vc = OAV
See Block Diagram
(Note 1)
Current Limit Not Asserted (Note 2)

MIN

••
•
•
•
•

2.0
2.2
1.22
4.85

175
160
75

Current Limit Not Asserted
2 < VIN < 8V
Isw=2A
Vsw = 5V, Switch Off
Vc = OAV (Burst Mode Operation)
Vc = 1.25V (Full Power) (Note 3)
0.9V $ Vc $1.2V, AVr/AVFB

VSHDN = 5V
VSHDN = 2V
VSHDN = OV

IT Pin Resistance to Ground
e • denotes specifications which apply over the O°C to 70°C
nperature range.
te1: Hysteresis is specified at DC. Output ripple depends on capacitor
e and ESR.

•
•
•
•
•
•
•
•

2.0
50
1.8

TYP
200
15

1.24
100
5.05
50
420
15
5
220
86
3.9
0.7
0.06
310
0.1
1
2.8
75

8
3
0.1
3.9

MAX
300
25
8
1.26
5.25

265
310
95

0.15
400
475
10
3.9

0.5
20
1

UNITS
~
~

V
V
V
nA
V
mV
kn
mV
mV
kHz
kHZ
%
lIS
lIS

%N
mV
mV
~

A
A
V/V
V
V
~
~

~
kn

Note 2: The LT1302 operates in a variable frequency mode. Switching
frequency depends on load inductance and operating conditions and may
be above specified limits.
Note 3: Minimum switch current 100% tested. Maximum switch current
guaranteed by design.

4-265

LT1302/LTl302-5
TYPICAL PERFORmAnCE CHARACTERISTICS
No-Load Quiescent Current
Circuit of Figure 1
600

_ 400 r-----1--t--+--+---t---I

500

!Z

400

TA = 25 0

1350f-~--+--t--r----1--1
~300

r-----1--t--+--+---t---I

~ 250

1'"""'-I--+-0+-+-+--1

a:

t!l

Switch Saturation Voltage

Switch Saturation Voltage

500 ,---,---r--r--,--,---.
450 _TA=k5°C-+_+_+_+-------l

400

b

/

300

~
1501---1---+--+-+-+---1
:::J
a 100r-----1--t--+--+---t---I

100

V

300

i:3

--

V

~ 250
z
o
;:::
~ 200

/

200 1---1---+--+-+-+---1
200

~

V

~

j

~

/V

ISW~2A

350

~ 150

50r-----1--t--+--+---t---I
OL-~--L-~-L-~-~

2.0

2.5

3.0
3.5
4.0
SUPPLY VOLTAGE (V)

4.5

100
-50

1
3
SWITCH CURRENT (A)

5.0

-25

0
25
50
TEMPERATURE (OC)

75

10'

1302001

LT1302 Feedback Voltage

Quiescent Current

LT1302-5 Sense Pin Resistance

1.250

300

600

1.245
1.240

~

§1.235

'"i:!: 1.230 V

--

500

.........

~

~

~

400

fa

300

'"~

~ 1.225

~

'"~ 1.220
c
t!! 1.215

.......V

f--

1!Z 200

~

~
a:

a 150

-

V

-

ffi

~ 200

ff3

t!l

1.210

VIN ;2.5V I
250 f- SWITCH OFF

""....,

,.....-

100

~
50

100

1.205
1.200
-50

-25

0
25
50
TEMPERATURE (OC)

75

o

100

-50

-25

0
25
50
TEMPERATURE (OC)

75

1302004

Error Amplifier Offset Voltage

LT1302-5 Output Voltage
5.075

.§. 20

w

c
>

tt0

10

.......V

t;;

V

.......

",.........

...--

~

~ 5.025

i:!:

~ 5.000

-50

-25

0
25
50
TEMPERATURE (OC)

75

100

1302G07

4-266

10

/"

/

~

-

4.5

r--.....

]; 4.0

~ 3.5

;:;:

~ 4.975
0

75

Maximum On-Time

z
o

/'

".",

--..... r--.....

I'

'"

3.0

4.950

2.5

4.925

o

0
25
50
TEMPERATURE (OC)

5.0

_5.050

$'

-25

1302006

5.100

25

15

-50

""'''''

30

'"i:3

o

100

4.900
-50

-25

0
25
50
TEMPERATURE (OC)

75

100

2.0
-50

-25

0
25
50
TEMPERATURE (OC)

75

10

LTl302/LT1302-5
rYPICAL PERFORmAnCE CHARACTERISTICS
Maximum Duly Cycle
300

/~

70

20

275

90

80

Shutdown Pin Bias Current

Oscillator Frequency

100

~ 250

V

225

:::>

S

s: 200

I-- V

V

v

18 f16

T~L 25°~

:i 14
!iii
1l!
cr

/

./

12
./

[5 10
z
~ 8

~

6

'"

4

/
/

:J:

60

50
-50

-

>

15

/"'"

_

175

-25

0
25
50
TEMPERATURE (OC)

75

150
-50

100

-25

0
25
50
TEMPERATURE (OC)

75

LT1302-5 Output Voltage vs
Load Current

o

100

/

012345678
SHUTDOWN VOLTAGE (V)

Maximum Output Power·
Boost Mode

5.2 0

20

5.1 5
16

~ 5.1 0
w

~ 5.0 5
~

5.00

VIN=4V

!::;

~ 4.95 - '--VIN = 2.2V-

o

=

VIN=3V= t--

/'

/

4.90

/

V

V

4.8 5
4.80

o

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
1302G13

o

o

10
INPUT VOLTAGE (V)

• APPROXIMATE

1302G14

.In FUnCTiOnS
iND (Pin 1): Signal Ground. Feedback resistor and 0.1 W
:eramic bypass capacitor from VIN should be connected
lirectly to this pin.
'c (Pin 2): Frequency Compensation Pin. Connect series
IC to GND. Keep trace short.
•HDN (Pin 3): Shutdown. Pull high to effect shutdown; tie
o ground for normal operation.
:B/Sense (Pin 4): Feedback/Sense. On the LT1302 this
lin connects to CMP1 input. On the LT1302-5 this pin
onnects to the output resistor string.

L7lJ!]~

IT (Pin 5): Normally left floating. Addition of a3.3k resistor
to GND forces the LT1302 into current mode at light loads.
Efficiency drops at light load but increases at medium
loads. See Applications Information section.
VIN (Pin 6): Supply Pin. Must be bypassed with: (1) a0.1 W
ceramicto GND, and (2) alarge value electrolytic to PGND .
When VIN is greater than 5V, a low value resistor (2Q to
10Q) is recommended to isolate the VIN pin from input
supply noise.

4-267

LTl302/LTl302-5

Pin FunCTions
SW (Pin 7): Switch Pin. Connect inductor and diode here.
Keep layout short and direct.
PGND (Pin 8): Power Ground. Pins 8 and 1 should be
connected under the package. In the SO package, pins 1

and 8 are thermally connected to the die. One square inch
of PCB copper provides an adequate heat sink for the
device.

BLOCK DIAGRAmS
L1

V I N - H r - - - - - - - - - - -........-----...r1rT"f-,.....------..,...~~-VOUT

R3
22k
C4
~ O.01I'F

Figure 2. LT1302 Block Diagram

4-268

.L7lJ!J~

LTl302/LT1302-5
ILOCK DIAGRAmS
SENSE

SW

VIN

r---------------~6~------------------------~

SHDN 3 1 - - - + _
3000

GND

Vc

3.6k

PGND

Figure 3. LT1302-5 Block Diagram

)PERATlon
he LT1302's operation can best be understood by
xamining the block diagram in Figure 2. The LT1302
perates in one of two modes, depending on load. With
ght loads, comparator CMP1 controls the output; with
eavy loads, control is passed to error amplifier A1.
urst Mode operation consists of monitoring the FB pin
oltage with hysteretic comparator CMP1. When the FB
oltage, related to the output voltage by external attenutor R1 and R2, falls below the 1.24V reference voltage,
1e oscillator is enabled. Switch 04 alternately turns on,
ausing current buildup in inductor L1, then turns off,
lIowing the built-up current to flow into output capaciH C3 via D1. Asthe output voltage increases, so does
1e FB voltage; when it exceeds the reference plus

L7lJD~

CMP1's hysteresis (about SmV) CMP1 turns the oscillator off. In this mode, peak switch current is limited to
approximately 1A by A2, 02, and 03. 02's current, set at
34~, flows through RS, causing A2's negative input to
be 2SmV lower than VIN. This node must fall more than
36mV below VIN for A2 to trip and turn off the oscillator.
The remaining 11 mV is generated by 03's current flowing through R4. Emitter-area scaling sets 03's collector
current to 0.62S% of switch 04's current. When 04's
current is 1A, 03's current is 6.2SmA, creating an 11 mV
drop across R4 which, added to RS's 2SmV drop, is
enough to trip A2.
When the output load is increased to the point where the
1A peak current cannot support the output voltage,

4-269

LTl302/LT1302-5
OPERATion
CMP1 stays on and the peak switch current is regulated
by the voltage on the Vc pin (A1 's output). Vc drives the
base of Q1. As the Vc voltage rises, Q2 conducts less
current, resulting in less drop across R5. Q4's peak
current must then increase in order for A2 to trip. This
current mode control results in good stability and immunity to input voltage variations. Because this is a linear,

closed-loop system, frequency compensation is required.
A series RC from Vc to ground provides the necessary
pole-zero combination.
The LT1302-5 incorporates feedback resistors R1 and
R2 into the device. Output voltage is set at 5.05V in Burst
Mode, dropping to 4.97V in current mode.

APPLICATions InFORmATion
Inductor Selection
Inductors used with the LT1302 must fulfill two requirements. First, the inductor must be able to handle current
of 2.5A to 3A without runaway saturation. Rod or drum
core units usually saturate gradually and it is acceptable to
exceed manufacturers' published saturation currents by
20% or so. Second, it should have low OCR, under 0.050
so that copper loss is kept low. Inductance value is not
critical. Generally, for low voltage inputs down to 2V, a
10J,lH inductor is recommended (such as Coilcraft 003316103). For inputs above 4V to 5V use a22J,lH unit (such as
Coilcraft 003316-223). Switching frequency can reach up
to 400kHz so the core material should be able to handle
high frequency without loss. Ferrite or molypermalloy
cores are a better choice than powdered iron. If EMI is a
concern atoroidal inductor is suggested, such as Coiltronics
CTX20-4.
For a boost converter, duty cycle can be calculated by the
following formula:

OC=1-(~)
VOUT
Aspecial situation exists where the VouTlVlN differential is
high, such as a2V-to-12V converter. The required duty
cycle is higher than the LT1302 can provide, so the
converter must be designed for discontinuous operation.
This means that inductor current goes to zero during the
switch off-time. In the 2V-to-12V case, inductance must
be low enough so that current in the inductor can reach
2A in a Single cycle. Inductor value can be defined by:

4-270

(VIN - Vsw ) x tON

L<~---"---

2A

With the 2V input avalue of 3.3J,lH is acceptable. Since the
inductance is so low, usually a smaller core size can be
used. Efficiency will not be as high as for the continuous
case since peak currents will necessarily be higher.
Table 1lists inductor suppliers along with appropriate part
numbers.
Table 1. Recommended Inductors
VENDOR
Coilcraft

Coiltronics
Oale
Sumida

PART NO.
003316-103
003316-153
003316-223
CTX10-2
CTX20-4
LPT4545-100LA
LPT4545-200LA
C0105-100
C0105-150
COR125-220

VALUE(lJH)
10
15
22
10
20
10
20
10
15
22

PHONE NO.
(708) 639-6400

(407) 241-7876
(605) 665-9301
(708) 956-0666

CapaCitor Selection
The output capacitor should have low ESR for proper
performance. A high ESR capacitor can result in "modehopping" between current mode and Burst Mode at high
load currents because the output voltage will increase by
Isw x ESR when the inductor current is flowing into the
diode. Figure 4 shows output voltage of an LT1302-5
boost converter with two 220~ AVX TPS capacitors atthe
output. Ripple voltage at a 51 OmA load is about 30mVp_p

LT1302/LT1302-5
APPLICATions InFoRmATion
and there is no low frequency component. The total ESR
is under 0.03Q. If a single 1001JF aluminum electrolytic
capacitor is used instead, the converter mode-hops between current mode and Burst Mode due to high ESR,
causing the voltage comparator to trip as shown in Figure
5. The ripple voltage is now over 500mVp_p and contains
a low frequency component. Maximum allowable output
capacitor ESR can be calculated by the following formula:
ESRMAX = Vos X VOUT

VREF x1A

where,
Vas = 15mV
VREF = 1.24V

Input Capacitor
The input supply should be decoupled with agood quality
electrolytic capaCitor close to the LT1302 to provide a
stable input supply. Long leads or traces from power
source to the switcher can have considerable impedance
at the LT1302's switching frequency. The input capacitor
provides a low impedance at high frequency. A 0.11JF
ceramic capacitor is required right atthe VIN pin. When the
input voltage can be above 5V, a 10nJ11JF decoupling
network for VIN is recommended as detailed in Figure 6.
This network is also recommended when driving atransformer.

•

VOUT
50mVlDIV

AC COUPLED

510mA
ILOAO 10mA

Figure 6. A10n/11JF Oecoupling Network at VIN Is
Recommended When Input Voltage Is Above 5V
500!JslDIV

13~ F 1235
:;:; 1230

-.. t-

~

~

J'..,

~

C!l

~

~ 1.225

o
>

'"

~ 1.220
a

~ 1.215

5.02

~

4.98

4.96

r-.....

./

5.00

!Jj

/

V

~

4.92

1.205

1200
-50

4.90
-50

1.200
-50

100

LBI Pin Bias Current

~

-25

0
25
50
TEMPERATURE (OC)

75

100

FB Pin Bias Current
1.50

18

18

1.40

16

12
10

:::>

'-'

........ ,...........

U)



'-'
U)

1"--

~

r--.



.....V

400

5.10

:;:; 1235

~

600

LT1303·5 Sense Voltage

1.250

>~
a:
a:

900

'[ 160

I

75

1000

ISW = 700mA

170

f-'

/1--""

5! 100

LT1303·5 Sense Pin Resistance
to Ground

VCESAT vs Temperature

VIN = 2V

1.30
1.20

>~
a:
a:

110

'-'

1.00

:::>

:I:

r--- r-

. . . r--

'-'

!::

SU)

0.90

- t-- t::::

0.80
0.70

o

-50

-25

0
25
50
TEMPERATURE (0C)

.L7lJ!J~

75

100

o

-50

-25

0
25
50
TEMPERATURE (0C)

75

100

0.60
-50

-25

25
50
TEMPERATURE (0C)

75

100

4-281

LTl303/LT1303~5

TYPICAL PERFORmAnCE CHARAOERISTICS
Oscillator Frequency

Switch On-Time

--

,,-

[-....

Maximum Duty Cycle

200

100

190

95

180

90

~ 170

85
~ 80

--

~160

- -

>fil150

S
140
a:
~

130

~

v

~

~

~
70
:::J
C

120

2

-50

-25

0
25
50
TEMPERATURE (OC)

75

100

75

~

/

65
60

110

55

100
-50

50
-50

-25

0
25
50
TEMPERATURE (OC)

75

100

-25

0
25
50
TEMPERATURE (OC)

lT1303Q10

190

Quiescent Current
500

SWITCH OFF
VIN" 2V

~170
~ 160
a:
13150
>-15 140
t.l

1Q
:::J
0

130
120

Switch Current Limit
1200

TA,,25°C
SWITCH OFF

~ 400

~180

<-

.§.
>--

!2:

~ 300

. a:

a>-15

.....-

--

200

-

13:5
o 100

110
100
-50

-25

0
25
50
TEMPERATURE (OC)

75

0

100

15
a:

f...-- r--

.....-

1100

-r-..,.

1000

a:

:::J

t.l
:J:

1:'!

900

VJ

800

10

0

LT13OaG13

L ~ 331lH
VL,,3V

§

INPUT VOLTAGE (V)

700

0

'"" """'"

LT1303G15

Low Battery Detector Transient
Response

Shutdown Pin Response
5V

Your

1VIDIV

VSHON
5V1DIV
200!JSIDIV
VIN ,,2V
VOUT" 5V

4-282

500!JSlDIV

LT1303G16

RLOAD" 1000
VIN ,,2V
VOUT" 5V
GOUT" 1001lf

10

INPUT VOLTAGE (V)
LTl30SG14

Transient Response
Figure 1 Circui.t

ILOAD

100

LTl303G12

Quiescent Current
200

75

5!JS1DIV

LT1303G17

RpUll-UP" 47k

LT1303/LT1303-5

Pin FunCTions
GND (Pin 1): Signal Ground. Tie to PGND under the
package.

LBI (Pin 5): Low-Battery Comparator Input. When voltage
on this pin below 1.24V, LBO is low.

LBO (Pin 2): Open-Collector Output of Low-Battery Comparator. Can sink 100~. Disabled when device is in
shutdown.

VIN (Pin 6): Supply Pin. Must be bypassed with a large
value electrolytic to ground. Keep bypass within 0.2" ofthe
device.

SHDN (Pin 3): Shutdown. Pull high to shut down the
device. Ground for normal operation.

SW (Pin 7): Switch Pin. Connect inductor and diode here.
Keep layout short and direct to minimize radio frequency
interference.

FB/Sense (Pin 4): On 1303 (adjustable) this pin connects
to the main comparator C1 input. On LT1303-5 this pin
connects to the resistor string that sets output voltage
at 5V.

PGND (Pin 8): Power ground. Tie to signal ground (pin1)
under the package. Bypass capacitor from VIN should be
tied directly to PGND within 0.2" of the device.

BLOCK DIAGRAmS

1.1
L1

6~~----------------------------

R1

R2

Figure 2. LT13D3 Block Digram

4-283

LT1303/LT1303-5
BLOCK DIAGRAmS
.. -

I

4

FB

6

~!:L

____________________________

7

fi"'!.... ..

I
I
I

I

R2
156k

GND

Figure 3. LT1303-5 Block Diagram

OPERATion
Operation of the LT1303 is best understood by referring to
the Block Diagram in Figure 2. When C1's negative input,
related to the output voltage by the appropriate resistordivider ratio, is higher than the 1.24V reference voltage,
C1 's output is low. C2, A3 and the oscillator are turned off,
drawing no current. Only the reference and C1 consume
current, typically 140~. When C1 's negative input drops
below 1.24V and overcomes C1 's 6mV hysteresis, C1 's
output goes high, enabling the oscillator, current comparator C2 and driver A3. Quiescent current increases to 2mA
as the device goes into active switching mode. Q1 then
turns on in controlled saturation for nominally 6115 or until
current comparator C2 trips, whichever comes first. The
switch then turns offfor approximately 1.5115, then turns on
again. The LT1303's switching causes current to alternately build up in L1and dump into output capacitor C4 via
D1, increasing the output voltage. When the output is high
enough to cause C1's output to go high, switching action
ceases. Capacitor C4 is left to supply current to the load
until VOUT decreases enough to force C1's output high, and
the entire cycle repeats. Figure 4 details relevant waveforms. C1's cycling causes low-to-mid-frequency ripple
voltage on the output. Ripple can be reduced by making the

4~284

output capacitor large. The 100W unit specified results in
ripple of 50mV to 100mV on the 5V output. A 220W
capacitor will decrease ripple by approximately 50%.
VOUT

100mVlDIV

AC COUPLED

Vsw

5V1DIV

IL
1A1DIV
20jlS/DIV

LT1303F04

Figure 4. Burst Mode Operation in Action

If switch current reaches 1A, causing C2 to trip, switch ontime is reduced and off-time increases slightly. This allows
continuous operation during bursts. C2 monitors the
voltage across 30 resistor R1 which is directly related to
the switch current. Q2's collector current is set by the
emitter-area ratio to 0.6% of Q1 's collector current. When
R1's voltage drop exceeds 18mV, corresponding to 1A
switch current, C2's output goes high, truncating the ontime portion of the oscillator cycle and increasing off-time

LTl 303/LTl 303-5
OPERATion
to about 21JS. Response time of C2, which determines
minimum on-time, is approximately 300ns.
Low BaHery Detector

hysteresis built in, but hysteresis can be added by
connecting a high-value resistor from LBI to LBO as
shown in Figure S. The internal reference can be accessed
via the comparator as shown in Figure 6.

The low battery detector is enabled when SHDN is low and
disabled when SHDN is high. The comparator has no

VIN

5V
R4
47k

VREF=1.24V (1
R1 = (VTRIP-1.24V) (43.5k)
HYSTERESIS = 30mV

+~)

VIN "VREF + 200mV
R1 + R2 =33k

Figure 6. Accessing Internal Reference
Figure 5. R3 Adds Hysteresis to Low-SaUery Detector

---------------------------APPLICATions InFORmATion
Inductor Section
Inductors suitable for use with the LT1303 usually fall in
the SJ.tH to SOJ.tH range. The inductor must: (1) handle
current of 1.2SA without saturating, (2) have enough
inductance to provide a di/dt lower than 400mAlIJS, and
(3) have low enough DC resistance to avoid excessive
heating or efficiency losses. Higher value inductors will
deliver more power buttend to be physically larger. Most
ferrite core drum or rod inductors such as those specified
in Table 1are suitable for use. It is acceptable to bias openflux inductors (e.g. Sumida CDS4) into saturation by 10 to
20% without adverse effects.
Table 1. Recommended Inductors
VENOOR
Coilcraft
Coiltronics

Sumida
Gowanda

SERIES
003316
001608
OCTAPAK
CTX20-1
CTX20-2
CTX33-4
C054
GA10

PHONE
APPROPRIATE VALUES NUMBERS
(708) 639-6400
101JH to 471JH
101JH
(407) 241-7876
201JH
201JH
331JH
(708) 956-0666
101JH to 331JH
(716) 532-2234
101JH to 331JH

Figure 7 shows inductor current of a suitable inductor,
di/dt is controlled at all times. The rapid rise in current
shown in Figure 8 results from this inductor saturating at
approximately 1A. Saturation occurs when the inductor
cannot hold any more magnetic energy in the core. Current
then increases rapidly, limited only by the resistance ofthe
winding. Figure 9's inductor has high DC resistance which
results in the exponential time constant shape of the
inductor current.

Il
500mAlDIV

5~DIV

Figure 7. Properly Chosen Inductor Does Not Saturate

4-285

II

LTl 303/LTl 303-5
APPLICATions InFoRmATion
Capacitor Selection

Figure 8. This Inductor Saturates at IL",lA. APoor Choice

Input and output capacitors should have low ESR for best
efficiency. Recommended capacitors include AVX TPS
series, Sprague 5950 series, and Sanyo OS-CON. The
output capacitor's ESR determines the high frequency
ripple amplitude. A 100j.iF capacitor is the minimum recommended for a5Voutput. Higher output voltages can use
lower capacitance values. For example, a 12V output can
use a 33j.iF or 47j.iF capacitor. The VIN pin of the LT1303
should be decoupled with a47j.iF or 100j.iF capacitor at the
pin. When driving atransformer, an additional decoupling
network of 100 and 0.1j.iF ceramic is recommended as
shown in Figure 10.
VIN .......- - - -......- - - ,

lT1303F09

Figure 9. Slight EXponential Shape to Inductor Current
Waveform Indicates Excessive DC Resistance

O.1~F

CERAMIC

Diode Selection
The LT1303's high switching speed demands ahigh speed
rectifier. Schottky diodes are preferred for their low forward drop and fast recovery. Suitable choices include the
1N5817, MBRS120LT3, and MBR0520LT1. Do not use
signal diodes such as 1N4148. They cannot carry 1A
current. Also avoid "general-purpose" diodes such as
1N4001. These are far too slow and are unsuitable for any
switching regulator application. For high temperature
applications asilicon diode such as the MUR1 05 will have
less leakage.'

4-286

Figure 10. 10n-1J.IF Network to LT1303 VIN Pin Provides
Additional Decoupling. Recommended When Driving
Transformers.
Table 2 Recommended Capacitors
VENDOR
AVX
Sanyo
Panasonic
Sprague

SERIES
TPS
OS-CON
HFQ

5950

TYPE
Surface Mount
Through-Hole
Through-Hole
Su rface Mount

PHONE
NUMBERS

(803) 448-9411
(619) 661-6835
(201) 348-5200
(603) 224-1961

LT1303/LT1303-5
TYPICAL APPLICATions
Setting Output Voltage on LT1303
1N5817

+

100~F

+

100~F

III
5V Step-Up Converter with Reference Output

_ _t-~~TPUT

+

r~
• SUMIDA CD54-220MC

4-287

LTl 303/LTl 303-5
TYPICAL APPLICATions
4-, 5-Cell to 5V Converter with Output Disconnect

5100

VOUT

---t--+- 5V
100mA

LT1303TA05

3-Cell to 3.3V Boost/Linear Converter with Output Disconnect

......---I....;;.......;........I\I'I/Ir--t- VOUT 3.3v/200mA

·SUMIDA CD54-1 OOMC
.. AVX TPS 330!,F/6.3V
11 % METAL FILM

4-288

LT1303/LT1303-5
TYPICAL APPLICATions
EL Panel Driver
MUR160

~~ - . . - - - - - -......---:-;:"'111-:-::,...-....- - - - -..... --------

1.5VTO

....!....C1·
*"50 PF

10n

+

47~F

EL PANEL

100Hz TO 1000Hz
SQUARE WAVE - - - - - - - - - - - - - '
DRIVE
• ADD C1 FOR OPEN-PANEL PROTECTION
"DALE LPE5047-A1321:15 TURNS RATIO (605) 666-9301
tR1 ADJUSTS VOUT 83VRMS TO 115VRMS

LTt303TA06

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1129

Micropower Low Dropout Regulator

700mA Output Current in SO-8 Package

LT1182/83/84

LCD and CCFL Backlight Controller

High Efficiency and Excellent Backlight Control Range

LT1301

5V to 12V/200mA Step-Up DC/DC Converter

12011A Quiescent Current

LT1302

2-Cell to 5V/600mA Step-Up DC/DC Converter

20011A Quiescent Current

LT1305

Micropower 2A Switch DC/DC Converter with Low-Battery Detect

2V to 5V at 400mA

LT1372
LTC@1472

500kHz Step-Up PWM, 1.5A Switch

Low Noise, Fixed Frequency Operation

PCMCIA Host Switch with Protection

Includes Current Limit and Thermal Shutdown

4-289

I~TLElcnHN~OI'O-G~q~----------U_130_5
~,
~
Micropower High Power
IT

DC/DC Converter with
Low-Battery Detector
FEATURES

DESCRIPTion

•
•
•
•
•
•
•

The LT@1305 is a micropower step-up DC/DC converter
that uses Burst Mode™ operation. Similar to the LT1303,
the LT1305 features a2A internal low-loss switch and can
deliver up to four times the output power of the LT1303.

5V at 400mA from 2V Input
Supply Voltage As Low As1.8V
120J,IA Quiescent Current
Low-BaHery Detector
Low VCESAT Switch: 310mV at 2A Typ
Uses Inexpensive Surface Mount Inductors
8-Lead SO Package

APPLICATions

Quiescent current is only 120J,IA and the Shutdown pin
further reduces current to 10J,IA. A low-battery detector
provides an open-collector output that goes low when the
input voltage drops below a preset level. The LT1305 is
available in an 8-pin SO, easing board space requirements.
LT, LTC and LTare registered trademarks of linear Technology Corporation.
Burst Mode is a trademark of linear Technology Corporation

• 2-Cell and 3-Cell to 5V Conversion
• EL Panel Drivers
• Portable Instruments

TYPICAL APPLICATiOn
2-Cell and 3-Cell to 5V!400mA DC/DC Converter
with Low-BaHery Detect

Efficiency
90

01
LOWBATTERV
GOES LOW AT
VSAl" 2.2V
2T03
CELLS

VIN =3.00V i--'

80

>
u

220l1F

Cl, C2: AVX TPSE22701OROl00
01: MOTOROLA MBRSl30LT3
L1: COILCRAFT 003316·103

4-290

l

1111

VOUT
5V
400mA

15

~

r,

1-F-\.#f+H-fll+--I-+++Ifl+II-\-VIN = 2.00V
I.
fI-II-++I+ttlt-++-ffiHftl-\.
VIN = 2.50V

i'3

70

LT12QS-TAOO

10
100
LOAD CURRENT (rnA)

1000

LT1305
ABSOLUTE mAXimum RATinGS
VIN Voltage .............................................................. 10V
SW1 Voltage ............................................................ 25V
FB Voltage ............................................................... 10V
Shutdown Voltage ................................................... 10V
LBO Voltage ............................................................. 10V
LBI Voltage .............................................................. 10V
Maximum Power Dissipation ............................. 500mW
Operating Temperature Range ..................... ooe to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300oe

PACKAGE/ORDER InFORmATion
ORDER PART
NUMBER

TOP VIEW

'""OM"

LBO 2
SHDN 3
FB 4

7SW
6 VIN
5 LBI

S8 PACKAGE
8-LEAD PLASTIC SO

LT1305eS8
S8 PART MARKING
1305

TJMAX =100'C, 6JA =80'C/W
Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS

TA = 25°C, VIN = 2.0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

10

Quiescent Current

VSHDN = 0.5V, VFB = 2V
VSHDN = 1.8V

VIN

Input Voltage Range
Feedback Voltage
Comparator Hysteresis
Feedback Pin Bias Current
Oscillator Frequency

VFB = 1V
Current Limit Not Asserted

MIN

••
•
•
•
•

tON

Switch On Time
Output Line Regulation

Current Limit Not Asserted

Switch Saturation Voltage
Switch Leakage Current

Isw= 1A
Vsw = 5V, Switch Off

Peak Switch Current

VIN = 2V

LBI Trip Voltage

VIN = 5V
(Note 2)

LBllnput Bias Current

VLBI = 1V

LBO Output Low

ILOAD = 100~

LBO Leakage Current

VLBI = 1.3V, VLBO = 5V

Shutdown Pin High

VSHDNL

Shutdown Pin Low

ISHDN

Shutdown Pin Bias Current

UNITS

200
15

~
~
V
V

1.55

1.22

1.24

1.26

V

6

12.5

mV

120

7

20

nA

155

185

kHz
%/oC

95

%

0.2

Maximum Duty Cycle

VSHDNH

MAX

120
7
1.8
2.0

Oscillator TC
DC

VCESAT

TYP

1.8V < VIN < 6V

VSHDN = 5V
VSHDN = 2V
VSHDN = OV

The. denotes specifications which apply over the O°C to 70°C operating
temperature range.
Nole 1: Hysteresis specified is DC. Output ripple may be higher if output
capacitance is insufficient or capacitor ESR is excessive.

•
•
•
•
•
•

•
•
•
•
•
•
•

75

86
5.6

~

0.06

0.15

140

280

0.1

10

1.35
1.20
1.15

2

2.35
2.50

1.21

1.24

%N
mV
~
A
A

2.15

A

1.27

V

7

20

nA

0.11

0.4

V

0.1

5

~
V

1.8
8.0
3.0
0.1

0.5

V

20

~
~
~

1

Nole 2: Low-battery detector comparator is inoperative when device is in
shutdown.

4-291

LT1305
TYPICAL PERFORmAnCE CHARACTERISTICS
Switch On Time

Maximum Duty Cycle

Oscillator Frequency
200

--

/

r-.....

-25

0
25
50
TEMPERATURE (OC)

190

95

180

90

:¥ 170

§a: 140

75

- -- --

~160

>~ 150
~

2
-50

100

130

I--

~

85
80

'"' 75
1:;
65
60

110

55
-25

0
25
50
TEMPERATURE (0C)

75

~

/

~ 70
:::>
c

120
100
-50

100

C

50
-50

100

-25

0
25
50
TEMPERATURE (0C)

75

100

LT131)50GOl

Quiescent Current
200
190

Quiescent Current
500

SWITCH OFF
VIN = 2V

a:

f-

ill

140

:::>
0

130
120

'"'en~

2.2

f-

~

a:

:::>

-

-

'"'f-

ill

200

-25

0
25
50
TEMPERATURE (OC)

75

:5
o 100

o
o

100

a:
a:

:::>

'"'

""'- ...........

1.8

:I:

f.-- !---

13

110
100
-50

zw 2.0

--- -

~ 300

160

a 150

g

~ 400

~~ ~;~
~

Current limit
2.4

TA = 25°C
SWITCH OFF

'"'t:::
ll:

1.6

'";:is

1.4

--

t-.

-....... ~

en
0..

1.2
1.0
-50

10

-25

0
25
50
TEMPERATURE eC)

INPUT VOLTAGE (V)

75

100

LT1305'G04

LBI Pin Bias Current

FB Pin Bias Current

20

~
fz

~
a:

FB Voltage

20

1.250

18

18

1.245

16

16

1.240

[

14

§1.235

f-

12

a:

10

14
12
10

:::>

'"'~

.........

..........

'"

ill
a:

---

:::>

r-.....

'"'~

..............

0;

--

,.-

-I'--..

'";:: 1.230 V

.........

~ 1.225

'"~ 1.220

i--

c

~

1.215

1.210
1.205

o

-50

-25

0
25
50
TEMPERATURE (OC)

75

100

LT1305·G07

4-292

o

-50

-25

0
25
50
TEMPERATURE (OC)

75

100

LT130S-G08

1.200
-50

-25

0
25
50
TEMPERATURE (OC)

75

100

LT1305
TYPICAL PERFORmAnCE CHARAOERISTICS
Low-Battery Detect Trip Point

Switch Saturation Voltage
TA = 25°C

1.240

w

1.230

:>
.s
250
w

/'

I--

.s

...... .........

~ 300

;::j

~

~
~

o

:: 1.220

V-

200

=> 150

53
@100

1.215
1.210

~

1.205
1.200
-50

,/'

§; 250

'";::j 1.225
~

300

:> 350

1.245

~ 1.235

Switch Saturation Voltage

400

1.250

-25

0
25
50
TEMPERATURE (OC)

75

100

".

... v

i.--" V

~
':; 200

§;

~

=>

53

100

'"t::

50

~

o

-

z
2 150

:l::

50

o

ISW=1A

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SWITCH CURRENT (A)

o

-50

-25

0
25
50
TEMPERATURE (OC)

75

100

Pin FunCTions
GND (Pin 1): Signal Ground. Tie to PGND under the
package.

LBI (Pin 5): Low-Battery Comparator Input. When voltage
on this pin is below 1.24V, LBO is low.

LBO (Pin 2): Open-Collector Output of Comparator C3.
Can sink 1OO~. High impedance when device is in shutdown.

VIN (Pin 6): Supply Pin. Must be bypassed with a large
value capacitor to gound. Keep bypass within 0.2" of the
device.

SHDN (Pin 3): Shutdown. Pull high to shut down the
LT1305. Ground for normal operation.

SW (Pin 7): Switch Pin. Connect inductor and diode here.
Keep layout short and direct to minimize radio frequency
interference.

FB (Pin 4): Feedback Input. Connects to main comparator
C1 input.

PGND (Pin 8): Power Ground. Tie to signal ground (pin 1)
under the package. Bypass capacitor from VIN should be
tied directly to PGND within 0.2" of the device.

4-293

II

LT1305
BLOCK DIAGRAm
L1

l~~-~--------------------------

R1

R2

-¥--

LT1305·FOl

Figure 1. LT1305 Block Diagram

OPERATion
Operation of the LT1305 is best understood by referring to
the Block Diagram in Figure 1. When C1 's negative input,
related to the output voltage by the appropriate resistordivider ratio, is higher than the 1.24V reference voltage,
C1 's output is low. C2, A3 and the oscillator are turned off,
drawing no current. Only the reference and C1 consume
current, typically 120~. When C1 's negative input drops
below 1.24V and overcomes C1 's 6mV hysteresis, C1 's
output goes high, enabling the oscillator, currentcomparator C2 and driver A3. Quiescent current increases to 2mA
as the device goes into active switching mode. Q1 then
turns on in controlled saturation for nominally 6~ or until
current comparator C2 trips, whichever comes first. The
switch then turns off for approximately 1.5JlS, then turns on
again. The LT1305's switching causes current to alternately build up in L1and dump into output capaCitor C4 via
01, increasing the output voltage. When the output is high
enough to cause C1 's output to go high, switching action
ceases. CapaCitor C4 is left to supply current to the load

4-294

until VOUT decreases enough to force C1 's output high, and
the entire cycle repeats. Figure 2 details relevant waveforms. C1 's cycling causes low-to-mid-frequency ripple
voltage on the output. Ripple can be reduced by making the
output capaCitor large. The 220~ unit specified results in
ripple of 50mV to 1OOmVon the 5V output. Paralleling two
capaCitors will decrease ripple by approximately 50%.
VOUT

100mVlDIV
AC COUPLED

Vsw

5V1DIV

Il
1A1DIV

50/lSIDIV

Figure 2. Burst Mode Operation

LT1305
OPERATion
If switch current reaches 2A, causing C2 to trip, switch on
time is reduced and off time increases slightly. This allows
continuous operation during bursts. C2 monitors the
voltage across 30 resistor R1 which is directly related to
the switch current. 02's collector current is set by the
emitter-area ratio to 0.6% of 01 's collector current. When
R1 's voltage drop exceeds 36mV, corresponding to 2A
switch current, C2's output goes high, truncating the on
time portion of the oscillator cycle and increasing off time
to about 2f..1S. Response time of C2, which determines
minimum on time, is approximately 300ns.
Low-Battery Detector
The low-battery detector is enabled when SHON is low and
disabled when SHON is high. The comparator has no
hysteresis built in, but hysteresis can be added by
connecting a high-value resistor from LBI to LBO as
shown in Figure 3. The internal reference can be accessed
via the comparator as shown in Figure 4.

Inductor Selection
Inductors used with the LT1305 must fulfill two requirements. First, the inductor must be able to handle current
of 2A to 2.5A without runaway saturation. Rod or drum
core units usually saturate gradually and it is acceptable to
exceed manufacturer's published saturation current by
20% or so. Second, the unit must have low OCR, under
0.050 so that copper loss is kept low and excess heating
is avoided. Inductance value is not critical. Generally, for
low voltage inputs below 3V a 10J-lH inductor is recommended (such as Coilcraft 003316-1 03). For inputs above
4V to 5V use a22J-lH unit (such as Coilcraft 003316-223).
Switching frequency can reach up to 300kHz so the core
material should be able to operate at high frequency
without excessive core loss. Ferrite or molypermalloy
cores are a better choice than powdered iron. If EMI is a
concern, a toroidal inductor is suggested, such as . .
Coiltronics CTX20-4.
..
CapaCitor Selection

5V
R4

R1 = (VTRlP -1.24V) (43.5k)
HYSTERESIS = 30mV

Figure 3. R3 Adds HystereSiS to Low-Battery Detector

Output and input capacitors should have low ESR for best
performance. Inexpensive aluminum electrolytics sometimes have ESR above 10, even for relatively large values
such as 1OO~, 16V units. Since the LT1305 has a 2A
current limit, 2V of ripple voltage would result with such a
capacitor at the output. Keep ESR below 0.050 to 0.1 0 for
reasonable ripple voltage. Tantalum capacitors such as
AVX TPS series or Sprague 5930 have low ESR and are
surface mount components. For lowest ESR, use Sanyo
OS-CON units (OS-CON is also available from Vishay).
These capacitors have superior ESR, small size and perform well at cold temperatures.
Diode Selection
A2A Schottky diode such as Motorola MBRS130LT3 is a
good choice for the rectifier diode. A 1N5821 or
MBRS130T3 are suitable as well. 00 not use "general
purpose" diodes such as 1N4001. They are much too slow
for use in switching regulator applications.

VREF=1.24V (1

+~)

VIN ;, VREF + 200mV
R1 + R2 - 33k

LT1305''''

Figure 4. Accessing Internal Reference

.L7lJn~

4-295

LT1305
TYPICAL APPLICATions
Setting Output Voltage

4-Cell-to-5V Converter

VIN _ ...._ _ _~,.,..rrY'\......_-I~......,

r---+---..... ~~omA

r - -.....-Vour
100!,F

+

- -SANYO OS-CON

5V Step-Up Converter with Reference Output
MBRS130LT3

.------+-- ~~omA
VREF

O~UT~~--t-----t----

1.24V

EL Panel Driver
MUR160

1.5VTO~~ -

....- - - - - - -....--:-~llil_::~----_I*'---....... - - - ,
-L-Cl.,-50pF

-#

+
10k
CPANEL ,; 100nF

LT1305·TA04

100Hz TO 1000Hz
SQUAREWAYE-----------------'
DRIVE
-ADD Cl FOR OPEN-PANEL PROTECTION
"DALE LPE5047-A1321:15 TURNS RATIO
10!,H PRIMARY INDUCTANCE (605) 666-9301
tRl ADJUSTS Your 83VRMS TO 115VRMS
ttAVX TPS OR SANYO OS-CON MUST HAVE ESR ';O.1511

4-296

LT1305
RELATED PARTS
PART NUMBER
LT1129

DESCRIPTION
Micropower Low Dropout Regulator

700mA Output Current in SO-8 Package

LT1182J83/84

LCD and CCFL Backlight Controller

High Efficiency and Excellent Backlight Control Range

LT1301

5V to 12V/200mA Step-Up DC/DC Converter

120~

Quiescent Current

LT1302

2-Cell to 5V/600mA Step-Up DC/DC Converter

200~

Quiescent Current

LT1303

Micropower DCIDC Converter with Low-Battery Detect

LT1372
LTC®1472

500kHz Step-Up PWM, 1.5A Switch

2V to 5V at 200mA
Low Noise, Fixed Frequency Operation

PCMCIA Host Switch with Protection

Includes Current Limit and Thermal Shutdown

.L7lJ!J~

COMMENTS

4-297

~Y~[1~~---5-0-0k-H-Z-H-ig-h-E-ff-ic-~:-ln_3~-~
3A Switching Regulator
FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•

The LT®1371 is amonolithic high frequency current mode
switching regulator. It can be operated in all standard
switching configurations including boost, buck, flyback,
forward, inverting and "Cuk." A3A high efficiency switch
is included on the die, along with all oscillator, control and
protection circuitry.

Faster Switching with Increased Efficiency
Uses Small Inductors: 4. 7~
All Surface Mount Components
Low Minimum Supply Voltage: 2.7V
Quiescent Current: 4mA Typ
Current Limited Power Switch: 3A
Regulates Positive or Negative Outputs
Shutdown Supply Current: 12!lA Typ
Easy External Synchronization

APPLICATions
•
•
•
•

The LT1371 typically consumes only 4mA quiescent
current and has higher efficiency than previous parts.
High frequency switching allows for very small inductors
to be used.
New design techniques increase flexibility and maintain
ease of use. SWitching is easily synchronized to an external logic level source. A logic low on the Shutdown pin
reduces supply current to 12!lA. Unique error amplifier
circuitry can regulate positive or negative output voltage
while maintaining simple frequency compensation techniques. Nonlinear error amplifier transconductance reduces output overshoot on start-up or overload recovery.
Oscillator frequency shifting protects external components during overload conditions.

Boost Regulators
Laptop Computer Supplies
Multiple Output Flyback Supplies
Inverting Supplies

D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
5V-10-12V Boost Converter

12V Output Efficiency

Dl

100

VIN = 5V

90

Cl··
2211F
25V

4-298

C4··

~~~F

x2

·COILCRAFT D03316P-472 (4.7I1H).
D03316p·l03 (IOI1H) OR
SUMIDA CDI 04·1 OOMC (IOI1H)
•• AVX TPSD226M025R0200
tMAX lOUT
Ll' lOUT
4.7I1H O.7A
10 H 0.8A

~

80

~

70

~

tt

/1'"

-

V

60

50
0.01

0.1
OUTPUT CURRENT (A)

LT1371
ABSOLUTE mAXimum RATinGS
Supply Voltage ....................................................... 30V
Switch Voltage .... .................................................... 35V
SIS, SHDN, SYNC Pin Voltage ................................ 30V
Feedback Pin Voltage (Transient, 10ms) .............. ±10V
Feedback Pin Current.... ........ .......... ..................... 10mA
Negative Feedback Pin Voltage
(Transient, 10ms) ............................................. ±10V

Operating Junction Temperature Range
Operating ........ ........................ .............. O°C to 125°C
Short Circuit ......................................... O°C to 150°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn

[i
FRONT VIEW

6

TAB
IS
GND

0

5
4
3

2
1

VIN
SIS
Vsw
GND
NFB
FB
Vc

ORDER PART
NUMBER

ORDER PART
NUMBER

TOP VIEW

LT1371CSW

LT1371CR

RPACKAGE
HEAD PLASTIC DD
TJMAX = 125°C, OJA = 30°CIW
WITH PACKAGE SOLDERED TO 0.5 INCH2 COPPER
AREA OVER BACKSIDE GROUND PLANE OR INTERNAL
POWER PLANE. 9JA CAN VARY FROM 20°CIW TO
>40°CIW DEPENDING ON MOUNTING TECHNIQUE

For7-lead TO-220 package availability contact LTC
Marketing.

SWPACKAGE
20-LEAD PLASTIC SO WIDE
TJMAX = 125°C, 9JA = 50°CIW
9JA WILL VARY FROM APPROXIMATELY 40°C/W WITH
O.75INCH2 OF 1OZ COPPER TO 50°CIW WITH O.33INCH2
OF 1OZ COPPER ON ADOUBLE-SIDED BOARD

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS
IIIN = 5V, Vc =O.6V, VFB =VREF, Vsw, SIS, SHON, SYNC and NFB pins open, unless otherwise noted.
SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VREF

Reference Voltage

Measured at Feedback Pin
Vc = O.BV

1.230
1.225

1.245
1.245

1.260
1.265

V
V

IFB

Feedback Input Current

VFB = VREF

250

550
900

nA
nA

0.01

0.03

'ioN

-2.490
-2.490

-2.445
-2.410

Reference Voltage Line Regulation

2.7V::; VIN::; 25V, Vc = O.BV

VNFR

Negative Feedback
Reference Voltage

Measured at Negative Feedback Pin
Feedback Pin Open, Vc = O.BV

INFB

Negative Feedback Input Current

VNFB = VNFR
2.7V::; VIN::; 25V, Vc = O.BV

Negative Feedback Reference Voltage
Line Regulation

1m

Error Amplifier Transconductance

.L7lJfJ~

Alc=±25~

•
•
•

•
•

-2.535
-2.570
-45

•
•

1100
700

V
V

-30

-15

~

0.01

0.05

'ioN

1500

1900
2300

III11ho
III11ho

4-299

LT1371

ELECTRICAL CHARACTERISTICS
VIN =5V, Vc =O.6V, VFB =VREF, Vsw, SIS, SHDN, SYNC and NFB pins open, unless otherwise noted.
SYMBOL

PARAMETER

CONDITIONS

Error Amplifier Source Current

VFB = VREF -150mV, Vc = 1.5V

Error Amplifier Sink Current

VFB = VREF + 150mV, Vc = 1.5V

Error Amplifier Clamp Voltage

High Clamp, VFB = 1V
Low Clamp, VFB = 1.5V

Av

Error Amplifier Voltage Gain

f

Vc Pin Threshold
Switching Frequency

MIN

TYP

MAX

UNITS

120

200

350

1400

2400

J.lA
J.lA

1.70
0.25

1.95
0.40

2.30
0.52

V
V

Duty Cycle = 0%

0.8

500
1

1.25

V

2.7V $ VIN $ 25V

460
440

500
500

540
560

kHz
kHz

Maximum Switch Duty Cycle
BV

Switch Current Limit Blanking Time
Output Switch Breakdown Voltage

VSAT

Output Switch ON Resistance

IUM

Switch Current Limit

L\IIN
L\lsw

Supply Current Increase During Switch ON Time

2.7V $ VIN $ 25V
Isw= 2A
Duty Cycle = 50%
Duty Cycle = 80% (Note 1)

•
•

•

•

85

95
260

•
•
•
•

35

130
47

ns
V

0.25

0.45

n

3.8
3.4
15

4.8
4.4

A
A
mAlA

3.0
2.6

Control Voltage to Switch Current
Transconductance
Supply Current
Shutdown Supply Current

2.7V $ VIN $ 25V

Shutdown Threshold

2.7V $ VIN $ 25V

2.7V $ VIN $ 25V, VS/S $ 0.6V

Shutdown Delay

SIS or SHDN Pin Input Current
Synchronization Frequency Range
The. denotes specifications which apply over the full operating
temperature range.

4-300

%

25

4

Minimum Input Voltage
10

V/V

OV $ VS/S or VSHDN $ 5V

•
•
•
•
•
•
•

AlV

2.4

2.7

V

4
12

5.5

rnA

30

J.lA

0.6

1.3

2

V

5
-10

12

25

lIS

12

J.lA

800

kHz

600

Nole 1: For duty cycles (DC) between 50% and 85%, minimum
guaranteed switch current is given by IUM = 1.33 (2.75 - DC).

LT1371
rYPICAL PERFORmAnCE CHARAOERISTICS
Switch Saturation Voltage
vs Switch Current

Switch Current Limit
vs Duty Cycle

1.0

.Y

150'C

~ 0.9

100'C~

0.8

~ ./

0.5

2SJC

A~D

.... ~'c

, / 1/

/.

0.6

2S~

V

'/.

0.7

Minimum Input Voltage
vs Temperature

/'

-55'C

-

0.3

o

o

I--+---+-+--+--f---+---+---l

>

5

~ 2.2

1-+--+-+-+-1-+--+---1

2.0

I--+---+-+--+--i---+---+---l

~~

0.1

2.6

~ ~V

,.

0.2

I--+---+-+--+--i---+---+---l

~ 2.4 ~'*=~==i=:t=~t=t~

::::::::

lfi '/ / ' -S5'C
IA t/. ,/

0.4

~

2.8

o
o

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
SWITCH CURRENT (A)

1.8 L---'-----'-_-'---"-_'--...L...---'----'
~~
0 ~ W ~ 100 1~ lW
TEMPERATURE ('C)

10 20 30 40 SO 60 70 80 90 100
DUTY CYCLE (%)

LT1371·G01

Shutdown Delay and Threshold
vs Temperature
20

2.0

18

1.8

16
[

~ f-- JHUTJOWN ITHREkHOLh- f----

r--..:

14

...... ;-......

12
;

~

Minimum Synchronization
Voltage vs Temperature

~,

....... ..........

~

8 I-SHUTDOWN DELAY

1.6 ~
c::
1.4

~

1.0 ~
0.8

ill
~

o
0.6 :;

0.4

S

o

-50 -25

0

0

--

2.0

o

t§

z

1.5

o

'"
13
~

1.0

"'i

0.5

Z
~

0

25 50 75 100 125 150
TEMPERATURE ('C)

-50 -25

~
~

2

.J

-3

"

I
IJ

-5

-1

0

0

4

S

7

8

9

~

""-,

ffi
u::

-200

\

-300

25 50 75 100 125 150
TEMPERATURE ('C)

-0.3

-0.2
-0.1
VREF
FEEDBACK PIN VOLTAGE (V)

I

90

C

70

I

0.1
lT1371·G06

Error Amplifier Transconductance
vs Temperature
2000

:g 1600
~ 1400
~ 1200

"':::>t;"

:::>

6

0&

~

~

e:

3

"'- ,-,--wc
..'I

12S'C

100

1800

80

'"
z

VOLTAGE (V)

5o

I
25'C

12 -100

@ 50

2

~

100

~

,\.1 (Vc)
gm = ,\.V (FB)

..........
..........

i"--

1000

;-......

800

L">

~

40

600

30

g 400

~ 20

200

~

1

---

V

110

1:;
EE 60

I
I

-4

200

L">

Switching Frequency
vs Feedback Pin Voltage

VIN = 5V

-1

'"

~

~ ~ ~ I~

"LT1371oGOS

SIS or SHDN Pin Input Current
vs Voltage

-2

300

~
ffi

LT1371'G04

[

~
>-

il'i

F

:;;

0.2

400
fSYNC = 700kHz

~ 2.5

a 1J~

1.2

~b

....,..

10

~ 3.0

Error Amplifier Output Current
vs Feedback Pin Voltage

10

o

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FEEDBACK PIN VOLTAGE (V)

o

-50 -25

0

25 50 75 100 125 150
TEMPERATURE ('C)
LT13710G09

4-301

•

LT1371
TYPICAL PERFORmAnCE CHARAaERISTICS
Vc Pin Threshold and High
Clamp Voltage vs Temperature

Feedback Input Current
vs Temperature

2.4

800

2.2

Vel HIG~ CLA~P

2.0
~

~ 700

~

~ 1.6
>

~ 1.2

of;: 1.0
0.8

I

:::l

a:

:::l

<>

~ -20

<>

--

-r-r-

I--- Ve THRESHOLD

200

~

100

0.6
0.4
-50 -25

""
~
fil

;;< 300

0

25 50 75 100 125 150
TEMPERATURE (OC)

o

.!

f - VNFB =VNFR

iE
-10
a:

500

':;
400
c..

.1

1....

_ VFB=VREF

~ 600

1.8

~ 1.4

I

Negative Feedback Input Current
vs Temperature

~

~

-- -- --

-50 -25

""
;a
<>

r-

-

}

fi3

~

?! -40

!;c

ffi
:z
0

25 50 75 100 125 150
TEMPERATURE ('C)

LT1371'Gl0

-30

-

-{i0
-50 -25

/'"

-

/

0

25 50 75 100 125 150
TEMPERATURE (OC)

LT1371'Gl1

Pin Funalons
VC: The compensation pin is used for frequency compensation, current limiting and soft start. It is the output ofthe
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the Vc pin to ground.
FB: The feedback pin is used for positive output voltage
sensing and oscillator frequency shifting. It is the inverting input to the error amplifier. The noninverting input of
this amplifier is internally tied to a 1.245V reference.
NFB: The negative feedback pin is used for negative
output voltage sensing. It is connected to the inverting
input of the negative feedback amplifier through a 100k
source resistor.

SIS (R Package Only): Shutdown and Synchronization
Pin. The SIS pin is logic level compatible. Shutdown is
active low and the shutdown threshold is typically 1.3V. For
normal operation, pull the SIS pin high, tie itto VIN or leave
it floating. To synchronize switching, drive the SIS pin
between 600kHz and 800kHz.

4-302

SHDN: (SW Package Only): The Shutdown pin is active
low and the shutdown threshold is typically 1.3V. For
normal operation, pull the SHDN pin high, tie it to VIN or
leave it floating.
SYNC (SW Package Only): To synchronize switching,
drive the SYNC pin between 600kHz and 800kHz. If not
used, the SYNC pin can be tied high, low or left floating.
VIN: Bypass input supply pin with a low ESR capaCitor,
1O¢= or more. The regulator goes into undervoltage lockout when VIN drops below 2.5V. Undervoltage lockout
stops switching and pulls the Vc pin low.

Vsw: The switch pin is the collector ofthe power switch and
has large currents flowing through it. Keep the traces to the
switching components as short as possible to minimize
radiation and voltage spikes.
GND: Tie all ground pins to a good quality ground plane.

LT1371
ILOCK DIAGRAm
SW

SYNC

lOOk

NFB-~-...-I

FB--'-""-I
O.04Q

-

GND SENSE

OR PACKAGE ONLY

GND

lT1371·SO

)PERATlon
he LT1371 is a current mode switcher. This means that
witch duty cycle is directly controlled by switch current
ither than by output voltage. Referring to the block
iagram, the switch is turned ON at the start of each
scillator cycle. It is turned OFF when switch current
~aches apredetermined level. Control of output voltage is
btained by using the output of a voltage sensing error
mplifier to set current trip level. This technique has
everal advantages. First, it has immediate response to
Iput voltage variations, unlike voltage mode switchers
rhich have notoriously poor line transient response.
econd, it reduces the 90° phase shift at mid-frequencies
I the energy storage inductor. This greatly simplifies
losed-Ioop frequency compensation under widely varyIg input voltage or output load conditions. Finally, it
Ilows simple pulse-by-pulse current limiting to provide
laximum switch protection under output overload or
hort conditions. A low dropout internal regulator proides a 2.3V supply for all internal circuitry. This low
ropout design allows input voltage to vary from 2.7V to
5V with virtually no change in device performance. A
DOkHz oscillator is the basic clock for all internal timing.
turns ON the output switch via the logic and driver
rcuitry. Special adaptive anti-sat circuitry detects onset
f saturation in the power switch and adjusts driver

current instantaneously to limit switch saturation. This
minimizes driver dissipation and provides very rapid turnoff of the switch.
A 1.245V bandgap reference biases the positive input of
the error amplifier. The negative input of the amplifier is
broughtoutfor positive output voltage sensing. The error
amplifier has nonlinear transconductance to reduce output overshoot on start-up or overload recovery. When
the feedback voltage exceeds the reference by 40mV,
error amplifier transconductance increases 10 times,
which reduces output overshoot. The feedback inputalso
invokes oscillator frequency shifting, which helps protect components during overload conditions. When the
feedback voltage drops below 0.6V, the oscillator frequency is reduced 5:1. Lower switching frequency allows
full control of switch current limit by reducing minimum
switch duty cycle.
Unique error amplifier circuitry allows the LT1371 to
directly regulate negative output voltages. The negative
feedback amplifier's 1OOk source resistor is brought out
for negative output voltage sensing. The NFB pin regulates
at -2.49V while the amplifier output internally drives the
FB pin to 1.245V. This architecture, which uses the same
main error amplifier, prevents duplicating functions and

4-303

LT1371
APPLICATions InFoRmATion
maintains ease of use. Consult LTC, Marketing for units
that can regulate down to -1.25V.
The error signal developed at the amplifier output is
brought out externally. This pin (Vc) has three different
functions. It is used for frequency compensation, current
limit adjustment and soft starting. During normal regulator operation this pin sits at a voltage between 1V (low

output current)and 1.9V (high output current). The errol
amplifier is acurrent output (gm) type, so this voltage can
be externally clamped for lowering current limit. likewise, acapacitor coupled external clamp will provide sofl
start. Switch duty cycle goes to zero if the Vc pin is pulled
below the control pin threshold, placing the LT1371 in an
idle mode.

APPLICATions InFoRmATion
Positive Output Voltage Setting
The LT1371 develops a 1.245V reference (VREF) from the
FB pin to ground. Output voltage is set by connecting the
FB pin to an output resistor divider (Figure 1). The FB pin
bias current represents a small error and can usually be
ignored for values of R2 up to 7k. The suggested value for
R2 is 6.19k. The NFB pin is normally left open for positive
output applications. Positive fixed voltage versions are
available (consult LTC, Marketing).

Your

:d

FB
PIN

R1

VOUPVREF(l

+~)

R1=R2(~-1)
1.245

VREFL":,R2
lT1371·Rl1

Figure 1. Positive Output Resistor Divider

Negative Output Voltage Setting
The LT1371 develops a-2.49V reference (VNFR) from the
NFB pin to ground. Output voltage is set by connecting the
NFB pin to an output resistor divider (Figure 2). The
-30!!A NFB pin bias current (lNFB) can cause output
voltage errors and should not be ignored. This has been
accounted for in the formula in Figure 2. The suggested
value for R2 is 2.49k. The FB pin is normally left open for
negative output applications.
Dual Polarity Output Voltage Sensing
Certain applications benefit from sensing both positive
and negative output voltages. One example is the "Dual
Output Flyback Converter with Overvoltage Protection"
circuit shown in the Typical Applications section. Each
output voltage resistor divider is individually set as described above. When both the FB and NFB pins are used,
the LT1371 acts to prevent either output from going
beyond its set output voltage. For example, in this application if the positive output were more heavily loaded than
the negative, the negative output would be greater and
would regulate at the desired set-point voltage. The pOSitive output would sag slightly below its set-point voltage.

4-304

Figure 2. Negative Output Resistor Divider

This technique prevents either output from going unregulated high at no load.
Shutdown and Synchronization
The 7-pin R package device has a dual function SIS pin
which is used for both shutdown and synchronization. The
SW package device has both aShutdown (SHDN) pin and
a Synchronization (SYNC) pin which can be used separately or tied together. These pins are logic level compatible and can be pulled high, tied to VIN or left floating fOI
normal operation. A logic low on the SIS pin or SHDN pin
activates shutdown, reducing the part's supply current to
12!!A. Typical synchronization range is from 1.05 to 1.a
times the part's natural switching frequency, but is only
guaranteed between 600kHz and 800kHz. A12J1S resetable
shutdown delay network guarantees the part will not go
into shutdown while receiving a synchronization signal
when the functions are combined.

LT1371
IPPLICATlons InFORmATion
aution should be used when synchronizing above 700kHz
ecause at higher sync frequencies the amplitude of the
Iternal slope compensation used to prevent subharmonic
witching is reduced. This type of subharmonic switching
nly occu rs when the duty cycle ofthe switch is above 50%.
ligher inductor values will tend to eliminate problems.

When choosing an inductor you might have to consider
maximum load current, core and copper losses, allowable
component height, output voltage ripple, EMI, fault
current in the inductor, saturation and, of course, cost.
The following procedure is suggested as away of handling
these somewhat complicated and conflicting requirements.

hermal Considerations

1. Assume that the average inductor current for a boost
converter is equal to load current times VouTlVlN and
decide whether or not the inductor must withstand
continuous overload conditions. If average inductor
current at maximum load current is 1A, for instance, a
1A inductor may not survive acontinuous 3A overload
condition. Also be aware that boost converters are not
short circuit protected and that, under output short
conditions, inductor current is limited only by the
available current of the input supply.

are should be taken to ensure that the worst-case input
Dltage and load current conditions do not cause excesive die temperatures. Typical thermal resistance is
O°C/W for the Rpackage and 50°C/W for the SW package
ut these numbers will vary depending on the mounting
lchniques (copper area, airflow, etc.). Heat is transferred
'om the Rpackage via the tab and from the SW package
ia pins 4 to 7 and 14 to 17.
verage supply current (including driver current) is:
liN = 4mA + DC [lsw/60 + Isw (0.004)]
Isw = switch current
DC = switch duty cycle
witch power dissipation is given by:
Psw = (ISW)2 (Rsw)(DC)
Rsw = output switch ON resistance
Dtal power dissipation of the die is the sum of supply
ment times supply voltage, plus switch power:
PD(TDTAL) = (IIN)(VIN) + Psw
urface mount heat sinks are also becoming available
hich can lower package thermal resistance by 2 or 3
meso One manufacturer is Wakefield Engineering who
ffers surface mount heat sinks for both the R package
>0) and SW package (SW20) and can be reached at (617)
45-5900.

hoosing the Inductor
lr most applications the inductor will fall in the range of
2¢1 to 22¢1. Lower values are chosen to reduce physiII size of the inductor. Higher values allow more output
ment because they reduce peak current seen by the
)wer switch, which has a 3A limit. Higher values also
Iduce input ripple voltage and reduce core loss.

L7lJD~

2. Calculate peak inductor current at full load current to
ensure thatthe inductor will not saturate. Peak current
can be significantly higher than output current, especially with smaller inductors and lighter loads, so don't
omit this step. Powdered iron cores are forgiving
because they saturate softly, whereas ferrite cores
saturate abruptly and other core materials fa" in between. The following formula assumes continuous
mode operation but it errs only slightly on the high side
for discontinuous mode, so it can be used for all
conditions.
IpEAK = (IOUT)(VOUT) + VIN(VOUT - VIN)
VIN
2(f)(L)(VOUT)
VIN = Minimum Input Voltage
f = 500kHz Switching Frequency
3. Decide if the design can tolerate an "open" core geometry, like a rod or barrel, which has high magnetic field
radiation, or whether it needs a closed core, like a
toroid, to prevent EMI problems. One would not want an
open core next to a magnetic storage media, for instance! This is a tough decision because the rods or
barrels are temptingly cheap and small and there are no
helpful guidelines to calculate when the magnetic field
radiation will be a problem.

4-305

LT1371
APPLICATions InFoRmATion
4. Start shopping for an inductor which meets the requirements of· core. shape, peak current (to avoid
saturation), average currenWo limit heating) and fault
current. If the inductor gets too hot, wire insulation will
melt and causeturn~to-turn shorts. Keep in mind that
all good things like high efficiency, low profile and high
temperature operation will increase cost, sometimes
dramatically.
5. After making an initial choice; consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the LTC, Applications Department if
you feel uncertain about the final choice. They have
experience with awide range of inductor types and can
tell you about the latest developments in low profile,
surface mounting, etc.
Output Capacitor
The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. At 500kHz any polarized capacitor
is essentially resistive. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range needed for typical LT1371 applications is 0.0250
to 0.20. Atypical output capacitor is an AVX type TPS,
22~ at 25V (2 each), with a guaranteed ESR less than
0.20. This is a "0" size surface mount solid tantalum
capacitor. TPS capacitors are specially constructed and
tested for low ESR, so they give the lowest ESR for agiven
volume. To further reduce ESR, multiple output capacitors can be used in parallel. The value in microfarads is
not particularly critical, and values from 22~ to greater
than 500~ work well, but you cannot cheat mother
nature on ESR. If you find a tiny 22~ solid tantalum
capacitor, it will have high ESR and output ripple voltage
will be terrible. Table 1shows some typical solid tantalum
surface mount capacitors.
Table 1. Surface Mount Solid Tantalum Capacitor
ESR and Ripple Current .
ESR (MAX 0)

RIPPLE CURRENT (A)

AVX TPS, Sprague 5930
AVX TAJ
DCASE SIZE

ECASE SIZE

0.1 to 0.3
0.7 to 0.9

0.7 to 1.1

AVX TPS, Sprague 5930
AVXTAJ

0.1 to 0.3
0.9 to 2.0

0.7 to 1.1
0.36 to 0.24

4-306

0.4

CCASE SIZE

ESR (MAX 0)

RIPPLE CURRENT (A)

0.2 (Typ)
1.8 to 3.0

0.5 (Typ)
0.22 to 0.17

2.5 to 10

0.16 to 0.08

AVXTPS
AVXTAJ

B CASE SIZE
AVXTAJ

Many engineers have heard that solid tantalum capacitor~
are prone to failure if they undergo high surge currents
This is historically true and AVX type TPS capacitors arE
specially tested for surge capability, butsurge ruggednes~
is not a critical issue with the output capacitor. Solie
tantalum capacitors fail during very high turn-on surges
which do not occur at the output of regulators. Higt
discharge surges, such as when the regulator output i~
dead-shorted, do not harm the capacitors.
Single inductor boost regulators have large RMS ripplE
current in the output capacitor, which must be rated te
handle the current. The formula to calculate this is:
Output Capacitor Ripple Current (RMS)

roc

IRIPPLE (RMS) = lOUT 1/1=DC
= lOUT

IvOUT-VIN
VIN

V·

DC = Switch Duty Cycle
Input Capacitors
The input capacitor of aboost converter is less critical dUE
to the factthatthe input current waveform is triangular anc
does not contain large squarewave currents as is found ir
the output capacitor. Capacitors in the range of 1O~ te
1OO~, with an ESR of 0.20 or less, work well up to full3t
switch current. Higher ESR capacitors may be acceptablE
at low switch currents. Input capacitor ripple current for (
boost converter is :
I
- 0.3(VIN)(VOUT - VIN)
RIPPLE (f)(L)(VOUT)
f = 500kHz Switching Frequency
The input capacitor can see avery high surge currentwher
a battery or high capacitance source is connected "live'
and solid tantalum capacitors can fail under this condition

LT1371
~PPLICATlons

InFORmATion

,everal manufacturers have developed tantalum capaci[)rs specially tested for surge capability (AVX TPS series,
~H instance) but even these units may fail if the input
oltage approaches the maximum voltage rating of the
apacitor during ahigh surge. AVX recommends derating
apacitor voltage by 2:1 for high surge applications.
:eramic, OS-CON and aluminum electrolytic capacitors
nay also be used and have a high tolerance to turn-on
urges.
:eramic CapaCitors
ligher value, lower cost ceramic capacitors are now
,ecoming available in smaller case sizes. These are tempt19 for switching regulator use because of their very low
SR. Unfortunately, the ESR is so low that it can cause
lOp stability problems. Solid tantalum capaCitor ESR
enerates a loop "zero" at 5kHz to 50kHz that is instrulental in giving acceptable loop phase margin. Ceramic
apacitors remain capacitive to beyond 300kHz and usuIIy resonate with their ESL before ESR becomes effective.
'hey are appropriate for input bypaSSing because of their
igh ripple current ratings and tolerance otturn-on surges.
lutput Diode
he suggested output diode (01) is a1N5821 Schottky or
s Motorola equivalent MBR330. It is rated at 3A average
)rward current and 30V reverse voltage. Typical forward
oltage is O.6V at 3A. The diode conducts current only
uring switch OFF time. Peak reverse voltage for boost
onverters is equal to regulator output voltage. Average
lrward current in normal operation is equal to output
urrent.

output voltage ripple attenuated by the output divider and
multiplied by the error amplifier. Without the second
capaCitor, Vc pin ripple is:
V P'R' I 1.245(VRIPPLE)(gm)(RC)
c In Ipp e =
(VOUT)
VRIPPLE = Output ripple (Vp-p)
gm = Error amplifier transconductance
(",1500l!mho)
Rc = Series resistor on Vc pin
VOUT = OC output voltage
To prevent irregular switching, Vc pin ripple should be
kept below 50mVp_p. Worst-case Vc pin ripple occurs at
maximum output load current and will also be increased if
poor Quality (high ESR) output capaCitors are used. The
addition of a O.0047~ capacitor on the Vc pin reduces
switching frequency ripple to only a few millivolts. A low
value for Rc will also reduce Vc pin ripple, but loop phase
margin may be inadequate.
Switch Node Considerations
For maximum efficiency, LT1371 switch rise and fall times
are made as short as possible. To prevent radiation and
high frequency resonance problems, proper layout of the
components connected to the switch node is essential. B
field (magnetic) radiation is minimized by keeping output
diode, Switch pin and output bypass capacitor leads as
short as possible. Figures 3 and 4 show recommended

requency Compensation
oop frequency compensation is performed on the output
f the error amplifier (Vc pin) with a series RC network.
he main pole is formed by the series capacitor and the
utput impedance (",,500kQ) of the error amplifier. The
ole falls in the range of 2Hz to 20Hz. The series resistor
reates a "zero" at 1kHz to 5kHz, which improves loop
tability and transient response. A second capacitor,
'pically one-tenth the size of the main compensation
apacitor, is sometimes used to reduce the switching
'eQuency ripple on the Vc pin. Vc pin ripple is caused by

L711!J~

KEEP PATH FROM
Vsw, OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE

Figure 3. Layout Considerations-R Package

4-307

LT1371
APPLICATions InFoRmATion

7

KEEP PATH FROM
VSW, OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE

positions for these components. Efield radiation is kep'
low by minimizing the length and area of all traces con·
nected to the Switch pin. Aground plane should always bl
used under the switcher circuitry to prevent interplam
coupling.
The high speed switching current path is shown schemati·
cally in Figure 5. Minimum lead length in this path i!
essential to ensure clean switching and low EMI. The patt
including the switch, output diode and output capacitor i!
the only one containing nanosecond rise and fall times
Keep this path as short as possible.
More Help

CONNECT ALL GROUND PINS TO GROUNO PLANE

Figure 4. Layout Considerations-8W Package
L1

SWITCH
NODE

.............rr.,..,..,.....- -...- -.....--...--VOUT

For more detailed information on switching regulatol
circuits, please see Application Note 19. Linear Technol·
ogy also offers a computer software program
SwitcherCAD, to assist in designing switching converters
In addition, our Applications Department is always read~
to lend a helping hand.

HIGH
FREQUENCY
CIRCULATING
PATH

Figure 5

TYPICAL APPLICATiOnS
Positive-to-Negative Converter with Direct Feedback

Dual Output Flyback Converter with Overvoltage Protection
R1

R2
1.21k
1%

13k
1%

'COILTRONICS CTX10·4
tMAJ(

lOUT

C2

O.047~F

C3

O.0047~F

4-308

]R3

T":"

2k

'DALE LPE-5047-100MB

LT1371
rYPICAL APPLICATions
2 li-Ion Cells 10 5V SEPIC Converter"·

Single li-Ion Cell 10 5V
Dl
.--_ _...._ _ _ _ _.....rvYV~>--.~.......>--~-VOUTt
5V

--+---1 1-_.........1-...._ _

VOUTt
5V

+
+

Cl
33~F

C3

SINGLE
li-Ion
CELL

+

C4"

Cl"

100~F

100~F

10V

10V

x2

100~F

20V

10V
x2

tMAX lOUT
Cl = AVX TPSD 336M020R0200
C2 = TOKIN lE475ZY5U-C304
C3 = AVX TPSD107M010R0100
"SINGLE INDUCTOR WITH TWO WINDINGS
COILTRONICS CTX10-4
""INPUT VOLTAGE MAY BE GREATER OR
LESS THAN OUTPUT VOLTAGE

lOUT

tMAX lOUT
lOUT VIN
O.85A 4V
lA 5V
1.3A 7V
1.5A 9V

VIN

"COILCRAFT D03316P-l03
" "AVX TPSD107M010R0100

1.2A 2.7V
1.6A 3.3V
1.6A 3.6V

.ELATED PARTS
'ART NUMBER

DESCRIPTION

COMMENTS

11171
TC®1265

100kHz 2.5A Boost Switching Regulator

Good for Up to VIN = 40V

12V 1.2A Monolithic Buck Converter

Converts 5V to 3.3V at 1A with 90% Efficiency

T1302

Micropower 2A Boost Converter

Converts 2V to 5V at 600mA in SO-8 Packages

T1372
T1373

500kHz 1.5A Boost Switching Regulator

Also Regulates Negative Flyback Outputs

Low Supply Current 2S0kHz 1.SA Boost Switching Regulator

90% Efficient Boost Converter with Constant Frequency

T1376

SOOkHz 1.SA Buck Switching Regulator

Steps Down from Up to 2SV Using 4.7~ Inductors

T1S12

SOOkHz 1.SA SEPIC Battery Charger

Input Voltage May Be Greater or Less Than Battery Voltage

T1513

SOOkHz 3A SEPIC Battery Charger

Input Voltage May Be Greater or Less Than Battery Voltage

L7lJn~

4-309

f""'-LlneJ\~Q~

~,

TECHNOLOGY

___

LT_13_72__
/LT_13_77
500kHz and 1MHz
High Efficiency
1.5A Switching Regulators

FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•
•
•

The LT@1372/LT1377 are monolithic high frequency
switching regulators. They can be operated in all standard
switching configurations including boost, buck, flyback,
forward, inverting and "Cuk." A1.5A high efficiency switch
is included on the die, along with all oscillator, control and
protection circuitry. All functions of the LT1372/LT1377
are integrated into 8-pin SO/PDIP packages.

Faster Switching with Increased Efficiency
Uses Small Inductors: 4. 7~
All Surface Mount Components
Only 0.5 Square Inch of Board Space
Low Minimum Supply Voltage: 2.7V
Quiescent Current: 4mA Typ
Current Limited Power Switch: 1.5A
Regulates Positive or Negative Outputs
Shutdown Supply Current: 12~ Typ
Easy External Synchronization
8-Pin SO or PDIP Packages

APPLICATions
•
•
•
•
•

Boost Regulators
CCFL Backlight Driver
Laptop Computer Supplies
Multiple Output Flyback Supplies
Inverting Supplies

The LT13721LT1377 typically consumes only 4mA quiescent current and has higher efficiency than previous parts.
High frequency switching allows for very small inductors
to be used. All surface mount components consume less
than 0.5 square inch of board space.
New design techniques increase flexibility and maintain
ease of use. Switching is easily synchronized to an externallogic level source. A logic low on the shutdown pin
reduces supply current to 12~. Unique error amplifier
circuitry can regulate positive or negative output voltage
while maintaining simple frequency compensation techniques. Nonlinear error amplifier transconductance reduces output overshoot on start-up or overload recovery.
Oscillator frequency shifting protects external components during overload conditions.
0, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn

12V Output Efficiency

5V-to-12V Boost Converter
100

VIN = 5V

90

Z

1:;
'COILCRAFf DOI608-472 (4.7"H) OR
COl LCRAFf DT3316-103 (10"H) OR
SUMIDA CD43-4R7 (4.7"H) OR
SUMIDA CD73-100KC (10"H) OR
•• AVX TPSD226M025R0200
tMAXloUT
Ll
lOUT
4.7"H 0.25A
10"H 0.35A
LT1372'TAOl

80

1ij

~

It

......
/'

V

70
60

50
0.01

0.1
OUTPUT CURRENT (A)
LT1372° TA02

4-310

..L7lJ!J~

LT1372/LT1377
IBSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

;upply Voltage ..... " ... " .... " ..... "" .. "." ............... " .. " 30V
;witch Voltage """",,",,"",,",,""",,"",,""""""""" 35V
;IS Pin Voltage """"""""""""""""""""""""""". 30V
eedback Pin Voltage (Transient, 10ms) """"""" ±10V
eedback Pin Current"" .......................... """,, ..... 10mA
legative Feedback Pin Voltage
(Transient, 10ms) " .. "" .......... " .. """ .... ,,"" .... ,,. ±10V
)perating Junction Temperature Range
Operating ...... """ ........ ,,"""""",, .... ,," O°C to 125°C*
Short Circuit .... "" .. " .. """ ...... " .. "",, ..... O°C to 150°C
,torage Temperature Range .......... ,," .. -65°C to 150°C
ead Temperature (Soldering, 10 sec) .... """,, ..... 300°C

ORDER PART
NUMBER

TOP VIEW

"O~
FB 2

6 GND S

SIS 4

N8 PACKAGE
8-LEAD PDlP

LT1372CN8
LT1372CS8
LT1377CS8

7 GND

NFB 3

5 VIN

58 PACKAGE
HEAD PLASTIC SO

S8 PART MARKING

TJMAX= 125'C, BJA= 130'C/W (N8)
TJMAX= 125'C, BJA = 120'C/W (S8)

1372
1377

Consult factory for Industrial and Military grade parts,

Units shipped prior to Date Code 9552 are rated at 1OO°C maximum
~erating temperature,

:LECTRICAL CHARACTERISTICS
IN =5V, Vc =D.6V, VFB =VREF, Vsw, SIS and NFB pins open, unless otherwise noted.
YMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

REF

Reference Voltage

Measured at Feedback Pin
Vc = 0.8V

1.230
1.225

1.245
1.245

1.260
1.265

V
V

B

Feedback Input Current

VFB = VREF

250

550
900

nA
nA

0.01

0.03
-2.445
-2.410

~FR

IFB

Reference Voltage Line Regulation

2.7V $ VIN $ 25V, Vc = 0.8V

Negative Feedback
Reference Voltage

Measured at Negative Feedback Pin
Feedback Pin Open, Vc = 0.8V

Negative Feedback Input Current

VNFB = VNFR
2.7V $ VIN $ 25V, Vc = 0.8V

Negative Feedback Reference Voltage
Line Regulation
n

Error Amplifier Transconductance

=±25/lA

Error Amplifier Source Current

VFB = VREF -150mV. Vc = 1.5V

Error Amplifier Sink Current

VFB = VREF + 150mV. Vc = 1.5V
High Clamp. VFB = 1V
Low Clamp. VFB = 1.5V

Error Amplifier Clamp Voltage
I

~Ic

•
•
• -2.535
• -2.570
• -45
•

•
•
•

2.7V $ VIN $ 25V
LT1372
LT1377

Maximum Switch Duty Cycle
Switch Current Limit Blanking Time
I

Output Switch Breakdown Voltage

2.7V$VIN$ 25V

iAT

Output Switch "On" Resistance

Isw=1A

L7lJ!J~

•

•
•
•
•

V
V

-30

-15

/lA

0.05

%N

1100
700

1500

1900
2300

Ilffiho
Ilffiho

120

200
1400

350

/lA

2400

IlA

1.95
0.40

2.30
0.52

V
V

1.70
0.25

V/V

500
Duty Cycle = 0%

%N

0.01

Error Amplifier Voltage Gain
Vc Pin Threshold
Switching Frequency

-2.490
-2.490

0.8

1

1.25

V

460
440
0.92
0.88

500
500
1
1

540
560
1.08
1.12

kHz
kHz
MHz
MHz

260

%
ns

0.8

Q

90

95
130

35

47
0.5

V

4-311

LT1372/LT1377
ELECTRICAL CHARACTERISTICS
VIN =5V, Vc =O.6V, VFB =VREF, VSW, SIS and MFB pins open, unless otherwise noted.
SYMBOL

PARAMETER

CONOITIONS

ILiM

Switch Current Limit

Duly Cycle = 50%
Duty Cycle = BO% (Note 1)

diiN
dlsw

Supply Current Increase During Switch On-Time

••

MIN

TYP

MAX

1.5
1.3

1.9
1.7

2.4
2.2

UNITS
P
P

15

25

mAIP

Control Voltage to Switch Current
Transconductance

•
•
•
•

Minimum Input Voltage
10

N~

2

Supply Current

2.7V:s: VIN :s: 25V

Shutdown Supply Current

2.7V:s: VIN :s: 25V, VS/S:S: 0.6V

Shutdown Threshold
Shutdown Delay

2.7V:s: VIN :s: 25V

SIS Pin Input Current

OV:s: VS/S:S: 5V
LT1372
LT1377

Synchronization Frequency Range

•
•
••

2.4

2.7

~

4

5.5

mA

!J.A

12

30

0.6

1.3

2

~

5
-10

12

25

~

12

!J.A
kHI
MHI

600
1.2

BOO
1.6

The. denotes specifications which apply over the full operating
temperature range.
Note 1: For duty cycles (DC) between 50% and 90%, minimum
guaranteed switch current is given by ILiM = 0.667 (2.75 - DC).

TYPICAL PERFORmAnCE CHARAOERISTICS
Switch Saturation Voltage
vs Switch Current
1.0

~
w

~

150'C

0.9

V

0.7

~

0

>
z

0.6

;j

0

i

::l

!;;:

0.5

y V25~

/ ./
/'

lb '/ ./ -55'C

0.4

IAV
Ib.! ~v

en 0.3
~ 0.2

:t:

§

en

3.0

V)'

100'C~

0.8

,/

..a1l~

0.1

o

"

o

Minimum Input Voltage
vs Temperature

Switch Current Limit
vs Duty Cycle

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SWITCH CURRENT (A)

g

2.5

>-

~ 2.0

~

2.8

J A~D

25 C
1""'=~50C

-wc ~

-

g§ 1.5
'-'

~ 1.0

~

0.5

o
a

10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
LT1372·G02

4-312

~ 2.6 1--+--+-+-+--+--+-+---1

~

2.4

bkd:::d==t=:t:t=t=l

~ 2.2

1--+--+-+-+--+--+-+---1

2.0

1--+--+-+-+--+--+-+---1

>
~

::l

1--+--+-+-+--+--+-+---1

1.8 '---'--'-----1._'---'--'-----1.---'
-50 -25 a 25 50 75 100 125 15(
TEMPERATURE ('C)
LT1372·GOS

LTl372/LT1377
~PICAL

PERFORmAnCE CHARACTERISTICS

Shutdown Delay and Threshold
vs Temperature

Minimum Synchronization
Voltage vs Temperature

20

2.0

lB

1.B
ITHREkHOLh- ~ I-- JHUTJOWN
~,

16

r--.:

14
12

..... '-.1.

r:>

-0-

f-SHUTDOWN DELAY

--

400

1~

fSYNC = 700kHz (LT1372)
fSYNC = l.4MHz (LT1377)

1.2

'"

~

--<
1.0 ::J:

~ O.B

2.0

:2

:2

rn

LT~ .-- ::::::V
~

1.5

2'

;0

o

0::

::J:

B
:2

'"

1.0

~ 0.5

2'

:iE

!5
<.:>

r--..

200

125°C

25°G 1
fi..'--SSOG

...."'1

f-

~
:::l
o

&.
--.::

100

"""

ffi

u:

~
~ -200
ffi

:>;

0
25 50 75 100 125 150
TEMPERATURE (oG)

I'\:

5! -100

>en

:$

1

300 I--I--

0::

c::

0.2
0

2.5

1.4 --<

0.4

-50 -25

w

~
'" go

en
1.6 ::J:

:;;>
0.6

o

3.0

~

0

r----..

10

c::

Error Amplifier Output Current
vs Feedback Pin Voltage

0

I

-300

-50 -25

0

25 50 75 100 125 150
TEMPERATURE (oG)

-0.3

-0.2
-0.1
VREF
FEEDBACK PIN VOLTAGE (V)

0.1

LT1372·G04

SIS Pin Input Current
vs Voltage

Error Amplifier Transconductance
vs Temperature

Switching Frequency
vs Feedback Pin Voltage

VIN = 5V

;;?
<.:>
0:

>f~

0

C

I

>-

110

2000

100

lBOO

I

90

BO

~

70

..:

<.:>

:J

-2

IE

'"

)

-3

:2

:;:
~

L

-4

-5

1E
:::l
fil

II

-1

ji;:

cn

I

-1

0

1

2 3 4 5 6
SIS PIN VOLTAGE (V)

7

B

9

.........

r--..

1200

60

:::l

~ BOO
§ 600

40

g

30

400

200

20

o

o

0.1 0.2 0.3 0.4 0.5 0.6 0.7 O.B 0.9 1.0
FEEDBACK PIN VOLTAGE (V)

-50 -25

0

25 50 75 100 125 150
TEMPERATURE (OC)
LT1372·G09

LT1372·a07

Vc Pin Threshold and High
Clamp Voltage vs Temperature
BOO

Vel HIG~ GLA~P

2.0
1.6

1.0

I

I

Q.B

-

0.6
).4
-50 -25

0

-- -

Vc THRESHOLD

a5
0::

25 50 75 100 125 150
TEMPERATURE (oG)

-10

0::

B

500

t::; -20

.--

0-

0:2

§

.!

-VNFB=VNFR

f-

600

t::; 400

I--I--

.1

~

_ VFB=VREF

<.:>

1.4
1.2

'[ 700

!Z
g§
:::l

1.B

Negative Feedback Inpul Current
vs Temperature

Feedback Input Current
vs Temperature

2.4
2.2

r--..

t; 1000

50

10

III (Vc)
gm = IIV (FB)

I"-...

:g 1600
.§, 1400

300

~ 200

~

-

'"<.:>

l - I-- -,....

r--

/

-50 -25

fa
~

~ -40

~

100

o

,/

;ii -30

-

-

V

:2

0

25 50 75 100 125 150
TEMPERATURE (oG)

-50
-50 -25

0

25 50 75 100 125 150
TEMPERATURE (OC)

LT1372"Gl1

l7lJ!J~

4-313

LTl 372/LTl 377

Pin FunCTions
Vc (Pin 1): The compensation pin is used for frequency
compensation, current limiting and soft start. It is the
output of the error amplifier and the input of the current
comparator. Loop frequency compensation can be performed with an RC network connected from the Vc pin to
ground.
FB (Pin 2): The feedback pin is used for positive output
voltage sensing and oscillator frequency shifting. It is the
inverting input to the error amplifier. The noninverting
input of this amplifier is internally tied to a 1.245V
reference.
NFB (Pin 3): The negative feedback pin is used for negative
output voltage sensing. It is connected to the inverting
input of the negative feedback amplifier through a 100k
source resistor.

VIN (Pin 5): Bypass input supply pin with 1Ollf or more. n
part goes into undervoltage lockout when VIN drops belo
2.5V. Undervoltage lockout stops switching and pulls tt
Vc pin low.
GND S(Pin 6): The ground sense pin is a "clean" grounl
The internal reference, error amplifier and negative feel
back amplifier are referred to the ground sense pin. Cor
nect it to ground. Keep the ground path connection to t~
output resistor divider and the Vc compensation netwOl
free of large ground currents.
GND (Pin 7): The ground pin is the emitter connection I
the power switch and has large currents flowing through i
It should be connected directly to a good quality groun
plane.
Vsw (Pin 8): The switch pin is the collector of the POWI

SIS (Pin 4): Shutdown and Synchronization Pin. The SIS . switch and has large currents flowing through it. Keep t~
pin is logic level compatible. Shutdown is active low and
the shutdown threshold is typically 1.3V. For normal
operation, pull the SIS pin high, tie it to VIN or leave it
floating. To synchronize switching, drive the SIS pin between 600kHz and 800kHz (LT1372) or 1.2MHz to 1.6MHz
(LT1377).

traces to the switching components as short as possible 1
minimize radiation and voltage spikes.

BLOCK DIAGRAm
SIS

NFB---'WIr_-I

F B - -........-I
0.080
Vc

-

GND SENSE

4-314

GND

LT1372oao

LT1372/LT1377
)PERATlon
he LT1372/LT1377 are current mode switchers. This
leans that switch duty cycle is directly controlled by
witch current rather than by output voltage. Referring to
le block diagram, the switch is turned "On" at the start of
ach oscillator cycle. It is turned "Off" when switch current
~aches apredetermined level. Control of output voltage is
btained by using the output of a voltage sensing error
mplifier to set current trip level. This technique has
everal advantages. First, it has immediate response to
IPUt voltage variations, unlike voltage mode switchers
'hich have notoriously poor line transient response.
econd, it reduces the 90 0 phase shift at mid-frequencies
I the energy storage inductor. This greatly simplifies
losed-Ioop frequency compensation under widely varyIg input voltage or output load conditions. Finally, it
lIows simple pulse-by-pulse current limiting to provide
laximum switch protection under output overload or
hort conditions. A low dropout internal regulator proides a 2.3V supply for all internal circuitry. This low
ropout design allows input voltage to vary from 2.7V to
5V with virtually no change in device performance. A
OOkHz (LT1372) or 1MHz (LT1377) oscillator is the basic
lock for all internal timing. It turns "On" the output switch
ia the logic and driver circuitry. Special adaptive anti-sat
ircuitry detects onset of saturation in the power switch
nd adjusts driver current instantaneously to limit switch
aturation. This minimizes driver dissipation and provides
9ry rapid turn-off of the switch.
1.245V bandgap reference biases the positive input of
Ie error amplifier. The negative input of the amplifier is
rought outfor positive output voltage sensing. The error
mplifier has nonlinear transconductance to reduce out-

put overshoot on start-up or overload recovery. When
the feedback voltage exceeds the reference by 40mV,
error amplifier transconductance increases ten times,
which red uces output overshoot. The feedback input also
invokes oscillator frequency shifting, which helps protect components during overload conditions. When the
feedback voltage drops below 0.6V, the oscillator frequency is reduced 5:1. Lowerswitching frequency allows
full control of switch current limit by reducing minimum
switch duty cycle.
Unique error amplifier circuitry allows the LT13721LT1377
to directly regulate negative output voltages. The negative
feedback amplifier's 1OOk source resistor is brought out
for negative output voltage sensing. The NFB pin regulates
at -2.49V while the amplifier output internally drives the
FB pin to 1.245V. This architecture, which uses the same
main error amplifier, prevents duplicating functions and
maintains ease of use. Consult LinearTechnology marketing for units that can regulate down to -1.25V.
The error signal developed at the amplifier output is
brought out externally. This pin (Vc) has three different
functions. It is used for frequency compensation, current
limit adjustment and soft starting. During normal regulator operation this pin sits at a voltage between 1V (lOW
output current) and 1.9V (high output current). The error
amplifier is acurrent output (gm) type, so this voltage can
be externally clamped for lowering current limit. likewise, acapacitor coupled external clamp will provide soft
start. Switch duty cycle goes to zero if the Vc pin is pulled
below the control pin threshold, placing the LT1372/
LT1377 in an idle mode.

IPPLICATlons InFORmATiOn
ositive Output Voltage Setting

he LT1372/LT1377 develops a 1.245V reference (VREF)
om the FB pin to ground. Output voltage is set by
)nnecting the FB pin to an output resistor divider
:igure 1}. The FB pin bias current represents a small
Torand can usually be ignored forvalues of R2 upto 7k.
he suggested value for R2 is 6.19k. The NFB pin is
::>rmally left open for positive output applications.

£'7lJ!J~

Vour= VREF (1 + ~)
R1 = R2( VOUT -1)
1.245

Figure 1. Positive Output Resistor Divider

4-315

LTl 372/LTl 377
APPLICATions InFoRmATion
Positive fixed voltage versions are available (consult
Linear Technology marketing).
Negative Output Voltage Setting
The LT1372/LT1377 develops a- 2.49V reference (VNFR)
from the NFB pin to ground. Output voltage is set by
connecting the NFB pin to an output resistor divider
(Figure 2). The -301lA NFB pin bias current (INFB) can
cause output voltage errors and should not be ignored.
This has been accounted for in the formula in Figure 2. The
suggested value for R2 is 2.49k. The FB pin is normally left
open for negative output application.
-Your
R1

-Your = VNFR (1

R2

R1 = (

INFB

NFB

L
-

PIN
VNFR

t

~) t

Irt

2R~9

t

INFB (R1)

.49)

2

30 x 10-'

LT1372°F02

Figure 2. Negative Output Resistor Divider

Dual Polarity Output Voltage Sensing
Certain applications benefit from sensing both positive
and negative output voltages. One example is the "Dual
Output Flyback Converter with Overvoltage Protection"
circuit shown in the Typical Applications section. Each
output voltage resistor divider is individually set as described above. When both the FB and NFB pins are used,
the LT1372/LT1377 acts to prevent either output from
going beyond its set output voltage. For example in this
application, if the positive output were more heavily loaded
than the negative, the negative output would be greater
and would regulate at the desired set-point voltage. The
positive output would sag slightly below its set-point
voltage. This technique prevents either output from going
unregulated high at no load.
Shutdown and Synchronization
The dual function SIS pin provides easy shutdown and
synchronization. It is logic level compatible and can be
pulled high, tied to VIN or left floating for normal operation.
A logic low on the SIS pin activates shutdown, reducing
the part's supply current to 121lA. Typical synchronization

4-316

range is from 1.05 to 1.8 times the part's natural switchinl
frequency, but is only guaranteed between 600kHz am
800kHz (LT1372) or 1.2MHz and 1.6MHz (LT1377). J
12f..1S resetable shutdown delay network guarantees thl
part will not go into shutdown while receiving a synchro
nization signal.
Caution should be used when synchronizing above 700kH
(LT1372) or 1.4MHz (LT1377) because at higher synl
frequencies the amplitude ofthe internal slope compensa
tion used to prevent subharmonic switching is reduced
This type of subharmonic switching only occurs when thl
duty cycle of the switch is above 50%. Higher inducto
values will tend to eliminate problems.
.
Thermal Considerations
Care should be taken to ensure that the worst-case inpu
voltage and load current conditions do not cause exces
sive die temperatures. The packages are rated at 120°C/\/1
for SO (S8) and 130°C/W for PDIP (N8).
Average supply current (including driver current) is:
liN = 4mA + DC (Isw/60 + Isw x 0.004)
Isw = switch current
DC = switch duty cycle
Switch power dissipation is given by:
Psw = (ISW)2 x Rsw x DC
Rsw = output switch "On" resistance
Total power dissipation of the die is the sum of
current times supply voltage plus switch power:

suppl~

PO(TOTAL) = (liN x VIN) + Psw
Choosing the Inductor
For most applications the inductor will fall in the range 0
to 22~. Lower values are chosen to reduce physi
cal size of the inductor. Higher values allow more outpu
current because they reduce peak current seen by thl
power switch, which has a 1.5A limit. Higher values alsl
reduce input ripple voltage and reduce core loss.
2.2~

When choosing an inductor you might have to conside
maximum load current, core and copper losses, allowabll
component height, output voltage ripple, EMI, faul

LT1372/LT1377
PPLICATlons InFORmATion
Irrent in the inductor, saturation, and of course, cost.
Ie following procedure is suggested as away of handling
ese somewhat complicated and conflicting requirements.
Assume that the average inductor current for a boost
converter is equal to load current times VourlVlN and
decide whether or not the inductor must withstand
continuous overload conditions. If average inductor
current at maximum load current is 0.5A, for instance,
a 0.5A inductor may not survive a continuous 1.5A
overload condition. Also be aware that boost converters are not short circuit protected, and that under
output short conditions, inductor current is limited only
by the available current of the input supply.
Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, especially with smaller inductors and lighter loads, so don't
omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall in between
somewhere. The following formula assumes continuous mode operation but it errors only slightly on the
high side for discontinuous mode, so it can be used for
all conditions.
IpEAK = lOUT x VOUT + VIN(VOUT- VIN)
VIN
2(f)(L)(VOUT)
VIN = Minimum Input Voltage
f = 500kHz Switching Frequency (LT1372) or
1MHz Switching Frequency (LT1377)
Decide if the design can tolerate an "open" core geometry like a rod or barrel, which have high magnetic field
radiation, or whether it needs aclosed core like atoroid
to prevent EMI problems. One would not want an open
core next to a magnetic storage media for instance!
This is atough decision because the rods or barrels are
temptingly cheap and small, and there are no helpful
guidelines to calculate when the magnetic field radiation will be a problem.

l7lJD~

4. Start shopping for an inductor which meets the requirements of core shape, peak current (to avoid
saturation), average current (to limit heating) and fault
current.lfthe inductor gets too hot, wire insulation will
melt and cause turn-to-turn shorts. Keep in mind that
all good things like high efficiency, low profile and high
temperature operation will increase cost, sometimes
dramatically.
5. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology application
department if you feel uncertain about the final choice.
They have experience with a wide range of inductor
types and can tell you about the latest developments in
low profile, surface mounting, etc.
Output Capacitor

The output capacitor is normally chosen by its effective
series resistance, (ESR), because this is what determines
output ripple voltage. At 500kHz, any polarized capacitor
is essentially resistive. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range for typical LT1372 and LT1377 applications is
0.050 to 0.50. Atypical output capacitor is an AVX type
TPS, 22J.IF at 25V, with aguaranteed ESR less than 0.20.
This is a"D" size surface mount solid tantalum capacitor.
TPS capacitors are specially constructed and tested for
low ESR, so they give the lowest ESR for agiven volume.
To further reduce ESR, multiple output capacitors can be
used in parallel. The value in microfarads is not particularly critical, and values from 22J.IF to greater than 500J.IF
work well, but you cannot cheat mother nature on ESR.
If you find atiny 22J.IF solid tantalum capacitor, it will have
high ESR, and output ripple voltage will be terrible. Table
1 shows some typical solid tantalum surface mount
capacitors.

4-317

LT1372/LT1377
APPLICATions InFoRmATion
Table 1. Surface Mount Solid Tantalum Capacitor
ESR and Ripple Current
ESR (MAX n)

RIPPLE CURRENT (A)

0.1 to 0.3
0:7 to 0.9

0.7 to 1.1
0.4

AVX TPS, Sprague 593D
AVXTAJ
CCASE SIZE

0.1 to 0.3
0.9 to 2.0

0.7 to 1.1
0.36 to 0.24

AVXTPS
AVXTAJ

0.2 (Typ)
1.8 to 3.0

0.5 (Typ)
0.22 to 0.17

2.5 to 10

0.16 to 0.08

ECASE SIZE
AVX TPS, Sprague 593D
AVXTAJ

oCASE SIZE

B CASE SIZE
AVXTAJ

Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true and type TPS capacitors are
specially tested for surge capability, but surge ruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges,
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
Single inductor boost regulators have large RMS ripple
current in the output capacitor, which must be rated to
handle the current. The formula to calculate this is:
Output Capacitor Ripple Current (RMS)

!DC

IRIPPLE (RMS) ::: lOUT Vf=DC

.
IvOUT-VIN
::: lOUT V' VIN

I
- O.3(VIN)(VOUT- VIN)
RIPPLE (f)(L)(VOUT)
f ::: 500kHz Switching frequency (LT1372) or,
1MHz Switching frequency (LT1377)
.
The input capacitor can see avery high surge current whe
a battery or high capacitance source is connected "liVE
and solid tantalum capacitors can fail under this conditior
Several manufacturers have developed a line of soli
tantalum capacitors specially tested for surge capabilil
(AVX TPSseries, for instance), but even these units rna
fail if the input voltage approaches the maximum voltag
rating ofthe capacitor. AVX recommends derating capac
tor voltage by 2:1 for high surge applications. Ceramic an
aluminum electrolytic capacitors may also be used an
have a high tolerance to turn-on surges.
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are no'
becoming available in smaller case sizes. These are temp:
ing for switching regulator use because of their very 1m
ESR. Unfortunately, the ESR is so low that it can caus
loop stability problems. Solid tantalum capacitor ES'
generates aloop "zero" at 5kHz to 50kHz that is instrumer
tal in giving acceptable loop phase margin. Ceramic cc
pacitors remain capacitive to beyond 300kHz and usuall
resonate with their ESL before ESR becomes effectivi
They are appropriate for input bypassing because of the
high ripple current ratings and tolerance otturn-on surge~
LinearTechnology plans to issue aDesign Note on the us
of ceramic capacitors in the near future.

Input Capacitors

Output Diode

The input capacitor of aboost converter is less critical due
to the factthatthe input current waveform is triangular and
does not contain large squarewave currents as is found in
the output capacitor. Capacitors in the range of 10W to
100wwith an ESR ofO.3n or less work well uptofull1.5A
switch current. Higher ESR capacitors may be acceptable
at low switch currents. Input capacitor ripple current for
boost converter is :

The suggested output diode (01) is a1N5818 Schottky (
its Motorola equivalent, MBR130.lt is rated at 1A averag
forward current and 30V reverse voltage. Typical forwar
voltage is 0.42V at 1A. The diode conducts current onl
during switch off time. Peak reverse voltage for bom
converters is equal to regulator output voltage. Averag
forward current in normal operation is equal to outPI
current.

4-318

LT1372/LT1377
~PPLICATlons

InFORmATion

:requency Compensation
_oop frequency compensation is performed on the output
)f the error amplifier (Ve pin) with a series RC network.
-he main pole is formed by the series capacitor and the
)utput impedance (",500kQ) of the error amplifier. The
)ole falls in the range of 2Hz to 20Hz. The series resistor
:reates a "zero" at 1kHz to 5kHz, which improves loop
;tability and transient response. A second capacitor,
ypically one-tenth the size of the main compensation
:apacitor, is sometimes used to reduce the switching
requency ripple on the Ve pin. Ve pin ripple is caused by
)utput voltage ripple attenuated by the output divider and
nultiplied by the error amplifier. Without the second
:apacitor, Ve pin ripple is:

(magnetic) radiation is minimized by keeping output diode, switch pin, and output bypass capacitor leads as
short as possible. Efield radiation is kept low by minimizing the length and area of all traces connected to the switch
pin. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling.
The high speed switching current path is shown schematically in Figure 3. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode, and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.

J r';·T.,;,I-~c-y
SWITCH

- . . . . .- . . . .

Ve Pin Ripple = 1.245(VRIPPLE)(gm)(Re)
(VOUT)
VRIPPLE = Output ripple (Vp_p)
gm = Error amplifier transconductance
(",1500llmho)
Re =Series resistor on Vc pin
VOUT = DC output voltage
prevent irregular switching, Ve pin ripple should be
:ept below 50mVp_p. Worst-case Ve pin ripple occurs at
naximum output load current and will also be increased
r poor quality (high ESR) output capacitors are used. The
,ddition of a O.0047J.1f capacitor on the Ve pin reduces
witching frequency ripple to only a few millivolts. A low
'alue for Re will also reduce Ve pin ripple, but loop phase
nargin may be inadequate.
'0

-VOUT

CIRCULATING
PATH

"':'"

LT1372°F03

Figure 3

More Help
For more detailed information on switching regulator
circuits, please see Application Note 19. Linear Technology also offers acomputersoftware program, SwitcherCAD,
to assist in designing switching converters. SwitcherCAD
will be updated in late 1995 forthe LT1372 and LT1377.ln
addition, our applications department is always ready to
lend a helping hand.

twitch Node Considerations
or maximum efficiency, switch rise and fall time are
nade as short as possible. To prevent radiation and high
requency resonance problems, proper layout of the comlonents connected to the switch node is essential. Bfield

L7lJfJ~

4-319

LT1372/LT1377
TYPICAL APPLICATions
Positive-to-Negative Converter with Direct Feedback

Dual Output Flyback Converter with Overvoltage Protection
R2
1.21k

Rl
13k

'-'--+4t-.....-- -VOUl
C3
O.0047J!F

R4 -15V
12.1k

T

L...-_ _ _ _ _... 1%
LT13720TAQ3

C3
0.0047J!F

]

T -:

C2
0.047J!F
R3
2k
'DALE LPE-4841-100MB (605) 665-9301

R5
2.49k
1%

90% Efficient CCFl Supply
low Ripple 5V to -3V "Cuk"t Converter

~e~~~--------------~

5mAMAX
Dl
lN4148

VOUT
~--....- -....- -.....- -3V

250mA

VIN
4.5V ~_--",-"""":"""--~~--~!..--.!.f-J
T030V

Rl
lk
1%
Cl
22J!F
10V
C3
47J!F
16V

2.7VTO
5.5V

-:11----.

'SUMIDA CLS62-100L
"MOTOROLA MBR0520LT3
tpATENTS MAY APPLY

22k
lN4148
OPTIONAL REMOTE
DIMMING
Cl = W1MA MKP-20
L1 = COILCRAFT DT3316-333
Ql. Q2 = zmx ZlX849 OR ROHM 2SC5001
Tl = COILTRONICS CTX 110609
'= 1% FILM RESISTOR
DO NOT SUBSTTME COMPONENTS
COILTRONICS (407) 241-7876
COILCRAFT (708) 639-8400

4-320

CCFL BACKLIGHT APPLICATION CIRCUITS
CONTAINED IN THIS DATA SHEET ARE
COVERED BY u.S. PATENT NUMBER 5408112
AND OTHER PATENTS PENDING

LT1372/LT1377
TYPICAL APPLICATions
2 LHon Cell to 5V SEPIC Converter

C1

C3

33~F

~~e~F

20V .

C1 ~ AVX TPSD 336M020R0200
C2 ~ TOKIN 1E105ZV5U-C103-F
C3 ~ AVX TPSD107M010R0100
'SINGlE INDUCTOR WITH TWO WINDINGS
COllTRONICS ClJ(10-1
tMA)( lOUT

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1172

100kHz 1.25A Boost Switching Regulator

LTC"'1265

12V 1.2A Monolithic Buck Converter

Good for Up to VIN = 40V
Converts 5V to 3.3V at 1A with 90% Efficiency

LT1302

Micropower 2A Boost Converter

Converts 2V to 5V at 600mA in S08 Packages

LT1376

500kHz 1.5A Buck Switching Regulator

Steps Down from Up to 25V Using 4.7~ Inductors

LT1373

Low Supply Current 250kHz 1.5A Boost Switching Regulator

90% Efficient Boost Converter with Constant Frequency

4-321

~7~JO~~V~--2-50-k-H-Z-LO-W-S-UP-P-I-y-c-L~-:r-!7-n~
High Efficiency
1.5A Switching Regulator
DESCRIPTiOn

FEATURES
•
•
•
•
•
•
•
•
•
•
•

1mA 10 at 250kHz
Uses Small Inductors: 15J11f
All Surface Mount Components
Only 0.6 Square Inch of Board Space
Low Minimum Supply Voltage: 2.7V
Constant Frequency Current Mode
Current Limited Power Switch: 1.5A
Regulates Positive or Negative Outputs
Shutdown Supply Current: 121JA Typ
Easy External Synchronization
8-Pin SO or PDIP Packages

APPLICATions
•
•
•
•
•

Boost Regulators
CCFL Backlight Driver
Laptop Computer Supplies
Multiple Output Flyback Supplies
Inverting Supplies

The LT®1373 is a low supply current high frequency
current mode switching regulator. It can be operated in all
standard switching configurations including boost, buck,
fly back, forward, inverting and "Cuk." A 1.5A high efficiency switch is included on the die, along with all oscillator, control, and protection circuitry. All functions of the
LT1373 are integrated into 8-pin SO/PDIP packages.
Compared to the 500kHz LT1372, which draws 4mA of
quiescent current, the LT1373 switches at 250kHz, typically consumes only 1rnA and has higher efficiency. High
frequency switching allows for small inductors to be used.
All surface mount components consume less than 0.6
square inch of board space.
New design techniques increase flexibility and maintain
ease of use. Switching is easily synchronized to an external logic level source. A logic low on the shutdown pin
reduces supply current to 121JA. Unique error amplifier
circuitry can regulate positive or negative output voltage
while maintaining simple frequency compensation techniques. Nonlinear error amplifier transconductance reduces output overshoot on start-up or overload recovery.
Oscillator frequency shifting protects external components during overload conditions.
LT, LTC and LT are l1l\listered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn

12V Output Efficiency

SV-to-12V Boost Converter

100
V1N =5V
1= 250kHz

Dl
90

,/

i!':.

80

i

70

~

Cl"
22~

60

...,

1I

I

I

50
1

4-322

10
100
OUTPUT CURRENT (mA)

1000

LT1373
ABSOLUTE mAXimum RATinGS
Supply Voltage ....................................................... 30V
Switch Voltage ............................................. ........... 35V
SIS Pin Voltage.. ...... ......................... .............. ........ 30V
Feedback Pin Voltage (Transient, 10ms) .............. ±10V
Feedback Pin Current........................................... 10mA
Negative Feedback Pin Voltage
(Transient, 10ms) ............................................. ±10V
Operating Junction Temperature Range
Operating ............................................ O°C to 125°C *
Short Circuit ......................................... O°C to 150°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATion
ORDER PART
NUMBER

TOP VIEW

"o'~

FB 2
NFB 3
SIS 4

N8 PACKAGE
8-LtAD PDlP

LT1373CN8
LT1373CS8

GND
GND s
5 VIN
7

6

S8 PACKAGE
8-LEAD PLASTIC SO

S8 PART MARKING

TJMAX= 125°C. 9JA= 130°C/W (N8)
TJMAX =125°C. 9JA= 120°C/W (SS)

1373

Consult factory for Industrial and Military grade parts.

'Units shipped prior to Date Code 9552 are rated at 100°C maximum
operating temperature.

ELECTRICAL CHARACTERISTICS
VIN = 5V, Vc = O.6V, VFB = VREF, Vsw, SIS and NFB pins open, unless otherwise noted.
SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VREF

Reference Voltage

Measured at Feedback Pin
Vc = 0.8V

1.230
1.225

1.245
1.245

1.260
1.265

V
V

IFB

Feedback Input Current

VFB = VREF

50

150
275

nA
nA

Reference Voltage Line Regulation

2.7V 5, VIN 5, 25V, Vc = 0.8V

0.01

0.03

%N

VNFR

Negative Feedback Reference Voltage

Measured at Negative Feedback Pin
Feedback Pin Open, Vc = 0.8V

INFB

Negative Feedback Input Current

VNFB = VNFR
2.7V 5, VIN 5, 25V, Vc = 0.8V

Negative Feedback Reference Voltage
Line Regulation
gm

Error Amplifier Transconductance

Alc= ±51JA

Error Amplifier Source Current

VFB = VREF -150mV, Vc = 1.5V

Error Amplifier Sink Current

VFB = VREF + 150mV, Vc = 1.5V
High Clamp, VFB = 1V
Low Clamp, VFB = 1.5V

Error Amplifier Clamp Voltage
Av
f

•
•
•
•
•

•
•
•
•

-12

250
150
25
1.70
0.25

Error Amplifier Voltage Gain

-2.490
-2.490
-7

-2

0.01

0.05

IJA
%N

375

500
600

IlIT1ho
IlIT1ho

V
V

50

90

850

1500

IJA
IJA

1.95
0.40

2.30
0.52

V
V

250

VN

Vc Pin Threshold

Duty Cycle = 0%

0.8

1

1.25

V

Switching Frequency

2.7V 5, VIN 5, 25V

225
210

250
250

275
290

kHz
kHz

500

ns

0.85

n

Maximum Switch Duty Cycle
Switch Current Limit Blanking Time
BV

Output Switch Breakdown Voltage

2.7V 5, VIN 5, 25V

VSAT

Output Switch "On" Resistance

Isw= 1A

•

•
•
•

90

95
340

35

%

47
0.5

V

4-323

LT1373
ELECTRICAL CHARACTERISTICS
VIN =5V, Vc =O.6V, VFB =VREF, VSW, SIS and MFB pins open, unless otherwise noted.
SYMBOL

PARAMETER

CONDITIONS

ILiM

Switch Current Limit

Duty Cycle =50%
Duty Cycle =80% (Note 1)

.6.IIN
.6.lsw

Supply Current Increase During Switch On-Time

•
•

MIN

TYP

MAX

UNITS

1.5
1.3

1.9
1.7

2.4
2.2

A
A

10

20

mAlA

Control Voltage to Switch Current
Transconductance

2

Minimum Input Voltage
10

Supply Current

2.7V:$ VIN :$ 25V

Shutdown Supply Current

2.7V:$ VIN :$ 25V, VS/S:$ 0.6V

Shutdown Threshold

2.7V :$ VIN :$ 25V

Shutdown Delay

SIS Pin Input Current

OV:$ VS/S:$ 5V

Synchronization Frequency Range

•
•
•
•
•
•
•

AlV

2.4
1

2.7
1.5

mA

!!A

12

30

0.6

1.3

2

5
-10

12

100

300

V

V
~

12

!!A

360

kHz

The. denotes specifications which apply over the full operating
temperature range.
Note 1: For duty cycles (DC) between 50% and 90%, minimum
guaranteed switch current is given by ILiM = 0.667 (2.75 - DC).

TYPICAL PERFORmAnCE CHARAOERISTICS
Switch Saturation Voltage
vs Switch Current
1.0

~

w

(!l

150°C
100°C)('

0.9
0.8

~

0.7

>
z

0.6

~

0

~

0

~ 0.5
a;;
:::J
!;;: 0.4
en

:J:

'"~

en

0.1

vx

25~

v yV

/ 1/
/

fi '/ ./ -55°C
A /": , /

0.3
0.2

Switch Currentlimil
vs Duty Cycle

~~
~~

,

o
o

""

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SWITCH CURRENT (A)

Minimum Input Voltage
vs Temperature

3.0

g

2.5

2.8
25 JC AJO
r""'=~50C -

t:
~ 2.0

~

b~:i:::i==t=::t::t=l:::]

1.0

~ 2.2

1--+---+-+-+-+---+--+---1

0.5

2.0

1-+--+-+-+-+--+-+--1

-55°C

~ 1.5

0:

:::>

~

§ 2.6 1--+---+-+-+-+---+--+---1
2.4

!2

'"~

1--+---+-+-+-+---+--+---1

~
...>

:::>

o

o

10 20 30 40 50 60 70 80 90 100
OUTY CYCLE (%)

1.8 '----'--'----'--'---'--'----'--'
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (OC)
LT1373-G03

4-324

LT1373
TYPICAL PERFORmAnCE CHARAnERISTICS
Shutdown Delay and Threshold
vs Temperature
20

2.0

a:

18

1.8

2:-

16

~

14

~

12

z

10

CI

s:0

........

...........

. . . . r--...

1.0

....... -=::::::

f- SHUTDOWN

::>

:I:
UJ

N

0.4

:s

5
~

-50 -25

0

0

3

~

f-

al
a:

I

a:

<>
f-

I

::>
0-

~

-1

z
0::

-2

.J

I
I

-4
-5

-1

0

o

1

2

3

4

5

"'"-

ffi

~ -25

25 50 75 100 125 150
TEMPERATURE (OC)

-0.3

6

7

8

I

80

g

§l 200

'"
z

40

20
10

SIS PIN VOLTAGE (V)

l>.1 (Vc)
gm = l>.V (FB)

r--.

:g 400
~
w

I

70

1ll

0.1

Error Amplifier Transconductance
vs Temperature

60

9

-0.2
-0.1
VREF
FEEDBACK PIN VOLTAGE (V)

500

90

30

\

-75

0

100

~

"

... &

u:

50

a:

J

~ -3

25

~
a'::>i
53

~

::>

125°C

25°C I
~'-55'C

::>

110

~
~

"-

50

Switching Frequency
vs Feedback Pin Voltage

VIN = 5V

I I

I'\:

f-- f--

~ -50
ffi

0
-50 -25

25 50 75 100 125 150
TEMPERATURE (OC)

75

:::J

~ 0.5

SIS Pin Input Current
vs Voltage

~

-

1.0

:;;
Z
~

0.2

o

..- ./'

Z
o
a:

Ri

?!
CJ

!S
<>
:=5

2.0

~ 1.5

--i

:I:

0.6

al
a:

o

en
0.8 :I:

DELAY

0
f-

~
~

1.2 :;:
z
~

100

~
f-

'SYNC = 330kHz

~ 2.5

0

.......:':>

3.0

d..

en
1.6 :I:
c:
104 --i
CJ

SJUTDhWN
THRESHOLD

..................

Error Amplifier Output Current
vs Feedback Pin Voltage

Minimum Synchronization
Voltage vs Temperature

...........
...........

!i;l 300

r--.

::J

o

<>
en

z

«

g:

o

100

o

-50 -25

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FEEDBACK PIN VOLTAGE (V)

0

25 50 75 100 125 150
TEMPERATURE (OC)

LT1373·GOB

Vc Pin Threshold and High
Clamp Voltage vs Temperature

Negative Feedback Input
Current vs Temperature

Feedback Input Current
vs Temperature

2.4

400

~

VFB = VREF

2.2

VCI

2.0

HIG~ CLA~P

~ 350

o
-2

~

300

§ -6

~ 1.6

1::'
::J

250

!3
0-

~ 1.4
>
;; 1.2

50-

200

~ 1.8

""
"-

~ 1.0

0.8

<>

<>

- r--- -

I--I--

0.6

004
-50 -25

0

eli

"" 150

25 50 75 100 125 150
TEMPERATURE (OC)

~

53

100

~

50

o

-8

~ -10

<>

~

Vc THRESHOLD

VNFB = VNFR

as -4
a:
~

,.-

..-

,..;

-12

CI

--

~ -14

............ ""'"

-50 -25

I

~ -16
!;;:

ffi
z

0

25 50 75 100 125 150
TEMPERATURE (OC)

-18

-20
-50 -25

0

25 50 75 100 125 150
TEMPERATURE (OC)

4-325

•

LT1373

Pin FunCTions
Vc (Pin 1): Compensation Pin. The Vc pin is used for
frequency compensation, current limiting and soft start. It
is the output of the error amplifier and the input of the
current comparator. Loop frequency compensation can be
performed with an RC network connected from the Vc pin
to ground.
FB (Pin 2): The feedback pin is used for positive output
voltage sensing and oscillator frequency shifting. It is the
inverting input to the error amplifier. The noninverting
input of this amplifier is internally tied to a 1.245V
reference.
NFB (Pin 3): The negative feedback pin is used for negative
output voltage sensing. It is connected to the inverting
input of the negative feedback amplifier through a 400k
source resistor.

SIS (Pin 4): Shutdown and Synchronization Pin. The SIS
pin is logic level compatible. Shutdown is active low and
the shutdown threshold is typically 1.3V. For normal
operation, pull the SIS pin high, tie it to VIN or leave it
floating. To synchronize switching, drive the SIS pin between 300kHz and 360kHz.

(Pin 5): Input Supply Pin. Bypass VIN with 10W or
more. The part goes into undervoltage lockout when VIN
drops below 2.5V. Undervoltage lockout stops switching
and pulls the Vc pin low.
VIN

GND S (Pin 6): The ground sense pin is a "clean" ground.
The internal reference, error amplifier and negative feedback amplifier are referred to the ground sense pin. Connect it to ground. Keep the ground path connection to the
output resistor divider and the Vc compensation network
free of large ground currents.
GND (Pin 7): The ground pin is the emitter connection of
the power switch and has large currents flowing through it.
It should be connected directly to a good quality ground
plane.
Vsw (Pin 8): The switch pin is the collector of the power
switch and has large currents flowing through it. Keep the
traces to the switching components as short as possible to
minimize radiation and voltage spikes.

BLOCK DIAGRAm
SW
SIS

NFB --'Wv--...-i

FB--'-"--i
0.08n

-

GND SENSE

4-326

GND

LT1S73'BD

LT1373
OPERATion
The LT1373 is a current mode switcher. This means that
switch duty cycle is directly controlled by switch current
rather than by output voltage. Referring to the block
diagram, the switch is turned "On" at the start of each
oscillator cycle. It is turned "Off" when switch current
reaches a predetermined level. Control of output voltage
is obtained by using the output of avoltage sensing error
amplifier to set current trip level. This technique has
several advantages. First, it has immediate response to
input voltage variations, unlike voltage mode switchers
which have notoriously poor line transient response.
Second, it reduces the 90° phase shift at mid-frequencies
in the energy storage inductor. This greatly simplifies
closed-loop frequency compensation under widely varying input voltage or output load conditions. Finally, it
allows simple pulse-by-pulse current limiting to provide
maximum switch protection under output overload or
short conditions. A low dropout internal regulator provides a 2.3V supply for all internal Circuitry. This low
dropout design allows input voltage to vary from 2.7V to
25V with virtually no change in device performance. A
250kHz oscillator is the basic clock for all internal timing.
It turns "On" the output switch via the logic and driver
circuitry. Special adaptive anti-sat circuitry detects onset
of saturation in the power switch and adjusts driver
current instantaneously to limit switch saturation. This
minimizes driver dissipation and provides very rapid
turn-off of the switch.
A1.245V bandgap reference biases the positive input of
the error amplifier. The negative input of the amplifier is
brought out for positive output voltage sensing. The error
amplifier has nonlinear transconductance to reduce out-

put overshoot on start-up or overload recovery. When
the feedback voltage exceeds the reference by 40mV,
error amplifier transconductance increases ten times,
which reduces output overshoot. Thefeedback input also
invokes oscillator frequency shifting, which helps protect components during overload conditions. When the
feedback voltage drops below 0.6V, the oscillator frequency is reduced 5:1. Lower switching frequency allows
full control of switch current limit by reducing minimum
switch duty cycle.
Unique error amplifier Circuitry allows the LT1373 to
directly regulate negative output voltages. The negative
feedback amplifier's 400k source resistor is brought out
for negative output voltage sensing. The NFB pin regulates
at -2.49V while the amplifier output internally drives the
FB pin to 1.245V. This architecture, which uses the same
main error amplifier, prevents duplicating functions and
maintains ease of use. (Consult Linear Technology Mar- . .
keting for units that can regulate down to -1.25V.)
..
The error signal developed at the amplifier output is
brought out externally. This pin (Vc) has three different
functions. It is used for frequency compensation, current
limit adjustment and soft starting. During normal regulator operation this pin sits at a voltage between 1V (low
output current) and 1.9V (high output current). The error
amplifier is acurrent output (gm) type, so this voltage can
be externally clamped for lowering current limit. likewise, acapaCitor coupled external clamp will provide soft
start. Switch duty cycle goes to zero ifthe Vc pin is pulled
below the control pin threshold, placing the LT1373 in an
idle mode.

APPLICATions InFORmATion
Positive Output Voltage Setting

The LT1373 develops a 1.245V reference (VREF) from the
FB pin to ground. Output voltage is set by connecting the
FB pin to an output resistor divider (Figure 1). The FB pin
iJias current represents a small error and can usually be
ignored for values of R2 up to 25k. The suggested value for
R2 is 24.9k. The NFB pin is normally left open for positive
3utput applications. Positive fixed voltage versions are
~vailable. (Consult Linear Technology Marketing.)

.L7lJ!J~

VOUT

:d

FB
PIN

R1

VOUr= VREF (1 +
VOUT

~)
)

R1 =R2 (1.245-1

VREFL-:-R2

Figure 1. Positive Output Resistor Divider

4-327

LT1373
APPLICATions InFoRmATion
Negative Output Voltage Setting
The LT1373 develops a- 2.49V reference (VNFR) from the
NFB pin to ground. Output voltage is set by connecting the
NFB pin to an output resistor divider (Figure 2). The -7JJA
NFB pin bias current (INFB) can cause output voltage errors
and should not be ignored. This has been accounted for in
the formula in Figure 2. The suggested value for R2 is
2.49k. The FB pin is normally left open for negative output
applications.

I1

NFB -vou:l

NFB
PIN

IVOUTI-2.49
Rl =

(2R~9) + (7 x 10-6)

VNFR
LT1373°F02

Figure 2. Negative Output Resistor Divider

Dual Polarity Output Voltage Sensing
Certain applications benefit from sensing both positive
and negative output voltages. One example is the Dual
Output Flyback Converter with Overvoltage Protection
circuit shown in the Typical Applications section. Each
output voltage resistor divider is individually set as described above. When both the FB and NFB pins are used,
the LT1373 acts to prevent either output from going
beyond its set output voltage. For example in this application, if the positive output were more heavily loaded than
the negative, the negative output would be greater and
would regulate at the desired set-pOint voltage. The positive output would sag slightly below its set-point voltage.
This technique prevents either output from going unregulated high at no load.
Shutdown and Synchronization
The dual function SIS pin provides easy shutdown and
synchronization. It is logic level compatible and can be
pulled high, tied to VIN or left floating for normal operation.
A logic low on the SIS pin activates shutdown, reducing
the part's supply currentto 12JJA. Typical synchronization
range is from 1.05 and 1.8 times the part's natural switching frequency, but is only guaranteed between 300kHz and
360kHz. A 12J.1S resetable shutdown delay network guar-

4-328

Caution should be used when synchronizing above
330kHz because at higher sync frequencies the amplitude of the internal slope compensation used to prevent
subharmonic switching is reduced. This type of
subharmonic switching only occurs when the duty cycle
of the switch is above 50%. Higher inductor values wi"
tend to eliminate problems.
Thermal Considerations

-Vour= VNFR(l + ~) + INFB (Rl)

--

R2

antees the part wi" not go into shutdown while receiving
a synchronization signal.

Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause excessive die temperatures. The packages are rated at 120°C/W
for SO (S8) and 130°C/W for PDIP (N8).
Average supply current (including driver current) is:
liN = 1rnA + DC (lsw/60 + Isw x 0.004)
Isw = switch current
DC = switch duty cycle
Switch power dissipation is given by:
Psw = (ISW)2 x Rsw x DC
Rsw = output switch "On" resistance
Total power dissipation of the die is the sum of supply
current times supply voltage plus switch power:
Po (TOTAL) = (lIN x VIN) + Psw
Choosing the Inductor
For most applications the inductor wi" fa" in the range of
1O~ to 50~. Lower values are chosen to reduce physical
size of the inductor. Higher values allow more output
current because they reduce peak current seen by the
power switch which has a 1.5A limit. Higher values also
reduce input ripple voltage, and reduce core loss.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, a"owable
component height, output voltage ripple, EMI, fault current in the inductor, saturation, and of course, cost. The
following procedure is suggested as a way of handling
these somewhat complicated and conflicting requirements.

LT1373
r-IPPLICATlons InFORmATion
1. Assume that the average inductor current (for a boost
converter) is equal to load current times VouTNIN and
decide whether or not the inductor must withstand
continuous overload conditions. If average inductor
current at maximum load current is O.SA, for instance,
a O.SA inductor may not survive a continuous 1.SA
overload condition. Also, be aware that boost converters are not short-circuit protected, and that under
output short conditions, inductor current is limited only
by the available current of the input supply.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be Significantly higher than output current, especially with smaller inductors and lighter loads, so don't
omit this step. Powered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall in between
somewhere. The following formula assumes continuous mode operation, but it errors only slightly on the
high side for discontinuous mode, so it can be used for
all conditions.
IpEAK = lOUT x VOUT + VIN (VOUT - VIN)
VIN
2(f)(L)(VOUT)
VIN = minimum input voltage
f = 2S0kHz switching frequency
3. Decide if the design can tolerate an "open" core geometry like a rod or barrel, which have high magnetic field
radiation, or whether it needs aclosed core like atoroid
to prevent EMI problems. One would not want an open
core next to a magnetic storage media for instance!
This is atough decision because the rods or barrels are
temptingly cheap and small, and there are no helpful
guidelines to calculate when the magnetic field radiation will be a problem.
4. Start shopping for an inductor which meets the requirements of core shape, peak current (to avoid saturation),
average current (to limit heating), and fault current, (if
the inductor gets too hot, wire insulation will melt and
cause turn-to-turn shorts). Keep in mind that all good
things like high efficiency, low profile and high temperature operation will increase cost, sometimes dramatically.

.L7lJ!J~

S. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology application
department if you feel uncertain about the final choice.
They have experience with a wide range of inductor
types and can tell you about the latest developments in
low profile, surface mounting, etc.
Output Capacitor
The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. At SOOkHz, any polarized capacitor
is essentially resistive. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range for typical LT1373 applications is O.OSQ to O.SQ. A
typical output capacitor is an AVX type TPS, 22J.lF at 2SV,
with a guaranteed ESR less than O.2Q. This is a "0" size
surface mount solid tantalum capacitor. TPS capacitors •
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. To further reduce
ESR, multiple output capacitors can be used in parallel.
The value in microfarads is not particularly critical and
values from 22~ to greaterthan SOO~ work well, but you
cannot cheat mother nature on ESR. If you find atiny 22~
solid tantalum capacitor, it will have high ESR and output
ripple voltage will be terrible. Table 1 shows some typical
solid tantalum surface mount capacitors.
Table 1. Surface Mount Solid Tantalum Capacitor
ESR and Ripple Current
E CASE SIZE
AVX TPS, Sprague 5930
AVXTAJ

ESR (MAX 0)

RIPPLE CURRENT (A)

0.1 to 0.3
0.7 to 0.9

0.7 to 1.1
0.4

0.1 to 0.3
0.9 to 2.0

0.7101.1
0.36 to 0.24

0.2 (Typ)
1.8to 3.0

0.5 (Typ)
0.22 to 0.17

2.5 to 10

0.16 to 0.08

oCASE SIZE
AVX TPS, Sprague 5930
AVXTAJ
CCASE SIZE
AVX TPS
AVX TAJ
B CASE SIZE
AVXTAJ

Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true and type TPS capacitors are

4-329

LT1373
APPLICATions InFoRmATion
specially tested for surge capability; butsurge ruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges,
which do .not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
Single inductor boost regulators have large RMS ripple
current in the output capacitor, which must be rated to
handle the current. The formula to calculate this is:
Output Capacitor Ripple Current (RMS)

. (DC
IRIPPLE (RMS) = lOUT Vf=[)C
_I
/VOUT - VIN
- OUT V VIN

Input Capacitors
The input capacitor of a boost converter is less critical due
to the fact that the input current waveform is triangular,
and does not contain largesquarewave currents as is
found in the output capacitor. Capacitors in the range of
1O~ to 1OO~ with an ESR (effective series resistance) of
0.3n or less work well up to a full 1.5A switch current.
Higher ESR capacitors may be acceptable at low switch
currents. Input capacitor ripple current for boost converter is:
I
O.3(VIN)(VOUT - VIN)
RIPPLE =
(f)(L)(VOUT)
f =250kHz switching frequency
The input capacitor can see avery high surge current when
a battery or high capacitance source is connected "live",
and solid tantalum capacitors can fail under this condition.
Several manufacturers have developed a line of solid
tantalum capacitors specially tested for surge capability
(AVX TPS series, for instance), but even these units may
fail if the input voltage approaches the maximum voltage
rating of the capacitor. AVX recommends derating capacitor voltage by 2:1 for high surge applications. Ceramic and
aluminum electrolytic capacitors may also be used and
have a high tolerance to turn-on surges.

4-330

Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates aloop "zero" at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
They are appropriate for input bypassing because of their
high ripple current ratings and tolerance oftum-on surges .
LinearTechnology plans to issue aDesign Note on the use
of ceramic capaCitors in the near future.

Output Diode
The suggested output diode (D1) is a 1N5818 Schottky or
its Motorola equivalent, MBR130. It is rated at 1A average
forward current and 30V reverse voltage. Typical forward
voltage is 0.42V at 1A. The diode conducts current only
during switch-off time. Peak reverse voltage for boost
converters is equal to regulator output voltage. Average
forward current in normal operation is equal to output
current.

Frequency Compensation
Loop frequency compensation is performed on the output
ofthe error amplifier (Vc pin) with aseries Rc network. The
main pole is formed by the series capaCitor and the output
impedance ('" 1Mn) of the error amplifier. The pole falls in
the range of 5Hz to 30Hz. The series resistor creates a
"zero" at 2kHzto 10kHz, which improves loop stability and
transient response. Asecond capaCitor, typically one tenth
the size ofthe main compensation capacitor, is sometimes
used to reduce the switching frequency ripple on the Vc
pin. Vc pin ripple is caused by output voltage ripple
attenuated by the output divider and multiplied by the error
amplifier. Without the second capacitor, Vc pin ripple is:
'R' I
1.245(VRIPPLE)(gm)(Rc)
Vc PIn
Ipp e =
V
OUT

LT1373
APPLICATions InFoRmATion
VRIPPLE = output ripple (Vp_p)
gm =error amplifier transconductance (",375J.U1lho)
Rc = series resistor on Vc pin
VOUT = DC output voltage
To prevent irregular switching, Vc pin ripple should be
kept below 50mVp_p. Worst-case Vc pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a O.0011JF capacitor on the Vc pin reduces
switching frequency ripple to only a few millivolts. A low
value for Rc will also reduce Vc pin ripple, but loop phase
margin may be inadequate.

The high speed switching current path is shown schematically in Figure 3. Minimum lead length in this path is
essential to ensure clean switching and low EM\, The path
including the switch, output diode and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.

HIGH
FREQUENCY
CIRCULATING
PATH

Switch Node Considerations
For maximum efficiency, switch rise and fall time are made
as short as possible. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the switch node is essential. B field
(magnetic) radiation is minimized by keeping output diode, switch pin and output bypass capacitor leads as short
as possible. Efield radiation is kept low by minimizing the
length and area of all traces connected to the switch pin.
A ground plane should always be used under the switcher
circuitry to prevent interplane coupling.

Figure 3

More Help
•
For more detailed information on switching regulator
circuits, please see AN19. Linear Technology also offers a
computer software program, SwitcherCAD, to assist in
designing switching converters. SwitcherCAD will be updated in late 1995 forthe LT1373.ln addition, our applications department is always ready to lend a helping hand.

TYPICAL APPLICATiOnS
Positive-to-Negative Converter with Direct Feedback

Dual Output Flyback Converter with Overvollage Protection
R2
1.21k

]

R1
13k

C2
O.D1I1F
R1
5k
'COILTRONICS CTX20·2 (407) 241-7876
]

C2
0.01 I1F
R3
5k
':"
'DALE LPE-4841-100MB (605) 665-9301

4-331

LT1373
TYPICAL APPLICATions
Low Ripple 5V to -3V "Cuk"t Converter

~~~~.----------------,

r--_-_---.-

90% Efficient CCFL Supply
VOUT
-3V
2S0mA

01
lN4148
VIN
4.SV ~.----+-+':""'---=4-~--""'!:....---!+-J
T030V

Rl
lk
1%
Cl
22j!F
10V

+

C3
47f1F
16V

2.7VTO
S.5V

_0------...,

02
lN4148

R2
4.99k
1%

10k

'SUMIDA CLS62-100L
"MOTOROLA MBROS20LT3
tpATENTS MAY APPLY

T

O.l !!F

OPTIONAL REMOTE
DIMMING
Cl = WIMA MKP-20
L1 ,; COILCRAFT 003316-104
Ql, Q2 = ZETEX lTX849 OR ROHM 2SC5001
Tl = COILTRONICS CTX 110609
• = 1% FILM RESISTOR
DO NOT SUBSTITUTE COMPONENTS
COILTRONICS (407) 241-7876
COILCRAFT (708) 639-6400

CCFL BACKLIGHT APPLICATION CIRCUITS
CONTAINED IN THIS DATA SHEET ARE
COVERED BY U.S. PATENT NUMBER 5408162
AND OTHER PATENTS PENDING

Two Li·lon Cells to 5V SEPIC Conveter
VIN
4VT09V

VOUTt
SV

OFFS ON

+

Cl
33f1F
20V

+ C3

1~(7'F

tMAX lOUT
Cl =AVX TPSD 336M020R0200
C2 =TOKIN 1E225ZYSU-C203-F
C3 = AVX TPSD 107M010R0100
Ll = COILTRONICS CTX33-2, SINGLE
INDUCTOR WITH lWO WINDINGS

4-332

lOUT
O.45A
O.S5A
O.65A
0.72A

VIN
4V
5V
7V
9V

LT13n-TA07

LT1373
RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1172
LTC@1265

100kHz 1.25A Boost Switching Regulator

Also for Flyback, Buck and Inverting Configurations

13V 1.2A Monolithic Buck Converter

Includes PMOS Switch On-Chip

LT1302

Micropower 2A Boost Converter

Converts 2V to SV at 600mA

LT1372

500kHz 1.5A Boost Switching Regulator

Also Regulates Negative Flyback Outputs

LT1376

500kHz 1.SA Buck Switching Regulator

LT1377

1MHz 1.5A Boost Switching Regulator

Handles Up to 25V Inputs
Only 1MHz Integrated Switching Regulator Available

•

4-333

f""'-LlneJ\~D~

~,

TECHNOLOGY

___

L_T13_75__
/LT_13_76
1.5A, 500kHz Step-Down
Switching Regulators

FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•

The LT@1375/LT1376 are 500kHz monolithic buck mode
switching regulators. A 1.5A switch is included on the die
along with all the necessary oscillator, control, and logic
circuitry. High switching frequency allows a considerable
reduction in the size of external components. Thetopology
is current mode for fast transient response and good loop
stability. Both fixed output voltage and adjustable parts are
available.

Constant 500kHz Switching Frequency
Easily Synchronizable
Uses All Surface Mount Components
Inductor Size Reduced to 5j.IH
Saturating Switch Design: O.4n
Effective Supply Current: 2.5mA
Shutdown Current: 201-1A
Cycle-by-Cycle Current Limiting

A special high speed bipolar process and new design
techniques achieve high efficiency at high switching frequency. Efficiency is maintained over a wide output current range by using the output to bias the circuitry and by
utilizing a supply boost capacitor to saturate the power
switch. A shutdown signal will reduce supply current to
201-1A on both parts. The LT1375 can be externally synchronized from 550kHz to 1MHz with logic level inputs.

APPLICATions
•
•
•
•

Portable Computers
Battery-Powered Systems
Battery Charger
Distributed Power

The LT1375/LT1376 fit into standard 8-pin PDIP and SO
packages. Full cycle-by-cycle short-circuit protection
and thermal shutdown are provided. Standard surface
mount external parts are used, including the inductor and
capacitors.
For low input voltage applications with 3.3V output, see
LT1507. This is a functionally identical part that can
operate with input voltages between 4.5V and 12V.

£T. LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
5V Buck Converter

Efficiency vs Load Current

02
1N914

100
Vour= 5V
VIN =10V
L =10f!H

90
6Vt

i~~~0-----C3'
lOf!F TO
50f!F

---"~.JJ.JLr-"""'--

/

= ON

, RIPPLE CURRENT ~ IOUT/2
,. INCREASE L1 TO 10f!H FOR LOAD CURRENTS ABOVE 0.6A AND TO 20f!H ABOVE 1A
t FOR INPUT VOLTAGE BELOW 7.5V, SOME RESTRICTIONS MAY APPLY.
SEE APPLICATIONS INFORMATION.

C1
100f!F,10V
SOLID
TANTALUM

....-

-

/

~ DEFAULT
-

4-334

OUTPUT"
5V, 1.25A

60

50

o

0.25

0.50
0.75
1.00
LOAD CURRENT (A)

1.25

LTl 375/LT 1376
ABSOLUTE mAXimum RATinGS
nput Voltage .......................................................... 25V
300st Pin Voltage. ............................... ... ..... ..... ...... 35V
>HDN Pin Voltage ..................................................... 7V
3ias Pin Voltage ........................................................ 7V
:B Pin Voltage (Adjustable Part) ............................ 3.5V
:B Pin Current (Adjustable Part) ............................ 1mA
>ense Voltage (Fixed 5V Part) ............ ... ................... 7V
>ync Pin Voltage ...................................................... 7V

~ACKAGEIORDER

Operating Ambient Temperature Range
LT1375C/L T1376C ................................. O°C to 70°C
LT13751/LT13761 ............................... -40°C to 85°C
Operating Junction Temperature Range
LT1375C/LT1376C ............................... O°C to 125° C
LT13751/LT13761 ............................. -40°C to 125°C
Storage Temperature Range ............ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

InFORmATiOn
ORDER PART
NUMBER

TOP VIEW

·~o"
VIN 2

7 FB/SENSE

Vsw 3

6 GND

SHDN 4

5 SYNC

N8 PACKAGE
8·LEAD PDIP
S8 PACKAGE
8·LEAD PLASTIC SO

OJA= 100°C! W (N8)
OJA = 120°C/W TO 150°CIW DEPENDING ON
PC BOARD LAYOUT (S8)

LT1375CN8
LT1375CN8-5
LT1375CS8
LT1375CS8-5
LT13751N8
LT13751N8-5
LT13751S8
LT13751S8-5
S8 PART
MARKING
1375
13755
13751
137515

ORDER PART
NUMBER

-0"
TOP VIEW

VIN 2

LT1376CN8
LT1376CN8-5
LT1376CS8
LT1376CS8-5
LT13761N8
LT1376IN8-5
LT13761S8
LT1376IS8-5

7 FB/SENSE

Vsw 3

6 GND

BIAS 4

5 SHDN

N8 PACKAGE
8·LEAD PDIP
S8 PACKAGE
8·LEAD PLASTIC SO

•

S8 PART
MARKING

OJA = 100°C/W (N8)
OJA = 120°C/W TO 151l"C/W DEPENDING ON
PC BOARD LAYOUT (S8)

1376
13765
13761
137615

:onsult factory for Military grade parts.

ELEORICAL CHARAOERISTICS
'J = 25°C,

VIN =15V, Vc =1.5V, boost open, switch open, unless otherwise noted.

'ARAMETER

CONDITIONS

leference Voltage (Adjustable)
All Conditions
:ense Voltage (Fixed 5V)
All Conditions
:ense Pin Resistance
leference Voltage Line Regulation
eedback Input Bias Current
rror Amplifier Voltage Gain
rror Amplifier Transconductance

•

•

MIN
2.39
2.36
4.94
4.90
7

5V :s:VIN:S: 25V
VSHDN = lV (Notes 1,7)
VSHDN = lV, AI (Ve) = ±101lA (Note 7)

•

•

200
1500
1100

TYP
2.42
5.0
10
0.01
0.5
400
2000

MAX
2.45
2.48
5.06
5.10
14
0.03
1.5

UNITS
V
V
V
V
k.Q

'Io/V

IlA

2700
3000

~ho
~ho

4-335

LT1375/LT 1376

ElEORICAl CHARAOERISTICS
TJ = 25°C, VIN = 15V, Vc = 1.5V, boost open, switch open, unless otherwise noted.
PARAMETER
Vc Pin to Switch Current Transconductance
Error AmplifierSource Current
Error flmplifier Sink Current
Vc Pin Switching Threshold
Vc Pin High Clamp
Switch Current Limit

Switch On Resistance (Note 6)
Maximum Switch Duty Cycle

Switch Frequency

Switch Frequency Line Regulation
Frequency Shifting Threshold on FB Pin
Minimum Input Voltage (Note 2)
Minimum Boost Voltage (Note 3)
Boost Current (Note 4)

CONDITIONS

MIN

VSHDN = IV, VFB = 2.7V or VSENSE = 4.4V
VSHDN = IV, VFB = 2.7V or VSENSE = 5.6V
Duty Cycle = 0
VSHDN = IV
Vc Open, VFB = 2.1V or VSENSE = 4.4V,
DC~50%
VBOOST = VIN + 5V
DC = 80%
Isw = 1.5A, VBOOST = VIN + 5V
VFB = 2.1V or VSENSE = 4.4V
-55°C ~ TJ ~ 125°C
TJ = 150°C
Vc Set to Give 50% Duty Cycle
-25°C ~TJ ~ 150°C
TJ ~-25°C
5V~VIN ~ 25V
III = 10kHz
Isw ~ 1.5A
VBOOST = VIN + 5V

Isw= 500mA
Isw = 1.5A

Input Supply Current (Note 5)
Output Supply Current (Note 5)
Shutdown Supply Current

VSIAS = 5V
VBIAS = 5V
VSHDN = OV, VIN ~ 25V, Vsw = OV, Vc Open

Lockout Threshold
Shutdown Thresholds

Vc Open
Vc Open

Minimum Synchronizing Amplitude (LT1375 Only)
Synchronizing Range (LT1375 Only)
Sync Pin Input Resistance

VIN = 5V

The. denotes specifications which apply over the full operating
temperature range.
Nole 1: Gain is measured with a Vc swing equal to 200mVabove the low
clamp level to 200mV below the upper clamp level.
Note 2: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator frequency remain
constant. Actual minimum input voltage to maintain a regulated output will
depend on output voltage and load current. See Applications Information.
Nole 3: This is the minimum voltage across the boost capaCitor needed to
guarantee full saturation of the internal power switch.
Nole 4: Boost current is the current flowing into the boost pin with the pin
held 5V above input voltage. It flows only during switch-on time.

4-336

Device Shutting Down
Device Starting Up

•

150

••

1.50
1.35

•

•
•
•
•
•
•
•
•
•
•
••

•

TYP
2
225
2
0.9
2.1

MAX

2

3
3
0.4
0.5

0.3
90
86
85
460
440
440
0.8

2.3
0.15
0.25

93
93
93
500

0.05
1.0
5.0
3
12
25
0.9
3.2
15
2.38
0.37
0.45
1.5

580
40

280

UNITS
A/V

IlA
mA
V
V

540
560
570
0.15
1.3
5.5
3.5
22
35
1.4
4.0
50
75
2.46
0.60
0.60
2.2
900

A
A
n
n
%
%
%
kHz
kHz
kHz
%/V
V
V
V
mA
mA
mA
mA

IlA
IlA
V
V
V
V
kHz
kn

Nole5: Input supply current is the bias current drawn by the input pin
when the bias pin is held at 5V with switching disabled. Output supply
current is the current drawn by the bias pin when the bias pin is held at
5V. Total input referred supply current is calculated by summing input
supply current (lSI) with a fraction of output supply current (Iso):
ITOT= lSI + (ISO)(VOUTNIN)(I.15)
With VIN = 15V, VOUT = 5V, lSI = O.gmA, Iso = 3.6mA, ITOT = 2.28mA.
Note 6: Switch-on resistance is calculated by dividing VIN to Vsw voltage
by the forced current (1.5A). See Typical Performance Characteristics for
the graph of switch voltage at other currents.
Note 7: Transconductance and voltage gain refer to the internal amplifier .
exclusive of the voltage divider. To calculate gain and transconductance
refer to sense pin on fixed voltage parts. Divide values shown by the ratio
VouT/2.42.

LT1 375/LT 1376
TYPICAL PERFORmAnCE CHARACTERISTICS
Inductor Core Loss

Switch Peak Current Limit

1.0 ,----,-----r--,----,------, 20
12

2.5

~PICAL

~-1_--+--~-1_-~8

[0.1
CJJ

§

:;s2.0

~-+""'-~-TYPE 52

"~

~====~~~~~PjO~W~D~ERiE~D~IR~O;N~ 1.2

5 rD

~

~

a:

8

~
"- 1.0

I--cc~NOCCDR'"'E~-,-~~~~,-:~CC~Sc-'T"'OFf,.L"'O-AD=-"""'I:::::---1

0.01

1.5

:r:

r=
§:

f-

rD
a:
a:

,....

200

~2.36

--

-

w

~ 2.42

""'-'~
53

80

100

o

",

r-:::::

~

c::

START-UP

f::0

~ 0.4
SHrDOT

a 25 50 75
TEMPERATURE (0C)

100

o

125

<'

------

2500

~ 125

:g2000
:;;;

.a

f-

100

~

75

/

it
::0
'"
f-

50

::0

"-

;;;;

~1500

VIN=2SY

::0

25

o

/
F-o

V
0.1

-

--.. r---...

o

125

20

a:

13

~

15

'"

10

f::0

/

-

";;;;

o

125

o

10
15
INPUT VOLTAGE (V)

20

25

Error Amplifier Transconductance
3000 rr--rTrr--rrnr,---rrrrr--rTrr--rTTTl 200

2500

............. ....."

H-+trt--t-ttt-+-+++t--t-+trN-t-H

150

:g 2000 H-+H+-+-H+H-H-++-+-1H+1!-.l::-+t-ll 100

~

::0

z
~ 1500

~1000

.......vIN =10V -

",.--

f-

rD
a:

- -.:::

t;

/

0.2
0.3
0.4
SHUTDOWN VOLTAGE (V)

r- ............

0.5

o'v

25

.a

Error Amplifier Transconductance

Shutdown Supply Current

/

-25
25
50
75 100
JUNCTION TEMPERATURE (OC)

VSHUTIOOWN =

-50 -25
0
25 50
75
100
JUNCTION TEMPERATURE (OC)

150

-

............

£LJT

2.40
-50

"::0

o
c

AT 2.38V STANDBYTHRESHOLD
(CURRENT FLOWS OUT OF PIN)

-50 -25

"'"I'---r. . . .

Shutdown Supply Current

~ 0.8

-

VOLTAGE

30

- ST~DB)

>

'-'

rD

40
60
DUTY CYCLE (%)

~
02.32

::0

a:
a:

~

Standby and Shutdown Thresholds

CUR~ENT ~EQUIR~D ~ORCEISHUT~OWN

~ 300

20

2.40

TO
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW ~A _r--

400

1.5

t:l: 2.41

o
o

Shutdown Pin Bias Current
500

~2.43
w

'" 0.5

CURRENT UNTIL LOAD CURRENT FALLS
LOW ENOUGH FOR CIRCUIT TO GO INTO
DISCONTINUOUS MODE

2.0

co

GUARAJEED MINIM:--

'-'

w

--..........

f-

U~

Feedback Pin Voltage and Current
2.44

50

:i!

~
~
.e

'-'

'"~
go

0.5

1000

500

o

-50 -25
0
25 50
75 100
JUNCTION TEMPERATURE (0C)

125

500 LL--LlJ.LL.J.J..J..L...LLUL.J.--LlJ.LL..l...LU
100
lk
10k
lOOk
1M
FREQUENCY (Hz)
1375176603

Kool

M~is

a registered trademark of Magnetics, Inc.

4-337

LT1375/LT 1376
TYPICAL PERFORmAnCE CHARACTERISTICS
Frequency Foldback

LT1376 Minimum Input Voltage
with 5V Output

Switching Frequency

~500r---'---~--~--~--~

600

8.5

~

~

1\--+-++--\--+-----1

400

:::J
U

a::

550

~
15 500

o
~ 300

>-

(;

iii 200 1---\1-+-1---1_-+_----1

@
fE

I'-- ...........

:::J

a

450

o

....._ . . . , j

0.5
1.0
1.5
2.0
FEEDBACK PIN VOLTAGE (V)

400
-50

2.5

r\

I
VOLTAGE TO
> 6.5 !-- r- START WITH
fSTANDARD
:::J
a.
CIRCUIT
;;; 6.0

7.0 !--

\

0

-25
25 50 75 100
JUNCTION TEMPERATURE (0C)

5.0
0.001

125

\

~~LTAdE1

MINIJJJ
TO RUN WITH
STANDARD CIRCUIT

5.5
0 L-_...L_-...Jo._ _....._

1~1~\~UMM1

w

~

.........

:;:

~

m

~ 7.5

E

~ 100~--~~-I---1_-+_----1

~

MINIMUM I'NPUTVOLTAG'ECAN BE
REDUCED BY ADDING A SMALL EXTERNAL
PNP.
f~~LlC~TI?~S INFORMATION

8.0

I

0.01
0.1
LOAD CURRENT (A)

1375176011

Maximum Load Current
at VOUT = 10V
1.50
VOUT! 10V
1.25

L~20"H_

1.50

'\ t'-... i""-

g1.00

......... "'"'
.........

g1.00

~ 0.75

~~
"",-L= 511H

a::

:::J

u

~

0.50

Maximum Load Current
at VOUT=5V

Maximum Load Current
at VOUT = 3.3V

~

1.25

\-. """"'-

~ 0.75

L= 511H I---

~
~

0.25

u

0.50

0.75

10
15
20
INPUT VOLTAGE (V)

o

25

o

vOUTi5V

10
15
20
INPUT VOLTAGE (V)

..,.V

<"

§.

ii'i
a::
a::

/

:::J

u
Z

c:
f-

en
0
0

4

ID

o

~

!3'"

1.0

0

>
0

0.8

ffl

a:

:r::
f-

0.50
0.75
1.00
SWITCH CURRENT (A)

1.25

1375176G16

4-338

TJ = 25°C

1.2

w

-'
0
:r::

0.25

25

0.8
SHUTDOWN

/

V-

10
15
20
INPUT VOLTAGE (V)

Switch Voltage Drop

Vc Pin Shutdown Threshold

I
I
o

o

1375/76&15

1.4

TJ = 2~oC

f-

o

25
1375176G14

Boost Pin Current
10

r---

0.25

1375178G13

12

"""""'-

0.50

Vour=3.3V

o

I.

L= 20"H

:::J

0.25

o

I-

~
I
~r-.. L=5I1H_

g1.00

a::

a::

........

::::--

1.25

:::J

u

-"

1.50
L= 2Ol1H
L= 1OI1H-

----

~ 0.6
w

r-- r-

V

'"
!j

r-

0.6
0.4
-50 -25
25 50 75 100
JUNCTION TEMPERATURE (OC)

125

~
:r::

0.4

~

~ 0.2

o

/
o

r
0.25

V

/f'

./

0.50 0.75 1.00 1.25
SWITCH CURRENT (A)

1.50

1375176G18

LT1375/LT1376

Pin FunCTions
BOOST (Pin 1): The boost pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional boost voltage allows the switch to saturate and
voltage loss approximates that of a 0.30 FET structure,
but with much smaller die area. Efficiency improves from
75% for conventional bipolar designs to > 87% for these
new parts.
Vsw (Pin 3): The switch pin is the emitter of the on-chip
power NPN switch. It is driven up to the input pin voltage
during switch on time. Inductor current drives the switch
pin negative during switch off time. Negative voltage is
clamped with the external catch diode. Maximum negative
switch voltage allowed is -0.8V.
SHDN (Pin 4 for LT1375, Pin 5 for LT1376): The shutdown pin is used to turn off the regulator and to reduce
input drain current to a few microamperes. Actually, this
pin has two separate thresholds, one at 2.38V to disable
switching, and a second at O.4V to force complete micropower shutdown. The 2.38V threshold functions as an
accurate undervoltage lockout (UVLO). This is sometimes
used to preventthe regulator from operating until the input
voltage has reached a predetermined level.
BIAS (Pin4, LT1376 Only):The bias pin is used to improve
efficiency when operating at higher input voltages and
light load current. Connecting this pin to the regulated
output voltage forces most ofthe internal circuitry to draw
its operating current from the output voltage rather than
the input supply. This is a much more efficient way of

doing business ifthe input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3.3V. Efficiency improvement at VIN = 20V,
VOUT =5V, and lOUT =25mA is over 10%.
SYNC (Pin 5, LT1375 Only): The sync pin is used to
synchronize the internal oscillator to an external signal. It
is directly logic compatible and can be driven with any
signal between 10% and 90% duty cycle. The synchronizing range is equal to initial operating frequency, up to
900kHz. See Synchronizing section in Applications Information for details.
FB/SENSE (Pin 7): The feedback pin is used to set output
voltage, using an external voltage divider that generates
2.42V at the pin with the desired output voltage. The fixed
voltage (-5) parts have the divider included on the chip,
and the FB pin is used as a sense pin, connected directly
to the 5V output. Two additional functions are performed . , .
by the FB pin. When the pin voltage drops below 1.7V, . .
switch current limit is reduced. Below 1V, switching
frequency is also reduced. See Feedback Pin Function
section in Applications Information for details.
Vc (Pin 8): The Vc pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can do
double duty as a current clamp or control loop override.
This pin sits at about 1V for very light loads and 2V at
maximum load. It can be driven to ground to shut off the
regulator, but if driven high, current must be limited to
4mA.

BLOCK DIAGRAm
The LT1376 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle ofthe power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. Aswitch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the

switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip pOint. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180 shift will occur.
The current fed system will have 90 0 phase shift at amuch
lower frequency, but will not have the additional 90 0 shift
0

4-339

LT1375/LT1376
BLOCK DIAGRAm
until well beyond the LC resonant frequency. This makes
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.

High switch efficiency is attained by using the boost pin to
provide avoltage to the switch driver which is higher than
the input voltage, allowing switch to be saturated. This
boosted voltage is generated with an external capacitor
and diode. Two comparators are connected to the shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has aD.4V threshold for complete
shutdown.

Most of the circuitry of the LT1376 operates from an
internal2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
power will be drawn from the external source (typically the
regulated output voltage). This will improve efficiency if
the bias pin voltage is lower than regulator input voltage.

O.1n
INPUT

BIAS

2.9V BIAS
REGULATOR

CURRENT
SENSE
AMPLIFIER
VOLTAGE GAIN = 10

INTERNAL

Vee

SLOPE COMP

BOOST

O.9V
500kHz
OSCILLATOR

SYNC

Rs
FLIP-FLOP

DRIVER
CIRCUITRY

R

Vsw

O.4V
FREQUENCY
SHIFT CIRCUIT

SHUTDOWN
3.5~

FOLDBACK
CURRENT
LIMIT
CLAMP

Q2

FB

Ve

2.42V
GND

Figure 1. Block Diagram

4-340

LT1 375/LT 1376
APPLICATions InFoRmATion
Table 1.

FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1376 is used to set output
voltage and also to provide several overload protection
features. The first part of this section deals with selecting
resistors to set output voltage and the remaining part talks
about fold back frequency and current limiting created by
the FB pin. Please read both parts before committing to a
final design. The fixed 5V LT1376-5 has internal divider
resistors and the FB pin is renamed SENSE, connected
directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
R1 = _R2-,(~VO_U_T-_2._42--<..)
2.42

OUTPUT
VOLTAGE
(V)

(kQ)

R1
(NEAREST 1%)
(kO)

3
3.3
5
6
8
10
12
15

4.99
4.99
4.99
4.99
4.99
4.99
4.99
4.99

1.21
1.82
5.36
7.32
11.5
15.8
19.6
26.1

R2

% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
+0.23
+0.08
+0.39
-0.5
-0.04
+0.83
-0.62
+0.52

More Than Just Voltage Feedback
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency . .
Foldback graph in Typical Performance Characteristics). . .
This is done to control power dissipation in both the IC and
in the external diode and inductor during short-circuit
conditions. A shorted output requires the switching regulator to operate at very low duty cycles, and the average
current through the diode and inductor is equal to the
short-circuit current limit ofthe switch (typically 2A forthe

...."rrY'--~

OUTPUT
5V

13751761'02

Figure 2. Frequency and Current Limit Foldback

4-341

Ll1375/LT1376
APPLICATions InFoRmATion
LT1376, folding back to less than 1A). Minimum switch on
time limitations would prevent the switcher from attaining
a sufficiently low duty cycle if switching frequency were
maintained at SOOkHz, so frequency is reduced by about
S:1 when the feedback pin voltage drops below 1V (see
Frequency Foldback graph). This does not affect operation
with normal load conditions; one simply sees a gear shift
in switching frequency during start-up as the output
voltage rises.
In addition to lower switching frequency, the LT1376 also
operates at lower switch current limit when the feedback
pin voltage drops below 1.7V. 02 in Figure 2 performs this
function by clamping the Vc pin to a voltage less than its
normal2.3V upper clamp level. This foldback current limit
greatly reduces power dissipation in the IC, diode and
inductor during short-circuit conditions. Again, it is nearly
transparent to the user under normal load conditions. The
only loads which may be affected are current source loads
which maintain full load current with output voltage less
than SO% of final value. In these rare situations the
feedback pin can be clamped above 1.SV with an external
diode to defeat foldback current limit. Caution: clamping
the feedback pin means that frequency shifting will also be
defeated, so acombination of high input voltage and dead
shorted output may cause the LT1376 to lose control of
current limit.
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. 01 is completely off during normal
operation. If the FB pin falls below 1V, 01 begins to
conduct current and reduces frequency at the rate of
approximately SkHzI~. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pu1l1S0~ out of the FB pin with 0.6V on the pin (Rolv
::;; 4k). The net result is that reductions in frequency and
current limit are affected by output voltage divider impedance. Although divider impedance is not critical, caution
should be used if resistors. are increased beyond the
suggested values and short-circuit conditions will occur
with high input voltage. High frequency pickup will increase and the protection accorded by frequency and
current fold back will decrease.

4-342

MAXIMUM OUTPUT LOAD CURRENT
Maximum load current for a buck converter is limited by
the maximum switch current rating (Ip) of the LT1376.
This current rating is 1.SA up toSO% duty cycle (DC),
decreasing to 1.3SA at 80% duty cycle. This is shown
graphically in Typical Performance Characteristics and as
shown in the formula below:
Ip = 1.SA for DC ::;; SO%
Ip= 1.6SA-0.1S {DC)-O.26 (DC)2forSO% < DC <90%
DC = Duty cycle = VouTlVlN
Example: with VOUT =SV, VIN =8V; DC =S/8 = 0.62S, and;
ISW(MAX) = 1.64 - 0.1S (0.62S) - 0.26 (0.62S)2 = 1.44A
Current rating decreases with duty cycle because the LT
1376 has internal slope compensation to prevent current
mode subharmonic switching. For more details, read
Application Note 19. The LT1376 is a little unusual in this
regard because it has nonlinear slope compensation which
gives better compensation with less reduction in current
limit.
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current. The following
formula assumes continuous mode operation, implying
that the term on the right is less than one-half of Ip.
IOUT(MAX) =
Continuous Mode

Ip -

(VOUT )(VIN - VOUT )
2(L)(f) ("IN )

For the conditions above;
(S)(8-S)
IOUT(MAX) = 1.44- (
)(
)( )
2 10e-6 SOOe3 8

=1.44-0.19 =1.2SA
AtVIN =1SV, duty cycle is 33%, so Ip is justequalto afixed
1.SA, and IOUT(MAX) is equal to:

LT1375/LT 1376
APPLICATions InFoRmATion
CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR

(5)( 15 - 5)
1.5 - 2(1 Oe-6 )(500e3 )(15) =1.5 - 0.33 = 1.17A
~ote

that there is less load current available at the higher
nput voltage because inductor ripple current increases.
rhis is not always the case. Certain combinations of
nductor value and input voltage range may yield lower
IVaiiable load current at the lowest input voltage due to
·educed peak switch current at high duty cycles. If load
;urrent is close to the maximum available, please check
naximum available current at both input voltage exTemes. To calculate actual peak switch current with a
liven set of conditions, use:

:or lighter loads where discontinuous operation can be
]sed, maximum load current is equal to:
IOUT(MAX) =
Discontinuous mode

(Ip )2(f)(L)(VOUT)
2(VOUT )(VIN - VOUT)

:xample: with L =2~, VOUT =5V, and VIN(MAX) =15V,

rhe main reason for using such atiny inductor is that it is
lhysically very small, but keep in mind that peak-to-peak
nductor current will be very high. This will increase output
ipple voltage.lfthe output capacitor has to be made larger
o reduce ripple voltage, the overall circuit could actually
vind up larger.

For most applications the output inductor will fall in the
range of 3~ to 20~. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1376 switch, which has a 1.5A limit. Higher values
also reduce output ripple voltage, and reduce core loss.
Graphs in the Typical Performance Characteristics section
show maximum output load current versus inductorsize
and input voltage. Asecond graph shows core loss versus
inductor size for various core materials.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allowable
component height, output voltage ripple, EMI, fault current in the inductor, saturation, and of course, cost. The
following procedure is suggested as a way of handling
these somewhat complicated and conflicting requirements. •
1. Choose a value in microhenries from the graphs of
maximum load current and core loss. Choosing asmall
inductor with lighter loads may result in discontinuous
mode of operation, butthe LT1376 is designed to work
well in either mode. Keep in mind that lower core loss
means higher cost, at least for closed core geometries
like toroids. The core loss graphs show both absolute
loss and percent loss for a5W output, so actual percent
losses must be calculated for each situation.
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
must withstand continuous fault conditions. If maximum load current is 0.5A, for instance, a0.5A inductor
may not survive acontinuous 1.5A overload condition.
Dead shorts will actually be more gentle on the inductor because the LT1376 has foldback current limiting.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, especially with smaller inductors and lighter loads, so don't
omit this step. Powdered iron cores are forgiving
because they saturate softly, whereas ferrite cores
saturate abruptly. Other core materials fall in between
somewhere. The following formula assumes continu-

4-343

LT1375/LT1376
APPLICATions InFORmATion
ous mode of operation, but it errs only slightly on the
high side for discontinuous mode, so it can be used for
all conditions.

Table 2.
VENDOR!
PART NO.

VALUE DC
CORE
(J.lH) (Amps) TYPE

SERIES
CORE
RESIS- MATER· HEIGHT
TANCE(Q)
(mm)
IAL

Coiltronics
CTX5-1

5

2.3

Tor

0.027

KMJ.l

4.2

CTX10-1

10

Tor

CTX20-1

20

1.9
1.0

Tor

0.039
0.137

KMJ.l
KMJ.l

4.2
4.2

CTX15-2

15

1.8

Tor

0.058

KMJ.l

6.0

CTX20-3

20

1.5

Tor

0.093

KMJ.l

4.7

3. Decide if the design can tolerate an "open" core geometry like a rod or barrel, which have high magnetic field
radiation, or whether itneeds aclosed core like atoroid
to prevent EMI problems. One would not want an open
core next to a magnetic storage media, for instance!
This is atoughdecision because the rods or barrels are
temptingly cheap and small and there are no helpful
guidelines to calculate when the magnetic field radiation will be a problem.

CTX20-4

2.2

Tor

0.059

1.8

Tor

0.021

KMJ.l
52

6.4

CTX5-1P

20
5

4.2

CTX10-1P

10

1.6

Tor

0.030

52

4.2

CTX15-1P

15

1.2

Tor

0.046

52

4.2

CTX20-1P

20

1.0

Tor

0.081

52

4.2

CTX20-2P

20

1.3

Tor

0.052

52

6.0

CTX20-4P

20

1.8

Tor

0.039

52

6.35

CORH64

10

0.084

Fer

4.5

4. Start shopping for an inductor (see representative
surface mount units in Table 2) which meets the
requirements of core shape, peak current (to avoid
saturation), average current (to limit heating), and fault
current (if the inductor gets too hot, wire insulation will
melt and cause turn-to-turn shorts). Keep in mind that
all good things like high efficiency, low profile, and high
temperature operation will increase cost, sometimes
dramatically. Get a quote on the cheapest unit first to
calibrate yourself on price, then ask for what you really
want.

22

SC

0.077

Fer

4.5

CORH73

10

1.7
1.2
1.7
1.1
1.4
1.1
2.4
1.7

SC

CORH74

SC
SC

0.055

Fer

3.4

0.15

Fer

3.4

Open

0.062

Fer

3.5

Open

0.085

Fer

3.5

Open

0.041

Fer

4.0

Open

0.062

Fer

4.0

VIN = Maximum input voltage
f = Switching frequency, 500kHz

5. After making an initial choice; consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology's applications department if you feel uncertain about the final
choice. They have experience with a wide range of
inductor types and can tell you about the latest developments in low profile, surface mounting, etc.

4-344

Sumida

CORH73

22

C073

10

C073

18

C0104

10

C0104

18

Gowanda
SM20-102K

10

1.3

Open

0.038

Fer

7.0

SM20-152K

15

1.3

Open

0.049

Fer

7.0

SM20-222K

22

1.3

Open

0.059

Fer

7.0

Dale
IHSM-4825

10

3.1

Open

0.071

Fer

5.6

IHSM-4825

22

Open

0.152

Fer

5.6

IHSM-5832

10

Open

0.053

Fer

7.1

IHSM-5832

22

1.7
4.3
2.8

Open

0.12

7.1

IHSM-7832

22

3.B

Open

0.054

Fer
' Fer

Tor = Toroid
SC = Semi-closed geometry
Fer = Ferrite core material
52 = Type 52 powdered iron core material
KMJ.l= KooIMJ.l

7.1

LT1375/LT1376
~PPLICATlons

InFORmATion

)utput Capacitor
-he output capacitor is normally chosen by its Effective
;eries Resistance (ESR), because this is what determines
lutput ripple voltage. At SOOkHz, any polarized capacitor
s essentially resistive. To get low ESR takes volume, so
lhysically smaller capacitors have high ESR. The ESR
ange for typical LT1376 applications is O.OSO to O.SO. A
ypical output capacitor is an AVX type TPS, 1001lf at 10V,
vith a guaranteed ESR less than 0.10. This is a "D" size
;urface mount solid tantalum capacitor. TPS capacitors
lre specially constructed and tested for low ESR, so they
live the lowest ESR for a given volume. The value in
nicrofarads is not particularly critical, and values from
!21lf to greater than SOOIlf work well, but you cannot
:heat mother nature on ESR. If you find a tiny 221lf solid
antalum capacitor, itwill have high ESR, and output ripple
roltage will be terrible. Table 3 shows some typical solid
antalum surface mount capacitors.
'able 3. Surface Mount Solid Tantalum Capacitor ESR
Ind Ripple Current
Case Size
,VX TPS, Sprague 593D
,VXTAJ

ESR (Max., Q)

Ripple Current (A)

0.1 to 0.3

0.7 to 1.1

0.7 to 0.9

0.4

I Case Size
,VX TPS, Sprague 593D

0.1 to 0.3

0.7 to 1.1

,VXTAJ

0.9 to 2.0

0.36 to 0.24

MXTPS

0.2 (typ)

0.5 (typ)

,VXTAJ

1.8103.0

0.22 to 0.17

2.5 to 10

0.16 to 0.08

: Case Size

,Case Size
,VXTAJ

~any engineers have heard that solid tantalum capacitors
Je prone to failure if they undergo high surge currents.
'his is historically true, and type TPS capacitors are
,peciallytested for surge capability, but surge ruggedness
:; not a critical issue with the output capacitor. Solid
antalum capacitors fail during very high turn-on surges,
~hich do not occur at the output of regulators. High
fischarge surges, such as when the regulator output is
lead shorted, do not harm the capacitors.

rent rating is not an issue. The current waveform is
triangular with atypical value of 200mARMS. The formula
to calculate this is:
Output Capacitor Ripple Current (RMS):

Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor's ESR
generates aloop "zero" at SkHzto SOkHzthat is instrumental in giving acceptable loop phase margin. Ceramic ca- . , . .
pacitors remain capacitive to beyond 300kHz and usually . .
resonate with their ESL before ESR becomes effective.
They are appropriate for input bypassing because of their
high ripple current ratings and tolerance otturn-on surges.
Linear Technology plans to issue a design note on the use
of ceramic capacitors in the near future.
OUTPUT RIPPLE VOLTAGE

Figure 3 shows a typical output ripple voltage waveform
for the LT1376. Ripple voltage is determined by the high
frequency impedance of the output capacitor, and ripple
current through the inductor. Peak-to-peak ripple current
through the inductor into the output capacitor is:

For high frequency switchers, the sum of ripple current
slew rates may also be relevant and can be calculated
from:

Inlike the input capacitor, RMS ripple current in the
lutput capacitor is normally low enough that ripple cur-

4-345

LT1375/LT 1376
APPLICATions InFoRmATion
Peak-to-peak output ripple voltage is the sum of a triwave
created by peak-to-peak ripple current times ESR, and a
square wave created by parasitic inductance (ESL) and
ripple current slew rate. Capacitive reactance is assumed
to be small compared to ESR or ESL.
VRIPPLE = (lp_p)(ESR) + (ESL)L ~!
Example: withVIN=10V, VOUT=SV, L=10~, ESR=O.1n,
ESL = 10nH:

I, p=
-

t °i
X1

5

) ) =O.5A
(10) 10e-6 SOOe3

10UT(VIN - VOUT)
10(AVG)=

10e-6

ID(AVG)=

VRIPPLE = (O.SA)(0.1) + (1 Oe-9)(1e6)

VOUTAT lOUT = 1A
20mVIDIV

VOUT AT lOUT = SOmA
INDUCTOR CURRENT
AT lOUT =1A
O.5A/DIV

m.,'Fll3

INDUCTOR CURRENT
AT lOUT = SOmA

Figure 3. LT1376 Ripple Voltage Waveform

CATCH DIODE
The suggested catch diode (D1) is a 1NS818 Schottky, or
its Motorola equivalent, MBR130.lt is rated at 1Aaverage
forward current and 30V reverse voltage. Typical forward
voltage is 0.42V at 1A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
regulator input voltage. Average forward current in normal operation can be calculated from:

4-346

1.8(1S-4)
1S
=1.32A

This is safe for short periods of time, but it would be
prudent to check with the diode manufacturer if continuous operation under these conditions must be tolerated.

= O.OS + 0.01 = 60mVp_p

O.5iJS/DIV

IN

This formula will not yield values higher than 1A with
maximum load current of 1.2SA unless the ratio of inputto
output voltage exceedsS:1. The only reason to consider a
larger diode is the worst-case condition of a high input
voltage and overloaded (not shorted) output. Under shortcircuit conditions, foldback current limit will reduce diode
current to less than 1A, but if the output is overloaded and
does not fall to less than 1/3 of nominal output voltage,
fold back will not take effect. With the overloaded condition, output current will increase to atypical value of 1.8A,
determined by peak switch current limit of 2A. With
VIN = 1SV, VOUT = 4V (SV overloaded) and lOUT = 1.8A:

L~=~=1e6
dt

v,

BOOST PIN CONSIDERATIONS
For most applications, the boost components are a 0.1 W
capacitor and a 1N914 or 1N4148 diode. The anode is
connected to the regulated output voltage and this generates a voltage across the boost capacitor nearly identical
to the regulated output. In certain applications, the anode
may instead be connected to the unregulated input voltage. This could be necessary if the regulated output
voltage is very low « 3V) or if the input voltage is less than
6V. Efficiency is not affected by the capacitor value, butthe
capacitor should have an ESR of less than 211 to ensure
that it can be recharged fully under the worst-case condition of minimum input voltage. Almost any type of film or
ceramic capacitor will work fine.

WARNING! Peak voltage on the boost pin is the sum of
unregulated input voltage plus the voltage across the
boost capacitor. This normally means that peak boost pin
voltage is equal to input voltage plus output voltage, but
when the boost diode is connected to the regulator input,
peak boost pin voltage is equal to twice the input voltage.

LT1375/LT 1376
r:lPPLICATlons InFORmATion
ge sure that boost pin voltage does not exceed its maxi71um rating.
:or nearly all applications, a 0.1 uF boost capacitor works
ust fine, but for the curious, more details are provided
lere. The size of the boost capacitor is determined by
iwi~ch drive current requirements. During switch on time,
Iram current on the capacitor is approximately 10mA +
OUTI7S. At peak load current of 1.2SA, this gives a total
Irain of 27mA. Capacitor ripple voltage is equal to the
lroduct of on time and drain current divided by capacitor
'alue;!:N =tON x 27mAlC. To keep capacitor ripple voltage
o less than O.SV (a slightly arbitrary number) atthe worst:ase condition of tON = 1.8J.1S, the capacitor needs to be
L1!lf. Boost capacitor ripple voltage is not a critical
larameter, but ifthe minimum voltage across the capacior drops to less than 3V, the power switch may not
;aturate fully and efficiency will drop. An approximate
ormula for absolute minimum capacitor value is:
_ (1 OmA + 10UTI7S)(VOUT/VIN)

CMIN -

-'---"""TT";~---1..l.-,..--.-L

(f)(VoUT-3V)
= Switching frequency
'OUT = Regulated output voltage
'IN = Minimum input voltage

·his formula can yield capacitor values substantially less
han 0.1!lf, but it should be used with caution since it does
lot take into account secondary factors such as capacitor
eries resistance, capacitance shift with temperature and
IUtPUt overload.
;HUTDOWN FUNCTION AND UNDERVOLTAGE
,OCKOUT
igure 4 shows how to add undervoltage lockout (UVLO)
) the LT1376. Typically, UVLO is used in situations where
1e input supply is current limited, or has a relatively high
ource resistance. A switching regulator draws constant
ower from the source, so source current increases as
ource voltage drops. This looks like a negative resistance
lad tothe source and can cause the source to current limit
r latch low under low source voltage conditions. UVLO
revents the regulator from operating at source voltages
,here these problems might occur.

L7lJ!1~

Threshold voltage for lockout is about 2.38V, slightly less
than the internal 2.42V reference voltage. A 3.S/lA bias
current flows out of the pin at threshold. This internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shutdown current is not an issue, the error due to this current
can be minimized by making RLO 10k or less. If shutdown
current is an issue, RLO can be raised to 1OOk, but the error
due to initial bias current and changes with temperature
should be considered.
RLO = 10k to 100k (2Sk suggested)
RHI =

RLO( VIN - 2.38V)

--'--~--'c-""

2.38V - RLO( 3.SJlA)
VIN = Minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capacitance to the switching nodes are minimized. If high resistor values are used, the shutdown pin should be bypassed
with a 1000pF capacitor to prevent coupling problems
from the switch node. If hysteresis is desired in the
undervoltage lockout point, a resistor RFB can be added to
the output node. Resistor values can be calculated from:
RLO[ViN - 2.38(~V/VoUT + 1)+ ~v]
RHI = _-"--_ _-'---,-_....,......'---..2
2.38 - R2(3.SIlA)
RFB = (RHI)(VOUT / ~v)
2Sk suggested for RLO
VIN = Input voltage at which switching stops as input
voltage descends to trip level
I!.V = Hysteresis in input voltage level
Example: output voltage is SV, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.SV. ~V is therefore 1.SV and VIN =
12V. Let RLO = 2Sk.

4-347

III

LT1375/LT1376
APPLICATions InFoRmATion
RFB
1--------------------~------------------------,1
1
I
I
1
1
1

INPUT -

-rY'YY1........._

.......- - t -

OUTPUT

1----+-..........1
1

1
1
1

::;:: C1

RLO

1
1

1
1
1
1

137517lJF04

Figure 4. Undervoltage Lockout

2Sk[12-2.38(1.S/S+ 1)+ 1.S]
RHI = --"----'----,--';---"-

2.38 - 2Sk(3.SIlA)

=

2Sk(10.41)

=114k
2.29
RFB =114k(S/1.S) =380k
SWITCH NODE CONSIDERATIONS

For maximum efficiency, switch rise and fall times are
made as short as possible. To prevent radiation and high
frequency resonance problems, proper layout ofthe components connected to the switch node is essential. 8 field
(magnetic) radiation is minimized by keeping catch diode,
switch pin, and input bypass capacitor leads as short as
possible. E field radiation is kept low by minimizing the
length and area of all traces connected to the switch pin
and boost pin. A ground plane should always be used
under the switcher Circuitry to prevent interplane coupling. A suggested layout for the critical components is
shown in Figure S. Note that the feedback resistors and
compensation components are kept as far as possible
from the switch node. Also note that the high current

4-348

ground path ofthe catch diode and input capacitor are kept
very short and separate from the analog ground line.
The high speed switching current path is shown schematically in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EM!. The path
including the switch, catch diode, and input capacitor is
the only one containing nanosecond rise and fall times. If
you follow this path on the PC layout, you will see that it is
irreducibly short. If you move the diode or input capacitor
away from the LT1376, get your resume in order. The
other paths contain only some combination of DC and
SOOkHz triwave, so are much less critical.
PARASITIC RESONANCE

Resonance or "ringing" may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schottky diodes have very high "a" junction capacitance that
can ring for many cycles when excited at high frequency.
Iftotallead length forthe input capacitor, diode and switch
path is 1 inch, the inductance will be approximately 2SnH.
Schottky diode capacitance of 100pF will create a resonance at 100MHz. This ringing is not harmful to the
LT1376 and can normally be ignored.

LTl 375/LT 1376
IfPPLICATlons InFORmATion

MINIMIZE AREA OF
CONNECTIONS TO THE
SWITCH NODE AND
BOOST NODE

MINIMIZE SIZE OF
FEEDBACK PIN
CONNECTIONS TO
AVOID PICKUP

KEEP INPUT CAPACITOR
AND CATCH DIODE CLOSE
TO REGULATOR AND
TERMINATE THEM
TO SAME POINT
TERMINATE
FEEDBACK RESISTORS
AND COMPENSATION
COMPONENTS
DlRECTLYTO SWITCHER
GROUND PIN
GROUND RING NEED
NOT BE AS SHOWN.
(NORMALLY EXISTS AS
INTERNAL PLANE)

CONNECT OUTPUT CAPACITOR
DIRECTLY TO HEAVY GROUND

TAKE OUTPUT DIRECTLY FROM END OF OUTPUT
CAPACITOR TO AVOID PARASITIC RESISTANCE
AND INDUCTANCE (KELVIN CONNECTION)

13751761'05

Figure 5. Suggested Layout

SWITCH NODE\

1I
:

VIN

CY'"""C

L1
5V

HIGH
FREQUENCY
CIRCULATING
PATH

":"

1375176F06

Figure 6. High Speed Switching Path

L7lJ!J~

4-349

.,.
. .

LT1375/LT 1376
APPLICATions InFoRmATion
Overshoot or ringing following switch fall time is created
by switch capacitance rather than diode capacitance. This
ringing per se is not harmful, but the overshoot can cause
problems if the amplitude becomes too high. The negative
voltage can forward bias parasitic junctions on the Ie chip
and cause erratic switching. The LT1376 has special
circuitry inside which mitigates this problem, but negative
voltages over 1V lasting longer than 10ns should be
avoided. Note that 1OOMHz oscilloscopes are barely fast
enough to see the details of the falling edge overshoot in
Figure 7.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor currentto fall to zero during part ofthe switch off
time (see Figure 8). Switch and diode capacitance resonate with the inductorto form damped ringing at 1MHzto
10 MHz. Again, this ringing is not harmful to the regulator
and it has not been shown to contribute significantly to
EMI. Any attempt to damp it with a resistive snubber will
degrade efficiency.

RISE AND FALL
WAVEFORMS ARE
SUPERIMPOSED
(PULSE WIDTH IS

5VIDIV

INPUT BYPASSING AND VOLTAGE RANGE
Input Bypass Capacitor

Step-down converters draw currentfrom the input supply
in pulses. The average height of these pulses is equal to
load current, and the duty cycle is equal to VouTIVIN. Rise
and fall time of the current is very fast. A local bypass
capacitor across the input supply is necessary to ensure
proper operation of the regulator and minimize the ripple
current fed back into the input supply. The capacitor also
forces switching current to flow in a tight local loop,
minimizing EMI.
Do not cheat on the ripple current rating of the Input
bypass capacitor, but also don't get hung up on the value
in microfarads. The input capacitor is intended to absorb
all the switching current ripple, which can have an RMS
value as high as one half of load current. Ripple current
ratings on the capacitor must be observed to ensure
reliable operation. The actual value of the capacitor in
microfarads is not particularly important because at
500kHz, any value above 5!!F is essentially resistive. RMS
ripple current rating is the critical parameter. Actual RMS
current can be calculated from:

2

IRIPPLE(RMS) =IOUT VOUT(VIN - VOUT )/\1N

NOT120ns)

20nsJDIV

\375/76 F07

Figure 7. Switch Node Resonance

I

5VIDIV

SWITCH NODE
VOLTAGE

~

INDUCTOR
CURRENT

l00mN[

The term inside the radical has a maximum value of 0.5
when input voltage is twice output, and stays near 0.5 for
a relatively wide range of input voltages. It is common
practice therefore to simply use the worst-case value and
assume that RMS ripple current is one half of load current.
At maximum output current of 1.5A for the LT1376, the
input bypass capacitor should be rated at 0.75A ripple
current. Note however, that there are many secondary
considerations in choosing the final ripple current rating.
These include ambient temperature, average versus peak
load current, equipment operating schedule, and required
product lifetime. For more details, see Application Notes
19 and 46, and Design Note 95.
Input Capacitor Type

O.5~IV

Figure 8. Discontinuous Mode Ringing

4-350

Some caution must be used when selecting the type of
capacitor used at the input to regulators. Aluminum

LTl 375/LT 1376
~PPLICATlons

InFORmATion

lectrolytics are lowest cost, but are physically large to
chieve adequate ripple current rating, and size contraints (especially height), may preclude their use. Ce~
imic capaCitors are now available in larger values, and
leir high ripple current and voltage rating make them
leal for input bypassing. Cost is fairly high and footprint
lay also be somewhat large. Solid tantalum capacitors
!ould be a good choice, except that they have a history of
ccasional spectacular failures when they are subjected to
lrge current surges during power-up. The capaCitors can
hort and then burn with a brilliant white light and lots of
asty smoke. This phenomenon occurs in only a small
ercentage of units, but it has led some OEM companies
) forbid their use in high surge applications. The input
ypass capacitor of regulators can see these high surges
,hen a battery or high capacitance source is connected.
everal manufacturers have developed a line of solid
tntalum capaCitors specially tested for surge capability
WX TPS series for instance, see Table 3), but even these
nits may fail if the input voltage surge approaches the
laximum voltage rating of the capacitor. AVX recomlends derating capacitor voltage by 2:1 for high surge
pplications. The highest voltage rating is 50V, so 25V
lay be a practical upper limit when using solid tantalum
ipacitors for input bypassing.
arger capacitors may be necessary when the input voltJe is very close to the minimum specified on the data
heet. Small voltage dips during switch on time are not
ormallya problem, but at very low input voltage they may
wse erratic operation because the input voltage drops
elow the minimum specification. Problems can also
Gcur if the input-to-output voltage differential is near
linimum. The amplitude of these dips is normally a
Inction of capacitor ESR and ESL because the capacitive
lactance is small compared to these terms. ESR tends to
~ the dominate term and is inversely related to physical
Ipacitor size within a given capacitor type.

linimum Input Voltage (After Start-Up)
linimum input voltage to make the LT1376 "run" corfctly is typically 5V, but to regulate the output, a buck
lnverter input voltage must always be higher than the
Jtput voltage. To calculate minimum operating input

voltage, switch voltage loss and maximum duty cycle
must be taken into account. With the LT1376, there is the
additional consideration of proper operation of the boost
circuit. The boost circuit allows the power switch to
saturate for high efficiency, but it also sometimes results
in a start-up or operating voltage that is several volts
higher than the standard running voltage, especially at
light loads. An approximate formula to calculate minimum
running voltage at load currents above 100mA is:
\I,

_

IN(MIN) -

VOUT + (loUT)(OAn)
0.88

Minimum Start-Up Voltage and Operation at
Light Loads
The boost capacitor supplies current to the Boost pin
during switch on time. This capacitor is recharged only
during switch off time. Under certain conditions of light
load and low input voltage, the capacitor may not be
recharged fully during the relatively short off time. This
causes the boost voltage to collapse and minimum input
voltage is increased. Start-up voltage at light loads is
higher than normal running voltage for the same reasons.
The graph in Figure 9 shows minimum input voltage for a
5V output, both for start-up and for normal operation.
B.O

II

7.5

,l~)

~ 7.0
~
~ 6.5
>
~
~ 6.0

(C)

I\-

(A)

\

\

(D)

5.5
5.0
0.001

0.01

(A) MINIMUM VOLTAGE
TO START WITH
STANDARD CIRCUIT
(B) MINIMUM VOLTAGE
TO RUN WITH
STANDARD CIRCUIT
(C) MINIMUM VOLTAGE
TO START WITH
PNP
(D) MINIMUM VOLTAGE
TO RUN WITH
PNP

0.1

LOAD CURRENT (A)

Figure 9. Minimum Input Voltage

4-351

LT1375/LT1376
APPLICATions InFoRmATion
The circuit in Figure 10 will allow operation at light load
with low input voltages. It uses a small PNP to charge the
boost capacitor C2, and an extra diode D3 to complete the
power path from Vsw to the boost capacitor.
Dl
lN914

!--~-+..rY'IfY"\.+-

OUTPUT

Cl

1375176F11J

Figure 10. Reducing Minimum Input Voltage

SYNCHRONIZING (Available on LT1375 Only)
The LT1375 has the bias pin replaced with a sync pin,
which is used to synchronize the internal oscillator to an
external signal. It is directly logic compatible and can be
driven with any signal between 10% and 90% duty cycle.
The synchronizing range is equal to initial operating frequency up to 900kHz. This means that minimum practical

sync frequency is equal to the worst-case high selfoscillating frequency (560kHz), not the typical operating
frequency of 500kHz. Caution should be used when synchronizing above 700kHz because at higher sync frequencies the amplitude of the internal slope compensation
used to prevent subharmonic switching is reduced. This
type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor
values will tend to eliminate problems. See Frequency
Compensation section for a discussion of an entirely
different cause of subharmonic switching before assuming that the cause is insufficient slope compensation.
Application Note 19 has more details on the theory of slope
compensation.

FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also introduce multiple poles into the feedback loop. The inductor
and output capacitor on a conventional step-down converter actually form aresonant tank circuit that can exhibit
peaking and a rapid 1800 phase shift at the resonant
frequency. By contrast, the LT1376 uses a"current mode"
architecture to help alleviate phase shift created by the
inductor. The basic connections are shown in Figure 11.
Figure 12 shows a Bode plot of the phase and gain of the

J

40
OUTPUT

m

~
I-

20

::>

Rl

0-

,

I-

,1
1
1
1
1
1
1

::>
0
0

I-

---I
1
ESR 1
1
1
Cl J11
___

z

40

1N:: 11\fv1 T

Voup5V
IOUp500mA

"'1\
-;-;

\

GAil

0

\
40 C

1

a:

\ PH..\S:

-J;?

\

~ -20

c
c

~<

-.c
80~

FI

'"

E

R2
~

10

100

lk
10k
FREQUENCY (Hz)

lOOk

~W

1M

1375/76F12
1375f76Fl1

Figure 11. Model for Loop Response

4-352

Figure 12. Response from Vc Pin to Output

LT1375/LT1376
IPPLICAllons InFoRmAllon
ower section ofthe LT1376, measured from the Vc pin to
1e output. Gain is set by the 2A!Vtransconductance ofthe
T1376 power section and the effective complex impednce from outputto ground. Gain rolls off smoothly above
1e 100Hz pole frequency set by the 1OOW output capacilr. Phase drop is limited to about 85°. Phase recovers and
ain levels off at the zero frequency (",16kHz) set by
apacitor ESR (0.1 Q).
rror amplifiertransconductance phase and gain are shown
1 Figure 13. The error amplifier can be modeled as a
·ansconductance of 2000!-IMho, with an output impednce of 200kQ in parallel with 12pF. In all practical
pplications, the compensation network from Vc pin to
round has a much lower impedance than the output
npedance of the amplifier at frequencies above 500Hz.
his means that the error amplifier characteristics themelves do not contribute excess phase shiftto the loop, and
1e phase/gain characteristics of the error amplifier secon are completely controlled by the external compensaon network.
1 Figure 14, full loop phase/gain characteristics are
hown with acompensation capacitor of 0.0033W, giving
1e error amplifier a pole at 240Hz, with phase rolling off
) 90° and staying there. The overall loop has a gain of
7dB at low frequency, rolling off to unity-gain at 20kHz.
hase shows atwo-pole characteristic until the ESR of the
utput capaCitor brings it back above 10kHz. Phase marin is about 60° at unity-gain.
3000

200

2500

150

:g2000
:;;

100

.=!,

z

~ 1500

50

VFB x 2.-3

1000
500 LL..LLLL-L-L.llL-LLLl.l..-L--'-ill-LI.J..U
100
1k
10k
100k
1M
FREQUENCY (Hz)
1375176F13

::g

Iii

C

.9

80

200

. .;LW+1
i\'AIN

60

150

~

40

100

'"g;

20

CD

z
:;;:

g

~

~

5
S6
"C

~

V~
PHASE

50 C

.9
VIN= 10V
\
Voup 5V,.IOUT = 500mA
Coup 100IlF, 10V, AVX TPS
Cc = ~.~,nF, Rc ~ ,~, L = 10llH

-20
10

100

1\

1k
10k
FREQUENCY (Hz)

100k

-50
1M

1375176f14

Figure 14. Overall Loop Characteristics

Analog experts will note that around 1kHz, phase dips very
close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a . , .
problem as long as it does not occur near unity-gain. In . . .
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR will cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over avery wide range of ESR
(;::: ±3:1).
What About a Resistor in the Compensation Network?

It is common practice in switching regulator design to add
a "zero" to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (Rc) in series with the
compensation capacitor. Increasing the size of this resistor generally creates better and better loop stability, but
there are two limitations on its value. First, the combination of output capaCitor ESR and a large value for Rc may
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for Rc
where gain margin falls to zero is:
.)
VOUT
(
Rc Loop Gam =1 = (G )(G )(ESR)(2.42)
MP MA

Figure 13. Error Amplifier Gain and Phase

£'7lJ!J~

4-353

LT1375/LT 1376
APPLICATions InFoRmATion
GMP = Transconductance of power stage = 2AIV
GMA = Error amplifier transconductance = 2e-3
ESR = Outputcapacitor ESR
2.42 = Reference voltage
With VOUT = 5V and ESR = 0.10, a value of 5.17k for Re
would yield zero gain margin, so this represents an upper
limit. There is a second limitation however which has
nothing to do with theoretical small signal dynamics. This
resistor sets high frequency gain of the error amplifier,
Including the gain at the switching frequency. If switching
frequency gain is high enough, output ripple voltage will
appear at the Ve pin with enough amplitude to muck up
proper operation of the regulator. In the marginal case,
subharmonic switching occurs, as evidenced byalternating pulse widths seen at the switch node. In more severe
cases, the regulator squeals or hisses audibly even though
the output voltage is still roughly correct. None ofthis will
show on a theoretical Bode plot because Bode is an
amplitude insensitive analysis. Tests have shown that if
ripple voltage on the Vcis held to less than 100mVp_p, the
LT1376 will be well behaved. The formula below will give
an estimate of Ve ripple voltage when Re is added to the
loop, assuming that Re is large compared to the reactance
of Ceat 500kHz.
\l

C(RIPPLE)

(Rc )(GMA)(VIN - VOUT )(ESR)(2.4)
(VIN)(L )( f)

GMA = Error amplifier transconductance (2000J,IMho)
If a computer simulation of the LT1376 showed that a
series compensation resistor of 3k gave best overall loop
response, with adequate gain margin, the resulting Ve pin
ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.10,
L = 1OIJH, would be:

VC(RIPPLE)

(3k)(2e-3)(10 - 5)(0.1)(2.4)
()(
= 0.144V
10 10e- 500e3

6)(

)

This ripple voltage is high enough to possibly create
subharmonic switching. In most situations acompromise
value « 2k in this case) for the resistor gives acceptable

4-354

phase margin and no subharmonic problems. In other
cases, the resistor may have to be largerto get acceptable
phase response, and some means must be used to control
ripple voltage at the Ve pin. The suggested way to do this
is to add acapacitor (CF) in parallel with the Re/Ce network
on the Ve pin. Pole frequency for this capacitor is typically
set at one-fifth of switching frequency so that it provides
significant attenuation of switching ripple, but does not
add unacceptable phase shift at loop unity-gain frequency.
With Re = 3k,

How Do I Test loop Stability?
The "standard" compensation for LT13i6 is a 3.3nF
capacitor for Cc, with Re = O. While this compensation will
work for most applications, the "optimum" value for loop
compensation components depends, to various extent, on
parameters which are not well controlled. These include
inductor value (±30% due to production tolerance, load
current and ripple current variations), output capacitanc€
(±20%to ±50% due to production tolerance, temperature, aging and changes at the load), output capacitor ESFi
(±200% due to production tolerance, temperature and
aging), and finally, DC input voltage and output loaQ
current. This makes it importantforthe designer to check
outthe final design to ensure that it is "robust" and tolerant
of all these variations.
I check switching regulator loop stability by pulse loading
the regulator output while observing transient response at
the output, using the circuit shown in Figure 15. The
regulator loop is "hit" with a small transient AC load
current at a relatively low frequency, 50Hz to 1kHz. This
causes the outputto jump afew millivolts, then settle back
tothe original value, asshown in Figure 16. Awell behaved
loop will settle back cleanly, whereas a loop with poor
phase or gain margin will "ring" as it settles. The numbel
of rings indicates the degree of stability, and the frequenc}
of the ringing shows the approximate unity-gain frequency of the loop. Amplitude of the signal is not particularly important, as long as the amplitude is not so high that
the loop behaves nonlinearly.

LT1375/LT1376
~PPLICATlons

InFORmATion
RIPPLE FILTER
(-4700---4~ik------~

TO X1

----i-"""".........w.......---T+ OSCILLOSCOPE
PROBE

I--..............

I

: 3300pF
I
I
1.... _____ - - - -

ADJUSTABLE
INPUT SUPPLY

I

330pF :
I
I

____ ,

TO
OSCILLOSCOPE
SYNC

1315176F15

Figure 15. Loop Stability Test Circuit

I

VOUT AT lOUT =
500mA
BEFORE FILTER
VOUT AT lOUT =
500mA
AFTER FILTER

10mVlDIV

~

VOUT AT lOUT =50mA
AFTER FILTER
LOAD PULSE
THROUGH son
f = 780Hz

5A!DIV

L
0.2ms/DIV

Figure 16. Loop Stability Check

he output of the regulator contains both the desired low
"equency transient information and a reasonable amount
f high frequency (500kHz) ripple. The ripple makes it
ifficult to observe the small transient, so a two-pole,
OOkHz filter has been added. This filter is not particularly
ritical; even if it attenuated the transient signal slightly,
lis wouldn't matter because amplitude is not critical.
.fter verifying that the setup is working correctly, I start
arying load current and input voltage to see if I can find
ny combination that makes the transient response look
uspiciously "ringy." This procedure may lead to an adlstment for best loop stability or faster loop transient
~sponse. Nearly always you will find that loop response
)oks better if you add in several kn for Re. Do this only
necessary, because as explained before, Re above 1k
lay require the addition of CF to control Vc pin ripple. If
verything looks OK, I use aheat gun and cold spray on the
ircuit (especially the output capacitor) to bring out any
lmperature-dependent characteristics.

Keep in mind that this procedure does not take initial
component tolerance into account. You should see fairly
clean response under all load and line conditions to ensure
that component variations will not cause problems. One
note here: according to Murphy, the component most . , . .
likely to be changed in production is the output capacitor, . .
because that is the component most likely to have manufacturer variations (in ESR) large enough to cause problems. It would be awise move to lock down the sources of
the output capacitor in production.
Apossible exception to the "clean response" rule is at very
light loads, as evidenced in Figure 16 with ILOAD =SOmA.
Switching regulators tend to have dramatic shifts in loop
response at very light loads, mostly because the inductor
current becomes discontinuous. One common result is
very slow but stable characteristics. A second possibility
is low phase margin, as evidenced by ringing atthe output
with transients. The good news is that the low phase
margin at light loads is not particularly sensitive to componentvariation, so if it looks reasonable under atransient
test, it will probably not be a problem in production. Note
that frequency of the light load ringing may vary with
componenttolerance but phase margin generally hangs in
there.

THERMAL CALCULATIONS
Power dissipation in the LT1376 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formulas show how to calculate each of these losses. These

4-355

LT1375/LT 1376
APPLICATions InFoRmATion
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:

Psw

TJ = TA + 9JA (ProT)
With the SO-8 package (9JA = 120°C/W), at an ambient
temperature of 70°C,
TJ = 70 + 120 (0.37) = 114.4°C

Rsw(lo~t(VOUT) +16ns(loUT)(1\,)(f)

Boost current loss:

Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
POSITIVE-TO-NEGATIVE CONVERTER

VOU /(0.008+ IOUT/75)
PBOOST = -----'------"V1N
Quiescent current loss:
(VOUT2)0.002)
Po ="'N(0.001) + VOUT (0.005)+ -"-----"--V1N
Rsw = SwitCh resistance (",0.4)
16ns = Equivalent switch current/voltage overlap time
f = Switch frequency

The circuit in Figure 17 is a classic positive-to-negative
topology using a grounded inductor. It differs from the
standard approach in the way the IC chip derives its
feedback Signal, however. Because the LT1376 accepts
only positive feedback signals, the ground pin must be tied
to the regulated negative output. A resistor divider to
ground or, in this case, the sense pin, then provides the
proper feedback voltage for the chip.
D1
1N4148

Example: with VIN = 10V, VOUT = 5V and lOUT = 1A:
Psw = (0.4)1(t(5) + (16e-9 )(1)(10)(500e3 )

C1
100~F

10VTANT

= 0.2 + 0.08 = 0.28W
PBOOST =

(5)2(0.008 + 1/75)
10

Po =10(0.001)+5(0.005)+

OUTPUT"
'---+--~~--~~ -5V,O.5A

= 0.053W
(5)2(0.002)
10
=0.04W

Total power dissipation is 0.28 + 0.053 + 0.04 = 0.37W.
Thermal resistance for LT1376 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 120°C/W. No plane will increase resistance to about
160°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:

4-356

• INCREASE L1 TO 10~H OR 20~H FOR HIGHER CURRENT APPLICATIONS.
SEE APPLICATIONS INFORMATION
•• MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

"'""m

Figure 17. Positive-la-Negative Converter

Inverting regulators differ from buck regulators in the
basic switching network. Current is delivered to the output
as square waves with a peak-to-peak amplitude much
greater than load current. This means that maximum load
current will be significantly less than the LT1376's 1.SA
maximum switch current, even with large inductor values.
The buck converter in comparison, delivers current to the
output as a triangular wave superimposed on a DC level
equal to load current, and load current can approach 1.5A

LT1375/LT 1376
APPLICATions InFoRmATion
with large inductors. Output ripple voltage forthe positiveto-negative converter will be much higher than a buck
converter. Ripple current in the output capacitor will also
be much higher. The following equations can be used to
calculate operating conditions forthe positive-to-negative
converter.
Maximum load current:

OUTPUT DIVIDER
If the adjustable part is used, the resistor connected to
VOUT (R2) should be set to approximately 5k. R1 is
calculated from:
R1 =R_2,,--(VO_UT_-_2.4--L2)
2.42

t

(\tiN )(VOUT ) ] ( ) (
)
Ip - (
)( )() VOUT \tiN - 0.5
2 VOUT + \tiN f L

IMAx =

(VOUT + V1N - 0.5)
(+)
VOUT
VF

Ip = Maximum rated switch current
VIN = Minimum input voltage
VOUT = Output voltage
VF = Catch diode forward voltage
0.5 = Switch voltage drop at 1.5A
Example: with VIN(MIN) = 4.7V, VOUT = 5V, L = 1O~, VF =
0.5V, Ip = 1.5A: IMAX = 0.52A. Note that this equation does
not take into account that maximum rated switch current
(Ip) on the LT1376 is reduced slightly for duty cycles
above 50%. If duty cycle is expected to exceed 50% (input
voltage less than output voltage), use the actuallp value
from the Electrical Characteristics table.

INDUCTOR VALUE
Unlike buck convertors, positive-to-negative converters
cannot use large inductor values to reduce output ripple
voltage. At 500kHz, values larger than 25~ make almost
no change in output ripple. The graph in Figure 18 shows
peak-to-peak output ripple voltage for a 5V to -5V converter versus inductor value. The criteria for choosing the
inductor is therefore typically based on ensuring that peak . , .
switch current rating is not exceeded. This gives the . .
lowest value of inductance that can be used, but in some
cases (lower output load currents) it may give avalue that
creates unnecessarily high output ripple voltage. A compromise value is often chosen that reduces output ripple.
As you can see from the graph, large inductors will not
give arbitrarily low ripple, but small inductors can give
high ripple.

Operating duty cycle:
150

DC=

r------,-,..------,----,-----,

VOUT + VF
V1N - 0.3 + VOUT + VF

(This formula uses an average value for switch loss, so it
may be several percent in error.)
With the conditions above:
DC _ _5_+_0_.5__ = 56%
4.7 -0.3+5+0.5
This duty cycle is close enough to 50% that Ip can be
assumed to be 1.5A.

10
15
20
INDUCTOR SIZE (~H)

25

Figure 18. Ripple Voltage on Posilive-to-Negative Converter

.L7lJ!J~

4-357

LT1375/LT 1376
APPLICATions InFoRmATion
The difficulty in calculating the minimum inductor size
needed is that you must first know whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current is 1.5A. The first step is to use
the following formula to calculate the load current where
the switcher must use continuous mode. If your load
current is less than this, use the discontinuous mode
formula to calculate minimum inductor needed. f load
current is higher, use the continuous mode formula.
Output current where continuous mode is needed:

ICONT =

(VIN)2(lpt
4(VIN+ VOUT)(VIN+ VOUT + VF)

Minimum inductor discontinuous mode:

In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
3~ for this application, but looking at the ripple voltage
chart shows that output ripple voltage could be reduced by
afactor of two by using a 15~ inductor. There is no rule
of thumb here to make afinal decision. If modest ripple is
needed and the larger inductor does the trick, go for it. If
ripple is noncritical use the smaller inductor. If ripple is
extremely critical, a second tilter may have to be added in
any case, and the lower value of inductance can be used.
Keep in mind that the output capacitor is the other critical
factor in determining output ripple voltage. Ripple shown
on the graph (Figure 18) is with a capacitor ESR of 0.1n.
This is reasonable for an AVX type TPS "D" or "E" size
surface mount solid tantalum capacitor, but the final capacitor chosen must be looked at carefully for ESR characteristics.

Ripple Current in the Input and Output Capacitors

Minimum inductor continuous mode:

For the example above, with maximum load current of
0.25A:

Positive-to-negative converters have high ripple current in
both the input and output capacitors. For long capacitor
lifetime, the RMS value of this current must be less than
the high frequency ripple current rating of the capacitor.
The following formula will give an approximate value for
RMS ripple current. This formula assumes continuous
mode and large inductor value. Small inductors will give
somewhat higher ripple current, especially in discontinuous mode. The exact formulas are very complex and
appear in Application Note 44, pages 30 and 31. For our
purposes here I have simply added afudge factor (ff). The
value for ff is about 1.2 for higher load currents and
L~1 O~. It increases to about 2.0 for smaller inductors at
lower load currents.

ICONT =
Capacitor IRMs = (ff)(loUT
This says that discontinuous mode can be used and the
minimum inductor needed is found from:

)~VOUT
V1N

ff = Fudge factor1 (1.2 to 2.0)

Diode Current
L MIN-

2(5)(0.25)
(500e3)(1.5)

2

2.211H
/""

Average diode current is equal to load current. Peak diode
current will be considerably higher.
1Normally, Jamoca Almond

4-358

LTl 375/LT 1376
IPPLICATlons InFORmATion
eak diode current:

Dual Output SEPIC Converter

Continuous Mode =

(VIN + VOUT)
(VIN)(VOUT)
lOUT
VIN
+ 2(L)(f)(VIN + VOUT )
Discontinuous Mode =

2(loUT)(VOUT)

(L)(f)

aep in mind that during start-up and output overloads,
lerage diode current may be much higher than with
xmalloads. Care should be used if diodes rated less than
~ are used, especially if continuous overload conditions
lust be tolerated.

The circuit in Figure 19 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard Coiltronics inductor. The topology for the 5V
output is a standard buck converter. The -5V topology
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates the SEPIC
(Single-Ended Primary Inductance Converter) topology
which improves regulation and reduces ripple current in
L1. For details on this circuit see Design Note 100.

D2
1N914

•

_ _~~~~j-_ _ ~~TPUT

GND-~----~-+--~-~---+---'

• L1 IS A SINGLE CORE WITH lWO WINDINGS
COILTRONICS #CTX1 0-2P
•• AVXTPSD107M010
t IF LOAD CAN GO TO ZERO. AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION

!375/76F19

Figure 19. Dual Output SEPIC Converter

iELATED PARTS
lRT NUMBER

DESCRIPTION

COMMENTS

1074/LT1 076

Step-Down Switching Regulator

40V Input, 100kHz, SA and 2A
External FET Switches

C1148

High Efficiency Synchronous Step-Down Switching Regulator

C1149

High Efficiency Synchronous Step-Down Switching Regulator

External FET Switches

C1174

0.5A, 150kHz Burst Mode'· Dperation

1176

High Efficiency Step-Down and Inverting DC/DC Converter
Step-Down Switching Regulator

13721LT1377

500kHz and 1MHz High Efficiency 1.5A Switching Regulators

Boost Topology

PDIP LT1076

's! Mode is a trademark of Linear Technology Corporation.

4-359

~7~lO~~--H-ig-h-p-O-w-e-r-S-t-e-~-~~-O-1:_3_~
Switching Regulator Controller
FEATURES

DESCRIPTion

• High Power 5V to 3.xV Switching Controller:
Can Exceed 10A Output
• All N-Channel External MOSFETs
• Constant Frequency Operation-Small L
• Excellent Output Regulation: ±1% Over Line, Load
and Temperature Variations
• High Efficiency: Over 95% Possible
• Fixed Frequency Operation
• No Low Value Sense Resistor Needed
• Outputs Can Drive External FETs with Up to
1O,OOOpF Gate Capacitance
• Quiescent Current: 350j.tA Typ, 1j.tA in Shutdown
• Fast Transient Response
• Adjustable or Fixed 3.3V Output
• Available in 8- and 16-Lead POI Pand SO Packages

The LTC®1430 is a high power, high efficiency switching
regulator controller optimized for 5V to 3.xV applications.
It includes a precision internal reference and an internal
feedback system that can provide output regulation of ±1%
over temperature, load current and line voltage shifts. The
LTC1430 uses a synchronous switching architecture with
two N-channel output devices, eliminating the need for a
high power, high cost P-channel device. Additionally, it
senses output current across the drain source resistance of
the upper N-channel FET, providing an adjustable current
limit without an external low value sense resistor.

APPLICATions
• Power Supply for P6™ and Pentium®
Microprocessors
• High Power 5V to 3.xV Regulators
• Local Regulation for Dual Voltage Logic Boards
• Low Voltage, High Current Battery Regulation

The LTC1430 includes afixed frequency PWM oscillatorfor
low output ripple under virtually all operating conditions.
The 200kHz free-running clock frequency can be externally
adjusted from 100kHz to above 500kHz. The LTC1430
features low 350j.tA quiescent current, allowing greater
than 90% efficiency operation in converter designs from
1A to greater than 50A output current. Shutdown mode
drops the LTC1430 supply current to 1j.tA.
D, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
P6 is a trademark of Intel Corporation.

TYPICAL APPLICATiOn
Efficiency

Typical 5V 10 3.3V, 10A Application
100

5V

TA =25'C
PVcc =5V
VOUT =3.3V

90

~

80

J

1';

1D 70
U

3.3V
10A

~

60
50

/

-

V

/

40
0.1

1

LOAD CURRENT (A)
M1A, M1 B, M2: MOTOROLA MTD20N03HL
CIN: AVX-TPSE227M010R0100
Cour: AVX-TPSE337M006R0100

4-360

10

LTC 1430
BSOLUTE mAXimum RATinGS
ate 1)

Ipply Voltage
VCC ....................................................................... 9V
PVCC1,2 .............................................................. 13V
put Voltage
IFS ......................................................... -0.3Vto 18V
All Other Inputs ......................... -0.3V to Vcc + 0.3V

Operating Temperature Range .................... O°C to 70°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ACKAGE/ORDER InFORmATiOn
ORDER
PART NUMBER

TOP VIEW

LTC1430CN8
LTC1430CS8

G108G2

PVCC1

2

GND

3

7 VCC/PVCC2

6

FB 4
N8 PACKAGE
HEAD PDIP

ORDER
PART NUMBER

TOP VIEW

PVCC1

2

LTC1430CN
LTC1430CS

PGND
GND

CaMP

5 SHDN
S8 PACKAGE
HEAD PLASTIC so

S8 PART MARKING
1430

TJMAX = l50'C, 9JA = 100°C/W (N8)
TJMAX = 150°C, 9JA = l50°C/W (S8)

SENSE'
SHDN

N PACKAGE
1HEAD PDIP

S PACKAGE
l6-LEAD PLASTIC

so

TJMAX = 150°C, 9JA = 70°C/W (N)
TJMAX =150°C, 9JA =110°C/W (S)

lsult factory for Industrial and Military grade parts,

LECTRICAL CHARAOERISTICS

(Note 2) Vee =5V, TA =25°C unless otherwise noted.

MBOL

PARAMETER

;

Supply Voltage

;C

PVeel, PVee2
Output Voltage

Figure 1

Feedback Voltage

Figure 1, SENSE' and SENSE Floating

3UT

Output Load Regulation
Output Line Regulation

Figure 1, lOUT = OA to lOA (Note 3)
Figure 1, Vee = 4.75V to 5.25V (Note 3)

e

Supply Current (Vee Only)

ee

Supply Current (PVec)

Figure 2, VSHDN = Vee
VSHDN = OV
Figure 2, PVee = 5V, VSHDN = Vee (Note 4)
VSHDN = OV
FREQSET Floating

JT

~

Internal Oscillator Frequency

CONDITIONS

SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current

v

Error Amplifier Transconductance

I

ILiM Amplifier Transconductance

l7lJD~

(Note 5)

MIN

•
•
•

TYP

MAX

V

13

V

1,265

1.28

V
V

5
1

20
5

mV
mV

350
1
1.5
0.1

700
10

200

260

~
~
mA
~
kHz

3,30

•
••
•

1.25

•
•
•
•

140

UNITS

8

4

V

2.4
0.8
±0.1

±1

V
~

650

tJMho

1300

tJMho

4-361

LTC1430
ELEORICAL CHARAOERISTICS

(Note 2) Vee = 5V, TA =25°C unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

IMAX

IMAX Sink Current
Soft Start Source Current

VI(MAX) =Vee

Driver Rise/Fall Time

=PVec2 =5V
Figure 3, PVee1 =PVCC2 =5V
VCOMP =Vcc

Iss
t" ts
tNOV
DCMAX

Driver Non-Overlap Time
Maximum Duty Cycle

Vss =0
Figure 3, PVCC1

The. denotes specifications which apply over the full operating
temperature range.
Nole 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Nole 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Nole 3: This parameter is guaranteed by correlation and is not tested
directly.

Pin FunCTions

•
•

TYP

MAX

8
-8

12
-12

16
-16

~

80

250

I

130

250

I

90

96

25

•

UNIl

MIN

~

,

Nole 4: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary witt
the LTC1430 operating frequency, operating voltage and the external FETi
used.
Note 5: The ILiM amplifier can sink but cannot source current. Under
normal (not current limited) operation, the ILiM output current will be zere

(16-Lead Package/8-Lead Package)

G1 (Pin 1/Pin 1): Driver Output 1. Connect this pin to the
gate ofthe upper N-channel MOSFET, M1. This output will
swing from PVCCl to PGND. It will always be low when G2
is high.

tive terminal. FB should be left floating in applications the
use the internal divider. To use an external resistor dividl
to set the output voltage, float SENSE+ and SENSE- an
connect the external resistor divider to FB.

PVCC1 (Pin 2IPin 2): Power Vcc for Driver 1. This is the
power supply input for G1. G1 will swing from PGND to
PVCC1. PVCC1 must be connected to a potential of at least
PVCC + VGS(ON)(M1). This potential can be generated
using an external supply or a simple charge pump connected to the switching node between the upper MOSFET
and the lower MOSFET; see Applications Information for
details.

SHDN (Pin 8IPin 5): Shutdown. A TIL compatible 10'
level at SHDN for longer than 50f..lS puts the LTC1430 in1
shutdown mode. In shutdown, G1 and G2 go low, a
internal circuits are disabled and the quiescent currer
drops to 1O~ max. ATIL compatible high level at SHD
allows the part to operate normally.

PGND (Pin 3/Pin 3): Power Ground. Both drivers return to
this pin. It should be connected to alow impedance ground
in close proximity to the source of M2. 8-lead parts have
PGND and GND tied together at pin 3.
GND (Pin 4/Pin 3): Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, GND should be connected to
PGND right at the LTC1430. 8-lead parts have PGND and
GND tied together internally at pin 3.
SENSE-, FB, SENSE+ (Pins 5, 6, 7IPin 4): These three
pins connect to the internal resistor divider and to the
internal feedback node. To use the internal divider to set
the output voltage to 3.3V, connect SENSE +to the positive
terminal of the output capacitor and SENSE - to the nega-

4-362

SS (Pin 9/NA): Soft Start. The SS pin allows an extem
capacitor to be connected to implement asoft start fUn!
tion. An external capaCitor from SS to ground controls t~
start-up time and also compensates the current limit 1001
allowing the LTC1430 to enter and exit current lim
cleanly. See Applications Information for more details.
COMP (Pin 10/Pin 6): External Compensation. The COM
pin is connected directly to the output ofthe error amplifil
and the input of the PWM. An RC network is used at thi
node to compensate the feedback loop to provide opt
mum transient response. See Applications Information f(
compensation details.
FREQSET (Pin 11/NA): Frequency Set. This pin is used 1
set the free running frequency of the internal oscillato
With the pin floating, the oscillator runs at about 200kH
A resistor from FREQSET to ground will speed up tt

LTC 1430

lin FunCTions

(16-Lead Package/8-Lead Package)

scillator; a resistor to Vee will slow it down. See Applicaons Information for resistor selection details.
~AX (Pin l2/NA): Current Limit Set. IMAX sets the threshId for the internal current limit comparator. If IFB drops
elow IMAX with G1 on, the LTC1430 will go into current
mit.IMAX has a12!lA pull-down to GND. It can be adjusted
'ith an external resistor to PVee or an external voltage
)urce.

'8 (Pin l3/NA): Current Limit Sense. Connect to the
Nitched node at the source of M1 and the drain of M2
lrough a1kresistor. The 1kresistor is required to prevent
)Itage transients from damaging IFB. This pin can be
lken up to 18V above GND without damage.

Vee (Pin l4/Pin 7): Power Supply. All low power internal
circuits drawtheirsupplyfrom this pin. Connectto aclean
power supply, separate from the main PVee supply at the
drain of M1. This pin requires a 4.7J.IF bypass capacitor.
8-lead parts have Vee and PVee2 tied together at pin 7 and
require a 10J.IF bypass to GND.
PVee2 (Pin l5/Pin 7): Power Vee for Driver 2. This is the
power supply input for G2. G2 will swing from GND to
PVee2. PVee2 is usually connected to the main high power
supply. The 8-lead parts have Vee and PVee2 tied together
at pin 7 and require a 10J.IF bypass to GND.
G2 (Pin l6/Pin 8): Driver Output 2. Connect this pin to the
gate of the lower N-channel MOSFET, M2. This output will
swing from PVee2 to PGND.lt will always be low when G1
is high.

ILOCK DIAGRAm
DELAY
SHDN

DI--------1r-;::-lI----,
INTERNAL
L....::.J
SHUTDOWN

JlJlI------------.

FREQSET

1--------1

"N 1----01

PVCC1
G1
PVCC2
G2
PGND

FB
SENSE+

..=..1.26V

LTC1430·ao

-f

4-363

LTC 1430
TEST CIRCUITS
PVcc = 5V

FB MEASUREMENT

'------t..JYY'V'I_-_3.3V

NG

M1A, M1B, M2: MOTOROLAMT020N03HL
GIN: AVX-TPSE227M01OR0100
Gour AVX·TPSE337M006R0100

LTC1430'FOl

Figure 1
5V

- - . - - - - G1 RISE/FALL

NG
NG
NG
NG

- - . - - - - G2 RISEIFALL

lTCl430"n;03

Figure 2

Figure 3

APPLICATions InFoRmATion
OVERVIEW

The LTC1430 is avoltage feedback PWM switching regulator controller (see Block Diagram) designed for use in
high power, low voltage step-down (buck) converters. It
includes an onboard PWM generator, a precision reference trimmed to ±O,5%, two high power MOSFET gate
drivers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 200kHz,
The 16-lead versions of the LTC1430 include a current
limit sensing circuit that uses the upper external power

4-364

MOSFET as a current sensing element, eliminating thl
need for an external sense resistor.
Also included in the 16-lead version is an internal soft star
feature that requires only a single external capacitor t(
operate. In addition, 16-lead parts feature an adjustabli
oscillator which can run at frequencies from 50kHz t(
beyond 500kHz, allowing added flexibility in external com
ponent selection, The 8-lead versions do not includl
current limit, internal soft start or frequency adjustability

LTC 1430
~PPLICRTlons

InFORmRTlon

'HEORY OF OPERATION
'rimary Feedback Loop
he LTC1430 senses the output voltage of the circuit atthe
utput capacitor with the SENSE + and SENSE- pins and
~eds this voltage back to the internal transconductance
mplifier FB. FB compares the resistor-divided output
oltage to the internal 1.26V reference and outputs an
rror signal to the PWM comparator. This is then comared to afixed frequency sawtooth waveform generated
y the internal oscillator to generate a pulse width modulted signal. This PWM signal is fed back to the external
~OSFETs through G1 and G2, cloSing the loop. Loop
ompensation is achieved with an external compensation
etwork at COMP, the output node of the FB transconducmce amplifier.
UN, MAX Feedback Loops
wo additional comparators in the feedback loop provide
igh speed fault correction in situations where the FB
mplifier may not respond quickly enough. MIN compares
le feedback signal to a voltage 40mV (3%) below the
lternal reference. At this point, the MIN comparator
verrides the FB amplifier and forces the loop to full duty
vcle, set by the inte rnal osci lIator at about 90%. Si milarly,
le MAX comparator monitors the output voltage at 3%
bove the internal reference and forces the output to 0%
uty cycle when tripped. These two comparators prevent
dreme output perturbations with fast output transients,
rhile allowing the main feedback loop to be optimally
ompensated for stability.
urrent Limit Loop
he 16-lead LTC1430 devices include yet another feedack loop to control operation in current limit. The current
mit loop is disabled in 8-lead devices. The ILiM amplifier
lOnitors the voltage drop across external MOSFET M1
'ith the IFB pin during the portion of the cycle when G1 is
igh.lt compares this voltagetothe voltage atthe IMAX pin.
s the peak current rises, the drop across M1 due to its
OS(ON) increases. When IFB drops below IMAX, indicating
lat M1 's drain current has exceeded the maximum level,
.1M starts to pull current out of the external soft start

L7lJ!J~

capaCitor, cutting the duty cycle and controlling the output
current level. At the same time, the ILiM comparator
generates a signal to disable the MIN comparator to
prevent it from conflicting with the current limit circuit. If
the internal feedback node drops below about 0.8V, indicating asevere output overload, the Circuitry will force the
internal oscillator to slow down by a factor of as much as
100. If desired, the turn on time of the current limit loop
can be controlled by adjusting the size of the soft start
capacitor, allowing the LTC1430 to withstand short overcurrent conditions without limiting.
By using the ROS(ON) of M1 to measure the output current,
the current limit circuit eliminates the sense resistor that
would otherwise be required and minimizes the number of
components in the external high current path. Because
power MOSFET ROS(ON) is nottightly controlled and varies
with temperature, the LTC1430 current limit is not designed to be accurate; it is meant to prevent damage to the
power supply circuitry during fault conditions. The actual
current level where the limiting circuit begins to take effect
may vary from unit to unit, depending on the power
MOSFETs used. See Soft Start and Current Limit for more
details on current limit operation.
MOSFET Gate Drive
Gate drive for the top N-channel MOSFET M1 is supplied
from PVCC1. This supply must be above PVcc ( the main
power supply input) by at least one power MOSFET
VGS(ON) for efficient operation. An internal level shifter
allows PVCC1 to operate at voltages above Vcc and PVcc,
up to 13V maximum. This higher voltage can be supplied
with a separate supply, or it can be generated using a
simple charge pump as shown in Figure 4. When using a
separate PVCC1 supply, the PVcc input may exhibit a large
inrush current if PVCC1 is present during power up. The
90% maximum duty cycle ensures that the charge pump
will always provide sufficient gate drive to M1. Gate drive
forthe bottom MOSFET M2 is provided through PVCC2 for
16-lead devices or VcC/PVCC2 for 8-lead devices. PVCC2
can usually be driven directly from PVcc with 16-lead
parts, although it can also be charge pumped or connected
to an alternate supply if desired. The 8-lead parts require
an RC filter from PVcc to ensure proper operation; see
Input Supply Considerations.

4-365

LTC 1430
APPLICATions InFoRmATion
PVcc

OPTIONAL

US~ ~R!~C~ ~ -I--+-~H~--l-O-O-kH-Z-'-1-.2-5-A-S-W-it-~-~-~~-~
Regulator with Catch Diode

FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•

The LT®1572 is a 1.25A 100kHz monolithic switching
regulator with on-board switch and catch diode included
in one package. It combines an LT1172 with a1ASchottky
catch diode. The LT1572 can be operated in all standard
switching configurations, including boost, buck, SEPIC,
flyback, forward, inverting and "Cuk". All necessary control, oscillator and protection cirCUitry is included on the
die with the high efficiency switch. This makes the part
extremely easy to use and provides "bustproof" operation
similar to that obtained with 3-pin linear regulators.

Catch Diode Included in Package
Wide Input Voltage Range: 3V to 30V
Low Quiescent Current: 6mA
Internal1.25A Switch
Very Few External Parts Required
Self-Protected Against Overloads
Operates in Nearly All Switching Topologies
Shutdown Mode Draws Only 50J.IA Typical Current
Can Be Externally Synchronized

APPLICATions

The LT1572 operates with supply voltages from 3V to 30V
and draws only 6mA quiescent current. It can deliver load
power up to 15W with no external power devices. By
utilizing acurrent mode switching technique, the LT1572
achieves excellent response to load and line transients.

• 3.3V-to-5V and 5V-to-12V Boost Converters
• Negative-to-Positive Converter
• SEPIC Converter (Input Can Be Greater or
Less Than Output)
• Battery Charger

The LT1572 has many unique features not found on the
more difficult to use control chips presently available. It
uses adaptive anti-sat switch drive to allow very wide
ranging load currents with no loss in efficiency. An externally activated shutdown mode reduces total supply current to 50J.IA typical for standby operation. External synchronizing of switching frequency is pOSSible, with arange
of 120kHz to 160kHz.
LT. LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn

Boosl Converter Efficiency

5V·to-12V Boosl Converler
Ll'
VIN
4.5V ---.._ _......,.YT'~-...,
T010V

100
'COILTRONICS CTX50-2
•• AVX TPS OR SPRAGUE 593D
fALWAYS CONNECT BOTH ANODE (2, 15)
AND CATHODE (3, 14) PINS

~

[;

80

15

~

C3
100~F

70

/

~

/

-

+ C2'"

10V

100~F

16V

60

50

_

4-374

BOOST CONVERTER
VIN = 5V
Vour= 12V

90

LT1512'TAOl

o

50

100
150
200
LOAD CURRENT (rnA)

250

LT1572
ABSOLUTE mAXimum RATinGS
Supply Voltage (Note 4) .......................................... 40V
Switch Output Voltage (Note 4) .............................. 60V
Feedback Pin Voltage (Transient, 1ms) ................ ±15V
Operating Junction Temperature Range
Operating .............................................. O°C to 100°C
Short Circuit ......................................... O°C to 125°C
Storage Temperature Range ............... -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER
ANOOE' 2
CATHODE'
GND
vc
FB

LT1572CS

DIODE
Average Forward Current .......................................... 1A
Peak Repetitive Forward Current .............................. 2A
Peak Non-Repetitive Forward Current.. ..................... 3A
Peak Repetitive Reverse Voltage ............................. 20V
Continuous (Average) Reverse Voltage .................. 15V
Operating Junction Temperature ............ " ........... 125°C
Note 1: Minimum effective switch "on" time for the LT1572 (in current
limit only) is ~ 0.6!JS. This limits the maximum safe input voltage during
an output shorted condition. Buck mode and inverting mode input voltage
during an output shorted condition is limited to:
VIN (max, output shorted) = 15V + R x IL + VI
buck and inverting mode
txf
R= Inductor DC resistance
IL = 2.5A
VI = Output catch diode forward voltage at IL
t = 0.6!JS, f = 100kHz switching frequency

ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER

SPACKAGE
16·LEAD PLASTIC so
'ALWAYS CONNECT BOTH ANODE
AND BOTH CATHODE PINS
TJMAX (REGULATOR) = 100°C
TJMAX (DIODE) = 125°C
SEE THERMAL MANAGEMENT SECTION FOR BJA
Consult factory for Industrial and Military grade parts.
Maximum input voltage can be increased by increasing R or VI.
External current limiting such as that shown in AN19, Figure 39, will
provide protection up to the full supply voltage rating. C1 in Figure 39
should be reduced to 200pF.
Transformer designs will tolerate much higher input voltages because
leakage inductance limits rate of rise of current in the switch. These
designs must be evaluated individually to assure that current limit is well
controlled up to maximum input voltage.
Boost mode designs are never protected against output shorts because
the external catch diode and inductor connect input to output.

•

Y,N =15V, Vc =D.5V, VFB =VREF, output pin open, unless otherwise noted.

CONDITIONS

MIN

TYP

MAX

UNITS

VREF

Reference Voltage

Measured at Feedback Pin
Vc = O.BV

1.224
1.214

1.244
1.244

1.264
1.274

V
V

IB

Feedback Input Current

VFB = VREF

350

750
1100

nA
nA

gm

Error Amplifier
Transconductance

Alc=±25~

3000
2400

4400

6000
7000

!1mho
!1mho

Error Amplifier Source or
Sink Current

Vc= 1.5V

150
120

200

350
400

~
~

Error Amplifier Clamp
Voltage

Hi Clamp, VFB = 1V
Lo Clamp, VFB = 1.5V

2.30
0.52

V
V

Reference Voltage Line
Regulation

3V ~ VIN ~ 40V
Vc = O.BV
0.9V ~ Vc ~ 1.4V

0.03

%/V

Av

Error Amplifier Voltage Gain
Minimum Input Voltage (Note 3)

10

Supply Current

3V ~ VIN ~ 40V, Vc = 0.6V

•
•
•
•

LBO
0.25

0.38

•
500

•

BOO

V/V

2.6

3.0

V

6

9

mA

4-375

LT1572

ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
Control Pin Threshold

VIN

=15V, Vc =D.5V, VFB =VREF, output pin open, unless otherwise noted.

CONDITIONS

MIN

TYP

MAX

UNITS

Duty Cycle = 0

0.8
0.6

0.9

1.08
1.25

V
V

0.4

0.45

0.54

V

15.0
14.0

16.3

17.6
18.0

V
V

4.5

6.8

9

V

0.01

0.03

%N

150

300

500

Ilmho

15
25

32
40

70
70

IlA
IlA

60

80

NormaliFlyback Threshold
on Feedback Pin
VFB

Flyback Reference Voltage
(Note 3)

IFB = 50llA

Change in Flyback Reference
Voltage

0.05" IFB" lmA

Flyback Reference Voltage
Line Regulation (Note 3)

IFB = 50llA
7V" VIN "VMAX
~Ic = ±101lA

Flyback Amplifier
Transconductance (gm)
Flyback Amplifier Source
and Sink Current

Vc = 0.6V, Source
IFB = 50IlA, Sink

BV

Output Switch Breakdown
Voltage (Note 4)

3V" VIN " 40V, Isw = 1.5mA

VSAT

Output Switch
"On" Resistance (Note 1)

•
•

••
•
•

0.60

Control Voltage to Switch
Current Transconductance
ILiM

Switch Current Limit

~IIN
~Isw

Supply Current Increase
During Switch On-Time

f

Switching Frequency

DCMAX

Maximum Switch Duty Cycle

V
1.00

2
Duty Cycle = 50%, TJ ~ 25°C
Duty Cycle = 50%, TJ < 25°C
Duty Cycle = 80% (Note 2)

Shutdown Mode
Supply Current

3V" VIN" 40V
Vc = 0.05V

Shutdown Mode
Threshold Voltage

3V" VIN" 40V

Flyback Sense Delay Time (Note 3)

•

•
•
•
•

•

1.25
1.25
1.00

88
85
80

100
50

Q

A/V
3.0
3.5
2.5

A
A
A

25

35

mAlA

100

112
115

kHz
kHz

90

95

%

100

250

IlA

150

250
300

mV
mV

1.5

Ils

DIODE
PARAMETER

CONDITIONS

Forward Voltage (Note 5)

If = 200mA
If= 500mA
If= lA

Reverse Leakage (Note 5)

VR = 5V, TJ = 25°C
VR = 5V, TJ = 75°C

Diode Thermal Resistance

4-376

MIN

TYP

MAX

UNITS

0.45
0.52
0.55

0.57
0.65
0.70

V
V
V

1
25

5
100

VR = 20V, TJ = 25°C
VR = 20V, TJ = 75°C

3
70

15
300

!lA
!lA
!lA
!lA

(Note 6)

90

••
•

°C/W

LT1572
ELECTRICAL CHARACTERISTICS

VIN =15V, Vc =D.5V, VFB =VREF, output pin open, unless otherwise noted.
Nole 5: See graphs for guaranteed forward voltage and reverse leakage
current over temperature. Parameters are 100% tested at 25°C and
guaranteed at other temperatures by design and QA sampling.
Nole 6: Package soldered to FR4 board with ~1 oz copper and an internal
or backside plane underneath the package to aid thermal transfer. Diode is
partly thermally coupled to regulator section. See Application Information
section for details on thermal calculations.

fhe • denotes the specifications which apply over the full operating
temperature range, O°C to 100°C for the regulator chip and O°C to 125°C
lor the diode.
~ole 1: Measured with Vc in hi clamp, VFB = O.BV. Isw = 1A.
Mole 2: For duty cycles (DC) between 50% and BO%, minimum
luaranteed switch current is given by ILiM = 0.B33 (2 - DC).
Mole 3: Minimum input voltage for isolated flyback mode is 7V.
Mole 4: Because the catch diode has a peak repetitive reverse voltage of
1OV, diode breakdown may be the limiting factor on input voltage or
;witch voltage in many applications.

TYPICAL PERFORmAnCE CHARACTERISTICS
Switch Current Limit vs Duty Cycle

Minimum Input Voltage
2.9
_ 2.8
2:-

.......... ~1ITC~ CU~REN~ = 1125A

.......

w

-55°C
_125°C

-

~

-

t:;: :::::::

>- 2.6

:::>

"~

~

::;;

-=::::::::

:::>

::;

o

........

2.5

~ 1.4

r-....,

~

1.2

>

1.0

0

r-....

"

.........

I'- "-

z0

SWITCH CURRENT = OA........ ........ I'-

........

./ ~ ~

~ 0.8

~ ~ I'

cc

!;;c 0.6
en

:r

~ 0.4

~

2.4

.Y

100~C,./'

:::>

~

0.2

o

2.3
-75 -50 -25 0 25 50 75 100 125 150
TEMPERATURE (OC)

10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)

150~

w

co

Z

~

o

2.7

§;

25°C

Switch Saturation Voltage
1.6

"

o

~

":~oC

~V

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
SWITCH CURRENT (A)

1572001

Line Regulation

Feedback Bias Current vs
Temperature

Reference Voltage vs Temperature
1.250

-~J=15~7
f-TJ=~
-1

," /

-2
-3

-4
-5

I

o

/

~

~

VJ....-'

~

~1.246

~ 1.244

o

~ 1.242
z'-'

TJ = 25°C

800

1.248

~

/'

.,/

1.240

.........

ili
cc

cc 500

~

:::>
<.:>

........

......

~ 1.238

/
20
30
40
INPUT VOLTAGE (V)

50

60
1572G04

1.234
-75 -50 -25

en 400

"" 300

i"- r--....



0-

::>

35

;;;: 30

.s

a:

u

15

TJ =25'C

140

!5

Supply Current vs Input Voltage"

40

....

~

o

/'~

V

,/1/

V 1/

12

15
a:

11

a:

::>

V

u

Shutdown Mode Supply Current

TJ = ~ 25'C

4500

160

F4000

./

~
!5
u

120

-

100

-

./

~

80

g;

60 , /

0-

""

40

o

--

o

./

/'

""/ '

'"

./
-55'C:5 TJ'; 125'C





.s

1000

450

900

400

\:t:.s
350
w

I-

z

~
a:

VSUPPLV= 60V

::>

u

VSUPPLY- 3V

~

00-

::>

Switch" Off" Characteristics

500

;

300

~

250

G
;:a

200

r--..

--?c

r-

150'C

r-

.......

-

800

-55'C

r-l

1700

@ 150
~ 100



!ii
:D
~.

'"

-100.2::
Vc VOLTAGE IS REDUCED UNTIL
50 I-- I- REGULATOR CURRENT DROPS I-- -50
BELOW 300llA

:;:; 1.6

'" 1.4

-30

~

4000

gc 3000

60

\

18

I

~

17

-

L

tJOk

I I

15
-75 -50 -25 0 25 50 75 100 125 150
TEMPERATURE ('C)

-24

490

-22

E

...,

,.
:I:

90 ~

-a

:;:; 470

'"~ 460 I--

'-'

-12 ~
-10 ~

~ 420

180

410

lOOk
1M
FREQUENCY (Hz)

210
10M

~

-14

~ 440 I-- ~

150

-1000

(tT THIRESHO~ I-""

-20 FR
-18 ~
1';
-16 ""
...,

;:; 450

120.m

....

FEEDBACK PIN VOLTAGE

o

~ 1000

~

10k

19

""'-' 480

30

.;;
~

~

Normal/Flyback Mode Threshold on
Feedback Pin

7000

~

RjB =5bon

20

16

6000

~

21

'"

.....-V

Transconductance of Error
Amplifier

~ 5000

~

>

1.0
-75 -50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE ('C)

-75 -50 -25 0 25 50 75 100 125 150
TEMPERATURE ('C)

I I

0

VV

::;;

22

w

/

~

1.2

o

/

/

1.8

-250 ~

VOLTAGE_

23

-300 g.

. / I-""

§;

2.2

-400

..... ~

'[ 300
~

Isolated Mode Flyback Reference
Voltage

Flyback Blanking Time

;li 430
c

r-FE~DBACK PI~ CUR~ENT I-- -

~ r--.... (ATTHRESHOLD)

400
-50 -25

r-..l
0

r-

---

c:

-81
-6

-4
25 50 75 100 125 150
TEMPERATURE ('C)

4-379

LT1572
BLOCK DIAGRAm
16V

SWITCH
OUT
ANODE

~J--o CATHODE

LT1172

FB

>---4..... vc

SHUTDOWN
CIRCUIT

0.160

0.15V

-=-

E1'

E2

'ALWAYS CONNECT E1 TO GROUND

OPERATion
The LT1572 is a current mode switcher. This means that
switch duty cycle is directly controlled by switch current
rather than by output voltage. Referring to the block
diagram, the switch is turned "on" at the start of each
oscillator cycle. It is turned "off" when switch current
reaches apredetermined level. Control of output voltage is
obtained by using the output of a voltage sensing error
amplifier to set current trip level. This technique has
several advantages. First, it has immediate response to
input voltage variations, unlike ordinary switchers which
have notoriously poor line transient response. Second, it
reduces the 90° phase shift at mid-frequencies in the
energy storage inductor. This greatly simplifies closedloop frequency compensation under widely varying input
voltage or output load conditions. Finally, it allows simple
pulse-by-pulse current limiting to provide maximum switch
protection under output overload or short conditions.

4-380

Alow dropout internal regulator provides a2.3V supply for
all internal circuitry on the LT1572. This low dropout
design allows input voltage to vary from 3V to 40V with
virtually no change in device performance. A 100kHz
oscillator is the basic clock for all internal timing. It turns
"on" the output switch via the logic and driver circuitry.
Special adaptive anti-sat circuitry detects onset of saturation in the power switch and adjusts driver current instantaneouslyto limit switch saturation. This minimizes driver
dissipation and provides very rapid turn-off of the switch.
A 1.2V bandgap reference biases the positive input of the
error amplifier. The negative input is brought out for
output voltage sensing. This feedback pin has a second
function; when pulled low with an external resistor, it
programs the LT1572 to disconnect the main error amplifier output and connects the output ofthe flyback amplifier

LT1572
OPERATion
to the comparator input. The LT1572 will then regulate the
value of the flyback pulse with respect to the supply
voltage. 1 This flyback pulse is directly proportional to
output voltage in the traditional transformer coupled flyback
topology regulator. By regulating the amplitude of the
flyback pulse, the output voltage can be regulated with no
direct connection between input and output. The output is
fully floating up to the breakdown voltage of the transformer windings. Multiple floating outputs are easily obtained with additional windings. A special delay network
inside the LT1572 ignores the leakage inductance spike at
the leading edge of the flyback pulse to improve output
regulation.
The error signal developed at the comparator input is
brought out externally. This pin (Vc) has four different
functions. It is used for frequency compensation, current
limit adjustment, soft starting, and total regulator shutdown. During normal regulator operation this pin sits at a
voltage between O.9V (low output current) and 2.0V (high
output current). The error amplifiers are current output
(gm) types, so this voltage can be externally clamped for
adjusting current limit. Likewise, a capacitor coupled
external clamp will provide soft start. Switch duty cycle
goes to zero if the Vc pin is pulled to ground through a
diode, placing the LT1572 in an idle mode. Pulling the Vc
pin below O.15V causes total regulator shutdown, with
only 50~ supply current for shutdown circuitry biasing.
See AN19 for full application details.

Other Application Help
More circuits and application help for the LT1572 can be
found in the LT1172 data sheet, both in loose form and in
the 1994 Linear Databook Volume III. Extensive additional
help is contained in Application Note 19. All application
circuits using the LT1172 can also use the LT1572 as long
as the 20V maximum reverse voltage of the diode is not
exceeded. A CAD program called SwitcherCAD is also
available. This program can be used with the LT1572 by
simply treating the LT1572 as an LT1172 and ignoring the
predicted die temperature results obtained from
SwitcherCAD itself.
Thermal Management
Thermal management is particularly important with the
LT1572 because both switch and diode power dissipation
increase rapidly at low input voltage when using the
popular boosttopology. Regulator and diode die tempera- •
ture must be calculated separately because they are not
connected to an isothermal plane inside the package.
Diode plus regulator thermal resistance is approximately
70°C/Wwhen the LT1572 is soldered to 1oz copper traces
over an internal or backside copper plane using FR4 board
material. However, individual calculation of die temperature must take thermal coupling into account. To accomplish this, thermal resistance is broken into two sections,
a common (coupled) section and a second uncoupled
section. Die temperatures are calculated from:

E1 and E2 Pins

TREG = TA + PREG (90°C/W) + PDIODE (45°C/W)

The LT1572 has the emitters of the power transistor
IJrought out separately from the ground pin. This eliminates errors due to ground pin voltage drops and allows
the user to reduce switch current limit 2:1 by leaving the
second emitter (E2) disconnected. The first emitter (E1)
should always be connected to the ground pin. Note that
switch "on" resistance doubles when E2 is left open, so
~fficiency will suffer somewhat when switch currents
axceed 300mA. Also, note that chip diSSipation will actuilly increase with E2 open during normal load operation,
~ven though dissipation in current limit mode will decrease.

TDIODE = TA+ PDIODE (90°C/W) + PREG (45°C/W)
TA= ambient temperature
TREG = regulator die temperature
TDIODE = diode die temperature
PREG = total regulator power dissipation
PDIODE = diode power dissipation
The following formulas can be used as a rough guide to
calculate LT1572 power dissipation. For more details,the
reader is referred to Application Note 19 (AN19), "Efficiency Calculations" section.

ISee note under block diagram .

.L7lJ!J~

4-381

LT1572
OPERATion
Average supply current (including driver current) is:
liN'" 6mA + Isw(0.004 + DC/40)
Isw = switch current
DC = switch duty cycle
Switch power dissipation is given by:
Psw = (ISW)2 x Rsw x DC
Rsw = LT1572 switch "on" resistance (1Q maximum)
Total power dissipation is the sum of supply currenttimes
input voltage plus switch power:
PREG = liN x VIN + Psw
In a typical example, using a boost converter to generate
12V at 0.12A from a5V input, duty cycle is approximately
60%, and switch current is about 0.65A, yielding:
liN =6mA + 0.65(0.004 + DC/40) =18mA
Psw = (0.65)2 x 1Q x 0.6 = 0.25W
PREG = 5V x 0.018A + 0.25 = 0.34W
Approximate diode power dissipation for boost and buck
converters is shown below. For other topologies or more
accurate results, see Application Note 19 or use
SwitcherCAD.
Boost: POIOOE =lOUT x VI
Buck: POIOOE = lOUT x VI x (VIN - VouT)NIN
VI =diode forward voltage at acurrent equal to lOUT for a
buck converter and lOUT x VouTNIN for aboost converter.
In most applications, full load current is used to calculate
die temperature. However, if overload conditions must
also be accounted for, three approaches are possible.
First, if loss of regulated output is acceptable under
overload conditions, the internal thermal limit of the
LT1572 will protect the die in most applications by shutting off switch current. Thermal limit is not a tested
parameter, however, and should be considered only for
noncritical applications with temporary overloads.
The second approach for lower current applications is to
leave the second switch emitter (E2) open. This increases

4-382

switch "on" resistance by 2:1, but reduces switch current
limit by 2:1 also, resulting in a net 2:1 reduction in 12R
switch dissipation under current limit conditions.
The third approach is to clamp the Vc pin to avoltage less
than its internal clamp level of 2V. The LT1172 switch
current limit is zero at approximately 1Von the Vc pin and
2A at 2V on the Vc pin. Peak switch current can be
externally clamped between these two levels with adiode.
See AN19 for details.
Diode Characteristics
The catch diode used in the LT1572 is a power Schottky
diode with a very low storage time and low forward
voltage. This gives good efficiency in switching regulator
applications, but some thought must be given to maximum operating voltage and high temperature reverse
leakage. Peak repetitive reverse voltage rating on the diode
is 20V. In a boost converter, maximum· diode reverse
voltage is equal to regulated output voltage, so this limits
maximum output voltage to 20V. In anegative-to-positive
converter, maximum diode voltage will be equal to the
sum of output voltage plus input voltage. Use the equations in Application Note 19 or SwitcherCAD or calculate
maximum diode voltage for other topologies.
Diode reverse leakage increases rapidly with temperature.
This leakage is not high enough to significantly impact
efficiency or diode power dissipation, but it can be of
concern in shutdown mode if the diode is connected in
such a way that the leakage adds to regulator shutdown
current. Use the graphs of diode leakage versus voltage
and temperature to ensure proper high temperature system performance.
The LT1572 diode is internally bonded to more than two
package pins to reduce internal bond wire currents. All
pins must be used to prevent excessive current in the
individual internal bond wires. This is important in low
load current applications because the LT1572 will draw
high surge currents during start-up (to charge the output
capacitor) even with no output load current.

LT1572
OPERATion
Synchronizing

Synchronizing with Bipolar Transistor

The LT1572 can be externally synchronized in the frequency range of 120kHz to 160kHz. This is accomplished
as shown in the accompanying figures. Synchronizing
occurs when the Ve pin is pulled to ground with an external
transistor. To avoid disturbing the DC characteristics of
the internal error amplifier, the width of the synchronizing
pulse should be under O.3!lS. C2 sets the pulse width at ==
O.2!lS. The effect of a synchronizing pulse on the LT1572
amplifier offset can be calculated from:

l

KqT }S)(fs{le +

~~ J

C2
39pF

R1

~nn
FROM 5V
LOGIC

~~s=~~--~~--~

Ie
KT = 26mV at 25°C
q
ts =pulse width
fs = pulse frequency
Ie =Ve source current ("'200~)
Ve =operating Ve voltage (1 V to 2V)
R3 =resistor used to set mid-frequency "zero"
in frequency compensation network.
With ts =O.2!lS, fs =150kHz, Ve =1.5V, and R3 =2k, offset
lIoltage shift is ",3.8mV. This is not particularly bothersome, but note that high offsets could result if R3 were
reduced to a much lower value. Also, the synchronizing
transistor must sink higher currents with low values of R3,
50 larger drives may have to be used. The transistor must
be capable of pulling the Vc pin to within 200mVof ground
to ensure synchronizing.

•

Synchronizing with MOS Transistor

'SILICONIX OR EQUIVALENT

4-383

LT1572
TYPICAL APPLICATions
Negative Buck Converter

• REQUIRED IF INPUT LEADS ~ 2"
•• PULSE ENGINEERING 92114
COILTRONICS 50-2-52
C3'
100~F

_7VTO_2Vd~ - -.....- -.....- -......----<11-----'

Backlight CCFL Supply (see AN55 lor details)
INPUT VOLTAGEt
4.5VTO 20V - _ - - - - - - - - - - - - - - - - - - - . ,
1k

lO~F

50k
INTENSITY
AD,IUST

+

TANT
R3
10k
•
.,
•••
t

01,02 = BCP56 OR MPS650/561
COILTRONICS CTX300-4
SUMIDA 6345-020 OR COILTRONICS 110092-1
A MODIFICATION WILL ALLOW OPERATION DOWN TO 4.5V. CONSULT FACTORY.

RELATED PARTS
PART NUMBER

DESCRIPTION

LT1172

100kHz, 1.25A High Efficiency Switching Regulator

LT1572 Without Diode

LT1173

Micropower DC/DC Converter Adjustable and Fixed 5V, 12V

Operates Down to 2V Input

LT1372

500kHz High Efficiency 1.5A Step-Up Switching Regulator

Latest Technology, Uses Tiny Inductors

LTC1574

High Efficiency Step-Down DC/DC Converter
with Internal Schottky Diode

LTC1174 with Diode

4-384

R1
5600

COMMENTS

L.YLln-l=AD

LTC 1574
LTC 1574-3.3/LTC 1574-5

U ,

TECHNOLOG~~~-H-ig-h--Ef-fi-c-ie-n-C-y-St-e-p---D-O-w-n

DC/DC Converters
with Internal Schottky Diode
FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•
•
•
•
•

The LTC@157 4 is a family of easy-to-use current mode
DC/DC converters ideally suited for 9V to 5V, 5V to 3.3V
and inverting operation. With an internal 0.90 switch (at
asupply voltage of 12V) and a low forward drop Schottky
diode (0.450V typ at 200mA, TA = 25°C), the LTC1574
requires only three external components to construct a
complete high efficiency DC/DC converter.

High Efficiency: Up to 94%
Usable in Noise-Sensitive Products
Peak Inductor Current Independent of Inductor Value
Short-Circuit Protection
Internal Low Forward Drop SchoHky Diode
Only Three External Components Required
Wide VIN Range: 4V to 18.5V (Absolute Maximum)
Low Dropout Operation
Low-Battery Detector
Pin Selectable Current Limit
Internal 0.90 Power Switch: VIN = 12V
Standby Current: 1301lA
Active Low Micropower Shutdown

The maximum inductor current of the LTC1574 family is
pin selectable to either 340mA or 600mA, optimizing
efficiency for awide range of applications. Operation up to
200kHz permits the use of small surface mount inductors
and capacitors.

APPLICATions
•
•
•
•
•
•

Under no load condition, the LTC1574 draws only 1301lA.
In shutdown, it draws a mere 21lA making this converter
ideal for battery-powered applications. In dropout, the
internal P-channel MOSFET switch is turned on continuously allowing the user to maximize the life of the battery _
source.
..

Inverting Converters
Step-Down Converters
Memory Backup Supply
Portable Instruments
Battery-Powered Equipment
Distributed Power Systems

For applications requiring higher output current or ultrahigh efficiency, seethe LTC1148 and LTC1265 data sheets.
For detailed applications information, see the LTC1174
data sheet.

U, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
L1C1574-5 Efficiency

High Efficiency Slep-Down Converter
100
VIN
5.5Vto
16V

22~F'

"*35V

~ 90
>
u
iii 85
(3

5V
175mA

~

80

100~F'

10V

L= 100~H
VOUT = 5V
IpGM = OV

95

75
70

VINU

~
VIN = 9V

/'

I~I

rL
1

10

100 200

LOAD CURRENT (rnA)

4-385

LTC 1574
LTC 1574-3.3/LTC 1574-5
ABSOLUTE mAXimUm RATinGS

PACKAGE/ORDER InFORmATion

(Voltage Referred to GND Pin)
Input Supply Voltage (Pin 5) .................. -O.3V to 18.5V
Switch Current (Pin 3, 14) ........................................ 1A
Switch Voltage (Pin 3, 14) .......................... VIN -18.5V
Operating Temperature Range .................... ODC to 70DC
Junction Temperature (Note 1) ............................ 125DC
Storage Temperature Range ................. -65 DCto 150DC
Lead Temperature (Soldering, 10 sec) .................. 300DC

ORDER PART
NUMBER
LTC1574CS
LTC157 4CS-3.3
LTC157 4CS-5

SPACKAGE
16-LEAD PIJ\STIC SO
•ADJUSTABLE OUTPUT VERSION
TJMAX =125°C, BJA =11 O°C/W
Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS TA =25°C, VIN =9V, VSHUTDOWN =VIN, IpGM =OV, unless otherwise specified.
SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

1

~

1.20

1.25

1.30

V

3.14
4.75

3.30
5.00

3.46
5.25

V
V

10

70

mV

IFB

Feedback Current into Pin 10

LTC1574

VFB

Feedback Voltage

LTC1574

VOUT

Regulated Output Voltage

LTC1574-3.3
LTC1574-5

AVOUT

Output Voltage Line
Regulation

VIN = 6V to 12V, ILOAD = 100mA, IpGM = VIN (Note 2)

Output Voltage Load
Regulation

LTC1574-3.3 (Note 2)

20mA < ILOAD < 175mA, IpGM = OV
20mA < ILOAD < 400mA, IpGM = VIN

-5
-45

-70
-70

mV
mV

LTC1574-5 (Note 2)

20mA < ILOAD < 175mA, IPGM = OV
20mA < ILOAD < 400mA, IpGM = VIN

-5
-50

-70
-70

mV
mV

450
130
2

600
180
25

~
~
~
V

10

Input DC Supply Current (Note 3)
Active Mode
Sleep Mode
Shutdown (Note 4)

4V < VIN < 16V, IpGM = OV
4V-

"ijj
i3

~

70

JIJL

r-,/

II

~
Y,N =9V

C

~ 80

10
100
LOAD CURRENT (rnA)

7S
70

SOO

lJsl!41
ill
V

~ 80
>-

~
70
60
SO

93

V

~
ijj

92

~

'/

L=SOflH
VOUP SV
IpGM =Y,N
COIL II,CTXSO-4

I

10
100
LOAD CURRENT (rnA)

1

CTXSO-4P

--

89

1

I

I

~ 100

II

10
100
LOAD CURRENT (rnA)

80

20
SOO

o

o

20

'\
S 6

7

8 9 10 11 12 13 14
INPUT VOLTAGE (V)

-

-

40
60
80
TEMPERATURE (OC)

1\
9: 1.3 \
g

1.2

,

~

1.1

I\,

1.0

J

.......

0.9
0.8

./

f-

,

TA=25'C_

1.4

en

II

"" 60
~ 40

VOUT =3.3V
11,~fM =Y,N

'\ ~\

V

1.7
1.6
1.S

Y,N =13.SV

::::I

Y,N =SV

I
\

Switch Resistance vs
Input Voltage

lz

~

ILOAD =300mA
IpGM =Y,N

90
400

:;c 140
.s 120

"

I II
ILOAD =100mA_
r\ ,\GM=OV

91

Switch Leakage Current
vs Temperature
160

L=100flH
._
cO'i=cror

""'-,

i3

IV

180

90

~

-

C

Y,N =9V

8S

i3

100

i3

~

I

VOU~= s~

...

94

IJ'~~6V

90

Efficiency Using Different Types
of Inductor Core Material

"ijj

IIIII

>-

"ijj

L=SOflH
Voup3.3V
IpGM =Y,N
COIL =CTXSO-4

1

9S

9S

VI
I

60
SO

Efficiency vs Input Voltage

Efficiency vs Load Current
100

100

100

.........

0.7

4

8

.........

..........

10 12 14 16
INPUT VOLTAGE (V)

18

20

4-387

LTC 1574
LTC 1574-3 .3/LTC 1574-5
Pin FunCTions
NC (Pins 1, 8, 9, 16):No Connection.
GND (Pins 2, 4, 13, 15):Ground.
SW (Pins 3, 14): Drain of P-Channel MOSFET Switch and
Cathode of Schottky Diode.
VIN (Pin 5): Input Supply Voltage. It must be decoupled
close to ground (Pin 4).
iPGM (Pin 6): This pin selects the current limit of the
P-channel switch. With IpGM = VIN, the currenttrip point is
600mA and with IpGM = OV, the current trip point is
reduced to 340mA.

VOUT or VFB (Pin 10): For the LTC1574, this pin connects
to the main voltage comparator input. On the LTC1574-5
and LTC1574-3.3, this pin goes to an internal resistive
divider which sets the output voltage.
LBoUT (Pin 11): Open drain of an N-Channel Pull-Down.
This pin will sink current when (Pin 12) LBIN goes below
1.25V.
LBIN (Pin 12): The (-) Input of the Low-Battery Voltage
Comparator. The (+) input is connected to a reference
voltage of 1.25V.

SHDN (Pin 7): Pulling this pin to ground keeps the internal
switch off and puts the LTC1574 in micropower shutdown.

APPLICATions InFoRmATion
Operating Frequency and Inductor
Since the LTC157 4 utilizes aconstant off-time architecture,
its operating frequency is dependent on the value OfVIN. The
frequency of operation can be expressed as:
f = _1_("1N - VOUTJ
tOFF "1N + VD

IpGM pin, the limit is either set to 340mA or 600mA. In
addition, the off-time of the switch is increased to allow the
inductor current to decay far enough to prevent any current
build-up (see Figure 1).

(HZ)

where tOFF = 4115 and VD is the voltage drop across the
internal Schottky diode. Note that the operating frequency
is a function of the input and output voltage.
Although the size of the inductor does not affect the frequency or inductor peak current, it does affect the ripple.
current. The peak-to-peak ripple current is given by:
IRiPPLE

= 4 x 10-6(VOUTL+ Vo) (Ap_p )

By choosing asmaller inductor, a low ESR (Effective Series
Resistance) outputfilter capacitor has to be used. Core loss
will increase due to higher ripple current.
Short-Circuit Protection
The LTC1574 is protected from output short circuits by its
internal current limit. Depending on the condition of the

4-388

L=100iM
VIF 13.5V

20~/DIV

Figure 1. Inductor Current with Output Shorted

Low-Battery Detector
The low-battery indicator senses the input voltage through
an external resistive divider. This divided voltage connects
to the "-" input of a voltage comparator (Pin 12) which is
compared with a1.25Vreference voltage. With the current

LTC 1574
LTC 1574-3,3/LTC 1574-5
APPLICATions InFoRmATion
going into Pin 12 being negligible, the following expression is used for setting the trip limit:
VLBTRIP = 1.25(1 +

:~)

R4

difference between the absolute maximum voltage rating
and the output voltage. Amaximum of 12V is specified in
Figure4, giving the circuit 1.5Vof headroomforVIN. Note
that the circuit can operate from a minimum of 4V,
making it ideal for a four NiCd cell application. For a
higher output current circuit, please refer to the Typical
Applications section.
INPUT VOLTAGE
4V TO 12V

R3

Figure 2. Low-Batlery Comparator

LTC1574 Adjustable Applications
The LTC157 4 develops a 1.25V reference voltage between
the feedback terminal (Pin 10) and ground (see Figure 3).
By selecting resistor R1, a constant current is caused to
flow through R1 and R2 to set the overall output voltage.
The regulated output voltage is determined by:
VOUT = 1.25(1 +

2 x 47;>F·
16V

":"

VOUT
- - - - - - - + - - - -5V

L...-_ _ _

u

45mA

" AVX TPSD476K016
COILTRONICS CTX50-4

1574-F04

Figure 4. Positive-to-Negative 5V Converter

Low Noise Regulators

~~)

For most applications, a 30k resistor is suggested for R1.
To prevent stray pickup, a 100pF capacitor is suggested
across R1 located close to the LTC1574.
VOUT

R2

100pF

R1

In some applications it is important not to introduce any
switching noise within the audio frequency range. Due to
the nature ofthe LTC1574 during Burst Mode™ operation,
there is a possibility that the regulator will introduce audio
noise at some load currents. To circumvent this problem,
a feed-forward capacitor can be used to shift the noise
spectrum up and out of the audio band. Figure 5 shows the
low noise connection with C2 being the feed-forward
capacitor. The peak-to-peak output ripple is reduced to
30mVoverthe entire load range. Atoroidal surface mount
Burst Mode is a trademark of Linear Technology Corporation

.---_ _......._ _----F"
T10V

Figure 3. LTC1574 Adjustable Configuration

Inverting Applications
The LTC1574 can easily be set up for a negative output
voltage. If -5V is desired, the LTC157 4-5 is ideal for this
application as it requires the least components. Figure 4
shows the schematic for this application. Note that the
output voltage is now taken off the GND pins. Therefore,
the maximum input voltage is now determined by the

5V

VOUT

=...rvYY''--1~~---'_ 3.3V

425mA
100;>F"
10V

":"

" AVXTPSD107K010
"" COILTRONICS CTX1 00-4

1574'F05

Figure 5. Low Noise 5V to 3.3V Regulator

4-389

LTC 1574
LTC 1574-3.3/LTC 1574-5
APPLICATions InFoRmATion
inductor L1 is chosen for its excellent self-shielding properties. Open magnetic structures such as drum and rod
cores are to be avoided since they inject high flux levels
into their surroundings. This can become a major source
of noise in any converter circuit.
Design Example
As a design example, assume VIN = 9V (nominal),
VOUT = SVand lOUT = 3S0mA maximum. The LTC1S74-S
is used forthis application with IpGM (Pin 6) connected to
VIN. The minimum value of L is determined by assuming
the LTC1S74-S is operating in continuous mode.
--- AVG CURRENT = lOUT

IRIPPLE = 4 x 10-6(VOUTL+ VD)

Solving for L in the above equation and with VD = O.SV,
L = 44~. The next higher standard value of L is SO~
(example: Coiltronics CTXSO-4). The operating frequency,
ignoring voltage across diode VD is:
f",,2.SX105(1- VOUT)
VIN
= 111kHz
With the value of L determined, the requirements for CIN
and COUT are calculated. For CIN, its RMS current rating
should be at least:

IpEAK + Iv

-2-

=350mA

TIME

)t

IOUT[VOUT(VIN - VOUT 2
'Ii
(ARMS)
IN
=174mA
For COUT, the RMS current rating should be at least:
IRMS =

1574·F06

Figure 6. Continuous Inductor Current

With lour=3S0mAand IpEAK=O.6A(lpGM=VIN), Iv=O.1A.
The peak-to-peak ripple inductor current, IRIPPLE, is O.SA
and is also equal to:

_lpEAK
RMS --2-

I

=300mA

TYPICAL APPLICATiOnS
low Noise, High EHiciency 3.3V Regulator
4VTO 12~~~~--""----""-'----'

VOUT

=-rn"Yr'----.........-~~-+- 3.3V

450mA

• AVX TPSD226K025
•• AVXTPSD107K010
t COILTRONICS CTX50-4

4-390

(Ap_p)

1574TA03

LTC 1574
LTC 1574-3.3 /LTC 1574-5
TYPICAL APPLICATions
Low Dropout 5V Step-Down Regulator with Low-Battery Detection
VIN
5.5V to 12.5V

'LOWBATTERY
INDICATOR

, LOW-BATTERY INDICATOR IS
SET UP TO TRIP ATVIN = 5.5V
" AVX TPSD476K016

162k

t SELECTION
MANUFACTURER
COILTRONICS
SUMIDA
GOWANDA

PART NO.
CTX100-4
CD75-101
GA10-l03K

TYPE
SURFACE MOUNT
SURFACE MOUNT
THROUGH HOLE

~~~~~____~_____ ~UT

471'F" 365rnA
16V

47.5k

x2

High Efficiency 3.3V Regulator

4VTO

VOUT

.;;:.;..:.-rryy'-_+-___ 3.3V
471'F'
16V

425rnA

x2

, AVX TPSD226K025
" AVX TPS0476K016
t COILTRONICS CTX50-4

Positive to -5V Converter
VIN
4VTO 12.5V

, LOW-BATTERY INDICATOR IS
SEllO TRIP AT VIN = 4.4V
., AVX TPSDl 06K035
••• AVX TPSDl 07KOl 0

4.7k
'LOWBATTERY
INDICATOR

t SELECTION
MANUFACTURER
COILTRONICS
COILCRAFT
SUMIDA
GOWANDA

PART NO.
CTX50-3
DT3316-473
CD54-470
GA10-472K

TYPE
SURFACE MOUNT
SURFACE MOUNT
SURFACE MOUNT
THROUGH HOLE

10
12.5

lOUT (rnA)
110
140
170
200
235

L-____________________~------------------~~-----~~~

4-391

LTC 1574
LTC 1574-3.3 /LTC 1574-5
RELATED PARTS
PART NUMBER
LT"'1076

DESCRIPTION
Step-Down Switching Regulator

COMMENTS
2A Monolithic Bipolar Switcher for VIN to 60V

LTC1174

High Efficiency Step-Down/Inverting DC/DC Converter

Same as LTC1574 Without Schottky Diode in SO-8 Package

LTC1265

1.2A, High Efficiency Step-Down DC/DC Converter

Current Mode with 0.3(.1 Switch for Higher Current

LT1375/LT1376

1.5A. 500kHz Step-Down Switching Regulator

High Frequency, Synchronizable in SO-8 Package

4-392

INDEX
SECTION 4-POWER PRODUCTS
PCMCIA HOST AND CARD POWER MANAGEMENT DEViCES .................................................................... 4-393
LT1106, Micropower Step-Up OC/DC Converter for PCMCIA Card Flash Memory ........................................ 4-146
LTC1262, 12V, 30mA Flash Memory Programming Supply .. ................................................................. 4-34
LT1312, Single PCMCIA VPP Oriver/Regulator ................................................................................ 4-394
LT1313, Dual PCMCIA VPP Oriver/Regulator ................................................................................... 4-405
LTC1314/LTC1315, PCMCIA Switching Matrix with Built-In N-Channel Vee Switch Drivers ............................. 4-415
LTC1470/L TC1471, Single and Dual PCMCIA Protected 3. 3V/5 V Vee Switches ........................................... 4-426
LTC1472, Protected PCMCIA Vee and VPP Switching Matrix .. .............................................................. 4-437

II

4-393

f"'-LlneJ\Q~_ _L_T1312

~,

TECHNOLOGY

Single PCMCIA
VPP Driver/Regulator

FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•
•
•

The LT®1312 is a member of Linear Technology
Corporation's family of PCMCIA drivers/regulators. The
LT1312 provides OV, 3.3V, 5V, 12V and Hi-Z regulated
power to the VPP pin of a PCMCIA card slot from asingle
unregulated 13Vto 20V supply. When used in conjunction
with a PC card interface controller, the LT1312 forms a
complete minimum component-count interface for palmtop, pen-based and notebook computers. The VPP output
voltage is selected by two logic compatible digital inputs
which interface directly with industry standard PC card
interface controllers.

Digital Selection of DV, Vcc, 12V or Hi-Z
12DmA Output Current Capability
Internal Current limiting and Thermal Shutdown
Automatic Switching from 3.3V to 5V
Powered from Unregulated 13V to 20V Supply
Logic Compatible with Standard PCMCIA Controllers
1~ Output Capacitor
30~ Quiescent Current in Hi-Z or OV Mode
VPP Valid Status Feedback Signal
No VPP Overshoot
8-Pin SO Packaging

Automatic 3.3V to 5V switching is provided by an internal
comparator which continuously monitors the PC card Vee
supply and automatically adjusts the regulated VPP output to match Vee when the VPP =Vee mode is selected.

. APPLICATiOnS
•
•
•
•
•
•

Notebook Computers
Palmtop Computers
Pen-Based Computers
Himdi-Terminals
Bar-Code Readers
Flash Memory Programming

An open-collector VPP VALID output is driven low when
VPP is in regulation at 12V.
The LT1312 is available in an 8-pin SO package.
LT, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Typical PCMCIA Single Slot VPP Driver
13VT020V

_t-----I~_1

PCMCIA
CARD SLOT
CONTROLLER

-+--~"'-_1

VPPI
VPP2
PCMCIA
CARD SLOT

Vee
LT1312 TAl

LT1312 TlIUTH TABLE
END
ENI

0
1
0
0
1

x= DON'T CARE

4-394

0
0
1
1
1

SENSE

x

VPPOUT

VALID

ov

1
0
1
1
1

3.0VTO 3.6V
4.5VT05.5V

12V
3.3V
5V

X

Hi-Z

X

Linear Technology PCMCIA Product Family
DEVICE

DESCRIPTION

PACKAGE

LT1312

SINGLE PCMCIA VPP DRIVER/REGULATOR

B-PIN SO

LT1313
DUAL PCMCIA VPP DRIVER/REGULATOR
LTC0!>1314 SINGLE PCMCIA SWITCH MATRIX

16-PIN SO'
14-PIN SO

LTC1315

DUAL PCMCIA SWITCH MATRIX

24-PIN SSDP

LTC1470

PROTECTED Vce 5Vf3.3V SWITCH MATRIX

B-PIN SO

LTC1472

PROTECTED Vcc AND VPP SWITCH MATRIX 16-PIN SO'

'NARROW BODY

LT1312
rlBSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

,upply Voltage .'" .................................................... 22V
)igitallnput Voltage ........................ 7V to (GND - O.3V)
,ense Input Voltage ......................... 7V to (GND - O.3V)
lalid Output Voltage ...................... 15V to (GND - O.3V)
Mput Short-Circuit Duration .......................... Indefinite
)perating Temperature ................................ O°C to 70°C
lunction Temperature ................................ O°C to 125°C
,torage Temperature Range .................. -65°C to 150°C
_ead Temperature (Soldering, 10 sec) .................. 300°C

ORDER PART
NUMBER

TOP VIEW
GND IT
ENO [I
EN1 [I
VALID [I

]] VPPOUT
]] N.C.

LT1312CSa

]] Vs
]] SENSE

sa PART MARKING

S8 PACKAGE
HEAD PLASTIC SO
TJMAX = 125'C. 9JA = 150'C/W

1312

Consult factory for Industrial and Military grade parts.

ELEORICAL CHARACTERISTICS

VS =13V to 20V, TA =25°C, unless otherwise noted.

iYMBOL

PARAMETER

CONOITIONS

rpPOUT

Output Voltage

Program to 12V, lOUT :5120mA (Note 1)
Program to 5V, 10UT:5 30mA (Note 1)
Program to 3.3V, 10UT:5 30mA (Note 1)
Program to OV, lOUT = -300~

LKG

Output Leakage

Program to Hi-Z, OV:5 VPPOUT :512V

Supply Current

Program to OV
Program to Hi-Z
Program to 12V, No Load
Program to 5V, No Load
Program to 3.3V, No Load
Program to 12V, lOUT = 120mA
Program to 5V, lOUT = 30mA
Program to 3.3V, lOUT = 30mA

,

.1M

Current Limit

ENH

Enable Input High Voltage

ENL
:NH

Enable Input Low Voltage

Program to 3.3V, 5V or 12V

Enable Input High Current

2.4V :5 VIN :5 5.5V

,NL

Enable Input Low Current

OV:5 VIN :5 O.4V

SEN5

Vcc Sense Threshold

VPPOUT = 3.3V to 5V

SEN3

Vcc Sense Threshold

VPPOUT= 5V to 3.3V

,EN

Vcc Sense Input Current

VALIDTH

VPP VALID Threshold Voltage

VSENSE= 5V
VSENSE = 3.3V
Program to 12V

rALID

VPP VALID Output Drive Current

Program to 12V, VVALID = O.4V

VPP VALID Output Leakage Current

Program to OV, VVALID = 12V

he • denotes the specifications which apply over the full operating
imperature range.

L7lJD~

MIN

TYP

MAX

•
•
•

11.52
4.75
3.135

12.00
5.00
3.30
0.42

12.48
5.25
3.465
0.60

UNITS

•
•
••
••
•
••

-10

10

~

30
30
230
75
55
126
31
31

50
50
360
120
90
132
33
33

~
~

mA
mA
mA

330

500

mA

•
•

2.4

•
•

3.60
3.60

4.00

4.50

38
18

60
30

•

10.5

11

11.5

1

3.3

V
V
V
V

~
~
~

V
0.4

V

50

~

0.01

1

~

4.05

4.50

20

0.1

V
V
~
~

V
mA

10

~

Note 1: For junction temperatures greater than 110°C, a minimum load
of 1mA is recommended.

4-395

LT1312
TYPICAL PERFORmAnCE CHARAOERISTICS
Quiescent Current (DV or Hi-Z Mode)

Quiescent Current (12V Mode)

50

~

TJ = 25'C
ENO= ENh OV
OR
ENO= ENh 5V

40

~

15
a;
30
a;
u

I-

w

u

20

::;
10

o

TJ = 25'C
ENO = 5V
EN1 = OV

a;

~
1il
::;

I-

15
a; 150
a;

300

::>

u

10
15
20
SUPPLY VOLTAGE (V)

Z

200

o
o

25

f\

I-

a 100

o

TJ = 25'C
ENO = OV
EN1 = 5V
RL =""

%200

RL =00

::>
<.>

1
I

ffl

0

~

{

::>

250

%400

I-

Z

Quiescent Current (3.3V/5V Mode)

500

/

w 100

u

V

\

ffl

::;

0

10
15
20
SUPPLY VOLTAGE (V)

50

VSENjE = 3.3V

o
o

25

VSENSE = 5V

10
15
20
SUPPLY VOLTAGE (V)

LT1312G2

Ground Pin Current (12V Mode)
10

V
/

L-

//

/'

r--

«

I-

z

w

a;
a;
::>
u

c

RL = 200n
IL = 60mA'

z

::>
0

TJ = 25'C
ENO = OV
EN1 = 5V
VSENSE = 5V

2.0

'"

RL =400n
IL =30mA'
'FOR VPPOUT = 12V

15
20
10
SUPPLY VOLTAGE (V)

~
~

RL = 16m
IL = 30mA'

"-

1.0

o

«

'"

V~POUT = 5V

10
15
20
SUPPLY VOLTAGE (V)

0::

/

::>

u

z

c::

V

0::

'"
o

o

---

20

V

/'

'I

/

V

40 60 80 100 120 140 160
OUTPUT CURRENT (rnA)

~

a;

o~

::r:
en

1.=:t:==I==::j:==ic=::::j

600

25
LT1312G6

S
15
400 1--+--t--+---+------1
0::
0::

::>

~ 300 1 - - + - - 1 - - + - - + - - - 1
::;

200 1-+--+--1----1----11------1

o

100 H---\--+--+--If---l
O~-~-~--~-~-~

20

25

r---~--r---'--.,....-...,

I-

li!

10
15
INPUT VOLTAGE (V)

'FOR VJpOUT = 3.3V
10
15
20
SUPPLY VOLTAGE (V)

Vs = 15V
VPPOUT = OV
«500 I---j---+----j--+---j

400
300 H--+--f---+--1I------1

o

o

Current Limit

::>

u

IL=10mA'

lT1312G5

LT1312GB

4-396

0.5

o

25

RL=33~n

/

::>
0

0::

l600 f----t--t---j---j---I
~
~ 500 f---+--f---+---1'-------1

S 12
15
a; 10

I

c
:z 1.0

Current Limit

I-

::>
0

RL=110n
IL = 30mA'

u

RL =
IL=10mA'
'FOR

1.5

0::

800 r---..,---,--r--..,---,
TJ = 25'C
700 f-VPPOUT = OV'-1I--+---+--1

c
:z

2.0

::>

50~n

I
y

0.5

o

25

«

TJ = 25'C
ENO = OV
EN1 = 5V
VSENSE = 3.3V

S

1.5

a;

TJ = 25'C
Vs = 15V

14

2.5

S

Ground Pin Current
16

Ground Pin Current (3.3V Mode)

2.5

RL ~ 100n
IL=120mA'

TJ = 25'C
ENO = 5V
EN1 = OV

o
o

--

Ground Pin Current (5V Mode)

25
lT1312Ga

C;S 200 1--+--t--+---+------1

:x:

~ 1001--+--1--+--+---1

O'--_-'-_......L.._....-.J'--_-'-_-'

o

25
50
75
100
JUNCTION TEMPERATURE ('C)

125
LT1312G9

LT1312
TYPICAL PERFORmAnCE CHARAOERISTICS
Enable Input Threshold Voltage
3.0

Enable Input Current
50

Vs = 15V

~ 2.5

~

w

;'"

Vee Sense Threshold Voltage
5.5

TJ = 25'C
Vs = 15V

~

40

ff3

5.0

~~

4.5

30

:l

f-

ili

2.0

0

'"'"=>

>

:l
0

1.5

:I:

tfl

'"

1.0

:I:
ff-

0:>

r-- r-- r--

f-

=>
"-

;;:

~

=>
"-

20

,-- f--

~

OJ

"'"
ili

;;: 0.5

10

-

SWliCH TO 5\ \

§? 4.0

-

I--"

TJ = 25'C
Vs = 15V

13

'"

SWITbH TO

:I:

~ 3.5

3LI

en

ili

~ 3.0

f;:

o

o

25
50
75
100
JUNCTION TEMPERATURE ('C)

o

125

o

1

VALID Output Voltage

Vee Sense Input Current

!

1.0

TJ = 25'C
Vs= 15V

/

40

f-

ili

'"'"=>

30

0:>
f-

=>

"-

;;:

20

w

'"
ili

'"~

10

o

V

o

/

Y'

/

V

/

~
w

Y'

;'"
0

>

0.8

=> 0.4

0

Cl

Oii!

> 0.2

o

~

,

11.8

, 11.6

f COUT=l~F
I
I
I
I

V\.

~>

':;E

~~
~~

r-'

COUT=10~F _

o

"-"'
"
~~
>

0.2

0.4 0.6
TIME (ms)

0.8

1.0

1.2

COUTO

@

--v-:---

;;3
0::

~
""-

~

a:

l-

0.5
1.0
1.S
2.0
2.S
VALID OUTPUT CURRENT (rnA)

20

40

0

-20

It-/cOUT = 11 O~F

I'

20

10

100

lk
10k
FREQUENCY (Hz)

lOOk

1M

Load Transient Response (12V)
0.4

w

COUT=l~Fll

I

l~FTANTALUM

I'

o

3.0

'"~~

~

0.2

COUT -l~F

ow

;:~

0

If.
:==>"'"
6-0.2 r-- COUT = 10~F
=>
o

-40

li~

IIII I II I
JilL III 1

60

z

0-

>-~

-0.2

80

Line Transient Response (12V)

Vs = 15V

~ 12.0

~
0::

o

•

TJ = 2S'C, 12V MODE
Vs = 15V + 100mVRMS RIPPLE

40

w

1.

TJ = 25'C
Vs = lSV
ENO = SV
ENl = OV

0

=>

./

Ripple Rejection (12V)

0.6

f-

12V Turn-On Waveform
12.2

125

100

~

"f-

~12.4

25
50
75
100
JUNCTION TEMPERATURE ('C)

0

ENABLE INPUT VOLTAGE (V)

~

o

LT1312Gl1

LT1312Gl0

50

2.5

2
3
4
5
ENABLE INPUT VOLTAGE (V)

-0.4

:;c
E

~ i="100

15

oili

13

-I

g§ 50
=>

0:>

-0.1

0.1

0.2 0.3
TIME (ms)

0.4

0.5

0.6

-0.1

0.1

0.2 0.3
TIME (ms)

0.4

0.5

0.6

LT1312G16

4-397

LT1312

Pin FunOlons
Supply Pin: Power is supplied to the device through the
supply pin. The supply pin should be bypassed to ground
if the device is more than 6 inches away from the main
supply capacitor. Abypass capacitor in the range of 0.1 J.IF
to 1J.IF is sufficient. The supply voltage to the LT1312 can
be loosely regulated between 13V and 20V. See Applications Information section for more detail.
VPPOUT Pin: This regulated output supplies powerto the
PCMCIA card VPP pins which are typically tied together
at the card socket. The VPPOUT output is current limited
to approximately 330mA. Thermal shutdown provides a
second level of protection. A1J.lFto 1OJ.IFtantalum output
capacitor is recommended. See Applications Information section for more detail on output capaCitor considerations.
Input Enable Pins: The two digital input pins are high
impedance inputs with approximately 20J,lA input current

at 2.4V. The input thresholds are compatible with CMOS
controllers and can be driven from either 5V or 3.3V
CMOS logiC. ESD protection diodes limit input excursions
to 0.6V below ground.

VALID Output Pin: This pin is an open-collector NPN
output which is driven low when the VPPOUT pin is in
regulation, i.e., when it is above 11 V. An external 51 kpullup resistor is connected between this output and the same
5Vor 3.3V logic supply powering the PCMCIA compatible
control logic.
Vee Sense Pin: A built-in comparator and 4V reference
automatically switches the VPPOUT from 5V to 3.3V depending upon the voltage sensed at the PCMCIA card
socket Vee pin. The input current for this pin is approximately 30J,lA. For 5Vonly operation, connectthe Sense pin
directly to ground. An ESD protection diode limits the
input voltage to 0.6V below ground.

BLOCK DIAGRAm

Vs

LOW DROPOUT
LINEAR
REGULATOR

VPPOUT

Vee SENSE

VALID

ENO

VOLTAGE
LOGIC CONTROL

EN1
11V

-:

4-398

-:

LT1312
OPERATion
The LT1312 is a programmable output voltage, low~ropout linear regulator designed specifically for PCMCIA
\/PP drive applications. Input power is typically obtained
rrom a loosely regulated input supply between 13V and
20V (see Applications Information section for more detail
~n the input power supply). The LT1312 consists of the
rollowing blocks:
Low Dropout Voltage Linear Regulator: The heart of the
LT1312 is a PNP-based low-dropout voltage regulator
Nhich drops the unregulated supply voltage from 13V to
20V down to 12V, 5V, 3.3V, OVor Hi-Z depending upon the
:;tate ofthetwo Enable inputs and the Vee Sense input. The
regulator has built-in current limiting and thermal shutjown to protect the device, the load, and the socket
19ainst inadvertent short circuiting to ground.

~PPLICATlons

WINDING POWER SUPPLIES

3ecause the LT1312 provides excellent output regulation,
he input power supply may be loosely regulated. One
:onvenient (and economic) source of power is an auxiliary
vinding on the main 5V switching regulator inductor in the
nain system power supply.
.TC®1142HV Auxiliary Winding Power Supply
:igure 1 is a schematic diagram which describes how a
oosely regulated 14V power supply is created by adding

L7lJ!J~

Vee Sense Comparator: When the Vee mode is selected,
the LT1312 automatically adjusts the regulated VPP output voltage to 3.3V or 5V depending upon the voltage
present at the PC card Vee supply pin. The threshold
voltage for the comparator is set at 4V and there is
approximately 50mV of hysteresis provided to ensure
clean switching between 3.3V and 5V.
VPP VALID Comparator: A voltage comparator monitors
the output voltage when the 12V mode is selected and is
driven low when the output is in regulation above 11 V.

InFORmATiOn

rhe LT1312 is a voltage programmable linear regulator
jesigned specifically for PCMCIA VPP driver applications.
rhe device operates with very low quiescent current
:30)JA) in the OV and Hi-Z modes of operation. In the Hi-Z
node, the output leakage current falls to 1)JA. Unloaded
~uiescent current rises to only 55)JA and 75)JA when
lrogrammed to 3.3V and 5V respectively. In addition to
:he low quiescent currents, the LT1312 incorporates sevlral protection features which make it ideal for PCMCIA
Ipplications. The LT1312 has built-in current limiting
:330mA) and thermal shutdown to protect the device and
he socket VPP pins against inadvertent short-circuit
:onditions.
~UXILIARY

Voltage Control Logic: The LT1312 has five possible
output modes: OV, 3.3V, 5V, 12V and Hi-Z. These five
modes are selected by the two Enable inputs and the Vee
Sense input as described by the Truth Table.

an auxiliary winding to the 5V inductor in a split 3.3V/5V
LTC1142HV power supply system. Aturns ratio of 1:1.8 is
used for transformer T1 to ensure that the input voltage to
the LT1312 falls between 13V and 20V under all load
conditions. The 9V output from this additional winding is
rectified by diode D2, added to the main 5V output and
applied to the input of the LT1312. (Note that the auxiliary
winding must be phased properly as shown in Figure 1.)
The auxiliary winding is referenced to the 5Voutput which
provides DC current feedback from the auxiliary supply to
the main 5V section. The AC transient response is improved by returning the negative lead of C5 to the 5V
output as shown.
When the 12V output is activated by a TIL high on the
Enable line, the 5V section ofthe LTC1142HVis forced into
continuous mode operation. A resistor divider composed
of R2, R3 and switch Q3 forces an offset which is subtracted from the internal offset atthe Sense - input (pin 14)
of the LTC1142HV. When this external offset cancels the
built-in 25mV offset, Burst Mode™ operation is inhibited
and the LTC1142HV is forced into continuous mode
operation. (See the LTC1142HV data sheet for further
detail). In this mode, the 14V auxiliary supply can be
Burst Mode is a trademark of Linear Technology Corporation.

4-399

•

LT1312
APPLICATions InFoRmATion
+---...,

VIN ,.:.::-~~---+--....

PDRIVE
14V AUXILIARY SUPPLY

112 LTC1142HV NDRIVE
5VREG

C5
22~F

FROM
CARD Vee PIN

ENO---~----------------I
EN1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

LT1312F1

VALlD-------------------~

"LPE-6562-A026 DALE (605) 665-9301

Figure 1_ Deriving 14V Power from an Auxiliary Winding on the LTC1142HV 5V Regulator

loaded without regard to the loading on the 5V output of
the LTC1142HV.
Continuous mode operation is only invoked when the
LT1312 is programmed to 12V. If the LT1312 is programmed to OV, 3.3V or 5V, power is obtained directly
from the main power source (battery pack) through diode
D1. Again, the LT1312 output can be loaded without
regard to the loading of the main 5V output.
R4 and C4 absorb transient voltage spikes associated with
the leakage inductance inherent in T1 's secondary winding
and ensure that the auxiliary supply does not exceed 20V.
Figure 2 is agraph of output voltage versus output current
for the auxiliary 14V supply shown in Figure 1. Note that
the auxiliary supply voltage is slightly higher when the 5V
output is heavily loaded. This is due to the increased
energy flowing through the main 5V inductor.
lTC1142 Auxiliary Power from the 3.3V Output
The circuit of Figure 1 can be modified for operation with
low-battery count applications (6 cell). As the input voltage falls, the 5V duty cycle increases to the point where

4-400

there is simply not enough time to transfer energy from the
5V primary to the auxiliary winding. For applications
where heavy 12V load currents exist in conjunction with
low input voltages (<6.5V), the auxiliary winding can be
derived from the 3.3V section instead of the 5V section of
the LTC1142. Inthis case, atransformer with aturns ratio
of 1:3.4 to 1:3.6 should be used in place ofthe 3.3V section
17
~ 16

VIN = BV
ENO = HI

w

~
'::; 15

~
....
5o

1i:

14

-

-

IOUT5V = 1A
~

lOUT5V=OmA

~ 13
::J

~

12

11

0.1

10

100

1000

AUXILIARY OUTPUT CURRENT (mA)
LT1312F2

Figure 2. LTC1142 Auxiliary Supply Voltage

LT1312
'PPLICAllons InFORmAlion
on this line that may damage sensitive PCMCIA flash
memory cards if applied directly to the VPP pins.

lductor as shown in Figure 3. MOSFET 04 and diode 04
ave been added and diode 01 is no longer used. In the
revious circuit, power is drawn directly from the batteries
1rough 01 , when the LTC1142 is in Burst Mode operation
nd the VPP pin requires 3.3V or 5V. For these lower input
oltages this technique is no longer valid as the input will
ill below the LT1312 regulator's dropout voltage. To
orrect for this situation, the additional switch 04 forces
1e switching regulator into continuous mode operation
Ihenever 3.3V, 5V or 12V is selected.

Flash Memory Card VPP Power Considerations
PCMCIA compatible flash memory cards require tight
regulation of the 12V VPP programming supply to ensure
thatthe internal flash memory circuits are never subjected
to damaging conditions. Flash memory circuits are typically rated with an absolute maximum of 13.5V and VPP
must be maintained at 12V ±5% under all possible load
conditions during erase and program cycles. Undervoltage
can decrease specified flash memory reliability and overvoltage can damage the device1.

INE POWERED SUPPLIES
1 line operated products such as: desktop computers,
edicated PC card readers/writers, medical equipment,
lSt and measurement equipment, etc., it is possible to
erive power from a relatively "raw" source such as a 5V
r 12V power supply. The 12V supply line in a desktop
omputer however, is usually too "dirty" to apply directly
) the VPP pins of a PCMCIA card socket. Power supply
witching and load transients may create voltage spikes

Generating 14V from 5V or 12V
It is important that the 12V VPP supply for the two VPP
lines to the card be free of voltage spikes. There should be
little or no overshoot during transitions to and from the . , .
12Vlevel.
..
1See Application Note AP-357, "Power Supply Solutions for Flash Memory,"

Intel Corporation, 1992.

VIN
5.4VTO 12V
V
IN

24
C4

T
01

C1
68f1F

":"
14V AUXILIARY SUPPLY

1/2 LTC1142
3.3V REG

SENSE+

~1_-+-_ _~..--.....

SENSE- t-=2;:..8-4----'lJIIv-~~----+-

...... 3.3V
OUTPUT

-=--------------...l

ENO-+-.:.....-....
EN1-+---------------------'

~lID----------------------...l
• LPE-6582-A086 DALE (605) 665-9301

LT1312F3

Figure 3. Deriving Auxiliary 14V Power from an LTC1142 3.3V Regulator

4-401

LT1312
APPLICATions InFoRmATion
lN5158

TO CARD VPP PIN
- . . - - OV, 5V, 12V OR HI-Z

Figure 4. Local 5V to 15V Boost Regulator for Line Operated Applications

Figure 5. Local12V to 15V Boost Regulator for Line Operated Applications

This is easily accomplished by generating a local 14V
supply from arelatively "dirty" 5Vor 12V supply as shown
in Figures 4 and 5. Precise voltage control (and further
filtering) is provided by the LT1312 driver/regulator. A
further advantage to this scheme is that it adds current
limit in series with the VPP pins to eliminate possible
damage to the card socket, the PC card, or the switching
power supply in the event of an accidental short circuit.
Output Capacitance
The LT1312 is designed to be stable with a wide range of
output capacitors. The minimum recommended value is a
1!JF with an ESR of 30 or less. The capacitor is connected
directly between the output pin and ground as shown in
Figure 6.
For applications where space is very limited, capacitors as
low as O.33!JF can be used. Extremely low ESR ceramic
capacitors with values less than 1!JF must have a 20
resistor added in series with the output capacitor as shown
in shown in Figure 7.

4-402

13VTO 20V-~~-----.

Figure 6. Recommended
·,JV

>1~

Tantalum Output Capacitor

IU~UV~_-----.

O.33!1F
~CERAMIC

Figure 7. Using a O.3~ to 1~ Output Capacitor

LT1312
~PPLICATlons

InFORmATion

'ransient and Switching Performance

Table 1. S8 Package"

'he LT1312 is designed to produce minimal overshoot with
:apacitors in the range of 11JF to 101JF. Larger capacitor
'alues can be used with a slowing of rise and fall times.

COPPER AREA
TOPSIDE
BACKSIDE

'he positive output slew rate is determined by the 330mA
:urrent limit and the output capacitor. The rise time for a
IV to 12V transition is approximately 40~, the rise time
or a 101JF capacitor is roughly 400~ (see the Transient
lesponse curves in the Typical Performance Characterisics section).
'he fall time from 12V to OV is set by the output capacitor
Ind an internal pull-down current source which sinks
.bout 30mA. This source will fully discharge a11JF capaciDr in less than 1ms.
'hermal Considerations
'ower dissipated by the device is the sum of two compolents: output current multiplied by the input-output differntial voltage lOUT x (VIN - VOUT), and ground pin current
nultiplied by supply voltage IGNO x VIN.
'he ground pin current can be found by examining the
iround Pin Current curves in the Typical Performance
:haracteristics section.
leat sinking, for surface mounted devices, is accomIlished by using the heat spreading capabilities of the PC
loard and its copper traces.
'he junction temperature ofthe LT1312 must be limited to
25°C to ensure proper operation. Use Table 1in conjuncon with the typical performance graphs, to calculate the
ower dissipation and die temperature for a particular
pplication and ensure that the die temperature does not
xceed 125°C under any operating conditions.

2500 sq mm

2500sq mm

THERMAL RESISTANCE
BDARDAREA (JUNCTION'TO'AMBIENTI
2500 sq mm
120°C/w

1000 sq mm

2500sq mm

2500 sq mm

120°C/W

225 sq mm

2500 sq mm

2500 sq mm

125°C/W

1000 sq mm 1000 sq mm
'Device is mounted topside.

1000 sq mm

131°C/W

Calculating Junction Temperature
Example: given an output voltage of 12V, an input supply
voltage of 14V, an output current of 100mA, and a
maximum ambient temperature of 50°C, what will the
maximum junction temperature be?
Power dissipated by the device will be equal to:
lOUT x (Vs - VPPOUT) + (lGND x VIN)
where:
IOUF 100mA
VIN = 14V
IGND at (lOUT = 100mA, VIN = 14V) = 5mA
so,
Po =1OOmA x (14V - 12V) + (5mA x 15V) =O.275W
Using Table 1, the thermal resistance will be in the range
of 120°C/W to 131 °C/W depending upon the copper area.
So the junction temperature rise above ambient will be
less than or equal to:
O.275W x 131°C/W =36°C
The maximum junction temperature will then be equal to
the junction temperature rise above ambient plus the
maximum ambient temperature or:
TJMAX =50°C + 36°C =86°C.

L7lJD~

4-403

LT1312
TYPICAL APPLICATions
Single Slot Interlace to CL-PD671 0
13Vr20V

T

51K

VCC

Vs
ENO

A_VPP_PGM

VPPOUT

A_VPP_VCC

EN1 LT1312

VPP_VALID

VALID

5V

d

I
II

Si9430DY OR
MMSF3P02HO

1--1 I'

-I
1
1
1 Si9933DY OR

~
:

Vcc

3.3V OR 5V

P

+

';"'-10~F

: MMDF2P01 HD

I

~I1

1

PCMCIA
CARD SLOT

r--

*

CIRRUS LOGIC
CL-PD6710

A_Vcc_3

VPP2

SENSE
GND

A_VCC_5

VPP1

T1~F L

L __ ~_I

3.3V

Single Slot Interlace to "365" Type Controller
VLOGIC

'.1

13VT0 20V

1

VCC
A_VPP_ENO

51k
ENO

A..,VPP_EN1

r

Vs
VPPOUT

PCMCIA
CARD SLOT

VALID

3.3V OR 5V

SENSE

~1~F

-!-

"365" TYPE
CONTROLLER

5V

I~'~''''"

I
Vs

IN1

G1

I,

LTC1157CSB
IN2

G2
GND

l.

MMSF5N02HD

1--1 I'

~:3
:

-I
1

:

+

T10~F

Si9956DY OR
: MMDF3N02HD

1
1

1

3.3V

RELATED PAATS
See PCMCIA Product Family table on the first page of this data sheet.

4-404

Vcc

+

GND

A_Vce-EN1

VPP2

EN1 LT1312

A:GPi

A_VCe-ENO

VPP1

LT1312TA3

LY~J!J~~~~-----D-u-a-l-p-c-~_T~_31_~
VPP Driver/Regulator
FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•
•

The LT®1313 is a member of Linear Technology
Corporation's PCMCIA driver/regulator family. It provides
OV, 3.3V, 5V, 12V and Hi-Z regulated power to the VPP
pins of two PCMCIA card slots from a single unregulated
13V to 20V supply. When used in conjunction with a PC Card
Interface Controller, the LT1313 forms acomplete minimum
component-count interface for palmtop, pen-based and notebook computers. The two VPP output voltages are independently selected by four logic compatible digital inputs
which interface directly with industry standard PC Card
Interface Controllers.

Digital Selection of OV, Vcc, 12V or Hi-Z
Output Current Capability: 120mA
Internal Current Limiting and Thermal Shutdown
Automatic SWitching from 3.3V to 5V
Powered from Unregulated 13V to 20V Supply
Logic Compatible with Standard PCMCIA Controllers
Output Capacitors: 1W
Quiescent Current in Hi-Z or OV Mode: 60~
Independent VPP Valid Status Feedback Signals
No VPP Overshoot

~PPLICATlons

Automatic 3.3V to 5V switching is provided by two independent comparators which continuously monitor each
PC card Vec supply voltage and automatically adjust the . , . .
VPP outputto match the associated Vee pin voltage when . .
the VPP = Vec mode is selected.

• Notebook Computers
Palmtop Computers
I Pen-Based Computers
I Handi-Terminals
I Bar-Code Readers
I Flash Memory Programming

I

Two open-collector VPP VALID outputs are provided to
indicate when the VPP outputs are in regulation at 12V.
The LT1313 is available in 16-pin SO packaging.

cr. LTC and LT are registered trademarks of Linear Technology Corporation.

rYPICAL APPLICATiOn
Typical PCMCIA Dual Slot VPP Driver
Linear Technology PCMCIA Product Family
VPPI
-"--""---1VPP2
PCMCIA
CARD SLOT
#1
DUAL PCMCIA
CARD SLOT
CONTROLLER

Vee
VPPI
-..--""---1VPP2
PCMCIA
CARD SLOT
#2

L7lJ[J~

DEVICE

DESCRIPTION

SINGLE PCMCIA VPP DRIVER/REGULATOR
LT1312
LT1313
DUAL PCMCIA VPP DRIVER/REGULATOR
LTC@1314 SINGLE PCMCIA SWITCH MATRIX

PACKAGE
8-PIN SO
16-PIN SO'
14-PIN SO

LTC1315

DUAL PCMCIA SWITCH MATRIX

24-PIN SSOP

LTC1470

PROTECTED Vcc 5V/3.3V SWITCH MATRIX

8-PIN SO

LTC1472

PROTECTED Vee AND VPP SWITCH MATRIX 16-PIN SO'

'NARROW BODY

4-405

LTl313
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

Supply Voltage ........................................................ 22V
Digital Input Voltage ........................ 7V to (GND - O.3V)
Sense Input Voltage ......................... 7V to (GND - O.3V)
VALID Output Voltage .................... 15V to (GND - O.3V)
Output Short-Circuit Duration .......................... Indefinite
Operating Temperature ................................ O°C to 70°C
Junction Temperature ................................ O°C to 125°C
Storage Temperature Range .................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER PART
NUMBER
LT1313CS

SPACKAGE
16-LEAD PLASTIC SO
TJMAX =125°C, OJA =100°C/W
Consult factory for Industrial and Military grade parts.

ELEORICAL CHARAOERISTICS
SYMBOL PARAMETER
Output Voltage

VPPOUT

ILKG
Is

Output Leakage
Supply Current

ILiM

Current Limit

VENH

Enable Input High Voltage

VENL

Enable Input Low Voltage

IENH

Enable Input High Current

Vs =13V to 20V, TA =25°C (Note 1), unless otherwise noted.

•••

11.52
4.75
3.135

Program to Hi-Z, OV:5: VPPOUT:5: 12V
Both Channels Programmed to OV
Both Channels Programmed to Hi-Z
One Channel Programmed to 12V, No Load (Note 3)
One Channel Programmed to 5V, No Load (Note 3)
One Channel Programmed to 3.3V, No Load (Note 3)
One Channel Programmed to 12V, lOUT = 120mA (Note 3)
One Channel Programmed to 5V, lOUT = 30mA (Note 3)
One Channel Programmed to 3.3V, lOUT = 30mA (Note 3)

•
•
•••
•
•
•
•

-10

•

2.4

Program to 3.3V, 5V or 12V (Note 3)

IENL

Enable Input Low Current

OV :5: VIN :5: O.4V

Vcc Sense Threshold

VPPOUT = 3.3V to 5V (Note 4)

VSEN3

Vcc Sense Threshold

VPPOUT = 5V to 3.3V (Note 4)

ISEN

Vee Sense Input Current

VSENSE= 5V
VSENSE = 3.3V
Program to 12V, (Note 5)

VPPvALID Outplit Leakage Current

•
•

Program to 12V, VVALID = O.4V, (Note 5)
Program to OV, VVALID = 12V, (Note 5)

The. denotes the specifications which apply over the full operating
temperature range.
Note 1: Both Vs pins (10, 14) must be connected together, and both
ground pins (1, 5) must be connected together.
Note 2: For junction temperatures greater than 110°C, a minimum
load of 1rnA is recommended.

4-406

•

2.4V :5: VIN :5: 5.5V

VSEN5

VVALIDTH VPPVALID Threshold Voltage
VPPVALIDOutput Drive Current
IVALID

MIN

CONDITIONS
Program to 12V, lOUT :5: 120mA (Note 2)
Program to 5V, IOUT:5: 30mA (Note 2)
Program to 3.3V, IOUT:5: 30mA (Note 2)
Program to OV, lOUT = -3001lA

•

TYP
12.00
5.00
3.30
0.42

MAX
12.48
5.25
3.465
0.60

60
60
260
105
85
126
31
31

100
100
400
150
120
132
33
33

rnA
rnA
rnA

330

500

rnA

10

UNITS
V
V
V
V

IlA
IlA
IlA
IlA
IlA
IlA

V
20
0.01

0.4

V

50
1

IlA
IlA
V

3.60

4.05

4.50

3.60

4.00

4.50

38
18

60
30

10.5

11

11.5

1

3.3
0.1

V

IlA
IlA
V
rnA

10

IlA

Note 3: The other channel is programmed to the OV mode (XENO =
XENl = OV) during this test.
Note 4: The Vcc sense threshold voltage tests are performed
independently.
Note 5: The VPPVALID tests are performed independently.

LTl313
'YPICAl PERFORmAnCE CHARAOERISTICS
Quiescent Current
(OV or Hi-Z Mode)

Quiescent Current (12V Mode)

100

500

TJ =25'C
BOTH CHANNELS PROGRAMMED TO OV
80 OR BOTH CHANNELS PROGRAMMED TO Hi-Z

=2~'C

I

I

Quiescent Current (3.3V/5V Mode)
250

I

TJ
ONE CHANNEL PROGRAMMED TO 12V
OTHER CHANNEL IN OV OR Hi-Z MODE -

~ 400

Rl =00

>-

60

i'i'i
g;;

r

40

0:
0:
::J

~

200

13

::;
o 100

J

o
o

10
15
20
SUPPLY VOLTAGE (V)

o

25

J

o

I

I

I

RL = 00

150

~l

<.:>

<.:>

I

20

~

300

::J

<.:>

2~'C

TJ =
ONE CHANNEL PROGRAMMED TO
~ 200 - VPP = Vee. OTHER CHANNEL IN - OV OR Hi-Z MODE

~

V

<.:>

100

13

VSEN~E

::;

o

10
15
20
SUPPLY VOLTAGE (V)

VSENSE = 3.3V
50

I

o

o

25

= 5V

J.

10
15
20
SUPPLY VOLTAGE (V)

1313603

1313602

Ground Pin Current (12V Mode)

Ground Pin Current (5V Mode)

10

2.5
TJ = 25'C
12V MODE
SINGLE OUTPUT

r-~r-RL = 1000
IL = 120mA'

/

o ~
o

2.0

>-

<.:>

"'

1.0

::J

0

0:

'"

RL = 4000
IL=30mA'
'FORVPPour= 12V

15
20
SUPPLY VOLTAGE (V)

0.5

o

25

10

i'i'i
0:

RL = 1671l
IL = 30mA'

::J
Cl

~

I
Y

o

TJ = 25'C
3.3VMODE
SINGLE OUTPUT
VSENSE = 3.3V

2.0

g

1.5

0:

RL = 2000
IL = 60mA'

V

!--

>-

i'i'i
0:

I

V/

~

Ground Pin Current (3.3V Mode)
2.5

TJ = 25'C
5V MODE
SINGLE OUTPUT
VSENSE = 5V

g

25

-

J

RL = 5000
IL -10mA'
'FOR

1.5
RL=1100
IL = 30mA'

0:

::J

Cl

z

1.0

I

=>

0
0:

'"

V~POUT = 5V

10
15
20
SUPPLY VOLTAGE (V)

r

<.:>

0.5

o

y

o

25

RL = 33100
IL=10mA'
'FOR

V~POUT = 3.3V

10
15
20
SUPPLY VOLTAGE (V)

25
1313606

Ground Pin Current
16

Current Limit

TJ = 25'C
Vs = 15V
SINGLE CHANNEL

14

~

g

12

!z

Current Limit

800 , - - - , - - - , - - - , - - - , . - TJ = 25'C
700 XVPPOUT = OV
SINGLE CHANNEL
600 f - - - + - - f - - t - - + - -

~ 500~-~--~-+--r---'

10

V
o

o

~
20

/'

/'

V

1/

V

40 60 80 100 120 140 160
OUTPUT CURRENT (mA)

::J

<.:>

r-;::j==+==+==t===1

>~ 400 I
~ 300 H - - t - - - r - - - t - - - j - - - - j

ti:

o 200 I - + - - t - - - r - - - t - - - j - - - - j
:0:

en

100

f-+-+--+--+---j---J

0 ......--'-----'---'----'-----'

o

10
15
INPUT VOLTAGE (V)

20

25

~

g

600 ,.----,,,..,.---,---,.--,--Vs = 15V
XVPPOUT = OV
500 SINGLE CHANNEL - - t - - - j - - - - - '

>~ 400 j - - - t - - - j - - - j - - - j r - - - j
0:

=>

~ 300 i - - - t - - - r - - - t - - - j i - - - - j

::;

f;"!

Y
b:

200

f----t---f---t----i---j

o

~ 100i---t---j---t---j---j
0L---L---~--~--~----"

o

25
50
75
100
JUNCTION TEMPERATURE ('C)

125

4-407

LTl313
TYPICAL PERFORmAnCE CHARAOERISTICS
Enable Input Threshold Voltage

Enable Input Current

3.0

5.5

VS=15V

TJ = 25'C
Vs = 15V

~ 2.5
w

'"~

2.0

0

>

90

1.5

:r

VJ

w

a:
:r 1.0
>>::;,
Il.

~

0.5

o

Vee Sense Threshold Voltage

50

1>- 40
15
a:

---- ---

a:

::;,

o

~

~
~
100
JUNCTION TEMPERATURE ('C)

~

~ 4.5

30

'"'

>::;,

Il.

r--..

~

20

,--r- f.--

~

«
'"

15

TJ = 25'C
Vs = 15V

~

ffi 5.0

10

9

SWITCH TOSV

III

SWITCH TO 3.3V

~ 4.0

-

:r

~ 3.S

ffi

~ 3.0

.g

o

125

o

1

2.5

5

o

~
~
100
JUNCTION TEMPERATURE ('C)

~

ENABLE INPUT VOLTAGE (V)

12!

1313911

Vee Sense Input Current

VALID Output Voltage

50

~

TJ = 25'C
Vs = 15V
40

>-

15
a:
a:

30

::;,

'"'

>::;,
Il.

~
w

20

VJ

15

VJ

~

10

o

Ripple Rejection (12V)
100

1.0

./

o

V

/

V

/

V

/

V

/

TJ = J5'C
Vs = 15V
12VMODE

~ 0.8

'"0

w

~

0

~
0::

0.6

0

&l

>::;,

0.4

0

0.2

o

1
2
3
4
S.6
Vee SENSE INPUT VOLTAGE (V)

r

o

I--

- ----

w

12.2

~

>-

~

12.0
11.8

/

,
I

~ 11.6
I

~>

COUT= 1~Fll

I

0-

>w

~
Coup1O~F_

~~5 -20
,:;1'
o

I

It./coUT=J10~F

1.0

1.2

1313616

CouP 11'F

;:~

0
::;,«
1= ~-O.2
::;,
o

-40

1N

100k

~

Il

1

CouP 10l'F

-0.4

,
<1'
E

51! ;::-100

015
-1~

-0.1

50

::;,

>

4-408

0.2

Ow

,

0.8

1k
10k
FREQUENCY (Hz)

0.4

'".....~>
-

~

~~ 13
0.4 0.6
TIME (ms)

100

Load Transient Response (12V)

~~ 15

0.2

10

w

>-~

-0.2

o

3.0

40

..... E 20

A.

COUT=1~F

20

Line Transient Response (12V)

Vs = 1SV

1.

Il.
Il.

a:

0.5
1.0
1.5
2.0
2.S
VALID OUTPUT CURRENT (mA)

i'

~

1313G14

12V Turn-On Waveform
~12.4

!::;

a:

V

:-.

40

Ul

1313G13

~

COUT = 1~FTANTALUM

j::

::::i

:;:

IIII IIII I
IIII IIII I

60

z

>

Il.

>::;,
0

TJ = 25'C, 12V MOOE
Vs = 1SV + 100mVRMS RIPPLE

a;- 80

0.1

0.2 0.3
TIME (ms)

0.4

0.5

0.6

'"'

-0.1

0.1

0.2 0.3
TIME (ms)

0.4

O.S

O.E

1313G18

LT1313

lin FunCTions
Ipply Pins: Power is supplied to the device through the
'0 supply pins which must be connected together at all
nes. The supply pins should be bypassed to ground if
e device is more than six inches away from the main
Ipply capacitor. Abypass capacitor in the range of 0.1 ~
1~ is sufficient. The supply voltage to the LT1313 can
i loosely regulated between 13V and 20V.
JPOUT Pins: Each regulated output supplies powerto the
'0 PCMCIA card VPP pins which are typically tied toither atthe socket. Each VPPOUT output is current limited
approximately 330mA. Thermal shutdown provides a
cond level of protection. A 1~ to 1O~ tantalum output
pacitor is recommended.
put Enable Pins: The four digital input pins are high
Ipedance inputs with approximately 20~ input current
2.4V. The input thresholds are compatible with CMOS
Introllersand can be driven from either 5Vor3.3V CMOS
Jic. ESD protection diodes limit input excursions to 0.6V
ilow ground.

:LOCK DIAGRAm

Vs

VALID Output Pins: These pins are open-collector NPN
outputs which are driven low when the corresponding
VPPOUT pin is in regulation, i.e., when it is above 11 V. Two
external 51 k pull-up resistors are connected between
these outputs and the same 5V or 3.3V logic supply
powering the PCMCIA compatible controllogiG.
Vec Sense Pins: Two independent comparators and 4V
references automatically switch the VPPOUT outputs from
5V to 3.3V depending upon the voltage sensed at the
corresponding PCMCIA card socket Vee pin. The input
current for these pins is approximately 30~. For 5V only
operation, connect the Sense pins directly to ground. An
ESD protection diode limits the input voltage to 0.6V below
ground.
Ground Pins: The two ground pins must be connected
together at all times.

(One Channel)

---------1

LOW DROPOUT
LINEAR
!----1---------XVPPOUT
REGULATOR

XVcc SENSE

4V
XVALID

XENO

_ _ _ _ _ _ _ _-1

VOLTAGE
LOGIC CONTROL

XEN1---------I
11V
x =A OR B

4-409

LTl313
OPERATion
The LT1313 is two programmable output voltage, lowdropout linear regulators designed specifically for PCMCIA
VPP drive applications. Input power is typically obtained
from a loosely regulated input supply between 13V and
20V. The LT1313 consists of the following blocks:
Two Low Dropout Voltage Linear Regulators: The heart
of the LT1313 is two PNP-based low-dropout voltage
regulators which drop the unregulated supply voltage
from 13V to 20V down to 12V, 5V, 3.3V, OV or Hi-Z
depending upon the state of the four Enable inputs and the
two Vee Sense inputs. The regulators have built-in current
limiting and thermal shutdown to protect the device, the
loads, and the sockets against inadvertent short circuiting
to ground.
Voltage Control Logic: The two VPPOUT outputs have five
possible output modes: OV, 3.3V, 5V, 12V and Hi-Z. These
five modes are selected by the four Enable inputs and the
two Vee Sense inputs as described by the Truth Table.
Vee Sense Comparators: When the Vee mode is selected,
the LT1313 automatically adjusts each regulated VPP output
voltage to 3.3V or 5V depending upon the voltage present

at the corresponding PC card Vee supply pin. The thresh
old voltage for these comparators is set at 4V and there i
approximately 50mV of hysteresis provided to ensur,
clean switching between 3.3V and 5V.
VPP VALID Comparator: Two voltage comparators moni
tor each output voltage when the 12V mode is selected ani
are driven low when the output is in regulation above 11 \i
These two outputs function separately.
LT1313 Truth Table
AEND

AEN1

ASENSE

AVPPour

AVALID

0
1
0
0
1

0
0
1
1
1

X
X

3.0Vto 3.6V
4.SVto S.SV
X

OV
12V
3.3V
SV
Hi-Z

1
0
1
1
1

BEND

BEN1

BSENSE

BVPPOUT

BVALID

0
1
0
0
1

0
0
1
1
1

X
X

OV
12V
3.3V
SV
Hi-Z

1
0
1
1
1

x= Don t Care

..

3.0Vto3.6V
4.SVto S.SV
X

Note: Each channel IS Independently controlled.

APPLICATions InFORmATion
The LT1313 is two voltage programmable linear regulators designed specifically for PCMCIA VPP driver applications. The device operates with very low quiescent current
(60~) in the OV and Hi-Z modes of operation. In the Hi-Z
mode, the output leakage current falls to 1~.ln addition
to the low quiescent currents, the LT1313 incorporates
several protection features which make it ideal for PCMCIA
applications. The LT1313 has built-in current limiting
(330mA) and thermal shutdown to protect the device and the
socket VPP pins against inadvertent short-circuit conditions.
Output CapaCitance
The LT1313 is designed to be stable with a wide range of
output capaCitors. The minimum recommended value is a
1J.lF with an ESR of 3n or less. The capaCitor is connected
directly between the output pin and ground. For applications
where space is very limited, capaCitors as low as O.33J.lF can

4-410

be used. Extremely low ESR ceramic capacitors with value~
less than 1J.lF must have a 2n resistor added in series witt
the output capacitor.
Transient and Switching Performance
The LT1313 is designed to produce minimal overshoo
with capacitors in the range of 1J.lF to 10J.lF. Large
capacitor values can be used with a slowing of rise am
fall times.
The positive output slew rate is determined by the 330mJ
current limit and the output capaCitor. The rise time for (
OV to 12V transition is approximately 401J8 and the riSE
time for a 10J.lF capacitor is roughly 4001J8 (see thE
Transient Response curves in the Typical PerformanCE
Characteristics section).

LT1313
'PPLICATlons InFORmATion
he fall time from 12V to OV is set by the output capacitor
nd an internal pull-down current source which sinks
bout 30mA. This source will fully discharge a11!f capaciJr in less than 1ms.
hermal Considerations
'ower dissipated by the device is the sum of two compoents: output current multiplied by the input-output differntial voltage: IOUTX (VIN - VOUT), and ground pin current
lultiplied by supply voltage: (lGNO x VIN).
he ground pin current can be found by examining the
iround Pin Current curves in the Typical Performance
haracteristics section.
leat sinking, for surface mounted devices, is accomlished by using the heat spreading capabilities of the PC
oard and its copper traces.
he junction temperature ofthe LT1313 must be limited to
25°C to ensure proper operation. Use Table 1, in conmction with the typical performance graphs, to calculate
le power dissipation and die temperature for aparticular
pplication and ensure that the die temperature does not
)(ceed 125°C under any operating conditions.
able 1. 16-Pin SO Package*
COPPER AREA
)PSIDE

iOO sq mm
lOOsq mm
15 sq mm
lOO sq mm

BACKSIDE
2500 sq mm
2500sq mm
2500 sq mm
1000 sq mm

BOARD AREA
2500sq mm
2500sq mm
2500 sq mm
1000 sq mm

THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)

120°C/W
120°C/W
125°C/W
131°C/W

Calculating Junction Temperature
Example: given an output voltage of 12V, an input supply
voltage of 14V, and an output current of 1OOmA (one VPP
output), and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be?
Power dissipated by the device will be equal to:
lOUT x (Vs - VPPOUT) + (lGNO x VIN)
where,
lOUT = 100mA
VIN = 14V
IGNO at (lOUT =100mA, VIN =14V) =5mA
so,
Po = 1OOmA x (14V -12V) + (5mA x 15V) = O.275W
USing Table 1, the thermal resistance will be in the range
of 120°C/W to 131 °C/W depending upon the copper area.
So the junction temperature rise above ambient will be
less than or equal to:
O.275W x 131 °C/W =36°C
The maximum junction temperature will then be equal to
the junction temperature rise above ambient plus the
maximum ambient temperature or:
TJMAX = 50°C + 36°C = 86°C

For more detailed applications information, see the LT1312
Single PCMCIA VPP Driver/Regulator data sheet.

)eviee is mounted on topSide.

L7lJ!J~

4-411

LTl313
TYPICAL APPLICATions
Dual Slot PCMCIA Interface to CL-PD6720
TO ~~~ -

.....--1~---.,

PCMCIA
CARD SLOT
#1

3.3V/5V

PCMCIA
CARD SLOT
#2

VPP_VALID 1---<1......- - CIRRUS LOGIC
CL-PD6720
AVec

5V 1 - - - 1 - - - - - - - - - - 1

AVec

3V 1--~--------1""'+-I

01
Si940SDY

BVeeWI--~---~

lOS
: Si9933DY

+

T

1

: 06
_: Si9933DY

1

1

1 _____

10 l'F

P-CHANNEL

vee SWITCHING__ 1I
..!.'!.V_ __________

- - - - - - - - - - - N"-CHANNELV; sWITcHiNG-uSiNG - - - - - - - - - -I
LTC1165 INVERTING N-CHANNEL DRIVERS
:
SV
AVec

5V - - ! - - - - - - - - ( J l I N 1

Vs

OUT11------;

"'---';--TO Vee SLOT 1

LTC116SCS8
A~e3V-r------'-~

OUT21-----+_;
GND OUT31--S-V- - - + - I

SV
OUT1

t - - - - - - - - - - - ! - - T O V e e SLOT 2
OUT2I------!-i

oura
1313TA02

4-412

LTl313
'YPICAl APPLICATions
Dual Slot PCMCIA Interface to "365" Type Controller

VPP1

- -.....- - - - - - - -.....---jVPP2
PCMCIA
CARD SLOT
#1

3.3V15V

Vee
VPP1

1 - - -.....- - - - - f - - - - - - - I V P P 2
PCMCIA
CARD SLOT
3.3V/5V

L7lJD~

#2

Vee

4-413

LTl313
TYPICAL APPLICATions
Dual Slot PCMCIA Driver/Regulator Powered from
Auxiliary Winding on SV Inductor of LTC1142HV DuaISVJ3.3V Switching Regulator

LTC1148
SINGLE
5VREG

- - : . . - _ TO "A" SLOT
VPP PINS

t-:-:--......---'W~.......----4~-.....-~~TPUT
FROM "A" SLOT
- - - V c c PIN

'LPE·6562·A026 DALE (605) 655·9301
AENO - i - - - - - - 4 I - - - - - - - - - - - - - - - - - - '
AEN1 - i - - - - - - - - - - - - - - - - - - - - - - - '
~ALlD-i--------------------~

--4_----------------------1

BENO
BEN1--------------------------'
~ALlD------------------------~

NOTE: SEE LT1312 DATA SHEET APPLICATIONS SECTION
FOR FURTHER DETAILS ON THIS CIRCUIT

RELATED PARTS
See PCMCIA Product Family table on the first page of this
data sheet.

4-414

FROM "B" SLOT
- - - V c c PIN

f""'-LlnO\~D~___
LTC_13_14__
/L_TC_13_15

~,

TECHNOLOGY

:EATURES
I

I
I

I
I
I
I
I

I

DESCRIPTion

Output Current Capability: 120mA
External12V Regulator Can Be Shut Down
Built-In N-Channel Vcc Switch Drivers
Digital Selection of OV, VCCIN, VPPIN or Hi-Z
3.3V or 5V Vcc Supply
Break-Before-Make Switching
0.1 ~ Quiescent Current in Hi-Z or OV Mode
No VPPOUT Overshoot
Logic Compatible with Standard PCMCIA Controllers

~PPLICATlons
I
I
I
I

I

PCMCIA Switching Matrix
with Built-In N-Channel
Vee Switch Drivers

Notebook Computers
Palmtop Computers
Pen-Based Computers
Handi-Terminals
Bar-Code Readers

The LTC@1314/LTC1315 provide the power switching
necessary to control Personal Computer Memory Card
International Association (PCMCIA) Release 2.0 card slots.
When used in conjunction with aPC card interface controller, these devices form a complete minimum component
count interface for palmtop, pen-based and notebook
computers.
The LTC1314/LTC1315 provide OV, 3.3V, 5V, 12V and
Hi-Z power output for flash VPP programming. A built-in
charge pump produces 12V of gate drive for inexpensive
N-channeI3.3V/5V Vcc switching. The 12V regulator can
be shut down when 12V is not required at VPPOUT. All
digital inputs are TTL compatible and interface directly
with industry standard PC card interface controllers.
The LTC1314 is available in 14-pin SO and the LTC1315 in
24-pin SSOP.
£T, LTC and LT are registered trademarks of Linear Teehnology Corporation.

fYPICAL APPLICATiOn
Linear Technology PCMCIA Product Family

DEVICE DESCRIPTION
LT1312 SINGLE PCMCIA VPP DRIVER/REGULATOR
LT1313 DUAL PCMCIA VPP DRIVER/REGULATOR
LTC"'1314 SINGLE PCMCIA SWITCH MATRIX
LTC1315 DUAL PCMCIA SWITCH MATRIX
LTC1470 PROTECTED Vce 5V/3.3V SWITCH MATRIX
LTC1472 PROTECTED Vcc AND VPP SWITCH MATRIX
·NARROW BODY

Typical PCMCIA Single Slot Driver

3.3V OR 5V

VIN

12V

R~~~rA~R
LT"1301

PACKAGE
a-PIN so
16-PIN so·
14-PIN so
24-PIN SSOP
a-PIN so
16-PIN SO·

LTC1314 Truth Table
PCMCIA
CARD SLOT
:ONTROLLER

----+--......-IVPPI
VPP2
PCMCIA
CARD SLOT

--+-.......- - - 1 Vee

3.3V

L7lJ!J~

END
0
0
1
1
X

EN1
0
1
0
1
X

x
x
x

x
X

x

Veeo

x
X
X
X
1
0
0
1

Vee1
X
X
X
X

VPPOUT
GND
VeelN
VPPIN
Hi-Z

a

x

1

X

a

x

1

X

DRV3
X
X
X
X
1

DRV5
X
X
X
X

a
a
a

1

a
a
a

X= DON'T CARE

4-415

LTC1314/LTC1315
ABSOLUTE mAXimum RATinGS
VPPIN to GND ........................................ 13.2V to -O.3V
Voo to GND ................................................. 7V to -O.3V
VCCIN to GND .............................................. 7V to -O.3V
VPPOUT to GND ............ .'......................... 13.2V to -O.3V

Digital Input Voltage ................................... 7V to -O.3V
Operating Temperature Range .................... O°C to 70°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER
LTC1314CS

ORDER PART
NUMBER

AVPPIN 1
ASHON 2

LTC1315CG

AEN1
AVcco

SPACKAGE
14-LEAO PLASTIC SO
GPACKAGE
24-LEAO PLASTIC SSOP

Consult factory for Industrial and Military grade parts_

ELECTRICAL CHARAOERISTICS Voo = 5V, VCCIN = 5V, VPP1N = 12V, TA = 25°C unless otherwise specified.
SYMBOL
VCCIN
VPPIN
Voo
Icc
Ipp

PARAMETER
Input Voltage Range
Input Voltage Range
Supply Voltage Range
VCCIN Supply Current, No Load
VPPIN Supply Current, No Load

IDD

VOD Supply Current, No Load

liN
lOUT
RON

Input Current: ENO, EN1, Vcca or VCC1
High Impedance Output Leakage Current
On Resistance, VPPOUT = VPPIN
On Resistance, VPPOUT = VCCIN
On Resistance, VPPOUT = GND
Input High Voltage, Digital Inputs
Input Low Voltage, Digital Inputs

VINH
VINL

4-416

CONDITIONS

VPPOUT = VPPIN, VCCIN, OV or Hi-Z
VPPOUT = VPPIN, VCCIN
VPPOUT = OV, Hi-Z
VPPOUT = VPPIN or VCCIN
VPPOUT = OV or Hi-Z
VPPOUT = OV or Hi-Z, DRV3 or DRV5 On
OV  Voo + 1V
CGATE =1000pF, Time for VGATE < 0.5V
VPPOUT =GND to VCCIN, VPPIN =OV, Note 1
VPPOUT =GND to VPPIN (Note 1)
VPPOUT =VCCIN to VPPIN (Note 1)
VPPOUT =VPPIN to VCCIN (Note 3)
VPPOUT =VPPIN to GND (Note 2)
VPPOUT =VCCIN to GND, VPPIN =OV (Note 2)
VPPOUT =Hi-Z to VPPIN or VCCIN (Notes 1, 6)

'he • denotes specifications which apply over the full operating
emperature range.
late 1: To 90% of the final value, COUF 0.1!J1', ROUF 2.9k.
late 2: To 10% of the final value, COUT = 0.1!J1', ROUT = 2.9k.

LTC1314/LTC1315
MIN
TYP
MAX
3.5
0.4
7
13
6
150
500
50
10
30
3
15
50
5
5
15
50
5
15
50
2
6
20
150
15
50
10
25
100
15
50
5

•
•

•

UNITS
V
V
V
~
~

~
~
~
~
~
~
~

Note 3: To 50% of the initial value, COUT = 0.1!J1', ROUT = 2.9k.
Note 4: Measured current data is per channel.
Note 5: Input logic low equal to OV, high equal to 5V.
Note 6: VPPIN = OV when switching from Hi-Z to VCCIN .

•

rYPICAL PERFORmAnCE CHARACTERISTICS
Switch On Resistance vs
Temperature
3.0
2.7

2.4

2.1
1.8
1.5 ".
1.2
0.9
0.6
0.3

o

VccISW~~
V
,/

--

--

VPP SWITCH
~

-50 -30 -10 10 30 50
TEMPERATURE ('C)

L7lJ!J~

70

90

ORV3/0RV5 Output Voltage vs
Temperature

Supply Current vs Temperature
75
70
.......... .......
I
65
............VPPOUT =VPPIN =12V;;(
60
..:;
f55
iii
............
0::
0::
=> 50
<.>
::; 45
00=> 40

VPPOUT =VCCIN - 35
VPPIN =12V
30
25
-50 -30 -10 10 30 50 70 90
TEMPERATURE ('C)

.!.

J J

r-

14.2

2: 14.0

V
./

w

~

~ 13.8

,/

>
~

VV

::: 13.6
=>

o

ill 13.4

/

V

113.2
13.0
-50 -30 -10 10 30 50
TEMPERATURE ('C)

70

90

4-417

LTC1314/LTC1315
TYPICAL PERFORmAnCE CHARACTERISTICS
100 vs Voo
80

20

VPPI~ = 12VI

~

1l

/

16

./

30

/

-/

'1

X

40

VPPOUT = VCC~

12
-;; 10

/

~

J I

/

10

o

o

VPPOUr=°VORHI-Z

/
2

o/

/

VPPOUT = VCCIN

j

o

3
Voo (V)

1/

v

/.~-

20

V

VPPOUT = VPp,N7

14

VPPOUT = VPPIN/

50

VOO = VCCIN = 5V
T = 25°C

18

70 I-VCCIN =5V
T= 25°C
60

V

1/ VPPOUT
= OV
ORHI-Z
2

4

6
8
VPPIN (V)

10

12

14

1314115G05

1314115004

Pin FunOlons
LTC1314
VPPIN (Pin 1): 12V Power Input
NC (Pin 2): Not Connected.
SHDN (Pin 3): Shutdown Output When the output is high,
the external12V regulator can be shut down to conserve
power consumption.
END, EN1 (Pins 4,5): Logic inputs that control the voltage
output on VPPOUT. The input thresholds are compatible
with TIL/CMOS levels. Refer to Truth Table.
Vcco (Pin 6): Logic input that controls the state of the
MOSFET gate driver DRV3. ESD protection device limits
input excursions to O.6V below ground.
VCC1 (Pin 7): Logic input that controls the state of the
MOSFET gate driver DRV5. ESD protection device limits
input excursions to O.6V below ground.

4-418

DRV5, DRV3(Pins 8,9): Gate driver outputs that control
the external MOSFETs that switch the Vee pin of card slot
to Hi-Z, 3.3V, or 5V.
Voo (Pin 10): Positive Supply, 4.5V:s; Voo:S; 5.5V. This pin
supplies the power to the control logic and the charge
pumps and must be continuously powered.
GND (Pin 11): Ground Connection.
VPPOUT (Pin 12): Switched output that provides OV, 3.3V,
5V, 12V, or Hi-Z to the VPP pin of the card slot Refer to
Truth Table.
NC (Pin 13): Not Connected.
VCCIN (Pin 14): 5V or 3.3V Power Input

LTC1314/LTC1315

Pin FunCTions
LTC1315
~PP'N

(Pins 1, 7): 12V Power Inputs.

SHDN (Pins 2,8): Shutdown Outputs. When the output is
ligh, the external 12V regulator can be shut down to
~onserve power consumption.
:NO, EN1 (Pins 3, 4, 9, 10): Logic inputs that control the
IOltage output on VPPOUT. The input thresholds are
;ompatible with TIL/CMOS levels. Refer to the Truth
rable.
IceD (Pins 5,11): Logic inputs that control the state ofthe
IIIOSFET gate driver ORV3. ESO protection device limits
nput excursions to O.6V below ground.

DRV5, DRV3 (Pins 13,14,19,20): Gate driver outputs
that control the external MOSFETs that switch the Vcc pin
of card slot to Hi-Z, 3.3V, or SV.
Voo (Pins 15,21): Positive Supplies, 4.SV s VDD S S.SV.
These pins supply the power to the control logic and the
charge pumps and must be continuously powered.
GND (Pins 16, 22): Ground Connections.
VPPOUT (Pins 17, 23): Switched outputs that provide OV,
3.3V, SV, 12V, or Hi-Ztothe VPPpin of the card slot. Refer
to the Truth Table.
VeclN (Pins 18, 24): SV or 3.3V Power Inputs.

ICC1 (Pins 6, 12): Logic inputs that control the state of the

IIIOSFET gate driver ORVS. ESO protection device limits
nput excursions to O.6V below ground.

----------------------------11
IlOCK DIAGRAm
LTC1314 or 1/2 LTC1315

END
BREAK-BE FOREMAKE SWITCHES
EN1

VPPOUT

GND

Veeo

r--I--------P--DRV3
GATE CHARGE
AND DISCHARGE
DRV5
CONTROL LOGIC

1-------.......-+-

Vee1

4-419

LTC 1314/LTC1315
SWITCHinG TimE WAVEFORms

--1nL.____~

END _ _ _ _

EN1

VPPIN-----

VPPOUT

VCCIN - - - - _ - - '

GND _ _J

NOTE: 111F CAPACITOR CONNECTED ON BOTH VPPIN AND VCCIN PINS AT TIMING TEST

APPLICATions InFORmATion
PCMCIA VPP control is easily accomplished using the
LTC1314 or LTC1315 switching matrix. Two control bits
(LTC1314) or four control bits (LTC1315) determine the
output voltage and standby/operate mode conditions. Output voltages of OV, VCCIN (3.3V or 5V), VPPIN, or a high
impedance state are available. When either the high impedance or low voltage (OV) conditions are selected, the device
switches into "sleep" mode and draws 0.1J,IA of current
from the VDD supply.
The LTC1314/LTC1315 are low resistance power MOSFET
switching matrices that operate from the computer system
main power supply. Device power is obtained from VDD,
which is 5V ±0.5V. The gate drives for the NFETs (both
internal and external) are derived from internal charge
pumps, therefore VPPIN is only required when it's switched
to VPPOUT. Internal break-before-make switches determine the output voltage and device mode.
Flash Memory Card VPP Power Considerations
PCMCIA compatible flash memory cards require tight
regulation of the 12V VPP programming supply to ensure
that the internal flash memory circuits are never subjected
to damaging conditions. Flash memory circuits are typi-

4-420

cally rated with an absolute maximum of 13.5V and VPP
must be maintained at 12V ±5% under all possible load
conditions during erase and program cycles. Undervoltage
can decrease specified flash memory reliability and overvoltage can damage the device.
Vee Switch Driver and VPP Switch Matrix
Figures 1 and 2 show the approach that is very space and
power efficient. The LTC1314/LTC1315 used in conjunction with the LT1301 DC/DC converter, provide complete
power management for aPCMCIA card slot. The LTC1314/
LTC1315 and LT1301 combination provides a highly efficient, minimal parts count solution. These circuits are
especially good for applications that are adding a PCMCIA
socket to existing systems that currently have only 5V or
3.3V available.
The LTC1314 drives three N-channel (LTC1315 six
N-channel) MOSFETs that provide Vcc pin power switching. On-chip charge pumps provide the necessary voltage
to fully enhance the switches. With the charge pumps onchip, the MOSFET drive is available without the need for a
12V supply. The LTC1314/LTC1315 provide a natural
break-before-make action and smooth transitions due to

LTC1314/LTC1315
APPLICATions InFoRmATion
L1

5V
C1: AVX TPSD476M016R0150
C2: AVX TPSD336M020R0200
L1: SUMIDA CD75-220K

- - - - - - - - - . - - -......- - ; VPP1
VPP2
PC CARD
SOCKET

PCMCIA
CONTROLLER

--~-+-------,.------; Vee

3.3V

Figure 1. LTC1314 Switch Matrix with the LT1301 Boost Regulator
L1

.---11----1 SHDN
PGND
C1: AVX TPSD476M016R0150
C2: AVX TPSD336M020R0200
l1: SUMIDA CD75-220K

---------1---1~--IVPP1

VPP2
PC CARD
SOCKET

--...:..+-----1-------l Vee

#1

PCMCIA
CONTROLLER
---...:..-----1~---<""""--IVPP1

VPP2
PC CARD
SOCKET
--~+-----1~-----I Vee #2

3.3V

Figure 2. Typical Two-Socket Application Using the LTC1315 and the LT1301

4-421

LTC1314/LTC1315
APPLICATions InFoRmATion
the asymmetrical turn-on and turn-off of the MOSFETs.
The LT1301 switching regulator is in shutdown mode and
consumes only 10J,lA until the VPP pins require 12V.
The VPP switching is accomplished by a combination of
the LTC1314/LTC1315 and LT1301. The LT1301 is in
shutdown mode to conserve power until the VPP pins
require 12V. When the VPP pins require 12V, the LT1301
is activated and the LTC1314/LTC1315's internal switches
route the VPPIN pin to the VPPOUT pin. The LT1301 is
capable of delivering 12V at 120mA maintaining high
efficiency. The LTC1314/LTC1315's break-before-make
and slope-controlled switching will ensure thaUhe output
voltage transition will be smooth, of moderate slope, and
without overshoot. This is critical for flash memory products to prevent damaging parts from overshoot and
ringing exceeding the 13.5V device limit.

13VTO 20V
(MAY BE FROM
AUXILLARY
WINDING)

With Higher Voltage Supplies Available

Often systems have an available supply voltage greater
than 12V. The LTC1314/LTC1315 can be used in conjunction with an LT1121 linear regulator to supply the PC card
socket with all necessary voltages. Figures 3 and 4 show
these circuits. The LTC1314/LTC1315 enable the LT1121
linear regulator only when 12V is required at the VPP pins.
In all other modes the LT1121 is in shutdown mode and
consumes only 16J,lA. The LT1121 also provides thermal
shutdown and current limiting features to protect the
socket, the card and the system regulator.
Supply Bypassing

For best results, bypass VCCIN and VPPIN at their inputs
with 1/lfcapacitors. VPPouTshould have aO.01/lfto O.1/lf
capacitor for noise reduction and electrostatic discharge
(ESD) damage prevention. Larger values of output capacitor will create large current spikes during transitions,
requiring larger bypass capaCitors on the VCCIN and VPPIN
pins.

VOUT 1-1----4-.....,..-'""1

---;-1---1 VIN
LT1121

ADJ ..........-

........
56.2k

1%

1---------.----1~....., VPP1
VPP2

PCMCIA
CONTROLLER

PC CARD
SOCKET

I---~----..---""" Vee
1314/15f03

3.3V

Figure 3. LTC1314 with the LT1121 Linear Regulator

4-422

LTC1314/LTC1315
APPLICATions InFoRmATion
13V TO 20V
(MAY BE FROM
AUXILIARY WINDING)

(12V)
VOUT . -......- - P - - - - ; 1 - - - ,

--;-t---i VIN
~ 10l'F

LT1121

.---"";;"'--1 SHDN
PGND

200pF

121k

-:;!;" 11'F

ADJ I -.....----t
GND
56.2k

- - - - - - -......- -.......--IVPP1
VPP2
PC CARD
SOCKET

--~~---......- - - - - I V c c #1

PCMCIA
CONTROLLER
- - - - - - -......- -.......--IVPP1
VPP2
PC CARD
SOCKET

--~~---......- - - - - I v c c #2
13141t5F04

Figure 4. Typical Two-Socket Application Using the LTC1315 and the LT1121

TYPICAL APPLICATiOnS
Single Slot Interface to CL -PD671 0
5V

12V
FROM LT1301

VPP_PGM

VPP1
VPP2

VPP_Vcc

PCMCIA
CARD SLOT

CIRRUS LOGIC
CL·PD6710
Vec_5

Vec

Vec_3

NOTE: CL-PD6710 HAS ACTIVE-LOW Vee DRIVE

LTCI314·TA02

3.3V

4-423

LTC1314/LTC1315
TYPICAL APPLICATions
Dual Slot Interface to CL-PD6720
5V

12V

A_VPP_PGM

- - - - - - - - - - _ - _....... VPP1
VPP2
PCMCIA
CARD SLOT

~VPP_Vee

B_VPP_PGM
B_VPP_Vee

- - - -.....>-----~.....- - - - I Vee

#1

CIRRUS LOGIC
CL-PD6720

~Vec-5
~Vec-3

- - - - - - - - - - - - ' - _ - _....... VPP1
VPP2
PCMCIA
CARD SLOT

B_Vec-5
B_Vec-3

----~~---~._----iVee n
LTC131S-TA02

3.3V

NOTE: CL-PD6720 HAS ACTIVE-LOW Vee DRIVE

Single Slot Interface to "365" Type Controller

5V

12V
FROM LT1301

----------<......--.---IVPP1
VPP2

A_VPP_EN1

PCMCIA
CARD SLOT

"365" TYPE
CONTROLLER

--....;.--+-.::..:.=:;;..:.=;.:.:..._-----!Vee

NOTE: "365" TYPE CONTROLLERS HAVE
ACTIVE-HIGH Vee DRIVE

4-424

3.3V

LTC1314/LTC1315
TYPICAL APPLICATions
Dual Slotlnterfae to "365" Type Controller
12V

5V

I\...VPP_ENO
I\...VPP_EN1
B_VPP_ENO
B_VPP_EN1

- - - - - - - - -....- -.....--1VPP1
VPP2
PCMCIA
CARD SLOT
- - - - . , ; .......- - - -....- - - - - 1 Vcc #1

"365" TYPE
CONTROLLER

A_VCC_ENO
A_Vcc_EN1
B_Vcc_ENO
B_Vcc_EN1

- - - - - - - - -....- -.....--1VPP1
VPP2
PCMCIA
CARD SLOT
- _ _-.,;......._ _ _ _...._ _ _--1 Vcc #2

3.3V

NOTE: "365" TYPE CONTROLLERS
HAVE ACTIVE-HIGH Vcc DRIVE

Typical PCMCIA Dual Slot Driver
3.3V OR 5V

V'N

12V

- - - - - - - 4 1 1 - - - _ - - 1 VPP1
VPP2
PCMCIA
CARD SLOT

- - - + - : 1 P - - - - - - j Vcc #1

LTC1315 Truth Table
END
0
0

1
0
1
1
X
X
X
X
X
X
x
X
x= DON'T CARE
1

PCMCIA
CARD SLOT
CONTROLLER

-------411---_--IVPP1
VPP2
PCMCIA
CARD SLOT
--.....;,.......---411------I vcc #2

ENl
0

Veco

x

X
X
X
1
0
0
1

Vee1
X
X
X
X
0
1
0
1

VPPOUT
GND
VCC'N
VPP'N
Hi-Z
X
X

x
X

DRV3
X
X
X
X
1
0
0
0

DRV5
X
X
X
X
0
1
0
0

lTC131S0TAOl

3.3V

RELATED PARTS
See PCMCIA Product Family table on the first page of this data sheet.

4-425

tlnt:J\12
TECHNOLOG~~~----------S-in-g-Ie-a-n-d--D-ua-I

f-..·.

~~

LTC 1470/LTC 1471

PCMCIA Protected
3.3V/5V Vee Switches
FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•
•
•
•

The LTC®1470 switches the Vee pins of a Personal Computer Memory Card International Association (PCMCIA)
card slot between three operating states: OFF, 3.3V and
5V. Two low RDS(ON) N-channel power MOSFETs are
driven by a built-in charge pump which generates a
voltage higher than the supply voltage to fully enhance
each switch when selected by the input control logic.

Single 3.3V/5V Switch in 8-Pin SO Package
DuaI3.3V/5V Switch in 16-Pin SO Package
Built-In Current limit and Thermal Shutdown
Built-In Charge Pumps (No 12V Required)
Extremely Low RDS(ON) MOSFET Switches
Output Current Capability: 1A
Inrush Current Limited (Drives 150~ Loads)
Quiescent Current in Standby: 1!JA
No Parasitic Body Diodes
Built-In XOR Function Eliminates "Glue" Logic
Break-Before-Make Switching
Controlled Rise and Fall Times

APPLICATions
•
•
•
•
•
•

The LTC1470 inputs are compatible with industry standard PCMCIA controllers. Abuilt-in XOR ensures that both
switches are never on atthe same time. This function also
makes the LTC1470 compatible with both active-low and
active-high controllers (see Applications Information section). The switch rise times are controlled to eliminate
power supply glitching.
The LTC1470 features built-in SafeSlot™ current limit and
thermal shutdown. The output is limited to 1Aduring short
circuit to ground but 2A of peak operating current is
allowed.

Notebook Computers
Palmtop Computers
Pen-Based Computers
Handi-Terminals
PC Card Reader/Writers
3.3V/5V Power Supply Switch

The LTC1471 is a dual version of the LTC1470 and is
available in a 16-pin SO package.
J..."T, LTC and LT are registered trademarks of Linear Technology Corporation.
SafeSlot is a trademark of Linear Technology Corporation.

TYPICAL APPLICATiOn
Linear Technology PCMCIA Product Family

Dual Slot PCMCIA 3.3V/5V Vee Switch

PCMCIA
~~+...c:~ CARD SLOT

PCMCIA
CARD SLOT
CONTROLLER

---~"'-I

PCMCIA
CARD SLOT

DEVICE

DESCRIPTION

PACKAGE

LT®1312

Single PCMCIA VPP Driver/Regulator

a-Pin SO

LT1313

Dual PCMCIA VPP Driver/Regulator

16-Pin SO*

LTC1314

Single PCMCIA Switch Matrix

14-Pin SO

LTC1315

Dual PCMCIA Switch Matrix

24-Pin SSOP

LTC1470

Single Protected VCC 3.3V/5V Switch Matrix

a-Pin SO

LTC1471

Dual Protected Vcc 3.3V/5V Switch Matrix

16-Pin SO*

LTC1472

Protected Vcc and VPP Switch Matrix

16-Pin SO*

*Narrow Body

4-426

LTC 1470/LTC 1471
ABSOLUTE mAXimum RATinGS
3.3V Supply Voltage (Note 1) .................................. 7V
5V Supply Voltage (Note1) ....................................... 7V
Enable Input Voltage ........................ 7V to (GND - 0.3V)
Output Voltage (OFF) (Note 1) ......... 7V to (GND - 0.3V)
Output Short-Circuit Duration .......................... Indefinite

Operating Temperature ............................... O°C to 70°C
Junction Temperature .......................................... 100°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

I

TOP VIEW

'~D'~

5VIN 2 .
ENl 3
ENO 4

3VIN
6 3VIN
5 GND

LTC1470CSa

7

sa PART MARKING

S8 PACKAGE
HEAD PLASTIC SO

1470

ORDER PART
NUMBER

TOP VIEW
AOUT II
A5VIN [I
AENl [l
AENO 11
GND
B3VIN
B3VIN II
BOUT [[

IJ:

I!

j]J AOUT
j]] A3VIN

El

LTC1471CS

A3VIN

j] GND

mBEND

1]] BENl

1Q] B5VIN

•

II BOUT

SPACKAGE
l6-LEAD PLASTIC SO
TJMAX =100°C, 9JA =100°C/W

TJMAX =100°C, 9JA =l50°C/W

Consult factory for Industrial and Military grade parts.

ELEORICAL CHARAOERISTICS

3VIN =3.3V, 5VIN =5V (Note 2), TA =25°&, unless otherwise noted.
MAX

SYMBOL

PARAMETER

3VIN

3.3V Supply Voltage Range

2.70

3.60

V

5VIN

SV Supply Voltage Range

4.7S

S.2S

V

13VIN

3.3V Supply Current

Program to Hi-Z (Note 3)
Program to 3.3V, No Load (Note 3)
Program to SV, No Load (Note 3)

15VIN

SV Supply Current

Program to Hi-Z (Note 3)
Program to 3.3V (Note 3)
Program to SV (Note 3)

~ON

3.3V Switch ON Resistance
SV Switch ON Resistance

Program to 3.3V, lOUT =SOOmA
Program to SV, lOUT =SOOmA

CONDITIONS

LKG

Output Leakage Current OFF

Program to Hi-Z, OV:s VOUT:S SV (Note 3)

LlM3V

3.3V Current Limit

Program to 3.3V, VOUT =OV (Note 4)

LlM5V

SV Current Limit

Program to SV, VOUT =OV (Note 4)

'ENH

Enable Input High Voltage

'ENL
EN

Enable Input Low Voltage
Enable Input Current

OV :sVEN:S 5V

MIN

•

••
•••
•

TYP

0.01
40
0.01

10
80
10

0.01
100
140

10
160
200

IlA
IlA
IlA
IlA
IlA
IlA

0.12
0.14

0.16
0.18

n
n

±10

IlA

1

A

1

•
•

•

UNITS

A

2.0

V
0.8

V

±1

IlA

4-427

LTC 1470/LTC 1471
ELEORICAL CHARAOERISTICS

3VIN = 3.3V, 5VIN = 5V (Note 2), TA = 25°C, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

to to Ia

Delay and Rise Time (Note 5)

Transition from OV to 3.3V, ROUT =lOOn, COUT =llJF

0.2

0.32

1.0

t3 tot5
totot5

Delay and Rise Time (Nole 5)

Transition from 3.3V to 5V, ROUT =lOOn, COUT =llJF

0.2

0.52

1.0

ms
ms

Delay and Rise Time (Note 5)

Transition from OV to 5V, ROUT =lOOn, COUT =llJF

0.2

0.38

1.0

ms

The. denotes the specifications which apply over the full operating
temperature range.
Note 1: For the LTC1470, the two output pins (1, 8) must be connected
together and the two 3.3V supply input pins (6 , 7) must be connected
together. For the LTC1471, the two AOUT pins (1, 16) must be connected
together, the two BOUT pins (8, 9) must be connected together, the two
A3VIN supply input pins (14, 15) must be connected together, the two
B3VIN supply pins (6, 7) must be connected together and the two GND
pins (5, 13) must be connected together.

Note 2: Power for the input logic and charge pump circuitry is derived
from the 5VIN supply pints) which must be continuously powered.
Note 3: Measured current is per channel with the other channel
programmed off for the LTC1471.
Note 4: The output is protected with fold back current limit which reduces
the short-circuit (OV) currents below peak permissible current levels at
higher output voltages.
Note 5: To 90% of final value.

TYPICAL PERFORmAnCE CHARACTERISTICS
3VIN Supply Current (OFF)

(LTC1470 or 1/2 LTC1471)

3VIN Supply Current (3.3V ON)
120

1

100 f-

TA =25°C
PROGRAMMED TO OFF

TA =25°C
PROGRAMMED TO
3.3V. NO LOAD

1
~

I-

80
15
a:;
a:;
:::>
t.:>

:::;
0..
0..

:::>

'"z

~

1

2

3f----1---+--+-+--+----1

a:;
a:;
:::>

60
40

I

20

oV
o

3

5VIN Supply Current (OFF)

~

~

1

-

-

2

~

2

0-

0..

:::>

'"z

a;

3

1

3VIN SUPPLY VOLTAGE (V)

3VIN SUPPLY VOLTAGE (V)

5VIN SUPPLY VOLTAGE (V)
1410171605

5VIN Supply Current (3.3V ON)

1
!Z
ij!
a:;
:::>
t.:>

~~
z

a;

TA =25°C
PROGRAMMED
TO 3.3V. NO LOAD

250

1
15

200
150
100

...,..,....

50

o

3.3V Switch Resistance

5VIN Supply Current (5V ON)
0.30

300

300

/"
o

1

2

--

3

..,..,.
~

~
~
z

w

t.:>

:i!
~
en

150
100
50

/
o

1

V
2

/

V

,/

0.20

ij! 0.15

:c

~ 0.10 l---

'"
iii;

ro 0.05

3

o

4

5VIN SUPPLY VOLTAGE (V)
1470171G03

PRO~RAMMEci

§: 0.25 r- T03.3V

200

o

4

TA=25°C
PROGRAMMED
TO 5V. NO LOAD

0..

a;

5VIN SUPPLY VOLTAGE (V)

4-428

a:;
a:;
:::>
t.:>

250 f-

147lV11 002

o

-----

~

W

.M

100

1~

JUNCTION TEMPERATURE (OC)
147W71G01

LTC 1470/LTC 1471
TYPICAL PERFORmAnCE CHARAOERISTICS
Inrush Current (3.3V SWitch)

5V Switch Resistance

9:
~

0.30

§S

3

PRodRAMME6
0.25 _ T05V

§

2

0.20

1;;
13
0.15
IX
:r:
~

§ 0.10
U)

ii;

0.05

o

-o

13

1

-

V-

gJ
;;;;

0

IX

~
~

~
§;
~
5
o

25
50
75
100
JUNCTION TEMPERATURE (0G)

125

I

TJ =25°C

/'\

IX
IX

:r:

~

(LTC1470 or 1/2 LTC1471)

~ "-

j

Inrush Current (5V Switch)

J

COUT =1501'F""'-Roup 6.6n

L

~
a:

2

13

1

gJ

0

IX

:r:

I

)~OUT115I'J
ROUT =6.00

6

0:

~

/ A co~p l~OI'F

2

IU

0

0

0.2

~
§;

I I
Roup6.6n

I--

>-~

5
o

0.4 0.6 O.B 1.0 1.2 1.4
TIME (ms)

CU~REN~
-

;;;;
~

/

-0.2

§S

TJ = 25°C

LIMITE,,)

Y

I .1
Coup 15 0l'F
ROUT" 10n

V

1

/

"'-

1/
I

/

6

I Goup 151'F
Roup 10n

.~

/V

2

V/

0

-0.2

0

0.2

0.4 0.6 O.B 1.0 1.2 1.4
TIME (ms)
1470171 GOa

Pin FunCTions
LTC1470
OUT (Pins 1, 8):Output Pins. The outputs of the LTC1470
are switched between three operating states: OFF, 3.3V
and 5V. These pins are protected against accidental short
circuits to ground by SafeS lot current limit circuitry which
protects the socket, the card, and the system power
supplies against damage. A second level of protection is
provided by thermal shutdown circuitry which protects
both switches against over-temperature conditions.

5VIN (Pin 2): 5V Input Supply Pin. The 5VIN supply pin
serves two purposes. The first purpose is as the power
supply inputforthe 5V NMOS switch. The second purpose
is to provide powerforthe input, gate drive, and protection
circuitry for both the 3.3V and 5V Vee switches. This pin
must therefore be continuously powered.
EN1, END (Pins 3, 4):Enable Inputs. The two Vee Enable
inputs are designed to interface directly with industry
standard PCMCIA controllers and are high impedance
CMOS gates with ESD protection diodes to ground, and

should not be forced below ground. Both inputs have
about 1OOmVof built-in hysteresis to ensure clean switching between operating modes. The LTC1470 is designed
to operate without12V power. The gates of the Vee NMOS
switches are powered by charge pumps from the 5VIN
supply pins (see Applications Information section for
more detail). The Enable inputs should be turned off (both
asserted high or both asserted low) at least 100j.lS before
the 5VIN power is removed to ensure that both Vee NMOS
switch gates are fully discharged and both switches are in
the high impedance mode.
GND (Pin 5): Ground Connection.

3VIN (Pins 6, 7): 3V Input Supply Pins. The 3VIN supply
pins serve as the power supply inputforthe 3.3V switches.
These pins do not provide any powerto the internal control
circuitry and therefore do not consume any power when
unloaded or turned off.

4-429

LTC 1470/LTC1471

Pin FunOlons
LTC1471
AOUT, BOUT(Pins 1, 16, 8, 9):Output Pins. The outputs
of the LTC1471 are switched between three operating
states: OFF, 3.3Vand 5V. These pins are protected against
accidental short circuits to ground by SafeS lot current
limit circuitry which protects the socket, the card, and the
system power supplies against damage. Asecond level of
protection is provided by thermal shutdown circuitry.
5VIN (Pins 2, 10): 5V Input Supply Pins. The 5VIN supply
pins serve two purposes. The first purpose is as the power
supply input for the 5V NMOS switches. The second
purpose is to provide power for the input, gate drive, and
protection circuitry. These pins must therefore be continuously powered.
EN1, END (Pins 3, 4, 11, 12):Enable Inputs. The enable
inputs are designed to interface directly with industry
standard PCMCIA controllers and are high impedance
CMOS gates with ESD protection diodes to ground, and

BLOCK DIAGRAm

should not be forced below ground. All four inputs have
about 1OOmVof built-in hysteresis to ensure clean switching between operating modes. The LTC1471 is designed
to operate without12V power. The gates ofthe Vee NMOS
switches are powered by charge pumps from the 5VIN
supply pins {see Applications Information section for
more detail}. The enable inputs should be turned off at
least 1OO~ before the 5VIN power is removed to ensure
that all NMOS switch gates are fully discharged and are in
the high impedance mode.
GND (Pins 5, 13): Ground Connections.
3VIN (Pins 6, 7, 14, 15):3V Input Supply Pins. The 3VIN
supply pins serve as the power supply input for the 3.3V
switches. These pins do not not provide any power to the
internal control circuitry, and therefore, do not consume
any power when unloaded or turned off.

(lTC1470 or 1!2lTC1471)

. - - - - - - _ - 5VIN

GATE CHARGE

~________~

.-----1 DIS~~2RGE

0.14Q

CONTROL LOGIC
END

ENI

4-430

OSCILLATOR
AND BIAS

TIL-TO-CMOS
CONVERTER

CHARGE
PUMP

GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC

CURRENT LIMIT
AND THERMAL
SHUTDOWN

OUTPUT

LTC1470/LTC1471
OPERATion
rhe LTC1470 (or 1/2 of the LTC1471) consists of the
'ollowing functional blocks:

on slowly (400j.lS typical rise time) but turns them off
much more quickly (typically 10j.lS).

Input TTL/CMOS Converters

Bias, Oscillator and Gate Charge Pump

rhe enable inputs are designed to accommodate a wide
-ange of 3V and 5V logic families. The input threshold
foltage is approximately 1.4V with approximately 100mV
If hysteresis. The inputs enable the bias generator, the
late charge pumps and the protection circuity which are
lowered from the 5V supply. Therefore, when the inputs
ire turned off, the entire circuit is powered down and the
5V supply current drops below 1fJA.

When either the 3.3V or 5V switch is enabled, a bias
current generator and high frequency oscillator are turned
on. The on-chip capacitive charge pump generates approximately 12Vof gate drive for the internal low RDS(ON)
NMOS Vee switches from the 5VIN power supply. Therefore, an external12V supply is not required to switch the
Vec output. The 5VIN supply current drops below 1fJA
when both switches are turned off.

COR Input Circuitry

Gate Charge and Discharge Control

3y employing an XOR function, which locks out the 3.3V
;witch when the 5V switch is turned on and locks out the
5V switch when the 3.3V switch is turned on, there is no
langer of both switches being on at the same time. This
(OR function also makes it possible to work with either
Ictive -low or active-high PCMCIA Vce switch control logic
see Applications Information section for further details).

All switches are designed to ramp on slowly (400j.lS typical
rise time). Turn-off time is much quicker (typically 10j.lS).
To ensure that both Vee NMOS switch gates are fully
discharged, program the switch to the high impedance . , . .
mode at least 100j.lS before turning off the 5V power . .
supply.
Switch Protection

Jreak-Before-Make Switch Control
Mt-in delays are provided to ensure that the 3.3Vand 5V
;witches are non-overlapping. Further, the gate charge
lUmp includes circuitry which ramps the NMOS switches

~PPLICATlons

InFORmATiOn

'he LTC1470/LTC1471 are designed to interface directly
lith industry standard PCMCIA card controllers.
~terfacing

with the CL-PD6710

igure 1 is a schematic diagram showing the LTC1470
lterfaced with a standard PCMCIA slot controller. The
JC1470accepts logic control directly from the CL-P0671 O.
'he XOR input function allows the LTC1470 to interface
irectly to the active-low Vee control outputs of the CL'06710 for 3.3V/5V voltage selection (see the following
;witch Truth Table). Therefore, no "glue" logic is required
1 interface to this PCMCIA compatible card controller.

L7lJD~

Both switches are protected against accidental short circuits with SafeSlot fold back current limit circuits which
limit the output current to typically 1A when the output is
shorted to ground. Both switches also have thermal shutdown which limits the power dissipation to safe levels.

3,3V --1~-"""'---'

5V--1I--CL·PD6710

Vcc_31---Vcc_51----

TO CARD

~~-'--":""Vcc PINS

1470J71RJl

Figure 1. Direct Interface to CL-PD6710 PCMCIA Controller

4-431

LTC1470/LTC1471
APPLICATions InFoRmATion
Truth Table for CL-PD6710 Controlle.r
A Vcc 3

ENO

A..Vcc_5
EN1

0
0

0

1
1

0

1

Supply Bypassing
For best results bypass the supply input pins with 1JlF
capacitors as close as possible to the LTC1470. Sometimes much larger capacitors are already available at the
outputs of the 3.3V and 5V power supply. In this case it is
still good practice to use 0.1 JlF capacitors as close as
possible to the device"especially if the power supply
output capacitors are more than 2" away on the printed
circuit board.

OUT
Hi-Z

3.3V
5V
Hi-Z

1

Interfacing with "365" Type Controllers
The LTC1470 also interfaces directly with "365" type
controllers as shown in Figure 2. Note that the Vee Enable
inputs are connected differently than to the CL -PD671 0
controller because the "365" type controllers use activehigh logic control of the Vee switches (see the following
Switch Truth Table). No "glue" logic is required to interface to this type of PCMCIA compatible controller.
3.3V

-t---......---.

"365" TYPE
CONTROLLER

Supply Sequencing

A_Vec_END 1 - - - -

t--.--.......

TO CARD
~ Vcc PINS

A_Vcc_EN1 1 - - - -

1410171F02

Figure 2. Direct Interface with "365" Type PCMCIA Controller
Truth Table for "365" Type Controller

ENO

4-432

The output pin is designed to ramp on slowly, typically
400~ rise time. Therefore, capacitors as large as 150JlF
can be driven without producing voltage spikes on the
3VIN or 5VIN supply pins (see graphs in Typical Performance Characteristics section). The output pin should
have a 0.1 JlF to 1JlF capacitor for noise reduction and
smoothing.
A 10k pull-down resistor is recommended at the output to
ensu re thatthe output capacitor is fu lIy discharged when the
output is switched OFF. This resistor also ensures that the
output is discharged between the 3.3V and 5V transition.

5V _ _ _-

A_Vcc_END

Output Capacitors and Pull·Down Resistor

A..Vcc_EN1
EN1

0
0

0

1
1

0

1
1

OUT
Hi-Z
3.3V
5V
Hi-Z

Because the 5V supply is the source of power for both of the
switch control circuits, it is best to sequence the power
supplies such that the 5V supply is powered before, or
simultaneous to, the application of 3.3V.
It is interesting to note, however, thatthe switches are NMOS
transistors which require charge pumps to generate gate
voltages higher than the supply rails for full enhancement.
Because the gate voltages start at OV when the supplies are
first activated, the switches always start in the off state and
do not produce glitches at the outputs when powered.
Ifthe5V supply must be turned off, itis importantto program
all switches to the Hi-Z or OV state at least 1OO~ before the
5V power is removed to ensure that the NMOS switch gates
are fully discharged to OV. Whenever pOSSible, however, it is
best to leave the 5VIN pin(s) continuously powered. The
LTC1470/LTC1471 quiescent current drops to <1pA with all
the switches turned off and therefore no 5V power is
consumed in the standby mode.

.L7lJ!J~

LTC 1470/LTC 1471
APPLICATions InFoRmATion
TOTAL SYSTEM COST CONSIDERATIONS

LTC1142HV Auxiliary Winding Power Supply

The cost of an additional step-up switching regulator, inductor, rectifier and capacitors to produce 12V for VPP can be
eliminated by using an auxiliary winding on either the 3.3V
or 5Voutput ofthe system switching regulatorto produce an
auxiliary 15V supply for VPP power.

Figure 3 is a schematic diagram which describes how a
loosely regulated 15V power supply is created by adding an
auxiliary winding to the 5V inductor in a split 3.3V/5V
LTC1142HV power supply system. An LT1313, dual VPP
regulator/driver with SafeSlot protection, produces "clean"
3.3V, 5V and 12V power from this loosely regulated 15V
output for the PC card slot VPP pins. (See LT1312 and
LT1313 data sheets for further detail.)

And, because the LTC1470/LTC1471 do not require 12V
power to operate (only 5V), the 12V VPP regulation and
switching may be operated separately from the 3.3V/5VVcc
switching. This increases system configuration flexibility
and reduces total system cost by eliminating the need for a
third regulator for 12V power.

Atums ratio of 1:1.8 is used fortransformerT1 to ensure that
the input voltage to the LT1313 falls between 13V and 20V
under all load conditions. The 9Voutput from this additional

VIN
6.5VTO 18V
VIN ~1O::"'-~~_ _ _ _ _ _-IH--'--_ _ _ _ _ _ _ _--'

+ Cl
*,681lF

1/2 LTCl142HV

(5V REG)
SENSE' ~15::----._ _-w.v-----t
C2
1000pF R2
SENSE- ~14",--~~_-,111\00nfv-_+-_~_ _-4-

• LPE-6562-A026 DALE (605) 665-9301
~~

_ _ _ TO "A" SLOT
Vee PINS

_~

_ _ _ TO "8" SLOT

Vee PINS

Figure 3. Cost Effective Complete SafeSlot Dual PCMCIA Power Management System
(with 15V Auxiliary Supply from LTC1142HV 5V Regulator Inductor)

4-433

LTC1470/LTC1471
APPLICATions InFoRmATion
winding is rectified by diode 02, added to the main 5Voutput
and applied to the input of the LT1313. (Note that the
auxiliary winding must be phased properly as shown in
Figure 3.)
.
When the 12Voutput is activated by aTTL high on eitherVPP
enable lines, the 5V section of the LTC1142HV is forced into
continuous mode operation. Aresistor divider composed of
R2, R3 and switch 03 forces an offset which is subtracted
from the internal offset at the Sense- input (pin 14) of the
LTC1142HV. When this external offset cancels the built-in
25mV offset, Burst Mode™ operation is inhibited and the
LTC1142HV is forced into continuous mode operation. (See
LTC1142HV data sheet for further detail.) In this mode, the
15V auxiliary supply can be loaded without regard to the
loading on the 5V output of the LTC1142HV.
Continuous mode operation is only invoked when the LT1313
is programmed to 12V. If the LT1313 is programmed to OV,
3.3V or 5V, power is obtained directly from the main power
source (battery pack) through diode 01. Again, the LT1313
output can be loaded without regard to the loading of the
main 5V output.

R4 and C4 absorb transient voltage spikes associated with
the leakage inductance inherent in T1 's secondary winding
and ensure that the auxiliary supply does not exceed 20V.

Auxiliary Power from the LTC1142 3.3V Output
For low-battery count applications (< 6.5V) it is necessary to
modify the circuit of Figure 3. As the input voltage falis, the
5V duty cycle increases to the point where there is simply not
enough time to transfer energy from the 5V primary winding
to the auxiliary winding. For applications where 12V load
currents exist in conjunction with these low input voltages,
use the circuit shown in Figure 4.ln this circuit, the auxiliary
15V supply is generated from an overwinding on the 3.3V
inductor of the LTC1142 regulator output.
In Figure 3, power is drawn directly from the batteries
through 01 when the regulator is in Burst Mode operation
and the VPP pins require 3.3Vor 5V.ln this circuit, however,
03 and 04 force the LTC1142 3.3V regulator into continuous
mode operation whenever 3.3V, 5V or 12V is programmed
at the VPPOUT pins of the LT1313. (See the LT1312 and
LT1313 data sheets for further detail.)
Burst Mode is a trademark of Linear Technology Corporation.

VIN
5.4VTO 11V
V
IN

24

112 LTC1142
(3.3V REG)

D4
18V

+

C5
681!F

R2
R4
100n
0.033n
SENSE- r28;;....----i_----'lWv--_t-_+-_+-_~- 3.3V
OUTPUT
HC86
AENVPPO ----\~
Q3
AENVPP1 --/L-./"I112N7002
HC86
BENVPPO
BENVPP1

':'

----\"----------.J ~ ~~7002

--/~'I

'CTX02-12753
COILTRONICS (407) 241-7876

Figure 4. Deriving 15V from the 3.3V Output of the LTC1142 for VPP Power

4-434

141(1{l1F1)4

LTC1470/LTC1471
TYPICAL APPLICATions
Dual Slot 3.3V/5V PCMCIA Controller with SafeSlot Current Limit
(Systems with No 12V Power Requirements)
3.3V _ - - -_ _......- _ - .

5V_

'"

VCC(OUn
PROGRAMMED
T05V

0.25

9:
w

80

a:

<0

20

-

I--"

0.15

a:

:J:

~ 0.10

I--"r-

s:
CJ)

0.05

o

o

o

~

~
~
100
JUNCTION TEMPERATURE (·C)

3VIN SUPPLY VOLTAGE (V)

3VIN SUPPLY VOLTAGE (V)
LTC1472TPC04

--

I---

>

"'

l - I-'
oV

125

LT1472TPC06

LTC1472TPC05

Inrush Current (5V SWitch)

3.3V Switch Resistance

.......-

f-"

LTC1472TPC02

LTC1472 TPCOl

TA = 25·C OUTPUT
PROGRAMMED TO OFF

200

a:
a:

::J

TA = 2soCVCC(OUT)
PROGRAMMED
TO 3.3V, NO LOAD

2S0

Inrush Current (3.3V SWitch)

0.30

9:

LIMITE, , ) V

r

w

<.:>

z

;'!:
CJ)

0.20

en

~ 0.15

:J:

~

~

0.10

t.- ~

~ t--

~

I-

w

'"~

>

Roup 10n

o

~

~

~

100
JUNCTION TEMPERATURE i·c)

12S

J' V

~
COUT =15~F
ROUT =10n

-

-0.2

0

0.2

0.4 0.6 0.8
TIME (ms)

t

<

COUT =151'~
ROUT =6.6n ,

~
~

~

o

1.0

1.2 1.4

LTC1472TPCOO

4-440

1 ,I

COUT =150l'F ROUT =6.6n

'"~

~

0

1/

w

/V
JV

5

13o

I,

TJ =25·C

1\

~··"~:W

~

~ 0.05

o

TJ =2S·C

CURRENT

VCC(OUn
PROGRAMMED
TO 3.3V

0.25

JA

IV

0
-0.2

COUT =150l'F _
ROUT =6.611
I
I
0.4 0.6 0.8 1.0 1.2 1.4
TIME (ms)

0

0.2

LTC1472TPCQ9

LTC 1472
TYPICAL PERFORmAnCE CHARAOERISTICS (VPP Section) Vee END = Vee EN1 = DV
VeC(IN) Supply Current (No Load)

VPPIN Supply Current (OFF)

VPPIN Supply Current (No Load)

100
TA = 25'C

1

80

Ii
:J:

60

'"'

40

_

-

VPPOUT PROGRAMMED
TO VPPIN OR VCC(INI

V-

>=>

:n
z

~6P(~;;ri 2V -f--+--+-+----1

'1 100
f-

:J:

=>
>-'
>-

Tp 25°C

TA = 25'C
VPPOUT PROGRAMMED
TO OV OR Hi-Z

20

Ir

8'

>

-20

iIi
a::

80

::;

'-'

60

=>


20

a::
=>

-=-

""-

z
ci:"
"-

-./
VPPOUT PROGRAMMED
TO OV OR Hi-Z

-1

o

o

10
VPPIN SUPPLY VOLTAGE

VCC(INI SUPPLY VOLTAGE (V)

VOD Supply Current (OFF)

12

14

10
VPPIN SUPPLY VOLTAGE

120
TA=25'C
VPPOUT PROGRAMMED
TO VPPIN. NO LOAD

100

'1
f-

iIi
a::

~

"-

=>



Voo SUPPLY VOLTAGE (V)

~

20

o

/

I
I

y V

a::

=>

o

Voo SUPPLY VOLTAGE (V)

TA = 25'C
VPPOUT PROGRAMMED
TO VPPIN. NO LOAD

100

/

80

a::

=>
'-'

14

VDD Supply Current (ON)

VDD Supply Current (No Load)
120

TA = 25'C
VPPOUT PROGRAMMED
TO OV OR Hi-Z

12

I

o

~IVPPIN[12V

I
VDD SUPPLY VOLTAGE (V)

LTC14nTJ>C14

LTC1472T1'C15

Switch Resistances
10

-

VCCIN TO VPPOUT

I- r-

1~
VPPIN TO VPPOUT

0.1

o

20

40
60
TEMPERATURE ('C)

80

100

4-441

•

LTC 1472
Pin FUnOIOnS
Enable Input (Pins 3,4,7,8)

VCC(IN) Supply (Pin 12)

The two Vcc and two VPP Enable inputs are designed to
interface directly with industry standard PCMCIA controllers. They are high impedance CMOS gates with ESD
protection diodes to ground, and should not be forced
below ground. Both sets of inputs have about 1OOmV of
built-in hysteresis to ensure clean switching between
operating modes.

The VCC(IN) supply pin is typically connected directly to the
VCC(OUT) pin from the Vcc switch section of the LTC1472.
It can also be connected directly to a 3.3V or 5V power
supply if desired. This supply pin does not provide any
power to the internal control circuitry and is simply the
inputto the VCC(INrVPPOUT switch and therefore does not
consume any power when unloaded or turned off.

Shutdown Output (Pin 6)

5VIN Supply (Pin 2)

The LTC1472 is designed to operate without continuous
12V power. The gates of the Vcc NMOS switches are
powered by charge pumps from the 5VIN supply, and the
gates of the VPP NMOS switches are powered by charge
pumps powered from the Voo supply when 12V is not
present at the VPPIN pin (see Application Information for
more detailS). Therefore, the external 12Vregulatorcan be
shut down most of the time, and only turned on when
programming the socket VPP pin to 12V.

The 5VIN supply pin serves two purposes. The first purpose is as the power supply inputforthe 5V NMOS switch.
The second purpose is to provide powerforthe input, gate
drive and protection cirCUitry for both the 3.3Vand 5V Vcc
switches, this pin must be continuously powered.

The shutdown output is active high; i.e. the system 12V
regulator is shut down when this output is held high and
turned on when this output is held low.
VPPIN Supply (Pin 5)
The VPPIN supply pin serves two purposes. The first
purpose is to provide power and gate drive for the VPPINVPPOUT switch. The second purpose is to provide optional
12V gate drive forthe VCC(INrVPPOUT switch. If, however,
this 12V power is not available, gate drive is obtained
automatically from the 5V Voo supply by an internal5V to
12V charge pump converter.
Voo Supply (Pin 9)
The Voo pin provides power for the input, charge pump
and control circuitry for the VPP section of the LTC1472
and therefore must be continuously powered. The standby
quiescent current is typically 0.1 ~ when the VPPOUT pin
is programmed to OVor Hi-Z and only rises to micropower
levels when the VPP switches are active.

4-442

The enable inputs should be turned off (both asserted high
or both asserted low) at least 1OOJ.lS before the 5VIN power
is removed to ensure that both VCC NMOS switch gates are
fully discharged and both switches are in the high impedance mode.
3VIN Supply (Pins 14,15)
The 3VIN supply pin serves as the power supply input for
the 3.3V switch. This pin does not provide any powertothe
internal control circuitry and therefore does not consume
any power when unloaded or turned off.
VCC(OUT) and VPPOUT Output (Pins 1,11,16)
The Vcc output of the LTC1472 is switched between the
three operating states: OFF, 3.3V, and 5V. The VPP output
is switched between four operating states: 0, VCC, 12Vand
Hi-Z. Both pins are protected against accidental shortcircuit conditions to ground by independent SafeSlot
foldback current-limit Circuitry which protects the socket,
card and the system power supplies against damage. A
second level of protection is provided by independent
thermal shut down circuitry which protects each switch
against overtemperature conditions.

LTC 1472
BLOCK DIAGRAm
r----------1r- 5VIN
GATEA~DARGE

t------J

0.140

DISCHARGE
CONTROL LOGIC

Vee ENO

Vee EN1

DL-TO-CMOS
CONVERTER

OSCILLATOR
AND BIAS

DUO-CMOS
CONVERTER

CHARGE
PUMP

CURRENT LIMIT
AND THERMAL
SHUTDOWN

VeC(DUT)

GATE CHARGE
AND

co~~~~t~~~IC t - - - - - - J

0.120

l'

VOO--SHDN

-------0<;,.

VPP ENO

DL-TO-CMOS
CONVERTER

VPP EN1

DL-TO-CMOS
CONVERTER

. - - - - - - - - -......GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC

CHARGE
PUMP

VPPIN

0.512

OSCILLATOR
AND BIAS

.----+-- VCC(IN)
GATE CHARGE
AND

>---1----., co~~~~t~~~IC
10V

CHARGE
PUMP
~"""'--VPPOUT

1000

OPERATion
The LTC1472 protected switch matrix is designed to be a
complete single slot solution for Vee and VPP switching in
aPCMCIAcompatible card system. The LTC1472 consists
Df two independent functional sections: the Vee switching
section, and the VPP switching section.

THE Vee SWITCHING SECTION
The Vee switching section of the LTC1472 consist of the
following functional blocks:

Vee Switch Input TTL-CMOS Converters
The LTC1472 Vee inputs are designed to accommodate a
wide range of 3Vand 5V logic families. The inputthreshold
voltage is approximately 1.4V with approximately 100mV
of hysteresis. The inputs enable the bias generator, the
gate charge pumps and the protection circuity which are
powered from the 5VIN supply. Therefore, when the inputs
are turned off, the entire circuit is powered down and the
5VIN supply current drops below 1!lA.

4-443

LTC 1472
OPERATion
Vee XOR Input Circuitry
The LTC1472 ensures that the 3.3V and 5V switches are
never turned on at the same time by employing an XOR
function which locks out the 3.3V switch when the 5V
switch is turned on, and locks out the 5V switch when the
3.3V switch is turned on. This XOR function also makes it
possible for the LTC14 72 to work with either active-low or
active-high PCMCIAVeeswitch control logic (seeApplications Information for further details).

to ground. Both switches also have independent thermal
shutdown which limits the power dissipation to safe
levels.
Vee Switch Truth Table
Vee END

Vee ENl

Vee OUT

0
1
0
1

0
0
1
1

OFF
5V
3.3V

OFF

Vee Break-Before-Make Switch Control

THE VPP SWITCHING SECTION

The LTC1472 has built-in delays to ensure that the 3.3V
and 5V switch are non-overlapping. Further, the gate
charge pumps include circuity which ramps the NMOS
switches on slowly (400J.lS typical rise time) but turn off
much more quickly (typically 10J.lS).

The VPP switching section of the LTC1472 consists of the
following functional blocks:

Vee Bias, Oscillator and Gate Charge Pump
When either the 3.3V or5V switch is enabled, a bias
current generator and high frequency oscillator are turned
on. An on-chip capacitive charge pump generates approximately 12V of gate drive for the internal low ROS(ON)
NMOS Vee switches from the 5VIN power supply. Therefore, an external12V supply is not required to switch the
Vee output. The 5VIN supply current drops below 11JA
when both switches are turned off.
Vee Gate Charge and Discharge Control
Both Vee switches are designed to ramp on slowly (400J.lS
typical rise time). Turn off time is much quicker
(typically 1OJ.lS).
To ensure that both Vee NMOS switch gates are fully
discharged, program the switch to the high impedance
mode at least 100J.lS before turning off the 5VIN power
supply.
Vee Switch Protection
Two levels of protection are designed into each of the
power switches in the LTC1472. Both Vee switches are
protected against accidental short circuits with SafeSlot
fold-back current limit circuits which limit the output
currentto typically 1Awhen the Vee(OUT) output is shorted

4-444

VPP Switch Input TTL-CMOS Converters
The VPP inputs are designed to accommodate a wide
range of 3V and 5V logic families. The input threshold
voltage is 1.4V with", 1OOmV of hysteresis. The inputs
enable the bias generator, the gate charge pumps and the
protection circuitry. When the inputs are turned off, the
entire circuit is powered down and the Voo and VPPIN
supply currents drop below 11JA.
VPP Break-Before-Make Switch Control
The VPP input section has built-in delays to ensure thatthe
VPP switchs are non-overlapping. Further, the gate charge
pumps include circuitry which ramps the NMOS switches
on slowly but turns them off quickly.
VPP Bias, Oscillator and Gate Charge Pump
When either the VPPIN-VPPOUT or Vee(IN)-VPPOUT switch
is enabled, a bias current generator and high frequency
oscillator are turned on. An on-Chip capacitive charge
pump generates approximately 23V of gate drive for the
internal low ROS(ON) NMOS VPPIN-VPPOUT switch from
the VPPIN power supply. The gate of the Vee(IN)-VPPOUT
NMOS switch is either powered by the external 12V
regulator (if left on) or automatically from abuilt-in charge
pump powered from the Voo supply when the external12V
supply drops below 10V. The Voo supply current drops
below 11JA when switched to either the OV or Hi-Z mode.

LTC 1472
)PERATlon
fPP Gate Charge and Discharge Control
-he VPP switches are designed to ramp slowly (typically
ens of f.lS) between output modes to reduce supply
"itching when powering large capacitive loads.

cally 1OOmA when protecting the 12V VPPIN supply and
60mA when protecting the Vee(IN) supply. (Higher operating currents are allowed at higher output voltages). Both
switches also have thermal shutdown.
VPP Switch Truth Table

fPP Switch Protection

VPP END

VPPENl

VPPOUT

0
0

0
1

VCC(IN)

loth VPP power switches are protected against accidental
,hort circuits with SafeSlot fold-back current limit circuits
vhich limit the short-circuit (OV) output current to typi-

~PPLICATlons

1

0

1

1

OV

VPP,N
Hi-Z

InFORmATiOn

-he LTC1472 is acomplete single slot Vee and VPP power
.upply switch matrix with SafeSlot current limit protection
In both outputs. It is designed to interface directly with
ndustry standard PCMCIA card controllers and to indusry standard 12V regulators.

nterfacing to the CL-PD671 0 and the L~1301
:igure 1 shows the LTC1472 interfaced to a standard
ICMCIA slot controller and an LT1301 step-up switching
egulator. The LTC1472 accepts logic control directly
rom the CL-PD6710 and in turn, controls the LT1301 to
lrovide clean 12V VPP programming power when reluired. The LT1301 is then shutdown (10~ standby
urrent) at all other times to conserve power.
'he XOR Vee input function allows the LTC1472 to interace directly to the active-low Vee control outputs of the
:L-PD6710 for 3.3V/5V voltage selection (see the Vee
;witch Truth Table). Therefore, no "glue" logic is required
[) interface to this PCMCIA compatible controller.
'he LTC1472 provides SafeSlot current-limit protection
~rthe LT1301 step-up regulator, the system 3.3V and 5V
egulators, the socket and the card. Further, depending
pon the system regulator's own current limits, it may
IIow the system power supplies to continue operation
uring a card/slot short circuit without losing data, etc.

MBRS130LT3

5v-_ _ _,....rY'YV'~--__+_-_....:......:.....,

LT1301
SHDN

NC

T O.1~F

--

47~F

T16V

--

TANT

3.3V-_-_---.

---_--'---oJ-! VPP1
VPP2
PCMCIA
CARD SLOT

Vce
-+---.-=~HVee

Figure 1. Direct Interface to Industry Standard PCMCIA
Controller and LT1301 Step-Up Switching Regulator

4-445

•

LTC 1472
APPLICATions InFoRmATion
Interfacing to "365" Type Controllers
The LTC1472 also interfaces directly with "365" type
controllers as shown in Figure 2. The Vee Enable inputs
are connected differently than to the CL -PD671 0 controller because the "365" type controllers use active-high
logic control of the Vee switches (see the Vee Switch Truth
Table). No "glue logic" is required to interface to this type
of PCMCIA compatible controller.

12V Power Requirements
Note that in Figure 2, a "local" 5V to 12V converter is not
used. The LTC1472 works equally well with or without
continuous 12V power. If the main power supply system
has 12V continuously available, simply connect it to the
VPPIN pin. Internal circuitry automatically senses its presence and uses it to switch the internal VPP switches.
The 12V shutdown output can be used to shut down the
system 12V power supply (if not required for any purpose
other than VPP programming).

5V Power Requirements
The LTC14 72 has been designed to operate without continuous 12V power, but continuous 5V power is required

at the VDD and 5VIN supply pins for proper operation and
should always be present when acard is powered (whether
it is a 5Vor 3.3V only card).
If the 5V power must be turned off, for example, to enter
a3.3V only full system "sleep" mode, the 5V supply must
be turned off at least 1OO!J.S after the Vee and VPP switches
have been programmed to the Hi-Z or OV states. This
ensures that the gates of the NMOS switches are completely discharged.
Also, the Vee switches cannot be operated properly without 5V power. They must be programmed to the off state
at least 100!J.S prior to turning the 5V supply off, or they
may be left in an indeterminate state.

Supply Bypassing
For best results, bypass the supply input pins with 1,.u:
capaCitors as close as possible to the LTC14 72. Sometimes, much larger capaCitors are already available at the
outputs ofthe 3.3V, 5Vand 12V powersupply.ln this case,
it is still good practice to use 0.1,.u: capaCitors as close as
possible to the LTC1472, espeCially if the power supply
output capacitors are more than 2" away on the printed
circuit board.

12V-----t------,

5V
VPP1
VPP2
"365"TYPE
CONTROLLER

~VPP_EN1

PCMCIA
CARD SLOT

Vee
Vee

A_Vcc_EN1

LTC1472-Rl2

Figure 2. Direct Interface to Industry Standard PCMCIA Controller and LT1301 Step-Up Switching Regulator

4-446

..L7lJ!J~

LTC 1472
'PPLICATlons InFORmATion
lutput Capacitors
'he VCC(OUT) pin is designed to ramp on slowly, typically
·OO!JS rise time. Therefore, capacitors as large as 150).lf
an be driven without producing voltage spikes on the
iVlN or 3VIN supply pins (see graphs in Typical Pertornance Characteristics). The VCC(OUT) pin should have a
1.1).1f to 1).1f capacitor for noise reduction and smoothing.
'he VPPOUT pin should have a 0.01).1f to 0.1).1f capacitor
Dr noise reduction. The VPPIN capacitors should be at
last equal to the VPPOUT capacitors to ensure smooth
ransitions between output voltages without creating spikes
In the system power supply lines.
;upply Sequencing
iecause the 5V supply is the source of power for both the
rcc and VPP switch control logic, it is bestto sequence the
,ower supplies such that the 5V supply is powered before
if simultaneous to the application of 3.3V or 12V power.
[ is interesting to note however, that all of the switches in
le LTC1472 are NMOS transistors which require charge
umps to generate gate voltages higher than the supply
ails for full enhancement. Because the gate voltages start

L7lJ!J~

a OV when the supplies are first activated, the switches
always start in the off state and do not produce glitches at
the output when powered.
Some PCMCIA switch matrix products employ PMOS
switches for 12VVPP control and great care must be taken
to ensure that the 5V control logic is powered before the
12V supply is turned on. If this sequence is not followed,
the PMOS VPP switch gate may start at ground potential
and the VPP output may be inadvertently forced to 12V.
Although, not advisable, it is possible to power the 12V
VPPIN supply pin of the LTC1472 priorto application of 5V
power. Only about 501lA flows to the VPPOUT pin under
these conditions.
If the 5V supply must be turned off, it is important to
program all switches to the Hi-Z or OV state at least 100!JS
before the 5V power is removed to ensure that all NMOS
switch gates are fully discharged to OV .
Whenever possible however, it is bestto leave the 5VIN and
VDD pins continuously powered. The LTC1472 quiescent
current drops to <1IlA with all the switches turned off and
therefore no 5V power is consumed in the standby mode.

4-447

•

LTC 1472
TYPICAL APPLICATions
Dual Protected PCMCIA Power Management System

MBRS130LT3
3.3Vor5V __....._ _...._ ........r.,-yY"\......_ _ _~I-_ _........;.12;;.;V~,.....

LT1301
SHDN

IUM
GND

3.3V-....-----t---.

NC

T

--

47flF
O. 1flF T16V
TANT

TO.

--

1flf

5V-....- -....-

- - -.....-.;.....;;"'--'---t-.....-I VPP1
VPP2
PCMCIA
CARD SLOT
A_VPP_PGM

t--t--------

A_VPP_Vcc

1--1--------

"vcc

A_Vcc_3

t--t-------t--t--------

-+-....-~.;.;.;;;..;.;..;...;..-t-.....-I Vee

A_Vcc--5

3.3V -

.....- - - - . . . - - . ,

CL-PD6720

5V-.....- -....-

- - -.....---'-""'----'--.....-1 VPP1
VPP2
PCMCIA
CARD SLOT
B_VPP]GM
B_VPP_Vcc
B_Vec_3
B_Vee_5

t--------t---------

1--------1---------

Vec

-+-""'---";;';';':";;:;;';':';;":"-""'-1 Vee
LTC1472-TAO'l

'FOR 5V TO 12V CONVERSION USE 10flH, COILCRAFT D01608-103. SEE LT1301 DATA SHEET
FOR MORE DETAILED INFORMATION ON INDUCTOR AND CAPACITOR SELECTION.

4-448

L7lJ!J~

LTC 1472
TYPICAL APPLICATions
Single Protected PCMCIA Power Management System
Using the LT1301 Powered from 3.3V or 5V

MBRS130LT3

12V

+---......-----.

3.3V OR 5V-......- -......---3.78
:::3.77

g

.00

V

~

..........

4.800

..........

4.775

il'! 4.750
0

25

50

TEMPERATURE (0C)

75

100

4.725
-50

..--

e: 3.74 ,......, .,.,.. ...-

'";:; 3.75

............

N

:5

'"~3.76

...........

'"a: 4.825

SHUTPOWN THRE~

-25

mA
mA

Regulator 1 Adjust Pin Voltage vs
Temperature

~4.950

::>

.10

.90
-50

••
•

Regulator 2 Oulpul Voltage vs
Temperature

.60

.20

mV

5
5

PERFORmAnCE CHARAOERISTICS

Low-Battery Detector Thresholds
vs Temperature

040

3
3

UNITS

15

Nole 7: Operating conditions are limited by maximum junction
temperature. The regulated output specification will not apply for all
possible combinations of input voltage and output current. When
operating at maximum output current, the input voltage range must be
limited. When operating at maximum input voltage, the output current
range must be limited.
Nole 8: Regulator 1 of the LT1239 is tested and specified with the adjust
pin (pin 1) tied to the output pin (pin 16). See Applications Information.
Nole 9: Dropout voltage is the minimum input/output voltage required to
maintain regulation at the specified output current. In dropout, the output
voltage measured at the package pins will be equal to (VIN - VOROPOUT).
Nole 10: The quiescent current of the comparator is included in the
ground pin current and quiescent current specifications for regulator 1.
The comparator output is turned off (pin 13 =OV, pin 12 =5V) during
these tests.
Note 11: Ground pin current for regulator 1 is tested with VIN = VOUT
(nominal) and a current source load. This means that the device is tested
in it's dropout region. Ground pin current will decrease slightly at higher
input voltages.
Nole 12: Adjust pin current flows into the adjust pin.
Nole 13: Shutdown pin current at VSHON = OV flows out of
the shutdown pin.
Nole 14: 6.BV is the nominal voltage of two lithium-ion cells.

• denotes specifications which apply over the full operating
Iperature range.
e 1: All voltages are with respect to the ground pins of the device
IS 2, 4, 5) unless otherwise specified.
e 2: The shutdown pin input voltage rating is required for a low
,edance source. Internal protection devices connected :0 the shutdown
will turn on and clamp the pin to approximately 7V or -0.6V. This
le allows the use of 5V logic devices to drive the pin directly. For high
'edance sources or logic running on supply voltages greater than 5.5V,
maximum current driven into the shutdown pin must be limited to

~PICAL

MAX

TYP
0

'" 3.73
=;
c

« 3.72
3.71

-25

0

25

50

75

100

TEMPERATURE (0C)

3.70
-50

-25

0

25

50

75

100

TEMPERATURE (Oc)
LT1239'TPC02

4-457

LT1239
TYPICAL PERFORmAnCE CHARQOERISTICS
Regulator 2 IMON2 Current vs
Output Current
250

250
VIN2 =1 6.8V
VIMON2 =ov

~

ffi .150

a:
a:

::>

j

,..--,---,...---r---r---.,

40

/1"

/

/

200

~

/

I---+---+-

10

30

15
a:

25

a:
::>
<>

20

w

15

::;

10

0Z

<>
en
w

'"

501---~~~--+-~-~

~
o

~

40
20
30
OUTPUT CURRENT (rnA)

r\

\

0-

50

o

VAOJ (PIN 1) = VOUT (PIN 16)

35

200

~ 100

Regulator 1, Comparator Quiescel
Current vs Input Voltage, Pin 14

Regulator 1 IMON Current vs
Output Current

10

50

~

o

40
20
30
OUTPUT CURRENT (rnA)

It

VPIN3= OV
f--

'---HiEGrrr

o

50

StjOWr)

5
INPUT VOLTAGE, PIN 14 (V)

LT12390Ti't05

Comparator Output Saturation
Voltage vs Output Current
20

~ 350

18

~

~

~
a:

~

...... 1/

150

;:i

5

!5o

/'

100
50

......

<>

0::>
0..
0::>

::>
0..

J

12
10

V

I-

8

::>
0

w

~

~

a:

o m~ w w

14

I-

w

V

oV

/

10

0

~

16

zw

ex:
ex:
::>
<>

Ij

12

::>

~

~

0-

a:

z

18

14

a:

250

20

16

!z
w

300

!2 200

Regulator 2 Reverse Output
Current vs Output Voltage

Regulator 1 Reverse Output
Current vs Output Voltage

400

~

LT12390rPi

V

o

00 ro ~ 00100
OUTPUT CURRENT (rnA)
~

o

1

en
ex:

V
= OV
1/ VINl
ADJ (PIN 1) = VOUT (PIN 16)

~

V

a:

o
2

3 4 5 6 7 8
OUTPUT VOLTAGE (V)

9 10

V

V

V

012345.6789
OUTPUT VOLTAGE (V)

LT1239orPC08

Regulator 2, Error Amp, LowBattery Detector Quiescent Current

Shutdown Pin Threshold
2.0
1.8

~

9

1.6

30

r-.

§!!

r-..
1.4

~

1.2

~

r-....

I"'--r-...

f-- (OFF-TO-ON)
1.0 f--ILOAo = 1rnA

0::

~ 0.8
c 0.6

f--

5

1J5 0.4
0.2

o

-50 -25

(OFF.~O-ONl-

~=30mA-

.......... ......

I"'--

r--__.......... t--...

15
a:

VSHON2 = OPEN CIRC~ ~

20

/~

a:

:::>

,...<>z

15

w

1,..,-" ..... ' - .....

<>

(ON·TO-OFF)
ILOAO=lmA -

-I

1

0
25 50
75
TEMPERATURE (OC)

f':

I--

100

125

LT1239·TPC10

4-458

25

~
,...

ffl 10

::;

'"

o

o

1

---

VSHON2 =OV
(REGULATOR 2
IN SHUTDOWN)

III

2 3 4 5 6 7 8
INPUT 2 VOLTAGE, PIN 10 (V)

9 10

LT1239·TPCl1

LTl239
tin FunCTions
~J

(Pin 1): Adjust Pin of Regulator 1. The regulator will
the adjust pin to 3.75V referred to ground. Bias
ment will be approximately 50nA and will flow into the
fjust pin.

E/A (IN) (Pin 7): Noninverting Inputof the Error Amplifier.
This pin should be tied to the center tap point in the output
divider for regulator 1. The bias current for this pin will be
in the range of 3nA and it will flow out of the pin.

MD (Pin 2): Ground Pin for Regulator 1. Note that the
ree ground pins (pins 2, 4, 5) are connected together
ternally and should all be grounded externally.

E/A (OUT) (Pin 8): Output of the Error Amplifier. This is
normally connected to the center tap of the backup cells.

lrvO

~DN1

(Pin 3): Shutdown Pin for Regulator 1. Regulator
output will be on if the shutdown pin is either: 1) Left
Jating (open circuit) or 2) pulled up to the 5V rail. If the
lutdown function is not used, the shutdown pin is norally left open circuit. Regulator 1 output will be off if the
lutdown pin is pulled to ground. The shutdown pin
Irrent with the pin pulled to ground will be in the range of
tA flowing out of the pin. The shutdown pin current with
e pin pulled up to 5V will be zero.
~D (Pin 4): Ground. This ground pin is tied to the
Ibstrate ofthe die, between regulator 1and the rest of the
rcuit. It is used as an isolation barrier between regulator
and the rest of the circuitry.
~D

(Pin 5): Ground Pin for Regulator 2.

-IDN2 (Pin 6): Shutdown Pin for Regulator 2. Regulator
output will be on if the shutdown pin is either: 1) Left
lating (open circuit) or 2) pulled up to the 5V rail. If the
lutdown function is not used, the shutdown pin is norally left open circuit. Regulator 2 output will be off if the
lutdown pin is pulled to ground. The shutdown pin
mnt with the pin pulled to ground will be in the range of
IA flowing out of the pin. The shutdown pin current with
e pin pulled up to 5V will be zero.

~nCTlonAL

INPUT2 (Pin 10): Input Pin (Vce) for Regulator2, the Error
Amplifier, and the Low-Battery Detection Circuit.
IMON 2 (Pin 11): Current Monitor Pin for Regulator 2.lfthe
current monitor function is not used, this pin should be
tied to the output pin of regulator 2.
OUT 2 (Pin 12): Output of Regulator 2. It is also the
inverting input and output of the comparator. If the main
5V system supply is up and running then the comparator
output will pull the output of regulator 2 up to 5V.
5VIN (Pin 13): Noninverting Input of the comparator and
the collector of the output driver. The collector of the
output driver is normally connected to the main 5V system
supply.
INPUT 1 (Pin 14): Input Pin (Vee) of Regulator 1.
IMON 1 (Pin 15): Current Monitor Pin for Regulator 1. The
current flowing out of this pin will be approximately 11200
of the output current of regulator 1. If the current monitor
function is not used, this pin should be tied to the output
pin of regulator 1.
OUT 1 (Pin 16): Output of Regulator 1.

DESCRIPTiOn

19u1ator 1: Regulator 1 is used to supply the charging
rrent to the backup batteries. It converts the voltage on
~ main battery to a fixed output voltage to charge the
ckup cells. The output voltage is set with a voltage
lider connected between the output and ground with a
J point of the divider connected to the adjust pin. The
Julator servos its output in order to maintain the adjust
1 at 3.75V referred to ground. The resistor divider
ould be chosen such that the divider current is approxi-

l7lJD~

Ne (Pin 9): Not Connected.

mately 51JA. This means the impedance from the adjust pin
to ground should be approximately 750kn. For safety
requirements a resistor can be placed between the output
pin and the top ofthe divider that sets the regulated output
voltage. The regulatorwill regulate the voltage atthe top of
the divider. Quiescent currentwill be 1OIJA to 151JA. Output
short-circuit current will be approximately 70mA.

4-459

LT1239
FunOlonAL DESCRIPTiOn
Comparator: The output of the comparator is connected to
the output of regulator 2. This point provides power to
memory and power management circuitry. The comparator looks at the main 5V power line and the output voltage
of regulator 2. If the main 5V line is up and regulating the
comparator output will pull up to 5V and supply power to
the memory from the main 5V regulator. If the main 5V
power line drops below 4.85Vthe comparator switches off
and regulator 2 will supply power to the memory from the
backup batteries. The comparator is powered from the raw
battery voltage at the input of regulator 1.
Error Amplifier: The Error Amplifier is used to equalize the
cell voltages of two lithium-ion cells connected in series.
The error amplifier is designed to source or sink 5mA.

Low-Battery Detector: The low-battery detector circuil
acts as an undervoltage lockout. This circuit turns regula·
tor 2 and the error amplifier off if the backup batter)
voltage drops below 5V. The low-battery detector circuil
will turn regulator 2 and the error amplifier back on wher
the backup battery voltage rises above 5.3V. This circuil
has a quiescent current of approximately 3J1A in thE
undervoltage condition.
Regulator 2: Regulator 2 is used to regulate the voltage o'
the backup batteries and isolate the backup batteries frorr
the main 5V line. This regulator will prevent reverSE
currentflowfrom the main 5V supply back into the backu~
cells.

BLOCK DIAGRAm
.-----~...-.I113 5VIN

INPUT 2 10

POWER
SWITCH

SHDN1 GND

IMON1

SHDN2 GND

IMON2

OUT2

1239BD

GROUND PINS 2, 4, 5 ARE TIED TO SUBSTRATE

APPLICATions InFORmATion
Device Overview
The LT1239 provides several functions needed for backup
battery management. It provides:
1. Battery Charging: The LT1239 can be set up to charge
lithium-ion or nickel cadmium batteries in either constant voltage or constant current mode.
2. Memory Power Controi: The LT1239 provides power
for the memory and includes automatic switch over

4-460

between the backup battery and the main 5V systen
power. When the 5V system supply is up and running i
is used to power the memory, the regulator prevent:
reverse current flow back into the backup batter)
Automatic switchover occurs when the 5V systen
supply drops below 4.85V and the regulator then pro
vides power to the memory from the backup cells
Memory power is uniterruptable.

LTl239

IPPLICATlons InFORmATion
Protection: Regulator 1 allows the use of current limiting resistors to prevent overcharging lithium-ion cells.
A low-battery detector shuts down regulator 2 and the
error amplifier to prevent over discharging the lithium
cells. An error amplifier is included to provide voltage
equalization for two series connected lithium-ion cells.
Ijusting Output Voltage
19u1ator 1 is an adjustable regulator. This allows the
Itput voltage to be set for various battery types and
Iitages. The output voltage is adjustable from 3.7SV up
20V. The regulator will servo its output voltage in order
maintain the adjust pin at 3. 7SV with respect to ground.
Ie output voltage is set with aresistor divider from output
ground as shown in Figure 1. The resistor values should
! chosen so that the current in the divider is approxiately S~. This means that the impedance from the
Ijust pin to ground should be approximately 7S0kn. The
lS current at the adjust pin is SOnA (typical) and will flow
to the adjust pin. The error in the output voltage, due to
eadjust pin bias current will be equal to the bias current
ultiplied by the value of R2 (IADJ x R2). This error is small
d is compensated for in the formulas shown in Figure 1.

Equalizing Lithium-Ion Cells
The error amplifier on the LT1239 is used to equalize the
cell voltages in a 2-cell lithium-ioll backup system. The
error amplifier is internally connected as a unity-gain
follower and is designed to sink or source about 3mA. The
bias current for the error amplifier will be approximately
3nA and will flow out of the pin. The output voltage of the
error amplifier can be set by connecting the input to a tap
point on the resistor divider used to set the output voltage
for regulator 1 as shown in Figure 2. The error amplifier
will then equalize the cell voltages by charging the cell with
the lowest output voltage. The output voltage of regulator
1 controls the total cell voltage and the error amplifier
forces the cell voltages to be equal. The error amplifier
output current will go to zero when the cell voltages are
equal and the total cell voltage is equal to the output
voltage of regulator 1.
6.BV
IN 1

rJ

OUT 1
R2 = 604k

REGULATOR 1
L...---r-_AD-IJ 3.7::

E/A (OUT)
69.Bk

3.4V
IN 1

I

r

OUTl
R2

REGULATOR 1

50nA

ADJ
51!A

Figure 2. Equalizing Lithium-Ion Cells

~

Rl

~

750k

":'

":'

VOUF 3.75 (1 + ~ ) + IADJ (R2)

R2 = (VOUT - 3.75V)
(3.75V!Rl) + IADJ
CHOOSE: Rl = 750k
IADJ =50nA

Figure 1. Adjusting Output Voltage

ample: To set the output voltage to 6.BV for a 2-cell
lium-ion system, use R1 =7S0k and IADJ =SOnA.
en:
R2

6.BV - 3.7SV

604k

= (3.7SV/7S0k) + SOnA =

l7lJD~

For battery voltages greater than the low-battery detection
threshold the error amplifier is active. For battery voltages
lower than the low-battery detection threshold the output
of the error amplifier is inactive. When the error amplifier
is active it can source or sink approximately 3mA. When
the error amplifier is inactive its output is a high impedance, as long as it is not forced above VIN2 or below
ground.
The error amplifier is powered from the same supply pin
as regulator 2. In most applications the backup batteries
and the output of regulator 1 will provide power to this
point. This means that the protection resistors (R4 in
Figure 5) in series with the output of regulator 2 will limit
the output current capability of the error amplifier in a
fault condition.

4-461

LT1239
APPLICATions InFoRmATion
Using the Current Monitor Furu:tion
The current monitor pin outputs acurrent proportional to
the output current of the regulator. Both regulator 1 and
regulator 2 have independent current monitor pins. The
current monitor function can be used to monitor charge in
the backup cells, to set up aconstant current output or to
adjust the current limit of the regulato.r. .The current
monitor pin should be tied to the output Pin If the current
monitor function is not used. This will minimize quiescent
current.
The current output of the current monitor pin can be
converted to avoltage by feeding the current monitor pin
output current through a resistor. The voltage ac~os~ the
resistor will be proportional to output current. ThiS signal
can be used to monitor the output current for either
regulator. Regulator 1output current is equal to the charge
current for the backup batteries plus the load current of
regulator 2. If regulator 1 output current is greater than
regulator 2 output current, the difference between the
currents is the charge current for the backup cells. If
regulator 2 output current is greater than regula~or 1
output current, the difference between the .current~ IS the
discharge current for the backup cells. By integrating the
difference between regulator 1 output current and regulator 2output current the total charge in the backup cells can
be determined.
Constant Current Charging

using regulator 1 and the circuit shown in Figure 3
In this circuit the voltage at the adjust pin is proportiona
to the output current. Regulator 1 will servo its output te
force 3.75V at the adjust pin. The output current will bE
scaled from the current monitor pin current by a ratio o'
220:1. Output current is equal to 220 x current monitor pir
current. The output current is set by choosing resistor R1
in the formula shown in Figure 3. Regulator 1 will sourCE
a constant current as long as the voltage at its input i!
greater than the battery voltage plus the dropout voltage 0
regulator 1. External power monitoring Circuitry can bE
used to shutdown regulator 1to terminate charge when (
low current sleep mode is desired.
SeHing Current Limit Using the Current Monitor Pin
With the addition of some simple external circuitry thE
current monitor pin can be used to control the outpu
short-circuit current of the regulator. As shown in FigUrE
4, the current monitor pin can be tied to ground througt
a resistor to generate a voltage proportional to outpu
current. When the voltage across R3 is equal to approxi·
mately 0.6V (one VB E) 01 will turn on and pull down on ~hE
shutdown pin of the regulator. 01 effectively steals dnvE
current from the regulator to limit the output current. C1
is needed to roll off the gain of 01. Current limit can be se
using the formula shown in Figure 4. This circuit. can bE
used with either regulator. The shutdown function car
also be used. An open-collector gate connected in paralle
with 01 can shut down the regulator.

NiCd backup batteries are normally charged with a constant current trickle charge. This can be accomplished
7-24V

MAIN
BATTERIES

NiCd
BACKUf
BATTER

NiCd
BACKUP
BATTERY

R3 = 0.6V x 220
IliM
VSHDNl
<0.25V
>2.SV
NC

ICHARGE
OFF
ON
ON

Rl = 3.75V x 220
ICHARGE

Figure 3. Constant Current Charging

4-462

Figure 4. Reducing Current Limit

Using the Comparator
The comparator in the LT1239 is intended to be use~ as ar
automatic switch over circuit between the main 5\

LTl239
APPLICATions InFoRmATion
system power and the backup batteries. The comparator
output will be driven high if the output of the 5V system
supply is greater than the 4.85V output of regulator 2.
Regulator 2will act as adiode to prevent current flow from
the 5V system supply back into the backup battery. Current flow into the output of regulator 2, with the output
pulled up to 5V, will be limited to approximately 6J.tA and
will flow to ground. If the main 5V system supply drops
below the 4.85V output of regulator 2 the comparator will
switch off and regulator 2 will provide power to the
memory. The comparator combined with regulator 2 and
the batteries provide an uninterruptable power source to
the memory and power monitoring circuitry.

Choosing Current Limiting Resistors
Due to UL safety considerations, circuits used to charge
lithium-ion batteries must have external resistors (passive
components) to limitthe available charge current in the
event of afailure in the charging circuit. The LT1239 allows
these resistors to be placed in series with the output
transistor of the regulator 1 as shown in Figure 5. The
current limiting resistor (R4) will be in series with the main
charge current path but will be inside the feedback loop of
regulator 1. Because the resistors are inside the feedback
loop they will not affect output voltage regulation in
normal operating conditions. The resistors should be
selected so that they limit the charge current below the
maximum level specified by the battery manufacturer. For
atypicaI3.4V, 50mA rechargeable backup cell (Panasonic
VL2330) the maximum charge current is specified at
300mA. Most users will choose to limit the current well
tlelowthe maximum charge current. It is importantto note
that these resistors can also limit the charge current
:luring normal operation. Since the charge current for a
typical lithium-ion button cell is normally less than 20mA
limited by the internal impedance of the cells during ~
~onstant voltage charge, the current limiting resistors do
not significantly affect the charge times for the backup
~ells. The worst case would occur if the regulator failed as
1 short and the main battery is at its maximum charge
{oltage. The current limiting resistor (R4) must be chosen
to limit the current to less than the manufacturers maxiTlum charging current with the difference between the
Tlain battery voltage and the backup battery voltage dropped
lCroSS it.

.L7lJ!J~

For example with a main battery voltage of 24V max, a
backup battery voltage of 6.8V and a maximum charge
current of 300mA, R4 must be greater than (24V -6.8V)/
300mA, R4 > 570.
R4 can also be used to limit the power dissipated by
regulator 1as shown in the following section. C1 is needed
for stability in circuits with protection resistors (R4).
The power dissipation in R4 during fault conditons can be
significant. it will be equal to:
{VINL - VBATTERy)2
R4
Power resistors with ratings greater than 0.25W orfusable
resistors may be required.

Thermal Considerations
The power dissipation of this device is made up of several
components.They are the power dissipation of each regu- •
lator, the comparator and the error amplifier. The largest
component will be due to the power in regulator 1, when
the charge current for the batteries is the highest and the
input voltage to regulator 1 is at the maximum. In most
systems this condition only occurs for ashort period after
the backup battery has been completely discharged. Both
regulators have thermal limiting circuitry which limits the
power in the regulator when the junction temperature
reaches about 100°C. The thermal limit temperature is set
low because the device is designed to work with batteries
specified to run at ambient temperatures below 60°C. The
power in regulator 1 can be limited with external resistors
placed in the feedback loop as shown in Figure 5. In
lithium-ion systems these resistors are required for safety
reasons.
The power in regulator 1 will be equal to:
[(VMAINBAmRY- VBACKUPBATTERY) x ICHGj- (ICHG x R4)
Note that for circuits with a current limiting resistor (R4)
the worst-case power point occurs when ICHG is equal to
the maximum charging currentl2.
Example: [(24V - 6.8V) x {71 mAl2)j- [(71 mAl2) x 240j
= 300mW
This is the only significant component of power dissipation
in the device and this condition will only occur when the

4-463

LT1239
APPLICATions InFoRmATion
backup batteries have been completely discharged. Once the
backup batteries are charged the power in regulator 1 drops
significantly. The power in regulator 2 when regulator 2 is
providing power to the memory will be equal to:
(VBACKUPBATTERY - 4.85V) x lOUT
lOUT is the current needed to power the memory and power
monitoring circuitry.
Example: (6.8V - 4.85V) x 30mA = 58.5mW
The power in the comparator when the comparator is providing power to the memory will be equal to:
(VSAT x lOUT)
lOUT is the current needed to power the memory and power
monitoring circuitry. Comparator Output Saturation Voltage
vs Output Current can be found in the Typical Performance
Characteristics.
Example: (VSAT x IlOAD) =(O.15V x 30mA) =4.5mW

Note that power for memory will be supplied by either
regulator 2 or the comparator. The power in the error
amplifier when the cells are unequalized will be equal to:
(VBACKUPBATTERy/2) x 3mA
Example: (6.8v/2) x 3mA = 10.2mW
This component goes to zero when the cell voltages are
equalized.
The thermal resistance of the LT1239 is 120°C/W when
the device is mounted to a PC board with at least one
ground or power plane. The junction temperature rise will
be equal to the total power in the device multiplied by
120°C/W or (PTOTAl x 120°C/W). For 300mW dissipation
the junction temperature rise will be (300mW x 120°C/W)
= 36°C. Given that the thermal limit temperature is approximately 100°C, this allows for a maximum ambient
temperature of roughly 60°C before the device thermal
limits. This temperature is near the maximum ambient
allowed for most battery types.

3.4V Li-Ion
CELL

3.4V Li-Ion
CELL

'THIS RESISTOR IS REQUIRED
BY SOME SAFETY AGENCIES.

Figure 5. Adding a Protection Resistor for lithium-Ion Charger

4-464

Lm"·,,,

LT1239
TYPICAL APPLICATions
NiCd Backup System with 20mA Charge Current

NiCd Backup System with 5mA Trickle Charge

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'ART NUMBER

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L7W!J~

COMMENTS

L7~J1JfJjB Microprocessor-co~;~:~!

Battery Management System

FEATURES

DESCRIPTiOn

• Fast Charge Nickel-Cadmium, Nickel-Metal-Hydride,
Lithium Ion or Lead-Acid Batteries under J.IP Control
• Flexible Current Regulation:
- Programmable 111 kHz PWM Current Regulator
with Built-In PFET Driver
- PFET Current Gating for Use with External Current
Regulator or Current Limited Transformer
• Discharge Mode
• Measures Battery Voltage, Battery Temperature and
Ambient Temperature with Internal 1O-Bit ADC
• Battery Voltage, Temperature and Charge Time
Fault Protection
• Built-In Voltage Regulator and Programmable
Battery Attenuator
• Easy-to-Use 3- or 4-Wire SerialllP Interface
• Accurate Gas Gauge Function
• Wide Supply Range: VDD = 4.5V to 16V
• Can Charge Batteries with Voltages Greater Than VDD
• Can Charge Batteries from Charging Supplies Greater
Than VDD
• Digital Input Pins Are High Impedance in
Shutdown Mode

The LTC®1325 provides the core of a flexible, cost-effective solution for an integrated battery management system. The monolithic CMOS chip controls the fast charging
of nickel-cadmium, nickel-metal-hydride, lead-acid or
lithium batteries under microprocessor control. The device features a programmable 111 kHz PWM constant
current source controller with built-in FET driver, 10-bit
ADC, internal voltage regulator, discharge-before-charge
controller, programmable battery voltage attenuator and
an easy-to-use serial interface.

APPLICATions
• System Integrated Battery Charger

TYPICAL APPLICATiOn

ff, LTC and LT are registered trademarks of Linear Technology Corporation.

Battery Charger for up to 8 HiCd or NiMH Cells

MPU

(•.g.8051)
p1.4!-+--"""':'

p1.31-+----""
p1.21-+------>:.

4-466

The chip may operate in one of five modes: power shutdown, idle, discharge, charge or gas gauge. In power
shutdown the supply current drops to 30J.IA and in the idle
mode, an ADC reading may be made without any switching
noise affecting the accuracy of the measurement. In the
discharge mode, the battery is discharged by an external
transistor while the battery is being monitored by the
LTC1325 for fault conditions. The charge mode is terminated by the !1P while monitoring any combination of
battery voltage and temperature, ambient temperature
and charge time. The LTC1325 also monitors the battery
for fault conditions before and during charging. In the gas
gauge mode the LTC1325 allows the total charge leaving
the battery to be calculated.

Voo
4.5VTO 16V

LTC 1325
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

[Notes 1, 2)

to GND ............................................................. 17V
11.11 Other Pins ................................ -O.3V to Voo + O.3V
Operating Temperature Range ..................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER PART
NUMBER

TOP VIEW

VOO

LTC1325CN
LTC1325CSW
ClK
lTF
MCV

7

NPACKAGE
SW PACKAGE
18-lEAD PDlP 18-LEAD PLASTIC SO WIDE
TJMAX • 125°C, OJA = 75°C/W (N)
TJMAX • 125°C, OJA .100°C/W (SW)
Consult factory for Industrial and Military grade parts,

ELEaRICAL CHARAaERISTICS
~YMBOL

DD
PD
IREG
-DREG
-'REG
rCREG
IOAC

PARAMETER
VDD Supply Voltage
VDD Supply Current
VDD Supply Current
Regulator Output Voltage
Regulator Load Regulation
Regulator Line Regulation
Regulator Output Tempco
DAC Output Voltage

IHYST

Fault Comparator Hysteresis

los

Fault Comparator Offset

IBATR
IBATP
IEDV
ILTF' VMCV
IHTF
IGG
10SlGGI
IF
'OLBATD

VBAT for BATR = 1
VBAT for BATP =1
Internal EDV Voltage
LTF, MCV Voltage Range
HTF Voltage Range
Gas Gauge Gain
Gas Gauge Offset
Internal Filter Resistor
Battery Divider Tolerance
Input Low Voltage
Input High Voltage
Low Level Input Current
High Level Input Current

IDD

'Il
'IH
Il
IH

L7lJ!J~

Voo =12V ±5%, TA =25°C, unless otherwise noted.

CONDITIONS
All TIL Inputs = OV or 5V, No Load on REG
Power-Down Mode, All TIL Inputs = OV or 5V
No Load
Sourcing Only, IREG = OmA to 2mA
No Load, Voo = 4.5V to 16V
No Load, O°C < TA < 70°C
VRI = 1, VRO = 1, 100% Duty Ratio, ICHRG = I (Note 7)
VRI = 1, VRO = 0,100% Duty Ratio, ICHRG = 1/3
VRI = 0, VRO = 1, 100% Duty Ratio, ICHRG = 1/5
VRI = 0, VRO = 0,100% Duty Ratio, ICHRG = 1/10
VHTF = IV, VEDV = 0.9V, VBATR = 100mV
VMCV = VLTF = 2V
VHTF = IV, VEDV = 0.9V, VBATR = 100mV
VMcv = VLTF =2V

•
•
•
•

MIN
4.5

3.047

140
48
30
16

TYP
1200
30
3.072
-1
-60
50
160
55
34
18
±20
±10
±50

MAX
16
2000
50
3.097
-5
-100
180
62
38
21

100

•
•

VDD-1.8
860
1.6
0.5

•
•
•
•

•

945
2.8
1.3

-4
±1
1000

-OAV < VSENSE < OV
-OAV < VSENSE < OV (Note 6)
All Division Ratios
CLK, CS, DIN
CLK, CS, DIN
VClK, Vcs or VDlN =OV
VClK, Vcs or VDlN =5V

900

-2
0.8
-2.5
-2.5

~
~
V
mVlmA

IlVN
ppm/oC
mV
mV
mV
mV
mV
mV
mV
mV
V
mV
V
V
LSB
0

2
1.3
1.7

UNITS
V

2.4
2.5
2.5

%
V
V
~
~

4-467

•

LTC 1325
ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

Output low Voltage
VOL
Output High Voltage
VOH
Hi-Z Output leakage
loz
DIS or PGATE Output High
VOHFET
DIS or PGATE Output low
VOlFET
Delay Time, ClK.j, to DOUT Valid
tdoO
Delay Time, cst to DOUT Hi-Z
tdis
Delay Time, ClK.j, to DOUT Enabled
ten
Time DOUT Remains Valid After ClK.j,
thOO
DOUT Rise Time
trOOUT
DOUT Fall Time
t!DOUT
Serial 110 Clock Frequency
fClK
PGATE Rise Time
trPGATE
PGATE Fall Ti me
tfPGATE
Internal Oscillator Frequency
fosc
AID Converter
Offset Error
Linearity Error
Full-Scale Error
On-Channel leakage
Off-Channel leakage

VDD = 12V ±5%, TA = 25°C, unless otherwise noted.

CONDITIONS

MIN

DOUT' lOUT = 1.6mA
DOUT, lOUT = -1.6mA
Vcs = SV
Voo = 4.SV to 16V
Voo = 4.SV to 16V
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
ClK Pin
CLOAO = lS00pF
CLOAO = lS00pF
Charge Mode, Fail-Safes Disabled

•
•
•
•
•
•
•
•
•
•
•
•
•
•

VIN Channel (Note 3)
VIN Channel (Notes 3, 4)
VIN Channel (Note 3)
VIN Channel ON Only (Notes 3, 5)
VIN Channel OFF (Notes 3, S)

•
•
•
•
•

TYP

MAX
0.4

UNITS
V
V

±10

!lA

2.4

V
V
ns
ns
ns
ns
ns
ns
kHz
ns
ns
kHz

VOO -O.OS
O.OS
6S0
S10
400
30

2S

90

111

2S0
100
SOO
lS0
150
130
±2
±O.S
±1
±10
±10

lSB
lSB
lSB

MAX

UNITS
ns

!lA
!lA

REcommEnDED CHARACTERISTICS
SYMBOL
thO I
tdsuCS
tdsuOI
tWHClK
tWlClK
tWHCS
tWlCS

PARAMETER
Hold Time, DIN After ClK!
Setup Time, CS Before First ClK!
Setup Time, DIN Stable Before First ClK!
ClK High Time
ClK low Time
CS High Time Between Data Transfers
CS low Time During Data Transfer

CONDITIONS

MSBF = 1
MSBF = 0

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to the GND pin.
Nole 3: VREG within specified min and max limits, ClK (Pin 5) = SOOkHz,
unless otherwise stated. ADC clock is the serial ClK.

4-468

MIN
150
1
400
0.8
1
1
43
52

TYP

~

ns
~
~

~

ClK Cycles
ClK Cycles

Nole 4: Linearity error is specified between the actual end points of the
AID transfer curve.
Nole 5: Channel leakage is measured after channel selection.
Nole 6: Gas gauge offset excludes AID offset error.
Nole 7: I = VOAc(Duty Ratio)/RsENSE, where VOAC is the DAC output
voltage with control bits VRl = VRO = 1, duty ratio = 1 and RSENSE is
determined by the user.

LTC 1325
rYPICAL PERFORmAnCE CHARACTERISTICS
Regulator Output Voltage vs
Load Current
3.082

3.077
~

3.076

TA = 27'C

........

~
::;
~
:;

5

3.073

>..

"

":>

........

..........

~ 3.080

~
~

3.077

~ 3.076

r-.... ........
i"'-

.0

~ 3.071

§
ffi
a:::

o

VDD = 12V

::>

:>

3.070

VDD=16V...,,;::; ~

3.079

§; 3.078
t:;

VDD = 4.5V

;;: 3.072

3.075

I~

3.074
3.073

0.5 1.0 1.5 2.0 2.5 3.0 3.5
LOAD CURRFNT (mA)

o

4.0

VR1 = 1, VRO = 1

I

I

r

100

I

a:

gj BO

tR1

10

20

20

11
~ 10

60

VBAT FOR BATP= HIGH, VDD =12V- -

:2 0.3

0.2

o

10

20

30 40 50 60
TEMPERATURE ('C)

~ -1.0

~ -1.5

a:

~ VCELL

~



'"'-'~

VCELL FOR BATR = HIGH

~ 0.1

o

0'
-0.5
z

f-

0.5

VDD = 12V

Gas Gauge Gain and Offset vs
Temperature

a:

'"a:
!;;:
0.4 I--VTBAT FOR HTF = HIGH, VHTF = 0.4V r-«
0-

r-

C
f::>

70

:x:

::>

'"

f--

I

VDD = 16V

VDD = 4.5V

'"ffl

a:

90

'"

:x:

0.7

o

20
30
40
50
TEMPERATURE ('C)

r-

--

15

;;: 10

VR1-0, VRO-O- 10

80

:x:

=

:3

:x: 0.6
f-

'"'-'~

a:
a:

VR1 -0, VRO-1=

o

30 40 50 60 70
TEMPERATURE ('C)

- --.l
-

z

o

10 20

........ ........

20

Fault Comparator Threshold vs
Temperature

VCELL FOR EDV = HIGH

o

'-'

40

1.0

a:

ilj

~

~ 0.9

'"ffl

o

Shutdown Current vs Temperature

VR1 -1, VRO-O_ ---c=

12

VDD = 12V

200

::>

20

O.B

~ t--

300

~

f-

10

400

25

;5 60

yR1 = 0'1 VRO = ~

o

.....-

500

90

0-

Fault Comparator Threshold vs
Temperature

:x:

80

>

1!VRO 0

J

VDD-4.5V- I--

f-"'

f-

BATTERY VOLTAGE (V)

:3

30 40 50 60 70
TEMPERATURE ('C)

VDD = 12V

;5 100

~R1 - O~ VRO - \
I
I

40

00-

>

~ 120

I

600

~

"VDD =4.5V

t:; 80

~ 60
!;i

o

,&3~

a:
a:
'-'

::>

VR1 =1, VRO=1- -

;:;

'-'

13

ilj

'[ 140

VDD = 12V, RSENSE = 1n,
L = 100!,H, P1i IRF95 1

;;: 120

..~

I

VDD= 16V- ~

700

::>

160

I

-=!,

f-

'"cc

180

140

900

;;: BOO

DAC Output Voltage vs
Temperature

160

§

~

a

...-::::

100

3.072

Charge Current vs Battery Voltage

.s

1000

~

I

3.081 f-IREG=O

:>

...........

~D=16V
~ ........ ........
3.075
........ ........
~i
3.074

u

Voo Supply Current vs
Temperature

Regulator Output Voltage vs
Temperature

I
o

10

20

"

"-

30 40 50 60
TEMPERATURE ('C)

"

70

80

4-469

•

LTC 1325
TYPICAL PERFORmAnCE CHARACTERISTICS
PGATE Rise Time vs
load Capacitance

PGATE Fall Time vs
load Capacitance

Differential Nonlinearity

1000

1200

900
1000

/,r
TAl = 2foc
V '/
TA=70
.,.,

~

c

:\!
>=
w

'"w0:

I-

«

'"

800

o

600
400

"-

200

o/
o

p
2

~~

y

~

V ~v
TA = O°C -

TA =

:\!

>=

TA=70°C/

=l 500

/. ?

300

o l""

o

6 8 10 12 14 16 18 20
LOAD CAPACITANCE (nF)

Discharge Rise and Fall Time
vs load Capacitance

4

z
z
z

-'
«

TA=O°C

>=
z

ffi -0.5 1---+--t-+--+-+--+-+--1
tt

~ III'"

2

0:

~

o

lh ~

200
100

4

LV

'"~

i:: 0.5 1--+--+-+-+--1-+--+--1
:::i

/ ~' /

~ 400

a:

A'' <: V ;;:

2rc1

600

~

-

p-

800

~ 700

Q

-1.0 "------L.----L_-'----"-----.l_-'-----"-----'
o 128 256 384 512 640 768 896 1024
CODE

6 8 10 12 14 16 18 20
LOAD CAPACITANCE (nF)

Minimum Charging Supply vs
Number of Cells

Integral Nonlinearity
1.0 ,--,.-----,-,-----,--,---,--,.--,

:%
:\!
>=

- TA= 70°C
12 - - - TA =
+-++-+-+-+-71
...... TA = O°C
RISE TIME

2rc

Voo = 12V
felK = 500kHz

V

"'i:: 0.5 1-+-I-+--1-+---+-+--I

'"~

10~+-++-+-+-~+-~~~

1/ ,

~...,

0:
~
z
z
o

v V"....' .. ".' ....

/,,~

,/'- ~••• "

:::i

"

'"

FALL TIME.....

/. ••••

-'
«
0:

_I""'".

~+-I---+---I-+--+-+---I

ill -0.5
ITA = 27°C. NiCd BATIERIES-+-+--t
VCELL = 1.4V NOMINAL

o """,JtI.:L~-L:'~---".'L-'"'..L'''-'----'----'-....L---1----.l
o

2

4

-1.0 '-------'---'-----'------'---'------'--'-----'

o

6 8 10 12 14 16 18 20
LOAD CAPACITANCE (nF)

NUMBER OF CELLS

Oscillator Frequency vs
Temperature
500

117

:[ 450

~

115

z

~

114

fE

113

g;;

112

o

~

U

gs

ClK 10 DOUT Enable Delay Time
vs Temperature

118

V

~116

.,.,V
V

111
110
109

400

~

350

g 300
~ 250
«

/

ill

200

>-

5150
o
~ 100

/

108
-40 -20

:\!
«

/'

/

':5

'-'
0
20
40
60
TEMPERATURE (0C)

80

100

768 896 1024

700

:g:

-

f-- f--

600

I

:\!
>=

--

>-

~

0
0

bOUT 60lNG HIGJ
500
400

1:::=== f:::===

;;;..-

I--: :::::
DOUT GOING LOW

:::i

;;

300

"

200

8

~

d 100

50

o

128 256 384 512 640
CODE

ClK to DOUT Valid Delay Time
vs Temperature

o

10

20

30 40
50 60
TEMPERATURE (0C)

70

80

1325G17

4-470

""

o

o

10

20

30 40 50 60
TEMPERATURE (0C)

70

80

LTC 1325

Pin FunCTions
REG (Pin 1): Internal Regulator Output. The regulator
provides a steady 3.072V to the internal analog Circuitry
and provides a temperature stable reference voltage for
generating MCV, HTF, lTF and thermistor bias voltages
with external resistors. Requires a4.7~ or greater bypass
capacitor to ground.
DOUT (Pin 2): TIL Data Output Signal for the Serial
Interface. DOUT and DIN may be tied together to form a
3-wire interface, or remain separated to form a 4-wire
interface. Data is transmitted on the falling edge of ClK
(Pin 5).
DIN (Pin 3): TIL Data Input Signal for the Serial Interface.
The data is latched into the chip on the rising edge of the
ClK (Pin 5).
CS (Pin 4): TIL Chip Select Signal for the Serial Interface.

SENSE (Pin 11): The Sense pin controls the switching of
the 111 kHz PWM constant current source in the charging
mode. The Sense pin is connected to an external sense
resistor RSENSE and the negative side of the battery. The
charging loop forces the average voltage at the Sense pin
to equal aprogrammable internal reference voltage VOAC.
The battery charging current is equal to VOAciRsENSE.
In the gas gauge mode the voltage across the Sense pin
is filtered by an RC network (RF and CF), amplified by
an inverting gain of four, then multiplexed to the ADC so
the average discharge current through the battery may
be measured and the total charge leaving the battery
calculated.
VIN (Pin 12): General Purpose ADC Input.

ClK (Pin 5): TIL Clock for the Serial Interface.

TAMB (Pin 13): Ambient Temperature Input. Connectto an
external thermistor network. Tie to REG if not used. May
be used as another general purpose ADC input.
•

lTF (Pin 6): Minimum Allowable Battery Temperature
Analog Input. lTF may be generated by a resistive divider
between REG (Pin 1) and ground.

TBAT (Pin 14): Battery Temperature Input. Connect to an
external NTC thermistor network. Tie to REG if not used.

MCV (Pin 7): Maximum Allowable Cell Voltage Analog
Input. MCV may be generated by a resistive divider between REG (Pin 1) and ground.
HTF (Pin 8): Maximum Allowable Battery Temperature
Analog Input. HTF may be generated by a resistive divider
between REG (Pin 1) and ground.
GND (Pin 9): Ground.
FilTER (Pin 10): The external filter capaCitor CF is connected to this pin. The filter capacitor is connected to the
Dutput of the internal resistive divider across the battery to
reduce the switching noise while charging. In the gas
gauge mode, CF along with an internal RF = 1k form a
lowpass filter to average the voltage across the sense
resistor.

VBAT (Pin 15): Battery Input. An internal voltage divider is
connected between the VBAT and Sense pins to normalize
all battery measurements to one cell voltage. The divider
is programmable to the following ratios: 1/1, 1/2, 1/3 . ..
1/15, 1/16. In shutdown and gas gauge modes the divider
is disconnected.
DIS (Pin 16): Active High Discharge Control Pin. Used
to turn on an external transistor which discharges the
battery.
PGATE (Pin 17): FET Driver Output. Swings from GND
to Voo.
Voo (Pin 18): Positive Supply Voltage. 4.5V < Voo < 16V.

4-471

LTC 1325
BLOCK DIAGRAm
VOO

18

I

DIGITAL INPUT CIRCUITS

5V
DIGITAL
REGULATOR

I
GND

9

~

2...;--CLK
CS
DIN
Dour

3.072V
ANALOG
REGULATOR

BATP, BATR, FMCV,
FEDV, FHTF, FLTF, lOUT
7
MODO TO MOD1, PS

CONTROL
LOGIC

4

-;-+

PS

3

SERIAL

1
ANALOG ANtDIGITAL Voo
ADC REFERENCE

16

_lOUT

6
8

FAULT
DETECT
CIRCUITRY

7

REG

DIS

LTF
HTF
MCV

....::....."0
..L

~

2tpS, MSBF

$OTODSl
SGUDIFF

12
13
14

,.....!2.

DlVOTO DlV3

~

4
1O-BIT
ND CONVERTER

ADC
MUX
r----TIMODO TO MODI VRO TO VR1, PS
GAS GAUGE

---"M~ ~
-l-

~~

~

~CHARGE

I....;

11
10

~
-::-

111kHz
OSCILLATOR

I~

{>E-

CHARGE LOOP
AND
GAS GAUGE

SENSE
FILTER
PGATE

DROTO DR3 3

r+TOUT

TIMEOUT LOGIC

1

_t

DUTY RATIO
GENERATOR

I-

LTCl32S'BD

TOO TO T02

TEST CIRCUITS
Load Circuit for tdDO. tr and tf

Load Circuit for tdis and ten
TEST POINT

5V t.lis WAVEFORM 2, len

3k
DOUTt-....."""'...-o-~

T

'--------'

4-472

100pF

~ldiS WAVEFORM 1
":"

LTC132S-rCIl2

LTC 1325
TEST CIRCUITS
Voltage Waveforms for DOUT Rise and Fall Times, Ir, I,

Voltage Waveforms for DOUT Delay Time, IdOO

CLK

\1...:O~8.:..V

- - - - - - - - - - 2.4V
_ _ _ _ _ _ _ _ __

-----I td00)i'-

{ [
_____

_ - - - - - - - O.4V
~tf

tr -------------.-

2.4V

]

DOUT
=======O.4V
LTC132S·TG03

On and 011 Channel Leakage

Voltage Waveforms for Idis

3.072V

2V

} - - - - I ON CHANNEL

~------------J
DOUT
WAVEFORM 1
(SEE NOTE 1)

-----------+--.

) OFF
CHANNELS
DOUT
WAVEFORM 2 - - - - - - - - - - - - - - - - '
(SEE NOTE 2)
NOTE: EXTERNAL CHANNELS ONLYTBAT, TAMS AND VIN

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS
SUCH THATTHE OUTPUT IS HIGH UNLESS DISABLED BY~.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS
SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY~.

Vollage Waveforms for len

~~~--------------,~----------------------DIN

~'-_ _ _ _ _""_ _ _-'

CLK

DOUT ________________________,~------~T~HR~E~E-~ST~A~TE~-------

L7lJn~

4-473

•

LTC 1325
TiminG DIAGRAm
MSB-FIRST DATA (MSBF = 1)

en
ClK "

'--____----'r---u

IliIuIlRI!!IIIIIII!!l!lil!lliI911Iiillll@:all!iI>lIIHillllilllfui@Mui!!I;III\!i!iJil:!IIiII!Ii1.

NUll
DOUT HI-Z
. : . : : . . : ; . - - - - - - - - - - - - - - - - - - - . D9

1_-- - - - - C O M M A N D W O R D - - - - - _ . I

BATP
D11DO

~-..!!!.i
~ ~

I-c--ADC DATA-I--sTATUSWORD-1

MSB-FIRST DATA (MSBF = 0)

en
ClK

[lnIUlIUlfLIUUU111lLfUUVLIlIUI

«
VR1

...Jr---u

' - -_ _-.lnL.._ _ _ _ _

lillIlIlli!iiimlhllillii:w::Cll!!lI!J::!iliiii1!i!!:iili:l:i:I!II:!+:liii!l!ii:ii!!lil!I;lji!:m!lli!liill!il

HI Z
NUll
BATP
FS
HI Z
DOUT':'::":;'--------------------.,~~~~

1_-- - - - - C O M M A N D W O R D - - - - - - . I

I.

ADCDATA

.1.

STATUSWORD-

~I

NOTE: THE TIMING DIAGRAM SHOWS TWO POSSIBLE COMMAND WORDS.
REFER TO FUNCTIONAL DESCRIPTION FOR INFORMATION ON HOW TO
CONSTRUCT THE COMMAND WORD

FunCTionAL DESCRIPTion
GENERAL DESCRIPTION

During normal operation, acommand word is shifted into
the chip via the serial interface, then an ADC measurement
is made and the 10-bit reading and chip status word are
shifted out. The command word configures the LTC1325
and forces it into one offive modes: power shutdown, idle,
discharge, charge or gas gauge mode.
In the power shutdown mode, the analog section is turned
off and the supply current drops to 301JA. The voltage
regulator, which provides power to the internal analog
circuitry and external bias networks, is shut down. The
voltage divider across the battery is disconnected and only
the voltage regulatorforthe serial interface logic is left on.
During the idle mode, the chip is fully powered but the
discharge, charge, and gas gauge circuits are off. The chip
may be placed in the idle mode momentarily while charging the battery, allowing an ADC measurementto be made
without any switching noise from the PWM current source
affecting the accuracy of the reading. The mode command
bits are picked off as they appear at DIN, allowing the
charging loop to turn off and settle while the remainder of
the command word is being shifted in.

4-474

During the discharge mode, the battery is discharged by
an external transistor and series resistor. The battery is
monitored for fault conditions.
In the charge mode, the f..lP monitors the battery's voltage,
temperature and ambient temperature via the 1O-bit ADC.
Termination methods such as -/!"vBAT, LlVBAT/LlTime,
LlTBAT, LlTBAT/Mime, Ll(T BAT - TA), maximum temperature, maximum voltage and maximum charge time maybe
accurately implemented in software. The LTC1325 also
monitors the battery for fault conditions.
In the gas gauge mode, the average voltage across the
sense resistor can be measured to determine the average
battery load current. The sense voltage is filtered by an RC
circuit, multiplied by an inverting gain of four, then converted by the ADC. The f..lP can then accumulate the ADC
measurements and do a time average to determine the
total charge leaving the battery. The RC circuit consists of
an internal 1k resistor RF and an external capacitor CF
connected to the Filter pin.

LTC 1325
FunCTionAL DESCRIPTiOn
COMMAND WORD

Bit 5: MSB-First/LSB-First (MSBF)

The command word is 22 bits long and contains all the
information needed to configure and control the chip. On
power-up all bits are cleared to logical "D."

The ADC data is programmed for MSB-first or LSB-first
sequence using the MSBF bit. See Serial I/O description
for details.
MSBF

DESCRIPTION
LSB-First Data Follows MSB-First Data
MSB-First Data Only

a
9

10

11

12

13

14

15

16

I~I~I~I~INI~I~IRI
17

18

19

20

21

22

IFSCLR I TOO I T01 I T02 I VRO I VR1 IlTC1325.m1
Figure 1. Command Word

Bit 1: Start Bit (Start)
The first "logical one" clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer and all leading zeros which precede this logical
one will be ignored. After the start bit is received, the
remaining bits of the command word will be clocked in.
Bits 2 and 3: Mode Select (MODO and MOD1)
The two mode bits determine which offour modesthe chip
will be in: idle, discharge, charge or gas gauge.
MOD1

MODO

a
a

a

1
1

a

1
1

DESCRIPTION
Idle
Discharge
Charge
Gas Gauge

Bit 4: Single-Ended Differential Conversion (SGL/DlFF)
SGUDIFF determines whether the ADC makes a single~nded measurement with respect to ground or a differential measurement with respect to the Sense pin.
SGLJDIFF

a

DESCRIPTION
Single-Ended ADC Conversion
Differential ADC Conversion (with respect to Sense)

.L7lJ!J~

Bits 6 to 8: ADC Data Input Select (DSO to DS2)
DS2, DS1 and DSD select which circuit is connected to the
ADC input. Do not use unlisted combinations.
DS2

DS1

DSO

a
a
a
a

a
a

a

1
1

a

1

a

a

1
1

DESCRIPTION
Gas Gauge Output
Battery Temperature Pin, TBAT
AmbientTemperature Pin, TAMB
Battery Divider Output Voltage, VCELL
VIN Pin

Bits 9 to 12: Battery Divider Ratio Select (DiVO to DlV3)
DIV3, DIV2, DIV1 and DIVD select the division ratio forthe
voltage divider across the battery.
DIV3

OlV2

DIV1

DlVO

a
a
a
a
a
a
a
a

a
a
a
a

a
a

a

1
1

a

1
1
1
1

a
a

a

1
1
1
1
1
1
1
1

1
1
1

1
1

a

a
a
a
a

a
a

a

1
1

a

1
1
1
1

a
a

a

1
1

a

1
1
1
1
1

DESCRIPTION
(VBAT - VSENSE)/1
(VBAT - VSENSE)/2
(VBAT - VSENSE)/3
(VBAT - VSENSE)/4
(VBAT - VSENSE)/5
(VBAT - VSENSE)/6
(VBAT - VSENSE)17
(VBAT - VSENSE)/8
(VBAT - VSENSE)/9
(VBAT - VSENSE)/1 a
(VBAT - VSENSE)/11
(VBAT - VSENSE)/12
(VBAT - VSENSE)/13
(VBAT- VSENSE)/14
(VBAT - VSENSE)/15
(VBAT - VSENSE)/16

4-475

LTC 1325
FunCTionAL DESCRIPTiOn
Bit 13: Power Shutdown (PS)
PS selects between the normal operating mode, or the
shutdown mode.
PS

DESCRIPTION
Normal Operation
Shutdown All Circu.its Except Digital Inputs

o

Bits 14 to 16: Duty Ratio Select (ORO to DR2)
OR2, OR1 and ORO select the duty cycle of the charging
loop operation (not 111 kHz PWM duty cycle). The last
three selections place the chip into atest mode and should
not be used.
DR2
0
0
0
0
1
1
1
1

DR1
0
0
1
1
0
0
1
1

ORO
0
1
0
1
0
1
0
1

DESCRIPTION
1/16
1/8
1/4
1/2
1
Test Mode 1
Test Mode 2
Test Mode 3

Bits 21 and 22: Charging loop Reference Voltage
Select (VRO and VR1)
VR1 and VRO select the desired reference voltage VCHRG
for the charging loop. The charging loop will force the
average voltage at the Sense pin to be equal to VOAC. The
average charging current is VOAclRsENSE (see Figure 4).
VR1
0
0
1
1

VRO
0
1
0
1

VOAC (mV)
18
34

55
160

STATUS WORD
The status word is 8 bits long and contains the status of
the internal fail-safe circuits.
1234567

[~[~[~~[~[~[~[~[ffi[
lTCl325-F02

Figure 2. Status Word

Bit 17: Fail-Safe latch Clear (FSClR)

Bit 1: Battery Present (BATP)

When FSCLR bit is setto one, the internal fail-safe timer is
reset to 0, and the fail-safe latches are reset. FSCLR is
automatically reset to 0 when CS goes high.

The BATP bit =1 indicates the presence of the battery. The
bit is set to 1 when the voltage at the VBAT pin falls below
(Voo -1.8V). BATP =0 when the battery is removed and
VBAT is pulled high by RTRK (see Figure 3).

FSCLR

DESCRIPTION
No Action
Reset Fail-Safe Timer and latches

o
1

BATP

o

Bits 18 to 20: Timeout Period Select (TOO to T02)
T02, T01 and TOO select the desired fail-safe timeout
period,toUT. On power-up, the defaulttimeout is 5minutes.
T02
0
0
0
0
1
1
1
1

T01
0
0
1
1
0
0
1
1

4-476

TOO
0
1
0
1
0
1
0
1

TIMEOUT (MINUTES)

5
10
20
40
80
160
320
Indefinite (No Timeout)

CONDITIONS
(Voo -1.8) < VBAT < Voo
VBAT < (Voo -1.8)

Bit 2: Battery Reversed (BATR) or Shorted
The BATR bit indicates when the battery is connected
backwards or shorted. The bit is set when the battery cell
voltage at the output of the battery divider VCELL is below
100mV.
BATR

o

CONDITIONS
VCELL> 100mV
VCELL < 100mV

LTC 1325
FunCTionAL DESCRIPTiOn
~it

3: Maximum Cell Voltage (FMCV)

rhe MCV bit indicates when the battery cell voltage has
lxceeded the preset limit. The bit is set when VCELL is
lreater than the voltage at the MCV pin.
FMCV

o

CONDITIONS
VCELL < VMCV
VCELL > VMCV

3it 4: End Discharge Voltage (FEDV)
rhe EDV bit indicates when the battery cell voltage has
jropped below an internally preset limit. The bit is set
IIIhen the battery cell voltage at the output of the voltage
jivider VCELL is less than 900mV.
FEDV

o

CONDITIONS
VCELL > 900mV
VCELL < 900mV

TOUT

o
1

CONDITIONS
No Timeout Has Occurred
Timeout Has Occurred

Bit 8: Fail-Safe Occurred (FS)
The FS bit indicates that one of the fault detection circuits
halted the discharging or charging cycle. The bit is set
when an EDV, LTF, HTF, or tOUT fault occurs during
discharge. During charging, the bit is set when a MCV,
LTF, HTF, or tOUT fault occurs. The bit is reset by the
command word bit FSCLR.
FS

o

CONDITIONS
No Fail-Safe Has Occurred
Fail-Safe Has Occurred

DETAILED DESCRIPTION
Fault Conditions

3it 5: High Temperature Fault (FHTF)
rhe HTF bit indicates when the battery temperature is too
ligh. Using a negative TC thermistor, the bit is set when
he voltage at the TBAT pin is less than the voltage at the
HF pin.

The LTC1325 monitors the battery for fault conditions
before and during discharge and charge (see Figure 3).
They include: battery removed/present (BATP), battery
reversed/shorted (BATR), maximum cell voltage exceeded
VDD

FHTF

o

CONDITIONS
REG

TBAT > VHTF
BATP

lit 6: Low Temperature Fault (FLTF)
-he LTF bit indicates when the battery temperature is too
ow. Using anegative TC thermistor, the bit is set when the
roltage at the TBAT pin is greater than the voltage at the
_TF pin.
FlTF

CONDITIONS

RTRK
R1

VBAT

PROGRAMMABLE
BATIERY
DIVIDER

FMCV

R2

SENSE

REG

MCV

FEDV

o
BATR

lit 7: Timeout (tOUT)
-he tOUT bit indicates that the battery charging time has
ixceeded the preset limit. The bit is set when the internal
imer exceeds the limit set by the command bits TOO, T01
lnd T02.

L7lJ!J~

FHTF

HTF

FLTF

LTF

R4
":'"

LTC1325'F03

Figure 3. Fail-Safe or Faull Detection Circuitry

4-477

•

LTC 1325
FunCTionAL DESCRIPTiOn
(MCV), minimum cell voltage exceeded (EDV), high temperature limit exceeded (HTF), low temperature limit exceeded (LTF) and time limit exceeded (tOUT). When afault
condition occurs, the discharge and charge loops are
disabled or prevented from turning on and the fail-safe bit
(FS) is set. The chip is reset by shifting in anew command
word with the fail-safe clear FSCLR bit set. The 8-bit status
word contains the state of each fault condition.

The chip enters the discharge mode when the proper
mode command bits are set and the power shutdown
command bit is clear. If a fault condition does not exist,
then the DIS pin is pulled up to Voo by the internal driver.
The DIS voltage is used to turn on an external transistor
which discharges the battery through an external series
resistor RDis.

Power Shutdown Mode

Discharging will continue until a new command word is
input to change the mode or a fault condition occurs.

Command: MOD1 = X, MODO = X, PS = 1

Charge Mode

Status:

Command: MOD1 = 1, MODO = 0, PS =

BATP = X, BATR = X, FMCV = X, FEDV = X,
FHTF = X, FLTF = X, tOUT = X

In the power shutdown mode, the analog section is turned
off and the supply current drops to 301lA. The voltage
regulator, which provides power to the internal analog
Circuitry and external bias networks, is shut down. The
voltage divider across the battery is disconnected and the
only circuit left on is the voltage regulator for the serial
interface logic.

Idle Mode
Command: MOD1 = 0, MODO = 0, PS = 0
Status:

BATP = X, BATR = X, FMCV = X, FEDV = X,
FHTF = X, FLTF = X, tOUT = X

The chip enters the idle mode when the proper mode
command bits are set and the power shutdown command
bit is cleared. During the idle mode, the chip is fully
powered, butthe discharge, charge and gas gauge circuits
are off. The chip may be placed in the idle mode momentarily while charging the battery, allowing an ADC measurementto be made without any switching noise from the
PWM current source affecting the accuracy of the reading.
The mode command bits are picked off as they appear at
DIN, so that while the rest of the command word is being
shifted in, the charging loop has time to settle before an
ADC measurement is made.

Discharge Mode
Command: MOD1 = 0, MODO = 1, PS = 0
Status:

4-478

BATP = 1, BATR = 0, FMCV = X, FEDV = 0,
FHTF = 0, FLTF = 0, tOUT = 0

Status:

°

BATP = 1, BATR = 0, FMCV = 0, FEDV = X,
FHTF = 0, FLTF = 0, tOUT = 0

The chip enters the charge mode when the proper mode
command bits are set and the power shutdown command
bit is clear. If afault condition does not existthen charging
can begin. Charging will continue until a new command
word is input to change the mode or a fault condition
occurs.
The charge current may be regulated by a programmable
111 kHz PWM buck current regulator, or by using the PFET
to gate an external current regulator or current limited
transformer.

111kHz PWM Controller
The block diagram of the charging loop connected as a
PWM buck current regulator is shown in Figure 4. The
PWM may operate in either continuous or discontinuous
mode. The loop forces the average voltage across the
sense resistorto be equal tothe voltage atthe output ofthe
DAC, so that the charging current becomes VOAclRsENSE.
With switch S2 on and the others off, amplifier A1 along
with C1, R1 and R2 are configured as an integrator with
16kHz bandwidth. The output of the integrator is the
average difference between the voltage across the sense
resistor and the DAC output voltage.
The rising edge ofthe oscillator waveform triggers the one
shot which sets the flip-flop output high. This turns on the
external PFET P1 by pulling its gate low via the FET driver.
With P1 on, the current through the inductor L1 starts to

LTC 1325
:unCTlonAL DESCRIPTiOn
Voo

4.5VTO 16V

GG VR1 VRD DACVOLTAGE
18mV
0
0
0
0
1
34mV
0
0
1
0
55mV
0
1
1
160mV
1
X
X
OmV
VRO, VR1

GG
CHIP
(GAS GAUGE) BOUNDARY

LTCl32S'F04

Figure 4. Charging Loop Block Diagram

ise as does the voltage across the sense resistor. When
he voltage across the sense resistor is greater than the
lutput of the integrator, comparator A2 changes state.
·his resets the flip-flop and P1 is turned off, Catch diode
11 clamps the drain of P1 one diode drop below ground
vhen the inductor flies back and the current through the
lductor starts to drop. The voltage across the sense
esistor also drops and may reach zero and stay there until
he next clock cycle begins.
·he average charging current is set by the output of the
lAC (VoAd and the duty ratio generator. VOAC can be
lrogrammed to one of four values with the following
atios: 1, 1/3, 1/5 or 1/10. The duty ratio can be set to
116, 1/8, 1/4, 1/2 or 1. When the duty ratio is 1, the duty
atio generator output is always low and the charge loop
'perates continuously (see Figure 4). At other duty ratio
ettings, the duty generator output is a square wave with
period of 42 seconds. The time for which the generator
,utput is low varies with the duty ratio setting. For ex-

L7lJ!J~

ample, if a duty ratio of 1/2 is programmed, the generator
output is low only for 4212 = 21 seconds. Since the loop
operates for only 21 out of every 42 seconds, the average
charging current is halved. In general, the average charging current is:
ICHRG = VOAc(Duty Ratio)/RsENSE
Gated PFET Controller
When using an external current regulator or current limited wall pack, simply remove the inductor L1 and catch
diode D1. Set the DAC control bits VR1 = 1 and VRO = 1,
and select the desired duty ratio. By insuring that the
voltage at the Sense pin is never greater than 140mV, the
output of the integrator A1 will saturate high and the
comparator A2 will never trip and turn the loop off. This
can be achieved by removing the sense resistor and
grounding the Sense pin or if the gas gauge is to be used,
selecting RSENSE so that RSENSE/lcHRG < 140mV.

4-479

•

LTC 1325
FunCTlonRl DESCRIPTiOn
Gas Gauge Mode
Command:
Status:

=1, MODO =1, PS =a
BATP =X, BATR =X, FMCV =X, FEDV =X,
FHTF =X, FLTF =X, tOUT =X
MOD1

In the gas gauge mode, the average voltage across the
sense resistor can be measured to determine the average
battery load current. The output ofthe DAC is setto ground
and switches S1, S3 and S4 are closed. A1 is configured
as an inverting amplifier with R1 and R2 setting the gain
to -4. The voltage across the sense resistor is filtered by
an RC circuit (RF, CF) amplified by A1, then converted by
the ADC.
The microprocessor can then accumulate the ADC measurements and do a time average to determine the total
charge leaving the battery. The Sense pin voltage should
not be more negative than -450mV to ensure linearity.
The RFCF circuit consists of an internal 1k resistor and an
external capacitor connected to the Filter pin. RFCF should
be longer than the measurement interval. With the serial
clock running at 100kHz, it take 380JlS to shift in the
command word and shift out the ADC measurement and
status word.
Trickle Resistor
An external trickle resistor has several functions. First, it
provides a continuous trickle charge current for topping
offthe battery and countering the effects of self-discharge.
Second, it can be used to condition a deeply discharged
batteryforcharging. The LTC1325will not charge abattery
unless its cell voltage is above 100mV (BATR). Finally, the
resistor is required by the battery detect circuit to pull the
VBAT pin high when the battery is removed.

SERIAL INTERFACE
The LTC1325 communicates with microprocessors and
other external cirCUitry via a synchronous, half duplex,
4-wire serial interface. The clock CLK synchronizes the
data transfer with each bit being transmitted on the falling
edge and captured on the rising CLKedge in both transmitting and receiving systems. The LTC1325 first receives
input data and then transmits back the AID conversion
result and status word (half duplex). Because of the half

4-480

duplex operation, DIN and DOUT may be tied together
allowing transmission over just three wires: CS, CLK and
DATA (DIN/DoUT)'
Data transfer is initiated by afalling chip select CS signal.
After CS falls, the LTC1325 looks for astart bit on DIN. The
start bit is the first "logical one" clocked into the DIN input
after CS goes low. The LTC1325 will ignore all leading
zeros which precede this logical one. After the start bit is
received, the 21 other control bits are shifted into the DIN
pin to configure the LTC1325 and start aconversion. After
the last command bit, the DOUT pin remains in three-state
for one clock period before it is taken low for one null bit.
Following the null bit, the conversion results and the 8
status bits are shifted outon the DOUT pin. Atthe end of the
data exchange, CS should be brought high.
MSB-First/lSB-First (MSBF Control Bit)
The output data of the LTC1325 is programmed for MSBfirst or LSB-first sequence using the MSFB control bit.
When MSBF = 1, data will appear on DOUT in MSB-first
format. This is followed by the 8 status bits. Logical zeros
will be filled in indefinitely following the last data bit to
accommodate longer word lengths required by some
microprocessors. When MSBF = 0, LSB-first data will
follow the MSB-first data. Regardless of the state of
MSBF, the status bits are always shifted out in the same
order (see Figure 2).
Accommodating Microprocessors with Different Word
lengths
The LTC1325 will fill zeros indefinitely after the transmitted data until CS is brought high. At that time DOUT is
disabled (three-stated). This makes for easy interfacing
to MPU serial ports with different transfer increments
including 4 bits (e.g., C0P400) and 8 bits (e.g., SPI and
MICROWIREIPLUS™). Any word length can be accommodated by the correct positioning of the start bit in the
input word.
Operation with DIN and DOUl Tied Together
The LTC1325 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to
MICROWIREIPLUS is atrademark of National Semiconductor Corp.

LTC 1325
FunCTionAL DESCRIPTiOn
communicate with the microprocessor. Data is transmitted in both directions on a single wire. The processor pin
connected to this data line should be configurable as either
an input or an output. The lTC1325 will take control of the
data line and drive it low after the 23rd falling ClK edge
after the start bit is received. Therefore the processor port
must be switched to an input before this happens to avoid
a conflict.

Power-Up AHer Shutdown
When a control word with the PS bit set to one is written
to the lTC1325, it enters shutdown mode in which the Voo
supply current is reduced to 30~. In this mode the onchip 3V regulator and all circuits powered off it are shut
down. The only circuits that remain alive are DIN, CS and
ClK input buffers. To take the lTC1325 out from shutdown mode, a high to low edge must be applied to the CS
pin. Either DIN or ClK must be low when CS is low to
prevent afalse control word from being transmitted to the
lTC1325. The 3V output decays with a time constant of
300ms with CREG = 4.71Jf. The microprocessor should
wait three seconds before applying awake-up edge to the
CS pin to ensure proper power-up.

BL
=exp[~(.:!.T - ...!.)~
RTO
To ~

(2)

R _
(~-2To)
L -RTO ~+2To

(3)

~ = [T (~)~
In (BL)
To - T ~
Rro

(4)

ex

=...!.
(dRr )
Rr dT

(5)
(6)

(-~

1

dVDlV
1
--=V
DlV (To) - - + dT
2T02 To

(7)

where,
VOIV (T) is the output of the divider,

TEMPERATURE SENSING

VREG is the voltage at the REG pin (3.072V nominal),

NTC (Negative Temperature Coefficient) Thermistors

Rr is the thermistor resistance at some temperature T,

The simplest method to sense temperature (battery or
ambient) with an NTC thermistor is to use avoltage divider
powered by the REG pin. This divider consists of a load
resistor RL in series with a thermistor Rr as shown in
Figure 3. For a given thermistor, there is a value of RL
which makes VDlV (T) linear over a narrow but adequate
temperature range. The easiest method (Inflection Point
Method) to calculate RL is to set the second temperature
derivative ofthe divider output to O. The equations relevant
to this method are:

Rro is the thermistor resistance at some reference
temperature To,

f(T)
(1 )

~

is a constant dependent on thermistor material,

ex is the temperature coefficient (in %/0C) of Rr at
To,and
all temperatures are in OK (Le., roc + 273)
There are two assumptions in the derivation of the above
equations. Pis assumed to be constant and the temperature coefficient of RL is small compared to that of the
thermistor.
Most thermistor data sheets specify Rro, p, Rr/Rro ratios
for two temperatures, ex, and tolerances for ~ and Rro.
Given p, and Rro, it is easy to calculate RL from equation

4-481

LTC 1325
APPLICATions InFoRmATion
(3). Alternatively, ~ may be calculated from the RT/RTO
ratio using equation (4) or from a, using equation (6).
As a numerical example, consider the Panasonic
ERT-D2FHL103S thermistor which has the following characteristics:
1. RT (25°C) = RTO = 10k
2. a =-4.6%IOC at To =25°C
3. Ratio R251'R50 = 2.9
Using equation (4) and R251'R50 = 2.9, ~ = (323 x 298)ln
(2.9)/(298 - 323) = 4099k. Alternatively, using equation
(6) and a =-4.6%IOC, ~ =- (-0.046) (298)2 =4085k.
Both values of ~ are close to each other. Substituting
~ =4085k into equation (3) gives RL =10k [4085 - (2 x
298)]/[4085 +(2 x 298)] =7.45k. The nearest 1% resistor
value is 7.5k. Figure 5 shows a plot of VDlv(T) measured
at various temperatures for this thermistor with a7.5k RL.

,,

4.5

4.0

2:

3.5

~

3.0

~

2.5

w

!:;

....~
is

,,

,IDEAL

ACTUAi:"o

"-I'..

2.0
1.5

"-

~ 1.0
~ 0.5

~~

,,

o
-0.5
-60 -40

-20 0
20
40
TEMPERATURE (Oe)

60

80

T = [2.605 - VOlv(T)]/0.034. The straight line approximation is accurate to within 2°C over atemperature range of
5°C to 45°C, assuming 3% ~ and 10% RTO tolerances.
PTC (Positive Temperature Coefficient) Thermistors
Positive Temperature Coefficient (PTC) thermistors may
be used in battery chargers that do not require accurate
temperature measurements. The resistance vs temperature characteristics of PTC exhibits a sharp increase at a
selectable switch temperature Ts. This sharp change is
exploited in chargers which use TCO (Temperature Cutoff)
or dTCO (Difference between battery and ambient temperature). With TCO termination, avoltage divider consisting of aPTC and alow temperature coefficient load resistor
is connected between REG and GND with the top end ofthe
PTC at REG. The PTC is mounted on the battery to sense
its temperature. The divider output is tied to TBAT. When
the switch temperature is reached, the PTC resistance
increases sharply causing TBAT to fall below HTF. This
causes an HTF fault and charging is terminated. To implement dTCO termination, the load resistor can, in principle,
be replaced by a matching PTC and the divider now
responds to differences between battery and ambient
temperature. With both TCO and dTCO terminations, the
position of the battery temperature PTC can be swapped
with the load resistor or ambienttemperature PTC.ln both
cases, an LTF fault terminates charge when the trip pOint
is reached. Note that in practice, matched PTCs are not
readily available and for dTCO termination, NTC thermistors are recommended.

HARDWARE DESIGN PROCEDURE
Figure 5. ERT-D2FHL1038 Divider

There are two methods of calculating battery or ambient
temperature from ADC readings of the TBAT or TAMB
channels. The first method is to store the VOlv(T) vs T
curve as a lookup table. The second method is to use a
straight line approximation. The equation of this line may
be calculated from the slope dVDlvidT at To [see equation
(7)] and assuming that the line passes through the point
[To, VDlv(T 0)] on the curve. For the ERT-D2FHL1 03S, the
slope is minus 34mV/oC and the equation of the line is

4-482

This section discusses the considerations in selecting
each component of a simple battery charger (see Figures
3 and 4). Further applications assistance is provided in
Application Note 64, using the LTC1325 Battery Management IC.
1. RSENSE: There are three factors in selecting RSENSE:
a. LTC1325 VREF and Duty Ratio Settings
b. Sense Resistor Dissipation
c. ILOAO(RsENSE) < -450mV for Gas Gauge Linearity

LTC 1325
APPLICATions InFoRmATion
The LTC1325 has five duty ratio and fourVOAC settings
giving 20 possible charge rates (for a given value of
RSENSE) as shown in the following table. For any
combination of VOAC and duty ratio, the average
charging current is given by:
AVG ICHRG = VoAc(Duty Ratio}/RsENSE
NORMALIZED
VOAC

1
1

l(VRl =1, VRO -1)
1/3(VRl =1, VRO =0) 1/3
1/5(VRl =0, VRO =1) 1/5
1110(VRl =0, VRO =0) 1/10

1/2
1/2
1/6
1/10
1/20

DUTY RATIO
1/4
1/8 1/16
1/4
1/12
1/20
1/40

1/8
1/24
1/40
1/80

1/16
1/48
1/80
1/160

Note that the table entries give relative charge rates
assuming thatthe VR1 =1, VRO =1, duty ratio =1entry
is equivalentto a1Ccharge rate. Therefore, the charge
rate (in C-units) for other VR1, VRO, and duty ratio
settings may be read directly from the table. In general, the VR1 =1, VRO =1, duty ratio =1 entry can be
equivalent to any charge rate, say ktimes 1C. Then all
entries in the table should be multiplied by k. In
general, VOAC and duty ratio settings are changed by
the microprocessor to charge batteries of different
capacities or to alter charge rates when charging the
same battery in several stages. For best accuracy, VR1
and VRO should be set to 1 where possible.
The power dissipation of the sense resistor varies
between charge, discharge and gas gauge modes and
should be calculated for all three modes. Typically,
dissipation is higher in discharge and gas gauge
modes since batteries can deliver higher currents than
they can be charged with.
In gas gauge mode, the load current supplied by the
battery should not exceed 450mVlRsENSE for the gas
gauge to remain linear in response. RSENSE should be
low enough to ensure that ILOAO(RsENSE) does not
fall below ground by more than 1 diode drop.
2. Voo Supply: Voo should be at least 1.8V above the
maximum battery voltage to prevent aBATP =0 error
when the LTC1325 is in charge or discharge mode. If
this requirement cannot be met in a specific application, an external battery divider should be connected

between the VBAT and Sense pins and the internal
divider should be set to divide-by-1.
The minimum Voo supply must be greater than the
end-of-charge voltage VEC times the number of cells
(n) in the battery plus drops across the on-resistance
of the PFET, inductor (Vd, battery internal resistance
RINT and sense resistor RSENSE.
Minimum Voo should be the greater voltage of the
results from these two equations:
Min Voo = ICHRG [ROS(ON)(P1) + RSENSE +
n(RINT)] + n(VEC) + VL
or,
Min Voo = n(VEC} + 1.8V
Assuming VEC = 1.6V, the LTC1325 will charge up to
8cells with a16V supply. For ahigher number of cells, . .
an external level shifter and regulator are needed. . .
In some applications, there are other circuits attached
to the charging supply. When the charging supply
(Voc) is powered down or removed, the battery may
supply current to these circuits through the PFET body
diode. To prevent this, a blocking diode can be added
in series with Voc as shown in the circuit in the Typical
Application section.
3. Inductor L: To minimize losses, the inductor should
have low winding resistance. It should be able to
handle expected peak charging currents without saturation. If the inductor saturates, the charging current
is limited only by the total PFET ROS(ON), inductor
winding resistance, RSENSE and Voo source resistance. This fault current may be high enough to
damage the battery or cause the maximum power
ratings of the PFET, inductor or RSENSE to be exceeded.
4. Catch Diode D1: The catch diode should have a low
forward drop and fast reverse recovery time to minimize power dissipation. Total power loss is given by:
PdOl = VF(lF) + (VR)(f)(tRR)(IF')

4-483

LTC 1325
APPLICATions InFoRmATion
where,
IF = forward diode current,
IF' = forward diode current just prior to turn off,
VF = forward drop,
VR =reverse diode voltage (approximately equal to Voo),
f = PWM frequency (111 kHz), and
tRR = reverse recovery time
The power and maximum reverse voltage ratings of the
diode should be greater than Pd01 and Voo respectively.
The catch diode should also have fast turn-on times to
reduce the voltage glitch at its cathode when turning on.
Schottky diodes have fast switching times and low
forward drops and are recommended for D1.
5. Trickle Resistor RTRK: RTRK sets the desired trickle
current in the battery to compensate for self-discharge which is in the order 1%and 2% of capacity per
day for NiCd and NiMH batteries respectively. Trickle
charge rates are typically in the C/30 to C/50 range,
where Cis battery capacity.
ITRK = (Voo - VBAT)/RTRK
where VBAT is the voltage of a full charged battery.
Note that ITRK varies as the battery is being charged.
6. Thermistor RTand Load RL: The total resistance of the
thermistor network should be greater than 30k at the
high temperature extreme to minimize effects of load
regulation (see REG pin loading).
7. Fault Setting Resistors R1, R2, R3 and R4: The voltage
levels at the LTF, HTF and MCV pins are tapped from
a resistor divider powered by the REG pin. The voltage
levels are selected taking into account:
a. Manufacturer Recommended Temperature and
Voltage limits,
b. Loading on the REG Pin « 2mA)
c. Input Voltage Ranges of the LTF, HTF and MCV
Comparators:
1.6V < VLTF, VMCV < 2.8V and O.5V < VHTF < 1.3V

4-484

d. Thermistor Divider Temperature Curve
Typical temperature limits for both NiCd and NiMH
batteries are shown below.
BATTERY
TYPE
Standard
Quick
Fast or Rapid
Trickle

DISCHARGE TEMP
RANGE (OC)

CHARGE TEMP
RANGE (OC)

MIN
-20
-20
-20
-20

MIN
0
10
15
0

MAX
45 to 50
45 to 50
45 to 50
45 to 50

MAX
45 to 50
45 to 50
45 to 50
45 to 50

Note that the discharge limits are wider. than the
charge limits. To prolong battery life, manufacturers
generally recommend discharge temperatures that
are similar to the charge limits. For this reason, the
LTC1325 recognizes the same LTF and HTF limits in
both charge and discharge modes. MCV should be set
just above the charging voltage per cell given in
battery specifications. The voltage at the LTF and HTF
pins should be set to correspond to narrowest temperature range. These are typically 15°C and 45°C.
The corresponding voltages may be read from the
thermistor divider temperature curve such as that
shown in Figure 5. For this thermistor, it works out to
be about for 2.12V for LTF and for 1.13V for HTF. The
MCV may be conveniently tied to LTF since MCV is
typically2V.1f desired, external analog switches under
microprocessor control may be used to vary the LTF,
HTF and MCV voltages between modes or for different
charge rates. The values of R1, R2, R3 and R4 in Figure
3 can be calculated from the following equations:
R4 = VHTf(REIVREG)
R3 = VMcv(RE - R4)
R2 = VLTF(RE) - (R3 + R4)
R1 = RE - (R2 + R3 + R4)
where RE = R1 + R2 + R3 + R4 is chosen to minimize
loading on the REG pin. A minimum value of 30k is
recommended. NotethatVLTF is assumed to be greater
than VMCV. If this is not the case, VLTF and VMCV in the
above equations should be swapped. If the MCV and
LTF pins are shorted to the same pOint, R2 should be
set to O.

LTC 1325
APPLICATions InFoRmATion
8. REG Pin Loading: The 3.072V regulator has a load
regulation specification of -5mV/mA. Since the ADC
uses the same regulator as reference, it is desirable to
reduce loading effects on the REG pin especially over
temperature. Thermistors with RTO values of at least
10k at 25 a C are recommended. At 50 a C, the thermistor resistance could drop by afactor of 3 from its
value at 25 a C. RL is chosen as explained in the section
on Temperature Sensing. The temperature coefficient
of RL is not critical since the thermistor tempco
dominates the sensing circuit.
9. ROls: ROls is selected to limit the discharge current to
avalue within the battery discharge specifications and
must have a power rating above 10lS2 (Rols) where:
lOIS = VSAT/[RoIS + ROS(ON)(N1)]
10. PFET(P1) and NFET(N1): For operation of the charge
and discharge loops, IVGS I < Voo since the PGATE
and DIS pins swing between 0 and Voo· IVGS I «Voo
to minimize power dissipation. The power ratings of
P1 and N1 should be above ICHRG 2[ROS(ON)(P1)] and
10lS2 [ROS(ON)(N1)] respectively. VOS(MAX) should be
above Voo.
Charging from Supplies Above 16V

In many applications, the charging supply is greater than
the 16V maximum Voo rating ofthe LTC1325. The LTC1325
can easily be adapted to charge the batteries from a
charging supply VOG that is above 16V by adding three
external sub-circuits:
1. A regulator to drop VOG down to within the supply
range of the LTC1325.
2. A level shifter between the PGATE and the gate of the
PFET, P1, to ensure that P1 can be completely turned
off when PGATE rises to Voo.
3. Avoltage clamp on the VSAT pin to prevent RTRKfrom
pulling VSAT above Voo.
The Wide Voltage Battery Charger circuit in the Typical
Application section shows low cost implementations of all
three sub-circuits. C1 , R11 and D4 generate a15V Voo for
the LTC1325. D3, R12 and C2 form a level shifter. The
zener D3 is chosen to clamp the source gate voltage of the

PFETto within the maximum gate source voltage rating of
the latter. Finally, D2 clamps VSAT to 15V.
Charging Batteries with Voltages Above 16V

To charge a battery with a maximum (fully charged) voltage
of above 16V, the charging supply VOG must be above 16V.
Thus the charger will need the regulator, level shifter and
clamp mentioned in the previous section. In addition, an
external battery divider must be added to limit the voltage at
the VSAT pin to less than Voo. This is shown in the typical
application circuit, Wide Voltage Battery Charger. The resistors R9 and R1 0 are selected to divide the battery voltage by
the number of cells in the battery and the battery divider
internal to the LTC1325 is set to divide-by-1. The external
divider prevents VSATfrom ever rising to Voo and this causes
the BATP (Battery Present Flag) to be high regardless of
whether the battery is physically present or not. This does not
affect the other operations of the LTC1325.
SOFTWARE DESIGN

A general charging algorithm consists of the following
stages:
Discharge Before Charge
Fast Charge
Top Off Charge
Trickle Charge
Under some operating and storage conditions, NiCd and
NiMH batteries may not provide full capacity. In particular,
repeated shallow charge and discharge cycles cause the
"memory effect" in NiCd batteries. In order to restore full
capacity (battery conditioning), these batteries have to be
subjected to several deep discharge/charge cycles which
will be provided by repetitions of the above algorithm.
Figure 6 shows a simplified flowchart of a charging algorithm. In practice, this flowchart has to be augmented to
take into account the occurrence of fail-safes at any pOint
in the algorithm. For example, the battery temperature
could rise above HTF during discharging or charging.
General programming notes are as follows:
1. The start bit is always high.
2. The SG L/D IFF bit is generally set to low so that the ADC
makes conversions with respect to ground.

4-485

LTC 1325
APPLICATions InFoRmATion
3. The MSBF bit is set depending on whether the microprocessor clocks in serial data with MSB- or LSB-first.
4. The DSO to DS2 bits can be anything except when
entering idle mode or when requesting for ADC readings. In these cases, DSO to DS2 are set to select the
desired reading: TBAT, VCELL or TAMB·
5. The PS bit should always be 0 so that the LTC1325
does not go into shutdown mode.
6. The ORO to DR2 should not select any ofthe test modes.
It may assume different settings between Fast charge
and Top Off charge in orderto alter the charging current.
7. The FSCLR bit should be setto 1to clear any faults and
reset the timer when starting Discharge, Fast charge
or Top Off. The status bits that the LTC1325 returns

during the same 1/0 operation (that FSCLR is set to 1)
should be checked to determine if faults were indeed
cleared, i.e., discharging or charging has begun. This
is not shown in the simplified flowchart of Figure 6.
For commands other than the START commands,
FSCLR should be set to 0 so as not to reset the timer.
8. The TOO to T02 bits should all be set to 1 in discharge
mode to ensure discharge does not end prematurely
due to a timeout fault. During Fast charge or Top Off
charge, these bits are set to a value suitable for the
charge rate used. For example, if the charge rate is 1C,
the timeout period should be set to 80 minutes.
9. In charge mode, the CF capacitor filters the VCELL node
and sees a small ripple due to ripple at the Sense pin.
Prior to taking an ADC reading, the LTC1325 is put in

1..-.-----:;':< TERMINATE? ~-=---....J

Figure 6. Simple Charging Algorithm

4-486

LTC 1325
APPLICATions InFoRmATion
idle mode to minimize noise. The microprocessor
should either disregard readings or wait for a second
or so before taking areading. This is to allow VCELL to
decay to the correct cell voltage. The worst case time
constant is 150kn (CF)'
10. Priorto the first START command, the battery divider
setting may be incorrect so that CF may charge to a
voltage that causes EDV, BATR or MCV faults. The
worst case time constant is as in (9). The microprocessor should check faults during the transmission of
aSTART command and resend the START command
again when CF has been given enough time to charge
up to the correct value.

wiper on a potentiometer between these two. Table 1
illustrates acomplete 6-byte exchange. Note that the first
byte is padded with zeroes to align the AID data and status
with byte boundaries.
SPCR = (SPIE =0, SPE =1, DWOM =0, MSTR =1,
CPOL =0, CPHA =0, SPR1 =0, SPRO =1)
DDRD = (BIT7 =0, BIT6 =0, DDR5 =1, DDR4 =1,
DDR3 =1, DDR2 =0, DDR1 =0, DDRO =1)
Table 1. 6-Byte Exchange SPI Communication with LTC1325
5V

68HC11

ss

MICROPROCESSOR INTERFACES
The LTC1325 can interface directly to eithersynchronous,
serial or parallel 1/0 ports of most popular microprocessors. With a parallel port, 3 or 4 1/0 lines can be programmed to form a serial link to the LTC1325.

Motorola SPI (68HC11)
The 68HC11 has a dedicated synchronous serial interface
Galled the Serial Peripheral Interface (SPI) which transfers
~ata with MSB-firstand in 8-bit increments. To communicate
with this microprocessor, the LTC1325 MSBF control bit
5hould be setto 1. TheSPI has four lines: Master In Slave Out
[MISO), Master Out Slave In (MaS I), Serial Clock (SCK) and
Slave Select (SS). The 68HC11 is configured as a Master by
tying the SS line high. A control byte is written to the Serial
Peripheral Control Register (SPCR) to select master mode,
5et baud rate and clock timing relationship. Another byte is
written to the Port DDirection Register (DDRD) to set MOSI,
SCK and bit (CS of LTC1325) as outputs. The 68HC11
~Iocks in data from the LTC1325 simultaneously under the
~ontrol of SCK. The microprocessor transmits the LTC1325
~ommandword in 4bytes. This is followed by2 more dummy
Jytes (with all bits set low) in order to clock in the remaining
.TC1325 ADC and status bits.

°

rhis software example allows you to verify communica:ions with the LTC1325. The command word configures
:he LTC1325 to perform an AID conversion on the general
Jurpose VIN input. VIN can be tied to GND or REG or to a

SCKI--_
MOSII--_
PORTD.O 1 - - _
MISO

o 1
1 o 1 o 1

0

1

o 1

0

1START 1MOOO 1BYTE #1 TX

1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 X IBYTE#1RX
BYTE #2 TX
1 x 1 x

x 1 x 1x

x 1 x 1 X BYTE #2 RX

1 0lV21 0lV3

PS 1 ORO 1 OR1

OR2 FSCLR 1 TOO BYTE #3 TX

1 x 1 x

x 1x 1x

T01

T02

VRO 1 VR1 1 0

x

x

x 1x 1x

x

x

x 1x 1x

D7

06

X

X 1 X BYTE#3RX

o 1 0

BYTE #4 TX

09

08

BYTE #4 RX

X

x

X BYTE#5TX

05 1 04103102

01

00 1BYTE #5 RX

~~~~~~~~~
X 1 x
x 1 x 1 x 1 x x x 1BYTE #6 TX
~~~~~~~~~

....B_AT_P1-1B_AT_RI1-FM_C-,VIL...F_EV0...JIL...F_HTF...JI_FL_TF-L-tO_UT-L-F_S.....1BYTE #6 RX
X= ~ON'T CARE

LTC1325·AI01

4-487

III

LTC 1325
APPLICATions InFORmAnon
LABEL MNEMONIC OPERAND

CSLOW
LOOP1

LOOP2

LOOP3

LDAA
STAA
LDAA
STAA
LDX
BCLR
LOAA
STAA
TST
BPL
LOAA
STAA
TST
BPL
LOAA
STAA
TST
BPL
LOAA
STAA

#$51
$1028
#$39
$1009
#$1000
$08,X,#$01
#$02
$102A
$1029
LOOP1
#$24
$102A
$1029
LOOP2
#$03
$102A
$1029
LOOP3
#$CO
$102A

.COMMENTS
Write control byte to the SPCR
Setup Port D DDRD
Port 0 Bit 0 is CS
Load port base AOOR
Take C"S low
Send Byte #1 (MSB) with
START bit
Check for SPI transfer
complete bit
Send Byte 2
Check for SPI transfer
complete bit
Send Byte 3
Check for SPltransfer
complete bit
Send Byte 4

TYPICAL APPLICATiOn

LABEL MNEMONIC OPERAND

COMMENTS

LOOP4 TST
BPL
LOAA
ANDA
STAA
LDAA
STAA
LOOP5 TST
BPL
LOAA
STAA
LOAA
STAA
LOOP6 TST
BPL
LOAA
STAA
BSET
BRA

Check for SPI transfer
complete bit
Get NO high byte
Mask off unwanted bits
Store in user memory
Send dummy Byte #1

$1029
LOOP4
$102A
#$03
HIOATA
#$00
$102A
$1029
LOOP5
$102A
LOOATA
#$00
$102A
$1029
LOOP6
$102A
STATUS
$OB,X,#$01
CSLOW

Check for SPI transfer
complete bit
Get NO low byte
Store in user memory
Send dummy Byte #2
Check for SPI transfer
complete bit
Get STATUS byte
Store in user memory
Raise CS high
Loop for continuous readings

Wide Voltage Battery Charger

I---------------~

I

NOTE 1

: NmE2

I

r-----P-----~~~~----~~~--~----------------,

RTRK

02
I
lN4744A:
15V
I

NOTE 1: NEEDED WHEN Voc > 16V OR MAXIMUM
BATTERY VOLTAGE, VBAl> 16V.
NOTE 2: REGULATOR. OMIT THIS BLOCK AND SHORT
VDD TO Voc WHEN Voc < 16V.
NOTE 3: LEVEL SHIFTER. OMIT THIS BLOCK AND SHORT
PGATE TO PI GATE WHEN Voc < 16V.

4-488

NOTE 4: ZENER TO CLAMP VBAl TO BELOW Voo.
OMIT WHEN Voc< 16V.
NOTE 5: EXTERNAL BATTERY DIVIDER. NEEDED WHEN
MAXIMUM BATTERY VOLTAGE, VBAl> 16V.
NOTE 6: VIN IS AN UNCOMMlmD AID CHANNEL.

NOTE 7: OPTIONAL DIODE TO PREVENT BAmRY
DRAIN WHEN THE CHARGING SUPPLY IS POWERED
DOWN (SEE SECTION 2, HARDWARE DESIGN
PROCEDURE).

LTC 1325
'ELATED PARTS
'ART NUMBER

DESCRIPTION

COMMENTS

r'"1510

Constant Voltage/Constant Current Battery Charger

1.3A, Li-Ion, NiCd, NiMH, Pb-Acid Charger

T1512

SEPIC Constant CurrenVConstant Voltage Battery Charger 0.75A, VIN Greater or Less Than VBAl

L7l'D~

4-489

NOTES

4-490

SECTion 5-lnTEAFACE

5-1

INDEX
SECTION 5-INTERFACE
INDEX ........................................................................................................................................ 5-2
SELECTION GUIDES ........................................................................................................................ 5-3
PROPRIETARY PRODUCTS
RS2321562 ................................................................................................................................. 5-9
LTC1348, 3.3V Low Power RS232 3-Driver/S-Receiver Transceiver ......................................................... 5-10
LT1537, Advanced Low Power 5V RS232 Transceiver with Small Capacitors ............................................... 5-18
RS485 ..................................................................................................................................... 5-25
LTC1480, 3.3V Ultra-Low Power RS485 Transceiver .. ........................................................................ 5-26
LTC1481, Ultra-Low Power RS485 Transceiver with Shutdown .............................................................. 5-34
LTC1483, Ultra-Low Power RS485 Low EMI Transceiver with Shutdown ................................................... 5-41
LTC1487, Ultra-Low Power RS485 with Low EMI, Shutdown and High Input Impedance ................................ 5-49
V.35 ....................................................................................................................................... 5-57
LTC1345, Single Supply V.35 Transceiver ........................................................................................ 5-58
LTC1346, 10Mbps DCEJDTE V.35 Transceiver ................................................................................. 13-65
AppleTalk@ ............................................................................................................................... 5-69
LTC1318, Single 5V RS232/RS422/AppleTall(lP DCE Transceiver ............................................................. 5-70
LTC1323, Single 5VAppieTall(lP Transceiver ..................................................................................... 5-77
LTC1324, Single Supply LocalTal1(lP Transceiver .............................................................................. 13-45
LT1389, AppleTal1(lP Peripheral Interface Transceiver ........................................................................ 13-73
INFRARED ................................................................................................................................ 5-89
LT1319, Multiple Modulation Standard Infrared Receiver .................................................................... 5-90
MIXED PROTOCOL .................................................................................................................... 5-101
LTC1334, Single 5V RS232/RS485 Multi-Protocol Transceiver ............................................................. 13-53

5-2

INTERFACE

I

rl

Multiple Drivers/Receivers

5V/3.3V Powered

I

LT1330 (SOx, SRx), LT1331 (SOx. SAx). lT1342 (30x, SRx)

1

RS232

l-{

3.3V Powered

Multiple Drivers/Receivers

J

LT1332 (30x, 5Rx) uses LT1109A.LTC1348 (30x, SRx)

-----1

~rl

5VPowered

I

2 Drivers, 2 Receivers

1

I

No Shutdown

I I

LT1181A (O.lj.tF Caps)

I

LT1180A (O.lIlF Caps)
LT1280A (Very Low Power)

LT1281A (Very Low Power)
LT1381 (Narrow SOle)
LTC1383 (Ultra-Low Power)

y

Shutdown/3 State RS232
and TTL Outputs

LTC1382 (Ultra~low Power)
LTC1384 (Ultra-low Power, Rx Enable)

I

Multiple Drivers/Receivers

IShutdown/3
State Outputs I I
No
I IRS232
Shutdown/3 State ; I I± 15kV ESD I
and Receiver(s) Active
Shutdown
and TTL Outputs
Protected
LT1237 (30x, SRx, lRx Active)

lT1130A(5Dx,5Rx)

LT1131A(5Dx,4Rx)

LTC1338 (SOx, 3Rx, 3Rx Active)

LT1132A (50x. 3Rx)
LT1133A (30x, SAx)
LT1134A (4Dx, 4Rx)

lT1136A (4Dx, SRx)

lT1341 (30x,5Rx, lRxActive)
LTCl347 (3Ox, 5Rx, SRx Active)

LT1138A (SOx, 3Rx) LT1137A
LTC1337 (30x, 5Rx)

lT1137A (30x, SRx) LT1537 (SOx, 5Rx)

LTC1349 (30x. 5Rx, 2Rx Active)

-----1

I

5V/+ 12V Powered
5V/+ 12V Powered

I
I

EIA/TIA562

H

RS485/RS422

3.3V Powered

I

I

No Shutdown

LT1039-16 (30x,3Rx)
LT1135A(5Dx,3Rx)

I I
I

:

H

Programmable EIA/TIA562/ I
RS232 or RS485
H

I

I

I 5V Powered I I ±5V Powered I
LTC1334 ('OxIRx232.
20xlRx485)

Shutdown/3 State RS232
and TTL Outputs

LT1039 (30x,3Rx)
LT1130A (4OX. ORx)
LT1132A (40x, ORx)

LTC1327 (30x, 5Rx)
LTC1350 (30x, 5Rx)
LTC1385 (30x,5Rx)

LTC1322, lTC1335
(40xlRx562,2DxlRx485)
LTC1321 (20xlRx562 or 232,
20xlRx485)

World's Lowest Power
RS485 Devices

e

I
I

H

••

LTC1318 (5V DCE Combination RS422, RS562)
LTC1320 (OTE Combination RS422, RS562)
lTC1323 (OTE 5V Combination RS422, RS562)
LTC1323·16 (5V Combination RS422, RS562)
LTC1324 (OTE or OTE Differential Line XCVR)
LT1389 (±5V Powered DCE)

1

L
I ±5V Powered I

LTC1345 (3Ox. 3Tx) DTE or DCE Selectable

LTC1346 (30x, 3Tx) DTE or DCE Selectable

H

SCSI Active Terminators

I
I

5V/+ 12V Powered

RS423

I

LTC485 (1 Ox, 1Rx) Low Power 75176
lTC486 (40x) Low Power 75172
lTC487 (40x) low Power 75174
LTC488 (4Rx) low Power 75173
LTC489 (4Rx) Low Power75175
LTC490 (1 Ox, 1Rx) low Power 75179
LTC491 (1 Ox, 1Rx) Low Power 75ALS180
LTC1400 (1 Ox, 1Rx) 3.3V Powered
lTC1481 (10x, 1Rx) Low Power 75ALS176 wlSlO
LTC1483(1Dx, lRx) LowEMt Low Pwr75ALS176wIS/D
LTC1485 (1 Ox, 1Rx) Low Power 75AlS176
LTC1487 (1Dx, lRx) Hi·Z LowPwr 75ALS176 w/SlD

I

1
I 5V Powered I

I

LT1f39A(30x,3Rx)
LT1l40A(50x,3Rx)
L~1141A (30x, 5Rx)

H AppleTalk"
V.35

I

LT1139A (4Dx, 4Rx)

-----1

1

Shutdown/3 State RS232
and TTL Outputs

Complete AppleTalk
Port

Shutdown/3 State RS423
Outputs

I

I

Ln032 (.ox. ORx)

m

I

I

I

I Active
For Use With I I For Use With I
Negation
Open Collector
Line Drivers
LT1118·2.85

H

Multiprotocol
(IrDA Newton)

Infrared Data Receiver
LT1319

Line Drivers
LT1117·2.85

I
AppleTalk is a regIstered trademark of Apple Computer. Inc.

5-3

RS232 INTERFACE SOLUTIONS
Complete RS232 PC Serial Ports: 3 Drivers, 5 Receivers
•
•
•
•
•
•

±1SkV ESD Protection (LT1137A)
±10kV ESD Protection (All Others)
3V Logic Compatible
Receiver Keep-Alive in Shutdown
SO, SSOP Packages
Ultra-Low Power (LTC1337: 1.SmW)

•
•
•
•
•
•

Flowthrough Architecture
0.1 JlF Capacitors
Low Power Shutdown
120kBaud Operation
Capable of Mouse Driving
3.3V or SV Powered

Typical Pin
Configuralion t
28 v27
C226
C2+
25
DRIVER IN
24
RXOUT
23
DRIVER IN
22
RXOUT
21
RXOUT
20
RXOUT
19
DRIVER IN
18
RX OUT'
17 GND

v+

3V
TYP
SUPPLY OR5V POWER
VOLTAGE LOGIC DISSlmW)

Rx
ACTIVE
IN SHDN

laiN
SHDN
lIlA)
1

DRIVER 10kV O.1I1F DEVICE
DISABLE ESD CAPS TYPE

5

5

30

0
1

60

X
X

3

3

1.5

0

1

-

5&3
3
5&3

3
3

30
42

1
1

60

3

34

1

60
60

X
X
X

3

3

1.5

1

70

5

5

1.5

0

1

-

5
5&3

5
3

60
60

1
0

60
1

X
X

5

5

1.5

5

80

3

3

1.5

oor5

0.20rl0

-

5

5

60

5V13VVcc
Cl+

xt
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X'
X
X'
X
X'
X
X
X
X
X
X
X
X
X

Cl-

LT1137A
LT1237

DRIVER OUT
RXIN

LTC1327
LT1330
LT1331
LT1331

DRIVER OUT
TO
LINE

RXIN
RXIN
RXIN'

LT1332"
LTC1337

DRIVER OUT

LT1341
LT1342

ON/OFF = 5V

LTC1347

RXIN

3VVl
(SEECHARn

, REMAINS ALIVE IN SHUTDOWN
DEPENDING ON PART TYPE
t EXCEPT LT1332 AND LTC1348

LTC1348

5
1.5
2
35
LTC1349
1.5
LTC1350
3
3
2
35
40
LT1537
5
5
0
1
X
'Requires one II!f capacitor
., Works with switching power supply to generate full RS232 output levels from 3V supplies
t 15kV ESO protection
5

13
14

5V Powered RS2322 Driver/2 Receiver Circuits
• Rugged Bipolar Construction
• ±1OkV ESD Protection
• 0.1 JlF Charge Pump Capacitors
SHUTDOWNI
RS232 AND
FAULT
TTL THREETOLERANT
STATE OUTPUTS
TO±25V
Yes
Yes
No
Yes
Yes
Yes
No
Yes
No
±15V
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
• Narrow 16-lead SO package

5-4

• Immune to Latch-Up
• Low Power Shutdown
• Three-State Outputs When Shut Down

COMMENTS
Ideal for Surface Mount, 10kV ESO
Replaces MAX202, 232A, 10kV ESO
Low Power LT1080
Low Power LTl081
Replaces MAX202
Ultra-Low Power LT1180A
Ultra-Low Power LT1181A, MAX232A Replacement
U~ra-Low Power LT1180A w/2Rx Alive in SHON
Ultra-Low Power 3V LT1180A
Ultra-Low Power 3V LT1181A

PART
NUMBER
LT1180A
LT1181 A
LT1280A
LT1281A
LT1381 ,
LTC1382
LTC1383*
LTC1384
LTC1385
LTC1386*

LT1180A, LT1280A,
LTC1382/4/5
2 Ox, 2 Rx

LT1181A, LT1281A,
LT1381 , LTC1383
20x,2RX

TO
LOGIC

RS232/RS422/RS485 INTERFACE SOLUTIONS
)ther RS232 Driver/Receiver Combinations
SHUTDDWNI

RS232 and
IRIVERS
4
4
3
3
5
5
5
3
4
5
4
5
4
5
3
5

RECEIVERS
0
0
3
3
5
4
3
5
4
3
5
3
4
3
5
3

SUPPLIES
REQUIRED
±12V
±12V
5V, ±12V
5V,±12V
5V
5V
5V
5V
5V
5V, ±12V
5V
5V
5V,12V
5V, ±12V
5V, ±12V
5V

TTL THREESTATE OUTPUTS
Yes
Yes
Yes
No
No
Yes
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes

FAULT
TOLERANT

lo±25V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

REQ'D
CHARGE
PUMP
CAPSIZE
N/A
N/A
N/A
N/A
O.llJF
O·V
O.llJF
O·V
O·V
N/A
O·V
O.llJF
O.llJF
N/A
N/A
O.llJF

COMMENTS
Low Power 1488 Upgrade
Low Power 1488 Upgrade Also Supports RS423
One Receiver Active in Shutdown
Rugged MC145406 Replacement
Synchronous Communications, ±10kV ESO
Synchronous Modem/DCE Interface, ±10kV ESD
Modem/DCE Interface, +10kV ESD
PC/OTE Interface, ±10kV ESO
5V Only 1488/1489 Replacement, ±10kV ESD
Modem/DCE Interface, ±10kV ESD
Synchronous PC/DTE Interface, ±10kV ESD
ModemlDCE Interface, ±10kV ESD
1488/1489 Replacement, ±1OkV ESD
Modem/DCE Interface, ±10kV ESD
PC/DTE Interface, ±10kV ESD
Ultra-low Power, 1 Receiver Keep-Alive in SHDN, ±10kV ESD

PART
NUMBER
LT1030
LT1032
m039
LT1039-16
LTl130A
LT1131A
lTl132A
lTl133A
lT1134A
lTl135A
lT1136A
m138A
lT1139A
lT1140A
lT1141A
lTC1338

'rogrammable EIAfflA5621RS232 and RS485 I/O Ports
Low Supply Current: 1mA Typical
1511A Supply Current in Shutdown
5V Powered (LTC1334)
120kBaud in EIAfTIA562 or RS232
1OM Baud in RS485/RS422
Self-Testing Capability in Loopback Mode
LTC1321/LTC1322 Have the Same Pinout
as SP301/SP302
RS232 OR EIA/TIA562
TRANSCEIVERS
2
4
4
4

lTC1321
2 RS485 DRIVERS/RECEIVERS
EIA/TIA562 DRIVERS/RECEIVERS

(7lJD~

RS485
TRANSCEIVERS
2
2
2

2

• LTC1335 Features Receiver Three-State Outputs
• Power-Up/Down Glitch-Free Outputs
• Driver Maintains High Impedance in Three-State,
Shutdown, or With Power Off
• Thermal Shutdown Protection
• Protection: I/O Lines Can Withstand ±2.5V
• Withstands Repeated ±10kV ESD Pulses
• SO Wide or Dual-In-Line Packages
OUTPUT
LEVELS
232/562
232/562
232
562

DRIVER
ENABLE

-

Yes
Yes

SELF TEST
LOOPBACK
Yes
Yes
Yes
Yes

PART NUMBER
lTC1321
lTC1322
LTC1334
lTC1335

lTC1334
2 RS485 DRIVERS/RECEIVERS
4 RS232 DRIVERS/RECEIVERS
lTC1335
lTC1322
5V POWERED
2 RS485 DRIVERS/RECEIVERS
2 RS485 DRIVERS/RECEIVERS
4 EIA/TIA562 DRIVERS/RECEIVERS
4 EIA/TIA562 DRIVERS/RECEIVERS

5-5

ISOLATED AND APPLETAL~ INTERFACE SOLUTIONS
Low Power Digital Isolators

Digital Isolation Interface
Data Rale Up 10 200kHz

• UL Recognized\\l (LTCl145A,LTCl146A)
File E15l738 to UL1577
• Low Input Current

I, =100kHz
DAi~ 5~...f1IL

1 DIN

LTC1145:700~, LTC1146:70~

ISOLATION
-

• Maximum Input Frequency
LTCl145:200kHz,LTCl146:20kHz
• TIL Level Output
• Noise Filter Prevents Glitches at the Output
• Output Can Be Synchronized to and External Clock
ISOLATION
VOLTAGE
2500
2500
500
500

• Low Power Opto-Isolator Replacemen
• Isolated Serial Data Interfaces
• Isolated Power MOSFET Drivers

GNDI 18

INPUT
CURRENT
7001lA
701lA
7001lA
701lA

_~,!!!I~-

LTC1145J46
5V
Vee 12

7 NC

MAX INPUT
FREQUENCY
200kHz
20kHz
200kHz
20kHz

8 OSC,.

aBoUT 11

9 GND2

Dour 10

GlITCH·FREE
OUTPUT FILTER
Yes
Yes
Yes
Yes

DATA
OUT

EXT CLOCK
SYNCH
Yes
Yes
Yes
Yes

UL
RECOGNIZED
1M
1M

PART NUMBER
LTC1145A
LTC1146A
LTC1145
LTC1146

Complete AppleTalk/LocaITa/~ Transceivers
•
•
•
•

Single Chip Complete AppleTalk DCE/DTE Solutions
Low Power
Micropower Shutdown (LTC1320/LTC1323/LTC1323-l6)
Micropower Receiver Keep Alive (LTC1323)
REQUIRED
SUPPLIES
±5V
5V
5V
5V
5V
5V

DCEJDTE
DTE
DTE
DTE
DCE
DTE/DCE
DCE
TXO
TXI
SO

AXEN

RXO
AXO
RXDO

Q;

~
~
~

~

r, ~

IT

,

GND [i

H

~VDD

el- 2
OPEN

6 TXO+

3

TXD 4

~ TXO

TXO~~ ~

~Vss

~iOO
~

SUPPLY
CURRENT
1.2mA
2.4mA
2.4mA
18mA
1mA
8mA/-3mA
C1+ 1

~ TXD-

.:.*
:~

AXI

1 RXO-

L jill AXil'

DTE

LTC1320

AXDO ~
G.O 12

CHARGE

PUMP

~
Ox

~
Rx

SHUTDOWN
FUNCTION
Yes
Yes
Yes
No
Yes
Yes

24 Vee

1 RECEIVER
KEEP ALIVE

SUPPLY IN
SHUTDOWN
301lA
651lA
651lA

Yes

-

-

VEE
TXO1XD+
TXO

TXD[!
TXO'N"
SO [[

17RXi

[!
RXOO .L
GND [!
RXEN

16 RXI

15 R}m14 RXO+

DTE

TC1323

13 PGN\

~

PART NUMBER
LTC1320
LTC1323
LTC1323·16
LTC1318
LTC1324
LT1389

-

11lA
101lA

Cl'L!. ::IeHARG' PUMPI!ii ~VGC
erC[
~G2'

23 02+
22 C221
2D
19
18

• Small Charge Pump Capacitors
• Drivers High Impedance in
Shutdown/Power Off States

• 5V Powered
(LTC1323/LTC1323-l6/LTC13l8)
• Surface Mount Packages
• Thermal/Short Circuit Protection

!HI 02~VEE

~nm-

lrunm+

~RXD-

""l. t!J RXC' DTE
LTC1323-16

If'
CI'
CI-

AXIt

-

~ :aC;~~~E~

3~
4

R8232

TXDI 5RS23~
6 R5232
TXO'
Vee

;~

24 V23 0222 02+

21 RXOl
20 lXI2
19 TXI1
18 GND

17
16
15
14
NC '-1...
12 _ _..J""""
13

AXil'
RXo-lAXI2

1~~

TXD'
11"''' l1RS422~

RXDOJR XO'
TXO

RXMOD
GND
NC

DCE

LTC1318

AppleTalk and LocalTalk are registered trademarks of Apple Computer, Inc.

V.35 Interface
• Single Chip Provides All V.35 Differential Clock
and Data Signals
• Operates From Single 5V Supply (LTC1345)
• Shutdown Mode Reduces Icc to lIlA Typ
• Software Selectable DTE or DCE Configuration
• ±10kV ESD Protection
• 1OM Baud Transmission Rate
• Transmitter Maintains High Impedance When
Disabled, Shut Down or with Power Off
• Meets cem V.35 Specification
• Transmitters are Short-Circuit Protected
• Available in Surface Mount SW Packages
• 5V Powered (LTC1345) ±5V Powered (LTC1346)

5-6

001""
m· ~
_
500

BECKMAN
627T5001125O

'

RS485 INTERFACE SOLUTIONS
RS485 Family Features
•
•
•
•
•
•
•
•
•
•

The LTC RS485 Advantage:
Low Power
60 _ _ _----,

Ultra-Low Power
CMOS Schottky Process
Designed for RS485 and RS422 Applications
Three-State RS485 Outputs When Shut Down
Power-Up/Down Glitch Free Outputs
Power-Saving Shutdown Mode (LTC1481, LTC1483, LTC1487)
Low EMI (LTC1483, LTC1487)
10MB Operation (LTC486-489, LTC1485)
Industry Standard Pinouts
SO Available

~50

~50

~

~

~

~ 40

40

~ 30

~ 30

i:'

i:'

~ 20

~ 20

i

~ 10

10

o
75176 lTC48S*
7517214 LTC48617"
'ULTRA lOW SUPPLY CURRENT

RS4851RS422 Interface
SUPPLIES
DRIVERS RECEIVERS REQUIRED
1
4
4
0
0
1
1
1
1
1
1

1
0
0
4
4
1
1
1
1
1
1

AND ~~~iLI~~

5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V

MAX
MAX
SHUTDOWN DRIVERS DISABLE INDUSTRY
DATA SUPPLY
SUPPLY
SUPPLY
STANDARD
RATE CURRENT CURRENT
CURENT
PINOUT COMMENTS
2.5MB
10MB
10MB
10MB
10MB
2.5MB
2.5MB
2.5MB
150kB
10MB
250kB

~

500~

75176
75172
75174
75173
75175
75179
75ALS180
75176
75176
75ALS176B
75176

150~

150~

10mA
10mA
500~
500~
500~

10~

120~

500~

10~

120~

10~

120~

3.5mA
200~

cc

RS485 110

lTC485, lTC1481, lTC1483,
lTC1485, lTC1487
10x,1 Rx

PART

Half Duplex 2-Wire RS485
Good For RS449, RS530, V.35 Inlertace
Good For RS449, RS530, V.35 Inlertace
Good For RS449, RS530, V.35 Inlertace
Good For RS449, RS530, V.35 Intertace
Full Duplex 4-Wire RS485
Full Duplex 4-Wire RS485
Ultra-Low Power Half Duplex 2-Wire RS485 wlSD
Low EMI Ultra-Low Power 2-Wire RS485 wlSD
High SpeedlHalf Duplex
High Inpullmpedance, Ultra-Low Power, Low EMI
2-Wire RS485 wlShutdown

Vcc~

LOGIC 110 ~

- l TC487
40x

40x

- l TC488
4Rx

lTC490
1 Ox, 1Rx

RS4851!0

II'" I'"" If'"" II'"
~ l TC486

NUMBER
LTC485
LTC486
LTC487
LTC488
LTC489
LTC490
LTC491
LTC1481
LTC1483
LTC1485
LTC1487

~

LOGIC 110
AND ENABLES

- l TC489
4Rx

vcc
Vee
RS485 110

lTC491
1 Ox, 1 Rx

Interface Standards
SPECIFICATION
Mode of Operation
Number of Drivers and Receivers
Allowed on One Line
Maximum Cable Length
Maximum Data Rate
Maximum Voltage Applied to Driver Output
Driver Output Signal
I Loaded
I Unloaded
Driver Load
Maximum Driver Output Current
Power ON
(High-Impedance State)
I Power OFF
Output Slew Rate
Receiver Input Voltage Range
Receiver Input Sensitivity
Receiver Input Resistance

l

RS232
Single-Ended
1 Driver,
1 Receiver
50 feet'
20kbls
±25V
±5V
±15V
3kn to 7kn

RS423
Single-Ended
1 Driver,
10 Receivers
4000 feet
100kbls
±6V
±3.6V
±6V
450n (Min)

RS422
Differential
1 Driver,
10 Receivers
4000 feet
10Mbls
-0.25Vto 6V
±2V
+5V
lOOn

-

-

-

VMAX/300n
30VlllS (Max)
±15V
+3V
3kQ to 7kn

±100!J,A
Controls Provided
±12V
+200mV
4kn (Min)

±lOOIlA

±7V
+200mV
4kQ (Min)

RS485
Differential
32 Drivers,
32 Receivers
4000 feet
10Mbls
-?V to 12V
±1.5V
+5V
54n

±lOOIlA
-

-7V to 12V
+200mV
12kn (Min)

RS562
Single-Ended
1 Driver,
1 Receiver
50 feet'
64kbls
+25V
±3.7V
+13.2V
3kn to 7kn
60mA
VMAx/300n
30V/IlS (Max)
±25V
+3V
3knto 7kn

or 2500pF cable capaCitance, as per EIA 232E

5-7

II

NOTES

5-8

.L7lJD~

INDEX
iECTION 5-INTERFACE
RS232/562
LTC1348, 3.3V Low Power RS232 3-0river/5-Receiver Transceiver •.••.•..•••.•..•••....••..••...••.....•............•..... 5-10
LT1537, Advanced Low Power 5V RS232 Transceiver with Small Capacitors ...........•...••...•...........•.....•....... 5-18

•

L7lJD~

5-9

.~,
f"""-unef\Q
TECHNOLOG~IY~-3-.-3V-I-5-.0-V-Lo-w-p-o-w-e-r-R-S2-3-2

LTC1348

3-Driver15-Receiver Transceiver
FEATURES

DESCRIPTion

Low Supply Current: 500~
Supply Current in Shutdown: O.2~
Supply Current in Receiver Alive Mode: 15~
ESD Protection over ±10kV
Operates from a Single 3.3V or 5V Supply
Operates to 120kBaud with 0.1 ~ Flying Capacitors
Three-State Outputs Are High Impedance When Off
Output Overvoltage Does Not Force Current
Back into Supplies
• RS232 I/O Lines Can Be Forced to ±2SV
Without Damage
• Flowthrough Architecture

The LTC@1348 is a3-driver/S-receiver RS232 transceiver
with very low supply current. The charge pump only
requires five 0.1 ~ capacitors. The LTC1348 provides full
RS232 output levels when operated over a wide supply
range of 3.0V to S.SV

•
•
•
•
•
•
•
•

APPLICATions
•
•
•
•

Notebook Computers
Palmtop Computers
Printers
Portable Instruments

The transceiver operates in one of four modes: Normal,
Receiver Disable, Receiver Alive and Shutdown. In Normal
or Receiver Disable mode, Icc is only SOOJ,JA in the no load
condition. In Shutdown mode, the supply current is further reduced to 0.2J,JA. In Receiver Alive mode, all five
receivers are kept alive and the supply current is 1SJ,JA. All
RS232 outputs assume a high impedance state in Shutdown or Receiver Alive mode or with the power off. The
receiver outputs assume a high impedance state in Receiver Disable or with the power off.
The LTC1348 is fully compliant with all data rate and
overvoltage RS232 specifications. The transceiver operates up to 120kbaud with all drivers loaded with 1000pF,
3kn. Both driver outputs and receiver inputs can be forced
to ±2SV without damage and can survive multiple ±10kV
ESD strikes.
LT. LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Supply Current

3-Drivers/5-Receivers with Shutdown
1200
C5

0.1j.lF -:;;!;" C2
- 0.1j.lF

C4
-:;;!;,,0.1j.lf

1.2

Vee = 3.3V

1000

1.0
rJ)

~

!;;; 800

V
~bt
~HUTDJWN-

600

13 400
200

o

-40

0.4
0.2

-20

0
20
40
TEMPERATURE (OC)

60

80

...c::
'"'"

::;:
0.6

ICUR~

'5

<3

5-10

0.8

,QUIESCENT
CURRENT

ll!
a:;

13
~

:I:

/

0

z
C")
c::

'"'"
~

1

LTC 1348
~BSOLUTE

mAXimum RATinGS

PACKAGE/ORDER InFORmATion

Note 1)
;upply Voltage (Vee) ................................................ 6V
nput Voltage
Driver ....................................... -0.3V to Vee + 0.3V
Receiver .. ... ......... ...................... ... ........ - 25V to 25V
Driver/Receiver Enable Pin ........ -0.3V to Vee + 0.3V
)utput Voltage
Driver .................................................... - 25V to 25V
Receiver .................................... -0.3V to Vee + 0.3V
;hort-Circuit Duration
V+ ................................................................... 30 sec
V- ................................................................... 30 sec
Driver Output .............................................. Indefinite
Receiver Output .......................................... Indefinite
)perating Temperature Range .................... O°C to 70°C
ltorage Temperature Range ................ -65°C to 150°C
.ead Temperature (Soldering, 10 sec) ................. 300°C

TOP VIEW

ORDER PART
NUMBER
LTC1348CG
LTC1348CSW

G PACKAGE
28·LEAD PLASTIC SSOP

SW PACKAGE
28·LEAD PLASTIC SO WIDE

TJMAX =125'C, 8JA =96'C/W (G)
TJMAX = 125'C, 8JA = B5'CIW (SW)

Consult factory for Industrial and Military grade parts.

)C ELECTRICAL CHARACTERISTICS
rcc =3.3V, C1 =C2 =C3 =C4 =C5 =O.1!lf, unless otherwise noted.
'ARAMETER
Iny Driver
lutput Voltage Swing
ogic Input Voltage Level
ogie Input Current
lutput Short-Circuit Current
lutput Leakage Current
ny Receiver
lput Voltage Thresholds

Iysteresis
lput Resistance
lutput Voltage
'utput Short-Circuit Current
utput Leakage Current

L7lJn~

I CONDITIONS
3kto GND

Positive
Negative

Input Low Level (VOUT =High)
Input High Level (VOUT =Low)
VIN =Vee
VIN =OV
VOUT =OV
Shutdown (Note 3) or Receiver Alive (Note 4), VOUT = ±20V
Input Threshold (Receiver Alive Mode)
Input Low Threshold (Normal Mode)
Input High Threshold (Normal Mode)
Normal Mode
VIN =±10V
Output Low, lOUT =-1.6mA (Vee =3.3V)
Output High, lOUT =160JJA (Vee = 3.3V)
Sinking Current, VOUT =Vee
Shutdown (Note 3), OV::; VOUT::; Vee

••
••
••
•
••
•
•
•

•
•

MIN

TYP

S.O
-S.O

6.7
-6.S
1.4
1.4

2.0

-S
±12
±10
O.B
O.B
0.1
3
3.0
-3

1.S
1.3
1.7
0.4
5
0.2
3.2
-20
1

MAX

O.B

UNITS
V
V
V
V

S
-20

JJA
JJA
rnA

±SOO

JJA

2.4
2.4
1
7
0.4

V
V
V
V
kn
V
V
rnA

10

JJA

5-11

LTC 1348

DC ELECTRICAL CHARACTERISTICS
Vee =3.3V, C1 =C2 =C3 =C4 =C5 =D.1~, unless otherwise noted.
PARAMETER
Power Supply Generator
V+ Output Voltage

v- Output Voltage
Supply Rise Time
Power Supply
Vee Supply Current
Supply Leakage Current (Vecl
Driver/Receiver Enable Threshold Low
Driver/Receiver Enable Threshold High

I CONDITIONS

MIN

TYP

MAX

B.O
7.S
-B.O
-7.0
0.2

10UT=OmA
lOUT = BmA
lOUT = OmA
10UT=-BmA
Shutdown to Turn·On
No Load (Note 2) Vee = 3.3V or SV
Receiver Alive Mode (Note 4) Vee = 3.3V or SV
Shutdown (Note 3)
Vee = 3.3V
Vee = 3.3V

•
•
•
•
•

2.0

UNITS
V
V
V
V
ms

O.S
15.0
0.2
1.4
1.4

1:5
30.0
10
O.B

mA
J.IA
J.IA
V
V

TYP
2S0
B
4
2
2
0.3
0.2
1.0
0.3

MAX

UNITS
kbps

AC ELEORICAL CHARAOERISTICS
Vee =3.3Vor 5V, C1 =C2 =C3 =C4 =C5 =D.1~, unless otherwise noted.
PARAMETER
Maximum Data Rate
Slew Rate
Driver Propagation Delay
(TIL to RS232)
Receiver Propagation Delay
(RS232 to TIL)

CONDITIONS
RL = 3k, CL = 1000pF, One Driver Switching
RL = 3k, CL = S1pF
RL = 3k, CL = 2500pF
tHLO (Figure 1)
tLHO (Figure 1)
tHLR (Figure 2) (Normal Mode)
tLHR (Figure 2) (Normal Mode)
tHLR (Figure 2) (Receiver Alive Mode)
tLHR (Figure 2) (Receiver Alive Mode)

The. denotes specifications which apply over the operating temperature
range of O°C ,,; TA ,,; 70°C.
Note1: Absolute maximum ratings are those values beyond which the life
of the device may be impaired.
Note 2: Supply current is measured with driver and receiver outputs
unloaded. The VOUN and VRUN = Vee.

5-12

•
••
••
•
•

MIN
120

30
3.5
3.S
O.B
0.8
2.0
2.0

V/fJS
V/fJS
fJS
fJS
fJS
fJS
fJS
fJS

Note 3: Supply current measurement in Shutdown is performed with
VOUN and VRlCEN = OV.
Nole 4: Supply current measurement in Receiver Alive mode is performed
with VOUN = OVand VRUN = Vee·

LTC 1348
'YPICAl PERFORmAnCE CHARACTERISTICS
Driver Dutput Voltage High/Low
vs. Load Capacitance (CLl

VS.
50

7
~~Ql
'-'
~

OUTPUT LOW
I
-120~1
I~

/"'"
/'

/ , 1 OUTPUT LOADED
3kn II 2500pF
-

/

/

10

Vee = 3.3V

20kbps

o

/

::::>

'"

~

/

20

00-

I

~

/'r'

a:

,-

~

i/

25

'-'

20

~

10

~

.....

:i:

20
30
40
50
TEMPERATURE (OC)

35

~
..... 30

i"...: ~s

'"

Vee- 3V _

Vee = 3.3V

Vee = 3.3V

S 10
'-'
(3
8

I
I
Vee = 3.3V

!.....

1D 14

I
ALL DRIVERS
LOADED WITH 3kn

OUTPUTI~

VS.

18

OUTPUT HIGH

-1
-2
-3
-4
-5
-6
-7

Driver Leakage in SHUTDOWN
Temperature (OC)

Driver Short-Curcuit Current
Temperature (OC)

20

o

LTCl348Gaa

VS.

Vee = 3V
Vee=3.3V~
,
,

/
Vor=-2V

15

y
~ 1-"'".'

o

-40 -20

0
20
40
60
TEMPERATURE (OC)

80

100

o

1.

~

'"
70

250

o

10

20
30
40
50
TEMPERATURE (OC)

,..........60

70

With Vee =3.3V
All Driver Outputs Loaded with
3kQ, 1000pF. 1 Driven at 250kbps
DRIVEN DRIVER
OUTPUT

DRIVER
INPUT

LTC1348G07

5-13

LTC 1348

Pin FunCTions
Vee: 3.3V or 5V Input Supply Pin. This pin should be
decoupled with a 0.1!1f ceramic capacitor.

efficiency, the capacitor's effective series resistance shoul!
be less than 1Q. Ceramic capacitors are recommended.

GND: Ground Pin.

DR IN: RS232 Driver Input Pins. Inputs are TTUCMm
compatible. The inputs of unused drivers can be lef
unconnected since 300k input pull-up resistors to Vee an
included on chip. To minimize power consumption, th~
internal driver pull-up resistors are disconnected from Ve(
in the Shutdown or Receiver Alive mode.

RX_EN: TTUCMOS Compatible Enable Pin. Refer to Table
1 for its functional description.
DR_EN: TTUCMOS Compatible Enable Pin. Refer to Table
1 for its functional description.
V+: Positive Supply Output (RS232 Drivers). This pin
requires an external capacitor C= 0.1!1f for charge storage. The capacitor may be tied to ground or Vee. With
multiple devices, the V+ and V- pins may be paralleled into
common capacitors. For large numbers of devices, increasing the size of the shared common storage capacitors is recommended to reduce ripple.

DR OUT: Driver Outputs at RS232 Voltage Levels. Output~
are in a high impedance state when in the Shutdown
Receiver Alive mode or Vee = OV. The driver outputs an
protected against ESD to ±1 OkV for human body mode
discharges.

V-: Negative Supply Output (RS232 Drivers). This pin
requires an external capacitor C= 0.1!1f for charge storage.

RX IN: Receiver Inputs. These pins can be forced to ±25\
without damage. The receiver inputs are protected agains
ESD to ±1 OkV for human body model discharges. Eact
receiver provides O.4Vof hysteresis for noise immunity.1r
Receiver Alive mode all receivers have no hysteresis.

C1+, C1-,C2'", C2"", C:r-, C:t: Commutating Capacitor
Inputs. These pins require three external capacitors C =
0.1!1f: one from C1 +to C1-, another from C2+ to C2- and
another from C3+ to C3-. To maintain charge pump

RX OUT: Receiver Outputs with TTUCMOS Voltage Lev
els. Outputs are in a high impedance state when in th~
Shutdown or Receiver Disable mode to allow data lin~
sharing.

Table 1 Functional Description
RXENABLE

DR ENABLE

Shutdown

MODE

0

0

Receiver
Disable

0

1

Receiver
Alive

1

0

Normal

1

1

5-14

DRIVERS

RECEIVERS

All Drivers Shutdown.
All Driver Outputs Assume High Impedance.
All Driver Pull-Up Resistors Disconnect
From Vce.
All Drivers Alive.

All Receivers Shutdown.
All Receiver Outputs Assume High Impedance.

0.211'

All Receiver Outputs in Three-State.

SOOI!!

All Drivers Shutdown.
All Driver Outputs in Three-State.
All Driver Pull-Up Resistors Disconnect
From Vee.
All Drivers Alive.

All Receivers Alive.

lSI!!

All Receivers Alive.

SOOI!!

Icc TVI

LTC 1348
.WITCHlnG TimE WAVEFORms
DRIVER
INPUT

,..---Vee

"f-_ _ _ _ _ _....!.1.;!!4V+--- ov

DRIVER
JUTPUT _ _---+"

.... - - V +

~-------+OV

OV

-

V-

,..---Vee

RX
INPUT

'--_ _ _ _ _ _..:.::1.3~V4-_ _

ov

RX
~-------+---..2AV Vee
OUTPUT _ _~
OV

tHLD - LTC1348·F02

Figure 1. Driver Propagation Delay Timing

Figure 2. Receiver Propagation Delay Timing

rEST CIRCUITS
ESD Test Circuit
DRIVER
INPUT

LTCl343'F03

Figure 3. Driver Timing Test Load

RS232 LINE PINS
PROTECTED TO ±1OkV

RX INPUT

LTC134B·F04

Figure 4. Receiver Timing Test Load

~PPLICATlons

-=

InFORmATiOn

'ower Supply
'he LTC1348 includes an on-board voltage-tripling charge
lump capable of generating ±8V from a single 3.3V
,upply. This allows the LTC1348 drivers to provide guarlnteed ±5V RS232-compliant voltage levels with a 3.3V
,upply. With all outputs loaded with 3kn, the LTC1348
:an typically swing ±5V with voltages as low as 2.85V. It
viii meet the ±3. 7V EIA562 levels with supply voltages as

L7lJ!l~

LTl348'TC

low as 2.2V. The charge pump requires three external
flying capacitors to operate; 0.1!lf ceramic capacitors are
adequate for most applications. For applications requiring
extremely high data rates or abnormally heavy output
loads, 0.33!lf flying capacitors are recommended. Bypass
and output capacitor values should match those of the
flying capacitors and all capacitors should be mounted as
close to the package as possible.

5-15

LTC 1348
APPLICATions InFoRmATion
High Data Rates
The LTC1348 maintains true RS232 ±5V minimum driver
output even at high data rates. Figure 5shows atest circuit
with 2m wires connecting the two test chips. Both chips
are run from 3.3V supplies. Figure 6 shows the typical line
waveforms with all three drivers, loaded with 1OOOpF and
3kQ, toggling simultaneously at 120kbaud. Figure 7shows

the same circuit with a single 1000pF/3kn loaded driver
driven at 250kbaud, and the other two drivers loaded but
not toggling. This closely approximates the actual behavior of an RS232 serial port, with only one driver (TX) driven
at high speed and the other two drivers (RTS and DTR)
driven ata relatively low data rate orat DC. Under the same
conditions, the LTC1348 can go as fast as 350kbaud and
still meet EIA562 (±3.7V) minimum driver output levels.

DRIVER OUTPUT

RECEIVER OUTPUT

DRIVER INPUT

lTC1348GOO

Figure 6. Driver Test Result at 120kbps

DRIVER OUTPUT

RECEIVER OUTPUT

DRIVER INPUT

Figure 5. Data Rate Evaluation Circuit
LTC1a4&S07

Figure 7. Driver Test Results at 250kbps

5-16

LTC 1348
iELATED PARTS
~RTNUMBER

DESCRIPTION

COMMENTS

'l137A

3-DR/5-RX RS232 Transceiver
3-DR/5-RX RS562 Transceiver

±15kV lEG-SOH ESD Protection
3,3V Operation

1330

3-DR/5-RX RS232

3V Logic Intenace

1331

3-DR/5-RX RS2321RS562 Transceiver

5V RS232 or 3V RS562 Operation

G1347

3-DR/5-RX Micropower RS232 Transceiver

5 Receivers Active in Shutdown

G1327

'-7lJ!J~

5-17

I-Y

~,

Llnm.D. . . _ _ _L_T153~
TECHNOLOGY

Advanced Low Powel
5V RS232 Transceiver wittSmall Capacitor~

FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•
•

The LT®1537 is athree-driver, five-receiver RS232 trans
ceiver, pin compatible with the LT1137A, offering pertor
mance improvements and two shutdown modes. Thl
LT1537's charge pump is designed for extended compliance and can deliver over 35mA of load current. Suppll
current is typically 8mA, competitive with similar CMm
devices. An advanced driver output stage operates up t(
250kbaud while driving heavy capacitive loads.

•
•
•
•

Low Cost
Uses Small Capacitors: 0.1/lf, 0.2/lf
1!JA Supply Current in Shutdown
120kBaud Operation for RL = 3k, CL = 2500pF
250kBaud Operation for RL =3k, Ct. =1000pF
CMOS Comparable Low Power: 40mW
Operates from a Single 5V Supply
Easy PC Layout: Flow-through Architecture
Rugged Bipolar Design
Outputs Assume a High Impedance State When Off
or Powered Down
Improved Protection: RS232 1/0 Lines Can Be Forced
to ±25V Without Damage
Output Overvoltage Does Not Force Current Back
into Supplies
Absolutely No Latch-Up
Available in SO Package

APPLICATions
• Notebook Computers
• Palmtop Computers

The LT1537 is fully compliant with all RS232 specifications. Special bipolar construction techniques protect thl
drivers and receivers beyond the fault conditions stipu
lated for RS232. Driver outputs and receiver inputs can bl
shorted to ±25V without damaging the device or thl
power supply generator. In addition, the RS232 1/0 pim
are resilient to multiple ±5kV ESD strikes.
The transceiver has two shutdown modes. One modI
disables the drivers and the charge pump, the other Shutl
down all circuitry. While shut down, the drivers am
receivers assume high impedance output states.
D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Output Waveforms
RECEIVER
OUTPUT
Cl = 50pF

DRIVER
OUTPUT
Rl =3k
Cl =2500pF

l.T1537·TA01

5-18

L7lJ!J~

LT1537
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

:Note 1)

Supply Voltage (Vee) ............................................. 5.5V
V+ ........................................................................ 13.2V
V- (Note 7) .......................................................... - 6.5V
Input Voltage
Driver ........................................................... V- to V+
Receiver .. .................... ......................... - 25V to 25V
Output Voltage
Driver ....................................... V+ - 25V to V- +25V
Receiver .................................... -0.3V to Vee + 0.3V
Short Circuit Duration
V+ ................................................................... 30 sec
V- ................................................................... 30 sec
Driver Output .............................................. Indefinite
Receiver Output .......................................... Indefinite
Operating Temperature Range
LT1537C ................................................. O°C to 70°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER

TOP VIEW

LT1537CG
LT1537CSW
DRIVER OUT 5
RXIN 6
DRIVER OUT 7

DRIVER OUT 1 1 1 - -.....

GPACKAGE
28·LEAD PLASTIC SSOP

SW PACKAGE
28-LEAD PLASTIC SO WIDE

TJMAX= 150"C, 0JA = 96"C/W (G)
TJMAX = 150"C, OJA = 85"C/W (SW)

Consult factory for Industrial and Military grade parts.

-------------111
ELECTRICAL CHARACTERISTICS
(Note 2)

~ARAMETER

I CONDITIONS

MIN

TYP

MAX

UNITS

~ower

Supply Generator
~+ Output
~- Output
)upply Current (Vee)
)upply Current When OFF (Vecl
)hutdown to Turn-On
)N/OFF Pin Thresholds
)N/OFF Pin Current
)river Disable Pin Thresholds
)river Disable Pin Current
)scillator Frequency
'ny Driver
Mput Voltage Swing
_ogic Input Voltage Level
_ogic Input Current
)utput Short-Circuit Current

.L7lJ!J~

•
•

(Note 3)
Shutdown (Note 4)
DRIVER DISABLE
C+, C- = 0.1~, C1, C2 = 0.2~
Input LOW Level (Device Shutdown)
Input HIGH Level (Device Enabled)
OV ~ VON/OFF ~ 5V
Input LOW Level (Drivers Enabled)
Input HIGH Level (Drivers Disabled)
OV ~ VDRIVER DISABLE ~ 5V

Load =3k to GND
Input LOW Level (VOUT =HIGH)
Input HIGH Level (VOUT =LOW)
0.8V ~ VIN ~ 2V
VOUT =OV

••
•
••
•

Positive
Negative

•••
•
•

2.4
-15
2.4
-10

8.6
-7,0
8
1.0
1,5
0.2
1.4
1.4
1.4
1.4

17
10

0.8
80
0.8
500

130
5.0
2

7.5
-6.3
1.4
1.4
5
±17

V
V
rnA

IJA

rnA
rns
V
V

IJA
V
V

IJA
kHz

-5.0
0.8
20

V
V
V

IJA
rnA

5-19

LT1537
ELECTRICAL CHARACTERISTICS
PARAMETER
I CONDITIONS
Any Driver
Output Leakage Current
Data Rate
Slew Rate
Propagation Delay

Any Reeeiver
Input Voltage Thresholds
Hysteresis
Input Resistance
Output Voltage
Output Leakage Current
Output Shori-Circuit Current
Propagation Delay

(Note 2)
MIN

•

Shutdown VOUT =±15V (Note 4)
RL =3k, CL =2500pF
RL =3k, CL =1000pF
RL =3k, CL =51pF
. RL =3k, CL =2500pF
Output Transition tHL HIGH to LOW (Note 5)
Output Transition tLH LOW to HIGH

••
•
••
•

VIN =±10V
Output LOW, lOUT =-1.6mA
Output HIGH, lOUT =160J,IA (Vee =5V)
Shutdown (Note 4) 0 S VOUT s Vce
Sinking Current, VOUT =Vee
Sourcing Current, VOUT =OV
Output Transition IHL HIGH to LOW (Note 6)
Output Transition tLH LOW to HIGH

The. denotes specifications which apply over the operating temperature
range (O°C s TA S 70°C for commercial grade and -40°C s TAs 85°C for
industrial grade).
Nole 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Nole 2: Testing done at Vec =5Vand VON/OFF =3V. C1 =C2 =0.2~,
C+ = C- = 0.1~.
Nole 3: Supply current is measured with driver and receiver outputs
unloaded and the driver inputs tied high.
Nole 4: Supply current and leakage current measurements in shutdown
are performed with VON/OFF = 0.1V. Supply current measurements using
DRIVER DISABLE are performed with VDRIVER DISABLE = 3V.

MAX

UNITS

10

100

J,IA
kBaud
kBaud

15
15
0.6
0.5

30

VI',lS
VI',lS
',lS
',lS

120
250
4

Input LOW Threshold (VOUT =HIGH)
Input HIGH Threshold (VOUT =LOW)

TYP

0.8

1.3
1.7
0.4
5
0.2
4.2
1
-20
20
250
350

0.1
3
3.5

10

1.3
1.3

V
V
V
kn
V
V
J,IA
rnA
rnA
ns
ns

2.4
1.0
7
0.4
10
-10
600
600

Nole 5: For driver delay measurements, RL = 3k and CL = 51 pF. Trigger
pOints are set between the driver's input logic threshold and the output
transition to the zero crossing (tHL = 1.4V to OV and tLH = 1.4V to OV).
Nole 6: For receiver delay measurements, CL = 51 pF. Trigger pOints are set
between the receiver's input logic threshold and the output transition to
standard nUCMOS logic threshold (tHL =1.3V to 2.4V and tLH =1.7V to
0.8V).
Nole 7: Absolute maximum externally applied voltage. Internal charge
pump may force a larger value on this pin.

TYPICAL PERFORmAnCE CHARACTERISTICS
Driver Output Voltage

Receiver Input Thresholds

2:6~~~

2: 2.50

~
~

2.25
i:i 2.00

w

5

4

I--+---t-+0 I--+-I--+---tl--+-I---I

2

o~ -2
~ -4

~ -6~=F==F=~~~~~~~
-8 f---+--f-

-10 L..---'--_L..---'----''----'--_'--.....I
-50 -25 a 25 50 75 100 125
TEMPERATURE ('e)

Supply Current vs Data Rate

3.00
2.75

80

3DRIVERS ACTIVE
70 f-RL=3k
eL =2500pF
<" 60
50

.§.

w

co

~1.75
....

a:
a:
::>
<>

::J:

>-1:00
0.75
0.50
-55 -25

40

0..

::>

INPUTL6w

'"

./"

20

/'

V

10
0 25 50 75
TEMPERATURE ('e)

100 125
ILT1537-TPC02

5-20

. /V

::;
30
0..

~1.50

'"~ 1.25

,./

~

INPUTHIGH

o

o

~

M ~ 100
DATA RATE (kBAUD)

1~

1M

LTXl531'TPCOS

LT1537
TYPICAL PERFORmAnCE CHARACTERISTICS
Positive Supply Output
Compliance Curve

-

10
~

::;
"::;

r--- r--

-

Negative Supply Output
Compliance Curve

Driver Disable Threshold

-10

i--

3.0

~ -8

:=:::>

o

""-~

~

-6

""-

"-

:::>

".u

en

:I)

~

::

2.5

-

~

~
~ 2.0

~
g
9o

-4

o

o

o

15

5
10
POSITIVE LOAD CURRENT (rnA)

l-I -

:I:

I-..

~

zffl -2

""-

-

I --...... r-

~ 1.0

~

:n

1.5

0.5

o

10
NEGATIVE LOAD CURRENT (rnA)

o

15

-55 -25

0
25
50
75
TEMPERATURE (0G)

100

125

LT1537'TPC04

On/Off Thresholds

Supply Current

3.0
2.5
2.0
1.5

40
35

-...... r-....
...........

30
25

3 DRIVERS LOA~ED R~ =3k

....~

0

20

2

DIRIVER~ LOADED RL =3k

a:
a:

~

15

1

DIRIVER~ LOAbED R~ ~

:;;0-

..........

1.0

20klBAUD

.§.

""
r--

w

~N

"""-

'"~

THRESHOLD

..........

>

r-......

""-

"-

:::>

OFF THRESHOLD ~

Driver Leakage in Shutdown
100

en

10

NO LOAD

o

--55 -25

:::>

1/

<.:>

w

VqUT=l~~~~

'";:2

VOUT= 15V

~

./

0.5

10

i'i'i

/
0
25
50
75
TEMPERATURE (OC)

100

o

-55 -25

125

0
25
50
75
TEMPERATURE (0G)

100

0.1

125

II
-55 -25

25 50
75
TEMPERATURE (OC)

100

125

LT1537·TPCOJl

Driver Output Short-Circuit Current

Receiver Short-Circuit Current
30

30
:;;0-

.§.

25

....

i'i'i 20

-

I~c+

............

a:
a:

:::>
<.:>

....

:5
a:
C3
>'a:

15

:;;0- 25
.§.
....z
w 20

..........

~ '-...

<.:>

a:
a:

:::>
<.:>

.........

....

.............

10

0

:5
a:
C3
>'a:

15

<.:>

-,..,

...........

---

10

-

.........

ISC+

r---....
IS?-

i'--

0
:I:

:I:

en

--

en

o

--55 -25

0
25 50
75
TEMPERATURE (OC)

100

125

o

-55 -25

0
25 50
75
TEMPERATURE (OC)

100

125

LTl531·TPC11

.L7lJ!J~

5-21

LT1537
TYPICAL PERFORmAnCE CHARACTERISTICS
Driver Output Waveforms

Shutdown to Driver Output
DRIVER
OUTPUT HIGH
Rl=3k

DRIVER OUTPUT
Rl =3k

10

5
DRIVER OUTPUT
Rl =3k
Cl = 2500pF
INPUT

ON/OFF PIN

LT1537·TPC12

Ln587'TPC13

Pin FunCTions
Yee: 5V Input Supply Pin. Supply current drops to zero in
the shutdown mode. This pin should be decoupled with a
0.1 J,lf ceramic capacitor close to the package pin. Insufficientsupply bypassing can result in low output drive levels
and erratic charge pump operation.
GND: Ground Pin.
ON/OFF: TTUCMOS Compatible Operating Mode Control.
A logic LOW puts the device in the shutdown mode which
reduces input supply current to zero and places all of the
drivers and receivers in high impedance state. A logic
HIGH fully enables the transceiver.
DRIYER DISABLE: This pin provides an alternate control
for the charge pump and RS232 drivers. A logic HIGH on
this pin shuts down the charge pump and places all drivers
in a high impedance state. Receivers remain active under
these conditions. Floating the driver disable pin or driving
itto alogic LOW level fully enables the transceiver. Alogic
LOW on the On/Off pin supersedes the state of the Driver
Disable pin. Supply current drops to 1.5mA when in
DRIVER DISABLE mode.
Y+: Positive Supply Output (RS232 Drivers). V+ "" 2Vee1.5V. This pin requires an external charge storage capacitor C:2: 0.1 J,lf, tied to ground or Vee. Larger value capacitors may be used to reduce supply ripple. With multiple
transceivers, the V+ and V- pins may be paralleled into
common capacitors. For large numbers of transceivers,
increasing the size ofthe shared common storage capacitors is recommended to reduce ripple.

5-22

Y-: Negative Supply Output (RS232 Drivers). V- ""
-(2Vee - 2.5V). This pin requires an external charge
storage capacitor C:2: 0.1 J,lf. V- is short-circuit proof for
30 seconds.

C1+, C1-, C2+, C2-: Commutating Capacitor Inputs. These
pins require two external capacitors C:2: 0.2J,lf: one from
C1+ to C1- and another from C2+ to C2-. To maintain
charge pump efficiency, the capacitor's effective series
resistance should be less than 20. Low ESR ceramic
capacitors work well in this application.
DRIYER IN: RS232 Driver Input Pins. These inputs are
TTUCMOS compatible. Inputs should not tie allowed to
float. Tie unused inputs to Vec.
DRIYER OUT: Driver Outputs at RS232 Voltage Levels.
Driver output swing meets RS232 levels for loads up to 3k.
Slew rates are controlled for lightly loaded lines. Output
current capability is sufficient for load conditions up to
2500pF. Outputs are in a high impedance state when in
shutdown mode, Vcc = OV or when the driver disable pin
is active. Outputs are fully short-circuit protected from V+ 25V to V+ - 25V. Applying higher voltages will not
damage the device if the overdrive is moderately current
limited. Short circuits on one output can load the power
supply generator and may disrupt the signal levels of the
other outputs. The driver outputs are protected against
ESD to ±5kV for human body model discharges.

LT1537
~In

FunCTions

RX IN: Receiver Inputs. These pins accept RS232 level
signals (±25V) into a protected 5k terminating resistor.
The receiver inputs are protected against ESO to ±5kV for
human body model discharges. Each receiver provides
O.4V of hysteresis for noise immunity. Open receiver
inputs assume a logic low state.

RX OUT: Receiver Outputs with TTL/CMOS Voltage Levels. Outputs are in a high impedance state when in shutdown mode to allow data line sharing. Outputs are fully
short-circuit protected to ground or Vee with the power
on, off, or in shutdown mode.

ESD PROTECTiOn
rhe RS232 line inputs ofthe LT1537 have on-chip protec'ion from ESO transients up to ±5kV during shutdown or
lower ON state. The protection structures actto divert the
)tatic discharge safely to system ground. In order for the
:SO protection to function effectively, the power supply
md ground pins of the LT1537 must be connected to
Jround through low impedances. The power supply
jecoupling capacitors and charge pump storage capaci:ors provide this low impedance in normal application of
:he circuit. The only constraint is that low ESR capacitors
Tlust be used for bypassing and charge storage. ESO
:esting must be done with pins Vee, V+, V- and GNO
)horted to ground or connected with low ESR capacitors.

ESD Test Circuit

RS232
LINE PINS
PROTECTED
TO ±5kV

I

1

rYPICAl APPLICATiOnS
LT1537 Driving Remote Powered LTC1382
..----1 Vee

ON/OFF = 5V

":'"

LT1531·TA03

5-23

LT1537
TYPICAL APPLICATions
Typical Mouse Driving Application

I------------------~I
MOUSE

I
I
I
I
I
I
I
I
I
I
I

,;;;;;....;....~....;;.;..-.-

.:;::...===:..-_

LOGIC "0'
LOGIC "0"

.;;.;.....=;..;.;;.'---- MOUSE DATA
..;,;;...;;;.;;,;.;;;;..;.;;;:..-- LOGIC "1"

I

:

(5)

(9)

I

lL~------} 1
'::"

DB9

'::"

LT1137AoTA114

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1137A

5V 3-Driver/5-Receiver RS232 Transceiver with Shutdown

Premium Performance Upgrade to LT1537

LT1138A
LT1237

5V 5-Driver/3-Receiver RS232 Transceiver

Premium Performance DCE, Compliment to LT1537
Lower Power, Premium Performance Upgrade to LT1537

LT1330

5V 3-Driverl5-Receiver RS232 Transceiver with 3V
Logic Interface and Shutdown

Premium Performance Device for 5V Systems with 3V Logic Supplies

LT1331

5V 3-Driver/5-Receiver RS232 Transceiver with 3V
Logic Interface and Receiver Active in Shutdown

LT1330 with Low Power Receiver That Stays Active During Shutdown

LTC1337

Ultra-Low Power 5V 3-Driver/5-Receiver RS232
Transceiver with Shutdown
5V 5-Driver/3-Receiver RS232 Transceiver with Shutdown

Ultra-Low Power, Premium Performance Upgrade to LT1537

LTC1338

5-24

5V 3-Driver/5-Receiver RS232 Transceiver with One
Receiver Active in Shutdown

Ultra-Low Power, Peripheral-Side Compliment to LT1537

INDEX
SECTION 5-INTERFACE
RS485
LTC1480,
LTC1481,
LTC1483,
LTC1487,

3.3V Ultra-Low Power RS485 Transceiver .......................................................................... 5-26
Ultra-Low Power RS485 Transceiver with Shutdown .............................................................. 5-34
Ultra-Low Power RS485 Low EMI Transceiver with Shutdown ................................................... 5-41
Ultra-Low Power RS485 with Low EMI, Shutdown and High Input Impedance ................................ 5-49

•

5-25

~7~JD~~fY'~----3-.3-V-U-I-tra-_-L-o-:_T~-O-1:_:_~
Transceiver
RS485

FEATURES

DESCRIPTion

•
•
•
•
•

The LTC®1480 is an ultra-low power differential line transceiver which provides full RS485 compatibility while operating from a single 3.3V supply. It is designed for data
transmission standard RS485 applications with extended
common-mode range (12V to -7V). It also meets the
requirements of RS422 and features high speed operation
up to 2.5Mb/s. The CMOS design offers significant power
savings without sacrificing ruggedness against overload
or ESD damage. Typical quiescent current is only 300IJA
while operating and 1IJA in shutdown.

•
•
•

True RS485 from a Single 3.3V Supply
low Power: Icc = 500~ Max with Driver Disabled
Icc =600f.lA Max with Driver Enabled, No load
1f.lA Quiescent in Shutdown Mode
ESD Protection to ±10kV on Receiver Inputs and
Driver Outputs
-7V to 12V Common-Mode Range Permits ±7V
Ground Difference Between Devices on the Data Line
Thermal Shutdown Protection
Power Up/Down Glitch-Free Driver Outputs Permit
Live Insertion or Removal of Transceiver
Driver Maintains High Impedance in Three-State or
with the Power Off
Up to 32 Transceivers on the Bus
50ns Typical Driver Propagation Delays with
10ns Skew
Pin Compatible with the LTC485

APPLICATions

The driver and receiver feature three-state outputs, with
the driver outputs maintaining high impedance over the
entire common-mode range. Excessive power dissipation
caused by bus contention or faults is prevented by a
thermal shutdown circuit which forces the driver outputs
into a high impedance state. The receiver has a fail-safe
feature which guarantees a high output state when the
inputs are left open. I/O pins are protected against multiple
ESD strikes of up to ±10kV.

• Battery-Powered RS485/RS422 Applications
• Low Power RS485/RS422 Transceiver
• Level Translator

The LTC1480 is fully specified over the commercial and
extended industrial temperature range. The LTC1480 is
available in 8-pin SO and DIP packages.

•
•
•
•

LT, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Driver Differential
Output Voltage vs Output Current

3.3V RS485 Network

3.5

Vee = 3.3V
3.0

RO

HE

~

DE

DE

~
~ 2.0

01

01

HE

2.5

1"r......

1"'-

0

> 1.5

~

'"
0

"-

1.0
0.5

a

5-26

TA = 25'C

o

10

'"

'\

20 30 40 50 60 70
OUTPUT CURRENT (mA)

80

90

LTC1480
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

(Note 1)

Supply Voltage (Vee) ................................................ 7V
Control Input Voltage ..................... -0.3V to Vee + 0.3V
Driver Input Voltage ....................... -0.3V to Vee + 0.3V
Driver Output Voltage ........................................... ±14V
Receiver Input Voltage .......................................... ±14V
Receiver Output Voltage ................ -0.3V to Vee + 0.3V
Operating Temperature Range
LTC1480C ........................................ O°C:s; TA:S; 70°C
LTC14801.... .......... ...................... -40°C:s; TA:s; 85°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

ELECTRICAL CHARACTERISTICS
VOD1

SYMBOL

PARAMETER
Differential Driver Output Voltage (Unloaded)

VOD2

Differential Driver Output Voltage (with Load)

INoD

Change in Magnitude of Driver Differential Output
Voltage for Complementary Output States

TOP VIEW

N8 PACKAGE
8-LEAD PDlP

S8 PACKAGE
8-LEAD PLASTIC SO

TJMAX= 125°C. 9JA= 130°C/W (N8)
TJMAX =125°C. 9JA= 150°C/W (S8)
Consult factory for Military grade parts.

Vee =3.3V (Notes 2, 3)
MIN

CONOITIONS
10= OV
R= 27n (RS485), Figure 1
R= son (RS422)

•
•
•

R= 27n or R= son, Figure 1

•
•

Driver Common-Mode Output Voltage

R= 27n or R= son, Figure 1

Change in Magnitude of Driver Common-Mode
Output Voltage for Complementary Output States

R = 27n or R= son, Figure 1

•

VIH

Input HIGH Voltage

DE, 01, RE

VIL

Input LOW Voltage

DE, 01, RE

IIN1

Input Current

DE, 01, RE

•
•

IIN2

Input Current (A, B)

DE = 0, Vcc = OV or 3.6V, VIN = 12V
DE = 0, Vcc = OV or 3.6V, VIN =-lV

VTH
LiVTH

Differential Input Threshold Voltage for Receiver

-7V ~VCM ~ 12V

Receiver Input Hysteresis

VOH

Receiver Output HIGH Voltage

VCM = OV
10 = -4mA, VID = 200mV

VOL

Receiver Output LOW Voltage

10 = 4mA, VID = - 200mV

10ZR

Three-State (High Impedance) Output
Current at Receiver

Vcc = Max, O.4V ~ Vo ~ 2.4V

RIN

Receiver Input Resistance
Supply Current

-7V ~ VCM ~ 12V
No Load, Output Enabled
No Load, Output Disabled

Voc
LiIVocl

Icc
ISHDN

Supply Current in Shutdown Mode

DE = 0, RE = Vcc

IOSD1

Driver Short-Circuit Current, VOUT = HIGH

-7V~Vo~12V

10802

Driver Short-Circuit Current, VOUT = LOW
Receiver Short-Circuit Current

-7V~Vo~12V

10SR

ORDER PART
NUMBER
LTC1480CN8
LTC1480lN8
LTC1480CS8
LTC1480lS8
S8 PART MARKING
1480
14801

OV ~ Vo ~ Vcc

•
••
•
•
•
•
•
•

MAX
3.3

1.5
2.0

UNITS
V

3.3

V
V

0.2

V

2

V

0.2

V
V

2

-0.2

0.8

V

±2

IlA

1.0
-0.8

rnA
rnA

0.2

V
mV

70

V

2
0.4

V

±1

IlA
kn

12

10

IlA
IlA
IlA

35

250

rnA

35

250

rnA

7

85

rnA

400
300

•
•
•
•

TYP

1

600
500

5-27

LTC1480
SWITCHinG CHARACTERISTICS
SYMBOL

PARAMETER
Driver Input to Output

tplH

Vee = 3.3V (Notes 2,3)

CONDITIONS

•

RDiFF = 540, Cll = Cl2 = 100pF,
(Figures 3 and 5)

MIN
25

TYP
50

MAX
80

UNITS
ns

25
50
80
•
10
20
tSKEW
• 5
15
40
tR, tF
•
Driver Enable to Output HIGH
Cl = 100pF (Figures 4,6), S2 Closed
70
120
ns
tZH
•
Driver Enable to Output LOW
Cl = 1OOpF (Figures 4, 6), S1 Closed
70
120
ns
tZl
•
Driver Disable Time from LOW
Cl = 15pF (Figures 4, 6), S1 Closed
70
120
ns
ILl
•
Driver Disable Time from HIGH
Cl = 15pF (Figures 4,6), S2 Closed
70
120
ns
tHZ
• 30 140 200
Receiver Input to Output
ns
tplH
RDiFF = 540, Cll = Cl2 = 100pF,
•
(Figure 3, 7)
Receiver Input to Output
ns
tpHl
• 30 14013 200
ItplH - tpHl I Differential Receiver Skew
ns
tSKD
Receiver
Enable
to
Output
LOW
CRl
=
15pF
(Figures
2,
8),
S1
Closed
50
80
ns
tZl
•
Receiver Enable to Output HIGH
CRl = 15pF (Figures 2, 8), S2 Closed
50
80
ns
tZH
•
Receiver Disable from LOW
CRl = 15pF (Figures 2, 8), S1 Closed
50
80
ns
tLl
•
Receiver Disable from HIGH
CRl = 15pF (Figures 2, 8), S2 Closed
50
80
ns
tHZ
• 2.5
Maximum Data Rate
MbitS/s
fMAX
• 50 200 600 ns
Time to Shutdown
DE=O, RE=S
tSHDN
•
Cl = 1OOpF (Figures 4, 6), S2 Closed
70
120
ns
tZH(SHDN) Driver Enable from Shutdown to Output HIGH
•
Cl = 100pF (Figures 4, 6), S1 Closed
70
120
ns
tZl(SHDN) Driver Enable from Shutdown to Output LOW
•
4500
ns
tZH(SHDN) Receiver Enable from Shutdown to Output HIGH Cl = 15pF (Figures 2, 8), S2 Closed
•
Receiver
Enable
from
Shutdown
to
Output
LOW
Cl
=
15pF
(Figures
2,
8),
S1
Closed
4500
ns
tZl(SHDN)
•
The. denotes specifications which apply over the full operating
Note 2: All currents into device pins are positive; all currents out ot device
Driver Input to Output
Driver Output to Output
Driver Rise or Fall TIme

tpHl

temperature range.
Nole 1: Absolute maximum ratings are those beyond which the safety of
the device cannot be guaranteed.

pins are negative. All voltages are referenced to device ground unless
otherwise specified.
Note 3: All typicals are given for Vcc = 3.3V and TA= 25°C.

TYPICAL PERFORmAnCE CHARAOERISTICS
425.
400 to--.
_375
1. 350
!;;:

~ 325
Z5
300 .
~

150

"

THERMAL SHUTDOWN
,WITH DRIVER ENABLED - r-:-

a:

8:: 275

::::l

VJ

"" ...... r-...I
'\,L!J e-

1

Vc~ =3.3J

100 _ TA=25°C

1!;;:

/

50

V~G=3t

20(}
-50 -25

I""--- r--

-vT

0 25 50 75 100 125 150 175
TEMPERATURE (OC)

/

V

~

::::l

RL =loon

w

2.0

0

1.9

- ----

>

...J

-

-50
-100
-150

o 0.5

~ 1.8

,/

V

zw
a:

V

1.0 1.5 2.0 2.5
OUTPUT VOLTAGE (V)

it25

1.7
1.6

r- .......!!!-=54Q

Vcr3.3~

3.0

3.5

LT148D-TPC02

5-28

2.1
~

,//

~
a:

::::l

5

--

2.2

~

c.:>

o

250
225

l-

r- b., DR~ DlSABlE9--r

Driver Differential Output Voltage
vs Temperature

Driver Output Low/High Voltage
vs Output Current

Supply Current vs Temperature

1.5
-40 -20

0 20 40 60
TEMPERATURE (OC)

80

100

LTC1480·Tf'COS

LTC 1480
TYPICAL PERFORmAnCE CHARAOERISTICS
Receiver Output Low Voltage
vs Output Current

Driver Skew vs Temperature
7.0
6.5

I

25

I

20

;::

-

5.0
4.5

~

V

'" 5.5

:E

/

1/

a:
a:

5
~
o

3.5
0
20
40
60
TEMPERATURE (OC)

15

80

J

.1.

V

<" -12

!z

-10

§

-8

~

/'

V
V

t.J

/

~

-6

o

-4
-2

oV
o

o

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.B 2.0
OUTPUT VOLTAGE (V)

100

.1

Vee = 3.3V
-14 r-TA = 25°C
.§.

I
10

-16

f.--" ~

V
/

::J
t.J

4.0

3.0
-40 -20

LV

TA = 25°C

6.0

.s

V~e = k.3V I

_ Vee=3.3V

Receiver Output High Voltage
vs Output Current

V

V

V

3.30 3.05 2.80 2.55 2.30 2.05 1.BO 1.55 1.30
OUTPUT VOLTAGE (V)

lTC14SO·TPCIl5

Receiver ItpLH vs Temperature

tpHL

I

Receiver Output Low Voltage
vs Temperature

12

0.6

Vee l=3.3VI

1/

10

/
o

-40 -20

V

:;;~

~~
~

5
o

/
0
20
40
60
TEMPERATURE (OC)

3.0

J

Vee = 3.3V
0.5 r-1 =BmA

/
f'- V

I

0.4
0.3

V

Receiver Output High Voltage
vs Temperature

V

....V

""

1-'.

2.8
w

:i!
~

100

f'-.-

~

>-

~ 2.4

0.2

o

-40 -20

......

~~

~

o
2.2

0.1

80

2.6

ve6 =3.3V
l=BmA

0
20
40
60
TEMPERATURE (OC)

80

100

2.0
-40 -20

b...

0
20 40
60
TEMPERATURE (OC)

LTC141100TPC08

I'

BO

100

LTC1480-TPC09

Pin FunOlons
RO (Pin 1): Receiver Output. If the receiver output is
enabled (RE LOW) and A> B by 200mV, then RO will be
HIGH. If A < B by 200mV, then RO will be LOW.
RE (Pin 2): Receiver Output Enable. A LOW enables the
receiver output, RO. A HIGH input forces the receiver
output into a high impedance state.
DE (Pin 3): Driver Outputs Enable. A HIGH on DE enables
the driver output. A, B and the chip will function as a line
driver. A low input will force the driver outputs into a high
impedance ~ate and the chip will function as a line
receiver. If RE is high and DE is LOW, the part will enter a
low power (1!lA) shutdown state. If RE is low and DE is

..L7lJ!J~

high, the driver outputs will be fed back to the receiver and
the receive output will correspond to the driver input.
DI (Pin 4): Driver Input. If the driver outputs are enabled
(DE HIGH) then a low on DI forces the outputs A LOW and
BHIGH. AHIGH on DI with the driver outputs enabled will
force A HIGH and BLOW.
GND (Pin 5): Ground.
A (Pin 6): Driver OutpuVReceiver Input.
B (Pin 7): Driver OutpuVReceiver Input.
VCC (Pin 8): Positive Supply. 3.0V < Vee < 3.6V.

5-29

LTC 1480
FunCTion TABLES
LTC1480 Receiving

LTC1480 TransmUting

RE

INPUTS
DE

DI

B

1
1

1

a
X

X
X

a

a
a

1

OUTPUTS

X

A

RE

a

1

1

a

z
z·

Z
Z·

a
a
a

INPUTS
DE

a

~O.2V

1

0

~-O.2V

a

a

Inputs Open

1

X

z·

1
a
'Shutdown mode

'Shutdown mode

DUTPUTS
RD

A-B

TEST CIRCUITS

T

"::"

1k

CRl

S2 o---::J....

"':'"

LTC1480'Rll

Figure 1. Driver DC Test Load

"

~Vee

vae

R

B

I ~""'"'b

RECEIVER
OUTPUT

ATha
R a

":'"

LTC1480'F02

Figure 2. Receiver Timing Test Load

3V

5pF

rG

S1o--vee

RO
OUTPUT
UNDER TEST

5000

S2

T

Figure 3. Driver/Receiver Timing Test Circuit

Cl

*

Figure 4. Driver Timing Test Load

SWITCHinG TimE WAVEFORms
3V

f =1MHz,I,,; 10ns, If'; 10ns

1.5V

DI

1.5V

OV
8
A
Va
OV
-Va

IpHl

\_IPlH

7: -IX .

~tsKEW

1/2 Va

90%

10%
t,_

-

VDIFF =V(A) - V(8)

Figure 5. Driver Propagation Delays

5-30

f 'T

-I

~tSKEW
10%

LTCl480'F05

LTC1480
;WITCHlnG TimE WAVEFORms
3V
OE

OV
3.3V
A, B
VOL
VOH
A, B
OV

f = 1MHz, 1,$10ns, If $10ns

1.5V

-

ILZ-

IZl(SHDN), IZl

-

-

1.5V

t;

2.3V

OUTPUT NORMALLY LOW

1110.5V

2.3V

OUTPUT NORMALLY HIGH

0.5V

-

t::-

IHZ-

IZH SHDN ,IZH

LTC1480'FOS

Figure 6. Driver Enable and Disable Times

RO

VOH - - - - - - - - - - - .
' \ 1.5V

V::~

IPHl::11:=

A- B

5V

~=1MHZ,I,$10nS,lf$10nS

\OV

-VOD2

t·

OUTPUT

IPlH)_-----

INPUT

OV
LTCl480'FQ7

Figure 7. Receiver Propagation Delays
3V
OV
3.3V
RO

-

1.5V
-

OV

-

ILZ-

IZl(SHDN), IZl

r

1.5V

OUTPUT NORMALLY LOW

1110.5V

1.5V

OUTPUT NORMALLY HIGH

0.5V

VOH
RO

'l1.5V

t= 1MHz, 1,$10ns, If'; IOns

-

IHZ-

IZH SHDN , IZH

t::-

LTC1480'F08

Figure 8. Receiver Enable and Disable Times

IPPLICATlons InFORmATiOn

Vee

;MOS Output Driver
rhe LTC1480 transceiver provides full RS485 compatibilty while operating from a single 3.3V supply. The RS485
;pecification requires that a transceiver withstand comnon-mode voltages of up to 12V or -7V at the RS485 line
:onnections. Additionally, the transceiver must be imnune to both ESD and latch-up, This rules out traditional
;MOS drivers, which include parasitic diodes from their
Iriver outputs to each supply rail (Figure 9), The LTC1480
,ses a proprietary process enhancement which adds a
lair of Schottky diodes to the output stage (Figure 10),
lreventing current from flowing when the common-mode

Vee

P~

~
J=j

:i: 01

LOGIC

--~ OUTPUT

LOGIC

---I

:1: 02

N1

-=

LTC1480'F10

Figure 9. Conventional
CMDS Output Stage

Figure 10.
LTC1480 Output Stage

5-31

LTC 1480
APPLICATions InFoRmATion
voltage exceeds the supply rails. Latch-up at the output
drivers is virtually eliminated and the driver is prevented
from loading the line under RS485 specified fault conditions. A proprietary output protection structure protects
the transceiver line terminals against ESD strikes of up to
±10kV.
When two or more drivers are connected to the same
transmission line, a potential condition exists whereby
more than two drivers are simultaneously active. If one or
more drivers is sourcing current while another driver is
sinking current, excessive power dissipation may occur
within either the sourcing or sinking element. This condition is defined as driver contention, since multiple drivers
are competing for one transmission line. The LTC1480
provides a current limiting scheme to prevent driver
contention failure. When driver contention occurs, the
current drawn is limited to about 70mA preventing excessive power dissipation within the drivers.
The LTC1480 has a thermal shutdown feature which
protects the part from excessive power dissipation. Under
extreme fault conditions, up to 250mA can flow through
the part causing rapid internal temperature rise. The
thermal shutdown circuit will disable the driver outputs
when the internal temperature reaches 150°C and turns
them back on when the temperature cools to 130°C. This
cycle will repeat as necessary until the fault condition is

removed.
Receiver Inputs
The LTC1480 features an input common-mode range
covering the entire RS485 specified range of -7V to 12V.
Differential signals of greater than ±200mV within the
specified input common-mode range will be converted to
a TTL compatible signal at the receiver output. A small
amount of input hysteresis is included to minimize the
effects of noise on the line signals.lfthe receiver inputs are
floating (unterminated) an internal pull-up of 1OI!A at the
Ainput will force the receiver outputto aknown high state.

Low Power Operation
The LTC1480 draws very little supply current whenever
the driver outputs are disabled. In shutdown mode the
quiescent current is typically less than 11!A. With the

5-32

receiver active and the driver outputs disabled, the LTC1480
will typically draw 3001!A quiescent current. With the
driver outputs enabled but unterminated, quiescent current will rise as one of the two outputs sources current into
the internal receiver input resistance. With the minimum
receiver input resistance of 12k and the maximum output
swing of 3.3V, the quiescent current will rise by a maximum of 2751!A. Typical quiescent current rise with the
driver enabled is about 1001!A.
The quiescent current rises significantly if the driver is
enabled when it is externally terminated. With 1/2 termination load (1200. between the driver outputs) the quiescent
current will jump to at least 13mA as the drivers force a
minimum of 1.5V across the termination resistance. With
a fully terminated 600. line attached, the current will rise
to greater than 25mA with the driver enabled, completely
overshadowing the extra 1OOI!A drawn by internal receiver
inputs.

Shutdown Mode
Both the receiver output (RO) and the driver outputs (A, B)
can be placed in three-state mode by bringing RE HIGH
and DE LOW respectively. In addition, the LTC1480 will
enter shutdown mode when RE is HIGH and DE is LOW.
In shutdown the LTC1480 typically draws only 11!A of
supply current. In order to guarantee that the part goes
into shutdown, RE must be high and DE must be LOW for
at least 600ns simultaneously. If this time duration is less
than 50ns the part will not enter shutdown mode.

Propagation Delay
Many digital encoding schemes are dependent upon the
difference in the propagation delay times of the driver and
receiver. Figure 11 shows the test circuit for the LTC1480
propagation delay.
The receiver delay times are:
ItpLH - tpHL I =13ns Typ, Vee =3.3V
The driver's skew times are:
tSKEW = 10ns Typ, Vee = 3.3V
20ns Max, Vee =3.3V, TA =-40°C to 85°C

LTC 1480
APPLICATions InFoRmATion
TIL IN

t"tf<6ns

~]

BR:19-- RECEIVER

vrL.___.......~O_OO_ _ _....I!

OUT
LTCl480-F11

*100 PF

Figure 11. Receiver Propagation Delay Test Circuit

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC485
LTC1481
LTC1483
LTC1485
LTC1487

5V Low Power RS485 Interface Transceiver
5V Ultra-Low Power RS485 Transceiver with Shutdown

Low power
Lowest power
Low EMl/lowest power
Highest speed

5V Ultra-Low Power RS485 Low EMI Transceiver with Shutdown
5V Differential Bus Transceiver
5V Ultra-Low Power RS485 with Low EMI Shutdown
and High Input Impendance

High input impendance/low EMI/lowest power

III

5-33

--L7~JD~~IY'III!--""----.-U-lt-ra-_l-o-W_Ll_p~_.~_4e....8!
RS485 Transceiver
with Shutdown
DESCRIPTion

FEATURES
•
•
•
•
•
•
•
•
•
•
•
•

Low Power: Icc = 120~ Max with Driver Disabled
Icc = 500~ Max with Driver Enabled, No Load
Drivers/Receivers Have ±10kV ESD Protection
1~ Quiescent Current in Shutdown Mode
High Speed: Up to 2.5Mbits/s Data Rate
Single 5V Supply
-7V to 12V Common-Mode Range Permits ±7V
Ground Difference Between Devices on the Data Line
Thermal Shutdown Protection
Power Up/Down Glitch-Free Driver Outputs Permit
Live Insertion or Removal of Transceiver
Driver Maintains High Impedance in Three-State
or with the Power Off
Up to 32 Transceivers on the Bus
30ns Typical Driver Propagation Delays
with 5ns Skew
Pin Compatible with the LTC485

The LTC@1481 is an ultra-low power differential line transceiver designed for data transmission standard RS485
applications. It will also meet the requirements of RS422.
The CMOS design offers significant power savings over its
bipolar counterparts without sacrificing ruggedness against
overload or ESD damage. Typical quiescent current is only
80~ while operating and less than 1~ in shutdown.
The driver and receiver feature three-state outputs, with
the driver outputs maintaining high impedance over the
entire common-mode range. Excessive power dissipation
caused by bus contention or faults is prevented by a
thermal shutdown circuit which forces the driver outputs
into a high impedance state. The receiver has a fail-safe
feature which guarantees a high output state when the
inputs are left open.

APPLICATiOnS

The LTC1481 is fully specified over the commercial and
extended industrial temperature range and is available in
8-pin DIP and SO packages.

• Battery-Powered RS485/RS422 Applications
• LowPower RS485/RS422 Transceiver
• Level Translator

D, LTC and LT are registered trademarks of Linear Technology Corporation.

•

TYPICAL APPLICATiOn

Supply Current vs Temperature
350

ROl

VCCl

300

REl-+.r--J~4~---....",........,

Rt

DE1--r----.,,------It+---........~...
OIl-,-~

1.... 250

~ 200

GND1

"

r--...

TH~RM1L

SJUTDhwN I
WIIH DRIVER ENABLEb -

.......
DRIVER ENABr;o-.

a::

~ ~-

:::>

Rt
R02

RE2-+.r--J"'~4~---+--......

GN02
lTC1481·TAOl

5-34

~ 100 I-- DRIVER DISABLED
50

DE2--r----.,,------It+---.....
OI2--r--t.,

~ 150

0-

VCC2

~-,-

r--.. r- ~

IY

o
-50 -25 0

25 50 75 100 125 150 175
TEMPERATURE (OC)

LTC1481
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

(Note 1)

Supply Voltage (Vee) .............................................. 12V
Control Input Voltage ..................... -O.5V to Vee + O.5V
Driver Input Voltage ....................... -O.5V to Vee + O.5V
Driver Output Voltage ........................................... ±14V
Receiver Input Voltage .......................................... ±14V
Receiver Output Voltage ................ -O.5V to Vee + O.5V
Operating Temperature Range
LTC1481 C........................................ O°C::; TA::; 70°C
LTC14811 .................................... -40°C::; TA::; 85°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER
LTC1481CN8
LTC14811N8
LTC1481CS8
LTC14811S8

TOPVIEW

N8 PACKAGE
HEAO PDIP

S8 PACKAGE
HEAD PLASTIC SO

TJMAX = 125'C, BJA = 130'C/W (N8)
TJMAX = 125'C, BJA = 150'C/W (S8)

S8 PART MARKING
1481
14811

Consult factory for Military grade parts,

ELECTRICAL CHARACTERISTICS

Vee = 5V (Notes 2, 3) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

V001

Differential Driver Output Voltage (Unloaded)

10 =a

VOD2

Differential Driver Output Voltage (with Load)

R =50n (RS422)
R =2m (RS485), Figure 1

LlVOD

Change in Magnitude of Driver Differential Output
Voltage for Complementary Output States

R =2m or R =50n, Figure 1

Voc

Driver Common-Mode Output Voltage

R =2m or R =50n, Figure 1

Lllvoel

Change in Magnitude of Driver Common-Mode
Output Voltage for Complementary Output States

R =2m or R =50n, Figure 1

VIH

Input High Voltage

DE, 01, RE

VIL

Input Low Voltage

DE, 01, RE

IIN1

Input Current

DE, 01, RE

IIN2

Input Current (A, 8)

DE =0, Vee =OVor 5.25V, VIN =12V
DE= 0, Vcc =OV or 5.25V, VIN =-7V

VTH

Differential Input Threshold Voltage for Receiver

-7V,,; VCM ,,;12V

LlVTH

Receiver Input Hysteresis

VCM =OV

VOH

Receiver Output High Voltage

10 =-4mA, VID =200mV

VOL

Receiver Output Low Voltage

10 =4mA, VID =-200mV

10ZR

Three-State (High Impedance) Output
Current at Receiver

Vcc =Max, OAV,,; Vo"; 2AV

RIN

Receiver Input Resistance

-7V,,;VCM,,;12V

Icc

Supply Current

No Load, Output Enabled
No Load, Output Disabled

ISHDN

Supply Current in Shutdown Mode

DE= 0, RE =Vcc

IOS01

Driver Short-Circuit Current, VOUT =HIGH

-7V,,;Vo,,;12V

IOS02

Driver Short-Circuit Current, VOUT =LOW

-7V,,;Vo ,,;12V

10SR

Receiver Short-Circuit Current

OV,,;Vo";Vee

MIN

•
•
•

TYP

2,0
1.5

•
•
•

•
•
•
•
•

MAX

UNITS

5

V

5

V
V

0.2

V

3

V

0.2

V
V

2
0.8

V

±2

!lA

1.0
-0,8

mA
mA

•
•
•
•
•

-0,2

•

12

10

•
•
•

!lA
!lA
!lA

35

250

mA

35

250

mA

7

85

mA

0.2

3,5

•
•

V
mV

45

V

OA

V

±1

!lA
kn

300
80
1

500
120

5-35

OIl

LTC1481
SWITCHinG CHARACTERISTICS

Vee =5V (Notes 2, 3) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

tpLH

Driver Input to Output

tpHL

Driver Input to Output

ROIFF =540, CL1 =CL2 =100pF,
(Figures 3, 5)

tSKEW
tr,t,

Driver Output to Output
Driver Rise or Fall Time

tZH

Driver Enable to Output High

CL =100pF (Figures 4, 6), S2 Closed

tZL

Driver Enable to Output Low

ILl

Driver Disable Time from Low

CL =100pF (Figures 4, 6), SI Closed
CL =15pF (Figures 4, 6), SI Closed

tHZ

Driver Disable Time from High

CL =15pF (Figures 4, 6), S2 Closed

tpLH

Receiver Input to Output

tpHL

Receiver Input to Output

RDIFF =540, CL1 =CL2 =100pF,
(Figures 3, 7)

tSKD

ItpLH - tpHL I Differential Receiver Skew

tZL

Receiver Enable to Output Low

CRL =15pF (Figures 2, 8), SI Closed

tZH

Receiver Enable to Output High

CRL =15pF (Figures 2, 8), S2 Closed

tLZ

Receiver Disable from Low

CRL =15pF (Figures 2, 8), SI Closed

tHZ

Receiver Disable from High

CRL =15pF (Figures 2, 8), S2 Closed

fMAX

Maximum Data Rate

tSHDN

Time to Shutdown

tZH(SHDN)

Driver Enable from Shutdown to Output High

DE =0, RE =S
CL =100pF (Figures 4, 6), S2 Closed

tZL(SHDN)
tZH(SHDN)

Driver Enable from Shutdown to Output Low

CL =100pF (Figures 4,6), SI Closed

Receiver Enable from Shutdown to Output High

CL =15pF (Figures 2, 8), S2 Closed

tZL(SHDN)

Receiver Enable from Shutdown to Output Low

CL =15pF (Figures 2, 8), SI Closed

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

MIN

TYP

MAX

10

30

60

ns

10

30

60

ns

5

10

ns

15

40

ns

40

70

ns

40
40

70
70

ns
ns

3

40

70

ns

30

140

200

ns

30

140

200

ns

13

ns

20

50

ns

20

50

ns

20

50

ns

20

50

ns
Mbits/s

200

600

ns

40

100

ns

40

100
3500

ns
ns

3500

ns

2.5
50

•

Nole 2: All currents into device pins are positive; all currents out at device
pins are negative. All voltages are referenced to device ground unless
..otherwise specified.
Nole 3: All typicals are given for Vcc = 5V and TA = 25°C.

The. denotes specifications which apply over the full operating
temperature range.
Nole 1: Absolute maximum ratings are those beyond which the safety of
the device cannot be guaranteed.

TYPICAL PERFORmAnCE CHARACTERISTICS
Driver Differential Output Voltage
vs Output Current
2.5

TA = 25'C
60

!

ffi

'"'"=>
0

f-

=>
Q.
f-

=>
0

.........

50

~

30

"

20
10

2.3

~

2.2

~

60

..........

<[

g

"""

ffi
'"'"=>

.........

1'-....

1.9

0

f-

3

=>
0

a

25

50

75

100

125

TEMPERATURE ('C)
1481 G01

I
II

40
30
20
10

1.6
1.5
-50 -25

50

7

=>
Q.

f-

1.8
2i 1.7

r\.
2

/

TA = 25'C

....... ~

It

\.

OUTPUT VOLTAGE M

5-36

2!:

70
RL=540_

=

'\.

2
3
OUTPUT VOLTAGE (V)

/

2.0

i

1.0

"50

---

75

.........

./

2.5

\

'\
1\

/

\

/

0.5

f--

100

o

125

-50 -25

TEMPERATURE (oC)

0

25

50

75

100

125

TEMPERATURE (oC)

Pin FunOlons
RO (Pin 1): Receiver Output. If the receiver output is
enabled (RE low), then if A>Bby 200mV, RO will be high.
If A < B by 200mV, then RO will be low.
RE (Pin 2): Receiver Output Enable. A low enables the
receiver output, RO. A high input forces the receiver
output into a high impedance state.
DE (Pin 3): Driver Outputs Enable. A high on DE enables
the driver output. A, B and the chip will function as a line
driver. Alow input will force the driver outputs into a high
impedance state and the chip will function as a line
receiver. If RE is high and DE is low, the part will enter alow
power (1!lA) shutdown state.

DI (Pin 4): Driver Input. If the driver outputs are enabled . . .
(DE high) then a low on 01 forces the outputs A low and B y
high. Ahigh on 01 with the driver outputs enabled will force
A high and Blow.
GND (Pin 5): Ground.
A (Pin 6): Driver Output/Receiver Input.
B (Pin 7): Driver Output/Receiver Input.
Vcc (Pin 8): Positive Supply. 4.7SV < Vee < S.2SV.

FunCTion TABLES
l TC1481 Receiving

l TC1481 Transmitting
INPUTS

INPUTS

OUTPUTS

OUTPUTS

RE

DE

01

B

A

RE

DE

A-B

X

1

1

0

1

1

1

1

0

0
0

0
Z
Z·

~-O.2V

0

0
X
X

0
0
0
0

~O.2V

X

0
0
0

1

'Shutdown mode for LTC1481

Z
Z·

1

RO

Inputs Open

1

X

Z·

'Shutdown mode for LTC1481

5-37

LTC1481
TEST CIRCUITS
RECEIVER
OUTPUT

A T h v aRD

Vae

R

B

":"
LTCl431'f(I1

Figure 1. Driver DC Test Load

Figure 2. Receiver Timing Tesl Load

rc.

3V

Slo---vee

sooa

OUTPUT
UNDER TEST

S2

'T' Cl
":"'

Figure 3. Driver/Receiver Timing Tesl Circuit

<>--:::L.

LTC1481'F04

"':'"

Figure 4. Driver Timing Test Load

SWITCHinG TimE WAVEFORms
3V-----------------,----------------------~

DI

ov
A

-----------l--'-:::1'·wt;:'~" """ " ...,".. '.'j'-.S-~----~I12::-:(::-a------~~
X~________________~X~__~,-------J
--J
112 Va

1.-1SKEW

VO~-----------------1~--------------------~

-Va ----------------=--.1'1
_______________I:::,O',:::.Y,..1f
. OV

1.-1SKEW

VDlFF =V(A) - V(B)

90%

1,-

LTC1481'F05

If

Figure 5. Driver Propagation Delays

3V
DE
OV

SV
A,B

--

Val

I.SV

- - IZl(SHDN), IZl

2.3V

OUTPUT NORMALLY LOW

2.3V

OUTPUT NORMALLY HIGH

VOH
A,B
OV

-

f = lMHz, I,,, IOns, If" IOns

- - IZH SHDN , tZH

I.SV
ILZ-

O.SV

O.SV
IHZ-

Figure 6. Driver Enable and Disable Times

5-38

r;:.

t:-

LTC1481'F06

LTC 1481
SWITCHinG TimE WAVEFORms

tv

VOH - - - - - - - - - - . .
RO

t

OUTPUT
VOL - - - - - - - - - - - - j : ' - - - - - =
5V . , ; ; , , ; , . . . - - - - - - '
f= lMHz, trs IOns, tIS IOns
tpHL
tpLH

VOD2 - - - - - - - - - - , .

A-8

OV
INPUT
-VOD2 - - - - - - - - - - ' - - - - - - - - - - - - '

OV

Figure 7. Receiver Propagation Delays

3V
OV

5V
RO

RO
OV

-

1.5V

1.5V

f = lMHz, tr S IOns, tl S IOns

r-- tZL(SHDN), tZL

tLZ-

1.5V

OUTPUT NORMALLY LOW

1.5V

OUTPUT NORMALLY HIGH

I+--- tZH (SHDN ) , tZH

c::-

0.5V

0.5V
tHZ-

t

LTC1481'FOB

Figure 8. Receiver Enable and Disable Times

APPLICATions InFORmATion
Basic Theory of Operation
Traditionally, RS485 transceivers have been designed
using bipolar technology because the common-mode
range of the device must extend beyond the supplies and
the device must be immune to ESO damage and latch-up.
Unfortunately, most bipolar devices draw a large amount
of supply current, which is unacceptable forthe numerous
applications that require low power consumption. The
LTC1481 is a CMOS RS485/RS422 transceiver which
features ultra-low power consumption without sacrificing
ESO and latch-up immunity.
The LTC1481 uses a proprietary driver output stage,
which allows acommon-mode range that extends beyond
the power supplies while virtually eliminating latch-up and
providing excellent ESO protection. Figure 9 shows the
LTC1481 output stage while Figure 10 shows a conventional CMOS output stage.
When the conventional CMOS output stage of Figure 10
enters a high impedance state, both the P-channel (P1)
and the N-channel (N1) are turned off. If the output is then
driven above Vce or below ground, the Pt/N -well diode

(01) or the Nt/P-substrate diode (02) respectively will
turn on and clamp the output to the supply. Thus, the
output stage is no longer in a high impedance state and is
not able to meetthe RS485 common-mode range requirement. In addition, the large amount of current flowing
through either diode will induce the well-known CMOS
latch-up condition, which could destroy the device.
The LTC1481 output stage of Figure 9 eliminates these
problems by adding two Schottky diodes, S03 and S04.
The Schottky diodes are fabricated by a proprietary modification to the standard N-well CMOS process. When the
output stage is operating normally, the Schottky diodes
are forward biased and have a small voltage drop across
them. When the output is in the high impedance state and
is driven above Vec or below ground, the parasitic diode
01 or 02 still turns on, butS03 orS04 will reverse bias and
prevent current from flowing into the N-well or the substrate. Thus the high impedance state is maintained even
with the output voltage beyond the supplies. With no
minority carrier current flowing into the N-well or substrate, latch-up is virtually eliminated under power-up or
power-down conditions.

5-39

LTC1481
APPLICATions InFoRmATion
Low Power Operation

t - - -.......-OUTPUT

LOGIC

The LTC1481 is designed to operate with a quiescent
current of 120J.IA max. With the driver in three-state,lee
will drop to this 120J.IA level. With the driver enabled there
will be additional current drawn by the internal 12k resistor. Under normal operating conditions this additional
current is overshadowed by the current drawn by the
external bus impedance.
Shutdown Mode

LTC1481·f09

Figure 9. LTC1481 Output Stage

Both the receiver output (RO) and the driver outputs (A, B)
can be placed in three-state mode by bringing RE high and
DE low respectively. In addition, the LTC1481 will enter
shutdown mode when RE is high and DE is low.
In shutdown the LTC1481 typically draws only 1J.IA of
supply current. In order to guarantee that the part goes
into shutdown, DE must be low and RE must be high for
at least 600ns simultaneously. If this time duration is less
than 50ns the part will not enter shutdown mode. Toggling
either RE or DE will wake the LTC1481 back up within
3.5JlS.

LOGIC

OUTPUT

Propagation Delay
Many digital encoding schemes are dependent upon the
difference in the propagation delay times of the driver and
receiver. Figure 11 shows the test circuit for the LTC1481
propagation delay.

Figure 10. Conventional CMOS Output Stage

The LTC1481 output stage will maintain ahigh impedance
state until the breakdown of the N-channel or P-channel is
reached when going positive or negative respectively. The
output will be clamped to either Vee or ground by a Zener
voltage plus aSchottky diode drop, but this voltage is well
beyond the RS485 operating range. Because the ESD
injected current in the N-well or substrate consists of
majority carriers, latch-Up is prevented by careful layout
techniques. An ESD cell protects output against multiple
10kV human body model ESD strikes.

The receiver delay times are:
itpLH -tpHLi =13ns Typ, Vee =5V
The drivers skew times are:
Skew =5ns Typ, Vee =5V
10ns Max, Vee =5V, TA =-40°C to 85°C

TTLIN-f;;'S

I r• If< 6ns

l

~~~~EIVER

'1'--__. . . .~4_n. _ _----'!

lTCi481'fl1

~100PF

Figure 11. Receiver Propagation Delay Test Circuit

5-40

''''''''''-uneJ\Q
~,

LTC1483
TECHNOLOGY Ultra-Low Power RS485 Low EMI
Transceiver with Shutdown
DESCRIPTion

FEATURES
•
•
•
•
•
•
•
•
•
•
•
•

Low Power: Icc =120/lA Max with Driver Disabled
Icc =5001JA Max with Driver Enabled, No Load
1/lA Quiescent Current in Shutdown Mode
Controlled Slew Rate Driver for Reduced EMI
Single 5V Supply
Drivers/Receivers Have ±10kV ESD Protection
- 7V to 12V Common-Mode Range Permits ±7V
Ground Difference Between Devices on the Data Line
Thermal Shutdown Protection
Power Up/Down Glitch-Free Driver Outputs Permit
Live Insertion or Removal of Transceiver
Driver Maintains High Impedance in Three-State
or with the Power Off
Up to 32 Transceivers on the Bus
Pin Compatible with the LTC485

APPLICATions
• Battery-Powered RS485/RS422 Applications
• Low Power RS485/RS422 Transceiver
• Level Translator

The LTC®1483 is an ultra-low power differential line transceiver deSigned for data transmission standard RS485
applications with extended common-mode range (-7V to
12V). It will also meet the requirements of RS422. The
LTC1483 featu res output drivers with controlled slew rate,
decreasing the EMI radiated from the RS485 lines, and
improving signal fidelity with misterminated lines. The
CMOS design offers significant power savings over its
bipolar counterparts without sacrificing rugged ness against
overload or ESD damage. Typical quiescent current is only
801JA while operating and less than 11JA in shutdown.
The driver and receiver feature three-state outputs, with
the driver outputs maintaining high impedance over the
entire common-mode range. Excessive power dissipation
caused by bus contention or faults is prevented by a
thermal shutdown circuit which forces the driver outputs . .
into a high impedance state. The receiver has a fail-safe ~
feature which guarantees a high output state when the
inputs are left open. I/O pins are protected against multiple
ESD strikes of over ±1 OkV.
The LTC1483 is fully specified over the commercial and
extended industrial temperature range and is available in
8-pin DIP and SO packages.
D. LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
ROI

VCC1

REI

RTERM

OEI
011

01

GNOI

A-B
R02

RTERM
VCC2

RE2
RO

OE2
012

GN02
LTC14B3oTAOl

5-41

LTC1483
ABSOLUTE mAXimum RATinGS
(Note 1)

PACKAGE/ORDER InFORmATiOn

Supply Voltage (Vee) .............................................. 12V
Control Input Voltage ..................... -0.5V to Vee + 0.5V
Driver Input Voltage ....................... -0.5V to Vee + 0.5V
Driver Output Voltage ........................................... ±14V
Receiver Input Voltage .......................................... ±14V
Receiver Output Voltage ................ -0.5V to Vee + 0.5V
Operating Temperature Range
LTC1483C ........................................ O°C::; TA::; 70°C
LTC14831 .................................... -40°C::; TA ::; 85°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER
LTC1483CN8
LTC14831N8
LTC1483CS8
LTC14831S8

TOP VIEW

NB PACKAGE
B·LEAD PDIP

SB PACKAGE
B·LEAD PLASTIC SO

TJMAX =125"C, 9JA= 130"C/W (NB)
TJMAX= 125"C, 9JA= 150"C/W (SB)

S8 PART MARKING
1483
14831

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

Vee =5V, (Notes 2,3) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

VOD1

Differential Driver Output Voltage (Unloaded)

VOD2

Differential Driver Output Voltage (with Load)

10 =0
R=50n (RS422)
R=270 (RS485), Figure 1

Change in Magnitude of Driver Differential Output
Voltage for Complementary Output States
Driver Common-Mode Output Voltage

R=270 or R =50n, Figure 1

Change in Magnitude of Driver Common-Mode
Output Voltage for Complementary Output States

R=270 or R =50n, Figure 1
DE, DI, RE

VIL

Input High Voltage
Input Low Voltage

IIN1

Input Current

DE, DI, RE

IIN2

Input Current (A, B)

DE =0, Vcc =OVor 5.25V, VIN =12V
DE =0, Vee =OV or 5.25V, VIN =-7V

dVOD
Voc
divoci
VIH

R=270 or R=50n, Figure 1

DE, DI, RE

VTH

Differential Input Threshold Voltage for Receiver

-7V:s; VCM:S; 12V

dVTH

Receiver Input Hysteresis

VOH

Receiver Output High Voltage

VeM =OV
10 =-4mA, VID =200mV

VOL

Receiver Output Low Voltage

10 =4mA, VID =-200mV

10ZR

Three-State (High Impedance) Output
Current at Receiver

Vee =Max, O.4V:s; Vo :s; 2.4V

RIN

Receiver Input Resistance

-7V:s;VCM:S;12V

lee

Supply Current

No Load, Output Enabled
No Load, Output Disabled

ISHDN

Supply Current in Shutdown Mode

10S01

Driver Short-Circuit Current, VOUT =HIGH

DE =0, RE =Vee
-7V:s;Vo:s;12V

IOSD2

Driver Short-Circuit Current, VOUT =LOW

-7V:s; Vo:S; 12V

10SR

Receiver Short-Circuit Current

OV:s; Vo:S; Vee

5-42

MIN

•
•
•
•
•
•

•

TYP

5
2
1.5

5
0.2

-0.2

•
•
•

12

•

35

•
•

V
V
V

3

V
V
V

0.8

•
•
•
•
•

UNITS
V

0.2
2

•
•

••

MAX

V

±2

~

1.0
-0.8

mA
mA

0.2
45

V
mV

3.5

V
0.4

V

±1

~

25

kn
500
120

~
~

10
250

~
mA

35

250

mA

7

85

mA

300
80
1

LTC1483
SWITCHinG CHARACTERISTICS

Vee =5V, (Notes 2,3) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

tpLH

Driver Input to Output

tpHL

Driver Input to Output

RDIFF = 540, CL1
(Figures 3, 5)

tSKEW

Driver Output to Output

tr,tf

Driver Rise or Fall Time

tZH

Driver Enable to Output High

CL = 100~;: (Figures 4, 6), S2 Closed

tZL

Driver Enable to Output Low

CL = 1OOpF (Figures 4, 6), S1 Closed

tLZ

Driver Disable Time from Low

CL = 15pF (Figures 4, 6), S1 Closed

tHZ

Driver Disable Time from High

CL = 15pF (Figures 4, 6), S2 Closed

tpLH

Receiver Input to Output

tpHL

Receiver Input to Output

RDIFF = 540, CL1 = CL2 = 100pF,
(Figures 3, 7)

tSKD

ItpLH - tpHL I Differential Receiver Skew

tZL

Receiver Enable to Output Low

CRL = 15pF (Figures 2, 8), S1 Closed

tZH

Receiver Enable to Output High

CRL = 15pF (Figures 2, 8), S2 Closed

tLZ

Receiver Disable from Low

tHZ

Receiver Disable from High

CRL = 15pF (Figures 2, 8), S1 Closed
CRL = 15pF (Figures 2, 8), S2 Closed

fMAX

Maximum Data Rate

tSHDN

Time to Shutdown

DE=O, RE= S

tZH(SHDN)

Driver Enable from Shutdown to Output High

CL = 1OOpF (Figures 4, 6), S2 Closed

tZL(SHDN)

Driver Enable from Shutdown to Output Low

CL = 1OOpF (Figures 4, 6), S1 Closed

tZH(SHDN)

Receiver Enable from Shutdown to Output High

CL = 15pF (Figures 2, 8), S2 Closed

tZL(SHDN)

Receiver Enable from Shutdown to Output Low

CL = 15pF (Figures 2, 8), S1 Closed

LTC1483
TYP

MIN
=

•

CLF 100pF,

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

MAX

UNITS

150

1200

ns

150

1200

ns

600

ns

150

1200

ns

100

1500

ns

100

1500

ns

150

1500

ns

150

1500

ns

100

30

140

200

ns

30

140

200

ns

13

ns

20

50

ns

20

50

ns

20

50

ns

20

50

ns

250

•

kbits/s

50

200

600

•
•

•
•

ns

2000

ns

2000

ns

3500

ns

3500

ns

Note 2: All currents into device pins are positive; all currents out ot device
pins are negative. All voltages are referenced to device ground unless
otherwise specified.
Note 3: All typicals are given for Vee = 5V and TA = 25°C.

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maximum ratings are those beyond which the safety of
the device cannot be guaranteed.

TYPICAL PERFORmAnCE CHARACTERISTICS
350
300

i'---

~ 250

W~IH

.........

~ 200

a:

=>

'" 150

~
!5
-

50

a:
a:

40

'"

30

~

'\
~

o
0

;;;:

\

%;

o
-50 -25

60

\

~-r-

,

TAI= 250e

\.

DRIVER ENABLED

DRIVER ENABG'D-r---.. ........

>-

70

TH~RML SJUTDbwN I_

.........

Driver Differential Output Voltage
vs Output Current

Receiver I tpLH -lpHL I vs
Temperature

Supply Current vs Temperature

25

50

TEMPERATURE

.............

75
(0G)

-

100

125

=>
>=>
Q.
>=>
0

"-

~

'" '\.
~

20

~

10

o

o

2

3

OUTPUT VOLTAGE (V)

"
5-43

II

LTC 1483
TYPICAL PERFORmAnCE CHARACTERISTICS
Driver Output Low Voltage
vs Output Current

Driver Differential Output Voltage
vs Temperature
70

2.5
2.4
~ 2.3

ttl
;::

............

60

.........

2.2

f"...

~ 2.1

;g

I

TA=25,b

RL=h4!L

~

50

.....

iD 40

........

2.0

g§

.............

~ 1.9

:::>
<.>

'5
'5
o

30

!l.

a:

tt

1.8
15 1.7

20

/
o L
o

Driver Output High Voltage
vs Output Current

/
1/

/

1.5
-50 -25

0
25 50
75
TEMPERATURE ('C)

100 125

/
V

-20

L30

!z
~

a:

-40

/

13 -50
'5

J

~ -60

0 _ 70

10

1.6

TA = 25~C

-10

-80
-90

2

.--o

OUTPUT VOLTAGE

--

V
2

/

/

J

V
3

OUTPUT VOLTAGE (V)

Pin FunOlons
RO (Pin 1): Receiver Output. If the receiver output is
enabled (RE low), then if A> Bby 200mV, RO will be high.
If A < B by 200mV, then RO will be low.
RE (Pin 2): Receiver Output Enable. A low enables the
receiver output, RO. A high input forces the receiver
output into a high impedance state.
DE (Pin 3): Driver Outputs Enable. A high on DE enables
the driver output. A, Band the chip will function as a line
driver. A low input will force the driver outputs into a high
impedance state and the chip will function as a line
receiver. If RE is high and DE is low, the part will entera low
power (1~) shutdown state.

DI (Pin 4): Driver Input. If the driver outputs are enabled
(DE high) then a Iowan DI forces the outputs A low and B
high. Ahigh on DI with the driver outputs enabled will force
A high and Blow.
GND (Pin 5): Ground.
A (Pin 6): Driver Output/Receiver Input.
B (Pin 7): Driver Output/Receiver Input.
VCC (Pin 8): Positive Supply. 4.75V < Vee < 5.25V.

FunCTion TABLES
LTC1483 Transmitting

LTC1483 Receiving

INPUTS

OUTPUTS

RE

DE

DI

B

A

X

1

1

1

X

1

0
1
Z
Z·

0
X
0
0
1
0
X
'Shutdown mode for LTC1483

5-44

0
Z
Z·

INPUTS
RE

DE

OUTPUTS

A-B

~O.2V
0
0
::;-O.2V
0
0
Inputs Open
0
0
X
1
0
'Shutdown mode for LTC1483

RO
1
0
1

z·

LTC1483
TEST CIRCUITS
'"

~VGG

T

VOG

R

B

I ru"",,,~

RECEIVER
OUTPUT

AThO
RO

'::"

1k

CRl

S2 o---:J....

":"

figure 1. Driver DC Test Load

":'"

LTC1483'F02

Figure 2. Receiver Timing Test Load

3V

~

S1O--VGG

OUTPUT
UNDER TEST

500Q

S2

T
Figure 3. Driver/Receiver Timing Test Circuit

Cl

*

Figure 4. Driver Timing Test Load

SWITCHinG TimE WAVEFORms
3V
DI

A

:J

;:

Vo

112 Vo
Vo
OV
-Vo

1,,, 10n8, II" 10n8

1 5V
.

OV

~r'~

-J

J15V

1--

IpHl

~

-J

k-ISKEW
90%

VOIFF = V(A) - V(B)

10%

k-ISKEW

'T

10%

1,Figure 5. Driver Propagation Delays

3V
{1.5V

DE
OV
5V
A, B

-

- - IZl(SHON), IZl

-

1.5V
Ill-

~

'l\2.3V

OUTPUT NORMALLY LOW

110.5V

2.3V

OUTPUT NORMALLY HIGH

0.5V

VOL
VOH
A, B
OV

I,,, 10n8,11" 10n8

- - IZH SHON , IZH

IHZ-

t:-

LTC1483'F06

Figure 6. Driver Enable and Disable Times

5-45

LTC1483
SWITCHinG TimE WAVEFORms
VOH - - - - - - - - - - ,
RO VOL _ _ _ _ _ _ _ _ _---t\\..II._!SV_ _ _

IP...::.Hl~;

A_:OD2 _ _ _ _ _ _ _ _

~OU~TP::::.UT!....__ _ _ t·SV

I,,, IOns, It" IOns

IPlH)r-- - - - OV
-VOD2 _ _ _ _ _ _ _ _ _~,._ _ _ _----!!IN!!::PU:::.T_ _ ___'_
LT"""'07

Figure 7. Receiver Propagation Delays
3V

RE

ov
SV

RO

RO
OV

I\1.SV

-

I.SV

1,< IOns, ItS IOns

~ IZl(SHDN),

ILZ-

IZl

c::

I.SV

OUTPUT NORMAllY LOW

If'O.SV

I.SV

OUTPUT NORMALLY HIGH

I\J o.sv
I HZ

k--- IZH(SHDN) IzH

---it::

LTCl483F06

Figure 8. Receiver Enable and Disable Times

APPLICATions InFORmATion
Basic Theory of Operation
Traditionally RS485 transceivers have been designed using bipolar technology because the common-mode range
of the device must extend beyond the supplies and the
device must be immune to ESO damage and latch-up,
Unfortunately, most bipolar devices draw a large amount
of supply current, which is unacceptable forthe numerous
applications that require low power consumption, The
LTC1483 is a CMOS RS485/RS422 transceiver which
features ultra-low power consumption without sacrificing
ESO and latch-up immunity,

(01) or the N+/P-substrate diode (02) respectively will
turn on and clamp the output to the supply, Thus, the
output stage is no longer in a high impedance state and is
not able to meetthe RS485 common-mode range requirement. In addition, the large amount of current flowing
through either diode will induce the well-known CMOS
latch-up condition, which could destroy the device,

Th~

LTC1483 uses a proprietary driver output stage,
which allows acommon-mode range that extends beyond
the power supplies while virtually eliminating latch-up and
providing excellent ESO protection. Figure 9 shows the
LTC1483 output stage while Figure 10 shows a conventional CMOS output stage.
When the conventional CMOS output stage of Figure 10
enters a high impedance state, both the P-channel (P1)
and the N-channel (N1) are turned off. Ifthe output is then
driven above Vce or below ground, the P+/N -well diode

5-46

OUTPUT

LOGIC

LOGIC

--,

--,

i: 02

Nl

P
"':"

LTCl483·fOg

Figure 9. LTC1483 Output Stage

i: 02

Nl

P
":'"

LTC1483·F10

Figure 10. Conventional
CMOS Output Stage

LTC1483
APPLICATions InFoRmATion
The LTC1483 output stage of Figure 9 eliminates these
problems by adding two Schottky diodes, SD3 and SD4.
The Schottky diodes are fabricated by a proprietary modification to the standard N-well CMOS process. When the
output stage is operating normally, the Schottky diodes
are forward biased and have a small voltage drop across
them. When the output is in the high impedance state and
is driven above Vee or below ground, the parasitic diode
D1 orD2 still turns on, butSD3 orSD4 will reverse bias and
prevent current from flowing into the N-well or the substrate. Thus the high impedance state is maintained even
with the output voltage beyond the supplies. With no
minority carrier current flowing into the N-well or substrate, latch-up is virtually eliminated under power-up or
power-down conditions.
The LTC1483 output stage will maintain a high impedance
state until the breakdown of the N-channel or P-channel is
reached when going positive or negative respectively. The
output will be clamped to either Vee or ground by a Zener
voltage plus aSchottky diode drop, but this voltage is well
beyond the RS485 operating range. An ESD cell protects
output against multiple ±1 OkV human body model ESD
strikes. Because the ESD injected current in the N-well or
substrate consists of majority carriers, latch-up is prevented by careful layout techniques.

Slew Rate
The LTC1483 is desig ned for systems that are sensitive to
electromagnetic radiation. The part features a slew rate
limited driver that reduces high frequency electromagnetic emissions, while improving signal fidelity by reducing reflections due to misterminated cables. Figures 11
and 12 show the spectrum of the signal atthe driver output
for a standard slew rate RS485 driver and the slew rate
limited LTC1483. The LTC1483 shows significant reduction of the high frequency harmonics. Because the driver
is slew rate limited, the maximum operating frequency is
limited to 250kbits/s.

Low Power Operation
The LTC1483 is designed to operate with a quiescent
current of 120~ max. With the driver in three-state lee will

20

10

~ -10

B'" -20

>

w

§

I-

-30

2

~ -40

9

-50
~.

-60

I

-70

ll~ ~

I 11 I I

~"

_l lJ. .1

1

j

I II i I I

1

'V'l

11

-80
0 2 3
FREQUENCY (MHz)

Figure 11. Typical RS485 Driver Output Spectrum
Transmitting at 150kHz

20

10

~

-10

iii
~

-20

w

~ -30
2

~ -40
:;;;

g

-50

-60

I I
J,l

-70
-80

1

l.L

o
FREQUENCY (MHz)

Figure 12. Slew Rate Limited LTC1483 Driver Output
Spectrum Transmitting at 150kHz

drop to this 120~ level. With the driver enabled there will
be additional current drawn by the internal 12k resistor.
Under normal operating conditions this additional current
is overshadowed by the current drawn by the external bus
impedance.

5-47

LTC 1483
APPLICATions InFoRmATion
Shutdown Mode
Both the receiver output (RO) and the driver outputs (A, B)
can be placed in three-state mode by bringing RE high and
DE low respectively. In addition, the LTC1483 will enter
shutdown mode when RE is high and DE is low.
In shutdown the LTC1483 typically draws only 1~ of
supply current. In order to guarantee that the part goes
into shutdown, RE must be high and DE must be low for
at least 600ns simultaneously. If this time duration is less

than 50ns the part will not enter shutdown mode. Toggling
either RE or DE will wake the LTC1483 back up within
3.5~.

If the slow slew rate driver was active immediately prior to
shutdown, the supply current will not drop to 1~ until the
driver outputs have reached asteady state; this can take as
long as 2.6JlS under worst case conditions. If the driver
was disabled prior to shutdown the supply current will
drop to 1~ immediately.

RELATED PARTS
PART NUMBER
LTC485

DESCRIPTION
5V Low Power RS485 Interface Transceiver

LTC1480
LTC1481
LTC1485

3.3V Ultra-Low Power RS485 Transceiver
5V Ultra-Low Power RS485 Transceiver with Shutdown
5V Differential Bus Transceiver

LTC1487

5V Ultra-Low Power RS485 with Low EMI Shutdown
and High Input Impendance

5-48

COMMENTS
Low Power
World's First 3V Powered 485 Transceiver with Low Power Consumption
Lowest Power
Highest Speed
High Input Impendance/Low EMIlLowest Power

--L7~JD~~~~---U-lt-ra---Lo-W-po-w-e-L~-~-~_~-~
with Low EML Shutdown
and High Input Impedance
FEATURES

DESCRIPTion

• High Input Impedance: Up to 256 Transceivers
on the Bus
• Low Power: Icc = 1201JA Max with Driver Disabled
• Icc = 200~ Max with Driver Enabled, No Load
• 11JA Quiescent Current in Shutdown Mode
• Controlled Slew Rate Driver for Reduced EMI
• Single 5V Supply
• ESD Protection to ±1 OkV On Receiver Inputs and
Driver outputs
• -7V to 12V Common-Mode Range Permits ±7V
Ground Difference Between Devices on the Data Line
• Thermal Shutdown Protection
• Power Up/Down Glitch-Free Driver Outputs Permit
Live Insertion or Removal of Transceiver
• Driver Maintains High Impedance in Three-State
or with the Power Off
• Pin Compatible with the LTC485

The LTC®1487 is an ultra-low power differential line transceiver designed with high impedance inputs allowing up to
256 transceivers to share a single bus. It meets the
requirements of RS485 and RS422. The LTC1487 features
output drivers with controlled slew rate, decreasing the
EMI radiated from the RS485 lines, and improving signal
fidelity with misterminated lines. The CMOS design offers
significant power savings without sacrificing ruggedness
against overload or ESD damage. Typical quiescent current is only 80~ while operating and 1~ in shutdown.

APPLICATions

The driver and receiver feature three-state outputs, with
the driver outputs maintaining high impedance over the
entire common-mode range. Excessive power dissipation
caused by bus contention or faults is prevented by a
thermal shutdown circuit which forces the driver outputs . .
into a high impedance state. The receiver has a fail-safe ~
feature which guarantees a high output state when the
inputs are left open. I/O pins are protected against multiple
ESD strikes of over±1 OkV using the Human Body Model.

• Battery-Powered RS485/RS422 Applications
• Low Power RS485/RS422 Transceiver
• Level Translator

The LTC1487 is fully specified over the commercial temperature range and is available in 8-pin DIP and SO
packages.
ff, LTC and LT are registered trademarks of Linear Technology Corporation.

rYPICAL APPLICATiOn
LTC1487

LTC1487
RO

DI

Ai:
DE
DI
1-

L7lJ!J~

~

A

ffi

>

-,

~

":' 1
1
1
1
1
1
1
1
1
1
1• ___________ 1
EQUIVALENT LOAD OF 256
LTC1487 TRANSCEIVERS

t::;

B

a::

RO

LTC1487·TAOl

LTC1487-TA{)2

5-49

LTC 1487
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

(Note 1)
Supply Voltage (Vee) .............................................. 12V
Control Input Voltage •.........•........•. -O.5V to Vee + O.5V
Driver Input Voltage ......................• -O.5V to Vee + O.5V
Driver Output Voltage ........................................... ±14V
Receiver Input Voltage .......................................... ±14V
Receiver Output Voltage .•.........•.... -O.5V to Vee + O.5V
Operating Temperature Range ............. O°C ~ TA ~ 70°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER

TOP VIEW

N8 PACKAGE
8-LEAOPOIP

S8 PACKAGE
8-LEAOPLASTICSO

LTC1487CN8
LTC1487CS8
LTC14871N8
LTC14871S8
S8 PART MARKING

TJMAX= l25"C, 9JA= l30"C/W (N8)
TJMAX =l25"C, 9JA= l50"C/W (S8)

1487
14871

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS

DOC:::; TA:::; 70°C, Vee = 5V (Notes 2, 3) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

VOOl

Differential Driver Output Voltage (Unloaded)

V002

Differential Driver Output Voltage (with Load)

10=0
R= 50n (RS422)
R= 2m (RS485), Figure 1

t.Voo

Change in Magnitude of Driver Differential Output
Voltage for Complementary Output States

R= 2m or R= 50n, Figure 1

Driver Common-Mode Output Voltage

R= 2m or R= 50n, Figure 1

Change in Magnitude of Driver Common-Mode
Output Voltage for Complementary Output States

R= 2m or R= 50n, Figure 1

VIH
VIL

Input High Voltage

DE, DI, RE

Input Low Voltage

DE, DI, RE

IIN1

Input Current

DE, DI, RE

IIN2

Input Current (A, B)

DE = 0, Vcc = OVor 5.25V, VIN = 12V
DE = 0, Vce = OV or 5.25V, VIN = -7V

VTH

Differential Input Threshold Voltage for Receiver

-7V:::;VCM~12V

t.VTH
VOH

Receiver Input Hysteresis
Receiver Output High Voltage

VeM= OV
10 = -4mA, VID = 200rnV

VOL

Receiver Output Low Voltage

10 = 4mA, VID = -200mV

10ZR

Three-State (High Impedance) Output
Current at Receiver

Vec = Max, O.4V ~ Va ~ 2.4V

RIN

Receiver Input Resistance

-7V~VeM~12V

Icc

Supply Current

No Load, Output Enabled
No Load, Output Disabled

ISHON

Supply Current in Shutdown Mode

DE = OV, RE = Vec

IOS01

Driver Short-Circuit Current, VOUT = HIGH

-7V~Vo~12V

IOS02

Driver Short-Circuit Current, VOUT = LOW

-7V~Vo~12V

10SR

Receiver Short-Circuit Current

OV ~ Vo ~ Vcc

Voc
t.IVocl

5-50

MIN

•
•
•
•
•
•

2.0
1,5

•

2

•
•
••
•
•
•
•
•

TYP

MAX
5

UNITS
V

5
0,2

V
V
V

3

V

0.2

V
V

-0.2

0.8

V

±2

IJA

0.30
-0.15

rnA
rnA

0.2
45

V
mV

3.5

V
0.4

V

±1

IJA

•
••

70

10

•
•
•

IJA
IJA
IJA

35

250

rnA

35

250

rnA

7

85

rnA

kn

96
120
80
1

200
120

LTC 1487

ELECTRICAL CHARACTERISTICS

-4o oe s TA s 85°e, Vee = 5V (Note 4) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

VOD1

Differential Driver Output Voltage (Unloaded)

10 = 0

VOD2

Differential Driver Output Voltage (with Load)

R= 50n (RS422)
R = 2m (RS485), Figure 1

Voc

Driver Common-Mode Output Voltage

R= 2m or R = 50n, Figure 1

VTH
tNTH

Differential Input Threshold Voltage for Receiver

-7V:'> VCM:'> 12V

Receiver Input Hysteresis

Icc

Supply Current

VCM = OV
No Load, Output Enabled
No Load, Output Disabled

ISHDN
tpLH

Supply Current in Shutdown Mode

DE = OV, RE = Vcc

Driver Input to Output

IpHL

Driver Input 10 Outpul

RDiFF = 54n, CL1 = CL2 = 100pF,
(Figures 3, 5)

ISKEW
Ir,lf

Driver OUlpul to OUlput

IpLH

Receiver Input to Oulput

IpHL

Receiver Input to Output

tSKD

ItpLH - tpHL I Differential Receiver Skew

fMAX

Maximum Data Rate

Driver Rise or Fall Time
RDiFF = 54n, CL1 = CL2 = 100pF,
(Figures 3, 7)

SWITCHinG CHARACTERISTICS
PARAMETER

CONDITIONS

tpLH

Driver Input to Output

IpHL

Driver Input to Output

RDIFF = 54n, CL1 = CL2 = 100pF,
(Figures 3, 5)

tsKEW
Ir,tf

Driver Output to Output

•
•
•
•
•
•
•
•

2.0
1.5
-0.2

MAX

V

5

V
V

3

V

0.2
120
80
1

UNITS

5

45

V
mV

200
120
10

IJA
IJA
IJA

150

1200

ns

150

1200

ns

600

ns

2000

ns
ns

100
150
30

140

250

30

140

250

13

ns
ns

250

kbps

IZH

Driver Enable to Output High

CL = 1OOpF (Figures 4, 6), S2 Closed

IZL

Driver Enable to Output Low

CL = 1OOpF (Figures 4, 6), Sl Closed

ILZ

Driver Disable Time from Low

CL = 15pF (Figures 4, 6), Sl Closed

1HZ
IpLH

Driver Disable Time from High

CL = 15pF (Figures 4, 6), S2 Closed

IpHL

Receiver Input to Output

RDIFF = S4n, CLf = CL2 = 100pF,
(Figures 3, 7)

ISKD

ItpLH - tpHL I Differenlial Receiver Skew

IZL

Receiver Enable to Output Low

CRL = lSpF (Figures 2, 8), Sl Closed

IZH

CRL = lSpF (Figures 2, 8), S2 Closed

ILZ

Receiver Enable to Output High
Receiver Disable from Low

1HZ

Receiver Disable from High

CRL = lSpF (Figures 2, 8), S2 Closed

IMAX

Maximum Data Rate

isHDN

Time to Shutdown

CRL = lSpF (Figures 2, 8), Sl Closed

DE=O,RE=

I

•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

MAX

UNITS

150

1200

ns

150

1200

ns

MIN

Driver Rise or Fall Time

L7lJ!J~

•
••
•
•
•
•
•

TYP

ooeSTAS7ooe, Vee=5V(Notes2, 3) unless otherwise noted.

SYMBOL

Receiver Input to Output

MIN

TYP

250

600

ns

150

1200

ns

100

1500

ns

100

1500

ns

150

1500

ns

150
30

ns

140

lS00
2S0

30

140

2S0

ns

13

ns

20

SO

ns

20

SO

20

SO

ns
ns

20

50

ns
kbps

250
50

ns

200

600

ns

5-51

LTC 1487
SWITCHinG CHARACTERISTICS

DoC::; TA::; 70°C, Vee =5V (Notes 2,3) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

tZii(SHDN)

Driver Enable from Shutdown to Output High

CL = 100pF (Figures 4, 6), S2 Closed

tZL(SHDN)

Driver Enable from Shutdown to Output Low

CL = 100pF (Figures 4, 6), S1 Closed

tZH(SHDN)

Receiver Enable from Shutdown to Output High

CL = 15pF (Figures 2, 8), S2 Closed

tZL(SHDN)

Receiver Enable from Shutdown to Output Low

CL = 15pF (Figures 2, 8), S1 Closed

TYP

MIN

•
•
•
•

MAX

UNITS

2000

ns

2000

ns

2000

ns

2000

ns

Nole 3: All typicals are given for Vce = 5V and TA = 25°C.
Nole 4: The LTC1487 is not tested and is not quality-assurance sampled at
-40°C and at 85°C. These specifications are guaranteed by design,
correlation, and/or inference from O°C, 25°C and/or 70°C tests.

The. denotes specifications which apply over the full operating
temperature range.
Nole 1: Absolute maximum ratings are Ihose beyond which the safety of
the device cannot be guaranteed.
Nole 2: All currents into device pins are positive; all currents out ot device
pins are negative. All voltages are referenced to device ground unless
otherwise specified.

TYPICAL PERFORmAnCE CHARACTERISTICS
Driver Differential Output Voltage
vs Output Current

Supply Current vs Temperature
450

I I I

400

I 1

350

THERMAL SHUTDOWN
WITH DRIVER ENABLED
AND NOMINAL LOAD

~ 300

!z

~ 250

I I I

a;;

~ 200

::;
2:
=>

150

'" 100
50

-+-r

1

--

1

80

~

70

~

t

1

DRIVER ENABLED
WITH NO LOAD

-50 -25 0

25

50

60

>--

50

a'a::i

a::
=>
>-=>
">-=>

u

0

DrIVE~ DISfBLEf WljH N~ LO~D

o

~

§.

J(

'" "

~2.18

'\

~2.16

\

30

"I""

-....

~ 2.08

"

""

~2.06

c

\.

TEMPERATURE ('C)

"'

~ 2.10

I\,

20

RL = 54!)

~2.14
~2.12

'\

40

o
o

2.24
2.22
2.20

TA = 25'C

10

75 100 125 150 175

Driver Differential Output Voltage
vs Temperature

'-

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT VOLTAGE (V)

2.04
2.02
2.00
-50 -25

0

25

50

............

...........

75

100

125

TEMPERATURE ('C)

LTCl487.TPCOl

Driver Output low Voltage
vs Output Current
120

TA = 25'C

V-

100
~

§. 80
>--

~

a;;

=> 60
u
>-=>
"- 40
>-=>

/

20

o

/

-10

I

o

-40
-50

~

-60

a::

u

~ -70
o

-80

J

-90

1

/

i

"-

2

3

OUTPUT VOLTAGE (V)
LTCl487.TPC04

5-52

t5

g;

-100

500

/

450

'[ -30
>--

Driver Skew vs Temperature

/

TA = 25'C

-20

V

0

Driver Output High Voltage
vs Output Current

--

/
,,-

/

400

l

//

g 350
~ 300

/

/
/

250

,/

200

./'

/"

150
-50 -25

o

V

0

25

50

75

TEMPERATURE ('C)

OUTPUT VOLTAGE (V)
LTC1481'Tf'{:1l5

100

125

LTC 1487
Pin FunOlons
RO (Pin 1): Receiver Output. If the receiver output is
~nabled (RE LOW), and A> 8 by 200mV, RO will be HIGH.
If A < B by 200mV, then RO will be LOW.
RE (Pin 2): Receiver Output Enable. A LOW enables the
receiver output, RD. A HIGH input forces the receiver
)utput into a high impedance state.
~E (Pin 3):

Driver Outputs Enable. A HIGH on DE enables
!he driver output. Aand Band the chip will function as aline
jriver. ALOW input will force the driver outputs into ahigh
mpedance state and the chip will function as a line
'eceiver. If RE is HIGH and DE is LOW, the part will enter
1 low power (1~) shutdown state.

DI (Pin 4): Driver Input. If the driver outputs are enabled
(DE HIGH) thena LOWon DI forces the outputs ALOWand
8 HIGH. A HIGH on DI with the driver outputs enabled will
force A HIGH and 8 LOW.
GND (Pin 5): Ground.
A (Pin 6): Driver OutpuVReceiver Input.
B (Pin 7): Driver OutpuVReceiver Input.
Vee (Pin 8): Positive Supply. 4.75V < Vee < 5.25V.

FunCTion TABLES
LTC1487 Transmitting

INPUTS
DE

RE

LTC1487 Receiving

OUTPUTS

X

1
1
0
1
0
'Shutdown mode
X
0

01

B

A

1
0
X
X

0
1
Z
Z·

1
0
Z
Z·

RE

INPUTS
DE

OUTPUTS
RO

A-B

•

1
0
1
Z·

~O.2V

0
0
0
0
0
0
1
0
'Shutdown mode

s-O.2V
Inputs Open

X

rEST CIRCUITS

ATh
R

VOD

R

B

voe

'::'
LTC1487'FOl

Figure 1. Driver DC Test Load

RECEIVER
OUTPUT

I nm"'''~

"

~Vee

lk

TCRl

":"

S2~

-=

LTC1487'f02

Figure 2. Receiver Timing Test Load

3V

Slo--vee

OUTPUT
UNDER TEST

~
5000

S2

T

"':'"

Figure 3. Driver/Receiver Timing Test Circuit

L7lJIJ~

Cl

~

lTC1487'F04

":'"

Figure 4. Driver Timing Test Load

5-53

LTC 1487
SWITCHinG TimE WAVEFORms
3v------------------·r-----------------------~
~

f = lMHz, I r " IOns, If'; IOns

1$

I.SV

OV----------------'I

1-

---------1ro~la~:rV-o----1~x~~~-:-~----------------~X
IpHL

A

-1I-ISKEW

'T

Vo
OV -----------------,;1"'0'/.-;-,-"i'I 90%

VOIFF = V(A) - V(B)

-yo
lTC1467'F05

Ir-

Figure 5. Driver Propagation Delays

3V
DE
OV
SV

A, B

-

f = lMHz, I r " IOns, If" IOns

1.5V
-

IZL(SHON), IZL

I.SV
ILZ-

t;

2.3V

OUTPUT NORMALLY LOW

(IO.SV

2.3V

OUTPUT NDRMALLY HIGH

O.SV

VOL
VOH
A,B
OV

-

-

IZH(SHON), IZH

IHZ-

t

LTCl481'F06

Figure 6. Driver Enable and Disable Times

t'

t·

VOH - - - - - - - - - - - - - - - - - - - - - _ _ .

SV
RO VOL------------------------+~--------~~~--------OUTPUT

::I

f = 1MHz, I r " IOns, If" 1Ons

A _ BV002 __________________
tPH_l

SV

IplH JOV

OV

-V002 _______________________
\;.'\".____________IN_P_UT_________
..J

LTCl487'Fl)7

Figure 7. Receiver Propagation Delays

3V

RE

ov
SV

RO

RO
OV

-

I.SV

-IZl(SHON),IZl
I.SV

II

I.SV
-

I.SV

f = lMHz, Ir " IOns, If" IOns
ILZ-

,IO.SV

OUTPUT NORMALLY HIGH

O.SV

IZH(SHON), IZH

IHZ-

Figure 8. Receiver Enable and Disable Times

5-54

];=-

OUTPUT NORMALLY LOW

r::::-

LTCl487'F08

LTC 1487
FlPPLICATlons InFORmATion
High Input Impedance
The LTC1487 is designed with a96kn (typ) input impedance to allow up to 256 transceivers to share a single
RS485 differential data bus. The RS485 specification
requires that a transceiver be able to drive as many as 32
"unit loads." One unit load (UL) is defined as an imped~nce that draws amaximum of 1mA with up to 12Vacross
it. Typical RS485 transceivers present between 0.5 and 1
unit load at their inputs. The 96kn input impedance of the
LTC1487 will draw only 125~ under the same 12V
~ondition, presenting only 0.125UL tothe bus. As aresult,
256 LTC1487 transceivers (32UUO.125UL = 256) can be
~onnected to a single RS485 data bus without exceeding
the RS485 driver load specification. The LTC1487 meets
~II other RS485 specifications, allowing it to operate
~qually well with standard RS485 transceiver devices or
~igh impedance transceivers.
~MOS

Output Driver

rhe RS485 specification requires that a transceiver with:;tand common-mode voltages of up to 12V or -7V at the
~S4851ine connections. Additionally, the transceiver must
1e immune to both ESD and latch-up. This rules out
:raditional CMOS drivers, which include parasitic diodes
:rom their driver outputs to each supply rail (Figure 9). The
_TC1487 uses a proprietary process enhancement which
idds a pair of Schottky diodes to the output stage (Figure
10), preventing current from flowing when the commonTlode voltage exceeds the supply rails. Latch-up at the
1UtPUt drivers is virtually eliminated and the driver is
1revented from loading the line under RS485 specified
:ault conditions. Aproprietary output protection structure
lrotects the transceiver line terminals against ESD strikes
'Human Body Model) of up to ±10kV.

Vee

t

P1n
SD3

f{
"'e"'
4.

D1

- - - OUTPUT

LOGIC

SD4

":"

lTC1487-F10

Figure 10. LTC1487 Output Stage

When two or more drivers are connected to the same
transmission line, a potential condition exists whereby
more than two drivers are simultaneously active. If one or
more drivers is sourcing current while another driver is
sinking current, excessive power dissipation may occur
within either the sourcing or sinking element. This condition is defined as driver contention, since multiple drivers
are competing for on.e !r~nsmission line. The LTC1 ~87 . .
provides a current limiting scheme to prevent driver ~
contention failure. When driver contention occurs, the
current drawn is limited to about 70mA, preventing excessive power dissipation within the drivers.
The LTC1487 has a thermal shutdown feature which
protects the part from excessive powe r dissi pation. Under
extreme fault conditions, up to 250mA can flow through
the part, causing rapid internal temperature rise. The
thermal shutdown circuit will disable the driver outputs
when the internal temperature reaches 150°C and turns
them back on when the temperature cools to 130°C. This
cycle will repeat as necessary until the fault condition is
removed.
Receiver Inputs

LOGIC

Figure 9. Conventional CMOS Output Stage

L7lJ!J~

The LTC1487 receiver features an input common-mode
range covering the entire RS485 specified range of -7V to
12V.lnternal96k input resistors from each line terminal to
ground provide the 0.125UL load to the RS485 bus.
Differential signals of greater than ±200mV within the
specified input common-mode range will be converted to
a TTL-compatible signal at the receiver output. A small
amount of input hysteresis is included to minimize the

5-55

LTC1487
APPLICATions InFoRmATion
effects of noise on the line signals.lfthe line is terminated
or the receiver inputs are shorted together, the receiver
output will retain the last valid line signal due to the 45mV
of hysteresis incorporated in the receiver circuit. If the
LTC1487transceiverinputs are leftfloating (unterminated),
an internal pull-up of 10~ at the A input will force the
receiver output to a known high state.

In shutdown the LTC1487 typically draws only 1~ of
supply current. In order to guarantee that the part goes
into shutdown, RE must be HIGH and DE must be LOW for
at least 600ns simultaneously. If this time duration is less
than 50ns the part will not enter shutdown mode. Toggling
either RE or DE will wake the LTC1487 back up within

Low Power Operation

If the driver is active immediately prior to shutdown, the
supply current will not drop to 1~ until the driver
outputs have reached asteady state; this can take as long
as 2.6~ under worst case conditions. If the driver is
disabled prior to shutdown the supply current will drop
to 1~ immediately.

The LTC1487 draws very little supply current whenever
the driver outputs are disabled. In shutdown mode, the
quiescent current is typically less than 1~. With the
receiver active and the driver outputs disabled, the LTC1487
will typically draw 80~ quiescent current. With the driver
outputs enabled but unterminated, quiescent current will
rise slightly as one of the two outputs sources current into
the internal receiver input resistance. With the minimum
receiver input resistance of 70k and the maximum output
swing of 5V, the quiescent current will rise by amaximum
of 72~. Typical quiescent current rise with the driver
enabled is about 40~.
The quiescent current rises Significantly if the driver is
enabled when it is externally terminated. With 1/2
termination load (1200. between the driver outputs), the
quiescent current will jump to at least 13mA as the drivers
force aminimum of 1.5Vacross the termination resistance.
With afully terminated 600. line attached, the current will
rise to greater than 25mA with the driver enabled,
completely overshadowing the extra 40~ drawn by the
internal receiver inputs.

3.5~.

Slew Rate and Propagation Delay
Many digital encoding schemes are dependent upon the
difference in the propagation delay times of the driver and
receiver. Figure 11 shows the test circuit for the LTC1487
propagation delay.
...Ll00PF

"'k:

BR

TIL IN

RECEIVER
OUT

1,.lj<6ns

"f'100PF

Figure 11. Receiver Propagation Delay Test Circuit

The receiver delay times are:
ItpLH - tpHL I =13ns Typ, Vee =5V

Shutdown Mode

The LTC1487 drivers feature controlled slew rate to reduce
system EMI and improve signal fidelity by redUCing reflections due to misterminated cables.

Both the receiver output (RO) and the driver outputs (A, B)
can be placed in three-state mode by bringing RE HIGH
and DE LOW respectively. In addition, the LTC1487 will
enter shutdown mode when RE is HIGH and DE is LOW.

The driver's skew times are:
Skew = 250ns Typ, Vee = 5V
600ns Max, Vee = 5V, TA = -40°C to 85°C

5-56

INDEX
;ECTION 5-INTERFACE
V.35
LTC1345, Single Supply V.35 Transceiver .......................•.......•......•.....................•••....••.•....•••......••.. 5·58
LTC1346, 10Mbps DCE/OTE V.35 Transceiver ...•••.....••.....••••....•••......•......•......................•.............•• 13·65

L7lJD~

5-57

f"'-LlnO\~D_ _
LTC_1345

~'TECHNOLOGY

Single Supply
V.35 Transceiver

FEATURES

DESCRIPTion

• Single Chip Provides All V.35 Differential Clock
and Data Signals
• Operates From Single 5V Supply
• Shutdown Mode Reduces Icc to 1J.IA Typ
• Software Selectable DTE or DCE Configuration
• Transmitters and Receivers Will Withstand
Repeated ±10kV ESD Pulses
• 10MBaud Transmission Rate
• Transmitter Maintains High Impedance When
Disabled, Shut Down, or with Power Off
• Meets CCITI V.35 Specification
• Transmitters are Short-Circuit Protected

The LTC®1345 is asingle chip transceiver that provides the
differential clock and data signals for aV.35 interface from
a single 5V supply. Combined with an external resistor
termination network and an LT®1134A RS232 transceiver
for the control signals, the LTC1345 forms acomplete low
power DTE or DCE V.35 interface port operating from a
single 5V supply.
The LTC1345 features three current output differential
transmitters, three differential receivers, and a charge
pump. The transceiver can be configured for DTE or DCE
operation or shut down using two Select pins. In the
Shutdown mode, the supply current is reduced to 1J.IA.
The transceiver operates up to 1OMbaud. All transmitters
feature short-circuit protection and a Receiver Output
Enable pin allows the receiver outputs to be forced into a
high impedance state. Both transmitter outputs and receiver inputs feature ±10kV ESD protection. The charge
pump features a regulated VEE output using three external
1J.LF capacitors.

APPLICATions
• Modems
• Telecommunications
• Data Routers

D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Clock and Data Signals for V.35 Interface
DTE

DCE

OJ=
GND (102)

0012S0
~
500

61 TECHNOLOGIES

62ITSOO/1250 (SOIC) OR
699TR501125 (DIP)

5-58

'::'

LTC 1345
IBSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

IDle 1)

upply Voltage, Vee .................................................. 6V
put Voltage
Transmitters ........................... -0.3V to (Vee + 0.3V)
Receivers ........ '" '" ................................. -18V to 18V
S1, S2, OE ............................... -0.3V to (Vee + 0.3V)
utput Voltage
Transmitters .......................................... -18V to 18V
Receivers ................................ -0.3V to (Vee + 0.3V)
VEE ..................................................................... -10V to 0.3V
10rt-Circuit Duration
Transmitter Output ..................................... Indefinite
Receiver Output .......................................... Indefinite
VEE .................................................................................. 30 sec
aerating Temperature Range
Commercial ............................................ O°C to 70°C
Industrial ........................................... -40°C to 85°C
orage Temperature Range ................ -65°C to 150°C
lad Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER
LTC1345CNW
LTC1345CSW
LTC13451NW
LTC13451SW

NW PACKAGE
28·LEAD PDlP WIDE

SW PACKAGE
28·LEAD PLASTIC so WIDE

THREE V.35 TRANSMITIERS AND THREE RECEIVERS
TJMAX = 125'C, 9JA = 56'C/W (NW)
TJMAX =125'C, 9JA =85'C/W (SW)

Consult factory for Military grade parts.

IC ELECTRICAL CHARAOERISTICS
MBOL
D

e
I

1
TH

I
~

L
R
R
I

:

PARAMETER
Transmitter Differential Output Voltage
Transmitter Common-Mode Output Voltage
Transmitter Output High Current
Transmitter Output Low Current
Transmitter Output Leakage Current
Transmitter Output Impedance
Differential Receiver Input Threshold Voltage
Receiver Input Hysterisis
Receiver Input Current (A, B)
Receiver Input Impedance
Receiver Output High Voltage
Receiver Output Low Voltage
Receiver Output Short-Circuit Current
Receiver Three-State Output Current
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Vec Supply Current

VEE Voltage

Vee = 5V ±5% (Noles 2, 3), unless olherwise specified.

CONDITIONS
Figure 1, -4V '" Vas'" 4V
Figure 1, Vas = OV
Vy,z=OV
VY,z= OV
S1 = S2 = OV, -5V '" Vy z'" 5V
-2V",Vy z",2V
-7V", (VA + VB)/2 '" 7V
-7V", (VA + VB)/2 '" 7V
-7V",VA,B",7V
-7V ",VA, B'" 7V
10 = 4mA, VB, A= 0.2V
10 = 4mA, VB, A= -0.2V
OV", Va '" Vcc
S1 = S2 = OV, OV'" Va '" Vcc
T, S1, S2, OE
T,S1,S2,OE
T,S1,S2,OE
Figure 1, Vas = 0, S1 = S2 = HIGH
No Load, S1 = S2 = HIGH
Shutdown, S1 = S2 = OV
No Load, S1 = S2 = HIGH

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•••

MIN
0.44
-0.6
-12.6
9.4

TYP
0.55
0
-11
11
±1
100
25
50

MAX
0,66
0.6
-9.4
12.6
±100
200
0.4

17.5
3

30
4.5
0.2

7

0.4
85
±10

2

118
19
1

-5.5

0.8
±10
170
30
100

UNITS
V
V
rnA
rnA
~

kn
mV
mV
rnA
kn
V
V
rnA
~

V
V
~

rnA
rnA
~

V

5-59

LTC 1345

AC ElEORICAl CHARAOERISTICS
SYMBOL
tR, tF
tpLH
tpHL
tSKEW
tpLH
tpHL
tSKEW
tZL
tZH
tLl
tHZ
fase
BRMAX

PARAMETER
Transmitter Rise or Fall Time
Transmitter Input to Output .J
Transmitter Input to Output 1..
Transmitter Output to Output
Receiver Input to Output
.J
Receiver Input to Output
1..
Differential Receiver Skew, tpLH - tpHL
Receiver Enable to Output LOW
Receiver Enable to Output HIGH
Receiver Disable From LOW
Receiver Disable From HIGH
Charge Pump Oscillator Frequency
Maximum Data Rate (Note 4)

vee = 5V ±5% (Notes 2,3), unless otherwise specified.

CONDITIONS
Figures 1 and 3, Vas = OV
Figures 1 and 3, Vas = OV
Figures 1 and 3, Vas = OV
Figures 1 and 3, Vas = OV
Figures 1 and 4, Vas = OV
Figures 1 and 4, Vas = OV
Figures 1 and 4, Vas = OV
Figures 2 and 5, CL = 15pF, S1 Closed
Figures 2 and 5, CL = 15pF, S2 Closed
Figures 2 and 5, CL = 15pF, S1 Closed
Figures 2 and 5, CL = 15pF, S2 Closed

The. denotes specifications which apply over the full operating
temperature range.
Nole 1: The absolute maximum ratings are those values beyond which the
safety of the device cannot be guaranteed.
Nole 2: All currents into device pins are termed positive; all currents out of
device pins are termed negative. All voltages are referenced to device
ground unless otherwise specified.

MIN

TYP
7
25
25
0
49
52
3
40
35
30
35
200
15

•

•
•
•

•
•
•
•
•
•

10

MAX
40
70
70

UNIT:
n
n
n
n
n
n
n
n
n
n
n
kH
MbaUi

100
100
70
70
70
70

Nole 3: All typicals are given for Vec = 5V, C1 = C2 = C3 = 11!f ceramic
capacitors and TA= 25°C.
Nole 4: Maximum data rate is specified for NRZ data encoding scheme.
The maximum data rate may be different for other data encoding schemes
Data rate is guaranteed by correlation and is not tested.

TYPICAL PERFORmAnCE CHARACTERISTICS
Transmitter Output Current
vs Temperature
13

20

vee = 5V

TA= 25'e
Vee = 5V i--t--t-+--+-i--\

1

112
~~

11

Transmitter Output Skew
vs Temperature

Transmitter Output Current
vs Output Voltage

12r--t-~-+--t--r-~-+--;

~
~
~
a

15

E

I-

~
;::

OJ

vee = 5V

10

10

V
9
-50 -25

9L-~~

25
50
75
TEMPERATURE eC)

100

125

__L-~~~L-~~

-2.0 -1.5 -1.0 -0.5 0 0.5 1.0
OUTPUT VOLTAGE (V)

1.5

2.0

LTCl34/i.TPC02

5-60

o

-50 -25

..- .......

V

25
50
75
TEMPERATURE ee)

-----100

12

LTCl345·TPCOO

LTC 1345
'YPICAl PERFORmAnCE CHARAaERISTICS
Receiver ItplH -tpHll
vs Temperature

Supply Current vs Temperature

20

VEE Voltage vs Temperature

140

3D

Vee = 5V

Vee = 5V

Vee = 5V

15

120

~
>-

i'i'i 100

10

a:
a:

-

-LLOADED
C">

c:
NOLOAD~

20

r-

o

-50 -25

.?!
80

0
25 50 75
TEMPERATURE ee)

100

125

60
-50 -25

15

0
25 50
75
TEMPERATURE ee)

100

10
125

~

'"~ ~ -5.5
-<
':;
z

"3

:::>
u

~

-5.0

25

0

>

-"l.0

-6.5 '----'-----'----'----'-"'----'----'
-50 -25
0
25 50 75 100 125
TEMPERATURE ee)

LTCl345·m:ns

Transmitter Output Waveforms
INPUT
5V/DIV

LTCl345'TPC06

Receiver Output Waveforms

INPUT
O.21DIV

OUTPUT
0.2V1DIV

OUTPUT
5VIDIV

LTCl345'TPC07

·In FUnCTiOnS
~+

(Pin 1): Capacitor C2 Positive Terminal.

R3 (Pin 11): Receiver 3 Output.

1+ (Pin 2): Capacitor C1 Positive Terminal.

R2 (Pin 12): Receiver 2 Output.

~C

R1 (Pin 13): Receiver 1 Output.

(Pin 3): Positive Supply, 4.75:5 Vee:5 5.25V.

1- (Pin 4): Capacitor C1 Negative Terminal.

OE (Pin 14): Receiver Output Enable.

NO (Pin 5): Ground. The positive terminal of C3 is
mnected to ground.

A1 (Pin 15): Receiver 1 Inverting Input.

I (Pin 6): Transmitter 1 Input.

A2 (Pin 17): Receiver 2 Inverting Input.

~

(Pin 7): Transmitter 2 Input.

I (Pin 8): Transmitter 3 Input.
I (Pin 9): Select Input 1.
~

(Pin 10): Select Input 2.

L7lJIJ~

81 (Pin 16): Receiver 1 Noninverting Input.
82 (Pin 18): Receiver 2 Noninverting Input.
A3 (Pin 19): Receiver 3 Inverting Input.
83 (Pin 20): Receiver 3 Noninverting Input.
Z3 (Pin 21): Transmitter 3 Inverting Output.

5-61

LTC 1345
Pin FunCTions
Y3 (Pin 22): Transmitter 3 Noninverting Output.

Y1 (Pin 26): Transmitter 1 Noninverting Output.

Z2 (Pin 23): Transmitter 2 Inverting Output.

VEE (Pin 27): Charge Pump Output. Connected to negativE
terminal of capacitor C3.

Y2 (Pin 24): Transmitter 2 Noninverting Output

C2- (Pin 28): Capacitor C2 Negative Terminal.

Z1 (Pin 25): Transmitter 1 Inverting Output.

FunCTion TABlES
Receiver

Transmitter and Receiver Configuration
Sl

S2

TX#

RX#

REMARKS

0
1
0
1

0
0
1
1

-

-

Shutdown

INPUTS
CONFIGURATION Sl S2 DE
B-A

1,2,3

1,2

DCE Mode, RX3 Shut Down

DTE or All ON

X

1

1,2

1,2,3

DTE Mode, TX3 Shut Down

DTE or All ON

X

1

1,2,3

1,2,3

All Active

DCE

1

0
0
X X
0 0

DCE
Disabled

Transmitter
INPUTS
CONFIGURATION Sl S2 T Y1 AND Y2
DTE

0
0
1
1
0

DTE
DCEor All ON
DCEor All ON
Shutdown

1
1
X
X

0

0
1
0
1
X

0
1
0
1
Z

1

Shutdown

OUTPUTS
Zl AND Z2

Y3

Z3

1

Z

Z

0
1
0
Z

Z
0

Z
1

1

0

Z

Z

0
0
0
0
1
X

OUTPUTS
RtAND R2
R3

~O.2V

1
0
1
0
Z
Z

:s;-O.2V
~O.2V

:s;-O.2V
X
X

1
0
Z
Z
Z
Z

TEST CIRCUITS
vee

y

! S1

500
RECEIVER
OUTPUT

500

z
Figure 1. V.35 Transmitter/Receiver Test Circuit

5-62

lTC1345·F!l1

~
1k

TeL

~2

"':'"

-=-

LTC1345° F02

Figure 2. Receiver Output Enable/Disable Timing Test load

LTC 1345
WITCHinG TimE WAVEFORms
3V

j = 1MHz: I,,, 10ns: If" 10ns

T
OV

y-z

Vo

90%

VDIFF = V(Y) - V(Z)

-Vo

z
Vo

Y

Figure 3. V.35 Transmitter Propagation Delays

VID

B-A

-----r---------~
OV f=1MHz:I,,,10ns:lj,,10ns INPUT

-VID----'

-_I_PL_H=t--t-_~~----------IP-HL71

VOH _ _ _ _
R

)fl.5V

OUTPUT

~.5V

VOL -----~

'-----LTC1345° F04

Figure 4. V.35 Receiver Propagation Delays

3V------.

OV----+-'----f=-1~M~HZ~:I~,"~1~on~s:~lf~"1~o~ns--'
5V - - - - - ' - - VOL

ILz1.-

----t---~ ....._. . ;O:. : ;UT.:. ;.P~UT. . ;N:. : ;OR. . ;M.: . :A:; ;L . . ;YL:;;;O.:..;.W--:-_E.. 0.5V
t,

OUTPUT NORMALLY HIGH !-IHZVOH -----'---+.~.......::;;:.;.:...::.;..:;==.:...;.:;;::;.;....:.....--.I-- O.5V
1.5V

R
OV-----~

Figure 5. Receiver Enable and Disable Times

L7lJ!J~

5-63

LTC 1345
APPLICATions InFORmAnon
Review of CCITT Recommendation V.35
Electrical Specifications
V.35 is a CCITT recommendation for synchronous data
transmission via modems. Appendix 2 of the recommendation describes the electrical specifications which are
summarized below:
1. The interface cable is balanced twisted-pair with 80n to
120n impedance.

Cable Termination
Each end of the cable connected to an LTC1345 must bE
terminated by either one of two electrically equivalen'
external Vor Ll resistor networks for proper operation. ThE
V-termination has two series connected 50n resistors anc
a125n resistor connected between ground and the centel
tap of the two 50n resistors as shown in Figure 6A.

2. The transmitter's source impedance is between 50n and
150n.
3. The transmitter's resistance between shorted terminals
and ground is 150n±15n.
4. When terminated by a1Oon resistive load, the terminalto-terminal voltage should be 0.55V ±20%.
5. The transmitter's rise time should be less than 1%of the
signal pulse or 40ns, whichever is greater.
6. The common-mode voltage at the transmitter output
should not exceed 0.6V.
7. The receiver impedance is 100n ±10n.
8. The receiver impedance to ground is 150n ±15n.
9. The transmitter or receiver should not be damaged by
connection to earth ground, short-circuiting, or cross
connection to other lines.
10. No data errors should occur with ±2V common-mode
change at either the transmitter or receiver, or ±4V ground
potential difference between transmitter and receiver.

5-64

LTt:134S 0 Fll6

Figure 6. Y and ~ Termination Networks

The alternative Ll-termination has a 120n resistor acros~
the twisted wires and two 300n resistors between eact
wire and ground as shown in Figure 6B. Standard 1/8W.
5% surface mount resistors can be used forthe terminatior
network. To maintain the proper differential output swing
the resistor tolerance must be 5% or less. A terminatior
network that combines all the resistors into an SO-1 ~
package is available from:
BI Technologies (Formerly Beckman Industrial)
Resistor Networks
4200 Bonita Place
Fullerton, CA 92635
Phone: (714) 447-2357
FAX: (714) 447-2500
Part #: BI Technologies 627T500/1250 (SOl C)
899TR50/125 (DIP)

LTC 1345
APPLICATions InFoRmATion
Theory of Operation
The transmitter output consists of complementary
switched-current sources as shown in Figure 7.
Vee

CHIP
BOUNDARY

I
I
I
I
Iy

T

I
I
I
Iz

50Q 125Q
50Q

':'

may be forced into a high impedance state by pulling the
output enable (OE) pin high. For normal operation OE
should be pulled low.
A charge pump generates the regulated negative supply
voltage (VEE) with three 1~ capacitors. Commutating
capacitors C1 and C2 form a voltage doubler and inverter
while C3 acts as a reservoir capacitor. To insure proper
operation, the capacitors must have an ESR less than 1n.
Monolithic ceramic or solid tantalum capacitors are good
choices. Under light loads, regulation at about -5.2V is
provided by a pulse-skipping scheme. Under heavy loads
the charge pump is on continuously. Asmall ripple of about
500mV will be present on VEE.
Two Select pins, S1 and S2, configure the chip for DTE,
DCE, all transmitters and receivers on, or Shutdown. In
Shutdown mode, Icc drops to 11JA. The outputs of the
transmitters and receivers are in high impedance states,
the charge pump stops and VEE is clamped to ground.

Figure 7. Simplified Transmitter Schematic

With a logic zero at the transmitter input, the inverting
output Z sources 11 mA and the noninverting output V
sinks 11 mA. The differential transmitter output voltage is
then set by the termination resistors. With two differential
50n resistors at each end of the cable, the voltage is set to
(50n x 11 mA) = 0.55V. With a logic 1 at the transmitter
input, output Z sinks 11 mA and V sources 11 mAo The
common-mode voltage of Vand Z is OV when both current
sources are matched and there is no ground potential
difference between the cable terminations. The transmitter
current sources have a common-mode range of ±2V,
which allows for aground difference between cable terminations of ±4V.
Each receiver input has a 30k resistance to ground and
requires external termination to meetthe V.35 input impedance specification. The receivers have an input hysteresis
of 50mV to improve noise immunity. The receiver output

ESD Protection
•
LTC1345 transmitter outputs and receiver inputs have onchip protection from multiple ±10kV ESD transients. ESD
testing is done using the Human Body ESD Model. ESD
testing must be done with an AC ground on the Vcc and VEE
supply pins. The low ESR supply decoupling and VEE
reservoir capacitors providethisAC ground during normal
operation.
Complete V.35 Port
Figure 8 shows the schematic of a complete surface
mounted, single 5V DTE and DCE V.35 port using only
three ICs and eight capacitors per port. The LTC1345 is
used to transmit the clock and data signals, and the
LT1134A to transmit the control signals. If test signals
140, 141, and 142 are not used, the transmitter inputs
should be tied to Vcc.

5-65

LTC 1345
APPLICATions InFoRmATion
DYE

m=

DCE

500 1250

VCC2

5V

I

"'I

;;;!I

"'I

£11
"'I

;;;!I
""I
Q
I

tl

°1
1__ -

-------------~~:::J
ISO 2593
ISO 2593
34-PIN OTE/OCE
34-PIN OTE/OCE
INTERFACE CONNECTOR INTERFACE CONNECTOR

Figure 8. Complete Single 5V V.35 Interface

5-66

LTC 1345
~PPLICATlons

InFORmATion

tS422/RS485 Applications
ihe receivers on the LTC1345 are ideal for RS422 and
~S485 applications. Using the test circuit in Figure 9, the
.TC1345 receivers are able to successfully reconstruct
he data stream with the common-mode voltage meeting
lS422 and RS485 requirements (12V to -7V).

RECEIVER
OUTPUT
5v/DIV

:igu res 10 and 11 show that the LTC1345 receivers are
'ery capable of reconstructing data at rates up to 10Mbaud.

RECI~~~~ A

OV
-5V
-10V

5v/DIV B

LTC1J45·Fl0

Figure 10. -7V Common Mode

RECI~~~~

15V

B

5v/DIV A
10V

5V

Figure 9 RS422/RS485 Receiver Interface

OV

RECEIVER
OUTPUT
5v/DIV
LTCl34S·Fl1

Figure 11. 12V Common Mode

5-67

NOTES

5-68

INDEX
:ECTION 5-INTERFACE
AppleTal!(®
LTC1318, Single 5V RS232/RS422/AppleTall(§ DCE Transceiver ............................................................• 5·70
LTC1323, Single 5V AppleTal1(§ Transceiver ..................................................................................... 5·77
LTC1324, Single Supply LocalTal1(§ Transceiver .............................................................................. 13·45
LT1389, AppleTal1(§ Peripherallnlerface Transceiver ........................................................................ 13·73

L7lJD~

5-69

f-IIW"'"llnt:N>
~, TECHNOLOG~f\(~----S-ing-le-5-V
LTC1318

RS232/RS422/AppleTalk®
DeE Transceiver
FEATURES

DESCRIPTion

• Single Chip Provides DCE RS232 or
RS422/AppleTalk DCE Port
• Operates from a Single 5V Supply
• Charge Pump Uses 0.1JJf Capacitors
• Output Common-Mode Voltage Range Exceeds
Power Supply Rails for All Drivers
• Driver Outputs Are High Impedance with Power Off
• Pin Selectable RS232/RS422 Receiver
• Thermal Shutdown Protection
• Drivers Are Short-Circuit Protected

The LTC®1318 is a single 5V, RS232/RS422 transceiver
for connection tothe DCE, or peripheral side of an interface
link. It includes an on-board charge pump to generate a
±8V supply which allows true RS232 output swings. The
charge pump requires only four external 0.1 JJf capacitors.
The LTC1318 includes two RS232 drivers, a differential
RS422 driver, a dedicated RS232 receiver, and a pin
selectable RS232/RS422 receiver which can receive either
single-ended or differential signals.

APPLICATions
• Dual-Mode RS232/RS422 Peripherals
• AppleTalk Peripherals
• Single 5V Systems

The LTC1318 features driver outputs which can be taken
to common-mode voltages outside the power supply rails
without damage. Additionally, the driver outputs assume
a high impedance state when the power is shut off,
preventing externally applied signals from feeding back
into the power supplies. The RS232 devices will operate at
speeds up to 1OOkbaud. The RS422 devices will operate
up to 2Mbaud.
The LTC1318 is available in a 24-lead SO Wide package.
£T, LTC and LT are registered trademarks of Linear Technology Corporation.
AppieTaik and LocaiTaik are registered trademarks of Apple Computer, Inc.

TYPICAL APPLICATiOn
Driver Output Waveforms
TXD
(5V/DIV)

~~~+---------------~

TO
DIGITAL

TXD'. TXD(2V1DIV)

SYSTEM

AXDO
(5V1DIV)

APPLETALK
NETWORK

5-70

Rl = 100U
Cl= 100pF

200nslDlV

1S18TA02

LTC1318
~BSOLUTE

mAXimum RATINGS

PACKAGE/ORDER InFORmATiOn

Note 1)

:;upply Voltage:
Vee ...................................................................................... 7V
V+ ................................................................................... 13.2V
V- ............................................................................... -13.2V
nput Voltage:
All Drivers .............................. -0.3 to (Vee + 0.3V)
All Receivers ....... ....... ..... ............ .... ... - 25V to 25V
RXMODE Pin ....................... - 0.3V to (Vee + 0.3V)
)utput Voltage:
RS232 Drivers ................ (V+ - 30V) to (V- + 30V)
RS422 Drivers ................................................ ±15V
All Receivers ........................ -0.3V to (Vee + 0.3V)
:;hort-Circuit Duration:
V+ or V- to GND .......................................... 30 sec
Driver or Receiver Outputs ...................... Indefinite
)perating Temperature Range .................... O°C to 70°C
_ead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER
LTC1318CSW

SWPACKAGE
24-LEAD PLASTIC SO WIDE
TJMAX =125'C, eJA =85'CIW

Consult factory for Industrial and Military grade parts

ELECTRICAL CHARACTERISTICS
's =5V ±5%, C1
iVMBOL
iupplies
Ge

,+

,-

=C2 = O.11lf, TA =DoC to 70°C, unless otherwise specified. (Notes 2, 3)

I PARAMETER

CONDITIONS

Supply Current

No Load

Positive Charge Pump Output Voltage

10ur=OmA
lOUT = 10mA, Vcc = 5V

Negative Charge Pump Output Voltage

lOUT = OmA
lOUT = - 5mA, Vee = 5V

lifferenlial Driver
Differential Driver Dutput Voltage
'aD

No Load (Figure 1)
RL = lOOn (Figure 1)
RL = lOOn (Figure 1)

IVOD

Change in Magnitude of Differential
Dutput Voltage

'oe

Common-Mode Output Voltage

RL = lOOn (Figure 1)

lSS
'IL

Short-Circuit Output Current
Input Low Voltage

-1V < VCMR <7V

Input High Voltage
IH
;ingle-Ended Driver

a

Dutput Voltage Swing

RL= 3k

lSS
IL

Short-Circuit Output Current
Input Low Voltage

VOUT = DV

IH
R

Input High Voltage
Dutput Slew Rate

L7lJ!J~

RL = 3k, CL = 51pF

•
••
••
••
•
•
•
•
•
•
•
•
•
•

MIN

TYP

MAX

9

30

7.8
6.8
-7.3
-6.3

8.8
7.4
-8.6
-7.3

mA
V
V
V
V

±4
±2

V
V

35

0.2

V

3
200
0.8

V
mA
V
V

0.8

mA
V
V

30

VI!JS

2.0
±5

7.3/-6.5

±5

17

2
4

UNITS

20

V

5-71

•

LTC1318

ELECTRICAL CHARACTERISTICS
VS = 5V ±5%, C1 = C2 = 0.1 J.IF, TA= DOC to 70°C, unless otherwise specified. (Notes 2, 3)
SYMBOL I PARAMETER
Differential Receiver
VTH
CMR
RIN
VOL
VOH

Output High Voltage

RIN

Input Voltage High Threshold
Hysteresis
Input Resistance

VOL
VOH

Output Low Voltage
Output High Voltage

loss

Short-Circuit Output Current

VILRXM
VIHRXM

RXMODE Input Low Voltage
RXMODE Input High Voltage

RXMODE Input Current
IINRXM
..
SWltchmg Characteristics
tpLH,HL
tsKEW
tR,F
tpLH HL
tsEL

Differential Driver Propagation Delay
Differential Driver Output to Output
Differential Driver Rise, Fall Time
Differential Receiver Propagation Delay
Receiver Mode Switching Time

VeM =OV
TA = 25°C

•
•
•

-0.2
-7

•
•
•
•
•

3.5
±7

3

TYP

30
5

lOUT = -1.6mA
lOUT = 1601lA, Vee = 5V
Va = GND or Vee

TA= 25°C
10UT=-4mA
lOUT = 4mA, Vee = 5V
Va = GND or Vee

VIN = OV or Vec
RL = 1000, CL = 100pF (Figures 2,3)
RL = 1000, CL = 100pF (Figures 2,3)
RL = 1000, CL = 100pF (Figures 2,3)
CL = 15pF, (Figures 4)

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maximum ratings are those values beyond which the life
of the device may be impaired.

5-72

MIN

Differential Receiver Threshold
Common-Mode Input Range
Hysteresis
Input Resistance
Output Low Voltage

Short-Circuit Output Current
loss
Single-Ended Receiver
Input Voltage Low Threshold
VL
VIH

CONDITIONS

•
•
•
•

•
•
•
•
•
•

•

0.8
0.1
3
3.5
±7
0.8

MAX

UNITS

0.2

V

7

V

7
0.4

mV
kO
V
V

±85

rnA

1.4
1.8
0.4
5
0.2
4.8

V
2.4
1.0
7
0.4
±85

1.6

V
V
kO
V
-V
rnA
V

2.0

V

±2

IlA

35

100

5
15

35
50
200
100

ns
ns

1.6

110
25

ns
ns
ns

Note 2: All currents into device pins are negative, all currents out of device
pins are positive. All voltages are referenced to ground unless otherwise
specified.
Note 3: All typicals are given at Vee = 5V, TA = 25°C.

LTC1318
TYPICAL PERFORmAnCE CHARACTERISTICS
Charge Pump Output Voltage
vs Load Current

Supply Current vs Temperature
10.0

10

r- Vee = 5V

9.B

;e-

9.6

§. 9.4
Ii 9.2

./

~

""

V

B.B

;!:

'"
w

'":x:'"

B.4

B.O

o

10

20 30 40
50
TEMPERATURE ('C)

60

;!: 2.0
w

TA = 25°C
r--Vee = 5V
ILOAD = v+ TO V-

-2
-4


c..

3.0

f--

'"'"'5:
a:
'"

. . . . r-....

1.5

«
.§. 96
f-94

o

I
10

20
30 40 50
TEMPERATURE (OC)

'-'
f--

"

::;

1\

1\

'-'
U

'"
'"''":x:en'"

10
B

-

=>

'"

-6

~ t:-....

B6
B4

o

10

20
30 40
50
TEMPERATURE (OC)

60

70

60

70

RS232 Driver Short-Circuit
Current vs Temperature
19.5

POSITIVE SWING

I

r- Vee = 5V

:[19.0
~ lB.5

Ise

=>

~ 17.5
::;

-~

~ 17.0
U

-4

Ise+

'"'- 16.5

NEGATIVE SWING

-B

'"~ 16.0
15.5

-10
10000

Ise+

-:::::::: :::--..

.......

~ lB.O

-2

a:

f:::::: ::--.

Ise

20.0

TA = 25°C
Vee = 5V

'"'"'5:

70

BB

B2
10 20 30 40 50 60 70 BO 90 100
LOAD CURRENT (rnA)

-

90

BO

o

60

I

92

o

f--

1\

L7lJ!J~

INPUT LOW (TXri)-

~i~IUT LOt (TXlll, TXlt)

9B _ Vee =5V

0.5

en
f-=>
c..

\

100
1000
CAPACITANCE (pF)

I--

RS422 Driver Short-Circuit
Current vs Temperature

'"'"=>

1.0

'"

\~

10

INPUT HIG1H (Txd)-::::::;

f-1'""

1.0
O.B

tii

z
§

........

10

1.2

15

TA = 25°C
Vee = 5V
ILOAD FROM TXD+,
TXD-TO GND

"

2.0

;!:

I~RSR+

INP~T HI± (TXlll, TXI~.l--

1.4

RS232 Driver Output Swing vs
Resistive Load

III T~Vee=12~!6
= 5V

15

I'-..

2.5

RS232 Driver Slew Rate vs
Load Capacitance

t--

"'

;!: 4.0

10 20 30 40 50 60 70 BO 90 100
LOAD CURRENT (rnA)

25

1.6

I

-

100

4.5

=>

1\

o

1.8

RS422 Driver Single-Ended
Output Swing vs Load Current

z
§

....... r-.,.

o

f--

5.0

"'

~

12

'"~
'">
9
'":x:
ffl
'":x:

Vee = 5V

LOAD CURRENT (rnA)

10

20

---

o

RS422 Driver Differential Output
Swing vs Load Current

o

2.2

'"
:;
c..
f-=>
c..
:;;
=>
c..

B.2

v+

w
=>

V

C>

..J
ll-

,..,

/"

x:
x: 9.0

"

...--

TTL Input Threshold
vs Temperature

1

2
3
4 5 6 7 B 910
RESISTIVE LOAD (kQ)

15.0

o

10

20
30 40
50
TEMPERATURE (OC)

5-73

LTC131B
TYPICAL PERFORmAnCE CHARACTERISTICS
RS232 Receiver IflPut Threshold
vs Temperature

RS422 Receiver Differential
Threshold vs Temperature
2.4

100

Ve6= 5V

90

!

80

INP~T~ ~

w

~ 70

s:

60

~

50

g§

40

:.....- :.....- r-

9

ffi

>-

30
20

....o

--

10

30

'"~

1.8

o

INJuTLdw~ ~

~-"""

20

~ 2.0

w

9
1.6
o
f3

I~PUT H1IGH (~XDO/~X02)

--.---

....-

....f--

1.4 _

II:

j:': 1.2 ---'::IYUT

24

I

Vee=5V

2.2

TTL Output Short-Circuit Current
vs Temperature

rUT

I

Lr

T (l
GH

50

60

70

TEMPERATURE (oG)

0.8

10

20

(RX01)

40

RXOl

r---

gj

18

t:
~

16

r--

<3

(RiDOIRi02)

30

20

II:

~
o

14

en

12

-

~~RX02

:I:

I
o

~
<.:>

1.0
40

22

II:

X01 )

I

I~PUTLOW

Vee = 5V

1

10
50

TEMPERATURE (oG)

60

70

o

10

20

30
40
50
TEMPERATURE (oG)

60

70

1318610

Pin FunCTions
V+ (Pin 1): Charge Pump Positive Output. This pin requires a 0.1 /If capacitor to ground. Under normal operation this pin maintains a voltage of about 8.8V above
ground. An external load can be connected between this
pin and ground or V-.

TXD- (Pin 11): Differential RS422 Driver Inverting Output.

C1+, C1- (Pins 2,3): C1 Inputs. Connect a0.1/lf capacitor
between C1 +and C1-.

RXMODE (Pin 15): This pin controls the state of the
differential/single-ended receiver. When RXMODE is low,
the receiver is in differential mode and will receive RS422
compatible signals at RXD+ and RXD-/RXI2 (pins 8
and 9). When RXMODE goes high, the receiver enters
single-ended mode and will receive RS232 compatible
signals at RXD-/RXI2. RXD+ is disabled in single-ended
mode. Both modes use the RXDO/RX02 pin (pin 17) as
their output.

RXI1 (Pin 4): First RS232 Single-Ended Receiver Input.
This is an inverting receiver.
TX01, TX02 (Pins 5,6): RS232 Single-Ended Driver Outputs.
Vce (Pin 7): Positive Supply Input. Apply 4.75V ~ Vee ~
5.25V to this pin. A 0.1 /If bypass capacitor is required.
RXD+ (Pin 8): When RXMODE (pin 15) is low, this pin acts
as the differential RS422 receiver positive input. When
RXMODE is high, this pin is disabled.
RXD-/RXI2 (Pin 9): When RXMODE (pin 15) is low, this
pin acts as the differential RS422 receiver negative input.
When RXMODE is high, this pin acts as the second RS232
receiver input. The receiver is inverting in RS232 mode.
TXD+ (Pin 10): Differential RS422 Driver Noninverting
Output.

5-74

NC (Pins 12,13): No Internal Connection.
GND (Pins 14, 18): Power Supply Ground. Connect both
pins to each other and to the ground.

TXD (Pin 16): Differential RS422 Driver Input (TIL Compatible).
RXDO/RX02 (Pin 17): This is the outputofthe configurable
differential/single-ended receiver.
TX11, TXI2 (Pins 20, 19): RS232 Driver Inputs (TIL
Compatible). Both are inverting inputs.
RX01 (Pin 21): First RS232 Receiver Outputs (TIL compatible).

LTC1318
Pin FunCTions
C2+, C2- (Pins 22,23): C2 inputs. Connect a0.1 ~ capacitor
between C2+ and C2-.
V- (Pin 24): Charge Pump Negative Output. This pin
requires a0.1 ~ capacitor to ground. Under normal opera-

tion, this pin maintains a voltage of about 8.6V below
ground. An external load can be connected between this
pin and ground or V+.

TEST CIRCUITS
Rt/2

+
Rt/2 Voc

1-

1318F(Jl

Figure 1.

Figure 2.

III

SWITCHinG WAVEFORms
3V

f =1MHz: Ir" IOns: If'; IOns

TXO
OV
Vo

50%
10%

-Vo
TXOVo
TXO+

Figure 3. Differential Driver

VOD2 ----~-__:_~~__:_-~-____..
(RXO+) -

(RXO~~OD2
VOH

'

~IPLHlz'"
1_ ~.,,"*,..,," Woo

\.
!+IPHL

RXOO

_~
1.5V

VOL _ _ _ _---'

1.5V

'--_----=:=

Figure 4. Differential Receiver

L7lJD~

5-75

LTC1318
APPLICATion InFoRmATion
Interface Standards
The LTC1318 provides compatibility with both RS232 and
RS422/AppleTalklLocalTalk standards in a single chip,
enabling a system to communicate using either protocol
as necessary. The LTC1318 provides two RS232 singleended drivers, one RS422 differential driver, and two
receivers. One of the receivers is a dedicated RS232
single-ended receiver, while the other can be configured
for RS232 (single-ended) or RS422 (differential) operation by controlling the logic state of the select pin. All
single-ended drivers and receivers meet the RS232C
specification for output swing, load driving capacity and
input range, and can additionally transmit and receive
signals as high as 100kbaud. The differential driver and
receiver can interface to both RS422 and AppleTalk networks, and can transmit and receive signals at rates
exceeding 2Mbaud.

to the C1 +/C1- and C2+/C2- pins, and two hold caps, one
from V+to ground and one from V- to ground. The charge
pump has enough extra capacity to drive light external
loads and still meet RS232 specifications; it will support a
10mA load from V+ to ground or a 5mA from V+ to V(Figure 5).
5V

Figure 5.

Fault Protection
The LTC1318 incorporates many protection features to
make it as "bustproof" as possible. All driver outputs and
receiver inputs are protected against ESD strikes to ±6kV,
eliminating the need for external protection devices in
most applications. All driver outputs can be taken outside
the power supply rails without damage and will not allow
current to be forced back into the supplies, preventing the
output fault from affecting other logic circuits using the
same power supply. Additionally, the driver outputs enter
a high impedance state when the power is removed,
preventing the system from loading the data lines when it
is shut off. All driver and receiver outputs are protected
against short circuits to ground or to the supply rails.

Charge Pump Power Supply
The LTC1318 includes an on-board charge pump to generate the voltages necessary for true RS232 compatible
output swing. This charge pump requires just four external 0.1 Wcapacitors to operate; two flying caps connected

5-76

Configurable RS422/RS232 Receiver
There are two line receivers in the LTC1318. One is a
dedicated RS232 receiver; the other can receive both
single-ended RS232 signals and differential RS422 signals. This second receiver has two inputs: RXD+ (pin 8)
and RXD- (pin 9) to accept differential signals. The RXD+
input is disabled in single-ended mode. The receiver mode
is set by the RXMODE (pin 15). A low level on RXMODE
configures the receiver in differential mode; it accepts
inputat RXD+ and RXD-and outputs the data at RXDO (pin
17). A high level at RXMODE forces the receiver into
single-ended mode; RXD+ is disabled, pin 9 switches
identity from RXD- to RXI2, and pin 17 switches from
RXDO to RX02, the single-ended data output. In this mode
the receiver accepts RS232 signals at RXI2 and outputs
the data through RX02. The receiver becomes inverting in
single-ended mode. This receiver can switch between its
two modes within 1OOns, allowing the system to sense the
input signal and configure itself accordingly.

~Y~JD~~~~-------Si-~:-~_~3_;V_3
AppleTalk@Transceiver
FEATURES

DESCRIPTion

• Single Chip Provides Complete
LocaITal~/AppleTalk Port
• Operates From a Single 5V Supply
• ESD Protection to ±1 OkV on Receiver Inputs
and Driver Outputs
• Low Power: Icc =2.4mA Typ
• Shutdown Pin Reduces Icc to O.5~ Typ
• Receiver Keep-Alive Function: Icc = 65~ Typ
• Differential Driver Drives Either Differential
AppleTalk or Single-Ended EIA562 Loads
• Drivers Maintain High Impedance in Three-State or
with Power Off
• Thermal Shutdown Protection
• Drivers are Short-Circuit Protected

The LTC@1323 is amulti-protocol line transceiver designed
to operate on AppleTalk or EIA562-compatible singleended networks while operating from asingle 5V supply.
There are two versions ofthe LTC1323 available: a16-pin
version designed to connect to an AppleTalk network,
and a 24-pin version which also includes the additional
single-ended drivers and receivers necessary to create
an Apple-compatible serial port. An on-board charge
pump generates a -5V supply which can be used to
power external devices. Additionally, the 24-pin LTC1323
features a micropower keep-alive mode during which
one ofthe single-ended receivers is kept active to monitor
external wake-up signals. The LTC1323 draws only2.4mA
quiescent current when active, 65~ in receiver keepalive mode, and O.5~ in shutdown, making it ideal for
use in battery-powered systems.

APPLICATions
• LocalTalk Peripherals
• Notebook/Palmtop Computers
• Battery-Powered Systems

D, LTC and LT are registered trademarks of Linear Technology Corporation.
AppleTalk and LocalTalk are registered trademarks of Apple Computer, Inc.

ThedifferentialdrivercandriveeitherdifferentialAppleTalk . .
loads or conventional single-ended loads. The driver ~
outputs three-state when disabled, during shutdown, in
receiver keep-alive mode, or when the power is off. The
driver outputs will maintain high impedance even with
output common-mode voltages beyond the power supply
rails. Both the driver outputs and receiver inputs are
protected againstESD damageto±1 OkV.

TYPICAL APPLICATiOn
LTC1323

50TO 100

50TO 100

IEMIFILTERI=~

"':I:'" 100pF

-----I~
-

~

I

LTCl323·TAOt

5-77

LTC1323
ABSOLUTE mAXimum RATinGS
Supply Voltage (Vee) ................................................ 7V
Input Voltage
Logic Inputs .............................. -O.3V to Vee + O.3V
Receiver Inputs ................................................ ±15V
Driver Output Voltage (Forced) ............................. ±15V

Driver Short-Circuit Duration .......................... Indefinite
Operating Temperature Range .................... O°C to 70°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

ORDER PART
NUMBER

LTC1323CG

LTC1323CS
1XD
1XDEN
SHDN

RXEN

S PACKAGE
16-LEAD PLASTIC SO

G PACKAGE
28·LEAD PLASTIC SSOP
TJMAl( = 150°C, 9JA = 96°C/W
TOP VIEW

ORDER PART
NUMBER
LTC1323CSW

1X1

TXDEN
SHDN

RXEN

SW PACKAGE
2HEAD PLASTIC SO WIDE
TJMAX =125°C, 9JA =85°CIW

Consult factory for Industrial and Military grade parts.

5-78

LTC1323

ELECTRICAL CHARACTERISTICS Vee = 5V ±10%, TA = DoC to 70°C (Notes 2,3)
SYMBOL I PARAMETER
ICDNDITIDNS
I MIN

TYP

MAX

2.4

4

mA

65

100

!lA

0.5

10

!lA

-5

-4.5

UNITS

Supplies
Icc

VEE

Normal Operation Supply Current

No Load. SHON = OV. CPEN = OV. TXOEN = OV.
RXEN =OV

Receiver Keep-Alive Supply Current

No Load. SHDN = OV. CPEN = Vee. TXDEN = OV.
RXEN = OV

Shutdown Supply Current

No Load. SHDN = Vec. CPEN = X. TXDEN = X.
RXEN = OV

Negative Supply Output Voltage

ILOAD ~ 10mA (Note 4).
Vee = 5V. RL = 100n (Figure 1).
TXI = Vee. RTXO = 3k (Figure 5)

•
•
•
•

-5.5

Charge Pump Oscillator Frequency
lose
Differential Driver

200

VOD

Differential Output Voltage

No Load
RL = 100n (Figure 1)

,Woo

Change in Magnitude 01 Differential
Output Voltage

RL = 100n (Figure 1)

•
•

V

kHz

±8
±2

V
0.2

V

3

V

Differential Driver
Voe

Differential Common-Mode
Output Voltage

RL = 100n

Vas

Single-Ended Output Voltage

No Load
RL = 3kto GND

VeMR
Iss

Common-Mode Range

SHDN = Vee or CPEN = Vee or Power Off
-5V ~ Va ~ 5V

loz

Three-State Output Current

Short-Circuit Current

SHDN = Vee or CPEN = Vee or Power Off.
-10V~Vo~10V

•

•
•
•

±4.0
±3.7
35

•

V
V
±10

V

120

500

mA

±2

±200

!lA

Single-Ended Driver (Nole 5)
Vas

Single-Ended Output Voltage

No Load
RL = 3k to GND

VeMR

Common-Mode Range

SHDN = Vee or CPEN = Vee or TXDEN = Vee
or Power Off

Iss

Short-Circuit Current

-5V ~Vo ~ 5V

loz

Three-State Output Current

SHDN = Vce or CPEN = Vee or TXDEN = Vee
or Power Off. -10V ~ Va ~ 10V

Input Resistance

-7V ~VIN ~ 7V

Differential Receiver Threshold Voltage

-7V~VeM~7V

Differential Receiver Input Hysteresis
Single-Ended Input. Low Voltage

-7V~VeM~7V

Single-Ended Input. High Voltage

(Note 5)

VOH

Output High Voltage

10=-4mA

VOL

Output Low Voltage

10 = 4mA

Iss

Output Short-Circuit Current

-5V ~ Va ~ 5V

loz

Output Three-State Current

-5V ~ Va ~ 5V. RXEN = Vee

•
•
•
•
•

±4.5
±3.7

35

V
V
±10

V

220

500

mA

±2

±200

!lA

200

mV

Receivers
RIN

(Note 5)

•
•
•
•
•
•
•
•
•

12

kn

-200
70

mV
0.8

2

V
V

3.5

V

7
±2

0.4

V

85

mA

±100

!lA

5-79

II

LTC1323
ELECTRICAL CHARACTERISTICS Vee = 5V ±10%, TA = DoC to 70°C (Notes 2 and 3)
SYMBOL I PARAMETER
ICONDITIONS
MIN

TYP

MAX

UNITS

0.8

V

±20

!lA

Logie Inputs
VIH

Input High Voltage

All Logic Input Pins

Input Low Voltage

All Logic Input Pins

VIL
Input Current
Ie
Switching Characteristics
Differential Driver Propagation Delay
tpLH, tpHL
Differential Driver Propagation Delay
with Single-Ended Load

tHDIS, tLDIS

tENH, tENL

VEER

RL =100n, CL =100pF (Figures 2, 7)
RL =3k, CL =1OOpF (Figures 3, 9)

Single-Ended Driver Propagation Delay

RL =3k, CL =100pF, (Figures 5,10) (Note 5)

Differential Receiver Propagation Delay

CL =15pF (Figures 2, 11)
CL =15pF (Figures 6, 12) (Note 5)

Single-Ended Receiver
Propagation Delay

tSKEW
tr,t,

All LogiC Input Pins

Inverting Receiver Propagation Delay
in Keep-Alive Mode,
SHDN =OV, CPEN =Vee
Differential Driver Output to Output
Differential Driver Rise/Fall Time

CL =15pF (Figures 6, 12) (Note 5)

RL =100n, CL =100pF (Figures 2, 7)
RL = 100n, CL =100pF (Figures 2, 7)

Differential Driver Rise/Fall Time
with Single-Ended Load

RL =3k, CL =100pF (Figures 3, 9)

Single-Ended Driver Rise/Fall Time

RL =3k, CL = 100pF (Figures 5, 10) (Note 5)

Differential Driver Output Active
to Disable

CL =15pF (Figures 4, 8)

Any Receiver Output Active to Disable

CL =15pF (Figures 4, 13)

Differential Driver
Enable to Output Active

CL =15pF (Figures 4, 8)

Any Receiver, Enable to Output Active

CL =15pF (Figures 4,13)

Supply Rise Time from Shutdown
or Receiver Keep-Alive

C1

=C2 =0.33~, CVEE =1~

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maKimum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified,

5-80

•
•
•
•
•

•
•
•
•

•
•
•
•
•
•

•
•
•

2.0

V
±1.0
40

120

ns

120

180

ns

40

120

ns

70
70

160
160

ns
ns

150

600

ns

10

50

50

150

ns
ns

50

150

ns

15

80

ns

180

250

ns

30

100

ns

180

250

ns

30

100

0.2

Note 3: All typicals are given at Vee = 5V, TA = 25°C.
Note 4: ILOAD is an external current being sunk into the VEE pin.
Note 5: These specifications apply to the 24-pin SO Wide package only.

ns
ms

LTC1323
TYPICAL PERFORmAnCE CHARACTERISTICS
Charge Pump Output Voltage
vs Load Current
-2.0

TA = 25'C
Vs = 5V
RL(Dlff) = 100Q
RL(SE) = 3k TO GND
VTXI = 5V

~-2.5
w

'"~ -3.0
o
;:: -3.5

/

"'~-4.0

o

/

I-

::J

0

a:
0

-3
-4

o

10
15
20
LOAD CURRENT (rnA)

25

30

'-'

~ 2.25

"'-

::J

TA = 25'C
Vs= 5V

~

"'

-4

'"z

I'

-3

V
,/

-5
50 100 200 300 500 1k 2k 3k
LOAD RESISTANCE (Q)

5k 10k

5k 10k

Single-Ended Driver Swing
vs Temperature

5.0
Vs = 5V
NO LOAD

:;;-

4.5

Vs =5V
RL = 100Q

I-

1"-

"'- """-...1'--

/

/

::J

"'-

I-

3.5

::J

0

0

"!;!

>

cr: 3.0

a:
0

ffi

a:
0

2.5

fil -1

;;! 2.0

>=
i'5

~
is

'" 2.00
1.75
1.50
-50 -25

"'-

I-

0

~

1.5
1.0

'"zU5

0.5

o '----L_'-----'-----'_--'-_'----'
25
50
75
TEMPERATURE eCI

100

125

-50 -25

II

::J

::J

I

VS=5V
RL =3kTOGND

~

;:: 4.0

.5.
§§ 2.50

-1

-2

Differential Driver Swing
vs Temperature

« 3.00
cr:

fil

0

50 100 200 300 500 1k 2k 3k
LOAD RESISTANCE (Q)

3.50

~ 2.75

a:
0

I

I--

-5

Supply Current vs Temperature
3.25

/

cr:

tt

>

V

--' -1
«
>=
i'5 -2

is

ffi

/'"

>

cr:

..........

"'-

ffi

«
[3 -5.5
-6.0

"'I-

::J

0

/

TA I 25'6
Vs = 5V

~
I-

::J

/

~ -4.5

"'~ -5.0

.......

~
I-

::J

::J

::J

Single-Ended Driver Swing
vs Load Resistance

Differential Driver Swing
vs Load Resistance

0
25
50
75
TEMPERATURE ('C)

100

125

-2
-3

-4

-5

I'--

-50 -25

0
25
50
75
TEMPERATURE ('C)

100

125

LTC1J23·TPC06

5-81

LTC 1323

Pin FunCTions
LTC1323CS

LTC1323CSW

LTC1323CG

C1+

Vee

G1+

Vee

G1+

G1-

G2+

G1-

G2+

G1-

G2+

TXO

G2-

GPEN

G2-

GPEN

G2-

VEE

TXO

VEE

TXOEN

Vee

TXO

NG

SHON

TXO-

TXI

TXO-

TXI

NG

RXEN

TXO+

TXOEN

TXO+

TXDEN

RXOO

RXO-

SHON

TXO

SHON

TXO-

GNO

RXO+

RXEN

RXi

RXEN

TXO+

RXO

RXI

RXO

TXO

RXO

RXO-

RXO

RXi

RXOO

RXO+

RXOO

RXI

GNO

PGNO

C1+: C1 Positive Input. Connect a O.33j.1f capacitor between C1 +and C1-.
C1-: C1 Negative Input. Connect a O.33j.1f capacitor between C1+ and C1-.
CPEN: TTL Level Charge Pump Enable Input. With CPEN
held low, the charge pump is enabled and the chip operates normally. When CPEN is pulled high, the charge
pump is disabled as well as both drivers, the noninverting
single-ended receiver, and the differential receiver. The
inverting single-ended receiver (RXI) is kept alive to
monitor the control line and Icc drops to 65~. To turn
off the receiver and drop Icc to O.5~, pull the SHDN pin
high.
TXD: Differential Driver Input (TTL compatible).
TXI: Single-Ended Driver Input (TTL compatible).
TXDEN: Differential Driver Output Enable (TTL compatible). A high level on this pin forces the differential driver
into three-state; a low level enables the driver. This input
does not affect the Single-ended driver.
SHDN: Shutdown Input (TTL compatible). When this pin
is high, the chip is shut down. All driver and receiver
outputs are three-state, the charge pump turns off, and the
supply current drops to O.5~. A low level on this pin
allows normal operation.

5-82

VEE

NG

RXO-

NG

RXO+

GNO

PGNO

RXEN: Receiver Enable (TTL compatible).A high level
on this pin disables the receivers and three-states the
logic outputs; a low level allows normal operation.
RXO: Inverting Single-Ended Receiver Output. Remains
active in the receiver keep-alive mode.
RXO: Noninverting Single-Ended Receiver Output.
RXDO: Differential Receiver Output.
GND: Signal Ground. Connect to PGND with 24-pin
package.
PGND: Power ground is connected internally to the charge
pump and differential driver. Connect to the GND pin.
RXD+: Differential Receiver Noninverting Input. When this
pin is ~ 200mV above RXD-, RXDO will be high; when this
pin is ~200mV below RXD-, RXDO will be low ..
RXD-: Differential Receiver Inverting Input.
RXI: Noninverting Receiver Input. This input controls the
RXO output.
RXI: Inverting Receiver Input. This input controls the RXO
output. In receiver keep-alive mode (CPEN high, SHDN
low), this receiver can be used to monitor a wake-up
control signal.

LTC1323
Pin FunCTions
TXO: Single-Ended Driver Output.

C2-: C2 Negative Input. Connect a O.33W capacitor
between C2+ and C2-.

TXD+: Differential Driver Noninverting Output.
TXD-: Differential Driver Inverting Output.

C2+: C2 Positive Input. Connect a O.331lF capacitor
between C2+ and C2-.

VEE: Negative Supply Charge Pump Output. Requires a
1Wbypass capacitor to ground. If an external load is
connected to the VEE pin, the bypass capacitor value
should be increased to 4.7W.

Vcc: Positive Supply Input. 4.5V '5, Vee '5, 5.5V. Requires a
1Wbypass capacitor to ground.

TEST CIRCUITS
TXO+--,--,

R

Vae

15pF

1

lTC1323of02

Figure 1

-=-

Figure 2

Figure 3

Vee

!

-rY
Tel
500n

OUTPUT

-

~~

S1

~~ ~~

~2
-

--

Figure 4

Figure 5

--

Figure 6

SWITCHinG WAVEFORms
3V

f = 1MHz: lr $1 Ons: If $1 Ons

TXO

ov
Va

90%

VDIFF = V(TXO+) ~ V(TXO~)

-Va
TXO~

-----l...--------,¥*----------.----'T_--------)f-)(,..---Va

TXO+

-I1_1SKEW

-II-ISKEW

Figure 7. Differential Driver

5-83

LTC 1323
SWITCHinG WAVEFORms
3 V - - -....

oV--------~~--f~=~I~MH~Z~:I~rS~I~On~s:~q~s~10~n~s---'
5V---~-ILZh
TXO+, TXOVOL ________1-_____'\._.....:;O;;,;UT~P;;,;UT~N:.:;O:.::RM;,;;.A;:;LL~Y..:L;;,;OW;,;,..-__
0,5V

VOH

OUTPUT NORMALLY HIGH

[-1HZ

t

+0.5V

--------------t-,-.....:;;;.;,;".;;.;..;;~;;;.;;;;;;.;..;.;;.;;.;.--__,j - -

TXO-, TXO+

OV------J

Figure 8. Differential Driver Enable and Disable

3V---------,--~~~~~~~-~

1.5V

TXO

f= IMHz: IrS IOns: IfS IOns

1.5V

OV---J
IpHLVOH------"'"
TXO'\ OV
VOL

J

'\

~V

~H--------------r4~9=0~%--------n9ruO%~,LI

TXO+
VOL

10%0,¥,

-----.:.::.::Jf

-.1

tr . -

3V---------,-_ _ _ _ _ _ _ _ _

~

Figure 9. Differential Driver With Single-Ended Load

f = IMHz: Ir S IOns: If S IOns

TXI
OV---J
VOH-----=~

TXO

LTC1323'F10

VOL------------~-r~~-------~~~

Figure 10. Single-Ended Driver

VOD2 ---------~----------___..
(RXO+) _ (RXO-)
f = IMHz: Ir'; IOns: If', IOns
-VOD2---"

VOH----------I-PL-H=R+-I----------IP-HL-~

RXOO
VOL _ _ _ _ _ _.J

1.5V

Figure 11. Differential Receiver

5-84

1.5V
'--_ _ __

LTC 1323
SWITCHinG WAVEFORms
VIH

RXI,

----r-----------...
1,5V

RXi

f=IMHz:lr ,,10ns:lf,,10ns

VOH----"""

2.4V

RXi
VOL - - - - - - 1 ' - = ' -_ _ _ _ _ _ _- '

VIH

RXI

------+,.------------...

V _ _ _ _- - J

1,5V

1,5V

Figure 12. Single-Ended Receiver
3V _ _.....

W _ _ _~~---f=-IM-HZ-:I~r"-10-ns~:4-"1-0n-s-J
5V---"---

IlZ1

RXO, RXO, RXDO
VOL - - - f - - - - - ,-_,;.;;OU.;.;.TP.;;.;UT..;,;,NO""R;,;;;.MA;;;;;LL"",YL;;,;,.OW;.;......-;_

.
O,5V

t.
VOH ------+,,--....:.;;.;.;,.;;.;.==:..;.:;.;:;;;......:.--.I-- O,5V
OUTPUT NORMALLY HIGH

!-IHZ-

~~~
OV

---LTC132S·F13

Figure 13. Receiver Enable and Disable

APPLICATions InFORmATion
Functional Description

The "serial port" on the back of an Apple-compatible
computer or peripheral is afairly versatile "multi-protocol"
connector. It must be able to connect to awide bandwidth
LAN (an AppleTalkiLocalTalk network), which requires a
high speed differential transceiver to meet the AppleTalk
specification, and it must also be able to connect directly to
a printer or modem through a short RS232 style link. The
LTC1323 is designed to provide all the functions necessary
to implement such a port on asingle chip. Two versions of
the LTC1323 are available: a 16-pin SO version which
provides the minimum solution for interfaCing to an
AppleTalk network in asmaller package, and alarger24-pin
SO Wide version which additionally includes all the handshaking lines required to implement acomplete AppleTalki
modem/printer serial port. All LTC1323s run from asingle
5V power supply while providing true single-ended compatibility, and include a O.5~ low power shutdown mode

to improve lifetime in battery-powered devices. The 24pin SO Wide version also includes a receiver keep-alive
mode for monitoring external signals while drawing 65~
typically.
The LTC1323 includes an RS422-compatible differential
driver/receiver pair for data transmission, with the driver
specified to drive 2V into the 100Q primary of a typical
LocalTalk interface transformer/RFI interference network.
Either output ofthe differential RS422 driver can also act as
an single-ended driver, allowing the LTC1323 to communicate over a standard serial connection. The 24-pin SO
Wide LTC1323 also includes an extra single ended only
driver and two extra RS232-compatible single-ended receivers for handshaking lines. All versions include an onboard charge pump to provide a regulated -5V supply
required for the single-ended drivers. The charge pump
can also provide up to 10mA of external load current to
power other circuitry.

5-85

LTC1323
APPLICATions InFoRmATion
Driving Differential AppleTalk or Single-Ended Loads

Power Shutdown

The differential driver is able to drive either an AppleTalk
load or a single-ended load such as a printer or modem.
With a differential AppleTalk load, TXD+ and TXD- will
typically swing between 1.2V and 3.SV (Figure 14a). With
a single-ended 3k load such as a printer, either TXD+ or
TXD- will meet the single-ended voltage swing requirement of±3.7V (Figure 14b). An automatic switching circuit
prevents the differential driverfrom overloading the charge
pump if the outputs are shorted to ground while driving
single-ended signals. This allows the second single-ended
driver to continue to operate normally when the first is
shorted, and allows external circuitry attached to the charge
pump output to continue to operate even if there are faults
at the driver outputs.

The power shutdown feature ofthe LTC1323 is designed
for battery-powered systems. When SHDN is forced
high the part enters shutdown mode. In shutdown the
supply current typically drops from 2.4mA to O.S!lA, the
charge pump turns off, and the driver and receiver
outputs are three-stated.

Vee = 5V

Receiver Keep-Alive Mode (24-Pin SO Wide Only)
The 24-pin SO Wide version of the LTC1323 also features
a power saving receiver keep-alive mode. When CPEN is
pulled high the charge pump is turned off and the outputs
of both drivers, the noninverting single-ended receiver and
the differential receiver are forced into three-state. The
inverting single-ended receiver (RXI) is kept alive with Icc
dropping to 6S!lA and the receiver delay time increasing to
a maximum of 400ns. The receiver can then be used to
monitor a wake-up control signal.
Charge Pump Capacitors and Supply Bypassing

Figure 14

Thermal Shutdown Protection
The LTC1323 includes a thermal shutdown circuit which
protects against prolonged shorts at the driver outputs. If
adriver output is shorted to another output orto the power
supply, the current will be initially limited to amaximum of
SOOmA. When the die temperature rises above 1SO°C, the
thermal shutdown circuit disables the driver outputs.
When the die cools to about 130°C, the outputs are reenabled. If the short still exists, the part will heat again and
the cycle will repeat. This oscillation occurs at about 10Hz
and prevents the part from being damaged by excessive
power dissipation. When the short is removed, the part will
return to normal operation.

5-86

The LTC1323 requires two external O.33W capacitors for
the charge pump to operate: one from C1+ to C1- and one
from C2+ to C2-. These capacitors should be low ESR
types and should be mounted as close as possible to the
LTC1323. Monolithic ceramic capacitors work well in this
application. Do not use capacitors greater than 2W at the
charge pump pins or internal peak currents can rise to
destructive levels. The LTC1323 also requires that both Vee
and VEE be well bypassed to ensure proper charge pump
operation and prevent data errors. A 1W capacitor from
Vee to ground is adequate. A1Wcapacitor is required from
VEE to ground and should be increased to 4.7W if an
external load is connected to the VEE pin. Ceramic or
tantalum capacitors are adequate for power supply bypassing; aluminum electrolytic capacitors should only be
used if their ESR is low enough for proper charge pump
operation. Inadequate bypass or charge pump capacitors
will cause the charge pump output to go out of regulation
prematurely, degrading the output swing at the SINGLEENDED driver outputs.

LTC1323
APPLICATions InFoRmATion
the LTC1323 uses a single supply differential driver, the
resistor values should be reduced to 50 to 100 to guarantee adequate voltage swing on the cable (Figure 16a). In
most applications, removing the resistors completely does
not cause an increase in EM I as long as ashielded connector and cable are used (Figure 16b). With the resistors
removed the only DC load is the primary resistance of the
LocalTalk transformer. This will increase the DC standby
current when the driver outputs are active, but does not
adversely affect the drivers because they can handle a
direct indefinite short circuits without damage. Transformer primary resistance should be above 150 to keep the
LTC1323 operating normally and prevent it from entering
thermal shutdown. For maximum swing and EMI immunity, a ferrite bead and capacitor T network can be used
(Figure 16c).

Driving an External Load from VEE
An external load may be connected between ground and
the VEE pin as shown in Figure 15. The LTC1323 VEE pin
will sink up to a maximum of 1OmA while maintaining the
pin voltage between -4.5Vand -5.5V.lf an external load
is connected, the VEE bypass capacitor should be i~­
creased to 4.7f.lF. Both LTC1323 and the external chip
should have separate Vee bypass capacitors but can
share the VEE capacitor.
EMI Filter
Most LocalTalk applications use an electromagnetic interference (EMI) filter consisting of a reSistor-capacitor T
network between each driver and receiver and the connector. Unfortunately, the resistors significantly attenuate the
drivers output signals before they reach the cable. Because

5!HO 100

FERRITE BEAD

50 TO 100

FERRITE BEAD

~ $100PF~

Vee = 5V

(a)

(c)

(b)

11I

Figure 16. EMI Filters

Figure 15

TYPICAL APPLICATiOn
Typical LocalTalk Connection
5V

0.33!lF

12011

.::....-_....-_--'UC1323.TAIl2

5-87

NOTES

5-88

INDEX
SECTION 5-INTERFACE
INFRARED
LT1319, Multiple Modulation Standard Infrared Receiver .................................................................... 5-90

5-89

I~TLElcnHNt1\OI'O-G~~~----------U_13_19
~,
~
Multiple Modulation Standard
IT

Infrared Receiver
FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•
•

The L~1319 is a general purpose building block that
contains all the circuitry necessary to transform modulated photodiode signals back to digital signals. The
circuit's flexibility permits it to receive multiple modulation
methods. A low noise, high frequency preamplifier performs acurrent-to-voltage conversion while rejecting low
frequency ambient interference with an AC coupling loop.
Two separate high impedance filter buffer inputs are
provided so that off-chip filtering can be tailored for
specific modulation schemes. The filter buffers drive separate differential gain stages that end in comparators with
internal hysteresis. The comparator thresholds are adjustable externally by the current into pin 11. One channel has
ahigh speed 25ns comparator required for high data rates.
The second channel's comparator has a 60ns response
time and is well suited to more modest data rates. Apower
saving shutdown feature is useful in portable applications.

Receives Multiple IR Modulation Methods
Low Noise, High Speed Preamp: 2pA/~, 7MHz
Low Frequency Ambient Rejection Loops
Dual Gain Channels: 8MHz, 400V/V
25ns and 60ns Comparators
16-Lead SO Package
5V Single Supply Operation
Supply Current: 14mA
Shutdown Supply Current: 500~
External Comparator Threshold Setting

mODULATion STAnDARDS
•
•
•
•

IRDA: SIR, FIR
Sharp/Newton
TV Remote
High Data Rate Modulation Methods

D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
IRDA and Sharp/Newton Data Receiver
. . . . - - - - SHUTDOWN INPUT
r - - - - I R D A DATA
. . . . - - - SHARP/NEWTON DATA

....---Vcc

~

01'"

• BPW34FA OR BPV22NF

LT1319-TA01

-

DGND

5-90

AGND

LT1319
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

Total Supply Voltage (Vcc to GND) ........................... 6V
Differential Voltage (Any Two Pins) .......................... 6V
Maximum Junction Temperature ......................... 150°C
Operating Temperature Range .................... ooe to 70°C
Specified Temperature Range ..................... ooe to 70°C
Storage Temperature Range ............... ; -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER
LT131ges

SPACKAGE
16-LEAD PLASTIC SO
TJMAX = 150°C, 9JA = 100°C/W

Consult factory for Industrial or Military grade parts.

ELECTRICAL CHARACTERISTICS

TA =25°C, VI5 =5V, VI =V12 =OV, Vs =Va =V14 =2V, unless otherwise specified.
SYMBOL
Vas

Avp

BWp
in

VBIAS
VBYPASS
IB
RIN

AVG
BWG
t,
VHYS
VOH
VOL

PARAMETER
Preamp Input Offset Voltage
Preamp Output Offset Voltage
Preamp Loop Offset Voltage
High Gain Loop Offset Voltage
Low Gain Loop Offset Voltage
Preamp Transimpedance
Preamp Output Swing, Positive
Preamp Output Swing, Negative
Preamp Bandwidth
Preamp Input Noise Current
Preamp Loop Rejection, Positive
Preamp Loop Rejection, Negative
Preamp Loop Output Current, Positive
Preamp Loop Output Current, Negative
Bias Voltage
Bypass Voltage
Filter Buffer Input Bias Current
Filter Buffer Input Resistance
Gain Stage Loop Rejection, Positive
Gain Stage Loop Rejection, Negative
Gain Stages Voltage Gain
Gain Stages Bandwidth
Fast Comparator Response Time
Slow Comparator Response Time
Fast Comparator Hysteresis Voltage
Slow Comparator Hysteresis Voltage
Fast Comparator Output High Voltage
Slow Comparator Output High Voltage
Fast Comparator Output Low Voltage
Slow Comparator Output Low Voltage

CONDITIONS
V (Pin 2) - V (Pin 5)
V (Pin 4) - V (Pin 5)
V (Pin 3) - V (Pin 5)
V (Pin 9) - V (Pin 5)
V (Pin 7) - V (Pin 5)
±1011A Into Pin 2,Measure tN (Pin 4), Fix Pin 3
10011A Out of Pin 2, Measure AV (Pin 4), Fix Pin 3
10011A Into Pin 2, Measure IW (Pin 4), Fix Pin 3
C(Pin 3) = 1!1f, Measure L3dB
C(Pin 3) = V, f = 10kHz
5011A Into Pin 2, Measure AV (Pin 4)
5011A Out of Pin 2, Measure AV (Pin 4)
10011A Out of Pin 2, Measure I (Pin 3), (Note 1)
10011A Into Pin 2, Measure I (Pin 3), (Note 1)
V (Pin 5)
V (Pin 16)
I (Pin 6), I (Pin 8)
AV = O.IV, Measure AlB Pin 6, Pin 8
AV = 50mV (Pin 6, Pin 8), Measure AV (Pin 7, Pin 9)
AV = -50mV (Pin 6, Pin 8), Measure AV (Pin 7, Pin 9)
(Note 2)
C(Pin 7) = C(Pin 9) = 1!If
10mV Overdrive
10mV Overdrive
(Note 3)
(Note 3)
AV (Pin 9) =-200mV, lmA Out of Pin 10 (Note 4)
AV (Pin 7) =-200mV, O.lmA Out of Pin 13 (Note 4)
AV (Pin 9) = 200mV, 80011A Into Pin 10
AV (Pin 7) = 200mV, 80011A Into Pin 13

MIN

50
600
600
10
0.25
-0.55

-3
-3
-150
50
1.7
4.75
0.1
0,33
-0.57

2.4
2.4

TYP
4
10
150
800
800
15
0.4
-0.4
7
2
-1
1
-100
100
1.9
4.9
0.5
40
0.45
-0.45
400
8
25
60
35
40
3.5
3.9
0.35
0.39

MAX
15
25
250
950
950
17
0.55
-0.25

3
3
-50
150
2.1
4.95
1.4
0.57
-0.33

0.5
0.5

UNITS
mV
mV
mV
mV
mV
kn
V
V
MHz
pA/-YHz
mV
mV

IIA
IIA
V
V

IIA
Mn
V
V
VIV
MHz
ns
ns
mV
mV
V
V
V
V

5-91

II

LT1319

ELECTRICAL CHARACTERISTICS

Tp 25°C, V15 =5V, V1 =V12 =OV, V6 =Va =V14 =2V, unless otherwise specified.
SYMBOL
VTH
VIH
VIL
IIH
IlL
Is
ISHDN

PARAMETER
Threshold Transimpedance
Threshold External Voltage
Shutdown Input High Voltage
Shutdown Input Low Voltage
Shutdown Input High Current
Shutdown Input Low Current
Supply Current
Supply Current in Shutdown

CONDITIONS
1001lA Into Pin 11 (Note 5)
1001lA Into Pin 11,V (Pin 11)

MIN

V (Pin 14) =2.4V
V (Pin 14) =OAV
V (Pin 14) =2V
V (Pin 14) =O.BV, V (Pin 6) =V (Pin B) =OV

-140
-400
10
300

-60
-260
14
500

MIN

TYP
4
10
150
BOO
BOO
15
0.4
-0.4
-1
1
-100
100
1.9
4.9
0.5
0.45
-0.45
3.5
3.9
0.35
0.39
0.9

O.B
2

TYP
2
0.9

MAX
1.2
O.B
-10
-130
1B
BOO

UNITS
kn
V
V
V
IlA
IlA
rnA
IlA

O°C:5 TA:5 70°C, V15 =5V, V1 =V12 =OV, V6 =Va =V14 =2V, unless otherwise specified.
SYMBOL
Vos

Avp

VBIAS
VBYPASS
IB

VOH
VOL
VTH
VIH
VIL
IIH
IlL
Is
ISHDN

PARAMETER
Preamp Input Offset Voltage
Preamp Output Offset Voltage
Preamp Loop Offset Voltage
High Gain Loop Offset Voltage
Low Gain Loop Offset Voltage
Preamp Transimpedance
Preamp Output Swing, Positive
Preamp Output Swing, Negative
Preamp Loop Rejection, Positive
Preamp Loop Rejection, Negative
Preamp Loop Output Current, Positive
Preamp Loop Output Current, Negative
Bias Voltage
Bypass Voltage
Filter Buffer Input Bias Current
Gain Stage Loop Rejection, Positive
Gain Stage Loop Rejection, Negative
Fast Comparator Output High Voltage
Slow Comparator Output High Voltage
Fast Comparator Output Low Voltage
Slow Comparator Output Low Voltage
Threshold External Voltage
Shutdown Input High Voltage
Shutdown Input Low Voltage
Shutdown Input High Current
Shutdown Input Low Current
Supply Current
Supply Current in Shutdown

CONDITIONS
V (Pin 2) - V (Pin 5)
V (Pin 4) - V (Pin 5)
V (Pin 3) - V (Pin 5)
V (Pin 9) - V (Pin 5)
V (Pin 7) - V (Pin 5)
±101lA Into Pin 2, Measure t:.V (Pin 4)
1001lA Out of Pin 2, Measure t:.V (Pin 4)
1001lA Into Pin 2, Measure t:.V (Pin 4)
501lA Into Pin 2, Measure t:.V (Pin 4)
501lA Out of Pin 2, Measure t:.V (Pin 4)
1001lA Out of Pin 2, Measure I (Pin 3), (Note 1)
1001lA Into Pin 2, Measure I (Pin 3), (Note 1)
V (Pin 5)
V (Pin 16)
I (Pin 6), I (Pin B)
t:.V =50mV (Pin 6, Pin B), Measure t:.V (Pin 7, Pin 9)
t:.V =-50mV (Pin 6, Pin B), Measure t:.V (Pin 7, Pin 9)
t:.V (Pin 9) =-200mV, 1rnA Out of Pin 10 (Note 4)
t:.V (Pin 7) =-200mV, 0.1mA Out of Pin 13 (Note 4)
t:.V (Pin 9) =200mV, BOOIlA Into Pin 10
t:.V (Pin 7) =200mV, BOOIlA Into Pin 13
1001lA Into Pin 11, V (Pin 11)

30
400
400
B.5
0.2
-0.6
-3.5
-3.5
-160
40
1.5
4.7
0.05
0.3
-0.6
2.4
2.4

V (Pin 14) =2.4V
V (Pin 14) =OAV
V (Pin 14) =2V
V (Pin 14) =O.BV, V (Pin 6) =V (Pin B) =OV

-160
-450
9
200

0.7
2

-60
-260
14
500

MAX
17
27
350
1200
1200
1B.5
0.6
-0.2
3.5
3.5
-40
160
2.3
4.97
1.6
0.6
-0.3

UNITS
mV
mV
mV
mV
mV
kn
V
V
mV
mV

0.5
0.5
1.3
O.B
0
-BO
20
900

IlA
IlA
V
V
IlA
V
V
V
V
V
V
V
V
V
IlA
IlA
rnA
IlA

Nole 1: Measure V (Pin 3) without input current for pin 2. Force pin 3to

Nole 4: Measure V (Pin 7) and V (Pin 9). Force these voltages to 200mV

this measured voltage (which disables the preamp loop). Measure the
current into and out of Pin 3 when Pin 2 is driven.
Nole 2: The gain is the differential voltage at the comparator inputs divided
by the differential voltage between the filter buffer output and VBIAS. This
parameter is not tested.
Nole 3: Hysteresis is the difference in comparator trip point measured
when the output is high and when the output is low. This parameter is
not tested.

below their nominal value to switch the comparators high.
Nole 5: The current into Pin 11 is multiplied by 4 and then applied to a
soon resistor on the positive comparator inputs. The threshold is
I (Pin 11) x 4 x soon.

5-92

LT1319
rYPICAL PERFORmAnCE CHARACTERISTICS
Preamp Highpass vs
Capacitance on FIL11

Preamp Frequency Response vs
Input Capacitance

Gain Stage Highpass vs
Capacitance on FILT2 or FILT2L

1000

1000

TA = 25°C

TA - 25°C

[

3

~
;

[

2
1

~

~

0

Jd:

-1

TotF

100

u::
z
0

§

10

w

~

'-'
Z

30pF

;::
13
;;;:

-2

~

«

-3

'-'

-4
-5
100k

1M

10M

20

TA = 25;~

i

10k

100k

TA~25JC

100k

~

I)

30PFI'

~

Ir

1M

1

1M

1k

10k

a:
a:
'-'
~

10M

"-

FREQUENCY (Hz)

1M

10M

FILTIN- or FILTINL- Referred
Threshold Voltage vs RT1
.....

RflLTER=1k

•

:> 0.9
oS

15

w

'"~

V

10

V

5

o

1

FILTER CUTOFF FREQUENCY (MHz)

~

0.7

"f--

0.6

"a:
ffi

-I-

0.1

0.8

~

/

'"
100M

100k

HIGHPASS CORNER FREQUENCY (Hz)

1.0

:::>

50

10

I

oz

,; 100

10k

1k

~

w

50pF

o

13

~

en

150

,

!

w
'-'
Z

;::

Input-Referred Noise vs
Lowpass Filler on PREOUT
"[

~

u::
z
o

HIGHPASS CORNER FREQUENCY (Hz)

Preamp Output Noise vs
Input Capacitance

~

~ 100

•

0.1
100

100M

FREQUENCY (Hz)

250

TA = 25°C

10

0.5

~

'"
20

30

i"'-,.

""" ~

40

RT1 (k.Q)

:IRCUIT DESCRIPTiOn
·he LT1319 is a general purpose low noise, high speed,
ligh gain, infrared receiver designed to easily provide IR
:ommunications with portable computers, PDAs, desktop
:omputers and peripherals. The receiver takes the photourrent from an infrared photodiode (Siemens BPW34FA
Ir Temic BPV22NF) and performs a current-to-voltage
onversion. After external filtering that is tailored for the
iesired communication standard, two filter buffers are
lrovided. There are dual gain chains with nominal gain of
·OOVIVthatfeed internal comparators with hysteresis. The
omparatorthresholds are set externally with acurrent into
1e VTH pin. The high frequency comparator has a reponse time of 25ns and is well-suited to high data rates.

L7lJ!J~

The low frequency comparator responds in 60ns and is
useful for more modest data rates such as Sharp/Newton
and IRDA-SI R. The circuit also contains shutdown circuitry
to reduce power consumption. Rejection of ambient interference is accomplished with AC coupling loops around the
preamp and the two gain stages. The rejection frequency is
set with an internal resistor and an external capacitor to
ground. This feature allows changing of the break frequency by simply switching in additional capacitors. To aid
in rejection of power supply noise there is internal supply
regulation and a fully differential topology after the filter
buffers.

5-93

LT1319
BLOCK DIAGRAm
BYPASS

RS3

20k

RFB
15k

RF2
2k

VB lAS

RFl
1k

RS2

5V

20k

GM2

5V

+ CF3
"*100 PF

CF4
+
2.2nF"*

+ CF5
~l1'F

NOTE: EXTERNAL COMPONENTS ARE SHOWN FOR AN IRDA AND SHARPINEWTON DATA RECEIVER.
LT\319'SO

5-94

-

LT1319
~PPLICATlons

InFORmATion

.ayout and Passive Components
rhe LT1319 requires carefullayouttechniques to minimize
larasitic signal coupling to the preamp input. A sample
loard layoutforthe circuit on the first page is shown in the
rypical Application section. The lead lengths on the photoliode must be as short as possible to Pin 2. Shielding is
ecommended overthe entire circuit. Aground plane must
Ie used and connected to Pin 1. The ground plane should
lxtend under the package and surround Pins 1to 9and Pin
16. A single point connection should be made to the
jround plane at Pin 12 (DIG_GND). The leads on Pins 6and
I should be short to prevent pickup into the gain stages.
rhe comparator output leads (Pins 10 and 13) should be
IS short as possible to minimize coupling back to the input
ria parasitic capacitance.
;apacitance on Pin 10 should be minimized as the comJarator output is pulled up by an internal 5k resistor. The
Issociated digital Circuitry should be located on the oppo,ite side of the PC board from the LT1319 or separated as
nuch as possible if on the same side of the board. Filter
:omponents should be located on the analog ground s!de
Jf the package. Bypass capacitors should be used on Pms
i, 11, 15 and 16 for best supply rejection.

'reamp
'he LT1319 preamp is a low noise, high speed current-to'oltage converter that has been optimized for an inp~t
:apacitance of 30pF (which corresponds to the capaclance of the above-mentioned photodiodes with approxinately 2V of back bias). A range of OpF to 50pF is
.cceptable. The amplifier obtains high bandwidth by pro'iding alow impedance input so thatthe input current is not
iltered by the photodiode capacitance.
'he dynamic range of the circuit will be limited at the low
!nd by the input-referred current noise of the preamplifier
nd the desired signal-to-noise ratio. At the other extreme
Ifthe dynamic range for very large input signals, the output
If the preamp is clamped by Schottky diodes across the
gedback resistor.
'he noise bandwidth is shaped by filtering at the output of
he preamplifier and by the AC coupling loop. The i~put
apacitance causes noise peaking for high bandWidth
pplications. Noise peaking can be explained by consider-

L7lJ!J~

ing the voltage noise gain. Referring to the Block Diagram,
at frequencies beyond the corner frequency of the AC
coupling loop, the preamp is in a noise gain of 2.5 due to
the ratio of (RFB + RL1 )/RL1' At high frequencies the input
capacitance approaches the same impedance as RL1 so the
noise gain increases. For example, at 500kHz the 30pF
input capacitance looks like 10.6kQ which increases the
noise gain to almost 4. The preamp is compensated to
provide aflat current-to-voltage frequency response with a
-3dB corner at 7MHz. The input current noise peaks up
considerably iffull bandwidth is used. To obtain best noise
performance, the output of the preamp should. be filtered to
the minimum bandwidth required for the desired modulation scheme. The graph of input-referred noise versus
lowpass filtering on the preamp output shows the noise
penalty for higher bandwidths.

AC Coupling Loops
There are three AC loops in the circuit that reject low
frequency inputs. The first loop is around the preamp ~nd . .
provides rejection of am~ient light source~. The operation ~
can be explained by looking at the Block Diagram. For low
frequency signals the transconductance amplifier, GM1,
compares the preamp output to the VBIAS voltage. This
differential voltage is transformed into a current that is fed
into the high impedance node at Pin 3 and transformed
back to avoltage. There is avoltage gain of approximately
60dB to this point which is then buffered to drive a 10k
resistor that is connected back to the input of the preamp.
This high gain loop attenuates the effect of low frequency
signals by the amount of the loop gain times the ratio of RL1
to RFB (I.e., 1000V/vx 10/15=667). Forhigherfrequ~ncies
the attenuation decreases due to the external capacitor on
Pin 3. Atfrequencies beyond where the loop gain equals 15/
10, signals are no longer attenuated. This high frequency
cutoff is at:
f = (15/1 0)/(21t x 4kn x CPIN3)
where 1/(4kQ) is the transconductance of the loop amplifier. For example, if CPIN3 = 300pF, the highpass frequency
is 200kHz which can aid in rejection of a wide range of
ambient interference.
The other two loops operate similarly around the gain
stages and also provide low frequency rejection. In addi-

5-95

LT1319
APPLICATions InFoRmATion
tion, the loops around the gain stages provide an accurate
DC threshold setting for the comparators. At DC, the loops
force the differential voltages at the output of the gain
stages to zero. The comparator threshold is set by the
currents provided by the VTH generator through the 5000
resistors RC1 and RC3. These currents are equal to 4 times
the current into pin 11. For 1OO~ into pin 11, the comparator thresholds are nominally 200mV.

Power Supply Rejection and Biasing
The LT1319 has very high gain and bandwidth so great care
is taken to reduce false output transitions due to power
supply noise. As afirst step the Vcc input is regulated down
to approximately 4V to power all the analog sections of the
circuit which are also tied to Analog Ground (Pin 1) as is the
substrate of the die. Additionally, the internal 4V is bypassed at Pin 16. The digital circuitry (the comparators and
shutdown logic) is powered directly off of Vcc and is
returned to Digital Ground (Pin 12). To provide aclean bias
point for the preamp, filter buffers and the gain stages, a
1.9V reference is generated from the 4V rail and is bypassed at Pin 5. The gain stages are pure differential
designs which inherently reject supply variations.

Filtering
Filtering is needed for two main reasons: sensitivity and
ambient rejection. Lowpass filtering is needed to limit the
bandwidth in order to minimize the noise. Low noise
permits reliable detection of smaller input signals over a
larger distance. Highpass filtering is used to reject interfering ambient signals. Interference includes low frequency
sources of infrared light such as sunlight, incandescent
lights, and ordinary fluorescent lights, as well as high
frequency sources such as TV remote controls (40kHz) and
high frequency fluorescent lighting (40kHz to 80kHz).
The circuittopology allows for filtering between the preamplifier and the filter buffers as well as filtering with the three
internal highpass loops. With two channels the filtering can
be optimized for different modulation schemes. The high
speed channel (with a25ns comparator) is ideal for modulation schemes using frequencies above 1MHz. Carrierbased methods as well as narrow pulse schemes can have

5-96

superior ambient rejection by adding in a dedicated highpass filter network. The application on the first page of the
data sheet is repeated in the Block Diagram and can be used
to illustrate the filtering for IRDA-SIR and Sharp/Newton.
The preamp highpass zero is set by GM1 and CF1. The break
frequency is located at:
f =(15knl1 OkO)/(21t x 4kO x 10nF) =6kHz
On the low speed channel there is alowpass filter at 800kHz
set by RF2 and CF3. The gain stage has a highpass filter set
by GM2 and CF4 at approximately 500kHz. The high speed
channel has an LC tank circuit at 500kHz with Q= 3 set by
RF1. The high speed gain stage has a highpass characteristic set by GM3 and CF5 with a break frequency of 1.1 kHz.
These filters are suitable for the 1.6!JS pulses and up to
115kbaud data rates of IRDA-SIR on the slow channel. The
fast channel is used for Sharp/Newton ASK Modulation
with 500kHz bursts at data rates up to 38.4kbaud.
A second circuit is shown in the Typical Applications
section for IRDA SIR/FIR. The first filter is the preamp
highpass loop set at 4kHz by CF1. SIR is run on the low
speed channel and is next filtered by an 800kHz lowpass
formed by RF2 and CF3 to reduce the noise bandwidth. A
final highpass for the lower speed channel is set by CF4 at
400kHz. The high speed channel is used by FIR which uses
220ns wide pulses. A lowpass formed by RF1 and CF2limit
the noise bandwidth. A 480kHz highpass filter is set by
CF6 and RF3. Note that RF3 is also used to bias the filter
buffer input to VBIAS (Pin 5). Afinal highpass at 110kHz is
set by CF5. The squelch circuit formed by Q1 , Q2 and RC1
to RC4 extends the short range performance and will be
discussed later.
In designing custom filters for different applications, the
following guidelines should be used.
1. Limit the noise bandwidth with a lowpass filter that has
arise time equal to half the pulse width. For example, for
1!JS pulses a 700kHz lowpass filter has a 10% to 90%
rise time of 0.35/700kHz = 500ns.
2. Limit the maximum highpass to 1/(4 x pulse width). For
1!JSpulses, 1/4!JS =250kHz.

LT1319
APPLICATions InFoRmATion
3. In setting the high pass filters, space the filters apart by
a factor of S to 10 to reduce overshoot due to filter
interaction. Overshoot becomes especially important
for high input levels because it can cause false pulses
which may not be tolerated in certain modulation
schemes. It is also more of a problem in modulation
schemes such as IRDA-SIR and FIR where the duty
cycle can get very low (Le., transmitting data with lots of
ones which are signaled with the absence of pulses). AC
coupled receivers when faced with low duty cycle data
set their thresholds close to the baseline DC level of the
data stream which converts small overshoots into erroneously received pulses.
4. As a general rule, place the lowest frequency highpass
around the preamp and the highest highpass around the
gain stage or between the preamp and gain stage. The
reason for this is again due to high signal levels where
there can be slow photocurrent tails. The tail response
can be filtered out by high enough frequency filters.
5. In all cases with custom filtering, orwhen modifying one
of the applications presented in this data sheet, try the
system over the full distance range with a full range of
duty cycle data streams. Modulation methods with fixed
or limited duty cycle are superior because they have little
or no data dependent problems.

receiver/photodiode combination can be obtained. The
minimum light intensity in the angular range is 40mW/sr
which translates to a photodiode current as follows (using
the BPW34FA data sheet specs):

Jsing the IRDA-SIR modulation scheme as an example,
lOwever, we can illustrate how some limits on the required

.L7lJ!J~

]
2

(1000mm)

x (O.6SA/W)(O.9S)(O.9S) = 164nA
The 7mm 2 term is the photodiode area. The 1OOOmm is the
distance from the light source. The O.6SA/W is the spectral
sensitivity at 880nm wavelength. The first 0.9S term is the
relative sensitivity at 8S0nm wavelength and the second
term is the sensitivity at 1So off axis. Similar calculations
are detailed in the Infrared Data Association Serial Infrared
(SIR) Physical Layer Link Specification, version 1.0. This
minimum photocurrent implies that the input-referred
noise cu rrent of the receiver be less than 13. 7n~ rms for a
bit error rate of 1E-9. With an 800kHz lowpass filter on the
preamp output the LT1319 has approximately 3.6nA rms of
input-referred current noise. The maximum photodiode
current at 20mm, on-axis with SOOmW/sr intensity:

Oynamic Range
fhe calculation of dynamic range can only be made in the
~ontext of a specific modulation scheme and with the
:;ystem variations taken into account. The required inforllation includes: minimum signal-to-noise ratio (or BER,
3it Error Rate requirement), photodiode capacitance at
1.9V back bias, preamp noise spectrum, preamp output
:iltering, AC loop cutoff frequencies, modulation method,
jemodulation method including allowable pulse widths
md the effect of missing or extra pulses, photodiode rise
md fall times, and ambient interference. The best solution
sto experimentally determine the maximum and minimum
jistancesatwhich adesired BER is obtained. This measure
)f dynamic range is more meaningful in terms ofthe overall
;ystem than any analytic solution.

7mm2

IpD(MIN) = (40mW/sr)x [

IpD(MAX) = (soomW/sr

)x[

7mm22]
(20mm)

x (O.6SA/W)(O.9S)= S.4mA
so we see that the dynamic range requirement is 90.4dB.
What is not obvious, however, is that the photodiode
output current is not simply a pulse of current, there is a
significanttail at high current levels that has atime constant
of more than 1~ which can cause distortion in the output
pulse width of the LT1319. This tail can be shown in the
following photograph which shows the voltage across aSk
resistor that is connected between the anode of a photodiode and ground. The cathode of the photodiode is
connected to 2V. There is a 2pF Schottky diode across the
resistor to clamp the voltage swing to less than O.SV. With
about 30pF photodiode capaCitance and 1OpF for an oscil-

5-97

~

S.

LT1319
APPLICATions InFoRmATion
loscope probe, any tail observed with a time constant
greater than 210ns is due to decaying photocurrent. The
first trace in the photograph shows the current with the
photodiode 1Ocm from asource with 100mW/sr intensity.
At 200mVldiv, there is about 401lA of peak current and the
decay is consistent with the 210ns time constant. The
lower trace shows the current with the photodiode 2cm
from the LEOs where the photodiode current is theoretically 25 times greater than at 1Ocm. The voltage is clamped
by the photodiode to nearly OAV, but what is now noticeable is that there is a tail with a time constant a bit greater
than 1~. If the signal is AC coupled and has a low duty
cycle, the waveform will be centered at the very bottom
which can result in very wide output pulses. This issue will
be discussed later in more detail and a method to circumvent it will be shown.
Photocurrent Waveforms

2:
c

10cm

~

"
.§'
2cm

1319AI01

Threshold Adjustment
The comparator thresholds are set by the current into Pin
11. The simplest method of setting this current is by a
resistor, RT1 tied between Pin 11 and Pin 15 (Vcc). Pin 11
should be bypassed. The current is given by:
(Vcc -0.9V)
ITH =-,;----+
(RT1 +2kn)
The threshold referred to the input of the filter buffer is:

v _ ITH X 4 x 500n
TH -

5-98

400VIV

or nominally 0.68mV for RTl = 30k. The largest practical
value of RT1 is 39k. The limitation tends to be switching
transients at the comparator outputs parasitically coupling
to the FILTIN or FILTINL inputs and is layout dependent.
Extending Short Range Performance
The short range performance of the LT1319 is normally
limited by the photocurrent tail, but in some instances the
peak current level cannot be supported by the output of the
preamplifier and the input will sag at Pin 2. Typically the
maximum input current is 6mA. To increase this currentto
20mA or more, place an NPN transistor with its emitter tied
to Pin 2, the base to Pin 4 and collector to the 5V supply.
The choice of transistor is dependent on the bandwidth
required for the preamp. The base-emitter capacitance of
the transistor (CJE), is in parallel with the 15k feedback
resistor of the preamplifier and performs a lowpass filtering function. For modest data rates such as IRDA-SIR and
Sharp/Newton a 2N3904 limits the bandwidth to 2MHz
which is ample. Forthe highest data rates, atransistor with
fT greaterthan 1GHz is needed such as MMBR941 LT1.
Another issue with large input Signals is the photocurrent
tail. When this tail is AC coupled and the data has alow duty
cycle, the output pulse width can become so wide that it
extends into the next bit interval. Ahighpass filter can reject
this tail, butforthe case of IRDA-SI R, rejecting the 1~ time
constant can cause rejection ofthe 1.6~ pulse which leads
to aloss of sensitivity and reduced maximum link distance.
The circuit on the front page ofthe data sheet uses a500kHz
highpass that trades off some sensitivity for rejection of
this tail. Unfortunately both maximum and minimum
distance are compromised. An alternative is shown in the
IRDA-SIRIFIRapplication.lnthis instance the final highpass
filter for SIR and FIR is moved into 400kHz, but a ciampi
squelch circuit consisting of 01, 02, and RC1 to RC4 is
added. 01 is used as described above to clamp the input,
but the input current level at which the clamp engages has
been modified by RC1 and RC2.
Without the resistors, 01 would turn on when the voltage
across the 15k resistor in the preamp reaches about 0.7V
(a current of 0.7V115kn = 471lA). The drop across RC1
reduces this voltage by about 480mV. The drop is set by the

LT1319
APPLICATions InFoRmATion
currentthrough RC2 which is [VCC-(VBIAS +0.48V)]/11 kn
= 238~ where VBIAS = 1.9V. Atthis new level (0.22v/15kn
= 14.7~), 01 turns on which clamps the preamp output.

The collector current of 01 provides base drive for 02
which saturates and pulls its collector close to 5V. The
FILT2Land FILT2 inputs are now pulled positive by Rcsand
RC4 which forces an offset at the inputs to the gain stages.
Referring to the Block Diagram, pulling FILT2L or FILT2
positive a voltage t:N provides a voltage of ~V/11 at the
inverting input ofthe first gain stage. This offset effectively
cuts off a portion of the tail at high input levels. The
magnitude of ~V is set by the value of Rcs, the current
sinking capability ofthetransconductance stages (1 OO~),
the value of CF4,CF5 and the duty cycle of the data pulses.

LED Drive Circuits
There are several simple circuits for driving LEDs. For low
speed modulation methods such as IRDA-SIR and Sharpl
Newton with pulses over 1f.lS, a 2N3904 in a SOT-23
package can be used as aswitch with aseries resistor in the
collector to limit the current drive. This circuit is shown
below with a suggested limiting resistor of 16n which
typically sets the current at 200mA. The supply voltage
must be well bypassed atthe connection to the LED in order
forthe supply notto sag when hit with afast current pulse.
A101lf low ESR capacitor should be used as well asa 0.11lf
RF quality capacitor to reduce the high frequency spikes.

The current must be selected to achieve the minimum
output light intensity at a given angle and must be lower
than the manufacturer's maximum current rating at the
maximum duty cycle of the modulation method. The optimum current is a function of the LED output, the LED
forward voltage, the drop across the transistor and the
minimum supply voltage.
_ (Vcc - VLED - Vsw )
ILED - ~-----'RSERIES
The minimum light output then can be obtained from the
LED data sheet. For IRDA-SIR the minimum intensity at 15°
off axis is 40mW/sr. For IRDA-FIR the spec rises to
100mW/sr. To increase light output and distance of the
link, asecond LED can be inserted in series with the first to
obtain twice the light output without consuming additional
supply current. The current variation will now be greater
because two LED forward drops must be accounted for and
the drop across the series resistor is greatly reduced.
For pulse widths less than 500ns the NPN should be
replaced by an N-channel MOSFET with on-resistance of
less than 1n with 5Von the gate. The FET can turn off much
more quickly than the saturated NPN and provides alower
effective on-resistance. Asuggested circuit is shown below
and includes two devices available in the SOT-23 package.

TYPICAL APPLICATiOnS

h

Vee

2N3904 FOR <1 MHz
MMBR941 LTl FOR> 1MHz

PIN 2
IN

2 LED Drive Circuit

LED Drive Circuit
for IRDA-SIR and Sharp/Newton

Optional Clamp Circuit

for IRDA-FIR
Vee

Vee

I ",;.

HSDL4220
TSH5400.P
DN304

HSDL4220

RD2
3.gn

PIN 4
PREOUT

~ t;!t

TSH540j"""
DN304
P

1319TA03

RD1

lOOn

VIN

Ql

--'IM.-j ~ NDS351 N
• .lTN020n

5-99

LT1319
TYPICAL APPLICATions
IRDA-SIR/FIR Data Receiver
~:------------------------I

• BPW34FA OR BPV22NF
•• THESE COMPONENTS ARE ONLY REQUIRED
FOR VERY LARGE INPUT CURRENTS THAT OCCUR
WHEN THE PHOTODIODE IS LESS THAN 3cm AWAY.
SEE TEXT.

OGNO

PC Board Layout for IRDA-SIR and Sharp/Newton Data Receiver with LED Drive Circuit

Ql

RFa

Dl

~D

D
vee

GNO

s/o

~0C83
D2

DRF4 eFI 0
CB4
CF3

0
0

RF2

0

LFt

D

RTl CDl C02

D D

UI

en
DDDD

~ ~

h~

COMPONENT

5-100

lj

0

IRD~

SHARP

TOP

BOTTOM

INDEX
)ECTION 5-INTERFACE
MIXED PROTOCOL
LTC1334, Single 5V RS232/RS485 Multi-Protocol Transceiver ............................................................. 13-53

L7lJD~

5-101

NOTES

5-102

iECTlon 6-DATA conVERSion

6-1

INDE)(
SECTION 6-DATA CONVERSION
INDEX ..............., ........................................................................................................................ 6-2
SELECTION GUIDES ........................................................................................................................ 6-3
PROPRIETARY PRODUCTS
ANALOG-TO-DiGITAL CONVERTERS ................................................................................................... 6-7
LTC1274/LTC1277, 12-8it, 10mW, 100ksps ADCs with 1pA Shutdown ..................................................... 13-22
LTC1279, 12-8it, 600ksps Sampling AID Converter with Shutdown .. ......................................................... 6-8
LTC1285/L TC1288, 3V Micropower Sampling 12-8it AID Converters in SO-8 Packages .................................. 6-24
LTC1392, Micropower Temperature, Power Supply and Differential Voltage Monitor ................................... 13-77
LTC1400, Complete SO-8, 12-8it, 400ksps AID Converter with Shutdown ................................................. 13-86
LTC1410, 12-8it, 1.25Msps Sampling AID Converter with Shutdown ...................................................... 13-97
LTC1522, 4-Channel, 3V Micropower Sampling 12-8it Serial I/O AID Converter ....................................... 13-134
ANALOG-TO-DIGITAL CONVERTERS, ENHANCED AND SECOND SOURCE
LT574A, Complete 12-8it AID Converter .......................................................................................... 6-48
DIGITAL-TO-ANALOG CONVERTERS .................................................................................................. 6-57
LTC1451/L TC1452/L TC1453, 12-8it Rail-to-Rail Micropower DACs in SO-8 ............................................... 6-58
DIGITAL-TO-ANALOG CONVERTERS, ENHANCED AND SECOND SOURCE
LTC7541A, Improved Industry Standard CMOS 12-8it Multiplying DAC ..................................................... 6-69
LTC7543/LTC8143, Improved Industry Standard Serial 12-8it Multiplying DACs .......................................... 6-73
LTC8043, Serial 12-8it Multiplying DAC in SO-8 ............................................................................... 6-80
MULTiPLEXERS .......................................................................................................................... 6-85
LTC1390, 8-Channel Analog Multiplexer with Serial Interface ............................................................... 6-86

6-2

DATA CONVERSION PRODUCTS
Analog-to-Digital Converters
Mlcropower
3V Supply In SO-8
Single Input, Micropower
LTC"'1286 (12,5ksps)

Single Input
LTC1285 (7,5ksps)

2-Channel MUX, Micropower
LTC1298 (11,lksps)

2-Channel MUX
lTC1288 (6,6ksps)

Serial Output
withMUX

I - - - - - - j Complete High Speed
Parallel Output

Single Input
LTC1287 (2.7V Operation, 30ksps)
LTC1292 (60ksps)
LTC1297 (50ksps, Auto Shutdown)
2-Channel MUX
LTC1291 (54ksps)
4-Channel MUX
LTC1522 (3V Powered, Micropower)
6-Channel MUX
LTC1293 (46ksps)
8-Channel MUX
LTC1290 (50ksps)
LTC1294 (46ksps)
LTC1289 (2.7V Operation, 25ksps)
LTC1296 (46ksps)

LTC1272 (250ksps, 7572 Upgrade)
LTC1273 (300ksps, OV to 5V Input)
LTC1274 (100ksps, Low Power wi Shutdown)
LTC1275 (300ksps, ±2,5V Input)
LTC1276 (300ksps, ±5V Input)
LTCI277 (100ksps, Low Power wi Shutdown)
LTC1278-4 (400ksps, OV to 5V or ±2,5V Input)
LTC1278-5 (500ksps, OV to 5V or±2,5V Input)
LTC1279 (600ksps, OV to 5V or ±2,5V Input)
LTC1282 (2,7V Operation, 140ksps)
LTC1410 (1 ,25Msps, ±2,5V Input)

Non-Sampling
LT574A (Industry Standard, 251J.S)

LTC1400 (400ksps)

Serial Output In SO-8,
3V to 9V Powered
Single Input, Micropower
LTC1096 (33ksps)
2-Channel MUX, Micropower
LTC1098 (33ksps)
Single Input, Fast
lTC1196 (IMsps)
2-Channel MUX, Fast
LTC1198 (750ksps)

Parallel Output
LTC1099 (300ksps)

Single Input
LTC1092 (38ksps)
2-Channel MUX
LTC1091 (31ksps)
6-Channel MUX
LTC1093 (26ksps)
LTC1095 (26ksps, Reference)
8-Channel MUX
LTC1090 (30ksps)
LTC1094 (26ksps)
LTC1283 (3V Operation, 15ksps)
Built-In Temperature Sensor and
Vee Monitor, lTC1392

)igital-to-Analog Converters
12-81t Serial In S0-8
LTC1257 (Single Supply, VOUT, Reference)
LTC1451 (5V Powered, OV to 4,095V
Rail-to-Rail Output, Reference)
LTC1452 (3V to 5V Single Supply,
Multiplying, Rail-to-Rail Output)
LTC1453 (3Vto 5V Single Supply,
OVto 2,5V Rail-to-Rail Output, Reference)

12-81t Industry Standard
Current Output Mulliplying
LTC7541 (Parallel Digital Input)
lTC7543 (Serial or Parallel Input)
LTC8043 (Serial Input, SO-8)
LTC8143 (Serial Input and Output)

6-3

DATA CONVERSION PRODUCTS

i\7.;\7~Y.

/.
lTC1272-3 250

3

15

ff

LTC1272·8 110

v'

~

J,N,SW 24

a

15

ff

ff

ff

NlA

15

ff

ff

ff

5

LTC1274

100

a

2.0

ff

ff

ff

LT

LTC1275

300 2.7

15

ff

ff

D

±2.5

LTC1276

3002.7

15

ff

ff

ff

±5

LTC1271

100

a

2

ff

ff ff

ff

ff

SW

24

lTC1278-4 400

2

15

ff

ff

ff

D

\2.5 f f

N,SW

24

lTC1278-5 5001.6

15

ff

ff

ff

.cr

5±2.5 f f

N,SW

24

LTC1279

6001.4

12

ff

ff

ff

LT \2.5 f f

N,SW

24

LTC1282

140

4.0

ff

ff

.1.7

~15.25

J,N,SW

24

LTC1285

7.' 1250.160' f f f f

LTC1286

12.5 80

5

LTC1217

30

L1C1288

6.6 141

24

O.250~

ff

ff
ff

1.'
O.210~

ff

ff ff

4

4

J,N,SW

24

J,N,SW 24
ff

SW

24

J,N,SW

24

J,N,SW 24
ff

ff

ff

1

ff

N,SO

ff

ff

1

ff

N,SO

1.2

J,N

ff

2.7 f f

N,SO

a
a
a
a

ff

ff

2

ff

ff

LTC1289

25

26

1.5

ff

ff

1.2 f f

J,N,SW

20

50

13

6

ff

a
a

ff ff

LTC1290

ff ff

D"

ff

1.2 f f

J,N,SW

20

LTC1291

54

12

6

ff

2

ff

ff

ff

NlA D"

J,N

LTC1292

80

12

6

D"

D"

ff

1.2

J,N

a
a

LTC1293

46

12

6

ff

6

D" D" D"

D"

1.2 D"

J,N,SW

16

LTC1294

46

12

ff

ff ff ff

D"

1.2 D"

J,N

20

LTC129&

4.

12

a
a

D" D" D"

ff

1.2 f f f f

J,N

20

LTt:1297

50

12

1.2 f f

J,N

2.7 f f

N,SO

ff

4.1

D"

N8,sa

a
a
a

D"

<2.,

ff

ff

•
•
•

D"
D"

11.1 90 0.340" D"

ff
ff

LTC140D

4002.1

LTt;1410

1250 0.75 12_ 20

LTC1522

10.5 60

LT574A

-

15

0.16

2

D"

ff

ff

ff

D" f f f f

4

25 40-25

t

r;;;;:.:Ln:::.l::'l1:..:9~-t'"_ _-:;:t--+5V / ' ~:~e~omw
+

O.1JtF

Consumption

-J ~ No Negalive
"" "'""'''
LINES

Internal Clock

ff

ff
ff

ff

N,SO

28

1.5

SO

1.

10

N

28

sample rate. Supply current listed IS at fSAMPLE{MAX)

&OOksps
Sample Rate

fO¢

D"

ff

With

ff

f f D"

D" D"

High Speed 12-Bit AID Converters

Relerence
Dulpul For
System Use

NfA

3002.7

*Average supply current drops

t

ff

LTC1213

LTC1298

ou~;-t----rt--I

~

ff

Supply Required
lor Unipolar Dperallon

Comparison of Specs and Features
DEVICE
TYPE
LTC1272
LTC1273
LTC1274

SAMPLING
FREQ
2S0ksps
300ksps
100ksps

LTC1275
LTC1276
LTC1277

300ksps
300ksps
100ksps

LTC1278-4

400ksps

LTC1278-5

500ksps

LTC1279

600ksps

LTC1282

140ksps

LTC1400

400ksps

LTC1410

1.2SMsps

• LTC1400: 400ksps in 80-8 Package!!

INPUT
S/(N+ D)
AT NYQUIST RANGE
6SdB
OV-SV
OV-SV
70dB
73dB
OV-4.096V
or±2.048
70dB
±2.SV
70dB
±SV
73dB
OV-4.096V
or±2.048
70dB
OV-SV
or±2.SV
OV-SV
70dB
or±2.SV
OV-SV
70dB
or±2.SV
OV-2.SV
68dB
or±1.2SV
70dB
OV-4.096V
or±2.048V
71dB
±2.5

'Low power shutdown with lOstant wake up

6-4

POWER
POWER
SUPPLY DISSIPATION
SV
75mW
SV
7SmW
5V
10mW
or±SV SI1W (Shutdown)
±5V
75mW
±5V
75mW
SV
10mW
O.8mW'
or±SV
SV
7SmW
or±SV
SmW'
SV
7SmW
or±SV
5mW'
SV
60mW
or±5V
7.SmW'
3V
12mW
or±3V
SV
75mW
or±SV
±5V
160mW

DATA CONVERSION PRODUCTS
Serial VO 12-8it AID Converters
12-8it Serial Interface AID Converter Systems
12~

Tir

Built.ln Sample II Hold
Conversion
for Single.Ended Conversions
Can Be Configured for {
S,""£-ENDED INPUT
,~
Up to 8 Single-Ended
±15VOVERV:i~5EV~~G~Y:
~~~
Vee
or 4 Oifferenfiallnpuls
• GH2
. or Both Bipolar.or
DIFFERENTIAL INPUT (+)
~~: LTC1290 D~~~
Smgle-Ended Operallon ±5V COMMON MODE RANGE H
cs

t

/

Low Power CMOS
~ Single 5V (or 3V)
Only SmA Supply Currenf, 5pA in
Supply Operation
Power Shutdown (LTC1290)
Seriall/O to Processor
+
5V
- Saves Wires
}
~:'\ALUM ""1T
- Simplifies Isolated Interface
T~NDfROM -=1N4148
-Interfaces Directly to Most
MICROPROCESSOR
Processors

=

:~~:

~LT102.1-5

Input Voltage Range
Extends to Power
Supply Rails

-5V

-=f"

~

8VTQ4QV

-=f" 1,F

"581T

Can be Operated Down to
1.2V (Reference) Full Span

Comparison of Specs and Features
Device Type
LTC1287
LTC1289
LTC1290
LTC1291
LTC1292
LTC1293
LTC1294
LTC1296
LTC1297
LTC1522

Analog Input
Channels
1
8
8
2
1
6
8
8
1
4

Supply
Voltage (V)
3
3/±3

5/±5
5
5

5/±5
5/±5
5/±5
5
3

Sample Rate
(ksps)
30
25
50
54
60
46
46
46
50
10.5

Number
01 Pins
8
20
20
8
8
16
20
20
8
16

Full/Hall
Duplex 110
Half

Auto
Shutdown

Shutdown
Stalus Pin

Full
Full
Half
Half
Half
Half
Half
Half
Half

X
X
X

•

lAicropower 12-8it AID Converters in 50-8 Packages
12~W, SO-8 Package, 12-Bit ADC
Samples at 200Hz and Runs Off a 3V Battery

!Vorld's Lowest Power 12-8it ADCs
12-Bit Resolution
8-Pin SO Plastic Package
Low Cost
Low Supply Current: 160~ Typ (LTC1285)
Guaranteed ±3/4LSB Max DNL
Auto-Shutdown to 1nA Typ
Single Supply 3V to 6V Operation
(LTC1285/88) or 5V to 9V (LTC1286/98)
On-Chip Sample-and-Hold
1OO~ Conversion Time
Sampling Rates: 12.5ksps (LTC1286)
11.1 ksps (LTC1298)
1/0 Compatible with SPI, Microwire, etc.
Differential Inputs (LTC1285, LTC1286)
2-Channel MUX (LTC1288, LTC1298)

MPU
(e.g .. 8051)

.-----IP1.4
1'--+----1 Pt3
I"--+S"""ER-IAL-O-AT-AL-1N-I
K P1.2

Supply Current vs Sample Rate
(LTC1285)

1000~1IB
TA 25'C

TOP VIEW

Vee _2.7V

VREF-2.5V
fCLK = 120kHz

100

~!II'lt~ltsoI'W

Power
Consu"!pllon
at1ksps

1 0 " .

S8 Package:
8-Lead Plastic SO

10L.1-UUllill1~~llW1~0~~~100
SAMPLE FREQUENCY (kHz)

L7lJD~

6-5

DATA CONVERSION PRODUCTS
8-Bit AID Converters in 8-Pin SO Packages
Lowest Power: LTC1096ILTC1098

Highest Speed: LTC11961LTC1198

•
•
•
•

•
•
•
•
•
•

801lA Maximum Supply Current
1nA Supply Current in Shutdown
Operate from 2.7V to 9V Single Supply
33ksps Sample Rate

Comparison of Specs and Features
Device Supply Voltage Max Sampling
Type
Range (Vee)
Rate (ksps)
LTC1096
2.7 10 9
33
LTC109a
2.7106
33
LTCl196
2.7 10 6
1000
LTCl19a
2.7 to 6
750

8-Bit Resolution
1Msps Sample Rate
100ns Sample/Hold Acquisition Time
Single Supply 2.7V to 6V Operation
Low Power: 1OmW at 3V, 50mW at 5V
Auto-Shutdown to 1nA (LTC1198)
TOP VIEW

PD@1ksps
(mW)
0.017
0.017
40
0.05

PD (mW)@Vee
MSR @fS(MAX)
0.6@5V
0.6@5V
55@5V
55@5V

Input
Range
OV 10 VREF
OVtoVee
OVtOVREF
OVlo Vee

Dour

N8 Package: 8-Lead PDIP
S8 Package: 8-Lead Plastic SO

10-Bit AID Converter "Systems on a Chip"
~+~

"""~~ ~~~~,~~~~~~
~

~~ ~

~~~~:~~-~/~~~~~
..

I!)



t1l

u..~ -40

;:!:

O::t:

g@
!::: H: -60
~~

,

VSS(VRIPPLE = 10mV)
DGND(VRIPPLE = 100mV)

::;:0-



1M

2.390

-8 -7 -6 -5 -4 -3 -2 -1
LOAD CURRENT (rnA)

1279G10

6-13

LTC 1279
Pin FunCTions
AIN (Pin 1): Analog Input. OV to SV (Unipolar), ±2.SV
(Bipolar).

conversion. The LTC1279 responds to CONVST signal
only if the signal applied to CS is a logic low.

VREF (Pin 2): 2.42V Reference Output. Bypass to AGND
(1 O~ tantalum in parallel with 0.1 ~ ceramic).

RO (Pin 20): READ Input. A logiC low signal applied to
this pin enables the output data drivers when the signal
applied to the CS pin is a logic low.

AGNO (Pin 3): Analog Ground.
011 to 04 (Pins 11 to 4): Three-State Data Outputs.
D11 is the Most Significant Bit.

OGNO (Pin 12): Digital Ground.
03 to DO (Pins 13 to 16): Three-State Data Outputs.

OVDD (Pin17): Digital PowerSupply,SV. TietoAVDD pin.

es (Pin 21): The CHIP SELECT input must be alogic low
for the ADC t~recognize the signals applied to the
CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is a logic low during a conversion.

SHON (Pin 18): Power Shutdown. The LTC1279 powers down when SHDN is low.

Vss (Pin 23): Negative Supply. -SV will select bipolar
operation. Bypass to AGND with 0.1~ ceramic. Tie to
analog ground to select unipolar operation.

eONVST (Pin 19): Conversion Start Input. It is active
low. The falling edge of the CONVST signal initiates a

AVDD (Pin 24): Positive Supply, SV. Bypass to AGND
(1 Ow tantalum in parallel with 0.1W ceramic).

FunCTionAL BLOCK DIAGRAm
CSAMPLE
AIN

-----~----111---....,

-AVoo
ZEROING
SWITCH

~

-DVoo
-VSS
(OV FOR UNIPOLAR MODE
OR -5V FOR BIPOLAR MODE)

VREF----...J

AGND-

D11

OUTPUT LATCHES
DGND-

DO
12796D

CONTROL LOGIC

6-14

.L7~!l~

LTC 1279
TEST CIRCUITS
Load Circuits for Access Timing

.,,+

Load Circuits for Output Float Delay

DBN

-I-3k-i~CL
":"

DGND

":"

CL

DBN

--1I"""3-k--i~-10-PF

10PF

":"

JDGND

A) HIGH-Z TO VOH (ta)
AND VOL TO VOH (to)

.,,+r
5V

5V

DGND

":"

":" DGND

A) VOH TO HIGH-Z

B) HIGH-Z TO VOL (ta)
AND VOH TO VOL (to)

B) VOL TO HIGH-Z
12n1TC02

1279TCOl

TiminG DIAGRAmS
CS to CONVST Setup Timing

CS to RD Setup Timing

:4q=~
1279 TOOl

SHDN to CONVST Wake-Up Timing

~J~
~r~
~1279TD02

CONVST

----------------------------11
APPLICATiOnS InFORmATion
CONVERSION DETAILS
The LTC1279 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with aprecision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)

SAMPLE

S
~-+------IA

R

Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.

Figure 1. AIN Input

During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capaCitor during the acquire phase, and the comparator
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 160ns will provide enough

time for the sample-and-hold capaCitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge onto the summing junction. This input charge is successively com-

6-15

LTC 1279
APPLICATions InFoRmATion
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the AIN input charge. The SAR contents (a 12-bit
data word) which represent the AIN are loaded into the
12-bit output latches.

DYNAMIC PERFORMANCE
The LTC1279 has excellent high speed sampling capability. FFT (Fast FourierTransform) testtechniques are used
to test the ADC's frequency response, distortion and
noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an
FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figures 2a
and 2b show typical LTC1279 FFT plots.

Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + 0)] is the
ratio between the RMS amplitude ofthe fundamental input
frequency to the RMS amplitude of all other frequency
components at the AID output. The output is band limited
to frequencies above DC and below half the sampling
frequency. Figure 2a shows atypical spectral content with
a600kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 300kHz as shown in Figure 2b.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is ameasurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) -1.76]/6.02

t-----t---

-10
!SAM~I,f:~n~~~~1
-20 / - - - - + - -301----+-------1
~-40 1 - - - - + - - - - - - - 1
'0

;:;:; - 5 0 1 - - - - / - - - - - - - - 1

c
E
-60 1 - - - - + - - - ' - - - - - - - 1

where Nis the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 600kHz the LTC1279 maintains very good ENOBs up
to the Nyquist input frequency of 300kHz. Refer to Figure 3.

0: -70 1 - - - - + - - - - - - - 1
~ -80 1 - - - - + - - - - - - - 1
-90 I----/---+;---,,-H
-100
-110
-120

'"~
o

50

100
150 200
FREQUENCY (kHz)

250

300
1279""

fSAMPLE = ~UUKt1Z-----H

fiN = 292.822kHz - - - - - H

-30/---------H
~-40 / - - - - - - - - - H
~ -50 I - - - - - - - - - - H
c
E
-60 I - - - - - - - - - - H

~ f-h=============~!

-70
'" -80
-90 H - - - - - - - ; - t - H
-100
-110
50

100
150 200
FREQUENCY (kHz)

250

300
t279F02

Figure 2b. LTC1279 Nonaveraged, 4096 Point FFT Plot
with 300kHz Input Frequency

6-16

9

III

74
68

-:.f..I.

II~YQJ;'st

I
FREQUENCY

I'-,.

......

en

62 ~
56

E:

7

50 ~
gj

~ 6
~ 5

~

15 8

Figure 2a. LTC1279 Nonaveraged, 4096 Point FFT Plot
with 100kHz Input Frequency
-10
-20

12
11
10

~

+

c

>

~

§ 4

~

o

.3

3

Q:
,!!;!

1

o

10k

fSAMPLE =1 ~~~~IHZ

lOOk
1M
FREQUENCY (Hz)

5M

Figure 3. Effective Bits and Signal/(Noise + Distortion) vs
Input Frequency

Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics ofthe input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and halfthe sampling frequency)HD is
expressed as:

LTC 1279
APPLICATions InFoRmATion
Figure 5 shows the IMD performance at a 100kHz input.

THO = 2010g -VV22 + V3 2 + V42 ... + VN2

V1

where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics. THO versus input frequency is shown in Figure 4. The LTC1279 has good
distortion performance up to the Nyquist frequency and
beyond.
~

0

~ -10

f-

~ -30
~

:~: ~i:~~;~~~

~ -40

/----11---------1
/----11---------1

~ -50

f-------1I------=-,------j

@-60 f-------1I--------..----';;;;!-H
12:;; -70 1--12fa-fbHf-,(2ft
"" -80
-90 ~---lIlI--=;"!I,-';::'::!.,""",-JIj.

o

50

100
150
200
FREQUENCY (kHz)

250

300

-40

Figure 5. Intermodulation Distortion Plot

~ -50
~

-20
-30

-100
-110
-120

fSA~PL~ ~ ~oh~~~

~ -20

I-

-10 ~-""'4I-I~-fSAMPLE=600kHz

-60

J..-.

'"~-70
§ -80

I-

~ -90

""_100

./

2ND HARMONIC
THO

J.&oII"TTi\ ;x V3RD HARMONIC

~nllill
10k

II IIII

lOOk
INPUT FREQUENCY (Hz)

1M

2M

Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full scale input signal.

Figure 4. Distortion vs Input Frequency

Full Power and Full Linear Bandwidth
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THO. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Iftwo pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where mand n = 0, 1, 2, 3, etc.
Forexample, the 2nd order IMDterms include (fa +fb) and
(fa -fb) while the 3rd order IMD terms include (2fa + fb),
(2fa - fb), (fa + 2fb), and (fa - 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of
the 2nd order IMD products can be expressed by the
following formula:
IMD (fa ± fb) = 2010g Amplitu~e at (fa ± fb)
Amplitude at fa

The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1279 has been designed to optimize input bandwidth,
allowing ADC to undersample input signals with frequencies above the converter's Nyquist Frequency. The noise
floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond
Nyquist.
Driving the Analog Input
The LTC1279's analog input is easy to drive. It draws only
one small current spike while charging the sample-andhold capaCitor althe end of conversion. During conversion
the analog input draws no current. The only requirement
is that the amplifier driving the analog input must settle
after the small current spike before the next conversion
starts. Any op amp that settles in 160ns to small current
transients will allow maximum speed operation. If slower

6-17

Ell

LTC 1279
APPLICATions InFoRmATion
op amps are used, more settling time can be provided by
increasing the time between conversions. Suitable devices capable of driving the ADC's AIN input include the
LT@1360, LT1220, LT1223 and LT1224 op amps.

Internal Reference
The LTC1279 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.42V.lt is internally connected to the DAC and
is available at pin 2 to provide up to 800~ current to an
external load.
For minimum code transition noise, the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (1 Ow tantalum in parallel with a
0.1W ceramic).
The VREF pin can be driven with a DAC or other means to
provide input span adjustment in bipolar mode. The VREF
pin must be driven to at least 2.4SV to prevent conflict with
the internal reference. The reference should be driven to
no more than 4.8V to keep the input span within the ±SV
supplies.
Figure 6 shows an LT1 006 op amp driving the VREF pin. (In
the unipolar mode, the input span is already OV to SV with

the internal reference so driving the reference is not
recommended, since the input span will exceed the supply
and codes will be lost at the full scale.) Figure 7 shows a
typical reference, the LT1 019A-2.S connected to the
LTC1279. This will provide an improved drift (equal to the
LT1 019A-2.S's maximum of Sppm/°C) and a±2.S82V full
scale.
UNIPOLAR/BIPOlAR OPERATION AND ADJUSTMENT
Figure 8a shows the ideal input/output characteristics for
the LTC1279. The code transitions occur midway between
successive integer LSB values (Le., O.SLSB, 1.SLSB,
2.SLSB, ... FS - 1.SLSB). The output code is naturally
binary with 1LSB = FS/4096 = SV/4096 = 1.22mV. Figure
8b shows the input/output transfer characteristics for the
bipolar mode in two's complement format.
1LSB = 4~~6

111.,,111

=4g~6

111...110
111...101
~

111...100

8
5

i3o
000".011

INPUT RANGE
±1.033x V R E F ( O U T ) - - - - - - - - - - .

000".010
000".001
000".000

UNIPOLAR
ZERO

r

J

lJ

J

J

J

J

J

I I

I
OV 1
LSB

FS-1LSB
INPUT VOLTAGE (V)

Figure 8a. LTC1279 Unipolar Transfer Characteristics

I

011...111

Figure 6. Driving the VREF with the LT1006 Op Amp

BI~OLAR

011...110
INPUT RANGE

±2.58V----------,
(= ±1.033 x VREF)

VIN
VOUT 1 - - - - 9 ' - - LT1019A-2.5

~

o

1J L1

000".001

~ 000".000

f?:

111...111

5

111".110
100".001
100".000

I

ZERO

j

I

li

J

J

1

-

FS=5V

1LSB = FS/4096 -

1 1 .1
-FS/2

Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1279 with the LT1019A-2.5

6-18

-1 OV 1
LSB
LSB
INPUT VOLTAGE (V)

1

FS/2-1LSB
12.7{lF08b

Figure 8b. LTC1279 Bipolar Transfer Characteristics

LTC 1279
APPLICATions InFoRmATion
Unipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 9a
shows the extra components required for full-scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 9b can be used. Forzero offset
error apply 0.61 mV (Le., 0.5LSB) at the input and adjust
the offset trim until the LTC1279 output code flickers
between 0000 0000 0000 and 0000 0000 0001. For zero
full-scale error apply an analog input of 4.99817V (Le.,
FS -1.5LSB or last code transition) at the input and adjust
R5 until the LTC1279 output code flickers between 1111
1111 1110 and 1111 1111 1111.

R5
1----<:JtL-SCALE
ADJUST
5V

R6

ADJUST

-5V

Figure 9c. LTC1279 Bipolar Offset and Full-Scale Adjust Circuit

Bipolar Offset and Full-Scale Error Adjustments

R1
V1 -J.,f.>lv-t---I

FULL·SCALE
ADJUST
ADDITIONAL PINS OMITIED FOR CLARITY "::"
±20LSB TRIM RANGE

Figure 9a. Full-Scale Adjust Circuit

ANALOG
INPUT --'I/'o~---;
lVTO 5V

5V

:igure 9b. LTC1279 Unipolar Offset and Full-Scale Adjust Circuit

Bipolar offset and full-scale errors are adjusted in asimilar
fashion to the unipolar case. Again, bipolar offset must be
adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset of the op amp
driving the analog input of the LTC1279 while the input
voltage is 0.5LSB below ground. This is done by applying
an input voltage of -0.61 mV (-0.5LSB) to the input in
Figure 9c and adjusting the R8 until the ADC output code . .
flickers between 0000 0000 0000 and 1111 1111 1111. ~
For full scale adjustment, an input voltage of 2.49817V
(FS -1.5LSBs) is applied to the input and R5 is adjusted
until the output code flickers between 0111 1111 1110
and 0111 1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolution or high speed AID converters. To obtain the best
performance from the LTC1279, a printed circuit board is
required. The printed circuit board's layout should ensure
that digital and analog signal lines are separated as much
as possible. In particular, care should be taken not to run
any digital trace alongside an analog signal trace or
underneath the ADC. The analog input should be screened
by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the AVDD and VREF pins as shown in
Figure 10. For the bipolar mode, a0.11lf ceramic provides

6-19

LTC 1279
APPLICATions InFoRmATion

Figure 10. Power Supply Grounding Practice

adequate bypassing for the Vss pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Input signal traces to AIN (pin 1) and signal return traces
from AGND (pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, ashielded cable between the signal source
and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC
appears as an error voltage in series with the input signal,
attention should be paid to reducing the ground circuit
impedances as much as possible.
A single pOint analog ground, separate from the logic
system ground, should be established with an analog
ground plane at pin 3 (AGND) or as close as possible to the
ADC. Pin 12 (DGND) and aU other analog grounds should
be connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to isolate the ADC data bus.

6-20

DIGITAL INTERFACE
The AID converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to aU peripheral memory interfacing. A separate CONVST is used to initiate a conversion.

Internal Clock
The AID converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.41JS. No external adjustments are required, and
with the typical acquisition time of 160ns, throughput
performance of 600ksps is assured.

Power Shutdown
The LTC1279 provides a power shutdown feature that
saves power when theADC is in inactive periods. To power
down the ADC, pin 18 (SHDN) needs to be driven low.
When in powershutdown mode, the LTC1279will not start
a conversion even though the CONVST goes low. All the
power is off except the Internal Reference which is still
active and provides 2.42V output voltage to the other
circuitry. In this mode the ADC draws 8.5mW instead of
60mW (for minimum power, the logic inputs must be
within 600mVofthe supply rails). The wake-up time from
the power shutdown to active state is 350ns.

LTC 1279
APPLICATions InFoRmATion
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CS, CONVST and RD. Figure 11
shows the logic structure associated with these inputs. A
logic "0" for CONVSTwili start aconversion after the ADC
has been selected (Le., CS is low). Once initiated, it cannot
be restarted until the conversion is complete. Converter
status is indicated by the BUSY output, and this is low
while conversion is in progress.
Figures 12 through 16 show several different modes of
operation. In modes 1aand 1b (Figures 12 and 13) CS and
RD are both tied low. The falling CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1ashows
operation with anarrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 14) CS is tied low. The falling CONVST
signal again starts the conversion. Data outputs are in
three-state until read by MPU with the RD signal. Mode 2
can be used for operation with a shared MPU databus.

In Slow memory and ROM modes (Figures 15 and 16) CS
is tied low and CONVSTand RD are tied together. The MPU
starts conversion and reads the output with the RD signal.
Conversions are started by the MPU or DSP (no external
sample clock).
In Slow memory mode the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into aWAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In ROM mode, the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the previ-

ous conversion result. After the conversion is complete,
the processor can read the new result (which will initiate
another conversion).

•

ACTIVE HIGH

; > 0 - - - + ENABLE THREE·STATE OUTPUTS
OB11 .... 0BO

CONVERSION
START (RISING
EDGE TRIGGER)
CONVST-r---------+----~

CLEAR

Figure 11. Internal logiC for Control Inputs CS, RD, CONVST and SHDN

DATA

DATA (N -1)
OB11 TO OBO

OATAN
OB11TO OBO

DATA (N + 1)
OB11 TO OBO

Figure 12. Mode 1a. CONVST Starts a Conversion. Data Ouputs Always Enabled. (CONVST = ~)

6-21

LTC 1279
APPLICATions InFoRmATion

DATA

DATA (N-1)
DB11T0 DBO

DATA (N + 1)
DB11T0 DBD

DATAN
DB11 TO DBD

Figure 13. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled.(CONVST = ~ )
1------111----~

DATA (N + 1)
DB11T0 DBD

DATA -------------~

1279F14

Figure 14. Mode 2. CONVST Starts a Conversion. Data is Read by RD
1 - - - - - - tcONV - - _

DATAN
DB11 TO DBD

DATA------

V

'"~
ANALOG INPUT
OV TO 3V RANGE

..:..-+----1 Pl.3
SERIAL DATA LINK

[5: 10
:::>


0.1

10

1

SAMPLE RATE (kHz)
LTC1285J88·TPC01

5

4

/

3

V

2

=0
./ cs
(AFT~R CONVERSION)-

1,/
1

_I
cs - Vcc

0.002

o

-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (Oc)
LTC1285/88·TPC0.2

o

/

/

fJ..

g;

en

50 vcc =2.7V
VREF = 2.5V
fCLK =120kHz

V

~

g;j
::;

fJ..
fJ..

::::>

en

7

~
<>

::; 100

lTC1285

7

TA =25°C

Vcc =2.7V
VREF =2.5V

a;

::::>

V

1

Shutdown Supply Current vs Clock
Rate with CS High and CS Low

Supply Current vs Temperature

1

~

~

00

00

100

1~

FREQUENCY (kHz)
LTC1285188·TPC03

6-27

LTC 1285/LTC 1288
TYPICAL PERFORmAnCE CHARACTERISTICS
Reference Current vs
Sample Rate (LTC1285)
50

1
I-

i:li
a:

a:
::>
<>
w
<>

i:li
a:

Ita:

40
30

20

/

15
10

51

1 50

/

i:li
a:

49

::>
to

48

a:
w

to

i:li

II:

Ita:

V

oV
o

1Ii
a:

=;;

./

I-

V

/

3.0

Vee = 2.7V
VREF = 2.5V
lelK = 120kHz
ISMPl = 7.5kHz

52

/

35
25

53

1/

TA = 25°C
Vee = 2.7V
VREF= 2.5V
!elK = 120kHz

45

3

5

~ 2.0

\

"

'"

,,:. 1.5

\

tu

47

[g

46

0

;;;;

45

'":t:z

44

2

Change in Offset
vs Reference Voltage

Reference Current vs Temperature

SAMPLE RATE (kHz)

5 25 45 65 85 105 125
TEMPERATURE (OC)

0.5

0.5

1.0

LTCl285188·T!'t04

-10

0.50
TA= 25°C
Vee = 2.7V
lelK = 120kHz
ISMPl = 7.5kHz

0.45

ill 0.40

'" .

-8
ill -7

,,:. 035

-

o
;;;;

I'....

~-0.05

~
5-0.10

a:

0.30

'5

0.25

::is

~

I'-..

5 0.10
0.05

-0.20

o

10

20
30 40
50
TEMPERATURE (OC)

60

70

........

......

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE M

I'-..

~

o

12
11

a:

o

z
!::!.

0.5

74
68 ~
z

-

~ 10
0

62

~
z

15

z
o
z

::>

~-0.5 1-+---11-+-1-+-+-+--1

~

ffi

::;

co
::;;

~

L-~_L

o

__L-~_L~__~~

512 10241536 2048 2560 3072 3584 4098
CODE
LTCl285188'Tl'tl1

z

~
o

TA = 25°C
Vee = 2.7V
!elK = 120kHz

1

10
INPUT FREQUENCY (kHz)

.9

56 c.
50 &

~
co

~

-

lTCl285/8a·lPcoe

Effective Bits and S/(N + D)
vs Input Frequency

ill

-1

r-

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE (V)

LTCl285188·1l'COe

~

6-28

r\.

-1

i""- t'-....

Differential Nonlinearity vs Code

tt
is

\

-2

lTCl285188'TPC07

ffi

~

'"

~ 0.15

-0.15
o

z -6
;;;:
'" -5
;;;;
w
-4
z

0

50

«
z

~
~

[;i

C
cn
~

C

z

30



TA = 25°C
Vee = 2.7V
10 VREF= 2.5V
ISMPL = ISMPL(MAX)

a

a:

"en

o

TA = 25°C
70 Vee = 2.7V
VREF = 2.5V
60 liN = 1kHz
ISMPL = ISMPL(MAX)
50

1

10

,/" i-"""

20

V

~

z

a

/'

z

~

60
70

:

20
10

90

o

100

100

TA = 25°C
Vee = 2.7V
VREF = 2.5V
ISMPL = ISMPL(MAX)

80

U3

10
INPUT FREQUENCY (kHz)

40

~ 50
:::>

V

30

30

C!l

20

:::>

80

:3
"- 40

40

IE

Attenuation vs Input Frequency

S/(N + D) vs Input Level

.... r...

100

-45 -40 -35 -30 -25 -20 -15 -10 -5
INPUT LEVEL (dB)

4096 Point FFT Plot

0

1k

""
TA =25°C
Vee =2.7V (VRIPPLE =1mV)
VREF =2.5V
ICLK =120kHZ

-10

-40

~

~

~

-20

-20

-40

19'-30

-60

'"isa: -50

~ -40

~

0

0

-60

:::>

t::

'"

:::>

t::
z

C!l

«

-80

II

:I:

@-60 I~ -70 r-80 r-90 r-

C!l

«
:;;

:;;

-80

-100

-100

'\

-100
0.5

Maximum Clock Frequency
vs Source Resistance

160

~ 140

-r--_

u

60
40
20

o

0.1

4.0

~

~

,/

N~

...

VIN

RSOURCE-

+INPUT

-INPUT

100

1
SOURCE RESISTANCE (1<.0)

10

220

§ 200
IE 180

'"

:I:

-INPUT

TA =25°C
VREf =2.5V

260

~ 240

5
;j!

1

10
100
1000
SOURCE RESISTANCE (il)

10M

Maximum Clock Frequency
vs Supply Voltage
280

a
E1000
cn

'~

10k
100k
1M
RIPPLE FREQUENCY (Hz)

1k

300

>=
z

100

fE 80

3.5

TA - 25°C
Vee = 2.7V
VREf = 2.5V

......... r-.,

~ 120

'"9

1.5 2.0 2.5 3.0
FREQUENCY (kHz)

10000
Tp 25°C
Vee = 2.7V
VREF= 2.5V

ilj

fa

1.0

Sample-and-Hold Acquisition
Time vs Source Resistance

200
180

10M

Power Supply Feedthrough
vs Ripple Frequency

Intarmodulation Distortion

-20

10k
100k
1M
INPUT FREQUENCY (Hz)

10000

9'" 160
u

V

/
/

........

-

....... ~

.......

140
120
100
2.5

3.0

3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)

5.5

6.0

LTC12/I5JBSoTPC21

6-29

LTC 1285/LTC 1288
TYPICAL PERFORmAnCE CHARACTERISTICS
Minimum Clock Frequency
for 0.1 LSB Error vs Temperature
120

'";:'~!:
~
:r:

80

F

60

flO

13
9
u

2.0

40
20

c;;

o

10

g 1.0

!3
I>-

/

./

2

o

20
30
40
50
TEMPERATURE ('C)

1.5

u

/

60

70

~ 0.5
;:'!:
c;;
is
0

2.5

3.0

V

Vee = 2.7V
VREF= 2.5V

-

2.5

ffl

a::

1000
TA = 25'C

w

iii

8

Input Channel Leakage Current
vs Temperature

~ 3.0

Vee =2.7V
VREF= 2.5V

100

~~

Digitallnpul Logic Threshold
vs Supply Voltage

100

V

....-...-

~

a::
a::

l1V

=>

u

ttl

~

3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)

lTCl2851880TPC22

/

10

5.5

6.0

1
ONCHANN~

0.1

0.01
-55 -35 -15

LTC12B5/88 0 1l'C23

,,

~

~FCHANNE

I~'
5 25 45 65 85 105 125
TEMPERATURE ('C)
LTC1285/880TPC24

Pin FunCTions
LTC1285

LTC1288

VREF (Pin 1): Reference Input. The reference input defines
the span of the AID converter.

IN+ (Pin 2): Positive Analog Input.

CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1288. A logic high on this input
disables and powers down the LTC1288.

IN- (Pin 3): Negative Analog Input.

CHO (Pin 2): Analog Input.

GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.

CH1 (Pin 3): Analog Input.

CS/SHDN (Pin 5): Chip Select Input. A logic low on this
input enables the LTC1285. A logic high on this input
disables and powers down the LTC1285.

GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
DIN (Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.

DOUT (Pin 6): Digital Data Output. The AID conversion
result is shifted out of this output.

DOUT (Pin 6): Digital Data Output. The AID conversion
result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer and determines conversion speed.

CLK (Pin 7): Shift Clock. This clock synchronizes the
serial data transfer and determines conversion speed.

Vcc (Pin 8): Power Supply Voltage. This pin provides
power to the AID converter. It must be kept free of noise
and ripple by bypassing directly to the analog ground
plane.

VCC/VREF (Pin 8): Power Supply and Reference Voltage.
This pin provides power and defines the span of the AID
converter. It must be kept free of noise and ripple by
bypassing directly to the analog ground plane.

6-30

LTC 1285/LTCl 288
BLOCK DIAGRAm
CS/SHDN

p--------------- ----------

r-~~~~1I~=t--~L,

:
I

T"I
I
I
I

IN+ (CHO)

DOUT

CS~MI-PL.....E"'--I

IN-(CH1)~~

> ......_ - - 1

SAR

GND
PIN NAMES IN PARENTHESES REFER TO THE LTC1288

TEST CIRCUITS
load Circuil for IdDO, Ir and I,
1.4V

Voltage Waveforms for DOUT Rise and Fall Times, Ir, I,

:!r
-lrJL

DOUT
3k

DOUT 1--.......- - - - TEST POINT

Jrmmn,.
--------------- VOL

......--tf

LTC1285/88·TC02

f100PF
LTC1285188·TCOl

Vollage Waveforms for DOUT Delay Times, IdDO

CLK1

_V~IL

TEST POINT
_ _ _ _ _ _ _ ____

_ldDO~
DOUT

load Circuil for Idis and len

- VOH
____________________________ VOL

Vee Idis WAVEFORM 2, len
~diS WAVEFORM 1

6-31

•

LTC 1285/LTC 1288

TEST CIRCUITS
Voltage Waveforms for tdis

Voltage Waveforms for ten
LTC1285

DOUT

~ ~~-----------------------------

---------------------+-----.

WAVEFORM 1
(SEE NOTE 1)

CLK

DOUT

WAVEFORM 2
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

°OUT

Voltage Waveforms for ten
LTC1288

~ ~~----------------------------------------------------____---J/
CLK

6-32

START

\~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

LTC 1285/LTC 1288
APPLICATion InFoRmATion
OVERVIEW
The LTC1285 and LTC1288 are 3V micropower, 12-bit,
successive approximation sampling AID converters. The
LTC1285 typically draws 160~ of supply current when
sampling at 7.5kHz while the LTC1288 nominally consumes 21 O~ of supply current when sampling at 6.6 kHz.
The extra 50~ of supply current on the LTC1288 comes
from the reference input which is intentionally tied to the
supply. Supply current drops linearly as the sample rate is
reduced (see Supply Current vs Sample Rate). The ADCs
automatically power down when not performing conversions, drawing only leakage current. They are packaged in
8-pin SO and DIP packages. The LTC1285 and LTC1288
operate on a single supply from 2.7V to 6V.
Both the LTC1285 and the LTC1288 contain a 12-bit
switched-capacitor ADC, a sample-and-hold, and a serial
port (see Block Diagram). Although they share the same

basic design, the LTC1285 and LTC1288 differ in some
respects. The LTC1285 has a differential input and has an
external reference input pin. It can measure signals floating on a DC common-mode voltage and can operate with
reduced spans to 1.5V. Reducing the spans allows it to
achieve 3661lV resolution. The LTC1288 has a two-channel input multiplexer and can convert either channel with
respect to ground or the difference between the two. The
reference input is tied to the supply pin.
SERIAL INTERFACE
The 2-channel LTC1288 communicates with microprocessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1285 uses a3-wire interface (see Operating Sequence
in Figures 1 and 2).

'1~'--------tcyC---------

cs!

-J~--------------------------~
r-tsucs

CLK

DOUT

-+~HI-.:..Z.....
tSMPL

'AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.
'
1------------~tCyC------------------......

"I

CLK

~--------------~--------------~
-I
HI-Z

DOUT -+---"H~I.Z:....,
tSMPL

'AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
'
tDATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB·FIRST DATA OR ZEROES.

LTCl2851B8·F01

Figure 1. LTC1285 Operating Sequence

6-33

LTC 1285/LTC 1288
APPLICATion InFoRmATion
MSB·First Data (MSBF =0)

___

~---------------------------~YC--------------------------------~-I

l-----------------,---------.....I

_I

CLK
ODDI
SIGN

START

DIN~

~DON'TCARE,_

SGU
MSBF
DIFF
DOUT _-I-""HI""-Z"",,

HI-Z

tSMPL

MSB·First Data (MSBF =1)

DDDI

~SIG~NIr-.",.""""""'""'""~~~~.,.,.,,.,.,.,"",,.,.,..,.,.,,,.,.,'""=

START

DIN~
§§1l

:
~DON'TCARE~
MSBF

IlJ

DIFF
HI-Z

DOUT _~H::.:I-Z'___+-.,
isMPL 1--__1---""-'''-'--------

• AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY,
tOATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.

Figure 2. LTC1288 Operating Sequence Example: Differential Inputs (CW, Cit-)

6-34

LTC 1285/LTCl 288
APPLICATion InFoRmATion
Data Transfer
The ClK synchronizes the data transfer with each bit
being transmitted on the falling ClK edge and captured
on the rising ClK edge in both transmitting and receiving
systems.
The l TC1285 does not require a configuration input word
and has no DIN pin. A falling CS initiates data transfer as
shown in the lTC1285 operating sequence. After CS falls
the second ClK pulse enables DOUT. After one null bit the
AID conversion result is output on the DOUT line. Bringing
CS high resets the lTC1285 for the next data exchange.
The lTC1288 first receives input data and then transmits
back the AID conversion result (half duplex). Because of
the half duplex operation, DIN and DOUT may be tied
together allowing transmission over just 3 wires: CS, ClK
and DATA (DIN/DoUT).
Data transfer is initiated by afalling chip select (CS) signal.
After CS falls the l TC1288 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the lTC1288 and starts the
conversion. After one null bit, the result of the conversion
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the lTC1288 in
preparation for the next data exchange.
~l~

The first "logical one" clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The lTC1288 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the DIN pin are then ignored until the next CS
cycle.
Multiplexer (MUX) Address
The bits of the input word following the START bit assign
the MUX configuration forthe requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the "+"
and "-" signs in the selected row of the following tables. In Single-ended mode, all input channels are measured ~
with respect to GND.
LTC1288 Channel Selection

!

I

I I f· t .I
••

1 NULL BIT

MUXADDRESS
SGLJDIFF ODD/SIGN

~

Dour 1

•

Start Bit

________~!l~________~rl

[§2J
SHIFTMUX
ADDRESS IN

the rising edge of the clock. The input data words are
defined as follows:

SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUXMODE

1
1
0
0

0
1
0
1

CHANNELl
0
1
+
+
+

-

GNO

-

+

SHIFT AID CONVERSION
RESULT OUT

MSB First/LSB First (MSBF)
Input Data Word
The lTC1285 requires no DIN word. It is permanently
configured to have a single differential input. The conversion result appears on the DOUT line. The data format is
MSB first followed by the lSB sequence. This provides
easy interface to MSB or lSB first serial ports. For MSB
first data the CS signal can be taken high after BO (see
Figure 1). The lTC1288 clocks data into the DIN input on

The output data of the l TC1288 is programmed for
MSB first or lSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
the DOUT line in MSB first format. logical zeros will be
filled in indefinitely following the last data bit. When the
MSBF bit is a logical zero, lSB first data will follow the
normal MSB first data on the DOUT line (see Operating
Sequence).

6-35

LTC 1285/LTC 1268
APPLICATion InFoRmATion
Transfer Curve
The l TC1285/l TC1288 are permanently configured for
unipolar only. The input span and code assignment for
this conversion type are shown in the following figures.
. Transfer Curve
111111111111

I

I

111111111110

I
.1
I
I
I
I
I

000000000001
I VIN
000000000000 +-.L...t--+----"\r----1-+---1__
llSB = VREF
4096
LTC1285188·Al04

either an input or an output. The l TC1288 will take control
of the data line and drive it low on the 4th falling ClK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens to avoid a conflict.
In the Typical Applications section, there is an example of
interfacing the lTC1288 with DIN and DouTtied together to
the Intel 8051 MPU.

ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 160~ and automatic
shutdown between conversions, the LTC1285/lTC1288
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). The auto-shutdown
allows the supply curve to drop with reduced sample rate.

Output Code
1000
OUTPUT CODE

INPUT VOLTAGE

INPUT VOLTAGE
(VREF = 5.OUUVj

11111111111111
11111111111110

VREF -llSB

VREF~2lSB

4.9.9878V
4.99756V

00000000000001
00000000000000

llSB
OV

0.00122V
OV

..

..

~~~i/tiv

2.5V

- felK = 120kHz

···

lTC1285188'AI05

Operation with DIN and DOUT Tied Together

/

The lTC1288 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to
communicate tothe microprocessor (MPU). Data is transmitted in both directions on a single wire. The processor
pin connected to this data line should be configurable as

1

0.1

1
10
SAMPLE FREQUENCY (kHz)

100

Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate

M_SB_FB_ITblA_~_H_ED_ _ _ _ _ _ _ _ _ _ ____

C S l...
• _ _ _ _ _ _ _ _ _ _ _ _ _ _ BY lTC1288

~
ClK

M. ,nor' /
--'1r-:::::\.
. START ~

!"'@®I+-__..... Bll ,--_81_0--/1 •
'-----------,v---------~. .: :~. . .-----~v.....;...----~. .
I
I

DATA
(DIN/Dour) _ _ _ _

ODD/SIGN

MPU CONTROLS DATA LINE AND SENDS
MUXADDRESS TO lTC1288

MSBF

I

I

I

I

I

PROCESSOR MUST RELEASE DATA LINE AFTER - I
4TH RISING ClK AND BEFORE THE 4TH FALLING ClK
I

I

lTC1288 CONTROLS DATA LINE AND SENDS
AID RESULT BACK TO MPU
,

1 - lTC1288 TAKES CONTROL OF DATA LINE

I

ON 4TH FALLING ClK
LTC1286/88F03

Figure 3. LTC12BB Operation with DIN and DOUT Tied Together

6-36

LTC 1285/LTCl 288
APPLICATion InFoRmATion
Several things must be taken into account to achieve such
a low power consumption.
Shutdown
The lTC1285/lTC1288 are equipped with automatic shutdown features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference
input becomes high impedance at the end of each conversion leaving the ClK running to clock out the lSB first data
or zeroes (see Figures 1and 2).lfthe CS is not running railto-rail, the input logic buffer will draw current. This current
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
ground when it is low and to supply voltage when it is high.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and ClK input have no effect on supply
current during this time. There is no need to stop DIN and
ClK with CS = high; they can continue to run without
drawing current.
Minimize CS Low Time
In systems that have significant time between conversions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the

/

TA =25°C
Vee =2.7V
VREF =2.5V

V

/'

/
./
,/

V

_I
CS - Vee

0.002

o

1

/' cs=o
(AFT~R CONVERSION)-

W

~
00
W
FREQUENCY (kHz)

100

lW

Figure 5. Shutdown Current with CS High is 1nA IYPically,
Regardless of the Clock. Shutdown Current with CS =Ground
Varies From 1!JA at 1kHz to 9~ at 120kHz

lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
lSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1J1A at 1kHz to 9J1A at 120kHz. When
CS =Vee, the logic is gated off and no supply current is
drawn regardless of the clock frequency.
DOUT Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capaCitor on the DOUT pin
can add more than 16.2J1A to the supply current at a
120kHz clock frequency. An extra 16.2J1A or so of current
goes into charging and discharging the load capaCitor. The
same goes for digital lines driven at a high frequency by
any logic. The Cx Vx f currents must be evaluated and the
troublesome ones minimized.
OPERATING ON OTHER THAN 3V SUPPLIES
Both the lTC1285 and the lTC1288 operate from a 2.7V . .
to 6V supply. To operate the lTC1285/lTC1288 on other . . .
than 3V supplies a few things must be kept in mind.
Input Logic Levels
The input logic levels of CS, ClK and DIN are made to
meet TIL on a3V supply. When the supply voltage varies,
the input logic levels also change. For the l TC12851
l TC1288 to sample and convert correctly, the digital
inputs have to be in the proper logical low and high levels
relative to the operating supply voltage (see typical curve
of Digital Input logic Threshold vs Supply Voltage). If
achieving micropower consumption is desirable, the
digital inputs must go rail-to-rail between supply voltage
and ground (see ACHIEVING MICROPOWER PERFORMANCE section).
Clock Frequency
The maximum recommended clock frequency is 120kHz
for the l TC1285/l TC1288 running off a 3V supply. With
the supply voltage changing, the maximum clock frequency forthe devices also changes (see the typical curve

6-37

LTC 1285/LTC 1288
APPLICATion InFoRmATion
of Maximum Clock Rate vs Supply Voltage). If the maximum clock frequency is used, care must be taken to
ensure that the device converts correctly.

BOARD LAYOUT CONSIDERATIONS

Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1285/LTC1288
operating on a 3V supply. The inputs of CS, CLK and DIN
of the LTC1285/LTC1288 have no problem to take a
voltage swing from OV to 5V. With the LTC1285 operating
on a 3V supply, the output of DOUT may only go between
OV and 3V. The 3V output level is higher enough to trip a
TTL input of the MPU. Figure 6 shows a 3V powered
LTC1285 interfacing a 5V system.
3V 4.7J!F

~...-----.
MPU
(e.g.8D51)

5V

P1.4

-+----4--1 P1.3
-+----1 P1.2

DIFFERENTIAL INPUTS
CDMMON·MODE RANGE
DVT03V
LTC1285

LTC1285/88·F06

Figure 6. Interfacing a 3V Powered LTC1285to a 5V System

Grounding and Bypassing
The LTC1285/LTC1288 are easy to use if some care is
taken. They should be used with an analog ground plane
and single pOint grounding techniques. The GND pin
should be tied directly to the ground plane.
The Vee pin should be bypassed to the ground plane with
a1OJ,lf tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1285/LTC1288 can
also operate with smaller 1J,1f or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
SAMPLE-AND-HOLD

Both the LTC1285 and the LTC1288 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1285 acquires input signals from "+" input
relative to "-" input during the tSMPL time (see Figure 1).
However, the S&H of the LTC1288 can sample input
signals in the single-ended mode or in the differential
inputs during the tSMPL time (see Figure 7).

elK

DIN

DOUT ------------i~----+____.

"+"INPUT

"-"INPUT

v

~

---------------'

Figure 7. LTC1288 "+" and "-" Input Settling Windows

6-38

=.'''

'----,='"~...

LTC 1285/LTC 1288
APPLICATion InFoRmATion
Single-Ended Inputs

"+" Input SeHling

The sample-and-hold of the lTC1288 allows conversion
of rapidly varying signals. The input voltage is sampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling ClK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.

The input capacitor of the lTC1285 is switched onto "+"
input during the tSMPL time (see Figure 1) and samples
the input signal within that time. However, the input
capacitor of the l TC1288 is switched onto U+" input
during the sample phase (tSMPL, see Figure 7). The
sample phase is 1 1/2 ClK cycles before conversion
starts. The voltage on the u+"input must settle completely within tSMPLE for the l TC1285 and the l TC1288
respectively. Minimizing RSOURCE+ and C1 will improve
the input settling time. If a large U+" input source resistance must be used, the sample time can be increased by
using a slower ClK frequency.

Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two voltages. In this case, the voltage on the selected "+" input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the voltage on the selected "-" input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be performed accurately. The conversion time is 12 ClK cycles.
Therefore, a change in the "-" input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the "-" input this error would be:
VERROR (MAX) = VPEAK x 2 x 1t X f("-") x 121fcLK
Where f("-") is the frequency of the "-" input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
ClK. In most cases VERROR will not be significant. For a
60Hz signal on the "-" input to generate a 1/4lSB error
(1521.N) with the converter running at ClK =120kHz, its
peak value would have to be 4.03mV.
ANALOG INPUTS
Because of the capacitive redistribution AID conversion
techniques used, the analog inputs of the lTC12851
lTC1288 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.

L7lJD~

"-" Input Settling
At the end of the tSMPL, the input capacitor switches to the
U_" input and conversion starts (see Figures 1 and 7).
During the conversion, the "+" input voltage is effectively
"held" by the sample-and-hold and will not affect the
conversion result. However, it is critical that the "-" input
voltage settles completely during the first ClK cycle ofthe
conversion time and befree of noise. Minimizing RSOURCE- . .
and C2 will improve settling time. If a large "-" input . .
source resistance must be used, the time allowed for
settling can be extended by using aslower ClK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the u+" and "-" input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps, including the l T1 006 and
lT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 12.5~ (u+"
input) which occur at the maximum clock rate of 120kHz.
Source Resistance
The analog inputs of the lTC1285/lTC1288 look like a
20pF capacitor (CIN) in series with a 500n resistor (RON)
as shown in Figure 8. CIN gets switched between the

6-39

LTC 1285/LTC 1288
APPLICATion InFoRmATion
selected "+" and "-" inputs once during each conversion
cycle. Large external source resistors and capacitances
will slow the settling of the inputs. It is important that the
overall RC time constants be short enough to allow the
analog inputs to completely settle within the allowed time.
Ut"

Input Leakage Current
Input leakage currents can also create errors ifthe source
resistance gets too large. For instance, the maximum
input leakage specification of 1~ (at 125°C) flowing
through asource resistance of 2400 will cause avoltage
drop of 240/lV or O.4LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve of Input Channel Leakage
Current vs Temperature).
REFERENCE INPUTS

Figure 8. Analog Input Equivalent Circuit

AC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 9. For large values of CF (e.g., 1/lf), the
capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with
a small resistor and large capaCitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately loc = 20pF x VIN/tCYC and is roughly
proportional to VIN. When running at the minimum cycle
time of 133.3f.lS, the input current equals 0.375~ at VIN
= 2.5V. In this case, a filter resistor of 1600 will cause
0.1 LSB of full-scale error. If a larger filter resistor must
be used, errors can be eliminated by increasing the cycle
time.

The reference input of the LTC1285 is effectively a 50kO
resistor from the time CS goes low to the end of the
conversion. The reference inputbecomesa high impedence
node at any other time (see Figure 10). Since the voltage
on the reference input defines the voltage span of the AID
converter, the reference input should be driven by a
reference with low ROUT (ex. LT1 004, LT1 019 and LT1 021)
or a voltage source with low ROUT.

lTC12&518S'F10

Figure 10. Reference Input Equivalent Circuit

Reduced Reference Operation
The minimum reference voltage of the LTC1288 is limited
to 2.7V because the Vcc supply and reference are internally tied together. However, the LTC1285 can operate
with reference voltages below 1.5V.

lTC1285J8B-fQ9

Figure 9. RC Input Filtering

6-40

The effective resolution of the LTC1285 can be increased
by redUCing the input span of the converter. The LTC1285
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Change in linearity vs Reference Voltage and Change in Gain vs Reference

LTC 1285/LTC 1288
APPLICATion InFoRmATion
Voltage). However, care must be taken when operating at
low values of VREF because of the reduced LSB step size
and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low VREF values:
1. Offset
2. Noise
3. Conversion speed (CLK frequency)

noise becomes equal to 3.3lSBs and a stable code may
be difficult to achieve. In this case averaging multiple
readings may be necessary.
This noise data was taken in avery clean setup. Any setup
induced noise (noise or ripple on Vcc, VREF or VIN) will add
to the internal noise. The lower the reference voltage to be
used the more critical it becomes to have aclean, noise free
setup.

Offset with Reduced VREF

Conversion Speed with Reduced VREF

The offset of the LTC1285 has alarger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Change in Offset vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of Vas. For example,
a Vas of 122,N which is O.2LSB with a 2.5V reference
becomes 1LSB with a1Vreference and 5LSBs with aO.2V
reference. If this offset is unacceptable, it can be corrected
digitally by the receiving system or by offsetting the U_"
input of the LTC1285.

With reduced reference voltages, the lSB step size is
reduced and the LTC1285 internal comparator overdrive is reduced. Therefore, it may be necessary to
reduce the maximum ClK frequency when low values
of VREF are used.

Noise with Reduced VREF
The total input referred noise of the LTC1285 can be
reduced to approximately 400~V peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 2.5V reference but will become a
larger fraction of an LSB as the size ofthe LSB is reduced.
For operation with a 2.5V reference, the 400~V noise is
only O.66LSB peak-to-peak. In this case, the lTC1285
noise will contribute a little bit of uncertainty to the
output code. However, for reduced references the noise
may become a significant fraction of an lSB and cause
undesirable jitter in the output code. For example, with
a 1.25V reference this same 400~V noise is 1.32lSB
peak-to-peak. This will reduce the range of input voltages over which astable output code can be achieved by
1LSB.lfthe reference is further reduced to 1V, the 400~V

.L7lJD~

DYNAMIC PERFORMANCE
The LTC1285/LTC1288 have exceptional sampling capability. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC's frequency response, distortion and noise at the rated throughput. By applying a
low distortion sine wave and analyzing the digital output . .
using an FFT algorithm, the ADC's spectral content can be . .
examined for frequencies outside the fundamental. Figure
11 shows a typical LTC1285 plot.

iii" -40
:!:w
c
~

Z
~
:2

-60

f--+--+--+-+-+-+---+---l

-80

1--+-+-+-+-+-+-+---1

-100

LTC1285188'TPC16

Figure 11. LTC1285 Non-Averaged, 4096 Point FFT Plot

6-41

LTC 1285/LTC1288
APPLICATion InFoRmATion
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio (SIN + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other frequency components at the ADC's output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 12 shows atypical spectral content with a 7.5kHz sampling rate.
_

12
11

~

10

~

74
68 ~
62
56 c:
50 .!!l

r-

S

9

~

OJ

o

6
5

'"'">

i

TA =25'C

Vcc =2.7V

o

fCLK =120kHz

1

10
INPUT FREQUENCY (kHz)

~v~+vj+v1+ ... +v~
V1

where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD specification in the Dynamic Accuracy table includes the 2nd
through 5th harmonics. With a 1kHz input signal, the
LTC1285/LTC1288 have typical THD of 80dB with
Vee = 2.7V.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition
to THD. IMD is the change in one sinusoidal input
caused by the presence of another sinusoidal input at a
different frequency.

u.

ffi
§'"

THD=2010g

100

Figure 12. Effective Bits and S/(N + OJ vs Input Frequency

Effective Number of Bits
The Effective Number of Bits (ENOBs) is ameasurement of
the resolution of an ADC and is directly related to S/(N+D)
by the equation:

If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa +fb) and
(fa - fb) while 3rd order IMD terms include (2fa + fb),
(2fa - fb), (fa + 2fb), and (fa - 2fb). If the two input sine
waves are equal in magnitudes, the value (in dB) ofthe 2nd
order IMD products can be expressed by the following
formula:

ENOB = [S/(N + D) -1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 7.5kHz with a 2.7V supply, the LTC1285
maintains above 10.7 ENOBs at 10kHz input frequency.
Above 10kHz the ENOBs gradually decline, as shown in
Figure 12, due to increasing second harmonic distortion.
The noise floor remains low.

For input frequencies of 2.05kHz and 3.05kHz, the IMD of
the LTC1285/LTC1288 is 72dB with a 2.7V supply.

Total Harmonic Distortion

Peak Harmonic or Spurious NOise

Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics ofthe input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half ofthe sampling frequency. THD
is defined as:

The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in dBs relative to the RMS value of afullscale input signal.

6-42

amplitude (fa ± fb)]
IMD(
fa ±)
fb = 2010g [ _ _ _.L......---L
amplitude at fa

LTC 1285/LTCl 288
TYPICAL APPLICATions
MICROPROCESSOR INTERFACES
The LTC1285/LTC1288 can interface directly without external hardware to most popular microprocessor (MPU)
synchronous serial formats (see Table 1). If an MPU
without a dedicated serial port is used, then 3 or 4 of the
MPU's parallel port lines can be programmed to form the
serial link to the LTC1285/LTC1288. Included here is one
serial interface example and one example showing a
parallel port programmed to form the serial interface.

Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1286/lTC1298

MC6805S2,S3
MC68HC11
MC68HC05
CDP68HC05

SPI

Hitachi

HD6305
HD63705
HD6301
HD63701
HD6303
HD64180

The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MS8
-first and in 8-bit increments. The DIN word sentto the data
register starts with the SPI process. With three 8-bit
transfers, the AID result is read into the MPU. The second
8-bittransfer clocks 811 through 88 ofthe AID conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits, 87 through 80, into the MPU. The data
is right justified into two memory locations. ANDing the
second byte with OFHEX clears the four most significant
bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
In this example the DIN word configures the input MUX for
asingle-ended inputto be applied to CHO. The conversion
result is output MS8-first.

SPI
SPI
SPI

RCA

Motorola SPI (MC68HC11)

MC68HC11 Code

TYPE OF INTERFACE

PART NUMBER
Motorola

SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O

National Semiconductor

C0P400 Family
COP800 Family
NS8050U
HPC16000 Family

MICROWIREt
MICROWIRE/PLUSt
MICROWIREIPLUSt
MICROWIREIPLUSt

Texas Instruments

TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011 *
TMS32020

Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port

Intel

8051
Bit Manipulation on Parallel Port
Requires external hardware
t MICROWIRE and MICROWIREIPLUS are trademarks of
National Semiconductor Corp.
*

6-43

LTC 1285/LTC 1288
TYPICAL APPLICATions
Timing Diagram for Interface to the MC68HC11

~\~----------------------------------~;ClK

O'N _ _ _ _

m

--'~71/1!IIml//I/J/I!JIIt~~'~W/11II!III!Jf/l!JlI!ll1

Dour - - - - - - - - - - - - - - " " " \

MPU
TRANSMIT
WORD

10 10 1

MPU
RECEIVED
WORD

0

1 0 1 0 1 0 1 0 l' 1
BYTE 1

1 ? 1 ? 1 ? 1 ? 1 ? 1 ? I? 1
BYTE 1

?

1

1~~itlg~~IMSBFI

I? I

?

1

?

x 1x 1x 1x 1x 1
BYTE 2

1 x Ixlxlxlxlxl x 1 x 1

1 0 1 B11 1Bl0 1 B9 1 BB 1
BYTE 2

1 B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 Bl 1 BO 1
BYTE 3

BYTE 3 (DUMMY)

Hardware and Software Interface to the MC68HC11
DOUT FROM LTC1298 STORED IN MC68HCll RAM
MSB

#62

I I I I I I I I
I
I
I I
0

0

0

0

B11

B10

B9

LSB

#63

B71 B61 B5

B41 B31 B21 B1

+-----1

DO

+-----1

SCK

t-----+I

MC6SHC11
MISO

1+-----1

MOSI

Bsl BYTE 1

BO

ANALOG {
INPUTS

BYTE2

LTC1285/88'TA04

LABEL MNEMONIC
LDM
STM
LDM
STM
LDM
STM
LDM
STM
LDM

LOOP

OPERAND
#$50
$1028
#$1B
$1009
#$01
$50
#$AO
$51
#$00

STM
LDX

$52
#$1000

BCLR
LDM
STM
LDM

$08,X,#$01
$50
$102A
$1029

6-44

COMMENTS
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT DDDR
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $50
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $51
LOAD DUMMY DIN WORD INTO
ACCA
LOAD DUMMY DIN DATA INTO $52
LOAD INDEX REGISTER X WITH
$1000
DO GOES LOW (CS GOES LOW)
LOAD DIN INTO ACC A FROM $50
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG

LABEL MNEMONIC
WAIT1 BPL
LDM
STM
WAIT2 LDM
BPL
LDM
STM
LDM
STM
WAIT3 LDM
BPL
BSET
LDM
STM
JMP

OPERAND
WAIT1
$51
$102A
$1029
WAIT2
$102A
$62
$52
$102A
$1029
WAIT3
$08,X#$01
$102A
$63
LOOP

COMMENTS
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1288 MSBs INTO ACC A
STORE MSBs IN $62
LOAD DUMMY INTO ACC A
FROM $52
LOAD DUMMY DIN INTO SPI,
STARTSCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
DO GOES HIGH (CS GOES HIGH)
LOAD LTC1288 LSBs IN ACC
STORE LSBs IN $63
START NEXT CONVERSION

LTC 1285/LTCl 288
rYPICAl APPLICATions
Interfacing to the Parallel Port of the INTEL 8051

Family
The Intel 8051 has been chosen to demonstrate the
interface between the l TC1288 and parallel port microprocessors. Normally the CS, ClK and DIN signals would
lJe generated on 3 port lines and the DOUT signal read on
i 4th port line. This works very well. However, we will
jemonstrate here an interface with the DIN and DOUT of the
LTC1288 tied together as described in the SERIAL INTERFACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1288 over the data line connected to P1.2. Then P1.2
s reconfigured as an input (by writing to it a one) and the
g051 reads back the 12-bit AID result over the same data
ine.

LABEL

LOOP 1

MOV

CLR
MOV
LOOP 2

LOOP 3

-----I
--r:;::::==i

P1.4
" ' - - - - - / P1.3 8051
P1.2
•
MUXADDRESS L..-_ _---I

ANALOG!
INPUTS

lTC1285/8S"TAOl

AID RESULT

MNEMONIC
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ

MOV

RLC
SETB
CLR
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ

MOV

LOOP 4

RRC
DJNZ

MOV

SETB
lOUT FROM 1288 STORED

OPERAND
COMMENTS
A, #FFH
DIN word fQLLTC1288
Pl.4
~ake sure CS is high
P1.4
CS goes low
R4, #04
Load counter
Rotate DIN bit into Carry
A
SCLK goes low
Pl.3
Pl.2, C
Output DIN bit to LTC1288
Pl.3
SCLK goes high
R4, LOOP 1 Next bit
Pl, #04
Bit 2 becomes an input
SCLK goes low
Pl.3
R4, #09
Load counter
C, P1.2
Read data bit into Carry
A
Rotate data bit into Acc.
SCLK goes high
P1.3
SCLK goes low
P1.3
R4, LOOP 2 Next bit
R2, A
Store MSBs in R2
A
Clear Acc.
Load counter
R4, #04
Read data bit into Carry
C, P1.2
Rotate data bit into Ace.
A
P1.3
SCLK goes high
P1.3
SCLK goes low
R4, LOOP 3 Next bit
R4, #04
Load counter
Rotate right into Acc.
A
R4, LOOP4 Next Rotate
R3,A
Store LSBs in R3
CS goes high
P1.4

IN 8501 RAM

MSB
~2 IB11 81089 B8 B7 86 85 84
LSB
0
~3 IB3 B2 B1 BO 0 0 0

1

1

MSBF BIT LATCHED
INTO LTC1288

\.

I

\~------------~!----------------------------~I
I
I
I

:LK

BO
I I

------------YT------------~,::,~------------------YT--------------------~
8051 P1.2 OUTPUTS DATA
TO LTC1288

I I

: :

LTC1288 SENDS AID RESULT
BACK TO 8051 P1.2

I I

8051 P1.2 RECONFIGURED
I I
AS IN INPUT AFTER THE 4TH RISING CLK _ : : _ LTC1288 TAKES CONTROL OF DATA
AND BEFORE THE 4TH FALLING CLK
LINE ON 4TH FALLING CLK

6-45

LTC 1285/LTC 1288
TYPICAL APPLICATions
A "Quick Look" Circuit for the LTC1285

Micropower Battery Voltage Monitor

Users can get aquick look at the function and timing of the
LT1285 by using the following simple circuit (Figure 13).
VREF is tied to Vee. VIN is applied to the +IN input and the
-IN input is tied to the ground. CS is driven at 1/16 the
clock rate by the 74C161 and OOUT outputs the data. The
output data from the OOUT pin can be viewed on an
oscilloscope that is set up to trigger on the falling edge of
CS (Figure 14). Note the LSB data is partially clocked out
before CS goes high.

A common problem in battery systems is battery voltage
monitoring. This circuit monitors the 1ocell stack of NiCad
or NiMH batteries found in laptop computers. Itdraws only
40~ from the 2.7V supply at fSMPL = 0.1 kHz and 30~ to
62~ from the battery. The 12-bits of resolution of the
LTC1285 are pOSitioned over the desired range of 8V to
16V. This is easily accomplished by using the AOC's
differential inputs. Tying the -input to the reference gives
an AOC input span of VREF to 2VREF (1 .2V to 2.4V). The
resistor divider then scales the input voltage for 8V to 16V.
BATIERY MONITOR
INPUT 8V TO 16V

2.7V

220k

cs
elK
DOUl

39k
LTC1285188 o F13

CLOCK IN 120kHz

'--v---'"
TO OSCillOSCOPE

Figure 13. "Quick Look" Circuillor the LTC1285

BIT

MSB
(Bl1)
VERTICAL: 2VIDIV
HORIZONTAL: 20~S/DIV

Figure 14. Scope Trace the LTC1285 "Quick Look" Circuil
Showing AJD Output 101010101010 (AAAHEX)

6-46

Figure 15. Micropower Battery Voltage Monitor

LTC 1285/LTC1288
"ELATED PARTS
'ART NUMBER

DESCRIPTION

COMMENTS

TC1096/lTC1098

8-Pin SOIC, Micropower 8-Bit ADC

TC1196/lTC1198

8-Pin SOIC, 1Msps 8-bit ADC

low Power, Small Size, low Cost
low Power, Small Size, low Cost

TC1282

3V High Speed Parallel 12-Bit ADC

Complete, VREF, ClK, Sample-and-Hold, 140ksps

TC1289

Multiplexed 3V, 1A 12-Bit AOC

8-Channel, 12-Bit Serial 110

TC1522

16-Pin SOIC, 3V Micropower 12-Bit ADC

4-Channel, 12-Bit Serial 110

•

L7lJD~

6-47

fAl'''''"llneJ\Q
~~TECHNOLOG~~~---------c-o-m--p-le-te--1-2--8-it
LT574A

AID Converter
FEATURES

DESCRIPTion

• Industry-Standard 574A Compatible
• Complete 12-Bit AID Converter with
Reference and Clock
• Improved Reference Output Current Capability
• 25!JS Maximum Conversion Time
• Fast Bus Access Time
• 8- or 16-Bit Microprocessor Interface
• Guaranteed Linearity over Temperature

The L~57 4A is a complete 12-bit AID converter in the
industry-standard 574A pinout. The three-state output
buffers interface directlyto an 8- or 16-bit microprocessor
bus. Ahigh precision 1OV reference and clock are included
on-chip, and the device provides full-rated performance
without external circuitry or clock signals.
The LT57 4A provides several advantages over other 574A
type devices. External load driving capability of the reference has been improved to up to 8.5mA beyond the ADC
current required. Maximum Vee has been increased to
22V and the reference can source full load current at aVee
of 11.4V without requiring an external buffer. The reference is trimmed to 1O.OOV with 0.2% maximum error and
5ppm/oC typical TC. Bus timing specifications are significantly faster than original 574A specifications, easing
microprocessor interface concerns.

APPLICATions
• Signal Processing
• Data Acquisition
• Process Monitoring and Control

£T, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL PERFORmAnCE
Integral Linearity
0.5

.-------:---,....----,------,,....----;------,----:---~

0.4
0.3

~ 0.2

g§

0.1

~

0

a:
a:

~ -0.1

z

:::;

-0.2
-0.3
-0.4
-0.5

'---~--~----'--~'---~-~----'------'-'

o

500

1000

1500

2000
CODE

6-48

2500

3000

3500

4000

LT574A
~BSOLUTE

mRXlmum RRTlnGS

PACKAGE/ORDER InFORmATion

ICC to Digital Common .................................. OV to 22V
lEE to Digital Common.. ........................... OV to -16.5V
ILOGIC to Digital Common ............................... OV to 7V
\nalog Common to Digital Common ...................... ±1V
ligitallnputs to
Digital Common .................... -O.5V to VLOGIC + O.5V
\nalog Inputs (REF In, BIP Off, 10VIN)
to Analog Common ................................ VEE to 16.5V
!OVIN to Analog Common ............................. VEE to 24V
IEF Out ................. Indefinite Short to Analog Common
Momentary Short to VCC
lower Dissipation ...... ................ ..................... 1000mW
'unction Temperature .......................................... 165°C
lperating Temperature Range
J, K, L Grades ......................................... O°C to 70°C
itorage Temperature ........................... -65°C to 150°C
.ead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER

TOP VIEW

LT574AJNW
LT574AKNW
LT574ALNW

NW PACKAGE
2B-LEAD PDIP WIDE
TJMAX =100'C, 9JA =70'C/W

Consult factory for Industrial and Military grade parts,

:onVERTER ELECTRICRL CHRRRCTERISTICS
A=25°C, Vcc =12V or 15V, VEE =- 12V, VLOGIC =5V, unless otherwise specified.
LT574AJ
ARAMETER
esolution
Itegral Linearity Error
ifferential Linearity Error (Minimum Resolution for Which
o Missing Codes are Guaranteed)
nipolar Offset (Adjustable to Zero)
ipolar Offset (Adjustable to Zero)
JII-Scale Calibration Error (With Fixed 50n
EF Outto REF In (Adjustable to Zero)
lmperature Coefficients
Unipolar Offset
Bipolar Offset
Full-Scale Calibration
upply Sensitivity (Change in Full Scale Calibration)
13.5V s Vcc s16.5Vor 11.4V sVcc s12.6V
-16.5V s VEE s-13.5Vor 12.6V s VEE s -11.4V
4.5V s VLOGIC s 5.5V
Iput Ranges
Unipolar
Bipolar
put Impedance
10V Span
20V Span

L7lJ!J~

•
•
•

MIN

TYP

LT574AL

LT574AK
MAX
12
±1

11

MIN

TYP

MAX
12
±0.5

12
±1
±4
±10

•
••

±2(10)
±2(10)
±9(50)

±1(5)
±1(5)
±5(27)

•
•
•

±2.0
±2.0
±0.5

±1.0
±1.0
±O.5

a
a
-5
-10
3
6

5
10

a
a

10
20
5
10

-5
-10

7
14

3
6

TYP

MAX
12
±0.5

12

±2
±4
±10

••
••
••

MIN

5
10

±1
±2
±4

UNITS
Bits
LSB
Bits
LSB
LSB
LSB

±1(5) LSB(ppm/°C)
±1(5) LSB(ppm/oC)
±2(10) LSB(ppm/oC)
±1.0
±1.0
±0.5

a
a

10
20
5
10

-5
-10

7
14

3
6

5
10

LSB
LSB
LSB

10
20
5
10

V
V
V
V

7
14

kn

kn

6-49

LT574A

InTERnAL REFEREnCE ELECTRICAL CHARACTERISTICS
PARAMETER
REF OUT Voltage (No Load)
Line Regulation, 11.4 ~ VIN ~ 22V
Load Regulation (Sourcing Current), 0 ~ lOUT ~ lOrnA

LT574AJ
MIN TYP MAX
9.98
10.02
1
5
10
12
30
50
50

•
•

•

Reference Temperature Coefficient

LT574AK
MIN TYP MAX
9.98
10.02
1
5
10
12
30
50
27

LT574AL
MIN TYP MAX
9.99
10.01
1
5
10
12
30
50
10

UNIT!
\

ppm/\
ppm/\
ppm/mt
ppm/mt
ppm;o(

DIGITAL AnD DC ELECTRICAL CHARACTERISTICS
SYMBOL

VIH
VIL
liN
CIN
VOH
VOL
COUT

PARAMETER
VLOGIC Supply Range
VEE Supply Range
Vcc Supply Range
VLOGIC Operating Current
VEE Operating Current
Vcc Operating Current
Power Dissipation
Logic High Input Voltage
Logic Low Input Voltage
Logic Input Current
Digital Input Pin Capacitance
Logic Output Voltage
Logic Low Output Voltage
Leakage Current
Output Capacitance

CONDITIONS

1218, CE, Ao, RIC, CE
1218, CE, Ao, RIC, CE

•
•
•
•

•
•
•
•
•
•

ISOURCE ~ 600~
ISINK ~ 1.6mA
High-Z State

LT574A, All Grades
MIN
MAX
TYP
4.5
5.0
5.5
-11.4
-16.5
11.4
22.0
27
40
-15
-25
3.5
1.7
390
700
2.0
5.5
-0.5
0.8
-100
100
5
2.4
0.4
-20
20
5

UNIT!
\
\
\

mJ
mt
mJ
mVl
\
\

W
pi
\
\

W
pi

The. denotes the specifications which apply over the full operating
temperature range.

DIGITAL TiminG ELECTRICAL CHARACTERISTICS
Tp 25°C, Vcc = 15V, VEE = -15V, VLOGIC = 5V, unless otherwise specified.

Read Timing, Full Control Mode

6-50

SYMBOL
too
tHO
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR

PARAMETER
Access Time (from CE)
Data Valid After CE Low
Output Float Delay
CS-to-CE Setup
RlC-to-CE Setup
AO-to-CE Setup
CS Valid After CE Low
RIC High After CE Low
Ao Valid After CE Low

LT574A, All Grades
MIN
TYP
MAX
75
150
25
150
50
0
50
50
0
50

UNIT!
m
m
m
m
m
m
m
m
m

LT574A
DIGITAL TiminG ELECTRICAL CHARACTERISTICS
TA =25°C, Vcc =15V, VEE =-15V, VLOGIC =5V, unless otherwise specified.
SYMBOL
tDSC
tHEC
tssc
tHSC
tSRC
tHRC
tSAC
tHAC
tc

Convert Start Timing, Full Control Mode

Stand-Alone Mode Timing

tHRL
tDS
tHDR
tHS
tHRH
tDDR

LT574A, All Grades
MIN
TYP
MAX
200
50
50
50
50
50
0
50

PARAMETER
STS Delay from CE
CE Pulse Width
CS-to-CE Setup
CS Low During CE High
R/C-to-CE Setup
RIC Low During CE High
AD-to-CE Setup
AD Valid During CE High
Conversion Time
8-Bit Cycle
12-Bit Cycle
Low RIC Pulse Width
STS Delay From RIC
Data Valid After RIC Low
STS Delay After Data Valid
High RIC Pulse Width
Data Access Time

10
15
50

200
25
25
150

600
150

BLOCK DIAGRAm

28

[IS
[IS

ns
ns
ns
ns
ns
ns

STATUS

27 DBll (MSB)
2..---..r----,-------1====~=T==j~
26 DB10

+VLOGIC
12/8 ..::...----i

cs

17
25

UNITS
ns
ns
ns
ns
ns
ns
ns
ns

NIB
A

.....::...----i CONTROL

Ao

LOGIC

RIC - " - - - - - I

CE~~

NIB
B

+Vcc~

REF OUT - " - - - - - I
SUCCESSIVE
APPROXIMATION
REGISTER

ANALOG -.::9:....-_ _ _ _..
COMMON

REF IN 10

19.95k

25 DB9
24 DBB
23 DB7
22 DB6
21 DB5
20 DB4

19 DB3
NIB lB DB2
C 17 DBl
16 DBO (LSB)
15 DIGITAL
~COMMON

12 BITS

-Vee _1_1_
BIP OFF 12
13
AIN 10V
14
AIN 20V

5k

574AfOl/BD

Figure 1. LT574A Block Diagram

6-51

LT574A
DISCUSSion OF SPECIFICATions
Integral Linearity Error
Integral linearity (INL) error refers to the deviation of each
code from atheoretical line drawn from "full scale." Zero
is defined as the input voltage occurring 0.5LSB (1.22mV
for 10V full scale) before the first code transition (0 to 1)
and "full scale" is defined as the voltage occurring 1.5LSB
beyond the last code transition (4094 to 4095).

Differential Linearity Error
A guaranteed "no missing codes" specification requires
that every code combination appears in a monotonically
increasing sequence. Thus LT574A grades which guarantee no missing codes to 12-bit resolution have amaximum
DNL error of ±1 LSB; grades which guarantee no missing
code to an 11-bit level means that all code combinations
ofthe upper 11 bits are present. In practice very few ofthe
12-bit codes are missing on the lower grade(s).

Unipolar Offset
Unipolar offset error is defined as the deviation of the first
code transition from a level 0.5LSB above analog common. Unipolar offset can be adjusted as shown on the
following pages. The unipolar offset temperature coeffi-

cient specifies the change of the first transition value
versus a change in ambient temperature.

Bipolar Offset
The major carry transition (2047 to 2048) should occu rfor
an analog value 0.5LSB above analog common in the
bipolar mode. Bipolar offset error can also be adjusted as
shown on the following pages. The bipolar offset error and
temperature coefficient specify the initial deviation and
maximum change in the error versus temperature.

Quantization Uncertainty
Analog-to-digital converters have inherent quantization
uncertainty of ±0.5LSB. This uncertainty is afundamental
property of the conversion process and cannot be reduced
for a converter of a given resolution.

Left-Justified Data
The LT574A uses a left-justified data format. The analog
input is represented as afraction offull scale, ranging from
oto 4095/4096. A binary point to the left of the MSB is
implied.

FEEDBACK TO AMPLIFIER

v-

liN IS MODULATED BY
CHANGES IN TEST CURRENT.
AMPLIFIER PULSE LOAD
RESPONSE LIMITED BY
OPEN-LOOP OUTPUT IMPEDANCE.

ANALOG COMMON

Figure 2. Op Amp/lT574A Interface

6-52

LT574A
DISCUSSion OF SPECIFICATions
Full-Scale Calibration Error

OFFSET
. R1
100k

The last output code transition (4094 to 4095) should
occur for an analog value 1.5LSB below the nominal full
scale (9.9963V for 1O.OOOV full scale). The deviation ofthe
actual level at which this transition occurs from the ideal
level is the full-scale calibration error. Typically less than
0.1% of full scale, this error can be adjusted to zero as
shown in Figures 3 and 4.
Temperature Coefficients
The temperature coefficients for unipolar offset, bipolar
offset and full-scale calibration specify the maximum
change from the nominal (25°C) value to TMIN or TMAX.
574AFOO

Power Supply Sensitivity

Figure 3. Unipolar Input Connections

The LT574A is specified using 5V and ±15V or ±12V
supplies. The major effect of power supply voltage deviations from the rated values will be a small change in fullscale calibration. This change results in a proportional
change in all code values.
Code Width

II

Code width is defined as the range of analog values for
which a given output code will occur. The ideal value of a
code width is equivalent to 1LSB (least significant bit) of
the full-scale range. In a 10V full-scale range one LSB
corresponds to 2.44mV.
Figure 4. Bipolar Input Connections

OPERATion
Circuit Operation
The LT574A provides the complete 12-bit analog-to-digital function with no external components. Ablock diagram
of the LT574A is shown in Figure 1. After a conversion is
initiated via the control section (described later) the clock
is enabled and the SAR is set to 1000 0000 0000. Once a
conversion is started it cannot be stopped or restarted.
The output buffers go into the Hi-Z state. The SAR, driven
by the internal clock, will sequence through the conversion cycle and return a signal indicating end-of-conversion to the control section. The control section then

disables the clock, bring the Status output low, and
enables control functions to allow data read functions via
external command.
During a conversion, the internal 12-bit current-output
DAC is sequenced by the SAR starting with the most
significant bit (MSB) and ending with the least significant
bit (LSB). At the end of the process the DAC outputs a
current which accurately balances the input signal current
through the 5k (10k) input resistor. The comparator looks
at the summing node at every bit test. If the DAC current
sum is greater than the input current, the bit is turned off;

6-53

LT574A
OPERATion
if less, the bit is left on. After all 12 bits have been tested,
the SAR contains a 12-bit digital representation of the
analog input signal accurate to 12 bits ±0.5LSB. Two 5k
input scaling resistors allow either 10V or 20V span
operation. The 10k bipolar offset resistor is connected to
the 10V reference for bipolar operation, or grounded for
unipolar operation.
Interna11D.DDV Reference
An LT1 021-1 0 low noise, high stability, buried-zener reference is used inside the LT574A device and guarantees
superior stability over time and temperature. This reference provides improved performance over other 57Hype
references in both voltage range and output currentsourcing capability. The reference is trimmed to 1O.OOV ±2%.lt
can supply up to B.5mA to an external load in addition to
the current required by the reference input resistor (0.5mA)
and the bipolar offset resistor (1 mAl. This is an additional
7mA over most other 574A-type devices. (The external
load should not change during aconversion.) The LT574A
also has an improved Vee supply range; the Vee input can
range from 11.2Vto 22V.lfoperatingfrom±12V supplies,
improved driving capability eliminates the need for an
external buffer to source external loads at room temperature or over the specified temperature range.
Driving the LT574A Analog Inputs
The signal source driving the LT574A input looks into a5k
or 10k impedance. However, the current drawn out of the
input pins is abruptly modulated as the ADC steps through
the bit tests. Low source impedance at high frequency,
necessary to hold the input voltage constant through the
conversion cycle, is required for 12-bit accurate conversions. The output impedance of an op amp is equal to its
open-loop output impedance divided by the loop gain
available atthe frequency of interest. Acceptable loop gain
at 500kHz is needed for use with the LT57 4A. An op amp
can be checked for suitability by monitoring the LT574A's
input with an oscilloscope while aconversion is in progress.
Each of the 12 disturbances should settle in 1!lS or less.
Suitable op amps include the LT1 055 or LT1122.

6-54

Layout Precautions and Supply Decoupling
It is critically important the LT574A power supplies be well
regulated and free of high frequency noise. Noisy supplies
will cause unstable output codes. If switching power
supplies must be used, considerable care must be used to
ensure that switching spikes are eliminated. (For more
information on constructing switching power supplies
suitable for use with precision analog circuits, please see
Linear Technology's Application Note 29). Just a few
millivolts of high frequency noise on the power supply will
result in several counts of error.
Decoupling capacitors should be used on all power supply
pins. VLOGle decoupling should be connected directly
from pin 1to pin 15 (digital common) and Vee and VEE pins
should be decoupled directly to analog common (pin 9). A
4. 7~ tantalum unit in parallel with a 0.1 ~ ceramic type
makes a suitable decoupling capacitor.
The LT574A should be located as far as possible from
digital circuitry on the board layout. Coupling between
analog and digital lines should be minimized. If analog and
digital lines must cross, they should do so at right angles.
Parallel analog and digital lines should be separated by a
pattern connected to common. Wire-wrap construction is
not recommended; careful printed circuit layout is preferred instead.
Grounding Considerations
The analog common (pin 9) is the internal reference
ground and should be connected directly to the analog
reference point of the system. It is the "high quality"
ground point. Pin 9 should be connected to digital common (pin 15) at the package to achieve all the high
performance accuracy available from the LT574A in noisy
digital environments. This single-point grounding is the
preferred method for grounding mixed analog/digital systems. Be sure there are no digital ground returns on the
analog side of the line; input signal returns should be
isolated from digital ground and returned directly to the
Single-point ground at the LT574A package.

LT574A
)PERATlon
ange Connections
he LTS74A has four standard input ranges: OV to 10V,
Vto 20V, -SV to SV, and -10Vto 10V. To use the 10V
mge, connectthe input signal between pins 13 and 9. To
se the 20V range, connect the input signal between pins
4 and 9. In both cases, the other pin of the two is left
rlconnected. Full-scale and offset adjustments are shown
I Figure 3.lffull-scaletrim is not needed, connectaSOn,
%metal film resistor between pins 8 and 10. To extend
Ie 10V range to 10.24V (2.SmVlbit) with gain trim
otentiometer (R2) should be replaced by ason resistor
,d a 200n potentiometer should be placed in series
ith the 1OVIN pin. To obtain afull-scale range of 20.48V
imVlbit), a soon potentiometer should be used in
lries with pin 14. Gain trim is now implemented with
lese potentiometers.

nipolar Calibration
1e first transition of the LTS7 4A occurs at avalue O.SLSB
Jove analog common, so that the exact analog input for
given code will be halfway between the code transitions.

'-7lJ!J~

This O.SLSB offset is built into the LTS7 4A. The unit will
behave in this manner, within specifications, if pin 12 is
connected to analog common (pin 9). Referring to Figure
3, R1 performs the offset adjust function. It should be
adjusted so that the first transition falls at exactly O.SLSB
above the analog common potential (nominally ground).
The circuit, as shown, will give approximately ±1SmV of
offset trim range. The full-scale trim is calibrated by
applying a voltage 1.SLSB below full scale (9.9963V for
10Vfull scale) and adjusting R2 such that the unit outputs
thecodes4096and4097(111111111110and11111111
1111 ).

Bipolar Operation
Bipolar operation connections are shown in Figure 4. The
be replaced by son, 1% resistors
If offset and gain specifications are sufficient. To calibrate,
apply an input signal O.SLSB above negative full scale
(0000 0000 0000 to 0000 0000 0001), then apply asignal
1.SLSB below positive full scale (4.9963V for the ±SV
range) and adjust R2 so that the lasttransition (11111111
1110 to 1111 1111 1111) is output.
~rim potentiometers can

6-55

NOTES

6-56

INDEX
iECTJON 6-DATA CONVERSION
DlGITAL-TO-ANALOG CONVERTERS
LTC1451/LTC1452/LTC1453, 12-8it Rail-to-Rail Micropower DACs in SO-8 ...............................................
DlGITAL-TO-ANALOG CONVERTERS, ENHANCED AND SECOND SOURCE
LTC7541A, Improved Industry Standard CMOS 12-8it Multiplying DAC .....................................................
LTC7543/LTC8143, Improved Industry Standard Serial 12-8it Multiplying DACs ..........................................
LTC8043, Serial 12-8it Multiplying DAC in SO-8 .........•............•...................•.......•........••.••.......••••....

L7lJD~

6-58
6-69
6-73

6-80

6-57

-l=Ar\
L1n
£7 U
.

.'

LlCI4bl

\I(

LTC 1452/LTC 145~
I
TECHN'O 'OG~'v-----~
IT
12-Bit Rail-to-Rai
Micropower DACs in SO-E

FEATURES

DESCRIPTiOn

•
•
•
•
•
•

The LTC@1451/LTC14521LTC1453 are complete singll
supply. rail-to-rail voltage output 12-bit digital-to-analo(
converters (DACs) in an SO-8 package. They include ar
output buffer amplifier and an easy-to-use 3-win
cascadable serial interface.

•
•
•
•
•
•

12-Bit Resolution
Buffered True Rail-to-Rail Voltage Output
3V Operation (LTC1453). Icc: 2501lA Typ
5V Operation (LTC1451). Icc: 4001lA Typ
3V to 5V Operation (LTC1452). Icc: 2251lA Typ
Built-In Reference: 2.048V (LTC1451)
1.220V (LTC1453)
Multiplying Version (LTC1452)
Power-On Reset
80-8 Package
3-Wire Cascadable Serial Interface
Maximum DNL Error: O.5L8B
LowCost

The LTC1451 has an onboard reference of 2.048V and i
full-scale output of 4.095V. It operates from asingle 4.5\
to 5.5V supply.
The LTC1452 is a multiplying DAC with afull-scale outpu
of twice the reference input voltage. It operates from i
single supply of 2.7V to 5.5V.

APPLICATions

The LTC1453 has an onboard 1.22V reference and a full,
scale output of 2.5V. It operates from a single supply 0
2.7V to 5.5V.

•
•
•
•

The low power supply current makes the LTC1451 famill
ideal for battery-powered applications. The space savin(
8-pin SO package and operation with no external compo'
nents provide the smallest 12-bit DAC system available.

Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones

D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Differential Nonlinearity
vs Input Code

Daisy-Chained Control Outputs
0.5

IlP

CONTROL
OUTPUT 1

ttl

I

~

a:

a'!

a:

0.0

1

I

I

..1.1.1, "II,L ll"J,l, 1,1,,1.1 ",u,1. .lIl, j"" I,'~I',
'1"1111' T'"

,.".,,'

w

.J

Z
C

-0.5

o

512 1024 153620482560 3072 3584 4095

CODE
1451/2J3TA02

145112f3TA01

6-58

LTC 1451
LTC 1452/LTC 1453
IBSOLUTE mAXimum RATinGS
ree to GND .............................................. -O.5V to 7.5V
TL Input Voltage .................................... -O.5V to 7.5V
rOUT .............................................. -O.5V to Vee + O.5V
IEF ................................................ -O.5V to Vee + O.5V
naximum Junction Temperature ......... -65°C to 125°C

Operating Temperature Range
Commercial ........................................... O°C to 70°C
Industrial ......................................... -40°C to 85°C
Storage Temperature Range ....•........... -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

IACKAGE/ORDER InFORmATiOn
TOP VIEW

'~o'·
DIN 2

CS/LD 3

DOUT

4

7

S8 PART MARKING

ORDER PART NUMBER

VOUT

REF
5 GND
6

N8 PACKAGE
S8 PACKAGE
8·LEAD PDIP
8-LEAD PLASTIC SO
TJMAX =125'C, 6JA =100'CIW (N8)
TJMAX =125'C, 6JA =150'CIW (S8)

LTC1451CN8
LTC1452CN8
LTC1453CN8
LTC14511N8
LTC14521N8
LTC14531N8

1451C
14511
1452C
14521
1453C
14531

LTC1451CS8
LTC1452CS8
LTC1453CS8
LTC14511S8
LTC14521S8
LTC14531S8

lnsult factory for Military grade parts.

:LEORICAL CHARACTERISTICS
cc =4.5V to 5.5V (LTC1451), 2.7V to 5.5V (LTC1452/LTC1453), internal or external reference (VREF:<::; Vcc/2), VOUT and REF
~Ioaded, TA = TMIN to TMAX, unless otherwise noted.
tMBOL

I PARAMETER

I CONDITIONS

MIN

TYP

MAX

UNITS

±0.5
±3.5
±4
±12
±18

Bits
LSB
LSB
LSB
mV
mV
IJ.V/oC

~C

IL

Resolution
Differential Nonlinearity
Integral Nonlinearity

)S

Offset Error

)STe

Offset Error Temperature
Coefficient
Full-Scale Voltage

~L

'S

'sTe

Full-Scale Voltage
Temperature Coefficient

L7lJ!J~

Guaranteed Monotonic (Note 1)
TA =25°C
(Note 1)
TA =25°C

When Using Internal Reference, LTC1451, TA =25°C
LTC1451
External2.048V Reference, Vee =5V, LTC1452
When Using Internal Reference, LTC1453, TA =25°C
LTC1453
When Using Internal Reference, LTC1451
When Using External 2.048V Reference, LTC1452
When Using Internal Reference, LTC1453

•
•

12

•
•
•
•
•

±15
4.065
4.045
4.075
2.470
2.460

4.095
4.095
4.095
2.500
2.500
±0.10
±0.02
±0.10

4.125
4.145
4.115
2.530
2.540

V
V
V
V
V
LSB/oe
LSB/oe
LSB/oC

6-59

LlCI4bl

LTC 1452/LTC1453
ELEORICAL CHARAOERISTICS
Vee =4.5V to 5.5V (LTC1451),2.7V to 5.5V (LTC1452/LTC1453), internal or external reference (VREF ~ Vee/2), VOUT and REF
unloaded, TA =TMIN to TMAX, unless otherwise noted.
SYMBOL

I

PARAMETER

Reference (LTC1451/LTC1453)
Reference Output Voltage
Reference Output
Temperature Coefficient
Reference Line Regulation
Reference Load Regulation

CONDITIONS

••

LTC1451
LTC1453

o::; lOUT::; 1001lA, LTC1451
LTC1453

Reference Input Range
Reference Input Resistance
Reference Input Capacitance
Short-Circuit Current
Power Supply

VREF::; Vee -1.5V

REF Shorted to GND

Vee

Positive Supply Voltage

For Specified Performance, LTC1451
LTC1452
LTC1453

lee

Supply Current

4.5V::; Vee::; 5.5V (Note 4), LTC1451
2.7V::; Vee::; 5.5V (Note 4), LTC1452
2.7V::; Vee::; 5.5V (Note 4), LTC1453

Op Amp DC Performance
Short-Circuit Current Low
Short-Circuit Current High
Output Impedance to GND
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time

Vour Shorted to GND
Vour Shorted to Vee
Input Code = 0
(Note 2)
(Notes 2, 3) to ±0.5LSB

Digital Feedthrough
SINAD

6-60

AC Feedthrough

REF = 1kHz, 2Vp.p, LTC1452

Signal-to-Noise + Distortion

REF = 1kHz, 2Vp_p, (Code: A1I1s) LTC1452

•
••
•
•
•
••
•
••
•
•
•
•
•

MIN

TYP

MAX

UNm

2.008
1.195

2.048
1.220
±O.OB

2.088
1.245

\
\
LSB/O(

0.7
0.2
0.6

±2
±1.5
±3

LSB/\
LSE
LSE
\

8

14
15

4.5
2.7
2.7
300
120
150

400
225
250

Vee/2
30

pi
BO

m~

5.5
5.5
5.5

\
\
\

620
350
500

~
~
~

100

mt
mt
r.

120
40
0.5

1.0

kf.

120

VI~

14

~

0.3

nVO!

-95

dE

B5

dE

LTC 1451
LTC 1452/LTC 1453
ELECTRICAL CHARACTERISTICS
Icc =5V (LTC1451LTC1452). Vcc =3V (LTC1453). TA =TMIN to TMAX
;YMBOL

PARAMETER

CONDITIONS

LTC1451/LTC1452
MIN
TYP
MAX

MIN

2.4

2.0

LTC1453
TYP

MAX

UNITS

ligilall/O
IIH

Digital Input High Voltage

III

Digital Input low Voltage

10H

Digital Output High Voltage

lOUT ~ -1mA

IOl

Digital Output Low Voltage

IOUT~

lEAK

Digital Input leakage

;IN

Digital Input Capacitance

V ~ GND to Vcc
Guaranteed by Design
Not Subject to Test

•
•
•
•
•
•

1mA

V
0.6

V

Vcc - 0.7

V

0.8
Vcc- 1.O
0.4

0.4

V

±10

±10

10

10

~
pF

40

60

ns

0

0

ns

40

60

ns

40
50

60
80

ns

40

60

ns

20

30

ns

150

220

ns

20

30

ns

;wilching
1

DIN Valid to ClK Setup

2

DIN Valid to ClK Hold

3

ClK High Time

4

ClK low Time

5

CS/LD Pu Ise Width

6

lSB ClK to CS/lD

7

CS/lD low to ClK

8

DOUT Output Delay

9

ClK Low to CS/lD low

•
•
•
•
•
•
•
•
•

CLOAD ~ 15pF

ns

Nole 2: load is 5kn in parallel with 100pF.
Nole 3: DAC switched between all1s and the code corresponding to Vas
for the part, i.e., lTC1451: code 18; LTC1453: code 30.
Nole 4: Digital inputs at OV or Vec.

'he • denotes specifications which apply over the full operating
emperature range.
lole 1: Nonlinearity is defined from the first code that is greater than or
qual to the maximum offset specification to code 4095 (full scale).

rYPICAL PERFORmAnCE CHARACTERISTICS
LTC1451 Minimum Supply
Voltage vs Load Current
5.4

LTC1451
Supply Current vs Temperature

LTC1453 Minimum Supply
Voltage vs Load Current

L1VO~T< 1lds

4.50

I

, 5.2

4.25

450

f--L1VO~T< 1lds

I

'"~ 3:75

5.0

~
::; 3.50

4.8

440

I
II
II

:>

;;; 4.00

430

1 420 I"'-

~ 410
a::
I" .....
§ 400
I"
u

0..

4.6
4.4

/
.....

4.2
4.0
0.0001 0.001

0.01

0.1

1

lOAD CURRENT (rnA)

!5
en

/

3.25

I

~ 3.00

:;;

Z 2.75

/
.."

:E

2.50
10

100

2.25
0.0001 0.001

0.D1

0.1

1

lOAD CURRENT (rnA)

L--"

::; 390
0..

!5
en

J

"-""

Vee = 5.5V

-,-

--L

"

Vee =4.5V

V ",""
L--"
Vee = 5V

380
370
360

10

100

350
-55

-25

5

35

65

95

125

TEMPERATURE (OC)
1451/213G03

L7lJ!J~

6-61

•

LTC 1451
LTC 1452/LTC1453
TYPICAL PERFORmAnCE CHARACTERISTICS
LTC1451
Supply Current vs Logic Input
Voltage
1.15

4.5
ALL DIGITAL INPUTS
TIED TOGETHER

1.05

4.0

~

~

u

~ 0.65
en 0.55

0.45

§ 2.5
en
>:::> 2.0
0>:::> 1.5
0

\

II

0-

:::>

0.35

II

co
z

0.75

\.

55°C= ~

~/

\

/

0.5

ZERO SCALE

~EDlOVepl

o

o 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC INPUT VOLTAGE (V)

25°C-

///1

Vee = 5V

1.0

"-I........ .........

.J

125°C//j

RLTlETml

~ 3.0

0.85

1000

11111
III
FULL SCALE

I

3.5

<,0.95

S
!z

LTC1451
Pull-Down Voltage vs Output Sink
Current Capability

LTC1451
Output Swing vs Load Resistance

10

100
1k
LOAD RESISTANCE (n)

0.1
0.0001 0.001 0.01
0.1
10
OUTPUT SINK CURRENT (rnA)

10k

145112/3604

LTC1451
Offset Voltage vs Temperature

LTC1451
Integral Nonlinearity (INL)

LTC1451
Differential Nonlinearity (DNL)
0.5

900

2.0
1.6

800
~
w

1.2

V

:;;-

a;:

700

tt 500
o

400

~
a:
:;E' 0.0

/

~
':; 600
~
i;:;

/

V
V

300
-55

-25

V

V

ffi

0.8

II

II

1.,1,,1.. 1. 1,.1

I

1 ,I

I

1

,J, .1,.1.1, . 1.. 1.1. LI ,1,1. HI, J"" .,.,~"

","''''

ffi
--'

0.4

;:;

0

J\

-0.5
125

o

512 1024 1536 2048 2560 3072 3584 4095
CODE

LTC1452
Total Harmonic Distortion + Noise
vs Frequency

z

-50

-2.0

o

1451fl13G09

LTC1451
Broadband Output Noise

l'U~e =15J

'I
VIN = 2Vp.p
VOUT" 4Vp.p

/

+

~ -60

~

0.2LSB/DIV

!jl-70
is
u

~ -80
::;;

~

-90

g
:I:

>--100
50 100

1k
10k
FREQUENCY (Hz)

100k

5mS/DIV
CODE = FFFH
BW = 3Hz TO 1.4MHz
GAIN = 1000
14511213610

1451/213G06

6-62

,

512 1024 15362048 2560307235844095
CODE

145112J3TA02

1451/213G/Jl

~

"'!i

Vee = 5V
INTERNAL REFERENCE
TA = 25°C

-1.6

_-40

''''Il\..

\1f

-1.2

'"~

,lI,

-0.8

""
95

r

'\d
f11 IJU 1"1j Ilf
IT
If

~-O.4

--'
z
<:>

5
35
65
TEMPERATURE (OC)

100

14511213 GOO

LTC 1451
LTC 1452/LTC 1453
Pin FunCTions
CLK: The TIL level Input for the Serial Interface Clock.
DIN: The TIL Levellnputforthe Serial Interface Data. Data
on the DIN pin is latched into the shift register on the rising
edge of the serial clock.

CS/LD: The TIL levellnputforthe Serial Interface Enable
and Load Control. When CS/lD is low the ClK signal is
enabled, so the data can be clocked in. When CS/lD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.

GND: Ground.
REF: The Output of the Internal Reference and the Input
to the DAC Resistor Ladder. An external reference with
voltage up to Vee/2 may be used for the lTC1452.
VOUT: The Buffered DAC Output.

Vee: The Positive Supply Input. 4.5V ::; Vee::; 5.5V
(lTC1451), 2.7::; Vee::; 5.5V (lTC1452/lTC1453). Requires a bypass capacitor to ground.

DOUT: The Output of the Shift Register which Becomes
Valid on the Rising Edge of the Serial Clock.

BLOCK DIAGRAm
----III Vee

pGND

TiminG DIAGRAm
ClK

D,N

CS/lD

Dour

B11
CURRENT WORD

6-63

LTC 1451
LTC 1452/LTC 1453
DEFiniTions
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2n) that divide the full-scale range. The resolution
does not imply linearity.
Full-Scale Voltage (VFS): This is the output of the DAC
when all bits are set to 1.
Voltage Onset Error (Vas): The theoretical voltage at the
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from asingle supply, the output cannot go
below zero. If the offset is negative, the output will remain
near OV resulting in the transfer curve shown in Figure 1.

The offset of the part is measured at the code that corresponds to the maximum offset specification:
Vos = VOUT - [(Code x VFs)/(2n - 1)1

Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the
end-pOints of the DAC transfer curve. Because the part
operates from a Single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated
as follows:

INL = [VOUT - Vos - (VFS - Vos)(code/4095)]/LSB
VOUT = The output voltage of the DAC measured at
the given input code
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:

DNL

Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.

LSB =(VFS - Vos)/(2n -1) =(VFS - Vos)/4095
Nominal LSBs:
LTC1451
LTC1452
LTC1453

LSB = 4.095v/4095 = 1mV
LSB = V(REF)/4095
LSB =2.5V/4095 =0.610mV

= (~VOUT - LSB)/LSB

~VOUT =

The measured voltage difference between
two adjacent codes

Digital Feedthrough: The glitch that appears atthe analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV x sec.

OUTPUT
VOLTAGE

r

NEGATIVE Ov
OFFSET 1

'

..'

DAC CODE
14511213 Fa1

Figure 1. Effect of Negative Offset

6-64

.L7lJ!J~

LTC 1451
LTC 1452/LTC 1453
OPERATion
Serial Interface

Reference

The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/lD is pulled high. The ClK is disabled internally when
CS/lD is high. Note: ClK must be low before CS/lD is
pulled low to avoid an extra internal clock pulse.

The lTC1451 includes an internal2.048V reference, making 1lSB equal to 1mV (gain of 2). The lTC1453 has an
internal reference of 1.22V with afull scale of 2.5V (gain of
2.05). The internal reference output is turned off when the
pin is forced above the reference voltage, allowing an
external reference to be connected to the reference pin.
The lTC1452 has no internal reference and the REF pin
must be driven externally. The buffer gain is 2, so the
external reference must be less than Vcc/2 and be capable
of driving the 8k minimum DAC resistor ladder.

The buffered output of the 12-bit shift register is available
on the DOUT pin which swings from GND to Vcc.
Multiple lTC1451/lTC1452/lTC1453s may be daisychained together by connecting the DOUT pin to the DIN
pin of the next chip, while the ClK and CS/lD signals
remain common to all chips in the daisy chain. The serial
data is clocked to all of the chips, then the CS/lD signal is
pulled high to update all of them simultaneously.

Voltage Output
The l TC1451 family's rail-to-rail buffered output can
source or sink 5mA over the entire operating temperature
range while pulling to within 300mVof the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 400 when driving aload to
the rails. The output can drive 1OOOpF without going into
oscillation.

6-65

Lie 14bl
LTC 1452/LTC 1453
TYPICAl·APPLICATlons
An Isolated 4mA to 20mA Process Controller
Has 3.3V Minimum Loop Voltage
.----------------------------.-~~IlJl~030v

Rs

100

-

L...------.......-IOUT
3.3V
OPTO-ISOLATORS

10k

elK
DIN

elK

(;S/lD

DIN

(;S/lD

This circuit shows how to use an LTC1453 to make an
opto-isolated digitally controlled 4mA to 20mA process
controller. The controller circuitry, including the optoisolation, is powered by the loop voltage that can have a
wide range of 3.3V to 30V. The 1.22V reference output of
the LTC1453 is used for the 4mA offset current and VOUT

6-66

is used for the digitally controlled OmA to 16mA current.
Rs is a sense resistor and the op amp modulates the
transistor Q1 to provide the 4mA to 20mA currentthrough
this resistor. The potentiometers allow for offset and fullscale adjustment. The control circuitry dissipates well
under the 4mA budget at zero-scale.

LTC 1451
LTC 1452/LTC 1453
TYPICAL APPLICATions
12-Bit 3V to 5V Voltage Output OAC

LTC1451: 4.5V TO 5.5V
LTC1452: 2.7V TO 5.5V
LTC1453: 2.7V TO 5.5V

I1 P

OUTPUT
LTC1451: OV TO 4.095V
LTC1452: OV TO 2 0 REF
LTC1453: OV TO 2.5V

LTC1451: 2.048V
LTC1452: EXTERNAL
LTC1453: 1.22V

Digitally Programmable Current Source

•

5V
Vs + 5VTO 100V
FOR RL,;50n
OIN 0 4.095
IouI' 4096 0 RA = OmA TO 10mA

This circuit shows adigitally programmable current source
from an external voltage source using an external op amp,
an LT1077 and an NPN transistor (2N3440). Any digital
word from 0 to 4095 is loaded into the LTC1451 and its
output correspondingly swings from OV to 4.095V. In the
configuration shown, this voltage will be forced across the

resistor RA. If RA is chosen to be 41 on the output current
will range from OmA at zero-scale to 10mA at full-scale.
The minimum voltage for Vs is determined by the load
resistor RL and Q1's VCESAT voltage. With a load resistor
of 50n, the voltage source can be as low as 5V.

6-67

LTC 1451
LTC 1452/LTC 1453
TYPICAL APPLICATions
A Wide Swing, Bipolar Output 12-Bit DAC
5V

·4.095 -4 096V
VOUT·. 2· DIN
4096
.

R3
10k

-5V

R4
20k

.........JIIwl'y----6-----'IIYv-' 14511213TA06

This circuit shows how to make a bipolar output 12-bit
DAC with a wide output swing using an LTC1451 and an
LT®1 077. R1 and R2 resistively divide down the LTC1451
output and an offset is summed in using the LTC1451
onboard 2.048V reference and R3 and R4. R5 ensures that

the onboard reference is always sourcing current and
never has to sink any current even when VOUT is at fullscale. The LT1 077 output will have a wide bipolar output
swing of-4.096V to 4.094V as shown in the figure above.
With this output swing 1LSB = 2mV.

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC1257

Single 12-Bit VOUT DAC, Full Scale:2.048V,
Vee: 4.75V to 15.75V. Reference Can Be Overdriven Up
to 12V, i.e., FS MAX = 12V

5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package

LTC7541
12-Bit Multiplying Parallel lOUT DAC
LTC7543/L TC8143 12-Bit Multiplying Serial louT DAC

5V Supply, Clear Pin and Serial Data Output (LTC8143)

LTC8043

5V Supply, SO-8 Package

6-68

12-Bit Multiplying Serial lOUT DAC

5V to 16V Supply, 12-Bit Wide Interface

~7lJ!J~

'''''''-Llnt1\~D

~,

TECHNOLOGY

___

L_TC75_41A
Improved
Industry Standard CMOS
12-Bit Multiplying DAC

FEATURES

DESCRIPTiOn

• Improved Direct Replacement for AD7541A
and AD7541
• 4-Quadrant Multiplication
• 12-Bit End-Point Linearity: ±O.5LSB DNL and INL
Over Temperature
• All Grades Guaranteed Monotonic
• Maximum Gain Error: ±1 LSB
• Single 5V to 15V Supply
• TTL and CMOS Logic Compatible
• Reduced Sensitivity to Op Amp Offset
• Low Power Consumption
• Virtually Latch-Up Proof
• Low Cost

The LTC@7541Aisa 12-bit resolution multiplying digitalto-analog converter (DAC).

APPLICATions
•
•
•
•
•

Motion Control Systems
Microprocessor-Controlled Calibration
Automatic Test Equipment
Programmable Gain Amplifiers
Digitally Controlled Filters

Laser-trimmed thin-film resistors provide excellent absolute accuracy. Precision matched resistors and CMOS
circuitry result in remarkable stability with temperature
and supply variations.
The LTC7541A is a superior pin compatible replacement
for the industry standard AD7541A1AD7541. Improvements include better typical accuracy and stability and
reduced sensitivity to output amplifier offset. The LTC7541A
is also very resistant to latch-up.
In addition to 2-quadrant and 4-quadrant multiplying
configurations, the LTC7541A performs well in digitally
programmable gain and non inverting voltage output applications. Low cost, improved performance and versatility make the LTC7541 A the best choice for many new
designs and for upgrading existing systems. Parts are •
available in 18-pin PDIP and 18-pin SO Wide packages.
CT, LTC and LT are registered trademarks of Linear Technology Corporation.

rYPICAl APPLICATiOn
2-Quadranl Multiplying DAC Has Less Than
O.5LSB (Typ) Total Unadjusted Error

Inlegral Nonlinearity Over Temperature
1.0
CD

'"'""
~

0.5

i==

;;S
Your

'"~
o
z

f---

0

TA~~ TA = 25°C

Z-t- -r

¥

""I
TA =-40°C

~
gl-0.5
~

DIGITAL INPUTS

-

-1.0

o

512 1024 1536 2048 2560 3072 3584 4095
DIGITAL INPUT CODE
7541ATA02

6-69

LTC7541A
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

Voo to GND ............................................... -O.5V to 17V
VREF to GND .................... :.•.... :...................,........... ±25V
RFB to GND ........................................................... ±25V
Digital Inputs to GND .................. -O.5V to (Voo + O.5V)
OUT 1, OUT 2 to GND .................. ":'O.5V to (Voo + O.5V)
Power Dissipation .................. ;.......................... 450mW
(Derate 6mW/oC Above 75°C)
Maximum JU,nction Temperature ......... -65°C to 125°C
Operating Temperature Range
Commercial (J, K Versions) .................. O°C to 70°C
lridustrial (B Version) ...................... -40°C to 85°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

TOP VIEW

ORDER PART
NUMBER

OUT2
GND
BIT1 (MSB)
BIT2

LTC7541ABN
LTC7541ABSW
LTC7541AJN
LTC7541AKN
LTC7541 AJSW
LTC7541AKSW

NPACKAGE
SW PACKAGE
18-LEAD PDIP 18-LEAD PLASTIC SO WIDE
TJMAX =150'C, 9JA =100'C/W (N)
TJMAX =150'C, 9JA =130'C/W (SW)
Consult factory for Military grade parts:

ELEORICAL CHARAOERISTICS
VDD =15V, VREF = 10V, OUT 1 = OUT 2 = GND = OV, TA =TMIN to TMAX, unless otherwise specified.
SYMBOL PARAMETER

CONDITIONS

MIN

LTC7541AJ
TYP
MAX

LTC7541AKJLTC7541AB
MIN
TYP
MAX

UNIT5

Accuracy

DNL
GE

Resolution
Integral Nonlinearity
(Relative Accuracy)
Differential Nonlinearity
Gain Error

ILKG

Gain Temperature Coefficient
Output Leakage Current

INL

PSRR
Power Supply Rejection
Reference Input
VREF Input Resistance
RREF
VREF Input Resistance
Temperature Coefficient

6-70

(Note 1)
Guaranteed Monotonic, TMIN to TMAX
(Note 2)
TA =25°C
TMIN to TMAX
(Note 3)
(Note 4)
TA =25°C
TMIN to TMAX
Voo =15V±5%

•

12

12

Bit!
LSE

•

±1

±O.5

•
•
•
•
•
•

±1
±6
±S
5
±S
±10
±0,002

±O.S
±1
±2
5
±5
±10
±0.002

LSE
LSE
LSE
ppm/O(

15

kr.
ppm/O(

1

7

11
-100

15

1

7

11
-100

n~
n~

%/%

LTC7541A
ElEORICAl CHARACTERISTICS
Voo =15V, VREF =1OV, OUT 1 =OUT 2 =GND =OV, TA=TMIN to TMAX, unless otherwise specified.
SYMBOL PARAMETER

CONDITIONS

Power Supply
Operating Supply Range
Voo
Suppy Current
100

MIN

•
••
•
•
•

Digital Inputs = VIH or VIL
Digital Inputs = OV or Voo

Oigilallnpuls
Digital Input High Voltage
VIH
Digital Input low Voltage
VIL
Digital Input Current
liN
Digital Input Capacitance
CIN
AC Performance
Propagation Delay
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Current Settling Time
Output Capacitance (Note 3)
COUT

5

All GRADES
TYP
MAX
15

16
2
100

(Notes 5, 6)
(Notes 5, 7)
VREF = ±10V, 10kHz Sinewave
(Note 5), To 0.01 % for FUll-Scale Change
Digital Inputs = VIH
COUT1
COUT2
Digital Inputs = VIL
COUT1
COUT2

V
mA

!!A

2.4
0.8
±1
8

0.001

•

(Note 3), VIN = OV

UNIT

100
1000
1.0
0.6

V
V

!!A
pF
ns
nV-sec
mVp•p

•
•
•
•

200
70
70
200

flS
pF
pF
pF
pF

Nole 5: OUT 1 load = 100n in parallel with 13pF.
Nole 6: Measured from digital input change to 90% of final analog value.
Digital inputs = OV to Voo or Voo to OV.
Nole 7: VREF = OV. All digital inputs OV to Voo or Voo to OV. Measured
using LT1363 as output amplifier.

The. denotes specifications which apply over the full operating
temperature range.
Note 1: ±0.5LSB = ±0.012% of full scale.
Nole 2: Using internal feedback resistor.
Nole 3: Guaranteed by design, not subject to test.
Nole 4: 10UT1 with all digital inputs = OV or IOUT2 with all digital
inputs = Voo.

BLOCK DIAGRAm

.. ~~
20k

y

~y 1
I

vooD--

GNO

-

RFB

OUT 1
OUT 2

r-'----''---......,

BIT1
(MSB)

BIT2

BIT 3

BIT4

BIT12
(LSB)

6-71

6

LTC7541A
TYPICAL APPLICATions
Unipolar Operation (2-0uadrant Multiplication)

Table 1. Unipolar Binary Code Table
ANALOG OUTPUT
VOUT

DIGITAL INPUTS

OIGITAL INPUT
MSB
LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000

VOUT

-VREF (4095/4096)
-VREF (2048/4096) = -VREF/2
-VREF (114096)
OV

-

Bipolar Operation (4-0uadrant Multiplication)
R2
R3
20k
20k
-10 TOVroE,j - - - -.......------------'\ofll'v-o..--w".-----,

VOUT

DIGITAL INPUTS

':"

Table 2. Bipolar Offset Binary Code Table
ANALOG OUTPUT
OIGITAL INPUT
MSB
LSB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000

VOUT

VREF (2047/2048)
VREF (1/2048)
OV
-VREF (1/2048)
-VREF

RELATED PARTS
PART NUMBER

DESCRIPTION

LTC1257

Complete Serial 1/0 VOUT 12-Bit DAC

5V to 15V Single Supply in 8-Pin SO and PDIP

LTC1451/LTC1452/LTC1453

Complete Serial 1/0 VOUT 12-Bit DACs

3V/5V Single Supply in 8-Pin SO and PDIP

LTC7543/LTC8143

Serial 1/0 Muliplying 12-Bit DACs

Clear Pin, Serial Data Output (LTC8143)

LTC8043

Serial Mulitplying 12-Bit DAC

8-Pin SO and PDIP

6-72

COMMENTS

f""'-Llnt:J\~D~___LTC_7_54_3/L_TC_81_43

~,

TECHNOLOGY Improved Industry Standard
Serial 12-Bit Multiplying DACs

FEATURES

DESCRIPTiOn

• Improved Direct Replacement for AD7543
and DAC-8143
• Low Cost
• DNL and INL Over Temperature: ±O.5LSB
• Easy, Fast and Flexible Serial Interface
• Daisy-Chain 3-Wire Interface for Multiple DAC
Systems (LTC8143)
• 1LSB Maximum Gain Error Over Temperature
Eliminates Adjustment
• Asynchronous Clear Input for Initialization
• Four-Quadrant Multiplication
• Low Power Consumption
• 16-Pin PDIP and SO Packages

The LTC@7543/LTC8143 are serial-input 12-bit multiplying digital-to-analog converters (DACs). They are superior
pin compatible replacements for the AD7543 and
DAC-8143.lmprovements include better accuracy, better
stability over temperature and supply variations, lower
sensitivity to output amplifier offset, tighter timing specifications and lower output capacitance.
An easy-to-use serial interface includes an asynchronous
CLEAR inputforsystems requiring initialization to aknown
state. The LTC8143 has aserial data output to allow daisychaining multiple DACs on a 3-wire interface bus.
These DACs are extremely versatile. They can be used for
2-quadrant and 4-quadrant multiplying, programmable
gain and single supply applications, such as non inverting
voltage output and biased or offset ground mode.

APPLICATions
•
•
•
•
•

Process Control and Industrial Automation
Remote Microprocessor-Controlled Systems
Digitally Controlled Filters and Power Supplies
Programmable Gain Amplifiers
Automatic Test Equipment

Parts are available in 16-pin PDIP and SO packages and
are specified over the extended industrial temperature range, -40°C to 85°C.
~
£T, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Multiplying OAC Has Easy 3-Wire Serial Interface

Integral Nonlinearity Over Temperature
1.0

VIN---'"

iii"
VJ
:. 0.5

CLOCK
DATA
LOAD

~
VOUT

-

~

:z

~
o
z

0

r-TA-85°C_ TA = 25°C r--r--

f-i:::-'-......:i

"K

~

TA- 40°C f - f -

~

ffi-0.5

~

-1.0

o

512 1024153620482560 3072 35844095
DIGITAL INPUT CODE
7S43/8143TA02

6-73

LTC7543/LTC8143
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

Vooto AGND ............................... ,.............. -O.5V to 7V
Voo to DGND .............................................. -O.5V to 7V
AGND to DGND ............................................ Voo + O.5V
DGND to AGND ............................................ Voo + O.5V
Digital Inputs to DGND ............... -O.5V to (Voo + O.5V)
VOUT1, VOUT2 to AGND ................. -O.5Vto (Voo + O.5V)
VREF to AGND, DGND ............................................ ±25V
VRFB to AGND, DGND ........................................... ±25V
Maximum Junction Temperature .......................... 150°C
Operating Temperature Range ............... -40°C to 85°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

TOP VIEW
OUTl

1

STBl

4

LDl

5

ORDER PART
NUMBER
LTC7543GKN
LTC7543KN
LTC7543GKSW
LTC7543KSW
LTC8143EN
LTC8143FN
LTC8143ESW
LTC8143FSW

NC (LTC7543)
SRO (LTC8143) 6
SRI 7
N PACKAGE
16-LEAD PDIP
SW PACKAGE
16-LEAD PLASTIC SO WIDE
TJMAX =150'C, 6JA =100'C/W (N)
TJMAX =150'C. 6JA =130'C/W (SW)

Consult factory for Military grade parts.

ACCURACY CHARACTERISTICS - LTC7543
VDD = 5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND =OV, TA = TMIN to TMAX, unless otherwise specified.
SYMBOL PARAMETER
Resolution
Integral Nonlinearity
INL
(Relative Accuracy)
ONL
Differential Nonlinearity
GE
Gain Error

ILKG

Gain Temperature Coefficient
(AGain/ATemp)
Output Leakage Current

CONOITIONS
(Note 1)
Guaranteed Monotonic, TMIN to TMAX
(Note 2)
TF 25°C
TMIN to TMAX
(Note 3)
(Note 4)

Zero-Scale Error
PSRR

6-74

Power Supply Rejection Ratio VDD= 5V±5%

TA = 25°C
TMIN to TMAX
TA = 25°C
TMIN to TMAX

•
•
•
•
•

•
•

•

MIN
12

LTC7543GK
TYP
MAX

1

LTC7543K
TYP
MAX

±O.5

±O.5·

UNITS
Bits
LSB

±O.5
±1
±1
5

±O.5
±2
±2
5

LSB
LSB
LSB
ppm/oC

±1
±10
±O.OO6
±O.O6
±O.0001 ±O.OO2

MIN
12

1

±1
±10
±O.OO6
±O.O6
±O.OOOl ±O.OO2

nA
nA
LSB
LSB
%/%

LTC7543/LTC8143

ACCURACY CHARACTERISTICS - lTC8143
SYMBOL PARAMETER
Resolution
Integral Nonlinearity
INL
(Relative Accuracy)
DNL
Differential Nonlinearity
Gain Error
GE
Gain Temperature Coefficient

CONDITIONS
(Note 1)
Guaranteed Monotonic, TMIN to TMAX
(Note 2)
TA = 25°C
TMIN to TMAX
(Note 3)

(~Gain/~Temp)

ILKG

Output Leakage Current

(Note 4)

TA = 25°C
TMIN to TMAX
TF 25°C
TMIN to TMAX

Zero-Scale Error
PSRR

Power Supply Rejection Ratio Voo = 5V±5%

•
•
•
•
•

MIN
12

•
•

•

LTC8143E
TYP
MAX

MIN
12

LTC8143F
TYP
MAX
±1

UNITS
Bits
LSB

±0.5

±1

LSB

±1
±2

±2
±2

LSB
LSB
ppm/oC

±0.5

1

1

5

5

±5
±25

±5
±25

nA
nA

±0.03
±0.15

±0.03
±0.15

LSB
LSB

±0.0001 ±0.002

±0.0001 ±0.002

%/%

ELECTRICAL CHARACTERISTICS - lTC7543/lTC8143

VDD =5V, VREF =10V, VDUT1 =VDUT2 =AGND =DGND =OV, TA =TMIN to TMAX, unless otherwise specified.

SYMBOL PARAMETER

LTC7543/LTC8143
ALL GRADES
MIN
TYP
MAX

CONDITIONS

UNITS

Reference Input

~RR~EF~~ILv~RE~FI~np~u~tR~e~Sis~ffi~n~ce__________~I~(~NO~te~5~)____________________~IL.~IL-~8____1~1__~15__~__~kn ~
AC Performance (Note 3)
Output Current Settling Time
Multiplying Feedthrough Error
Digital-to-Analog Glitch Energy
THO
Total Harmonic Distortion
Output Noise Voltage Density
Analog Outputs (Note 3)
Output Capacitance
COUT

Digital Inputs
Digital Input High Voltage
Digital Input Low Voltage
VIL
Digital Input Current
liN
Digital Input Capacitance
CIN
Digital Outputs: SRO (LTC8143 Only)
Digital Output High
VOH
Digital Output Low
VOL

~

(Notes 6, 7)
VREF =±10V, 10kHz Sinewave
(Notes 6, 8)
(Note 9)
(Note 10)
DAC Register Loaded to All 1s

COUT1
COUT2

DAC Register Loaded to All Os

COUT1
COUT2

VIH

L7lJ[f~

VIN = OV to Voo
(Note 3), VIN = OV

•
•
•
•
•
••

0.25

IJS

0.8

2

mVp_p

2

20

nV-sec

-108

-92

dB
nV/.yHz

13

••
•
•
•
•

1

60
20

90
60

30
50

60
90

0.001

0.8
±1
8

!IA

0.4

V

2.4

4

pF
pF
pF
pF
V
V
pF
V

6-75

LTC7543/LTC8143

ELECTRICAL CHARACTERISTICS -

lTC7543/LTC8143

Voo = 5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND = OV, TA =JMIN to TMAX, unless otherwise specified.

SYMBOL

PARAMETER

l TC7543/LTC8143
.ALL GRADES
MIN
TYP
MAX

CONDITIONS

UNITS

Timing Characteristics (Note 3)
tpS1
tpS2

Serial Input to Strobe Setup Time
(IsTB = 80ns)

STBl Used as the Strobe
STB2 Used as the Strobe

tpS3

STB3 Used as the Strobe

tpS4

STB4 Used as the Strobe

tpH1
tpH2

Serial Input to Strobe Hold Time
(IsTB = 80ns)

STB1 Used as the Strobe
STB2 Used as the Strobe

tpH3

STB3 Used as the Strobe

tpH4

STB4 Used as the Strobe

tSRI

Serial Input Data Pulse Width

IsTB1, tSTB2, Strobe Pulse Width
tSTB3, tSTB4
IsTB1, tSTB2, Strobe Pulse Width
tSTB3, tSTB4
Load Pulse Width
tlP1, It.P2
tASB

(Note 11)
(Note 12)

LSB Strobed into Input Register
to Load DAC Register Time

Clear Pulse Width
telR
SRO Timing Characteristics (LTC8143 Only)
tpp

STB2, STB3, STB4 Strobe to SRO
Propagation Delay

STBl to SRO Propagation Delay
tpP1
Power Supply
Vpp

Supply Voltage

Ipp

Supply Current

Cl = 50pF
Cl = 50pF

Digital Inputs = OV or Vpp
Digital Inputs = VIH or Vil

The. denotes specifications which app:y over the full operating
temperature range.
Nole 1: ±0.5LSB = ±0.012% of full scale.
Nole 2: Using internal feedback resistor.
Nole 3: Guaranleed by design, not subject to test.
Nole 4: IOUT1 with DAC register loaded with all Os or IOUT2 with DAC
register loaded with all 1s.
Nole 5: Typical temperature coefficient is 100ppm/oC.
Nole 6: OUT 1 load = 100n in parallel with 13pF.
Nole 7: To 0.Q1 % for a full-scale change, measured from falling edge of
LDl or LD2.

6-76

•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
••

50

5

ns

20

-5

ns

0

-30

ns

0

-30

ns

30

10

ns

50

25

ns

80

55

ns

80

55

ns

80

ns

80

ns

80

ns

140

ns

0

ns

80

ns

220

120

ns

150

80

ns

4.75

5

5.25

V

0.1
2

mA
mA

Nole 8: VREF = OV. DAC register contents changed from all Os to all 1s or
from all 1s to all Os.
Nole 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s.
Nole 10: Calculation from en = ~4KTRB where: K = Boltzmann constant
(J/KO); R= resistance (n); T = resistor temperature (OK); B= bandwidth
(Hz).
Nole 11: Minimum high time for STBl , STB2, STB4. Minimum low time
for STB3.
Nole 12. Minimum low time for STB1, STB2, STB4. Minimum high time
for STB3.

LTC7543/LTC8143
BLOCK DIAGRAm
20k

20k

20k

VREF 151---.--...- -...--'WH~-'I/\,..,......--i'~-'I/\"""....-..,

OUT1

VoolE}--

OUT2
AGND

BIT4

BIT 2
(LSB)

STB1
INPUT 12-BIT SHIFT REGISTER

IN 1....1-------'10 SRI

------------,
I

6 SRO I

I
I

~

7543/814380

I

_____ .!:~~1~~~~U

DGND@--

TiminG DIAGRAm

STROBE INPUT
STB1, STB2, STB4
(INVERT FOR STB3)

___-+_---1

SRI

SRO
(LTC8143 ONLY)

BIT 1 (MSB)
CURRENT WORD
750W8143 TOOl

6-77

LTC 7543/LTC8143
TRUTH TABLES
Table 1. LTC7543/LTC8143 Input Register
CONTROL INPUTS .
STB1 STB2 STB3 STB4
S
0
1
0
S
1
0
0
l:.
0
0
0
S
1
0
0
X
X
X
1
X
1
X
X
X
X
0
X
X
X
X
1

Table 2. LTC7543/LTC8143 DAC Register

Input Register Operation
(LTC8143: SRO Operation)
Serial Data Bit on SRI Loaded into Input
Register, MSB First
(LTC8143: Data Bit or SRI Appears on
SRO Pin After 12 Clocked Bits)
No Input Register Operation
(LTC8143: No SRO Operation)

CONTROL INPUTS
CLR L01 L02
0
X
X
1
X
0

X
1
0

OAC Register Operation
Reset DAC Register to All Os (Asynchronous
Operation; No Effect on Input Register)
No DAC Register Operation
Load DAC Register with the Contents of Input
Register

TYPICAL APPLICATiOnS
Unipolar Dperation (2-Quadrant Multiplication)

VOUT
OVTO -VREF

TO NEXT DAC
FOR DAISY-CHAINING
(LTC8143)

7543J8143TAQ3

Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER IN
OAC REGISTER
MSB
LSB

6-78

ANALOG OUTPUT

Your

1111

1111

1111

- VREF (4095/4096)

1000

0000

0000

- VREF (2048/4096) = - VREF/2

0000

0000

0001

-VREF (1/4096)

0000

0000

0000

OV

LTC7543/LTCB143
TYPICAL APPLICAnOnS
Bipolar Operation (4-Quadrant Multiplication)

VOUT

Bipolar Offset Binary Code Table
DIGITAL INPUT
BINARY NUMBER IN
DAC REGISTER
MSB
LSB

ANALOG OUTPUT
VOUT

1111

1111

1111

VREF (2047/2048)

1000

0000

0001

VREF (1/2048)

1000

0000

0000

OV

0111

1111

1111

- VREF (1/2048)

0000

0000

0000

- VREF (2048/2048) = - VREF

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC1257

Complete Serial 1/0 VOUT 12-Bit DAC

LTC1451/LTC1452/LTC1453

5V to 15V Single Supply in 8-Pin SO and PDIP
3V/5V Single Supply in 8-Pin SO and PDIP

LTC7541A

Complete Serial 1/0 VOUT 12-Bit DACs
Parallel 1/0 Mulitplying 12-Bit DAC

LTC8043

Serial Mulitplying 12-Bit DAC

.L7lJD~

12-Bit Wide Input
a-Pin SO and PDIP

6-79

I~TLElcnHNt1\O"OQG~v~--------_U_C_80_43
~
Serial12-Bit Multiplying

~,

IT

DAC in SO-8
FEATURES

DESCRIPTiOn

• Improved Direct Replacement for DAC-S043 and
MAX543
• 80-8 Package
• DNL and INL Over Temperature: ±O.5L8B
• Easy, Fast and Flexible Serial Interface
• ±1L8B Maximum Gain Error
• 4-Quadrant Multiplication
• Low Power Consumption
• Low Cost

The LTC®S043 is a serial-input 12-bit multiplying digitalto-analog converter (DAC). It is asuperior pin compatible
replacement for the DAC-S043. Improvements include
better accuracy, better stability over temperature and
supply variations, lower sensitivity to output amplifier
offset, tighter timing specifications and lower output capacitance.
An easy-to-use 3-wire serial interface is well-suited to
remote or isolated applications
The LTCS043 is extremely versatile. It can be used for
2-quadrant and 4-quadrant multiplying, programmable
gain and single supply applications, such as noninverting
voltage output mode.

APPLICATions
•
•
•
•
•

Process Control and Industrial Automation
Remote Microprocessor-Controlled Systems
Digitally Controlled Filters and Power Supplies
Programmable Gain Amplifiers
Automatic Test Equipment

Parts are available in S-pin SO and PDIP packages and are
specified over the extended industrial temperature range,
-40°C to S5°C.
LT, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Integral Nonlinearity Over Temperature

80-8 Multiplying OAC Has Easy 3-Wire 8eriallnterface

1.0

'"
~

;:- 0.5
>--

~

CLOCK

~

DATA
LOAD

VOUT

'"a
'"

r-- TA = 815"C~

~TA=25"C~ _

0
\

~

=-40"C

",-0.5
~
~

-1.0

o

512 10241536 2048 2560 3072 35844095
DIGITAL INPUT CODE
LTC8043 "TPC02

6-80

LTC8043
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

VDD to GND ................................................. -O.5V to 7V
Digital Inputs to GND .................. -O.5V to (VDD + O.5V)

TOP VIEW

ORDER PART
NUMBER

'~o'oo

VIOUT to GND ............................... -O.5V to (VDD + O.5V)
VREF to GND .......................................................... ±25V

RFB 2

lOUT

VRFB to GND .......................................................... ±25V
Maximum Junction Temperature .......................... 150°C

ClK
SRI
5 ill
7

3

GND 4

N8 PACKAGE
HEAD PDIP

Operating Temperature Range ............... -40°C to 85°C
Storage Temperature Range ................ -65°C to 150°C

LTC8043EN8
LTC8043FN8
LTC8043ES8
LTC8043FS8

6

S8 PACKAGE
HEAD PLASTIC SO

TJMAX = 150'C. 8JA = 130'C/W (N8)
TJMAX = 150'C. 8JA = 190'C/W (S8)

Lead Temperature (Soldering, 10 sec) .................. 300°C

..

Consult factory for Military grade parts.

ACCURACY CHARACTERISTICS
SYMBOL PARAMETER
Resolution
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Gain Error
GE

IlKG

Gain Temperature Coefficient
(L\Gain/L\Temp)
Output Leakage Current

CONDITIONS
(Note 1)
Guaranteed Monotonic, TMIN to TMAX
(Note 2)
TA = 25°C
TMIN to TMAX
(Note 3)
(Note 4)

TA = 25°C
TMIN to TMAX
TA = 25°C
TMIN to TMAX

Zero-Scale Error
PSRR

Power Supply Rejection Ratio Voo = 5V±5%

•
•

MIN
12

LTC8043E
TYP
MAX

•
•

•
•
•

•

1

MIN
12

±0.5
±0.5
±1
±2
5

LTC8043F
TYP
MAX

1

±1
±1
±2
±2
5

±5
±25
±0.03
±0.15
±0.0001 ±0.002

±5
±25
±0.03
±0.15
±0.0001 ±0.002

UNITS
Bits
LSB
LSB
LSB
LSB
ppm/oC
nA
nA
LSB
LSB
%/%

ELEORICAL CHARAOERISTICS
Voo =5V, VREF =10V, VIDUT =GND =OV, Tp TMIN to TMAX, unless otherwise specified.
SYMBOL PARAMETER
Reference Input
RREF
IVREF Input Resistance
AC Performance (Note 3)

THO

CONDITIONS

I (Note 5)

Output Current Sellling Time

(Noles 6, 7)

Multiplying Feedthrough Error
Digital-to-Analog Glitch Energy

VREF = ±10V, 10kHz Sinewave
(Notes 6, 8)

Total Harmonic Distortion

(NoteS)

Output Noise Voltage Density

(Note 10)

Analog Outputs (Note 3)
GOUT

Output CapaCitance

MIN

I• I

•
•
•
•
•

7

ALL GRADES
TYP
MAX

UNITS

kn

11

15

0.25

1

~

0.7

1

mVp_p

2

20

nVSEC

-108

-S2

dB

17

nV/\I'Hz

DAC Register Loaded to All 1s

60

SO

pF

DAG Register Loaded to All Os

30

60

pF

6-81

LTC B043
ElEORICAl CHARAOERISTICS
VDD = 5V, VREF = 10V, VIDUT = GND = OV, TA = TMIN to TMAl(, unless otherwise specified.
SYMBOL PARAMETER
Digitallnpuls
Digital Input High Voltage
VIH

CONDITIONS

Digital Input Low Voltage
Vil
Digital Input Current
liN
Digital Input Capacitance
CIN
Timing Characteristics (Note 3)
tos
tOH
tSRI
tCH

MIN

•
•
•
•
•
•
•
•
•
•
•

VIN =OV to Voo
VIN =OV.(Note 3)

Serial Input to Clock Setup Time
Serial Input to Clock Hold Time
Serial Input Data Pulse Width
Clock Pulse Width High

Clock Pulse Width Low
Load Pulse Width
LSB Clocked into Input Register
tASB
to Load DAC Register Time
Power Supply
Supply Voltage
Voo

tCl
tLO

100

•
••

Digital Inputs =OV or Voo
Digital Inputs =VIH or VIN

Supply Current

The. denotes specifications which apply over the full operating
temperature range.
Note 1: ±0.5LSB = ±0.012% of full scale.
Note 2: Using internal feedback resistor.
Note 3: Guaranteed by design. not subject to test.
Note 4: lOUT with DAC register loaded with all Os.
Note 5: Typical temperature coefficient is 100ppm1"C.
Note 6: lOUT load = 1000 in parallel with 13pF.

ALL GRADES
TYP
MAX

2.4
0.8

V

±1
8

!iA
pF

30

-5

ns

60
80
80

25

ns
ns
ns

80
140

ns
ns

0

ns

4.75

5

5.25

V

100
500

!iA
!iA

Note 7: To 0.01% for a full-scaie change, measured from
falling edge of LD.
Note 8: VREF = OV. DAC register contents changed from all Os to all 1s or
from alils to all Os.
Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with alils.
Note 10: 10Hz to 100kHz between RFB and lOUT. Calculation from en =
.y4KTRB where: K= Boltzmann constant (J/KO); R= resistance (0);
T = resistor temperature (OK); B= bandwidth (Hz).

BIT 3

BIT4

OAC REGISTER

6-82

V
0.001

BLOCK DIAGRAm

ClK

UNITS

INPUT 12·BIT SHIFT REGISTER

BIT12
(lSB)

IN I~'I----...,m SRI

LTC8043
TiminG DIRGRRm
elK INPUT

----+----'

SRI

ill _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~~

~
TYPICRL RPPLICRTlons
Unipolar Operation (2-Quadrant Multiplication)
Table 1. Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
MSB
LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000

ANALOG OUTPUT

Your
-VREF (4095/4096)
-VREF (2048/4096) = -VREF/2
-VREF (1/4096)
OV

II

Bipolar Operation (4-Quadrant Multiplication)
R2

R3

Table 2. Bipolar Offset Binary Code Table

2°fvk_...,
-10VTO~RO~ - ._ _ _ _-'t/\20fyk_ _ _ _......._--'tA

VOUT

DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
MSB
LSB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000

ANALOG OUTPUT

Your
+VREF (2047/2048)
+VREF (1/2048)
OV
-VREF (1/2048)
-VREF (2048/2048) =-VREF

RELRTED PRRTS
PART NUMBER

OESCRIPTION

LTC1257
LTC1451/LTC14521LTC1453

Complete Serial 1/0 VOUT 12-Bit DAC

COMMENTS
5Vto 15V Single Supply in 8-Pin SO and PDIP

Complete Serial 110 VOUT 12-Bit DACs

3V/5V Single Supply in 8-Pin SO and PDIP

LTC7541A

Parallel 1/0 Multiplying 12-Bit DAC

12-Bit Wide Input

LTC7543/LTC8143

Serial 1/0 Mulitplying 12-Bit DACs

Clear Pin and Serial Data Output (LTC8143)

6-83

NOTES

6-84

INDEX
SECTION 6-DATA CONVERSION
MULTIPLEXERS
LTC1390, 8-Channel Analog Multiplexer with Serial Interface ............................................................... 6-86

6-85

f-'''"llneJ\Q
~, TECHNOLOG~IY~----8--C-ha-nn-el

LTC 1390

Analog Multiplexer
with Serial Interface
FEATURES

DESCRIPTion

• 3-Wire Serial Digital Interface
• Data Retransmission Allows Series Connection
with Serial AID Converters
• Single 3V to ±5V Supply Operation
• Analog Inputs May Extend to Supply Rails
• Low Charge Injection
• Low RON: 750 Max
• Low Leakage: ±5nA Max
• Guaranteed Break-Before-Make
• TIUCMOS Compatible for All Digital Inputs
• Cascadable to Allow Additional Channels
• Can Be Used as a Demultiplexer

The LTC®1390 is ahigh performance CMOS 8-to-1 analog
multiplexer. It features a 3-wire digital interface with a
bidirectional data retransmission feature, allowing it to be
wired in series with aserial AID converter while using only
one serial port. The interface also allows several LTC1390s
to be wired in series or parallel, increasing the number of
MUX channels available using only asingle digital port. All
the above features are also valid when LTC1390 operates
as a demultiplexer such as with a D/A converter.

APPLICATions
• Data Acquisition Systems
• Communication Systems
• Signal Multiplexing/Demultiplexing

The LTC1390 features atypical RON of 450, typical switch
leakage of 50pA, and guaranteed break-before-make operation. Charge injection is ±10pC maximum. All digital
inputs are TIL and CMOS compatible when operated from
single or dual supplies. The inputs can withstand 100mA
fault currents.
The LTC1390 is available in 16-pin PDIP and narrow SO
packages.
D, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
ON-Resistance vs
Analog Input Voltage

Vee
250

TA = 25°C

(\

200

V+=3~

V-=OV
~ 150

ANALOG
INPUTS

z

/

>'en!:

~

100

~
3-WIRE {DATA

TO MUXAND ADC

C~----"""'+----+------LTC1-"'_"""'TAO'
CS

-------4......

----1

\

V+=5V
V =-5V

50

INT~~~~~~

I

a

~

~

~ 4
~
a 1 2 3 4
ANALOG INPUT VOLTAGE, Vs (V)

5

LTC1S90·TA02

6-86

LTC 1390
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

(Note 1)

Total Supply Voltage (V+ to V-) .............................. 15V
Input Voltage
Analog Inputs ........................ v- - O.3V to v+ + O.3V
Digital Inputs ........................................ -O.3V to 15V
Digital Outputs ............................ -O.3V to V+ + O.3V
Power Dissipation ................ ................ ............. 500mW
Operating Temperature Range ..................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER

TOP VIEW

LTC1390CN
LTC1390CS
S6

S7
N PACKAGE
16·LEAO PDlP

S PACKAGE
16-LEAO PLASTIC SO

TJMAX= 150'C. 8JA= 70'C/W (N)
TJMAX= 150'C. 8JA = 100'C/W (S)

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS
V+ =5V, V- =-5V, GND =OV, TA =operating temperature unless otherwise noted.
SYMBOL

I PARAMETER

I CONDITIONS

MIN

TYP

MAX

UNITS

Switch
VANALOG

Analog Signal Range

(Note 2)

RON

On Resistance

Vs =±3.5V, 10 =1mA
TMIN
25°C
TMAX

•

-5

45

75
75
120

n
n
n
%
%/oC

O.S

IS(OFF)

Off Input Leakage

Vs =4V, Vo =-4V; Vs =-4V, Vo =4V
Channel Off

10(OFF)

Off Output Leakage

Vs =4V, Vo =-4V; Vs =-4V, Vo =4V
Channel Off

10(ON)

On Channel Leakage

Vs =Vo =±4V
Channel On

VINH

High Level Input Voltage

V+ =S.2SV

VINL

V+ =4.7SV

IINL,IINH

Low Level Input Voltage
Low or High Level Current

VOH

High Level Output Voltage

V+ =4.7SV, 10 =10~
V+ =4.7SV, 10 =360~

Input

Low Level Output Voltage

V

20

dRON vs Vs
dRON vs Temperature

VOL

5

VIN =5V, VIN =OV

V+ =4.7SV, 10 =O.SmA

•
•
•
•
•
•

•
•

O.OS

±S
±SO

nA
nA

O.OS

±S
±SO

nA
nA

O.OS

±S
±SO

nA
nA

2.4

V
0.8
±1

2.4

4.74
4.S0
0.16

V
~

V
V
0.8

V

6-87

LTC 1390

ELECTRICAL CHARACTERISTICS
Y+ =5Y, Y- =-5Y~ GND = OY, TA = operating temperature unless otherwise noted.
SYMBOL I PARAMETER
Dynamic

MIN

I CONDITIONS

TYP

MAX

UNITS

fCLK

Clock Frequency

5

MHz

tON

Enable Turn-On Time

Vs =2.5V, RL =1k, CL =35pF

260

400

ns

tOFF

Enable Turn-Off Time

Vs =2.5V, RL =1k, CL =35pF

100

200

tOPEN
OIRR

Break-Belore-Make Interval

ns
ns

Off Isolation

Vs =2Vp_p, RL =1k, f =100kHz

70

OINJ

Charge Injection

Rs =0, CL =1000pF, Vs =1V (Note 2)

±2

CS(OFF)
CO(OFF)
Supply

Source Off Capacitance

5

pF

Drain Off Capacitance

10

pF

I'

Positive Supply Current

All Logic Inputs Tied Together, VIN = OV or VIN = 5V

15

40

Negative Supply Current

All Logic Inputs Tied Together, VIN = OV or VIN = 5V

15

40

TYP

MAX

35

155

dB
±10

pC

Y+ =3V, V- = GND = OV, TA = operating temperature unless otherwise noted.
SYMBOL

I PARAMETER

I CONDITIONS

MIN

UNITS

Switch
VANALOG
RON

Analog Signal Range

(Note 2)

On Resistance

Vs =1.2V, 10 =1mA
TMIN
25°C
TMAX

IS(OFF)
la(OFF)

Off Output Leakage

Vs =2.5V, Va =0.5V; Vs =0.5V, Va =2.SV (Note 3)
Channel Off

Ip(ON)

On Channel Leakage

Vs =Vo =0.5V, Vs =Vo =2.5V (Note 3)
Channel On

VINH

High Level Input Voltage

V' =3.3V

VINL

Low Level Input Voltage

V' =2.7V
VIN =3V, VIN =OV
V' =2.7V, 10 =20~
V' =2.7V, 10 =400~

IINL,IINH

High Level Output Voltage

VOL

Low Level Output Voltage

6-88

200

3

V

255
255
300

n
n
n
%
%/oC

0.5
Vs =2.SV, Va =O.SV; Vs =0.5V, Va =2.SV (Note 3)
Channel Off

Input

VOH

0

20

aRON vs Vs
aRON vs Temperature
Off Input Leakage

Low or High Level Current

•

V' =2.7V, 10 =20~
V' =2.7V, 10 =300~

•
•

•
•
•
•
•

•

±O.OS

±S
±50

nA
nA

±0.05

±5
±50

nA
nA

±O.OS

±5
±50

nA
nA

2.4

2

V
0.8

V

±1

~
V
V

2.68
2.27
0.01
0.15

0.8

V
V

LTC 1390
ELECTRICAL CHARACTERISTICS
1+ =3V, v- =GND =OV, TA =operating temperature unless otherwise noted.
iYMBOL

I PARAMETER

I CONDITIONS

MIN

TYP

MAX

UNITS

Iynamic
CLK

Clock Frequency

ON

Enable Turn-On Time

Vs = 1.5V, RL = 1k, CL = 35pF (Note 4)

490

700

ns

OFF

Enable Turn-Off Time
Break-Before-Make Interval

Vs = 1.5V, RL = 1k, CL = 35pF (Note 4)
(Note 4)

190

300

ns

Off Isolation

llNJ
:s(OFF)

Charge Injection

:D(OFF)
iupply

Drain Off Capacitance

OPEN
llRR

5

125

MHz

290

ns

Vs = 2Vp_p, RL = 1k, f = 100kHz

70

dB

Rs = 0, CL = 1000pF, Vs = 1V (Note 2)

±1

Source Off Capacitance

±5

pC
pF

5
10

I Positive Supply Current

IAll Logic Inputs Tied Together, VIN = OV or VIN = 3V

'he • denotes specifications which apply over the full operating
emperature range.
lole 1: Absolute maximum ratings are those beyond which the safety of
he device may be impaired.
lole 2: Guaranteed by design.

pF

0.2

2

Nole 3: Leakage current with a single 3V supply is guaranteed by
correlation with the leakage current of the ±5V supply.
Nole 4: Timing specifications with a single 3V supply is guaranteed by
correlation with the timing specifications of the ±5V supply.

rYPICAL PERFORmAnCE CHARAaERISTICS
Driver Output Low Voltage
vs Output Current

ON-Resistance vs Temperature
300
250
200
150

-

I

f-- f--

-;::;

v-=ov
Vs=1.2V
I

-

300
250

§ 200
u

~

--

I

~

~
v-=ov

Driver Output High Voltage
vs Output Current

-

Vs =11.2V

:::>
u

50

o

:Z
100
o

10

20 30 40 50
TEMPERATURE eC)

60

70

o

:::>

o

10

I

20 30 40 50
TEMPERATURE ee)

f-

:::>
0

r-

-4

DATA
-5

-6

60

70

DAiAY

V
~

0-

v+Lv
V-=-5V
Vs=ov

50

I
o

f-

c::

V+l5V
V-=-5V
Vs =ov

<"
.S- -2
f1'c::5 -3
c::

150

ffj

100

TA =25"C
V+=5V
v- =-5V

-1

-7

2.0

./

V

v/
V

W

/

/

2.5

3.0 3.5
4.0 4.5
OUTPUT VOLTAGE (V)

5.0

LTC13900G03

6-89

•

LTC 1390
Pin FunCTions
SO to S7 (Pins no 8): Analog Multiplexer Inputs/Analog
Demultiplexer Outputs.

analog signal transmission and allows data transfer from
Data 2 to Data 1.

GND (Pin 9): Digital Ground. Connect to system ground.

Data 1 (Pin 12): Bidirectional DigitallnpuVOutput (TTU
CMOS Compatible). Input for the channel selection bits.

ClK (Pin 10): System Clock (TTUCMOS Compatible). The
clock synchronizes the channel selection bits and the
serial data transfer from Data 1 to Data 2.

Data 2 (Pin 13): Bidirectional DigitallnpuVOutput (TTU
CMOS Compatible).

CS (Pin 11): Chip Select Input (TTUCMOS Compatible). A
logic high on this input enables LTC1390 to read in the
channel selection bits and allow data transfer from Data 1
to Data 2. A logic low enables the desired channel for

y- (Pin 14): Negative Supply.

D (Pin 15): Analog Multiplexer Output/Analog
Demultiplexer Input.
y+ (Pin 16): Positive Supply.

APPLICATions InFoRmATion
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1390 required for MUX operation. The
LTC1390 uses Data 1 to select its 8 channels and a chip
select input CS to switch on the selected channel as shown
in Figure 2.
ClK
DATAl

CS ----0"1..-_----1

ANALOG
OUTPUT

Figure 1: Simplified Block Diagram 01 the MUX Operation

When CS is high, the input data on the Data 1 pin is latched
into the 4-bit shift register on each rising clock edge. The
input data consists of an "EN" bit and astring of three bits
for channel selection. If "EN" bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. To ensure correct operation, the CS must be
pulled low before the next rising clock edge.
Once the CS is pulled low, all channels are simultaneously
switched off to ensure abreak-before-make interval. After
adelay oftON, the selected channel is switched on allowing
signal transmission. The selected channel remains on
until the next falling edge of CS, and after a delay of tOFF,
it terminates the analog signal transmission and subsequently allows the selection ofthe next channel. If "EN" bit
is logic low, as illustrated in the second data sequence, it
disables all channels and there will be no analog signal

ClK

DATA 1
ANY
ANALOG
INPUTS

Figure 2: Multiplexer Operation

6-90

LTC 1390
APPLICATions InFoRmATion
transmission. Table 1 shows the various bit combinations
for channel selection.
Table 1. Logic Table for Channel Selection
CHANNEL STATUS
All Off

B2
X
0
0
0
0
1
1
1
1

EN
0
1
1
1
1
1
1
1
1

SO
S1
S2
S3
S4
S5
S6
S7

B1
X
0
0
1
1
0
0
1
1

BO
X
0

1
0
1
0
1
0
1

selection or to Data 2 via Buffer 1 for data transfer. Data
appears at Data 2 after the fourth rising edge of the clock.
When CS is low, Buffer 2 is enabled and Buffer 1 is
disabled, thus digital input data is directly transferred from
Data 2 to Data 1 without any clock delay.
Multiplexer Expansion
Several LTC1390s can be daisy-chained to expand the
number of multiplexer inputs. No additional interface
ports are required for the expansion. Figure 5 shows two
LTC1390s connected at their analog outputs to form a16to-1 multiplexer at the inputto an LTC1286A1D converter.

Digital Data Transfer Operation
The block diagram of Figure 3 shows the components
contained within the LTC1390 required for digital data
transfer. Digital data transfer operation can be performed
from Data 1 to Data 2 and vice versa as shown in Figure 4.
When CS is high, Buffer 1 is enabled and Buffer 2 is
disabled. The digital input data is fed into the 4-bit shift
register and then shifted to the MUX switches for channel

ANALOG
INPUTS

elK

cs
DATA1

ANALOG
INPUTS

- + - - - - - - -....
-4------<

Figure 3. Simplified Block Diagram of the Digital Data
Transfer Dperation

DATA 1

Hi-Z

/.:'::t~

/

--.:.;;..;;.....-~_ _D_AT_AI_N_ _ __

DATA2_
LTC1SOO-F04

Figure 4. Digital Data Transfer Dperation

..L7lJ!J~

Figure 5. Daisy-Chaining Two LTC1390s for Expansion

To ensure that only one channel is switched on at anyone
time, two sets of channel selection bits are needed for Data
as shown in Figure 6. The first data sequence is used to
switch off one MUX and the second data sequence is used
to select one channel from the other MUX, or vice versa.
In other words, if bit "ENA" is high and bit "ENB" is low,
one channel of MUX A is switched on and all channels of
MUX Bare switched off. If bit "ENA" is low and bit "ENB"
is high, all channels of MUX A are switched off and one
channel of MUX B is switched on .

6-91

LTC1390
APPLICATions InFoRmATion
ClK

DIGITAL INPUT FROM lTC1390

DIGITAL OUTPUT FROM lTC1286

LTC1300'F06

Figure 6. Timing Diagram for Figure 5

TYPICAL APPLICATiOnS
Daisy-Chaining Five LTC1390s
8YPASS CAPACITOR FROM v+ TO GND AND
V- TO GND REQUIRED FOR EACH LTC1390

ANALOG
INPUTS

ANALOG
INPUTS
ANALOG
INPUTS

ANALOG
INPUTS
ANALOG
INPUTS

.:.:....---t-+-+-t---DATA·
~---t-+-+~--~

.l.l!----t-+.......- - - C L K
"REQUIRES FIVE HIT CHANNEL
SELECTION DATA BYTES
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '

6-92

LTC'390 o f01

LTC 1390
TYPICAL APPLICATions
Interfacing LTC139D with LTC1257 for Demultiplex Operation

ANALOG
OUTPUTS

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC201 AILTC202/LTC203
LTC221 IL TC222

Micropower, Low Charge Injection, Quad CMOS Analog Switches
Micropower, Low Charge Injection, Quad CMOS Analog Switches
with Data Latches

Parallel Controlled with Data Latches

LTC128x1LTC129x

Serial AIDs with Integral MUXs

.L7lJ!J~

Each Channel is Independently Controlled

6-93

NOTES

6-94

SECTion 7-VOLTAGE REFEREnCES

7-1

INDE)(
SECTION 7-VOLTAGE REFERENCES
INDEX ••..•••....•.....•..•..........................••....••.....•••..•...••.•.•••••..••••..••.••..•...••.••...••••..•••..••.••••...•.••..... 7-2
SELECTION GUIDES .•••.........•....•......••...••........•....•.••..•••..•••....•.••...••••...••..•...•...•.••..••...•...•.•..••.•...•••• 7-3
PROPRIETARY PRODUCTS
LT1236, Precision Reference ....•..........................•....••....•......•...................•......•.......•................... 7-5

7-2

VOLTAGE REFERENCES
Listed by Temperature Drift (T.e.) and Initial Accuracy
1.25V Output
T.C.
*LT1034B-l.2
*LTl 034-1.2
*LTl 004-1.2
*LM385B-1.2
*LM385-1.2

ACCURACY
*LTl 004-1.2
* LT1034B-1.2
*LT1034-1.2
*LM385B-l.2
*LM385-1.2

6.9V to 6.95V Output
T.C.
LTZ1000
LM399A
LM399
LM329A
LM329B
LM329C

ACCURACY
LM329A
LTZ1000
LM329B
LM329C
LM329D
LM299A

2.5V Output
T.C.
ACCURACY
LTl 019C-2.5 LT580M
LTl009C-2.5 LT1019C-2.5
LT1009-2.5
LT580M
LTl 034B-2.5 LT580L
LT580L
LT1034-2.5
*LT1 004C-2.5 LT580K
LT1034-2.5 * LT1 004C-2.5
LT580K
*LM385B-2.5
* LM385B-2.5 *LM385-2.5
LM336B-2.5
LT580J
*LM385-2.5
LM336B-2.5
LM336-2.5
LM336-2.5

4.5VOutput
T.C.
LTl 019C-4.5

ACCURACY

5.0VOutput
T.C.
LT1027A-5
LT1027B-5
LT1027C-5
LT1236A-5
LT1027D-5
LTl 021 B-5
LT1027E-5
LT1236B-5
LT1236C-5
REF-02E
LT1019-5
LT1029A
REF-02H
LTl 021 C-5
LT1021D-5
LT1029
REF-02C
REF-02D

ACCURACY
LT1027A-5
LT1027B-5
LT1027C-5
LT1236A-5
LT1021C-5
LT1027D-5
LT1027E-5
LT1236B-5
LT1236C-5
REF-02E
LT1019-5
LT1021B-5
LT1021D-5
LT1029A
REF-02H
LT1029
REF-02C
REF-02D

7V Output
T.C.
LT1021B-7
LT1021 D-7
LT1034

ACCURACY
LT1021B-7
LT1021D-7
LT1034

lOVOutput
T.C.
LT1236A-l0
LT1019A-l0
LT1021C-l0
LT1236B-l0
LT1236C-l0
LT1031C
REF-OlE
LT581K
LT1019-10
LT1031D
LT581J
LT1021B-l0
LT1021D-l0
LT1031B
REF-01H
REF-01C

ACCURACY
LT1236A-l0
LT1019A-l0
LT1021B-l0
LT1236B-l0
LT1236C-l0
LT1031B-l0
REF-OlE
LT1031C
LT581K
LT1019-10
LT1021C-l0
LT1021D-l0
LT1031D
REF-01H
LT581J
REF-01C

* Micropower

7-3

VOLTAGE REFERENCE SELECTION GUIDE
Commercial ooe to 70 e
0

VOLTAGE
Vz
(V)

VOLTAGE
TOLERANCE
MAXIMUM
TA= 25°C

1.235

±0.32%
±1%

TEMPETATURE
DRIFT, ppm/"C
OR mVCHANGE

MllJINO
TEMP

LTlO04-t.2
LT1034B-l.2

20ppm (typ)
20ppm (max)

M,I
M,I

101lA to 20mA
201lA to 20mA

H, S,Z
H, S, Z

±1%

LT1034-1.2

40ppm (max)

M,I

201lA to 20mA

H, S, Z

±2'10
±1%

LM38S-1.2
LM38SB-1.2

20ppm (typ)
20ppm (typ)

M,I
M

ISIlA to 20mA
ISIlA to 20mA

H, Z
H,Z

±0.8%
±0.2%
±O.4%
±O.OS%
±0.2%
±1%

LT1004-2.S
LT1009
LT100988
LT1019A-2.S
LTlOI9-2.S
LT1034B-2.S

20ppm (typ)
SmV (max)
2Sppm (max)
Sppm (max)
20ppm (max)
20ppm(max)

M,I
M,I
M,I
M
M,I
M,I

201lA to 20mA
4001lA to 10mA
4001lA to 20mA
1.0mA
1.2mA
201lA to 20mA

H,S,Z
H,Z
S
H,N
H, N, S
H,S,Z

±1%

LT1034-2.S

40ppm (max)

M,I

201lA to 20mA

H, S, Z

±4'10
±2'10
±3'10
±1.S%
±3'10
±1%
±O.4%
±0.4%

LM33S-2.S
LM336B-2.S
LM365-2.S
LM38SB-2.S
LTS80J
LTS80KlK
LTS80UU
LTS80M

SmV(max)
6mV(max)
20ppm (typ)
20ppm (typ)
8Sppm (max)
40ppm (max)
2Sppm (max)
10ppm (max)

M
M
M,I
M

4001lA to 10mA
4001lA to 10mA
201lA to 20mA
201lA to 20mA
I.SmA
I.SmA
I.SmA
I.SmA

H,Z
H,Z
H, Z
H,Z
H
H
H
H

4.5

±O.OS%
±0.2%

Sppm (max)
20ppm (max)

5.0

±O.OS%
±0.2%
±1%
±O.OS%
±1%
±0.02%
±O.OS%
± 0.05%
± 0.05%
± 0.1%
±0.2%
±1%
±O.OS%
±O.I%
±O.I%
±1%
±2'10
±0.3%
±O.S%

LT1019A-4.S
LTlOI9-4.S
LT1019A-S
LT1019-S
LTI 021 B-S
LT1021C-S
LTI 021 D-S
LT1027A
LT1027B
LT1027C
LTl027D
LT1027E
LTl029A
LTl029
LTI236A-S
LT1236B-S
LT1236C-S
REF02C
REF02D
REF02E!A
REF02H

Sppm (max)
20ppm (max)
Sppm (max)
20ppm (max)
20ppm (max)
2ppm (max)
2ppm (max)
3ppm (max)
Sppm (max)
7.Sppm (max)
20ppm (max)
34ppm (max)
Sppm (max)
10ppm (max)
ISppm (max)
6Sppm (max)
2S0ppm (max)
8.Sppm (max)
2Sppm (max)

M
M,I
M
M,I
M,I
M,I
M,I

6.9

±3'10
±5'10
±S%
±S%
±4'10

LM329A
LM329B
LM329C
LM329D
LTZlOOO

10ppm (max)
20ppm (max)
SOppm (max)
100ppm (max)
O.lppm

M
M
M

6001lA to ISmA
6001lA to ISmA
6001lA to ISmA
6001lA to 1SmA
4mA

H, Z
H, Z
H,Z
H, Z
H

6.95

±S%
±S%

LM399
LM399A

2ppm (max)
lppm (max)

M
M

SOOIlA to 10mA
SOOIlA to 10mA

H
H

7.0

±0.7%
±0.7%

LTI 021 B-7
LTl021 0-7

Sppm (max)
20ppm (max)

M
M

1.0mA
1.0mA

H,N
H,N,S

Low DriIVNoise, Exc Stability
Low Gost, High Performance

10.0

±O.OS%
±0.2%
±O.S%
±O.OS%
±O.S%
±O.OS%
±O.I%
±0.2%
±O.OS%
±O.I%
±O.I%
±0.3%
±O.I%
±O.OS%
±1%
±0.3%
±O.S%

LTI019A-l0
LTlO19-10
LTl021B-l0
LTl021G-l0
LTl021D-l0
LTl031B
LTl031G
LT1031D
LT1236A-l0
LT1236B-l0
LT1236G-l0
LT581J/S
LT581Krr
LTS81L/U
REF01G
REF01E/A
REF01H

Sppm (max)
20ppm (max)
Sppm (max)
20ppm (max)
20ppm (max)
Sppm (max)
ISppm (max)
2Sppm (max)
Sppm (max)
10ppm (max)
ISppm (max)
30ppm (max)
15ppm (max)
Sppm (max)
65ppm (max)
8.Sppm (max)
25ppm (max)

M
M,I
M,I
M,I
M,I
M
M
M
I
I
I
M
M
M
M
M

1.2mA
1.2mA
1.7mA
1.7mA
1.7mA
1.7mA
1.7mA
l.7mA
1.2mA
1.2mA
1.2mA
1.0mA
1.0mA
1.0mA
1.6mA
l.4mA
l.4mA

H, N
H,N,S
H, N
H, N
H,N,S
H
H
H
N,S
N,S
N, S
H
H
H
H,J, N
H,J, N
H,J, N

Precision Bandgap
Precision Bandgap
Very Low Drift
Very Tight Initial Tolerance
Low Gost, High Performance
Very Low Drift
Very Tight Initial Tolerance
Low Gost, High Performance
Tight Tolerance and Low TG Together
Tight Tolerance and Low TC Together
TightTolerance and LowTG Together
3 Terminal Low Drift
3 Terminal Low Drift
3 Terminal Low Drift
Precision Bandgap
Precision Bandgap
Precision Bandgap

2.5

PART NUMBER

*LTZI DOD requires external control and biasing circuits.

7-4

M
M

M
M
I
I
I
M

OPERATING
CURRENT RANGE
(OR SUPPLY CURRENT)

1.2mA
1.2mA
1.2mA
1.2mA
1.2mA
1.2mA
1.2mA
2mA
2mA
2mA
2mA
2mA
7001lA to 10mA
7001lA to 10mA
1.2mA
1.2mA
1.2mA
1.6mA
2.0mA
l.4mA
l.4mA

PACKAGE
TYPE

IMPORTANT FEATURES
Micropower
Low TC Micropower with
7V Aux Reference
Low TC Micropower with
7V Aux Reference
Micropower
Micropower
Micropower
Precision
Precision
Precision Bandgap
Precision Bandgap
Low TC Micropower with
7V Aux Reference
Low TC Micropower with
7V Aux Reference
General Purpose
General Purpose
Micropower
Micropower
3 Terminal Low Drift
3 Terminal Low Drift
3 Terminal Low Drift
3 Terminal Low Drift

H,N
H, N,S

Precision Bandgap
Precision Bandgap
Precision Bandgap
H,N
H, N,S Precision Bandgap
Very Low Drift
H,N
Very Tight Initial Tolerance
H,N
H, J, N, S Low Cost, High Performance
H
PreCision, Enhanced Dynamics
Precision, Enhanced DynamiCS
H,N
H,N
PreCision, Enhanced Dynamics
N, H,S PreCision, Enhanced Dynamics
N, H,S PreCision, Enhanced Dynamics
Precision Bandgap
H,Z
H,Z
Precision Bandgap
Tight Tolerance and Low TC Together
N, S
Tight Tolerance and Low TC Together
N,S
N, S
Tight Tolerance and Low TC Together
H,J, N Precision Bandgap
H,J, N Bandgap
H,J, N Precision Bandgap
H,J, N Precision Bandgap
Low Drift
Low Drift
General Purpose
General Purpose
Ultra Low Drift,
2ppm Long Term Stability'
Ultra Low Drift
Ultra Low Drift

~Y~JD~G~~IIiII.!I-----p-re-C-iS-io-n-R-e-f-e~-~-~-~-~
FEATURES

DESCRIPTion

•
•
•
•
•
•
•
•
•
•

The L~1236 is aprecision reference that combines ultralow drift and noise with excellent long-term stability and
high output accuracy. The reference output will both
source and sink up to 1OmA and is almost totally immune
to input voltage variations. Two voltages are available: 5V
and 1OV. The 1OV version can be used as ashunt regulator
(two-terminal zener) with the same precision characteristics as the three-terminal connection. Special care has
been taken to minimize thermal regulation effects and
temperature induced hysteresis.

Ultra-Low Drift: 5ppm/oC Max
Trimmed to High Accuracy: 0.05% Max
Industrial Temperature Range SO Package
Operates in Series or Shunt Mode
Pin Compatible with AD586, AD587
Output Sinks and Sources in Series Mode
Very Low Noise < 1ppm p_p (0.1 Hz to 10Hz)
100% Noise Tested
> 100dB Ripple Rejection
Minimum Input/Output Differential of 1V

The LT1236 combines both superior accuracy and temperature coefficient specifications withoutthe use of high
power, on-Chip heaters. The LT1236 references are based
on a buried zener diode structure which eliminates noise
and stability problems with surface breakdown devices.
Further, a subsurface zener exhibits better temperature
drift and time stability than even the best band-gap
references .

APPLICATions
•
•
•
•
•

AID and D/A Converters
Precision Regulators
Precision Scales
Inertial Navigation Systems
Digital Voltmeters

.cr, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Typical Distribution of Temperature Drift

Basic Positive and Negative Connections

VOUT

24
22
20
18

NC

-VOUT

Rl = VOUT-(V-)
ILOAD + 1.5mA

Rl

16
~ 14


....::::>
....::::>c..
0

10k

60

l

1.4

!3

1.2

5o

TJ =-55°C
1.0
TJ -125°C

-5

-10 -B -6 -4 -2 0 2 4 6 B 10
SOURCING
SINKING
OUTPUT CURRENT (mA)
LT""G09

100

~

Thermal Regulation, LT1236-5

VIN = BV

VIN = 25V
aPOWER 1200~W

I)
~

,/

ill

-0.5

<.~>

-1.0

........

!3

::::>

I

10

15 20 25 30
INPUT VOLTAGE (V)

35

40

Load Transient Response,
LT1236-5, CLOAO = 0

-

"" THERMAL
REGULATION'_

IlOAO = 10mA

10

o

-

§

a::
a::

<.>

I

I--pLOAD
_ R:6!L~~V

[

40

~ 20

L

o

BO

50

~ 30

TJ = 25°C

0.4

20 40
60
TEMPERATURE (OC)

Sink Mode* Current Limit,
LT1236-5

IOUp 0

0.6

-2

-4

1.6

O.B

-1

-3

5.000
-40 -20

Quiescent Current, LT1236-5
1.B

./'

::J:

5.001

100
1k
BANDWIDTH (Hz)

10

,/'

w

o
".

./

.§.

-rH236-5

o

o

'\

5.003

~

~

0.2

~

~

.....H::t:U

Load Regulation LT1236-5

5.005

COUT= 0
FILTER = 1 POLE
flOW = 0.1Hz

o

4

6 B 10 12 14
OUTPUT VOLTAGE (V)

20

16 1B

40 60 BO
TIME (ms)

100 120 140

'NOTE THAT AN INPUT VOLTAGE IS REQUIRED
FOR 5V UNITS.

'INDEPENDENT OF TEMPERATURE COEFFICIENT

Load Transient Response,
LT1236-5, CLOAO =1000pF

Output Noise 0.1 Hz to 10Hz,
LT1236-5

LTl236G12

FILTERING = 1 ZERO AT 0.1Hz
2 POLES AT 10Hz

I

S-t-f-f'......,-f-'H;o..-f-ll-I+\.r-+l-fIo--f

~ I-#---+-"+-+--t--ll-H-+~

w

~r-~~~-+~~~~~~~-1
<.>~~~~~~--lI-f-f=~-r-1

!3

H-+-+-+--H,f-\-

5o~~4-~-+-4~~~+-~~~

I

r-- 51lV (1ppm)
,........•

1

....

..
t

alSOURCE = 1001lAp_p

o

5 10
TIME (MINUTES)

LT1236G13

7-9

LT1236
TYPICAL PERFORmAnCE CHARACTERISTICS
Output Voltage Temperature
Drift, LT1236-10

Load Regulation, LT1236-10

10.0020

r-

10.0015

~ 10.0005

/

;::!:

g10.0000
:=5

9.9995

I

::>

o

9.9990
9.9985

VIN=12V

./

~10.0010

;;-

/

.s
w

.

OJ

z

'-'

/

-20

/

:I:
f-

::>

0f-

::>
0

/
V

9.9980
-40

0
20
40
60
TEMPERATURE eC)

80

-1
-2

100

o

~ 0.8

0.6

o

l- I-

5o

/' .<'I--

l/

~

-4

0.2

2
4
6
8
10
OUTPUT TO GROUND VOLTAGE (V)

12

t;

)
o

10

15 20 25 30
INPUT VOLTAGE (V)

35

40

LT1236G18

INPUT PIN OPEN

VIN = 30V
dPOWER = 200mW

50

I

30

I

-

~

~ -0.5
~
[5 -1.0

...- V

a:

5o

I

LOAD

I- REGULATION

.---''---

V

- --

-- 1'0-

--

f-

~

~ 20

'-'

,

Thermal Regulation, LT1236-10

0::
0::

./

o

o

TJ = 125°C

'I
IV

;;;

::>

TJ=125°C

0.8

~ 0.6

~

, / ' KTJ~25OC

B

(

f-

~ 40

/

..,/" ...<

0::

B0.4
0.2

-

0.4

60

./ ./

f-

15

TJ = -55°C

1.0

f-

Shunt Mode Current Limit,
LT1236-10

:;(

r---

f5
0::

_ITJ = J50C J--- J---

0::

.s

~ 1.2
51.0

1.2

-10 -8 -6 -4 -2 0 2 4 6 8 10
SOURCING
SINKING
OUTPUT CURRENT (mA)

INPUT PIN OPEN

1.4

1.4

!

-5

1.6

!

...-

V

~J = _155 oC

lOUT = 0

1.6

/

-3

Shunt Characteristics, LT1236-10
1.8

Input Supply Current, LT1236-10
1.8

-1.5

THERMAL
REGULATION'

ILOAD = 10mA

10

o
o

4

6 8 10 12 14
OUTPUT VOLTAGE (V)

20

16 18

40 60 80
TIME (ms)

100 120 14

'INDEPENDENT OF TEMPERATURE COEFFICIENl

Load Transient Response,
LT1236-10, CLOAO =0

I I

rISINliOlmA,-

ISOURCE = 0

~tl

tfr
+1

I
I I l

ISXRCE = 0.2mA

50mV

It]\

J ISINK = 0.8mA
-',1\

I I

rlSINK = 0.8mA,_

-1"1 • l

ISOURCE = 0 I\.

rtl
5mV

1t

r

ISINK = 1.2mA

1

I

ISOURCE = 0.5mA

T II

I I l

rlsOURCE = 2·10mA

ISINK = 2·10mA
dlslNK = 100~p_p

0123401234
TIME (J!s)
NOTE VERTICAL SCALE CHANGE
BETWEEN SOURCING AND SINKING
LT1236G22

rlSOURCE = 2-1 OmA
dlSOURCE = 100~p_p

FILTERING = 1 ZERO AT O.lHz
2 POLES AT 10Hz

I

20mV

V ISINK = 1.0mA

dlSOURCE = 1OO~p_p

7-10

Output Noise 0.1 Hz to 10Hz,
LT1236-10

Load Transient Response,
LT1236-10, CLOAD = 1000pF

I

-10J!V(1ppm)

t

i

V

\
/ISINK = l.4mA

Ivlhl

t

lJISINK = 2-10mA
dISIN'K = l'OO~p_p

0123401234
TIME (J!S)
NOTE VERTICAL SCALE CHANGE
BETWEEN SOURCING AND SINKING
LT1236G23

2
TIME (MINUTES)
LT1236G24

LT1236
IPPLICAllons InFORmAlion
Ifect of Reference Drift on System Accuracy
large portion of the temperature drift error budget in
lany systems is the system reference voltage. This graph
dicates the maximum temperature coefficient allowable
the reference is to contribute no more than 0.5LSB error
I the overall system performance. The example shown is
12-bit system designed to operate over a temperature
Inge from 25°C to 65°C. Assuming the system calibraln is performed at 25°C, the temperature span is 40°C.
can be seen from the graph that the temperature coeffient of the reference must be no worse than 3ppm;oC if
is to contribute less than 0.5LBS error. For this reason,
e LT1236 family has been optimized for low drift.
Maximum Allowable Reference Drill
100

in series with a20kn potentiometer will give ±1 OmV trim
range. Effect on the output TC will be only 1ppm/oC for the
±5mV trim needed to set the "A" device to 10.000V.
LT1236-5
The LT1236-5 does have an output voltage trim pin, but
the TC of the nominal 4V open circuit voltage at pin 5 is
about -1. 7mV/oC. For the voltage trimming not to affect
reference output TC, the external trim voltage must track
the voltage on the trim pin. Input impedance of the trim pin
is about 100kn and attenuation to the output is 13:1. The
technique shown below is suggested for trimming the
output of the LT1236-5 while maintaining minimum shift
in output temperature coefficient. The R1/R2 ratio is
chosen to minimize interaction of trimming and TC shifts,
so the exact values shown should be used.

8-BIT

1""--

\.
\

\

r-....

l"- t--

~IT

12-BIT

-

""

~I

........

r-....

I"- r- I -

10 20 30 40 50 60 70 80 90 100
TEMPERATURE SPAN (OC)

'imming Output Voltage
Ie LT1236-1 0has atrim pin for adjusting output voltage.
Ie impedance of the trim pin is about 12kn with a
)minal open circuit voltage of 5V. It is designed to be
'iven from a source impedance of 3kQ or less to miniize changes in the LT1236 TC with output trimming.
tenuation between the trim pin and the output is 70:1.
lis allows ±70mV trim range when the trim pin is tied to
e wiper of a potentiometer connected between the
ltput and ground. A 10kn potentiometer is recomended, preferably a 20 turn cermet type with stable
laracteristics over time and temperature.
Ie LT1236-1 0 "A" version is pre-trimmed to ±5mV and
erefore can utilize a restricted trim range. A75k resistor

L7lJ!J~

Capacitive Loading and Transient Response
The LT1236 is stable with all capacitive loads, but for
optimum settling with load transients, output capacitance
should be under 1OOOpF. The output stage ofthe reference
is class AB with a fairly low idling current. This makes
transient response worse-case at light load currents.
Because of internal current drain on the output, actual
worst-case occurs at ILOAD = 0 on LT1236-5 and ILOAD =
1.4mA (sinking) on LT1236-1 O. Significantly better load
transient response is obtained by moving slightly away
from these paints. See Load Transient Response curves
for details. In general, best transient response is obtained
when the output is sourcing current. In critical applications, a 10J,lf solid tantalum capacitor with several ohms
in series provides optimum output bypass.

7-11

LT1236
APPLICATions InFoRmATion
Kelvin Connections
Although the LT1236 does. not have true force/sense
capability at its outputs, significant improvements in ground
loop and line loss problems can be achieved with proper
hook-up. In series mode operation, the ground pin of the
LT1236 carries only", 1mA and can be used as a sense
line, greatly reducing ground loop and loss problems on
the low side of the reference. The high side supplies load
current so line resistance must be kept low. Twelve feet of
#22 gauge hook-up wire or 1 foot of 0.025 inch printed
circuit trace will create 2mV loss at 1OmA output current.
This is equivalent to 1LSB in a 10V, 12-bit system.
The following circuits show proper hook-up to minimize
errors due to ground loops and line losses. Losses in the
output lead can be greatly reduced by adding a PNP boost
transistor if load currents are 5mA or higher. R2 can be
added to further reduce current in the output sense lead.

temperature gradients in the package leads. Variations ir
thermal resistance, caused by uneven air flow, creatE
differential lead temperatures, thereby causing thermo,
electric voltage noise at the output ofthe reference.
Standard Series Mode

KEEP THIS LINE RESISTANCE LOW
INPUT

~~~~~ ----------~
Series Mode with Boost Transistor

EHects of Air Movement on Low Frequency Noise
The LT1236 has very low noise because ofthe buried zener
used in its design. In the 0.1 Hzto 10Hz band, peak-to-peak
noise is about 0.5ppm of the DC output. To achieve this
low noise, however, care must be taken to shield the
. reference from ambient air turbulence. Air movement can
create noise because of thermoelectric differences between Ie package leads and printed circuit board materials
and/or sockets. Power dissipation in the reference, even
though it rarely exceeds 20mW, is enough to cause small

'OPTIONAL-REDUCES CURRENT IN OUTPUT SENSE
LEAD: R2 = 2.4k (LT1236-5). 5.6k (LT1236-10)

TYPICAL APPLICATiOnS
Restricted Trim Range for Improved
Resolution, 10V, "A" Version Only

LT1236-10 Full Trim Range (±O.7%)

Negative Series Reference
15V

~-""10.000V

--"'-VOUT

R2
-15V-+~...t
~

TRIM RANGE =±10mV

7-12

LT12S6TA,10

LT1236TA03

'CAN BE RAISED TO 20k FOR LESS
CRITICAL APPLICATIONS

2N2905

LT1236
rYPICAL APPLICATions
Boosted Output Current
with No Current Limit

Boosted Output Current
with Current Limit

'+" (VOUT+ 1.8V) - - - _ - - - - ,

±10V Output Reference

V+" VOUT + 2.8V .....- -.....- - - - ,

~

R1
220(1

R1
2200

8.20
+10V

10VAT
100mA

r - - -...- -.....-..-

COM

t------

-10V

10VAT
100mA

21'F
SOLID
TANT

21'F
SOLID
TANT

"GLOWS IN CURRENT LIMIT,
DO NOT OMIT
-15V

Handling Higher Load Currents

Operating 5V Reference from 5V Supply
r -____. -__________________

~~~~~C

CMOS LOGIC
5V
REFERENCE

"FOR HIGHER FREQUENCIES C1 AND C2 MAY BE DECREASED
""PARALLEL GATES FOR HIGHER REFERENCE CURRENT LOADING
"SELECT R1 TO DELIVER TYPICAL LOAD CURRENT.
LT1236 WILL THEN SOURCE OR SINK AS NECESSARY
TO MAINTAIN PROPER OUTPUT. DO NOT REMOVE LOAD
AS OUTPUT WILL BE DRIVEN UNREGULATED HIGH. LINE
REGULATION IS DEGRADED IN THIS APPLICATION

Trimming 10V Units to 10.24V
CMOS DAC with Low Drift Full-Scale Trimming""
R3
4.02K

1%

R4'

~----------------+< ~~~eSCALE
....---lREF

CMOS
DAC
LTC7543

ADJUST
10V
F.S.

4.32k -:L.-_ _

~5k

V-:-15V"

1.2k
-15V

"TC LESS THAN 200ppmrc
""NO ZERO ADJUST REQUIRED
WITH LT1007 (Vos'; 60I'V)

'MUST BE WELL REGULATED
t!"ooJ: _15mV
dV- - V

7-13

LT1236
TYPICAL APPLICATions
Negative Shunt Reference Driven
by Current Source

Strain Gauge Conditioner for 350(1 Bridge
R1
35m
112W

15V

VOUT
X100
2m

-11VTO-40V

"----------~ -5V

35m
1/2W
-15V
'THIS RESISTOR PROVIDES POSITIVE FEEDBACK TO
THE BRIDGE TO ELIMINATE LOADING EFFECT OF
THE AMPLIFIER. EFFECTIVE ZIN OF AMPLIFIER
STAGE IS:< 1Mn. IF R2 TO R5 ARE CHANGED.
SET R6= R3

"BRIDGE IS ULTRA-LINEAR WHEN ALL LEGS ARE
ACTIVE, TWO IN COMPRESSION AND TWO IN TENSION,
OR WHEN ONE SIDE IS ACTIVE WITH ONE COMPRESSED
AND ONE TENSIONED LEG
tOFFSET AND DRIFT OF LM301AARE VIRTUALLY
ELIMINATED BY DIFFERENTIAL CONNECTION OF LT1 012C
LTl236TAD6

2·Pole Lowpass Filtered Reference

Precision DAC Reference with System TC Trim

15V
8.87k
1%
50k
ROOM TEMP
TRIM
1.24k
1%
200k
1%

L--..Io,JIfv---.....-

'TRIMS 1mA REFERENCE CURRENT
TC BY ±40ppml°C. THIS TRIM
SCHEME HAS VERY LITTLE EFFECT ON ROOM
TEMPERATURE CURRENT TO MINIMIZE ITERATIVE
TRIMMING

7-14

- - - - - -....---~ -VREF

~

... 1mA

-

DAC

B.45k

LT1236
rYPICAl APPLICATions
Ultra-Linear Platinum Temperature Sensor"

20V
R2'
5k

R10
182k
1%

R1"
253k

R8

1~~~~1~0~M~+-____t-________________+-__~~~__--,

R3"
5k

,,

R4
4.75k
1%

~

,
,
,

~'>-I4

R7
392k
1%

Rst
,
1000ATI
O'C
,

,

----,

-15V

R5
200k
1%

R6
619k
1%

-15V
tSTANDARD INDUSTRIAL 1000 PLATINUM 4-WIRE SENSOR,
ROSEMOUNT 78S OR EQUIVALENT. Q( = 0.00385
TRIM R9 FOR VOUT = OV AT O'C
TRIM R12 FOR Voup 10V AT 100'C
TRIM R14 FOR VOUT = 5V AT 50'C
USE TRIM SEQUENCE AS SHOWN. TRIMS ARE NON INTERACTIVE
SO THAT ONLY ONE TRIM SEQUENCE IS NORMALLY REQUIRED.
"FEEDBACK LINEARIZES OUTPUT TO ± 0.005'C FROM
-50'C TO 150'C
"WIREWOUND RESISTORS WITH LOW TC

eQUIVALEnT SCHEmATIC
INPUT ....-------,

r-----------......---+-.....--+_ OUTPUT
03

R1

R2

~----------~~~~----~GND

L7lJ!J~

7-15

LT1236

RELATED PARTS
PART NUMBER
LT1019
LT1027

7-16

DESCRIPTION
Precision Bandgap Reference
Precision 5V Reference

COMMENTS
0.05%, 5ppm/°C
0.02%, 2ppm/oC

SECTion 8-monOLITHIC FILTERS

•
8-1

INDEX
SECTION 8-MONOLITHIC FILTERS
INDEX ........................................................................................................................................ 8-2
SELECTION GUiDES ....... ................................................................................................................. 8-3
PROPRIETARY PRODUCTS
LTC1164-8, Ultra-Selective, Low Power 8th Order Elliptic Bandpass Filter with Adjustable Gain ........................ 8-5

8-2

SWITCHED-CAPACITOR FILTERS
User Configured
Universal Filters

PreConfigured
Lowpass Filters

Very High Speed

5th Order DC Accurate
Butterworth

LTC1264 (200kHz, 4 Section)

High Speed/low Noise
LTC1064 (140kHz, 4 Section)

LTC1 062 (20kHz)
LTC1063 (50kHz, 1mV Vos Typ)

5th Order DC Accurate
Linear Phase
LTC1065 (60kHz, 1mVVos Typ)

Medium Speed
LTC1 059 (40kHz, 1 Section)
LTC1060 (20kHz, 2 Section)
LTC1061 (35kHz, 3 Section)

low Power/low Noise
LTC1164 (20kHz, 4 Section)

Semi-Custom/low Noise
LTC1064-XX (4 Section)
LTC1164-XX (4 Section)

8th Order 14-Bit DC
Accurate Elliptic/Linear Phase
LTC1066-1 (100kHz, ±1mV Vos Typ)

8th Order
Cauer/low Noise
LTC1064-1 (50kHz)
LTC 1064-4 (100kHz)
LTC1164-6 (20kHz, Low Power)

8th Order
Butterworth/low Noise
LTC1064-2 (Up to 140kHz)

8th Order Linear Phase
Bessel/low Noise
LTC1 064-3 (Up to 100kHz)

Bandpass Filters

8th Order Selectable
Butterworth/Linear Phase
LTC1164-5 (Up to 20kHz, Low Noise)

Ultra-Selective 8th Order
Elliptic w / Adjustable Gain
LTC1164-8 (Up to 7kHz)

8th Order Linear Phase
and Fast Rolloff
LTC1264-7 (Up to 200kHz, High Speed)
LTC1164-7 (Up to 20kHz, Low Power)
LTC1064-7 (Up to 100kHz, Low Noise)

8-3

ANALOG FILTER SELECTION GUIDE
Introduction

Features

The LTC family of switched-capacitor filters offers the system designer cost
effective and space saving alternatives to filter designs implemented with op
amps. Asingle IC filter can be used to replace multiple amplifiers and external
capacitors.

•
•
•
•
•
•
•

Since their center frequencies are set by a stable external clock, switchedcapacitor filters virtually eliminate the temperature drift problems associated
with active RC filter designs. This clock tuning also allows the adjustment of
corner frequency over a wide range (greater than 106:1 for the LTC1064
family), permitting one filter to do the job of multiple active RC filters.
LTC's filter offerings include Single, dual, triple, and quad block products and
range in performance from improved replacements forthe industry standard
MF5 and MF10, to state-of-the-art products such as the LTC1 064/1164/1264
families. The LTC1064/1164/1264 "Dash Series" products are one chip
solutions requiring no external components. Our semi-custom programs
offer an ASIC solution to high performance or higher volume system needs.

PART
NUMBER
LTC1059
LTC1060
LTC1061
LTC1062
LTC1063
LTC1064
LTC1064-1
LTC1064-2
LTC1064-3
LTC1064-4
LTC1064-7
LTC1064-XX
LTC1065
LTC1066-1
LTC1164
LTC1164-5
LTC1164-6
LTC1164-7
LTC1164-8
LTC1164-XX
LTC1264
LTC1264-7
LTCI264-XX

8-4

FILTER
ORDER
2
4
6
5
5
8
8
8
8
8
8
8
5
8
8
8
8
8
8
8
8
8
8

10 MAX
40kHz
20kHz
35kHz
20kHz
50kHz
140kHz
50kHz
140kHz
100kHz
100kHz
100kHz
to 140kHz
60kHz
100kHz
20kHz
20kHz
20kHz
20kHz
7kHz
to 20kHz
200kHz
200kHz
to 200kHz

fO/lCLK
100,50:1
100,50:1
100,50:1
100:1
100:1
100,50:1
100:1
100,50:1
150,75:1
100,50:1
100,50:1
100,50:1
100:1
100,50:1
100,50:1
100,50:1
100,50:1
100,50:1
100:1
100,50:1
20:1
50,25:1
50,25:1

TClo
5ppm/oC
10ppm/oC
lppm/oC
10ppm/oC
1ppml"C
1ppm/oC
1ppm/oC
1ppm/oC
1ppm/oC
1ppm/oC
1ppm/oC
1ppm/oC
1ppm/oC
lppm/oC
1ppm/oC
1ppm/oC
1ppm/oC
1ppm/oC
lppm/oC
lppm/oC
lppm/oC
lppm/oC
lppm/oC

SO
PKG
Y
Y
Y
Y
y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

Clock-Tunable Center Frequencies
Stable, Selectable Clock-to-Center Frequency Ratios
Center Frequencies to 200kHz
Noise Performance As Low As 80llVRMS
Available with Zero DC Offset
Filter CAD Program Available for Low-Effort DeSign
Available as Universal Filter Blocks, Dedicated Filters,
or Semi-Custom Fixed Filters
• Improved Replacements for Industry Standard MF5
and MF10
• Available in Surface Mount Packages

Applications
•
•
•
•
•
•

Anti-Aliasing Filters
Smoothing Filters
Telecom Filters
Spectral Analysis
Loop Filters
Audio

MIL TEMP
AVAIL
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
Y
Y
Y
Y

PIN
COUNT
14
20
20
8
8
24
14
14
14
14
14
14
8
18
24
14
14
14
14
14
24
14
14

FEATURES
Low NOise, Low Crosstalk, Universal Filter Block
Improved MF5 Replacement
Improved MF10 Replacement
Fifth Order Low Pass Filter, No DC Offset
Clock-Tunable DC Accurate Butterworth
Universal, Low Noise, Fast Quad Filter
Low Noise, Cauer Lowpass Filter
Low Noise, High Frequency Butterworth Lowpass Filter
Low Noise, Linear Phase Bessel Lowpass Filter
Low NOise, High Speed Cauer Lowpass Filter
Constant Group Delay, Lowpass Filter
Semi-Custom Low Noise, High Speed Filter
ClOCk-Tunable DC Accurate Bessel
14-Bit DC Accurate, Pin Selectable Cauer/Bessel
Universal, Low Noise, Low Power, Wide Dynamic Range Filter
Low Power, Butterworth/Bessel Lowpass Filter
Low Power, Elliptic Lowpass Filter
Constant Group Delay, Low Power, Lowpass Filter
Ultra-Selective Elliptic Bandpass Filter w/Adjustable Gain
Semi-Custom Low Noise, Low Power Filter
Very High Speed Universal Quad Filter
Constant Group Delay, High Speed, Lowpass Filter
Semi-Custom Very High Speed Filter

f~TLElcnHNt1\OI'O-G~~~--------_UC_ll_64_-8
~,
~
Ultra-Selective, Low Power
IT

8th Order Elliptic Bandpass Filter
with Adjustable Gain

FEATURES

DESCRIPTiOn

• Ultra-Selectivity
(50dB Attenuation at ±4% of Center Frequency)
• Adjustable Passband Gain
• Noise Independent of Gain
• Filter Noise: 270,.NRMS, Vs = Single SV Supply
• Clock-Tunable (Center Frequency =fCLK/1 00)
• Center Frequencies up to SkHz, Vs = ±SV
(TypicaiISuPPLY =3.2mA)
• Center Frequencies up to 4kHz, Vs =Single SV Supply
(TypicallsuPPLY = 2.3mA)

The LTC@1164-8 is amonolithic ultra-selective, 8th order,
elliptic bandpass filter. The passband of the LTC1164-8 is
tuned with an external clock and the clock-to-center frequency ratio is 100:1. The -3dB pass bandwidth is typically 1% of the filter center frequency. The stopband
attenuation of the LTC1164-8 is greater than SOdB. The
lower and upper stopband frequencies are less than 0.96
x center frequency and greater than 1.04 x center frequency, respectively.
The LTC1164-8 requires an external op amp and two
external resistors (see the circuit below). The filter's gain
at center frequency is set by the ratio RIN/RF. For a gain
equal to one and an optimum dynamic range, RF should be
set to 61.9k and RIN should be 340k. For gains other than
one, RIN = 340k/Gain. Gains up to 1000 are obtainable.
Setting the filter's gain with input resistor RIN does not
increase the filter's wideband noise. The 270llVRMS
wideband noise of the LTC1164-8 is independent of the
filter's center frequency.

APPLICATions
•
•
•
•

Asynchronous Narrowband Signal Detectors
Low Frequency Asynchronous Demodulators
Handheld Spectrum Analyzers
In-Band Tone Signaling Detectors

The LTC1164-8 is available in a 14-pin PDI P or a 16-pin
surface mount SO Wide package.
£T, LTC and LT are registered trademarks of linear Technology Corporation .

------------------------------------------------------TYPICAL APPLICATiOn

Frequency Response

Ultra-Narrow 1kHz Bandpass Filter with Gain = 10
Gain =340k/RIN, 1/(2lt x RF x CF);:: 10 x Center Frequency

30

20

t
I

11\
II \

10

o

50dB

iii -10

~ -20

''""' -30 .......
-40

VOUT

I
I

v"ll

-50

I
t

IV-

/'-

"

-60
- - - SHORT CONNECTION UNDER IC AND
SHIELDED BY A GROUND PLANE

-5V

LTC1164-a-TAQl

-70

0.90

0.95
1.00 1.05
FREQUENCY (kHz)

1.10

1.15

11~TA02

.L7lJ!J~

8-5

•

LTCl164-B
ABSOLUTE mAxmum RATinGS
Total Supply Voltage (V+ to V-) ........................... 16.5V
Power Dissipation ............................................. 700mW
Burn-In Voltage ................................................... 16.5V
Voltage at Any Input .... (V- - O.3V) :::; VIN :::; (V+ + O.3V)
Operating Temperature Range* .................. O°C to 70°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

Maximum Clock Frequency
Vs = ±7.5V .................................................... 720kHz
Vs = ±5V ....................................................... 540kHz
Vs = Single 5V ............................................... 430kHz
'For an extended operating temperature range contact LTC Marketing for
details.

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER

TOP VIEW

ORDER PART
NUMBER

TOP VIEW

LTC1164-8CN

N PACKAGE
1HEADPDIP

LTC1164-8CSW

SW PACKAGE
16-LEAD PLASTIC SO WIDE

TJMAX = 110'C, 6JA = 65'C/W

TJMAX = 110'C, 6JA = 85'C/W

Consult factory for Industrial and Military grade parts.

ELEORICAL CHARACTERISTICS

(See Test Circuit)
TA =25°C, Center Frequency =fClK/100, fClK =100kHz (the clock signal is a TTL or CMOS square wave, clock rise or fall time::;; 11JS),
the AC test signal level is 1VRMS for Vs =±5V or O.5VRMS for Vs =±2.375V, unless otherwise specified.
PARAMETER
Gain at Center Frequency

Gain at 0.995 x Center Frequency and
1.005 x Center Frequency
(Referenced to Gain at Center Frequency)

CONDITIONS

MIN

TYP

Vs =±2.375V

fiN = 1000Hz

Vs =±5V

fiN = 1000Hz

Vs =±2.375V

fiN = 995Hz

-3
-4
-3
-4
-8
-9
-8
-9

0±1.5
0±2.0
0±1.5
0±2.0
-3±2

fiN = 1005Hz
Vs =±5V

Lower Stopband Attenuation
(Referenced to Gain at Center Frequency)

Vs =±2.375V

Vs =±5V

8-6

fiN = 995Hz
fiN = 1005Hz
fiN = 960Hz (Note 1)
fiN = 800Hz
fiN = 960Hz (Note 1)
fiN = 800Hz

•
•
•
•
•

-48
-50
-48
-48

-3±2
-3±2
-3±2
-52
-52
-52
-52

MAX
3
4
3
4
-1
0
-1
0

-58
-60

UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

LTC 1164-8
ELECTRICAL CHARAOERISTICS
·A

(See Test Circuit)

=25°C, Center Frequency =fCLK/100, felK =100kHz ( the clock signal is a TTL or CMOS square wave, clock rise or fall time :::; 1/JS),

he AC test signal level is 1VRMS for Vs =±5V or O.5VRMS for Vs =±2.375V, unless otherwise specified.
'ARAMETER
Ipper Stopband Attenuation
Referenced to Gain at Center Frequency)

Vs =±2.375V

Output for < 0.25%
otal Harmonic Distortion
lutput DC Offset

MIN

TYP

-48
-50
-48

-52
-52

-48

-52
-52

fiN = 1200Hz

•

fiN = 1040Hz (Note 1)
fiN = 1200Hz

Vs =±5V
~aximum

CONDITIONS
fiN = 1040Hz (Note 1)

Vs = ±2.5V
fiN = 1000Hz
Vs = ±5V
fiN = 1000Hz
Vs = ±2.5V (At the Output of External Op Amp)
Vs =±5V
Vs = ±2.375V

'ower Supply Current (Note 2)

Vs =±5V
Vs =±7.5V
'ower Supply Range
he • denotes specifications which apply over the full operating
lmperature range.
lole 1: The minimum stopband attenuation at 960Hz and 1040Hz is
uaranteed by design and test correlation.

MAX

UNITS

-58
-60

dB
dB
dB
dB
dB

1.0
2.5
-40±50
-50±60

•
•
•

2.3
3.2
4.5
±2.375

4.0
4.5
7.0
8.0

VRMS
VRMS
mV
mV
mA
mA
mA
mA

11.0
12.5
±8

mA
mA
V

Nole 2: The maximum current over temperature is at O°C. At 70°C the
maximum current is less than its maximum value at 25°C.

rYPICAL PERFORmAnCE CHARACTERISTICS
Passband Variations
vs Power Supply

Gain vs Frequency
10

-10

TA = 25°C

fCLK = 100kHz
GAIN=1
RIN = 340k
Rf= 61.9k ~

Vs =±5V
lCLK = 100kHz

-3

-20
~

-30

~ -6

-40

,

, -50

~

-60
-70

~ -9

V' /

-12

I

-80
-90

z

760

880
1000
1120
FREQUENCY (Hz)

~V

~ 'f'

,-

--

Vs

=1±2.5~

~-~

VS=±5V~ ~
I

\

Vs=±7.5~\

\

1240

i"'-

-3

~ -6
z -9
:;;:
C!l -12

-24
995

1000
1005
FREQUENCY (Hz)

1010

I\,
\

/
/
/
984

"-

"- ...... 1\f.\..
992
1000
1008
FREQUENCY (Hz)

120
60

"0

\

"\

180

-60 ~
1);
-120 m

\

"\.

-15

-21

/

-

TA=25°C
Vs =±5V
fCLK = 100kHz

I)(

-18

-15
-18
990

•

Passband Gain and Phase
vs Frequency

-180.§
-240
-300
-360

-420

1016

LTC118H'TPC02

8-7

LTC 1164-8
TYPICAL PERFORmAnCE CHARAOERISTICS
Passband Gain and Delay
vs Frequency
TA =25°C
Vs =±5V
tCLK =100kHz

-\

V

-3

1/

~ -6

\

J

'" -9

0..
0..

'"
0..

I
3.0

3.5

lTC1164-S·TPC07

8-8

-68

r--+~++tttlH-----+-+++tfflt--l

0.01

0.1
INPUT VOLTAGE (VRMS)

Output vs Input

(/

k

III

~

I(J

2.0

~oC

tCLK = 100kHz
tCENTER = 1kHz
tiN = 1kHz
~

~

I

IVs JNGLE5V

r-- (PINS 3, 5 AT I~

~ -30
'" -40

I

1.0

I

>-10
OJ

iII -20

V

V

-50

o

'--

~

25°CP

3.0

o

AGND=2V

-62r--+~++~t-~~~~~-l

10

'"0:
~

r-...

8

0.1
INPUT VOLTAGE (VRMS)

'"~
:::>

T

-44 b-+-+-++tffiH--+-++++t+f+IJ--l

-80~~~~~~~~~~~~

-80
0.01

0:
0:

2.~

1.5
2.0
2.5
INPUT VOLTAGE (Vp.p)

~

~4~-+-r++~H--+-++++t+HI--l

~

'"

1.0

-68

w

0>

0.5

~ -38,- ~b~~~;~~N:J;1~N~t~OO~

~ -56
...,

<" 4.0
.§.

AGNDAT2V

-80

~ -32 r--

5.0

/

TA= 25°C
Vs = SINGLE 5V
tlN= 1kHz
tCLK = 100kHz

-

-74

10

r---r-~~~~~~~.-TT1'-----'

-26 f--

Power Supply Current
vs Power Supply Voltage

I

'"9 -70

-20

~ -50 f---'~'=I--!-+++f-Ht--lJ~G~N~ ~ ~15V r-

~ -56
t::-62

1016

V
IJ

I

'" -60

i5

-44

TA = 25°C
I- Vs =±5V
I- tiN = 1kHz
tCLK = 100kHz
I- FILTER GAIN AT tCENTER = 1 OUTPUT OP AMP IS LT1 006

i5
'"
-50
+

THD + Noise vs Input Voltage
-40

THI) + Noise vs Input Voltage

THD + Noise vs Input Voltage
100

L
0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0
POWER SUPPLY VOLTAGE
OR Vl

tv+

LTC1164·8·TPCOB

~

.#

-60
-60 -50

1/

/

L

A
Vs=±5V

-40 -30 -20 -10
INPUT LEVEL (dBV)

10

LTC 1164-8

Pin FunCTions

(14-Lead PDlP)

V+, V- (Pins 4,12): Power Supply Pins. The V+ (pin 4)
and the V- (pin 12) should be bypassed with a 0.1 ~
capacitor to a reliable ground plane. The filter's power
supplies should be isolated from other digital or high
voltage analog supplies. A low noise linear supply is
recommended. Using a switching power supply will
lower the signal-to-noise ratio of the filter. The power
supply during power-up should have a slew rate of less
than 1Vlj.lS.

power supply for the clock source should not be the filter's
power supply. The analog ground for the filter should be
connected to the clock's ground at a single point only.
Table 1 shows the clock's low and high level threshold
values for dual or single supply operation. Apulse generator can be used as a clock source provided the high level
on-time is at least 1j.lS. Sine waves are not recommended
for clock input frequencies less than 100kHz. The clock's
rise or fall time should be equal to or less than 1j.lS.

For dual supply operation ifthe V+ supply is applied before
the V- supply or the V- supply is applied before the V+
supply, a signal diode on each supply pin to ground will
prevent latch-up. Figures 1 and 2 show typical connections for dual and single supply operation.

Table 1. Clock Source High and Low Threshold Levels

fClK (Pin 11): Clock Input Pin. Any TTL or CMOS clock

source with a square wave output and 50% duty cycle
(±10%) is an adequate clock source for the device. The

---+....:.

5V _ _
'1N4148
OR EQUIVALENT

POWER SUPPLY

HIGH lEVEL

LOW LEVEL

Single Supply = 5V

>1.45V

7.80V

<6.5V

Dual Supply = ±2.5V

>O.73V

<-2.0V

Dual Supply = ±5V

>1.45V

2.18V

--"'NIr........--I

VOUT

-=

-.-0.1~F

-5V

VOUT = AVERAGE OF ASS [VPEAK x SIN (21t x fCENTER x t)l, ±10% FROM tvp.p TO 7Vp.p
RIN =340klGAIN; fCENTER =fCLK/100; 1/(21t x Rr x Cr) ~ 10 x fCENTER
1/(21t x Rl xCI) ~ fCENTER/l 0; 1/(21t x R2 x C2) ~ fCENTER/25; R2 x C2 = R3 x C3

LTC1164·S·TA03

8-13

LTC 1164-8
TYPICAL APPLICATions
Tone Detector-Detecting a Low Level Signal Buried in Wideband Noise
tCLI<

FOR OPTIMUM TONE DETECTION, THE SIGNAL'S FREQUENCY SHOULD BE IN THE
FILTER'S PASSBANO AND WITHIN ±0.1% FROM tCENTER.
AT VOUT, LOGIC HIGH =SIGNAL AT VIN, LOGIC LOW =NO SIGNAL ATVIN.
THE MINIMUM DETECTABLE SIGNAL ATVIN: VIN(MIN) = 200mVRMS/GAIN.
THE MAXIMUM NOISE SPECTRAL DENSITY AT VIN: VIN = 32mVRMsI[GAIN x 'i'\BWliJ
WHERE: (BW}j = 0.01 x tCENTER AND IS THE NOISE EQUIVALENT BANDWIDTH
OF THE FILTER
GAIN = 340klRIN AND IS THE FILTER GAIN AT/CENTER
RIN =340klGAIN; tCENTER =tCLK/l00; 1/(21< x RF x CF) ~ 10 x teENTER
1/(2" x Rl xCI) "tCENTEWl 0; 1/(21< x R3 x C2) "tCENTER/32

>-+",-+-VOUT
R3
10k

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC1064

Universal Filter Building Block

This Part, with External Resistors, Allows Design of Bandpass
Filters Similar to LTC1164-8 (Up to 50kHz)

LTC1164

Universal Filter Building Block

This Part, with External Resistors, Allows Design of Bandpass
Filters Similar to LTC1164-8 (Low Power Up to 20kHz)

LTC1264

Universal Filter Building Block

This Part, with External Resistors, Allows Design of Bandpass
Filters Similar to LTC1164-8 (Up to 100kHz)

See Table 4 for additional information

8-14

SECTion 9-mICROPROCESSOR
SUPERVISORY
CIRCUITS

9-1

INDEX
SECTION· 9-MICROPROCESSOR SUPERVISORY CIRCUITS
INDEX ........................................................................................................................................ 9-2
SELECTION GUIDE ......................................................................................................................... 9-3
PROPRIETARY PRODUCTS
LTC690lL TC6911L TC6941L TC695, Microprocessor Supervisory Circuits ......................................................... '920B
9-4
LTC6921L TC693, Microprocessor Supervisory Circuits ..................................................................................... '940B
9-4
LTC694-3.3IL TC695-3.3, 3.3V Microprocessor Supervisory Circuits ................................................................ '940B 9-19
LTC699, Microprocessor Supervisory Circuit ................................................................................................... '920B 9-18
LTC1232, Microprocessor Supervisory Circuit ................................................................................................. '920B 9-22
LTC1235, Microprocessor Supervisory Circuit with Conditional Battery Backup .............................................. '920B 9-29

9-2

MICROPROCESSOR SUPERVISORY CIRCUITS
LTC Family of Supervisory Circuit Products
1235

FUNCTION
Pushbutton Reset
Battery Backup Switching-UL Recognized
Conditional Battery Backup
RAM Write Protect
Watchdog Timer
Power Fail Warning
Power Up/Down Reset
ResetThreshold (V)
Reset Pulse Width (ms)
Guaranteed Vee Reset level (V)
Power Supply Current lilA)
Packages: Plastic
CERDIP
SO
Temperature Ranges
Noles: 1. 4.62V or 4.37V threshold selectable
2. 0.300' SO wide package

X
X
X
X
X
X
X

4.65
200
1.0
600
16
162
C

690

691

692

693

694/694-3.3

695/695-3.3

X

X

X

X

X

X

X
X
X

X
X
X
X

X
X
X
4.65/2.90
200
1.0
600
8
8
83
C, I

X
X
X
X
4.65/2.90
200
1.0
600
16
16
162
C, I

699

1232
X

4.65
50
1.0
600
8
8
83
C, I

4.65
50
1.0
600
16
16
162
C, I

X
X
X
X

X
X
X
4.40
200
1.0
600
8

4.40
200
1.0
600
16

83
C, I

162
C.I

X

X

X
4.65
200
1.0
600

4.62 1
610
1.0
500

8

8

83
C

83
C

X

3. 0.150" SO narrow package
4. Temperalure ranges: C= O°C to 7IfC I =-40°C to 85°C M = -55'C to 125'C

Definitions of Functions
Pushbutton Reset: Provides a manual reset input, usually triggered by a
pushbutton switch, which is debounced and will initiate the usual reset
sequence.
Battery Backup Switching: When Vcc drops below the battery voltage, VOUT
is connected to VBATI and the device is placed in standby mode to conserve
power. This provides backup power to the CMOS RAM while consuming less
than lIlA of supply current. LTC devices are UL recognized for lithium
battery backup.
Conditional Battery Backup: Electrically disconnects the battery during
shipment and storage to prevent unnecessary discharge. Disconnection is
done by detecting the power down sequencing of the supply and battery
inputs.
RAM Write Protect: The system RAM enable line is gated by the supervisory
circuit. When the supply voltage drops below the reset voltage threshold,

the enable line is inhibited, preventing erroneous data from being written
into the RAM when Vee is at an invalid level. The maximum enable delay for
LTC's supervisors is 45ns.
Watchdog Timer: Monitors the activity of the IlP. The processor must
toggle this input line before the given timeout period expires, or a reset will
be initiated. This function is intended to prevent IlP'S from becoming
accidentally stalled in microcode loops indefinitely.
Power Fail Warning: Provides early warning to the IlP of an impending
power failure by monitoring the unregulated power supply. This gives the
processor time to perform shutdown activities before all regulated power
is lost.
Power Up/Down Reset: Resets the IlP when the power supply line drops
below the preset threshold. LTC's supervisors will hold the reset line low
down to supply voltages of I.OV, providing a reliable reset through Vee
voltages which may allow the processor to begin operation.

Pin Configurations
TOP VIEW

TOP VIEW
VBATT

1

VOUT

Vee
GND

4

BATION
LOW LINE

J PACKAGE
16-LEAD CERDIP

LDWlINE

6

OSC IN

7

J PACKAGE
N PACKAGE
l6-LEAD CERDIP
l6-LEAD PDIP
SWPACKAGE
l6-LEAD PLASTIC SO WIDE

N PACKAGE
l6-LEAD PDIP
TOP VIEW

TDPVIEW

J8 PACKAGE
N8 PACKAGE
8-LEAD CERDIP
8-LEAD PDlP
S8 PACKAGE
8-LEAD PLASTIC SO

S8 PACKAGE
HEAD PLASTIC SO

N8 PACKAGE
8-LEAD PDIP
58 PACKAGE
HEAD PLASTIC SO

9-3

NOTES

9-4

SECTion lo-comPARATORS

10-1

INDEX
SECTION1o-COMPARATORS
INDEX .•••...•.•..•.••..•.••..•••..••...••.•••.••.••...••••..•••....••.••••••••••..•••••.•••••.••••••••••••••••••••••••••• , •.••••..••••.••• 10-1
SELECTION GUIDE ••..••...•..•...•...••..•...•.•••....•...•••...••...•.•...•.••..•••..•••••.•..•••••....•••.•.•••.•••.••.••••••••••.•••. 10-2
PROPRIETARY PRODUCTS
LTC1443/LTC1444/LTC1445, Low Power Quad Comparators ..••••••••••..•••••..•••...•••.•••..•••••..•••••.••••.•.•••••• 13-108

10-2

COMPARATOR SELECTION GUIDE
Comparators
Response
Time

Vos (MAX)
20mV

10mV

3mV

2.5mV

2mV 1.5mV

1mV

TTL
ECL
O.5mV OUTPUTS OUTPUTS

QUAD

LTC1040

IOOIJS

DUAL

GROUND
SENSE

MICROPOWER

ADDITIONAL
COMMENTS

LTC1040

LTC1040

LTC1040

Sampling: Consumes
1.51'Wat 1 Sample/Sec.

LTC1041

LTC1041

Bang-Bang Controller:
1.51'Wat 1 SamplelSec.

LTC1042

LTC1042

Sampling Window Comp.:
1.5!NV at 1 Sample/Sec.

LT1017

LT1017

601lA Max. Icc/Operates
to 1.1V

LTC1041
LTC1042
LT1017

151JS
LTCI443/4/5

121JS

m018

250ns

LTtOl!

m018

m018

250!lA Max. Icc/Operates
tol.tv
12-Bit Accurate

m015
LT1116

High Speed 2-Channel
Line Receiver

m015

Ground Sense/Single Supply

m116

LT1116
m016

6.5n8

m018

mOI1A

LT1015

12ns

LTCI443/4/5 LTCI443/4/5 Built-In Reference.
8.51lA Supply Current

LTCI443/4/5

41JS

14ns

LT1017

No Min. Input Slew Rate
RequirementiLatched Output

m016
LT685

LT685

Latched Outputs

LT1017 Provides Lower Power Operation than CMOS

as Input Frequency Increases
10000

'~1
z

/
V

1000

"":to
'"

'"
'"'"
:::>
'"

- --

CMOS COMPARATOY

W

0..

>~

100

10
0.001

0.01

LT1017

0.1

10

100

FREQUENCY (kHz)
tOUTPUTS UNLOADED. TA = 25'C

LTICVoltaga-TA02

LT1016 Doesn't Oscillate with Slowly Changing Input Signals
V+

THRESHOLD VOLTAGE (VTH)

(VTH)

-7""7'''~'''---='''~;;::--7'''~'''---"'''''"""",,"-o;;:-­
SLOWLY CHANGING
INPUT SIGNAL

CLEAN, SQUARED UP OUTPUT
SIGNAL WITH NO OSCILLATIONS
LTIC Voltage oTAOl

10-3

NOTES

10-4

SECTion ll-SPECIAl FunCTion

m

11-1

INDEX
SECTION 11-SPECIAL FUNCTIONS
INDEX ....................................................................................................................................... 11-2
SELECTION GUIDE ................................................................•....................................................... 11-3
PROPRIETARY PRODUCTS
LTK001, Thermocouple Cold Junction Compensator and Matched Amplifier .................................................... '900B 11-3
LTC201A!LTC202JLTC203, Micropower, Low Charge Injection, Quad CMOS Analog Switches ......................... '920B 11-4
LTC2211L TC222, Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches ........... '920B 11-15
Ln 025, Micropower Thermocouple Cold Junction Compensator ..................................................................... '90DB 11-7
LTC1043, Dual Precision Instrumentation Switched Capacitor Building Block .................................................. '90DB 11-15
LTC1043CS, Dual Precision Instrumentation Switched Capacitor Building Block .............................................. '90DB 11-31
Lnoaa, Wideband RMS-DC Converter Building Block ...................................................................................... '90DB 11-33

11-2

SPECIAL FUNCTIONS
Analog Switches
Family Features
• Micropower: 40J,lA Max Supply Current
• Single 5V or ±15V Operation
• apc Charge Injection
• Low ON Resistance
• Low Leakage
• Guaranteed Break Before Make
MAX INPUT
PART
NUMBER
LTC201A

NUMBER OF
CHANNELS
4

LTC202

4

LTC203
LTC221
LTC222

4
4
4

LATCHED
INPUTS

MAXON
RESISTANCE
125n

AND OUTPUT
OFF LEAKAGE
5nA

MAX
SUPPLY
CURRENT
40!lA

400nsl300ns

125n

5nA

40!lA

400nsl300ns

125n
900
90n

5nA
5nA
5nA

40(.lA
40(.lA
40(.lA

400nsl300ns
400ns/300ns
400ns/300ns

X
X

MAX

TONfTOFF

FEATURES
Lower ON Resistance, Charge Injection, Supply Current
Than DG201A. Single 5V to ±15V Supply Operation
Lower ON Resistance, Charge Injection, Supply Current
Than DG202. Single 5V to ±15V Supply Operation
Low ON Resistance, Charge Injection, Supply Current
Lower Charge Injection, Supply Current Than DG221
Lower Charge Injection, Supply Current Than DG222

Other Products
PART NUMBER
LF198(A)/LF398(A)
LM134/LM334

DESCRIPTION
Sample-and-Hold Amplifier
Adiustable Current Source

PACKAGE
OPTIONS
H, J8, N8, S
H,Z,S8

LT1025

Thermocouple Cold Junction Compensator

J8, N8

LT1088

RMS to DC Converter

D, N

LTC1043

Precision Switched-Capacitor Building Block

D, N, S

LTK001

Thermocouple Cold Junction Compensator
Matched Amplifier

J, N

FEATURES
12-Bit Accurate (LF198A), 61JS Acquisition Time, 0.005% Max Gain Error.
1(.IA to 1OmA Adjustment Range, Floating Current Source, 0.02%N
Regulation, Can Be Used as Temperature Sensor.
Provides O'C Cold Junction Compensation of Types E, J, K, R, S, T
Thermocouples. Low Supply Current (80(.IA) and Operates with Single 4V
to 36V DC Supply.
Thermal RMS to DC Conversion Permits 1% Accuracy to 50MHz, 2% to
1OOMHz and Handles Crest Factor up to 50:1.
120dB CMRR, when Used as Instrumentation Front End, Allows SwitchedCapacitor Design Techniques at Board Level.
LT1 025 with Matched Amplifier (LTKAOO or LTKA01) Provides Lower Error
Specs than Using Worst Case Errors of LT1 025 and Standard Precision Op
Amp.

111

11-3

NOTES

11-4

SECTion 12-mllITARY PRODUCTS

12-1

INDEX
SECTION 12-MILITARY PRODUCTS
INDEX ....................................................................................................................................... 12-2
MILITARY PRODUCTS/PROGRAMS ..................................................................................................... 12-3
JAN ...................................................................................................................................... 12-3
MIL-M-38510 Class B Flow (Figure 1) .......................................................................................... 12-4
MIL-M-38510 Class S Flow (Figure 2) .......................................................................................... 12-5
Standard Military Drawings .......................................................................................................... 12-4
SMD Preparation Flowchart (Figure 3) ......................................................................................... 12-6
SMDs Get a New Part Numbering System ......................................................................................... 12-6
MIL-STD·883 Product ................................................................................................................. 12-7
883 Group A Sampling Plan (Table 1) .......................................................................................... 12-7
Hi-Rei (SCDs) .......................................................................................................................... 12-7
Radiation Hardness Program ........................................................................................................12-7
Representative "RH" Product Manufacturing Flow (Figure 4) ............................................................. 12-8
Military Market Commitment ........................................................................................................ 12-7
883 Certificate of Conformance ..................................................................................................... 12-9
MIL-STD-883 Test Methods ........................................................................................................ 12-10
Military Parts List ................................................................................................................... 12-14

.---------NOTE----------,
Military product data sheets are available from your local LTC
Sales Representative, or by calling LTC Communications at
(800) 637-5545.

12-2

f~Llnet\12

~,

MILITARY PRODUCTS

TECHNOLOG~IY------

LINEAR TECHNOLOGY MILITARY PRODUCTS/
PROGRAMS
Linear Technology Corporation (LTC) offers a comprehensive range of high performance analog/linear
integrated circuits including; Data Converters, Interface
devices, High Speed Amplifiers, Precision Operational
I\mplifiers, Comparators, Voltage References, DC-DC
Converters, Switches, Voltage Regulators, Switching
Regulators, PWMs, and other special function products
serving the rigorous demands of the military marketplace.
fhe Company's specification system, quality procedures
md policies were set up from the beginning to meet the
~xacting demands of MIL-Q-9858 (Quality Program
Requirements), MIL-I-45208 (Inspection System
Requirements), MIL-M-38510 (General Specification for
Microcircuits), MIL-STD-976 (Certification Requirements
lor Microcircuits), MIL-STD-883 (Test Methods and
Procedures for Microelectronics) and more recently the
ISO 9000 (Internal Standards for Quality Management).
In addition, the Company has introduced aline of radiation
:olerant devices which are offered with two different inlouse levels of enhanced reliability processing to serve
Jround, air and/or space applications, including customer
Jenerated Source Controlled Drawings (SCDs) for avarilty of missions.
_TC's military programs include:
• JAN Class S
• JAN Class B
• Standard Military Drawings (SMDs)
• 883
• Hi-Rei (SCDs)
• LTC "RH", Radiation hardened devices

L7lJD~

LTC JAN
At the end of 1969, the Solid State Applications Branch of
the Rome Air Development Center (RADC) issued the first
copy of MIL-M-38510. This general specification
for microcircuits established the procedures that a
manufacturer must follow to have products listed on the
Qualified Parts List (QPL).
One major problem faced by defense contractors using
semiconductor devices was the inability to interchange
devices caused by aproliferation of non-standard electrical
specifications. The 38510 (JAN) program addressed this
problem by publishing detailed electrical specifications
(slash sheets) for each componentto be listed on the QPL.
JAN devices are completely processed in the United States
or its territories and all wafer fabrication, wafer sort,
assembly, testing, and conformance testing are performed
onshore.
In August 1984, LTC was visited by a team of Defense
Electronics Supply Center (DESC) personnel. This team
spent almost four days auditing LTC and at the end of the
visit they awarded the Company "Class B Line Certification." This was a first for any company to receive this
distinction on their first audit!
In early 1985, LTC joined the ranks of the eighteen
existing QPL suppliers. Of these eighteen, only a handful
of suppliers partiCipate in the linear military JAN market.
LTC believes its analog design experience and manufacturing strength has and will continue to make significant . . " .
contributions to this market.
...
LTC's first QPL listing was achieved in February 1985, one
year after the Company made JAN Class B a corporate

12-3

MILITARY PRODUCTS
goal. Other companies have typically taken 2to 3years to
achieve this status. The line certification and QPL approvals were awarded to MIL-M-38510 and MIL-STD-883
specifications. Since that time the Company has been reaudited to the latest revisions of these specifications and
has maintained an uninterrupted certification record for
the manufacture of JAN QPL products.

products listed on the Class BQualified Parts List (Part 1)
and 40 products on the Class S Qualified Parts List
(Part 1). To receive an updated copy ofLTC's current JAN
QPL product offering, contact your local LTC sales office
or LTC Military Marketing.

In November 1987, LTC was audited by ateam from DESC,
Naval Weapons Support Center and Aerospace Corporation and was awarded "Class S Line Certification."

In June 1994, LTC was granted transitional Qualified
Manufacturers List (QML) certification to MIL-1-38535 by
DESC, and will be pursuing full QML certification.

LTC's policy of providing JAN linear components supports
the United States Government's position of standardization
to decrease the number of active part types maintained by
DESC. This number is currently in excess of 85,000 for all
types of components (contrasted to approximately 8,000
industry standard components). Standardization will clearly
decrease costs and assist in the maintenance of military
weapons systems and equipment now in the field.

LTC Standard Military Drawings

LTC maintains its JAN product offerings under the current
revision of MIL-1-38535, Appendix A. LTC now offers 45

PRESEAL INTERNAL
VISUAL MIL-STD-883,
METHOD 2010
CONDITION B 100%

25°C ELECTRICAL TEST
100%

100%

..
.

BURN-IN
160 HOURS AT 12SoC
(OR EQUIVALENT)
100%

I

STABILIZATION BAKE
MIL-STD-883, METHOD
1008 CONDITION C
100%
I
TEMPERATURE CYCLING
Mll-STD-883, METHOD
1010 CONDITION C
100%

DESC drawings were initiated in 1976 to standardize the
electrical requirements for full temperature-tested military components. These DESC drawings (or minispecs)
were initially issued for low power Schottky devices (54LS)
used by defense subcontractors on the Air Force's F16.
The program accomplished standardization of testing,
without the delays associated with the qualification process for JAN components.

CONSTANT ACCELERATION
MIL-STD-883.
METHOD 2001 (Yl ONLy)
CONDITION E 100%

WAFER FABRICATION AND
DEVICE ASSEMBLY

SEAL

For JAN Flows See Figure 1 and Figure 2.

.

ELECTRICAL TEST
2SoC, 12SoC, -SsoC
100% PER APPLICABLE
MIL-M-38S10 SLASH SHEET
MARK

GROSS LEAK TEST
MIL-STD-883.
METHOD 1014
CONDITIONC
100%
GROUP A, ACCEPTANCE
MIL-STD-883, METHOD
S005TABLE 1, PER
APPLICABLE MIL-M-38S1 0
SLASH SHEET
EXTERNAL VISUAL
MIL-STD-883,
METHOD 2009
100%

100%

I
SOLDERDIP IF APPLICABLE
100%

'LTC IMPOSED
"TO-3 DEVICES AT CONDITION D. 20Kg MAX.

FINE LEAK TEST
MIL-STD-883.
METHOD 1014
CONDITION A 100%

ELECTRICAL
100%

LOT QUALIFICATION
(QCI) MIL-STD-883.
METHOD500S
GROUP B.C, AND D
GROUP B PERFORMED ON EACH LOT
BOX STOCK
UlI..-8TD·01

Figure 1. MIL-M-38510 Class B Flow

12-4

MILITARY PRODUCTS
WAFER FABRICATION AND
DEVICE ASSEMBLY
WAFER LOT ACCEPTANCE
MIL-STD-883,
METHOD 5007
NON-DESTRUCTIVE BOND
PULL MIL -STD-883,
METHOD 2023
100%
PRE SEAL INTERNAL
VISUAL MIL-STD-883,
METHOD 2010
CONDITION A 100%
SEAL MONITOR PER MIL-STD-976

I
REVERSE BIAS BURN-IN 72 HOURS
AT 150"C STATIC
PER APPLICABLE
MIL-M-3851 0 SLASH
SHEET
100%

CONSTANT ACCELERATION
MIL-STD-883,
METHOD 2001 (Yl ONLY)
CONDITIONE
(T0-3 PACKAGE CONDITION D)
100%

125"C, -55"C AND AC
TESTING PER APPLICABLE
DEVICE SPECIFICATION
100%
TOP MARK

I

GROUP A, ACCEPTANCE
MIL-STO-883, METHOD
5005 TABLE 1, PER
APPLICABLE DEVICE
SPECIFICATION
100%

..

FINE LEAK TEST
MIL-STD-883,
METHOD 1014
CONDITION A 100%

I
BURN-IN DYNAMIC
240 HOURS AT 125"C
(OR EQUIVALENT)
PER APPLICABLE MIL-M-38510
SLASH SHEET
100%
I
25"C ELECTRICAL TEST
READ AND RECORD PER
APPLICABLE DEVICE
SPECIFICATION
100%

SERIALIZATION

.

25"C ELECTRICAL TEST
100%

TEMPERATURE CYCLING
MIL-STD-883, METHOD
1010 CONDITION C
100%

PARTICLE IMPACT NOISE DETECTION
(PIND) MIL-STD-883, METHOD 2020
CONDITION A 100%

ELECTRICAL 3RD ROOM
25"C PER APPLICABLE DEVICE
SPECIFICATION
100%

25"C ELECTRICAL TEST
100%

.
..
..

GROSS LEAK TEST
MIL-STD-883,
METHOD 1014
CONDITIONC
100%
EXTERNAL VISUAL
MIL-STD-883,
METHOD 2009
100%
QUALITY CONFORMANCE
INSPECTION PER
MIL-STD-883, METHOD 5005
GROUP BAND D
TEST FOR ClASS S

100%
BOX STOCK

SOLDER DIP IF APPLICABLE
100%

100%

SHIP TO CUSTOMER
Mll·Sro-02

X-RAY MIL-STD-883,
METHOD 2012 (2 VIEWS)
100%

• IN THE CASE WHERE THERE IS NO APPLICABLE MIL-M38510 SLASH SHEET, THE BURN-IN SCHEMATIC AS WELL AS THE APPLICABILITY OF 100%
DYNAMIC BURN-IN SHALL BE NEGOTIATED BETWEEN THE CUSTOMER AND LINEAR TECHNOLOGY CORPORATION •
•• APPLICABLE DEVICE SPECIFICATION SHALL BE THE MIL-M38510 DEVICE SPECIFICATION, OR A DEVICE SPECIFICATION AGREED UPON BETWEEN
THE CUSTOMER AND LINEAR TECHNOLOGY CORPORATION .
• CUSTOMER SOURCE INSPECTION WILL BE ADDED AS SPECIFIED IN CUSTOMER'S PURCHASE ORDER.

Figure 2. MIL-M-3851D Class S Flow

The DESC drawing was viewed as apreliminary specification priorto JAN approval, and it ranks second in the order
of purchasing hierarchy to JAN. This order is defined in
Requirement 64 of MIL-STD-454.lf aJAN part is available,
it is still preferred, however, there are many types of
devices where the volume is such thatthe cost of afull JAN
qualification may not be justified, but where a need exists
for electrical standardization.
CMOS and analog circuits were added to the DESC Drawing Program in 1977, 1978 and 1979, but widespread

acceptance of these parts was not achieved. Today with
more emphasis being placed on standardization, the interest level in DESC drawings has accelerated. This category
of product can be built offshore with 883-level processing . " .
and the electrical parameters are tested specifically to the . . .
DESC drawing.
To provide parts to a DESC drawing, a manufacturer has
to have at least one part on the 38510 QPL. He must also
provide DESC with acertificate of compliance agreeing to
the tests and conditions listed on the drawing.

12-5

MILITARY PRODUCTS
CONTRACTOR INCORPORATES CHANGES
AND SENDS DRAFT WITH COF CTO
DEVICE MANUFACTURERS

CONTRACTOR SUBMITS 5962 PART
REQUESTTO DESC MPCAG

CONTRACTOR RETURNS REVISED DRAFT
PACKAGE TO DESC
CONTRACTOR DRAWING IN
ACCORDANCE WITH CONTRACT

DEVICE MANUFACTURER SENDS COMMENTS
REGARDING DRAFT TO CONTRACTOR
AND COPIES TO DESC

CONTRACTOR/MANUFACTURER PREPARES
PRELIMINARY DRAFT

DEVICE, CONTRACTOR, AND DEVICE
MANUFACTURERS RESOLVE COMMENTS
AND SEND THE COF CTO CONTRACTOR
AND DESC'

CONTRACTOR/MANUFACTURER SUBMITS
PRELIMINARY DRAFT TO DESC

DESC PREPARES, APPROVES AND
DATES FINAL MIL DRAWING

DESC REVIEWS PRELIMINARY DRAFT
AND PROVIDES RECOMMENDED CHANGES

ADVANCE COPIES SENT TO CONTRACTOR
AND DEVICE MANUFACTURERS

CONTRACTORIMANUFACTURER, DESC
RESOLVE COMMENTS

MIL DRAWING IS REPRODUCED AND
DISTRIBUTED BY DESC
'CONTRACTOR SHALL ALSO SUBMIT A LIST
OF ALTERNATE SOURCES TO DESC-ECS
ATTIME OF SUBMISSION OF COF C

Figure 3. SMD Preparation Flowchart

In 1986a new program named Standard Military Drawings
(SMDs) was launched by DESC. This replaced the previous DESC Drawing Program, This new program is aimed
directly at standardizing electrical requirements with the
objective to decrease the time required to issue a military
drawing. To achieve this, we have set up a computer
link-up with the DESC Standardized Mil Drawing Group.
LTC is actively supporting this Standard Military Drawing
program and we are working closely with DESC and OEMs
to participate in this government plan toward a greater
level of standardization in military specifications.
LTC has over 134 devices listed on DESC and Mil drawings, and we are actively supporting these standardization
programs by having parts available off the shelf from LTC
and from distribution outlets.
For SMD Flow see Figure 3,
SMDs Get A New Part Numbering System
A new numbering system has beervintroduced to standardize the part numbering system for JAN 38510 and
SMD (Standard Military Drawing) products.

12-6

Under the new system, the SMD number 5962XXXXXZZuyy will be used, with a minor change for the
38510 qual'd devices. This will make one part have one
part number with just the grade identification being
different (M =SMD, B=JAN Band S=JAN S). An example
of this follows:
Old System
LTC PART NUMBER
LT1 021 CMH-5/883

"OLD" SMD NO.
5962-8876202GA

JAN PART NUMBER
JM38510/12407BGA

New System
LTC PART NUMBER

"NEW" SMD ONE PART NUMBER SYSTEM

LT1 021 CMH-5/883

5962-8876202(M, B or S)GA

This was implemented on January 1, 1990, for all SMDs
and slash sheets created after this date, Devices listed or
approved in the past will retain their respective existing
part numbers.

MILITARY PRODUCTS
LTC MIL-STD-883 Product

LTC Hi-Rei (SCDs)

The semiconductor industry 883 designation on military
semiconductor components established a defacto standard in response to asignificant demand from the military
defense contractors. The Government recognized the
existence of 883 components in the recent revisions of
MIL-STD-883. Requirements for compliant 883 components are now defined very specifically in paragraph 1.2.1
of this document.

LTC recognizes the need for Source Controlled Drawings
(SCDs) and the Company's DESC-certified line is well
equipped to handle these requirements for space and
hi-rei applications. The Company has a comprehensive
specification review procedure and emphasis is placed on
compliance to test methods and procedures. Over 8,000
specifications have been reviewed to date with fast feedback to our customers.

MIL-STD-883 is atest procedures and methods document
which is revised periodically and defines the conditions
for two categories of product, Class Band Class S. Class
Bis intended for applications where maintenance is difficult
or expensive and where reliability is vital. Class S is
intended for space and critical applications where
replacement is extremely difficult or impossible and where
reliability is imperative.

LTC has serviced SCD orders including "s" level specifications with an emphasis on compliance with customer
purchase order requirements and on-time delivery performance. A dedicated SL traveller is initiated to baseline
the manufacturing and test flow requirements to service
each order.

On December 31, 1984, a key clause was added to MIL5TD-883, "paragraph 1.2.1." This states that if amanufacturer advertises, certifies, or marks parts as compliant
with MIL-STD-883 those parts must meet all of the provisions of MIL-STD-883, apractice consistent with "Truth in
~dvertising."
~ccording to the Defense Electronics Supply Center (a
Jranch of the Defense Department's Logistics Agency),
!he intent of paragraph 1.2.1 was to link MIL-STD-883
Nith the controls and details contained in MIL-M-38510,
md, by extension, MIL-I-38535, Appendix A.

l TC can state that all of its 883 products are in full
~ompliance with the latest revision of MIL -STD-883. We
lave over 333 versions of our 883 products listed in our
:urrent catalog, including operational amplifiers, voltage
'egulators, voltage references, comparators, and our adlanced line of proprietary CMOS circuits.
rable 1. LTC 883 Group A Sampling Plan

AC Parametric

CONDITION
TA =25°C
TA =-55°C
+125°C
TA =25°C

.L7lJD~

SAMPLE SIZE
116
116
116
116

LTC's Radiation Hardness Program
LTC has developed a proprietary design/wafer fabrication
process for RAD HARD (RH prefix) products, complemented by aseparate set of RH data sheets. Each RH data
sheet specifies the end pOint electrical test requirements
for Total Dose irradiation testing performed on a sample
basis. We offer in certain cases, the option of using
the slash sheet electricals for the pre-radiation test
limits instead of the LTC RH data sheet electricals. But in
all cases the post-radiation electricals are per LTC's RH
data sheets.
Due to the unique wafer processing required to make RH
products, the RH products are not totally compliant with
all the Class Srequirements of MIL-STD-883. Since MILSTD-883 specifically prohibits the marking of noncompliant products with the 883 compliance (c) indicator,
LTC's RH products are marked with the LTC RH prefix part
number or with a special mark specified by the customer. •
Military Market Commitment

883
TEST
DC Parametric
DC Parametric

LTC's Product Marketing Group can provide you with
more details on a case-by-case basis.

ACCEPT
0
0
0
0

LTC is afocused, dedicated company servicing the needs
of the linear military marketplace. We are shipping to the
top U.S. defense electronics contractors who have qualified and approved our products. LTC is committed to
being the best and most proficient high quality supplier of
analog military components .

12-7

MILITARY PRODUCTS

LTC PROPRIETARY
RH WAFER FABRICATION
• THE TOPSIDE GLASSIFICATION
THICKNESS IS NON-COMPLIANT
TO MIL-STO-883 METHOD 5007

PARTICLE IMPACT NOISE
DETECTION (PIND) TEST PER
MIL-STO-883 METHOD 2020
CONDITION A 100%

*
SERIAlZATION

WAFER LOT ACCEPTANCE
MIL-STD-883 METHOD 5007
• GLASSIFICATION THICKNESS IS
NON-COMPLIANT PER ABOVE
CAN SAMPLE BUILD
FOR WAFER BUYOFF
• TOTAL DOSE IRRADIATION TEST
TO ASSURE COMPLIANCE TO
LTC "RH" DATASHEET. SIS =4
DEVICES PER WAFER,
ACCEPT =O. NOTE: TOTAL DOSE
IRRADIATION TESTING PER
MIL-8TO-883 METHOD 10191S
AVAILABLE FOR A CHARGE
ASSEMBLY NON-DESTRUCTIVE
BOND PULL PER MIL-STO-883
METHOD 2023
100%
PRESEAL INTERNAL VISUAL PER
MIL-STO-883 METHOD 2010
CONDITION A 100%
SEAL MONITOR PER MIL-STD-976
TEMPERATURE CYCLING PER
MIL-STO-883 METHOD 1010
CONDITIONC
100%
CONSTANT ACCELERATION PER
MIL-STD-883 METHOD 2001
(Y1 ONLy) CONDITION E
(TO-3 PACKAGE CONDITION D)
100%

*

*

100%

TOPMARK TO CUSTOMER NON
883 COMPLIANT MARKING
100%
SOLDER DIP
(IF APPLICABLE)
100%

PRE BURN-IN ELECTRICAL IN
ACCORDANCE WITH APPLICABLE
DEVICE SPECIFICATION
100%

RADIOGRAPHY (X-RAY) PER
MIL-STD-883 METHOD 2012,
2 VIEWS
100%

REVERSE BIASBURN-IN TEST PER
MIL-STO-883 METHOD 1015
CONDITION A OR C72 HOURS
AT 150°C MINIMUM IN
ACCORDANCE WITH APPLICABLE
DEVICE SPECIFICATION
100%

ELECTRICAL TEST IN
ACCORDANCE WITH APPLICABLE
DEVICE SPECIFICATION
100%

INTERIM (POST BURN-IN)
ELECTRICAL TEST IN
ACCORDANCE WITH APPLICABLE
DEVICE SPECIFICATION
100%
DYNAMIC BURN-IN PER
MIL-STO-883 METHOD 1015
240 HOURS AT 125°C MINIMUM
IN ACCORDANCE WITH
APPLICABLE DEVICE
SPECIFICATION. SINCE DYNAMIC
BURN-IN IS ONLY APPLICABLE
TO SOME PRODUCTS, THE NEED
TO PERFORM 100% DYNAMIC
BURN-IN MUST BE NEGOTIATED
BETWEEN THE CUSTOMER
AND LTC
100%
ELECTRICAL TEST 25°C, 125°C,
-55°C IN ACCORDANCE WITH
APPLICABLE DEVICE
SPECIFICATION
100%

GROUP A ELECTRICAL TEST PER
MIL-STD-883 METHOD 5005
TABLE 1 IN ACCORDANCE
WITH APPLICABLE
DEVICE SPECIFICATION
FINE LEAK TEST PER
MIL-STD-883 METHOD 1014
CONDITION A 100%
GROSS LEAK TEST PER
MIL-STD-883 METHOD 1014
CONDITION C 100%
EXTERNAL VISUAL PER
MIL-STD-883 METHOD 2009
100%
QUALITY CONFORMANCE
INSPECTION PER MIL-STO-883
METHOD 5005 GROUP BAND 0
TESTS FOR CLASS S

PDA CALCULATION 5% MAX, 3%
MAX FOR FUNCTIONAL
PARAMETERS AT 25°C

SHIP TO CUSTOMER
MIL·S1D-04

DENOTES PROCESS STEPS THAT ARE NON-COMPLIANT TO THE CLASS S REQUIREMENTS OF MIL-STO-883. FOR MORE DETAILS CONSULT
THE FACTORY.

Figure 4. LTC Representative "RH" Product Manufacturing Flow

.

BOXSTOCK

NOTE: 1. APPLICABLE DEVICE SPECIFICATION SHALL BE THE MIL-M-38510 DEVICE SPECIFICATION, OR A DEVICE SPECIFICATION AGREED UPON
BETWEEN THE CUSTOMER AND LTC.
2. CUSTOMER SOURCE INSPECTION WILL BE ADDED AS SPECIFIED ON CUSTOMER'S PURCHASE ORDER.

12-8

*

MILITARY PRODUCTS
883 CERTIFICATE OF CONFORMANCE - LEVEL B

.TC Part Number _ _ _ _ _ _ _ _ __
.ot Traceability No. _ _ _ _ _ _ _ _ __

QUALITY ASSURANCE INSPECTOR
DATE

SIGNATURE

lurchase Order No. _ _ _ _ _ _ _ _ __
:ustomer Name _ _ _ _ _ _ _ _ _ PIN _ _ _ _ _ _ __ Q t y - - - - - - late Code
Shipper # _ _ _ _ _ __ Traveller Lot # _ _ _ _ _ __
lroup A = _ _ __

Group B =_____ Group C=_____ Group D= _ _ _ __

lroup B/3 He-Inspection Date, If Applicable _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
.lNEAR TECHNOLOGY CORPORATION HEREBY DECLARES THAT THE COMPONENTS SPECIFIED ON THE ABOVE
lURCHASE ORDER COMPLY WITH YOUR SPECIFICATIONS AND REQUIREMENTS OF MIL-STD-883. ALL
;UPPORTING DOCUMENTATION AND RECORDS ARE RETAINED ON FILE BY LTC AND ARE AVAILABLE FOR
NSPECTION. THE MAJOR ELEMENTS OF THE 883 PROGRAM ARE SHOWN BELOW.
Operation
Internal Visual
Temperature Cycling
Constant Acceleration
Fine Leak
Gross Leak
Burn-in
Final Electrical

Screening Procedure MIL-STD-883, Method 5004
Method 2010, Condition B
Method 1010, Condition C, 10 cycles -65°C to 150°C
Method 2001, Condition E, 30k g Y1 axis (TO-3 PKG Condition Dat 20k g)
Method 1014, Condition A
~
Method 1014, Condition C
~ ~
Method 1015, 160 hrs at 125°C (or equivalent)
~~
+25°C DC (per LTC Data Sheet) PDA = 5%
~T"
+125°C or 150°C DC
~

y

~"'"

QA Acceptance
Quality Conformance
External Visual

-55°C DC
1
+25°CAC
~,..
Method 5005 Group A (samplellot)
Group B(samplellot)
Group C(sample every 6 monthS/Circuit Group)
Group D (sample every 6 months/Package Family)
Method 2009

NOTE: Each operation is performed on a 100% basis unless otherwise stated.
FORM No. 00·03·6072

.lNEAR TECHNOLOGY CORPORATION
630 McCarthy Blvd.
~ilpitas, CA 95035-7487

12-9

MILITARY PRODUCTS
LINEAR TECHNOLOGY CORPORATION
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
GROUP A DATA
Mil-Std-883, METHOD 5005
LTCP~:~____________________
GENERIC TYPE: _ _ _ _ _ _ ___
ASSEMBLY LOC: _ _ _ _ _ _ _ __

LOT #: _________________
PKG: _ _ _ _ _ _ _ _~_

Ace

SIS

DATECODE: _______________

#

FAILED

#

DATE
TESTED

OPER
NUMBER

SUBGROUP 1
Static tests at 25°C

0

116

0

116

0

116

0

116

0

116

0

116

0

116'j

0

116

0

116

0

116

0

116

SUBGROUP 2
Static tests at maximum rated operating
temperature

SUBGROUP 3
Static tests at minimum rated operating
temperature

SUBGROUP 4
Dynamic tests at 25°C

SUBGROUPS
Dynamic tests at maximum rated operating
temperature

SUBGROUP 6
Dynamic tests at minimum rated operating
temperature

SUBGROUP 7
Functional tests at 25°C

,~~~

~, ~ ~
~

.....

~~p

SUBGROUP 8
Functional tests at maximum and minimum
operating temperature

SUBGROUP 9
Switching tests at 25°C

SUBGROUP 10
Switching tests at maximum rated operating
temperature

SUBGROUP 11
Switching tests at minimum rated operating
temperature

QA APPROVAL: ______

DATE: _ _ __
FORM No. 00-03-6037

12-10

.L7lJD~

MILITARY PRODUCTS
LINEAR TECHNOLOGY CORPORATION
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
GROUP 8 DATA (Class 8)
Mil-Std-883, METHOD 5005
LTC PIN: _ _ _ _ _ _ _ _ __
GENERIC TYPE: _ _ _ _ _ __
ASSEMBLY LOC: _ _ _ _ _ __

LOT#: _ _ _ _ _ _ __
PKG: _ _ _ _ _ _ __

TEST

METHOD

CONDITION

SAMPLE
SIZE
SERIES

ACC
#

SUBGROUP 2
Resistance to Solvents

2015

SUBGROUP 3
Solderability

2003

Soldering Temp. of
245°C ± 5°C

10

0

SUBGROUP 5
Bond Strength

2011

CorD

15

0

DATE CODE: _ _ _ _ _ __

SIS

#
FAILED

OPER

0

QA APPROVAL:

DATE:
FORM No. 00·03-6006

LINEAR TECHNOLOGY CORPORATION
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
GROUP C DATA (Class 8)
Mil-Std-883, METHOD 5005
LTC PIN: _ _ _ _ _ _ _ _ __
LOT#: _ _ _ _ _ _ __
PKG: _ _ _ _ _ _ __
GENERIC TYPE: _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ CT. GROUP: _ _ _ _ __

TEST

SUBGROUP 1
Steady State
Life Test
Electrical Endpoints

METHOD

CONDITION

1005

TA= 125°C
(1000 Hours or Equiv.)

SAMPLE
SIZE
SERIES

ACC
#

5

0

DATE CODE:

SIS

Test #
QA APPROVAL:

DATE: _ _ __
FORM No. 00·03-6007

12-11

MILITARYPRODUCTS
LINEAR TECHNOLOGY CORPORATION
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
GROUP B DATA (Class S)
Mil-Std-883, METHOD 5005
LTCP~:

____________________

GENERIC TYPE: _ _ _ _ _ _ _----,
ASSEMBLY LOC: _ _ _ _ _ _ ___

TEST

SUBGROUP 1
Physical Dimensions
Internal Water-Vapor
Content
SUBGROUP 2
Resistance to Solvents
Intemal Visual and
Mechanical
Bond Strength
Die Shear Test
SUBGROUP 3
Solderability
SUBGROUP 4
Lead Integrity
Seal
Fine
Gross
Lid Torque
SUBGROUPS
Electrical End-Points
Steady State Life
Electrical End-Points
SUBGROUP 6
Electrical End-Points
Temperature CyCling
Constant Acceleration
Seal
Fine
Gross
Electrical End-Points
SUBGROUP 7
ESD Classification

LOT #: _______________
PKG: _ _ _ _ _ _ _ ___

METHOD

CONDITION

2016
1018

5000 ppm Max

SAMPLE
SIZE
SERIES

DATE CODE: _ _ _ _ _ _ __

Ace
#

SIS

0
0

3
2

10

0
0

22 Wires
3

0

22 Leads

2015
2013,
2014
2011
2019

Design and Construction
Requirements
CorD

2003
or 2022

Soldering Temp. of
245°C±5°C

10

2004
1014

B2 (Lead Fatigue)

5

2024

Glass Frit Seal Only
Test #
C,D,orE
Test #

5

0

45

1005

Test #
C 100 Cycles
EY10nly
(TO-3 at Condition D,
20Kg)

15

0

15

1010
2001
1014

15

N/A

--

~
1
j:
~
0

OPER
#

-~ ~ ~~~

45

Test #
3015

Qual or Re-Design
Only

QA APPROVAL: ______

12-12

DATE
TESTED

#
FAILED

DATE: ______

.L7lJ~

MILITARY PRODUCTS
INEAR TECHNOLOGY CORPORATION
630 McCarthy Blvd.
'ilpitas, CA 95035-7487
GROUP D DATA (Class B or S)

Mil-Std-883, METHOD 5005
LTC PIN: _ _ _ _ _ _ _ _ _ __
GENERIC TYPE: _ _ _ _ _ _ __
ASSEMBLYLOC: _ _ _ _ _ _ __

TEST

METHOD

SUBGROUP 1
Physical Dimensions

2016

SUBGROUP 2
Lead Integrity

2004

Fine Leak
Gross Leak

1014
1014

SUBGROUP 3
Thermal Shock
Temperature Cycle
Moisture Resistance
Fine Leak
Gross Leak
Visual Examination

1011
1010
1004
1014
1014
10041
1010

Electrical End-Points
SUBGROUP 4
Mechanical Shock
Vibration, Variable
Frequency
Constant Acceleration
Fine Leak
Gross Leak
Visual Examination

LOT#: _ _ _ _ _ _ _ __
PKG: _ _ _ _ _ _ _ __

CONDITION

DATECODE: _ _ _ _ _ __

SAMPLE
SIZE
SERIES

ACC
#

SIS

15

0

15

5

0

45 Leads

15

0

15

#
FAILED

OPER
#

B2 (Lead Fatigue)

B
C

15 Cycles
100 Cycles

.. c=._

Test #
15
2002
2007

B
A

2001
1014
1014
10101
1011

E

Electrical End-Points

DATE
TESTED

0

~~

Yl0nly

(TO-3at
Condition D, 20Kg)

'~ ~Y'

tfIJ~

~~

Test #

SUBGROUPS
Salt Atmosphere
Fine Leak
Gross Leak
Visual Examination

1009
1014
1014
1009

Visual Criteria

SUBGROUP 6
Internal Water-Vapor

1018

5000 ppm Max

SUBGROUP 7
Adhesion of Lead Finish

2025

SUBGROUPS
Lid Torque

2024

15

0

0

3

0

15

0

5

15

A

15

•

Glass Frit Seal Only
QA APPROVAL: _ _ _ __

DATE: _ _ _ __
FORM No. 00-03-6008

12., 13

MILITARY PRODUCTS
Mil tTARY PARTS liST

JAN SQPL

JM38510110103SGA (LM101AH)
JM38510110103SHA (LM101AW)
JM38510nol03SPA (LM101AJ8)
JM38510110104SCA (LM108AJ)
JM38510110104SGA (LM108AH)
JM3851011010'SHA (LM108AW)
JM38510110104SPA (LM108AJ8)
JM38511l110107SGA (LM118H)
JM38510110304SGA (LMll1H)
JM38510110308SCA (LMll9J)

JM38510/10306SIA (LM119H)
JM38510110306SHA (LM119W)
JM38510110307SCA (LTll9AJ)
JM38510110307SIA (LT119AH)
JM38510110307SHA (LTl19AW)
JM38510111401SPA (LFl55J8)
JM3851 0I11402SGA (LF156H)
JM38510111402SPA (LF156J8)
JM38510111404SGA (LFl55AH)

JM3851 0I11404SPA (LF155AJ8)
JM38510111405SGA (LF156AH)
JM38510111405SPA (LFl56AJ8)
JM38510111703SXA (LM117H)
JM38510111704SYA (LM117K)
JM38510111803SXA (LM137H)
JM38510111804SYA (LM137K)
JM38511l112407SGA (LT1021-5H)
JM38510112408SGA (LTl 021-7H)

JM38510112409SGA (LT1021-10H)
JM38510112501SGA (LF198H)
JM38510n3501SGA (OP07AH)
JM38510113501SPA (OP07AJ8)
JM38510113502SGA (OP07H)
JM38510113502SPA (OP07J8)
JM38510113503SGA (OP27AH)
JM38510113500SPA (OP27AJ8)
JM38510114802SXA (LTlO09H)

JAN BQPL

JM385101101038CA (LM101AJ)
JM38511l110103BGA (LM101AH)
JM38511l110103BHA (LM101AW)
JM38511l1101038PA (LM101AJ8)
JM38510110104BCA ILM108AJ)
JM38511l110104BGA (LM10BAH)
JM38510/10104BPA (LM108AJ8)
JM3851 on 01 06BEA (LH210BAO)
JM38510110107BCA (LMll8J)
JM3851 011 01 07BGA (LM118H)
JM3851 011 01 07BHA (LM118W)
JM38510110107BPA (LMll6J8)

JM38510/10304BGA (LMll1 H)
JM38510110306BIA (LMl19H)
JM38510110306BCA (LMll9J)
JM38510110306BHA (LMl19W)
JM38510110307BCA (LT119AJ)
JM38510/10307BIA (LT119AH)
JM3851 0I10307BHA·(LTll9AW)
JM38510/11401BGA (LF155H)
JM38510/11401BPA (LF156J8)
JM38510111402BGA (LF156H)
JM38510111402BHA (LF159W)

JM38510111402BPA(LF156J8)
JM38510111404BGA (LF155AH)
JM38510111404BPA (LF155AJ8)
JM38510111405BGA (LF156AH)
JM38510111405BHA (LF156W)
JM38510111405BPA (LF156AJ8)
JM38510111703BXA (LM117H)
JM38511l111704BVA (LMl17K)
JM3851 0I11706BVA (LM138K)
JM38510111803BXA (LM137H)
JM3851 0I11804BVA (LM137K)

JM38510112407BGA (LT1021-5H)
JM38511l112408BGA (LT1021-7H)
JM38510112409BGA (LTl021-10H)
JM3851 0112501 BGA (LFl98H)
JM38510113501BGA (OP07AH)
JM38510113501 BPA (OP07AJ8)
JM38510113502BGA (OP07H)
JM3851 0/13502BPA (OP07J8)
JM38510113503BGA (OP27AH)
JM38510113503BPA (OP27AJ8)
JM38511l114802BXA (LTl009H)

DESC Drawings

7703401XA (LMll7H)
7703401VA (LM117K)
7703402XA (LM117HVH)
7703402VA (LM117HVK)
7703403XA (LM137H)
7703403VA (LM137K)
7703404XA (LM137HVH)
7703404VA (LM137HVK)
7703405XA (LTl17AH)

7703405VA (LT117AK)
7703406XA (LT137AH)
7703406VA (LT137AK)
7703407XA (LT117AHVH)
7703407VA (LTl17AHVK)
7703408XA (LT137AHVH)
770340BVA (LTl37AHVK)
7802801EA (SG1524J)
8203601GA (OP07AH)

8203601PA IOP07AJ8)
8203602GA (OP07H)
8203602PA (OP07J8)
8418001XA (LM136AH-2.5)
8551401GA (REF02AH)
8551401PA (REF02AJ8)
8600801EA(LT685)
8601401CA (LMl19J)

8601401HA (LMl19W)
86014011A (LMl19H)
8601402CA (LTll9AJ)
8601402HA (LTll9AW)
86014021A (LT119AH)
8687702XA (LTlllAH)
8687702PA (LTll1AJ8)

Standard Military
Drawings (SMD)

5982-3870701 MGA (LTC1044MH)
5962-3870702MPA (LTC1044MJ)
5962-8880601EA (LTl846J)
5962-8680602EA (LT1847J)
5962-8684501lA (lTl016MH)
5962-8684501PA (LT1018MJ8)
5962-8686101XA (LT58OSH)
5962-8686102XA (LT58OTH)
5962-8686103XA (LT580UH)
5962-8687701GA (LT111AH)
5962-8687701 PA (LT111 AJ8)
5962-8686201XA (lH0070-0H)
5962-8688202XA (lHOO70-1 H)
5962-8688203XA (lH0070-2H)
5962-8688701CA (OP227AJ)
5962-8757801 GA (lTlOO7AMH)
5962-8757801 PA (lTl 007AMJ8)
5962-8759401XA (lMl86H-1.2)
5962-8759402XA (lM185H-2.5)
5962-8760401GA (lMl0H)
5962-8760401PA (lMl0J8)
5962-876660lVA (LT1 080MJ)
5962-8766602EA (lTl081MJ)
5962-8767501XA (lMl50K)
5962-8767502XA (lT15OAK)
5962-8771501CA (lT1002AMJ)
5962-8773801 GA (lTlOO1MH)
5962-8773801 PA (lTl001 MJ8)
5962-87738036A (lTl 001 AMH)
5962-87738036PA (lTlOO1AMJ)
5962-8774101 XA (lTl033MK)
5962-8777501VA (lM123K)
5962-8777502VA (lM123AK)
5962-8863701GA (OP37AH)
5962-8863701 PA (OP37AJ8)
5962-8863702GA (OP37BH)
5962-8853702PA (OP37BJ8)
5962-8863703GA (OP37CH)
5962-8863703PA (OP37CJ8)
5962-8856101XA (LMl99AH)
5962-8856102XA (lM199H)
5962-8856201 XA (lTl 01 OMH)
5962-8856201VA (lTl 01 OMK)
5962-8856701GA (lT1037AMH)
5962-8856701PA (lTl037AMJ8)
5962-8859701 XA (lTl004MH-l.2)
5962-8859702XA (lTlO04MH-2.5)

5962-8860001GA (LT1021 BMH-l0)
5962-8860002GA (LTl021CMH-l0)
5962-8860003GA (LT1021OMH-l0)
5962-8862201GA (LT1028MH)
5962-8862201 PA ILT1028MJ8)
5962-8862202GA (lTl028AMH)
5962-8862202PA (lTl028AMJ8)
5962-8864101 RA (LTCl 06QAMJ)
5962-8864102RA (LTC1060MJ)
5962-81164601XA ILTl085MK)
5962-8864701GA (LT1021BMH-7)
5962-8864702GA (lTl021OMH-7)
5962-887510lVA (lTl039MJ)
5962-8875102EA (LT1 039MJ16)
5962-8878001 GA (lTl013AMH)
5962-8876001 PA (LTlO13AMJ8)
5962-8876002GA (lTl013MH)
5962-8878002PA (LT1013MJ8)
5962-8876201GA (LT1 021BMH-5)
5962-8876202GA ILTl 021 CMH-5)
5962-8876203GA (LT1021OMH-5)
5962-8944001 CA (lTl032MJ)
5962-8948301 LA (lTC1064MJ)
5962-8950401GA (lTl017MH)
5962-8950401PA (lTlO17MJ8)
5962-8950402GA (LT1018MH)
5962-8950402PA (lTlO18MJ8)
5962-8951101 EA (lTl525AJ)
5962-8951102EA (lTl527AJ)
5962-8952101XA (lTlO84MK)
5962-8956201GA (LT1054MH)
5962-8956201 PA (LTl 054MJ8)
5962-8958101GA (REF01AH)
5962-8958101PA (REF01AJ8)
5962-8961001XA (lTlO09MH)
5962-8962201GA (lT1 022AMH)
5962-8962202GA (LTlO22MH)
5962-8967701CA (LT1014AMJ)
5962-8967702CA (lTl014MJ)
5962-8978201CA (LTC1052MJ)
5962-8978201GA (LTC1052MH)
5962-8978201 PA (LTCl 052MJ8)
5962-8980201XA (lTl031BMH)
5962-8980202XA (LT1031CMH)
5962-8980203XA (LTl031OMH)
5962-8983002RA (lTC1290BMJ)
5962-8983003RA (LTC1290CMJ)

5962-8983004RA (LTC12900MJ)
5962-8987301VA (LTlO03MK)
5962-8989701CA (LT1058AMJ)
5962-8989701XA (LT105BAML)
5962-8989702CA (LTl053MJ)
5962-8992101XA (LM129AH)
5962-8992102XA (LM129BH)
5962-8992103XA (LMl29CH)
5962-8997601GA (LTlO55AMH)
5962-8997602GA (LT1056AMH)
5962-8997603GA (LT1055MH)
5962-8997804GA (lTl056MH)
5962-8998101XA (lTl086MK)
5962-8998101VA (lTlO86MH)
5962-9050701XA (lM134H-3)
5962-9050702XA (lMl34H-6)
5962-9050703XA (lM134H)
5962-9051901XA (lTl029AMH)
5962-9051902XA (lTl029MH)
5962-9054501RA (LTC1045MJ)
5962-9056801CA IOP237AJ)
5962-9056802CA (OP237CJ)
5962-9059501GA (lTl019AMH-l0)
5962-9059502GA (LT1 019AMH-5)
5962-9059503GA (LT1019AMH-4.5)
5962-9059504GA (lTl019AMH-2.5)
5962-9059505GA (lTlO19MH-l0)
5962-9059506GA (LT1019MH-5)
5962-9059507GA (LT1019MH-4.5)
5962-9059508GA (lTl019MH-2.5)
5962-9062701GA (LT10l1AMH)
5962-9JJ62701PA (lTlOllAMJ8)
5962-9062702GA (lT1011 MH)
5962-9062702PA (lTl0l1MJ8)
5962-9064901CA (lTC1064-4MJ)
5962-9064901XA (lTC1064-4Ml)
5962-9069301MCA (LTC1064-1MJJ883)
5962-9069302MCA (lTC1064-1AMJi883)
5962-9073902MXA (lT1084-5MK)
5962-9073903MXA (lT1085-5MK)
5962-9073904MXA (lTl066-5MK)
5962-9081701 MGA (LT1057AMH)
5962-9081701MPA (lTl057AMJ8)
5962-9081702MGA (lT1057MH)
5962-9081702MPA (LT1057MJ8)
5962-9082501MVA (lTl070MK)

5962-9082502MVA (LTlO71MK)
5962-9082503MVA (LT1072MK)
5962-9082503MPA (LT1072MJ8)
5962-9082504MVA (LT1070HVMK)
5962-9082505MVA (LT1071 HVMK)
5962-9082506MVA (lTlOnHVMK)
5962-9084101 MCA (LT1020MJ)
5962-9084201 MGA (LT1 012MH)
5962-9084201 MPA (L TlO12MJ8)
5962-9084202MGA ILTl012AMH)
5962-9064202MPA (lTl012AMJ8)
5962-9159501 MPA (lTC1062MJ8)
5962-9161901MPA (LTC1042MK)
5962-9163201 MCA (lTl079MJ)
5962-9163202MCA (lTl079AMJ)
5962-9163203MCA (LT1078MJ)
5962-9163204MCA (lTl078AMJ)
5962-9163204MGA (lTl078AMH)
5962-9163204MPA (LT1078AMJ8)
5962-9172901 MVA (LT1180MJ)
5962-9172902MEA (LT1181 MJ)
5962-9172903MVA (lT1280MJ)
5962-9172904MEA (lT1281 MJ)
5962-9207901MPA (lTl172MJ8)
5962-9207901MPA (lT1172MJ8)
5962-9208001MPA (LTC485MJ8)
5962-9305701MPA (lTC1291CMJ)
5962-9305702MPA (lTC1292CMJ)
5962-9305703MEA (lTCl293CMJ)
5962·9305704MRA (lTC1294CMJ)
5962-9311901MVA (lTl076MK)
5962-9311902MVA (lTl076HVMK)
5962-9318401 MPA (lTl229MJ8)
5962·9318402MCA (lTl2320MJ)
5962·9319001 MPA (lT1241 MJ8)
5962-9319002MPA (lT1242MJ8)
5962-9319JJ03MPA (lTl243MJ8)
5962-9319004MPA (lT1244MJ8)
5962-9319005MPA IlTl245MJ8)
5962-9321201MPA (lTlll1 MJ8)
5962·9322401 MPA (lT1120MJ8)
5962-9323801 MCA (LTl125MJ)
5962-9323802MPA (lT1124MJ)
5962-9323B03MCA (lTl125AMJ)
5962-9323804MPA (LT1124AMJ)
5962-9451601MPA (LT118AJ8)

Radiation
Hardened

RH07
RH27C
RH37C
RH101A

12.,14

RH108A
RH111
RHll7
RH118

RH119
RH129
RH137
RH1009

RH1011
RH1013
RH1014
RH1021-5

RH1021-7
RH1021-10
RH1056
RH1078

MILITARY PRODUCTS
MILITARY PARTS LIST
883

LF155AHi883
LF155H/883
LF158AHI883

LM1 01 AJBi883
LM107H/883
LM107JBi883

Ln078AMH188a
LT1 078AMJBi883
LT1078MH1883
LT1078MJ8I883
LT1079AMJi883
LT1 079MJ/883
LT1124AMJ8\883
LT1124MJBi883
LT1125AMJBi883
LT1125MJBI883
LT1126AMJBi883
LT1126MJB1883
LT1127AMJ8I883
LT1127MJi8B3
LT1172MJ8/883
LT1228MJ8/883
LTC1050AMHI883
LTC1050AMJBI8B3

LTC1050AMJi883
LTC1050MHi883
LTC1050MJBI883
LTC1050MJI883
LTC1051AMHi8B3
LTC1Q51AMJ8I883
LTC1051MJ8I883
LTC1052MHI883
LTC1052MJ/883
LTC1052MJBI883
LTC1150MJBI883
OP-OsAH/883
OP-oSAJBI883
OP..Q5H/883
OP-05J8/883
OP-05AW/883
OP-OSW/883
OP..Q7AH/883

OP..Q7AJBi883
OP..Q7H/883
OP..Q7JBi883
OP-15AH/883
OP-15BHI883
OP-15CHlB83
OP-15CJ8/883
OP-16AH/883
OP-16BHI883
OP-16CH/883
OP-16CJBi8B3
OP-27AH/883
OP-27AJ8I883
OP-27BJBI883
OP-27BH/883

LF156H/883

LM108AH/883

LF158JB1883
LF156W/883
LF412AMHi883
LF412MH1883
LF412AMJBI883
LF412MJ8I883
LHOO70-0H/883
LHOO70-1 H/883
LH0070-2H1883
LH2108A01883
LH21080/883
LM10H1883
LM1OJBi883
LM101AHJ883

LM108Hi883
LM108AJ8I883
LT118AHf883
LT118AJ8I883
LT1001AMHI883
LnOO1AMJ8/883
LT1001MHi883
LT1001MJ81883
LT1002AMJi883
LT1002MJ/883
LT1006AMH/883
LT1006AMJ8I883
LT1008MH/883
Ln006MJ8I883

LT1 007AMHi883
LT1007AMJBI883
LT1007MH/883
LT1007MJ8I883
LT1008MH/883
LT1Q12AMHI883
LT1012MD/883
LT1012MH/883
LT1013AMHlB83
LT1013AMJBi883
LT1013MH/883
LT1013MJBi883
LT1014AMJ1883
LT1014MJ/883
LT1024AMD/883
LT1024MD/883
LT1 055AMH/883
LT1 055MHi883

LM118Hi8B3
LM11BJBi883
LM118WI883
LT1022AMHI883
LT1022MHl883

LT1028AMH/883
LT1028AMJ8I883
LT1028MH/883
LT1028MJ8I883
LT1037AMH/883

LT1 037AMJB1883
LT1037MHl883
LT1037MJB1883
LT1056AMHI883
LT1 05BMH/8B3

LT1057AMH/883
LT1057AMJ8I883
LT1057MHI883
LT1057MJB1883
LT1058AMJi883

LT1058AMU883
LT1058MJ/883
LT1187MJ8/883
LT1189MJBI883
LT1190MJ8I883

LT1191MJ81833
LT1192MJ8I883
LT1193MJ81883
LT1194MJBi883
LT1195MJB1883

LT1223MJ8I883
LTl229MJBI883
LT1230MJ/883

LMl17H/883
LM117HVH!883
LMl17HVKl883
LM117K1883
LM123K/883
LM137H1883
LM137HVHf883

LM137HVKI883
LM137Ki8B3
LM138Ki8B3
LMl50K/883
LT117AHl883
LT117AHVH/8B3
LT117AHVK/883

LT117 AKl883
LT123AKJ883
LT137AH/8B3
LT137AHVH/883
LT137AHVK/883
LT137AKiB83
LT138AK/883

LT150AK/883
LT1003MKi883
LT1005MK/883
LT1020MJi883
LT1 02BMJBI883
LT1 026MHBi883
LT1033MKlS83

LT1035MKl883
LT1036MKi883
LT1054MJBI883
LT1054MH/883
LT1074MKi883
LT1 074HVMKi8B3
LT1076MKl883

LT1076HVMKl883
LT10B3MK-5I883
LT1083MK-121883
LT1084MK/883
LT10B4MK-5I883
LT1084MK-1218B3
LT1085MKI883

LTl086MH/883
LT1086MKi883
LT1 086MK-518B3
LT10BBMK-121883
LT1120MJBi8B3

LM129AH/883
LM12BBHI883
LM129CH/883
LM134H/8B3
LMl34H-31883
LMl34H-6I883
LM136AH-2.51883
LM136H-2.5I883
LM1B5H-1.21883
LM185H-2.5/883

LM199AHi883
LM199AH-201883
LM199H1883
LT580SHi883
LT580THl883
LT580UH1883
LT581SHI8B3
LT5B1TH/883
LT5B1UH/883
LT1004MH-1.2I883

LT1004MH-2.5/8B3
LT10oeMH/883
LT1019AMH-2.51883
LT1019AMH-4.5I883
LT1 019AMH-5I883
LT1019AMH·1O/8B3
LT1019MH-2.51883
LT1019MH-4.5I883
LT1019MH-5/883
LT1019MH-1018B3

LT1 021 BMH-5/8B3
LT1021CMH-5/883
LT1021DMH-51883
LT1021BMH-7/883
LT1021DMH-7/883
LT1021BMH-101883
LT1021CMH-101883
LT1021DMH-101883
LT1029AMH/BB3
LT1029MH/8B3

LT1 031 BMH1883
LT1031CMHi8B3
LT1031DMH/883
LT1034BMH-1.21883
LT1034BMH-2.51883
LT1034MH-l.2/883
LT1034MH-2.5J883
REF..Q1AHi883
REF..Q1AJBi883
REF..Q1 H/883

REF-01JBi883
REF..Q2AH/883
REF-02AJ8I883
REF..Q2Hi8B3
REF-02J8I883

883

LM111H1883
LM111J8I883
LM119H/8B3
LM119J/883

LM119W1883
LT111 AHi883
LT111 AJBI883
LT119AH/883

LT119AJ/883
LT685MH1883
LT685MJ/883
LT1 011 AMH/883

LT1011AMJ8J883
LT1011MHi8B3
LT1 011 MJBI883
LT1016MHI883

LT1016MJJ883
LT1016MJBi883
LT101BMLI883
LT1017MHlB83

LT1017MJBiB83
LT1018MH/883
LT1018MJ8I883
LTC1042MJ8I883

883

LT1070MKl8B3
LT1070HVMK/883
LT1 071 MKI883
LT1071HVMKlB83

LT1072MKI883
LT1072HVMKl883
LT1072MJ81883
LT1241MJ8/883

LT1242MJ8/883
LT1243MJ8I883
LT1244MJ8I883
LT1245MJ8/883

LT1524JJ883
LT1525AJ1883
LT1527 AJi883
LT1846J1883

LT1B47J/883
SG1524J/8B3
SG1525AJi883
SG1527AJi883

883

LT1032MJ/883
LTl039MJ/883
LT1 039MJ1 BI883

LT10BOMJi883
LT1081MJI883
LT1180MJ/883

LT11BOAMJi883
LTl181AMJ/883
LT1181MJ/883

LT12BOMJI883
LT1281MJ1883
LTC485MJ8/883

LTC1045MJi8B3

883

LTC1059AMJ1883
LTC1059MJi883
LTC1060AMJ/883
LTC1060MJi883

LTC1061AMJl883
LTC1061MJ/883
LTC1062MJBi883
LTC1063MJB1883

LTC1064MJ/883
LTC1064-1AMJ/883
LTC1064-1 MJi8B3
LTC1064-2MJ/883

LTC1064-2Mli883
LTC1064-4MJJ883
LTC1064-4Mli883
LTC11 84MJI883

LTC1164AMJ/883
LTC1164-5MJi883
LTC11B4-7MJI883

883

LTC10B4MJ18B3
LTC1290BMJi883
LTC1290CMJ/883

LTC12B00MJ/883
LTC12B3BMJ/883
LTC1293CMJ18B3

LTC1293DMJi883
LTC1294BMJ/883
LTC1294CMJI883

LTC12940MJ1883

LFl98AH/883
LF198H/883
LT1010MHi8B3

LT1010MK1883
LTC2Q1AMJ/883
LTC1041MJBi883

LTC1043MD/883
LTC1Q44MH/883
LTC1044MJBI883

Operational
Amplifiers

883
High Speed
OpAmps

883
Regulators

883
References

Comparators

Switched-Mode
Control Circuits

Interface

OP·37AJ8/883
OP-37BJBI883
OP-37CH/883
OP-37CJ81883
OP-227AJi883
OP-227CJ/883

OP-237AJ1883
OP-237CJ1883

OP-27CH/883

OP-27CJB1883
OP-37AH/883

------------------~
Filters

Data
Converters

Other 883

L7lJ~

. .

12-15

NOTES

12-16

;ECTlon 13-nEW PRODUCTS

13-1

L7~J!J~

INDE)

SECTION 13-NEW PRODUCTS
INDEX .......................................................•............................................................................. 13-2
PROPRIETARY PRODUCTS
LT1160/LT1162, Half-/Ful/-Bridge N-Channel Power MOSFET Drivers ...................................................... 13-3
LTC1177-5/LT1177-12, Isolated MOSFET Drivers ............................................................................. 13-16
LT1186, OAC Programmable CCFL Switching Regulator (Bits-to-Nits™) .................................................. 4-196
LT1236, Precision Reference ........................................................................................................ 7-5
LT1239, Backup Banery Management Circuit .................................................................................. 4-454
LTC1274/LTC1277, 12-Bit, 10mW, 100kspsAID Converters with IpA Shutdown ......................................... 13-22
LT1304/LT1304-3.3/LT1304-5, Micropower OC/DC Converters with Low-Battery Detector Active in Shutdown ..... 13-37
LT1309, 500kHz Micropower OC/DC Converter for Flash Memory .......................................................... 13-41
LT1311, Quad 12MHz, 145ns Settling Precision Current-to-Voltage Converter for Optical Disk Drives ................ 2-34
LTC1324, Single Supply LocalTalffD Transceiver .............................................................................. 13-45
LTC1334, Single 5V RS232/RS485 Multi-Protocol Transceiver ............................................................. 13-53
LTC1346, 10Mbps DCE/DTE V.35 Transceiver ................................................................................. 13-65
LT1373, 250kHz Low Supply Current High Efficiency 1.5A Switching Regulator .......................................... 4-322
LT1375/LT1376, 1.5A, 500kHz Step-Down Switching Regulators ........................................................... 4-334
LT1389, AppleTalffD Peripherallntertace Transceiver ........................................................................ 13-73
LTC1392, Micropower Temperature, Power Supply and Differential Voltage Monitor ................................... 13-77
LTC1400, Complete SO-8, 12-Bit, 400ksps AID Converter with Shutdown .. ............................................... 13-86
LTC1410, 12-Bit, 1.25Msps Sampling AID Converter with Shutdown ...................................................... 13-97
LTC1429, Clock-Synchronized Switched Capacitor-Regulated Voltage Inverter •...•....•...•............................. 4-41
LTC1430, High Power Step-Down Switching Regulator Control/er .......................................................... 4-360
LTCI443/LTCI444/LTCI445, Low Power Quad Comparators .............................................................. 13-108
LTCI477/LTCI478, Single and Dual Protected High-Side Switches ...................................................... 13-112
LT1510, Constant-Voltage/Constant-Current Banery Charger ............................................................. 13-120
LT1512, SEPIC Constant-CurrentiConstant-Voltage Banery Charger ..................................................... 13-130
LT1521/LT1521-3/LT1521-3.3/LT1521-5, 300mA Low Dropout Regulators with Micropower
Quiescent Current and Shutdown .................................................................................................. 4-79
LTC1522, 4-Channel, 3V Micropower Sampling 12-Bit Serial I/O AID Converter ....................................... 13-134
LT1528, 3A Low Dropout Regulator for Microprocessor Applications ....................................................... 4-91
LT1529/LT1529-3.3/LT1529-5, 3A Low Dropout Regulators with Micropower Quiescent CUrrent and Shutdown ... 4-101
LTC1550/LTC1551, Low Noise, Switched Capacitor-Regulated Voltage Inverters ..................................... 13-142
LT1572, 100kHz, 1.25A Switching Regulator with Catch Diode ............................................................. 4-374
LT1580/LT1580-2.5, 7A, Very Low Dropout Regulator ...................................................................... 13-148

13-2

£.7Lin

U~UlfU~lb ~lSlblS~~lS
Final Electrical Specifications

LTl160/LTl162
TECHNOLO~G~~~--------H-a-If--/-F-U-II--B-ri-d-g-e
N-Channel
Power MOSFET Drivers
July 1995

:EATURES
I
I

I
I

I
I
I
I

I

DESCRIPTiOn

Floating Top Driver SWitches Up to 60V
Drives Gate of Top N-Channel MOSFET
above Load HV Supply
180ns Transition Times Driving 10,000pF
Adaptive Nonoverlapping Gate Drives Prevent
Shoot-Through
Top Drive Protection at High Duty Cycles
nUCMOS Input Levels
Undervoltage Lockout with Hysteresis
Operates at Supply Voltages from 1OV to 15V
Separate Top and Bottom Drive Pins

'PPLICATlons
I
I
I
I
I
I

PWM of High Current Inductive Loads
Half-Bridge and Full-Bridge Motor Control
Synchronous Step-Down Switching Regulators
3-Phase Brushless Motor Drive
High Current Transducer Drivers
Class D Power Amplifiers

The LT@1160/LT1162 are cost effective half-/full-bridge
N-channel power MOSFET drivers. The floating driver can
drive the top side N-channel power MOSFETs operating off
a high voltage (HV) rail of up to 60V (absolute maximum).
The internal logic prevents the inputs from turning the
power MOSFETs in a half-bridge on at the same time. Its
unique adaptive protection against shoot-through currents eliminates all matching requirements for the two
MOSFETs. This greatly eases the design of high efficiency
motor control and switching regulator systems.
During low supply or start-up conditions, the undervoltage
lockout actively pulls the driver outputs low to prevent the
power MOSFETs from being partially turned on. The O.5V
hysteresis allows reliable operation even with slowly varying supplies.
The LT1162 is adual version ofthe LT1160 and is available
in a 24-pin PDIP or in a 24-pin SO Wide package.
D, LTC and LT are registered trademarks of Linear Technology Corporation.

rYPICAL APPLICATiOn
lN4148

12V

~_-"'--+--'-Il

SV+

HV = 60V MAX

BOOST

10 PV+

14

T GATE DR .-13--.--+_---1

~
± 1000~F
100V

IRFZ44

-

T GATE FB 12
4 UV OUT

T SOURCE

~-~---+-n

LT1160
PWM
OHz TO 100kHz

-.ruLI1--

IN TOP
IN BOnOM

IN TOP IN BOnOM T GATE DR B GATE DR
L
L
L
L
L
H
L
H
H
L
H
L
H
H
L
L

13-3

•

LTl160/LTl162
ABSOLUTE mAxmum RATinGS
Supply Voltage (Note 1) .......................................... 20V
Boost Voltage ................ ......................................... lSV
Peak Output Currents « 10JlS) .............................. 1.SA
Input Pin Voltages .......................... -O.3V to V+ + O.3V
Top Source Voltage ..................................... -SV to 60V
Boost to Source Voltage ........................... -O.3V to 20V

Operating Temperature Range
Commercial .......................................... O°C to lO°C
Industrial ......................................... -40°C to 8SoC
Junction Temperature (Note 2) ............................ 12SoC
Storage Temperature Range ................ -6SoC to 1S0°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
TOP VIEW

IN BOTTOM 3
UV OUT 4
SGND
PGND
NC 7

ORDER PART
NUMBER
LT1160CN
LT1160CS
LT11601N
LT11601S

TOP VIEW
SV+ A
INTOPA
IN BOTTOM A
UVOUTA

ORDER PART
NUMBER

1
2
3

LT1162CN
LT1162CSW
LT11621N
LT11621SW

4

BGATE FB A 6

NPACKAGE
14-LEAD PDIP
SPACKAGE
14-LEAD PLASTIC SO

NPACKAGE
24-LEAD POIP

TJMAX = 125'C, 9JA = 70'c/W (N)
TJMAX =125'C, 9JA =110'C/W (S)

SW PACKAGE
24-LEAD PLASTIC SO WIDE

TJMAX =125'C, 9JA =58'C/W (N)
TJMAX = 125'C, 9JA = 8O'C/W (SW)

Consult factory for Military grade parts.

ELEORICAL CHARAOERISTICS

Test Circuit, TA = 25°C, V+ = VBOOST = 12V, VTSOURCE = OV, CGATE = 3000pF.
Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.
SYMBOL PARAMETER
DC Supply Current (Note 3)
Is

IBOOST

Boost Current (Note 3)

VIL

Input Logic Low

VIH

Input Logic High

CONDITIONS
V+ =15V, VINTOP =0.8V, VINBOTTOM =2V
V+ =15V, VINTOP =2V, VINBOTTOM =0.8V
V+ =15V, VINTOP =0.8V, VINBOTTOM =0.8V
V+ =15V, VTSOURCE =BOV, VBOOST =75V,
VINTOP = VINBOTTOM =0.8V

VINTOP =VINBOTTOM =4V

•
•
•

MIN
7
7
7

TYP
11
10
11

MAX
15
15
15

3

4.5

B

1.4

0.8

UNITS

rnA
rnA
rnA
rnA
\I

2

1.7

II

7

25

8.3

8.8

9.3

II

7.8

8.3

8.8

II

jJA

liN

Input Current

V+UVH

V+ Undervoltage Start-Up Threshold

V+UVL

V+ Undervoltage Shutdown Threshold

VBUVH

VBOOST Undervoltage Start-Up Threshold

VTSOURCE =BOV (VBoosr- VTSOURCE)

8.8

9.3

9.8

II

VBUVL

VBOOST Undervoltage Shutdown Threshold

VTSOURCE = BOV (VBOOST - VTSOURCE)

8.2

8.7

9.2

II

13-4

LTl 160/LT1 162
LEaRICAl CHARAaERISTICS

Test Circuit, TA=25°C, V+=VBDDST=12V, VTSDURCE= OV, CGATE=3000pF.
Ite Feedback pins connected to Gate Drive pins, unless otherwise specified.
MBOL PARAMETER
AK
IT
i

CONOITIONS

Undervoltage Output Leakage
Undervoltage Output Saturation
Top Gate ON Voltage

V+=15V

Bottom Gate ON Voltage
Top Gate OFF Voltage
Bottom Gate OFF Voltage

VINTOP = O.BV, V,NBonoM = 2V
V,NTOP = O.BV, V,NBonoM = 2V

Top Gate Rise Time
Bottom Gate Rise Time
Top Gate Fall Time
Bottom Gate Fall Time
Top Gate Turn On Delay
Bottom Gate Turn On Delay
Top Gate Turn Off Delay

V+ = 7.5V,

'4 = 2.5mA

V,NTOP = 2V, V,NBonOM = O.BV

V,NTOP = 2V, V,NBonOM = O.BV
V,NTOP (+) Transition, V,NBonoM = O.BV,
Measured at VTGATE DR (Note 4)
V,NBonoM (+) Transition, V,NTOP = O.BV,
Measured at VBGATE OR (Note 4)
V,NTOP (-) Transition, V,NBonoM = O.BV,
Measured at VTGATE OR (Note 4)
V,NBonoM (-) Transition, V,NTOP = O.BV,
Measured at VBGATE OR (Note 4)
V,NTOP (+) Transition, V,NBonoM = O.BV,
Measured at VTGATE DR (Note 4)
V,NBonoM (+) Transition, V,NTOP = O.BV,
Measured at VBGATE OR (Note 4)
V,NTOP H Transition, V,NBonoM = O.BV,
Measured at VTGATE OR (Note 4)

Bottom Gate Turn Off Delay

V,NBonoM (-) Transition, V,NTOP = O.BV,
Measured at VBGATE OR (Note 4)

Top Gate Lockout Delay

V,NBonoM (+) Transition, V,NTOP = 2V,
Measured at VTGATE OR (Note 4)
V,NTOP (+) Transition, V,NBonoM = 2V,
Measured at VBGATE OR (Note 4)

Bottom Gate Lockout Delay
Top Gate Release Delay

V,NBonoM H Transition, V,NTOP = 2V,
Measured at VTGATE OR (Note 4)

Bottom Gate Release Delay

V,NTOP H Transition, V,NBonoM = 2V,
Measured at VBGATE DR (Note 4)

denotes specifications which apply over the full operating
'perature range.
Ie 1: For the LTl160, Pins 1, 10 should be connected together. For the
1162, Pins 1, 7, 14, 20 should be connected together.
Ie 2: TJ is calculated from the ambient temperature TA and power
lipation Po according to the following formulas:
LTl160CN/LT1160IN: TJ = TA + (Po x 70°C/W)
LT1l60CS/LT1l60IS: TJ = TA + (Po x ll0°C/W)
LT1162CN/LTll62IN: TJ = TA + (Po x 5BoC/W)
LT1162CS/LT1162IS: TJ = TA + (Po x BO°C/W)
I•

•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•

MIN

TYP

MAX

11
11

0.1
0.2
11.3
11.3

5
0.4
12
12

0.4
0.4
130

0.7
0.7
200

ns

90

200

ns

60

140

ns

60

140

ns

250

500

ns

200

400

ns

300

600

ns

200

400

ns

300

600

ns

250

500

ns

250

500

ns

200

400

ns

UNITS

IJA
V
V
V
V
V

Nole 3: Is is the sum of currents through SV+, PV+ and Boost pins.
IBOOST is the current through the Boost pin. Dynamic supply current is
higher due to the gate charge being delivered at the switching frequency.
See Typical Performance Characteristics and Applications Information
sections. The LT1160 = 1/2 LT1l62.
Nole 4: Gate rise limes are measured from 2V to 10V and fall times are
measured from 10V to 2V. Delay times are measured from the input
transition to when the gate voltage has risen to 2V or decreased to 10V.

13-5

LTH60/LTl162
TYPICAL PERFORmAnCE CHARACTERISTICS
DC Supply Current \IS
Supply Voltage
14

r-~--.---r-~--.---r--'

14

13

r--+--~--r--+--~~r-~

13

g§

a>-

it
::::>

'"

11

f--t--+""7'1"74--c;,.j""'--f--l

12
.§.. 11

<'

<'

I--

I--

il:i
c::

10 r--+---:7q...~f-::::..-~VINTOP = HIGH
)"l.
VINBonOM = LOW
;\
I
I
VINTOP = LOW
VINBonOM = HIGH

c::

10

12
14 16 18
SUPPLY VOLTAGE (V)

20

.§..

il:i
c::

10

c::

::::>

::::>

~
"-

~
"-

'"

'"

<.>

<.>

"-

"::::>

5'----l.----'-__'----l.-__-'-__'--.....J

8

DC + Dynamic Supply Current
vs Input Frequency

DC Supply Current vs
Temperature

12

!!Z

(LT1160 or 1/2 LT1162)

::>

5
-50

22

-25

25 50
75
TEMPERATURE (OC)

100

10
100
INPUT FREQUENCY (kHz)

125

10C

1160/621301

DC + Dynamic Supply Current
vs Input Frequency
60

56% 'o~W g~CL~
V'=12V

50

.§.. 40

~~ATE ~1000 OpF

!Z
w
c::
c::

::::>

liT

30

<.>

~

""::::>

'"

CGATE

20 - -

/
I

12 f-

~

11
~ 10

w

w

I

0

~ ~ooJ/

>

I ~

~
~

I

fmr fri

~S~ART-UP THRESHOLD-- -

f--- I-SHUTDOWN THRESHOLD_ -

I

~

'"

./

11

0

"-

VTS~URCE f60V

10 f---

>

SHUTDOWN THRESHOLD- -

~
"::::>

/

~

START-UP THRESHOLD

'"i3

I I

....... ~
10

Undervoltage Lockout (VOOOST)
13

12

I

III

<'

Undervoltage Lockout (V +)
13

~

1GO

o

1

10
100
INPUT FREQUENCY (kHz)

1

4
-50

1000

-25

25 50
75
TEMPERATURE (0C)

100

4
-50 -25

125

0
25 50
75
TEMPERATURE (OC)

100

1160162004

1160162606

Input Threshold Voltage vs
Temperature
2.0

I

V'! 12V
~
w

1.8

~

J..--

~ 1.6

0

>
Cl

-' 1.4

'"f3

:I:

a:

:I:
I-I--

1.2

-

I--

-- Pr-

Top or Bottom Input Pin Current
vs Temperature
13

-'

12

~ 11
~ 10

\
\

\.

c::
c::

<.>

':;
"-

100

125

'\

"

::::>

;;;

0
25 50
75
TEMPERATURE (OC)

4
-50 -25

!

3.5

I--

3.0

il:i
c::

/

::>
<.>

"-

I--

If

2.0

/

::::>

i'-....

";;; 1.5
1.0

........... r-....

0
25 50
75
TEMPERATURE (OC)

100

./

0.5
125

o

J

/

c:: 2.5

1160162G08

13-6

)

V

4.0

";;;
1.0

-25

5.0
I
4.5 f- v+ ~ 12V

V+=12V_
VIN =4V

::::>

0.8
-50

Top or Bottom Input Pin Current
vs Input Voltage

14

~~

12

//
4

6

7 8
9 10
INPUT VOLTAGE (V)

11
1160162G09

LT1 160/LT1 162
rYPICAL PERFORmAnCE CHARAOERISTICS
Bottom Gate Rise Time
vs Temperature

Bottom Gate Fall Time
vs Temperature

V+ = 12V

210

./

I

190 -

150

J

CLOAD = 1000~

-

/"

V

~
>--

I-- I-""

--'

'"::0

--

50
-50

-

f-- CLOAD = 3000pF

~

f-r

-25

-

~

70

IXI

100

I-- r-

V

a:

~

-

CLOAD = 3000pF

15
>--

120

0
25
50
75
TEMPERATURE eC)

100

CLOAD = 1000~

120

l.--

./'V

V

--

125

300
250

V

z

V

CLOAD = 3000pF

60

-r:

40

~ 200

a:

I---

1=
150

0
25
50
75
TEMPERATURE (OC)

100

125

400

;:::

~

-25

Turn Off Delay Time vs
Temperature

CLOAD = 3rOPF

350
~

...J,.

I

~DAD = ;oOOPi-

V+=12V
CLOAD = 3000pF

V+ = 12V

c

80

- -

CLOAD = 3000p~

I--- >-J

80
-50

400
V+= 12V

140

160
140

Turn On Delay Time vs
Temperature

180
160

180

100
-25

V

V

;:::
w 200
en

CLO~D = 10~OPF~

30
-50

125

240

~ 220

""

50

CLOA~ - 1O~OPF-

0
25
50
75
TEMPERATURE (OC)

/

90

Top Gate Fall Time
vs Temperature

100

--

~ 130

!

/'

CLOAD = 10000pF

""

CLOAD = 10000pF

260

150

110

V+ = 12V

280

g 170
~ 110

90 -

300
V+ = 12V

190

130

70

Top Gate Rise Time
vs Temperature

210

230

170

(LT1160 or 1/2 LT1162)

350

/

TJPDRIVE~ /
V
/

.",

~ 300
;:::
>
;j 250
c

V

.....

z~

~Blonoi DRIViR

I-- V

...-

V

V

TOr DRIVER- r--

--

BonOM DRIVE!!.-

200

a:

1=

/"
///

-

r-

150

CLOAD = 1000pF
20
-50 -25

25
50
75
TEMPERATURE (OC)

100

100
-50

125

-25

0
25
50
75
TEMPERATURE (OC)

100

100
-50

125

-25

0
25
50
75
TEMPERATURE (OC)

100

125

11160162613

Lockout Delay Time vs
Temperature
400

I
CLDAD = 3000pF

~ 300

;:::
>

~ 250

c
>-::::>

~

u

=:

400

V+~12V

350

V

Release Delay Time vs
Temperature

"./
/

g'

I

;:::
>

V~PDRIVER- r---

~ f--BonOM DRIVER

V

350

w

~

200

a:
150

150

0
25 50
75
TEMPERATURE (0C)

100

TOP DRIVER/

~ 250

200

-25

./

~ 300

c

1--1----

100
-50

V+ = 12V
_ CLOAD = 3000pF

125

-

100
-50

V

V

-25

V

,........ /
./'

/

....

Krn-OM DRIVER

0
25 50
75
TEMPERATURE (OC)

100

125

1160162G17

L7lJ!J~

13-7

LTl160lLTl162

Pin FunOlons
LT1160

LT1162

SY+ (Pin 1): Main Signal Supply. Must be closely decoupled
to the signal ground Pin S.

SY+(Pins 1, 7): Main Signal Supply. Must be closely
decoupled to ground pins Sand 1l.

IN TOP (Pin 2): Top Driver Input. Pin2 is disabled when Pin
3 is high. A 3k input resistor followed by a sV internal
clamp prevents saturation of the input transistors.

IN TOP (Pins 2, 8): Top Driver Input. The Input Top is
disabled when the Input Bottom is high. A3k input resistor
followed by aSV internal clamp prevents saturation of the
input transistors.

IN BOTTOM (Pin 3): Bottom Driver Input. Pin 3 is disabled
when Pin 2 is high. A 3k input resistor followed by a SV
internal clamp prevents saturation ofthe inputtransistors.
UY OUT (Pin 4): Undervoltage Output. Open collector NPN
output which turns on when V+ drops below the
undervoltage threshold.
SGND (Pin 5): Small Signal Ground. Must be routed
separately from other grounds to the system ground.
PGND (Pin 6): BottomDriver Power Ground. Connects to
source of bottom N-channel MOSFET.
B GATE FB (Pin 8): Bottom Gate Feedback. Must connect
directly to the bottom power MOSFET gate. The top
MOSFET turn-on is inhibited until Pin 8 has discharged to
below 2.5V.
B GATE DR (Pin 9): Bottom Gate Drive. The high current
drive point for the bottom MOSFET. When a gate resistor
is used it is inserted between Pin 9 and the gate of the
MOSFET.
PY+ (Pin 10): Bottom Driver Supply. Must be connected to
the same supply as Pin 1.
T SOURCE (Pin 11): Top Driver Return. Connects to the
top MOSFET source and the low side of the bootstrap
capacitor.
T GATE FB (Pin 12): Top Gate Feedback. Must connect
directly to the top power MOSFET gate. The bottom
MOSFETturn-on is inhibited untilV12-V11 has discharged
to below 2.9V.

IN BOTTOM (Pins 3, 9): Bottom Driver Input. The Input
Bottom is disabled when the Input Top is high. A3k input
resistor followed by a SV internal clamp prevents saturation of the input transistors.
UY OUT (Pins 4, 10): Undervoltage Output. Open collector
NPN output which turns on when V+ drops below the
undervoltage threshold.
GND (Pins 5, 11):Ground Connection.
B GATE FB (Pins 6, 12): Bottom Gate Feedback. Must
connect directly to the bottom power MOSFET gate. The
top MOSFET turn-on is inhibited until Bottom Gate Feedback pins have discharged to below 2.SV.
B GATE DR (Pins 13, 19): Bottom Gate Drive. The high
current drive point for the bottom MOSFET. When a gate
resistor is used it is inserted between Bottom Gate Drive
pin and the gate of the MOSFET.
PY+ (Pins 14, 20): Bottom Driver Supply. Must be connected to the same supply as Pins 1 and 7.
T SOURCE (Pins 15, 21):Top Driver Return. Connects to
the top MOSFET source and the low side of the bootstrap
capacitor.
T GATE FB (Pins 16, 22): Top Gate Feedback. Must
connect directly to the top power MOSFET gate. The
bottom MOSFET turn-on is inhibited until VTGF- VTSOURCE
has discharged to below 2.9V.

TGATE DR (Pin 13):TopGate Drive. The high current drive
point for the top MOSFET. When agate resistor is used it
is inserted between Pin 13 and the gate ofthe MOSFET.

TGATE DR (Pins 17, 23):Top Gate Drive. The high current
drive point for the top MOSFET. When a gate resistor is
used it is inserted between the Top Gate Drive pin and the
gate of the MOSFET.

BOOST (Pin 14): Top Driver Supply. Connects to the high
side of the bootstrap capacitor.

BOOST (Pins 18, 24):Top Driver Supply. Connects to the
high side of the bootstrap capacitor.

13-8

LT1 160/LT1 162
FunCTionAL DIAGRAm

(LT1160 or 1/2 LT1162)

BOOST

SV+o----B
T GATE DR
TGATE FB
IN TOP

TSOURCE

IN BonOM

UVOUT

B GATE DR

SGND
lT1160
PGND

, ..

12lT1162 GND :•••: •••••••• ;

rEST CIRCUIT

B GATE FB

(LT1160 or 1/2 LT1162)

SV+

BOOST
T GATE DR

INTOP
.".

IN BonOM

T GATE FB

UVOUT

TSOURCE

SGND

B GATE OR

PGND

B GATE FB

PV'

•

(lT1160)
50Q
.".

.".

.".

.".

.".

13-9

LTl 160/LT1 162
TiminG DIAGRAm
2V - - - - - ....- - - - - ,
INTOP
O.8V----~

IN BonOM
O.8V

12V -+----i~--+----+---r_t_Jl_:;;;v~
TOP GATE
ORIVER OV

-+-----1----1---+---1-:-'1

12V -+--+--+.._---...1
sonOM
GATE
DRIVER OV

_+-..1

OPERATion (Refer 10 Functional Diagram)
The LT1160 (or 1/2 LT1162) incorporates two independent driver channels with separate inputs and outputs. The
inputs are nUCMOS compatible; they can withstand
input voltages as high as V+. The 1.4V input threshold is
regulated and has 300mVof hysteresis. Both channels are
noninverting drivers. The internal logic prevents both
outputs from simultaneously turning on under any input
conditions. When both inputs are high both outputs are
actively held low.
The floating supply for the top driver is provided by a
bootstrap capacitor between the Boost pin and the Top
Source pin. This capacitor is recharged each time the
negative plate goes low in PWM operation.
The undervoltage detection circuit disables both channels
.when V+ is below the undervoltage trip point. A separate

13-10

UV detect block disables the high side channel when
VBOOST - VTSOURCE is below its own undervoltage trip
point.
The top and bottom gate drivers in the LT1160 each utilize
two gate connections: 1) a gate drive pin, which provides
the turn on and turn off currents through an optional series
gate resistor, and 2) a gate feedback pin which connects
directly to the gate to monitor the gate-to-source voltage.
Whenever there is an input transition to command the
outputs to change states, the LT1160 follows a logical
sequence to turn off one MOSFET and turn on the other.
First, turn off is initiated, then VGS is monitored until it has
decreased below the turn off threshold, and finally the
other gate is turned on.

LTl160/LTl162
IPPLICATlons InFORmATion
lwer MOSFET Selection

Paralleling MOSFETs

nce the LT1160 (or 112 LT1162) inherently protects the
p and bottom MOSFETs from simultaneous conduction,
ere are no size or matching constraints. Therefore selecm can be made based on the operating voltage and
)S(ON) requirements. The MOSFET BVoss should be
'eater than the HV and should be increased to 2 x HV in
lrsh environments with frequent fault conditions. Forthe
"1160 maximum operating HV supply of60V, the MOSFET
loss should be from 60V to 120V.

When the above calculations result in alower ROS(ON) than
is economically feasible with a single MOSFET, two or
more MOSFETs can be paralleled. The MOSFETs will
inherently share the currents according to their ROS(ON)
ratio as long as they are thermally connected (e.g., on a
common heat sink). The LT1160 top and bottom drivers
can each drive five power MOSFETs in parallel with only a
small loss in switching speeds (see Typical Performance
Characteristics). A low value resistor (100 to 470) in
series with each individual MOSFET gate may be required
to "decouple" each MOSFET from its neighbors to prevent
high frequency oscillations (consult manufacturer's recommendations). If gate decoupling resistors are used the
corresponding gate feedback pin can be connected to any
one of the gates as shown in Figure 1.

Ie MOSFET ROS(ON) is specified at TJ = 25°C and is
Inerally chosen based on the operating efficiency relired as long as the maximum MOSFET junction temIrature is not exceeded. The dissipation while each
OSFET is on is given by:
P =D(los)2(1 +o)ROS(ON)
here Dis the duty cycle and 0 is the increase in ROS(ON)
the anticipated MOSFET junction temperature. From this
luation the required ROS(ON) can be derived:

Driving multiple MOSFETs in parallel may restrict the
operating frequency to prevent overdissipation in the
LT1160 (see the following Gate Charge and Driver Dissipation).
GATE DR

11~;:::t--4

LTl160
GATE FB

,r example, if the MOSFET loss is to be limited to 2W
len operating at 5A and a 90% duty cycle, the required
)S(ON) would be 0.089Qf(1 +0). (1 +0) is given for each
DSFET in the form of a normalized ROS(ON) vs temperare curve, but 0 = 0.007/°C can be used as an approximaIn for low voltage MOSFETs. Thus, if TA= 85°C and the
ailable heat sinking has athermal resistance of 20°C/W,
e MOSFET junction temperature will be 125°C and
= 0.007(125 - 25) = 0.7. This means that the required
)S(ON) of the MOSFET will be 0.0890/1.7 =0.05230,
lich can be satisfied by an International Rectifier IRFZ34.
ansition losses result from the power dissipated in each
DSFET during the time it is transitioning from off to on,
from on to off. These losses are proportional to fx (HV)2
d vary from insignificant to being a limiting factor on
erating frequency in some high voltage applications.

• OPTIONAL 10n

Figure 1. Paralleling MOSFETs

Gate Charge and Driver Dissipation
A useful indicator of the load presented to the driver by a
power MOSFET is the total gate charge OG, which includes
the additional charge required by the gate-to-drain swing.
OG is usually specified for VGS =1OV and Vos =0.8VOS(MAX)·
When the supply current is measured in a switching
application, it will be larger than given by the DC electrical
characteristics because of the additional supply current ~
associated with sourcing the MOSFET gate charge:
...
ISUPPLY= Ioc+ ( -dOG)

dt

l7lJD~

TOP

(dOG)
+
dt BonOM

13-11

LTll 60/LT 1162
APPLICATions InFoRmATion
The actual increase in supply current is slightly higher due
to LT1160 switching losses and the fact that the gates are
being charged to more than 10V. Supply Current vs
Input Frequency is given in the Typical Performance
Characteristics.
The LT1160 junction temperature can be estimated by
using the equations given in Note 2 of the Electrical
Characteristics. For example, the LT11601S is limited to
less than 31 mA from a 12V supply:
TJ = 85°C + (31 mA x 12V x 110°C/W)

=126°C exceeds absolute maximum
In order to prevent the maximum junction temperature
from being exceeded, the LT1160 supply current must be
verified while driving the full complement of the chosen
MOSFET type at the maximum switching frequency.
Ugly Transient Issues
In PWM applications the drain current of the top MOSFET
is a square wave atthe inputfrequency and duty cycle. To
prevent large voltage transients at the top drain, alow ESR
electrolytic capaCitor must be used and returned to the
power ground. The capaCitor is generally in the range of
25~ to 5000~ and must be physically sized for the RMS
currentflowing in the drain to prevent heating and premature failure. In addition, the LT1160 requires a separate
1O~ capaCitor connected closely between Pins 1 and 5
(the LT1162 requires two 1O~ capacitors connected
between Pins 1 and 5, and Pins 7 and 11).
The LT1160 top source is internally protected against
transients below ground and above supply. However, the
gate drive pins cannot be forced below ground. In most
applications, negative transients coupled from the source
to the gate of the top MOSFET do not cause any problems.
Switching Regulator Applications
The LT1160 (or 1/2 LT1162) is ideal as a synchronous
switch driver to improve the efficiency of step-down
(buck) switching regulators. Most step-down regulators
use a high current Schottky diode to conduct the inductor
current when the switch is off. The fractions of the oscil-

13-12

lator period that the switch is on (switch conducting) ani
off (diode conducting) are given by:
Switch ON = (

V~~T ) x Total Period

Switch OFF = ( HV

~~OUT ) x Total Period

Note that for HV > 2VOUT the switch is off longer than it i
on, making the diode losses more significant than th
switch. The worst case for the diode is during a shor
circuit, when VOUT approaches zero and the diode con
ducts the short-circuit current almost continuously.
Figure 2 shows the LT1160 used to synchronously drive.
pair of power MOSFETs in astep-down regulator applica
tion, where the top MOSFET is the switch and the botto~
MOSFET replaces the Schottky diode. Since both conduc
tion paths have low losses, this approach can result in ver
high efficiency (90% to 95%) in most applications. Fa
regulators under 10A, using low ROS(ON) N-channE
MOSFETs eliminates the need for heat sinks. RGS holds th
top MOSFET off when HV is applied before the 12V suppl~
One fundamental difference in the operation of a step
down regulatorwith synchronous switching is that it neve
becomes discontinuous at light loads. The inductor cur
rent doesn't stop ramping down when it reaches zero bu
actually reverses polarity resulting in a constant rippl
current independent of load. This does not cause asignifi
cant efficiency loss (as might be expected) since th
negative inductor current is returned to HV when th
switch turns back on. However, 12R losses will occu
under these conditions due to the recirculating current~
The LT1160 performs the synchronous MOSFET drive in
step-down switching regulator. A reference and PWM ar
required to complete the regulator. Any voltage mode a
current mode PWM controller may be used but the LT3521
is particularly well-suited to high power, high efficienc
applications such as the 10A circuit shown in Figure 4. I
higher current regulators a small Schottky diode across th
bottom MOSFET helps to reduce reverse-recovery switchin
losses.

LTl 160/LT1 162
APPLICATions InFoRmATion

.....

-

HV
BOOST

SV+

TGATE DR

12V-_ PV+

T GATE FB

REFPWM
OUTA
OUTA

T

--

_.....

r---<

LT1160

IJ

±L
~

RGST

RSENSE

TSOURCE
IN TOP

B GATE DR

IN BOTTOM B GATEFB

VaUT

.:!:.'-

:~

~

"*

U'J:J

"

Figure 2. Adding Synchronous Switching to a Step-Down Switching Regulator

Motor Drive Applications
In applications where rotation is always in the same
~irection, asingle LT1160 controlling ahalf-bridge can be
used to drive a DC motor. One end of the motor may be
wnnected either to supply orto ground as seen on Figure
3. A motor in this configuration is controlled by its inputs
iVhich give three alternatives: run, free running stop (coasting) and fast stop ("plugging" braking, with the motor
shorted by one of the MOSFETs).
rod rive a DC motor in both directions the LT1162 can be
used to drive an H-bridge output stage. In this configuration the motor can be made to run clockwise, counter:Iockwise, stop rapidly ("plugging" braking) or free run
[coast) to a stop. A very rapid stop may be achieved by
"eversing the current, though this requires more careful
jesign to stop the motor dead. In practice a closed-loop
:ontrol system with tachometric feedback is usually
lecessary.

.L7lJ!J~

The motor speed in these examples can be controlled by
switching the drivers with pulse width modulated square
waves. This approach is particularly suitable for microcomputers/DSP control loops.
....--+-_-HV

+

LT1160
SV+

BOOST

1---"

'*

TGATE DR ........._f---I

12V

T GATE FB
T SOURCE

I---+---+-cr

IN TOP

B GATE DR ........._f---I

IN BOTTOM

B GATE FB
PGND

1---......--...

Figure 3. Driving a Supply Referenced Motor

13-13

LT1 160/LT1 162
TYPICAL APPLICATions

12V

+

4.7k

~101lF

SV,

+ +
Ef~"J; "J;

2200llF EA
LOW ESR

LT1160
BOOST

14

IRFZ44

T GATE DR

IN TOP

IN BOnOM T GATE FB

0:-

~

RS"

o.oom
5V

T SOURCE

UVOUT

SHUTDOWN ~H+--"'"

L'
70llH

SGND

PV'

PGND

B GATE DR

NC

B GATE FB

+

5400llF

E

WESR

__________~Q0vO~__________~

, MAGNETICS CORE #55585-A2
30 TURNS 14GA MAGNET WIRE

" DALE TYPE LVR-3
ULTRONIX RCS01

Figure 4. 90% Efficiency, 40V to SV 10A Low Dropout Voltage Mode Switching Regulator

12V
2200llF EA

1N4148

+

16

~101lF

15
14

11lF

+
-:;r

25k

, HURRICANE LAB
HL-KM147U

BOOST

14

LT1846
12

7

IN TOP

~~

"J;"J;

1N4148

13
0.11lF 5

LT1160
SV'

TGATE DR

IRFZ44

1k
IN BonOM T GATE FB

Rs"

o.oom
UVOUT

T SOURCE

SGND

PV'

PGND

B GATE DR

NC

B GATE FB

5V

+

10
MBR340

" DALE TYPE LVR-3
ULTRONIX RCS01

Figure S. 90% Efficiency, 40V to SV 10A Low Dropout Current Mode Switching Regulator

13-14

5400llF

Ii"'

LT1 160/LT1 162
TYPICAL APPLICATions
100"F

IN

10k

---1:+

150k
TO.00331'F

ilk

12V

5V

lk

LTl015

3
lk

2

7

3

6

100k~

5

.".-

lk

I

*4

7

~

LT1016

+

~11'F

o.I1'F+

~

.".

~

--14

..L

~
10"F

TO.0033J!F
.".

=:=47J!F

S

*

9

10k

T

lli?I'111
.".1 Ok

95k

13

3

L

r--±

.".

LT105S

~

150k
10k

-

~

_..Q;I1'F

T

BGATE FBA

IRFZ44
I!::;"

BOOST B

IN TOP B

TGATEDRB

IN BOTTOM B TGATEFB B
T SOURCE B

GND B

PV' B

BGATEFBB

BGATE DR B

17

~_..£;I1'F

T

r1L13

I

~I'F

J;

1000"F

~

15

L'
15S"H

%

19
'
BGATE DRA h.

SV'B

I
330k >--

21

IRFZ44
I
I

iL

J;

330k

C·

.~

--,-

~

IR~t:>~~I
I
+ 10l'F

I~

J;

12V

10

..!..

IRI~

PV'A ~414S

GNDA

r- 0:1~

11

-' ";tti'

200k

r

";J;

23

T SOURCE A

~ UV OUT B

~

10k

1'--14
2

7

i.L.

~.".

IN SOTTOMA TGATEFBA

~ UVOUTA

-,-

lk

+~

.....2.

~
.".~

5

.:!:.L

TGATEDRA

INTOPA

I'--S
2

IOO0l'F

BOOST A ~

r-t-l2 SV'A

7

TC442S

lN~4S

LT1162

12-~

...2-~
2

~10"F

~O.I"F

TO. l "F

60VMAX_

~~

95k
T47J!F

10k

i

lOk

'Keel MJ!·CORE #7754S-A7
35 TURNS 14GA MAGNET WIRE
fCARRIER = 100kH,

200k

Figure 6. 200W Class D, 10Hz 101kHz Amplifier
Kool Mil is a registered trademark of Magnetics, Inc.

lEI

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1158

Half-Bridge N-Channel Power MOSFET Driver

Single Input, Continuous Current Protection and Internal Charge
Pump for DC Operation

L7lJ!J~

13-15

L7LIn

UlNJU UUt',\l1, IfUlSl1,lSt',\;§JlS
Final Electrical Specifications

LTCl177 -5/LTCl177 -12

TECHNOLO~G~~~-----ISO-I-a-te-d--M-O-S-F-ET-D-r-iv-e-rS
May 1995

DESCRIPTion

FEATURES

®'i\l

The LTC®1177-S/LTC1177-12 are isolated high-side
MOSFET drivers. When used with an external N-channel
MOSFET, the LTC1177 -S/LTC1177 -12 form an isolated
solid state switch for reliable bounce-free switching operation. The output does not require an auxiliary power
supply to maintain an on-state condition.

• UL Recognized
File E151738 to UL1577
• No Secondary Power Supply
• Drives Any Logic Level FET
• Low Input Current: 1mA Typ (LTC1177-S),
2.SmA Typ (LTC1177 -12)
• Turns On in 1ms Typ and Turns Off in 1ms Typ
• 2S00VRMS of Isolation Voltage
• Isolates Input from High Voltage Transients at Load
• Clean, Bounce-Free Switching
• Current Limit
• Small Outline Package

Two lead frame capacitors are used to transfer energy
from the inputto drive the gate ofthe MOSFET and provide
the necessary isolation. Unlike opto-isolated FET drivers,
the input current for the LTC1177-S is only 1mA and
2.SmA for LTC1177 -12. It also does not have the aging
problems endemic to opto-couplers.

APPLICATions

Both devices provide 2S00VRMS (1 minute) or 3000VRMS
(1 second) of output-to-input isolation.

•
•
•
•

The LTC1177-S/LTC1177-12 are available in the 18-pin
PDW or 28-pin SO Wide package.

Solid State Relay
Isolated Solenoid Driver
Isolated Motor Driver
Isolated Lamp Driver

LT, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Isolated High-Side Switch
f = 50Hz
5VOR12V n n
OV...J LJ L

. - - - - - - - - - , 18
1 VIN
GNDI
LTC1177-5
LTCI177-12

V+ = 40V
ISOLATION BARRIER
- ---------

+

471lF

T

50V
MTD3055EL

7 NC

NC

8. NC

GND2

OUT

SENSE

10

+ - - - - - - -.......
ROUT

500

13-16

VOUT

LTCl 177-5/LTC1l77-1 2
ABSOLUTE mAXimum RATinGS
Input Voltages
VIN (LTC1177-5) ....................... 6V to
VIN (LTC1177-12) ..•.•.•..•.•...• 13.2V to
Sense (LTC1177-5) .•.•.••.•••.••.•... 6V to
Sense (LTC1177 -12) .............. 12V to
)utput Voltages .......................... 12V to

(GND1 - 0.3V)
(GND1- 0.3V)
(GND2 - 0.3V)
(GND2 - 0.3V)
(GND2 - 0.3V)

Operating Temperature Range
Commercial .•.•••..••.••.•.•.••.•.•..••.•••••••.••••.••• O°C to 70°C
Industrial ........................................... -40°C to 85°C
Storage Temperature Range •.............•••• -65°C to 150°C
Lead Temperature (Soldering, 10 sec) •...••..•.••••.••. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER PART
NUMBER
TOP VIEW

TOP VIEW

ORDER PART
NUMBER
LTC1177CSW-5
LTC1177CSW-12
LTC1177ISW-5
LTC11771SW-12

LTC1177CN-5
LTC1177CN-12
LTC11771N-5
LTC1177IN-12

N PACKAGE
18-LEAD PDlP
TJMAX =125°C, OJA =11 QOC/W

SWPACKAGE
28·LEAD PLASTIC SO WIDE
TJMAX =125°C, 9JA= 125'C/W

;onsult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS
IYMBOL PARAMETER
Output Voltage (Refer to GND2)
lOUT

IN
LIM

Input Current
Current Limit

ON

Turn On Time

OFF
'ISO

Turn Off Time
Isolation Voltage

CM

Common-Mode Slew Rate

L7lJD~

VIN =5V, TA =25°C, unless otherwise noted.

CONDITIONS
COUT =1000pF, No Load (N Pkg)
COUT =1000pF, No Load, VIN =4.75V (N Pkg)
COUT =1000pF, No Load (SW Pkg)
COUT =1000pF, No Load, VIN =4.75V (SW Pkg)
CIN =1000pF
RSENSE =1Q (LTC1177C-5)
RSENSE =1Q (LTC11771-5)
COUT =1000pF, No Load (LTC1177C-5)
COUT =1000pF, No Load (LTC11771-5)
COUT =1000pF, No Load
1 Minute (Note 1)
1 Second
VOUT < 1.5, COUP 1000pF

••
••
•
••
••
•

MIN
6.5
5.5
7.0
6.0
400
350

LTC1177-5
TYP
MAX
7.5
10
6.5
10
B.O
10
7.0
10
1.0
1.5
620
BOO
620
900
1.0
4.0
1.0
4.5
1.0
l.B

UNITS
V
V
V
V
rnA
rnA
rnA
ms
ms
ms

1000

VRMS
VRMS
V/IJS

2500
3000

13-17

II

LTC1l77-5/LTCl177-12
ELECTRICAL CHARACTERISTICS

VIN = 12V, TA = 25°C unless otherwise noted.
LTC1177-12

SYMBOL

PARAMETER

CONDITIONS

VOUT

Output Voltage (Refer to GND2)

COUT =1000pF, No Load (LTC1177C-12, N Pkg)
CouP 1000pF, No Load (LTC1177C-12, SW Pkg)
.COUT =1000pF, VIN =11.4V (LTC1177C-12, N Pkg)
COUT =1000pF, VIN =11.4V (LTC1177C-12, SW Pkg)
COUT =1000pF, No Load (LTC11771-12, N Pkg)
COUT =1000pF, No Load (LTC11771-12, SW Pkg)
COUT =1000pF, VIN =11.4V (LTC11771-12, SW Pkg)

liN

Input Current

CIN =1000pF (LTC1177C-12)
CIN =1000pF (LTC11771-12)

ILiM

Current Limit

toN

Turn On Time

RSENSE =1n (LTC1177C-12)
RSENSE =1n (LTC11771-12)
COUT =1000pF, No Load (LTC1177C-12)
COUT =1000pF, No Load (LTC11771-12, N Pkg)
COUT =1000pF, No Load (LTC11771-12, SW Pkg)

tOFF

Turn Off Time

VIsa

Isolation Voltage

••
••
•••
••
••
•
•
•
•

COUT =1000pF, No Load (LTC1177C-12)
COUT =1000pF, No Load (LTC11771-12, N Pkg)
COUT =1000pF, No Load (LTC11771-12, SW Pkg)
1 Minute (Note 1)
1 Second

TCM

Common-Mode Slew Rate

MIN

TYP

MAX

4.65
5.00
4.40
4.60
4.50
4.75
4.50

5.2
5.7
4.9
5.3
5.2
5.7
5.3

8
8
7
7
8
8
7

V
V
V
V
V
V
V

2.5
2.5

3.0
3.4

mA
mA

620
620

800
900

mA
mA

1.0
1.0
1.0

2.5

ms
ms
ms

1.0
1.0
1.0

1.2

400
350

UNITS

2.5

ms
ms
ms

1.5

2500

VRMS

3000

VRMS
1000

VOUT < 1.5V, Cour- 1000pF

The. denotes specifications which apply over the full operating
temperature range.

V/IJS

Nole 1: Value derived from 1 second test.

TYPICAL PERFORmAnCE CHARACTERISTICS
LTC1177-12
Turn Off Time vs Temperature
1.6

1.2
VIN = 12V
1.1

!

1.0

!!!

~ 0.9

~

1.6,---,---,----::;;>'1
TA= 25°C
1.4 VIN = 12V-l-----+-~_£.j

I

VIN = 12V
1.4

~ 0-.
........

o

;2

~ 0.8

!w

~

25

50

~

~ 1.0

SO-28

;2

~ 0.8

~

75

100

0.6

125

~

~

0.4
-55 -25

7

.J

11n-12 1301

., 1.2

t----+-----;~+---:."c_----j

S
~ 1.0

>=

~ ~0-28

t-----I7'---7-+------j

;2

o 0.8 t-----7'-f-:7'<-..::-=-=+------j

;2

a:

~ 0.6 jL-----:;;~+_--+-----I
0.41-"'---+_--+-----1

a

25

50

75

TEMPERATURE (OC)

TEMPERATURE (Oc)

13-18

N-18

o

N-ll~

a

1.2

:;;

0.7
0.6
-55 -25

LTC1177-12
Turn On Time to VOUT = 4.5V vs
Output CapaCitance

LTC1177-12
Turn On Time vs Temperature

100

125

0.2 '--_ _.L..-_ _- ' - - _ - - - '
500
1000
1500
2000
OUTPUT CAPACITANCE (pF)

LTC1l77 -5/LTCl177 -12
rYPICAL PERFORmAnCE CHARACTERISTICS
LTC1177-12
Turn-Off Time to Vour =1V vs
Output Capacitance

LTC1177-12
Output Current vs Output Voltage

1.1 . - - - - - - - - , - - - - , - - - - - ,

14
12

~ 1.0 1------+------otlY''---+----j

5

LTC1177-12
Output Voltage vs Temperature

TA 25°C
VIN=12VNO LOAD

1\.'\

"~"-

0.9 I---+----+---+----j

80-~

>

!5

t--..

o

o

5.6

"-

§

~

5.4
5.2

I--

,- ~
N-18 , /

/'

./

/

/

/'

/

5.0
-55 -25

3
OUTPUT VOLTAGE (V)

,;'

/

'"'"

...........
2000

6.0

~ 5.8
o

~-28

~

1000
1500
OUTPUT CAPACITANCE (pF)

VIN = 12V
NO LOAD

6.2
~

N-~

....-

6.4

~

1\

0
25 50
75
TEMPERATURE (0C)

100

125

1'77-12604

3.0
2.8

[ 2.6

j 2.4

TA = k5°C

/

80~

I~ ~

~ 2.2
)

~

VIN = 12V
NO LOAD

~r--.

2.0

"~ ~

N-18

80-28

./

"" ~

1.6
-55 -25

l/:: ~

~

1.8

0
25 50
75
TEMPERATURE (OC)

100

LTC1177-12
Input Current vs Input Voltage

LTC1177-12
Output Voltage vs Input Voltage

LTC1177-12
Input Current vs Temperature

125

~ ~8

/

~

9

10

TA = k5°C

~ 2.6

a:
a:

N~

::>

~ 2.2

::>

"~

1.8

11
12
13
INPUT VOLTAGE (V)

~

3.0

1

V
3

3.4

14

15

1.4

V
9

V
10

V

~

~

11
12
13
INPUT VOLTAGE (V)

r

14

15

1177·12G08

»In FUnCTiOnS
rlN: Voltage Input, 5.25V ~ VIN ~ 4.75V (LTC1177 -5) and
2.6V ~ VIN ~ 11.4V (LTC1177-12). Connect a O.01W
apacitor between VIN and GND1 when the source imped.nce is high or the VIN connection is long_

IUT: Output Voltage. The output voltage level is 8V (typ)
or SW package and 7.5V (typ) for N package (LTC1177i) with 5V at VIN pin; 5.7V (typ) for SW package and 5_2V
typ) for Npackage (LTC1177-12) with 12VatVIN pin. This
lin is to drive the gate of the external N-channel MOSFET.

L7lJ[J~

SENSE: Current Limit Sense Input. Connecting a1g resistor from the Sense pin to GND2 would limit the current
through the power MOSFET at around 620mA (tyP)-IUM =
620mVlRsENSE·
GND2: Floating Ground Connects to the source of the
external N-channel MOSFET_
GND1: Input Ground_ The ground connection of the input
control signal.

13-19

•

LTCl177 -5/LTCl177 -12
BLOCK DIAGRAm
ISOLATION BARRIER..-_ _....
OSCILLATOR

1"$:-"_-1 '::loo---I

I - -......---OUT
SENSE

GND1

SWITCHinG WAVEFORms

2.5V OR 6V

VOUT
1V
OV

TYPICAL APPLICATions
Isolated High-Side Switch with Fold-Back Current Limit

Solid State Relay

~
ISOLATION BARRIER
VIN

OUT

,-;1--,

I -.......---t--I

ISOLATION BARRIER
I

n

5VOR12V
OV.J L

1

20M

V+ = 24V

AC60Hz

VIN

I
I

1

I
I

1 Si9944DY
LTC1177-5
LTC1177-12
I
I
I
I

I

1

,_-T-_:

SENSE

I

GND1

:

GND2

t-....----'

SENSE
GND1

OUT
1177TA03

13-20

I

LTC1177-5
LTG1177-12

1
1

'--_-++-I-I

OUT H - - - I

:

1

GND2

1-_--....

LTCl177-5/LTCl177-12
TYPICAL APPLICATions
Solid State Relay

-f\:;- AC 60Hz

ISOLATION BARRIER

1--;3--,
t----+
I'

:

L_ _ _ _ .J

LTC1177-5
LTC1177-12

20M
IRFR224

SENSE
GND1

GND2

':"

OUT

VIN

LTC1177-5
LTC1177-12
SENSE
GND1

GND2

':"

Fully Floating 50°F to 100°F Thermostat

17,
5V OR 12V

r=

49.9k
9

11
LTC1177-5
LTC1177-12

4.32k
5k

~
2
3

Vp_p

VIN

LTC1041

SET POINT

OSC

GND
*8

~11

6.81k

....!

GND

DELTA

DELTA.= O.5°F

49.90

~t

V+ 8

ON/OFF

~

rL-

I

10M

1=

+
==10"F

=1"F

560

1,3

I

!.fit"
1*
I

1cl'OO"'

26VAC
2-WIRE
THERMOSTAT

!.--- -

Si9955DY

5,

ALL RESISTORS 1°Y.
• YELLOW SPRING S INSTRUMENT CO. INC. PIN 44007
DRIVING THERMI STaR WITH Vp_p ELIMINATES 3.8°F
SELF-HEATING ERROR

II

RELATED PARTS
PART NUMBER
LTC1145/LTC1146
LT1158
LTC1255

DESCRIPTION
Low Power Digital Isolator
Half-Bridge N-Channel Power MOSFET Driver
Dual 24V High-Side MOSFET Driver

COMMENTS
Can Pass Digital Information Across Isolation Barrier
Can Be Used for Motor Speed Control
User Set Current Limiting

13-21

L.YLIn
.

UU~U

U ULn'llS

IIllLSlSLSLn'I~LS

Final Electrical Specifications

LTC 1274/LTCl 277

TECHNOLO~G~~~-----12---Bi-t,-1-O-m-W-,-l-O-O-k-SP-S
ADCs with 1JlA Shutdown
June 1995

FEATURES

DESCRIPTion

• Low Power Dissipation: 10mW Typical
• Sample Rate: 100ksps
• Samples Inputs Well Beyond Nyquist, 71 dB S/(N + D)
and 77dB THO Minimum at fiN = 100kHz
• Single Supply 5V or ±5V Operation
• ±O.5LSB Maximum INL and
±0.75LSB Maximum DNL (A Grade)
• Power Shutdown to 1/lA in Sleep Mode
• 160~ Nap Mode (LTC1277) with Instant Wake-Up
• 30ppm/oC (Max) Internal Reference (A Grade) Can
Be Overdriven
• Internal Synchronized Clock
• OV to 4.096V or ±2.048V Input Ranges (1 mVlLSB)
• 24-Lead SO Wide Package

The LTC@1274/LTC1277 are 8~ sampling 12-bit AID
converters which draw only 2mA (typ) from asingle 5V or
±5V supplies. These easy-to-use devices come complete
with a 2~ sample-and-hold, a precision reference and an
internally trimmed clock. Unipolar and bipolar conversion
modes add to the flexibility of the ADCs.

The AID converters convert OV to 4.096V unipolar inputs
from a single 5V supply or ±2.048V bipolar inputs from
±5V supplies.

APPLICATions
•
•
•
•
•
•

Two power-down modes are available in the LTC1277. In
Nap mode, the LTC1277 draws only 160~ and the instant
wake-up from Nap mode allows the LTC1277 to be powered down even during brief inactive periods. In Sleep
mode only 1~ will be drawn. A REFRDY signal is used to
show the ADC is ready to sample after waking up from
Sleep mode. The LTC1274 also provides the Sleep mode
and REFRDY signal.

Battery-Powered Portable Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Spectrum Analysis

The LTC1274 has a single-ended input and a 12-bit
parallel data format. The LTC1277 offers a differential
input and a 2-byte read format. The bipolar mode is
formatted as 2's complement for the LTC1274 and offset
binary for the LTC1277.
.u, LTC and LT are registered trademarks 01 Linear Technology Corporation.

TYPICAL APPLICATiOn
Single 5V Supply, 10mW, 100kHz, 12-Bit ADC
LTC1277
ANALOG 1 A +
DIFFERENTIAL INPUTS 2 IN
2.42V
(OV TO 4.096V) 3 AINVREF OUTPUT ---:-4I~"---"-I VREF
4 AGNO
5 REFROY
6 SLEEP
7 NAP

8 07
9 06
10 05

PARAt~g
BUS

11 04
12 OGNO

5V

V

...-----;-.--4

1-"2.:,.4

DO 23

Vss~---.
BUSY 22
1---+--4
CS 21
Ali 20

CONVST 19
HBEN 18
OPTIONAL 3V SUPPLY,
17
FOR BUSY, REFROY
VLDGIC
----- ANOOATABITSTO
00/8 16
INTERFACE WITH 3V
01/9 15
PROCESSOR

~
~

12
11
10

74
68
en
62 ~
56
50 :5

I.

NYQ~I~TIFWJ~~EN6y

s;

9

8

ffi

gj

::;;

+

'"
:::>

c

z

~

~
~

~
5

.3

3

Co

02110 14
03/11 13

~~~§~~UlTC1274171'TAG1
13-22

Effective Bits and SignaHo-(Noise + Distortion)
vs Input Frequency

.!:!

o

lSAMPLE = 100ksps

1

10
100
INPUT FREQUENCY (kHz)

1000

LTC1274177oTA02

LTC 1274/LTCl 277
ABSOLUTE mAXimum RATinGS
(Noles 1, 2)

Supply Voltage (Voo) ................................................ 7V
Negative Supply Voltage (Vss)
Bipolar Operation Only .......................... -6V to GND
Total Supply Voltage (Voo to VSS)
Bipolar Operation Only ......... .................. ............ 12V
Analog Input Voltage (Note 3)
Unipolar Operation ................... - O.3V to Voo + O.3V
Bipolar Operation ............... Vss - O.3V to Voo + O.3V
Digital Input Voltage (Note 4)
Unipolar Operation .............................. - O.3V to 12V
Bipolar Operation .......................... Vss - O.3V to 12V

Digital Output Voltage
Unipolar Operation ................... - O.3V to Voo + O.3V
Bipolar Operation ...................... -O.3V to Voo + O.3V
Power Dissipation ............ ........... ..... ............. .... 500mW
Operating Temperature Range
Commercial ............................................ O°C to 70°C
Industrial ........................................... -40°C to 85°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

PACKAGE/ORDER InFORmATiOn
ORDER
PART NUMBER

TOP VIEW

ORDER
PART NUMBER

TOP VIEW

LTC1274CSW
LTC1274AISW
LTC12741SW

LTC1277CSW
LTC1277AISW
LTC1277ISW

13 03111

---':111..-_.....J- (011 = MSB)

SWPACKAGE
24-LEAO PLASTIC SO WIDE

SW PACKAGE
24-LEAO PLASTIC so WIDE

Consult factory for Military grade parts.

conVERTER CHARACTERISTICS
PARAMETER

(Note 7)

Differential Linearity Error
Offset Error

(Note 8)

Gain Error
Gain Error Tempco

LTC1274AJLTC1277A
MIN
TYP
MAX

CONDITIONS

Resolution (No Missing Codes)
Integral Linearity Error

Wilh Inlernal Reference (Noles 5, 6)

10UT(REF)

=0

•
•
•
•
•

LTC1274/LTC1277
MIN
TYP
MAX

12

12

±5

±O.5
±O.75
±4
±5
±15
±30

UNITS
Bits

±1
±1
±5

±10

LSB
LSB

±7

LSB
LSB

±20
±45

LSB
ppm/oC

13-23

LTC 1274/LTCl 277
AnALOG InpUT

(Note 5)

SYMBOL PARAMETER

CONOITIONS

VIN

Analog Input Range (Note 10)

4.75V ::;; Voo ::;; 5.25V (Unipolar)
4.75V ::;; Voo ::;; 5.25V, -5.25V ::;; Vss ::;; - 2.45V (Bipolar)

liN
CIN

Analog Input Leakage Current
Analog Input Capacitance

CS = High
Between Conversions (Sample Mode)
During Conversions (Hold Mode)

DynAmiC ACCURACY
PARAMETER

CONDITIONS

S/(N + D)

Signal-to-Noise
Plus Distortion Ratio

50kHz Input Signal
100kHz Input Signal

IMD

•

V
V

IlA
pF
pF

45
5

•

Total Harmonic Distortion 50kHz Input Signal
Up to 5th Harmonic
100kHz Input Signal
Peak Harmonic or
Spurious Noise

50kHz Input Signal
100kHz Input Signal

Intermodulation Distortion

flN1

LTC1274A/LTC1277A
MIN
TYP
MAX

LTC1274/LTC1277
MIN
TYP
MAX

73
72.5

73
72.5

71

-84
-82

•

= 96.95kHz, flN2 = 97.68kHz
2nd Order Terms
3rd Order Terms

70

-82

UNITS
dB
dB

-77

-84
-82

-76

dB
dB

-77

-84
-82

-76

dB
dB

-84

•

-78
-81

-78
-81

dB
dB

Full Power Bandwidth

2

2

MHz

Full Linear Bandwidth
[S/(N + D) ~ 68dB]

400

400

kHz

InTERnAL REFEREnCE CHARACTERISTICS

(Note 5)

PARAMETER

CONDITIONS

LTC1274A/LTC1277A
MIN
TYP
MAX

LTC1274/LTC1277
MIN
TYP
MAX

VREF Output Voltage

lOUT = 0

2.400

2.400

VREF Output Tempco
VREF Line Regulation

lOUT = 0
4.75V::;; Voo::;; 5.25V
-5.25V::;; Vss ::;; -4.75V

VREF load Regulation

701lA ~ lOUT ~ -5mA

•

SYMBOL PARAMETER
High level Input Voltage
low Level Input Voltage
Digital Input Current

VIH
VIL
liN

Digital Input Capacitance
High Level Output Voltage, All logic Outputs

13-24

2.420
±5

2.440
±30

0.01
0.01

VIN = OV to Voo
Voo = 4.75V
10 = -101lA
10 = -2001lA

2.440
±45

UNITS
V
ppm/oC
LSBN
LSBN

lSB/mA

2

(Note 5)
LTC1274AJLTC1277A
LTC1274/LTC1277
MIN
TYP
MAX

CONDITIONS
Voo= 5.25V
Voo = 4.75V

2.420
±10
0.01
0.01

2

DIGITAL InpuTS AnD DIGITAL OUTPUTS

CIN
VOH

UNITS

(Notes 5,9)

SYMBOL

THD

••

LTC1274AJLTC1277A
LTC1274/LTC1277
MIN
TYP
MAX
Oto 4.096
±2.048
±1

•
•
•
•

2.4
0.8
±10

4.0

UNITS
V
V

IlA

5

pF

4.7

V
V

LTC 1274/LTCl 277
DIGITAL InpUTS AnD DIGITAL OUTPUTS
SYMBOL PARAMETER
VOL

Low Level Output Voltage,
All Logic Outputs

LTC127 4A/LTC1277A
LTC1274fLTC1277
MIN
TYP
MAX

CONDITIONS
Voo =4.75V
10 =1601lA
10 =1.6mA

10l

High-Z Output Leakage 011 to 00/8

COl

High-Z Output Capacitance 011 to 00/8

VOUT =OV to Voo, CS High
CS High (Note 10)

ISOURCE
ISINK

Output Source Current

VOUT =OV

Output Sink Current

VOUT =Voo

POWER REQUIREmEnTS

(Note 5)

0.05
0.10

•
•
•

0.4

V
V

±10

IlA

15

mA

10

mA

(Note 5)

CONDITIONS

Voo

Positive Supply Voltage (Notes 11,12)

Unipolar and Bipolar Mode

4.75

5.25

VSS

Negative Supply Voltage (Note 11)

Bipolar Mode Only

-2.45

-5.25

100

Positive Supply Current

fSAMPLE =100ksps
NAP =OV (LTC1277 Only)
SLEEP =OV

Iss

Negative Supply Current

fSAMPLE =100ksps, Bipolar Mode Only
SLEEP =OV

PDlSS

Power Dissi pation

fSAMPLE =100ksps
NAP =OV (LTC1277 Only)
SLEEP =OV (Unipolar/Bipolar)

TiminG CHARACTERISTICS
SYMBOL

PARAMETER

CONDITIONS

Maximum Sampling Frequency

(Note 11)

tCONV

Conversion Time

tACO
t,

Acquisition Time
CSJ, to ROJ, Setup Time

(Note 10)

t2

CSJ, to CONVST J, Setup Time

(Note 10)

t3

NAP! to CONVST J, Wake-Up Time

(LTC1277 Only) (Note 11)

t4

CONVST Low Time

(Note 13)

t5

CONVSTJ, to BUSY J, Delay

CL =100pF

t6

Data Ready Before BUSY!

CL =100pF

t7

Delay Between Conversions

(Note 11)

t8

Wait Time RDJ, After BUSY!

(Note 10)

t9

Data Access Time After RDJ,

CL =20pF (Note 10)
CL =100pF

Bus Relinquish Time

••
•
•
•
••
•

UNITS
V
V

2
160
0.3

4
320

40
0.3

70
5

IlA
IlA
IlA
IlA

10
0.8

20
1.8
25/50

mW
mW
!1W

LTC1274A/LTC1277A
LTC1274/LTC1277
TYP
MAX
MIN

UNITS

5

mA

(Note 5) See Figures 4 to 8.

fSAMPLE(MAX)

t,o

pF

-10

LTC1274A/LTC1277A
LTC1274/LTC1277
TYP
MIN
MAX

SYMBOL PARAMETER

UNITS

CL =100pF

•
•
•
•
•

•
•
•
•
•
•
•

•

100

ksps
6

8

0.35

2

0

ns
ns

30
2

!1S
ns

40
70
20

150

ns

0.35

2

!1S

50

110
140

ns
ns

65

125
170

ns
ns

60

90
100

ns
ns

ns

65

-20

20
20

!1S
!1S

ns

13-25

II

LTC 1274/LTCl 277
TiminG CHARACTERISTICS
SYMBOL
t11
t12
t13
t14
t15
t16
t17
t18

PARAMETER
RD Low Time
CONVST High Time
Aperture Delay of Sample-and-Hold
SLEEPt to REFRDyt Wake-Up Time
HBENt to High Byte Data Valid
HBEN! to Low Byte Data Valid
HBENt to RD! Setup Time
RDt to HBEN! Setup Time

(Nole 5) See Figures410 8.
LTC1274AJLTC1277A
LTC1274/LTC1277
MIN
TYP
MAX

CONDITIONS
(Note 10)
(Notes 10, 13)

•

•

10!d' Bypass at VREF Pin
CL = 100pF (LTC1277 Only)
CL = 100pF (LTC1277 Only)
(Note 10) (LTC1277 Only)
(Note 10) (LTC1277 Only)

The. denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA =25°C.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below Vss (ground for unipolar
mode) or above Voo, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below Vss (ground for
unipolar mode) or above Voo without latch-Up.
Note 4: When these pin voltages are taken below Vss (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below Vss (ground for unipolar mode)
without latch-up. These pins are not clamped to Voo.
Note 5: Voo = 5V (Vss = -5V for bipolar mode), fSAMPLE = 100ksps,
tr = tf = 5ns unless otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpOints of the transfer curve.
The deviation is measured from the center of the quantization band.

•
•
•
•

t9
40
35
4
35
45

UNITS
ns
ns

100
100

10
10

ns
ms
ns
ns
ns
ns

Note 8: For LTC1274, bipolar offset is the offset voltage measured from
-0.5LSB when the output code flickers between 0000 0000 0000 and
111111111111. For LTC1277, bipolar offset voltage is measured from
-0.5LSB when the output code flickers between 011111111111 and
100000000000.
Note 9: The AC tests apply to bipolar mode only and the S/(N + D) is 71 dB
(typ) for unipolar mode at 100kHz input frequency.
Note 10: Guaranteed by design, not subject to test.
Note 11: Recommended operating conditions.
Nole 12: AIN must not exceed Voo or fall below Vss by more than 50mV to
specified accuracy.
Nole 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 400ns after conversion start (Le., before the first bit decision) or
after BUSY rises (Le., after bit test). See timing diagrams mode 1a and 1b
(Figures 4, 5).

Pin FunCTions
LTC1274
AIN (Pin 1): Analog Input. OV to 4.096V (unipolar) or
±2.048V (bipolar).
VREF (Pin 2): 2.42V Reference Output. Bypass to AGND
(10JlFtantalum in parallel with O.1JlFceramic). VREFcan be
overdriven positive with an external reference voltage.
AGNO (Pin 3): Analog Ground.
011 to 04 (Pins 4 to 11): Three-State Data Outputs. 011
is the Most Significant Bit.
OGNO (Pin 12): Digital Ground.

13-26

03 to 00 (Pins 13 to 16): Three-State Data Outputs.
REFROY (Pin 17): Reference Ready Signal. It goes HIGH
when the reference has settled after SLEEP and the ADC is
ready to sample.
SLEEP (Pin 18): Sleep Mode Input. Tie this pin to LOW to
put the ADC in Sleep mode and save power (REFRDY will
go LOW). The device will draw 1pA in this mode.
CONVST (Pin 19): Conversion Start Signal. This active
LOW signal starts C!...f.onversion on its falling edge (to
recognize CONVST, CS has to be LOW.)

LTC 1274/LTCl 277

Pin FunCTions
RO (Pin 20): Read Input. This enables the output drivers
when CS is LOW.
es (Pin 21): The Chip Select input must be lowforthe ADC
to recognize CONVST and RD inputs.
BUSY (Pin 21): The Busy output shows the converter
status. It is LOW when a conversion is in progress. The
rising Busy edge can be used to latch the conversion
result.
Vss (Pin 23): Negative 5V Supply. -5V will sel~ct ~ipol~r
operation. Bypass to AGND with .0.1w ceram~c. Tie this
pin to analog ground to select unipolar operation.
Voo (Pin 24): Positive 5V Supply. Bypass to AGND (10W
tantalum in parallel with 0.1 W ceramic).

lTC1277
AIN+ (Pin 1): Positive Analog Input. (AIN+ - AIN -) =OV to
4.096V (unipolar) or ±2.048V (bipolar).
AIN- (Pin 2): Negative Analog Input. T~is pin need~ to be
free of noise during conversion. For single-ended Inputs
tie AIN - to analog ground.
VREF (Pin 3): 2.42V Reference Output. B~pass to AGND
(1 Ow tantalum in parallel with 0.1Wceramlc). VREF can be
overdriven positive with an external reference voltage.
AGNO (Pin 4): Analog Ground.

07 to 04* (Pins 8 to 11): Three-State Data Outputs.
OGNO (Pin 12): Digital Ground.
03/11 to 00/8* (Pins 13 to 16): Three-State Data Outputs.
D11 is the Most Significant Bit.
VLOGIC (Pin 17): 5V or 3V Digital Power Supply. This pin
allows a 5V or 3V logic interface with the processor. All
logic outputs (Data Bits, BUSY and REFRDY) will swing
between OV and VLOGIC.
HBEN (Pin 18): High Byte Enable Input. The four .Mo~t
Significant Bits will appear at pins 13 t~ 16 when th.ls pin
is HIGH. The LTC1277 uses straight binary for Unipolar
mode and offset binary for bipolar mode.
eONVST (Pin 19): Conversion Start Signal. This active I?w
signal starts a conversion on its falling edge (to recognize
CONVST, CS has to be LOW).
RO (Pin 20): Read Input. This enables the output drivers
when CS is LOW.
es (Pin 21): The Chip Select input ~ust be LOW for the
ADC to recognize CONVST and RD Inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is LOW when a conversion is in progress.
Vss (Pin 23): -5V negative supply will sele~t b.ipol~r
operation. Bypass to AGND with a. 0.1 W cera~lc. Tie thiS
pin to analog ground to select Unipolar operation.

REFROY (Pin 5): Reference Ready Signal. It goes HIGH
when the reference has settled after SLEEP and the ADC is
ready to sample.

Voo (Pin 24): 5V Positive Supply. By~ass to AGND (10W
tantalum in parallel with 0.1 W ceramic).

SLEEP (Pin 6): Sleep Mode Input. Tie this pin to LOW ~o
put the ADC in Sleep mode and save power (REFRDY Will
go LOW). The device will draw 1~ in this mode.

Table 1 LTC1277 Two-Byte Read Data Bus Status

NAP (Pin 7): Nap Mode Input. Pulling this pin LOW will
shut down all currents in the ADC except the reference. In
this modetheADC draws 160~. Wake-up from Nap mode
is about 2j.1S.

'The LTC1277 bipolar mode is in offse1 binary.

DATA
OUTPUTS

07

06

05

04

LOW Byte DB? DB6 DB5 DB4
HIGH Byte LOW LOW LOW LOW

03/11

02{10

DB3

DB2

DB1

DBO

DB11

DB10

DB9

DB8

01/9 00/8

m
13-27

LTC1274/LTC1277
BLOCK DIAGRAmS
LTC1274
CSAMPLE
AIN

-+-------0

VREF

-+--------,

~---III---'

VDD
ZEROING SWITCHES

Vss

(OV FOR UNIPOLAR MODE OR
-5V FOR BIPOLAR MODE)

.....- - - 0...

REFROY

_+-__.....

AGNO
OGNO
011

J-r-- DO

L-_ _ _ _ _ _ _

LTC1274'BD

LTC1277

AIN+
AIN-

CSAMPLE

:-0---1

VDD
ZEROING SWITCHES

VREF

VSS
(OV FOR UNIPOLAR MODE OR
-5V FOR BIPOLAR MODE)

REFRDY
AGND
DGND
D7
D1/9
DO/8

HBEN SLEEP NAP CONVST

13-28

Rli cs

BUSY

VLDGIC
3V OR 5V

LTC 1274/LTCl 277
TiminG DIAGRAm
CS to RD Setup Timing

CS to CONVST Setup Timing

:~~
LTC12741n·roo1

NAP to CONVST Setup Timing (LTC1277)

SLEEP to REFRDY Wake-Up Timing
SLEEP

-:1'
---I

114

rr=-.--

REFRDY - - '
LTC1274177·TDIJ3

APPLICATions InFoRmATion
Driving the Analog Input
The analog input of the LTC1274/LTC1277 is easy to
drive. It draws only one small current spike while charging the sample-and-hold capacitor at the end of conversion. During conversion the analog input draws only a
small leakage current. The only requirement is that the
amplifier driving the analog input must settle after the
small current spike before the next conversion starts.
Any op amp that settles in 2~ to small current transients
will allow maximum speed operation. If slower op amps
are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADCs' AIN input include the Lf"l1 006,
LT1007, LT1220, LT1223 and LT1224 op amps.

the conversion result. It is critical that the AIN- input
voltage be free of noise and settles completely during the
conversion.
Internal Reference
The ADCs have an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmed to 2.42V.lt is internally connected to the DAC and
is available at pin 2 (LTC1274) or pin 3 (LTC1277) to
provide up to 1rnA current to an external load.

LTC1277 AIN+/AIN-Input Settling

For minimum code transition noise the reference output
should be decoupled with a capaCitor to filter wideband
noise from the reference (1 0J,lf tantalum in parallel with a
0.1J,lf ceramic).

The input capacitorforthe LTC1277 is switched onto the
AIN+ input during the sample phase. The voltage on the
AIN+ input must settle completely within the sample
period. Atthe end ofthe sample phase the input capaCitor
switches to the AIN- input and the conversion starts.
During the conversion, the AIN+ input voltage is effectively "held" by the sample-and-hold and will not affect

The VREF pin can be driven with a DAC or other means to
provide input span adjustment. The VREF pin must be
driven to at least 2.45V to prevent conflict with the internal
reference. The reference should be driven to no more than
3V to keep the input span within the 5V supply in unipolar
mode. In bipolar mode the reference should be driven to
no more than 5V, the positive supply voltage of the Chip.

13-29

m

LTC 1274/LTCl 277
APPLICATions InFoRmATion
Figure 1 shows an LT1006 op amp driving the reference
pin. In unipolar mode, the reference can be driven up to
2.95V at which pOint it will provide aOV to 5V input span.
Forthe bipolar mode, the reference can be driven up to 5V
at which point it will provide a±4.23V input span. Figure
2 shows a typical reference, the LT1 019A-2.5 connected
to the LTC1274. This will provide an improved drift (equal
to the maximum 5ppm/o C of the LT1019A-2.5) and a
±2.115V (bipolar) or 4.231 V (unipolar) full scale.
.INPUT RANGE:
±0.846VREF(OUT)
IN BIPOLAR MODE AND - - - - - - - - - - - - .
OVREF(OUT) TO
1.69VREF(OUT) IN
UNIPOLAR MODE

Wire wrap boards are not recommended for high resolution or high speed AID converters. To obtain the best
performance from the LTC1274/LTC1277, a printed circuit board is required. Layoutforthe printed circuit board
should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
b~ taken not to run any digital track alongside an analog
signal track or underneath the ADC. The analog input
should be screened by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in
Figure 3. For bipolar mode, a 0.1~ ceramic provides
adequate bypassing forthe Vss pin. The capaCitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.

Figure 1. Driving the VREF with the LT1 006 Op Amp

Input signal leads to AIN and signal return leads from
AGND (pin 3 for LTC127 4, pin 4 for LTC1277) should be
kept as short as possible to minimize input noise coupling.ln applications where this is not possible ashielded
cable between source and.ADC is recommended.

INPUT RANGE:
±2.115V (±0.846 x VREF)
IN BIPOLAR AND - - - - - - - - - - - ,
OV TO 4.231V (1.69VREF(OUT))
5V
IN UNIPOLAR MODE .....--L----.
VOUT
LT1019A-2.5

BOARD LAYOUT AND BYPASSING

Also, since any potential difference in grounds between
the Signal source and the ADC appears as an error voltage
in series with the input signal, attention should be paid to
reducing the ground circuit impedances as much as
possible.

t-----.......
R2
10k t-~-...JV.O/Ir-"

LTC1274
LTC1277

L..-......._ _ _ _ _ _---,lAGND
AIN- (LTC1277)
ADDITIONAL PINS OMITIED FOR CLARITY
LTC1274177F5a
±20LSB TRIM RANGE

-=

Figure 5a. Full-Scale Adjust Circuit
ANALOG

1~:~6 ...JV.iI'v-1~

AIN (LTC1274)

>-1~----tAIN' (LTC1277)
R4
100k
R5

5V

L..----+<:JtL-SCALE
ADJUST
5V
R7
100k
R6
40011

LTC1274
LTC1277

~gk

-=

OFFSET
ADJUST

Figure 5b. LTC1274/LTC1277 Unipolar Offset
and Full-Scale Adjust Circuit

LTC1274 Bipolar Offset and Full-Scale Error
Adjustments
Bipolar offset and full-scale errors for LTC127 4 are adjusted in a similar fashion to the unipolar case. Again,
bipolar offset must be adjusted before full-scale error.
Bipolar offset error adjustment is achieved by trimming
the offset of the op amp driving the analog input of the

13-32

>-....-_ _ _-4A1N (LTC1274)

AIN' (LTC1277)

R4
100k
R5

LTC1274
LTC1277

'-----~:JtL-SCALE
ADJUST

-'l.rvv--.----I

4.096V

R1
ANALOG 10k
INPUT .JW1r+---I

R3
100k
R6
20011

R7
100k

5V

~gk

-=

AIN- (LTC1277)
LTC1274177f5<:

OFFSET
ADJUST
-5V

Figure 5c. LTC1274/LTC1277 Bipolar Offset
and Full-Scale Adjust Circuit

LTC1274 while the input voltage is 0.5LSB below ground.
This is done by applying an input voltage of -0.50mV
(-0.5LSB) to the input in Figure 5c and adjusting the R8
until the ADC output code flickers between 0000 0000
0000 and 1111 11111111. For full-scale adjustment, an
input voltage of 2.0465V (FS -1.5LSBs) is applied to the
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111.
LTC1277 Bipolar Offset and Full-Scale Error
Adjustments
Bipolar offset and full-scale errors are adjusted in asimilar
fashion to the unipolar case. Again, bipolar offset must be
adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset of the op amp
driving the analog input of the LTC1277 while the input
voltage is 0.5LSB below ground. This is done by applying
an input voltage of -0.50mV (-0.5LSB) to the input in
Figure 5c and adjusting the R8 until the ADC output code
flickers between 0111 1111 1111 and 1000 0000 0000.
For full-scale adjustment, an input voltage of 2.0465V (FS
-1.5LSBs) is applied to the input and R5 is adjusted until
the output code flickers between the input 1111 1111
111 0 and 1111 1111 1111.

LTC 1274/LTCl 277
APPLICATions InFoRmATion
Power Shutdown
The LTC1274/LTC1277 provide shutdown features that
will save power when the ADC is in inactive periods. Both
ADCs have a Sleep mode. To power down the ADCs,
SLEEP (pin 18 in LTC127 4 or pin 6 in LTC1277) needs to
be tied low. When in Sleep mode, the LTC1274/LTC1277
will not start a conversion even though the CONVST goes
low. The parts are drawing 1~. After releasing from the
Sleep mode, the ADCs need 4ms (1 O~ bypass capacitor
on VREF pin) to wake up and a REFRDY signal will go to
high to indicate the ADC is ready to do conversions.
Forthe LTC1277, it has an additional Nap mode. When pin
7 (NAP pin the LTC1277) is tied low, all the power is off
except the internal reference which is still active and
provides 2.42Voutputvoltage to the other circuitry. In this
mode the ADC draws 0.8mW instead of 1OmW (for minimum power, the logic inputs must be within 600mV from
the supply rails). The wake-up time from the power
shutdown to active state is 2!JS.

Timing and Control
Conversion start and data read operations are controlled
by three digital inputs in the LTC127 4: CS, CONVST and
RD. For the LTC1277 there are four digital inputs: CS,
CONVST, RD and HBEN. Alogic "O"for CONVSTwili start
a conversion after the ADC has been selected (i.e., CS is
low). Once initiated, it cannot be restarted until the
conversion is complete. Converter status is indicated by
the BUSY output and this is LOW while conversion is in
progress. The High Byte Enable input (HBEN) in the
LTC1277 is to multiplex the 12 bits of conversion data
onto the lower 07 to 00/8 outputs.

Figures 6 through 10 show several different modes of
operation. In modes 1aand 1b (Figures6and 7) CS and RD
are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1ashows
operation with anarrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 8) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD
signal. Mode 2 can be used for operation with a shared
MPU databus.
In slow memory and ROM modes (Figures 9 and 10) CS is
tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In ROM mode, the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the
previous conversion result. After the conversion is complete, the processor can read the new result and initiate
another conversion.

II
13-33

LTC 1274/LTC1277
APPLICATions InFoRmATion
cs=Rlj=o
HBEN (LTCI277)

' ...

"I

tcONV

-4--~ ~SAMPLEN}

-

115
(SAMPLE N + I)

1\

i.--

17

15{

LTCI274 DATA

DATA(N-I)
DBI1TO DBa

LTCI277 DATA

DATA (N-I)
DB7TO DBa

-

1\

J
16

~

)!
)!

DATA(N + I}
DBII TO DBa

DATAN
DBII TO DBa

DATAN
DB7TO DBa

)

DATAN
DBII TO DBS

)!

DATAN
DB7TO DBa

DATA(N + I}
DB7 TO DBa
LTC1274/77'FOB

Figure 6. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =t..r-u-)

HBEN (LTC1277)
-;~---ICONV----I

DATA(N -I)
DBI1TO DBa

LTCI274 DATA

LTCI277DATA

DATA (N + I)
DBI1TO DBa

~~jWDB~
LTC1274177'F07

Figure 7. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = JLJl.. )

13-34

LTC 1274/LTCl 277
APPLICATions InFoRmATion

HBEN (LTCI277)

M--------------------~

LTC1274 DATA

DATAN
DB7TO DBO

LTCI277 DATA

LTC12741170FQB

Figure 8. Mode 2. CONVST Starts a Conversion. Data is Read by RD

- -

cs=O

115

HBEN (LTC1277)

I\.

- 17

•

ICONV

~ ~(SAMPLEN)

LTC1274 DATA

LTCI277 DATA

-

h

(SAMPLE N + 1)

--110----

15 -

19

.

118

~

- -

DATA(N-1) )
DB11T0 DBO

DATA(N-1) )
DB7 TO DBO

16

DATAN
DB11 TO DBO

DATAN
DATAN
)
DB7TO DBa
-

~

70

IIJ:~I= 2.15J! ml io-'
IIIIIII~
VIN =1.8V

~

u

i'1i

~

60
50

SHUTDOWN
'SUMIDA CD54-220
"IN5817

~

80

499k

+

VIN=3:3V~ IIII~ llJ]

l

":" lT1304TA01

40
0.1

1
10
100
LOAD CURRENT (rnA)

500

LT1304TA02

13-37

LTl304/LT1304-3.3/LT1304-5
A8S0LUTEmAxmum RATinGS

PACKAGE/ORDER InFORmADon

V,N Voltage ................................................................ 8V
SW Voltage ......•...............•.....•....••...••...•••. -O.4V to 25V
FB Voltage (LT1304) ..............•.....•........•••...••. V,N + 0.3V
Sense Voltage (LT1304-3.3/LT1304-5) ..................... 8V
ILiM Voltage .............................................................. 5V
SHDN Voltage ..••....••....•....•........................................ 6V
LBI Voltage •....••....•.•.•.•..•.•..•......••.••••..•.•..•.•..•.•.....••.•.V,N
LBO Voltage ..••.••••...•...............•................•....•.......•.•.. 8V
Maximum Power Dissipation ....•..•.••..••....••....•••. 500mW
Junction Temperature ........•.•..•.•..••.•..•.•...••....••...• 125°C
Operating Temperature Range .....•..............• O°C to 70°C
Storage Temperature Range ........•....•... -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER PART
NUMBER

TOP VIEW

"'0""'' ·'

LBO 2
VIN 3
SW4

SHDN
6 IUM
5GND
7

S8 PACKAGE
HEAD PLASTIC SO
"FIXED OUTPUT VERSION
TJMAX = 125'C, OJA = 150'CIW

LT1304CS8
LT1304CS8-3.3
LT1304CS8-5

S8 PART MARKING
1304
13043
13045

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS
PARAMETER
Minimum Operating Voltage
Operating Voltage Range
Quiescent Current
Quiescent Current in Shutdown
Comparator Trip Point
FB Pin Bias Current
Sense Pin Leakage in Shutdown
Output Sense Voltage
Line Regulation
LBllnput Threshold
LBI Bias Current
LBllnput Hysteresis
LBO Output Voltage Low
LBO Output Leakage Current
SHDN Input Voltage High
SHDN Input Voltage Low
SHDN Pin Bias Current
Switch Off Time
Switch On Time
Maximum Duty Cycle
Peak Switch Current
Switch Saturation Voltage
Switch Leakage

13-38

VIN =2V, VSHDN =2V unless otherwise noted.
MIN

CONDITIONS

VSHDN = 2V, Not Switching
VSHDN = OV, VIN = 2V
VSHDN = OV, VIN = 5V
LT1304
LT1304
VSHDN = OV, Fixed Output Versions
LT1304-3.3
LT1304-5
1.8V ~ VIN ~ 8V
Falling Edge

ISINK = 5001lA
LBI = 1.5V, LBO = 5V

VSHDN = 5V
VSHDN = OV
Current Limit Not Asserted
Current Limit Not Asserted
ILIM Pin Open, VIN = 5V
20k from ILiM to GND
Isw= lA
Isw= 700mA
Switch Off, Vsw = 5V

•
•
•
••
•
•
•
••
•
•
•

•
•
•
••
••
•
•
•
•
•

1.22

3.17
4.80
1.10

TYP

MAX

UNITS

1.5

1.65
8
200
15
50
1.26
25
1
3.43
5.25
0.15
1.24
20
65
0.4
0.1

V
V

120
7
27
1.24
10
0.002
3.3
5.05
0.04
1.17
6
35
0.2
0.01

1.4

-5
1
4
76
O.B

5
-2
1.5
6
80
1
500
0.50
0.26
0.01

0.4
8
2
8
88
1.2

0.35
7

IlA
IlA
IlA
V
nA

IlA
V
V
%/V
V
nA
mV
V

IlA
V
V

IlA
IlA
~
~

%
A
mA
V
V

IlA

LTl304/LT1304-3.3/LT1304-5
ELECTRICAL CHARACTERISTICS

VIN = 2V, VSHDN = 2V unless otherwise noted.

The. denotes specifications which apply over the DOC to 7DoC operating
temperature range.

Pin FunOlons
LBI (Pin 1): Low-Battery Detector Input. When voltage on
this pin is less than 1.17V, detector output is low.

GND (Pin 5): Device Ground. Must be low impedance;
solder directly to ground plane.

LBO (Pin 2): Low-Battery Detector Output. Open collector
can sink up to 500/lA. Low-battery detector remains active
when device is shut down.

ILIM (Pin 6): Current Limit Set Pin. Floatfor 1Apeak switch
current; a resistor to ground will lower peak current.

V,N (Pin 3): Input Supply. Must be bypassed with a large
value capacitor close «0.2") to the pin. See required
layout in the Typical Applications.
SW (Pin 4): Collector of Power NPN. Keep coppertraces on
this pin short and direct to minimize RFI.

SHDN (Pin 7): Shutdown Input. When low, switching
regulator is turned off. The low-battery detector remains
active.
FB/SENSE (Pin 8): On the LT1304 (adjustable) this pin
goes to the comparator input. On the fixed-output versions, the pin connects to the resistor divider which sets
output voltage. The divider is disconnected from the pin
during shutdown.

BLOCK DIAGRAmS
LT1304 Block Diagram

LT1304-3.3/LT1304-5 Block Diagram

LT1304-3.3: R1 = 355k
LT1304·5: R1 = 195k

13-39

LTl304/LT1304-3.3/LT1304-5
TYPICAL APPLICATions
Ultra-Low 10 2-Cell Boost Converter
MBR0530

-la~10J!A

SW

-=- 2 CELLS

+

100llF

LT1304
FB
SHDN

ILiM
GND

'1% METAL FILM
"SUMIDA CD54-330

: 4
::::::: CELLS

+

1.21M'

+

":'"

4-Cell to 5V Converter
100llF

5V
100mA
50% EFFICIENT AT ILOAD =10J!A
80% EFFICIENT AT ILOAD =10mA

3.83M'

LBI

220llF

LT1304TAD4

Required Layout for Specified Performance.
Input Capacitor Must be Placed as Shown

1N5818 OR
MBRS130LT3

t - - t - - - t - ~~omA
100llF

'SUMIDA CD54-220

SHUTDOWN

-::- LT1304TA03

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT1073

Single Cell, Micropower DC/DC Converter

951lA Quiescent Current, 1V Minimum Input

LT1121

150mA Low Dropout Regulator

451lA Quiescent Current, 400mV Dropout at Full Load

LTC'"1174

Micropower Step-Down DC/DC Converter

Over 90% Efficiency at 5V/425mA Output

LT1301

Fixed 5V112V Micropower DC/DC Converter

12V1200mA from 5V, 1201lA la, 88% Efficiency

LT1302

High Output Current Micropower DC/DC Converter

5V1600mA from 2V, 2A Internal Switch, 2001lA 10

13-40

L.7LIn

U~UlfUt%lL lR1lS:lLlS:t%~lS:
Final Electrical Specifications

LT1309
TECHNOLO~G~~~------5-0-0-kH-Z--M-iC-r-O-p-o-w-e-r

DC/DC Converter
for Flash Memory
May 1995

DESCRIPTion

FEATURES
I

I
I
I
I

I
I

I
I

I

I
I
I

I
I
I

60mA Output Current at 12V from 3V or 5V Supply
Shutdown to 9J.11\
VPP VALID Comparator
Up to 85% Efficiency
Switching Frequency: 6S0kHz (Typical)
Quiescent Current: SOO~
Low VCESAT Switch: 300mV at O.SA (Typical)
Soft Start Reduces Supply Current Transients
Uses Low Value, Small Size,
Surface Mount Inductors
Available in 8-Lead SO Package

Flash Memory VPP Generators
Type II and III PCMCIA Card DCfDC Converters
3V to 12V, SV to 12V Converters
Portable Computers and Instruments
Cellular Telephones
DCfDC Converter Module Replacements

The LT@1309 is a SOOkHz micropower DCfDC converter
for Flash Memory. The regulator features Burst Mode™
operation with a O.SA, 300mV switch, enabling 8S%
efficiency at the fixed 12V output. High frequency operation permits the use of small value, and therefore small
size, surface mount inductors and capacitors. The LT1309
comes in an 8-lead SO package allowing extremely
compact PC board layouts. These features make the
device attractive for PCMCIA cards, cellular phones and
other applications where PC board space is limited.
Quiescent current is 6S0~ decreasing to 9~ when the
part shuts down. The device includes a Soft Start feature
which limits supply current transients during turn-on.
The LT1309 contains a VPP VALID comparator with a
logic output that goes low when the output voltage is
ready to program 12V Flash Memory. This comparator
simplifies the interface to external control logic.
LT, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.

rYPICAL APPLICATiOn
12V, 60mA Flash Memory Programming Supply

12V Output Efficiency
86

3VTO ~~

D1 t

vpp 12V, 60mA

VIN = 5V

--..--------

as

. / VVIN=3.3V

78

C3

J

~ 76
74

• MURATA ERIE LOH3C1 OOKOYMOO
"CERAMIC
t MOTOROLA MBR0530

L7lJ[J~

I--"

IX

72

70

'(
1

10
LOAD CURRENT (rnA)

100

13-41

LT1309
ABSOLUTE mAXimum RATinGS
Vee Voltage ............................................................... 7V
Vsw Voltage ............................................................ 20V
VSENSE Voltage ....................................................... 20V
VON/OFF Voltage ......................................................... 7V
VSEL Voltage ............................................................. 7V
ILiM Voltage .............................................................. 7V
Maximum Power Dissipation ............................ 500mW
Operating Temperature Range ..................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

PACKAGE/ORDER InFORmATion
ORDER PART
NUMBER

TOP VIEW
SOFfSTART 0 8 ON/OFF
Vee 2
7 SENSE
PGND 3
6 VPPVALID
Vsw 4
5 GND
S8 PACKAGE
8-LEAD PLASTIC SO

LT1309CS8
S8 PART MARKING
1309

TJMAX =150'C. 6JA =150'CIW

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS
SYMBOL
10

TA =25°C, Vee =5V, VON/OFF =3V, unless otherwise noted.

PARAMETER
Quiescent Current

VSENSE = 12V

CONDITIONS

MIN

TYP
650

Quiescent Current, Shutdown

VON/OFF = 0.2V

9

Input Voltage Range

2

•

Output Sense Voltage
Output Referred Comparator Hysteresis
Oscillator Frequency

fosc
OC

Maximum Duty Cycle

tON

Switch On Time
Reference Line Regulation

VCESAT

Current Limit Not Asserted

•

11.5

UNITS

900
15

~

6
12

12.6

35

~

V
V
mV

400

500

700

kH2

80

85

92

%

1.7

~

2V < VIN < BV

0.06

0.15

%/V

Switch Saturation Voltage

Isw = 0.5A

230

350

mV

Switch Leakage Current

0.1

10

~

Switch Current Limit

Vsw = 12V, Switch Off
VIN = 5V, Soft Start Floating
VIN = 3V, Soft Start Floating

600
650

900
950

mA
mA

Soft Start Current

Soft Start Grounded

80

120

~
V

450
500

ON/OFF Input Voltage Low
ON/OFF Input Voltage High
ON/OFF Bias Current

0.8

V

1.6
VON/OFF = 5V
VON/OFF = 3V
VON/OFF = OV

Sense Pin Input Current
VPP VALID Threshold

VON/OFF = 0.2V
VSENSE Rising (High to Low Transition)

VPP VALID Output Voltage Low

ISINK= 100~

VPP VALID Output Voltage High

ISOURCE = 2.5~

The. denotes specifications which apply over the full operating
temperature range.

13-42

MAX

•

16.0
8.0
0.1

24.0
14.0
1.0

~
~
~

50.0
0.1

90
1
12

~
~

0.13

0.3

Ii

11.4
4

4.5

V
V

LT1309
TYPICAL PERFORmAnCE CHARAOERISTICS
Supply Current

Sense Voltage
800

12.20

-

12.15
12.10
~
tlj 12.05

~

012.00
>

r--

-

~ 11.95

'" 11.90

700

Vee =5V

1

Vee =3V

f-

iii
a:

"

600

..-/

a:

::>

'-'

':; 500
0..
0..

::>

'" 400

11.85
11.80
-50

-25

0
25
50
TEMPERATURE (OC)

75

300
-50

100

Supply Current In Shutdown
12
~

I

C

"'--'
§2

f-

a:
::>
'-'
':;

-r--

0..
0..

::>

'"
o

-50

75

100

75

100

Maximum Duty Cycle

vee - 5V

10

iii
a:

0
25
50
TEMPERATURE (OC)

95

14

:;:

-25

-25

I--Vee = 3V

50
25
TEMPERATURE (OC)

'-'

85

~

80

~

75

~
c

I

:;

75

90

/'

70
-50

100

/"

-25

r-

25
50
TEMPERATURE (OC)

LT13OS-TPCC3

Start-Up Waveforms, ILOAD =1mA
12V

VOUT
5V1DIV

VOUT
2V/DIV

12V OUTPUT
1V1DIV
AC COUPLED

IL
500mNDIV

VPPVALID
10VlDlV

Load Transient Response,
COUT = 1!JF

Start-Up Waveforms, ILOAD =10mA

ILOAO

~~~~

VONiOFi
10VlDIV

VONIOFF

10VIDIV
50~DIV

50~DIV

50~DIV

LT13og·TPC07

III
13-43

LT1309

Pin FunCTions
SOFT START (Pin 1): A 0.1 Jlf/1 Mn parallel RC from this
pin to GND provides a Soft Start function upon device
turn-on. Initially about 80jJA will flow from the pin into the
capacitor. When the voltage at the pin reaches approximately OAV, current ceases flowing out of the pin.
Vee (Pin 2): Input Supply. Both pins should be tied
together. At least 1Jlf input bypass capacitance is required. More capacitance reduces ringing on the supply
line.
PGND (Pin 3): Power Ground. Connect to ground plane.
Vsw (Pin 4): Collector of Power Switch. High dV/dt
present on this pin. To minimize radiated noise keep
layout short and direct.

GND (Pin 5): Signal Ground. Connect to ground plane.
VPP VALID (Pin 6): This pin provides a logic signal
indicating that output voltage is greater than 11AV. Active
low with internal 200k pull-up resistor.
SENSE (Pin 7): Output Sense Pin. This pin connects to a
resistive divider that sets the output voltage. In shutdown,
the resistor string is disconnected and current into this pin
reduces to < 1jJA.
ON/OFF (Pin 8): Shutdown Control. When pulled below
1.5V, this pin disables the LT1309 and reduces supply
currentto 9jJA. All circuitry is disabled in shutdown. The
part is enabled when ON/OFF is greater than 1.5V.

BLOCK DIAGRAm
ON/OFF

~---.._

POWER ON

sw
SOFT START

fib

GND

PGND

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LT11 06

Micropower Step-Up DC/DC Converter, 12V at 60mA

Thin TSSOP Package for Type I PCMCIA Card

LT1109-12

Micropower Step-Up DC/DC Converter, 12V at 60mA

Flash Memory VPP Generator, Adjustable Also

LT1109A-12

Micropower Step-Up DC/DC Converter, 12V at 120mA

VPP Generator, Adjustable Also

LTC"'1262

Inductorless Flash Memory Programming Supply, 12V at 30mA

Switched Capacitor Converter, No Inductor

LT1303

Micropower High Efficiency DC/DC Converter with Low-Battery Detector

Adjustable and Fixed 5V, lOUT up to 200mA

13-44

L7LI n

UlffiU UU~16

lru151615~§j15

Final Electrical Specifications

LTC 1324
TECHNOLO~G~~~--S-i-n-g-Ie-s-u-p-P-I-Y-L-O-C-a-IT-a-Ik-®

Transceiver
April 1995

FEATURES

DESCRIPTiOn

•
•
•
•

The LTC®1324 is a single 5V line transceiver designed to
operate on Apple®LocalTalk networks. The driver features
a digitally selectable low slew rate mode for reduced EMI
emissions. The chip draws only 1mA quiescent current
when active and 11JA in shutdown. The differential driver
outputs three-state when disabled, during shutdown or
when the power is off. The driver outputs will maintain
high impedance even with output common-mode voltages beyond the power supply rails. Both the driver
outputs and receiver inputs are protected against ESD
damage to ±1OkV.

•
•
•
•

Single Chip 5V LocalTalk Port
Low Power: Icc =1rnA Typ
Shutdown Pin Reduces Icc to 11JA Typ
Digitally Selectable Low Slew Rate Mode for
Reduced EMI Ernrnisions
ESD Protection to ±10kV on Receiver Inputs and
Driver Outputs
Drivers Maintain High Impedance in Three-State or
with Power Off
Thermal Shutdown Protection
Drivers Are Short-Circuit Protected

The LTC1324 is available in a 16-pin SO Wide package.

APPLICATions
• LocalTalk Peripherals
• Notebook and Palmtop Computers
• Battery-Powered Systems

£r, LTC and LT are registered trademarks of Linear Technology Corporation.
Apple and Locarralk are registered trademarks of Apple Computer, Inc.

TYPICAL APPLICATiOn
Waveform of Driver

Typical LocalTalk Connection for Low EMI
5V

16
12

~11-----"II(E

SLEW RATE CONTROL
DATA IN
TX ENABLE
SHUTDOWN
-RX ENABLE

LocalTalk
TRANSFORMER

6

10

DATA OUT
1324TAD1

1324TA02

13-45

LTC 1324
ABSOLUTE mAxmum RATinGS

PACKAGE/ORDER InFORmATion

(Note 1)

ORDER PART
NUMBER

Supply Voltage (Vee) ................................................ 7V
Input Voltage (Logic Inputs) ........ -O.3V to (Vec +O.3V)
Input Voltage (Receiver Inputs) ............................ ±15V
Driver Output Voltage (Forced) ............................. ±15V
Driver Short-Circuit Duration .......................... Indefinite
Operating Temperature Range .................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

LTC1324CN
LTC1324CSW

N PACKAGE
16-LEAD PDIP

SW PACKAGE
16-LEAD PLASTIC SO WIDE

TJMAX =150'C, BJA =110'C/W (N)
TJMAX 150'C, BJA 150'C/W (S)

=

=

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARAOERISTICS

I

Vee = 5V, TA = Doe to 70 0 e(Notes 2,3), unless otherwise noted.

ICONDITIONS

SYMBOL PARAMETER

I

MIN

TYP

I'\fAX

UNITS

Supplies
Icc

Normal Operation Supply Current
Shutdown Supply Current

No Load, SHDN = OV, TXDEN = OV, RXEN = OV
No Load, SHDN = Vec

2
10

rnA
~

Differential Driver
VOD

Differential Output Voltage

No Load
RL = son (Figure 1)

!!.Voo

Change in Magnitude of Differential
Output Voltage

RL = SOn (Figure 1)

Voe

Differential Common-Mode Output Voltage

RL = son (Figure 1)

Iss

Short-Circuit Current

OV<;,Vo<;,5V

loz

Three-State Output Current

(TXDEN = Vce and TXDEN = GND) or
SHDN = Vee or or Power Off, -10V <;,Vo <;, 10V

•
•

±4,O
±2,0

•
•

35

•
•
•
•

2.4

V
V
0.2

V

3.0

V

120

250

rnA

±2

±200

~

Logic Inputs
VIH

Input High Voltage

All Logic Input Pins

VIL

Input Low Voltage

All Logic Input Pins

liN

Input Current

ION

Pull-Down Current

13-46

"

SHDN, TXDEN, RXDEN, VIN = OV to Vee
RXDEN, TXDEN, SR, VIN = OV to Vee

V
0.8

V

±1

±20

~

15

60

~

LTC 1324

iLECTRICAL CHARACTERISTICS
'MBOL

I PARAMETER

Vee = 5V, TA = DoC to 70°C (Notes 2, 3), unless otherwise noted.

I CONDITIONS

MIN

TYP

MAX

UNITS

Iceiver
Input Resistance

-7V:s: VIN:S: 7V

Receiver Threshold Voltage

-7V:s: VeM:S:7V

Receiver Input Hysteresis

-7V:s:VeM:s:7V

IH

Output High Voltage

10=-4mA

IL

Output Low Voltage

10 =4mA

)

Output Short-Circuit Current

OV:S:Vo:s:5V

1

Output Three-State Current

OV:s: Vo:S: 5V, RXEN = Vee, RXEN = GNO

N

12

•

litching Characteristics
.H, tpHL

(EW

tf

jis, tLdis

m, tENL

Oriver Propagation Delay
Without Slew Rate Control

RL = 1000, CL = 1000 (Figures 2, 4)
SR = GND

Driver Propagation Delay
with Slew Rate Control

RL = 1000, CL = 1OOpF (Figures 2, 4)
SR = Vee

Receiver Propagation Delay

CL = 15pF (Figures 2, 6)

Driver Output to Output
Without Slew Rate Control

RL = 1000, CL = 100pF (Figures 2, 4)
SR = GND

Driver Output to Output
with Slew Rate Control

RL = 1000, CL = 100pF (Figures 2, 4)
SR = GND

Driver Rise/Fall Time
Without Slew Rate Control

RL = 1000, CL = 100pF (Figures 2,4)
SR = GND

Driver Rise/Fall Time
with Slew Rate Control

RL = 1000, CL = 100pF (Figures 2, 4)
SR = Vee

Driver Output Active to Disable
Without Slew Rate Control

CL = 15pF (Figures 3, 5)
SR = GND

Driver Output Active to Disable
with Slew Rate Control

CL = 15pF (Figures 3, 5)
SR = Vee

Receiver Output Active to Disable

CL = 15pF (Figures 3, 7)

Driver Enable to Output Active
Without Slew Rate Control

CL = 15pF (Figures 3, 5)
SR = GND

Driver Enable to Output Active
with Slew Rate Control

CL = 15pF (Figures 3, 5)
SR = Vee

Receiver Enable to Output Active

CL = 15pF (Figures 3, 7)

e. denotes specifications which apply over the full operating
nperature range.
Ite1: Absolute maximum ratings are those values beyond which the life
a device may be impaired.

•
•
•

kO

-200

200

mV

70

mV
V

3.5
7

0.4

V

85

rnA

•
•
•

±2

±100

IlA

40

120

ns

0.4

1

J.IS

•

70

160

ns

10

50

ns

25

100

IlS

50

150

ns

0.4

1

J.IS

50

150

ns

0.7

2

J.IS

30

100

ns

50

150

ns

250

750

ns

30

100

ns

•
•
•
•
•

•
•
•
•
•

Note 2: All currents into device pins are positive and all currents out of
device pins are negative. All voltages are reference to ground unless
otherwise specified.
Note 3: All typicals are given at Vee = 5V, TA = 25°C.

III
13-47

LTC 1324
TYPICAL PERFORmAnCE CHARACTERISTICS
Driver Differential Output Voltage
vs Output Current
TA = 25'G

"-

70

"- ~

< 60
§.
50
z>w

D..
l-

=>

0

-

120

80

a:
a:
=>
'-'
>=>

Driver Output High Voltage
vs Output Current

Driver Output Low Voltage
vs Output Current

40

TA= 25'G
100

>-

iii
cc:

l".

1""-

30
20

cc:
=>
>=>
D..
>=>

/

60

'-'

''\,

/

40

0

""-

10

o

/

<
§. 80

20

o

o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)

./
o

V

0.5

105
TA =25'G
90
<
§. 75
z>Ii! 60
cc:
=>
'-'

45

c.
>=>

30

~

0

/

.........

~

."

'\

\

15

1.0
1.5
2.0
OUTPUT VOLTAGE (V)

2.5

o

3.0

1.0

r\
""- 5.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5
DRIVER OUTPUT HIGH VOLTAGE (V)

1324002

Receiver Output High Voltage
vs Output Current

Receiver Output Low Voltage
vs Output Current
30
25

!>-

iii
a:

a:
=>
'-'
>=>
D..
>=>

/

20
15

/
V

10

0

o!
o

I

16

/'

TA=25'G

110
TA = 25'G

14

!

V

:---"r-.,

12

100

.......

~ 10

<
§. 90

.........

>-

=>
'-'

~
f;::

6

o

4

:::I

iii
80
cc:

""i'..

cc:
cc:

17

<
§. 16

0.4

0.8
1.2
1.6
OUTPUT VOLTAGE (V)

2.0

2.5

3.0
3.5
4.0
OUTPUT VOLTAGE (V)

I\.
'\

a:

13
12
11

<850

.;;

"-

~ 825
cc:

"-

~

""

~ 775

c.
=>
VJ

I'-...

10
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE ('G)

13-48

800

'-'

........

4.5

"

r--...

.........

750
725

........

40
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE ('G)

5.0

"''''''

r-.
~

'\.

""I'-...

50

Supply Current (Driver and
Receiver Enabled) vs Temperature
875

=>
'-' 14
>=>
D..
=>

60

0

I\-

1324905

1\

iii
a: 15

0

70

=>
D..
>=>

\

o

2.0

900

>-

l-

'-'

l-

r\

Receiver Short-Circuit Current
vs Temperature
18

cc:
=>

" '\.

1324G04

19

Driver Short-Circuit Current
vs Temperature

4.2

Driver Skew vs Temperature
Ili/FFFFFr="1

4.0

1--,.....+--+-1-+-+--+--+-----1

./V

., 3.8 1-+--1--1--1-+--+--+--+--1

'\.

;;; 3.6

I"

:;;

>=

"-

"r--...

700
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE ('G)

1-+--+--+-1-+-+--+--+-----1

3.4

1-+--1--1--1-+--+--+--+--1

3.2

1-+--+--+-1-+-+--+--+-----1

3.0 L...L....L-L---1_.L....L.-"--'----'
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE ('G)

LTC 1324
rYPICAL PERFORmAnCE CHARAOERISTICS
Receiver Output Low Voltage
vs Temperature

Receiver Output High Voltage
vs Temperature

0.8

4.00
I =8mA

0.7

2:

... V

0.6

/'

~ 0.5
§! 0.4
I-

~ 0.3

o

......

'"

I =8mA

.........

_3.50

§! 3.00

"-.

~ 2.75

6

2.50
2.25

-55 -35 -15 5

25

45

65

85 105 125

2.00
-55 -35 -15 5

TEMPERATURE ('C)

2.9

~

2.8

~

2.7

",

-

a5

2.6
2.5

a:

45

65

85 105 125

Receiver ItpLH -tPHL I
vs Temperature

~L = lboQ
.........

........

I'-

\ h..
.........

\..

I'-..

I-

~
Cl

25

"

TEMPERATURE ('C)

Driver Differential Output Voltage
vs Temperature

~

I'-

I-

I-

a

2:
w

.........

~

0.2

3.1

.........

~ 3.25

0.1

3.0

r--....

2:.

/

,..... V . . . .

3.75

"'

i\
\

2.4
2.3
-55 -35 -15 5

25

45

65

85 105 125

TEMPERATURE ('C)

o

-55 -35 -15 5

25

./

I

I' j

'"

45 65

If

85 105 125

TEMPERATURE ('C)
1324G13

C (Pin 1, 13): No Internal Connection.
R (Pin 2): Slew Rate Control (TTL Compatible). A high
vel on this pin forces the RS485 driver into the low slew
lte mode. Alow level enables the driver into the high slew
lte or normal mode. Connected to an internal pull-down.
KD (Pin 3): RS485 Driver Input (TTL Compatible).
KDEN (Pin 4): Driver Output Enable (TTL Compatible). A
gh level on this pin and a low level on TXDEN (pin 15)
Irces the RS485 driver into three-state. A low level
lables the driver.

SHDN (Pin 5): Shutdown Input (TTL Compatible). When
this pin is high, the chip is shut down; the driver and
receiver outputs three-state; and the supply current drops
to 1~. A low level on this pin allows normal operation.
RXEN (Pin 6): Receiver Enable (TTL Compatible). A high
level on this pin and a low level on RXEN (pin 14) disables
the receiver and three-states the logic outputs. Alow level
allows normal operation.
RXDO (Pin 7): RS485 Receiver Output.
GND (Pin 8): Ground.

13-49

lEI

LTC1324
Pin Funalons
RXD+ (Pin 9): RS485 Receiver Noninverting Input. When
this pin is~200mVabove RXD-, RXDO will be high. When
this pin is ~ 200mV below RXD-, RXDO will be low.

the receiver and three-states the logic outputs. Ahigh level
allows normal operation. Connected to an internal pulldown.

RXD- (Pin 10): RS485 Receiver Inverting Input.
TXD- (Pin 12): RS485 Driver Inverting Output.

TXDEN (Pin 15): Driver Output Enable (TTL Compatible).
A low level on this pin and a high level on TXDEN (pin 4)
forces the RS485 driver into three-state. A high level
enables the driver. Connected to an internal pull-down.

RXEN (Pin 14): Receiver Enable (TTL Compatible). A low
level on this pin and a high level on RXEN (pin 6) disables

Vee (Pin 16): The Positive Supply Input. 4.75V $; Vee $;
5.25V. Requires a 1J.lF bypass capacitor to ground.

TXD+ (Pin 11): RS485 Driver Noninverting Output.

TEST CIRCUITS
Vee

!

-rY
Tel
50011

Voo
15pF

R

OUTPUT

SI

~2

Voe

l~

1324F01

Figure 1.

Figure 2.

Figure 3.

SWITCHinG WAVEFORms
3V
TXO

,= IMHz: IrS IOns: If S IOns

ov
Va

'-va
TXO-

__~__~~~~____~':~vo________~)(~
Vo'

TXO+

-1l-tsKEW
Figure 4. Differential Driver

13-50

~II:ISKEW

1324'"

LTC 1324
SWITCHinG WAVEFORms
3V _ _......

TXOEN

f= 1MHz: I,~ 10n8: If';; 10n8
OV
tLZ

5V

---+------.

TXO+, TXO2.3V
VOL _ _ _-l-___'------:°:.::.uT~PU:.:.T:.:.::NO::.::RM:::;A:;;:;LLY.:..:L::::;OW::.......:_....JI
VOH _ _ _ _ _--+_r-----:O~UT.:..:PU:.:..T:.:.::NO::.:;RM::;,,:A::::,LLY:..:.H::,::IG:.;..H_----.1

TXO-, TXO+

2.3V
OV----~

Figure 5. Differential Driver Enable and Disable

(RXO+) - (RXOl

VOD2 ----~-.....,....~-.,...,._------,.
f = 1MHz: I,,;; 10n8: If ~ 10n8

-VOD2---'

VOH _ _ _ _ _
IPL_H-_l+_..-_ _ _ _ _ _ _I_PHL

~.5V

)l1.5V

RXOO

j

VOL - - - - - - '

' - - - -___

Figure 6. Differential Receiver
3V _ _......

RXEN

OV _ _ _+-,_ _ _f_=1_M_Hz~:I,_';;_10n_8:~4~_1_0n_8-J

5V---+--......
RXO, RXO, RXOO

2.3V
VOL _ _ _-I-_ _'--.....::O.::.;UT.:.,:PU:,;,;TN:,:,::O;,,:::RM:::;:AL::::,LY:.,:;L.::.;OW::......:._....Jl

VOH _ _~_ _--+.,-.....::O~UT.:..:PU:,;,;TN;,:,;:O;, : :RM::;, :AL:: :,LY:. :.H: ,: IG:.;. H_----.1

RXO, RXO, RXOO
OV----~

Figure 7. Receiver Enable and Disable

~PPLICATlons

InFORmATiOn

rhermal Shutdown Protection
rhe LTC1324 includes a thermal shutdown circuit which
Jrotects against prolonged shorts at the driver outputs, If
i driver output is shorted to another output orto the power
)Upply, the current will be initially limited to amaximum of
250mA. When the die temperature rises above 150°C, the
:hermal shutdown circuit turns off the driver outputs.
Nhen the die cools to about 130°C, the outputs re-enable.
fthe short still exists, the part will heat again and the cycle
/ViII repeat. This oscillation occurs at about 10Hz and

L7lJ~

prevents the part from being damaged by excessive power
dissipation, When the short is removed, the part will return
to normal operation.

Power Shutdown
The power shutdown feature of the LTC1324 is designed
for battery-powered systems, When SHDN is forced high,
the part events shutdown mode. In shutdown, the supply
current typically drops from 1mA to 1~and the driver and
receiver outputs are three-stated.

13-51

lEI

LTC1324
APPLICATions InFoRmATion
Supply Bypassing
The LTC1324 requires Vee be bypassed to prevent data
errors. A 1~ capacitor from Vee to ground is adequate.
EMI Filters and Slew Rate Control
Most LocalTalk applications need to use an electromagnetic interference (EMI) filter consisting of a resistorcapacitor T network between each driver, receiver and the
connector. Unfortunately, the resistors will attenuate the
driver's output signal applied to the cable. Because the
LTC1324 uses a single 5V supply, the resistors' values
should be reduced from 220 which is normally used to
5.10 to insure enough voltage swing on the cable (Figure
8). Another way to get maximum swing and EMI immunity
is to use a ferrite bead and capacitor as the T network

(Figure 9). For data rates below 250kb/s, the LTC1324
features a low EMI mode which limits the rise time of the
drivers to 400ns. With a lower rise time, the EMI network
can be eliminated, allowing more Signal voltage to reach
the cable. Figures 1Oand 11 show the output signals ofthe
driver with different slew rates.

Figure 10. High Slew Rate Mode

Figure 8.
FERRITE BEAD

()

FERRITE BEAD

::or ()

)

~100PF

Figure 9.

Figure 11. Low Slew Rate Mode

RELATED PARTS
.PART NUMBER

DESCRIPTION
Single 5V Powered RS2321RS422 Transceiver

COMMENTS
Pin Selectable RS232/RS422 Receiver. Available in 24-Pin SO Wide Package

LTC1320

RS4221RS562 Transceiver

Available in lS-Pin SO Wide Package

LTC1323

Single 5V Powered RS422/RS562 Transceiver

Available in l6-Pin and 24-Pin SO Wide Package

LTC13l8

13-52

£.7 LIn

~[M~lr~~[L ~~[L~~~~
Final Electrical Specifications

LTC1334

TECHNOLO~G~~~----S-in-g-le-5-V--R-S2-3-2-/-R-S4-8-5

Multi-Protocol Transceiver
June 1995

FEATURES

DESCRIPTion

• Four RS232 Transceivers or Two RS485
Transceivers on One Chip
• Operates from a Single 5V Supply
• Withstands Repeated ±10kV ESD Pulses
• Uses Small Charge Pump Capacitors: 0.1~
• Low Supply Current: 8mA Typical
• 10/lA Supply Current in Shutdown
• 250kBaud in RS232 Mode
• 10MBaud in RS485/RS422 Mode
• Self-Testing Capability in Loopback Mode
• Power-Up/Down Glitch-Free Outputs
• Driver Maintains High Impedance in Three-State,
Shutdown or with Power Off
• Thermal Shutdown Protection
• I/O Lines Can Withstand ±25V

The LTC@1334 is a low power CMOS bidirectional transceiver featuring two reconfigurable interface ports. It can
be configured as two RS485 differential ports, as two dual
RS232 single-ended ports or as one RS485 differential
port and one dual RS232 single-ended port. An on board
charge pump requires four 0.1 ~ capacitors to generate
boosted positive and negative supplies, allowing the RS232
drivers to meet the RS232 ±5Voutput swing requirement
with only a single 5V supply. A shutdown mode reduces
the Icc supply current to 10/lA.

APPLICATions
•
•
•
•

Low Power RS485/RS422!RS232/EIA562 Interface
Software-Selectable Multi-Protocol Interface Port
Cable Repeaters
Level Translators

The RS232 transceivers operate to 250kbaud typical and
are in full compliance with RS232 specifications. The
RS485 transceivers operate to 1OM baud and are in full
compliance with RS485 and RS422 specifications. All
interface drivers feature short-circuit and thermal shutdown protection. An enable pin allows RS485 driver
outputs to be forced into high impedance, which is maintained even when the outputs are forced beyond supply
rails or power is off. Both driver outputs and receiver
inputs feature ±10kV ESD protection. A loopback mode
allows the driver outputs to be connected back to the
receiver inputs for diagnostic self-test.
£T, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
2rl h1 28rl h27

27rl h28 1 rl h2

LTC1334

LTC1334

3
....L..

"::I:' VCCl
":'

5V....L..

~ RX OUT

DR ENABLE
DR IN
5V
5V
ORIN
DR IN
RXOUT
RXOUT

26
24
23
22
21

(r

....
..I
~
....

20
19

4
5

7
9

....

I

6
8

RS485 INTERFACE

I

~120n

'lJ'JJ. 120n~

I

I

4000-FT 24-GAUGE TWISTED PAIR

5V

5V
OV

11

RS232 INTERFACE

OV

13
12
11
10
9

'"
1.......V

.L.
~
....

8
4

26
17
18
19
21
20

....

24

18

:::

10

5

:::

25

17

VA

13

6

12

7

;:

22

16

;:

"'A

'"

14

14

'"

...r?~

.L7lJ!J~

.;t_

3

J.

ALL CAPACITORS: 0.11'F MONOLITHIC CERAMIC TYPE

J

23

RXOUT

*'

m

....1....
VCC2
5V

DR ENABLE
DR IN
5V
5V
RXOUT
RXOUT
ORIN
DR IN

~

m

LTC1334·YAQ1

13-53

LTC 1334
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

(Nole 1)

TWO: RS485 TRANSCEIVERS
FOUR: RS232 TRANSCEIVERS

Supply Voltage (Vee) ............................................. 6.5V
Input Voltage
Drivers ................................... -0.3V to (Vee + 0.3V)
Receivers ............................................. -25V to 25V
ON/OFF, LB, SEL1, SEL2 ........ -0.3V to (Vee + 0.3V)
Output Voltage
Drivers ............ ..... ............... ....... .......... -18V to 18V
Receivers ............................... -0.3V to (Vee + 0.3V)
Short-Circuit Duration
Output ........................................................ Indefinite
VDD, VEE, C1 +, C1-, C2+, C2- .......................... 30 sec
Operating Temperature Range
Commercial........................................... O°C to 70°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C

ORDER PART
NUMBER
LTC1334CNW
LTC1334CSW

NW PACKAGE
SW PACKAGE
28-LEAD PDIP WIDE 28-LEAD PLASTIC SO WIDE
TJMAx = 125'C, eJA = 56'C/W (NW)
TJMAX =125'C, eJA =85'C/W (SW)
Consult factory for Industrial and Military grade parts.

DC ELECTRICAL CHARACTERISTICS Vee = 5V, C1 = C2 = C3 = C4 = O.111f (Notes 2, 3)
SYMBOL I PARAMETER
I CONDITIONS
I MIN TYP

MAX

UNITS

=

RS485 Driver (SEL1 SEl2 = HIGH)
Differential Driver Output Voltage (Unloaded)
VODl
Differential Driver Output Voltage (With Load)
VOD2
IlVOD
Voc

III Voc I
10SD

10 = 0
Figure 1, R = 50n (RS422)
Figure 1, R = 2m (RS485)

Change in Magnitude of Driver Differential
Output Voltage for Complementary Output States
Driver Common-Mode Output Voltage

Figure 1, R = 2m or R =50n

Change in Magnitude of Driver Common-Mode
Output Voltage for Complementary Output States
Driver Short-Circuit Current

Figure 1, R = 2m or R = 50n

Figure 1, R = 2m or R = 50n

-7V ~Vo ~ 12V, Vo = HIGH
-7V ~ Vo ~ 12V, Vo = LOW (Note 4)

Three-State Output Current (V, Z)
10ZD
RS232 Driver (SEL1 = SEL2 = LOW)
Output Voltage Swing
Vo

-7V~Vo~12V

Output Short-Circuit Current
10SD
Driver Inputs and Conlrollnpuls

Vo = OV

VIH
VIL
liN

Input High Voltage
Input Low Voltage
Input Current

13-54

Figure 4, RL = 3k, Positive
Figure 4, RL = 3k, Negative

D, DE, ON/OFF, SEL1, SEL2, LB
D, DE, ON/OFF, SEL1, SEL2, LB
D, SEL1"gLL
DE, ON/OFF, LB

•

••
•
•
•
••

2.0
1.5

••
•

5
-5

•
•
••

2

35
10

V

6
6
6

V
V

0.2

V

3
0.2

V
V

250
250

rnA
rnA

±5

!!A
V
V

6.5
-6.5
±11

±60

-4

0.8
±10
-15

rnA
V
V

!!A
!!A

LTC 1334

DC ELECTRICAL CHARACTERISTICS
SYMBOL I PARAMETER
RS485 Receiver (SEL 1 =SEL2 =HIGH)
Dilferentiallnput Threshold Voltage
VTH
t.VTH

Input Hysteresis

Input Current (A, B)
liN
Input Resistance
RIN
RS232 Receiver (SEL1 =SEL2 =LOW)
VTH
t.VTH

Receiver Input Threshold Voltage

Vee =5V, C1 = C2=C3= C4= O.11!f (Noles 2, 3)

I CONDITIONS
-7V $ VCM $12V
VCM = OV
- 7V $ VIN $12V
-7V $ VIN $12V
Input Low Threshold
Input High Threshold

Receiver Input Hysteresis

Receiver Input Resistance
RIN
Receiver Output

•
•

•
••

VIN=±10

VOH

Receiver Output High Voltage

10 = -3mA,

VOL

Receiver Output Low Voltage

10 = 3mA,

10SR

Short·Circuit Current

OV $ Vo $ Vcc

10ZR

Three-State Output Current

ON/OFF = OV

Inactive "8" Output Pull-Up Resistance (Note 5)

ON/OFF = HIGH, SELl = SEL2 = HIGH

Voo

Voo Output Voltage

No Load, ON/OFF = HIGH
IOD = -lOrnA, ON/OFF = HIGH

VEE

VEE Output Voltage

No Load, ON/OFF = HIGH
lEE = lOrnA, ON/OFF = HIGH

ROB
Power Supply Generator

I MIN

VIN = OV, SELl = SEL2 = LOW

VIN = 3V, SELl = SEL2 = LOW

•
•
•
•

TYP

-0.2

MAX
0.2

70
24

2.4

V
V

7

kQ

V

0.6
5

3.5

4.6
0.2

7

rnA
ill

0.8

3

V
mV

±1
12

UNITS

V
0.4

V

85

rnA

±10

IJA

50

ill

8
6.5

V
V

-7.6
-6.5

V
V

Power Supply
ICC

VCC Supply Current

No Load, SELl = SEL2 = HIGH
Shutdown, ON/OFF = OV

AC ELECTRICAL CHARACTERISTICS
SYMBOL I PARAMETER
RS232 Mode (SEL1 =SEL2 =LOW)
BRMAX
SR

rnA

8
10

IJA

Vee = 5V, C1 = C2 = C3 = C4 = O.11!f (Noles 2,3)

I CONDITIONS

Maximum Data Rate (Note 6)

Figure 4, RL = 3k, CL = 51 pF

Slew Rate

Figure 4, RL = 3k, CL = 51 pF
Figure 4, RL = 3k, CL = 1000pF

I MIN

TYP

MAX

250

••

kBaud
30

4

UNITS

V/iJS
V/iJS

tT

Transition Time

Figure 4, RL = 3k, CL = 2500pF

1.9

iJS

tpLH

Driver Input to Output

Figures 4, 9, RL = 3k, CL = 51 pF

0.6

iJS

tpHL

Driver Input to Output

Figures 4, 9, RL = 3k, CL = 51pF

0.6

iJS

tpLH

Receiver Input to Output

Figures 5, 10

0.3

iJS

Receiver Inputto Output
tpHL
RS485 Mode (SEL1 =SEL2 = HIGH)

Figures 5, 10

0.4

iJS

BRMAX

Maximum Data Rate (Note 6)

Figures 2, 6, RL = 54Q, CL = 100pF

15

MBaud

tpLH

Driver Input to Output

Figures 2, 6, RL = 54Q, CL = 100pF

40

ns

tpHL

Driver Input to Output

Figures 2, 6, RL = 54Q, CL = 100pF

40

ns

ISKEW
Ir,t,

Driver Output to Output

Figures 2, 6, RL = 54Q, CL = 100pF

5

ns

Driver Rise and Fall Time

Figures 2, 6, RL = 54Q, CL = 100pF

15

ns

13-55

lEI

LTC-1334
AC ELEORICAL CHARAOERISTICS Vee =5V, C1 =C2 =C3 =C4 =O.1!lf (Notes 2, 3)
SYMBOL I PARAMETER
MIN
TYP
ICONDITIONS

MAX

UNITS

RS485 Mode (SEl1 = SEl2 = HIGH)
Driver Enable to Output low
tZL

Figures 3, 7, CL = 100pF, S1 Closed

50

ns

tZH

Driver Enable to Output High

Figures 3, 7, CL = 100pF, S2 Closed

50

ns

tLZ

Driver Disable from LOW

Figures 3,7, CL = 15pF, S1 Closed

50

ns

tHZ
tpLH

Driver Disable from HIGH

Figures 3,7, CL = 15pF, S2 Closed

ns

Receiver Input to Output

Figures 2, 8, RL = 540, CL = 100pF

60
60

tpHL

Receiver Input to Output

Figures 2, 8, RL = 540, CL = 100pF

70

ns

tSKEW

Differential Receiver Skew, ItpLH - tpHL I

Figures 2, 8, RL = 540, CL = 100pF

10

ns

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to device ground unless
otherwise specified.
Note 3: All typicals are given at Vcc = 5V, C1 = C2 = C3 = C4 = 0.1 J.IF
and TA = 25°C.

ns

Note 4: Short-circuit current for RS485 driver output low state folds back
above Vcc. Peak current occurs around Vo = 3V.
Note 5: The "8" RS232 receiver output is disabled in RS485 mode
(SEL1 = SEL2 = HIGH). The unused output goes into a high impedance
mode and has a resistor to Vcc. See Applications Information section for
more details.
Note 6: The maximum data rate is specified for NRZ data encoding
scheme. The maximum data rate may be different for other data encoding
schemes. Data rate is guaranteed by correlation and is not tested.

Pin FunCTions
28 C2+

Cl+

27
26

Voo

cr
vee
RBl

81
Yl

Zl
SELl

RAl

--"-I......-=::±:-OCin

DZ1/0E1
DYl
[]j

ON/OFF
DY2
DZ2/DE2
RA2
RB2

VEE

C1+(Pin 1): Commutating Capacitor C1 Positive Terminal.
Requires 0.1J.IF external capacitor between Pins 1 and 2.
C1- (Pin 2): Commutating Capacitor C1 Negative Terminal.

Voo (Pin 3): Positive Supply Output for RS232 Drivers.
Requires an external 0.1 J.IF capacitor to ground.
A1 (Pin 4): Receiver Input.
81 (Pin 5): Receiver Input.
Y1 (Pin 6): Driver Output.
Z1 (Pin 7): Driver Output.
SEL1 (Pin 8): Interface Mode Select Input.
SEL2 (Pin 9): Interface Mode Select Input.
Z2 (Pin 1D): Driver Output.
Y2 (Pin 11): Driver Output.
82 (Pin 12): Receiver Input.
A2 (Pin 13): Receiver Input.
GND (Pin 14): Ground.
VEE (Pin 15): Negative Supply Output. Requires an external
0.1 J.IF capaCitor to ground.
RB2 (Pin 16): Receiver Output.
RA2 (Pin 17): Receiver Output.
DZ2/DE2 (Pin 18): RS232 Driver Input in RS232 Mode.
RS485 Driver Enable with internal pull-up in RS485 mode.

LTC 1334
Pin FunCTions
DY2 (Pin 19): Driver Input.
ON/OFF (Pin 20): A HIGH logic input enables the transceivers. A LOW puts the device into shutdown mode and
reduces Icc to 101lA. This pin has an internal pull-up.
lB (Pin 21): Loopback Control Input. A LOW logic level
enables internal loopback connections. This pin has an
internal pull-up.
DY1 (Pin 22): Driver Input.
DZ1/DE1 (Pin 23): RS232 Driver Input in RS232 Mode.
RS485 Driver Enable with internal pull-up in RS485 mode.

RA1 (Pin 24): Receiver Output.
RB1 (Pin 25): Receiver Output.
Vee (Pin 26): Positive Supply; 4.75V:5: Vcc:5: 5.25V
C2- (Pin 27): Com mutating Capacitor C2 Negative Terminal. Requires 0.1 pF external capacitor between Pins 27
and 28.
C2+ (Pin 28): Commutating Capacitor C2 Positive Terminal.

FunCTion TABLES
RS485 Driver Mode
ON/OFF

1
1
1
1
0

RS232 Driver Mode

INPUTS
SEL
DE

1
1
1
1
1

1
1
1
0
X

D

CONDITIONS

0
1
X
X
X

No Fault
No Fault
Thermal Fault
X
X

OUTPUTS
Z
Y

0
1
Z
Z
Z

1
0
Z
Z
Z

RS485 Receiver Mode

ON/OFF

INPUTS
SEL

D

CONDITIONS

Y, Z

1
1
1
0

0
0
0
0

0
1
X
X

No Fault

1
0
Z
Z

OUTPUTS

No Fault
Thermal Fault
X

RS232 Receiver Mode

ON/OFF

INPUTS
SEL

OUTPUTS

B-A

1

1

<-O.2V

1

1

1
0

1
1

> O.2V
Inputs Open

RA
0
1
1

Ra'
1
1

X

Z

Z

1

ON/OFF

INPUTS
SEL

A, B

1
1
1
0

0
0
0
0

0
1
Inputs Open
X

OUTPUTS

RA, Ra
1
0
1
Z

'See Note 5

13-57

LTC 1334
BLOCK DIAGRAmS
Interface Configuration with Loopback Disabled
PORT 1 = RS485 MDDE
PORT 2 = RS232 MOOE
.28

PORT 1 = RS232 MODE
PORT 2 = RS232 MODE
28

PORT 1 = RS232 MODE
PORT 2 = RS485 MODE
28

PORT 1 = RS485 MODE
PORT 2 = RS485 MODE
28

Cl

C2

Vee
4

-';;:-Al

RBl
RAl

81

DZl

Yl
Zl

OYl

SELl = 5V
[jj

[jj

ON

ON

DY2

DY2

DE2

DE2

RA2

RA2

RB2
VEE

~

.".

Interface Configuration with Loopback Enabled
PORT 1 = RS232 MODE
PORT 2 = RS232 MODE
28
Cl

PORT 1 = RS485 MODE
PORT 2 = RS232 MODE
28

PORT 1 = RS232 MODE
PORT 2 = RS485 MODE
28

C2 Cl

C2 Cl

PORT 1 = RS485 MODE
PORT 2 = RS485 MODE
28
C2 Cl

C2

RBl
RAl
Yl

Yl

Zl
SELl =5V ~1--4,....JI""

DEl

Zl
SEL1 =5V ~-"""...I""

SEL2 = 5V
19
18
17

DY2
Dll

...:9+-~~

Z2 10

DY2

Y2 11

DE2

RA'

16
15

RB'
VEE

~

13-58

-:::c:LTC13S4oBO02

":'"

LTC 1334
TEST CIRCUITS
z--,-...,
R

R

Vae

15pF

1

LTCl334·FOl

LTC1334'F03

Figure 1. RS485 Driver
Test Load

Figure 2. RS485 Driver/Receiver
Timing Test Circuit

Figure 3. RS485 Driver Output
Enable/Disable Timing Test Load

Figure 4. RS232 Driver
Timing Test Circuit

Figure 5. RS232 Receiver
Timing Test Circuit

;WITCHlnG WAVEFORmS

3V

f = lMHz: I, ~ IOns: If';; IOns

D
OV
Va

90%

z-v

VDIFF = V(Z) - V(V)

-Va

v

__~~¥*___~,:_a______¥~~__
Va

-11-tSKEW

-11-tsKEW

Figure 6. RS485 Driver Propagation Delays

13-59

LTC 1334
SWITCHinG WAVEFORms
3V------~r---~f=~I~MH~Z:74~s~10~ns~:~~s7.10~ns--~
DE
oV------'

-------+--

5V
V,Z
VOL ______

1LZ1_

-+_____ . . .__..:::O;:,:UT;",:PU:.:,.TN:.:.:O::.::RM:::;A:::.::LL~YL;;:,OW::.-!-_

VOH

!-IHZ- +

------------+, __....:O:;.::U.;;,TP.;:.UT:...;,N:.:;;OR.;::M:;.::AL::.LV:...;,H;::IG;:.:.H____.....

O.5V

1_ _
•

O.5V

Z, V
OV - - - - - - - - - - - '
LTCl334·Rl7

Figure 7. RS485 Driver Enable and Disable Times

B-A

VOD2 --------r-.....,..~.....,..-:-::-.....,...-:-::-----~
OV f=IMHz:I,sI0ns:lp;10ns
INPUT

-VOD2 - - - - - - '
VOH _________I_PL_·:--+L,..________--.,;.O.;..UT.;..PU;...T____
1P_.j

R

71.5V
VOL __________..J

" \ : .5V
'-----"7"'~,~~4.-::::ro'

Figure 8. RS485 Receiver Propagation Delays
3V
D

OV
Va
V,Z
-Va

{~

"{.

~.

'WJ

LTC1334°F09

Figure 9. RS232 Driver Propagation Delays

VIH
A, B
VIL
VOH
R
VOL

t:"~J

{"

'"~

O.BV

Figure 10. RS232 Receiver Propagation Delays

13-60

2.4V

lTCl334°F10

LTC 1334
~PPLICATlons
~asic

InFORmATion

Theory of Operation

rhe LTC1334 has two interface ports. Each port may be
~onfigured as apair of single-ended RS232 transceivers
Jr as a differential RS485 transceiver by forcing the
Jort'sselection inputtoa LOWor HIGH, respectively. The
_TC1334 provides two RS232 drivers and two RS232
'eceivers or one RS485 driver and one RS485 receiver
Jer port. All the interface drivers feature three-state
Jutputs. Interface outputs are forced into high impedwce when the driver is disabled in the shutdown mode
Jr with the power off.
~II the interface driver outputs are fault-protected by a
;urrent limiting and thermal shutdown circuit. The thernal shutdown circuit disables both the RS232 and RS485
1river outputs when the die temperature reaches 150°C.
rhe thermal shutdown circuit re-enables the drivers when
:he die temperature cools to 130°C.

n RS485 mode, Shutdown mode or with the power off,
he input resistance of the receiver is 24k. The input
'esistance drops to 5k in RS232 mode.
~ logic LOW at the ON/OFF pin

shuts down the device an.d
orces all the outputs into a high impedance state. A logic

HIGH enables the device. An internal4~ current source
to Vee pulls the ON/OFF pin HIGH if it is left open.
In RS485 mode, an internal 4~ current source pulls the
driver enable pin HIGH if left open. The RS485 receiver has
a 4~ current source at the noninverting input. If both !he
RS485 receiver inputs are open, the output goes to a high
state. Both the current sources are disabled in the RS232
mode. The receiver output Bis inactive in RS485 mode and
has a50k pull-up resistor to provide aknown output state
in this mode.
Aloopback mode enables internal connections from ?river
outputs to receiver inputs for self-test when the LB pin has
aLOW logic state. The driver outputs are not isolated from
the external loads. This allows transmitter verification
under the loaded condition. An internal4~ current source
pulls the LB pin HIGH if left open and disables the loop back
configuration.
RS232/RS485 Applications
The LTC1334 can support both RS232 and RS485 levels
with a single 5V supply as shown in Figure 11.

28
C2
Vee
5V

0.11lF

27

LTC1334

2 0.11lF

26

TO. 1IlF

RXOUT

OR ENABLE
ORIN
5V
5V
OR IN
ORIN

C1
VDD

TO. 1IlF

24
23

1200 RS485 110
22
21

5V

20
19
18

RXOUT

III
Figure 11. RS232JRS485 Interlaces

13-61

LTC 1334
RPPLICRTlons InFoRmRTlon
Multi-Protocol Applications
28

LTC1334

1-=----:'-='

C1

,.....,.CI-.-HI-'- INPUT A

tv--r- INPUT B
IX>.......-+"- OUTPUT A

"';;';;;~-Q~-+t..:..7-

PORT1
INTERFACE

The LTC1334 is well-suited for software controlled interface mode selection. Each port has a selection pin as
shown in Figure 12. The single-ended transceivers support both RS232 and EIA562 levels. The differential transceivers support both RS485 and RS422.

Typical Applications
A typical RS232/EIA562 interface application is shown in
Figure 13 with the LTC1334.

OUTPUT B

1/2 LTC1334

1/2 LTC1334

DR IN 19

11

RS2321

DR IN 18

10

EIA562

4

25 RX OUT

RX OUT 17

13 INTERFACE

22 DR IN

RX OUT 16

12

23 DR IN
8

LINES

9

,.....,.a-ri-iF-INPUT A

LTC1334.F13

RX OUT -,,17+r+<

CJ.....I-~.:;...INPUT B

1'0-.......+:... OUTPUT A

Figure 12. Multi-Protocol Interface

PORT 2
INTERFACE

A typical connection for a RS485 transceiver is shown ir
Figure 14. Atwisted pair of wires connects up to 32 driver~
and receivers for half duplex multipoint data transmission.
The wires must be terminated at both ends with resistor~
equal to the wire's characteristic impedance. An optiona
shield around the twisted pair helps to reduce unwantec
noise and should be connected to ground at only one end

1/2 LTC1334

RX OUT 24

RX OUT

DR ENABLE 23

DR ENABLE

DR IN 22

DR IN

8

'-----'r-- 5V

Figure 14. Typical Connection for RS485 Interface

13-62

"':"

Figure 13. Typical Connection for RS232/EIA562 Interface

1/2 LTC1334

5V

24 RX OUT

LTC 1334
APPLICATions InFoRmATion
A typical RS422 connection (Figure 15) allows one driver
and ten receivers on atwisted pair of wires terminated with
a 100n resistor at one end.
A typical twisted-pair line repeater is shown in Figure 16.
As data transmission rate drops with increased cable
length, repeaters can be inserted to improve transmission
rate or to transmit beyond the RS422 4000-foot limit.
The LTC1334 can be used to translate RS232 to RS422
interface levels or vice versa as shown in Figure 17. One

port is configured as an RS232 transceiver and the other
as an RS485 transceiver.
Using two LTC1334s as level translators, the RS2321
EIA562 interface distance can be extended to 4000 feet
with twisted-pair wires (Figure 18).
AppleTalk®/LocaITalk® Applications
An AppleTalk application is shown in Figure 19 with the
LTC1323 and the LTC1334.
AppleTalk and LocalTalk are registered trademarks of Apple Computer, Inc.

112 LTC1334
RX OUT

DR ENABLE
DR IN
5V

RXOUT

Figure 15. Typical Connection for RS422 Interface

5V

R ? f 2 j !10on

~CJ

~

:

5V

RX IN _1:.::,3H.;>o-'
RS232/EIA562
TXOUT

TX OUT _1:.:,1+-~

112 LTC1334

Figure 16. Typical Cable Repeater for RS422 Interface

Figure 17. Typical RS232/EIA562 to RS422 Level Translator

5V

RX IN ....:1,::.3H:>o-'

L..f>o-+1;";,,.1 DR OUT
RS232/EIA562

RS232/E1A562
DR OUT _1;";,,.1t--<> TA:> 70°C
PARAMETER
I CONDITIONS

MIN

TYP

MAX

UNITS

Differential Receiver
Differential Input Voltage Thresholds

-7V~VeM~12V

Receiver Input Hysteresis

-7V ~ VeM ~ 12V

-0.2

0.2

Input Resistance

12

Input Common-Mode Voltage

-7

V
mV

70

kO
12

V

Output Voltage

Output High, lOUT =16011A
Output Low, loup -1.6mA

2.4

4.0
0.2

0.4

V
V

Output Short-Circuit Current

Sinking Current, VOUT =Vee
Sourcing Current, VOUT =OV

-20

-10
10

20

mA
mA

40

70

ns

2.4

V
V

0.1

1.3
1.7
0.4

1.0

V

3

5

7

kO

0.2
4.2

0.4

3.5

V
V

Propagation Delay
Smgle-Ended Receiver
Input Voltage Threshold

Input Low Threshold
Input High Threshold

0.8

Hysteresis
Input Resistance

-5V ~VIN ~ 5V

Output Voltage

Output Low, lOUT =-1.6mA
Output High, lOUT =160mA (Vee =5V)

Output Short-Circuit Current
Propagation Delay

Sinking Current, VOUT =Vee
Sourcing Current, VOUT =OV

-20

Output Transition High to Low, tHL
Output Transition Low to High, tLH

-10
10

20

mA
mA

250
350

600
600

ns
ns

4.0
-4.4

-3.7

V
V

Single-Ended Drivers
Output Voltage

Output High, RL =3k
Output Low, RL =3k

3.7
-10

10

Output Leakage Current

Logic Input Current
Shutdown or Driver Disable Modes

-100

100

Output Short-Circuit Current

Sinking Current, VOUT =OV
Sourcing Current, VOUT =OV

-40

-10
50

60

100

Slew Rate
Propagation Delay

60

mA
mA
100

Driver Disable Delay

40

75

Driver Enable Delay

60

100

Note 1: Absolute maximum ratings are those values beyond which the life
of the device may be impaired.
Note 2: Unless otherwise specified, testing done at Vee = 5V, VEE = -5V
and VTXEN = OV. Outputs and single-ended receiver inputs are open. Driver
inputs are tied to Vce. Differential receiver input RD- is biased at 2.6V,
RD+ at 2.4V.

IIA
IIA
V/JJS
ns
ns
ns

Note 3: For driver delay measurements, RL = 3k and CL = 51 pF. Trigger
points are set between the driver's input logic threshold and the output
transition to the zero crossing. (tHL =tLH =1.4V to OV)
Note 4: For receiver delay measurements, CL = 51 pF. Trigger points are
set between the receiver's input logic threshold and the output transition
to standard TTL/CMOS logic threshold. (tHL = 1.3V to 2.4V and tLH = 1.7V
toO.8V)

~

-----------------------------~
Pin
Funalons
RXEN (Pin 1): Receiver Enable Control. An open pin or a
logic low allows normal operation of the receivers. Alogic
high causes receiver outputs to become high impedance,
allowing sharing of the receiver output data lines.

GND (Pin 2): Ground Pin.
RS OUT (Pin 3): Single-Ended Receiver Output with TTU
CMOS Voltage Levels. The output is fully short-circuit
protected to GND or Vee.

13-75

LT1389

Pin FunOlons
RO OUT (Pin 4): Differential Receiver Output Pin with TTU
CMOS Voltage Levels. The output is fully short-circuit
protected to GND or Vee.
TS IN (Pins 5, 6): Single-Ended Driver Input Pins. These
inputs are TTUCMOS compatible. An input logic low
causes a driver output high. Tie unused inputs to GND.
TO IN (Pin 7): Differential Driver Input Pin. ATTUCMOS
compatible logic input. A logic high causes driver output
RDt to swing high and RD-Iow. Tie input to Vee when not
in use.
TXEN (Pin 8): A TTUCMOS logic high places the driver
outputs into a high impedance state. A logic low fully
enables the transmit capabilities. Transitions occur at data
rate speeds to facilitate data line multiplexing.
VEE: (Pin 9): -5V Input Supply Pin. This pin should be

decoupled with a 0.11JF ceramic capacitor.
Vcc (Pin 10): 5V Input Supply Pin. This pin should be
decoupled with a 0.11JF ceramic capacitor.
TO OUTt, TO OUT- (Pins 11, 12): Differential Driver
Output Pins. Outputs drive 100n differential loads to
RS422 levels, and are also capable of supplying RS562
levels to single-ended loads greater than 3kn. Outputs are

in a high impedance state when TXEN is high or Vee = OV.
Outputs are fully short-circuit protected from VOUT = VEE
+ 20V to VOUT = Vee - 20V. Applying higher voltages will
not damage the device if the overdrive is moderately
current limited.
TS OUT (Pins 13, 14): Single-Ended Driver Outputs at
RS562 Voltage Levels. Outputs are in a high impedance
state when TXEN is high or Vee = OV. Outputs are fully
short-circuit protected from VOUT = VEE + 20V to VOUT =
Vee - 20V. Applying higher voltage will not damage the
device if the overdrive is moderately current limited.
RO-, ROt (Pins 15, 16): Differential Receiver Input Pins.
Common-mode input range is-7Vto 12V. Receiver inputs
have 50mV of hysteresis for noise immunity.
RS IN (Pin 17): Single-Ended Receiver Input. This pin
accepts RS232 or RS562 level signals (±30V) into a
protected 5k terminating resistor. The receiver input provides O.4V of hysteresis for noise immunity. Data rates to
120kbaud are supported.
ON/OFF (Pin 18): A logic low level on this pin shuts down
the circuit. All receiver and driver outputs are high impedance. A logic high allows normal operation of the circuit.

TEST CIRCUITS

1388F01

Figure 1. Differential Output Test Circuit

Figure 2. Single·Ended Output Test Circuit

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC1320

Appletalk Transceiver

Complete OTE Port

LTC1334

RS2321RS485 Multi-Protocol Transceiver

Appletalk Compatible

LTC1337

5V 3-0river/5-Receiver Micropower RS232 Transceiver

500J,IA Quiescent Current

LTC1345

V.35 Differential Transceiver

Low Power V.35 Solution

LTC1348

3.3V 3-0river/5-Receiver RS232 Transceiver

True RS232 from 3.3V Supplies

13-76

£.7LIn

UU'\JU U UlFIlLS lnlLSLSLSlFIl@LS

Final Electrical Specifications

LTC 1392
TECHNOLO·~G~IY~--M-i-C-rO-p-o-w-e-r~-e-m-p-e-ra-t-u-re-,
Power Supply and
Differential Voltage Monitor
July 1995

FEATURES

DESCRIPTion

• Complete Ambient Temperature Sensor Onboard
• Power Supply Monitor
• 10-Bit Resolution Rail-to-Rail Common-Mode
Differential Voltage Input
• Available in 8-Pin SO
• O.2~ Supply Current When Idle
• 350~ Supply Current When Converting
• Single Supply Voltage: 4.5V to 6V
• Three-Wire Half-Duplex Serial 1/0
• Communicates with Most MPU Serial Ports and All
MPU Parallel 1/0 Ports

The LTC@1392 is a micropower data acquisition system
designed to measure temperature, on-chip supply voltage
and differential rail-to-rail common-mode voltage. The
device features a temperature sensor, a 1O-Bit AID converter with sample-and-hold, a high accuracy bandgap
reference and a three-wire half-duplex serial interface.

APPLICATions
•
•
•
•

Temperature Measurement
Power Supply Measurement
Current Measurement
Remote Data Acquisition

The LTC1392 can be programmed to measure ambient
temperature, power supply voltage and external voltage at
the differential input pins, which can be used for current
measurement. When measuring temperature, the output
code of the AID converter is linearly proportional to the
temperature in °Celsius. Wafer level trimming achieves
±2°C initial accuracy at room temperature and ±4°C over
the full-40°C to 85°C temperature range.
The on-chip serial port allows efficient data transfer to a
wide range of MPUs over three wires. This, coupled with
low power consumption, makes remote location sensing
possible and facilitates transmitting data through isolation barriers.
LT, LTC and IT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Complete Temperature, Supply Voltage and
Supply Current Monitor

Output Temperature Error
- - - lTC1392C
GUARANTEED
LIMIT

----- lTC13921
GUARANTEED
LIMIT

lTC1392
P1.4 1---+-l1 DIN
MPU

2 DOUT

(e.g., 68HC11)
3 ClK
P1.31----"-I
P1.2

4

CS

--TYPICAL

Vee 8
-VIN ~7+-_..
+VIN 6
GND 5
_5L-~~-L~_L-~~

-40 -20

0

20

40

60

80

100

TEMPERATURE eC)

13-77

LTC1392
ABSOLUTE mAXimum RATinGS

PACKAGE/ORDER InFORmATion

(Note 1)

Supply Voltage (Vee) ................................................ 7V
Input Voltage ................................. -O.3V to Vee + O.3V
Output Voltage ............................... -O.3V to Vee + O.3V
Operating Temperature Range
Commercial ............................................ O°C to 70°C
Industrial ........................................... -40°C to 85°C
Junction Temperature .......................................... 150°C
Storage Temperature Range ................ - 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER

TOP VIEW

"0'·

DOUT 2
ClK 3

cs

6 +VIN

4

N8 PACKAGE
8-lEAD PDIP

LTC1392CN8
LTC1392CS8
LTC13921N8
LTC13921S8

7 -VIN

5 GND

S8 PACKAGE
8-lEAD PLASTIC SO

S8 PART MARKING

TJMAX = 150·C, OJA = 1OO·C/W (N8)
TJMAX = 150·C, OJA= 150·CIW (S8)

1392
13921

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS
PARAMETER

(Note 3)

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply To Digital Conversion
Resolution
Total Absolute Error

Vcc =4.5V to 6V

10

Bit

Vce =4.5V to 6V, O°C ~ TA ~ 700 e
Vce =4.5V to 6V, -40°C ~ TA ~ 85°C

±5
±8

LSB
LSB

oillerential Voltage to Digital
Conversion (Full-Scale Input =1V)
Resolution

10

Integral Linearity Error (Note 5)
Oifferential Linearity Error
Offset Error
Full-Scale Error
Input Refered Noise

•
•
•
•

LSB

±1

LSB
LSB

•
•
•
•

±4

LSB

±2

LSB

±4
±10
±1

Differential Voltage to Digital
Conversion (Full-Scale Input =O.5V)
Resolution
Oifferential Linearity Error
Offset Error
Full-Scale Error
Input Refered Noise

LSB
LSBRMS

10

Integral Linearity Error (Note 5)

Bit

±2

±8

Bit

LSB
±20

±2

LSB
LSBRMS

Temperature to Digital Conversion (LTC1392)
Accuracy

TA=25°C (Note 7)
TA =TMAX or TMIN (Note 7)

Nonlinearity

TMIN ~ TA ~ TMAX (Note 4)

13-78

••

±2
±4
±1

°C
°C
°C

LTC 1392
ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

ION lEAKAGE

On-Channel leakage Current (Note 6)

10FF lEAKAGE

Off-Channel leakage Current (Note 6)

(Nole 3)

High level Input Voltage

Vee = 5.25V

Vil

low level Input Voltage

Vee = 4.75V

IIH

High level Input Current

III

low level Input Current

VOH

High level Output Voltage

Vee = 4.75V, lOUT = 1011A
Vec = 4.75V, lOUT = 36011A

VOL

low level Output Voltage

loz

Hi-Z Output Current

Vec = 4.75V, lOUT = 1.6mA
CS High

IsouReE

Output Source Current

VOUT = OV

VIN = Vee
VIN = OV

ISINK

Output Sink Current

Icc

Supply Current

tSMPl

Analog Input Sample Time

VOUT = Vee
CS High
teve = 76118, felK = 250kHz
See Figure 1

teoNv

Conversion Time

See Figure 1

41Do

Delay Time, ClK,!, to DOUT Data Valid

CLOAD = 100pF

4!n

Delay Time, ClK,!, to DOUT Data Enabled

CLOAD = 100pF

41is
thDO
t,

Delay Time, CS I to DOUT Hi-Z

CIN

TYP

•

VIH

tr

MIN

CONDITIONS

Time Dutput Data Remains Valid After ClK,!,

CLOAD = 100pF

DOUT Fall Time

CLOAD = 100pF

DOUT Rise Time
Input Capacitance

CLOAD = 100pF
Analog Input On-Channel
Analog Input Off-Channel

•
•
•
•
•
•
•
•

MAX
±1
±1
0.4

V

5
-5

IIA
IIA

4.74
4.72

V
V
0.4
±5

-25
0.1
300

ClK Cycles

150

300

60

150

ns

170

450

ns

30

Digital Input

IIA
IIA
ClK Cycles

10

•

IIA
mA

5
500

1.5

•
•
•
•

V
mA

45

•

IIA
IIA
V

2

4.5
2.4

UNITS

ns

ns

70

250

ns

25

100

ns

30
5

pF
pF

5

pF

REcommEnDED OPERATinG conDITions
SYMBOL

PARAMETER

Vee

Supply Voltage

fClK

Clock Frequency

tcve

CONDITIONS

MIN

TYP

MAX

UNITS

4.5

6

V

50
74
144

250

kHz

Total Cycle Time

Vee = 5V
fClK = 250kHz
Temperature Conversion Only

thDi

Hold Time, DIN After ClKI

Vee = 5V

150

118
118
ns

lsucs
tWAKEUP

Setup Time CS'!' Before First ClKI (See Figure 1)
Wakeup Time CS'!' Before Start Bitl (See Figure 1)

Vee = 5V

2

118

Vee = 5V
Temperature Conversion Only

10
80

tsuDI

Setup Time, DIN Stable Before ClKI

Vce = 5V

150

118
118
ns

tWHelK

Clock High Time

Vec = 5V

1.6

118

tWlClK
tWHCS

Clock low Time

Vcc = 5V
Vcc = 5V, fClK = 250kHz

2

118

2

118

tWlCS

CS low Time During Data Transfer

72
142

118
118

CS High Time Between Data Transfer Cycles

Vcc = 5V, fClK = 250kHz
Temperature Conversion Only

13-79

LTC1392
REcommEnDED OPERATinG COnDITiOnS
The. denotes specifications which apply over the operating temperature
range (DoC::; TA::; 70°C for commercial grade and -40°C::; TA::; 85°C for
industrial grade).
Nole 1: Absolute maximum ratings are those values beyond which the life
of the device may be impaired.
Nole 2: All voltage values are with respect to GND.
Note 3: Testing done at Vcc =5V, ClK =250kHz and TA =25°C unless
otherwise specified.

Nole 4: Temperature integral nonlinearity is defined as the deviation of the
AID code versus temperature curve from the best-fit straight line over the
device's rated temperature range.
Nole 5: Voltage integral nonlinearity is defined as the deviation of a code
from a straight line passing through the actual end points of the transfer
curve.
Nole 6: Channel leakage current is measured after the channel selection.
Nole 7: See guaranteed temperature limit curves vs temperature range on
the first page of this data sheet.

TYPICAL PERFORmAnCE CHARAOERISTICS
Differential Nonlinearity,
Power Supply Voltage Mode
"' 1.0

'"

~

a:

15

0.5

Supply Current vs Temperature
350

,----,---,---.---,--,--.,----.,----~

~
o

Integral Nonlinearity,
Power Supply Voltage Mode

1-+-+-+-+--+--+--+---1-----1

345

~

15
a:

0.5

1--+-+-+-+-+-+-+-+-1

ffi

E:

o

a: 330

~

a:
~

~ O~~~~~
z

z
::::;
z
o
z

~

::::;

~-0.5 1--+---+---+---+-+-+-+-+--1

z
o
z
:;;!-0.5

It

ffi
~

1li
a:

o -1.0

'--'---'---'---"---"---"---"----'----'
256 320 384 448 512 576 640 704 768 832
CODE

a:

~ 340
:::>
!; 335

1--+---+-+-+-+-+-+-+-1

-1.0 '--'---"---"---"---"----"---"---'--'
256 320 384 448 512 576 640 704 768 832
CODE

325
o
:;;! 320
;::
ijj 315
a:
310
0 305

-- - r-

'"'""-r-.

tt

300
-40 -20

0
20 40
60
TEMPERATURE (Oc)

80

100

Pin FunCTions
DIN (Pin 1): Digital Input. The AID configuration word is
shifted into this input.

+VIN (Pin 6): Positive Analog Differential Input. The pin
can be used as a single-ended input by grounding -VIN.

DOUT (Pin 2): Digital Output. The AID result is shifted out
of this output.

- VIN (Pin 7): Negative Analog Differential Input. The input

CLK (Pin 3): Shift Clock. This clock synchronizes the serial
data.

Vcc (Pin8): Positive Supply. This supply must be kept free
from noise and ripple by bypassing directly to the ground
plane.

CS (Pin 4): Chip Select Input. A logic Iowan this input
enables the LTC1392.
GND (Pin 5): Ground Pin. GND should be tied directly to
an analog ground plane.

13-80

must be free from noise.

LTC1392
BLOCK DIAGRAm
r------------------------------------.------~----~3~ClK

10-BIT
CAPACITIVE DAC

+ ANALOG
INPUT
MUX

VREF- +VIN -"---.....,~
-VIN

10
BITS

10-BIT
SAR

I-----tl\-----<.--I

+

':"""---+L=--_..J
4CS

Is

VCC

GND

TEST CIRCUITS
Voltage Waveforms for DDUT Delay Time, IdDD

Load Circuil for tdDD, Ir and I,
1.4V

ClK)

_V~IL

_ _ _ _ _ _ _ _ _ ___

3k
DOUT I---~~----- TEST POINT
- ' - 100pF

0,.

T

--.£

-lrJL

____________ :::
LTC1392·TC03

Voltage Waveforms for DOUT Rise and Fall Times, Ir and I,
DOUT

-'''~

Vollage Waveforms for Idis

[--- '.
- - - - - -

----..

tf

VOL

1291TCD4

Load Circuit for tdis and len

DOUT
WAVEFORM 1
(SEE NOTE 1)
DOUT
WAVEFORM 2
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNTIL DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 21S FOR AN OUTPUT WITH INTERNAL CONDITiONS SUCH
THAT THE OUTPUT IS LOW UNTIL DISABLED BY THE OUTPUT CONTROl.

TEST POINT

LTC1S92-rcos

3k
DOUT

5V Idis WAVEFORM 2, len

1-+-1II'o1'v-CY"-

L--_---'

T

.L7lJ!J£OO

f l d l S WAVEFORM 1
100pF

13-81

LTC 1392
APPLICATions InFoRmATion
The lTC1392· is a micropower data acquisition system
designed to measure temperature, on-chip power supply
voltage and differential input voltage. The l TC1392 contains the following functional blocks:
1. On-chip temperature sensor
2. 1O-bit successive approximation capacitive ADC
3. Bandgap reference
4. Analog multiplexer (MUX)
5. Sample-and-hold (S/H)
6. Synchronous, half-duplex serial interface
7. Control and timing logic

DIGITAL CONSIDERATIONS
Serial Interface
The lTC1392 communicates with microprocessors and
other external circuitry via a synchronous, half-duplex,
three-wire serial interface (see Figure 1). The clock (ClK)
synchronizes the data transfer with each bit being transmitted on the falling ClK edge and captured on the rising
ClK edge in both transmitting and receiving systems. The
input data is first received and then the AID conversion
result is transmitted (half-duplex). Half-duplex operation
allows DIN and DOUT to be tied together allowing transmission over three wires: CS, ClKand DATA (DIN/DoUT)' Data
transfer is initiated by afalling chip select (CS) signal. After
the falling CS is recognized, an 80J1S delay is needed for
temperature measurement or a1OJ1S delay for other measurements, followed by a 4-bit input word which configures the lTC1392 for the current conVersion. This data
word is shifted into the DIN input. DIN is then disabled from
shifting in any data and the DOUT pin is configured from
three-state to an output pin. A null bit and the result of the
current conversion are serially transmitted on the falling
ClK edge onto the DOUT line. The format of the AID result
can be either MSB-first sequence or MSB-first sequence
followed by an lSB-first sequence. This provides easy
interface to MSB- or lSB-first serial ports. Bringing CS
high resets the lTC1392 for the next data exchange.

13-82

INPUT DATA WORD
The lTC1392 4-bit input word is clocked into the DIN input
on the first four rising ClK edges after CS is recognized.
Further inputs on the DIN input are then ignored until the
next CS cycle. The four bits of the input word are defined
as follows:
BIT3

BITo

Start

MSBF

Start Bit
The first "logic one" clocked into the DIN input after CS
goes low is the Start Bit. The Start Bit initiates the data
transfer and all leading zeros which precede this logical
one will be ignored. After the Start Bit is received the
remaining bits of the input word will be clocked in. Further
input on the DIN pin are then ignored until the next CS
cycle.
Measurement Modes Selection
The two bits of the input word following the Start Bit assign
the measurement mode for the requested conversion.
Table 1 shows the modes selection. Whenever there is a
mode change from another mode to temperature measurement, atemperature mode initializing cycle is needed.
The first temperature data measurement after a mode
change should be ignored.
Table 1. Measurement Modes Selection
SELECT
1

0
0
1
1

SELECT

0
0
1
0
1

MEASUREMENT MODE
Temperature
Power Supply Voltage
Differential Input, 1V Full Scale
Differential Input, O.SV Full Scale

MSB-FirstlLSB-First (MSBF)
The output data of the lTC1392 is programmed for
MSB-first or lSB-first sequence using the MSBF bit. When
the MSBF bit is a logical one, data will appear on the DOUT

LTC 1392
APPLICATions InFoRmATion
MSB-First Data (MSBF =1)
I-
·--------------tcvc---------------~·I

~I~------------------------------~~
__1 I--tsucs
elK
twAKEUP

---''777:''777.'7777=''777.'7777==''777==''777.'7777==''777==''777'7777======m

r-- SEl t FSE;;:,.lO
DIN~
--j

START

MSBF
Hi-Z

Dour _....;H:::.,:i-Z,--_+---..

FillED WITH ZEROS

MSB-First Data (MSBF =0)
I-I·--------------t~---------------~·I

~I~---------------------------------~
-I 1-"""
elK
tWAKEUP

r-- SELl SElO
DIN~
--j

START

MSBF
HI-Z

DOUT _-""Hi-Z"-_-f---.

FillED WITH ZEROS

Figure 1.

line in MSB-first format. Logical zeros will be filled in
indefinitely following the last data bit to accommodate
longer word lengths required by some microprocessors.
When the MSBF bit is a logical zero, LSB-first data will
follow the normal MSB-first data on the Dour line.
CONVERSIONS

Temperature Conversion
The LTC1392 measures temperature through the use of an
on-chip, proprietary temperature measurementtechnique.
The temperature reading is provided in a 1a-bit, unipolar
format. Table 2 describes the exact relationship of output
data to measured temperature or equation 1 can be used
to calculate the temperature.
Temperature (OC) =Output Code/4 -130

Note that the LTC13921 is only specified for use over the
-40°C to 85°C operating temperature range. Temperature
outside this range may have errors greater than those
shown in the electrical characteristic table.
Table 2. Codes for Temperature Conversion
OUTPUT COOE

TEMPERATURE (OC)

1111111111
1111111110
...
1001110101
1001110100
1001110011

125.75
125.50

...
27.25
27.00
26.75

...

...

0000000001
0000000000

-129.75
-130.00

•

(1)

13-83

LTC1392
APPLICATions InFoRmATion
Voltage Supply (Vce) Monitor
The LTC1392 measures supply voltage through the onchip Vee supply line. The Vee reading is provided in a
10-bit, unipolar format. Table 3 describes the exact relationship of output data to measured Vee or equation (2)
can be used to calculate the measured Vee.
Measured Vee =
(7.26 - 2.42) x Output Code/1 024 + 2.42
(2)
The guaranteed supply voltage monitor range is from 4.5V
to 6V. Typical parts are able to maintain the measurement
accuracy with Vcc as low as 3.25V. The typical INL and
DNL error plots shown on page 4 are measured with Vee
from 3.63V to 6.353V.
Table 3. Codes for Voltage Supply Conversion
OUTPUT CODE

Supply Voltage (Vee)

1011110110
1011110101
...
1000100010

6.003V
5.998V

...
0110111001
0110111000

...
5.001V
...
4.504V
4.500V

Differential Voltage Conversion
The LTC1392 measures the differential input voltage
through pins+ VINand-VIN.lnput rangesofO.5Vor1Vfull
scale are available for differential voltage measurement

13-84

with resolutions of 10 bits. Tables 4a and 4b describe the
exact relationship of output data to measured differential
input voltage in the 1Vand 0.5V input range. Equations (3)
and (4) can be used to calculate the differential voltage in
the 1V and 0.5V input voltage range respectively. The
output code is in unipolar format.
Differential Voltage = 10-bit code/1 024
Differential Voltage = 0.5 x (10-bit code)/1024

(3)
(4)

Table 4a. Codes for 1V Differential Voltage Range
OUTPUT
CODE

INPUT
VOLTAGE

INPUT
RANGE=1V

1111111111

1V -1LSB

999.0mV

1111111110

1V - 2LSB
...
1LSB
OLSB

998.0mV
...
0.977mV
O.OOmV

...
0000000001
0000000000

REMARKS

1LSB = 1/1024

Table 4b. Codes forO.5V Differential Voltage Range
OUTPUT
CODE

INPUT
VOLTAGE

INPUT
RANGE = O.5V

1111111111

O.SV -1LSB

499.0mV

1111111110

0.5V -2LSB
...
1LSB
OLSB

498.1mV
...
0.488mV
O.OOmV

...
0000000001
0000000000

REMARKS

1LSB = 0.5/1024

LTC 1392
TYPICAL APPLICATions
System Monitor for Two Supply Voltages and Ambient Temperature

r - - - - - - - t fB

P1.4
MPU
(e.g., 8051)
P1.3
P1.2

GND

C1
220pf
M1,M2,M3:
MOTOROLA MTD20N03Hl

System Monitor for Relative Humidity, Supply Voltage and Ambient Temperature

1/4LTC1043

16

5V

~O.l~f
-5V
17

5V

4700
1k
1%

P1.4

10k

1J

MPU
(e.g., B051)
P1.3
P1.2

l~f

SENSOR

22M

10k
5%
RHTRIM

1k
1%

33k

SENSOR: PANAMETRICS IRHS
500pf AT RH = 76%
l.7pf/%RH

RELATED PARTS
~ART

NUMBER
_T1025

DESCRIPTION

Micropower Thermocouple Cold Junction Compensator
_TC1285/LTC1288 3V Micropower 12-Bit ADC with Auto Shutdown

COMMENT
Compatible with Standard Thermocouples (E, J, K, R, S, T)
Differential or 2-Channel Multiplexed, Single Supply

_TC1286/LTC1298 Micropower 12-Bit ADC with Auto Shutdown

Differential or 2-Channel Multiplexed, Single Supply

_TC1390

SPI, aSPI Compatible, Single 5V or 3V, Low RON, Low Charge Injection

Low Power, Precision 8-to-1 Analog Multiplexer

13-85

f ~ LIn~
1Plfi1~lbUlli'ilJUINJLA\lfi1l1
~~ TECHNOLOG~~~-----c-O-m-p-le-t-e-S-O--8-~-~-~~-~-I~
400ksps ADC with Shutdown
May 1995

FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•
•
•
•

The LTC®1400 is a complete 400ksps, 12-bit AID converterwhich draws only75mWfrom a5Vor± 5V supplies.
This easy-to-use device comes complete with a 200ns
sample-and-hold and a precision reference. Unipolar and
bipolar conversion modes add to the flexibility ofthe ADC.
The LTC1400 is capable of going into two power saving
modes: NAP and SLEEP. In SLEEP mode, it consumes
only 6mW of power and can wake up and convert immediately. In the SLEEP mode, it consumes 30llW of power
typically. Upon power-up from SLEEP mode, a reference
ready (REFRDY) signal is available in the serial data word
to indicate that the reference has settled and the chip is
ready to convert.

Complete 12-Bit ADC in SO-8
Single Supply 5V or ±5V Operation
Sample Rate: 400ksps
Power Dissipation: 75mW (Typ)
70dB S/(N + D) and 74dB THO at Nyquist
No Missing Codes over Temperature
NAP Mode with Instant Wake-Up: 6mW
SLEEP Mode: 30llW
High Impendance Analog Input
Input Range (1 mVlLSB): OV to 4.096 or ± 2.048V
Internal Reference Can Be Overdriven Externally
3-Wire Interface to DSPs and Processors

APPLICATions
•
•
•
•
•
•
•
•

The LTC1400 converts OVto 4.096V unipolar inputs from
a single 5V supply and ±2.048V bipolar inputs from ±5V
supplies. Maximum DC specs include ±1 LSB INL, ±1 LSB
DNL and 25ppm/oC drift overtemperature. Guaranteed AC
performance includes 70dB S/(N +D) and 76dB THO at an
input frequency of 100kHz, over temperature.

High Speed Data AcquiSition
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Digital Radio
Spectrum Analysis
Low Power and Battery-Operated Systems
Handheld or Portable Instruments

The 3-wire serial port allows compact and efficient data
transferto awide range of microprocessors, microcontrollers
and DSPs.
D. LTC and l Tare regislered Irademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
Single 5V Supply, 400kHz, 12-Bit Sampling AID Converter

Power Consumption vs Sample Rate
100 .---r-r-r-r---,---,,---,--.

5V
I

Vee

Vss

8

+

MPU
':'

"'T" 10l1F "'T"0.1I1F ANALOG INPUT
~
~
(OV TO 4.096V)

2 AIN

CONY 7

P1.4

lTC1400
3 VREF
ClK
2.42V REFOUT-.-........--~

+

1011F

T_ T_

0.111F

P1.3

':'4'-G~D_ _D---'5
OUT SERIAL

P12
.

DATA LINK
LTCl4000TAOl

0.001 '---'--'--'--'--L...-...JL...-...JL...-...J
0.01 0.1 1 10 100 1k 10k 100k 1M
SAMPLE RATE (Hz)
LTC1400'TA02:

13-86

LTC 1400
~BSOLUTE

mAXimum RATinGS

PACKAGE/ORDER InFORmATiOn

Noles 1, 2)

)upply Voltage (Vee) ................................................. 7V
~egative Supply Voltage (Vss) .................... -6V to GND
iotal Supply Voltage (Vee to Vss)
Bipolar Operation Only ........................................ 12V
~nalog Input Voltage (Note 3)
Unipolar Operation .................. -0.3V to (Vee + 0.3V)
Bipolar Operation ........... (Vss - 0.3V) to (Vee + 0.3V)
)igitallnput Voltage (Note 4)
Unipolar Operation ................................ -0.3V to 12V
Bipolar Operation ......................... (Vss - 0.3V) to 12V
)igital Output Voltage
Unipolar Operation .................. -0.3V to (Vee + 0.3V)
Bipolar Operation ........... (Vss - 0.3V) to (Vee + 0.3V)
lower Dissipation .............................................. 500mW
)peration Temperature Range
LTC1400C ................................................ oaC to 70 aC
LTC14001 ............................................ -40 aCto 85 aC
Itorage Temperature Range ................. -65 aCto 150aC
.ead Temperature (Soldering, 10 sec) .................. 300 aC

'OWER REQUIREmEIlTS
YMBOL

ee

Negative Supply Voltage (Note 6)
Positive Supply Current

is

Negative Supply Current

0

Power Dissipation

55

InALOG InpUT

'"0'"

AIN 2
VREF 3
GNO 4

N8 PACKAGE
HEAD POIP

S8 PACKAGE
HEAD PLASTIC SO

S8 PART MARKING

TJMAX = 150°C, BJA = 130°CIW (N8)
TJMAJ( = 150°C, BJA = 175°C/W (58)

1400
14001

Consult factory for Military grade parts.

CONDITIONS
Unipolar
Bipolar
Bipolar Only
fSAMPlE =400ksps
NAP Mode
SLEEP Mode
fSAMPlE = 400ksps, V5S =-5V
NAP Mode
SLEEP Mode
fSAMPlE =400ksps
NAP Mode
SLEEP Mode

MIN
4.75
4.75
-2.45

•
•
•
•
••
•
•

TYP

15
1.0
5.0
0.3
0.2
1
75

6

•

30

MAX
5.25
5.25
-5.25
30
3.0
20.0
0.6
0.5
5
160
20
125

UNITS
V
V
V
mA
mA
~

mA
mA
~

mW
mW
IlW

(Nole5)

YMBOL PARAMETER

CONDITIONS

IN

Analog Input Range (Note 7)

N

Analog Input Leakage Current

During Conversions (Hold Mode)

IN

Analog Input Capacitance

Between Conversions (Sample Mode)
During Conversions (Hold Mode)

L7~JD~

LTC1400CN8
LTC1400CS8
LTC1400lN8
LTC1400lS8

CONV
6 ClK
5 Dour
7

(Nole 5)

PARAMETER
Positive Supply Voltage (Note 6)

)0

ORDER PART
NUMBER

TOP VIEW

4.75V,.:; Vec":; 5.25V (Unipolar)
4.75V ,.:; Vee":; S.2SV, -S.2SV,.:; Vss ,.:; -2.4SV (Bipolar)

MIN

••
•

TYP

MAX

oto 4.096

V
V

±2.048
±1
45
5

UNITS

~

pF
pF

13-87

iii

LTC 1400
conVERTER CHARACTERISTICS
PARAMETER

With internal reference (Notes 5, B)

CONDITIONS

MIN

•

Resolution (No Missing Codes)
Integral Linearity Error

(Note 10)

Full-Scale Error
Full-Scale Tempco

DynAmiC ACCURACY

IMD

±1

LSB

±1

LSB

±4
±6

LSB
LSB

±15

LSB

±45

ppml"C

MIN

TYP

MAX

UNITS

70

72
70

(Note 5)

SYMBOL PARAMETER
S/(N + D) Signal-to-Noise
Plus Distortion Ratio
THO

UNITS

±10

•

10UT(REFl = 0

MAX

Bits

•
•
•

(Note 9)

Differential Linearity Error
Offset Error

TYP

12

CONDITIONS

•
•
•

100kHz Input Signal
200kHz Input Signal

Total Harmonic Distortion
Up to 5th Harmonic

100kHz Input Signal
200kHz Input Signal

Peak Harmonic or
Spurious Noise

100kHz Input Signal
200kHz Input Signal

Intermodulation Distortion

flNl = 99.3kHz, flN2 = 102.4kHz
flNl = 199.37kHz, flN2 = 202.4kHz

-80
-74

-76

dB
dB

-84
-74

-76

dB
dB

-82
-70

Full Power Bandwidth
Full Linear Bandwidth (S/(N + D) ;:: 68dB)

InTERnAL REFEREnCE CHARACTERISTICS

dB
dB

dB
dB

4

MHz

350

kHz

(Note 5)

PARAMETER

CONDITIONS

MIN

TYP

MAX

VREF Output Voltage

louT = 0

2.400

2.420

2.440

V

VREF Output Tempco

±10

±45

ppml"C

VREF Line Regulation

lOUT = 0
4.75V::; Vee::; 5.25V
-S.2SV::; Vss::; OV

VREF Load Regulation

0::; HOUTI ::; lmA

DIGITAL InpUTS AnD OUTPUTS
SYMBOL PARAMETER
High Level Input Voltage

VIH

VIL
liN
CIN
VOH

Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage

CONDITIONS
Vee = 5.25V
Vee = 4.75V
VIN = OV to Vee
Vee = 4.75V, 10 =-10~
Vee = 4.75V, 10 = -200~

Low Level Output Voltage

Vee = 5.25V, 10 = 160~
Vee = 5.25V, 10 = 1.6mA

loz
Coz

Hi-Z Output Leakage DOUT
Hi-Z Output Capacitance DOUT (Note 7)
Output Source Current
Output Sink Current

VOUT = OV to Vee

13-88

0.01
O.Ot

LSBIV
LSBIV

2

LSB/mA

(Note 5)

VOL

IsouReE
ISINK

•

UNITS

VOUT = 0
VOUT = Vee

•
•
•
•
•

•
•

MIN
2.0

TYP

MAX
0.8

V
V

±10

~

5
4.7

pF

4.0
0.05
0.10

UNITS

0.4
±10
15

V
V
V
V
~

pF

-10

mA

10

mA

LTC 1400
riminG CHARACTERISTICS

(Note 5)

;YMBOL

PARAMETER

CONDITIONS

lAMPLE(MAX)

Maximum Sampling Frequency

(Note 6)

;ONV

Minimum Conversion Time

lea

(Note 7)

;LK

Acquisition Time (Unipolar Mode)
(Bipolar Mode Vss = -5V)
ClK Frequency

NK(NAP)

Time to Wake Up from NAP Mode

(Note 7)

I

Minimum ClK Pulse Width to Return to Active Mode

~

Minimum CONvi to ClKi Setup Time

!

Maximum CONvi After leading ClKi

I

Minimum CONV Pulse Width

;

Time from CLKi to Sample Mode

(Note 11)
(Note 7)

;

Aperture Delay of Sample-and-Hold (Note 7)

Jitter < 50ps

,

Minimum Delay Between Conversion (Unipolar Mode)
(Bipolar Mode Vss = -5V)

!

Delay Time, CLKi to DOUT Valid

CLOAD = 20pF

I

Delay Time, CLKi to DouT Hi-Z

CLOAD = 20pF

10

Time from Previous Data Remain Valid After CLKi

CLOAD = 20pF

he. denotes specifications which apply over the full operating
'mperature range; all other limits and typicals TA = 25°C.
ate 1: Absolute maximum ratings are those values beyond which the life
I a device may be impaired.
ole 2: All voltage values are with respect to GND.
ole 3: When these pin voltages are taken below Vss (ground for unipolar
lode) or above Vee, they will be clamped by internal diodes. This product
In handle input currents greater than 40mA below Vss (ground for
lipolar mode) or above Vee without latch-up.
ate 4: When these pin voltages are taken below Vss (ground for unipolar
lode), they will be clamped by internal diodes. This product can handle
put currents greater than 40mA below Vss (ground for unipolar mode)
ithout latch-up. These pins are not clamped to Vee.
ate 5: Vee = 5V, fSAMPLE = 400kHz, t, = tf = 5ns unless otherwise
lecified.

L7lJD~

MIN

•
•
•
•
•

•
•
•
•
•
•
••
•
•
•

TYP

MAX

UNITS

400

kHz

300
270

J.lS
ns
ns
MHz

2.1
230
200
0.1

6.4
350

14

ns

20

50

ns

40

80

ns

-20

0

ns

20

50

ns

80
45

65

ns
ns

265
235

385
355

ns
ns

40

65

ns

40

80

ns

25

ns

Note 6: Recommended operating conditions.
Note 7: Guaranteed by design, not subject to test.
Note 8: linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 9: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Nole 10: Bipolar offset is the offset voltage measured from -0.5lSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Nole 11: The rising edge of CONV starts a conversion. If CONV returns
low at a bit decision point during the conversion, it can create small errors.
For best performance ensure that CONV returns low either within 120ns
after conversion starts (i.e., before the first bit decision) or after the 14
clock cycle. (Figure 9 Timing Diagram).

13-89

LTC1400
Pin FUnOIOnS
Vee (Pin 1): Positive Supply, 5V. Bypass to GND (10W
tantalum in parallel with O.1W ceramic).
AIN (Pin 2):Analog Input. OVt04.096V (Unipolar), ±2.04BV

(Bipolar).
VREF (Pin 3): 2.42V Reference Output. Bypass to GND

(10W tantalum in parallel with O.1W ceramic).
GND (Pin 4): Ground. GND should be tied directly to an
analog ground plane.
DOUT (Pin 5): The AID conversion result is shifted outfrom
this pin.

ClK (Pin 6): Clock. This clock synchronizes the serial data
transfer. Aminimum ClK pulse of 50ns will cause the ADC
to wake up from NAP or SLEEP mode.
CONV (Pin 7): Conversion Start Signal. This active high
signal starts aconversion on its rising edge. Keeping ClK
low and pulsing CONVtwo/fourtimes will puttheADC into
NAP/SLEEP mode.
Vss (Pin 8): Negative Supply. -5V for bipolar operation.
Bypass to GND with O.1IJF ceramic. Vss should short to
GND for unipolar operation.

FunOlonAL BLOCK DIAGRAm
CSAMPLE
AIN

ZEROING SWITCH

--------(~ I - - -......--
a

000 .. ,001

1J

000 .. ,000

100.. ,001
100.. ,000

1

I

111...111
111...110

LTC1400
VIN Vourt--.......- -...... VREF

11

1

I

1+

I

1

LT1019A-5
-FS/2
GND

Vss
-5V
LTC1400 o f03

Figure 3. Supplying a 5V Reference Voltage to the
LTC1400 with the LT1019A-5

UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT
Figure 4 shows the ideal inpuVoutput characteristics for
LTC1400. The code transitions occur midway between
successive integer LSB values (Le., O.SLSB, 1.SLSB,
2.SLSB, ... FS - 1.SLSB). The output code is naturally
binary with 1LSB = 4.096/4096 = 1mV. Figure Sshows the
inpuVoutput transfer characteristics for the bipolar mode
in two's complement format.
1LSB =~
4096

111...111

= 4,096
4096

111...110
111...101

i!5

a

I

111...100

'-'
>-=>
a.

!;
a

000.. ,011
000 .. ,010
000 .. ,001
000 .. ,000

UNIPOLAR
ZERO

1, J

1

..t

1

r

I

-1 OV 1
LSB LSB
INPUT VOLTAGE (V)

FS/2 -lLSB
LTC11400·F05

Figure 5. LTC1400 Bipolar Transfer Characteristics

Unipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 6a
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the onset
of the op amp driving AIN (Le., A1 in Figure 6b). For zero
offset error, apply O.SmV (Le., O.SLSB) at the input and
adjust the offset trim until the LTC1400 output code
flickers between 0000 0000 0000 and 0000 0000 0001.
For zero full-scale error, apply an analog input of 4.094SV
(FS-1.SLSB or last code transition) atthe input and adjust
RS until the LTC1400 output code flickers between 1111
1111 1110 and 1111 1111 1111.

1

I
OV 1
LSB

FS-1LSB
INPUT VOLTAGE (V)
LTC1400'FD4

Figure 4. LTC1400 Unipolar Transfer Characteristics

FULL-SCALE
ADJUST
L---..>-------7IAGND
ADDITIONAL PINS OMITIED FDR CLARITY
±20LSB TRIM RANGE

LTC1400'FQ6a

Figure 6a. Full-Scale Adjust Circuit

13-92

..L7lJD~

LTC 1400
r:lPPLICATlons InFORmATion
BOARD LAYOUT AND BYPASSING

ANALOG
INPUT -JVI.1'v--<~----,I
lVTO 4.096V

R4
100k

5V

LTC1400

R9

R5

20n ' - -_ _~

~JL~-SCALE
ADJUST
R3
100k

R7

5V

RB

..c:: ~~~SET

....----'\,1M
OOk..........

ADJUST

R6
400n

Figure 6b. LTC1400 Offset and Full-Scale Adjust Circuit

Jipolar Offset and Full-Scale Error Adjustments
3ipolar offset and full-scale errors are adjusted in asimilar
ash ion to the unipolar case. Bipolar offset error adjustnent is achieved by trimming the offset of the op amp
lriving the analog input of the LTC1400 while the input
fOltage is O.SLSB below ground. This is done by applying
In input voltage of -O.SmV (-O.SLSB) to the input in
:igure 6c and adjusting the op amp until the ADC output
:ode flickers between 0000 0000 0000 and 1111 1111
1111. Forfull-scale adjustment, an inputvoltage of 2.046SV
FS -1.SLSBs) is applied to the input and RS is adjusted
mtiitheoutputcodeflickersbetween011111111110and
)111 1111 1111.
R1
10k

INALOG
INPUT ~>I'v-_---l
,2.04BV
R2
10k

R4
100k
R5

Wire-wrap boards are not recommended for high resolution or high speed AID converters. To obtain the best
performance from the LTC1400, a printed circuit board is
required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by GND.
High quality tantalum and ceramic bypass capacitors
should be used at the Vce and VREF pins as shown in the
Typical Application on the first page of this data sheet. For
the bipolar mode, a 0.1 ~ ceramic provides adequate
bypassing for the Vss pin. The capacitors must be located
as close to the pins as possible. The traces connecting the
pins and the bypass capacitors must be kept short and
should be made as wide as possible.
Input signal leads to AIN and signal return leads from GND
(Pin 4) should be kept as short as possible to minimize
noise coupling. In applications where this is not possible,
a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds
between the signal source and ADC appears as an error
voltage in series with the input signal, attention should be
paid to reducing the ground circuit impedance as much as
possible.
Figure 7shows the recommended system ground connections. All analog circuitry grounds should be terminated at
the LTC1400GND pin. Theground return from the LTC1400
DIGITAL SUPPLY
5V

LTC1400

'----~ ~J~L-SCALE
ADJUST
R3
100k

R7
5V RB
100k
20k
......~Nv--+< OFFSET
ADJUST
RS
-5V
200n
lTC1400°F06c

Figure 6c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit

L7lJD~

lTCl4000f07

Figure 7. Power Supply Connection

13-93

LTC1400
APPLICATions InFoRmATion
Pin 4 to the power supply should be low impedance for
noise free operation. Digital circuitry grounds must be
connected to the digital supply common.

power instead of 75mW (for minimum power, the logiC
inputs must be within 500mV of the supply rails). The
wake-up time from the NAP mode to the active mode is
350ns. In the SLEEP mode, the power consumption is
reduced to minimum by cutting off the supply to all
internal circuitry including the reference. Figure 8 shows
the ways to power down lTC1400. The chip can enter the
NAP mode by keeping the ClK signal low and pulsing the
CONV signal twice. For SLEEP mode operation, CONV
signal should be activated four times while ClK is kept
low.

In applications where the ADC data outputs and control
signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the
microprocessor into aWait state during conversion or by
using three-state buffers to isolate the ADC data bus.

The lTC1400 can be returned to active mode easily. This
can be achieved by pulsing the ClK Signal. During the
transition from SLEEP mode to active mode, the VREF
voltage ramp-up time is a function of the loading conditions. With a 1O~ bypass capacitor, the wake-up time
from SLEEP mode is typically 4ms. A REFRDY signal will
be activated once the reference has settled and is ready for
AID conversion. This REFRDY bit is outputto the Dour pin
before the rest ofthe AID converted code.

Power-Down Mode
Upon power-up, the lTC1400 is initialized to the active
state and is ready for conversion. However, the chip can be
easily placed into the NAP or SLEEP mode by exercising
the right combination of ClK and CONV signal. In the NAP
mode all power is off except the internal reference, which
is still active and provides 2.42V output voltage to the
other circuitry. In this mode, the ADC draws only 6mW of
ClK

___________~rl~---------------------------~~--~rl~--------~~---------I 1---

---1 1---

11

11

CONV

NAP

SLEEP

_______---'

-----------------------------~~I
~I~------------~--------

REFRDY

----''-----------------------.

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE DOUT WORD.

Figure 8. NAP Mode and SLEEP Mode Waveforms

13-94

.----

~~I--~----------~~----~!

LTC 1400
IPPLICATlons InFORmATion
'IGITAL INTERFACE
he digital interface requires only three digital lines. ClK
nd CONY are both inputs, and the Dour output provides
le conversion result in serial form.
igure 9 shows the digital timing diagram of the lTC1400
uring the AID conversion. The CONY rising edge starts
le conversion. Once initiated, it can not be restarted until

the conversion is completed.lfthe time from CONY signal
to ClK rising edge is less than t2, the digital output will be
delayed by one clock cycle.
The digital output data is updated on the rising edge of the
ClK line. Dour data should be captured by the receiving
system on the rising ClK edge. Data remains valid for a
minimum time of t10 after the rising ClK edge to allow
capture to occur.

ClK

CONY _ _.....I

INTERNAL ~::::-=--'-iL.-_ _ _ _ _ _ _~~_ _ _ _ _ _ _
S/HSTATUS

.J

f.:-------I

ICONV

--------+1·1

I----------ISAMPLE------------i

LTC14{lO·FQ9

Figure 9. ADC Digital Timing Diagram

ClK

ClK

---r--:\~====-- 90%
DOUT

DOUT

_ _ _ _...Jf-~==-VOl

_ _ _ _~----"o,;===--10%
LTC1400·Fl0

Figure 1D. ClK to DoUT Delay

13-95

LTC 1400
TYPICAL APPLICATion
LTC1400 with Parallel Oulput
5V
5 V - : - 9 - - - - . - - - - - - . . 4 1 -1
.:...jVCC

+

10~F

O.l~F

""'T"-::-

ANALOG INPUT
(OV TO 4.096V)

2 AIN

Vss 8

CONV

10

r-~=--'

12 RCKSRClR QA 15
.J..
.J..
1
2.42V
3
lTC1400
6
aB
REFERENCE - - -......- - -.......----""!VREF
ClKI-"---i---o<
11 SRCK
ac 2
3
OUTPUT
14 74HC595 QD 4
O.l~F
4 GND
OOUT'"'5:....--;------!--+-~SER
QE 5
QF 6
-::13 G
QG 7
QH
-::QH' 9
3-WIRE SERIAL
INTERFACE LINK
""'T"-::-

CONVI-!7_--o
:::;
ll::

1)l

~

z

150

......... .........

100
50

a

Switch Resistance (5V)

Switch Resistance

300

~

/
o

2

/'"

~0.20

'"

~ 0.10

~

a

6

4

VIN2 = VIN3 = NC -

~O.15
a:

r-~

SUPPLY VOLTAGE (V)

f--

:J:

~0.10

~
I

~

0.05

ALL VIN PINS CONNECTED

I

a

3
4
5
INPUT VOLTAGE (V)

1

VINS = VIN1 = 5V
VIN2 = VIN3 = ~

~

............

:J:

0.05

3

..

0.20

a

Switch Resistance (3.3V)

~

~
~
100
JUNCTION TEMPERATURE ('C)

3.0

0.25

_ 2.5

Output Current (5V)
Tp 25'G

TJ = 25'C

z
~

~0.15
II:
:I:

~0.10

~

5.

....
z

w

f--- c-VINS = VIN1 = 3.3

II:
II:
::J

VIN27VIN~

f..-- """"

. I.

t:: 1.5

J

U

tE0

1.0

'"

0.5

~

~

100
JUNCTION TEMPERATURE ('C)

125

o

I

o

3.
OUTPUT VOLTAGE (V)

CURRENTWjJ~25'CI

CURRENT

~~u,","_

""y'"'-"

" "";;~Ii""

ALL VIN PINS = 3.3V

l)N3 = Jc

/

o

-0.4

[t...-V'
0.4

GOUT = 470~F

~~25'b

f

r

COUT = 10~F

7

AL VIN lNS 5V

0.8 1.2 1.6
TIME (ms)

2.0

I

-u,"" ~~'"'"""'"
J~

'-

Vf~
COUT = 10~F

13-114

o

Inrush Current (3.3V)

.J---t
/

LTC1477114780TPC07

J

lTC147T11478°T!"006

Inrush Current (5V)

2
3
4
OUTPUT VOLTAGE (V)

J..

LTC14n/14780Tflt05

Tp25'C

o

l

SUPPLY VOLTAGE (V)

Output Current (3.3V)

o

ALL VIN PINS = 5V

o

VIN2 = VIN3 = NC

LTC1471!14780TPC04

VIN2.=

~

-

V-

a

lJ~

<.>

VIN2 = VIN3 = NC

:J:

~

4

II:
::J

::J

II:

~

o

g
~
a:

(

<.>

0.05

a

ALL VIN PINS
CONNECTED

2.0

<.>

ALL VIN PINS = 3.3V

125

LTC1477114780TPC03

Short-Circuit Current

0.30

~0.20

~~

LTC1477114780TPC02

LTC1477f1478·TPCOl

9:

n

2.4 2.8

LTC1471!1478 0 TPC08

o

-0.4

al

0.4

GOUT = 470~F

0.8 1.2 1.6 2.0
TIME (ms)

2.4 2.8

LTC147711478°TPC09

LTC 1477 /LTC1478

Pin FunOlons
LTC1477

LTC1478

EN (Pin 4): The enable input is a high impendance CMOS
gate with an ESD protection diode to ground and should
not be forced below ground. This input has about 100mV
of built-in hysteresis to ensure clean switching.

AEN, BEN {Pins 4, 12):The enable inputs are high impedance CMOS gates with ESD protection diodes to ground
and should not be forced below ground. These inputs
have about 100mV of built-in hysteresis to ensure clean
switching.

VINS, VIN1 {Pins 3,2):The VINS supply pin must always be
connected to the VIN1 supply pin (see Block Diagram). The
VINS supply pin provides power for the input control logic,
the current limit and thermal shutdown circuitry; plus
provides a sense connection to the input power supply.
The gate ofthe NMOS switch is powered by acharge pump
from the VINS supply pin (see Block Diagram). The VIN1
supply pin provides connection to the drain of 1/2 of the
output power device.
VIN2, VIN3 (Pins 7,6): The VIN2 and VIN3 supply pins are
typically tied to the VINS and VIN1 supply pins for lowest on
resistance; i.e., when all four VIN pins are connected
together the entire power device is connected (see Block
Diagram). Each auxiliary supply pin, VIN2 and VIN3, is
connected to the drain of 1/4 of the power device. The VIN2
and VIN3 pins can be selectively disconnected to reduce
the short-circuit current limit at the expense of higher
RDS(ON)' (See Applications Information section for more
detail.)
VOUT (Pins 1,8): The output pins of the LTC1477 must
always be tied together. The output is protected against
accidental short-circuits to ground by a current-limit circuit which protects the system power supply and load
against damage. A second level of protection is provided
by thermal shutdown circuitry which limits the die temperature to 130°C.

AVINS, AVIN1, BVINS, BVIN1 {Pins 3,2; 11 ,10):The AVINS
or BVINS supply pin must always be connected to the
AVIN1 or BVIN1 supply pin (see Block Diagram). The AVINS
and BVINS supply pins provide power forthe input control
logic, the current limit and thermal shutdown circuitry;
plus provides a sense connection to the input power
supply. The gate of the NMOS switch is powered by a
charge pump from the AVINS and BVINS supply pins (see
Block Diagram). The AVIN1 and BVIN1 supply pins provide
connection to the drain of 1/2 of the output power device.
AVIN2, AVIN3, BVIN2, BVIN3. {Pins 15,14; 7,6):The AVIN2,
AVIN3, BVIN2 and BVIN3 supply pins are typically tied to the
AVINS, AVIN1, BVINS and BVIN1 supply pins for lowest on
resistance; i.e., when all four AVIN, BVIN pins are connected together the entire power device is connected (see
Block Diagram). Each auxiliary supply pin, AVIN2, AVIN3,
BVIN2 and BVIN3, is connected to the drain of approximately 1/4 of the corresponding power device. The AVIN2,
AVIN3, BVIN2 and BVIN3 pins can be selectively disconnected to reduce the short-circuit limit at the expense of
higher RDS(ON)' (See Applications Information section for
more detail.)
AVOUT, BVOUT{Pins1 ,16; 8,9):Theoutputs ofthe LTC1478
are protected against accidental short-circuits to ground
by acurrent-limit circuit which protects the system power
supplies and loads against damage. A second level of
protection is provided by thermal shutdown circuitry
which limits the die temperature to approximately 130°C.

13-115

LTC 1477/LTC1478
OPERATion (LTC1477 or single channel of LTC1478)
Input TTL-CMOS Converter

Switch Protection

The LTC1477 enable input is designed to accommodate a
wide range of 3Vand 5V logic families. The inputthreshold
voltage is approximately 1.4V with 1OOmV of hysteresis.
The input enables the bias generator, the gate charge
pump and the protection circuitry. Therefore, when the
enable input is turned off, the entire circuit is powered
down and the supply current drops below 1~.

Two levels of protection are designed into the power
switch in the LTC1477. The switch is protected against
accidental short-circuits with acurrent limit circuit which
limits the output current to typically 2A when the output is
shorted to ground. The LTC1477 also has thermal shutdown set at approximately 130°C which limits the power
dissipation to safe levels.

Ramped Switch Control

LTC1478 Operation

The LTC1477 gate charge pump includes circuitry which
ramps the NMOS switch on slowly (1 ms typical rise time)
but turns it off much more quickly (typically 20JlS).

The LTC1478 dual protected switch can be thought of as
two independent LTC1477 single protected switches. The
input supply voltages may be from separate power sources.
The ground connection, however, is common to both
channels and must be connected to the same potential.

Bias, Oscillator and Gate Charge Pump
When the switch is enabled, a bias current generator and
high frequency oscillator are turned on. The on-chip
capacitive charge pump generates approximately 12V of
gate drive for the internal low ROS(ON) NMOS switch from
the power supply. No external12V supply is required to
switch the output.

BLOCK DIAGRAm

(LTC1477 or single channel of LTC1478)

GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC

EN

TIL-TO-CMOS
CONVERTER

OSCILLATOR
AND BIAS

CHARGE
PUMP

CURRENT LIMIT
AND THERMAL
SHUTDOWN

' - - - - - + - VOUT
LTC147711478"SDOl

13-116

LTC 1477 /LTC 1478
APPLICATions InFoRmATion
Tailoring IlIMIT and RDS(DN) for load Requirements

Supply Bypassing

The LTC1477 is designed to current limit at approximately
2A during ashort-circuit with all the VIN pins connected to
the input power supply. It is possible however, to reduce
this current by selectively disconnecting two of the four
power supply pins (VIN2 and VIN3). Table 1 lists the effects
of disconnecting these pins on ROS(ON) and short-circuit
current limit

For best results, bypass the supply input pins with asingle
1.01lf capacitor as close as possible to the LTC1477.
Sometimes, much larger capacitors are already available
at the output of the power supply. In this case, it is still
good practice to use aO.11lf capacitor as close as possible
to the LTC1477, especially if the power supply output
capacitor is more than 2" away on the printed circuit board.

Table 1. Effects of Disconnecting VIN2 and VIN3
All VIN PINS
VIN2 AND VIN3
VIN3
CONNECTED DISCONNECTED DISCONNECTED

Output Capacitor

0.070
2A

ROS(ON)

ILiMIT

0.090
1.5A

0.120
0.85A

Note: 5V Operation

Note that there is an inverse relationship between output
current limit and switch resistance. This allows the tailoring of the switch parameter to the expected load current
and system current limit requirements.
A couple of examples are helpful:
1. If a nominal load of 1A was controlled by the switch
configured to current limit at 2A (all VIN pins connected
together), the ROS(ON) would be O.07n and the voltage
drop across the switch would be 70mV. The power
dissipated by the switch would only be 70mW.
2. If a nominal load of O.5A was controlled by the switch
configured to current limit at O.85A (VIN2 and VIN3
disconnected), the ROS(ON) would increase to O.14n.
But the voltage drop would remain at 70mV and the
switch power dissipation would drop to 35mW.

The output pin is designed to ramp on slowly, typically
1ms rise time. Therefore, very large output capacitors can
be driven without producing voltage spikes on the supply
pins (see graphs in Typical Performance Characteristics).
The output pin should have a 11lf capacitor for noise
reduction and smoothing.
Supply and Input Sequencing

The LTC1477 is designed to operate with continuous
power (quiescent current drops to < 1j.tA when disabled).
If the power must be turned off, for example to enter a
system "sleep" mode, the enable input must be turned off
100!!S before the input supply is turned off to ensure that
the gate of the NMOS switch is completely discharged
before power is removed. However, the input control and
power can be applied simultaneously during power up.

TYPICAL APPLICATiOnS
1. SA Protected Switch

2A Protected Switch
2.7V TO 5.5V

-Ti>-;::====::::;:+----.- Ise

=

2A

2.7VTO

5.5V~~

__- - - - - _ _ .

.------.....-t--...-Ise = 1.SA

III

LTC1477

ON/OFF

t..:E,;;".N_ _ _G:;;,;N:..JO

ON/OFF

VINS

VIN3

EN

GNO

'-------'

13-117

LTC1477/LTC1478
TYPICAL APPLICATions
O.85A Protected Switch

2A Protected Switch Driving a Large Capacitive Load

2.7V TO 5.5V-.....--; . - - - - - - - - -.....~,....ISC = 0.85A

2.7VTO

5.5V-,-,-;::======::;+_+-

VOUT

LTC1477

ON/OFF

VINS

VIN3

EN

GND

ON/OFF
":"

EN

GND

LTC1477/1418-TA05

":'"

Adding Short-Circuit Protection to an LT1301 Step-Up Switching Regulator (O.01!lA Standby Current)
L1'
1Ol1H

MBRS130LT3
12V

5V
VOUT

SW

VIN

VOUT

SEL
VIN1

VIN2
LT1301

LTC1477

ON/OFF

SENSE

VINS

VIN3

EN

GNO

NC

T--

O1I1F
.

"::"

"::"

"::"

'COILCRAFT D01608-103

+

SHDN

r-

4711F
TANT
16V

"::"

5V to 3.3V Selector Switch with Slope Control and D_D1!lA Standby Current
5V~""'-~---------,

0.1 11F

J

'5V ON/OFF

AVOUT

AVOUT

AVIN1

AVIN2

AVINS

AVIN3

1k

+

1OOl1F

110V
"::"

GND

AEN
LTC1478
GND

3.3V

5V12A OR
3.3V12A

"::"

BEN

BVIN3

BVINS

BVIN2

BVIN1

BVOUT

BVOUT

'3.3VON/OFF _ _ _ _ _ _ _ _ _ _ _- '
LTC14771147S0TAOS

'ALLOW AT LEAST 100ms BETWEEN 5V AND 3.3V SWITCHING FOR DISCHARGE OF 100l1F OUTPUT CAPACITOR

13-118

LTC14771147S·TAG6

LTC 1477 /LTC1478
RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC1153

Electronic Circuit Breaker

LTC1154

Single High-Side Driver

MOSFET Driver with Adjustable Reset Time
MDSFET Driver with Switch Status Output

LTC1155

Dual High-Side Driver

Dual MDSFET Driver with Protection

LTC1470

5V and 3.3V Vcc Switch

SafeSlot™ Protected Switch in a-Lead SO

LTC1471

Dual 5V and 3.3V Vcc Switch

Dual Version of LTC1470 in 16-Lead SO

LTC1472

PCMCIA Vcc and VPP Switches

Complete Single Channel SafeSlot Protection

SafeSlot IS atrademark of Linear Technology Corporation.

13-119

£.7LIn

uU\JU U UlFUts UllLSLSl5lFU87%)

LTl510
ABSOLUTE mAXimum RATinGS
Supply Voltage (VMAX) ............................................ 27V
Switch Voltage with Respect to GND ...................... -3V
Boost Pin Voltage with Respect to Vee ................... 30V
Boost Pin Voltage with Respect to GND ................. -5V
Ve, PROG, OVP Pin Voltage ...................................... av
ISAT (Average) ........................................................ 1.5A

Switch Current (Peak) ............................................... 2A
Operating Junction
Temperature Range ............................... O°C to 125°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

PACKAGE/ORDER InFORmATiOn
TOP VIEW

ORDER PART
NUMBER
TOP VIEW

LT1510csa

S8 PACKAGE
8-LEAD PLASTIC SO

ORDER PART
NUMBER

SW
BOOST

LT1510CN
LT1510CS

sa PART MARKING

TJMAX = 125'C. 9JA = 125'C/W

1510

NPACKAGE
16-LEAD POI P
SPACKAGE'
16-LEAD PLASTIC SO
TJMAX = 125'C. 9JA = 75'C/W (N)
TJMAX = 125'C. 9JA = 50'C/W (S)'

, FOUR CORNER PINS ARE FUSED
TO INTERNAL DIE ATTACH
PADDLE FOR HEAT SINKING.
CONNECTTHESE FOUR PINS TO
EXPANDED PC LANDS FOR
PROPER HEAT SINKING.

Consult factory for Industrial and Military grade parts.

ELEORICAL CHARACTERISTICS
Vee =16V, VOAT =BV, VMAX (maximum operating Vee) =25V, no load on any outputs, unless otherwise noted.
PARAMETER

ICONDITIONS

MIN

I UNITS

TYP

MAX

2.90
2.91

3.9
4.1

mA
mA

1.0
1.5
100

1.050
1.575
110

A
A
mA

Overall
Supply Current

VPROG =2.7V, Vcc $ 20V
VPROG =2.7V, 20V < Vcc $ VMAX

DC Battery Current, IBAT (Note 1)

8V $ Vcc $ VMAX, OV:;:; VBAT:;:; 20V
RpROG =4.93k
RpROG =3.28k (Note 4)
RpROG =49.3k

Vcc Undervoltage Lockout (Switch OFF) Threshold
Reverse Current from Battery (When Vcc Is Not
Connected, Vsw Is Floating)

VBAT $ 20V
20V < VBAT $ VMAX

Boost Pin Current

Vee - VBOOST $ 20V
20V < Vee - VBOOST :;:; VMAX
2V $ VBOOST - Vcc $ 8V (Switch ON)
8V < VBOOST - Vcc $ 25V (Switch ON)

•
•
••
•
•
•
•
•
••
•

0.950
1.425
90

6

7

8

V

3
3

6

~
~

0.10
0.25

10
20

8

6

9

8

12

~
~
mA
mA

13-121

LTl510
ELECTRICAL CHARAOERISTICS
Vee = 16V, VBAT = BV, VMAX (maximum operating Vee) = 25V, no load on any outputs, unless otherwise noted.
PARAMETER

I CONDITIONS

MIN

TYP

MAX

UNITS

0.3

0.42
1.50

Q
Q

Switch
Switch ON Resistance

8V::; Vee::; VMAX
Isw = 1.5A, VBOOST - Vsw 2: 2V (Note 4)
Isw = lA, VBOOST - Vsw < 2V

AIBOOST/Alsw During Switch ON

VBOOST= 24V

Switch OFF Leakage Current

Vsw = OV, Vee::; 20V
20V < Vee::; VMAX

Maximum VBAT with Switch ON
Minimum IpROG for Switch ON
Minimum IpROG for Switch OFF at VPROG ::; IV
Current Sense Amplifier Inputs (SENSE, BAT)

•
•
••
•
•
•

25

35

mAlA

2
4

100
200

IJA
IJA
V

Vee- 2
2

4

1

1.2

7

IJA
mA

0.12

Q

0.2

0.25

Q

-100

-200

IJA
V

Vee- 2

V

0.08

Sense Resistance (RS1)
Total Resistance from SENSE to BAT (Note 3)

•

Input Bias Current

•
•

Input Common-Mode Low
Input Common-Mode High
Reference

-0.25

Reference Voltage (Note 1) S8 Package

RpROG = 4.93k, Measured at PROG Pin

2.430

2.465

2.495

V

Reference Voltage (Note 2) N16, S16 Packages

RpROG = 3.28k, Measured at OVP with
VA Supplying IpROG and Switch OFF

2.453

2.465

2.477

V

Reference Voltage Tolerance

All Conditions of Vee, Temperature

2.489

V

Oscillator

•

Switching Frequency
Switching Frequency Tolerance

All Conditions of Vee, Temperature

•

Maximum Duty Cycle
Current Amplifier (CA2)
Transconductance

Ve = IV, Ivc = ±11JA

Voltage Amplifier (VA)
Transconductance (Note 2)

Output Currrent from 1OOIJA to 5001JA

Output Source Current

VPROG = 2.5V, Vovp = 2.5V

OVP Input Bias Current

At 0.75mA VA Output Current

13-122

200

210

kHz

180

200

220

kHz

85

93

150

250

••

Vc 2: 0.45V
Ve < 0.45V

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Tested with Test Circuit 1.

190

•

Maximum Vc for Switch OFF
Ivc Current (Out of Pin)

•

2.441

0.4

•
•

0.6

1.1
50

Note 2: Tested with Test Circuit 2.
Note 3: Sense resistor RS1 and package bond wires.
Note 4: Applies to 16-pin only.

%
400

IJITlho

0.7

V

42
3

IJA
mA

1

mho

3

mA

150

nA

LTl510
TYPICAL PERFORmAnCE CHARAOERISTICS
Thermally Limited Maximum
Charging Current, a-Pin SOIC

Thermally Limited Maximum
Charging Current, 16-Pin SOIC

1.3 ,--,----,----,-----,----,
(9JA=125'CIW)
g
TAMAX=60'C
,.. 1.1 TJMAX=125'C

15

'"'"
~
'"

0.9

u

0.7

::>

!

i--+----t-----+---::I_=-J
i--+----f-,,£---+---t-----j

1.5

,..g
15

a'"'"
'"c:;;
'"
:z:
u
OJ

.
.

4VBA~ER(

1.3 r-- 8V BATIERY

V

12VBATIERY

Efficiency of Figure 2 Circuit
100

/

V

96
94
./

1.1
16V BATIERY

V

x

~ 0.5

90

~

88

(9JA=50'CIW)
TAMAX=60'C
TJMAX=125'C

0.7

0.5

92

15
i5

0.9

::;;

0.3 '----'----'---'----'------'
o
10
15
20
25
INPUT VOLTAGE (V)

~

>u

::;;
::>
::;;

::;;
::>
::;;

o

Vee l= 15V I
VBAP 8.4V

98

~

I"'--..

/
86
II
84

..........
........

82

10
15
INPUT VOLTAGE (V)

20

80

25

0.1

0.3

0.5

0.7 0.9
IBAT(A)

1.1

1.3

1.5

1510001

Switching Frequency vs
Temperature

Icc YS Duty Cycle

lee YS Vee
7.0

210
Vee = 16V

o'c~

-

~5'C

----- --- --

~ -m:c

~200

-

~

15

I-

r-

,....,V

10

20

po

::>

8

,-. / '

IE 190

30 40 50 60
DUTY CYCLE ('!o)

70

80

VREF Line Regulation

~~ V
12~

195

..-

5.0

180
-20

0

20

4.5

40 60 80 100 120 140
TEMPERATURE ('C)

IYA YS L1VOVP (Voltage

Amplifier)

o

10

15
Vee (V)

20

25

30

Maximum Duty Cycle

0.003

98

0.002
0.001

ALL TEMPE::~

..V

-0.001

97

-

96
w

V

10

15
Vee (V)

20

25

30
1510602

o t...,:: ~

o

~ I-

rr

-./

o

-

~ 95

-0.002
-0.003

O'C

6.5

185

o
o

-

J.

MAXIMUM DUTY CYCLE
205

",

~

VV
l-

-r

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IVA (mA)

--'
u
>u

~

::>

'"

94

..........

93
92

......

91
90

o

20

40
60
80 100
TEMPERATURE ('C)

120

140

1510G09

13-123

LT1510
TYPICAL PERFORmAnCE CHARAOERISTICS
Vc Pin Characteristic

Switch Current vs Boost Current
vs Boost Voltage

PROG Pin Characteristic

-1.20
-1.08
-0.96

50

i\.

-0.84
-0.72

,
~
\25 bi

,

o

'/

! -0.60
3- 0.48

L

/~5°C_

,'.

-0.24

J

o

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Vc(V)

-S

o

a;;
a;;

25

f-

20

0
0

15

'"

'(
0.12

10

o

2
VPROG (V)

1 _1_

28V ~
18V-k;


<.:>

~

-0.36

V~e =1sv

45

&~

I!!!!!! ~ P"
o

Ie! p-

~

~

I--

~V

0.2 0.4 O.S 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SWITCH CURRENT (A)
1510G01

BLOCK DIAGRAm
r----------------------------------------------------- --------------.
200kHz
OSCILLATOR

I

:

JLJLJL

SHUTDOWN

I

Vsw

Vee

BOOST

Vee-.....--I

~------------~R

~----------------------__IR

+

SW

-=-1.5V

T
VBAT

SLOPE COMPENSATION

GNDD
SENSE

BAT

R1
1k

R3

OVP
I

VREF
2.4S5V

Ve

:
I

SOk

I
I

VREF

I
":'
I
IL_________________________________________ _

I
I

_______________________ J I

PROG

CHARGING CURRENT IBAT
= (lpROG)(2000)

=(2.465V) (2000)
RpROG

13-124

I
I

I
I

LTl510
OPERATion
The LT151 0 is a current mode PWM step-down (buck)
switcher. The battery DC charging current is programmed
by a resistor RpROG (or a DAC output current) atthe PROG
pin (see Block Diagram). Amplifier CA1 converts the
charging current through RS1 to a much lower current
IpROG (500/lA'A) fed into the PROG pin. Amplifier CA2
compares the output of CA1with the programmed current
and drives the PWM loop to force them to be equal. High
DC accuracy is achieved with averaging capacitor CPROG.
Note that IpROG has both AC and DC components. IpROG
goes through R1 and generates a ramp signal that is fed to
the PWM control comparator C1 through buffer B1 and

level shift resistors R2 and R3, forming the current mode
inner loop. The Boost pin drives the switch NPN Qsw into
saturation and reduces power loss. For batteries like
lithium-ion that require both constant-current and constant-voltage charging, the 0.5%, 2.465V reference and
the amplifier VA reduce the charging current when battery
voltage reaches the preset level. For NiMH and NiCd, VA
can be used for overvoltage protection. When input voltage is not present, the charger goes into low current (3~
typically) sleep mode as input drops down to 0.7V below
battery voltage. To shut down the charger, simply pull the
Vc pin low with a transistor.

APPLICATions InFORmATion
Input and Output Capacitors
The input capacitor is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. Worst-case RMS ripple current will be equal to one half of output charging current.
Actual capacitance value is not important. Solid tantalum
capacitors such as the AVX TPS and Sprague 5930 series
have high ripple current rating in a relatively small surface
mount package, but caution must be used when tantalum
capacitors are used for input bypass. High input surge
currents can be created when the adapter is hot-plugged
to the charger and solid tantalum capacitors have aknown
failure mechanism when subjected to very high turn on
surge currents. Highest possible voltage rating on the
capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity
ceramic (5!-iF to 10!-iF) from Tokin, et aI., and the old
standby, aluminum electrolytic, which will require more
microfarads to achieve adequate ripple rating.
The output capacitor is also assumed to absorb all output
switching ripple, which has a worst-case RMS value of
approximately (1 Oe- 6)/(inductance L) or 0.33A for a30f,lH
inductor. EMI considerations usually make it desirable to

.L7lJ!1~

minimize ripple current in the battery leads, and beads or
inductors may be added to increase battery impedance at
the 200kHz switching frequency. Output switching ripple
will then split between the battery and the output capacitor
depending on the ESR of the output capacitor and the
battery impedance.

Thermal Calculations
If the LT151 0 is used for charging currents above O.4A, a
thermal calculation should be done to ensure that junction
temperature will not exceed 125°C. Power dissipation in
the IC is caused by bias and driver current, switch resistance, switch transition losses and the current sense
resistor. The following equations show that maximum
practical charging current for the B-pin SO package (125°
C/W thermal resistance) is about O.BA for an B.4V battery
and 1.1 A for a 4.2V battery. This assumes a 60°C maximum ambient temperature. The 16-pin SO, with athermal
resistance of 50°C/W, can provide a full 1.5A charging
current in many situations. The 16-pin POI Pfalls between
these extremes. Graphs are shown in the Typical Performance Characteristics section.

13-125

lEI

LT1510

TEST CIRCUITS
Test Circuil1
LT1510
-IBAT

1
1
1

1
1

~~~-------------------:

1510TCOl

Tesl Circuil2
LT1510

1

1
1

1
1
______________________
PROG
VREF:1

10k
10k

13-126

LT1510
APPLICATions InFoRmATion
PBIAS = (3.5mA)(VIN) + 1.5mA(VBAT)
+ (VBATt [7.5mA+(0.012)(I BAT)]
VIN

t

For a 2-level charger, R1 and R2 are found from;

R
_ (I BAT)(VBAT
DRIVER - 50(VIN)
Psw =

(IBAT)2(~W)(VBAT) + (tol)(VIN)(IBAT)(f)
IN

PSENSE = (0.180)(IBAT

t

Rsw = Switch ON resistance"" 0.350
tal =Effective switch overlap time"" 1Ons
f =200kHz
Example: VIN =15V, VBAT =8.4V, IBAT =1.2A;
PBIAS = (3.5mA)(15)+ 1.5mA(8.4)
+

(8~~2 [7.5mA+(0.012)(1.2)]=0.17W

PDRIVER

Psw =

(1.2)(8.4)2
( ) =0.11W
5015

(1.2)2(~.:5)( 8.4) + 1oe- (15)(1.2)(200kHZ)
9

= 0.28 + 0.04 = 0.32W
PSENSE =

(2000)(2.465)
ICHRG = -"--~'---~
RpROG
ICHRG =Battery charging current
RpROG = Total resistance from PROG pin to ground

(0.18)(1.2t =0.26W

Total Power in the IC is:
0.17 + 0.11 + 0.32+ 0.26 = 0.86W

R1 = (2.465)(2000)
ILOW

R2 = (2.465)(2000)
IHI-ILOW

All battery chargers with fast-charge rates require some
means to detect full charge state in the battery to terminate
the high charging current. NiCd batteries are typically
charged at high current until temperature rise or battery
voltage decrease is detected as an indication of near full
charge. The charging current is then reduced to a much
lower value and maintained as a constant trickle charge.
An intermediate "top off" current may be used for a fixed
time period to reduce 100% charge time.
NiMH batteries are similar in chemistry to NiCd but have
two differences related to charging. First, the inflection
characteristic in battery voltage as full charge is approached is not nearly as pronounced. This makes it more
difficult to use dV/dt as an indicator of full charge, and
change of temperature is more often used with atemperature sensor in the battery pack. Secondly, constant trickle
charge may not be recommended. Instead, a moderate
level of current is used on a pulse basis ("" 1%to 5% duty
cycle) with the time-averaged value substituting for a
constant low trickle.
When a microprocessor DAC output is used to control
charging current, it must be capable of sinking current
at a compliance up to 2.5V if connected directly to the
PROG pin.
Lithium-Ion Charging

Nickel-Cadmium and Nickel-Metal-Hydride Charging

The circuit in Figure 1 on the first page of this data sheet
uses the 8-pin LT151 0 to charge NiCd or NiMH batteries
up to 12V with charging currents of 0.5A when 01 is on
and 50mA when 01 is off. The basic formula for charging
current is:

The circuit in Figure 2 uses the 16-pin LT1510 to charge
lithium-ion batteries at a constant 1.3A until battery voltage reaches alimit set by R3 and R4. The charger will then
automatically go into a constant-voltage mode with current decreasing to zero overtime as the battery reaches full
charge. This is the normal regimen for lithium-ion charg-

13-127

lEI

LTl510
APPLICATions InFoRmATion
ing, with the charger holding the battery at "float" voltage
indefinitely. In this case no external sensing offull charge
is needed.
Current through the R3/R4 divider is set at acompromise
value of 25J.IA to minimize battery drain when the charger
is off and to avoid large errors duetothe 50nA bias current
ofthe OVP pin. Q3 can be added if it is desired to eliminate
even this low current drain. A 47k resistor from adapter
output to ground should be added if Q3 is used to ensure
that the gate is pulled to ground.
With divider current set at 25J.IA, R4 =2.465/25J.IA =100k
and,
R3- (R4)(VSAT-2.465) _ 100k(8.4-2.465)
- 2.465 + R4( 0.05J,!A) - 2.465 + 1OOk(0.05J,!A)
=

240k

Lithium-ion batteries typically require float voltage accuracy of 1%to 2%. Accuracy of the LT151 0 OVP voltage is
±0.5% at 25°C and ±1 %overfull temperature. This leads
to the possibility that very accurate (0.1 %) resistors might

be needed for R3 and R4. Actually, the temperature of the
LT1510 will rarely exceed 50°C in float mode because
charging currents have tapered off to alow level, so 0.25%
resistors will normally provide the required level of overall
accuracy.
Some battery manufacturers recommend termination of
constant-voltage float mode after charging current has
dropped below aspecified level (typically 50mA to 1OOmA)
and afurther timeout period of 30 minutes to 90 minutes
has elapsed. This may extend the life of the battery, so
check with manufacturers for details. The circuit in Figure
3 will detect when charging current has dropped below
75mA. This logic signal is used to initiate atimeout period,
after which the LT1510 can be shut down by pulling the Vc
pin low with an open collector or drain. Some external
means must be used to detect the need for additional
charging if needed, or the charger may be turned on
periodically to complete a short float-voltage cycle.
Current trip level is determined by the battery voltage, R1
through R3, and the internal LT1510 sense resistor
(:= 0.18(2 pin-to-pin). D2 generates hysteresis in the trip
level to avoid multiple comparator transitions.

BAT

yt---H

ADAPTER
OUTPUT

O.lBO

INTERNAL
SENSE
RESISTOR

3.3V OR 5V
R4
470k

LT151 0

GND
R2
D2
560k 1N414B
R3
430k

•

R1(VBAT)
TRIP CURRENT = (R2 + R3)(0.lBO)

Figure 3. Current Comparator for Initialing Float Timeout

13-128

LT1510
TYPICAL APPLICATion
Adjustable Voltage Regulator with Precision Adjustable Current Limit

O.22flF

LT15l0

1N58l9
SW

VCC2

1-.....----:-+.....- - - ~~~ TO 25V

-::r::- lOOflF

VCC1
BOOST

PROG

GND

RpROG

POT
lOOk

Vc

4.93k

OVP
SENSE

-=-

BAT 1-.....- -.....- - - VOUT
2.5VT015V
CURRENT LIMIT LEVEL
50mA TO lA

L -_ _ _..J

CURRENT LIMIT LEVEL =(2R.465V)(2000)

lk

PROG

RELATED PARTS
PART NUMBER

DESCRIPTION

COMMENTS

LTC®1325

Microprocessor-Controlled Battery Management
System

Can Charge, Discharge and Gas Gauge NiCd, NiMH and Pb-Acid
Batteries with Software Charging Profiles

LT1372/LT1377

500kHz/1 MHz Step-Up Switching Regulators

High Frequency, Small Inductor, High Efficiency Switchers, 1.5A Switch

LT1373

250kHz Step-Up Switching Regulator

High Efficiency, Low Quiescent Current, 1.5A Switch

LT1376

500kHz Step-Down Switching Regulator

High Frequency, Small Inductor, High Efficiency Switcher, 1.5A Switch

LT1512

SEPIC Battery Charger

VIN Can Be Higher or Lower Than Battery Voltage

lEI
13-129

£7Lin

UU~U

U ULr;llS

lnlLSlSLSLr;l~LS

Final Electrical Specifications

LT1512

TECHNOLO~G~~~----S-EP-I-C-C-o-n-s-ta-n-t--C-u-rr-e-n-t/

Constant-Voltage
Battery Charger
May 1995

FEATURES

DESCRIPTiOn

• Charger Input Voltage May Be Higher or
Lower Than Battery Voltage
• Charges Any Number of Cells Up to 20V
• 1% Voltage Feedback Accuracy for Lithium Batteries
• 100mV Current Sense Voltage for High Efficiency
• Battery Can Be Grounded Directly
• 500kHz Switching Frequency Minimizes
Inductor Size
• Charging Current Easily Programmable or Shut Down

The LT®1512 is a500kHz current mode switching regulator specially configured to create a constant-current,
constant-voltage battery charger. In addition to the usual
voltage feedback node, it has a current sense feedback
circuitfor accurately controlling output current of aflyback
or SEPIC topology charger. These topologies allow the
current sense circuitto be ground referred and completely
separated from the battery itself, simplifying battery switching and eliminating ground loop errors. In addition, these
topologies allow charging even when the input voltage is
lower than the battery voltage.

APPLICATions
•
•
•
•

Battery Charging of NiCd, NiMH or Lithium Cells
Precision Current Limited Power Supply
Constant-Voltage, Constant-Current Supply
Transducer Excitation

Maximum switch current on the LT1512 is 1.5A. This
allows battery charging currents up to 0.75A. Overall size
of the charger circuit is typically less than 0.7 in 2, and all
components can be low profile surface mount. Accuracy
of 1% in constant-voltage mode is perfect for lithium
battery applications. Charging current can be easily programmed for NiCd or NiMH batteries. A3A version of the
LT1512 will be available in the near future.
D; LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATiOn
SEPIC Charger with O.5A Output Current

Maximum Charging Current
1.0 r - - - r - - - - , - - - r - - = - r - - ,

L1A"
WALL
ADAPTER-_---_,.....;rrlr"Y"\.....,
INPUT + C3

T~~vF

OFFS ON

0.8

g

AN~i~~
SHUTDOWN

f----+---7£.j--,--'-r'-------l

0.6 1---+-7F---

!isa:
+

C1

~~~F

aa:

0.4

1---+--+--+---+--1

0.2

INDUCTOR = 33~H
ACTUAL PROGRAMMED CHARGING
CURRENT WILL BE INDEPENDENT OF
INPUT VOLTAGE AND BATTERY VOLTAGE
IF IT DOES NOT EXCEED VALUES SHOWN

oL--L_~_L-~_~

o

13-130

10
15
INPUT VOLTAGE (V)

20

25

LT1512
RBSOLUTE mRXlmum RRTlnGS

PRCKRGE/ORDER InFORmATion

Supply Voltage ....................................................... 30V
Switch Voltage.... ... ...... ..... .......... ... ..... ........ ............ 35V
SIS Pin Voltage ....................................................... 30V
VFB Pin Voltage (Transient, 10ms) ........................ ±10V
VFB Pin Current .................................................... 10mA
IFB Pin Voltage (Transient, 10ms) ......................... ±10V
Operating Junction Temperature Range
Operating .............................................. O°C to 125°C
Short Circuit ......................................... O°C to 150°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

ORDER PART
NUMBER

TOP VIEW

"o'~

VFB 2

6 GND S

SIS 4

5 VIN

N8 PACKAGE
HEAD PDlP

LT1512CN8
LT1512CS8

7 GND

IFB 3

S8 PACKAGE
HEAD PLASTIC SO

S8 PART MARKING

TJMAX = 125'C, 8JA = 130'C/W (N8)
TJMAX = 125'C, 8JA = 120'CI W(S8)

1512

Consult factory for Industrial and Military grade parts.

ELECTRICRL CHARRCTERISTICS
VIN = SV, Vc = O.6V, VFB = VREF, IFB =OV, Vsw and SIS pins open, unless otherwise noted.
SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VREF

VFB Reference Voltage

Measured at VFB Pin
Vc = 0.8V

1.233
1.228

1.245
1.245

1.257
1.262

V
V

VFB Input Current

VFB = VREF

250

550
600

nA
nA

VFB Reference Voltage Line Regulation

2.7V ~ VIN ~ 25V, Vc = 0.8V

0.01

0.03

IFB Reference Voltage

Measured at IFB Pin
VFB =OV, Vc = 0.8V

%/V
mV
mV

IFB Input Current
IFB Reference Voltage Line Regulation

VIFB = VIREF
2.7V ~ VIN ~ 25V, Vc = 0.8V

Error Amplifier Transconductance

dlc = ±25f.IA

IREF

gm

Error Amplifier Source Current

VFB = VREF -150mV, Vc = 1.5V

Error Amplifier Sink Current

VFB = VREF + 150mV, Vc = 1.5V
High Clamp, VFB = 1V
Low Clamp, VFB = 1.5V

Error Amplifier Clamp Voltage
Av
f

•
•
•
•
•
•
•
•
•

-100
-100
-20
1100
700
120
1.70
0.25

Error Amplifier Voltage Gain

0.01

0.05

f.IA
%N

1500

1900
2300

iJITlho
iJITlho

200

350

f.IA

1400

2400

1.95
0.40

2.30
0.52

f.IA
V
V

500

VIV

Vc Pin Threshold

Duty Cycle = 0%

0.8

1

1.25

V

Switching Frequency

2.7V ~ VIN ~ 25V

460
440

500
500

540
560

kHz
kHz

260

ns

0.5

0.8

n

1.9
1.7

2.4
2.2

A
A

15

25

mAlA

Maximum Switch Duty Cycle
Switch Current Limit Blanking Time
BV

Output Switch Breakdown Voltage

2.7V ~ VIN ~ 25V

VSAT

Output Switch "On" Resistance

ILiM

Switch Current Limit

Isw= 1A
Duty Cycle = 50%
Duty Cycle = 80% (Note 1)

diiN
dlsw

Supply Current Increase During Switch On Time

•
•
•
•
•
•

90

95
130

35
1.5
1.3

%

47

V

13-131

LT1512
ELECTRICAL CHARACTERISTICS
VIN = 5V, Vc = O.6V, VFB = VREF, IFB =OV, Vsw and SIS pins open, unless otherwise noted.
SYMBOL

PARAMETER

CONOITIONS

MIN

Control Voltage to Switch Current
Transconductance
Supply Current

2.7V ~ VIN ~ 25V

Shutdown Supply Current

2.7V ~ VIN ~ 25V, VS/S ~ 0.6V

Shutdown Threshold

2.7V ~ VIN ~ 25V

Shutdown Delay

SIS Pin Input Current
Synchronization Frequency Range
The. denotes specifications which apply over the full operating
temperature range.

MAX

OV ~ VS/S ~ 5V

•
•
•
•
•
•
•

2.4

2.7

V

4
12

5.5

rnA

30

!lA

0.6

1.3

2

V

5

12

25

lIS

-10

12

!lA

600

800

kHz

Nole 1: For duty cycles (DC) between 50% and 90%, minimum
guaranteed switch current is given by ILiM = 0.667 (2.75 - DC).

BLOCK DIAGRAm

SIS

5k

VfB----i

GND SENSE

13-132

UNITS

AlV

2

Minimum Input Voltage
10

TYP

0.08n

GND

LT1512·BD

LT1512
OPERATion
The LT1512 is a current mode switcher. This means that
switch duty cycle is directly controlled by switch current
rather than by output voltage or current. Referring to the
Block Diagram, the switch is turned "on" atthe start of each
oscillator cycle. It is turned "off" when switch current
reaches a predetermined level. Control of output voltage
and current is obtained by using the output of a dual
feedback voltage sensing error amplifier to set switch
current trip level. This technique has the advantage of
simplified loop frequency compensation. A low dropout
internal regulator provides a 2.3V supply for all internal
circuitry on the LT1512. This low dropout design allows
input voltage to vary from 2.7V to 25V. A500kHz oscillator
is the basic clock for all internal timing. It turns "on" the
output switch via the logic and driver circuitry. Special
adaptive anti-sat circuitry detects onset of satu ration in the
power switch and adjusts driver current instantaneously to
limit switch saturation. This minimizes driver dissipation
and provides very rapid turn-off of the switch.

A unique error amplifier design has two inverting inputs
which allow for sensing both output voltage and current. A
1.245V bandgap reference biases the non inverting input.
Thefirst inverting input ofthe error amplifier is brought out
for positive output voltage sensing. The second inverting
input is driven by a "current" amplifier which is sensing
output current via an external current sense resistor. The
current amplifier is set to a fixed gain of ",-12 which
provides a -1 OOmV current limit sense voltage.
The error signal developed at the amplifier output is
brought out externally and is used for frequency compensation. During normal regulator operation this pin sits at a
voltage between 1V (low output current) and 1.9V (high
output current). Switch duty cycle goes to zero ifthe Vc pin
is pulled below the Vc pin threshold, placing the LT1512 in
an idle mode.

APPLICATions InFORmATion
The LT1512 is an IC battery charger chip specifically optimized to use the SEPIC converter topology. A complete
charger schematic is shown in the Typical Application. The
SEPIC (Single-Ended Primary Inductance Converter) topology has llnique advantages for battery charging. It will
operate with input voltages above or below the battery
Ifoltage, has no path for battery discharge when turned off,
and eliminates the snubber losses of fly back designs. It also
has a current sense point that is ground referred and need
not be connected directly to the battery. The two inductors
:;hown are actually just two identical windings on one
inductor core, although two separate inductors can be used.
~ current sense voltage of -100mV is generated with
respectto ground across R3. This sets maximum charging
~urrentto 0.5Awhen the battery is belowfloatvoltage (lMAX
= 100mV/R3). The average current through R3 is always
dentical to the current delivered to the battery. R4 and C4
'ilter the current signal to deliver a smooth feedback to the
IFB pin. R1 and R2 form adivider for battery voltage sensing
md set the battery float voltage. The suggested value for R2
s 12.4k. R1 is calculated from:

.L7lJlJ~

R1 =

VOUT - 1.245
1.245 + (3 x 10-7)
R2
VOUT = battery float voltage
Maximum input voltage for this circuit is partly determined
by battery voltage. A SEPIC converter has an off-state
switch voltage equal to input voltage plus output voltage.
The LT1512 has a maximum input voltage of 30V and a
maximum switch voltage of 35V, so this limits maximum
input voltage to 30V, or 35V - VBATIERY, whichever is less.
The dual function SIS pin provides easy shutdown and
synchronization. It is logiC level compatible and can be
pulled high or left floating for normal operation. A logic low
on the SIS pin activates shutdown, reducing input supply
currentto 12IJA. To synchronize switching, drive the SIS pin ~
between 600kHz and 800kHz.
...

More Information
For further LT1512 characteristics and applications information, please consultthe LT1372 data sheet. Exceptforthe
error amplifier circuitry, the LT1512 is similarto the LT1372 .

13-133

,-11
,,'"11neJ\Q
~,. TECHNOLOG~fY~-4--c-h-a-n-n-e-I,-3-V-M-ic-r-o-L~-~_~_!-~
""ln1lSlbUWAJUlRJ~ln1l1

11

Sampling 12-Bit Serial
I/O A/D Converter
June 1995

FEATURES

DESCRIPTiOn

•
•
•
•
•
•
•
•
•
•
•

The LTC®1522 is a 4-channel, 3V micropower, 12-bit
sampling AID converter. Whenever it is not pertorming
conversions, it typically draws only 1601lA of supply
current when converting and automatically powering down
to atypical supply current of 1nA. The LTC1522 is available
in a16-pin SOIC package and operates on a3V supply. The
12-bit, switched-capacitor, successive approximation ADC
includes a software configurable 4-channel MUX as well
as sample-and-hold.

12-Bit Resolution
Auto Shutdown to 1nA
Guaranteed ±3/4LSB Max DNL
Low Supply Current: 1601lA
Single Supply 3V Operation
4-Channel Multiplexer
On-Chip Sample-and-Hold
Conversion Time: 60JlS
Sampling Rates: 10.5ksps
1/0 Compatible with SPI, MICROWIRE™, etc.
16-Pin SO Package

APPLICATions
•
•
•
•
•
•

Pen Screen Digitizing
Battery-Operated Systems
Remote Data Acquisition
Isolated Data Acquisition
Battery Monitoring
Temperature Measurement

On-chip serial ports allow efficient data transfer to a wide
range of microprocessors and microcontrollers over three
wires. This, coupled with micropowerconsumption, makes
remote location possible and facilitates transmitting data
through isolation barriers.
The circuit can be used in ratiometric applications or with
an external reference. The high impedance analog inputs
and the ability to operate with reduced spans (to 1.5V full
scale) allow direct connection to sensors and transducers
in many applications, eliminating the need for gain stages.
£T, LTC and IT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corp.

TYPICAL APPLICATiOn
12JlW, 4-Channel, 12-Bit ADC Samples at 200Hz and Runs 011 a 3V Battery
IIlF

3V

~h-l'l~
ANALOG INPUTS
OV TO 3V RANGE

1J

1 CHO
2 CHI

I
MUXOUT~
V 16
ee

14
3 CH2
DIN
4
- 13
CH3 l TC1522CS CS
SHA IN
ClK 12
11
VREF
Vee
10
DOUT
9
8 GND

SERIAL DATA LINK
MPU
SERIAL DATA LINK
(MICROWIRE'M AND
SPI COMPATIBLE)

.....1.
---.!

~COM

cs

lTC1522·TAOl

13-134

LTC 1522
ABSOLUTE mAxmum RATinGS

PACKAGE/ORDER InFORmATiOn

[Notes 1,2)

ORDER PART
NUMBER

Supply Voltage (Vee) to GND ................................... 12V
Voltage
Analog Reference .................... -O.3V to (Vee + O.3V)
Analog Input ............................ -O.3V to (Vee + O.3V)
Digitallnputs ......................................... -O.3Vto 12V
Digital Output ........................... -O.3V to (Vee +O.3V)
Power Dissipation .............................................. 500mW
Dperating Temperature Range ..................... O°C to 70°C
Storage Temperature Range ................. -65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

LTC1522CS

SPACKAGE
16-LEAD PLASTIC SO
TJMAX = 125"C. eJA = 120"C/W

Consult factory for Industrial and Military grade parts.

REcommEnDED OPERATinG conDITions
SYMBOL
{cc
'ClK
ICYC
:hDI
:sucs
:suDI
:WHClK
:WlClK
:WHCS
WlCS

PARAMETER
Supply Voltage (Note 3)
Clock Frequency
Total Cycle Time
Hold Time, DIN After ClKi
Setup Time CSJ, Before First ClKi (See Operating Sequence)
Setup Time, DIN Stable Before ClKi
ClK High Time
ClK low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer

~onVERTER

iYMBOL
)/(N + D)
'HD
,FOR

CONDITIONS

•
•
•
•
•

(Note 6)

(Notes 7, 8)
(Notes 7, 8)
(Note 9)

ACCURACY

•

TYP

MAX
3.6
200

UNITS
V
kHz
~

ns
~

ns
~
~

~
~

(Note 5)
MIN
12

TYP

MAX
±3
±3/4
±3
±8

1.5V to Vec + 0.05V
-0.05V to Vcc + 0.05V
±1

UNITS
Bits
LSB
lSB
lSB
LSB
V
V

IJA

(Note 5) fSMPL = 10.5kHz

PARAMETER
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion (Up to 5th Harmonic)
Spurious-Free Dynamic Range
Peak Harmonic or Spurious Noise

L7lJD~

Vcc = 2.7V
fClK = 200kHz
Vcc = 2.7V
Vcc = 2.7V
Vce = 2.7V
Vcc = 2.7V
Vcc = 2.7V
fClK = 200kHz
fClK = 200kHz

AnD mULTIPLEXER CHARAOERISTICS

IARAMETER
lesolution (No Missing Codes)
ntegral Linearity Error
liflerential Linearity Error
lflset Error
,ain Error
IEF Input Range
lnalog Input Range
malog Input leakage Current

~YnAmIC

MIN
2.7
(Note 4)
95
450
2
600
1.5
1.5
25
70

CONDITIONS

CONDITIONS
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal

MIN

TYP
68
-78
80
-80

MAX

UNITS
dB
dB
dB
dB

13-135

LTC 1522
DIGITAL AnD DC ELECTRICAL CHARAOERISTICS
VIH
Vil
IIH
III
VOH

SYMBOL

PARAMETER
High level Input Voltage
low level Input Voltage
High level Input Current
low level Input Current
High level Output Voltage

VOL
loz
ISOURCE
ISINK
RREF

Low level Output Voltage
Hi-Z Output leakage
Output Source Current
Output Sink Current
Reference Input Resistance

IREF

Reference Current

Icc

Supply Current

AC CHARACTERISTICS
SYMBOL

CONDITIONS
Vcc = 3.BV
Vcc = 2.7V
VIN = Vee
VIN =OV
Vcc = 2.7V, 10 = 101lA
Vcc = 2.7V, 10 = 3BOllA
Vcc = 2.7V, 10 = 4001lA
CS = High
VOUT = OV
VOUT = Vcc

•
•
•
•
•
•

•
•

MIN
2.0

TYP

MAX
0.8
2.5
-2.5

2.40
2.10

2.B4
2.30
0.4
±3
-10
15
2700
BO
0.001
50
50
0.001
1BO
1BO

~=VIH

CS = Vil
CS = Vcc
tcvc ~ 7BOJlS, fClK:S; 25kHz
tcvc ~ 95JlS, fClK:S; 200kHz
CS = Vcc, ClK = Vcc, DIN = Vcc
tcvc ~ 7BOJlS, fClK:S; 25kHz
!evc ~ 95JlS, fClK:S; 200kHz

•
•

•
•

UNITS
V
V

!JA
!JA
V
V
V

IlA
rnA
rnA
Mn
kn

2.5
70
±3
320

IlA
IlA
IlA
IlA
IlA
IlA

(Note 5)

tSMPl
tSMPl(MAX)

PARAMETER
Analog Input Sample Time
Maximum Sampling Frequency

tCONV
tdOO
tdis
ten
thOO
tf
tr
tON
tOFF
tOPEN
CIN

Conversion Time
Delay Time, ClK,l. to DOUT Data Valid
Delay Time, cst to DOUT Hi-Z
Delay Time, ClK,l. to DOUT Enabled
Time Output Data Remains Valid After CLK,l.
DOUT Fall Time
DOUT Rise Time
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Input Capacitance

CONDITIONS
See Operating Sequence 1
See Operating Sequence 1
See Operating Sequence 1
See Test Circuits
See Test Circuits
See Test Circuits
CLOAD = 100pF
See Test Circuits
See Test Circuits
See Operating Sequence 1
See Operating Sequence 2

MIN

TYP
1.5

MAX

10.5

•
•
•

•
•

125
Analog Inputs On-Channel
Off-Channel
Digital Input

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: This device is specified at 2.7V. Consult factory for SV
specified devices.
Note 4: Increased leakage currents at elevated temperatures cause the StH
to droop, therefore it is recommended that fClK ~ 120kHz at 70°C and
fClK ~ 1kHz at 2SoC.
Note 5: Vcc = 2.7V,VREF = 2.SV and ClK = 200kHz unless otherwise
specified.

13-136

(Note 5)

12
BOO
220
180
520
60
80
490
190
290
20
5
5

1500
BOO
500
180
180
700
300

UNITS
ClK Cycles
kHz
ClK Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF

Note 6: Linearity error is specified between the actual end points of the
ND transfer curve.
Note 7: Two on-Chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above Vcc. This spec allows 50mV forward
bias of either diode for 2.7V:s; Vcc:S; 3.BV. This means that as long as the
reference or analog input does not exceed the supply voltage by more than
SOmV, the output code will be correct. To achieve an absolute OV to 3V
input voltage range will therefore require a minimum supply voltage of
2.950V over initial tolerance, temperature variations and loading.
Note B: Recommended operating condition.
Note 9: Channel leakage current is measured after the channel selection.

LTC 1522

Pin FunOlons
CHO (Pin 1): Analog Multiplexer Input.

low on this input enables the lTC1522 to sample the
selected channel and start the conversion.

CH1 (Pin 2): Analog Multiplexer Input.

DOUT (Pin 10): Digital Data Output. The AID conversion
result is shifted out of this output.

CH2 (Pin 3): Analog Multiplexer Input.
CH3 (Pin 4): Analog Multiplexer Input.
SHA IN (Pin 5): Sample-and-Hold Amplifier Input. This
input is the positive analog input to the ADC. Tie to MUX
OUT for normal operation.
VREF (Pin 6): Reference Input. The reference input defines
the span of the AID converter.
COM (Pin 7): Negative Analog Input. This input is ~he
negative analog input to the ADC and must be free of nOise
with respect to GND.
GND (Pin 8): Analog Ground. GND should be tied directly
to an analog ground plane.
CS (Pin 9): Chip Select Input. A logic high on this input
allows the lTC1522 to select a particular channel. A logic

Vce (Pin 11): Power Supply Voltage. This pin provides
power to the AID converter. It must be bypassed directly
to the analog ground plane.
ClK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
CS (Pin 13): Chip Select Input. This input should be tied
to pin 9.
DIN (Pin 14): Digital Data Input. The multiplexer address
is shifted into this input.
MUX OUT (Pin 15): MUX Output. This pin is the ~utput of
the multiplexer. Tie to SHA IN for normal operation.
Vee (Pin 16): Power Supply Voltage. This pin should be
tied to pin 11.

TEST CIRCUITS
Vollage Waveforms for DOUT Rise and Fall Times, Ir, I,

Load Circuil for IdDO, Ir and I,
1.4V

DOUT
- - - - - - - - VIL

3k
DOUT 1------4~-- TEST POINT

LTC1522'TC02

- ' - 100pF

T

LTCl522·TCOl

Vollage Waveforms for DOUT Delay Times, IdDO
ClK

DOUT

~I;,,:V!..IL

Voltage Waveforms for len
lTC1522

CS\'--___________

_ _ _ _ _ __

r_"'DO~---====:::-

____

II

VIH

- - - - - - - - - - VIL

ClK

LTC1522'TC03

DOUT

L7~JD~

13-137

LTC 1522
TEST CIRCUITS
Voltage Waveforms for tdis

Load Circuit for tdls and ten
TEST POINT

Vee Idis WAVEFORM 2. len

' - - _.....

~

~_Idis WAVEFORM 1
100pF

DOUT

90%

WAVEFORM 1
(SEE NOTE 1)
t.!is
DOUT

LTC1522'TC04

WAVEFORM 2
(SEE NOTE 2) _ _-,-_ _ _ _ _ _---"
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 21S FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1522oTCQ6

APPLICATions InFoRmATion
INPUT DATA WORD
The LTC1522 uses CS and DIN to select one ·of its four
channels as shown in the operating sequence figures and
Table 1.
When CS is high, the input data on the DIN pin is latched
into the four-bit shift register on the rising edge of the
clock. The input data word consists of an "EN" bit and a
string of three bits for channel selection. If the "EN" bit is
logic high as illustrated in Operating Sequence 1, it enables the selected channel. To ensure correct operation,
the CS must be pulled low before the next rising edge ofthe
clock. More than four input bits can be sent to the ADC
without problems. The channel will be determined by the
last four bits clocked in before CS falls.
Once the CS is pulled low, all channels are simultaneously switched off to ensure a break-before-make
interval. After a delay of tON, the selected channel is
switched on allowing signal transmission. The selected
channel remains on until the next falling edge of CS; and
after a delay of tOFF, it turns off and subsequently allows
the selection of the next channel. If the "EN" bit is logic
low, as illustrated in Operating Sequence 2, it disables all
channels. Table 1 shows the various bit combinations for
channel selection.

13-138

Table 1 Logic Table for Channel Selection
. 01
Channel Status
EN
02
All Off
0
X
X
CHO
1
0
0

CH1
CH2
CH3

1
1
1

0
0
0

DO
X
0

0

1

1
1

0

1

ANALOG CONSIDERATIONS
Grounding
The LTC1522 should be used with an analog ground plane
and single-point grounding techniques. Do not use wirewrapping techniques to breadboard and evaluate the device. To achieve the optimum performance use a printed
circuit board. The Ground pin (Pin 8) should be tied
directly to the ground plane with minimum lead length.
Bypassing
For good performance, the LTC1522 Vcc and VREF pins
must be free of noise and ripple. Any changes in the
VCCIVREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code.
Bypass the VCCIVREF pin directly to the analog ground
plane with a minimum of a 0.1!lf capacitor and leads as
short as possible.

LTC 1522
.PPLICATlons InFORmATion
nalog Inputs
ecause of the capacitive redistribution AID conversion
lchniques used, the analog inputs of the LTC1522 have
apacitive switching input current spikes. These current

spikes settle quickly and do not cause a problem. But if
large source resistances are used or if slow settling op
amps drive the inputs, take care to ensure the transients
caused by the current spikes settle completely before the
conversion begins.

Operating Sequence 1
Example: (CH2, GND)

cs

,---------!cYC-------___..,

1-1

~

I

-----L

~I

ClK

DOUT

CHOTO
CH3

J~:!JIuT

____---.JL...j

COM = GND
lTC1522'TD01

Operating Sequence 2
Example: (ALL Channels Off)
1-I'------~--!cyC-------_'1

cs - '

I~--~L

ClK

•

CHOTa
CH3
SHAIN =
MUXOUT

COM =GND

L71'!J~

13-139

LTC 1522
TYPICAL APPLICATions
Microprocessor Interfaces

Motorola SPI (MC68HCD5)

The LTC1522 can interface directly (without external hardware) to most popular microprocessors' (MPU) synchronous serial formats (see Table 2). If an MPU without a
dedicated serial port is used, then three of the MPU's
parallel port lines can be programmed to form the serial
link to the LTC1522. Included here is one serial interface
example.

The MC68HC05 has been chosen as an example of an MPl
with adedicated serial port. This MPU transfers data MSB
first and in 8-bit increments. The DIN word sent to the date
register starts the SPI process. With three 8-bit transfer:
the AID result is read into the MPU. The second 8-bi
transfer clocks B11 through B7 of the AID conversior
result into the processor. The third 8-bit transfer clockl
the remaining bits B6 through BO into the MPU. ANDin(
the second byte with 1FHEX clears the three most signifi.
cant bits and ANDing the third byte with FEHEX clears thl
least significant bit.

Table 2. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1522**
PART NUMBER
Motorola
MC6805S2, S3
MC68HC11
MC68HC05
RCA
CDP68HC05
Hitachi
HD6305
HD6301
HD63701
HD6303
HD64180
National Semiconductor
COP400 Family
COP800 Family
NS8050U
HPC16000 Family
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020*
TMS370C050

TYPE OF INTERFACE
SPI
SPI
SPI
SPi
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
MICROWIRE
MICROWIREIPLUS™
MICROWIREIPLUS
MICROWIREIPLUS
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
SPI

• Requires external hardware.
* * Contact factory for interface information for processors not on this list.
MICROWIREIPLUS is a trademark of National Semiconductor Corp.

13-140

lOA #$52
STA $OA
LDA #$FF
STA
STA
STA
lOA

$04
$05
$06
#$08

STA $50
START BSET 0,$02
LOA $50
STA $OC
LOOP1 TST SOB
BPL LOOP1
BCLR 0,$02
LDA SOC
STA $OC
LOOP2 TST SOB
BPL LOOP2
LOA SOC
STA SOC
AND #$IF
STA $00
LOOP3 TST $OB
BPL LOOP3
LDA SOC
AND #$FE
STA $01
JMP START

MC68HC05 CODE
Configuration data for serial peripheral
control register (Interrupts disabled, output
enabled, master, Norm = 0, Ph = 0, Clkl16)
Load configuration data into location $OA (SPCR)
Configuration data for I/O ports
(all bits are set as outputs)
Load configuration data into Port A DDR ($04)
Load configuration data into Port BDDR ($05)
Load configuration data into Port CDDR ($06)
Put DIN word for LTC1522 into Accumulator
(CHO with respect to GND)
Load DIN word into memory location $50
Bit aPort C($02) goes high (CS goes high)
Load DIN word at $50 into Accumulator
Load DIN word into SPI data register ($OC) and
start clocking data
Test status of SPIF bit in SPI status register ($OB)
Loop if not done with transfer to previous
instruction
Bit 0 Port C($02) goes low (CS goes low)
Load contents of SPI data register into Accumulator
Start next SPI cycle
Test status of SPIF
Loop if not done
Load contents of SPI data register into Accumulator
Start next SPI cycle
Clear 3 MSBs of first DOUT word
Load Port A ($00) with MSBs
Test status of SPIF
Loop if not done
Load contents of SPI data register into Accumulator
Clear LSB of second DOUT word
Load Port B ($01) with LSBs
Go back to start and repeat program

LTC 1522
TYPICAL APPLICATions
Data Exchange Between LTC1522 and MC68HC05

\~-----------------------------ClK

---'~II((II)IIIfIlJjfflllllfll/l P9~YC~~~ 'I1f(((1III!//I!)I!J/I!J/I(/III

DIN _ _

Dour - - - - - - - - - - - - - - - ,

MPU
TRANSMIT
WORD

I

MPU
RECEIVED
WORD

1?1?111?1?1?1?1?1

0

I

0

I

0

I

0

I EN I D2 I D1 I DO I

Ixlxlxlxlxlxlxlxl

Ixlxlxlxlxlxlxlxl

BYTE 2

BYTE 1

BYTE 3

1 ? 1 ? 1 0 1B11 1 BlO 1 B91 BB 1 B7 1

BYTE 1

lool~IMI~I~I~lwl~1

BYTE 2

BYTE 3

LTC1522-TA02

Hardware and Software Interface to Motorola MC68HC05
DOUT FROM lTC1522 STORED IN MC68HC05 RAM
MSB

#00

I I I I I I I I I
0

0

0

B11

B10

B9

BB

B7

BYTE 1
ANALOG {
INPUTS

lSB

#01

I I I I I I I I I
B6

B5

B4

B3

B2

B1

BO

0

BYTE 2

-

cs
ClK
lTC1522
DIN
Dour

co
SCK
MC6BHC05
MOSI
MISO

RELATED PARTS
PART NUMBER
l TCl 096/lTCl 098
lTCl196/lTCl198
lTC1282
LTC1285/LTC1288
lTC1289

DESCRIPTION
8-Pin SO, Micropower 8-Bit ADC
8-Pin S0, 1Msps 8-Bit ADC
3V High Speed Parallel l2-Bit ADC
8-Pin S0, 3V Micropower l2-Bit ADC
Mutiplexed 3V lA l2-Bit ADC

COMMENTS
Low Power, Small Size, low Cost
low Power, Small Size, low Cost
l40ksps, Complete with VREF, ClK, Sample-and-Hold
l2-Bit ADC in SO-8
8-ChanneI12-Bit Serial 1/0

lEI
.L7lJD~

13-141

.f= AD
L
I
n
u ,
£.7
.

lFlililS',LbUlI\YJlJUlNJLA\liliLf

LTC 1550/LTC 1551
TECHNOLOG~~~-----L-o-w-N-o-i-se-,-S-w-it-c-h-e~d

Capacitor-Regulated
Voltage Inverters
June 1995

FEATURES

DESCRIPTiOn

• Regulated Negative Voltage from Single
Positive Supply
• Low Output Ripple: Less Than 1mV Typ
• High Charge Pump Frequency: 900kHz Typ
• REG Output Indicates Output Is in Regulation
• Small Charge Pump Capacitors: 0.1 W
• Requires Only Four External Capacitors
• Fixed -4.1V or Adjustable Output
• Shutdown Mode Drops Supply Current to 1}.IA
• Output Current: Up to 20mA
• Output Regulation: 5%
• Available in 8-Pin SO and 16-Pin SSOP Packages

The LTC®1550/LTC1551 are switched-capacitor voltage
inverters with internal linear post regulators. Each is
available in a fixed -4.1 Vversion while the LTC1550 also
offers an adjustable output voltage version. Typical output
ripple is below 1mV. The LTC1550/LTC1551 are designed
for use as bias voltage generators for GaAs transmitter
FETs in portable RF and cellular telephone applications.

APPLICATions
•
•
•
•

GaAs FET Bias Generators
Negative Supply Generators
Battery-Powered Systems
Single Supply Applications

The LTC1550/LTC1551 operate from asingle 4.5Vto 6.5V
supply, with atypical quiescent current of 5mAatVee =5V.
Both devices include a TIL compatible shutdown pin
which drops supply currentto 0.2}.IA typically. The LTC1550
shutdown pin is active low (SHDN) while the LTC1551
shutdown pin is active high (SHDN). Only four external
components are required for fixed output parts: an input
bypass capacitor, two 0.1 W charge pump capacitors and
a 10W filter capacitor at the linear regulator output.
Adjustable parts require two additional resistors to set the
output voltage.
Each version of the LTC1550/LTC1551 will supply up to
20mA output current with guaranteed.output regulation of
±5%. The 16-pin version of the LTC1550/LTC1551 includes an open-drain REG output which pulls low to
indicate that the output is within 5% of the set value.
For applications with Vee supplies as low as 3V, see the
LTC1261. For applications requiring an external synchronization clock and Vee as low as 3V, see the LTC1429.

LT. LTC and LT are registered trademarks 01 Linear Technology Corporation.

TYPICAL APPLICATiOn
-4V Generator with 1mVp.p Noise

VOUT Output Noise and Ripple

2mV/DIV
Vour=-4.1V
ILOAD = lOrnA
Cl
O.lI1F

13-142

1550151TAOl

10IJS/DIV

1550151TA02

LTC 1550/LTC1551
~BSOLUTE

mAXimum RATinGS

lote 1)
upply Voltage (Note 2) ............................................ lV
utput Voltage ................................ 0.3V to (Vcc -14V)
otal Voltage, Vcc to CPOUT (Note 2) ...................... 14V
Iput Voltage (SHDN Pin) ........... -0.3V to (Vcc + 0.3V)
Iput Voltage (REG Pin) ............................ -0.3V to 12V

Output Short-Circuit Duration .......................... Indefinite
Operating Temperature Range .................... O°C to lO°C
Storage Temperature Range ................ -65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C

IACKAGEIORDER InFORmATiOn
TOP VIEW
1
16 ~Vee
15
SHDN'"
w~ 2
14 ~ REG
NC~ 3
VOUT ~ 4
13
SENSE
12
ADJ"
C1-~ 5
PGND
6
11
CPOUT
AGND § 7
10
NC
8
9
NC
NC
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150'C, 8JA = 150'C/W
NC~

§
§

TOP VIEW

LTC1550CGN
LTC1550CGN-4.1
LTC1551CGN-4.1

~'"··o"··

lEF

,e
IL
,G
j

~

LTC1550CS8-4.1
LTC1551 CS8-4.1

S8 PART MARKING
15504
15514

* NC for fixed output versions.
** SHDN for LTC1550, SHDN for LTC1551

(Note 3)

=C2 =O.l).1f, COUT =10).lf, unless otherwise specified.

PARAMETER
Supply Voltage
Reference Voltage
Supply Current
Internal Oscillator Frequency
REG Output Low Voltage
REG Sink Current
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
Turn On Time

L7lJfJ~

CPOUT
6 GND
5 cr
7

S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150'C, 8JA = 150'C/W

1550
155041
155141

:LEORICAL CHARAOERISTICS
'MBOL
:e

Vee 2
C1' 3 ','
VOUT 4 '

GN PART MARKING

Insult factory for Industrial and Military grade parts.

c =4.5V to 6.5V, C1

ORDER
PART NUMBER

ORDER
PART NUMBER

CONDITIONS
(Note 2)
VSHDN = GND (LTC1551)or Vee (LTC1550)
VSHDN = Vee = 5V (LTC1551) or GND (LTC1550)
IREG = 1rnA, Vee = 5V
VREG = 0.8V, Vee = 5V

VSHDN = Vee
loup lOrnA

MIN
4.5

••
•
•
•
•
•

8
2.0

TYP
1.24
5.0
0.2
900
0.1
15

0.1
1

MAX
6.5
7.0
10.0
0.8

0.8
1

UNITS
V
V
rnA

IJA
kHz
V
rnA
V
V

IJA
rns

13-143

LTC 1550/LTC 1551
ELEORICAL CHARAOERISTICS
Vs =4.5V to 6.5V, C1

(Note 3)

=C2 =O.11JF, COUT =101JF, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

t..VOUT

Output Regulation (LTC1550 Only)

Vee =5V, O,s; IOUT,s; lOrnA
Vee =6V, O,s; IOUT,s; 20mA

TYP
MAX
UNITS
1
5
%
1
5
%
Output Voltage (LTC1550-4.1, LTC1551-4.1) Vee =4.SV, O,s; IOUT,s; 5mA
-3.9
-4.1
-4.3
V
VOUT
-3.9
-4.1
-4.3
V
Vee =5V, O,s; IOUT,s; lOrnA
-3.9
-4.1
-4.3
V
Vee =6V, O,s; IOUT,s; 20mA
Output Short-Circuit Current
50
125
rnA
Ise
VOUT =OV, Vee =5V
60
125
rnA
VOUT =OV, Vee =6V
Output Ripple Voltage
1
mV
VRIPPLE
Note 2: The output should never be set to exceed Vee -14V.
The. denotes specifications which apply over the full operating
temperature range.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
Note 1: Absolute Maximum Ratings are those values beyond which the life
specified. All typicals are given at TA = 25°C.
of adevice may be impaired.
MIN

•
•
•
•
•
•

•

Pin FunCTions
SHDN: Shutdown (TTL Compatible). This pin is active low
(SHDN) for the LTC1550 and active high (SHDN) for the
LTC1551. When this pin is at Vee (GND for LTC1551), the
LTC1550 operates normally. When SHDN is pulled LOW
(HIGH for LTC1551), the LTC1550 enters shutdown mode.
In shutdown, the charge pump stops, the output collapses
to OV, and the quiescent current drops typically to 0.2/lA.
Vcc: Power Supply. Vee requires an input voltage between
4.5V and 6.5V. The difference between the input voltage
and output should never be set to exceed 14V or damage
to the chip may occur. Vee must be bypassed to PGND
(GND for the B-pin package) with at least a 1Wcapacitor
placed in close proximity to the chip. A 4.7W or larger
bypass capacitor is recommended to minimize noise and
ripple at the output.
C1 +: C1 Positive Input. Connecta 0.1 Wcapacitor between
C1 + and C1-.
VOUT: Negative Voltage Output. This pin must be bypassed
to ground with a 4.7W or larger capacitor to ensure
regulator loop stability. At least 10).IF is recommended to
provide specified output ripple. An additional low ESR
0.1 Wcapacitor is recommended to minimize high frequency spikes at the output.

13-144

C1-: C1 Negative Input. Connect a 0.1).IF capacitor from
C1 + to C1-.
GND: Ground. Connect to a low impedance ground. A
ground plane will help minimize regulation errors.
CPOUT: Negative Charge Pump Output. This pin requires a
0.1 Wstorage capaCitor to ground.
SENSE: Connectto VOUT. The LTC1550/LTC1551 internal
regulator uses this pin to sense the output voltage. For
optimum regulation, SENSE should be connected close to
the output load.

16-Pin SSOP Only
PGND: Power Ground. Connectto alow impedance ground.
PGND should be connected to the same potential as
AGND.
AGND: Analog Ground. Connect to a low impedance
ground. AGND should be connected to a ground plane to
minimize regulation errors.
REG: This is an open-drain output that pulls low when the
output voltage iswithin 5% ofthesetvalue.ltwill sinkBmA
to ground with a 5V supply. The external circuitry must
provide a pull-up or REG will not swing high. The voltage
at REG may exceed Vee and can be pulled up to 12Vabove
ground without damage.

LTC 1550/LTC 1551
OJ: For adjustable versions only, this is the feedback
oint for the external resistor divider string. Connect a
ivider string from AGND to VOUT with the divided tap
Jnnected to ADJ. Note that the resistor string needs to be
Jnnected "upside-down"from atraditional negative regu-

~lOCK

lator. See the Applications Information section for hookup details.

NC: No Internal Connection.

DIAGRAm

~

~COUT

CPOUT

VOUT

ADJ

CHARGE
PUMP

LINEAR
REGULATOR

• FIXED OUTPUT
VERSIONS ONLY

REG

SENSE

•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

•
13-145

LTC 1550/LTC 1551
APPLICATions InFoRmATion
THEORY OF OPERATION
The LTC1550/LTC1551 are switched-capacitor, inverting
charge pumps with integral linear post regulators to
provide a regulated, low ripple negative output voltage.
The charge pump runs at ahigh 900kHz frequency to keep
noise out of the 400kHz to 600kHz IF bands commonly
used by portable radio frequency systems, and to minimize the size of the external capacitors required. The
LTC1550/LTC1551 require only two external 0.1 ~ charge
pump capacitors: an input bypass capacitor and a single
output capacitor. At least 4. 7~ is required atthe output to
maintain loop stability; for optimum output stability over
temperature and minimum ripple, 1O~ or greater is
recommended.
The LTC1550 features an active-low shutdown pin which
drops quiescent current to below 1~. The LTC1551 is
identical to the LTC1550 but the shutdown pin is active
high. Both the LTC1550/LTC1551 are available with fixed
-4.1 Voutput voltage, and the LTC1550 is also available in
an adjustable output version. Both devices can be configured with other output voltages. Contact the Linear Technology marketing for more information.

L-..-----+-.......-....--_-~~Ulv
ROUT

8200
":"

Figure la. Test Circuit Used for Spectrum Analysis

:;;"-

~
~

is
z

Figure 1ashows the test circuit used for spectrum analysis
with test conditions Vcc = 6V, lOUT = 5mA. Figures 1band
1care the VOUT spectrum plots forthe test circuit in Figure
1a, covering from 100Hz to 1MHz and to 10MHz respectively. The fundamental switching frequency appears at
900kHz.
Output ripple can be further reduced by increasing the size
ofthe output capacitor, or by including asmall external RC
or LC filter at the output. A ferrite bead in series with the
output capaCitor will reduce the output ripple to negligible
levels.

13-146

70
60
50
40
30
20
10
0
-10
-20
lk

Minimizing Output Noise and Ripple
Output ripple is largely eliminated by the internal linear
regulator. It is typically below 1mVp_p with output loads
between zero and 10mA. Residual ripple is at the 900kHz
switching frequency of the charge pump and is usually not
aproblem in most systems. This high frequency ripple can
be minimized by using a low ESR capacitor at the output.
An 0.1 ~ ceramic capacitor in parallel with a 1O~ tantalum makes a good combination.

1550151FOla

10k
FREQUENCY (Hz)

lOOk

1M
15S0/51FOlb

Figure lb. Spectrum Plot of VOUT from 100Hz to lMHz
70 ,_········'·_·T··_···,·····,·

60
50 !·····_·_-_··t··__·
-

~

40
30 i-····---+_····

w

20 ;............... ;.......

U)

is
z

10

+....+...

~···--·-i·---···!-·-

-10 ,_.._ .•_._+...._-+.
-20 ,_._......_-+._-+_..j

-30
lOOk

1M
FREQUENCY (Hz)

10M
1550151FOlc

Figure lc. Spectrum Plot of Your from 100kHz to 10MHz

Output load and line transient response can be optimized
by increasing the size of the output bypass capacitor.
Adjustable parts can further improve transient response
by bypassing the upper resistor R1 (Figure 2) in the
feedback divider with acapacitor. A1OOpF bypass capacitor is usually adequate.

LTC 1550/LTC 1551
APPLICATions InFoRmATion
'djustable Hookup
fhe LTC1550 is available in an adjustable output version
nthe 16-pin SSOP package. The output voltage is set with
1 resistor divider from GND to SENSElVoUT (Figure 2).
~ote that the internal reference and the internal feedback
lmplifier are set up as a positive-output regulator refermced to the SENSE pin, not a negative regulator refermced to ground. The output resistor divider must be set
:0 provide a 1.24Vat the ADJ pin with respect to VOUT. For
lxample, a-3.0Voutputwould require a13k resistor from
3ND to ADJ, and a 9.1 k resistor to SENSENoUT. If, after
;onnecting the divider resistors, the output voltage is not
Nhat you expected, try swapping them.

PGND, AGND 1-'6,;,.,.,7-...._..,

R2
VOUT, SENSE 4, 11

Voup -1.24V ( R1:2R2 )
1550J51F02

Figure 2. External Resistor Connections

rYPICAL APPLICATiOn
Minimum Pari Count, Negative -4.1V Generator
SHDN

.---=~ Vee

SENSE 8
CPOUT

j-:.7_-+_--,

LTC1551-4.1
3 C1+
GND 6

4 VOUT

'-------+-+-- Voup.-4.1V

'ELATED PARTS
'ART NUMBER

DESCRIPTION

COMMENTS

n054

Switched Capacitor Voltage Converter with Regulator

100mA Switched Capacitor Converter

TC1261

Switched Capacitor Regulated Voltage Inverter

Selectable Fixed Output Voltages

TC1429

Clock-Synchronized Switched Capacitor Voltage Inverter

Synchronizable

13-147

LYLIn
.

-- -- - -- -- -

----~

------

Final Electrical Specifications

LTl 580/LTl 580-2.5

TECHNOLO·~G~IY~-----7-A-,-\/I-e-ry-.-Lo-w-

. ..

Dropout Regulator
June 1995

FEATURES

DESCRIPTiOn

• Low Dropout, 540mV at 7A Output Current in
Dual Supply Mode
• Fast Transient Response
• Remote Sense
• 1mV Load Regulation
• Fixed 2.5V Output and Adjustable Output
• No Supply Sequencing Problems in
Dual Supply Mode

The LT®1580 is a 7A low dropout regulator designed to
power the new generation of microprocessors. The drop·
out voltage of this device is 1OOmV at light loads rising to
just 540mV at 7A. To achieve this dropout a second low
current input voltage, 1V greater than the output voltage,
is required. The device can also be used as asingle supply
device where dropout is comparable to an LT1584. Sev·
eral other new features have been added to this device.

APPLICATions

A remote Sense pin is brought out. This feature virtually
eliminates output voltage variations due to load changes.
Typical load regulation, measured at the Sense pin, for a
load current step of 1OOmA to 7A is less than 1mV.

•
•
•
•

Microprocessor Supplies
Post Regulators for Switching Supplies
High Current Regulators
5V to 3.XXV for Pentium® Processors Operating
at 90MHz, 100MHz, 120MHz and Beyond
• 3.3V to 2.9V for Portable Pentium Processor
• Power PC™ Series

The LT1580 has fast transient response, equal to the
LT1584. On fixed voltage devices, the Adjust pin is broughl
out. A small capaCitor on the Adjust pin further improves
transient response.
This device is ideal for generating processor supplies 01
2V to 3V on motherboards where both 5V and 3.3V
supplies are available.
£T, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is aregistered trademark of Intel Corporation. Power PC is atrademark of IBM Corporation

TYPICAL APPLICATiOn
2.5V Microprocessor Supply
3·~X

-....---1 POWER

Load Current Step Response
2.5VI7A

OUTPUT

I---~)-'

+ 330~F
rOS-CON

5V _ _ _
O.2A

+

VOllT
50mVIDIV

LTI580-2.5

~

10~F

"JTANT

Load

l

7A

400mA

13-148

LTl 580/LTl 580-2.5
ABSOLUTE mAXimum RATinGS

PREconDITiOninG

VPOWER Input Voltage ................................................ 6V
VCONTROL Input Voltage ........................................... 13V
Storage Temperature ............................ -65°C to 150°C
Operating Junction Temperature Range
Control Section ...................................... O°C to 125°C
Power Transistor ................................... O°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C

100% Thermal Limit Functional Test

PACKAGE/ORDER InFORmATiOn
FRONT VIEW
5

0

4
3
2
1

I

I
I

VPOWER
VCONTROL
OUTPUT
ADJUST
SENSE

FRONT VIEW

ORDER PART
NUMBER
LT1580CT

TPACKAGE, 5-LEAD TO-220

6
5

0

4
3
2
1
T7

6JA =50'C/W

NC
VPOWER
AOJUST
OUTPUT
VCONTROL
GND
SENSE

7

ORDER PART
NUMBER
LT1580CT7 -2.5

PACKAGE. HEAD TO-220
6JA =50'C/W

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS
PARAMETER
Output Voltage - LT1580-2.5

(Note 1)

CONDITIONS

VCONTRDL =5V, VPOWER =3.3V, ILOAD =OmA
VCONTROL =4V to 12V, VPOWER =3V to 5.5V, ILOAD =OmA to 4A
VCONTROL =4V to 12V, VPOWER =3.3V to 5.5V, ILOAD =OmA to 7A
Reference Voltage - LT1580
VCONTROL =2.75V, VPOWER =2V, ILOAD =lOrnA
(VADJ =0)
VCONTROL =2.7V to 12V, VPOWER =1.75V to 5.5V, lOUT =10mA to 4A
VCONTROL =2.7V to 12V, VPOWER =2.05V to 5.5V, lOUT =10mA to 7A
Line Regulation - LT1580-2.5
VCONTROL =3.65V to 12V, VPOWER =3V to 5.5V, ILOAD =10mA
LT1580
VCONTROL =2.5Vto 12V, VPOWER =1.75V to 5.5V, ILOAD =10mA
Load Regulation - LT1580-2.5
VCONTROL =5V, VPOWER =3.3V, ILOAD =OmA to 7A
LT1580 (VADJ =OV) VCONTROL =2.75V, VPOWER =2.1V, ILOAD =lOrnA to 7A
Minimum Load Current - LT1580
VCONTROL =5V, VPOWER =3.3V, VADJ = OV (Note 3)
Control Pin Current - LT1580-2.5
VCONTROL =5V, VPOWER =3.3V, ILOAD =100mA
(Note 4)
VCONTROL =5V, VPOWER =3.3V, ILOAD =4A
VCONTROL =5V, VPOWER =3V, ILOAD =4A
VCONTROL =5V, VPOWER =3.3V, ILOAD =7A
Control Pin Current - LT1580
VCONTROL =2.75V, VPOWER =2.05V, ILOAD =100mA
(Note 4)
VCONTROL =2.75V, VPOWER =2.05V, ILOAD =4A
VCONTROL =2.75V, VPOWER =1.75V, ILOAD =4A
VCONTROL =2.75V, VPOWER =2.05V, ILOAD =7A
Ground Pin Current - LT1580-2.5
VCONTROL =5V, VPOWER =3.3V, ILOAD =OmA
Adjust Pin Current - LT1580 (VADJ =OV) VCONTROL =2.75V, VPOWER =2.05V, ILOAD =OmA
Current Limit - LT1580-2.5
VCONTROL =5V, VPOWER =3.3V, AVOUT =100mV
LT1580 (VADJ =OV) VCONTROL =2.75V, VPOWER =2.05V, AVOUT =100mV
Ripple Rejection - LT1580-2.5
Vc =Vp =5V Avg, VRIPPLE =lVp_p, lOUT =4A, TJ =25°C
LT1580
Vc =Vp =3.75V Avg, VRIPPLE =lVp_p, VADJ =OV, lOUT =4A, TJ =25°C

••
••
••
••
•
••

MIN
2.485
2.475
2.475
1.243
1.237
1.237

•
•
•
••

•
•
•
•
•

7.1
7.1
60
60

TYP
2.500
2.500
2.500
1.250
1.250
1.250
1
1
1
1
5
6
30
33
60
6
30
33
60
6
50
8
8
80
80

MAX
2.515
2.525
2.525
1.257
1.263
1.263
3
3
5
5
10
10
60
70
120
10
60
70
120
10
120

UNITS
V
V
V
V
V
V
mV
mV
mV
mV
mA
rnA
rnA
rnA
mA
rnA
mA
rnA
mA
rnA

!iA
A
A
dB
dB

13-149

lEI

LT1580/LT1580-2.5
ELEORICAL CHARACTERISnCS
PARAMETER
Thermal Regulation
Thermal Resistance, Junction-to-Case
Dropout Voltaga (Nota 2)
Minimum VCONTROL - LT1580-2.5
(VCONTROL - VOUT)

Minimum VCONTROL - LT1580
(VCDNTROL - VDur)
(VADJ =0)

Minimum VPOWER - LT1S80-2.S
(VPOWER - VOUT)

Minimum VPOWER - LT1580
(VPOWER - VOUT)
(VADJ =0)

CONDITIONS
30ms Pulse
T, T7 Packages, Control Circuitry/Power Transistor
VPOWER =3.3V, ILOAO =100mA
VPOWER =3.3V, ILOAO =1A
VPOWER =3.3V, ILOAD =4A
VPOWER =3.3V, ILOAD =7A
VPOWER =2.05V, ILOAD =100mA
VPOWER =2.05V, ILOAD =1A
VPOWER =2.05V, ILOAD =2.75A
VPOWER =2.05V, ILOAD =4A
VPOWER =2.0SV, ILOAD =7A
VCONTROL =SV, ILOAD =100mA
VCONTROL =5V, ILOAD =1A
VCONTROL =SV, ILOAD =4A, TJ =25°C
VCONTROL =5V, ILOAD =4A
VCONTROL =SV, ILOAD =7A, TJ =25°C
VCONTROL =SV, ILOAD =7A
VCONTROL =2.75V, ILOAD =100mA
VCONTROL =2.75V, ILOAD =1A
VCONTROL =2.75V, ILOAD 2.7SA
VCONTROL =2.7SV, ILOAD =4A, TJ =25°C
VCONTROL =2.75V, ILOAD =4A
VCONTROL =2.75V, ILOAD =7A, TJ =25°C
VCONTROL =2.7SV, ILOAD =7A

The. denotes specifications which apply over the full operating
temperature range.
Note 1: Unless otherwise specified VOUT = VSENSE. Forthe LT1S80
adjustable device VADJ = OV.
Note 2: For the LT1580, dropout is caused by either minimum control
voltage (VCONTROU or minimum power voltage (VPOWER). Both parameters
are specified with respect to the output voltage. The specifications represent
the minimum inpuVoutput voltage required to maintain 1% regulation.

Pin FunOlons

1

••
••
•
•••
•
••

•
•
•
•

•
•
•

TYP
0.002
0.65

MAX
0.020
2.70

UNITS
%/W
°C/W

1.00
1.00
1.06
1.15
1.00
1.00
1.05
1.06
1.15
0.10
0.15
0.34

1.15
1.15
1.20
1.30
1.15
1.15
1.18
1.20
1.30
0.17
0.22
0.40
0.50
0.62
0.80
0.17
0.22
0.38
0.40
0.50
0.62
0.80

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

0.54
0.70
0.10
0.15
0.26
0.34
0.S4
0.70

Note 3: For the LT1580 adjustable device the minimum load current is the
minimum current required to maintain regulation. Normally the current in
the resistor divider used to set the output voltage is selected to meet the
minimum load current requirement.
Note 4: The control pin current is the drive current required for the output
transistor. This current will track output current with roughly a 1:100 ratio.
The minimum value is equal to the quiescent current of the device.

(5-lead TO·220n·Lead TO·220)

SENSE (Pin 1): This pin is the positive side of the reference
voltage for the device. With this pin it is possible to Kelvin
Sense the output voltage at the load.
ADJUST (Pin 215): This pin is the negative side of the
reference voltage for the device. Transient response can
be improved by adding asmall bypass capaCitor from the
Adjust pin to ground. For fixed voltage devices the Adjust
pin is also brought out to allow the user to add a bypass
capaCitor.
GND (Pin 2, 7-Lead Only): For fixed voltage devices this
is the bottom of the resistor divider that sets the output
voltage.

13-150

MIN

I

VPOWER (Pin 5/6): This is the collector to the power device

of the LT1580. The output load current is supplied through
this pin. For the device to regulate, the voltage at this pin
must be between 0.1V and 0.8V greater than the output
voltage (see Dropout specifications).
VCONTROL (Pin 4/3): This pin is the supply pin for the

control Circuitry of the device. The current flow into this
pin will be about 1% of the output current. For the device
to regulate, the voltage at this pin must be between 1.0V
and 1.3V greater than the output voltage (see Dropout
specifications).
OUTPUT (Pin 3/4): This is the power output of the device.

LTl 580/LTl 580-2.5
~PPLICATlons

InFORmATion

rhe LT1580 is a low dropout regulator designed to power
he new generation of microprocessors. The device uses
I two supply approach to maximize efficiency. The collecor of the output power device is brought out to minimize
he dropout at high current. A separate input control
roltage with an input current of approximately 1% of the
)utput current requires a slightly higher input voltage (1 V
a 1.5V). The device is designed to take advantage of the
act that most motherboards will have both 5V and 3.3V
iupplies available. The main output current will come from
he 3.3V supply while the 5V supply only has to supply a
elatively small drive current.
'wo other new featu res have been added tothis device. An
)utput sense pin has been added to allow true Kelvin
iensing of the output voltage. This feature can virtually
Iliminate errors in the output voltage due to load regulaion. Regulation will be optimum at the paint where the
iense pin is tied to the output pin. Forfixed voltage devices
he adjust pin, not normally available, is brought out to
Illow bypassing. Bypassing the adjust pin with a small
:apacitor in the range of 0.1 Wto 0.3~ can improve
ransient response significantly. Good transient response
lecomes even more important as processor operating
nargins continue to shrink.
;pecial care has been taken to ensure that there are no
;upply sequencing problems. The output voltage will not
urn on until both supplies are operating. If the control
'oltage comes up first, the output current will be limited to

a few milliamperes until the power input voltage comes
up. If the power input comes up first the output will not
turn on at all until the control voltage comes up. The output
can never come up unregulated.
The LT1580 can also be used as a single supply device
with the control and power inputs tied together. In this
mode, the dropout will be determined by the minimum
control voltage (1.15V to 1.3V).

Adjustable Operation
The output voltage of the LT1580 can be adjusted using a
resistor divider as shown in Figure 1. The reference
voltage of the device is connected between the sense pin
and the adjust pin. R1 should be 100n or less to ensure
that the minimum load current specification is met.
+

330!,F

Tos.cON

5V
0.2A

_..-_-1 CONTROL

VOUF 1.25V(1 +

ADJH---,

~) + IADJ (R2)

IADJ = 501lA
'MAKING R1 = 100n ENSURES THAT MINIMUM OUTPUT CURRENT REQUIREMENT IS MET.

Figure 1. Adjustable Operation

'ELATED PARTS
ART NUMBER

DESCRIPTION

COMMENTS

TC"1266

Synchronous Switching Controller

>90% Efficient High Current Microprocessor Supply

TC1267
T1430

Dual High Efficiency Synchronous Switching Regulator
High Power Synchronous Step-Down Switching Regulator

>90% Efficiency with Fixed 5V, 3.3V or Adjustable Outputs
>90% Efficient High Current Microprocessor Supply

T1584

7A Low Dropout Fast Transient Response Regulator

For High Performance Microprocessors

T1585

4.BA Low Dropout Fast Transient Response Regulator

For High Performance Microprocessors

T1587

3A Low Dropout Fast Transient Response Regulator

For High Performance Microprocessors

lEI

13-151

NOTES

13-152

SECTion 14-PACKAGE InFoRmATion

.L7lJD~

14-1

INDEX
SECTION 14-PACKAGE DIMENSIONS
INDEX ....................................................................................................................................... 14-2
PACKAGE CROSS REFERENCE .......................................................................................................... 14-3
PACKAGE DIMENSIONS .................................................................. ~ ............................................... 14-5
SURFACE MOUNT PRODUCTS ........................................................................................................ 14-36
TAPE AND REEL ......................................................................................................................... 14-47
TO-220 LEAD BEND OPTIONS ......................................................................................................... 14-54

14-2

f"""""-Llnet\Q
~, TECHNOLOG~f{-----PACKAGE CROSS REFERENCE

PACKAGE OUTLINE

0 m'
0:::0 wmw

C

...a:m
w

N

w

C

c;;

.

"'c

~~~
rnu')C

UJc::=

to-.- n:s

t=a

0

'5

0

:5ii
"'E
U,)u,)

...·c
c

-=

u,)

LTC

NSC

08

0

0

14-, 16-, 18- and 20-Lead
Side Brazed (Hermetic)

0

0

0

20-Lead Plastic TSSOP (0.173)

F

!iiiiiiiil

t:J
0

~

G

16-,20- and 24-Lead Plastic
SSOP (Narrow 0.150)

GN

36- and 44-Lead Plastic
SSOP (Wide 0.300)

GW

MSA

H

H

Q

z
~

""0

MSA

RS

1,,,,,,,,"",,,",,,,,,,1

0

~

w

:IE

0

CJ rwmw

ffic

-

H

3- or Head TO-39 Metal Can

H

H

H

2-,3- or Head Standard TO-46
Metal Can or in Thermal Caps

H

H

H

3-Lead TO-52 Metal Can

H

E
I!

z
~
-'

~
w
:IE

'"
'"-'

l ..

f

"---

.. c.J

0

T
T

(IT)

8-Lead Ceramic DIP (Hermetic)

J8

J
J8

a

14-,16-,18-,20- and 24-Lead
Ceramic DIP
(Narrow 0.300, Hermetic)

J

J
J14
J16

0
a

a

D~

D~
_-I
I

.

i

I
I

VB
aB
XB

L

-

-

DL
PW

-

I

I
I
I
I
I

I
I

-

-

MAXIM
DA
DO, DE,
DN,DP
UP,
UG,
UI

DB

AP,
AG,
AT

-

DB

AX

-

H
J
K

G

I
I

H
J
K

G

-

T

VS
lV,
TW,
VS

-

-

T

-

iI

T

lV,

iI

TW,

r.:._
r
,

[.-

I z
I

U

JG

V

JA

V
a
X

L
J

J

J

RD, RN,
RE, RP

T

L

-

K

-

K

KQ

-

-

KJ

K

KS

F

FN

FN
FK

L

L

F

FN

FN
FK

L

L

OP
REF
CMP

MC

TL

LX
SG

MAX

:
I

28-Lead Ceramic DIP
(Wide 0.600, Hermetic)

JW

-

Head TO-3 Metal Can

K

K
Steel

-

Head TO-3 Metal Can

K

K

-

20-Pin Leadless Chip Carrier
(Rectangular, Hermetic)

L

E

E

i

JG,
JI

I

00

"1

LlNFIN
-

SR

"'.2

.
'"

TI
-

i

0 ?m

..
:5
=
a..
is:

I

I

-'

~
DOD

MOT

I

8- or 1O-Lead TO-5 Metal Can

u,)

U

16-, 20-, 24- and 28-Lead
Plastic SSOP (0.209)

-

ADIJPMI

~

0

!

DESCRIPTION
8-Lead Side Brazed (Hermetic)

i
i
i

I
20-Pin Leadless Chip Carrier
(Square 0.350, Hermetic)

Proprietary Device Prefixes

LS

E

E

LT
LTC

LFLP
LH MF
LM

AD

i

I
I
I

14-3

PACKAGE CROSS REFERENCE
PACKAGE OUTLINE

q0
q0
q0

..
if

.~..
- ...
....
.....

Clrrm

a..J:

:fl...
ii:

c:J
I :: :

~~
e~

:

.5

.,.!:
;;

.,.E

c:J

~

-

ClmDi

Q~
""<:'
N

C>

I-

~

"-

~~~~~~
~ ~~

;

~

'!'

I:!

NSC

M

-

5-Lead Plastic DD Pak

PMI

TI

LlNFIN

MAXIM

I

-

-

-

-

-

Q

-

-

-

-

-

-

-

-

-

-

-

-

~

mQ

I

I
I

?-Lead Plastic DD Pak

R

-

-

8-Lead PDIP, Plastic Dual-In-Line

N8

N
N8

N

;

P

PI

P

M

P

14-,16-,18-,20- and 24-Lead
PDIP, Plastic Dual-In-Line
(Narrow 0.300)

N

N
N14

N

I

P

P2

N
NE

N

ND, NE, NN,
NP, NG

-

N

P

P

N

-

PI

-

-

-

-

K

D

0

-

SA

0

0

-

SO
SE

0

0

-

WE,WN,
WP,WF
WG,WI

-

-

-

-

UR

-

T

-

KC
KV

P
P

C
C

-

-

-

-

C

I
I

Head Plastic TO-3P
(Similar to TO-247)

I
I

NW
P

-

--

I
I
I
I
I
I

8-Lead Plastic SO
(Narrow 0.150)

S8

M

R

14- and 16-Lead Plastic SO
(Narrow 0.150)

S

M

R

16-,18-,20-,24- and 2R-Lead
Plastic SO (Wide 0.300)

SW

M

R

3-Lead Plastic SOT-223
Small Outline Transistor

ST

-

-

I S08
I
I S014
I S016

I
I S016
I S018
S020
I S024
I S028
I
I
3- or 5-Lead Plastic TO-220

T
T

T
T

-

-

I
I

?-Lead Plastic TO-220
(Formerly Y Package)

T7

-

-

I
I
I

I
10-Lead Flatpak, Glass Sealed
(Hermetic)

W

W

10- or 14-Lead Flatpak, Metal
Sealed, Bottom Brazed
(Hermetic)

WB

F

3-Lead, Plastic TO-92 Package

Z

Proprietary Device Prefixes

L

I

RC

I
AH-148I OH-148
LM
Z

F

-

-

F

FB

W010
W014

-

M

P

LP

-

ZR

MC

TL

LX
SG

MAX

I

-

U010

I
I
LT
LTC

LF LP
LH MF

LM

14-4

AOI/PMI

-

~

--=N

LTC

I

28-Lead PDIP, Plastic Dual-In-Line
I[(,~~L,U,I~,.Ji~/·,u!·I"? (Wide 0.600)

~ ~
0

0:;;

WVWW

DESCRIPTION
3-Lead Plastic DD Pak

AD

I OP
I REF
I CMP

f""-LlneJ\~D~

~,

TECHNOLOGY

__

PA_CK_A_GE_D_IM_EN_SI_ON_S

08 Package
8-Lead Side Brazed (Hermetic)
(LTC DWG #05-08-1210)

0.290
(7.366)
~TYP

PIN NO.1 _
IDENT

~T""T":'T''"'T''':'''r"I~

0.020 - 0.060
(0.508 - 1.524)~

a
,

..i:;:::;;:;:;;;:;:::;;::;:;i

(0.203-0.381~1

l--

0.300
(7.620)
REF

L
11=

1--+

0.125 0.054 j~
0.100!0010
(3.175) (1.372)- (2.54LO.254)
MIN
TYP
0.015 - 0.023
(0.381 - 0.584)
os 0695

oPackage
14-Lead Side Brazed (Hermetic)
(LTC DWG # 05-08-1210)

0.290
(7.366)
TYP

~~~~~~J.
0.020 - 0.060

~
~
I .
0.300

I

I--- (7.620)REF

1

0.485,
(12.319)
MAX

0.165
(4.191)
MAX

(0.508 -1.524;..)=~===;:;===::::;:I:=::1-t

~_j[0'054
(3.175)
MIN

(2.540 ± 0.254)
0.015 - 0.023
(0.381 - 0.584)

(1.372)
TYP
0140595

14-5

PACKAGE DIMENSIONS
D Package
16-Lead Side Brazed (Hermetic)
(LTC DWG # 05-08-1210)

0.290
(7.366)
TYP

..............................-T"""r""'..-.-.-...,...,....,~...,......~

r--

~
~

0.300
I
I- - (7.620)---1

REF

a

I

0.485

0.165

'1'

1:: ::
1

0.125
(3.175)
MIN

1--1.

d'j I~IL

I 0.054

0.100±0.010
(2.540 ± 0.254)
0.015 - 0.023
(0.381 0.584)

(1.372)
TYP

DPackage
18-Lead Side Brazed (Hermetic)
(LTC DWG # 05-08-1210)
0.910
(23.114)

MAX

-t
0.290
(7.366)
TYP

~~~~~~~~

r------ ~
0.485

0.165
(4.191)

~~T~j
~
~
I

.

0.300

I

I -(7.620)---1
REF

14-6

0.125
(3.175)
MIN

1--.+

~Jt~

0.100+0.010
(2.540 ± 0.254)
0.015 - 0.023
(0.381 0.584)

0.054
(1.372)
TYP
0180895

PACKAGE DIMENSIONS
D Package
20-Lead Side Brazed (Hermetic)
(LTC DWG #05-08-1210)
1.010
(25.654)
MAX

r

0.290
(7.366)
TYP

~~~~~~~~~

r---

0.485

0.165

-----J

(4191)

I::::i~i

~ 1 . 'oou....
u

~
I .
I

~t
---II--

0.300

~ (7.620) ----I

(2.540 ± 0.254)

(3.175)
MIN

REF

0.015 - 0.023
(0.381 0.584)

::

(TvP)

""695

F Package
20-Lead Plastic TSSOP (0.173)
(LTC DWG # 05-08-1650)

rrn

0.252 - 0.260'
(6.40 6.60)

2019181716151413

I
RRt---.1

T
0.246 - 0.256

o
1 2 3 4 5 6 7 8 9 10

I

(4.30-4.48)

idI{
t

0.043
(1.10)
MAX

_O.169-0.176'~1

0.0035 - 0.0071
(0.09 - 0.18)

0.020 - 0.028
(0.50 - 0.70)

r_ oot

-I9I-- t

'DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

€iiiiiiiiiiirii-f1
IL

~~~~f ~ 1BSC

0.007-0.012
(0.18-0.30) -

0.002 - 0.006
(0.05-0.15)

""TSSOPC895

14-7

PACKAGE DIMENSIONS
GPackage
16-Lead Plastic SSOP (0.209)
(LTe DWG # 05-08-1640)

~

0.239-0.249"_+--.
(6.07 - 7.33)
16 15 14 13 12 11 10 9

1

0.301 - 0.311

o

"'TOOl

12345678
__ 0.205 - 0.212"
(5.20 - 5.38)

0.068 - 0.078
(1.73-1.99)

0'-8'

t

0.022-0.037
(0.55 - 0.95)

I I~

-I

r-

b'---uO~D-~O~O-~O~O-uDudJ
~OO~~~ ~ ~ IL t
BSC

"DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.002 0.008
(0.05-0.21)

0.010-0.015 _
(0.25 - 0.38)

GPackage
20-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)

~

0.278-0.289"_+--.
(7.07 - 7.33)
20 191817 16 15 14 1312 11

1

T

0.301 - 0.311

o
1 2 3 4 5 6 7 8 9 10
__ 0.205-0.212"
(5.20 - 5.38)

0'-8'

t

0.022-0.037
(0.55-0.95)

I I~

-I

r-

"DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH.INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

14-8

0.0256~
~
(0.65)
BSC

0.010-0.015 _
(0.25 - 0.38)

IL

0.002 - 0.008
(0.05 - 0.21)

PACKAGE DIMENSIONS
GPackage
24-Lead Plastic SSOP (0.209)

I"

'h

(LTC DWG # 05-08-1640)

0.318-0.328"
(8.07 8.33)
24 232221 20 19 18 17 16 15 14 13

1
~r~

0.301 - 0.311

o
1 2 3 4 5 6 7 8 9 10 11 12
__ 0.205-0.212"~
(5.20 - 5.38)

0' _8'

0.022-0.037
(0.55 - 0.95)

_I

+
I

r-

t

0.0256
(0.65)
SSC

II

-I ~

"DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
""DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.010-0.015 _ _
(0.25 0.38)

GPackage
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)

I"

0.002 - 0.008
(0.05 - 0.21)

'h

0.397 - 0.407"
(10.07 10.33)
28 27 26 25 24 23 22 21 20 19 18 17 16 15

1

T
0.301 - 0.311

o
1 2 3 4 5 6 7 8 9 10 11 12 13 14
__ 0.205 - 0.212"
(5.20 - 5.38)

0.068 - 0.078
(1.73-1.99)

0'-8'

+

0.005 - 0.009
(0.13 0.22)

~

"DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
""DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

fr@1Il@lD"D"@"QJJ]~
~oO~~f -I 1- II
t
SSC

0.010-0.015 _
(0.25 - 0.38)

_

0.002 - 0.008
(0.05-0.21)

G2fI SSOP 0894

14-9

PACKAGE DIMENSIONS
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)

1-- (~:~~~-~:!~; I
rl161514131211

~~I

I

r

0.229 - 0.244

"T~
1

0.0075-00098
(0.191

,..----<.\\'"

0.015 ± 0.004 45'
(0.38 ± 0.10) x

:C

0.004 - 0.009
(0.102-0.249)

tt66666666lJ
-I ~ -I ~ t

0'i8'TYP

0.016-0.050
(0.406 1.270)

12345678

0.053 - 0.069
(1.351-1.748)

LjJ~(~~~~1'1\~

f=11-

0.150 - 0.157"

0.008-0.012
(0.203 - 0.305)

0.025
(0.635)
BSC

• DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
•• DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.01 O· (0.254mm) PER SIDE

GN16(S50P)0895

GN Package
20-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)

-.-----t

l

0.229 - 0.244

r·"'" "", ,. "", -,
(~:~~~ =~:~~~;

.

0.150-0.157"
(3.810 - 3.988)

'"'T' ' ~~~~
_11_

2 3 4 5 6 7 8 9 10
0.015 ±0.004 x 45'
(0.38 ± 0.1 0)

J§~~~5?~\\ O'i8' TYP
L:j(
1~

0.0075 - 0.0098
(0.191

q I.-

0.016-0.050
(0.406 -1.270)

• DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006' (0.152mm) PER SIDE
•• DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

14-10

0.053 - 0.069

_,,,::

0.004 - 0.009

"l~T~
"-"'

..

0.008 - 0.012

0.025

t

BSC

QN20(SSOP)0895

PACKAGE DIMENSIONS
GN Package
24-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)

11-

1 2 3 4 5 6 7 8 9 10 11 12
0.015±0.004x45°
(0.38±0.10)

0.0075 - 0.0098 jE~~~~?~i\ 0°-48° TYP
(0191-C)

J-'!:::,

~II_ 0016-0.050
, --I
(0.406 -1.270)

0.053 - 0.069

0.004 - 0.009

""~j"~
0.008 - 0.012
(0.203-0.305)

~

t

0.025
BSC

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006' (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

GN24(SsoPj0595

GW Package
36-Lead Plastic SSOP (Wide 0.300)
(LTC DWG # 05-08-1642)

h

0.602-0.612*
(15.290
-15.544)
•
363534333231 302928272625242322 21 20 19

0.400 - 0.410

IL;: ;0:;: ;:;:;: ;:;:;: ;:;:;: ;:;:;: ;:; : ;:;:;: ;:;:;: ;:;:;:;:;:;:;:;:;:;:;:~ ,".'M["''''

G

(7:;i~7. ~:r;J-

0.010 - 0.016 x 450
(0.254 - 0.406)
-

r-+

0.009-0.012
(0.231 - 0.305)

0.024 - 0.040
(0.610-1.016) -

I

1 2 3 4 5 6 7 8 9 1011 12131415161718
0.097-0.104
(2.463 - 2.641)

0.090-0.094
(2.286 - 2.387)

l~~
j I.- IL

0.031
0.012-0.017
(0.800)
(0.304-0.431)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
SHALL NOT EXCEED 0.006' (0.152mm) PER SIDE
FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

0.005-0.012
(0.127 0.305)

14-11

PACKAGE DIMENSIONS
GW Package
44-Lead Plastic SSOP (Wide 0.300)
(LTC DWG # 05-08-1642)

0.400-0.410
(10,160-10.414)

~:;::;:;::;::;:;;::;::;::;::;:;::;:;::;::,::;:u

IL;::;:;:;:0

G

(~':;i~~:~~r;}

0,010 - 0,016 x 45"
(0,254 - 0,406)
-

lJ
0,00911:125
(0,231 - 0,3175)

0,024 - 0,040
(0,610 - 1.016)

1 2 3 4 5 6 7 8 9 10111213141516171819202122

I

0,097 - 0,104
(2,463 - 2,641)

0,090 - 0,094
(2,286 - 2,387)

~MJlllJIJLOAOoOuOJlPooJ3J
j I IL

"
_Ii-=+'
I-I

0,031
0,012-0,017
(0,800)
(0,304-0.431)
TYP
'DIMENSION DOES NOT INCLUDE MOLD FLASH, MOLD FLASH "DIMENSION DOES NOT INCLUDE INTERLEAD FLASH, INTERLEAD
SHALL NOT EXCEED 0,006" (0,152mm) PER SIDE
FLASH SHALL NOT EXCEED 0,010' (0,254mm) PER SIDE

0,005-0,012
(0,127-0,305)

H Package
8-Lead TO-5 Metal Can (0.200 PC D)
(LTC DWG # 05-08-1320)
-

0,040
(1.016)
MAX

0,335 - 0,370
(8,509 - 9,398)
DIA
I- 0.305 - 0.335
I (7.747=8.509)

1 +--------.-0,165 - 0,185
(4,191-4,699)

L

~
="",~:-:-_~:~,~_~:~~-~:--Gp-ALA-UNG-EE---+f!
f~'

SEATING
PLANE

0,010-0,045'
(0,254 -1 ,143)

00 0 00

~

I--

(12.700-19,050)
--------',0,016 - 0,021"
(0.406 - 0,533)

,/ >
A

45"TYP

REFERENCE
- - - PLANE
0,500 - 0,750

0,027 - 0,045

A-\:--../
,L.-(0.686-1.143)
0,027 - 0.034 / ' "
(0.686 - 0.864)

'LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0,045" BELOW THE REFERENCE PLANE
"FOR SOLDER DIP LEAD FINISH LEAD DIAMETER IS 0.016- 0,024
,
(0,406 - 0,61 0)
H8(T0-5) 0.200 PCD 0595

14-12

PACKAGE DIMENSIONS
H Package
a-Lead TO-5 Metal Can (0.230 PCO)
(LTC DWG #05-08-1321)

- (~:~~~=~:~~~)
~
DIA
I- 0.305 - 0.335
I (7.747=8.509)

1
0.050

I (1.270)
0.165-0.185
L
MAX
(4.191-4.699)
~ r:;;:;;;;:::;::::;;;;:~--,tL.------t~--- ~t.:~~ENCE
I

SEATING
PLANE

0.040
(1.016)
MAX

t

0.010-0.045'
(0.254 -1.143)

F-hll-..-W---WW---.,-

00 0 00

--I k-

~~~f

0.500-0.750
(12.700-19.050)

0.016 - 0.021"
(0.406 - 0.533)

*

'LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045" BELOW THE REFERENCE PLANE
"FOR SOLDER DIP LEAD FINISH LEAD DIAMETER IS 0.016 -0.024
,
(0.406 - 0.610)
H8 (TD-S) 0.230 PCD0595

H Package
10-Lead TO-5 Metal Can
(LTC DWG # 05-08-1322)

0.165-0.185
(4.191 - 4.699)

=:"11,,~:-=-::-,-=-~:,:-=-~'-:'~~-Gp-ALAU-NG-EE---:ll'---~~!fu~ENCE
0.500 - 0.750
~"

(12.700 -19.050)

*

'LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045' BELOW THE REFERENCE PLANE
"FOR SOLDER DIP LEAD FINISH LEAD DIAMETER IS 0.016 - 0.024
,
(0.406-0.610)
H10(TO-5}0595

14-13

PACKAGE DIMENSIONS
H Package
Head TO-39 Metal Can

(LTC DWG # 05-08-1330)

(LTC DWG # 05-08-1331)

~:~:;~i::it*~
(t;)Q

-- (~:~~=~:~;~)

0.050

(k~~)

0.165-0.185

L

~(4.191_4.699)

L

REFERENCE

b

H Package
3-Lead TO-39 Metal Can

PLANE~

REFERENCE

PLANE~

•

000
I.-

0.016-0.019·~
(0.406 - 0.483)
DlA
0.200
(5.080) lYP

0.500
(12.700)
MIN

I- 0.305 - 0.335
I (7.747 - 8.509)

Q o:J
1

0.165-0.185
(4.191-4.699)

----.-L

00

0.016-0.019·:....11.(0.406 - 0.483)
DlA
0.200
(5.080)
lYP --t-<--~
_

0.500
(12.700)
MIN

H4(TO·39)0895

H3[T0-39)G5lI5

'LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045" BELOW THE REFERENCE PLANE
"FOR SOLDER DIP LEAD FINISH LEAD DIAMETER IS 0.016 - 0.024
,
(0.406 - 0.610)

'LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045' BELOW THE REFERENCE PLANE
"FOR SOLDER DIP LEAD FINISH LEAD DIAMETER IS 0.016 - 0.024
,
(0.406-0.610)

H Package
Head and 3-Lead TO-46 Metal Can

H Package
Head TO-46 Metal Can

HPackage
3-Lead TO-52 Metal Can

(LTC DWG # 05-08-1340)

(LTC DWG #05-08-1341)

(LTC DWG # 05-08-1350)

0.209 - 0.219
(5.309-5.537)F
0.178-0.195
(4.521-4.953)
0.015
0.500 (0'381)~
(12.700) MAX

- I;

---I
I

PLANE

T
0.500
(12.700)
MIN

I
•
_J-

o00

0'209_0'219~
(5.309
- 5.563)
0.178-0.195
(4.521 - 4.953)«

0.085-0.105
(2.159-2.667)

REFERENCE
PLANE

0.025

0.209 - 0.230

"I

~

-.l
•

000

(~~i)

0.016-0.019·.:....11.(0.406-0.483)
DIA

0.085-0.105
(2.159 - 2.667)

0.025

_0 0 0
_

lYP

FOR 3-LEAD PACKAGE ONLY

'LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045' BELOW THE REFERENCE PLANE
"FOR SOLDER DIP LEAD FINISH LEAD DIAMETER IS 0.G16-0.024
,
(0.406 - 0.610)

14-14

+
0.025

(~~)

f.4

-(~:~~~)

0.036 - 0.046
(0.914 -1.168)

•

0.016 - 0.019".:....11.(0406D1 83)

il

0.036 - 0.046
(0.914-1.168)

...l

(1ijmO)
REFERENCEt
PLANE
-

(~~)

0.016 - 0.019·.:....11.(0.406D 483)

0.100
(2.540)
lYP

(5.309_5.842):A
0.115-0.150
0.178 - 0.195
(2.921 - 3.B1 0)
(4.521-4.953) ~
0.500

0.036 - 0.046
(0.914 -1.168)

0.050
(1.270)
lYP

PACKAGE DIMENSIONS
J8 Package
8-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0405

CORNER LEADS OPTION
(4 PLCS)

f
,
,

I I
0.045 - 0.068 ----I I-(1.143 -1.727)
FULL LEAD
OPTION

~_~[(1~~7)r-

0.023 -0.045
(0.584-1.143)
HALF LEAD
OPTION

(0127)
MIN

8

7

6

-,

0.220-0.310
(5.588 -7.874)

~..."..,......,~Ll

0.200
(5.080)

MAX

0.045 - 0.068
(1.143-1.727)

Jt

I

_

0.014 - 0.026
(0.360 - 0.660)

0125
3.175
0100±0.010 MIN
(2.540 ± 0.254)

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.

J Package
14-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)

CORNER LEADS OPTION
(4 PLCS)

~
:
,

0.045 - 0.068
(1.143-1.727)
FULL LEAD
OPTION

--II I__

0.023- 0.045
(0.584 1.143)
HALF LEAD
OPTION

0.785
(19.939)
MAX

0.005 _
(0.127)
MIN

0.025
(0.635)
RADTYP

-t
0.220 - 0.310
(5.588 - 7.874)

"-r-r-r--r~..,......,--,--T"""""T""' -~

0.300 BSC

~(~);l

1_ 0.385 ± 0.025 -.J
(9.779 ± 0.635)

J1l ---i

0.045-0068
(1143-1727)-

0.014 - 0.026
-(0.360 - 0.660)

I

0.100±0010
i--(2.540± 0 254)

0.200
(5.080)
MAX

0.125
(3.175)
MIN
J140694

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS.

14-15

PACKAGE DIMENSIONS
J Package
16-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-111 0)
0.840

CORNER LEADS OPTION
(4 PLCS)

!
I
I

II

0.045-0.068_
(1.143-1.727)
FULL LEAD
OPTION

0.005
(0.127)MIN

0.023-0.045
(0.584 1.143)
HALF LEAD
OPTION

(21.336)~
MAX

1

-

13

12

11

10

9

-t
0.220 - 0.31 0
(5.588 - 7.874)

"-r.r--~.,.....,.-:-r"T":"'T"""~rT"'T"'""'U

_

0.200
(5.080)

::::~d---I

I--- 0.385+0.025

(9.779±0.635)

o";_o~~i
:U

r: :
c= jl_

(0.

380

0.125
(3175)
MIN

0.045-0.068
(1.143-1.727)
0.014 - 0.026

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS

I

I

0.100±0.010

~(2.540±0254)

-

-(0.360 - 0.660)

J16"",

J Package
18-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
CORNER LEADS OPTION
(4 PLCS)

!
:

I I
0.045 - 0.068 --I ~
(1.143 -1.727)
FULL LEAD
OPTION

0.023 -0.045
(0.584 -1.143)
HALF LEAD
OPTION

0.005 __
(0.127)
MIN

0.025
(0.635)
RADTYP

(~4936~4)~
1_
C
MAX

18

17

16

15

14

13

12

11

10

1

0.220 - 0.31 0
(5.590 - 7.870)

~~~~U
0.200
(5.080)
MAX

0.015 - 0.060
(0.380 - 1.520)

I-::=--==--C=--==--==--==--C=--==--=-U

-.~

I--

0.100±0.010
(2.540 ± 0.254)

J1B0694

14-16

PACKAGE DIMENSIONS
J Package
20-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05·08-1110)

'f

1.060
(26.924)
MAX

CORNER LEADS OPTION
(4 PLCS)

0.023-0.045
(0.584-1.143)
HALF LEAD
OPTION

:
,

I I_
0.045 - 0.068 --I
(1.143 -1.727)
FULL LEAD
OPTION

---------1'1

0.220 - 0.31 0

I--

0.005

0.200

~~

~~

r
""""'"~nMAX

(0.381

I---

1

0.12~

_I

0.385 ± 0.025
(9.779 ± 0.635)

.524)

(3.175)
MIN

III

-:to.045-0.068
(1.143-1.727)
0.014 - 0.026
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.
(0.356 - 0.660)

I I 0.100±0.010
1---1-- (2.540 ± 0.254)
J200694

J Package
24-Lead CERDIP (Narrow 0.300, Hermetic)
(DWG # 05-08-1110)

1

' 0 - - - - - - - - - - 1.290
(32.77)
MAX

CORNER LEADS OPTION
(4 PLCS)

t

-.-------

,
,

0.045-0.068 _
(1.143-1.727)
FULL LEAD
OPTION

I I_

I

0.22010.310 0.025
(5.588 -7.874) (0.635)
~
RAD TYP

1
0.300 BSC

-

Lb

0.023- 0.045
(0.584-1.143)
HALF LEAD
OPTION

(ii762BsC)

I

;l

0.005
-(0.127)
MIN

0.015 - 0.060
(0.381 -1.524) .....,,=--==;--=,.---;o=--==;--=,.---;o=--=~=,---;==--=~=c-I

-~

0' -15'
~

I

0.385 ± 0.025

I

I--- (9.779 ± 0.635)-----1

0125
(3175)

1

--

MIN
NOTE LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS - -

t

0045-0068
---(1143-1727)

I I 0.100±0.010
1---1-- (2.540 ± 0.254)

0014 - 0.026
(0360 - 0.660)

14-17

II

PACKAGE DIMENSIONS
JW Package
28-Lead CERDIP (Wide 0.600, Hermetic)
(LTC DWG #05-08-1120)
1.490
- - - - - - - - - (37,85) - - - - - - - - -

CORNER LEADS OPTION
(4 PLCS)

,

I I
0,045 - 0,068:-----1 I-(1,143-1.727)

F~~T~:D

MAX

(~,~ !=~,~:~)
HALF LEAD
OPTION

"

0,025
(0,635)
RAD TYP

0500-0.610
(12.700-15.494)

MAX

0,225
(5.715)
MAX
0015-0075IT

I- + - - - -

I

0,685 +0,025
~ -------.
+0,635)
(17,40 -1.524

'~r'Qr rrrMrrrrrrrrr
~ t~,: : : : ~:::
::::,
MIN

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS,

I-J-

I

0005
(0 127)
MIN

--

:;:,

0014-0,026
(0,360 - 0,660)

KPackage
Head TO-3 Metal Can
(6omil Diameter Leads)

KPackage
2-Lead TO-3 Metal Can
(LTC DWG # 05-08-1310)

(LTC DWG # 05-08-1312)
0,320 - 0,350

.'~~=======;=========(~~::~::'
0,420 - 0,480
(10,67-12,19)

t

0,320 - 0,350

'r~=======;========(~~::t,
0,420- 0.480
(10,67 -12,19)

-I ~ (0,965
0,038 - 0,043
-1.09)

t

0,151- 0,161
(3,86 - 4,09)
DlA,2PLCS

-I ~ 0,058
- 0,062
(1.47-1.57)

0,151-0,161
(3,86 - 4,09)
DlA, 2 PLACES

K2(T0-3jOll9O

I<2(TO-3}Il895

14-18

PACKAGE DIMENSIONS
KPackage
Head TO-3 Metal Can
(LTC DWG # 05-08-1311)
0.320 - 0.350

(8'13t8'89)C========;~~=====(:J~:~~~~:~~)

t

T

0.420 -0.480
(10.67 -12.19)

t

-i /.- (0.965
0.038 - 0.043
-1.09)

0.151-0.161
(3.84 - 4.09)
DIA 2 PLC
0.167-0.177
(4.24 -4.49)
R

K4(TW)0695

L Package
20-Pin Leadless Chip Carrier (Rectangular, Hermetic)
(LTC DWG # 05-08-1250)
__ 0.060 - 0.075
(1.524 -1.95)

(~:~~~) x 45' 3PLCs

__ 0.050 - 0.065
(1.270 -1.651)

REF

o.420

(-10.668)
MAX

0.420 - 0.440
(10.668 -11.176)

TOP

f---. 0.280
(7.112)
MAX

___
L20(ReC)0694

14-19

PACKAGE DIMENSIONS
LS Package
20-Pin Leadless Chip Carrier (Square 0.350, Hermetic)
(LTC DWG#05-08-1260)

r-

0.064 - 0.090
(1.626 - 2.286)

___ 0.054 - 0.076
(1.371 - 1.930)

0.300 ± 0.004 -3-t----TOP-----H;.(7.62 ± 0.102)
SQ.

1..20(80)07115

MPackage
3-Lead Plastic DD Pak
(LTC DWG # 05-08-1460)
0.060
(1.524)
TYP

t-(~-0.415

4

U-10.541)

1

D
t=J-

--.--.------I-;====='t
*
WTYP

0.300
-- (7.620) --

BOnOM VIEW OF DO PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAK SINK

0.143+ 0.012
-0.020

(3632~~:~~~)

L-i
~

I--

0.050

0.203 )
(0102+
. -0.102

-*0.090-0.110
(2.286 2.794)

(1.270)
TYP

LltDJl1

14-20

0.004 ~~:~~~

0.059
(1.499)
TYP

0.330-0.370
(8.382 - 9.398)

IlL 0.050±0.012

0013-0023
(0:330 0:584)--11--

(1.270 ± 0.305)
M(DD3)0895

PACKAGE DIMENSIONS
N8 Package
8-Lead POIP (Narrow 0.300)
(LTC DWG # 05-08-1510)

~ (100~06~; ~
MAX

I

8

7

6

5

0.255 ± 0.015'
(6.477 ± 0.381)

L~~~
S-

0.065

~

(1.651)

TYP

0.005

I

I--

(O~I~)

0325 +0.025
I
. -0.Q15----..J
+0.635)
(8255
. -0.381

0.100±0.010
(2.540 ± 0.254)

LI Jl

0.018±0.003
(0.457 ± 0.076)

'THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.Q1 0 INCH (0.254mm)

N Package
14-Lead PDlP (Narrow 0.300)
(LTC DWG # 05-08-151 0)
0.770' - - - - -...
(19.558)

I

MAX

-t

11

0.255 ± 0.015'
(6.477 ± 0.381)

L~;=;;;;:;=~~~
0.130±0.005

(:~:I:' '1' '" I==r---.=----.==r--.=.--=,-.=I-~=r__.=l ~
MIN

I_

0325
+0.025 __
.
-0.015

TI~

I

0.005
_
(0.125)
MIN
0.100±0.010
(2.540 ± 0.254)
'THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
+0.635)
(8.255 -0.381

0.125 - (3.175)
MIN

LII

(~:~~~)
TYP

~ -(0:457:0:076)
0018

0003

N14069.

14-21

PACKAGE DIMENSIONS
NPackage
16-Lead PDlP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770"
..
·-----(19.558)

------.

I

MAX

1

1

0.255 ±0.015"
(6.477 ± 0.381)

L~~~~~;?
~

____-+--I----,l
1

0.065
(1.651)

TYP

_II.-

-

"THESE DIMENSIONS 00 NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.018±0.003
(0.457 ± 0.076)
N16D695

NPackage
18-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.900"

1 - - - - - - - (22.860) - - - - - - 1
MAX

0.130 ± 0.005

(3.302~~________________~~____~1

1J

1

~5~

(0~~1)
I

k-

0 325 .0.025
I
. -0.015--1
+0.635)
(8.255 -0.381

0.125

~~

(~:~~~)
~

JL

0.100 ± 0.010
(2.540 ± 0.254)
"THESE DIMENSIONS 00 NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

14-22

MIN

-

-II.-

(~:~:~)
TYP
0.018±0.003

~ill±~~

PACKAGE DIMENSIONS
N Package
18-Lead PDIP Isolation Barrier (Narrow 0.300)
(LTC DWG # 05-08-1590)
0.900'
- - - - - - (22.860) - - - - - MAX

0.255 ± 0.015'
(6.477± 0.381)

L~;;;;;;;;;==~~~
0.130 ± 0.005

0.045 - 0.065 _
(1.143-1.651)

I

~---------rr-~i

t0.065
(1.651)
TYP
0.100 ± 0.010
(2.540 ± 0.254) -

I

I _11_
~

0.018 ± 0.003
(0.457 ± 0.076)

'THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N Package
20-Lead PDlP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.040'

1 - - - - - - - - (26.416) - - - - - - - - - + 1
MAX

0.255 ± 0.015"
(6.477 ± 0.381)

L~~~~~~~
0.130 ± 0.005
(3.302 ± 0.127)
0.Q15

(OJI~l)
0 325 +0.025
I
k-- . -0.Q15---1
+0.635)
(8.255 -0.381

~

£.--------1-1-----, t

'±1

I

0.125
(3.175)
MIN

-

0.005

(O~I~)

J L-JL

(~:~~~)
TYP

0.01B±0.003
(0.457± 0.076)

0.100±0.010
(2.540 ± 0.254)

'THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

14-23

PACKAGE DIMENSIONS
N Package
24-Lead PDlP (Narrow 0.300)
(LTC DWG #05-08-1510)
1.265·

r

· I - - - - - - - - - - (32.131) - - - - - - - - - - 1
24

I

0.255 ± 0.015·
(6.477 ± 0.381)

~~~~~~~~~
0.300 - 0.325

---j

rr(7.620-8.255\

I

fL~
1(~0.2 9-0.381\) +J

0.130 ± 0.005

~:.::~!lT~I=r--.=,,---.=r...,,=r-"""'---.=r-.=r-i=r-.==r--.=r--.=r""""---.=I ~

0.325 ~~:~~~

0.125
(3.175)
MIN

0.005
(0.127)
MIN

(1.651)

JL

TYP

~III--- 0.018 ± 0.003
(0.457 ± 0.076)

+0.635)
(8.255 -0.381

0.100 ± 0.010
(2.540 ± 0.254)
'THESE DIMENSIONS 00 NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N2>41l895

NW Package
28-Lead PDlP (Wide 0.600)
(LTC DWG # 05-08-1520)

0.505 - 0.560'

L

(12.827

1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;=;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;=;;;;;;;;;;;;;;;;;;;;;;;;;;1

0.150 ± 0.005
(3.810 ± 0.127)
0.Q15

(~:~~:=~:~~~)
~

+0.025
0.625-0.015
+0.635)
(15.87 -0.381

-...J

(0~~1)

±=t[ J L.jl-

£b--=,......,=--=---.::r-=--=,........,=--=,..--,=--=---.::r-=--=,........,o=I t

(~~~)

.

0.125
(3.175)

MIN
'THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

14-24

-.1

0.005,
(0.127,
MIN
0.100 ± 0.010
(2.540 ± 0.254)

0.018 ± 0.003
(0.457 ± 0.076)

PACKAGE DIMENSIONS
P Package
3-Lead Plastic TO-3P (Similar to TO-247)
(LTC DWG # 05-08-1450)

0.275
(6.985)

I

0.580
(14.732)

j

1

r

0.700

17
(

r=

0.830 - 0.870
(21.08-22.10)

r

0.620-0.640 - - (15.75-16.26)

I

0.060 - 0.080
(1.52 - 2.03)

MOUNTING HOLE
0.115-0.145
(2.92 - 3.68)
OIA

I

0.580 - 0.600
(14.73-15.24)

EJECTOR PIN MARKS

'1-----'+11-

~21~~=~~~:
DIA

0.170
(4.32)
MAX
0.780 - 0.800
(19.81-20.32)

0.215
-(5.46)
BSC

J

0.087 - 0.1 02
(2.21 - 2.59)
0.020 - 0.040
(0.51-1.02)

Q Package
5-Lead Plastic OD Pak
(LTC DWG # 05-08-1461)
0.060
(1.524)

NP

i
0.004 ~~:~~~
0.203 )
(0102+
. -0.102

0.300
-- (7.620) --BOTTOM VIEW OF DD PAK
ITCHED AREA IS SOLDER PLATED
COPPER HEAK SINK

0.143 ~~:~~~

0013-0023
IlL 0.050±0.012
(0:330 _ 0:584) -II--- (1.270 ± 0.305)

0.305 )
(3632+
. -0.508
Q(D05) 0695

14-25

PACKAGE DIMENSIONS
RPackage
Head Plastic DD Pak
(LTC DWG # 05-08-1462)
0.060
(1.524)
lYP

+

t

0.004 ~~:~~~

0.330 - 0.370
(8.382 9.398)

0.203 )
(0102+
. -0.102

0013-0023
IlL 0.050+0.012
(0:330 _ 0:584) ~ I-- (1.270 ± 0.305)

0.300
-- (7.620) -BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAK SINK

R(007) 0695

lilloooool
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)

rfi
8

0'189-0'197'~

(4.801

5.004)

7

6

5

I

0.228-0.244
(5.791-6.197)

0.010-0.020
(0.254 _ 0.508) x

45°1

LJ I

0.008 - 0.01 0
(0.203

t=I

1-0.016-0.050
0.406 -1.270

~

r

~
1

nn

0.053 - 0.069

J ~jlYP
1

'DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006' (0.152mm) PER SIDE
"DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

14-26

0.150-0.157"
(3.810-3.988)

(1.346 -1.752)

CJ CJ t::J

0.014-0.0:
(0.355 - 0.483)

d

T T

0.004 _ 0.010
(0.101

0.254)

~

0.050

---I I-- 1---+1- (1.270)
BSC

f
6080695

PACKAGE DIMENSIONS
S Package
14-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.337-0.344'
(8.560-8.738)

~
~
R RI
r~~1..-...I...I...1
•

14

13

12

11

11

0.228-0.244
(5.791-6.197)

0.150-0.157"
(3.810-3.988)

Ll

0.010-0.020 4 5 0 l i
(0.254 _ 0.508) x
0.008-0.010

0.053 - 0.069
(1.346 1.752)

r------..

f~

'1 y'"

""[11
D

~

U

0.004-0.010

W W Ert:::rt=n~

g(0.101-0.254)

O.OlH.O~-J=l- Uo.057 = =

LO.016-0.050
0.406 1.270

(0.355 - 0.483)

~

t

(1.270)

TYP

'DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

S Package
16-Lead Plastic Small Oulline (Narrow 0.150)
(LTC DWG # 05-08-161 0)
0.386 - 0.394 '

1-------(9.804-10.008)~

...---+

13

12

R R RI

I

0.228-0.244
(5.791-6.197)

0.010-0.020 x 45°---!
(0.254 - 0.508)

I

0.008 - 0.01 0

"'"L:n 1

t l I 0.016-0.050
-I 1---0.406-1.270

I

0.150-0.157"
(3.810-3.988)

L!-----I~
0.053 - 0.069
(1.346 -1.752)

) ~r

0.004 - 0.01 0
(0.101 - 0.254)

1 6:w=w=t::::::tw J::tw=w:E!
0.014 - 0.019
(0.355 - 0.483)

I I I I 0.050
-I r- r----t- (1.270)
TYP

+

t

S160695

'DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLO FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

14-27

PACKAGE DIMENSIONS
SW Package
16-Lead Plastic Small Oulline (Wide 0.300)
(LTC DWG # 05-08-1620)

~

0398-0413'
(10109 -10 490)

11~

16151413 12

1

0.394-0.419

NOTE 1

1L;:;:;: ;: :;: :;:;:;:;: : ;: :;: :;: ;: ;: ;: ;!cr~

G

0.291 - 0.299"
(7.391 -7.595)

2

4

3

5

6

7

8

0.093 - 0.104
(2.362 - 2.642)

0.010 - 0.029 x 45°--1
(0.254 - 0.737)
I

-+
L

L

00-8°TYP

r

0.009 - 0.013
(0.229 - 0.330)

0.037 - 0.045
(0'::11.143)

t~
0 0 ODD D0 ~2t
~~ ~
~ w~

IL

co co w

(1.2701-.1
1TYP 0.014 _ 0.019

w

0.004-0.012
(0.102 - 0.305)

(0.356 - 0.462) - .
TYP
NOTE:
1. PIN lIDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
-DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSION DOES NOT INCLUDE INTERLEAD FLASH.INTERLEAD FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

SW Package
18-Lead Plastic Small Oulline (Wide 0.300)
(LTC DWG # 05-08-1620)

~
16

0.447-0463(11.354-11760)

17 16 15

14 13

516 (WIDE) 01195

Wh

12 11

10

0.394-0.419

SEE NOTE

~r:;;:n;:;;::o:;;::;;:::c~ "MT~I

G

0'291-0'299"_~

2

(7.391- 7.595)

0.010-0.029 x450--l

~~-um

I

3

4

5

6

7

6

0.093 - 0.104
(2362-2642)

0.037 - 0.045
(0.940-1.143)

..

~

LJ{ ;-',
/Jl~TYP tn 0 0 DO 0 0 0 0 d21
r
~ t ~~-.T l:: ~ ~ ~ ~ W---=r

0.009 _ 0.013
(0.229-0.330)

NOTE 1

0.016 _ 0.050
(0.406 -1.270)

JI

(1.270)
TYP

0.014 -0.019

JL

(0.35~~.462)
NOTE:
1. PIN lIDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
-DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD fLASH SHALL NOT EXCEED 0.006' (0.152mm) PER SIDE
-'DIMENSION DOES NOT INCLUDE INTERLEAD fLASH. INTERLEAD fLASH SHALL NOT EXCEED O.OW (0.254mm) PER SIDE

14-28

0.004 -0.012
(0.102-0.305)

SI8(WIDEjOll95

PACKAGE DIMENSIONS
SW Package
2o-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)

~
20

19 18

0.496-0.512'
(12.598 -13.005)
17 16

15

14

13

12

0.394 -0.419
(10.007 -1 0.643)

NOTE 1

_ _ 0.291_0.299'.;}
(7.391 7.595)
0.010-0.029 x45'--I
~~-~n
I

LJ(
0.0091:13
(0.229 - 0.330)

/JI1

2

4

0093 - 0 104
(2362-2642)

O'-8'TVP

NOTE 1
0.016-0.050
(0.406 -1.270)

5

6

7

8

9

I

10

0.037 - 0.045
(0940-1143)
~

af
11~ D~0012

t~ D~ DD~ DDOD

~ J~l-t ~r--r

Co"

3

t

00

OOh-OO

TYP

00

00

00

(0.102 - 0.305)

0.014-0.019 __

___

(0.3~;;~.482)

.",~~,..,

NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLlEO WITH OR WITHOUT ANY OF THE OPTIONS.
'DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSION DOES NOT INCLUDE INTERLEAD FLASH.INTERLEAD FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

SW Package
24-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)

0.394-0.419

NOTE 1

' 'T' '
0.291 - 0.299"
(7.391 7.595)

~

2

3

4

5

6

7

8

9

10

11

12

0.010 - 0.029 x 450---.j

(0.254 - 0.737)

I

L

r

0.009 - 0.013
(0.229 - 0.330)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
'DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (D.152mm) PER SIDE
"DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

S24(WIDEjOO95

14-29

PACKAGE DIMENSIONS
SWPackage
28-Lead Plastic Small Oulline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 - 0.712'
(17.70-18.08)
28 27

26 25

24

23

22 21

20 19 18

17 16 15

NOTE 1

0.291 - 0.299"
(7.391 -7.595) ; }
0.010-0.029 x 45°_I
(0.254 - 0.737)

NOTE:
1. PIN 1IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
'DlMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
"DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010' (0.254mm) PER SIDE

S28(WIDE)OiI95

SW Package
28-Lead Plastic Small Outline Isolation Barrier (Wide 0.300)
(LTC DWG # 05-08-1690)
0.697 - 0.712"
(17.70-18.08)
18

NOTE 1

17 16

15

0.394-0.419

~;:;: ;: ; :;:;:;: ;:= = : : ;:;:;: ;: ; :;:;:;:;: '~r2

11

3

12 13 14

0.037 - 0.045
(0.940-1.143)

J

Lf1"''''''''''f
0 DDl11f
0.009-0.013
(0.229 - 0.330)

0.014 - 0.019 _
(0.356 - 0.482)

NOTE:
1. PIN 1 IDENT, NOTCH ON TOP ANO CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
"DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLO FLASH SHALL NOT EXCEED 0.006' (0.152mm) PER SIDE
""DIMENSION DOES NOT INCLUDE INTERLEAD FLASH.INTERLEAD FLASH SHALL NOT EXCEED 0.01a' (O.254mm) PER SIDE

14-30

IL

0.004-0.012
(0.102-0.305)

5W28(ISO)0695

PACKAGE DIMENSIONS

fl

ST Package
Head Plastic SOT-223
(LTC DWG # 05-08-1630)

0.248
- 0.264
(6.30-6.71)
0.116-0.124
(2.95 - 3.15)

0.264 - 0.287 ~
(6.71 - 7.29)

I

_1

+___ _
I

..:;:0.;;:;13~0_-0"".1';:C46:=--t+-- _ _ _
(3.30 - 3.71)

I+I

~==r=I=l=:;;:;;::;=~
I

---I

(2.29)

-

0.033-0.041
(0.84 -1.04)

.L

0M

100-16°_1 ;./_ _ _~

"" ~,..----+---"""

(~~) lJic~33

0.010-0.014

~

~~-u~

~~~~~~-1
rI
10 -1;r

0.012
(0.31)
MIN

(0.64 - 0.84)
0.181
(4.60)
NOM

0

--I

ST3(SOT-233)0192

T Package
3-Lead Plastic TO-220
(LTC DWG # 05-08-1420)
0.165-0.180 ~
(4.293 - 4.699)

0.390-0.415 -I4----~
(9.906-10.541)

t
I

t-

",0"".4""60,--",,0.5,,,00,,=-.
(11.684 -12.700)
0.980 -1.070
(24.892-27.178)

D

--I

I

0.045 _ 0.055
1---(1.143-1.397)

0.230 - 0.270
(5.842 - 6.858)

+

'=====I---t.

0.570 -0.620
(14.478-15.748)
0.330 -0.370
(8.382 - 9.398)

i
~

_-+__

0.520 - 0.570
(13.208 -14.478)

l

-.1..

0218-0.252
(5.537 - 6.401)

-I

1::=I t=

0.090-0.110
(2.286-2794)
0.028 - 0.038
(0.711 - 0.965)

1111

0050
(1 270)
TYP

--II-

0.013 - 0.023
(0.330 0.584) ~

0.095-0.115
(2.413 2.921)
T3(TO-22O)0S95

For Lead Bend Options See Page 14-54

14-31

PACKAGE DIMENSIONS
T Package
5-Lead PlasticTO-22o (Straight Lead)
(Nonstandard Flow 06)
(LTC DWG # 05-08-1421)
0.390-0.415
(9.906-10.541)

L

-0

/

. .L-." D
.1

0.147-0.155
(3.734 3.937)
DlA

/

it

~

I

r

!

0.230 0.270
(5.842 - 6.858)

+

0.165 -0.180
(4.293-4.572)

-.---i

(11.684 -12.700)

0.045-0.055

[""-'~

0.570- 0.620
15.748)
0.330 _ 0.370

t "..n-

J

(8.382 9.398)

0.980-1.070
(24.892-27.178)

r

0.520 - 0.570
(13.208 -14.478)

1 --I I- --II..-

0.057 - 0.077
(1.448 -1.956)

--I f--

0.013 - 0.023
(0.330 0.584) ~

0.028 - 0.038
(0.711 - 0.965)

0.095-0.115
(2.413 - 2.921)
T5[TO-220)(STRAIGHT}0695

For Lead Bend Options See Page 14-54
T Package
5-Lead Plastic TO-22o (Standard)
(LTC DWG # 05-08-1421)
0.165 -0.180
(4.293-4.572)

0.147-0.155
0.390-0.415 -+0;------+1' ~ (3.734-3.937)
(9.906 10.541)
DIA

I

)"

D
--t
L
r-(

'r.------I--f'CJ-+

0.460-0.500
(11.684 -12.700)

iI
(:-:C1~C:;:~ =~-=~56~ 8)

0.230! 0.270
(5.842 - 6.858)

0.620
(15.75)

0.330 _ 0.370

0.700 - 0.728
(17.780-18.491)

l! -

t

0.152-0.202
0.260 - 0.320 (3.860 - 5.130)
(6.604-8.128)
---

0.057 - 0.077
(1.448 - 1.956)

J I---I

~

~ (0.711
0.028-0.038
0.965)

1

TYP

J

(8.382 9.398)

0.095-0.115
(2.413-2.921)

0.013 - 0.023
(0.330 - 0.584)
0.135-0.165
0.155-0.195
(3.429 4.191) +o-----\--t- (3.937 - 4.953)
T5[TO-220)0694

For Lead Bend Options See Page 14-54

14-32

PACKAGE DIMENSIONS
17 Package
Head Plastic TO-220 (Straight Lead)
(Nonstandard Flow 06)
(LTC DWG # 05-08-1422)
0.147-0.155
0.390-0.415 +----~V (3.734-3.937)
(9.906-10.541)
/
DIA

D -t

r-{
-.----.i-+--V+-+
.I

t-r

0.460-0.500
(11.684 -12.700)

0.980-1.070
(24.892 _ 27.178)

0.230! 0.270
(5.842 - 6.858)

0.165 -0.180
(4.293 - 4.572)

Fo
....1

__

0.045 - 0.055
(1.143 -1.397)

tI

0.570 - 0.620
(14.478-15.748)
0.330 _ 0.370
(8.382 -9.398)

~

_---'-_ _---L

0.520 - 0.620
(13.208 4.224)

0.040 - 0.060
(1.016-1.524)

--I I.-

~~

0.026 - 0.036
(0.660-0.914)

II

0.013 - 0.023
(0.330-0.584)-:' --

0.095-0.115
-- (2.41 - 2.92)
T7 (STRAfGTI 0695

For Lead Bend Options See Page 14-54
T7 Package
Head Plastic 10-220 (Standard)
(LTC DWG # 05-08-1422)

0.390 - 0.415
(9.906 -1 0.541) -+O,....----+j

'D
=====I-t

0.230 - 0.270
(5.842 - 6.858)

--.----t-+-+

;;:0;,;;.4",60;---O';0';,:;50~0

L

(11.684 -12.700)

0.570 - 0.620
(14.478-15.748)
0.330 _ 0.370

(8.382 - 9.398)

0.095-0.115
(2.413-2.921)

11-4- .... I-- 0.026 - 0.036

0.040 - 0.060 ....
(1.016 1.524)

1

(0.660-0.914)

0.013 - 0.023
(0.330 - 0.584)
0.155-0.195
(3.937 - 4.953)
T7 fjo-220} (FORMED) 0095

For Lead Bend Options See Page 14-54

14-33

PACKAGE DIMENSIONS
WPackage
10-Lead Flatpak Glass Sealed (Hermetic)
(LTC DWG #05-08-1130)

L

0290'
(7:366) -------0.010-0.019'~ ,--MAX --' _
(0.254 - 0.483) I' I I .
. I

0.005
(0.127)
MIN

0.003 - 0.006"
(0.076 - 0.152)

r

0.250 - 0.370"

-1=
0.240 - 0.260
(6.096 - 6.604)

DETAIL

t-

A

I

0.050'
(1.270) BSC

0.005
(0.127) MIN

I
I
1+-----1

lo~

0.250 - 0.370
(6.350 - 9.398)

_

(1.143)
MAX

~
~

j.+- 0.026 - 0.045

-

----

I (0.660-1.143)
0.030 - 0.085

(0.762 - 2.159)

NOTES:
'THIS DIMENSION ALLOWS FOR OFF-CENTER LID,
MENISCUS AND GLASS OVERRUN.
"INCREASE DIMENSIONS BY 0.003 INCHES (0.076 mm)
WHEN LEAD FINISH A IS APPLIED (SOLDER DIPPED).

0.008 - 0.015
(0.203 - 0.381)

WlO(GLASS)0895

WB Package
10-Lead Flatpak Metal Sealed Bottom Brazed (Hermetic)
(LTC DWG # 05-08-1230)

I- 0.015 - 0.022
(0.381-0.559)

-H

0.290
(7.366) - MAX

t--

-J -

0.005
(0.127)
MIN

r't-0.250 - 0.370
(6.350 - 9.398)

0.030
(0.762)
MIN

tt-

t
t
0.125

0.240 - 0.260
(6.096 - 6.604)

PIN 1 10 ON
BOTTOM SIDE

)",""'T"T'r-n"'Tl'"'TT'~l

(3.175)
MIN

•t

0.030
(0.762)
MIN

0.250 - 0.370
(6.350 - 9.398)

11_

0.050 ±0.005 ---I
(1.270 ±0.127)

1 0.045
(1.143)
MAX

1------1

0.045-0.115
(1.143-2.921) -

0.004 - 0.009
(0.102-0.229)

_

0.010
(0.254)
MIN

WlO(METAL}0894

14-34

PACKAGE DIMENSIONS
WB Package
14-Lead Flatpak Metal Sealed Bollom Brazed (Hermetic)
(LTC DWG #05-08-1240)
0390

I- ( 9 : 9 0 6 ) 0.015 - 0.022
(0.381 - 0.559) -]-I

1-

MAX

-I

0.005
-(0.127)
MIN

0.004 - 0.009

...-__-1_ ~(0.102-0.229)

t

0.250 - 0.370

0.030
(0.762)
MIN

t
t

0.125
(3.175)
MIN

0.240 - 0.260
(6.096 - 6.604)

PIN 1 10 ON
BOTTOM SIDE

/L,-T""T'I""T'!""'T"I"'TT""rT""T~l

•t

-j

0.030
(0.762)
MIN

0.250 - 0.370
(6.350 - 9.398)

0.050 ±0.005
(1.270 ±0.127)

_I I--

~

0.045
(1.143)
MAX

I
0.045-0.115
(1.143-2.921)

-

0.010
-(0.254)
_
MIN
W14 (METAL) 0594

Z Package
3-Lead Plastic TO-92 (Similar to TO-226)

0.060 ± 0.005
(1.524± 0.127)
DlA
"-

(LTC DWG # 05-08-1410)

I

0.180±0.005
(4.572 ± 0.127)
0.060 ± 0.01 0

"-~==~
~,~-------:

0.180 ± 0.005
(4.572±0.127)

t

I]

:

~

lC\:
V

0.050 ± 0.005
(1.270 ± 0.127)

0.90
(2.286)
NOM

:--t

________ l * t
-r

I
(L~~~
0.500

__

0.050 UNCONTROLLED
(1.270) LEAD DIMENSION
MAX

J UL·m,,"~
~

1

(1.524 ±0.254)

+

0.140 ± 0.010
(3.556 ± 0.127)

t

~

_II.- (0.381
0.015 ± 0.002
± 0.051)

Z3(TO-92)0695

a

(0.406 ± 0.076)

14-35

f""-LlntA~D~s_U_RFA_C_E_M_O_UN_T_PR_O_DU_C_TS

~,

TECHNOLOGY

Introduction
Linear Technology Corporation (LTC) was founded in
1981 to address the growing demand for high performance and superior quality linear integrated circuits.
Today, LTC has successfully established a leadership
position by introducing and supplying leading edge products in each of the industry's basic functional groupsop amps, comparators, voltage regulators, references,
switched-capacitor filters, interface, data conversion, and
a variety of special function CMOS devices, in all major
package styles.
Early on, LTC made the commitment to provide advanced
technology, surface mount packaging. This made Linear
Technology the first company to offer true precision and
high performance linear devices across the full range of
functional categories, plus many of the popular secondsource devices in JEDEC Standard packages:
SO (0.150) 8, 14, 16
SO (0.300) 16, 18, 20, 24, 28
SSOP (0.150) 16, 20, 24
SSOP (0.209) 16, 20, 24, 28
SSOP (0.300) 36, 44
TSSOP (0.173) 20

This section contains information summarizing LTC's
capabilities and services for surface mount packaged
products, as well as specific device data sheets.

Package Descriptions
LTC's SO packages conform to Standard JEDEC Small
Outline drawings.
In some instances, an LTC product available in an 8-pin
standard DIP package is offered in a 16-pin SO package.
This covers the situation where the die is too large to be
accommodated by the smaller SO-8 package. Although it
is preferable for an SO-8 device to have the same pinout as
the standard 8-pin dual-in-line version, some devices
necessitate a rotation of the die to fit in the SO-8 package.
Please refer to the applicable SO device data sheet, or
consult with the factory to verify exact pinouts for each
device.

Electrical Specifications
Wherever possible, electrical specifications for a surface
mount technology (SMT)* device are the same as the
plastiC molded equivalent. Exceptions to this are identified
by the omission of the standard product electrical grade
designator from the part number.
For example:

The continuing demand for more complete surface mount
designs has spurred the introduction oftwo power surface
mount packages by LTC-the 3-lead SOT-223 and the
DD package available in 3-, 5- and 7-lead versions. Many
LTC power products are now being introduced in these
packages which, for the first time, enable high power
deSigns to be realized using 100% surface mount devices.
Support for LTC's surface mount devices includes service
fortape and reel, antistatic rails, quality and reliability data,
and data sheets on each product.

• LT1 013D88 has the same electrical specifications
as LT1 013DN8, since the "D" is common to both
product numbers.

LTC intends to address customer demand for surface
mount devices where technology and die sizes permit,
making the combination of small package size and high
performance linear devices readily available to our users.

• Terminology: SO = Small Outline, SOT = Small Outline Transistor,
SSOP =Shrink Small Outline Package, TSSOP =Thin Shrink Small
Outline Package.
LTC package code designators for SMT products are:
F=TSSOP, G=SSOP, GN =Narrow Body SSOP, GW =Wide Body
SSOP, M, Q and R=DD Pak, S =Narrow Body SO, SW =Wide Body SO,
ST = SOT-223.

14-36

• LT1 012S8 has one or more different electrical specifications than LT1 012CN8, as the "C" is missing from
this product designator suffix.
Please consultthe appropriate SMT package data sheetfor
complete electrical specifications.

SURFACE MOUNT PRODUCTS
Marking

Lead Finish and Solderability

Because of the limited space available for part marking on
some SMT packages, abbreviated marking codes are used
to identify the device. These codes, if used, are identified
in the individual SMT package data sheets.

Lead finish is electroplated, lead-tin, with a low carbon
content. Solderability meets the requirements of MILSTD-883C, Method 2003. Recommended solder pads are
given in Figure 1.

Recommended Solder Pads
F Package (0.173)
TSSOP-2o

0.047
±0.005

0.038
±0.005

rDDDDi

rOOOOi
0.257
MIN

GN Package Narrow (0.150)
SSOP-16, SSOP-2o, SSOP-24

GPackage (0.209)
SSOP-2o, SSOP-24, SSOP-28

0.181
±0.005

0.045 ±0.005

o.[OOOOi
MIN

. ."J~D8j~:~~,

. .",.J}2j ~~,.m
NOTE: ALL DIMENSIONS ARE IN INCHES

0.150-0.165

.,,~..1,~D2j ~~.m
NOTE: ALL DIMENSIONS ARE IN INCHES

SMPOBA

NOTE: ALL DIMENSIONS ARE IN INCHES

GW Package Wide (0.300)
SSOP-36, SSOP-44

MPackage
Head DD

0.045
±0.005

1

1-----

-1

0.420 - - -...

fDDDD

._",lD~D ~ ~~,:~
NOTE: ALL DIMENSIONS ARE IN INCHES

1

0.350

_l
,,~~oDr

0.56

Ogo

1--10.070

NOTE: ALL DIMENSIONS ARE IN INCHES

'MP 03

Figure 1_ Recommended Solder Pads

L7lJn~

14-37

SURFACE MOUNT PRODUCTS
QPackage
Head DD
1••- - -

0.420

R Package
Head DD

----~i1

1••- - - 0.420 - - - - - 1

1

1

0.350

0.350

_l

q!

l

0.56

QQ~[ ~DDDr·090
--I

~DD-10.090
-I

I--

1-0.042

NOTE: ALL DIMENSIONS ARE IN INCHES

81 Package
3-Lead 801-223
0.045
±0.005

rDDDD~

MIN

r---+

0.129

1

MAX

I

1

8W Package Wide (0.300)
80-16, 80-18, 80-20, 80-24, 80-28
0.045
±0.OO5

0.059
MAX

.~..~~D~D ~ ~~w +=

0.248
BSC

0.420
MIN

0.059
MAX

NOTE: ALL DIMENSIONS ARE IN INCHES

fDDDD1

~L....-+--.J

0.160
±0.005

1-0.035

NOTE: ALL OIMENSIONS ARE IN INCHES

8MP"

8 Package (0.150)
80-8, 80-14, 80-16

0.245

8MPOI

NOTE: ALL DIMENSIONS ARE IN INCHES

'MP<"

0.325
±0.005

.~. LD~~~:~,
NOTE: ALL DIMENSIONS ARE IN INCHES

Figure 1. Recommended 80lder Pads (Continued)

14-38

0.56

SMP02

SURFACE MOUNT PRODUCTS
~ave

and Reflow Soldering

ollowing are the recommended procedures for soldering
urface mount packages to PC boards.

material with copper traces, in still air at 25°C. 8JA with a
ceramic substrate is about 70% of the FR4 value. Maximum power dissipation may be calculated by the following
formula:

. Wave Soldering
•
•
•
•

Use solder plating boards.
Dispense adhesive to hold components on board.
Place components on board.
Cure adhesive per adhesive manufacturer's specification.
• Foam flux using RMA (Rosin Mildly Activating) flux.
• Wave solder using a dual wave soldering system at
240°C to 260°C for 2 seconds per wave.
• Clean board.
. Reflow Soldering
•
•
•
•
•
•
•
•
•
•
•
•

•

Use of solder plating boards is recommended.
Screen solder paste on board.
Mount components on board.
Infrared or forced hot air convection reflow is recommended for best performance.
Preheat peak temperature 125°C ± 15°C and 2°C to
5°C per second rise.
Activation temperature 130°C to 150°C.
Reflow begins at 183°C (63Sn/37Pb).
Time above 183°C for at least 30 seconds.
Peak package body temperature 220°C maximum.
Cooling rate 2°C to 5°C per second.
Clean boards.
For Vapor Phase Reflow, recommended parameter
ranges for:
- Heating rate: 6°C per second maximum
- Preheat temperature: 45°C to 80°C
- Time above 200°C: 50 seconds to 90 seconds
- Peak package temperature: 212°C to 219°C
Hand soldering of DO and SOT-223 package is not
recommended.

hermallnformation
able 1 shows the range of junction-to-ambient thermal
lsi stance of SO devices mounted on a PCB of FR4

RDMAX (TA)-- TJMAXe - TA
JA

where,
TJMAX = Maximum operating junction temperature.
TA = Desired ambient operating temperature.
8JA = Junction-to-ambient thermal resistance.
Table 1. Typical Thermal Resistance Values
50-8

150°C/W to 200°C/W

80-18

70°C/W to 100°C/W

SO-14

1OO°C/W to 140°C/W

70°C/W to 90°C/W

SO-16 (0.150)

90°C/W to 130°C/W

50-20
80-24

SO-16 (0.300)

85°C/W to 100°C/W

50-28

55°C/W to 75°C/W

60°C/W to 80°C/W

Conditions: PCB mount on FR4 material, still air at 25°C, copper trace.

Thermal resistance for power packages (DO and SOT-223)
depends greatly on the individual device type. Please
consult the device data sheets for thermal information.
More current data, by device type, may be obtained by
contacting LTC, Marketing Department.
Tape and Reel Packing (See Tape and Reel Section)
Plastic Tube Packing
LTC's Surface Mount products are packed in "antistatic"
plastic tubes with the tube dimensions indicated in Figure
2. Unit quantities packaged per tube are listed below in
Table 2.
Table 2. Devices Per Tube
LTC Package
Code Designator

LTC Package
Style

Actual
Lead Count

Number
of Units

F

TSSOP (0.173)

20

74

G

16
20

77

G

SSOP (0.209)
SSOP (0.209)

G

SSOP (0.209)

24

59

G
GN

SSOP (0.209)

28

47

SSOP (0.150)

16

100

GN

SSOP (0.150)

20,24

55

GW

SSOP (0.300)

36

32

GW

SSOP (0.300)

44

27

66

14-39

SURFACE MOUNT PRODUCTS
Table 2. Devices Per Tube
LTC Package
Code Designator

LTC Package
Style

Actual
Lead Count

Number
of Units

LTC Package
Code Designator

LTC Package
Style

Actual
Lead Count

Number
of Units

DD

3,5,7

47

8

SW
SW

16

S8 (0.150)

50
100

SW (0.300)

S8

SW (0.300)

18

40

S

S (0.150)

14

55

SW

SW(0.300)

20

38

S

S (0.150)

16

50

SW

SW(0.300)

24

ST

SOT-223

3

78

SW

SW (0.300)

28

32
27

M, Q, R

PLASTIC TUBE SPECIFICATiOnS
S (0.150)
SO Package Shipping Tube

SW (0.300)
SO Package Shipping Tube
0.060

0.265

fT

j

0.280

-11

0.070

LENGTH: 20.50

0.580

0.310

~ 1;~~

NOTE: ALL DIMENSIONS ARE IN INCHES

ST
SOT-223 Package Shipping Tube
5--\"''"-iI---t~

LENGTH: 20.75

0.063±0.007

~ 1;~~

NOTE: ALL DIMENSIONS ARE IN INCHES

Note 1: Tolerances: ±0.010 unless otherwise specified.

Note 2: Material: antistatic treated rigid transparent PVC or rigid black
conductive.
Note 3: Printing: "LTC logo, Linear Technology Corp., Antistatic" on
topside oftube.

0.20±0.005

R 0.020

x4, REF
NOTE: ALL DIMENSIONS ARE IN INCHES

Figure 2

14-40

SURFACE MOUNT PRODUCTS
urface Mount Small Outline (SO), DD and SOT Device Packaging
near Technology now offers a continually increasing number of high
rrformance CMOS and bipolar linear devices in surface mount packages.
sted in the next several pages are device types now available in the DO power
lckages and the JEDEC standard outline packages; SO (Small Outline 0.150
ld 0.300 body widths), SSOP (Shrink Small Outline 0.150, 0.209 and 0.300

body widths), TSSOP (Thin Shrink Small Outline 0.173 body width) and
SOT-223 (Small Outline Transistor). For pinout configurations and electrical
specification limits, consult either your LTC sales representative or the
factory.

Surface Mount Packages:
LTC Package Suffix:
~RODUCT
~peralional

LF398
LM318
LT1 001 C
~ TI 006
LT1007C
LT1008
_T1012
,T1013D
~ T1 0131
31014D
.Tl0141
.Tt028C
_Tl037C
.TC1047C
.TC1049C
_TC1050C
_TC1051C
_TC1052C
_TC1 053C
_Tl055
_T1 056
.T1057
.T10571
•T1 058
.Tl0581
.Tt077
.Tl078
.1'10781
_T1079
_Tl0791
_Tl097
_Tl112
_Tl113C
_Tl114
_T1115C
_T1122C
.T1122D
.T1124C
.T1125C
.Tl126C
.T1127C
.T1128C
.TC1150C
.TC1151 C
.TC1152C
.TC11521
.T1178
.T1179
.T1187C
.T1189C
.T1190C
.Tt191 C
.T1192C
.T1193C
.T1194C
.T1195C

DESCRI~ION

Amplifiers
S8
Sample & Hold Amp
S8
FastOpAmp
S8
Precision Op Amp
S8
Precision Single Supply Op Amp
S8
Low Noise, High Speed, Precision Op Amp
S8
Uncompensated, Picoamp Input, Precision Op Amp
S8
Picoamp Input Current, Precision Op Amp, C·Load™
S8
Dual Precision Single Supply Op Amp
S8
Dual Precision Single Supply Op Amp
SW
Quad Precision Single Supply Op Amp
SW
Quad Precision Single Supply Op Amp
S8
Ultra Low Noise Op Amp
S8
Low Noise, High Speed Precision Op Amp
SW
Dual Micropower Zero·Drift Op Amp w/lnternal Caps
S8
Low Power Zero·Drift Op Amp w/lnternal Caps
S8
Zero-Drift Op Amp w/lnternal Caps
SW
Dual Zero-Drift Op Amp w/lnternal Caps
SW
Low Noise Zero-Drift Op Amp
SW
Quad Precision Zero-Drift Op Amp w/lnternal Caps
S8
JFET Input, High Speed, Precision Op Amp
S8
JFET Input, High Speed, Precision Op Amp
S8
Dual JFET Input, High Speed, Precision Op Amp
S8
Dual JFET Input, High Speed, Precision Op Amp
SW
Quad JFET Input, High Speed, Precision Op Amp
SW
Quad JFET Input, High Speed, Precision Op Amp
S8
Precision Micropower Op Amp
S8
Dual Precision Micropower Op Amp
S8
Dual Precision Micropower Op Amp
SW
Quad Precision Micropower Op Amp
SW
Quad Precision Micropower Op Amp
S8
Low Cost, Low Power, PreCision Op Amp
S8
Dual Precision Op Amp, C-Load
S8
Dual Low Noise, Precision, JFET Input Op Amp
SW
Quad Precision Op AmQc.C-Load
SW
50MHz, l1V/!(s, lnVNHzAudioOpAmp
S8
Fast Settling, JFET Input Op Amp
S8
FastSettling,JFETlnputOpAmp
S8
Dual Low Noise, High Speed, Precision Op Amp
SW
Quad Low Noise, High Speed, Precision Op Amp
S8
Decamp Dual Low Noise, High Speed, Precision Op Amp
SW
Decamp Dual Low Noise, High Speed, Precision Op Amp
S8
Unity-Gain Stable Ultra Low Noise Op Amp
S8
±15V Zero-Drift Op Amp w/lnternal Caps
SW
Dual ±15V Zero-Drift Op Amp
S8
Rail-to-RaillnputiOutput Zero-Drift Op Amp, C-Load
S8
Rail-to-RaillnputiOutput Zero-Drift Op Amp
S8
Dual Precision Micropower Op Amp
SW
Quad Precision Micropower Op Amp
S8
Low Power Video Difference Amp
S8
Low Power Video Difference Amp
S8
50MHz High Speed Video Op Amp
S8
90MHz High Speed Video Op Amp
58
350M Hz (Av 2: 25)High Speed Video Op Amp
58
80MHz (Adj Gain) High Speed Video Op Amp
58
35MHz (Av = 10) Fixed Differential Video Op Amp
58
Low Power, High Speed Op Amp

TSSOP
F
PRODUCT
LT1200C
LTt201C
LTt202C
LT1206C
LT1208C
LT1209C
LT1211C
LT1212C
LT1213C
LT1214C
LT1215C
LT1216C
LT1217C
LT1220C
LT1221C
LT1222C
LTt223C
LT1224C
LT1225C
LTt226C
LT1227C
LT1228C
LT1229C
LT1230C
LTC1250C
LT1251C
LT1252C
LT1253C
LTt254C
LT1256C
LT1259C
LT1260C
LT1311C
LT1354C
LT1355C
LT1356C
LT1357C
LTt358C
LT1359C
LT1360C
LTt361C
LT1362C
LT1363C
LTt364C
LT1365C
LT1366C
LT1367C
LT1368C
LT1369C
LT1413
LT1457
OP-07C
Op·27G
OP-37G
OP-470G

DESCRI~ION

Low Power, High Speed Op Amp, C-Load
58
Dual Low Power, High Speed Op Amp, C-Load
58
Quad Low Power, High Speed Op Amp, C-Load
S
58, R 250mA, 60MHz Current Feedback Amplifier, C-Load
58
Dual Very High Speed Op Amp, C-Load
Quad Very High Speed Op Amp, C-Load
5
14MHz Dual Precision Op Amp
58
14MHz Quad Precision Op Amp
S
28M Hz Dual Precision Op Amp
S8
28M Hz Quad Precision Op Amp
S
23MHz Dual Precision Op Amp
58
23MHz Quad Precision Op Amp
5
Low Power, 10MHz Current Feedback Amplifier
S8
Very High Speed Op Amp
58
S8
Very High Speed Op Amp (Av 2: 4)
S8
Very High Speed Op Amp (Av 2: 1O,Ext Camp)
S8
100MHz Current Feedback Amplifier
45MHz Very High Speed Op Amp, C-Load
S8
S8
150MHz (Av 2: 5) High Speed Op Amp
S8
1GHz (Av 2: 25) High Speed Op Amp
S8
140MHz High Speed Current Feedback Op Amp
S8
1OOMHz Current Feedback Amplifier w/DC Gain Control
sa Dual 1OOMHz Current Feedback Amplifier
Quad 1OOMHz Current Feedback Amplifier
S
Ultra Low Noise Zero-Drift Op Amp
S8
40MHz Video Fader/Amplifier
S
Low Cost Video Amplifier
S8
Low Cost Dual Video Amplifier
S8
Low Cost Quad Video Amplifier
S
S
40MHz DC Gain Controller Amplifier
Dual 130MHz CFA with SHUTDOWN
S
Triple 130MHz CFA with SHUTDOWN
S
Quad 12Mhz, 145ns Settling Precision Current-to-Voltage
S
Converter for Optical Disk Drives
12MHz, 400Vl!lS Op Amp, C-Load
S8
S8
Dual 12MHz, 400Vl!lS Op Amp, C-Load
Quad 12MHz, 400Vl!lS Op Amp, C-Load
S
25M Hz, 600Vl!lS Op Amp, C-Load
S8
S8
Dual 25M Hz, 600Vl!lS Op Amp, C-Load
S
Quad 25MHz, 600Vl!lS Op Amp, C-Load
S8
50 MHz, 800Vl!lS Op Amp, C-Load
Dual 4mA, 50MHz, 800Vl!lS Op Amp, C-Load
S8
Quad 50MHz, 800Vl!lS Op Amp, C-Load
S
70MHz, 1000V/!(s Op Amp, C-Load
S8
S8
Dual6mA, 70MHz, 1000Vl!lS Op Amp, C-Load
Quad 70MHz, 1000Vl!lS Op Amp, C-Load
S
Dual Rail-to-RaillnputiOutput Op Amp
S8
Quad Rail-to-RaillnputiOutput Op Amp
S
S8
Dual Rail-to-RaillnputiOutput Op Amp
S
Quad Rail-to-RaillnputiOutput Op Amp
S8
Dual Single-Supply, Precision Op Amp
S8
Dual Precision JFET Op Amp, C-Load
S8
Precision Op Amp
Low Noise, High Speed, Precision Op Amp
S8
Low Noise, High Speed, PreCision Op Amp
S8
Quad Low Noise, Precision Op Amp
S

.oad is a trademark of Linear Technology Corporation

L7lJD~

14-41

SURFACE MOUNT PRODUCTS
Surface Mount Small Outline (SO), DD and SOT Device Packaging
PRODUCT
DESCRIPTION
Battery Management/Charging
lT1239C
Backup Battery ManagemenllC, li-Ion or NiCd
S
lT1510C
Battery Charger
S8
lT1510C
Battery Charger
S
lT1512C
SEPIC Battery Charger
S8
lTC1325C
IlI'-Controlied Battery Management System
SW
Instrumentation Amps
lTCll00AC S8
Consult Factory
lTC1100C
Chopper Stabilized Instrumentation Amp
SW
lT1101
SW
Precision Micropower Instrumentation Amp
lT11011
SW
Precision Micropower Instrumentation Amp
Comparators
LT1011C
S8
Precision Volt Comparator
High Speed Comparator
lTl016C
S8
High Speed Comparator
lT10161
S8
LT1017C
S8
Micropower Dual Comparator
LT10171
Micropower Dual Comparator
S8
LT1018C
S8
Micropower Dual Comparator
LTC1040C
SW
Micropower Dual Sampling Comparator
LTC1041C
Bang-Bang Controlier
S8
LT1116C
High Speed, Ground-Sensing Comparator
S8
LTC1443C
Quad Micropower Comparator and Reference
S
lTC1444C
Quad Micropower Comparator and Reference
S
LTC1445C
Quad Micropower Comparator and Reference
S
Data Acquisition
LTC1090C
SW 10-Bit AID with 8-Channel MUX & SlH
LTC1093C
SW 10-Bit AID with 6-Channel MUX & StH
LTC1096AC S8
8-Bit Micropower AID with StH
LTC1096C
S8
8-Bit Micropower AID with StH
LTC1098AC
S8
8-Bit Micropower AID with StH
LTC1098C
S8
8-Bit Micropower AID with StH
LTC1099C
SW 8-Bit High Speed ADC with StH
LTC10991
SW 8-Bit High Speed ADC with StH
LTC1196-1 AC S8
8-Bit, 600ns, 1MHz Sampling ADC
lTC1196-1BC S8
8-Bit, 600ns, 1MHz Sampling ADC
LTC1196-2AC S8
8-Bit, 710ns, 800kHz Sampling ADC
LTC1196-2BC S8
8-Bit, 710ns, 800kHz Sampling ADC
LTC1198-1 AC S8
2-Channel, 8-Bit, 600ns, 750kHz, Sampling ADC
LTC1198-1 BC S8
2-Channel, 8-Bit, 600ns, 750kHz, Sampling ADC
l TC1198-2AC S8
2-Channel, 8-Bit, 710ns, 750kHz, Sampling ADC
l TC1198-2BC S8
2-Channel, 8-Bit, 710ns, 750kHz, Sampling ADC
lTC1257C
S8
12-Bit Complete VOUT DAC
LTC12571
S8
12-Bit Complete VOUT DAC
l TCI272-3AC SW 12-Bit 3~s Paraliel 110 AID with StH
LTCI272-3BC SW 12-Bit 3~s ParalielliO AID with StH
LTCI272-3CC SW 12-Bit 3~ ParalielliO AID with StH
LTCI272-8AC SW 12-Bit 8~s ParalielliO AID with StH
LTCI272-8BC SW 12-Bit 8~s ParalielliO AID with StH
LTCI272-8CC SW 12-Bit 8~s ParalielliO AID with StH
LTC1273AC SW 12-Bit 3~s ParalielliO with StH & Reference
LTC1273BC SW 12-Bit 3~ ParalielliO with StH & Reference
LTC1274AI
SW 12-Bit 6~ Parallel 110 AID with Reference and Shutdown
LTC1274C
SW 12-Bit 6~ ParalielliO AID with Reference and Shutdown
LTC12741
SW 12-Bit 6~ Parallel 110 AID with Reference and Shutdown
LTC1275AC SW 12-Bit 3~s Parallel 110 with StH & Reference
LTC1275BC SW 12-Bit 3~ Parallel 110 with StH & Reference
LTC1276AC SW 12-Bit 3~s Parallel 110 with StH & Reference
LTC1276BC SW 12-Bit 3~s Parallel 110 with StH & Reference
LTC1277AI
SW 12-Bit 6~ Parallel 110 with StH & Reference
LTCI277C
SW 12-Bit 6~ Parallel 110 with S/H & Reference
LTC12771
SW 12-Bit 6~ Parallel 110 with StH & Reference
LTC1278-4C SW 12-Bit 2"5~ High Speed Sampling AID
LTC1278-41
SW 12-Bit 2"5~ High Speed Sampling AID
LTC1278-5C SW 12-Bit 2"5~ High Speed Sampling AID
LTC1278-51
SW 12-Bit 2"5~ High Speed Sampling AID

14-42

PRODUCT
lTC1279C
lTC12791
LTC1282AC
LTC1282BC
LTC1285C
LTC12851
lTC1286C
LTC12861
LTC1288C
LTC12881
LTC1289BC
LTC1289CC
LTC1290BC
LTC1290BI
LTC1290CC
LTC1290CI
LTC1290DC
LTC1290DI
LTC1293BC
LTC1293CC
LTC1293DC
LTC1294BC
LTC1294BI
LTC1294CC
LTC1294DC
LTC1296BC
LTC1296BI
LTC1296CC
LTC1296CI
LTC1296DC
LTC1296D1
LTC1298C
LTC12981
LTC1390C
LTC1392C
LTC13921
LTC1400C
LTC14001
LTC1410AC

DESCRIPTION
SW
SW
SW
SW
S8
S8
S8
S8
S8
S8
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
S8
S8
S
S8
S8
S8
S8
SW

LTC1410BC SW
LTC1410AI

SW

LTC1410BI

SW

LTC1410C

SW

LTC14101

SW

LTC1451C
LTC14511
LTC1452C
LTC14521
LTC1453C
LTC14531
LTC1522C
LTC7541AJ
LTC7541AK
LTC7543GK
LTC7543K
LTC8043E
LTC8043F
LTC8143E
LTC8143F

S8
S8
S8
S8
S8
S8
S
S
SW
SW
SW
S8
S8
SW
SW

12-Bit 1.6~s Parallel 110 with StH & Reference
12-Bit 1"6~s Parallel 110 with StH & Reference
12-Bit 6~s Parallel 110 with StH & Reference
12-Bit 6~s Parallel 110 with StH & Reference
12-Bit 3V Micropower ADC with StH
12-Bit 3V Micropower ADC with StH
12-Bit Micropower AID with StH
12-Bit Micropower AID with StH
12-Bit 3V Micropower ADC with StH
12-Bit 3V Micropower ADC with StH
12-Bit 3V 8-Channel MUX, StH Full Duplex 110
12-Bit 3V 8-Channel MUX, StH Fuli Duplex 110
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 6-Channel MUX & StH
12-Bit AID with 6-Channel MUX & StH
12-Bit AID with 6-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH
12-Bit AID with 8-Channel MUX & StH, Single Supply
12-Bit AID with 8-Channel MUX & StH, Single Supply
12-Bit AID with 8-Channel MUX & StH, Single Supply
12-Bit AID with 8-Channel MUX & StH, Single Supply
12-Bit AID with 8-Channel MUX & StH, Single Supply
12-Bit AID with 8-Channel MUX & StH, Single Supply
12-Bit Micropower AID with StH
12-Bit Mic"ropower AID with StH
8-Channel Serial 110 Analog MUX
1O-Bit Environment Monitor ADC
10-Bit Environment Monitor ADC
Complete SO-8, 12-Bit 400ksps ADC with Shutdown
Complete SO-8, 12-Bit 400ksps ADC with Shutdown
12-Bit 700ns Parallel 110 ADC with Reference and
Shutdown
12-Bit 700ns Parallel 110 ADC with Reference and
Shutdown
12-Bit 700ns Parallel 110 ADC with Reference and
Shutdown
12-Bi1700ns Parallel 110 ADC with Reference and
Shutdown
12-Bit 700ns Parallel 110 ADC with Reference and
Shutdown
12-Bit 700ns ParalielliO ADC with Reference and
Shutdown
12-Bit Complete VOUT DAC
12-Bit Complete VOUT DAC
12-Bit VOUT MUlitplying Rail-to-Rail DAC
12-Bit VOUT Mulitplying Rail-to-Rail DAC
12-Bit Complete VOUT DAC 3V/5V Operation
12-Bit Complete VOUT DAC 3Vt5V Operation
4-Channel3V Micropower Sampling 12-Bit Serial 110 ADC
Improved Industry Std CMOS 12-Bit Multiplying DAC
Improved Industry Std CMOS 12-Bit Multiplying DAC
Improved Industry Std Serial 12-Bit Multiplying DAC
Improved Industry Std Serial 12-Bit Multiplying DAC
Serial 12-Bit Multiplying DAC in SO-8
Serial 12-Bit Multiplying DAC in SO-8
Improved IndustryStd Serial 12-Bit Multiplying DAC
Improved Industry Std Serial 12-Bit Multiplying DAC

I

SURFACE MOUNT PRODUCTS
3urface Mount Small Outline (SO), DD and SOT Device Packaging
PRODUCT

I

DESCRIPTION

Regulators, PWMs, DC/DC Converters
LT1020C SW
IlPower Low Dropout Regulator with Comparator
LT10201
SW
IlPower Low Dropout Regulator with Comparator
LT1072C S8
40kHz 1.2SA Switching Regulator
l Tl073C S8
IlPower Switching Regulator Works Down to tv Input,
S8-S,12 Adjustable & Fixed SV, 12V Outputs
lTt076C a
2A Step-Down Switching Regulator
lTl076C a
2A Step-Down Switching Regulator, +SV Output
lTl076C R
2A Step-Down Switching Regulator with Shutdown,
S-lead DO Package, Adjustable Output
2A Step-Down Switching Regulator with Shutdown,
lTl076C R-S
7-lead DO Package, SV
l Tl076HVC R
2A Step-Down Switching Regulator, ?-lead DO Pkg
l Tl 084C M
SA low Dropout Regulator, 3-lead DO Package
lT1 08SC M
Adjustable low Dropout Pos Voltage Regulator, 3A
lT108SC M-3.3
3.3V low Dropout Voltage Regulator, 3A
lT1 08SC M-3.6
3.6V low Dropout Voltage Regulator, 3A
lT1 086C M
I.SA low Dropout Regulator, 3-lead DO Pkg
lTl086C M-3.3
3.3V low Dropout Positive Voltage Regulator, I.SA
l Tl086C M-3.6
3.6V low Dropout Positive Voltage Regulator, I.SA
l Tll07C S8
IlPower DCfDC Converter Works Down to 2V Input,
S8-S,12 Adjustable & Fixed SV, 12V Outputs
l Tll08C S8, S8-S, IlPower DCfDC Converter Works Down to 2V Input,
S8-12
Adjustable & Fixed SV, 12V Outputs
LTll09AC S8
IlPower DCfDC Converter with Shutdown & 100kHz
Swtiching Frequency, Adjustable & Fixed SV, 12V Outputs
l TIl 09AC S8-S
!!power Switching Regulator, SV Output
l Tll09AC S8-12
!!power Switching Regulator, 12V Output
LTll09C S8, S8-S, IlPower DCfDC Converter with Shutdown & 100kHz
S8-12
Switching Frequency, Adjustable & Fixed SV, 12V Outputs
lTlll0C S8, S8-S, IlPower DCfOC Converter Works Down to IV Input,
S8-12
Adjustable & Fixed SV, 12V Outputs
l T1111 C S8, S8-S, IlPower Switching Regulator Works Down to 2V Input,
S8-12
Adjustable & Fixed SV, 12V Outputs
l T11111 S8
!!power Adjustable Switching Regulator
lT1117C M
Adjustable Low Dropout Regulator
l T1117C M-3.3
3.3V low Dropout Regulator
LT1117C M-S
SV low Dropout Regulator
l TllllC ST
low Dropout 800mA Adjustable Regulator
lTII17C ST-S
low Dropout 800mA Regulator, SV
lTt117C ST-2.8S Active SCSI-2 Terminator, 2.8SV
l T1117C ST-3.3
low Dropout 800mA Fixed 3.3V Regulator
l T1118C S8-2.S
2.SV SourcefSink low Dropout Regulator
l T1118C S8-2.8S SCSI SourcefSink Terminator
lT1118C S8-S
SV SourcefSink low Dropout Regulator
l T1118C ST-2.S
2.SV SourcefSink low Dropout Regulator
l T1118C ST-2.8S SCSI Sou reefSink Terminator
LT1118C ST-S
SV Sou reefSink low Dropout Regulator
l Tt120AC S8
!!power Voltage Regulator and Comparator with Shutdown
lT1120C S8
IlPower low Dropout Regulator with Shutdown
lTt121AC S8,
IlPower low Dropout Regulator with Shutdown,
S8-3.3, S Adjustable & Fixed 3.3V, SV Outputs
lT1121AI S8
Adjustable low Dropout !!p Regulator
lT1121AI S8-3.3
3.3V low Dropout !!power Regulator
SV low Dropout !!power Regulator
lT1121AI S8-S
lT1121C S8,
IlPower Low Dropout Regulator with Shutdown,
S8-3.3, S Adjustable & Fixed 3.3V, SV Outputs
LTt121C ST-3.3, S IlPower low Dropout Regulator, Fixed 3.3V, SV Output
lT11211 S8
Adjustable low Dropout !!power Regulator
LTt1211 S8-3.3
3.3V low Dropout !!power Regulator
LTt121 I S8-S
SV low Dropout !!power Regulator
LT11211 ST-3.3
3.3V low Dropout !!power Regulator
LT11211 ST-5
5V low Dropout !!power Regulator
LT1123C ST
low Dropout Regulator Driver
LT1129C a, a-3.3 700mA !!power low Dropout Voltage Regulator
LTt129C a-s
IlPower low Dropout Regulator, Fixed 5V Output
LT1129C S8
Adjustable 700mA IlPower low Droput Regulator
LT1129C S8-3.3
3.3V 700mA !!power low Droput Regulator

L7lJD~

PRODUCT

DESCRIPTION

LT1129C
LT1129C
LTt129C
LTt1291

S8-S
SV 700mA IlPower Low Droput Regulator
ST-3.3
700mA !!power Low Droput Regulator
ST-S
IlPower Low Dropout Regulator, Fixed 5V Output
a, a-3.3, 700mA IlPower Low Dropout Voltage Regulator
a-s
Adjustable 700mA !!power Low Droput Regulator
LTt1291 S8
LT11291 S8-3.3, S 3.3V and SV 700mA !!power Low Droput Regulator
LT11291 ST-3.3, S 700mA !!power Low Droput Regulator, 3.3V and SV Fixed
LTC1142C G
Dual High Efficiency Switching Regulator Controller
LTC1142HVC G
HV Dual High Efficiency Switching Regulator Controller
LTC1142HVC G-ADJ Adjustable HV Dual High Efficiency Sw. Reg. Controller
Dual High Efficiency Switching Regulator Controller
lTC1143C SW
20V Switched Capacitor Voltage Converter
LTC1144C S8
LTC11441 S8
20V Switched Capacitor Voltage Converter
LTC1147C S8-3.3, S High Efficiency Step-Down Switching Regulator Controller
High Efficiency Step-Down Switching Regulator Controller
LTC1147LC S8,
S8-3.3
LTC1148C S,
High Efficiency Step-Down Synchronous Switching
S-3.3, S Regulator Controller
LTC1148HVC S,
High Efficiency Step-Down Synchronous Switching
.
S-3.3, S Regulator Controller
LTC1148LC S,
High Efficiency Step-Down Synchronous Switching
S-3.3
Regulator Controller
High Efficiency Step-Down Synchronous Switching
LTC1149C S,
S-3.3, S Regulator Controller, 48V Inputs
High Efficiency Step-Down Synchronous Switching
LTC11S9C S,
S-3.3, S Regulator Controller
High Efficiency Step-Down Synchronous Switching
LTCllS9C G,
G-3.3, S Regulator Controller
100kHz SA Switching Regulator, 5-Lead DD Pkg
LT1170C
a
100kHz 2.SA Switching Regulator, 5-Lead DO Pkg
LT1171C
a
100kHz 1.2SA Switching Regulator
lT1172C
SW
1.2SA High Efficiency 100kHz Switching Regulator
LT1172C
S8
LTI172C
100kHz 1.2SA Switching Regulator, 5-Lead DD Pkg
a
100kHz
1.2SA Power Switching Regulator
LTI1721
S8
LT1173C
IlPower Switching Regulator for Inputs Greater than
S8
S8-5,12 2V, Adjustable & Fixed SV, 12V Versions
High Efficiency, 400mA Step-Down Switching Regulator
LTC1174C S8,
S8-3.3, S
HV Adjustable !!power Step-Down DCfDC Converter
LTC1174HVC S8
LTC1174HVC S8-3.3 HV 3.3V !!power Step-Down DCfDC Converter
LTC1174HVC S8-S HV SV !!power Step-Down DCfDC Converter
LTC11741 S8
Adjustable !!power Step-Down DCfDC Converter
lT117SC
S8-S
-SV Micropower Low Dropout Regulator
S8-ADJ Negative Adjustable Low Dropout Regulator
LT117SC
LT1176C
SW
100kHz lA Step-Down Switching Regulator with Shutdown
LT1176C
SW-S SV lA Step-Down Switching Regulator
LT1182C
LCDfCCFL Dual Switching Regulator
S
l TCfCCFL Dual Switching Regulator
LT1183C
S
lT1184C
CCFL Switching Regulator for Grounded Bulbs
S
LT1184FC S
CCFL Switching Regulator for Floating or Grounded Bulbs
LT1186C
CCFL Switching Regulator wfDigital Brightness Control
S
LT1241C
Current Mode PWM Controller
S8
Current Mode PWM Controller
LT1241I
S8
LT1242C
Current Mode PWM Controller
S8
lT12421
Current Mode PWM Controller
S8
Current Mode PWM Controller
lT1243C
S8
Current Mode PWM Controller
LT12431
S8
Current Mode PWM Controller
LT1244C
S8
Current Mode PWM Controller
LT12441
S8
Current Mode PWM Controller
LT124SC
S8
lT124S1
S8
Current Mode PWM Controller
LT1246C
S8
1MHz Current Mode PWM Controller
LT1247C
S8
1MHz Current Mode PWM Controller
lT1248C
Power Factor Correction Contoller
S
lT12481
Power Factor Correction Contoller
S
LT1249C
8-Pin Power Factor Correction Controller
S8
lT12491
8-Pin Power Factor Correction Controller
S8

14-43

III

SURFACE MOUNT PRODUCTS
Surface Mount Small Outline (SO), DD and SOT Device Packaging
PRODUCT
lTC1262C S8
lTC1265C S,
S-3.3,5
lTC1266C S,
S-3.3,5
lTC1267C G,
G-ADJ,
G-ADJ5
lT1268BC Q
lT1268C Q
lT1269C Q
lT1269C SW
lT1271C Q
lT1300C S8
lT1301C S8
lT1301l S8
lT1302C S8
lT1302C S8-5
lT1303C
lT1303C
lT1304C
LT1305C
lT1309C
LT1371C
lT1371C
lT1372C
lT1373C
lT1375C

S8
S8-5
S8,
S8-3.3,5
S8
S8
R
SW
S8
S8
S8, S8-5

lT13751

S8, S8-S

lT1376C

S8, S8-S

lT13761

S8, S8-5

lT1377C
l TC1430C
lT1432C
lT1432C
LT1521C
lT1521C
lT1521C
lT1521C
lT1521C
lT1521C
lT1521C
lT15211
lT15211
lT15211
lT1521 I
lT1521 I
lT1S211
lT1521 I
lT1572C
lTC1574C

S8
S, S8
S8
S8-3.3
S8
S8-3.0
S8-3.3
S8-S
ST-3.0
ST-3.3
ST-S
S8
S8-3.0
S8-3.3
S8-S
ST-3.0
ST-3.3
ST-S
S
S, S-3.3,
S-S
M

LT158SC
LT158SC

LT1587C
SG3524

DESCRIPTION
12V, 30mA VPP Generator
1.2A High Efficiency Step-Down DC/DC Converter
in Adjustable, Fixed 3.3V and 5V Output
High Efficiency Synchronous Switching Regulator
Controller in Adjustable, Fixed 3.3V and 5V Output
Dual High Voltage High Efficiency Synchronous
Switching Regulator Controller
7.5A, IS0kHz Switching Regulator
7.5A, IS0kHz Switching Regulator, S-lead Package
4A, Power Switching Regulator, 5-lead DD Package
100kHz 4A Switching Regulator, 20-lead SOIC
60kHz 4A Switching Regulator, S-lead DD Package
~Power Step-Up DC/DC Converter, 1.8V Input
~Power Step-Up DC/DC Converter, 1.8V Input
5v/12V ~ower DC/DC Boost Converter
~Power High Current Step-Up DC/DC Converter
~ower High Current Step-Up Fixed 5V Output DC/DC
Converter
Sv/12V ~ower DC/DC Boost Converter with lBD
SV ~ower DC/DC Boost Converter with lBD
Micropower DC/DC Converter with low-Batery Detector
Active in Shutdown
Micropower High Current DC/DC Converter
SOOkHz Micropower DC/DC Converter
3A/SOOkHz High Efficiency Switching Regulator
3A/SOOkHz High Efficiency Switching Regulator
1.5A/500kHz Step-Up Switching Regulator
1.5A/250kHz Step-Up Switching Regulator
I.SA/500kHz Step-Down Switching Regulator in
Adjustable and Fixed 5V Outputs
I.SA/500kHz Step-Down Switching Regulator in
Adjustable and Fixed SV Outputs
I.SA/SOOkHz Step-Down Switching Regulator in
Adjustable and Fixed SV Outputs
I.SA/500kHz Step-Down Switching Regulator in
Adjustable and Fixed 5V Outputs
I.SA/1 MHz Step-Up Switching Regulator
High Power Step-Down Switching Regulator
High Efficiency Switching Regulator Controller
High Efficiency 3.3V Controiler
300mA ~ower Low Dropout Adjustable Voltage Regulator
300mA ~ower low Dropout 3V Voltage Regulator
300mA ~ower low Dropout 3.3V Voltage Regulator
300mA ~ower low Dropout 5V Voltage Regulator
300mA ~ower low Dropout 3V Voltage Regulator
300mA ~ower low Dropout 3.3V Voltage Regulator
300mA ~ower Low Dropout 5V Voltage Regulator
300mA ~ower Low Dropout Adj Voltage Regulator
300mA ~ower low Dropout 3V Voltage Regulator
300mA ~ower low Dropout 3.3V Voltage Regulator
300mA ~ower low Dropout 5V Voltage Regulator
300mA ~ower low Dropout 3V Voltage Regulator
300mA !Jl'ower low Dropout 3.3V Voltage Regulator
300mA !Jl'ower low Dropout 5V Voltage Regulator
1.5A Switching Regulator w/Built-ln Schottky Rectifier
High Efficiency Step-Down Switching Regulator with
Internal Schottky Rectifier
4A and 4.6A low Dropout Regulator, 3-Lead DD Package,
Fixed Output
3.3V, 3.38V, 3.45V, 3.6V and Adjustable Outputs

M-3.3,
M-3.38,
M-3.45,
M-3.6
M, M-3.3 3A Low Dropout Regulator, 3-lead DD Package,
M-3.45, Fixed and Adjustable Output Voltage
M-3.6
Pulse Width Modulator
S

14-44

PRODUCT
DESCRIPTION
Switched-Capacitor Voltage Converters
High Current Switched-Capacitor Voltage Converter
lTC660C S8
5V to ±10V Switched-Capacitor Voltage Converter
lT1026C S8
Dual Precision Instrumentation Switched Capacitor
LTC1043C SW
Building Block
Switched-Capacitor Voltage Converter, 13V
l TCI 044AC S8
Switched-Capacitor Voltage Converter
lTC1044C S8
Switched-Capacitor Voltage Converter, 13V
l TC1044AI S8
lTC1046C S8
50mA Switched-Capacitor Voltage Converter
lTC10461 S8
SOmA Switched-Capacitor Voltage Converter
lTl054C S8,SW 100mA Switched-Capacitor Voltage Converter
lT10541 SW
100mA SWitched-Capacitor Voltage Converter
lTC1144C S8
20V SWitched-Capacitor Voltage Converter
lTC11441 S8
20V Switched-Capacitor Voltage Converter
lTC1261C S, S8,
Switched-Capacitor Voltage Inverter for GaAs FET Bias
S8-4
S8-4.5
lTC1429C S, S8-4 (+)-to-(-) Converter w/Regulation, External Clock
lTC1550C G, G-4.1 low Noise, (+)-to(-) Switched-Capacitor Converter
G8-4.1
lTC1550C S, S8-4.1 low Noise, (+)-to(-) Switched-Capacitor Converter
lTC1551C G-4.1
low Noise, (+)-to(-) Switched-Capacitor Converter
G8-4.1
S-4.1
S8-4.1
Switched-Capacitor Filters
2nd Order Universal Filter
LTC10S9C
S
Dual 2nd Order Universal Filter
lTC1060C
SW
lTC1061C
SW
Triple 2nd Order Universal Filter
5th Order lowpass Filter (Patented)
lTC1062C
SW
low Offset Clock-Tunable Lowpass Filter
lTC1063C
SW
100kHz Quad 2nd Order Universal Filter
lTC1064C
SW
LTC1064-1C SW
8th Order Cauer lowpass Filter
lTC1064-2C SW
8th Order Butterworth lowpass Filter
l TC1064-3C SW
8th Order Bessel (linear Phase) lowpass Filter
lTC1064-4C SW
8th Order CauerITransitionallowpass Filter
lTC1064-7C SW
100kHz Phase Corrected lowpass Filter
l TC1064-XXC SW High Speed, low Noise Quad Semi-Custom Filter
low Offset Clock-Tunable lowpass Filter
lTC1065C
SW
low Offset Clock Sweep, Bessel Filter
lTC10651
SW
14-Bit Accurate, 8th Order, LP Filter
lTC1066-1C SW
low Power Quad 2nd Order Universal Filter
lTC1164C
SW
lTC1164AC SW
Quad 20kHz Low Power
lTC1164-5C SW
Low Power, 8th Order, Butterworth Filter
lTC1164-6C SW
Low Power, 8th Order, Cauer Filter
lTC1164-7C SW
low Power, 8th Order, linear Phase Filter
lTC1164-8 SW
Ultra-Selective Elliptic Bandpass Filter w/Adjustable Gain
LTCI164-XXC SW
Low Power, Low Noise Quad Semi-Custom Filter
High Speed, Quad 2nd Order Universal Filter
lTC1264C
SW
LTC1264-7C SW
High Speed, 8th Order, linear Phase Filter
Reterences
Constant Current Source & Temperature Sensor Reference
LM334
S8
S8-1.2 1.2V Bandgap Voltage Reference
LM385
S8-2.5 2.5V Bandgap Voltage Reference
lM385
LM385B
S8-1.2 1.2V Bandgap Voltage Reference
S8-2.5 2.5V Bandgap Voltage Reference
lM385B
lTl004C
S8-1.2 1.2V Bandgap Voltage Reference
lTf004C
S8-2.5 2.5V Bandgap Voltage Reference
lTf0041
S8-1.2 1.2V Bandgap Voltage Reference
S8-2.5 2.5V Bandgap Voltage Reference
lTf0041
2.SV Reference
lT1009
S8
2.SV Reference
lTf0091
S8
S8-2.S 2.SV Precision Reference
lTf019C
S8-4.S 4.5V Precision Reference
lTf019C
lTl019C
S8-5
5V Precision Reference
lTl019C
S8-10 10V PreciSion Reference

SURFACE MOUNT PRODUCTS
>urface Mount Small Outline (SO), DD and SOT Device Packaging
DESCRIPTION

PRODUCT
LTl021DC S8-5
LTl021DC S8-7
LT1021DC S8-10
LT1027DC S8-5
LT1027EC S8-S
S8-1.2
LT1034C
S8-2.S
LT1034C
LT10341
S8-2.5
LT1236AC S8-5
LT1236AC S8-10
S8-1O
LT1236AI
LT1236BC S8-5
LT1236BC S8-10
S8-5
LT1236BI
S8-1O
LT1236BI
LT1236CC S8-5
LT1236CC S8-10
S8-5
LT1236CI
S8-10
LT1236CI
LT1431C
S8
LT1431I
S8
Interface Circuits
LTC485C
S8
LTC4851
S8
LTC486C
SW
LTC4861
SW
SW
LTC487C
LTC487I
SW
LTC488C
SW
LTC4881
SW
LTC489C
SW
SW
LTC4891
LTC490C
S8
LTC4901
S8
LTC491C
S
LTC491I
S
LT1030C
SW
LT1032C
SW
LT1039C
SW16
LT10391
SW16
LT1039C
SW18
LT1080C
SW
LT10801
SW
LTl081C
SW
LT1081 I
SW
LT1130AC SW
LT1131AG SW
LT1132AG
LT1133AG
LT1134AG
LT1134AI
LT1135AG
LT1136AG
LT1137AG
LT1137AI
LT1138AC
LT1139AC

5V Precision Reference
7V Precision Reference
10V Precision Reference
5V S.Oppm Buried Zener Precision Reference
SV 7.5ppm Buried Zener Precision Reference
Micropower Dual Reference: 1.2V, 7V
Micropower Dual Reference: 2.5V, 7V
2.5V Reference, 40ppm/'C Max TC
5V Precision Reference
10V Precison Reference
10V Precison Reference
5V Precision Reference
10V Precison Reference
5V Precision Reference
10V Precision Reference
5V Precision Reference
10V Precision Reference
5V Precision Reference
10V Precision Reference
Programmable Reference
Programmable Reference

Ultralow Power RS485 Transceiver
Ultralow Power RS485 Transceiver
Ultralow Power RS485 Interface Device
Ultralow Power RS485 Interface Device
Ultralow Power RS485 Interface Device
Ultralow Power RS485 Interface Device
Ultralow Power RS485 Quad Receiver
Ultralow Power RS485 Quad Receiver
Ultralow Power RS485 Quad Receiver
Ultralow Power RS485 Quad Receiver
Ultralow Power RS485 Full-Duplex Transceiver
Ultralow Power RS485 Full-Duplex Transceiver
Ultralow Power RS485 Full-Duplex Transceiver
Ultralow Power RS485 Full-Duplex Transceiver
Quad Low Power Line Driver
Quad Low Power Line Driver with Response Time Control
3-DX/3-RX RS232 Transceiver with Shutdown
3-DX/3-RX RS232 Transceiver with Shutdown
3-DXl3-RX RS232 Transceiver
Dual RS232 Transceiver with 5V to ±9V Pump &Shutdown
Dual RS232 Transceiver with 5V to ±9V Pump
Dual RS232 Transceiver with 5V to ±9V Pump &Shutdown
Dual RS232 Transceiver with 5V to ±9V Pump
5-DXl5-RX RS232 Transceiver with 5V to ±9V Pump
5-DX/4-RX RS232 Transceiver with 5V to ±9V Pump
&Shutdown
5-DXl3-RX RS232 Transceiver with 5V to ±9V Pump
SW
3-DXl5-RX RS232 Transceiver with SV to ±9V Pump
SW
4-DX/4-RX RS232 Transceiver with SV to ±9V Pump
SW
4-DXl4-RX 5V RS232 Transceiver
SW
5-DXl3-RX RS232 Transceiver
SW
4-DXl5-RX RS232 Transceiver with 5V to ±9V Pump
SW
&Shutdown
G,SW 3-DX/5-RX RS232 Transceiver with 5V to ±9V Pump &
Shutdown &±10kV ESD
SW
3-DX/5-RX RS232 Transceiver with 5V and Shutdown
G,SW 5-DX/3-RX RS232 Transceiver with 5V to ±9V Pump &
Shutdown
4-DXl4-RX RS232 Transceiver, SV!12V Powered
SW
with Shutdown

DESCRIPTION

PRODUCT
LT1140AC
LT1141AG
LT1180AC
LT1180AI

SW
SW
SW
SW

LT1181AC
LT1237C

SW
G,SW

LT1280AC

SW

LT1281AC
LT12811
LTC1318C
LT1319C
LTC1320C
LTC1321C
LTC1321I
LTC1322C
LTC13221
LTC1323C
LTC1324C
LTC1327C
LT1330G

SW
SW
SW
S
S
S
S
S
S
G,SW
SW
G, SW
G, S

LT1331C
LT1332C
LTC1334C
LTC13341
LTC1335C
LTC13351
LTC1337C
LTC1338C
LTC13381
LT1341G

G,SW
G,SW
SW
SW
SW
SW
G,SW
G, SW
G,SW
G,SW

LT1342C

G,SW

LTC1345C
LTC13451
LTC1346C
LTC13461
LTC1347C

SW
SW
SW
SW
G,SW

LTG1348C
LTC1349C

G,SW
G,SW

LTC13491

G,SW

LTC1350C
LTC13501
LT1381C
LT1381I
LTC1382C
LTC1383C
LTC1384C

G,SW
G,SW
S
S
SW
S
G,SW

LTC1385C

G,SW

LTC1386C
LTC1480C
LTC14801
LTC1481C
LTC1482C
LTC14821

S
S8
S8
S8
S8
S8

5-DXl3-RX RS232 Transceiver with Shutdown
3-DXl5-RX RS232 Transceiver with Shutdown
±1 OkV, 5V RS232 DX/RX with Shutdown, 0.1 i1F
Dual RS232 Transceiver with 5V to ±9V Pump &
Shutdown
Dual RS232 Transceiver with 5V to ±9V Pump
3-DXl5-RX RS232 Transceiver with 5V to ± 9V Pump,
Single RX Keep-Alive &Shutdown
Dual RS232 Transceiver with 5V to ±9V Pump &
Shutdown
Dual RS232 Transceiver with 5V to ±9V Pump
Low Power Dual RS232 Transceiver with 5V to ±9V Pump
Single 5V AppleTalk® DCE Transceiver
Infrared Receiver, Dual Channel
AppleTalk Transceiver
Programmable EIAfTIA562/RS232 and RS485 Transceiver
Programmable EIAfTIA562/RS232 and RS485 Transceiver
Programmable EIAfTIA562/RS232 and RS485 Transceiver
Programmable EIAfTIA562/RS232 and RS485 Transceiver
Single 5V AppleTalk Transceiver
5V Powered Apple/LocalTalk® Transceiver
3V Low Power EIA562 3-DX/5-RX Transceiver
5V RS232 Transceiver with 3V Logic Interface and 1 RX
Active in Shutdown
3-DX/5-RX RS232 Transceiver with 3V-Only Supply
3-DXlS-RX RS232 Transceiver with Low Power
SV Powered Programmable EIAfTIA232/485 Transceiver
SV Powered Programmable EIAfTIA232/485 Transceiver
Programmable EIAfTIA562 and RS485 Transceiver
Programmable EIAfTIA562 and RS485 Transceiver
3-DX/5-RX RS232 Transceiver with flPower
5V Low Power RS232 Transceiver with flPower
SV Low Power RS232 Transceiver with flPower
3-DX/5-RX RS232 Transceiver with Shutdown and
OX Disable
3-DX/5-RX RS232 Transceiver with 3V &5V Logic
Supplies
Single Supply V.25 Transceiver
Single Supply V.35 Transceiver
±5V powered V.35 Transceiver
±5V powered V.3S Transceiver
SV Low Power RS232 3-DX/S-RX Transceiver with S RX
Active in Shutdown
3.3V Low Power RS232 3-DXl5-RX Transceiver
5V Low Power RS232 3-DXl5-RX Transceiver with 2 RX
Active in Shutdown
5V Low Power RS232 3-DX/5-RX Transceiver with 2 RX
Active in Shutdown
3.3V Low Power EIAfTIA562 3-DXl5-RX Transceiver
3.3V Low Power EIAfTIA562 3-DXl5-RX Transceiver
Dual RS232 Transceiver with Narrow 16-Lead SOIC
Dual RS232 Transceiver with Narrow 16-Lead SOIC
5V Low Power RS232 Transceiver
5V Low Power RS232 Transceiver
5V Low Power RS232 Transceiver with 3 RX Active
in Shutdown
3V Low Power EIAfTIA562 Transceiver with 2 RX Active
in Shutdown
RS232 2-DXl2-RX in Narrow SOIC
3V powered RS485 Transceiver
3V powered RS485 Transceiver
Ultralow Power RS485 Transceiver with Shutdown
Low Power RS485 Transceiver with Carrier Detect
Low Power RS485 Transceiver with Carrier Detect

lpleTalk is a registered trademark of Apple Computer, Inc.

L7lJD~

14-45

SURFACE MOUNT PRODUCTS
Surface Mount Small Outline (SO), DD and SOT Device Packaging
PRODUCT
LTC1483C

DESCRIPTION
Low EMI Ultralow Power RS485 Transceiver
with Shutdown
LTC14831
58
Low EMI Ultralow Power RS485 Transceiver
with Shutdown
LTC1484C 58
Low Power RS485 Transceiver w/Fail-Safe Receiver Input
LTC14841 58
Low Power RS485 Transceiver w/Fail-Safe Receiver Input
LTC1485C 58
10Mbitis Low Power RS485 Half-Duplex Transceiver
LTC14851 S8
High Speed RS485 DXlRX
LTC1487C S8
High Input Impedance Ultralow Power RS485
Transceiver with Shutdown
LTC14871
High Input Impedance Ultralow Power RS485
58
Transceiver with Shutdown
LT1537C
G,SW ±15kV ESD Protected RS232 3-DXl5-RX
LT15371
G,SW ±15kV ESD Protected RS232 3-DXl5-RX
Analog SwRehes
LTC201AC S
Micropower, Low Charge Injection, Quad CMOS Analog
Switch
LTC202C
Micropower, Low Charge Injection, Quad CMOS Analog
S
SWitch
LTC203C
Micropower, Low Charge Injection, Quad CMOS Analog
S
Switch
LTC221C
Micropower, Low Charge Injection, Quad CMOS Analog
S
Switch with Data Latches
LTC222C
Micropower, Low Charge Injection, Quad CMOS Analog
S
Switch with Data Latches
High Side SwHehes and DrivelS
LTC1153C S8
Electronic Circuit Breaker
LTC1154C 58
Single High Side MOSFET Switch Driver
LTC1155C S8
Dual High Side MOSFET SWitch Driver
LTC11551 S8
Dual High Side MOSFET Switch Driver
LTC1156C SW
Quad High Side MOSFET Switch Driver
LTC1157C S8
Dua13.3V Supply High-Side MOSFET Switch Driver
LT1158C
SW
Half-Bridge N-ClTannel Power MOSFET Driver
LT11581
SW
Half-Bridge N-Channel Power MOSFET Driver
LT1161C
SW
Quad High Side MOSFET Driver
LT11611
SW
Quad High Voltage, High Side N-Channel MOSFET Driver
LTC1163C 58
Triple 1.8V Supply High-Side MOSFET Switch
LTC1165C S8
Triple 1.8V Supply High-Side MOSFET Switch
LTC1177C S,S-5 High Side Switch Driver
S-12
LTC1255C S8
Dual24V High Side Switch Driver
LTC12551 58
Dual 24V High Side Switch Driver
LTCI477C S8
High Side Switches and Drivers
LTC1478C S8
High Side SWitches and Drivers

14-46

58

PRODUCT
DESCRIPTION
Watchdog Timer/Microprocessor Supervisory
Microprocessor Supervisory Circuit
LTC690C
58
LTC6901
S8
Microprocessor Supervisory Circuit
LTC691C
SW
Microprocessor Supervisory Circuit
LTC691I
SW
Microprocessor Supervisory Circuit
LTC692C
S8
Microprocessor Supervisory Circuit
LTC6921
Microprocessor Supervisory Circuit
S8
SW
Microprocessor Supervisory Circuit
LTC693C
LTC6931
SW
Microprocessor Supervisory Circuit
Microprocessor Supervisory Circuit
LTC694C
58
S8-3.3 3.3V Microprocessor Supervisory Circuit
LTC694C
Microprocessor Supervisory Circuit
LTC6941
S8
58-3.3 3.3V Microprocessor Supervisory Circuit
LTC6941
Microprocessor Supervisory Circuit
LTC695C
SW
S-3.3 3.3V Microprocessor Supervisory Circuit
LTC695C
Microprocessor Supervisory Circuit
LTC6951
SW
LTC6951
5-3.3 3.3V Microprocessor Supervisory Circuit
LTC699C
Microprocessor Supervisory Circuit
S8
LTC6991
58
Microprocessor Supervisory Circuit
LTC1232C 58
Microprocessor Supervisory Circuit
LTC12321
Microprocessor Supervisory Circuit
58
SW
Microprocessor Supervisory Circuit
LTC1235C
LTC12351
SW
Microprocessor Supervisory Circuit
Video Mulilplexers
150MHz, 2:1 Video Multiplexer
LT1203
58
4-lnput Video Multiplexer with 75MHz CFA
LT1204
SW
Dual 150MHz, 2:1 or 4:1 Video Multiplexer
LT1205
5
PCMCIA Power Management
LTl106C
F
!1Power DC/DC Converter for PCMCIA Flash Memory
Cards
Single PCMCIA VPP Regulator
LT1312C
58
LT1313C
Dual PCMCIA VPP Regulator
5
LTC1314C G, S Single PCMCIA VPP SwitclTlVce Driver
LTC1315C G,S
Dual PCMCIA VPP SwitehNee Driver
LTC1470C 58
Single Protected lA PCMCIA Vee Switch
LTC1471C 5
Dual Protected lA PCMCIA Vee Switch
LTCI472C S
Single Protected PCMCIA VPP and Vee Switch

''''''-LlneJ\~Q~___
TAP_E_AN_D_RE_EL

~,

TECHNOLOGY

TAPE AnD REEL SPECIFICATionS-SURFACE mounT
Tape and Reel Packing
Tape and reel packing is available for all SO, SOT-223,
SSOP, TSSOP and DD packages in accordance with EIA
Specification 481-A. Table 1 lists the applicable tape

widths, dimensions and quantitiesforall LTC small outline
products. Consult factory for tape and reel pricing and
minimum order requirements.

Table 1. Tape and Reel Specifications
LTC Package
Code Designator

LTC
Package Style

Number of
Leads Offered

W
Tape Width

P
Component Pitch

Po
Hole Pitch

Reel
Diameter

Units
per Reel

F

TSSOP (0.173)

20

G

SSOP (0.209)

16

16mm

8mm

4mm

13"

2,500

16mm

12mm

4mm

13"

G

SSOP (0.209)

20,24

2,000

16mm

12mm

4mm

13"

1,800

G

SSOP (0.209)

GN

SSOP (0.150)

28

24mm

12mm

4mm

13"

2,000

16

12mm

8mm

4mm

13"

2,500

GN

SSOP (0.150)

20,24

16mm

8mm

4mm

13"

2,500

GW

SSOP (0.300)

36,44

24mm

12mm

4mm

13"

1,000

DO

3,50r7

24mm

16mm

4mm

13"

750

S8

S8 (0.150)

8

12mm

8mm

4mm

13"

2,500

S

S (0.150)

14

16mm

8mm

4mm

13"

2,500

S

S (0.150)

16

16mm

8mm

4mm

13"

2,500

M,Q,R

ST

SOT-223

3

16mm

12mm

4mm

13"

2,000

SW

SW (0.300)

16

16mm

12mm

4mm

13"

1,000

SW

SW (0.300)

18

24mm

12mm

4mm

13"

1,000

SW

SW (0.300)

20

24mm

12mm

4mm

13"

1,000

SW

SW (0.300)

24

24mm

12mm

4mm

13"

1,000

SW

SW (0.300)

28

24mm

12mm

4mm

13"

1,000

Embossed Carrier Dimensions (12mm, 16mm, 24mm Tape Only)
Po ---.lo-J---

TOP COVER
TAPE

B1

1 ~

Ko
SEE NOTE 1

L..-_.:...._-'----.,."--+-_ _ _ _+

bCHINE REFERENCE ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND Bo
USER DIRECTION OF FEED

~------lo.---~

........

CENTER LINES
OF CAVITY

14-47

TAPE AND REEL
TAPE AnD REEL SPECIFICATionS-SURFACE mounT
Embossed Tape - Constant Dimensions
Tape Size
12mm
16mm
24mm

D
+0.10
-0.0

1.5
(0.059)

E
1.75 ±0.10
(0.069 ± 0.004)

Po
4.0 ±0.10
(0.157 ± 0.004)

I(Max.)
0.600
(0.024)

AoBo Ko
See Note 1

~~.~04

Embossed Tape Variable Dimensions
Tape Size
12mm
16mm
24mm

B1 Max.
8.2
(0.323)
12.1
(0.476)
20.1
(0.791)

D1 Min.

F

KMax.

P2

5.5±0.05
(0.217 ± 0.002)
1.5
(0.059)

7.5 ±0.10
(0.295 ± 0.004)

2.0 ±0.05
(0.079 ± 0.002)
6.5
(0.256)

2.0 ±0.10
(0.079 ± 0.004)

11.5±0.10
(0.453 ± 0.004)

Nole 1: Ao Bo Ko are determined by component size. The clearance
between the component and the cavity must be within 0.05 (0.002) min.
to 0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035)
max. for 16mm tape and 0.050 (0.002) min. to 1.00 (0.039) max. for
24mm tape and larger. The component cannot rotate more than 10° within
the determined cavity.

RMIN

14-48

W
12.0 ±0.30
(0.472± 0.012)
16±0.30
(0.630 ± 0.012)
24±0.30
(0.945 ± 0.012)

Nole 2: Tape and components shall pass around radius "R" without
damage.
Note 3: Dimensions are in millimeters (inches) unless otherwise noted.

Bending Radius

BENDING RADIUS
SEE NOTE 2

RMin.
30
(1.181)
40
(1.575)
50
(1.969)

SMP14

TAPE AND REEL
TAPE AnD REEL SPECIFICATionS-SURFACE mounT
Component Rotation
10" MAXIMUM
COMPONENT ROTATION

TYPICAL
COMPONENT CAVITY
CENTER LINE

TYPICAL
COMPONENT

~ CENTERLINE

Tape Camber (Top View)
100mm
1-------(3.937) - - - - - - . 1

ALLOWABLE CAMBER TO BE 1mmllOOmm NONACCUMULATIVE OVER 250mm

Tape Leader (StartJEnd) Specification
CARRIER TAPE
START

IL

160mm (6.30) MIN

+ +
COMPONENTS

EMPTY COMPONENT POCKETS
SEALED WITH COVER TAPE

390mm (22.05)
(15.35) MAX
MIN
560mm

-II

a

EMPTY COMPONENT POCKETS
SEALED WITH COVER TAPE

USER DIRECTION OF FEED

14-49

TAPE AND REEL
TAPE AnD REEL SPECIFICATionS-SURFACE mounT
S1
S01-223 Devices

o

0

0

0

0

0

0

0

ecce
USER DIRECTION OF FEED

M,Q,R
DD Pak Devices

o

0 0 0 0 0 0 0 0 000

USER DIRECTION OF FEED

F, G, GN, GW, S8, S, SW
SSOP, 1SS0P Devices
I

I

I

I

I

I

I

I

I

Ef)-Ef)-Ef)-Ef)-Ef)-Ef)-Ef)-Ef)-Ef)-

:8 ]8:]8~ 8
cO

]

~~~~
USER DIRECTION OF FEED

14-50

I

SMPt9

TAPE AND REEL
REEL DimEnSionS-SURFACE mounT
Direction of Feed

Reel Dimensions
--jI

I-

W

2
(MEASURED
AT HUB)

40mm (1.575) MIN
ACCESS HOLE AT
SLOT LOCATION

LJF;,
D":~
til
"
-r::-~;

A

\

C

-~ - I

~

I

N

-~

FULL RADIUS"
TAPE SLOT IN CORE
FOR TAPE START
2.5mm (0.098) MIN WIDTH
10mm (0.394) MIN DEPTH

"DRIVE SPOKES OPTIONAl. IF USED,
ASTERISKED DIMENSIONS APPLY.

G (MEASURED AT HUB)---II.-

TAPE
SIZE
12mm

A
MAX
330
(12.992)

C

0*

MIN
1.5
(0.059)

13.0 ±0.20
(0.512 ± 0.008)

MIN
20.2
(0.795)

N
MIN
50
(1.969)

16mm

330
(12.992)

1.5
(0.059)

13.0 ±0.20
(0.512 ± 0.008)

20.2
(0.795)

50
(1.969)

24mm

330
(12.992)

1.5
(0.059)

13.0±0.20
(0.512 ± 0.008)

20.2
(0.795)

50
(1.969)

B

G
MAX
12.4 ~ 6·~
( 0.488

164 + 2.0
. -0.00
( 0.646

~ ~:~~8 )

244 + 2.0
. -0.00
( 0.961

Vletric dimensions will govern.

~ ~:~~8 )

~ ~:~~8 )

W2
MAX
18.4
(0.724)
22.4
(0.882)

30.4
(1.197)

Note 1: All dimensions in millimeters (inches) unless otherwise noted.
Note 2: English measurements rounded and for reference only.

14-51

TAPE AND REEL
TAPE AnD REEL SPECIFICATlonS-TO·92
TO-92 Tape Dimension

TO-92 Reel Dimensions

Table 1
SYMBOL
D
H

Hl
H4
P
PO

Pl
P2
S
W

Wl
Fl, F2

DESCRIPTION
Sprocket Hole Diameter
Length from Seating Plane
Sprocket Hole Location
Component Base Height
Sprocket Hole Pitch
Pitch of Component
Lead Location
Center of Seating Plane Location
Component Lead Spacing
Carrier Tape Width
Adhesive Tape Width
Lead-to-Lead Distance

DIMENSION (mm)
4±0.2
16±0.5
9±0.5
20 Max
12.7±0.2
12.7±0.5
3.85 ±0.5

6.35 ±Oo4

."
356mm
"TV?

..........

.... ,

,,

,
•

5 +8, -0.2
18+1,-0.5
6.0 ±1.0
2.5 +004, -0.1
TO-92"

14-52

TAPE AND REEL
TAPE AnD REEL SPECIFICATlonS-TO·92
Tape Orientation on Reel

Ammo Pak Tape Orientation Inside Box

LABELS
ON THIS SIDE
OFBOX

Package Orientation on Tape
STYLE E: Standard
(Flat Side of Package Faces Toward the Adhesive Tape)

STYLE A: Special Lot
(Rounded Side of Package Faces Toward the Adhesive Tape)

CARRIER
TAPE

14-53

f-Y"'"tlnt:f\Q
TECHNOLOG~IY------

TO-220 LEAD BEND OPTIONS

~,
Introduction

On the following pages are a variety of lead bend options
available for TO-220 packages from Linear Technology
Corporation. The special adders, flows, and minimums
that have been established for these lead bend options are:

It is important to remember orders for these nonstandard
flows require a minimum gO-day notification for cancellation or rescheduling. Also note that special flow orders for
U.S. distribution must be approved in advance.

Flows 30 to 37 Special Lead Bends for TO-220
(Minimum Order: 1,000 units)
Special lead bends subject
1,000 to 4,999 units
to additional charges and
5,000 to 9,999 units
order conditions. Contact
10,000 to 24,999 units
LTC, Sales/Marketing for
more information.
> 25,000 units

TO-220 5-Lead Package Outline (Flow 30)

0.390-0.415

(9.906-10.541)---I+----~

ri

0.165 - 0.180
(4.293 - 4.572)

~

EATING
PLANE
0.045 - 0.055
(1.143-1.397)

r

0.600 - 0.620'
(15.240 -15.748)

0.095-0.115
(2.413 - 2.921)

I

III
~

0.057-0.0n
(1.448 -1.956) 0.028 - 0.038
(0.711 - 0.965)

JL

'MEASURED AT SEATING PLANE
T5{FLOW30)DBS6

14-54

TO-220 LEAD BEND OPTIONS
TO-220 5-Lead Package Outline (Flow 31)

0.390-0.415

(9.906-10.541)-!-<----~

0.147 - 0.155
(3.734 - 3.937)
DIA

-I
0.565 - 0.585 '
0.025R
(0.635)
1YP

"'"T'~
0.057-0.077 - I
(1.448 -1.956)

I-J

(~~~: =~~~~)

0.135 ± 0.010'
(3.429 ± 0.254)

I

-

'MEASURED AT SEATING PLANE

-(101~g3)
1YP

TO-220 Head Package Outline (Flow 32)

0.390-0.415
(9.906 -10.541) ~----~

0.147 - 0.155
(3.734 - 3.937)
DlA

0.165-0.180
(4.293 - 4.572)

T5(TO·220)(FLOW31)S9S

r&
~

0.045 - 0.055
(1.143-1.397)

0.045 ± 0.020
(1.143 ± 0.508)

~ ~I
r-~
0.090-0.110
(2.286-2.794) -

I

~II
0.055 ±0.010
(1.397 ±O.254)

--

0.020±0.010
(0.508±0.254j

__ 0.013-0.023
(0.330 - 0.584)
T3ITO·2201IFLOW32jOO95

II
14-55

TO-220 LEAD BEND OPTIONS
10-220 Head Package Outline (Flow 33)

0.390-0.415

(9.906-10.541)+----~/

0.147-0.155
(3.734 - 3.937)
DIA

0.165 -0.160
(4.293 - 4.572)

nt
--I

0.045 _ 0.055
(1.143-1.397)

0.045 ± 0.020
(1.143 ± 0.506)

LJ

=-Ii-- 0.020±0.010

t~

0.057 - 0.077
(1.446 -1.956)

--I

I

(0.506 ± 0.254)

~i-- 0.013-0.023
0.055 ± 0.010
(0.330 - 0.564)
(1.397 ± 0.254)
i5($Uflfi!.CE)0694

TO-220 3-Lead Package Outline (Flow 34)

0.390-0.415
(9.906-10.541)

0.147-0.155
(3.734 - 3.937)
DlA

0.165 -0.160
(4.293 - 4.572)

rJ-I
~

EATING
PLANE
0.045 - 0.055
(1.143-1.397)

0.570 + 0.015'

JO~"
0.095-0.115
(2.413 - 2.921)

0.120 ± 0.007
(3.046 ± 0.176)
'MEASURED AT SEATING PLANE

14-56

= t 0.100 ± 0.010'
---.-l(2.540 ± 0.254) t

W

0.013 - 0.023 j
(0.330 - 0.564)
T3(TO-220}(FLOWM)695

TO-220 LEAD BEND OPTIONS
10-220 Head Package Oulline (Flow 35)

0.390 - 0.415
(9.906-10.541) +~---~

0.045 ± 0.020
(1.143±0.508)

LJ

=..j k-

t~

0.040 - 0.060
(1.016-1.524)

1

0.020±0.010
(0.508±0.254)

T----=:i 1_

-I

0.013 - 0.023
(0.330 - 0.584)

0.055 ± 0.010
(1.397 ± 0.254)

T7(,ro-220)(FLOW35)0694

10-220 3-Lead Package Oulline (Flow 36)

0.390 - 0.415

(9.906-10.541)+----~

0.165 --0.180
(4.293
4.572)

I!
-I

0.090-0.110 . I
(2.286-2.794)---'

J

Jt

~

0.028 - 0.038
(0.711 - 0.965)

0.045 - 0.055
(1.143 -1.397)

r-- (1.270)
0.050

l

0.22
(5.60)
TYP

0.013 - 0.023
(0.330 - 0.584)

TYP

13(TO-220)(FLOW36)695

II
14-57

TO-220 LEAD BEND OPTIONS
17 Head Package Outline (Flow 37)
0.390-0.415
(9.906-10.541) -+<----~

0.147-0.155
(3.734 - 3.937)
DIA

0165-0.180 IlEATING PLANE
(4293 - 4.572)
0.045 - 0 055
---1
(1.143-1.397)

i

~

0.600 - 0.620'
(15.240-15.748)
0.025R
(0.635)

0.095-0.115
(2.413 - 2.921)

il J L

0.057 - 0.067 _I
(1.448-1.702)
0.026 - 0.036
(0.660-0.914)

'MEASURED AT SEATING PLANE

TVP

0.140-0.160'
(3.556 - 4.054)
0.110
(2.794)
MIN

0.013 - 0.023
(0.330 - 0.584)

-(lOi~~~)TVP

14-58

T7[TO-nGl(FLOW37)0695

SECTion 15-APPEnDICES

15-1

INDEX
SECTION 15-APPENDICES
INDEX ....................................................................................................................................... 15-2
INTRODUCTION TO QUALITY AND RELIABILITY ASSURANCE PROGRAMS ...................................................... 15-3
ISO 9001 QUALITY MANUAL ........•...........................................................•........••....•........•.......•........ 15-5
RELIABILITY ASSURANCE PROGRAM ................................................................................................ 15-30
QUALITY ASSURANCE PROGRAM .................................................................................................... 15-46
Wafer Fabrication Flowchart ....................................................................................................... 15-52
Assembly Flowchart ................................................................................................................. 15-61
Test and End-o'-Line Flowchart ................................................................................................... 15-65
R-FLOW ................................................................................................................................... 15-66
ESD PROTECTION PROGRAM ......................................................................................................... 15-67
STATISTICAL PROCESS CONTROL ................................................................................................... 15-78
DICE PRODUCTS ........................................................................................................................ 15-81
DESIGN TOOLS .......................................................................................................................... 15-83
Application Notes .................................................................................................................... 15-83
Design Notes ......................................................................................................................... 15-87
Applications on Disk ................................................................................................................ 15-90
Technical Publications ............................................................................................................. 15-90

15-2

''''''''-unt:f\Q

~,

INTRODUCTION

TECHNOLOG~f\(------

Quality and Reliability Assurance Programs
Linear Technology Corporation (LTC) has a wide-ranging
program integrating vendor participation, design
engineering, and manufacturing to produce the most
~eliable and highest quality linear integrated circuits
available on the market. Our modern manufacturing
facility in Milpitas, California is DESC Class Sand Class B
line certified; MIL-I-38535 QML transitional certified, and
ISO 9001 certified. We have successfully completed over
90 major OEM quality system surveys to MIL-Q-9858 and
MIL-I-45208 including achieving several major customer
quality awards. Our Quality and Reliability Assurance
Programs are summarized below:
• Wafer Fabrication - Amodern class 100 area modular
clean room construction with full environmental
monitors. Emphasis is placed on statistical process
control, CV plots, SEM monitors and on our proprietary
dual layer passivation system.
• SPC (Statistical Process Control) - LTC is committed
to SPC as the cornerstone of our continuous quality
improvement and Total Quality Management System
(TQMS) programs. SPC is fully implemented in all
manufacturing areas.
• Assembly and End ofUne-lncoming inspection of a"
materials and piece-parts, line surveillance and process
control monitors.
• Testing - Incoming inspection and acceptance of all
offshore lots prior to release to test. LTX and Eagle
testers, multipass testing with closed-loop binning to
reduce outgoing electrical defective levels. Many "beyond
data sheet" tests and full temperature QA lot buy-ofts are
performed as standard processing.
• Traceability - Abackside or side mark is placed on all
units, where space permits, to give information on each
unit to identify the wafer fab lot, assembly, end of line
(e.o.l.) and test lots. The information provided exceeds
the seal week traceability control required by MIL-STO883.
• ESD (Electrostatic Discharge) - A full program is in
place from design through manufacturing. Products are
fully characterized to MIL-STO-883 (Method 3015) and
strict controls on handling and packaging are observed.

• Training and Certification - Operator training has
been established for all operations and recertification is
performed every 6 months.
• Major Change Control - Major change controls are
in place to notify our customers in accordance with
MIL-I-38535, LTC internal specifications, or specific
customer specifications as required.
• Quality Assurance - Full monitoring and reporting of
quality data with emphasis on Statistical Process Control
(SPC) charts and continuous quality improvement. Refer
to our section on Quality Assurance Program.
• Failure Analysis and Reporting - Afull analytical lab
and formal program exists to record, analyze and take
appropriate corrective action on all returns. A report is
generated and sent to the customer stating our findings
and action.
• Reliability Flows - LTC reliability flows include Class
Sand Class BJAN-3851 0, Standard Military Drawings
(SMD), DESC Drawings, 883, R-Flow, LTC proprietary
Hi-Rei Radiation Hardered (RH) products, and Hi-Rei
(Source Controlled Drawings). In addition, specialized
processing such as SEM, PIND and other tests can be
performed as required.
• Reliability Monitor - LTC has a unique reliability
structure built into each wafer that is used to obtain
rapid feedback on reliability. This data is obtained in less
than one week, versus 40 weeks for a typical reliability
audit. See the LTC Reliability Assurance Program for
more details. LTC has a comprehensive Quick Reaction
Reliability (QR2) monitor program for plastic packaged
devices. A variety of tests are performed on every oneweek date code, for every package type and lead count
and real time feedback to the assembly facilities.
• Reliability Reporting - Data is gathered on a monthly
basis for selected process technology/product family/
package combinations. This data is summarized each
quarter and published in aReliability Data Pack showing
Operating Life, 85/85, HAST, Autoclave, Temperature
Cycle, Thermal Shock, 883 Group C, and 883 Group D
summary data. Copies of Reliability Data Pack summaries
are available by writing or calling Linear Technology
Corporation, 1630 McCarthy Blvd., Milpitas, CA 95035. ~
1-800-4-LlNEAR (1-800-454-6327).
...

15-3

INTRODUCTION

O""~)'

\ ..I;",~tru.U~

CERTIFICATE
~
Tl'llInJv.~e.1l
Linear 'nIchnology Corporation

..__.

"""""--....

*-'....--~-

M _ _ ...-......... No.

_

P_'", _ _ IJIII,"'''''i _ _ ''''''
DIN 180 90011 EN 29001

-"'11l1li10<1

lllo_III_ _

...

~":",=""No.

15-4

ISO 9001 QUALITY MANUAL

cf@~~
CERTIFICATE
1~~JiI
The TOV-Zertifizierungsgerneinschaft e.v.
hereby certifies that

Linear Technology Corporation
Milpitas, CA

has established and applies
a quality system for
Design and manufacturing of • broad line of
high performance linea, Integrated clrculta
An audit was performed, Report No.
3088
Proof has been furnished that the requirements according to

DIN ISO 9001 I EN 29001
are fulfilled.
The certificate is valid until
March31,1898
Certificate Registration No.
091003098

Bonn.07.oe.ll1t3

A

~07.oe.,_

TOV Rheinland
Gruppe

Specification 06·09-0005, REV. E

.L7lJ!J~

15-5

ISO 9001 QUALITY MANUAL
QUALITY, RELIABILITY, AND SERVICE
POLICY STATEMENT
Th~

cornerstone of Linear Technology's Quality, Reliability, & Service (QRS) Program is to
achIeve 100% customer satisfaction by producing the most technically advanced product with the
best quality, on-time delivery, and service. Top management is fully committed to this goal. but to
achieve this goal requires the involvement and dedication of every employee.
Since 1983 when the fll"St product was shipped. Linear Technology has achieved numerous
accomplishments in the area of quality and service, among which are:
• 1st company in the industry to achieve the Department Of Defense line certification for
Mll...-M-38S10 Class B products dming its first audit in 1984.
• Among the first group of manufacturers to be certified in the Ship-To-Stock Program at
Compaq Computers in 1986.
• 1st company in Silicon Valley to achieve the Ford Ql Award for Excellence in Quality in
1988.
The above achievements were made possible by the commitment and dedication of employees who
pay attention to details and whose motto is "Do thejob right thefirst time" .
Customer requirements and expectations in the areas of Quality and Service are becoming
increasingly more demanding. Linear Technology not only intends to 1Met those requirements and
expectations for survival, but also to exceed them to maintain a world-class leadership position.
The standard will be error-free products and error-free perfonnance. This standard commits all of
Linear Technology's employees to a QRS Policy that takes precedence over all other considerations
and leaves no room for error or failures. LTC's goal is zero defects.

Robert SWtJlIIOII
President fJ1Id Chief Executive OJ'Jicer

Pau' ChalltaliJt
Vice Pruidenl of Quality fJ1Id Reliability

Specification 06-09-0005, REV. E

15-6

."·"llnt:1\12

I1

, .. . .I11

~,

ISO 9001 QUALIlY MANUAL

TECHNOLOGY~~-------

QUALITY SYSTEM FOR DESIGN, DEVELOPMENT,
PRODUCTION, AND SERVICING

o INTRODUCTION

3.0 DEFINITIONS

This policy defines the organization and policies of Linear
Technology Corporation (LTC) and assures conformance to
requirements during design, development, production,
testing, inspection and shipment of products. It sets out the
general quality policies, procedures and practices of LTC.

For the purpose of this quality manual, the definitions given
in ISO 8402 shall apply.
Below is a list of acronyms used by LTC:
CMR
Customer Material Return
CSI
Customer Source Inspection
01
De-Ionized
DMR
Discrepant Material Report
DRC
Design Rules Check
ECN
Engineering Change Notice
EOL
End-of-Line
F/A
Failure Analysis
GAUGE R&R Gauge Repeatability and Reproducibility
GSI
Government Source Inspection
IFR
Inspection Failure Report
IQC
Incoming Quality Control
MPS
Material Procurement Specifications
MRB
Material Review Board
MSE
Measurement System Evaluation
OCAP
Out-of-Control Action Plan
PO
Purchase Order
PAT
Process (or Preventive) Action Team
PG
Pattern Generation
QA
Quality Assurance
QAP
Quality Assurance Policy
QAR
Quality Audit Report
QCT
Quality Control Teams
RMA
Return Material Authorization
RPL
Released Product Listing
SL
Special Lot
SOP
Standard Operating Procedure
SPC
Statistical Process Control
SSS
Stop/Start Sheet
TECN
Temporary Engineering Change Notice
TML
Top Mark Layout
TOMS
Total Quality Management System
VCAR
Vendor Corrective Action Request

1.0 SCOPE
The requirements specified in this Quality Manual are
designed to prevent and detect any nonconformances during
design, development, production, testing and inspection.

2.0 FIELD OF APPLICATION
The Quality Program specified herein is designed to ensure
100% customer satisfaction by ensuring product
conformance to achieve and maintain the highest level of
product quality and reliability and to ensure a program for
continuous improvement. This manual applies to all
manufacturing locations and to all military and commercial
products manufactured by LTC.

REFERENCES
ISO 8402
ISO 9000

Quality Vocabulary
Quality Management and Quality Assurance
Standards: Guidelines for Selection and Use

ISO 9001

Quality Systems: Models for Quality Assurance in
Design/Development, Production, Installation and
Servicing

ISO 9002

Quality Systems: Model for Quality Assurance in
Production and Installation.

ISO 9004

Quality Management and Quality System Elements
Guidelines

ISO 10011-1

Guidelines for Auditing Quality Systems, Part 1

ISO 10011-2

Guidelines for Auditing Quality Systems, Part 2

ISO 10013-3

Guidelines for Auditing Quality Systems, Part 3

ISO 10012-1

Quality Assurance Requirements for Measuring

Specification 06-09-0005, REV. E

15-7

ISO 9001 QUALITY MANUAL
4.0 QUALITY SYSTEM REQUIREMENT
LTC's Total Quality Management System (TQMS)
encompasses the concept of strategic Quality planning and
management to ensure a program of continuous Quality and
reliability improvement.
The Quality system is designed to meet the requirements of:
•
•
•
•
•
•
•
•
•
•
•

ISO 9001
MIL-STD-883
MIL-STD-976
MIL-M-38510 (Class B and Class S)
MIL-I-38535, Appendix A
MIL-I-45208
MIL-STD-45662
MIL-Q-9858
ANSIINCSL Z540-1-1994
Our commercial customers
Our goal of defect-free products

LTC pledges that its products shall be manufactured in
accordance with the applicable specifications or to specific
customer requirements.

4.1 MANAGEMENT RESPONSIBILITY
LTC's management with executive responsibility shall ensure
that the Quality policy is understood, implemented, and
maintained at all levels in the organization.

4.1.1 Quality Policy
See Policy Statement in the front of this manual.

4.1.2 Organizational Chart
A current organizational chart showing senior management
and the organizational reporting structure is available upon
request from the secretary of the Vice President of Finance.

LTC Organizational Chart
.~-.--"

--1:

.... "" ..

Boardo!
Directors

"""-;'

:
[----------------------------------

~ ........................... J

President

&C.E.O.
' - - _ - - ,_ _- - '

Specification 06·09·0005. REV. E

15-8

ISO 9001 QUALITY MANUAL
4.1.2.1 Responsibility and Authority
A) All employees in this organization have the authority to
initiate action to prevent the occurrence of product,
process, and quality system nonconformity by notifying
the appropriate support or management personnel.
B) Inspectors have the responsibility to identify and record
product and process problems via a Stop/Start or
Inspection Failure Report.
C) Any employee in the organization has the organizational
freedom and authority to initiate, recommend, or provide
solutions relating to product, process and quality system
nonconformances.
D) Engineering, Quality Assurance and management have
the responsibility to verify the implementation of
solutions.
E) Any employee in the factory that is running a process at
an SPC location has the responsibility to suspend an
operation in the event of an out-of-control process orto
control further processing in accordance with the
associated Out-of-Control Action Plan (OCAP) by issuing
a Stop/Start.
Quality Assurance, Engineering, Production Control and
Customer Service have the responsibility to suspend or
control the f~rther pr?~essing and delivery of nonconforming
product until the defiCiency or unsatisfactory condition has
been corrected. This can be done via the issuance of a Stop/
Start or Inspection Failure Report (IFR) via an ECNITECN to
a specification or via a ship-hold.

4.1.2.2 Verification Resources and Personnel
All verification activities and requirements shall be
documented in the appropriate standard operating
procedures (SOP) or detailed specifications to include
inspection, test, and monitoring of the design, production,
and product. Design reviews and audits ofthe quality system,
processes, and/or product shall be carried out by personnel
independent of those having responsibility for the work
being performed.
All verification personnel are required to be trained and
certified perthe LTC training and certification program (spec
06-09-0002 and 05-06-0007), and records of training are to
be maintained. Adequate resources shall be identified and
assigned forthe areas of management, performance of work
and verification activities, including internal quality audits.

4.1.2.3 Management Representative
The Manager of Quality Assurance and Reliability has the
authority and responsibility for ensuring thatthe requirements
of this Quality Manual are implemented and maintained.

A multidisciplinary approach is used for decision-making
and to manage concept development through production
and shipping.

4.1.3 Management Review
The Quality and Reliability Manager shall assure that the
effectiveness of the quality system is reviewed and reported
on, as shown below:
A) Annual strategic quality planning and goal setting to
drive continuous quality and reliability improvement
programs. This meeting is held at the beginning of each
fiscal year with all department heads participating. The
resulting goals are reviewed and approved by the
management.
B) Quarterly management review of company performance
vs. the Corporate Quality goals. The performance to
goals is summarized by the Quality Assurance manager
and distributed to the department heads. Semiannual
reviews are distributed to the President and Vice
Presidents.
C) Quality systems audit results shall be reviewed annually
and at the end of each period by middle and upper
management to determine the adequacy of, and
compliance to, the documented quality system. Upper
management includes the COO and President/CEO.
D) Quarterly Cpk reports of all critical process nodes by the
SPC Manager.
E) Monthly QA reports to management including the
President and COO, to report detailed results and trend
analysis of QA monitors and gates.
F) On areal-time basis, the following reviews and/or actions
are performed:
* Quality system audit results shall be reviewed to
determine the effectiveness of the quality system.
* Failure analysis, root cause identification, and
corrective action.
* Customer request for corrective action.
* Process/Preventive Action Teams (PATs) findings
and recommendations.
* Review of nonconforming material/product reports.
G) The Quality Manual and/or procedures shall be revised
when necessary to reflect the decisions of management
reviews.
H) Records of all reviews shall be maintained forevaluation
as required.
'

Specification 06~09-0005, REV. E

15-9

ISO 9001 QUALITY MANUAL
4.2 QUALITY SYSTEM
4.2.1 General
The quality system of LTC consists of the Quality Manual,
quality procedures for inspection, surveillance, and
monitoring to ensure that our products conform to customer
requirements.

4.2.2 Quality System Procedures
Documented and implemented procedures consistent with
the requirements of ISO 9001 and stated quality policy shall
form a part of the quality system.

4.2.3 Quality Planning
The system is designed to meet the requirements of ISO
9001, and the other requirements outlined in Section 4.0.
The quality planning process covers all processes from
incoming inspection through shipping.
Quality planning includes:
A) The preparation of quality plans in accordance with the
specific requirements.
B) The identification and acquisition of any controls,
processes, inspection equipment, fixtures, and total
production resources and skills that may be needed to
achieve the required quality.
C) Ensuring the compatibility of the deSign, the production
process installation, servicing, inspection and test
procedures, and the applicable documentation.
D) The updating, as necessary of quality control; inspection,
and testing techniques, including the development of
new instrumentation.
E) The identification of any measurement requirement
involving capability that exceeds the known state of the
art in sufficient time for the needed capability to be
developed.
F) The identification of suitable verification at all required
test, and inspection gates.
G) The clarification of standards of acceptability for all
features and requirements, including those which contain
a subjective element (Le., workmanship standards).
H) The identification and preparation of quality records.
(For records, see Section 4.16.)

REFERENCES
Spec Number Title
06-03-5000

Customer Specification Review

06-03-5001

Internal SL Specification Procedure

06-04-0011

Design to RPL Flowchart

00-01-1006

SOP: Engineering Change Notice

08-07-1001

Calibration Program Requirements

05-03-8082

Assembly Workmanship Standards

06-03-7050

Record Keeping

4.3 CONTRACT REVIEW
4.3.1 General
Documented procedures shall be implemented and
maintained for the performance of contract review and for
the coordination of these activities.

4.3.2 Review
Prior to acceptance of acontract or order, it shall be reviewed
in accordance with the referenced specifications herein,
resolving issues, and determining the capability of the
organization to meet customer requirements. Any differences
identified during contract review will be documented and
defined by an "SL" (Specified Lot) or by aspecial flow perthe
specifications below. If LTC cannot agree to any portion of
the contract, a waiver agreement must be approved by the
end-customer before the product is delivered.
(For records, see Section 4.16.)

REFERENCES
Spec Number Tille
06-03-5000
Customer Specification
06-03-5001

SL (Special Lot) Specification Procedure

Current Rev.

Device Catalogs, Data Book, Supplements

4.4 DESIGN CONTROL
4.4.1 General
LTC produces a broad line of standard, high performance
linear integrated circuits which are defined in the marketing
catalogs and data books. Design criteria and manufacturing
capabilities have been established to support these products.
(For records, see Section 4.16.)

4.4.2 Design and Development Planning
LTC Spec 06-04-0011 provides a guideline flowchart from
design conception to product qualification and RPL. Since
LTC manufactures primarily standard products, as opposed
to custom products, there is no need to establish milestone
Specification 06-09'()005. REV. E

15-10

ISO 9001 QUALITY MAN UAL
charts forthe customer. Design and verification activities are
planned and assigned to qualified personnel equipped with
adequate resources.

4.4.3 Organizational and Technical
Interfaces
Adesign review meeting is held weekly with engineering and
management to review the status, document progress, and
technical requirements of each design.

4.4.4 Design Input
Inputs for design typically come from review of customer's
requirements, contract review, and marketing research to
. identify featu res which should be incorporated into aproduct.
The primary goal is to provide customers with designs that
reducetheircomponentand board level costs, while providing
leading edge technology. LTC manufactures primarily
standard (non-custom) products. Based on the above inputs,
the final design concept is developed in-house.

4.4.5 Design Output
The design output, an integrated circuit, is defined and
described in a data sheet, which is released when the
product is qualified. Product characterization and qualification
are conducted to verify conformance to data sheet
requirements.
The data sheet specifies the product performance limits as
well as any other pertinent information pertaining to the
product, e.g., design considerations that are critical in the
safe and proper functioning of the product, regulatory
requirements, etc.

4.4.6 Design Review
Design shall plan, conduct design reviews which are
documented, and assigned to competent personnel
representing all applicable functions.

4.4.7 Design Verification
Design verification shall establish thatthe product meets the
data sheet requirements. Since the products designed by
LTC are proprietary products (defined by LTC), LTC may
change the final data sheet to match the characterization
results prior to release. This further ensures that the design
input matches the design output.

4.4.8 Design Validation
Design validation shall be performed prior to release to
ensure that the product conforms to design requirements in
accordance with Quality Assurance and Reliability Assurance
Qualification requirements, 06-04-0001.

4.4.9 Design Documentation
The identification, documentation, and appropriate review
and approval of all changes and modifications are
accomplished via ECNs to the Mask Sequence Specification,
02-01-xxxx.
Design changes are controlled via LTC-supplied designs and
bills of material to subcontractors.
(For records, see Section 4.16.)
REFERENCES (Company proprietary)
Spec Number Tille
80-01-xxxx

CMOS Design Rules

80-02-xxxx

Bipolar Design Rules

02-01-xxxx

Mask Sequence Specifications

02-02-1 000

LTC Milpitas Fab New Product Documentation
Requirements

02-02-1002

LTC Product Release to Fab Procedure

05-01-xxxx

Assembly Bonding Diagram and Bill of Materials

06-04-0001

Quality Assurance/Reliability Assurance Qualification
Requirements

06-04-0011

Design to RPL Flowchart

09-01-0001

Released Product ListingITop Mark Content and
Layout Procedure

4.5 DOCUMENT AND DATA CONTROL
4.5.1 General
Documented and implemented procedures shall govern the
control of all documents and data relating to the quality
system.

4.5.2 Document and Data Approval and Issue
Pertinent issues of appropriate documents are available at
all locations where operations are essential to the effective
functioning of the quality system. Any initiation or change of
the docu mentation req uired for procurement, manufacturing,
and inspection of materials and product is controlled by the
Document Control department to ensu re review and approval
by authorized personnel prior to issue.
Data associated with this Quality System shall be maintained
and documented per Section 4.16, Control of Quality Records.
The Document Control group is responsible for the
maintenance, control, reproduction, distribution and
historical archiving of all of LTC's product and procedural
documentation. Document Control services all internal
areas in which Document Control Books (DCBs)
are located, per the internal specifications listed on
following page:

Specification 06-09-0005, REV. E

15-11

m

ISO 9001 QUALITY MANUAL
REFERENCES
Spec Number Tille
00-01-0010

Specification 10 Master Plan

00-01-0005

Temporary Engineering Change Notice Procedure

00-01-1006

Standard Operating Procedure (SOP): Engineering
Change Notice

00-01-1008

SOP: Specification Format and Organization

00-01-3100

ECN Approval Matrix

00-01-0001

Standard Operating Procedure: Document Control

00-01-0003

Distribution of Levell Specifications

00-01-3111

DCB Locations Report

4.6 PURCHASING
4.6.1 General
Purchasing shall ensure that material purchased from
suppliers and subcontractors is in conformance to specified
requirements. Records of qualified suppliers shall be
maintained.

4.6.1.1 Supplier Responsibility
It is the responsibility of the supplier to provide and maintain
a quality system which will assure compliance with the
requirements of the applicable material procurement
specification, 01-xx-xxxx and the specifications listed below.

4.5.3 Document and Data Changes

REFERENCES

Document Control shall promptly post or route ECNs
(Engineering Change Notices) and TECNs (Temporary
Engineering Change Notices) to the appropriate locations
when ECN approval is complete. The information on the
ECN shall contain, as a minimum, the affected document
number, description of the change, effective date and
duration, affected documentation, justification for the
change, documentation of material disposition, distribution,
and approval signatures.
Previous revision history is available from the Document
Control department. Additional justification and background
information shall be provided by the ECN originator upon
request of the deSignated Signatory.
Document Control maintains a Master Spec Listing which
includes the revision letter, effectivity date, specification
number, product number (when applicable), and title. See
00-01-0001, SOP: Document Control.
When any change is made, LTC's standard practice is to
generate an ECN or TECN to aspecification or process. Each
time an ECN or a TECN is generated, the revision changes
and spec copies are reissued to all required Level 1 and Level
2 Document Control Book locations within the factory and all
satellite locations as called out on the document footer.

Spec Number Tille

REFERENCES
Spec Number Tille
00-01-1006

SOP: Engineering Change Notice

00-01-3100

ECN Approval Matrix

00-01-1008

SOP: Specification Format and Organization

00-01-0005

Temporary Engineering Change Notice

00-01-0001

SOP: Document Control

06-09-0003
01-xx-xxxx

Purchasing Procedure

09-01-0004

Qualified Vendor Listing Procedure

09-01-0008
06-01-0011

Approved Subcontractor Listing
Vendor Corrective Action

06-09-0018

SOP: Inventory Control

Material Procurement Specification

06-01-0006

Incoming Inspection, General

06-01-0007

Incoming Inspection, Subcontracted Materials

01-xx-xxxx

Applicable Drawing And Stores Item Numbers

4.6.2 Assessment of Subcontractors
Selection of sources to be qualified will be made upon the
supplier's ability to conform to agreed upon requirements
for quality, cost, delivery, and based upon previous
performance.
LTC exercises tight control over critical subcontractors to
prevent field reliability problems. The effectiveness of these
controls is continually assessed through on-site engineering
surveillances, incoming inspection results, reliability monitor
results, and subcontractor-supplied SPC and Cpk data. This
is defined in Specification 06-01-0020.
Previously qualified suppliers may continue to be used as
long as they demonstrate the capability to meet all conditions
and requirements.
Suppliers and subcontractors are granted approval after
qualification testing and inspection of materials purchased
under preliminary approval status. A monthly record of
approved suppliers' and subcontractors' history is maintained
and updated after completion of inspections and the
disposition of all lots.

Speefflcation 116-09·0005. REV. E

15-12

ISO 9001 QUALITY MANUAL
:;uppliers and subcontractors that consistently demonstrate
lxceptionally high acceptance rates will become candidates
or participation in the Preferred Vendor Program.
Jetermination of suitability will be based on the following:
\) Consistently high acceptance rate through Incoming
Inspection.
3) No field-related problems.
~) Recommendation by LTC's Preferred Vendor Board
after reviewing the survey results from the vendor.
J) Willingness onthe partofthe supplierto provide periodic
statistical data on the critical nodes/parameters that
have been identified.
:) Suppliers and subcontractors that qualify for the
partnership program will be placed on a reduced
surveillance schedule, and they will be awarded agreater
share of the business.
IEFERENCES
ipec Number Tille
16-09-0003
Purchasing Procedure
11-xx-xxxx

Material Procurement Specifications

19-01-0004

Approved Vendor List

Type B: Indirect material consists of all material other than
direct that is directly used in the manufacture of a
product.
Type C: Indirect material consists of all material not directly
used in the manufacture of a product.
Type D: Engineering evaluations consist of material
specifically purchased for evaluations purposes
and which Engineering will inspect. Type Dmaterial
is not used as direct material, and will not be stored
in an area where Type A material is stored. Type D
material can be upgraded to Type A by having the
requester complete a "Request to Enter a Part into
Stores" and by having QA perform an incoming
inspection on the material.
The purchase order is reviewed and approved by the
management of the originating department. Additionally,
Quality Assurance reviews and approves Purchase Orders
for Type A and B material.
REFERENCES
Spec Number Title
06-09-0003

Purchasing Procedure

01-xx-xxxx

Material Procurement Specifications

16-01-0007

Incoming Inspection, Subcontracted Material

19-01-0008

Approved Subcontractor Listing

4.6.4 Verification of Purchased Products

16-01-0020

Distributor/Supplier/Subcontractor Survey and Audit
for Qualification and Disqualification Procedures

When specified in the contract, the purchaser or his/her
representative shall be afforded the right to verify at source
or upon receipt that the purchased product conforms to
specific requirements. Verification by the purchaser shall
not absolve the supplier/subcontractor of his/her
responsibility to provide acceptable products, nor shall it
preclude subsequent rejection.
When the purchaser or his/her representative elects to carry
out verification atthe subcontractor's plant, such verification
shall not be used by the supplier or subcontractor as
evidence of effective controls of quality by the supplier/
subcontractor.

16-06-0001

Statistical Process Control (SPC)

16-04-0002

Reliability Audit Program

16-05-7001

Failure Analysis Program

16-09-0008

Preferred Vendor Program

1.6.3 Purchasing Data
'he purchase order shall list the LTC stock number, the
lescription ofthe part, and designate the material as Type A,
I, C, or D if applicable. The purchase order shall also state
he drawing number or part number and the current revision
evel, the quantity needed, the applicable material
lrocurement spec. and revision (for Type A & B materials
mly), the required delivery date(s) and the negotiated price.
t shall also include inspection, test, and packaging
equirements, as applicable. All Type A and B parts and
naterials shall be purchased from original equipment
nanufacturers, approved vendors and subcontractors, and
,uthorized distributors. Below is a list of the categories:
'ype A: Direct material that has distinct value-added identity
on the finished product.

4.7 CONTROL OF CUSTOMER-SUPPLIED
PRODUCT
It is currently not LTC's practice to include purchasersupplied materials in products. Therefore, this clause of ISO
9001 does not apply. In the event that LTC should agree
contractually to accepVuse purchaser-supplied product,
LTC will document the procedures to verify, store, and
maintain such product. Verification by the supplier does not
absolve the customer of the responsibility to provide
acceptable product.

Jecification 06-09-0005, REV. E

L7lJ!J~

15-13

IIW
~

ISO 9001 QUALITY MANUAL
4.8 PRODUCT IDENTIFICATION AND
TRACEABILITY
Inventory identification and traceability shall be controlled
through the assignment of product numbers, run numbers,
lot numbers, serial numbers, date codes and back mark
codes as appropriate.
Run card and lottravelermust, asa minimum, specify the lot
number or run number, operation, device type or stock
number, quantity in/out or quantity inspected/rejected (for
inspection points). Runcards and lot travelers accompany
the material through the factory until it reaches Boxstock.
Offshore subcontracted material shall be identified by general
back mark codes.
The device back mark code is used to provide complete
traceability to test lot traveler, assembly lot traveler, wafer
fab traveler, and raw materials used. Where space allows,
the complete backside mark code is imprinted, as follows:
(For records, see Section 4.16.)
C/ANBBB/XXIYY, where:
C

AA
BBB

Denotes Plant of Origin: Country of Origin (COO)
Denotes Device Type
Denotes Assembly Lot Number

A) Documented work instructions and necessary equipment
and facilities shall be available and approved for all
processes that affect the quality of the product.
B) It is the responsibility of each organization that handles
product to monitor and control its processes.
C) Each organization has the responsibility for establishing
requirements for the approval of processes and
equipment.
D) Standards for workmanship shall be defined in each
area either in documents called "workmanship
standards" or "standard operating procedures," or by
physical examples of product that conforms to
requirement.
E) It is the responsibility of each department to assure its
equipment is suitably maintained.
F) Only certified personnel perform qualified processes.
G) For records, see Section 4.16.

REFERENCES
Spec Number Title
00-01-1008
SOP: Specification Format and Organization
06-02-XXXX

Quality Process Monitor Specs

06-0S-XXXX

Procedures, Quality Audit

06-09-XXXX

Procedures, QA Standard Operating

05-03-S0S2
OS-07-1001

Assembly Workmanship Standards
Operator Training and Certification Program

Spec Number Title

06-09-0002
06-03-7050

05-03-4601

OS-07-1003

Fab Maintenance P.M.

OS-07-0656

Special Facilities Safety Guidelines and Procedures

xx
yy

Denotes Year
Denotes Seal Week

REFERENCES
Country of Origin and Backside Mark

MIL -M-3S51 0 Slash Sheet Drawings
SMD

Standard Military Drawings

DESC Drawing SMD or Slash Sheet Drawings
MIL-STD-SS3 Compliant Data Sheets, LTC Data Book

4.9 PROCESS CONTROL
4.9.1 General
Processes which directly affect the quality of products or
services delivered by LTC shall be carried out under controlled
conditions. Controlled conditions include a production plan
as well as appropriate controls for material, production and
servicing equipment, processes and procedures, computer
software, personnel, associated supplies, facilities, and
environment.

Calibration Program Requirements
Record Keeping

4.9.2 Special Processes
Statistical Process Control (SPC) is implemented on all
critical processes throughout the manufacturing flow.
All products shipped by LTC are 100% tested and inspected
several times. All new products are fully characterized and
qualified before release. LTC's Reliability program is designed
to continually assess the performance of LTC devices in the
field.
All of the above controls work together to ensure that any
processing deficiencies become apparent before the product
is delivered to the end customer. Therefore, LTC does not
have any "special processes. "See specifications listed on
following page.

Specification 06·09·0005, REV. E

15-14

ISO 9001 QUALITY MANUAL
~EFERENCES

;pec Number Tille
lO-01-1006

SOP: Engineering Change Notice

l6-03-5001
l6-06-0001

Statistical Process Control (SPC)

l6-04-0002
l6-04-0011
l6-04-0012

SL (Special Lot) Specification Procedure
Reliability Audit Program
Reliability Monitor Program
QR2 (Quick Reaction Reliability) Program

l6-04-0001

Quality Assurance/Reliability Assurance Qualification
Requirements

(X-XX-XXXX

Applicable Standard Operating Procedures

()(-XX-XXXX

(Also, Specifications referenced in 4.10.2 apply to 4.9.)

1.10 INSPECTION AND TESTING
1.10.1 General

Lots which pass all the criteria specified shall be considered
acceptable. All logs, lot travelers, and boxes are stamped
with a box IQC accept-date stamp prior to releasing the
appropriate location.
If a lot fails any criteria, the lot is rejected and an inspection
failure report (IFR) is initiated, All reject samples must be
segregated and attached to the IFR. The responsible QA and
Manufacturing Engineer must review and disposition the
rejects and complete the IFR form.
The applicable Package and QA Engineers shall be responsible
for notifying the supplier of any rejections and for following
up on corrective action Discrepant Material Reports (DMR).

REFERENCES
Spec Number

Title

06-09-0003

Purchasing Procedure

final inspection and testing shall be performed in
Iccordance with referenced procedures to verify acceptance
:0 specified requirements.

06-01-0006

Incoming Inspection, General

I. 10.2 Receiving Inspection and Testing

~II

~eceiving/Production Control shall be responsible for
;egregating all incoming material until completion of IQC
nspection and for routing subcontracted assembly lots to
QC for inspection.

'-10.2.1
n accordance witH LTC's Quality Assurance procedures, all
rype Aand Type Bpurchased materials shall be subjected to
lA Incoming Inspection.
rype A: Direct materialthathas distinct value-added identity
on the finished product.
rype B: Indirect material consists of all material other than
direct that is directly used in the manufacture of a
product.

1.10.2.2
_ots may be released for further processing prior to
:ompletion of incoming inspection. However, IQC must be
:ompleted within 24 hours or 72 hours, depending upon the
ype of material that was released. If the sample fails, IQC
IOtifies Production Control who works together to recapture
he lot, provided that PC ensures that the affected lot(s) are
lot shipped prior to completion of IQC inspection.

06-01-0007

Incoming Inspection, Sub-Material

06-01-0011

Vendor Corrective Action

06-02-0020
01-xx-xxxx

Material Procurement Specifications

06-08-0013

Control of AgefTemperature Sensitive Materials

08-07-1001

Calibration Program Requirements

Inspection Failure Report (lFR) Procedure

4.10.3 In-Process Inspection and Testing
LTC shall:
A) Inspect, test and identify product as required by the
quality plan or documented procedures.
B) Establish productconformanceto specified requirements
by use of process monitoring and control methods. See
Section 4.20 for specifics.
C) Hold product until the required inspections and tests
have been completed or necessary reports have been
received and verified except when product is released
under positive recall procedures. See Section 4.10.1.
Release under positive recall procedures shall not
preclude the activities outlined in Section 4.10.2A.
D) Identify nonconforming products.
See specifications listed on following page.

peeification 06'()9'OOOS, REV. E

L7lJ!l~

15-15

ISO 9001 QUALITY MANUAL
REFERENCES (Representative)

REFERENCES

Inspection

Hold

Monitors

Test

Records

06-02-0001
06-02-0003
06-02-0005
06-02-0007
06-02-0009
06-02-0014
06-02-7002
06-02-7003
06-02-7004
06-02-7070
06-03-7028
06-03-7029
06-03-7030
06-03-7031
06-03-7035
06-03-7036
06-03-7038
06-03-7061
06-03-7062
06-03-7066
06-06-0001
06-08-0014
08-07-1001

06-02-0020

06-02-0002
06-02-0004
06-02-0008
06-02-0012
06-02-0017
06-02-0022
06-02-5001
06-02-7036
06-08-0002
06-08-0003
06-08-0004
06-08-0005
06-08-0015
06-09-0018
06-09-0019
06-09-9001
06-09-9003

06-02-0006
06-02-0011
06-02-0019
06-02-0031
06-03-0011
06-03-0012
06-03-7001
06-03-7003
06-03-7004
06-03-7006
06-03-7007
06-03-7008
06-03-7009
06-03-7011
06-03-7012
06-03-7016
06-03-7017
06-03-7018
06-03-7019
06-03-7025
06-03-7026
06-03-7027
06-03-7032
06-03-7033
06-03-7034
06-03-7063
06-03-7064
06-03-7065
06-03-7067
06-04-0001
06-08-0006

06-03-7050
06-03-7051
06-03-5000
06-03-5001
06-03-7068
09-01-0002
09-01-0004
09-01-0005
09-01-0008

4.10.4 Final Inspection and Testing
All products will undergo a final test according to the
applicable test procedure, and will be inspected for
completeness of specified requirements, appearance against
applicable workmanship standards, and all associated data
and documentation are available and authorized.
Electrical test and visuaVmechanical acceptance shall precede
transfer to the Finished Goods inventory area. Finished
Goods inventory consists only of products formally on the
released product listing (RPL). Additionally, it is impossible
to ship product that is not on the RPL, as the computer will
not print a shipper. Inspection of product prior to shipment
shall assure compliance to contractual requirements as
described by referenced procedures and applicable "SL" or
special flow requirements.
The government shall be allowed access to LTC and
subcontractor facilities to verify acceptability, when
contractually required.

Spec Number Tille
06-02-0014

Outgoing QA Electrical Test for 883, STANDARD MIL,
and Commercial Devices

06-02-0013

QA External Visual Inspection

06-02-7002

QA Post Pack Inspection

06-02-7003

QA Shipbench Inspection

04-04-XXXX

Final Test Set-Up Specifications

4.10.5 All Inspection and Test Records
Records that product has passed all required inspections
and tests as defined in the Quality plan must be maintained.
These include records from: Test, Visual/Mechanical, Postpack, Boxstock, Shipbench, SL, and Flows.
Specific procedures defining acceptance criteria for
inspection and test records may be found by referring to the
specifications listed below, or on the applicable lot
travelers. Records shall identify the inspection authority
responsible forthe release of product, and shall clearly show
the acceptance or failure of required inspections or tests
(reference Section 4.12).
Nonconforming material shall be identified, segregated, and
dispositioned in accordance with Section 4.13 and referenced
procedures. See Section 4.16 for specifics.
REFERENCES
Spec Number Tille
06-03-7050

Record Keeping

00-01-1006

SOP: Engineering Change Notice

4.10.6 Test Software Control
Test software shall be approved before use by Test
Engineering. Test software shall be stored for use in a
controlled access "server," from which only the most current
and approved software shall be used to test product.
Adocument-controlled Test Program Bookcontains released
(04-12-xxxx) test program listings, including the program
name and latest revision for each device type for Wafer Sort,
Final Test, and QA tests. Revisions used are recorded on the
test flow traveler, which also serves as a test specification.
Changes to test procedures can only be made after an ECN
has been approved and signed off. Majorchangesto software
(as defined in spec 06-04-0007) can only be made after an
ECN has been approved and signed off.

Specification OS-Q9.0005. REV. E

15-16

ISO 9001 QUALITY MANUAL
Whenever possible, equipment accuracy to parameter
tolerance shall be of at leasta 10:1 ratio. However, when 10:1
accuracy is not possible, electrical quality is guaranteed by
guard banding test limits against the published data sheet.
Guard bands are set by a combination of published test
equipment specifications and SPC techniques. This ensures
that parametric readings outside device specifications are
deleted, resulting in the faulty unit being rejected.
Additionally, afinal QAsampling plan guarantees acceptance
to quality limits inside of published data sheet parameters.

REFERENCES
Spec Number
00-01-1006
04-04-6300
04-01-xxxx
04-13-xxxx
04-21-xxxx
04-12-xxxx
04-14-xxxx
04-25-xxxx
06-04-0007
06-04-0009

Tille
SOP: Engineering Change Notice
Test Area SOP
Standard Product Test Flows
SL Product Test Flows
SMD and DESC Drawing Test Flows
Test Program List
SL Product Test Program Index
SMD and DESC Drawing Test Programs
Customer Notification of Maior Changes
Datasheet Change Control

4.11 CONTROL OF INSPECTION,
MEASURING, AND TEST EQUIPMENT
A) LTC measuring and test equipment shall be controlled,
calibrated, and maintained prior to release for use
during production, installation, or servicing to
demonstrate the conformance of product to the
specified requirements. Subcontractors and vendors
shall demonstrate conformance to the intent of MILSTD-45662.
8) Aunique identification must be provided forall equipment
and tools requiring calibration. This will be included on
the calibration recall list which includes the department
number, equipment type and due date.
C) The re-calibration frequency must be determined and
recorded. The calibration of inspection, measuring and
test equipment, including torque tools, shall be checked
before use or if the equipment is dropped (or otherwise
subjected to impact).
D) LTC uses outside calibration laboratories or services
provided by the original equipment manufacturer.
Priorto any contractual agreement, all outside calibration
labs used to calibrate any of LTC's test and measurement
equipment must be audited by QA to MIL-STD-45662

and 08-07-1001 "Calibration Program" requirements.
The outside calibration system and controls mustcomply
with MIL-STD-45662 requirements.
Outside calibration labs shall be responsible for
maintaining acomplete and accurate list of instruments
and equipment from LTC under the service agreement.
The list shall identify the instruments to be serviced by
means of coded symbols to identify the service performed
and recall period.
The outside lab shall furnish data sheets or certification
for each calibration performed.
E) Criteria are established for review of equipment to
determine if calibration is required. If any ofthe following
conditions is met, calibration will not be required.
1) Equipment performs a particular function, but it is
required that other calibrated equipment be used
with equipment at initial setup.
2) The performance of equipment is monitored through
the use of calibrated equipment.
3) Equipment is used for indication only.
4) Equipment where calibration has no meaning or
cannot be performed.
5) Equipment will be identified with a sticker stating,
"calibration not required."
F) New equipment calibrated directly by original
manufacturers shall be accepted ifthey meetthe following
requirements:
1) Calibrates equipment in accordance with established
written calibration procedures.
2) Records all out-of-spec conditions with before and
after values.
3) Supplies original calibration data and paperwork
which satisfy these requirements:
a) The appropriate inspection, measuring, and
test equipment are selected to provide the
required accuracy for all measurements to be
made. The equipment to be used and
measurements to be made shall be defined in
the detailed procedures or travelers.
b) Calibration and adjustment are performed as
required by the individual calibration procedure
and/or manufacturer's specifications. Primary,
secondary, and working standards are to be
traceable to the National Institute of Standards
and Technology (NIST) or to natural physical
constants.

Specification 06·09·0005. REV. E

15-17

ISO 9001 QUALITY MANUAL
G) Where test hardware ortest software is used, correlation
units are tested to ensure equipment has been set up
and running properly. Correlation units are run at the
frequency defined in the applicable procedures.
Correlation wafer/units are also used to verify the setups and test programs if the operators are experiencing
a large number of rejects.
In general, test hardware, software, and techniques are
considered proprietary to LTC. Such information is not
released except by non-disclosure agreement and by
authorization ofthe Chief Operating Officer. However, to
resolve correlation difficulties with customers, LTC can
provide serialized and data logged devices.
H) Procedures describing the verification of calibrated
equipment are listed below:
1) The accuracy, precision, and capability of inspection
and measurement equipment must be sufficient to
provide meaningful results. Equipment is selected
based on manufacturers' guaranteed operating
specifications and tolerances. During initial
inspection/test development, correlation studies are
conducted to verify desired results.
2) For critical inspections or where an SPC control
chart is to be used, a Measurement System
Evaluation (MSE) or Gauge Repeatability and
Reproducibility (Gauge R & R) is conducted to
ensure capability.
3) Every user is responsible for checking the calibration
status of a calibrated tool or piece of equipment
before it is used and is responsible to see that it is
not used if calibration is required before use. This is
done by verifying the data on the calibration sticker
and/or as defined in the applicable detailed
proeedure.
I) Records of recall notices shall also be maintained along
with calibration certificates of conformance (C of C) in
the applicable equipment history file.
A history file shall be kept by QA for each piece of
calibrated equipment. The file shall consist of calibration
data sheets, calibration certificate of conformance, and
out-of-tolerance evaluation forms (if applicable).
The test maintenance group shall be responsible for
maintaining the calibration data sheets on equipment
under their calibration program, with acopy going to QA
for the history file.
Records shall be kept a minimum period of 5 years (or
longer, if required by customer contract).

J) In the event that a piece of equipment is found to be out
of calibration, consideration is given to review all previous
work completed with the equipment since the previous
calibration.
Any out-of-calibration condition that is determined to
adversely affect product quality or reliability will require
rectification, customer notification and possible recall
of product.
K) Calibration procedures shall have the specified
temperature and humidity for specific environmental
conditions listed in the various equipment calibration
specifications. Areas where operations are sensitive to
surrounding environment shall be specified, monitored,
and controlled.
L) Upon receipt and before use, equipment is inspected for
damage and verification that appropriate calibration
stickers have been affixed to the equipment.
M) Production tOOling used as inspection media shall be
controlled and checked for accuracy at set intervals,
according to calibration procedures.
N) As deemed necessary to verify acceptability, government
and customer representatives shall be allowed access to
personnel and use of calibrated equipment.
0) Any advanced metrology requirement (exceeding the
known state-of-the-art technology) identified during
contract review shall be addressed by Test Engineering
and reported on the spec review form.
REFERENCES
Spec Number
Title
MIL-STO-45662 Calibration Systems Requirements
08-07-1001

Calibration Program Requirements

04-05-xxxx

Applicable Test Preventive Maintenance
(PM) Calibration Procedures

02-05-xxxx

Applicable Fabrication P.M. Calibration Procedures

08-07-1003

Fab Maintenance P.M. Specification

06-06-0001

Statistical Process Control (SPC)

06-08-0002

Controlled Environment Surveillance

08-07-xxxx

Applicable Facilities P.M. Procedures

4.12 INSPECTION AND TEST STATUS
Inspection stamps serve to identify the inspector who has
accepted or made an authorized disposition of material or
product. Trained and certified inspectors shall be issued
inspection stamps which areto be used to indicate completion
of acceptance testing.
Inspection stamp design is unique to LTC.
Specification 06-09-0005. REV. E

15-18

ISO 9001 QUALITY MANUAL
Each inspection area shall segregate inventory according to
inspection status and implement positive controls to
segregate accepted materials from rejected material.
Manufacturing lot travelers shall accompany all material.
The traveler shall show at least those manufacturing steps
from the last quality gate function and/or all manufacturing
operations which describe work operations being inspected.
Lot travelers shall indicate completion of manufacturing
operations by operator initials or number, date and quantity
out.
The identification of inspection and test status shall be
maintained (as defined in the procedures referenced herein);
throughout production of the product to ensure that only
product that has passed the required inspections and tests
is shipped.
Each gate inspection shall include verification that specified
manufacturing and inspection steps have been completed.
Only accepted material which passes QA Final Inspection is
allowed in the Boxstock area. All containers are identified
with a QA stamp on the label of the box. Only product which
is fully qualified and on the Released Products List (RPL) can
be shipped from Boxstock.

REFERENCES
Spec Number
06-02-0001
06-02-1000
06-06-0002
06-02-0020
06-02-7003
06-02-7002
06-02-0003
06-02-0007
06-02-0009
06-02-0014
09-01-0002

nonconformance shall be recorded and corrected before the
product is moved to the next step in the process, with
notification to the functions concerned.
All processes, work operations, quality records, service
reports, and customer complaints are analyzed to detect and
eliminate potential causes of nonconforming product.

4.13.2 Review and Disposition of
Nonconforming Material
Where anonconformance is detected in process, the product
shall be scrapped, reworked, or returned to the preceding
step for correction. MRB dispositions for raw materials are
as specified in #06-01-0006.
All rework shall be performed per approved procedures and
results shall be recorded on the appropriate rework traveler.
Reworked product shall be re-inspected/re-screened in
accordance with documented procedures.
LTC does not perform repair on any shippable product.
The responsibility for review and the authorityfordisposition
of nonconforming product and materials are described in
the following procedures:

REFERENCES
Spec Number

Title
Quality Assurance Inspection, Wafer Sort
Quality Control CheckpOints
QA Inspection Stamp Control
Inspection Failure Report
QA Boxstock Inspection
QA Post-Pack Inspection
QA 2nd Optical Inspection
QA 3rd Optical Inspection
Group-A Electrical Test
Outgoing QA Electrical Test for 883, STANDARD
MIL, and Commercial
Released Product Listing

4.13 CONTROL OF NONCONFORMING
PRODUCT
4.13.1 General
Nonconforming material shall be identified and segregated
to prevent unauthorized or accidental use. Where
nonconformance is detected during a verification step, the

06-02-0020
06-01-0006
06-01-xxxx
06-02-xxxx
06-03-xxxx
06-09-0018
06-09-0019
06-09-0022
02-04-1102
06-02-3000

Title
Inspection Failure Report
Incoming Inspection, General (~9.8-9.16)
Applicable Incoming Inspection Procedures
Applicable Inspections and Monitoring Procedures
Applicable Inspection and Test Operational
Procedures
SOP: Inventory Control
Engineering Alert: Minimum Yield Requirements
Nonconforming Material Control Procedure
Stop/Start Procedure
CMR

4.14 CORRECTIVE AND PREVENTIVE
ACTION
4.14.1 General
Prevention proceclures and corrective action procedures to
ensure thatthe product conforms to established specification
and quality standards are vital parts of LTC's continuous
quality improvement program.

Specification 06-09-0005. REV. E

15-19

ISO 9001 QUALITY MANUAL
A) The intent is to identify the root cause of a
nonconformance and for correction and prevention of
recurrence. This applies to all manufacturing and support
operations responsible for the manufacture of product,
and shall apply to (but not be limited to): Design,
Purchasing, Manufacturing, Testing, Final Packaging
for Shipment, Customer Material Returns and Failure
Analysis.
Emphasis shall be placed on identifying the root cause
and the prevention of recurrence ofthe nonconformance.
This may include containment, an interim corrective
action, a final corrective action, and subsequent audits
to ensure that the required corrective action measures
are in place and are effective in preventing recurrence of
nonconformances.
The response time goals are:
• Containment within 24 hours.
• Verification within 48 hours.
• Root cause and corrective action identification plan
within 10 days.
B) Discrepancies found during incoming inspection of raw
material lots are documented on a Discrepant Material
Report (DMR) by the QA group. Once a rejection is
determined by the MRB to be valid, the QA Group is
required to generate aVendor Corrective Action Request
(VCAR). Upon receipt of the completed VCAR from the
supplier, Quality Engineering shall determine if the
corrective action is sufficient to prevent a recurrence of
the problem. If a supplier does not provide effective
corrective action, the supplier may be disqualified.
Discrepancies found during in-process or outgoing
inspection are documented on an Inspection Failure
Report (IFR) by QA, or on a Stop/Start by Production if
the in-process inspection is performed by the production
group. The IFR or Stop/Start is reviewed by the
appropriate Engineering group to determine lot
disposition and appropriate corrective action. AlllFRs
are summarized in a monthly trend report by the QA
department. The report is issued to the responsible
Production and Engineering groups for review with
emphasis placed on eliminating recurring problems.
Other activities which may identify the need for initiating
corrective action are:
• calibration (out of tolerance)
• failures from a QA inspection step (IFR)
• results from reliability monitoring
• results from quality measurement analysis

•
•
•
•

corrective action reports
SPC chart OCAPs
findings from process audits and quality system audits
management reviews ofthe quality system and quality
trends
• customer feedback
• vendor ratings and audits
• failure analysis
C) When quality problems or undesirable trends occur, the
Quality Control Team (QCT) is responsible for initiating
a meeting or series of meetings to establish a Process
Action Team (PAT) to identify and define corrective
action measures. These meetings are held until the
problems are resolved orwhen quality levels are improved
to an acceptable level.
D) The responsibility for taking appropriate preventive and
corrective action is to be shared among Production,
Quality Assurance, Reliability, and Engineering groups.
Representation on the PATs should reflect this shared
responsibility of preventive/corrective action. All of the
above groups are responsible for ensuring that the
corrective actions are effective.
E) Any changes in procedures which resultfrom acorrective
action are documented through the Engineering Change
Notice (ECN) procedure and are recorded in the
Document Control department.
F) All customer failure analysis reports are distributed to
management, including the president and chief operating
officer.

REFERENCES
Spec Number
06-02-0020

Tille
Inspection Failure Report (IFR) Procedure

06-01-0011

Vendor Corrective Action

02-04-1102

Stop/Start Procedure

06-02-3000

Customer Material Return Processing
Procedure

06-05-7001

Failure Analysis Program

06-06-0001

Statistical Process Control

06-08-0014

Quality Audit Procedure

06-01-0006/06-09-0003 Material Review Board (MRB) Procedures
06-06-0003

Team Problem-Solving

06-09-0020

Corrective and Preventive Action Program

Spec.ication 06'()9'()005. REV. E

15-20

ISO 9001 QUALITY MANUAL
4.14.2 Corrective Action

4.15.2 Handling

The procedures for corrective action shall include:

All production parts, supplies, and components shall be
handled in amannerthatwill prevent damage ordeterioration.
Handling requirements are further defined in the following:

A) the effective handling of customer complaints and reports
of product nonconformities;
B) investigation of the cause of nonconformities relating to
product, process, and quality system, and recording the
results of the investigation (see 4.16);
C) determination of the corrective action needed to
eliminate the cause of nonconformities;
D) application of controls to ensure that corrective action is
taken and that it is effective.

4.14.3 Preventive Action
The procedures for preventive action shall include:
A) the use of appropriate sources of information such as
processes and work operations which affect product
quality, audit results, quality records, service reports,
and customer complaints to detect, analyze, and eliminate
potential causes of nonconformities;
B) determination of the steps needed to deal with any
problems requiring preventive action;
C) initiation of preventive action and application of controls
to ensure that it is effective;
D) confirmation that relevant information on actions taken
is submitted for management review (see 4.1.3).

4.15 HANDLING, STORAGE, PACKAGING,
AND DELIVERY
4.15.1 General
Documented procedures define the system for the
preservation, segregation, and handling of all items and
Jovernment-owned property throughout the entire
llanufacturing and inspection flow through storage
md snipping. Precautions shall be taken to protect
llaterial from abuse, misuse, damage, deterioration, and
Jnauthorized use.

REFERENCES
Spec Number

Tille

06-09-0015

SOP to Prevent Product Mixing

06-09-9001
06-08-0005

Electrostatic Discharge Control Requirements
Environment Requirements for Processing and
Storage

06-09-0018

SOP: Inventory Control

04-04-6300

Test Area SOP

05-03-7903
06-01-0006

Mark and Pack SOP
Incoming Inspection, General

06-01-0007

Incoming Inspection, Subcontracted Material

06-09-0001

Quality Assurance Policy

4.15.3 Storage
All materials processed shall be stored in a manner that will
minimizethe possibility of incurring damage or deterioration.
During the scheduled quality system audit, samples of stock
shall be checked for damage and deterioration of packaging.
Access to the Stores, Boxstock, and Dispatch areas shall be
limited to authorized personnel.
The condition of product in stock shall be assessed at
appropriate intervals for the detection of deterioration.
Procedures for receipt, dispatch, and storage of material are
referenced in the following specifications:

REFERENCES
Spec Number

Title

06-07-0001

Dispatch Procedure

06-07-0002
06-08-0005

Boxstock Procedure
Environment Requirements for Processing and
Storage

06-09-0004

SOP: Stores

06-09-0018

SOP: Inventory Control

06-09-9001
09-07-0003

Special Flows

Electrostatic Discharge Control Requirement

06-04-0011

Reliability Monitor Program (Boxstock Audit)

06-08-0013

Control of AgefTemperature Sensitive Materials

:pecification 06-09-0005, REV. E

15-21

ISO 9001 QUALITY MANUAL
4.15.4 Packaging
All materials shall be packaged in amannerthatwill minimize
the possibility of incurring damage or deterioration during
storage and handling. Procedures defining further
requirements for packaging may be found by referencing
procedures in the following specs:

REFERENCES
Spec Number
05-03-2000
05-03-2003
05-03-4601
05-03-4604
05-03-7899
05-03-7900

Tille
Wafer Pack

05-03-7901

Die Pack

05-03-7903

Mark and Pack SOP

Break and Plate
Back/Side Mark
Mark and Pack Incoming Procedure
Pack Partial Finish Product Singapore
Pack

06-01-0026

Incoming Inspection Age Sensitive Material

06-01-0010

Incoming Inspection Anti-Static/Conductive
Packaging Material

06-02-7002

QA Post-Pack Inspection

06-07-0002

Boxstock Procedure

06-08-0013

Control of AgefTemperature Sensitive Materials

06-09-9001
09-01-0005

Electrostatic Discharge Control Requirements
Top Mark Layout Listing (TML)

09-07-0003

Special Flows

4.15.5 Preservation
(Does not apply)

4.15.6 Delivery
Unless specified in the contract, the Customer Service
department is responsible for the selection of carriers and
the arrangement of shipments. The final boxing and shipping
of finished products is the responsibility of the shipping
departmentto ensure protection of product quality after final
inspection and during transit to its final destination.

Specific procedures defining the details ofthese processes
are listed below:

REFERENCES
Spec Number
06-07-0002
06-02-7003
06-09-9001

Tille
Boxstock Procedure
QA Shipbench Inspection
Electrostatic Discharge Control Requirements

4.16 CONTROL OF QUALITY RECORDS
Quality records shall be retained in such a manner as to be
retrievable. These records document conformance to
specifications and the effective operation of the quality
system.
All records used to substantiate controls for military/
aerospace, high reliability, MIL-M-38510 and MIL-STD-883
product shall be retained for a minimum of five (5) years.
For commercial products not covered by customer purchase
order record retention requirements, records of
manufacturing, quality assurance, and support groups are
retained for a period shown below.
All quality records shall be legible and traceable to the
product involved. Quality records shall be stored and
maintained so that they are readily retrievable in facilities
that provide asuitable environmentto minimize deterioration,
damage, or loss.
Where contractually agreed upon, quality records shall be
made available for evaluation by the customer or the
customer's representative for an agreed period.
The following procedures contain additional requirements
regarding record keeping:

REFERENCES
Spec Number
06-03-7050
06-03-7051

Tille
Record Keeping
Electronic Archiving Operating Procedure

Specification OS-09·0OO5. REV. E

15-22

ISO 9001 QUALITY MANUAL
1.16.1 Quality Records Matrix
rhe following table (Quality Records Matrix) identifies the types of quality record, where the record is kept, the method of
;torage, the position or function responsible and the minimum retention period.
luality Records Matrix
luality Record

Location

Method

Responsible

Period

luality System Review Report

QA

File

QA

Min. 3 Years

lesign Verification

Engineering

File

P.E.lD. Engr.

Life of Prod uct

;ontract Review

Cust. Spec. Review

File

QA

5 Years

nspection Records

QA/lQC

Elect. File

QA/lQC

Min. 5 Years

:ailure Analysis Reports

QAlRel.

Elect. File/Data Base

QAlRel.

Min. 5 Years

nitial Documentation/Subsequent Changes
n Design Material or Processing,
lualification Test and Change Records

QAlHi ReI.

Elect. File/Data Base

QAlHi ReI.

Min. 5 Years

,pecification (Documents, Applicable Forms)

Doc. Control

File/Data Base

Doc. Control

Life of Document

;alibration

QAlTest Maint.

File/Data Base

QAlTest Maint.

Life of Equipment

n-Process Monitor Inspection Logs
;ontrol Charts Stop/Start Sheets/IFRs

QA/lQC

Elect. File

QAlIQC

Min. 5 Years

III JAN 38510, 883, Customer Rei, Wafer Fab Assembly,
,creening Qualification, Quality Inspection Records
including all printouts, read/record data)

Hi Rei/JAN Prog/QA

Elect. File

Hi Rei/Jan Prog/QA

Min. 5 Years

III Commercial Fab Travellers, Wafer Sort Summaries,
:inal Electrical Screening, QA Inspection Records, and
~ark and Pack Travellers

QAlManufacturing

Manufacturing/
VAX File/QA
Elect. File

Wafer Fab,
Test, Mark & Pack

Min. 3 Years

III Commercial Assembly, Qualification and
luality Inspection Records, (including all printouts,
ead/record data)

QA

Elect. File/File

QA

Min. 1 Year

III Procurement Documents
III QA Inspection Stamp Control Records

Purchasing

File/Data Base

Purchasing

Min. 5 Years

Doc. Control

File

Doc. Control

Min. 5 Years

luality Audit Reports (QARs), Audit Logs (two years),
'endor/Sub-Contractor Audits, Customer Audits, Quality
leficiency Records (QDRs) generated by DESC
Ir DCMC, Distributor Audit Reports

QA Audit

File

QA Audit

Min. 5 Years

lperator Training/
:ertification

Personnel/
Applicable Trainer

File
Elect. File

Personnel
Applicable Trainer

Active File, 1 Yr.
Active File, 1 Yr.

:ontrol Charts (SPC)

Applicable Area

File

Area Supervisor

Min. 3 Years

nil -SPEC Library
JOE Results, Problem Analysis and
'referred Vendor Records

QA

File

QA

Life of Document

SPC Dept.

File

QA

Min. 5 Years

peeification 06·09·0005, REV. E

L7lJ!J~

15-23

ISO 9001 QUALITY MANUAL
4.17 INTERNAL QUALITY AUDITS
Internal audits of the quality system shall be conducted
according to aschedule established by the Corporate Quality
Audit department. The schedule shall ensure that all areas
operating under the quality system described in this quality
manual are audited at least once per year.
The results of these audits shall be documented and
communicated tothe managementofthe area being audited.
Management will ensure that corrective actions are taken to
resolve audit findings. (See Section 4.16).
Quality system audit results shall be reviewed to determine
the adequacy of, and compliance to, the documented quality
system.
The corporate auditor will follow-up until corrective action is
implemented. (See Section 4.16).
The results of internal quality audits shall be part of the input
to management review activities. (See Section 4.1.3).
The audit process is detailed in the following procedures:

REFERENCES
Spec Number
06-08-0014

Title
Quality Audit

Personnel performing specific assigned tasks shall be
qualified on the basis of appropriate education, training and/
or experience, as required.
Training records shall be maintained by each functional
supervisor, and a copy is to be sent to Human Resources.
Records shall indicate: Employee Name, Date of Hire, Badge
Number, Department Number, Supervisor, Spec Trained to
(Title of Spec and Number), number of training hours,
Initials of Trainer, Operator's Initials, Date Certified. (See
Section 4.16).
It shall be the responsibility of the quality systems audit
department to monitor the training and certification records
to ensure compliance with the documented requirements.

REFERENCES
Spec Number

Tille

06-09-0002

Operator Training and Certification Program

05-06-0007

EOL Operator Training and Certification Program

06-09-0007
06-09-9001

ESD Control Procedure

06-08-0005
08-07-0028

LTC Safety Policy (Required By 06-09-0002)
Environmental Requirements for Processing and
Storage
Wafer Fab Smock Procedure

06-08-0015
06-01-0020

MIL-M-38510 Quality Audit Checklist
Distributor/Supplier/Sub-Contractor/ Vendor
Survey/Audit Qualification/Disqualification
Procedure

06-03-7050

Record Keeping Procedure

xx-xx-xxxx

Applicable Specifications / Training Specifications
per Work Area

09-01-0008

Approved Subcontractor Listing

4.19 SERVICING (FAILURE ANALYSIS)

09-01-0004

Approved Vendor Listing

06-03-7050

Record Keeping

06-03-7051

Electronic Archiving Operating Procedure

Failure analysis of devices returned from customers is the
only service which is provided by LTC.
Failure analysis is the joint responsibility of the Reliability
group, Product Engineering, and DeSign Engineering. Outside
analytical labs are utilized in special areas which require
capabilities beyond the scope of the in-house equipment.
Procedures for identification, handling, and analysis of
reject or defective devices shall be documented. This
information will be conveyed to the customer and government
representative via a formal Failure Analysis Report in
accordance with established industry standards including,
but not limited to, MIL-M-3851 0, MIL-I-38535 Appendix A,
and MIL-Q-9858.
A summary report of failure analysis activity findings shall
be prepared and submitted to management on a quarterly
basis, or more frequently, if necessary.

4.18 TRAINING
Each department shall establish training requirements for all
jobs that effect the quality of product shipped to customers.
Individual departments shall maintain records to indicate
that a person has satisfactorily completed the appropriate
training for his/her assigned job.
It is the responsibility of each functional manager to insure
that his/her personnel receive proper training. All employees
are to be trained and motivated to provide excellence in
workmanship throughout the manufacturing process and to
provide the service to our customers which is the standard
by which other companies are judged.

Specification 06-09'{)005, REV. E

15-24

ISO 9001 QUALITY MANUAL
REFERENCES
Spec Number

Title

06-05-7001

Failure Analysis Program

MIL-I-38535

General Spec for Microcircuits

MIL -Q-9858

Quality Program Requirement

4.20 STATISTICAL TECHNIQUES
4.20.1 Identification of Need
A Statistical Process Control (SPC) program is in place to
improve process capability, reduce process variations,
provide continuous improvement, and provide robust designs
along with the statistical sampling plans used as an integral
part of inspection and testing.
The SPC program is applicable to all manufacturing
processes, to operations which use statistical sampling for
control or acceptance purposes, and to designs that are
deemed critical.
Statistical techniques are employed by LTCto analyze process
data and to identify the root causes of process variation so
that the process can be modified to achieve:
A) Continuous reduction of variability around the desired
target;
B) Consistency over time;
C) Conformance to requirements.
The SPC program comprises the following key elements:
A) An SPC structure: Steering Committee (Corporate level),
Quality Control Teams (area SPC facilitators/
management), and Process Action Teams (PATs).
B) Employeetraining: Basic SPC, Advanced SPC, Design of
Experiments, and Team Organization.
C) Establishment and documentation of Critical Nodes in
manufacturing/related processes via flow charts and
Control Plan Detail tables.
D) LTC's Self-Audit program of the SPC program.
E) Application of SPC to manufacturing, inspection,
calibration, maintenance, preventive maintenance,
environmental control, document control, purchasing
materials, service data, and other areas as the need
arises.
F) Formation of SPC Process Action Teams (PATs)
composed of representation from manufacturing,
engineering, maintenance, (and as applicable, quality
engineering) with the objective of applying SPC to solve
problems, improve process capabilities and reduce
process variation.

G) Reports shall be established to measure progress made
in terms of improved process capabilities (Cp & Cpk
indexes) and quality improvements.
H) Statistical Sampling procedures are employed forthose
operations not requiring 100% inspection or which are
destructive in nature.
I) Goal setting for continuous quality improvement.
Specific statistical methods and applications available include,
but are not limited to, the following:
A) Design of Experiments/factorial analysis
B) Analysis of variance/factorial analysis
C) Safety evaluation/risk analysis
D) Tests of significance
E) Quality control charts/Cum-Sum techniques
F) Statistical sampling inspection

4.20.2 Procedures
Documented procedures shall be implemented and
maintained for controlling the application of the identified
statistical techniques.
REFERENCES
Spec Number
MIL-STD-105

Tille
Sampling Procedures and Tables for Inspection by
Attributes

06-06-0001

Statistical Process Control (SPC) Procedure

06-06-0003

Team Problem Solving

4.21 QUALITY COST
Quality cost data, the cost of scrap, rework, and prevention
of defective material are of primary concern at LTC.
Quality cost data shall be collected, analyzed, and used to
improve effectiveness, efficiency, and control waste. This
data is in the form of yield reports and scrap reports, which
are compared to their respective specified goals.
The overall operating expenses of the Quality Assurance
Department are forecast and budgeted on an annual basis.
The cost of department operation is broken down into
specific categories. Each category is reviewed on a monthly
basis to assess actual cost versus planned cost.
All yield, scrap, and cost data are considered LTC Confidential,
and may only be reviewed with customers upon the express,
written permission of LTC's Chief Operating Officer.

,pecification 06-09-0005. REV. E

15-25

ISO 9001 QUALITY MANUAL
APPENDIX A-RELIABILITY
ASSURANCE
• The Reliability Assurance group shall be made up of
professional individuals with training and experience in
environmental stress testing, failure analysis techniques,
reliability calculations, and reliability predictions of
integrated circuits.
• The activities of the Reliability Assurance group shall
focus on measurements of product reliability, as well as
the identification and timely elimination of design and
processing deficiencies which limit or otherwise
compromise product reliability.
• Reliability Assurance shall exercise full authority overthe
qualification of all products, processes, materials, and
manufacturing locations.
• The Reliability Assurance group shall prepare and
implement written program plans and detailed procedures
covering, as a minimum, these areas:
Wafer Fabrication Reliability Monitor Program
Quick Reaction Reliability Audit Program
Long-Term Reliability Audit Program
New Product/Process/Material Qualification Program
Major Change Qualification
Assembly Subcontractor Qualification
Failure Analysis and Corrective Action Program
• Achieving extremely low failure rates during product life
in the field demands that the integrated circuit
manufacturer audit reliability performance of outgoing
products.
• Product reliability audits are the responsibility of the
Reliability group, with immediate responsibility for
program implementation, performance, and reporting
assigned to the Manager of Quality and Reliability
Assurance.
• A summary data file shall be maintained on all product
families. This summary shall include, as a minimum, the
device type tested, the package type, the assembly
location, the manufacturing date code, the actual test
condition used, the sample size, the duration of the test,
and the number of failures observed.
• Management shall be apprised immediate/yof any audit
results which indicate thatfailure rate goals are not being
met or that significant degradation in performance is
evident.

PRODUCT QUALIFICATION PROGRAM
• New products will not be released without acceptable
reliability data as defined by Reliability and Quality
Assurance and the responsible engineering groups.
• Before any major design or process change is considered
qualified, sufficient test data shall be collected to
demonstrate that the processes used conform to
applicable government, industry, customer, and internal
specifications. The finished devices must be capable of
passing all tests as required by applicable government,
industry, customer and LTC specifications.
• A major change is defined as a significant departure
from the existing approved process/design, as agreed by
Reliability Assurance and Manufacturing, or DeSign and
documented in LTC's 06-04-0001 and 06-04-0006
Qualification Specifications.
• Similarity in materials and design to previously qualified
products shall be considered sufficient for purposes of
new product or process change qualification. Similarity
data may be supplemented with test data on the product
in question in those areas where similarity does not
justify blanket qualification of the product or change
approval.
• Life test data on one device within a product family can
be used to generically qualify other devices within the
same product family, providing the devices are
encapsulated in packages made from the same materials
and sealed using the same sealing process. For purposes
of qualification, aproduct family includes all microcircuit
chips of equivalent complexity or function made in the
same wafer fab area using the same process.
• Qualification requirements shall be established and
documented for all products and processes.
Documentation shall include the tests, test conditions,
and pass/fail criteria which must be met before the
product or process is considered fully qualified.
• Qualification tests shall include environmental tests and
mechanical tests as specified in the LTC 06-04-0001
spec, but shall not necessarily be limited to these tests
where device service conditions are known to be more
severe than the test conditions in the standard
qualification.
• Qualification requirements on MIL-STD-883, SMD
(standard military device), and MIL-M-38510 devices
shall be per Method 5005 of MI L-STD-883, asa minimum.

Specification 06'09-0005, REV, E

15-26

ISO 9001 QUALITY MANUAL
• Major changes on MIL-M-3851 0 devices shall be as
defined in MIL-M-3851 0 and qualification requirements
as specified in MIL-M-38510.
• Qualification test reports shall be retained for a minimum
period of five years.

~PPENDIX

REFERENCES
Spec Number
06-04-0001

Tille
Quality Assurance/Reliability Assurance
Qualification Requirements

06-04-0006
06-04-0011

Qualification of Changes on 38510 Products
Reliability Monitor Program

06-04-0012

QR2 (Quick Reaction Reliability) Program

B-MAJOR CHANGE NOTIFICATION

• The major change definitions and requirements per MILM-38510 for military products, LTC's major change
requirements for commercial products, and specific
customer change requirements shall befullydocumented
by the Quality Assurance group.

• The Quality Assurance and Reliability manager is
responsible for ensuring that a major change is not
implemented until customers who have major change
notification requirements are notified and have approved
the major change.

• The responsible Engineering group and/or Quality
Assurance group is responsible for initiating a major
change via an ECN processed through the Document
Control group. Appropriate qualification and test data
justifying the major change shall support the ECN.
• The Quality Assurance and Reliability manager is
responsible for maintaining a database of customers
who require major change notification.

• The Quality Assurance and Reliability manager is
responsible for sending the customer appropriate
qualification and test data justifying the major change
and for maintaining a record of all customer major
change notifications.

REFERENCES
Spec Number
06-04-0007

Tille
Customer Notification of Major Changes

06-04-0006

Qualification of Changes on 38510 Products

3Cification 06M09-0005, REV. E

L7lJ!J~

15-27

ISO 9001 QUALITY MANUAL
APPENDIX C-ENVIRONMENTAL CONTROL
• The Facilities and Maintenance departments are
responsible for control of following items to support the
manufacture of integrated circuits:
Temperature and humidity control
Controlled filtered air hoods
Airborne particle control
De-ionized (01) water
Gases
Clean dry air
• It shall be the responsibility of the Facilities Engineering
and Maintenance departments to establish and maintain
the necessary equipment and controls to provide the
services listed above.
• It shall be the responsibility of the Facilities Engineering
and Maintenance departments to define and document
the requirements for such facilities based on the
requirements of the various product groups.
• It shall be the responsibility of the Quality Assurance and
Systems Quality Audit departments to monitorthe quality
of these services listed above.

• The Quality and Reliability Assurance department shall
perform a periodic surveillance of the environmental
controls.
• Surveillance inspection records shall be maintained by
Quality Assurance and shall include as a minimum a
monthly report of hood/area temperature, humidity and
particle count, and DI water bacteria count and resistivity.
• Surveillance inspection records shall be maintained for a
minimum of five years, per MIL-M-3851 O.

REFERENCES
Spec Number
06-08-0002

Title
Controlled Environment Surveillance

06-08-0004

Deionized. Water Monitor

06-01-0016

Incoming Inspection: Gases

01-07-0001

MPS: Gases

06-01-0005
01-65-0001

Incoming Inspection: Chemicals
MPS: Chemicals

Specification 06-09-0005. REV. E

15-28

ISO 9001 QUALITY MANUAL
~PPENDIX

D-MILITARY STANDARD CROSS REFERENCE MATRIX

i-09-0005
lclion Number Quality System Element

'eface

Quality Policy

1.2
1
2
3
4

Organizational Chart

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
IpendixA
Ipendix B
Ipendix C

Management Responsibility
Quality System
Contract Review
DeSign Control
Document and Data Control
Purchasing

ISO 9001
1994

MIL-Q-9858

4.1.1
N/A
4.1.2
3.1
4.1.2.1-4.1.3
1.3
4.2
1.3
4.3
3.2
1.3
4.4
4.5
3.3,4.1
4.6
5.1,5.2,7.1

Control of Customer Supplied Product
Product Identification and Traceability

MIL-I-45208

MIL-I-38535
Appendix C

MIL-STD-45662

N/A

N/A

N/A

N/A

30.1.3.1
3.1
30.1
3.1
30.1,30.1.3
N/A
30.1.1.1
30.1.1.6
N/A
3.2.1,3.2.4 30.1.1.8,30.1.2.4
3.11.2,3.11.3
30.1.1.1
N/A
3.6
30.1.1.12,30.1.2
3.5
30.1.1.4,30.1.2.6
3.4
3.1,3.10-3.12 30.1.1.3,30.1.1.5,
30.1.1.6,30.1.1.12

N/A

4.1
4.1,5.1
N/A
N/A
5.5,5.8
5.11
N/A
5.2,5.10

4.7
4.8
4.9
4.10

7.2
6.1
6.2
6.1-6.3,7.1

Control of Inspection, Measuring,
and Test Equipment

4.11

4.2-4.5

3.3

30.1.1.9,30.1.2.5

5.2,5.4

Inspection and Test Status

4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
N/A
N/A
N/A
N/A

6.7
6.5
3.5
6.4
3.4
N/A
N/A
3.5
6.6
3.6
N/A
N/A
6.2

3.5
3.7
3.2.3
N/A
3.2.2
N/A
N/A
N/A
3.9
N/A
N/A
3.1
N/A

30.1.2.2
30.1.1.10
30.1.1.11
30.1.1.14
30.1.2,30.1.2.2
40.3.1
30.1.1.2,30.1.2.1
30.1.1.10,30.1.2.3
30.1.1.3
N/A
N/A
30.1.2.4
30.1.1.7

5.10
5.6
5.6,5.7
5.12
5.9
5.7
N/A
N/A
N/A
N/A

Process Control
Inspection and Testing

Control of Nonconforming Product
Corrective and Preventive Action
Handling, Storage, Packaging, and Delivery
Control of Quality Records
Internal Quality Audits
Training
Servicing (Failure Analysis)
Statistical Techniques
Quality Cost
Reliability Assurance
Major Change Notification
Environmental Control

N/A
N/A

5.4
5.6
5.3

cificalion 06·09·0005, REV. E

15-29

f-yrLln'(,I\Q
~, TECHNOLOG~fY~-

RELIABILITY ASSURANCI
_ _ _P_RO_G_RA_~

INTRODUCTION
In 1981 Linear Technology Corporation was founded
with the intention of becoming a world leader in
high performance analog semiconductors. To achieve
this goal Linear Technology Corporation committed itself
to consistently meet its customers' needs in four areas:

o Functional Value
o Quality

o Reliability
o Service

Linear Technology Corporation has achieved its primar
goal and is now focused to achieve 100% custome
satisfaction.
This brochure defines the key elements of LinearTechnolog
Corporation's Reliability Assurance Program which is divide
into three groups:

o Reliability Planning
o Manufacturing for Reliability
o Reliability Assessment and Improvement

The Focus and Commitment
of
Linear Technology
Corporation

15-30

RELIABILITY ASSURANCE PROGRAM

IELIABILITY PLANNING
eliability planning takes three forms at Linear Technology
Jrporation (LTC). The first is the establishment of the
liability requirements for a product to be released to
anufacturing. The second is the definition and
lplementation of apredictive reliability system. Thethird is
lsigning for reliability, which includes new product
lVelopment, materials selection, and construction
chniques.

selected to optimize device performance and also to fit easily
into a variety of packages without creating potential bond
loop problems that could result in shorted wires.
The Predictive Reliability System

'e fully realize that the cost of failure in the field is many
'ders of magnitude more than the initial component cost.
lerefore, the goal of the reliability planning process is to
'ovide reliable product to reduce the cost of ownership to
Jr customers.

eliability Criteria
key element of reliability planning is LTC's internal
lecification entitled "Quality Assurance/Reliability
;surance Qualification Requirement." It contains acomplete
lscription of the interrelationships of the various groups
volved in meeting LTC's reliability objectives and defines
e guidelines for release decisions which affect quality and
liability of the device.

redictive Reliability System
IC has developed a predictive reliability system which
)mbines quality and reliability information in a database to
ovide reliability summaries and trend analysis. A block
agram of the system is shown on this page.

esigning for Reliability
msiderable planning goes into the design of LTC's products.
lis planning includes device layout considerations, selection
input and output protection schemes, selection of fab
ocessing technology, and specification of materials and
anufacturing techniques.
stringent set of bipolar and CMOS design rules have been
,tablished to enhance reliability and optimize
anufacturability through robust design. At the design
age the reliability of the circuit is heavily dependent
I layout considerations. The rules for thickness and width
metallization have been defined to minimize the current
insity and prevent electromigration. Current density
Iculations are required to be performed on all products to
Isure that the designs are conservative. The routing of the
etal pattern is designed to eliminate potential inversion or
lkage failures and guard ring structures are used where
'propriate. The positions of bonding pads are carefully

The thermal layout of our circuits also receives considerable
attention to minimize parametric drift and optimize
performance. In the case of voltage regulators, for any given
power dissipation, there will be some temperature difference
between the power transistor and the control circuitry due to
their separation on the die. This temperature difference is a
desirable situation which is used to reduce the power
transistor's temperature effect on the control circuitry.
Additionally, the power transistor has a higher maximum

15-31

RELIABILITY ASSURANCE PROGRAM
junction temperature rating than that of the control circuitry
and may be allowed to run warmer without degradation.
Such LTC products are also designed for maximum efficiency
to reduce power dissipation and thereby improve reliability
and reduce the cost of heat sinking in the customer's
product.
All of our voltage regulators include thermal limiting in the
circuitry to shut down the device if the temperature exceeds
the safe operating conditions. Additional insurance is provided
by employing short-circuit current protection to safeguard
against catastrophic failure. The philosophy of incorporating
fault-tolerant designs with innovative circuit protection
concepts is a fundamental design rule at LTC.
Thermal Resistance Model of LTC's Voltage Regulators
CONTROL CIRCUITRY

POWER TRANSISTOR

R9JC

R9JC

(Control CircuHry)

(PowerQ)

Linear circuits with total supply currents in the microam
range cannot tolerate leakages induced by contaminatior
Whether the circuit is bipolar, CMOS or complementar
bipolar, the circuit must withstand high operating voltag
and high temperature for thousands of hours without leakag
currents degrading device performance. LTC uses advance
process techniques to shield the die from sodiur
contamination while preventing electron accumulatio
causing surface inversions. This, combined with continuou
monitoring of the assembly process, ensures high reliabilit
devices.
LTC utilizes state-of-the-art processes in manufacturing it
products. Our high voltage bipolar process provides hig
gain, low noise general purpose devices as well as hig
power integrated circuits. CMOS can provide high complexit
ICs with a large digital content. Complementary bipolar,
new process developed in-house by LTC, provides hig
speed NPNs and PNPs on the same monolithic die
Complementary bipolar enables an expanded product rang
forlinearcircuits and is suitableforvery high speed amplifier!
general purpose linear signal processing or even high spee l
D/A converters. All of these products are characterized b
high reliability, low power consumption and the ability tl
operate from awide range of power supplies and over awid
range of ambient temperatures.
LTC's Process Structures

Another major design consideration in circuit reliability is
tolerance to electrostatic discharge (ESD) and electrical
overstress (EOS). ESD is a problem encountered both in
normal handling and circuit assembly. It also affects the
reliability of the final product when cables are exposed to
ESD such as in line drivers and receivers.
The implementation of ESD protection structures in linear
integrated circuits is much more difficult than in digital
circuits. The linear circuit must provide protection for electrical
overstress while maintaining the ability to measure current
levels in the picoamp range. Interface circuits have input and
output connections that normally operate at voltages in
excess of the power supply, thereby precluding the use of
clamp structures to the power supply for ESD protection.
LTC, using a combination of circuit design and proprietary
structures, provides high levels of overstress immunity to its
devices which enhances their reliability. As agoal, all devices
are designed for a minimum of 2,OOOV ESD protection with
some devices achieving 5,OOOV to 1O,OOOV ESD protection.

15-32

5

3

7
1. N-Well CMOS/BiCMOS
2. Poly J-FET
3. High Speed Bipolar
4. Complementary Bipolar
5. Super Beta Structure
6. BiFET Structure
7. Silicon Gate CMOS Structure

RELIABILITY ASSURANCE PROGRAM
In order to ensure that device performance and reliability
goals are achieved on new products, design review meetings
are held regularly during the design and development phase.

Material Selection
LTC has selected assembly processes and materials that are
closely matched to achieve the highest reliability level in both
ultra-precision and high power devices. Compatibility
between the different package elements, such as the molding
compound and lead frame, are carefully researched and
qualified. The choice of materials and assembly processes is
especially critical in surface mount devices, which must
maintain reliability after being subjected to harsh board
soldering environments. At LTC we are using the latest stateof-the-art assembly equipment and materials to guarantee
reliability. Our low stress epoxy molding compound is
extremely low in ionic impurities.
Similar improvements have been made in hermetic packages
in the modern low temperature glass ceramic seals and
improved die attach materials.
LTC's Dual Layer Passivation System

To protect the die from degradation before assembly, and
from the long term effects of the package environment, LTC
has developed aproprietary dual layer passivation. This dual
layer passivation system is free from cracks and pinhole
defects and offers an outstanding moisture barrier without
detrimental side effects to device performance.

Design of Experiments
LTC is committed to the use of design of experiments (DOE)
when developing new products and processes. We firmly
believe that design of experiments will be the new industry
standard for product and process development.
DOE has been successfully utilized on numerous products
and processes at LTC. DOE, coupled with response surface
methodology, has provided LTC the ability to solve complex
problems that were previously unsolvable. We have used
DOE to characterize wafer fab processes and provided this
information to our IC designers which enabled them to
produce devices that were less sensitive to manufacturing
variations.
Response Surface Model of
PIND Yield after Welding Operation

SILICON
1. Contamination Free Passivation Oxide
2. Conformal Oxide Underlayer

---.-I

3. Plasma Nitride Top Layer - - - - - - - '

15-33

RELIABILITY ASSURANCE PROGRAM

MANUFACTURING FOR RELIABILITY
LTC is keenly aware ofthe influence which the manufacturing
process has on the quality and reliability of the finished
product. For this reason, LTC has placed critical emphasis
onthe manufacturing facility and associated process controls.
LTC's claims of outstanding manufacturing capability and
controls are validated by the fact that we achieved Class S
Certification by DESC in November of 1987.

Microprocessor-controlled furnaces are used to eliminate
the effects of process variations and human errors. Thin film
processing employs fully automated sputtering and metal
etch systems.
Automated Metal Etch System

LTC's strategy in manufacturing for reliability includes the
use of automated state-of-the-art equipment, protection of
the product as it moves through manufacturing, effective
inspection and screening, device traceability and statistical
process control. These and other similar tight controls are
applied from wafer fabrication through product shipment.

Wafer Fab
In wafer fabrication, the key to a reliable process is process
control. Two major thrusts of process control in the wafer
fab are the application of statistical process control (SPC)
and the use of automated processing equipment. Automated
equipment employing cassette-to-cassette wafer transfer,
proximity mode aligners and projection steppers has
significantly reduced handling related defects.
Projection Stepper

All of these equipment enhancements work together to yield
a process that is consistent and repeatable with a minimum
of wafer handling. Quality control monitors and inspections
at various points in the process, coupled with the use of
control charting throughout the fab area, ensure consistent
processing. The quality of the oxide is checked regularly
using CV plots to check for contamination and surface state
anomalies. Scanning electron microscope inspection is
performed periodically each day to ensu re the integ rity ofthe
metallization system.

Assembly
The introduction of new equipment and techniques in
the assembly process has had a tremendous impact on
device reliability. The use of automated equipment has
reduced the handling and subsequent damage of die and
wafers. In situations where die or wafers must be handled,
vacuum wands and vacuum pens have replaced tweezers
and thereby decreased damage due to scratches. Automated
wire bonding machines have produced more consistent wire
bonding quality and improved productivity.
All products receive a thorough visual inspection per MiIStd-883 Method 2010 Condition B or an equivalent visual
criteria prior to encapsulation.

15-34

RELIABILITY ASSURANCE PROGRAM
High Speed Automatic Bonder

documents are stored, their 10 number, date and classification
are recorded in the system's database to facilitate retrieval.
This system allows fab travelers, test travelers and other
critical documents to be retrieved in minutes as opposed to
hours or days.
Optical Oisk Archive System

rraceability
_TC has an outstanding traceability control system. Abackside
nark or a side mark is used to code information including
he country of assembly, assembly facility, exact assembly
otseal date, waferfab lot, dietype and revision. Additionally,
his backside mark will identify any nonstandard processing
~hich may have been required using a custom flow. At the
Ifafer level, each wafer is laser-scribed to include the fab
un number and waferserial number. This traceability benefit
s offered as a standard feature on all packages where space
lliows and is part of the "added value" of LTC products.
Traceability Control Using Backside Mark
or Side Mark Coding

Reliability Screening
Although our standard product families are recognized
for their very low infant mortality, customer-requested
additional reliability screening can be provided by LTC. This
added reliability screening for commercial or industrial level
products is offered for both hermetic and plastic devices
and is designated as our "R" flow process signified by a
IR symbol as a suffix to the part number.
The "R" flow includes temperature cycle, burn-in and QA
testing at DoC, 25°C, and 70°C. A simplified flow chart of
the "R" flow is shown in Table 1 at the end of the Reliability
Assurance Program section. The hermetic devices are also
offered as JAN Class S or Class B, Standardized Military
Drawings (SMDs) and also as MIL-STD-883 devices.
LTe offers a cost-effective reliability screen for hermetic
product using the MIL-STD-883 screening and quality
conformance inspection. This flow is defined in our "MILSTD-883" brochure and depicted in a brief flow diagram
shown in Table 2.

·0 enhance traceability LTC is using the latest state-of-thert document archival system. This computerized system
ncorporates a document scanner which digitizes and
om presses documents to be stored on optical disks. As the

L7lJD~

The MIL-STD-883 burn-in at 125°C for 160 hours is roughly
equivalent to 80,000 hours or approximately 9 years of
continuous operation at a normal operating temperature of
around 55°C (assuming an activation energy of 1.0 electron
volts).

15-35

RELIABILITY ASSURANCE PROGRAM
Whether testing plastic or hermetic devices, the engineers at
LTC routinely add tests in addition to the standard data sheet
tests. These added tests are used to detect potential flaws
that could impact reliability and provide additional device
compatibility with subtle application-related performance
characteristics. Examples of such additional tests are the
exercising of thermal shutdown mode of regulators prior to
burn-in or the stressing of on-chip capacitors with voltages
in excess of the device maximum rating to induce failure in
substandard lots.
Data sheet electrical parameters are measured before and
after the specified stress testing to ensure the electrical
integrity of the devices.

Statistical Process Control
At LTC we believe that quality and reliability should be built
into a product as opposed to simply screening out bad
devices. Statistical process control (SPC) is ideally suited to
our manufacturing goals. SPC has enabled us to run
processes with uniform and centered distributions which
have not only optimized yields, but have also produced a
finished product that is rugged and reliable.

UCL
UWL
(!l

[[

w
>

AVG

LWL
LCL

UCL

RBAR

LCL

Control charting at all critical processes is used to identify
the need for corrective action before an out-of-control
situation occurs, thus reducing the overall process variation.
LTC has an active SPC program. The generic process from

15-36

• Steering Committee
• SPC Quality Control Teams (QCTs)
• Process/Preventive Action Teams (PATs)
The Steering Committee provides the leadership forthe SPC
process, while the QCTs are responsible for the
implementation and maintenance of SPC within their
respective operational groups. PATs are formed by the QCTs
to implement certain initial or corrective measures with
specific stated goals using SPC tools. There are four QCTs
in place:
•
•
•
•

Wafer Fab
Quality and Reliability
Local Assembly
End-of-Line (which includes Test, Mark, Pack,
Product and Test Engineering)

Since, by definition, a PAT functions until its stated goal is
attained, their number and tasks are constantly changing.
We have had as many as 23 active PATs which include
operators and maintenance personnel.

Example of Control Chart for SOIC Coplanarity

..fll
..

wafer fabrication through shipping has been flow-charted
with critical nodes defined. The Control Plan Detail outlines
the various attributes of the activities surrounding that
particular activity. Organization for SPC is comprised of the:

Training is provided in-house for a majority of LTC's
employees, who receive test materials and 135 to 279 hours
of instruction in one or more of the following courses:
•
•
•
•

Basic SPC
Advanced SPC
Design of Experiments
Team Organization

An important aspect of the SPC program at LTC involves the
use of Design of Experiments to solve specific problems,
develop new products/processes, and characterize new
products and/or processes.
LTC is driving SPC beyond our own factory. A Preferred
Supplier Program has been implemented with our raw
materials suppliers, wherein parameters deemed critical to
the manufacturing process at LTC are controlled statistically
by the raw material supplier. Evidence of this control is
supplied to LTC on aregular basis. This system of customersupplier cooperation ensures the integrity of the materials
and maintains a mutual focus on improvement.

RELIABILITY ASSURANCE PROGRAM

RELIABILITY ASSESSMENT
AND IMPROVEMENT
LTC combines a traditional approach to reliability which
incorporates product qualification and long term reliability
assessment with a "leading edge" approach, which
incorporates wafer level reliability testing and in-line assembly
reliability monitoring.

Qualification Testing
Before a new product can be released to production, strict
qualification testing requirements must be met. These same
qualification requirements apply to new processes, new
materials, new designs and major changes in any of these
areas. The guidelines for qualification of process or product
changes are detailed in MIL-M-3851 O. At LTC we adhere to
those guidelines and in many cases impose additional
testing per our own requirements. Examples of some of the
qualification tests which are used by LTC are shown in Table
3 at the end of the Reliability Assurance Program.
As part of new product qualification, LTC performs ESD
sensitivity classification testing of devices to Method 3015
of MIL-STD-883. This ESD sensitivity testing uses both the
human body model and the machine model. During this
rigorous testing, every pin combination on at least three
devices is subjected to three positive pulses followed by
three negative pulses at the specified voltage increment with
a one-second cool down period between pulses. Following
this ESD testing, the device is tested for opens or shorts
on a curve tracer and then must pass the full data sheet
limits on the automatic test equipment.
Additionally for CMOS circuits, latch-up testing is performed
on every pin to determine the device's ability to source or
sink current without destructive latch-up. We require new
LTC products to handle increasingly high currents without
latch-up and subsequently meet all data sheet parameters.

Wafer Level Reliability Assessment
As an additional reliability control, LTC has innovated a
strategy for auditing the wafer fab process. Diagnostic
structures, in addition to the device structures, are specifically
designed as either bipolar or CMOS reliability test patterns
and are stepped into all wafers. These structures are tested
during fabrication using a parametriC analyzer. Then these
test vehicles are used to investigate and detect potential yield
and reliability hazards after assembly.
The bipolar process version ofthis structure is optimized to
accelerate, under temperature and bias, the two most
common failure mechanisms in linear circuits; mobile positive
ions and surface charge-induced inversions. This threeterminal structure is scribed from awafer and assembled in
either a hermetic or plastic package. These devices are
burned in for a predetermined temperature and time. The
same structures becomes sensitive to either failure
mechanism depending upon the bias scheme used during
burn-in. A limit is defined for the leakage current change
during burn-in; afailure indicates awaferfab problem which
will be addressed by the process engineering group.
The CMOS process version allows measurements of
thresholds of various sizes and kinds of N-channel and
P-channel MOSFETs. Body effects, L effective, sheet
resistance, zener breakdown voltage, contact metal resistance
and impact ionization current are measurable with this chip
which is assembled in a 20-lead DIP.
Bipolar Test Pattern

Reliable radiation-hardened devices are produced by LTC
using a proprietary process technology designed to meet or
exceed 1OOk RADS total dose. Qualification testing of these
devices using aCobalt60 source has demonstrated excellent
results on a number of products. Data sheets for our RADhard product line are available from your local sales
representative.

15-37

RELIABILITY ASSURANCE PROGRAM
Electrical testing is performed on the structure before and
after burn-in. After evaluating any sample population shifts
or failures, process engineering is apprised of the results of
this process monitor.
The use of test patterns allows any device to be monitored
and also gives faster unambiguous feedback than is normally
achieved by performing reliability testing on assembled
product. Reliability data is generated in less than one week,
giving immediate feedback to the production line.
LTC utilizes this new reliability control technique in addition
to the conventional reliability audit on randomly pulled
finished product. Operating Life tests are performed and the
distributions of key parameters before and after testing are
evaluated for stability and control.

Quick Reaction Reliability Monitor
As a complement to the wafer level reliability program, a
monitor program focused on assembly-related issues has
been fully implemented; -This reliability monitor program,
known as the Quick Reaction Reliability (QR2) monitor, has
been specifically tailored to provide quick feedback of
reliability assessment of the assembly operation. The tests
in the QR2 program are designed to identity reliability
weaknesses associated with wire bonding, die attach, package
encapsulation and contamination-related failures. The actual
tests performed in the QR2 Monitor Program are shown in
Table 4.
In orderto ensure that representative reliability assessment
is made, the QR2 sampling matrix requires QR2 testing of
every date code from each assembly location on each
package type and lead count from that assembly location.
This provides a weekly snapshot of the reliability of all
packages from all assembly locations. The basic strategy is
to evaluate as many production lots as possible to provide
maximum confidence to our customers.
Should a failure occur during QR2 testing, the entire
production lot is impounded before shipment. Failures are
analyzed to determine validity and the root cause of any valid
failure. Quite often additional samples are pulled and tested
for an extended period of time. Lots with substandard
reliability performance are scrapped. The data generated
from this program is used to establish a program for
continuous quality improvement with ourassemblyfacilities.

15-38

Long Term Reliability Monitor
LTC also conducts a traditional long term reliability monitor
program on devices pulled from Boxstock. This long-term
reliability monitor is used for extended life and end-of-life
approximations such as Failure in Time (FIT) calculations.
The long term reliability monitor also serves as a check
against our short-term reliability estimates.
The long-term reliability tests are designed to evaluate
deSign, waferfab and assembly-related weaknesses. Industry
standard reliability tests and the relatively new Highly
Accelerated Stress Test (HAST) have been incorporated into
this program. The long term reliability monitor tests are
shown in Table 5.
The most severe tests for plastiC package devices are
the temperature and humidity tests, particularly HASTtesting.
We. have included HAST testing in the long-term reliability
monitor program dueto the highly accelerated nature of this
test. This test accelerates the penetration of moisture through
the external protective encapsulant or along the interface
between the encapsulant and the metallic lead frame.
Additionally, the HAST test is conducted with the device
under bias. The HAST test places the plastiC devices in a
humid environment of 85% relative humidity under 45psi of
pressure at 130°C to 140°C. Under these conditions, 24
hours of HAST testing at 140°C is roughly equivalent to
1,000 hours of 85°C/85% RH testing. The employment of
HAST testing has dramatically reduced the length of time
required for qualification.
Qual Samples Being Loaded into the HAST System

RELIABILITY ASSURANCE PROGRAM
Acceleration Factor Using HAST Compared to 85/85

Scanning Electron Microscope with
X-RAY Dispersive Analysis

100.00

a:

§
it
z

Q 10.00

~w

-'

w

~
95 105 115 125 135 145
TEMPERATURE (OC)

Group Cand 0 Testing
Since LTC is a certified producer of JAN 38510 and 883
product, we perform Group Cand Dtesting regularly on our
devices. This data is also incorporated into the reliability
datapack (consult LTC). The Group C and D test lists are
shown in Tables 6 and 7.

Failure Analysis and Corrective Action
LTC is extremely concerned with all failures whether they
occur in-house or at a customer location. We have focused
significant resources in the area of failure verification and
analysis.
LTC offers failure analysis services to its customers, free of
charge. In an emergency situation a preliminary failure
analysis report can be issued within 24 hours. Our failure
analysis database revealed that the vast majority of all
devices returned for failure analysis are invalid due to
improper application, gross misuse, orthey are fully functional
and meet all data sheet parameters. LTC also offers
outstanding applications assistance to help the customer
achieve the full value of our products.

We are equally concerned with failures that are identified
during reliability and qualification testing. As with field
failures, the in-house failures are analyzed in detail to pinpoint
the exact failure mechanism and to identify the root cause.
In many cases where ESD or EOS is the suspected cause of
the failure, fault simulation is carried out by over-stressing
good devices to recreate the fault condition.
LTC has invested in failure analysis resources in the form of
experienced, seasoned engineers, and equipment such as a
full metallurgical lab, IC deprocessing equipment and a
scanning electron microscope with voltage contrasts,
Electron Beam-Induced Current (EBIC), Energy Dispersive
X-ray Analysis (EDAX), and a computerized database.
All failure analysis reports are documented in detail and
distributed appropriately. All valid failure analyses require
prompt and effective corrective action which is driven to
completion by the quality and reliability organization.
Corrective actions are implemented in accordance with
LTC's internal document "Corrective Action Procedure"
which details the method and responsibilities for timely
corrective action. This procedure is summarized in aseparate
brochure which is available to our customers upon request.

15-39

RELIABILITY ASSURANCE PROGRAM
Failure Rate Calculations

Typical Failure Analysis Flow
1. A request for failure analysis Initiates
the action of analyzing failures.
2. All details of the failure are recorded and a failure
analysis number is assigned to the request.

Failure rates at LTC are calculated using MIL-STD-690B
which is based upon the exponential distribution model for
predicting microelectronic device reliability. Examples of FIT
and Mean Time Between Failure (MTBF) are shown in the
sample calculation below.
Sample Calculation:

3. Perform external visual examination.

Step 1. Calculate Failure Rate at Test Condition
(150°C).

4. Read and record all electrical parameters
at all temperatures noting falling parameters.

Assume 77 units of Op-Life for 1000 hours with 0 failures:

5. Perform hermeticity (not for
plastic packaged devices).

Device Hours at Test Condition =77 Units x 1000 Hours
equals 77,000 Device Hours at 150°C

6. Bake at 175'C for 16 hours.
7. Read and record all parameters at all temperatures
noting falling and shifting parametric readings.

Value from Table A -1 (MIL - STD- 690B)
Fail Rate = - - - - - - - - - ' - - - - - - - - ' Device Hours

8. Decapsulation or delidding.

= 91,641 =1.19%1k Hours(11,900 FITs\
77,000
1

9. Internal visual microscopic
inspection from 5X to 400X.
10. Read and record all parameters at all temperatures
noting failing and shifting parameters.
11. Review all pertinent date and plan the next
series of steps based upon the results so far.

The Arrhenius model is used to extrapolate afailure rate from
an accelerated test condition to ause temperature condition.
Step 2. Calculate Acceleration Factor and Extrapolate
Equivalent Failure Rate to 55°C.

At = Acceleration Factor

12. Remove topside nitride and oxide layers.
13. Read and record all parameters at all temperatures
noting falling and shifting parameters.
14. Probe circuit using micromanipulator
in order to Isolate the failure site.
15. Scanning electron microscopy.
16. Voltage contrast/electron
beam-Induced current.

(

At = e

1.0
0.0000863

17. Cross-sectioning and junction staining.
18. Fault simulation for electrostatic discharge
damage and electrical overstress-related failures.
19. Analyze all the results of these steps including
observations, discussions and recommendations.
RAPOB

15-40

At =2791

)( 1
328

1)
423

RELIABI LlTY ASSURANCE PROGRAM
Where:

Reliability Datapack

Ea =Activation Energy (Assume 1.0 eV)
K = Boltzmann's Constant = 8.63 X 10-5 eV/oKelvin
T2 =Test Condition Temperature in °Kelvin
T1 = Use Condition Temperature in °Kelvin
e =2.71828 (Natural Antilog)
Now the equivalent failure rate is calculated:
Failure Rate (550C) = Failure Rate at Test Condition
Acceleration Factor
11,900 FITs
2791

On a quarterly basis, the reliability department compiles and
publishes areport which summarizes all the reliability testing
results. This report is intended to provide our customers
with a means of determining system reliability. The data is
presented at 150°C and at 125°C for those customers who
wish to perform their own failure rate calculations. Contact
LTC for this report.
In addition, uptothe minute reliability summary data reports
on particular devices can be generated from the computerized
reliability database. ESD simulation testing reports and
current density calculations of individual device types are
also available upon request.
Should you desire additional information, please contact
your local LTC representative.

= 4.2637 FITs
Finally MTBF is calculated:
MTBF= 100,000 = 234,700,000 Hours
0.000426
or 26,778 Years.

15-41

RELIABILITY ASSURANCE PROGRAM
Table 1. "R" Flow for Plastic Dual·ln·line Packages

Table 2. Screening Flow per MIL·STD·883, Method 5004

l

1MILD 1

BURN·IN

INTERNAL VISUAL

BURN·IN

150"C for 30 hrs
(Equivalent to 160 hrs at
125"C for E. = 1.0eV)

Method 2010
Condition B
100%

Method 1015
160 hrs at 125"C
(or Equivalent)
100%

2nd 25"C
ELECT TEST

STABILIZATION BAKE

~
Full Para ACIDC
PDA10%

1MjRK 1

Method 1008
CondltionC
100%

•

TEMPERATURE
CYCLING

Mark Permanency
Test

Method 1010
CondltionC
10 Cycles
-65"C to 150"C
100%

~

~

lIN.PROCESS QA
Solderability
Test

CONSTANT
ACCELERATION

IN·PROCESS QA

~
13 TEMP ELECT QA 1
O"C, 25"C, 70"C

•l
Ip1r

1st 25"C
ELECT TEST
Full Para AC/DC

~
QA ACCEPTANCE
Method 5005
Group A (Sample/Lot)
Group B (Sample/Lot)
Group C (Sample
Every 3 Months per
Generic Group)
Group D (Sample
Every 6 Months per
Package Type)

FINE LEAK

I EXTERNAL VISUAL I

•
•

Method 1014
Condition A
100%

Method 1014
Condition C
100%

l

15-42

25"C DC (per LTC
Data Sheet)
PDA=5%
125"C or 150"C DC
-55"CDC
25"CAC
100%

Method 2001
Condition E
30K G's Y1 Axis
(TO-3 Pkg at 20K G's)
100%

GROSS LEAK

1=1

•

FINAL ELECTRICAL

•

Method 2009
100%

RELIABILITY ASSURANCE PROGRAM
Table 3. Reliability Qualification Test Guidelines for Plastic Packages

Continuous Operation at Max Rated
Supply Voltage
TA = 125°C or
TA=150°C
Continuous Operation at Max Rated
Supply Voltage, Min Supply Current
= 85°C, 85% RH

1000 Hours
500 Hours

500 Hours
168 Hours

1000 Hours

500 Hours

5%,Aee=0

Temperature Humidity
Bias Life (85/85)

JEDEC Spec 22

Highly Accelerated Stress
Test (HAST)

JEDEC Spec 22

Continuous Operation at Max Rated
Supply Voltage, Min Supply Current
= 140°C, 85% RH, 3

Equivalent to
1000 Hours
85/85

Equivalent to
500 Hours
85/85

5%, Aee = 0

Temperature Cycle (T/C)

MIL-STD-883
Method 1010
Condition C

Air-to-Air, -65°C to 150°C,
>10 Minutes Dwell Time

1000 Cycles

500 Cycles

5%, Aee = 0

Thermal Shock (T/S)

MIL-STD-883
Method 1011
Condition C

Liquid-to-Liquid, - 65°C to 125°C,
> 5 Minutes Dwell Time

1000 Cycles

500 Cycles

5%, Aee = 0

Autoclave (Pressure Pot
with Bias) (BPPT)

JEDEC Spec 22

Continuous Storage at TA = 105°C,
100% RH, 1.67 Atmospheres, Max Rated
Supply Voltage for the Last 3 Hours

350 Hours

350 Hours

5%, Ace = 0

Pot

JEDEC Spec 22

Continuous
100% RH,

350 Hours

350 Hours

5%, Ace = 0

Power Cycle (PW)
Regulators Only

MIL-STD-883
Method 1006

Power Cycled "ON" and "OFF" as
Required to Cycle Case Temperature
Between 60°C and 120°C

50,000 Cycles

10,000 Cycles

15%, Ace = a

Thermal Resistance
(TMLR)

MIL-STD-883
Method 1012
Condition C

Junction to Case or Junction to
Ambient as Appropriate

N/A

N/A

15%, Ace = 0

Dye Penetrant (DY)

MIL-STD-883
Method 1014

Immersion in Dye Penetrant at 60 PSIG
for 2 Hours Minimum

N/A

N/A

15%, Ace = a

X-Ray Inspection
Radiography (XRAY)

MIL-STD-883
Method 2012

Top View Only

N/A

N/A

15%, Aee = 0

121°C,

II
15-43 .

RELIABILIN ASSURANCE PROGRAM
Table 4. Quick Reaction Reliability (QR2) Monitor Program

Continuous Operation at Max Rated
Supply Voltage, TA= 125°C or
= 150°C
Continuous Operation at Max Rated
Supply Voltage, Min Supply Current,
= 85°C, 85% RH

168 Hours

45

5%, Ace = 0

JEDEC Spec 22

Continuous Operation at Max Rated
Supply Voltage, Min Supply Current,
TA = 140°C, 85% RH, 3 Atmospheres

48 Hours

45

5%, Acc = 0

Temperature Cycle (TIC)

MIL -STD-883
Method 1010
Condition C

Air-to-Air, - 65°C to 150°C,
>10 Minutes Dwell Time

100 Cycles

45

5%, Acc = 0

Thermal Shock (TIS)

MIL-STD-883
Method 1011
Condition C

Liquid-to-Liquid, - 65°C to 150°C,
>5 Minutes Dwell Time

100 Cycles

45

5%,Acc=0

JEDEC Spec 22

Continuous
100% RH,

48 Hours

45

5%, Acc = 0

X-Ray Inspection
Radiography (XRAY)

MIL-STD-883
Method 2012

Top View Only

N/A

45

5%, Acc = 0

Package Separation
Visual Inspection

N/A

30X Magnification

N/A

45

5%, Acc = 0

Un molded Strip
Evaluation

N/A

30X Magnification

N/A

Hot Intermittent Opens
Test at Subcontractor

N/A

Automated Electrical Test at 125°C

N/A

250

N/A

Biased Moisture Life Test
(85/85)
or
Highly Accelerated Stress
Test (HAST)

Pot

1 Strip

N/A

Table 5. Long-Term Reliability Monitor Program

Continuous Operation at Max Rated
Supply Voltage, TA= 125°C or
TA = +150°C
Biased Moisture Life Test
(85/85)

Continuous Operation at Max Rated
Supply Voltage, Min Supply Current,
= 85°C, 85% RH

1000 Hours

45

5%, Acc = 0

Highly Accelerated Stress
Test (HAST)

Continuous Operation at Max Rated
Supply Voltage, Min Supply Current,
= 140°C, 85% RH, 3

48 Hours

45

5%, Acc = 0

Temperature Cycle (TIC)

MIL-STD-883
Method 1010
Condition C

Air-to-Air, -65°C to 150°C,
>10 Minutes Dwell Time

1000 Cycles

45

5%,Acc=0

Thermal Shock (TIS)

MIL-STD-883
Method 1011
Condition B

Liquid-to-Liquid, -65°C to 50°C,
>5 Minutes Dwell Time

1000 Cycles

45

5%,Acc=0

Autoclave (Pressure Pot
without Bias) (PPT)

JEDEC Spec 22

Continuous Storage alTA = 121°C,
100% RH, 2 Atmospheres

1000 Hours

45

5%, Acc = 0

15-44

RELIABILITY ASSURANCE PROGRAM
Table 6. Group Cper MIL-STD-883C Method 5005

Group C-1
Operating Life Test
(Op-Life)

MIL-STD-883
Method 1005

Continuous Operation at Max Rated
Supply Voltage
TA= +125°C or
TA= +150°C

1000 Hours
500 Hours

45

N/A

15

5%, Acc = 0

Table 7. Group D per MIL-STD-883C Method 5005

MIL-STD-883
Method 2016

Group 0-3
Thermal Shock
Temperature Cycle
Moisture Resistance
Hermeticity
Visual Exam
End Point Electricals
Group 0-4
Mechanical Shock
Vib. Variable Frequency
Constant Acceleration
Hermeticity
Visual Exam
End Point Electricals

MIL-STD-883
Method 2004
MIL-STD-883
Method 1011
Method 1010
Method 1004
Method 1014
Method 1004/1

15
Condition B2
Condition B
Condition C

MIL-STD-883
Method 2002
Condition B
Method 2007
Condition A
Method 2001
Condition E (Y1 Only)
Method 1014
Method 1010/11

Group 0-5
Salt Atmosphere
Hermeticity
Visual Exam

MIL-STD-883
Method 1009
Method 1014
Method 1009

Group 0-6
Internal Water Vapor

MIL-STD-883
Method 1018

Group 0-7
Adhesion of Lead Finish

MIL-STD-883
Method 2025

Group 0-8
Lid Torque

MIL-STD-883
Method 2024

Condition A

N/A

(Glass Frit Seal Only)

15%, Acc = 0

15

15%, Acc = 0

15

15%, Acc = 0

24 Hours

N/A
N/A

15
15 Cycles
100 Cycles

3

0

N/A

N/A

15

15%, Acc = 0

5

15%, Acc =0

15-45

·
,-,,"°1
I
neJ\.D
~, TECHNOLOGY

QUAUTY ASSURANCE PROGRAM

At Linear Technology Corporation (LTC) our overriding
commitment is to achieve excellence in Quality, Reliability
and Service (QRS) and total customer satisfaction. We
interpret the word "excellence" to mean delivering products that conSistently exceed all the requirements and
expectations of our customers. The commitment to QRS
extends from the president to every employee, from
design to product qualification, and from manufacturing
to shipping. To meet this commitment, LTC has established a comprehensive program called "Quality for the
Nineties."
This program is divided into four separate, but highly
interrelated programs; Quality Environment, Total Quality
Management System (TQMS), Vendor PartiCipation, and
Focus for the Nineties.

Quality Environment

A comprehensive operator training and certification
program has been established that covers every area of
manufacturing from incoming raw material inspection,
waferfabrication, assembly, and testto shipping. Emphasis
is placed on compliance with specifications, statistical
process control (SPC) performance to quality goals,
electrostatic discharge damage (ESD) awareness and
controls, encouraging operators to think quality and
recommend quality improvement ideas.
To ensure compliance with speCifications, aQuality Audit
Team performs a systems audit of key manufacturing
areas and suppliers at periodic intervals. Compliance with
process specifications and the detailed programs of
the Corporate IS09001 Quality Policy are verified, and
discrepancies reported for quick resolution with special
emphasis to eliminate recurring problems. The performance of each area is then rated, providing a strong
incentive for each area to excel.

The first program, Quality Environment, serves as the
building block for three other programs. It entails
establishing an environment that is conducive to the
participation of each and every employee in helping to
build quality into our products. This program encourages
every employee to identify any quality problem and
partiCipate in recommending solutions.

With the philosophy that each department, starting from
incoming raw materials, is considered a customer of the
preceding department, every effort is made by working
closely together to meet or exceed our end-customer
requirements and goals.

Quality for the '90s

Systems Quality Audit-Tracking Recurring Problems

\

\

\

\

~l\

\

f\

\

o
1

15-46

2 3 4

5

6 7 B 9 10 11 12
PERIOD

.L7lJD~

QUALITY ASSURANCE PROGRAM
Total Ouality Management System (TOMS)
The second program starts with the incorporation of
innovative but conservative design and layout rules to
achieve the best performance without sacrificing quality
and reliability. During the design and development cycle,
design, product, package, manufacturing, quality and
reliability engineering groups participate in design reviews to ensure that all program aspects are covered,
ranging from product performance objectives to ensuring
reproducibility and repeatability in wafer fabrication and
assembly. Special emphasis is placed on devising input
protection circuitry to minimize susceptibility to voltage
spikes and ESD, optimizing thermal layout to minimiz.e
parametric drift, and optimizing bond pad layout to maxImize assembly and electrical test yields, at the same time
allowing the die to be assembled in a wide selection of
packages.
Once the design is approved, a stringent manufacturing
qualification test plan is conducted on the initial engineering runs. The test plan is selected to bring out any
weaknesses in the design and any manufacturability problems, and includes reliability stress tests such as high
Raw Material Controls
VENDOR QUALIFICATION·
MINIMUM 3 MANUFACTURING LOTS

QUALIFIED VENDOR LIST·
ADDITION OF NEWLY QUALIFIED VENDOR TO LIST

~
STRINGENT INCOMING INSPECTION ON EVERY LOT:
• DIMENSIONAL
• VISUAL EXAMINATION
• FUNCTIONAL TESTING TO SIMULATE ACTUAL
MANUFACTURING CONDITIONS
• PLATING THICKNESS MEASUREMENTS
• COMPOSITIONAL ANALYSIS
• CHEMICAL ANALYSIS FOR CONTAMINANTS
• SPC ON CRITICAL PARAMETERS

I

I

ACCEPT-RELEASE TO
RAW MATERIAL STORE~

I

temperature Operational Life and HAST (Highly Accelerated Stress Testing) for plastic packages, and MIL-STD883 method 5005 qualification testing for hermetic packages. Product performance on these tests must be equ~1
to or better than similar products within the same generic
group to be considered qualified. Major design, package,
material and process changes are also subjected to these
same stringent qualification requirements. In addition to
achieving the required reliability performance, an engineering change must also achieve manufacturing yield
and quality performance levels equal to or better than the
original productto be considered qualified. Amajor change
control procedure is in place to notify customers of major
changes for approval prior to implementation when required.
In manufacturing, process controls start with vendor
qualification on raw material piece parts. A Qualified
Vendor List is maintained and performance of each vendor
is continuously monitored on aVendor Rating Program. A
dimensional, visual, functional and, where applicable,
compositional analysis is performed on each dir~ct ~aw
material lot. Automated state-of-the-art wafer fabricatIOn,
assembly and test equipment, cassette-to-cassett~ ha~­
dling in wafer fabrication and automated handling In
assembly are utilized, where possible, to maintain manufacturing consistency and quality. Only fully trained and
certified operators are allowed to work on production
material.
Stringent statistical process controls, typically beyond
industry standards, are established for each critical manufacturing step in wafer fabrication, wafer test, assembly,
SEM Monitor of Metallization Quality

I
REJECT-VENDOR
CORRECTIVE ACTION

VENDOR PERFORMANCE TRACKINGTO DETERMINE VENDOR QUALIFICATIONI
DISQUALIFICATION STATUS

VENDOR SELECTIONFOR THE PREFERRED VENDOR LISTING
AND SHIP-TO-STOCK PROGRAM

15-47

QUALITY ASSURANCE PROGRAM
package finishing, mark and pack and shipping as depicted in the Wafer Fabrication, Assembly,Test and Endof-Line flowcharts.
The process controls include monitors of critical assembly
processes and lot acceptance inspection for operations
requiring 100% production inspection. Preseal visual
inspection is performed per MIL-STD-883 Method
2010 Test Condition B. Statistical process control
techniques are employed in optimizing process parameters,
and monitoring process performance through the use of
control charts with action limits and upper and lower
control limits, and in parametric distribution analysis at
electrical test.
Electrical quality is guaranteed by conservative guardbanding on production test programs of a minimum of
three machine guard bands, by using state-of-the-art test
equipment and 0.04% AQL for lot acceptance testing at
25°C for all military and commercial lots. Additional tests,
like rack burn-in, beyond the data sheet specifications on
regulator products are performed by exercising the parts
in athermal shutdown mode. These tests are incorporated
into the test flowto improve reliability and weed out infant
mortality failures. Visual and mechanical quality is optimized by minimizing handling of parts in assembly, test
Actual Xand RChart 01 Aluminum Sputter Deposition Using
Sensor Number Control

='

1i.1 'Ib

'1

-

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bl~J

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[.J..l 30~~~ttH~~~ttHffi
z

The1'\N.~I'IIIt.tIafte.v.

--"

LlrMIIIr Dahnologr Corporation
hasllllBbllshedandllllfl/l8l
1I~~1Or

An _ _

PI-0

Initial
Oxidation

Oxidation
Furnace

Visual

UV Lamp (100%)
20X Microscope

2 Wafers!Run
< 2 Defects! Field
of View

Logbook

Oxide Thickness

Nanospec

3 Wafers!Cycle

y-o

Collector
Mask

Resist Mask
HF Etchan! Bath

Final Inspection

Optical
Microscope 100X

"Z" Pattern Scan
100% of the Wafers

¢

Collector
Implant

Implant

15-52

Production
Log
Logbook

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING FAD REWORK

¢-o

PROCESS
STEP
Collector
Diffusion

DESCRIPTION
Oxidation and
Diffusion
Furnace

EPI

EPI Re-Ox

Deposit EPI
Gemini Reactor

Oxidation
Furnace

INSPECTION!
TEST CRITERIA
Visual

EQUIPMENT
UV Lamp (100%)
20X Microscope

SAMPLING
PLAN
2 Wafers/Run
< 2 Defects/Field

Oxide Thickness

Nanospec

2 Wafers/Run

RII
XJ

4 Point Probe

1 Test Wafer/Run

Philtec Groove

1 Test Wafer/Cycle

Visual

UV Lamp

100% for EPI Spike
More Than 5 Wafers
is Reject

Interference
Contrast Microscope

More Than 1 Slip
and Stacking Fault
is Reject

RII
EPI Thickness

4 Point Probe

2 Reading/Pass

X and Moving R

Nicolet

2 Reading/Pass

Visual

UV Lamp

100%

Run Chart
Logbook

20X Microscope

2Wafers/Run
< 2 Defects/Field
of View

Nanospec

2 Wafers/Run

Final Inspection

Optical Microscope
100X

"Z" Pattern Scan.
100% of the Wafers

Production Log

UV Lamp

100% < 10 Defects/
Wafer

Trend Chart

20X Microscope

2 Wafers/Run
< 4 Defects/Field
of View

4 Point Probe

2 Test Wafers/Run

UV Lamp

100% < 10 Defects/
Wafer

20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

R[l
XJ
TOX

4 Point Probe

2 Test Wafers/Run

Philtec Groove
Nanospec

1 Test Chip/Run
2 Product Wafers/
Run
"Z" Pattern Scan
100% of the Wafers

Production
Logbook

Trend Chart

c;>-o

Resist Mask
HF Etchant Bath

¢-o

Isolation
Predeposition

Boron Deposition Visual
Furnace

ro

~

~

Diffusion
Furnace

SPC
TECHNIQUE
Logbook

Oxide Thickness
Isolation
Mask

Isolation
Diffusion

METHOD AND

RII
Visual

Sinker Mask

Resist Mask
HF Etchant
Bath

Final Inspection

Optical Microscope
100X

Sinker
Predeposition

Deposition
Furnace

Visual

UV Lamp

100% < 10 Defects/
Wafer
2 Test Wafers/Run

Diffusion
Furnace

RII
Visual

4 Point Probe

Sinker
Diffusion

Ru
TOX

UV Lamp

100%

20X Microscope

< 3 Defects/Field
of View

4 Point Probe

2 Test Wafers/Run

Nanospec

2 Test Wafers/Run

Logbook

Logbook

15-53

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING FAB REWORK

~

ra

Q-o

PROCESS
STEP
Base Mask

OESCRIPTION
Resist Mask
HF Etchant Bath

INSPECTION!
TEST CRITERIA
Final Inspection

METHOOANO
EQUIPMENT
Optical Microscope
100X

SAMPLING
PLAN
"Z" Pattern Scan
100% of the Wafers

SPC
TECHNIQUE
Xand R

ISO Oiode
Check

Curve Tracer
BVCSO

BVCSO

Curve Tracer

4 Wafers/Run
>1 Per 12 Readings
Is Fail

Logbook

Base
Predeposition

Deposition
Furnace

Visual

UV Lamp

Xand R

20X Microscope

100% < 10 Defects/
Wafer
2 Wafers/Run
< 4 Defects/Field
of View

R[J

4 Point Probe

2 Test Wafers/Run

Visual

UV Lamp

100% < 10 Defects/
Wafer

20X Microscope

2 Wafers/Run
< 4 Defects/Field
of View

Rr:l
TOX

4 Point Probe

2 Test Wafers/Run

Nanospec

2 Product Wafers/
Run
"Z" Pattern Scan
100% of the Wafers

Base Diffusion

Diffusion
Furnace

Trend Chart

Emitter Mask

Resist Mask
HF Etchant Bath

Final Inspection

Optical Microscope
100X

c{-o

CB Diode
Check

Curve Tracer

BVCBO

Curve Tracer

<10utof16
Readings is Fail

Logbook

Q-o

Emitter
Diffusion

Deposition
Furnace

Ru

4 Point Probe

2 Test Chip/Cycle

Logbook

Beta/LV

Curve Tracer

3 Sites/Wafer
Every Fourth Wafer
> 2 Readings Out
of Spec

Final Inspection

Optical Microscope
100X

"Z" Pattern Scan
100% of the Wafers

Production Log

Optical Microscope
1000X

Critical Dimension
Measure. 2 Wafers/
Run Lot, Accept
on 0 Failures
< 5 Defects/Wafer
100%
2 Readings/ Pass

Trend Chart

"Z" Pattern Scan
100% of the Wafers

Production Log

Critical Dimension
Measure. 2 Wafers/
Run Lot, Accept
on 0 Failures

CD Logbook

9-0

Contact Mask

(

15-54

Resist Mask
HF Etchant Bath

UV Lamp

Metal
Deposition

Deposition
Sputter Machine

Visual
R,lIThickness

4 Point Probe

Metal Mask

Resist Mask
Etchant Bath

Final Inspection

Optical Microscope
200X
Optical Microscope
1000X

Production Log

Xand R

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING FAB REWORK

¢-o
&-0
(

(

era
0-0

~
6-0

PROCESS
STEP
Alloy

DESCRIPTION
Anneal Furnace

Electrical Test

To Evaluate
Electrical
Parameters
LOMAC

LPOM

Passivation
LPCVD Furnace

PEN

PECVD Nitride
Deposition
Furnace

INSPECTIONI
TEST CRITERIA
Visual

METHOD AND

SAMPLING
PLAN
100% < 10 Defects/
Wafer

SPC
TECHNIQUE
Logbook

2 Wafers/Run

Logbook

UV Lamp

100%, > 2 Color
Changes is Fail

X and R

lOX Microscope

3 Wafers/Cycle
< 3 Defects/Field
of View

TOX

Nanospec

Phosphorous
Concentration

10:1 HP Etch Rate

3 Wafers/Cycle
3 Wafers/Cycle

Visual

UV Lamp

100%, >2 Color
Changes Is Fail

lOX Microscope

2 Wafers/Run,
< 5 Defects/Field
of View

Thickness

Nanospec

3 Wafers/Cycle

Index of
Refraction

Elipsometer

3 Wafers/Cycle

Final Inspection

Optical Microscope
100X

"ZOO Pattern Scan.
100% of the Wafers

Production Log

100%

Logbook

Visual

EQUIPMENT
UV Lamp

Trend Chart

Pad Mask

Resist Mask
RF Plasma Etch
and Oxide Wet
Etchant Bath

Electrical Test

Evaluate
Electrical
Parameters

Backlap

Disco.

N/A

N/A

N/A

Logbook

Backside
Metal

Backside
Metallization

Visual

Unaided Eye

100%

Logbook

SEM

Step Coverage

2 Photos

Scanning

1 Wafer/Week

Logbook

General
Metallization

1 Photo

Electron
Microscope

15-55

QUALITY ASSURANCE PROGRAM
WAFER FABRICATION FLOWCHART
Generic CMOS Process
Vendor:
Package:
Location of Wafer Fab:
Assembly:
Final Test:
Q.C. Test:
Source Accept Test:
Qua lily Contact:

FLOWCHART
INCOMING FAB REWORK
\7

Linear Technology Corporation
Plastic SOIC/DIP
Linear Technology Corporation, Milpitas, CA
Carsem Unisem Penang Malaysia, ASAT Hong Kong
Linear Technology Corporation, Milpitas, CA, or Singapore
Linear Technology Corporation, Milpitas, CA, or Singapore
Linear Technology Corporation, Milpitas, CA, or Singapore
QA Manager, LTC, Milpitas, CA
(408) 432-1900
PROCESS
STEP
Incoming Raw
Material
Inspection

DESCRIPTION
Wafers

INSPECTION!
TEST CRITERIA
Visual: Scratches,
Pits, Haze, Craters,
Dimples,
Contamination,
Oxygen/Carbon
Measurement
Resistivityl
Conductivity
Dimensional
Thickness and
Taper/Bow
Orientation
Cof CVerification
Against "MPS"
Requirements

Photo Mask
Plates

Visual C.D.
Measurement

Chemicals

Cof CVerification
Against "MPS"
Requirements

Gases

Plus Yearly
Gas Analysis

METHOO ANO
EQUIPMENT

V INCOMING
D QUALITY INSPECTION AND GATE

o
o

MANUFACTURING PROCESS
QUALITY MONITOR/SURVEILLANCE

D REWORK

SAMPLING
PLAN

1X Inspection

1.0% AQUo
2.5% AQL Level 1

Infrared
Spectrometer
Magnetron
VII Meter
Calipers
Dial Thickness
Gauge
Break Test

SIS = 2, Acc = 0

SPC
TECHNIQUE
% LAR Trend
Chart and %
Defective Trend
Chart

SIS = 2, Acc = 0
2.5% AQL, Level S1
2.5% AQL, Level S1
S/S=1,Acc=0
Each Batch

AMS-100
Calipers
Comparator

Each Plate

Logbook

UV Lamp

Each Batch

Logbook

Outside Lab

Each Target

Logbook

Logbook

Targets

Cof CVerification

Initial
Oxidation

Oxidation
Furnace

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defectsl
Field of View

c;ro

Oxide Thickness

Nanospec

3 Wafers/Cycle

P-Well
Mask

Resist Mask
HF Etchant Bath

Visual

Optical
Microscope 100X

"Z" Pattern Scan
100% of the Wafers

Production
Log

Q-o

Pre-Implant
Oxidation

Oxidation
Furnace

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defectsl
Field of View

Logbook

Oxide Thickness

Nanospec

3 Wafer/Cycle

15-56

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING FAB REWORK

PROCESS
STEP
P-Well
Implant

DESCRIPTION
Implant

&-0

P-Well Drive

Furnace

0-0

Strip All Oxide

HF Etchant Bath

Pad Oxidation

«-0

INSPECTION!
TEST CRITERIA

METHOD AND
EQUIPMENT

SAMPLING
PLAN

SPC
TECHNIQUE
Logbook

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

Oxide Thickness

Nanospec

3 Wafers/Cycle

Oxidation
Furnace

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

Oxide Thickness

Nanospec

3 Wafers/Cycle

Nitride
Deposition

Nitride
Furnace

Visual

UP Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

Nitride Thickness

Nanospec

3 Wafers/Cycle

9-0

Active Mask

RF Plasma
Etch

Microscope 400X

"Z" Pattern Scan
100% of the Wafers

Production
Log

¢

Field Implant
Mask

Resist Mask
HF Etchant Bath

Visual Inspection
Critical Dimensions
Visual Inspection

Microscope 400X

"Z" Pattern Scan
100% of the Wafers

Production
Log

9

Boron Field
Implant

Implant

CMOS Strip
Resist
N-Field
Implant Mask

RF Plasma
Sulfuric Acid

Visual Inspection

Microscope 100X

"Z" Pattern Scan
100% of the Wafers

Logbook

Resist Mask
HF Etchant Bath

UVVisual

UV Lamp (100%)
20X Microscope

2 Wafers/ Run
< 2 Defects/Field
of View

Production
Log

Visual Inspection

Microscope 100X

"Z" Pattern Scan
100% of the Wafers

&-0

9

6-0

9

Logbook

Logbook
Logbook

Logbook

Logbook

Photo Field
Implant

Implant

Logbook

¢

CMOS Strip
Resist

RF Plasma
Sulfuric Acid

Visual Inspection

Microscope 100X

"Z" Pattern Scan
100% of the Wafers

Logbook

6-0

LOCOS Oxide

Oxidation
Furnace

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

Logbook

Oxide Thickness

Nanospec

3 Wafers/Cycle

?

Plasma Nitride
Strip

RF Plasma
Etch

Visual

UV Lamp (100%)
20X Microscope

9
0

CMOS Cap
Mask

Resist Mask
HF Etchant Bath

Critical Dimensions

Optical
Microscope 100X

2 Wafers/Run
< 2 Defects/Field
of View
"Z" Pattern Scan
100% of the Wafers

Cap Implant

Implant

¢

CMOS Strip
Resist

RF Plasma
Sulfuric Acid

Visual Inspection

Microscope 100X

9

Etch Pad
Oxide

HF Etchant Bath

"Z" Pattern Scan
100% of the Wafers

Logbook

Production
Log
Logbook
Logbook
Logbook

15-57

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING FAB REWORK

6

PROCESS
STEP

Gate Oxide

DESCRIPTION

Oxidation
Furnace

METHOOANO
EQUIPMENT

SAMPLING
PLAN

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

P-Channel Oxide
Thickness

Nanospec

3 Wafers/Cycle

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

N-Channel Oxide
Thickness

Nanospec

3 Wafers/Cycle

Visual

Optical
Microscope 100X

"Z" Pattern Scan
100% of the Wafers

INSPECTION/
TEST CRITERIA

SPC
TECHNIQUE

Logbook

«-0

VTP Implant
Mask

Resist Mask
HF Etchant Bath

¢

Boron VT
Implant

Implant

9

CMOS Strip
Resist

RF Plasma
Sulfuric Acid

Visual Inspection

Poly
Deposition

Furnace

Poly Thickness

Back Etch
Mask

Resist Mask
RF Plasma and
HF Etchant Bath

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

Logbook

~

Sinker PreDesposition

Deposition
Furnace

Visual

UV Lamp (100%)
20X Microscope

100% < 10 Defects/
Wafer

Trend Chart

RS (Q/sq)

4 Point Probe

2 Test Wafers/Run

CMOS Gate
Mask

Resist Mask
RF Plasma and
HF Etchant Bath

Visual Inspection

Optical
Microscope 100X

"z" Pattern Scan
100% of the Wafers

Production
Log

¢-o

P + Implant
Mask

Resist Mask

Visual Inspection

Optical
Microscope 1OOX

"z" Pattern Scan

Production
Log

9
9

Pand SID
Implant

Implant

CMOS Strip
Resist

RF Plasma
Sulfuric Acid

Visual Inspection

Microscope 100X

"Z" Pattern Scan
100% of the Wafers

Production
Log

¢

N + Implant
Mask

Resist Mask

Visual Inspection

Microscope 100X

"z" Pattern Scan

Logbook

9

N + SID
Implant

Implant

CMOS Strip
Resist

RF Plasma
Sulfuric Acid

Visual Inspection

Microscope 100X

"Z" Pattern Scan
100% of the Wafers

Logbook

Source Drain
Re-Ox

Oxidation
Furnace

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Oefects/Field
of View

Logbook

¢-o

~

9

&-0

15-58

Production
Log
Logbook

Microscope 100X

"Z" Pattern Scan
100% of the Wafers

Logbook
Logbook

100% of the Wafers

Logbook

100% of the Wafers
Logbook

P + Oxide Thickness

Nanospec

3 Wafers/Cycle

Visual

UV Lamp (100%)
20X Microscope

2 Wafers/Run
< 2 Defects/Field
of View

N + Oxide Thickness

Nanospec

3 Wafers/Cycle

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING FAB REWORK

&-0
0-0

&-0

ra
6-0
«
~

PROCESS
STEP
LPOE

CMOS Getter
CMOS Contact
Mask

INSPECTIONI
TEST CRITERIA
Visual

METHOOAND
EQUIPMENT
UV Lamp (100%)
20X Microscope

SAMPLING
PLAN
2 WaferS/Run
< 2 DefectsIField
of View

LPOE
Thickness

Nanospec

3 Wafers/Cycle

Furnace

RS (Q/sq)

4 Point Probe

Resist Mask
HF Etchant Bath

UV Visual

UV Lamp (100%)
20X Microscope

Visual Inspection

Microscope 100X

2 Test Wafers/Run Trend Chart
2 WaferS/Run
Production
Log
< 2 Oefects/Field
of View
"Z" Pattern Scan
100% of the Wafers
Logbook
< 5 Defects/Wafer
100%
2 Test Chip/Cycle
"Z" Pattern Scan
Production
100% of the Wafers Log

DESCRIPTION
LPOE
LPCVD
Furnace

Aluminum
Desposition

Deposition
Sputter Machine

Visual

UVLamp

RS (Q/sq)

4 Point Probe

CMOS Metal
Mask

Resist Mask
Metal Etchant
Bath

Final Inspection
Critical Dimensions

Optical
Microscope 2
200X

Alloy

Anneal Furnace

Electrical Test

LOMAC
Parametric
Analyzer

LPOM

Passivation
LPCVD
Furnace

Visual

Visual

LPOM Thickness

PEN
(

PECVD
Nitride
Deposition

Phosphorous
Concentration
Visual

Furnace

I

Pad Mask

Resist Mask
RF Plasma
Etch and HF
Etchant Bath

SPC
TECHNIQUE
Logbook

Optical
Microscope 2
1000X

Critical Dimension
Measure 2 Wafers/
Run Lot, Accept On
oFailures

UV Lamp

100% < 10 DefectS/
Wafer
2 Wafers/Run

Logbook

UV Lamp

100%, More Than
2 Color Change
Is Fail

Trend Chart

lOX Microscope

3 WaferS/Cycle
< 3 Defects/Field
of View
3 Wafers/Cycle

Nanospec
10:1 HFEtch Rate
UV Lamp

lOX Microscope

LPOM Thickness

Nanospec

Index of Refraction

Elipsometer

Final Inspection

Optical Microscope
100X

Logbook

3 WaferS/Cycle

100%, More Than
2 Color Change
Is Fail
3 Wafers/Cycle
< 5 DefectsIField
of View
3 Wafers/Cycle
3 WaferS/Cycle
"Z" Pattern Scan
100% of the Wafers

Trend Chart

Production
Log

15-59

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING FAD REWORK

ra

0-0

9

6-0

PROCESS
STEP
Electrical Test

Backlap
Backside Gold
SEM

DESCRIPTION
LOMAC
Parametric
Analyzer
DISCO
Backside
Metallization
Step Coverage
General Metal

15-60

INSPECTIONI
TEST CRITERIA

NlA
Visual
2 Photos
1 Photo

METHOD AND
EQUIPMENT

SAMPLING
PLAN
100%

SPC
TECHNIQUE
Logbook

N/A

Logbook

N/A
Unaided Eye

100%

Scanning
Electron Microscope

CMOS =1 Wafer/
Week

Logbook

N-Well and P-Well =
1 Wafer Every Run

.L7lJD~

QUALITY ASSURANCE PROGRAM
ASSEMBLY FLOWCHART
Generic CMOS or Bipolar Process
Vendor:
Package:
Location of Wafer Fab:
Assembly:
Final Test:
Q.C. Test:
Source Accept Test:
Quality Contact:

Linear Technology Corporation
Plastic SOIC
Linear Technology Corporation, Milpitas, CA
Carsem/Unisem/Penang-Malaysia, ASAT-Hong Kong
Linear Technology Corporation, Milpitas, CA, or Singapore
Linear Technology Corporation, Milpitas, CA, or Singapore
Linear Technology Corporation, Milpitas, CA, or Singapore
QA Manager, LTC, Milpitas, CA
(408) 432-1900

FLOWCHART
INCOMING ASSY REWORK

PROCESS
STEP

\7

Incoming
Raw Material
Inspection

DESCRIPTION

Walers

INSPECTION!
TEST CRITERIA

Visual; Scratches
Pits, Haze, Craters
Dimples,
Contamination
Oxygen/Carbon
Measurement
Resistivity/
Conductivity
Dimentional
Thickness and
Taper/Bow
Orientation
Cof CVerification
Against "MPS"

Chemicals

Requirements
Plus yearly

Gases
100% Die Level
Electrical Test
Rejects Are
Red Inked

Gas Analysis

Wafer Sort
Monitor

Monitor
Probing and
2nd Optical
Quality

Probe Defects
2nd Optical Defects

Kit for
Overseas
Assembly

Wafers Are
Kitted with
LTC Bonding
Diagram and
LTC Assembly
Traveler

Wafer Sort

METHOD AND
EQUIPMENT

\jINCOMING

D QUALITY INSPECTION AND GATE

o
o
o

MANUFACTURING PROCESS
QUALITY MONITOR/SURVEILLANCE
REWORK

SAMPLING
PLAN

1X Inspection

1.0% AQLto
2.5% AQL
Levell

Infrared
Spectrometer
Magnetron
VII Meter
Calipers
Dial Thickness
Gauge
Break Test

SIS = 2, ACC = 0

SPC
TECHNIQUE

% LAR Trend
Chart and
% Defective
Trend Chart

SIS = 2, ACC = 0

2.5% AQL, Level S1
SIS = 1, ACC = 0
Each Bach
Each Bath

Wafer Prober

3X to 75X
Microscope

Minimum of3
Times/Shift
S/S=1,ACC=0

% Defective
Trend Chart

15-61

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING ASS( REWORK

U

PROCESS
STEP
Incoming
Piece Parts
Inspection

DESCRIPTION
Lead Frame

INSPECTIONI
TEST CRITERIA
Visual

METHOOAND
EQUIPMENT
10Xto 30X
Microscope

Mechanical

Optical Comparator,
Calipers, X-Ray
Fluorescence

SAMPLING
PLAN
1% AQL, Level 2

SPC
TECHNIQUE
% LAR Trend
Chart

3 WaferS/Shift

Go/No Go
Inspection

Functional
(Assembly Process
Simulation):
Bond Pull Test
Die Shear Test

9

Wafer Mount

6

9-0

ro
«0
¢
(

Preparation for
Die Separation

Visual Inspection

Unaided Eye

Wafer Saw

Die Separation

Alignment Accuracy

TV Alignment
Micro Automation
on Disco Saw lOX to
30X Microscope

Every Wafer/
Machine, 6 Cuts/
Wafer
oPPM Target

nP Chart

Wafer Saw
Monitor

Saw KERF

Saw Quality
Saw Accuracy

TM Microscope
or Equivalent

Once/Shift
4 Cuts/Machine
CPK 1.5 Target

X RChart

Die Attach

Die Bonded to
Lead Frame
with Epoxy

Visual Inspection

Auto Die Bonder

2 Strips/Mag

nP Chart

Die Attach
Monitor

Visual Quality
Die Shear Test

10Xto 30X
Microscope
Die Shear Tester

4 Units 1XlMachine/ GolNo Go
Shift (or Per
Customer Request)

Epoxy Cure

Epoxy Cure

PyrometerlTC

1XlMachine/Shift
CPK 1.5 Target

XR

Defects

Auto Thermosonic
Ball Bonder

Visual

Microscope

4 Strip/Mag

nP Chart

Bond Pull
Strength

Bond Pull Tester

10 Wires
1X/Machine/Shift
CPK 1.5

X RChart

Ball Shear

Ball Shear Tester

10 Balls
lX/Machine/Shift
CPK 1.5

X RChart

Cratering Test

Visual

4 Units/Day/Shift

GolNo Go

Peel Test

Visual

10 Wires
1XlMachine/Shift
oPPM

Go/No Go

Die, Die Bond,
Wire Bond Visual
Quality

30Xto 60X
Microscope

Every Lot
AQL = 0,04%
oPPM

Waver Mount
Monitor

Wire Bond

Q-o

I
15-62

oPPM Target

Ball Bonds
Gold 1.00 Mil
Wire

Wire Bond
Monitor

QA3rd
Optical
Inspection

Check for
Workmanship
Quality Prior
to Molding

oPPM

oPPM

oPPM

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING AS1rf REWORK

~J

~
0

6-0
9

6
[

PROCESS
STEP
Mold

Mold Monitor

OESCRIPTION
Encapsulation
with Epoxy
Novalac
Molding Quality

INSPECTIONI
TEST CRITERIA

METHOOANO
EQUIPMENT
Transfer Mold

SAMPLING
PLAN

SPC
TECHNIQUE
nP Chart

Visual: Chip, Void
and Cracks,
Misalignment, etc.

oPPM

oPPM

7X1Shift/Machine

nP Chart

Mold Temperature

Pyrometer

1X1ShifVMachine
CPK 1.5

X R Chart

Transfer Press

Hydr Load Cell

1XlMonth/Machine
4 Strips (Min)

Go/No Go

VoidslWire Sweep
Visual Quality

X-Ray

1X1Machine/Shift
Change of Device
Change of Compnd
oPPM

nP Chart

Unaided Eye

Mechanical
Deflash

Remove Mold
Flash from
Package

UF and Heat Sink
Must Be Free from
Mold Flash

3X to 10X
Microscope

4 Strips (Min)
1XlSubloVMachine
oPPM

nP Chart

Siurry
Deflash

Remove Mold
Flash from
Package

UF and Heat Sink
Must Be Free from
Mold Flash

Unaided Eye

10 Strips/4X/ShifV
Machine 0 PPM

nP Chart

Visual
Inspection

Visual

Unaided Eye

100% Inspect

Go/No Go

MPT

Unaided Eye

10 Units/Sublot

Go/No Go

1X1Machine/Shift
CPK 1.5

X R Chart

5 Strips/4X1Shift

nP Chart

Marking
Marking
Permanency
Test
Post Mold
Cure

Mold Quality

Temperature

Pyrometer

Solder Plate

Solder Plate
Bath

Visual Inspection

Unaided Eye

Solder Plate
Inspection

Trim and Form
Singulation

Solder Plate
Quality

Visual
Inspection

oPPM
oPPM

oPPM

Thermometer

1 Reading 2X1Shift
CPK 1.5

Thickness and
Composition

XRF

5 Frames/Shift
CPK 1.5

X R Chart

Visual
Inspection

Unaided Eye
Solderability
Tester

5 Units/Sublot

Go/No Go

Steam Aging

3X to 10X
Microscope

5 Units/Day/
Different Type of
Package 0 PPM

Go/No Go

Thickness and
Composition

XRF

5 Readings/Sublot

Go/No Go

Visual

Unaided Eye

2 Tubes/Sublot

nP Chart

Lead Gap/
Microcrack

3X to 10X
Microscope

10 Units 1X1
Machine/Shift
oPPM

Go/No Go

Coplanarity

Jig and Microscope

6 Units/Machine
Min 1X1Shift
oPPM

X R Chart

oPPM

oPPM
oPPM

15-63

QUALITY ASSURANCE PROGRAM
FLOWCHART
INCOMING ASS( REWORK

6

>-0

?
6

15-64

PROCESS
STEP

DESCRIPTION

Final Visual

Visual

Final Visual
Inspection

Visual
Quality

Pack

Packing and
Preparation for
Delivery

Ship to
LTC

INSPECTloNI
TEST CRITERIA
Mark, Correct
Mark, Marking
Permanency Test
(If Ink Marked)
Visual: Bent Leads
Mold Flash,
Solder Quality, Etc.
Mark, Correct
Mark, Marking
Permanency Test
(If Ink Marked)
Visual: Bent Leads
Mold Flash,
Solder Quality, Etc.

METHOD AND
EQUIPMENT
Unaided Eye

SAMPLING
PLAN

SPC
TECHNIQUE

100%

GolNo Go

Unaided Eye

SIS = 15
ACC=O

GolNo Go

Antistatic Shipping
Tube

Every Lot 100%
Basis

oPPM

QUALITY ASSURANCE PROGRAM
EOL (END-Of-LINE) fLOWCHART
Generic CMOS or Bipolar Process
Vendor:
Package:
Location of Wafer Fab:
Assembly:
Final Test:
Q.C. Test:
Source Accept Test:
Quality Contact:

FLOWCHART

0

Linear Technology Corporation
Plastic SOIC
Linear Technology Corporation, Milpitas, CA
Carsem/Unisem/Penang-Malaysia, ASAT-Hong Kong
Linear Technology Corporation, Milpitas, CA, or Singapore
Linear Technology Corporation, Milpitas, CA, or Singapore
Linear Technology Corporation, Milpitas, CA, or Singapore
QA Manager, LTC, Milpitas, CA
(408) 432-1900
PROCESS
STEP
LTC Incoming
Inspection

DESCRIPTION
Check Quality
of Incoming
Assembled
Material

INSPECTION!
TEST CRITERIA
Package Dimension
External Visual
Mark Permanency
(If Ink-Marked)
Solderability
Die Attach Quality
Lead Fatigue Test

Class Test

Electrical
Test

Test to GuardBanded Data Sheet
Test Limits

QA Electrical
Test at 25°C

Electrical
Quality

QA Electrical
Test at 70°C
and at O°C

Electrical
Quality

Test to GuardBanded Data Sheet
Test Limits
Test to GuardBanded Data Sheet
Test Limits

External
Visual
Inspection

Check for
Package
Quality

Visual: Bent Leads,
Lead Form Criteria,
Mold VoidslCracks,
etc.

I

QA Post Pack
Inspection

Packagel
Pack Quality
Inspection

Verify Correct Top
Mark, Correct Pack
Method, Correct
Labeling, External
Visual Inspection

I

QA Shipbench
Inspection

Plant
Clearance
Inspection

Paperwork Check,
Verify Correct Part
Number and Correct
PAR Count

~

6

METHOD AND
EQUIPMENT
Optical Comparator
and Calipers
3X to 30X
Microscope
MIL-STD-883
Method 2015
MIL-STD-883
Method 2003
Pliers
Lead Fatigue Tester
LTX Integrated
Circuit Test
System
LTX Integrated
Circuit Test
System
LTX Integrated
Circuit Test
System
3X Eyepiece

\lINCOMING

D QUALITY INSPECTION AND GATE

o
o

MANUFACTURING PROCESS
QUALITY MONITORISURVEILLANCE

D REWORK

SAMPLING
PLAN

SIS = 2, Acc = 0

SPC
TECHNIQUE
%LAR
Trend Chart

SIS = 76, Acc = 0
SIS = 4, Acc = 0
SIS = 3, Acc = 0
SIS = 5, Acc = 0
S/S=10,Acc=0
100%

SIS = 125, Acc = 0

PPM Chart

SIS = 125, Acc = 3

PPM Chart

100%

Yield Chart

3Xto 10X
Microscope
Inspection

SIS = 125, Acc = 0

% LAR and
PPM P.A.
Chart

Unaided Eye
Inspection

LTPD = 2%
S/S=116,Acc=0

Ship to
Customer

II
15-65

~~~JD~~~~

_________

R_-F_LO_W

Linear Technology Corporation R-Flow
Reliability has been a key focal point at Linear Technology
Corporation (LTC) since its inception in 1981. Our standard product reliability is monitored closely and we have
generated an extensive reliability database for both hermetic and plastic devices. This data is published on a
quarterly basis and we are seeing very low reliability failure
rates in the under 1 FIT range at 55°C. *
In response to customer requests, we have added an
even higher level of reliability screening for commercial

hermetic and plastic components. LTC's R-Flow adds a
burn-in equivalent to 160 hours at 125°C to the standard
commercial process flow. Following burn-in, a 100%
room temperature test is performed and a 10% PDA
(Percent Defective Allowed) is applied. This PDA limit
affords an additional level of insurance on a lot-by-Iot
basis and prevents the occasional disparate lotfrom being
shipped for critical applications. The additional room
temperature insertion also decreases the probability of
any electrical defectives in the R-Flow lot.

*1 FIT = 1 failure in 109 device hours.

R-Flow lor TO-5 and CERDIP Packages

,..

SEAL

BURN-IN
150°C FOR 30 HRS.
(EQUIV. TO 160 HRS.
AT 125°C FOR Ea = 1eVj

R-Flow lor Plastic Dual-In-Line Packages
--+

MOLD

BURN-IN
1SOOC FOR 30 HRS.
(EQUIV. TO 160 HRS.
AT 125°C FOR Ea = 1oV)

I

I

I

I

TEMP CYCLE
5 CYCLES
- 65°C TO 150°C

2nd 25°C TEST
FULL PARA. AC/DC
PDA 10%

CURE
6 HRS AT moc

2nd 25°C
ELECTTEST
FULL PARA. AC/DC
PDA 10%

I

I

I

I

IN PROCESS QA
FINE/GROSS LEAK

MARK

SOLDER PLATE

MARK

I

I

I

I

SOLDER DIP (H-PKG)
OR
TIN PLATE (J-PKG)

IN-PROCESS QA
SOLDERABILITY
TEST

IN-PROCESS QA

QA ELECT
25°C, 0.1 % AQL

I

I

I

I

QA ELECT

QA ELECT

25°C, 0.1 % AQL

TEMP CYCLE
5 CYCLES
O°C TO 150°C

O°C, 70°C
SKIP LOT

I

I

I

O°C, 70°C
SKIP LOT

OUTGOING QA
(OFFSHORE)

PACK

I

I

I

I

OUTGOING QA
(OFFSHORE)

PACK

INCOMING QA
(ONSHORE)

OUTGOING QA

I

I

I

I

INCOMING QA
(ONSHORE)

OUTGOING QA

1st 25°C
ELECT TEST
FULL PARA. AC/DC

I

I

QAGATE
VISUAL AND
SOLDERABILITY TEST

I

QA ELECT

FINE/GROSS LEAK
100%

1st 25°C TEST
FULL PARA. AC/DC

15-66

I--

SHIP

I--

SHIP

f-.,. .llneJ\Q

~,

ESD PROTECTION PROGRAM

TECHNOLO~GY~-----

Introduction
As integrated circuit technologies achieve higher speed,
smaller geometries, lower power and lower voltage, there
is a trend toward greater ESD (Electrostatic Discharge
Damage) susceptibility. State-of-the-art CMOS ICs can be
susceptible to as little as SOV, a static level that is way
below the SOOV to 1S,OOOV commonly found in an ESD
unprotected work environment. As these state-of-the-art
ICs get designed into systems, the ESD susceptibility of
system hardware also increases proportionately. Industry
estimates of losses due to ESD are in the range of a few
billion dollars annually.
It has now become increasingly more important for all
semiconductor manufacturers and users of semiconductors and other electronic components to fully understand
the nature of ESD, the sources of ESD, and its impact on
quality and reliability, to effectively deal with this silent
chip killer.
Linear Technology Corporation (LTC) has successfully
undertaken a simple but effective ESD Protection Program as part of an overall program designed to enhance
product quality and reliability. Described in this section
are the key points of this program.
This objective is to provide increased ESD awareness by
showing the sources of ESD in the work environment, and
to recommend key points for the successful implementation of an ESD program on a company-wide basis.
The end result of asuccessful ESD program would be the
reduction of line failures, final inspection failures and field
failures, improved manufacturing yields, improved product quality and reliability and lower warranty costs. We
hope that this will help to convince the reader that an ESD
Protection Program must be an integral part of every
electronic company's product quality and reliability program.
Key Elements of a Successful ESD Protection Program
Recent improvements in failure analysis techniques to
correctly identify ESD failures together with an increase in
ESD related information from technical publications, EOS/

ESD symposiums and vendors have significantly helped
to increase ESD awareness.
The ESD Protection Program at LTC was successfully
launched in 1983 when production of ICs was first started.
A constant upgrading of the program is still underway.
During the ongoing efforts to improve product quality and
reliability, previously unrecognized ESD related problems
have been brought to light and corrected.
An effective ESD Protection Program must start at product
deSign, and encompass all manufacturing and handling
steps up to and including field service and repair. Our
design goal is to achieve an ESD susceptibility level of
2,OOOV or greater.
Since the sources of static in any work environment are
similar, key elements of the program successfully implemented at LTC can also be applied to all users of electronic
components. Where these key elements apply, static
controls generiC to an electronic systems manufacturer
are included.
The key elements of asuccessful ESD Protection Program
include:
1. Understanding static electricity.
2. Understanding ESD related failure mechanisms.
3. ESD sensitivity testing.
4. Establishing an ESD task force to outline the requirements of the program, sell the program to management, implementthe program, review progress against
milestones, and follow up to ensure the program is
continuously improved and upgraded. Selecting an
ESD coordinator to interface with all departments
affected.
S. Conducting a facility evaluation to help identify the
sources of ESD and establish static control measures.
6. Setting up an audit program.
7. Selecting ESD protective materials and equipment.
8. Establishing a training and ESD awareness program.

15-67

ESD PROTECTION PROGRAM
What is Static Electricity?

Inductive Charging

Lightning and sparks from a metallic doorknob during a
dry month are examples of static electricity. The magnitude of static charge is dependent on many variables,
among them the size, shape, material composition, surface characteristics and hum id ity. There are basically th ree
primary static generators: triboelectric, inductive and capacitive charging.

Static can also be caused by induction, where a charged
surface induces polarization on a nearby material. Ifthere
is a path to ground for the induced charge, an ESD event
may take place immediately. An example of an induced
charge is when the plastiC portion of a molded IC package
acquires acharge either through triboelectric charging or
other means, produces an electrostatic field and induces
acharge on the conductive leads of the device. When the
device leads are grounded, a short duration damaging
static pulse can take place.

Triboelectric Charging
The most common static generator is triboelectric charging. It is caused when two materials (one or both of which
are insulators) come in contact and are suddenly separated
or rubbed together, creating an imbalance of electrons on
the materials and thus static charge.
Some materials readily give up electrons whereas others
tend to accumulate excess electrons. The Triboelectric
Series lists materials in descending order from positive to
negative charging due to this triboelectric effect. Asample
triboelectric series is shown here. Amaterial that is higher
on the list, e.g., a human body, will become positively
charged when rubbed with a material, e.g., polyester, that
is lower on the list, due to the transfer of electrons from the
human body to the polyester material.
Triboelectric Series
Human Body
Positive
Glass
+
Mica
Nylon
Wool
Fur
Silk
Aluminum
Paper
Cotton
Steel
Wood
Hard Rubber
Orion
Polyester
Polyethylene
Negative
PVC (Vinyl)
Teflon

15-68

Capacitive Charging
The capaCitance of a charged body relative in position to
another body also has an effect on the static field. To see
that this is true, one need only look at the equation a= CV
(charge equals capaCitance times voltage). Ifthe charge is
constant, voltage increases as capacitance decreases to
maintain equilibrium. As capacitance decreases the voltage will increase until discharge occurs via an arc. A low
voltage on a body with a high capacitance to ground can
become a damaging voltage when the body moves away
from the ground plane. For example, a 100V charge on a
common plastiC bag lying on a bench may increase to a
few thousand volts when picked up by an operator, due to
a decrease in capaCitance.
These sources of static can be found almost anywhere in
an unprotected work environment, on personnel wearing
synthetic clothing and smocks, on equipment with painted
or anodized surfaces, and on materials such as carpets,
waxed vinyl floors, and ungrounded work surfaces.
Understanding the Failure Mechanisms
In the past, analysis of electrical failures to pinpoint ESD
as acause was often difficult. Butwith abetter understandingoffailure mechanisms and their causes, and the use of
more sophisticated techniques like scanning electron microscopy (SEM), pinpOinting ESD failures can now be part
of a routine failure analysis.

ESD PROTECTION PROGRAM
arametric or functional failure of bipolar and MOS ICs
an occur as a result of ESD.
he primary ESD failure mechanisms include:
. Dielectric Breakdown: This is a predominant failure
mechanism on MOS devices when the voltage across
the oxide exceeds the dielectric breakdown strength.
This failure mechanism is basically voltage dependent
where the voltage must be high enough to cause
dielectric breakdown. As such, the thinner the oxide,
the higher the susceptibility to ESD. MOS device failures are characterized by resistive shorts from the
input to VDD or Vss.
MOS Transistor Structure
Showing ESD Included Pinholes at Gate Oxide

,---~

SOURCE

GATE

l

~--~

~==:::::F'~-

PINHOLES

3. Parametric Degradation: On precision, high speed
ICs (e.g., bipolar operational amplifiers with a typical
input bias current of 1OpA and low input offset voltage
of typically SOf.LV) ESD can cause device degradation,
besides functional failures. This can impact electrical
performance and adversely affect device reliability.
This degradation in device parametric performance is
far more difficult to pinpoint as an ESD related failure
mode. It is also the least understood among the failure
modes. The extent of this degradation is dependent on
the number of ESD pulses and the level of damage
sustained. The first ESD pulse may not cause an IC to
fail the electrical data sheet limits but with each subsequent ESD pulse, the parametric performance can
degrade to the point where the device no longer meets
the data sheet limits.
There is a great deal of current research focused on
ESD induced latent failures, and there now appears to
be more evidence of this type of failure mechanism.

ORAIN

This failure mechanism can also be found on bipolar
ICs which have metallization runs overactive semiconductor regions separated by a thin oxide. Device failures are characterized by resistive or high leakage
paths .
. Thermal Runaway (Second Breakdown): This failure
mechanism results in junction melting when the melting temperature of silicon (141S0C) is reached. This is
basically a power dependent failure mechanism; the
ESD pulse shape, duration and energy can produce
power levels resulting in localized heating and eventually junction melting, even though the voltage level is
below that required to cause dielectric breakdown.
Breakdown of the emitter-base junction of a NPN
transistor is a common ESD related failure mode on
bipolar ICs, since the highest current density occurs on
the smallest current carrying area which is typically the
emitter-base junction. Low current gain (hFE) is very
sensitive indicator of emitter-base junction damage on
bipolar linear ICs.

£'7lJD~

RESISTIVE SHORT ON A
METALLIZATION STRIP OVER
A THIN OXIDE N + REGION
ON A BIPOLAR Ie

ESD Failure Analysis Program
ESD defect identification must be an integral part of afailure
analysis program. The key objectives are to help identify
the ESD failure mechanism, isolate the cause for failure,
and implement corrective action to prevent recurrence. All
devices suspected of being damaged by ESD after initial
electrical verification, should be failure analyzed.
...

e..

15-69

ESD PROTECTION PROGRAM
An ESD failure analysis program is outlined below.
1. Initial electrical test verification.
2. Review device history to determine if there are any
similar failures in the past. Review ESD sensitivity data
if available.
3. Investigate conditions in any area that can potentially
cause ESD damage. Common potential problem areas
include:
• Proper grounding procedures not being followed
(e.g., conductive table/floor mats not grounded,
personnel not wearing wrist strap, etc.)
• Improper handling (e.g., handling devices at nonESD protected station)
• Transporting devices in unapproved containers (e.g.,
in common plastic bags/tubes/tote boxes)
• Changes in procedures or operation
• Changes in equipment
• Design deficiencies
4. Failure analysis sequence:
Bench testing and curve tracer analysis
Pin-to-pin analysis
Internal visual (1 Ox to 1000 x)
Liquid crystal hot spot detection
Scanning electron microscopy (SEM), secondary
ion mass spectrometry (SIMS), energy dispersive
X-ray analysis (EDX), scanning auger microprobe
(SAM), radiography, voltage contrast, electron beam
induced current (EBIC)
• Plasma/chemical etching
• Special fault decoration
• Micro-sectioning
• Documentation
An excellent failure analysis manual is published by the
Rome Air Development Center titled Failure Analysis
Techniques-A Procedural Guide.
•
•
•
•
•

5. Duplication of failure by stressing identical devices.
The same or similar electrical failure mode is a good
indicator of an ESD induced failure mode.
6. Implement corrective action to prevent recurrence.
Corrective action may include:

15-70

• Component, board, sUb-system or system levelredesign
• Improve ESD controls
., Improve part handling
• Improve ESD awareness
• Improve compliance with ESD protection procedures
• Increase audit frequencies
• Improve packaging materials and procedures

Corrective action taken by the end user should include a
thorough review of electrical and mechanical packaging
designs. In addition the end users should consult with the
IC manufacturer on their findings, request failure analysis
of suspected ESD failures if needed and require the IC
manufacturer to take appropriate corrective action on any
confirmed ESD failure.
ESD Sensitivity (ESDS) Testing

ESDS testing is crucial in helping the IC designer and the
end user evaluate the ESD susceptibility of a particular
device. At LTC, ESDS testing is incorporated into the
failure analysis program and is performed on each device
as part ofthe product characterization program. The ESDS
testing is also part of new product qualification. LTC
performs this ESDS testing according to MIL-STD-883
Method 3015.
The ESDS testing provides immediate feedback to the IC
designer on any weakness found in the design and permits
design correction before product release. The ESDS data
collected is also used as baseline data to evaluate the effect
of any future design changes on the ESDS testing performance, and to help ensure that the final packaging methods meet MIL-M-38510 requirements. Devices are categorized as either Class One, Class two or Class Three,
each with asusceptibility range from OV to 2000V, above
2000V but below 4000V, and above 4000V respectively.
Topside marking with equilateral triangles is specified by
MIL-M-3851 O.
Since people are considered to be a prime source of ESD,
the ESDS test circuit is based on a human ESD model. A
15000 resistor and a1OOpF capacitor are used in the test
circuit. Human capaCitance is typically 50pFto 250pF, with
the majority of people at 100pF or less, and human

ESD PROTECTION PROGRAM
resistance ranges from 10000 to SOOOO. An ESD failure
is defined as a voltage level which causes sufficient
damage to the device such that it no longer meets the
electrical data sheet limits.
After initial ESDS testing, it is important that ESDS test
monitoring be performed periodically on devices from
various lots to determine lot-to-Iot variation. The VZAP-2
report titled "Electrostatic Discharge (ESD) Susceptibility
of Electronic Devices" published by the Reliability Analysis
Center, Rome Air Development Center, contains a wealth
of information on ESDS testing data on devices of different
process technologies from many manufactures. The data
in this report clearly indicates a large lot-to-Iot variation
relating to ESD susceptibility on the same device.

Design for ESD Protection
ESD protection designs employed on LTC devices include:
1. Input clamp diodes
2. Input series resistors to limit ESD current in conjunction with clamp diodes
3. New ESD structures
4. Eliminating metallization runs over thin oxide regions
when they are tied directly to external pins

ESD Task Force

7. Measure the cost-to-benefit ratio of the program

Facilities Evaluation
The ESD task force should be responsible for facility
evaluation. This evaluation should be guided by the ESD
coordinator. The ESD coordinator should be chosen for
strong knowledge of ESD controls and for the ability to
effectively interface with all effected departments. The
primary objective ofthe task force is to pinpoint areas that
represent the source of static electricity and potential yield
losses due to ESD.
Arepresentative, preferably the engineering or production
manager, from each ofthe key manufacturing areas should
be represented on this task force. At LTC this effort is
headed by the Quality Assurance Manager and the Package Engineering Manager. The balance of the ESD task
force members are the Test Engineering, Product Engineering and Production Managers.
The only equipment needed for this survey is afield static
meter which measures static up to a level of SOkV. Both
nuclear and electronic type static meters are available
from manufactures like 3M, Simco, Wescorp, Scientific
Enterprises, Voyager Technologies and ACL.
Regardless of area classification, all manufacturing areas
can be broken down into the following categories for
evaluation purposes.

An ESD task force should consist of members from each
effected department to do the foundation work, sell the
program to management, and implement the program
with the following objective:

1. Personnel: Personnel represents one of the largest
source of static, form the type of clothing, smocks and
shoes that they wear (for example, polyester or nylon
smocks).

1. Develop, approve and implement an ESD control specification covering all aspects of design, ESD protected
materials and equipment, and manufacturing

2. The Environment: The environment includes the room
humidity and floors. Relative humidity plays a major
part in determining the level of static generated. For
example, at 10% to 20% RH a person walking across
a carpeted floor can develop 3SkV versus 1.SkV when
the relative humidity is increased to 70% to 80%.
Therefore the humidity level must be controlled and
should not be allowed to fluctuate over a broad range.

2. Raise the level of ESD awareness
3. Develop a training and certification program
4. Work with all departments on any ESD questions or
problems
S. Develop aprogram to educate and assist sales personnel, distributors and customers to minimize ESD
6. Review and qualify new ESD protective materials and
equipment, and keep specification and training program upgraded

Floors also represent one of the greatest contributors
of static generation on personnel, moving carts or
equipment because of movement across its surface.
Carpeted and waxed vinyl floors are prime static generators.

15-71

IP.!I
IIiI

ESD PROTECTION PROGRAM
3. Work Surfaces: Painted or vinyl-covered table tops,
vinyl-covered chairs, conveyor belts, racks, carts and
shelving are also static generators.
4. Equipment: Anodized surfaces, plexiglass covers, ungrounded solder guns, plastic solder suckers, heat
guns and blowers are also static generators.
5. Materials: Look out for common plastic work holders,
foam, common plastic tote boxes and packaging containers.
Examples of typical static levels are shown in the table
below.
ESD SOURCE
Walking across a carpeted floor

RELATIVE HUMIDITY
10%"20% 70%"80%
1.5kV
35kV

Walking across a vinyl floor

12kV

O.3kV

Picking up a common plastic bag

15kV

O.5kV

Sliding plastiC box over bench/conveyor

15kV

2.0kV

Ungrounded solder sucker

SkV

1.0kV

Plastic cabinets

SkV

1.0kV

This ESD survey should include all direct and support
manufacturing areas where semiconductor and otherelectronic components are handled and should be extended to
cover distribution offices. Once the facility evaluation is
completed, the results are reviewed by the ESD taskforce,
and controls are selected to combat each potential ESD
problem area.
The ESD Protection Program
The degree of static control should be determined by the
most static sensitive device or assembly in the operation.
Top management support and implementing the same
basic controls in all areas with no double standards will
help to ensure success.
The basic concept of complete static protection is the
prevention of static buildup, the removal of any already
existing charges, and the protection of electronic components from induced fields. The first and foremost line of
defense is the personnel wrist strap together with grounded
conductive or static dissipative table tops, and conductive
heel straps and grounded conductive or static dissipative
floor mats.

15-72

To increase ESD awareness at LTC, all ESD Protection
Areas are marked by an identifying label (for example,
label shown below). This label alerts all personnel that ESD
protection procedures are enforced in the area.

ATTENTION
~

ELECTROSTATIC

iI6. SENSITIVE AREA
DO NOT ENTER
WITHOUT PROPER
ELECTROSTATIC
SAFETY EQUIPMENT

r}"
,to

SENSITIVE ELECTRONIC
DEVICES IN THIS AREA.
•
USE CAUTION.
L...-_ _ _ _ _....I

ESP'll4

ESD Protected Workstation
Example of ESD Protected Workstations are shown in
Figures 1 and 2.
Option 1 (Figure 1): All electronic components, subassemblies and assemblies must be handled at an ESD
protected workstation only. The figure illustrates an ESD
protected workstation consisting of a static dissipative
table mat grounded to earth or electrical ground through
a 1Mn series resistor, with the requirement that the
operator wears a grounded insulated conductive wrist
strap with a1Mn series resistor. This 1Mn series resistor
protects the operator from electrical shock, should the
operator come in contact with a potentially lethal voltage.
Option 1 should be used where the operator does not
require a large degree of freedom, e.g., during product
inspection, etc.
Option 2 (Figure 2): Shows an alternate installation
method for an ESD protected workstation. It consists of a
conductive or static dissipative floor mat grounded to
earth or electrical ground through a 1Mn series resistor
with the operator wearing a conductive shoe strap. This
installation is typically used where the operator needs
freedom of movement over alarge area, e.g., environmental chamber loading and unloading, electrical testing, etc.
To be effective the conductive shoe strap must make
contact with the wearer's foot or thin sock and be attached
to the wearer's shoe to maximize contact between the
strap and the conductive or static dissipative floor.

ESD PROTECTION PROGRAM
Iption 3: Utilizes the same conductive or static dissipative
oor mat installation as Option 2 with the exception that
le operator is grounded via a wrist strap through the
quipment ground instead of aconductive shoe strap. It is

utilized where an operator is working with a piece of
freestanding equipment and does not require agreat deal
of freedom of movement.

ELECTRIC POWER EQUIPMENT ~

'r-----.

3. WRIST STRAP

[ ;?/]

2. GROUND CORD

4. INSULATION PAD
1. CONDUCTIVE OR STATIC
DISSIPATIVE TABLE MAT

TABLETOP

GROUND '::'
MATERIALS: 1. 1/16' THICK CONDUCTIVE OR STATIC DISSIPATIVE TABLE MAT WITH
SURFACE RESISTIVITY OF ,;; 1080 PER SQUARE.
2. INSULATED CONDUCTIVE GROUND CORD WITH A SERIES RESISTOR OF 112W
MINIMUM, 1MO± 10%, AND 18AWG OR LARGER INSULATED WIRE.
3. INSULATED CONDUCTIVE WRIST STRAP WITH 1/4W MINIMUM, 1MO ± 10%
AND 20AWG OR LARGER INSULATED WIRE. THE CURRENT LIMITING 1MO
RESISTOR MUST BE LOCATED RIGHT NEXT TO THE WRIST TO PREVENT THE
POSSIBILITY OF SHUNTING THE RESISTOR.
4. POWER TEST EQUIPMENT MUST BE CHASSIS GROUNDED VIA A 3-PRONG
PLUG, AND PLACED ON AN INSULATION PAD MADE OF FORMICA, FIBERGLASS
OR EQUIVALENT MATERIAL.

"D~l

Figure 1

2. CONDUCTIVE SHOE STRAP
1. CONDUCTIVE FLOOR MAT
OR CONDUCTIVE FLOORING

GROUND
MATERIALS: 1. OPTIONAL 1/8' THICK CONDUCTIVE OR STATIC DISSIPATIVE MAT OR

~~~I~¥~';!i 6~~~~b~ ~~lsg~~~~GTIVE FLOOR TILES) WITH A SURFACE
2. CONDUCTIVE SHOE STRAP WITH A SURFACE RESISTIVITY OF,;; 1080 PER SQUARE.
3. INSULATED CONDUCTIVE GROUND CORD WITH A SERIES RESISTOR OF 1/2W
eSDF02
MINIMUM, 1MO±10%, AND 18AWG OR LARGER INSULATED WIRE.

III

Figure 2

L7lJD~

15-73

ESD PROTECTION PROGRAM
Handling
At LTC all products are handled, transported and staged in
volume conductive tote boxes. This offers maximum
protection to the components from triboelectrically generated and inductive static charges. The rule is-under no
circumstances should components be removed from
their approved containers except at an ESD protected
workstation.

Final Packaging
Only antistatic, static disSipative and conductive final
packaging containers (for example, antistatic or conductive dip tubes, volume conductive carbon loaded plastic
bags or metallic film laminate bags, foil lined boxes) are
used. Filler (dunnage) material used should be antistatic,
noncorrosive, and should not crumble, flake, powder,
shred or be of fibrous construction. Conductive packing
materials are preferred since they not only prevent buildup
of triboelectric charge, but also provide shielding from
external fields.

Other ESD Preventative Measures
• Where possible, ban all static bearing materials,
e.g., common plastics, styrofoam from the work environment.
• Use only synthetic material smocks with 1% to 2%
interwoven steel.
• Ensure all electronic and electromechanical equipment
is chassis grounded, including conveyor belts, vapor
degreasers and baskets, solder pots, etc.
• Tips of hand soldering irons are to be grounded.
• All parts of hand tools (e.g., pliers, etc.) which can be
expected to come in contact with electronic components are to be made of conductive material and
grounded.

• High velocity air movement is to be delivered through a
static neutralizer.
• Air ionizers are to be employed in neutralizing static
buildup on insulators if they have to be used or as an
extra precautionary measure for extremely sensitive
devices.
• Do not slide electronic components over a surface.
Air ionizers come in three basic types: nuclear, AC and
pulsed DC. These ionizers can neutralize static charges on
nonconductive materials by supplying the materials with
a stream of both positive and negative ions.
The advantage ofthe AC or pulsed DC type air ionizer is that
there is no recurring annual replacement cost. The disadvantages are: it emits ozone which can damage rubber in
equipment; EMI (Elector Magnetic Interference); and an
imbalance in the stream of ions if not properly maintained,
therefore necessitating frequent preventive maintenance.
The advantages of the nuclear type air ionizer are low
maintenance, no ozone, no EMI and no imbalance problems. The disadvantages are that it requires careful handling because of the radioactive source and the annual
recurring cost to replace the radioactive source.
The selection of air ionizers must be done with care and
with awareness of the above limitations. The squirrel cage
ionized air blower has been proven to produce a significantly more even distribution of ion patterns than does a
conventional fan blower design.

Maintenance
ESD protective floor and table coverings must be properly
maintained. Do not wax them. Cleaners must not degrade
their electrical properties. Vacuum to remove loose particles, followed by a wet mop with a solution of mild
detergent and hot water.

Periodic Audits

• Conductive shorting bars are to be installed on all
terminations for PC boards with electronic components
during assembly, loading, inspecting, repairing, soldering, storing and transporting.

• Compliance with ESD control procedures.

• All PC boards with electronic components are not to be
handled by their circuitry, connector pOints or connector pins.

• Ensure that the conductive ground cord connection is
intact by measuring the series resistance to ground
with an ohmmeter.

15-74

At LTC periodic audits are conducted to check on the
following at least quarterly unless otherwise noted.

ESD PROTECTION PROGRAM
Ensure that wrist straps are still functional by measuring the resistance from the person to ground. The
ground lead of the ohmmeter is connected to the
ground connection of the wrist strap, and the positve
lead is connected to astainless steel electrode (one inch
in diameter and three inches long #304 stainless steel)
which is held by the person. This test method not only
checks the resistance of the series resistor, but also
resistance through the ground cord and any contact
resistance between the wrist strap and the person's
skin. This test procedure is required when wrist straps
with an elastic nylon band with interwoven metallic
strands are used, since the metallic strands break down
with prolonged use. This monitor frequency may be
shortened depending on audit results.
Wrist Strap Resistance Test Setup
OHMMETER

#304
STAINLESS STEEL
ELECTRODE

~,----"

ESO·OS

L7lJn~

• Measure the surface resistivity of conductive or static
dissipative table tops once every quarter using ASTMF-150-72, ASTM-D-257 or ASTM-D-991 test methods
as appropriate.
Materials Selection and Specification
Based on the tremendous amount of ESD protective
materials available, it is important that materials are selected based on a stringent qualification. Once the materials have been selected and specifications defined, a
material procurement specification needs to be initiated
that defines the materials and quality requirements to the
vendor. One of the major pitfalls is to procure material in
haste, e.g., a wrist strap, only to find out it does not
perform reliably.
The SOAR-1 report titled "ESD Protective Material and
Equipment: A Critical Review" published by the Rome Air
Development Center is an excellent reference on the
various types of ESD protective materials available.
At LTC a minimum of three manufacturing lots from a
potential vendor are subjected to qualification testing per
the requirements of the material procurement specification for ESD protective materials. The vendor is considered qualified only when all three lots are found to be
acceptable. Once vendors have been qualified, all incoming ESD protective materials are subjected to a stringent
incoming inspection.
Thefollowing table summarizes asample material and test
specification for ESD protective materials .

15-75

•

ESD PROTECTION PROGRAM
MATERIAL

Wrist Strap

Conductive or Static
Dissipative Table and Floor
Coverings, Conductive Tote
Boxes, Conductive Shoe
Straps
Conductive Foam
Antistatic and Conductive
Dip Tubes

Antistatic and Conductive
Bags
Static Eliminators/lonized
Air Blowers

PROPERTIES/DESCRIPTION

TEST METHODS

• Insulated coil cord with alMn ±10%, 1/4W minimum
series resistor molded into snap fastener (at wrist end),
and an elastic wrist band with inner metallic filaments
and insulative exterior
• Must not shed particles
• Must not support bacterial or fungal growth
• Conductive: surface resistivity < 105n/square, Static
Dissipative: surface resistivity> 105 < 109n/square

Measure series resistance with ohmmeter. Apply normal
tug to both ends of strap and remeasure series resistance.
Resistance must be between 0.8Mn to 1.2Mn.

• Shall not contain more than 30ppm CI, K, Na when a
quantitative chemical analysis is performed
• Must not support bacterial or fungal growth
• Must not exhibit an oily film

With devices inserted into the foam, the foam must not
cause lead corrosion after a24-hour 8soC/8S% RH
temperature/humidity storage.
Must meet an Electrostatic Decay test per Federal Test
Method Standard 101 Test Method 4046. Material charged
to SOOOV must be discharged to 1%of its initial value (50V)
in 2seconds after a24-hour conditioning at 15% relative
humidity.
Test method for antistatic bags same as for antistatic/
conductive dip tubes. Test method for conductive bags
same as for conductive tablelfloor coverings.

• Antistatic bags must meet MIL-B-81705 type.
• Conductive bags must meet MIL-B-l17 and sealing
requirements of MIL-B-8170S
• Must not support bacterial or fungal growth
• Ozone level: 0.1 ppm maximum for 8-hour exposure
• Noise: 60dB maximum
• EMI: nondetectable when measured 6inches away

Training and Certification Program
The training program should be developed to increase
ESD awareness and to assist all personnel in complying
with the ESD control specification. The program should
include:

Test per ASTM-F-1S0-72, ASTM-D-2S7, ASTM-D-991 (for
surface resistivity < 106n/square).

Voltage Decay test: Anonconductive sheet of material

charged to SkV must be discharged to 1%of its initial value
(SOV) in 2seconds at adistance of 2feet from the ionizer or
larger distance if application calls for alarger distance.

idea to show ESD awareness films and video tapes which
are available from a variety of sources (Reference 3
provides a list of films and video tapes). Personnel are
retrained and recertified at a minimum frequency of once
per year.

1. A discussion on "What is Static Electricity?"

Measuring the Benefits

2. How ESD affects ICs

Where pOSSible, the benefits of an ESD Protection Program should be tracked and quantified. The two yardsticks
used at LTC are final test yields and OA electrical average
outgoing quality (AOO). Since the implementation of this
program, there has been asignificant improvement in final
test yields especially on static sensitive CMOS devices.
With the elimination of ESD as a potential failure cause, the
electrical AOO has averaged well under 100ppm for all
products combined. Improvements such as this help to
provide positive feedback to manufacturing and support
personnel on the importance of an ESD Protection Program, and also help to ensure its continuing success.

3. Estimated cost of ESD related losses

4. Materials and equipment for controlling static
5. The importance of wearing the wrist strap
6. The importance of an audit program
7. Encourage floor personnel to alert the ESD task force
to any ESD potential areas
ESD training should be incorporated into the personnel
training and certification program. At LTC only fully trained
and certified personnel are allowed to do actual production
work. To help increase ESD awareness, it is often a good

15-76

.L7lJ~

ESD PROTECTION PROGRAM
leferences
1. DOD-STD-1686

Electrostatic Discharge Control
Program for Electrical and
Electronic Parts, Assemblies and
Equipment

2. DOD-HDBK-263 Electrostatic Discharge Control
Handbook for Electrical and
Electronic Parts, Assemblies and
Equipment
3. SOAR-1

4. VZAP-2

5. EOS-1, EOS-2,
etc.

L7lJD~

State-of-the-Art Report ESD
Protective Materials and Equipment: A Critical Review,
published by the Rome Air
Development Center
Electrostatic Discharge (ESD)
Susceptibility Data, published by
the Rome Air Development
Center

6. MIL-STD-883

Test Methods and Procedures
For Microelectronics

7. MIL-I-38534

General Specification for Integrated Circuits (Microcircuits)
Manufacturing

8. MIL-M-55565

Microcircuits, Packaging of

9. MIL-M-81705

Barrier Materials, Flexible,
Electrostatic - Free, Heat
Sealable

10. FED-STD-101

Preservation, Packaging and
Packing Materials Test Procedures; Test Methods, 4046:
Electrostatic Properties of

11. EIA-625

Requirements for Handling
Electrostatic Discharge-Sensitive
(EDSS) Devices

Electrical Overstress/Electrostatic Discharge Symposium
Proceedings, 1979 to Current
Year

15-77

, ..y . ·tlneJ\12 STATISTICAL PROCESS CONTROL

~,

TECHNOLOGY

LinearTechnology Corporation (LTC) has an active Statistical Process Control (SPC) system. It operates via the
interrelated mechanisms of: a structure, control charts
with built-in contingency action plans, operational area
documentation (flowcharts and control plan detailS), an
SPC training program, each of which is defined in the
Company's officially controlled SPC specification.

Structure
At the core of the SPC system are the Process (or Preventive) Action Teams (PATs). These cross-functional teams
are comprised of individuals directly involved with a
process element or problem. In a production operation,
they typically involve production operators, lead operators, maintenance, engineering and/or supervision. In a
nonproduction operation, the PATs are comprised of
operating employees and representatives of related
functions.
Each operating group (e.g., Wafer Fab) has a formal SPC
presence in the form of an SPC Quality Control Team
(QCT). These SPC QCTs are comprised mostly of the
manager and staff of that particular operating unit bearing
the responsibility to implement and maintain SPC within
their respective areas.
This QCT structure is the leadership ofthat operating unit,
and as such, sanctions the various PATs within its jurisdiction as they implement and maintain SPC and/or solve
specific problems in their respective areas. In addition, the
QCT conducts monthly reviews of SPC charts, action
items and new programs.
The QCTs, in turn, report to the SPC Steering Committee.
This body conSists of the President, Chief Operating
Officer, Vice President of Operations, Vice President of
Quality & Reliability and the SPC Manager. Thus, it has
the corporate leadership responsibility for SPC at Linear
Technology.

15-78

WaferFab
QCT

End-of-Line
QCT

Worldwide
Assembly
QCT

Qua/ity&
Reliability
QCT
SPCFOl

Figure 1. Linear Technology Corporation
SPC Quality Control Teams

Control Charts
The control charts at LTC are manually charted by the
operators to ensure that they are the custodians of the
process, its trends, and defined corrective measures (as
opposed to computerized SPC charting).
The contingency action plan, known as the Out-of-Control
Action Plan (OCAP), defines the specific corrective actions
when the process experiences out-of-control situations.
No control chart is put in place without an OCAP. This
strategy has in effect empowered the work force, while
freeing the engineering staff for systematic and continuous improvement.

Flowcharts and Control Plan Details
The flowcharts serve to graphically display the flow 01
products in each operational area, as well as define and
communicate the critical nodes of that operation. The
details of each critical node are defined in the Control Plan
Detail, which serves as aplanning, reporting and communication tool.

STATISTICAL PROCESS CONTROL
n example of a flowchart and the related Control Plan
etail for one operational area (e.g., The Wafer Fabrication
rea) Figure 2 and Table 1 follow:

PC-1

Training Program
In order to pursue and continue the smooth operation of
the SPC system within LTC, an all-encompassing instructional program for employees was initiated according to
the following plan.

Initial Oxide

Capacitor Oxide

Collector Mask

Contact Mask

Collector Diffusion

Metal Deposition

Epi Growth

Metal Mask

Isolation Mask

Alloy

The content of the training courses is as follows:

Isolation Diffusion

Electrical Test

BASIC SPC: Philosophy of SPC, concepts of variation,
control, capability; tools and techniques for control and
capability, including histograms, capability studies, control charting; 80 problem solving, including normality,
brainstorming, cause and effect diagramming, Pareto
analysis, capability index/ratio.

Low-Pressure Oxide
(Metal)

~C-2

Base Mask

~C-3

Base Diffusion

PECVD Nitride

Emitter Mask

Pad Mask

Emitter Diffusion

Backlap

Low-Pressure Oxide
(Oxide)

Backside Metal

SPC-4

Transfer 10
WaferSor!

Figure 2. General Bipolar Wafer Fabrication Flowchart

Each employee deSignated for SPC training is classified
into one of three groups, and attends the specific classroom instruction for that classification. The courses and
length of training (hours) for each group are designated in
Table 2.

ADVANCED SPC: Review of basic concepts, fundamentals
of Measurement System Evaluation (Gauge R&R), process capability studies, determination and use of control
charts, i.e., X& R, Median & R, X& Moving R, p, np, u, and
c chart techniques. Chart interpretation and the basics of
attributes sampling system.

Ible 1. Linear Technology Corporation Process Control Plan Detail for Bipolar Wafer Fab
Process Capability
Cp
Cpk
1.59 -1.89 1.12 -1.41

,PC Node
Id Process
(SPC-1)
Epi
Growth

Critical
Features
Resistivity

Measurement
Method
4-Point
Probe

Sample
Size
2

Sample
Frequency

SPC Control
System

MSE
(Gauge R&R)

Batch

X & Moving
R Chart with
Adaptive Control

Acceptable

(SPC-2)
;ase Mask

CDs

OSI-VLS1

1 Site!
3 Wafers

Batch

X&RChart
with
Adaptive Control

Acceptable

(SPC-3)
Base
Ie position

Sheet
Resistance

4-Point
Probe

3 Sites!
3 Wafers

Batch

X & R Chart

Acceptable

1.87 - >2.0 1.70 -1.95

On Line

(SPC-4)
LPOM

Thickness

Nanospec

5 Sites!
3 Wafers

Batch

X & R Chart

Acceptable

1.82 - 2.31

On Line

~

1.54

1.54

1.74 -1.94

Status
On Line

Out of
Control*

Process Action Team (PAT) has been initiated to bring process under control.

L7lJD~

15-79

STATISTICAL PROCESS CONTROL
Table 2.
Group II

Trainee Audience

Basic SPC

Advanced SPC

DOE

Team Org.

Tolal

1
2
3

Engineering (Technical)

15
15
15

20
20

24

4
4

63
39
15

ManagemenVSupervision Technicians
Operators

DESIGN OF EXPERIMENTS (DOE): Philosophy and need
of experimental design, experimental methodologies utilizing Fisher &Taguchi concepts. Response Surface Methodology for parameters and tolerance designs, including
AN OVA and analysis of co-variance.
TEAM ORGANIZATION: An outline ofthe SPC organization
within LTG, the concepts of the SPC Quality Control Teams
(SPC aCTs) and Preventive/Process Action Teams (PATs).
Strategies for Detailed Control Plans and Out-of-Control
Action Plans (OCAPs). Concepts of team effectiveness.

-

-

-

ments will become significant. Products and processe
developed using the DOE tools will have the quality bui
in. The consequence of this built-in quality is predictabl,
performance at the lowest possible cost.
100%

r-------------,
Quality
Contribution
due to
INSPECTION

75%

Manufacturing Excellence
One of the LTC goals is manufacturing excellence. The
traditional SPC techniques seekto produce processes that
are capable and in control. To improve those processes
and to determine rational parameters and specification
tolerance of new products and processes requires the
Design of Experiments (DOEs) methodology.
LTC actively pursues the screening techniques described
by Fisher as well as the optimization techniques of Box and
Taguchi. These latter techniques, known as Response
Surface Methodologyand Taguchi Methods, are partiCUlarly useful in developing robust products and processes,
with a minimum of sensitivity to process variation.
Contribution to Quality
Contribution to quality improvement has evolved from one
dominated by ATTRIBUTE INSPECTION (pass/fail) to one
involving amixture of SPC and attribute inspection. As we
progress further, the contribution of Design of Experi-

15-80

50%

25%
Quality
Contribution
due to
DESIGN OF
EXPERIMENTS

0%

'-----''--_~

_ _ _ _ _ _---'

1980
1990
2000
TIME---------SPC'F03

Figure 3. The Semiconductor Quality Evolution

The concepts of SPC and DOE have already been institu
tionalized within LTC and will provide the methodology tl
ensure a process of continuing improvement.

f""'-LinCA.~D~___D_'C_EP_RO_D_UC_TS

~,

TECHNOLOGY

INTRODUCTION
jnearTechnology Corporation (LTC) offers awide variety
)f precision linear ICs in die form. It is our intent to offer
jice electrically tested to levels which can be expected to
field the best possible performance in hybrid circuits.
;omplicating this task is the fact that many specifications
liven for our standard packaged products cannot be
:ested at the wafer level. Further, parameters which are
100% tested at wafer probe testing may shift during the
jie attach/assembly process.
)ata sheets are available that contain ordering information
or obtaining dice products. They are available from your
ocal LTC Sales Rep, or from LTC Marketing.

lENERAL INFORMATION
:Iectrical Testing
)ice are 100% tested in waferform at 25°C to the DC limits
;hown on the dice data sheet for agiven device type. Many
_TC packaged products have multiple electrical grades
lssociated with abasic die type. Across reference appears
In each dice data sheet indicating which die product grade
;hould be ordered to optimize candidates to meet the
;pecifications of the desired finished product grade. This
nformation should be used as a guideline only since LTC
loes not guarantee electrical specifications after assemlly. Since electrical testing is done only at 25°C, no
Ibsolute guarantee can be made regarding performance at
lther temperatures. Some LTC products require postlackage trimming to overcome certain assembly-related
larameter shifts. Details on this trimming may be obained by contacting the factory.

risuallnspection
lice are 100% visually inspected in accordance with MILiTD-883, Method 2010 Condition B.

Chip Dimensions
Chip dimensions are as indicated on individual dice data
sheets. Tolerance is ±1 mil. Chip thickness ranges from
12 mils to 20 mils, depending on product type. Bond pad
dimensions are 4.5 mils x 4.5 mils minimum.

Topside Passivation
LTC products are passivated with a 2- layer system: a
proprietary depOSited oxide gives a crack-free conformal
coverage of metal and oxide steps. A plasma nitride
overcoat protects the die from ionic contamination and
scratches during handling, testing and assembly. Note
that LTC uses fuse link, laser and zener zap trimming
techniques which may require windows in the passivation
over the trim pOints. This passivation system is a major
contributor to the extremely high reliability demonstrated
throughout millions of device hours of accelerated testing
of LTC devices in plastiC and hermetic packages.

Topside Metallization
The metallization is a minimum of 11,000 A thick unless
otherwise specified. The Quality of the metallization step
coverage is monitored via a weekly SEM inspection per
MIL-STD-883, Method 2018.

Backside Metal
Dice products are normally provided without backside
metallization. Contact LTC for details about availability of
LTC products with a particular backside metallization.

Backside Potential
LTC products are junction isolated. For proper operation
the backside must be electrically connected to either the
most negative potential seen by the IC or the most positive
potential. This information is given in the individual dice
data sheets.

15-81

DICE PRODUCTS
Packaging

Electrostatic Discharge (ESD) Precautions

Dice are packaged in compartmentalized waffle packs for
ease of handling and storage. Each waffle pack contains
100 dice. Special packaging methods are also available by
contacting the factory.

Each dice lot is guaranteed to meet the following requirements:

Precision linear devices, espeCially those with very low
(pA) input bias current levels and low « 50J.lV) input offset
voltages are susceptible to shifts in electrical performance
and ESD damage as a result of improper handling. LTC
recommends that ESD precautions, such as grounded
conductive work stations, grounded conductive wrist
straps and grounded equipment, be taken to prevent ESD
damage.

• Internal visual per MIL-STD-883, Method 2010, Condition B: 1.0% AQL Leveili.

ORDERING INFORMATION

Quality Levels of Dice Shipped

• Electrical: Due to variations in assembly methods and
packaging techniques LTC does not guarantee electrical specifications after assembly. When a determination as to the finished products assembly yield is
needed, the lot acceptance testing available at extra
cost should be pursued.

Reliability Assurance
In addition to the more conventional reliability audits
performed on finished products, LTC has innovated a
unique periodic wafer fab reliability audit using aspecially
designed reliability structure that is stepped into all wafers. The test structure is optimized to accelerate the two
primary failure mechanisms in linear circuits: mobile
positive ions and surface charge-induced inversions. This
provides a continuous monitor on the reliability performance of LTC's wafer fab processes and provides immediate feedback to wafer fab typically within one week.

15-82

Dice may be ordered by the part number defined in the dice
data sheet. Minimum direct dice order per delivery is
1,000 pieces or $5,000, whichever is greater. Other minimums and conditions may also apply. Smaller quantities
are available from authorized dice processing companies.
Insome cases, tighter parameter selections than indicated
on the dice data sheets can be obtained by special order.
Please contact the factory for details.

Lot Acceptance Testing
Lot acceptance testing (LAT) based on sample assembly
and testing is available at extra cost. Sample sizes and
acceptable electrical test limits vary from device to device
and must be negotiated at the time of quoting. Contact the
factory for details.

~~~JD~~2~

_______D_ES_'G_N_TO_O_~

Application Notes
AN1

AN2

AN3

AN4

AN5

AN6

AN7

ANB

AN9

Understanding and Applying the LT1DD5 Multifunction Regulator
This application note describes the unique operating characteristics of the LT1005 and describes a number of useful applications
which take advantage of the regulator's ability to control the output
with a logic control signal.
Perlormance Enhancement Techniques for 3-Terminal
Regulators
This application note describes a number of enhancement circuit
techniques used with eXisting 3-terminal regulators which extend
current capability, limit power dissipation, provide high voltage
output, operate from 11 OVAC or 220VAC withoutthe need to switch
transformer windings, and many other useful application ideas.
Applications for a Switched-Capacitor Instrumentation
Building Block
This application note describes awide range of useful applications
forthe LTC1 043 dual precision instrumentation switched-capacitor
building block. Some of the applications described are ultra high
performance instrumentation amplifier, lock-in amplifier, wide range
digitally controlled variable gain amplifier, relative humidity sensor
signal conditioner, LVDTsignal conditioner, charge pump FN and
V/F converters, 12-bit AID converter and more.
Application for a New Power Buffer
The LT1 01 0150mA power buffer is described in anumber of useful
applications such as boosted op amp, afeed-forward, wideband DC
stabilized buffer, a video line driver amplifier, a fast sample-hold
with hold step compensation, an overload protected motor speed
controller, and a piezoelectric fan servo.
Thermal Techniques in Measurement and Control Circuitry
Six applications utilizing thermally based circuits are detailed.
Included are a 50MHz RMS to DC converter, and anemometer, a
liquid flowmeter and others. A general discussion of thermodynamic considerations involved in circuitry is also presented.
Applications of New Precision Dp Amps
Application considerations and circuits for the LT1 001 and LT1 002
single and dual precision amplifiers are illustrated in a number 01
circuits, including strain gauge signal conditioners, linearized platinum RTD circuits, an ultra precision dead zone circuit for motor
servos and other examples.
Some Techniques for Direct Digitization of Transducer Outputs
Analog-to-digital conversion circuits which directly digitize low
level transducer outputs, without DC preamplification, are presented. Covered are circuits which operate with thermocouples,
strain gauges, humidity sensors, level transducers and other
sensors.
Power Conditioning Techniques for Batteries
A variety of approaches for power conditioning batteries is given.
Switching and linear regulators and converters are shown, with
attention to efficiency and low power operation. 14 circuits are
presented with performance data.
Application Considerations and Circuits for a New
Chopper-Stabilized Dp Amp
A discussion of circuit, layout and construction considerations for
low level DC circuits includes error analysis of solder, wire and
connector junctions. Applications include sub-microvolt instru-

AN1D

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

mentation and isolation amplifiers, stabilized buffers and comparators and precision data converters.
Methods for Measuring Dp Amp Settling Time
The AN10 begins with a survey of methods lor measuring op amp
settling time. This commentary develops into circuits for measuring settling time to 0.0005%. Construction details and results are
presented. Appended sections cover oscilloscope overload limitations and amplifier frequency compensation.
Designing Linear Circuits for 5V Operation
This note covers the considerations for designing precision linear
circuits which must operate from asingle 5V supply. Applications
include various transducer signal conditioners, instrumentation
amplifiers, controllers and isolated data converters.
Circuit Techniques for Clock Sources
Circuits for clock sources are presented. Special attention is given
to crystal-based designs including TXCOs and VXCOs.
High Speed Comparator Techniques
The AN13 is an extensive discussion of the causes and cures of
problems in very high speed comparator circuits. A separate
applications section presents circuits, including a0.025% accurate
1Hz to 30MHz V/F converter, a 200ns 0.01% sample-hold and a
1OMHzfiber-optic receiver. Five appendices covering related topics
complete this note.
Designs for High Frequency Voltage-to-Frequency Converlers
Avariety of high performance VlFcircuits is presented. Included are
a 1Hz to 1OOMHz design, a quartz-stabilized type and a 0.0007%
linear unit. Other circuits feature 1.5V operation, sine wave output
an nonlinear transfer functions. A separate section examines the
trade-offs and advantages olvarious approaches to VlF conversion.
Circuitry for Single Cell Operation
1.5V powered circuits for complex linear functions are detailed.
Designs include a V/F converter, a 1O-bit AID, sample-hold amplifiers, a switching regulator and other circuits. Also included is a
section of component considerations for 1.5V powered linear
circuits.
Unique IC Buffer Enhances Dp Amp Designs,
Tames Fast Ampliliers
This note describes some of the unique Ie design techniques
incorporated into afast, monolithic power buffer, the LT1 01 O. Also,
some application ideas are described such as capacitive load
driving, boosting fast op amp output current and power supply
circuits.
Consideration for Successive Approximation AID Converters
A tutorial on SAR type AID converters, this note contains detailed
information on several 12-bit circuits. Comparator, clocking, and
preamplifier designs are discussed. A final circuit gives a 12-bit
conversion in 1.8flS. Appended sections explain the basic SAR
technique and explore D/A considerations.
Power Gain Stages for Monolithic Amplifiers
This note presents output state circuits which provide power gain
lor monolithic amplifiers. The circuits feature voltage gain, current
gain, or both. Eleven designs are shown, and performance is
summarized. A generalized method for frequency compensation
appears in a separate section.

15-83

III

DESIGN TOOLS
AN19

AN2D

AN21

AN22

AN23

AN24

AN25

AN26

LT1D7D Design Manual
This design manual is an extenSive discussion of all standard
switching configurations for the LT1070; including buck, boost,
flyback, forward, inverting and "Cuk." The manual includes comprehensive information on the LT1 070, the external components
used with it, and complete formulas for calculating component
values.
Applications for a DC Accurate Lowpass
Switched-Capacitor Filter
Discusses the principles of operation of the LTC1062 and helpful
hints for its application. Various application circuits are explained
in detail with focus on how to cascade two LTC 1062s and how to
obtain notches. Noise and distortion performance are fully illustrated.
Composite Amplifiers
Applications often require an amplifier that has extremely high
performance in several areas. For example, high speed and DC
precision are often needed. If asingle device cannot simultaneously
achieve the desired characteristics, acomposite amplifier made up
of two (or more) devices can be configured to do the job. AN21
shows examples of composite approaches in designs combining
speed, precision, low noise and high power.
A Monolithic IC for 1DDMHz RMS/DC Conversion
AN22 details the theoretical and application aspects of the LT1 088
thermal RMS/DC converter. The basic theory behind thermal RMS/
DC conversion is discussed and design details of the LT1 088 are
presented. Circuitry for RMS/DC converters, wideband input buffers and heater protection is shown.
Micropower Circuits for Signal Conditioning
Low power operation of electronic apparatus has become increasingly desirable. AN23 describes avariety of low power circuits for
transducer signal conditioning. Also included are designs for data
converters and switching regulators. Three appended sections
discuss guidelines for micropower design, strobed power operation and effects of test equipment on micropower circuits.
Unique Applications for the LTC1D62 Lowpass Filler
Highlights the LTC1062 as a lowpass filter in a phase lock loop.
Describes how the loop's bandwidth can be increased and the VCO
output jitter reduced when the LTC1 062 is the loop filter. Compares
it with a passive RC loop filter.
Also discussed is the use of LTC1 062 as simple bandpass and
bandstop filter.
Switching Regulators for Poets
Subtitled "A Gentle Guide for the Trepidatious," this is atutorial on
switching regulator design. The text assumes no switching regulator design experience, contains no equations, and requires no
inductor construction to build the circuits described.
Designs detailed include flyback, isolated telecom, off-line, and
others. Appended sections cover component considerations, measurement techniques and steps involved in developing a working
circuit.
Acollection of interface applications between various microprocessors/controllers and the LTC1090 family of data acquisition systems. The note is divided into sections specific to each interface.
The following sections are available:

15-84

Microprocessorl
Number
Microconlroller
AID
AN26A
LTC1090
8051
AN26B
LTC1090
68HC05
AN26C
LTC1090
63705
AN26D
LTC1090
COP820
LTC1090
AN26E
TMS7742
AN26F
COP402N
LTC1090
AN26G
LTC1091
8051
AN26H
LTC1091
68HC05
AN261
LTC1091
COP820
AN26J
LTC1091
TMS7742
AN26K
LTC1091
COP402N
AN26L
LTC1091
HD63705VO
AN26M
LTC1090
TMS320C25
AN26N
LTC1091/92
TMS320C25
AN260
LTC1090
Z-80
AN26P
LTC1090
HD64180
AN26Q
LTC1091
HD64180
LTC 1094
AN26R
TMS320C25
These interface notes demonstrate the ease with which the LTC1 090
family can be interfaced to microprocessors/controllers having
either parallel or serial ports. A complete hardware and software
description of the interface is included.
AN27A ASimple Method of Designing Multiple Order All Pole Bandpass
Filters by Cascading 2nd Order Sections
Presents two methods of designing high quality switched-capacitor
bandpass filters. Both methods are intended to vastly simplify the
mathematics involved in filter design by using tabular methods. The
text assumed no filter design experience but allows high quality
filters to be implemented by techniques not presented before in the
literature. The designs are' implemented by numerous examples
using devices from LTC'sSwitched-Capacitorfilterfamily: LTC1060,
LTC1 061, and LTC1064. Butterworth and Chebyshev bandpass
filters are discussed.
AN28 Thermocouple Measurement
Considerations for thermocouple-based temperature measurement
are discussed. A tutorial on temperature sensors summarizes
performance of various types, establishing a perspective on thermocouples. Thermocouples are then focused on. Included are
sections covering cold-junction compensation, amplifier selection,
differential/isolation techniques, protection, and linearization. Complete schematics are given for all circuits. Processor-based linearization is also presented with the necessary software detailed.
AN29
Some Thoughts on DC/DC Converters
This note examines awide range of DC/DC converter applications.
Single inductor, transformer, and switched-capacitor converter
designs are shown. Special topics like low noise, high efficiency,
low quiescent current, high voltage, and wide-input voltage range
converters are covered. Appended sections explain some fundamental properties of different types of converters.
AN3D Switching Regulator Circuit Collection
Switching regulators are of universal interest. Linear Technology
has made a major effort to address this topic. A catalog of circuits
has been compiled so that adesign engineer can swiftly determine
which converter type is best. This catalog serves as a visual index
to be browsed through for a specific or general interest.

DESIGN TOOLS
'N31

IN32

IN33

IN34

IN35

'N36

Linear Circuits for Digital Systems
Subtitled "Some Affable Analogs for Digital Devotees," discusses a
number of analog circuits useful in predominantly digital systems.
Vpp generators for flash memories receive extensive treatment.
Other examples include acurrent loop transmitter, dropout detectors, power management circuits, and clocks.
High Efliciency Linear Regulators
Presents circuit techniques permitting high efficiency to be obtained with linear regulation. Particular attention is given to the
problem of maintaining high efficiency with widely varying inputs,
outputs and loading. Appendix sections review component characteristics and measurement methods.
Converting Light to Digits: LTC1099 Half-Flash B-Bit AID
Converter Digitizes Photodiode Array
This application note describes a linear Technology "Half-Flash"
AID converter, the LTC1 099, being connected to a256 element line
scan photodiode array. This technology adapts itself to handheld
(Le., low power) bar code readers, as well as high resolution
automated machine inspection applications.
LTC1099 Enables PC-Based Data Acquisition Board to
Operate DC-20kHz
A complete design for a data acquisition card for the IBM PC is
detailed in this application note. Additionally, C language code is
provided to allow sampling of data at speed of more than 20kHz. The
speed limitation is strictly based on the execution speed of the "C"
data acquisition loop. A "Turbo" XT can acquire data at speeds
greater than 20kHz. Machines with 80286 and 80386 processors
can go faster than 20kHz. The computer that was used as atest bed
in this application was an XT running at 4.77MHz and therefore all
system timing and acquisition time measurements are based on a
4.77MHz clock speed.
Step-Down Switching Regulators
Discusses the LT1074, an easily applied step-down regulator IC.
Basic concepts and circuits are described along with more sophisticated applications. Six appended sections cover LT1 074 circuitry
detail, inductor and discrete component selection, current measuring techniques, efficiency considerations and other topics.
Acollection of interface applications between various microprocessors/controllers and the LTC1290 family of data acquisition systems. The note is divided into sections specific to each interface.
The following sections are available:
Microprocessor!
Number
Microcontroller
AID
AN36A
LTC1290
8051
AN36B
LTC1290
MC68HC05
AN36C
LTC1290/LTC1090
TMS370
AN36D
LTC1290
COP820C
AN36E
LTC1290
TMS7742
AN36F
LTC1290
COP402N
AN360
LTC1290
Z-80
AN36P
LTC1290
HD64180
These interface notes demonstrate the ease with which the LTC1290
can be interfaced to microprocessors/controllers having either
parallel or serial ports. Acomplete hardware and software description of the interface is included.

AN37

AN3B

AN39

AN40

AN41

AN42

AN43

AN44

Fast Charge Circuits lor NiCad Batteries
Safe, fast charging of NiCad batteries is attractive in manyapplications. This note details simple, thermally-based fast charge circuitry for NiCads. Performance data is summarized and compared
to other charging methods.
FilterCAD User's Manual, Version 1.00
This note isthe manualfor FCAD, acomputer-aided design program
for designing filters with LTC's switched-capacitor filter family.
FCAD helps users design good filters with a minimum amount of
effort. The experienced filter designer can use the program to
achieve better results by providing the ability to play "what if" with
the values and configuration of various components.
Parasitic Capacitance Effects in Step-Up Transformer Design
This note explores the causes of the large resonating current spikes
on the leading edge of the switch current waveform. These anomalies are exacerbated in very high voltage designs.
Take the Mystery Out of the Switched-Capacitor Filter:
The System Designer's Filler Compendium
This note presents guidelines for circuits utilizing LTC's switchedcapacitor filters. The discussion focuses on how to optimize filter
performance by optimizing the printed wiring board, the power
supply, and the output buffering olthe filter. Many additional topics
are discussed such as how to select the proper filter response for
the application and how to characterize a filter's THO for DSP
applications.
Questions and Answers on the SPICE Macromodel Library
This note provides answers to some of the more common questions concerning LTC's Macromodellibrary. Topics include hardware and software requirements, model characteristics, and limitations and interpretation of results.
Voltage Reference Circuit Collection
A wide variety of voltage reference circuits are detailed in this
extensive guidebook of circuits. The detailed schematics cover
simple and precision approaches at a variety of power levels.
Included are 2and 3terminal devices in series and shunt modes for
positive and negative polarities. Appended sections cover resistor
and capacitor selection and trimming techniques.
Bridge Circuits
Subtitled "Marrying Gain and Balance," this note covers signal
conditioning circuits for various types of bridges. Included are
transducer bridges, AC bridges, Wien bridge oscillators, Schottky
bridges, and others. Special attention is given to amplifier selection
criteria. Appended sections cover strain gauge transducers, understanding distortion measurements, and historical perspectives on
bridge readout mechanisms and Wein bridge oscillators.
LT1074/LT1076 Design Manual
This note discusses the use of the LT1 074 and LT1076 high
efficiency switching regulators. These regulators are specifically
designed for ease of use. This application note is intended to
eliminate the most common errors that customers make when
using switching regulators as well as offering inSight into the inner
workings of switching designs. There is an entirely new treatment
of inductor design based upon simple mathematical formulas that
yield direct results. There are extensive tutorial sections devoted to
the care and feeding of the Positive Step-Down (Buck) Converter,
the Tapped Inductor Buck Converter, the Positive-to-Negative
Converter and the Negative Boost Converter. Additionally, many . . .
troubleshooting hints are included as well as oscilloscope techniques, . . .

15-85

DESIGN TOOLS
AN45

AN46

AN47

AN48

AN49

AN50

AN51

AN52

soft-start architectures, and micropower shutdown and EMI
suppression methods.
Measurement and Control Circuit Collection
A variety of measurement and control circuits are included in this
application note. Eighteen circuits, including ultra-low noise amplifiers, current sources, transducer signal conditioners, oscillators,
data converters and power supplies are presented. The circuits
emphasize precision specifications with relatively simple configurations.
Efficiency Characteristics of Switching Regulator Circuits
Efficiency varies for different DC/DC converters. This application
note compares the efficiency characteristics of some of the more
popular types. Step-up, step-down, flyback, negative-to- positive,
and positive-to-negative are shown. Appended sections discuss
how to select the proper aluminum electrolytic capacitor and
explain power switch and output diode loss calculations.
High Speed Amplifier Techniques
This application note, subtitled "A Designer's Companion for Wideband Circuitry," is intended as areference source for designing with
fast amplifiers. Approximately 150 pages and 300 figures cover
frequently encountered problems and their possible causes. Circuits include a wide range of amplifiers, filters, oscillators, data
converters and signal conditioners. Eleven appended sections
discuss related topics including oscilloscopes, probe selection,
measurement and equipment considerations, and breadboarding
techniques.
Using the LTC Op Amp Macromodels .
LTC's op amp macro models are described in detail, along with the
theory behind each model and complete schematics of each topology. Extended modeling topiCS are discussed, such as phasel
frequency response modifications and asymmetric slew rate for
JFET op amp models. LTC's macromodels are optimized for accuracy and fast simulation times. Simulation times can be further
reduced by using streamlining techniques found throughout AN48.
Illumination Circuitry for Liquid Crystal Displays
Current generation portable computers and instruments utilize
backlit liquid crystal displays. The back light requires a highly
efficient, high voltage AC source as well as other supply circuitry.
AN49 details these circuits and also includes sections on efficiency
measurements and instrumentation considerations. A separate
section discusses physical and layout considerations for the
display.
Interfacing to Microprocessor Based 5V Systems
This application note discusses avariety of approaches for interfacing analog signals to 5V powered systems. Synthesizing a "rail-torail" op amp and scaling techniques for AID converters are covered.
Avoltage-to-frequency converter, applicable where high resolution
is required, is also presented.
Power Conditioning lor Notebook and Palmlop Systems
Notebook and palmtop systems need a number of voltages developed from abattery. Competitive solutions require small size, high
efficiency and light weight. This publication includes circuits for
high efficiency 5Vand 3.3V switching and linear regulators, back
light display drivers and battery chargers. All the circuits are
specifically tailored lor the requirements oullined above.
Linear Technology Magazine Circuit Collection, Vol 1
This application note consolidates the circuits from the first few
years of Linear Technology Magazine into one publication. Pre-

15-86

AN53

AN54

AN55

AN56

AN57

sented in the note are avariety of circuits ranging from a50W high
efficiency (> 90%) switching regulatorto steep roll-off filter circuits
with low distortion to 12-bit differential temperature measurement
systems.
Micropower High-Side MOSFET Drivers
This application note describes the operation of high-side Nchannel MOSFET switch drivers designed specifically for operation
in battery-powered equipment, such as notebook and palmtop
computers and portable medical instruments. A selection guide
simplifies the proper choice of MOSFET and driver for a particular
high-side switch application. Circuits to drive and protect load
impedances ranging from large inductors to large capacitors are
described and asection on surface mount and copper clad shunts
is included.
Power Conversion from Milliamps to Amps at Ultra High
Eltlciency (Up to 95%)
This application note discusses the use olthe LTC1147, LTC1148,
and LTC1149 ultra high efficiency switching regulators in a wide
variety of applications. These controllers feature a current-mode
architecture which includes an automatic low current operating
mode called Burst ModelM operation, making greater than 90%
efficiencies possible at output currents as low as 10mA. This
feature maximizes battery life while aproduct is in sleep or standby
modes. In addition, the LTC1148 and LTC1149 are synchronous
switching regulators which achieve high efficiency conversion
from 1OmA to 10A.
Techniques lor 92% Efficient LCD Illumination
This publication details several LCD backlight circuits which feature
92% efficiency. Other benefits include low voltage operation,
synchronizing capability, higher output power for color displays,
and extended dimming range. Extensive coverage of practical
issues includes layout problems, multi-lamp displays, safety and
reliability concerns and efficiency and photometric measurements.
Also included is a review of circuits which did not work along with
appropriate commentary.
"Better Than Bessel" Linear Phase Fillers lor
Data Communications
The pace of the world of digital communications is increasing at a
tremendous rate. Each day the engineer is requested to compact
more data in the same channel bandwidth with closer channel
spacing. This application note discusses some olthe requirements
and techniques for using the new LTC1064/1164 and LTC1264-7
filters which were designed specifically for digital communications.
The terms "channel bandwidth: "eye diagrams" and "linear phase"
filtering are discussed withoutlhe need forthe "engineering speak"
which permeates many textbook explanations of the same
subjects.
Video Circuit Collection
AN57, the Video Circuit Collection, features a variety of video
circuits deSigned at LTC. The LT1204 70MHz multiplexer is featured in anumber of circuits which require excellent video isolation
from channel to channel. High speed voltage and current feedback
amplifiers are highlighted throughoutlhe section on video processing circuits. There is a section on applying Current Feedback
Amplifiers (CFAs) and a number of articles taken from the Linear
Technology Magazine.

DESIGN TOOLS
AN58

AN59

AN60

5V to 3.3V Converters for Microprocessor Systems
Many popular microprocessors operate from 3.3V supplies, yet
they are used in systems where the predominate source of power
is 5V. AN58 presents a collection of both linear and switching
regulator solutions for conversion of 5V to 3.3V at currents ranging
from 1OOmA to 20A. Applications information and acomparison of
various bypass capacitor types is included. Most of the designs can
be easily modified for other intermediate voltages such as 3.45V,
3.7V, and 4.1V.
Applications olthe LT1300 and LT1301 Micropower
DC/DC Converters
This note covers operation and applications of the LT1300 and
LTf301 high efficiency micropower step-up DCIDC converter ICs.
Internal operation of the ICs is described in detail. A variety of
applications are presented, ranging from straightforward 2-cell to
5V converters and 5V to 12V converters to exotic transducer-based
circuits such as flame detectors and CCFL drivers. Converters from
both 2-cell and 4-cell inputs are included. Operating hours at
various load currents are presented and relative merits of different
battery types are discussed.
PCMCIA Card and Card Socket Power Management
Most portable systems have expansion sockets conforming to the
standards set by the Personal Computer Memory Card International
Association (PCMCIA). This standard requires the host to perform
an unusual amount of switching on both the Vcc and VPP voltage
lines. Card designers face difficult power management and DCIDC
conversion issues of their own. Board real estate and component
height are at a premium making design difficult and component
selection critical. This application note discusses in detail both the
host and card designer issues and highlights several new products
designed specifically for these applications.

AN61

AN62

AN63

Practical Circuitry for Measurement and Control Problems
This collection of circuits was worked out between June 1991 and
July of 1994. Most were designed at customer request or are
derivatives of such efforts. Types of circuits include power converters, transducer signal conditioners, amplifiers and Signal
generators. Specific circuits include low noise amplifiers, high
power single cell DCIDC converters, portable high accuracy
barometers, a 10mHz 1% accuracy RMSIDC converter, and
random noise generators. Appended sections cover noise theory
and present a historical perspective of wide band amplifiers.
Data Acquisition Circuit Collection
This application note presents a wide variety of data acquisition
circuits. The detailed circuit schematics cover 8-,10-, and 12-bit
ADC and DAC applications, serial and parallel digital interfaces,
battery monitoring, temperature sensing, isolated interfaces, and
connections to various popular microprocessors and microcontrollers. An appendix covers suggested voltage references.
Power Supply Modules for the P54C-VR Pentium'"
Microprocessor
This application note describes the design of both linear and
switching regulators which provide power for 90MHz Pentium
processors. The circuits are intended to comply with Intel's modular power supply specification and provide sufficient power for
cache RAM and chip sets in addition to the CPU. They are also
capable of providing the additional power required by an upgrade
"overdrive" processor.

Burst Mode is a trademark of linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.

)esign Notes
DESIGN NOTE 1
New Data Acquisition Systems Communicate With Microprocessors Over
Four Wires
DESIGN NOTE 2
Sampling Of Signals For Digital Filtering And Gate Measurements
DESIGN NOTE 3
Operational Amplifier Selection Guide For Optimum Noise Performance
DESIGN NOTE 4
New Developments In RS232 Interfaces
DESIGN NOTE 5
Temperature Measurement Using The LTCI 090/91/92 Series Of Data Acquilition Systems
DESIGN NOTE 6
Operational Amplifier Selection Guide For Optimum Noise Performance
DESIGN NOTE 7
)C Accurate Filter Eases PLL Design
DESIGN NOTE 8
Inductor Selection For LTf070 Switching Regulators
DESIGN NOTE 9
~hopper Amplifiers Complement a DC Accurate Lowpass Filter
DESIGN NOTE 10
:lectrically Isolating Data Acquisition Systems

DESIGN NOTE 11
Achieving Microamp Quiescent Current In Switching Regulators
DESIGN NOTE 12
An LT1013 And LTf014 Op Amp SPICE MacroModel
DESIGN NOTE 13
Closed-Loop Control With The LTC1090 Series Of Data Acquisition Systems
DESIGN NOTE 14
Extending The Applications Of 5V Powered RS232 Transceivers
DESIGN NOTE 15
Noise Calculations In Op Amp Circuits
DESIGN NOTE 16
SWitched-Capacitor Lowpass Filters For Anti-Aliasing Applications
DESIGN NOTE 17
Programming Pulse Generators For Flash EPROMs
DESIGN NOTE 18
A Battery-Powered Laptop Computer Power Supply
DESIGN NOTE 19
A Two-Wire Isolated And Powered 10-Bit Data Acquisition System
DESIGN NOTE 20
Hex Level Shift Shrinks Board Space
DESIGN NOTE 21
Floating Input Extends Regulator Capabilities

15-87

DESIGN TOOLS
DESIGN NDYE 22
New 12-Bit Data Acquisition Systems Communicate With Microprocessors
Over Four Wires
DESIGN NDYE 23
Micropower, Single Supply Applications:
(1) A Self-Biased, Buffered Reference
(2) Megaohm Input Impedance Difference Amplifier
DESIGN NOYE 24
Complex Data Acquisition System Uses Few Components
DESIGN NOYE 25
A Single Amplifier, Precision High Voltage Instrument Amp
DESIGN NOYE 26
Auto-Zeroing AID Offset Voltage
DESIGN NOYE 27
Design Considerations For RS232 Interfaces
DESIGN NOYE 28
A SPICE Op Amp Macromodel For The LT1 012
DESIGN NOYE 29
A Single Supply RS232 Interface For Bipolar AID Converters
DESIGN NOYE 30
RS232 Transceiver With Automatic Power Shutdown Control
DESIGN NOYE 31
Isolated Power Supplies For Local Area Networks
DESIGN NOYE 32
A Simple Ultra Low Dropout Regulator
DESIGN NOYE 33
Powering 3.3V Digital Systems
DESIGN NOTE 34
Active Termination For SCSI-2 Bus
DESIGN NOYE 35
12-Bit 8-Channel Data Acquisition System Interface To IBM PC Serial Port
DESIGN NOYE 36
Ultra Low Noise Op Amp Combines Chopper And Bipolar Op Amps
DESIGN NOYE 37
High Dynamic Range Bandpass Filters For Communication
DESIGN NOTE 38
Applications For A New Micropower, Low Charge Injection Analog Switch
DESIGN NOYE 39
Low Power CMOS RS485 Transceiver
DESIGN NOYE 40
Designing With A New Family Of Instrumentation Amplifiers
DESIGN NOYE 41
Switching Regulator Allows Alkalines To Replace NiCads
DESIGN NOYE 42
Chopper vs Bipolar Op Amps - An Unbiased Comparison
DESIGN NOYE 43
LT1056 Improved JFET Op Amp Macromodel Slews Asymmetrically
DESIGN NOYE 44
A Single Ultra Low Dropou1 Regulator
DESIGN NOTE 45
Signal Conditioning For Platinum Temperature Transducers
DESIGN NOTE 46
Current Feedback Amplifier "Do's and Don't's"
DESIGN NOYE 47
Switching Regulator Generates Both Positive and Negative Supply with a
Single Inductor

15-88

DESIGN NOYE 48
No Design Switching Regulator 5V, 5A Buck (Step Down) Regulator
DESIGN NOYE 49
No Design Switching Regulator 5V Buck-Boost (Positive-to-Negative)
Regulator
DESIGN NOYE 50
High Frequency Amplifier Evaluation Board
DESIGN NOYE 51
Gain Trimming in Instrumentation Amplifier Based Systems
DESIGN NOYE 52
DC-DC Converters for Portable Computers
DESIGN NOYE 53
High Performance Frequency Compensation Gives DC-to-DC Converter 75~
Response With High Stability
DESIGN NOYE 54
A 4-Cell Ni-Cad Regulator/Charger for Notebook Computers
DESIGN NOYE 55
New Low Cost Differential Input Video Amplifiers Simplify Designs and
Improve Performance
DESIGN NOYE 56
3V Operation of Linear Technology Op Amps
DESIGN NOYE 57
Video Ci rcu its Collection
DESIGN NOYE 58
A Simple, Surface Mount Flash Memory Vpp Generator
DESIGN NOYE 59
5V High Current Step-Down Switchers
DESIGN NOYE 60
The LTC1 096 and 1097: Micropower, SO-8, 8-BitAlDs Sample at 1kHz on 31lA
of Supply Current
DESIGN NOYE 61
Peak Detectors Gain in Speed and Performance
DESIGN NOYE 62
No Design Offline Power Supply
DESIGN NOYE 63
2 AA Cells Replace 9V Battery, Extend Operating Life
DESIGN NOYE 64
RS232 Transceivers for Hand-Held Computers Withstand 10kV ESD
DESIGN NOYE 65
Send Color Video 1000 Feet Over Low Cost Twisted-Pair
DESIGN NOYE 66
New 5V and 3V, 12-Bit ADCs Sample at 300kHz on 75mW
and 140kHz on 12mW
DESIGN NOYE 67
A 1mV Offset, Clock-Tunable, Monolithic 5-Pole Lowpass Filter
DESIGN NOYE 68
New Synchronous Stepdown Switching Regulators Achieve 95% Efficiency
DESIGN NOYE 69
Low Parts Count DC/DC Converter Circuit with 3.3V and 5V Outputs
DESIGN NOYE 70
A Broadband Random Noise Generator
DESIGN NOYE 71
Regulator Circuit Generates Both 3.3Vand 5V Outputs from 3.3Vor 5Vto Run
Computers and RS232
DESIGN NOYE 72
Single LTC1149 Delivers 3.3V and 5V at 17W

DESIGN TOOLS
DESIGN NOTE 73
A Simple High Efficiency, Step-Down Switching Regulator
DESIGN NOTE 74
Techniques for Deriving 3.3V from 5V Supplies
DESIGN NOTE 75
RS232 Interface Circuits for 3.3V Systems
DESIGN NOTE 76
PC Card Power Management Techniques
DESIGN NOTE 77
Single LTC1149 Provides 3.3V and 5V in Surface Mount
DESIGN NOTE 78
Triple Output 3.3V, SV, and 12V High Efficiency Notebook Power Supply
DESIGN NOTE 79
Single 4-lnput IC Gives Over 90dB Crosstalk Rejection at 10MHz and is
Expandable
DESIGN NOTE 80
ESD Testing for RS232 Interface Circuits
DESIGN NOTE 81
4x4 Video Crosspoint Has 1OOMHz Bandwidth and 85dB Rejection at 10MHz
DESIGN NOTE 82
5V to 3.3V Regulator with Fail-Safe Switchover
DESIGN NOTE 83
C-Load™ Op Amps Tame Instabilities
DESIGN NOTE 84
Source Resistance Induced Dislortion in Op Amps
DESIGN NOTE 85
Interfacing to Apple LocalTalk" Networks
DESIGN NOTE 86
Ultra-Low Power, High Efficiency DC/DC Converter Operates Outside the
Audio Band
DESIGN NOTE 87
Fast Regulator Paces High Performance Processors
DESIGN NOTE 88
New 500ksps and 600ksps AOCs Match Needs of High Speed Applications
DESIGN NOTE 89
Applications of the LT1366 Rail-to-Rail Amplifier
DESIGN NOTE 90
High Efficiency Power Sources for PentiumlM Processors
DESIGN NOTE 91
5V to 3.3V Circuit Collection
DESIGN NOTE 92
An Adjustable Video Cable Equalizer Using the LT1256
DESIGN NOTE 93
PCMCIA Socket Voltage Switching (Why Your Portable System Needs
SafeSlotT• Protection)
DESIGN NOTE 94
Interfacing to V.35 Networks

DESIGN NOTE 95
Capacitor and EMI Considerations for New High Frequency Switching
Regulators
DESIGN NOTE 96
LTCI451/52153: 12-Bit Rail-to-Rail Micropower DACs in an SO-8
DESIGN NOTE 97
Flash Memory VPP Generator Reference Designs
DESIGN NOTE 98
Highly Integrated High Efficiency DC/DC Conversion
DESIGN NOTE 99
LT1182 Floating CCFL with Dual Polarity Contrast
DESIGN NOTE 100
Dual Output Regulator Uses Only One Inductor
DESIGN NOTE 101
A Precision Wideband Current Probe for LCD Backlight Measurement
DESIGN NOTE 102
RS485 Transceivers Reduce Power and EMI
DESIGN NOTE 103
New LTC1266 Switching Regulator Provides High Efficiency at lOA Loads
DESIGN NOTE 104
LTC141 0: 1.25Msps 12-Bit AID Converter Cuts Power Dissipation and Size
DESIGN NOTE 105
LTC1265: A New, High Efficiency Monolithic Buck Converter
DESIGN NOTE 106
The LTC1392: Temperature and Voltage Measurement in a Single Chip
DESIGN NOTE 107
C-Load™Op Amps Conquer Instabilities
DESIGN NOTE 108
250kHz, 1rnA IQ Constant Frequency Switcher Tames Portable Systems
Power
DESIGN NOTE 109
Micropower Buck/Boost Circuits, Part 1: Converting Three Cells to 3.3V
DESIGN NOTE 110
Micropower Buck/Boost Circuits, Part 2: Converting Four Cells to SV
DESIGN NOTE 111
LT1510 High Efficiency Lithium-Ion Battery Charger
DESIGN NOTE 112
LTC1390: A Versatile 8-Channel Multiplexer
DESIGN NOTE 113
Big Power for Big Processors: The LTC1430 Synchronous Regulator
DESIGN NOTE 114
The LTC1267 Dual Switching Regulator Controller Operates from High Input
Voltages
DESIGN NOTE 115
Create a Virtual Ground with the LT1118-2.S Sink/Source Voltage Regulator
C-Load and SafeSlot are trademarks of Linear Technology Corporation.
LocalTalk is a registered trademark of Apple Computer. Inc.

15-89

DESIGN TOOLS
Applications on Disk
NOISE OISK
This IBM-PC (or compatible) program allows the user to calculate circuit
noise using LTC op amps, determine the best LTC op amp for a low noise
application, display the noise data for LTC op amps, calculate resistor nOise,
and calculate noise using specs for any op amp.

SPICE MACROMOOEL DISK
This IBM-PC (or compatible) high density diskette contains the library of LTC
op amp SPICE macro models. The models can be used with any version of
SPICE for general analog circuit simulations. The diskette also contains
working circuit examples using the models, and a demonstration copy of
PSpice™ by MircoSim. Also included are Application Notes 41 and 48 which
describe the macromodels.
PSpice is atrademark of MicroSim Corporation.

Technical Publications
1990 Linear Databook, Vol/This 1440 page collection of
data sheets covers op amps.
vollege regulators. references.
comparators. fitters. PWMs.
data conversion and interface
products (bipolar and CMOS). in
both commercial and military
grades. The catalog features
well over 300 devices.
$10.00

$10.00

15-90

- This 1248 page supplement
to the 1990 Linear Databook is
a collection of all products introduced in 1991 and 1992 The
catalog contains full data
sheets for over 140 devices.
The 1992 Linear Databook
Supplement is a companion to
the 1990 Linear Databook.
which should not be discarded.
$10.00

$10.00

1994 Llnesr Databook, VOI/IIThis 1826 page supplement to
the 1990 and 1992 Unear
Databooks is a collection of all
products introduced since 1992.
A total of 152 product data
sheets are included with updated
selection guides. The 1994 Linear Databook Vol III is a compan·
ion to the 1990 and 1992 Linear
Databooks. which should not be
discarded. $10.00

$10.00

1992 Linear Databook
Supplement (will become the
1992 Llnesr Databook, VallI)

To Order These Publications
Call Toll Free 1-800-4-LlNEAR

DESIGN TOOLS
Technical Publications
~~~"'i:!~y

-m!fui'''III,1I.

$20.00

$20.00

Power Solutions BrochureThis 64 page collection of circuits
contains real~life solutions for common
power supply design problems. There
are over 45 circuits, including
descriptions, graphs and perlorrnance
specifications. Topics covered include
PCMCIA power management,
microprocessor power supplies,
portable equipment power supplies,
micropower DC/DC, step-up and stepdown switching regulators, off-line
switching regulators, linear regulators
and switched capacitor conversion.

Interface Product HandbookThis 424 page handbook features
LTC's complete line of line driver
and receiver products for RS232,
RS485, RS423, RS422, V.35 and
AppleTalk applications. Linear's
particular expertise in this area
involves low power consumption,
high numbers of drivers and
receivers in one package, mixed
RS232 and RS485 devices, 10kV
ESD protection of RS232 devices
and surlace mount packages.

1990 Linear Applications
Handbook· Volume 1928 pages full of application
ideas covered in depth by 40
Application Notes and 33 Design Notes. This catalog covers
a broad range of "real world" linear circuitry. In addition to detailed, systems-oriented circuits,
this handbook contains broad
tutorial content together with liberal use of schematics and
scope photography. A special
feature in this edition includes a
22-page section on SPICE
macromodels. $20.00

1993 Linear Applications
Handbook· Volume 11Continues the stream of "real
world" linear circuitry initiated by
the 1990 Handbook. Similar in
scope to the 1990 edition, the
new book covers Application
Notes 40 through 54 and Design
Notes 33 through 69. Additionally, references and articles
from non-LTC publications that
we have found useful are also
included. $20.00

SwitcherCAD HandbookThis 144 page manual,
including disk, guides the user
through SwitcherCAD - a
powerlul PC software tool
which aids in the deSign and
optimization of switching
regulators. The program can
cut days off the design cycle by
selecting topologies, calculating
operating paints and specifying
component values and
manufacturer's part numbers.
$20.00

$20.00

To Order These Publications
Call Toll Free 1-80D-4-LlNEAR

15-91

NOTES

15-92

QUICK REFEREnCE InDEX
LT1381 ................. '9408 5-120
LTC1382 ............... '9408 5-127
LTC1383 ............... '9408 5-133
LTC1384 ............... '9408 5-139
LTC1385 ............... '9408 5-145
LTC1386 ............... '9408 5-151
LT1389 ....................... 13-73
LTC1390 ....................... 6-86
LTC1392 ...................... 13-77
LTC1400 ...................... 13-86
LTC1410 ...................... 13-97
LT1413 ................. '9408 2-68
LTC1429 ....................... 4-41
LTC1430 ...................... 4-360
LT1431 ................. '9208 7-13
LT1432 ................. '9208 4-145
LT1432-3.3 .................. 4-137
LTC1443 .................... 13-108
LTC1444 .................... 13-108
LTC1445 .................... 13-108
LTC1451 ....................... 6-58
LTC1452 ....................... 6-58
LTC1453 ....................... 6-58
LT1457 ................. '9408 2-76
LTC1470 ...................... 4-426
LTC1471 ........ .............. 4-426
LTC1472 ...................... 4-437
LTC1477 .................... 13-112
LTC1478 .................... 13-112
LTC1480 ....................... 5-26
LTC1481 ....................... 5-34
LTC1483 ....................... 5-41
LTC1485 ............... '9408 5-166
LTC1487 ....................... 5-49
LT1510 ..................... 13-120
LT1512 ..................... 13-130
LT1521 ........................ 4-79
LT1521-3 ...................... 4-79
LT1521-3.3 ................... 4-79
LT1521-5 ...................... 4-79
LTC1522 .................... 13-134
LT1524 ................. '9008 5-85
LT1525A ............... '9008 5-97
LT1526 ................. '9008 5-105

LT1527A ............... '9008 5-97
LT1528 ........................ 4-91
LT1529 ....................... 4-101
LT1529-3.3 .................. 4-101
LT1529-5 ..................... 4-101
LT1537 ........................ 5-18
LTC1550 .................... 13-142
LTC1551 .................... 13-142
LT1572 ......... '" ........... 4-374
LTC1574 ...................... 4-385
LTC1574-3.3 ................. 4-385
LTC1574-5 ................... 4-385
LT1580 ..................... 13-148
LT1580-2.5 ................ 13-148
LT1584 ....................... 4-112
LT1585 ................ ....... 4-112
LT1587 ....................... 4-112
LT1846 ................. '9008 5-113
LT1847 ................. '9008 5-113
LT3524 ................. '9008 5-85
LT3525A ............... '9008 5-97
LT3526 ................. '9008 5-105
LT3527A ............... '9008 5-97
LT3846 ................. '9008 5-113
LT3847 ................. '9008 5-113
LTC7541A ..................... 6-69
LTC7543 ....................... 6-73
LTC7652 ............... '9008 2-197
LTC7660 ............... '9008
5-9
LTC8043 ....................... 6-80
LTC8143 ....................... 6-73
LTK001 ................. :9008 11-3
LTZ1 000 ............... '9008
3-9
LTZ1 OOOA ............. '9008
3-9
OP-05 ................... '9008 2-321
OP-07 ................... '9008 2-329
OP-07CS8 ............. '9008 2-337
OP-15 ................... '9008 2-341
OP-16 ................... '9008 2-341
OP-27 ................... '9008 2-345
OP-37 ................... '9008 2-345
OP-215 ................. '9008 2-275
OP-227 ................. '9008 2-357
OP-237 ................. '9008 2-357

OP-270 .................
OP-470 .................
REF-01 ..................
REF-02 ..................
SG1524 ................
SG1525A ..............
SG1527A ..............
SG3524 ................
SG3524S ..............
SG3525A ..............
SG3527A ..............

'9208 2-120
'9208 2-120
'9008 3-125
'9008 3-125
'9008 5-85
'9008
5-97
'9008 5-97
'9008 5-85
'9008 5-93
'9008 5-97
'9008 5-97

Note: All products in BOLD are in this Databook. others appear in LTC's 1990, 1992 and 1994 Databooks (,90D8 = LTC's 1990 Databook, '92D8 = LTC's 1992 Databook Supplement
and '94D8 =LTe's 1994 Databook).

LINEAR TECHNOLOGY CORPORATION
1630 McCarthy Blvd., Milpitas, CA 95035-7417
Phone: (408) 432-1900
FAX: (408) 434-0507
Telex: 499-3977

© LINEAR TECHNOLOGY CORPORATION 1995

LT/BNCP 1195 75K



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