1995_Logic_Devices_Digital_Signal_Processing_Data_Book 1995 Logic Devices Digital Signal Processing Data Book

User Manual: 1995_Logic_Devices_Digital_Signal_Processing_Data_Book
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DEVICES NCQRPOAATED

.JULU
628 East Evelyn Avenue
Sunnyvale, California 94086
(408) 737-3300 • FAX (408) 733-7690
Copyright © 1995, LOGIC Devices Incorporated
Product Catalog No. LDSPDB9507 -15M
MVD-OBAB.3-070595

Printed in U.S.A.

-

---------------...-.-.------------

-~---

DEVICES INCORPORATED

IMPORTANT NOTICE
LOGIC DEVICES INCORPORATED (LDI) reserves the right to make
changes to or to discontinue any semiconductor product or service
identified in this publication without notice. LDI advises its customers
to obtain the latest version of the relevant information to verify, before
placing orders, that the information being relied upon is current.
LDI warrants performance of its semiconductor products to current
specifications in accordance with LDI's standard warranty. Testing and
other quality control techniques are utilized to the extent that LDI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
LDI assumes no liability for LDI applications assistance, customer
product design, software performance, or infringement of patents or
services described herein. Nor does LDI warrant or represent that any
license, either expressed or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of LDI
covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
LOGIC DEVICES INCORPORATED products are not intended for use
in life support applications, devices or systems. Use of a LOGIC
Devices product in such application without the prior written consent of
the appropriate LOGIC Devices officer is prohibited.

Copyright © 1995, LOGIC Devices Incorporated

DEVICES INCORPORATED

Ordering Information

•

Video Imaging Products

•

Arithmetic Logic Units & Special Arithmetic Functions
Multipliers & Multiplier-Accumulators
Register Products

II
II
II

Peripheral Products

•

FIFO Products

•

Quality and Reliability

•

Technology and Design Features

•

Package Information

•

Product Listing
Sales Offices

III
•

- .. _.......__ ..

;;; -=a .... =~-

:..:w=:..==
&...iir
--

-""-""'

DEVICES INCORPORATED

PUBLICATION TEAM
Darren Andrus:

Production Team, Cover Design

Michael De Caro:

Project Leader, Production Coordinator, Production Team,
Technical Editing, Cover Design, Cover Production

Tim Flaherty:

Technical Editing

Cecelia Kong:

Cover Design

Table of Contents
1. ORDERING INFORMATION .................................................................................................................................. 1-1
2. VIDEO IMAGING PRODUCTS ............................................................................................................................. 2-1
LF2242
LF2246
LF2247
LF2249
LF2250
LF2272
LF43168
LF43881
LF43891
LF48212
LF48410
LF48908
LF9501
LF9502

12/16-bit Half-Band Digital Filter ........................................................................................................... 2-3
11 x 10-bit Image Filter ............................................................................................................................ 2-11
11 x 10-bit Image Filter with Coefficient RAM .................................................................................... 2-19
12 x 12-bit Digital Mixer .......................................................................................................................... 2-29
12 x 10-bit Matrix Multiplier .................................................................................................................. 2-37
Colorspace Converter/Corrector (3 x 12-bits) ..................................................................................... 2-53
Dual 8-Tap FIR Filter ............................................................................................................................... 2-63
8 x 8-bit Digital Filter ............................................................................................................................... 2-79
9 x 9-bit Digital Filter ............................................................................................................................... 2-91
Alpha Mixer ............................................................................................................................................ 2-103
1024 x 24-bit Video Histogrammer ...................................................................................................... 2-113
Two Dimensional Convolver ................................................................................................................ 2-129
1K Programmable Line Buffer .............................................................................................................. 2-145
2K Programmable Line Buffer .............................................................................................................. 2-153

3. ARITHMETIC LOGIC UNITS & SPECIAL ARITHMETIC FUNCTIONS ..................................... 3-1
Arithmetic Logic Units
L4C381
16-bit Cascadable ALU .............................................................................................................................. 3-3
Special Arithmetic Functions
LSH32
32-bit Cascadable Barrel Shifter ............................................................................................................. 3-15
32-bit Cascadable Barrel Shifter with Registers ................................................................................... 3-25
LSH33
LlOC23
64 x 1 Digital Correlator .......................................................................................................................... 3-33

4. MULTIPLIERS & MULTIPLIER-ACCUMULATORS ................................................................................. 4-1
Multipliers
LMU08
8 x 8-bit Parallel Multiplier, Signed ......................................................................................................... 4-3
LMU8U
8 x 8-bit Parallel Multiplier, Unsigned .................................................................................................... 4-3
12 x 12-bit Parallel Multiplier ................................................................................................................. 4-11
LMU12
LMU112
12 x 12-bit Parallel Multiplier, Reduced Pinout ................................................................................... 4-17
16 x 16-bit Parallel Multiplier ................................................................................................................. 4-23
LMU16
16 x 16-bit Parallel Multiplier, Surface Mount ..................................................................................... 4-23
LMU216
LMU18
16 x 16-bit Parallel Multiplier, 32 Outputs ........................................................................................... 4-31
LMU217
16 x 16-bit Parallel Multiplier, Microprogrammable, Surface Mount .............................................. 4-39
Multiplier-Accumulators
LMA1009 12 x 12-bit Multiplier-Accumulator ....................................................................................................... 4-45
LMA2009 12 x 12-bit Multiplier-Accumulator, Surface Mount ........................................................................... 4-45
LMA1010 16 x 16-bit Multiplier-Accumulator ....................................................................................................... 4-53
LMA2010 16 x 16-bit Multiplier-Accumulator, Surface Mount ........................................................................... 4-53
Multiplier-Summers
LMS12
12 x 12 + 26-bit Cascadable Multiplier-Summer, FIR ......................................................................... 4-61

v

Table of Contents
5. REGISTER PRODUCTS ............................................................................................................................................... 5-1
Pipeline Registers
L29C520
4 x 8-bit Multilevel Pipeline Register (1-4 Stages) ................................................................................. 5-3
L29C521
4 x 8-bit Multilevel Pipeline Register (1-4 Stages) ................................................................................. 5-3
LPR520
4 x 16-bit Multilevel Pipeline Register (1-4 Stages) ............................................................................. 5-11
LPR521
4 x 16-bit Multilevel Pipeline Register (1-4 Stages) ............................................................................. 5-11
LPR200
8 x 16-bit Multilevel Pipeline Register (1-8 Stages) ............................................................................. 5-17
LPR201
7 x 16-bit Multilevel Pipeline Register (1-7 Stages) ............................................................................. 5-17
L29C525
16 x 8-bit Dual8-Deep Pipeline Register (1-16 Stages) ....................................................................... 5-27
LlOC11
4/8-bit Variable Length Shift Register (3-18 Stages) ........................................................................... 5-35
L21C11
8-bit Variable Length Shift Register (1-16 Stages) ............................................................................... 5-41
Shadow Registers
L29C818
8-bit Serial Scan Shadow Register .......................................................................................................... 5-47

6. PERIPHERAL PRODUCTS ........................................................................................................................................ 6-1
L5380
L53C80

SCSI Bus Controller ................................................................................................................................... 6-3
SCSI Bus Controller ................................................................................................................................... 6-3

7. FIFO PRODUCTS ............................................................................................................................................................ 7-1
L8C201
L8C202
L8C203
L8C204
L8C211
L8C221
LBC231
LBC241

512 x 9, Asynchronous ............................................................................................................................... 7-3
1K x 9, Asynchronous ................................................................................................................................ 7-3
2K x 9, Asynchronous ................................................................................................................................ 7-3
4K x 9, Asynchronous ................................................................................................................................ 7-3
512 x 9, Synchronous ............................................................................................................................... 7-23
1K x 9, Synchronous ................................................................................................................................. 7-23
2K x 9, Synchronous ................................................................................................................................. 7-23
4K x 9, Synchronous ................................................................................................................................. 7-23

8. QUALITY AND RELIABILITY ................................................................................................................................ 8-1
9. TECHNOLOGY AND DESIGN FEATURES .................................................................................................... 9-1
Latchup and ESD Protection ........................................................................................................................................... 9-3
Power Dissipation in LOGIC Devices Products ........................................................................................................... 9-7

10. PACKAGE INFORMATION ................................................................................................................................... 10-1
LOGIC Devices/MIL-STD-1835 Package Code Cross-Reference ............................................................................ 10-3
Thermal Considerations ................................................................................................................................................ 10-5
Package Marking Guide ................................................................................................................................................ 10-7
Mechanical Drawings .................................................................................................................................................... 10-9

11. PRODUCT LISTING ................................................................................................................................................... 11-1
12. SALES OFFICES ............................................................................................................................................................. 12-1

vi

Numeric Table of Contents
LlOCll
LlOC23
L21Cll
L29C520
L29C521
L29C525
L29C818
L4C381
L5380
L53C80
L8C201
L8C202
L8C203
L8C204
L8C2ll
L8C221
L8C231
L8C241
LF2242
LF2246
LF2247
LF2249
LF2250
LF2272
LF43168
LF43881
LF43891
LF48212
LF48410
LF48908
LF9501
LF9502
LMA1009
LMA1010
LMA2009
LMA2010
LMS12
LMU08
LMU1l2
LMU12
LMU16
LMU18
LMU216
LMU217
LMU8U

4/8-bit Variable Length Shift Register (3-18 Stages) ............................................................................................ 5-35
64 x 1 Digital Correlator ........................................................................................................................................... 3-33
8-bit Variable Length Shift Register (1-16 Stages) ................................................................................................ 5-41
4 x 8-bit Multilevel Pipeline Register (1-4 Stages) .................................................................................................. 5-3
4 x 8-bit Multilevel Pipeline Register (1-4 Stages) .................................................................................................. 5-3
16 x 8-bit Dua18-Deep Pipeline Register (1-16 Stages) ........................................................................................ 5-27
8-bit Serial Scan Shadow Register ........................................................................................................................... 5-47
16-bit Cascadable ALU ............................................................................................................................................... 3-3
SCSI Bus Controller ..................................................................................................................................................... 6-3
SCSI Bus Controller ..................................................................................................................................................... 6-3
512 x 9, Asynchronous FIFO ...................................................................................................................................... 7-3
lK x 9, Asynchronous FIFO ....................................................................................................................................... 7-3
2K x 9, Asynchronous FIFO ....................................................................................................................................... 7-3
4K x 9, Asynchronous FIFO ....................................................................................................................................... 7-3
512 x 9, Synchronous FIFO ....................................................................................................................................... 7-23
1K x 9, Synchronous FIFO ........................................................................................................................................ 7-23
2K x 9, Synchronous FIFO ........................................................................................................................................ 7-23
4K x 9, Synchronous FIFO ........................................................................................................................................ 7-23
12/16-bit Half-Band Digital Filter ............................................................................................................................ 2-3
11 x 10-bit Image Filter ............................................................................................................................................. 2-11
11 x 10-bit Image Filter with Coefficient RAM ..................................................................................................... 2-19
12 x 12-bit Digital Mixer ........................................................................................................................................... 2-29
12 x 10-bit Matrix Multiplier .................................................................................................................................... 2-37
Colorspace Converter /Corrector (3 x 12-bits) ...................................................................................................... 2-53
Dual 8-Tap FIR Filter ................................................................................................................................................ 2-63
8 x 8-bit Digital Filter ................................................................................................................................................ 2-79
9 x 9-bit Digital Filter ................................................................................................................................................ 2-91
Alpha Mixer ............................................................................................................................................................. 2-103
1024 x 24-bit Video Histrogrammer ..................................................................................................................... 2-113
Two Dimensional Convolver ................................................................................................................................. 2-129
1K Programmable Line Buffer ............................................................................................................................... 2-145
2K Programmable Line Buffer ............................................................................................................................... 2-153
12 x 12-bit Multiplier-Accumulator ........................................................................................................................ 4-45
16 x 16-bit Multiplier-Accumulator ........................................................................................................................ 4-53
12 x 12-bit Multiplier-Accumulator, Surface Mount ............................................................................................ 4-45
16 x 16-bit Multiplier-Accumulator, Surface Mount ............................................................................................ 4-53
12 x 12 + 26-bit Cascadable Multiplier-Summer, FIR .......................................................................................... 4-61
8 x 8-bit Parallel Multiplier, Signed .......................................................................................................................... 4-3
12 x 12-bit Parallel Multiplier, Reduced Pinout .................................................................................................... 4-17
12 x 12-bit Parallel Multiplier .................................................................................................................................. 4-11
16 x 16-bit Parallel Multiplier .................................................................................................................................. 4-23
16 x 16-bit Parallel Multiplier, 32 Outputs ............................................................................................................ 4-31
16 x 16-bit Parallel Multiplier, Surface Mount ...................................................................................................... 4-23
16 x 16-bit Parallel Multiplier, Microprogrammable, Surface Mount ............................................................... 4-39
8 x 8-bit Parallel Multiplier, Unsigned ..................................................................................................................... 4-3

vii

Numeric Table of Contents
LPR200
LPR201
LPR520
LPR521
LSH32
LSH33

8 x 16-bit Multilevel Pipeline Register (1-8 Stages) .............................................................................................. 5-17
7 x 16-bit Multilevel Pipeline Register (1-7 Stages) .............................................................................................. 5-17
4 x 16-bit Multilevel Pipeline Register (1-4 Stages) .............................................................................................. 5-11
4 x 16-bit Multilevel Pipeline Register (1-4 Stages) .............................................................................................. 5-11
32-bit Cascadable Barrel Shifter .............................................................................................................................. 3-15
32-bit Cascadable Barrel Shifter with Registers .................................................................................................... 3-25

viii

DEVICES INCORPORATED

Ordering Information

Video Imaging

IFHL}UIL}t;!l:S

&

Products

Reliability

II

- ---

= ===iiii== =
-~~-~

==~~:tI..,.

DEVICES INCORPORATED

=========~I
Ordering Information

•

1-1

DEVICES INCORPORATED

-

- --- --------- -------------~--DEVICES INCORPORATED

TO CONSTRUCT A VALID PART NUMBER:
In order to construct a valid LOGIC Devices part number, begin with the generic number obtained from the data sheet
header. To this number, append two or three characters from the tables below indicating the desired package code,
temperature range, and screening. Finally, append one or two digits indicating the performance grade desired. Most
devices are offered in several speed grades with the part number suffix indicating a critical path delay in nanoseconds.

FOR MORE INFORMATION ON AVAILABLE PART NUMBERS:
All products are not offered with all combinations of package styles, temperature ranges, and screening. The Ordering
Information table on the last page of each data sheet indicates explicitly all valid combinations of package, temperature,
screening, and performance codes for a given product.

L 7C108

C M B 20 L

(1)

(3)

(2)

Package Codes
Suffix

Description

C,I*

CerDIP

D,H*

Sidebraze, Hermetic DIP

G

Ceramic Pin Grid Array

J

Plastic J-Lead Chip Carrier

K, T*

Ceramic Leadless Chip Carrier

M

CerFlat

P,N*

Plastic DIP

Q

Plastic Quad Flatpack

W

Plastic SOJ (J-Lead)

y

Ceramic SOJ (J-Lead)

(4)

(5)

(6)

(7)

Temperature Range
Suffix

Description
Commercial
O°C to +70°C

C

I

Industrial
-40°C to +85°C

M

Military
-55°C to +125°C

Key:
(1 )
(2)
(3)
(4)
(5)
(6)
(7)

Prefix, LOGIC Devices Inc.
Device number
Package code
Temperature range
Screening
Performance/speed grade
Low power designation

Screening
Suffix
No
Designator
B

Description

Commercial Flow
MIL-STD-883
Class B Compliant

* Some devices are available in packages of
two widths. For devices available in a single
width, C, D, K, and P are used.

======================= Ordering Information
1-3

1

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----~
------------ - --~---

.-

DEVICES INCORPORATED

- -- --------~--------- - --

-

--.~---...

DEVICES INCORPORATED

Video Imaging Products

•

------------- -- ----...--. -.. -.-.-..-. -.-. -..-.

-~---

DEVICES INCORPORATED

Video Imaging Products

VIDEO IMAGING PRODUCTS ....................................................................................................................................... 2-1
LF2242
LF2246
LF2247
LF2249
LF2250
LF2272
LF43168
LF43881
LF43891
LF48212
LF48410
LF48908
LF9501
LF9502

12/16-bit Half-Band Digital Filter ..................................................................................................................... 2-3
11 x 10-bit Image Filter ...................................................................................................................................... 2-11 •
11 x lO-bit Image Filter with Coefficient RAM .............................................................................................. 2-19
12 x 12-bit Digital Mixer .................................................................................................................................... 2-29
12 x lO-bit Matrix Multiplier ............................................................................................................................ 2-37
Colorspace Converter /Corrector (3 x 12-bits) ............................................................................................... 2-53
Dual 8-Tap FIR Filter ......................................................................................................................................... 2-63
8 x 8-bit Digital Filter ......................................................................................................................................... 2-79
9 x 9-bit Digital Filter ......................................................................................................................................... 2-91
Alpha Mixer ...................................................................................................................................................... 2-103
1024 x 24-bit Video Histogrammer ................................................................................................................ 2-113
Two Dimensional Convolver ......................................................................................................................... 2-129
1K Programmable Line Buffer ....................................................................................................................... 2-145
2K Programmable Line Buffer ....................................................................................................................... 2-153

2·1

DEVICES INCORPORATED

=fi==-=~

=~~=~

DEVICES INCORPORATED

o 40 MHz Clock Rate
o Passband (0 to 0.22/5)
Ripple: ±0.02 dB
Stopband (0.28/5 to 0.5/5)
Rejection: 59.4 dB
o User-Selectable 2:1 Decimation or
1:2 Interpolation
o 12-bit Two's Complement Input
and 16-bit Output with UserSelectable Rounding to 9 through
16 Bits
o User-Selectable Two's Complement
or Inverted Offset Binary Output
Formats
o Three-State Outputs
o Replaces TRW/Raytheon TMC2242
o Package Styles Available:
• 44-pin plastic LCC, J-Lead
• 44-pin Plastic Quad Flatpack

o

LF2242
12/16-bit Half-Band Interpolatingl
Decimating Digital Filter

The LF2242 is a linear-phase, halfsample rate. Once data is clocked in,
band (low pass) interpolating/
the 55-value output response begins
decimating digital filter that, unlike
after 6 clock cycles and ends after 60 •
intricate analog filters, requires no
clock cycles. The pipeline latency
tuning. The LF2242 can also signififrom the input of an impulse response
cantly reduce the complexity of
to its corresponding output peak is 33
traditional analog anti-aliasing preclock cycles.
filters without compromising the
signal bandwidth or attenuation. This The output data may be in either
two's complement format or inverted
can be achieved by using the LF2242
offset
binary format. To avoid
as a decimating post-filter with an
truncation errors, the output data is
A/D converter and by sampling the
always internally rounded before it is
signal at twice the rate needed.
latched into the output register.
Likewise, by using the LF2242 as an
Rounding is user-selectable, and the
interpolating pre-filter with a
output data can be rounded from 16
D/ A converter, the corresponding
bit values down to 9 bit values.
analog reconstruction post-filter
circuitry can be simplified.
DC gain of the LF2242 is 1.0015
(0.0126 dB) in pass-through and
The coefficients of the LF2242 are
fixed, and the only user programming decimate modes and 0.5007 (-3.004
dB) in interpolate mode. Passband
required is the selection of the mode
ripple does not exceed ±O.02 dB from
(interpolate, decimate, or passo
to 0.22/5 with stopband attenuation
through) and rounding. The asyngreater than 59.4 dB from 0.28/5 to
chronous three-state output enable
control simplifies interfacing to a bus. 0.5/5 (Nyquist frequency). The
response of the filter is -6 dB at
Data can be input into the LF2242 at a 0.25/5' Full compliance with CCIR
Recommendation 601 (-12 dB at
rate of up to 40 million samples per
second. Within the 40 MHz I/O limit, 0.25/5) can be achieved by cascading
the output sample rate can be onetwo devices serially.
half, equal to, or two times the input

~16,

~

~S015-{)

ClK ----~~ TO All REGISTERS
INT DEC SYNC

=====================Video Imaging Products
2-3

OB/27/95-LOS.2242-C

LF2242
DEVICES INCORPORATED

12116-bit Half-Band Interpolating!
Decimating Digital Filter
Controls
INT - Interpolation Control

0

'\

-10

\

-20

iii'

-30

z

-40

"

-50

:24(

When INT is LOW and DEC is HIGH
(Table 1), the device internally forces
every other incoming data sample to
zero. This effectively halves the input
data rate and the output amplitude.

DEC - Decimation Control

~O

1U1f~

-70

il\Anl

I' I

UH

I

-80

o

0.1fs

0.2fs

0.3fs

When DEC is LOW and !NT is HIGH
(Table 1), the output register is strobed
on every other rising edge of CLK
(driven at half the clock rate), decimating the output data stream.

O.4fs

0.5fS

FREQUENCY (NORMALIZED)

SIGNAL DEFINITIONS
Power

Inputs
SIl1-{) - Data Input

12-bit two's complement data input
port. Data is latched into the register on
+5 V power supply. All pins must be the rising edge of CLK. The LSB is Slo
(Figure 2).
connected.

VccandGND

Clock

Outputs

CLK - Master Clock

5015-0 Data Output

·Input and output registers run at full
clock rate

The rising edge of CLK strobes all regis- The current 16-bit result is available on
ters. All timing specifications are refer- the 5015-0 outputs. The LF2242' s limiter
ensures that a valid full-scale (7FFF
enced to the rising edge of CLK.
positive or 8000 negative) output will be
generated in the event of an internal
SYNC - Synchronization Control
overflow. The LSB is SOo (Figure 2).
Incoming data is synchronized by holding SYNC HIGH on CLKN, and then by
bringing SYNC LOW on CLKN+1 with
the first word of input data. SYNC is
held LOW until resynchronization is
desired, or it can be toggled at half the
clock rate. For interpolation (INT =
LOW), input data should be presented
at the first rising edge of CLK for which
SYNC is LOW and then at every alternate rising edge of CLK thereafter.
SYNC is inactive if DEC and INT are
equal (pass-through mode).

====================Video Imaging Products
2-4

06/27/95-LDS.2242·C

- - _--...-.
.. _- .. --- -.......-------

=~~=~

LF2242

.-....-......

DEVICES INCORPORATED

12116-bit Half-Band Interpolatingl
Decimating Digital Filter
RND2-0 - Rounding Control
The rounding control inputs set the position of the effective LSB of the output
data by adding a rounding bit to the
internal bit position that is one below
that specified by RND2-0. All bits below
the effective LSB position are subse- •
quently zeroed (Table 2).

Two's Complement Input Format
111109 S ' i t 3 2 1 0 1
_20 2-1 2--2 2-3
2-8 2-9 2-1°2-11
(Sign)

Two's Complement Output Format (TCO = 1, Non-interpolate)
1 15 14 13 12 ' i t 3 2 1 01
_20 2-1 2--2 2-3
Z-12 2-132-142-15

TCO - Two's Complement Format
Control

(Sign)

The TCO input determines the format of
the output data. When TCO is HIGH,
the output data is presented in two's
complement format. When TCO is
LOW, the data is in inverted offset binary format (all output bits are inverted
except the MSB - the MSB is unchanged).
'

Two's Complement Output Format (TCO = 1, Interpolate)
1 15 14 13 12 ' i t 3

2

1

01

(Sign)

Inverted Offset Binary Output Format (TCO
1 15 14 13 12 ' i t 3

=0, Non-Interpolate)

2

~

0 1

OE - Output Enable

(Sign)

Inverted Offset Binary Output Format (TCO
1 15 14 13 12 ' i t 3

=0, Interpolate)

2

When the OE signal is LOW, the current
data in the output register is available
on the 5015-0 pins. When OE is HIGH,
the outputs are in a high-impedance
state.

01

(Sign)

'R'

000

X

X

X

X

X

X

X

X

X

X

X

X

R

001

X

X

X

X

X

X

X

X

X

X

X

R

0

010

X

X

X

X

X

X

X

X

X

X

R

0

0

011

X

X

X

X

X

X

X

X

X

R

0

0

0

100

X

X

X

X

X

X

X

X

R

0

0

0

0

101

X

X

X

X

X

X

X

R

0

0

0

0

0

110

X

X

X

X

X

X

R

0

0

0

0

0

0

111

X

X

X

X

X

R

0

0

0

0

0

0

0

indicates the half-LSB rounded bit (effective LSB position)

====================Video Imaging Products
2-5

06/27/9s-LDS,2242·C

LF2242
DEVICES INCORPORATED

12116-bit Half-Band Interpolating/
Decimating Digital Filter

Storage temperature ............................................................................................................ -65°C to +150°C
Operating ambient temperature ............................................................................................ -55°C to +125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V
Signal applied to high impedance output ....................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs ........................................................... ........ ........ ................................... 25 mA
Latchup current ................................................................................................................................ > 400 mA

Temperature Range (Ambient)

Mode

Active Operation, Commercial

Symbol

O°C to +70°C

Parameter

Test Condition

VOH

Output High Voltage

Vee

VOL

Output Low Voltage

Vee =Min., IOL =4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

Ground

loz

Output Leakage Current

lee1

Supply Voltage

4.75 V ~ Vee ~ 5.25 V

Min

=Min., IOH =-2.0 mA

Typ

Max

2.4

Unit

V
0.4

V

2.0

Vee

V

0.0

0.8

V

±10

!lA

(Note 12)

±40

!lA

Vee Current, Dynamic

(Notes 5, 6)

140

mA

lee2

Vee Current, Quiescent

(Note 7)

10

mA

CIN

Input Capacitance

TA =25°C, f

=1 MHz

10

pF

COUT

Output Capacitance

TA =25°C, f

=1 MHz

10

pF

~

VIN ~ Vee (Note 12)

====================Video Imaging Products
2-6

06/27/95-LDS.2242-C

- --------- -..-..--------- -

--....--..-.

LF2242

-

-~---

DEVICES INCORPORATED

12/16-bit Half-Band Interpolatingl
Decimating Digital Filter

..

.'",'

"

."',

LF224225

33
Symbol

Parameter

Min

Max

Min

tCYC

Cycle Time

33

25

tpw

Clock Pulse Width

10

10

ts

Input Setup Time

10

8

tH

Input Hold Time

0

0

Max

I------t-'--------------+--------+--+-----+------l •

tD

Output Delay

20

16

tDIS

Three-State Output Disable Delay (Note 11)

15

15

tENA

Three-State Output Enable Delay (Note 11)

15

15

2

10

9

8

7

3

ClK

SYNC

N+1

5111-0

5015-0

=:::x

N+2

X
tDIS

5E

r"O::~

f(N)

X

f(N+1)

X

f(N+2)

x::=

tENA

===================== Video Imaging Products
2-7

06/27/95-LDS,2242-C

........ ..-.-.----- -......
-----........ _---

----~~-~

LF2242

DEVICES INCORPORATED

12116-bit Half-Band Interpolating!
Decimating Digital Filter

-~---

2

7

3

8

10

9

ClK

SYNC

N+2

SI11-o

S015-o

==::x

x
IDIS

OE

2

Fe=
~

X

8

7

3

ClK

YN)

ffN+1)

X

>e:::

f(N+2)

lENA

9

10

•••

SYNC

N+l

Slll-0

SOl5-0

==::x

N+2

x
IDfS

OE

rr:~

fIN)

X

f{N+2)

lENA

==================== Video Imaging Products
2-8

06/27/95-LDS_2242-C

LF2242
DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

12116-bit Half-Band Interpolatingl
Decimating Digital Filter

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tOISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 m V
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

VCC

do

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

}

,"

a. A 0.1 J.IF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
anteed as specified.
ground and tester common.
5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated by: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.
where
N
C
V
F

4

= total number of device outputs
= capacitive load per output
= supply voltage
= clock frequency

t - -.......--oOUTPUT

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 20 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

"+
01

-==~~~!!J!!!l~~~

TRISTATE
OUTPUTS _

=====================Video Imaging Products
2-9

06/27/95-LDS.2242-C

_- .......
- _----

5:~YE~

LF2242

DEVICES INCORPORATED

12116-bit Half-Band Interpolating!
Decimating Digital Filter

44-pin

44-pin

~;!~

°

010

~;!~ W 0lu ~lI:::Cl~
ocncncnOI--Cl_cnU(!)cn
0 I U W l!z >- ...J Z .:::::

°

~lI:::Cl~

o 0 0 IW W l!z >- ...J z -=
(/)(/)(/)Ol-Cl_(/)OC)(/)
6 5 4 3 2
8012
8011

Vcc

81s

S012
S011
SOlO
S09
SOs

817

GND

8010

8110

809

819

80s

Top
View

GND
Vcc

vcc

81s

807

815

80s

814

S07
SOs
SOs
S04

813

805
804

17
29
18 192021 22232425262728

Vcc

~

1
2
3
4
5
6
7
8
9
10
11

~~~;5f~~t;;~~~

GND
vcc
Sl10
SI9
Sis
SI7
Sis
Sis
SI4
SI3

Top
View

vcc
C\I('I')vLOCO ...... COO'lO
__ C\I
________________
C\IC\IC\I

M
N
0
N
0
0
N C
OOOOClClCl(j)(j)(j)Z
(/)(/)(/)(/)~~~
C)
~

•

GND

•

~

880
88 i58.E.::::: £!!Cl
cncncncnZZzcncncnz
a: a: a:

(!)

Plastic J-Lead Chip Carrier

(J1)
33 ns
25 ns

LF2242QC33
LF2242QC25

LF2242JC33
LF2242JC25

==================== Video Imaging Products
2-10

06/27/95-LDS.2242-C

-- -- -- ------=:.....

=-:......=:...::

LF2246

-

-~---

11

DEVICES INCORPORATED

o 66 MHz Data and Coefficient Input
and Computation Rate
o Four 11 x lO-bit Multipliers with
Individual Data and Coefficient
Inputs and a 2S-bit Accumulator
o User-Selectable Fractional or
Integer Two's Complement Data
Formats
o Fully Registered, Pipelined Architecture
o Input and Output Data Registers,
with User-Configurable Enables
o TIuee-State Outputs
o Fully TTL Compatible
o Ideally Suited for Image Processing
and Filtering Applications
o Replaces TRW IRaytheon TMC2246
o Package Styles Available:
• 120-pin Pin Grid Array
• 120-pin Plastic Quad Flatpack

X

10-bit Image Fi Iter

outputs, and controls are registered
The LF2246 consists of an array of
four 11 x lO-bit registered multipliers on the rising edge of clock, except for
followed by a summer and a 2S-bit
OEN. The LF2246 operates at a clock
accumulator. All multiplier inputs
rate of 66 MHz over the full tempera- . .
are user accessible and can be upture and supply voltage ranges.
dated every clock cycle with either
The LF2246 is applicable for performfractional or integer two's compleing pixel interpolation in image
ment data. The pipelined architecture manipulation and filtering applicahas fully registered input and output
tions. The LF2246 can perform a
ports and an asynchronous three-state bilinear interpolation of an image (4output enable control to simplify the
pixel kernels) at real-time video rates
design of complex systems. The
when used with an image resampling
pipeline latency for all inputs is five
sequencer. Larger kernels or more
clock cycles.
complex functions can be realized by
Storage for mixing and filtering
utilizing multiple devices.
coefficients can be accomplished by
Unrestricted access to all data and
holding the data or coefficient inputs coefficient input ports provides the
over multiple clock cycles. A 2S-bit
LF2246 with considerable flexibility in
accumulator path allows cumulative
applications such as digital filters,
word growth which may be internally adaptive FIR filters, mixers, and other
rounded to 16 bits. Output data is
similar systems requiring high-speed
updated every clock cycle and may be processing.
held under user control. All inputs,

ENSEl ---1f-.,-+--+--+~-l--+--+-",,---t--I----+--,

ACC

FSEl

OEN ---------------~
ClK - - - -__ TO ALL REGISTERS

===================== Video Imaging Products
2·11

06/27/95-lDS.2246·E

.. - - -= -......... . .-------.....-.

-~~=~

~

-~--

.......-

LF2246

DEVICES INCORPORATED

11 x 10-bit Image Filter

Data

Coefficient

- - - - Fractional Two's Complement (FSEL = 0) - - - 19

8

7

_20 2 1 2-2

lit

2

1

0 1

110 9

2-7 2-8 2-l1

8

_21 20 2 1

(Sign)

lit

2

0

2-7 2-8 2-9

(Sign)

Integer Two's Complement (FSEL = 1) - - - 19

8

7

_29 28 27

lit

2

1

0 1

110 9

8

_210 29 28

22 21 20

(Sign)

lit

2

0

22 21 20

(Sign)

- - - Fractional Two's Complement (FSEL = 0) - - -

Integer Two's Complement (FSEL = 1) - - - -

115

14 13 12 11 10 9

8

7

6

5

4

3

2

o

x=

"Don't Care"
'N' = 1, 2, 3, or 4

OCEN - Clock Enable
When OCEN is LOW, data in the premux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register is
held preventing the output register's
contents from changing (if FSEL does
not change). Accumulation continues
internally as long as ACC is HIGH,
despite the state of OCEN.

FSEL - Format Select

SIGNAL DEFINITIONS

Power

Controls
ENB1-ENB4 - Input Enable

The ENBN (N = 1, 2, 3, or 4) input allows
either or both the DN and CN registers to
be updated on each clock cycle. When
ENBN is LOW, registers DN and CN are
both
strobed by the next rising edge of
Clock
CLK. When ENBN is HIGH and EN5EL
CLK - Master Clock
is LOW, register DN is strobed while
The rising edge of CLK strobes all en- register CN is held. If both ENBN and
abled registers. All timing specifica- ENSEL are HIGH, register DN is held,
tions are referenced to the rising edge of and register CN is strobed (Table 1).
CLK.
ENSEL - Enable Select
Inputs
The ENSEL input in conjunction with
0194-049-0 - Oata Input
the individual input enables ENB1D1-D4 are lO-bit data input registers. ENB4 determines whether the data or
the coefficient input registers will be
The L5B is DNO (Figure 1a).
held on the next rising edge of CLK
C11(J.4-C410-0 - Coefficient Input
(Table 1).
C1-C4 are ll-bit coefficient input regisOEN
- Output Enable
ters. The L5B is CNO (Figure 1a).
When the OEN signal is LOW, the curOutputs
rent data in the output register is available on the S15-O pins. When OEN is
Sl5-0 - Data Output
The current 16-bit result is available on HIGH, the outputs are in a high-impedance state.
the 515-0 outputs (Figure 1b).

VccandGNO
+5 V power supply. All pins must be
connected.

When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two's
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumulator result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two's
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.

ACC - Accumulator Control
The ACC input determines whether internal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. If FSEL is also LOW,
one-half LSB rounding to 16 bits is performed on the result. This allows summations without propagating roundoff
errors. WhenACC is HIGH, the emerging product is added to the sum of the
previous products, without additional
rounding.

====================Video Imaging Products
2-12

06/27/95-LDS.2246-E

'-D~I~

LF2246

-~---

DEVICES INCORPORATED

11 x 10-bit Image Filter

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V

•

Signal applied to high impedance output ....................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

Parameter

Test Condition

VOH

Output High Voltage

Vee = Min., IOH = -2.0 mA

VOL

Output Low Voltage

Vee = Min., IOL = 4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

!Ix

Input Current

loz

Supply Voltage
4.75 V:,; Vee:,; 5.25 V
4.50 V :,; Vee:,; 5.50 V

Min

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground:,; VIN:'; Vee (Note 12)

±10

J.lA

Output Leakage Current

(Note 12)

±40

J.lA

leel

Vee Current, Dynamic

(Notes 5, 6)

100

mA

lee2

Vee Current, Quiescent

(Note 7)

6

mA

CIN

Input Capacitance

TA = 25°C, f = 1 MHz

10

pF

COUT

Output Capacitance

TA = 25°C, f = 1 MHz

10

pF

====================Video Imaging Products
2·13

06127195-LDS.2246·E

.......
--_--- -- ..-----_-----.

----~
--.-..
- - --

LF2246

DEVICES INCORPORATED

11 x 10-bit Image Filter

3

4

5

6

ClK

019-0- 049-0

C110-o -

C410·0

CONTROLS
(Except OEN)

OEN

tD~815-0

X

X

SN-l

SN

>Q;L

Video Imaging Products
06/27/95-LDS_2246-E

2-14
-----

- ,...
............... _=

::f"!!=~

=-=-=-==~

LF2246

DEVICES INCORPORATED

11 x 10-bit Image Filter

-~---

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vec

d,
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

~r

a. A 0.11JF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actualtest conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
anteed as specified.
ground and tester common.
5. Supply current for a given applica- b. Ground and Vee supply planes
tioncanbeaccuratelyapproximatedby: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.
where
N
C
V
F

4

= total number of device outputs
= capacitive load per output
= supply voltage
= clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

t--...,..--oOUTPUT

n+

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 30 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

====================Video Imaging Products
2·15

06/27/95-LDS.2246·E

•

-.-

---

Lu~aE!

LF2246

-~---

DEVICES INCORPORATED

11 x 10-bit Image Filter

120-pin

2

A

, ... ,
,_I

...

I_I

3

4

5

7

, ... , ... , ... , ... ,

I_I

1.....1

I_I

ENSEL ENB2 ENB3 047

B

6
1.....1

...

1.....1

8

...

...

...

F
G

I_I

...

...

I_I

OEN ClK ENBl 04s
1.....1

13

1.....1

...

.

...

...

I_I

I_I

I_I

511

512

GNO

, ..

59

510

Vee
, ...

1.....1

1.....1

1.....1

,

...

J

1.....1

1.....1

1.....1

1.....1

C4s

C41

C31

...

...

1.....1

I_I

1.....1

1.....1

C38 C310

030

1.....1

1.....1

1.....1

035

036

034

1.....1

I_I

1.....1

, .. , .. , ..

Top View
Through Package
(Le., Component Side Pinout)

1.....1

.
,.

, 032
, . 033
,.
I_I
I_I
I_I

031

GNO
1.....1

54

...

1.....1

, ... C37
, ... C39
, ..

C34

,56. ,55.. Vee
, ..
1.....1 1.....1
,

1.....1

, .. C33
, .. C36
, ..

1.....1

,57... ,58... GNO
, ...
I_I

1.....1

Vee

KEY

, . I_I
,.
, .. I_I

I_I

1.....1

I_I

, ... 514
, .. OCEN
, ..

I_I

,

...

,

...

, ... 038
, 037
,
...

...

1.....1

1.....1

53

GNO

029

039

I_I

, ...

027

1.....1

1.....1

1.....1

1.....1

1.....1

1.....1

1.....1

...

...

,

...

, .. , . , .

K

I_I

L

1.....1

1.....1

1.....1

I_I

1.....1

50

017

015

012

C19 GNO

, ... 026
, ...
,52.. ,51.. 018
, .. , ... , ... , .. , ... , ... , ... , ... 023
, .. 02B
I_I

1.....1

I_I

Vee

C20

1.....1

1.....1

, 024
, 025
, I_I
, . , .. , .. C24
, .. 020
, ...
, .. , .. , .. I_I
, .. I_I
, .. C28
1.....1 1.....1 1.....1 I_I
1.....1 1.....1 I_I
1.....1 1.....1 I_I
...

, 011
, Cl10
, C17
, C13
, Cl0
, . 021
, .. 022
, .. C15
, .. C22
, .. C25
, .. C29
, ... 014
, ...
,_I
,_I
1.....1 1.....1 1.....1 1.....1 1.....1 1.....1 1.....1

019

N

1.....1

044 GNO

I_I

, ... , ... , .. I, ..I

H

M

12

, C44
, ... C42
, ... C30
, ... C3s
, ...
, ... , ... , .. I_I
, . 046
, .. 040
, .. C49
, . C47
, .. 043
I_I
I_I
I_I

I_I

513

E

11

, 041
, C410
, C48
, C4s
, C43
, C40
, C32
,
, I_I
, ... , , ... 045
, ... 042
I_I
1.....1 1.....1 1.....1 I_I
1.....1 I_I
1.....1 1.....1 1.....1 1.....1 1.....1
515

D

10

, ... , ... , ... , ... , ... ,_I
, ...
1.....1 I_I

1.....1

ACC F5El ENB4 049

C

9

016

...

...

I_I

I_I

013

010

...

...

C18

C16

C14

...

C12

Cl1

33 ns

LF2246GC33

25 ns

LF2246GC25

15 ns

LF2246GC15

33 ns

LF2246GM33

25 ns

LF2246GM25

33 ns

LF2246GMB33

25 ns

LF2246GMB25

C21

C23

I_I

I_I

C26

C27 C210

==================== Video Imaging Products
2·16

06/27/95-LDS.2246·E

- -..---- -...-.-...-..

~ -~--

~~=-==:...-~---

LF2246

DEVICES INCORPORATED

11 x 10-bit Image Filter

120-pin

ClK
F8El
ACC
OCEN
OEN
815
814

GNO
813

812
811

vee
810

8.
88

GNO
87
86

Top

View

85

Vee
84
83
82

GNO
81

80
019
018
017
010

33 ns
25 ns
15 ns

..

C32
C33
C34
C35
C36
C37
C36
C39
C310
030
031
032
033
034
035
030
037
038
GNO
039
029
028
027
026
02.
024
023
022
021
020

LF2246QC33
LF2246QC25
LF2246QC15

====================Video Imaging Products
2-17

OS/27/95-l08.224S-E

--

.....--.

--......

-~

LU£:=E..;

-~---

DEVICES INCORPORATED

- -- ---- =-u:..:=~
---

LF 2247

-'""-""

Image Filter with Coefficient RAM

DEVICES INCORPORATED

o
o
o
o
o

66 MHz Data Input and Computation Rate
Four 11 x lO-bit Multipliers with
Individual Data and Coefficient
Inputs and a 2S-bit Accumulator
Four 32 x ll-bit Serially Loadable
Coefficient Registers
Fractional or Integer Two's
Complement Operands
Package Styles Available:
• 84-pin Plastic LCC, J-Lead
• lOO-pin Plastic Quad Flatpack
• 84-pin Pin Grid Array

01!Hl

ENB1

The LF2247 consists of an array of four
11 x lO-bit registered multipliers
followed by a summer and a 2S-bit
accumulator. The LF2247 provides a
coefficient register file containing four
32 x ll-bit registers which are capable
of storing 32 different sets of filter
coefficients for the multiplier array.
All multiplier data inputs are user
accessible and can be updated every
clock cycle with either fractional or
integer two's complement data. The
pipelined architecture has fully
registered input and output ports and

02!Hl

03,.()

ENB2

an asynchronous three-state output
enable control to simplify the design
of complex systems. The pipeline
latency for all inputs is five clock
cycles.
A 2S-bit accumulator path allows
cumulative word growth which may
be internally rounded to 16 bits.
Output data is updated every clock
cycle and may be held under user
control. The data inputs/outputs and
control inputs are registered on the
rising edge of eLK. The Serial Data In
signal, SDIN, is registered on the

ENB,

04,.()

ENB4

ACC----~

25

b - - - - - - - - OCEN

FSEl-----.!

OEN-----------------~

ClK ----.~ TO All REGISTERS
(EXCEPT COEFFICIENT REGISTERS)

S15.()

===================== Video Imaging Products
2·19

06/27/95-LDS.2247·B

-

.-

---

i:g~l~

LF2247

DEVICES INCORPORATED

Image Filter with Coefficient RAM
Inputs

D19-0 - D49-0 - Data Input
Data

Coefficient

- - - - Fractional Two's Complement (FSEL
9 8 7 ~ 2 1 0
2-7 2-8 2-9
_2°2-1 2-2

I

=0) - - - -

110 9 8 ~ 2 1 0
_21 20 2-1
2-7 ~ ~

A4-0 - Row Address

(Sign)

(Sign)

Integer Two's Complement (FSEL = 1) - - - 19 8 7
_2 9 2 8 27

~

2 1 0
22 21 20

I

(Sign)

110

9 8
_210 2 9 2 8

~

2
0
22 21 2°

(Sign)

- - - Fractional Two's Complement (FSEL = 0) - - 115 14 13 12 11 10 9 8 7 6 5 4 3 2
0
_26 2 5 24 2 3 22 21 20 2-1 2-2 ~ 2-4 ~ ~ 2-7 2-8 2-9
(Sign)

----Integer Two's Complement (FSEL = 1) - - - 115 14 13 12 11 10 9 8 7 6 5 4 3 2
0
_2 15 2 14 2 13 212 211 210 2 9 2 8 27 2 6 2 5 24 2 3 22 21 20
(Sign)

rising edge of SCLK. The LF2247
operates at a clock rate of 66 MHz
over the full temperature and supply
voltage ranges.

SIGNAL DEFINITIONS

The LF2247 is applicable for performing pixel interpolation in image
manipulation and filtering applications. The LF2247 can perform a
bilinear interpolation of an image (4pixel kernels) at real-time video rates
when used with an image resampling
sequencer. Larger kernels or more
complex functions can be realized by
utilizing multiple devices.

+5 V power supply. All pins must be
connected.

Unrestricted access to all data ports
and an addressable coefficient register
file provides the LF2247 with considerable flexibility in applications such
as digital filters, adaptive FIR filters,
mixers, and other similar systems
requiring high-speed processing.

D1-D4 are the lO-bit registered data
input ports. Data is latched on the
rising edge of CLK.

Power

VccandGND

Clocks

A4-Q determines which row of data in
the coefficient register file is used to
feed data to the multiplier array. A4-0
is latched on the rising edge of CLK.
When a new row address is loaded
into the row address register, data
from the register file will be latched
into the multiplier input registers on
the next rising edge of CLK.

SDIN - Serial Data Input
SDIN is used to serially load data into
the coefficient registers. Data present
on SDIN is shifted into the coefficient
register file on the rising edge of SCLK
when SEN is LOW. The ll-bit coefficients are loaded into the coefficient
register file in 16-bit words as shown
in Figure 2. The five most significant
bits of the first 16-bit word determine
which row the data is written to in the
coefficient registers. Note that the five
most significant bits of the remaining
three 16-bit words are ignored. After
all four 16-bit words are shifted into
the register file, the lower eleven bits
of each word (the coefficient data) are
stored into the coefficient registers.
Outputs

CLK - Master Clock
The rising edge of CLK strobes all
enabled registers except for the
coefficient registers.

SCLK - Serial Clock
The rising edge of SCLK shifts data
into and through the coefficient
register file when it is enabled for
serial data shifting.

S15-0 - Data Output
S15-0 is the 16-bit registered data
output port.
Controls

ENB1-ENB4 - Data Input Enables
The ENBN (N = 1,2, 3, or 4) inputs
allow the DN registers to be updated
on each clock cycle. When ENBN is
LOW, data on DN9-0 is latched into

==================== Video Imaging Products
2-20

06/27/95-LDS.2247·8

- --...--.-........ ..-.---......----- -

----~----~

LF2247

DEVICES INCORPORATED

Image Filter with Coefficient RAM

~

-~---

the ON register on the rising edge of
CLK. When ENBN is HIGH, data on
ON9-0 is not latched into the ON
register and the register contents will
not be changed.

OEN - Output Enable
When OEN is LOW, S15-O is enabled
for output. When OEN is HIGH, S15-0
is placed in a high-impedance state.

OCEN - Clock Enable

SECOND 16-BIT WORD

A

&

1

1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132
0 0 0 1 0 1 1 1 1 1 1 0 1 1 OOXXXXXOOOl 0 0 0 1 1 00,

.

.

ROW
ADDRESS

ENBA - Row Address Input Enable
The ENBA input allows the row
address register to be updated on each
clock cycle. When ENBA is LOW,
data on A4-O is latched into the row
address register on the rising edge of
CLK. When ENBA is HIGH, data on
A4-O is not latched into the row
address register and the register
contents will not be changed.

FIRST 16-BIT WORD
I

DATA FOR
COEFFICIENT REGISTER 4

.

DON'T
CARES

.

DATA FOR
COEFFICIENT REGISTER 3

THIRD 16-BIT WORD

FOURTH 16-BIT WORD

•

A

,

1

~~~~~~$~~~~#~~Q~~~~~roM~~~~~OO~~~M

...

XXXXXOOll0l00l00XXXXXllllll00l00
~'

DON'T
CARES

DATA FOR
COEFFICIENT REGISTER 2

DON'T
CARES

DATA FOR
COEFFICIENT REGISTER 1

'

SHOWN IS SERIAL DATA STREAM TO LOAD ROW ADDRESS 2 WITH:
COEFFICIENT REGISTER 1 =7E4
COEFFICIENT REGISTER 2 = 1A4
COEFFICIENT REGISTER 3 = 08C
COEFFICIENT REGISTER 4 = 7EC

formed if the accumulator control
input ACC is LOW. When FSEL is
HIGH, the data input is assumed to be
in integer two's complement format,
and the lower 16 bits of the accumulator are presented at the output. No
rounding is performed when FSEL is
HIGH.

When OCEN is LOW, data in the premux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register
is held preventing the output
ACC - Accumulator Control
register's contents from changing (if
FSEL does not change). Accumulation The ACC input determines whether
continues internally as long as ACC is internal accumulation is performed on
HIGH, despite the state of OCEN.
the data input during the current
clock cycle. If ACC is LOW, no
FSEL - Format Select
accumulation is performed, the prior
accumulated sum is cleared, and the
When FSEL is LOW, the data input
current sum of products is output. If
during the current clock cycle is
FSEL is also LOW, one-half LSB
assumed to be in fractional two's
rounding to 16 bits is performed on
complement format, and the upper 16
the result. When ACC is HIGH, the
bits of the accumulator are presented
emerging product is added to the sum
at the output. Rounding of the
of the previous products, without
accumulator result to 16 bits is peradditional rounding.

SEN - Serial Input Enable
The SEN input enables the shifting of
serial data through the registers in the
coefficient register file. When SEN is
LOW, serial data on SOIN is shifted
into the coefficient register file on the
rising edge of SCLK. SEN must
remain LOW until all four coefficients
have been clocked in. SEN does not
need to be pulsed between consecutive data sets. It can remain LOW
while the entire register file is loaded
by a constant bit stream. When SEN is
HIGH, data can not be shifted into the
register file and the register file's
contents will not be changed. When
enabling the coefficient register file for
serial data input, the LF2247 requires
a HIGH to LOW transition of SEN in
order to function properly. Therefore,
SEN needs to be set HIGH immediately after power up to ensure proper
operation of the serial input circuitry.

====================Video Imaging Products
2-21

06/27/95-LDS.2247-8

•

LF2247
DEVICES INCORPORATED

Image Filter with Coefficient RAM

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ........................ .................................................. .... -0.5 V to Vee + 0.5 V
Signal applied to high impedance output................ ...................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial
Active Operation, Military

Supply Voltage

O°C to +70°C

4.75 V ::; Vee::; 5.25 V

-55°C to +125°C

4.50 V ::; Vee::; 5.50 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., IOH = -2.0 mA

2.4

VoL

Output Low Voltage

Vee = Min., IOL = 4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Symbol

Typ

Max

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground::; VIN ::; Vee (Note 12)

±10

IIA

Output Leakage Current

Ground::; VOUT::; Vee (Note 12)

±40

IIA

lee1

Vee Current, Dynamic

(Notes 5,6)

100

mA

lee2

Vee Current, Quiescent

(Note 7)

6.0

mA

CIN

Input Capacitance

TA = 25°C, f = 1 MHz

10

pF

COUT

Output Capacitance

TA = 25°C, f = 1 MHz

10

pF

==================== Video Imaging Products
2-22

OS/27/95-LDS.2247·B

-......
..---_-..--- ..-- ------

---...-...-~

.-.......-.

LF2247

-~---

DEVICES INCORPORATED

Image Filter with Coefficient RAM

6

5

4

ClK

D19-0 - D49-0

A4-o
CONTROLS
(Except OEN)
OEN

515-0

X

a

tENAb
HIGH IMPEDANCE

tOE
SN-,

SN

X

SN+1

Video Imaging Products
2-23

06/27/95-LDS.2247-B

LF2247
DEVICES INCORPORATED

Image Filter with Coefficient RAM

63
SCLK _ _ _ _- /

SEN

SDIN

~ tss

tSH
A4

64

j'~,,"~

~------------I
>IO 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

Parameter

Test Condition

VoH

Output High Voltage

Vcc = Min., IOH = -2.0 mA

VoL

Output Low Voltage

Vcc = Min., IOL = 4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Supply Voltage
4.75 V:5 Vee:5 5.25 V
4.50 V :5 Vee :5 5.50 V

Min

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground:5 VIN:5 Vee (Note 12)

±10

J.IA

Output Leakage Current

(Note 12)

±40

J.IA

lee1

Vee Current, Dynamic

(Notes 5,6)

100

rnA

lee2

Vee Current, Quiescent

(Note?)

6

mA

CIN

Input Capacitance

TA = 25°C, f = 1 MHz

10

pF

COUT

Output Capacitance

TA = 25°C, f = 1 MHz

10

pF

==================== Video Imaging Products
2-32

06/2B/95-LDS.2249-E

---- -- ------_
......
_---~--~

LF2249

~----

-~---

DEVICES INCORPORATED

12 x 12-bit Digital Mixer

•

•••

CLK

CONTROLS
(Except eEl

p
-_-_~~~~~~:x_'-_-_-_-_-_-_-_-_-_f-3 ttENA-

~*==~~Xg)C=:::>
12

DATA
OUTPUTS

PIN
NAME

YC11-S

Y7-4

•

Y7-4

Y3-0

CASOUT3-0

YC3-0

Z11-0

CASOUT15-4

ZC11-0

10
10

9-MULTIPLIER
ARRAY

10

=====================Video Imaging Products
2-37

03/11/94-LOS.2250-0

•

-=

..- ..---_
_----.----.-_ ..
.......--""-"'"---

-=a.:=.. =-=a

LF2250

DEVICES INCORPORATED

OPERATING MODES
The LF2250 can realize four different
user-selectable digital filtering architectures as determined by the state of
the mode (MODEI-O) inputs. Upon
selection of the desired function, the
LF2250 automatically chooses the
appropriate internal data paths and
input/ output bus structure. Table 1
details the modes of operation.

12 x 10-bit Matrix Multiplier
BIT WEIGHTING

SIGNAL DEFINITIONS

The internal sum of products of the
LF2250 can grow to 23 bits. However,
in order to keep the output format of
the matrix multiply mode (Mode 00)
identical to the input format, the X, Y,
and Z outputs are truncated to 12-bit
integer words. In the filter modes
(Modes 01, 10, 11), the cascade output
is always half-LSB rounded to 16 bits
(12 integer bits and 4 fractional bits).
The user may half-LSB round the
output to any size less than 16 bits by
simply forcing a "1" into the bit
position of the cascade input immediately below the desired LSB. For
example, if half-LSB rounding to 12
bits is desired, then a "1" must be
forced into the CASIN3 bit position
(CASOUT4 would then be the LSB).

Power

DATA FORMATTING

In all four modes, the user may adjust

The coefficient input ports (KA, KB,
KC) are lO-bit fractional two's complement format regardless of the operating mode. The data input ports (A, B,
C) are 12-bit integer two's complement format regardless of the operatingmode.

the bit weighting, by applying an
identical scaling correction factor to
both the input and output data
streams. If the coefficients are rescaled, then the relative weightings of
the cascade-in and cascade-out ports
will differ accordingly. Figure 1
illustrates the input and output bit
weightings for all four modes.

In the matrix multiplier mode (Mode

00), the data output ports (X, Y, Z) are
DATA OVERFLOW
12-bit integer two's complement
format. In the FIR filter and convolver Because the LF2250's matched input
modes (Modes 01,10,11), the X, Y,
and output data formats accommoand Z ports are configured as the
date unity gain (0 dB), input condicascade-in (CASINl5-0) and cascadetions that could lead to numeric
out (CASOUT1s-o) ports. These ports
overflow may exist. To ensure that no
assume 16-bit (12-bit integer, 4-bit
overflow conditions occur, the user
fractional) two's complement data on
must be aware of the maximum input
both the inputs and outputs. Table 2
data and coefficient word sizes
shows the data port formatting for
allowable for each specific algorithm
each of the four operating modes.
being performed.

VccandGND
+5 V power supply. All pins must be
connected.
Clock

CLK - Master Clock
The rising edge of CLK strobes all
enabled registers. All timing specifications are referenced to the rising
edge ofCLK.
Inputs

All-0, Bll-0, Cll-0 - Data Inputs
A, B, and C are the 12-bit registered

data input ports. Data presented to
these ports is latched into the multiplier input registers for the curren~
operating mode (Table 1). In the filter
modes (Modes 01, 10, 11), the rising
edge of CLK internally right-shifts
new data to the next filter tap.

KA9-0, KB9-0, KC9-0 - Coefficient Inputs
KA, KB, and KC are the 10-bit registered coefficient input ports. Data
presented to these ports is latched into
the corresponding internal coefficient
register set defined by CWEI-O (Table
4) on the next rising edge of CLK.
Table 3 shows which coefficient
registers are available for each coefficient input port.

====================Video Imaging Products
2-38

03111/94-LDS.22S0-D

-- ....- - - -

~-~

-=-Ui.:E~
...... - - -

LF2250

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier
CASOUT15-0 - Cascade Output

- - - - Data Input (All Modes) - - - 111 10 9 8 7
_211 210 2 9 28 27

6 5 4 3 2
0
26 2 5 24 23 22 21 20

(Sign)

-

Coefficient Input (All Modes) -

19 8 7 6 5 4 3 2 1 01
_2° 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9
(Sign)

- - - - - Cascade Input (Modes 01, 10, 11) - - - - 115 14 13 12 11 10 9 8 7 6 5 4 3 2
0
_211 210 2 9 2 8 27 2 6 2 5 24 2 3 22 21 20 2 1 2-2 2-3 2-4
(Sign)

In the filter modes (Modes 01,10,11),

the 12-bit Z port and four bits of the Y
port are internally reconfigured as the
16-bit registered cascade output port.

NOTE: The X, Y, and Z ports are
automatically reconfigured by the LF2250
as the cascade-in and cascade-out ports as
required for each operating mode. Because
both the X and Z ports are used for the
cascade ports, all X port pins and all Z
port pins are labelled as XC and Zc,
respectively. All Y port pins that are used
for the cascade ports are labelled as Y C.
Those Y port pins which are not used for
the cascade ports are labelled as Y.
Controls

MODEI-O - Mode Select

- - Internal Sum (All Modes)-120 19 18 17 ,.. 3 2 1 0
_211 2 10 2 9 28
2-6 2 7 ~ 2 9

I

(Sign)

- - - - Result (Mode 00) - - - - 111 10 9 8 7
_211 2 10 2 9 28 27

6 5 4 3 2
0
2 6 2 5 24 23 22 21 2 0

The registered mode select inputs
determine the operating mode of the
LF2250 (Table 1) for data being input
on the next clock cycle. When switching between modes, the internal
pipeline latencies of the device must
be observed. After switching operating modes, the user must allow
enough clock cycles to pass to flush
the internal registers before valid data
will appear on the outputs.

(Sign)

CWEI-O - Coefficient Write Enable
- - - - Cascade Out (Modes 01, 10, 11) - - - - 115 14 13 12 11 10 9 8 7 6 5 4 3 2
0
_211 2 10 2 9 2 8 27 2 6 2 5 24 2 3 22 21 2 0 2 1 2-2 2-3 2-4
(Sign)

CASIN15-0 - Cascade Input

Outputs

In the filter modes (Modes 01, 10, 11),

X11'{), Y11-0, Zl1-0 - Data Outputs

the 12-bit X port and four bits of the Y
port are internally reconfigured as the
16-bit registered cascade input port.
Data presented to this port will be
added to the internal sum of products.

The registered coefficient write enable
inputs determine which internal
coefficient register set to update
(Table 4) on the next clock cycle.

X, Y, and Z are the 12-bit registered
output ports for the matrix multiply
mode (Mode 00). These ports are
automatically reconfigured for the
filter modes (Modes 01,10,11) as the
cascade-in and cascade-out ports.

=====================Video Imaging Products
2·39

03/11/94-LDS.2250-D

- -......
-- -......- ----------~-

~----.....-.----~
-~

LF2250

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

DETAILS OF OPERATION

3 x 3 Matrix Multiplier - Mode 00
In this mode, all three input ports (A,
B, C) and all three output ports (X, Y,
Z) are utilized to implement a 3 x 3
matrix multiplication (triple dot
product). Each truncated 12-bit
output is the sum of all three input
words multiplied by the appropriate
coefficients (Table 5). The pipeline
latency for this mode is five clock
cycles. Therefore, the sum of products
will be output five clock cycles after
the input data has been latched. New
output data is subsequently available
every clock cycle thereafter.

(comprising of the summation of the
multiplications of the last nine data
inputs with their related coefficients)
becomes available (Table 5). The
CASIN term is also added to each new
output. The internal bus structure and
pipeline delays allow new input data
to be added every cycle while maintaining the structure of the filtering
operation. This addition of new data
every cycle produces the effect of the
convolution window moving to the
next pixel column.

Using the A and B ports, input data is
loaded and multiplied by the onboard coefficients. These products are
then summed with the CASIN data
and rounded to create the 16-bit
output. The cascade ports allow
multiple devices to be used together
for use with larger kernels. As with
Mode 10, each cycle results in a 16-bit
output created from the products and
summations performed.

- - - - - - - 3 x 3 Matrix Multiplier - Mode 00
X(n+4)

A(n)KA1(n)

+ B(n)KB1(n)

+ C(n)KC1(n)

Y(n+4)

A(n)KA2(n)

+ B(n)KB2(n)

+ C(n)KC2(n)

Z(n+4)

A(n)KA3(n)

+ B(n)KB3(n)

+ C(n)KC3(n)

- - - - - - - - 9-Tap FIR Filter -

CASOUT(n+12)

Mode 01 - - - - - - - -

A(n+8)KA3(n+8) + A(n+7)KA2(n+7) + A(n+6)KA1(n+6)
+ B(n+5)KB3(n+8) + B(n+4)KB2(n+7) + B(n+3)KB1(n+6)

9-Tap FIR Filter - Mode 01
This mode utilizes the 12-bit A and B
data input ports as well as the 16-bit
CASIN port. The input data should
be presented to the A and B ports
simultaneously. The resulting 9sample response, which is half-LSB
rounded to 16 bits, begins after five
clock cycles and ends after 13 clock
cycles (Table 5). The pipeline latency
from the input of an impulse response
to the center of the output response is
nine clock cycles. The latency from
the CASIN port to the CASOUT port
is four clock cycles. New output data
is available every clock cycle.

4 x 2-Pixel Convolver - Mode 11

+ B(n+2)KC3(n+8) + B(n+1)KC2(n+7) + B(n)KC1(n+6)
+ CASIN(n+9)

3
CASOUT(n+6)

x 3-Pixel Convolver -

Mode 10

A(n+2)KA3(n+2) + A(n+1)KA2(n+1) + A(n)KA1(n)
+ B(n+2)KB3(n+2) + B(n+1)KB2(n+1) + B(n)KB1(n)
+ C(n+2)KC3(n+2) + C(n+1)KC2(n+1) + C(n)KC1(n)
+ CASIN(n+3)

4 x 2-Pixel Convolver - Mode 11
CASOUT(n+7)

A(n+3)KA3(n+3) + A(n+2)KA2(n+2) + A(n+1)KA1(n+1)
+ A(n)KC3(n+3)

+ B(n+3)KB3(n+3) + B(n+2)KB2(n+2)

3 x 3-Pixel Convolver - Mode 10

+ B(n+1)KB1(n+1) + B(n)KC1(n+1)

When configured in this mode, line
delayed data is loaded through the A,
B, and C input ports. During each
cycle, a new rounded 16-bit output

+ CASIN(n+4)

====================Video Imaging Products
2-40

03/11/94-LDS.2250·D

-

-= --~-=-~~
---------- - --

LF2250

-~---

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

KA-T-~

II
B_T-~

KB

C-T-~

KC-T-~

x

y

z

====================== Video Imaging Products
2-41

03/11/94-LDS.22S0-D

- -....-._
- --.....
=-=-==..===.......
.......

--

-~----

LF2250

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

-~--

KA

21

21

21

KB_10r-~

21

21

21

KC --..:1:;,<0'-+I

CASIN --..:1:;,<6'-+I

NOTE:

NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS

CASOUT

= = = = = = = = = = = = = = = = = = = = Video Imaging Products
2-42

03111194-LDS.2250-D

_..-_--_.........
--- --................
----~

-... -......-.-~
-

LF2250

-~---

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

10

•

KA-7'-~

12

B-7'-~

10

KB-7'-~

10

KC-7'-~

CASIN

16

-7'-~

CASOUT

===================== Video Imaging Products
2-43

03111194-LDS.2250-D

LF2250
DEVICES INCORPORATED

A

12 x 10-bit Matrix Multiplier

12

-'7'-~

10

KA-r-~

12

10

KB-r-~

KC

NOTE:

10

-'7'-~

NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS

CASOUT

==================== Video Imaging Products
2-44

03/11/94-LDS.2250-D

- -- ~------------------~---

--

-~~-~

LF2250

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V

..

Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V
Signal applied to high impedance output ...................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs.............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to + 125°C

Parameter

Test Condition

VOH

Output High Voltage

Vcc

= Min., IOH =-2.0 mA

VOL

Output Low Voltage

Vcc

= Min., IOL =4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIx

Input Current

Ground

loz

Output Leakage Current

lee1

Supply Voltage
4.75 V ~ Vee ~ 5.25 V
4.50 V

~

Vee ~ 5.50 V

Min

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

±10

~

(Note 12)

±40

~

Vee Current, Dynamic

(Notes 5, 6)

160

mA

lee2

Vee Current, Quiescent

(Note 7)

12

mA

CIN

Input Capacitance

TA = 25°C, f

= 1 MHz

10

pF

COUT

Output CapaCitance

TA = 25°C, f = 1 MHz

10

pF

~

VIN

~

Vee (Note 12)

====================Video Imaging Products
2-45

03/11194-LDS.2250-D

- ---------- -.......
-------.....-.
......
-~~-~

-~--

LF2250

-

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

==================== Video Imaging Products
2-46

03/11/94-LDS.2250-D

-

;; -=-.-=.;;..=.

------ -------- - --~---

LF2250

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

ClK

CWE1-o

•

KA. KB. KC

1.0

A.B.C

MODE,-o

xxxxxxxxxC==========]o![o===========XX

10

X11-0

Y11-0
KA2 + KB2 + KC2

Z11-0

KA3 + KB3 + KC3

•••

A.B

1.0

MODE1-O xxxxxxxxXC===============2]01===============:::xxxxxxx
CASIN,,-Q

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>C§iD<=== • • • ==:x=:::BK&B1C::JX,..--::K"'C'::-""""'XC=JK@C:g:2=JXC=::EK£CL1=J><..........B13*===

= = = = = = = = = = = = = = = = = = = = Video Imaging Products
2-47

03/11/94-LDS_2250-D

-= -.-=.-----=-=-==.==
.......
.-=-~~

LF2250

-~--"""-'"
DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

•••

ClK

CWE1.0

KA, KB, KC

1.0
MODE1-o xxxxxxxxxC=================]10C=================XX
A, B,C

CASIN1s-o

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>e:§l:Xxxxxxxxxxxxxxxxxx xxx xx

-----V===::xC===X::::::::: ••• =:::X===:Jx

CASOUT1S-O - - - - - / '

.,

.

x

KA3+KB3+KC3

~r-ID

Xr;;::;;;;:;;;;:~7

KA2+KB2+KC2 'KA1+KB1+KC1

10

*==

11

•••

MODE1-o xxxxxxxxxC=================jJl1C================:::::XX
CASIN1fH)

CASOUT,S-o

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx>C§DCxxxxxxxxxxxxxxx
DD
, . - - -_____ ~;;;::::;;;;;::: r-1aa
~::===)xC====X::::::::: • • • =:::x===:::::xC:::;:KA3;;:+~KB;3;::;XC:::;KA2;:;;::+~K;B3;::X'""""'KA""'-+"'KB"""""'~C1 +KC3 ~

==================== Video Imaging Products
2-48

03/11194-lDS.2250-D

. - - -....- --- -------

~.-..-.-~

.,--.,

--~--...--- ........
--.-.-

LF2250

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -{).5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/lOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

VCC

d,
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

~n

a. A 0.1 /IF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DDT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
anteed as specified.
ground and tester common.
S. Supply current for a given applica- b. Ground and Vee supply planes
tioncanbeaccuratelyapproximatedby: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.
where

4

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DDT
input levels relative to the DDT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 20 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case rebut not 100% tested.
quirements of all parts. Responses from
the internal circuitry are specified from

t--....,...-o OUTPUT
n+

0.2 V

0.2V

=====================Video Imaging Products
2-49

03/11/94-LDS.2250-D

•

LF2250
DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

120-pin

2
A
B

3

, .. , ,
,_I
1....1
...

...

I ....'

,

...

I ....'

9

10

G

H

J

I ....'

I ....'

I ....'

I ....'

I ....'

l

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

...

I ....'

I ....'

I ....'

, ... XC2
, ... XCs
, ... Vee
,
1 ,

I ....'

...

I ....'

...

I ....'

I ....'

I ....'

I ....'

GND C10 GND Vec

I ....'

I ....'

I ....'

Co

Ba

,Bs... ,B3... ,B1...

I ....'

I ....'

, ... XCo
, ... XC3
, ...

I ....'

I ....'

...

I ....'

I ....'

Top View

I ....'

I ....'

I ....'

I ....'

I ....'

,Ae ,Aa...

I ....'

I ....'

...

I ....'

...

I ....'

...

I ....'

(Le., Component Side Pinout)

I ....'

I ....'

,A3... ,A2 ,A4...
...

I ....'

I ....'

,Y4... YCo
, ... Vee
, ...

I ....'

I ....'

,A7... ,A6 ,As...

Through Package

I ....'

,Ys... ,Y6... GND
, ...

I ....'

...

A11

,

I ....'

I ....'

, ... ,Bo A10
, ...

I ....'

,Y7... YCa
, ... Vee
, ...

I ....'

ClK

KEY

, ... , ... GND
, ...

I ....'

I ....'

I ....'

GND

I ....'

, ... ,Ao ,A1...

I ....'

, ... YC2
, ... GND
, ...

...

I ....'

I ....'

,

,

I ....'

KAa eWE1 eWEo
...

...

, ...

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

YC3

ZCo

ZC3

KA4

KA7

KAe

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

...

...

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

,

...

, ... , ... , ... ,

...

, ... ,

...

I ....'

,

...

, ... , ... , ... ,

...

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

, ...

, ... ZC4
, ... ZCs
, ... GND
, ... KCo
, ... GND
, Vee
, KBo
, ... KB4
, ... KBe
, ... KA1
, ... KAs
, KA6
, ...

I ....'

..

...

ZC2

N

I ....'

, ... XCa
, ... XCs
, ... XC11
, MODE1
, ... ,C9 ,C6... ,C4... ,C2 B11
, ... ,Be... ,Be... ,B2...

ZC1

M

13

...

YC1

K

12

, ... ,Ca... ,C7... ,Cs ,C3... ,C1... B10
, ... ,B7... ,B4...

YC9 YC10

F

11

I ....'

...

YC11

E

8

,

I ....'

...

7

, ... , ... , ... , ... , ... , ... , ... , ... , ... ,_I
, ..

I ....'

, ... ,

6

I ....'

XCe XC10 MODEo C11

XC1

D

5

XC7

XC4

C

4

I ....'

..

, ... ZCe
, ... KC4
, ... KB2
, ... KA2
, ... KA3
, ... ZC11
, ... KC2
, ... KC6
, ... KCe
, ... KBs
, ... KBe
, ZC7
,
,_I
,_I
I ....'

ZCs

I ....'

I ....'

ZCa ZC10 KC1

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

KC3

KCs

KC7

KCB

KB1

KB3

KB6

KB7

33 ns
25 ns

LF2250GC33
lF2250GC25

33 ns
25 ns

lF2250GM33
LF2250GM25

33 ns
25 ns

lF2250GMB33
LF2250GMB25

KAo

=====================Video Imaging Products
2·50

03111194-LDS.22S0·D

----........
--- ------------

....-..
---........-_

-

LF2250

-~---

DEVICES INCORPORATED

12 x 10-bit Matrix Multiplier

12o-pin

xc.

B4
B3
ClK
B.
61
Bo
A11
A10
A9

XC5

xc.
XC3

xc.
XC1
XCo

GND
YC11
YC10
YC.

As
A7
Aa
A5

Vee
YCa
Y7
Ya

GND
Y5

Y4

Top
View

A1
Ao

YCo

GND
CWEo
CWE1
KA9

KAa

GND

KA7
KAa
KA5
KA4

ZCO
ZC1
ZC.

KA3

ZC3

25 ns

A2

Vee
YC1
YC.
YC3

33 ns

M
As

ZC4

KA2

ZC5

KA1

LF2250QC33
LF2250QC25

===================== Video Imaging Products
2-51

03111194-lDS.2250-D

--.......
..- -----..-- ------..--.~-

-~--.....-.

-~---

DEVICES INCORPORATED

=:::.::=-=~

LF2272

=~~=~

Colorspace Converter/
Corrector (3 x 12-bits)

DEVICES INCORPORATED

o 40 MHz Data and Computation
Rate
o Full Precision Internal Calculations
with Output Rounding
DOn-board lO-bit Coefficient Storage
o Overflow Capability in Low
Resolution Applications
o Two's Complement Input and
Output Data Format
o 3 Simultaneous 12-bit Channels
(64 Giga Colors)
o Applications:
• Component Color Standards
Translations (RGB, YIQ, YUV)
• Color-Temperature Conversion
• Image Capturing and Manipulation
• Composite Color Encoding/
Decoding
• Three-Dimensional Perspective
Translation
o Replaces TRW/Raytheon TMC2272
o Package Styles Available:
• 120-pin Pin Grid Array
• 120-pin Plastic Quad Flatpack

The LF2272 is a high-speed digital
colorspace converter / corrector
consisting of three simultaneous 12-bit
input and output channels for functionality up to 64 Giga (236) colors.
Some of the applications the LF2272
can be used for include phosphor
colorimetry correction, image capturing and manipulation, composite color
encoding/ decoding, color matching,
and composite color standards
conversion/ transcoding.
The 3 x 3 matrix multiplier (triple dot
product) allows users to easily perform three-dimensional perspective
translations or video format conversions at real-time video rates. By
using the LF2272, conversions can be
made from the RGB (color component) format to the YIQ (quadrature
encoded chrominance) or YUV (color
difference) formats and vice versa
(YIQ or YUV to RGB). Differing signal
formats in each stage of a system can
be disregarded. For example, using

an LF2272 at each format interface
allows each stage of a system to
operate on the data while in the
appropriate format.
All inputs and outputs, as well as all
control lines, are registered on the
rising edge of clock. The LF2272
operates at clock rates up to 40 MHz
over the full commercial temperature
and supply voltage ranges. A narrower data path can be used to allow
the LF2272 to work with many
different imaging applications.
DETAILS OF OPERATION
All three input ports (A, B, C) and all
three output ports (X, Y, Z) are
utilized to implement a 3 x 3 matrix
multiplication (triple dot product).
Each truncated 12-bit output is the
sum of all three input words multiplied by the appropriate coefficients
(Table 1). The pipeline latency is five
clock cycles. Therefore, the sum of

ClK
CWEll-0

DATA
INPUTS

COEFFICIENT
INPUTS

{

{

All-0
B11·0
C11-0

KA9-0
KB9-0
KC9-D

,

2

12
T

,
12
,

12

® ® ®
® ® ®
® ® ®

12
12
12

Xll-0

Y11-0
Zll-0

}

DATA
OUTPUTS

10
10

9-MUlTIPLIER
ARRAY

10

=====================Video Imaging Products
2-53

OS/2B/95-LDS.2272-D

•

-

- ---

= ===-== =
-~~~~

LF2272

--.-.~~-

-~--~

DEVICES INCORPORATED

products will be output five clock
cycles after the input data has been
registered. New output data is
subsequently available every clock
cycle thereafter.
DATA FORMATTING

The data input ports (A, B, C) and
data output ports (X, Y, Z) are 12-bit
integer two's complement format.
The coefficient input ports (KA, KB,
KC) are IO-bit fractional two's
complement format. Refer to
Figures la and lb.
BIT WEIGHTING

The internal sum of products of the
LF2272 can grow to 23 bits. However,
in order to keep the output format
identical to the input format, the X, Y,
and Z outputs are rounded to 12-bit
integer words. The rounding is done
only at the final output stage to allow
accuracy, with correct rounding and
overflow, for applications requiring
less than 12-bit integer words. The
user may adjust the bit weighting by
applying an identical scaling correction factor to both the input and
output data streams.

Colorspace Converterl
Corrector (3 x 12-bits)

X(n+4)

A(n)KA1(n)

+ B(n)KB1(n)

+ C(n)KC1(n)

Y(n+4)

A(n)KA2(n)

+ B(n)KB2(n)

+ C(n)KC2(n)

Z(n+4)

A(n)KA3(n)

+ B(n)KB3(n)

+ C(n)KC3(n)

DATA OVERFLOW

SYSTEMS SMALLER THAN 12-BITS

Because the LF2272's matched input
and output data formats accommodate unity gain (0 dB), input conditions that could lead to numeric
overflow may exist. To ensure that no
overflow conditions occur, the user
must be aware of the maximum input
data and coefficient word sizes
allowable for each specific algorithm
being performed.

Using a data path less than 12-bits
requires the input data to be right
justified and sign extended to 12-bits
because the LF2272 carries out all
calculations to full precision. Since all
least-significant bits are used, the
desired X, Y, and Z outputs are
rounded correctly and upper-order
output bits are used for overflow.

- - - - - - Data Input - - - - - 111 10 9 8 7
_211 2 10 2 9 2 8 27

6 5 4 3 2
0
2 6 2 5 24 2 3 22 21 2 0

(Sign)

- - - - Coefficient Input - - - 19 8 7 6 5
_20 2-1 2-2 2-3 2-4

4

z-s

3 2
0
2-6 ~7 2--8 2-9

(Sign)

- - - - Internal Sum - - - 120 19 18 17
_211 2 10 2 9 28

~ 3
2-6

2
~7

0
2--8 2-9

(Sign)

- - - - - - Result - - - - - - 111 10 9 8 7
_211 2 10 2 9 2 8 27

6 5 4 3 2
0
2 6 2 5 24 2 3 22 21 20

(Sign)

===================== Video Imaging Products
2·54

06/28/95-LDS.2272·D

--.......- _..--------- --------..-.----~~-~

LF2272

DEVICES INCORPORATED

Colorspace Converterl
Corrector (3 x 12-bits)

SIGNAL DEFINITIONS
Power

VccandGND
+5 V power supply. All pins must be
connected.
Clock

Outputs

CLK - Master Clock
Xll-0,

The rising edge of CLK strobes all
enabled registers. All timing specifications are referenced to the rising
edgeofCLK.

Yll-O,

Zl1-0 -

Data Outputs

X, Y, and Z are the 12-bit registered
data output ports.
Controls

Inputs

CWELl-o - Coefficient Write Enable

All-0, B11-0, Cll-0 - Data Inputs

The registered coefficient write enable
inputs determine which internal
coefficient register set to update
(Table 3) on the next clock cycle.

A, B, and C are the 12-bit registered
data input ports. Data presented to
these ports is latched into the multiplier input registers.

KA9-0, KB9-0, KC9-0 - Coefficient Inputs
KA, KB, and KC are the lO-bit registered coefficient input ports. Data
presented to these ports is latched into
the corresponding internal coefficient
register set defined by CWELI-O
(Table 3) on the next rising edge of
CLK. Table 2 shows which coefficient
registers are available for each coefficient input port.

==================== Video Imaging Products
2·55

06/28/95-LDS.2272·D

---- -- ---------.....
-~--~

LF2272

-

---..-.~-

-~---

DEVICES INCORPORATED

Colorspace Converterl
Corrector (3 x 12-bits)

A

KA

B

KB

C

KC

x

y

z

==================== Video Imaging Products
2-56

06/2B/95-LDS.2272-D

- -- ------------- ...... -- -

-

-~~-~

LF2272

DEVICES INCORPORATED

Colorspace Converterl
Corrector (3 x 12-bits)

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V

•

Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V
Signal applied to high impedance output ...................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs .............................................................................................................. 25 rnA
Latchup current ................................................................................................................................ > 400 rnA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

Parameter

Test Condition

VoH

Output High Voltage

Vcc

=Min., IOH =-2.0 rnA

VoL

Output Low Voltage

Vcc

=Min., IOL =4.0 rnA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

Ground

loz

Output Leakage Current

lee1

Supply Voltage
4.75 V

~

Vee ~ 5.25 V

4.50 V ~ Vee ~ 5.50 V

Min

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

±10

IlA

(Note 12)

±40

IlA

Vee Current, Dynamic

(Notes 5,6)

160

rnA

lee2

Vee Current, Quiescent

(Note 7)

12

rnA

CIN

Input Capacitance

TA

=25°C, f =1 MHz

10

pF

COUT

Output Capacitance

TA

=25°C, f =1 MHz

10

pF

~

VIN

~

Vee (Note 12)

=====================Video Imaging Products
2·57

06/28/95-LDS.2272·D

- ----..-.

- -- -------- ----------""-"'"---~~-~

LF2272

DEVICES INCORPORATED

Colorspace Converterl
Corrector (3 x 12-bits)

2

3

4

8

5

ClK

CWElHl

X)bd:~~>CE:)O~>c:rr::::x:~>c====][====::xx

10
Xl1-0

KA1 + KB1 + KC1

Yl1-Q

KA2 + KB2 + KC2

Zl1-0

===>c===>c===X===X===)(===:X===3k~KA3~+;K~B3~+;K~C3(C==

==================== Video Imaging Products
2-58

OS/28/95-LDS_2272-D

--......
-------- --- ----...--.

_....--.

_ _ -...r ____ -...-.

LF2272

-

-~---

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

Colorspace Converterl
Corrector (3 x 12-bits)

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/toIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may beused. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 rnA to reduce the RC
delay component of the measurement.

the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 m V
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vce

do

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

}
~n

a. A 0.1 ~F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
ground and tester common.
anteed as specified.

5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated by: must be brought directly to the DDT
NCV2 F
socket or contactor fingers.
where
N
C
V
F

4

= total number of device outputs
= capacitive load per output

=supply voltage

= clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 20 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.

+--....,...-0 OUTPUT
n+
D1
p-

-:::==~~~~~#=::::

TRISTATE
OUTPUTS _

=====================Video Imaging Products
2-59

06/2B/95-LDS.2272-D

----- --- ---------- - -----~~-~

LF2272

-

.--.....-.~--

-.-.-

DEVICES INCORPORATED

Colorspace Converterl
Corrector (3 x 12-bits)

120-pin

2

A
B

C
D

, ..
,_I

3

4

5

6

7

8

9

10

11

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

, ... CTT
, ... ,Ca... ,C7... ,C5... , ... , ... , ... ,
,X7... ,Xs... XTO
, ... GND
CT

BTO

B7

,

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

X5

Xs

XTT

GND

Cs

Cs

C4

C2

BTT

Bs

Bs

B2

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

Co

Ba

,B5... ,B3 ,BT

,

...

I ....'

, ... , ... , ... , ... , ... , ... , ... , ... , ... , ... , ... , ...

,XT ,X2... ,XS... Vee
, ...
1 ,
...

I ....'

I ....'

GND CTO GND Vee

I ....'

, ... ,Xo... ,X3...

...

I ....'

I ....'

Bo

ATO

I ....'

I ....'

I ....'

, ... ,

KEY

,Vs... VTO
, ... GND
, ...

ATT

I ....'

I ....'

I ....'

I ....'

Top View

I ....'

I ....'

Through Package

Vs

,

GND

(i.e., Component Side Pinout)

I ....'

I ....'

I ....'

,

...

I ....'

I ....'

K

I ....'

I ....'

I ....'

I ....'

I ....'

...

I ....'

I ....'

I ....'

I ....'

,A3... ,A2 ,A4...
...

, ...
,V4... ,Vo... Vee

J

...

...

V5

...

,

,A7... ,As ,A5...

I ....'
...

...

, ... ,As ,As...

I ....'

,V7... ,Va... Vee
, ...

,

...

I ....'

ClK

I ....'

N

...

I ....'

F

M

...

B4

X4

I ....'

l

..

I ....'

C3

I ....'

VTT

H

13

, ... , ... , ... , ... , ... , ... , ... , ... , ... , ... , ... ,_I
,

I ....'

E

G

12

, ...
,VT... ,V2... GND

I ....'

I ....'

GND

, ...

,Ao...

I ....'

,AT...

I ....'

I ....'

I ....'

KAa CWElT CWELD

,

,V3 ,Zo ,Z3... ,

...

, ... , ... ,

...

, ... ,

...

,

...

...

,

...

I ....'

I ....'

KA7

KAs

,

...

,

...

...

...

I ....'

I ....'

I ....'

ZT

Z4

Zs

I ....'

I ....'

I ....'

...

...

...

...

...

...

...

'-'
Z5

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

Za

ZTO

KCT

KC3

KC5

KC7

KCa

KBT

KB3

KBs

KB7

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

GND KCo GND Vee KBo KB4 KBs KAT
I ....'

I ....'

,

...

I ....'

I ....'

KA5
I ....'

...

, ...

, ...

, ...

, ... , ...

KAs

I ....'

I ....'

I ....'

I ....'

I ....'

I ....'

, ... , ... , ... , ... , ... , ... ,
I ....'

, ...

I ....'

KA4

, ...

, KC2
, KC4
, KCs
, KCs
, KB2
, ... KBs
, ... KA2
, ... KA3
, ..
,Z2.. ,Z7 ,Zs ZTT
, ... KB5
,_I

33 ns
25 ns

LF2272GC33
lF2272GC25

33 ns
25 ns

lF2272GM33
lF2272GM25

33 ns
25 ns

lF2272GMB33
lF2272GMB25

KAo

====================Video Imaging Products
2·60

OS/2S/S5-LOS.2272-0

- - --I...u!ii£;

LF2272

-~---

DEVICES INCORPORATED

Colorspace Converterl
Corrector (3 x 12-bits)

120-pin

B4

XB
Xs
X4

B3

elK

x,
X2
x,

Xo
GND
V11
v,o
V9

Vee
VB
V7
VB
GND
Vs
V4
Vo

vee
V,
V2
V,
GND
Zo
Z,

Z2
Z3
Z4
Zs

33 ns
25 ns

B2

B'
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Top
View

Bo
A11
A,o
A9
AB
A7
AB
As
M
A3
A2

A,
Ao
GND
eWEo
eWE,
KA9
KAB

KA7
KAB

KAs
KA4
KA3
KA2

KA,

LF2272QC33
LF2272QC25

====================Video Imaging Products
2-61

06/28/95-LDS.2272-D

=-=-==-===.......r
- ---

-~~-~ ---~~-

-~---

DEVICES INCORPORATED

-- -- ----------=--=-=
- -=
-=--

-~

LF43168

~

Dual 8-Tap FIR Filter

DEVICES INCORPORATED

o 66 MHz Data and Computation Rate The LF43168 is a high-speed dual FIR
filter capable of filtering data at realo Two Independent 8-Tap or Single
16-Tap FIR Filters

o lO-bit Data and Coefficient Inputs

o 32 Programmable Coefficient Sets
o Supports Interleaved Coefficient Sets
o User Programmable Decimation up

o
o
o
o

to 16:1
Maximum of 256 FIR Filter Taps,
16 x 16 2-D Kernels, or 10 x 20-bit
Data and Coefficients
Replaces Harris HSP43168
Available 100% Screened to
MlL-STD-883, Class B
Package Styles Available:
• 84-pin Plastic LCC, J-Lead
• 100-pin Plastic Quad Flatpack
• 84-pin Ceramic PGA

INB9·oJ
OUTe·o

time video rates. The device contains
two FIR filters which may be used as
two separate filters or cascaded to
form one filter. The input and coefficient data are both lO-bits and can be
in unsigned, two's complement, or
mixed mode format.

The filter architecture is optimized for
symmetric coefficient sets. When
symmetric coefficient sets are used,
each filter can be configured as an 8-tap
FIR filter. If the two filters are cascaded, a 16-tap FIR filter can be
implemented. When asymmetric
coefficient sets are used, each filter is
configured as a 4-tap FIR filter. If both
filters are cascaded, an 8-tap filter can

~

10
9

INAll-o

CSEL4-Q
CIN9·0
Ae-Q

There is on-chip storage for 32
different sets of coefficients. Each set
consists of eight coefficients. Access
to more than one coefficient set
facilitates adaptive filtering operations. The 28-bit filter output can be
rounded from 8 to 19 bits.

~
;J

~J

10

be implemented. The LF43168 can
decimate the output data by as much
as 16:1. When the device is programmed to decimate, the number of •
clock cycles available to calculate filter
taps increases. When configured for
16:1 decimation, each filter can be
configured as a 128-tap FIR filter (if
symmetric coefficient sets are used).
By cascading these two filters, the
device can be configured as a 256-tap
FIR filter.

V
5
10
9

WR

ICOEFFICIENT~
BANK A

y

CONTROL

FILTER
CELLA

ICOEFFICIENT~

f--

BANKB

FILTER
CELLB

I
~
I MUXlADDER I

9

119

I

OUT27·9

=====================Video Imaging Products
2-63

07/12/95-LDS.4316e·A

IIIIII
~ ~I::b
~

~

__FJJ=i !,~L!§J=I~ _______________________________ _

__________________ ,=I~ f!L.!~~!__

Mu~mRL-----------=~--~------~-------------------------------------------r------~---------------------------------------------,

~ tmb
111111
~ ~'~~II

2l

TXFR~~~__1

Cl

_I

INAa-o

~~.
MU>LCTAL

.1

--+------------'

FWRD

.1

RVRS

_I

~

...
WR
CSEL.4-0

<

ACCEN

is:

c

CD

0

3

MUX1-G

I',

.16 I

.. I

MUXI

I",

c
!!.

ROUND_CTRL

CO

C»

ceo

~

C»
"0

j

oCC

3! "'tI

:a
'"r 0

~

OEL

~:v-'

!!
:D

I

'" a.
:,.
C
(JJ

'"0;
~

()
t/)

CLK

NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPEUNE DElAYS.

--- --

- ----------------..........
.....-.- ......
-~-----

LF4316S

DEVICES INCORPORATED

DualS-Tap FIR Filter

SIGNAL DEFINITIONS
Power

Coefficient

Data

VccandGND
+5 V power supply. All pins must be
connected.

Fractional Unsigned

9 8 7
2° 21 2-2

~

2
01
27 2-s 2-9

19 8 7
20 21 Z-2

~

2
0
2 7 2-s2 9

Clock

CLK - Master Clock
The rising edge of CLK strobes all
enabled registers.

Fractional Two's Complement

9 8 7
_2°2 1 22

~

2
o1
2 7 2-s2 9

(Sign)

0
19 8 7 ~2
_20 Z-1 2-2
2-7 2-s 2-9
(Sign)

Inputs

INA9-0 - Data Input (FIR Filter A)
INA9-0 is the lO-bit registered data
input port for FIR Filter A. INA9-0
can also be used to send data to FIR
Filter B. Data is latched on the
rising edge of CLK.

Fractional Unsigned

1272625"'210

*

Fractional Two's Complement

127 26 25

2

2

0 1

16

Z-172

18

INB9-0 - Data Input (FIR Filter B)
INB9-0 is the lO-bit registered data
input port for FIR Filter B. Data is
latched on the rising edge of CLK.
INB9-1 is also used as OUTs-o, the nine
least significant bits of the data output
port (see OUT27-O section).

CIN9-0 - Coefficient/Control Data Input
CIN9-0 is the data input port for the
coefficient and control registers. Data
is latched on the rising edge of WR.

A8-0 - Coefficient/Control Address
As-o provides the write address for data
on CIN9-0. Data is latched on the
falling edge of WR.
WR -

Coefficient/Control Write

The rising edge of WR latches data on
CIN9-0 into the coefficient/ control
register addressed by As-o.

CSEL4-0 - Coefficient Select
CSEL4-0 determines which set of
coefficients is sent to the multipliers in
both FIR filters. Data is latched on the
rising edge of CLK.

Outputs

FWRD - Forward ALU Input

OUT27-0 - Data Output

When FWRD is LOW, data from the
forward decimation path is sent to the
"A" inputs on the ALUs. When
FWRD is HIGH, "Q" is sent to the "A"
inputs on the ALUs. This signal is
latched on the rising edge of CLK.

OUT27-0 is the 28-bit registered data
output port. OUTs-O is also used as
INB9-1, the nine most significant bits
of the FIR Filter B data input port (see
INB9-O section). If both filters are
configured for even-symmetric
coefficients, and both input and
coefficient data is unsigned, the filter
output data will be unsigned. Otherwise, the output data will be in two's
complement format.
Controls

SHFTEN - Shift Enable
When SHFTEN is LOW, data on
INA9-0 and INB9-0 can be latched into
the device and data can be shifted
through the decimation registers.
When SHFTEN is HIGH, data on
INA9-0 and INB9-0 can not be latched
into the device and data in the input
and decimation registers is held. This
signal is latched on the rising edge
ofCLK.

RVRS - Reverse ALU Input
When RVRS is LOW, data from the
reverse decimation path is sent to the
"B" inputs on the ALUs. When RVRS
is HIGH, "Q" is sent to the "B" inputs
on the ALUs. This signal is latched on
the rising edge of CLK.

TXFR - LIFO Transfer Control
When TXFR goes LOW, the LIFO
sending data to the reverse decimation
path becomes the LIFO receiving data
from the forward decimation path,
and the LIFO receiving data from the
forward decimation path becomes the
LIFO sending data to the reverse
decimation path. The device must see
a HIGH to LOW transition of TXFR in
order to switch UFOs. This signal is
latched on the rising edge of CLK.

=====================Video Imaging Products
2-65

07/12/95-LDS.43168·A

---- --- ------------_ .......

-~~-~

-~----........-.
-...-.

LF43168

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

ACCEN - Accumulate Enable
When ACCEN is HIGH, both accumulators are enabled for accumulation
and writing to the accumulator output
registers is disabled (the registers hold
their values). When ACCEN goes
LOW, accumulation is halted (by
sending zeros to the accumulator
feedback inputs) and writing to the
accumulator output registers is
enabled. This signal is latched on the
rising edge of CLK.

0-3

MUXI-O - Mux/Adder Control
MUXI-O controls the Mux/ Adder as
shown in Table 3. Data is latched on
the rising edge of CLK.
OEL - Output Enable Low
When OEL is LOW, OUT8-0 is enabled
for output and INB9-1 can not be used.
When OEL is HIGH, OUT8-0 is placed
in a high-impedance state and INB9-1
is available for data input.

Decimation Factor!
0000
Decimation Register Delay Length 0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

= No Decimation, Delay by 1
Decimate by 2, Delay by 2
= Decimate by 3, Delay by 3
Decimate by 4, Delay by 4
Decimate by 5, Delay by 5
Decimate by 6, Delay by 6
= Decimate by 7, Delay by 7
Decimate by 8, Delay by 8
Decimate by 9, Delay by 9
Decimate by 10, Delay by 10
Decimate by 11, Delay by 11
= Decimate by 12, Delay by 12
Decimate by 13, Delay by 13
= Decimate by 14, Delay by 14
= Decimate by 15, Delay by 15
= Decimate
16,

=

=
=
=
=
=
=
=
=

4

Filter Mode Select

5

Coefficient Symmetry Select

o = Single Filter Mode
1 = Dual Filter Mode
o = Even-Symmetric Coefficients

6

FIR Filter A: Odd!Even Taps

o = Odd Number of Filter Taps

7

FIR Filter B: Odd/Even Taps

o = Odd Number of Filter

8

FIR Filter B Input Source

0=
1 =

9

Interleaved/Non-Interleaved
Coefficient Sets

o = Non-Interleaved Coefficient Sets

1 = Odd-Symmetric Coefficients
1 = Even Number of Filter

OEH - Output Enable High
When OEH is LOW, OUT27-9 is
enabled for output. When OEH is
HIGH, OUT27-9 is placed in a highimpedance state.

Bits 0-3 of Control Register 0 control
the decimation registers. The decimaControl Registers
tion factor and decimation register
delay length is set using these bits.
There are two control registers which
determine how the LF43168 is config- Bit 4 determines if FIR filters A and B
operate separately as two filters or
ured. Tables 1 and 2 show how each
together as one filter. Bit 5 is used to
register is organized. Data on CIN9-O
select even or odd-symmetric coeffiis latched into the addressed control
cients. Bits 6 and 7 determine if there
register on the rising edge of WR.
are an even or odd number of taps in
Address data is input on A8-O. Confilters A and B respectively. When the
trol Register 0 is written to using
FIR filters are set to operate as two
address OOOH. Control Register 1 is
separate filters, bit 8 selects either
written to using address 001H (Note
INA9-0 or INB9-0 as the filter B input
that addresses 002H to OFFH are
source. Bit 9 determines if the coeffireserved and should not be written
to). When a control register is written cient set used is interleaved or nonto, a reset occurs which lasts for 6 CLK interleaved (see Interleaved Coefficient Filters section). Most applicacycles from when WR goes HIGH.
tions use non-interleaved coefficient
This reset does not alter any data in
sets (bit 9 set to "0").
the coefficient banks. Control data
can be loaded asynchronously to CLK.
FUNCTIONAL DESCRIPTION

1 = Interleaved Coefficient Sets

Bits 0 and 1 of Control Register 1
determine the input and coefficient
data formats respectively for filter A.
Bits 2 and 3 determine the input and
coefficient data formats respectively
for filter B. Bit 4 is used to enable or
disable data reversal on the reverse
decimation path. When data reversal
is enabled, the data order is reversed
before being sent to the reverse
decimation path. Bits 5-8 select where
rounding will occur on the output
data (See Mux/ Adder section). Bit 9
enables or disables output rounding.
Coefficient Banks
The coefficient banks supply coefficient data to the multipliers in both
FIR filters. The LF43168 can store 32
different coefficient sets. A coefficient

====================Video Imaging Products
2-66

07/12/95-LDS.43168·A

- - -----_--;;;

~.:.=~

..
-""-"""---

LF43168

.--.~...-.-~

DEVICES INCORPORATED

o

Dual8-Tap FIR Filter

FIR Filter A Input Data Format

0= Unsigned
1 = Two's Complement

FIR Filter A Coefficient Format

0= Unsigned
1 = Two's r.nmnlerrlenl

2

FIR Filter B Input Data Format

0= Unsigned
1 = Two's r.nmnlerrlenl

3

FIR Filter B Coefficient Format

0= Unsigned
1 = Two's r.nlmnllAmlAni

4

Data Order Reversal Enable

0= Enabled
1 = Disabled

Output Round Position

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011

5-8

9

Output Round Enable

set consists of 8 coefficient values.
Each bank can hold 32 lO-bit values.
CSEU-O is used to select which
coefficient set is sent to the filter
multipliers. The coefficient set fed to
the multipliers may be switched every
CLK cycle if desired.
Data on CIN9-O is latched into the
addressed coefficient bank on the
rising edge of WR. Address data is
input on As-o and is decoded as
follows: AI-O determines the bank
number ("00", "01", "10", and "11"
correspond to banks 0, 1,2, and 3
respectively), A2 determines which
filter ("0" = filter A, "1" = filter B), A7-3
determines which set number the
coefficient is in, and As must be set to
"1". For example, an address of
"100111011" will load coefficient set 7
in bank 3 of filter A with data. Coefficient data can be loaded asynchronously to CLK.

grammed to decimate by 2 to 16 (see
Decimation section and Table 1).
SHFTEN enables and disables the
shifting of data through the decimation registers. When SHFTEN is LOW,
data on INA9-O and INB9-O can be
latched into the device and data can
be shifted through the decimation
registers. When SHFTEN is HIGH,
•
data on INA9-O and INB9-O can not be
latched into the device and data in the
input and decimation registers is held.
Data feedback circuitry is positioned
between the forward and reverse
decimation registers. It controls how
data from the forward decimation
path is fed to the reverse decimation
path. The feedback circuitry can
either reverse the data order or pass
the data unchanged to the reverse
decimation path. The mux/ demux
sends incoming data to one of the
UFOs or the data feedback decimation
register. The UFOs and decimation
register feed into a mux. This mux
determines if one of the UFOs or the
decimation register sends data to the
reverse decimation path.

= 2-10
= 2-9
= 2-8
= 2-7
= 2-6

= 2-5
= 2-4
= 2-3

= 2-2
= 2-1

= 20
= 21

0= Enabled
1 = Disabled

If the data order needs to be reversed

Decimation Registers

The decimation registers are provided
to take advantage of symmetric filter
coefficients and to provide data
storage for 2-D filtering. The outputs
of the registers are fed into the ALUs.
Both inputs to an ALU need to be
multiplied by the same filter coefficient. By adding or subtracting the
two data inputs together before being
sent to the filter multiplier, the number of filter taps needed is cut in half.
Therefore, an 8-tap FIR filter can be
made with only four multipliers. The
decimation registers are divided into
two groups, the forward and reverse
decimation registers. As can be seen
in Figure 1, data flows left to right
through the forward decimation
registers and right to left through the
reverse decimation registers. The
decimation registers can be pro-

before being sent to the reverse
decimation path (for example, when
decimating), Data Reversal Mode
should be enabled by setting bit 4 of
Control Register 1 to "0". When Data
Reversal is enabled, data from the
forward decimation path is written
into one of the LIFOs in the data
feedback section while the other LIFO
sends data to the reverse decimation
path. When TXFR goes LOW, the
UFO sending data to the reverse
decimation path becomes the UFO
receiving data from the forward
decimation path, and the UFO
receiving data from the forward
decimation path becomes the UFO
sending data to the reverse decimation
path. The device must see a HIGH to
LOW transition of TXFR in order to
switch UFOs. The size of data blocks
sent to the reverse decimation path is
determined by how often TXFR goes
LOW. To send data blocks of size 8 to

=====================Video Imaging Products
2-67

07/12/95-LDS.43166-A

-

- ---

=
=-=-=:.===......

.r':~=~

LF43168

-~---

DEVICES INCORPORATED

the reverse decimation path, TXFR
would have to be set LOW once every
8 CLK cycles. Once a data block size
has been established (by asserting
TXFR at the proper frequency),
changing the frequency or phase of
TXFR assertion will cause unknown
results.
If data should be passed to the reverse

decimation path with the order
unchanged, Data Reversal Mode
should be disabled by setting bit 4 of
Control Register 1 to "1" and TXFR
must be set LOW. When Data Reversal is disabled, data from the forward
decimation path is written into the
data feedback decimation register.
The output of this register sends data
to the reverse decimation path. The
delay length of this register is the
same as the forward and reverse
decimation register's delay length.

Dual 8-Tap FIR Filter
Decimation

Accumulators

Decimation by N is accomplished by
only reading the LF43168's output once
every N clock cycles. For example, to
decimate by 10, the output should
only be read once every 10 clock
cycles. When not decimating, the
maximum number of taps possible
with a single filter in dual filter mode
is eight. When decimating by N, there
are N - 1 clock cycles between output
readings when the filter output is not
read. These extra clock cycles can be
used to calculate more filter taps. As
the decimation factor increases, the
number of available filter taps increases
also. When programmed to decimate
by N, the number of filter taps for a
single filter in dual filter mode increases
to8N.

The multiplier outputs are fed into an
accumulator. Each filter has its own
accumulator. The accumulator can be
set to accumulate the multiplier
outputs or sum the multiplier outputs
and send the result to the accumulator
output register. When ACCEN is
HIGH, both accumulators are enabled
for accumulation and writing to the
accumulator output registers is
disabled (the registers hold their
values). When ACCEN goes LOW,
accumulation is halted (by sending
zeros to the accumulator feedback
inputs) and writing to the accumulator output registers is enabled.
MuxlAdder

When the LF43168 is configured as
two FIR filters, the Mux/ Adder is
used to determine which filter drives
When the LF43168 is configured to
the output port. When the LF43168 is
The ALUs can perform the following
operate as a single FIR filter, the
operations: B + A, B - A, pass A, pass configured as a single FIR filter, the
forward and reverse decimation paths B, and negate A (-A). If FWRD is
Mux/ Adder is used to sum the
in filters A and B are cascaded together. LOW, the forward decimation path
outputs of the two filters and send the
The data feedback section in filter B
provides the A inputs to the ALUs. If result to the output port. If lO-bit data
routes data from the forward decima- FWRD is HIGH, the A inputs are set to and 20-bit coefficients or 20-bit data
tion path to the reverse decimation
and lO-bit coefficients are required,
"0". If RVRS is LOW, the reverse
path. The configuration of filter B's
decimation path provides the B inputs the Mux/ Adder can facilitate this by
feedback section determines how data to the ALUs. If RVRS is HIGH, the B
scaling filter B's output by 2-10 before
is sent to the reverse decimation path. inputs are set to "0". FWRD, RVRS,
being added to filter A:s output.
Data going through the feedback
and the filter configuration determine MUXI-O determines what function the
section in filter A is sent through the
which ALU operation is performed. If Mux/ Adder performs (see Table 3).
decimation register.
FWRD and RVRS are both set LOW,
and the filter is set for even-symmetric The Mux/ Adder is also used to round
The point at which data from the
coefficients,
the ALU will perform the the output data before it is sent to the
forward decimation path is sent to the
output port. Output data is rounded by
B + A operation. If FWRD and RVRS
data feedback section is determined
adding a "1" to the bit position selected
are
both
set
LOW,
and
the
filter
is
set
by whether the filter is set to have an
using
bits 5-8 of Control Register 1 (see
for odd-symmetric coefficients, the
even or odd number of filter taps. If
Table 2). For example, to round the
ALU
will
perform
the
B
A
operation.
the filter is set to have an even number
If FWRD is set LOW, RVRS is set
of taps, the output of the third forward decimation register is sent to the HIGH, and the filter is set for evensymmetric coefficients, the ALU will
feedback section. If the filter is set to
perform the pass A operation. If
have an odd number of taps, the data
FWRD is set LOW, RVRS is set HIGH,
that will be output from the third
and
the filter is set for odd-symmetric
forward decimation register on the
next CLK cycle is sent to the feedback coefficients, the ALU will perform the
negate A operation. If FWRD is set
section.
HIGH, RVRS is set LOW, and the filter
is set for either even or odd-symmetric
coefficients, the ALU will perform the
pass B operation.
Arithmetic Logic Units

====================Video Imaging Products
2·68

07/12195-LDS.43168-A

.-.--- - ----.. ---...---

- .-.-.
- --~ -~--

LF43168

-~---

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

I

876 5 4 3 2

I

7 6 5 4 3 2

Even-Tap, Even-Symmetric

Odd-Tap, Even-Symmetric

Even-Tap, Odd-Symmetric

Coefficient Set

Coefficient Set

Coefficient Set

DATA IN

--.---+~

DATA IN --.---+~

COEFO

COEFO

COEF1 - - 1 - - - + 1

COEF 1 - - 1 - - - + 1

COEF2 - - + - - - - - + - - _ _ _ + !

COEF2--+-----+--____+i

ooEF3--+----+----+--.(

OO~F3--I-----+----+---.(

EVEN-TAP FILTER

output to 16 bits, bits 5-8 of Control
Register 1 should be set to "0011"_ This
will cause a "1" to be added to bit
position 2""7_
Symmetric Coefficients

The LF43168 filter architecture is
optimized for symmetric filter coefficient sets_ Figure 3 shows examples of
the different types of symmetric
coefficient sets_ In even-symmetric
sets, each coefficient value appears
twice (except in odd-tap sets where
the middle value appears only once)_
In odd-symmetric sets, each coefficient
appears twice, but one value is
positive and one is negative_ If the

ODD-TAP FILTER

two data input values that will be
multiplied by the same coefficient are
added or subtracted before being sent
to the filter multiplier, the number of
multipliers needed for an N-tap filter
is cut in half_ Therefore, an 8-tap filter
can be implemented with four multipliers if a symmetric coefficient set is
used_
FILTER CONFIGURATIONS
Figures 4-6 show the data paths from
filter input to filter multipliers for all
symmetric coefficient filters_ Figure 7
shows the interleaved coefficient filter
configuration_ Each diagram shows

one of the two FIR filters when the
device is configured for dual filter
mode_ The diagrams can be expanded
to include both filters when the device
is configured for single filter mode_
Even-Symmetric Coefficient Filters

Figure 4 shows the two possible
configurations when the device is
programmed for even-symmetric
coefficients and no decimation_
Note that coefficient 3 on the oddtap filter must be divided by two to
get the correct result (The coefficient
must be input to the device already
divided by two)_

=====================Video Imaging Products
2-69

07112195-LDS.4316B-A

•

---- -- ----------~~-~

LF43168

-

==~~=~

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

EVEN-TAP FILTER

ODD-TAP FILTER

EVEN-TAP FILTER (NO DECIMATION)

DECIMATING, EVEN-TAP FILTER

Figure 5 shows the two possible
configurations when the device is
programmed as a decimating, evensymmetric coefficient filter_ The delay
length of the decimation registers will
be equal to the decimation factor that
the device is programmed for. Since
only four coefficients (effectively
eight) can be sent to the filter multipli-

ers on a clock cycle, it may be necessary (depending on the coefficient set)
to change the coefficients fed to the
multipliers on different CLK cycles for
filters with more than eight taps. Note
that for the odd-tap filter, the middle
coefficient of the coefficient set must
be divided by two to get the correct
result.

Odd-Symmetric Coefficient Filters

Figure 6 shows the two possible
configurations when the device is
programmed for odd-symmetric
coefficients. Note that odd-tap, oddsymmetric coefficient filters are not
possible.

===================== Video Imaging Products
2-70

07112195-LDS.43168-A

-

-- --------- --- -.......------ -

LF43168

DEVICES INCORPORATED

Dual8-Tap FIR Filter

Interleaved Coefficient Filters
Figure 7 shows the filter configuration
when the device is programmed for
interleaved coefficients. An interleaved coefficient set contains two
separate odd-tap, even-symmetric
coefficient sets which have been
interleaved together (see Figure 8). If
two data sets are interleaved into the
same serial data stream, they can both
be filtered by different coefficient sets
if the two coefficient sets are also
interleaved. The LF43168 is configured as an interleaved coefficient filter
by programming the device for
interleaved coefficient sets, evensymmetric coefficients, odd number of
filter taps, and data reversal disabled.
Note that coefficient 3, in Figure 7,
must be divided by two to get the
correct result.

N ~ Delay Length (Decimatiorl Factor)

DATA IN ---,---t~

COEF 1

--+---+1

COEF2 --+-----+--~

+-__

roEF3 _ _

~

___+-_-+

2

ODD·TAP INTERLEAVED FILTER

Asymmetric Coefficient Filters
It is possible to have asymmetric

coefficient filters. Asymmetric coefficient sets do not exhibit even or odd
symmetric properties. A 4-tap asymmetric filter is possible by putting the
device in even-tap, pass A mode and
then feeding the asymmetric coefficient set to the multipliers. An 8-tap
asymmetric filter is possible if the
device is clocked twice as fast as the
input data rate. It will take two eLK
cycles to calculate the output. On the
first eLK cycle, the reverse decimation
path is selected to feed data to the
filter multipliers. On the second eLK
cycle, the coefficients sent to the
multipliers are changed (if necessary)
and the forward decimation path is
selected to feed data to the filter
multipliers.

7 6 5 4 3 2 1

Odd-Tap, Even-Symmetric
Coefficient Set A

14131211 10 9 8 7 6 5 4 3 2

Interleaved Coefficient Set
I

II I

I

Consisting of Sets A and B

7 654 3 2
Odd-Tap, Even-Symmetric
Coefficient Set B

===================== Video Imaging Products
2-71

07l12/95-LDS.43168-A

LF43168
DEVICES INCORPORATED

Dual 8-Tap FIR Filter

Storage temperature ............................................. .......... ..................................................... -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V
Signal applied to high impedance output ....................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs.............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode
Active Operation, Commercial
Active Operation, Military

Symbol

Temperature Range (Ambient)
O°Cto +70°C
-55°C to +125°C

Supply Voltage
4.75 V ~ Vee ~ 5.25 V
4.50 V ~ Vee ~ 5.50 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., 10H = -2.0 mA

2.6

VoL

Output Low Voltage

Vee = Min., 10L = 4.0 mA

~H

Input High Voltage

~L

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground

~

VIN

loz

Output Leakage Current

Ground

~

VOUT

leel

Vee Current, Dynamic

lee2

Typ

Max

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Vee (Note 12)

±10

~

~

±10

~

(Notes 5,6)

300

mA

Vee Current, Quiescent

(Note?)

500

~

CIN

Input Capacitance

TA = 25°C, f = 1 MHz

12

pF

COUT

Output Capacitance

TA = 25°C, f = 1 MHz

12

pF

~

Vee (Note 12)

==================== Video Imaging Products
2·72

07/12/95-LDS.43168·A

.............. _--- .....-.-.--_-----""-""------......
---~~-

LF43168

-

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

..

ClK
INPUT~ --------------,I/~~~.Ir------------------------_t------------------------CONTROLS' ______________/ I ' ____
~------------------------

-J'-________________________

~-O

- - - - - - - - - - - - - -__________Jr~_____J.,~

__+_--~------~r_------------------------

+-------------------------

CIN9-0 ______________________________.....T~_ _ _ _ _ ___' "~_ _ _ _ _ _

tENAi

tDIS3

OUT27-0

______~X~______________
~·

HIGH IMPEDANCE

tD~

-{--------~*=-----------.X
~--------~

~-----

'includes INA9-o, INB9-0, CSEl4-o, ACCEN, MUX1-0, SHFTEN, FWRD, RVRS, and TXFR.

=====================Video Imaging Products
2-73

07/12/95-LDS.43168-A

-=-F::F!!=~
----- --.-.......,--

LF43168

-~---

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

ClK

_+--------------

INPUTS/ - - - - - - - - - - . . ~'---'---... ~------------_;_-----------CONTROLS' _ _ _ _ _ _ _/ " _ _
____________
-J'I~

As-o

------------....IT'-----/-,~-+_-,__---_If_------------

CINg-o _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.1'1''-_ _ _--/

tENA
_----tD-'S-3
-'X'--_______
-

OUT27-0 _ _ _

HIGH IMPEDANC':.

'------t-------------

--j

to

r::=

--{----~:c---------..X
~

_ _ _ __ J

~

__

'includes INAg-o, INBg-o, CSEl4-0, ACCEN, MUX1-0, SHFTEN, FWRD, RVRS, and TXFR_

====================== Video Imaging Products
2-74

0711 2/95-LDSA3 168-A

---------- -- -----------.....-.
-- ........-..~-~

LF4316a

--.-..

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.

Dual a-Tap FIR Filter

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified lOR and IOL at an
output voltage of VOR min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of lOR and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

5. Supply current for a given application can be accurately approximated
by:

b. Ground and Vee supply planes
must be brought directly to the DUT
socket or contactor fingers.

4

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

VCC

d.
}
~r

a. A 0.1 ~ ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary should be installed between device Vee
from those deSignated but operation is and the tester common, and device
guaranteed as specified.
ground and tester common.

NCV2 F

where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 Vof
Vee or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from

t--~--oOUTPUT

n+
D1

p-

-==~~~!!!!!l~~~
t

TRISTATE
OUTPUTS_

O.2V

O.2V

====================Video Imaging Products
2·75

07/12195-LDS.43168·A

•

-

- -.,--.,
- - -.-..--......
.....
_......--- -------------""-""---

LF4316a

DEVICES INCORPORATED

Dual a-Tap FIR Filter

84-pin

87654321M~~~OOMMnMM

GIN7
GINa
GINs
GIN4

•

74

AGGEN
Vee
GlK

GND

GIN3
GIN2
GIN1
GINo
INA9
INAB
INA7
INAa
INAs
Vee
INA4
INA3
INA2
INA1
INAo
INB9

RVRS
FWRD
SHFTEN
TXFR

GND
OEH

Top
View

31
32

54

mM • • ~.~~~aa«.~~~~W~~~

OUT27
OUT26
OUT2S
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT1B
OUT17
Vee

Plastic J-Lead Chip Carrier

(J3)

30 ns
22 ns
15 ns

LF43168JC30
LF43168JC22
LF43168JC15

==================== Video Imaging Products
2-76

07/12/9S-LDS.431a8-A

- --- ---------------------

LF43168

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

ORDERING INFORMATION
100-pin

ClN4

GND
GND
GIN3
ClN2

GINl
CINo

INA,
INA.
INA7

INA6
INA5
Vee
Vee
INA4
INA,
INA2
INAl

INAo
NG
NC
INB9
INB.
INS7

..

MUXl
MUXo

GIN.
NG
GIN?
NC
GIN6
CIN5

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Top
View

RVRS
NC
FWRD
SHFTEN
TXFR
ACCEN
Vee
Vee
ClK
GND
GND
OEH
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17

NC
Vee

Vee
GND
GND

Speed

Plastic Quad Flatpack
(Q2)

30 ns
22 ns
15 ns

LF43168QC30
LF43168QC22
LF43168QC 15

===================== Video Imaging Products
2-77

07/12/95-LDS.43168-A

LF43168
DEVICES INCORPORATED

Dual 8-Tap FIR Filter

84-pin
2

A

... , ..

'-'
, ...

3

4

5

I_I

0

, ... , ... ,

I_I

E

, ... GIN?
, ...

I_I

...

I_I

I_I

I_I

I_I

I_I

I_I

CIN6

CSElo

A6

As

,

...

I_I

I_I

CIN3

GND

I_I

I_I

I_I

I_I

Ao

I_I

\_J~

MUX1 MUXoSHFTEN

,.... , ....
,_I
,_I
, ... , ...
I_I
I_I

FWRD TXFR

I_I

Top View

I_I

elK

Through Package

I_I

, ... INA9
, ... INAe
, ...

, ... GND
, ... OEH
, ...

I_I

I_I

I_I

OUT26 OUT22 OUT2?

I_I

I_I

, ... I_I
, ... I_I
, ...
I_I

, INAs
,
I_I
I_I

INA?

OUT25 OUT23 OUT24

I_I

INA4

...

(i.e., Component Side Pinout)

, ... , ...

I_I

INAs

, I_I
,
I_I
...

INA2
K

11

, ... AGGEN
, ... IVee
, ...I

I_I

, ... GIN1
, ... GIN2
, ...

...

J

I_I

, ... , ... , ...

INA6
H

I_I

, ... ,A2... ,As...

Vee
G

I_I

GIN9 GSEl2 Vee

GINo

F

10

~

I_I
...

9

RVRS
,Ae... ,A?... ,A4... ,A1... GND
, ... WR
,.... , ....

CIN4

,

8

, ... , ... , ... , ... , ... , ... , ... , ... I, ...I , ..
I_I
I_I
I_I
I_I
I_I
I_I
I_I

GINs
C

7

I_I

CINe CSEl4 CSEL3 CSEl1
B

6

, ... , ... , ...

...

I_I

I_I

I_I

OUT20 OUT21

, ... I_I
, ...
I_I

I_I

, ... INAo
, , , INB3
, ... OEl
, OUT9
, , ... , ... OUT1?
, OUT19
,
I_I
I_I
I_I
I_I
I_I
I_I
I_I
I_I
I_I
I_I
I_I
...

...

...

...

...

...

...

, ... INB?
, ... GND
, ... INB2
, ... INBc
, ... Vee
, ... OUT130UT16
, ... , ... Vee
, ... OUT16
, .. INBe
, ..
I_I

INA1

L

'-'

INB9

I_I

I_I

I_I

I_I

I_I

INBs

INB4

INB1 OUT11 OUT10 OUT12 OUT14 OUT1S GND

30 ns
22 ns
15 ns

LF43168GC30
LF43168GC22
LF43168GC15

39 ns
30 ns
22 ns

LF43168GM39
LF43168GM30
LF43168GM22

39 ns
30 ns
22 ns

LF43168GMB39
LF43168GMB30
LF43168GMB22

I_I

I_I

'-'

I_I

INB6

===================== Video Imaging Products
2-78

07/12/95-LDS.4316B-A

.=. .=.=.=.
-= =-=::..:
------=-=:.......r

LF43881

-~---

8

DEVICES INCORPORATED

o 30 MHz Maximum Sampling Rate
o

o
o

o
o
o
o
o
o
o
o

240 MHz Multiply-Accumulate Rate
8 Filter Cells
8-bit Unsigned or Two's Complement
Data
8-bitUnsignedorTwo'sComplement
Coefficients
26-bit Data Outputs
Shift-and-Add Output Stage for
Combining Filter Outputs
Expandable Data Size, Coefficient
Size, and Filter Length
User-Selectable 2:1,3:1, or 4:1
Decimation
Available 100% Screened to
MIL-STD-883, Class B
Replaces Harris HSP43881 and
HSP43881/883
Package Styles Available:
• 84-pin Plastic LCC, J-Lead
• 10D-pin Plastic Quad Flatpack
CeramicPGA

The LF43881 is a video-speed digital
filter that contains eight filter cells
(taps) cascaded internally and a shiftand-add output stage. An 8 x 8
multiplier, three decimation registers,
and a 26-bit accumulator are contained in each filter cell. The output
stage of the LF43881 contains a 26-bit
accumulator which can add the
contents of any filter stage to the
output stage accumulator shifted right
by 8 bits. 8-bit unsigned or two's
complement format for data and
coefficients can be independently
selected.

X

8-bit Digital Filter

rate, a single LF43881 can process
larger filter lengths by using multiple
passes. The sampling rate can range
from 0 to 30 MHz. Over 1000 taps
may be processed without overflows
due to the architecture of the device.
The output sample rate can be reduced to one-half, one-third, or onefourth the input sample rate by using
the three decimation registers contained in every filter cell. Matrix
multiplication, N x N spatial correlations/ convolutions, and other 2-D
operations for image processing can
also be achieved using these registers.

Expanded coefficients and word sizes
can be processed by cascading multiple LF43881s to implement larger
filter lengths without affecting the
sample rate. By reducing the sample

DIN7·0

DIENB, CIENB,
ERASE, DCM,·o

TCS

TCCO

TCCI

COUTl·o

CIN7·0
ADR2·0

-i'-~

___1---""'+--~4---___1----+-+--~>----+---___+---...J

26

SHADD-----------------~
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~ OUTPUT

SENBH

STAGE

RESET--~--------------~
26

TO All CEllS
ClK - - -__ TO All REGISTERS

SUM25-O

=====================Video Imaging Products
2·79

08112/94-LDS.4388,·E

2

- .....- - -........-

- -........-------------- -......
-~-

LF43881

~----

DEVICES INCORPORATED

8 x 8-bit Digital Filter

CIENB.D

TCCI

DCMo.D

LD

C.TCCI

CREG

DCM1.D

LD
TRI-STATE BUFFERS
ON FILTER CELL 7 ONLY
- - - - - - - - - - - - - -I

D1 REG
C7-0

CIN7·0

TCCO
COUT7-O

a

7-0

COENB

I
1_____________ J

I
I
I
I
I
I
I
I
I

C

B
DIENB.D

TCS

LD

1-------

I
I
I
I

X REG
X8-O

DIN7·0

DCM1

I
I
I
I
I
I

DCM1.D

DCMo

DCMo.D

RESET

RESET.D

DIENB
CIENB

-------- I

DIENB.D
LATCHES

CIENB.D

ADRo

ADRo.D

ADR1

ADR1.D

ADR2

ADR2.D

ERASE

ERASE.D
RESET.D
ERASE.D

CELLn
CELLO
CELL 1
ADRo
ADR1

DECODER

ADR2

CELL 2
CELL3
CELLn

CELL4

Q

CELLS
CELL 6
CELL 7

AOUT2&-O
CLK
RESET.D

• TO ALL REGISTERS
• TO ALL REGISTERS (EXCEPT ACCUMULATOR AND T-REGISTER)

=====================Video Imaging Products
2-80

08/12/94-LDS.43881-E

=

..............

_-

~~=Ir!!!
=-~=..==
-~---

......

LF43881

DEVICES INCORPORATED

8 x 8-bit Digital Filter

FILTER CELL DESCRIPTION
8-bit coefficients are loaded into the
C register (CIN7-0) and are output as
COUT7-0 (the COENB signal enables
the COUT7-0 outputs). The path
taken by the coefficients varies
according to the decimation mode
chosen. With no decimation, the
coefficients move directly from the
C register, bypassing all decimation
registers, and are available at the
output on the following clock cycle.
When decimation is chosen, the
coefficient output is delayed by 1, 2,
or 3 clock cycles depending on how
many decimation registers the
coefficients pass through (D1, D2, or
D3). The number of decimation
registers the coefficients pass
through is determined by DCMI-O.
Refer to Table 1 for choosing a
decimation mode.

SHADD

ADR2·o.D
26

26

26

26

26

26

26

26

•

CEll RESULT

Q

MUX

o

26

OUTPUT
BUFFER
25-8

26

CIENB enables the C and D registers
for coefficient loading. The registers
are loaded on the rising edge of CLK
when CIENB is LOW. CIENB is
latched and delayed internally which
enables the registers for loading one
clock cycle after CIENB goes active
(loading takes place on the second
rising edge of CLK after CIENB goes
LOW). Therefore, CIENB must be
LOW one clock cycle before the
coefficients are placed on the CIN7-O
inputs. The coefficients are held when
CIENB is HIGH.
DIENB enables the X register for the
loading of data. The X register is
loaded on the rising edge of CLK
when DIENB is LOW. DIENB is
latched and delayed internally (loading takes place on the second rising
edge of CLK after DIENB goes LOW).
Therefore, DIENB must be LOW one
clock cycle before the data is placed on
the DIN7-O inputs. The X register is
loaded with all zeros when DIENB is
HIGH.
The output of the C register (C8-0) and
X register (X8-O) provide the inputs of
the 8 x 8 multiplier. The multiplier is
followed by two pipeline registers,

D

SENBl
SENBH
ClK ---.~ TO All REGISTERS
RESET.D

TRI-STATE
BUFFER
26

• TO All REGISTERS

M REGO and M REGl. The output of
the multiplier is sign extended and is
used as one of the inputs to the 26-bit
adder. The output of the 26-bit
accumulator provides the second
input to the adder. Both the accumulator and T register are loaded simultaneously with the output of the
adder.
The accumulator is loaded with the
output of the adder on every clock
cycle unless cleared. Clearing the
accumulator can be achieved using
two methods. The first method, when
both RESET and ERASE are LOW,
causes all accumulators and all

registers in the device to be cleared
together. RESET and ERASE are
latched and delayed internally causing the clearing to occur on the second
clock cycle after RESET and ERASE go
active.
The second method, when only
ERASE is LOW, clears a single accumulator of a selected cell. The cell is
selected using the ADR2-o inputs
(decoded to Cell n). ERASE is latched
and delayed internally causing the
clearing to occur on the second clock
cycle after ERASE goes active. Refer
to Table 2 for clearing registers and
accumulators.

=====================Video Imaging Products
2·81

08/12/94-LDS.43881-E

---- --......- -------_
..

--

~--

LF43881

--~--~--DEVICES INCORPORATED

8 x 8-bit Digital Filter
SIGNAL DEFINITIONS
Power

VccandGND
+5 V power supply. All pins must be
connected.
Clock

CLK - Master Clock
The rising edge of CLK strobes all
registers. All timing specifications are
referenced to the rising edge of CLK.
Inputs

DIN7-0 - Data Input
OUTPUT STAGE DESCRIPTION

multiplexer selects the contents of a
filter cell accumulator addressed by
ADRz-o. Otherwise, the output
multiplexer selects the contents of the
output buffer.

The 26-bit adder contained in the
output stage can add the contents of
any filter cell accumulator (selected by
ADRz-o) with the 18 most significant
bits of the output buffer. The result is If the same address remains on the
stored back into the output buffer.
ADRz-O inputs for more than one clock
The complete operation takes only one cycle, SUM25-O will not change to
clock cycle. The eight least significant reflect any updates to the addressed
cell accumulator. Only the result from
bits of the output buffer are lost.
the first selection of the cell (first clock
The Zero multiplexer is controlled by
cycle) will be output. This allows the
the SHADD input signal. This allows interface of slow memory devices
selection of either the 18 most signifiwhere the output needs to be active
cant bits of the output buffer or all
for more than one clock cycle. Normal
zeros for the adder input. When
FIR operation is not affected because
SHADD is LOW, all zeros will be
ADRz-o is changed sequentially.
selected. When SHADD is HIGH, the
18 most significant bits of the output
NUMBER SYSTEMS
buffer are selected enabling the shiftand-add operation. SHADD is
Data and coefficients can be reprelatched and delayed internally by one sented as either unsigned or two's
clock cycle.
complement numbers. The TCS and
TCCI inputs determine which of the
The output multiplexer is also contwo formats is to be used. All values
trolled by the SHADD input signal.
are represented as 9-bit two's compleThis allows selection of either a filter
ment numbers internally. The value
cell accumulator, selected by ADRz-O,
of the ninth bit is determined by the
or the output buffer to be output to
number system selected. The ninth bit
the SUM25-0 bus. Only the 26 least
is a sign extended bit when the two's
significant bits from either a filter cell
complement mode is chosen. When
accumulator or the output buffer are
the unsigned mode is chosen, the
output on SUM25-0. If SHADD is
ninth bit is zero.
LOW during two consecutive clock
cycles (low during the current and
previous clock cycle), the output

8-bit data is latched into the X register
of each filter cell simultaneously. The
TCS signal selects the appropriate
data format type. The DIENB signal
enables loading of the data.

CIN7-0 - Coefficient Input
8-bit coefficients are latched into the C
register of Filter Cell O. The TCCI
signal selects the appropriate coefficient format type. The CIENB signal
enables loading of the coefficients.
Outputs

SUM2S-0 - Data Output
The 26-bit result from an individual
filter cell will appear when ADR2-O is
used to select the filter cell result.
SHADD in conjunction with ADRz-O is
used to select the output from the
shift-and-add output stage.

COUT7-0 - Coefficient Output
The 8-bit coefficient output from
Filter Cell 7 can be connected to the
CIN7-0 coefficient input of the same
LF43881 to recirculate the coefficients.
COUT7-D can also be connected to the
CIN7-0 of another LF43881 to cascade
the devices. The COENB signal
enables the output of the coefficients.

====================Video Imaging Products
2-82

08/12/94-LDS.43881·E

-- - --- -- ..----.,
_--...--.

-...--.
-

LF43881

~-.-..-.~-~

-~---

DEVICES INCORPORATED

Controls

8 x 8-bit Digital Filter
CIENB - Coefficient Input Enable

TCS - Data Format Control

The CIENB input enables the C and D
registers of every filter cell. While
The TCS input determines the interCIENB is LOW, the C and appropriate
pretation of the input data. When
D registers are loaded with the
TCS is HIGH, two's complement
coefficient data on the rising edge of
arithmetic is used. When TCS is
CLK. While CIENB is HIGH, the
LOW, unsigned arithmetic is used.
contents of the C and D registers are
held and the CLK signal is ignored.
TCCI - Coefficient Input Format Control By using CIENB in its active state,
coefficient data can be shifted from
The TCCI input determines the
cell to cell. CIENB must be low one
interpretation of the coefficients.
clock cycle prior to presenting the
When TCCI is HIGH, two's complecoefficient data on the CIN7..(J input
ment arithmetic is used. When TCCI
since it is latched and delayed interis LOW, unsigned arithmetic is used.
nally.

TCCO - Coefficient Output Format

COENB - Coefficient Output Enable
The TCCO output shows the format of
The COENB input enables the
the COUT7-0 coefficient output.
TCCO follows the TCCI input. When COUT7-0 and TCCO outputs. When
COENB is LOW, the outputs are
cascading multiple LF43881s, the
TCCO output of one device should be enabled. When COENB is HIGH, the
outputs are placed in a high-impedconnected to the TCCI input of
ance state.
another device. The COENB signal
enables TCCO.
DCMI-0 - Decimation Control
DIENB - Data Input Enable
The DIENB input enables the X
register of every filter cell. While
DIENB is LOW, the X registers are
loaded with the data present at the
DIN7-0 inputs on the rising edge of
CLK. While DIENB is HIGH, all bits
of DIN7-0 are forced to zero and a
rising edge of CLK will load the X
register of every filter cell with all
zeros. DIENB must be low one clock
cycle prior to presenting the input
data on the DIN7-0 input since it is
latched and delayed internally.

The DCMI-O inputs select the number of decimation registers to use
(Table 1). Coefficients are passed
from one cell to another at a rate
determined by DCMI-O. When no
decimation registers are selected,
the coefficients are passed from cell
to cell on every rising edge of CLK
(no decimation). When one decimation register is selected, the coefficients are passed from cell to cell on
every other rising edge of CLK (2:1
decimation). When two decimation
registers are selected, the coefficients are passed from cell to cell on
every third rising edge of CLK (3:1
decimation) and so on. DCMI-O is
latched and delayed internally.

ADR2-0 - Cell Accumulator Select
The ADR2-0 inputs select which cell's
accumulator will available at the
SUM25-0 output or added to the
output stage accumulator. In both
cases, ADR2-D is latched and delayed
by one clock cycle. If the same
address remains on the ADR2-D inputs
for more than one clock cycle,
SUM25-0 will not change if the contents of the accumulator changes.
Only the result from the first selection
of the cell (first clock cycle) by ADR2-o
will be available. ADR2-o is also used
to select which accumulator to clear
when ERASE is LOW.

SENBH - MSB Output Enable
When SENBH is LOW, SUM25-16 is
enabled. When SENBH is HIGH,
SUM25-16 is placed in a high-impedance state.

SENBL - LSB Output Enable
When SENBL is LOW, SUM15-0 is
enabled. When SENBL is HIGH,
SUM15..(J is placed in a high-impedance state.

RESET - Register Reset Control
When RESET is LOW, all registers are
cleared simultaneously except the cell
accumulators. RESET can be used
with ERASE to clear all cell accumulators. RESET is latched and delayed
internally. Refer to Table 2.

ERASE - Accumulator Erase Control
When ERASE is LOW, the cell accumulator specified by ADR2-o is
cleared. When RESET is LOW in
conjunction with ERASE, all cell
accumulators are cleared. Refer to
Table 2.

====================Video Imaging Products
2·83

08/12/94-LDS.43881·E

-_---- -- .._.._--...........-

~~~-~

~

-........-.-

-~--

LF43881

........

DEVICES INCORPORATED

8 x 8-bit Digital Filter

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V
Signal applied to high impedance output ....................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs........................................ ...................................................................... 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial
Active Operation, Military

Symbol

Supply Voltage

O°C to +70°C

4.75 V:::; Vee:::; 5.25 V

-55°C to + 125°C

4.50 V :::; Vee:::; 5.50 V

Min

Parameter

Test Condition

VoH

Output High Voltage

Vee = Min., IOH = -400 !LA

VoL

Output Low Voltage

Vee = Min., IOL = 2.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

loz

Typ

Max

2.6

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground:::; VIN :::; Vee (Note 12)

±10

!LA

Output Leakage Current

(Note 12)

±10

!LA

leel

Vee Current, Dynamic

(Notes 5,6)

160

mA

lee2

Vee Current, Quiescent

(Note 7)

750

!LA

CIN

Input Capacitance

TA=25°C,f=1 MHz

10

pF

COUT

Output Capacitance

TA = 25°C, f = 1 MHz

10

pF

=====================Video Imaging Products
2-84

08112194-LDS.43881·E

........ ------- -........
-------

--. ~ -~--.,
.....-_-...
--.-..

LF43881

DEVICES INCORPORATED

8 x 8-bit Digital Filter

Ipw
~

CLK

Ipw

IH

~Is

DIN,.,
CIN,·,

CONTROLS'
HIGH IMPEDANCE

OUTPUTSt

_

loo~

------I

tODS

OUTPUT ENABLESt

r--

tDIS---l

C

tENA

-----------'~-----,
'includes DIENB, CIENB, ERASE, RESET, TCS, TCCI, SHADD, DCM1-O, and ADR,-O.
tincludes TCCO, SUM,.·" and COUT,·,.
tincludes SENBL, SENBH, and COENB.

===================== Video Imaging Products
2-85

08112194--LDS.43881-E

--....-..
--- -----------....-..

~ -~--~--~--~---

LF43881

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for ex-.
tended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

8 x 8-bit Digital Filter

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 rnA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vee

d.
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast tum-on/tum-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

~r

a. A 0.1 ~ ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
ground and tester common.
anteed as specified.
5. Supply current for a given applica- b. Ground and Vee supply planes
tion canbe accurately approximated by: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.
where

4

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 20 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case rebut not 100% tested.
quirements of all parts. Responses from
the internal circuitry are specified from

t--~-o OUTPUT

n+
01

p-

TRISTATE -===~~~~~${
OUTPUTS t
02V

O.2V

=====================Video Imaging Products
2·86

08/12/94-LDS.43881-E

---- - ----....-..

--~-~ -~------~---~---

-

LF43881

DEVICES INCORPORATED

8 x 8-bit Digital Filter

84-pin

SUM23
SUM22
Vee
SUM2'
SUM20
SUM,.
SUM,s
GND
SUM17
SUM'6
Vee
SUM'5
SUM'4
SUM'3
SUM'2
GND
SUM11
SUM,o
SUM.
SUMs
~~

11109 8 7 6 5 4 3 2 184838281807978777675
12
•
74
73

Top
View

~

~

COUT6
COUT7
GND
TCCO
COENS
Vee
ERASE
RESET
DIENS
TCS
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN,
DINo
CIENS
TCCI
Vee

•

~M~~~~~~~Ga#e~Q~.w~~~

50
40
33
25

ns
ns
ns
ns

LF43881 JC50
LF43881 JC40
LF43881 JC33
LF43881JC25

=====================Video Imaging Products
2-87

08/12/94-LDS.43881-E

- -------- ------_
.....
..
_-----~---

-

LF43881

DEVICES INCORPORATED

8 x 8-bit Digital Filter

100-pin

DCM,
SUM2.
GND
GND
SUM2a
SUM22

COUT.
COUTs

Vee
Vee
COUTs
COUT?
GND
GND
TCCO
COENB

vee
Vee
SUM2'
SUM20
SUM,.
SUM,.
GND
GND
SUM17
SUM16

Vee
vee

Vee
vee

Top
View

SUM,s
SUM,.
SUM,a
SUM12

GND
SUM11
SUM,o
SUM.
SUM.
SUM7
NC
SUM.

50
40
33
25

ns
ns
ns
ns

ERASE
RESET
DIENB
TCS
DIN7
DINs
DINs
DIN.
DINa
DIN2
DIN'
DINo
CIENB
TCCI

Vee
CIN7
CINo
GND

LF43881 QC50
LF43881 QC40
LF43881 QC33
LF43881 QC25

====================Video Imaging Products
2-88

08/12/9'-LDS.43881-E

LF43881
DEVICES INCORPORATED

8 x 8-bit Digital Filter

84-pin
2
A
B
C
D
E

F
G

... ,...

4

3

5

6

7

J

10

11

, ...

,....

,.....

,....

,....

,....

,....

,.....

,.....

,.....

,

' .....'

,

,

' .....'

' .....'

' .....'

' .....'

' .....'

,_I
, , " , , , , , , '.....' , , , , '.....' '.....' '.....'
V";c cOOr7 TCCo m res DIN1 DiN2 ems CIN7 CINs CIN4
,..... , ....
,..... ,_,
,. ....
,..... ,..... , ....
,_I
,
, '.....'
,
,
'
.....
'
'
.....
'
DIENB DINs DIN4
ciNs CIN3
COUTs COUTs
,

I

,

,

,

GND coENB Vcc RESET DiN7 DINs DlN3 DINo rcci Vcc GND
,..... ,..... ,.... ,.... ,.... ,.... ,..... ,..... ,..... ,.... , ....

,,....., ,,. ....,
COUr3 cOOr4
,,....., ,,....., ,, ....,

•

,..... ,_I
, ....
,_I

,.....

CIN1 ciNo SENBL
,.... ,..... ,. ....

,_I ,_I ,_)

Through Package

GND COUTo SHADD
,..... ,.... ,. ....

(i.e., Componen1 Side Pinout)

,_I ,_I \,. . .J
,.... ,_I
, ....
,_I

CIN2 Vee
,.... ,. ....

'.....' , , "

Top View

cOOr1 GND COUr2
,..... ,..... , ....

,_I '_' ,. . . J

SUMo Vcc GND
,.... ,..... ,. ....
,

,

' .....'

' .....1

SUM1 SUM3 SUM2

ADR2 DCMo CLK

H

9

8

,. ....

,. ....
,
,
'
.....'
SUMs SUM4
ADR1 ADRo
,.....
,....
,
....
,....
,
....
,..... ,. ....
,, ,, ,,
,
,
'
.....'
'Vcc
.....' SUM2s
'.....'
S~ SUM17 SUM1S
SUM? GND
,..... ,..... ,..... ,.... ,..... ,..... ,.... ,..... ,..... ,..... ,.
'.....' '.....' '.....' '.....' " , , , , , , " '.....' '.....'
SENBH SlJM24 GND Vcc SUM19 GND SUM1S SUM12 SUMIO SUMs SUM6
....

K
L

,...

,.....

,.....

,.....

,....

,....

,....

,.....

,.....

,.....

, ...

'...,1 ,_I ,_, ,_I \,_, '_. '. . . ' ,_I ,. . . .1 ,_I '...,'
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 Vcc SUM13 GND SUM11 SUMs

50 ns
40 ns
33 ns
25 ns

LF43881 GC50
LF43881 GC40
LF43881 GC33
LF43881 GC25

50 ns
40 ns
33 ns

LF43881GM50
LF43881GM40
LF43881GM33

50 ns
40 ns
33 ns

LF43881GMB50
LF43881GMB40
LF43881GMB33

===================== Video Imaging Products
2-89

08/12/94-LDS.43881·E

DEVICES INCORPORATED

- ----------

-- - - - =-:....=:.....:=::.........

LF43891

-~---

~

o
o
o
o
o

o
o
o
o
o

o
o

30 MHz Maximum Sampling Rate
240 MHz Multiply-Accumulate Rate
8 Filter Cells
8-bit Unsigned or 9-bit Two's
Complement Data
8-bit Unsigned or 9-bit Two's
Complement Coefficients
26-bit Data Outputs
Shift-and-Add Output Stage for
Combining Filter Outputs
Expandable Data Size, Coefficient
Size, and Filter Length
User-Selectable 2:1, 3:1, or 4:1
Decimation
Available 100% Screened to
MIL-STD-883, Class B
Replaces Harris HSP43891 and
HSP43891/883
Package Styles Available:
• 84-pin Plastic LCC, J-Lead
• 100-pin Plastic Quad Flatpack
CeramicPGA

9 x 9-bit Digital Filter

The LF43891 is a video-speed digital
rate, a single LF43891 can process
filter that contains eight filter cells
larger filter lengths by using multiple
(taps) cascaded internally and a shift- passes. The sampling rate can range
from 0 to 30 MHz. Over 1000 taps
and-add output stage. A 9 x 9 multiplier, three decimation registers, and a may be processed without overflows
26-bit accumulator are contained in
due to the architecture of the device.
each filter cell. The output stage of the
LF43891 contains a 26-bit accumulator The output sample rate can be reduced to one-half, one-third, or onewhich can add the contents of any
fourth the input sample rate by using
filter stage to the output stage accuthe three decimation registers conmulator shifted right by 8 bits. 8-bit
tained in every filter cell. Matrix
unsigned or 9-bit two's complement
format for data and coefficients can be multiplication, N x N spatial correlations/ convolutions, and other 2-D
independently selected.
operations for image processing can
Expanded coefficients and word sizes also be achieved using these registers.
can be processed by cascading multiple LF43891s to implement larger
filter lengths without affecting the
sample rate. By reducing the sample

DIENB, CIENB,
ERASE, DCM,-o

DIN8-0

CINs-o

COUTs-o

ADR2~-r~*-~----~~----~~------*-r-----~~----~~------*-+-----~

SHADD--------------------------------~

SENBl ________________________________~ OUTPUT
SENBH
STAGE
RES8---.----------------------------~

2B

TO All CEllS
ClK - - - - - - _ . TO All REGISTERS

SUM25~

=====================Video Imaging Products
2-91

08112194-LDS.4389'-E

•

LF43891
DEVICES INCORPORATED

9 x 9-bit Digital Filter

CIENB.D

DCMo.D

DCM1.D

LD

LD

LD

LD

TRI-STATE BUFFER
ON FILTER CELL 7 ONLY

r-- -------- ---I

Ca·o

CINa.., -----~ C REG ~~';""-~D1REG

1

f-------~o

~---~---~o

COUTa-o
COENB

1

1
1
1
1

1

~ _ ____________ J

a..,

DIENB.D - - - - - - -

------LD
DINa-o _ _ _ _ _

~

X REG

r-___________________

~X~

_______

--------

_+--~

1
1
1
1
1
1
1

1
1

1
1
1
1
1

1
1
1
1

1
1
1

DeMI

DCM1.D

1
1

DCMo

DCMo.D

1
1

RESET

RESET.D

DIENB

DIENB.D

CIENB

LATCHES

CIENB.D

ADRo

ADRo.D

ADR,

ADR,.D

ADR2

ADR2.D

ERASE

I

- ______ 11

ERASE.D
RESET.D
ERASE.D

CELLn
CELLO
CELL 1
ADRo
ADR'

DECODER

ADR2

CELL 2
CELL 3
CELL 4

CELLn

Qt---~

CELLS
CELL 6
CELL 7

AOUT25-0
CLK
RESET.D

----~.~TO

ALL REGISTERS

• TO ALL REGISTERS (EXCEPT ACCUMULATOR AND T-REGISTER)

===================== Video Imaging Products
2-92

08/12194-lDS.43891-E

LF43891
DEVICES INCORPORATED

9 x 9-bit Digital Filter

FILTER CELL DESCRIPTION

9-bit coefficients are loaded into the
C register (CINB-O) and are output as
COUTB-O (the COENB signal enables
the COUTB-O outputs). The path
taken by the coefficients varies
according to the decimation mode
chosen. With no decimation, the
coefficients move directly from the
C register, bypassing all decimation
registers, and are available at the
output on the following clock cycle.
When decimation is chosen, the
coefficient output is delayed by 1, 2,
or 3 clock cycles depending on how
many decimation registers the
coefficients pass through (D1, D2, or
D3). The number of decimation
registers the coefficients pass
through is determined by DCMI-O.
Refer to Table 1 for choosing a
decimation mode.

SHADD

ADR2-0.D
26

26

26

26

26

26

26

26

•

CEll RESULT

Q

MUX

a

26

OUTPUT
BUFFER
25-8

26

CIENB enables the C and D registers
for coefficient loading. The registers
are loaded on the rising edge of CLK
when CIENB is LOW. CIENB is
latched and delayed internally which
enables the registers for loading one
clock cycle after CIENB goes active
(loading takes place on the second
rising edge of CLK after CIENB goes
LOW). Therefore, CIENB must be
LOW one clock cycle before the
coefficients are placed on the CINB-O
inputs. The coefficients are held when
CIENB is HIGH.
DIENB enables the X register for the
loading of data. The X register is
loaded on the rising edge of CLK
when DIENB is LOW. DIENB is
latched and delayed internally (loading takes place on the second rising
edge of CLK after DIENB goes LOW).
Therefore, DIENB must be LOW one
clock cycle before the data is placed on
the DINB-O inputs. The X register is
loaded with all zeros when DIENB is
HIGH.
The output of the C register (0-0) and
X register (XB-O) provide the inputs of
the 9 x 9 multiplier. The multiplier is
followed by two pipeline registers,

TRI-STATE
BUFFER
ClK

• TO All REGISTERS

RESET.D

• TO All REGISTERS

M REGO and M REG1. The output of
the multiplier is sign extended and is
used as one of the inputs to the 26-bit
adder. The output of the 26-bit
accumulator provides the second
input to the adder. Both the accumulator and T register are loaded simultaneously with the output of the
adder.
The accumulator is loaded with the
output of the adder on every clock
cycle unless cleared. Clearing the
accumulator can be achieved using
two methods. The first method, when
both RESET and ERASE are LOW,
causes all accumulators and all

26

registers in the device to be cleared
together. RESET and ERASE are
latched and delayed internally causing the clearing to occur on the second
clock cycle after RESET and ERASE go
active.
The second method, when only
ERASE is LOW, clears a single accumulator of a selected cell. The cell is
selected using the ADR2-o inputs
(decoded to Cell n). ERASE is latched
and delayed internally causing the
clearing to occur on the second clock
cycle after ERASE goes active. Refer
to Table 2 for clearing registers and
accumulators.

=====================Video Imaging Products
2-93

08/12/94-LDS.43891-E

LF43891
DEVICES INCORPORATED

9 x 9-bit Digital Filter
SIGNAL DEFINITIONS
Power

VccandGND
+5 V power supply. All pins must be
connected.
Clock

CLK - Master Clock
The rising edge of CLK strobes all
registers. All timing specifications are
referenced to the rising edge of CLK
Inputs
DIN8-0 - Data Input
OUTPUT STAGE DESCRIPTION

cycles (low during the current and
previous clock cycle), the output
multiplexer selects the contents of a
filter cell accumulator addressed by
ADR2-o. Otherwise, the output
multiplexer selects the contents of the
output buffer.

The 26-bit adder contained in the
output stage can add the contents of
any filter cell accumulator (selected by
A:DR2-0) with the 18 most significant
bIts of the output buffer. The result is
stored back into the output buffer.
The complete operation takes only one If the same address remains on the
clock cycle. The eight least significant ADR2-O inputs for more than one clock
cycle, SUM25-O will not change to
bits of the output buffer are lost.
reflect any updates to the addressed
The Zero multiplexer is controlled by
cell accumulator. Only the result from
the SHADD input signal. This allows the first selection of the cell (first clock
selection of either the 18 most significycle) will be output. This allows the
cant bits of the output buffer or all
interface of slow memory devices
zeros for the adder input. When
where the output needs to be active
SHADD is LOW, all zeros will be
for more than one clock cycle. Normal
selected. When SHADD is HIGH, the FIR operation is not affected because
18 most significant bits of the output
ADR2-O is changed sequentially.
buffer are selected enabling the shiftand-add operation. SHADD is
latched and delayed internally by one NUMBER SYSTEMS
clock cycle.
Data and coefficients can be represented as either 8-bit unsigned or 9-bit
The output multiplexer is also contwo's complement numbers. All
tro~ed by the SHADD input signal.
values are represented as 9-bit two's
This allows selection of either a filter
complement numbers internally. If
cell accumulator, selected by ADR2-O,
the most significant or sign bit is a
or the output buffer to be output to
zero, the multiplier can multiply 8-bit
the SUM25-0 bus. Only the 26 least
unsigned numbers.
significant bits from either a filter cell
accumulator or the output buffer are
output on SUM25-0. If SHADD is
LOW during two consecutive clock

9-bit data is latched into the X register
of each filter cell simultaneously. The
DIENB signal enables loading of the
data.
CIN8-O - Coefficient Input
9-bit coefficients are latched into the C
register of Filter Cell O. The CIENB
signal enables loading of the coefficients.
Outputs

SUM25-0 - Data Output
The 26-bit result from an individual
filter cell will appear when ADR2-O is
used to select the filter cell result.
SHADD in conjunction with ADR2-o is
used to select the output from the
shift-and-add output stage.

COUT8-0 - Coefficient Output
The 9-bit coefficient output from
Filter Cell 7 can be connected to the
CINs-o coefficient input of the same
LF43891 to recirculate the coefficients.
COUTs-o can also be connected to the
CINs-O of another LF43891 to cascade
the devices. The COENB signal
enables the output of the coefficients.

==================== Video Imaging Products
2-94

08/12/94-LDS.43891-E

--

....-..

......

....-..-....-..

--~-

-~---=-:..=~==--

LF43891

-~---

DEVICES INCORPORATED

9 x 9-bit Digital Filter

Controls

DCMI-0 - Decimation Control

SENBH - MSB Output Enable

DIENB - Data Input Enable

The DCMI-O inputs select the number of decimation registers to use
(Table 1). Coefficients are passed
from one cell to another at a rate
determined by DCMI-O. When no
decimation registers are selected,
the coefficients are passed from cell
to cell on every rising edge of CLK
(no decimation). When one deci~a
tion register is selected, the coefflcients are passed from cell to cell on
every other rising edge of C~K (~:1
decimation). When two deClmatIon
registers are selected, the coefficients are passed from cell to cell on
every third rising edge of CLK (~:1
decimation) and so on. DCMI-O IS
latched and delayed internally.

When SENBH is LOW, SUM25-16 is
enabled. When SENBH is HIGH,
SUM25-16 is placed in a high-impedance state.

The DIENB input enables the X
register of every filter cell. While
DIENB is LOW, the X registers are
loaded with the data present at the
DINs-o inputs on the rising edge of
CLK. While DIENB is HIGH, all bits
of DINs-O are forced to zero and a
rising edge of CLK will load the X
register of every filter cell with all
zeros. DIENB must be low one clock
cycle prior to presenting ~e inr~t
data on the DINs-o input smce It IS
latched and delayed internally.

CIENB - Coefficient Input Enable
The CIENB input enables the C and D
registers of every filter cell. While
CIENB is LOW, the C and appropriate
D registers are loaded with the
coefficient data on the rising edge of
CLK. While CIENB is HIGH, the
contents of the C and D registers are
held and the CLK signal is ignored.
By using CIENB in its ac~ve state,
coefficient data can be shifted from
cell to cell. CIENB must be low one
clock cycle prior to presenting the
coefficient data on the CINs-o input
since it is latched and delayed internally.

COENB - Coefficient Output Enable
The COENB input enables the
COUTs-o output. When COENB is
LOW, the outputs are enabled. When
COENB is HIGH, the outputs are
placed in a high-impedance state.

ADR2-O - Cell Accumulator Select

SENBL - LSB Output Enable
When SENBL is LOW, SUM15-O is
enabled. When SENBL is HIGH,
SUM15-0 is placed in a high-impedance state.

RESET - Register Reset Control
When RESET is LOW, all registers are
cleared simultaneously except the cell
accumulators. RESET can be used
with ERASE to clear all cell accumulators. RESET is latched and delayed
internally. Refer to Table 2.

The ADR2-o inputs select which cell's ERASE - Accumulator Erase Control
accumulator will available at the
When ERASE is LOW, the cell accuSUM25-0 output or added to the
mulator specified by ADR2-O is
output stage accumulator. In both
cleared. When RESET is LOW in
cases, ADR2-O is latched and delayed
conjunction with ERASE, all cell
by one clock cycle. If the same.
accumulators are cleared. Refer to
address remains on the ADR2-0 mputs
Table 2.
for more than one clock cycle,
SUM25-0 will not change if the contents of the accumulator changes.
Only the result from the first selection
of the cell (first clock cycle) by ADR2-O
will be available. ADR2-O is also used
to select which accumulator to clear
when ERASE is LOW.

=========================== Video Imagin~8/~/~~L~s~~9~~
2-95

•

_= - ----.......

~ II"!!!=~

LF43891

~------...-~
-~
DEVICES INCORPORATED

9 x 9-bit Digital Filter

Storage temperature ............................................................................................................ -65°C to +150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V
Signal applied to high impedance output ....................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs.............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial
Active Operation, Military

Symbol

Supply Voltage

O°C to +70°C

4.75 V::; Vee::; 5.25 V

-55°C to + 125°C

4.50 V ::; Vee::; 5.50 V

Min

Parameter

Test Condition

VoH

Output High Voltage

Vee = Min., IOH = -400 IJA

VoL

Output Low Voltage

Vee = Min., IOL = 2.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

loz

Typ

Max

2.6

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground::; VIN ::; Vee (Note 12)

±10

IJA

Output Leakage Current

(Note 12)

±10

IJA

lee1

Vee Current, Dynamic

(Notes 5, 6)

160

mA

lee2

Vee Current, Quiescent

(Note 7)

750

IJA

CIN

Input Capacitance

TA = 25°C, f = 1 MHz

10

pF

COUT

Output Capacitance

TA = 25°C, f = 1 MHz

10

pF

===================== Video Imaging Products
2·96

08/12/94-LDS.43891·E

-

- - -------- --,.,------ ...-.--~

LF43891

--.-..

DEVICES INCORPORATED

9 x 9-bit Digital Filter

I-----------+------+-----+----+----+----+----+----+---r---------l •

Ipw
ClK
~Is

IH

IPW

DINs-o
CINs-o

CONTROLS'
HIGH IMPEDANCE

OUTPUTSt

C
----------'~-_IOO~----l
tODS

OUTPUT ENABlES*

r--

tDIS----l

tENA

'includes DIENB, CIENB, ERASE, RESET, SHADD, DCM,-o, and ADR,-o.
tincludes SUM25-O and COUTs-o.
*includes SENBl, SENBH, and COENB.

====================Video Imaging Products
2-97

OB/12/94-LDS.43891-E

LF43891
DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

9 x 9-bit Digital Filter

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 rnA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 m V
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vee

d.
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

~n

a. A 0.1 J.LF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
ground and tester common.
anteed as specified.
5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated by: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.
where

4

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

+--...,...-0 OUTPUT

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 20 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the extervee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case re8. These parameters are guaranteed
quirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

n+
D1

po-

-===~~~~~#
,

TRISTATE
OUTPUTS _

O.2V

0.2 V

==================== Video Imaging Products
2·98

08/12/94--LDS.43891·E

LF43891
DEVICES INCORPORATED

9 x 9-bit Digital Filter

84-pin

SUM23
SUM22

11109 8 7 6 5
12

4 3 2

184838281807978777675
•
74
73

Vee
SUM2'
SUM20
SUM,.
SUM,s
GND

•

Vee

SUM'7
SUM'6

ERASE
RESET
DIENB
DINs
DIN7
DIN6
DINs
DIN.
DIN3
DIN2
DIN,
DINa
CIENB
CINs

Top
View

Vee
SUM,s
SUM,.
SUM'3
SUM'2
GND
SUM"
SUM,o
SUM.
SUMs
W~

COUT6
COUT7
GND
COUTs
COENB

M

~

Vee

.M~~~~~.~Ga"e~Q~.~~~~

50
40
33
25

ns
ns
ns
ns

LF43891 JC50
LF43891 JC40
LF43891 JC33
LF43891JC25

===================== Video Imaging Products
2-99

08/12/94-LDS .•389'·E

LF43891
DEVICES INCORPORATED

9 x 9-bit Digital Filter

~r

100-pin

0_

o.

g

~Z88~~CC~~~<88
cczzuc

~~
~cc

§§

~w
~
OOZZOO
mW»«~~C~ffiffi~~G~ou>oooo~

50
40
33
25

ns
ns
ns
ns

LF43891 QC50
LF43891 QC40
LF43891 QC33
LF43891 QC25

====================Video Imaging Products
2-100

08/12/9.-LDS.43891-E

-

- ..-..............
- --------_----~------

LF43891

-~---

DEVICES INCORPORATED

9 x 9-bit Digital Filter

84-pin

A
B

c
D

~,....

2

3

4

5

6

7

8

9

"

"

"

"

"

"

"

"

" I \,...I \" I

,...

\

,--I
Top View

,...

, __I

,...

, __I

"

, __•

,...I

\

,...I

\

"

L

" I ," I

\

" I ,"__I ,,__...I

,

Through Package

(i.e., Component Side Pinout)

SUM> Vce GND

"

\ __1

' __I

ADR2 DCMo CLK

SUMI

" 1 ,"__I

,

sUMs

"

' __I

,...I

\

,...I

\

SUM2

"

, __I

SUMs SUM4

,...
,--I

" ,,__...,--I
Vee SUM2s

K

•

CIN1 ciNo SENSL

H

J

, ....

CiN2 Vee

GND COUTo SHADD
G

"

," I
," I
," I
," I
\" I
\" I
\" I
\" I
\" I
\" I
\"
.....'
vec COUr7 coUrs ~ DiNa DiNl DiN2 ems ciN? ciNs CIN4
," I
,,...
__I
,"
__I
," I
,, ...I
\" I
\"
.....'
cOOr5 cOOrs
riiEfu! DIN5 DIN4
ciNs CIN3
...1
\" I
\,__
\" I
\" I

COUrl GND cOOr2

F

11

~N~ ~~8 ~e~ R~f~ ~iN~ ~iN~ ~iN13 ~iNlo ~iN~ ~e~ ~N~

C00r3 cOOr4
E

10

,...I

,

,...

\ __1

,...I

\

"I

\

,...I

,

sEiiR
S~
,.... ,...

,...I

\

,...I

\

, ...

, __I

SUM7 GND

,...

, __I

, ...

, __I

GND Vce SUM19 GND SUM15 SUM12 SUMIO SUMs SUMs
,... ,... ,... ,... ,... ,... ,... ,... , ....
1 \__1 \__1 \ I \ I \ I \ I \ I \ I
DCMl SUM23 SUM22 SUM2t SUMIS SUM14 Vee SUM13 GND SUMll SUM9

,_I \__

,_I

50 ns
40 ns
33 ns
25 ns

LF43891 GC50
LF43891 GC40
LF43891 GC33
LF43891 GC25

50 ns
40 ns
33 ns

LF43891 GM50
LF43891 GM40
LF43891 GM33

50 ns
40 ns
33 ns

LF43891GMB50
LF43891GMB40
LF43891GMB33

==================== Video Imaging Products
2·101

08/12194-LDS.43891·E

DEVICES INCORPORATED

- .- - --

LF 48212

Lu~ic;

-~--~

12

DEVICES INCORPORATED

o 40 MHz Data and Computation

o
o
o
o

o

Rate
Two's Complement or Unsigned
Operands
On-board Programmable Delay
Stages
Programmable Output Rounding
Replaces Harris HSP48212
Package Styles Available:
• 68-pin Plastic LCC, J-Lead
• 64-pin Plastic Quad Flatpack

The LF48212 is a high-speed video
alpha mixer capable of mixing video
signals at real-time video rates. It
takes two 12-bit video signals and
mixes them together using an alpha
mix factor. Alpha determines the
weighting that each video signal
receives during the mix operation.
The input video data can be in either
unsigned or two's complement
format, but both inputs must be in the

ct11-0

X

12-bit Alpha Mixer

same format. Independently controlled programmable delay stages are
provided for the input and control
signals to allow for allignment of
•
input data if necessary. The delay
stages can be programmed to have
from 0 to 7 delays. The 13-bit output
of the alpha mixer is registered with
three-state drivers and may be
rounded to 8, 10, 12, or 13-bits.

DINA11-o

DINB11-0

BYPASS
DEL
LD

CLK _ _
MIXEN _ _
OE _ _

TC

RND1-0

NOTE:

NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS.

DOUT12·0

===================== Video Imaging Products
2-103

OB/28J95-LDS.4S212-8

--

- -- ---------------.-.-- .-.....--.-~

LF48212

DEVICES INCORPORATED

12 x 12-bit Alpha Mixer

SIGNAL DEFINITIONS
Power

VccandGND

111 10 9 8 7 6 5 4 3 2
0
20 2-1 2-2 2-3 2-4 2-5 2 6 27 2 8 2921°211

+S V power supply. All pins must be
connected.
Clock

CLK - Master Clock

Outputs

The rising edge of CLK strobes all
enabled registers except for the Delay
Control Register.

DOUT12-0 - Data Output
DOUT12-0 is the 13-bit registered data
output port.

Inputs

Controls

DINAll-0 - Pixel Data Input A

TC - Data Format Control

DINAll-O is one of the 12-bit registered data input ports. Data is latched
on the rising edge of CLK.

TC determines if the input data is in
unsigned or two's complement
format. If TC is LOW, the data is in
two's complement format. If TC is
HIGH, the data is in unsigned format.
Data present on TC is latched on the
rising edge of CLK. TC only affects
the data that is being latched into the
LF48212. Changing TC does not affect
internal data already in the pipeline.

DINBll-0 - Pixel Data Input B
DINBll-O is the other 12-bit registered
data input port. Data is latched on the
rising edge of CLK.

all-0 - Alpha Mix Input

the Delay Control Register with the
appropriate value. Note that this
signal is not intended to change
during active operation of the
LF48212.

RND1-O - Output Rounding Control

all-O determines the weighting
MIXEN - Alpha Mix Input Enable
applied to the data input signals
before being mixed together. DINAll-O When HIGH, data on all-O is latched
and DINBll-O receive weightings of a
into the LF48212 on the rising edge of
and 1.0 - a respectively. all-O is
CLK. When LOW, data on all-O is not
unsigned and restricted to the range of latched and the last value loaded is
oto 1.0. Figure 1 shows the data
held as the alpha mix value.
format for all-O. If a value greater
LD - Load Strobe
than 1.0 is latched into the Alpha Mix
Input, internal circuitry will force the
The rising edge of LD latches the data
value to be equal to 1.0. Data is
on DEL into the Delay Control Register.
latched on the rising edge of CLK.
BYPASS - Bypass Delay Stage Control
DEL - Delay Data Input
The BYPASS control is used to bypass
DEL is used to load the Delay Control the internal programmable delay
Register. The Delay Control Register
stages. When BYPASS is set HIGH,
contains a IS-bit value which deterthe Delay Control Register will
mines the number of delay stages
automatically be loaded with a "0".
added to the input and control signals. This will set the number of programThe IS-bit data value is loaded serially mable delay stages to zero for all
into the Delay Control Register using
input and control signals. When
DEL and LD. Data present on DEL is
BYPASS is LOW, the desired number
latched on the rising edge of LD.
of delay stages can be set by loading

RNDI-O determines how the output of
the LF48212 is rounded. The output
may be rounded to 8, 10, 12, or 13-bits.
Table 1 lists the different rounding
possibilities and the associated value
for RNDI-O. Rounding is accomplished by adding a "1" to the bit to
the right of what will become the least
significant bit. Then the bit that had
the "1" added to it and all bits to the
right of it are set to "0". Data present
on RNDI-O is latched on the rising
edge of CLK. When RNDI-O is latched
in, it only applies to the video input
data latched in at the same time.
Changing RNDI-O does not affect the
rounding format for internal data
already in the pipeline.
OE - Output Enable
When OE is LOW, DOUT12-0 is
enabled for output. When OE is
HIGH, DOUT12-0 is placed in a highimpedance state.

==================== Video Imaging Products
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- --- --.-.------------......--------

-

LF48212

-~---

DEVICES INCORPORATED

FUNCTIONAL DESCRIPTION

The two video signals to be mixed
together are input to the LF48212
using DINAn-O and DINBn-o. Data
present on DINAn-o and DINBn-o is
latched on the rising edge of CLK.
The input data may be in either
unsigned or two's complement
format, but both inputs must be in the
same format. TC determines the
format of the input data. When TC is
HIGH, the input data is in unsigned
format. When TC is LOW, the input
data is in two's complement format.
TC is latched on the rising edge of
CLK and only affects the input data
latched in at the same time. The data
already"!? the pipeline is not affected
when TC changes.
DINAn-O and DINBn-O are mixed
together using an alpha mix factor
(an-o) as defined by the equation
listed in Figure 2. an-o is unsigned
and restricted to the range of 0 to 1.0.
MIXEN controls the loading of alpha
mix data. When MIXEN is HIGH,
data present on an-O is latched on the
rising edge of CLK. When MIXEN is
LOW, data present on an-o is not
latched and the last value loaded is
held as the alpha mix value.

12 X 12-bit Alpha Mixer
delay stages to DINBn-O, DELAYs-3
should be set to "100". DELAY14-0 is
loaded serially into the Delay Control
Register using DEL and LD. DELAYo
is the first value loaded and DELAY14
is the last. Data present on DEL is
latched on the rising edge of LD.
BYPASS is used to disable the programmable delay stages. When
BYPASS is HIGH, the Delay Control
Register is automatically loaded with
a "0". This sets all programmable
delay stages to a length of zero. When
BYPASS is LOW, the Delay Control
Register may be loaded to set the
desired number of delay stages. Note
that BYPASS is not intended to change
during active operation of the
LF48212.

of the internal summer output is not
needed. The Adjust stage takes the
output of the internal summer and left
shifts the data one bit position. This
removes the MSB of the internal
summer output and provides one
more bit of precision for the output
data.
. .
The output data of the LF48212 may
be rounded to 8, 10, 12, or 13-bits.
RNDI-O determines how the output is
rounded (See Table 1). RNDI-O is
latched on the rising edge of CLK and
only affects the input data latched in
at the same time. The data already in
the pipeline is not affected when
RNDI-O changes.

The Adjust stage of the LF48212 is
used to maximize the precision of the
output data. Since a can never be
larger than 1.0, the most significant bit

DEL

iD

DELAY11 }

It is possible to add extra delay stages
to the input data and control signals
by using the programmable delay
stages. The IS-bit value (DELAY14-0)
stored in the Delay Control Register
determines the number of delay stages
added. DELAYl4-0 is divided into S
groups of 3-bits each. Each 3-bit
group contains the delay information
for one of the input data or control
signals. Figure 3 shows the block
diagram of the Delay Control Register
as well as a list of the input data and
control signals that may be delayed
and the DELAY signals that control
them. The delay length can be programmed to be from 0 to 7 stages. The
delay length is set by loading the
binary equivalent of the desired delay
length into the appropriate 3-bit
group. For example, to add four extra

TC DELAY

DELAY10
DELAY9

DELAYs
DELAY7

}

(W·o DELAY

}

DINB11·0 DELAY

}

DINA11·oDELAY

DELAY.

DELAY.
DELAY,
DELAY3

DELAY2
DELAY,
DELAYo

===================== Video Imaging Products
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LF48212
DEVICES INCORPORATED

12 x 12-bit Alpha Mixer

Storage temperature ............................................................................................................ -65°C to +150°C
Operating ambient temperature ........................................................................................... -55°C to +125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground .............................................................................. -0.5 V to Vee + 0.5 V
Signal applied to high impedance output................ ...................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs ............................................................................................................. 25 rnA
Latchup current ................................................................................................................................ > 400 rnA

Active Operation, Commercial

Symbol

O°C to +70°C

4.75 V ~ Vee ~ 5.25 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., IOH = -400 ~A

2.6

VoL

Output Low Voltage

Vee = Min., IOL = 2.0 rnA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Typ

Max

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground ~ VIN ~ Vee (Note 12)

±10

~

Output Leakage Current

Ground ~ VOUT ~ Vee (Note 12)

±10

~

lee1

Vee Current, Dynamic

(Notes 5, 6)

120

rnA

lee2

Vee Current, Quiescent

(Note 7)

500

~

CIN

Input Capacitance

TA = 25°C, f = 1 MHz

10

pF

COUT

Output Capacitance

TA = 25°C, f = 1 MHz

10

pF

==================== Video Imaging Products
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-

- -- ------------- ....... - - --

LF48212

DEVICES INCORPORATED

12 x 12-bit Alpha Mixer

LF4821225
Symbol

Parameter

Min

tCYC

Cycle Time

25

tpw

Clock Pulse Width

10

ts

Input Setup Time

10

tH

Input Hold Time

0

Max

tD

Output Delay

13

tENA

Three-State Output Enable Delay (Note 11)

13

tDIS

Three-State Output Disable Delay (Note 11)

13

ClK
DINAl1-0
DINB11-0

c

tCYC
tpw

tpw-==l

.t::==ts

tH-==.j

F-ts

tH-=:j

)I(

)K

K
-tD

DOUT12-0

~

tDIS

~

i:=-tENA
HIGH IMPEDANCE

'includes MIXEN, TC, and RND1-0.

===================== Video Imaging Products
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..

-

- -- --------- -..---~--~ ---~

LF48212

DEVICES INCORPORATED

LD _ E t L P W

DEL _ _ _ _E t D S

12 x 12-bit Alpha Mixer

t
1.

tLPW~~

_ __

IDH3_--------------------

===================== Video Imaging Products
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- ---------- ---------------

LF48212

--..-.---~

.........

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

12 x 12-bit Alpha Mixer

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified 10H and 10L at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of 10H and 10L
respectively, and a balancing voltage of
1.5 V may beused. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 rnA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

VCC

d,
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on I turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

~r

a. A 0.1 ~F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary shouldbeinstalledbetweendeviceVee
from those designated but operation is and the tester common, and device
guaranteed as specified.
ground and tester common.
5. Supply current for a given applicab. Ground and Vee supply planes
tion can be accurately approximated must be brought directly to the DUT
by:
socket or contactor fingers.
NCV2 F

4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a minimum or maximum value. Input re6. Tested with all outputs changing ev- quirements are specified from the point
ery cycle and no load, at a 40 MHz clock of view of the external system driving
the chip. Setup time, for example, is
rate.
specified as a minimum since the exter7. Tested with all inputs within 0.1 Vof nal system must supply at least that
Vee or Ground, no load.
much time to meet the worst-case re8. These parameters are guaranteed quirements of all parts. Responses from
the internal circuitry are specified from
but not 100% tested.

+--~-OOUTPUT

n+
D1

p-

~~~;~i~ --~~t"#="""~Fi'~
O.2V

O.2V

===================== Video Imaging Products
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..

- --.-. ---------.........------ ------

-

LF48212

DEVICES INCORPORATED

12 x 12-bit Alpha Mixer

S8-pin

8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
•
60

DINB11
DINB10
DINB9
DINBB
DINB7
DINBs
GND
DINB5
NC
DINB4
DINB3
DINB2
DINB1
DINBo
RND1
RNDo
DEL

Top
View

OE
DOUT,2
DOUT11
DOUT1O
DOUT9
GND
DOUTB
DOUT7
NC
DOUTs
DOUT5

Vee
DOUT4

26

44

DOUT3
DOUT2
DOUT,
DOUTo

V~~~~~~M~~~~S~~G~

Plastic J-Lead Chip Carrier
(J2)

25 ns

LF48212JC25

===================== Video Imaging Products
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- --------- ---...---------

LF48212

------~
-~---

DEVICES INCORPORATED

12 x 12-bit Alpha Mixer

64-pin
(J)

(J)
zw
~
l<:x
()
o~a.
d~§B~B~~@eg@§BB~

DINB11
DINB10
DINBs
DINBs
DINB?
DINB6
GND
DINB5
DINB4
DINB3
DINB2
DINB1
DINBo
RND1
RNDo
DEL

25 ns

•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

•

"It('t)C\I,...OCJ)cn ...... COIO"It('t)C\I,...OCJ)
COCOCOCOCOIOI.t)lt)IOlt)I.t)lt)lt)lt)lt)"It

Top
View

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

33

OE
DOUT12
DOUT11
DOUT10
DOUTs
GND
DOUTs
DOUT?
DOUTs
DOUT5
VCC

DOUT4
DOUT3
DOUT2
DOUT1
DOUTo

LF48212QC25

===================== Video Imaging Products
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--.......
-- -.......- ---------........
...--.

.-...

_....--.

-..._

-

-~---

DEVICES INCORPORATED

-- - -..,,-----

=--:....=:a..:
- -=:........r
--

LF48410

~---

-~

DEVICES INCORPORATED

o 40 MHz Data Input and Computation Rate
o 1024 x 24-bit Memory Array
o Histograms of Images up to 4K x
4K with lO-bit Pixel Resolution
o Memory Array Flash Clear
o User-Programmable Modes:
Histogram, Histogram Accumulate,
Look Up Table, Bin Accumulate,
Delay Memory, Delay and Subtract,
Single Port RAM
o Available 100% Screened to
MIL-STD-883, Class B
o Replaces Harris HSP48410 and
HSP48410/883
o Package Styles Available:
• 84-pin Plastic LCC, J-Lead
• 84-pin Ceramic PGA

1024 x 24-bit Video Histogrammer

The LF48410 is capable of generating
histograms and Cumulative Distribution Functions of video images. It
may also be used as a look up table, a
bin accumulator, a delay memory
(delay and subtract also possible), or a
single port RAM. The on-chip 1024 x
24-bit memory array facilitates
histograms of images up to 4K x 4K
pixels with a lO-bit pixel resolution.
Once the histogram of a video image
is stored in the memory array, the
Cumulative Distribution Function can
be calculated by putting the device in
Histogram Accumulate Mode. Transformation functions can be performed
on pixel values when the device is in

Look Up Table Mode. If the Cumulative Distribution Function is the
desired transformation function, the
LF48410 can calculate it and have it
. .
available for Look Up Table Mode.
When the device is in Delay Memory
Mode, it functions as a video row
buffer. In this mode, the LF48410 can
buffer video lines as long as 1028
pixels. The device can also function as
an asynchronous single port RAM.
During asynchronous modes, the
device can be configured as a 1028 x
24, 1028 x 16, or 1028 x 8-bit RAM. A
Flash Clear function is provided
which sets all memory array locations
and data path registers to "0".

==================== Video Imaging Products
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LF48410
DEVICES INCORPORATED

SIGNAL DEFINITIONS
Power

VccandGND
+5 V power supply. All pins must be
connected.

Clock

CLK - Master Clock
When operating in a synchronous
mode, the rising edge of CLK strobes
all enabled registers. CLK has no
effect when operating in an asynchronousmode.
Inputs

PIN9-0 - Pixel Data Input
PIN9-0 provides address information
to the memory array in Histogram,
Bin Accumulate, and Look Up Table
Modes. Data is latched on the rising
edgeofCLK.

DIN23-0 - Data Input
In Bin Accumulate Mode, DIN23-0

provides data to the internal summer
to be added to data already in the
memory array. In Look Up Table
Mode, OIN23-O is used to load the
memory array with the desired
values. In Delay Memory Mode, the
data to be delayed is input to the
memory array using DIN23-0, and in
Delay and Subtract Mode it also
provides data to be subtracted from
the delayed data. In all four modes,
DIN23-O is latched on the rising edge
ofCLK.

IOA9-0 - Asynchronous Address Input
IOA9-0 provides address information
to the memory array in Asynchronous
16 and 24 Modes.

1024 X 24-bit Video Histogrammer
edge of LD. To ensure proper operation of the device, START must be
HIGH while changing modes, and
there must be at least one rising ed~
of CLK between the rising edge of LD
and the falling edge of START.
Inputs/Outputs

DI023-0 - Data Input/Output
In all synchronous modes, DI023-o is
the 24-bit registered data output port.
In all asynchronous modes, DI023-O is
both the data input and data output
port for the memory array.
Controls

START - Device Enable
START is used to enable and disable
the synchronous modes of operation
(except for the Delay Memory and
Delay and Subtract Modes). The
synchronous mode sections explain
how START functions in each mode.
START has no effect in asynchronous
modes. Data is latched on the rising
edge of CLK. START must be held
HIGH when changing from one mode
to another. To ensure proper operation of the device, there must be at
least one rising ed~of CLK between
the rising edge of LD and the falling
edge of START.
RD - Read/Output Enable

UWS - Upper Word Select
UWS is only used in Asynchronous 16
Mode. If UWS is LOW and a memory
write is performed, data on DI015-0 is
written to the lower 16 bits of the
addressed 24-bit word. If UWS is
LOW and a memory read is performed, the lower 16 bits of the
addressed 24-bit word will be output
on 01015-0. If UWS is HIGH and a
memory write is performed, data on
0107-0 is written to the upper 8 bits of
the addressed 24-bit word. If UWS is
HIGH and a memory read is performed, the upper 8 bits of the
addressed 24-bit word will be
output on DI07-0.

FC - Flash Clear
When FC is LOW, all memory array
locations and data path registers are
set to "0". To ensure that Flash Clear
functions properly, FC should not be
set LOW until START is HIGH
(synchronous modes) or WR is HIGH
(asynchronous modes).
LD - Function Load Strobe

Data present on FCTz-O is latched into
the LF484lO on the rising edge of LD.
To ensure proper operation of the
device, there must be at least one
rising edge of CLK between the rising
edge of LD and the falling edge of
START.

In all synchronous modes, RD is used

as an o~ut enable for 01023-0.
When RD is LOW, 01023-0 is enabled
for output. When RD is HIGH, 01023-0
is placed in a high-impedance state. In
all asynchronous modes, RD is used as
a read enable for the memory array
(see asynchronous mode sections for
details).
WR - Write Enable

FCT2-0 - Function Input

In all asynchronous modes, WR is

FCTz-o is used to put the LF48410 into
one of its eight modes of operation
(Table 1). Data is latched on the rising

used as a write enable for the memory
array (see asynchronous mode sec- .
tions for details). WR has no effect In
the synchronous modes.

==================== Video Imaging Products
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-- .....
-=- -- ----="':-=.. -

LF48410

==~'====~

DEVICES INCORPORATED

1024 X 24-bit Video Histogrammer

HISTOGRAM MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure 1.
The memory array keeps track of how
many times a particular pixel.value is
used in a video image. The pIxel
value is input on PIN9-O and is latched
on the rising edge of CLK. Data at the
address defined by PIN9-0 is read out
of the memory array and incremented
by one. The data is then written back
to the memory array, in the same
location it was read from, and is also
output on DI023-O (if RD is L0"Y)' As
long as START is LOW, the devIce
will be enabled for Histogram Mode.
When START is HIGH, the device will
still read pixel values, but the addressed data will not be incremented. The
unchanged data is output on DI023-0
and is not written back to the memory
array (writing is disabled). START is
delayed internally three clock cycles to
match the latency of the address
generator.

01023-0
PIN9{)

START-------t

elK -------+- TO ALL REGISTERS

0102>0

HISTOGRAM ACCUMULATE
MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure 2.
This mode is used to calculate the
Cumulative Distribution Function of a
video image. Before this can be done,
the histogram of the image must
already be in the memory array. The
internal counter is used to generate
address data for the memory array.
Data at the address defined by the
counter is read out of the memory
array and added to the sum of the
data from all previous address
locations. This new value is written
back to the memory array, in the same
location where the last read occurred,
and is also output on DI023-0 (if RD is
LOW). After all memory locations
with histogram data are accumulated,
the memory array will contain the
Cumulative Distribution Function.
After this mode is selected, the
internal counter and all data path
registers are reset to zero when

(TOALL~~';;;IS~TE;;;AS;;-)----~~~-.J

START is set LOW. Every rising edge
of CLK causes the counter to increment its output by one until the
counter reaches a value of 1023. At
this point, the counter will hold the
value of 1023 and writing to the
memory array will be disabled .. As
long as START is LOW, the deVIce
will be enabled for Histogram Accumulate Mode. When START is HIGH,
the counter will still increment its
address values, but the addressed
data will not be added to anything.
The unchanged data is output on
DI023-0 and is not written back to the
memory array (writing is disabled).
START is delayed internally three
clock cycles to match the latency of the
address generator.

LOOK UP TABLE MODE
When the LF484lO is in this mode, the
chip is configured as shown in ~igure 3.
This mode is used to perform fixed
transformation functions on pixel
values. The transformation function
can be loaded into the memory array
in Look Up Table Write Mode, Asynchronous 16/24 Mode, or Histogram
Accumulate Mode. In Look Up Table
Write Mode, data is loaded into the
memory array using DIN23-0, CLK:
and START. The internal counter IS
used to generate address data for the
memory array. When START goes
LOW, the counter is reset to zero. As
long as START is LOW, d~t~ on
DIN23-O is latched on the rlsmg edge
of CLK and loaded into the memory

=========================== Video Imagin~6/~/~~L~s~:~~
2-115

•

- ------- .....
_--=-=-==-==:......r

LF48410

-~---

DEVICES INCORPORATED

1024 x 24-bit Video Histogrammer

DlN23"()

DIQ23..()
PIN9"()

BIN ACCUMULATE MODE

TERsI----G~~J

(TO ALL elK
REGiSTERS)

START

--------+1

ClK ----------. TO ALL REGISTERS

array at the address defined by the
counter. The value already in the
memory array at that address is
output on DI023-0 (if RD is LOW).
Every rising edge of CLK causes the
counter to increment its output by one
until the counter reaches a value of
1023. At this point, the counter will
hold the value of 1023 and writing to
the memory array will be disabled.
DIN23-O is delayed internally three
clock cycles to match the latency of the
address generator. In Asynchronous
16/24 Mode, data is loaded into the
memory array as detailed in the

of the memory array and output on
DI023-0 (if RD is LOW). If Look Up
Table Write Mode was used to load
the memory array, it is important to
wait until the third clock cycle after
START goes HIGH to input data on
PIN9-0 to insure that all data is written
into the memory array before any
reading is done.

NOTE: NUMBER IN REGISTER INDICATES
NUMBER Of PIPELINE DELAYS.

NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPEUNE DELAYS.

asynchronous mode sections. If the
Cumulative Distribution Function is
the desired transformation function,
the memory array will contain this
data as soon as the Histogram Accumulate function has been completed.
Once the memory array contains the
desired data, the device needs to be
put in Look Up Table Read Mode by
setting START HIGH. In Look Up
Table Read Mode, pixel values are
input on PIN9-0 and are latched on the
rising edge of CLK. Data at the
address defined by PIN9-O is read out

When the LF48410 is in this mode, the
chip is configured as shown in Figure 4.
PIN9-0 provides address data for the
memory array and is latched on the
rising edge of CLK. Data at the
address defined by PIN9-O is read out
of the memory array and added to the
data on DIN23-O. This new value is
written back to the memory array, in
the same location where the last read
occured, and is also output on DI023-0
(if RD is LOW). As long as START is
LOW, the device will be enabled for
Bin Accumulate Mode. When START
is HIGH, the device will still read
address values on PIN9-0, but the
addressed data will not be added to
anything. The unchanged data will be
output on DI023-0 and is not written
back to the memory array (writing is
disabled). START and DIN23-0 are
delayed internally three clock cycles to
match the latency of the address
generator.
DELAY MEMORY MODE
When the LF484lO is in this mode, the
chip is configured as shown in Figure 5.
This mode allows the device to
function as a row buffer. The internal
counter is used to generate address
data for the memory array. When
START goes LOW, the counter is reset
to zero. Delay length (row length) is
determined by reseting the counter
every N-4 clock cycles, where N is the
number of delays. For example, to set

==================== Video Imaging Products
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----- -- ..--_---

-~~-~

LF48410

.-..~--......-.

-~---

DEVICES INCORPORATED

the number of delays to 10, START
would have to be set LOW every 6
cycles. The maximum delay length i~
1028 and the minimum delay length IS
6. Data on DIN23-O is latched on the
rising edge of CLK and loaded into
the memory array at the address
defined by the counter. Data is output
on DI023-0 (if RD is LOW). If the
counter reaches the value of 1023, the
counter will hold this value and
writing to the memory array will be
disabled.

1024 X 24-bit Video Histogrammer

DtN23-0

01023-0

(TOALL~'ta';;;'S;:;;TE;:;;RS;;-)----~~~J

iffiiFIf--------.J
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DElAYS.

DELAY AND SUBTRACT MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure 6.
The internal counter is used to generate address data for the memory
array. When START goes LOW, the
counter is reset to zero. Delay length
(row length) is determined by reseting
the counter every N-4 clock cycles,
where N is the number of delays. The
maximum delay length is 1028 and the
minimum delay length is 6. Data on
DIN23-0 is latched on the rising edge
of CLK and loaded into the memory
array at the address defined by the .
counter. Data is output on DI023-O (if
RD is LOW). Before data read from
the memory array is output to DI023-0,
input data is subtracted from it
according to the following formula:
OUTc = D(C-N+l) - D(C-3). OUTc is
the data sent to the output port
(DI023-0) on clock cycle C. D(C-N+l) is
the data latched into the device on
clock cycle C-N+1, and D(C-3) is the
data latched into the device on clock
cycle C-3. N is the number of delays.
For example, to determine what will
be output on DI023-O on clock cycle 12
when the device is set for 10 delays,
set C=12 and N=10 to obtain:
OUT12 = D3 - D9. If the counter
reaches the value of 1023, the counter
will hold this value and writing to the
memory array will be disabled.

DIN2> 400 mA

Temperature Range (Ambient)
O°C to +70°C
-55°C to +125°C

Mode
Active Operation, Commercial
Active Operation, Military

Symbol

Supply Voltage
4.75 V ~ Vee ~ 5.25 V
4.50 V ~ Vee ~ 5.50 V

Min

Parameter

Test Condition

VoH

Output High Voltage

Vee

=Min., 10H =-2.0 mA

VoL

Output Low Voltage

Vee

=Min., 10L =4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground

~

VIN

loz

Output Leakage Current

Ground

~

VOUT

leel

Vee Current, Dynamic

lee2

Typ

Max

2.6

Unit
V

0.4

V

2.2

Vee

V

0.0

0.8

V

Vee (Note 12)

±10

!1A

~

±10

!1A

(Notes 5, 6)

310

mA

Vee Current, Quiescent

(Note 7)

500

!1A

CIN

Input Capacitance

TA =25°C, f =1 MHz

12

pF

COUT

Output Capacitance

TA =25°C, f =1 MHz

12

pF

~

Vee (Note 12)

===================== Video Imaging Products
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OS/29/95-LDS.4B410-D

-

= -.-=a.. _--- .....
---

~=..=.
~ -~-~--

-....----.....,
--.-..

LF48410

DEVICES INCORPORATED

1024 x 24-bit Video Histogrammer

==================== Video Imaging Products
2·120

06/29/95-LDS.48410-D

---=- -- -----

,..~=~

-

LF48410

--~-.--~

-~---..-..

DEVICES INCORPORATED

1024 x 24-bit Video Histogrammer

===================== Video Imaging Products
2-121

06129195-LDS.48410-D

--..-- _-..--__-..-

- --......-------- -

LF48410

DEVICES INCORPORATED

1024 x 24-bit Video Histogrammer

2

4

3

5

7

6

elK
START

PIN9-0

RD
IDIS

}..:=

D1023-0

lENA

HIGH IMPEDANCE

E

ID

£

X

X

>C

3'

"RAM contents not changed.

2

4

3

5

6

7

elK
START

RD
IDIS

}..:=

D1023-0

~IGH

lENA

IMPEDANCE

E

ID

£

X

X

>C

3'

"RAM contents not changed.

2

4

3

6

5

7

elK

PIN9-0 _ _ _J '----'--t-:--' '--_-"-_J '-_--""_-'

'-_+-_-' "'-___-' '--_-"-_J '-_---'-_-'

DIN23-0 _ _ _/1'---'----'-_-/"''--_-=-_.../ '-_--=-_-/ "'--~I---' "'--_'----' "'--_'-----J "'--_ _---J

IDISr-

D1023-0

==============>--

lENA
HIGH IMPEDANCE

E-------r
ID

~_ _ _""'

x'-_---'-_---.JX'-__3_'_ _>c

"RAM contents not changed.

====================Video Imaging Products
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06/29/95-LOS.48410-0

----.. ----- --..........---_

-

...-... ...-...-...-...
-~---

LF48410

~--

-~---

DEVICES INCORPORATED

1024 x 24-bit Video Histogrammer

2

4

3

6

5

7

elK
START'

•

DIN23-0

RD

DI023-o

=1".~

J'E~E

HIGH IMPEDANCE

·START must be held lOW a minimum of tSH after the rising edge of elK that loads the last value of DIN23-0_

2

4

3

5

7

6

elK
START'

PIN9-0

RD

D1023-0

=1", ~

J'''''E

HIGH IMPEDANCE

>C

·START must be held HIGH a minimum of tSH after the rising edge of elK that loads the last value of PIN9-0_

RO _ _ _ _ _----'1

:::::::::::::::::=}-tDlsr

01023-0

tD~

tENAE
HIGH IMPEDANCE

__

_

------------~~

Shown are the wavefonns for a delay length of 10_

===================== Video Imaging Products
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- - --=
===iii== =
-""-"'"--....-.--....-.

LF48410

--....-.--~

DEVICES INCORPORATED

1024 x 24-bit Video Histogrammer

tCY
twL

twH

I"

"
J:=

IOA9·0

uws'

tAS

- - I - - tAH--=:j

)K

)I(.

-----------------r-------3------------twos

01023·0

I

{

-I--- tWDH

'applies only to 16-bit Asynchronous Mode.

tCY
tRL

I

tRH

{

~

IOA9·0
UWS·

.l:=tAS-- -tAH--=:j

)K

)K
f--tDIS--j

i - - - tRD--===:1
01023-0

HIGH IMPEDANCE

HIGH IMPEDANCE

}I\

'applies only to 16-bit Asynchronous Mode.

lO-----c~~
FCT2-o3

:s?f-----tLS

FC

=:::::1

------C J-----tFL

START' -----------~

'there must be at least one rising edge of ClK between
the rising edge of i1l and the falling edge of START.

==================== Video Imaging Products
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- ._-_

- .---- --------..---""-"'"--- - --

LF48410

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.

2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

1024 x 24-bit Video Histogrammer

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vee

d,
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

~r

a. A 0.1 j.lF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary should be installed between device Vee
from those designated but operation is and the tester common, and device
guaranteed as specified.
ground and tester common.

5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated must be brought directly to the DUT
by:
NCV2 F
socket or contactor fingers.

4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 Vof
Vee or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

+--....,...--0 OUTPUT
n+

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from

===================== Video Imaging Products
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OS/29/95-LDS.4B410·D

•

LF48410
DEVICES INCORPORATED

1024 x 24-bit Video Histogrammer

84-pin

FC
RD
START

11109 8 7 6 5 4 3 2 184838281807978777675
12
•
74
73

iJ5
FCT2
FCT,
FCTo
WR
GND
UWS
10Ag
10As
IOA7
10As
IOA5
lOA
,....

,_I

,_I

FCT2

ffi

FCTl GND IOA5 lOA? IOA4 IOA2 IOA1

Vee

,I

,

,... ,_I
"
,_I
,... ,_I
"
,_I

DI04 DI05

,

1

,

1

,_I

,_I

WR UWS 16A6 IOA3 10Ao DIOo DI02
,.... ,.... ,.... ,.... ,.... ,.... ,... , ..
, 1 ,_I ,_I ,_I ,_I ,_I ,_I '..,'

30 ns
25 ns

LF48410GC30
LF48410GC25

39 ns
30 ns

LF48410GM39
LF48410GM30

39 ns
30 ns

LF48410GMB39
LF48410GMB30

=====================Video Imaging Products
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06/29/95-LDS.48410-D

--- ------ ..-----_----.-.---

-~---

DEVICES INCORPORATED

-= -..=...=.
-- --==..=.
=----

L F48908

=-:....::...:

-~--DEVICES INCORPORATED

Two Dimensional Convolver

o 40 MHz Data and Computation

The LF48908 is a high-speed two
Rate
dimensional convolver that implements a 3 x 3 kernel convolution at
o Nine Multiplier Array with 8-bit
real-time video rates. Programmable
Data and 8-bit Coefficient Inputs
buffers are located on-chip,
o Separate Cascade Input and Output row
eliminating the need for external data
Ports
storage. Each row buffer can store up
o On-board Programmable Row
to 1024 pixels. Two internal register
Buffers
banks are provided allowing two
o Two Coefficient Mask Registers
separate sets of filter coefficients to be
DOn-board 8-bit ALU
stored simultaneously. Adaptive filter
operations are possible when both
o Two's Complement or Unsigned
Operands
register banks are used. An on-chip
ALU is provided, allowing real-time
o Replaces Harris HSP48908
arithmetic
and logical pixel point
o DESC SMD No. 5962-93007
operations to be performed on the
o Available 100% Screened to
image data. The 3 x 3 convolver
MIL-STD-883, Class B
comprises nine 8 x 8-bit multipliers,
o Package Styles Available:
various pipeline registers, and sum• 84-pin Plastic LCC, J-Lead
mers. A complete sum-of-products
• 100-pin Plastic Quad Flatpack
operation is performed every clock
• 84-pin Ceramic PGA

cycle. The FRAME signal resets all
data registers without affecting the
control and coefficient registers.
•
Pixel and coefficient input data are
both 8-bits and can be either signed or
unsigned integers. Image data should
be in a raster scan non-interlaced
format. The LF48908 can internally
store images as wide as 1024 pixels for
the 3 x 3 convolution. By using
external row buffers and multiple
LF48908s, longer pixel rows can be
used and convolutions with larger
kernel sizes can be performed. Output data is 20-bits and this guarantees
no overflow for kernel sizes up to 4 x 4.
A separate cascade input is used as
the data input for summing results
from multiple LF48908s. It can also
function as the data input path when
external line buffers are used.

16
CASll5-0

8
DINHl

8
CIN!>-O

3

~

ROW
BUFFERS

I

lD
CS

3x3

CONVOLVER

20
DOUT19·0

8
CAS07·o

ClK
HOLD

EAlU
RESET

CONTROL
LOGIC

FRAME
OE

=====================Video Imaging Products
2·129

07/12/95-LDS.48908·D

--

- - ---------- ----.--.-..-.
--.....-.-""-,,,,--~.-..-~

LF48908

DEVICES INCORPORATED

Two Dimensional Convolver

ALU

15-8

7-0

8
DIN7-o --_r_----.t
8
CIN9-0

7-0

8

1--..-4----7''--- CAS07-o

8

----.,--'-'---,~

ALU
REGISTER

10

F

C

3
A2-o --_r_----.t CONTROL
L D - - - - - - a LOGIC
CS------a

E

H

B

CLK----_~
HOLD----_~
EALU----_~

RESET

----_~

FRAME

----_~

OE----_~

16
CASI1S-o --_-~

DOUT19-o
NOTE: NUMBERS IN REGISTER INDICATE
NUMBER OF PIPELINE DELAYS.

==================== Video Imaging Products
2-130

07/12/95-LDS.48908-D

----...
_-.,
_.......
---- ---- -----

_--..... .........

-

LF48908

-~---

DEVICES INCORPORATED

Two Dimensional Convolver

SIGNAL DEFINITIONS

CAS07-0 - Cascade Output

A2-0 - Control Logic Address Lines

Power

The data presented on CAS07-0 is the
internal ALU output delayed by twice
the programmed internal row buffer
length.

A2-0 determines which Control Logic
Register will receive the CIN9-O data.

VccandGND
+5 V power supply. All pins must be
connected.

Controls
Clock

CLK - Master Clock
The rising edge of CLK strobes all
enabled registers except for the
Control Logic Registers.
Inputs

DIN7-0 - Pixel Data Input
DIN7-0 is the 8-bit registered pixel
data input port. Data is latched on the
rising edge of CLK.

CIN9-0 - Coefficient and Control Logic
Register Input
CIN7-O is used to load the Coefficient
Registers or can be used to provide a
second operand input to the ALU.
CIN8-0 is used to load the Initialization Register. CIN9-0 is used to load
the ALU Microcode and Row Buffer
Length Registers. The Control Register Address Lines, Az-o, determine
which register will receive the CIN
data. The CIN data is loaded into the
addressed register by using the CS
and LD control inputs.

CASI15-O - Cascade Input
The cascade input is used when
multiple LF48908s are cascaded
together or when external row buffers
are needed. This allows convolutions
of larger kernels or longer row sizes.
Outputs

DOUT19-0 - Data Output
DOUT19-0 is the 20-bit registered data
output port.

RESET - Reset Control
When RESET is LOW, all internal
circuitry is reset, all outputs are forced
LOW, all Control Logic Registers are
loaded with their default values
(which is 0 for each one except the
ALU Microcode Register which has a
default value of "0000011000"), and all
other internal registers are loaded
with a "0".

FRAME - New Frame Input Control

CS - Chip Select

When CS is LOW, data can be loaded
into the Control Logic Registers .
When CS is HIGH, data can not be
loaded and the register contents will
not be changed.
LD -

Load Strobe

If CS and LD are LOW, the data

present on CIN9-0 will be latched into
the Control Logic Register addressed
by A2-O on the rising edge of LD.
FUNCTIONAL DESCRIPTION

The LF48908, a two-dimensional
convolver, executes convolutions using
internal row buffers to reduce design
complexity and board space requirements. 8-bit image data, in raster scan,
non-interlace format, is convolved with
one of two internal, 3 x 3 userprogramab1e IDter kernels. Two 1024 x 8EALU - Enable ALU Register Input
bit row buffers provide the data delay
needed to perform two-dimensional
When HIGH, data on CIN7-0 is latched
convolutions on a single chip. The result
into the ALU Register on the next
output of 2G-bits allows for word growth
rising edge of CLK. When LOW, data
during the convolution operation.
on CIN7-O will not be latched into the
ALU Register and the register conThe input data path (DIN7-O) provides
tents will not be changed.
access to an 8-bit ALU. This allows
point operations to be performed on
the incoming data stream before
HOLD - Hold Control
reaching the row buffers and the
The HOLD input is used to disable
convolver. The length of these buffers
CLK from all of the internal circuitry.
is programmable for use in various
HOLD is latched on the rising edge of video formats without the need for
CLK and takes effect on the next rising additional external delay.
edge of CLK. When HOLD is HIGH,
This device is configured by loading
CLK will have no effect on the
the coefficent data (filter kernels) and
LF48908 and all internal data will
row buffer length through the
remain unchanged.
coefficent data path (CIN7-0). Internal
registers are addressed using the Az-o
OE - Output Enable
address lines. Chip Select (CS) and
When OE is LOW, DOUT19-0 is
Load Strobe (LD) complete the
enabled for output. When OE is
configuration interface which may be
HIGH, OOUT19-0 is placed in a highcontrolled by standard microprocesimpedance state.
sors without additional external logic.

When asserted, FRAME sigI!als the
start of a new frame. When FRAME is
LOW, all internal circuitry is reset
except for the ALU Microcode, Row
Length, Initialization, Coefficient, and
ALU Registers.

==================== Video Imaging Products
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•

---- -- -----------------_
......
-~~-~

LF48908

-

-~---

DEVICES INCORPORATED

The filtered image data is output on
the Data Output bus (DOUT19-0). This
bus is registered with three-state
drivers to facilatate use on a standard
microprocessor system bus.
OataInput
Image data is input to the 3 x 3
convolver using DIN7-0. Data present
on DIN7-0 is latched into a programmable pipeline delay on the rising
edge of CLK. The programmable
pipeline delay (1 to 4 clock cycles)
allows for synchronization of input
data when multiple LF48908s are
cascaded together to perform larger
convolutions. This delay is programed via the Initialization Register
(see Table 3). The image data format,
unsigned or two's complement, is also
controlled by this register.

Two Dimensional Convolver
data path, while the "B" operand is
taken from the ALU Register. The
ALU Register is loaded using CIN7-0
and EALU. With EALU HIGH, data
from CIN7-0 is loaded into the ALU
Register on the rising edge of CLK.
With EALU LOW, the data is held in
the ALU Register. Since CIN7-0 is also
used to load the Control Logic Registers, it is possible to overwrite data in
those registers if CS and LD are active
when loading the ALU Register.
Therefore, special care must be taken
to ensure that CS and LO are not
active when writing to the ALU
Register.

multiplier array. The Cascade Output
(CAS07-{) provides a 2X row delay of
the input data allowing for cascading
of LF48908s to handle larger frames
and/ or kernel sizes. If more than 1024
delay stages are needed, it is possible
to use external row buffers and bypass
the internal row buffers. Bit 0 of the
Initialization Register determines if
internal or external row buffers are
used. If Bit 0 is a "0", the internal row
buffers are used. If Bit 0 is a "1", the
internal row buffers are bypassed and
external row buffers may be used.

Programmable Row Buffers

The multiplier array comprises nine
8 x 8-bit multipliers. The active
Coefficient Register supplies the
coefficents to each of the multipliers,
while the pixel data comes from the
data input path and row buffers. The
array forms a sum-of-products result
as defined by the equation listed in
Figure 3.

The two internal row buffers provide
the delay needed to perform the twodimensional convolution. The row
buffers function like 8-bit serial shift
Coefficient data is input to the 3 x 3
registers with a user-programmable
convolver using either of two Coefdelay from 1 to 1024 stages (it is
ficient Registers (CREGo or CREGl).
possible to select delay stages of 1 or
The Coefficient Registers are loaded
2, but this leads to meaningless results
through CIN7-{) using the A2-{), CS, and
for a 3 x 3 kernel convolution). The
LD controls. The coefficient data
row buffer length is set via the Row
format, unsigned or two's compleLength Register (see Row Length
ment, is determined by the InitializaRegister Section). The row buffers are
tion Register.
connected in series to provide the
proper pixel information to the
Arithmetic Logic Unit
The input data path ALU with shifter
allows pixel point operations to be
performed on the incoming image.
These operations include arithmetic
functions, logical masking, and left/
right shifts. The lO-bit ALU Microcode Register controls the various
operations. The three upper bits
control the shift amount and direction
while the seven lower bits determine
the arithmetic or logical operation.
The shift operation is performed on
the output of the ALU. This shift
operation is independent of the
arithmetic or logical operation of the
ALU.

PIXEL INPUT DATA

3 x 3 Multiplier Array

CONTROL LOGIC
Four sets of registers, the ALU Microcode, Row Length, Initialization, and
Coefficient, define the Control Logic
section. These registers are updated

FILTER KERNEL

P1

P2

P3

A

B

C

P4

P5

P6

D

E

F

P7

P8

P9

G

H

I

MULTIPLIER ARRAY OUTPUT = A(P1) + B(P2) + C(P3)

+ D(P4) + E(P5) + F(P6)
+ G(P7) + H(P8) + I(P9)

Tables 1 and 2 show the operations of
the ALU Microcode Register. The"A"
operand comes from the DIN input

===================== Video Imaging Products
2-132

07/12/95-LDS.48908-D

-- ------

- .-..-.......
-...--.
-- --------~--......-.
-""-"'"---

LF48908

DEVICES INCORPORATED

Two Dimensional Convolver

-

ENCR1

ENCRo

3
A2. 400 rnA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

Parameter

Test Condition

VoH

Output High Voltage

Vee

=Min., 10H =-400 j.LA

VoL

Output Low Voltage

Vee

=Min., 10L =2.0 rnA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground

~

VIN

loz

Output Leakage Current

Ground

~

VOUT ~ Vee (Note 12)

lee1

Vee Current, Dynamic

lee2

Supply Voltage
4.75 V

~

Vee

~

5.25 V

4.50 V

~

Vee

~

5.50 V

Min

Typ

Max

2.8

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

±10

j.LA

±10

j.LA

(Notes 5, 6)

110

rnA

Vee Current, Quiescent

(Note?)

500

j.LA

CIN

Input Capacitance

TA

=25°C, f =1 MHz

10

pF

COUT

Output Capacitance

TA

=25°C, f =1 MHz

12

pF

~

Vee (Note 12)

==================== Video Imaging Products
2·136

07/12/95-LDS.48908·D

---- -.......- _-_--

-.,--., --~-~----

LF48908

-~--DEVICES INCORPORATED

ClK
DIN7-0
CAS115-0
CIN7-0
(AlU REG DATA)

Two Dimensional Convolver

,r-

tCYC
tPWL

~

,l:==.tDS
)I(

tDH--=:j
)I(

,I:==.tcs

tCH--=:j

)I(
I:==.tES

EAlU

tPWH~

~

.Ii"

)I(
tEH..:=j

"k.
~

OE

I-t~
CAS07-0

·l-tDIS-

~
I="tENA-

)I(

~tg
DOUT19-0

HIGH IMPEDANCE

==================== Video Imaging Products
2-137

07/12/95-LDS.48908-D

- - ----------=~~~~

LF48908

--~--..-.

-~---

DEVICES INCORPORATED

ClK
DIN7-0
CAS115-0
CIN7-0
(AlU REG DATA)

Two Dimensional Convolver

.r---

ICYC

"'I<..

./

.i:==IOS
)I(

10H-=:j

.t::==.ICS

ICH-=:j

)I(

)I(
t::==.IES

EAlU

-===::-I

IPWH

1PWL

)I(
IEH-=:j

~

"'k.

OE

CAS07-o

"'I<..
I--I0-=:::::j .
)I(

f---DOUT19-0

to--==:!
)I(

I----IOIS-

I='"IENA-

HIGH IMPEDANCE

==================== Video Imaging Products
2-138

07/12/95-LOSAB90B-0

--

- ----.
- -------...--.
-----""-""--~

LF48908

--~--....-.

DEVICES INCORPORATED

Two Dimensional Convolver

•

ClK ____________________________________________~~
tLPW

.. I .

,,'------

tLCS'

lD
CIN9-0

A2-o

cs

J

.1

tCDS

tCDH-=:!

~
tAS

--------------------C

tAH-=J.

)I(
tcss

-I---

tCSH

]t----------

'applies only when the lF48908 is in active operation.

==================== Video Imaging Products
2-139

07l12/95-LOS.4890B-D

- - -----------.......

-~~-~

~------~----~

LF48908

DEVICES INCORPORATED

Two Dimensional Convolver

-~---

elK
~tHS

i

tHH

HOLD

t"

tHS------i
{

FRAME
_---.CtRPW~

RESET

_

tFPW

" ~j

"

1

_ _ _ _ _ _ _ __

--.-fi

==================== Video Imaging Products
2-140

07/12/95-LDS.48908-D

---------- -- ----..--.~-~

~

LF48908

---~--,......

-~---..-..

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of --0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

Two Dimensional Convolver

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDiS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDiSABLE
measurements, the load current is
increased to 10 rnA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

VCC

d,
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

~r

a. A O.IIlF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary should be installed between device Vee
from those designated but operation is and the tester common, and device
guaranteed as specified.
ground and tester common.
5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated must be brought directly to the DUT
by:
NCV2 F
socket or contactor fingers.

4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 Vof
Vee or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

+--...,...-0 OUTPUT
n+

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from

====================Video Imaging Products
2-141

07/12/95-LDS.4890B-D

•

LF48908
DEVICES INCORPORATED

Two Dimensional Convolver

84-pin

CIN3
CIN4
CINs
CINs
CIN7
CINB
CIN9
GND
CLK
Vee
HOLD

11109 8 7 6 5 4 3 2 164838281807978777675
12
•
74
73

Top

View

Li5
CS
A2
A1
Ao
EALU
CAShs
CASh4
CASh3
CASh2

32
~~

50 ns
31 ns
25 ns

54

• • ~ • • ~~~a"~~Q~~OO~~~

CASOs
CAS07
DOUTo
DOUT1
DOUT2
GND
DOUT3
DOUT4
DOUTs
DOUT6
DOUT7
Vee
DOUTB
GND
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
GND

LF48908JC50
LF48908JC31
LF48908JC25

==================== Video Imaging Products
2-142

07/1219S-LDS.4B90B-D

LF48908
DEVICES INCORPORATED

Two Dimensional Convolver

100-pin

CIN1
CIN2
NC
NC

80
79
78

CIN3

76
75
74
73
72
71
70
69
68

CIN.
CIN5
CINs
CIN7
CINs
CINe
GND
GND
CLK
Vee
Vee
HOLD

ill

cs

A2
A1
Ao
EALU
CASI1.
CASI1.
CASI1.
CASI12
NC
NC
CASI11

50 ns
31 ns
25 ns

77

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
25
27
28
29
30

Top
View

GND
CAS05
NC
CAS06
CAS07
DOUTo
DOun
DOUT2
GND
GND
DOUT.
DOUT.
DOUT5

•

DOUTe

DOUT7
VCC
VCC
DOUTs
GND
GND
DOUTe
DOUno
DOUT11

DOUn2
DOUn.

DOUT14
GND
GND
DOUn5
DOUn6

LF489080C50
LF489080C31
LF489080C25

==================== Video Imaging Products
2·143

07/12/95-LDS.48908·D

LF48908
DEVICES INCORPORATED

Two Dimensional Convolver

84-pln
2

A

3

4

5

6

7

8

9

10

11

,...... ,.... ,.... ,.... ,..... ,.... ,..... ,... ,..... , ...
'_I'
. . } ,_I ,_I ,_I ,_, ,_, ,_I ,_I '..,,'
OE CASOl CAS03 CAS04 CASOo
,..... ,.... ,..... ,.... ,.... ,..... ,.... ,.... ,..... ,.... , ....
'...... ,_I ,_I \ J \ J ,_I ,_I ,_I ,_I ,_I ,_,
CIN5 CIN3 CINl DINs DIN3 CASCo GND CAS02 GND CASOs DOUTo
,.... ,.... , ....
,. .... ,_I
,. ....
,..... , ....
,_I
,_I
,_I
\
,_, '-'

~

,...

'..,,'

CIN2 CINo DIN? DIN5 DIN2 DINl

B

c

)

CINs CIN4

D
E

,...

, ....
,_I

,_I
CINs CIN?
,..... ,_I
,..... , ....
,_,
,_I
ClK GND CIN9

F

G
H

,_I
" ,_I
"
" ,_I
Al Vee HOLD
," I ,_I
"
" ,_I
Cs A2 [5
,_I
" ,_I
"
Ao

J

K

EALU

, ....

DIN4 DINo Vee

CAS07DOUTl
,. .... ,. ....

,_I ,_I
,... ,_I ,__
,_,
DOUT3 DOUT4 DOUTs
,.... ,_I
,.... ,,.__
...
,_,
DOUT2 GND
,..... ,. ....

TopV/ew

Through Package
(i.e., Component Side Pinout)

DOUT7 DOUTs DOUT6
,.... ,..... ,. ....

,_I ,_I ,_I
, ... ,_I
,. ...
,_,

Vee GND DOUTs
DOUTll DOUTl0

,. ... ,_I
,. ....
,_J
DOUT14DOUT12
CASI2 CASll
,.... CASls
,..... ,.... ,..... ,..... ,..... ,..... ,. ....
,_I ,_I \,....I ,_I
,_I
,_I ,_I ,_, ,_I ,_, ,_I
,....

'-'
'-'
CASI1S
CASI13
,..... ,....

,. .... ,_I
,. .... ,_,
,. ....
,_,

CASI14 CASlll CASllo CASI7 CASI4 Vee FRAME DOUT1SDOUT16 GND DOUT13

L

,.. ,.... ,..... ,.... ,..... ,..... ,..... ,..... ,..... ,.... , ...
'..,,'
,_I ,_I ,_I ,_I ,_I ,_I ,_, ,_I ,_I '..,'

CASI12 CASls CASls CASI6 CASI3 RESET CASlo GND DOUT1SDOUT17DOUT1S

50 ns
31 ns
25 ns

LF48908GC50
LF48908GC31
LF48908GC25

50 ns
37 ns
25 ns

LF48908GM50
LF48908GM37
LF48908GM25

50 ns
37 ns
25 ns

LF48908GMB50
LF48908GMB37
LF48908GMB25

==================== Video Imaging Products
2-144

O?/12195-LDS.4S90S-D

-- --- ..-- _-..-----

LF9501

=-:....=:...:
- -=:..--

-~

~

Programmable Line Buffer

o

50 MHz Maximum Operating
Frequency
o Programmable Buffer Length from
2 to 1281 Clock Cycles
o 10-bit Data Inputs and Outputs
o Data Delay and Data Recirculation
Modes
o Supports Positive or Negative Edge
System Clocks
o Expandable Data Word Width or
Buffer Length
o Replaces Harris HSP9501
o Package Style Available:
• 44-pin Plastic LCC, J-Lead

The LF9501 is a high-speed, lO-bit
programmable line buffer. Some
applications the LF9501 is useful for
include sample rate conversion, data
time compression/ expansion, software controlled data alignment, and
programmable serial data shifting. By
using the MODSEL pin, two different
modes of operation can be selected:
delay mode and data recirculation
mode. The delay mode provides a
minimum of 2 to a maximum of 1281
clock cycles of delay between the
input and output of the device. The
data recirculation mode provides a
feedback path from the data output to
the data input for use as a programmable circular buffer.
By using the length control input
(LClo-O) and the length control enable
(LCEN) the length of the delay buffer
or amount of recirculation delay can

MODSEl

lC010·0

be programmed. Providing a delay
value on the LCIO-O inputs and driving
LCEN LOW will load the delay value
into the length control register on the •
next selected clock edge. Two registers, one preceeding the programmable delay RAM and one following,
are included in the delay path. Therefore, the programmed delay value
should equal the desired delay minus
2. This consequently means that the
value loaded into the length control
register must range from 0 to 1279 (to
provide an overall range of 2 to 1281).
The active edge of the clock input,
either positive or negative edge, can
be selected with the clock select
(CLKSEL) input. All timing is based
on the active clock edge selected by
CLKSEL. Data can be held temporarily by using the clock enable
(CLKEN) input.

lCEN

w

-'
C!l

0:

D19·0

w

tii

10

(!j

w

::<
« «
::< 0:
::<
«
0:
(!)

0:

~
w

0 0
0:
Il.

OE
0:

10

w

I-

en

(!j

10

D09'()

w

0:

10

ClKSEl
ClKEN

0:

B~
00:
-'w
w

TO All REGISTERS

()Z

ClK

(!)

===================== Video Imaging Products
2-145

06/29/95-LDS.9501-C

-

• .........
.-=a
-.. -......----- -.......
-~ -~--

LF9501

--~~-

DEVICES INCORPORATED

Programmable Line Buffer

SIGNAL DEFINITIONS

Outputs

CLKSEL - Clock Select

Power

D09-0 - Data Output

VccandGND

The lO-bit data output appears on
009-0 on the Nth clock cycle, where N
is the overall delay (desired delay).

The CLKSEL control allows the
selection of the active edge of CLK. A
LOW on CLKSEL selects negativeedge triggering of the device. Driving
CLKSEL HIGH selects positive-edge
triggering. All timing specifications
are referrenced to the selected active
edgeofCLK.

+5 V power supply. All pins must be
connected.
Clock

CLK - Master Clock
The active edge of CLK, selected by
CLKSEL, strobes all registers. All
timing specifications are referenced to
the active edge of CLK.
Inputs

DI9-0 - Data Input
lO-bit data, from the data input, is
latched into the device on the active
edge of CLK when MODSEL is LOW.

Controls

LCEN - Length Control Enable
When LCEN is driven LOW, the next
active clock edge will cause the
loading of the delay value present at
the LClo-o input.

OE - Output Enable
The Output Enable controls the state
of 009-0. Driving OE LOW enables
the output port. When OE is HIGH,
009-0 is placed in a high-impedance
state. The internal transfer of data is
not affected by this control.

LClO-0 - Length Control Input
The II-bit value is used to specify the
length of the delay buffer, between
DI9-0 and D09-O, or the amount of
recirculation delay. An integer value
ranging from 0 to 1279 is used to
select a delay ranging from 2 to 1281
clock cycles. The value placed on the
LCIO-O inputs is equal to the desired
delay minus 2. The data presented on
LCIO-O is loaded into the device on the
active edge of CLK, selected b L CLKSEL, in conjunction with LCEN
being driven LOW.

MODSEL - Mode Select
The Mode Select pin is used to choose
the desired mode of operation: data
delay mode or data recirculation
mode. Driving MODSEL LOW places
the device in the delay mode. The
device operates as a programmable
pipeline register. New data from the
019-0 input is loaded on every active
edge of CLK. Driving MODSEL
HIGH places thedevice in the data
recirculation mode. The device
operates as a programmable circular
buffer. The output of the device is
routed back to the input. MODSEL
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.

CLKEN - Clock Enable
The Clock Enable control enables and
disables the CLK input. Driving
CLKEN LOW enables CLK and causes
the device to operate in a normal
fashion. When CLKEN is HIGH, CLK
is disabled and the device will hold all
internal operations and data. CLKEN
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
The changing of CLKEN takes effect
on the active edge of CLK following
the edge in which it was latched.

====================Video Imaging Products
2·146

06/29/95-LDS.9501-C

- -.-....-._
- -------.......
----- --~---

-

LF9501

DEVICES INCORPORATED

Programmable Line Buffer

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ....... ....... ................................................................ -0.5 V to Vee + 0.5 V

•

Signal applied to high impedance output ...................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Temperature Range (Ambient)
O°C to +70°C

Active Operation, Commercial

Symbol

Parameter

Test Condition

Min

VOH

Output High Voltage

Vee

=Min., IOH =-4.0 mA

VOL

Output Low Voltage

Vee

=Min., IOl =4.0 mA

VlH

Input High Voltage

Vll

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground::; VIN ::; Vee (Note 12)

±10

~

Output Leakage Current

Ground::; VOUT::; Vee (Note 12)

±10

~

leel

Vee Current, Dynamic

(Notes 5, 6)

125

mA

lee2

Vee Current, Quiescent

(Note 7)

500

~

CIN

Input Capacitance

TA =25°C, f

=1 MHz

10

pF

COUT

Output Capacitance

TA

=25°C, f =1 MHz

10

pF

===================== Video Imaging Products
2·147

06/29/95-LDS.9501·C

........
=--=---------=-............
.-------.-..---DEVICES INCORPORATED

LF9501

~

Programmable Line Buffer

elK' _ _ _ I

MOOSEl

009-0

:::::::::::::j]~~~::::::::::~!H~IG~H~IM~P~E~DA~N~C~E1=::::::::::::::::::

tDIS

tENA

OE _______________________- J I

'When ct:KSEL is HIGH, assume elK is inverted.

==================== Video Imaging Products
2-148

06/29/95-LDS.9501-C

-........ ---==-==

==
=
-""-""---

LF9501

.-..~.....--~

DEVICES INCORPORATED

Programmable Line Buffer

~----------~~~~II

/

ClK'

tESJ

1

/

r

tpw

ClKEN
INTERNAL
CLOCK

ClK'

"
tlES

lCEN

lC1O-0

J

" W"iJ
/

"-

'--r-

/

/

tlEH

~

tlS

ltEs

"-

/

~

/

/

:;I£-

.1

J tlH

:*:

:*:

'When ClKSEl is HIGH, assume ClK is inverted_

==================== Video Imaging Products
2-149

06129195-LDS.9501-C

-

- ---

=~~=~
=-=-=
=-==:L..i;'
-~---

LF9501

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.

3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

Programmable Line Buffer

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tors test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDiSABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vec

d.
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

~n

a. A O.lI1F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary should be installed between device Vee
from those designated but operation is and the tester common, and device
ground and tester common.
guaranteed as specified.
5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated must be brought directly to the DUT
by:
NCV2 F
socket or contactor fingers.

4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 25 MHz clock
rate.
7. Tested with all inputs within 0.1 Vof
Vee or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

+---t--o OUTPUT
n+

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from

=====================Video Imaging Products
2-150

06129195-LDS.9501-C

- -......
--- --......- -------------.....-.
~-

LF9501

-~--~

DEVICES INCORPORATED

Programmable Line Buffer

44-pin
...J

I~

Iw
w
oo~~"'8c3ug
CJJ

Z

zzuug...J...J...J::E

6 5 4 :l 2 1 4443424140
39

•

003
004
Vee
GND
005
DO.
007
DOs

Top
View

17
29
18 19 20 21 22 23 24 25 26 27 28

•

010
011
012
013
014
Vee
GND
015
01.
017
Dis

O)IUJo..-oO)col'-coO)u
8 o ggggggg oz

40 ns
31 ns
25 ns
20 ns

LF9501JC25
LF9501JC20

==================== Video Imaging Products
2-151

06/29/95-LDS.9501-C

= ........ ---

=-=~=Ifr"!!.

=-~~=~
-~---

DEVICES INCORPORATED

-- ----- --::.-. --=-=-=
.::-=-:.-. . -.-

-~

DEVICES

LF9502

INCORPORATE~

2K Programmable Line Buffer

o 50 MHz Maximum Operating
o
o
o
o
o
o

Frequency
Programmable Buffer Length from
2 to 2049 Clock Cycles
10-bit Data Inputs and Outputs
Data Delay and Data Recirculation
Modes
Supports Positive or Negative Edge
System Clocks
Expandable Data Word Width or
Buffer Length
Package Style Available:
• 44-pin Plastic LCC, J-Lead

The LF9502 is a high-speed, lO-bit
programmable line buffer. Some
applications the LF9502 is useful for
include sample rate conversion, data
time compression/ expansion, software controlled data alignment, and
programmable serial data shifting. By
using the MODSEL pin, two different
modes of operation can be selected:
delay mode and data recirculation
mode. The delay mode provides a
minimum of 2 to a maximum of 2049
clock cycles of delay between the
input and output of the device. The
data recirculation mode provides a
feedback path from the data output to
the data input for use as a programmable circular buffer.
By using the length control input
(LClO-O) and the length control enable
(LCEN) the length of the delay buffer
or amount of recirculation delay can

MODSEL

LC010·0

W

..J

D19'{)

w

f-

CIJ

lO

aw

::;:

::;: >-

«
::l
O:w
(!)O

0:

The active edge of the clock input,
either positive or negative edge, can
be selected with the clock select
(CLKSEL) input. All timing is based
on the active clock edge selected by
CLKSEL. Data can be held temporarily by using the clock enable
(CLKEN) input.

LCEN

«
«
::;: 0:
III

0:

be programmed. Providing a delay
value on the LCIO-O inputs and driving
LCEN LOW will load the delay value
into the length control register on the
next selected clock edge. Two regiSters, one preceeding the programmable delay RAM and one following,
are included in the delay path. Therefore, the programmed delay value
should equal the desired delay minus
2. This consequently means that the
value loaded into the length control
register must range from 0 to 2047 (to
provide an overall range of 2 to 2049).

0:><:
g:C\I

OE
0:
W

10

Iii

aw

10

DQg·o

0:

10

CLKSEL
CLKEN
CLK

0:

:><:~

u «
00:
..J w
uz
w

TO ALL REGISTERS

(!)

==================== Video Imaging Products
2-153

06/29/95-LDS.9502-B

LF9502
DEVICES INCORPORATED

2K Programmable Line Buffer

SIGNAL DEFINITIONS

Outputs

CLKSEL - Clock Select

Power

D09-0 - Data Output

VccandGND

The lO-bit data output appears on
D09-O on the Nth clock cycle, where N
is the overall delay (desired delay).

The CLKSEL control allows the
selection of the active edge of CLK. A
LOW on CLKSEL selects negativeedge triggering of the device. Driving
CLKSEL HIGH selects positive-edge
triggering. All timing specifications
are referrenced to the selected active
edgeofCLK.

+5 V power supply. All pins must be
connected.
Clock

CLK - Master Clock
The active edge of CLK, selected by
CLKSEL, strobes all registers. All
timing specifications are referenced to
the active edge of CLK.
Inputs

DI9-0 - Data Input
lO-bit data, from the data input, is
latched into the device on the active
edge of CLK when MODSEL is LOW.

Controls

LCEN - Length Control Enable
. When LCEN is driven LOW, the next
active clock edge will cause the
loading of the delay value present at
the LClO-O input.
OE -

Output Enable

The Output Enable controls the state
of D09-o. Driving OE LOW enables
the output port. When OE is HIGH,
D09-o is placed in a high-impedance
state. The internal transfer of data is
not affected by this control.

LOO-o - Length Control Input
The I1-bit value is used to specify the
length of the delay buffer, between
D19-0 and D09-O, or the amount of
recirculation delay. An integer value
ranging from 0 to 2047 is used to
select a delay ranging from 2 to 2049
clock cycles. The value placed on the
LOo-o inputs is equal to the desired
delay minus 2. The data presented on
LOo-o is loaded into the device on the
active edge of CLK, selected b~
CLKSEL, in conjunction with LCEN
being driven LOW.

MODSEL - Mode Select
The Mode Select pin is used to choose
the desired mode of operation: data
delay mode or data recirculation
mode. Driving MODSEL LOW places
the device in the delay mode. The
device operates as a programmable
pipeline register. New data from the
D19-0 input is loaded on every active
edge of CLK. Driving MODSEL
HIGH places the device in the data
recirculation mode. The device
operates as a programmable circular
buffer. The output of the device is
routed back to the input. MODSEL
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.

CLKEN - Clock Enable
The Clock Enable control enables and
disables the CLK input. Driving
CLKEN LOW enables CLK and causes
the device to operate in a normal
fashion. When CLKEN is HIGH, CLK
is disabled and the device will hold all
internal operations and data. CLKEN
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
The changing of CLKEN takes effect
on the active edge of CLK following
the edge in which it was latched.

==================== Video Imaging Products
2-154

06/29/95-LDS.9502·B

LF9502
DEVICES INCORPORATED

2K Programmable Line Buffer

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to +125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ................................................. ........... .................. -0.5 V to Vee + 0.5 V

•

Signal applied to high impedance output ...................................................................... -0.5 V to Vee + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Active Operation, Commercial

Symbol

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee

=Min., IOH =-4.0 mA

VoL

Output Low Voltage

Vee

=Min., IOL =4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground

S;

loz

Output Leakage Current

Ground

S;

lee1

Vee Current, Dynamic

lee2

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

VIN s; Vee (Note 12)

±10

~

VOUT s; Vee (Note 12)

±10

~

(Notes 5,6)

125

mA

Vee Current, Quiescent

(Note 7)

500

~

CIN

Input Capacitance

TA =25°C, f =1 MHz

10

pF

COUT

Output Capacitance

TA =25°C, f =1 MHz

10

pF

===================== Video Imaging Products
2·155

06/29/95-LDS.9502·B

-.,---= - -----

~~=..-=.

--

LF9502

---...-.~--

-~---

DEVICES INCORPORATED

2K Programmable Line Buffer

elK' _ _........1

MODSEl

D09·0

======j=*XIDk:=====f~~~~~=========
tDIS

OE _______________________

tENA

~

*When ClKSEl is HIGH, assume ClK is inverted.

====================Video Imaging Products
2·156

06/29/95-LDS.9502·B

----- -- ..-----_---.....-.--~~-.-...

LF9502

-~---

DEVICES INCORPORATED

2K Programmable Line Buffer

/

ClK'

tESJ

1

/

t

tpw

ClKEN
INTERNAL
CLOCK

\..

/

/

\..

l~iJ

'--

/

\..

r-

ltEs

\..

ClK' _ _..I
tLES - t - - - t - - t L E H

tLS -t-----i--+_ tLH

lCl0·0 _ _ _-../"-_-+-..71'-_____________________

'When ClKSEl is HIGH, assume ClK is inverted.

==================== Video Imaging Products
2·157

06/29/95-LDS.9502·B

-- -- ---.......
=-=-==..==

--~--~----~---

LF9502

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.

2K Programmable Line Buffer

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at

the high temperature extreme, which is
the worst case for leakage current.

VCC

do

3. This device provides hard clamping This device has high-speed outputs ca-

of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

}

pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

~n

a. A 0.1 J.lF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary should be installed between device Vee
from those designated but operation is and the tester common, and device
guaranteed as specified.
ground and tester common.
5. Supply current for a given applica-

b. Ground and Vee supply planes
tion can be accurately approximated must be brought directly to the DUT
by:
NCV2 F
socket or contactor fingers.

4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 25 MHz clock
rate.
7. Tested with allinputs within 0.1 Vof
Vee or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.

t--""1--o OUTPUT

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from

n+
D1
p-

-==::~~~~~~==
t

TRISTATE
OUTPUTS_

O.2V

O.2V

===================== Video Imaging Products
2·15B

06129195-LDS.9502·B

--- -- -----------'"-"'--------..--.
........
....--..-.-.

-.-..-.

LF9502

~

DEVICES INCORPORATED

2K Programmable Line Buffer

44-pin

5 4 3 2 1 4443 42 41 40
39
•

000

•

010

Oh
DO.

004
Vee

GND

11

Top
View

DOs

000
007
008

40 ns
31 ns
25 ns
20 ns

17
29
18 19 20 21 22 23 24 25 26 27 28

012
01.
014
Vee

GNO
Dis
016
017
018

LF9502JC40
LF9502JC31
LF9502JC25
LF9502JC20

= = = = = = = = = = = = = = = = = = = = Video Imaging Products
2·159

06/29/95-LDS.9502·B

----,.,
-- --.......--------

--

~.:.=-=-

.-..........-.----~

DEVICES INCORPORATED

--------..- --- -----

_

-~-
.........
_ _ -.-r

-~---

DEVICES INCORPORATED

Arithmetic Logic Units & Special Arithmetic Functions

Multipliers

Product Listing

•

DEVICES INCORPORATED

Arithmetic Logic Units & Special Arithmetic Functions

ARITHMETIC LOGIC UNITS & SPECIAL ARITHMETIC FUNCTIONS ............................................... 3-1
Arithmetic Logic Units
L4C381
16-bit Cascadable ALU ........................................................................................................................................ 3-3
Special Arithmetic Functions
LSH32
32-bit Cascadable Barrel Shifter ....................................................................................................................... 3-15
LSH33
32-bit Cascadable Barrel Shifter with Registers ............................................................................................. 3-25 . .
LlOC23
64 x 1 Digital Correlator .................................................................................................................................... 3-33

3-1

DEVICES INCORPORATED

- -- --- =-=:...:
------==-=--

L4C381

-~---

16-bit Cascadable ALU

DEVICES INCORPORATED

o
o
o
o
o
o

The L4C381 is a flexible, high speed,
cascadable 16-bit Arithmetic and
Logic Unit. It combines four 381-type
4-bit ALUs, a look-ahead carry
generator, and miscellaneous interface
logic - all in a single 68-pin package.
While containing new features to
support high speed pipelined architectures and single 16-bit bus configurations, the L4C381 retains full performance and functional compatibility with
the bipolar '381 designs.

High-Speed (15ns), Low Power
16-bit Cascadable ALU
Implements Add, Subtract, Accumulate, Two's Complement, Pass,
and Logic Operations
All Registers Have a Bypass Path
for Complete Flexibility
DESC SMD No. 5962-89959
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 68-pin Plastic LCC, J-Lead
• 68-pin Ceramic LCC
• 68-pin Ceramic PGA

The L4C381 can be cascaded to
perform 32-bit or greater operations.
See "Cascading the L4C381" toward

A1S-Ao

815-80

ENA --~

the end of this data sheet for more
information.
ARCHITECTURE
The L4C381 operates on two 16-bit
operands (A and B) and produces a
. .
16-bit result (F). Three select lines
control the ALU and provide 3
arithmetic, 3 logical, and 2 initialization functions. Full ALU status is
provided to support cascading to
longer word lengths. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal
feedback path allows the registered
ALU output to be routed to one of the
ALU inputs, accommodating chain
operations and accumulation. Furthermore, the A or B input can be
forced to Zero allowing unary functions on either operand.
ALU OPERATIONS

FTAB

;.--+---...;27L--_

4

P, G, C1. +-_---;5.<.-_ __\.
OVF, Z

FTF

'---r----'

OSA
OSB

S2·So. Co

The 52-So lines specify the operation
to be performed. The ALU functions
and their select codes are shown in
Table 1.
The two functions, B minus A and
A minus B, can be achieved by setting
the carry input of the least significant
slice and selecting codes 001 and OlD
respectively.

--------~

~ ---------~

ClK - - . TO All REGISTERS

F15·Fo

======================Arithmetic Logic Units
3·3

06119195-LDS,381·L

L4C381
DEVICES INCORPORATED

16-bit Cascadable ALU

ALUSTATUS
The ALU provides Overflow and Zero
status bits. Carry, Propagate, and
Generate outputs are also provided
for cascading. These outputs are
defined for the three arithmetic
functions only. The ALU sets the Zero
output when all 16 output bits are
zero. The Generate, Propagate, C16,
and OVF flags for the A + B operation
are defined in Table 2. The status
flags produced for NOT(A) + B and
A + NOT(B) can be found by complementing Ai and Bi respectively in
Table 2.

Bit Carry Generate = gi = AiBi
Bit Carry Propagate =pi =Ai + Bi

fori=O ... 15
fori=O ... 15

Po = po
Pi = pi (PH)

fori=1 ... 15

and
Go = go
Gi = gi + pi (Gi-l)
Ci = Gi-l + Pi-l (Co)

for i = 1 ... 15
for i = 1 ... 15

then

G
OPERAND REGISTERS
The L4C381 has two 16-bit wide input registers for operands A and B.
These registers are rising edge triggered by a common clock. The A
register is enabled for input by setting
the ENA control LOW, and the B
register is enabled for input by setting
the ENB control LOW. When either
the ENA control or ENB control is
HIGH, the data in the corresponding
input register will not change.
This architecture allows the L4C381 to
accept arguments from a single 16-bit
data bus. For those applications that
do not require registered inputs, both
the A and B operand registers can be
bypassed with the FTAB control line.
When the FTAB control is asserted
(FTAB = HiGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
OUTPUT REGISTER
The output of the ALU drives the
input of a 16-bit register. This risingedge-triggered register is clocked by
the same clock as the input registers.
When the ENF control is LOW, data
from the ALU will be clocked into the

= NOT(G1S)
= NOT(P1S)
C16 = G1S + P1SCO
OVF = C1S XOR C16
j5

output register. By disabling the
output register, intermediate results
can be held while loading new input
operands. Three-state drivers controlled by the OE input allow the
L4C381 to be configured in a single
bidirectional bus system.
The output register can be bypassed
by asserting the FTF control signal
(FTF = HiGH). When the FTF control When both operand select lines are
low, the L4C381 is configured as a
is asserted, output data is routed
chain
calculation ALU. The registered
around the output register, however,
ALU output is passed back to the B
it continues to function normally via
input to the ALU. This allows accuthe ENF control. The contents of the
output register will again be available mulation operations to be performed
by providing new operands via the A
on the output pins if FTF is released.
With both FTAB and FTF true (HiGH) input port. The accumulator can be
the L4C381 is functionally identical to preloaded from the A input by setting
OSA true. By forcing the function
four cascaded 54S381-type devices.
select lines to the CLEAR state (000),
the accumulator may be cleared. Note
OPERAND SELECTION
that this feedback operation is not
The two operand select lines, OSA and affected by the state of the FTF
OSB, control multiplexers that precede control. That is, the F outputs of the
the ALU inputs. These multiplexers
L4C381 may be driven directly by the
provide an operand force-to-zero
ALU. The output register continues to
function as well as F register feedback function, however, and provides the
to the B input. Table 3 shows the
ALU B operand source.
inputs to the ALU as a function of the
operand select inputs. Either the A or
B operands may be forced to zero.

===================== Arithmetic Logic Units
3-4

06/19/95-LDS.381-L

-.-.--..------------- -........
....-..

--~-

L4C381

~--....

-~---

DEVICES INCORPORATED

16-bit Cascadable ALU

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current. ........................................................ ..... .................................. ............... ................. > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Military

Symbol

4.75 V ~ Vee

~

5.25 V

-55°C to + 125°C

4.50 V ~ Vee

~

5.50 V

Parameter

Test Condition

VoH

Output High Voltage

Vee

VoL

Output Low Voltage

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

Ground ~ VIN

loz

Output Leakage Current

Ground

lee1

Vee Current, Dynamic

(Notes 5,6)

lee2

Vee Current, Quiescent

(Note 7)

Min

=Min., IOH =-2.0 mA
Vee =Min., IOL =8.0 mA

~

Supply Voltage

O°Cto +70°C

Active Operation, Commercial

~

VOUT

•

Typ

Max

2.4

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Vee (Note 12)

±20

j.tA

~

±20

j.tA

30

mA

1.5

mA

Vee (Note 12)
15

=====================Arithmetic Logic Units
3-5

06119195-LDS.381·L

...--_---- .-............- --------.--......-.
--'""-'"~-~

L4C381

DEVICES INCORPORATED

FlAB = 0, FlF=O
Clock

16-bit Cascadable ALU

F1S-Fo

P,G

OVF,Z

32

38

53
34

36
22

42

42

42

56
37

38

53
34

36
22

30

55

42

42

42

40

36

46

37

Co
S2-S0, OSA, OS8

C16 F1S-Fo

26

P,G

OVF,Z

C16 F1S-Fo

44

32

28

20

34

35

44
28

32
20

32

34

35

30

40

32

30
32

P,G

OVF,Z

C16

22

26

22

22

18

18

22

22

22

28
22

22

26
18

22
18

26

22

22

22

22

22

22

18

18

22

22

22

FTAB = 0, FTF= 1
Clock
Co
S2-S0, OSA, OS8
FlAB = 1, FTF = 0
A15-Ao, 815-80
Clock

46

32

FlAB = 1, FlF = 1
A15-Ao, 815-80

22

26

Co
S2-S0, OSA, OS8

30

42

34

22

42

42

28

20

32

34

35

55

36

46

37

40

30

40

32

26

22

22

22

38

53

30

44

32

28

22

26

22

34

36
22

46

Co

56
37

28

20

22

S2-S0, OSA, OS8

55

42

42

42

34

35

26

Clock (OSA, OS8 = 0)

30
40

L4C381-55

Input

32

L4C381-40

FTAB=O

FlAB = 1

FTAB=O

Setup Hold

Setup Hold

Setup Hold

22

18

18

22

22

L4C381-26

FTAB = 1

FlAB =0

Setup Hold Setup Hold

FTAB = 1

Setup Hold

A15-Ao, 815-80

8

2

35

2

8

2

28

2

8

2

16

2

Co

21

0

21

0

16

0

16

0

8

0

8

0

S2-S0, OSA, OS8

44

0

44

0

32

0

32

0

18

0

18

0

ENA, EN8, ENF

10

2

10

2

10

2

10

2

8

2

8

2

L4C381-55

L4C381-40

L4C381-26

tENA

20

18

16

tDIS

20

18

16

L4C381-55

L4C381-40

L4C381-26

Minimum Cycle Time

43

34

20

Highgoing Pulse

15

10

10

Lowgoing Pulse

15

10

10

Arithmetic Logic Units
3-6

06/19/95-LDS.381-L

-

....... .......

=

_.......

--.-.....-.....-==~E==

L4C381

-~---

DEVICES INCORPORATED

FTAB=O,FTF=O
Clock

16-bit Cascadable ALU

F15-Fo

P,G

OVF,Z

11

20

20

20

14

14

18

20

18

20

20

20

15

14

14

14

18

20

18

15

16

20

17

Co
S2-S0, OSA, OSB
FTAB = 0, FTF = 1
Clock

20

Co

18

S2-S0, OSA, OSB

20

C16 F15-Fo

11

P,G

OVF,Z

C16

15

15

15

13

13

14

15

14

15

15
13

15
13

14

15

14

14

15

14

13

13

14

15

14

•

FTAB = 1, FTF = 0
A15-Ao, B15-Bo
Clock

11

11

Co
S2-S0, OSA, OSB
FTAB = 1, FTF = 1
A15-Ao, B15-Bo

14

14

18

20

18

20

16

20

17

15

14

15

14

Clock (OSA, OSB = 0)

20

20

20

20

15

15

15

15

Co

18

14

14

14

13

13

S2-S0, OSA, OSB

20

20

18

15

15

14

18

L4C381-20

Input

14

L4C381-15

FTAB=O

FTAB=1

FTAB=O

FlAB = 1

Setup Hold

Setup Hold

Setup Hold

Setup Hold

A15-Ao, B15-Bo

5

0

14

0

5

0

12

0

Co

12

0

12

0

10

0

10

0

S2-S0, OSA, OSB

15

0

15

0

12

0

12

0

ENA, ENB, ENF

5

0

5

0

5

0

5

0

L4C381-20

L4C381-15

tENA

8

6

tDIS

8

6

L4C381-20

L4C381-15

Minimum Cycle Time

18

14

Highgoing Pulse

5

4

Lowgoing Pulse

5

4

Arithmetic Logic Units
3-7

06/19/95-LDS.381-L

----- -- -----=-=-==-==:......r
--.-..------.-~

L4C381

DEVICES INCORPORATED

FTAB = 0, FTF = 0
Clock

16-bit Cascadable ALU

F1S-Fo

P,G

OVF,Z

37

44

63
42

45
25

48

48

48

63

45

56

42

25

32
46

Co
S2-S0, aSA, aSB
FlAB = 0, FlF = 1
Clock

C16 F1S-Fo

68
42

44

Co
S2-S0, aSA, aSB

66

48

48

48

44

56

44

FTAB = 1, FTF = 0
A15-Ao, B15-Bo
Clock

28

37

Co
S2-S0, aSA, aSB

42

25

48

48

65

44

56

44

45

44

63
42

45

56

Co

68
42

25

32

S2-S0, aSA, aSB

66

48

48

48

46

Clock (aSA, aSB = 0)

34

50
32

34
23

38

38

38

34

50
32

34
23

38

38

38

32

46

36

P,G

OVF,Z

C16

28

34
22

28
22

28

28

28

34
26

28

34
22

28
22

30

28

28

28

28

28

28

22

22

28

28

28

28

C16 F1S-Fo

26

26
32

23

38

38

32

46

36

30

28

28

34

50

34

34

28

34

28

32

23

26

22

22

38

38

30

28

28

38

L4C381-65

Input

OVF,Z

28
48

FlAB = 1, FlF = 1
A15-Ao, B15-Bo

P,G

38

L4C381-45

28

L4C381-30

FTAB=O

FlAB = 1

FTAB=O

FTAB= 1

FTAB=O

FTAB=1

Setup Hold

Setup Hold

Setup Hold

Setup Hold

Setup Hold

Setup Hold

A15-Ao, B15-Bo

10

3

43

3

8

3

33

3

8

3

20

3

Co

25

0

25

0

20

0

20

0

12

0

12

0

S2-S0, aSA, aSB

50

0

50

0

36

0

36

0

20

0

20

0

ENA, ENB, ENF

12

2

12

2

10

2

10

2

10

2

10

2

L4C381-65

L4C381-45

L4C381-30

tENA

22

20

18

tDIS

22

20

18

L4C381-65

L4C381-45

L4C381-30

Minimum Cycle Time

52

38

26

Highgoing Pulse

20

15

12

Lowgoing Pulse

20

15

12

Arithmetic Logic Units
3-8

06/19/95-LDS.381-L

- ------ --------- -~~-~

-..-.

L4C381

-..-.

-~---

DEVICES INCORPORATED

16-bit Cascadable ALU

F1S-Fo

P,G

OVF,Z

14

24

24

24

18

18

22

24

22

24

24

24

Co

25
21

18

S2-S0, OSA, OSB

25

22

24

20

25

22

FTAB = 0, FTF= 0
Clock
Co
S2-S0, OSA, OSB
FTAB=0,FTF=1
Clock

FTAB = 1, FTF = 0
A15-Ao, B15-Bo
Clock

P,G

OVF,Z

C16

20

20

20

16

16

18

20

18

20

18

20
17

20
16

20
16

22

20

18

20

18

17

20

17

16

16

18

20

18

C16 F1S-Fo

14

14

14

Co
S2-S0, OSA, OSB
FTAB = 1, FTF = 1
A15-Ao, B15-Bo
Clock (OSA, OSB = 0)

22

18

18

24

22

25

20

25

22

20

17

20

17

25

24

24

24

20

20

20

18

18

17

16

20
16

22

24

22

20

18

20

18

Co

21

S2-S0, OSA, OSB

25

L4C381-25

Input

..

L4C381-20

FTAB=O

FTAB = 1

FTAB=O

FTAB= 1

Setup Hold

Setup Hold

Setup Hold

Setup Hold

A15-Ao, B15-Bo

7

2

14

2

6

2

12

2

Co

14

0

14

0

12

0

12

0

S2-S0, OSA, OSB

19

0

19

0

16

0

16

0

ENA, ENB, ENF

7

0

7

0

6

0

6

0

L4C381-25

L4C381-20

tENA

14

10

Minimum Cycle Time

tDIS

14

10

L4C381-25

L4C381-20

20

18

Highgoing Pulse

8

6

Lowgoing Pulse

8

6

Arithmetic Logic Units
3-9

06/19/95-LDS.381-L

L4C381
DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operationofthese products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

16-bit Cascadable ALU

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tOISABLE
measurements, the load current is
increased to 10 rnA to reduce the RC
delay component of the measurement.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

a. A 0.1 ~F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
ground and tester common.
anteed as specified.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vce

d,
}
~r

5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated by: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.
where

4

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case re8. These parameters are guaranteed
quirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

====================== Arithmetic Logic Units
3·10

06/1 9/95-LDS.381·L

............ _-- --.--.-------- -

----~-

L4C381

DEVICES INCORPORATED

16-bit Cascadable ALU

___

~

....... _

_..r

-~---

Cascading the L4C381 to 32 bits is
accomplished simply by connecting
the C16 output of the least significant
slice to the Co input of the most significant slice. The 52-So, OSA, OSB,
ENA, ENB, and ENF lines are
common to both devices. The Zero
output flags should be logically
ANDed to produce the Zero flag for
the 32-bit result. The OVF and C16
outputs of the most significant slice
are valid for the 32-bit result.
Propagation delay calculations for this
configuration require two steps: First
determine the propagation delay from
the input of interest to the C16 output
of the lower slice. Add this number
to the delay from the Co input of the
upper slice to the output of interest

(of the Co setup time, if the F register
is used). The sum gives the overall
input-to-output delay (or setup time)
for the 32-bit configuration. This
method gives a conservative result,
since the C16 output is very lightly
loaded. Formulas for calculation of
all critical delays for a 32-bit system
are shown in Figures 4A through 4D.
Cascading to greater than 32 bits can
be accomplished in two ways: The
simplest (but slowest) method is to
simply connect the C16 output of each
slice to the Co input of the next more
significant slice. Propagation delays
are calculated as for the 32-bit case,
except that the Co to C16 delays for all
intermediate slices must be added to
the overall delay for each path. A

faster method is to use an external
carry-Iookahead generator. The P and
G outputs of each slice are connected
as inputs to the CLA generator, which
in turn produces the Co inputs for
each slice except the least significant.
The C16 outputs are not used in this
case, except for the most significant
one, which is the carry out of the
•
overall system. The carry in to the
system is connected to the Co input of
the least significant slice, and also to
the carry lookahead generator.
Propagation delays for this configuration are the sum of the time to P, G,
for the least significant slice, the
propagation delay of the carry lookahead generator, and the Co to output
time of the most significant slice.

====================== Arithmetic Logic Units
3-11

OS/19/95-LDS.381-L

- -.. --------_
..:::...,... -

• ~~=.=a-

L4C381

-~

DEVICES INCORPORATED

16-bit Cascadable ALU

From

To

Calculated Specification Limit

Clock
Clock
Co
52-So, OSA, OSB
A,B
Co
52-So, OSA, OSB
ENA,ENB,ENF
Minimum cycle time

..... F

Same as 16-bit case
(Clock ..... C16) + (Co ..... Out)
(Co ..... C16) + (Co ..... Out)
(52-SO, OSA, OSB ..... C16) + (Co ..... Out)
Same as 16-bit case
(Co ..... C16) + (Co Setup time)
(52-So, OSA, OSB ..... C16) + (Co Setup time)
Same as 16-bit case
(Clock ..... C16) + (Co Setup time)

..... Other
..... Other
..... Other
Setup time
Setup time
Setup time
Setup time

----------------------------1

-----------------------1
A3,-A,.

B31-B16

:

A15-Ao

B15-Bo

:

I

I

I

I

I
I

I
I

I

CLOCK

:
I

Co,So-S2
:
OSA,OSB :
I
I

I
I
I
I

I
I

I
I

MOST
SIGNIFICANT
SLICE

I

:

I

F31-F1.

F15-Fo

~

From

To

.....

Clock
Clock

Co
Co
52-SO, OSA, OSB
S2-S0, OSA, OSB
A,B
Co
S2-S0, OSA, OSB
ENA, ENB, ENF
Minimum cycle time

.....
.....
.....
.....

.....

:

____________________________ J

LEAST
SIGNIFICANT
SLICE

Calculated Specification Limit
(Clock ..... C16) + (Co ..... F)
(Clock ..... C16) + (Co ..... Out)
(Co ..... C16) + (Co ..... F)
(Co ..... C16) + (Co ..... Out)
(S2-S0, OSA, OSB ..... C16) + (Co ..... F)
(S2-S0, OSA, OSB ..... C16) + (Co ..... Out)
Same as 16-bit case
(Co ..... C16) + (Co Setup time)
(S2-S0, OSA, OSB ..... C16) + (Co Setup time)
Same as 16-bit case
(Clock ..... C16) + (Co Setup time)

F
Other
F
Other

F

Other
Setup time
Setup time
Setup time
Setup time

,-----------------------

I

I

I
I
I
:
I

A31-A1.

B3,-B,.

I

A15-Ao

:

B15-Bo

I
I
I
I

CLOCK

I
I

CO,SO-S2
OSA,OSB

I
I
I

I
I

I

MOST
SIGNIFICANT
SLICE

I
I

I

I
I

: ______________________
F31-F16
I
JI
I

:
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI

I

~

~~~

LEAST
SIGNIFICANT
SLICE

====================== Arithmetic Logic Units
3-12

06l19/95-LOS.381-L

L4C381
DEVICES INCORPORATED

16-bit Cascadable ALU

From
Clock
A,B

Calculated Specification Limit
Same as l6-bit case
(A, B -+ C16) + (Co -+ Out)
(Co -+ CIS) + (Co -+ Out)
(52-So, OSA, OSB -+ C16) + (Co -+ Out)
(A, B -+ C16) + (Co Setup time)
(Co -+ CIS) + (Co Setup time)
(52-SO, OSA, OSB -+ CIS) + (Co Setup time)
Same as l6-bit case
(Clock -+ CIS) + (Co Setup time)

To

F

-+
-+
-+
-+

Other
Other
Other
Setup time
Setup time
Setup time
Setup time

Co

52-So, OSA, OSB
A,B
Co
52-So, OSA, OSB
ENA,ENB,ENF
Minimum cycle time
(F register accumulate loop)

..

r----------------------~

A31-Al.

I

B3,-B,.

A1S-Ao

I
I

B1S-Bo

I

CO,So-S2
OSA,OSB

I

I
I

I
I
I

I
I

CLOCK:

MOST
SIGNIFICANT
SLICE

CLOCK

I
I

F31-F16

I

L ______________________

From
A,B
A,B

I
I
I
I

I
I
I
I

J:

:

F15-Fo

I ______ ------------~----------

To

Calculated Specification Limit
(A, B -+ CIS) + (Co -+ F)
(A, B -+ CIS) + (Co -+ Out)
(Co -+ C16) + (Co -+ F)
(Co -+ CIS) + (Co -+ Out)
(52-SO, OSA, OSB -+ CIS) + (Co -+ F)
(52-SO, OSA, OSB -+ CIS) + (Co -+ Out)
(A, B -+ C1S) + (Co Setup time)
(Co -+ CIS) + (Co Setup time)
(52-SO, OSA, OSB -+ C16) + (Co Setup time)
Same as l6-bit case
(Clock -+ CIS) + (Co Setup time)

-+
-+
-+
-+
-+
-+

F
Other
F
Other
F
Other
Setup time
Setup time
Setup time
Setup time

Co
Co
52-SO, OSA, OSB
52-SO, OSA, OSB
A,B

Co

52-SO, OSA, OSB
ENA,ENB,ENF
Minimum cycle time
(F register accumulate loop)

---------------------~
I
A31-Al.
B31-B16
I
I

I
I
I
I

I----------------------------~

:

A1S-Ao

16
F31-Fl.

I ______________________

:

:
I

Co,SO-S2 I
OSA,OSB :

:
I

I

!
16

I
I
I
I
~

B1S-Bo

I

I

~---T----Jj~--~:~--~
MOST
SIGNIFICANT
SLICE

LEAST
SIGNIFICANT
SLICE

I
I
I
I

F1S-Fo
:
L ____________________________ I
I

LEAST
SIGNIFICANT
SLICE

======================Arithmetic Logic Units
3-13

06J19/9S-LOS.381·L

--.-.--.-.
--""'-""'"----.--------------

-...--.-.

L4C381

DEVICES INCDRPORATED

16-bit Cascadable ALU

68-pin

68-pin
2
It)

~

C')

C\J

....

~~

A.
AID
Al1
A12
A13
A14
A1S
ClK
Vee
GND
C16

P
G
ZERO
OVF
ENF
FTF

.0
11
12
13
14
15
16
17
18
I.
20
21

•8

7 6 5 4

3

2 i~j 68 67 66 65 64 63 62

610

59
56

57
56
55
54

Top
View

53
52

51
50

49

22

48

23
24

47

25

45

26

48
44

V~~~~~~M~~~~~~M~48

A
B7
Bs
Bs
B4
B3
B2
Bl
Bo
ENA
ENB
FTAB
OSB
OSA
S2
SI
So
Co

ns
ns
ns
ns
ns

65
45
30
25
20

ns
ns
ns
ns
ns

65 ns
45ns
30 ns
25 ns
20 ns

L4C381 JC55
L4C381 JC40
L4C381 JC26
L4C381 JC20
L4C381JC15

4

5

6

7

8

" '-'
" '-' '-' '-'
" '-' '-'
"
'-'
A7
As
A.
A.
A5
B'5 B••
,_I
'-' As '-'
AI.
As '-'
A4 '-'
A2 '-'
A. '-'
B14 '-'
B12
"'-' '-'
"
A12 All
" '-'
"
'-'
A14
Ala
" '-'
"
Top View
'-'
CLK
A15
Through Package
"
'-' Vee
'-'
GND
(i.e., Component Side Pinout)
" '-'
'-'
j5
C.s
" '-'
'-'
ZERO G
'-' OVF
'-'
ENF
"'-' ,_I
" " '-'
"
"
" " '-'
FTF BE '-'
F14 F12 '-'
Fl. FB '-'
FB '-'
F4
" '-' '-' '-' '-'
'-'
'-'
'-'
F.5 Fl. Fl1
Fs
F7
F5
Fa
~

,~

B
C
D
E
F

,~

,~

,~

,~

,~

,~

,~

,~

,~

,~

,~

G

,~

H

,~

,~

,~

K

,~

~il~i~~ll£l~l~~~f

55
40
26
20
15

3

9

10

11

0

«<~««~oommoooooo~~
.1""\..-..-.--------.-

,~

,~

,~

,~

L4C381 KC55
L4C381 KC40
L4C381 KC26
L4C381 KC20
L4C381 KC15

L4C381 GC55
L4C381 GC40
L4C381 GC26
L4C381 GC20
L4C381GC15

L4C381KM65
L4C381KM45
L4C381KM30
L4C381KM25
L4C381KM20

L4C381GM65
L4C381GM45
L4C381GM30
L4C381GM25
L4C381GM20

L4C381 KMB65
L4C381 KMB45
L4C381 KMB30
L4C381KMB25
L4C381 KMB20

L4C381GMB65
L4C381GMB45
L4C381GMB30
L4C381GMB25
L4C381GMB20

,~

" "
'-'
Bs
Bl1 '-'

,_I
"
'-'
B7
Bl. BB '-'
" '-'
"
'-'
B5
Bs
" '-'
"
'-'
Ba
B4
" '-'
"
'-'
Bl
B2
"'-' '-'
"
ENA eo
'-' ENB
'-'
FTAB
'-' OSB
'-'
OSA
"
'-'
'-'
SI
52
,_I
"'-' " '-'
C.
SO
F2
'-'
'-'
F.
Fl
,~

,~

,~

,~

,~

,~

,~

,~

,~

,~

Arithmetic Logic Units
3-14

OSI19/95-LDS.381-L

-_

--- .---.
..-__--......--.- =-==:......

LSH32

~

=-:....=
-~---

~

32-bit Cascadable Barrel Shifter

o 32-bit Input, 32-bit Output Multio

o
o
o
o
o
o
o

plexed to 16 Lines
Full 0-31 Position Barrel Shift
Capability
Integral Priority Encoder for 32-bit
Floating Point Normalization
Sign-Magnitude or Two's Complement Mantissa Representation
32-bit Linear Shifts with Sign or
Zero Fill
Independent Priority Encoder
Outputs for Block Floating Point
DESC SMD No. 5962-89717
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 68-pin Plastic LCe, J-Lead
• 68-pin Ceramic LCC
• 68-pin Ceramic PGA

The LsH32 is a 32-bit high speed
shifter designed for use in floating
point normalization, word pack/
unpack, field extraction, and similar
applications. It has 32 data inputs,
and 16 output lines. Any shift configuration of the 32 inputs, including
circular (barrel) shifting, left shifts
with zero fill, and right shift with sign
extend are possible. In addition, a
built-in priority encoder is provided to
aid floating point normalization.
SHIFT ARRAY
The 32 inputs to the LSH32 are
applied to a 32-bit shift array. The 32
outputs of this array are multiplexed
down to 16 lines for presentation at
the device outputs. The array may be

32

32

RIGHT/LEFT

----+---.1

------11------+----1..1

32-bit
BARREL
SHIFT
ARRAY

FILL/WRAP ----t-----t-~o-L-,-----.,_J

16
NORM

16

----t---

In fill mode, as in wrap mode, the shift
code input represents the number of
shift positions directly for left shifts,
but the two's complement of the shift
code results in the equivalent right
shift. However, for fill mode the R/L
input can be viewed as the most

5

S04-S00

Essentially the LSH32 is configured as
a left shift device. That is, a shift code
of 000002 results in no shift of the
input field. A code of 000012 provides
an effective left shift of 1 position, etc.
When viewed as a right shift, the shift
code corresponds to the two's complement of the shift distance, i.e., a shift
code of 111112 (-lto) results in a right
shift of one position, etc.
When not in the wrap mode, the
LSH32 fills bit positions for which
there is no corresponding input bit.
The fill value and the positions filled
depend on the RIGHT/LEFT (R/L)
direction pin. This pin is a don't care
input when in wrap mode. For left
shifts in fill mode, lower bits are filled
with zero as shown in Table 2. For
right shifts, however, the SIGN input
is used as the fill value. Table 3
depicts the bits to be filled as a
function of shift code for the right shift
case. Note that the R/L input changes
only the fill convention, and does not
affect the definition of the shift code.

SIGN 131-10

S14-810

configured such that any contiguous
16-bit field (including wraparound of
the 32 inputs) may be presented to the
output pins under control of the shift
code field (wrap mode). Alternatively, the wrap feature may be
disabled, resulting in zero or sign bit
•
fill, as appropriate (fill mode). The
shift code control assignments and the
resulting input to output mapping for
the wrap mode are shown in Table 1.

OE

Y15-YO

MS/LS

==================== Special Arithmetic Functions
3-15

06/30/95-LDS.32-M

LO~I~

LSH32

DEVICES INCORPORATED

Shift Code

00000
00001
00010
00011

32-bit Cascadable Barrel Shifter

Y31

Y30

Y29

Y16

131
130

130

129

116

115

12

11

10

129

128

115

114

11

10

131

Y15

Y2

Y1

Yo

significant bit of a 6-bit two's complement shift code, comprised of R/L
concatenated with the SI4-SIO lines.
Thus a positive shift code (R/L = 0)
results in a left shift of 0-31 positions,
and a negative code (R/L = 1) a right
shift of up to 32 positions. The LSH32
can thus effectively select any contiguous 32-bit field out of a (sign extended
and zero filled) 96-bit "input."

129

128

127

114

113

10

131

130

128

127

. 126

113

112

131

130

129

01111
10000
10001
10010

116

115

114

11

10

119

118

117

115

114

113

10

131

118

117

116

114

113

112

131

130

117

116

115

113

112

111

130

129

116

115

114

The shift array outputs are applied to
a 2:1 multiplexer controlled by the
MS/LS select line. This multiplexer
makes available at the output pins
either the most significant or least
significant 16 outputs of the shift
array.

11100
11101
11110
11111

13

12

11

120

119

16

15

14

PRIORITY ENCODER

12

11

10

119

118

15

14

13

11

10

131

118

117

14

13

12

10

131

130

117

116

13

12

11

Shift Code

Y31

Y30

Y29

Y16

Y15

Y2

Y1

Yo

00000
00001
00010
00011

131

130

129

116

115

12

11

10

130

129

128

115

114

11

10

129

128

127

114

113

10

128

127

126

113

112

0

0
0

0
0
0

01111
10000
10001
10010

116

115

114

11

10

115

114

113

10

114

113

112

113

112

111

0
0

0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

11100
11101
11110
11111

13

12

11

12

11

10

11

10

10

0

0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

OUTPUT MULTIPLEXER

The 32-bit input bus drives a priority
encoder which is used to determine
the first significant position for
purposes of normalization. The
priority encoder produces a five-bit
code representing the location of the
first non-zero bit in the input word.
Code assignment is such that the
priority encoder output represents the
number of shift positions required to
left align the first non-zero bit of the
input word. Prior to the priority
encoder, the input bits are individually exclusive OR' ed with the SIGN
input. This allows normalization in
floating point systems using two's
complement mantissa representation.
A negative value in two's complement
representation will cause the exclusive
OR gates to invert the input data to
the encoder. As a result the leading
significant digit will always be "1."
This affects only the encoder inputs;
the shift array always operates on the
raw input data. The priority encoder
function table is shown in Table 4.

Special Arithmetic Functions
3-16
--------

-~-

06/30/95-LDS.32·M

L(j~j~

LSH32

-~---

DEVICES INCORPORATED

32-bit Cascadable Barrel Shifter
NORMALIZE MULTIPLXER

Shift Code

V31

V30

V29

V16

V15

V2

V1

Vo

00000
00001
00010
00011

S
S
S
S

S
S
S
S

S
S
S
S

S
S
S
S

S
S
S
S

S
S
S

S
S

131

131

130

131

130

129

01111
10000
10001
10010

S
S
S
S

S
S
S
S

S
S
S
S

S
S

S

119

118

117

131

118

117

116

11100
11101
11110
11111

S
S
S
S

S
S
S
131

S

131

130

117

116

115

130

129

116

115

114

S
S

120

119

16

15

14

119

118

15

14

13

131

118

117

14

13

12

130

117

116

13

12

11

The NORM input, when asserted
results in the priority encoder output
driving the internal shift code inputs
directly. It is exactly equivalent to
routing the 504-500 outputs back to
the SI4-SIo inputs. The NORM input
provides faster normalization of 32-bit
data by avoiding the delay associated
with routing the shift code off chip.
When using the NORM function, the
LSH32 should be placed in fill mode,
with the R/[ input low.
APPLICATIONS EXAMPLES
Normalization of mantissas up to 32
bits can be accomplished directly by a
single LSH32. The NORM input is
asserted, and fill mode and left shift
are selected. The normalized mantissa
is then available at the device output
in two 16-bit segments, under the
control of the output data multiplexer
select, the MS/LS.
If it is desirable to avoid the necessity

131

130

129

116

115

12

11

10

Shift Code

1
0
0

X

X
X

X
X
X

X
X
X

X
X
X

X
X
X

X
X
X

00000
00001
00010

0
0
0

0
0
0

0
0
0

X

0
0

0

X
X
X

X
X
X

X
X
X

01111
10000
10001

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

0
0
0

1
0
0

X

11110
11111
11111

0

1
0

of multiplexing output data in 16-bit
segments, two LSH32 devices can be
used in parallel. Both devices receive
the same input word, with the MS/LS
select line of one wired high, and the
other low. Each device will then
independently determine the shift
distance required for normalization,
and the full 32 bits of output data will
be available simultaneously.

=================== Special Arithmetic Functions
3·17

06/30/95-LDS.32·M

II

- ==~E==
- --E
----...... .....
- -_.......
-

LSH32

DEVICES INCORPORATED

32-bit Cascadable Barrel Shifter

LONG-WORD NORMALIZATION
(MULTIPLE CYCLES)

Normalization of floating point
mantissas longer than 32 bits can be
accomplished by cascading L5H32
units. When cascading for normalization, the device inputs are overlapped
such that each device lower in priority
than the first shares 16 inputs with its
more significant neighbor. Fill mode
and left shift are selected, however,
internal normalization (NORM) is not
used. The most significant result half
of each device is enabled to the
output. The shift out (504-500) lines
of the most significant slice are
connected to the shift in lines of all

slices, including the first. The exception is that all 514 lines are grounded,
limiting the shift distance to 16
positions. The shift distance required
for normalization is produced by the
priority encoder in the most significant slice. The priority encoder will
produce the shift code necessary to
normalize the input word if the
leading non-zero digit is found in the
upper 16 bits. If this is the case, the
number of shift positions necessary to
accomplish normalization is placed on
the S04-S00 outputs for use by all
slices, and the appropriate 0-15 bit
shift is accomplished. If the upper 16
bits are all zero, then the maximum
shift of 15 places is executed. 5ingle

163·148

147-132

131-116

clock normalization requiring shifts
longer than 16 bits can be accomplished by a bank-select technique
described below.
SINGLE CYCLE LONG-WORD
NORMALIZATION

An extension of the above concept is a
single clock normalization of long
words (potentially requiring shifts of
more than 15 places). The arrangement of L5H32s required is shown in
Figure 1. Cascading of L5H32 units is
accomplished by connecting the 513510 input lines of each unit to the 503SOo outputs of the most significant
device in the row as before. Essen-

115-10

o

MSBs

Y63-Y48

Y47-Y32

Y31-Y16

Y15-YO

=================== Special Arithmetic Functions
3-18

06/30/95-LDS.32-M

- - ---------'"-"'---......-----_
.......
~

-~-..--.

LSH32

-

DEVICES INCORPORATED

tially the LSH32s are arranged in
multiple rows or banks such that the
inputs to successive rows are leftshifted by 16 positions. The outputs
of each row are multiplexed onto a
three-state bus. The normalization
problem then reduces to selecting
from among the several banks that
one which has the first non-zero bit
of the input value among its 16 most
significant positions. If the most
significant one in the input me was
within the upper 16 locations of a
given bank, the S04 output of the
most significant slice in that bank will
be low. Single clock normalization
can thus be accomplished simply by
enabling onto the three-state output
bus the highest priority bank in which
this condition is met. In this way the
input word will be normalized
regardless of the number of shift
positions required to accomplish this.

32-bit Cascadable Barrel Shifter
The number of shift positions can be
determined simply by concatenation
of the S03-S00 outputs of the most
significant slice in the selected row
with the encoded Output Enable-bits
determining the row number. Note
that lower rows need not be fully
populated. This is because they
represent left shifts in multiples of 16
positions, and the lower bits of the
output word will be zero filled. In
order to accomplish this zero fill, the
least significant device in each row is
always enabled, and the row select is
instead connected to the SI4 input.
This will force the shift length of the
least significant device to a value
greater than 15 whenever the row
containing that device is not selected.
This results in zero fill being accomplished by the equivalently positioned
slice in a higher bank, as shown in the
diagram.

BLOCK FLOATING POINT

With a small amount of external logic,
block floating point operations are
easily accomplished by the LSH32.
Data resulting from a vector operation
are applied to the LSH32 with the
NORM-input deasserted. The S04SOo outputs fill then represent the
normalization shift distance for each
vector element in turn. By use of an
external latch and comparator, the
maximum shift distance encountered
across all elements in the vector is
saved for use in the next block operation (or block normalization). During
this subsequent pass through the data,
the shift code saved from the previous
pass is applied uniformly across all
elements ofthe vector. Since the
LSH32 is not used in the internal
normalize mode, this operation can be
pipelined, thereby obtaining the
desired shift distance for the next pass
while simultaneously applying the
normalization required from the
previous pass.

=================== Special Arithmetic Functions
3-19

06/30/95-LDS.32·M

3

.--=- =-==iiiii==
-------.....-.=
--~--

LSH32

-~---

DEVICES INCORPORATED

32-bit Cascadable Barrel Shifter

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs ....... ,...................................................................................................... 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

Parameter

Test Condition

VOH

Output High Voltage

Vee = Min., IOH = -2.0 mA

VOL

Output Low Voltage

Vee = Min., IOL = 8.0 mA

ViH

Input High Voltage

ViL

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground

~

VIN

loz

Output Leakage Current

Ground

~

VOUT ~ Vee (Note 12)

leel

Vee Current, Dynamic

(Notes 5, 6)

lee2

Vee Current, Quiescent

(Note 7)

~

Supply Voltage
4.75 V ~ Vee
4.50 V

~

~

5.25 V

Vee ~ 5.50 V

Min

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

±20

~

±20

~

30

mA

1.5

mA

Vee (Note 12)

10

=================== Special Arithmetic Functions
3-20

06/30/95-LDS.32-M

-= -- -------_..

.-=a ... =~-

LSH32

-

----~--~---

DEVICES INCORPORATED

32-bit Cascadable Barrel Shifter

131-10

SIGN
S14-S10

RIGHT/LEFT

'"

MS/[S
I---tIY, llYN -

)I{

S04-S00

I-tMS~

I---- tISO-==:J

)!(

Y31-YO

tSIY

OE
Y31-Yo

-------C

~tENA----t

tOIS--:

----J

HIGH IMPEDANCE

I~

--- 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial
Active Operation, Military

Symbol

Supply Voltage

O°C to +70°C

4.75 V:;:; Vee:;:; 5.25 V

-55°C to +125°C

4.50 V :;:; Vee:;:; 5.50 V

Min

Parameter

Test Condition

VoH

Output High Voltage

Vee

=Min., IOH =-2.0 mA

VoL

Output Low Voltage

Vee

=Min., IOL =8.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Typ

Max

2.4

Unit
V

0.4

V

2.0

Vee

V

0.0

0.8

V

Ground:;:; VIN:;:; Vee (Note 12)

±20

jJA

Output Leakage Current

Ground:;:; VOUT:;:; Vee (Note 12)

±20

jJA

leel

Vee Current, Dynamic

(Notes 5, 6)

30

mA

lee2

Vee Current, Quiescent

(Note 7)

1.5

mA

10

=================== Special Arithmetic Functions
3-28

06/30/95-LDS.33-L

LSH33
DEVICES INCORPORATED

32-bit Barrel Shifter with Registers

Y15-YO

S04-S00

Y15-YO

S04-S00

Y15-YO

S04-S00

28
28

28

24
24

24

15
15

15

73/40
52
52
28

55/-

58/30
40
40
24

42/-

20/20
20
20
15

20/-

28
28

28

24
24

24

15
15

15

73/40
52
52
28

55/-

58/30

42/-

20/20
20
20
15

20/-

FTI = 0, FTO = 0
elK
M8/l8

•

FTI = 0, FTO= 1
elK (NORM = 0/1)
814-810
R/C, FIW
M8/l8

FTI = 1, FTO = 0
elK
M8/l8
FTI = 1, FTO = 1
131-10,8IGN
(NORM = 0/1)
814-810
RIC, FiW
M8/l8

40
40

24

LSH33-40

Input

LSH33-30

LSH33-20

FTI=O

FTI = 1

FTI=O

FTI=1

FTI=O

FTI = 1

Setup Hold

Setup Hold

Setup Hold

Setup Hold

Setup Hold

Setup Hold

131-10, SIGN

12

3

20

2

10

3

15

2

8

0

8

2

814-810

17

0

17

0

15

0

15

0

8

0

8

0

RIC, FiW

12

0

12

0

10

0

10

0

8

0

8

0

ENI, ENO

12

0

12

0

10

0

10

0

8

0

8

0

LSH33-40

LSH33-30

LSH33-20

tENA

20

17

15

tDIS

20

17

15

LSH33-40

LSH33-30

LSH33-20

Minimum Cycle Time

30

20

15

Highgoing Pulse

12

9

7

Lowgoing Pulse

12

9

7

Special Arithmetic Functions
3·29

06/30/95-LDS.33·L

--------""-"'"----.. _----...--.
.....
~...--.

-

-~--~-

LSH33

DEVICES INCORPORATED

32-bit Barrel Shifter with Registers

.-...~~-

Y1S-YO

S04-S00

Y15-YO

S04-S00

Y15-YO

S04-S00

32
32

32

28
28

28

24
24

24

80/50
62
62
32

65/-

73/40
52
52
28

55/-

58/30
40
40
24

42/-

32
32

32

28
28

28

24
24

24

80/50
62
62
62

65/-

73/40
52
52
28

55/-

58/30
40
40
24

42/-

FTI = 0, FTO = 0
elK
MS/lS
FTI = 0, FTO= 1
elK (NORM = 0/1)
SI4-Slo

R/L, FiW
MS/lS
FTI = 1, FTO = 0
elK
MS/lS
FTI = 1, FTO = 1
131-10, SIGN
(NORM =0/1)
SI4-Slo

R/L, FiW
MS/lS

lSH33-50

Input

lSH33-40

LSH33-30

FTI=O

FTI=1

FTI=O

FTI =1

FTI=O

FTI= 1

Setup Hold

Setup Hold

Setup Hold

Setup Hold

Setup Hold

Setup Hold

131-10, SIGN

15

3

20

2

12

3

20

2

10

0

15

2

SI4-Slo

20

0

20

0

17

0

17

0

15

0

15

0

R/L, FIW

15

0

15

0

12

0

12

0

10

0

10

0

ENI, ENO

15

0

15

0

12

0

12

0

10

0

10

0

LSH33-50

LSH33-40

LSH33-30

tENA

22

20

17

tDIS

22

20

17

lSH33-50

lSH33-40

lSH33-30

Minimum Cycle Time

35

30

20

Highgoing Pulse

15

12

9

Lowgoing Pulse

15

12

9

Special Arithmetic Functions
3-30

06/30/95-LDS.33-L

--

.---

=~;:"'!!!=~
=-=-=:.==
=-..r
-~---

LSH33

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

32-bit Barrel Shifter with Registers

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/torS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and torSABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at •
the high temperature extreme, which is
the worst case for leakage current.

VCC

d.
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

~n

a. A 0.1 J.l.F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
ground and tester common.
anteed as specified.

5. Supply current for a given applica- b. Ground and Vee supply planes
tioncanbeaccuratelyapproximatedby: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.
where
N
C
V
F

4

total number of device outputs
= capacitive load per output
= supply voltage
= clock frequency
=

t--....,..-o OUTPUT

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the extervee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case re8. These parameters are guaranteed
quirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

n+
01

p-

-==~~f!!J!!!l~~~==

TRISTATE
OUTPUTS _

=================== Special Arithmetic Functions
3-31

06/30/95-LDS.33-L

--

- --....--.
..-..- -....-.....-.
~--------...-.
-""-"""---~--

LSH33

---~

DEVICES INCORPORATED

32-bit Barrel Shifter with Registers

68-pin

68-pin

2
Q

m

~

~

~

v

~

~

~

0

~

m

~

~

~

v

z

~~~~~~~~~~======G

Iso

10

131

11

SIGN
SI/04

987654321116867666564636261

L,

60

A

B

59

GND
113

12

58

112

C

13

57

111

56

110

SI/02

15

55

19

SIIOI
SllOo
NORM

16

54

18

E

17
18
19
20
21
22
23
24
25
26

53
52

17
16

F

ClK
ENI

FTI
END

FTO

R/L
Ffii
Y31115

5

6

7

9

,~

" '-'
"
'-'
'-' SilO.
'-'
SilO.
"'-' '-'
SllOo SIIOI
,... , ....

51

15

50

14

49

13

48

12

47

11

46
45

10

44

vu~so~~~~~~~~M~~~~

,~

LSH33JC40
LSH33JC30
LSH33JC20

11

,~

,_I ,_I

D

,~

,~

G
H

Vee
Vee

K

'_I~
elK NORM

"
'-'
FTI
"
'-'
FTO
"
'-'
FtW

"
'-'
EM
'-'
END

"

,_I

,_I

Top View
Through Package
(i.e., Component Side Pinout)

,~

,...
,_I
110
,...
,_I
la
,...
,_I
16
,...
,_,
14
,....
,_,

112

, ....
,_I
,111...
,_I
,19...
,_I
,17...
,_I
,15....
,_I

113

12

13

10

11

,... ,_I
, ...
,_I

"
'-'
RiL

" ," 1 ," 1 ," I ," I ," , ," 1 ,_I
" ,_I
" ,_I
"
Vee Vee
,_I
,_I
,_I
,_I
,_I
,_I
,_I
,_,
,
1
" " " " " " " " "

Y31115 Y3OI14 Y28112 Y26f10 Y24/8 Y2216 Y2OJ4 Y1812 Y1610

Y29N3 Y27111 Y25/9 Y2317 Y2115 Y1913 Y1711

40 ns
30 ns
20 ns

10

... '-'
" '-'
" '-'
" '-'
" '-' '-'
" '-'
" '-'
" '-'
"
12.
128
120
118
116
114
124
122
126
" '-'
" '-'
" '-'
" '-'
" '-'
" '-' '-' '-' (';'1 '-'
'-'
1.,
1.0
127
12S
12.
121
II.
117
lIS GND GND
,... , ...

SilO. SIGN

14

Top
View

4

,~

,~

SI/03

3

C

LSH33KC40
LSH33KC30
LSH33KC20

LSH33GC40
LSH33GC30
LSH33GC20

50 ns
40 ns
30 ns

LSH33KM50
LSH33KM40
LSH33KM30

LSH33GM50
LSH33GM40
LSH33GM30

50 ns
40 ns
30 ns

LSH33KMB50
LSH33KMB40
LSH33KMB30

LSH33GMB50
LSH33GMB40
LSH33GMB30

5E MSiLS

=================== Special Arithmetic Functions
3-32

06/30/95-LDS.33-l

-

- ...-----.- -:......
.-=-=-=:.:=
-~--....-.~-~

L10C23

DEVICES INCORPORATED

64-bit Digital Correlator

o High Speed (50 MHz), Low Power

o
o
o
o
o

o

(125 m W), CMOS 64-bit Digital
Correlator
Replaces TRW /Raytheon
TDC1023/TMC2023
Bit Can be Selectively Masked
Three-State Outputs
DESC SMD No. 5962-89711
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 24-pin Plastic DIP
• 24-pin Ceramic DIP
• 28-pin Ceramic LCC

The LlOC23 is a high speed CMOS
64-bit digital correlator. It is pinfor-pin equivalent to the TRW /
Raytheon TDC1023/TMC2023. The
LlOC23 operates over the full
military ambient temperature range
using advanced CMOS technology.
The LlOC23 produces the 7-bit correlation score of two input words of up
to 64 bits, denoted A and B. The A
and B inputs are serially shifted into
two independently clocked 64-bit
registers. The A register is clocked on

AIN _ , - - . - - , - - - - , , - - ,

ClKA

".
x }+---------"
r--------r--r---.--r---.~

MOUT
MIN

ClKM

ClKC
ClKS

INV

ClKS

6E----o../

Rs.o

The outputs of the B register drive a
64-bit transparent latch, denoted the
C latch. The C latch is controlled by
the LCL (Load C Latch) input. A
HIGH level on the LCL input causes
the C latch to be transparent, allowing
the contents of the B register to be
applied directly to the correlator
array. When the LCL input is LOW,
the data in the C latch is held, so that
the B input may be loaded with a new
correlation reference without affecting
the current reference value stored in C.
Each bit in the A register is exclusive
NOR'ed with the corresponding bit in
the C latch, implementing a single bit
multiplication at each bit position.

AOUT ......- - - - - - - - - ,

ClKS

the rising edge of CLK A, and the B
register is clocked on the rising edge
ofCLK B.

The mask register, denoted by M, is a
third 64-bit register, which is serially
loaded from the M input on the rising
edge of CLK M. Bit positions in the
M register which are set to zero mask
the corresponding bits in the A and C
registers from participating in the
correlation score. This can be used to
reduce the effective length of the
correlation, or to correlate against only
one channel of a bit-multiplexed
datastream without deinterleaving
the data.
The output of the masking process is a
64-bit vector which contains ones in
the locations in which A and B data
match, and which are unmasked
(M register contains a '1'). This 64-bit
vector is applied to a pipelined digital
summer which calculates the total
number of ones in the vector (the
correlation score). The summer
network contains three pipeline
stages, which are clocked on the rising
edge of CLK S. Calculation of a

CFl

==================== Special Arithmetic Functions
3-33

06/23/95-lDS.23·G

II

--

- ..- _--..-_---- -........------- -

L10C23

DEVICES INCORPORATED

correlation score therefore requires
three clock cycles, but a new result can
be obtained on each cycle once the
pipeline is filled.
Because a portion of the summer logic
is located between the input registers
and the first pipeline register, some
timing restrictions exist between
CLK Sand CLK A, CLK B, or CLK M.
CLK S may be tied to an input clock
(usually CLK A) to obtain a continuously updated correlation score,
delayed by three cycles from the data.
Under this condition, CLK S may be
skewed later than CLK A by no more
than tSK to assure that the A register
outputs have not changed before the
S clock occurs.
Alternatively, CLK S may be asyncronous to the input clocks, as long as
data is stable at the pipeline register
inputs prior to the CLK S rising edge.
This condition can be met by assuring
that CLK S occurs at least tps after the
input clock.
The summer output represents a
count of the number of matching
positions in the input data streams.
This 7-bit result can be inverted (one's
complemented) by loading a T into
the INV register.

64-bit Digital Correlator
Correlation values which exceed a
predetermined threshold can be
detected via the Threshold register
and Comparator. The Threshold
register is loaded with a 7-bit value
via the R6-0 pins at the rising edge of
CLK C and while OE is HIGH. To
achieve synchronization with the
digital summer, the Threshold register
contents are fed into pipeline registers
clocked by CLK S. The compare flag
output (CFL) goes HIGH when the
summer output is equal to or greater
than the contents of the Threshold
register.
Cascading the LlOC23 devices for
longer correlation lengths and more
bits of reference or data precision is
easily accomplished. The A, B, and M
registers have serial outputs to
directly drive the corresponding
inputs of succeeding devices. The
correlation scores of multiple devices
in such a system should be added
together to obtain the overall correlation score.
Correlation on data exceeding one bit
of precision can be accomplished by
first calculating single-bit correlation
scores at each bit position, then
adding the results after weighting
them appropriately. Thus, one
LlOC23 would be used for each bit of
precision in the data.

Logic Devices' L4C38116-bit ALU can
be used to assist in adding the outputs
of several LlOC23 correlators. When
adding several 7-bit correlation scores,
advantage can be taken of the fact that
the sum of two 7-bit numbers will not
exceed 8 bits. Thus the L4C381 can
simultaneously perform two 7-bit
additions. The first two operands are
applied to A6-0 and B6-0, with the
result appearing on F7-0. The second
pair of operands are applied to A14-S
and B14-S, with the result appearing in
FIS-S. The unused inputs are tied to
ground. If it can be guaranteed that at
least one of the input scores will not
reach its maximum value of 64, then
this technique can also be applied in
the second tier of adders. In this case,
while the inputs have 8 bits of precision, the maximum value that their
sum can assume is 255, which is
expressable in 8 bits.
Alternatively, when performing long
correlations on relatively slow datastreams, one L4C381 can be configured using its feedback mode to
accumulate the correlation scores of a
number of LlOC23s. To accomplish
this, the outputs of all the correlators
are tied together on a three-state bus.
Each one is sequentially enabled and
clocked into the L4C381, which
accumulates the total resulting score.

====================Special Arithmetic Functions
3-34

06/2S/95-LDS.2S·G

- -..- ---------.-------.-.-- -

-

L10C23

DEVICES INCORPORATED

64-bit Digital Correlator

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

II
Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to + 125°C

Parameter

Test Condition

VOH

Output High Voltage

Vee

= Min., IOH =-2.0 mA

VOL

Output Low Voltage

Vee

= Min., IOL =4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Supply Voltage
4.75 V ::; Vee::; 5.25 V
4.50 V ::; Vee::; 5.50 V

Min

Typ

Max

3.5

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground::; VIN::; Vee (Note 12)

±20

J.IA

Output Leakage Current

Ground::; VOUT::; Vee (Note 12)

±20

J.IA

lee1

Vee Current, Dynamic

(Notes 5,6)

100

mA

lee2

Vee Current, Quiescent

(Note 7)

0.5

mA

25

==================== Special Arithmetic Functions
3·35

OS/23/95-LDS.23-G

--....----_------ -.....
------........

~-~

.--...-.
-~~-

........-

L10C23

DEVICES INCORPORATED

64-bit Digital Correlator

tps
tpw

A,8,M
DATA

ts

tH

*-

*: - - tpw

A,8,M

.1

A,8,M

tpw

~

ClK

tOABM

*-

OUT

I - tsLCL-==:j
lCl

"k:
tps
tSK

tpw

tpw

-{

r

ClKS

tcs-r-l-~

ClKC

-tpw-

tOR

Re-o
toc

CFl

tOIS

1

-1

OUT

J

ts

J

tH
IN

1

i----!

tENA
OUT

=i

=================== Special Arithmetic Functions
3-36

06/23/95-LOS.23-G

- -- --------------------

-

L10C23

-~--DEVICES INCORPORATED

64-bit Digital Correlator

SWI'T~HfNG.CHARAC'TI:RISTI~S

1\II1t.IT~~'t()~E~A'I'IN~f:l~NGE(~55QC~C)+1~5.0Q).rsJQtI3S9)10~. . •. . .. · ·•·•• ·.r .•.•. •.•.• . .•. ·r· •. ..
L10C2335

60

Min

Max

Max

20
Min

Symbol

Parameter

Min

tPABM

A, B, M Clock Period

58

33

20

tpw

A, B, M, S, C Clock Pulse Width

20

14

8

ts

Input Setup Time

22

12

12

tH

Input Hold Time

0

0

0

tBLCL

B Clock to LCL Hold

20

14

8

tcs

C Clock to S Clock

58

33

20

tDABM

A, B, M Clock to A, B, M Out

tps

S Clock Period, A, B, M Clock to S Clock Delay

23

30
33

58

Max

20
20

tSK

A, B, M Clock to S Clock Skew (Note 8)

3

3

3

tOR

S Clock to R6-0

40

35

27

tDC

S Clock to CFL

30

23

18

tENA

Output Enable Time (Note 11)

35

20

18

tolS

Output Disable Time (Note 11)

40

18

16

tps
tpw

A,B,M
DATA

tS)k

)ktH
~tpw

CLK
A, B,M

tpw

{

7

:;ktOABM

A, B,M
OUT
_

tBLCL--==:j

LCL

~
tps
tpw

tSK

tpw

{.

CLKS

tcs---

CLKC
_tpw_

tOR

~

Rs-o
toc

CFL

tOIS

·1

OUT

I

ts

t
I'

J
IN

'I

tH

---r-

tENA
OUT

~

==================== Special Arithmetic Functions
3-37

OS/23/95-LOS.23-G

•

- --- --------- ---~---

-

L10C23

DEVICES INCORPORATED

64-bit Digital Correlator

1. Maximum Ratings indicate stress 9. AC specifications are tested with
specifications only. Functional oper- input transition times less than 3 ns,
ation of these products at values be- output reference levels of 1.5 V (except
yond those indicated in the Operating tENA/tDIS test), and input levels of
Conditions table is not implied. Expo- nominally 0 to 3.0 V. Output loading
sure to maximum rating conditions for may be a resistive divider which
extended periods may affect reliability. provides for specified IOH and IOL at an
output voltage of VOH min and VOL
2. The products described by this specmax respectively. Alternatively, a
ification include internal circuitry de- diode bridge with upper and lower
signed to protect the chip from damag- current sources of IOH and IOL
ing substrate injection currents and ac- respectively, and a balancing voltage of
cumulations of static charge. Never- 1.5 V may be used.
Parasitic
theless, conventional precautions capacitance is 30 pF minimum, and
should be observed during storage, may be distributed. For tENABLE and
handling, and use of these circuits in tDISABLE measurements, the load
order to avoid exposure to excessive current is increased to 10 mA to reduce
electrical stress values.
the RC delay component of the
3. This device provides hard clamping measurement.
of transient undershoot and overshoot. This device has high speed outputs caInput levels below ground or above Vee pable of large instantaneous current
will be clamped beginning at -0.6 V and pulses and fast turn-on I turn-off times.
Vee + 0.6 V. The device can withstand As a result, care must be exercised in
indefinite operation with inputs in the the testing of this device. The following
range of -D.5 V to +7.0 V. Device opera- measures are recommended:
tion will not be adversely affected, however, input current levels will be well in a. A O.l11F ceramic capacitor should be
excess of 100 mA.
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary from
(DDT) as possible. Similar capacitors
those designated but operation is guar- should be installed between device Vee
anteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated
b. Ground and Vee supply planes
by:
must be brought directly to the DUT

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

socket or contactor fingers.
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

==================== Special Arithmetic Functions
3·38

06/23/95-LDS.23·G

=

....-..

.......

_-

="11~=~
=-=...==.==L..ir

L10C23

-~---

DEVICES INCORPORATED

64-bit Digital Correlator

24-pin -

24-pin - 0.3" wide

ClKB
ClKM
ClKA
lCl
MOUT
AOUT
BOUT
CFl

Vee

MIN
AIN
BIN
ClKC
ClKS
INV

DE
Rs
R5
R.
R3

50 ns
30 ns
20 ns

0.6" wide

Vee

MIN
AIN
BIN
ClKC
ClKS
INV

DE
Rs
R5
R.
R3

GND

Ro
Rl
R2

L10C23PC50
L10C23PC30
L10C23PC20

L10C23NC50
L10C23NC30
L10C23NC20

ClKB
ClKM
ClKA
lCl
MOUT
AOUT
BOUT
CFl

•

GND

Ro
Rl
R2

L10C23CC50
L10C23CC30
L10C23CC20

60 ns
35 ns
20 ns

L10C23CM60
L10C23CM35
L10C23CM20

60 ns
35 ns
20 ns

L 1OC23CMB60
L 1OC23CMB35
L10C23CMB20

=================== Special Arithmetic Functions
3-39

06/23/95-LDS.23-G

- ,..~=~
- --=-=-====
......

=

L10C23

-~--DEVICES INCORPORATED

64-bit Digital Correlator

28-pin

m::iEc(
~~88~~~

c(::iE»uuu
NC

5

BIN

6

ClKC
ClKS

8

INV

9

OE
Rs

7

4

3

2 :1: 28 27 26
:_,
25

Top

lCl

24

MOlrr

23

AOUT

22

BOUT

21

CFl

10

20

11

19
12 13 14 15 16 17 18

GND
GND

View

50 ns
30 ns
20 ns

L10C23KC50
L10C23KC30
L10C23KC20

60 ns
35 ns
20 ns

L10C23KM60
L10C23KM35
L10C23KM20

60 ns
35 ns
20 ns

L 1OC23KMB60
L 1OC23KMB35
L 1OC23KMB20

=================== Special Arithmetic Functions
3-40

06/23/95-LDS.23-G

- .....- ---.....

- --........-----_------ ~-

DEVICES INCORPORATED

Multipliers & Multiplier-Accumulators

•

- ---

i-ufifC
-~--DEVICES INCORPORATED

Multipliers & Multiplier-Accumulators

MULTIPLIERS & MULTIPLIER-ACCUMULATORS ........................................................................................... 4-1
Multipliers
LMU08
8 x 8-bit Parallel Multiplier, Signed ................................................................................................................... 4-3
LMU8U
8 x 8-bit Parallel Multiplier, Unsigned .............................................................................................................. 4-3
12 x 12-bit Parallel Multiplier ........................................................................................................................... 4-11
LMU12
LMU112
12 x 12-bit Parallel Multiplier, Reduced Pinout ............................................................................................. 4-17
16 x 16-bit Parallel Multiplier ........................................................................................................................... 4-23
LMU16
16 x 16-bit Parallel Multiplier, Surface Mount ............................................................................................... 4-23
LMU216
16 x 16-bit Parallel Multiplier, 32 Outputs ..................................................................................................... 4-31
LMU18
LMU217
16 x 16-bit Parallel Multiplier, Microprogrammable, Surface Mount ........................................................ 4-39
Multiplier-Accumulators
LMA1009 12 x 12-bit Multiplier-Accumulator ................................................................................................................. 4-45
LMA2009 12 x 12-bit Multiplier-Accumulator, Surface Mount ..................................................................................... 4-45
LMA1010 16 x 16-bit Multiplier-Accumulator ................................................................................................................. 4-53
LMA2010 16 x 16-bit Multiplier-Accumulator, Surface Mount.. ................................................................................... 4-53
Multiplier-Summers
LMS12
12 x 12 + 26-bit Cascadable Multiplier-Summer, FIR ................................................................................... 4-61

4-1

•

DEVICES INCORPORATED

o
o
o
o

o
o
o
o
o

~~fagG

LMU08/8U

~

8 x 8-bit Parallel Multiplier

35 ns Worst-Case Multiply Time
Low Power CMOS Technology
LMU08 Replaces TRW TMC208K
LMU8U Replaces TRW TMC28KU
Two's Complement (LMU08), or
Unsigned Operands (LMU8U)
Three-State Outputs
DESC SMD No. 5962-88739
Available 100% Screened to
MIL-SID-883, Class B
Package Styles Available:
• 40-pin Plastic DIP
• 4O-pin Ceramic DIP
• 44-pin Plastic LCC, J-Lead
• 44-pin Ceramic LCC

The LMU08 and LMU8U are highspeed, low power 8-bit parallel
multipliers. They are pin-for-pin
equivalents with TRW TMC208K and
TMC28KU type multipliers. Full
military ambient temperature range
operation is attained by the use of
advanced CMOS technology.
Both the LMU08 and the LMU8U
produce the 16-bit product of two
8-bit numbers. The LMU08 accepts
operands in two's complement format,
and produces a two's complement
result. The product is provided in two
halves with the sign bit replicated as
the most significant bit of both halves.

A7·0

B7-0

CLKA--~~-------4~~~ITERl

CLKB--~~~~----~===+====~~

This facilitates use of the LMU08
product as a double precision operand in 8-bit systems. The LMU8U
operates on unsigned data, producing
an unsigned magnitude result.
Both the LMU08 and the LMU8U
feature independently controlled
registers for both inputs and the
product, which along with three-state
outputs allows easy interfacing with
•
microprocessor busses. Provision is
made in the LMU08 and LMU8U for
proper rounding of the product to
8-bit precision. The round input is
loaded at the rising edge of the logical
OR of CLK A and CLK B for the
LMU08. The LMU8U latches RND on
the rising edge of CLK A only. In
either case, a '1' is added in the most
significant position of the lower
product byte when RND is asserted.
Subsequent truncation of the least
significant product byte results in a
correctly rounded 8-bit result.

II:

w

RND - - - - - - - + 1 ~ 1 - - - - - - - + 1

Ci

w

II:

8

8

8

8
R7-0

R15-B

========================= Multipliers
4-3

OS/29/95-LDS.08/BU-K

~

--

--..- -- .. _-----------~---

~--.-.-.

-~--~

LMU08/8U

DEVICES INCORPORATED

8 x 8-bit Parallel Multiplier

AIN

BIN

- - - - - - L M U 0 8 Fractional Two's Complement - - - - - -

17651it2101

17651it2

~~~
(Sign)

~~~
(Sign)

~~~

01

~~~

LMU08 Integer Two's Complement

17

6 5
_27 26 2 5

~2

17

o1

6 5
_27 2 6 2 5

22 21 2°

(Sign)

~ 2

01

~2

01

22 21 2°

(Sign)

LMU8U Unsigned Fractional

171

6 5
2- 2-2 2-3

~2

2-6 Z-7

171

01

6 5
2- 2-2 2-3

z-a

2-6 2-7 2-8

- - - - - - - - LMU8U Unsigned Integer - - - - - - - -

MSP

LSP

- - - - - - LMU08 Fractional Two's Complement - - - - - -

115 14

13
_20 2-1 2-2

lit 10

9 8
2-6 2-6 2-7

1
_2° 2-8 2--9

(Sign)

(Sign)

- - - - - - - LMU081nteger Two's Complement - - - - - - -

115 14

13
_2 14 2 13 212

lit 10

9

8

1

(Sign)

- - - - - - - - LMU8U Unsigned Fractional - - - - - - - -

115 14

13

lit 10

9

8

1

- - - - - - - - LMU8U Unsigned Integer - - - - - - - -

=========================Multipliers
4-4

06/29/95-LDS.08/8U-K

-- -------- ------- - ---

-

LMU08/8U

-~---

DEVICES INCORPORATED

8 x 8-bit Parallel Multiplier

Storage temperature ............................................................................................................ -65°C to +150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C

Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Temperature Range (Ambient)

Mode
Active Operation, Commercial

O°C to +70°C

Active Operation, Military

-55°C to + 125°C

4.50 V :;:; Vee:;:; 5.50 V

Min

Parameter

Test Condition

VOH

Output High Voltage

Vee

=Min., 10H =-2.0 mA

VOL

Output Low Voltage

Vee

=Min., 10L =8.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Symbol

..

Supply Voltage
4.75 V:;:; Vee:;:; 5.25 V

Typ

Max

Unit
V

3.5
0.5

V

2.0

Vee

V

0.0

0.8

V

Ground:;:; VIN:;:; Vee (Note 12)

±20

~

Output Leakage Current

Ground:;:; VOUT $ Vee (Note 12)

±20

~

lee1

Vee Current, Dynamic

(Notes 5, 6)

24

mA

lee2

Vee Current, Quiescent

(Note 7)

1.0

mA

8

========================== Multipliers
4-5

06/29/95-LDS.08/8U-K

-• -.......
---------.....-......=~

LMU08/8U

---~

-~---

DEVICES INCORPORATED

8 x 8-bit Parallel Multiplier

.t=
INPUT

ts

- I - tH..:j

)K

)I(

I--ClKA
ClKB

Il'

tpw

tpw

X
tMC

ClKR
to

X

jl'

R15-0

I-- tDIS ------l
r

l=tENA
HIGH IMPEDANCE

J

========================= Multipliers
4·6

06/29/95-LDS.08/8U·K

-

- ---

L.D£ifC
-~---

LMU08/8U

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

8 x 8-bit Parallel Multiplier

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
Parasitic
1.5 V may be used.
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tOISABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

tENA

6~~~~ ____~~-,~~~~~~__
O.2V

a. A 0.1 IlF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is
should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.

:yo~ can be accurately approximated b. Ground and Vee supply planes

NCV2 F

4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case rebut not 100% tested.
quirements of all parts. Responses from
the internal circuitry are specified from

========================= Multipliers
4-7

OS/29/95-LDS.OB/BU-K

II

- ..- ~-------~--~-----------~---

--

LMU08/8U

DEVICES INCORPORATED

8 x 8-bit Parallel Multiplier

40-pin - 0.6" wide

R,o
R9
Rs
ClKR
OEM
OEl
(R7) RSl
Rs
Rs

R.
R3
R2

R,
Ro
Ao
A,
A2
A3
A.
As

70 ns
50 ns
35 ns

90 ns
60 ns
45 ns

44-pin

"'~
a:
()zodd:a:a:a:a:a:a:a:
lill '"
~
~ iii

R11
R'2
R'3
R,o
RSM (R,s)
BS (B7)
B6
B5
GND
B.
Vee
B3
B2
B,
Bo
RND
ClKB
ClKA
AS (A7)
A6

0

OEl
(R7) RSl
Ro
Rs
Ro
R3
R2
R,
Ro
Ao
NC

7

N

ro

6 5 0 3 2 :1: 04 43 42 41 40
:_,

30

NC
BS(B7)
Bo
Bs
GND
Bo
Vee
B3
B2
B,

29

Bo

39

8

38

9
10

37
36

11

35

Top
View

12
13

34
33
32

"

15
16
17

31

18 19 20 21 22 23 24 25 26 27 28

<~.il«<~~~~!;l

-...J...Ja:

:5,.00

LMU08PC70
LMU08PC50
LMU08PC35

LMU08JC70
LMU08JC50
LMU08JC35

LMU08CMB90
LMU08CMB60
LMU08CMB45

LMU08KMB90
LMU08KMB60
LMU08KMB45

=========================Multipliers
4-8

06129195-LDS.0818U-K

--------_
...... _--- --- -----~--~

LMU08/8U

-~--DEVICES INCORPORATED

40-pin -

8 X 8-bit Parallel Multiplier

0.6" wide

R10
R.
R.
ClKR
OEM
OEl
R7
R.
Rs
R4
R3
R2
Rl
Ro
Ao
Al
A2
A3
A4
As

70 ns
50 ns
35 ns

90 ns
60 ns
45 ns

44-pin

R11
R12
R13
R,.
R,S
B7
B.
Bs
GND
B4
Vee
B3
B2
Bl
Bo
RND
ClKB
ClKA
A7
As

0:

Ol~ ~

~ ~ ~

zod~&:a:a:lia:a:a:
0

-

N

•

6 5
3 2 :1: 44 43 42 41 40
L,
39
OEl 7
38
R7 8
37
R. 9
36
Rs 10
35
R. 11
Top
34
R3 12
View
33
R2 13
32
Rl 14
31C
Ro 15
30
Ao 16
NC )17 1. 20 21 22 23 24 25 26 27 2~9
,8

NC
B7
B.
Bs
GND
B4
Vee
B3
B2
Bl
Bo

«.:.;:««~~~~
--,--,0:

UU

LMU8UPC70
LMU8UPC50
LMU8UPC35

LMU8UJC70
LMU8UJC50
LMU8UJC35

LMU8UKMB90
LMU8UKMB60
LMU8UKMB45

LMU8UCMB90
LMU8UCMB60
LMU8UCMB45

========================= Multipliers
4-9

06/29/95-LDS.08/8U-K

a

----------- -- -------- - -~~-~

-...-.

......-.

-~---

DEVICES INCORPORATED

-= ..=.~=~
-----~
--~

LMU12

-

=-~:...:==--.-..-

12 x 12-bit Parallel Multiplier

o 35 ns Worst-Case Multiply Time
o Low Power CMOS Technology
o Replaces TRW MPY012H

o
o

o
o

Two's Complement, Unsigned, or
Mixed Operands
Three-State Outputs
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 64-pin Sidebraze, Hermetic DIP
• 68-pin Ceramic PGA

TCA

The LMU12 is a high-speed, low
power 12-bit parallel multiplier. It is
pin and functionally compatible with
TRW MPY012H devices. Full military
ambient temperature range operation
is attained by the use of advanced
CMOS technology.
The LMU12 produces the 24-bit
product of two 12-bit numbers. Data
present at the A inputs, along with
the TCA control bit, is loaded into the
A register on the rising edge of
CLK A. B data and the TCB control
bit are similarly loaded by CLK B.

A11'o

TC6

611·0

ClK A - _ _ < l - - - - - - b
ClK 6

-+r-----'==+==-~

0:

RND

-------'~

UJ

til 1 - - - - - . - 1

The TCA and TCB controls specify
the A and B operands as two's
complement when HIGH, or unsigned magnitude when LOW.
RND is loaded on the rising edge of
the logical OR of CLK A and CLK B.
RND, when HIGH, adds '1' to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 12 least
significant bits produces a result
correctly rounded to 12-bit precision.
At the output, the Right Shift control
(RS) selects either of two output
formats. RS LOW produces a 23-bit
product with a copy of the sign bit
inserted in the MSB position of the
least significant half. RS HIGH gives
a full 24-bit product. Two 12-bit
output registers are provided to hold
the most and least significant halves
of the result (MSP and LSP) as
defined by RS. These registers are
loaded on the rising edge of CLK M
and CLK L respectively. For asynchronous output, these registers may
be made transparent by setting the
feed through control (FT) HIGH.

i3
UJ
0:

RS

---------.1

12
12
FT ----------~--~--+_-_
ClK M - - - - - - - - - - { >

ClK l

OEM -----------~

R23·12

/ r - - - OEl

R11·0

========================= Multipliers
4-11

06/29/95-LDS.12-1

•

LMU12
DEVICES INCORPORATED

12 x 12-bit Parallel Multiplier

AIN

BIN

-----Fractional Two's Complement (TCA, TCB = 1) - - - - 111109,*2101
_20 2-1 2-2
2-9 Z-10Z-11

111 10 9
_20 Z-1 2-2

(Sign)

(Sign)

Integer Two's Complement (TCA, TCB

~

111 10 9
_2 11 210 2 9

2
01
22 21 20

2 1 0
Z-9 Z-10Z-11

=1)

111 10 9
_2 11 2 10 2 9

(Sign)

'*
~

2
0
22 21 20

(Sign)

Unsigned Fractional (TCA, TCB
2 1 01
~ 2-102-112-12

111 10 9
2-1 Z-2 z-3

111 10 9
2-1 Z-2 z-3

Unsigned Integer (TCA, TCB

~

111 10 9
211 210 2 9

=0)

2
01
22 21 20

=0)

111 10 9
211 2 10 2 9

MSP

'*

~

2
0
22 21 2 0

LSP

------Fractlonal Two's Complement (RS
123 22 21
_20 2-1 2-2

2 1 0
~ 2-102-112-12

14 13 12

I

=0 ) - - - - - -

111 10 9
_20 2-12 2-13

(Sign)

'*

2 1 0
2-20 2-21 Z-22

(Sign)

'* z-a

------Fractional Two's Complement (RS = 1 ) - - - - - 123 22 21
_21 20 2-1

14 13 121
2-9 2-10

111 10 9
Z-11 2-12 2-13

I!i

2 1 0
2-20 2-21 ~2

I

(Sign)

- - - - - - - I n t e g e r Two's Complement (RS = 1) - - - - - - 1232221,*1413121
_2 23 222 221
214 2 13 212

11110 91!i 2
0
211 2 10 2 9
22 21 20

(Sign)

--------Unsigned Fractional (RS = 1) - - - - - - - 123 22 21
2-1 2-2 2-3

I!i 14

13 121
2-102-112-12

'*

111 10 9
2-13 Z-14 Z-15

I!i

2 1 0
2-22 Z-23 2-24

I

- - - - - - - - U n s i g n e d Integer (RS = 1 ) - - - - - - - 123 22 21
223 222 221

14 13 121
214 2 13 212

111 10 9
211 2 10 29

I!i

2
0
22 21 2 0

=========================Multipliers
4-12

06/29/95-LDS.12·1

- - --= ===-== =
....
~.-.-.-~

LMU12

...-.~--

-~--"""'-""
DEVICES INCORPORATED

12 x 12-bit Parallel Multiplier

Storage temperature ............................................................................................................ --65°C to +150°C
Operating ambient temperature ........................................................................................... -55°C to +125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ....................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 rnA
Latchup current ................................................................................................................................ > 400 rnA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to + 125°C

Test Condition

VOH

Output High Voltage

Vee = Min., IOH = -2.0 rnA

VOL

Output Low Voltage

Vee = Min., IOL = 8.0 rnA

\IIH

Input High Voltage

\ilL

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground

~

VIN

loz

Output Leakage Current

Ground

~

VOUT

leel

Vee Current, Dynamic

(Notes 5, 6)

lee2

Vee Current, Quiescent

(Note 7)

~

~

Vee

~

5.25 V

4.50 V

~

Vee

~

5.50 V

Min

Parameter

•

Supply Voltage
4.75 V

Typ

Max

3.5

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Vee (Note 12)

±20

~

~

±20

~

25

rnA

1.0

rnA

Vee (Note 12)
12

=========================Multipliers
4·13

06/29/95-LDS.12·1

LMU12
DEVICES INCORPORATED

12 x 12-bit Parallel Multiplier

.I::::.ts~ ~tH~

INPUT

)I(

I-tpw

CLKA
CLKS

i

tpw

~

tMC

l'

CLKL
CLKM

tD

tMUC

OEL
OEM
tENA--j

-t="tDIS-=:l
R23-Q

HIGH IMPEDANCE

~

=========================Multipliers
4-14

06/29/95-LDS.12-1

--.. -- -......-- -----~--~

.--.

-~--

-

LMU12

~--

-~---

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping

of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo
4. Actual test conditions may vary
from those designated but operation is
guaranteed as specified.
5. Supply current for a given application can be accurately approximated
by:
NCV2 F

4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

12 x 12-bit Parallel Multiplier

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/toIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDiSABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.
This device has high-speed outputs ca-

pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at

the high temperature extreme, which is
the worst case for leakage current.

tENA

-==~~~2!!l!:~~~==
t

TRISTATE
OUTPUTS -

O.2V

a. A O.lI1F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device Vee
and the tester common, and device
ground and tester common.
b. Ground and Vee supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case re8. These parameters are guaranteed
quirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

========================= Multipliers
4-15

06/29/95-l0S.12-1

II

-

- -.....
- -------.. _--------~

~-~

LMU12

-~--~

DEVICES INCORPORATED

12 x 12-bit Parallel Multiplier

64-pin

68-pin
A7
As

A5
A4
A3

A2
Al
Ao
Ro
Rl
R2
R3
R4
Rs
Rs
R7
RB
R.
RIO
R11
OEL
OEM
GND
GND
FT
RS
CLKL
CLKM
R12
R13
Rl'
R15

1
2
3

•

61

5
6

9
10
11
12
13
1.
15
16
17
18
19
20
21
22
23
2.
25
26
27
28
29
30
31
32

.,

AB
A.
Al0
A11
CLKA
CLKB
RND
TCA
80

2
A

B
C

82
83
84
85
Vee
Vee
Vee
8s
B7
BB
8.
810
811
TC8
R23

0
E

F
G
H

A22
K

R21

R20
R19
R18
R17
R16

3

4

5

6

7

8

10

" '"j '-'
" '-'
" '-'
" '-'
" '-'
" '-'
" '-'
"
'-'
NC
Ao
Al0 CLKA RND
A2
M
As
AB
"
"
"
"
"
"
"
"
"
'-'
'-'
'-'
'-'
'-'
'-' '-'
'-'
Rl
Ro
Al
As '-'
A5 '-'
A7
A.
A11 CLKB TCA
" '-'
"
"
'-'
'-'
R3
R2
81
" '-'
"
"
'-'
'-'
Rs
R.
B3
" '-'
"
"
Top View
'-'
'-'
R7
Rs
85
Through Package
"
"
" '-'
'-'
'-'
R.
RB
Vee
(i.e., Component Side Pinout)
"
"
" '-'
'-'
'-'
R11
Rl0
Bs
," , "
"
'-'
'-'
OEM OEL
B8
" '-'
"
"
'-'
'-'
GND GND
Bl0
,.
, ..
" '-' '-' '-' '-'
" '-'
" '-'
" '-'
" '-'
" '-'
'-'
NC
FT CLKL R12 Rl' R16 R18 R20 R22 TCB
" '-'
" " '-'
" " '-'
" " '-'
" "
'-'
RS CLKM '-'
R13 R15 '-'
NC
R17 Rl. '-'
R21
R23 '-'

""

65 ns
45 ns
35 ns

LMU12DC65
LMU12DC45
LMU12DC35

LMU12GC65
LMU12GC45
LMU12GC35

75 ns
55 ns
45 ns

LMU12DM75
LMU12DM55
LMU12DM45

LMU12GM75
LMU12GM55
LMU12GM45

75 ns
55 ns
45 ns

LMU12DMB75
LMU12DMB55
LMU12DMB45

LMU12GMB75
LMU12GMB55
LMU12GMB45

11

"
'-'
NC
"
'-'
Bo
"
'-'
B2
"
'-'
B4
"
'-'
Vee
"
'-'
Vee
"
'-'
B7
"'-'
B.
"
'-'
B11

=========================Multipliers
4-16

06/29/95-LDS.12-1

- --

--==---

= ~~=~
-=-:....=:....=

LMU112

~

12 x 12-bit Parallel Multiplier

-~---

o

50 ns Worst-Case Multiply Time

o Low Power CMOS Technology
o Replaces TRW MPYl12K
o Two's Complement or Unsigned
Operands
o Three-State Outputs
o Available 100% Screened to
MIL-STD-883, Class B
o Package Styles Available:
• 48-pin Plastic DIP
• 48-pin Sidebraze, Hermetic DIP
• 52-pin Plastic LCC, J-Lead

The LMU112 is a high-speed, low
power 12-bit parallel multiplier built
using advanced CMOS technology.
The LMU112 is pin and functionally
compatible with TRW's MPYl12K.
The A and B input operands are
loaded into their respective registers
on the rising edge of the separate
clock inputs (CLK A and CLK B).
Two's complement or unsigned
magnitude operands are accommodated via the operand control bit (TC)

TC

A11·0

For two's complement operands, the
17 most significant bits at the output
of the asynchronous multiplier array
are shifted one bit position to the left.
This is done to discard the redundant
copy of the sign-bit, which is in the
most significant bit position, and
extend the bit precision by one bit.
The result is then truncated to the 16
MSB's and loaded into the output
register on the rising edge of CLK B.
The contents of the output register are
made available via three-state buffers
by asserting OE. When OE is deasserted, the outputs (R23-S) are in the
high impedance state.

ClK A - - - - - - - - 1 >
ClKB

B11·0

which is loaded along with the B
operands. The operands are specified
to be in two's complement format
when TC is asserted and unsigned
magnitude when TC is deasserted.
Mixed mode operation is not allowed.

----~r---~~==+====---~

24

FORMAT ADJUST

16

RESULT REGISTER

OE ------------------------~

16

R23·e

=========================Multipliers
4-17

06129195-LDS.112·F

•

- - --LufisC

LMU112

-~--~

DEVICES INCORPORATED

12 x 12-bit Parallel Multiplier

AIN

BIN

------Fractional Two's Complement (TC = 1) - - - - - 111 10 9
_20 :!1 2-2

~ 2

1 0
2-9 :!10:!11

I

111 10 9
_20 :!1 :!2

(Sign)

~ 2

1 0
2-92-10211

(Sign)

Integer Two's Complement (TC
111 10 9
_2 11 2 10 2 9

~

2
o
22 21 2 0

I

=1)

111 10 9
_2 11 2 10 2 9

(Sign)

~

2
0
22 21 20

(Sign)

Unsigned Fractional (TC
111 10 9
2-1 2-2 2-3

2 1 oI
~ 2-102-112-12

111 10 9
:!1 2-2 2-3

Unsigned Integer (TC
111 10 9
211 2 10 2 9

~

2
o
22 21 2 0

=0)

I

=0)
111 10 9
211 2 10 29

MSP

2 1 0
~ 2-102-112-12

~

2
0
22 21 2 0

LSP

-----Fractional Two's Complement-----

I

123 22 21 ~ 14 13 121
_20 2-1 2-2
2-9 2-10 2-11

111 10 9 8
2-122-132-14 :!15

(Sign)

------Integer Two's Complement - - - - - 123 22 21
_222221 2 20

~ 14 13 121

111 10 9 8
2 10 2 9 28 27

2 13 212 211

I

(Sign)

-------Unsigned Fractional------123 22 21
2-1 ~ ~

~ 14 13 121

111 10 9 81
2-132-142-15 :!16

2-102-11 :!12

-------Unsigned Integer - - - - - - 123 22 21
2 23 222 221

~ 14 13 121

111 10 9 8
211 2 10 2 9 28

214 2 13 212

I

=========================Multipliers
4-18

06/29/95-LDS.112-F

_---------_- --.......- -----

LMU112

-.-.-......---....

-~---

DEVICES INCORPORATED

12

X

12-bit Parallel Multiplier

Storage temperature ............................................................................................................ -65°C to +150°C
Operating ambient temperature ........................................................................................... -55°C to +125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

c:. .

r.•·.......
()'""'P""'~R...A
...T"")IN""".• ~""·i
· .... b""~D
....
·I...fl..;.6.....
·~....
S._
.···T<-"O-'f_lI.e....6I....t""SfJe
....
· • • · ....C....
ifl_·(jd_·.···""'et..;.e~ct-'ric._ia......I ....
~I1...id.·s""'
. . ·•.··•~~f_tc....fTl....·nflL··•. ·•··....¢h~a"""riil....b.te"""il
. . ....·~....f#;"'-.··~""·~.................;.;...~
. .: •. . . . • . •'""
.•.••.• _
.••~
...................;;;t
..••.•...:...
.•••..• ~~~_-I •
Mode

Temperature Range (Ambient)

Active Operation, Commercial
Active Operation, Military

I·.·""; .. ·••••.. •••••·••·•• .....

Symbol

. ?J..z,

••

21,8\l"';;'~;"""

',;

Supply Voltage

O°C to +70°C

4.75 V:5 Vee:5 5.25 V

-55°C to + 125°C

4.50 V :5 Vee :5 5.50 V

·············;..·~:..j,~;1t:·······,;;·····; ~4)Ir\.·

Parameter

Test Condition

VOH

Output High Voltage

Vee

=Min., 10H =-2.0 mA

VOL

Output Low Voltage

Vee

= Min., 10L =8.0 mA

ViH

Input High Voltage

ViL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

• •·...r·t . . .·...i.·.H. •.. ·r·.···. .· · .· •.. ···i./.·····.·.···········.... .• •.•. . .
Min

Typ

Max

3.5

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground :5 VIN :5 Vee (Note 12)

±20

~

Output Leakage Current

Ground :5 VOUT:5 Vee (Note 12)

±20

~

lee1

Vee Current, Dynamic

(Notes 5, 6)

20

mA

lee2

Vee Current, Quiescent

(Note 7)

1.0

mA

10

========================== Multipliers
4-19

06/29/95-LOS.112-F

LMU112
DEVICES INCORPORATED

12 x 12-bit Parallel Multiplier

65
Symbol

Parameter

Min

55
Max

Min

tMC

Clocked Multiply Time

tpw

Clock Pulse Width

20

20

ts

Input Register Setup Time

15

15

tH

Input Register Hold Time

3

3

65

Max

55

tD

Output Delay

30

30

tENA

Three-State Output Enable Delay (Note 11)

30

30

tDIS

Three-State Output Disable Delay (Note 11)

30

30

SVMCHI
~ts- -tH-=1
INPUT

tMC
ClKA

elKS

-{

tpw

tpw

~~----tD----~Jl

R23-8

__
L_""=1 """""~" L""=1:~_~-

==========================Multipliers
4-20

06/29/95-LDS.112-F

...-..--- --............
-.---.---""-"'--._---_.......----~

LMU112

-...

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.

3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

12 x 12-bit Parallel Multiplier

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
Parasitic
1.5 V may be used.
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tOISABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

tENA.
-===~~i!!!!LMU16/~16BL()Cj(

The LMU16 and LMU216 are highspeed, low power 16-bit parallel
multipliers. The LMU16 and LMU216
are functionally identical; they differ
only in packaging. Full military
ambient temperature range operation
is attained by the use of advanced
CMOS technology.

RND is loaded on the rising edge of
the logical OR of CLK A and CLK B.
RND, when HIGH, adds T to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.

The LMU16 and LMU216 produce the
32-bit product of two 16-bit numbers.
Data present at the A inputs, along with
the TCA control bit, is loaded into the A
register on the rising edge of CLK A. B
data and the TCB control bit are
similarly loaded by CLK B. The TCA
and TCB controls specify the A and B
operands as two's complement when
HIGH, or unsigned magnitude when
LOW.

At the output, the Right Shift control
(RS) selects either of two output
•
formats. RS LOW produces a 31-bit
product with a copy of the sign bit
inserted in the MSB postion of the
least significant half. RS HIGH gives a
full 32-bit product. Two 16-bit output
registers are provided to hold the
most and least significant halves of the
result (MSP and LSP) as defined by
RS. These registers are loaded on the
rising edge of CLK M and CLK L
respectively. For asynchronous
output, these registers may be made
transparent by setting the feed
through control (FT) HIGH.

DIAt;BAM
B15-01
R1S-0

RND

The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP
outputs to be driven by the m;::o.;:"st~~
significant half of the result. MSPSEL
HIGH routes the least significant half
of the result to the MSP outputs. In
addition, the LSP is available via the B
port through a separate three-state
buffer.

-----.J

elK l

OEM

The output multiplexer control
MSPSEL uses a pin which is a supply
ground in the TRW MPY016H/
TMC216H. When this control is LOW
(GND), the function is that of the
MPY016H/TMC216H, thus allowing
full compatibility.

----------0.

R31-16

========================== Multipliers
4-23

06/30/95-lDS .16/216-H

~

--..--.
---- --.-.-........- ---------------....
- - -~

LMU16/216

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

AIN

BIN

- - - - - Fractional Two's Complement (TCA, TCB

115 14 13 j+ 2
_20 2-1 2-2

1

0 1

=1) - - - - -

115 14 13 j+ 2 1 0
_20 2-1 22
2 13 2 14 2 15

(Sign)

(Sign)

- - - - - - Integer Two's Complement (TCA, TCB

=1) - - - - - -

115 14 13 j+ 2
0 1
_2 15 2'4 2'3
22 2' 20

115 14 13 j+ 2
0
_2 15 2'4 2'3
22 2' 2°

(Sign)

(Sign)

-------Unsigned Fractional (TCA, TCB

115 14 13 j+ 2

1

0 1

=0 ) - - - - - - -

115 14 13 j+ 2

1

0

=0 ) - - - - - - o
115 14 13 j+ 2

- - - - - - - U n s i g n e d Integer (TCA, TCB

L...:117,:-5_17:4_1~3_j+,"\.!,-=;2:--,:,.--:::0,.....1
2 15 2'4 2'3

22 2' 20

2 15 2'4 2'3

MSP

22 2' 2°

LSP

- - - - - - Fractional Two's Complement (RS

=0) - - - - - -

131 30 29 j+ 18 17 161
_20 2-1 2-2
2-132-142-15

115 14 13 j+ 2 1 0
_2°2-162-17
2-282-292-30

(Sign)

(Sign)

- - - - - - Fractional Two's Complement (RS

131 30 29 j+ 18 17 161
_2' 2° 2-1

= 1) - - - - - -

115 14 13 j+ 2

0

(Sign)

- - - - - - - I n t e g e r Two's Complement (RS = 1) - - - - - - -

131 30 29 j+ 18 17 16\
_2 31 2 30 229
2'8 217 2'6

115 14 13 j+ 2

0

(Sign)

- - - - - - - - Unsigned Fractional (RS = 1) - - - - - - - -

131 30 29 j+ 18 17 161
2-142-152-16
2-1 2-2 2-3

115 14 13 j+ 2 1 0
2-17 2-18 2-19
2-3°2--31 2--32

- - - - - - - - Unsigned Integer (RS

131 30 29 j+ 18 17 161
2'8 217 2'6

=1) - - - - - - - 115 14 13 j+ 2

0

==========================Multipliers
4-24

06/30/95-LDS.16/216-H

------- ----_..--__-..-- - --~---

-

LMU16/216

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

Storage temperature ............................................................................................................ --65°C to +150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

Parameter

Test Condition

VoH

Output High Voltage

Vee = Min., IOH = -2.0 mA

VoL

Output Low Voltage

Vee = Min., IOL = 8.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

loz

II

Supply Voltage
4.75 V:O:;; Vee:o:;; 5.25 V
4.50 V

:0:;;

Vee

:0:;;

Min

5.50 V

Typ

Max

3.5

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground:O:;; VIN:O:;; Vee (Note 12)

±20

~

Output Leakage Current

Ground:o:;; VOUT:O:;; Vee (Note 12)

±20

~

leel

Vee Current, Dynamic

(Notes 5,6)

25

mA

lee2

Vee Current, Quiescent

(Note 7)

1.0

mA

12

========================= Multipliers
4-25

OS/30/95-LDS.l S/21 S-H

----

.~~.~

........-

----~-

LMU16/216

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

~------~-...-

-~---

.t=IS-I-I':j

INPUT

)\\

JK.
t---Ipw

ClKA
ClKB

Ipw

~

Jf
10

ClKl
ClKM

:J

IMC

.I:=.ISEL-

-*
IMUC

¥

~
IDI~

t.:=IENA
HIGH IMPEDANCE

R31-O

=========================Multipliers
4-26

06130195-LDS.161216-H

--

- -. ----------.--- --........---...-~-~

LMU16/216

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

I NOteS.
1. Maximum Ratings indicate stress 9. AC specifications are tested with
specifications only. Functional oper- input transition times less than 3 ns,
ation of these products at values be- output reference levels of 1.5 V (except
yond those indicated in the Operating tENA/tDiS test), and input levels of
Conditions table is not implied. Expo- nominally 0 to 3.0 V. Output loading
sure to maximum rating conditions for may be a resistive divider which
extended periods may affect reliability. provides for specified IOH and IOL at an
output voltage of VOH min and VOL
2. The products described by this specmax respectively. Alternatively, a
ification include internal circuitry de- diode bridge with upper and lower
signed to protect the chip from damag- current sources of IOH and IOL
ing substrate injection currents and ac- respectively, and a balancing voltage of
cumulations of static charge. Never- 1.5 V may be used.
Parasitic
theless, conventional precautions capacitance is 30 pF minimum, and
should be observed during storage,
may be distributed. For tENABLE and
handling, and use of these circuits in tDISABLE measurements, the load
order to avoid exposure to excessive current is increased to 10 mA to reduce
electrical stress values.
the RC delay component of the
3. This device provides hard clamping measurement.
of transient undershoot and overshoot. This device has high-speed outputs caInput levels below ground or above Vee pable of large instantaneous current
will be clamped beginning at -0.6 V and pulses and fast turn-on/ turn-off times.
Vee + 0.6 V. The device can withstand As a result, care must be exercised in
indefinite operation with inputs in the the testing of this device. The following
range of -D.5 V to +7.0 V. Device opera- measures are recommended:
tion will not be adversely affected, however, input current levels will be well in a. A 0.1 ~F ceramic capacitor should be
excess of 100 rnA.
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated
b. Ground and Vee supply planes
by:
must be brought directly to the DUT

4
where
N
C
V
F

= total number of device outputs
= capacitive load per output
= supply voltage
=

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at

the high temperature extreme, which is
the worst case for leakage current.

lOIS

tENA

OE
TRISTATE _ _ _~~:""'==~~
OUTPUTS

t

__

o.zv

socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

clock frequency

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.

========================== Multipliers
4-27

06/30/95-LDS.16/216·H

•

---------.. __
-..---.....----..-------....---

LMU16/216

-

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

68-pin

64-pin
A4
A3
A2
Al
Ao
DEL
ClK l
ClKS
Ro, Bo
R1, B1
R2,B2
R3, B3
A4,B4
AS,Bs
R6,B6
A7, B7
Rs,Bs
R9,B9
R10,B10
R11,B11
R12,B12
R13,B13
R14,B14
R1S,B1S
A16
An
A18
A19
A20
A21
A22
A23

1
2
3
4

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

A5
A6
A7

3

AlO
Al1
A12
A13
A14
A15
ClKA
AND

A

B

",_I
,-

A/Bl

,_I
R/B3
,_I
"
,,_I
R/Bl
,_I
"
RIB,
,_I
"
,,_I
,_I
"
,_I
"
,~

C
D

RIB5

TCS

E

Vee
Vee

F

GND
GND
MSPSEl

G

FT

RlBll

AS
OEM
ClKM
A31
AM
A29
A28
A27
A26
A25
A24

H

K

,,_I
,_I
,,_I
,_I
"
,,_I
,_I
"
,_I
"
,,_I
,_I
"
,_I
"
,_I
NC
,~

R/B4
R/B6
R/B8

9

RIB12

RIB15

RIB14

NC

R16
,~

Rn

11

A1

A3

A5

A7

A9

Al1

A2

A4

A6

A8

A10

A12

NC

A14

A13

CLKA

A1S

TCA

RND

,~

Ao

,~

TCB

RlBlO

RIB13

10

,,,,,,,, , ,_I
'..J ,_I ,_I ,_I ,_I ,_I
,,,,,,,,,_I ,_I ,_I ,_I ,_I ,_I ,_I ,_I ,_I
,_I
" ,_I
,,_I
" ,_I
,_I
" ,_I
"
Top View
Through Package
,_I
,_I
" "
Vee
(i.e., Component Side Pinout)
,, , ,_I

CLKB DEL

RlBo CLK L
R/B2

4

GND

,.,

Vee

"

~~_I

MSPSEL GND

,_I
" ,_I
"
FT
,_I
,_I
,_I
,_I
,_I
,_I
,_I
,_I
,_I
"
" " "
" "
,,,_I
,_I ,_I
" ,_I
"
" ,_I ,_I ,_I
'-'
RS

,~

R18

R20

Rl'

R21

,~

,~

R30 CLKM OEM

R22

R24

R26

R28
,~

,~

R23

R25

R27

R29

R3l

,~

Speed

Sidebraze Hermetic DIP
(06)

Ceramic Pin Grid Array
(G2)

65 ns
55 ns
45 ns

LMU16DC65
LMU16DC55
LMU16DC45

LMU16GC65
LMU16GC55
LMU16GC45

75 ns
65 ns
55 ns

LMU16DM75
LMU16DM65
LMU16DM55

LMU16GM75
LMU16GM65
LMU16GM55

75 ns
65 ns
55 ns

LMU16DMB75
LMU16DMB65
LMU16DMB55

LMU16GMB75
LMU16GMB65
LMU16GMB55

NC

==========================Multipliers
4-28

06/30/9S-LOS.16/216-H

- --......------_
--..............
---......-

-~--~-~---

LMU16/216

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

~

68-pin

9

8

7 6

5 4

3

2 :1i ~ ~ ~~ ~ ~ ~ ~

RSl
Rso

60

NC

11

59

A12

R29

12

58

R28

13

57

All
Al0

R27

14

58

A9

R26

15

55

As

R25

16

54

A7

R24
R23

17
18

53

A6

62

R22

19

51

A5
A4

R21

20

50

A3

R20
R19

21

49

A2

22

48

Al

R1S

23

47

Ao

R17

24

46

~6

~

46

NC

26

OEl
ClKl
ClKB

10

:_,

Top
View

44

V~~OO~~~~~~~~M~~~49

•

~~~~~~~~~~~~~~~~~
to ' 400 rnA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to + 125°C

II

Supply Voltage
4.75 V:<::; Vee:<::; 5.25 V
4.50 V :<: ; Vee :<: ; 5.50 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., IOH = -2.0 rnA

3.5

VoL

Output Low Voltage

Vee = Min., IOL = B.O rnA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

loz

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

O.B

V

Ground:<::; VIN:<::; Vee (Note 12)

±20

~

Output Leakage Current

Ground:<::; VOUT:<::; Vee (Note 12)

±20

~

leet

Vee Current, Dynamic

(Notes 5, 6)

45

rnA

lee2

Vee Current, Quiescent

(Note 7)

1.0

rnA

25

========================== Multipliers
4·33

06/30/95-LDS.l B·G

--

- ......
--_....,.._
__ ......--- -------------.-..

LMU18

-~

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

Is

INPUT

IH

---l!'-----f--.Jf'----------------------

t~--+-----t~----~~-t~

CLOCK

to

tMC
tMUC

1------tsEL----i
OEM
OEL _ _ _ _ _ _ _J

R31·0

=========================Multipliers
4-34

06/30/95-LDS.18·G

---- -- ------------.-.
-~~-~

LMU18

~----

-~---

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

16 x 16-bit Parallel Multiplier

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
Parasitic
1.5 V may be used.
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
torSABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

tE~
-==~~~~~~~==

TRISTATE
OUTPUTS _

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

a. A 0.11JF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated
b. Ground and Vee supply planes
by:
must be brought directly to the DUT
NCV2 F
socket or contactor fingers.

4

where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case re8. These parameters are guaranteed
but not 100% tested.
quirementsofall parts. Responsesfrom
the internal circuitry are specified from

==========================Multipliers
4-35

06/30/95-LDS.18·G

II

_- .............
_.......
- _..--_--~---- -------~---

--

LMU18

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

84-pin

87654321MM~~oo~~nM~

•

BlO
B11

74

All

73

A12

B12

A13

B13

A14

B14

A15

B15

ENA

ENB
ClK

RND
TCA
TCB
Vee

OEl

GND

Top
View

Vee

Ro

GND
GND
MSPSEl
FT

Rl

R2
~

~

R4
R5

OEM
ENR

~

~

~

~

RB

R9

32

55

R30

54

R29

~M~~~~~~~Ga"a~Q~GW~~~

65 ns
45 ns
35 ns

LMU18JC65
LMU18JC45
LMU18JC35

==========================Multipliers
4-36

06/30/9s-LDS.l B-G

-------......--- -----------.......

LMU18

-...--............--_

-~---

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

84-pin

2
A

B

T , ...

'-'
89

"
'~I
87

"
'~I

4

5

86

"
'~I
B4

88

85

812

810

"
'~I

"
'~I

D

"
'~I

,_I
"

," I
,_I
"

814

"
'~I

Ro

EN8

"
'~I

"
'~I

813
815

"
'~I

G

R1

H

"

'~I
R4

J

811

L

83

8

7

"
'~I

9

"

,~I

"

,~I

A2

A5

A7

A6

A9

10

"

'~I

11

, ...

As

'-'
A11

82

A1

A3

A10

A13

,~I

"

,~I

"

,~I

"

,_I
" ,_I
"

80

Ao

A4

A12

A14

"
'~I

,_I
"
,_I
"
Vee
,_I
"

"
'~I
R2

Through Package

"
'~I

"
'~I

"

"
'~I

'~I

"
'~I
RS

'-'
R9

R12

"
'~I

,_I
" ,_I
"

FT MSPSEL

,....

\_1

R5

R11

"
'~I

R13

•

GND GND RND

"

R10

ENA

TCA TC8

,~I

(Le., Component Side Pinout)

"

,~I

A15

Vee

'~I

"
'~I

,R7...

,_I
"

Top View

R3

,_I
"
R8
,_I
" ,_I
"

"
'~I
R6

K

"
'~I

81

OEl ClK GND

F

6

" ,_I
"
" '~I
" '~I
" '~I
" '~I
" ,_I
" '~I
" ,~I
" ,_I
" ,_I
'~I

C

E

3

, ....

\_1

ENR OEM

"
'~I

"
'~I

R14

"
'~I

R15

"
'~I

R17

R18

GND

Vee

,_I
"
"

,~I

R16

"
'~I

"
'~I

R19

65 ns
45 ns
35 ns

LMU18GC65
LMU18GC45
LMU18GC35

75 ns
55 ns
45 ns

LMU18GM75
LMU18GM55
LMU18GM45

75 ns
55 ns
45 ns

LMU18GMB75
LMU18GMB55
LMU18GMB45

"
'~I

"
'~I

R22

"
'~I

R21

R30

"
'~I

R24

,~I

"

,~I

R20

R23

"

"
'~I

R27

"

'~I

R25

"
'~I

R31

"

,~I

"

,~I

R29

R31

"
'~I

'-'
R28

R26

, ...

=========================Multipliers
4-37

06/30/95-LDS.18-G

DEVICES INCORPORATED

---..~::...:=
------==---

LMU217

-

-~---

~

16 x 16-bit Parallel multiplier

o 45 ns Worst-Case Multiply Time

o
o
o
o
o
o

o
o

Low Power CMOS Technology
Replaces Cypress CY7C517,
IDT 7217L, and AMD Am29517
Single Clock Architecture with
Register Enables
Two's Complement, Unsigned, or
Mixed Operands
Three-State Outputs
DESC SMD No. 5962-87686
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 68-pin Plastic LCC, J-Lead
• 68-pin Ceramic LCC

The LMU217 is a high-speed, low
power 16-bit parallel multiplier. Full
military ambient temperature range
operation is attained by the use of
advanced CMOS technology.
The LMU217 produces the 32-bit
product of two 16-bit numbers. Data
present at the A inputs, along with the
TCA control bit, is loaded into the A
register on the rising edge of CLK. B
data and the TCB control bit are
similarly loaded. Loading of the A
and B registers is controlled by the
ENA and ENB controls. When HIGH,
these controls prevent application of
the clock to the respective register.
The TCA and TCB controls specify

B15·01

R,5·0

CLK_

-=k===i~~~~~-J

ENA ENB

a:

Lil

RND is loaded on the rising edge of
CLK, provided either ENA or ENB are
LOW. RND, when HIGH, adds T to
the most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
•
significant bits produces a result
correctly rounded to 16-bit precision.
At the output, the Right Shift control
(RS) selects either of two output
formats. RS LOW produces a 31-bit
product with a copy of the sign bit
inserted in the MSB postion of the
least significant half. RS HIGH gives a
full 32-bit product. Two 16-bit output
registers are provided to hold the
most and least significant halves of the
result (MSP and LSP) as defined by
RS. These registers are loaded on the
rising edge of CLK, subject to the ENR
control. When ENR is HIGH, clocking
of the result registers is prevented.
For asynchronous output, these
registers may be made transparent by
setting the feed through control (FT)
HIGH.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP
outputs to be driven by the most
significant half of the result. c;-;;==MSPSEL
HIGH routes the least significant half
of the result to the MSP pins. In
addition, the LSP is available via the B
port through a separate three-state
buffer.

f-

RND -----i~CfJ I------~

(!j
w

a:

16

the operands as two's complement
when HIGH, or unsigned magnitude
when LOW.

16

FT---------~-_+--_+-~

MSPSEL - - - - - - - - - - - . . . . .

RS1-16

==========================Multipliers
4-39

06/30/95-LDS.217·A

~

_- ----.......
---------- -........
-..__.-....

LMU217

-~---

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

BIN

AIN

- - - - - Fractional Two's Complement (TCA, TCB = 1) - - - - -

115 14 13 *
_2°2 ' 22

2 1 0 1
2'32142'5

115 14 13 *
_2°2 ' 22

(Sign)

2 1 0
2'32142'5

(Sign)

Integer Two's Complement (TCA, TCB = 1)

115 14 13~ 2 1 o 1
22 2' 2°
_2'5 2 14 2'3

0
115 14 13 ~ 2
22 2' 2°
_2 '5 214 2'3

(Sign)

(Sign)

-------Unsigned Fractional (TCA, TCB = 0 ) - - - - - - -

115 14 13 *

2

0 1

115 14 13 *

2

1

0

- - - - - - - U n s i g n e d Integer (TCA, TCB = 0 ) - - - - - - -

L.:11~5-17.4-1:..;:3:--~.>..~~2::__':__'0"::_'1
215 214 213

115 14 13 *
215 214 2'3

22 2' 20

o
2
22 2' 2°

LSP

MSP

- - - - - - Fractional Two's Complement (RS = 0) - - - - - -

131 30 29 *
_20 2 1 2-2

18 17 161
2 13 2 142 15

115 14 13 *
_2°2-162-17

(Sign)

2 1 0
2-282-292-30

(Sign)

------Fractional Two's Complement (RS = 1) - - - - - -

1313029*1817161
_2' 20 2 1
2 122 13 2 14

1151413* 2 1 0
2-152-162-17
2-282-292-30

(Sign)

- - - - - - - I n t e g e r Two's Complement (RS = 1) - - - - - - -

131 30 29 *
_2 31 230 229

18 17 161
2'8 217 2'6

115 14 13 *
2'5 214 2'3

2
0
22 2' 2°

(Sign)

- - - - - - - - Unsigned Fractional (RS = 1) - - - - - - - -

131 30 29 *

18 17 161

115 14 13 *
2 17 2 18 2 19

2 1 0
2--30 2 31 2--32

- - - - - - - - Unsigned Integer (RS = 1) - - - - - - - -

131 30 29 *

18 17 161

115 14 13 *

2

0

=========================Multipliers
4-40

06/30/95-LDS.217-A

-

- -- -------------------~~-~

LMU217

-~---

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C

Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs.......................................... ............................................. ....................... 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

~

Vee

~

5.25 V

4.50 V

~

Vee

~

5.50 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., IOH = -2.0 mA

3.5

VoL

Output Low Voltage

Vee = Min., IOL = 8.0 mA

V1H

Input High Voltage

V1L

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground

~

VIN

loz

Output Leakage Current

Ground

~

VOUT ~ Vee (Note 12)

lee1

Vee Current, Dynamic

(Notes 5,6)

lee2

Vee Current, Quiescent

(Note 7)

~

•

Supply Voltage
4.75 V

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

±20

IlA

±20

IlA

25

mA

1.0

mA

Vee (Note 12)

12

==========================Multipliers
4-41

06/30/95-LDS.217·A

_-----.....
-.......,.
--- -................
------...--~-.....--.

LMU217

-

~.....,

--.-.-

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

r--IS~

r--1H-

INPUT

i<;.
IS---J--IH

...r

~
-Ipw

IPW-==:j

Ipw

.1

'k.

ClK

'k.
10

IMC

!Mue

f
~
"I--IOIS---j

IsEL

~
eleNA
HIGH IMPEDANCE

R31-O

========================= Multipliers
4-42

06130195-LDS.217·A

-

. - .----- - -------- ----------........ - - -

LMU217

DEVICES INCORPORATEO

16 x 16-bit Parallel Multiplier

I NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.

2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tOISABLE measurements, the load
current is increased to 10 rnA to reduce
the RC delay component of the
measurement.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

tENA

tDIS

6~~;~~~

~~tE:±-~~~~t
0.2V

0.2 V

a. A 0.1 ~F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated
b. Ground and Vee supply planes
by:
must be brought directly to the DUT
socket or contactor fingers.
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
S. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

========================== Multipliers
4-43

06/30/95-LDS.217·A

II

- ------------

- ------- - --""'-"'"---

-~---

LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

58-pin

I~

°lil~ool:i:~iiHHB~il~!~~
zwOOC
~~~»~~ocw~~~
R31

10

2 :1: 68 67 66 65 64 63 62 61
:_!
60

NC

R30

11

59

A12

R29

12

58

All

R28

13

57

Al0

R27

14

56

A9

R26

15

55

As

R25

16

54

A?

R24

17

53

A6

52

As

51

A4

R23

9

8

7

6

5

4

3

Top
View

18

R22

19

R21

20

50

A3

R20

21

49

R19

22

48

A2
Al

R18

23

47

Ao

R17

24

46

R16

25

45

OEl
ClK

NC

26

44

ENB

V ••

M~

•• M ••

~

•••

~.48

Plastic J-Lead
Chip Carrier (J2)
LMU217JC65
LMU217JC55
LMU217JC45

75 ns
65 ns
55 ns

LMU217KMB75
LMU217KMB65
LMU217KMB55

=========================Multipliers
4-44

06/30/95-LDS.217-A

LMA 1009/2009

LEEi;;j:...;;
---

-~

~

o
o
o
o
o
o
o

o
o

12 x 12-bit Multiplier-Accumulator

45 ns Multiply-Accumulate Time
Low Power CMOS Technology
Replaces TRW TDC1009/TMC2009
Two's Complement or Unsigned
Operands
Accumulator Performs Preload,
Accumulate, and Subtract
Three-State Outputs
DESC SMD No. 5962-90996
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 64-pin Sidebraze, Hermetic DIP
• 68-pin Ceramic PGA
• 68-pin Plastic LCC, J-Lead
• 68-pin Ceramic LCC

The LMAI009 and LMA2009 are highspeed, low power 12-bit multiplieraccumulators. They are pin-for-pin
equivalent to the TRW TDClO09 /
TMC2009 multiplier-accumulators.
The LMA1009 and LMA2009 are
functionally identical; they differ only
in packaging. Full ambient temperature range operation is achieved by the
use of advanced CMOS technology.
The LMA1009 /2009 produces the 24bit product of two 12-bit numbers. The
results of a series of multiplications
may be accumulated to form the sum of
products. Accumulation is performed
to 27-bit precision with the multiplier
product sign extended as appropriate.

A11·o

B11-o

ClK A
ClK B

RND
TC
ACC
SUB

OEX
OEM
OEl
PREl

The ACC and SUB inputs control
accumulator operation. ACC lllGH
results in addition of the multiplier
product and the accumulator contents,
with the result stored in the accumulator register on the rising edge of CLK R.
ACC and SUB lllGH results in subtraction of the accumulator contents from
the multiplier product, with the result
stored in the accumulator register.
With ACC LOW, no accumulation
occurs and the next product is loaded
directly into the accumulator register.
The LMA1009 /2009 output register
(accumulator register) is divided into
three independently controlled sections.
The least significant result (LSR) and
most significant result (MSR) registers
are 12 bits in length. The extended
result register (XTR) is 3 bits long.

lEX
lEM
lEl

OEX
OEM
OEl

Data present at the A and B input
registers is latched on the rising edges
of CLK A and CLK B respectively.
RND, TC, ACC, and SUB controls are
latched on the rising edge of the logical
OR of CLK A and CLK B. TC specifies
the input as two's complement
(TC HIGH) or unsigned magnitude
(TCLOW). RND,whenlllGH,adds'l'
to the most significant bit position of
the least significant half of the product. . .
Subsequent truncation of the 12 least
significant bits produces a result
correctly rounded to 12-bit precision.

lEX
27

ClK R

3
R26-24

12

12

Each output register has an independent output enable control. In addition
to providing control of the three-state
output buffers, when OEX, OEM, or
OEL are lllGH and PREL is lllGH,
data can be preloaded via the bidirectional output pins into the respective
output registers. Data present on the
output pins is latched on the rising
edge of CLK R. The interrelation of
PREL and the enable controls is summarized in Table 1.

R11-0

R23-12

===================== Multiplier-Accumulators
4-45

06/29/95-LDS.10/2009-F

LMA1009/2009
DEVICES INCORPORATED

12 x 12-bit Multiplier-Accumulator

L

L

L

L

OUT

OUT OUT

L

L

L

H

OUT

OUT

Z

L

L

H

L

OUT

Z

OUT

L

L

H

H

OUT

Z

Z

L

H

L

L

Z

OUT OUT

L

H

L

H

Z

OUT

Z

L

H

H

L

Z

Z

OUT

Fractional Two's Complement (TC = 1)

111 10 9
_20 2-1 Z-2

(Sign)

(Sign)

~ 2

0
2-9 2-10 2-11

Integer Two's Complement (TC = 1)

L

H

H

H

Z

Z

z

H

L

L

L

Z

Z

Z

H

L

L

H

Z

Z

PREL
Z

111 10 9
_2 11 2 10 29

H

L

H

L

Z

PREL

H

L

H

H

Z

PREL PREL

H

H

L

L

PREL

Z

Z

H

H

L

H

PREL

Z

PREL

H

H

H

L

PREL PREL

H

H

H

H

PREL PREL PREL

oI

~2

22 21 20

(Sign)

111 10 9
_2 11 2 10 29

~

2
0
22 21 20

(Sign)

Unsigned Fractional (TC = 0)

111 10 9
2-1 z-2 2-3

oI

~2

2-102-112-12

111 10 9
2-1 2-2 ~

2
0
~ 2-102-112-12

Z

PREL= Preload data to appropriate register
OUT = Register available on output pins
Z
= High impedance state

XTR

111 10 9 ~ 2
01
_20 2-1 2-2
2-9 2-10 2-11

Unsigned Integer (TC = 0)

111 10 9
211 2 10 29

~

2
o
22 21 20

I

111 10 9
211 2 10 29

MSR

~

2
0
22 21 20

LSR

Fractional Two's Complement

126 25 241
_24 23 22

123 22 21 ~ 14 13 121
21 20 2-1
2--8 2-92-10

0
111 10 9 ~ 2
Z-20 2-21 2-22
2-11 2-12 2-13

(Sign)

Integer Two's Complement

126 25 241
_226 2 25 224

123 22 21 ~ 14 13 121
223 222 221
214 2 13 212

111 10 9
211 2 10 29

~

2
0
22 21 20

(Sign)

Unsigned Fractional

126 25 241
22 21 20

123 22 21 ~ 14 13 121
Z-1O 2-11 2-12
2-1 2--2 ~

0
111 10 9 ~ 2
2-13 Z-14 2-15
2-22 2-23 2--24

Unsigned Integer

126 25 241
2 26 2 25 224

123 22 21 ~ 14 13 121
223 222 221
214 2 13 212

111 10 9
211 2 10 29

~

2
0
22 21 20

===================== Multiplier-Accumulators
4-46

06/29/95--LDS.10/2009-F

-__.......
--_- -............................
._----_-...-_
.........-------

LMA 1009/2009

DEVICES INCORPORATED

12 x 12-bit Multiplier-Accumulator

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

-55°C to +125°C

4.75 V

~

Vee

~

5.25 V

4.50 V

~

Vee

~

5.50 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., 10H = -2.0 mA

3.5

VoL

Output Low Voltage

Vee = Min., 10L = 8.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

Ground

~

VIN

loz

Output Leakage Current

Ground

~

VOUT ~ Vee (Note 12)

lee1

Vee Current, Dynamic

(Notes 5, 6)

lee2

Vee Current, Quiescent

(Note 7)

Symbol

~

..

Supply Voltage

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

±20

~

±20

~

25

mA

1.0

mA

Vee (Note 12)

12

=====================Multiplier-Accumulators
4-47

06/29/95-LDS.10/2009·F

---- -.......----.....-

..,..., .....-.-.---.
-~------

LMA1009/2009

~~----

-~---

DEVICES INCORPORATED

12 x 12-bit Multiplier-Accumulator

A11-0
B11-0

ClKA
ClKB

PREl

~

R26-0

~
-\

tpw

"

tD-

~

------..J

-

.'

tMC

-tPW--=:j

ClKR

%
J - - t s p - t-- tHP-

-----.J~

PRELOAD

-I--

tDIS

"k:.

--j

I=tENA--J
HIGH IMPEDANCE

.J~

OUTPUT

"includes OEX, OEM, OEl

===================== Multiplier-Accumulators
4-48

06/29/95-LDS.10/2009-F

LMA 1009/2009
DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this spec-

ification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

12 x 12-bit Multiplier-Accumulator

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDISABLE measurements, the load
current is increased to 10 rnA to reduce
the RC delay component of the
measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

a. A O.lIlF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated
b. Ground and Vee supply planes
by:
must be brought directly to the DUT
NCV2 F
socket or contactor fingers.

4

where
N
C
V
F

= total number of device outputs
= capacitive load per output
=

supply voltage

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

= clock frequency

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

=====================Multiplier-Accumulators
4-49

06/29/95-LDS.10/2009-F

LMA1009/2009
DEVICES INCORPORATED

12 x 12-bit Multiplier-Accumulator

68-pin

64-pin
~

A4 [ 1
A:il ~ 2
A2 ~ 3
A1 [ 4
Ao
5
ACC
6
SUB
7
8
RND
9
OEl
10
Ro
11
R1
R2 12
R,
13
R.
15
Rs
16
GND
R6
17
R7
18
RB
19
R.
20
21
R10
R11
22
ClKR
23
24
PREl
OEM
25
26
R12
27
R13
28
R14
29
R15
30
R16
31
R17
32
R1B

,.

64
63
62
61
60
59
58
57
56
55
54

53
52
51
50
49
48

~j
45

44~

43 ~
42 ]
41 ~
40 ~
39 ~
38 ]

37 ~
36 ~
35 ~
34 ~
33 ]

As
AB
A7
As
A.
A10
A11
ClKA
ClKB
Bo
B1
B2
B3

2

3
,~

A
B
C
D

B4
B5
Vee
B5

E

" '-'
'-'
NC RND
" '-'
" '-'
"
'-'
Ro OEl SUB
" '-'
"
'-'
R2
R1
"'-' '-'
"
R4
R3
" '-'
"
'-'
GND Rs
'-'
'-'
R7
R6
"
'-'
'-'
Re
R8
" '-'
"
'-'
R11
R10
"
'-'
'-'
PREl elK R
,.
" ~ "
'-'
NC OEM '-'
R13
" '-'
"
'-'
R'2 R14

"

,~

F

B7
Il8
BB
B10
B11
TC
OEX
R2B
R2S
R24
R2'
R22
R2'
R20
R,.

,~

G

H

K

,~

4

7

8

9

10

11

,~

" '-'
" '-'
" '-'
" '-'
" '-'
" '-'
'-'

ACC

A1

,~

A3

As

A7

AQ

,~

,~

,~

A11

" '-' '-' '-' C· '-'
" '-' '-'
'-'
A10 ClKA NC
Ao
A2
A4
AB
AB
" '-'
'-'
Bo ClKB
" '-'
"
'-'
B2
B1
"
"
Top View
'-'
'-'
B,
B4
Through Package
'-'
'-'
Vee B5
(Le., Component Side Pinout)
" '-'
'-'
B7
B5
" '-'
"
'-'
B.
BB
"
'-'
'-'
B11
, .. B10
" '-'
" '-'
" '-' '-'
" '-' '-' '-'
'-'
R,s R'7 R,. R2'
, .. , .. R23
, .. R2S OEX TC
"
" " '-' '-' '-' '-' '-'
'-'
R,. '-'
NC
R'B 1120 R22 1124 R20
,~

,~

,~

,~

,~

,~

,~

,~

,~

75 ns
55 ns
45 ns

LMA 1009DC75
LMA 1009DC55
LMA 1009DC45

LMA 1009GC75
LMA 1009GC55
LMA 1009GC45

95 ns
65 ns
55 ns

LMA 1009DM95
LMA 1009DM65
LMA 1009DM55

LMA1009GM95
LMA1009GM65
LMA1009GM55

95 ns
65 ns
55 ns

LMA1009DMB95
LMA1009DMB65
LMA1009DMB55

LMA 1009GMB95
LMA 1009GMB65
LMA 1009GMB55

===================== Multiplier-Accumulators
4-50

06/29/95-lDS.10/2009-F

-------==-==
- - -=
=
=......
----....--.-.
---

LMA1009/2009

DEVICES INCORPORATED

12 x 12-bit Multiplier-Accumulator
.........

LMA:2009 -ORDERING INFORMATION

.......

58-pin

'"
o~roromromm>z>mrommmmo
~ ~ m 00 ~ ~ E 0 E ~ v ~ N ~ 0 ~
10 9

OEX
R26

11

R25

12

R24

13

R23

14

R22

15

R21

16

R20

17

Ri9

18

8

7

6

5

4

2 i~j 68 67 66 65 64 63 62 610

A11
AlO

57
56

A9

53
52
51

Top
View

R1B

19

Ri7

20

50
49
48

R16

21

R15

22

R14

23

R13

24

R12

25

GEM

26

47
46
45

V ••

~~

•• M ••

Plastic J-Lead
Chip Carrier (J2)

75 ns
55 ns
45 ns

LMA2009JC75
LMA2009JC55
LMA2009JC45

~

•••

elK A

59
58

55
54

Speed

95 ns
65 ns
55 ns

3

44

~.a

A8
A7
A6
As
A4

•

A3
A2
A1
Ao
ACC
SUB
RND

GEL

Ceramic Leadless
Chip Carrier (K3)

. ..•. •. .

..: . «/

LMA2009KMB95
LMA2009KMB65
LMA2009KMB55

====================== Multiplier-Accumulators
4-51

06/29/95-LDS.10/2009-F

----------------- ------------...---.-.
-.

-~---

DEVICES INCORPORATED

Lu~~~

LMA 1010/2010

~

16 x 16-bit Multiplier-Accumulator

-~---

o 45 ns Multiply-Accumulate Time
o Replaces TRW TMC221O, Cypress
o
o

CY7C5l0, IDT 721OL, and AMD
Am29510
Two's Complement or Unsigned
Operands
Accumulator Performs Preload,
Accumulate, and Subtract

o Three-State Outputs
o
o
o

DESC SMD No. 5962-88733
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 64-pin Sidebraze, Hermetic DIP
• 68-pin Ceramic PGA
• 68-pin Plastic LCC, J-Lead
• 68-pin Ceramic LCC

The LMAI010 and LMA2010 are highspeed, low power l6-bit multiplieraccumulators. The LMAl010 and
LMA2010 are functionally identical;
they differ only in packaging. Full
military ambient temperature range
operation is achieved with advanced
CMOS technology.
The LMAl010 and LMA2010 produce
the 32-bit product of two l6-bit numbers. The results of a series of multiplications may be accumulated to form the
sum of products. Accumulation is
performed to 35-bit precision with the
multiplier product sign extended as
appropriate.
Data present at the A and B input
registers is latched on the rising edges

A15-0

ClKA-==+~==============~~~~~__J

of CLK A and CLK B respectively.
RND, TC, ACC, and SUB controls are
latched on the rising edge of the logical
OR of CLK A and CLK B. TC specifies
the input as two's complement
(TC HIGH) or unsigned magnitude
(TC LOW). RND, when HIGH, adds '1'
to the most significant bit position of
the least significant half of the product.
Subsequent truncation of the 16 least
•
significant bits produces a result
correctly rounded to 16-bit precision.
ACC and SUB control accumulator
operation. ACC HIGH results in
addition of the multiplier product and
the accumulator contents, with the
result stored in the accumulator register
on the rising edge of CLK R. ACC and
SUB HIGH results in subtraction of the
accumulator contents from the
multiplier product, with the result
stored in the accumulator register.
With ACC LOW, no accumulation
occurs and the next product is loaded
directly into the accumulator register.

ClK B-

RND-----+I
TC------.J
ACC-----+I
SUB-----+I

OEX
OEM
OEl
PREl

The LMAl010/2010 output register
(accumulator register) is divided into
three independently controlled sections.
The least significant result (LSR) and
most significant result (MSR) registers
are 16 bits in length. The extended
result register (XTR) is 3 bits long. The
output signals R15-D and input signals
B15-0 share the same bidirectional pins.
Each output register has an independent output enable control. In addition
to providing three-state control of the
output buffers, when OEX, OEM, or
OEL are HIGH and PREL is HIGH,
data can be pre10aded via the bidirectional output pins into the respective
output registers. Data present on the
output pins is latched on the rising
edge of CLK R. The interrelation of
PREL and the enable controls is summarized in Table 1.

=====================Multiplier-Accumulators
OS/29/95-lDS.1 0/201 0·1

~

LMA1010/2010
DEVICES INCORPORATED

16 x 16-bit Multiplier-Accumulator

L

L

L

L

OUT

OUT OUT

L

L

L

H

OUT

OUT

Z

L

L

H

L

OUT

Z

OUT

L

L

H

H

OUT

Z

z

L

H

L

L

Z

OUT OUT

L

H

L

H

Z

OUT

Z

L

H

H

L

Z

Z

OUT

L

H

H

H

Z

Z

z

H

L

L

L

Z

Z

Z

H

L

L

H

Z

Z

PREL
Z

H

L

H

L

Z

PREL

H

L

H

H

Z

PREL PREL

H

H

L

L

PREL

Z

Z

H

H

L

H

PREL

Z

PREL

H

H

H

L

PREL PREL

H

H

H

H

PREL PREL PREL

115 14 13~ 2 1 01
2-132-142-15
_20 2-1 2-2

115 14 13
_20 2-1 2-2

(Sign)

(Sign)

Integer Two's Complement (TC

115 14 13
_2 15 2 14 2 13

(Sign)

(Sign)

Unsigned Fractional (TC

115 14 13~ 2
o1
2-14~152 16
~1 2-22-3

115 14 13~ 2
o1
22 21 2°
2 15 214 2 13

MSR

2
~13

0 1
2-142-15

~ 2

0
22 21 2°

=0)

115 14 13
2-1 2-2 2-3

Unsigned Integer (TC

~

=1)

115 14 13~ 2
01
22 21 2°
_2 15 2 14 2 13

Z

PREL= Preload data to appropriate register
OUT = Register available on output pins
Z
= High impedance state

XTR

Fractional Two's Complement (TC = 1)

~ 2

1

0

~14~152-16

=0)

115 14 13
2 15 214 2 13

~ 2

0
22 21 2°

LSR

Fractional Two's Complement

134 33 321
_24 2 3 22

131 30 29 ~ 18 17 161
2-12 ~13 2-14
21 20 ~1

115 14 13~ 2 1 0 1
2-152-162-17
2-28~29~

(Sign)

Integer Two's Complement

134 33 321
_2 34 2 33 2 32

131 30 29 ~ 18 17 161
2 18 217 2 16
2 31 2 30 2 29

0
115 14 13~ 2
22 21 2°
2 15 214 2 13

(Sign)

Unsigned Fractional

134 33 321
22 21 2°

131 30 29 ~ 18 17 161
~142-152 16
~1 2-2 2-3

115 14 13~ 2 1 0
2-172-182-19
2-30 2-31 2-32

Unsigned Integer

134 33 321
2 34 2 33 2 32

131 30 29 ~ 18 17 161
2 18 217 2 16
2 31 230 2 29

0
115 14 13~ 2
22 21 2°
2 15 214 2 13

=====================Multiplier-Accumulators
4-54

06/29/95-LDS.1 01201 0-1

I.Dt;I~

LMA 1010/2010

-~---

DEVICES INCORPORATED

16 x 16-bit Multiplier-Accumulator

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C

Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

-55°C to +125°C

4.50 V ::; Vee::; 5.50 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., IOH = -2.0 mA

3.5

VoL

Output Low Voltage

Vee = Min., IOL = 8.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIx

Input Current

loz

Symbol

•

Supply Voltage
4.75 V ::; Vee::; 5.25 V

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground::; VIN::; Vee (Note 12)

±20

I1A

Output Leakage Current

Ground::; VOUT ::; Vee (Note 12)

±20

I1A

lee1

Vee Current, Dynamic

(Notes 5, 6)

25

mA

lee2

Vee Current, Quiescent

(Note 7)

1.0

mA

12

=====================Multiplier-Accumulators
4·55

06/29/95-LDS.1 0/201 0·1

-

_..--__-..---- ----- ----- - --~---

LMA1010/2010

DEVICES INCORPORATED

16 x 16-bit Multiplier-Accumulator

A15-o
815-0

ClKA
ClK8

r--- tpw--===t
~

ClKR

+

tMC

I
tpw

PREl

R34-0

-

I - t s p - j--IHPPRELOAD

-I--

lOIS

----l

~

tD-

-'k:
HIGH IMPEDANCE

I-="

lENA

---I
OUTPUT

'includes OEX, OEM, OEl

===================== Multiplier-Accumulators
4-56

06/29/95-LDS.1 0/201 0-1

- ------.--.---- --..-..-.-.-.
---..-.-_
.......----- -........
--

LMA 1010/2010

DEVICES INCORPORATED

I N01ES

16 x 16-bit Multiplier-Accumulator

o
0

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.

3. This device provides hard clamping

of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of --0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDIS test), and input levels of
nominany 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDISABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on I turn-off times.
As a result, care must be exercised in
the testing of this device. The fonowing
measures are recommended:

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at

the high temperature extreme, which is
the worst case for leakage current.

TRISTATE -==-_1!:¥~~~fi~_
OUTPUTS t
0.2 V

0.2V

a. A 0.1 ~F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be instaned between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated
b. Ground and Vee supply planes
by:
must be brought directly to the DUT
2F
NCV
--socket or contactor fingers.

4

where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with an outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with an inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case reS. These parameters are guaranteed
quirements of an parts. Responses from
but not 100% tested.
the internal circuitry are specified from

====================== Multiplier-Accumulators
4-57

06/29/95-LDSo 10/201 0-1

- -------- ----..---~------- --------

LMA 1010/2010

DEVICES INCORPORATED

16 x 16-bit Multiplier-Accumulator

54-pin

58-pin
A7
A8

As
A4
As

80, Ao
81, Al

89, A9
810, Ala
811, All

813, A13
814, A14
815, A15

R16
R17
R16
R19
R20
R21
R23

Speed

4

2
A11
A12
A13
A14
A1S
OEl
RND
SUB

A
B

C
D

ClKA
ClKB
Vee
TC
OEX
PREl
OEM
ClK R
R34
R33
RS2
R31
Rso
R29
R28
R27
R26
R2S
_ _ _ _ _ _..r R24

E

F
G
H

"

10

\~I

\~I

\~I

"

\~I

"

\~I

"

\~I

NC

BIRo

A1

As

As

A7

\~I

"

(:;"

\~I

"

\~I

\~I

B/R2 B/R1
,,-

Ao

A2

A4

C'
A6

(:;"

\~I

"

\~I

"

\~I

Ag

An

,-

A13

A8

A10

--

\~I

A12

A14

NC

\~I

"

\~I

B/R4 B/R3
,-

OEl
,-

A1S
,-

B/R6 B/Rs

SUB RND

""

\~I

\~I

"

\~I

\

I

"

\~I

\~I

\~I

,-

\~I

B/Rg B/R8
,,-

,-

"

\~I

"

\~I

ClKA ACC

"

,~ I

"

\~I

Vee ClK B

(i.e., Component Side Pinout)

,-

,-

\~I

\~I

\~I

B/Rl1

B/Al0

OEX

TC

\~I

\~I

'~I

\~I

,-

"

,-

\~I

"

\~I

NC

,-

,-

\~I

\_,
--

\~I

,-

"

\~I

"

\~I

,-

,-

\~I

\_,

--

R26
,-

R28
,-

R30
,-

R32
,-

R2S

R27

R29

R31

NC

\~I

,-

,-

R20
,-

R22

\~I

\~I

R17

R19

R21

R23

\~I

--

\~I

R24
,-

"

R18
,-

\~I

\~I

\~I

\~I

,-

\~I

R34 ClK R

\~I

\~I

R16
,\~I

\~I

OEM PREl

B/R1S B/R14

Sidebraze Hermetic DIP
(06)

'-'

,~ I

Top View
Through Package

\~ I

B/R13 B/A12

K

"

\~I

GND B/R7
,,\~I

"

11

,-

\~ I

R33

\~I

Ceramic Pin Grid Array
(G2)

LMA1010DC65
LMA1010DC55
LMA1010DC45

75 ns
65 ns
55 ns

LMA1010DM75
LMA1010DM65
LMA1010DM55

LMA1010GM75
LMA1010GM65
LMA 101 OGM55

75 ns
65 ns
55 ns

LMA 101 ODMB75
LMA 101 ODMB65
LMA 101 ODMB55

LMA 101 OGMB75
LMA1010GMB65
LMA1010GMB55

======================Multiplier-Accumulators
4-58

06/29/95-lDS.1 01201 0-1

-

- --.-.-.
- -------....--.
=-=-=:.==
L..ir
- ....... - - -

LMA1010/2010

DEVICES INCORPORATED

16 x 16-bit Multiplier-Accumulator

68-pin

0_

c:c:

~~~~~~~<~~~~~~~~~
A15

82, R2

59
68
57
56
55
54
53
52
51

B3, R3
B4, R4
B5, R5
B6, R6
B7, R7
GND
GND

20

50

Bl0, Rl0

21

49
48
47
46
45
44

B11,
B12,
B13,
B14,
B15,

11
12
13
14
15
16

Vee
Vee
Vee
Vee

17

R34

8

7

6

5

3

2

T
op

18
19

View

22

23
24
25
26

4

i~J

68 67 66 65 64 63 62 610

OEl
RND
SUB
ACC
ClKA
ClK B

TC
OEX
PREl
OEM
ClK R

65 ns
55 ns
45 ns

10 9

V~~~~~M34~~~5859.M~~

•

Ba, Ra
B9, R9
Rll
R12
R13
R14
R15

R1S

LMA2010JC65
LMA2010JC55
LMA2010JC45

75 ns
65 ns
55 ns

75 ns
65 ns
55 ns

LMA2010KMB75
LMA2010KMB65
LMA2010KMB55

===================== Multiplier-Accumulators
4-59

OS/29/95-lDS.l 01201 0-1

DEVICES INCORPORATED

------

=--u:..:=~

LM s 12

~

12-bit Cascadable Multiplier-Summer

~.....--.

-.---.

-~---

L-IF_E_AT_U_R_ES_·_ _ _ _

--'1 IDESCRIPTION

o 12 x 12-bit Multiplier with
o

o

Pipelined 26-bit Output Summer
Summer has 26-bit Input Port Fully
Independent from Multiplier
Inputs
Cascadable to Form Video Rate FIR
Filter with 3-bit Headroom

o A, B, and C Input Registers Sepao
o
o
o

rately Enabled for Maximum
Flexibility
25 MHz Data Rate for FIR Filtering
Applications
High Speed, Low Power CMOS
Technology
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 84-pin Plastic LCe, J-Lead
• 84-pin Ceramic PGA

The LMS12 is a high-speed 12 x 12-bit
combinatorial multiplier integrated
with a 26-bit adder in a single 84-pin
package. It is an ideal building block
for the implementation of very highspeed FIR filters for video, RADAR,
and other similar applications. The
LMS12 implements the general form
(A.B) + C. As a result, it is also useful
in implementing polynomial approximations to transcendental functions.
ARCHITECTURE
A block diagram of the LMS12 is
shown below. Its major features are
discussed individually in the following paragraphs.
MULTIPLIER
The All-O and Bll-O inputs to the
LMS12 are captured at the rising edge
of the clock in the 12-bit A and B input
registers, respectively. These registers
are independently enabled by the

Al1-0

B11-0

12

QC~~~~r--------------ENB
CLK _ _

a:

FTS

LU
f-

!!2

C25-0

26

C!)

LU

825-0

a:
u

ENA and ENB inputs. The registered
input data are then applied to a
12 x 12-bit multiplier array, which
produces a 24-bit result. Both the
inputs and outputs of the multiplier
are in two's complement format. The
multiplication result forms the input
to the 24-bit product register.
SUMMER
The C25-0 inputs to the LMS12 form a
26-bit two's complement number
which is captured in the C register at
the rising edge of the clock. The C
register is enabled by assertion of the
ENC input. The summer is a 26-bit
adder which operates on the C
register data and the sign extended
contents of the product register to
produce a 26-bit sum. This sum is
applied to the 26-bit S register.
OUTPUT MULTIPLEXER
The FTS input controls a multiplexer
which selects the data to be output on
the S25-0 lines. When FTS is asserted,
the summer result is applied directly
to the S output port. When FTS is
deasserted, the multiplexer selects the
S register for output on the Sport,
effecting a one-cycle delay of the
summer result. The S output port can
be forced to a high-impedance state by
driving the OE control line high. FTS
would be asserted for conventional
FIR filter applications, however the
insertion of zero-coefficient filter taps
may be accomplished by negating
FTS. Negating FTS also allows
application of the same filter transfer
function to two interleaved datastreams with successive input and
output sample points occurring on
alternate clock cycles.

OE

ENC

=======================Multiplier-Summers
4-61

06/29/95-LDS.S12-E

•

- -- --------------- ---

LMS12

-~---

DEVICES INCORPORATED

12-bit Cascadable Multiplier-Summer

x(n) --~----'-------'----r---~

h4

Yin)

x(n) -------,--------r-------~-------_,-------,

yin)

APPLICATIONS

The LMS12 is designed specifically for
high-speed FIR filtering applications
requiring a throughput rate of one
output sample per clock period. By
cascading LMS12 units, the transpose
form of the FIR transfer function is
implemented directly, with each of the
LMS12 units supplying one of the
filter weights, and the cascaded
summers accumulating the results.
The signal flow graph for a 5-tap FIR
filter and the equivalent implementation using LMS12's is shown in
Figure 1.

The operation of the 5-tap FIR filter
implementation of Figure 1 is depicted
in Table 1. The filter weights h4 - ho
are assumed to be latched in the B
input registers of the LMS12 units.
The x(n) data is applied in parallel to
the A input registers of all devices.
For descriptive purposes in the table,
the A register contents and sum
output data of each device is labelled

according to the index of the weight
applied by that device; i.e., So is
produced by the rightmost device,
which has ho as its filter weight and
Ao as its input register contents. Each
column represents one clock cycle,
with the data passing a particular
point in the system illustrated across
each row.

======================= Multiplier-Summers
4-62

06/29/95-LDS.S12-E

LMS12
DEVICES INCORPORATED

A4 Register

12-bit Cascadable Multiplier-Summer

Xn

Xn+1
h4Xn

Xn+2
h4Xn+1

Xn+3
h4Xn+2

Xn+4
h4Xn+3

Xn+5
h4Xn+4

Xn+6
h4Xn+5

Xn+7
h4Xn+6

Xn

Xn+1
h3Xn
+h4Xn-1

Xn+2
h3Xn+1
+h4Xn

Xn+3
h3Xn+2
+h4Xn+1

Xn+4
h3Xn+3
+h4Xn+2

Xn+5
h3Xn+4
+h4Xn+3

Xn+6
h3Xn+5
+h4Xn+4

Xn+7
h3Xn+6
+h4Xn+5

Xn

Xn+1
h2Xn
+ h3Xn-1
+h4Xn-2

Xn+2
h2Xn+1
+h3Xn
+h4Xn-1

Xn+3
h2Xn+2
+h3Xn+1
+h4Xn

Xn+4
h2Xn+3
+h3Xn+2
+h4Xn+1

Xn+5
h2Xn+4
+h3Xn+3
+h4Xn+2

Xn+6
h2Xn+5
+h3Xn+4
+h4Xn+3

Xn+7
h2Xn+6
+h3Xn+5
+h4Xn+4

Xn

Xn+1
h1Xn
+h2Xn-1
+h3Xn-2
+h4Xn-3

Xn+2
h1Xn+1
+h2Xn
+h3Xn-1
+h4Xn-2

Xn+3
h1Xn+2
+h2Xn+1
+h3Xn
+h4Xn-1

Xn+4
h1Xn+3
+h2Xn+2
+h3Xn+1
+h4Xn

Xn+5
h1Xn+4
+ h2Xn+3
+h3Xn+2
+h4Xn+1

Xn+6
h1Xn+5
+h2Xn+4
+h3Xn+3
+ h4Xn+2

Xn+7
h1Xn+6
+h2Xn+5
+h3Xn+4
+h4Xn+3

Xn

Xn+1
hoXn
+h1Xn-1
+h2Xn-2
+h3Xn-3
+h4Xn-4

Xn+2
hOXn+1
+h1Xn
+h2Xn-1
+h3Xn-2
+h4Xn-3

Xn+3
hOXn+2
+h1Xn+1
+h2Xn
+h3Xn-1
+h4Xn-2

Xn+4
hOXn+3
+h1Xn+2
+h2Xn+1
+h3Xn
+h4Xn-1

Xn+5
hOXn+4
+h1Xn+3
+h2Xn+2
+h3Xn+1
+h4Xn

Xn+6
hOXn+5
+h1Xn+4
+h2Xn+3
+h3Xn+2
+h4Xn+1

Xn+7
hOXn+6
+h1Xn+5
+h2Xn+4
+h3Xn+3
+h4Xn+2

Sum4
A3 Register

Sum3
A2 Register

Sum2

A1 Register

Sum 1

Ao Register

SumO

AIN

BIN

- - - - - - - - - Fractional Two's Complement - - - - - - - 1111091!)t2
01
_20 2-1 z-2
Z-9 Z-1O 2 11

1111091!)t2
0
_20 2 1 Z-2
2-9 Z-1O 2 11

(Sign)

(Sign)

Integer Two's Complement
111 10 9
_2 11 210 29

~

2
01
22 21 2°

111 10 9
_2 11 210 29

(Sign)

~

2
0
22 21 2°

(Sign)

- - - - - - - - - Fractional Two's Complement - - - - - - - - 125 241
_2 3 22

123 22 21

I!)t

14 13 121

111 10 9

I!)t

2

0

(Sign)

- - - - - - - - - Integer Two's Complement - - - - - - - - 125 241

123 22 21

I!)t

14 13 12

I

111 10 9

I!)t

2

0

_225 22'
(Sign)

=======================Multiplier-Summers
4-63

06/29/95-LDS.S12-E

•

---- -- -----.-..-..-.---

~---.-...
~
-~--~-

LMS12

-~---

DEVICES INCORPORATED

12-bit Cascadable Multiplier-Summer

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

-55°C to + 125°C

Supply Voltage
4.75 V:O;; Vee:o;; 5.25 V
4.50 V

:0;;

Vee

:0;;

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., IOH = -2.0 mA

3.5

VoL

Output Low Voltage

Vee = Min., IOL = 4.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Symbol

5.50 V

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground:O;; VIN:O;; Vee (Note 12)

±20

~

Output Leakage Current

Ground:o;; VOUT:O;; Vee (Note 12)

±20

~

leel

Vee Current, Dynamic

(Notes 5,6)

25

mA

lee2

Vee Current, Quiescent

(Note?)

1.0

mA

15

======================= Multiplier-Summers
4·64

06/29/95-LD8.S 12·E

-----_
........-....... -......-.
--- -..- -----...--.~-

LMS12

~.....-.

-~---

DEVICES INCORPORATED

12-bit Cascadable Multiplier-Summer

INPUTS
A,B,C

)
tSAB
tse

tHAB
tHe

IE

I(
tSEN

tpw

tHEN

CLOCK
tpw

f

SOUTPUTS
to

ROUTPUTS

~

__:l
__ ~----~H~IG~H~IM~p=~~~~e~E_tE_N_A~

___________________
tO_IS_

__ } - - - - - - - - - - - - - - - - - - - - - - -

=======================Multiplier-Summers
4-65

06/29/95-LOS.S12-E

----- --- -----..---

...-. ...-.-...-.
-~--~.-...-..-.

LMS12

-~---

DEVICES INCORPORATED

12-bit Cascadable Multiplier-Summer

INPUTS

A,B,C

tSAB
tsc

tHAB
tHC

;~

)1(
tsEN

tpw

tHEN

CLOCK

1-

tpw
SOUTPUTS

to

ROUTPUTS

~

_=:1
___ ~----~H~IG~H~IM~P=~~A~NC~E_tE_N_A_~_~

___________________
tO_IS_

f
_______________________

======================= Multiplier-Summers
4-66

06/29/95-LDS.S12-E

- -- -----------~-------- - --

LMS12

DEVICES INCORPORATED

12-bit Cascadable Multiplier-Summer

INOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3; This device provides hard clamping

of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDiS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDISABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
t-F_IG_U_R_E_3,:"",_T-:-H_R_ES_H_O_L_D_L_E-:-V_E_LS--I . .
tOIS

tENA

6~~~~~~ ----=.I>'t~-""':=.=='i'~-02V

a. A 0.1 !IF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated b. Ground and Vee supply planes
by:
must be brought directly to the DUT
socket or contactor fingers.
where
N
C
V
F

=
=
=
=

total number of device outputs
capacitive load per output
supply voltage
clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

=======================Multiplier-Summers
4·67

06/29/95-LDS.S12·E

- -------- ------.
--~------- ---------

-

LMS12

DEVICES INCORPORATED

12-bit Cascadable Multiplier-Summer

84-pin

B2

11 10 9 8 7 6 5 4 3 2 1 84838281 80797877 76 75
12
•
74

B3
B4

GND
C5
C6

ClK

C7
C8

B5
B6
B7
B8
B9

C9

ClO

Cll
C'2

Top
View

B10
B11

ENB

C'3
C14
C15

C16
C17
C18

S25
S24

S23
S22

C19

S21

C20

S20

C21

OE

C22

FTS
~

C23

M

~

~

~~~~~W~~~G~M~~Q~~W~~~

Plastic J-Lead Chip Carrier
(J3)
65 ns
50 ns
40 ns

LMS12JC65
LMS12JC50
LMS12JC40

======================= Multiplier-Summers
4-68

06/29/95-LDS.S12-E

=

..............

_-

,,~=~
=-~::..===--r
-~--DEVICES INCORPORATED

LMS12
12-bit Cascadable Multiplier-Summer

84-pin
2
A
6
C

,_I

T , ..

"

I

3
I

61

ENA

I_I

"

I_I

64

62

"

I_I

ClK

"

"

4

5

6

7

8

"

I_I

"

I_I

"

I_I

"

I_I

"

I_I

I_I

"

I_I

,.
,_I

A9

A6

As

A2

ENC

C1

C2

GND

I_I

"

I_I

"

I_I

"

I_I

"

I_I

"

I_I

"

I_I

"

I_I

60

A10

A7

A3

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C24 C22
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,_I
" " " " " " " " " ,_I

Vee

65 ns
50 ns
40 ns

LMS12GC65
LMS12GC50
LMS12GC40

65 ns
50 ns

LMS12GM65
LMS12GM50

65 ns
50 ns

LMS12GMB65
LMS12GMB50

C25

=======================Multiplier-Summers
4-69

06/29/95-LDS.S12-E

DEVICES INCORPORATED

--

- .--.
- .--.------------- -.......------ DEVICES INCORPORATED

Register Products

•

---- -........-- -----..--_--------..-.
---

DEVICES INCORPORATED

Register Products

REGISTER PRODUCTS ........................................................................................................................................................ 5-1
Pipeline Registers
L29C520
4 x S-bit Multilevel Pipeline Register (1-4 Stages) ........................................................................................... 5-3
L29C521
4 x S-bit Multilevel Pipeline Register (1-4 Stages) ........................................................................................... 5-3
LPR520
4 x 16-bit Multilevel Pipeline Register (1-4 Stages) ....................................................................................... 5-11
LPR521
4 x 16-bit Multilevel Pipeline Register (1-4 Stages) ....................................................................................... 5-11
LPR200
S x 16-bit Multilevel Pipeline Register (1-S Stages) ....................................................................................... 5-17
LPR201
7 x 16-bit Multilevel Pipeline Register (1-7 Stages) ....................................................................................... 5-17
16 x S-bit DualS-Deep Pipeline Register (1-16 Stages) ................................................................................. 5-27
L29C525
LlOCll
4/S-bit Variable Length Shift Register (3-1S Stages) ..................................................................................... 5-35
L21 C11
S-bit Variable Length Shift Register (1-16 Stages) ......................................................................................... 5-41

s~2~~~1~egis~~:t Serial Scan Shadow Register ................................................................................................................... 5-47 •

5·1

-= ...... __ ..
~

.:.:~
-

~--==-==1L...iir

-~---

DEVICES INCORPORATED

~EEC;~G

L29C520/521

~

4 x a-bit Multilevel Pipeline Register

-~---

[J
[J

[J
[J
[J
[J
[J
[J
[J
[J

Four 8-bit Registers
Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline
Register
Hold, Shift, and Load Instructions
Separate Data In and Data Out Pins
High-Speed, Low Power CMOS
Technology
Three-State Outputs
DESC SMD No. 5962-91762
Available 100% Screened to
MIL-STD-883, Class B
Replaces IDT29FCT520 /IDT29FCT521
and AMD Am29520/ Am29521
Package Styles Available:
• 24-pin Plastic DIP
• 24-pin Ceramic DIP
• 28-pin Plastic LCC, J-Lead
• 28-pin Ceramic LCC
• 24-pin Ceramic Flatpack
• 24-pin Plastic SSOP

The L29C520 and L29C521 are pinfor-pin compatible with the
IDT29FCT520 /IDT29FCT521 and
AMD Am29520/ Am29521, implemented in low power CMOS.
The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.
The Instruction pins,lI-o, control the
loading of the registers. For either
device, the registers may be configured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, 11-0
may be set to prevent any register
from changing.

The 51-0 select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.

/---t--t---------I.

08-0

REG 1
REG 2
REG3
REG 4

Y7-O

6E
81-0

2

11-0

--1----

CLK--

======================= Pipeline Registers
5-3

06123195-LDS.52011·L

-----.--.....------- --------...----.-..
-~---

-

L29C520/521

DEVICES INCORPORATED

4 x a-bit Multilevel Pipeline Register

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

Symbol

-55°C to +125°C

Supply Voltage
4.75 V:::; Vee:::; 5.25 V
4.50 V :::; Vee:::; 5.50 V

Parameter

Test Condition

Min

VOH

Output High Voltage

Vee = Min., IOH =-15.0 mA

2.4

VOL

Output Low Voltage

Vee = Min., IOL = 24.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground:::; VIN:::; Vee (Note 12)

±20

!lA

Output Leakage Current

Ground:::; VOUT:::; Vee (Note 12)

±20

!lA

leel

Vee Current, Dynamic

(Notes 5, 6)

30

mA

lee2

Vee Current, Quiescent

(Note 7)

1.5

mA

======================= Pipeline Registers
5-4

OS/23/95-LDS.520/1-L

- --- -------------~---

-

L29C520/521

DEVICES INCORPORATED

4 x a-bit Multilevel Pipeline Register

COMMI:RCjAL.QJ>tR1.fINGRANGI!!(O"CtO+7'O~)·. Ndt~~9,1{)l(l$}· . . . . . . . . . .........

)

..

:

.iif.•.·•.•·.>.·.···
L29C520/521-

22
Symbol

Parameter

Min

14
Max

Min

Max

tpo

Clock to Output Delay

22

14

tSEL

Select to Output Delay

20

13

tpw

Clock Pulse Width

10

7

tSI

Instruction Setup Time

10

5

3
10

5

1

tHI

Instruction Hold Time

tso

Data Setup Time

tHO

Data Hold Time

tENA

Three-State Output Enable Delay (Note 11)

21

15

tOIS

Three-State Output Disable Delay (Note 11)

15

12

3

1

}Mi.~tf:~~~.·QP~·:
L29C520/521-

24

30
Symbol
tpo

Parameter

Min

Max

Min

30

Clock to Output Delay

16
Max

Min

24

30

Max

16

22

15

tSEL

Select to Output Delay

tpw

Clock Pulse Width

15

10

8

tSI

Instruction Setup Time

15

10

6

tHI

Instruction Hold Time

5

3

2

tso

Data Setup Time

15

10

6

tHO

Data Hold Time

5

3

2

tENA

Three-State Output Enable Delay (Note 11)

25

22

16

tOIS

Three-State Output Disable Delay (Note 11)

20

16

13

11-0
lSI
D7-0

IHI

)
---Iso

IHO
Ipw

81-0

Ipw

{

ClK

f

J

~

X

f--Ipo
I-----ISEL----}-j

------+--~

FIOIS3

L-IENA=t
HIGH

IMPEDANC~

Y7-0

======================= Pipeline Registers
5-5

06/23/95-LDS.520/1-L

--

---- --- ...
.__- -.. .-.........---------~
- - --

L29C520/521

DEVICES INCORPORATED

4 x 8-bit Multilevel Pipeline Register

1. Maximum Ratings indicate stress 9. AC specifications are tested with
specifications only. Functional oper- input transition times less than 3 ns,
ation of these products at values be- output reference levels of 1.5 V (except
yond those indicated in the Operating tENA/tDIS test), and input levels of
Conditions table is not implied. Expo- nominally 0 to 3.0 V. Output loading
sure to maximum rating conditions for may be a resistive divider which
extended periods may affect reliability. provides for specified IOH and IOL at an
output voltage of VOH min and VOL
2. The products described by this spec- max respectively. Alternatively, a
ification include internal circuitry de- diode bridge with upper and lower
signed to protect the chip from damag- current sources of IOH and IOL
ing substrate injection currents and ac- respectively, and a balancing voltage of
cumulations of static charge. Never- 1.5 V may be used.
Parasitic
theless, conventional precautions capacitance is 30 pF minimum, and
should be observed during storage, may be distributed. For tENABLE and
handling, and use of these circuits in tDISABLE measurements, the load
order to avoid exposure to excessive current is increased to 10 rnA to reduce
electrical stress values.
the RC delay component of the
3. This device provides hard clamping measurement.
of transient undershoot and overshoot. This device has high-speed outputs caInput levels below ground or above Vee pable of large instantaneous current
will be clamped beginning at -0.6 V and pulses and fast turn-on/ turn-off times.
Vee + 0.6 V. The device can withstand As a result, care must be exercised in
indefinite operation with inputs in the the testing of this device. The following
range of -0.5 V to +7.0 V. Device opera- measures are recommended:
tion will not be adversely affected, however, input current levels will be well in a. A 0.1 IlF ceramic capacitor should be
excess of 100 mA.
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated b. Ground and Vee supply planes
by:
must be brought directly to the DUT
NCV 2 F
socket or contactor fingers.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 m V
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

4

where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
S. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

======================== Pipeline Registers
5·6

06/23/95-LDS.520/1·L

------------ ---- --------

L29C520/521

---...-~
--.-.-

DEVICES INCORPORATED

24-pin -

4

0.3" wide

X

8-bit Multilevel Pipeline Register

28-pin

10

Vee

11

80

Do

81

D1

Yo

D2

Y1

D3

Y2

D4

Y3

D5

Y4

D6

Y5

D7

Y6

ClK

Y7

GND

OE

()

u

0

()

0

,...

ZQ.!:.!2>UlUl

4
D1

5

D2

6

D3

7

D4

8

D5

9

D6
NC

3

2 :1: 28 27 26
:_,
25

NC

24

Yo

23

Y1

22

Y2

21

Y3

10

20

Y4

11

19
12 13 14 15 16 17 18

Y5

Top
View

•

b ~ ~ Ii!:! >= );'. ~
0C!l

Plastic DIP
Speed

22 ns
14 ns

L29C520PC22
L29C520PC14

30 ns
24 ns
16 ns

L29C520CM30
L29C520CM24
L29C520CM16

L29C520KM30
L29C520KM24
L29C520KM16

30 ns
24 ns
16 ns

L29C520CMB30
L29C520CMB24
L29C520CMB16

L29C520KMB30
L29C520KMB24
L29C520KMB16

======================= Pipeline Registers
5-7

06/23/95-LDS.520/1-L

---------- - ----.-

_ ---.--~
_ -...-_-..r
-

L29C520/521

-~---

DEVICES INCORPORATED

4 x 8-bit Multilevel Pipeline Register

24-pin -

24-pin

c::::::<,
c::::::<,
c::::::<,
c::::::<,
c::::::<,
c::::::<,
c::::::<,
c::::::<,
c::::::<,
c::::::<,
ClK c::::::<,
GND c::::::<,
10
11
Do
D1
D2
D3
D4
D5
D6
D7

1-

2
3
4
5
6
7
8
9
10
11
12

21

'>==
'>==
'>==
'>==
'>==
'>==
'>==
'>==
'>==
'>==
'>==
'>==

0.209" wide

10
11
Do
D1
D2
D3
D4
D5
D6
D7

Vee

So
S1
Yo
Y1
Y2
Y3
Y4
Y5
Y6
Y7

ClK

OE

GND

Vee

23
22
21
20
19
18
17
10 15
11 14
12 13

So
S1
Yo
Y,
Y2
Y3
Y4
Y5
Y6
Y7
OE

Plastic SSOP
(S1)

Ceramic Flatpack
(M1)
22 ns
14 ns

30 ns
24 ns
16 ns

L29C520MMB30
L29C520MMB24
L29C520MMB16

======================= Pipeline Registers
5·8

06/23/95-LDS.520/1-L

L29C520/521
DEVICES INCORPORATED

24-pin -

22 ns

4 x 8-bit Multilevel Pipeline Register

0.3" wide

28-pin

10

Vce

11

So

00

81

01

Yo

02

Y1

03

Y2

04

Y3

Os

Y4

06

Y5

07

Ya

ClK
GNO

Y7

L29C521 PC22

<..l
00

Uo

....

ZCl.::::.!2>UlUl

01

5

02

6

03

7

04

8

05

9

06

10

NC

11

4

3

2 :1: 28 27 26
:_,
25
24

NC
Yo

23

Y1

22

Y2

21

Y3

20

Y4

19
12 13 14 15 16 17 18

Y5

Top
View

•

Ci~~I~>=~~

OE

UC)

L29C521 CC22

L29C521 JC22

L29C521 KC22

30 ns
24 ns

L29C521CM30
L29C521CM24

l29C521 KM30
L29C521 KM24

30 ns
24 ns

l29C521CMB30
L29C521 CMB24

L29C521 KMB30
L29C521 KMB24

=======================Pipeline Registers
5-9

06/23/9S-LDS.520/1-L

- -- -----.-.-.......---..-..-----_
.......
- -----~~-

L29C520/521

--.....-.

DEVICES INCORPORATED

4 x 8-bit Multilevel Pipeline Register

24-pin

lo~
11~
Do~
D1~
D2~
D3~
D4~
Ds~
D6~

D7~
~
GND~

elK

30 ns
24 ns

8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

}::=I Vee
}::=I 80
}::=I 81
}::=I Yo
}::=I Y1
}::=I Y2
}::=I Y3
}::=I Y4
}::=I Ys
}::=I Y6
}::=I Y7
}::=I OE

L29C521 MMB30
L29C521 MMB24

======================= Pipeline Registers
5-10

06/23/9S-LDS.S20/1-L

Lu~~~
---

-~

UrVICE:S INC(JHPUHAIU)

o
o

o
o
o
o
o

o
o

Four 16-bit Registers
Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline
Register
Hold, Shift, and Load Instructions
Separate Data In and Data Out Pins
High-Speed, Low Power CMOS
Technology
Three-State Outputs
DESC SMD No. 5962-89716
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 40-pin Plastic DIP
• 40-pin Ceramic DIP
• 44-pin Plastic LCC, J-Lead
• 44-pin Ceramic LCC

LPR520/521
4

X

16-bit Multilevel Pipeline Register

The LPR520 and LPR521 are functionally
compatible with the IDT29FCT520 /
IDT29FCT521 and AMD Am29520/
Am29521 but have 16-bit inputs and
outputs. They are implemented in low
power CMOS.
The LPR520 and LPR521 contain four
registers which can be configured as
two independent, 2-level pipelines or
as one 4-level pipeline.
The Instruction pins, 11-0, control the
loading of the registers. For either
device, the registers may be configured as a four-stage delay line, with
data loaded into Rl and shifted
sequentially through R2, R3, and R4.
Also, for the LPR520, data may be
loaded from the inputs into either Rl
or R3 with only R2 or R4 shifting. The
LPR521 differs from the LPR520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, 11-0
may be set to prevent any register
from changing.

015·0

REG 1
REG 2
REG 3

Y1S·0

REG 4

The Sl-0 select lines control a 4-to-l
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.

t,(~1.~1.......

. .•••.•.

......

.. . . .

LPf'~~OIN!STRUC1'tON l'.(BLE
h

10

L

L

Description
D-+R1

R1-+R2

R2-+R3

R3-+R4

L

H

HOLD

HOLD

D-+R3

R3-+R4

R1-+R2

HOLD

HOLD

H

L

D-+R1

H

H

ALL REGISTERS ON HOLD

h

10

Description

L

L

D-+R1

R1-+R2

R2-+R3

R3-+R4

L

H

HOLD

HOLD

D-+R3

HOLD

H

L

D-+R1

HOLD

HOLD

HOLD

H

H

ALL REGISTERS ON HOLD

SI So

Register Selected

L

L

Register 4

L

H

Register 3

H

L

Register 2

H

H

Register 1

DE
81-0

2

11-0 - - ; - - .
CLK~

======================= Pipeline Registers
5-11

06i30i9S-LDS. PS20il-K

•

-...---------

-......------~=-==-===----

LPR520/521

DEVICES INCORPORATED

4 x 16-bit Multilevel Pipeline Register

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 rnA
Latchup current ................................................................................................................................ > 400 rnA

Mode

Temperature Range (Ambient)

Active Operation, Commercial
Active Operation, Military

Symbol

Supply Voltage

O°C to +70°C

4.75 V::; Vee::; 5.25 V

-55°C to + 125°C

4.50 V ::; Vee::; 5.50 V

Parameter

Test Condition

VOH

Output High Voltage

Vee

= Min., 10H =-2.0 rnA

VOL

Output Low Voltage

Vee

=Min., 10L =8.0 rnA

ViH

Input High Voltage

ViL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Min

Typ

Max

2.4

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground::; VIN ::; Vee (Note 12)

±20

JlA

Output Leakage Current

Ground::; VOUT::; Vee (Note 12)

±20

JlA

lee1

Vee Current, Dynamic

(Notes 5,6)

40

rnA

lee2

Vee Current, Quiescent

(Note 7)

1.0

rnA

10

========================Pipeline Registers
5-12

06i30i95-LDS.P520il-K

_...... --- - -----

..............
....--..---~-~--~--.-..-.
_-...

LPR520/521

-~---

DEVICES INCORPORATED

4 x 16-bit Multilevel Pipeline Register

11-0
lSI

IHI

015-0

-tso

IHO

r

CLK

Ipw

{

;f

Ipw
51-0

x.

*.

I

I--Ipo

1-----IsEl----}--I

v:: --------------]-+-Llols3

LIENA=t

HIGH IMPEOANC~

======================= Pipeline Registers
5-13

OS/30/95-LDS. P520/1-K

E

~

_-

--~

.....

==~E==
--....

LPR520/521

-~---

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

4 x 16-bit Multilevel Pipeline Register

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tors test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tmsABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

This device has high-speed outputs capable of large instantaneous current
pulses and fast tum-on/tum-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

a. A 0.1 J.1F ceramic capacitor should be
installed between vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (OUT) as possible. Similar capacitors
from those designated but operation is should be installed between device vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated b. Ground and Vee supply planes
by:
must be brought directly to the OUT
NCV2 F
socket or contactor fingers.

4

where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required OUT
input levels relative to the OUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum· or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

=======================Pipeline Registers
5·14

06/30/95-LDS.P520/1·K

-

..-...

..-...--

L.D!if£!
-~---

LPR520/521

DEVICES INCORPORATED

4 X 16-bit Multilevel Pipeline Register

44-pin

40-pin - 0.6" wide

25 n5
22 ns
15 ns

30 ns
24 ns
18 ns

10

Vee

11

50

Do

51

D1

Vo

D2

V1

D3

V2

D.

V3

D5

V.

D6

V5

D7

Vo

D8

V7

D9

V8

D10

V9

D11

V10

D12

V11

D13

V12

D14

V1S

D15

V14

elK

V15

GND

OE

U ~ _ 0
8 0 _ 0
ZClClCl.::::::.!2>cnm»
6

D3

5

4

3

_

2 :1: 44 43 42 41 40
:_,

D.

39

NC

38

V2

D5

9

37

V3

D6

10

36

V.

D7

11

35

V5

D8

12

34

V6

D9

13

33

V7

D10

14

32

V8

D11

15

31

V9

16

30

V10

(17 '8 192021 22232425 26 27 269

V11

D12
NC

Top

View

--~

~

~

~

Cllw

~

~

~

N

U

CiCiCidi§O>=>=>=>=Z

LPR520JC25
LPR520JC22
LPR520JC15

LPR520PC25
LPR520PC22
LPR520PC15

LPR520KMB30
LPR520KMB24
LPR520KMB18

LPR520CMB30
LPR520CMB24
LPR520CMB18

======================= Pipeline Registers
5-15

06/30/95-LDS. P52011-K

•

LPR520/521
DEVICES INCORPORATED

4 x 16-bit Multilevel Pipeline Register

44-pin

40-pin - 0.6" wide

10
11

Do
01

D2
03
D.
05
07
08
09
010
011
012
013
0,.
015
ClK
GNO

25 ns
22 ns
15 ns

30 ns
24 ns
18 ns

Vee

So

~8c8.:::£ga3c1)~>=

Sl
Yo
Yl
Y2
Y3
Y.
Y5
Y6
Y7
Y8
Y9
Yl0
Y11
Y,2

03

0.
05
06
07
08
09
010
011
012
NC

Y13
Y,.

7
8
9
10
11
12
13

6 5

•3

38

37
36
35

Top

3.
33

View

,.

15
16
17

2 :1: 44 43 42 41 40
L!
39

32

31
30
29
18 19 20 21 22 23 2. 25 26 27 28
~

~

~

~

CIW

~

~

~

NC
Y2
Y3
Y.
Y5
Ye
Y7
Y8
Y9
Yl0
Y11

NO

oood15°»»Z

Y15

5E

LPR521JC25
LPR521JC22
LPR521JC15

LPR521PC25
LPR521PC22
LPR521PC15

LPR521 KMB30
LPR521 KMB24
LPR521KMB18

LPR521CMB30
LPR521CMB24
LPR521CMB18

=======================Pipeline Registers
5-16

06/30/95-LDS.P52011-K

Lu~~~

-~---

~

o

Pipeline Registers Eight I6-bit High-Speed (LPR200) or
Seven I6-bit High-Speed with a
Direct Feed-Through Path (LPR201)
o Programmable Multilevel Register
Configurations
o Access time of 10 ns
o Hold, Shift, and Load Instructions
o Replaces IDT73200 and IDT73201
o Available 100% Screened to
MIL-STD-883, Class B
o Package Styles Available:
• 48-pin Plastic DIP
• 48-pin Sidebraze, Hermetic DIP
• 52-pin Plastic LCC, J-Lead
• 52-pin Ceramic LCC

LPR200/201
16-bit Multilevel Pipeline Register

The LPR200 and LPR201 are programmable multilevel pipeline registers.
Both devices are pin-for-pin compatible with the IDT73200 and IDT73201.
The LPR200 contains eight I6-bit
high-speed pipeline registers which
can be configured as eight independent, I-level pipelines; four independent, 2-level pipelines; two
independent, 4-level pipelines; or as
one 8-level pipeline.

and shifted sequentially through B, C,
D, E, F, and G (and H in the case of the
LPR200) as shown in Table 1. The
Instruction pins may also be set to
prevent any register from changing.
The Select lines, S2-0, control an 8-to-I
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allow simultaneous write and
read operations on different registers.

•

The LPR20I contains seven I6-bit
high-speed pipeline registers which
can be configured as seven independent, I-level pipelines; three independent, 2-level plus one I-level pipelines; one 4-level plus one 3-level
pipeline; or as one 7-level pipeline.
The Instruction pins, 13-0, control the
loading of the registers. The registers
can be configured as a seven-stage
delay line (eight-stage in the case of
the LPR200) with data loaded into A

A REG
BREG
CREG
DREG
EREG
FREG

Y15-o

OE

GREG
(!l

w
w

II:

SE12·o

13-0---+CLK_

'Appliesto
LPR200 only

CEN_

tApplies to
LPR2010nly

=======================Pipeline Registers
5-17

OS/30/95-LDS.P200/1·C

--.....
-=- -- -----

~="!!!=:"'f!!.

-........-.

LPR200/201

_-...-.
-

-~---

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

SIGNAL DEFINITIONS
Power

Single 8-Level (LPR200)
Single 7-Level (LPR201)

Two 4-Level (LPR200)
One 4 Level, One 3-Level (LPR201)

VccandGND
+5 V power supply. All pins must be
connected.

A

B

Clock

Inputs

D15-0 - Data Input
16-bit data input port. Data is latched
into the registers on the rising edge of
CLK.
Outputs

Y15-0 - Data Output

l
E

F

B

F

G

C

G

H*

D

H*

+

+

CLK - Master Clock
The rising edge of CLK strobes all
registers.

l
A

Four 2-Level (LPR200)
2-Level, One 1-Level (LPR201

Eight 1-Level (LPR200)
Seven 1-Level (LPR201 )

$$
$$

16-bit data output port.
Controls

13-0 - Instruction Control
The instruction control pins select
which register operation will be
carried out. Refer to Tables 2 and 3.

*Applies to LPR200 only

OE - Output Enable

SEL2-0 - Output Select
The output select pins control which
register contents will appear at the
Y15-0 output pins. Refer to Tables 4
and 5.

When OE is LOW, the register data
specified by SELz-o is available on the
Yl5-0 output pins. When OE is HIGH,
the output port is in a high-impedance
state.

CEN - Clock Enable
When CEN is LOW, the instruction
designated by 13-0 is performed on the
registers. When CEN is HIGH, no
register operations are performed.

=======================Pipeline Registers
5-18

06/30/95-LDS.P200/1·C

_.. __ ..
--- --...........
-----

...-.. ....-..-....-..
-~
_____ -....r
-

LPR200/201

~-..-.

-~--

........

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

II

======================= Pipeline Registers
5-19

06/30/95-LDS.P200/1-C

..... - - ------------....---------

-~

-~

LPR200/201

-~---

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

Storage temperature ... ......... ............ ................ .... ..... .............. ........ ....... ...... ..... ..... ..... ......... --65°C to + 155°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ................................................................................ -0.5 V to Vee + 0.5 V
Signal applied to high impedance output .... ,.................................................................. -0.5 V to Vee + 0.5 V
Output current into low outputs .............................................................................................................. 50 rnA
Latchup current ................................................................................................................................ > 400 rnA

Temperature Range (Ambient)

Mode
Active Operation, Commercial
Active Operation, Military

Symbol

Supply Voltage

O°C to +70°C

4.75 V:,; Vee:,; 5.25 V

-55°C to + 125°C

4.50 V :,; Vee:,; 5.50 V

Parameter

Test Condition

Min

VOH

Output High Voltage

Vcc

= Min., IOH =-8.0 rnA

VOL

Output Low Voltage

Vcc

=Min., IOL = 16 rnA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

loz

Typ

Max

Unit
V

2.4
0.4

V

2.0

Vee

V

0.0

0.8

V

Ground:'; VIN:'; Vee (Note 12)

±20

!!A

Output Leakage Current

(Note 12)

±20

!!A

lee1

Vee Current, Dynamic

(Notes 5, 6)

10

30

rnA

lee2

Vee Current, Quiescent

(Note 7)

2.0

10

rnA

CIN

Input Capacitance

TA

= 25°C, f = 1 MHz

10

pF

COUT

Output Capacitance

TA

=25°C, f = 1 MHz

12

pF

=======================Pipeline Registers
5·20

06/30/95-LDS. P200/1·C

- -------......
.....
.........
--- ------------.-.
~-

LPR200/201

-~---

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

Ipw

1

CLK
I-""---Isl

1",_

i - - IsD

IHD_

Ipw

13-0

015-0

I---IPD _ _

SEL2.o

I

IsEL

Y15-0

m ___

II

tPDDO

.

HIGH IMPEDANCE

F1D1S---i

C

teNA

======================= Pipeline Registers
5-21

06130195-LDS. P20011-C

-

-

- -- ------.....-..-.-.
.....-.
----..-~--- - ---

LPR200/201

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

tpw

1

elK

r - - - tSI

tHI_

_

tHO _

tpw

13-0

tso

D15-0

i---tpo_

SEL2-o

I

tSEL
HIGH IMPEDANCE

Y15-0
I •

~

tPDDO

•

I

Ftol~

-------

e

tENA

=======================Pipeline Registers
5-22

06/30/95-lDS. P200/1-C

----- -------.---

-.........-----------...--- - --

LPR200/201

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -D.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guaranteed as specified.

16-bit Multilevel Pipeline Register

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tOIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 ~F ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device Vee
and the tester common, and device
ground and tester common.

5. Supply current for a given applica- b. Ground and Vee supply planes
tion can be accurately approximated by: must be brought directly to the DUT
socket or contactor fingers.
NCV2 F
where

4

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F =clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

t----t-OOUTPUT

n+

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 10 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case re8. These parameters are guaranteed
quirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

======================== Pipeline Registers
5·23

06/30/95-LDS.P200/1·C

- - -------- --.----- - --

-

-~~-~

LPR200/201

-~--DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

48-pin

52-pin

10
CEN
Do
D1
D2
D3
D4
D5
D6
D7
GND
Vee
DB
D9
D10
D11
D12
D13
D14
D15
SE12
SEl1
SElo

Plastic DIP
(P5)
20 ns
15 ns
12 ns
10 ns

20 ns
15 ns
12 ns

12
13
Yo
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
Vee
GND
YB
Y9
VlO
V11
GND
V12
V13
V14
V15
OE
ClK

o

C\I

T"""

0

12
W

0

...

C\I

C')

20000.2:..!:.£:!.£2>->->->-

D3
D4
D5
D6
D7
GND
Vee
DB
D9
D10
D11
D12
NC

B
9
10
11
12

7 6 5 4 3 2 :1: 52 51 50 49 48 47
:~~

46

45
44
43

13
14
15

Top
View

42
41
40

16
17
1a

39
3B
37
36

19
20

35
34

21 22 23 24 25 26 27 28 29 30 31 32 33

NC
GND
Y4
Y5
Y6
Y7
Vee
GND
Va
V9
V10
V11
GND

g c5 5 ~ Cd ~ dI~ ~ ~ ~ ~ ~
(J)(J)(J)

Sidebraze Hermetic DIP
(OS)

LPR200PC20
LPR200PC15
LPR200PC12
LPR200PC10

LPR200JC20
LPR200JC15
LPR200JC12
LPR200JC10

LPR200KMB20
LPR200KMB15
LPR200KMB12

LPR200DMB20
LPR200DMB15
LPR200DMB12

========================Pipeline Registers
5-24

06/30/95-LDS.P20011-e

LPR200/201
DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

52-pin

48-pin

10
CEN
Do
D1
D2
D3
D.
D5
D6
D7
GND
Vee
DB
D9
DlO
D11
D12
D13
D1'
D15
SEL2
SEl1
SELo

20 ns
15 ns
12 ns
10 ns

20 ns
15 ns
12 ns

12
13
Yo
Y1
Y2
Y3
GND
Y.
Y5
Y6
Y7
Vee
GND
Y8
Ya
YlO

U

C\I

....

0

Iw
Z

0.,....

C\I

(I')

ZClCCO.2=~~>->->->

D3
D.
Ds
D6
D7
GND
Vcc
D8
D9
D10
D11
D12
NC

Y"
GND
Y12
Y13
Y,.
Y,5
OE
ClK

8
9
10
11
12
13

7 6 5

•3

L,

52

51 50 49 48 47

46
.5
44

43

42

,.

15
16
17
18
19
20

2 :1 i

.,

Top

.0
39
38
37
36
35

View

34

21 22 23 24 25 26 27 28 29 30 31 32 33
(I')

v

~

~

.... 0

~IW

~

v

(I')

C\I

NC
GND
Y4
Ys
Y6
Y7
Vcc
GND
Y8
Y9
Y10
Y11
GND

0

i5i5i5~~~dO>=>=>=>=Z

LPR201PC20
LPR201PC15
LPR201PC12
LPR201PC10

LPR201JC20
LPR201JC15
LPR201JC12
LPR201JC10

LPR201 KMB20
LPR201KMB15
LPR201KMB12

LPR201 DMB20
LPR201DMB15
LPR201DMB12

=======================Pipeline Registers
5-25

06/30/9S-LDS.P20011-C

•

- --------- ----------

==~~=~

DEVICES INCORPORATED

-- - ------- --

L29C525

-

=-=-=~=::......

-~---

Dual Pipeline Register

DEVICES INCORPORATED

o Dual8-Deep Pipeline Register
o Configurable to Single 16-Deep
o Low Power CMOS Technology
o Replaces AMD Am29525

o Load, Shift, and Hold Instructions
o Separate Data In and Data Out Pins
o Three-State Outputs
o DESC SMD No. 5962-91696
o Available 100% Screened to

o

MIL-STD-883, Class B
Package Styles Available:
• 28-pin Plastic DIP
• 28-pin Sidebraze, Hermetic DIP
• 28-pin Ceramic DIP
• 28-pin Plastic LCC, J-Lead
• 28-pin Ceramic LCC
• 28-pin Ceramic Flatpack

The L29C525 is a high-speed, low
power CMOS pipeline register. It is
pin-for-pin compatible with the AMD
Am29525. The L29C525 can be
configured as two independent 8-level
pipelines or as a single 16-level
pipeline. The configuration implemented is determined by the instruction code (11-0) as shown in Table 2.
The 11-0 instruction code controls the
internal routing of data and loading of
each register. For instruction 11-0 = 00
(Push A and B), data applied at the
D7-O inputs is latched into register AD
on the rising edge of CLK. The
contents of AD simultaneously move
to register AI, Al moves to A2, and so
on. The contents of register A7 are
wrapped back to register BO. The
registers on the B side are similarly
shifted, with the contents of register
B710st.

~
cr:
w

07-0

8

I,·o---r2

!;(
cr:

w
f0-

foUl

Ul

cr:

cr:

aw

aw

elK _ _

Instruction 11-0 = 01 (Push B) acts
similarly to the Push A and B
instruction, except that only the B side
registers are shifted. The input data is
applied to register BO, and the
contents of register B7 are lost. The
contents of the A side registers are
unaffected. Instruction 11-0 = 10 (Push
A) is identical to the Push B
instruction, except that the A side
registers are shifted and the B side
registers are unaffected.
Instruction 11-0 = 11 (Hold) causes no
internal data movement. It is equivalent to preventing the application of a
clock edge to any internal register.
The contents of any of the registers is
selectable at the output through the
use of the 53-0 control inputs. The
independence of the I and S control
lines allows simultaneous reading and
writing. Encoding for the S3-0 controls
is given in Table 3.

AO
A1
A2
A3
A4

A5
A6
A7
80
81
82
83
84
85
86
87

Y7-0

8
OE

S3-0

4

=======================Pipeline Registers
5-27

OB/2B/95-LDS.29C525-A

5

- "'II""!!!=:-e.
- ...... _=

~:...=:.==:..;-

L29C525

DEVICES INCORPORATED

Dual Pipeline Register

-~---

Single 16 Level

DualS Level

Push A and B

Push A

PushB

HOLD

AO
A1
A2.

A3
A4

A5
A6
A7

80
81
82
83
84
85
86
87

AO
A1
A2.

A3
A4

A5
A6
A7

80
81
82
83
84
85
86
87

AO
A1
A2.

A3
A4

A5
A6
A7

o
o
o

Hold All Registers

HOLD

HOLD

HOLD

80
81
82
83
84
85
86
87

AO
A1
A2
A3
A4
A5
A6
A7

80
81
82
83
84
85
86
87

o

AS

o

A6
A7

======================= Pipeline Registers
5-28

06/28/95-LDS.29C525-A

L29C525
DEVICES INCORPORATED

Dual Pipeline Register

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to + 125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

-55°C to + 125°C

Supply Voltage
4.75 V::;; Vee::;; 5.25 V
4.50V::;;Vee::;;5.50V

•

L - - -_ _ _ _ _ _ _ _- - - - - '

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee = Min., IOH = -12 mA

2.4

VoL

Output Low Voltage

Vee = Min., IOL = 24 mA

V1H

Input High Voltage

V1L

Input Low Voltage

(Note 3)

IIX

Input Current

loz

Symbol

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground::;; VIN ::;; Vee (Note 12)

±20

~

Output Leakage Current

Ground::;; VOUT ::;; Vee (Note 12)

±20

~

lee1

Vee Current, Dynamic

(Notes 5,6)

35

mA

lee2

Vee Current, Quiescent

(Note?)

1.0

mA

10

======================= Pipeline Registers
5·29

06/2B/95-LDS.29C525·A

--

- -...........----------------- - -.-..-.

.---.---

~

L29C525

DEVICES INCORPORATED

Dual Pipeline Register

I - - - t S D - t--tHD D7-0

f---

tHI-

tSI

11-0

tpw

tpw

{

lE

elK

I-tPD83-0

~

tSEL

~
I=tENA-j

-t=tDIS-i
HIGH IMPEDANCE
Y7-0

J(

======================= Pipeline Registers
5-30

06/28/95-LDS.29C525-A

- ----_........-....-...

~--

-~-=-:w=~=~
-~---

L29C525

DEVICES INCORPORATED

Dual Pipeline Register

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/toIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
Parasitic
1.5 V may be used.
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDISABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

•

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

a. A 0.1 J.IF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated b. Ground and Vee supply planes
by:
must be brought directly to the DUT
NCV2 F
socket or contactor fingers.

4

where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

=======================Pipeline Registers
5-31

06/28/9S-LDS.29CS2S·A

- -------.......
--- ------_
----- - --~---

-

L29C525

DEVICES INCORPORATED

28-pin -

Dual Pipeline Register

0.3" wide

81
80
Do
D1
D2
D3
Vee
GND
D4
D5
D6
D7
10
CLK

20 ns
15 ns

L29C525PC20
L29C525PC15

28-pin -

0.4" wide

81
80
Do
D1
D2
D3
Vee
GND
D4
D5
D6
D7
10

82
83
Yo
Y1
Y2
Y3
Vee
GND
OE
Y4
Y5
Y6
Y7
11

CLK

L29C525NC20
L29C525NC15

L29C525DC20
L29C525DC15

82
83
Yo
Y1
Y2
Y3
Vee
GND
OE
Y4
Ys
Y6
Y7

11

L29C5251C20
L29C5251C15

25 ns
20 ns

L29C525DM25
L29C525DM20

L29C5251M25
L29C5251M20

25 ns
20 ns

L29C525DMB25
L29C525DMB20

L29C5251MB25
L29C5251MB20

======================= Pipeline Registers
5-32

06/28/9S-LDS.2geS2S-A

----.-.---_
-- --.....- ----.......-

~-~
-,.--,.
-

L29C525

-~---

DEVICES INCORPORATED

Dual Pipeline Register

28-pin

28-pin

o o0
'I"'"

Y1

24

Y2

23

Y3

22

VCC

21

GNO

10

20

OE

11

19
12 13 14 15 16 17 18

5

03

6

VCC

7

GNO

8

04

9

Os
06

3

Top
View

81~
8o~
Oo~
01~

>0

2 :1: 28 27 26
:_~
25

02

4

0
.... C\I (')
(IJ(IJ(IJ(IJ

02~
03~
VCC~
GNO~
04~

Os~
06~
07~
lo~
elK ~

Y4

B.E~':::>=~~
()

20 ns
15 ns

25 ns
20 ns

12
3
4
5

28

6

23
22
21
20

7

8
9
10
11
12
13
14

25

'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J
'i==:J

82
83
Yo
Y1
Y2
Y3
VCC
GNO

OE
Y4
Ys
Y6
Y7
11

L29C525JC20
L29C525JC15

L29C525KMB25
L29C525KMB20

L29C525MMB25
L29C525MMB20

=======================Pipeline Registers
5-33

0612819S-LDS.29CS2S-A

•

DEVICES INCORPORATED

-----

L10c 11

- ----

=-U~=~
-~----DEVICES INCORPORATED

4/8-bit Variable Length Shift Register

o Variable Length 4 or 8-bit Wide
o
o
o

o
o
o

o

The LlOCll is a high-speed, low
Shift Register
power CMOS variable length shift
register. The LIOCll consists of two
Selectable Delay Length from 3 to
4-bit wide, adjustable length shift
18 Stages
registers. These registers share control
Low Power CMOS Technology
signals and a common clock. Both
Replaces TRW lRaytheon TMC2011
shift registers can be programmed
Load, Shift, and Hold Instructions
together to any length from 3 to 18
Separate Data In and Data Out Pins stages inclusive, or one register can be
, fixed at 18 stages of delay while the
Available 100% Screened to
MIL-STO-883, Class B
other is variable. The configuration
implemented is determined by the
Package Styles Available:
Length Code (L3-O) and the MODE
• 24-pin Plastic DIP
control line as shown in Table 1.
• 24-pin Ceramic DIP
• 28-pin Plastic LCC, J-Lead
Each input is applied to a chain of
registers which are clocked on the
rising edge of the common CLK input.
These registers are numbered Rl
through R17 and Rl' through RI7',
corresponding to the 03-0 and 07-4
data fields respectively. A multiplexer serves to route the contents of
any of registers R2 through R17 to the
output register, denoted R18. A
similar multiplexer operates on the
contents of R2' through RI7' to load

RI8'. Note that the minimum-length
path from data inputs to outputs is Rl
to R2 to R18, consisting of three stages
of delay.
The MODE input determines whether
one or both of the internal shift
registers have variable length. When
MODE = 0, both 03-0 and 07-4 are
delayed by an amount which is
controlled by L3-O. When MODE = 1,
the 07-4 field is delayed by 18 stages
independent of L3-O.
The Length Code (L3-O) controls the
number of stages of delay applied to
the 0 inputs as shown in Table 1.
When the Length Code is 0, the inputs
are delayed by 3 clock periods. When
the Length Code is 1, the delay is 4
clock periods, and so forth. The
Length Code and MODE inputs are
latched on the rising edge of CLK.
Both the Length Code and MODE
values may be changed at any time
without affecting the contents of
registers Rl through R17 or Rl'
through RI7'.

0:
4

D3-0

a:
w

ti

aw

elK _

• • •

a:

4
La-o

a:
w

I-

en

aw
a:

MODE

..J

0:
4

D7-4

a:
w

l-

en

aw

• • •

a:

=======================Pipeline Registers
5-35

06/23/95-LDS.ll-H

•

-=

---

....:~=:"'!f!!
=-=-==-==
=---

L10C11

-~---

DEVICES INCORPORATED

La

L2

Ll

0
0
0
0
0
0
0
0
1

0
0
0
0
1

0
0

Storage temperature ...................................................... -65°C to + 150°C
0

3
4
5
6
7
8

3
4
5
6
7
8

3
4
5
6
7
8

0

9

9

9

10
11
12
13
14
15
16
17
18

10
11
12
13
14
15
16
17
18

10
11
12
13
14
15
16
17
18

0
1
0
0

0

1

1

1

0
0
0
0

0
0

0
0

0
0

0
1
0

Symbol

4/8-bit Variable Length Shift Register

18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18

Operating ambient temperature ...................................... -55°C to + 125°C
Vee supply voltage with respect to ground ...................... -0.5 V to +7.0 V
Input signal with respect to ground .................................. -3.0 V to +7.0 V
Signal applied to high impedance output ......................... -3.0 V to +7.0 V
Output current into low outputs ....................................................... 25mA
Latchup current .......................................................................... > 400 mA

Mode

Temperature Range

Supply Voltage

Active Operation, Com.

O°C to +70°C

4.75 V:::; Vee:::; 5.25 V

Active Operation, Mil.

-55°C to +125°C

4.50 V :::; Vee:::; 5.50 V

Parameter

Test Condition

Min

VOH

Output High Voltage

Vee = Min., IOH = -12 mA

2.4

VOL

Output Low Voltage

Vee = Min., IOL = 24 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

IIX

Input Current

Ground:::; VIN :::; Vee (Note 12)

leel

Vee Current, Dynamic

(Notes 5, 6)

lee2

Vee Current, Quiescent

(Note 7)

Typ

Max

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

±20

J.IA

20

mA

1.0

mA

10

======================= Pipeline Registers
5-36

OS/23/95-LDS.11-H

....-..-__-.....
..
- - ....._--..-_
---_

...-....
....--......-.
--.--..-.

...--.
-

L10C11

-~---

DEVICES INCORPORATED

D7-0

4/S-bit Variable Length Shift Register

tSD

tHD-

tSL

tHL-

~~

.7~

La-a

~

MODE

tpw

I.

tpw

{

elK
tPD

*'--________

Y7-0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

=======================Pipeline Registers
5-37

06/23/9&-LDS.11-H

- --------- -..--...------ -------

-

L10C11

-~---

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.

4/S-bit Variable Length Shift Register

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDiS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDiSABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

3. This device provides hard clamping
of transient undershoot and overshoot. This device has high-speed outputs caInput levels below ground or above Vee pable of large instantaneous current
will be clamped beginning at -0.6 V and pulses and fast turn-on/turn-off times.
Vee + 0.6 V. The device can withstand As a result, care must be exercised in
indefinite operation with inputs in the the testing of this device. The following
range of -0.5 V to +7.0 V. Device opera- measures are recommended:
tion will not be adversely affected, however, input current levels will be well in a. A 0.11JF ceramic capacitor should be
excess of 100 mAo
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated
b. Ground and Vee supply planes
by:
must be brought directly to the DUT
NCV2 F
--socket or contactor fingers.

4

where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

=======================Pipeline Registers
5·38

06/23/95-LDS.11·H

- - -----........

-~--~=-~&.:=:....
-~---

L10C11

DEVICES INCORPORATED

24-pin -

4/8-bit Variable Length Shift Register

0.3" wide

Do
01
02
03
Lo
L1
Vce

CLK
04
05
Os
07

25 ns
20 ns
15 ns

L10CllPC25
L10CllPC20
L10CllPC15

24-pin -

L2
L3

L1 OCll CMB30
L10CllCMB25
L1 OCll CMB20

GNO
MODE
Y4
Ys
Ys
Y7

CLK
04
05
Os
07

Ll0CllCC25
Ll0CllCC20
Ll0CllCC15

30 ns
25 ns
20 ns

L2
L3

Vee

GNO
MODE
Y4
Ys
Ys
Y7

Ll0CllCM30
Ll0CllCM25
Ll0CllCM20

Yo
Y1
Y2
Y3

Do
01
02
03
Lo
L1

Yo
Y1
Y2
Y3

30 ns
25 ns
20 ns

0.6" wide

L10CllNC25
L10CllNC20
L10CllNC15

======================= Pipeline Registers
OS/23/9S-LDS.11-H
5-39

•

-

- -- .,------..,--.,
- --~---

.-.-.--~

L10C11

DEVICES INCORPORATED

4/S-bit Variable Length Shift Register

28-pin

C\I

.....

0

0

.....

C\I

(')

000>->->->3 2 1 282726
25

•

Ds

Lo

L2
l3
GND
GND
MODE
NC

Top
View
D4
NC
an

CD

,...

f'..

NC

CD

an

'V

000>->->->-

25 ns
20 ns
15 ns

L10C11JC25
L10C11JC20
L10C11JC15

====================== Pipeline Registers
5-40

OB/23/95-LDS.11-H

--------=-=:....:
-===-..r
--

L21C11

-

-~

~

o Variable Length 8-bit Wide Shift
Register
o Selectable Delay Length from 1 to
16 Stages
o Low Power CMOS Technology
o Replaces TRW lRaytheon TMC2111
o Load, Shift, and Hold Instructions
o Separate Data In and Data Out Pins
o Available 100% Screened to
MIL-STD-883, Class B
o Package Styles Available:
• 24-pin Plastic DIP
• 24-pin Ceramic DIP
• 28-pin Plastic LCC, J-Lead

a-bit Variable Length Shift Register

The L21Cll is a high-speed, low
power CMOS variable length shift
register. It consists of a single 8-bit
wide, adjustable length shift register. The shift register can be programmed to any length from 1 to 16
stages inclusive. The length of the
shift register is determined by the
Length Code (L3-0) as shown in
Table 1.
The data input is applied to a chain
of registers which are clocked on the
rising edge of the CLK input. These
registers are numbered R1 through
R15. A multiplexer serves to route
the contents of any register, R1
through R15, or the data input, D7-0,
to the output register, denoted R16.
Note that the minimum-length path
from data input to output is through
R16, consisting of a single stage of
delay.

The Length Code (L3-0) controls the
number of delay stages applied to the
D7-O inputs as shown in Table 1.
When the Length Code is 0, the input
is delayed by 1 clock period. When
the Length Code is 1, the delay is 2
clock periods, and so forth. The
Length Code inputs are latched on the
rising edge of CLK. The Length Code
value may be changed at any time
without affecting the contents of
registers R1 through R15.

R15
R14
R13

8

•
•
•R3

• • •

07-0

Y7-O

R2
R1

r:r:

4
~-O --~~~

a~w ~----------------------------------------------~
r:r:

...J

elK _

TO All REGISTERS

=======================Pipeline Registers
5-41

06/23/95-LDS.21 Cll-B

•

L21C11
DEVICES INCORPORATED

8-bit Variable Length Shift Register

Storage temperature ...................................................... -65°C to + 150°C
0
0
0
0
0
0
0
0

0
0
0
0

0
0
0
0

0
0
1
0
0

0
0

0
1
0
1
0
1
0
0
1

0
0

Symbol

0

0
1
0

1
2
3
4
5
6
7
8

Operating ambient temperature ...................................... -55°C to + 125°C
Vee supply voltage with respect to ground ...................... -0.5 V to +7.0 V
Input signal with respect to ground .................................. -3.0 V to +7.0 V
Signal applied to high impedance output ......................... -3.0 V to +7.0 V
Output current into low outputs ....................................................... 25mA
Latchup current .......................................................................... > 400 mA

9

10
11
12
13
14
15
16

Mode

Temperature Range

Supply Voltage

Active Operation, Com.

O°Cto +70°C

4.75 V ::; Vee::; 5.25 V

Active Operation, Mil.

-55°C to + 125°C

4.50 V ::; Vee::; 5.50 V

Parameter

Test Condition

Min

VoH

Output High Voltage

Vee

=Min., IOH =-12 mA

VoL

Output Low Voltage

Vee

=Min., IOL =24 mA

V1H

Input High Voltage

V1L

Input Low Voltage

(Note 3)

Ilx

Input Current

Ground::; VIN::; Vee (Note 12)

leel

Vee Current, Dynamic

(Notes 5, 6)

lee2

Vee Current, Quiescent

(Note 7)

Typ

Max

2.4

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

±20

J.IA

20

mA

1.0

mA

10

=======================Pipeline Registers
5-42

06/23/95-LDS.21 C11·B

--.-.--- -............- ------------

-.-.

L21C11

~-~

-~---

DEVICES INCORPORATED

8-bit Variable Length Shift Register

tSD

tHD-

tSL

tHL-

D7-0

La-o
tpw

~

eLK
I.

tPD

tpw

¥

*. _________

Y7-0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

======================Pipeline Registers
5-43

06/23/95-LDS.21C11-B

--.....
-- -......------.-

- ------- - --""'-"""--~-

L21C11

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.
4. Actual test conditions may vary
from those designated but operation is
guaranteed as specified.
5. Supply current for a given application can be accurately approximated
by:
NCV2 F

4
where
N
C
V
F

= total number of device outputs
= capacitive load per output
=

supply voltage

= clock frequency

8-bit Variable Length Shift Register

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDrs test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDISABLE measurements, the load
current is increased to 10 rnA to reduce
the RC delay component of the
measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vee

do

}
1

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:
a. A 0.1 J.IF ceramic capacitor should be
installed between vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device vee
and the tester common, and device
ground and tester common.
b. Ground and Vee supply planes
must be brought directly to the DUT
socket or contactor fingers.

+---t--oOUTPUT

n+

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
much
time to meet the worst-case re8. These parameters are guaranteed
quirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

01
p--

TRISTATE
OUTPUTS

--=~t-'J!2t!.!!!!:!~~!l
.2V

O.2V

=======================Pipeline Registers
5-44

OB/23/95-LDS.21 ell·B

- . ----- .-.-.-.----- -----.-.---.....-.,

.,

-

L21C11

-~---

DEVICES INCORPORATED

a-bit Variable Length Shift Register

24-pin - 0.3" wide

Do
D1
D2
D3
lo
II

vcc
ClK
D4
Ds
De
D7

2S-pin

C\I

Yo
Y1
Y2
Y3
l2
l3
GND
GND
Y4
Ys
Ye
Y7

T"""

a

a

.,....

C\I

C"l

000>->->->3 2 1 282726
25

•

03
II

04
NC

Top
View

NC
l2
l3
GNO
GNO
GND
NC

21

11
19
12131415161718
10

(!)

I'--

I'--

(!)

10

"->->->-

Plastic J-Lead Chip Carrier
(J4)
25 ns
20 ns
15 ns

L21C11PC25
L21C11PC20
L21C11PC15

L21C11JC25
L21C11JC20
L21C11JC15

30 ns
25 ns
20 ns

L21C11CM30
L21C11CM25
L21C11CM20

30 ns
25 ns
20 ns

L21C11CMB30
L21 C11 CMB25
L21 C11 CMB20

======================= Pipeline Registers
5-45

06/23/9S-LDS.21 Cll-8

•

DEVICES INCORPORATED

-- - -----=::......

- - - - -=-:......=::...=
----

....-.-.

L29C818

~

a-bit Serial Scan Shadow Register

.---.

~

-~

o Octal Register with Additional 8-bit The L29C818 is a high-speed octal
o

o
o

o
o

o
o

Shiftable Shadow Register
Serial Load/Verify of Writable
Control Store RAM
Serial Stimulus/Observation of
Sequential Logic
High-Speed, Low Power CMOS
Technology
Replaces AMD Am29818
DESC SMD No. 5962-90515
Available 100% Screened to
MIL-STD-883, Class B
Package Styles Available:
• 24-pin Plastic DIP
• 24-pin Sidebraze, Hermetic DIP
• 28-pin Ceramic LCC

register designed especially for
applications using serial-scan diagnostics or writable control store. It is pin
and functionally compatible with the
AMD Am29818 bipolar device.
The L29C818 consists of an octal
register, the P register, internally
connected to an 8-bit shift register, the
S register. Each has its own corresponding clock pin and the P register
has a three-state output control.
An input control signal, MODE, in
combination with the S register serial
data input (SDI) pin controls data
routing within the L29C818. When
the MODE input is LOW, indicating
normal operation, data present on the
D7-0 pins is loaded into the P register
on the rising edge of CLK P. The
contents of the P register are visible on
the output pins Y7-0 when the OE
control line is LOW.

Also, data present on the SDI pin is
loaded into the least significant
position of the S register on the rising
edge of CLK S. In this mode, the S
register performs a right-shift operation with the contents of each bit
position replaced by the value in the
next least significant location. The
value in S7 is shifted out on the serial
data output (SDO) pin. The SDI and
SDO pins allow serial connection of
multiple L29C818 devices into a
diagnostic loop. When MODE is
LOW, the operation of the P and S
registers are completely independent
and no timing relationship is enforced
between CLK P and CLK S.
When MODE is HIGH, the internal
multiplexers route data between the S
and P registers and the Y port. The
contents of the S register are loaded
into the P register on the rising edge of

SDI---r----~---L--~---------L.SDO
ClK S ---j--r-----j>S REGISTER

MODE~1I~--1L__- ,__~

Yo

S7-0

y,

y,

SDI~------_r--+_------+_----------~~

D7-0 --+-+-+--------------+--~

SDO
MODE

-+-~----->~

ClK S --------I>

ClKP----------------~~~~~
So

OE--------------------~J

S REGISTER

Y7-0

=======================Shadow Registers
5-47

06/23/95-LDS.818-G

II

- -..- _--..--_------- ...... -- ---

-

L29C818

DEVICES INCORPORATED

CLK P. In diagnostic applications, this
allows a data value input via serial
scan to be loaded into the active data
path of the machine.
When the MODE pin is HIGH, CLK S
causes a parallel, rather than serial,
load of the S register. In this mode,
the S register is loaded from the Y7-0
pins at the rising edge of CLK S. This
is useful in writable control store
applications for read-back of the
control store via the serial path.
When MODE is HIGH, the SDI pin is
used as a control input to enable or
disable the loading of the S register. It
also affects routing of the S register
contents onto the D7-0 outputs. When
SDI is LOW, the S register is enabled
for loading as above. When SDI is
HIGH however, CLK S is prevented
from reaching the S register and no
load occurs. In order to allow the SDI
pin to serve as an enable signal for all
L29C818 devices in a serial configuration, special handling of the SDI input

8-bit Serial Scan Shadow Register
is required. When MODE is HIGH,
the SDI input drives the SDO output
directly, bypassing the S register. This
means that the SDI value will apply
simultaneously to all L29C818s in a
serial loop. However, to ensure
proper operation of a given device,
the user must ensure that the SDI
setup time to CLK S is extended by
the sum of the SDI to SDO delays of
all previous devices in the serial path.
The D7-0 port is normally used as the
input port to the D register. For
writable control store applications
however, this port is connected to the
I/O pins of the RAM used as a control
store. In order to load this RAM
through the serial path, it is necessary
to drive the S register contents onto
the D7-0 pins. This is accomplished
when MODE and SDI are HIGH and a
CLK S rising edge occurs. Note from
above that with SDI HIGH, no loading
of the S register occurs. However, a
flip-flop is set which synchronously
enables the D port output buffer. The

D output remains enabled until the
first rising edge of CLK S during
which either SDI or MODE is LOW.
Thus to load a control store RAM,
data would be shifted in with MODE
LOW. When an entire control store
word is present in the serial S registers, the SDI and MODE pins are
brought HIGH for one or more cycles,
preventing further shifting of the S
registers and enabling the contents
onto the D port for writing into the
RAM.
To verify the contents of a control
store RAM, the RAM is read into the
D register in the normal fashion.
Then, the D contents are transferred in
parallel to the S register by driving
MODE HIGH with SDI LOW. The S
register contents are then scanned out
serially by returning MODE LOW and
applying CLK S pulses.

'If OE is LOW, the P register value will be loaded into the S register. If OE is HIGH, a value may be applied externally to the Y7·0 pins.

======================= Shadow Registers
5-48

06/23/95-LDS.818-G

------- --- ------

--- -........------ -

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ........................................................................................... -55°C to +125°C
Vee supply voltage with respect to ground ........................................................................... -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA
Latchup current ................................................................................................................................ > 400 mA

Mode

Temperature Range (Ambient)

Active Operation, Commercial

O°C to +70°C

Active Operation, Military

-55°C to +125°C

Supply Voltage
4.75 V:::; Vee:::; 5.25 V
4.50V:::;Vee:::;5.50V

•

'------------------'

>iIi
•..L"'~.,·.:'...:.·.T';
.1
Symbol

.',.'.' '··1 ,. ·LX.···. ,··.'.'L·•.· '• ·"" . • '".> . ··L?'.,·:,;::;;~.',7A'~+,,'4))'·.,.·

• •. • • ,i...... ?!......'.,!i· . i>

Parameter

Test Condition

Min

VOH

Output High Voltage

Vee=Min.,loH=-12.0mA

2.4

VOL

Output Low Voltage

Vee = Min., IOL = 24.0 mA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Current

loz

Typ

• i •• >f·.'• •.
Max

,i.

Unit
V

0.5

V

2.0

Vee

V

0.0

0.8

V

Ground:::; VIN:::; Vee (Note 12)

±20

~

Output Leakage Current

Ground:::; VOUT:::; Vee (Note 12)

±20

~

lee1

Vee Current, Dynamic

(Notes 5,6)

15

mA

lee2

Vee Current, Quiescent

(Note 7)

1.0

mA

10

=======================Shadow Registers
5·49

OS/23/95-LDS .81 8-G

----------- -....-..........- ----------..-.
- - --

-....-.
-

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

MODE

r---

tSMP

tHMP

I--tSDP

tHDP

D7-0

X

CLKP
tpwp

Y7-0

HIGH IMPEDANCE

~l

1---4OE

tENA

~

I

tpwp

1
HIGH IMPEDANCE

tPDY

r::LtDIS

~

====================== Shadow Registers
5-50

06f23f95-LDS.818-G

---------.-.--- -----..-.-. -.---

L29C818

---~-.---~---

DEVICES INCORPORATED

10"". _i, "0°

8-bit Serial Scan Shadow Register

::':"', _1.~'~A~'

.i!~h"'"

.....

~oo.ii'.1;o.o.'o,

····>i·,· . < . . • • •

'°0 ·'.'· ••

,~,

.•...••••••. ....•

·.·.i·ui ···i

L29C81825

15

Symbol

Parameter

Min

Max

Min

tpws

elK S Pulse Width

25

tDSSO

elK Sto SDO

tSSIS

SDI to elK S Setup Time

tHSSI

elK S to SDI Hold Time

tSMS

MODE to elK S Setup Time

tHSM

elK S to MODE Hold Time

2

2

tDMSO

MODE to SDO

16

16

tDSISO

SDI to SDO

16

15

25
10

Max

15
25
10

0

0

12

12

MODE

•••

SDI
!HSSI

•••

elKS
!PWS

•••

SDO
!DSSO

=======================Shadow Registers
5-51

06/23/95-LDS.818-G

----.-.-.-- --- ----------...-.--.---.

L29C818

-~---

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

t

MODE

ISMP

ClKP

ClKS

J

Issp

J

IHPM

J

"

====================== Shadow Registers
5-52

OS/23/95-LDS.818-G

-

- --------- -------------.........----- - --

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

COMM6R~IAL.()~ERAl'l~GRAN~~(o(>e.tQ+10:~¢).tYtl~~~j. . . ........>.... ......> ..... >.·....· . ·. . ».>i
L29C81825

Symbol

Parameter

Min

15
Max

Min

tSYS

Y7-0 to elK S Setup Time

5

tHSY

elK S to Y7-0 Hold Time

5

5

tSMS

MODE to elK S Setup Time

12

12

tHSM

elK S to MODE Hold Time

2

2

tSSIS

SOl to elK S Setup Time

10

10

tHSSI

elK S to SOl Hold Time

0

0

. . . . . . . . . . . · .· ·. · . . ·. ·. ·. . . . t·.·.•.·.i

Max

5

c
• > ••.•.••·•·• ·.···.i>

i . . .·•· .·. i ••... y . . . . •. . .•. . . . . . .

l29C81824

30
Symbol

Parameter

Min

Max

Min

tSYS

Y7-0 to elK S Setup Time

tHSY

elK S to Y7-0 Hold Time

tSMS

MODE to elK S Setup Time

tHSM

elK S to MODE Hold Time

5

5

tSSIS

SOl to elK S Setup Time

12

12

tHSSI

elK S to SOl Hold Time

0

0

5
5

5

12

12

EXTERNALLY DRIVEN

Y7-0

Isys

elKS

Max

5

IHSY

It'

MODE
~ISMS- - I H S M -

SOl
I---lsSls- - I H S S I -

=======================Shadow Registers
5-53

06/23/95-LDS.818-G

•

- ---- -------- ---------------~---

-

L29C818

DEVICES INCORPORATED

8-bit Serial Scan Shadow Register

MODE

;
ISMS

IHSM

IHSM

f---ISMS

SOl

1<;.
ISSIS

i---Issis

IHSSI

IHSSI

elKS

07-0

HIGH IMPEDANCE

I

IDISD

IENAD

t=1

HIGH IMPEDANCE

======================= Shadow Registers
5-54

06/23/95-LDS.818-G

---------------------------

.-...--.-.

L29C818

-

-~---

DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond those indicated in the Operating
Conditions table is not implied. Exposure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mAo

8-bit Serial Scan Shadow Register

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDISABLE measurements, the load
current is increased to 10 rnA to reduce
the RC delay component of the
measurement.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.

11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

tENA

-===~~-'2~~f$L=
f

TRISTATE
OUTPUTS -

0.2 V

0.2 V

a. A O.I/-lF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DDT) as possible. Similar capacitors
from those designated but operation is should be installed between device Vee
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated b. Ground and Vee supply planes
by:
must be brought directly to the DDT
NCV2 F
socket or contactor fingers.

4

where
N
C
V
F

=
=
=
=

total number of device outputs
capacitive load per output
supply voltage
clock frequency

C. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.

======================= Shadow Registers
5-55

06/23/95-LDS.818·G

•

- ---------- --...-------

L29C818

-

-~---~---

DEVICES INCORPORATED

24-pin -

8-bit Serial Scan Shadow Register

OE

CLKS

VCC
MOOE

00

Va

01

V1

02

V2

03

V3

04

V4

Os

Vs

06

V6

07

V7

SOl
GNO

25 ns
15 ns

28-pin

0.3" wide

4

3

2 :1: 28 27 26
:_,
25

01

S

02

6

03

7

NC

8

04

9

Os

10

20

Vs

06

11

19
12 13 14 15 16 17 18

V6

Top
View

V1

24

V2

23

V3

22

NC

21

V4

SOO

CLKP

Plastic DIP
(P2)

Sidebraze
Hermetic DIP (02)

L29C818PC25
L29C818PC15

L29C818CC25
L29C818CC15

Ceramic Leadless Chip Carrier
(K1)

-~~~~~-

30 ns
24 ns

L29C818CM30
L29C818CM24

30 ns
24 ns

L29C818CMB30
L29C818CMB24

L29C818KMB30
L29C818KMB24

======================= Shadow Registers
5-56

06/23/95-LDS.818-G

--

-.----------- -......---------...-.-- - -DEVICES INCORPORATED

Peripheral Products

II

- -........
------- --......- ----~-

-...-.--~

-~---

DEVICES INCORPORATED

Peripheral Products

PERIPHERAL PRODUCTS .................................................................................................................................................. 6-1
L5380
L53C80

SCSI Bus Controller ............................................................................................................................................. 6-3
SCSI Bus Controller ............................................................................................................................................. 6-3

II

6·1

-

- ------- -.-.-.-- -------- - ---

-~---

DEVICES INCORPORATED

Lu~s~

L5380/53C80

~

SCSI Bus Controller

-~--~

I
o Asynchronous Transfer Rate Up to

o
o

o
o
o
o

4 Mbytes/sec
Low Power CMOS Technology
Replaces NCR 5380/53C80/
53C80-40 and AMD Am5380/53C80
On-Chip SCSI Bus Drivers
Supports Arbitration, Selection/
Reselection, Initiator or Target Roles
Programmed or DMA I/O, Handshake or Wait State DMA Interlock
Package Styles Available:
• 40/ 48-pin Plastic DIP
• 48-pin Sidebraze, Hermetic DIP
• 44-pin Plastic LCe, J-Lead

The L5380/53C80 are high performance SCSI bus controllers which
support the physical layer of the SCSI
(Small Computer System Interface)
bus as defined by the ANSI X3T9.2
committee. It is pin and functionally
compatible with the NMOS NCR5380,
while offering up to a 2.5x performance improvement, lOx power reduction, and lower cost. Replacement of
the NMOS 5380 by the LOGIC Devices
L5380 / 53C80 will result in an immediate transfer rate improvement due
to REQ/ ACK and DRQ/DACK
handshake response times up to 5
times faster than previous devices.
While remaining firmware compatible
with the NCR5380, the L5380/53C80
provides bug fixes and state machine
enhancements allowing even larger
throughput gains for new designs.

The L5380/53C80 supports asynchronous data transfer between initiator
and target at up to 4 Mbytes/sec. It
operates in either initiator or target
roles and offers a choice of programmed I/O (direct microprocessor
manipulation of handshake) or any of
several DMA modes (autonomous
handshake and data transfer operations). The L5380/53C80 has internal
hardware to support arbitration and
can monitor and generate interrupts
for a variety of error conditions. It
provides extensive bus status monitoring features and includes buffers
capable of directly driving a terminated SCSI bus for a compact imple•
mentation.

CS
lOR
lOW

A2
A1
Ao

RESET
IRQ

DRQ

DACK
EOP

READY

hn=t=='--.,.....,.-14~L~=~ RST, BSY

+--~~-~~~~-T~

T-lr!==t~;-;:::========~

SEL,ACK
ATN

f - -L----A.I/O,
- - - - , / C/D, REQ
MSG

CONTROL AND STATUS BUS

=======================Peripheral Products
6-3

06/23/95-LDS.5380-G

-.:::..
------ --------=------~.:.

L5380/53C80

-

.......

DEVICES INCORPORATED

PIN DEFINITIONS
A. SCSI Bus
SDB7-O -

SCSI DATA BUS 7--0

Bidirectional/ Active low. The 8-bit
SCSI data bus is defined by these pins.
SDB7 is the most significant bit.
During arbitration phase, these lines
contain the SCSI ID numbers of all
initiators arbitrating for the SCSI bus;
SDB7 represents the initiator with the
highest priority. During the selection/reselection phase, these lines
contain the ID number of the device
that won the arbitration along with
the ID number of the device to be
selected/ reselected.
SDBP -

SCSI Bus Controller
shake between the initiator and target.
Data is latched by the target on the
lowgoing edge of ACK for target
receive operations.
ATN -

RST -

Bidirectional! Active low. RST when
active indicates a SCSI bus reset
condition.
I/O -

SELECT

Bidirectional! Active low. SEL is
asserted by the initiator to select a
target. It is also asserted by the target
when reselecting it as an initiator.

CONTROL/DATA

Bidirectional! Active low. C/D is
controlled by the target and when
asserted, indicates CONTROL (command or status) information is on the
SCSI d~ta bus. DATA is specified
when C/D is deasserted.

BUSY
MSG -

Bidirectional/ Active low. BSY is
asserted to indicate that the SCSI bus
is active.
ACK -

INPUT/OUTPUT

Bidirectional! Active low. T/o is
controlled by the target and specifies
the direction of information transfer.
WhenI;O is asserted, the direction of
transfer is to the initiator. 1/0 is also
asserted by the target during RESELECTION phase to distinguish it from
SELECTION phase.
C/D -

BSY -

SCSI BUS RESET

SCSI DATA BUS PARITY

Bidirectional! Active low. SDBP is the
parity bit of the SCSI data bus. Odd
parity is used, meaning that the total
number of ones on the bus, including
the parity bit, is odd. Parity is always
generated when sending information,
however checking for parity errors
when receiving information is a user
option. Parity is not valid during
arbitration phase.
SEL -

ATTENTION

Bidirectional! Active low. ATN is
asserted by the initiator after successful selection of a target, to indicate an
intention to send a message to the target. The target responds to ATN by
entering the MESSAGE OUT phase.

MESSAGE

Bidirectional! Active low. MSG is
controlled by the target, and when
asserted indicates MESSAGE phase.

B. Microprocessor Bus
CS -

CHIP SELECT

Input/ Active low. This signal enables
reading or writing of the internal
registers by the microprocessor, using
memory mapped I/O. An alternate
method for reading selected registers
is available for DMA.
DRQ -

DMA REQUEST

Output/ Active high. This signal is
used to indicate that the L5380/53C80
is ready to execute the next cycle of a
DMA transfer on the microprocessor
bus. For send operations, it indicates
that the output data register is ready
to receive the next byte from the DMA
controller or CPU. For receive operations, it indicates that the input data
register contains the next byte to be
read by the DMA controller or CPU.
IRQ -

INTERRUPT REQUEST

Output/ Active high. The L5380/
53C80 asserts this signal to indicate to
the microprocessor that one of the
several interrupt conditions have been
met. These include SCSI bus fault
conditions as well as other events
requiring microprocessor intervention.
Most interrupt types are individually
maskable.
lOR -

I/O READ

Input/ Active low. lOR is used in conjunction with CS and A2--D to execute a
memory mapped read of a L5380/
53C80 internal register. It is also used
in conjunction with DACK to execute
a DMA read of the SCSI Input Data
Register.

ACKNOWLEDGE
REQ -

Bidirectional/ Active low. ACK is
asserted by the initiator during any
information transfer phase in response
to assertion of REQ by the target.
Similarly, ACK is deasserted after
REQ becomes inactive. These two
signals form the data transfer hand-

REQUEST

Bidirectional! Active low. REQ is
asserted by the target to begin the
handshake associated with transfer of
a byte over the SCSI data bus. REQ is
deasserted upon receipt of ACK from
the initiator. Data is latched by the
initiator on the lowgoing edge of REQ
for initiator receive operations.

READY -

READY

Output/ Active high. Ready is used
rather than DRQ as an alternate
method for controlling DMA data
transfer. This DMA type is termed
blockmode DMA and must be specifically enabled by the CPU. In block-

======================Peripheral Products
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-------

L5380/53C80

-~---

DEVICES INCORPORATED

SCSI Bus Controller
ADDRESS 2-0

mode DMA, data is throttled by treating the L5380/53C80 as wait state
memory. I/O (DMA) cycles are
initiated at the maximum rate sustainable by the DMA controller/memory
subsystem, but all cycles are extended
(wait-states inserted) until READY is
asserted by the L5380/53C80. This is
generally the fastest DMA method
since memory subsystem addressing
can be overlapped with SCSI operations (flyby mode).

A2-0 -

DACK -

L5380/53C80
INTERNAL REGISTERS

WRITE ADDRESS 1
Initiator Command Register

Overview

The Initiator Command Register is a
read/write register which allows CPU
control of the SCSI signals asserted by
the initiator. Some bits in this register
are not readable, and these positions
are mapped to status bits useful in
•
monitoring the progress of arbitration.
These, along with the initiation of
system-wide reset and test functions,
may also be of use to the target.

DMA ACKNOWLEDGE

Input/ Active low. DACK is used in
conjunction with lOR or lOW to
enable reading or writing of the SCSI
Input and Output Data Registers
when in DMA mode. DACK resets
DRQ and must not occur simultaneously with CS.
EOP -

END OF PROCESS

Input/ Active low. This input is used
to indicate to the L5380 / 53C80 that a
DMA transfer is to be concluded. The
L5380/53C80 can automatically
generate an interrupt in response to
receiving EOP from the DMA controller.
RESET -

CPU BUS RESET

Input/ Active low. This input clears
all internal registers and state machines.
It does not result in assertion of the
RST signal on the SCSI bus and
therefore affects only the local L5380/
53C80 and not other devices on the
bus.
lOW -

I/O WRITE

Input/ Active low. lOW is used in
conjunction with CS and A2-O to
execute a memory mapped write of a
L5380/53C80 internal register. It is
also used in conjunction with DACK
to execute a DMA write of the SCSI
Output Data Register.

Inputs/ Active high. These signals, in
conjunction with CS, lOR, and lOW,
address the L5380 / 53C80 internal
registers for CPU read/write operations.
D7-O -

DATA 7-0

Bidirectional! Active high. These
signals are the microprocessor data
bus. D7 is the most significant bit.

The L5380/53C80 contains registers
that are directly addressed by the
microprocessor. These registers allow
for monitoring of SCSI bus activity,
controlling the operation of the
L5380/53C80, and determining the
cause of interrupts. In many cases, a
read-only and a write-only register are
mapped to the same address. Some
addresses are dummy registers which
are used to implement a control
operation but do not correspond to a
physical register. The state of the CPU
data bus when writing or reading
these dummy registers is 'don't care'.
Tables 1 and 3 show the address and
name of each register as well as bit
definitions.
Register Descriptions
A. Write Operations
The following paragraphs give
detailed descriptions of the function of
each bit in the L5380/53C80 internal
registers for write operations as
shown in Table 1.
WRITE ADDRESS 0
Output Data Register
The Output Data Register is a writeonly register used for sending information to the SCSI data bus. During
arbitration, the arbitrating SCSI device

asserts its ID via this register. The
device which wins arbitration also
asserts the "OR" of its ID and the ID
of the target/initiator to be selected/
reselected. In programmed I/O mode
this register is written using CS and
lOW with A2-D = 000. In DMA mode,
it is written when lOW and DACK are
simultaneously active, irrespective of
the state of the address lines. Note
that a "1" written to the Output Data
Register becomes a low state when
asserted on the active-low SCSI bus.

Rl Bit 7 - Assert RST

When this bit is set, the L5380 /53C80
asserts the RST line on the SCSI bus,
initializing all devices on the bus to
the reset condition. All logic and
internal registers of the L5380 /53C80
are reset, except for the Assert RST bit
itself, the Testmode bit (Rl bit 6) and
the IRQ (interrupt request) latch. The
IRQ pin becomes active indicating a
SCSI bus reset interrupt. This interrupt is not maskable.
Rl Bit 6 -

Testmode

When this bit is set, the L5380/53C80
places all outputs, including both SCSI
and CPU signals, in a high impedance
state. This effectively removes the
device from the system as an aid to
system diagnostics. Note that internal
registers may still be written to while
in Testrnode. The L5380/53C80
returns to normal operation when
Testmode is reset. The Testmode bit is
reset by either writing a "0" to Rl bit 6

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L5380/53C80

-~---

DEVICES INCORPORATED

or via the RESET (CPU reset) pin.
Testmode is not affected by the RST
(SCSI bus reset) signal, or by the
Assert RST bit in the Initiator Command Register (R1 bit 7).

Rl Bit 5 - Not Used
Rl Bit 4 - Assert ACK
When this bit is set, ACK is asserted
on the SCSI bus. Resetting this bit
deasserts ACK. Note that ACK will
be asserted only if the Targetmode bit
(R2 bit 6) is reset, indicating that the
L5380/53C80 is acting as an initiator.

Rl Bit 3 - Assert BSY
When this bit is set, BSY is asserted on
the SCSI bus. Resetting this bit deasserts BSY. BSY is asserted to indicate
that the device has been selected or
reselected, and deasserting BSY causes
a bus free condition.

Rl Bit 2 - Assert SEL
When this bit is set, SEL is asserted on
the SCSI bus. Resetting this bit deasserts SEL. SEL is normally asserted
after a successful arbitration.

Rl Bit 1 - Assert ATN
When this bit is set, A TN is asserted
on the SCSI bus. Resetting this bit
deasserts ATN. ATN is asserted by
the initiator to request message out
phase. Note that ATN will be asserted
only if the Targetmode bit (R2 bit 6) is
reset, indicating that the L5380 / 53C80
is acting as an initiator.

Rl Bit 0 - Assert Data Bus
When this bit is set, the open drain
SCSI data bus and parity drivers are
enabled and the contents of the
Output Data Register are driven onto
the SCSI data lines. In addition to the
Assert Data Bus bit, enabling of the
SCSI bus drivers requires one of the
following two sets of conditions:
When the L5380/53C80 is operating
as an initiator, the Targetmode bit
(R2 bit 6) must be reset, the 1;0 pin
must be negated (initiator to target

SCSI Bus Controller
transfer) and no phase mismatch
condition can exist. A phase mismatch occurs when the MSG, C/D,
and 1;0 bits of the Target Command
Register (R3) do not match the corresponding SCSI control lines.
When the L5380/L53C80 is operating
as a target, the Targetmode bit will be
set, and in this case Assert Data Bus
will enable the outputs unconditionally.
The Assert Data Bus bit need not be
set for arbitration to occur; when the
Arbitrate bit (R2 bit 0) is set, and a bus
free condition is detected, the data bus
will be enabled for arbitration regardless of the state of the Assert Data Bus
bit.
Finally, note that the Testmode bit
(R1 bit 6) overrides all other controls,
including Assert Data Bus and Arbitrate, and disables all outputs.
WRITE ADDRESS 2
Mode Register
The Mode register is a read/write
register which provides control over
several aspects of L5380/53C80
operation. Programmed I/O or two
different types of DMA transfer may
be selected, initiator or target device
operation is accommodated, and
parity checking and interrupts may be
enabled via this register. The function
of each individual bit is described as
follows:
R2 Bit 7 -

Blockmode

This bit must be used in conjunction
with DMA Mode (R2 bit 1). It is used
to select the type of handshake
desired between the L5380 / 53C80 and
the external DMA controller. See
"L5380/53C80 Data Transfers" for a
complete discussion of the transfer
types supported.
R2 Bit 6 -

Targetmode

When Targetmode is reset, the device
will operate as an initiator. This
enables the SCSI signals ATN and
ACK to be asserted. Targetmode also
affects state machine operation for
DMA transfers and the conditions
necessary for enabling the SCSI Data
bus drivers. (See Assert Databus,
R1 bit 0).
R2 Bit 5 -

Enable Parity Check

When this bit is set, information
received on the SCSI data bus is
checked for odd parity. The Parity
Error latch will be set whenever data
is received under DMA control or the
Current SCSI Data Register (Read
Register 0) is read by the CPU. The
state of the Parity Error latch can be
determined by reading R5 bit 5, and it
can be reset by a read to Address 7.
Note that ENABLE PARITY CHECK
must be set if parity error interrupts
are to be generated. This interrupt can
be separately masked by the Enable
Parity Interrupt bit (R2 bit 4) while
retaining the state of the Parity Error
latch for later examination by the

cpu.

R2 Bit 4 -

Enable Parity Interrupt

When this bit is set, the L5380/53C80
will set the interrupt request latch,
and assert IRQ (interrupt request) if it
detects a parity error. Enable Parity
Check (R2 bit 5) must also be set if
parity error interrupts are desired.
R2 Bit 3 -

Enable End Of OMA

Interrupt
When this bit is set, the L5380 / 53C80
will set the interrupt request latch,
and assert IRQ (interrupt request) if it
detects a valid EOP (End of Process)
signal. EOP is normally generated by
a DMA controller to indicate the end
of a DMA transfer. EOP is valid only
when coincident with lOR or lOW and
DACK.

When this bit is set, the L5380 /53C80
will operate as a SCSI target device.
This enables the SCSI signals 1/0,
C/D, MSG, and REQ to be asserted.

====================== Peripheral Products
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DEVICES INCORPORATED

SCSI Bus Controller

R2 Bit 2 - Monitor Busy
When this bit is set, the L5380/53C80
continuously monitors the state of the
BSY signal. Absence of BSY for a
period longer than 400 ns (but less than
1200 ns) will cause the L5380 /53C80 to
set the BSYERR and IRQ (interrupt
request) latches. In addition, the six
least significant bits of the Initiator
Command Register are reset, and all
SCSI data and control outputs are
disabled until the BSYERR latch is reset.
This effectively discounects the L5380/
53C80 from the SCSI bus in response to
an unexpected discounect by another
device. It also allows the CPU to be
interrupted when the SCSI bus becomes
free in systems where arbitration is not
used and an EOP signal is not available.

R2 Bit 1 - DMA Mode
When this bit is set, the L5380 / 53C80's
internal state machines automatically
control the SCSI signals REQ and ACK
(as appropriate for initiator or target
operation) and the CPU signals DRQ
and READY. DMA Mode must be set
prior to starting a DMA transfer in
either direction. The DMA Mode bit is
reset whenever a bus free condition is
detected (BSY is not active). This aborts
DMA operations when a loss of BSY
occurs, regardless of the state of the
Monitor Busy bit (R2 bit 2.) The DMA
Mode bit is not reset when EOP is
received, but must be specifically reset
by the CPU. EOP does, however,
inhibit additional DMA cycles from
occurring.
R2 Bit 0 - Arbitrate

This bit is set to indicate a desire to
arbitrate for use of the SCSI bus. Before
setting the Arbitrate bit, the SCSI
Output Data Register (Write Register 0)
must be written with the SCSI ID
assigned to the arbitrating SCSI device.
The bit position of register RO which is
set represents the priority number of
the SCSI device, with bit 7 the highest
priority. See the section on "Arbitration" for a full discussion of the L5380/
53C80 arbitration procedure.

. ...•...

Address 0 -

7

........................................

......

}...

...

•..........•

) ..... ......................

; ..

Output Data Register

3

2

o

Initiator Command Register
6
5
4
3

2

o

765

Address 1 -

...•..... ... .......•..•

ASSERT TEST
RST
MODE

4

ASSERT ASSERT ASSERT ASSERT ASSERT
ACK
BSY
SEL
ATN
DATA
BUS

Address 2 - Mode Register

7

5

6

3

4

BLOCK TARGET ENABLE ENABLE ENABLE
MODE MODE PARITY PARITY EODMA
CHECK INT'RPT INT'RPT

2

MaN 1TOR
BUSY

0

DMA
MODE

ARBITRATE

Address 3 - Target Command Register

7

6

5

4

LAST
BYTE
SENT

3

2

o

ASSERT ASSERT ASSERT ASSERT
REO
MSG
CID
TIO

Address 4 -10 Select Register

4

3

2

o

4

3

2

o

3

2

o

Start DMA Initiator Receive
6
5
4
3

2

o

765

Address 5 - Start DMA Send

7

Address 6 -

7

Address 7 -

7

6

5

Start DMA Target Receive

6

5

4

======================= Peripheral Products
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-------.......----- - ----.

-

L5380/53C80

DEVICES INCORPORATED

WRITE ADDRESS 3
Target Command Register
The Target Command Register is a
read/write register which allows CPU
control of the SCSI signals asserted by
the target. In addition, this register
contains a read-only status flag useful
in unambiguously determining when
the last byte of a DMA transfer has
actually been sent over the SCSI bus.

SCSI Bus Controller
R3

Bit 1 - Assert

e/D

When this bit is set, C/D is asserted
on the SCSI bus. Resetting this bit
deasserts C/D. Note that C/D will be
asserted only if the Targetmode bit
(R2 bit 6) is set, indicating that the
L5380 / 53C80 is acting as a target.
When operating as an initiator, this bit
is compared against the C/D input,
and an interrupt is generated if they
differ at the falling edge of REQ.

When operating as an initiator with
DMA mode set, the Assert MSG,
R3 Bit a- Assert 7/0
Assert C/D, and Assert Y!O bits are
When
this bit is set, I/o is asserted on
used as a template to compare against
the
SCSI
bus. Resetting this bit
the corresponding SCSI control signals
deasserts Va. Note that Va will be
provided by the target. A phase
asserted only if the Targetrnode bit
mismatch interrupt will be generated
on the falling edge of the REQ input if (R2 bit 6) is set, indicating that the
L5380 / 53C80 is acting as a target.
the template does not match the state
When operating as an initiator, this bit
of the signals. Therefore the CPU
should initialize these bits to the phase is compared against the I/o input,
and an interrupt is generated if they
of the expected data transfer. An
interrupt, then, will signal an intent by differ at the falling edge of REQ.
the target to change to a new phase.
WRITE ADDRESS 4
The SCSI information transfer phases
ID Select Register
and their associated direction of data
The ID Select Register is a write-only
transfer are given in Table 2.
register which is used to monitor
R3 Bits 7-4 - Not Used
selection or reselection attempts to the
L5380/53C80. In arbitrating systems,
R3 Bit 3 - Assert REQ
an ID number is assigned to each SCSI
When this bit is set, REQ is asserted
device by setting a single bit position
of the ID Select Register. Each SCSI
on the SCSI bus. Resetting this bit
deasserts REQ. Note that REQ will be data pin is inverted and compared
asserted only if the Targetmode bit
with the corresponding bit in the ID
Select Register. If any matches are
(R2 bit 6) is set, indicating that the
found while a bus free condition exists
L5380 /53C80 is acting as a target.
R3

and SEL is active, the L5380/53C80
will generate an interrupt to indicate a
selection or reselection. During
selection or reselection, parity checking may be enabled by setting the
Enable Parity Check bit (R2 bit 5). This
interrupt may be masked by resetting
all bits in this register.
WRITE ADDRESS 5
Start DMA Send
This is a dummy register. Writes to
this location are detected and cause
the L5380 / 53C80 internal state
machine to execute a DMA send
operation. This location is used for
either initiator or target DMA send.
The DMAMODE bit (R2 bit 1) must be
set prior to writing this location.
WRITE ADDRESS 6
Start DMA Target Receive
This is a dummy register. Writes to
this location are detected and cause
the L5380/53C80 internal state
machine to execute a target DMA
receive operation. The DMAMODE
bit (R2 bit 1) and the Targetmode bit
(R2 bit 6) must be set prior to writing
this location.
WRITE ADDRESS 7
Start DMA Initiator Receive
This is a dummy register. Writes to
this location are detected and cause
the L5380/53C80 internal state
machine to execute an initiator DMA

Bit 2 - Assert MSG

When this bit is set, MSG is asserted
on the SCSI bus. Resetting this bit
deasserts MSG. Note that MSG will
be asserted only if the Targetrnode bit
(R2 bit 6) is set, indicating that the
L5380 /53C80 is acting as a target.
When operating as an initiator, this bit
is compared against the MSG input,
and an interrupt is generated if they
differ at the falling edge of REQ.

MSG CID 1/0

0

0

0

0

0

0

Direction

Message In

Target
Initiator

1

Message Out

0

Unused

0

Status In

1

Command

Initiator

0

Data In

Target

Data Out

Initiator

0
1

Phase

IT
IT

Initiator
Target

Unused

0
0

Target

IT
IT
IT
IT

Initiator
Target
Initiator
Target

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DEVICES INCORPORATED

receive operation. The DMAMODE
bit (R2 bit 1) must be set and the
Targetmode bit (R2 bit 6) must be
reset prior to writing this location.
B. READ OPERA nONS

SCSI Bus Controller
it indicates that the L5380/53C80 has
detected a bus free condition and is
currently arbitrating for control of the
bus. See the section on "Arbitration"
for a complete discussion of the
L5380/53C80 arbitration mechanism.
Resetting the Arbitrate bit will reset
ARBITRATION IN PROGRESS.

The following paragraphs give
detailed descriptions of the function of
Rl Bit 5 - Lost Arbitration
each bit in the L5380/53C80 internal
registers for read operations as shown For this bit to be active, the Arbitrate
in Table 3.
bit (R2 bit 0) must be set. When LOST
ARBITRATION is set, it indicates that
READ ADDRESS 0
the L5380 /53C80 has arbitrated for
Current SCSI Data Bus
the SCSI bus (see R1 bit 6 above) and
The Current SCSI Data Bus Register
has detected the assertion of SEL by
allows the microprocessor to monitor
another (higher priority) device. The
the SCSI data bus at any time, by
L5380 / 53C80 responds to loss of
asserting CS and lOR with address
arbitration by immediately disconlines A2-D = 000. The SCSI data lines
tinuing the arbitration attempt.
are not actually registered, but gated
Resetting the Arbitrate bit will reset
directly onto the CPU bus whenever
LOST ARBITRATION.
Address 000 is read by the CPU.
READ ADDRESS 2
Therefore, reads of this location
Mode Register
should only be done when the SCSI
data lines are guaranteed to be stable
Reading the Mode Register simply
by the SCSI protocol. For systems
reflects the status of the bits in that
which implement SCSI bus arbitraregister.
tion, this location is read to determine
READ ADDRESS 3
whether devices having higher
priorities are also arbitrating. Program- Target Command Register
med I/O data transfer uses this
Reading the Target Command Regislocation for reading data transferred
ter simply reflects the status of the
on the SCSI data bus. With parity
bits in that register, except for bit 7,
checking enabled, SCSI data bus
LAST BYTE SENT.
parity checking is done at the beginning of the read cycle for fast error
R3 bit 7 - Last Byte Sent
detection. Note that the SCSI data bus
This read only bit indicates that the
is inverted to become active high
last byte of data loaded into the
when presented to the CPU.
L5380/53C80 during a DMA send
READ ADDRESS 1
operation has actually been transInitiator Command Register
ferred over the SCSI bus. Note that
the end of process flag and the correReading bit 7 or bits 4-0 of the Initiator Command Register simply reflects sponding interrupt occur when this
byte is loaded into the L5380/53C80,
the status of the corresponding bit in
but
do not reflect whether it has
the register. Bits 6 and 5 are mapped
actually been sent. This bit is not
to other signals as discussed below:
present in the NCR5380, but is present
Rl Bit 6 - Arbitration In Progress
in the NCR53C80. Last Byte Sent is
reset when the DMAMODE bit
For this bit to be active, the Arbitrate
(R2 bit 1) is reset.
bit (R2 bit 0) must be set. When
ARBITRATION IN PROGRESS is set,

READ ADDRESS 4
Current SCSI Control Register
The Current SCSI Control Register
provides a means for the CPU to
directly monitor the state of the SCSI
bus control signals. The SCSI control
lines are not actually registered, but
gated directly onto the CPU bus
whenever Address 100 is read by the
CPU. The value of each bit position
represents the complement of the corresponding (low true) SCSI Signal Pin.
READ ADDRESS 5
DMA Status Register
The DMA Status Register provides a
means for the CPU to determine the
status of a DMA transfer and to
determine the cause of an interrupt. It
also makes available the final two
SCSI bus signals which are not
included in the Current SCSI Control
Register. The function of each individual bit is defined as follows:
R5 Bit 7 -

End of DMA

When this bit is set, it indicates that a
valid EOP has been received during a
DMA transfer. A valid EOP occurs
when EOP, DACK, and either lOR or
lOW are simultaneously active for the
minimum specified time. End of
DMA is reset when the DMAMODE
bit (R2 bit 1) is reset.
Note that for DMA send operations,
an END OF DMA status indicates
only that the last byte of the transfer is
loaded into the Output Data Register
of the sending device, not that it has
actually been transferred over the
SCSI bus. For this reason, the L5380/
53C80 provides an additional status
bit; Last Byte Sent (R3 bit 7) which
indicates that this final byte has been
transferred to the receiving end. This
bit is not present in the NCR5380.
Also, note that the DMAMODE bit is
reset automatically whenever a loss of
busy condition is detected, which in
turn resets END OF DMA. Therefore

======================= Peripheral Products
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6

-- - -

- -...-.-.
.-_..-__-...-.-.
----- ........ - --

L5380/53C80

DEVICES INCORPORATED

the DMA Status Register should be
read prior to resetting the Assert BSY
bit (R1 bit 3) at the conclusion of a
DMA transfer.
R5 Bit 6 -

7

I

SOB?

I

5

3

4

2

SOB61 SOB51 SOB41 SOB31 SOB2

7

0

Address 2 -

3

4

3

4

5

6

Address 4 -

0

DMA
MODE

ARBITRATE

3

2

0

Current SCSI Control Register

7

I

4

5

6
BSY

Address 5 -

I

REO

I

MSG

6

5

4

END
OF
DMA

DMA
REO.

PARITY
ERROR

INTERRUPT
REO.

Address 6 -

7

2

C/O

T/o

3

2

PHASE BUSY
MATCH ERROR

5

4

3

SOB61 SOB51 SOB41 SOB3

Address 7 -

0
SEL

I

PARITY

I

0

ATN

ACK

Input Data Register

6

I

I

3

DMA Status Register

7

7

2

MONITOR
BUSY

ASSERT ASSERT ASSERT ASSERT
C/D
I/O
REO
MSG

LAST
BYTE
SENT

SOB?

0

Target Command Register

7

I

2

ASSERT ASSERT ASSERT ASSERT ASSERT
BSY
ACK
SEL
ATN
DATA
BUS

5

6

Address 3 -

Phase Match

When this bit is set, it indicates that
the MSG, C/D, and 1;0 lines match
the state of the Assert MSG, Assert
C/D, and Assert 1;0 bits in the Target
Command Register. PHASEMATCH
is not actually registered, but represents a continuous comparison of
these three phase bits to the corresponding internal register locations.
This bit is intended for use by the

4

5

LOST
ARB.

BLOCK TARGET ENABLE ENABLE ENABLE
MODE MODE PARITY PARITY EODMA
CHECK INT'RPT INT'RPT

RST

SOBo

Mode Register

7

I

SOB1

Initiator Command Register

6

ASSERT ARB. IN
RST
PROGRESS

Interrupt Request

This bit reflects the state of the IRQ
signaL The L5380/53C80 asserts IRQ
to generate an interrupt to the CPU.
See the section on "Interrupts" for
further information on the possible
sources of interrupts in the L5380/
53C80. INTERRUPT REQUEST can be
reset by a read to the Reset Error /
Interrupt Register (Register 7).
R5 Bit 3 -

Current SCSI Data Bus

6

Address 1 -

Parity Error

This bit can only be set if Enable
Parity Check (R2 bit 5) is set. When
enabled, the Parity Error bit is set if
incoming SCSI data in either initiator
or target mode, or during selection
phase, does not correctly reflect odd
parity. PARITY ERROR can be reset
by a read to the Reset Error /Interrupt
Register (Register 7).
R5 Bit 4 -

Address 0 -

DMA Request

This bit reflects the state of the DRQ
(DMA Request) signaL In programmed I/O, this bit can be polled by the
CPU to determine whether there is a
pending request for byte transfer.
For DMA send operations, DMA
REQUEST is reset when DACK and
lOW are simultaneously asserted. For
DMA receive operations, simultaneous DACK and lOR will reset DMA
REQUEST. DMA REQUEST is reset
unconditionally when the
DMAMODE bit (R2 bit 1) is reset.
R5 Bit 5 -

SCSI Bus Controller

0

2
SOB2

SOB1

SOBo

Reset Error/Interrupt Register

5

6

4

3

2

0

====================== Peripheral Products
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06/23/95-LOS.5380-G

------ -----------.-

L5380/53C80

-

--.-.---~
-~---

DEVICES INCORPORATED

initiator to detect that the target
device has changed to a different
information transfer phase. When the
L5380/53C80 detects a phase mismatch, PHASEMATCH is reset, and
information transfer to or from the
SCSI bus is inhibited.
RS Bit 2 -

Busy Error

This bit can only be set if the Monitor
Busy bit (R2 bit 2) is set. When set,
Busy Error indicates that the BSY pin
has been false for a period at least
equal to a bus settle delay (400 ns).
When the Busy Error condition is
detected, all SCSI signal pins are
disabled, and the DMAMODE bit
(R2 bit 1) and bits 5-0 of the Initiator
Command Register are reset. Busy
Error can be reset by a read to the
Reset Error /Interrupt Register
(Register 7).
RS Bits 1,0 - ATN, ACK

Like the Current SCSI Control Register, these bits provide a means for the
CPU to directly monitor the state of
the SCSI bus control signals. The SCSI
control lines are not actually registered, but gated directly onto the CPU
bus whenever Address 5 is read by
the CPU. The value of each bit
position represents the complement of
the corresponding (low true) SCSI
Signal Pin.
READ ADDRESS 6
Input Data Register
This register acts as a temporary
holding register for information
received from the SCSI data bus during DMA transfers (DMAMODE bit,
R2 bit 1 is set). In the initiator mode,
the L5380/53C80 latches the SCSI data
when REQ goes active. In the target
mode, data is latched when ACK goes
active. The contents of this register
represent the negation of the low-true
SCSI data. The contents of the SCSI
Input Data Register are gated onto the
CPU data bus when DACK and lOR
are simultaneously true, or by a CPU
read of location 6. Note that DACK
and CS must never be active simulta-

SCSI Bus Controller
neously in order to prevent conflicting
read operations. Parity may optionally be checked on the data as it is
loaded into this register.

SCSI Bus Reset Interrupt

A SCSI Bus Reset Interrupt occurs
when the SCSI RST signal becomes
active. This may be due to another
SCSI device driving the RST line, or
READ ADDRESS 7
because the Assert RST bit (R1 bit 7)
Reset Error/Interrupt Register
has been set, causing the L5380/53C80
This is a dummy register. Reads to
to drive the SCSI RST line. The value of
this location are detected and used to
the SCSI RST line is visible as R4 bit 7;
reset the Interrupt Request Latch (IRQ however, this line is not latched and
signal) and the PARITY ERROR,
therefore may have changed state by
INTERRUPT REQUEST, and BUSY
the time the CPU responds to the
ERROR latches (visible as bits 5, 4, and interrupt and polls this location. For
2 of Register 5).
this reason, a SCSI Bus Reset Interrupt
should be assumed if no other interINTERRUPTS
rupt condition is active when reading
The L5380/53C80 generates interrupts Registers 4 and 5.
to the CPU by setting the Interrupt
The SCSI Bus Reset Interrupt is
Request Latch, which directly drives
nonmaskable. The expected read
the IRQ (Interrupt Request) line. The
values for the Current SCSI Control
IRQ output will reflect the state of the Register and the DMA Status Register •
Interrupt Request Latch under all
upon encountering this interrupt are
conditions except when Testmode
given in Table 4.
(R1 bit 6) is active, when it is in a high
SelectionlReselection Interrupt
impedance state. The Interrupt
Request Latch may be reset by reading A Selection/Reselection Interrupt
Address 7, the Reset Error /Interrupt
occurs when the SCSI SEL signal
Register. A read of this location also
becomes active, the SCSI bus matches
resets several error condition latches
the bit set in the ID Select Register,
as discussed in the section on "Interand BSY has been false for at least a
nal Registers".
bus settle delay. When the I;o pin is
Interrupts may be caused by any of six
conditions, most of which may be
masked by resetting enable bits in the
appropriate registers. The following
sections describe each interrupt type,
its cause, and how it may be reset.
Upon receiving an interrupt, the CPU
may read the Current SCSI Control
Register (R4) and the DMA Status
Register (R5) to determine the cause of
the interrupt. While the following
discussions indicate the expected
values of these registers following an
interrupt, it is recommended that bits
in these registers which are not
germane to determining the cause of
an interrupt be masked off in firmware prior to implementing a comparison. A typical operational sequence for
an interrupt service routine is given at
the end of this section.

asserted, the interrupt should be
interpreted as a reselection. The
Selection/Reselection Interrupt may
be masked by resetting all bits in the
ID Select Register. The expected read
values for the Current SCSI Control
Register and the DMA Status Register
upon encountering this interrupt are
given in Table 4.
Loss of Busy Interrupt
A Loss of Busy Interrupt occurs when
the SCSI BSY signal has been inactive
for at least a bus settle delay (400 ns).
The Loss of Busy Interrupt may be
masked by resetting the Monitor Busy
bit (R2 bit 2). Resetting Monitor Busy
also prevents the Busy Error latch
(Read R5 bit 2) from being set. The
expected read values for the Current

======================= Peripheral Products
6-11

06123195-LDS.5380·G

•

- --- --------------- - ---~---

-

L5380/53C80

DEVICES INCORPORATED

SCSI Control Register and the DMA
Status Register upon encountering
this interrupt are given in Table 4.
Phase Mismatch Interrupt
A Phase Mismatch Interrupt occurs
when the DMAMODE bit (R2 bit 1) is
set, REQ is active on the SCSI bus, and
the SCSI phase signals MSG, C/D,
and I/O do not match the corresponding bits in the Target Command
Register. This interrupt is intended
for use by the initiator to detect a
change of phase by the target during a
DMA transfer. When operating as a
target, the SCSI phase lines will
normally be asserted via the Target
Command Register, so no phase
mismatch will be generated unless
another SCSI device is erroneously
driving the phase lines to an unintended state.
The result of the continuous comparison of the SCSI phase lines to the
Target Command Register contents is
visible as the Phase Match bit (Read
R5 bit 3). This flag operates irrespective of the state of DMAMODE and
REQ. As long as a phase mismatch
condition persists, the L5380/53C80 is
prevented from recognizing active
REQ inputs, and SCSI output data
drivers are disabled.
The Phase Mismatch Interrupt is
nonmaskable, however it will only
occur when operating in DMAMODE.
The expected read values for the
Current SCSI Control Register and the
DMA Status Register upon encountering this interrupt are given in Table 4.
Parity Error Interrupt
A Parity Error Interrupt occurs when
incorrect parity is detected during a
read of the SCSI bus. Parity checking
occurs under the following conditions:
Parity is checked during a programmed I/O read of the Current SCSI
Data Register (Read RO), when CS and
lOR are active and the A2-0 lines are
000. Parity is also checked during

SCSI Bus Controller
DMA read operations (DMAMODE
bit, R2 bit 1 is set) when ACK is active
for target receive, or REQ is active for
initiator receive.

•

~;;;.

!

Read Address 4 -

The Parity Error latch is set when
parity error checking is enabled and
one of the above parity error conditions is encountered. This latch is
:.;;;;;;;,.5,;.';;

; ..;.

Current SCSI Control Register

7

6

5

4

3

2

1

0

RST

BSY

REO

MSG

c/o

I/O

SEL

PARITY

0

0

0

0

0

X

X

1=RESEL

1

X

0

0

0

0

0

X

X

X

0

X

X

X

X

X

X

X

X

X

0

X

2

1

0

ATN

ACK

SCSI Bus Reset Interrupt

X

0

0

Selection/Reselection Interrupt

0

0

0

Loss of Busy Interrupt
0

0

0

Phase Mismatch Interrupt

0

1

1

Parity Error Interrupt

0

X

X

End of DMA Interrupt

0

X

1

Read Address 5 -

DMA Status Register

5

7

6

END
OF
DMA

DMA
REO

4

PARITY INTERERROR RUPT
REO

3

PHASE BUSY
MATCH ERROR

SCSI Bus Reset Interrupt

0
0
1
0
Selection/Reselection Interrupt
0

0

0

1

0

0

0

1

X

0

X

0

1

X

1

0

0

1

0

X

X

0

1

X

X

X

X

1

X

0

0

X

Loss of Busy Interrupt
0

0

0

Phase Mismatch Interrupt

0

0

0

Parity Error Interrupt

X

X

1

End of DMA Interrupt

1

0

0

====================== Peripheral Products
6-12

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-

.......

-II. :--Sr=
.....
U • ..,-

L5380/53C80

DEVICES INCORPORATED

visible as bit 5 of the DMA Status
Register (Read R5). The Parity Error
Interrupt may be masked and setting
of the Parity Error latch prevented by
resetting the Enable Parity Check bit
(Write R2 bit 5). The Parity Error latch
can be reset by reading the Reset
Error /Interrupt Register (Read R7).
The expected read values for the
Current SCSI Control Register and the
DMA Status Register upon encountering this interrupt are given in Table 4.
End of DMA Interrupt
An End of DMA Interrupt occurs
when a valid EOP (End of Process)
signal is detected during a DMA
transfer. EOP is valid when EOP,
DACK, and either lOR or lOW are
simultaneously asserted for the minimum specified time. EOP inputs not
occurring during I/O read or write
operations are ignored.
The End of DMA latch is set whenever
the DMAMODE bit (R2 bit 1) is set
and a valid EOP is received. This
latch is visible as bit 7 of the DMA
Status Register (Read RS). The End of
DMA Interrupt may be masked by
resetting the Enable EODMA Interrupt bit (Write R2 bit 3). This bit does
not affect the End of DMA latch,
however. The End of DMA latch can
be reset by resetting the DMAMODE
bit in the Mode Register. The expected
read values for the Current SCSI
Control Register and the DMA Status
Register upon encountering this
interrupt are given in Table 4.
DATA TRANSFERS
The L5380/53C80 supports programmed I/O under CPU control or DMA
transfer via a DMA controller when
transferring information to and from
the SCSI data bus. Programmed I/O
can be implemented entirely in
firmware or using minimum external
logic for accessing the appropriate
registers. Under DMA control, the
L5380/53C80's DMA interface logic
and internal state machines provide

SCSI Bus Controller
the necessary control of the REQ-ACK
handshake. Each type of transfer is
fully described in the following
sections.
Programmed 1/0
Two forms of programmed I/O are
supported by the L5380/53CBO. For
normal programmed I/O, the SCSI
handshake is accomplished by setting
bits in the Initiator or Target Command registers to assert SCSI control
lines, and polling the Current SCSI
Control and DMA Control registers
for the appropriate responses. Since
for this method the control is contained
in firmware, the cycle times are
relatively slow. It is most appropriate

for transferring small blocks of data
such as SCSI command blocks or
messages, where the overhead of
setting up a DMA controller could
be significant.
PseudoDMA
An alternate method of programmed
I/O allows the state machines of the
L5380 / 53C80 to handle the SCSI
handshake, thereby improving
performance in systems which do not
employ a hardware DMA controller.
To implement Pseudo DMA, the
DMAMODE bit is set. The CPU polls
the DRQ bit in the DMA Control
Register to determine when a byte
should be written to or read from the

Read Address 5 > TEMP
: Read DMA Status Reg to variable TEMP •
r-------------;
IF TEMP" AND" HEX (10) = 0
THEN GO TO NEXT DEVICE

: IRQ not active, so L53BO/L53CBO
was not the source of this interrupt

TEMP" AND" HEX (AC) ..... TEMP : Mask off irrevelant bits
IF TEMP> HEX (7F) THEN
GOTO EODMA

: End of DMA Interrupt

IF TEMP> HEX (1 F) THEN
GOTO PARERR

: Parity Error Interrupt

IF TEMP> HEX (03) THEN
GO TO BYSERR

: Loss of Busy Interrupt

IF TEMP = HEX (00) THEN
GO TO PHASERR

: Phase Mismatch Interrupt

Read Address 4 ..... TEMP

: Read Current SCSI Control Reg
to variable TEMP

TEMP "AND" HEX (06) ..... TEMP : Mask off irrevelant bits
IF TEMP = HEX (06) THEN
GOTORESEL

: Reselection Interrupt

IF TEMP = HEX (02) THEN
GOTOSEL

: Selection Interrupt

IF TEMP = HEX (00) THEN
GO TO RESET

: SCSI Bus Reset Interrupt

======================= Peripheral Products
6-13

06l23/95-LDS.5380·G

•

---- -- -----

--- -........------ -

-....-.-~

-

L5380/53C80

DEVICES INCORPORATED

L5380/53C80. When reading or
writing, external logic must be used to
decode the L5380/53C80 location and
produce DACK, since it is used by the
internal state machines. Also, CS
must be suppressed since it may not
be asserted simultaneously with
DACK.
Normal DMA Mode
Normal DMA mode is obtained when
the DMAMODE bit is set but the
Blockmode bit is reset. The DMA
process is started by writing to the
Start DMA Send, Start DMA Initiator
Receive, or Start DMA Target Receive
locations as appropriate. Once
started, the internal state machines of
the L5380/53C80 manage the REQACK handshake protocol, as well as
the DRQ-DACK handshake with the
DMA controller.
The L5380/53C80 will assert DRQ
whenever it is ready to transfer a byte
to or from the DMA controller. In
response to DRQ, the controller asserts
DACK and lOR to read the byte, or
DACK and lOW to write a byte to the
L5380/53C80. For write operations,
the byte is latched at the rising edge of
the logical AND of DACK and lOW.
The transfer can be terminated by
asserting EOP during a read or write
operation, or by resetting the
DMAMODE bit.
Block DMA Mode
When the Blockmode bit is set, the
DMA handshake is no longer dependent on interlocked DRQ-DACK cycles.
Instead, the DMA controller may be
allowed to free-run, with data flow
throttled by inserting "wait-states" in
the DMA transfer to or from the
L5380/53C80. Wait-states, which are
idle clock cycles inserted during the
I/O read or write operation, are
inserted by the DMA controller until
the READY output of the L5380/
53C80 goes true, allowing the bus
cycle to conclude.

SCSI Bus Controller
The READY output will be deasserted
under the following conditions: For
send operations, READY will be false
whenever the Output Data Register
contains a byte which has not been
transferred over the SCSI bus. This
allows the DMA controller to access
RAM to fetch the next byte, but
postpones the end of the CPU bus
cycle until the previous byte has been
transferred, freeing the Output Data
Register to receive it.
For receive operations, READY will be
false whenever the Input Data Register is empty. This allows the DMA
controller to address the RAM for a
write operation, but postpones the
end of the CPU bus cycle until the
incoming byte is stored in the Input
Data Register and is available on the
CPU bus.
Note that when blockmode is
employed, DACK may optionally
remain asserted throughout the DMA
transfer, since it is not used in an
interlocked DMA handshake (Its
interlock function is replaced by lOR
or lOW). Also, DRQ will be asserted
in the normal way when operating in
blockmode. To gain the abovementioned performance benefits, it should
be used only to initiate the first byte
transfer, with READY used to throttle
succeeding transfers. This methodology is compatible with DMA controllers such as the Intel 8237 and AMD
Am9516/9517.
In summary, blockmode operation
offers the potential for improved
transfer rates by overlapping the
DMA memory access with the SCSI
transfer. This is of particular value
when used with DMA controllers
capable of "flyby" operation, where
the data is transferred directly from
memory to the peripheral, and does
not pass through the DMA controller
itself. This transfer rate gain is
achieved at the expense of locking up
the CPU bus for a time equal to the
SCSI transit time of the entire block.

This may be strongly preferable in
some systems where net disk access
time is a crucial performance factor.
Also, the time required to arbitrate for
the CPU bus on a byte-by-byte basis
may well be longer than the cycles
wasted waiting for SCSI transfers to
take place, especially with fast
peripherals which operate from a
high speed sector buffer.
Terminating DMA Transfers
DMA transfers, either normal or
blockmode, may be terminated in a
number of ways. The following
sections describe these methods,
along with providing information
about correct sequencing of various
signals to effect a clean exit from a
DMA process.
EOP Signal
The EOP signal is usually generated
by a DMA controller to indicate that
its transfer counter has decremented
to zero. In order to be recognized by
the L5380/53C80, it should be asserted
simultaneously with the DACK and
lOR or lOW signals corresponding to
the last byte in the transfer. Note that
in the case of send operations, asserting EOP indicates to the L5380/53C80
that SCSI transfers should cease after
transmission of the byte loaded while
EOP is asserted. In order to determine when this last byte has actually
been sent, the Last Byte Sent flag in
the Target Command Register may be
examined. This flag is not present in
the NCR implementation of the 5380,
but is available in the 53C80, a nonpin-compatible variant. The EOP
input does not reset the DMAMODE
bit, but after transmission of the last
byte causes the internal state machine
to return to an idle condition, so that
no further SCSI handshaking will
occur until another transmission is
explicitly initiated. Note that the
NCR version of the 5380, upon
receiving an EOP, will stop asserting
DRQ, but will continue to issue ACK
in response to additional REQ inputs,

=======================Peripheral Products
6·14

06/23/95-LDS.5380·G

-

-- ---------- -.......------

L5380/53C80

.-..-.,-,

DEVICES INCORPORATED

potentially causing data loss if the
target initiates another data transmission without an intervening phase
change. The L5380/53C80 prevents
this spurious DMA handshake from
occurring.
DMAModeBit
Resetting the DMAMODE bit in the
Mode Register causes a hard reset of
the internal DMA state machines, and
thus an effective termination of a
DMA transfer. Since unlike the EOP
case the state machine is not allowed
to exit gracefully, care must be taken
in the timing of DMAMODE reset.
For receive operations, the
DMAMODE bit should be reset after
the last DRQ is received, but prior to
asserting DACK to prevent an additional REQ or ACK from occurring.
For normal DMA mode, resetting this
bit will cause DRQ to go inactive.
However, the last byte received
remains in the SCSI Input Data
Register and may be read either by
the normal DACK and lOR DMA
read or using a CPU read of Address 6.
For blockmode DMA, READY will
remain asserted when DMAMODE is
reset, allowing the DMA controller to
retrieve the last byte in the normal
fashion. The NCR version of the 5380
fails to keep READY asserted when
DMAMODE is reset, potentially
causing deadlock on the CPU bus.
Bus Phase Mismatch
When operating in DMAMODE as an
initiator, a bus phase mismatch can be
used to terminate a data transfer. If the
C/D, I;0, and MSG lines fail to match
the corresponding bits in the Target
Command Register, it will prevent
recognition of REQ, and will disable the
SCSI data and parity output drivers.
Also, when REQ becomes active, an
interrupt will be generated. Because
REQ is not recognized, the effect is to
stop the DMA transfer, although the
state machine does not return to idle
until either DMAMODE is reset or a
valid EOP is received.

SCSI Bus Controller
One caution should be observed
when using phase changes to end
DMA transfers: While this method
does not require the initiator to keep a
transfer counter, it depends on the
target causing a phase change between
any two consecutive information
transfer phases. Since this is not
required by the protocol, it must be
guaranteed by the target software.
Otherwise the target may begin a new
information transfer without the
initiator recognizing the boundary
between the two.
ARBITRATION
The L5380/53C80 contains on-chip
hardware to assist in arbitrating for
the SCSI bus. This arbitration logic
cooperates with the host firmware to
effect SCSI arbitration, as described in
the following paragraphs:
The SCSI arbitration timeline begins
with detection of a bus free condition
at time to. Bus free is defined as BSY
and SEL inactive for at least a bus
settle delay (400 ns). Following the
bus settle delay, the SCSI device must
wait an additional bus free delay of
800 ns, for a total of 1200 ns after to,
prior to driving any signal. Thus a
minimum of 1200 ns must elapse from
initial deassertion of BSY to the beginning of an arbitration attempt. A final
constraint is that arbitration may not
begin if more than a bus set delay
(1800 ns) has elapsed since BSY
became active (arbitration began),
corresponding to 2200 ns after to.
The CPU indicates a desire to arbitrate by setting the Arbitrate bit
(R2 bit 0). When Arbitrate is set, the
L5380/53C80 will monitor the state of
BSY and SEL to detect a bus free
condition. The actual implementation
uses an internal delay line to provide
a time reference for detection of a bus
free condition. This delay is nominally 800 ns during which BSY and
SEL must be inactive. This time
represents the center of the window
between the Bus Settle Delay (400 ns)

and the Bus Free Delay (400 + 800 =
1200 ns). When Bus Free is detected,
the L5380/53C80 waits for an additional time of nominally 900 ns (1700 ns
nominal since to) and asserts BSY and
the contents of the Output Data
Register. This time represents the
center of the 1200 ns-2200 ns window
between the earliest and latest legal
arbitration attempt. Since the actual
delays are process and temperature
dependent, they will vary in practice,
but will always remain well within
the specified limits.
Once arbitration has begun (BSY and
the Output Data Register asserted,)
the Arbitration In Progress bit (Rl bit 6)
will be set, allowing the CPU to detect
the fact that arbitration has begun.
The CPU should then wait one
arbitration delay (2.2 Ils) before
reading the bus to determine whether •
arbitration has been won or lost. The
Lost Arbitration bit (R2 bit 7) will be
active if the L5380 /53C80 has detected
SEL active on the SCSI bus, indicating
that another SCSI device has declared
itself the winner of the arbitration.
SEL active also disables the SCSI
output drivers, allowing the winning
arbitrator to proceed with its transfer.
BUG FIXES/ENHANCMENTS
The NCR5380 and the Am5380 have
some architectural bugs, both published and unpublished. The LOGIC
Devices L5380/53C80 was designed to
eliminate these bugs while maintaining pin and architectural compatibility. A list of these errors along with
solutions implemented in the L5380/
53C80 is itemized below.
1. When executing blockmode DMA
send operations, the READY signal is
intended to insert memory wait states
as a mechanism to throttle data
transfer, with the DMA controller in a
free-running loop. The NCR/
Am5380 erroneously allows the
contents of the Output Data Register
to be overwritten by subsequent bytes
prior to acknowledgment of the

======================= Peripheral Products
6·15

06i23i9S-LDS.S380·G

•

-

-------------------- - --~---

L5380/53C80

DEVICES INCORPORATED

current byte by the SCSI receiver.
This causes loss of data when operating in blockmode if the sender's DMA
cycle is faster than the receiver's.
2. Assertion of EOP during
blockmode DMA transfers fails to
cause assertion of READY in the
NCR/ Am53S0. This may prevent the
CPU from becoming bus master and
can result in lockup of the CPU bus in
a not-ready state. In block DMA send
mode when EOP is received, the
L53S0 /53CSO reasserts READY
immediately after transmitting the
final byte. For receive mode, READY
is asserted immediately.
3. When a valid EOP is detected, the
NCR/ Am53S0 prevents assertion of
additional DRQ's, but continues to
respond to SCSI handshakes. This
means that additional data transmitted without phase change may be lost.
The L53S0/53CSO, like the NCR/
Am53S0 remains in DMAMODE after
an EOP. However, the internal state
machine returns to an idle condition
and does not respond to additional
SCSI handshake attempts until
another data transfer is explicitly
initiated.

SCSI Bus Controller
4. When operating as an initiator in
DMAMODE, the NCR/ Am53S0 leaves
ACK asserted after receipt of a valid
EOP, requiring the CPU to deassert it.
When a valid EOP is detected, the
L53S0/53C80 deasserts ACK properly.
5. If the NCR/ Am53S0 is not terminated on the SCSI side, the floating RST
pin will cause spurious interrupts. The
L5380 /53C80 contains internal high
value pullups to set unterminated SCSI
pins to the inactive state.
6. During DMA send operations, when
a valid EOP signal is received by the
NCR/ Am53S0, no convenient indication exists to indicate that the last byte
of data (loaded simultaneously with
EOP) has in fact been successfully
transmitted. The L5380/53C80 provides Last Byte status bit mapped to
bit 7 of the Target Command Register.
This bit will be set after a valid EOP has
occurred, and the final byte has been
transmitted successfully.
7. During the reselection phase, the
NCR/ AM53S0 may reset the reselection interrupt if the contents of the
Target Command Register do not
match the current SCSI bus phase. The
L5380 /53CSO does not spuriously reset
this interrupt.

S. In the NCR/ Am5380, the phase
mismatch interrupt is captured in an
edge triggered fashion on the active
edge of REQ. During reselection, this
interrupt might not be generated even
though a phase change has occurred.
The reason for this is as follows:
• The initiator DMAMODE bit
must be set in order to receive a
phase-match interrupt.
• However, the DMAMODE bit
cannot be set unless BSY is active.
• BSY will be driven active by the
target only after the relesection
has occurred.
• Once BSY has been asserted by
the target, it may then assert REQ
before the initia tor has set the
DMAMODE bit, and the initiator
will then fail to generate an
interrupt.
The L5380/53C80 interrupt latch will
be set if a phase mismatch condition
exists when the later of REQ or
DMAMODE become active. In this
way, the mismatch will always be
detected, even if the target asserts
REQ before the initiator sets
DMAMODE.

====================== Peripheral Products
6-16

06/23/95-LDS.5380·G

- --------- ---------- -.......------ -

-

L5380/53C80

DEVICES INCORPORATED

SCSI Bus Controller

Storage temperature .... .... ..... ..... ..... .... ... ........ .............. ....... ....... ..... ... ....... ..... ..... ... ..... ... ...... -65°C to + 150°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Output voltage .............................................................................................................................. 0.0 V to Vee
Input voltage ............................................................................................................................. 0.0 V to +5.5 V
IOL Low Level Output Current (SCSI Bus) ....................................................... ,..................................... 48 mA
IOL Low Level Output Current (other pins) ............................................................................................... 8 mA
IOH High Level Output Current (other pins) ............................................................................................ -4 mA

~~~~~'i"IN~Cj6NDI'i"i()NS··.·•.•ri:j
Mode

Temperature Range (Ambient)

Active Operation, Commercial

Symbol

Parameter

DoC to +70°C

Test Condition

4.75 V ~ Vee

~

Min

5.25 V

Typ

Max

Unit

ViL

Input Low Voltage

0.0

0.8

V

ViH

Input High Voltage

2.0

Vee

V

VOL

Output Low Voltage
(SCSI bus)

Vee

0.5

V

VOL

Output Low Voltage
(other pins)

Vee = Min, IOL = 8 mA

0.5

V

VoH

Output High Voltage
(other pins)

Vee

liN

Input Current*

Vee = Max, VIN = 0 - Vee (SCSI bus)

65

~

liN

Input Cu rrent*

Vee = Max, VIN = 0 - Vee (other pins)

20

~

Icc

Supply Current

Vee = Max, VIH = 2.4,
VIL = 0.4, 4 MHz cycle,
No Load, No Termination

20

mA

Icc

Supply Current
Quiescent

Same as above, inputs stable

1.5

mA

=Min, IOL =48 mA

=Min, IOH =-4 mA

V

3.5

10

*Not tested at low temperature extreme.

======================= Peripheral Products
6·17

06/23/95-LDS.53BO·G

•

- -------- --...-.-------- - ---~---

-

L5380/53C80

DEVICES INCORPORATED

SCSI Bus Controller

~

-!>v-

T

1

T

I
I

I

lOR

8237 A
DMA
CONTROLLER

~

t

lOW RESET

lOR

lOW RESET IRQ

DREQx

DRQ

DACKx

-DACK

READY

READY

EOP

EOP

ClK

L5380/
L53C80
SCSI
CONTROLLER

AEN
ADSTB

~ OE

-

0
lATCH

A7-4

A3-0

DB7-0

D7-0

W ~YSTEM

DATA BUS

JJ

M-o

.{~

NCSI CONTROV

NCSI DATA BU:V

CS
j

STB

A15-0

0

"-.)' ",,),
ADDRESS BUS A15-0

SEl
SDB7-0
SDBP

====================== Peripheral Products
6-18

OS/23/95-LDS.5380-G

-- -

- ---.
- ----------.
- ------- - --"".....---

L5380/53C80

DEVICES INCORPORATED

.CPU lIVRITE.~d.j.;E>TIMING(n$)

SCSI Bus Controller

.....

. . . . ..•••• •

•.• >

, } ., •..•. >;'.}

< . . >.:'.>'>,> ..

< .•....•.••.•.•.••••

•

•••••••

Commercial
2 Mbytes/sec
4 Mbytes/sec
Symbol

Parameter

Min

T1

Address Setup to Write Enable

10

5

T2

Address Hold from End of Write Enable

5

5

T3

Width of Write Enable

40

20

T4

Data Setup to End of Write Enable

20

5

T5

Data Hold from End of Write Enable

10

5

.> .

'

Min

Max

....

~~ T2 JZZZZZZZZZZZZ2

ZZZZZZZZZLc

A::

Max

_ _ _. r : = T 3

~~____~~/

lOW

J;-T4

/-rZ"7Z"7Z"'Z"""'T'"':Z~Zr-Z7"Z-rZ"7Z"'Z"""'T'"':Z~Zr-Z7"/7"Z"7Z"7'¥

D7-0

-T5-:-1¥-:Z~Zr-Z7"Z-rZ"7Z"'Z"""'T'"':/~Zr-Z7"Z-r/"7Z"7Z",/..--,
..

···.·q~Q!·a~~.~qy~J..g·.ItMI~~,;(~~)i.;i:::·· i.}!;.: .•• ,·S·>i.·;,.i.c,;·'c·,·. . ,.•·•• :,D.,;;,;:;::!·. f;·.;!>,··.;·;··.·· . }(:.: . . ;.••:'; •.• .•·.·~.t::,i':;·.:.'·}.· .....:.,. ,> .•:, ., ..•;
Commercial
2 Mbytes/sec
4 Mbytes/sec
Symbol

Parameter

Min

T1

Address Setup to Read Enable

10

T2

Address Hold from End of Read Enable

T3

Data Access Time from Read Enable

Max

Min

Max

5
5

5
50

30

:: ZZZZZZZZZr__~~-~~-------~~~--T-2~ZZZZZZZZZZZZ2
::

~~T_3

/~XZZZ7ZZZZZZZZZZ2

___

=======================Peripheral Products
6-19

06/23/95-LDS.5380-G

•

- -- --------- ------~---

-

L5380/53C80

DEVICES INCORPORATED

l:bQM~·:~:L.·:;:
'~~.~.!':C ~~.,•.

i..',

Symbol

SCSI Bus Controller

c. ccF c: ·~·.cc·· <.•·.•. ·c'"'·...<. ,;".r:;t~~1·::[.<.:.::i.:;.cr.;~:;i:·;·~c:;':il . <. ::c[c.f<.cccc.~;;:!:cr~(::.:c.i;,:·:r·:;'·;.·.r .c;;·.•c.•. •c·c.i.;.<;·• • c:i.•·.·•. c:.·.C:;c:...G·: •.;·c:·!· .•.• £(
Commercial
2 Mbytes/sec
4 Mbytes/sec
Min
Max
Min
Max

Parameter
The following apply for all DMA Modes

T1

ORO False from Write Enable
(concurrence of lOW and DACK)

T2

Width of Write Enable
(concurrence of lOW and DACK)

60

20

60

30

T4

Data Setup to End of Write Enable

20

5

T5

Data Hold from End of Write Enable

15

5

T6

Concurrent Width of EOP, lOW, and DACK

50

T9

REO False to ACK False

20
45

90

T13

End of Write Enable to Valid SCSI Data

T14

SCSI Data Setup Time to ACK True

T7

REO False to ORO True

T8
T10

45

65
60

65

The following apply for Normal DMA Mode only
60

30

DACK False to ACK True (REO True)

185

165

REO True to ACK True (DACK False)

70

35

The following apply for Blockmode DMA only
T3

lOW Recovery Time

40

20

T8

lOW False to ACK True (REO True)

185

165

T10

REO True to ACK True (lOW False)

70

35

T11

REO False to READY True

60

30

T12

lOW False to READY False

70

35

""k

DRQ

------------

-----------07-0

_________ .:K.

T1

---------------------------------T3

I--T2

------

.I:=T4~- T5-===:j.

/ / / / / / / / / / / /)1(

)1(/ / / / / / / / / / / / / / /

BYTE N

X/////////LL/~L~

BYTE N (BLOCKMODE)

07-0

-------

.71"

~T6T7--

TB

"k
l~T1o-

-T9

.71"
-T12-==:j

T11---j

READY

.71"

"k
I.

T13

1"':

T14-

--------=-~..:------*-----BYTE N-1

BYTE N

= = = = = = = = = = = = = = = = = = = = = = Peripheral Products
6-20

06/23/95-LDS.5380-G

--..--- ---- --------

-~----...-.
-...-.

L5380/53C80

-~---

DEVICES INCORPORATED

..L"",';,;". ,"",'

.~

~:.J:
~',

Symbol

SCSI Bus Controller

',' ,'

·}?f';.!...;.·>. . '• • ,.i,,",• • •'." • ",.·,• ,• • • 'i...),.f·.·,• . t;iI·.',.

""~. ,. .,.. ~ . ;,~;~;.~(~$l'. " ·"', . ·',. ,. ." ," . 'i{,'.• .• .• • •'• '••••••.•••••• "'; ,• ,·•.•.,• •,•.

Commercial
2 Mbytes/sec
4 Mbytes/sec
Min
Max
Min
Max

Parameter
The following apply for all DMA Modes

T1

DRO False from Concurrence of lOR and DACK

60

30

T3

Data Access Time from Concurrence of
lOR and DACK

60

20

T4

Concurrent Width of EOP, lOR, and DACK

50

20

T7

REO True to ACK True

T12

SCSI Data Setup Time to REO True

20

5

T13*

SCSI Data Hold Time from REO True

15

10

T5

REO True to DRO True

60

30

T6

DACK False to ACK False (REO False)

90

55

T8

REO False to ACK False (DACK False)

80

55

T2

lOR Recovery Time

70

35

The following apply for Normal DMA Mode only

The following apply for Blockmode DMA only

40

20

T6

lOR False to ACK False (REO False)

90

45

T8

REO False to ACK False (lOR False)

80

45

T9

REO True to READY True

60

30

T10

READY True to CPU Data Valid

15

15

T11

lOR False to READY False

70

35

'{

ORO

-T1--·1

---------------------------------T--

---------------- -------

}'

---------------

-----

07-0

07-0

///////// ///)

-T3-1.

T2

BYTE N

BYTE N (BLOCKMODE)
~T4-

!-T5-

T6

TB

I---T7

REAOY

T11

I-- T9 - 1 - : - - T1 0 ;01"
T12-I--T13

r-

i

*Data must be held on the SCSI bus until ACK becomes True

======================= Peripheral Products
6·21

06i23i95-LDS,53BO-G

•

-

- --------- ------ ------------

L5380/53C80

-~

DEVICES INCORPORATED

SCSI Bus Controller

T1

ORQ False from Write Enable
(concurrence of lOW and OACK)

T2

Width of Write Enable
(concurrence of lOW and OACK)

60

""-

~T1

07-0

----------1--- T2

------------

------

///////

•/

D7-0

/

/

20

60

DRQ

------------

30

--

-

--------

--- ---

T3

----

--------------

.;¥

/

/~

9-

T4

- - - T 5~

*// / / / / / / / / / / / / /

BYTE N

L/LL/L~LLLLLLLL

BYTE N (BLOCKMODE)

.t-- T6 -

"k
-T7-

T8

,v

---.., ~T9---1

T10

k
-T12-==::j

I---T11-j

READY

.;¥
II

SDB7-0
SDBP

T13

""-

~

T14-

------------------------~~---------BYTE N-1

BYTE N

======================= Peripheral Products
6-22

06/23/95-LDS.5380-G

--------- --- ----.....--.~-.-....-.

-

L5380/53C80

.-..~--~

-~---

DEVICES INCORPORATED

SCSI Bus Controller

T1

ORO False from Concurrence of lOR and DACK

60

T3

Data Access Time from Concurrence of
lOR and DACK

60

30
20

~

ORQ

-T1-1

---------------

¥---------------------------------T--

-------

T2

--------------- ----07-0

07-0

/////////

///

!--T3-I.

BYTE N

BYTE N (BLOCKMODE)
I----T4-

-T5-

T6

;Ii'
_

T7-------':'1

TB

:>I"
T11

- T 9 - t = . . T1O -

REAOY

K

-{

-T12--T13

SOB7-0
SOBP

I,
i<.

BYTE N

"Yf-///////////////////////L//L/LL/L/

'Data must be held on the SCSI bus until REO becomes False

======================= Peripheral Products
6-23

06/23/95-LDS.5380-G

L5380/53C80
DEVICES INCORPORATED

1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot.
Input levels below ground or above Vee
will be clamped beginning at -0.6 V and
Vee + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of -0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 rnA.

SCSI Bus Controller

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tENA/tDIS test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
1.5 V may be used. Parasitic capacitance
is 30 pF minimum, and may be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 rnA to reduce the RC
delay component of the measurement.

the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with specified loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

vec

d,
}

This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/ tum-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

~n

a. A 0.1 IlF ceramic capacitor should be
installed between Vee and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
4. Actual test conditions may vary from should be installed between device Vee
those designated but operation is guar- and the tester common, and device
anteed as specified.
ground and tester common.
5. Supply current for a given applica- b. Ground and vee supply planes
tion canbe accurately approximated by: must be brought directly to the DUT
NCV2 F
socket or contactor fingers.

--where

4

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

c. Input voltages should be adjusted to
compensate for inductive ground and
Vee noise to maintain required DUT
input levels relative to the DUT ground
pin.

+---t--oOUTPUT
n+

10. Each parameter is shown as a min6. Tested with all outputs changing ev- imum or maximum value. Input reery cycle and no load, at a 5 MHz clock quirements are specified from the point
of view of the external system driving
rate.
the chip. Setup time, for example, is
7. Tested with all inputs within 0.1 Vof specified as a minimum since the exterVee or Ground, no load.
nal system must supply at least that
8. These parameters are guaranteed much time to meet the worst-case requirements of all parts. Responses from
but not 100% tested.
the internal circuitry are specified from

======================Peripheral Products
6-24

OS/23/95-LDS.5380·G

- ---_
----- --.---.--....... .. --""-""---

L5380/53C80

-~
~----

~~

DEVICES INCORPORATED

40-pin -

SCSI Bus Controller

0.6" wide

44-pin

Do

D1
02
03
04
05

SDB7
SOB6
SOBs
SDB4
SOB3
SDB2
SDB1
SDBa
SOBP
GNO
SEL
BSY
ACK
ATN
RST

Os
07

A2
A1
Vee
Aa
lOW
RESET
EOP
DACK
READY
lOR
IRQ
ORO

1/0

CID
MSG
REO

4
2

I~I~I~I~ 8 ~ 0 ~ IS 0 Cl
SOB3

7 6 5 4 3 2

SOB2
SOB1
SOBa

8
9
10

SOBP
GNO
GNO
SEL

11
12
13
14

BSY
ACK

15
16
17

i~j

44 43 42 41

4~9
38

06
07

A2
A1

Top
View

35

30

Vee
NC
Aa
lOW
RESET
EOP

29

OACK

34
33
32

31

18 19 20 21 22 23 24 25 26 27 28

•

CS

L5380PC4
L5380PC2

L5380JC4
L538OJC2

====================== Peripheral Products
6-25

06/23/95-LDS.5380-G

L5380/53C80
OEVICES INCORPORATEO

SCSI Bus Controller

48-pin

44-pin
SOB7
RST
GNO
BSY
SEL
ATN
NC
RESET
IRO
ORO
EOP
OACK
GNO
READY
Ao
A1

A2.
NC
CS
lOW
lOR
07
06
Os

SOBs
SOBs
GNO
SOB.
SOB3
SOB2
NC
SOB1
SOBo
GNO
SOBP
REO
ACK

I-wcnZClJClClClZClCl
IZI~I~
°1~lml~l~ °1~IS


Plastic J-Lead Chip Carrier
(J1)

4
2

L53C80PC4
L53C80PC2

L53C80DC4
L53C80DC2

L53C80JC4
L53C80JC2

======================= Peripheral Products
6-26

06/23/95-LDS.5380-G

-.-.-.-- - ,.,--------.-...----

-

- ---

.-.-.

~

-~---

DEVICES INCORPORATED

Peripheral
FIFO Products

•

---------- --...-.---------....-....-..

-

-~---

DEVICES INCORPORATED

FIFO Products

FIFO Products ............................................................................................................................................................................... 7-1
L8C201
L8C202
L8C203
L8C204
L8C211
L8C221
L8C231
L8C241

512 x 9, Asynchronous ......................................................................................................................................... 7-3
1K x 9, Asynchronous .......................................................................................................................................... 7-3
2K x 9, Asynchronous .......................................................................................................................................... 7-3
4K x 9, Asynchronous .......................................................................................................................................... 7-3
512 x 9, Synchronous ......................................................................................................................................... 7-23
1K x 9, Synchronous .......................................................................................................................................... 7-23
2K x 9, Synchronous .......................................................................................................................................... 7-23
4K x 9, Synchronous .......................................................................................................................................... 7-23

•

7-1

- ---"'"-""---

5...U£iE~

DEVICES INCORPORATED

~~~g{;

L8C201/202/203/204

DEVICES INCORPORATED

512/1 Kl2K14K x 9-bit Asynchronous FIFO

o First-In/First-Out (FIFO) using
o
o
o
o
o
o
o
o

o

Dual-Port Memory
Advanced CMOS Technology
High Speed - to 10 ns Access Time
Asynchronous and Simultaneous
Read and Write
Fully Expandable by both Word
Depth and/ or Bit Width
Empty and Full Warning Flags
Half-Full Flag Capability
Auto Retransmit Capability
Plug Compatible with IDT720x,
Cypress CY7C4x, and Samsung
KM75COx
Package Styles Available:
• 28-pin Plastic DIP
• 32-pin Plastic LCC

The L8C201, L8C202, L8C203, and
L8C204 are dual-port First-In/FirstOut (FIFO) memories. The FIFO
memory products are organized as:
L8C201 - 512 x 9-bit
L8C202 - 1024 x 9-bit
L8C203 - 2048 x 9-bit
L8C204 - 4096 x 9-bit
Each device utilizes a special algorithm
that loads and empties data on a firstin/first-out basis. Full and Empty flags
are provided to prevent data overflow
and underflow. Three additional pins
are also provided to allow for unlimited
expansion in both word size and depth.
Depth Expansion does not result in a
flow-through penalty. Multiple devices
are connected with the data and control
signals in parallel. The active device is
determined by the E~ansion In (XI)
and Expansion Out (XO) signals which
are daisy chained from device to
device.

The read and write operations are
internally sequential through the use
of ring pointers. No address information is required to load and unload
data. The write o..Eeration occurs
when the Write (W) signal is LOW.
Read occurs when Read (R) goes
LOW. The nine data outputs go to the
high impedance state when R is
HIGH. Retransmit (RT) capability
allows for reset of the read pointer
when RT is pulsed LOW, allowing for
retransmission of data from the
beginnin..£. Read Enable (R) and Write
Enable (W) must both be HIGH
during a retransmit cycle, and then R
is used to access the data. A Half-Full
(HF) output flag is available in the
single device and width expansion
modes. In the depth expansion
configuration, this pin provides the
•
Expansion Out (XO) information
which is used to tell the next FIFO that
it will be activated.
These FIFOs are designed to have the
fastest data access possible. Even in
lower cycle time applications, faster
access time can eliminate timing
bottlenecks as well as leave enough
margin to allow the use of the devices
without external bus drivers.

DATA INPUTS
08-0

9

The FIFOs are designed for those
applications requiring asychronous
and simultaneous read/writes in
multiprocessing and rate buffer
applications.

DATA OUTPUTS
Q.-O

R---+'!

Xi ------+L~~~f___-----xo/RF

====================== FIFO Products
7-3

03/07/95-LDS.8C201/2/3/4-D

- - --=---= =-===--

=~~=~

L8C201/2021203/204

-~---

DEVICES INCORPORATED

SIGNAL DEFINITIONS
Inputs

RS-Reset
Reset is accomplished whenever the
Reset (RS) input is taken to a LOW
state. During reset, both internal read
and write pointers are set to the first
location. A reset is required after
power-up before a write operation can
take place. Both the Read Enable (R)
and Write Enable (W) inputs must be
in the HIGH state during the window
shown (i.e., tWHSH before the rising
edge of RS) and should not change
until tSHWL after the rising edge of
RS. Hall-Full Flag (HF) will be reset to
high after Reset (RS).

W- Write Enable
A write cycle is initiated on the falling
edge of this input if the Full Flag (FF)
is not set. Data setup and hold time
must be adhered to with respect to the
rising edge of the Write Enable (W).
Data is stored in the RAM array
sequentially and independently of any
on-going read operation.
To prevent data overflow, the Full
Flag (FF) will go LOW, inhibiting
further write operations. Upon the
completion of a valid read operation,
the Full Flag (FF) will go HIGH after
tRHFH, allowing a valid write to
begin. When the FIFO is full, the
internal write pointer is blocked from
W, so external changes in W will not
affect the FIFO when it is full.

R- Read Enable
A read cycle is initiated on the falling
edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The
data is accessed on a First-In/FirstOut basis, independent of any ongoing write operation. After Read
Enable (R) goes HIGH, the Data
Outputs (Ds·o) will return to a high
impedance condition until the next
read operation. When all the data has
been read from the FIFO, the Empty
Flag (EF) will go LOW, allowing the

512/1 Kl2K14K X 9-bit Asynchronous FIFO
"final" read cycle but inhibiting
further read operations with the data
outputs remaining in a high impedance state. Once a valid write operating has been accomplished, the Empty
Flag (EF) will go HIGH after tWHEH
and a valid read can then begin.
When the FIFO is empty, the internal
read pointer is blocked from R so
external changes in R will not affect
the FIFO.

Outputs

FF - Full Flag
The Full Flag (FF) will go LOW,
inhibiting further write operations,
indicating that the device is full. If the
read pointer is not moved after Reset
(RS), the Full Flag (FF) will go LOW
after 512 writes for the L8C201, 1024
writes for the L8C202, 2048 writes for
the L8C203, and 4096 writes for the
L8C204.

FL/RT - First Load/Retransmit
This is a dual-purpose input. In the
Depth Expansion Mode, this pin is
grounded to indicate that it is the first
loaded (see Operating Modes). In the
Single Device Mode, this pin acts as
the retransmit input. The Single
Device Mode is initiated by grounding
the Expansion In (XI).
The FIFOs can be made to retransmit
data when the Retransmit Enable
control (RT) input is pulsed LOW. A
retransmit operation will set the
internal read pointer to the first location
and will not affect the write pointer.
Read Enable (R) and Write Enable (W)
must be in the HIGH state during
retransmit. This feature is useful when
less than the full memory has been
written between resets. Retransmit will
affect the Half-Full Flag (HF), depending on the relative locations of the read
and write pointers. The retransmit
feature is not compatible with the
Depth Expansion Mode.

XI - Expansion In
This input is a dual-purpose pin.
Expansion In (XI) is grounded to
indicate an operation in the single
device mode. Expansion In (XI) is
connected to Expansion Out (XO) of
the previous device in the Depth
Expansion or Daisy Chain Mode.

Ds-o - Data Input
Data input signals for 9-bit wide data.
Data has setup and hold time requirements with respect to the rising edge
ofW.

EF - Empty Flag
The Empty Flag (EF) will go LOW,
inhibiting further read operations,
when the read pointer is equal to the
write pointer, indicating that the
device is empty.

XO/HF - Expansion Out/Half-Full Flag
This is a dual-purpose output. In the
Single Device Mode, when Expansion
In (XI) is grounded, this output acts as
an indication of a half-full memory.
After half of the memory is filled and
at the falling edge of the next write
operation, the Half-Full Flag (HF) will
be set to LOW and will remain set
until the difference between the write
pointer and read pointer is less than or
equal to one-half of the total memory
of the device. The Half-Full Flag (HF)
is then deasserted by the rising edge
of the read operation.
In the Depth Expansion Mode,
Expansion In (XI) is connected to
Expansion Out (XO) of the previous
device. This output acts as a signal to
the next device in the daisy chain by
providing a pulse to the next device
when the previous device reaches the
last location of memory.

Qs-o - Data Output
Data outputs for 9-bit wide data. This
data is in a high impedance condition
whenever Read Enable (R) is in a
HIGH state or the device is empty.

======================= FIFO Products
7·4

03/07/95-LDS.8C201/2/3/4·D

_--------- -................
----.....
---.~--

--.....-.~-

L8C201/2021203/204

-

-~---

DEVICES INCORPORATED

OPERATING MODES

Single Device Mode

512/1 Kl2K14K
4. External logic is needed to generate
a composite Full Flag (FF) and
Empty Flag (EF). This requires the
ORing of all EFs and ORing of all
FFs (Le., all must be set to generate
the correct composite FF or EF).

A single FIFO may be used when the
application requirements are for the
number of words in a single device.
The FIFOs are in a Single Device
5. The Retransmit (RT) function and
Configuration when the Expansion In
Half-Full Flag (HF) are not avail(XI) control input is grounded. In this
able in the Depth Expansion Mode.
mode the Half-Full Flag (HF), which is
an active-low output, is the active
Bidirectional Mode
function of the combination pin XO /
HF.
Applications which require data
buffering between two systems (each
system capable of read and write
Width Expansion Mode
operations) can be achieved by pairing
Word width may be increased simply FIFOs. Care must be taken to assure
by connecting the corresponding input that the appropriate flag is monitored
control signals of multiple devices.
by each system (i.e., FF is monitored
Status flags (EF, FF, and HF) can be
on the device when W is used; EF is
detected from anyone device. Any
monitored on the device when R is
word width can be attained by adding used). Both Depth Expansion and
additional FIFOs. Flag detection is
Width Expansion may be used in this
accomplished by monitoring the FF,
mode.
EF, and HF signals on either (any)
device used in the width expansion
Data Flow-Through Modes
configuration. Do not connect any
output signals together.
Two types of flow-through modes are
permitted: a read flow-through and
Depth Expansion (Daisy Chain) Mode
write flow-through mode. For the
read flow-through mode, the FIFO
The FIFOs can easily be adapted to
permits the reading of a single word
applications where the requirements
after writing one word data into an
are for greater than the number of
empty FIFO. The data is enabled on
words in a single device. Any depth
the bus in (tWHEH + tRLQV) ns after
can be attained by adding additional
the rising edge of W, called the first
FIFOs. The FIFOs operates in the
write ed~, and it remains on the bus
Depth Expansion configuration when until the R line is raised from LOW-tothe following conditions are met:
HIGH, after which the bus would go
1. The first device must be designated into a three-state mode after (tAHQZ)
ns. The EF line would have a pulse
by grounding the First Load (FL)
showing temporary de-assertion and
control input.
then would be asserted. During the
2. All other devices must have FL in
period of time that Ris LOW, more
the HIGH state.
words can be written to the FIFO (the
subsequent writes after the first write3. The Expansion Out (XO) pin of
edge will de-assert the Empty Flag).
each device must be tied to the
However, the same word (written on
Expansion In (Xl) pin of the next
device with the last device connect- the first write-edge) presented to the
output bus as the read pointer, would
ing back to the first.

X

9-bit Asynchronous FIFO
not be incremented when Ris LOW.
On toggling R, the other words that
are written to the FIFO will appear on
the output bus as in the read cycle
timings.
In the write flow-through mode, the

FIFO permits the writing of a single
word of data immediately after
reading one word of data from a full
FIFO. The R line causes the FF to be
de-asserted but the W line, being
LOW, causes it to be asserted again in
anticipation of a new data word. On
the rising edge of W, the new word is
loaded in the FIFO. The W line must
be toggled when FF is not asserted to
write new data in the FIFO and to
increment the write pointer. The user
must be aware that there is no minimum value for tRLEL and tWLFL.
These pulses may be slightly different
during some operating conditions and
lot variations.

= = = = = = = = = = = = = = = = = = = = = = FIFO Products
7·5

03/07/95-LDS.8C201/2/3/4·D

•

--

- .-.------------- ------- - -.-

L8C201/202/203/204

-~---

DEVICES INCORPORATED

51211 Kl2K14K x 9-bit Asynchronous FIFO

Storage temperature ............................................................................................................ -65°C to + 150°C
Operating ambient temperature ............................................................................................ -55°C to + 125°C
Vee supply voltage with respect to ground ............................................................................. -0.5 V to +7.0 V
Input signal with respect to ground ......................................................................................... -0.5 V to +7.0 V
Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V
Output current into low outputs .............................................................................................................. 25 mA

Temperature Range (Ambient)
O°C to +70°C
-40°C to +85°C

Mode
Active Operation, Commercial
Active Operation, Industrial

Symbol

Parameter

Test Condition

VOH

Output High Voltage

Vcc

= 4.5 V, 10H = -2.0 rnA

VOL

Output Low Voltage

Vce

= 4.5 V, 10L = 8.0 rnA

VlH

Input High Voltage

VlL

Input Low Voltage

(Note 3)

Ilx

Input Leakage Current

Ground

loz

Output Leakage Current

REB VIH, GND ~ VOUT ~ Vce

lee2

Vce Current, TTL Inactive

All Inputs

= VIH MIN (Note 6)

ICC3

Vee Current, CMOS Standby

All Inputs

= Vcc (Note 12)

CIN

Input Capacitance

Ambient Temp

COUT

Output Capacitance

Test Frequency

~

VIN

~

Supply Voltage
4.5 V :s; Vee :s; 5.5 V
4.5 V :s; Vee :s; 5.5 V

Min

Typ

Max Unit

2.4

Vcc

V
0.4

V

2.0

Vcc
+0.3

V

-0.5

0.8

V

-1

+1

IlA

-10

+10

!lA

15

mA

5

mA

5

pF

7

pF

= 25°C, Vcc = 4.5 V
= 1 MHz (Note 9)

L8C201/2021203/204-

Symbol
Icel

Parameter
I Vee Current, Active

Test Condition
I (Note5)

25

15

12

10

Unit

100

120

150

180

mA

======================= FIFO Products
7-6

03107195-LDS.8C201121314·D

- ---- -.....-.--------------......

.-.....-.

L8C201/2021203/204

-

-~

-~---

51211 Kl2K14K x 9-bit Asynchronous FIFO

DEVICES INCORPORATED

iN

E

tWLWL
twLWH

~ IDVWH
DB-O

I

WHWLq

/

\WHDX ~

DATA-IN VALID

DATA-IN VALID

r--------tRHsH - - - - - - /

Rllll~~~r--------------r---------------ffi~L----------~

i------------tSl.HH,tSLFH------------i

======================= FIFO Products
7-7

03/07/95-LDS.BC201/213/4-D

- ---------- -----.....
......-.---_
......

-

-~~-~

L8C201/2021203/204

-~---

DEVICES INCORPORATED

51211 Kl2K14K x 9-bit Asynchronous FIFO

i - - - - t - tRLQV
DATA
OUT

HF, EF,

-------t_---C~OK~~~~>---t-------------t_------_f--_<~~~V~A~LlD[)~~~-VALID

FF

FLAG VALID

=======================FIFO Products
7-8

03/07/95-LDS.8C201/2/3/4-D

L8C201/2021203/204
DEVICES INCORPORATED

51211 Kl2K14K x 9-bit Asynchronous FIFO

w

T
twHEH-+'1_ _-1

~----------------------------------------------~

-tEHRH

R"""""""",~~~~"""""

T

~----------------~.
-w ---------------.

~-------------------------1T

tRHFH -+'1_ _-1

~-----~---------------------------------------1
I---tFHWH

HALF-FULL OR LESS

MORE THAN
HALF-FULL

HALF-FULL OR LESS

w

,
I---twLH~

I----tRHHH

.Jf"

-'I<:

======================= FIFO Products
7-9

03107195-LD$,BC201121314-D

-

= ........
=~
. .,--.,
=-=-=:..===--~

L8C201/202/203/204

-~---

51211 Kl2K14K x 9-bit Asynchronous FIFO

DEVICES INCORPORATED

WRITE TO
LAST PHYSICAL
LOCATION
READ FROM

X: ________~~_tA_LO_L

~""'s,=

~_-_-_~:------~~~:_~_~_T_1O_N ~~~-HO-H---________

________

J----txLXH - - - - 1 - - - - tXHXL----I

WRITE TO
FIRST PHYSICAL
LOCATION

W -------'""--~~~_--/
READ FROM
FIRST PHYSICAL
LOCATION

=======================FIFO Products
7-10

03/07/95-LDS.8C201/2/3/4-D

--.....
-------- ----- ------.---.

L8C201/2021203/204

.---~--......-.

-~---

51211 Kl2K14K x 9-bit Asynchronous FIFO

DEVICES INCORPORATED

DATA IN ________~x~

_______________________________________________________________

"

•

tEHRH

""""""""""

*

I--tRLE~

"'k:

.1

I------ twHFH
DATA OUT

tRLOV
DATA-QUT VALID

IFHWH-

""""""""""

I------ IRHFH

twLF~

I'-

"'k:
t=.tDVWH

DATA IN

.1
DATA OUT

.I

twHDX

DATA-IN VALID

XXXX

IRLOV
DATA-QUTVALID

;OOOC

= = = = = = = = = = = = = = = = = = = = = = = FIFO Products
7-11

03/07/95-LDS.8C201/2/3/4-D

- - --LuCiE€:!
-~---

L8C201/2021203/204
51211 Kl2K14K x 9-bit Asynchronous FIFO

DEVICES INCORPORATED

I

-FF
9/

D8-0

xo

EF

9

L8C20X

/

,---+

08-0

Xi FL

Vcc

t

+---G=

XO

-FF
9/

~

9

L8C20X

/

Xi FL

,
9/

~

EF

.....--

t
-FF

XO

EF
9/

L8C20X

/

Xi FLQ

t

Reset

o

X

o

Retransmit
ReadlWrite

o
o
o

=

Location Zero

'Location Zero

o

1

1

Location Zero

Unchanged

x

X

X

Increment

Increment

x

X

X

Location Zero Disabled

Location Zero Disabled

o

1

X

X

X

X

MODE
Reset First Device
Reset All Others

o

ReadlWrite
(1) See Figure 1 (Depth Expansion Block Diagram)
(2) Unchanged

=======================FIFO Products
7-12

03/07/95-LDS.8C201/2/3/4-D

-- - --------.-.--~

~-~

--~-~----

L8C201/2021203/204

-~---

DEVICES INCORPORATED

1. Maximum Ratings indicate stress specifications only. Functional operation of these
products at values beyond those indicated
in the Operating Conditions table is not
implied. Exposure to maximum rating conditions for extended periods may affect reliability of the tested device.
2. The products described by this specification include internal circuitry designed to
protect the chip from damaging substrate
injection currents and accumulations of
static charge. Nevertheless, conventional
precautions should be observed during
storage, handling, and use of these circuits
in order to avoid exposure to excessive electrical stress values.
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at-O.6 V.
A current in excess of 100 rnA is required to
reach -2 V. The device can withstand indefinite operation with inputs as low as-3 V
subject only to power dissipation and bond
wire fusing constraints.
4. "Typical" supply current values are not
shown but may be approximated. At a Vee
of +5.0 V, an ambient temperature of +25°C
and with nominal manufacturing parameters, the operating supply currents will be
approximately 3/4 or less of the maximum
values shown.
5. Tested with outputs open and data inputs changing at the specified read and
write cycle rate. The device is neither full or
empty for the test.
6. Tested with outputs open in the worst
control signal combination (Le.,
W, R, XI, FL, and RS).

~~ ~ut

51211 Kl2K14K x 9-bit Asynchronous FIFO

ments of all parts. Responses from the internal circuitry are specified from the point of
view of the device. Access time, for example, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
10. When cascading devices, the reset pulse
width must be increased to equal tsLSH +
tSLHH.

11. It is not recommended that Logic Devices and other vendor parts be cascaded
together. The parts are designed to be pinfor-pin compatible but temperature and
voltage compensation may vary from vendor to vendor. Logic Devices can only guarantee the cascading of Logic Devices parts to
other Logic Devices parts.
12. Tested with output open and RS = FL

Rl 480Q
+5 V

OUTPUT

INCLUDING
JIG AND
SCOPE

I

30PF

R2
255Q

R1480Q
+5V

OUTPUT

o---~---~

= XI = R= W = Vee.
13. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.

INCLUDING
JIG AND
SCOPE

R2
25SQ

14. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 2b. This parameter is sampled and
not 100% tested.

•

15. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. Inadequate attention to setups and procedures
can cause a good part to be rejected as faulty.
Long high-inductance leads that cause supply bounce must be avoided by bringing the
Vee and ground planes directly up to the
contactor fingers. A 0.01 J.lF high frequency
capacitor is also required between Vee and
ground. To avoid signal reflections, proper
terminations must be used.

7. These parameters are guaranteed but not
100% tested.
8. Test conditions assume input transition
times of 5 ns or less, reference levels of 1.5 V,
output loading for specified IOL and IOH
plus 30 pF (Fig. 2a), and input pulse levels of
oto 3.0 V (Fig. 3).
9. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the external system driving the chip. For example,
tRLRH is specified as a minimum since the
external system must supply at least that
much time to meet the worst-case require-

======================= FIFO Products
7-13

03/07/95-LDS.8C201/2/3/4-D

L8C201/2021203/204
DEVICES INCORPORATED

28-pin -

51211 Kl2K14K x 9-bit Asynchronous FIFO

0.3" wide

28-pin -

Vi

Vcc

Vi

Vcc

Da
D3
D2
D1
Do

D4

D4
Ds
Ds
D7

FuRT

Da
D3
D2
D1
Do

FuRT

Xi

AS

Xi

AS

FF

EF

FF

Qo

XO/HF
07
Os
Os
04

Ds
Ds
D7

01
02
03
Oa
GND

25 ns
15 ns
12 ns
10 ns

0.6" wide

EF

00
01
02
03
Oa
GND

R

L8C201PI25
L8C201PI15
L8C201PI12
L8C201PI10

XOIHF

Or
06
Os
04

R

L8C201NI25
L8C201NI15
L8C201NI12
L8C201NI10

======================= FIFO Products
7-14

03/07/9s-LDS.ac201/213/4-D

---- -- -------~--

=-~IL:==.......
-~---

L8C201/2021203/204

DEVICES INCORPORATED

51211 Kl2K14K x 9-bit Asynchronous FIFO

32-pin

8 ciS: ~ ~ (3 0
4 3

2 1 3231 30
29

•

D1
Do

NC

Xi
00
01
02

fLIRT

Top
View

FF
NC

D6
D7

AS
EF
XO/HF

22
13
21
14 15 16 17 18 1920
(0)

co 0

Ule:

OOzz

'= esc ==II
0 .600

j

0.12J~ ~ ~ ~ ~~~~~ L~J J~:.~

0.200

0.045
0.065

0.100
BSC

0.014
0.026

BSC

SEATING PLANE

02 -

24-pin, 0.3" wide

24

0195lJmr
0.125

0.125
0.175

~~~*O'O4O
--..I I......II.-

J

0.100

TYPICAL

0.016
0.020

0.060

t

o0.320
.300

j

R

-.lj.- 0.008
0.012

SEATING PLANE

====================== Package Information
10-16

-=- -----

F&~=re.
-

Mechanical Drawings

==~,...~

DEVICES INCORPORATED

03 -

40-pin, 0.6" wide

[;;;;;;):::I:::::::I}
0.125

I~

.1

1.980
2.020

to.600j
0.620

01~~\!:~ I

0.1251
0.175

04 -

--.I

1.-0.100
TYPICAL

0.Q16JI..

0.060
SEATING PLANE

0.020

I O~

-+lk-0:012

64-pin, 0.9" wide, cavity up

64

II
0.125
0.195

r0.125 J

1--- 0.890 -----..j
1...........= 0.910 =--.1

~

~~

1I~0'040
-+-II+-

~

0.060

0.175

0.100
TYPICAL

0.016
0.020

~

---i1--.0.008
-11- 0.012

SEATING PLANE

= = = = = = = = = P a c k a g e Information
10-17

Mechanical Drawings
DEVICES INCORPORATED

05 -

48-pin, 0.6" wide

48

06 -

64-pin, 0.9" wide, cavity down

64

[::::::::::::::;;:::::::::::::::I~
0.120
0.150

b
r-

O.125J
0.175

~

0.090
o.lO!i

~t

~ ~

~~

0.100
TYPICAL

0,016
0.020

1 1--- 0.890 --1
-LI....--- 0.910----.1
t~
"l-0.006

-0.030
0.050
SEATING PLANE

0.012

= = = = = = = = = P a c k a g e Information
1()"18

- -- -------..
----~---

-

Mechanical Drawings

DEVICES INCORPORATED

07 - 20-pin, 0.3" wide

20

:~::bm
0.125
0.175

*

r- j
0 300
.

1F°32
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