1995_NEC_Application_Specific_Memory 1995 NEC Application Specific Memory
User Manual: 1995_NEC_Application_Specific_Memory
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NEG Electronics Inc.
NEe
Application Specific Memory
1995 Data Book
Document No. M11 002EU1 VODBOO
©1995 NEC Electronics Inc. All rights reserved.
Printed in the United States of America.
No part of this document may be copied or reproduced in any form or by any means without the prior consent of NEC Electronics Inc.
(NECEL). The information in this document is subject to change without notice. Devices sold by NECEL are covered by the warranty and
patent indemnification provisions appearing in NECEL Terms and Conditions of Sale only. NECEL makes no warranty, express, statutory,
implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
NECEL makes no warranty of merchantability or fitness for any purpose. NECEL assumes no responsibility for any errors that may appear in
this document. NECEL makes no commitment to update or to keep current information contained in this document. The devices listed in this
document are not suitable for use in applications such as, but not limited to, aircraft, aerospace eqUipment, submarine cables, nuclear reactor
control systems and life support systems. If customers intend to use NEC devices in these applications orthey intend to use "standard" quality
grade NEC devices in applications not intended by NECEL, please contact our sales people in advance. "Standard" quality grade devices are
recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial
robots, audio and visual equipment, and other consumer products. "Special" quality grade devices are recommended for automotive and
transportation equipment, traffic control systems, anti-disaster and anti-crime systems, etc.
Index
ISelection Guide
I
IDual Port Graphics Buffer
7
ILine Buffer
189
IField Buffer
227
IRambus™ DRAM
253
ISynchronous GRAM
357
iii
. . . . - - - - - - - NOTES FOR CMOS DEVICES - - - - - - - - . , ; - - ,
G)
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. ,It is recommended to
avoid using insulators that easily build static electricity.
Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
®
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
®
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, 1/0 settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
iv
Contents
Selection Guide.............................................................................. 1
Dual Port Graphics Buffer.......................... ........... .................... .... 7
256Kx 16
256Kx 8
Fast Page
IlPD482444 ... ........ ........ ........ .....
9
Hyper Page
IlPD482445 ...... .................... ......
9
Fast Page
Hyper Page
-
IlPD482234 ................................ 107
IlPD482235 ................................ 107
Line Buffer ................................................................................... 189
I 8DK H 5K x 16110K x 8 I------li 5V±1O%
I4DK HI-5_K_X_8_ _ _~--l1 5V±l0%
~ IlPD485506 ................................ 191
~ IlPD485505 ................................ 211
Field Buffer .................................................................................. 227
12M
H
256Kx8
1------l15V±1O%
~ IlPD42280 .................................. 229
Rambus DRAM ........................................................................... 253
118M
H
IMx9x2 banks 1---l13.3V±O.15V ~ IlPD488170L ............................. 255
116M
H
1M x 8 x 2 banks 1---l13.3V±0.15V ~ IlPD488130L ............................. 305
Synchronous GRAM ................................................................... 357
I 8M H
128K x 32 x 2 banks 1-1----11 3.3V±O.3V ~ IlPD481850 ................................ 359
v
Selection Guide
Part Number
Dual Port Graphics Buffer
~PD48
_ __----II
II
v~o Letter: 5.0V±1O%
L -A
2445 L G5 - A 70
-
r- - r- - r- - r-
-
-
-
r--
NECCMOS
.
Application Specific Memory
Device code - - - - - - - '
.·i···~····~~i~i(;$• jqtf.~rJ
5: Line Buffer
8: Rambus DRAM
Capacity - - - - - - - - - '
2: 2Mbits
4: 4Mbits
Words organization - - - - -.....
3: x 8 words
4: x 16 words
Function - - - - - - - - - - '
4: Fast page mode
5: Hyper page mode
Package
---------------1
LE : SO]
GW : Shrink SOP
G5 : TSOP(II)
RAS access time - - - - - - - - - - - - - - - '
60: 60ns
70: 70ns
80: 80ns
2
. 3.3V±0.3V
Line Buffer
IlPD48 -5 506 -r---rooG5 - 25
NEC CMOS Application
Specific Memory
I
Device code - - - - - - -......
1 : Graphics RAM
2: Dual Port Graphics Buffer
i !i il ili!l lili ililill i lililililil
8: Rambus DRAM
Function -------------1
SOS: SK x 8 bits
S06: SK x 16 bits/10K x 8 bits
Package - - - - - - - - - - - - - - 1
G : SOP
GS : TSOP(IT)
Read/Write cycle time - - - - - - - - - - - - - - - '
2S : 2Sns(Read cycle), 2Sns(Write cycle)
27: 27ns(Read cycle), 2Sns(Write cycle)
3S: 3Sns(Read cycle), 3Sns(Write cycle)
3
Field Buffer
yPD42280 GU - 30
2 M bits field buffer _ _ _ _......1
I
Package - - - - - - - - - - - - - - '
GU: SOP
V : ZIP
Access time, Read/Write cycle time ----------1
30: 2Sns(Access time), 30ns(Read cycle), 3Ons(Write cycle)
40: 3Ons(Access time), 4Ons(Read cycle), 4Ons(Write cycle)
60: 4Ons(Access time), 6Ons(Read cycle), 6Ons(Writc cycle)
4
RambusDRAM
,uPD488 170 L VN - A50
NEC CMOS Application _----II
Specific Memory
Device code - - - - - - - - - - '
1 : Graphics RAM
2: Dual Port Graphics Buffer
5: Line Buffer
Capacity--------------I
170: IBM bits(lM words X 9 bits X 2 banks)
130: 16M bits(lM words X 8 bits X 2 banks)
Operating voltage -------------1
L: 3.3V±0.15V
Package - - - - - - - - - - - - - - - - '
VN: 32 pin plastic SVP(II X 25)
G6: 72/36 pin plastic SSOP type
Clock frequency - - - - - - - - - - - - - - - - '
A50: 250MHz
A45: 225MHz
5
Dual Port Graphics Buffer
7
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
~PD482444,482445
4M-Bit Dual Port Graphics Buffer
256K WORDS BY 16 BITS
Description
The JlPD482444 and JlPD482445 have a random access port and a serial access port. The random access
port has a 4M-bit (262,144 words x 16 bits) memory cell array structure. The serial access port can perform
clock operations of up to 50 MHz from the 8K-bit data register (512 words x 16 bits).
To simplify the graphics system design, the split data transfer function and binary boundary jump function
have been adopted so that the number of split data registers can be programmed with the software during
serial read/write operations.
The JlPD482445 is provided with the hyper page mode, an improved version of the fast page mode of the
JlPD482444. The random access port can input and output data by CAS clock operations of up to 33 MHz. The
power supply voltage is 5 V ± 10 'Yo.
Features
Dual port structure (Random access port, Serial access port)
• Random access port (262,144-word x 16-bit structure)
----
JlPD482444
JlPD482444-60
JlPD482444-70'
RAS access time
60 ns(MAX.)
70 ns(MAX.)
Fast page mode cycle time
35 ns(MIN.)
40 ns(MIN.)
JlPD482445
----------
JlPD482445-60
JlPD482445-70
RAS access time
60 ns(MAX.)
70 ns(MAX.)
Hyper page mode cycle time
30 ns(MIN.)
35 ns(MIN.)
• Flash write function Note
• Block write function (8 columns)Note
• Mask write (Write-per-bit function)
• 512 refresh cycles /8 ms
• CAS before RAS refresh, RAS only refresh, Hidden refresh
Note Write-per-bit can be specified.
The information in this document is subject to change without notice.
·3585 (Japan)
9
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gPD482444,482445
• Serial access port (512 words x 16 bits organization)
• Serial read/write cycle time
JlPD482444-60
JlPD482444-70
JlPD482445-60
JlPD482445-70
20 ns(MIN.)
22 ns(MIN.)
• Serial data read/write
• Split buffer data transfer
• Binary boundary jump function
Ordering Information
RAS Access Time
ns (MAX.)
Package
Power Supply
Voltage
Page Mode
50
54-pin plastic shrink
5 V ± 10 %
Fast page mode
JlPD482444GW-70
70
SOP (525 mil)
tJPD482445GW-60
60
64-pin plastic shrink
5 V ± 10 %
Hyper page mode
70
SOP (525 mil)
Part Number
JlPD482444GW-50
IIPD482445GW-70
10
NEe
gPD482444,482445
Pin Configurations (Marking Side)
64-Pin Plastic Shrink SOP (525 mill
WO/IOO
Sial
W1/101
Vee
SI02
W2/102
SI03
W3/103
GND
SI04
W4/104
SI05
W5/105
Vee
SI060
W6/106
SI07
W7/107
GND
LWE
UWE
RAS
A8
A7
AS
AS
A4
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
0
'l::'l::
"CI"CI
CC
t
t
NN
~.,..
en.,..
Ci)Ci)
~.,..
:E:E
44
0
43
42
41
40
39
38
37
36
35
34
33
SC
SE
GND
SI015
W15/1015
SI014
W14/1014
Vee
SI013
W13/1013
SI012
W12/1012
GND
SI011
Wll/IOll
SI010
Wl0/1010
Vee
SI09
W9/109
SI08
W8I108
GND
DSF
NC
CAS
aSF
AO
Al
A2
A3
GND
AO to AS
WO to W15/100 to 1015
SIOO to SI015
RAS
CAS
Address inputs
Mask data selects/Data inputs and outputs
Serial data inputs and outputs
DT/OE
UWE. LWE
SE
Data transfer/Output enable
Write-per-bit/Write enable
SC
QSF
DSF
Vee
Row address strobe
Column address strobe
Serial data input/Output enable
Serial clock
Special function output
Special function enable
GND
Power supply voltage
Ground
NcNote
No connection
Note Some signals can be applied because this pin is not connected to the inside of the chip.
11
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yPD482444,482445
Block Diagram
RAS
CAS
DT/OE
UWE
LWE
DSF
-,'--....
Vcc-GND-
Refresh
Counter
o
511
Column Decoder
AO
512 columns x 16
A1
A2
f:.3
Memory Cell Array
(512 x 512 x 16)
A4
"'
~
a:
'"
A5
in
A6
A7
AS
SE-------1-----------------,
12
OSF
SIOO
SI015
NEe
yPD482444,482445
1. Pin Functions
This product is equipped with the RAS, CAS, UWE, LWE, DT/OE, AD to A8, DSF, SC, SE inputs, QSF output,
and WO to W15/100 to 1015,5100 to 51015 input/output pins.
(1/3)
Pin Name
RAS
(Row address strobe)
Input/
Function
Output
Input
This signal latches the row addresses (AD to A8), selects the corresponding
word line, and activates the sense amplifier. It also refreshes the memory
cell array of the one line (8,192 bits) selected from the row addresses (AD
to A8).
It also serves as the signal which selects the following operations.
• Write-per-bit
• Flash write
• CAS before RAS refresh
• Split data transfer
CAS
This signal latches the column addresses (AD to A8), selects the digit line
(Column address
connecting the sense amplifier, and activates the output circuit which
strobe)
outputs data to the random access port.
It also serves as the signal which selects the following operations.
• Read/write
• Block write
• Color register set
• Mask register set
AO to A8
These are the address input pins, TAP register input pins, and STOP
(Address inputs)
register input pins.
This is a 9-bit address bus. It inputs a total of 18 bits ofthe address signal,
starting from the upper 9 bits (row address) and then followed by the lower
9 bits, (column bits) (address multiplex method). Using these, one word
memory cells (16 bits) areselected from the 262, 144wordsx 16 bits memory
cell array.
During use, specify the row address, activate the RAS signal, latch the row
address, switch to the column address, and activate the CAS signal. After
activating the RAS and CAS signals, each address signal is taken into the
device. For this reason, the address input setup time (tASR, tASC) and hold
time (tRAH, tCAH) are specified for activating the RAS and CAS signals.
In the data transfer cycle, this TAP register input pin functions as the
address input pin which selects the memory cell fortransferring (9 bits are
latched at the falling edge of RAS) and the TAP register data input pin
which specifies the start addresses of the serial read/write operation after
data transfer (9 bits are latched at the falling edge of the CAS).
This pin functions as the STOP register input pin when the STOP register
is set (STOP register data (9 bits) are latched atthe falling edge of the RAS.)
13
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yPD482444,482445
(2/3)
Pin Name
Input/
Output
Input
(Data transfer/
output enable)
Function
Thesearethe data transfer control signal and read operation control signal
respectively. They have different functions in the data transfer cycle and
read cycle.
The data transfer cycle is initiated when a low level is input to this pin at
the falling edge of RAS.
Read operation is performed when this signal, and the RAS and CAS
signals are activated. The input/output pin is high impedance when this
signal is not activated. When the UWE and LWE signals are activated while
the DT/DE signals are activated, the DT/OE signals are invalid in the
memory and read operations cannot be performed.
(Write enable)
These are the write operation control signal and mask write cycle (writeper-bit function) mask data input control signal, respectively.
UWE controls the upper bytes (W8 to W15/108to 1015) and LWE controls
the lower bytes (WO to W7/IOO to 107) of the input/output pins.
When this signal, RAS and CAS signals are activated, write operations or
mask write can be performed. These mode are determined by the level
of UWE and LWE at the falling edge of RAS.
• High level ....... 8 or 16-bit write cycle
• Low level ........ Mask write cycle (Write-per-bit)
DSF
(Special function
enable)
This signal controls the selection of functions.
The selection of functions is determined by the level of this signal at the
falling edge of the RAS and CAS. The functions will change as follows
when this signal is high level.
• The data transfer "yele changes to a split data transfer cycle.
• The read/write cycle of each RAS clock changes to the flash write cycle.
• The write cycle of each CAS clock changes to the block write cycle.
WO to W15/100 to 1015
(Mask data selects!
Data inputs, outputs)
Input/These are normally 16-bit data bus and are used for inputting and
Output· outputting data. (100 to 1015).
Function as the mask data input pins (WO to W15) in the mask write cycle
(write-per-bit function).
Write operations can be performed only for WO to W15 that are input with
a high level at the falling edge of RAS (new mask data).
Functions as the column selection data input pin in the block write cycle.
14
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yPD482444,482445
(3/3)
Pin Name
sc
Input!
Output
Function
Input
This pin inputs the clock which controls the serial access port operation.
(Serial clock)
1:;Sii;i~iR~~(rj
' .... ,
..
I"'"
The data of the data register which is synchronized with the rising edge
of the SC are output from the SIOO to SI015 pins and kept until the next
SC rising edge.
.....
~l~!~
:
',
:
The data from the SIOO to SI015 pins are latched at the rising edge of the
SC and written in the data register.
SE
(Serial data input!
This is a control pin for the serial access port input/output buffer.
It controls data output during serial reading and controls data input during
serial writing.
output enable)
By inputting the serial clock, the serial pointer will operate even if SE has
not been activated (high level input).
SIOO to SI015
(Serial data inputs/
Input!
Output
These are the serial data input and output pins of the serial access port.
Output
This is a position discrimination pin of the serial pointer (upper side or
lower side).
outputs)
aSF
(Special function
output)
Which side is being serial accessed (upper side or lower side) can be
discriminated according to the output of this pin .
• High level. ...... Upper side (Addresses 256 to 511)
• Low level ..•..... Lower side (Addresses 0 to 255)
15
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yPD482444,482445
2. Random Access Port Operations
The operation mode is determined by the CAS, DT/OE, UWE, LWE, and DSF level at the falling edge of RAS
and DSF level at the falling edge of CAS.
Table 2-1. Operation Mode
CAS
RAS Falling Edge
Falling Edge
CAS DT/OE UWE LWE DSF
Operation Mode
DSF
H
H
H
H
L
L
Read/Write cycle
H
H
H
H
L
H
Block write cycle
H
H
L
L
L
L
Mask write cycle Note 1
H
H
L
H
L
L
Upper byte mask write cycle Note 1
H
H
H
L
L
L
Lower byte mask write cycle Note 1
H
H
L
L
L
H
H
H
L
H
L
H
III
"0
u>
..
Block mask write cycleNote 1
Upper byte block mask write cycle Note 1
III
H
H
H
L
L
H
.;:
H
H
H
H
H
H
"a
H
H
H
H
H
L
H
H
L
L
H
x
Flash write cycle Note 1
H
H
L
H
H
x
Upper byte flash write cycle Note 1
H
H
H
L
H
x
Lower byte flash write cycle Note ,
H
L
H
H
L
x
H
x
H
H
L
L
H
L
H
L
L
x
H
L
L
L
H
x
L
x
x
x
L
x
L
x
H
H
H
x
L
x
L
L
H
x
H
H
x
x
x
x
-
3:
:II
a::
Lower byte block mask write cycle Note 1
Color register set cycle
Write mask register set cycle
.!!
!eo Single read data transfer cycle
u
~
.!!
Split read data transfer cycle
.::'"
Single write data transfer cycle Note ,
.l!!
Split write data transfer cycleNote ,
'"<:
'"
Q
III
U
ti
.c:
1/1
III
iia::
CAS before RAS refresh cycle (Option reset)Note 1,2
CAS before RAS refresh cycle (No reset)
CAS before RAS refresh cycle (STOP register set)Note 2
RAS only refresh cycle
Notes 1. Observe the following conditions when using the new mask data or old mask data in these cycles.
(1) Old mask data
Can be used after setting the mask data using the write mask register set cycle.
(2) New mask data
Can be used after selecting the new mask register using the write mask register set cycle (new
mask selection) and after the optional reset cycle.
2. The STOP register is set to "FFH (11111111)" by the optional reset cycle.
Remark H: High level, L: Low level, x: High level or low level
16
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yPD482444,482445
2.1 Random Read Cycle
This product has a common 16-bit input/output pin. To output data, specify the address using the RAS and
CAS clocks and then set DT/OE to low level.
The data output will be kept until one of the following conditions is set.
(1) Set RAS and CAS to high level
(2) Set DT/OE to high level
(3) Set UWE and LWE to low level (UWE controls the upper bytes, LWE controls the lower bytes)
. The read cycle and data transfer cycle are differentiated according to the level of DT/OE at the falling eage
ofthe RAS clock. If DT/OE is set to low level atthe falling edge ofthe RAS clock, data transfer cycle operations
will be initiated. Therefore, to set the read cycle, input a high level above tOHH (MIN.) to DT/OE from the falling
edge of the RAS clock, and then input a low level.
Caution Set the DSFto low level at the falling edge of RAS. If set to high level, the memory cell data cannot
be output.
2.1.1 Extended Read Data Output IJLPD482445.)
The JlPD482445 adopts the hyper page mode cycle which is a faster resd/write cycle than the fast page mode of
the JlPD482444 (Hyper page mode cycle time: 30 ns (MIN.)).
With this cycle, the read data output can be kept until the next CAS cycle, and because the output is extended,
the minimum cycle can easily be used. For example, by fixing DT/OE at low level after dropping RAS and
executing the hyper page read cycle, each time the column address is latched at the falling edge of CAS, the data
output will be updated and kept until the next falling edge of CAS. As a result, the output will be extended only
during CAS precharge time (tcp) as compared to the normal fast page mode.
Figure 2-1. Extended Data Output of Hyper Page Mode
RAS (Input)
CAS (Input)
AD to AS (Input)
DT/OE (Input)
Note 1
WIIO (Output)
Note 2
Note 1
High-Z
~J<"f'1
High-Z
Notes 1. Time during which the output data is kept in the fast page read cycle.
2. Time during which the output data is kept in the hyper page read cycle I E part: Extended data
output).
17
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yPD482444,482445
2.2 Random Write Cycle (Early Write, Late Write, Read Modify Write)
There are three types of random write cycles-the early write, late write, and read modify write. To use these
cycles, activate the RAS and CAS clocks and set UWE and LWE to low level. In addition, as this product has two
write enables, data input can be controlled for every 8 bits (upper byte and lower byte). UWE controls the upper
bytes'(W8 to W15/108 to 1015) while LWE controls the lower bytes (WO to W7/100 to 107). Byte write cycle can
therefore be performed by controlling UWE and LWE.
The random write cycle, regardless of the word/byte write cycle, latches the word data (16 bits) iIJPut to the
data bus. By inputting a low level to UWE (or LWE) during the byte write cycle, the latched word (16 bits) data
will be written only in the upper byte (or lower byte) and the data ofthe unselected lower byte (or upper byte)
will be ignored. In the same write cycle, by inputting a low level to LWE (or UWE) later, the ignored lower byte
(or upper byte) data can be written. By controlling the UWE and LWE pins, the word data (16 bits) in the same
cycle can be written in one byte (8 bits).
The UWE and LWE also control the mask data for the write-per-bit function (mask write cycle). Therefore,
when performing the normal write cycle which does not use the write-per-bit function, set these pins to high
level at the falling edge of the RAS clock.
2.2.1 Early Write Cycle
The early write cycle controls data writing according to the CAS clock.
To execute this cycle, set UWE and LWE to low level earlier than the CAS clock. The write data is taken into
the device at the falling edge of the CAS clock.
2.2.2 Late Write Cycle
The late write cycle controls data writing according to the WE clock.
To execute this cycle, set UWE and LWE to low level later than the CAS clock. The write data is taken into
the device at the falling edge of UWE and LWE. To set the output to high impedance at this time, keep DT/OE
at high level until UWE and LWE are input.
2.2.3 Read Modify Write Cycle
The read modify write cycle performs data reading and writing in one RAS and CAS cycle.
To execute this cycle, delay UWE and LWE from the late write cycle bytRWD (MIN.), tCWD (MIN.), and tAWD (MIN.).
Follow the tOEZ and tOED specifications so that the output data and input data do not clash in the data bus. Th.e
data after modification can be input after more than tOED (MIN.) from the rising edge of DT/OE.
2.3 Fast Page Mode Cycle (,uPD482444)
The IlPD482444 adopts the fast page mode. This mode accesses memory cells in the same row array in about 1/3
of the time taken by the normal random read/write cycle. This fast page mode cycle is executed by repeating the CAS
clock cycle more than two times while the RAS clock is being activated. In this mode read, write and read modify
write cycles are available for each of the consecutive CAS cycles within the same RAS cycle.
2.4 Hyper Page Mode Cycle I,uPD482445, 482445L)
The IlPD482445 adopts a hyper page mode cycle which is a faster read/write cycle than the fast page mode of the
IlPD482444 (Hyper page mode cycle time: 30 ns (MIN.)).
In this cycle, because the read data output is kept until the following CAS cycle and as a result, the output
is extended, the minimum cycle can easily be used. The output is extended compared to the normal fast page
mode of J!PD482444. Refer to 2.1.1 Extended Read Data Output.
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2.5 Flash Write Cycle
This cycle writes the color register data in a 8, 192-bit or.4,096-bit memory cell in one cycle. The memory cell
range for one flash write cycle is 512 columns on the same row address (512-column x 16 . 10 = 8,192 bits or
512-column x 8 . 10
= 4,096 bits).
2.5.1 Execution of Flash Write Cycle
(1) Execution of flash write for word (512-column x 16 • 10
= 8,192
bits)
To execute the flash write cycle, set both UWE and LWE to low level at the falling edge of RAS.
By using the write-per-bitfunction (new mask data/old mask data), only the required W/IO can be selected
and written.
(2) Execution of flash write for byte (512-column x 8 • 10
= 4,096
bits)
To 'execute the flash write cycle, set either UWE or LWE to low level at the falling edge of RAS.
By using the write-per-bit function (new mask data/old mask data), only the required W/IO can be selected
and written.
Figure 2-2. Memory Cell Range That Can be Written with Flash Write Cycle
W15/108to 1015
512
Remark
Ei'iD is the memory cell range that can be written in one flash write cycle.
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2.6 Block Write Cycle
This cycle writes the color register data in 12S-bit or 64-bit memory cell in one cycle. The memory cell range
in which data can be written in one block write cycle is eight continuous columns on one row address (S-column
x 16-· 10 " 12S bits or S-column x S . 10 = 64 bits).
Any column of the eight columns can be selected and writing prohibited. Determine whether to write or
prohibit writing according to the data selected for column.
2.6.1 Free Column Selection
Determine which column to select according to the wilo pin to which the data selected for the column is to
be input.
The eight columns (1st to Sth) correspond to WO to W15/100 to 1015 to which the data selected for column
will be input (The following table shows the 1stto 8th columns specified by AO, A 1, and A2 and the corresponding
WIlD pins to which the data selected will be input.).
2.6.2 Column Select Data
Input column select data for every eight columns at the upper 64 bits and lower 64 bits (a total of 16 columns).
The data will be written if the column select data is H 1H. Writing will be prohibited if the column select data is
"0".
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2.6.3 Execution of Block Write Cycle
At the falling edge ofthe slowest signal (CAS, UWE, or LWE), input the "1" column select data or "0" column
select data to WO to.W15/100 to 1015 corresponding to columns 1st to Sth.
By using the write-per-bit (new mask data/old mask data) function, only the required W/IO can be selected
and written.
Table 2-2. I/O Pins Input with Column Select Data Corresponding to Columns 1st to 8th
Column Select Data of Lower Byte (100 to 107)
Selected S
Columns
1st column
2nd column
3rd column
4th column
5th column
6th column
7th column
Sth column
Column Address
and Corresponding . Column
Select
W/IO Pin
Data
A2 A1 AO 10
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100
101
102
103
104
105
106
107
Writing
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
Column Select Data of Upper Byte (108 to 1015)
Selected S
Columns
1st column
2nd column
3rd column
4th column
5th column
6th column
7th column
8th column
Column Address
and Corresponding
W/IO Pin
A2 A1 AO
10
0
lOS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
109
1010
1011
1012
1013
1014
1015
Column
Select
Data
Writing
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
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Figure 2-3. Memory Cell Range That Can be Written in Block Write Cycle
' - - - - 7th Column (W14/1014)
' - - - - - 6th Column (W13/1013)
' - - - - - - - 5th Column (WI2/1012)
L-_ _ _..,,-_ _ 4th Column (Wll/1011)
512
' - - - - - - - - - 3rd Column (WI 01101 0)
' - - - - - - - - - - - 2nd Column (WSII09)
L-_ _ _ _ _ _ _ _ _ _ 15tColumn (W6IIOB)
'----7th Column 1W61106)
' - - - - - G t h Column (W51105)
L - - - - - - 5 t h Column (W41104)
L - - - - - - - 4 t h Column (W3/103)
' - - - - - - - - - 3 r d Column (W2/102)
L - - - - - - - - - - 2 n d Column (WlI101)
' - - - - - - - - - - - - 1 5 t Column (WO/IOO)
c::::J
Remarks 1.
is the memory cell range that can be written in one block write cycle.
2. ( ) is the WIlD pin input with the column select data.
2.7 Register Set Cycle (Color Register, Write Mask Reg.ister)
This cycle writes data in the color register and write mask register. To execute the register set cycle, set CAS,
DTIDE, UWE, LWE and DSF to high level at the falling edge of RAS. Determine which register to select according
to the DSF level at the falling edge of CAS.
The register set cycle also serves as the RAS only refresh cycle.
Table 2-3. Register Selection
DSF level at CAS falling edge
Selected register
High level
Color register
Low level
Write mask register
Caution After selecting the write mask register and writing the mask data, the write-per-bit function in the
mask write cycle will be set for the old mask register. Refer to 2.8.1 Write-Per-Bit Function.
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2.8 Mask Write Cycle
Cycles that use the write-per-bit function during the random write cycle, flash write cycle, block write cycle,
write data transfer cycle, are called mask write cycles. In the fast page/hyper page mode write cycle, the mask
data cannot be changed during the CAS cycle.
2.8.1 Write-Per-Bit Function
The write-per-bit function writes data using the mask data only in the required IO-pin. It writes when the mask
data is "1" and prohibits writing when the data is "0".
Table 2-4. Mask Data Selection
WPin
Mask Data
Writing
WOto W15
1
Yes
0
No
2.8.2 Selecting Mask Data
There are two ways ofselecting mask data. One is the new mask data method and the other is the old mask
data method.
With the new mask data method, new mask data is set in the cycle writing. With the old mask data, mask
data set in the write mask register is used.
(1) New Mask Data Method
The new mask data method consists of the write mask register set cycle (new mask selection) method
and CAS before RAS refresh cycle (optional reset cycle) method.
(a) Method Using Write Mask Register Set Cycle (New Mask Selection)
To switch to the mode using new mask data, keep the DT/OE, UWE, LWE DSF to high level and set
the CAS and DSF to high level at the falling edge of RAS, the DSF to low level at the falling edge of
CAS, and start up the next RAS and CAS after the teAs and tRAS.
As a result, the write-per-bit flinction can be used using the new mask data from the next mask write
cycle.
(b) Method Using CAS Before RAS Refresh Cycle (Optional Reset Cycle)
To switch to the mode using new mask data, set the DSF to low level at the falling edge of CAS in
the CAS before RAS refresh cycle.
As a result, the write-per-bit function can be used using the old mask data from the next mask write
cycle.
(2) Old Mask Data Method
To switch to the mode using old mask data, set the DSF to low level at the falling edge of CAS in the write
mask register set cycle, and write the mask data in the write mask register.
As a result, the write-per-bit function can be used using the old mask data from the next mask write cycle.
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2.8.3 Execution of Mask Write Cycle
To execute the write-per-bit function, selectthe new mask data method or old mask data method, and set UWE
and LWE to low level at the falling edge of RAS of each write cycle (UWE controls the upper byte (W8 to W15/
108 to 1015) and LWE controls the lower byte (WO to W7/IOO to 107).). At this time, input the mask data to the
W pin in the write cycle using the new mask data. In the write cycle using the old mask data, as the mask data
set to the write mask register will be used, there is no need to input the mask data to the W pin.
This function is valid only at the falling edge of RAS. In the fast page/hyper page mode write cycle, the mask
data determined in the first RAS cycle for moving onto the next fast page/hyper page mode will be valid while
the fast page/hyper page mode write cycle continues.
2.9 Refresh Cycle
The refresh cycle of this product consists of the CAS before RAS refresh cycle and refresh cycle using external
address inputs (RAS only refresh and read/write refresh). The refresh period is the same as the 2M-bit dual port
graphics buffer (x 8),512 cycles/S ms.
2.9.1 Refresh Cycle Using External Address Input (RAS Only Refresh and Read/Write Refresh)
By specifying the row address using the 9 bits between AO to AS at the falling edge of RAS, setting CAS to
high level, and keeping CAS at high level while RAS is low level, the memory cells on the specified row address
(512 x 16 bits) can be refreshed. At this time, refresh is executed, WO to W15/100 to 1015 pins are kept at high
impedance, and information such as memory contents, register data, function settings, etc. are all also kept.
At the falling edge of RAS, all cycles whose CAS are high level input the external address. Therefore, in addition to the read/write cycle operations, etc. refresh operations similar to the RAS only refresh operations will be
performed. For this reason, in systems in which addresses in the memory are always increased or decreased,
it may not be necessary to perform refresh again.
When several devices exist on one bus, data will clash in the bus during the above readlwrite operations unless
each device is equipped with a buffer. Consequently, as it is necessary to set the I/O line to high impedance
beforehand during refresh, normally the RAS only refresh operation is used.
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2.9.2 CAS Before RAS Refresh Cycle (Including Hidden Refresh)
When CAS is setto low level atthe falling edge of RAS, the refresh address is supplied from the internal refresh
address counter. The internal refresh address counter is increased automatically each time this refresh cycle
is executed.
During this refresh cycle, functions of random access port and serial access port are selected as follows
according to the DSF, UWE, and LWE levels at the falling edge of RAS.
(1) When DSF is low level: Optional reset
All STOP register data become" 1" and the mask write cycle switches to the new mask data method.
(2) When DSF is high level and UWE, LWE are low level: STOP register set
The STOP register data is input from the AO to A8 pins at the falling edge of RAS.
(3) When DSF, UWE, and LWE are high level: No reset
Only refresh operations are performed and the function selection state is kept.
In all cases, the W/IO pin is kept at high impedance. When CAS and DT/OE are.kept low level while the mode
is changed to the CAS before RAS refresh cycle following the read cycle, and RAS is activated, the hidden refresh
cycle will be initiated. In this cycle, theW/IO pin does not become high impedance and the data read in the former
read cycle will be kept as it is.
Because internal memory operations are equivalent to CAS b~fore RAS refresh, no external addresses are
required.
Like CAS before RAS refresh, in the hidden cycle, functions will be selected according to the level ofDSF, UWE,
and LWE at the falling edge of RAS. Operations are guaranteed when DSF is low level and when DSF, UWE,
and LWE are high level.
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3. Serial Access Port Operations
There are two types of data transfer cycles-data transfer from the random access port to the serial access port
(read data transfer) and data transfer from the serial access port to the random access port (write data transfer).
There are also two types of data transfer methods-single data transfer and split data transfer.
To set the data transfer cycle, input high level to CAS and input low level to DT/OE at the falling edge of RAS.
The data transfer type differs according to the input levels of UWE, LWE, and DSF at the falling edge of RAS.
Table 3-1. Serial Access Port Operation Mode
At RAS Falling Edge
CAS DTIOE
H
L
Transfer Direction
Data Transfer Type
UWE, LWE DSF
H
L
Transfer
Destination
Single read data transfer
Random access
Serial access
port
Random access
port
H
L
H
H
Split read data transfer
port
H
L
L
L
Single mask write data transferNote
H
L
L
H
Split mask write data transferNote
Serial access
port
Note Write-per-bit function can be specified.
Remark H: High level, L: Low level
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3.1 Single Data Transfer Method
With this method, 512 words x 16 bits (whole memory range of serial access port) data is transferred at one
time. This method can be used in both write data transfer and read data transfer.
3.1.1 Single Read Data Transfer Cycle
This cycle transfers the SK-bit (512 words x 16 bits) data of the random access port to the serial access port
in one cycle.
(a) Setting of Single Read Data Transfer Cycle
To set the data transfer cycle, input a high level to CAS, UWE, and LWE and low level to DT/OE and DSF
at the falling edge of RAS.
Using the row address input to AO to AS at the falling edge of RAS, the memory cells (512 words x 16
bits) of the transfer source of the random access port can be selected. The address data input to AO to
AS at the falling edge of CAS will be latched as the TAP register data. Refer to 3.4 TAP Register.
(b) Execution of Single Read Data Transfer Cycle
To execute the data transfer cycle, set the single read data transfer cycle and then input a high level to
DT/OE and RAS.
When SC is active (edge control), data transfer will be executed at the rising edge of DT/OE. When SC
is inactive (self control), it will be executed atthe rising edge of RAS. Atthe same time, the serial address
pointer jumps to the start column (TAP) of the next serial read cycle, and the TAP register will be set the
empty state.
After the transfer is completed, the new serial access port data is output after tSCA following the rise of
the SC clock that occurs after tSOH if the SC is active, and after tSOHR if SC is inactive.
Caution When the single read data transfer cycle is executed while the serial access port is performing
serial write operations, the serial access port will start serial read operations at the rising edge
of RAS. Refer to 4. Electrical Characteristics Read Data Transfer Cycle (Serial Write ~ Serial
Read Switching) Timings.
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3.1.2 Single Mask Write Data Transfer Cycle
This cycle transfers 8K-bit (512 word x 16 bits) data ofthe serial access port to the random access port in one
cycle. Because UWE and LWE are low level atthe falling edge of RAS, the write-per-bitfunction always functions
in this transfer cycle. Refer to 2.8 Mask Write Cycle.
(a) Setting of Single Mask Write Data Transfer Cycle
To set this cycle, latch the data to be transferred to the serial access port, and then input a high level to
CAS and low level to DT/DE, UWE, LWE, and DSF at the falling edge of RAS. Because the write-per-bit
function functions in this transfer operation, for the new mask data method, the mask data must be
supplied to WO to W15 at the falling edge of RAS, and for the old mask data method, there is no need
to control the mask data.
The memory cells (512 words x 16 bits) ofthe transfer destination ofthe random access port are selected
using the row address input to AO to A8 at the falling edge of RAS. The address data input to AO to A8
at the falling edge of CAS is input as the TAP register data. Refer to 3.4 TAP Register.
(b) Execution of Single Mask Write Data Transfer Cycle
To execute this cycle, set the single write data transfer cycle and then input high level to RAS. Data will
be transferred at the rising edge of RAS. At the same time, the serial address pointer jumps to the start
column (TAP) of the next serial write cycle, and the TAP register will be set the empty state.
After the transfer is completed, the new serial access port data is latched atthe rising edge ofthe SC clock
that occurs after tSDHR.
Caution 1. When the single mask write data transfer cycle is executed while the serial access port is
performing serial read operations, the serial access port will start serial write operations at
the rising edge of RAS. Refer to 4. Electrical Characteristics Write Data Transfer Cycle (Serial
Read ~ Serial Write Switching) Timings.
2. Always make CAS low level in the write data transfer cycle and latch TAP. If write data
transfer is performed without setting TAP, serial access port operations cannot be ensured
until either one of the following points. If the SC clock is input during this time, the serial
register value also cannot be guaranteed.
• Until the falling edge of CAS during the write data transfer cycle
• Until the read data transfer cycle is executed again
Figure 3-1. Single Write Data Transfer and TAP Operation
Before transfer
Random Access Port . . . - - - - - - - - - ,
After transfer
Random Access Port . . . - - - - - - - - - - - . .
TAP register
I·Empty·1
Seria I Access Port
Serial Access Port
-"""T------.J
1..1
L
28
TAP
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3.2 Split Data Transfer Method
With this method, the 512 words x 16 bits (whole memory range of serial access port) data is divided into the
lower column (0 to 255) and upper column (256 to 511), each consisting of 256 words x 16 bits.
Because the columns are divided into upper and lower columns with this method, data transfer can be
performed on lower column (or upper column) while performing read/write operations in the upper column (or
lower column). For this reason, transfer timing design is easy. This transfer method can be used in both write
data transfer and read data transfer.
3.2.1 Split Read Data Transfer Cycle
This cycle divides the 8K-bit (512 words x 16 bits) data of the random access port into the lower and upper
columns and transfers them to the serial access port.
In this cycle, the serial read/write can be performed in the columns to which data is not transfer.
(a) Setting of Split Read Data Transfer Cycle
To set this cycle, input a high level to CAS, UWE, LWE and DSF, and low level to DT/OE at the falling edge
of RAS.
The memory cells (512 words x 16 bits) of the transfer source of the random access port are selected
using the row address input to AO to A8 at the falling edge of RAS. And the address data input to AO to
A7 at the falling edge of CAS is latched as the TAP register data of serial access port. There is no need
to control address data input to A8. Refer to 3.4 TAP Register.
(b) Execution of Split Read Data Transfer Cycle
To execute this cycle, set the split read data transfer cycle and then input the high level to RAS. Data will
be transferred at the rising edge of RAS. Data is transferred from the random access port to the serial
access port automatically at the column side where serial access port is inactive. To confirm the
transferred column side, check the output state of the QSF pin. Refer to 3.3.3 QSF Pin Output.
When the serial address pointer comes to the jump source address specified by the STOP register, the
serial address pointer jumps to the start column (TAP) ofthe serial read/write cycle atthe inactive column
side, and the TAP register will be set the empty state.
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3.2.2 Split Mask Write Data Transfer Cycle
This cycle divides the SK-bit (512 wordsx 16 bits) data of the serial access port into the lower and uppercolumns
and transfers them to the random access port.'
In' this cycle, serial read/write can be performed for columns to which data is not transferred.
Because UWE and LWE are low level at the falling edge of RAS, the write-per-bit function always functions
in this transfer cycle. Refer to 2.8 Mask Write Cycle.
(a) Setting of Split Mask Write Data Transfer Cycle
To set this data transfer cycle, input a high level to CAS and DSF and low level to DT/OE, UWE, and LWE
at the falling edge of RAS. Because the write-per-bit function functions in this transfer operation, for the
new mask data method, the mask data must be supplied to WO to W15 at the falling edge of RAs, and
for the old mask data method, there is no need to control the mask data.
The memory cells (512 words x 16 bits) of the transfer destination of the random access port are selected
using the row address input to AO to AS at the falling edge of RAs. The address data input to AO to A7
at the falling edge of CAS is input as the TAP register data. There is no need to control address data input
to AS. Refer to 3.4 TAP Register.
(b) Execution of Split Mask Write Data Transfer Cycle
To execute this cycle, set the split write data transfer cycle and then input high level to RAS. Data will
be transferred at the rising edge of RAs. Data is transferred from the serial access port to the random
access port automatically at the column side where the serial access port is inactive. To confirm the
transferred column side, check the output state of the QSF pin. Refer to 3.3.3 QSF Pin Output.
When the serial address pointer comes to the jump source address specified by the STOP register, the
serial address pointer jumps to the start column (TAP) of the serial read/write cycle at the inactive column
side, and the TAP register will be set the empty state.
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Figure 3-2. Split Mask Write Data Transfer and TAP Operations
After transfer (Upper column)
Before transfer (Upper coiumn)
Random Access Port . . . - - - - - - . - - - - - ,
Random Access Port
r-------.-----,
Transfer
destination
TAP register
l'Emp~'1
Serial Access Port
Serial Access Port
'------t--------'
c=J "'tillu....-'-_·_··. .1.
~ata 1
Serial write start
Before transfer (Lower column)
Random Access Port . . . - - - - - - . - - - - - ,
After transfer (Lower column)
Random Access Port
fL'-'----l TAP register
l'Emp~'1
s,,;,, """,
portp
Serial Access Port 1
L-...l_ _--'
C::C;data2
Seria I write start (TAP data 1)
3.3 Serial Read/Write
The serial access port (512K x 16 bits) is independent from the random access port and can perform read and
write operations. The serial access port performing single data transfer and split data transfer can not perform
read and write operations independently.
Caution When the power is turned on, the serial access port sets into the input (write) mode and the SIO
pin is the high impedance state.
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3.3.1 Serial Read Cycle
To set the serial read cycle, perform the single read data transfer cycle (The mode will not change in the split
read data transfer cycle.).
Execute the single read data transfer cycle and latch the data and TAP data. By inputting a clock signal to
the SC pin and inputting a low level to the SE pin, data will be output from the serial address pointer specified
by TAP register. The data synchronizes with the rising edge of the SC clock and is output from the 5100 to 51015
pin, and the data is kept until the next rising edge of the SC clock.
(a) Reading.Jump
The SE pin controls the 510 pin output buffer independently from the SC clock. By setting the SE pin to
high level even while inputting the SC clock, 5100 to 51015 pins become high impedance. But the
operations of serial address pointer will be continued while the SC clcck is being input even though
reading has been prohibited from SE pin. Reading-jump of the column can be performed using this
function.
3.3.2 Serial Write Cycle
To set the serial write cycle, perform the single write data transfer cycle (The mode will not change in the split
write data transfer cycle.). To prevent the transfer data from being written in the memory cell of the random
access port, set all bits of the mask data to "0" and control the mask data.
Execute the single write data transfer cycle and set the serial write cycle. By inputting the clock signal to the
SC pin and inputting a low level to the SE pin, data can be latched from the serial address pointer specified by
TAP register. The data synchronizes with the rising edge of the SC clock and is input from 5100 to 81015 pins.
Be sure to follow the specifications for the setup time (tsES) and hold time (tSEH) of SE pin for the SC clock.
(a) Writing-Jumps (Intermittent Writing)
The SE pin controls writing operations independently from the SC clock. By setting the SE pin to high
level even while inputting the SC clock, writing will not be executed. But the operations of serial address
pointer will be continued while the SC clock is being input even though writing has been prohibited from
SE pin. These functions enable writing-jumps (intermittent writing) to be performed. The masked data
is kept as the old data.
3.3.3 QSF Pin Output
QSF pin determines whether the serial address pointer is at the upper column side (addresses 256 to 511)
or the lower column side (addresses 0 to 255) at the rising edge of the following SC clock during serial read or
write. In other words, it outputs the uppermost bit (AS) of the column address of the serial address pointer.
The following table shows the aSF pin output state and the access pointer of followil19 SC clocks.
32
Access Address of Following SC clock
aSF Output
Addresses 0 to 255
Low level
Addresses 256 to 511
High level
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3.4 TAP (Top Access Point) Register
The TAP register is a data register which specifies the start address (first serial address point
=TAP) of the
serial read or serial write.
Set data -to this register each time' a transfer cycle is executed.
3.4.1 Setting of TAP Register
The data input to AO to A8 at the falling edge of CAS during the setting of a transfer cycle is set as the TAP
register data. By executing the transfer cycle, the start address of the following serial read (or write) operations
is specified by the data of the TAP register and the TAP register will be kept in the empty state until the TAP register is set again.
In the split data transfer cycle, because the inactive serial access port column addresses are specified by the
data of the TAP register automatically, there is no need to control the A8 data.
Caution When the TAP register is empty, the address following the 511 serial address point will be o. In
addition, because the serial address pointer will not jump to the column specified by the STOP
register, the binary boundary jump function cannot be used. Refer to 3.6 Binary Boundary Jump
Function.
3.5 STOP Register
The STOP register is a data register which determines the column of the jump source when jumping to a
different column side (lower column or upper column) in the split data transfer cycle. Five types of columns can
be selected for starting jump (jumping is possible at 2,4,8, 16, and 32 points). The following table shows the
correspondence between the column at the jump source and data of the STOP register.
Once set, the STOP register data is kept until it is set again.
3.5.1 Setting of STOP Register
To set the STOP register, set UWE and LWE to low level at the falling edge of RAS in the CAS before RAS
refresh cycle. The data input to AO to A7 will be input as the STOP register data.
Table 3-2. STOP Register Data and Jump Source Column
STOP Register Data
DiviBit
A7 A6 A5 A4 A3 to AO sian Width
1
1
1
1
1
1/2
256
Jump Source Bit Column (Decimal Number)
255
511
0
1
1
1
1
1/4
128
127,255
383,511
0
0
1
1
1
1/8
64
63, 127, 191,255
319,383, 447, 511
0
0
0
1
1
1/16
32
31,63,95,127,159,191,223,255
287,319,351,383,415,447,479,511
0
0
0
0
1
1/32
16
15,31,47,63,79,95,111,127,143,159,175,191,207,223, 239,255
271, 287, 303,319,335,351,367,383,399,415,431,447,463,479,495,511
Remark A8: Don't care.
Caution When the power is supplied, all STOP register data will be set to all "1".
33
NEe
gPD482444,482445
3.6 Binary Boundary Jump Function
This function causes the serial address pointer jump to the TAP specified by the TAP register when the pointer
moves to a column specified by the STOP register (split data transfer).
This function cannot be used when the jump destination address is not set (TAP register is empty).
This function facilitates tile map application which divides the screen into tiles and manages data for each
tile.
3.6.1 Usage of Binary Boundary Jump Function
After setting the STOP register, execute the single read (or write) data transfer and initialize the serial access
port. The initialization process will switch the serial access port read (or write) operations, set TAP, set the serial
access port data, and set the TAP register to empty. By inputting the serial clock in this state, the serial access
port will read (or write) operations from TAP in ascending order of address. Because the TAP register is in the
empty state, the address at the jump source set by the STOP register will be ignored, and the serial address
pointer will move on.
When the column to be jumped approaches, execute split data transfer and set new TAP data in the TAP
register. The serial pointer will jump at the desired jump source address. Jump can be controlled freely by
repeating these operations.
3.7 Special Operations
3.7.1 Serial Address Set Operations
Because the serial address counter is undefined when the power up, the serial access port operations when
the SC clock is input are not guaranteed. Execute single read (or write) transfer after turning on the power. The
serial access port will be initialized, enabling serial access port operations to be performed.
3.7.2 Lap Around Operations
If all the data of the register is read (write) during data transfer while the serial read (write) cycle is being
executed, the serial pointer will repeat 0 to 511.
3.7.3 Cycle After Power On
Execute the dummy cycle eight times more than 100 JlS after Vee reaches the specified voltage in the recommended operation conditions.
If RAS, CAS, DT/OE, UWE, LWE are kept at high level when the power is turned on, the following will be set
automatically.
• Serial access port ........ Input mode, 510: High impedance
• Color register ............... Undefined
• Mask register ............... AII "1"
• TAP register ................. Undefined
• STOP register .............. AII "1"
34
NEe
yPD482444,482445
4. Electrical Characteristics
4.1 ,uPD482444, 482445 (Power Supply Voltage Vee
= 5 V ± 10 'Yo)
Absolute Maximum Ratings
Symbol
Rating
Unit
Pin voltage
Vr
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
mA
Power dissipation
Po
1.5
W
TA
o to 70
°C
Tstg
-55 to +125
°C
Parameter
Operating ambient temperature
Storage temperature
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
in the operational sections of this characteristics. Exposure to Absolute Maximum rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
MIN.
TYP.
MAX.
Unit
Supply voltage
Vee
4.5
5.0
5.5
V
High level input voltage
VIH
2.4
5.5
V
Low level input voltage
VIL
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
°C
Parameter
35
NEe
.uPD482444,482445
DC Characteristics 1 (Recommended operating conditions unless otherwise noted)
Parameter
Symbol
Input leakage current
Test conditions
TYP.
MAX.
Unit
-10
+10
!1A
WilD, SID, QSF are inactive,
-10
+10
!1A
VOH (R)
= 0 V to 5.5 V
IOH (R) =-1.0mA
2.4
VOL (R)
IOL (R)
= 2.1mA
VOH (S)
IOH (S)
= -1.0mA
VOL(S)
IOL (S)
= 2.1mA
ilL
VIN
= 0 V to 5.5 V,
MIN.
Other inputs are 0 V
Output leakage current
IOL
VOUT
Random access port
V
high level output voltage
Random access port
0.4
V
low level output voltage
Serial access port
2.4
V
high level output voltage
Serial access port
0.4
V
MAX.
Unit
pF
low level output voltage
Capacitance ITA
= 25 ·C, f = 1MHz)
Parameter
Test conditions
CII
RAS, CAS, UWE, LWE, DT/DE, DSF, SE, SC
S
CI2
AO to AS
5
Input/Output Capacitance
Cio
WilD (0 to 15), SID (0 to 15)
7
Output Capacitance
Co
QSF
7
Input Capacitance
36
MIN.
TYP.
Symbol
"
pF
pF
NEe
yPD482444,482445
DC Characteristics 2 (Recommended operating conditions unless otherwise noted)Note 1
jlP0482444·60 jlP0482444· 70
Serial
Random Access Port
Access Port
Symbol /lP0482445·60 jlPD482445· 70 Unit Conditions
Standby Active
Random Read/Write Cycle
RAS, CAS cycle,
tRC =tRC (MIN.), 10 = OmA
0
Standby
RAS = CAS = V'H,
DouT = high impedance
0
RAS only refresh cycle
RAS cycle, CAS = V'H,
tRC =tRC (MIN.)
0
Fast/Hyper page mode cycle
RAS = VIL, CAS cycle,
tpc =tpc (MIN.) or tHPC =tHPC (MIN.)
0
CAS before RAS refresh cycle
tRC =tRC (MIN.)
0
0
0
0
0
0
Data transfer cycle
tRC =tRC (MIN.)
0
0
Color/Mask write register set cycle
tRC =tRC (MIN.)
0
0
Flash write cycle
IRc = tRC (MIN.)
0
0
Block write cycle
IRc =tRC (MIN.)
0
0
Fast/Hyper page mode block write cycle
tpc = tpc (MIN.) or tHPC = tHPC (MIN.)
0
0
MIN.
MAX.
MIN.
MAX.
Icc,
110
95
1cC7
130
110
Icc2
10
10
mA
Nota 2
Icca
50
45
mA
Nota 2
IcC3
100
85
mA
Nota 3
Icc9
140
120
Icc.
120
105
mA
Note 4, 5
Icc,o
150
130
Iccs
100
95
Iccll
130
120
Icco
120
105
ICC12
150
130
Iccll
90
80
Icc,.
120
105
Icc,s
90
80
Icc,.
120
105
Icc17
110
100
Icc,s
140
125
Icc,9
135
120
Icc20
155
135
mA
mA
mA
mA
mA
mA
mA
Note 4, 5
Notes 1. No load on W/IO, 510, QSF. The current consumption actually used depends on the output load
and operating frequency of each pin.
2. A change in row addresses must not occur more than once in tRC
=tRC (MIN.).
3. When the address input is set to VIH or VIL during the tRAS period.
4. Value when the address in tpc one cycle is changed once when JlPD482444 tpc
=tpc (MIN.).
=tHPC (MIN.).
5. Value when the address in tHpc one cycle is changed once when JlPD482445 tHPC
37
NEe
yPD482444,482445
AC Characteristics (TA
= 0 to 70 ·C, Vee = 5.0 V ± 10 %, GND = 0 VI Notes 1, 2, 3, 4
(1/4)
(Common for PPD482444, 4824451
PPD482444-60 PPD482444-70
Parameter
Symbol PPD482445-60 PPD482445-70 Unit
Condition
MIN. MAX. MIN. MAX.
70
ns
NoteS
18
18
ns
NoteS
ns
NoteS
Access time from RAS
tRAC
60
Access time from CAS
tCAC
Access time from column address
tAl<
30
35
Access time from CAS trailing edge
tAcp
30
35
ns
Access time from OE
tOEA
18
18
ns
Serial output access time from SC
tSCA
15
17
ns
Serial output access time from SE
tSEA
15
17
ns
Output disable time from SE high
tSEZ
0
15
ns
Random read or write cycle time
tRC
110
tRWC
160
Transition time (Rise/Fall)
IT
3
RAS precharge time
tRP
40
RAS pulse width
tRAS
60
tRASP
60
RAS hold time
tRSH
CAS precharge time
Read modify-write cycle time
15
0
130
ns
180
35
3
Note 6
ns
35
ns
50
ns
10,000
70
10,000 ns
125,000
70
125,000 ns
15
18
ns
tCPN
10
10
ns
tcp
10
10
·ns
CAS hold time
tCSH
60
70
RAS to CAS delay time
tRCD
25
30
CAS high to RAS low precharge time
tCRP
10
10
ns
RAS high to CAS low precharge time
tRpc
10
10
ns
Row address setup time
tASR
0
0
ns
Row address hold time
tRAH
15
15
ns
Column address setup time
tASC
0
0
ns
Column address hold time
tCAH
10
10
ns
RAS to column address delay time
tRAO
15
Column address to RAS lead time
tRAL
30
35
ns
Read command setup time
tRCS
0
0
ns
(Non page model
RAS pulse width
(Fast page/Hyper page mode)
(Non page mode)
CAS precharge time
(Fast page/Hyper page mode)
38
40
30
15
ns
50
35
ns
ns
Note S
N(!te S
NEe
,uP0482444, 482445
(2/4)
(Common for PPD482444. 482445)
Parameter
,uPD482444-60 ,uPD482444-70
Symbol ,uPD482445-60 JlPD482445-70 Unit
Condition
MIN. MAX. MIN. MAX.
tRRH
0
0
ns
Note 7
tRCH
0
0
ns
Note 7
OE hold time after RAS high
tORH
10
10
ns
OE hold time after CAS high
tOCH
10
10
ns
Write command setup time
twcs
0
0
ns
Write command hold time
twCH
12
12
ns
Write command pulse width
twp
12
12
ns
Write command to RAS lead time
tRWL
20
20
ns
Write command to CAS lead time
tCWL
15
15
ns
Data in setup time
tos
0
0
ns
NoteS
Data in hold time
toH
15
15
ns
Note S
Refresh period
tREF
CAS to UWE. LWE delay time
tCWD
40
40
ns
Note 9
Read command hold time after
RAS high
Read command hold time after
CAS high
8
8
Note 9
ms
RAS to UWE. LWE delay time
tRWO
85
90
ns
Note 9
Column address to UWE. LWE delay time
tAWD
55
55
ns
Note 9
CAS setup time
tCSR
5
5
ns
tCHR
10
10
ns
Masked byte write setup time
tMCS
0
0
ns
Masked byte write to RAS hold time
tMRH
0
0
ns
Masked byte write to CAS hold time
tMCH
0
0
ns
DT low setup time
toLS
0
0
ns
(for CAS before RAS refresh cycle)
CAS hold time
(for CAS before RAS refresh cycle)
DT low hold time after RAS low
tROH
55
60
ns
Note 10
DT low hold time after RAS low
tAOHS
15
15
ns
Note 10
DT low hold time after CAS low
tCOH
20
20
ns
Note 10
DT low hold time after address
tAoo
25
25
ns
Note 10
SC high to DT high
tsoo
0
0
ns
Note 10
SC high to CAS low
tssc
10
10
ns
Note 10. 14. 15
SC low hold time after DT high
tSOH
60
60
ns
Note 10
39
NEe
uPD482444,482445
(Common for PPD482444, 482445)
Parameter
(3/4)
JlPD482444-60 JLPD482444-70
Symbol JlPD482445-60 JLPD482445-70 Unit
Condition
MIN. MAX. MIN. MAX.
SC low hold time after DT high
tSOHA
60
60
ns
DE high to data in setup delay time
tOEO
15
15
ns
DE high hold time after
tOEH
0
0
ns
Serial clock cycle time
tscc
20
22
ns
SC pulse width
tSCH
5
5
ns
SC precharge time
tSCL
5
5
ns
SE low to serial output setup
tsoo
3
5
ns
tSOH
3
5
ns
Note 10, 14
UWE, LWE low
delay time
Serial output hold time after
SC high
40
DT high setup time
tOHS
0
0
ns
DT high hold time
tOHH
15
15
ns
DT high to RAS high delay time
tOTA
0
0
ns
DT high pulse width
tOTP
20
20
ns
DE to RAS inactive setup time
tOES
0
0
ns
Write-per-bit setup time
twas
0
0
ns
Write-per-bit hold time
twaH
15
15
ns
DSF setup time from RAS
tFAS
0
0
ns
DSF hold time from RAS
tFAH
15
15
ns
DSF setup time from CAS
tFCS
0
0
ns
DSF hold time from CAS
tFCH
12
12
ns
Write-per-bit selection setup time
tws
0
0
ns
Write-per-bit selection hold time
twH
15
15
ns
SE pulse width
tSEE
5
5
ns
SE precharge time
tSEP
5
5
ns
SE setup time
tSES
0
0
ns
SE hold time from SC
tSEH
10
10
ns
Serial data in setup time
tSIS
0
0
ns
Serial data in hold time
tSIH
10
10
ns
Serial input disable time from SC
tSIZ
0
0
ns
Serial output disable time from RAS
tSAZ
0
0
ns
Note 10
NEe
j.lPD482444,482445
(4/4)
(Common for IJPD482444. 482445)
Parameter
pPD482444·60 pPD482444·70
Symbol PPD482445·60 pPD482445·70 Unit
Condition
MIN. MAX. MIN. MAX.
Serial input enable time from RAS
tSZH
40
40
ns
SC setup time from RAS
tSRS
10
10
ns
Note 13, 14, 15
SC hold time from RAS
tSRH
10
10
ns
Note 13
Propagation delay time from
tpo
0
20
0
20
ns
tRao
0
80
0
95
ns
teao
0
60
0
65
ns
toaD
0
30
0
30
ns
toaR
0
40
0
40
ns
SC to QSF
Propagation delay time from
RAS to QSF
Propagation delay time from
CAS to QSF
Propagation delay time from
DT/OE to QSF
Propagation delay time from
RAS high to QSF
41
NEe
gPD482444,482445
(,uPD482444 Only)
JLPD482444-60 JLPD482444-70
Parameter
Symbol
MIN. MAX. MIN. MAX.
Unit
Condition
Output disable time from CAS high
tOFF
0
15
0
15
ns
Note 6,11
Output disable time from OE high
tOEZ
0
15
0
15
ns
Note 6,11
Output disable time from LWE, UWE low
twEZ
0
15
0
15
ns
Note 6,11
Write command pulse width
twpz
12
12
ns
Note 11
tpc
35
40
ns
tPRWC
90
95
ns
tCAS
15
15
100,000 ns
Fast page mode cycle time
Fast page mode read modify
write cycle time
CAS pulse width
100,000
(,uPD482445 Only)
IlPD482445-60 JLPD482445-70
Parameter
Symbol
·Unit
MIN. MAX. MIN. MAX.
Output hold time from CAS
tOHC
3
Output disable time from RAS high
tOFR
0
ns
5
15
0
15
ns
Note 6,12
ns
Note 6,12
Output disable time from CAS high
tOFC
0
15
0
15
Output disable time from OE high
tOEZ
0
15
0
15
ns
Note 6,12
Output disable time from LWE, UWE low
twEZ
0
15
0
15
ns
Note 6,12
Write command pulse width
twPz
12
12
ns
Note 12
Hyper page mode cycle time
tHPC
30
35
ns
tHPRWC
80
90
ns
tHCAS
10
10
100,000 ns
Hyper page mode read modify
write cycle time
CAS pulse width
42
Condition
100,000
NEe
yPD482444,482445
Notes 1. All applied voltages are referenced to GND.
2. After power up, wait more than 100 f.JS and then, execute eight RAS cycles as dummy cycles to
initialize internal circuit.
3. Measure at IT
=5 ns
4. AC characteristic measuring conditions
(2) Output voltage determined
(1) Input voltage, timing
V,HIM,N,
= 2.4 V
VILIMAXI
= 0.8 V
. ____ ~-3.0V
:L
---d:
I
I
1
J
l.
I
I
VOHIMINI
= 2.0V
VOLIMAX.I
= 0.8 V
-i-:---11-'-
tr = 5 ns
tr = 5 ns
(3) Output load conditions
Random Access Port
Serial Access Port
TVCC
Vcc
~ 1.838!l
1.8380
W/IO - - - . - - - - ;
SIO
50 pF
9930
9930
5. For read cycle, access time is defined as follows:
Input conditions
Access time
Access time from RAS
tRAD S tRAD (MAX.) and tRCD S tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAO > tRAD (MAX.) and tRCD S tRCD (MAX.)
fAA (MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA, tCAC) is to be used for finding
out data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.)
will not cause any operation problems.
6. tSEz, tOEZ, twEZ, tOFF, tOFR, and tOFC define the time when the output achieves the condition of high
impedance and is not referenced to VOH or VOL.
7. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
S. These parameters are referenced to the following points.
(1) Early write cycle
(2) Late write cycle
The falling edge of CAS
: The falling edge of UWE, LWE
(3) Read modify write cycle : The falling edge of UWE, LWE
9. twcs ~ twcs (MIN.) is the condition for early write cycle to be set. DouT becomes high impedance
during the cycle.
tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.), are conditions for read modify write cycle
to be set. The data of the selected address is output to DOUT.
If any of the above conditions are not met, pin WIIO will become undefined.
43
NEe
uPD482444,482445
Notes 10. One of the following specifications will be valid depending on the type ofread data transfer method
used.
(1) DT/OE edge control: Satisfy the following specifications.
• For DT/OE edge inputs : tRDH, tCDH, tADO, tOTR
: tsoo, tSDH
• For SC inputs
(2) Self control: Satisfy the following specification.
• For DT/OE edge inputs : tROHS
• For SC inputs
: tssc, tSDHR
11. Control pins CAS, OE, UWE, LWEtoset pin W/IO to high impedance. Becausethetimingsatwhich
CAS and OE are set to high level and UWE and LWE are set to low level affect the high impedance
state, the specifications will change as follows.
(1) When CAS is set to high level at OE (low level) and UWE and LWE (high level) at the end of
the read cycle: tOFF is valid
(2) When UWE and LWE are set to low level at CAS (low level) and OE (low level) at the end of
the read cycle: twEZ and twpz are valid
(3) When OE is set to high level at CAS (low level) and UWE and LWE (high level) at the end of
the read cycle: tOEZ is valid
12. Control pins RAS, CAS, OE, UWE, LWE to set pin W/IO to high impedance. Because the timings
at which RAS, CAS, and OE are set to high level and UWE and LWE are set to low level affect the
high impedance state, the specifications will change as follows.
When controlling RAS and CAS, the output cannot be made high impedance unless both pins are
set to high. There is difference between tOFC and tOFR, because RAS and CAS control is specified
from the rising edge of the slower one.
(1) When RAS is set to high level after CAS is set to high level at OE (low level) and UWE and
LWE (high level) at the end of the read cycle: tOFR is valid
(2) When CAS is set to high level after RAS is set to high level at OE (low level) and UWE and
LWE (high level) at the end of the read cycle: tOFC is valid
(3) When UWE and LWE are set to low level at RAS, CAS (low level) and OE (low level) at the
end of the read cycle: twEZ and twpz are valid
(4) When OE is set to high level at RAS, CAS (low level) and UWE and LWE (high level) at the
end of the read cycle: tOEZ is valid
13. The tSRS and tSRH in the hidden refresh cycle, CAS before RAS refresh cycle (STOP register set cycle
and optional reset cycle) are specified to guarantee the serial port operations until the transfer
cycle is executed after the STOP register value is changed. When the STOP register value is n9t
to be changed, or when the binary boundary jump function is not used (when the TAP register
is empty), tSRS and tSRH will not be specified.
14. tssc (split read data transfer cycle) and tSRS (split write data transfer cycle) are specified atthe rising
edge of SC which reads/writes the address of the jump source in the binary boundary jump
function. tSOHR (split read data transfer cycle and split write data transfer cycle) is specified at the
rising edge of SC which reads/writes the address ofthe jump destination in the binary boundary
jump function. The rising edge of these SCs cannot be input in periods (1) and (2).
(1) Split read data transfer cycle: Period from the rising edge of the SC specifying tssc to that
ofthe SC specifyi ng tSOHR (Refer to Note 2 Split Read/Write Data Transfer Cycle Timing Chart.)
(2) Split write data transfer cycle: Period from the rising edge of the SC specifying tsRS to that
of the SC specifying tSOHR (Referto Note 2 Split Read/Write Data Transfer Cycle Timing Chart.)
15. Limitations of split read/write data transfer cycle during serial write operations. When split read/
write data transfer is performed while serial write is executedforthe column specified by the STOP
register, serial write operations cannot be guaranteed.
44
NEe
yPD482444,482445
Read Cycle (JIf'D4824441
tRe
tRP
tRAS
RAS (Input)
V'HVILtesH
tReD
CAS (Input)
tRSH
V,HV,LtRAL
teAH
'lAse
Address (Input)
V,HV'L-
COL.
tRes
UWE (input)
V'HV,LtRes
LWE (Input)
V,HV'L-
DT/OE (Input) V,HV,L-
teAC
________
WOto W151
VOHIOOtoI015(Output) VOL-
_______________________ _
DATA OUT
tFRS
DSF (input)
,:!i~~.~
tFRH
V,HV,L-
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, SIO pins in this cycle.
45
NEe
,uP0482444,482445
Read Cycle (Extended data output: ppD482445.)
tRC
tRP
tRAS
RAS (Input) V'HVILtCSH
tRCo
tRSH
H
CAS (Input) V,HV,LtRAL
tCAH
tAsc
Address (Input) V,HV'L-
COL.
tACS
UWE (Input)
V,HV,LtRCS
LWE (Input)
V,HV,L-
DT/OE (Input) V,HV,LtOEZ
tOFC
tOFR
tCAC
WOtoW151
VOH100to 1015(Output) VOL-
--------
tFRS
--------~~~~-----------------------
DATA OUT
tFRH
V'HDSF (Input) V,L-
Remark Because the serial access port operates independently of the random access port. there is no need
to control the SC. SE. 510 pins in this cycle.
46
NEe
uPD482444,482445
Early Write Cycle/Early Block Write Cycle
tRC
RAS (Input) VV'H -
IL-
V,HCAS (Input) V,L-
V,H-
Address (Input) V,L-
--
V,H-
-
V,H-
UWE (Input) V,L-
LWE (Input) V'L-
--
V,H-
WO to W151
V,H-
DT/OE (Input) V,L-
100 to 1015 (Input) V,L-
V,HDSF (Input) V,L-
Note tCAS for the JlPD482444
tHCAS for the JlPD482445
Remarks 1. When D5F is high level: Block write cycle
When D5F is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the 5C, 5E, 510 pins in this cycle.
47
NEe
,uPD482444,482445
Upper Byte Early Write Cycle/Upper Byte Early Block Write Cycle
tRC
tRAS
RP
-
V,HRAS Iinput) V,LtCSH
tRCO
tCRP
tRSH
tCPN
V,H- -----ir--+l'-------"
CAS !Input) V'L-
_
tRAL
V,HAddress !Input) V,L-
--
V,H-
--
V'H-
--
V,H-
UWE !Input) V'L-
LWE !Input) V'L-
DT/OE !Input) V'L-
W8toW1S/
V,H108 to 101 S!lnput) V'L-
V,H-
DSF !Input) V'L-
~~~
____-L~LJ
Note tCAS for the JLPD482444
tHCAS for the JlPD482445
Remarks 1. WO to W7/IOO to 107: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected, input the column selection data to DATA IN.
5. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
48
NEe
uPD482444,482445
Lower Byte Early Write Cycle/Lower Byte Early Block Write Cycle
tRC
tRP
tllAS
-
V,H-
RAS (Input) VILtCSH
tRCD
-
tRSH
tCRP
tCPN
V,H-
CAS (Input) V,LtRAL
V,H-
Address (Input) V,L-
_
V,H-
UWE (Input) V,L-
--
V,H-
--
V,H-
'r7I:-,j~-44~+--,-~~I+-----------===~~"t'"""<~..--
LWE (Input) V,L-
DT/OE (Input) V'L-
wo to W71
V'H-
100 to 107 (Input) V'L-
V,H-
DSF (Input) V,L-
................" - -_ _................1
Note tCAS for the JlPD482444
tHCAS for the JLPD482445
Remarks 1. W8 to W15/108 to 1015: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected, input the column selection data to DATA IN.
5. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
49
NEe
gPD482444,482445
Late Write Cycle/Late Block Write Cycle
tRC
tRAS
-
RAS
tRP
V,H(Input) VILtCSH
tRCD
_
V,H-
---ir--t-I------,
tRSH
tCAS. tHCAS"'"
CAS (Input) VILtRAL
Address
V,H(Input) VIL-
--
V,H-
-,
LWI:
V,H(Input) VIL-
--
V,H-
UWE (Input) VIL-
DT/OE (Input) VIL-
WO to WI5t
V,H100 to 1015 (Input) VIL-
V,H-
DSF (Input) VIL~~~----~~~
Note tCAS for the ,uPD482444
tHCAS for the ,uPD482445
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
50
NEe
.uPD482444,482445
Upper Byte Late Write Cycle/Upper Byte Late Block Write Cycle
tRC
tRAS
tRP
RAS (Input)
tCSH
CAS (Input)
Address (Input)
UWE (Input)
V,HV,L-
V,HV,L-
LWE (Input)
DT/OE (Input)
W8toW15/
V,H108 to 1015 (Input) V,L-
DSF (Input)
Note tCAS for the JLPD482444
tHCAS for the JLPD482445
Remarks 1. WO to W7/IOO to 107: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected, input the column selection data to DATA IN.
5. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
51
NEe
,uPD482444, 482445
Lower Byte Late Write Cycle/Lower Byte Late Block Write Cycle
tRe
tRAS
tRP
V'HRAS (Input) VlltCSH
V'HCAS (Input) Vll-
V'H-
Address (Input) V'L-
-V'HUWE (Input) V'L-
V'HLWE (Input) V'L-
wo to W7/
V'H100 to 107 (Input) V'L-
DSF (Input) V'H-
V'L-
Note tCAS fO'r the PPD482444
tHCAS for the pPD482445
Remarks 1. W8 to W15/108 to 1015: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected, input the column selection data to DATA IN.
5. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle ..
52
NEe
uPD482444,482445
Read Modify Write Cycle/Read Modify Block Write Cycle
tRWC
tRAS
V,H-
RAS (Input) V,L-
V,H-
CAS (I n put) V'L-
V,H-
Address (Input) V'L-
V'H-
UWE (Input) V,L-
V,HLWE (Input) V'L-
-
V'H-
DT/OE (Input) V,L-
V,HWO {
to
W15l
100
to
1015
(Input) V,LtOEZ
(Output) VVO H -
OL-
__________
~2~~~
________ _
DATA OUT
V,H-
DSF (Input) V,L-
Note tCAS for the ,uPD482444
tHCAS for the ,uPD482445
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
53
NEe
pPD482444,482445
Read Modify Upper Byte Write Cycle/Read Modify Upper Byte Block Write Cycle
tRWC
tRAC
V,HRAS (Input) V,LtCRP
tCSH
tRCO
tRSH
tCAS. tHCAs"-
V,HCAS (Input) V,L-
tCPN
tRAL
V,HAddress (Input) V,L-
V,HUWE (Input) V,L-
V,HLWE (Input) V,L-
V,HDT/OE (Input) V,L-
V,H(Input) V,L-
WO
to
¥)---
W7/ {
100
to
107
tOE2
_________ __________
VOH(Output) VOL-
~~D~~
______ _
tRAC
tOED
tAA
1----t+--1l-7tCA:.:.C~
W8
to
{
W15/
V,H(Input) V,LtOE2
)08
to
1015
VOH(Output) VOL-
V,HDSF (Input) V,L-
54
High-Z
--------------------~~~~--------
NEe
Note
uPD482444,482445
tCAS
for the JlPD482444
for the JlPD482445
tHCAS
~emarks
1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
55
NEe
JLPD482444,482445
Read Modify Lower Byte Write Cycle/Read Modify Lower Byte Block Write Cycle
tRWC
tRAC
RAS (Input)
V,HV'LtCSH
tCRP
tCPN
tRSH
tRCO
tCAS.tH~
V,H-
CAS (Input) V,LtRAL
VII.-
Address (Input) V,L-
UWE (Input)
V,HV,LtRWO
tCWL
tAwo
tcwo
LWE (Input)
V,HV'LtOEH
V,H-
DT/OE (Input) V,LtOED
tos
WO
tOH
V'H-
(Input) V,L-
to
tRAC
tAA
t----t-l-l-:'tCA=-C-l
W8
V,H-
(Input) V,L-
to
W15/{
1015
VOH-
(Output) VOL-
V,H-
DSF (Input) V,L-
56
_______ _
tOED
High-Z
tOEZ
108
to
X}---
~
____________________
VOH(Output) VOL-
b
to
107
~
100
~
W7/ {
DATA ____________________ tllg!':Z_______ _
OUT
NEe
yPD482444,482445
Note tCAS for the J.LPD482444
tHCAS for the J.LPD482445
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
57
NEe
pPD482444,482445
Fas1 Page Mode Read Cycle IJLPD482444)
tRC
tRASP
-
tRP
V,H-
RAS (Input) V,L-
tRCD-
-
V,HCAS (Input) V,L-
tCAS
-++t----'"
V,HAddress (Input) V,L-
--
V,H-
UWE (Input) V'L-
I-£-'-++...J
LWE (Input) V,H-
V,L - I-.I.~-M,L.J
-
-
V,H- -+-i-i-+--~"'T-M.
DT/OE (Input) V,L-
RA
WOtoW1S/
VOH100 to I01SIOutputi VOL- - - - -tFRS
DATA OUT.,.
DATA OUT "N"
tFRH
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, SID pins in this cycle.
5B
NEe
gPD482444,482445
Hyper Page Mode Read Cycle (Extended data output: PPD482445)
tRC
tRASP
tRP
V,HRAS (Input) V'L-
tRco
tHCAS
V,HCAS (Input) V'L-
V,HAddress (Input) V,L-
-V,HUWE (Input) V'L-
L...L-'-+-TL.J
-V,HDT/OE (Input) V,L-
WOtoW15/
VOH100 to 1015 (Output) VOL- -- -- tFRS
DATA OUT 'N'
tFRH
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, SID pins in this cycle.
59
NEe
yPD482444,482445
Fast Page, Hyper Page Mode Early Write Cycle/Fast Page, Hyper Page Mode Early Block Write Cycle
V,HRAS.(lnput) VIl-
V'HCAS (Input) V'l-
V,HAddress (Input) V,l-
__
V'HUWE (Input) V'l-
-VIHLWE (Input) V,l-
-V,HDT/OE (Input) V'l-
WO to W151
V'H100 to 1015 (Input) V,l-
V,HDSF (Input) V'l-
Notes 1. tpc for the ¢>D482444
tHPC for the 1LPD482445
2. tCAS for the 1LPD482444
tHCAS for the ¢>D482445
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
60
NEe
gPD482444,482445
Fast Page, Hyper Page Mode Upper Byte Early Write Cycle/
Fast Page, Hyper Page Mode Upper Byte Early Block Write Cycle
-
V,H-
-
V,H-
RAS (Input) V'L-
CAS (Input) V,L-
V,HAddress (Input) V,L-
-V'HUWE (Input) V,L-
-V,HLWE (Input) V,L-
WBto W1SI
V,H108 to 101S (Input) V,L-
V,HDSF (Input) V,L-
Notes 1. tpc for the JlPD482444
tHPC for the JlPD482445
2. tCAS for the JLPD482444
tHCAS for the JLPD482445
Remarks 1. WO to W7/IOO to 107: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected, input the column selection data to DATA IN.
S. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
61
NEe
yPD482444,482445
Fast Page, Hyper Page Mode Lower Byte Early Write Cyclel
Fast Page, Hyper Page Mode Lower Byte Early Block Write Cycle
-
V,H-
_
V,H-
RAS (Input) VIl-
-+-++----""\1
CAS (Input) V,L-
V,HAddress (Input) V,L-
UWE (Input) VV'H -
IL-
__
V,HLWE (Input) V'L-
--
V,H-
DT/OE (Input) V'L-
WOtoW7!
V,H100 to 107 (Input) V'L-
V,HDSF (Input) V,L-
_~_..Ij-L...t..J
Notes 1. tpc for the PPD482444
tHPC for the
~PD482445
2. tCAS for the PPD482444
tHCAS for the PPD482445,
Remarks 1. W8 to W15/108 to 1015: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected, input the column selection data to DATA IN.
5. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
62
NEe
gPD482444,482445
Fast Page, Hyper Page Mode Late Write Cycle/Fast Page, Hyper Page Mode Late Block Write Cycle
V,Hf.lAS (Input) V,L-
V,HCAS (Input) V'L-
V,HAddress (Input) V,L-
-V,HUWE (Input) V,L-
_
V'HLWE (Input) V,L-
-V,HDT/OE (Input) V,L-
WOtoW15{
V,H100 to 1015 (Input) V,L-
V,HDSF (Input) V,L-
Notes 1. tpc for the ,uPD482444
tHPC for the ,uPD482445
2. tCAS for the ,uPD482444
tHCAS for the ,uPD482445
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
63
NEe
yPD482444,482445
Fast Page, Hyper Page Mode Upper Byte Late Write Cycle/
Fast Page, Hyper Page Mode Upper Byte Late Block Write Cycle
tRASP
tRP
V,HRAS (Input) VIL-
V'HCAS (Input) V'L-
V,HAddress (Input) V'L-
-V,HUWE (Input) V'L-
-V,HLWE (Input) V,L-
-V,HDT/OE (Input) V,L-
W8toW15/
V,H108 to 1015 (Input) V,L-
V,HDSF (Input) V,L-
Notes 1. tpc for the J.LPD482444
tHPC for the J.LPD482445
2. tCAS for the J.LPD482444
tHCAS for the J.LPD482445
Remarks 1. WO to W7/IOO to 107: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected, input the column selection data to DATA IN.
5. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
64
NEe
yPD482444,482445
Fast Page. Hyper Page Mode Lower Byte Late Write Cyclel
Fast Page. Hyper Page Mode Lower Byte Late Block Write Cycle
tRASP
tAP
V'HRAS (Input) VIL-
V'HCAS (Input) VIL-
V'HAddress (Input) VIL-
-V'HUWE (Input) V'L-
-V'HlWE (Input) V'L-
-V'HDT/OE (Input) V'L-
wo to W7!
V'H100 to 107 (Input) V'L-
V'HDSF (Input) V'L-
Notes 1. tpc for the ~D482444
tHPC for the ~D482445
2. tCAS for the ~D482444
tHCAS for the ,uPD482445
Remarks 1. W8 to W15/108 to 1015: Don't care
2. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
3. WPB: Write-per-bit
4. When block write cycle is selected. input the column selection data to DATA IN.
5. Because the serial access port operates independently of the random access port. there is no
need to control the SC. SE. 510 pins in this cycle.
65
NEe
pPD482444,482445
Fast Page Mode Read Modify Write Cycle IjlPD482444)/
Fast Page Mode Read Modify Block Write Cycle (jlPD482444)
--
RAS (Input)
tRP
tRASP
r~
·IL
tpRWC
tPRWC
tRCD
CAS (Input)
V,HV'L-
tCSH
tASR
Address (Input)
V,HV,L-
UWE (Input)
LWE (Input)
tASC
5>
ROW
V,HV,L-
COL.'1'
I
WPB
Select
-a&
V,HV,L-
XXXX)( ~
tAwe
~
tRWO
'-
tAwo
t~
tcwo
JYf!.
WPB
Select
'--
tRWO
DT/OE (Input)
VIHV,L-
\\(
IJ
~r~J
VOHVOL-
,
----tws
(Input)
V,HV,L-
DSF (Input)
VIHV,L-
--
I
tCA
f-- I tOHS tOHH
to
W15/
100
to
1015
p22
__lii~~-~_
tOEe
~
~
~
tcwe
~
t!~b-'?
tRCS
~
tcwo
0
lAcp
~
~
I
~
_!:f~g~:Z_
-~9
l:...II
-
tcwo
t:;:'
___ ,:!i9~-~ __
--
Hja't~
tCWL
~
c}'~
tOE~
~l
-~ 'N'
-
--I-!!(!~~--~
~
--tos
I-II--tos
tRWL
~
""~ ~ I
tOEe
~
~y
itAcP
1M
tOEZ
E
-
tcwo
tAwo
I-H-
-~?. L..J.
:xx XXXXX
tAwo
~
tAwe
~
_.. --
twP
M
COL.'N'
~
~
-~~
twH
Mask
data
J(XXX
tAwo
tRAC
1M
~
COL.'2'
~
tcwo
tr;;
-H
tCPN
tRAL
lAsc
tCAH
I- ~
t
tCAS
I-h
twas twSH
t---\
tCAS
~
tRSH
~
~
r--
H:--tes
~~---
-I:!i!lt).-~~E/@
xr 11wri!~~~ect :xxxxx wri~~~~~ect :xxxxx: wri~~~~ectXXXXXXXXX
tFRStFRH
~~
~~
F4
Remarks 1, When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN_
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle_
66
NEe
yPD482444, 482445
Fast Page Mode Read Modify Upper Byte Write Cycle (IJPD48244411
Fast Page Mode Read Modify Upper Byte Block Write Cycle (IJPD482444)
tAP
tRASP
RAS (Input)
V,HV,L-
~
h I--
-----,
tpAWC
tACO
CAS (Input)
tCAS
~
Address (Input)
ROW
t~
LWE (Input)
V,HV,L-
V,HV,L-
tAl!
J
WPB
select
r:
tcwo
~
~
tAWO
~
~r-;
(Input)
V,HV,L-
to
W7/
)00
to
107
.
lji.9~-~
--
~
tAA
~~g~:Z__
-
__
II
-~
~r~"'
(Input)
tws
V,HV,L-
--
V,HV,L-
I- tMCH
~~.
"1"
"-
~MAH
--
- --
tFAH
~
+OO
!il9_h: Z
69
NEe
#D482444, 482445
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected. input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port. there is no
need to control the SC. SE. SIO pins in this cycle.
70
NEe
gPD482444,482445
Hyper Page Mode Read Modify Write Cycle (Extended data output: PPD482445)
Hyper Page Mode Read Modify Block Write Cycle (Extended data output: PPD482445)
tRP
-
V'H-
_
V,H-
RAS (Input) VIL-
CAS (Input) VIL-
V'H-
Address (Input) V'L-
--
V'H-
--
V'H-
--
V'H-
UWE (Input) VIL-
LWE (Input) V'L-
DT/OE (Input) V'L-
WO{ (Output)
to
~~~=
W15/
100
to
1015
V'H-
(Input) V'L-
V'H-
DSF (Input) V'L-
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SID pins in this cycle.
71
NEe
[MEMO]
72
gPD482444,482445
NEe
yPD482444,482445
Hyper Page Mode Read Modify Upper Byte Write Cycle (Extended data output: JLPD4824451
Hyper Page Mode Read Modify Upper Byte Block Write Cycle (Extended data output: JLPD482445I
tRP
tRASP
RAS (Input)
~I~=
~
-
Jr--,
IL
tRSH
'-5;""- !;
tRAD
We
V,HAddress (Input) V'L-
ROW
VIHUWE (Input) V,L-
WPB
select
~
LI
tCWD
tAr-
J
~
'--
lAsc
teAH
t--
l:::1
COL.'2"
lAWD
WO{(output)
to
W7/
- ----
~~:= - ----
108
tws
\f-
V,H(Input) V,L-
--
l:!i9~-?
V,HDSF (Input) V'L-
~
~ I~-
W
I-
~~
--
-
!:l~g~:.Z____
~i~~-~ ____
tFRH
.-- --
Ii-
tOEH
r\
'1'
"-
~
~I
-- -
-
tOEZ
- -- --- -
--1 "2'
''-
tRAC
lAcp
tAA
tAA
I-
L
~)
i2
OEZ
Ir-
__ l:!i9~-? _____
'N'
-,"
tACP
tAA
f-
~
i-
~
=
-fA :XX --- -- -l-f--
~
-j-_ tos
tAA
~
-- -
e
.~
X
'2"
~
~
tAA
~
-- -
ItCAC
r-
~
-.~
E
'N'
@
eEZ
-~~-~~~~---- -~~--~~~~----
W15/
lOB
to
1015
(Input) V,H- • ____ _
VIL-
-----«fXt;--- ~i~~-~ -«IXIJ---
75
NEe
yPD482444,482445
Remarks 1. WhenDSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SID pins in this cycle.
76
NEe
yPD482444,482445
Flash Write Cycle
tRC
tRAS
V'H-
RAS (Input) V'L-
tCRP
CAS (Input)
V'HV'L-
Address (Input)
V'HV'L-
UWE (Input)
V'HV'L-
LWE (Input)
V'HV'L-
tCHR
V'H-
DT/OE (Input) V'L-
woto W151
V'H100 to 1015 (Input) V'L- ~~yll:.::r;::.::::.r,CJJ.~~.o.~)l.:~OJ.~~CJJ.~~CJJ.~~iOI~)l.:~CJJ.~~a.
V'H-
DSF (Input) V'LRemark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, 510 pins in this cycle.
77
NEe
,uPD482444, 482445
Flash Write Cycle (Upper Byte Flash Write)
tRC
tRAS
-
VIH-
RAS (Input) VILtCRP
-
tCHR
VIH-
CAS (Input) VIL-
VIH- ""rn'7\,r.u...-i-I~'jI\rulOlt7tfuro~Aru'Ol:AfurornAru'Ol:Aru~rn""7cr
Address (Input) VIL _ ~Qt:yll:....:;:;';:':"'J-'QJ.:.lL~£lj'-l£lI.:.l£lQJ.:.lLliQ£lj:.lLlI.:.l£l'-l£:lI.:.liQ£lj:.lLlI.:.l£lQt::lI.:.~
--
VIH-
UWE (Input) VIL-
--
VIH-
--
VIH-
-l--l..+_++--'l-"'-'-I.:...l.J-L-""-",-'-"'-'-'-'-~L-":...l.-'-"'-'-'-'-~'-I."-",-'-"'-'-'-'-~
LWE (Input) VIL-
DT/OE (Input) VIL-
W8toW15f
VIH108 to 1015 (Input) VIL-
VIH-
DSF (Input) VIL-
Caution After the falling edge of RAS, the operations performed for the upper byte will be the same as the
RAS only refresh cycle.
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, 510 pins in this cycle.
78
NEe
yPD482444,482445
Flash Write Cycle (Lower Byte Flash Write)
tRC
tRAS
-
VIH-
RAS (Input) VIl-
tCRP
-
tCHR
VIH-
CAS (Input) VIL-
VIH-
Address (Input) VIL-
--
VIH-
--
VIH-
UWE (Input) VIL-
DT/OE (Input) VIL-
wo to W7
VIH100 to 107 (Input) VIL -
~~7\~~~:-\-~:7\.70rn~""~~~~70'OI~70rn~""rn:m~~70'OI'"
DA~y~c....;':""':=:I-'V.:ll.:~f.Y..l£.:\£lj~~\£lj~~i£l/~~f.Y.'y':'\£ljf.Y.~\£lj~~i£l/~
VIH-
DSF (Input) VIL-
Caution After the falling edge of RAS, the operations performed for the upper byte will be the same as the
RAS only refresh cycle.
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, 510 pins in this cycle.
79
NEe
tLPD482444,482445
RAS Only Refresh Cycle
tRC
tRAS
Ms (Input)
VV'H -
IL-
tCRP
tRPC
CAS (Input) V,HV'L- _ _ _J
Address (Input) V,HV,L-
DT/OE (Input) VV'H -
IL-
WO to W15/ (Output) VOH - _ _ _ _ _ _ _ _ _ _ _
100 to 1015
VOL-
_ ______________f!i\!h.:~ __________________________________ _
tFRS
tFRH
DSF (Input) V,HV,LRemarks 1. UWE, LWE: Don't care
2. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
80
NEe
yPD482444,482445
CAS Before RAS Refresh Cycle (Optional Reset)
tRC
tRAS
tRP
RAS (Input) VIHVILtRPC
tCHR
CAS (Input) VIHVIL-
High·Z
WO 10 W15t (OUlput) VOH - ___________________ _
100101015
VOLtFRS
IFRH
---JR
tSRS
SC
(Input) VVIH IL-
--.---'lr--L
_ _ _
Remarks ,. AD to A8, UWE, LWE, DT/OE: Don't care
2. Because the serial access port operates independently of the random access port, there is rio
need to control the SE. 510 pins in this cycle.
81
NEe
.uPD482444,482445
CAS Before RAS Refresh Cycle (STOP Register Set)
tRC
tRAS
RAS
(Input)
tRP
V,H-
VIL-
tRPC
tesR
CAS
(Input)
V'HV,L-
tASR
Address
UWE
LWE
(Input)
(Input)
tCHR
V,HV,L-
tRAH
BOUNDARY CODE
twBS
twBH
twos
twSH
V,HV'l-
(Input) V,HV'L-
WOto W15/ (Output) VOH- ___________________ _
100tol015
VOLtFRS
DSF
V,H(Input) V'L-
tSRS
SC
tFRH
tSRH
(Input) VV'H -
IL- _ _ _ _ _. J
Remarks 1. DT/OE: Don't care
2. Because the serial access port operates independently of the random access port, there is np
need to control the SE, SIO pins in this cycle.
82
NEe
#PD482444,482445
CAS Before RAS Refresh Cycle (No Reset)
tRe
tRP
tRAS
.
RAS (Input)
V,HVILtRPC
tCSR
CAS (Input)
UWE (Input)
LWE (Input)
WOte Wl5/
tCHR
VIHVIL-
VIHVIL-
VIHVIL-
twas
twaH
twas
twu ..
£...I...J...J....I...J....z....I
1....£-<-......-<-.1....1
VeH- __________________ _
_____
Hlg_h:~
____________________________ '________ .
JOOte J015 (Output) VOLtFRS
DSF (input)
VIHVIL-
tFRH
1....£..J...J....I...J....z....I
Remarks 1. AO to AS, DT/OE: Don't care
2. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
83
NEe
yPD482444,482445
Hidden Refresh Cycle (PPD482444)
tRC
tRC
tRAS
tRAS
"RAS (Input) VIHVIL-
-
VIH-
CAS (Input) VIL-
VIH-
Address (Input) VIL-
UWE (Input)
~I~ =
-VIt.LWE (Input) VIL-
--
VIH-
DT/OE (Input) VILtRAC
tOFF
tAA
tOEZ
tCAC
tOEA
WO toW15/
VOH100 to 1015 (Output) VOL-
___ ~i~~-~ ____________ _
DATA OUT
High-Z
----------
VIH-
DSF (Input) VIL-
VIH-
SC (Input) VIL-
Remarks 1. When DSF is high level: Reset select
=No Reset
When DSF is low level : Reset select = Optional Reset
2. Because the serial access port operates independently of the random access port, there is no
need to control the SE, 510 pins in this cycle.
84
NEe
yPD482444,482445
Hidden Refresh Cycle (Extended data output: jLPD482445)
tRC
tRC
tRAS
tRAS
RAS (Input)
V,HV'L-
tCRP
tRCO
tRSH
tCHR
tCPN
tHCAS
tRAO
Address (Input)
UWE (Input)
LWE (Input)
tRAL
V,HV,L-
V,HV,L-
V,HV,L-
V,H-
DT/OE (Input) V,L-
tRAC
tAA
VOH-
WOtoW151
___
tCAC
tOEA
"2i~~-~
____________ _
100 to 1015 (Outputl VOL-
DSF (Input)
SC (Input)
V,HV'L-
tOEZ
DATA OUT
High-Z
----------
~~------~~~~~~
V,HV'L-
Remarks 1. When DSF is high level: Reset select
=No Reset
When DSF is low level : Reset select = Optional Reset
2. Because the serial access port operates independently of the random access port, there is no
need to control the SE, SIO pins in this cycle.
85
NEe
yPD482444, 482445
Register Set Cycle (Early Write)
tRC
tRAS
RAS (Input)
V,HV,LtCSH
tCRP
tRCO
tRSH
tCPN
tCAS tHCASNote '
V,HCAS (Input) V,L-
Address (Input)
V,HV,L-
UWE (Input)
V,HV,L-
LWE (Input)
V,HV,L-
V,H-
DT/OE (Input) V,LtOH
woto W15/
V,H100 to 1015 (Input) V,LtFCH
DSF (Input)
V,HV,L _
Register select
Notes 1. tCAS for the ,uPD482444
tHCAS for the PPD482445
2. Refresh address (RAS only refresh)
Remarks 1. When DSF is high level: Register select = Color Register Select
When DSF is low level : Register select =Write Mask Register Select
2. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
86
NEe
yPD482444,482445
Register Set Cycle (Upper Byte Early Write)
tRe
tRAS
-
tRP
V,H-
RAS (Input) V'LtCSH
tReD
-
tRSH
teRP
tePN
V,H-
CAS (Input) V,L-
V,H-
Address (Input) V'L-
-V,H _ -'-r-v--++-+~
UWE (Input) V'L-
___
V'H- -'-r~---H---+--~~--++----------------------~------~~~~
LWE (Input) V,L-
W8toW15/
V,H108 to 1015 (Input! V,L-
____
..............,"-><......,..f->L..K...lC-lL..~
V,H - -,-r-V----V--ril. 11'"------\1 1\1\7\7\j~~7\]~7\.7\]\7\7\j1\jl\7\7\j'\7'i-:7\l
DSF (Input) V,L-
Notes 1. tCAS for the }lPD482444
tHCAS for the JlPD482445
2. Refresh address (RAS only refresh)
Remarks 1. WO to W7/IOO to 107: Don't care
2. When DSF is high level: Register select .. Color Register Select
When DSF is low level : Register select .. Write Mask Register Select
3. Because the serial access port operates independently of the random access port, there is no
need to control the SC. SE. SIO pins in this cycle.
87
NEe
,uPD482444,482445
Register Set Cycle (Lower Byte Early Write)
tRC
tRAS
tRP
VIHRAS (Input) VILtCSH
tRCO
tRSH
tCAS tHCAS"ot. 1
tCAP
tCPN
VIH-
CAS (Input) VIL-
VIHAddress (Input) VIL-
VIHUWE (Input) VIL-
LWE (Input) VIHVIL-
DT/OE (Input)
WOtoW7/
~I~ =
VIH-
100 to 107 (Input) VIL -
DJ!.l£ll.J~W-ll.JlJJ.~~ I\.._T'T""--..II ,,...¥-.It..J''-¥...¥-.K..l''-¥...¥-.K..l''-¥...¥-.K..lLll:...x...K..lLll~
VIH-
DSF (Input) VIL-
Notes 1. tCAS for the IlPD482444
tHCAS for the IJPD482445
2. Refresh address (RAS only refresh)
Remarks 1. W8 to W15/108 to 1015: Don't care
2. When DSF is high level: Register select = Color Register Select
When DSF is low level : Register select = Write Mask Register Select
3. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
88
NEe
gPD482444,482445
Register Set Cycle (Late Write)
tRe
tRP
tRAS
RAS (input)
V,H V,LteRP
tesH
tRSH
tRCO
tCAS tHCASNote 1
CAS (Input)
Address (Input)
V,HV'L-
V,HV,L-
!wi>
UWE (Input)
V,HV,L-
LWE (Input)
V'HV'L-
twp
tOEH
DT/OE (Input)
V'HV'Ltos
woto W15/
10010 1015 (Input)
V'HV,L-
DSF (Input)
V'HV,L-
tOH
DATA IN
Notes 1. tCAS for the tLPD482444
tHCAS for the tLPD482445
2. Refresh address (RAS only refresh)
Remarks 1. When DSF is high level: Register select = Color Register Select
When DSF is low level : Register select
=Write Mask Register Select
2. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SID pins in this cycle.
89
NEe
gPD482444,482445
Register Set Cycle (Upper Byte Late Write)
tRC
tRAS
tRP
V,H RAS (Input) VILtCSH
tRCO
tCRP
tCPN
tRSH
VIH-
CAS (Input) VIL-
VIH-
Address (Input) V,L-
VIH-
UWE (Input) VIL-
VIH-
LWE (Input) VIL-
DT/OE
(Input)
VIHVIL-
tos
wsto W15/
VIHlOB to 1015 (Input) VIL _
tOH
DATA IN
VIH-
DSF (Input) VIL-
Notes 1. tCAS for the JlPD482444
tHCAS for the pPD482445
2. Refresh address (RAS only refresh)
Remarks 1. WO to W7/IOO to 107: Don't care
2. When DSF is high level: Register select
When DSF is low level : Register select
=Color Register Select
=Write Mask Register Select
3. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
90
NEe
pPD482444,482445
Register Set Cycle (Lower Byte Late Write)
tRC
tRAS
tRP
~r~ =
RAS (Input)
tCSH
tCRP
tCPN
VIH-
Address (Input)
VIL-
UWE (Input)
VIHVIL-
LWE (Input)
VIHVrL-
VIH(Input)
VIL-
VIHVIL-
WOtoW7/
100 to 107 (Input)
DSF
tCRP
tRSH
tCAS tHCASNoto 1
VrHVrL-
CAS (Input)
DT/OE
tRCO
VIHVIL-
(Input)
Notes 1.
teAs
for the
tHCAS
~PD482444
for the ~D482445.
2. Refresh address (RAS only refresh)
Remarks 1. W8 to W15/108 to 1015: Don't care
2. When DSF is high level: Register select
When DSF is low level : Register select
= Color Register Select
= Write Mask Register Select
3. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
91
NEe
#0482444, 482445
Mask Register Set Cycle (New Mask Selection)
tRC
tRAS
tRP
V,HRAS (Input)
V'LtCSH
. tRCD
tRSH
tCAS tHCAS
0<0
V,H-
CAS (Input) V,L-
tCPN
V,HAddress (Input) V,L-
V'H-
UWE (Input) V,L-
V,H-
LWE (Input) V,L-
V,H-
DT/OE (Input) V,L-
wo to WI 51
100tol015
(Output) VVOH -
_______ _
_____
~J~~~
__________________________ _
OL-
V,H-
DSF (Input) V,L-
Notes 1. tCAS for the IlPD482444
tHCAS for the JlPD482445
2. Refresh address (RAS only refresh)
3. Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, 510 pins in this cycle.
92
NEe
yPD482444,482445
Read Data Transfer Cycle (SC Active)
tRC
tRAS
RAS (Input)
VIHVIL-
CAS (Input)
VIHVIL-
Address (Input)
VIH-
UWE(lnput)
VIHVIL-
LWE (Input)
VIHVIL-
DT/OE (Input)
VIHVIL-
to W15t
100 to 1015 (Outputl
VOHVOL-
WO
VIL-
----------~~~:~----------tFRS
DSF (Input)
SE (Input)
tFRH
VIHVIL-
VIHVIL- _ _
L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
t+-______________
tscc
SC (Input)
VIHVIL-
SIOO to SI015 (Outputl
VVOH OL-
aSF (Output)
VOHVOL-
Note
tCAS
!soo
tsOH
for the JlPD482444
tHCAS
for the JlPD482445
93
NEe
gPD482444,482445
Read Data Transfer Cycle (SC Inactive)
tRC
tRAS
--
RAS (Input)
V'HV'L-
CAS (Input) V'H-
V'L-
Address (Input) V'H-
V'L-
UWE (Input) V'H-
V'L-
LWE (Input) V'H-
VIL-
DT/OE (Input) V".VIL-
VOltwoto W15/
100 to 1015 10utput) VOL-
-------tFRS
_________~i~~~
tFRH
DSF (Input) V'H-
V'L-
SE (Input) V'H-
V'L-
L
tsOHR
tROD
tcoo
tooo
SC (Input)
V'HV'L-
VOH-
SIOO to SI01510utputi VOL-
n-1
n
tpo
'QSF (Output) VVOH -
OL-
Note tCAS for the JlPD482444
94
tHCAS for the JlPD482445
New data output start
NEe
yPD482444,482445
Read Data Transfer Cycle (Serial Write
~
Serial Read Switching)
tRC
tRAS
RAS '(Input) V,HVIL-
CAS (Input) V,H VIL-
Address (Input) V,H-
V,L-
UWE (Input) V,HV'L-
LWE (Input) V,HV,L-
DT/OE (Input) V,HV'L-
WOtoW15'
VOH100 to 1015 (Outputl VOL-
DSF (Input) V,H V'L-
SE (Input) V,HV,L- __L______
~--------_+------~H-----------------~-------------------tSOHR
tROD
tssc
tcoo
toaD
tSCH
SC (Input) V,H -
V,L-
tSIZ
SIOO {
(Input)
~,~ =
to
51015
(Output) VOH -
_ __________________________ ,:!i9':!-~ _____________ _
VOL-
!PO
tOOR
QSF (Output) VOHVOL- ____________________
~~
____________________________
New data output start
_L~
____________
Note tCAS for the ¢>D482444
tHCAS for the ¢>D482445
95
NEe
[MEMO]
96
gPD482444, 482445
NEe
yPD482444,482445
Split Read Data Transfer Cycle
tRe
tRP
tRAS
RAS (Input) V,HV,L-
CAS (Input)
V,HV'L-
Address (Input)
V,HV,L-
UWE (Input)
V,HV,L-
LWE (Input) V,HV'L-
woto W15/
VOH100 to 1015 (Output) VOL-
V,HDSF (Input) V,L _
SE (Input)
+ _________-t-__________
V,HV,L- --=L:..-_ _ _ _ _ _ _ _ _ _
tSOHR
tsse
tsee
Note 2
V,HSC (Input) V,L _
(Input) VV'H -
IL-
OSF (Output) VVOH OL-
97
NEe
uPD482444,482445
Notes 1. tCAS for the JlPD482444
tHCAS for the JlPD482445
2. Do not perform the following two serial read/write during this period .
• Serial read/write of jump source address set to the STOP register of the data register which does
not perform the data transfer cycle .
• Serial read/write of last address of data register (Address 255 or 511)
98
NEe
yPD482444,482445
Write Data Transfer Cycle
tRC
tRP
tRAS
V,HRAS" (Input)
V,L-
CAS (Input)
V,HV'L-
Address (Input)
V,HV'L-
UWE (Input) V,HV,L-
LWE (Input)
V,HV,L-
DT/OE (Input)
V,HV'L-
WO to W15/ (Input) V,H100 to 1015
V,L-
DSF (Input)
V,HV'L-
SE (Input)
V,HV,L-
L
tSOHR
tcao
5C (Input)
SIOO
to
51015
V,HV,L _
(Input) V,HV,L-
a5F (Output) VVOH -
OL- ________________~------------------------------------~----------
Note
tCAS
for the JIPD482444
tHCAS
for the IlPD482445
99
NEe
gPD482444,482445
Write Data Transfer Cycle (Serial Read
~
Serial Write Switching)
tRC
tRAS
tRP
RAS (Input) V,H-
VILtCSH
tRCD
CAS (Input) V,HV,L-
Address (Input)
V,HV'L-
LWE (Input)
V,HV,L-
WOtoW15/ (Input)
IDa to 1015
SE
(Input)
tRSH
tCAS tHCASNoto
tCPN
_ _--'
V,HV,L - ..L..~"-Jj~ " - n - - - " '\j:...l£..lL.~~YI:...l£..lL..lC...lC..'IL..l'-ll~...x..lf-'Lli~...x..~L.l'-ll~"""~""-'L.
V,HV,L-
-=L----++---------t--------~r_---------"
tSDHR
tCOD
tROD
SC (Input) VIH-
V,L-
;~105{
(Input)
V,H -
• ________________Hlg_h:~ _____________
VIL-
tsCA
(Output) VOHVOL -
-----r--.Ii
aSF (Output) VVOH -
OL-
Note teAs for the J.lPD482444
tHCAS for the JtPD482445,
100
_
. tSRZ
DATA OUT
__________ ~i9~-~ _________ _
NEe
gPD482444,482445
Split Write Data Transfer Cycle
tRC
tRAS
RAS (Input)
V'HV,e-
CAS (Input)
V'HV,e-
Address (I nput)
V'HV,e-
UWE (Input)
V'HV'L-
LWE (Input)
V'HV,e-
tRP
DT/OE (Input) V'H-
V,e-
WO to Wl 51 (Input)
100 to 1015
V'HV'L-
DSF (Input)
V,HV,L-
SE (Input)
V,HV,e-
SC (Input)
SIOO{
(Input)
L
V,HV'L-
~,~=
to
SI015
(Output) VOHVOL-
aSF (Output) VOHVoe-
101
NEe
,uPD482444,482445
Notes 1. tCAS for the tLPD482444
tHCAS for the tLPD482445
2. Do not perform the following two serial read/write during this period.
Serial read/write of jump source address set to the STOP register of the data register which does
not perform the data transfer cycle.
Serial read/write of last address of data register (Address 255 or 511)
102
NEe
yPD482444,482445
Serial Read Cycle
tsEE
SE (Input)
V,HV'L-
tSEZ
tscc
SC (Input)
tsccNoteZ
tsccNote1
V,HV,L-
tSOH
SIOO
to
SI015
(Output) VOH- ___
VOL-
!i19_h:2.. -- --
DATA OUT
VOH- ________________________- J
QSF (Output) VOL-
Notes 1. Last address of data register (Address 255 or 511)
2. Starting address of data register newly read (address is specified in the data transfer cycle).
Remark Because the random access port operates independently of the serial access port, there is no need
to control the RAS, CAS, Address, UWE, LWE, DT/DE, WI/D, DSF pins in this cycle.
Serial Write Cycle
tsccNote 1
tscc
tSCH
SC (Input)
tSCH
tSCL
tsccNoteZ
tsCL
tsCL
V,HV,L _
tSES
tSEH
tsES
tSEH
tsES
tSEH
tsES
tSEH
SE (Input) V,H-
V,L-
5100
to
SI015
(Input) VvOH OL-
QSF (Output) VVOH -
OL-
Notes 1. Last address of data register (Address 255 or 511)
2. Starting address of data register newly read (address is specified in the data transfer cycle).
Remark Because the random access port operates independently of the serial access port, there is no need
to control the RAS, CAS, Address, UWE, LWE, DT/DE, WI/D, DSF pins in this cycle.
103
NEe
gPD482444,482445
5. Package Drawings
64 PIN PLASTIC SHRINK SOP (525 mil)
64
33
detail of lead end
o
It)
tI
o
It)
H
I
~----~-----++-J
--- - ,- - - ----~
I
~+=..t
L
P64GW-B0-525A-l
NOTE
Each lead centerline is located within 0.10
mm {O.004 inch} of its true position {T.P.} at
maximum material condition.
\
104
ITEM
MILLIMETERS
INCHES
A
26.30 MAX.
1.036 MAX.
B
0.75 MAX.
0.030 MAX.
C
O.B {T.P.}
0.031 {T.P.}
0
0.35±0.05
0.014~g:gg~
E
0.15±0.05
0;006±0.002
F
2.3 MAX.
0.091 MAX.
G
2.0
0.079
H
13.B±0.3
0.543~:m
I
11.B±0.1
0.465~g:gg~
J
1.0±0.2
O. 039~g:gg~
K
0.20~g:6~
O.OOB~g:gg~
L
0.5±0.2
0.020~g:gg~
M
0.10
0.004
N
0.10
0.004
NEe
.uPD482444,482445
6. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the ttPD482444 and 482445.
Types of Surface Mount Device
,uPD482444GW
: 64-Pin Plastic Shrink SOP (525 mil)
,uPD482445GW
: 64-Pin Plastic Shrink SOP (525 mil)
105
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[MEMO]
106
,uPD482444,482445
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
~PD482234,482235
2M-Bit Dual Port Graphics Buffer
256K-WORD BY 8-BIT
Description
The JLPD482234 and JLPD482235 have a random access port and a serial access port. The random access
port has a 2M-bit (262, 144 words x 8 bits) memory cell array structure. The serial access port can perform
clock operations of up to 55 MHz from the 4K-bit data register (512 words x 8 bits).
To simplify the graphics system design, the split data transfer function and binary boundary jump function
have been adopted so that the number of split data registers can be programmed with the software during
serial read/write operations.
The JLPD482235 is provided with the hyper page mode, an improved version of the fast page mode of the
JLPD482234. The random access port can input and output data by CAS clock operations of up to 33 MHz.
Features
Dual port structure (Random access port, Serial access port)
• Random access port (262, 144-word x 8-bit structure)
-------
JLPD482234
JlPD482234-60
JLPD482234-70
JlPD482234-80
RAS access time
60 ns(MAX.)
70 ns(MAX.)
80 ns(MAX.)
Fast page mode cycle time
40 ns(MIN.)
45 ns(MIN.)
50 ns(MIN.)
JlPD482235
JLPD482235-60
JLPD482235-70
JLPD482235-80
RAS access time
60 ns(MAX.)
70 ns(MAX.)
80 ns(MAX.)
Hyper page mode cycle time
30 ns(MIN.)
35 ns(MIN.)
40 ns(MIN.)
• Flash write function Note
• Block write function (4 columns)Note
• Mask write (Write-per-bit function)
• 512 refresh cycles /8 ms
• CAS before RAS refresh, RAS only refresh, Hidden refresh
Note Write-per-bit can be specified.
The information in this document is subject to change without notice.
IC·3645 (Japan)
107
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pPD482234,482235
• Serial access port (512 words x 8 bits organization)
•. Serial read/write cycle time
.llPD482234-60, 482235-60
llPD482234-70, 482235-70
llPD482234-80, 482235-80
18 ns (MIN.)
22 ns (MIN.)
25 ns (MIN.)
• Serial data read/write
• Split buffer data transfer
• Binary boundary jump function
Version A. F. and E
There are three versions, A, F, and E, to both the JlPD482234 and llPD482235. These versions operate with
different specifications.
• Overview of each version
JlPD482234
The table below summarizes the operation of each version of the IlPD482234.
Item
Reference
Version A
Versions F and E
Specifying a column for data transfer
during split data transfer cycle
3.2 Split Data
Transfer Method
"MSB Don't Care" only
Version F: MSB Don't Care
Version E: MSB Care
Selecting a new mask data method
during mask write cycle
2.8.2 Selecting
Mask Data
Option reset cycle only
Both option reset cycle and
new mask selection can be
used.
1LPD482235
The table below summarizes the operation of each version of the IlPD482235.
Item
Reforonco
Version A
Versions F and E
Specifying a column for data transfor
during split data transfer cyclo
3.2 Split Data
Transfar Method
"MSB Don't Care" only
Version F: MS~ Don't Care
Version E: MSB Care
Selecting a new mask data system
during mask write cycle
2.8.2 Selecting
Mask Data
Option reset cycle only
Both option reset cycle and
new mask selection can be
used.
Latched control
(conforming to JEDEC)
Non-latched control
OE control system during hyper page 2.4.1 Setting the
Output to the
mode cycle
High Impedance
State
" How to identify each version
Each version is identified with its lot number (Refer to 7. Example of Stamping).
108
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Ordering Information
Part Number
RAS Access Time
Package
ns (MAX.)
IlPD482234LE-60
60
IlPD482234LE-70
70
IlPD482234LE-80
80
IlPD482234G5-60
60
IlPD482234G5-70
70
IlPD482234G 5-80·
80
IlPD482235LE-60
60
IlPD482235LE-70
70
IlPD482235LE-80
80
IlPD482235G5-60
60
IlPD482235G5-70
70
IlPD482235G5-80
80
40-pin plastic SOJ (400mil)
Page Mode
Fast page mode
44-pin plastic TSOP (II)
(400mil)
40-pin plastic SOJ (400mil)
Hyper page mode
44-pin plastic TSOP (II)
(400mil)
109
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yPD482234,482235
Pin Configurations (Marking Side)
40-pin plastic SOJ (400 mill
Vee
40
GND
39
SI07
SIOO
38
SI06
Sial
37
SI05
36
SI04
SC
SI02
2
5
SI03
35
SE
DT/OE
34
W7/107
33
W6/106
32
W5/105
31
W4/104
NN
30
GND
Ul""
In In
29
DSF
WO/IOO
1::1::
Wl/IOl
."."
W2I102
10
W3/103
11
ee
titi
NN
ww
GND
12
WBM/E
13
28
NC
RAS
14
27
CAS
A8
15
26
QSF
A7
16
25
AO
A6
17
24
Al
A5
18
23
A2
A4
19
22
A3
Vee
20
21
GND
AO to AS
Address inputs
WO to W7/100 to 107
Mask data selects/Data inputs and outputs
SIOO to SI07
Serial data inputs and outputs
RAS
Row address strobe
Column address strobe
CAS
DT/OE
Data transfer/Output enable
WB/WE
Write-per-bit/Write enable
SE
Serial data input/Output enable
Serial clock
SC
QSF
Special function output
DSF
Special function enable
Vee
Power supply voltage
GND
Ground
No connection
NcNote
Note Some signals can be applied because this pin is not connected to the inside of the chip.
110
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gPD482234,482235
44-pin plastic TSOP (II) (400 mill
Vcc
1
2
0
44
GND
SI07
SIOO
3
SI06
SI01
4
SI05
SI02
5
SI04
SI03
6
SE
DT/OE
7
W7/107
8
9
W2/102
10
W6!106
"):::"):::
-u-u
W5/105
&&
NN
W4!104
CC
NN
ww
en ....
enC1l
!i)!i)
W3!103
13
GND
GND
14
DSF
WBNVE
15
NC
RAS
16
CAS
A8
17
QSF
A7
18
AO
A6
19
A1
A5
20
A4
21
Vcco-- 22
A2
0
24
A3
23 --oGND
AO to AS
Address inputs
WO to W7/IOO to 107
SIOO to SI07
RAS
CAS
DT/OE
WB,WE
Mask data selects/Data inputs and outputs
Serial data inputs and outputs
Row address strobe
Column address strobe
Data transfer/Output enable
Write-per-bit/Write enable
Serial data input/Output enable
Serial clock
SE
SC
QSF
DSF
Vee
GND
NcNote
Special function output
Special function enable
Power supply voltage
Ground
No connection
Note Some signals can be applied because this pin is not connected to the inside of the chip.
111
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,uPD482234,482235
Block Diagram
RAS
CAS
DT/OE
DSF--pt_--,
Vcc--
GND--
Refresh
Counter
511
Column Decoder
~-------
512columnsx8 -------t---t
Memory Cell Array
(512 x 512 x 8)
SE-----+---------,
112
QSF
SIOO
SI07
,uPD482234,482235
NEe.
1. Pin Functions
This product is equipped with the RAS, CAS, WB/WE, DT/OE, AO to AS, DSF, SC, SE inputs, QSF output, and
WO to W7/100 to 107, SIOO to SI07 input/output pins.
(1/3)
Pin Name
RAS
(Row address strobe)
Input/
Function
Output
Input
This signal latches the row addresses (AO to AS), selects the corresponding
word line, and activates the sense amplifier. It also refreshes the memory
cell array of the one line (4,096 bits) selected from the row addresses (AO
to AS).
It also serves as the signal which selects the following operations.
• Write-per-bit
• Flash write
• CAS before RAS refresh
• Split data transfer
CAS
This signal latches the column addresses (AO to AS), selects the digit line
(Column address
connecting the sense amplifier, and activates the output circuit which
strobe)
outputs data to the random access port.
It also serves as the signal which selects the following operations.
• Read/write
• Block write
• Color register set
• Mask register set
AO to AS
These are the address input pins, TAP register input pins, and STOP
(Address inputs)
register input pins .
.A.~~~.ess 1~P.l1t '
This is a 9-bit address bus. It inputs a total of 18 bits of the address signal,
starting from the upper 9 bits (row address) and then followed by the lower
9 bits (column bits) (address multiplex method). Using these, one word
memory cells (S bits) are selected from the 262,144 words x 8 bits memory
cell array.
During use, specify the row address, activate the RAS signal, latch the row
address, switch to the column address, and activate the CAS signal. After
activating the RAS and CAS signals, each address signal is taken into the
device. For this reason, the address input setup time (tASR, tASC) and hold
time (tRAH, tCAH) are specified for activating the RAS and CAS signals.
In the data transfer cycle, this TAP register input pin functions as the
address input pin which selects the memory cell fortransferring (9 bits are
latched at the falling edge of RAS) and the TAP register data input pin
which specifies the start addresses ofthe serial read/write operation after
data transfer (9 bits are latched at the falling edge of the CAS).
This pin functions as the STOP register input pin when the STOP register
is set (STOP register data (9 bits) are latched atthe falling edge of the RAS.)
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yPD482234,482235
(2/3)
Pin Name
Input/
Output
Input
(Data transfer/
output enable)
Function
These are the data transfer control signal and read operation control signal
respectively. They have different functions in the data transfer cycle and
read cycle.
Read operation is performed when this signal, and the RAS and CAS
signals are activated. The input/output pin is high impedance when this
signal is not activated. When the WB/WE signal is activated while the
DT/OE signal is activated, the DT/OE signal is invalid in the memory and
read operations cannot be performed.
These are the write operation control signal and mask write cycle (writeper-bit function) mask data input control signal, respectively.
WB/WE
(Write-per-bit/
Write enable)
When this signal, RAS and CAS signals are activated, write operations or
mask write can be performed. These mode are determined by the level
of WB/WE at the falling edge of RAS.
• High level ....... 8-bit write cycle
• Low level ........ Mask write cycle (Write-per-bit)
This signal controls the selection of functions.
The selection of functions is determined by the level of this signal at the
falling edge of the RAS and CAS. The functions will change as follows
DSF
(Special function
enable)
when this signal is high level.
• The data transfer cycle changes to a split data transfer cycle.
• The read/Write cycle of each RAS clock changes to the flash write cycle.
• The write cycle of each CAS clock changes to the block write cycle.
WO to W7/100 to 107
(Mask data selects/
Data inputs, outputs)
Input/
Output
These are normally 8-bit data bus and are used for inputting and outputting
data. (100 to 107).
Function as the mask data input pins (WO to W7) in the mask write cycle
(write-per-bit function).
Write operations can be performed only for WO to W7 that are input with
a high level at the falling edge of RAS (new mask data).
Functions as the column selection data input pin in the block write cycle.
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yPD482234,482235
(3/3)
Pin Name
sc
Input!
Function
Output
Input
This pin inputs the clock which controls the serial access port operation.
(Serial clock)
:~ifi"f:
The data of the data register which is synchronized with the rising edge
ofthe SC are output from the SIOO to SI07 pins and kept until the next SC
rising edge.
:~~(Write
'
The data from the SIOO to SI07 pins are latched at the rising edge of the
SC and written in the data register.
SE
(Serial data input/
This is a control pin for the serial access port input/output buffer.
Itcontrols data output during serial reading and controls data input during
output enable)
serial writing.
By inputting the serial clock, the serial pointer will operate even if SE has
not been activated (high level input).
SIOO to SI07
Input/
(Serial data inputs/
outputs)
Output
aSF
Output
These are the serial data input and output pins of the serial access port.
(Special function
This is a position discrimination pin of the serial pointer (upper side or
lower side).
output)
Which side is being serial accessed (upper side or lower side) can be
discriminated according to the output of this pin .
• High level ....... Upper side (Addresses 256 to 511)
• Low level ........ Lower side (Addresses 0 to 255)
115
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.uPD482234, 482235
2. Random Access Port Operations
Theoperation mode is determined by the CAS, DT/OE, WB/WE, and DSF level at the falling edge of RAS and
DSF level at the falling edge of CAS.
Table 2-1. Operation Mode
CAS
RAS Falling Edge
CAS DT/OE WB/WE
Falling Edge
DSF
DSF
H
H
x
L
x
H
H
H
L
L
Operation Mode
Read cycle
Write cycle
GI
H
I--H
H
H
L
H
Block write cycle
.
::
Mask write cycle (New mask/Old mask)Note 1
to)
H
L
L
L
H
L
L
H
1----
H
1
GI
;t::
-
Block mask write cycle (New mask/Old mask)Note 1
"C
H
H
H.
H
H
III
Ql
Color register set cycle
II:
f---.
H
- -_ ..
H
H
H
H
H
L
Write mask register set cycle
H
L
H
x
Flash write cycle (New mask/Old mask)Note 1
L
H
L
x
H
L
H
H
x
H
L
L
L
x
H
L
L
H
x
L
x
x
L
x
L
x
H
H
x
~
.;c
~
Single read data transfer cycle
Split read data transfer cycle
Single write data transfer cycle (New mask/Old mask)Note 1
~
Split write data transfer cycle (New mask/Old mask)Note 1
GI
CAS before RAS refresh cycle (Option reset)Note 1.2
>
to)
CAS before RAS refresh cycle (No reset)
U
.l:.
L
x
L
H
x
H
H
x
L
x
Xl
.:::Ql
II:
CAS before RAS refresh cycle (STOP register set)Note 2
RAS only refresh cycle
Notes 1. Observe the following conditions when using the new mask data or old mask data in these cycles.
(1) Old mask data
Can be used after setting the mask data using the write mask register set cycle.
(2) New mask data
Can be used after selecting the new mask register using the write mask register set cycle (new
mask selection) (Unusable in version A) and after the optional reset cycle.
2. The STOP register is set to "FFH (11111111)" by the optional reset cycle.
Remark H: High level, L: Low level, x: High level or low level
116
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yPD482234,482235
2.1 Random Read Cycle
This product has a common 8-bit input/output pin. To output data, specify the address using the RAS and
CAS clocks and then set DT/OE to low level.
The data output will be kept until one of the following conditions is set.
(1) Set RAS and CAS to high level
(2) Set DT/OE to high level
(3) Set WB/WE to low level
The read cycle and data transfer cycle are differentiated according to the level of DT/OE at the falling edge
of the RAS clock. If DT/OE is set to low level at the falling edge of the RAS clock, data transfer cycle operations
will be initiated. Therefore, to set the read cycle, input a high level above tOHH (MIN.) to DT/OE from the falling
edge of the RAS clock, and then input a low level.
Caution Set the DSF to low level at the falling edge of RAS. If set to high level, the memory cell data cannot
be output.
2.1.1 Extended Read Data Output
(~PD482235)
The ~PD482235 adopt the hyper page mode cycle which is a faster read/write cycle than the fast page mode
of the
~PD482234
(Hyper page mode cycle time: 30 ns (MIN.)).
With this cycle, the read data output can be kept until the next CAS cycle, and because the output is extended,
the minimum cycle can easily be used. For example, by fixing DT/OE at low level after dropping RAS and
executing the hyper page read cycle, each time the column address is latched at the falling edge of CAS, the data
output will be updated and kept until the next falling edge of CAS. As a result, the output will be extended only
during CAS precharge time (tep) as compared to the normal fast page mode.
Figure 2-1. Extended Data Output of Hyper Page Mode
RAS (Input)
CAS (Input)
Address (Input)
DT/OE (Input)
W/IO (Output)
Notes 1. Time during which the output"data is kept in the fast page read cycle.
2. Time during which the output data is kept in the hyper page read cycle
output).
(III part:
Extended data
117
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gPD482234,482235
2.2 Random Write Cycle (Early Write, Late Write, Read Modify Write)
There are three types of random write cycles-the early write, late write, and read modify write. To use these
cycles, activate the FlAS and CAS clocks and set WB/WE to low level.
The WB/WE also controls the mask data for the write-per-bit function (mask write cycle). Therefore, when
performing the normal write cycle which does not use the write-per-bit function, set this pin to high level at the
falling edge of the RAS clock.
2.2.1 Early Write Cycle
The early write cycle controls data writing according to the CAS clock.
To execute this cycle, set WB/WE to low level earlier than the CAS clock. The write data is taken into the device
at the falling edge of the CAS clock.
2.2.2 Late Write Cycle
The late write cycle controls data writing according to the WE clock.
To execute this cycle, set WB/WE to low level later than the CAS clock. The write data is taken into the device
at the falling edge of WB/WE. To set the output to high impedance at this time, keep OT/OE at high level until
WB/WE is input.
2.2.3 Read Modify Write Cycle
The read modify write cycle performs data reading and writing in one RAS and CAS cycle.
To execute this cycle, delay WB/WE from the late write cycle by tAWD (MIN.), tCWD (MIN.), and tAWD (MIN.). Follow
the tOEZ and tOED specifications so that the output data and input data do not clash in the data bus. The data after
modification can be input after more than tOED (MIN.) from the rising edge of OT/OE.
118
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opPD482234,482235
2.3 Fast Page Mode Cycle IpPD482234)
The /lPD482234 adopts the fast page mode. This mode accesses memory cells in the same row array in about 1/3
of the time taken by the normal random read/write cycle. This fast page mode cycle is executed by repeating the CAS
clock cycle more than two times while the RAS clock is being activated. In this mode read, write and read modify
write cycles are available for each of the consecutive CAS cycles within the same RAS cycle.
2.4 Hyper Page Mode Cycle I}lPD482235)
The /lPD482235 adopts a hyper page mode cycle which is a faster read/write cycle than the fast page mode of the
/lPD482434 (Hyper page mode cycle time: 30 ns (MIN.)).
In this cycle, because the read data output is kept until the following CAS cycle and as a result, the output
is extended, the minimum cycle can easily be used. The output is extended compared to the normal fast page
mode of .uPD482234. Refer to 2.1.1 Extended Read Data Output.
2.4.1 Setting the Output to the High Impedance State
The hyper page mode can use one of three methods of setting the output pin to the high impedance state
depending on the version; these methods are WE control, OE control (latched control), and OE control (nonlatched control).
Table 2-2 lists the correspondence between the output control types and versions A, F, and E.
Table 2-2. Correspondence between Each Output Control Method and Versions A. F. and E
Version A
Version F
Version E
WE control
usable
usable
usable
OE control (latched control),
usable
unusable
unusable
unusable
usable
usable
Output control
conforming to JEDEC
OE control (non-latched control)
119
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yPD482234,482235
(1) WE control (usable in all versions)
After a high level is input to CAS, when a pulse conforming to the
twEZ
specification is supplied to the
WE pin (WE = enable) during the same CAS cycle, the W/IO pin is held in the high impedance state until
the next CAS cycle.
Figure 2-2. WE Control Output Control
RAS (Input)
\ \ . ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
\1.....-_----1
\1.....-_----1
CAS (Input)
Address (Input)
WErwS (Input)
DT/OE (Input)
WIIO (Output)
------~~~~-------
DATAl
___
~~~:Z
__ _
High-Z
--------
(2) OE control (latched control) (usable in version A)
After a high level is input to CAS, when a high level is supplied to the OE pin (OE
= disable) during the
same CAS cycle, the W/IO pin is held in the high impedance state until the next CAS cycle. This specification
enables efficient use of OE interleaving during parallel connection.
Figure 2-3. OE Control Output Control (Latched Control)
RAS (Input) \ \ . ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CAS (Input)
\'--_----1
\1.....-_----1
Address (Input)
WErwS (Input) ]
::~: ~'-~-:Z--------------{~~~D~A~T~A~l~=D!>!'----<,..-D-A-T-A-2-~
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(3) OE control (non-latched control) (usable in versions F and E)
When a high level is input to the OE pin (OE
= disable) during the same CAS cycle, the W/IO pin enters
the high impedance state. If a low level is inputto the OE pin again before the next CAS cycle (DE = enable),
the. data at the same address is output to the WIlD pin again.
Figure 2-4. DE Control Output Control (Non-Latched Control)
RAS (Input)
\1...________________________
CAS (Input)
Address (Input)
WE/WB (Input)
DT/OE (Input)
High-Z
WIlD (Output) - - - - - - - - - - - - - - -
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.uPD482234, 482235
2.5 Flash Write Cycle
This cycle writes the color register data in a 4,096-bit memory cell in one cycle. The memory cell range for
one flash write cycle is 512 columns on the same row address (512-column x 8· 10 = 4,096 bits).
2.5.1 Execution of Flash Write Cycle
To execute the flash write cycle, set WB/WE to low level at the falling edge of RAS.
By using the write-per-bit function (new mask data/old mask data), only the required W/IO can be selected
and written.
Figure 2-5. Memory Cell Range That Can be Written with Flash Write Cycle
IAlO"" I AI., "Inn
to 107
512
Remark
122
c::::J is the memory cell range that can be written in one flash write cycle.
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gPD482234,482235
2.6 Block Write Cycle
This cycle writes the color register data in 32-bit memory cell in one cycle. The memory cell range in which
data can be written in one block write cycle is four continuous columns on one row address (4-column x 8 . 10
= 32 bits).
Anycolumn ofthefour columns can be selected and writing prohibited. Determine whether to write or prohibit
writing according to the data selected for column.
2.6.1 Free Column Selection
Determine which column to select according to the WIIO pin to which the data selected for the column is to
be input.
The four columns (1st to 4th) correspond to WO to W3/100 to 103 to which the data selected for column will
be input (The following table shows the 1st to 4th columns specified by AO and A 1 and the corresponding
WIIO pins to which the data selected will be input.).
2.6.2 Column Select Data
Input column select data for every four columns at the 32 bits (4-column x 8· 10). The data will be written
if the column select data is "1". Writing will be prohibited if the column select data is "0"
2.6.3 Execution of Block Write Cycle
At the falling edge ofthe slowest signal (CAS, WB/WE), input the" 1" column select data or "0" column select
data to WO to W3/100 to 103 corresponding to columns 1st to 4th.
By using the write-per-bit (new mask datalold mask data) function, only the required WIlD can be selected
and written.
Table 2-3. 1/0 Pins Input with Column Select Data Corresponding to Columns 1st to 4th
Selected 4 Columns
1st column
2nd column
3rd column
4th column
Column Address and Corresponding
WIIO Pin
A1
AO
10
0
0
100
0
1
1
1
0
1
101
102
103
Column Select Data
Writing
1
Yes·
0
No
1
Yes
0
No
1
Yes
0
No
1
Yes
0
No
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Figure 2-6. Memory Cell Range That Can be Written in Block Write Cycle
512
L -_ _ _
3rd Columns (W2/102)
' - - - - - - 2nd Columns (W1/101)
L -_ _ _ _ _ _
Remarks 1.
1st Columns (WO/IOO)
IiIiEI is the memory cell range that can be written in one block write cycle.
2. ( ) is the W/IO pin input with the column select data.
2.7 Register Set Cycle (Color Register, Write Mask Register)
This cycle writes data in the color register and write mask register. To execute the register set cycle, set CAS,
DT/OE, WB/WE and DSF to high level at the falling edge of RAS. Determine which register tq select according
to the DSF level at the falling edge of CAS.
The register set cycle also serves as the RAS only refresh cycle.
Table 2-4. Register Selection
DSF level at CAS falling edge
Selected register
High level
Color register
Low level
Write mask register
Caution After selecting the write mask register and writing the mask data, the write-per-bit function in the
mask write cycle will be set for the old mask register. Refer to 2.B.1 Write-Per-Bit Function.
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2.8 Mask Write Cycle
Cycles that use the write-per-bit function during the random write cycle, flash write cycle, block write cycle,
write data transfer cycle, are called mask write cycles. In the fast page/hyper page mode write cycle, the mask
data cannot be changed during the CAS cycle.
2.8.1 Write-Per-Bit Function
The write-per-bit function writes data using the mask data only in the required IO-pin. It writes when the mask
data is "1" and prohibits writing when the data is "0".
Table 2-5. Mask Data Selection
WPin
WO to W7
Mask Data
Writing
1
Yes
0
No
2.8.2 Selecting Mask Data
There are two ways of selecting mask data. One is the new mask data method and the other is the old mask
data method.
With the new mask data method, new mask data is set in the cycle writing. With the old mask data, mask
data set in the write mask register is used.
(1) New Mask Data Method
The new mask data method consists of the write mask register set cycle (new mask selection) method
and CAS before RAS refresh cycle (optional reset cycle) method.
However, only the CAS before RAS refresh cycle (option reset cycle) can be used in version A. Table 26 lists how to select the new mask data method for each version.
Table 2-6. New Mask Data Selection Method for Each Version
New mask data selection method
Method to use the write mask
Version A
Version F
Version E
unusable
usable
usable
usable
usable
usable
register set cycle (new mask
selection)
Method to use the CAS before
--
RAS refresh cycle (option reset
cycle.)
(a) Method Using Write Mask Register Set Cycle (New Mask Selection) (Versions F and E)
This method is usable in both version F and version E.
----
To switch to the mode using new mask data, keep the DT/OE, WB/WE DSF to high level and set the
CAS and DSF to high level at the falling edge of RAS, the DSF to low level at the falling edge of CAS,
and start up the next RAS and CAS after the tCAS and tRAS.
As a result, the write-per-bit function can be used using the new mask data from the next mask write
cycle.
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(b) Method Using CAS Before RAS Refresh Cycle (Optional Reset Cycle) (All versions)
This method is usable in all versions.
To switch to the mode using new mask data, set the DSF to low level at the falling edge of CAS in
the CAS before RAS refresh cycle.
As a result, the write-per-bit function can be used using the old mask data from the next mask write
cycle.
(2) Old Mask Data Method
To switch to the mode using old mask data, set the DSF to low level at the falling edge of CAS in the write
mask register set cycle, and write the mask data in the write mask register.
As a result, the write-per-bit function can be used using the old mask data from the next mask write cycle.
2.8.3 Execution of Mask Write Cycle
To execute the write-per-bit function, select the new mask data method or old mask data method, and set
WB/WE to low level at the falling edge of RAS of each write cycle. At this time, input the mask data to the W
pin in the write cycle using the new mask data. In the write cycle using the old mask data, as the mask data set
to the write mask register will be used, there is no need to input the mask data to the W pin.
This function is valid only at the falling edge of RAS. In the fast page/hyper page mode write cycle, the mask
data determined in the first RAS cycle for moving onto the next fast page/hyper page mode will be valid while
the fast page/hyper page mode write cycle continues.
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2.9 Refresh Cycle
The refresh cycle of this product consists of the CAS before RAS refresh cycle and refresh cycle using external
address inputs (RAS only refresh and read/write refresh). The refresh period is the same as the DRAM (Standard),
512 cycles/8 ms.
2.9.1 Refresh Cycle Using External Address Input (RAS Only Refresh and Read/Write Refresh)
By specifying the row address using the 9 bits between AO to A8 at the falling edge of RAS, setting CAS· and
DT/OE to high level, and keeping CAS at high level while RAS is low level, the memory cells on the specified
row address (512 x 8 bits) can be refreshed. At this time, refresh is executed, WO to W7/IOO to 107 pins are kept
at high impedance, and information such as memory contents, register data, function settings, etc. are all also
kept.
At the falling edge of RAS, all cycles whose CAS are high level input the external address. Therefore, in addition to the read/write cycle operations, etc. refresh operations similar to the RAS only refresh operations will be
performed. For this reason, in systems in which addresses in the memory are always increased or decreased,
it may not be necessary to perform refresh again.
When several devices exist on one bus, data will clash in the bus during the above read/write operations unless
each device is equipped with a buffer. Consequently, as it is necessary to set the I/O line to high impedance
beforehand during refresh, normally the RAS only refresh operation is used.
2.9.2 CAS Before RAS Refresh Cycle (Including Hidden Refresh)
When CAS is setto low level atthe falling edge of RAS, the refresh address is supplied from the internal refresh
address counter. The internal refresh address counter is increased automatically each time this refresh cycle
is executed.
During this refresh cycle, functions of random access port and serial access port are selected as follows
according to the DSF and WB/WE levels at the falling edge of RAS.
(1) When DSF is low level: Optional reset
All STOP register data become" 1" and the mask write cycle switches to the new mask data method.
(2) When DSF is high level and WB/WE is low level: STOP register set
The STOP register data is input from the AO to A7 pins at the falling edge of RAS.
(3) When DSF, WB/WE is high level: No reset
Only refresh operations are performed and the function selection state is kept.
In all cases, the W/IO pin is kept at high impedance. When CAS and DT/OE are kept low level while the mode
is changed to the CAS before RAS refresh cycle following the read cycle, and RAS is activated, the hidden refresh
cycle will be initiated. In this cycle, the W/IO pin does not become high impedance and the data read in the former
read cycle will be kept as it is.
Because internal memory operations are equivalent to CAS before RAS refresh, no external addresses are
required.
Like CAS before RAS refresh, in the hidden cycle, functions will be selected according to the level of DSF,
WB/WE at the falling edge of RAS. Operations are guaranteed when DSF is low level and when DSF, WB/WE
are high level.
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3. Serial Access Port Operations
There are two types of data transfer cycles-data transfer from the random access port to the serial access port
(read ,data transfer) and data transfer from the serial access port to the random access port (write data transfer).
There are also two types of data transfer methods-single data transfer and split data transfer.
To set the data transfer cycle, input high level to CAS and input low level to DT/OE at the falling edge of RAS.
The data transfer type differs according to the input levels of WB/WE, and DSF at the falling edge of RAS.
Table 3-1. Serial Access Port Operation Mode
At RAS Falling Edge
CAS DT/OE WB/WE
H
L
H
Transfer Direction
Data Transfer Type
DSF
L
Transfer
Destination
Single read data transfer
Random access
Serial access
port
I----
H
L
H
H
Split read data transfer
port
H
L
L
L
Single mask write data transfer Note
Serial access
Random access
H
L
L
H
Split mask write data transferNote
port
port
Note Write-per-bit function can be specified.
Remark H: High level, L: Low level
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3.1 Single Data Transfer Method
With this method, 512 words x 8 bits (whole memory range of serial access port) data is transferred at one
time. This method can be used in both write data transfer and read data transfer.
3.1.1 Single Read Data Transfer Cycle
This cycle transfers the 4K-bit (512 words x 8 bits) data of the random access port to the serial access port
in one cycle.
(a) Setting of Single Read Data Transfer Cycle
To set the data transfer cycle, input a high level to CAS and WB/WE and low level to DT/OE and DSF at
the falling edge of RAS.
Using the row address input to AD to A8 at the falling edge of RAS, the memory cells (512 words x 8 bits)
of the transfer source of the random access port can be selected. The address data input to AD to A8 at
the falling edge of CAS will be latched as the TAP register data of serial access port. Refer to 3.4 TAP
Register.
(b) Execution of Single Read Data Transfer Cycle
To execute the data transfer cycle, set the single read data transfer cycle and then input a high level to
DT/OE and RAS.
When SC is active (edge control), data transfer will be executed at the rising edge of DT/DE. When SC
is inactive (self control), it will be executed at the rising edge of RAS. At the same time, the serial address
pointer jumps to the start column (TAP) of the next serial read cycle, and the TAP register will be set the
empty state.
After the transfer is completed, the new serial access port data is output after tSCA following the rise of
the SC clock that occurs after tSDH if the SC is active, and after tSDHR if SC is inactive.
Caution When the single read data transfer cycle is executed while the serial access port is performing
serial write operations. the serial access port will start serial read operations at the rising edge
of RAS. Refer to 4. Electrical Characteristics Read Data Transfer Cycle (Serial Write ~ Serial
Read Switching) Timings,
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3.1.2 Single Mask Write Data Transfer Cycle
This cycle transfers 4K-bit (512 word x 8 bits) data of the serial access port to the random access port in one
cycle. Because WB/WE is low level at the falling edge of RAS, the write-per-bit function always functions in this
transfer cycle. Refer to 2.8 Mask Write Cycle.
(a) Setting of Single Mask Write Data Transfer Cycle
To set this cycle, latch the data to be transferred to the serial access port, and then input a high level to
CAS and low level to DT/OE, WB/WE, and DSF atthefalling edge of RAS. Becausethewrite-per-bitfunction
functions in this transfer operation, for the new mask data method, the mask data must be supplied to
WD to W7 at the falling edge of RAS, and for the old mask data method, there is no need to control the
mask data.
The memory cells (512 words x 8 bits) of the transfer destination of the random access port are selected
using the row address input to AD to A8 at the falling edge of RAS. The address data input to AD to A8
atthe falling edge of CAS is input as the TAP register data of serial access port. Refer to 3.4 TAP Register.
(b) Execution of Single Mask Write Data Transfer Cycle
To execute this cycle, set the single write data transfer cycle and then input high level to RAS. Data will
be transferred at the rising edge of RAS. At the same time, the serial address pointer jumps to the start
column (TAP) of the next serial write cycle, and the TAP register will be set the empty state.
After the transfer is completed, the new serial access port data is latched at the rising edge of the SC clock
that occurs after
\!;IJIIH.
Caution 1. When the single mask write data transfer cycle is executed while the serial access port is
performing serial read operations, the serial access port will start serial write operations at
the risin!) edge of RAS. Refer to 4. Electrical Characteristics Write Data Transfer Cycle (Serial
Read
) Serial Write Switching) Timings.
2. Always make CAS low level in the write data transfer cycle and latch TAP. If write data
transfer is performed without setting TAP, serial access port operations cannot be ensured
until either one of the following points. If the SC clock is input during this time, the serial
register value also cannot be guaranteed.
• Until the falling edge of CAS during the write data transfer cycle
• Until the read data transfer cycle is executed again
Figure 3-1. Single Write Data Transfer and TAP Operation
Before transfer
Random Access Port
r----------,
After transfer
Random Access Port
r----------,
TAP register
I·Em pty" I
Serial Access Port
Serial Access Port
LI_--.______
....J
C
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TAP
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3.2 Split Data Transfer Method
With this method, the 512 words x S bits (whole memory range of serial access port) data is divided into the
lower column (0 to 255) and upper column (256 to 511), each consisting of 256 words x S bits.
Because the columns are divided into upper and lower columns with this method, data transfer can be
performed on lower column (or upper column) while performing read/write operations in the upper column (or
lower column). For this reason, transfer timing design is easy. This transfer method can be used in both write
data transfer and read data transfer.
This transfer method uses -either oftwo modes, "MSB Care" and "MSB Don't Care," depending on the method
used to select the column for data transfer (See the table below.). The mode to be used varies from one version
to another. Refer to 7. Example of Stamping for how to identify each version.
Table 3-2. Differences between the MSB Don't Care and MSB Care Modes
Version
Mode
MSB Don't Care
Versions A and F
Function
AS input as TAP is ignored, and an inactive column is selected
automatically for data transfer.
MSB Care
Version E
Thecolumn (upper or lower) is specified fordata transfer according
to AS input as TAP.
3.2.1 Split Read Data Transfer Cycle (Versions A and F: For "MSB Don't Care")
This cycle divides the 4K-bit (512 words x S bits) data of the random access port into the lower and upper
columns and transfers them to the serial access port.
In this cycle, the serial read/write can be performed in the columns to which data is not transfer.
(a) Setting of Split Read Data Transfer Cycle
To set this cycle, input a high level to CAS, WB/WE and DSF, and low level to DT/OE at the falling edge
of RAS.
The memory cells (512 words x S bits) of the transfer source of the random access port are selected
using the row address input to AO to AS at the falling edge of RAS. And the address data input to AO to
A7 at the falling edge of CAS is latched as the TAP register data of serial access port. Refer to 3.4 TAP
Register. There is no need to control address data input to AS (See the table below.).
Table 3-3. Relationships among Data Register Transfer Destination, A8 Inputs, and aSF
Outputs (Split Read Data Transfer Cycle in the MSB Don't Care Mode)
AS data input to the TAP register
aSF output
AS=x
aSF = 1
Lower column (addresses 0 to 255)
aSF = 0
Upper column (addresses 256 to 511)
Remark
Data register transfer destination
1 = high level; 0 = low level; x = high or low level
(b) Execution of Split Read Data Transfer Cycle
To execute this cycle, set the split read data transfer cycle and then input the high level to RAS. Data will
be transferred at the rising edge of RAS. Data is transferred from the random access port to the serial
access port automatically at the column side (Column not pointed to by the serial address pointer) where
serial access port is inactive. To confirm the transferred column side, check the output state of the aSF
pin. Refer to 3.3.3 aSF Pin Output.
When the serial address pointer comes to the jump source address specified by the STOP register, the
serial address pointer jumps to the start column (TAP) of the serial read/write cycle at the inactive column
side, and the TAP register will be set the empty state.
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3.2.2 Split Read Data Transfer Cycle (Versions E: For "MSB Care")
This cycle divides the 4K-bit (512 words x 8 bits) data of the random access port into the lower and upper
columns and transfers them to the serial access port.
In this cycle, the serial read/write can be performed in the columns to which data is not transfer.
(a) Setting of Split Read Data Transfer Cycle
To set this cycle, input a high level to CAS, WB/WE and DSF, and low level to DT/OE at the falling edge
of RAS.
The memory cells (512 words x 8 bits) of the transfer source of the random access port are selected
using the row address input to AO to A8 at the falling edge of RAS. And the address data input to AO to
A8 at the falling edge of CAS is latched as the TAP register data of serial access port. Refer to 3.4 TAP
Register.
If the address data input to A8 is 0, data in lower columns is trasferred from the random access port to
the serial access port. If it is 1, data in upper columns is transferred from the random access port to the
serial access port. To perform the data transfer in columns for which no serial read is not being made
(columns for which the serial register is inactive), it is necessary to supply an'inverted QSF output to A8
(See the table below.).
Table 3-4. Relationships among Data Register Transfer Destination, AS Inputs, and QSF
Outputs (Split Read Data Transfer Cycle in the MSB Care Mode)
A8 data input to the TAP register
QSF output
A8=0
QSF = 1
A8 = 1
QSF
Remark
1 = high level; 0
~
~
0
Data register transfer destination
Lower column (addresses 0 to 255)
Upper column (addresses 256 to 511)
low level
(b) Execution of Split Read Data Transfer Cycle
To execute this cycle, set the split read data transfer cycle and then input the high level to RAS. Data will
be transferred at the rising edge of RAS. Data in the upper or lower column is transferred from the random
access portto the serial access port, depending on the data inputto A8. To confirm the transferred column
side, check the output state of the QSF pin. Refer to 3.3.3 QSF Pin Output.
When the serial address pointer comes to the jump source address specified by the STOP register, the
serial address pointer jumps to the start column (TAP) ofthe serial read/write cycle atthe inactive. column
side, and the TAP register will be set the empty state.
Caution When data is tranferred in a split read data transfer cycle, if the related serial register is already
involved in serial read/write operation, the serial address pointer changes during data transfer,
and the TAP register becomes empty. The timing for this operation is the same as for the read
data transfer cycle (SC inactive).
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3.2.3 Split Mask Write Data Transfer Cycle (Versions A and F: For nMSB Don't Caren)
This cycle divides the 4K-bit (512 words x8 bits) data ofthe serial access port into the lower and upper columns
and transfers them to the random access port.
In this cycle, serial read/write can be performed for columns to which data is not transferred.
Because WB/WE is low level at the falling edge of RAS, the write-per-bit function always functions in this
transfer cycle. Refer to 2.S Mask Write Cycle.
(a) Setting of Split Mask Write Data Transfer Cycle
To set this data transfer cycle, input a high level to CAS and DSF and low level to DT/OE, WB/WE at the
falling edge of RAS. Because the write-per-bit function functions in this transfer operation, for the new
mask data method, the mask data must be supplied to WO to W7 at the falling edge of RAS, and for the
old mask data method, there is no need to control the mask data.
The memory cells (512 words x 8 bits) of the transfer destination of the random access port are selected
using the row address input to AO to A8 at the falling edge of RAS. The address data input to AO to A7
at the falling edge of CAS is input as the TAP register data. Refer to 3.4 TAP Register. There is no need
to control address data input to A8 (See the table below,),
Table 3-5. Relationships among Data Register Transfer Source, AS Inputs, and aSF
Outputs (Split Write Data Transfer Cycle in the MSB Don't Care Mode)
A8 data input to the TAP register
aSF output
AS = x
aSF = 1
Lower column (addresses 0 to 255)
aSF=O
Upper column (addresses 256 to 511)
Remark
Data register transfer destination
1 = high lovol; 0 = low lovel; x = high or low level
(b) Execution of Split Mask Writo Data Transfer Cycle
To execute this cycle, set tho split write data transfer cycle and then input high level to RAS. Data will
be transferred at the rising edge of RAS. Data is transferred from the serial access port to the random
access port automatically at the column side (Column not pointed to by the serial address pointer) where
the serial access port is inactive. To confirm the transferred column side, check the output state of the
aSF pin. Refer to 3.3.3 aSF Pin Output.
When the serial address pointer comes to the jump source address specified by the STOP register, the
serial address pointer jumps to the start column (TAP) ofthe serial read/write cycle at the inactive column
side, and the TAP register will be set the empty state.
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3.2.4 Split Mask Write Data Transfer Cycle (Versions E: For "MSB Care")
This cycle divides the 4K-bit (512 words x 8 bits) data of the serial access port into the lower and upper columns
and transfers them to the random access port.
In·this cycle, serial read/write can be performed for columns to which data is not transferred.
Because WB/WE is low level at the falling edge of RAS, the write-per-bit function always functions in this
transfer cycle. Refer to 2.S Mask Write Cycle.
(a) Setting of Split Mask Write Data Transfer Cycle
To set this data transfer cycle, input a high level to CAS and DSF and low level to DT/OE, WB/WE at the
falling edge of RAS. Because the write-per-bit function functions in this transfer operation, for the new
mask data method, the mask data must be supplied to WO to W7 at the falling edge of RAS, and for the
old mask data method, there is no need to control the mask data.
The memory cells (512 words x 8 bits) of the transfer destination ofthe random access port are selected
using the row address input to AO to A8 at the falling edge of RAS. The address data input to AO to A8
at the falling edge of CAS is input as the TAP register data. Refer to 3.4 TAP Register.
If the address data input to A8 is 0, data in lower columns is transferred fro'm the serial access port to
the random access port. If it is 1, data in upper columns is transferred from the serial access port to the
random access port. To perform the data transfer in columns for which no serial write is not being made
(columns for which the serial register is inactive), it is necessary to supply an inverted QSF output to A8
(See the table below.).
Table 3-6. Relationships among Data Register Transfer Source, AS Inputs, and aSF
Outputs (Split Write Data Transfer Cycle in the MSB Care Mode)
AB data input to the TAP register
QSF output
A8= 0
aSF = 1
Lower column (addresses 0 to 255)
A8 = 1
QSF=O
Upper column (addresses 256 to 511)
Remark
Data register transfer destination
1 = high level; 0 = low level
(b) Execution of Split Mask Write Data Transfer Cycle
To execute this cycle, set the split write data transfer cycle and then input high level to RAS. Data will
be transferred at the rising edge of RAS. Data in the upper or lower column is transferred from the serial
access port to the random access port, depending on the data input to AB. To confirm the transferred
column side, check the output state of the QSF pin. Refer to 3.3.3 aSF Pin Output.
When the serial address pointer comes to the jump source address specified by the STOP register, the
serial address pointer jumps to the start column (TAP) ofthe serial read/write cycle at the inactive column
side, and the TAP register will be set the empty state.
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Figure 3·2. Split Mask Write Data Transfer and TAP Operations
Before transfer (Upper column)
Random Access Port . - - - - - - - , - - - - - ,
After transfer (Upper column)
Random Access Port . - - - - - - - , - - - - - ,
TAP register
'''Empty'' ,
Serial Access Port
Serial Access Port
+-____----l
L-_ _ _ _
c==J
I:,Ba.:...l..'_ _--.I
~ata 1
Serial write start
Before transfer (Lower column)
Random Access Port
After transfer (Lower column)
Random Access Port , - - - - - - , - - - - - ,
~"-~~-I TAP register
"Em pty"
S"I,' A,,~,
portp
Serial Access portL,I-L_ _---J
Serial write start (TAP data 1)
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3.3 Serial Read/Write
The serial access port (512K x B bits) is independent from the random access port and can perform read and
write operations. The serial access port performing single data transfer and split data transfer can not perform
read and write operations independently.
Caution When the power is turned on, the serial access port sets into the input (write) mode and the SIO
pin is the high impedance state.
3.3.1 Serial Read Cycle
To set the serial read cycle, perform the single read data transfer cycle (The mode will not change in the split
read data transfer cycle.).
Execute the single read data transfer cycle and latch the data and TAP data. By inputting a clock signal to
the SC pin and inputting a low level to the SE pin, data will be output from the serial address pointer specified
by TAP register. The data synchronizes with the rising edge of the SC clock and is output from the SIOO to SI07
pin, and the data is kept until the next rising edge of the SC clock.
(a) Reading-Jump
The SE pin controls the SIO pin output buffer independently from the SC clock. By setting the SE pin to
high level even while inputting the SC clock, SIOO to SI07 pins become high impedance. But the
operations of serial address pointer will be continued while the SC clock is being input even though
reading has been prohibited from SE pin. Reading-jump of the ·column can be performed using this
function.
3.3.2 Serial Write Cycle
To set the serial write cycle, perform the single write data transfer cycle (The mode will not change in the split
write data transfer cycle.). To prevent the transfer data from being written in the memory cell of the random
access port, set all bits of the mask data to "0" and control the mask data.
Execute the single write data transfer cycle and set the serial write cycle. By inputting the clock signal to the
SC pin and inputting a low level to the SE pin, data can be latched from the serial address pointer specified by
TAP register. The data synchronizes with the rising edge of the SC clock and is input from SIOO to SI07 pins.
Be sure to follow the specifications for the setup time (tSES) and hold time (tSEH) of SE pin for the SC clock..
(a) Writing-Jumps (Intermittent Writing)
The SE pin controls writing operations independently from the SC clock. By setting the SE pin to high
level even while inputting the SC clock, writing will not be executed. But the operations of serial address
pointer will be continued while the SC clock is being input even though writing has been prohibited from
SE pin. These functions enable writing-jumps (intermittent writing) to be performed. The masked data
is kept as the old data.
3.3.3 aSF Pin Output
aSF pin determines whether the serial address pointer is at the upper column side (addresses 256 to 511)
or the lower column side (addresses 0 to 255) at the rising edge of the following SC clock during serial read or
write. In other words, it outputs the uppermost bit (AB) of the column address of the serial address pointer.
The following table shows the aSF pin output state and the access pointer of following SC clocks.
136
Access Address of Following SC clock
aSF Output
Addresses 0 to 255
Low level
Addresses 256 to 511
High level
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3.4 TAP (Top Access Point) Register
The TAP register is a data register which specifies the start address (first serial address point = TAP) of the
serial read or serial write.
Set data, to this register each time a transfer cycle is executed.
3.4.1 Setting of TAP Register
The data input to AO to A8 at the falling edge of CAS during the setting of a transfer cycle is'set as the TAP
register data. By executing the transfer cycle, the start address of the following serial read (or write) operations
is specified by the data of the TAP register and the TAP register will be kept in the empty state until the TAP register is set again.
In the split data transfer cycle (Versions A and F: For "MSB Don't Care"), because the inactive serial access
port column addresses are specified by the data of the TAP register automatically, there is no need to control
the A8 data. However in the split data transfer cycle (Version E: For "MSB Care"), the data in the TAP register,
which is input to A8, specifies the column on the side that performs the transfer (A8 = 0: Lower column, A8 =
1: Upper column).
Caution When the TAP register is empty, the address following the 511 serial address point will be
o.
In
addition, because the serial address pointer will not jump to the column specified by the STOP
register, the binary boundary jump function cannot be used. Refer to 3.6 Binary Boundary Jump
Function.
3.5 STOP Register
The STOP register is a data register which determines the column of the jump source when jumping to a
different column side (lower column or upper column) in the split data transfer cycle. Five types of columns can
be selected for starting jump (jumping' is possible at 2,4,8, 16, and 32 points). The following table shows the
correspondence between the column at the jump source and data of the STOP register.
Once set, the STOP register data is kept until it is set again.
3.5.1 Setting of STOP Register
To set the STOP register, set WB/WE to low level at the falling edge of RAS in the CAS before RAS refresh
cycle. The data input to AO to A7 will be input as the STOP register data.
137
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yPD482234,482235
Table 3-7. STOP Register Data and Jump Source Column
STOP Register Data
DiviBit
A7 A6 A5 A4 A3 to AO sion Width
1
1
1
1
1
1/2
256
Jump Source Bit Column (Decimal Number)
255
511
1
0
1
1
1
1/4
128
127, 255
383, 511
0
0
1
1
1
1/8
64
63, 127, 191, 255
319,383,447,511
0
0
0
1
1
1/16
32
31,63,95, 127, 159, 191,223,255
287,319,351,383,415, 447, 479, 511
0
0
0
0
1
1/32
16
15,31. 47, 63, 79,95,111,127,143,159,175,191,207,223,239,255
271,287,303,319,335,351,367,383,399,415,431, 447, 463, 479, 495, 511
Remark A8: Don't care.
Caution When the power is supplied, all STOP register data will be set to all "1".
3.6 Binary Boundary Jump Function
This function causes the serial address pointer jumptothe TAP specified by the TAP register when the pointer
moves to a column specified by the STOP register (split data transfer).
This function cannot be used when the jump destination address is not set (TAP register is empty).
This function facilitates tile map application which divides the screen into tiles and manages data for each
tile.
3.6.1 Usage of Binary Boundary Jump Function
After setting the STOP register, execute the single read (or write) data transfer and initialize the serial access
port. The initialization process will switch the serial access port read (or write) operations, set TAP, set the serial
access port data, and set the TAP register to empty. By inputting the serial clock in this state, the serial access
port will read (or write) operations from TAP in ascending order of address. Because the TAP register is in the
empty state, the address at the jump source set by the STOP register will be ignored, and the serial address
pointer will move on.
When the column to be jumped approaches, execute split data transfer and set new TAP data in the TAP
register. The serial pointer will jump at the desired jump source address. Jump can be controlled freely by
repeating these operations.
138
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yPD482234,482235
3.7 Special Operations
3.7.1 Serial Address Set Operations
Because -the serial address counter is undefined when the power up, the serial access port operations when
the SC clock is input are not guaranteed. Execute single read (or write) transfer after turning on the power. The
serial access port will be initialized, enabling serial access port operations to be performed.
3.7.2 Lap Around Operations
If all the data of the register is read (write) during data transfer while the serial read (write) cycle is being
executed, the serial pointer will repeat 0 to 511.
3.7.3 Cycle After Power On
After supplying power, initialize the internal circuitry by waiting for at least 100 liS after Vcc <:: 4.5 V, then
supplying at least 8 RAS clock cycles. The RAS clock only requires that tAC, tAAS, and tAP are satisfied; there is
no problem if other signals are in any state. Note however that ifthe signal supplied to RAS, CAS, DT/OE, and
WB/WE is high at power-on, the serial access port and each register have the following values.
• Serial access port ........ Input mode, SID: High impedance
• Color register ............... Undefined
• Mask register ............... AII "1"
• TAP register ................. Undefined
• STOP register .............. AII "1"
139
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gPD482234,482235
4. Electrical Characteristics
Absolute Maximum Ratings
Symbol
Rating
Unit
Pin voltage
VT
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
rnA
Parameter
Power dissipation
Po
1.5
W
Operating ambient temperature
TA
o to 70
°C
Storage temperature
Tstg
-55 to +125
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
in the operational sections of this characteristics. Exposure to Absolute Maximum rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
MIN.
TYP.
MAX.
Unit
Supply voltage
Vee
4.5
5.0
5.5
V
High level input voltage
VIH
2.4
5.5
V
Low level input voltage
VIL
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
°C
Parameter
140
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yPD482234,482235
DC Characteristics 1 (Recommended operating conditions unless otherwise noted)
Symbol
Parameter
Input leakage current
MAX.
Unit
-10
+10
p.A
WilD, 510, QSF are inactive,
-10
+10
p.A
VOH (R)
= 0 V to 5.5 V
IOH (R) = -1.0mA
2.4
VOL (R)
IOL (A)
= 2.1 rnA
VOH (5)
IOH (5)
= -1.0mA
VOL (5)
101. (5) " 2.1 rnA
ilL
Test conditions
VIN
= 0 V to 5.5 V,
MIN.
TYP.
Other inputs are 0 V
Output leakage current
IOL
VOUT
Random access port
V
high level output voltage
Random access port
0.4
V
low level output voltage
Serial access port
2.4
V
high level output voltage
Serial access port
0.4
V
MAX.
Unit
pF
low level output voltage
Capacitance (TA
=25 ·C, f =1MHz)
Parameter
Input Capacitance
Symbol
Test conditions
MIN.
TYP.
Cil
RAS, CAS, WB/WE, OT/OE, OSF, SE, SC
8
CI2
AO to A8
5
Input/Output Capacitance
Cia
WilD (0 to 7), 510 (0 to 7)
7
pF
Output Capacitance
Co
QSF
7
pF
141
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gPD482234,482235
DC Characteristics 2 (Recommended operating conditions unless otherwise notedlNote 1
(JlPD4822341
JlPD482234-60 JlPD482234-70 JlPD482234-80
Serial Access Port
Random Access Port
Random Read/Write Cycle
RAS, CAS cycle,
tRC
= tRC (MIN.),
10
Standby Active
0
0
= OmA
Standby
= CAS = V'H,
DouT = high impedance
0
Symbol
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit Conditions
Icc,
110
130
130
Icc,
155
195
190
Icc2
10
10
10
mA
1
1
1
mA
ICC8
55
70
65
mA
Icc3
110
115
115
mA
Note 4
Icc.
155
180
175
Icc.
100
100
90
mA
Note 5
Icc,o
145
165
150
Iccs
110
90
90
Icc11
155
155
150
Ice6
120
140
140
Icc12
165
205
200
Icen
100
120
120
Icc"
145
185
180
lec10
100
120
120
Icclo
145
185
180
Icc 17
120
130
130
lce'8
165
195
190
Icc,.
100
110
100
lce20
130
175
160
mA
Note 2
RAS
0
RAS only refresh cycle
RAS cycle, CAS
tRC = tnc (MIN.)
= VIH,
0
0
Fast page mode cycle
RAS = VIl, CAS cycle,
trc = tpc (MIN.)
0
CAS before RAS refresh cycle
tile = tRC (MIN.)
0
0
Note 3
i-==
0
Onto transfer cycle
tile = tRe (MIN.)
0
0
Color/Mask write register set cycle
tliC = tRC (MIN_)
0
0
Flnsh write cycle
tnc = tRe (MIN.)
0
0
Block write cycle
tliC = tRe (MIN.)
0
0
Fnst page mode block write cycle
tre = tpe (MIN.)
0
0
mA
mA
mA
mA
mA
mA
Note 5
Notes ,_ No load on WilD, 510, QSF. The current consumption actually used depends on the output load
and operating frequency of each pin_
2_ A change in row addresses must not occur more than once in tRC = tRC (MIN_).
3. RAS, CAS, and SE remain at VIH
VIH
~
~
Vcc - 0.2 V, and AD to A8, WB/WE, DT/OE, DSF, SC remain at
Vcc - 0_2 V or VIL:5 GND + 0_2 V.
4. When the address input is set to VIH or VIL during the tRAS period_
5_ Value when the address in tpc one cycle is changed once when tpc = tpc (MIN_)_
142
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yPD482234,482235
DC Characteristics 2 (Recommended operating conditions unless otherwise noted)Note 1
(,uPD482235)
IIPD482235·60 /lPD482235·70 /lPD482235·80
Serial Access Port
Random Access Port
Standby Active
Random ReadlWrite Cycle
RAS, CAS cycle,
0
=tRC (MIN.), 10 = OmA
tRC
0
Standby
RAS
DouT
0
= CAS = VIH,
= high impedance
0
RAS only refresh cycle
RAS cycle, CAS VIH,
tRC tRC (MIN.)
0
Hyper page mode cycle
RAS VIL, CAS cycle,
tHPC tHPC (MIN.)
0
CAS before RAS refresh cycle
tRC tRC (MIN.)
0
=
=
0
=
=
0
=
0
Data transfer cycle
tRC tRC (MIN.)
0
=
0
Color/Mask write register set cycle
tRe tRC (MIN.)
0
=
0
Flash write cycle
tRC tRC (MIN.)
0
Block write cycle
tRC tRC (MIN.)
0
=
0
=
0
Hyper page mode block write cycle
tHPe tHPC (MIN.)
0
=
0
Symbol
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit Conditions
mA
ICCl
110
130
130
IcC7
155
195
190
Icc2
10
10
10
mA
1
1
1
mA
Icc.
55
70
65
mA
Icc3
110
115
115
mA
Note 4
Icc9
155
180
175
Icc.
120
130
120
mA
Noto 5
ICC10
155
195
180
Icc,
110
90
90
Icc11
155
155
150
Iccs
120
140
140
ICC12
165
205
200
Ice13
100
120
120
lec14
145
185
180
Iccl.
100
120
120
lecl.
145
185
180
lee17
120
130
130
lecl.
165
195
190
lee19
140
135
125
Icc20
190
200
185
Note 2
Note 3
mA
mA
mA
mA
mA
mA
Noto 5
Notes 1. No load on WIlD, SID, QSF. The current consumption actually used depends on the output load
and operating frequency of each pin.
2. A change in row addresses must not occur more than once in tRC = tRC (MIN.).
3. RAS, CAS, and SE remain at VIH
VIH
?;
VCC - 0.2 V or VIL
S;
?;
VCC - 0.2 V, and AO to A8, WB/WE, DT/OE, DSF, SC remain at
GND + 0.2 V.
4. When the address input is set to VIH or VIL during the
mAS
period.
5. Value when the address in tHPC one cycle is changed once when tHPC = tHPC (MIN.).
143
NEe
uPD482234,482235
AC Characteristics (TA
= 0 to 70 ·C, Vee = 5.0 V ± 10 %, GND = 0 v)Notes 1, 2. 3, 4
(Common for JLPD482234, 482235)
Parameter
(1/4)
,uPD482234-60 ,uPD482234-70 ,uPD482234-80
Symbol ,uPD482235-60 ,uPD482235-70 ,uPD482235-80 Unit
Condition
MIN. MAX. MIN. MAX. MIN. MAX.
Access time from RAS
tRAC
60
70
80
ns
Note 5
Access time from CAS
tCAC
15
20
25
ns
Note 5
Access time from column address
tAA
30
35
40
ns
.Note 5
Access time from CAS trailing edge
tACP
35
40
45
ns
Access time from OE
tOEA
15
20
25
ns
Serial output access time from SC
tSCA
15
17
20
ns
Serial output access time from SE
tSEA
15
17
20
ns
Output disable time from SE high
tSEZ
0
15
15
20
ns
Random read or write cycle time
tRC
120
140
150
ns
IRWC
165
185
205
ns
IT
3
tAP
50
tRAS
60
10,000
70
tRASP
60
100,000
70
tRSH
15
tCPN
10
tcp
CAS hold time
Read modify-write cycle time
Transition time (Rise/Fall)
-
-RAS precharge time
35
0
3
35
0
3
35
ns
60
ns
10,000
80
10,000 ns
100,000
80
100,000 ns
20
25
ns
10
10
ns
10
10
10
ns
tCSH
60
70
80
ns
RAS to CAS delay time
tACO
20
CAS high to RAS low precharge time
tCRP
5
10
10
ns
RAS high to CAS low precharge time
tRPC
10
10
10
ns
Row address setup time
tASA
0
0
0
ns
Row address hold time
tRAH
10
10
12
ns
Column address setup time
tASC
0
0
0
ns
Column address hold time
tCAH
10
10
12
ns
RAS to column address delay time
tRAD
15
Column address to RAS lead time
tRAL
30
35
40
ns
Read command setup time
tACS
0
0
0
ns
-.
RAS pulse width
60
NoteS
(Non page mode)
HAS pulse width
(Fast page/Hyper page mode)
RAS hold time
--
CAS precharge time
(Non page mode)
CAS precharge time
(Fast page/Hyper page mode)
144
40
30
20
15
50
35
22
17
55
40
ns
ns
Note 5
NoteS
NEe
yPD482234,482235
(2/4)
(Common for JlPD482234. 482235)
/lPD482234-60 JlPD482234-70 JIPD482234-80
Parameter
Symbol JlPD482235-60 JlPD482235-70 JlPD482235-80 Unit
Condition
MIN. MAX. MIN. MAX. MIN. MAX.
tRRH
0
0
0
ns
Note 7
tRCH
0
0
0
ns
Note 7
DE hold time after RAS high
tORH
10
10
10
ns
Note 8
DE hold time after CAS high
tacH
10
10
10
ns
Note 8
Write command setup time
twcs
0
0
0
ns
Note 10
Write command hold time
twCH
10
12
15
ns
Write command pulse width
twp
10
12
15
ns
Write command to RAS lead time
tRWL
20
20
20
ns
Write command to CAS lead time
tCWL
15
15
20
ns
Data in setup time
tDS
0
0
0
ns
Note 9
Data in hold time
tDH
12
12
15
ns
Note 9
Refresh period
tREF
CAS to WB/WE delay time
tCWD
40
40
50
ns
Note 10
RAS to WB/WE delay time
tRWD
85
90
105
ns
Note 10
Column address to WB/WE delay time
tAWD
55
55
65
ns
Note 10
CAS setup time
tCSR
0
0
0
ns
tCHR
10
10
12
ns
DT low setup time.
tOLS
0
0
0
ns
DT low hold time after RAS low
tRDH
55
65
70
ns
Note 11
DT low hold time after RAS low
tROHS
10
25
30
ns
Note 11
DT low hold time after CAS low
tCDH
15
20
25
ns
Note 11
DT low hold time after address
tAOD
20
25
30
ns
Note 11
SC high to DT high
tSDD
0
0
0
ns
Note 11
SC high to CAS low
tssc
10
10
10
ns
Note 11. 15. 16
SC low hold time after DT high
tSDH
40
40
50
ns
Note 11
Read command hold time after
RAS high
Read command hold time after
CAS high
8
8
8
ms
(for CAS before RAS refresh cycle)
CAS hold time
-
-
(for CAS before RAS refresh cycle)
145
NEe
gPD482234,482235
(Common for IlPD482234, 482235)
Parameter
(3/4)
JLPD482234-60 JLPD482234-70 JLPD482234-80
Symbol JLPD482235-60 JLPD482235-70 JLPD482235-80 Unit
Condition
MIN. MAX. MIN. MAX. MIN. MAX.
SC low hold time after DT high
tSOHA
40
45
55
ns
OE high to data in setup delay time
tOEO
15
15
20
ns
OE high hold time after
tOEH
0
0
0
ns
tscc
18
22
25
ns
ns
Note 11, 15
WBfWE low
Serial clock cycle time
SC pulse width
tSCH
5
5
7
SC precharge time
tSCL
5
5
7
ns
SE low to serial output setup
tsoo
3
5
5
ns
tSOH
3
5
5
ns
DT high setup time
tOHS
0
0
0
ns
DT high hold time
tOHH
10
10
12
ns
DT high to RAS high delay time
tOTA
0
0
0
ns
delay time
Serial output hold time after
SC high
146
DT high pulse width
tOTP
20
20
25
ns
OE to RAS inactive setup time
tOES
0
0
0
ns
Write-per-bit setup time
twBS
0
0
0
ns
Write-per-bit hold time
twBH
10
10
12
ns
DSF setup time from RAS
tFAS
0
0
0
ns
DSF hold time from RAS
tFAH
10
10
12
ns
DSF setup time from CAS
tFCS
0
0
0
ns
DSF hold time from CAS
tFCH
10
12
15
ns
Write-per-bit selection setup time
tws
0
0
0
ns
Write-per-bit selection hold time
twH
10
10
12
ns
SE pulse width
tSEE
5
5
7
ns
SE precharge time
tSEP
5
5
7
ns
SE setup time
tSES
0
0
0
ns
SE hold time from SC
tSEH
10
10
12
ns
Serial data in setup time
tSIS
0
0
0
ns
Serial data in hold time
tSIH
10
10
12
ns
Serial input disable time from SC
tSIZ
0
0
0
ns
Serial output disable time from RAS
tSAZ
0
0
0
ns
Note 11
NEe
yPD482234,482235
(4/4)
(Common for JLPD482234, 482235)
Parameter
JlPD4B2234-60 JlPD4B2234-70 JLPD482234-BO
JlPD482235-60
JlPD482235-70 JLPD482235-BO Unit
Symbol
MIN.
Condition
MAX. MIN. MAX. MIN. MAX.
Serial input enable time from RAS
tSZH
20
20
25
ns
SC setup time from RAS
tSRS
10
10
10
ns
Note 14. 15. 16
SC hold time from RAS
tSRH
10
10
10
ns
Note 14
Propagation delay time from
tpo
20
20
25
ns
tROD
80
95
105
ns
65
75
ns
SC to aSF
Propagation delay time from
RAS to aSF
- - ----- ----
1-
Propagation delay time from
teao
60
toaD
30
30
35
ns
toaR
40
40
45
ns
CAS to aSF
Propagation delay time from
DT/OE to aSF
Propagation delay time from
RAS high to aSF
147
NEe
yPD482234,482235
(ttPD482234 Only)
.uPD482234-60 ,uPD482234-70 .uPD482234-80
Parameter
Symbol
MIN. MAX. MIN. MAX. MIN. MAX.
Output disable time from CAS high
tOFF
15
Unit
Condition
15
0
20
ns
Note 6,12
Output disable time from OE high
tOEZ
°
0
15
°
0
15
0
20
ns
Note 6,12
Output disable time from WB/WE low
twEZ
0
15
0
15
0
20
ns
Note 6, 12
Write command pulse width
twpz
10
12
15
ns
Note 12
tpc
40
45
50
ns
tPRWC
90
90
105
ns
tCAS
15
Fast page mode cycle time
Fast page mode read modify
write cycle time
CAS pulse width
10,000
20
10,000
20
10,000
ns
(11PD482235 Only)
IIPD482235-60 pPD482235-70 pPD482235-80
Parameter
Symbol
MIN. MAX. MIN.
MAX. MIN. MAX.
Unit
Condition
Access time from previous CAS
tACE
60
65
75
ns
Note 17
Access time from previous WE
tAWE
55
60
70
ns
Note 17
Output hold time from CAS
tOHC
3
Output disable time from RAS high
tOFR
0
15
0
15
0
20
ns
Note 6, 13
Output disable time from CAS high
tOFC
0
15
0
15
0
20
ns
Note 6,13
Output disable time from OE high
torz
0
15
0
20
ns
Note 6,13
Output disable time from WB/WE low
tW[Z
°
15
15
0
15
0
20
ns
Note 6, 13
Note 13
0
-
5
5
ns
Write command pulse width
tWI'7.
10
12
15
ns
Hyper page mode cycle time
tHPC
30
35
40
ns
tHPRWC
80
90
105
ns
tHCAS
10
Hyper page mode read modify
write cycle time
CAS pulse width
148
10,000
10
10,000
12
10,000
ns
NEe
yPD482234,482235
Notes 1. All applied voltages are referenced to GND.
2. After supplying power, initialize the internal circuitry by waiting for at least 100 JlS after Vcc ~ 4.5 V,
then supplying at least8 RAS clock cycles. The RAS clock only requires tAC, tAAS, and tAP are satisfied;
there is no problem if other signals are in any state.
3. Measure at tT = 5 ns
4. AC characteristic measuring conditions
(2) Output voltage determined
(1) Input voltage, timing
V,H (MIN.)
= 2.4
:
:
~
-3'0V
V
I
V(L(MAXI
= 0.8 V
----I
• I
VOH (MIN I
= 2.0 V
VOL (MAX.)
= 0.8 V
I
I
I
I
I
I
I
:.
tr = 5 ns
I'
• :
tr = 5 ns
(3) Output load conditions
Serial Access Port
Random Access Port
Vee
Vee
1.8380
1,8380
WIIO - - _ - - - - ;
SIO
50 pF
9930
9930
5. For read cycle, access time is defined as follows:
Input conditions
tRAD
Access time
Access time from RAS
tAAD (MAX.) and tACO
:S;
tACO (MAX.)
tAAC (MAX.)
tRAC (MAX.)
tAAD > tAAD (MAX.) and tACO
:S;
tACO (MAX.)
tAA (MAX.)
tAAD + tAA (MAX.)
tCAC (MAX.)
tACO + tCAC (MAX.)
:S;
tACO> tACO (MAX.)
tAAD (MAX.) and tACO (MAX.) are specified as reference points only;they are not restrictive operating
parameters. They are used to determine which access time (tAAC, tAA, tCAC) is to be used for finding
out data will be available. Therefore, the input conditions tAAD ~ tRAD (MAX.) and tRCD ~ tACO (MAX.)
will not cause any operation problems.
6. tSEZ, tOEz, twEZ, tOFF, tOFA, and tOFC define the time when the output achieves the condition of high
impedance and is not referenced to VOH or VOL.
7. Either tACH (MIN.) or tAAH (MIN.) should be met in read cycles.
S. Because tOAH and tOCH are used during the mask register set cycle (new mask selection) only, these
ratings are applied only to versions F and E.
9. These parameters are referenced to the following points.
(1) Early write cycle
The falling edge of CAS
(2) Late write cycle
The falling edge of WB/WE
(3) Read modify write cycle
The falling edge of WB/WE
149
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gPD482234,482235
Notes 10. twcs
~
twcs (MIN.) is the condition for early write cycle to be set. DOUT becomes high impedance
during the cycle.
tAWD ~ tAWD (MIN.), tCWD ~ tewD (MIN.). tAWD ~ tAWD (MIN.), are conditions for read modify write cycle
to be set. The data of the selected address is output to DOUT.
If any of the above conditions are not met, pin W/IO will become undefined.
11. One of the following specifications will be valid depending on the type of read data transfer method
used.
(1) DT/OE edge control: Satisfy the following specifications.
• For DT/OE edge inputs : tRDH, tCDH, tADD, tDTR
• For SC inputs
: tSDD, tSDH
(2) Self control: Satisfy the following specification.
• For DT/OE edge inputs : tADHS
• For SC inputs
: tssc, tSDHR
12. Control pins CAS, DT/OE, WB/WEtosetpinW/IOto high impedance. Becausethetimingsatwhich
CAS and DT/OE are set to high level and WB/WE is setto low level affect the high impedance state,
the specifications will change as follows.
(1) When CAS is set to high level at DT/OE (low level) and WB/WE (high level) at the end of the
read cycle: tDFF is valid
(2) When WB/WE is set to low level at CAS (low level) and DT/OE (low level) at the end of the
read cycle: tWEZ and twpz are valid
(3) When DT/OE is set to high level at CAS (low level) and WB/WE (high level) at the end of the
read cycle: tOEZ is valid
13. Control pins RAS, CAS, DT/OE, WB/WE to set pin W/IO to high impedance. Because the timings
at which RAS, CAS, and DT/OE are set to high level and WB/WE is set to low level affect the high
impedance state, the specifications will change as follows.
When controlling RAS and CAS, the output cannot be made high impedance unless both pins are
set to high. There is difference between tOFC and tOFR, because RAS and CAS control is specified
from the rising edge of the slower one.
(1) When RAS is set to high level after CAS is set to high level at DT/OE (low level) and WB/WE
(high level) at the end of the read cycle: tOFR is valid
(2) When CAS is set to high level after RAS is set to high level at DT/OE (low level) and WB/WE
(high level) at the end of the read cycle: tOFC is valid
(3) When WB/WE is set to low level at RAS, CAS (low level) and DT/OE (low level) at the end of
the read cycle: twEZ and twpz are valid
(4) When DT/OE is set to high level at RAS, CAS (low level) and WB/WE (high level) at the end
of the read cycle: tOEZ is valid
14. The tSRS and tSRH in the hidden refresh cycle, CAS before RAS refresh cycle (STOP register set cycle
and optional reset cycle) are specified to guarantee the serial port operations until the transfer
cycle is executed after the STOP register value is changed. When the STOP register value is not
to be changed, or when the binary boundary jump function is not used (when the TAP register
is empty), tSRS and tSRH will not be specified,
150
NEe
yPD482234,482235
15. tssc (split read data transfer cycle) and tSRS (split write data transfer cycle) are specified at the rising
edge of SC which reads/writes the address of the jump source in the binary boundary jump
function. tSDHR (split read data transfer cycle and split write data transfer cycle) is specified at the
rising edge of SC which reads/writes the address of the jump destination in the binary boundary
jump function. The rising edge of these SCs cannot be input in periods (1) and (2).
(1) Split read data transfer cycle: Period from the rising edge of the SC specifying tssc to that
ofthe SC specifying tSDHR (Refer to Note 2 Split Read/Write Data Transfer Cycle Timing Chart.)
(2) Split write data transfer cycle: Period from the rising edge of the SC specifying tSRS to that
ofthe SC specifying tSDHR (Referto Note 2 Split Read/Write Data Transfer Cycle Timing Chart.)
16. Restrictions to the split read data transfer cycle during serial write operation
(1) If split read data transfer is attempted for an address which is already involved in serial write,
normal operation is not guaranteed, except for a period in which no serial write has been
performed, that is from when SE goes low at the rising edge of SC to just before the serial
write begins.
(2) If split read data transfer is attempted when an address involved in serial write is the boundary
address specified by the STOP register, normal operation is not guaranteed, except for a
period in which no serial write has been performed, that is from just after the mask write or
mask split write transfer cycle is executed to just before the serial write is started by setting
SE to a low .level at the rising edge of SC.
17. In the hyper page mode, the hyper page mode read modify write cycle, the hyper page mode read
modify block write cycle, this parameter is valid when the read cycle changes to the write cycle.
151
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yPD482234,482235
Read Cycle (JlPD4822341
tRC
tRAS
tRP
RAS (Input) V'H-
VIl-
tCSH
tRCo
CAS (Input)
tRSH
V,HV,LtRAL
IAsc
Address (Input)
V,HV,L-
WBM/E (Input)
V,HV'L-
DT/DE (Input)
VIIIVII -
tCAH
tOEZ
tOFF
tCAC
________
VOH-
WO to W7/
J:!i2~-~
_______________________ _
DATADUT
100 to 107 (Output) VOL-
tFRS
DSF (Input)
tFRH
VIIIVII-
Remark Because the serial access port operates independently of the random access por:!. there is no need
to control the SC. SE. SIO pins in this cycle.
152
NEe
yPD482234,482235
Read Cycle (Extended data output: IlPD482235)
tRC
tRAS
tRP
RAS (Input) VIH-
VILtCSH
tRCD
tRSH
tHCAS
CAS (Input) VIH-
VILtASC
tRAL
tCAH
Address (Input) VIHVIL-
WBNJE (Input)
VIHVIL-
DT/OE (Input)
VIHVILtRAC
tDEZ
tM
tOFC
~ _ _ _ _ t",C-,AC,-,--t-:--i 1"'_-----"tO"'FR'--I
..tOEA.
--------~~~~-----------------------
WOto W7/
VOH100 to 107 (Output) VOL-
tFRS
DSF (Input)
DATA OUT
tFRH
VIHVIL _
Remark Because the serial access port operates independently of the random access port, ther~ is no need
to control the SC, SE, 510 pins in this cycle.
153
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yPD482234, 482235
Early Write Cycle/Early Block Write Cycle
tRe
tRAS
tRP
V,HRAS (Input)
VII tesH
tReD
tRSH
teAs tHCAS Note
V,HCAS (Input) VIltRAL
V,HAddress (Input) V,L-
V'H-
WBNl/E (Input) V,L-
V,H-
DT/OE (Input) V,L-
woto W7/
V'H100 to 107 (Input) V'L-
V'H-
DSF (Input) V'L-
Note tCAS for the JtPD482234
tHCAS for the JtPD482235
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
154
NEe
pPD482234,482235
Late Write Cycle/Late Block Write Cycle
tRe
tAAS
RAS (Input)
V,HVIL-
CAS (Input)
V,HV,L-
Address (Input)
V,HV'L-
WBf\NE (Input)
V'HV'L-
DT/OE (Input)
V,H _ --;r7-V---H-------t+---tt--+"....-.........,,:--t"-r"T"""'t"'""l:--t"-r"T"""......
V,L-
WO to W7/
V,H100 to 107 (Input) V,L-
DSF (Input)
V,HV,L _
~~~
____-L~~
Note tCAS for the IIPD482234
tHCAS for the tlPD482235
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
155
NEe
yPD482234,482235
Read Modify Write Cycle/Read Modify Block Write Cycle
tRWC
tRAS
RAS (Input)
V'HV'LtCSH
tRCD
tRSH
tCAS, tHCAS Note
CAS (Input)
V'HV,LtRAL
Address (Input)
V,HV,L _
tAWD
tCWD
twp
V,HWBNl/E (Input) V,L _
tOEH
DT10E (Input)
VIIIVII-
tCAe
tOEA
WO{
to
(Input)
V,HV,L-
W7/
100
to
107
tOEZ
(Output)
VOHVOL-
DSF (Input)
V,HV,L _
DATA OUT
----------~~~~~---------
Note tCAS for the ILPD482234
tHCAS for the ILPD482235
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
156
NEe
pPD482234,482235
Fast Page Mode Read Cycle I,uPD482234)
tRC
tRASP
RAS (Input)
CAS (Input)
Address (Input)
V'H-
V'l-
V'H-
V,l _
V,H-
V,l _
V,H _
WBfWE (Input)
tRP
V'l-
"""7-rTM..-++-..!f----++-t-----++-+----+---1H--7
L...l....L..~...J
V,HDT/OE (Input)
V'l-
tR'
WO to W7/
VOH100 to 107 (Outputl VOL - -
___Hj9.h.:~ _____ _
DATA OUT '1'
- - - tFRS
--
DATA OUT '2'
DATAOUT'N'
tFRH
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, sE, 510 pins in this cycle.
157
NEe
yPD482234,482235
Hyper Page Mode Read Cycle (Extended data output: ~D4822351
tAC
tRASP
RAS (Input)
tRP
VIHVIL-
tRCO
CAS (Input)
VIHVIl-
Address (Input)
VIHVil _
tHCAS
VIH-
WBNVE (Input) VIl-
tAA
WP
tAA
VIH-
DT/OE (Input) VIl-
WOtoW7/
VOH100 to 107 {Outputl VOL _ - - - - tFRS
DATA OUT 'N'
tFRH
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, SID pins in this cycle.
158
NEe
yPD482234,482235
Hyper Page Mode Read Cycle (WE controlled)
(Extended data output: JLPD482235 (Versions A, F and Ell
tRC
tRASP
RAS (Input)
tRP
V'HV'L-
tRCO
tHCAS
V'H-
CAS (Input) V,L-
Address (Input)
V'HV,L _
WB/WE (Input) V,H VIL -
I....A"-L-+'P
V,H _ --T-++-v-.r"C:~"T"'\ 1---+---\
DT/DE (Input) V,L-
WO to W7/
VOH 100 to 107 (Outputl VOL - • • • • •
tFRS
Hinh Z
• ••• ~ .-•••••• -
"--_ _ _..JI
tFRH
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, 510 pins in this cycle.
159
NEe
.uPD482234, 482235
Hyper Page Mode Read Cycle (OE controlled: Latched controll
(Extended data output: }lPD482235 (Version All
tRC
tRASP
RAS (Input)
tRP
V,,,VIL _
tHPC
tRCo
CAS (Input)
V,HV,L-
Address (Input)
V,HV,L _
WB/WE (Input)
V,HV,L-
tHPC
tCRP
tRSH
tHCAS
L-L-L-f,L.J
DT/OE (Input)
V,H _ -+-+!-..h""""'"T"'T"'\
V,L-
WO to W7/
VOH100 to I07 'Outpu\) VOL- ----tFRS
DATAOUT'N'
tFRH
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, 510 pins in this cycle.
160
NEe
yPD482234,482235
Hyper Page Mode Read Cycle (DE controlled: Non-Latched control)
(Extended data output: tLPD482235 (Versions F. Ell
tAe
tAP
tRASP
RAS (Input)
V,HV,L _
tHPC
tACO
tCAP
tASH
tHCAS
V'H-
CAS (Input) V,L _
Address (Input)
WBNJE (Input)
DT/OE (Input)
V,HV,L _
V,H V,L - L-/.~-+-rL..J
V,H _
V,L-
--Ir-Hf---.h-.-....-"
tRAG
WO to W7/
VOH 100 to 107 (Output! VOL - - - - - tFAS
Hi!J!h Z
-- - -
.: - - - - - --
DATA OUT 'N'
"--_-JI
tFAH
Remark Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE. 510 pins in this cycle.
161
NEe
yPD482234, 482235
Fast Page, Hyper Page Mode Early Write Cycle/Fast Page, Hyper Page Mode Early Block Write Cycle
tRASP
RAS (Input)
V,HV,L-
CAS (Input)
V'HV,L-
Address (Input)
V'HV,L-
WB/WE (Input)
V,HV,l-
tRP
VIII-
DT/OE (Input)
V'L-
WO 10 W7/
10010107 (Input)
V,HV,L-
DSF (Input)
V,HV'L-
~'"L-_~
Notes 1. tpc for the JlPD482234
tHPC for the JlPD482235
2. tCAS for the JlPD482234
tHCAS for the JlPD482235
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
162
NEe
yPD482234,482235
Fast Page, Hyper Page Mode Late Write Cycle/Fast Page, Hyper Page Mode Late Block Write Cycle
RAS (Input)
CAS (Input)
V,H -
VIl-
V,HAddress (Input)
WBNJE (Input)
DT/OE (Input)
WOtoW7/
100 to 107 (Input)
DSF (Input)
VIl-
V'H-
V,L-
V,H-
V'L-
V'H-
V,L-
V,H-
V,L-
Notes 1. tpc for the jlPD482234
tHPC for the jlPD482235
2. tCAS for the jlPD482234
tHCAS for the jlPD482235
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
163
NEe
gPD482234,482235
Fast Page Mode Read Modify Write Cycle IJlPD48223411
Fast Page Mode Read Modify Block Write Cycle IJlPD482234)
tRASP
RAS (Input)
tRP
V'H-
V'L-
tRCO
V,H CAS (Input)
V,L _
---1-+-----"
tCSH
I-------N------VI
tCAS
V,HAddress (Input)
WBNJE (Input)
DT/OE (Input)
WO{ (Output)
to
W7/
100
to
107
V'L-
VIII-
VIl-
V'H-
V'L-
-':jigtlL __ _
':;~~ =
tws
twH
VIII-
(Input)
DSF (Input)
V,L-
V,H-
V'L-
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
164
NEe
yPD482234,482235
Hyper Page Mode Read Modify Write Cycle (Extended data output: pPD48223511
Hyper Page Mode Read Modify Block Write Cycle (Extended data output: PPD482235)
tRP
tRASP
RAS (Input)
V,HVILtRSH
tRCD
CAS (Input)
tCSH
V'HV'L-
tliCAS
Address (Input)
V,HV,L-
WBNVE (Input)
V'HV,L-
DT/OE (Input)
V'HV'L-
worp~1
to
_Hig_h:~
VOHVOL-
W7/
100
tws
___
-
twH
to
107
(Input)
DSF (Input)
V,HV'L-
V'HV,L-
Remarks 1. When DSF is high level: Block write cycle
When DSF is low level : Write cycle
2. WPB: Write-per-bit
3. When block write cycle is selected, input the column selection data to DATA IN.
4. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
165
NEe
yPD482234,482235
Flash Write Cycle
tRC
tRAS
RAS (Input)
VIHVILtCRP
CAS (Input)
VIHVIL-
Address (Input)
VIHVIL-
WB/WE (Input)
VIHVIL-
DT/OE (Input)
VIHVIL-
WOto W71
100 to 107 (Input)
VIIIVIL-
tCHR
Vltl-
DSF (Input) VIL-
Remark Because the serial access port operates independently ofthe random access port, there is no need
to control the SC, SE, SID pins in this cycle.
166
NEe
yPD482234,482235
RAS Only Refresh Cycle
tRe
tRAS
RAS (Input)
V'HV,LteRP
CAS (Input)
V'HV'L-
Address (Input)
V'HV'L-
DT/OE (Input)
V,HV'L-
WO10 W7/
VOH1001010710UlpUl) VOL-
tRPe
----------- ---------------~q~~----------------------------------tFRS
DSF (Input)
V,HV,L-
Remarks 1. WB/WE: Don't care
2. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, 510 pins in this cycle.
167
NEe
,uPD482234,482235
CAS Before RAS Refresh Cycle (Optional Reset)
tRC
tRAS
tRP
RAS (Input) VII'VIltRPC
tCHR
CAS (Input) V'HV'L-
High-Z
WO to W7/ (Output) VOH - ___________________ _
100 to 107
VOLtFRS
SC (Input)
tFRII
---'R'-______________~
~,','= ____
Remarks 1. Address, WB/WE, DT/OE: Don't care
2. Because the serial access port operates independently of the random access port, there is no
need to control the SE, 510 pins in this cycle.
168
NEe
pPD482234,482235
CAS Before RAS Refresh Cycle (STOP Register Set)
tAe
tAP
tRAS
RAS (Input) V,HV'LtAPe
tesA
teHR
CAS (Input) V'HVIL-
tASA
Address (Input)
V'HV,L-
BOUNDARY CODE
twas
WBNVE (Input)
tWB"
V,HV'L-
High-Z
WO to W7/
VOH 100 to 107 (Output) VOL-
-----------------------tFAS
DSF (Input)
tRAH
tFRH
V,HV,L _
L-J'-<....L-.........'-<..-'
tSRS
SC (Input)
tSAH
~,~ =_ _ _ _---J
Remarks 1. DT/OE: Don't care
2. Because the serial access port operates independently of the random access port, there is no
need to control the SE, SIO pins in this cycle.
169
NEe
uPD482234,482235
CAS Before RAS Refresh Cycle (No Reset)
tAC
tRAS
RAS (Input)
tAP
V,HVILtAPC
tCSA
tCHA
CAS (Input) V'HV,L-
twas
WBNJE (Input)
WO to W7/
100 to 107
twaH
~,~ = L...L....L....t....L...L..L...J
VOII - __________________________H!g..h~~
___________ .. ________________________ •
(Outpull VOItillS
DSF (Input)
V,HV'L-
trlUl
L...L...L...I"-L-.L..L...J
Remarks 1. Address, DT/OE: Don't care
2. Because the serial acces~ort operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
170
NEe
pPD482234,482235
Hidden Refresh Cycle IILPD482234)
tRe
tRe
tRAS
tRAS
RAS (Input)
V'HVil _
CAS (Input)
V'HV,L-
Address (Input)
V,HVIl-
WB/WE (Input)
V'HVil _
DT/OE (Input)
V,HV,LtOFF
teAe
tOEZ
tOEA
High-Z
WO to W7!
VOH100 to 107 10utputi VOL-
-------------------tFRS
DSF (Input)
V,HV,L _
SC (Input)
V'HVIl-
DATA OUT
High-Z
tFRH
Remarks 1. When DSF is high level: Reset select
When DSF is low level : Reset select
= No Reset
= Optional Reset
2. Because the serial access port operates independently of the random access port, there is no
need to control the SE, SIO pins in this cycle.
171
NEe
yPD482234,482235
Hidden Refresh Cycle (Extended data output: PPD482235)
tRC
tRC
tRAS
tRAS
V'H-
RAS (Input) V,,-
tCRP
tRCD
tCHR
tRSH
tCPN
tHCAS
V'H-
CAS (Input) V,,-
tRAL
Address (Input)
Wii/wE (Input)
V'H-
V'L-
V,HV,L _
VIII-
"DT/OE (Input) V,LtRAG
tCAC
tOEZ
tOEA
High-Z
WI) 10 W7/
VOII lOll 10 107 (Output) VOL-
-------------------tFRS
tFRH
tHIS
DATA OUT
High-Z
----------
tFRH
VIII-
DSF (Input)
V,L-
V,H-
SC (Input) V,L _
Remarks 1. When DSF is high level: Reset select = No Reset
When DSF is low level : Reset select = Optional Reset
2. Because the serial access port operates independently of the random access port. there is no
need to control the SE. SIO pins in this cycle.
172
NEe
yPD482234,482235
Register Set Cycle (Early Write)
tRC
tRAS
RAS (In'put)
VIHVILtCSH
tRSH
tCAS. tHCAS No.. 1
tRCO
CAS (Input)
VIHVIL-
Address (Input)
VIHVIL-
VIH-
WBrNE (Input) VIL-
DT/OE (Input)
VIHVILtOH
WOto W7/
100 to 107 (Input)
VIHVILtFCH
DSF (Input)
VIHVIL _
Resister select
Notes 1. tCAS for the tLPD482234
tHCAS for the tLPD482235
2. Refresh address (RAS only refresh)
Remarks 1. When DSF is high level: Register select = Color Register Select
When DSF is low level : Register select = Write Mask Register Select
2. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SIO pins in this cycle.
173
NEe
gPD482234,482235
Register Set Cycle (Late Write)
tRC
tRP
tRAS
RAS (Input)
V'HV'LtCSH
tRCO
CAS (Input)
Address (Input)
tRSH
tCAS, tHCAS NolO 1
tCRP
tCPN
V'HV'L-
V,HV'L-
twp
V'HWB/'NE (Input) V,LtOEH
DT/DE (Input)
VIIIV,LtOH
tos
V,Hwoto W7/
100 to 107 (Input) V,L-
DATA IN
V,H-
DSF (Input) V,L _
Notes 1. tCAS for the JlPD482234
tHCAS for the IlPD482235
2. Refresh address (RAS only refresh)
Remarks 1. When DSF is high level: Register select = Color Register Select
When DSF is low level : Register select
=Write Mask Register Select
2. Because the serial access port operates independently of the random access port, there is no
need to control the SC, SE, SID pins in this cycle.
174
NEe
yPD482234,482235
Mask Register Set Cycle (New Mask Selection) (Versions F and E only)
tRC
tRAS
RAS (Input)
tRP
V'HV'LtCSH
CAS (Input)
V'HV'L-
Address (Input)
V,HV,L-
WBNJE (Input)
V'HV,L-
DT/OE (Input)
V,HV,L-
WO to W7/
VOH100 to 107 10utput) VOL-
------~q~~---------------------------
V,H-
DSF (Input) V,L _
Notes 1. tCAS for the 1LPD482234
tHCAS for the 1LPD482235
2. Refresh address (RAS only refresh)
Remark
Because the serial access port operates independently of the random access port, there is no need
to control the SC, SE, 510 pins in this cycle.
175
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yPD482234,482235
Read Data Transfer Cycle (SC Active)
tRC
tRAS
RAS (Input) V'H-
V'L-
CAS (Input)
V'HV'L-
Address (Input)
V'HV'L-
WBNl/E (Input)
V'HV'L-
DT/OE (Input)
V'HV'L-
WO to W7/
100 to 107 (Output)
__________
VOHVOL _
tFRS
DSF (Input)
SE (Input)
SC (Input)
__________ _
tFRH
~,',' =
V,HV,L _
L
~~------------------------~+-----------------------tscc
tSDD
tSDH
V".-
V,L-
VOH-
SIOO to SI07 10utput) VOL-
QSF (Output) VVOH -
OL-
Note tCAS for the JlPD482234
tHCAS for the JlPD482235
176
~~~:z
NEe
yPD482234,482235
Read Data Transfer Cycle (SC Inactive)
tRC
tRAS
RAS (Input) V,HV'l-
CAS (Input)
V,H V'l-
Address (Input)
V,HV,l-
WBNl/E (Input)
V,HV,l-
DT/OE (Input)
V'HV'l-
WO to W7/
100 to 107
VOH(Output) VOltFRS
tFRH
DSF (Input) V,HV,l-
tSOHR
SE (Input)
VII.V,l-
L
tOOD
tROO
tcoo
tSCl
SC (Input)
VII.V'l-
tSCH
Fixed at either a low or high level
tsCA
VOHSIOO to SI0710utputi VOl-
n-1
n
New data output start
OSF (Output) VOHVOl-
Note tCAS for the JlPD482234
tHCAS for the JlPD482235
177
NEe
gPD482234,482235
Read Data Transfer Cycle (Serial Write
~
Serial Read Switching)
tRC
tRAS
RAS (Input)
V'HV'L-
CAS (Input)
V'HV,L _
Address (Input)
V'HV,L-
WBNl/E (Input)
V'HV'L-
tRP
''---
DT/OE (Input) V'fIV'LWOtoW7
100 to 107 (Output)
VOH VOL-
DSF (Input)
V,HV'L-
SE (Input)
V'HV,L -
tSOHR
L
toOD
tROD
tssc
. tSCL
SC (Input)
tcao
tsCil
V,H V'L-
Fixed at either a low or high level
tSIZ
SIOO {
(Input)
High-Z
~,: =
-- ---- ------tSCA
to
SI07
(Output)
'0~: = -----------
----------------~i2~-~ - - - - - - - - - - - - - tpo
VOH-
OSF (Output) VOL-
Note
tCAS
for the
tHCAS
178
~PD482234
for the ~PD482235
tOOR
New data output start
NEe
yPD482234,482235
Split Read Data Transfer Cycle
tRe
tRAS
tRP
RAS (lnp'ut) V,HV,L-
CAS (Input)
V,HV,L-
Address (Input)
V,HV,L-
WBNJE (Input)
V,HV,L-
DT/OE (Input) V'HV,L-
WO to W7/
100 to 107
VOH-
(Output) VOL-
DSF (Input)
V,HV,L-
SE (Input)
V,HV,L-
L
tsOHR
tssc
tsce
SC (Input)
Note 2
V,HV'L-
(Input) VV'H -
IL-
QSF (Output) VVOHOL-
Notes 1. teAs for the IlPD482234
tHeAS for the IlPD482235
2. Do not perform the following two serial read/write during this period.
• Serial read/write of jump source address set to the STOP register of the data register which does
not perform the data transfer cycle.
• Serial read/write of last address of data register (Address 255 or 511)
• Data register serial read for the side to be involved in data transfer cycle (for version E only)
179
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yPD482234,482235
Write Data Transfer Cycle
tRC
tRAS
tRP
V,HRAS (Input)
V'L-
CAS (Input)
V'HV'L-
Address (Input)
V'HV'L-
WBNVE (Input)
V,HV,L-
DT/OE (Input)
V".V'L-
wo to W7!
100 to 107 (Input)
V,HV'L-
DSF (Input)
V'HV'L-
SE (Input)
V'HV'L-
L
tSOHR
tcoo
tROD
SC (Input)
V,HV,L _
SIOO
to (Input)
SI07
V,HV'L-
Fixed at either a low or high level
QSF (Output) VVOH OL- ________________~----------------------------------~~----------
Note
tCAS
for the JlPD482234
tHCAS
180
for the JlPD482235
NEe
pPD482234,482235
Write Data Transfer Cycle (Serial Read -) Serial Write Switching)
tRe
tRAS
RAS (Input)
tRP
V,HV'ltesH
tReD
CAS (Input)
V,HVIl-
Address (Input)
V'HVIl-
WBMJE (Input)
V,HVIl-
DT/OE (Input)
V,HV,l-
(Input)
V,HV,l-
DSF (Input)
V,HV'l-
SE (Input)
V'HV,l-
WO to W7/
100 to 107
tRSH
too, tHCAS Note
tePN
tSDHR
teao
tun/)
SC (Input) V,HV,l-
Fixed at either a law or high level
ISZII
(Input)
V,H -
• ________________Hlg_h:~ _____________ _
V,l-
tSRZ
SIOO{
to
SI07
(Output)
VOHVOl-
DATA OUT
----------~~~~----------
QSF (Output) VOHVOl-
Note tCAS for the ~PD482234
tHCAS for the
~PD482235
181
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yPD482234,482235
Split Write Data Transfer Cycle
tRC
tRAS
RAS (Input)
VII'V,l-
-
tCRP
CAS (Input)
VII'V'l-
tCSH
tncD
V'HV'l-
WB/WE (Input)
V'HV,"-
DT/OE (Input)
V'HV,"-
WO to W7/ (Input)
100 to 107
VII'V'"-
DSF (Input)
V'HV'"-
SE (Input)
V'HV'L-
SC (Input)
V'H-
(Input)
V'HV'L-
V'"-
:~: ,0,,,,,,, V~{
VOL-
QSF (Output) VVOH OL-
182
tRSH
tCAS tHCAS
tCPN
tRAH
Address (Input)
tRP
L
lAse
teAH
Not.,
NEe
yPD482234,482235
Notes 1. tCAS for the JlPD482234
tHCAS for the JlPD482235·
2. Do not perform the following two serial read/write during this period.
• Serial read/write of jump source address set to the STOP register of the data register which does
not perform the data transfer cycle.
• Serial read/write of last address of data register (Address 255 or 511)
• Data register serial read for the side to be involved in data transfer cycle (for version E only)
183
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yPD482234,482235
Serial Read Cycle
tSEE
SE (Input) V,HV'L-
tSEZ
tscc Not••
tscc Note'
tscc
SC (Input) V,HV,LtSCA
tsOH
SIOO
to (Output) ;/" - ____HiQ.h:Z_ - - - SI07
OL-
DATA OUT
OSF (Output) VVOH OL- ______________________________J
~-----------------------------------
Notes 1. Last address of data register (Address 255 or 511)
2. Starting address of data register newly read (address is specified in the data transfer cycle).
Remark Because the random access port operates independently ofthe serial access port, there is no need
----
-- --
to control the RAS, CAS, Address, WBfWE, OT/OE, WI/O. OSF pins in this cycle.
Serial Write Cycle
tSCH
SC (Input)
tscc Note 2
tscc Not.'
tscc
tSCL
tsc"
tSCL
tSCH
tSCL
V'HV,L _
SE (Input) V'HV'L-
SIOO
to (Input) VVOH 5107
OL-
tpo
OSF (Output) VVOH -
OL-
Notes 1. Last address of data register (Address 255 or 511)
2. Starting address of data register newly read (address is specified in the data transfer cycle).
Remark Because the random access port operates independently of the serial access port. there is no need
-- ----to control the RAS, CAS. Address, WBfWE. DT/OE. WI/O, OSF pins in this cycle.
184
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gPD482234,482235
5. Package Drawings
40 PIN PLASTIC SOJ (400 mil)
B
40
21
++------------------- + -------------------+
U
Cl
n-------r-----~r-===~~
p
N
~I
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum matorial condition.
ITEM
MILLIMETERS .
INCHES
B
26.29~8:j5
1.035~8:8?~
c
D
10.16
11.1B±D".2
0.400
0.440±g.00B
E
1.0B±0.15
0.043~8:88~
F
G
0.7
3.5±0.2
0.02B
0.13B±0.00B
H
2.4±0.2
0.094~8:88~
K
O.B MIN.
2.6
1.27(T.P.)
0.031 MIN.
0.102
0.050(T.P.)
M
0.40±0.10
0.016~8:88g
N
P
T
0.12
9.40±0.20
0.15
RO.B5
0.005
0.370±0.00B
0.006
RO.0?3
u
0.20~8:6~
0.00B~8:88~
a
P4QLE·400A·2
185
NEe
yPD482234,482235
44 PIN PLASTIC TSOP(ll) (400 mil)
44
23
detail of lead end
1-r-------------+---------------r
{~
w
NOTE
Each load centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
c..
MILLIMETERS
INCHES
....:..:.A=--.:.:=~:..:..::;=--~~:;.,-18.63 MAX.
0.734 MAX.
0.93 MAX.
0.037 MAX.
_8::-_.::..:.:.::.,::.::-::-::_--=-=-=-=-,--::::,::..::...._
0.8 iT.P.)
0.031 iT.P.)
C
D
0.32~8:8~
0.013±0.OO3
E
0.1 ±0.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1
0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400±0.004
0.8±0.2
0.031 ~8:88~
0 .025
0145+
.
-0.015
0.006±0.001
G
H
K
L
0.5±0.1
0.020~8:8g~
M
0.13
0.10
30 + 70
_3·
0.005
0.004
70
3 0 +_3·
N
P
S44G5-8(}'7JF4
186
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gPD482234,482235
6. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the JlPD482234, JlPD482235.
Types of Surface Mount Device
JlPD482234LE-xx
40-pin plastic SOJ (400 mil)
JlPD482235LE-xx
40-pin plastic SOJ (400 mil)
tLPD482234G5-xx
44-pin plastic TSOP (II) (400 mil)
JlPD482235G5-xx,
44-pin plastic TSOP (II) (400 mil)
7. Example of Stamping
Letter A in the fifth character position in a lot number signifies version A, letter F, version F, and letter E,
version E.
NEe
JAPAN
0482235
XXXXDXXXX
v
Lot number
187
Line Buffer
189
DATA SHEET
NEe/
MOS INTEGRATED CIRCUIT
,uPD485506
LINE BUFFER
5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
Description
The IlPD485506 is a high speed FIFO (First in First Out) ine buffer. Word organization can be changed either
5 048 words by 16 bits or 10 096 words by 8 bits.
Its CMOS static circuitry provides high speed access and low power consumption.
The .uPD485506 can be used for one line delay and time axis conversion in high speed facsimile machines
and digital copiers.
Moreover, the .uPD485506 can execute read and write operations independently on an asynchronous basis.
Thus the .uPD485506 is suitable as a buffer for data transfer between units with different transfer rates and
as a buffer for the synchronization of multiple input signals.
Features
• 5048 words by 16 bits (Word mode) /10096 words by 8 bits (Byte mode)
• Full static operation; data hold time = infinity
• Suitable for sampling one line of A3 size paper (16 dots/mm)
• Asynchronous read/write operations available
• Variable length delay bits; 21 to 5 048 bits or 10096 bits (Cycle time: 25 ns)
19 to 5 048 bits or 10096 bits (Cycle time: 27 ns)
• Power supply voltage Vee
= 5 V ± 10 %
• All input/output TTL compatible
• 3-state output
Ordering Information
Part Number
R/W Cycle Time
/lPD485506G5-25
25 ns
/lPD485506G5.27
27 ns Nota
Package
44-pin plastic TSOP
Quality Grade
(II)
Standard
(400 mil)
Note Write cycle time is 25 ns.
Please refer to "Quality grade on NEC Semiconductor Devices· (Document number IEI-1209) published by
NEe Corporation to know the specification of quality grade on the devices and its recommended applications.
The information In this document Is subject to change without notice.
1336A (Japan)
191
NEe
yPD485506
Pin Configuration (Marking side)
44-pin Plastic TSOP (III (400 mill
44
D'NO
DouTi
2
43
DIN 1
DOUT1
3
42
DIN2
DOUT3
4
41
D'N3
DouT4
5
40
DIN4
6
39
D,NS
7
38
D'N6
DOUT7
8
37
DIN7
OE
RE
9
10
36
.35
WE
GND
11
RSTR
12
DOUTO
DOUT5
a.-
DOUT6
RCK
13
1::
."
C
&
U1
U1
CI
34
en
33
RSTW
U1
32
WCK
Vee
Cl
Vee
14
31
DOUTS
15
30
D,NS
DOUT9
16
29
D'N9
DouTio
17
28
D'Nl0
DOUT11
18
27
DINI1
DOUT12
19
26
DIN12
DOUT13
20
25
D'NI3
DOUTI. ~
21
24
D,Nl.
DouTis
22
23
D'N1S
DINO to DIN1S
Data Inputs
DOUTO to DOUT1S : Data ,Outputs
192
MD
GND
WCK
Write Clock Input
RCK
WE
Read Clock Input
Write Enable Input
RE
OE
Read Enable Input
Output Enable Input
RSTW
RSTR
Reset Write Input
Reset Read Input
MD
Mode Set Input
Vee
GND
+5 V Power Supply
Ground
NEe
gPD485506
Block Diagram
- - - - - Vee
GND
r---::~--:--:-~-':-:---I--- RSTR
RSTW
WCK
WE
L,...---":=~~~':':"_-.LL---'-::~;::=':"':'=--.Y-- RCK
----+
t-----RE
D'NO
DouTo
DIN1
DOUTl
DIN2
D,N'
gc
Iii
:j:
U
DC
0
DIN4
DINS
~
=>
a.
-=
=>
'5
a.
gc
40384 bits
(5048 by8)
Memory Cell Array
DouT2
a
DouT3
'5
DouT4
=>
0
DouT5
U
B-
-=
D,NS
DouT6
DIN7
DouT7
D'N8
DouT8
D'N9
DouT9
DOUTlli
D'N'O
DIN11
~DC
D'N'2
'5
a.
Iii
40384 bits
(5048 by 8)
Memory Cell Array
.s
:j:
=>
DC
'5
a.
'5
0
D'N'3
~
0
DOUTlt
'5
DouT12
0
DOUTl3
u
B=>
D'N'4
DOUTl4
D'N'5
DOUTl5
MD
193
NEe
j.1PD485506
Pin Function
Pin
Pin
Number
23 - 30
37 - 44
D'NO
I
D'N1S
Pin
Name
I/O
Data
Input
In
Function
Write data input pins.
The data inputs are strobed by the rising edge of WCK at the end of a
cycle and the setup and hold times (tos, tOH) are defined at this point.
Out
Read data output pins.
The access time is regulated from the rising edge of RCK at the beginning
of a cycle and defined by tACo
Reset
Write
Input
In
Reset input pin for the initialization of the write address pointer.
The state of RSTW is strobed by the rising edge of WCK at the beginning
of a cycle and the setup and hold times (tRS, tRH) are defined.
RSTR
Reset
Read
Input
In
Reset input pin for the initialization of the read address pointer.
The state of RSTR is strobed by the rising edge of RCK at the beginning of
a cycle and the setup and hold times (tRS, tRH) are defined.
36
WE
Write
Enablo
Input
In
Write operation control signal input pin.
When WE is in tho disable mode (uH" level), the internal write operation is
inhibited ond tho write address pointer stops at the current position.
10
RE
Road
Enable
Input
In
Read oporation control signal input pin..
When RE is in the disable mode (uH" level), the internal read operation is
inhibited and the read address pointer stops at the current position. The
data outputs remain valid for that address.
9
OE
Output
Enable
Input
In
Output operation control signal input pin.
When OE is in the disable mode (UHU level). the data out is inhibited and
Data
Output
15 - 22
DOUTO
I
DouT1s
33
RSTW
12
1-8
194
Symbol
the output changes to high impedance. The internal read operation is
executed at that time and the read address pointer incremented in
synchronization with the read clock.
32
WCK
Write
Clock
Input
In
Write clock input pin.
When WE is enabled (UlU level), the write operation is executed in
synchronization with the write clock. The write address pointer is
incremented simultaneously.
13
RCK
Read
Clock
Input
In
Read clock input pin.
When RE is enabled (UlU level), the read operation is executed in synchronization with the read clock. The read address pointer is incremented
simultaneously.
35
MD
Mode
Set
Input
In
Mode set input pin.
The level of MD gives the operation mode. When MD is in ululevel,
5048 words by 16 bits configuration with D'NO - D,N'5, DOUTO - DouT15 is
enabled. When MD is in UH" level, 10096 words by 8 bits configuration
with D'NO - D'N7, DOUTO - DOUT7 is enabled.
NEe
flPD485506
Operation Mode
(1) Mode Set Cycle (5 048 words by 16 bits or 10096 words by 8 bits organization)
.uPD485506 has a capability of selecting from two operation modes by judging the MD level when RSTW
or RSTR is enabled in the reset cycle.
MD Level
Bit Configuration
"L"
5 048 words by 16 bits
"H"
Caution
Control Signal
Data Inputs/Outputs
WCK, WE, RSTW
DINO - DIN"
10096 words by 8 bits
DouTo - DOUTl6
RCK,RE,RSTR
DINO· DIN1
WCK, WE, RSTW
DouTo - Dou11
RCK,RE, RSTR
Don't change the MD level during a reset cycle.
5 048 Words by 16 Bits FIFO
WCK
WE
RSTW
5048 Words
by
16 Bits
DINO - DIN15
RCK
RE
RSTR
DouTO - DouT15
OE
10096 Words by 8 Bits FIFO
WCK
DINO - DIN'
10096 Words by 8 Bits
DOUTO - DOUT7
Remark Fix DINS - DIN15 to "L" or "H" level in the 10096 words by 8 bits mode.
195
NEe
,uPD485506
(2) Write Cycle
When the WE input is enabled I"L" level), a write cycle is executed in synchronization with the WCK clock
input.
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after
a one-line 15048 bits or 10096 bits) delay and write data can be processed with the same clock.
When creating a variable length delay line by controlling WE or RSTW, delay bits are as follows.
Part Number
Cycle Time
Delay Bits
IlPD485506-25
25 ns
21 to 5 048 bits/21 to 10 096 bits
Il PD485506-27
Unless inhibited by WE, the internal write address will automatically wrap around from 5047 to 0 and
begin incrementing again.
(3) Read Cycle
When the RE input is enabled ("L" level), a read cycle is executed in synchronization with the RCK clock
input. When the OE input is also enabled ("L" level) at that time, data is output at tACo
When creating a variable length delay line by controlling RE or RSTR, delay bits are as follows.
Part Number
Cyclo Time
Delay Bits
IlPD485506-25
25 ns
21 to 5 048 bits/21 to 10096 bits
IlPD485506-27
27 ns
19 to 5 048 bits/19 to 10 096 bits
When read and write cycles contend forthe same line for a time axis conversion, etc., the old data (previous
line) may be output for the last 21 bits in the case of 25 ns read cycle time, the last 19 bits in the case of
27 ns read cycle time.
Unless inhibited by RE, the internal read address will automatically wrap around from 5047 to 0 and begin
incrementing again.
(4) Write Reset Cycle/Read Reset Cycle
After power up, the IlPD485506 requires the initialization of internal circuits because the read and write
address pointers are not defined at that time.
It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK
and RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE, WE
or OE.
Caution
196
Write and read reset cycles can be executed asynchronously. However, 1/2 cycle and 500 ns is
required after a write cycle to read the data written In a cycle.
NEe
yPD485506
Electrical Specifications
• All voltages are referenced to GND.
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
V
Voltage on any pin relative to GND
Vr
_0.5 Nota to Vee + 0.5
Supply voltage
Vee
-0.5 to +7.0
V
Output current
10
20
mA
Power dissipation
Po
1
W
Operating temperature
Topt
o to +70
'C
Storage temperature
Tstg
-55 to +125
'C
= 10 ns)
Note -3.0 V MIN. (Pulse width
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Condition
Symbol
MIN.
TYP.
MAX.
Unit
4.5
5.0
5.5
V
2.4
Vee + 0.5
V
-o.3 Note
+0.8
V
70
'C
MAX.
Unit
140
mA
Supply voltage
Vee
High level input voltage
V,H
Low level input voltage
V,l
Ambient temperature
T.
0
Note -3.0 V MIN. (Pulse width
= 10 ns)
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Input leakage current
Output leakage current
Symbol
Test Condition
TYP.
Icc
"
10
V, = 0 to Vee. Other Input 0 V
-10
+10
p.A
Vo = 0 to Vee.
Dour: High Impedance
-10
+10
p.A
2.4
0.4
V
High level output voltage
VOH
10H = -1 mA
Low level output voltage
VOL
10l = 2 mA
Capacitance (T.
MIN.
V
= +25 'C, f = 1 MHz)
Parameter
Symbol
Test Condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C,
10
pF
Output capacitance
Co
10
pF
197
NEe·
J..LPD485506
AC Characteristics (Recommended Operating Conditions unless otherwise notedlNotes1, 2, 3
Paramoter
Write clock cycle time
198
/LPD485506-25
/LPD485506-27
MIN.
MIN.
Symbol
MAX.
MAX.
Unit
Notes
tWCK
25
25
ns
Write clock pulse width
twcw
9
9
ns
Write clock precharge time
twcp
9
9
ns
Read clock cycle time
tRCK
25
27
ns
Read clock pulse width
tRCW
9
9
ns
Read clock precharge time
tRCP
9
9
ns
Access time
tAC
Output hold time
tOH
5
Output low-impedance time
tLZ
5
18
5·
18
ns
4
Output high-impedance time
tHZ
5
18
5
18
ns
4
Input data setup time
tos
7
Input data hold time
toH
MD Sot setup timo
tMS
MD Sot hold time
tMH
MD Sot time
tMo
Output low·impedance time (Mode change)
tLZM
5
18
5
Output high·impedance time (Mode change)
tHZM
5
18
5
RSTW/RSTR Setup time
tRS
7
RSTW/RSTR Hold time
tn.l
RSTW/RSTR Deselected time (1)
tnrn
18
18
ns
ns
5
7
ns
3
3
ns
20
20
ns
10
10
ns
0
0
ns
5
18
ns
4
18
ns
4
7
ns
6
3
3
ns
6
3
3
ns
7
RSTW/RSTR Deselected timo (2)
tn"2
7
7
ns
7
WE Setup time
twrG
7
7
ns
8
WE Hold time
twrll
3
3
ns
8
WE Deselected time (1)
tw,,"
3
3
ns
9
WE Doselected time (2)
tWEN2
7
7
ns
9
RE Setup time
tRES
7
7
ns
10
RE Hold time
tREH
3
3
ns
10
RE Deselected time (1)
tREN'
3
3
ns
11
RE Deselected time (2)
tREN2
7
7
ns
11
OE Setup time
tOES
7
7
ns
10
OE Hold time
tOEH
3
3
ns
10
OE Deselected time (1)
tOEN'
3
3
ns
11
11
OE Deselected time (2)
tOEN2
7
7
ns
WE Disable time
twEw
0
0
ms
RE Disable time
tREW
0
0
ms
OE Disable time
tOEW
0
0
ms
'Write reset time
tRSlW
0
0
ms
Read reset time
tRSTR
0
0
Transition time
tT
3
35
3
ms
35
ns
NEe
yPD485506
= 5 ns.
2. AC Characteristics test condition
Notes 1. AC measurements assume tT
Input Timing Specification
-fA
'f\~:
3.0V _ _ _ _
oV
r
., I
tr
:
II:
: ..
=5 ns
I_
tr = 5 ns
Output Timing Specification
High.Z
2.0V
High-Z
O.8V
Output Loads for Timing
- .......-Vcc
-
1.8kn
Dour
.......-Vcc
1.8kn
Dour
1.1 kn
1.1 kn
(tLZ,tHZ\
3. Input timing reference levels = 1.5 V.
4. tLZ, tHZ, tLZM and tHZM are measured at ±200 mV from the steady state voltage. Under any conditions,
tLZ ~ tHZ and tLZM ~ tHZM.
5. Mode set signal (MO) must be input synchronously with write reset signal (tRSTW period) or read
reset signal (tRSTR period). Under this condition, tRSTW =tMO (tRSTR =tMO).
6. If either tRS or tRH is less than the specified value, reset operations are not guaranteed.
7. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding
or following the period of reset operations.
S. If either twES or twEH is less than the specified value, write disable operations are not guaranteed.
9. If either twEN1 or twEN2 is less than the specified value, internal write disable operations may extend
to cycles preceding or following the period of write disable operations.
10. If either tRES or tREH, tOES or tOEH is less than the specified value, read disable operations are not
guaranteed.
11. If either tREN1 or tREN2, tOEN1 or tOEN2 is less than the specified value, internal read disable operations
may extend to cycles preceding or following the period of read disable operations.
199
NEe
,uPD485506
Write Cycle
Cycle n
I Cycle n+ 1 I Cycle n+2 I
I Cycle n+3 I
Disable Cycle
twCK
twcP
WCK (Input)
WE (Input)
DIN (Input)
Remark RSTW = "H" level
Read Cycle IRE Control)
[CYclo-;;-J ICycle n+ 1 I
rcycTo"" 21
C
Disable Cycle
I Cycle n+31
tncK
nCK (Input)
fiE (Input)
DOl" (Outpul)
Remark OE
_ _ _---J>
= "L"
level. RSTR
= "H"
level
Read Cycle IOE Control)
Cycle n
I Cycle n+ 1 I Cycle n+2
1
Disable Cycle
1
I
Cyclem
tRCK
tRCP
RCK (Input)
IOEH
IOEN2
lAc
OE (input)
III
Dour (Output)
200
. J-!.i9!':L .....
Remark RE = "L" level. RSTR = "W level
III
... ··n· .~!~~:~ ....... .
NEe
,uPD485506
Write Reset Cycle (WE Controlled 11
cleO
Reset C cle
WCK(lnput)
tRS
tRN1
tRH
tRSTWNote
tRN2
RSTW(lnput)
WE (Input)
"L" Level
~~~~----------+-------------+-------------~-------------+
DIN (Input)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
Write Reset Cycle (WE Controlled 21
Disable
cle
WCK (Input)
tRN1
tRS
!wEN1
twes
tRSlW Nota
tRH
tRN2
tweH
tweN2
RSTW (Input)
WE (Input)
twew
DIN (Input)
Note In write reset cycle, reset operation is executed even without a reset cycie (tRsTWI.
WCK can be input any number of times in a reset cycle.
201
NEe
JIPD485506
Read Reset Cycle IRE Controlled 11
RCK (Input)
tAN1
tRS
tRSTRNoto
tRH
tRN2
RSTR (Input)
RE (Input)
DOUT (Output)
Note In read reset cycle, reset operation is executed even without a reset cycle {tRsTRI.
RCK can be input any number of times in a reset cycle.
Remark OE
~
"L" level
Read Reset Cycle IRE Controlled 21
RCK (Input)
tANl
tns
tREN1
tRES
tRSTR Nolo
tRH
tRN2
tREH
tREN2
RSTR (Input)
RE (Input)
tREW
DOUT (Output)
Indefinite Data
Note In read reset cycle, reset operation is executed even without a reset cycle {tRsTRI.
RCK can be input any number of times in a reset cycle.
Remark OE
202
~
"L" level
NEe
,uPD485506
Application
• 1 H Delay Line
.uPD485506 easily allows a 1 H (5048 bits/10 096 bits) delay line (see Figure 1, 2 below).
It is also possible to change the number of delay bits depending on the cycle time as follows.
Part Number
Cycle Time
Delay Bits
.uPD485506-25
.uPD485506-27
25 ns
21 to 5 048 bits/21 to 10 096 bits
27 ns
19 to 5 048 bits/19 to 10 096 bits
To change the number of delay bits, you can choose the one of the following methods.
Adjustments of the number of delay bits
(1) Reset the cycle proportionate to the delay length (Figure 3).
(2) Shift the input timing of write reset (RSTW) and read reset signals (RSTR) according to the delay length
(Figure 4).
(3) Shift the address by disabling WE or RE for the period proportionate to the delay length (Figure 5).
Caution
After power up, the pPD485506 requires the initialization of internal circuits because the read
and write address pointers are not defined at that time.
Fig. 1 1 H Delay Line Circuit
40 MHz Clock
Data Input
Reset
WCK
RCK
DIN
Dour
8/16
Data Output
8/16
WE
RE
RSTW
RSTR
203
NEe
,uPD485506
Fig. 2 1 H Delay Line Timing
1-------- 1 H
(5 048 Cycles)
tWCK
tRCK
I Cycle 0 I I Cycle 1 I I Cycle 2
I
_ _ _ _ _ _-+-_____ 2 H
(5 048 Cycles)
ICycle50471Icx?e5048llc~le5049IIQ1Cle5050IICyCle50511
.10)
.. 111
.. (2)
. ....(3u.')_--'.
WCK/RCK
(Input)
RSlWl
RS'ffi
(Input)
DIN
(Input)
L.K...lLlL.l'-¥..lfI'\.-...JIY...lf
Remark RE, WE, OE
= "L"
level
Fig. 3 n-Bit De.lay Line Timing (1)
1H
2H
- - - - - - - o f - - - - - - ( n Cycles)
II
I
I---twc
- K- - - - (n Cycles;
tRCK
I Cycle 0
II
Cycle 1
WCK/RCK
(Input)
RSlWl
RSTR
(Input)
DIN
(Input)
L.K.........K-1I...lL.,,'-_II ...~
Remark RE, WE, OE
204
= "L"
level
Cycle 2
I Cycle (n-l) I
I. eX10 Iclon
II Cv?en+lll Qlclen+211 CYClen+31
. . 11 )
.. 12)
. wl""3')L-.....J.
NEe
,uPD485506
Fig. 4 n-Bit Delay Line Timing (2)
twc.
tRC.
I Cycle 0 I I Cycle 1 I
I
Cycle 2
I
II
II
ICycle n-lll Cxclen
C~len+l
Cxclen +2 11 cyclen+31
. 10 I
. . !1 I
. . 121
. 11>!.3'11......---J.
W.
WCK/RCK
(Input)
RSTW
(Input)
RSTR
(lnputl
DIN
(Input)
Remark RE. WE. DE = "L" level
Fig. 5 n-Bit Delay Line Timing (3)
twc.
tAC.
I Cycle 0 I I Cycle 1 I I Cycle 2
I
WCK/RCK
(Input)
RSTWI
RSTR
(Input)
RE
(Input)
DIN
(Input)
Remark WE. DE = "L" level
205
NEe
yPD485506
Fig. 6 Mode Set Cycle (Write) (1)
Reset C cle
tMS
tMO
tMH
tRS
tRSlW
tRH
MD
(Input)
RSTW
(Input)
tAN'
WCK
(Input)
tos
D,NO- D'N'
(Input)
D'N' - D'N15
rx...,...,,..1;::::::±::=:j
(Input)
Romark WE
= "L"
level
Fig. 7 Mode Set Cycle (Write) (2)
Reset C cle
IMs
tMO
tRS
tRSlW
MD
(Input)
RSTW
(Input)
tAN.
WCK
(Input)
D'NO- D'N'
(Input)
D'N8- D'N"
(Input)
Remark WE
206
= "L"
level
IRH
tOH
NEe
,uPD485506
Fig. 8 Mode Set Cycle IRead) 111
ResetC Ie
tMD
tMH
MD
(Input)
RSTR
(Input)
tRSTn
tRH
RCK
(Input)
DOUT. - DOUT7
(Output)
DOUTio~~~~~~ --:-::--i,I\.7\lO\J---:-:--;iI'iA~ ....U••..••••..•••••••••••••••~I~(~:-~••••••••••••••••••••••••••••.
Remark RE, DE
= "L"
level
Fig. 9 Mode Set Cycle (Rend I 12)
MD
(Input)
RSTR
(Input)
RCK
(Input)
DOUT. - DOUT7
(Output) _ _ _JI
DOUTa - Doun.
(Output)
Remark RE, DE
= uL" level
207
NEe
,uPD485506
Package Drawing
44 PIN PLASTIC TSOP(m (400 mill
23
detail of lead end
;-r-------------+---------------r
LLI
l~
o
N
S44G5-80-7JF1-l
NOTE
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
208
ITEM
MILLIMETERS
INCHES
A
18.81 MAX.
0.741 MAX.
B
1.0 MAX.
0.040 MAX.
C
0.8 (T.P.)
0.031 (T.P.)
D
0.30±0.10
0.012~g:gg~·
E
0.05±0.05
0.002±0.002
F
1.1 MAX.
0.044 MAX.
G
0.97
0.038
H
11.76±0.2
0.463±0.008
I
10.16±0.1
0.400±0.004
J
0.8±0.2
O. 031 ~g:gg~
K
0.125~g:6~
O. 005~g:gg~
L
0.5±0.1
0.020~g:gg~
M
0.13
0.005
N
0.10
0.004
NEe
,uPD485506
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the pPD485506.
Type of Surface Mount Device
JlPD485506G: 44·pin Plastic TSOP (II) (400 mill
209
NEe
[MEMO]
210
,uPD485506
DATA SHEET
MOS INTEGRATED CIRCUIT
jlPD485505
~~:>.
Yr.;:> ~(
LINE BUFFER
5K-WORD BY 8-BIT
U~L.~)
Description
; 1;11 /ri1-f I(Iff. '~ C);,,"£7:J/J
The ,uPD485505 is a 5048 words by 8 bits high speed FIFO (First In First Out) line buffer. !isci'(cfS'static
circuitry provides high speed access and low power consumption.
The tLPD485505 can be used for one line delay and time axis conversion In high speed facsimile machines
and digital copiers.
Moreover, the ,uPD485505 can execute read and write operations independently on an asynchronol,ls basis.
Thus the ,uPD485505 is suitable as a buffer for data transfer between units with different transfer rates and
as a buffer for the synchronization of multiple input signals.
Features
•
•
•
•
•
5 048 words by 8 bits
Full static operation; data hold time = infinity
Suitable for sampling one line of A3 size paper (16 dots/mm)
Asynchronous read/write operations available
Variable length delay bits; 21 to 5048 bits (Cycle time: 25 ns)
19 to 5048 bits (Cycle time: 27 ns)
• Power supply voltage Vee = 5 V ± 10 %
• All input/output TTL compatible
• 3-state output
Ordering Information
Part Number
R/W Cycle Time
pPD485505G-25
25 ns
pPD485505G-27
27 ns Note
Package
24-pin plastic SOP
Quality Grade
Standard
(450 mill
Note Write cycle time is 25 ns.
Please refer to "Quality grade on NEC Semiconductor Devices· (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
IC·3340A (Japan)
211
NEe
yPD485505
Pin Configuration (Marking side)
24-pin Plastic SOP (450 mil)
('
'"
DINO
DOUTO
DouTI
2·
DOUT2
3
4
D0UT3
RE
RSTR
5
GND
7
6
RCK
8
9
10
11
12
D0UT4
DouTS
D0UT6
DouT1
DINO - DIN7
DIN.
~
~
I
22
DIN2
21
20
19
18
WE
RSTW
Vee
17
WCK
16
DIN4
15
DIN5
14
DIN6
13
DIN?
DIN3
Data Inputs
DouTo - DouT7 : Data Outputs
WCK
212
Write Clock Input
RCK
Read Clock Input
WE
Write Enable Input
RE
Read Enable Input
RSTW
Reset Write Input
RSTR
Reset Read Input
Vee
+5 V Power Supply
GND
Ground
NEe
,uPD485505
Block Diagram
---Vee
---GNO
WCK
Write Address Pointer
1 - - - - - - RSTW
,----RE
D'NO
OOUTO
DIN 1
OOUTI
0'N2
D'N3
D,N.
OOU12
403B4 bits
(5 04B by B)
OOUT3
Memory Cell Array
Dour.
D'N5
Oours
0'N6
00ur6
0'N7
OOUT7
WE---'
RSTR - - - - - + 1
Read Address Pointer
RCK
213
NEe
,uPD485505
Pin Function
Pin
Symbol
Pin
Name
I/O
13 - 16
D'NO
I
Data
Input
In
21 - 24
D,N'
1-4
Data
Output
9 - 12
DouTo
I
DouT7
19
RSTW
6
Pin
Number
214
Function
Write data input pins.
The data inputs are strobed by the rising edge of WCK at the end of a
cycle and the setup and hold times (tos, tOH) are defined at this point.
Out
Read data output pins.
The access t'ime is regulated from the rising edge of RCK at the beginning
of a cycle and defined by tACo
Reset
Write
Input
In
Reset input pin for the initialization of the write address pointer.
The state of RSTW is strobed by the rising edge of WCK at the beginning
of a cycle and the setup and hold times (tRS, tRH) are defined.
RSTR
Reset
Read
Input
In
Reset input pin for the initialization of the read address pointer.
The state of RSTR is strobed by the rising edge of RCK at the beginning of
a cycle and the setup and hold times (tRS, tRH) are defined.
20
WE
Write
Enable
Input
In
Write operation control signal input pin.
When WE is in the disable mode ("H" level), the internal write operation is
inhibited and the write address pointer stops at the current position.
5
RE
Read
Enable
Input
In
Read operation control signal input pin.
When RE is in the disable mode ("H" level), the internal read operation is
inhibited and the read-address pointer stops at the current position. The
output changes to high impedance.
17
WCK
Write
Clock
Input
In
Write clock input pin.
When WE is enabled ("L" level), the write operation is executed in
synchronization with the write clock. The write address pointer is
incremented simultaneously.
8
RCK
Read
Clock
Input
In
Read clock input pin.
When RE is enabled ("L" level), the read operation is executed in synchronization with the read clock. The read address pointer is incremented
simultaneously.
NEe
yPD485505
Operation Mode
(1) Write Cycle
When the WE input is enabled ("L" level), a write cycle is executed in synchronization with the WCK clock
input.
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after
a one-line (5 048 bits) delay and write data can be processed with the same clock.
When creating a variable length delay line by controlling WE or RSTW, delay bits are as follows.
Part Number
Cycle Time
Delay Bits
.uPD485505-25
25 ns
21 to 5 048 bits
.uPD485505-27
Unless inhibited by WE, the internal write address will automatically wrap around from 5047 to 0 and
begin incrementing again.
(2) Read Cycle
When the RE input is enabled ("L" level), a read cycle is executed in synchronization with the RCK clock
input and data is output at tACo
When creating a variable length delay line by controlling RE or RSTR, delay bits are as follows.
Part Number
Cycle Time
Delay Bits
.uPD485505-25
25 ns
21 to 5 048 bits
.uPD485505-27
27 ns
19 to 5 048 bits
When read and write cycles contend forthe same line for a time axis conversion, etc., the old data (previous
line) may be output for the last 21 bits in the case of 25 ns read cycle time, the last 1.9 bits in the case of
27 ns read cycle time.
Unless inhibited by RE, the internal read address will automatically wrap around from 5047 to 0 and begin
incrementing again.
(3) Write Reset Cycle/Read Reset Cycle
After power up, the ~PD485505 requires the initialization of internal circuits because the read and write
address pointers are not defined at that time.
It is necessary to satisfy setup requirements and hO.ld times as measured from the rising edge of WCK
and RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE or
WE.
Caution
Write and read reset cycles can be executed asynchronously. However, 1/2 cycle and 500 ns is
required after a write cycle to read the data written in a cycle.
215
NEe
,uPD485505
o
Electrical Specifications
• All voltages are referenced to GND.
Absolute Maximum Ratings
Rating
Unit
Voltage on any pin relative to GND
Parameter
Symbol
VT
Condition
_0.5 Note to Vee + 0.5
V
Supply voltage
Vee
-0.5 to +7.0
V
Output current
10
20
mA
Operating temperature
Topt
o to +70
'C
Storage temperature
Tstg
-55 to +125
'C
Note -3.0 V MIN. !Pulse width
Caution
= 10 ns)
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN.
TYP.
MAX.
Unit
Supply voltage
Vee
4.5
5.0
5.5
V
Hig h level input voltago
V,H
2.4
Vee + 0.5
V
Low level input voltage
V,L
-O.3 Note
+0.8
V
Ambient temperature
T.
0
70
'C
MAX.
Unit
Parameter
f---
Symbol
Condition
Note -3.0 V MIN. (Pulse width = 10 ns)
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Test Condition
Symbol
MIN.
TYP.
Operating current
Icc
80
mA
Input leakage current
II
V, = 0 to Vee. Other Input 0 V
-10
+10
pA
Output leakage current
10
Va
-10
+10
pA
0.4
V
c
0 to Vee.
DouT: High Impedance
High level output voltage
VOH
IOH = -1 mA
Low level output voltage
VOL
IOL=2mA
Capacitance (T.
V
=+25 'C, f =1 MHz)
Parameter
216
2.4
Symbol
Test Condition
MAX.
Unit
Input capacitance
C,
MIN.
TYP.
10
pF
Output capacitance
Co
10
pF
NEe
flPD485505
AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3
,uPD485505-25
Parameter
Symbol
MIN.
MAX.
/lPD485505-27
MIN.
MAX.
Unit
Write clock cycle time
twCK
25
25
ns
Write clock pulse width
twcw
9
9
ns
Write clock precharge time
twcp
9
9
ns
Read clock cycle time
tRCK
25
27
ns
Read clock pulse width
tRCW
9
9
ns
Read clock precharge time
tRCP
9
9
ns
Access time
tAC
Output hold time
tOH
5
Output low-impedance time
tLZ
5
18
18
18
Output high-impedance time
tHZ
5
Input data setup time
tos
7
18
5
Notes
ns
ns
5
18
ns
4
5
18
ns
4
7
ns
Input data hold time
tOH
3
3
ns
RSTW/RSTR Setup time
tRS
7
7
ns
5
5
RSTW/RSTR Hold time
tRH
3
3
ns
RSTW/RSTR Deselected time (1)
tRN1
3
3
ns
6
RSTW/RSTR Deselected time (2)
tAN'
7
7
ns
6
WE Setup time
twES
7
7
ns
7
WE Hold time
twEH
3
3
ns
7
WE Deselected time (1)
twEN1
3
3
ns
8
WE Deselected time (2)
twEN'
7
7
ns
8
RE Setup time
tRES
7
7
ns
9
RE Hold time
tREH
3
3
ns
9
RE Deselected time (1)
t~EN1
3
3
ns
10
10
RE Deselected time (2)
tREN'
7
7
ns
WE Disable time
tWEW
0
0
ms
RE Disable time
tREW
0
0
ms
Write reset time
tRSTW
0
0
ms
Read reset time
tASTR
0
Transition time
tT
3
0
35
3
ms·
35
ns
217
NEe
.uPD485505
Notes 1. AC measurements assume tT = 5 ns.
2. AC Characteristics test condition
Input Timing Specification
.
,
,
.,,
,.
,
tT = 5 ns
tT
= 5 ns
Output Timing Specification
High-Z
High-Z
Output Loads for Timing
-
-
.......-Vcc
1.8kO
1.8kO
Dour
Dour
1.1 kO
(tAc. IOHI
3.
4.
5.
6.
......-Vcc
f
1.1 kO
PF
(Ill. 1HZ)
Input timing reference levels = 1.5 V.
tLZ and tHZ are measured at ±200 mV from the steady state voltage. Under any conditions, tLZ ~ tHZ.
If either tRS or tRH is less than the specified value, reset operations are not guaranteed.
If either tRNl or tRN2 is less than the specified value, reset operations may extend to cycles preceding
or following the period of reset operations.
7. If either tWES or twEH is less than the specified value, write disable operations are not guaranteed.
8. If either tWENl or twEN2 is less than the specified value, internal write disable operations may extend
to cycles preceding or following the period of write disable operations.
9. If either tRES or tREH is less than the specified value, read disable operations are not guaranteed.
10. If either tRENl or tREN2 is less than the specified value, internal read disable operations may extend
to cycles preceding or following the period of read disable operations.
218
NEe
,uPD485505
Write Cycle
Cycle n
I Cycle n+1
I Cycle n+2 I
Disable Cycle
I Cycle n+3 I
twcP
WCK (Input)
WE (Input)
DIN
(Input)
Remark RSTW
= "H"
level
Read Cycle
[
Cycle n
I Cycle n+ 1 I Cycle n+2 I
Disable Cycle
I Cycle n+3 I
tRCK
RCK (Input)
tAc
RE (Input)
. tLZ
DOUT
_. _. -?t .~~~~.!..-- .....
(Output)
Remark
RSTR
= "H"
level
219
NEe
,uPD485505
Write Reset Cycle (WE Controlled 11
Reset C de
C deO
WCK(lnput)
tRS
tRSTWNote
tRH
tRN2
RSTW (Input)
WE (Input)
"L" Level
------------------+-------------+-------------~------------_r
DIN (Input)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSlW).
WCK can be input any number of times in a reset cycle.
Write Reset Cycle (WE Controlled 21
Disable C cle
WCK (Input)
tRNI
tRS
tweNI
tW[S
tnsTWNolo
tRH
tRN2
twEil
twEN2
RSTW (Input)
WE (Input)
twEW
DIN (Input)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSlW).
WCK can be input any number of times in a reset cycle.
220
NEe
,uPD485505
Read Reset Cycle (RE Controlled 1)
RCK (Input)
tRN'
tRS
tRSTR Nota
tRH
tRN'
RSTR (Input)
RE (Input)
Dour (Output)
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
Read Reset Cycle (RE Controlled 2)
RCK (Input)
tRN'
tRS
tREN'
tRES
tRSTR Not.
tRH
tRN'
tREH
tREN2
RSTR (Input)
RE (Input)
tREW
tAG
Dour (Output)
------------~!~~:-~------------
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
221
NEe
,uPD485505
Application
• 1 H Delay Line
JlPD485505 easily allows a 1 H (5048 bits) delay line (see Figure 1, 2 below).
It is also possible to change the number of delay bits depending on the cycle time as follows.
Part Number
Cycle Time
Delay Bits
pPD485505-25
25 ns
21 to 5 048 bits
pPD485505-27
27 ns
19 to 5 048 bits
To change the number of delay bits, you can choose the one of the following methods.
Adjustments of the number of delay bits
(1) Reset the cycle proportionate to the delay length (Figure 3).
(2) Shift the input timing of write reset (RSTW) and read reset signals (RSTR) according to the delay length
(Figure 4).
(3) Shift the address by disabling WE or RE for the period proportionate to the delay length (Figure 5).
Caution
After power up, the jIPD485505 requires the initialization of internal circuits because the read
and write address pointers are not defined at that time.
Fig. 1 1 H Delay Line Circuit
40 MHz Clock
Reset
WCK
Data Input
-....,..,¥--------I DIN
8
222
RCK
Dour I-----+-....,..;~- Data Output
8
NEe
,uPD485505
Fig. 2 1 H Delay Line Timing
2H
(5 048 Cycles)
1H
twcK
(5 048 Cycles)
tRCK
I Cycle 0 I I Cycle 1 I I Cycle 2 1
ICycle 5 0471
WCK/RCK
(Input)
RSlWl
RSTR
(Input)
DIN
(Input) ~~.K..ll-lt.J/
Remark RE, WE = "L" level
Fig. 3 n-Bit Delay Line Timing (1)
tWCK
tACK
1H
(n Cycles)
2H
(n Cycles)
I Cycle 0 I I Cycle 1 1I Cycle 2 I
WCK/RCK
(Input)
RSlWl
RSTR
(Input)
DIN
(I nput) L..,lI;~X-lol-lt.J/
Remark RE, WE = "L" level
223
NEe
jlPD485505
Fig. 4 n-Bit Delay Line Timing (2)
tweK
tRCK
I Cycle 0 I I Cycle 1 I I Cycle 2 I
ICycie n-ll I Cycle n IICycie n+lllCycle n+21 ICycle n+31
WCK/RCK
(Input)
RSTW
(Input)
RSTR
tos
(Input)
DIN
(Input)
1
DOIH
(Output)
,-/\MI\MMI\MMMI\M.lL..lL.lo!...lL.lL..lL.lo!...lL.lL..lL.lo!...lLll..lLJL..lL.l£..ljLJL~11LlI'-¥..lL..lL.lo!...lL.lL..lL.lo!.JI
Remark RE. WE = "L" level
Fig. 5 n-Bit Delay Line Timing (3)
twCK
tRCK
I Cycle 0 I I Cyclo 1 I I Cycle 2 I
WCK/RCK
(Input)
RSTWI
RSTR
(Input)
RE
(Input)
DIN
(Input)
Remark WE = "L" level
224
I Cycle n-ll I Cycle n I ICycie n+ 11 ICycle n+21 ICycle n+31
NEe
,uPD485505
Package Drawing
24 PIN PLASTIC SOP (450 mil)
detail of lead end
o
o
ttl
+1
o
ttl
u..
~.
w~W
lD I$IM~I
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
B
P24GM-50-450A-2
ITEM
MILLIMETERS
INCHES
A
16.51 MAX.
0.650 MAX.
8
1.27 MAX.
0.050 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40±0.10
0.016~g:gg3
E
O.l~g:~
0.004~g:gg~
F
2.5 MAX.
0.099 MAX.
G
2.00
0.079
H
12.2±0.3
0.480~:ga
I
8.4
0.331
J
1.9
0.075
K
0.15~:~g
0.006~g:g~
0.035~:gg~
L
0.9±0.2
M
0.12
0.005
N
0.10
0.004
225
NEe
,uPD485505
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
Type of Surface Mount Device
~PD485505G:
226
24-pin Plastic SOP (450 mil)
~PD485505.
Field Buffer
227
DATA SHEET
MOS INTEGRATED CIRCUIT
,uPD42280
2 M-BIT FIELD BUFFER
The IlPD42280 is a high-speed field buffer equipped with a memory of 256K words x 8bit (262, 224 x 8bit)
configuration. The high-speed and the low power consumption are realized in CMOS dynamic circuit.
The IlPD42280 consists of FIFO (First In First Out) configuration, and the write/read operations are possible
asynchronously and simultaneously.
Because it has refresh circuit internally, 1 field delay line and time axis conversion etc. are realized easily.
Therefore it is suitable for YC separation between frames, interpolation between fields, reproduction of
freeze picture and frame synchronizer in the digital TV, VCR systems.
FEATURES
• 256K words x 8 bit FIFO configuration
•
•
•
•
•
•
Write/read operations are possible asynchronously and simultaneously
Reset is possible apart from write/read address (real time reset)
Serial read cycle time
30 ns(MIN.)
: 25 ns(MAX.)
Serial read access time
: 30 ns(MIN.)
Serial write cycle time
Self refresh function incorporated
• Output enable
• All I/O TIL compatible
• CMOS low power consumption: (tRCK, twCK
• 28 pin plastic SOP (450 mil)
• 28 pin plastic ZIP (400 mil)
= 30 ns)
100
= 50 rnA (TYP.)
IlPD42280GU
IlPD42280V
ORDERING INFORMATION
Part number
Package
Read cycle time Access time Write cycle time
(ns)
(ns)
(ns)
Quality level
pPD42280GU-30
28-pin plastic SOP (450 mil)
30
25
30
Standard
pPD42280V-30
28-pin plastic ZIP (400 mil)
30
25
30
Standard
Please refer to "Quality grade on NEC Semiconductor Devices' (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The Information in this document Is subJect to change without notice.
IC'2991 A (Japan)
229
I\)
w
o
5 Z
~
rn
~
n
»
G')
Refresh
timer
Write address pointer
rf1
WCK
RCK
WRST
RRST
WE
RE
OE
I
Write data register
~
.
..
Controller
.
..
f-----+-
&
Write
address
counter
Read
address
counter
Timing
generator
..
..
.
~
Refresh
address
counter
i
I
r----
U
rr
J
Write data register
»
s:
~
I~
(;
t)
Q)
0;
256Kx 8
Memory cell array
VI
VI
VI
,---.
-
~
-u
-u
Input
buffer
V
80 x8
SRAM buffer
«
r--
~
I
Read data register
I
I
I
::D
r----
T
I
I Write address pointer J
Read address pointer
1
I Read data register
I
I Read address pointer
.>
Output
buffer
000 to 007
VDD
x2
GNDx2
~
~
"'tJ
C
0l=Io
N
N
00
o
NEe
.uPD42280
PIN CONFIGURATION
28 PIN SOP (450 mil)
28 PIN ZIP (400 mil)
(Top View)
(Bottom View)
0
010
GNO
28
000
OE
2
011
2
27
001
000
4
012
3
26
002
002
6
013
4
25
003
010
8
WE
5
24
RE
012
10
GNO
6
23
GNO
WE
12
TEST
7
1::
"'1:1
C
WRST
8
WCK
9
~
I\)
I\)
00
0
22
OE
G'l
21
RRST
~
20
RCK
C
Voo
10
19
Voo
014
11
18
004
015
12
17
005
016
13
16
006
017
14
15
007
TEST
WCK
3
RE
5
001
7
003
9
011
11
013
13
GNO
15
WRST
17
Voo
19
015
21
017
23
005
25
007
27
RRST
Q)
14
C>
C
16
014
18
016
20
004
22
006
24
RCK
26
Voo
28
"0
U5
:.i2
«;
6
Pin name
DID to 017
Data input
Input
DOD to 007
Data output
Output
WCK
Write clock input
Input
RCK
Read clock input
Input
WE
Write enable input
Input
RE
Read enable input
Input
OE
Output enable input
Input
WRST
Write reset input
Input
RRST
Read reset input
Input
TEST
Test pin
Input
Voo
+5 V power source
GND
Ground
231
NEe
1.
PIN FUNCTION
Pin name
010 to 017
000 to 007
232
,uPD42280
Input/Output
Function
I
This is a write data input. Fetching data is executed on the back rise up edge of
WCK input cycle, and the setup/hold time (tos, tOH) are specified against the edge.
0
(3-state)
This is a read data output. The access time is specified from the front rise up edge
of RCK cycle and determined by tACo It is 3 state output.
WRST
I
This is a reset input for initializing a write address.
Fetching reset signals is executed on the front rise up edge of WCK input cycle,
and the setup/hold time (tRS, tRH) are specified against the edge.
RRST
I
This is a reset input for initializing a read address.
Fetching reset signals is executed on the front rise up edge of RCK input cycle,
and the setup/hold time (tRS, tRH) are specified against the edge.
WE
I
This is a write operation control input. In case of high level, the internal write
operation is prohibited, and the write address pointer is also stopped at the
present position. WE signal is fetched on the front rise up edge of WCK input cycle.
RE
I
This is a read operation control input. In case of high level, the internal read
operation is executed, and the read address pointer is stopped at the present
position. RE signal is fetched on the front rise up edge of RCK input cycle.
OE
I
This is a read dota control input. In case of high-level, 000 to 007 will be high
impodanco. In the read address pointer an increment is executed synchronously for RCK, not depending on the OE signal input level. OE signal is
fetchod on the front rise up edge of RCK input cycle.
WCK
I
This is a write clock input. The write operation is executed synchronously for
the write clock when WE is in low level, and in the write address pointer, the
increment is executed at the same time.
RCK
I
This is a read clock input, The read operation is done synchronously for the
read clock, and when RE is in low level, in the read address pointer the
increment is executed at the same time.
TEST
I
This is a pin for testing. It is to be fixed on low level on the practical operation.
NEe
2.
,uPD42280
EXPLANATION FOR THE MEMORY AND FUNCTION BLOCK
2.1
MEMORY CELL ARRAY
This is a memory cell array in this product consisting of dynamic memory cells, with 256K x 8 (2M bit)
configuration.
2.2 INPUT BUFFER
This is a buffer to input the signals of 010 to 017 to the write data register or SRAM buffer.
2.3
OUTPUT BUFFER
This is a buffer to output the data from the read data register or SRAM buffer to 000 to 017.
2.4 WRITE DATA REGISTER/WRITE ADDRESS POINTER
This is a register to temporarily store the data input to 010 to 017. The input data is stored in the address
directed by the write address pointer. In the write address pointer, its content increases every WCK input.
When the write data register is filled with data, the data are transferred to the memory cell array together,
and the write address pointer is reset to the 0 address. The data are transferred by 64 words unit.
2.5 READ DATA REGISTER/READ ADDRESS POINTER
This is a register to temporarily store the data transferred together from the memory cell array. The data
in the register directed by the read address pointer is output to 000 to 007. In the read address pointer,
its content increases every RCK input. When the read data register is emptied, the data read from the
memory cell array is transferred together to the register, and the read address pointer is reset to the 0
address. The data are transferred by 64 words unit.
2.6
SRAM
This is a buffer to store the data for 80 words after the write address is reset by WRST. Also, when a read
address is reset by the input of RRST signals, the data for 80 words after the reset is output (to 000 to 007)
from SRAM buffer.
2.7
WRITE ADDRESS COUNTER
This is a counter to direct the row address of the write data. When the data is transferred to memory cell
array from the write data register, the content of the counter increases. When input of the last address is
attained, the content of the counter is reset to the 0 address.
2.8
READ ADDRESS COUNTER
This is a counter to direct the row address of the read data. When the data is transferred to the read data
register from memory cell array, the content of the counter increases. When input of RRST signals or the
last address is attained, the content of the counter is reset to the 0 address.
2.9
REFRESH ADDRESS COUNTER/REFRESH TIMER
This is a counter to direct the refresh address. Its content is increased one by one by the refresh timer.
Because self refresh function is incorporated, the refresh operation is executed automatically.
2.10
ADDRESS SELECTOR
This is a selector which selects one ofthe addresses directed by the address counter, read address counter
and refresh address counter as the row address of memory cell array.
2.11
CONTROLLER/TIMING GENERATOR
Each block is controlled by the control signals from the input pins of this block.
233
NEe
3.
gPD42280
MEMORY OPERATION
3.1
WRITE OPERATION
When WE input is in low level, the data input to 010 to 017 is written into the write data register every
8 bits together synchronizing with WCK input.
The write data should be input to meet the setup time and the hold time for the back rise up edge ofWCK
input cycle.
When WE input is attained to a high level, the write operation is prohibited. The write address pointer
is stopped at the position of high level input state. When the low level is input again, the operation is started
from the stopped address.
Though the write operation is prohibited at any time, WE signal should be input to meet the set up time
and the hold time for the rise up edge of WCK.
3.2
READ OPERATION
When RE input and OE input are in low level, the data is output to 000 to 007 from the read data register
every 8 bits together synchronizing with RCK input.
The read data is output after access time (tAC) from the rise up edge of RCK input cycle.
When RE input is attained to a high level, the read address pointer is stopped at the position of the high
level input state. When inputting a low level again, the operation is started from the stopped address.
When OE input is attained to a high level, the output will be a high impedance. The content ofthe read
address pointer increases synchronously with RCK input, not depending on the input level of OE signal.
Thougil tile read operation can be prohibited at any time, RE signal/OE signal should be input to meet
the setup time and hold time for the rise up edge of RCK.
When the new data is read, the write address should be preceded 200 to 262, 223 or less cycles than the
read -_ _ _ Aeset
1..-.-_ _ _ _ _ _ _
n_n
f se: Color subcarrier frequency
Fig. 2
1 field delay line timing diagram
Field m + 1
Field m
o
2
n
0'
l'
2'
3'
WCK
ACK
WAST
AAST
DIO to DI7
DOOto D07
xXXXXXXXXXXXX:
2.0V
O.BV
Data of the Field m
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
245
NEe
,uPD42280
(2) The new data read
With connection as shown in Fig. 3 by ilJputting RRST 200 cycle after WRST, new data (the latest written
data) can be read. (See ·Fig.4)
Fig. 3 Circuit of new data read
4 fsc
WCK
OIOto
B
RCK
000
017
to 007
WE
RE
B
OE
WRST
RRST
Read
reset
Write
reset
f sc: Color subcarrier frequency
Fig. 4 The new data read timing diagram
o
2
WCK
RCK
199
200
201
202
203
2.4V
010 to 017
000 to 007
xxxxxxxxxxxxx:
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
246
2.0V
O.BV
NEe
.uPD42280
(31 Double speed conversion
By reading with double cycles for the write cycle. the double speed conversion can be done. Fig. 5 shows
an example circuit in which the data is written by 13.5 MHz and the data is read by 27 MHz. In this
example. the same field is read 2 times (Timing Fig. 6).
Caution
Note that when the read and the write compete each other in the same field like this
application. in the last 192 words. the data before 1 field may be output.
Fig. 5 Circuit of double speed conversion
13.5 MHz
27 MHz
WCK
B
DIOto
DI7
WE
RCK
DOO
to DOl
B
FiE
OE
WRST
Write
reset
RRST
Read
reset
The application circuits and their parameters are for references only and are not intended for use in actual design-in's ..
247
~
OJ
Fig. 6
l
Double speed conversion timing diagram
~
n-1
n
o·
WCK
'U-U-U
WRST
.).
Field m + 1 - - - - - - - -
~~
1~'----J~rfL.--.-A---J
RCK
RRST
000 to 007
(In the last 192 words. the data before 1 field may be output.)
""C
C
~
N
N
CO
Q
NEe
6.
.uPD42280
PACKAGE DRAWINGS
28 PIN PLASTIC SOP (450 mil)
detail of lead end
o
o
LO
tl
o
LO
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
P28G M-50-450A2-2
ITEM
MILLIMETERS
INCHES
f\
19.05 MAX.
0.750 MAX.
B
1.27 MAX.
0.050 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40±0.10
0.016~g:gg~
E
O.UO.l
O. 004~g:gg~
1--.-
F
3.0 MAX.
0.119 MAX.
G
2.55
0.100
H
11.8±0.3
0.465~g:gg
I
8.4
0.331
J
1.7
0.067
K
0.15~g:6g
0.006~g:gg~
L
0.7±0.2
0.028~g:gg~
M
0.12
0.005
N
0.10
0.004
249
NEe
,uPD42280
28PIN PLASTIC ZIP (400mil)
N
r---:-=-
A
I~
'\
:e
d
28
1
........ Ir-
~
I
I
- F !-
I
G~~ I
Q!JITJ
J
I
I
v- I I---
P28V-254-400A
NOTE
Each lead centerline is located within 0.25 mm
(0.010 inch) of its true position (T.P.) at maximum material condition.
250
ITEM
A
F
MILLIMETERS
36.83 MAX.
0.5+ 0.1
INCHES
1.450 MAX.
0.020::8:gg~
G
.p0.25
.p0.Ol0
H
2.54
0.100
I
1.27
0.050
J
1.27 MAX.
0.050 MAX.
K
1.0 MIN.
0.039 MIN.
M
8.9 MAX.
0.350 MAX.
N
2.8±0.2
0.110:':8:GGg
Q
10.16 MAX.
0.400 MAX.
V
0.25:':8:&g
0.01 0:':8:gg~
W
2.54
0.100
y
3.3±0.6
0.130±0.02
NEe
7.
,uPD42280
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering J./PD42280.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (lEI-127).
Please consult with our sales offices in case other soldering process is used, or in case other soldering
is done under different conditions.
TYPE OF SURFACE MOUNT DEVICE
J./PD42280GU: 28-pin plastic SOP 1450 mil)
Soldering process
Soldering conditions
Symbol
Infrared ray reflow
Peak temperature of package surface: 235°C or below,
Reflow time: 30 seconds or below (210°C or higher),
Number of reflow processes: MAX. 2
Exposure limit No•• : 3 days (20 hours pre-baking is
required at 125°C afterwards)
[Remark]
(1) Please start the second reflow process after the temperature, raised by the first reflow process, returns to normal.
(2) Please avoid removing the residual flux with water after
the first reflow process.
IR35-203-2
VPS
Peak temperature of package surface: 215°C or below,
Reflow time: 40 seconds or below (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit Not. : 3 days (20 hours pre-baking is
required at 125 ·C afterwards)
[Remark]
(1) Please start the second reflow process after the temperature, raised by tho first reflow process, returns to normal.
(2) Please avoid removing thn rosidunl flux with water after
the first reflow process.
VP15-203-2
Wave Soldering
Solder temperature: 260 ·C or below,
Flow time: 10 seconds or below,
Temperature of pre-heat: 120 ·C MAX. (Plastic surface
temperature)
Number of flow process: 1
Exposure limit N••• : 3 days (10 hours pre-baking is
required at 125 ·C afterwards)
WS60-203-1
Partial heating method
Terminal temperature: 300 ·C or below,
Time: 3 seconds or below (Per one side of the device).
-
Note
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25°C and relative humidity at 65 % or less.
Caution
Do not apply more than one soldering method at anyone time, except for ·Partial heating
method".
251
NEe
,uPD42280
TYPE OF THROUGH HOLE MOUNT DEVICE
pPD42280V: 28-pin plastic ZIP (400 mill
Soldering process
Soldering conditions
Wave soldering
(For leads only)
Solder temperature: 260·C or below.
Flow time: 10 seconds or below
Partial hoating method
Terminal temperature: 300·C or below.
Time: 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
252
Rambus DRAM.
253
PRELIMINARY DATA SHEET
NEe/
MOS INTEGRATED CIRCUIT
,uPD488170L
18M-BIT Rambus DRAM
1M-WORD X 9-BIT X 2-BANK
Description
The 18-Megabit Rambus™ DRAM (RDRAMTM) is an extremely-high-speed CMOS DRAM organized as 2M
words by 9 bits and capable of bursting up to 256 bytes of data at 2 ns per byte. The use of Rambus Signaling
Logic (RSL) technology makes this 500 MHz transfer rate achievable while using conventional system and
board design methodologies. Low latency is attained by using the RDRAM's large internal sense amplifier
arrays as high speed caches.
RDRAMs are general purpose high-performance memory devices suitable for use in a broad range of
applications including main memory, graphics, video, and any other application whew high-performance
and low cost are required.
Detailed information about product features and specifications can be found in the following document.
Please make sure to read this document before starting design.
Rambus DRAM user's manual (Reference Manual) : IEU-1401
Rambus and RDRAM are trademarks of Rambus Inc.
Features
•
Rambus Interface
• 500 MB/sec peak transfer rate per RDRAM
•
•
RSL interface
Synchronous protocol for fast block-oriented transfers
•
Direct connection to Rambus ASICs, MPUs, and Peripherals
•
40 ns from start of read request to first byte; 2 ns per byte thereafter
• Features for graphics include random-access mode, write-per-bit and mask-per-bit operations
•
Dual 2K-Byte sense amplifiers act as caches for low latency accesses
•
Multiple power-saving modes
•
On-chip registers for flexible addressing and timing
•
Low pincount-only 15 active signals
•
Standardized pinout across multiple generations of RDRAMs
•
3.3 volt operation
Ordering Information
Clock Frequency
Operation Voltage
~PD488170LVN-A50
250MHz
3.3±0.15 V
32-pin plastic SVP (11 x 25)
~PD488170LVN-A45
225MHz
3.3±0.15 V
32-pin plastic SVP (11 x 25)
~PD488170LG6-A50
250MHz
3.3±0.15 V
72/36-pin plastic SSOP type
~PD488170LG6-A45
225MHz
3.3±0.15 V
72/36-pin plastic SSOP type
Part Number
Package
The information in this document is subject to change without notice.
10-33848 (Japan)
255
NEe
,uPD488170L
Pin Configuration (Marking Side)
32-pin plastic SVP (11 x 25)
72/36-pin plastic SSOP type
Voo 0 - - GND
2
BusData8
3
GND
4
BusData7
5
NC
6
BusEnable
7
Voo
8
BusData6
9
GND
256
10
BusData5
11
Voo.
12
RxClk
13
GNDI\
14
TxClk
15
."
Voo
16
BusData4
17
~ ~
co ~
GND
18
BusCtrl
19
Sin
20
VREF
71
SOut
22
BusData3
/3
GND
1.4
BusData2
2'.:J
NC
26
BusData1
27
GND
28
BusDataO
29
NC
30
GND
31
Voo
32
1::
1::
C
C
.......
0
r
Cl
'"
."
....
0
<
Z
BusData 0 - BusData 8
: Bus Data (Input/Output)
RxClk
: Receive Clock (Input)
TxClk
: Transmit Clock (Input)
VREF
: Logic Threshold Voltage (Input)
BusCtrl
: BusCtrl (Input/Output)
BusEnable
: BusEnable (Input)
Voo, Voo.
: Power Supply
GND, GNDA
: Ground
Sin
: Serial Input (Input)
SOut
: Serial Output (Output)
NC
: No Connection
NEe
,uPD488170L
Block Diagram
!
DRAM Array - Bank 0
DRAM Array - Bank 1
c
o
:~
~
MDReg [7 : O[ [8 : 0]
Control Logic
Primary or Secondary Channel
257
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,uPD488170L
1. Pin Function
Signal
BusData [8:0]
I/O
Description
I/O
Signal lines for request, write data, and read data
packets. The request packet contains the address,
operation codes, and the count of the bytes to be
transferred. This is a low-swing, active-low signal
referenced to
RxClk
I
VAEF.
Receive clock.
Incoming request and write data
packets are aligned to this clock.
This is a low-
swing, active-low signal referenced to
TxClk
I
VAEF.
Transmit clock. Outgoing acknowledge and read
packets are aligned with this clock. This is a lowswing, active-low signal referenced to
VRn
.. _-
I
...
BusCtrl
1/0
VAEF.
Logic tllreshold voltage for low swing signals.
- .. -- - ._-
Control signal to frame packets, to transmit part of
the operation code, and to acknowledge requests.
Low-swing, active-low signal referenced to
BusEnable
I
VREF.
Control signal to enable the bus. Long assertions of
this signal will reset all devices on the Channel. This
is a low-swing, active-low signal referenced to
+3.3
VDD, VDDA
V
power supply.
VDDA
VREF.
is a separate analog
supply.
GND, GNDA
Circuit ground. GNDA is a separate analog ground.
I
Initialization daisy chain input. TTL levels. Active
0
Initialization daisy chain output. TTL levels. Active
Sin
.-
SOut
-
high.
high.
258
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,uPD488170L
2. Rambus System Overview
Atypical Rambus memory system has three main elements: the Rambus Channel, the RDRAMs, and a
Rambus Interface on a controller. The logical representation of this is shown in the following figure.
Figure 2-1. Logical Representation
Rambus
Channe I
Master
Controller
DRAM
Core
Rambus Interface
RDRAMs
jRambus
Channel
Slaves)
Rambus Interface
illLLlI
111111
Rambus Channel
= 9 bits every 2 ns
The Rambus Channel is a synchronous, high-speed, byte-wide bus that is used to directly connect
Rambus devices together. Using only 13 high-speed signals, the Channel carries all address, data, and
control information to and from devices through the use of a high level block-oriented protocol.
The Rambus Interface is implemented on both master and slave devices. Rambus masters are the only
devices capable of generating transaction requests and can be ASIC devices, memory controllers, graphics
engines, peripheral chips, or microprocessors. RDIV\Ms are slave devices and only respond to requests
from master devices.
The following figure shows a typical physical implementation of a Rambus system. It includes a controller
ASIC that acts as the Channel master and a base set of RDRAMs soldered directly to the board. An RSocket™
is included on the Channel for memory upgrade using RModule™ expansion cards.
Figure 2-2. A Rambus System Example
Memory Modules
RDRAM
________ Secondary Channels
Socket for
Expansion
\
RDRAM
\
!
· 1 to 320 RDRAMs per system
· 28 traces per Channel
· Controlled impedance design
259
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,uPD488170L
3. Rambus Signaling Logic
RSL technology is the key to attaining the high data rates available in Rambus systems. By employing
high quality transmission lines, current-mode drivers, low capacitive loading, low-voltage signaling, and
precise clocking, systems reliably transfer data at 2 nanosecond intervals on a Rambus Channel with signal
quality that is superior to TTL or GTL-based interfaces.
All Rambus Interfaces incorporate special logic to convert signals from RSL to CMOS levels for internal
use. In addition, these interfaces convert the Channel data rate of one byte every 2 nanoseconds to an
internal data rate of 8 bytes every 16 nanoseconds as shown in the following figure. Although the bandwidth
remainl! the same, the use of a wide internal bus eases internal timing requirements for chip designers.
Figure 3-1. Converting the Channel Data Rate
II
BankB
Bank7
BankS
1
Bank6
Bank3
(3"nI:.4
B,1Il~2
Bank1
RDRAM4
Sense amp cache page 2"
Sense amp cache page 1
IRegj~
Address Comparators
~'ngl
f=!
RDRAM3
RD RAM2
RORAM
Byteh
~
ay;f"
--':c'---
~
~
~
Byteb
Rambus Channel
9 bits every 2 ns
~
1"1"1'1"1"1'1"1"1
Ramb us Interface Cell
-Macroceilin Embedded
Arr<1( and Standard
Cell llbranes
-Converts Rambus
Channcl small SWing
s.gnals to ASIC-corecom p.1llhlc CMOS luvd<,
·ConvCrls9M!.cvery
2 1072 bas(x2)
eve. V lGns
-ContarnsPLls
·Allvendors cells
are 100% compatible
n,
260
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,uPD488170L
4. Register Space Map
The following table summarizes the registers included in all IBM RDRAMs.
Table 4-1. Registers Space Map
Adr[20:10]
Adr[9:2]
Device Type[3:0][8:0]
xx ... xx
00000000
0
Deviceld[3:0][8:0]
xx ... xx
00000001
1
Delay[3:0][8:0]
xx ... xx
00000010
2
Mode[3:0][8:0]
xx ... xx
00000011
3
Reflnterval [3:0][8:0]
xx ... xx
00000100
4
RefRow[3:0][8:0]
xx ... xx
00000101
5
Raslnterval[3:0][8:0]
xx ... xx
00000110
6
Minlnterval[3:0][8:0]
xx .•. xx
00000111
7
AddressSelect[3:0][8:0]
xx ... xx
00001000
8
DeviceManufacturer[3:0][8:0]
xx ... xx
00001001
9
Undefined
xx ... xx
0000101x
10-11
Undefined
xx ... xx
000011xx
12-15
Undefined
xx ... xx
0001xxxx
16-31
Register Name
Register Number
.... --
Undefined
xx ... xx
00 1xxxxx
32-63
Undefined
xx ... xx
01xxxxxx
64-127
Row[3:0][8:0]
xx ... xx
10000000
128
Undefined
xx ... xx
10000001
129
Undefined
xx ... xx
1000001x
._--
130-131
Undefined
xx ... xx
100001xx
132-135
Undefined
xx ... xx
10001xxx
136-143
Undefined
xx ... xx
1001xxxx
144-159
Undefined
xx .•. xx
1010xxxx
160-175
Undefined
xx ... xx
1011xxxx
176-191
Undefined
xx ... xx
1100xxxx
192-207
Undefined
xx ... xx
1101xxxx
208-223
Undefined
xx ... xx
1110xxxx
224-239
Undefined
xx ... xx
1111xxxx
240-255
.-.
(1) Device Type Register
This register specifies RDRAM configuration and size.
(2) Deviceld Register
This register specifies RDRAM base address.
261
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,uPD488170L
(3) Delay Register
This register specifies RDRAM programmable CAS delay values.
(4) Mode Register
This register specifies RDRAM programmable output drive current.
IS) Reflnterval Register
This register specifies RDRAM programmable refresh interval.
Reflnterval Register is used to time the refresh interval for devices which require refresh.
(6) RefRow Register
This register specifies RDRAM refresh row and bank address.
The Ref Row register contains read-write fields. It is used to keep track of the bank and row being
refreshed. Normally this register is only read or written for testing purposes. The fields are aliased in
the following way:
.RowFieldI7:1) equals RefRow[O)[7:1)
RowField[9:8) equals RefRow(2)[l:0)
BankField(3) equals RefRow[ 1)[3)
171 Raslnterval Register
This register specifies RDRAM programmable RAS delay values. The Raslnterval Register contains four
write-only fields. When a rowmiss occurs, or when a row is being refreshed during a burst refresh
operation, it is necessary for the control logic of an RDRAM to count the appropriate number of clock
cycles (tCYCLE) for four intervals. This is done with a counter which is loaded successively with three
values from the Raslnterval Register. This counter is not available for read access and must be tested
indirectly.
(8) Minlnterval Register
This register specifies RDRAM refresh and powerdown control.
This register provides the minimum values for three time intervals for framing packets.
The time intervals are specified in clock cycle (tCYCLE) units.
Caution Minlnterval Register[3J[2]
=0 is necessary.
Because, IBM RDRAM cannot accept Power Down
request.
(9) AddressSelect Register
This register specifies RDRAM address mapping.
(10) DeviceManufacturer Register
This register specifies RDRAM manufacturer information.
This register specifies the manufacturer of the device. Additional bits are available for manufacturer
specific information, e.g. stepping or revision numbers:
(11) Row Register
This register specifies RDRAM current sensed row in each bank.
The detailed functional description is provided in RDRAM Reference Manual.
262
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J.lPD488170L
5. Packet Formation
5.1 Packet Summary
The following table summarizes the transmit/receive functionality of the two RDRAM types for the different
packet classes.
Table 5·1. Transmitting/Receiving Devices for Packet Types
Packet Type
Initiating Devices
pPD488170L
Request Packet
Transmit
Receive
Acknowledge Packet
Receive
Transmit
Read Data Packet
Receive
Transmit
Write Data Packet
Transmit
Receive
Serial Address Packet
--. Serial Control Packet
Transmit
Receive
Transmit
Receive.
Serial Mode Packet
Transmit
Receive
.-
----
..
- -- -
-.- ..
~---.
5.2 Request Packet
The request packet format is shown in the following figure.
Figure 5·1. Request Packet Format
Devico I'in~
'" - - - - -,- - - - - , - - - - - r - - - -
Clock
Cycle
Number
1-- -
-
-
:
(0)
I
even
-1- - -
-
-
T -
- -
-
_.,. - -
.• - ", .• - -
-
- T -
-
-
- -1- -
-
- -
,
-
-
-
-
- I
Bus- I Bus- I Bus- I Bus- I Bus- I Bus· I Bus· I Bus- I Bus- I Bus- I Bus- I
: Enable: Ctrl : Data : Data : Data : Data : Dota : Data : Data : Data : Data :
~
~
(!~
J~) ~ ~5L ~ (~I__ ~ _
L2L~ (!)__ ~
I
:_____ _____ _I8L_: __ _1_ __ _
__
!3J __ :__
__
_1°1 __:
- -.
Op
(0)
I
1-------1
:
(0)
IL
odd
______
:
Op
Op
I
(1)
(3)
~
:
(1)
:
I
even
I
:
odd
:
~--(-11--:
~------1
:
(2)
I
even
I
(2)
:
I
L------t
:
odd
I ______ II
1-
Time
Count
(1: 0)
Adr
(1: 0)
This means that this pin is not used by this packet. If it is not used
by another packet. it is pulled to a logic zero value.
The vertical axis in all packet figures in the following sections shows time in units of clock cycles, with each
clock cycle broken into even and odd bus ticks. The timing is relative, measured from the beginning of the
packet.
263
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,uPD488170L
5.2.1 Start Field
A device should start framing a request packet when it sees this bit asserted to a logical one and it is not
looking for an acknowledge packet nor framing an earlier request packet.
5.2.2 Op[3:0). OpX[1:0) Fields
The command opcode also determines which packets (in addition to the request packet) will form the
transaction. A detailed functional description of the actions that an RDRAM takes for each implemented
command is provided in "Rambus DRAM user's manual (Reference Manual)". The following table summarizes
the functionality of each subcommand:
Table 5-2. Subcommand Summary
SubCommand
Description
Rseq
Read sequential data from memory space.
..
.
------
Rnsq
Read non·sequential (random·access) data from memory space.
Wseq
Write sequential data to memory space.
Wnsq
Write non-sequential (random-access) data to memory space.
Wbns
Write non-sequential (random·access) data to memory space with non·contiguous byte masking.
Npb
Write data is from data packet. There is no bit mask .
Opb
Write data is from data packet. The bit mask is in the MDReg.
Bpb
Write data is from data packet. The bit mask is also from the data packet.
_-
--
------ .. -----
."--
...
-._---"--
...
----
!-------
Mpb
Write data is from MDReg. The bit mask is from the data packet.
Rreg
I----
Read sequential data from register space.
-_.
- - _..
Wreg
Write sequential clata to registor space.
WregB
Broadcast write with no Okay acknowledge permitted.
Alt
Alternate command (same function as the primary command - intended for use in future shared
memory multiprocessor systems).
The memory read commands are forn:Jed using the Rseq and Rnsq subcommands to select sequential or
nonsequential (random) access. The Alt and "null" subcommands select between two equivalent command
sets ("null" means no subcommand). The "Alt" subcommands are reserved for use in future shared memory
multiprocessor systems.
RrrrAaa
Rrrr
= {Rseq.
Rnsq}
Aaa = {Alt. null}
264
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pPD488170L
The following table summarizes the available write commands and shows how they are formed from a 3x4
matrix of the Wwww and Bbb subcommands. The Alt and "null" subcommands have the same meaning as
in the memory read commands.
WwwwBbbAaa Wwww = {Wseq, Wnsq, Wbns}
Bbb = {Npb, Dpb, Bpb, Mpb}
Aaa = {Alt, null}
Table 5-3. Write Commands
-Bbb
subcommand
Wseq
(seq entia I-access
with contiguous
byte masking)
_0-- Wwww subcommands
Wnsq
(non-sequentialaccess)
Wbns
(non-seq uential-access
with non-contiguous-bytemasking)
Npb
WseqNpb
WnsqNpb
WbnsNpb
Dpb
WseqDpb
WnsqDpb
WbnsDpb
Mpb
WseqMpb
WnsqMpb
WbnsMpb
Bpb
Wsoql3pb
WnsqBpb
Not implemented
--
There are three Wwww subcornrnands. They control the accessing pattern and the use of non-contiguous
byte masking.
Wseq - octbyte blocks in the RDRAM core are accessed in sequential (ascending little-endien) address
order. Contiguous byte masking is controlled with the Adr[2:0] and Count[2:0] fields of the
request packet.
Wnsq - octbyte blocks in the RDRAM core are accessed in non-sequential address order.
The
addresses for the cictbyte blocks within the sensed row come from serial address packets
which are received on the BusEnable pin.
The address order is arbitrary.
Wbns - octbyte blocks in the RDRAM core are accessed in non-sequential address order, as in the
Wnsq subcommand. In addition, byte masks are transmitted with the write data, permitting
arbitrary non-contiguous byte masking of this write data. The bytemask oct bytes are not
included in the total oct byte transfer count; i.e. a Count[7:3] field of 31 implies 4 bitmask
oct bytes and 32 write data oct bytes, for a data packet size of 36 oct bytes.
There are four Bbb subcommands. They select the type of bit masking to be applied to the write data.
Npb (no-per-bit) -
There is no bit mask applied to thewrite data. The MDReg is not used or modified.
Dpb (data-per-bit) - The MDReg is used as a bit mask, the write data comes from the data packet. The
same bit mask is used for each octbyte. This is also called persistent bit masking.
The MDReg is not modified.
265
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,uPD488170L
Mpb (mask-per-bit) - The bit mask comes from the data packet, the write data comes from the MDReg.
The same data is used for each octbyte. This is also called color masking. The
MDReg is not modified.
Bpb (both-per-bit) - The bit mask and the write data come from the data packet. The MDReg is not
used, but is modified as a side effect (the WwwwBpbAaa commands are. used
to load the MDReg for the WwwwDpbAaa and WwwwMpbAaa commands).
This is also called non-persistent bit masking.
The bitmask oct bytes are included in the total octbyte transfer count; i.e. a
Count[7:3] field of 31 implies 16 bitmask oct bytes and 16 write data octbytes.
5.2.2.1 Op[3:0] and OpX[1:0] Fields for IBM RDRAM
The Op and OpX fields are summarized in the following table.
Table 5-4. Op[3:0] and OpX[1:0] Fields - Command Encodings
266
0,,13:0]
OpX[l:01 = 00
OpXll:01 = 01
OpX[l:0] = 10
OpX[l:0] = 11
0000
Rsoq
Rnsq
Rsrv
Rsrv
0001
RsoqAlt
RnsqAlt
Rsrv
Rsrv
0010
Rsrv
Rsrv
Rsrv
Rsrv
0011
Rsrv
Rsrv
Rsrv
Rsrv
0100
WseqNpb
WseqDpb
WseqBpb
WseqMpb
0101
WseqNpbAlt
WseqDpbAlt
WseqBpbAlt
WseqMpbAlt
0110
Rreg
Rsrv
Rsrv
Rsrv
0111
Wrcg
Rsrv
Rsrv
Rsrv
1000
WnsqNpb
WnsqDpb
WnsqBpb
WnsqMpb
1001
WnsqNpbAlt
WnsqDpbAlt
WnsqBpbAlt
WnsqMpbAlt
1010
Rsrv
Rsrv
Rsrv
Rsrv
1011
Rsrv
Rsrv
Rsrv
Rsrv
1100
WbnsNpb
WbnsDpb
Rsrv
WbnsMpb
1101
WbnsNpbAlt
WbnsDpbAlt
Rsrv
WbnsMpbAlt
1110
Rsrv
Rsrv
Rsrv
Rsrv
1111
WregB
Rsrv
Rsrv
Rsrv
,
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,uPD488170L
The command opcode determines whether the other fields of the request packet are implemented (Imp)
or unimplemented (Unimp). This is summarized in the table below.
Table 5-5. IBM RDRAM Request Packet Fields - Imp or Unimp
Count[7:3)
Count[2)
Count[1:0)
Close
ReqUnimp[7:0)
Unimp(OO) Unimp(O.O)
Unimp(1)
Unimp(11)
Unimp(O)
Unimp(O.O)
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Imp
Il11p
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqNpb
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqDpb
Imp
Imp
Imp
Il11p
Imp
Imp
Imp
Unirnp(O.O)
WseqBpb
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqMpb
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqNpbAlt
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqDpbAlt
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqBpbAlt
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqMpbAlt
Imp
Imp
Imp
Imp
Rreg
Imp
Wreg
Imp
WnsqNpb
Imp
WnsqDpb
Command
Adr[35:3)
Adr[2)
Rsrv
Unimp(O.O)
Unimp(O)
Rseq
Imp
Imp
Imp
Rnsq
Imp
Imp
RseqAlt
Imp
RnsqAlt
Adr[1:0)
Imp
Imp
Imp
Unimp(O.O)
Imp
Unimp(OO) Unimp(O.O)
Unimp(1)
Unimp(11)
Unimp(O)
Unimp(O.O)
Imp
Unimp(OO) Unimp(O.O)
Unimp(1)
Unimp(11)
Unimp(O)
Unimp(O.O)
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqBpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqMpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqNpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqDpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqBpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqMpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsNpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsDpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsMpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsNpbAlt
Imp
Unimp(O.O)
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
WbnsDpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsMpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WregB
Imp
Imp
Unimp(1)
Unimp(11)
Unimp(O)
Unimp(O.O)
Unimp(OO) Unimp(O.O)
267
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yPD488170L
5.2.3 Adr[35:0] Field
The Adr field is used as either a memory or register space address depending upon the OP[3:0] and OpX[1 :0]
fields. Devices extract a portion of the Adr field to match against their Deviceld register (ldMatch), thus
selecting the device to which the request is directed. The remainder ofthe Adr field accesses the desired region
of the device's memory or register space. The memory read and write commands and the Rreg and Wreg
commands will only take place ifthere is an IdMatch. The IdMatch criteria is ignored forthe WRegBcommands,
with all responding devices performing the required actions.
The Rambus protocol uses quadbyte resolution in the data packet for register space read and write
commands; i.e. one quadbyte is the smallest data item that may be transferred, and all transfers are an integral
number of quadbytes. The Adr[35:2] field is the quadbyte address. The Adr[1:0] field is Unimp for these
commands, and should be driven with "00" by initiating devices.
The Rambus protocol uses octbyte resolution in the data packet for memory space read and write
commands; i.e. one octbyte is the smallest data item that -may be transferred, and all transfers are an integral
number of octbytes. The Adr[35:3] field is the octbyte address.
Some commands use the Adr[2:0] field to specify contiguous byte masking. Refer to "Rambus DRAM user's
manuallReference Manual)".
5.2.4 Count[7:0] Field
Tlw following table summarizes the transfer count ranges for IBM RDRAMs:
Table 5-6. Transfer Count Summary
,uPD488170L
Count Range
Maximum count for memory space
32 oct bytes
Minimum count for memory space
1 oct byte
Maximum count for register space
1 quadbyte
Minimum count for register space
1 quadbyte
----
-------- ---
Register space read and write commands use a transfer count of one quadbyte, regardless ofthe Count[7:0]
field value.
Memory space read and write commands specify the number of octbytes to be transferred with the
Count[7:3] field. An offset-by-one-encoding is used so that "00000" specifies one octbyte, "00001" specifies
two octbytes, and so on up to "11111" which specifies thirty-two octbytes. The transfer count does include
the octbytes containing bitmasks (for commands using the Bpb subcommand). The transfer count does not
include the oct bytes containing non-contiguous ByteMasks (for commands using the Wbns subcommand).
Some commands use the Count[2:0] field to specify contiguous byte masking. Refer to "Rambus DRAM
user's manual (Reference Manual)".
Memory space transactions to RDRAMs are not allowed to cross internal row address boundaries within
the device. Attempts to do so have Undef (undefined) results. These row boundaries are at 2kbyte intervals
for IBM RDRAMs.
268
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,uPD488170L
5.2.5 Adr[2:0] and Count[2:0] Fields for Contiguous Byte Masking
An initiating device wishing to transfer an arbitrary number of contiguous bytes to a starting address on
an arbitrary byte boundary may do so with theAdr[2:0] and Count[2:0] fields for some ofthe commands. These
commands include:
RrrrAaa
WseqBbbAaa
The transfer count and starting address are given by:
MasterCount[7:0] specifies the number of bytes which the master device wishes to transfer.
Adr[35:0] specifies the starting byte address (this is the same as the Adr[35:0] field in the request
packet)
Where the convention used by the initiating device for the count is that Master-Count[7:0] = "00000000"
means one byte, MasterCount[7:0] = "00000001" means two bytes and MasterCount[7:0] = "11111111" means
256 bytes (an offset-by-one encoding; the data block count is equal to MasterCount[7:0]+1).
The initiating device converts this internal count value into a value for the request packet with the following
formula. Little-endien byte addressing is used for specifying bytes within octbytes.
Count[7:0] = Adr[2:0] + MasterCount[7:0]
(Eq5-1)
Where "+" denotes unsigned in.eger addition of two bit fields (short fields are zero-extended on the left).
If the value of Adr[2:0] + MasterCount[7:0] is greater than 255 (it may be as much as 262), then the initiating
device must break the request into two transactions.
The Adr[2:0] and Count[2:0] field generate masks for individual bytes within an octbyte. The Adr[35:3] and
Count[7:3] field have the octbyte resolution previously described. The following tables show how the byte
masks are generated. In the case of memory read transactions, the byte masks that are generated do not affect
the data that is returned by the RDRAM; all data bytes in the first and last octbytes are returned in the read
data packet.
In the case of memory write transactions, ByteMaskLS[7:0] applies to the first octbyte at Mem[AV][7:0][8:0].
Byte MaskMS[7:0] applies to the last octbyte at Mem[AV+CV][7:0][8:0]. All intermediate oct bytes use a byte
mask of 11111111 (a one means the byte is written, a zero means it is not). Here AV is the value ofthe Adr[35:,3]
field when interpreted as an unsigned, 33 bit integer, and CV is the value of the Count[7:3] field when
interpreted as an unsigned, 5 bit interger. If the Count[7:3] is "00000" (one octbyte), the ByteMaskLS[7:0] and
ByteMaskMS[7:0] masks are logically 'anded' together to give the effective byte mask.:
Table 5-7. Adr[2:0] to ByteMaskLS[7:0] Encoding
Adr[2:0]
ByteMaskLS[7:0]
Adr[2:0]
ByteMaskLS[7:0]
000
11111111
100
11110000
001
11111110
101
11100000
010
11111100
110
11000000
011
11111000
111
10000000
269
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Table 5-8. Count[2:0] to ByteMaskMS[7:0] Encoding
Count[2:0) ByteMaskMS[7:0) Count[2:0) ByteMaskMS[7:0)
000
00000001
100
00011111
001
00000011
101
00111111
010
00000111
110
01111111
011
00001111
111
11111111
The detailed functional description is provided in "Rambus DRAM user's manual (Reference Manual)".
5.2.6 Close Field
The Close field causes a currently accessed row to be explicitly restored (written back to the core if its Dirty
flag for that bank is set) after the current access has completed. This reduces the latency of a subsequent acces's
to a different row of memory space in, the same bank of that device; i.e. the tRele,Sensodele,n Nack timing is used
rather than the tRotrySensedDirty timing.
Table 5-9. Close Field Encodings
Description
Close Field
Don't restore the currently accessed row of memory. It may be left sensed and
0
either clean or dirty.
I--
1
Restore the currently accessed row of memory if its Dirty flag is set. It will be left
sensed and clean.
5.2.7 RcqUnimp[7:0] Fields
These fields are unimplemented (Unimp) in the request packet. They should be driven as zeroes by initiating
devices which satisfy this Version of the Rambus protocol.
Responding devices which satisfy this Version of the Rambus protocol should ignore these fields and
process the request according to the content of the Start. Op[3:0). OpXl1 :0). Adr[35:01. Count[7:0). and Close
fields. The protocol Version number of a device is held in the DeviceType register.
270
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5.3
.uPD488170L
Acknowledge Packet
The Ack[1:0] field carries the acknowledge encoding from the responding device(s) to the initiating device
and a'ny other listening devices. The following figure shows the format of the acknowledge packet.
Figure 5-2. Acknowledge Packet Format
Device Pins
·-----L-----'-----r-----I-----'-----r----'-----r-----I-----'-----1
, Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- ,
Clock
Cycle
Number
: Enable:
1-------.
[01
I
even
I
l
r-----[01
,l _ _odd
____
Ctrl
: Data
: Data
: Data
:_ _ _ _ _ .J' _ _ _ _ _ 'L [_____
8 1 'I _____
171 I'
'
[61
: Data
: Data : Data : Data
: Data
: Data
:
'
'
'
'
'.
[51
[41
'
[3]
,
[21
[11
[01
. ____ 1_____ .J _____ L _ _ _ _ _ 1_ _ _ _ _ .J _ _ _ _ _ L _ _ _ _ _ I
.j:
,-, :;::~~~~::~:::~-.._---T[_:~.-=~==~~~'T.~
-:'l::.:t~i:
:.:.,
.-. -..-.-.: .- .:-.. .'.I. -.. .-.. . -. . . -.. I =
. :1::~=.T.T'L=~~-,.
C
:': .~ :~.. ' .. .
1<'~.,,~~:\:
J
Time
.........-.. _...-.....
~.~,:f. ~.:.~:.J.•;~.?(~
. .. "
This means that this pin is not u~U(1 hy tllI~; packet. If it is not used
by another packet. it is pulled to a loOic /Uro value.
--------'
The following table summarizes the four combinations of the Ack[ 1:0] field. Tho I\ck3 combination is U ndef.
The Okay combination indicates that the read or write access to the specified space will take place.
When a responding device acknowledges a request with a Nack, then there will be no immediate change
in the state of the device's memory space or register space. The responding devic:o will take the appropriate
steps to make the requested region of memory or register space accessible when the initiating device makes
a subsequent request. The initiating device will need to wait some device-dependont length of time until the
requested region is available.
There are three possible reasons for an RDRAM to respond with Nack. They arc summarized below. The
detailed functional description is provided in "Rambus DRAM user's manual (Reference Manua!)".
tPostMemWriteDelay or tPostRegWriteDelay violation
RowMiss (this causes a delay of tRetrySensedClean or tRetrySensedDirty)
ongoing refresh (this causes a delay of up to tRetryAefresh)
271
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Table 5-10. Ack[1:0] Encodings
Commands
allowed to
Ack
use the Ack [1:0)
Combination
00
All
Name
Nonexistent Indicates passive acceptance of the request (WregB), or
commands
----
All
Description
other commands).
.
01
Okay
Indicates that the request was accepted by the addressed
--
10
Nack
commands
272
Spec
by the addressed (responding) device.
but WregB
'AIi-
Spec
indicates that the addressed device did not respond (all
commands
'Ail
Spec
Undef
Indicates that the request could not be accepted because
Spec
the state of the responding device prevented an access
at the fixed timing slot.
11
Ack3
This should not be returned by this responding device.
commands
Initiating devices will, when presented with this combi-
but WregB
nation, have an undefined response.
Undef
NEe
,uPD488170L
5.4 Data Packet
The following figure shows the format of a data packet for register space read and write commands. It
consists of 1 quadbyte driven on the BusData[8:0] wires for RDRAMs.
Other responding devices may support data packet lengths longer than one quadbyte.
Figure 5-3. Data Packet Format (Register Space)
Device Pins
.. - - - - -,- - - - - , - - - - - r - - - -
Bus- I Bus: Enable: Ctrl
~
I
Clock
Cycle
Number
:
[0]
-1- -
-
-
-"T - -
- -
-
r - - - - , - - - - -
T" -
-
-
-
-,- -
-
-
-, -
-
-
-
-
I
Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I
: Data : Data : Data : Data : Data : Data : Data : Data : Data :
5 ~ [~I__ ~ 3) __ :__
~
[?~ _l_l~l
~ I~I __ ~ _
I
:_____ _____ _£81 __:__
__ :__ L1_ __
_1
L2l_ __
!01 __:
I
I ______
even JI
L
I
:
[01
odd
:
111
I
r------j
even
I
I-------t
[11
I
odd
I
'_ - -
-
-
Time
I
__ I
This means that this pin is not used by this packet. If it is not used
by another packet. it is pulled to n loUic zero value.
---- --------- --------'
The following figure shows the format of a data packet for memory spaco read and write commands. For
most of these commalHh;. it consists of 1 to :12 octbytos driven on the BusData[8:0] wires. In the figure. "n"
is either the CV valliD (if the transaction is allowed to complete) or the last count value (if the transaction is
terminated prematurely by the serial control packet). "CV" is the value of the Count[7:3] field when interpreted
as an unsigned. 5 bit integer.
The detailed functional description is provided in "Rambus DRAM user's manual (Reference Manual)".
273
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gPD488170L
Figure 5-4. Data Packet Format (Memory Space)
Del(ice Pins
.. - - - - -,- - - - - , - - - - - r - - - - -,- - - - -
Clock
Cycle
Number
I
I
1-
[0]
odd
___ - __
111
Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I
: Data : Data : Data : Data : Data : Data : Data : Data : Data :
I
I
I
I
[8]
I
[7]
, _ _ _ _ _ ...1 _ _ _ __ L ___ __ 1 _ _ _ _ _
I
[6]
I
[5]
I
[4]
I
[3]
I
12]
l
I
I
1
I
even _
L _____
I
[1]
I
odd
r------
1
[2]
even
______
)
I
1-
I
I
I
I
L
[2]
odd
I
______ !
I
[3]
even
I
I
r-----131
odd
I
I
I
I
I
r-------J
I
.~~;
-
Data
10]17] [8: 0]
I
I
1
------,
:
[4*n]
I
even
r------
[4*n]
:
I
1
:
~ __o~~ __ :
: [4*n+1] :
I
I
even I
: (4*~~1]-:
:
odd
I
r------~
: [4*n+2] :
I
even I
1- _ _ _ _ _ _ 1
: [4*n+2] :
I
odd
:
:-14*~~3]- :
:
even
r------
:
1
: [4*n+3] :
I ______
odd JI
~
Time
274
I
[1]
I
[0]
I
J. _____ ,_____ ...J _ _ _ _ _ L _ _ _ _ _ • _ _ _ _ _ ...1 _ _ _ _ _ L _ _ _ _ _ I
.':.:
10]
even
r------
T - - - - -,- - - - - -, - - - - - T - - - - -,- - - - - , - - - - - I
Bus- I Bus: Enable: Ctrl
I
This means that this pin is not used by this packet. If it is not used
by another packet, it is pulled to a logic zero value.
NEe
,uPD488170L
5.5 Serial Address Packet Format
The serial address packet is transmitted by the initiating device and received by the responding devices.
It provides eight low-order address bits for each oct byte which is accessed in memory space (a non-sequential
or random-access transfer). These eight address bits are transferred serially on the BusEnable pin of the
RDRAM, and are thus called a serial address. Each eight bit serial address accesses an octbyte of data within
the RowSenseAmpCache of one of the two banks of the RDRAM. The complete set of serial 'addresses
transmitted by the initiating device during the transaction are referred to as a serial address packet. The
commands which use this packet are the RnsqAaa, WnsqBbbAaa, and WbnsBbbAaa classes of commands.
The high order bits for each oct byte are provided by the Adr[35:11] address bits from the request packet.
The low-order address bits for the first octbyte are Adr[10:3]. also from the request packet. The low-order
address bits for octbytes [n:1] are provided by the serial address packet. As before, "n" is either the CV value
(if the transaction is allowed to complete) or the last count value (ifthe transaction is terminated prematurely
by the serial control packet). "CV" is the value of the Count[7:3] field when interpreted as an unsigned, 5 bit
integer. The detailed functional description is provided in "Rembus DRAM user's manual (Reference Manual)".
Table 5-11. Serial Address Fields (i
Serial Address Field
SAdr[i][10:3]
Description
Low-order address bits for each octbyte.
= n:1)
Unimp
Imp
Imp
275
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,uPD488170L
Figure 5-5. Serial Address Packet Format
Device Pins
r-----I-----'-----r-----I-----T-----r----'-----r-----'-----,-----.
,I
Clock
Cycle
Number
------.
[41
'181
[71
[61
'
[51
[41
[31
121
[11
[01
: _ _ _ _ _ .JI _ _ _ _ _ L ___ __I
I _'_ _ _ _ 1.I _ _ _ _ _ L ____ .JI _ _ _ _ _ LI _ _ _ _ _ I1_ _ _ _ _ .JI _ _ _ _ _ IL _____ II
I
even
r------
':
, Bus- I Bus- , Bus- , Bus- , Bus- , Bus- , Bus- I Bus- , Bus- , Bus- I Bus- ,
: Enable: Ctrl : Data : Data : Data : 'Data : Data : Data : Data : Data : Data :
141
4
I
odd
1-------:
[51
I
I
I
I
even
I
[51
odd
r
L ______ :
r------
161
even
____
161
odd
,
1
:
JI
I
------j
171
f
even
171
:
I
odd
I
.-------,
,
r-------J
SAdr
[111101
I----I----I--,-,-,·""-···,,·"''''''''-'''''''''--~~~~----~--:-:-':-:-'-+::-~:::-I
,, - - - - - - - 1
[4*nl
I
even
I
t
r------~
[4*nl
~
I
__o.?9 __ !
SAdr
Inl131
SAdr
[n1141
,I 14*n+11 ':
SAdr
even I
.------1
Inl151
1
, [4*n+11 '
:
odd
r------
:
i
: [4*n+21 :
II- _ _
even
'
____ J
: [4*n+21 :
,
odd
:
.------1
,
I
[4*n+31 '
I
even 'I
r------ 1
: 14*n+31 :
,'"
odd
Time
276
'
______ .1
'""-----.. -----.--------""----'-~-'-~
This monns that this pin is not used by this packet. If it is not used
by another packet, it is pulled to a logic zero value,
NEe
,uPD488170L
5.5.1 Serial Control Packet Format
The serial control packet is transmitted by the initiating device and received by the responding devices.
It provides for the early termination of a memory space read or write transaction (before the specified data
count in the Count[7:3) field has elapsed). It consists of eight bits transferred serially on the BusCtrl pin of
the device, thus it is referred to as a serial control packet. The eight bits have the same timing alIgnment as
the serial address packet. The commands which use this packet are all of those which access memory space.
The register read and write commands do not use the serial control packet. The IBM RDRAM implements
this packet.
The termination occurs on octbyte data packet boundaries. The next figure shows the format of the serial
control packet. The following table summarizes the function of the bits within the serial control packet. Note
that the bits in the even bus ticks must be zero in order for framing to work properly (otherwise, one of these
bits would be interpreted as the Start bit of a new request packet). The SCtrl[5) bit is used to control
termination, and the other three odd bus tick bits are unimplemented.
Table 5-12. Serial Control Fields
Serial Control
Fields
SCtrl[O)
Description
This bit must be a zero due to fralTlil1U roquirollwl1ts.
~~~----~--~-------
SCtrl(1)
unimplemented
SCtrl(2)
This bit must be a zero due to framing requirements.
- -- -- -----
'---=-=---c::-:-:----I---=--c-~------:---
-
------
- - --
- ------ - - -----------------------~-----+---------1
SCtrl(3)
unimplemented
SCtrl(4)
This bit must be a zero due to framing requirements.
SCtrl(5)
o means
SCtrl(6)
1 means terminate the current access.
-------- ----------------------------+---------1
This bit must be a zero due to framing requirements.
SCtrl[7]
unimplemented
---~--~----------+~~~~
------------------------------~--------_1
don't termirwte the current access.
-~----------4-~-~
If a memory read transaction (RrrrAaa) is terminated by asserting the SCtrl(5) bit to a logical one, the data
octbyte with which it is associated is not transmitted by the responding device. The initiatin-g device may start
a new transaction once the transmission of the read data packet has ceased.
The detailed functional
description is provided in "Rambus DRAM user's manual (Reference Manua"".
277
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,uPD488170L
Figure 5-6. Serial Control Packet Format
Device Pins
~-----I-----'-----r-----I-----T-----r----,-----r-----I -----'-----1
Bus- I Bus: Enable: Ctrl
~
I
Clock
Cycle
Number
Bus· I Bus- I Bus- t Bus- I Bus- I Bus- I Bus- I Bus- I Bus- I
: Data : Data : Data : Data : Data : Data : Data : Data : Data :
~
17L
J~l __ ~ _ 5 ~ I~I__ ~
L2! _~ __I!l__ ~ _
I
:_____ _____ _!81 __:__
_1_
L1_ __
_13L _: __
!OL_:
:- --IOJ --:
even
1
r------~
J
10J
~
I
I
:
odd
______
JI
111
I
even
:
111
I
L------ 1
I
odd
r------~
121
:
even
I
I
121
I
I
odd
:
I
I""------~
I. __ , _ _ _ _ j
131
~_~~~n__
I
13J
03~
~ __
I
__ ;
Time
278
t
This means that this pin is not used by this packet. If it is not used
by another packet, it is pulled to a logic zero value.
NEe
jlPD488170L
5.5.2 Serial Mode Packet Format
The serial mode packet transmitted by initiating devices, and received by responding device. Its format
is shown in the following figure.
Figure 5·7. Serial Mode Packet Format
Device Pins
.... - - - - -,- - - - - , - - - - - r - - - -
Clock
Cycle
Number
,------,' [ 0 ) ,
,
even,
r------,
-1- -
- -
- 1 - - - - -
r - - - -, - - - - -
T -
- -
- -1- -
- -
-
,
-
-
-
-
- I
, Bus· , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- ,
: Enable: Ctrl : Data : Data : Data : Data : Data : Data : Data : Data : Data :
:_ _ _ _ _ ..1' _ _ _ _ _ 'L. [
8 ) '1 _____
[7) .1, _____
[6) ,1_____
[5) J , _____
[4) 1., _ _[3)
[2) .J, _ _[1)
[0)
,I
_____
_ _ _ ,1_____
_ _ _ ,L. _____
SMode
[0)
r-~_;~~_+----,_--
10)
:
,1 _ _odd
_ _ _ _ ..1'
" This means that this pin is not used by thi-~-p~-~ket. If i-i is Imt used
by another packet. it is pulled to a logic zero value.
Time
I
The serial mode packet modifies the state of the CountOO[7:0) and Count11[7:0) counters.
These counters cause operating mode transitions when they reach special values. The detailed functional
description is provided in "Rambus DRAM user's manual (Reference Manual)".
A serial mode packet with the SMode[1 :0) field setto 00 is the default. Most transitions are caused by blocks
of sequential serial mode packets, each with the SMode[1:0) field set to 11. The serial mode packets should
never set SMode[1 :0) field to 01 or 10. This is because in some of the operating modes, the clock generator
is unlocked (the frequency is correct but not the phaso). Whon this happens, the BusEnable receiver is unable
to discriminate anything other than long pulses of wro~; or onos. Bocaww the frequency of the clock generator
is correct, it can count the length of these pulses with moderate accuracy.
Table 5·13. Serial Mode Fields
SMode[1:0)
Description
Spec/Rsrv/
Undef
Spec
00
Increments CountOO[3:01. clears Count11[7:0).
01
-
10
-
Undef
11
Increments Count11[7:0), clears CountOO[3:0)
Spec
Undef
279
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6. State Diagram
The following figure is a state diagram of the Frame state machine. The operating mode of the device
depends upon which of the nine states it is in:
reset mode - ResetState
standby mode - StandbyState
active mode - ActiveState, IdCompareState, DeviceState, OkayState, NackState, AckWindowState
This section will only discuss the first three states (ResetState, StandbyState, ActiveState). The remaining
five states which are shown shaded in the state diagram (ldCompareState, DeviceState, OkayState, NackState,
AckWindowState) will be dealt with in the "Rambus DRAM user's manual (Reference Manuall".
The device will enter ResetState when power is initially applied (PowerOn). In ResetState, the device will
be in the reset operating mode, in which all control registers assume a known state. If power has just been
applied, the device will pass through ActiveState and settle in StandbyState, and remain there until serial mode
packets are received from an initiating device.
Figure 6-1. Frame State Machine - State Diagram
IlCGctState (reset mode)
(plncc device in known state)
PowerOn
Count11 = IModoAR. MIN
BusCtrleven = 1
(Start Bit)
AckWindowState (active mode)
(wait for AckWinDelay to elapse)
Execute si\jJnal
to Command
state machine
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ActiveState is the state in which all decisions are made to transition to the states for the other operating
modes. From here, the device will also enter the transaction-framing states. Refer to "Rambus DRAM user's
manual (Reference Manua!)".
After poweron, the device will re-enter ResetState when the value of the Countll[7:0] counter is greater
than or equal to tModeAR,MIN. The device will leave ResetState when the value of the Countll [7:0] counter is
less than tModeSA.MIN. This will happen when an SMode[1 :0] field of 00 is received, causing the Countll [7:0]
counter to clear.
The device will enter StandbyState when the value of the CountOO[3:0] counter is greater than or equal to
tModeDelay,MAX. The device will leave StandbyState when the value of the Countll [7:0] counter is greater than
or equal to tModeSA,MIN.
Caution
The device will enter PowerDownState when the PO bit is set (after a delay of txxxx). But PO
(Minlnterval Register [3][2])
=0 is necessary.
Because, IBM RDRAM cannot accept Power Down
request.
6.1 Parameters for Operating Mode Transitions
The following table summarizes the parameter values associated with operating mode transitions of a
responding device. A minimum and maximum value are given forthe parametersto account for implementation
differences. In all cases, the SMode[l:0] field of the consecutive serial mode packets must have the value 11
to cause an operating mode transition (with the exception of the tModeDelay.MAX as mentioned in the previous
section).
Initiating devices must use values within the minimum and maximum SMode packet count
requirements shown above to control operating mode transitions.
Table 6-1. Responding Device Parameters for Operating Mode Transitions
Count
Parameter
Name
Minimum
(clock
cycles)
Maximum
(clock
cycles)
tModeSA
1
4
Description
Number of SMode packets to calise a transition from
Standby-Mode to ActiveMode
,
Rsrv
5
9
Reserved for future functionality
Undef
10
15
Undefined
Rsrv
21
189
Reserved for future functionality
Undef
190
207
Undefined
Rsrv
225
253
Reserved for future functionality
Undef
254
271
Undefined
tModeAR
272
-
Number of SMode packets to cause a transition from Active-
tModeDffSet
4
-
..
""-
Mode to ResetMode
Offset from beginning of SMode packet to request packet for
standby to active transition
tModeDelay
-
10
Delay from end of SMode packet to request packet for
standby to active transition
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6.2 Standby Mode and Active Mode
The following figure shows the basic transitions between active and standby modes in response to serial
mode packets
Figure 6-2. Basic ActiveMode/StandbyMode Transitions
.
Clock
Cycles
Bus En BusCtrl
tModeSA. MIN
BusData IB : 01
I
tModeOffSel. MIN
tModcDclclY, r.l"'~
Active Mode
This is a timing diagram, with time increasing in the downward direction. The time scale is in clock cycles,
as shown on the left scale. The value of each of the eleven low-swing signal pins of the responding device
is shown with the assumption that tTR is zero (the responding device is located at the master end of the
Channel).
Serial mode packets with an SMode[ 1:0] field are shown as a box with a "11" label in the BusEn column.
The BusEnable defaults to
<1
logical zero villuc, The initiating device has transmitted tModeSA,MAX serial mode
packets with SMode[1:0J equal to 11 (this is the longest sequence permitted for invoking a standby to active
transition). After the first tModcSA,MIN serial mode packets, the device begins the transition to active mode. It
reaches active mode after tModcOffS"I, MIN clock cycles after the start of the first serial mode packet. It remains
there for tModeOffSetMAX clock cycles after the last serial mode packet,
The responding device is in active mode when it begins framing the request packet. A transaction may
begin in any of the clock cycles with the light shading above (labeled "Active Mode"),
If the serial mode packet(s) causing a standby to active mode transition are not followed by a transaction
with tModcOffSet,MAX clock cycles after the last serial mode packet, then the responding device will return to
standby mode.
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The next figure shows the case in which a transaction is started as early as possible after a serial mode
packet which causes a standby to active mode transition.
Figure 6-3. ActiveMode/StandbyMode Transition - Early Transaction
.
Clock
Cycles
[
BU5Data
BusEn BusCtrl
tMod,SA, MIN
I
,--18_:_0~J_ _ _ _ _ _ __
T
tModeOffSet. M~
,
~
Transaction (Active Mode)
"IF)'~.:::"'f[~"]!f;;;
A transaction is composed of packet types other than serial mode packets, and will be defined in the next
chapter. These other packet types lie entirely inside the heavy black box in the above two figures. When a
transaction has completed, the device returns to standby mode.
The detailed functional description is
provided in "Rambus DRAM user's manual (Reference Manua))".
6.3 ResetMode
Reset mode is entered when a consecutive sequence of tModnllll,MIN serial modo packets with a value of 11
are seen by a responding device (shown in the following figure), In rO:;l!l modI), all devices enter a known
state from which they may be Initialized. The device remains in roSOllllOdu for a:; 10110 as serial mode packets
with 11 value are received. When one or more serial mode packlll:; wilh a vall/() of 00 are seen, the responding
device enters the active mode state.
Although devices enter the active mode state immediately, their clock cilGlJitry requires a time tLock,MIN to
resynchronize. Initiating devices must wait this long after the transition out of reset mode before starting any
transactions.
Note that in order to keep the devices in active mode during this synchronization process, it is necessary
to provide a burst of serial mode packets every tModeDelay.MAX clock cycles. This burst is shown as tModeSA,MAX
in length, but may, of course, be as short as tModeSA,MIN. If the device is not kept in active mode during
synchronization, then the synchronization process requires tLock.MIN clock cycles.
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Figure 6·4. ResetMode to ActiveMode Transition
.
Clock
Cycles
Bus Data [8 : OJ
BusEn BusCtrl
§
tModeSA, M I N I
T
Active Mode
tModeOffSet. Mj_
tM","·'•• M I N I
tModeOffSet.
tModetl-elay, MAX
Active Mode
tr,lutH).·II'/.I,'AX
Active Mode
T
~
tLoCk. Active, MIN
tModeS" M I N I
tModeOllSet.
T
M~
Transaction (Active Model
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7. Transactions
7.1 Read Transactions
The following figure shows the basic form of a memory space or register space read transaction. There are request
and acknowledge packets. with the same tAckDelay and tAckWooDelay timing constraints as already discussed (tAckWooDelay
will not be shown explicitly on any further transaction diagrams in this document.
When the responding device transmits an Okay acknowledge packet to the initiating device. it will also transmit
a data packet with read data. This packet is sent a time tA.adDelayafter the end of the request packet. The tReadDelay
value is in tCYCLE units and is programmed into the ReadDelay field of the Delay register of each responding device.
It is not required to be the same for all devices within a Rambus system. but the difference (tAeadDol.y . tAckDelay) is
required to be the same. This allows initiating devices to use the acknowledge packet to determine when the read
data packet begins. The detailed functional description is provided in "Rambus DRAM user's manual (Reference
Manuall".
Figure 7-1. Read Transaction
.
Clock
BusEn BusCtrl
Cycles
tAckD••y
BusData [8 : OJ
j
----'---+----t'Ai-:·cT"k-l- ~.
I-- _
tRCadDelay
+...L..
............_. _ _ _ _ _ _ _ _ _ _ _ _ _ _
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7.2 Write Transactions
The following figure shows the basic form of a memory space or register space write transaction. There are request
and acknowledge packets, with the same tAckDelay and tAckWonDelay timing constraints as already discussed.
When the initiating device transmits a request packet to the responding devices, it will also transmit a data packet
with write data. This packet is sent a time tWrlteDelay cycles after the end of the request packet. The tWrlteDelay is in
tCYCLE units and is programmed into the Write Delay field of the Delay register of each responding device. It is required
to be the same for all devices within a Rambus system. A responding device will see the same tWnteDelay interval
between the request and write data packets whether the device is on the Primary Channel or on a Secondary Channel.
If the responding device returns an Okay acknowledge packet, then the transaction is complete at the end of the
acknowledge window or at the end of the write data packet, whichever is later. The next request packet can be
transmitted in the following clock cycle except for the case in which a register or memory space write to a device
is followed by any other transaction to that device. In that case, one of the following two intervals must be inserted
between the two transactions, where the memory or register case depends upon the first transaction.
•
tPostRegWriteDelay if the current transaction is a register space access
•
tro,tMemWnteDelay if the current transaction is a memory space access
If the r()~;ponding device returns a Nack or Nonexistent acknowledge packet for a write command, then no write
data packet is required by the responding device. The current transaction is complete at the end of the acknowledge
window, or when the initiating device stops transmitting the write data packet, whichever is later. The next request
packet Cilll be transmitted in the following clock cycle. For the case of a Nack or Nonexistent, the initiating device
must termillate the write data packet before another initiating device is given control'of the Rambus Channel for a
transaction. This is part of the arbitration mechanism used by the initiating devices. The arbitration mechanism is
not
specifi(~d
is provirlml
111
in this document because it does not use the Rambus Channel. The detailed functional description
"Rambus DRAM user's manual (Reference Manual)".
Figure 7-2. Write Transaction
Clock
Cycles
BusEn 8usCtri
BusData (8 : 01
Request
•
tAckDof
twnteDelay
Data
lAck
f-"l"",
tpost~cgWrltcDelav or tPostMemwrileDelaV
I
I
286
Next transaction to same device
Next transaction to different device
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7.3 Read Transactions with Serial Address Packet
The following figure shows a memory space read transaction for a command which uses the serial address packet.
For a transaction which moves (n+ 1) octbytes of read data, the serial address packet will be (4 x n) clock cycles in
length (recall that the low-order address bits for the first octbyte of read data come from the request packet).
Each serial address subpacket (each SAdr[i](l 0:31 field) is transmitted by the initiating device a time tSenalReadOffSet
clock cycles before the octbyte of read data to which it corresponds. This means that the serial address packet will
move with the read data packet, with a constant offset.
•
tSerialAeadOffSet is the delay from the beginning of a serial address subpacket to the beginning of the read data
subpacket (oct byte) with which it is associated.
The detailed functional description is provided in "Ram bus DRAM user's manual (Reference Manual)".
Figure 7-3. Read Transaction with Serial Address Packet
Clock
Cycles
BusEn BusCtrl
BusData [8 : 01
Request
~
SAdr
(1)
[10: 31
-ML
U~k-'
tFleadDeiay
-,
SAdr .
In-1)
[10: 31
Data [01 [7 : 01 [8 : 01
=RData [01 [7 : 01 [8 : 01
SAdr
[nl
110: 31
Data [11 [7 : OJ 18: 01
=RData (1) [7: 0118: 01
- - _._-
I---tSenalReadOffS et
Data [n-1) [7 : 01 [8 : 01
Data [nl [7 : 01 [8 : OJ
=RData [n-1) [7 : 0118 : 01
=RData Inl [7 : 01 [8 : 01
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7.4 Write Transactions with Serial Address Packet
The following figure shows a memory space write transaction for a command which uses the serial address packet.
For a transaction which moves (n+ 1) octbytes of write data, the serial·address packet will be (4 x n) clock cycles
in length (recall that the low-order address bits for the first octbyte of write data come from the request packet).
Each serial address subpacket (each SAdr{i][1 0:3) field) is transmitted by the initiating device a time tSerialWrrteOffSet
clock cycles before the octbyte of write data to which it corresponds. This means that the serial address packet
will move with the write data packet, with a constant offset.
•
tScrlillWnteOffSet is the delay from the beginning of a serial address subpacket to the beginning of
the write data subpacket (octbyte) with which it is associated.
Note tha.! this offset interval is measured at the initiating device or the responding device; it will be the same at
either point since the serial address packet and write data packet are moving in the same direction - from initiating
device to responding device.
Figure 7-4. Write Transaction with Serial Address Packet
Clock
Cycles
BusEn BusCtrl
Bus Data [8 : 0]
~----------------------------------------------
SAdr
Request
111
110: 31
tAckDe
'~l
t
-
~
tWn'eoelav
Data [0] [7 : 0] [8 : 0]
=WData [0] [7 : 0] [8 : 0]
Data (1] [7: 0] (8: 0]
=WData [1] [7: 0] (8: 0]
SAdr
[n-1]
(10: 3]
-
I
SAdr
[n]
(10: 3]
tSCII.1IWlllcOIf
Data [n-1] [7: 0] [8: 0]
Data [n] (7 : 0] [8 : 0]
.+
=WData [n] [7 : O[ [8 : 0]
'tPostRegWrileOel,ay Or tPostMemWfltCOd,1V
I
I
288
=WData (n-1] [7 : 0] [8: 0]
Next transaction to same device
Next transaction to different device
~
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7.5 Read Transactions with Serial Control Packet
The following figure shows a memory space read transaction for a command which uses the serial control packet.
This packet is used to terminate a transaction before the (CV+ 1) octbytes of ruau data have been transferred, where
CV is the value of the Count[7:3] Field when interpreted as an unsigned, five Ilit integer. In the example shown,
the read data is terminated after (n) octbytes have been transferred.
The serial control packet is transmitted by the initiating device a time
t~;"",,"(,.,HiOIiSCI
clock cycles before the end
of the last read data oct byte which is transmitted by the responding device.
The serial control packet is also constrained to lie entirely outside the tActWII,i'td.,y interval, as shown in the figure,
in order to avoid interference with the acknowledge packet which is being returned by the responding device.
Violation of this constraint will produce undefined (Unde!) results. The detailed functional description is provided
in "Rambus DRAM user's manual (Reference Manuall".
Figure 7-5. Read Transaction with Serial Control Packet
Clock
BusEn BusCtrl
Bus Datil 18 : 01
------------------------
Cycles
-----------------
Request
-r-
I--:--:-
l~ctO'~Y
lAck
._--
tRei3dDelay
tAckWlndOel ay
The serial contra I
packet must not Ii e
inside the acknowledg e
window
Data 10J [7 : OJ [8 : OJ
=RData [OJ [7 : OJ 18 : OJ
...
.-
....
-'--
SCtrl
17: 01
Datil /n-:ll II : OIIB : 01
=RData [n·31 [7 : OJ [8 : 01
tScflatRcadOffS el
Data In-21 17 : 01 [8 : 01
=RData [n-2J [7 : 01 [8 : OJ
Data In-lJ [7 : 01 [8 : 01
=RData [n-1I17 : 01 18 : OJ
..
-'--
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7.6 Write Transactions with Serial Control Packet
The following figure shows a memory space write transaction for a command which uses the serial control packet.
This packet is used to terminate a transaction before the (CV+ 1) oct bytes of write data have been transferred, where
CV is the value of the Count[7:3] field when interpreted as an unsigned, five bit integer. In the example shown, the
write data is terminated after (n) oct bytes have been transferred.
The sefial control packet is transmitted by the initiating device a time tSenalWnteOffSet clock cycles before the ·end
of the last write data oct byte which is transmitted by the initiating device.
Note that this offset interval is measured at the initiating device or the responding device; it will be the same at
either since the serial address packet and write data packet are moving in the same direction - from initiating device
to responding device.
The serial control packet is also constrained to lie entirely outside the tAckWinDelay interval, as shown in the figure,
in order to avoid interference with the acknowledge packet which is being returned by the responding device.
Violation of this constraint will produce undefined (Undef) results.
Figure 7-6. Write Transaction with Serial Control Packet
C:lock
Cycles
BusData [8 : 01
BusEn BusCtrl
Request
tAckDelay
1
v
-ML
Data (0) [7 : 0) (8 : 0)
=WData (0) [7 : 0) [8 : 0)
Data (1) (7 : 0) (8 : 0)
=WData (1) (7 : 0)18: 0)
tAckWlndDe lay
-
The serial contr01
packet must not lie
inside the acknowledg e
window
-
--
-
SCtrl
17: 0)
Data (n-2)17 : 0)18 : 0)
=WData (n-2) [7 : 0) (8 : 0)
Data [n-l) (7 : 0)18: 0)
=WData In-1I17 : 0)18 : 01
tSCrI.llWrlteO flSet
-
..
-
1
tPQS1MemWriteDeiav
I
I
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Next transaction to same device
Next transaction to different device
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8. Nack Acknowledge Response
8.1 Retry and Miss Latency
If a responding device returns a Nack acknowledge packet, then no read or write data packet is transacted.
The current transaction is complete at the end of the acknowledge window. It will be necessary to wait for
an interval oftime (called a tAETAY interval) before resubmitting the transaction. The following figure" illustrates
this case.
Figure 8-1. Nack Acknowledge Response
Clock
Cycles
g
BusEn BusCtrl
BusData 18 : 01
; .~....
".
',/'
Transaction
Nack Acknowledge Response
tRetrySensedCIC<.I,1
or
tRetrySensedDlrty
or
tRetryRefresh
tReadMI'l'>
or
tWnteMlss
tReadHlt
or
Transaction
Okay Acknowledge Response
tWnleHl1
Read Data or Write Data Packet
Once the tAETAY interval has elapsed, the transaction may be restarted by the initiating device, and the
RDRAM will return an Okay acknowledge packet and the data packet will be transferred. An RDRAM will Nack
any other transactions which are issued during the tAETAY interval.
Two miss latency parameters may be derived with the following equations:
=tAETAY + tAeadHit
(Eq 8-1)
tWriteMiss = tAETAY + tWriteHit
(Eq 8-2)
tAeadMiss
where tAETAY = {tAetrySensedClean, tAetrySensedDirty, tAetryAefresh}. The tAeadMiss and tWriteMiss parameters are the time from
the beginning of the original (Nacked) request packet to the beginning of the data packet which is eventually
transferred.
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8.2 tRETRV Interval
8.2.1 Retry Due to RowMiss
If an initiating device requests a region of memory space in -an RDRAM slave which is not currently held
in the RowSenseAmpCache, the RDRAM will respond with a Nackacknowledge packet., The RDRAM will then
begin a RowMiss operation to get the proper row into the RowSenseAmpCache. During the RowMiss,ttie
RDRAM will Nack any request it is given. When the RowMiss is complete, the new row may be accessed.
Each bank has a Valid flag and a Dirty flag for its Row register. After reset, both are zero. After a RowMiss
has caused a new row to be placed into the RowSenseAmpCache, the Row register contains its row address
and the Valid flag is set to a one. If the RowSenseAmpCache contents are modified with a memory write
transaction, the dirty flag will be set. These flags are not directly accessible to initiating devices.
A subsequent RowMiss will cause the old row to be written back to the bank (if it was dirty and an explicit
restore was not forced with the Close bit in the request packet) and a new row to be placed into the
RowSenseAmpCache. The time required for this is called the tRETRYtime, and is added to the normal read and
write hit latency times, as shown in the preceding figure. These times are given by the following equations.
The component parameters are shown in a subsequent table. All ofthese tRETRY intervals correspond roughly
to the cycle time parameter tRC of a conventional page mode DRAM. This is because RDRAMs use CAS-type
accesses for all memory read and write transactions.
After a new row is sensed and placed into the RowSenseAmpCache, a final interval tRowlmprestore is used to
restore the row in core back to its original state. This is necessary because the DRAM sense operation is
destructive. This interval is not in the critical timing path, and is performed in parallel with a subsequent data
transfer. It can extend a subsequent retry operation.
There are two tRETRY equations for the IBM RDRAM:
tRetrySensedClean
=
+ tRowPrecharge + tRowSense
(Eq 8-3)
+ tRowExprostore + tRowPrecharge + tRowSense
(Eq 8-4)
tRowOverHcad
tRetrySensedDirty = tRowOvcrHoad
The detailed functional description is provided in "Rambus DRAM user's manual (Reference Manua!)".
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8.2.2 Retry Due to Pending Burst Refresh
In a IBM RDRAM, a refresh burst will also restore the currently accessed row if it is dirty. This requires
a tRowExprestore interval. If the row is clean, this interval is not required. A burst of four rows are precharged/
sensed/restored (using the tRowlmprestore interval), and the current row is precharged/sensed so the RDRAM is
left with its RowSenseAmpCache state unaltered (except the row's dirty flag will be cleared):
tRetryRefresh =
(tRowOverHead + tRowExprestore Note 1 + 2tRowPrechargo Note 2 + tRowSense)
+ 4 (tRowOverHead + tRowlmprestoro + 2tRowProchargo Noto 2 + tRowSense)
(Eq 8-5)
When a transaction initiates a manual burst refresh in an RDRAM (transaction "A" in the figure below), the
RDRAM will Nack all further transactions directed to in during the tRetryRufr",.h interval after. No information
from these Nackedtransactionswill be retained after the tRetryRefresh interval. After thetRetryRefresh interval, transactions
will be handled in a normal fashion. The detailed functional description is provided in "Rambus DRAM user's
manual (Reference Manual)".
Notes 1.
2.
This term is not present if the current row is clean.
This term is present twice in each cycle because the tRowPrecharge interval is also used to ensure
that a minimum delay between restore operations is met.
Figure 8-2. Transaction Holdoff Due to Burst Refresh
Clock
Cycles
~
~
Bus Data 18 : OJ
BusEn Busetrl
----------------------
.~;j...
..
Transaction A-Start Manual Burst Refresh
Okay Acknowledge Response
§
tRetryAefresh
Transaction B
Nack Acknowledge Response
!
~
Transaction B
Normal Response
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8.3 Retry Component Intervals
The tRETRY intervals are built from the tRowOverHead, tRowPrecharge, tRowSense, tRowlmprestore, and tRowE.prestore intervals.
All five intervals are measured in tCYCLE units, and thus scale with the clock frequency.
The tRowOvorHcad interval consists of the RowMiss state machine overhead. The remaining four intervals
represent the width of intervals used for timing core operations. These core operations have minimum times .
measured in nanosecond units (this is shown in the "core timing(ns)" columns in the table below). The four
intervals are composed of a fixed part and a variable (programmable) part. Ifthe clockJrequency is reduced,
the variable part may be reduced so the sum of the fixed and variable parts remain greater than or equal to
the minimum core operation time (in nanoseconds).
Table 8-1. Retry Components
Fixed ,Part (overhead)
Delay
tCYCLE Units
Variable Part Note
(4 ns)
Parameter
tRowOvcrHllfld
r-
..
tn(IWPfccharge
tRowSense
tRowlmprestore
6
Row overhead
r---
-
-_.
4
RowPrecharge[4:0]
1
RowSense overhead
4
RowSense[4:0]
7
RowlmpRestore overhead 4
with tCYCLE
= 4ns
24
20
44
56
10
RowExpRestore overhead 4
-----
RowExpRestore[ 4:0]
core timing (ns)
nfa
RowPrecharge overhead
RowlmpRestore[4:0]
tRowExprestore
IBM RDRAM
r--· .
and
32
4
Note The variable part is programmed into the indicated field of the Raslnterval register.
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9. AddressMapping
The address space decoding logic contained in a IBM RDRAM is shown in the following figure. The initiating
device places a 33 bit physical octbyte address Adr[35:3) on the Channel. This address is received by the
RDRAM slave. The AddressSelect[1][ 1:0). [0][7:1) control register allows individual bits of the Adr[28:20) and
Adr [19:11) fields to be swapped to produce the AdrS[28:20) and AdrS(19:11) fields. The Adr[35:29) and
Adr[10:3) fields pass through unaltered to the AdrS[35:29) and AdrS(10:3) fields. The figure shows the case
when AddressSelect[O][7:1J.[1][1:0) = 111111111. and the two ninc bit address fields are exchanged. The
detailed functional description is provided in "Rambus DRAM user's manual (Reference ManuaU".
Figure 9·1. AddressMapping Hardware
35343332313029282726252423222120191817161514131211109 B 7 6 543
Adr [35: 21
Address in Request Packet
C....:I_7_:,..01:..........J
'--_";""'-r:::"""..J...._ _':'-'''''':''_--1._ _.....:...,,..-:''''''_.l...-_
8
AddressSelect [0117 : 11. III [1 : 01
= 111111111
AdrS [35: 21
Address used by RDRAM Core
L......::-:-:-::-:-:-:-:-::-:~:--::-:-..:-____--1._ _~__:......_.l...-__C....:[....:7_:....:01:..........J
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10. Electrical Characteristics (Preliminary)
Absolute Maximum Ratings
Symbol
Parameter
MIN.
MAX.
Unit
VI,ABS
Voltage applied to any RSL pin with respect to GND
-0.5 .
Voo+0.5
V
VI,TTL,ABS
Voltage applied to any TTL pin with respect to GND
-0.5
Voo+0.5
V
VOO,ABS
Voltage on VOO with respect to GND
-0.5
VOO,MAX+ 1.0
V
TOPT
Operation temperature
0
+70
·C
TSTORE
Storage temperature
-55
+125
·C
Caution
Note
1
The following table represents stress ratings only, and functional operation at the maximums
is not guaranteed. Extended exposure to the maximum ratings may affect device reliability.
Furthermore. although devices contain protective circuitry to resist damage from static electric
discharge, always take precautions to avoid high static voltages or electric fields.
Note 1 This parameter apply at the status of using 50% Rambus channel by Read or Write and a transverse
nir flow greater than' .5m/s maintained.
Thermal Parameters
Symbol
Parameter
TJ
Junction operating temperature
ElJC
Junction-to-Case thermal resistance
r----
MIN.
MAX.
Unit
100
·C
5
·C/W
MAX.
Unit
Capacitance
Symbol
296
Parameter
MIN.
CliO
Low-swing input/output parasitic capacitance
2
pF
CI,TTL
TTL input parasitic capacitance
8
pF
NEe
).lPD488170L
Power Consumption
MAX.
Unit
-A45
110
rnA
-A50
125
-A45
330
-A50
350
Read Operation Current
-A45
440
(Burst Length = 256)
-A50
480
Write Operation Current
-A45
435
-A50
460
Parameter
Mode
ICCl
Active Current
IcC2
Standby Current
Icc3
IcC4
Caution These do not include the
10L
MIN.
rnA
rnA
rnA
current passing through the low-swing pins to ground.
Recommended Operating Conditions
Symbol
Parameter
Vee, VeeA Supply voltage
MIN.
MAX.
Unit
3.15
3.45
V
VREF
Reference voltage
1.95
2.15
V
Vswing
Input voltage range
1.0
1.4
V
Vll
Input low voltage
VREF-0.7
VREF-0.5
V
VIH
Input high voltage
VREF+0.5
VREF+0.7
V
Vll, TTL
TTL input low voltage
-0.5
+0.8
V
VIH, TTL
TTL input high voltage
2.0
Vee+0.5
V
DC Characteristics (Recommended operating conditions unless otherwise noted)
MIN.
MAX.
Unit
IREF
Symbol
VREF current
Parameter
VREF=Maximum
Conditions
-10
+10
pA
IOH
High level output current
O~VouT~Vee
-10
+10
pA
IOl
Low level output current
VouT=1.6 V
25
rnA
II, TTL
TTL input leakage current
O~VI, TTL~Vee
-10
+10
pA
VOH, TTL
High level TTL output voltage
IOH, TTl=-0.25 rnA
2.4
Vee
V
VOL, TTL
Low level TTL output voltage
IOL, TTL=1.0 rnA
0
0.4
V
297
NEe
,uPD488170L
Recommended Timing Conditions
Symbol
Parameter
MIN.
MAX.
Unit
200
Jls
0.3
0.7
ns
-A45
4.45
6
ns
-A50
4
6
ns
tCYCLE/2
tCYCLE/2
ns
tPAUSE
Pause time after Power On
tcn, tcr
TxClk and RxClk input rise and fall times
tCYCLE
TxClk and RxClk cycle times
tTICK
Transport time per bit per pin (this timing interval is
synthesized by the RDRAM's internal clock generator)
tCH, tCL
TxClk and RxClk high and low times
47%
53%
tCYCLE
tTR
TxClk-RxClk differential
0.25
0.7
ns
tso
Sln-to-SOut propagation delay
50
ns
to
1----ts
1---III
TxClk-to-Data/Control output time
tCYCLE/8+0.05 tCYCLE3/8-0.05
ns
Data/Control-to-RxClk setup time
tCYCLE/4-0.05
ns
RxClk-to-Data/Control hold time
tCYCLE/4-0.05
IREf
Refresh interval
tLOCK
RDRAM internal clock generator lack time
ns
32
500
ms
tCYCLE
Transaction Timing Characteristics
Symbol
tPostRegWrilt!Dday
Parameter
Delay from the end of the current transaction to the
MIN.
Unit
6
tCYCLE
4
tCYCLE
2
tCYCLE
12
tCYCLE
8
tCYCLE
beginning of the next transaction if Ihe current transaction
is a write to register space and Ihe next transaction is
made to the same device.
Use zero delay if the next transaction is to a different
device.
tPostMemWritcDelay
Delay from the end of the current transaction to the
beginning of the next transaction if the current transaction
is a write to memory space and the next transaction is
made to the same device.
Use zero delay if the next transaction is to a different
device.
tPostMemReadDelay
Delay from the end of the current memory read transaction to the beginning of the next transaction.
tSerialReadOffSet
Delay from the beginning of a serial address subpacket or
serial control packet to the beginning of the read data
subpacket (octbyte) with which it is associated.
tSerialWriteOffSet
Delay from the beginning of a serial address subpacket or
serial control packet to the beginning of the write data
subpacket (octbyte) with which it is associated.
298
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,uPD488170L
Data and Transaction Latency Characteristics
Symbol
Parameter
MIN.
Unit
Notes
tReadDelay
Delay from the end of a read request packet to the
7
tCYCLE
1
1
tCYCLE
2
beginning of the read data packet.
tWriteDelay
Delay from the end of a write request packet to the
beginning of the write data packet.
Notes 1. tReadDelay is programmed to its minimum value.
2. tWriteDelay is programmed to its minimum value.
Hit, Retry and Miss Delay Characteristics
Symbol
tRead Hit
Parameter
MIN.
Unit
Notes
Start of request packet to start of read data packet for
10
tCYCLE
1
4
tCYCLE
1
22
tCYCLE
2
30
tCYCLE
2
Clean
191
tCYCLE
2
Dirty
199
32
tCYCLE
3
26
tCYCLE
3
row hit (Okay).
-
.~
Start of request packet to start of write data packet for
tWriteHit
row hit (Okay).
tRetrySensedClean
-
.. -
Start of request packet for row miss (Nack) to start
of request packet for row hit (Okay).
The previous row is unmodified.
tAetrySensedDirty
Start of request packet for row miss (Nack) to start
of request packet for row hit (Okay).
The previous row is modified.
tRetryRefresh
tRead Miss
Start of request packet for row miss
(Nack) to start of request packet for row
hit (Okay).
Start of request packet for row miss (Nack) to start of
Read Data packet for row hit (Okay).
tWriteMiss
Start of request packet for row miss (Nack) to start of
Write Data packet for row hit (Okay).
Notes
1. Programmable
2. tRowExprestore, tPrecharge, and tsense are programmed to their minimum value.
3. Calculated with tRetrySensedCleen(MIN).
299
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.uPD488170L
Rise/Fall Timing Chart
V R.elk, VTxClk
__ mm __ uumumum_mmmm __ mmu[_u
~m
V,HIM,NI
___
VILIMAXI
-------
--
~----------------------------------------------.
tCF
tCR
Clock Timing Chart
(CYCLE
tCYCLE
VRClk
VREF-
Receive Data Timing Chart
Vnclk
VREF-
VD<1laOut
or
VControlOut
300
VREF-
\cYCLE
tCYCLE
NEe
,uPD488170L
Transmit Data Timing Chart
tCYCLE
tCYCLE
or
VCllI1lrl)IOllt
Serial Configuration Pin Timing Chart
VSln
)r(I: '•. "~L!MAXI
VSW, TTL -
,I
Iso (MIN I
VSOut
VSln
4-
--------------------~
------------------
------------------~
~---------------
VSW, TIL -
VSW, TTL -
t5DO
VSOUI
VSW. TTL -
Remark Vsw,
TTL
= 1.5 V
301
.uPD488170L
11. Package Drawings
32 PIN PLASTIC SVP (11 X 25)
A
--;--K
Detail of
NOTE
:1' Each 1/0 lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
:1:
* Each support lead centerline is located within 0.18 mm (0.007 inch)
of its true position (T.P.) at maximum material condition.
ITEM
A
B
® - ®' part
~~
MILLIMETERS
INCHES
25.30 MAX.
11.0±0.1
0.996 MAX.
0.433±0.OO4
C
0.24±0.06
0.009~8:88~
D
L
0.13
0.65 (T.P.)
2.575 MAX.
0.10
0.52±0.06
0.9 (T.P.)
23.20
1.25
11.80 MAX.
0.005
0'.026 (T.P.)
0.102 MAX.
0.004
0.020±0.002
0.035 (T.P.)
0.913
0.049
0.465 MAX.
M
0.5±0.1
0.020~8:88~
N
3.70 MAX.
0.146 MAX.
P
0.17~8:8~g
0.007±0.001
Q
0.9±0.25
0.035~8:816
R
3 0 + 70
-3'
3 0 + 70
-3'
S
T
1.90 MAX.
0.18
0.075 MAX.
0.007
E
F
G
H
J
K
S32VN-65-9
302
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.uPD488170L
72/36 PIN PLASTIC SSOP TYPE
~------------~R~------------~4-S
IT]
detail of lead end
++--------1---------1Il...
I.
A
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
.1
ITEM
MILLIMETERS
A
C
25.30 MAX.
2.575 MAX.
0.65 (T.P.)
0.996 MAX.
0.102 MAX.
0.026 (T.P.) .
0
0.24±0.06
0.009~g:g8~
E
0.25±0.05
0.01 o~g:gg~
F
1.6 MAX.
1.25
13.0±0.2
11.0+0.1
0.063 MAX.
0.049
0.512±0.008
0.433±0.004
B
G
H
INCHES
1.0±0.2
K
0.17~8:8~~
O.OOHO.OOl
L
0.5±0.1
0.020~8:88~
M
N
0.13
0.10
0.005
0.004
Q
0.65 (T.P.)
22.75
1.275 MAX.
0.026 (T.P.)
0.896
0.051 MAX.
P32G6-65A
R
S
303
NEe
(MEMO)
304
,uPD488170L
PRELIMINARY DATA SHEET
~EC/
MOS INTEGRATED CIRCUIT
jlPD488130L
16M-BIT Rambus DRAM
1M-WORD X 8-BIT X 2-BANK
Description
The 16-Megabit Rambus™ DRAM (RDRAMTM) is an extremely-high-speed CMOS DRAM organized as 2M
words by 8 bits and capable of bursting up to 256 bytes of data at 2 ns per byte. The use of Rambus Signaling
Logic (RSL) technology makes this 500 MHz transfer rate achievable while using conventional system and
board design methodologies. Low latency is attained by using the RDRAM's large internal sense amplifier
arrays as high speed caches.
RDRAMs are general purpose high-performance memory devices suitable for use in a broad range of
applications including main memory, graphics, video, and any other application where high-performance
and low cost are required.
Detailed information about product features and specifications can be found in the following document.
Please make sure to read this document before starting design.
Rambus DRAM user's manuallReference Manual) : IEU-1401
Rambus and RDRAM are trademarks of Rambus Inc.
Features
• Rambus Interface
• 500 MB/sec peak transfer rate per RDRAM
• RSL interface
• Synchronous protocol for fast block-oriented transfers
•
Direct connection to Rambus ASICs, MPUs, and Peripherals
• 40 ns from start of read request to first byte; 2 ns per byte thereafter
• Features for graphics include random-access mode, write-per-bit and mask-per-bit operations
•
Dual 2K-Byte sense amplifiers act as caches for low latency accesses
•
Multiple power-saving modes
• On-chip registers for flexible addressing and timing
•
Low pincount-only 15 active signals
• Standardized pinout across multiple generations of RDRAMs
• 3.3 volt operation
Ordering Information
Part Number
Clock Frequency
Operation Voltage
250MHz
3.3±0.15 V
JLPD488130L VN-A45
225M Hz
3.3±0.15 V
32-pin plastic SVP (11 x 25)
JLPD488130LG6-A50
250MHz
3.3±0.15 V
72/36-pin plastic SSOP type
JLPD488130LG6-A45
225M Hz
3.3±0.15 V
72/36-pin plastic SSOP type
JLPD488130LVN-A50
Package
32-pin plastic SVP (11 x 25)
The information in this document Is subject to change without notice.
0-3656 (Japan)
305
NEe
,uPD488130L
Pin Configuration (Marking Side)
32-pin plastic SVP 111 x 25)
72/36-pin plastic SSOP type
Voo
1
GND
2
BusData8
3
GND
4
BusData7
5
NC
6
BusEnable
7
Voo
8
BusData6
9
GND
306
10
BusData5
11
VOilA
12
RxClk
13
GNDA
14
TxClk
15
Voo
16
BusData4
17
GND
18
BusCtrl
19
Sin
20
VREF
21
SOut
22
BU5Dala3
23
GND
24
BusDala2
25
NC
26
BusDatal
27
GND
28
BusDataO
29
NC
30
GND
31
Voo
32
'1:: '1::
"II "II
C C
..
iw i..w
o 0
r- rGl <
en 2
BusData 0 - BusData 8
: Bus Data (Input/Output)
RxClk
: Receive Clock (Input)
TxClk
: Transmit Clock (Input)
VREF
: Logic Threshold Voltage (Input)
BusCtrl
: BusCtrl (Input/Output)
BusEnable
: BusEnable (Input)
Voo. VOOA
: Power Supply
GND. GNDA
: Ground
Sin
: Serial Input (Input)
SOut
: Serial Output (Output)
NC
: No Connection
NEe
pPD488130L
Block Diagram
DRAM Array - Bank 0
DRAM Array - Bank 1
MDReg [7 : O[ [8 : 0]
Control Logic
Primary or Secondary Channel
307
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,uPD488130L
1. Pin Function
Signal
BusData [8:0)
I/O
Description
I/O
Signal lines for request, write data, and read data
packets. The request packet contains the address,
operation codes, and the count of the bytes to be
transferred. This is a low-swing, active-low signal
referenced to VREF.
BusData [8) is "Don't Care" in data packet of the
accessing memory space.
RxClk
I
Receive clock. Incoming request and write data
packets are aligned to this clock. This is a lowswing, active-low signal referenced to VREF.
TxClk
I
Transmit clock. Outgoing acknowledge and read
packets are aligned with this clock. This is a lowswing, active-low signal referenced to VREF.
I
Logic threshold voltage for low swing signals.
-VIII:!'
BusCtrl
BusEnable
I/O
Control signal to frame packets, to transmit part of
the operation code, and to acknowledge requests.
Low-swing, active-low signal referenced to VREF.
I
Control signal to enable the bus. Long assertions of
this signal will reset all devices on the Channel. This
is a low-swing, active-low signal referenced to VREF.
Voo, VOOA
+3.3 V power supply.
supply.
GND,GNDA
Circuit ground. GNDA is a separate analog ground.
Sin
I
VOOA
is a separate analog
Initialization daisy chain input. TTL levels. Active
high.
SOut
308
0
Initialization daisy chain output. TTL levels. Active
high.
NEe
,uPD488130L
2. Rambus System Overview
A typical Rambus memory system has three main elements: the Rambus Channel, the RDRAMs, and a
Rambtls Interface on a controller. The logical representation of this is shown in the following figure.
Figure 2-1. Logical Representation
Rambu s
Channe I
Master
Controller
DRAM
Core
Rambus Interface
RDRAMs
(Rambus
Channel
Slaves)
Rambus Interface
'f
Rambus Channel
=8 bits every 2 ns
The Rambus Channel is a synchronous, high-speed, byte-wide bus that is used to directly connect
Rambus devices together. Using only 13 high-speed signals, the Channel carries all address, data, and
control information to and from devices through the use of a high level block-oriented protocol.
The Rambus Interface is implemented on both master and slave devices. Rambus masters are the only
devices capable of generating transaction requests and can be ASIC devices, memory controllers, graphics
engines, peripheral chips, or microprocessors. RDRAMs are slave devices and only respond to requests
from master devices.
The following figure shows a typical physical implementation ofa Rambus system. It includes a controller
ASIC that acts as the Channel master and a base set of RDRAMs soldered directly to the board. An RSocket™
is included on the Channel for memory upgrade using RModule™ expansion cards.
Figure 2-2. A Rambus System Example
Memory Modules
________ Secondary Channels
Socket for
Expansion
\
RDRAM
\
!
· 1 to 320 RDRAMs per system
· 28 traces per Channel
· Controlled impedance design
309
NEe
yPD488130L
3. Rambus Signaling Logic
RSL technology isthe key to attaining the high data rates available in Rambus systems. By employing
high quality transmission lines, current-mode drivers, low capacitive loading, low-voltage signaling, and
precise clocking, systems reliably transfer data at 2 nanosecond intervals on a Rambus Channel with signal
quality that is superior to TTL or GTL-based interfaces.
All Rambus Interfaces incorporate special logic to convert signals from RSL to CMOS levels for internal
use. In addition, these interfaces convert the Channel data rate of one byte every 2 nanoseconds to an
internal data rate of8 bytes every 16 nanoseconds as shown in the following figure. Although the bandwidth
remains the same, the use of a wide internal bus eases internal timing requirements for chip designers.
Figure 3-1. Converting the Channel Data Rate
II
BankS
Bank7
Bank6
BankS
I
Bank4
Bank3
Bank!
Bank2
RORAM4
RoMM3
Sense amp cache page 1
II"~~
Sense amp cache pago 2
Address Comparators
~kll1gl
no MM2
nDMM
Byteh
""tvi;g
~
~
~
~
~
By to/!
Rambus Channl"
8 bits every 2 no;
"lbICI"IOI'I'lhl
Rambus Interface een
-Mac rocell in Embedded
ArrilVand Standard
C~' libraries
-Converls Rambus
Cha nncls",-"II ~Wlng
.,
nals 10 ASIC coro
com pal/blo CMOS Iovels
-ConYCrtsBblt50Ycry
2n. loG4 bits 1)(2)
everv ISns
-Contalns PlLs
...
·Allvendors cells
100% compatible
310
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,uPD488130L
4. Register Space Map
The following table summarizes the registers included in all 16M RDRAMs.
Table 4-1. Registers Space Map
Adr[20:10]
Adr[9:2]
Device Type[3:0][8:0]
xx ...xx
00000000
0
Deviceld[3:0][8:0)
xx ...xx
00000001
1
Register Name
Register Number
Delay[3:0][8:0)
xx ...xx
00000010
2
Mode[3:0][8:0)
xx ... xx
00000011
3
Reflnterval[3:0][8:0]
xx ... xx
00000100
4
RefRow[3:0][8:0)
xx ... xx
00000101
5
Raslriterval[3:0][8:0)
xx ... xx
00000110
6
MinlntervaI[3:0](8:0)
xx ...xx
00000111
7
AddressSelect[3:0][8:0)
xx ...xx
00001000
8
DeviceManufacturer[3:0][8:0]
xx ...xx
00001001
9
Undefined
xx ... xx
0000101x
10-11
Undefined
xx, .. xx
000011xx
12-15
Undefined
xx ... xx
0001xxxx
16-31
Undefined
xx ... xx
001xxxxx
32-63
Undefined
xx ... xx
01xxxxxx
64-127
Row[3:0][8:0)
xx ... xx
10000000
128
Undefined
xx ... xx
10000001
129
Undefined
xx ... xx
1000001x
130-131
Undefined
xx ... xx
100001xx
132-135
Undefined
xx ... xx
10001xxx
136-143
Undefined
xx ...xx
100 1xxxx
144-159
Undefined
xx ...xx
1010xxxx
160-175
Undefined
xx ... xx
1011xxxx
176-191
Undefined
xx ...xx
1100xxxx
192-207
Undefined
xx ...xx
1101xxxx
208-223
Undefined
xx ... xx
1110xxxx
224-239
Undefined
xx ... xx
1111xxxx
240-255
(1) Device Type Register
This register specifies RDRAM configuration and size.
Device Type (0) (2)=0: This means that the RDRAM is 8-bit wide.
(2) Deviceld Register
This register specifies RDRAM base address.
311
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,uPD488130L
(3) Delay Register
This register specifies RDRAM programmable CAS delay values.
(4) Mode Register
This register specifies RDRAM programmable output drive current.
15) Reflnterval Register
This register specifies RDRAM programmable refresh interval.
Reflnterval Register is used to time the refresh interval for devices which require refresh.
(6) RefRow Register
This register specifies RDRAM refresh row and bank address.
The Ref Row register contains read-write fields. It is used to keep track of the bank and row being
refreshed. Normally this register is only read or written for testing purposes. The fields are aliased in
the following way:
RowField[7:1] equals RefRow[0][7:1]
RowField[9:8] equals RefRow[2][ 1:0]
BankField[3] equals RefRow[1][3]
(7) Raslnterval Register
This register specifies RDRAM programmable RAS delay values. The Raslnterval Register contains four
write-only fields. When a rowmiss occurs, or when a row is being refreshed during a burst refresh
operation, it is necessary for the control logic of an RDRAM to count the appropriate number of clock
cyclos (tCYCLE) for four intervals. This is done with a counter which is loaded successively with three
values from the Raslnterval Register. This counter is not available for read access and must be tested
indirectly.
(8) Minlnterval Register
This register specifies RDRAM refresh and powerdown control.
This register provides the minimum values for three time intervals for framing packets.
The time intervals are specified in clock cycle (tCYCLE) units.
(9) AddressSelect Register
This register specifies RDRAM address mapping.
(10) DeviceManufacturer Register
This register specifies RDRAM manufacturer information.
This register specifies the manufacturer of the device. Additional bits are available for manufacturer
specific information, e.g. stepping or revision numbers.
(11) Row Register
This register specifies RDRAM current sensed row in each bank.
The detailed functional description is provided in RDRAM Reference Manual.
312
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,uPD488130L
5. Packet Formation
5.1 Packet Summary
The following table summarizes the transmit/receive functionality for the different packet classes.
Table 5-1. Transmitting/Receiving Devices for Packet Types
Packet Type
Initiating Devices
Request Packet
Transmit
Acknowledge Packet
Receive
---
/lPD488130L
..
Receive
_- --Transmit
--
--
Read Data Packet
Receive
Transmit
Write Data Packet
Transmit
Receive
Serial Address Packet
Transmit
Receive
Serial Control Packet
Transmit
Receive
Serial Mode Packet
Transmit
Receive
--
----
5.2 Request Packet
The request packet format is shown in the following figure.
Figure 5-1. Request Packet Format
Dovico Pin,;
-
~ Bu-s~
Clock
Cycle
Number
: Enablo:
,- - - - - --,
:
(0)
I
even
-:. B~5- - :. i3Gs: - ~ -Bus:- -:- B~s- - ~ -B~'~;- : a-us: ~ - B~s- - ~ -Bu-s: -:- Bus·- ~ -B~s: -:
I
I
I
Gtrl
Start
Op
Op
Op
(3J
10)
1-------1
I
I
IL
I
I
I
~
I
(0)
odd
______
•I
(1)
Data: Data : Data : Data : Data : Data : Data : Data : Data :
_LIBL .: . .r!L.~.l~I .. ~ _~5L~ ..[~I.. ~ .PL.:. . L2L~. J!I.. ~.!01. ~
:
11)
I
I
I
even J
______
(1)
:
odd
I
I
1-------1
I
(2)
even
I
L------ t
I
12)
o9~
:___ __ :
Time
Count
[1 :01
Adr
[1 :0)
This means that this pin is not used by this packet. If it is not used
by another packet. it is pulled to a logic zero value.
The vertical axis in all packet figures in the following sections shows time in units of clock cyc[es. with each
clock cycle broken into even and odd bus ticks. The timing is relative. measured from the beginning of the
packet.
313
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,uPD488130L
5.2.1 Start Field
A device should start framing a request packet when it sees this bit asserted to a logical one and it is not
looking for an acknowledge packet nor framing an earlier request packet.
5.2.2 Op[3:0], OpX[1:0] Fields
The command opcode also determines which packets (in addition to the request packet) will form the
transaction. A detailed functional description of the actions that an RDRAM takes for each implemented
command is provided in "Rambus DRAM user's manual (Reference Manual)". The following table summarizes
the functionality of each subcommand:
Table 5-2. Subcommand Summary
SubCommand
Description
Rseq
Read sequential data from memory space.
Rnsq
Reod non·sequential (random·access) data from memory space.
Wseq
Write sequential data to memory space.
Wnsq
Write non-sequential (random·access) data to memory space.
Wbns
Write non·sequential (random-access) data to memory space with non-contiguous byte masking.
Npb
Write data is from data packet. There is no bit mask.
Dpb
Write data is from data packet. The bit mask is in the MDReg.
Bpb
Write data is from data packet. The bit mask is also from the data packet.
Mpb
Write data is from MDReg. The bit mask is from the data packet.
Rreg
Read sequential data from register space.
Wreg
Write sequential data to ragister space.
WregB
Broadcast write with no Okay acknowledge permitted.
Alt
Alternate command (same function as the primnry command - intended for use in future shared
---
--
-
--
---
memory multiprocessor systems).
The memory read commands are formed using the Rseq and Rnsq subcommands to select sequential or
nonsequential (random) access. The Alt and "null" subcommands select between two equivalent command
sets ("null" means no subcommand). The "Alt" subcommands are reserved for use in future shared memory
multiprocessor
system~.
RrrrAaa
Rrrr
Aaa
314
= {Rseq, Rnsq}
= {Alt, null}
NEe
,uPD488130L
The following table summarizes the available write commands and shows how they are formed from a 3x4
matrix of the Wwww and Bbb subcommands. The Alt and "null" subcommands have the same meaning as
in the memory read commands.
WwwwBbbAaa Wwww = {Wseq, Wnsq, Wbns}
Bbb = {Npb, Dpb, Bpb, Mpb}
Aaa = {Alt, null}
Table 5-3. Write Commands
Wwww subcommands
--- Bbb
subcommand
Wseq
(seqential-access
with contiguous
byte masking)
Wnsq
(non-sequentialaccess)
Wbns
(non-sequential-access
with non-contiguous-bytemaskinn)
Npb
WseqNpb
WnsqNpb
WbnsNpb
Dpb
WseqDpb
WnsqDpb
WbnsDpb
Mpb
WseqMpb
WnsqMpb
WbnsMpb
Bpb
WseqBpb
WnsqBpb
Not implemented
----
---
There are three Wwwwsubcommands. They control the accessing pattern and the use of non-contiguous
byte masking.
Wseq - octbyte blocks in the RDRAM core are accessed in sequential (ascending little-endien) address
order. Contiguous byte masking is controlled with the Adr[2:0] and Count[2:0) fields of the
req u est packet.
Wnsq - oct byte blocks in the RDRAM core are accessed in non-sequential address order.
The
addresses for the octbyte blocks within the sensed row come from serial address packets
which are received on the BusEnable pin.
The address order is arbitrary.
Wbns - octbyte blocks in the RDRAM core are accessed in non-sequential address order, as in the
Wnsq subcommand. In addition, byte masks are transmitted with the write data, permitting
arbitrary non-contiguous byte masking of this write data. The bytemask octbytes are not
included in the total octbyte transfer count; i.e. a Count[7:3] field of 31 implies 4 bitmask
octbytes and 32 write data octbytes, for a data packet size of 36 octbytes.
There are four Bbb subcommands. They select the type of bit masking to be applied to the write data.
Npb (no-per-bit) -
There is no bit mask applied to the write data. The MDReg is not used or modified.
Dpb (data-per-bit) - The MDReg is used as a bit mask, the write data comes from the data packet. The
same bit mask is used for each octbyte. This is also called persistent bit masking.
The MDReg is not modified.
315
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,uPD488130L
Mpb (mask-per-bit) - The bit mask comes from the data packet, the write data comes from the MDReg.
The same data is used for each octbyte. This is also called color masking. The
MDReg is not modified.
Bpb (both-per-bit) - The bit mask and the write data come from the data packet. The MDReg is not
used, but is modified as a side effect (the WwwwBpbAaa commands are
~sed
to load the MDReg for the WwwwDpbAaa and WwwwMpbAaa commands).
This is also called non-persistent bit masking.
The bitmask oct bytes are included in the total oct byte transfer count; i.e. a
Count[7:3) field of 31 implies 16 bitmask octbytes and 16 write data octbytes.
5.2.2.1 Op[3:O] and OpX[1:0] Fields for 16M RDRAM
The Op and OpX fields are summarized in the following table.
Table 5-4. Op[3:O] and OpX[1:0] Fields - Command Encodings
Op[3:0]
316
OpX[1:0]
= 00
OpX[1:0]
= 01
OpX[1:0]
= 10
OpX[1 :0]
= 11
0000
Rseq
Rnsq
Rsrv
Rsrv
0001
RseqAlt
RnsqAlt
Rsrv
Rsrv
0010
Rsrv
Rsrv
Rsrv
Rsrv
0011
Rsrv
Rsrv
Rsrv
Rsrv
0100
WseqNpb
WseqOpb
WseqBpb
WseqMpb
0101
WsoqNpbAlt
WseqOpbAlt
WseqBpbAlt
WseqMpbAlt
0110
Rreg
Rsrv
Rsrv
Rsrv
0111
Wrog
Rsrv
Rsrv
Rsrv
1000
WnsqNpb
WnsqOpb
WnsqBpb
WnsqMpb
1001
WnsqNpbAlt
WnsqOpbAlt
WnsqBpbAlt
WnsqMpbAlt
1010
Rsrv
Rsrv
Rsrv
Rsrv
1011
Rsrv
Rsrv
Rsrv
Rsrv
1100
WbnsNpb
WbnsOpb
Rsrv
WbnsMpb
1101
WbnsNpbAlt
WbnsOpbAlt
Rsrv
WbnsMpbAlt
1110
Rsrv
Rsrv
Rsrv
Rsrv
1111
WregB
Rsrv
Rsrv
Rsrv
NEe
,uPD488130L
The command opcode determines whether the other fields of the request packet are implemented (Imp)
or unimplemented (Unimp). This is summarized in the table below.
Table 5-5. 16M RDRAM Request Packet Fields - Imp or Unimp
Count[7:3]
Count[2]
Count[1:0]
Close
ReqUnimp[7:0]
Unimp(OO) Unimp(O.O)
Unimp(1)
Unimp(11)
Unimp(O)
Unimp(O.O)
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
Imp
Unimp(O.O)
Command
Adr[35:3]
Adr[2]
Adr[1:0]
Rsrv
Unimp(O.O)
Unimp(O)
Rseq
Imp
Imp
Imp
Rnsq
Imp
Imp
RseqAlt
Imp
RnsqAlt
WseqNpb
WseqDpb
Imp
Imp
Imp
Imp
Imp
Imp
WseqBpb
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqMpb
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqNpbAlt
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqDpbAlt
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqBpbAlt
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
WseqMpbAlt
Imp
Imp
Imp
Imp
Imp
Imp
Imp
Unimp(O.O)
Unimp(O)
Unimp(O.O)
Rreg
Imp
Imp
Unimp(OO) Unimp(O.O)
Unimp(1)
Unimp(11)
Wreg
Imp
Imp
Unimp(OO) Unimp(O.O)
Unimp(1)
Unimp(11)
Unimp(O)
Unimp(O.O)
WnsqNpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqDpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqBpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqMpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqNpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqDpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqBpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WnsqMpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsNpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsDpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsMpb
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WbnsNpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
Unimp(11)
Imp
Unimp(O.O)
WbnsDpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
WbnsMpbAlt
Imp
Unimp(O)
Unimp(OO)
Imp
Unimp(1)
Unimp(11)
Imp
Unimp(O.O)
WregB
Imp
Imp
Unimp(1)
Unimp(11)
Unimp(O)
Unimp(O.O)
Unimp(OO) Unimp(O.O)
317
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yPD488130L
5.2.3 Adr[35:0] Field
The Adr field is used as either a memory or register space address depending upon the OP[3:0) and OpX[1 :0)
fields. Devices extract a portion of the Adr field to match against their Deviceld register (ldMatch). thus
selecting the device to which the request is directed. The remainder of the Adrfield accesses the desired region
of the device's memory or register space. The memory read and write commands and the Rreg and Wreg
commandswill only take place ifthere is an IdMatch: The IdMatch criteria is ignored forthe WRegB commands,
with all responding devices performing the required actions.
The Rambus protocol uses quad byte resolution in the data packet for register space read and write
commands; i.e. one quad byte is the smallest data item that may be transferred. and all transfers are an integral
number of quadbytes. The Adr[35:2) field is the quadbyte address. The Adr[1:0) field is Unimp for these
commands. and should be driven with "00· by initiating devices.
The Rambus protocol uses octbyte resolution in the data packet for memory space read and write
commands; i.e. one octbyte is the smallest data item that may be transferred. and all transfers are an integral
number of octbytes. The Adr[35:3) field is the octbyte address.
Some commands use the Adr[2:0) field to specify contiguous byte masking. Referto "Rambus DRAM user's
manual (Reference Manuall".
5.2.4 Count[7:0) Field
The following table summarizes the transfer count ranges for 16M RDRAMs:
Table 5-6. Transfer Count Summary
Count Range
IlPD488130L
Maximum count for memory space
320ctbytes
Minimum count for memory space
1 octbyte
Maximum count for register space
1 quadbyte
Minimum count for register space
1 quadbyte
-----------
...
---
------------.---------
Register space read and write commands use a transfer count of one quadbyte. regardless of the Count[7:0]
field value.
Memory space read and write commands specify the number of octbytes to be transferred with the
Count[7:3] field. An offset-by-one-encoding is used so that ·00000· specifies one octbyte. ·00001" specifies
two octbytes. and so on up to "11111" which specifies thirty-two octbytes. The transfer count does include
the octbytes containing bitmasks (for commands using the Bpb subcommand). The transfer count does not
include the octbytes containing non-contiguous ByteMasks (for commands using the Wbns subcommand).
Some commands use the Count[2:0] field to specify contiguous byte masking. Refer to "Ram bus DRAM
user's manual (Reference Manuall".
Memory space transactions to RDRAMs are not allowed to cross internal row address boundaries within
the device. Attempts to do so have Undef (undefined) results. These row boundaries are at 2kbyte intervals
for 16M RDRAMs.
318
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,uPD488130L
5.2.5 Adr[2:0] and Count[2:0] Fields for Contiguous Byte Masking
An initiating device wishing to transfer an arbitrary number of contiguous bytes to a starting address on
an arbitrary byte boundary may do so with the Adr[2:0) and Count[2:0) fields for some of the commands. These
commands include:
RrrrAaa
WseqBbbAaa
The transfer count and starting address are given by:
MasterCount[7:0) specifies the number of bytes which the master device wishes to transfer.
Adr[35:0) specifies the starting byte address (this is the same as the Adr[35:0) field in the request
packet)
Where the convention used by the initiating device for the count is that Master-Count[7:0) = "00000000"
means one byte, MasterCount[7:0) ="00000001" means two bytes and MasterCount[7:0)
="11111111" means
256 bytes (an offset-by-one encoding; the data block count is equal to MasterCount[7:0)+1).
The initiating device converts this internal count value into a value forthe request packet with the following
formula. Little-endien byte addressing is used for specifying bytes within octbytes.
Count[7:0) = Adr[2:0) + MasterCount[7:0)
(Eq 5-1)
Where "+" denotes unsigned integer addition of two bit fields (short fields are zero-extended on the left).
Ifthe value of Adr[2:0) + MasterCount[7:0) is greater than 255 (it may be as much as 262), then the initiating
device must break the request into two transactions.
The Adr[2:0) and Count[2:0) field generate masks for individual bytes within an octbyte. The Adr[35:3) and
Count[7:3) field have the octbyte resolution previously described. The following tables show how the byte
masks are generated. In the case of memory read transactions, the byte masks that are generated do not affect
the data that is returned by the RDRAM; all data bytes in the first and last octbytes are returned in the read
data packet.
In the case of memory write transactions, ByteMaskLS[7:0) applies to the first octbyte at Mem[AV1l7:01l8:0).
Byte MaskMS[7:0) applies to the last oct byte at Mem[AV+CV)[7:0)[8:0). All intermediate oct bytes use a byte
maskof 11111111 (a one means the byte is written, a zero means it is not). Here AV is the value of the Adr[35:3)
field when interpreted as an unsigned, 33 bit integer, and CV is the value of the Count[7:3) field when
interpreted as an unsigned, 5 bit interger. If the Count[7:3) is '00000' (one octbyte). the ByteMaskLS[7:0) and
ByteMaskMS[7:0) masks are logically 'anded' together to give the effective byte mask.:
Table 5-7. Adr[2:0] to ByteMaskLS[7:0J, Encoding
Adr[2:0)
ByteMaskLS[7:0)
Adr[2:0)
ByteMaskLS[7:0)
000
11111111
100
11110000
001
11111110
101
11100000
010
11111100
110
11000000
011
11111000
111
10000000
319
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,uPD488130L
Table 5-8. Count[2:0] to ByteMaskMS[7:0] Encoding
Count[2:0] ByteMaskMS[7:0] Count[2:0] ByteMaskMS[7:0]
000
00000001
100
00011111
001
00000011
101
00111111
010
00000111
110
01111111
011
00001111
111
11111111
The detailed functional description is provided in "Ram bus DRAM user's manuallReference Manua"".
5.2.6 Close Field
The Close field causes a currently accessed row to be explicitly restored (written back to the core if its Dirty
flag for that bank is set) after the current access has completed. This reduces the latency ofa subsequent access
to a different row of memory space in the same bank of that device; i.e. the tReterSensedClean Nack timing is used.
rather than the tRetryScnscdOirty timing.
Table 5-9. Close Field Encodings
Close Field
0
1
Description
Don't restore the currently accessed row of memory. It may be left sensed and
either clean or dirty.
Restore the currently accessed row of memory if its Dirty flag is set. It will be left
sensed and clean.
5.2.7 ReqUnimp[7:0] Fields
These fields are unimplemented (Unimp) in the request packet. They should be driven as zeroes by initiating
devices which satisfy this Version of the Rambus protocol.
Responding devices which satisfy this Version of the Rambus protocol should ignore these fields and
process the request according to the content of the Start, Op[3:0), OpX[1 :0], Adr[35:0], Count[7:0), and Close
fields. The protocol Version number of a device is held in the OeviceType register.
320
NEe
5.3
.uPD488130L
Acknowledge Packet
The Ack[1 :0) field carries the acknowledge encoding from the responding device(s) to the initiating device
and any other listening devices. The following figure shows the format of the acknowledge packet.
Figure 5-2. Acknowledge Packet Format
Device Pins
~-----I-----'-----r-----I-----T-----r----,-----r-----I -----,-----,
I
Clock
Cycle
Number
Bus-
I
: Enable:
BusCtrl
I
Bus-
I
Bus-
I
Bus-
I
Bus-
I
Bus-
I
Bus-
: Data : Data : Data : Data : Data : Data
I
Bus-
I
Bus-
: Data : Data
I
Bus-
I
: Data :
:_____ ~ _____ ~ _181 __:__ [?L _~ _J~[ __~ _L5! _~ _)~I__ ~ _13) __ :__ I?! _~ __[!I__ ~ _1°1 __:
[01
I
even
I
[01
:
I
odd
I
r------
l
I _ _ _ _ _ _ .J
This means that this pin is not used by this packet. If it is not used
by another packet. it is pulled to a logic zero value.
Time
The fo[lowing table summarizes the four combinations ofthe Ack[1 :0) field. The Ack3 combination is Undef.
The Okay combination indicates that the read or write access to the specified space will take place.
When a responding device acknowledges a request with a Nack, then there will be no immediate change
in the state of the device's memory space or register space. The responding device will take the appropriate
steps to make the requested region of memory or [ogister space accessible when the initiating device makes
a subsequent request. The initiating device will nood to wait some device-dependent length oftime until the
requested region is available.
There are three possible reasons for an RDRAM to respond with Nack. They are summarized below. The
detailed functional description is provided in "Ram bus DRAM user's manual (Reference Manual)".
tPostMomWrituDolay
or
tpo~IIRooWrjtoDolay
violation
RowMiss (this causes a delay of tRetrySensedClean or tRetrySensedDirtv)
ongoing refresh (this causes a delay of up to tRetryRefresh)
321
NEe
,uPD488130L
Table 5-10. Ack[1:0] Encodings
Commands
allowed to
Ack
use the Ack [1:0]
Combination
All
00
Name
Description
Nonexistent Indicates passive acceptance of the request (WregB), or
commands
Spec
Undef
Spec
indicates that the addressed device did not respond (all
other commands).
All
01
Okay
Indicates that the request was accepted by the addressed
Spec
by the addressed (responding) device.
commands
but WregB
All
10
Nack
commands
f-------
All
322
Indicates that the request could not be accepted because
Spec
the state of the responding device prevented an access
at the fixed timing slot.
11
Ack3
This should not be returned by this responding device.
commands
Initiating devices will, when presented with this combi-
but WregB
nation, have an undefined response.
Undef
NEe
,uPD488130L
5.4 Data Packet
The following figure shows the format of a data packet for register space read and write commands. It
consists of 1 quadbyte driven on the BusData[8:0] wires for RDRAMs.
Other responding devices may support data packet lengths longer than one quadbyte.
Figure 5-3. Data Packet Format (Register Space)
Device Pins
~-----I-----'-----r----~-----,-----r----,-----r-----I-----,-----.
I
I
I
I
I
I
I
I
I
I
I
I
BusBusBusBusBusBusBusBusBusBusBus: Enable: Ctrl : Data : Data : Data : Data : Data : Data : Data : Data : Data :
Clock
Cycle
Number
:
[01
~_~~e:.n
:_____ ~ _____ ~ _181 __:__ [?~ _1_1~1 __ ~ _l5L ~ __[~I__ ~_13L _: __ ~L~ _J!I __ ~ _!01 __:
:
__ ~
:
[0]
:
:
odd
:
r------l
:
[11
I
even
I
1-------1
I
[11
:
odd
1_ _ _ _ _ _ _ 1I
Time
This means that this pin is not used by this packet. If it is not used
by another packet, it is pulled to a logic zero value.
The following figure shows the format of a data packet for memory space read and write commands. For
most of these commands, it consists of 1 to 32 oct bytes driven on the BusData[7:0] wires. Bus Data [8] is not
used by this packet. [n the figure, "n" is either the CV value (if the transaction is allowed to complete) or the
last count value (if the transaction is terminated prematurely by the sorial control packet!. ·CV" is the value
of the Count[7:3] field when interpreted as an unsigned, 5 bit integer.
The detailed functional description is provided in "Rambus DRAM user's manual (Reference Manual)".
5,4.1 MD Reg [7:01 [7:01=U
This register holds the write data or mask for the persistent per-bit operations (Dpb & Mpb). The MDreg
need not implement the ninth bits when the RDRAM is 8-bit wide.
323
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)lPD488130L
Figure 5·4. Data Packet Format (Memory Space)
Device Pins
~-----r----'-----r-----t-----~-----r----'-----T-----r- ---,-----.
Bus- , Bus- , Bus- I Bus- , Bus- , Bus- , Bus- , Bus- , Bus- , Bus- I Bus- I
: Enable: Ctrl : Data : Data : pata : Data : Data : Data : Data : Data : Data :
~
~ ~81
J~J . . ~. 5 ~ [~J•. ~
~. J!J•. ~
I
Clock
Cycle
Number
:..... .. ___ . ..:. _[!L .l.
L1. ..
.l3J ..:.. !.2L.
1------- 1
:
[OJ
I
even
r-----I
[OJ
:
I
i
I
'
1- _ _odd
____ 1
I
I
[lJ
even
I
[lJ
I
I
1------- 1
I
:
odd
:
r------ t
[2[
:
even
I
I
I-------J
I
[2J
odd
IL _____ _
I
I
[3J
even
.-----[3J
odd
r-------
I
- ----1
[4*nJ
even
I
------~
[4*nJ
:
odd
______
1I
,
[4*n+1J :
, even
.-------1
I
:
[4*n+1J I
odd
:
r------
i
: [4*n+2J :
even
I
I
I- ______ J
: [4*n+2J :
,
odd
:
1"------1
I [4*n+3J '
: even :
r------ 1
: [4*n+3J :
I'- ______
odd .J'
Time
324
This means that this pin is not used by this packet. If it is not used
by another packet. it is pulled to a logic zero value.
.101 ..:
NEe
.uPD488130L
5.5 Serial Address Packet Format
The serial address packet is transmitted by the initiating device and received by the responding devices.
It provides eight low-order address bits for each octbyte which is accessed in memory space (a non-sequential
or random-access transfer). These eight address bits are transferred serially on the BusEnable pin of the
RDRAM, and are thus called a serial address. Each eight bit serial address accesses an octbyte of data within
the RowSenseAmpCache of one of the two banks of the RDRAM. The complete set of serial addresses
transmitted by the initiating device during the transaction are referred to as a serial address packet. The
commands which use this packet are the RnsqAaa, WnsqBbbAaa, and WbnsBbbAaa classes of commands.
The high order bits for each oct byte are provided by the Adr[35:11] address bits from the request packet.
The low-order address bits for the first oct byte are Adr[10:3], also from the request packet. The low-order
address bits for oct bytes [n:1] are provided by the serial address packet. As before, On" is either the CV value
(if the transaction is allowed to complete) or the last count value (if the transaction is terminated prematurely
by the serial control packet). ·CV" is the value of the Count[7:3] field when interpreted as an unsigned, 5 bit
integer. The detailed functional description is provided in "Rembus DRAM user's manual (Reference Manuall".
Table 5-11. Serial Address Fields Ii
Serial Address Field
SAdr[i][10:3]
Description
Low-order address bits for each octbyte.
= n:1)
Unimp
Imp
Imp
325
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,uPD488130L
Figure 5,5. Serial Address Packet Format
Device Pins
~-----I-----'-----r----'-----T-----r----'-----T-----I-----,-----,
I
I
I
I
I
I
I
I
I
I
I
I
BusBusBusBusBusBusBus-' BusBusBusBus: Enable: Ctrl : Data : Data : Data : Data : Data : Data : Data : Data : Data :
Clock
Cycle
Number
[8]
[7]
: _____ ..1I _____ IL _____ 1
I _____ .L
I
[6]
_____
IL
[5]
____
[4]' 1.I _ _[3]
I _____
[2] JI _____
[1] IL _____
[0]
.JI _____
___ 1
II
1- - - - - - - I
[4[
I
:
even
I
[4[
:
r------ i
odd
I _ _ _ _ _ _ JI
I-
I
L
[5]
even
______
I
I
~
:
[5[:
:
odd
I
r------ 1
[6]
I
I ______
even
I[6]
I
I
JI '
:
odd
IL ______ ~I
I
[7]
:
I
even
1"------1
I
[7]
I
I
odd
:
.... ------~
I
.-------1
I
:
[4'111
:
I
evon
r--· --~
:
I
~
[4'nl
:
odd
_____
JI
: [4'n+1] :
I
ovon I
I
: [4'-n~ 1]-:
SAdr
:
[n] [6]
: [4'n+2] :
I __
even
I_ _ _ _ JI
[n] [7]
:
odd
r--"---i
: [4'n+2] :
I
odd
I
~------{
I [4'n+3] I
I
I
even I
I
SAdr
SAdr
[n] [8]
r------ 1
: [4'n+3] :
I
odd .1I
1. _ _ _ _ _ _
Time
326
This means that this pin is not used by this packet. If it is not used
by another packet. it is pulled to a logic zero value,
NEe
.uPD488130L
5.5.1 Serial Control Packet Format
The serial control packet is transmitted by the initiating device and received by the responding devices.
It provides for the early termination of a memory space read or write transaction (before the specified data
count in the Count[7:3] field has elapsed). It consists of eight bits transferred serially on the BusCtrl pin of
the device, thus it is referred to as a serial control packet. The eight bits have the same timing alignment as
the serial address packet. The commands which use this packet are all of those which access memo'ry space.
The register read and write commands do not use the serial control packet. The 16M RDRAM implements
this packet.
The termination occurs on octbyte data packet boundaries. The next figure shows the format of the serial
control packet. The following table summarizes the function of the bits within the serial control packet. Note
that the bits in the even bus ticks must be zero in order for framing to work properly (otherwise, one of these
bits would be interpreted as the Start bit of a new request packet). The SCtr1[5] bit is used to control
termination, and the other three odd bus tick bits are unimplemented.
"
Table 5·12. Serial Control Fields
Serial Control
Fields
SCtrl[O]
SCtrl[1]
SCtrl[2]
SCtrl[3]
SCtrl[4]
SCtr1[5]
Unimp
Imp
Imp
Description
This bit must be a zero due to framing requirements.
unimplemented
Unimp(O)
This bit must be a zero due to framing requirements.
ynimplemented
Imp
Unimp(O)
This bit must be a zero due to framing requirements.
o means don't terminate the current access.
Imp
Imp
1 means terminate the current accoss.
SCtr1[6]
This bit must be a zero due to framing roquiromonts.
SCtr1[7]
unimplemented
.-
Imp
Unimp(O)
If a memory read transaction (RrrrAaa) is terminated by asserting the SCtrl[5] bit to a logical one, the data
octbyte with which it is associated is riot transmitted by the responding device. The initiating.device may star~
a new transaction once the transmission of the read data packet has ceased.
description is provided in "Rambus DRAM user's manual (Reference ManuaU".
The detailed functional
327
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Figure 5-6. Serial Control Packet Format
Device Pins
~-----I-----'-----r----'-----T-----~----'-----T-----r- ---,-----,
I
I
I
I
I
I
I
I
I
I
I
I
BusBus: Enable: Ctrl
Clock
Cycle
Number
BusBusBusBusBusBusBusBusBus: Data : Data : Data : Data : Data : Data : Data : Data : Data :
lSI
17J
16J
15J
141
131
121
11 I
IOJ
: _ _ _ _ _ ..1I _ _ _ _ _ IL ___ __ I1_____ J.I _ _ _ _ _ IL.. ____ .JI _____ 1.
I _____ I1_____ ...1I _____ IL _____ I
:- --10'- -:
:
even
:
101
:
r------~
~
I
__o.?9 __ ~
III
I
I
even
:
L------ 1
:
11J
I
odd
r-----12J
I
I
4
I
even
,..------1I
121
I
odd
:
IL. _ _ _ _ _ _ ,
:
131
:__ ~~o_n__ •
131
:
~
"Ilino
328
:
ocld
______
JI
This means that this pin is not used by this packet. If it is not used
by another packet, it is pulled to a logic zero value.
NEe
,uPD488130L
5.5.2 Serial Mode Packet Format
The serial mode packet transmitted by initiating devices, and received by responding device. Its format
is shown in the following figure.
Figure 5-7. Serial Mode Packet Format
Device Pins
r-----r----'-----r----'-----T-----r----'-----r-----r----1-----1
BusBusBusBusBusBusBusBusBusBusBus-
I
Clock
Cycle
Number
I
I
I
: Enable:
I
Ctrl
I
I
I
I
I
I
I
I
I
: Data : Data : Data : Data : Data : Data : Data : Data : Data :
:_____ 1_____ ~ _181_ .:_ . [7L . ~ . J~I __ ~ _151_ ~ __ [~I__ ~ _131. .:.. I!! .1_ J!I__ ~ _1°1_ .:
[01
even
r------t
[01
odd
:
1I _ _ _ _ _ _ ...1I
This means that this pin is not used by this packet. If it is not used
by another packet. it is pulled to a logic zero value.
Time
The serial mode packet modifies the state of the CountOO[7:0] and Count11[7:0] counters.
These counters cause operating mode transitions when they reach special values. The detailed functional
description is provided in "Rambus DRAM user's manual (Reference Manual)".
A serial mode packet with the SMode[1 :0] field setto 00 is the default. Most transitions are caused by blocks
of sequential serial mode packets, each with the SMode[1 :0] field set to 11. The serial mode packets should
never set SMode[1 :0] field to 01 or 10. This is becauso in some of the operating modes, the clock generator
is unlocked (the frequency is correct but not tho phaso). When this happens, the BusEnable receiver is unable
to discriminate anything other than long pulses of zeros or ones. Because the frequency ofthe clock generator
is correct, it can count the length of these pulses with moderate accuracy.
Table 5-13. Serial Mode Fields
SMode[1:0]
Description
Spec/Rsrv/
Undef
Spec
Undef
00
Increments CountOO[3:01. clears Count11[7:0].
01
10
-
-
Undef
11
Increments Count11[7:0], clears CountOO[3:0]
Spec
329
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6. State Diagram
The following figure is a state diagram of the Frame state machine. The operating mode of the device
depends upon which of the nine states it is in:
reset mode - ResetState
powerdown mode - PowerDownState
standby mode - StandbyState
active mode - ActiveState, IdCompareState, DeviceState, OkayState, NackState, AckWindowState
This section will only discuss the first three states (ResetState, StandbyState, ActiveState). The remaining
five states which are shown shaded in the state diagram (ldCompareState, DeviceState, OkayState, NackState,
AckWindowState) will be dealt with in the "Ram bus DRAM user's manual (Reference Manual}".
The device will enter ResetState when power is initially applied (PowerOn). In ResetState, the device will
be in the reset operating mode, in which all control registers assume a known state. If power has just been
applied, the device will pass through ActiveState and settle in StandbyState, and remain there until serial mode
packets are received from an initiating device.
Figure 6-1. Frame State Machine - State Diagram
11esetState (reset mode)
(pl'lce device in known state)
Power DownState (powerdown mode)
(minimum power dissipation)
PowerOn
=
Count11
= tMod(!/Ifl, t.W~
Count11> tModePA [Pll. MIN
(Assert ClearPDI
L--_ _ _ _.,...--,,...-_ _ _----'
BusCtrlmn
(Start Bit)
Write SetPD in Minlnterval register
=1
AckWindowState (active mode)
(wait for AckWinDelay to elapse)
Execute signal
to Command
state machine
330
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.uPD488130L
ActiveState is the state in which all decisions are made to transition to the states for the other operating
modes. From here, the device will also enter the transaction-framing states. Refer to "Rambus DRAM user's
manual (Reference Manua!)".
After poweron, the device will re-enter ResetState when the value of the Count11 [7:0] counter is greater
than or equal to tModeAR.MIN. The device will leave ResetState when the value of the Countl1[7:0] counter is
less than tModeSA.MIN. This will happen when an SMode[1:0] field of 00 is received, causing the Countl1[7:0]
counter to clear.
The device will enter StandbyState when the value of the CountOO[3:0] counter is greater than or equal to
tModeOelay,MAX, The device will leave StandbyState when the value of the Count11 [7:0] counter is greater than
or equal to tModeSA,MIN.
6.1 Parameters for Operating Mode Transitions
The following table summarizes the parameter values associated with operntino mode transitions of a
responding device. A minimum and maximum value are given forthe parameters to account for implementation
differences. In all cases, the SMode[1:0] field of the consecutive serial mode packets must have the value 11
to cause an operating mode transition (with the exception of the tModeOelay,MAX as mentioned in the previous
section).
Initiating devices must use values within the minimum and maximum SMode packet count
requirements shown above to control operating mode transitions.
Table
6-1.
Responding Device Parameters for Operating Mode Transitions
Count
Parameter
Name
Minimum
(clock
cycles)
Maximum
(clock
cycles)
tModoSA
1
4
Number of SMode packets to cause a transition from
Standby-Mode to ActiveMode
-----
f----------
Description
9
Reserved for future functionality
15
Undefined
21
189
Reserved for future functionality
190
207
Undefined
Rsrv
225
253
Reserved for future functionality
Undef
254
271
Undefined
tModeAR
272
-
Number of SMode packets to cause a transition from Active-
Rsrv
5
Undef
10
Rsrv
Undef
--
---
Mode to ResetMode
tModeOffSet
4
-
Offset from beginning of SMode packet to request packet for
standby to active transition
tModeOelay
-
10
Delay from end of SMode packet to request packet for
standby to active transition
331
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pPD488130L
6.2 Standby Mode and Active Mode
The following figure shows the basic transitions between active and standby modes in response to serial
mode packets
Figure 6-2. Basic ActiveMode/StandbyMode Transitions
.
Clock
Cycles
BusEn BusCtrl
tModoSA, MIN
BusData 18 : 0]
I
tModeOffSet, MIN
tModeDelay, MAX
AetiveMode
This is a timing diagram, with time increasing in the downward direction. The time scale is in clock cycles,
as shown on the left scale. The value of each of the eleven low-swing signal pins of the responding device
is shown with the assumption that tTR is zero (the responding device is located at the master end of the
Channel).
Serial mode packets with an SMode[1:0] field are shown as a box with a '11· label in the BusEn column.
The BusEnable defaults to a logical zero value. The initiating device has transmitted tModoSA,MAX serial mode
packets with SMode[1:0] equal to 11 (this is the longest sequence permitted for invoking a standby to active
transition). After the first tMod.SA,MIN serial mode packets, the device begins the transition to active mode. It
reaches active mode after tMod.OffSot, MIN clock cycles after the start of the first serial mode packet. It remains'
there for tMod,OIlS,t,MAX clock cycles after the last serial mode packet.
The responding device is in active mode when it begins framing the request packet. A transaction may
begin in any of the clock cycles with the light shading above (labeled "Active Mode").
If the serial mode packet(s) causing a standby to active mode transition are not followed by a transaction
with tMod,OIlSe.. MAX clock cycles after the last serial mode packet, then the responding device will return to
standby mode.
332
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,uPD488130L
The next figure shows the case in which a transaction is started as early as possible after a serial mode
packet which causes a standby to active mode transition.
Figure 6-3. ActiveMode/StandbyMode Transition - Early Transaction
.
Clock
Cycles
~
BusEn BusCtrl
tMod,SA. MIN
::::r:::
BusData 18 : 01
T
tModeOffSet. M~
Transaction (Active Model
E
A transaction is composed of packet types other than serial mode packets, and will be defined in the next
chapter. These other packet types lie entirely inside the heavy black box in the above figure. When a
transaction has completed, the device returns to standby mode. The detailed functional description is
provided in "Rambus DRAM user's manual (Reference Manual)".
333
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6.3 Power Down Mode
When responding devices watch the bus, their interface circuits consume power. Standby mode reduces
this power by trading a small latency for reduced power. While in.standby mode, the device's receivers are
inactive.
Figure 6-4. ActiveMode to PowerDownMode Transition
Clock
Cycles
~
~
BusEn
BusCtrl
,
tMo"'·~A. MIN
I
tModeOffSet.
BusData IB : 01
I
M~
Transaction (Active Mode)
Write SetPD in SpecFunc Field of Minlnterval Register
Power may be greatly reduced using the powerdown mode at the expense of moderate latency. In
powerdown mode, the device's receivers and clock circuitry are inactive. The device may deactivate other
power-hungry circuits also. Power-up enables all these circuits and makes the device available for transactions
once the clock circuitry resynchronizes and stabilizes.
Powerdown mode is controlled by the PO bit. This bit is not directly accessible in the register space. Instead,
the "SetPD" combination is written to the SpecFunc field in the Minlnterval register, as indicated in the above
figure. When this is done, the RDRAM performs the following operations:
Restore and precharge the RowSenseAmpCache for both banks
Disable the clock generator
Disable all DC current sources except for a special BusEnable receiver
When these operations have completed, the RDRAM is in powerdown mode. It will consume power for
refresh (which is performed with the Sln/SOutTTL pins), and it will consume a small amount of power watching
the BusEnable pin waiting for a serial mode packet of the proper length. The detailed functional description
is provided in "Rambus DRAM user's manual (Reference Manual)".
334
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6.4 ResetMode
Reset mode is entered when a consecutive sequence of tModoAR.MIN serial mode packets with a value of 11
are seen by a responding device (shown in the following figure). In reset mode, all devices enter a known
state from which they may be Initialized. The device remains in reset mode for as long as serial mode packets
with 11 value are received. When one or more serial mode packets with a value of 00 are seen, the responding
device enters the active mode state.
Although devices enter the active mode state immediately, their clock circuitry requires a time tLock.MIN to
resynchronize. Initiating devices must wait this long after the transition out of reset mode before starting any
transactions.
Note that in order to keep the devices in active mode during this synchronization process, it is necessary
to provide a burst of serial mode packets every tModoOeloy.MAX clock cycles. This burst is shown as tModeSA.MAX
in length, but may, of course, be as short as tModoSA.MIN. If the device is not kept in active mode during
synchronization, then the synchronization process requires tLock.MIN clock cycles.
335
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Figure 6-5. ResetMode to ActiveMode Transition
Clock
Cycles
.
BusEn BusCtrl
BusData [8 : OJ
E
~
IModeSA. M I N I
tModeOffSet.
IMOdcSA, M I N I
tModcOffSet.
T
Active Mode
M1
T
M1
Active Mode
Active MQde
tModcSA, M I N I
T
tModuOIIS!'I, M j _
Active Mode
tloCk. Act1ve, MIU
tModeSA, M I N I
tModeOffSet.
T
M1
Transaction (Active Mode)
336
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7. Transactions
7.1 Read Transactions
The following figure shows the basic form of a memory space or register space read transaction. There are request
and acknowledge packets, with the same tAckDelay and tAckWinDelay timing constraints as already discussed (tAckW,oDelay
will not be shown explicitly on any further transaction diagrams in this document.
When the responding device transmits an Okay acknowledge packet to the initiating device, it will also transmit
a data packet with read data. This packet is sent a time tRead Delay after the end of the request packet. The tRead Delay
value is in tCYCLE units and is programmed into the ReadDelay field of the Delay register of each responding device.
It is not required to be the same for all devices within a Rambus system, but the difference (tlloadDelay - tAckDelay) is
required to be the same. This allows initiating dovices to use the acknowledge packet to determine when the read
data packet begins. The detailed functional description is providod in "Rambus DRAM user's manual (Reference
Manual)".
Figure 7-1. Read Transaction
.
Clock
Cycles
BusEn BusCtrl
BusData (8 : 01
tAckDe lav!
~
.-r-
tReadOelay
t~"dOe'.., -
tAckOel,,>,
_...........
337
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7.2 Write Transactions
The following figure shows the basic form of a memory space or register space write transaction. There are request
and acknowledge packets, with the same tAckDelay and tAckWmDelay timing constraints as already discussed.
When the initiating device transmits a request packet to the responding devices, it will also transmit a data packet
with write data. This packet is sent a time tWriteDelay cycles after the end of the request packet. The tWriteDelay is in
tCYCLE units and is programmed into the Write Delay field of the Delay register of each responding device. It is required
to be the same for all devices within a Rambus system. A responding device will see the same tWriteDelay interval
between the request and write data packets whether the device is on the Primary Channel or on a Secondary Channel.
If the responding device returns an Okay acknowledge packet, then the transaction is complete at the end of the
acknowledge window or at the end of the write data packet, whichever is later. The next request packet can be
transmitted in the following clock cycle except for the case in which a register or memory space write to a device
is followed by any other transaction to that device. In that case, one of the following two intervals must be inserted
between the two transactions, where the memory or register case depends upon the first transaction.
•
tPoc.tRegWriteDelay if the current transaction is a register space access
•
tPostMemWriteDelay if the current transaction is a memory space access
If the responding device returns a Nack or Nonexistent acknowledge packet for a write command, then no write
data packet is required by the responding device. The current transaction is complete at the end of the acknowledge
window, or when the initiating device stops transmitting the write data packet, whichever is later. The next request
packet can be transmitted in the following clock cycle. For the case of a Nack or Nonexistent, the initiating device
must terminate the write data packet before another initiating device is given control of the Rambus Channel for a
transaction. This is part of the arbitration mechanism used by the initiating devices. The arbitration mechanism is
not specified in this document because it does not use the Rambus Channel. The detailed functional description
is provided in "Rambus DRAM user's manual (Reference Manual)".
Figure 7-2. Write Transaction
Clock
Cycles
BusEn BusCtrl
BusData [8 : OJ
Request
t
tACkDe:[
:I
Data
Ack
~
1tPO,tRQgWlfmDelB;'m:~_":
.'
.
.. .
"
338
twnteDelay
'~..
;.'
.
I
Next transaction to same device
I
Next transaction to different device
~
~
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.uPD488130L
7.3 Read Transactions with Serial Address Packet
The following figure shows a memory space read transaction for a command which uses the serial address packet.
For a transaction which moves (n+ 1) oct bytes of read data, the serial address packet will be (4 x n) clock cycles in
length (recall that the low-order address bits for the first octbyte of read data come from the request packet).
Each serial address subpacket (each SAdr[i][1 0:3] field) is transmitted by the initiating device a time tSerialReadOffSe,
clock cycles before the oct byte of read data to which it corresponds, This means that the serial address' packet will
move with the read data packet, with a constant offset.
•
tSenalReadOffSe! is the delay from the beginning of a serial address subpackct to the beginning of the read data
subpacket (octbyte) with which it is associated,
The detailed functional description is provided in "Rambus DRAM user's manual (Reference Manuall",
Figure 7-3. Read Transaction with Serial Address Packet
Clock
Cycles
BusEn BusCtrl
BusData [8 : 01
Request
I--SAdr
[11
(10: 31
..ML
I~~,
tlleodOolay
SAdr'"
In-11
(10: 31
SAdr
(nl
(10: 31
~
Data (01 [7 : 0118 : 01 = RData (01 (7 : 01 (8 : 01
DilIll
111 1'1 : 0118: 01 = RData (11 (7: 0118: 01
---.,.._._._-
tScrlillRcadOffSet
Data (n-11 (7 : 01 (8: 01 = RData [n-11 [7 : 0118: 01
Data (nl (7 : 01 (8 : 01 = RData (nl [7 : 01 (8 : 01
339
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7.4 Write Transactions with Serial Address Packet
The following figure shows a memory space write transaction for a command which uses the serial address packet.
For a transaction which moves (n+ 1) octbytes of write data, the serial address packet will be (4
x n) clock cycles
in length (recall that the low-order address bits for the first octbyte of write data come from the request packet).
Each serial address subpacket (each SAdr[ill1 0:3J field) is transmitted by the initiating device a time tSerialWriteOffSet
clock cycles before the octbyte of write data to which it corresponds. This means that the serial address packet
will move with the write data packet, with a constant offset.
•
tSerialWriteOffSet is the delay from the beginning of a serial address subpacket to the beginning of
the write data subpacket (octbyte) with which it is associated.
Note that this offset interval is measured at the initiating device or the responding device; it will be the same at
either point since the serial address packet and write data packet are moving in the same direction - from initiating
device to responding device.
Figure 7-4. Write Transaction with Serial Address Packet
Clock
Cycles
BusEn Buselrl
BusData [8 : 0)
':5!'dr
Request
[11
[10 :3)
tAckOo
~!
I-:-:- '.
... ' i tWlilOlJela.
lAck
Data [01 [7 : 01 [8 : 0)
=WData (0) [7 : 0) [8 : 0)
Data (1) [7: O[ [8: 01
=WData (1) [7: 0) [8: 0)
;------:-:
SAdr
[n-l)
[10: 31
--
I
tSt'lhlIV\'rllCOfl
SAdr
[nl
.....,-':"
[10: 3)
-:~: .'
r--
Data )n-1) [7: 0) [8: 0)
Data [n) [7 : 0) 18 : 01
l
=WData [n) [7 : 0) [8 : 0)
tP.stA.~O!!D",Wpr~~~ .'.
I
I
340
=WData [n-l) [7: 0)18: 01
..
.
..' ..:', .
.
.,:
Next transaction to same device
Next transaction to different device
~
~
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pPD488130L
7.5 Read Transactions with Serial Control Packet
The following figure shows a memory space read transaction for a command which uses the serial control packet.
This packet is used to terminate a transaction before the (CV+ 1) octbytes of read data have been transferred, where
CV is the value of the Count[7:31 Field when interpreted as an unsigned, five bit integer. In the example shown,
the read data is terminated after (n) octbytes have been transferred.
The serial control packet is transmitted by the initiating device a time tSerialReadOffSet clock cycles before the end
of the last read data octbyte which is transmitted by the responding device.
The serial control packet is also constrained to lie entirely outside the tAckWinDelay interval, as shown in the figure,
in order to avoid interference with the acknowledge packet which is being returned by the responding device.
Violation of this constraint will produce undefined (Undef) results. The detailed functional description is provided
in "Rambus DRAM user's manual (Reference Manua!)".
Figure 7-5. Read Transaction with Serial Control Packet
.
Clock
Cycles
Bus En BusCtrl
Bus Data [8 : 0]
Request
-,-
tAckWmdDe ~y
The serial contro I
packet must not Ii e
inside the acknowledg e
window
-
11$D~Y
Data [0] [7 : 0] [8 : 0] = RData [0] [7 : 0] [8 : 0]
......
-............
-SCtrl
17: 0)
tSerialReadOffSet
tlloidOeioy
.............
Data [n·3111 : OIIB : 01 = ROata [n-3] [7 : 01 [8 : 0)
Data [n-2) [7 : 0) 18 : 0) = RData [n-2) [7 : 0) 18 : 0)
Data [n-1) [7: 0) [8: 0) = RData [n-1) [7: 0) 18: 0]
-'--
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7.6 Write Transactions with Serial Control Packet
The following figure shows a memory space write transaction for a command which uses the serial control packet.
This packet is used to terminate a transaction before the (CV+ 1) oct bytes of write data have been transferred, where
CV is the value of the Count[7:3) field when interpreted as an unsigned, five bit integer. In the example shown, the
write data is terminated after (n) oct bytes have been transferred.
The serial control packet is transmitted by the initiating device a time tSerialWriteOffSet clock cycles before the' end
of the last write data octbyte which is transmitted by the initiating device.
Note that this offset interval is measured at the initiating device or the responding device; it will be the same at
either since the serial address packet and write data packet are moving in the same direction - from initiating device
to responding device.
The serial control packet is also constrained to lie entirely outside the tAckWinOelay interval, as shown in the figure,
in order to avoid interference with the acknowledge packet which is being returned by the responding device.
Violation of this constraint will produce undefined (Undef) results.
Figure 7-6. Write Transaction with Serial Control Packet
Clock
Cycles
BusEn BusCtrl
BusData (8 : 0)
.----------------------------------Request
,!
tAckDelay
lAck
'tAckWlndD
Data [0) [7 : 0) [8 : 0)
=WData (0) [7 : 0) (8 : 0)
Data [1) [7: 0) [8: 0)
=WData (1) [7: 0) [8: 0)
.'ay
The serial cont rol
packet must not lie
inside the acknowled ge
windo w.
.H
.
',:
. ',"
- - ...............
SCtri
(7: 0)
Data [n-2) [7 : 0) [8 : 0)
=WData [n-2) (7 : 0) [8 : 0)
Data [n-1) [7 : 0)[8 : 0)
=WData [n-lI (7 : 0) (B : 0)
tSctlaIVVII100 IISol
..
... :,;,.:
H:" . .. . ..
~
.)!~~~)
I
I
342
;.:.
'~:.:
.'
.
..
Next transaction to same device
Next transaction to different device
}:
~
~
NEe
,uPD488130L
8. Nack Acknowledge Response
8.1 Retry and Miss Latency
If a responding device returns a Nack acknowledge packet, then no read or write data packet is transacted.
The current transaction is complete at the end of the acknowledge window. It will be necessary to wait for
an interval oftime (called a tRETRY interval) before resubmitting the transaction. The following figure illustrates
this case.
Figure 8-1. Nack Acknowledge Response
Clock
Cycles
§
.
BusEn BusCtrl
BusData [8 : 0]
Transaction
Nack Acknowledge Response
tRetrvSensedClean
or
tRetrySensedDlrty
or
tRetryRefresh
tReadMlss
or
twriteMISS
tReadH~
or
Transaction
Okay Acknowledge Response
tWriteHl1
Read Data or Write Data Packet
Once the tRETRY interval has elapsed, the transaction may be restarted by the initiating device, and the
RDRAM will return an Okay acknowledge packet and the data packet will be transferred. An RDRAM will Nack
any other transactions which are issued during the tRETRY interval.
Two miss latency parameters may be derived with the following equations:
=tRETRY + tRe.dHit
twriteMiss = tRETRY + twriteHit
tReadMiss
(Eq 8-1)
(Eq 8-2)
where tRETRY = {tRetrySensedClean, tRetrySensedDirty, tRetryRefresh}. The tReadMiss and twriteMiss parameters are the time from
the beginning of the original (Nacked) request packet to the beginning of the data packet which is eventually
transferred.
343
NEe
,uPD488130L
8.2 tRETRY Interval
8.2.1 Retry Due to RowMiss
If an initiating device requests a region of memory space in an RDRAM slave which is not currently held
in the RowSenseAmpCache, the RDRAM will respond with a Nackacknowledge packet. The RDRAM will then
begin a RowMiss operation to get the proper row into the RowSenseAmpCache. During the RowMiss, the
RDRAM will Nack any request it is given. When the RowMiss is complete, the new row may be accessed.
Each bank has a Valid flag and a Dirty flag for its Row register. After reset, both are zero. After a RowMiss
has caused a new row to be placed into the RowSenseAmpCache, the Row register contains its row address
and the Valid flag is set to a one. If the RowSenseAmpCache contents are modified with a memory write
transaction, the dirty flag will be set. These flags are not directly accessiQle to initiating devices.
A subsequent RowMiss will cause the old row to be written back to the bank (if it was dirty and an explicit
restore was not forced with the Close bit in the request packet) and a new row to be placed into the
RowSenseAmpCache. The time required for this is called the tRETRY time, and is added to the normal read and
write hit latency times, as shown in the preceding figure. These times are given by the following equations.
The component parameters are shown in a subsequent table. All of these tRETRY intervals correspond roughly
to the cycle time parameter tRC of a conventional page mode DRAM. This is because RDRAMs use CAS-type
accesses for all memory read and write transactions.
After a new row is sensed and placed into the RowSenseAmpCache, a final interval tRowlmprestore is used to
restore the row in core back to its original state. This is necessary because the DRAM sense operation is
destructive. This interval is not in the critical timing path, and is performed in parallel with a subsequent data
transfer. It can extend a subsequent retry operation.
There are two tRETRY equations for the 16M RDRAM:
tRetrvScnsedClean
= tRowOverHead + tRowProchargo + tRowSonse
tRetrySensodDlrty = tRowOverHead + tRowExprestore + tRowPrecharge + tRowSen.e
(Eq 8-3)
(Eq 8-4)
The detailed functional description is provided in "Rambus DRAM user's manual (Reference Manual)".
344
NEe
.uPD488130L
8.2.2 Retry Due to Pending Burst Refresh
In a 16M RDRAM, a refresh burst will also restore the currently accessed row if it is dirty. This requires
a tRowExprestore interval. If the row is clean, this interval is not required. A burst of four rows are precharged/
sensed/restored (using the tRowlmprestore interval), and the current row is precharged/sensed so the RDRAM is
left with its RowSenseAmpCache state unaltered (except the row's dirty flag will be cleared):
tRetryAefresh
=
(tRowOverHead
+ tRowExprestore Note 1
+ 2tRowPrcchargo Note 2 + tRowSense)
+ 4 (tRowOverHead + tRowlmprcstorc + 2tRowPruchargc Noto 2 + tRowSense)
(Eq 8-5)
When a transaction initiates a manual burst refresh in an RDRAM (transaction "A" in the figure below), the
RDRAM will Nack all further transactions directed to in during the tRot,yRofro"h interval after. No information
from these Nackedtransactionswill be retained afterthetRetryRefresh interval. Afterthetn"trynefresh interval. transactions
will be handled in a normal fashion. The detailed functional description is provided in "Rambus DRAM user's
manual (Reference Manual)".
Notes 1.
2.
This term is not present if the current row is clean.
This term is present twice in each cycle because the tRowPrecharge interval is also used to ensure
that a minimum delay between restore operations is met.
Figure 8-2. Transaction Holdoff Due to Burst Refresh
Clock
Cycles
~
~
~
!
~
BusEn BusCtrl
BusData [8 : 01
,.,.------------------------------------------------
Transaction A-Start Manual Burst Refresh
Okay Acknowledge Response
tRetryRefresh
Transaction B
Nack Acknowledge Response
Transaction B
Normal Response
345
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,uPD488130L
8.3 Retry Component Intervals
The tRETRY intervals are built from the tRowOverHead, tRowPrecharge, tRowSense, tRowlmprestore, and tRowExprestore intervals.
All five intervals are measured in tCYCLE units, and thus scale with the clock frequency.
The tRowOvcrHcad interval consists of the RowMiss state machine overhead. The remaining four intervals
represent the width of intervals used for timing core operations. These core operations have minimum times
measured in nanosecond units (this is shown in the ·core timing(ns)" columns in the table below). The four
intervals are composed of a fixed part and a variable (programmable) part. If the clock frequency is reduced,
the variable part may be reduced so the sum of the fixed and variable parts remain greater than or equal to
the minimum core operation time (in nanoseconds).
Table 8-1. Retry Components
and
Parameter
tnnwOvurlluiltl
tRowPrecharge
tRowSense
tRowlmprestorc
-
Row overhead
6
-
nfa
RowPrecharge overhead
4
RowPrecharge[4:0]
1
--
RowSense overhead
4
RowSense[4:0]
7
RowlmpRestore overhead 4
--------
with tCYCLE = 4ns
24
- -p-
20
44
56
10
RowExpRestore overhead 4
RowExpRestore[4:0]
core timing (ns)
tCYCLE Units
(4 ns)
Variable PartNote
RowlmpRestore[4:0]
tRowExprostorn
16M RDRAM
Fixed Part (overhead)
Delay
32
4
Note The variable part is programmed into the indicated field of the Raslnterval register.
346
NEe
,uPD488130L
9. AddressMapping
The address space decoding logic contained in a 16M RDRAM is shown in the following figure. The initiating
device places a 33 bit physical octbyte address Adr[35:3] on the Channel. This address is received by the
RDRAM slave. The AddressSelect[1][1:0], [0][7:1] control register allows individual bits ofthe Adr[28:20] and
Adr [19:11] fields to be swapped to produce the AdrS[28:20] and AdrS[19:11] fields. The Adr[35:29] and
Adr[10:3] fields pass through unaltered to the AdrS[35:29] and AdrS[10:3] fields. The figure shows the case
when AddressSelect[0][7:1].[1][1 :0] = 111111111, and the two nine bit address fields are exchanged. The
detailed functional description is provided in "Rambus DRAM user's manual (Reference Manua"".
Figure 9-1. AddressMapping Hardware
I
..
353433323130292827262524232221201918171615141312111098 7 6 543
I
I
I
I
Adr [35 : 21
Address in Request Packet ,--_D_[1_5_:,..,,9,....1_.l...-_ _
R_[8".,...:0_1_---I_ _D_[8,..,:,....0_1_-,-__C....;,..[7_:.,.0:-1- - - l
9~
7
I
AddressSelect [01 [7 : 1I. [11 [1 : 01
= 111111111
I 9
-'
JI--"---+------I,
I
I
°~
mux
_
_
1
~9
8
~
° I
1 mux
I
I
I
AdrS [35 : 21
Address used by RDRAM Core ,--_D_[1_5_:_9_'_.l...-_ _
D_[8_:0_,_---I_ _R
_[8_:_0_1_-,-__C_[7_:_0_'- - - l
353433323130292827262524232221201918171615141312111098 7 6 543
347
NEe
JlPD488130L
10. Electrical Characteristics (Preliminary)
Absolute Maximum Ratings
Symbol
Parameter
MIN.
MAX.·
VI,ABS
Voltage applied to any RSL pin with respect to GND
-0.5
·Voo+0.5
V
VI.TTL.ASS
Voltage applied to any TTL pin with respect to GND
-0.5
Voo+0.5
V
VOO.ABS
Voltage on Voo with respect to GND
-0.5
VOO.MAX+ 1.0
V
TOPT
Operation temperature
0
+70
·C
TSToRE
Storage temperature
-55
+125
·C
Caution
Unit
Note
1
The following table represents stress ratings only, and functional operation at the maximums
is not guaranteed. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although devices contain protective circuitry to resist damage from static electric
discharge, always take precautions to avoid high static voltages or electric fields.
Note 1 This parameter apply at the status of using 50% Rambus channel by Read or Write and a transverse
air flow greater than 1.5m/s maintained.
Thermal Parameters
Symbol
Parameter
TJ
Junction operating temperature
ElJC
Junction-to-Case thermal resistance
MIN.
MAX.
Unit
100
·C
5
·C/W
MAX.
Unit
Capacitance
Symbol
348
Parameter
MIN.
CliO
Low-swing input/output parasitic capacitance
2
pF
CI.TTL
TTL input parasitic capacitance
8
pF
NEe
,uPD488130L
Power Consumption
Iccl
lce2
MAX.
Unit
-A45
110
mA
-A50
125
-A45
330
-A50
350
Parameter
Mode
MIN.
Active Current
Standby Current
Icc3
Read Operation Current
-A45
440
(Burst Length = 256)
-A50
480
Icc4
Write Operation Current
-A45
435
-A50
460
Icc5
Power Down Current
mA
mA
mA
mA
T.B.D
Caution These do not include the IOL current passing through the low-swing pins to ground.
Recommended Operating Conditions
Symbol
Parameter
VDD, VDDA Supply voltage
MIN.
MAX.
Unit
3.15
3.45
V
1.95
2.15
V
VREF
Reference voltage
Vowing
Input voltage range
1.0
1.4
V
VIL
Input low voltage
VREF-0.7
VREF-0.5
V
VIH
Input high voltage
VREF+0.5
VREF+0.7
V
VIL, TTL
TTL input low voltage
-0.5
+0.8
V
VIH, TTL
TTL input high voltage
2.0
VDo+O.5
V
DC Characteristics (Recommended operating conditions unless otherwise noted)
Symbol
Parameter
Conditions
MIN.
MAX.
Unit
VREF=Maximum
-10
+10
pA.
-10
+10
pA.
25
mA
IREF
VREF cu rrent
IOH
High level output current
OS;VOU~VDD
IOL
Low level output current
VouT=1.6 V
II, TTL
TTL input leakage current
0:5 VI, TTL :5VDD
-10
+10
pA.
VOH, TTL
High level TTL output voltage
IOH, TTL=-0.25 mA
2.4
VDD
V
VOL, TTL
Low level TTL output voltage
IOL, TTL= 1.0 mA
0
0.4
V
349
NEe
,uPD488130L
Recommended Timing Conditions
Symbol
Pause time after Power On
tCR, tCF
TxClk and RxClk input rise and fall times
tCYCLE
TxClk and RxClk cycle times
tTICK
MIN:
Parameter
tPAUSE
MAX.
Unit
200
J.IS
0.3
0.7
ns
-A45
4.45
6
ns
-A50
4
6
ns
tCYCLe/2
tCYCLE/2
ns
Transport time per bit per pin (this timing interval is
synthesized by the RDRAM's internal clock generator)
tCH, tCL
TxClk and RxClk high and low times
47%
53%
tCYCLE
0.25
0.7
ns
50
ns
tTR
TxClk-RxClk differential
tso
Sln-to-SOut propagation delay
to
TxClk-to-Data/Control output time
tCYCLe/8+0.05 tCYCLE3/8-:0.05
ns
ts
Data/Control-to-RxClk setup time
tCYCLe/4-0.05
ns
til
RxClk-to-Data/Control hold time
tCYCLE/4-0.05
ns
:tilEr
Refresh interval
32
tl.OCK
RDRAM internal clock generator lock time
500
ms
tCYCLE
Transaction Timing Characteristics
Symbol
tP()~;tHngWriteDeI8V
Parameter
Delay from the end of the current transaction to the
MIN.
Unit
6
tCYCLE
4
tCYCLE
2
tCYCLE
12
tevCLE
8
tevCLE
beginning of the next transaction if the current transaction
is a write to register space and the next transaction is
made to the same device.
Use zero delay if the next transaction is to a different
device.
tPostMemWriteDelay
Delay from the end of the current transaction to the
beginning of the next transaction if the current transaction
is a write to memory space and the next transaction is
made to the same device.
Use zero delay if the next transaction is to a different
device.
tPostMemReadOelay
Delay from the end of the current memory read transaction to the beginning of the next transaction.
tSerialReadOffSet
Delay from the beginning of a serial address subpacket or
serial control packet to the beginning of the read data
subpacket (octbyte) with which it is associated.
tSerialWriteOffSet
Delay from the beginning of a serial address subpacket or
serial control packet to the beginning of the write data
subpacket (octbyte) with which it is associated.
350
NEe
,uPD488130L
Data and Transaction Latency Characteristics
Symbol
Parameter
MIN.
Unit
Notes
tAeadDelay
Delay from the end of a read request packet to the
7
tCYCLE
1
1
tCYCLE
2
beginning of the read data packet.
tWriteDelay
Delay from the end of a write request packet to the
beginning of the write data packet.
Notes 1. tAeadDelay is programmed to its minimum value.
2. tWriteDelay is programmed to its minimum value.
Hit, Retry and Miss Delay Characteristics
Symbol
tAeadHit
Parameter
MIN.
Unit
Notos
Start of request packet to start of read data packet for
10
tCYCLE
1
4
tCYCLE
1
22
tCYCLE
2
30
tCYCLE
2
Clean
191
tCYCLE
2
Dirty
199
32
tCYCLE
3
26
tCYCLE
3
row hit (Okay).
tWriteHit
Start of req uest packet to start of write data packet for
row hit (Okay).
tAetrySensedClean
Start of request packet for row miss (Nack) to start
of request packet for row hit (Okay).
The previous row is unmodified.
tAetrySen.edDlrty
Start of request packet for row miss (Nack) to start
of request packet for row hit (Okay).
The previous row is modified.
tAeiryAefre.h
tAe.dMiss
Start of request packet for row miss
(Nack) to start of request packet for row
hit (Okay).
Start of request packet for row miss (Nack) to start of
Read Data packet for row hit (Okay).
tWriteMiss
Start of request packet for row miss (Nack) to start of
Write Data packet for row hit (Okay).
Notes 1. Programmable
2. tAowExprestore, tPrecharge, and tsense are programmed to there minimum value.
3. Calculated with tAetrySensedCleanlMINI.
351
NEe
,uPD488130L
Rise/Fall Timing Chart
VRxClk, VTxClk
VIIHMIN I -
--ls----------------------------------------------------{---
VIL(MAXI - - - - - - -
- -
~----------------------------------------------.
b
b
Clock Timing Chart
tCYCLE
VTCIk
VREF-
VRClk
VnEF-
tcYCLE
Receive Data Timing Chart
tevelE
VRCI'
VREF-
VOalaOu!
or
VREF-
VControlOut
352
tevelE
NEe
J.lPD488130L
Transmit Data Timing Chart
tCYClE
tCYClE
VRClk
VOataOut
or
VCOIltrolOut
Serial Configuration Pin Timing Chart
VS(n
VSW. TIL -
tSD. m (MAX.)
tSD(M(N.}
VSOur
V~.m-
VS(n
V~.TIl-
tsDO
VSOur
VSW. m -
Remark Vsw,
TIL
= 1.5 V
353
NEe
yPD488130L
11. Package Drawings
32 PIN PLASTIC SVP (11 X 25)
A
...J
* D~
Clzi>1
Detail of @ - @' part
NOTE
Each 1/0 lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
*
** Each support lead centerline is located within 0.18 mm (0.007 inch)
of its true position (T.P.) at maximum material condition.
ITEM
A
B
~:
MILLIMETERS
INCHES
25.30 MAX.
11.010.1
0.996 MAX.
0.433±0.004
C
0.2410.06
0.009~8:88~
0
0.13
0.65 (T.P.)
2.575 MAX.
0.10
0.52±0.06
0.9 (T.P.)
23.20
1.25
11.80 MAX.
0.005
0.026 (T. P.)
0.102 MAX.
0.004
0.020±0.002
0.035 (T.P.)
0.913
0.049
0.465 MAX.
E
F
G
H
I
J
K
L
M
0.5±0.1
0.020~8:88~
N
3.70 MAX.
0.146 MAX.
p
0.17~8:8~~
0.007tO.00l
Q
0.9±0.25
0.035~8:8n
R
3 0 _3'
+70
3 0 _3'
+ 70
S
1.90 MAX.
0.18
0.075 MAX.
0.007
T
S32VN-65-9
354
NEe
pPD488130L
72/36 PIN PLASTIC SSOP TYPE
~------------~R~------------~4-S
detail of lead end
++--------------+---------------+
a..
I.
A
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
C
25.30 MAX.
2.575 MAX.
0.65 (T.P.)
0.996 MAX.
0.102 MAX.
0.026 (T.P.)
0
0.24±0.06
0.009~8:88~
E
0.25±0.05
0.01O::8:88~
F
1.6 MAX.
1.25
13.0±0.2
11.0±0.1
0.063 MAX.
0.049
0.512±0.008
0.433±0.004
1.0±0.2
0.039::8:88ij
K
0.17::8:m
0.007±0.001
L
0.5±0.1
0.020::g:gg~
M
N
0.13
0.10
70
30 +
_3 0
0.005
0.004
3 0 +_3700
0.65 (T.P.)
22.75
1.275 MAX.
0.026 (T.P.)
0.896
0.051 MAX.
s
G
H
P
Q
R
S
P32G6-65A
355
NEe
[MEMO)
356
,uPD488130L
Synchronous GRAM
357
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
,uPD481850
8M-bit Synchronous GRAM
Description
The ,uPD481850 is a synchronous graphics memory (SGRAM) organized as 12B K words x 32 bits x 2 banks
random access port.
This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write
function to improve capability in graphics system.
This product is packaged in 100-pin plastic OFP (14 x 20 mm).
Features
• 131,072 words x 32 bits x 2 banks memory
• Synchronous interface (Fully synchronous DRAM with all input signals are latched at rising edge of clock)
Pulsed interface
Automatic precharge and controlled precharge commands
Ping-pong operation between the two internal memory banks
Up to 100 MHz operation frequency
• Possible to assert random column address in every cycle
• Dual internal banks controlled by A9 (Bank Address: BA)
• Byte control using DOMO to DQM3 signals both in read and write cycle
• 8-column Block Write (BW) function
• Persistent write per bit (WPB) function
• Programmable wrap sequence (Sequential/Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (1, 2, and 3)
• Power Down operation and Clock Suspend operation
• Auto refresh (CBR refresh) or self refresh capability
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 100-pin Plastic OFP (14 x 20 mm)
• 1,024 refresh cycles/16 ms
• Burst termination by Precharge command
• Burst termination by Burst stop command (in case of full-page burst)
Ordering Information
Part number
Cycle time
ns (MIN.)
Clock frequency
jlPD481850GF-A 1O-JBT
10
100
jlPD481850GF-A 12-JBT
12
83
jlPD481850GF-A 15-JBT
15
66
MHz (MAX.)
Package
100-pin Plastic QFP (14 x 20 mm)
The information in this document Is subject to change without notice.
Ml0235EJ1VODSOO (Japan)
359
NEe
jlPD481850
Part Number
Synchronous GRAM
,uPD48 1 8 5
NEC CMOS Application Specific Memory
~
o
GF
-,--
A 10
-
--
Device code
1: Graphics RAM
Capacity - - - - - - - - - - - - - - - - - - - - '
8: 8M bits
Words organization
5: x32
Function
Package
GF: QFP
Vee
----------------------------------~
A: 3.3 V ± 0.3 V
Cycle time
10: 10 ns
12: 12 ns
15: 15 ns
360
--
NEe
,uPD481850
Pin Configuration (Marking Side)
100-pin Plastic QFP (14 x 20 mm)
omoo~m~~MN~omoo~wm~MN~omoo~m~~MN~
oo~~~~~~~~~~mmmWIDIDIDIDIDIDmmmmmmmmm
D029
VssO
D030
D031
Vss
81
50
82
83
84
49
48
47
85
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
86
87
44
88
43
Vee
DOO
DOl
VssO
D02
96
97
35
34
98
33
32
89
90
pPD481850GF-Axx-JBT
91
92
93
94
95
99
100
0
au a
l:l >::l 0N N
~
N MOO N
N
N \) '; ".;
o~cc~cc~OO~OO~
OO~Oo~aa
M
a
U'l
1,1)
cc
............
cc
AO -A9
U)
cc
cc~cc
IWS 1 Bank active
L
H
H
H
x
x
NOP
Continue burst to end -> Bank active
Undefined
ILLEGAL
L
H
H
L
H
x
L
H
H
L
L
x
'
.
BST
1, 2, 4, 8 burst length; Nop (Continue burst
to end -> Bank active)
Full page burst; Burst stop
Write/Block wril"
Ba,nk active
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
BA, CA, A8
READ/READA
Term burst, new read: Determine AP
7
L
H
L
L
H
BA, CA. A8
BW/BWA
Term burst, Start block write: Determine AP
7,8
L
H
L
L
L
BA,CA,AS
WRIT/WRITA
Term burst, start write: Determine AP
7,8
L
L
H
H
H
BA,RA
ACTWPB
ILLEGAL
3
L
L
H
H
L
BA,RA
ACT
ILLEGAL
3
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA, A8
PRE/PALL
Term burst, precharge timing for reads
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Code
SRS
ILLEGAL
L
L
L
L
L
Op-Codo
MRS
ILLEGAL
H
x
x
x
x
x
DESL
Continue burst to end -> Write recovering
L
H
H
H
x
x
NOP
Continue burst to end -> Write recovering
L
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
BST
1,2,4, B burst length; Nop (Continue burst
to end
--l
Bank active)
Full page burst; Burst stop
374
--l
--l
Bank active
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
BA,CA,AB
READ/READA
Term burst, stort read: Determine AP
7,8
L
H
L
L
H
BA,CA,A8
BW/BWA
Term burst, new block write: Determine AP
7
L
H
L
L
L
BA,CA,AB
WRIT/WRITA
Term burst, new write: 'Determine AP
7
L
L
H
H
H
BA,RA
ACTWPB
ILLEGAL
3
L
L
H
H
L
BA,RA
ACT
ILLEGAL
3
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA,AS
PRE/PALL
Term burst, precharge timing for writes
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Code
SRS
ILLEGAL
L
L
L
L
L
Op-Code
MRS
ILLEGAL
3,9
NEe
j1PD481850
(3/71
Current state
Read with
auto precharge
Write/Block write
with auto
precharge
CS RAS CAS WE DSF
Address
Action
Command
Notes
H
x
x
x
x
x
DESL
Continue burst to end .... precharging
L
H
H
H
x
x
NOP
Continue burst to end .... precharging
L
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
BST
ILLEGAL
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
BA, CA, AS
READ/READA
ILLEGAL
L
H
L
L
H
BA, CA, AS
BW/BWA
ILLEGAL
L
H
L
L
L
BA, CA, AS
WRIT/WRITA
ILLEGAL
L
L
H
H
H
BA,RA
ACTWPB
ILLEGAL
3
L
L
H
H
L
BA, RA
ACT
ILLEGAL
3
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA,AS
PRE/PALL
ILLEGAL
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Code
SRS
ILLEGAL
L
L
L
L
L
Op-Code
MRS
ILLEGAL
H
x
x
x
x
x
DESL
3
..
-
Continue burst to end .... Write recovering
with auto precharge
L
H
H
H
x
x
NOP
Continue burst to end
~
Write recovering
with auto precharge
x
L
H
H
L
H
H
L
L
L
H
L
H
H
L
H
L
H
L
BA, CA, AS
READ/READA
ILLEGAL
L
H
L
L
H
BA, CA, AS
BW/BWA
ILLEGAL
L
H
L
L
L
BA, CA, A8
WRIT/WRITA
ILLEGAL
L
L
H
H
H
BA,RA
ACTWPB
ILLEGAL
3
L
L
H
H
L
BA,RA
ACT
ILLEGAL
3
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA,AS
PRE/PALL
ILLEGAL
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Code
SRS
ILLEGAL
L
L
L
L
L
Op-Code
MRS
ILLEGAL
L
H
Undefined
ILLEGAL
x
BST
ILLEGAL
x
Undefined
ILLEGAL
,
3
375
NEe
,uPD481850
(4/7)
Current state
CS RAS CAS WE DSF
Prechnrging
Address
Command
Action
x
x
x
L
H
H
L
H
H
L
H
H
L
L
x
BST
ILLEGAL
L
H
L
H
H
x
Undefined
ILLEGAL
H
Notes
Nop --> Enter idle after tRP
x
x
DESL
H
x
x
NOP
Nap --> Enter idle after top
L
H
x
Undefined
ILLEGAL
3
L
H
L
H
L
BA,CA,AB
READ/READA
ILLEGAL
3
L
H
L
L
H
BA,CA,AS
BW/BWA
ILLEGAL
3
L
H
L
L
L
BA,CA,AS
WRIT/WRITA
ILLEGAL
3
L
L
H
H
H
BA. RA
ACTWPB
ILLEGAL
3
L
L
H
H
L
BA, RA
ACT
ILLEGAL
3
L
L
H
L
H
x
Undefined
ILLEGAL
L
---L
L
H
L
L
BA,AS
PRE/PALL
Nap --> Enter idle after top
-
L
-L
L
-
---- - -
L
L
I-!
I-!
x
Undefined
ILLEGAL
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
H
Op-Code
SRS
Special register access
L
L
L
L
Op-Cadc
MRS
ILLEGIIL
11
--
Bank
(tOCD)
376
activa1il\~J
H
x
x
x
x
x
DESL
Nap -) Enter bank active after tOCD
L
H
H
H
x
x
NOP
Nop --> Enter bank active after toco
L
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
BST
ILLEGAL
I-I
x
Undefined
ILLEGAL
READ/READA
ILLEGAL
3
BW/BWA
ILLEGAL
3
WRIT/WRITA
ILLEGAL
3
BA,RA
ACTWPB
ILLEGAL
3,10
3,10
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
L
L
L
H
H
L
L
H
H
L
BA,RA
ACT
ILLEGAL
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA,AS
PRE/PALL
ILLEGAL
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Cade
SRS
Special register access
L
L
L
L
L
Op-Code
MRS
ILLEGAL
-,---
OIl,CII,AB
L
--- ---IlII,CA,AB
II
-I3A,CA,AS
L
H
-
3
3
NEe
.uPD481850
(5/7)
Current state
Write recovering
(tope)
H
x
x
x
x
Action
Command
DESL
Notes
Nop -) Enter bank active after tDP1.
L
H
H
H
x
x
NOP
Nap -) Enter bank active after
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
BST
ILLEGAL
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
BA,CA,A8
READ/READA
Begin read; Latch CI\: Determine AP
L
H
L
L
H
BA,CA,A8
BW/BWA
Begin block write; Latcil CA: Detormine AP
L
H
L
L
L
BA. CA, A8
WRIT/WRITA
Begin write; Latch CA: Determine AP
tOPL
3
....
__
.
8
L
L
H
H
H
BA. RA
ACTWPB
ILLEGAL
3
L
L
H
H
L
BA. RA
ACT
ILLEGAL
3
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA,A8
PRE/PALL
ILLEGAL
L
H
H
x
Undefined
ILLEGAL
L
H
L
x
REF/SELF
ILLEGAL
I--
with auto
x
L
L
L
I-- - L
L
Write recovering
Address
CS RAS CAS WE DSF
_.. .
.
-
3
L
L
L
L
H
Op-Code
SRS
Special register access
L
L
L
L
L
Op-Codc
MilS
ILLEGAL
H
x
x
x
x
x
IJI:SI.
L
H
H
H
x
x
NOP
Nap· » Enter IHt:dmruu after lOf'L
L
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
BST
ILLEGAL
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
BA,CA,A8
READ/READA
ILLEGAL
3,8
L
H
L
L
H
BA,CA,A8
BW/BWA
ILLEGAL
3
L
H
L
L
L
BA,CA,A8
WRIT/WRITA
ILLEGAL
3
L
L
H
H
H
BA, RA
ACTWPB
ILLEGAL
3
L
L
H
H
L
BA, RA
ACT
ILLEGAL
3
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA,A8
PRE/PALL
ILLEGAL
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Code
SRS
Special register access
Op-Code
MRS
ILLEGAL
precharge
L
L
L
L
L
--
_.
Nop
\ Ellt!'r
pmGhllr~l(I
oftur
tlll'l
..
3
377
NEe
gPD481850
(6/7)
Current state
CS
Refreshing
H
-
Mode register
accessing
378
RAS CAS WE DSF
x
x
x
x
Address
x
Command
DESL
Action
Nop --> Enter idle after tRe
L
H
H
H
x
x
NOP
Nop --> Enter idle after tRe
L
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
BST
ILLEGAL
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
BA,CA,AS
READ/READA
ILLEGAL
L
H
L
L
H
BA,CA,AS
BW/BWA
ILLEGAL
L
H
L
L
L
BA, CA, AS
WRIT/WRITA
ILLEGAL
L
L
H
H
H
BA,RA
ACTWPB
ILLEGAL
L
L
BA,RA
ACT
ILLEGAL
H
H
L
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA, AS
PRE/PALL
ILLEGAL
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Code
SRS
ILLEGAL
L
L
L
L
L
Op-Code
MRS
ILLEGAL
DESL
Nop -) Enter idle after tFlsc
NOP
Nop --> Enter idle after tRse
H
;.,
:-:
x
x
:.-
--L
H
H
H
x
x
L
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
BST
ILLEGAL
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
BA, CA, AS
READ/READA
ILLEGAL
L
H
L
L
H
BA,CA,A8
BW/BWA
ILLEGAL
L
H
L
L
L
GA, CA, A8
WRIT/WRITA
ILLEGAL
L
L
H
H
II
BA,RA
ACTWPB
ILLEGAL
L
L
H
H
L
BA,RA
ACT
ILLEGAL
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
BA,AS
PRE/PALL
ILLEGAL
L
L
L
H
H
x
Undefined
ILLEGAL
L
L
L
H
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op-Code
SRS
ILLEGAL
L
L
L
L
L
Op-Code
MRS
ILLEGAL
--- ---
Notes
NEe
,uPD481850
(7/71
Current state
Specia I mode
register
CS RAS CAS WE DSF
Address
Command
Action
H
x
x
x
x
x
DESL
L
H
H
H
x
x
NOP
Nap
L
H
H
L
H
x
Undefined
ILLEGAL
L
H
H
L
L
x
SST
ILLEGAL
L
H
L
H
H
x
Undefined
ILLEGAL
L
H
L
H
L
SA,CA,A8
READ/READA
ILLEGAL
L
H
L
L
H
SA, CA. AS
SW/SWA
ILLEGAL
L
H
L
L
L
SA,CA,AS
WRiT/Wf1ITA
ILLEGAL
L
L
H
H
H
SA,RA
ACTWPB
ILLEGAL
L
L
H
H
L
SA, RA
ACT
ILLEGAL
L
L
H
L
H
x
Undefined
ILLEGAL
L
L
H
L
L
SA,A8
PRE/PALL
ILLEGAL
L
L
L
Ii
H
x
Undefined
ILLEGAL
accessing
Notos
Nop ~ Enter previous state after tRse
~
Enter previous state after
. _---- ----- ..
tAse
-------
-_.- ._--_..
-_._-
---....
------
L
L
L
Ii
L
x
REF/SELF
ILLEGAL
L
L
L
L
H
Op·Code
SRS
ILLEGAL
L
L
L
L
L
Op·Code
MRS
ILLEGAL
Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level). IlPD481850 will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA).
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), jlPD481850 will enter Self refresh. All input
buffers except CKE will be disabled.
5. Illegal if tllW is not satisfied.
6.
7.
8.
9.
10.
11.
12.
Illegal if tllAS is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don't satisfy tDPL.
Illegal if tRRD is not satisfied.
Nop to bank precharging or in idle state. May precharge bank(s) indicated by BA (and A8).
Illegal if any bank is not idle.
Remark Legend:
= Low level, x = High or Low level (Don't care), V = Valid Data input,
= Bank address (A9), A8 = Precharge select, RA = Row address, CA = Column address,
Term = Terminate, AP = Auto precharge, NOP = No operation,
H = High level, L
BA
ILLEGAL = Device operation and/or data-integrity are not guaranteed
379
NEe
j1PD481850
4.5 Command Truth Table for CKE
CKE
Current state
n-l
Self refresh
IS.R.)
Self refresh
recovery
POWC!T down
W.D.I
Both bonks idle
Any state other
than listed
above
Cs RAs
CAS WE DSF
Address
Action
Notes
n
H
x
x
x
X
X
X
x
INVALID. CLKln·1) would exit S.R.
H
H
H
x
x
x
x
x
S.R. Recovery
1
L
H
L
H
H
x
x
x
S.R. Recovery
-1
L
H
L
H
L
x
-x
x
ILLEGAL
1
L
H
L
L
x
x
x
x
ILLEGAL
1
L
L
x
x
x
x
x
x
Maintain S.R.
H
H
H
x
x
x
x
x
Idle after IRe
H
H
L
H
H
H
x
x
Idle after tRe
H
H
L
H
H
L
x
x
ILLEGAL
H
H
L
H
L
x
x
x
ILLEGAL
H
H
L
L
x
x
x
x
ILLEGAL
H
L
H
x
x
x
x
x
Begin clock suspend next cycle
H
x
x
Begin clock suspend next cycle
H
L
L
H
H
H
L
L
H
H
L
x
x
ILLEGAL
H
L
L
H
l
x
x
x
ILLEGAL
H
L
L
L
x
x
x
x
ILLEGAL
L
H
x
x
x
x
x
x
Exit clock suspcnd next cycle
L
L
x
x
x
x
x
x
Maintain clock suspend
H
x
x
)(
)(
x
x
L
H
)(
x
x
x
x
x
EXIT P.O .... Idle
INVALID. ClKln·1) would exit P.O.
l
L
x
x
x
x
x
x
Maintain power down mode
H
H
H
x
x
x
x
x
Refer to operations in Operative Command Table
H
H
L
H
x
x
x
x
Refer to operations in Operative Command Tobie
H
H
L
L
H
x
x
x
Refer to operation" in Operative Command Table
H
H
L
L
l
H
L
x
Refresh
H
H
L
L
L
L
x
Op·Code
Refer to operntion" in Operntive Command Table
x
x
x
x
Refer to operntions in Operative Command Table
Refer to operations in Operative Command Table
H
L
H
x
H
L
L
H
x
x
x
x
H
L
L
L
H
x
x
x
Refer to operations in Operative Command Table
H
L
L
L
L
H
L
x
Self refresh
H
L
L
L
L
L
x
Op·Code
Refer to operations in Operative Command Table
L
x
x
x
x
x
x
x
Power down
H
H
x
x
x
x
x
x
Refer to operations in Operative Command Table
H
L
x
x
x
x
x
x
Begin clock suspend next cycle
L
H
x
x
x
x
x
x
Exit clock suspend next cycle
L
L
x
x
x
x
x
x
Maintain clock suspend
1
,
2
2
3
Notes 1. CKE low to High transition will re-enable ClK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
2. Power down and Self refresh can be entered only from the both banks idle state.
3. Must be legal command as defined in Operative Command Table.
Remark legend:
H = High level, l
380
=low level, x =High or low level (Don't care)
NEe
,uPD481850
4.6 Command Truth Table for Two Banks Operation
CS
RAS
CAS
WE
DSF
A9(BA)
AS
A7-AO
Action
"FROM" StateNote '
"TO· StateNato 2
H
x
x
x
x
x
x
x
NOP
Any
L
H
H
H
L
x
x
x
NOP
Any
Any
L
H
H
L
L
x
x
x
(RIW/A)OIl/A)1
AOII/A)1
IOIl/A)1
lOll/A) 1
(R!W/A)1(IJA)O
A111/A)O
I1I1/A)O
1111/A)0
(RIW/A)1 (lJA)O
RP111/A)O
L
L
H
H
L
L
H
L
L
L/H
H
H
CA
H
H
CA
A1(R!W)O
RP1AO
H
L
CA
(RIW/A)111/A)O
R111/A)0
H
L
CA
A1(RIW)O
R1AO
L
H
CA
(RIW/A)OIl/A)1
RPD(I/A)I
L
H
CA
AO(RIW)1
RPOA1
ROII/A)1
L
L
CA
L
L
CA
AO(RIW)1
ROA1
H
H
CA
(RIW/A)1(IJA)O
WP111/A)O
H
H
CA
A1(R!W)O
WP1AO
H
L
CA
(R!W/A)1(I/A)O
W1(IJA)D
H
L
CA
A1(R!W)O
W1AO
(R!W/A)O(VA)1
WPO(l/A)1
L
L
L
L
II
H
H
L
L/H
L
Road
(RIWIA)O(IJA)1
-L
L
BST
Any
Writo/Block Writ"
-H - -CA
CA
H
AO(RIWl1
WPOA1
L
L
CA
(RIW/A)OIl/A)1
WO(l/A)1
L
L
CA
AO(RIW)1
WOA1
H
RA
11AnyO
AIAnyO
L
RA
x
H
x
x
H
x
(RIW/NIl1(I/A)O
1110
H
L
x
(RIW/NIl111/A)0
1111/A)0
H
L
x
II/A) 1(RIW/NIlO
11 (RIW/NIlO
L
L
x
(1lIWINIlO(l/A)1
101l/A)1
L
L
x
(I/A)0(RIWINI)1
10(RIWINIl1
x
x
Refresh
1011
1011
Mode Register
1011
1011
(VA)O(l/A)1
(l/A)01l/A)1
L
L
L
H
L
x
L
L
L
L
L
Op-Code
Activato Row
Precharge
IDAny1
AOAny1
(RIW/NIlOII/A)1
1011
Access
L
L
L
L
H
Op-Code
Special Register
Access
Notes 1. If the JlPD481850 is in a state other than above listed in the "From State" column, the command
is illegal.
2. The states listed under "To" might not be entered on the next clock cycle.
Timing restrictions apply.
381
NEe
pPD481850
Remark Legend:
H = High level, L = Low level, x = High or Low level (Don't care),
BA = Bank address (A9), I = Idle, A = Bank active,
R = Read with No precharge (No precharge is posted)
W = Write with No precharge (No precharge is posted)
RP = Read with auto precharge (No precharge is posted)
WP = Write with auto' precharge (No precharge is posted)
= Any State
Any
XOV1 = BankO is in state "X", Bank1 = in state "V"
(XN)OZ1 = Z1(XN)O = BankO is in state "X" or "V", Bank1 is in state "Z"
5. Initialization
The synchronous GRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100-/lS or longer pause must precede any signal
toggling.
(2) After the pause, both banks must be precharged using the Precharge command (The Precharge all
banks command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed.
After the mode register set cycle, tRSC (20 ns minimum) pause must be satisfied as well.
(4) Two or more CBR (Auto) refresh must be performed.
Remarks 1.
2.
The sequence of Mode register programming and Refresh above may be transposed.
CKE and DaM may be held high until the Precharge command is asserted to ensure databus Hi-Z.
382
NEe
gPD481850
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A9 through AO
as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
A9 through A7
CAS latency:
A6 through A4
Wrap type :
A3
Burst length:
A2 through AO
Following mode register programming, 'no command can be asserted before at least 20 ns (tRse) have
elapsed.
CAS Latency
CAS latency is the most critical ofthe parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade ofthe device. The table on page
52 shows the relationship of CAS latency to the clock period and the speed grade of the device.
Burst Length
Burst Length is the number of words that will bo output or input in a read or write cycle. After a read burst
is completed, the output bus will become Hi-Z.
The burst length is programmable as 1,2,4,8 or full pa!Ju (2!.i6 columns).
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable
as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system.
Some microprocessor cache system are optimized for sequential addressing and others for interleaved
addressing. The table on the page 27 shows the addressing sequence for each burst length using them.
Sequential mode supports bursts of 1, 2, 4 and 8, Interleave mode supports bursts of 4 and 8. Additionally,
sequential sequence supports the full page length.
383
NEe
,uPD481850
7. Mode Register
I
9
8
a
a
9
8
7
1
a
a
9
8
7
1
a
8
I
7
I
4
6
4
6
6
5
V
v
9
8
7
6
a
I
a
a
2
Burst Read and Single Write
Ifor Write Through Cache)
BL
a
2
3
Use in future
1
I
3
I WT I
LTMODE
7
a
a
2
3
JEDEC Standard Test Set Irefresh counter test)
1
I I I
4
5
x
9
I
6
1
I
I
LTMODE
4
3
2
v
v
v
4
3
2
I WT I
a
v
v
I
Vender Specific
V = Valid
a
x- Don't care
J
BL
Mode Register Set
Bits2-O
000
001
010
Burst length
'--
I
I
Wmp type
8
100
101
110
111
R
R
R
Full page
1
Latency
mode
1
2
4
all
01
I
WT-l
R
R
4
8
R
R
R
R
WT=O
J
J
Sequential
Interleave
I
Bits6-4
000
001
010
011
CAS latency
R
1
2
3
101
110
111
R
R
R
1----;-00- -----"R-
Remark R:. Reserved
Mode Register Write Timing
CLK~
CKE
CAS
WE
DSF
AD-AS
"
384
Mode Register Write
NEe
,uPD481850
7.1 Burst Length and Sequence
[Burst of Two]
Starting Address (column
address AD, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0
0, 1
Not support
1
1,0
Not support
--
[Burst of Four]
Starting Address (column
address A1 - AD, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
00
0,1,2,3
01
1,2,3,0
0,1,2,3
1,0,3,2
10
2,3,0,1
2,3,0,1
11
3,0,1,2
3,2,1,0
[Burst of Eight]
Starting Address (column
address A2 - AO, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
000
0, 1,2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1,2,3, 4, 5,6,7,0
1, 0, 3, 2, 5, 4, 7, 6
010
--
011
---
2, 3, 4, 5, 6, 7, 0, 1
2,3,0, 1,6,7, 4, 5
3, 4, 5, 6, 7, 0, 1, 2
3,2, 1, 0, 7, 6, 5, 4
100
4,5,6,7,0, 1,2,3
-
4, 5, 6, 7, 0, 1, 2, 3
----
101
5, 6, 7, 0, 1, 2, 3, 4
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7,0, 1,2,3,4,5,6
7, 6, 5, 4, 3, 2, 1, 0
5, 4, 7, 6, 1,0,3,2
--
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256.
385
NEe
,uPD481850
8. Programming the Special Register
The special register is programming by the Special register set command using address bits A9 through
AO and data bits DOO through D031. The color and mask register retain data until it is reprogrammed or
the device losed power.
The special register has four fields.
A9 through A7
Reserved
Color register: A6
Mask register: A5
A4 through AO
Reserved
Following special register programming, no command can be asserted before at least 20 ns (tRSC) have
elapsed.
Color Register
Color register is used as write data in Block Write cycle. In Special Register set command, if A5 is "0"
and A6 is "1", the color register is selected. And the data of DOO through D031 is stored to color register
as color data (write data).
Mask Register
Mask rDoister is used as write mask data in Write and Block Write cycle. In Special Register set command,
if A5 is" 1" ilild A6 is "0", the mask register is selected. And the data of DOO through D031 is stored to mask
register as write mask data.
Special Register
!J
8
I () I
0
7
I
0
6
5
I LC I LM I
4
3
2
0
I () I
0
o
I
0
I
0
I
Mask Register
Color Register
Remark
386
Bits 5
Function
0
Not Load
1
Load
Bits 6
Function
0
Not Load
1
Load
If LC and LM are both high (1), data of Mask and Color register will be unknown.
NEe
,uPD481850
9. Address Bits of Bank-Select and Precharge
Row
I AO I A1 I A2 I A3 I A4 I A5 I A6 I A7 I AS I A9 I--
I I I
AO
0
r--
(Activate command),
A1
A2
A3
A4
A5
A6
A7
AS
A9
(Precharge command)
.
~:~~~:a~:~~:mmand
Select Bank B
IIActivate" cOlnmand
Result
AS
A9
0
0
0
Precharge Bank A
1
x
Precharge Bank B
'-:-Precharge All Banks
1
x: Don't care
I
-'-
o
disables Auto-Precharge
(End of Burst)
1
enables Auto·Precharge
(End of Burst)
0
enables Read/Write
commands for Bank A
1
enables Read/Write
commands for Bank B
IMIMI~I~IA4IMIMI~IMI~1
Col.
(CAS strobes)
---Prechargll for Bank A
ClK
CKE
CS
I
~
H
Precharge for Banl<
ClK
CKE
~
CS
(l
~
H
-
Precharge for All Banks
ClK
CKE
~
CS
~
H
~
RAS
\\\\\\\\\
11////111
RAS
\\\\\\\\\
/1111/111
RAS
\\\\\\\\\
////1//11
CAS
lllllllll
\\\\\\\\\
CAS
lllllllll
\\\\\\\\\
CAS
lllllllll
\\\\\\\\\
WE
\\\\\\\\\
///1//111
/11////11
/////11//
////11///
\\\\\\\\\
\\\\\\\\\
111/11111
/11/11/11
WE
\\\\\\\\\
DSF
\\\\\\\\\
///11/1/1
11//11//1
AS
\\\\\\\\\
/11//////
AS
2llllllll
\\\\\\\\\
A9
2llllllll
\\\\\\\\\
A9
~
DSF
AS
A9
\\\\\\\\\
\\\\\\\~
\\\\\\\~
WE
DSF
387
NEe
,uPD481850
10. Precharge
The precharge command can be asserted anytime after tRAS(MIN.) is satisfied.
Soon after the precharge command is asserted, precharge operation performed and the synchronqus
GRAM enters the idle state aftertRP is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in
the burst is as follows.
It is depending on the CAS latency.
CAS latency
~
1
CAS latency
~
2 or 3 : One clock earlier than the last read data.
: At the same clock as the last read data.
Burst length~4
TO
T1
T2
T3
T4
T6
T5
T7
ClK
CAS latency
=1
,
,,
Command
,
DO
::~""1Hi-z:
-...............
01
02
03
04
.•..-...••.•.•.•.•.••..••.
I
I
I
I
I
CAS latency
=2
l
I
I
I
'
I
I
I
I
'
I
I
I
I
I
,
Command
DO
:•.•....... ::~:Hi.Z
.•.•.••....
01
02
03
04 .... ...••.....
~
I
,
~....
I
I
CAS latency
,
I
I
=3
~
I
I
,
I
,
@
Command
DO
~
, •......... ::::~""lIi'Z:
...••..... ~..•...•.•.. ~....
01
02
03
04 ...• ~
I
r
I
I
I
I
I
,
I
I
I
I
I
,
,
I
I
I
I
I
I
(tRAS is satisfied)
In orderto write all data to the memory cell correctly, the asynchronous parameter "toPL" must be satisfied.
The tOPL(MIN.) specification defines the earliest time that a precharge command can be asserted. Minimum
number of clocks are calculated by dividing tOPL (MIN.) with clock cycle time.
In summary, the precharge command can be asserted relative to reference clock that indicates the last data
word is valid. In the following table, minus means clocks before the reference; plus means time after the
reference.
CAS latency
388
Read
Write
1
0
+toPL IMIN.I
2
-1
+toPL IMIN.I
3
-1
+loPL IMIN.I
NEe
j1PD481850
". Auto Precharge
During a read or write/block write command cycle, A8 controls whether auto precharge is selected. AS high
in the read or write/block write command (Read with Auto precharge command or Write with Auto precharge
command/Block Write with Auto precharge command), auto precharge is selected and begins after the burst
access automatically.
When the tRAS is not satisfied, the precharge does not start at above timing. And the precharge will start
when the tRAS is satisfied.
The clock that begins the auto precharge cycle is depend on both the CAS latency programmed into the
mode register and whether READ or WRITE/BLOCK WRITE cycle.
11.1 Read with Auto Precharge
When using auto precharge in READ cycle, knowing when the precharge start:; i:; irnJ.lurtant because the
next activate command tothe bank being precharged cannot be executed until the precharge cycle ends. Once
auto precharge has started, an activate command to the bank can be asserted after tRP has been satisfied.
During READ cycle, the auto precharge begins after tRAS and begins on the clock that indicates the last data
word output during the burst is valid (CAS latency of 1) or one clock earlier (CAS latency of 2 or 3).
Burst length __ 11
TO
Tl
T2
T3
T4
-IB
T7
T6
T5
ClK
I
I
I
I
I
I
=1
CAS latency
~EADA~
Command
I
I
I
I
I
DO
CAS latency
~--.-
=3
Command
~EA~A~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
f
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
: Auto precharge starts:
:
:
I
I
I
I
I
I
f
I
,
I
I
I
I
I
I
I
I
I
I
' 1
I
I
I
I
J
: Hi-Z
:
-.. ----T-------..---.. -,..--.. --.. ·
I
I
I
i
~EA~A~
I
I
I
~-
I
I
I
I
I
I
I
I
Hi-Z
· .... ·--rI .. --.... --.... ----..,I...... -.. ---.. -----T .... -......
I
r--.......................,----.. --.. ----.... r---.. ..
I
DO
I
I
I
I
I
:Auto precharge starts:
..------.... . -. ---
I
Command
CAS latency
I
I
I
I
I
I
I
I
I
I
I
=2
DO
,
I
I
I
I
I
I
I
I
I
I
I
I
I
: Auto precharge starts:
:
I
I
I
I
I
I
I
I
I
I
I
I
I
f
I
I
I
I
I
I
I
Hi-Z
. . ---.. ------i----..-----.. .--r. . ---------.. .1----....
·····"r·······
(tRAS
I
is satisfied)
Remark READA means Read with Auto precharge
389
NEe
,uPD481850
11.2 Write with Auto Precharge
In write cycle, the tOAL must be satisfied to assert the all commands to the bank being precharged. And
it is not necessary to know when the precharge starts. In block write cycle, the tBAL must be satisfied to assert
the all commands to the bank being precharged. And it is not necessary to know the precharge starts.
During WRITE cycle, the auto precharge begins after tRAS and begins one clock· after the last data word input
to the device (CAS latency of 1 or 2) or two clocks after (CAS latency of 3).
Burst length = 4
TO
Tl
T2
T3
T5
T4
T7
T6
T8
ClK
1
CAS latency
=1
Command
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DOM
DO
397
NEe
,uPD481850
For CAS latency of 3, the READ and WRITE command interval is [Burst length + 11 cycles. The data bus
must be Hi-Z using DQM before WRITE to avoid data conflict. And DQM must be kept being High from at least
3 clocks to 1 clock before the WRITE command.
ex.) CAS latency
TO
T1
T2
T3
T4
T6
T5
ClK
,,
DOM
I
I
DO
,
,
Command
I
I
Command
I
I
®
®
DOM
I
I
I
I
DO
402
~-----
I
I
I
I
I
I
Hi-Z
I
:
I
I
I
I
I
I
I
.[
1
........ -~ ........ --_ . -.. . t----------- ~ . .-.. ----.... -I
I
I
tRP
I
NEe
,uPD481850
16. Electrical Specifications (Preliminary)
• All voltage are referenced to Vss (GND).
•
After power up, wait morethan 100 J1S and then, execute Power on sequence and Auto Refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Ruting
Unit
VT
-1.0 to +4.6
V
Vee, VeeO
-1.0 to +4.6
V
Short circuit output current
10
50
mA
Power dissipation
Po
1
Operating ambient temperature
TA
o to 70
Tstg
-55 to +125
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Storage temperature
Caution
Condition
W
-----·C
·C
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
3.3
3.6
V
V
Unit
Supply voltage
Vee
3.0
High level input voltage
V,H
2.0
Vee + 0.3
low level input voltage
V,L
-0.3
+0.8
V
70
DC
Operating ---'-"=--j
2.0 V
1.4 V ----------------------0.8 V .-------------
elK
2.0 V .----1.4 V -------------0.8 V .-----
Input
tAC
tC)H
Output
1.4 V
Synchronous Characteristics
11/21
-10
Symbol
Parameter
Clock cyclo time
-12
MAX. MIN.
-15
MAX.
MIN.
MAX.
15
(66MHz)
Unit Note
CAS latency=3
teK3
10 (100MHz
12
(83MHzl
CAS latency=2
tCK2
16
(66MHz)
18
(55MHzl 19.5 (50MHz)
ns
CAS latency=l
teK'
30
(33MHz)
36
(28MHz)
(25MHz)
ns
39
ns
CAS latency=3
tAC3
9
11
14
ns
1
CAS latency=2
tAC'
12
15
16.5
ns
1
CAS latency=l
tACI
27
33
36
ns
1
Access timo from CLK
tell
3.5
CLK low level width
tel
Data-out hold time
tOH
CLK high level width
4
5
3.5
4
5
ns
4
4
4
ns
tLZ
0
tHZ3
4
8
4
8
4
10
ns
CAS latency = 2
tHZ2
4
11
4
11
4
11
ns
CAS latency = 1
tHZ1
4
27
4
27
4
27
ns
Data-in setup time
tDS
3
3.5
3.5
ns
Data-in hold time
tOH
1
1.5
1.5
ns
Address setup time
tAS
3
3.5
3.5
ns
Address hold time
tAH
. 1
1.5
1.5
ns
CKE setup time
teKs
3
3.5
3.5
ns
CKE hold time
teKH
1
1.5
1.5
ns
CKE setup time (Power down exit)
tCKSP
3
3.5
3.5
ns
Data-out high-impedance time
Note 1. Loading capacitance is 30 pF.
0
ns
CAS latency = 3
Data-out low-impedance time
406
MIN.
0
ns
NEe
yPD481850
(2/2)
Synchronous Characteristics
-10
Parameter
-15
-12
Unit Note
Symbol
MIN.
Command (CS, RAS, CAS, WE, DSF, DOM)
MAX. MIN.
MAX.
MIN.
MAX.
tCMS
3
3.5
3.5
ns
tCMH
1
1.5
1.5
ns
setup time
Command (CS, RAS, CAS, WE, DSF, DOM)
hold time
Asynchronous Characteristics
-10
Parameter
-15
-12
Symbol
Unit Note
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
REF to REF/ACT Command period
tRC
100
ACT to PRE Command period
tRAS
70
PRE to ACT Command period
tRP
30
Delay time ACT to READ/WRITE Command
tRCD
30
ns
ns
ACT(O) to ACT(l) Command
p~riod
120
120,000
130
ns
90
120,000 ns
36
39
ns
36
39
ns
120,000
84
tRRD
30
36
39
Data-in to PRE
CAS
lalency~3
tOl'l3
1CLK+10
1CLK,·12
1CLK+15
Command period
CAS latency~2
IDI'l2
15
18
19.5
ns
CAS latency=l
tDPL1
15
18
19.5
ns
Data-in to ACT (REF) CAS latency=3
tDALl
2CLK+30
2CLK+36
2CLK+45
ns
Command period
CAS latency=2
tDAL2
lCLK+30
lCLK+36
lCLK+39
ns
CAS latency=l
tDAL1
lCLK+30
lCLK+36
1CLK+39
ns
Block write cycle time
tBwe
20
24
30
ns
Block write data-in
CAS latency=3
tBPL3
lCLK+20
1CLK+24
lCLK+30
ns
to PRE Command
CAS latency=2
tBPL2
30
36
39
ns
CAS latency=l
tBPL1
30
36
36
ns
CAS latency=3
tBAL3
2CLK+40
2CLK+48
2CLK+60
ns
CAS latency=2
tBAL2
lCLK+40
1CLK+48
_..
lCLK+52
ns
CAS latency=l
tBAL1
lCLK+40
1CLK+48
lCLK+52
ns
Mode'register set cycle time
tRSC
20
Transition time
IT
.--"---
-
(Auto precharge)
period
Block write data-in
Active (REF)
Command Period
(Auto Precharge)
Refresh time
tREF
1
-
20
30
16
1
20
30
16
1
ns
30
ns
16
ms
c
407
23
z
co
16.1
AC Parameters for Read/Write Cycles
AC Parameters for Read Timing (Burst length
Tl
TO
~
T3
T2
= 2,
CAS latency
T4
T5
~
= 2)
T7
T6
TS
T9
no
Tll
n3
T12
r---\,
CLK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
AS
ADD
DOM
0-3
DO
I
I
_____Hj-.L ___
I
I
-------t--------r--------~--
nJ>aJ
~
I
I
g g
~*;
5.
n:IJa>
0(11"
3 .. =>
30.'"
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32lm
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a.
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0
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=>
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mar»
=>
a.
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0l=Io
00
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o
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m
AC Parameters for Write Timing (Burst length = 4. CAS latency = 2)
TO
I
T2
T1
T4
T3
T5
T6
T7
T8
T9
I I
T10
I I I I I I I I I I II n
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
ClK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DOM
0-3
DO
o»m
~ ~Ul
3a;
[CD
~
co
:;~g'
S:s'~
1!0»
6°
II
cg
o»m
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[CD
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5.
co
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9-
a· ~
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......
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l
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16.4 Basic Cycles
16.4.1 Initialization
Power on Sequence and Auto Refresh
I I I I I I I In I I I I I I I I I I I I I I I
TO
CLK
RAS
CAS
DSF
A9
(BA)
AS
T4
I
I
T5
T6
~
I
I
tRSC (~O nsl
'
T8
T9
Tll
Tl2
T13
T14
T15
I
I
I
I
I
I
I
I
I
:
I
I
Tl6
T17
Tl8
T19
T20
I
T21
I
I
~
I
I
•
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
!
7
:
-+-'>
TlO
~~~~~~~~~~~~~
!
! ! ! : !~!
.;!!
:
::
refres~ cycles ,are nec ssary : :
I
:
I
,.--7------!
I
I
I
~. . . . . r..........
(::::;::::::~::::,,};~:;i(~
~ .:«................
:::.:~~~I.W
,.,
b::::::':::::(
~. ... IIQII
V:::::{{~~
~
"""""-I
WE
T3
---t--"1'j !
I
cs
T2
~~~~
;
!:
Hi9h level !s neces~ary
I
CKE
TI
I
I
.~
I
I
I
I
I
I
I
I
I
I
I
I
.&~~::)}~, ~
• •
.~~>
__ i .
I
I
I
I
I
-
~~
~
M$M$tti:{::
'ADDRESS KEY'
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADD
-~/(
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DOM
-t----'),
•
I
•
I
I
L
I
I
I
I
I
:
I
I
I
I
I
I
I
I
r
I
I
I
I
I
I
I
J
r
:
I
I
I
I
I
:
I
:
I
:
I
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
I
I
I
0-3
Hi~h level ~s neces~ary:
HI-Z : _____ !.: _____ :!.. ____ ..!:_____ .!:_____ !.: _____ : ____ -!:_____ ..!:_____ !: _____ !.: _____:!.. ____ ..!:_____ .!: _____ !.: _____ : ____ J:_____ .!:_____ !.: ___ ... _!..: _____I:_____ J:
__ ..!:___
~).l
DO
~
!
t
!
All Banks
Precharge
Mode Regisler
Set Command
Refresh
Command
Command
is necessary
is necessary
is necessary
IRP
~
t
t
Activate
Command
Refresh
Command
is necessary
IRc
IRC
"0
C
~
00
..a
00
U1
o
z
m
16.4.2 Mode Register Set
Mode Register (Burst length = 4, CAS latency = 2)
I TO I Tl I T2 I T3 I T4 I T5 I T6 I T7
i
T8
ClK
CKE
CS
CAS
tAse (20 ns)
:
.....
:
:,
:
:
,
r-+---~-----T'----+---~-----T----+----+-----T----r----+----+---~-----T----+
,
"
I
I
I
I
I
:
.., _
~
DSF
~
I
t
I
e\p
I
:
I
I
I
I
I
I
I
,
I
I
I
I
v<}}\:::
I
WE
I
I
I
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I
I
I
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I
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I
I
I
I
I
I
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I
I
I
$, 1':4 \,*>':'::::::\
•
&a ~:~_r~t~
I
I
I
.
I
1
1
I
I
t i l
I
I
t
I
I
~
A8
..,: ..
ADD
l$mWBI$it~mc)_c~w:::::·:·::·:::~_~:::::::w~
I
I
I
0·3
I
'ADDRESS KEY'
I
I
I
I
I
I
1
:~t~
~::::::;,~
I
I
I
I
L
I
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I
I
I
I
I
I
I
I
I
I
I
1
;
I
;
1
r
I
I
I
I
I
_~:::~i:_;:'~::~:::~:~
I
I
DO
I
:
~;::::::::::::.::
~r):":"}
I
A9
(8A)
DOM
"
,,
H :
:
RAS
I T9 I TlO I Tll I 112 I T13 I T14 I Tl5 I T16 I T17 I T18 I T19 I T20 I T21 I
.
HI-Z
I
I
I
I
I
I
I
I
I
I
~
~
I
I
I
I
I
I
I
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~
~
~
I
I
I
I
1
I
~
~
I
I
I
I
I
1
I
I
I
I
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I
I
I
I
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I
I
~
~
I
I
__J_____ 1_____ ___ __ !... ____ _____ _____ 1. _____ _____ _____ _____ ! __ ___ _____ _____ ___ __1 _____ !. _____ ___ _.L ____ ____ _!. _____ _____ __ ___ J
~
All Banks
Mode
Activate
Precharge
Register
Command
Command
Set
Command
is valid
If necessary
~
~
~
tAP
'"C
C
.;::..
00
....:10
00
(J'1
o
~
w
.J>.
......
z
.J>.
16.4.3 Refresh Cycle
CSR Refresh (CAS latency = 2)
I I I I I I I I
TO
TI
T2
T3
T4
T5
T6
T7
I T8
i9
110
I I I I I I I I I I I I
TIl
Tl2
Tl3
T14
Tl5
Tl6
T17
TIS
T19
T20
~
T21
ClK
CKE
cs
RAS
CAS
WE
DSF
A9
(BA)
AS
ADD
o
DOM
I
DO
:
l
0-3
0
I
II
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
.... _1 .......... L.... ___L........ J........ _1_ ........ L.... ___ L........ J........ _1 __ .... _1 ___ .... L_ ...... J.......... J_ .... __ 1_ ........ L........ _L ........ J...... __ 1__ . . __ 1........ _L --.... J.... -@:r
r
r
Precharge
Command
if necessary
r
CBR refresh
tRP
r
CBR refresh
tRe
Activate
Command
r
Read
Command
tRe
"tJ
C
0l:Io
CO
...
CO
U'I
o
z
~
Self Refresh (entry and exit)
I I I I I
TO
Tl
T2
13
I I I I I I
T7
T4
T8
TS
TlO
Tll
I I I I I I
T12
Tl7
Tl8
TlS
T20
T21
ClK
CKE
cs
RAS
CAS
WE
DSF
AS
IBAl
AS
ADD
DQM
0-3
l(
-
t
DQ
I
I
I
--
I
--I
I
:
I
I
I
))
},-
I
I
...... .! ...... -_! .......... !. ...... __ 1- __ .... J .. __ .. __ .... ~r. .. :. ........ _:... .. __ .. ..!_ ........ .! .... __ .. ! ~
Auto Precharge after Read Burst (3/3) IBurst lengtll ~ 4, CAS latency
I I
TO
Tl
I
T2
I I I I I
T3
T4
T5
T6
T7
I
T8
i
= 3)
~9 I Tl0
I I I
Tll
T12
T13
I
T14
I I I I I
T15
Tl5
T17
T18
T19
I
T20
I
T21
I
ClK
~
----,
~
I
I
I
H
CKE
:
I
I
I
I
-I
I:
I
1
I
:
I
I
I
~
~
----.
----.
1
I
I
I
I
I
-
I
:
t
::
1
I
I
t
,,
,
cs
RAS
CAS
~
1
1
I
I
I
I
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I
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-----.
----.
-,
L
I
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:
I
:
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,
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1
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"
"
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,
t i
L. ______ !
:.:
l
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_I
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l
:.-
~
~
:
I
j:::::,::::::•
t
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___ -.l _____ ~
••
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____ L ______ r ____ I
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f::~:::<. ~:~
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:~~:
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:
/'~ =:.;.;.;"/
<:::;:::
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3:~}i:~\
,
WE
A9
(BA)
-------.
~ . . \ aW@(\d \~ \l~ . . . . .
n~/~~.~:
~
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DSF
----.
V:·:.;:·?:·~
.-::::::::~::::~:'. .
I
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:
I
1
I
I
IR~a~
ADD
I{ R~a _ _ C~ %R~a mWI§t~R C~a ~ C~b ~ R~b _ _ C~b ~
DOM
0-3
/
:
:
:
I
I
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I I !
I
\'$@oomIW'(A~b~, ~
: :
I
I
I
I
Activate Command
for Bank A
I
:
I
ActLte
Command
for Bank B
Bank A
Read Command without
Auto Precharge
Bank 8
Read Command with
Auto Precharge
I
:
:
:
:
:
:
:
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r
I t t
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t
1
1
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1:
I
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I:
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: : :
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L
Z _____ .! _____ !. __________ ~__
____ ~ __H"!:._...:
I
DO
,
R~a*WJ ,w~
I
AS
Bank A
Read Command with
Auto Precharge
t
Auto Precharge
Start for Bank B
::
::
I
I
I
I
1
I
r::::!::-:\r:::::.
--!.-----!..-----L-~b2
Auto
Precharge
Start for
Bank A
Activate Command
for Bank B
L
Bank B
Read Command with
Auto Precharge
""C
C
0l=Io
00
~
00
CJ'I
o
z
rn
n
Auto Precharge after Write Burst (1/3) (Burst length = 4, CAS latency = 1)
1 TO
1 Tl
1 T2
1 T3
1 T4
1 T5
1 T6
1 T7
I
1
I
~
I
I
I
1
1 T8
1 T9
1 TlO 1 T11
l'i2 I
,,3 1 T14 1 T15 I T16 1 Tl7 1 T18 1 T19 1 T20 I T21
1
ClK
CKE
cs
RAS
CAS
WE
H .,
_ _ _1-------'_ _ J
I
I
i
I
I
-----.l _ _ . __ .1
!
1
~_
I
I
J
------.
------.
I
I
I ,
------.
----;
I
L
t ,
~
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:
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J
W __ •
I
I
I
1
I
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___ \
I
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I
J
~ I __
a$Wk:::::::l
m: :Jffiw.~/~~\~
• • ~/"~\~
DSF
A9
(BA)
A8
ADD
DOM
0-3
C"'31~100i :::.~
DO
Activate
Command
for Bank A
Bank A
;:: __ , :..
Command
','.':.:;C'::7"'~~~.::
for Bank B
Bank B
'0',-.:1'.
Write Command without
Write Command \vith
Auto Prechcrge
Auto Precharge
Auto Precharge
Auto Precharge
Start for Bank B
Bank B
WnteCommand
with
Ii
Activate
Command
for Bank A
Bank A
Wllte Command
with
Auto Pre charge
Auto Precharge
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank B
"'C
C
.j:::I.
00
....10
00
(J'1
o
:::
CD
.l>-
z
I\:)
o
Auto Precharge after Write Burst (2/3) (BUTst length = 4, CAS latency
~
= 2)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
TlO
Tll
T12
T13
T14
Tl5
Tl6
Tl7
T18
Tl9
T20
T21
ClK
CKE
cs
RAS
CAS
WE
DSF
A9
(BA)
AS
ADD.
DOM
0-3
DO
t
Activate Command
for Bank A
I
Command
Bank A
for Bank B
Bank B
Write Command without
Write Command with
Auto Precharge
Auto Precherge
."
C
,J:Io
CO
CO
U'I
o
z
Auto Precharge after Write Burst (3/3) (Burst length = 4. CAS latency = 3)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
Til
Tl0
T12
T13
T14
T15
T16
T17
T1S
T19
T20
~
T21
ClK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
AS
ADD
DOM
l
0-3
DO
t
Activate Command
for Bank A
with
Write Command without
BankB
Write Command with
Auto Precharge
Auto Precharge
Auto Precharge
Write Command
Auto Precharge
Start for Bank B
."
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0l:Io
00
....10
00
c.n
Q
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I\J
I\J
z
~
16.4.5 Full Page Mode Cycle
Full Page READ Cycle 11/31 (CAS latency; 1)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
TlO
Tll
T12
T13
T14
T15
T16
T17
Tl8
T19
T20
T21
ClK
CKE
cs
RAS
CAS
WE
DSF
AS
(BA)
AS
ADD
DaM
0-3
DO
t
Activate
Command
for Bank A
I
Activate
Command
for Bank B
Read
Command
for Bank A
Precharge
Command
for Bank B
Burst cannot
end in Full
Page mode
I
Activate
Burst stop
Command
Command
for Bank B
~
""C
C
0l:Io
00
...a
00
UI
o
z
m
n
Full Page READ Cycle (2/31 (CAS latency = 21
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
TlO
TIl
T12
T13
T14
T15
T16
T17
T18
Tl9
120
T2l
ClK
,
CKE
CS
RAS
CAS
WE
DSF
:,
,,,
••
, ••
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A9
(BA)
~
AS
iR~aRBa~~~:~:~:::::~:::»::}:::W:?:~
ADD
DaM
0-3
DO
,
~
I
L
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!::~':::::
I
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li!{R~a.C~.R~a~_c~a.::::::::::}}::::};:::m~R~b _ _
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L____ _
. .':!~~:_____ J_____ 1_ .. ___ L___ J 'n6'" V~1l~.1.1V~A'u.'J'{ rM,,_?
.! _____ l. _____ !... _____
Read
Activate
Read
Comma:-.:::
for Bank;"
Command
Command
E~;s:
for Bank A
for Bank A
E:.-.::J
I
cannot
in Full
Page mode
Activate
Command
Burst stop
Command
for Bank B
IRP
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00
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l
Full Page READ Cycle (3/3) (CAS latency
= 3)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
12
T3
T4
T5
T6
T7
T8
T9
TlO
Tll
T12
T13
Tl4
T15
T16
T17
T18
T19
T20
T21
~
ClK
CKE
cs
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
DQ
Activate
Command
for Bank A
Command
for Bank B
Precharge
Bu ....t stop
Command
Command
for Bank B
tAP
Activate
Command
for Bank B
."
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0l=Io
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....
CO
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~
Full Page WRITE Cycle (1/3) (CAS latency = 1)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
Tl0
Tll
T12
T13
T14
T15
T16
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T19
T20
T21
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CAS
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Precharge
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I
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~
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T14
T15
T16
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T20
T21
CLK
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CAS
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PRE (Precharge) Termination of Burst 11/3) (Burst length = 2. 4. 8. Full. CAS latency = 1)
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T7
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15
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T4
T5
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Clock Suspension during Burst Read (using CKE function) (3(3) (Burst length =
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~.
CAS latency
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I
= 3)
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SUSPENDED
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at end of burst
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T18
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T19
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Clock Suspension during Burst Write (using CKE Function) (2/3) (Burst length
I
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T4
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T5
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CAS latency
I
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T14
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T15
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T16
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T17
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T18
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T19
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T20
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I
I
I
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I
I
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,
,
:
I
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,
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1
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t
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1
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1
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•
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i
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:::::::::::::::
i i i '
.__ ! - - --- ~--- - -!- -- - _J_ -~ DAa 1
Activate
Command
:
I
_
~".'
.. " " " " " " " "
AQMt<.,>:,.~«
RAa
.:.:.>,.:~.
-; ":-:.:.:«
I
I
...:'.." . " " " " " " " ' "
/;:::;:.:::::{\)mij;ij;i$M§$m@,&§t_
A8
DOM
I
" " " " " " " , ' "
....\\
DSF
(BA)
I
1
-,:.~~:::,:{).
........ ,·x"'.....
I
.;,
I
WE
\.....-.J...--I
I
r
DAa2
1-CLOCK
SUSPENDED
X~;:~~::::::})f~~fX DAa3
2-CLOCK
SUSPENDED
I i i
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DAa4 - - 1. - - - - - ~- - ---!- - - -- J __ - --! --- --!.- - - --!...- -- _J __ ---.!
3-ClOCK
SUSPENDED
\:J
C
~
CO
..a
CO
(,TI
o
z
16.4.8 Power Down Mode
Power Down Mode and Clock Suspension (Burst length
TO
Tl
T3
T2
T5
T4
= 4, CAS latency
T8
T7
T6
m
=
I I I I I I I I I I I I I,n
T9
TlO
21
Tll
Tl2
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
CS
RAS
=~::.::::;:::;.~- -~~!!"'"
_~_r:(~_
0~·~"""'b·"~·
I
CAS
WE
DSF
A9
(BA)
I
I
I
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f
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,
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-
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" " ' "
?:::::::::::::::_-
I
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r
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1
I
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~~:::::::::::::-
J
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' i i
.......
I
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1
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~~:::::;:::;:::;;;-...... ......
.-'
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RAa
CAa
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','
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? .................. ;.
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I
I
- ... - - - - - - - - - - _ - - - - - - - _ - _ - _ -. ________________ ...... _......
Activate
Command
for Bank A
,
Power Down
Mode. Entry
;
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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--'-----,
,
,
I
I
I
I
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...... ___ ... __ _ ...... __ ............................................................... -.- ............ ...
r\ I\ ... 'J
Read
Command
for Bank A
Power Down
Mode Exit
ACTIVE STANDBY
-..j
I
I
,
t5
I
_
_""~.:.:-:.;.:.;.:.;""
ADO
00
I
-'~".""'
I
I
I
DOM
0-3
I
I
,
~~"
A8
I
Precharge
Co,.,-:crand
Clock Mask
Start
Clocl; r·.'las~
End
"tI
C
Power Down
Mode Exit
Power Down
Mode Entry
PRECHARGE STANDBY
..j::Io
00
.....a
00
UI
o
.,.
UJ
co
2.
~
16.4.9 Other Cycles
Byte Read/Write Operation (by DaM) (Burst length = 4. CAS latency = 2)
I I I I I I I I I I I I I I I I I I I I I I I
TO
ClK
Tl
T2
T3
T4
T5
T6
T7
T8
T9
Tl0
Tll
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
---f,
~
CKE
:
H
CS
RAS
CAS
WE
DSF
A9
(SA)
A8
ADD
DOMl
DQ 0-7
'"
~I
/Xvv.
~ ~\
,
,
,
----:-----~-----+-,,
,,
,,
I
I
I
I
I
I
I
I
DO 8 - 15 ____ !. _____ !.. _____I_____ J __ _
Activate
Command
for Bank B
Read
Command
for Bank B
-c
Byte of
C
D08-15
not Read
not Read
not Read
-I=ao
00
~
00
U1
o
z
~
Burst Read and Single Write (Burst length
I
TO
I
Tl
I
T2
I
T3
I
T4
I
T5
I
= 4,
T6
I
CAS latency
T7
I
I
T8
= 2)
T9
I
TlO
I
Tl1
112
I
T13
I
T14
I
T15
I
T16
I
T17
I
118
I
Tl9
I
T20
I
T21
I
ClK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DOMO~
. . . .
DOM1~
,
000-7
I
--- -1- - -- •
I
I
. . . .
,
,
,
I
I
I
I
I
I
I
I
I
I
__ J _____ _____ :
L __ _
:~:'
I
___ I_____ 1I _____ 1I _____ L_
_J __
~
DQ8-15
Activate
Command
for Bank B
Read
Command
for Bank B
: G}'
: :
DBe --:------:
,
- 1-\ ~__
""'-r-J
I
I
1
-i- - - - - T-----r
~
~
Single
\/Vrite
Single
Read
Write
Command
Command
Command
"
'
J
I
~LA-L---J
---'----A-J
t
Single
Write
Command
"'tJ
C
~
00
~
00
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CD
~
~
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o
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Special Register Set (Burst length = 4, CAS latency = 2)
I I I I I I I I I I I no I I I I I I I I I I I I
TO
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
ClK
CKE
cs
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0-3
,
I
•
- - - -I- ........... ..f - ...... -
DQ
I
All Banks
Special
Precharge
Command
If necessary
Register Set
Command
I
I
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I
J
111·"-
I
:
I
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+ ..................... -- ........ ..f ........... + .................... -~ ........ -t- .................... +- ........... - .. -- -1-"-
t
Activate
Command
is valid
tAP
Remark Special Register Set command is able to input al any stale.
""C
C
~
...
CO
CO
c.n
o
z
~
Random Row Write with WPB (Pingpong banks) (1/3) (Burst length = 8, CAS latency = 1)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
TlO
Tll
T12
T13
Tl4
T15
Tl6
T17
T18
T19
T20
T21
CLK
CKE
cs
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DOM
0-3
DO
com~and f
Activate
with WPB lor Bank A
Write Command lor Bank A
WPB is enable.
~
Activate Command
lor Bank B
Write Command
lor Bank B
WPB is disable.
Precharge Command
for Bank A
Activate Command
lor BankA
~
Precharge
Command
for Bank B
f.::;: 8;;:-:\: A
v~pa IS
c"s.ab:e.
"'C
~
C
0l=Io
00
00
U1
o
-I»
~
.l'>
.l'>
f\)
l
m
n
Random Row Write with WPB (Ping pong banks) (213) (Burst length
= 8,
CAS latency
= 2)
I I I I I I I I I I I I I I I I I I I I I I I
TO
'ClK
CKE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
----t,
-+, H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DOM
0-3
DO
'--
Activate
Command
withWPB
for Bank A
t
Write
Command
for Bank A
WPB is enable,
Activate
Write
Command
for Bank B
Command
for Bank B
WPB is disable"
Activate
Command
for Bank A
Precharge
Command
for Bank A
tRCO
tDPt
~
tR?
WPB is disable
"tI
C
~
00
~
00
U1
o
z
~
Random Row Write with WPB (Pingpong banks) (3/3) (Burst length = 8, CAS latency = 3)
I I I I I I I I I I I I I I I I I I I I I I I
TO
ClK
CKE
Tl
T2
T3
T4
T5
T6
T7
T8
T9
T10
TIl
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
-:
-+-L
, H
CS
RAS
CAS
WE
DSF
A9
IBAl
A8
ADD
DOM
0-3
DO
Activate
Write Command
for Bank A
WPB is enable.
Command
withWPB
for Bank A
tRCO
!
Activate
Write Command
Write Command
Precharge
Command
for Bank 8
Command
Cco-o-,oc,d
for Bank A
for Bank B
WPB is disable.
for Bank A
fa: B,,,k A
WPB is disable.
Command
for Bank B
;....::.i,'.c~e
Precharge
tRP
tDf't
."
C
.;a.
00
....lo
00
U'I
o
tc.:>
-l>-l>-l>-
z
m
n
Block Write (page at same bank) (CAS latency
TO
I
T1
I
T2
I
T3
I
I
T4
T5
I
T6
= 3)
I
T7
I
T8
I
T9
I
TlO
I
Tll
I
T12
I
T13
I
T14
I
T15
I
T16
I
T17
I
T18
I
T19
I
CLK
CKE
cs
RAS
CAS
WE
DSF
A9
(BA)
AS
ADD
DOM
0-3
I
I
I
I
I
I
I
I
---
~
-,- - - - - - - , -
Column Mask
I
-
t
I
I
.
I
I
I
I
I
I
I
I
I
I
I
J
I
I
I
I
I
I
I
I
I
I
I
I
f
I
DO
Block Write
for Bank B
Activate
Command
tor Bank B
tRCD
Block Write
for Bank B
Block Write
for Bank B
tBWC
tswc
Block Write
for Bank B
tBwe
Precharge
Command
for Bank B
tBf'l
Block Write
Activate
Command
for Bank B
WPB is enable.
withWPB
for Bank B
tf'.?
tRCD
""C
C
~
00
....Jo
00
c.n
o
z
~
Block Write (page at same bank) changing color and mask data (CAS latency = 3)
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
I
TlO
I
Tll
I
T12
I
Tl3
I
Tl4
I
Tl5
I
T16
I
Tl7
I
T18
I
T19
I
ClK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DOM
0-3
DO
"'tJ
Activate
Command
for Bank B
withWPB
Block Write
for Bank B
tReD
Special Register
Write Command
(Mask data)
towe
Block Write
for Bank B
IRse (20 ns)
Special Register
Write Command
(Color data)
lowe
S·o:,; Write
::, 8ank B
Block Write
for Bank B
tRse (20 ns)
b·.:
Activate
Command
for Bank B
Precharge
Command
for Bank B
tBPl
C
~
00
....lo
tACO
00
U'1
Q
tC1l
.;:.
.;:.
OJ
l
~
Interleaved Block Write (CAS latency = 3)
I
TO
I
T2
Tl
I
T7
T6
T5
T4
T3
T8
I
T9
I
TlO
I
I
TlI
T12
I
T13
I
T14
I
Tl5
I
T16
I
Tl7
I
Tl8
I
T19
I
ClK
CKE
,,
cs
RAS
•
CAS
•
WE
•
DSF
A9
(BA)
A8
,
fff$W¥~'fW/
~:)\
~
~.. W!JJ{I9 ~ ~ _ _
~ • • , . . . :~:~
~ • • i~'''':~
\
.., ••
I
I
.~\
~~~
.~/\W"'./~_~~~
_
I
I
ADD
I
I
J
I
I
"
I
I
I
I
RBa: ~
eAa
RAa
I
I
....
r;;t-x~ii$
I
CBa
I
CAb
,
I
DOM
0-3
1
I
I
I
1
I
I
I
:::/\':
;--- :
1
:
---r
I
I
I
'/\'
I
:-
,
I
:
:
:
I
I
_
I
I
I
I
I
I
eBb
I
:
:
:
1
:
I
I
I
I
I
I
RBb
I
I
I
I
J
I
I
I
I
I
/\'I~::::'
/
\
I
I
I
I
I
Colum~Mask
I
"
I
I
I
I
~t~~
I
~
--:----:-- ---
: ------:-- --:-
I
I
':
I
:
:
:
DO
Actate
Command
)
~_A
AcLate
Command
)
prec~arge
1
)
~_B
Block Write
for Bank A
tReD
Block Write
for Bank B
tReD
Block Write
for Bank A
t,wc
Command
AcLate
Command
~_B
~_B
Block Write
for Bank B
tawc
"'tJ
tE:FL
tRP
C
~
00
..a
00
U'1
o
z
~
16.6 Application Cycles
16.6.1 Page Cycles with Same Bank
Random Column Read (Page with same bank) (1/3) (Burst length = 4, CAS latency = 1)
I I I I I I I I I I I I I I I I I I I I I I I
TO
TI
T2
T3
T4
T5
T6
T7
T8
T9
TlO
Tl1
T12
Tl3
Tl4
T15
Tl6
T17
T18
Tl9
T20
T21
ClK
CKE
cs
RAS
CAS
WE
DSF
A9
(BA)
AS
ADD
DOM
0·3
DO
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
)
Read
Command
for Bank A
Precharge
.:-.:: .:;:::;
Ee=:l
Cc:r.rr:ar.d Command Corr.:-:-.and
fo~
Bank A for Bank A for Ea~.;'" A
~
""C
C
.a::.
00
~
00
UI
o
~
.j>.
.j>.
z
(X)
~
Random Column Read (Page with same bank) (2/3) (Burst length = 4, CAS latency = 2)
I I I I I I I I I I I no I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
T8
T9
Tll
T12
,13
T14
T15
T16
T17
T18
T19
T20
T21
ClK
CKE
Cs
RAS
CAS
WE
DSF
A9
IBAI
A8
ADD
DaM
0-3
DO
Activate
Command
lor Bank A
Read
Command
lor Bank A
Read
Command
lor Bank A
Read
Command
lor Bank A
Precharge
Command
lor BankA
Activate
Command
lor Bank A
tAP
Read
Command
lor Bank A
""C
C
.p..
00
00
U1
o
z
~
Random Column Read IPage with same bankl 13/31 (Burst length = 4, CAS latency = 3)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
TS
T9
110
111
112
T13
T14
T15
116
T17
T1S
fc:
82::"1;';"
T19
T20
T2l
ClK
CKE
cs
RAS
CAS
WE
DSF
A9
(BAI
AS
ADD
DOM
0-3
DO
Read Command
for Bank A Read Command
for Bank A
Precharge Command
for Bank A
tAP
Read Command
for Bank A
"tJ
C
.;..
00
....a
00
(J'I
o
t
CD
.p.
z
(J1
o
~
Random Column Write (Page with same bank) (1{3) (Burst length
= 4,
CAS latency
= 1)
I I I I I I I I I I I I I I I I I I I I I I I
TO
Tl
T2
T3
T4
T5
T6
T7
TS
T9
Tl0
T11
T12
T13
T14
T15
T16
T17
TIS
T19
T20
T21
ClK
CKE
cs
RAS
CAS
WE
DSF
A9
(SA)
AS
ADD
DOM
0-3
DO
Activate
Command
for Bank B
Write Command
for Bank B
Wnte Commar,d Wnte Command
for Ban\: B
for Bank B
Precharge
Write Command
Command
for Bank B
for Bank B
Activate Command
for Bank B
~
"'C
C
0l=Io
CO
..a
CO
U1
o
z
~
Random Column Write (Page with same bank) (2/3) (Burst length
I
TO
I
Tl
I
T2
I
T3
I
T4
I
T5
I
T6
I
T7
I
T8
I
T9
I
T10
~
~
2)
T13
I
4, CAS latency
I
T1l
I
T12
I
T14
I
T15
I
T16
I
T17
I
T18
I
T19
I
T20
I
T2l
I
ClK
CKE
H
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DOM
0-3
DO
,,
,
j
- --
,
,
---- -- -- - -----Activate
Command
for Bank B
Write
Write
Wnte
Pre charge
ActIVate
Command
Command
Command
Corr,rr.".o
for Bank B
Command
for Bank 8
Command
for Bank B
for Bank B
for Bank B
to: "",;, 8
tRP
\'.;.:8
""C
C
,J::o.
00
....l
00
(11
o
.j:>.
CJl
.J:>.
c.n
z
f\)
~
= ~,
Random Column Write (Page with same bank) (3/3) (Burst length
I TO I T1 I T2 I T3 I T4 I T5 I T6 I
T7
CAS latency
= 3)
I T8 I T9 I TlO I Tll I T12 I'T13 I T14 I T15 I T16 I T17 I T18 I T19 I T20 I T21 I
ClK
CKE
,
,,
CS
~ ~ ~ V:;:;::::::}X~W_ _Wa _
~
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16.6.2 Cycles with Pingpong Banks
Random Row Read (Pingpong banks) (1/3) (Burst length = 8, CAS latency = 1)
I I I I I I I I I I I I I I I I I I I I I I I
TO
T1
T2
T3
T4
T5
T6
T7
T8
T9
TlO
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T13
T14
T15
T16
T17
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Random Row Read (Pingpong banks) (2/3) (Burst length = 8, CAS latency = 2)
I I I I I I I I I I I I I I I I I I I I I I I
TO
ClK
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Tl
T2
T3
T4
T5
T6
T7
T8
T9
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T12
T13
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T16
T17
T18
Tl9
T20
T21
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CAS latency
tRP
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for Bank B
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Random Row Read (Pingpong banks) (3/3) (Burst length = 8, CAS latency = 3)
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for Bank B
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T17
T18
T19
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T2
T3
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110
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T17
118
119
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= 2, CAS latency = 1)
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T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
113
T14
T15
T16
T17
T18
T19
T20
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16.6.3 READ and WRITE Cycles
READ and WRITE (1/31 (Burst length
= 4,
CAS latency
= 11
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TO
T1
T2
T3
T4
T5
T6
T7
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O-clock latency
2-clock latency
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READ and WRITE (2/31 (Burst length = 4, CAS latency = 21
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T15
T16
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T19
T20
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O-clock latency
f
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Interleaved Column READ Cycle (1/3) (Burst length = 4, CAS latency = 1)
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T2
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T3
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T4
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I I I I I I I I I I I I I I I I I I I I I I I
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T2
T3
T4
T5
T6
T7
T8
T9
Tl0
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T12
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T14
T15
T16
T17
T18
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T21
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Interleaved Column READ Cycle (3/3) (Burst length = 4, CAS latency = 3)
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T2
T3
T4
T5
T6
T7
T8
T9
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Tll
112
T13
T14
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T16
T17
T18
119
T20
T21
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for Bank B
for Bank A
for Bank B
for Bank A
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tRCO
tARO
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Interleaved Column WRITE Cycle 11/31 (Burst length = 4, CAS latency = 11
I I I I I I I I I I I I I I I I I I I I I I I
TO
ClK
Tl
T2
T3
T4
T5
T6
T7
T8
T9
TlO
Tl1
T12
T13
Tl4
T15
T16
T17
Tl8
Tl9
T20
T21
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for Bank A
~
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for Bank B
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Interleaved Column WRITE Cycle (2/3) (Burst length = 4, CAS latency = 2)
I
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T2
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T3
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T4
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T5
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tor Bank B
Write
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tor Bank B
Write
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tor Bank B
Write
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Precharge
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tor Bank B
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Interleaved Column WRITE Cycle (3/3) (Burst length = 4, CAS latency = 3)
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T3
T4
T5
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T6
T7
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T14
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T16
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T20
T21
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0-3
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for Bank A
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for Bank B
Activate
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tRCO
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tOPL
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full Page Random Column Read (Burst length
z
~
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Tl
T2
T3
T4
T5
T6
Full Page, CAS latency
T7
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I I I I I I I I I I I I I I
T9
TlO
Tll
T12
Tl3
T14
T15
T16
T17
T18
T19
T20
T21
ClK
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cs
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CAS
WE
DSF
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(BA)
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DOM
0-3
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for Bank A
Activate
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Read
Command
for Bank B
for Bank B
Read
Command
Read
Command
Read
Command
Read
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Precharge Command
Command
CC.'1~;-nand
for Bank A
for Bank A
for Bank B
for Bank A
fe; Bank B
for Bank B
(PRE Termination)
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full Page Random Column Write (Burst length ~ Full Page, CAS (atency ~ 2)
I I I I I I I I I I I I I
TO
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tll
T12
113
I I I I I I I I I
T14
T15
T16
T17
T18
T19
T20
T21
ClK
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cs
RAS
CAS
WE
DSF
A9
(8A)
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ADD
DOM
0-3
DO
Activate
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for Bank A
Activate
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for Bank B
Write
Command
for Bank B
Write
Write
Command
Command
for Bank A
for Bank A
Write
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for Bank B
Write
Command
for BankA
Write
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for Bank B
Precharge Command
for Bank B
(PRE Termination)
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G
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
0.913~8:88~
A
23.2±0.2
B
20.0±0.2
0.7B7~8:88~
C
14.0±0.2
0.551 ~8:88~
0
17.2±0.2
0.B25
0.575
0.677±0.00B
0.032
0.023
F
G
H
0.32~g:8~
0.013±0.003
0.005
0.026 (T.P.)
K
0.13
0.65 (T.P.)
1.6±0.2
L
0.B±0.2
0.031~8:88~
M
0.17~g:8g
0.007±0.002
N
0.10
2.7
0.125±0.075
3 0 +70
-3°
3.0 MAX.
0.004
0.106
0.005±0.003
P
Q
R
S
0.063±0.00B
0.119MAX.
S100GF-65-JBT
471
NEe
18. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the ,uPD481850.
Type of Surface Mount Device
jlPD481850GF-JBT: 100-pin Plastic QFP (14 x 20 mml
472
gPD481850
Source Exif Data:
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