1995_NEC_Dynamic_RAM_Module 1995 NEC Dynamic RAM Module
User Manual: 1995_NEC_Dynamic_RAM_Module
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NEG Electronics Inc.
NEe
Dynamic RAM Module
Fall 1995 Data Book
Document No. M10584EJ1VODBU1
©1995 NEC Electronics Inc. All rights reserved.
Printed in the United States of America.
No part of this document may be copied or reproduced in anyfonn or by any means withoutthe prior consent of NEC Electronics Inc. (NECEL).
The infonnation in this document is subject to change without notice. Devices sold by NECEL are covered by the warranty and patent
indemnification provisions appearing in NECEL Tenns and Conditions of Sale only. NECEL makes no warranty, express, statutory, implied
or by description, regarding the information setforth herein or regarding the freedom of the described devices from patent infringement. NECEL
makes no warranty of merchantability or fitness for any purpose. NECEL assumes no responsibility for any errors that may appear in this
document. NECEL makes no commitment to update or to keep current information contained in this document. The devices listed in this
document are not suitable for use in applications such as, but not limited to, aircraft, aerospace equipment, submarine cables, nuclear reactor
control systems and life support systems. If customers intend to use NEC devices in these applications or they intend to use "standard" quality
grade NEC devices in applications not intended by NECEL, please contact our sales people in advance. "Standard" quality grade devices are
recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial
robots, audio and visual equipment, and other consumer products. "Special" quality grade devices are recommended for automotive and
transportation equipment, traffic control systems, anti-disaster and anti-crime systems, etc.
Index
I
Selection Guide
II_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--.:1~
4 Byte SIMM I--~--l Fast Page ,
_ _ _ _ _ _ _ _ _ _ _ _~13~
Hyper Page (EDO) 1 _ _ _ _ _ _ _ _~l~O~l
ISmall Outline DIMM 11----------- ------
151
8 Byte DIMM 1---.----1 Fast Page 1 _ _ _ _ _ _ _ _ _ _ _----=:20~3
Hyper Page (EDO) r-_ _ _ _ _ _ _ _~2~9~9
I Timing Chart II_ _ _ _ _ _ _ _ _'----_ _ _ _ _ _~36~5
iii
...-------NOTES FOR CMOS DEVICES--------.
CD
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
®
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to Voo or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
®
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
iv
Contents
Selection Guide ".................. I. I..... I... I..... I............... I.....................
1
4 Byte SIMM................................................................................ 13
4 Byte SIMM
Hyper Page
(EDO)
MC-421000A32BA,421000A32FA........
15
MC-421000A32, 421000A36 SERIES ....
25
MC-422000A32BA, 422000A32FA ........
43
MC-422000A32, 422000A36 SERIES ....
53
MC-424000A32, 424000A36 SERIES....
69
MC-428000A32, 428000A36 SERIES ....
85
MC-421000F32........................................ 103
MC-422000F32........................................ 115
MC-424000F32........................................ 127
MC-428000F32........................................ 139
Small Outline DIMM ................................................................. 151
SODIMM
MC-42S 1000LAD32S SERIES ............... 153
MC-42S2000LAB32S SERIES ............... 163
MC-42S2000LAD32S SERIES ............... 173
MC-42S4000LAB32S SERIES ............... 183
MC-42S4000LAC32S SERIES ............... 193
v
8 Byte DIMM ............................................................................. 203
8 Byte DIMM
MC-421000AA64FA ............................... 205
MC-421000AA64FB ................................ 217
MC-421000AD72F................................... 227
MC-422000AA64FB ................................ 237
MC-422000AB72F ................................... 249
MC-422000LAB72F (3.3 V) .................... 259
MC-424000AB72F ................................... 269
MC-424000AC72F................................... 279
MC-424000LAB72F (3.3 V) .................... 289
Hyper Page
(EDO)
MC-421000FA64FB ............................... 301
MC-422000FA64FB ................................. 313
MC-422000FB72F.................................... 325
MC-422000LFB72F (3.3 V) .................... 335
MC-424000FC72F.................................... 345
MC-424000LFC72F (3.3 V) .................... 355
vi
Timing Chart 1 ........................................................................... 365
Timing Chart 2 ........................................................................... 375
Timing Chart 3 ........................................................................... 385
Timing Chart 4 ........................................................................... 397
Timing Chart 5 ........................................................................... 409
Timing Chart 6
419
Timing Chart 7 ............ ...... ......................................................... 429
Timing Chart 8 .. ........... ...... ....................... .............. ............... ..... 443
Timing Chart 9 .. ...... ...... ...... .................... ......... .......... ............. ... 457
Timing Chart 10 ......................................................................... 473
vii
Synchronous DRAM DIMM .................................................. ;...TBD
Synchronous DRAM DIMM
MC-4S2AA72
MC-4S2BA72
MC-4S4BA72
MC-4S4BC72
TBD
TBD
TBD
TBD
TBD
viii
Selection Guide
Part Number
72-pin SIMM
MC-42 2000 A 32 F - 60
-r-
-.--
-r-
--
NEC CMOS _ _--II
DRAM MODULE
Depth in K unit - - - - - - - '
1000: 1M
2000: 2M
4000: 4M
8000: 8M
Function(MAX. 2 digits) - - - - - - '
1st digit: Function
A: Fast Page
F: Hyper Page (EDO)
2nd digit: Detail of Function
Organization - - - - - - - - - - - '
32: x 32
36: x 36
Package Description(MAX. 2 digits) - - - - - - I
1st digit: General Description
F: Socket type (Gold plating)
B: Socket type (Solder coating)
2nd digit: Detail of Package
Access T i m e - - - - - - - - - - - - - - I
60: 60ns
70: 70ns
80: 80ns
2
72-pin SO DIMM
;
IV~A:
3.3 V±O.3 V
MC-42 S 1000 L AA 32- SA
- A60
--
NECCMI
-,,-
DRAM MODULE
Self Refresh _ _ _.....J
Depth in K unit - - - - - - - '
1000: 1M
2000: 2M
4000: 4M
Function (2 digits) _ _ _ _ _ _ _....J
1st digit: General Function
A: Fast Page
2nd digit: Detail of Function
B: 2K Refresh, x 8 devices
C: 2K Refresh, x 4 devices
D: 1K Refresh, x 16 devices
Organization - - - - - - - - - - - - - '
32: x 32
Package Description (2 digits) - - - - - - - - - - '
1st digit: General Description
S: Small Out-line DIMM
2nd digit: Detail of Package
A: Gold, 1 inch
Access Time ----------------~
60: 60ns
70: 70ns
80: 80ns
3
168-pin 8 Byte DIMM
.----------.,r-vcc
V ± 0.25 V
I -L-A::5.0
3.3 V ± 0.3 v
I
MC-42 S 4000 L AB 72 F - A60
NECCMI -
-r-- -,- -,
DRAM MODULE
Self Refresh _ _ _- I
Depth in K unit - - - - - '
1000: 1M
2000: 2M
4000: 4M
Function (2 digits) - - - - - - - - - '
1st digit: General Function
A: Fast Page
F: Hyper Page (EDO)
2nd digi t: Detail of Function
A: lK Refresh, Parity or Non parity
B: 2K Refresh, ECC
C: 4K Refresh, ECC
D: 1K Refresh, ECC
Organization _ _ _ _ _ _ _ _ _ _ _--1
64: x 64
72: x 72
Package Description (MAX. 2 digits) - - - - - - '
1st digit: General Description
F: Socket type (Gold plating)
2nd digit: Detail of Package
-: TSOP, linch (First product)
Alphabetical order in the same
configuration and function
Access Time - - - - - - - - - - - - - - - - 1
60: 60ns
70: 70ns
80: 80ns
4
200-pin 8 Byte SDRAM DIMM
MC-45 4AA 72F-A lOL
NEC CMOS _ _--,I
SDRAM MODULE
Depth in M unit------l
1 : 1M
2 :2M
4:4M
8 : 8M
16: 16M
Function (2 digits) - - - - - - I
1st digit: Interface & Buffering
A: L VTfL, Unbuffered
B: LVTfL, Buffered
2nd digit: Bank & Write mode
A: Single bank, Word Write
B: Single bank, Byte Write
C: Dual bank, Word Write
D: Dual bank, Byte Write
I
Power
-: Normal
L: Low Power
' - - - CLK Cycle Time
10 : IOns
12: 12ns
13 : 13ns
L--.---Vcc
A: 3.3 V ± 0.3 V
B:RFU
Organization _ _ _ _ _ _ _ _---4
64: x 64
72: x 72
80: x 80
Package Description (MAX. 2 digits) -----'
1st digit: General Description
F: Socket type (Gold plating)
2nd digit: Detail of Package
-: First product
5
0'1
72-pin SIMM Fast Page Line-up (x 32)
Organization
Part Number
Access Time
Refresh
Cycle
(ns)
MC-421000A32B
MC-421000A32F
lMx32
MC-421000A32BA
MC-421000A32FA
MC-422000A32B
2Mx32
MC-422000A32F
4Mx32
8Mx32
MC-424000A32B
MC-424000A32F
I
60,70.80
Single
side
G/P
1 K/16 ms
Double
side
5.0 :!:
0.5V
60.70.80
Double
side
Single
side
60.70.80
2 K/32 ms
60.70.80
Double
side
Remark
Height
SIC
G/P
60,70,80
100
Monolithic Device
Package
Edge
Mounted
side
connector
Single
s'de
MC-428000A32B
MC-428000A32F
Supply
Voltage
60,70,80,
100
MC-422000A32BA
MC-422000A32FA
I
SIC
SIC
G/P
SIC
Org.
Pkg.
Amt.
lMx4
300 mil SOJ
8
1Mx 16
400 mil SOJ
2
1Mx4
300 mil SOJ
16
1Mx16
400 mil SOJ
4
4Mx4
300 mil SOJ
8
4Mx4
300 mil SOJ
16
1 inch
G/P
SIC
G/P
SIC
G/P
SIC: Solder Coated. G/P: Gold Plated
72-pin SIMM Fast Page Line-up (x 36)
Organization
Part Number
Access Time
Refresh
Cycle
Supply
Voltage
(ns)
lMx36
MC-421000A36BJ
70,80,100
MC-421000A36FJ
MC-421000A36BE
lK116 ms
MC-421000A36FE
Package
Monolithic Device
Edge
Mounted
connector
side
SIC
Single
side
G/P
Double
side
G/P
SIC
Remark
Height
(inch)
Org.
Pkg.
Amt.
1.25
lMx4
1Mx1
300 mil SOJ
300 mil SOJ
8
4
1.0
1Mx4
lMx1
300 mil SOJ
300 mil SOJ
8
4
I
,
2Mx36
5.0±
0.5V
70,80,100
MC-422000A36BJ
MC-422000A36FJ
MC-424000A36BJ
4Mx36
MC-424000A36FJ
MC-424000A36BE
Single
side
60,70,80
2K/32 ms
MC-424000A36FE
8Mx36
MC-428000A36BJ
MC-428000A36FJ
Double
side
60,70,80
Double
side
Double
side
SIC
1.25
1Mx4
lMxl
300 mil SOJ
300 mil SOJ
16
8
1.25
4Mx4
4Mxl
300 mil SOJ
300 mil SOJ
8
4
1.0
4Mx4
4Mx 1
300mil SOJ
300mil SOJ
8
4
1.25
4Mx4
4Mxl
300 mil SOJ
300 mil SOJ
16
8
G/P
SIC
G/P
SIC
G/P
SIC
G/P
i
I
II
I
I
SIC: Solder Coated, G/P: Gold Plated
~
co
72-pin SIMM Hyper Page (EDO) Line-up
Organization
Part Number
Access Time
Refresh
Cycle
I
!
Supply
Voltage
,
(ns)
MC-421000F32BA
1Mx32
Package
Edge
Mounted
connector
side
Single
side
60, 70
MC-421000F32FA
1 1 InAIlIMAX.)
tRCD
>
tRCD IMAX.)
and tRCD ~ tRCD (MAX.)
Access Time
Access Time from RAS
tRAe IMAX.)
IRAC IMAX.)
!AA IMAX.)
tRAD
+ tM IMAX.)
tCAC IMAX.)
tRCD
+ tCAC IMAX.)
tRAO (MAX.) and tRCO (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA ortcAc) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAO ;:: tRAO (MAX.) and tRCO ;:: tRCO
(MAX.) will not cause any operation problems.
11. Loading conditions are 1 TTL and 100 pF.
12. tOFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not referenced
to VOH or VOL.
13.
14.
15.
16.
tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
Either tRCH (M)N.) or tRRH (MIN.) should be met in read cycles.
In early write cycles, tWCH (MIN.) should be met.
tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles.
17. If twcs ;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
22
Timing Chart
Please refer to Timing Chart 1, page 365.
23
NEe
MC·421000A32BA, 421000A32FA
Package Drawing
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
1c=J
DO
>-
0
J
o
c
E
o
o
detail of
® Part
1F
••
0>
ITEM
A
B
C
0
E
G
H
MILLIMETERS
107.95±0.13
101.19
44.45
6.35
INCHES
4.250±0.006
3.9S4
1.750
0.250
44.45
1.750
10.16
1.27 (T.P.)
0.400
0.050 (T.P.)
0.250
M
6.35
2.03
6.35
25.4
N
P
5.0S MAX.
R1.57
0.200 MAX.
RO.062
S
4>3.1S
4>0.125
T
1.27~g:6s
0.050±0.004
v
0.25 MAX.
1.04±0.05
3.15 MIN.
3.17 MIN.
K
W
X
V
24
--W--T
O.OSO
0.250
1.000
0.010 MAX.
0.041 ±0.002
0.124 MIN.
0.124 MIN.
M72B·50A46
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC-421000A32, 421000A36 SERIES
1 M-WORD BY 32-BIT, 1 M-WORD BY 36-BIT DYNAMIC RAM MODULE
FAST PAGE MODE
Description
The MC-421000A32 series is a 1,048,576 words by 32 bits dynillllic: IlAM lTlodulo on which 8 pieces of
4 M DRAM: /-lPD424400 are assembled.
The MC-421000A36 series is a 1,048,576 words by 36 bits dynamic HAM lTlodulo
011
which 8 pieces of
4 M DRAM: JLPD424400 and 4 pieces of 1 M DRAM: /-lPD421000 are assemhl()d.
These modules provide high density and large quantities of mOlT1ory in a small spaco without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
•
1,048,576 words by 32 bits organization (MC-421000A32 series)
•
1,048,576 words by 36 bits organization (MC-421000A36 series)
•
Fast access and cycle time
Power consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-421000A32-60
60 ns
120 ns
5,280 mW
MC-421000A32-70
70 ns
140 ns
4,400 mW
44mW
MC-421000A32-80
80 ns
160 ns
3,960 mW
(CMOS level input)
MC-421000A32-10
100 ns
190 ns
3,520 mW
MC-421000A3S-70
70 ns
140 ns
6,1.S0 mW
6SmW
(CMOS level input)
Family
Active
MC-421000A36-80
80 ns
1S0 ns
5,500 mW
MC-421000A3S-10
100 ns
190 ns
4,840 mW
•
1,024 refresh cycles/16 ms
•
CAS before RAS refresh, RAS only refresh, Hidden refresh
• 72-pin single in-line memory module (Pin pitch
•
Standby
= 1.27 mm)
Single +5.0 V ±0.5 V power supply
• Access time can be distinguished with characteristics of PD-pins (PDO to PD3)
The information in this document is subiect to change without notice.
M10424EJ3VODSOO (Japan)
25
NEe
MC-421000A32, 421000A36 SERIES
Ordering Information
[MC-421000A32 series)
Pmt number
Access time
(MAX.)
MC·421000A32B-60
60 ns
MC·421000A32B-70
70 ns
MC-421000A32B-80
80 ns
MC-421000A32B-l0
100 ns
MC-421000A32F-60
60 ns
MC-421000A32F-70
70 ns
MC-421000A32F-80
80 ns
MC-421 000A32F-l 0
100 ns
Package
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
Mounted devices
8 pieces of JlPD424400LA
(300 mil SOJ)
[Single side]
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Gold plating
[MC-421000A36 series]
Purt nurnbcr
MC-421000A36BE-70
Access time
(MAX.)
70 ns
Package
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
MC-421000A36BE-80
80 ns
MC-421000A368E-l0
100 ns
MC-421000A36FE-70
70 ns
Mounted devices
8 pieces of JlPD424400LA
(300 mil SOJ)
4 pieces of JlPD421000LA
(300 mil SOJ)
72-pin Single In-line Memory Module
(Socket Type)
[Double side]
Edge connector: Gold plating
MC-421000A36FE-80
80 ns
MC-421000A36FE-l0
100 ns
MC-421000A368J-70
26
70 ns
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
8 pieces of JlPD424400LA
(300 mil SOJ)
MC-421000A368J-80
80 ns
4 pieces of JlPD421000LA
MC-421 000A36BJ-l 0
100 ns
(300 mil SOJ)
MC-421000A36FJ-70
70 ns
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Gold plating
MC-421000A36FJ-80
80 ns
MC-421000A36FJ;10
100 ns
[Single side]
NEe
MC-421000A32, 421000A36 SERIES
Pin Configuration
[MC-421000A32 series]
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating. Gold plating)
GND
1/00
1/016
1/01
1/017
1/02
1/018
1/03
1/019
Vee
NC
AO
Al
A2
A3
A4
A5
A6
NC
1/04
1/020
1/05
1/021
1/06
1/022
1/07
1/023
A7
NC
Vee
A8
A9
NC
RAS2
NC
NC
NC
NC
JiliQ
CASO
CAS2
CAS3
CASl
RASO
NC
NC
WE
NC
1/08
1/024
1/09
1/025
1/010
1/026
1/011
1/027
1/012
1/028
Vee
1/029
1/013
1/030
1/014
1/031
1/015
NC
PDO
PDl
PD2
PD3
NC
GND
1
2
3
4
5
6
o
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
AO - A9
Address Inputs
1/00 - 1/031
Data Inputs/Outputs
CASO - CAS3
Column Address Strobe
RASO.RAS2
Row Address Strobe
WE
Write Enable
Vee
Power Supply
GND
Ground
NC
No connection
54
55
56
57
58
59
60
61
62
63
The internal connection of PO pins (PDO to PD3)
depends on access time.
64
65
66
67
68
69
70
71
72
o
Access Time
Pin
Name
Pin
No.
60
POD
67
GNO
GNO
GNO
GNO
POl
68
GNO
GNO
GNO
GNO
P02
69
NC
GNO
NC
GNO
P03
70
NC
NC
GNO
GNO
ns
70
ns
80
ns
100
ns
27
NEe
MC-421000A32, 421000A36 SERIES
[MC-421000A36 series)
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating, Gold plating)
GND
1
2
1/01
4
1/00
1/018
1/019
1/02
1/020
1/03
1/021
Vee
NC
AO
Al
A2
A3
5
6
7
8
9
10
11
12
13
14
15
A9
1/026
1/08
34
35
36
A6
NC
1/04
1/022
I/O~
1/013
IIOG
1/024
1/07
1/025
A7
NC
Vee
A8
NC
RAS2
1/017
1/035
GND
CAS!!
CAS2
C8S3
CASl
RASO
NC
NC
WE
NC
1/09
1/027
1/010
1/028
1/011
1/029
1/012
1/030
1/013
1/031
Vee
1/032
1/014
1/033
1/015
1/034
1/016
NC
PDO
PDl
PD2
PD3
NC
GND
28
3
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A4
A5
o
33
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
AO - A9
Address Inputs
1/00 - 1/035
CASO - CAS3
Column Address Strobe
Data Inputs/Outputs
RASO, RAS2
Row Address Strobe
WE
Write Enable
Vee
Power Supply
GNO
Ground
No connection
NC
55
56
57
58
59
60
61
62
63
64
The internal connection of PO pins (POO to P03)
depends on access time.
65
66
67
68
69
70
71
0 - 72
o
Access Time
Pin
Name
Pin
No.
70 ns
80 ns
100 ns
PDO
67
GND
GND
GND
GND
PD1
68
GND
GND
GND
GND
PD2
69
NC
GND
NC
GND
PD3
70
NC
NC
GND
GND
NEe
MC-421000A32, 421000A36 SERIES
Block Diagram
[MC-421000A32 series]
RASO
CASO
~
1/00
1/01
1/02
1/03
~
1/04
1/05
1/06
1/07
~
1/01
1/02
1/03
1/04
OE
1/01
1/02
1/03
1/04
OE
CASl
1/08
1/09
1/010
1/011
1/01
1/02
1/03
~
~
1/012
1/013
1/014
1/015
~
i
CAS RAS
Remark 00 - 07 : jlP0424400
00
+
+
CAS RAS
01
i
CAS RAS
02
~4
1/01
1/02
1/03
1/04
DE
RAS2
CAS2
+
+
CAS RAS
03
-.i
1/01
1/02
1/03
1/016
1/017
1/018
1/019
~
1/020
1/021
1/022
1/023
:Jr
CAS RAS
04
~4
1/01
1/02
1/03
1/04
+
+
CAS RAS
05
BE
CAS3
t
1/01
1/02
1/03
1/04
1/024
1/025
1/026
1/027
:Jr
1/028
1/029
1/030 '"'
1/031
~
CAS RAS
06
6E
1/01
1/02
1/03
1/04
-.i
i
CAS RAS
07
JIE
AO - A9 0 ) - - - - - - - , 00 - 07
WE 0
• 00-07
Vee 0
~
'00 - 07
:r: CO - C,7
GNO 0 ) - - - - - -.....
-+-0------- 00 - 07
29
NEe
MC-421000A32, 421000A36 SERIES
[MC-421000A36 series]
RASO
CASO
1/00
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CASl
Q
-.
o·
Q.
• RAS!
1/01
1/02
1/03
CAS
DO
~4
~
1/01
1/02
1/03
1/04
(}-o
(}-o
+
+
CAS
RAS
01
OE
r--1 Dou!
DIN
t
t
CAS
RAS
MO
Q
1/09
1/010
1/011
1/012
~
(}-o-(}-o-
1/013
1/014
1/015
1/016
Q.
()~
--
---.
----.
1/01
1/02
1/03
-- - . IfQ4
+
+
CAS
RAS
02
; ; - - b""I
1/01
1/02
1/03
1/04
.,
.,
CAS
RAS
03
OE
r--1 Dour
DIN
1/017
RAS2
CAS2
Q
1/018
1/019
1/020
1/021
Q.
Q.
Q.
Q.
1/022
1/023
1/024
1/025
Q.
.,
j
CAS
11I\S
M1
Q
CI\S
RAS
04
1/026
CAS3
1/027
1/028
1/029
1/030
06
1/031
1/032
1/033
1/034
CAS
07
CAS
1/035
AO-A9
WE
Vee
GND
30
RAS
Q
Q
Q
Q
..
l
RAS
M3
DO - D7, MO - M3
DO-D7,MO-M3
T
.
DO-D7,MO-M3
CO - C11
.
DO-D7,MO-M3
Remark DO - D7
: JlPD424400
MO - M3 : JlPD421 000
NEe
MC-421000A32, 421000A36 SERIES
Electrical Specifications Notes 1,2
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
50
mA
Output current
10
Power dissipation
Po
MC-421000A32
8
MC-421000A36
12
W
Operating ambient temperature
TA
o to +70
°C
Storage temperature
T~IIJ
-55 to +125
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability_
Recommended Operating Conditions
Symbol
Parameter
Condition
MIN.
TYP.
5.0
MAX.
Unit
Supply voltage
Vee
4.5
5.5
V
High level input voltage
V,H
2.4
Vee + 1.0
V
Low level input voltage
VIL
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
°C
MAX.
Unit
Capacitance ITA = 25°C, f
= 1 MHz)
[MC-421000A32 series]
Parameter
Input capacitance
Data Input/Output capacitance
Symbol
Test Condition
MIN.
TYP.
Cil
AO - A9
68
C"
WE
76
CIJ
RASO, RAS2
43
C"
CASO - CAS3
29
CliO
1/00 - 1/031
17
pF
MAX.
Unit
pF
[MC-421000A36 series]
Parameter
Input capacitance
Data Input/Output capacitance
Symbol
Test Condition
MIN.
TYP.
Cil
AO - A9
88
C"
WE
104
C"
RASO, RAS2
57
C"
CASO - CAS3
36
CliOI
1/00 - 1/07, 1/09 - 1/016,
pF
1/018 - 1/025, 1/027 - 1/034
CliO'
1/08, 1/017, 1/026, 1/035
17
pF
22
31
NEe
MC-421000A32, 421000A36 SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[MC-421000A32 series)
Parameter
Operating current
Standby current
Symbol
Icc,
Icc2
Operating current
lee3
Icc.
(Fast page mode)
-'
CAS before RAS
ICC!,
refresh current
MAX.
RAS, CAS Cycling
tRAC = 60 ns
960
tRC = tRC IMIN.'
10 = 0 mA
tRAC = 70 ns
800
tRAC = 80 ns
720
tRAC = 100 ns
640
RAS, CAS ~ V," IMIN.'
RAS, CAS
RAS only refresh current
MIN.
Test condition
~
Vee - 0.2 V
RAS Cycling
CAS ~ V,H IMIN.'
tRC = tRe IMIN.'
10 = 0 mA
RAS " VIL IMAX." CAS Cycling
trc = trc IMIN.I
10 = 0 mA
10 = 0 mA
16
10 = 0 mA
8
tRAe = 60 ns
960
tRAC = 70 ns
800
tRAC = 80 ns
720
tRAe = 100 ns
640
tRAC = 60 ns
720
tRAC = 70 ns
640
tilAe = 80 ns
560
tilAC = 100 ns
480
RAS Cycling
tilAe = 60 ns
960
= tRC fMI~1.I
tRAe = 70 ns
800
tRAe = 80 ns
720
tRAe = 100 ns
640
tRC
10 = 0 mA
Input leakage current
I""
V, = 0 to 5.5 V
All other pins not under test = 0 V
Output leakage current
32
Unit
Notes
mA
3,4,7
mA
mA
3,4,5,7
mA
3,4,6
mA
3,4
-10
+10
}1A
+10
}1A
lOlL'
Vo = 0 to 5.5 V
Output is disabled (Hi-Z)
-10
High level output voltage
VOH
10 = -5.0 mA
2.4
Low level output voltage
VOL
10 = +4.2 mA
V
0.4
V
NEe
MC-421000A32, 421000A36 SERIES
[MC-421000A36 series]
Parameter
Operating current
Symbol
Icc,
Test condition
MIN.
MAX.
tRC = tRC IMIN.)
tRAC = 70 ns
1,120
tRAC = 80 ns
1,000
tRAC = 100 ns
880
10 = 0 mA
Standby current
Icc2
RAS, CAS
~
V,H IMIN.)
RAS, CAS ~ Vcc - 0.2 V
RAS only refresh current
Icc3
CAS
~
VIII IMIN,I
== tne
(MIN,)
10 = 0 mA
Operating current
Icc.
10= 0 mA
24
10 = 0 mA
12
tRAC = 70 ns
1,120
tRAC = 80 ns
1,000
tRAC = 100 ns
880
Icc5
tRAC = 70 ns
920
tRAC = 80 ns
800
tRAC = 100 ns
680
= tRC (MIN.I
tRAC = 70 n5
1,120
tRAC = 80 nu
-_....
tRAC = 100 115
1,000
10 = 0 mA
Input leakage current
Ii Il)
V, = 0 to 5.5 V
All other pins not under test = 0 V
Output leakage current
lOll)
3,4,7
mA
mA
3,4,5,7
mA
3,4,6
mA
3,4
RAS Cycling
tRC
refresh current
mA
RAS 5 VILIMAX,h CAS Cycling
tpc = tpc IMIN,)
10 = 0 mA
CAS before RAS
Notes
RAS Cycling
tAC
(Fast page model
Unit
RAS, CAS Cycling
Vo = 0 to 5.5 V
Output is disabled (Hi-Zl
High level output voltage
VOH
10 = -5.0 mA
Low level output voltage
VOL
10 = +4.2 mA
880
-10
+10
pA
-10
+10
pA
2.4
V
0.4
V
33
NEe
MC-421000A32, 421000A36 SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8. 9
[MC-421000A32 series)
Symbol
Parameter
tRAe = 60 ns tRAe = 70 ns tRAe
=80 ns
tRAe
=100 ns
ReadiWrite Cycle Time
tRe
120
140
160
190
Fast Page Mode Cycle Time
tpe
40
45
50
60
Accoss Time from RAS
tRAe
Access Time from CAS
teAe
Access Time Column Addross
tAA
Access Time from CAS Procharge
tAep
35
RAS to Column Addross Delay Time
tRAD
15
CAS to Data Setup Time
telz
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
15
0
15
0
20
0
tT
3
50
3
50
3
50
3
10,000
70
Transition Time (Rise and Fall)
~-
Unit
Notes
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
.-
RAS Prcclwrge Time
60
tRP
50
tRAS
60
tRASP
60
tnsu
20
ns
ns
70
80.
15
20
20
30
35
40
40
45
55
ns
11
50
ns
10
ns
11
25
ns
12
50
ns
30
15
35
0
17
40
0
60
100
17
ns
10. 11
25
ns
10. 11
50
ns
10. 11
0
'70
80
ns
80
10,000 100 10,000
ns
80
125,000 100 125,000
ns
20
25
ns
~---
RAS Pulse Width
--
RAS Pulse Width (Fast Page Modo)
c-=RAS Hold Time
1---
--
teAs
15
test!
60
RAS to CAS Delay Time
tRCD
20
CAS to RAS Precharge Time
teRP
10
CAS Precharge Time
tCPN
10
CAS Precharge Time (Fast Page Modo)
tep
10
RAS Precharge CAS Hold Time
tRPC
10
RAS Hold Time from CAS Prechargo
tRHep
Row Address Setup Time
tASR
Row Address Hold Time
CAS Pulso Width
1-=..CAS Hold Time
34
--
-
125.000
70
10,000
125,000
20
10,000
20
10,000
70
40
20
20
10,000
80
50
25
25
10,000
100
60
25
ns
ns
75
ns
10
10
10
ns
13
10
10
10
ns
10
10
10
ns
10
10
10
ns
35
40
45
55
ns
0
0
0
0
ns
tRAH
10
10
12
12
ns
Column Address Setup Time
tASe
0
0
0
0
ns
Column Address Hold Time
teAH
15
15
15
20
ns
Column Address Lead Time Referenced to RAS
tRAl
30
35
40
50
ns
Read Command Setup Time
tRes
0
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
10
10
10
10
ns
14
Read Command Hold Time Referenced to CAS
tReH
0
0
0
0
ns
14
WE Hold Time Referenced to CAS
10
tWCH
15
15
15
20
ns
15
Data-in Setup Time
tDS
0
0
0
0
ns
16
Data-in Hold Time
tDH
15
15
15
20
ns
16
Write Command Setup Time
twes
0
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tesR
10
10
10
10
ns
CAS Hold Time (CAS before RAS Refresh)
teHR
15
15
15
20
ns
WE Setup Time
twSR
10
10
10
10
ns
WE Hold Time
tWHR
15
15
15
20
Refresh Time
tREF
16
16
16
ns
16
ms
NEe
MC-421000A32, 421000A36 SERIES
[MC-421000A36 series]
Parameter
Symbol
tRAe
= 70 ns
tRAe
= 80 ns
tRAe
= 100 ns
Unit
Notes
MIN. MAX. MIN. MAX. MIN. MAX.
Read/Write Cycle Time
tRe
140
160
190
ns
Fast Page Mode Cycle Time
tpe
45
50
60
ns
Access Time from RAS
tRAe
70
80
100
ns
10, 11
Access Time from CAS
tCAC
20
20
25
ns
10, 11
Access Time Column Address
1M
35
40
50
ns
10, 11
Access Time from CAS Precharge
IACP
40
45
55
ns
11
RAS to Column Address Delay Time
tRAD
15
50
ns
10
CAS to Data Setup Time
ICLZ
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
15
0
20
0
tT
3
50
3
50
3
35
17
40
17
;---
Transition Time (Rise and Fall)
0
ns
11
25
ns
12
50
ns
0
RAS Precharge Time
tRP
60
70
80
RAS Pulse Width
tRAS
70
10,000
80
10,000 100 10,000
RAS Pulse Width (Fast Page Mode)
tRASP
70
12~.OOO
80
125,000 100
RAS Hold Time
tRSH
20
CAS Pulse Width
teAS
20
CAS Hold Time
tesH
70
-.
10,000
20
-
20
25
25,000
25
10,000
80
50
ns
25
ns
ns
10,000
100
60
ns
ns
ns
RAS to CAS Delay Time
tReD
20
ns
10
CAS to RAS Precharge Time
teRP
10
10
10
ns
13
CAS Precharge Time
tePN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tep
10
10
10
ns
RAS Precharge CAS Hold Time
tRPe
10
10
10
RAS Hold Time from CAS Precharge
tRHep
40
45
55
ns
Row Address Setup Time
IASR
0
0
0
ns
---
25
75
ns
--
Row Address Hold Time
tRAH
10
12
12
ns
Column Address Sotup Time
lAse
0
0
0
ns
Column Address Hold Timo
teAH
17
20
20
ns
Column Address Lead Timo Roforonced to RAS
tRAL
35
40
50
ns
Read Command Setup Timo
IRCS
0
0
0
ns
Read Command Hold Time Reforonced to RAS
tRRH
10
10
10
ns
14
Read Command Hold Time Referenced to CAS
tReH
0
0
0
ns·
"14
WE Hold Time Referenced to CAS
tweH
15
15
20
ns
15
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tDH
15
20
20
ns
16
Write Command Setup Time
twes
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tesR
10
10
10
ns
CAS Hold Time (CAS before RAS Refresh)
teHR
15
15
20
ns
WE Setup Time
twsR
10
10
10
ns
WE Hold Time
twHR
15
Refresh Time
tREF
--
15
16
20
16
ns
16
ms
35
NEe
MC-421000A32, 421000A36 SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 J1S and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. ICC1, IcC3, IcC4 and IcC5 depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. IcC3 is measured assuming that all column address inputs are held at either high or low.
6. IcC4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. IcCl and IcC3 are measured assuming that address can be changed once or less during RAS:5 VIL
(MAX.! and CAS 2! VIH (MIN.!.
S. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
"---'-"--~------i
i
V,L IMAX)
=0.8 V
,
- - _____ _______
I•
I
, ,
,
: :
I
I
I
-~-
tT : : : 5 ns
I
: :
I
tT = 5 ns
(2) Output timing specification
VOII IMIN)
= 2.4 V
--------~
... --- -
VOL (MAX) = 0.4 V -----------.--
)--
'--------I
10. For read cycles, access time is defined as follows:
Input Conditions
Access Time
tRAD
:5
tRAD (MAX.) and tRCD
:5
tRAD
>
tRAD (MAX.) and tRCD
:5 tRCD (MAX.)
tRCD
>
tRCD (MAX.)
tRCD (MAX.)
Access Time from RAS
tRAC (MAX.)
tRAC (MAX.)
tAA(MAX.)
tRAD
+ tAA (MAX.)
tCAC(MAX.1
tRCD
+ tCAC (MAX.)
tRAO(MAX.! and tRCO(MAX.! are specified as reference points only; they are not restrictive operating
parameters'. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAO 2! tRAO (MAX.I
and tRCO 2! tRCO (MAX.I will not cause any operation problems.
11. Loading conditions are 2 TTLs and 100 pF.
12. tOFF (MAX.! defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13. tCRP (M(N.! requirements should be applied to RAS/CAS cycles.
14. Either tRCH (MIN.! or tRRH (MIN.! should be met in read cycles.
15. In early write cycles', tWCH (MIN.! should be met.
16. tos (MIN.! and tOH (MIN.I are referenced to the CAS falling edge in early write cycles.
17. If twcs 2! twcs (MIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
36
Timing Chart
Please refer to Timing Chart 2, page 375.
37
NEe
MC-421000A32, 421000A36 SERIES
Package Drawings
[MC-421000A32B,421000A32F)
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
---=--:----------I'i '111
!'f4-I'
s
0000 ' ~ ,
0000
r
c
o
o
detail of
® Part
~x
[8J
M72B-50A2'-'
ITEM
MILLIMETERS
INCHES
A
107.95±0.13
4.250±0.006
B
101.19
3.984
C
4445
1.750
D
6.35
0.250
-E
_ _0".
44.45
1.750
10.16
0.400
H
1.27 (T.P.)
0.050 (T.P.)
I
6.35
0.250
J
2.03
0.080
K
6.35
0.250
G
38
4-T
E
M
25.4
1.000
N
5.08 MAX.
0.200 MAX.
P
R 2.0
R 0.079
S
~3.'8
~0.125
T
1.27~g:~8
0.050±0.004
U
6.5 MIN.
0.255 MIN.
V
0.25 MAX.
0.010 MAX.
W
1.04±0.05
0.041 ±0.002
X
2.54 MIN.
0.100 MIN.
y
3.75 MIN.
0.147 MIN.
NEe
MC-421000A32, 421000A36 SERIES
(Not Applicable)
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
11--1
.----!--IDS
----------I
---------"'--:
,
n
I
DDorJOOOD
DODD .
y
,
I ,
1
JA)~
OJ
c
CJCJCJCJ_-I,
'
; --I-I-T
E
D
o
o
M72B-50A19-1
detail of
® Part
W
~x
[E]>
ITEM
MILLIMETERS
INCHES
A
107 ,95±0, 13
4,250±0,006
B
101,19
3,984
C
44.45
1.750
D
6,35
0,250
E
44.45
1,750
G
10,16
0.400
H
1.27 (T.P.)
0.050 (T. P.)
I
6.35
0.250
J
2.03
0.080
K
6.35
0.250
M
25.4
1.000
N
5.08 MAX.
0.200 MAX.
P
R 2.0
R 0.079
S
~3.18
~0.125
0.050±0.004
T
1.27:8~B
U
5.32 MIN.
0.209 MIN.
V
0.25 MAX.
0.010 MAX.
W
1.04±0.05
0.041 ±0.002
X
2.54 MIN.
0.100MIN.
Y
3.75 MIN.
0.147 MIN.
39
NEe
MC-421000A32, 421000A36 SERIES
[MC-421000A36BE.421000A36FE]
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
N
000000
e
o
i;:, ~ :'0
,
00000
o
i,
[
I
[
I
I
"
I
r - - r - - .. -
detail 011 f\) part
ITEM
I--- I-
M72B-50A33-1
INCHES
A
107.95±0.13
4.250±0.O06
B
101.19
3.984
I--- II--- l-
40
MILLIMETERS
e
44.45
1.750
D
6.35
0.250
E
44.45
1.750
G
10.16
0.400
H
1.27 (T.P.)
0.050 (T.P.)
I
6.35
0.250
J
2.03
0.080
K
6.35
0.250
M
25.4
1.000
N
9.0 MAX.
0.355 MAX.
P
R 1.57
R 0.062
S
113.18
110.125
T
1.27:8 ~B
0.050±0.004
U
6.0 MIN.
0.236 MIN.
0.010 MAX.
V
0.25 MAX.
W
1.04±0.05
0.041 ±0.002
X
2.54 MIN.
0.100 MIN.
NEe
MC-421000A32, 421000A36 SERIES
[MC·421000A36BJ.421000A36FJ]
72 PIN SINGLE IN·LlNE MODULE (SOCKET TYPE)
A
F- [:: ::][:: :::];:::: ::]
III
B
S
ill
000000000
:.~
@
[EJ
C
D
E
0
0
detail of
® Part
4px
[EJ
.------ITEM
MILLIMETERS
A
M72B·50A23·2
INCHES
107.95±0.13
4.250±0.006
3.984
B
101.19
C
44.45
1.750
D
6.35
0.250
E
44.45
1.750
G
10.16
0400
H
1.27 IT.P.I
0.050 (T. P.I
I
6.35
0.250
J
2.03
0.080
K
6.35
0.250
M
31.75
1250
N
5.08 MAX.
0.200 MAX.
P
R 2.0
R 0.079
S
~3.18
~0.125
T
1.27~g·JB
0.050±0.004
U
3.78 MIN.
0.148 MIN.
0.010 MAX.
V
0.25 MAX.
W
1.04±0.05
0.041 ±0.002
X
2.54 MIN.
0.100 MIN.
41
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC·422000A32BA, 422000A32FA
2 M-WORD BY 32-BIT DYNAMIC RAM MODULE
FAST PAGE MODE
Description
The MC-422000A32BA, 422000A32FA are 2,097,152 words by 32 bits dynamic RAM module
6n which 4 pieces
of 16 M DRAM: jlPD4218160 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
2,097,152 words by 32 bits organization
•
Fast access and cycle time
Power consumption
Access time
R/W cycle time
(MAX.)
(MIN.)
MC-422000A32-60
60 ns
110 ns
1,7S2 mW
MC-422000A32-70
70 ns
130 ns
1,672 mW
Family
(MAX.)
Active
Standby
22 mW
(CMOS level input)
SO ns
MC-422000A32-S0
•
1,024 refresh cycles/16 ms
•
CAS before RAS refresh, RAS only refresh, Hidden refresh
1,562 mW
150 ns
72-pin single in-line memory module (Pin pitch = 1.27 mm)
•
Single +5.0 V ±C.5 V power supply
Access time can be distinguished with characteristics of PD-pins
(PD~
to PD3)
The information in this document is subject to change without notice.
Ml0501EJ2VODSOO (Japan)
43
NEe
MC-422000A32BA, 422000A32FA
Ordering Information
I'art number
MC-422000A32BA-60
MC-422000A32BA-70
44
Access time
(MAX.)
60 ns
70 ns
Package
72-pin Single In-line Memory Module
(Socket Type)
Mounted devices
4 pieces of .uPD4218160LE
(400 mil SOJ)
Edge connector: Solder coating (HAL)
MC-422000A32BA-80
80 ns
MC·'122000A32FA-60
60 ns
MC·422000A32FA-70
70 ns
MC·422000A32FA-80
80 ns
[Double side]
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Gold plating
NEe
MC-422000A32BA, 422000A32FA
Pin Configuration
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating. Gold plating)
o
GND
1/00
1/016
1/01
1/017
1/02
1/018
1/03
1/019
Vee
NC
AO
Al
A2
A3
A4
A5
A6
NC
1/04
1/020
1/05
1/021
1/06
1/022
1/07
1/023
A7
NC
Vee
A8
A9
RAS3
RAS2
NC
NC
NC
NC
37
CASO
CAS2
CAS3
CASl
B8SQ
RASl
40
Jlli.Q
~~
NC
1/08
1/024
1/09
1/025
1/010
1/026
1/011
1/027
1/012
1/028
Vee
1/029
1/013
1/030
1/014
1/031
1/015
NC
PDO
PDl
PD2
PD3
NC
GND
38
39
41
42
43
44
45
46
47
48
49
50
51
52
53
AO - A9
1/00 - 1/031
CASO - CAS3
RASa - RAS3
Address Inputs
WE
Vcc
Write Enable
Power Supply
GND
NC
Ground
No connection
Data Inputs/Outputs
Column Address Strobe
Row Address Strobe
54
55
56
57
The internal connection of PO pins (PDO to PD3)
depends on access time.
58
59
60
61
62
Access Time
64
Pin
Name
Pin
No.
60 ns
70 ns
80 ns
66
PDO
67
NC
NC
NC
PDl
68
69
NC
NC
NC
PD2
NC
GND
NC
PD3
70
NC
NC
GND
63
65
67
68
69
70
71
72
o
NEe
MC-422000A32BA, 422000A32FA
Block Diagram
WE
~
RASO
CAS1
,
~
CASO
1/00 0 - 1/01 0 - 1/02 0 - 1/03 0 - 1/04 0 - 1/05 0 - 1/06 0 - 1/07 0 " - 1/08 0 - 1109 0 - 1/010 0---1/011 0---1/012 0 - 1/013 0 - 1/014 0---1/015 0 - -
RAS1
1
!
!
1/0 1 LCAS UCAS RAS WE
1/02
1/03
1/04
1/05
1/06
1107
1/08
1/09
1/010
11011
1/012
1/013
1/014
1/015
1/016
00
OE
I71r
1
1/01 LCAS UCAS RAS WE
1/02
1/03
1/04
1/05
1/06
1/07
1/08
02
1/09
1/010
1/011
1/012
1/013
1/014
1/015
1/016
OE
-:rn-
~
a
+
1/016 0 - - .
I/O 17 0 - - .
1/018 0 - 1/019 0---1/020 0 - 1/021 0---1/022 0---1/023 0 - 1/024 0---1/025 0 - 1/026 0 - 1/027 0---1/028 0 - 1/029 0---1/030 0 - 1/031 a - -
~RAS3
1
!
+
1/0 1 LCAS UCAS RAS WE
1/02
1/03
1/04
1/05
1/06
1/07
1/08
1/09
1/010
I/O 11
1/012
1/013
1/014
1/015
1/016
1/02
1/03
1/04
1/05
1/06
1107
1/08
1/09
I/O 10
1/011
1/012
1/013
1/014
1/015
1/016
01
OE
AO-A90
Vee a
""7tr
Remark DO - 03: 1LP04218160
03
OE
• 00-03
:::t: CO-o3 00-03
GNO a T . 00-03
46
1
1/0 1 LCAS UCAS HAS WE
""7tr
NEe
MC-422000A32BA, 422000A32FA
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
mA
Power dissipation
PD
4
W
Operating ambient temperature
TA
a to +70
'C
Storage temperature
TsIg
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthisspecification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Condition
Symbol
MIN.
TYP.
5.0
MAX.
Unit
Supply voltage
Vee
4.5
5.5
V
High level input voltage
V,H
2.4
Vee + 1.0
V
Low level input voltage
VIL
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
'c
MAX.
Unit
Capacitance (TA
=25 'c, f =1 MHz)
Parameter
Input capacitance
Data InpuVOutput capacitance
Symbol
Test Condition
MIN.
TYP.
40
CII
AO - A9
C'2
WE
48
C'3
RASa - RAS3
22
C'4
CASO - CAS3
29
CliO
1/00 -1/031
26
pF
pF
47
NEe
MC-422000A32BA, 422000A32FA
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Standby current
Test condition
Symbol
Iccl
Icc2
Operating current
Icc,
Icc.
tRAC
324
tRAC
304
RAS, CAS <: V,H (MIN.)
= 0 mA
10 = 0 mA
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
RAS Cycling
CAS <: V,H (MIN.)
tRC = tRC (MIN.)
10 = 0 mA
RAS $
10
CAS before HAS
Icc!,
refresh current
48
VIlIMAX.),
CAS Cycling
tpc = tpc !M\f~ )
(Fast page mode)
Input leakage current
Ii (l)
Output leakage current
10(1(
High level output voltage
VOII
Low level output voltage
VOL
= 60 ns
= 70 ns
tRAC = 80 ns
MAX.
RAS, CAS Cycling
tRC = tRC (MIN.)
10 = 0 mA
RAS, CAS <: Vcc - 0.2 V
RAS only refresh current
MIN.
= 0 mA
I~AS Cycling
tllC = tRC (MIN.)
10 = 0 mA
Unit
Notes
mA
3,4,7
284
8
10
mA
4
324
304
mA
3,4,5,7
mA
3,4,6
mA
3,4
284
184
164
144
324
304
284
V, = 0 to 5.5 V
All other pins not under test" 0 V
-10
+10
JJA
Vo = 0 to 5.5 V
Output is disabled (I-li-Z)
-10
+10
J1A
I"" -2.5 mA
2.4
I" = +2.1 mA
V
0.4
V
NEe
MC-422000A32BA, 422000A32FA
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
tRAC = 60 ns
tRAC = 70 ns
Notes 8, 9
tRAC = 80 ns
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
Notes
MAX.
ReadlWrite Cycle Time
tRC
110
130
150
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Access Time from RAS
tRAC
60
70
80
ns
10,11
Access Time from CAS
tCAC
15
20
20
ns
10,11
Access Time Column Address
tAA
30
35
40
ns
10,11
Access Time from CAS Precharge
tACP
35
40
45
ns
11
RAS to Column Address Delay Time
tRAD
15
30
15
35
17
40
ns
10
CAS to Data Setup Time
IcLz
13
a
a
15
a
a
11
tOFF
a
a
ns
Output Buffer Turn-off Delay Time from CAS
15
ns
12
Transition Time (Rise and Fall)
IT
3
50
3
50
3
50
ns
RAS Pre charge Time
tRP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
70
125,000
80
125,000
ns
10,000
20
10,000
20
RAS Hold Time
tRSH
15
CAS Pulse Widlh
ICAS
15
CAS Hold Time
ICSH
60
50
60
18
ns
20
70
ns
10,000
80
ns
ns
RAS 10 CAS Delay Time
IRCD
20
CAS to RAS Precharge Time
leRP
5
5
CAS Pre charge Time
ICPN
10
10
CAS Precharge Time (Fast Page Mode)
Icp
10
10
10
ns
RAS Precharge CAS Hold Time
IRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
35
40
45
ns
Row Address Setup Time
IASA
a
a
a
ns
Row Address Hold Time
IRAH
10
10
12
ns
Column Address Setup Time
IASC
a
0
0
ns
Column Address Hold Time
ICAH
15
15
15
ns
Column Address Lead Time Referenced 10 RAS
IRAl
30
35
40
ns
a
a
Read Command Setup Time
IRes
Read Command Hold Time Referenced 10 RAS
IRAH
Read Command Hold Time Referenced 10 CAS
IRCH
a
a
a
WE Hold Time Referenced 10 CAS
twCH
Data-in Selup Time
45
20
50
25
60
ns
10
5
ns
13
10
ns
0
ns
ns
0
a
a
ns
14
10
10
15
ns
15
IDS
a
a
a
ns
16
Dala-in Hold Time
IDH
10
15
15
ns
16
17
Wrile Command Selup Time
Iwes
a
a
a
ns
CAS Selup Time (CAS before RAS Refresh)
leSR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
teHA
10
10
10
ns
WE Hold Time
IWHR
15
Refresh Time
IREF
15
16
15
16
14
ns
16
ms
49
NEe
MC-422000A32BA, 422000A32FA
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute eight CAS before RAS or RAS only refresh
cycles as dummy cycles to initialize internal circuit.
3. ICC1, Icc3, Icc4 and Iccs depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.
7. ICCl and Icc3 are measured assuming that address can be changed once or less during RAS::; VIL (MAX.)
and CAS
~
VIH (MIN.).
B. AC measurements assume IT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
Vit.
IM.N.)
=2.4 V
·--------..~·.. ·,·i
i
_______________
V" IMAX.) = 0.8 V
-
I
I
I
,
,
I
I
It = 5 ns
I
: :;..
: :
-:
-~-;o_--
tr = 5 ns
(2) Output timing specification
VOH
IM'N.)"
2.4 V -----.--~
.. -..
VOL
IMAX, =
0.4 V --------------
}-
'-------I
10. For read cycles, accoss time is defined as follows:
Input Conditions
IRAD $ IRAD IMAX.)
tRAD
>
tRCD
> IRCD (MAX.)
tRAD IMAX.)
Access Time
Access Time from RAS
and
tRCD $ IRCD (MAX.)
lRAC (MAX.)
tRAC(MAX.}
and
tRCD $ tRCD (MAX.)
IAA (MAX.)
tRAD
+ 1M (MAX.)
tCAC (MAX.)
tRCO
+ tCAC (MAX.)
tRAO (MAX.) and tRco (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAO ~ tRAO (MAX.) and tACO ~ tACO
(MAX.) will not cause any operation problems.
11. Loading conditions are 1 TTL and 100 pF.
12. tOFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not referenced
to VOH or VOl.
13.
14.
15.
16.
17.
50
tCAP (MIN.) requirements should be applied to RAS/CAS cycles.
Either tACH (MIN.) or tAAH (MIN.) should be met in read cycles.
In early write cycles, tWCH (MIN.) should be met.
tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles.
If twcs ~ twcs (M}N.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
Timing Chart
Please refer to Timing Chart 1, page 365.
51
NEe
MC-422000A32BA, 422000A32FA
Package Drawing
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
'1'1
[==1
s
N
B
I" .
CJ.
>-
J
[8J
D
C
O[::=~
E
[:~
detail of
® Part
1fr-
•
[BJ>
ITEM
A
B
C
0
MILLIMETERS
107.95±0.13
101.19
INCHES
4.250±0.006
3.984
44.45
6.35
1.750
0.250
44.45
10.16
1.27 (T.P.)
6.35
2.03
6.35
25.4
9.0 MAX.
R1.57
q'l3.18
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.000
0.355 MAX.
RO.062
q'l0.125
T
1.27~g:68
0.050±0.004
v
0.25 MAX.
1.04±0.05
3.15 MIN.
3.17 MIN.
0.010 MAX.
0.041±0.002
0.124 MIN.
0.124 MIN.
M72B-50A45
D
E
G
H
K
M
N
P
S
W
X
Y
52
-4-T
DATA SHEET
NEe
D05A (Japan)
MOS INTEGRATED CIRCUIT
MC-422000A32, 422000A36 SERIES
2 M-WORD BY 32-BIT, 2 M-WORD BY 36-BIT DYNAMIC RAM MODULE
FAST PAGE MODE
Description
The MC-422000A32 series is a 2 097 152 words by 32 bits dynamic RAM module on which 16 pieces of
4 M DRAM (JIPD424400) are assembled.
The MC-422000A36 series is a 2 097 152 words by 36 bits dynamic RAM module on which 16 pieces of
4 M DRAM (JIPD424400) and 8 pieces of 1 M DRAM (JIPD421000) are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
.2097 152 words by 32 bits organization (MC-422000A32 series)
.2097 152 words by 36 bits organization (MC-422000A36 series)
• Fast access and cycle time
Access time
(MAX.)
Family
R/W cycle time
(MIN.)
Power consumption
.(MAX.)
Active
MC-422000A32-60
60 ns
120 ns
5355 mW
MC-422000A32-70
70 ns
140 ns
4515 mW
MC-422000A32-80
80 ns
160 ns
4095 mW
MC-422000A32-10
100 ns
190 ns
3675 mW
MC-422000A36-70
70 ns
140 ns
6195 mW
MC-422000A36-80
80 ns
160 ns
5565 mW
MC-422000A36-10
100 ns
190 ns
4935 mW
Standby
84mW
126mW
• 1 024 refresh cycles/16 ms
• Three refresh modes are available: CAS before RAS refresh. RAS only refresh. Hidden refresh
• 72-pin single in-line memory module (Pin pitch = 1.27 mm)
• All inputs and outputs are TTL compatible
• Single +5.0 V ± 5 % power supply
• Access time can be distinguished with characteristics of PD-pins(PDO to PD3)
Tha information in this documant Is subjact to change without notice.
53
NEe
MC-422000A32, 422000A36 SERIES
Ordering Information
Part number
Access time
(MAX.)
MC-422000A32B-60
60 ns
MC-422000A32B-70
70 ns
MC-422000A32 B-80
80 ns
MC-422000A32B-10
100 ns
MC-422000A32F-60
60 ns
MC-422000A32F-70
70 ns
MC-422000A32F-80
80 ns
MC-422000A32F-10
100 ns
Package
Mounted devices
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
16 pieces of pPD424400LA
(300 mil SOJ)
72-pin Single In-line Memory Module
[Double side]
(Socket Type)
Edge connector: Gold plating
72-pin Single In-line Memory Module
MC-422000A368J-70
70 ns
MC-422000A36BJ-80
80 ns
MC-422000A368J-10
100 ns
(Socket Type)
Edge connector: Solder coating (HAL)
16 pieces of pPD424400LA
(300 mil SOJ)
8 pieces of pPD421000LA
(300 mil SOJ)
72-pin Single In-line Memory Module
MC-422000A36FJ-70
70 ns
MC-422000A36FJ-80
80 ns
MC-422000A36FJ-10
100 ns
(Socket Type)
[Double side]
Edge connector: Gold plating
Quality Grade
Standard
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number I EI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
54
NEe
MC-422000A32, 422000A36 SERIES
Pin Configurations (Front view)
[MC-422000A32 series)
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating. Gold plating)
GNO
1100
11016
1101
11017
1102
11018
1103
11019
Vee
o
NC
AO
AI
A2
A3
A4
A5
A6
NC
1104
1/020
1105
11021
1/06
1/022
1/07
1/023
A7
NC
Vee
A8
A9
RAS3
RAS2
NC
NC
NC
NC
GNO
CASO
CAS2
CAS3
CASI
RASO
RASI
s:s:
..
""""
00
~~
~~
AO-A9
: Address Inputs
1/00-1/031
: Data Inputs/Outputs
--CASO-CAS3
----RASO-RAS3
: Column Address Strobe
: Row Address Strobe
00
00
00
WE
: Write Enable
»ww
Vee
: Power Supply
I\)~
"TIOI
GND
: Ground
NC
: No connection
The internal connection
NC
WE
~f
PO pins (PDO to PD3)
depends on access time.
NC
1/08
1/024
1/09
1/025
1/010
1/026
Pin
1/011
1/027
Name No.
1/012
1/028
Access Time
Pin
60 ns 70 ns 80 ns 100 ns
Vee
1/029
1/013
PDO
67
NC
NC
NC
NC
PD1
68
NC
NC
NC
NC
PD2
69
NC
GND
NC
GND
PD3
70
NC
NC
GND
GND
1/030
1/014
1/031
1/015
NC
POO
POI
P02
P03
NC
GNO
o
55
NEe
MC-422000A32, 422000A36 SERIES
[MC-422000A36 series)
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating, Gold plating)
o
GNO
1/00
11018
1/01
1/019
1/02
1/020
1/03
1/021
Vee
NC
AO
Al
A2
A3
A4
A5
A6
NC
1/04
1/022
1/05
11023
1/06
1/024
1/07
a.
a.
a.a.-
I/O~5
A'( 0 -
NC 0
Vee 0
A8
A9
RAS3
RAS2
1/026
1/08
1/017
1/035
GNO
~
~
~
~
AO-A9
: Address Inputs
1/00-1/035
: Data Inputs/Outputs
--CASO-CAS3
-RASO-RAS3
: Row Address Strobe
WE
: Write Enable
Vee
: Power Supply
GND
: Ground
NC
: No connection
: Column Address Strobe
"RAm!
~
The internal connection of PO pins (PDO to PD3)
NC
M
depends on access time,
NC
1109
1/027
1/010
1/028
11011
Pin
Pin
Access Time
Name
No,
70 ns 80 ns 100 ns
11032
11014
POO
67
NC
NC
NC
NC
1/033
1/015
1/034
P01
68
NC
NC
NC
NC
P02
69
NC
GNO
NC
GNO
PD3
70
NC
NC
GNO
GND
1/029
1/012
1/030
1/013
11031
Vee
11016
NC
POO
POl
P02
P03
NC
GNO
56
o
NEe
MC-422000A32, 422000A36 SERIES
Block Diagrams
[MC-422000A32 series]
RASO'o---------,
CASO,o--r=======~==~~---~======~__L-,
1/01
1/02
1/03
1/04
1/01
1/02
1/03
1/04
00
OE
OE
1/01
1/02
1/03
1/04
1/01
1/02
1/03
1/04
01
OE
RASl
Remark 00-015: ,uP0424400
OB
09
OE
CASl
1/01
1/02
1/03
1/04
CAS RAS
02
OE
1/01
1/02
1/03
1/04
CAS RAS
010
OE
1/01
1/02
1/03
1/04
CAS
RAS
03
DE
1/01
1/02
1/03
1/04
CAS RAS
011
OE
RAS2o--------~
CAS2o---r=======~=d~~--~r=====~__~,
CAS RAS
012
CAS3
1/01
1/02
1/03
1/04
CAS RAS
06
OE
CAS RAS
07
014
1/01
1/02
1/03
1/04
CAS RAS
015
OE
DE
WEo
Vcco
GNOo
CAS RAS
OE
1/01
1/02
1/03
1/04
AO-A9 0
1/01
1/02
1/03
1/04
• 00-015
• 00- 015
:!:
. 00-015
:;: CO - C15 • 00- 015
57
NEe
MC-422000A32, 422000A36 SERIES
[MC-422000A36 series]
RASO
CAso
1/000-1/010-1/020-1/030--
1/01
1/02
1/03
1/04
&
OE
1/0401/0501/0601/070-
1/01
1/02
1/03
1/04
&
OE
DO
&
CAS RAS
&
Omn
D
CAS RAS
MO
CAS RAS
1
CAS RAS
09
OE
DIN
Dour
CAS RAS
M4
CAS 1
1/090-I/O 100-·I/O 110--··
I/O 120--
1/01
1/02
1/03
1/04
1/01
1/02
1/03
1/04
CAS RAS
02
DE
&
I/O 130---0
I/O 140---0
I/O 150---0
I/O160-
&
1/01
1/02
1/03
1/04
CAS
RAS
OE
&
&
DIN
1/017
DoUT
RAS2 0 - - CAS2 0 - - - I/O 180-I/O 190+I/O200-I/O 210+-
CAS RAS
Ml
CAS RAS
I/O220--I/O230--I/O240-I/O250--
1/01
1/02
1/03
1/04
CAS RAS
I
1/02
1/03
1/04
CAS RAS
011
OE
1
DIN
Doul
&
OE
1/01
1/02
1/03
1/04
04
..1
&
CAS RAS
M5
&
Dour
CAS RAS
M2
rl
CAS RAS
012
OE
1
1/01
1/02
1/03
1/04
05
DIN
1/026
_rl
010
-
1/01
1/02
1/03
1/04
bE
;r/;.
._--
-_....-
03
CAS RAS
OE
. - 1/01
CAS RAS
013
OE
DIN
OOUT
CAS RAS
M6
CAS3
I/O270-I/O280-II0290-I/O300-
1/01
1/02
1/03
1/04
CAS RAS
06
DE
&
I/O3101/03201/0330-1/0340--
1/01
1/02
1/03
1/04
&
OE
&
CAS RAS
&
Dour
AO-A90~---
WEo
58
VeeoGNOo-
CAS RAS
M3
D
00-015,MO-M7
• 00-015,MO-M7
-:1:.----
00-015,MO-M7
TCO-C2300_015,MO_M7
CAS RAS
014
OE
1
1/01
1/02
1/03
1/04
07
DIN
1/035
1/01
1/02
1/03
1/04
CAS RAS
015
DE
DIN
Doul
Remark 00-015: JlP0424400
MO-M7 : JlP0421 000
08
OE
1/01
1/02
1/03
1/04
01
DIN
1/08
1/01
1/02
1/03
1/04
CAS RAS
CAS RAS
M7
NEe
MC-422000A32, 422000A36 SERIES
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
-1.0to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
Power dissipation
Po
Voltage on any pin relative to GND
Condition
mA
50
MC-422000A32
16
MC-422000A36
24
W
Operating temperature
Topt
o to +70
'C
Storage temperature
TSl g
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Condition
Symbol
MIN.
TYP.
MAX.
4.75
5.0
5.25
Unit
Supply voltage
Vee
High level input voltage
VIH
Vee +1.0
V
Low level input voltage
VIL
-1.0
+0.8
V
Ambient temperature
T.
0
70
'C
MAX.
Unit
Capacitance ITa
- -------- ---
2.4
V
=+25'C, f =1 MHz)
[MC-422000A32 series)
Parameter
Symbol
MIN.
TYp.
Cll
AO-A9
121
CI2
WE
137
CI3
RASO - RAS3
48
CI4
CASO-CAS3
48
1/00-1/031
29
pF
MAX.
Unit
Input capacitance
Data Input/Output capacitance
Test condition
CliO
pF
[MC-422000A36 series)
Parameter
Test condition
Symbol
MIN.
TYp.
Cll
AO-A9
161
CI2
WE
193
CI3
RASO-RAS3
62
CI4
CASO -CAS3
62
Input capacitance
pF
1/00 -1/07,1/09 -1/016,
CIiOl
Data Input/Output capacitance
CII02
1/018 -1/025,1/027 -1/034
1/08,1/017,1/026,1/035
29
pF
39
59
NEe
MC-422000A32, 422000A36 SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[MC-422000A32 series)
Parameter
Symbol
MIN.
Test condition
MAX.
Unit
Notes
rnA
3,4,7
1020
tRAC = 60 ns
RAS, CAS Cycling
Operating current
ICCl
10=OmA
Standby current
-
-
Icc3
Icc.
Input leakage curront
700
10=OmA
32
RAS, CAS iii:; Vcc-0.2 V
10=0 rnA
16 .
Iccs
Ii (LI
tRAC = 60 ns
1020
CAS iii:; VIH (MIN.I
tRAC = 70 ns
860
tRC = tRC(MIN.1
tRAC = 80 ns
780
10=OmA
tRAC = 100 ns
700
tRAC = 60 ns
780
tRAC = 70 ns
700
tRAC = 80 ns
620
tRAC = 100 ns
540
RAS ;:;; VIL IMAX.!, CAS Cycling
tpc = tpC(MIN.1
10=OmA
-
CAS before RAS
refresh current
tRAC = 100 ns
Icc2
Operating current
(Fast page mode)
860
780
RAS, CAS iii:; VIH (MIN.I
RAS Cycling
RAS only refresh current
tRAC = 70 ns
tRAC = 80 ns
tRC = tRC(MIN.1
RAS Cycling
tRC = tRcIMIN.1
10 = 0 rnA
tRAC = 60 ns
1020
tRAC = 70 ns
860
tRAC = 80 ns
780
tRAC = 100 ns
700
rnA
rnA
3,4,5,7
rnA
3,4,6'
rnA
3,4
VI = 0 to 5.5 V
-10
+10
JlA
-10
+10
JlA
all othor pins not under test = 0 V
Output leakage current
10lLI
1/00 to 1/031 is disabled (Hi-Z)
Vo = 0 to 5.5 V
60
High level output voltage
VOH
10=-5.0 rnA
Low level output voltage
VOL
10=+4.2 rnA
V
2.4
0.4
V
NEe
MC-422000A32, 422000A36 SERIES
[MC-422000A36 series]
Parameter
Symbol
Test condition
RAS, CAS Cycling
Operating current
Icc1
MAX.
tRAC = 70 ns
1 180
tRAC = 80 ns
1060
tRAC = 100 ns
940
tRC=tRCIMIN.)
10=OmA
Standby current
MIN.
RAS, CAS ~ VIH IMIN.)
10=OmA
48
RAS, CAS s:; Vcc-0.2 V
10=OmA
24
Icc2
Unit
Notes
rnA
3,4,7
mA
RAS Cycling
--
RAS only refresh current
Icc3
Operating current
(Fast page mode)
Icc4
CAS s:; VIH IMIN.)
tRAC = 70 ns
1180
tRC = tRcIMIN.)
tRAC = 80 ns
1060
10=0 rnA
tRAC = 100 ns
940
RAS :;;; VILIMAX.), CAS Cycling
tpC=tpcIMIN.)
10=OrnA
tRAC = 70 ns
980
~
80 ns
860
100 ns
740
tRAC
tRAC~
_
CAS before RAS
refresh current
Input leakage current
Iccs
I ilL)
RAS Cycling
tRC = tRCIMIN.)
10=OrnA
OM
____
tRAC = 70 ns
•
3,4,5,7
rnA
3,4,6
rnA
3,4
--1180
-.--- ---'
tllAC = 80 ns
1060
tllAC = 100 ns
940
-0._-
mA
VI =Ot05.5V
-10
+10
JlA
-10
+10
/lA
all other pins not under test = 0 V
Output leakage current
lOll)
1/00 to 1/035 is disabled (Hi-Z)
Vo=Oto 5.5 V
High level output voltage
VOH
10 =-5.0 rnA
Low level output voltage
VOL
10=+4.2 rnA
V
2.4
0.4
V
61
NEe
MC-422000A32, 422000A36 SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Svmbol
Parameter
Read or Write Cycle Time
--Fast Page Mode Cycle Time (Read or Write)
----Access Time from RAS
--
tRAC =60 ns
tRAC =70 ns
Noles 8, 9, 18
tRAC =80 ns
tRAC =100 ns
MIN. MAX . MIN. MAX. MIN. MAX. MIN. MAX.
Unit Notes
tRC
120
140
160
190
ns
tpc
40
45
50
60
ns
tRAC
_
IMC-422000A32
Access Time from CAS (Falling Edge) I
tCAe
Access Time from Column Address
tAA
60
70
80
100
ns
10,11
f--
20
20
25
ns
10,11
30
35
40
50
ns
10,11
55
ns
11
15
MC-422000A36
Access Time from CAS Precharge
tACP
RAS to Column Address Delay Time
tRAD
15
CAS to Data Setup Time
tCLZ
0
Output Buffer Turn-off Delay Time (CAS)
tOFF
0
15
0
15
0
20
0
Transition Time (Rise and Fall)
tT
3
50
3
50
3
50
3
RAS Precharge Time
tRP
50
70
80
RAS Pulse Width (Random Read, Write Cycle)
tRAS
60
10000
70
10000
80
10000 100
10 DOC
RAS Pulse Width (Fast Page Mode)
tRASP
60
125000
70
125000
80
125000 100
125000
RAS Hold Time
tRSH
20
CAS Pulse Width
tCAS
20
CAS Hold Time
tCSH
60
RAS to
-- - --
CAS Doloy Time
IMC-422000A32
IMC-422000A36
tRCD
40
35
20
15
30
35
0
20
20
20
20
25
ns
10
ns
11
25
ns
12
50
ns
50
0
ns
25
10 DOC
25
ns
ns
ns
100
60
ns
ns
25
10000
80
50
17
-
90
ns
10
13
75
CAS to RAS Precharge Time
tCRP
10
10
10
10
ns
CAS Precharge Time
tCPN
10
10
10
10
ns
tcp
10
10
10
10
ns
tRPC
10
10
10
10
ns
tRHCP
35
40
45
55
ns
ns
---
CAS Precharge Time (Fast Page Mode)
- -
RAS Precharge CAS Hold Time
-
RAS Hold Time from CAS Precharge
-
-_ ..
Row Address Setup Time
tASR
0
0
0
0
Row Address Hold Time
tRAH
10
10
12
12
ns
Column Address Setup Time
tASC
0
0
0
0
ns
tCAH
15
20
ns
Column Address Hold Time
IMC-422000A32
JMC-422000A36
-
15
15
f--
17
20
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
50
ns
Read Command Setup Time
tRCS
0
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
10
10
10
10
ns
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
0
ns
14
Write Command Hold Time Referenced to CAS
tWCH
15
15
15
20
ns
15
Data-in Setup Time
tDS
0
0
0
0
ns
16
20
ns
16
17
Data-in Hold Time
IMC-422000A32
J
tDH
15
15
f---
15
MC-422000A36
62
40
20
10000
70
40
17
0
60
10000
45
20
Write Command Setup Time
twcs
0
0
0
0
ns
CAS Setup Time for CAS before RAS Refresh
tCSR
10
10
10
10
ns
CAS Hold Time for CAS before RAS Refresh
tCHR
15
15
15
20
ns
WE Setup Time
tWSR
10
10
10
10
ns
WE Hold Time
tWHR
15
15
15
Refresh Timo
tREF
16
16
20
16
ns
16
ms
14
NEe
MC-422000A32, 422000A36 SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 J1S and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. Iccl, IcC3, IcC4 and Iccs depend on cycle rates ( tAC and tpc ).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. IcC4 is measured assuming that all column address inputs are switched only once during each fast
page cycle.
7. ICCI and IcC3 are measured assuming that address can be changed once or less during RAS ;;i VIL
(MAX.) and CAS ~ VIH (MIN.).
B. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
VIH(MIN.)=2.4V---------~----'
:
VIL (MAX.)
,,
,,
:
:
I
t
I
r
I
I
,
I
= 0.8 V ~ ____________ '
I
III: :_
III: ,"
h=5ns'
h= 5 ns
(2) Output timing specification
VOH (MIN.) =2.4V
------~
VOL (MAX.) = 0.4 V
------~'-_ _ _ _---'_
}-
10. For read cycles, access time is defined as follows:
Input Conditions
Access Time
t AAO ;;i t AAO (MAX.) . tACO ;;i tACO (MAX.)
tAAO
tACO
> tAAO(MAX.). tAco;;i tACO (MAX.)
> tACO (MAX.)
Access TIme from RAS
tAAC(MAX.)
tAAC(MAX.)
tAA(MAX.)
tAAO + tAA(MAX.)
tCAC (MAX.)
tACO + t CAC (MAX.)
tAAO (MAX.) and tACO(MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tAAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tAAO ~ tAAO(MAX.) and
tACO ~ tACO (MAX.) will not cause any operation problems.
11. Loading conditions are
2 TILs and 100 pF.
12. tOFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not referenced
to VOH or VOL.
-- --
13. tCAP (MIN.) requirement should be applied for RAS / CAS cycles preceded by any cycles.
14. Either tACH (MIN.) or tAAH (MIN.) should be met in read cycles.
15. In early write cycles, twCH (MIN.) should be met.
16.
tos (MIN.) and tOH (MIIII.) are referenced to the CAS falling edge in early write cycles.
17. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
18. The column "trac
= 60 ns" is not applicable to MC-422000A36.
63
Timing Chart
Please refer to Timing Chart 2, page 375.
64
NEe
MC-422000A32, 422000A36 SERIES
Package Drawings
MC-422000A32B, 422000A32F
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
N
s
DODD.
detail of @ Part
-*x
[E]
M72B-50A22-1
ITEM
MILLIMETERS
INCHES
A
107.95±0.13
4.250±0.006
3.984
-_.
--
B
101.19
C
44.45
1.750
D
6.35
0.250
E
44.45
1.750
G
10.16
0.400
H
1.27 (T.P.)
0.050 (T.P.I
I
6.35
0.250
J
2.03
0.080
K
6.35
0.250
M
25.4
1.000
N
9.0 MAX.
0.355 MAX.
P
R 2.0
R 0.079
S
113.18
910.125
T
1.27~8~B
0.050±0.004
U
6.5 MIN.
0.255 MIN.
V
0.25 MAX.
0.010 MAX.
W
1.04±0.05
0.041 ±0.002
X
2.54 MIN.
0.100 MIN.
y
3.75 MIN.
0.147 MIN.
65
NEe
MC-422000A32, 422000A36 SERIES
(Not Applicable)
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
°000000000000°
M72B-50A20-1
detail of
® Pm!
ITEM
MILLIMETERS
INCHES
A
107 .95±0. 13
4.250±0.006
B
101.19
3.984
C
44.45
1.750
D
6.35
0.250
E
44.45
1.750
G
10.16
0.400
H
1.27 (T.P.)
0.050 (T.P.)
I
6.35
0.250
J
2.03
0.080
6.35
0.250
-
.
K
--.
66
~-.
M
25.4
1.000
N
9.0 MAX.
0.354 MAX.
P
R 2.0
R 0.079
S
113.18
110.125
0.050±0.004
T
1.27!8ba
U
5.32 MIN.
0.209 MIN.
.V
0.25 MAX.
0.010 MAX.
W
1.04±0.05
0.041 ±0.002
X
2.54 MIN.
0.100 MIN.
y
3.75 MIN.
0.147 MIN.
NEe
MC-422000A32, 422000A36 SERIES
MC-422000A36BJ, 422000A36FJ
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
B
I
~
t9~ ~
'\
I
0000000000
CJ c::J c:J c:J
..
-.-U
J-
1111 1111 II III!'
~
+-[8]
c
D
E
M72B-50A44
----
ITEM
detail of
® part
-
MILLIMETERS
INCHES
A
107_95±0.13
4_250±0.006
B
101.19
3.984
C
44.45
1.750
D
6.35
0.250
E
44.45
1.750
G
10.16
0.400
H
1.27 (T.P.)
0.050 (T.P.)
I
6.35
0.250
J
2.03
K
- ....
M
f------
-6.35
--- .. _--- ".__.31.75
_._----- -----
0.080
0.250
1.250
N
9.0 MAX.
0.355 MAX.
P
Rl.57
RO.062
S
4>3.18
4>0.125
T
1.27~8J8
0.050±0.004
U
3.17 MIN.
0.124 MIN.
V
0.25 MAX.
0.010 MAX.
W
1.04±0.05
0.041 ±0.002
X
3.15 MIN.
0.124 MIN.
67
DATA SHEET
~EC
MOS INTEGRATED CIRCUIT
MC-424000A32, 424000A36 SERIES
4 M-WORD BY 32-BIT, 4 M-WORD BY 36-BIT DYNAMIC RAM MODULE
FAST PAGE MODE
Description
The MC-424000A32 series is a 4.194.304 words by 32 bits dynamic RAM module on which 8 pieces of
16 M DRAM: ttPD4217400 are assembled.
The MC-424000A36 series is a 4.194.304 words by 36 bits dynamic RAM module on which 8 pieces of
16 M DRAM: ttPD4217400 and 4 pieces of 4 M DRAM: ttPD424100 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 4.194.304 words by 32 bits organization (MC-424000A32 series)
• 4.194.304 words by 36 bits organization (MC-424000A36 series)
• Fast access and cycle time
Power consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
MC-424000A32-60
60 ns
110 ns
4.840 mW
MC-424000A32-70
70 ns
130 ns
4.400mW
MC-424000A32-80
80 ns
150 ns
3.960 mW
Family
(MIN.)
Active
•
•
•
•
•
•
MC-424000A36-60
60 ns
110 ns
7.480 mW
MC-424000A36-70
70 ns
130 ns
6.600 mW
MC-424000A36-80
80 ns
150 ns
5.940 mW
Standby
44mW
(CMOS level input)
66mW
ICMOS level input)
2.048 refresh cycles/32 ms
2.048 refresh cycles/16 ms (MC-424000A36 burst refesh)
CAS before RAS refresh. RAS only refresh. Hidden refresh
72-pin single in-line memory module (Pin pitch", 1.27 mm)
Single +5.0 V ±0.5 V power supply
Access time can be distinguished with characteristics of PO-pins (PDO to PD3)
The Information In this document Is subject to change without notice.
459 (Japan)
69
NEe
MC-424000A32, 424000A36 SERIES
Ordering Information
[MC-424000A32 series]
Part number
Access time
(MAX.)
MC·424000A32B-60
60 ns
MC-424000A32B-70
70 ns
Package
72-pin Single In-line Memory Module
(Socket Type)
Mounted devices
8 pieces of JLPD4217400LA
(300 mil SOJ)
Edge connector: Solder coating (HAL)
MC-424000A32B-80
80 ns
MC-424000A32F-60
60 ns
MC-424000A32F-70
70 ns
MC-424000A32F-80
80 ns
[Single side]
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Gold plating
[MC-424000A36 series]
Part number
Access time
(MAX.)
MC·424000A36BE-60
60 ns
MC-424000A36BE-70
70 ns
MC-424000A36BE-80
80 ns
MC-424000A36FE-60
60 ns
MC-424000A36FE-70
70 ns
MC-424000A36FE-80
80 ns
MC-424000A36BJ-60
60 ns
MC-424000A36BJ-70
70 ns
MC-424000A36BJ-80
80 ns
MC-424000A36FJ-60
60 ns
MC-424000A36FJ-70
70 ns
MC-424000A36FJ-80
80 ns
Package
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
Mounted devices
8 pieces of JLPD4217400LA
(300 mil SOJ)
4 pieces of JLPD424100LA
(300 mil SOJ)
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Gold plating
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
[Double side]
8 pieces of JLPD4217400LA
(300 mil SOJ)
4 pieces of JLPD424100LA
(300 mil SOJ)
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Gold plating
[Single side]
Quality Grade
Standard
Please refer to "Quality grade on NEC Semiconductor Devices· (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
70
NEe
MC-424000A32, 424000A36 SERIES
Pin Configuration
[MC-424000A32 series!
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating, Gold plating)
GND
1/00
1/016
1/01
1/017
1/02
1/018
1/03
1/019
Vee
NC
AO
Al
A2
A3
A4
A5
A6
Al0
1/04
1/020
1/05
1/021
1/06
1/022
1/07
1/023
A7
NC
Vee
A8
A9
RA~~
NC
NC
NC
NC
.YNQ
CASO
CAS2
CAS3
CASl
RASO
NC
NC
WE
NC
1/08
1/024
1/09
1/025
1/010
1/026
1/011
1/027
1/012
1/028
Vee
1/029
1/013
1/030
1/014
1/031
1/015
NC
PDO
PDl
PD2
PD3
NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
o
37
38
39
40
41
42
43
Address Inputs
Data Inputs/Outputs
AD - Al0
1/00 - 1/031
CASO - CAS3
RASO, RAS2
44
45
46
47
48
49
50
51
52
53
Column Address Strobe
Row Address Strobe
Write Enable
WE
Vee
Power Supply
Ground
No connection
GNO
NC
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
The internal connection of PO pins (POD to P03)
depends on access time.
o
Access Time
Pin
Name
Pin
No.
60 ns
70 ns
80 ns
PDO
67
GND
GND
GND
POl
68
NC
NC
NC
PD2
69
NC
GND
NC
PD3
70
NC
NC
GND
71
NEe
MC-424000A32, 424000A36 SERIES
[MC-424000A36 series]
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating. Gold plating)
GND
1/00
1/018
1/01
1/019
1/02
1/020
1/03
1/021
Vee
NC
AO
Al
A2
A3
A4
A5
A6
Al0
1/04
1/022
1/05
1/023
1/06
1/024
1/07
1/025
A7
NC
Vee
A8
A9
NC
RAS2
1/026
1/08
1/017
1/035
l3NQ
~S.Q
CAS2
~s:J
C8S.1
RASO
NC
.ill;
WE
NC
1/09
1/027
1/010
1/028
1/011
1/029
1/012
1/030
1/013
1/031
Vee
1/032
1/014
1/033
1/015
1/034
1/016
NC
PDO
PDl
PD2
PD3
NC
GND
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
o
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AO - Al0
Address Inputs
1/00 - 1/035
CASO - CAS3
RASO. RAS2
WE
Vee
GND
Data Inputs/Outputs
Column Address Strobe
Row Address Strobe
Write Enable
Power Supply·
Ground
No connection
NC
The internal connection of PO pins (PDO to PD3)
depends on access time.
o
Access lime
Pin
Name
Pin
No.
60 ns
70 ns
80 ns
PDO
67
GND
GND
GND
PDl
68
NC
NC
NC
PD2
69
NC
GND
NC
PD3
70
NC
NC
GND
NEe
MC-424000A32, 424000A36 SERIES
Block Diagram
(MC-424000A32 series]
RASO
CASO
I{OO
1101
1{02
1103
1/01
1{02
1{03
1{04
~
•
CAS
BE
Jr
1{01
1{02
1{03
1{04
1{04
1/05 ;...
1{06
1/07
Remark DO - 07 : IlP042l7400
• •
CAS
RAS
01
BE
Jr
CAS 1
~
1/01
1102
1{03
1108
1{09
1{010
11011
CAS
1101
1/02
1103
1104
• •
CAS
RAS2
CAS2
1/01
1102
1103
1{016
1/017
11018
11019
~4
Jr
1101
1{02
1{03
1{04
•
CAS RAS
04
RAS
05
CAS3
1{01
1102
1103
1{024
1{025
1/026 ':::
1{027
~4
Jr
1{01
1{02
1{03
1/04
OF
~
Jr
GNOO
, ,
CAS
BE
Jr
AO-A10 0
WEO
Vee 0
RAS
03
BE
Jr
1{020
1{021
1/022
1{023
RAS
02
~4
Jr
1{012
1{013
1{014
1{015
1/028
1/029
1/030
1/031
RAS
00
..
00-07
00-07
~
+
CAS RAS
06
•
+
CAS RAS
07
.
'X. CO-C?
00-07
00-07
73
NEe
MC-424000A32, 424000A36 SERIES
[MC-424000A36 series)
, !
RASO
CASO
1/00
1/01
1/02
1/03
1/01
1/02
1/03
O.
~4
1/01
1/02
1/03
1/04
1/04 ;...
1/05
1/06
1/07
1/08
CASl
1/09
1/010
1/011
1/012
~
CAS
1/01
1/02
1/03
a.
a.
~4
1/01
1/02
1/03
1/04
1/013
1/014
1/015
1/016
• •
• •
CAS
RAS
MO
+
+
CAS
RAS
02
, ,
CAS
RAS
03
~
1/017
RAS
01
Oi=
r-i
Dlrr
Dow
-
,
CAS RAs
Ml
RAS2o---------------------~
CAS2o------------------.
1/018
1/019
1/020 O·
1/021 o·
CAS
RAS
04
1/022
1/023
1/024
1/025
1/026
CAS3
1/027
1/028
1/029
1/030
06
1/031
1/032
1/033
1/034
CAS
AO-Al0 0
WE 0
Vee 0
GNDO
74
RAS
07
CAS
M3
1/035
.•
Remark DO - D7 : JlPD4217400
MO-M3: JlPD424100
CAS
BE
r--I Dour
DIN
RAS
DO
RAS
DO-D7. MO-M3
DO-D7. MO-M3
:::t:
• DO-D7. MO-M3
CO- Cll
T
• DO - D7. MO - M3
NEe
MC-424000A32, 424000A36 SERIES
Electrical Specifications Notes 1. 2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output cu rrent
10
50
mA
Power dissipation
Po
MC-424000A32
8
MC-424000A36
12
W
Operating temperature
Top,
o to +70
·C
Storage temperature
Tstg
-55 to +125
·C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described inthe operational section ofthis specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
4.5
5.0
5.5
V
2.4
Vee + 1.0
V
-1.0
+0.8
V
70
·C
MAX.
Unit
Supply voltage
Vee
High level input voltage
V,H
Low level input voltage
V,L
Ambient temperature
T.
0
Capacitance IT.
= +25 ·C. f = ,
-
MHz)
[MC-424000A32 seriesl
Parameter
Input capacitance
Data Input/Output capacitance
Symbol
Test Condition
MIN.
TYP.
CII
AD - Al0
68
C"
WE
76
Cil
RASO, RAS2
43
C"
CASO - CAS3
29
CliO
1/00 -1/031
17
pF
MAX.
Unit
pF
[MC-424000A36 seriesl
Parameter
Input capacitance
Data Input/Output capacitance
Symbol
Test Condition
MIN.
TYP.
CII
AD - Al0
88
C'2
WE
104
C'3
RASO. RAS2
57
C"
CASO - CAS3
36
CliO!
1/00 - 1/07. 1/09 - 1/016.
1/018 -1/025. 1/027 - 1/034
17
CIID2
1/08. 1/017. 1/026, 1/035
22
pF
pF
75
NEe
MC-424000A32, 424000A36 SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[MC-424000A32 seriesl
Parameter
Operating current
Symbol
Iccl
Test condition
RAS only refresh current
Icc2
Icc3
RAS, CAS Cycling
hAC = 60 ns
880
tRAC = 70 ns
800
tRAC = 80 ns
720
lo=OmA
16
RAS, CAS ~ Vcc - 0.2 V
10= 0 rnA
8
RAS Cycling
CAS ~ V,H IMIN.I
tRAC = 60 ns
880
tRAC = 70 ns
800
RAS, CAS
tnc
Icc.
(Fast page model
~
V,H IMIN.!
c: tAC (MIN.I
tRAC = 80 ns
720
RAS $ V,L IMAX.I, CAS Cycling
tRAC = 60 ns
560
tpc = tpc IMIN.!
tRAC = 70 ns
480
tRAC = 80 ns
400
RAS Cycling
t.AC = 60 ns
880
tRC = tRC 1M IN.!
t.AC = 70 ns
800
t ....C = 80 ns
720
10
Operating current
= 0 rnA
10 = 0 rnA
CAS before RAS
IcC5
refresh current
MAX.
tRC = tRC IMIN.!
10 = 0 rnA
Standby current
MIN.
Unit
Notes
rnA
3,4,7
rnA
rnA
3,4,5,7
rnA
3,4,6
rnA
3,4
lo-OmA
Input leakage current
IIILI
V, = 0 to 5.5 V
All other pins not undor test = 0 V
Output leakage current
lOll!
Vo = 0 to 5.5 V
Output is disabled (Hi-Z)
76
High level output voltage
VOH
10 = -5.0 rnA
Low level output voltage
VOL
10 = +4.2 rnA
-10
+10
pA
-10
+10
pA
2.4'
V
0.4
V
NEe
MC-424000A32, 424000A36 SERIES
[MC-424000A36 series)
Parameter
Operating current
Standby current
RAS only refresh current
Operating current
Symbol
Icc1
Icc2
Icc3
Icce
(Fast page mode)
Test condition
RAS, CAS Cycling
tRC = tRC 1M IN.!
10= 0 mA
MIN.
tRAC = 60 ns
Iccs
refresh current
Input leakage current
lill!
hAC = 70 ns
1,200
tRAC = 80 ns
1,080
RAS, CAS
~
V,H IMIN.!
10 = 0 mA
24
RAS, CAS
~
Vcc - 0.2 V
10 = 0 mA
12
RAS Cycling
CAS ~ V,H IMIN.!
tRC = hc IMIN.!
10= 0 mA
tRAC = 60 ns
RAS S VllIMAX.!, CAS Cycling
tpc = tpc IMIN.I
tRAC = 60 ns
920
tRAC = 70 ns
800
tRAC = 70 ns
1,200
1,080
tRAC = 80 ns
680
RAS Cycling
tRAC = 60 ns
1,360
tRC = tRC IMIN.!
10 = 0 mA
tRAC = 70 ns
1,200
tRAC = 80 ns
1,080
All other pins not under test = 0 V
Notes
mA
3,4,7
mA
1,360
tRAC = 80 ns
V, = 0 to 5.5 V
Unit
1,360
10 = 0 mA
CAS before RAS
MAX.
mA
3,4,5,7
mA
3,4,6
mA
3, 4
-10
+10
pA
+10
pA
Output leakage current
10 III
Vo = 0 to 5.5 V
Output is disabled (Hi-Z)
-10
High level output voltage
VOH
10 = -5.0 mA
2.4
low level output voltage
VOL
10 = +4.2 mA
V
0.4
V
77
NEe
MC-424000A32, 424000A36 SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Notes 8, 9
[MC-424000A32 series]
Parameter
Symbol
tRAC = 60 ns
MIN.
78
MAX.
tRAC = 70 ns
MIN.
MAX.
tRAC = 80 ns
MIN.
Read/Write Cycle Time
tRC
110
130
150
Fast Page Mode Cycle Time
tpc
40
45
50
Access Time from RAS
tRAC
60
Unit
Notes
MAX.
ns
ns
70
80
ns
10, 11
Access Time from CAS
tCAC
15
18
20
ns
10,11
Access Time Column Address
tAA
30
35
40
ns
10, 11
Access Time from CAS Precharge
tACP
35
40
45
ns
11
RAS to Column Address Delay Time
tRAD
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
ns
11
12
30
15
35
0
17
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
15
0
15
0
20
ns
Transition Time (Rise and Fall)
tT
3
50
3
50
3
50
ns
RAS Precharge Time
tR'
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tnA5P
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
trlStl
15
CAS Pulse Width
tCAr.
15
CAS Hold Time
tCSII
60
RAS to CAS Dolay Time
tRCD
20
CAS to RAS Procharge Time
tCRP
5
5
CAS Prechorgo Time
tCPN
10
CAS Prechorgo Time (Fast Page Mode)
tcp
RAS Prechargo CAS Hold Time
tRPC
RAS Hold Timo from CAS Precharge
Row Address Setup Time
50
60
18
10,000
18
ns
20
10,000
70
20
ns
10,000
80
ns
ns
10
5
ns
13
10
10
ns
10
10
10
ns
5
5
5
ns
tRHCP
35
40
45
ns
tASR
0
0
0
ns
40
20
50
25
ns
60
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
IAsc
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAl
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
tWCH
10
10
15
ns
15
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tDH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tCSR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
ns
WE Setup Time
twSR
10
10
10
ns
WE Hold Time
twHR
15
15
15
Refresh Time
tREF
32
32
ns
32
ms
NEe
MC-424000A32, 424000A36 SERIES
[MC-424000A36 series]
Parameter
Symbol
tRAC" 60 ns
MIN.
MAX.
tRAC
=70 ns
tRAC
=80 ns
MIN.
MAX.
MIN.
MAX.
Unit
Notes
Read/Write Cycle Time
tRC
110
130
Fast Page Mode Cycle Time
tpc
40
45
Access Time from RAS
tRAC
60
70
80
ns
10, 11
Access Time from CAS
tCAC
15
20
20
ns
10, 11
150
ns
50
ns
Access Time Column Address
tAA
30
35
40
ns
10, 11
Access Time from CAS Precharge
tACP
35
40
45
ns
11
RAS to Column Address Delay Time
tRAO
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
15
Transition Time (Rise and Fall)
tT
3
50
RAS Precharge Time
tRP
40
RAS Pulse Width
hAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
70
125,000
80
125,000
ns
10,000
20
10,000
20
RAS Hold Time
tRSH
20
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tRCO
20
CAS to RAS Precharge Time
tCRP
10
30
15
35
0
0
0
15
3
50
50
0
20
3
50
60
70
11
ns
12
ns
--
ns
10,000
ns
ns
80
ns
10
10
10
ns
13
20
50
25
ns
ns
20
20
40
17
60
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
ns
RAS Precharge CAS Hold Time
tRPC
10
10
10
RAS Hold Time from CAS Precharge
tRHCP
35
40
45
ns
Row Address Setup Time
tASR
0
0
0
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
ns
Column Address Hold Time
tCAH
15
15
15
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referencod to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twCH
15
15
15
ns
15
Data-in Setup Time
tos
0
0
0
ns
16
Data-in Hold Time
tOH
15
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tCSR
10
10
10
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
ns
WE Setup Time
twSR
10
10
10
ns
WE Hold Time
twHR
15
15
15
Refresh Time
I Distributed refresh
I Burst refresh
tREF
ns
32
32
32
ms
16
16
16
ms
79
NEe
MC-424000A32, 424000A36 SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100
}IS
and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. IcCl, IcC3, IcC4 and Iccs depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. IcC3 is measured assuming that all column address inputs are held at either high or low.
6. IcC4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. IcCl and IcC3 are measured assuming that address can be changed once or less during RAS S VIL
(MAX.) and CAS;:: VIH (MIN.).
S. AC measurements assume IT
= 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H IMIN.I
=2.4 V
VIlIMAXI
= O.8V
tT=5ns
tr= 5ns
(2) Output timing specification
VOH IMIN.I
= 2.4 V
-------~------
VOL IMAXI
=0.4 V
--------------
} -
'-------"
10. For read cycles, access time is defined as follows:
Input Conditions
tRAO
S
tRAO
> tRAO IMAx')
tRCO
> tRCO IMAX.)
tltAO IMAX.) and tRCO
and tRCD
Access Time
Access Time from RAS
S
tRCO IMAX.)
tRACIMAX.)
tRACIMAX.1
S
tRCO IMAX.)
tAAIMAX.)
tRAD
+ tAA IMAX.)
tCACIMAX.)
tRCO
+ tCAC IMAX.)
tRAO (MAX.) and tRCO (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, 1M or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAO;:: tRAO(MAX.)
and tRCO ;:: tRCO (MAX.) will not cause any operation problems.
11. Loading conditions are 2 TILs and 100 pF.
12. tOFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13.
14.
15.
16.
tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
In early write cycles, twCH (MIN.) should be met.
tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles.
17. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
80
Timing Chart
Please refer to Timing Chart 2, page 375.
81
NEe
MC-424000A32, 424000A36 SERIES
Package Drawings
[MC-424000A32B, 424000A32F]
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
B
R~-4--------------------------------------------~
('),------t--{'kJ-S
00000000'
c
o
E
o
o
detail of ® part
W
*x
ITEM
A
MILLIMETERS
107.95:1:0.13
INCHES
4.250:1:0.006
B
101.19:1:0.13
3.984~:80og
C
0
E
K
M
N
P
44.45
6.85
44.45
10.16
1.27 (T.P.)
6.35
2.03
6.35
25.4
5.08 MAX.
R1.57
1.750
0.250
1.750
0.400
0.050 (T.P.)
0.250
O.OBO
0.250
1.000
0.200 MAX.
RO.082
R
3.38:1:0.13
0.133~:~
s
;3.18
;0.125
T
1.27~:6a
0.050:1:0.004
u
5.5 MIN.
0.25 MAX.
1.04:1:0.05
2.54 MIN.
0.216 MIN.
0.010 MAX.
0.041:1:0.002
0.100 MIN.
M72B-5OA54
G
H
[[]>
V
W
X
82
NEe
MC-424000A32, 424000A36 SERIES
[MC-424000A36BE, 424000A36FE]
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
N
000000
s
c
0
D
E
000000
detail of
® part
+
.x
[8]>
ITEM
A
B
C
D
E
G
H
I
0
MILLIMETERS
107.95±0.13
101.19
44.45
6.35
44.45
10.16
1.27 (T.P.)
6.35
2.03
6.35
25.4
9.0 MAX.
R1.57
';3.18
4.250±0.006
3.984
1.750
0.250
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.000
0.355 MAX.
RO.062
';0.125
T
1.27~8:&8
0.050±0.004
u
5.08 MIN.
0.25 MAX.
1.04±0.05
3.15 MIN.
0.200 MIN.
0.010 MAX.
0.041±0.002
0.124 MIN.
M72B-50A47
J
K
M
N
P
S
V
W
X
INCHES
83
NEe
MC-424000A32, 424000A36 SERIES
IMC-424000A36BJ, 424000A36FJ]
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
I'
S
\
B
0000000000
c:::::] c::::::]
~1 ~T .."""""""""""""""",
p /
\
'1"
c
·1 " , "" " , " " " " " " " " " " " ,.
D
E
o
o
detail of ® part
:ir-
-3I
x
0>
ITEM MILLIMETERS
A
107.95tO.13
e
101.19
44.45
C
0
6.35
E
44.45
G
10.16
H
·1.27 (T.P.)
I
6.35
J
2.03
K
6.35
M
31.75
N
5.08 MAX.
P
Rl.57
S
913.18
INCHES
4.250tO.006
3.984
1.750
0.250
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.250
0.200 MAX.
RO.062
910.125
T
1.27~g:68
0.050tO.004
u
3.17 MIN.
0.25 MAX.
1.04tO.05
3.15 MIN.
0.124 MIN.
0.010 MAX.
0.041 to.002
0.124 MIN.
M72B-50A51-1
V
W
X
84
(+
®/
[[]
J
.1
DATA SHEET
NEe
~-3455
MOS INTEGRATED CIRCUIT
MC-428000A32, 428000A36 SERIES
8 M-WORD BY 32-BIT, 8 M-WORD BY 36-BIT DYNAMIC RAM MODULE
FAST PAGE MODE
Description
The MC-428000A32 series is a 8,388,608 words by 32 bits dynamic RAM module on which 16 pieces of
16 M DRAM: .uPD4217400 are assembled.
The MC-428000A36 series is a 8,388,608 words by 36 bits dynamic RAM module on which 16 pieces of
16 M DRAM: .uPD4217400 and 8 pieces of 4 M DRAM: .uPD424100 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 8,388,608 words by 32 bits organization (MC-428000A32 series)
• 8,388,608 words by 36 bits organization (MC-428000A36 series)
• Fast access and cycle time
Power consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-428000A32-60
60 ns
110 ns
5,170 mW
MC-428000A32-70
70 ns
130 ns
4,730 mW
MC-428000A32-80
80 ns
150 ns
4,290 mW
MC-428000A36-60
60 ns
110 ns
7,810 mW
MC-428000A36-70
70 ns
130 ns
6,930 mW
MC-428000A36-80
80 ns
150 ns
6,270 mW
Family
Active
Standby
88mW
(CMOS level input)
132mW
(CMOS level input)
• 2,048 refresh cycles/32 ms
• 2,048 refresh cycles/16 ms (MC-428000A36 burst refesh)
• CAS before RAS refresh, RAS only refresh, Hidden refresh
• 72-pin single in-line memory module (Pin pitch = 1.27 mm)
• Single +5.0 V ±0.5 V power supply
• Access time can be distinguished with characteristics of PD-pins (PDO to PD3)
The Information in this document is subject to change without notice.
(Japan)
85
NEe
MC·428000A32, 428000A36 SERIES
Ordering Information
[MC-428000A32 series]
Part number
Access time
(MAX.)
MC-42BOOOA32B-60
60 ns
MC-42BOOOA32B-70
70 ns
MC-42BOOOA32B-BO
BO ns
MC-42BOOOA32F-60
60 ns
MC-42BOOOA32F-70
70 ns
MC-42BOOOA32F-BO
BO ns
Package
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
Mounted devices
16 pieces of JlPD4217400LA
(300 mil SOJ)
[Double side)
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Gold plating
[MC-428000A36 series]
Pmt number
Access time
(MAX.)
MC·42BOOOA36BJ-60
60 ns
MC·42BOOOA36BJ-70
70 ns
MC-42BOOOA36BJ-BO
BO ns
MC-42BOOOA36FJ·60
60 ns
MC-42BOOOA36FJ·70
70 ns
MC-42BOOOA36FJ·BO
BO ns
Package
72-pin Single In-line Memory Module
(Socket Type)
Edge connector: Solder coating (HAL)
Mounted devices
16 pieces of JlPD4217400LA
(300 mil SOJ)
B pieces of JlPD4241 OOLA
(300 mil SOJ)
72-pin Single In-line Memory Module
(Socket Typo)
Edge connector: Gold plating
(Double side)
Quality Grade
Standard
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
86
NEe
MC-428000A32, 428000A36 SERIES
Pin Configurations
(MC-428000A32 series]
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating. Gold plating)
GND
1/00
1/016
1/01
1/017
1/02
1/018
1/03
1/019
Vee
NC
AO
Al
A2
A3
A4
A5
A6
Ala
1/04
1/020
1/05
1/021
1/06
1/022
1/07
1/023
A7
NC
Vee
A8
~
RAS3
RAS2
NC
NC
NC
NC
GND
CASO
CAS2
CAS3
CASl
RASa
RASl
~~
NC
1/08
1/024
1/09
1/025
1/010
1/026
1/011
1/027
1/012
1/028
Vee
1/029
1/013
1/030
1/014
1/031
1/015
NC
PDO
PDl
PD2
PD3
NC
GND
1
2
3
o
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AO - A10
Addross Inputs
1/00 - 1/031
CASO - CAS3
Data Inputs/Outputs
Column Address Strobe
~ddress
RASO - RAS3
Row
WE
Write Enable
Strobe
Vee
Power Supply
GND
NC
Ground
No connection
The internal connection of PO pins (PDO to PD3)
depends on access time.
o
Access Time
Pin
Name
Pin
No.
PDO
67
NC
NC
NC
PD1
GND
GND
GND
PD2
68
69
NC
GND
NC
PD3
70
NC
NC
GND
60 ns
70 ns
80 ns
87
NEe
MC-428000A32, 428000A36 SERIES
[MC-428000A36 series]
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating. Gold plating)
GND
1/00
1/018
1/01
1/019
1/02
1/020
1/03
1/021
Vee
NC
AO
A1
A2
A3
A4
A5
A6
1'110
1/04
1/022
1/05
1/023
1/06
1/024
1/07
1/025
fI7
NC
Vee
1\8
1\9
HI\S3
HI\S2
1/026
1/08
1/017
1/035
GND
CASO
CAS2
CAS3
CASl
RASO
RASl
.N.C
WE
NC
1/09
1/027
1/010
1/028
1/011
1/029
1/012
1/030
1/013
1/031
Vee
1/032
1/014
1/033
1/015
1/034
1/016
IIlC
PDO
PDl
PD2
PD3
NC
GND
88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
o
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AO - A10
Address Inputs
1/00 -1/035
CASO - CAS3
Column Address Strobe
Data Inputs/Outputs
RASO - RAS3
Row Address Strobe
WE
Write Enable
Power Supply.
Vee
GND
NC
Ground
No connection
The internal connection of PO pins (PDO to PD3)
depends on access time.
o
Access Time
Pin
Name
Pin
No.
PDO
67
NC
NC
NC
PD1
68
GND
GND
GND
60 ns
70 ns
80 ns
PD2
69
NC
GND
NC
PD3
70
NC
NC
GND
NEe
MC-428000A32, 428000A36 SERIES
Block Diagrams
[MC-428000A32 series]
RASO 0 - - - - - - - - - ,
CASOo-----~-+-------.
CAS RAS
1/00
1/01
1/02
1/03
00
1/04
1/05
1/06
1/07
01
CAS RAS
Remark 00 - 015: PP04217400
1-----1
CAS RAS
1---]
09
CASlo-----~-+_------~
1/08
1/09
1/010
1/011
010
1/012
1/013
1/014
1/015
011
CAS RAS
CAS RAS
RAS2o---------,
,----0
RAS3
CAS2o-----~-+_------,
1/016
1/017
1/018
1/019
04
1/020
1/021
1/022
1/023
05
CAS RAS
CAS RAS
CAS RAS
1---]
012
CAS RAS
1---]
013
CAS3O-----~-+_------~
1{01
1/024
1/025
1/026
1/027
1/02
1{03
1{04
CAS RAS
014
OE
1{01
1/028
1/029
1/030
1/031
1/02
1{03
1{04
CAS RAS
015
OE
AO-Al0 0>----" 00-015
WE 0
" 00-015
Vee 0:1:
" 00-015
GNO 0
T
CO-C15
"
00-015
89
NEe
MC-428000A32, 428000A36 SERIES
[MC-428000A36 series]
RASO 0 - - - - - - - - - ,
CASOo-----~-7-------.
CAS RAS
00
CAS RAS
08
1----1
Remark DO - 015: JIf'04217400
MO - M7: JIf'0424100
010
CAS RAS
011
RAS3
1/01
1----11/02
t - - - - t 1/03
t - - - - t 1/04
012
OE
CAS RAS
CAS RAS
05
013
015
CAS RAS
1/035
M3
AD - A10 O>------"'·~ DO - 015. MO - M7
WE 0
• DO - 015. MO - M7
Vee 0
~
• DO - 015. MO - M7
CO-C23
GNOO
T
'00-015.MO-M7
90
DIN
Dour
CAS RAS
M7
NEe
MC-428000A32, 428000A36 SERIES
Electrical Specifications
Notes 1. 2
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
-1.0 to +7.0
V
50
rnA
Supply voltage
Vee
Output current
10
Power dissipation
Po
MC-428000A32
16
MC-428000A36
24
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
T"g
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
Condition
Vee
MIN.
TYP.
MAX.
Unit
4.5
5.0
5.5
V
High level input voltage
VIH
2.4
Vee + 1.0
V
Low level input voltage
VIL
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
'C
MAX.
Unit
Capacitance ITA
= 25 ·c, f = 1 MHz)
[MC-428000A32 series]
Parameter
Input capacitance
Data Input/Output capacitance
Symbol
Test Condition
MIN.
TYP.
Cil
AD - A10
121
CI2
WE
137
Cil
RASO - RAS3
48
CI4
CASO - CAS3
48
Cvo
1/00 -1/031
29
pF
MAX.
Unit
pF
[MC-428000A36 series]
Parameter
Input capacitance
Symbol
Test Condition
MIN.
TYP.
Cll
AD - A10
161
CI2
WE
193
CI3
RASO - RAS3
62
pF
Data Input/Output capacitance
CI4
CASO - CAS3
62
CUOl
1/00 - 1/07. 1/09 - 1/016.
1/018 -1/025.1/027 - 1/034
29
CU02
1/08.1/017.1/026.1/035
39
pF
91
NEe
MC-428000A32, 428000A36 SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[MC-428000A32 series]
Parameter
Operating current
Symbol
ICCl
Test condition
RAS, CAS Cycling
tRC = tRC IMIN.I
MIN.
tRAC = 60 ns
860
= 80 ns
780
tRAC
RAS only refresh current
Operating current
Icc2
Icc3
Icc.
RAS, CAS ~ VIH IMIN.)
10 = 0 mA
32
RAS, CAS ~ Vcc - 0.2 V
10= 0 mA
16
RAS Cycling
CAS ~ VIH 1M IN.)
tRC = tRC IMIN.)
10=OmA
tRAC = 60 ns
tRAC = 70 ns
860
tRAC = 80 ns
780
RAS S; VIL IMAX.), CAS Cycling
tRAC = 60 ns
620
tRAC = 70 ns
540
tpc = tpc IMIN.)
(Fast page mode)
Unit
Notes
mA
3,4,7
94Q
tRAC = 70 ns
10= 0 mA
Standby current
MAX.
mA
940
mA
3,4,5,7
mA
3,4,6
mA
3,4
10 = 0 mA
CAS before RAS
Icc,
RAS Cycling
tRC = tRC IMIN.)
refresh current
tRAC =·80 ns
460
tRAe = 60 ns
940
tRAC = 70 ns
860
tRAC = 80 ns
780
10 = 0 mA
I n put leakage current
II IL)
VI = 0 to 5.5 V
All othor pins not under test = 0 V
Output leakage current
lOlL)
+10
pA
-10
+10
pA
Va = 0 to 5.5 V
Output is disabled (Hi-Z)
92
-10
=-5.0 mA
High level output voltage
VOH
10
Low level output voltage
VOL
10 = +4.2 mA
2.4
V
0.4
V
NEe
MC-428000A32, 428000A36 SERIES
(MC-428000A36 series]
Parameter
Operating current
Symbol
Icc,
Test condition
RAS, CAS Cycling
tRC = tRC 1M IN.)
MIN.
MAX.
tRAC = 60 ns
1,420
tRAC = 70 ns
1,2S0
tRAC = 80 ns
1,140
Unit
Notes
mA
3,4,7
10=OmA
Standby current
RAS only refresh current
Operating current
Icc2
Icc3
Icc.
RAS, CAS;:' VIH IMIN.,
10 = 0 mA
48
RAS, CAS;:' Vcc - 0.2 V
10 = 0 rnA
24
RAS Cycling
CAS;:' VIH IMIN.)
tRC = tRC IMIN.)
10 = 0 mA
tRAC = 60 ns
1,420
tRAC = 70 ns
1,2S0
tRAC = 80 ns
1,140
tRAC = SO ns
980
RAS S VIL lMAX." CAS Cycling
tpc tpc (MIN.)
CI
(Fast page mode)
tRAC = 70 ns
860
=80 ns
740
10 = 0 rnA
tHAC
CAS before RAS
Iccs
RAS Cycling
tRC = tRC 1M IN.,
refresh current
tRAC = SO ns
1,420
tHAC = 70 ns
1,2S0
tHAC = 80 ns
1,140
mA
rnA
3,4,5,7
rnA
3,4,6
rnA
3,4
10=OmA
Input leakage current
hili
VI = 0 to 5.5 V
All other pins not under test = 0 V
Output leakage current
10 III
-10
+10
pA
-10
+10
pA
0.4
V
Vo = 0 to 5.5 V
Output is disabled (Hi-Z)
High level output voltage
VOH
10 = -5.0 mA
Low level output voltage
VOL
10 = +4.2 rnA
2.4
V
93
NEe
MC-428000A32, 428000A36 SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
[MC-428000A32 series]
Parameter
Symbol
tRAe
MIN.
94
= 60 ns
tRAe
= 70 ns
tRAe
MAX.
MIN.
MAX.
MIN.
=
80 ns
Unit
Notes
MAX.
Read/Write Cycle Time
tRe
110
130
150
Fast Page Mode Cycle Time
tpe
40
45
50
Access Time from RAS
tRAe
60
70
80
ns
10, 11
Access Time from CAS
teAe
15
18
20
ns
10,11
Access Time Column Address
tAA
30
35
40
ns
10, 11
Access Time from CAS Precharge
tAep
40
45
ns
11
RAS to Column Address Delay Time
tRAo
15
35
30,
40
ns
10
CAS to Data Setup Time
teLZ
0
ns
11
Output Buffer Turn·off Deiay Time from CAS
tOFF
0
15
0
20
ns
12
Transition Time (Rise and Fall)
tT
3
50
3
50
ns
RAS Prccharge Time
tAP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tnA~p
60
125,000
70
125,000
80
125,000
ns
10,000
18
10,000
20
15
35
0
17
ns
ns
0
0
15
3
50
50
60
18
ns
RAS Hold Time
tRSII
15
CAS Pulse Width
teAs
15
20
CAS Hold Time
tesH
60
RAS to CAS Delay Time
tReo
20
CAS to RAS Precharge Time
teRP
5
5
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tep
10
10
10
ns
70
40
20
ns
10,000
80
50
25
ns
ns
60
5
ns
10
ns
13
RAS Prechorgo CAS Hold Time
tRPe
5
5
5
ns
RAS Hold Time from CAS Prechargo
tRHep
35
40
45
ns
Row Address Setup Time
tASA
0
0
0
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tAse
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAl
30
35
40
ns
Read Command Setup Time
tRes
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tReH
0
0
0
ns
14
WE Hold Time Referenced to CAS
tWCH
10
10
15
ns
15
Data-in Setup Time
tos
0
0
0
ns
16
Data-in Hold Time
toH
10
15
15
ns
16
Write Command Setup Time
twes
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tesR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
teHR
10
10
10
ns
WE Setup Time
twSR
10
10
10
ns
WE Hold Time
twHR
15
15
15
Refresh Time
tREF
32
32
ns
32
ms
NEe
MC-428000A32, 428000A36 SERIES
[MC-428000A36 series]
Parameter
Symbol
tAAC
= 60 ns
tAAC
MIN.
MAX.
MIN.
ReadIWrite Cycle Time
tAC
110
40
= 70
ns
tAAC
MAX.
MIN.
130
= 80
ns
Unit
Notes
MAX.
150
ns
Fast Page Mode Cycle Time
tpc
Access Time from RAS
tAAC
60
70
80
ns
Access Time from CAS
tCAC
15
20
20
ns
10, 11
Access Time Column Address
tAA
30
35
40
ns
10, 11
Access Time from CAS Precharge
tACP
35
40
45
ns
11
RAS to Column Address Delay Time
tAAO
40
ns
10
15
45
30
15
50
35
17
0
ns
0
10, 11
CAS to Data Setup Time
tClZ
0
ns
11
Output Buffer Turn-off Delay Time from CAS
to"
0
15
0
15
0
20
ns
12
Transition Time (Rise and Fall)
tT
3
50
3
50
3
50
ns
RAS Precharge Time
tllP
40
RAS Pulse Width
tAAS
60
10,000
70
50
10,000
80
60
10,000
ns
RAS Pulse Width (Fast Page Mode)
tAASP
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
tASH
20
CAS Pulse Width
tCAS
15
20
10,000
20
ns
20
10,000
70
20
ns
10,000
ns
60
ns
10
13
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tACO
20
CAS to RAS Precharge Time
tCAP
10
10
10
ns
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tAPC
10
10
10
ns
RAS Hold Time from CAS Precharge
tAHCP
35
40
45
ns
Row Address Setup Time
tASA
0
0
0
ns
Row Address Hold Time
tAAH
10.
10
12
ns
Column Address Setup Time
tASC
0
a
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tAAL
30
35
40
ns
Read Command Setup Time
tACS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tAAH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tACH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twCH
15
15
15
ns
15
Data-in Setup Time
tos
0
0
0
ns
16
40
20
80
50
25
ns
Data-in Hold Time
tOH
15
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tCSA
10
10
10
ns
ns
CAS Hold Time (CAS before RAS Refresh)
tCHA
10
10
10
WE Setup Time
twsA
10
10
10
ns
WE Hold Time
tWHA
15
15
15
ns
Refresh Time
I Distributed refresh
I Burst refresh
tAEF
32
32
32
ms
·16
16
16
ms
95
NEe
MC-428000A32, 428000A36 SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3.
4.
5.
6.
Iccl, IcC3, Icc4 and Iccs depend on cycle rates (tRC and tpc).
Specified values are obtained with outputs unloaded.
Icc3 is measured assuming that all column address inputs are held at either high or low.
IcC4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. IcCl and Icc3 are measured assuming that address can be changed once or less during RAS:5 VIL
(MAX.) and CAS ~ VIH (MIN.).
S. AC measurements assume tT
= 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
VII'
,M'' , = 2.4 V .----------~-----,i
i
VII
,MAXI
______________
I
I
,
= 0.8 V
,
,
I
I
: :
.:
tT = 5 ns
I
:, ;.
:
tT = 5 ns
(2) Output timing specification
VOH
IMIN.)
=2.4 V
------.~------
VOL IMAX.) = 0.4 V ------ .. ------
}-
\.--..-.J
10. For read cycles, access time is defined as follows:
Input
tRAD
S
tRAD
> tRAD (MAX.)
tRCD
> tRCD (MAX.'
Conditions
tRAD (MAX., and tRCD
and tRCD
Access Time
Access Time from RAS
S
tRCD (MAX.)
tRAC (MAX.)
tRAC(MAX.)
S
tRCD (MAX.)
tAA(MAX.)
tRAD
+ tAA (MAX.)
tCAC(MAX.)
tRCD
+ tCAC (MAX.,
tRAD(MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.)
and tRCD
~
tRCD (MAX.) will not cause any operation problems.
11. Loading conditions are 2 TILs and 100 pF.
12. tOFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13. tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
14. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
15. In early write cycles, twCH (MIN.) should be met.
16. tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles.
17. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
96
Timing Chart
Please refer to Timing Chart 2, page 375.
97
NEe
MC-428000A32, 428000A36 SERIES
Package Drawings
[MC-428000A32B. 428000A32F]
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
B
R~-+------------------------------------------~
N
~s 00000000,
p
c
D
detail of
® part
w
~x
0>
E
ITEM
MILLIMETERS
INCHES
A
107.95±0.13
4.250±0.006
B
101.19±0.13
3.984 :8:88~
c
44.45
6.35
44.45
1.750
0.250
D
E
N
P
10.16
1.27 (T.P.)
6.35
2.03
6.35
25.4
9.0 MAX.
Rl.57
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.000
0.355 MAX.
RO.062
R
3.38±0.13
0.133:8:GGG
s
tP3.18
tPO.125
T
1.27:8:68
0.050±0.004
u
5.5 MIN.
0.25 MAX.
1.04±0.05
2.54 MIN.
0.216 MIN.
0.010 MAX.
O.04HO.OO2
0.100 MIN.
G
H
J
K
_M
V
W
X
M72B-50A55
98
NEe
MC-428000A32, 428000A36 SERIES
[MC-428000A36BJ, 428000A36FJ]
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
I","
N
"iI
B
0000000000
c::::::] c::::::] C::: C:::
s
:::::J
:::::J
c
E
o
o
0000000000
detail of ® part
i!-
-*x
[8:(
ITEM
A
B
C
0
E
MILLIMETERS
107.95±0.13
101.19
44.45
6.35
INCHES
4.250±0.006
3.984
1.750
0.250
K
M
N
P
44.45
10.16
1.27 (T.P.)
6.35
2.03
6.35
31.75
9.0 MAX.
R1.57
0.050 (T.P.)
0.250
0.080
0.250
1.250
0.355 MAX.
RO.062
S
413.18
410.125
G
H
1.750
0.400
T
1.27~g:68
0.050±0.004
u
3.17 MIN.
V
0.25 MAX.
1.04±0.05
3.15 MIN.
0.124 MIN.
0.010 MAX.
0.041 ±0.002
0.124 MIN.
W
X
M72B-50A50
99
4 Byte SIMM
[Hyper Page (EDO)]
101
PRELIMINARY DATA SHEET
(CMOS
~~l'IEGRATIED
CIRCUIT
MC=421000F32
1 M·WOIRD IBV 32·1811" DVNAMIC /RAM MODULE
IHIVPER PAGE MODE (ECO)
Description
The MC-421000F32 is a 1,048,576 words by 32 bits dynamic RAM module on which 2
pieces of 16M DRAM: pPD4218165 are assembied.
These modules provide hige density and large quantities of memory in a small space without utilizing
the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
features
o
o
o
Hyper page mode (EDO)
1,048,576 words by 32 bits organization
Fast access and cycle time
Family
Access time
R/W cycle time
Hyper page mode
(MAX.)
(MIN.)
cycle time (MIN.)
Power consumption
(MAX.)
Active
Standby
MC421000F32-60
60 ns
104 ns
25 ns
1,760 mW
11 mW
MC421000F32-70
70 ns
124 ns
30 ns
1,650mW
(CMOS level input)
1,024 refresh cycle I 16ms
CAS before RAS refresh, RAS only refresh, Hidden refresh
o 72-pin single in-line memory module (Pin pitch = 1.27 mm)
o Single +5.0 V ±0.5 V power supply
o Access time can be distinguished with characteris1ics of PO-pins (PDO to PD3)
o
o
D43BEJ1 VODSOO (Japan)
Tho Infonnatlon In thlG documont IG oubJoct to chlll\go without notlco.
103
NEe
MC-421000F32
Ordering Infonnation
Part number
104
Access time
(MAX.)
MC-421000F32BA-60
60 ns
MC-421000F32BA-70
70 ns
MC-421000F32FA·60
60 ns
MC-42 1000F32FA-70
70 ns
Package
Mounted devices
72·pin Single In·line Memory Module (Socket Typel
Edge connector: Solder coatlng(HAL)
2 pieces of II PD421S165LE
72·pln Single In·llne Memory Module (Socket TVpe)
Edge connector: Gold plating
(Single side)
(400mil SOJ)
NEe
MC-421000F32
Pin Configuration
72-pin Single In-line Memory Modulo Socl(et TVPo (Edge connector: Solder coating, Gold plating)
GND
1/00
V016
1/01
1/017
1/02
1/018
1/03
1/019
Vee
NC
AD
A1
A2
A3
A4
AS
A6
NC
V04
V020
V05
V021
V06
V022
1/07
1/023
A7
NC
Vee
A8
A9
NC
RAS2
NC
NC
NC
NC
Jill.Q
C
~2
CAS3
CAS1
RASO
NC
.NC
WE
NC
1/08
V024
V09
V025
V010
V026
V011
V027
V012
V028
Vee
1/029
V013
V030
1/014
V031
1/015
NC
PDO
PD1
PD2
PD3
NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
o
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
AO-A9
: Address Inputs
I/OO-V031
: Data Inputs/Outputs
43
CASO-CAS3
: Column Address Strobe
44
45
RASD,RAS2
: Row Address Strobe
46
WE
: Write Enable
48
Vcc
: Power Supply
GND
: Ground
NC
: No connection
40
41
42
47
49
50
51
52
53
54
The internal connection of PO pins (POD to P03)
55
56
57
58
59
60
61
62
63
depends on access times_
64
65
66
67
68
69
70
71
72
o
AcceasTime
Pin
No.
SOns
70ns
PDQ
67
GND
GND
PD1
68
GND
GND
PD2
PD3
68
NC
NC
GND
Pin
Name
70
NC
105
NEe
MC-421000F32
Block Diagram
WE
RASO
CAS1
CASO
WE
VOO
VOl
V02
V03
V04
V05
V06
V07
VOB
va 9 ()4
1/010()4
VO 11
VO 12
VO 13
VO 14
va 15
DO
OE
RAS2
CAS3
CAS2
VO 16
VO 17
VO lB
VO 19
V020
va 21
va 22
V023
V024
V025
V026
va 27
V02B
V029
V030
V031
WE
VOl
V02
V03
V04
V05
va6
V07
VOB
V09
VO 10
va 11
VO 12
va 13
va 14
VO 15
VO 16
D1
OE
AO-A90
VccO
GNOO
106
• 00,01
::t:
• 00,01
:;::CO, C~ ~O, 01
Remark ~O, 01:J.t P0421 B165
NEe
MC-421000F32
Electrical Specifications
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on Any Pin Relative to GND
VT
-1.0 to +7.0
V
Supply Voltage
Vee
-1.0 to +7.0
V
Output Current
10
50
rnA
Power Dissipation
Po
2
W
Operating Ambient Temperature
TA
o to +70
·C
Storage Temperature
Tot;
-55 to +125
·C
Caution
Exposing the device to stress above thoBe listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated undor conditions outside the limits
described in the operational section of this opecification. Expoaure to Absolute Maximum Rating
conditions for extended periodo may affect devico reliability.
Recommended Operating Conditions
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Supply Voltage
Vee
4.6
5.0
5.5
V
High Level Input Voltage
VIH
2.4
Vee +1.0
V
Low Level Input Voltage
VIL
-1.0
+0.8
V
Operating Ambient Temperature
TA
0
70
·C
MAX.
Unit
pF
Capacitance (Ta
Condition
= 25 ·C, f = 1 MHz)
Parameter
Input Capacitance
Data Input!Output Capacitance
Symbol
Coridition
MIN.
TYP.
CII
AO· A9
30
CI2
WE
34
Cia
RASa. RAS2
22
CI4
CASO ·CAS3
22
eVD
1/00·1/031
20
pF
107
NEe
MC-421000F32
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
RAS, CAS Cycling
Operating current
IcCl
MIN.
MAX.
tRAc=60 ns
320
tRAc=70 ns
300
tRC = tRcIMIN.)
10=OmA
Unit
Notes
mA
1,2,3
RAS, CAS St; VIH IMIN.I, 10 = 0 mA
4
Standby current
Icc2
mA
RAS, CAS St; Vcc - 0.2 V, 10 = 0 mA
2
RAS Cycling
CAS St; VIH IMIN.)
RAS only refresh current
IcC3
RAS ~ VIL IMAX.)
Icc4
CAS Cycling
tHPC = tHPC IMIN.)
10 = 0 mA
RAS Cycling
CAS before RAS
refresh current
IcC5
Input leakage current
Ii III
Output leakage current
lOll)
320
tRAc=70 ns
300
tRAc=60ns
220
tRAc=70ns
200
tRAc=60ns
320
tRAc=70 ns
300
tAc = tRC IMIN.I
10= 0 mA
Oporating current
(Hyper page modo)
tRAc=60 ns
=tRC IMIN.)
10 = OmA
tRC
VI = Oto 5.5 V
all other pins not under test = 0 V
Vo = Oto 5.5 V
mA
1,2,3.4
mA
1,2,5
mA
1.2
-10
+10
pA
-10
+10
pA
Output is disabled CHi-ZJ
High level outputvoltageloVl
VOH
10=-2.5 mA
level output voltage
VOL
10 = +2.1 mA
Not..
1.
ICC1, IcCl, IcC4, Iccs depend on cycle rates (tRC and tHPC).
2.
Specified values are obtained with outputs unloaded.
3.
2.4
V
0.4
V
ICCl and IcC3 are measured assuming that address can be changed once or less during RAS :!i!
VILIMAX.I and CAS St; VIHIMIN.).
4. Icca is measured assuming that all column address inputs are held at either high or low.
S.
Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page cycle.
108
NEe
MC-421000F32
AC Characteristics (Recommended Operating Conditions unl... otherwi.. noted)
AC Characteristics T..t Conditions
(1) Input timing specification
(2) Output timing specification
VIH (MIN.)
= 2.4 V ---------------
VIL (MAX.I
= 0.8 V·--·---------
'
'
VOH (MIN.)
= 2.4
V------.-.-.·.·.·.·t...___""': ......
VOL (MAX.)
= 0.4
V------------\
I
n=2 ns
(3) Loading conditions are 100 pF + 1 TILs.
Common to Read, Write Cycle
Parameter
Symbol
tRAC" 60 ns
tRAC" 70 ns
MIN.
MAX.
MIN.
MAX.
Read I Write Cycle Time
tRC
104
-
124
RAS Precharge Time
tRP
40
-
60
-
~ Precharge Time
-
10
-
Unit Notos
ns
ns
tCPN
10
Pulse Width
tRAS
60
10000
70
10000
ns
CAS Pulse Width
tCAS
10
10000
12
10000
ns
"RAS
12
-
ns
60
-
ns
46
14
62
ns
1
12
30
12
36
ns
1
6
-
6
-
ns
2
-
10
-
ns
0
-
ns
12
-
ns
RAS Hold Time
tRSH
10
CAS Hold Time
tCSH
40
RAS to CAS Delay Time
tRCO
14
RAS to Column Address Delay Time
tRAD
m to m
tCRP
Row Address Setup Time
lAsR
0
Row Address Hold Time
t!\AH
10
Column Address Setup Time
lAsc
0
Column Address Hold Time
tCAH
10
CAS to Data Setup Time
tCLl
0
Transition Time (Rise and Fall)
tr
1
Refresh Time
tREF
Precharge Time
ns
-
-
0
ns
0
-
ns
60
1
60
ns
16
-
16
ms
109
NEe
MC-421000F32
Notes 1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD:S tRAD (MAX.) and tRCD;:a; tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD> tRAD (MAX.) and tRCD;:a; tRCD (MAX.)
tAA(MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD(MAX.) and tRCD(MAX.) are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAc, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD i1:; tRAD(MAX.) and tRCD i1:;
tRCD(MAX.) will not cause any operation problems.
2. tCRP(MIN.) requirement is applied to RAS, CAS cycles.
Read Cycle
Parameter
Svmbol
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
-
60
-
70
ns
1
15
ns
1
1
Unit Notes
Access Time from RAS
tRAC
Access Time from CAS
tCAC
-
18
Access Time from Column Address
1M
-
30
-
35
ns
Column Addre99 Lead TIme Referenced to RAS
tRAL
30
0
Read Command Hold TIme Referenced to RAS
tRRH
0
0
Read Command Hold Time Referenced to CAS
tACH
0
-
-
ns
tRCS
-
36
Read Command Setup Time
0
0
ns
ns
2
ns
2
Notes 1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD;:a; tRAD (MAX.) and tRCD;:a; tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD> tRAD (MAX.) and tRCD;:a; tRCD (MAX.)
tAA(MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAx.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD(MAX.) and tRCD(MAX.) are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, 1M or tCAC) is to be used for finding
out when output data will be available. Therefore, the input cDndit'ions tRAD i1:; tRAD(MAX.) and tRCD i1:;
tRCD(MAX.) will not cause any operation problems.
2. Either tRCH(MIN.) or tRRH(MIN.) should be met in read cycles.
110
NEe
MC-421000F32
Write Cycle
Parameter
Symbol
tRAC e 60 ns
tRAc =70 ns
MIN.
MAX.
MIN.
MAX.
Unit Notes
WE Hold Time Referenced to CAS
twCH
10
-
ns
twcs
0
-
10
WE Setup Time
0
-
ns
1
Data-in Setup Time
tos
0
-
0
-
ns
2
Data-in Hold Time
tOH
10
-
10
-
ns
2
Not.. 1. If twcs s: twcsIMIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
2. tOSIMIN.) and tOHIMIN.) are referenced to the CAS falling edge in early write cycles.
111
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MC-421000F32
Hyper Page Mode
Symbol
Parameter
tRAC
=60 ns
tRAC
MIN.
MAX.
MIN.
=70 ns
MAX. Unit Notes
-
Read I Write Cycle Time
tHPC
26
-
30
FOIS Pulse Width
tRAsP
60
126000
70
126000 ns
CAS Pulse Width
tHCAS
10
10000
12
10000
ns
CAS Precharge Time
tcp
10
-
10
-
ns
Access Time from I:1i:S Precharge
tAcp
-
36
-
40
ns
-
ns
ns
1
RAS Hold Time from CAS Precharge
tRHCP
36
-
40
Data Output Hold Time
tOHC
6
-
6
-
ns
Output Buffer Turn-off Delay from WE
twez
0
13
0
16
ns
3
2,3
WE Pulse Width
twPz
10
-
10
-
ns
Output Buffer Turn-off Delay from RAS
tOFR
0
13
0
16
ns
2.3
Output Buffer Turn-off Delay from CAS
tOFC
0
13
0
16
ns
2.3
Not•• 1.
tHPCIMIN.1 is applied to access time from CAS
2.
tOFcIMAx'I, tOFRIMAx.1 and tweZIMAX.1 define the time when the output achieves the condition of Hi-Z and
3.
To make II0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE as follows. The
is not referenced to VOH or VOL.
-- - - -
effective specification depends on state of each signal.
(1) Both RAS and CAS are Inactive (at the end of read cycle)
WE : inactive
tOF,C is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
--
--
--
--
(2) Both RAS and CAS .are inactive or RAS is active and CAS is inactive(at the end of read cycle)
WE : active and either tRRH or tRCH must be met.. • twez and twPz is effective.
Refresh Cycle
tRAC
Parameter
Symbol
CAS Setup Time
CAS Hold Time (CAS before
W
Precharge
m
Refresh)
CAS Hold Time
WE Hold Time (Hidden Refresh Cycle)
112
=60 ns
tRAC -70 ns
Unit
MIN.
MAX.
MIN.
MAX.
ns
ns
tCSR
6
-
6
tCHR
10
-
10
tRPC
6
6
twHR
16
-
-
16
-
ns
ns
Note
Timing Chart
Please refer to Timing Chart 3, page 385.
113
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MC-421000F32
Package Drawings
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
N
-U-T
[EJ
J
c
D
E
o
o
detail of
® Part
*x
0>
ITEM
A
B
C
0
E
MILLIMETERS
107.95:1:0.13
101.19
44.45
6.35
G
K
M
N
P
S
10.16
1.27 (T.P.)
6.35
2.03
6.35
25.4
5.08 MAX.
R1.57
,3.18
INCHES
4.250:1:0.006
3.984
1.750
0.250
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.000
0.200 MAX.
RO.062
;0.125
'r
1.27.:!:8:~8
0.050:1:0.004
v
0.25 MAX.
1.04:1:0.05
3.15 MIN.
3.17 MIN.
0.010 MAX.
0.041 :1:0.002
0.124 MIN.
0.124 MIN.
M72B-liOA46
H
J
W
X
Y
114
4~.45
PRELIMINARY DATA SHEET
~EC/
CMOS INTEGRATED CIRCUIT
MC-422000F32
2 M-WORD BY 32-BIT DYNAMIC RAM MODULE
HYPER PAGE MODE (EDO)
Description
The MC-422000F32 is a 2,097,152 words by 32 bits dynamic RAM module on which 4
pieces of 16M DRAM: pPD4218165 are assembied.
These modules provide hige density and large quantities of memory in a small space without utilizing
the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• Hyper page mode (EDO)
o 2,097,152 words by 32 bits organization
o Fast access and cycle time
Family
Access time
R/W cycle time
Hyper page mode
(MAX.)
(MIN.)
Power consumption
(MAX.)
cycle time (MIN.)
Active
Standby
MC-422000F32-60
60 ns
104 ns
25 ns
1,782 mW
22mW
MC-422000F32-70
70 ns
124 ns
30 ns
1,122 mW
(CMOS lavel input)
o 1,024 refresh cycle I 16ms
o CAS before RAS refresh, RAS only refresh, Hidden refresh
• 72-pin single in-line memory module (Pin pitch = 1.27 mm)
• Single +5.0 V ±0.5 V power supply
• Access time can be distinguished with characteristics of PO-pins (PDO to PD3)
The Infonnlltlon In til.. document .. IUbject to chMp without notice.
·39EJ1VODSOO (Japan)
115
NEe
MC-422000F32
Ordering Information
Part number
116
Access time
(MAX.)
Package
MC-422000F32BA-60
60 ns
72-pln Single In-line Memory Module CSocket Typel
MC-422000F32BA-70
70 ns
Edge connector: Solder coatlngCHALI
MC-422000F32FA-60
60 ns
72-pln Single In-line Memory Module CSocket Typel
MC-422000F32FA-70
70 ns
Edge connector: Gold plating
Mounted devices
4 pieces of", PD421S165LE
(400mil SOJ)
(Single sidel
NEe
MC-422000F32
Pin Configumtion
72-pin Single In-line Momory Modulo Soc![ot TVPo (Edgo connocior : Soldor coating, Gold plating)
GND
1/00
1/016
1/01
1/017
1/02
1/018
1/03
1/019
Vee
NC
AO
A1
A2
A3
A4
A5
A6
NC
1/04
1/020
1/05
1/021.
1/06
1/022
1/07
1/023
A7
NC
Vee
A8
~
RAS3
RAS2
NC
NC
NC
NC
GND
CASO
CAS2
CAS3
~
.BASil
RAS1
.lli;
WE
NC
1/08
1/024
1/09
1/025
1/010
1/026
1/011
1/027
1/012
1/028
Vee
1/029
1/013
1/030
1/014
1/031
1/015
NC
PDO
PD1
PD2
PD3
NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
o
37
38
39
40
41
42
AO-AS
43
44
45
46
47
48
49
50
51
52
53
54
: Data Inputs/Outputs
CASD-CAS3
: Column Address Strobe
RASD-RAS3
: Row Address Strobe
WE
: Write Enable
Voo
: Power Supply
GNO
: Ground
NC
: No connection
The internal connection of PO pins (POD to P03)
55
56
57
58
59
60
61
62
63
depends on 800ess times.
64
65
66
67
68
69
70
71
72
: Address Inputs
1/00-1/031
o
AcceIls Time
Pin
Pin
Noma
No.
60""
70n&
NC
POD
01
NC
POl
68
NC
NC
PD2
69
NC
GND
POl
70
NC
NC
117
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MC-422000F32
Block Diagram
Remark 00·03 : JlPD4218165
WE
~
RASO
CASl
CASO
t
,
,
1
1/00 0 - - I/O 1 LCAS UCAS RAS WE
I/O 1 0 - - 1/02
1/02 0------0 1/03
1/03 0 - - 1/04
1/04 0 - - 1/05
V05 0 - - 1/06
1/06 0 - - 1/07
V07 0 - - I/O B
DO
VOB 0 - - I/O 9
1/09 0 - - I/O 10
I/O 10 0 - - 1/011
1/011 Q 4 - - I/O 12
I/O 12 Q 4 - - 1/013
I/O 13 0 - - I/O 14
1/014 0 - - 1/015
I/O 15 0 - - 1/016
~Im-
+
~Im-
+
+
1/018 0 - I/O 19 0 - 1/020 0 - 1/021 0 - 1/022 0 - 1/023 0 - 1/024. 0 - 1/025, 0 - 1/026io-1/027' 0 - 1/0281 0 - 1/0291 0 - 1/0301 0 - 1/031 0 - -
1/03
1/04
1/05
1/06
1/07
1/08
1/09
1/010
1/011
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
WE
118
RAS3
1
I/O 1 LCAS UCAS RAS WE
01
OE
1
1/01 LCAS UCAS RAS WE
1/02
1/03
1/04
1/05
1/06
1/07
1/08
02
1/09
1/010
I/O 11
I/O 12
I/O 13
1/014
1/015
1/016
I
I/O 16 0 - - I/O 1 LCAS UCAS RAS
I/O 17 0 - - 1/02
RASl
-:rtr
1/02
1/03
1/04
1/05
1/06
1/07
1/08
1/09
I/O 10
1/011
I/O 12
I/O 13
1/014
I/O 15
I/O 16
03
OE
AO-A90
.00-03
Vee 0
GNO 0
:oL CO-C3" 00-03
T
• 00-03
--:rh-
NEe
MC-422000F32
Electrical Specifications
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on Any Pin Relative to GND
VT
-1.0 to +7.0
V
Supply Voltage
Vee
-1.0 to +7.0
V
Output Current
10
50
mA
Power Dissipation
Po
4
W
Operating Ambient Temperature
TA
oto +70
·C
Storage Temperature
Tatg
-55 to +125
·C
Caution
Exposing tho device to Btreoo above thosa listed in Absolute Maximum Ratings could cause
permanent damage. Tho devico io not meant to be operated under conditions outsido the limim
d8I3Cribed in 1he operational ooction of thiD opacification. Expooure to Abooluta Maximum Rating
conditiono gor emended periodo may affect device reliability.
Recommended Operating Conditions
MIN.
TYP.
MAX.
Supply Voltage
Vee
4.5
5.0
5.6
V
High Level Input Voltage
VIH
2.4
Vee +1.0
V
Low Level Input Voltage
VIL
-1.0
+0.8
V
Operating Ambient Temperature
TA
0
70
°C
MAX.
Uni~
pF
Parameter
Symbol
Condition
Unit
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance
Data Input/Output Capacitance
Symbol
Condition
MIN.
TYP.
ell
AO-A9
40
CI2
WE
48
CI3
RASO - RAS3
22
CI4
CASO -CAS3
29
Cvo
1/00 - V031
26
pF
119
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MC-422000F32
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
RAS, CAS Cycling
Operating current
lecl
tRC - tRC(MIN.)
10=OmA
MIN.
MAX.
tRAe-60 ns
324
tRAe=70 ns
304
Unit
Notes
mA
1.2,3
RAS, CAS ~ VIH (MIN.),lo = 0 mA
8
Standby current
lee2
mA
RAS, CAS ~ Vee - 0.2 V, 10.0 mA
RAS only refresh current
leC3
RAS Cycling
CAS ~ V)H IMIN.)
tRc = tRC (MIN.)
10 = 0 mA
RAS ~ VIL (MAX.)
Operating current
(Hyper page model
Icc4
CAS Cycling
tHPC = tHPC IMIN.)
10
= 0 mA
RAS Cycling
CAS before RAS
refresh curront
Icc5
tRC
=tRC IMIN.)
10 = 0 mA
tRAc=60 ns
IIIL)
Output lookage current
10(L)
High level outputvoltageLow
VOH
10
=-2.5 mA
level output voltage
VOL
10
c
Va
c
324
tRAe .. 70 ns
304
tRAe=60ns
224
tRAc=70 ns
204
mAc=60 ns
324
tRAc=70 ns
304
VI = 010 5.5 V
ell othor pins not under test .. 0 V
Input lonknge curront
4
0 to 5.5 V
OUlput is disabled (Hi-Zl
+2.1 mA
mA
1,2,3,4
mA
1.2,6
mA
1.2
-10
+10
IIA
-10
+10
#AA
2.4
V
0.4
V
Notes 1. ICC1, IcC3, Icc4, Icc5 depend on cycle rates (mc and tHPC).
2. Specified values are obtained with outputs unloaded.
3. ICCI and IcC3 are measured assuming that address can be changed once or less during RAS :!
VILlMAX.) and CAS ~ VIHIMIN.).
4. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page cycle.
120
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MC-422000F32
AC Characteristics IRecommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
2.4 V
VIH (MIN.)
=
VIL (MAX.)
= 0.8 V·------------
(2) Output timing specification
---------------
'
VOH (MIN.)
'
VOL (MAX.)
=
=
2.4
--J:-I
V------------------J...___
0.4 V------------\:.
n
-.
tT= 2 ns
(3) Loading conditions are 100 pF + 1 TTLs.
Common to Read, Write Cycle
Parameter
Symbol
tRAC
MIN.
=60 ns
tRAC
=70 ns
MAX.
MIN.
MAX.
124
10
-
Unit Notoa
Read I Write Cycle Time
tIIc
104
RAS Precharge Time
tRP
40
-
~ Precharge Time
tCPN
10
-
'RAS Pulse Width
tRAS
60
10000
70
10000
ns
CAS Pulse Width
tCAs
10
10000
12
10000
ns
RAS Hold Time
tRSH
10
-
12
ns
CAS Hold Time
tCSH
40
-
60
-
60
ns
ns
ns
ns
RAS to CAS Delay Time
tRCD
14
46
14
62
ns
1
RAS to Column Address Delay TIme
tRAD
12
30
12
36
ns
1
~ to 'RAS Precharge Time
tCRP
6
6
2
tAlR
0
Row Address Hold TIme
tRAH
10
Column Address Setup TIme
tAlc
0
Column Address Hold TIme
tCAH
10
-
10
12
-
ns
Row Address Setup TIme
-
CAS to Data Setup Time
tcLZ
0
-
0
-
ns
Transition TIme (Rise and Falll
tT
1
60
1
60
ns
Refresh Time
tREF
16
-
16
ms
-
0
0
ns
ns
ns
ns
121
NEe
Notes 1.
MC-422000F32
For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD S tRAD (MAX.I and tRCD:a tRCD (MAltI
tRAC (MAX.I
tRAC (MAX.I
tRAD> tRAD (MAX.I and tRCD S tRCD (MAX.I
tAA(MAX.1
tRAD + tAA (MAX.I
tRCD > tRCD (MAX.I
tCAC (MAltI
tRCD + tCAC (MAX.I
tRAD(MAX.1 and tRCD(MAX.1 are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAc, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD ~ tRAD(MAX.1 and tRCD ~
tRCD(MAX.1 will not cause any operation problems.
2. tCRP(MIN.1 requirement is applied to RAS, CAS cycles.
Read Cycle
Parameter
Svmbol
Access Time from RAS
tRAc
Access Time from CAS
tCAC
tRAC
=60 ns
tRAC
Unit Notes
MIN.
MAX.
MIN.
MAX.
-
60
-
70
ns
1
15
-
18
ns
1
30
-
35
ns
1
-
ns
-
ns
Access Time from Column Address
tAA
Column Address Lead Time Referenced to RAS
tRAL
30
-
35
Read Command Setup Time
tRCS
0
-
0
Read Command Hold Time Referenced to RAS
tRRH
0
0
Read Command Hold Time Referencod to CAS
tRCH
-
Not.. 1.
=70 ns
0
0
ns
2
ns
2
For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD:a tRAD (MAX.I and tRCD:a tRCD (MAX.I
tRAC (MAltI
tRAC (MAX.I
tRAD> tRAD (MAltI and tRCD:a tRCD (MAX.I
tAA (MAX.I
tRAD + tAA (MAX.I
tRCD > tRCD (MAX.I
tCAC (MAX.I
tRCD + tCAC (MAX.I
tRAD(MAX.1 and tRCO(MAX.1 are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD ~ tRAD(MAX.1 and tRCD ~
tRCD(MAX.1 will not cause any operation problems.
2.
122
Either tRCH(MIN.1 or tRRH(MIN.1 should be met in read cycles.
NEe
MC-422000F32
Write Cycle
Parameter
Symbol
=60 ns
tRAC
=70 ns.
MIN.
MAX.
MIN.
MAX.
-
tRAC
WE Hold Time Referenced to ~
twCH
10
-
10
WE Setup Time
twcs
0
-
0
Data·in Setup Time
tos
0
-
0
Data·in Hold Time
tOH
10
-
10
Not.s 1. If twcs
Unit Notes
ns
ns
1
ns
2
ns
2
~ twcsIMIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
2. tOSIMIN.) and tOHIMIN.) are referenced to the CAS falling edge in early write cycles.
123
NEe
MC-422000F32
Hyper Page Mode
Symbol
Parameter
Read I Write Cycle Time
tHPC
tRAC = 60 ns
MIN. MAX.
tRAC = 70 ns
MIN. MAX. Unit Notes-
25
-
3D
70
125000
ns
12
10000
ns
~
Pulse Width
tRASP
60
125000
~
Pulse Width
tHCAS
10
10000
~
Precharge Time
-
ns
1
tcp
10
-
10
-
ns
Access Time from ~ Precharge
tAcp
-
35
-
40
ns
RAS Hold Time from CAS Precharge
tRHCP
35
40
tDHC
6
6
-
ns
Data Output Hold Time
-
0
16
ns
2,3
ns
Output Buffer Turn-off Delay from WE
twEz
0
13
WE Pulse Width
twPz
10
-
10
-
ns
3
tOFR
0
13
0
16
ns
2.3
tOF~
0
13
0
16
ns
2.3
Output Buffer Turn-off Delay from RAS
Output Buffer Turn-off Delay from CAS
Notes 1.
2.
tHPC(MIN.) is applied to access time from CAS
tOFcIMAl<.), tOFAIMAX.) and twEZ(MAX.) define the time when the output achieves the condition of Hi-Z and
is not referenced to VOH or VOL.
3.
-- - - -
To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE as follows. The
effoctive specification depends on state of each signal.
(1) Both RAS and CAS are Inactive (at the end of read cycle)
WE : inactive
tOFC is effective when RAS is inactivated before CAS is inactivated.
--
---
tOFA is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are inactive or RAS is active and CAS is inactivelat the end of read cycle)
WE : active and either tRRH or tRCH must be met.. • twEz and twPz is effective.
Refresh Cycle
tRAC
Symbol
Parameter
tRAC. 70 ns
Unit
MAX.
MIN.
MAX.
tCSR
6
-
ns
10
-
6
tCHR
10
-
ns
RAS Precharge CAS Hold Time
tRPC
6
-
6
-
ns
WE Hold Time (Hidden Refresh Cycle)
twHR
15
-
16
-
ns
CAS Setup Time
CAS Hold Time
124
=60 ns
MIN.
(m before m
Refresh)
Note
Timing Chart
Please refer to Timing Chart 3, page 385.
125
NEe
MC-422000F32
Package Drawings
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
il
..
B
1.
S
\
GI ~T
~
I
, I
I\.
I
II
ClCl <+
'111111111I111J III I!
'1111111111111111111111111111111111 '
JL/
"
"i,
>-
[8J
J
c
o
-U-T
E
0
°Il
II
detail of
® Part
*x
[]J>
ITEM MILLIMETERS
A
107.9S±0.13
B
101.19
44.45
C
8.35
0
'44.45
E
G
10.18
1.27 (T.P.)
H
8.35
2.03
J
K
M
N
P
S
~8.35
25.4
9.0 MAX.
R1.57
INCHES
4.250±D.008
3.984
1.750
0.250
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.000
0.355 MAX.
RO.082
~3.18
~O.125
T
1.27~:~8
0.050±0.DD4
V
0.25 MAX.
1.04±0.05
3.15 MIN.
3.17 MIN.
0.010 MAX.
0.041±D.002
0.124 MIN.
0.124 MIN.
11728.Q1A4&
W
X
Y
126
N
PRELIMINARY DATA SHEET
CMOS INTEGRATED CIRCUIT
-.lEe/
MC-424000F32
4 M-WORD BY 32-BIT DYNAMIC RAM MODULE
HYPER PAGE MODE eEDO)
Description
The MC-424000F32 is a 4,194,304 words by 32 bits dynamic RAM module on which 8 pieces of
16M DRAM: I'PD4217405 are assembied.
These modules provide hige density and large quantities of memory in a small space without utilizing
the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• Hyper page mode (EDO)
• 4,194,304 words by 32 bits organization
o Fast access and cycle time
Family
Power consumption
(MAX.)
Access time
R/W cycle time
Hyper page mode
(MAX.)
(MIN.)
cycle time (MIN.)
Active
Standby
MC-424000F32-60
60 ns
104 ns
25 ns
4,840mW
44mW
MC-424000F32-70
70 ns
124 ns
30 n8
4,400mW
(CMOS level input)
•
•
•
•
•
2,048 refresh cycle I 32ms
CAS before RAS refresh, RAS only refresh, Hidden refresh
72-pin single in-line memory module (Pin pitch - 1.27 mm)
Single +5.0 V ±0.5 V power supply
Access time can be distinguished with characteristics of PO-pins (PDO to PD3)
Tho Infonnatlon In this cIocumllllt Is IUb/Kt to chM.. without notice.
533EJ1 VODSOO (Japan)
127
NEe
MC-424000F32
Ordering Information
Part number
128
Access time
(MAX.)
Package
MC-424000F32B-60
60 ns
72-pln Single In-line Memory Module (Socket Typel
MC-424000F32B-70
70 ns
Edge connector: Solder coatlng(HAlI
MC-424000F32F-60
60 ns
72-pin Single In-line Memory Module (Socket Typel
MC-424000F32F-70
70 ns
Edge connector: Gold plating
Mounted devices
8 pieces of It PD4217405LA
(300mil SOJ)
[Single sidel
NEe
MC-424000F32
Pin Configuration
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating, Gold plating)
GND
1/00
1/016
1/01
1/017
1/02
1/018
1/03
1/019
Vee
NC
AO
Al
A2
A3
A4
A5
A6
Al0
1/04
1/020
1/05
1/021
1/06
1/022
1/07
1/023
A7
NC
Vee
A8
A9
NC
RAS2
NC
NC
NC
NC
JlliQ
~
A 2
~
~
RASO
NC
g
WE
NC
1/08
1/024
1/09
1/025
1/010
V026
1/011
1/027
1/012
1/028
Vee
1/029
1/013
1/030
1/014
1/031
V015
NC
PDO
PDl
PD2
PD3
NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
o
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AO-A1D
: Address Inputs
1/00-1/031
: Data Inputs/Outputs
CASO-CAS3
: Column Address Strobe
RASO,RAS2
: Row Address Strobe
WE
: Write Enable
Vee
: Power Supply
GND
: Ground
NC
: No connection
The internal connection of PO pins (POD to PD3)
depends on access times.
Pin
Nama
o
Pin
No.
Access Time
60ns
70ns
PDO
67
GNO
GNO
POl
68
NC
NC
PD2
68
NC
GNO
PD3
70
NC
NC
129
NEe
MC-424000F32
Block Diagram
RASO
CASO
1/00
1/01
1/02
1/03
1/04
1/05
1/06
1/07
~
1/01
1/02
V03
&
~
&
CASl
1/08
1/09
~
1/01
1/02
1/03
1/04
t
CAS RAS
DO
t
t
CAS RAS
01
Oi=
t
1/01
1/02
V03
1/010
CAS RAS
02
UQ4
1/011
&
1/012
1/013
1/014 '::'
1/015
;},RAS2
CAS2
1/016
1/017 ;...
1/018 ;...
11019
Oi=
1/01
1/02
1/03
1/04
~
~
CAS RAS
03
OE
~
1/020 ;...
t
1/01
1/02
1/03
&
1/021
1/022
1/023
~
1/01
1/02
1/03
~4
!
CAS RAS
D4
t
t
CAS RAS
OS
'71r
CAS3
1/024 ;...
1/025
1/026
11027
-
1/028
1/029 "1/030
1/031
&
D6
1/01
1/02
t
t
CAS RAS
07
V03
1/04
&
--.t.
CAS RAS
1/01
1/02
1/03
~4
15E
AO-Al00----.. 00-07
W!:o
.. 00-07
Vee a
~
.. 00-07
CO-C7
GNOO
T
.. 00-07
130
Remark DO - 07 : It P04217405
NEe
MC-424000F32
Electrical Specifications
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
V
Voltage on Any Pin Relative to GND
VT
-1.0 to +7.0
Supply Voltage
Vee
-1.0 to +7.0
V
Output Current
10
50
mA
Power Dissipation
Pc
8
W
Operating Ambient Temperature
TA
o to +70
·C
Storage Temperature
T.tg
-65 to +125
·C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated undar conditions outside the limits
described in the operational saetion of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device raliability.
Recommended Operating Conditions
Parameter
Symbol
Supply Voltage
Vee
Condition
MIN.
TYP.
MAX.
Unit
4.5
5.0
5.5
V
High Level Input Voltage
VIH
2.4
Vee +1.0
V
Low Level Input Voltage
VIL
-1.0
+0.8
V
Operating Ambient Temperature
TA
0
70
·C
MAX.
Unit
pF
Capacitance (Ta = 25 ·C, f = 1 MHz)
Parameter
Input Capacitance
Data Input/Output Capacitance
Symbol
Condition
MIN.
TYP.
0,
AO - A10
68
CI2
WE
76
03
RASO,RAS2
43
04
CASO-CAS3
29
Cvo
1/00 - 1/031
17
pF
131
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MC-424000F32
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Icc,
Test condition
RAS. CAS Cycling
tRC .. tRcIMIN.)
10=OmA
MIN.
MAX.
tRAc=60ns
880
tRAc=70ns
800
Unit
Notes
mA
1.2.3
RAS. CAS ~ VIH IMIN.). 10 .. 0 mA
16
Standby current
Icc2
mA
RAS. CAS ~ Vcc - 0.2 V. 10 .. 0 mA
8
RAS Cycling
RAS only refresh current
Icc3
CAS ~ VIH IMIN.)
tAc = tRC IMIN.)
10= OmA
RAS :Ii VIL 1MAX.)
Operating current
(Hyper page model
Icc4
CAS Cycling
tHPC = tHPC IMIN.)
10=OmA
RAS Cycling
CAS before RAS
refresh current
Iccs
tRC '" tRC IMIN.)
10 .. OmA
tRAc=60ns
880
tRAc=70 ns
800
tRAc-60ns
720
tRAc .. 70 ns
640
tRAc .. 60 ns
880
tRAc=70ns
800
mA
1.2.3,4
mA
1.2.6
mA
1.2
Input leakage current
IIIU
VI .. Oto 6.5 V
all other pins not under test .. 0 V
-10
+10
IAA
Output leakage current
lOlL)
Vo = Oto 5.5 V
Output is disabled (Hi·Z)
-10
+10
pA
High level outputvoltageLolII
VOH
10 =-2.6 mA
level output voltage
VOL
10=+2.1 mA
2A
V
0.4
V
Notes 1. Icc" ICCl, Icc4. Iccs depend on cycle rates (tAc and tHPC).
2.
Specified values are obtained with outputs unloaded.
3. Icc, and IcCl are measured assuming that address can be changed once or less during RAS
VILlMAX.) and CAS i: VIHIMIN.).
4. Icc3 is measured assuming that all column address inputs are held at either high or low.
S.
Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page cycle.
132
=-
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MC-424000F32
AC Characteristics (Rocommended Operating Conditions unless otherwise noted)
AC Charactlllriotiw Tctst Conditiono
(1) Input timing specification
VIH IMIN.I =
VIL IMAX.I
2.4
(2) Output timing specification
V ---------------
=0.8 V·------------
•
VOH IMIN.I =
•
(3) Loading conditions are 100 pF
2.4
VOL IMAX.I = 0.4
V------_-::_-_-_-J. . ______\-----.
I
V------------\
+ 2 TTLs.
Common to Read, Writo Cycle
Parameter
Read I Write Cycle Time
tRAC = 60 ns
tRAc
=70 ns
MIN.
MAX.
MIN.
MAX.
tRI;
104
-
124
-
Symbol
Unit Notos
ns
RAS Precharge Time
tRP
40
CAS Precharge Time
tCPN
10
RAS Pulse Width
tRAS
60
10000
70
10000
ns
12
10000
ns
50
10
ns
ns
CAS Pulse Width
tCAS
10
10000
RAS Hold Time
tRSH
10
-
12
CAS Hold Time
tcsH
40
-
60
-
RAS to CAS Delay Time
tRco
14
45
14
62
ns
RAS to Column Address Delay Time
tRAD
12
30
12
36
ns
1
CAS to it6:S Precharge Time
tCRP
6
2
lAsR
0
0
-
ns
Row Address Setup Time
Row Address Hold Time
tRAH
10
10
-
ns
Column Address Setup Time
lAsc
0
-
6
0
-
ns
12
-
ns
ns
ns
ns
Column Address Hold Time
tCAH
10
CAS to Data Setup Time
tCLl
0
-
0
-
ns
Transition Time (Rise and Fall)
tT
1
50
1
50
ns
Refresh Time
tREF
16
-
16
ms
-
1
133
NEe
Not.s
MC-424000F32
1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD S tRAD IMAX.} and tRcD S tRCD (MAX.)
tRAC IMAX.}
tRAC (MAX.)
tRAD> tRAD (MAX.) and tRCD S tRCD IMAX.}
tAAIMAX.}
tRAD + tAA IMAX.}
tRCD > tRCD IMAX.}
tCAC (MAX.)
tRCD + tCAC IMAX.}
tRAD(MAX.} and tRCDIMAX.} are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD
!it tRAD(MAX.} and tRCD
~
tRCDIMAX.} will not cause any operation problems.
2. tCRPIMIN.} requirement is applied to RAS, CAS cycles.
Read Cycle
Parameter
Svmbol
tRAc = 60 ns
MIN.
tRAC
=70 ns
Unit Notes
MAX.
MIN.
MAX.
70
ns
18
ns
Access Time from RAS
tRAC
-
60
Access Time from CAS
tCAC
15
Access Time from Column Address
tAA
-
-
30
-
35
ns
Column Address Lead Time Referenced to RAS
tRAL
30
35
tRCS
0
Read Command Hold Time Referenced to RAS
tRRH
0
0
Read Command Hold Time Referenced to CAS
tRCH
0
-
-
ns
Read Command Setup Time
-
Not..
0
0
,
,
,
ns
ns
2
ns
2
1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD:2 tRAD IMAX.} and tRcD:2 tRCD 1MAX.}
tRAC IMAX.}
tRAC 1MAX.}
tRAD> tRAD 1MAX.} and tRcD:5! tRCD IMAX.}
tAA(MAX.}
tRAD + tAA IMAX.}
tRCD > tRCD 1MAX.}
tCAC IMAX.}
tRCO + teAc 1MAX.)
tRAD(MAX.) and tRCDIMAX.} are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAc, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAO ~ tRAD(MAX.) and tRCD
tRCD(MAX.) will not cause any operation problems.
2.
134
Either tRCHIMIN.} or tRRHIMIN.) should be met in read cycles.
E=
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MC-424000F32
Write Cycle
Parameter
Symbol
tRAC
MIN.
=60 ns
MAX.
tRAC
=70 ns
MIN.
MAX.
Unit Notes
WE Hold Time Referenced to ~
twCH
10
-
10
-
ns
WE Setup Time
twcs
0
-
ns
1
tos
0
0
-
ns
2
Data-in Hold Time
tOH
10
-
0
Data-in Setup Time
10
-
ns
2
Not.. 1. If twcs 5; tWCS(MIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
2. tOS(MIN.1 and tOH(MIN.1 are referenced to the CAS falling edge in early write cycles.
135
NEe
MC-424000F32
Hyper Page Mode
Symbol
Parameter
tRAC = 60 ns
MIN. MAX.
tRAC = 70 ns
MIN. MAX. Unit Notes
Read I Write Cycle Time
tHPC
25
-
30
~
Pulse Width
tRASP
60
125000
70
125000 ns
~
Pulse Width
tHCAS
10
10000
12
10000
ns
~
Precharge Time
tcp
10
-
10
-
ns
tAcp
-
35
-
40
ns
40
-
ns
5
-
ns
Access Time from CAS Procharge
RAS Hold Time from CAS Precharge
tRHCP
35
-
Data Output Hold Time
tOHC
5
-
-
ns
1
Output Buffer Turn-off Delay from WE
twEz
0
13
0
15
ns
WE Pulse Width
twPz
10
-
10
-
ns
3
Output Buffer Turn-off Delay from RAS
tOFR
0
13
0
15
ns
2.3
Output Buffer Turn-off Delay from CAS
tOFC
0
13
0
15
ns
2.3
Notes 1.
2,3
tHPC(MIN.) is applied to access time from CAS
2.
tOFC(MAl<.), tOFR(MAl<.) and twEZ(MAX.) define the time when the output achieves 'the condition of Hi-Z and
3.
To make 1I0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE as follows. The
is not referenced to VOH or VOL.
-- - - -
effective specification depends on state of each signal~
(1) Both RAS and CAS are Inactive (at the end of read cycle)
WE : inactive
tOFC is effective when RAS is inactivated before CAS is inactivated.
------(2) Both RAS and CAS are inactive or RAS is active and CAS is inactive(at the end of read cycle)
tOFR is effective when CAS is inactivated before RAS is inactivated.
WE: active and either tRRH or tRCH must be met.. • twEz and twPz is effective.
Refresh Cycle
tRAC
Parameter
Symbol
tRAC
=70 ns
Unit
MIN.
MAX.
MIN.
MAX.
tCSR
5
-
ns
10
10
-
ns
tRPC
5
5
twHR
15
WE Setup Time
twsR
10
-
ns
WE Hold Time
-
5
tCHR
~SetupTime
CAS Hold Time (~ before
m
136
=60 ns
m
Precharge ~ Hold Time
Refreshl
15
10
ns
ns
Note
Timing Chart
Please refer to Timing Chart 4, page 397.
137
NEe
MC-424000F32
Package Drawings
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
B
R~-+------------------------------------------~
(!l.-----t--t!!l:S
00000000'
o
c
E
o
o
detail of ® part
W
~llx
0>
MIWMETERS
107.95:lO.13
INCHES
4.250:lO.008
B
101.19:lO.13
3.984j:~
c
M
N
P
44.45
6.35
44.45
10.16
1.27 (T.P.)
6.35
2.03
6.35
25.4
5.06 MAX.
R1.57
1.750
0.250
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.000
0.200 MAX.
RO.062
R
3.38:lO.13
0.133j:882
S
,3.18
,0.125
T
1.27+0·1
~.06
O.050:lO.lI04
U
V
W
X
5.5 MIN.
0.25 MAX.
1.04:lO.OS
2.54 MIN.
0.216 MIN.
0.010 MAX.
0.041 :lO.OO2
0.100 MIN.
ITEM
A
0
E
G
H
I
J
K
M728-50A54
138
PRELIMINARY DATA SHEET
CMOS iNTEGRATED CIRCUIT
.!EC/
MC-428000F32
8 M·WORD BY 32·BIT DYNAMIC RAM MODULE
HYPER PAGIE MODIE (IEIOO)
Description
The MC-428000F32 is a 8,388,608 words by 32 bits dynamic RAM module on which 16 pieces of
16M DRAM: IlPD4217405 are assembied.
These modules provide hige density and large quantities of memory in a small space without utilizing
the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
o Hyper page mode (EDO)
o 8,388,608 words by 32 bits organization
o Fast access and cycle time
Family
Access time
R/W cycle time
Hyper page mode
(MAX.)
(MIN.)
cycle time (MIN.)
Power consumption
(MAX.)
Active
Standby
MC-428000F32-60
60 ns
104 ns
26 ns
6,170mW
88mW
MC-428000F32-70
70 ns
124 ns
30 n8
4,730mW
(CMOS level input)
o 2,048 refresh cycle I 32ms
o CAS before RAS refresh, RAS only refresh, Hidden refresh
o 72-pin single in-line memory module (Pin pitch .. 1.27 mm)
o Single +5.0 V ±0.5 V power supply
4) Access time can be distinguished with characteristics of PO-pins (PDO to PD3)
;34EJ1VODSOO (Japan)
Tho Infonnatlon En thlo document 1:1 ouIIJact to chenga without notice.
139
NEe
MC-428000F32
Ordering Information
Part number
140
Access time
(MAX.)
Package
MC-428000F32B-60
60 ns
72-pin Single In-line Memory Module (Socket Type)
MC-428000F32B-70
70 ns
Edge connector: Solder coatlng(HALI
MC-428000F32F-60
60 ns
72-pln Single In-line Memory Module (Socket Type)
MC-428000F32F-70
70 ns
Edge connector: Gold plating
Mounted devices
16 pieces of /l PD4217405LA
(300mil SOJ)
(Single side]
NEe
MC-428000F32
Pin Configuration
72-pin Single In-line Memory Module Socket Type (Edge connector: Solder coating, Gold plating)
GND
VOO
V016
VOl
1/017
1/02
V018
V03
1/019
Vee
NC
AO
Al
A2
A3
A4
A5
A6
Al0
V04
V020
V05
1/021
V06
V022
V07
V023
A7
NC
Vee
A8
A9
RAS3
RAS2
NC
NC
NC
NC
...GtID
~
CA 2
em
CAS.!
BAS.ll
RASI
J>K;
WE
NC
V08
V024
V09
V025
V010
V026
V011
V027
V012
V028
Vee
V029
V013
V030
V014
V031
V015
NC
PDO
PDl
PD2
PD3
NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
o
37
38
39
40
41
42
43
44
45
46
AO·A1D
: Address Inputs
1/00-1/031
: Data Inputs/Outputs
CASO-CAS3
: Column Address Strobe
RASD·RAS3
: Row Address Strobe,
'WE
47
48
49
50
51
52
53
: Write Enable
Vee
: Power Supply
GND
: Ground
NC
: No connection
The internal connection of PO pins (POD to PD3)
54
55
56
57
58
59
60
61
62
63
depends on access times.
Pin
Name
Pin
No.
Access Time
SOns
'Ons
64
PDO
~
NC
NC
66
POI
68
GNO
GNO
65
67
68
69
70
71
72
o
P02
68
NC
GNO
PD3
70
NC
NC
141
NEe
MC-428000F32
Block Diagram
RASOo------------,
CASOo---------~--r-----------_,
VOO
CAS RAS
V01
V02
V03
DO
V04
V05
V06
V07
D1
CAS1
CAS RAS
Remark 00-015: 1E'04217405
1---1
1---1
o---------~~~----------_.
V08
V09
V010
CAS RAS
D10
Vo"
CAS RAS
V012
V013
D11
VO'4
V015
RAS2o------------,
CAS2o-------~~~----------~
V016
V017
V018
V019
V020
V021
V022
V023
CAS RAS
D4
CAS RAS
OS
1---1
1---1
.---oRAS3
CAS RAS
D12
CAS RAS
D13
CAS3O---------~-+----------__,
V024
V025
V026
CAS RAS
D6
1---1
V027
V028
V029
V030
V031
AO-A100-----..... 00-015
~O
.. 00-015
Vee 0
:t
• 00-015
CO-C15
GNO 0
T
• 00-015
142
CAS RAS
D14
CAS RAS
D15
NEe
MC-428000F32
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on Any Pin Relative to GND
VT
-1.0 to +7.0
V
Supply Voltage
Vee
-1.0 to +7.0
V
Output Current
10
50
mA
16
W
Power Dissipation
Po
Operating Ambient Temperature
TA
oto +70
·C
Storage Temperature
T.tg
-55 to +125
·C
Caution
Exposing the device to st.... above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational uaction of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
5.0
MAX.
Unit
Supply Voltage
Vee
4.5
5.5
V
High Level Input Voltage
VIH
2.4
Vee +1.0
V
Low Level Input Voltage
VIL
-1.0
+0.8
V
Operating Ambient Temperature
TA
0
70
·C
Capacitance (Ta = 25 ·C, f = 1 MHz)
Parameter
Input Capacitance
Data Input/Output Capacitance
Symbol
Condition
MIN.
TYP.
MAX.
Unit
CII
AO - Al0
121
pF
CI2
WE
137
CI3
RASO·RAS3
48
CI4
CASO - CAS3
48
evo
1/00 - V031
29
pF
143
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MC-428000F32
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
IccI
Test condition
RAS. CAS Cycling
tRC = tRcIMIN.1
10=OmA
MIN.
tRAc=60 ns
MAX.
Unit
Notes
mA
1.2.3
940
860
tRAc=70ns
RAS. CAS ~ VIH IMIN.I. 10 = 0 mA
32
Standby current
Icc2
mA
RAS. CAS ~ Vcc - 0.2 V. 10 = 0 mA
RAS only refresh current
IcC3
RASCyciing
CAS ~ VIH IMIN.I
tAc = tRC IMIN.I
10= 0 mA
RAS ~ VIL IMAX.I
Operating current
(Hyper page model
CAS before RAS
refresh current
Icc4
CAS Cycling
tHPC = tHPC IMIN.I
10 = 0 rnA
RAS Cycling
Iccs
Input leakage current
II ILl
Output leakage current
IOILI
tRC = tRC IMIN.I
10= OmA
16
tRAc=60ns
940
tRAc=70ns
860
tRAc=60 ns
780
tRAc=70ns
700
tRAc=60 ns
940
tRAc=70ns
860
VI=Ot05.5V
all other pins not under test =0 V
Vo. Oto 5.5 V
VOH
10 =-2.5 mA
level output voltage
VOL
10 = +2.1 mA
1.2.3,4
mA
1.2..5
mA
1.2
-10
+10
IlA
-10
+10
IlA
Output is disabled (Hi-Z)
High level outputvoltn[JoLoIIII
mA
2A
V
OA
V
Notes 1. ICCI, Icc3. Icc4, Ices depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3.
IccI and IcC3 are measured assuming that address can be changed once or less during RAS ;1!
VIL(MAltI and CAS ~ VIH(MIN.I.
4.
Icc3 is measured assuming that all column address inputs are held at either high or low.
S.
Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page cycle.
144
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MC-428000F32
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
(2) Output timing specification
VIH IMIN.) =
2.4 V
---------______
Vil IMAX.) =
0.8 V
_____________
I
VOH IMIN.) =
I
VOL IMAX.)
:
~,
2.4
V--------:--.-:.-t. .___---J\ .. __..
I
= 0.4 V------------\.
tr= 2 ns
(3) Loading conditions are 100 pF + 2 TTLs.
Common to Read, Writo Cycle
Parameter
Symbol
tAAC = 60 ns
tRAc
=70 ns
MIN.
MAX.
MIN.
MAX.
-
124
-
Unit Notes
Read I Write Cycle Time
tAC
104
RAS Precharge Time
tAl'
40
~ Precharge Time
tCI'N
10
'RAS Pulse Width
tRAS
CAS Pulse Width
tCAS
RAS Hold Time
tRSH
10
-
12
-
-
50
-
ns
1
ns
ns
60
-
10
-
60
10000
70
10000
ns
10
10000
12
10000
ns
ns
ns
CAS Hold Time
tCSH
40
RAS to CAS Delay Time
tRCD
14
45
14
62
ns
RAS to Column Address Delay Time
tRAD
12
30
12
36
ns
1
~ to ~ Precharge Time
tCRP
6
-
6
-
ns
2
Row Address Setup Time
lAsR
0
tRAH
10
10
-
ns
Row Address Hold Time
-
0
Column Address Setup Time
lAsc
0
Column Address Hold Time
tCAH
10
CAS to Data Setup Time
tCLZ
Transition Time (Rise and Fall)
tT
Refresh Time
tREF
ns
-
0
-
ns
12
ns
0
-
0
-
1
60
1
60
ns
16
-
16
ms
-
ns
145
NEe
Notes
MC-428000F32
1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD S tRAD IMAX.) and tRcD;a tRCD IMAX.)
tRAC IMAX.)
tRAC IMAX.)
tRAD> tRAD IMAX.) and tRCD S tRCD IMAX.I
tAAIMAX.)
tRAD + tAA IMAX.I
tRCD > tRCD IMAX.I
tCAC IMAX.I
tRCD + tCAC IMAX.I
tRADIMAX.1 and tRCDIMAX.1 are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAc, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD
IE: tRAOlMAX.1 and tRCD IE:
tRCDIMAX.1 will not cause any operation problems.
----
2. tCRPIMIN.1 requirement is applied to RAS, CAS cycles.
Read Cycle
Svmbol
Parameter
tRAC" 60 ns
tRAC
=70 ns
MIN.
MAX.
MIN.
MAX.
Unit Notes
Access Time from RAS
tRAc
-
60
-
70
ns
1
Access Time from CAS
tCAC
-
18
ns
1
Access Time from Column Address
tAA
-
15
30
-
35
ns
1
Column Address lead Timo Roferenced to RAS
tRAL
30
-
35
tRCS
0
-
0
Read Command Hold TIme Referenced to RAS
tRRH
0
-
0
-
ns
Read Command Setup Time
ns
2
Read Command Hold Time Referenced to CAS
tRCH
0
-
0
-
ns
2
ns
Notes 1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD;a tRAD IMAX.I and tRcD;a tRCD 1MAX.1
tRAC 1MAX.1
tRAC IMAX.I
tRAD> tRAD IMAX.1 and tRcD;a tRcD 1MAX.1
tAAIMAX.1
tRAD + tAA IMAX.1
tRCD > tRCD IMAX.)
tCAC IMAX.I
tRCD + tCAC IMAX.I
tRADIMAX.1 and tRCDIMAX.1 are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD
tRCDIMAX.) will not cause any operation problems.
2.
146
Either tRCHIMIN.1 or tRRHIMIN.1 should be met in read cycles.
IE: tRADIMAX.1 and tRCD
~
NEe
MC-428000F32
Write Cycle
Parameter
tRAC
=70 ns
MIN.
MAX.
MIN.
MAX.
tRAC
Symbol
=60 ns
Un,t Notes
WE Hold Time Referenced to ~
twCH
10
-
10
-
ns
WE Setup Time
twcs
0
0
1
tos
0
ns
2
Data-in Hold Time
tOH
10
-
10
-
ns
Data-in Setup Time
-
ns
2
Not.. 1. If twcs
0
s= twcsIMIN.I. the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
2. tOSIMIN.I and tDHIMIN.I are referenced to the CAS falling edge in early write cycles.
147
NEe
MC-428000F32
Hyper Page Mode
Parameter
Symbol
tRAC" 60 ns
MIN. MAX.
tRAC =70 ns
MIN. MAX. Unit Notes
Read I Write Cycle Tima
tHPC
25
-
30
-
~
Pulse Width
tRASP
60
125000
70
125000
ns
CAS Pulse Width
tHCAS
10
10000
12
10000
ns
CAS Pracharge Time
tcp
10
-
10
-
ns
Access Time from ~ Precharge
tAcp
-
35
-
40
ns
ns
ns
1
RAS Hold Time from CAS Precharge
tRHCP
35
-
40
Data Output Hold Time
tDHC
5
-
5
-
Output Buffer Turn-off Delay from WE
twEz
0
13
0
15
ns
3
ns
2.3
WE Pulse Width
twPz
10
-
10
-
ns
Output Buffer Turn-off Delay from RAS
tOFR
0
13
0
15
ns
2.3
Output Buffer Turn-off Deley from CAS
tOFc
0
13
0
15
ns
2.3
Not•• 1.
tHPCIMIN.) is applied to access time from CAS
2.
tOFCIMAX.I, tOFRIMAX.) and twEZIMAX.1 define the time when the output achieves the condition of Hi-Z and
3.
To mal(e I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE as follows. The
is not referenced to VOH or VOL.
-- - - -
effective specification depends on state of each signal.
(1) Both RAS and CAS are Inactivo (at the end of read cycle)
WE : inactive
tOFC is effective when RAS is inactivated before CAS is inactivated.
----------(2) Both RAS and CAS are inactive or RAS is active and CAS is inactive(at the end of read cycle)
--
tOFR is effective when CAS is inactivated before RAS is inactivated.
WE : active and either tRRH or tRCH must be met.. • twEz and twPz is effective.-
Refresh Cycle
Parameter
~SetupTime
CAS Hold Time (~ before
148
tRAC" 60 ns
tRAC" 70 ns
MIN.
MAX.
MIN.
MAX.
tcsR
5
1&
-
ns
10
-
&
tCHR
10
-
ns
Symbol
W Refresh)
RA§ Precharge ~ Hold Time
tRPC
&
WE Hold Time
twHR
1&
WE Setup Time
twsR
10
10
&
Unit
ns
ns
ns
Note
Timing Chart
Please refer to Timing Chart 4, page 397.
149
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MC-428000F32
Package Drawings
72 PIN SINGLE IN-LINE MODULE (SOCKET TYPE)
A
B
R~-+--------------------------------------------~
S
.--------t-N
00000000'
o
c
E
ITEM
detail of
® part
.x
W
0
MILUMETERS
107.95:lO.13
INCHES
4.250:l0.006
B
101.19:lO.13
3.984 ..0.005
-0.006
C
J
K
M
N
P
44.45
6.35
44.45
10.16
1.27 (T.P.)
6.35
2.03
6.35
25.4
9.0 MAX.
R157
1.750
0.250
1.750
0.400
0.050 (T.P.)
0.250
0.080
0.250
1.000
0.355 MAX.
RO.062
R
3.38:lO.13
0.133~:~
s
;3.18
;0.125
T
1.27~:Ja
0.050:l0.DD4
u
55 MIN.
0.25 MAX.
1.04:lO.05
2.54 MIN.
0.216 MIN.
0.010 MAl<.
0.041:lO.002
0.100 MIN.
M72B-&OA&i
A
0
E
G
H
>
V
W
X
150
N
Small Outline DIMM
151
DATA SHEET
~EC
MOS INTEGRATED CIRCUIT
MC-42S1000LAD32S SERIES
1 M-WORD BY 32-BIT DYNAMIC RAM MODULE (SO DIMM)
FAST PAGE MODE
Description
The MC-42S1000LAD32S series is a 1,048,576 words by 32 bits dynamic RAM module (Small Outline DIMM)
on which 2 pieces of 16 M DRAM: IlPD42S18160L are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• CAS before RAS self refresh, CAS before RAS refresh, RAS only refresh, Hidden refresh
•
1,048,576 words by 32 bits organization
• Fast access and cycle time
Access time
(MAX.)
Family
Power consumption
(MAX.)
R/W cycle time
(MIN.)
Active
•
MC-42S 1000LAD32S-A60
60 ns
110 ns
MC-42S 1000LAD32S-A70
70 ns
130 ns
MC-42S 1000LAD32S-A80
80 ns
150 ns
:-3449 (Japan)
1,080 mW
1,008 mW
---
1.08 mW
(CMOS level input)
936 mW
1,024 refresh cycles/128 ms
• 72-pin dual in-line memory module (Pin pitch
•
Standby
= 1.27 mm)
Single +3.3 V ±0.3 V power supply
The information in this document Is subject to change without notice.
153
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MC-42S1000LAD32S SERIES
Ordering Information
Part number
154
Access time
(MAX.)
MC-4251000LAD32SA-A60
60 ns
MC-4251000LAD32SA-A70
70 ns
MC-4251000LAD32SA-A80
80 ns
Package
72-pin Dua) In-line Memory Module
(Socket Type)
Edge connector: Gold plating
Mounted devices
2 pieces of IlPD42S18160LG5
(400 mil TSOP (II))
[Single side]
NEe
MC-42S1000lAD32S SERIES
Pin Configuration
72-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
:s:
c;>
~
(I)
~
0
0
0
S;
C
Col)
N
CJ)
»
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1/00
1/02
1/04
1/06
Vee
AO
A2
A4
A6
NC
1/09
1/011
1/013
A7
Vee
A9
RAS2
NC
1/017
CASO
CAS3
RASO
NC
NC
1/019
1/021
1/023
1/024
1/026
1/027
1/029
1/031
PD2
PD4
PD6
GND
GND
1/01
1/03
1/05
1/07
PDl
Al
A3
A5
NC
1/08
1/010
1/012
1/014
NC
A8
NC
1/015
1/016
GND
CAS2
CASl
NC
WE
1/018
1/020
1/022
NC
1/025
1/028
Vee
1/030
NC
PD3
PD5
PD7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
~
(I)
N
CO)
C
:50
0
0
...
(I)
~I
CJ
:E
The internal connection of PO pins (P01 to P07).
AD - A9
Address Inputs
1/00 - 1/031
Oata Inputs/Outputs
RASO, RAS2
Row Address Strobe
CASO - CAS3
Column Address Strobe
WE
Write Enable
PD1
11
NC
NC
NC
PD1 - PD7
Presence Detect Pins
PD2
66
GND
GND
GND
Vee
Power Supply
PD3
67
GND
GND
GND
GND
Ground
PD4
68
NC
NC
NC
NC
No connection
PD5
69
NC
GND
NC
PD6
70
NC
NC
GND
PD7
71
GND
GND
GND
Pin
Name
Pin
No.
Access Time
60 ns
70 ns
80 ns
155
NEe
MC-42S1000LAD32S SERIES
Block Diagram
Remark DO, 01 :
WE
RASO
CASl
CASO
~
1
LCAS UCAS RAS
1/00
1/01 01/02 ~
1/03
1/04
1/05
1/06
1/07
1/08
1/09
1/010
1/011
1/012
1/013
1/014
1/015
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
1/09
1/010
1/011
1/012
1/013
1/014
1/015
1/016
DO
OEI].
1
j
LCAS UCAS RAS
1/016
1/017
1/018
1/019
1/020
1/021
1/022
1/023
1/024
1/025
1/026
1/027
1/028
1/029
1/030
1/031
~
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
1/09
1/010
1/011
1/012
1/013
1/014
1/015
1/016
AO-A9
156
WE
WE
01
OEI].
0------- 00.01
Vee o--~t-----. 00.01
CO. Cl
GNOo---~---. 00.01
:r:
~PD42S18160L
(TSOP (II))
NEe
MC·42S1000LAD32S SERIES
Electrical Specifications
Notes 1. 2
Absolute Maximum Ratings
Rating
Unit
Voltage on any pin relative to GND
Parameter
Symbol
VT
Condition
-0.5 to +4.6
V
Supply voltage
Vee
-0.5 to +4.6
V
Output current
10
20
mA
Power dissipation
Po
2
W
Operating ambient temperature
TA
o to +70
'C
Til.
-55 to +125
'C
Storage temperature
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
3.3
3.6
V
V
Supply voltage
Vee
3.0
High level input voltage
VIH
2.0
Vee + 0.3
Low level input voltage
VIL
-0.3
+0.8
V
Operating ambient temperature
TA
0
70
'C
MAX.
Unit
Capacitance ITA
= 25 ·C. f = 1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
Test Condition
Symbol
MIN.
TYP.
Cn
AO-A9
29
CI2
WE
29
CI3
RASO.RAS2
23
CI4
CASO - CAS3
17
CliO
1/00 -1/031
12
pF
pF
157
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MC-42S1000LAD32S SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
IcCl
Test condition
RAS only refresh current
Operating current
Icc,
Icc3
Icc.
. (Fast page modo)
RAS, CAS Cycling
tRAC = 60 ns
300
tRA!: = 70 ns
280
tRAC = 80 ns
260
10= 0 mA
1.0
RAS, CAS ~ Vcc - 0.2 V
10 = 0 mA
0.3
RAS Cycling
CAS ~ V,H (MIN.I
tRC = tRC (MIN.I
10 = 0 mA
tRAC = 60 ns
300
tRAC = 70 ns
280
tRAC = 80 ns
260
RAS S V,l (MAX.), CAS Cycling
tRAC = 60 ns
180
tpc = tpc (MIN.I
tRAC = 70 ns
160
tRAC = 80 ns
140
RAS Cycling
tRAC = 60 ns
300
tRC = tRC (MIN.I
tRAC = 70 ns
280
tRAC = 80 ns
260
tRAS:> 1 JlS
RAS, CAS
~
V,H (MIN.I
Icc5
rafrosh currant
CAS before RAS
Icco
Notes
mA
3,4,7
mA
3,4,5,7
mA
3,4,6
mA
3,4
360
pA
3, 4
300
pA
4
-5
+5
pA
Output is disabled (Hi-ZI
-5
+5
pA
2.4
10 = 0 mA
long refresh current
Unit
mA
10 = 0 mA
CAS beforo RAS
MAX.
tRC = tRC (MIN.I
10 = 0 mA
Standby current
MIN.
CAS before RAS refresh:
tnc =125.0 lIS
---RAS, CAS:
Vcc -0.2 V :> VIII:> V,H IMAX.I
o V ~ VIL:> 0.2 V
Standby:
----
RAS, CAS ~ Vcc -0.2 V
Address: VIII or V,l
WE:V,H
10= 0 mA
CAS before RAS
ICCl
salf refresh current
RAS, CAS:
tRASS = 5 ms
Vcc -0.2 V s V,H S V,H (MAltI
o V :> Vil :> 0.2 V
10=OmA
Input leakage current
h(ll
V, = 0 to 3.6 V
All other pins not under test = 0 V
Output leakage current
158
10 III
Va = 0 to 3.6 V
High level output voltage
VOH
10 - -2.0 mA
Low level output voltage
Val
10 = +2.0 mA
V
0.4
V
NEe
MC-42S1000LAD32S SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
Symbol
tRAC = 60 ns
MIN.
MAX.
tRAC = 70 ns
MIN.
MAX.
tRAC = 80 ns
MIN.
Unit
Notes
MAX.
Read/Write Cycle Time
tRC
110
130
150
Fast Page Mode Cycle Time
tpc
40
45
50
Access Time from RAS
tRAC
60
70
80
ns
10, 11
Access Time from CAS
tCAC
15
20
20
ns
10, 11
Access Time Column Address
tAA
30
35
40
ns
10,11
Access Time from CAS Precharge
tACP
35
40
45
ns
11
RAS to Column Address Delay Time
tRAO
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
Output Buffer Turn-off Delay Time from CAS
tOFF
30
15
0
13
50
ns
ns
35
17
0
15
0
15
3
50
3
50
0
0
ns
11
ns
12
Transition Time (Rise and Fall)
tT
3
RAS Precharge Time
hp
40
RAS Pulse Width
hAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
tRSH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tRCO
20
ns
10
CAS to RAS Precharge Time
tCRP
5
5
5
ns
13
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
35
40
45
ns
Row Address Setup Time
tASR
0
0
0
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
tCAH
15
15
15
ns
Column Address Hold Time
50
60
18
10,000
20
20
10,000
70
45
20
20
ns
10,000
80
50
25
ns
ns
ns
ns
60
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twCH
10
10
15
ns
15
Data-in Setup Time
tos
0
0
0
ns
16
Data-in Hold Time
tOH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tCSR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
ns
RAS Pulse Width (CAS before RAS Self Refresh)
tRASS
100
100
100
JJS
RAS Precharge Time (CAS before RAS Self Refresh)
tRPS
110
130
150
ns
CAS Hold Time (CAS before RAS Self Refresh)
tCHS
-50
-50
-50
ns
WE Hold Time
twHR
15
Refresh Time
tREF
15
128
15
128
ns
128
ms
159
NEe
MC-42S 1OOOLAD32S SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3.
4.
5.
6.
icC', Icc3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tpc).
Specified values are obtained with outputs unloaded.
Icc3 is measured assuming that all column address inputs are held at either high or low.
Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. Icc, and Icc3 are measured assuming that address can be changed once or less during RAS $ VIL
(MAX.I and CAS
~
VIH (MIN.).
8. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H 1M IN I
=2.0 V .----------~-----1
1
V,l IMAlO
=0.8 V
______________
t
I
I
,
,
I
,
,
I
I
I
I
.
I
I
I
-~
IT = 5 ns
I
I
I
:.
tT=5ns
(2) Output timing specification
VOH IMIN.)
=2.0 V
VOllMAXI
=O.B V
10. For read cycles, access time is defined as follows:
Input Conditions
tnAD ~ tRAD IMAX.) and tACO S tACO IMAX.)
tRAD IMAX.) and tRCD ~ tACO IMAX.)
lRAD
>
tACO
> tRCD IMAX.)
Access Time
Access Time from ~
tRACIMAX.)
tRACIMAX.)
tAAIMAX.)
IRAD
+
tCACIMAX.)
tRCD
+ tCAC IMAX.)
lAA IMAX.)
tRAO (MAX.) and tRCO (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tM or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAO ~ tRAO (MAX.)
and tRCO ~ tRCO (MAX.) will not cause any operation problems.
11. Loading conditions are 1 TIL and 100 pF.
12. tOFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13. tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
14. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
15. In early write cycles, twCH (MIN.) should be met.
16. tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles.
17. Iftwcs ~ twCS(MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
160
Timing Chart
Please refer to Timing Chart 5, page 409.
161
NEe
MC-42S1000LAD32S SERIES
Package Drawing
72 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A
N
z
lo::
®
P
c
o
detail of ® part
W
.x
[]]>
ITEM
MILLIMETERS
INCHES
A
Q
59.69±0.13
44.45
8.255
1.27 (T.P.)
7.62
2.0
3.18
17.78
25.4
2.45 MAX.
R2.0
R2.0
2.35±0.006
1.750
0.325
0.050 (T.P.)
0.300
0.079
0.125
0.700
1.000
0.097 MAX.
RO.079
RO.079
R
4.0±0.1
s
;1.8
0.157:8:88i
;0.071
C
F
H
J
K
L
M
N
P
T
1.0±0.1
0.039:8:88i
u
3.18 MIN.
0.25 MAX.
0.125 MIN.
0.010 MAX.
V
W
1.0±0.05
0.039:8:88~
X
2.54 MIN.
2.0 MIN.
2.0 MIN.
0.100 MIN.
0.078 MIN.
0.078 MIN.
Y
Z
M72S-50A4
162
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC-42S2000LAB32S SERIES
2 M-WORD BY 32-BIT DYNAMIC RAM MODULE (SO DIMM)
FAST PAGE MODE
Description
The MC-42S2000LAB32S series is a 2,097,152 words by 32 bits dynamic RAM module (Small Outline DIMM)
on which 4 pieces of 16 M DRAM: ttPD42S17800L are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• CAS before RAS self refresh, CAS before RAS refresh, RAS only refresh, Hidden refresh
• 2,097,152 words by 32 bits organization
• Fast access and cycle time
Power consumption
(MAX.)
Family
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-42S2000LAB32S-A60
60 ns
110 ns
1,440 mW
MC-42S2000LAB32S-A70
70 ns
130 ns
1,296 mW
MC-42S2000LAB32S-A80
80 ns
150 ns
1,152 mW
Active
Standby
2.16 mW
(CMOS level input)
• 2,048 refresh cycles/128 ms
• 72-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Single +3.3 V ±0.3 V power supply
Ordering Information
Part number
Access time
(MAX.)
MC-42S2000LAB32SA-A60
60 ns
MC-42S2000LAB32SA-A70
70 ns
MC-42S2000LAB32SA-A80
80 ns
Mounted devices
Package
72-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
4 pieces of JLPD42S17800LG5
(400 mil TSOP (11)
[Single side)
The information in this document is subject to change without notice.
Ml0054EJ3VODSOO (Japan)
163
NEe
MC-42S2000LAB32S SERIES
Pin Configuration
72-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
s:
~
tUJ
N
Q
Q
Q
~
D:I
CAl
N
en
»
GND
Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Write Enable
Presence Detect Pins
Power Supply
Ground
NC
No connection
AO - A10
1/00 - 1/031
RASO. RAS2
CASO - CAS3
WE
PD1 - PD7
Vee
164
2
1/00
1/02
4
6
1/04
1/06
8
10
Vee
12
AO
14
A2
16
A4
A6
18
20
NC
22
1/09
24
1/011
26
1/013
28
A7
30
Vee
32
A9
34
RAS2
36
NC
1/017
38
40
CASO
42 --oCAS3
44 - - 0 RASO
46
NC
NC
48
50
1/019
52
1/021
54
1/023
1/024
56
1/026
58
60
1/027
62
11029
64
1/031
66
P02
68
P04
70
P06
72
GNO
GND
1/01
1/03
1/05
1/07
POl
Al
A3
A5
Al0
1/08
1/010
1/012
1/014
NC
A8
NC
1/015
1/016
GNO
CAS2
CASl
NC
WE
11018
11020
11022
NC
11025
11028
Vee
1/030
NC
P03
P05
P07
1
3
5
7
9
11
13
15
17
19
21
23'
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
ct
UJ
N
CO)
~
:3
Q
Q
Q
N
UJ
~
I
CJ
:E
The internal connection of PD pins (PD1 to PD7).
Access Time.
Pin
Name
Pin
No.
80 ns
11
60 ns
GNO
70 ns
POl
GNO
GNO
PD2
66
NC
NC
NC
P03
67
GND
GND
GND
PD4
68
NC
NC
NC
PD5
69
NC
GND
NC
PD6
70
NC
NC
GND
PD7
71
GND
GND
GND
NEe
MC-42S2000LAB32S SERIES
Block Diagram
,I ,I ,
1/00
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
1/08
1/09
1/010
1/011
1/012
1/013
1/014
1/015
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
00
OE,*
1
+
1/016
1/017
1/018
1/019
1/020
1/021
1/022
1/023
01
OE~
•1
02
OE,*
,
1/024
1/025
1/026
1/027
1/028
1/029
1/030
1/031
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
~
~
GNOO
1
CAS RAS WE
03
OEr---;;,.
.. 00-03
AO-Al00
Vee 0
Remark 00-03: ,uP042S17BOOLG5 (TSOP (11))
£
CO-C3
..
00-03
.
00-03
165
NEe
MC-42S2000LAB32S SERIES
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-0.5 to +4.6
V
Supply voltage
Vee
-0.5 to +4.6
V
Output current
10
20
mA
Power dissipation
Po
4
W
Operating ambient temperature
TA
o to +10
·C
Storage temperature
TSlg
-55 to +125
·C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parnmeter
Vee
High level input voltage
V,H
Low level input voltage
VIL
Operating ambient temperature
TA
Capacitance ITA
Condition
MIN.
TYP.
MAX.
Unit
3.0
3.3
3.6
V
2.0
Vee + 0.3
V
-0.3
+0.8
V
10
·C
MAX.
Unit
pF
0
= 25 ·C. f = 1 MHz)
Parameter
Input cnpncitnncc
Data Input/Output capacitance
166
Symbol
Supply voltage
Symbol
Test Condition
MIN.
TYP.
C"
AO - A10
35
C"
WE
43
C'l
RASO, RAS2
30
C"
CASO - CAS3
11
CliO
1/00 -1/031
12
pF
NEe
MC-42S2000LAB32S SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Standby current
Symbol
Iccl
Icc,
RAS only refresh current
Operating current
(Fast page mode)
CAS before RAS
Iccs
refresh current
CAS before RAS
long refresh current
Icc6
Test condition
MIN.
MAX.
Unit
Notes
mA
3,4,7
RAS, CAS Cycling
tRAC = 60 ns
400
tRC = tRC (M'N.'
10 = 0 mA
tRAC = 70 ns
360
tRAC = 80 ns
320
RAS, CAS
~
V'H (M'N.)
10 = 0 mA
2.0
RAS, CAS
~
Vcc - 0.2 V
10 = 0 mA
0.6
mA
RAS Cycling
CAS ~ V'H (M(N.'
tRC = tRC (M'N.)
10=OmA
tRAC = 60 ns
400
tRAC = 70 ns
360
tRAC = 80 ns
320
RAS S VIL (MAX.), CAS Cycling
tpc = tpc (M'N.)
10=OmA
tRAC = 60 ns
280
tRAC = 70 ns
240
tRAC = 80 ns
200
RAS Cycling
tRAC = 60 ns
400
tRC = tRC (M'N.)
10= 0 mA
tRAC = 70 ns
360
tRAC = 80 ns
320
CAS before RAS refresh:
tRAS S 1 JIS
800
3, 4
600
4
mA
3,4, S, 7
mA
3,4,6
mA
3, 4
tRC = 62.S JIS
RAS, CAS:
Vcc -0.2 V S V'H S V'H (MAX.)
o V S V'L S 0.2 V
Standby:
RAS, CAS
~
Vcc -0.2 V
Address: V'H or V'L
WE:V'H
10=OmA
CAS before RAS
self refresh current
RAS, CAS:
tRASS = S ms
Vcc -0.2 V S V'H S V'H (MAX.)
o V S V'L S 0.2 V
10= 0 mA
Input leakage current
I"u
V, = 0 to 3.6 V
All other pins not under test = 0 V
-S
+S
Output leakage current
10(L}
Vo = 0 to 3.6 V
Output is disabled (Hi-Z)
-S
+S
High level output voltage
VOH
10 =-2.0 mA
2.4
Low level output voltage
VOL
10 = +2.0 mA
V
0.4
V
167
NEe
MC-42S2000LAB32S SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Symbol
Parameter
= 60 ns
tRAC
= 70 ns
tRAC
MAX.
MIN.
MAX.
MIN.
= 80
ns
Unit
Notes
MAX.
Read/Write Cycle Time
tRC
110
130
150
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Access Time from RAS
tRAC
60
70
80
ns
10, 11
Access Time from CAS
tCAC
15
18
20
ns
10, 11
Access Time Column Address
tAA
30
35
40
ns
10, 11
Access Time from CAS Precharge
tACP
35
40
45
ns
11
RAS to Column Address Delay Time
tRAD
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
ns
11
12
30
15
35
0
17
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
13
0
15
0
15
ns
Transition Time (Rise and Fall)
tT
3
50
3
50
3
50
ns
RAS Precharge Time
tRP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RI\S Pulse Width (Fast Page Mode)
..
RI\S Hold Time
tRASP
60
125,000
70
125,000
80
125,000
ns
tRSH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tncD
20
ns
10
CAS to RAS Precharge Time
tCRP
5
5
5
ns
13
CAS Precharge Time
tcrN
10
10
10
ns
tcr
10
10
10
ns
-----
--
.-
... -
CAS Precharge Time (Fast Page Mode)
._.
50
60
18
10,000
18
20
10,000
70
45
20
ns
20
ns
10,000
80
50
25
ns
ns
60
tnrc
5
5
5
ns
tRHCP
35
40
45
ns
tASR
0
0
0
ns
Row Address Hold Time
tnAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twCH
10
10
15
ns
15
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tDH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tCSR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
ns
RAS Precharge CAS Hold Time
._-
RAS Hold Time from CAS Precharge
Row Address Setup Time
168
tRAC
MIN.
..
-_..
RAS Pulse Width (CAS before RAS Self Refresh)
tRASS
100
100
100
JlS
RAS Precharge Time (CAS before RAS Self Refresh)
tRPS
110
130
150
ns
CAS Hold Time (CAS before RAS Self Refresh)
tCHS
-50
-50
-50
ns
WE Setup Time
twSR
10
10
ns
WE Hold Time
tWHR
10
15
15
15
ns
Refresh Time
tREF
128
128
128
ms
NEe
MC-42S2000LAB32S SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. icc', Icc3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. Icc, and Icc3 are measured assuming that address can be changed once or less during RAS 5 VIL
(MAX.! and CAS
~
VIH IMIN.!.
8. AC measurements assume tr = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H
(MIN)
= 2.0 V
V,L (MAX ( = 0.8 V
----------~-----i
!
,I
______________
,I
,
,
: :
I
,
: :
I...
I
IT = 5 ns
I ..
IT = 5 ns
(2) Output timing specification
VOH
(MIN.(
= 2.0 V
VOL (MAX.) = 0.8 V
10. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD '" tRAD (MAX.) and tRCD '" tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
and
tAAIMAX.1
tRAO
+ tAA (MAX.I
tCAC (MAX.)
tRCD
+ tCAC (MAX.)
tAAO
> tRAD IMAX,I
tRCO ~ tRCD (MAX.,
tRCD > tRCD (MAX.)
tRAO (MAX.! and tRCO IMAX.! are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAD ~ tRAO (MAX.!
and tRCO
~
tRCO (MAX.! will not cause any operation problems.
11. Loading conditions are 1 TTL and 100 pF.
12. tOFF IMAX.! defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13.
14.
15.
16.
17.
tCRP (MIN.! requirements should be applied to RAS/CAS cycles.
Either tRCH (MIN.) or tRRH (MIN.) sh'ould be met in read cycles.
In early write cycles, twCH (MIN.) should be met.
tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles.
If twcs
~
twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
169
Timing Chart
Please refer to Timing Chart 6, page 419.
170
NEe
MC-42S2000LAB32S SERIES
Package Drawing
72PIN DUAL IN-LINE MODULE (SOCKET TYPE)
I--------A ---------1"
Q
S
(OPTIONAL HOLES)
K
P
~~----c-----~
ITEM
MILLIMETERS
A
59.69±0.13
------
detail of
® part
C
F
H
K
L
M
N
P
Q
S
44.45
8.255
1.27 (T.P.)
7.B2
INCHES
2.35±0.006
1.750
0.325
0.050 (T.P.)
0.300
2.03±0.13
0.060~8:88~
3.175±0.13
17.76
25.4±0.13
2.463 MAX.
R2.0
R2.0
III 1.6
0.125±0.00B
0.700
1.000±0.00B
0.097 MAX.
RO.079
RO.079
1Il0.071
T
1.0±0.1
0.039~8:88~
u
3.175 MIN.
0.25 MAX.
1.04±0.05
2.54 MIN.
0.125 MIN.
0.010 MAX.
0.041±0.002
0.100 MIN.
M728-50A 1·2
V
W
X
171
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC-42S2000LAD32S SERIES
2 M-WORD BY 32-BIT DYNAMIC RAM MODULE (SO DIMM)
FAST PAGE MODE
Description
The MC-42S2000LAD32S series is a 2,097,152 words by 32 bits dynamic RAM module (Small Outline DIMM)
on which 4 pieces of 16 M DRAM: JlPD42S18160L are assembled.
This module provides high density and large quantitios of memory in a small space without utilizing tho
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• CAS before RAS self refresh, CAS before RAS refresh, RAS only rofresh, Hidden refresh
• 2,097,152 words by 32 bits organization
• Fast access and cycle time
Power consumption
(MAX.)
Family
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-42S2000LAD32S-A60
60 ns
110 ns
1,083.6 mW
MC-42S2000LAD32S-A10
10 ns
130 ns
1,011.6 mW
MC-42S2000LAD32S-A80
80 ns
150 ns
939.6 mW
--
Activo
•
Standby
2.16 mW
(CMOS level input)
, ,024 refresh cycles/128 ms
• 72-pin dual in-line memory module (Pin pitch
= 1.27 mm)
• Single +3.3 V ±0.3 V power supply
The Information In this document is subject to change without notice.
IC-J461 (Japan)
173
NEe
MC-42S2000LAD32S SERIES
Ordering Information
Part number
174
Access time
(MAX.)
MC-42S2000LAD32SA-A60
60 ns
MC-42S2000LAD32SA-A70
70 ns
MC-42S2000LAD32SA-A80
80 ns
Package
72-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
Mounted devices
4 pieces of /lPD42S18160LG5
(400 mil TSOP (11))
[Double side]
NEe
MC-42S2000LAD32S SERIES
Pin Configuration
72-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
C
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
N
44
s:
c;')
t
en
N
0
0
0
>
w
en
:J>
46
48
50
52
54
56
58
60
62
64
66
68
70
72
AO -A9
Address Inputs
1/00 RASa
CASO
WE
PD1 -
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Write Enable
1/031
- RAS3
- CAS3
1/00
1/02
1/04
1/06
Vee
AO
A2
A4
A6
NC
1/09
1/011
1/013
A7
Vee
A9
RAS"2
NC
!lQJl
CASa
CAS3
RASa
NC
NC
1/019
1/021
1/023
1/024
1/026
1/027
1/029
1/031
PD2
PD4
PD6
GND
GND
1/01
1/03
1/05
1/07
PDl
Al
A3
A5
NC
1/08
1/010
1/012
1/014
NC
A8
RAS3
1/015
1/016
GND
CAS2
CASl
RASl
WE
1/018
1/020
1/022
NC
1/025
1/028
Vee
1/030
NC
PD3
PD5
PD7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
oct
en
N
~
C
:s8
0
N
en
.
~
CJ
:E
The internal connection of PD pins (PD1 - PD7).
Access Time
Pin
Name
Pin
No.
60 ns
11
NC
70 ns
NC
80 ns
PDl
PD2
66
GND
GND
GND
Vee
Presence Detect Pins
Power Supply
PD3
67
GND
GND
GND
GND
NC
Ground
No connection
PD4
68
GND
GND
GND
PD5
PD6
69
NC
GND
NC
to
PD7
71
NC
GND
NC
GND
GND
GND
PD7
NC
175
NEe
MC-42S2000LAD32S SERIES
Block Diagram
WE
RASl
RASO
CASl
CASO
I
~
~
LCAS UCAS RAS
1/00
1/01 o·
1/02
1/03
1/04
1/05
1/06 0"
1/07 0"
1/08
1/09
1/010
1/011
1/012
1/013 01/014 01/015 o·
~
WE
!
LCAS UCAS RAS
1/01
1/02
1/03
1/04
WE
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/05
1/06
1/07
1/08
1/09
1/08
1/09
00
1/010
02
1/010
1/011
1/012
1/013
1/014
1/015
1/011
1/012
1/013
.. 1/014
.. 1/015
1/016
1/016
,bElr
OEII
RAS3
I
~
~
~
LCAS UCAS RAS
1/016 0.1/017
WE
1/01
1/01
1/02
1/03
1/04
1/02
1/018
1/019
1/020
1/021
1/05
1/06
1/022
1/023
1/07
1/08
1/09
1/024
1/025
1/026
1/027
1/028
1/029
1/030
1/031
WE
1/03
1/04
1/05
1/06
1/07
1/08
1/09
01
1/010
03
1/010
1/011
1/011
1/012
1/013
1/014
1/015
1/016
1/012
1/013
1/014
1/015
1/016
OElr
AO-A9 0 - - - - - - . 00-03
Vee o--~_---. 00-03
...J- CO-C3
GNO o--T
___--_. 00-03
176
1
LCAS UCAS RAS
Remark 00-03: IlP042S18160LG5 (TSOP (11))
OEII
NEe
MC-42S2000LAD32S SERIES
Electrical Specifications
Notes 1.2
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-0.5 to +4.6
V
Supply voltage
Vee
-0.5 to +4.6
V
Output current
10
20
mA
Power dissipation
Po
8
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
Tot.
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
3.0
3.3
3.6
V
2.0
Vee + 0.3
V
-0.3
+0.8
V
70
'C
MAX.
Unit
Supply voltage
Vee
High level input voltage
VIH
Low level input voltage
VIL
Operating ambient temperature
TA
0
Capacitance ITA
=25 'C, f =1 MHz)
Parameter
Input capacitance
Symbol
Test Condition
MIN.
TYP.
CII
AO-A9
35
CI2
WE
43
CI3
RASO - RAS3
23
CI.
CASO - CAS3
24
CliO
1/00 - 1/031
19
pF
Data Input/Output capacitance
pF
177
NEe
MC-42S2000LAD32S SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Icc,
Test condition
Icc2
301
tRC = tRC IMIN.I
tRAC = 70 ns
281
tRAC = 80 ns
261
10- 0 mA
2.0
10 = 0 mA
0.6
RAS Cycling
CAS;;: V,H IMIN.I
tRC = tRC IMIN.)
10=OmA
tRAC = 60 ns
301
tRAC = 70 ns
281
tRAC = 80 ns
261
RAS S V,L IMAX.I, CAS Cycling
tRAC = 60 ns
181
tpc = tpc IMIN.I
tRAC = 70 ns
161
= 80 ns
141
RAS Cycling
tRAC = 60 ns
301
tnc = tRC IMIN.)
tAAC = 70 ns
281
tRAC = 80 ns
261
tRAS S 1 Jls
RAS. CAS;;: VIH IMIN.)
---RAS. CAS;;: Vcc RAS only refresh current
Operating current
Icc3
Icc.
(Fast page mode)
0.2 V
10=OmA
CAS before RAS
Iccs
refresh current
tRAC
--
10 = 0 mA
CAS before RAS
IccG
long refresh current
MAX.
tRAC - 60 ns
10=OmA
Standby current
MIN.
RAS. CAS Cycling
Unit
Notes
mA
3.4.7
mA
mA
3.4.5.7
mA
3.4.6
mA
3.4
720
pA
3.4
600
pA
4
-5
+5
pA
-5
+5
pA
-
--
CAS before RAS refresh:
tnc = 125.0 liS
RAS. CAS:
Vcc -0.2 V S VIH S V,H IMAX.)
o V S V,L S 0.2 V
Standby:
RAS. CAS;;: Vcc -0.2 V
Address: V,H or V,L
WE:V,H
10= 0 mA
CAS before RAS
Icc,
RAS. CAS:
self refresh current
tRASS = 5 ms
Vcc -0.2 V s V,H S V,H IMAX.I
o V S V,L S 0.2 V
10-OmA
Input leakage current
h IL)
V,. 0 to 3.6 V
All other pins not under test = 0 V
Output leakage current
10 III
Va = 0 to 3.6 V
Output is disabled (Hi-Z)
178
=-2.0 mA
High level output voltage
VOH
10
Low level output voltage
VOL
10 = +2.0 mA
2.4
V
0.4
V
NEe
MC-42S2000LAD32S SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
tRAC
= 60 ns
tRAC
= 70 ns
tRAC
= 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Notes 8, 9
Unit
Notes
Read/Write Cycle Time
tRC
110
130
150
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Access Time from RAS
tRAC
60
70
80
ns
Access Time from CAS
tCAC
15
20
20
ns
10, 11
Access Time Column Address
tAA
30
35
40
ns
10, 11
Access Time from CAS Precharge
tACP
45
ns
11
RAS to Column Address Delay Time
tRAD
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
Output Buffer Turn-off Delay Time from CAS
tOFF
Transition Time (Rise and Fall)
RAS Precharge Time
35
40
30
15
0
13
tr
3
50
tRP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
70
125,000
RAS Hold Time
tRSH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tRCD
20
CAS to RAS Precharge Time
tCRP
5
35
17
ns
11
0
15
0
15
ns
12
3
50
3
50
ns
80
10,000
ns
80
125,000
ns
0
0
50
60
18
10,000
20
20
ns
20
10,000
70
45
10, 11
20
ns
10,000
ns
60
ns
10
ns
13
80
50
25
5
5
ns
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
35
40
45
ns
Row Address Setup Time
tASR
0
0
0
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twcH
10
10
15
ns
15
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tDH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tCSR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
ns
RAS Pulse Width (CAS before RAS Self Refresh)
bASS
100
100
100
JJS
RAS Precharge Time (CAS before RAS Self Refresh)
tRPS
110
130
150
ns
CAS Hold Time (CAS before RAS Self Refresh)
tCHS
-50
-50
-50
ns
WE Hold Time
twHR
15
15
15
ns
Refresh Time
tREF
128
128
128
ms
179
NEe
MC-42S2000LAD32S SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 J.IS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3.
4.
5.
6.
Icc1, Icc3, Icc4, Icc5 and Icc6 depend on cycle rates (tRC and tpc).
Specified values are obtained with outputs unloaded.
Icc3 is measured assuming that all column address inputs are held at either high or low.
Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS::;; VIL
IMAX.) and CAS
~
VIH (MIN.).
B. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H
iMIN.'
=2.0 V
VIL
(MAX.'
= 0.8 V
.----------:AfL-----,i
i
______________
I
I
,
,
I
I
,
I
I
I
I
I
I
-,
IT
I
I
r
;tT = 5 ns
-~
=5 ns
(2) Output timing specification
(MIN.'
= 2.0 V
VOL (MAX,
= O.B V
VOl!
10. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD s tRAD (MAX.' and tRCD S tRCD (MAX.'
tRACIMAX.'
tRACIMAX.'
tRAD > tnAD (MAX.I and tRCD S tRCD (MAX.'
tAA(MAX.,
tRAD + tAA (MAX.'
tRCD > tRCD (MAX.I
tCAC(MAX.1
tRCD + tCAC (MAX.I
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, 1M or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.)
and tRCD
~
tRCD (MAX.) will not cause any operation problems.
11. Loading conditions are 1 TTL and 100 pF.
12. tDFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13.
14.
15.
16.
17.
180
tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
Either tRCH (MIN.) or tRRH (M)N.) should be met in read cycles.
In early write cycles, twCH (MIN.) should be met.
tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles.
Iftwcs ~ twCS(MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
Timing Chart
Please refer to Timing Chart 5, page 409.
181
NEe
MC-42S2000LAD32S SERIES
Package Drawing
72 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A
N
z
Q
~
p
®
[[]
c
o
DO
detail of ® part
-if-
-Mtrx
[[]>
ITEM
A
C
F
Q
2.0
3.18
17.78
25.4
3.8 MAX.
R2.0
R2.0
INCHES
2.35±0.00S
1.750
0.325
0.050 (T.P.)
0.300
0.079
0.125
0.700
1.000
0.150 MAX.
RO.079
RO.079
H
I
J
K
L
M
N
P
MILLIMETERS
59.S9±0.13
44.45
8.255
1.27 (T.P.)
7.S2
R
4.0±0.1
0.157~8:88~
s
184
2
1/00
1/02
4
6
1/04
1/06
8
10
Vee
12
AO
14
A2
16
A4
A6
18
20
NC
22
1/09
24
1/011
26
1/013
28
A7
30
Vee
32 ---OA9
34 ~---O R.A.S2
36 -oNC
38 ~ ~o 1/917
40 ~- - -0 CIISO
42 ~
o CIIS3
o il11S0
44
() NC
46 ONC
48 -~o
1/019
50
52
~1/021
54
~1/023
~ 1/024
56
58
~1/026
60
1/027
62
1/029
64
1/031
66
PD2
PD4
68
70
PD6
72
GND
~-
AO - A10
Address Inputs
1/00 - 1/031
Data Inputs/Outputs
RASO - RAS3
Row Address Strobe
CASO - CAS3
Column Address Strobe
GND
1/01
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
1/03
1/05
1/07
PDl
Al
A3
A5
Al0
1/08
1/010
1/012
1/014
NC
A8
I1AS3
1/015~
1/0160~-
GND
CAS20CASloRASlO--
~
til
N
M
IX!
:30
0
0
"'"
rJ)
~
U
45
:!!
47
WEo--~
49
1/0180-1/020o--~
1/022O--~
51
53
NCO-- 55
1/025
57
1/028
59
Vee
61
1/030
63
NC
65
PD3
67
PD5
69
PD7
71
The internal connection of PD pins (PD1 to PD7).
Access Time
Pin
Name
Pin
No.
60 ns
70 ns
80 ns
11
GND
GNO
GNO
WE
Write Enable
P01
PD1 - PD7
Presence Detect Pins
PD2
66
NC
NC
NC
Vee
Power Supply
PD3
67
GND
GND
GND
GND
Ground
NC
No connection
PD4
68
GNO
GND
GNO
P05
69
NC
GNO
NC
P06
70
NC
NC
GND
P07
71
GND
GNO
GNO
NEe
MC-42S4000LAB32S SERIES
Block Diagram
~
I
!
1/00
1/01
1/02
1/03
1/04
1/05
1/06
1/07
~
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
I
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
RAS2
CAS2
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
~
CAS3
02
01:"*
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
CAS RAS WE
03
OE"*
+ +
04
,,,
010 -,;,.
+
+ +
~
01
OE"*
+ + +
1/08
1/09
1/010
1/011
1/012
1/013
1/014
I/q15
1/024
1/025
1/026
1/027
1/028
1/029
1/030
1/031
DO
I
CAS1
1/016
1/017
1/018
1/019
1/020
1/021
1/022
1/023
CAS RAS WE
OE"*
06
OE"*
05
,
OE~
07
OE"*
AO-A10 0 - - - - - -..
• DO-D7
o---:c..----.
Vee
DO-D7
=r=CO-C7
GND 0------+----+-----.. DO-D7
Remark 00-07: IlP042S17800LG5 (TSOP (II))
185
NEe
MC-42S4000LAB32S SERIES
Electrical Specifications Notes 1,2
Absolute Maximum Ratings
Rating
Unit
Voltage on any pin relative to GND
Symbol
VT
-0.5 to +4.6
V
Supply voltage
Vee
-0.5 to +4.6
V
Output current
10
.20
mA
Parameter
Condition
Power dissipation
Po
8
W
Operating ambient temperature
TA
o to +70
·C
Storage temperature
Tstg
-55 to +125
·C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Vee
High level input voltage
V,H
Condition
.. _-
.. -
MIN.
TYP.
3.0
3.3
MAX.
Unit
3.6
V
2.0
Vee + 0.3
V
Low level input voltage
VIC
-0.3
+0.8
V
Operating ambient temperature
TA
0
70
·C
Capacitance ITA
= 25 ·C, f = 1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
186
Symbol
Symbol
Test Condition
MIN.
TYP.
MAX.
Unit
Cil
AO· A10
55
pF
C"
WE
71
C'3
RASO - RAS3
30
C,.
CASO - CAS3
24
CliO
1/00 - 1/031
19
pF
NEe
MC-42S4000LAB32S SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
IccI
Test condition
Icc,
RAS only refresh current
Icc3
Operating current
Icc.
(Fast page mode)
Icc.
Iccs
mA
3,4,7
405
tRAC = 70 ns
365
tRAC = 80 ns
325
10 = 0 mA
4.0
RAS, CAS
~
V,H IMIN.I
RAS, CAS
~
Vcc - 0.2 V
10 = 0 mA
1.2
tRAC = 60 ns
405
= 70 ns
365
RAS Cycling
CAS ~ V,H IMIN.I
tRC = tRC IMIN.I
10 = 0 mA
IliAC = 80 ns
325
RAS :5 V,L IMAX.I, CAS Cycling
IliAC" 60 ns
285
IliAC" 70 ns
245
IliAC" BO ns
205
tllAC
-----.-1---+----1
mA
mA
3,4,5,7
mA
3,4,6
-_ .. - -+---+----1
~--_r--+_--I----4
RAS Cycling
IliAC " 60 ns
405
tRC = tRC IMIN.I
IliAC,' 70 ns
365
IliAC" 110 ns
325
IRAS "', I/s
10= 0 mA
CAS before RAS
Notes
tRAC = 60 ns
~-------r_--+_--------·I---
CAS before RAS
Unit
RAS, CAS Cycling
tpc = tpc IMIN.I
10 = 0 mA
refresh current
MAX.
tRC = tRC IMIN.I
10 = 0 mA
Standby current
MIN.
CAS before RAS refresh:
mA
3,4
1.6
mA
3,4
1.2
mA
4
tRC =62.5 JJS
long refresh current
----
RAS, CAS:
Vcc -0.2 V :5V,H :5V,H IMAX.I
o V:5 V,L :50.2 V
Standby:
----
RAS, CAS
~Vcc
-0.2 V
Address: V,H or V,L
WE :V,H
10
CAS before RAS
Icc7
self refresh current
= 0 mA
RAS, CAS:
tRASS
= 5 ms
Vcc -0.2 V :5V,H :5V,H IMAX.I
V :5V,L :50.2 V
o
10 = 0 mA
Input leakage current
hiLI
V, = 0 to 3.6 V
-5
+5
-5
+5
All other pins not under test = 0 V
Output leakage current
Vo = 0 to 3.6 V
Output is disabled (Hi-Z)
High level output voltage
VOH
10 = -2.0 mA
Low level output voltage
VOL
10 = +2.0 mA
V
2.4
0.4
V
187
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MC-42S4000LAB32S SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
tRAC
= 60 ns
tRAC
= 70 ns
tRAC
= 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read/Write Cycle Time
tRC
110
130
150
Fast Page Mode Cycle Time
tpc
40
45
50
Access Time from RAS
tRAC
60
tCAC
Access Time from CAS
Access Time Column Address
. tAA
Access Time from CAS Precharge
tACP
RAS to Column Address Delay Time
tRAD
15
CAS to Data Setup Time
tCLZ
0
Unit
ns
70
80
ns
10, 11
15
18
20
ns
10, 11
30
35
40
ns
10, 11
35
40
45
ns
11
40
ns
10
ns
11
12
30
15
35
0
17
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
13
0
15
0
15
ns
tT
3
50
3
50
3
50
ns
RAS Prccharge Time
tRP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
IRSH
15
15
Notes
ns
Transition Time (Rise and Fall)
60
50
18
10,000
18
ns
20
10,000
20
ns
10,000
CAS Pulse Width
tCAS
CAS Hold Time
test{
RAS to CAS Delay Time
tneD
20
ns
10
CAS to RAS Precharge Time
tcnp
5
5
5
ns
13
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
35
40
45
ns
Row Address Setllp Time
tASR
0
0
0
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
ns
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
tWCH
10
10
15
ns
15
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tDH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tCSR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
ns
RAS Pulse Width (CAS before RAS Self Refresh)
tRASS
100
100
100
JlS
RAS Precharge Time (CAS before RAS Self Refresh)
tRPS
110
130
150
ns
CAS Hold Time (CAS before RAS Self Refresh)
tCHS
-50
-50
-50
ns
WE Setup Time
twSR
10
10
10
ns
WE Hold Time
tWHR
15
15
15
Refresh Time
tREF
--.-
Read Command
188
Symbol
Setu~
Time
---
_60 ....
70
45
128
20
80
50
128
25
ns
ns
60
ns
128
ms
NEe
MC-42S4000LAB32S SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JiS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. IccI, Icc3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. IccI and Icc3 are measured assuming that address can be changed once or less during RAS ~ VIL
IMAX.) and CAS;:: VIH IMIN.).
8. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H
IMIN.I
= 2.0 V
·----------~-----,-i
!,
______________
I
I
,
,
V,L IMAX.I = 0.8 V
I
I
I
I
I
I
,
,
I
1:,
,
I
I
:.
IT = 5 ns
IT = 5 ns
(2) Output timing specification
VOH
IMIN.)
= 2.0 V
VOL IMAKI = 0.8 V
10. For read cycles, access time is defined as follows:
Input Conditions
tRAO $ tRAO IMAX.I and tRCO $ tRCO IMAX.I
tRAD
>
bAD (MAX.)
tRCO
>
tRCO IMAX.I
and
tRCO
S tRCO (MAX.)
Access Time
Access Time from RAS
tRAC IMAX.I
tRAC IMAX.I
tAAIMAX.1
tRAO
+ tAA (MAX.)
tCACIMAX.1
tRco
+ tCAC IMAX.I
tRAO(MAX.) and tRCO(MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAO ~ tRAD(MAX.)
and tRCO ;:: tRCO IMAX.) will not cause any operation problems.
11. Loading conditions are 1 TTL and 100 pF.
12. tOFF IMAX.) defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13. tCAP IMIN.) requirements should .be applied to RAS/CAS cycles.
14. Either tRCH (MIN.) or tRRH IMIN.) should be met in read cycles.
15. In early write cycles, twCH IMIN.) should be met.
16. tos IMIN.) and tOH IMIN.) are referenced to the CAS falling edge in early write cycles.
17. Iftwcs ~ twcsIMIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
189
Timing Chart
Please refer to Timing Chart 6, page 419.
190
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MC-42S4000LAB32S SERIES
Package Drawing
72PIN DUAL IN-LINE MODULE (SOCKET TYPE)
f-------- A
-------.J'I
Q
S
(OPTIONAL HOLES)
K
DODD
p
--+~----
c---
o
detail of ® part
ITEM
A
C
F
H
MILLIMETERS
59.69+0.13
44.45
8.255
1.27 (T.P.)
7.62
K
L
M
N
P
x
Q
S
INCHES
2.35+0.006
1.750
0.325
0.050 (T.P.)
0.300
2.03±0.13
0.080~8:88~
3.175±0.13
17.78
25.4±0.13
3.81 MAX.
R2.0
R2.0
q, 1.8
0.125±0.006
0.700
1.000±0.006
0.150 MAX.
RO.079
RO.079
q,0.071
T
1.0±0.1
0.039~8:88~
u
3.175 MIN.
0.25 MAX.
1.04±0.05
2.54 MIN.
0.125 MIN.
0.010 MAX.
0.04110.002
0.100 MIN.
M725-S0A2·2
V
W
X
191
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC·42S4000LAC32S SERIES
4 M-WORD BY 32-BIT DYNAMIC RAM MODULE (SO DIMM)
FAST PAGE MODE
Description
The MC-42S4000LAC32S series is a 4,194,304 words by 32 bits dynamic RAM module (Small Outline DIMM)
on which 8 pieces of 16 M DRAM: J.LPD42S17400LG3 (TSOP (11) are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• CAS before RAS self refresh, CAS before RAS refresh, RAS only refresh, Hidden refresh
• 4,194,304 words by 32 bits organization
• Fast access and cycle time
Power consumption
(MAX.)
Family
Access time
(MAX.)
R/W cycle time
MC-42S4000LAC32S-A60
60 ns
110 ns
2,880 mW
MC-42S4000LAC32S-A70
70 ns
130 ns
2,592 mW
MC-42S4000LAC32S-A80
80 ns
150 ns
2,304 mW
(MIN.)
Active
• 2,048 refresh cycles/128 ms
• 72-pin dual in-line memory module (Pin pitch
Standby
4.32 mW
(CMOS level input)
= 1.27 mm)
• Single +3.3 V ±0.3 V power supply
The Information In this document Is subject to change without notice.
IC'3460 (Japan)
193
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MC-42S4000LAC32S SERIES
Ordering Information
Part number
194
Access time
(MAX.)
MC-42S4000LAC32SA-A60
60 ns
MC-42S4000LAC32SA-A70
70 ns
MC-42S4000LAC32SA-ASO
80 ns
Package
72-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
Mounted devices
8 pieces of /lPD42S17400LG3
(300 mil TSOP (11))
[Double side]
NEe
MC-42S4000LAC32S SERIES
Pin Configuration
72-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
3:
\I
~
I
5
~
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
AO - A10
1/00 - 1/031
RASa. RAS2
CASO - CAS3
WE
PD1 - PD7
Vee
GND
NC
Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Write Enable
Presence Detect Pins
Power Supply
Ground
No connection
1/00
1/02
1/04
1/06
Vee
GNO
1/010-0-
AO
A2
POl
Al
A3
A5
Al0
1/08
1/010
A4
A6
NC
1/09
1/011
1/013
A7
Vee
A9
RAS2
NC
1/017
CASO
CAS3
RASO
NC
NC
1/019
1/021
1/023
1/024
1/026
1/027
1/029
1/031
P02
PD4
PD6
GNO
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
1/0301/05
1/07
1/012
1/014
NC
AS
NC
1/015
1/016
GNO
CAS2
CASl
NC
WE
1/018
1/020
1/022
NC
1/025
1/028
Vee
1/030
~
~
S
§
/I)
~
~
63
NC
P03
P05
P07
65
67
69
71
The internal connection of PO pins (PD1 to PD7).
Pin
Name
Access Time
Pin
No.
60 ns
70 ns
PD1
11
NC
NC
NC
PD2
66
NC
NC
NC
PD3
67
GND
GND
GND
P04
68
NC
NC
NC
PDS
69
NC
GNO
NC
80 ns
P06
70
NC
NC
GNO
P07
71
GNO
GNO
GNO
195
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MC-42S4000LAC32S SERIES
Block Diagram
Remark 00-07: ttPD42S17400LG3 (TSOP (II))
1/00
1/01
1/02
1/03
1/01
1/02
1/03
1/04
*OE
1/04
~
1/05
1/06
1/07 0-
1/09
1/010
1/011
+
RAS
, ,
J
WE
1/01 CAS RAS
1/02
03
1/03
1/04
*OE
WE
+
CAS
+
1/016
1/017
1/01
1/02
1/018
1/019
1/03
1LQ4
*OE
1/020
1/021
1/022
1/023
1/01 CAS RAS
1/02
05
1/03
1LQ4
*OE
1/024
1/01
1/025
1/02
1/03
1LQ4
OE
1/026
1/027
*
1/028
1/029
1/01
1/030
1/03
1/031
1/04
*OE
1/02
RAS
~
WE
04
+
+
CAS
t
RAS
t
WE
WE
06
, , ,
CAS
RAS
07
AD-A 10 o-----~· DO-D7
196
i
WE
1/01 CAS RAS
1/02
02
1/03
1/04
*OE
+
1/012
1/013
1/014
1/015
+
WE
DO
1/01 CAS RAS
1/02
1/03
01
1LQ4
*OE
CASl
1/08
+
CAS
Vee O------~~--. DD-D7
CD-C7
GNDO
T
. DO-D7
WE
NEe
MC-42S4000lAC32S SERIES
Electrical Specifications Notes 1,2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-0.5 to +4.6
V
Supply voltage
Vee
-0.5 to +4.6
V
Output current
10
20
mA
Power dissipation
PD
8
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
Tstg
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
3.3
MAX.
Unit
Supply voltage
Vee
3.0
3.6
V
High level input voltage
V,H
2.0
Vee + 0.3
V
Low level input voltage
V,L
-0.3
+0.8
V
Operating ambient temperature
TA
0
70
'C
MAX.
Unit
Capacitance ITA
=25 'C, f =1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
Test Condition
Symbol
MIN.
TYP.
CII
AO·A10
55
C"
WE
71
C'3
RASO, RAS2
36
C"
CASO· CAS3
19
CliO
1/00·1/031
10
pF
pF
197
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MC-42S4000LAC32S SERIES
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
ICCI
Test condition
RAS only refresh current
Operating current
Icc,
Icc3
Icc.
(Fast page mode)
RAS, CAS Cycling
hAC = 60 ns
800
tRAC = 70 ns
720
tRAC = 80 ns
640
RAS, CAS ~ V'H IM'N.!
10=OmA
4
RAS, CAS ~ Vcc - 0.2 V
10= 0 mA
1.2
RAS Cycling
CAS ~ V'H IM,N.!
tRC = tRC IM,N.l
10= 0 mA
tRAC = 60 ns
800
tRAC = 70 ns
720
RAS S V,L IMAX.J, CAS Cycling
tpc = tpc IM,N.!
10= 0 mA
CAS before RAS
Icca
rafresh current
CAS before RAS
lcee
tRAC = 80 ns
640
tRAC = 60 ns
560
tRAC = 70 ns
480
tRAC = 80 ns
400
Unit
Notes
mA
3,4,7
mA
mA
3,4,5,7
mA
3,4,6
mA
3,4
RAS Cycling
tRAC = 60 ns
800
tRC = tRC IM,N.l
tRAC = 70 ns
720
tRAC = 80 ns
640
tRAS S 1 liS
1.6
mA
3,4
1.2
mA
4
-5
+5
pA
-5
+5
pA
10=OmA
long refresh current
MAX.
tRC = tRC IM,N.'
10= 0 mA
Standby current
MIN.
CAS before RAS refresh:
tRC = 62.5 JlS
---RAS, CAS:
Vcc -0.2 V s V'H S V'H IMAX.l
o V S V'L S 0.2 V
Standby:
--
RAS ~ Vcc -0.2 V
Address: V'H or V'L
WE:V'H
10 = 0 mA
CAS bafora RAS
Icc7
self refresh current
RAS, CAS:
tRASS = 5 ms
Vee -0.2 V S V'H S V'H IMAlt!
o V S V'L S 0.2 V
10= 0 mA
Input leakage current
11Iu
V, = 0 to 3.6 V
All other pins not under test - 0 V
Output leakage current
lOlL!
Vo = Oto 3.6 V
Output is disabled (Hi-Zl
198
High level output voltage
VOH
10=-2.0 mA
Low level output voltage
VOL
10= +2.0 mA
2.4
V
0.4
V
NEe
MC-42S4000lAC32S SERIES
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
Symbol
tAAe
= 60 ns
tAAe
= 70 ns
tAAe
=80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Notes
Read/Write Cycle Time
tAe
110
130
150
Fast Page Mode Cycle Time
tpe
40
45
50
Access Time from RAS
tAAe
60
70
80
ns
10, 11
Access Time from CAS
teAe
15
18
20
ns
10, 11
Access Time Column Address
tAA
30
35
40
ns
10, 11
Access Time from CAS Precharge
tAep
45
ns
11
RAS to Column Address Delay Time
tAAO
15
40
ns
10
CAS to Data Setup Time
teLZ
0
ns
11
12
35
30
40
15
35
0
17
ns
ns
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
15
0
15
0
20
ns
Transition Time (Rise and Fall)
tT
3
50
3
50
3
50
ns
RAS Precharge Time
tAP
40
RAS Pulse Width
tAAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tAASP
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
tASH
15
CAS Pulse Width
tCAS
15
10,000
18
10,000
ns
CAS Hold Time
tesH
60
RAS to CAS Delay Time
tnco
20
CAS to RAS Precharge Time
ten ...
5
5
CAS Precharge Time
tePN
10
10
50
60
18
20
10,000
70
40
20
ns
20
ns
80
50
25
ns
60
ns
10
5
ns
13
10
ns
10
10
10
ns
RAS Precharge CAS Hold Time
tlll'C
5
5
5
ns
RAS Hold Time from CAS Precharge
tlUICE'
.. _.
35
40
45
ns
Row Address Setup Time
tA,n
0
0
0
ns
Row Address Hold Time
tAAH
10
10
12
ns
Column Address Setup Time
tAse
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
CAS Precharge Time (Fast Page Mode)
tcf·
._-_
...
Column Address Lead Time Referenced to RAS
tAAL
30
35
40
ns
Read Command Setup Time
tAes
0
0
0
ns
Read Command Hold Time Referenced to RAS
tAAH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
tweH
10
10
15
ns
15
Data-in Setup Time
tos
0
0
0
ns
16
Data-in Hold Time
tOH
10
15
15
ns
16
Write Command Setup Time
twes
0
0
0
ns
17
CAS Setup Time (CAS before RAS Refresh)
tesR
5
5
5
ns
ns
CAS Hold Time (CAS before RAS Refresh)
teHR
10
10
10
WE Setup Time
twSR
10
10
10
ns
WE Hold Time
twHR
15
15
15
ns
RAS Pulse Width (CAS before RAS Self Refresh)
tRASS
100
100
100
/IS
RAS Precharge Time (CAS before RAS Self Refresh)
tAPS
110
130
150
ns
CAS Hold Time (CAS before RAS Self Refresh)
teHs
-50
Refresh Time
tREF
-50
128
-50
128
ns
128
ms
199
NEe
MC-42S4000LAC32S SERIES
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 ps and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. IccI, Icc3, Icc., Iccs and Icc6 depend on cycle rates (tAC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
S. Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. IccI and Icc3 are measured assuming that address can be changed once or less during RAS:s; Vil
(MAX.) and CAS ~ VIH (MIN.).
S. AC measurements assume tr = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
VIH
(MIN.I
= 2.0 V
.----------~-----i
i
______________
I
I
,
: :
Vil (MAX.) = 0.8 V
I
Ji!
I
,
: :
I
..
tr = 5 ns
I
..
tr = 5 ns
(2) Output timing specification
VOH (MIN.) = 2.0 V
VOL (MAX.)
=0.8 V
10. For read cycles, access time is defined as follows:
Input Conditions
tRAD
:S
tRAD
> tRAD (MAX.)
tAco >
tRAD (MAX.) and
Access Time
Access Time from RAS
tAco :S
tRCD (MAX.)
tRAC (MAX.)
tRAC(MAX.)
:S
tRCD (MAX.)
tAA(MAX.)
tRAD
+
tAA (MAX.)
tCAC(MAX.)
tRCD
+
tCAC (MAX.)
and tRCD
tRCD (MAX.)
tRAO(MAX.) and tRCO (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, 1M or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tAAO ~ tAAO (MAX.)
and tACO ~ tRCO (MAX.) will not cause any operation problems.
11. Loading conditions are 1 TIL and 100 pF.
12. tOFF (MAX.) defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
13.
14.
15.
1S.
17.
200
tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
In early write cycles, twCH (MIN.) should be met.
tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles.
If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
Timing Chart
Please refer to Timing Chart 6, page 419.
201
NEe
MC-42S4000LAC32S SERIES
Package Drawing
72 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A
N
z
Q
p
®
[8]
c
o
DODD
detail of ® part
~x
[[]>
202
ITEM
A
C
F
H
MILLIMETERS
59.69±0.13
44.45
8.255
1.27 (T.P.)
7.62
INCHES
2.35±0.006
1.750
0.325
0.050 (T.P.)
0.300
0.079
0.125
0.700
1.000
0.150 MAX.
RO.079
RO.079
Q
2.0
3.18
17.78
25.4
3.8 MAX.
R2.0
R2.0
R
4.0±0.1
0.157~8:88~
s
---------~--__,
WEoo-~~~------_r_.
WE20-1~--------+-,
CASO O--f).--------,
CAS4 0-1;>-------,
.------:~~~",....,,~
.------:~~~",....,,~
1/00
I/O 1
I/O 2
1/03
I/O 32
I/O 33
1/034
1/04
I/O 5
1/06
1/07
I/O 36
I/O 37
1/038
I/O 39
1/035
CAS10--D>---------,
CAS5 o-~)>---------,
.------:*'-d::~",....,,!::_,
1/040
1/041
1/042
1/043
1/044
1/045
1/046
1/047
CAS2 o---D>---------,
CAS6 0--0--------,
....------:::b--d:::--:::!:",....,,;"""
I/O 16
.------:;~~~;;--;;~
I/O 48
I/O 49
I/O 17
I/O 18
I/O 19
1/050
I/O 51
I/O 52
1/020
I/O 21
I/O 22
I/O 23
I/O 53
1/054
I/O 55
CAS3 o-~)>---------,
CAS7 0-1)--------,
.------:*'-d::~=-""!::_,
.------:~~~",....,,!::-,
I/O 24
I/O 25
1/026
I/O 27
1/056
1/028
I/O 29
1/030
1/031
I/O 60
I/O 61
I/O 62
I/O 63
o----f>-- AO : DO - 07
o----f>-- AO: 08 - 015
Al - A9 o----f>-- DO - 015
AO
80
I/O 57
I/O 58
I/O 59
POE~
POl - P08~ Vccor GNO
100. 101 0
Vee 0
Remark DO - 015 : ,uPD424400
208
GNOO
NC or GNO
::l:
• 00-015
Co-C15
T
• 00-015
NEe
MC-421000AA64FA
Electrical Specifications
Notes 1. 2
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
mA
Power dissipation
Po
18
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
Totg
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device Is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
5.0
MAX.
Unit
Supply voltage
Vee
4.75
5.25
V
High level input voltage
V,H
2.4
Vee + 1.0
V
Low level input voltage
V,L
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
·C
MAX.
Unit
Capacitance ITA
=25 'c, f =1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
Symbol
Test Condition
MIN.
TYP.
C"
AO - A9. 60
20
C'2
WEO. WE2
20
C'3
RASO.RAS2
78
C,.
CASO - CAS7
20
C's
OEO.OE2
20
eva
1/00 -1/063
20
pF
pF
209
NEe
MC-421000AA64FA
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Icc1
Test condition
RAS only refresh current
Operating current
Icc2
Icc3
Icc.
(Fast page mode)
tRAC = 60 ns
1,984
tRC = tRC IMIN.)
tRAC = 70 ns
1,664
tRAC = 80 ns
1,504
RAS, CAS 2: V,H IMIN.)
10= 0 mA
96
RAS, CAS 2: Vcc - 0.2 V
10= 0 mA
80
RAS Cycling
CAS 2: VIH 1M IN.)
tRC = tRC IMIN.)
10 = 0 mA
tRAC = 60 ns
1,984
tRAC = 70 ns
1,664
tRAC = 80 ns
1,504
RAS S VIL IMAX.), CAS Cycling
tRAC = 60 ns
1,504
tpc = tpc IMIN.)
tRAC = 70 ns
1,344
tRAC = 80 ns
1,184
RAS Cycling
tRAC = 60 ns
1,984
tAC :: tAC IMIN.I
tRAC = 70 ns
1,664
tRAC = 80 ns
1,504
10 = 0 mA
CAS boforo RAS
Icc!i
rofrosh current
10 = 0 mA
Input leakage curront
hiLi
V, = 0 to 5.5 V
/RAS
I
All other pins not under test = 0 V Othors
Output leakage current
lOlL)
Vo = 0 to 5.5 V
Output is disabled (Hi-Z)
210
MAX.
RAS, CAS Cycling
10= 0 mA
Standby current
MIN.
High level output voltage
VOH
10 = -5.0 mA
Low level output voltage
VOL
10 = +4.2 mA
-10
+10
-5
+1
-10
+10
2.4
Unit
Notes
mA
3,4,7
mA
mA
3,4,5,7
mA
3,4,6
mA
3,4
p.A
pA
V
0.4
V
NEe
MC-421000AA64FA
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
Symbol
tRAC = 60 ns
MIN.
MAX.
tRAC = 70 ns
MIN.
MAX.
tRAC = 80 ns
MIN.
Unit
Notes
MAX.
ReadIWrite Cycle Time
tRC
110
130
160
ns
Read Modify Write Cycle Time
tRWC
165
190
225
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Read Modify Write Cycle Time (Fast Page Mode)
tPRWC
80
90
100
Access Time from RAS
tRAC
60
70
80
ns
10, 11
Access Time from CAS
tCAC
20
25
25
ns
10, 11
Access Time Column Address
tAA
35
40
45
ns
10, 11
Access Time from CAS Precharge
tACP
40
45
50
ns
11
Access Time from OE
tOEA
20
25
25
ns
11
RAS to Column Address Delay Time
tRAD
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
ns
11
OE to Data Setup Time
tOLZ
0
Output Buffer Turn-off Delay Time from CAS
tOFF
0
30
15
35
0
0
0
15
0
17
0
15
0
OE to Data Delay Time
tOED
15
Output Buffer Turn-off Delay Time from OE
tOEZ
0
OE Hold Time
tOEH
0
0
0
OE Lead Time Referenced to RAS
tOES
0
0
0
Transition Time (Rise and Fall)
tr
3
15
15
0
3
70
10,000
70
125,000
RAS Precharge Time
tRP
40
tRAS
60
10,000
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
RAS Hold Time
tRSH
15
CAS Pulse Width
tcAS
15
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tRCD
20
CAS to RAS Precharge Time
tCRP
10
10
CAS Precharge Time
tCPN
10
10
50
50
20
20
3
10,000
11
ns
12
ns
ns
50
ns
80
10,000
ns
80
125,000
20
12
ns
ns
ns
ns
10,000
ns
60
ns
10
10
ns
13
10
ns
80
50
ns
ns
20
20
70
40
0
70
20
10,000
20
20
15
50
RAS Pulse Width
ns
25
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
10
10
10
ns
RAS Hold Time from CAS Precharge
tRHCP
40
45
50
ns
Row Address Setup Time
tASR
5
5
5
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
10
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twCH
15
15
15
ns
15
WE Pulse Width
twp
10
10
15
ns
15
211
NEe
MC-421000AA64FA
Parameter
Data·in Setup Time
212
Symbol
tRAC
= 60 ns
tRAC
= 70 ns
tRAC
= 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Notes
16
tos
0
0
0
ns
Data·in Hold Time
tOH
15
15
15
ns
16
Write Command Setup Time
twcs'
0
0
0
ns
17
CAS to WE Delay Time
tcwo
35
40
45
ns
17
RAS to WE Delay Time
tRWO
90
100
115
ns
17
CAS Precharge to WE Delay Time
tcPWO
55
60
70
ns
17
Column Address to WE Delay Time
tAWO
55
60
70
ns
17
WE Lead Time Referenced to RAS
tRWL
20
25
25
ns
WE Lead Time Referenced to CAS
tCWL
15
15
15
ns
CAS Setup Time (CAS before RAS Refresh)
tCSR
10
10
10
ns
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
15
WE Setup Time
twSR
0
0
10
ns
WE Hold Timo
twHR
10
10
15
ns
Refresh Timo
tREF
16
16
16
ms
NEe
MC-421000AA64FA
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. IccI, Icc3, Icc4 and Iccs depend on cycle rates· (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. IccI and Icc3 are measured assuming that address can be changed once or less during RAS 50 VIL
(MAX.1 and CAS
~
VIH {MIN.I.
B. AC measurements assume tT
= 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H (MIN.!
=2.4 V
V,L (MAI(,J
= 0.8 V
.----------:i1lL-----i
i
~_____________
,
,
,
I
I
I
I
,
I
I
I
.~
tr
I
:'
I
I
.
.: ;
=5 ns
tr
=5 ns
(2) Output timing specification
VOH (MIN.!
= 2.4 V
VOL (MAI(,J
= 0.4 V
10. For read cycles, access time is defined as follows:
Input Conditions
tRAD
50 tRAD IMAlt! and
tRCD S tRCD IMAX.!
Access Time
tRACIMAX.1
Access Time from RAS
tRACIMAX.1
tRAD
>
tRAD IMAX.) and tRCD S tRCD IMAX.!
tAAIMAX.!
tRAD
+ tAA IMAX.)
tRCD
>
tRCD IMAX.!
tCACIMAX.)
tRCD
+ tCAC IMAX.)
tRAD{MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, 1M or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions IRAD ~ tRAD {MAX.1
and tRCD
~
tRCD (MAX.) will not cause any operation problems.
11. Loading conditions are 2 TTLs and 100 pF.
12. tOFF (MAX.) and tOEZ (MAX.) define the time at which the output achieves the condition of Hi-Z and
are not referenced to VOH or VOL.
13. tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
14. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
15. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH
(MIN.) should be met.
213
NEe
MC-421000AA64FA
16. tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write
cycles and read modify cycles, they are referenced to the WE falling edge.
17. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. IftRwo ~tRWO(MIN.), tcwo ~ tCWO(MIN.), tAWD ~ tAWO(MIN.) and tcPWO
~
tCPWO(MIN.), the cycle
is read modify write cycle and the data out will contain data read from the selected cell. If neither
of the above conditions is met, the state of the data out is indeterminate.
214
Timing Chart
Please refer to Timing Chart 7, page 429.
215
NEe
MC-421000AA64FA
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A
a:
-- I-Y
z--
sF-00000
(OPTIONAL HOLES)
~,
l
nTl,
"
,
~
,
0000 G
"""'
, 0
~
1--1--[8]
I~G
I-
c
0
E
~ITDDDI;DIIIIIIIIIID'DDD1
detail of
® part
--rr-
~
m
ITEM
A
B
C
D
E
G
H
I
L
M
N
Q
MILLIMETERS
133.35±0.13
11.43
36.83
6.35
54.61
6.35
1.27 (T.P.)
8.89
17.78
25.4
9.0 MAX.
R2.0
INCHES
5.25±0.006
0.450
1.450
0.250
2.150
0.250
0.050 (T.P.)
0.350
0.700
1.000
0.355 MAX.
RO.079
R
4.0±0.1
0.157 ~g:gg~
s
T
3.0
1.27±0.1
0.118
0.05±0.004
U
V
4.0 MIN.
0.25 MAX.
0.157 MIN.
0.010 MAX.
W
1.0±0.05
0.039 ~g:88~
X
2.54 MIN.
3.0 MIN.
3.0 MIN.
0.100 MIN.
0.118 MIN.
0.118MIN.
Y
Z
Ml688-50Al
216
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC-421000AA64FB
1 M-WORD BY 64-BIT DYNAMIC RAM MODULE
FAST PAGE MODE
Description
The MC-421000AA64FB is a 1,048,576 words by 64 bits dynamic RAM module on which 4 pieces of 16 M
DRAM: tlPD4218160 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Oecoupling capacitors are mounted on power supply line for noise reduction.
Features
•
1,048,576 words by 64 bits organization
•
Fast access and cycle time
Power consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
MC-421000AAS4-S0
SO ns
110 ns
3.S8W
MC-421000AAS4-70
70 ns
130 ns
3.47 W
MC-421000AAS4-80
80 ns
150 ns
3.2SW
Family
(MIN.)
Active
Standby
33SmW
(CMOS level inputl
1,024 refresh cycles/16 ms
•
• CAS before RAS refresh, RAS only refresh, Hidden refresh
•
16S-pin dual in-line memory module (Pin pitch = 1.27 mm)
•
Single +5.0 V ±O.25 V power supply
Ordering Information
Part number
Access time
(MAX.)
MC-421000AAS4FB-SO
SO ns
MC-421000AAS4FB-70
70 ns
MC-421000AAS4FB-80
80 ns
Mounted devices
Package
1S8-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
4 pieces of pPD42181S0LE
(400 mil SOJ)
[Single side]
The Information in this document is subject to change without notice.
IC·3591 (Japan)
217
NEe
MC-421000AA64FB
Pin Configuration
16B-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
o
0
GND
1/032
1/033
1/034
1/035
V'"
1/04
1/05
1/06
1/07
NC
GND
1/040
1/041
1/042
1/043
1/044
NC
GND
1/08
1/09
I/O 10
I/O 11
I/O 12
1/045
1/046
1/047
NC
GNO
NC
-oNC
---OVec
-ONe
I/O 13
I/O 14
I/O 15
NC
GND
NC
NC
Vr.r.
~-O(:AS'
--oCAS3
NC
NC
GNO
Al
A3
A5
A7
A9
NC
NC
Vee
125 -oNC
126
--0 SO
127 -----OGND
128 ---ONC
179 -ONe
130 -'-OCi\~!J
CilS,
131
132
POt
133
Vee
134
NC
135
NC
136
1/048
137
1/049
138
GND
139
1/050
140
1/051
141
1/052
142
1/053
143
Vee
144
1/054
145
NC
146
NC
147
NC
148
NC
149
1/055
-150
NC
151
1/056
152
GND
153
1/057
154
1/058
155
1/0 59
156
1/060
157
Vee
158
1/061
159
1/062
160
1/063
161
NC
162
GND
163
PD2
164
PD4
165
PD6
166
POS
167
1Dl
168
Vee
0
V",
1/036
1/037
1/038
1/039
Vee
218
GND
1/00
1/01
I/O 2
1/03
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Vee
PD and ID Table
wEiioCAsli O-~ 28
CA~~ O-~
29
30
31
GN[lO ---- 32
ACIO --~ 33
A1 () - --~ 34
RASCI 0
at!) 0
--~
--~
A.\ 0
AI; ()
.. 35
~ 36
All ()
N!' n-Nt. ()
.. 37
Ve, ()
--
38
39
40
J.l1.()
Nt:
Access Time
Pin
Name
Pin
No.
60 ns
70 ns
PD1
79
L
L
L
PD2
163
L
L
L
80 ns
PD3
80
H
H
H
PD4
164
L
L
L
PD5
81
L
L
L
PD6
165
H
L
H
PD7
82
H
H
L
(1-
GNI) ()
or? ()
litiS? ()Ci'iS40
CA~t;O
W"~O
PD8
166
H
H
H
IDO
83
GND
GND
GND
101
167
GND
GND
GND
V(! 0
NC
NC
I/O 16
I/O 17
GND
I/O 18
I/O 19
1/020
1/021
Remark H :
VOH,
L:
VOL
Vee
1/022
NC
NC
NC
NC
1/023
NC
1/024
GND
1/025
1/026
1/027
1/028
AD - A9, BO
: Address Inputs
I/O 0 - I/O 63 : Data Inputs/Outputs
---RASO, RAS2 : Row Address Strobe
Vee
1/029
1/030
1/031
NC
GND
PDl
PD3
PD5
PD7
1DO
Vee
0
CASO - CAS7:
--WED, WE2
--OEO,OE2
Column Address Strobe
Write Enable
Output Enable
PDE
Presence Detect Enable
PDl - PDB
Presence Detect Pins
IDO, 101
Identity Pins
Vee
GND
Power Supply
Ground
NC
No connection
NEe
MC-421000AA64FB
Block Diagram
RAS20-----------,
RASO
OEO
WEO
CASO
r
1/
LCAS
1/01
I/O 2
1/02
1/03
1/04
1/05
1/03
1/06
~
1/
CAS1
RAS WE OE
1/01
1/04
1/05
1/06
1/07
DO
1/08
CAS5
UCAS
1/08
1/09
I/O 16
I/O 15
I/O 41
I/O 15
I/O 10
I/O 14
1/042
I/O 14
I/O 11
I/O 12
I/O 13
I/O 12
1/043
1/044
I/O 12
I/O 13
I/O 11
1/045
1/011
I/O 14
I/O 15
I/O 10
1/046
I/O 10
1/09
1/047
1/09
CAS2
r
LCAS
I/O
1/01
I/O 17
I/O 18
1/03
I/O 19
1/04
I/O 20
I/O 21
1/05
I/O 22
I/O
CAS3
~
I/O 24
I/O 25
RAS WE OE
1/02
1/06
1/07
1/08
03
01
UCAS
1/016
I/O 15
I/O 26
I/O 27
I/O 14
I/O 28
I/O 29
I/O 12
I/O 30
I/O 31
I/O 10
I/O 13
I/O 11
1/09
0--{>----- AO : 00, 01
BO 0--{>----- AO : 02, 03
A 1 - A9 0--{>----- 00 - 03
AO
POE~
POl - P08
~ Vee or GNO
100, 101 0 1 - - - - - NC or GNO
Vee
o>---::1:---+-'
GNOO
Remark
I/O 13
00 - 03 : tLP04218160
=r CO-C3.
00-03
00-03
219
NEe
MC-421000AA64FB
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Parameter
Condition
Symbol
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
mA
Power dissipation
Po
6
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
TS1g
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Condition
MIN.
TYP.
MAX.
·Unit
4.75
5.0
5.25
V
2.4
Vee + 1.0
V
-1.0
+0.8
V
70
'C
Vee
High level input voltage
VIH
Low level input voltage
VIL
Operating ambient temperature
TA
0
--
Capacitance ITA
=25 'C. f =1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
220
Symbol
Supply voltage
Symbol
Test Condition
MAX.
Unit
CI1
AD - AS, BO
MIN.
TYP.
20
pF
CI2
WED, WE2
20
CI3
RASO, RAS2
45
CI.
CASO - CAS7
20
CIS
OEO,OE2
20
CliO
1/00 -1/063
20
pF
NEe
MC-421000AA64FB
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Iccl
Test condition
MAX.
Unit
Notes
RAS, CAS Cycling
tAAC = 60 ns
700
mA
3,4,7
tAC = tAC IMIN.)
tAAC = 70 ns
660
tAAC = 80 ns
620
---RAS, CAS ~ V,H IMIN.)
10 = 0 mA
68
RAS, CAS ~ Vcc - 0.2 V
10 = 0 mA
64
RAS Cycling
CAS ~ V,H IMIN.)
tAC = tAC IMIN.)
tAAC = 60 ns
700
tRAC = 70 ns
660
10= 0 mA
tAAC = 80 ns
620
RAS 5 VIL IMAX.), CAS Cycling
tAAC = 60 ns
420
tpc = tpc IMIN.)
tRAC = 70 ns
380
tRAC = 80 ns
340
10 = 0 mA
Standby current
RAS only refresh current
Operating current
Icc2
Icc3
Icc.
(Fast page mode)
10 = 0 mA
CAS before RAS
Iccs
refresh cu rrent
RAS Cycling
tRAC = 60 ns
700
tRC = tRC IMIN.)
tRAC
= 70 ns
tRAC = 80 nn
660
10 = 0 mA
Input leakage current
I'IL)
V, = 0 to 5.5 V
All other pins not under test
Output leakage current
lOlL)
MIN.
Va = 0 to 5.5 V
IRAS
= 0 V IOthers
mA
mA
3,4,5,7
rnA
3,4,6
mA
3,4
620
-10
+10
-5
+1
-10
+10
!lA
!lA
Output is disabled (Hi-Z)
High level output voltage
VOH
10 = -2.5 mA
Low level output voltage
VOL
10 = +2.1 mA
2.4
V
0.4
V
221
NEe
MC-421000AA64FB
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
Symbol
tRAe = 60 ns
MIN.
222
MAX.
tRAe = 70 ns
MIN.
MAX.
tRAe = 80 ns
MIN.
Unit
ReadIWrite Cycle Time
tRe
110
130
150
ns
Read Modify Write Cycle Time
tRwe
173
195
215
ns
Fast Page Mode Cycle Time
tpe
40
45
50
ns
Read Modify Write Cycle Time (Fast Page Mode)
tPRwe
85
90
105
Access Time from RAS
tRAe
60
70
Access Time from CAS
teAe
20
25
Access Time Column Address
tAA
35
Access Time from CAS Precharge
tAep
40
Access Time from OE
tOEA
20
RAS to Column Address Delay Time
tRAD
15
30
15
Notes
MAX.
ns
80
ns
10, 11
25
ns
10, 11
40
45
ns
10, 11
45
50
ns
11
25
25
ns
11
40
ns
10
11
35
17
CAS to Data Setup Time
teLZ
0
0
0
ns
OE to Data Setup Time
tOlZ
0
0
0
ns
11
Output Buffer Turn-off Delay Time from CAS
tOFF
0
ns
12
OE to Data Delay Time
tOED
13
Output Buffer Turn-off Delay Time from OE
tOEZ
0
OE Hold Time
tOEtI
0
13
0
15
15
13
0
0
15
15
15
0
0
ns
15
0
ns
12
ns
OE Lead Time Referenced to RAS
tOES
0
Transition Time (Rise and Fall)
tT
3
RAS Precharge Time
tRP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
tRSH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tesH
60
RAS to CAS Delay Time
tReD
20
ns
10
CAS to RAS Precharge Time
teRP
5
5
5
ns
13
CAS Precharge Time
tePN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tep
10
10
10
ns
RAS Precharge CAS Hold Time
tRPe
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHep
40
45
50
ns
Row Address Setup Time
tASR
5
5
5
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tAse
0
0
0
ns
Column Address Hold Time
teAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAl
30
35
40
ns
Read Command Setup Time
tRes
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tReH
0
0
0
ns
14
WE Hold Time Referenced to CAS
tweH
10
10
15
ns
15
WE Pulse Width
twp
10
10
15
ns
15
0
50
3
0
50
10,000
20
ns
10,000
80
70
45
20
50
25
ns
ns
20
18
20
ns
50
60
50
10,000
3
ns
ns
60
NEe
MC-421000AA64FB
Symbol
Parameter
tAAC = 60 ns
MIN.
MAX.
tAAC = 70 ns
MIN.
MAX.
tAAC = 80 ns
MIN.
Unit
Notes
MAX.
Data-in Setup Time
tDS
0
0
'0
ns
16
Data-in Hold Time
tOH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS to WE Delay Time
tCWD
38
40
45
ns
17
RAS to WE Delay Time
tAWD
93
105
115
ns
17
CAS Precharge to WE Delay Time
tCPWD
60
65
70
ns
17
Column Address to WE Delay Time
tAWD
58
65
70
ns
17
WE Lead Time Referenced to RAS
tAWL
25
25
25
ns
WE Lead Time Referenced to CAS
tCWL
15
15
15
ns
CAS Setup Time (CAS before RAS Refresh)
tCSA
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
teHA
10
10
15
ns
WE Hold Time
tWHA
15
15
15
ns
Refresh Time
tAEF
16
16
16
ms
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. Iccl, icC3, icC4 and iccs depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. icC3 is measured assuming that all column address inputs are held at either high or low.
6. icC4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. icCl and Icc3 are measured assuming that address can be changed once or less durinn RAS::;
(MAX.I
and CAS?
VIL
VIH (MIN.I.
S. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H
IMIN I
= 2.4 V
VIL
(MAX)
= 0.8 V
.----------~-----,,
,
I
______________
,,
,
,,
II
II
::
•
tT
= 5 ns
,
,
: ::«
Jr,
tT = 5 ns
(2) Output timing specification
VaH
IMIN I
= 2.4 V
VOL
(MAXI
= 0.4 V
223
NEe
MC-421000AA64FB
10. For read cycles. access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD S tRAD IMAX.I and tRCD S tRCD IMAX.I
tRACIMAX.1
tRACIMAX.1
tRAD > tRAD IMAX.I and tRCD S tRCD IMAX.I
tMIMAX.1
tRAD + tAA IMAX.I
tRCD > tRCD IMAX.I
tCACIMAX.1
tRCD + tCAC IMAX.I
tRAO(MAX.! and tRCO(MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC. tAA or tCAC) is to be used for
finding out when output data will be available. Therefore. the input conditions tRAD -------+-----,
WEO
WE2
1/01
1/02
1/03
1/04
1/05
I/O 6
I/O 7
1/03
1/04
1/05
1/06
1/07
1/08
UCAS
1/016
1/015
1/014
1/013
1/012
1/011
1/010
1/09
I/O 8
1/09
1/010
1/011
1/012
1/013
1/014
1/015
DO
1/023
1/052
1/053
1/054
1/055
1/056
1/057
1/058
1/059
1/024
1/025
1/026
1/027
1/028
1/029
1/030
1/031
1/060
1/061
1/062
1/063
1/064
1/065
1/066
1/067
1/01
1/02
1/016
1/017
1/018
1/019
1/020
1/021
1/022
1/03
1/04
1/05
1/06
1/032o--~
1/068
1/033
1/069
1/070
1/071
1/034
1/035
AO
BO
A 1 - A9
PDE~
POl - PD8 ~ Vee or GNO
o----t>-- AO : DO - D2
o----t>-- AO : D3 - 05
o----t>-- 00 - D5
Remark 00, 01, 03, 04: JLP04218160
1/016
1/015
1/014
1/013
1/012
1/011
100. 101 0
Vee 0
GNO 0
02,05: JLP0424400
NC or GNO
:t: CO _ C5 • 00 - 05
T
• 00-05
229
NEe
MC-421000AD72F
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Symbol
Parameter
Condition
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
mA
Power dissipation
Po
8
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
Tstg
-55 to + 125
:C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthisspecification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
MIN.
TYP.
4.75
5.0
MAX.
Unit
Supply voltage
Vee
5.25
V
High level input voltage
V,H
2.4
Vee + 1.0
V
Low level input voltage
V,L
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
'C
MAX.
Unit
20
pF
Capacitance ITA
-
=25 ·c, f =1 MHz)
Parameter
Input capacitance
Symbol
Data Input/Output capacitance
Test Condition
MIN.
TYP.
C"
AO· A9, BO
Cil
WEO. WE2
20
RASO,RAS2
36
C"
r---CII
230
Condition
CASO.CAS4
20
Ct!l
OEO.OE2
20
CliO
1/00 -1/071
20
pF
NEe
MC-421000AD72F
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Iccl
Test condition
RAS, CAS Cycling
tRC = tRC IMIN.!
10 =
Standby current
RAS only refresh current
Icc,
Icc3
a mA
Icc4
(Fast page mode)
Icc5
refresh current
3,4,7
tRAC = 70 ns
860
tRAC = 80 ns
800
a mA
a mA
RAS Cycling
CAS ~ V,H 1M IN.!
tRAC = 60 ns
940
tRAC = 70 ns
860
tRAC = 80 ns
800
RAS S VILIMAX.I, CAS Cyciino
tliAC = 60 ns
600
tpc = tpc IMIN.!
tlll\C ;.::
70 n:i
540
a mA
--
RAS Cycling
V, =
a mA
a to 5.5 V
11I/.e
--
' '/0
til,\(:
. BO "';
liAS
lOlL!
Va =
a to 5.5 V
mA
3,4,6
480
940
-860
-_
.
11,;
I
3,4,5,7
- - - - .. . -
GO "';
tlt,\!:
mA
.----~
·80 "';
tll.\[
mA
66
tRC = tRC IMIN.!
10= mA
All other pins not under test ~ _0 V (1111)1 ,;
Output leakage current
72
10 =
tRC = tRC IMIN.!
II III
Notes
mA
10 =
10 =
Input leakage current
Unit
940
RAS, CAS ~ V,H IMIN.!
10 =
CAS befo re RAS
MAX.
RAS, CAS ~ Vcc - 0.2 V
a
Operating current
MIN.
tRAC = 60 ns
800
-10
I'
.J
-·10
+10
---
III A
3, 4
'- -"-'I/A
+1
+10
pA
Output is disabled (Hi-Z)
High level output voltage
VOH
10 = -2.5 mA
Low level output voltage
VOL
10 = +2.1 mA
2.4
V
0.4
V
231
NEe
MC-421000AD72F
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
Symbol
tRAC = 60 ns
MIN.
232
MAX.
tRAC = 70 ns
MIN.
MAX.
tRAC = 80 ns
MIN.
Unit
Notes
MAX.
Read/Write Cycle Time
tRC
110
130
160
Read Modify Write Cycle Time
tRWC
173
195
225
ns
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Read Modify Write Cycle Time (Fast Page Mode)
tPRWC
85
90
105
ns
Access Time from RAS
tRAC
Access Time from CAS
Access Time Column Address
60
70
80
ns
10, 11
tCAC
20
25
25
ns
10, 11
tAA
35
40
45
ns
10, 11
Access Time from CAS Precharge
tACP
40
45
50
ns
11
Access Time from OE
tOEA
20
25
25
ns
11
40
RAS to Column Address Delay Time
tRAD
15
ns
10
CAS to Data Setup Time
tClZ
0
0
0
ns
11
OE to Data Setup Time
tOlZ
0
0
0
ns
11
Output Buffer Turn·off Delay Time from CAS
tOFF
0
ns
12
OE to Data Delay Time
tOED
15
Output Buffer Turn·off Delay Time from OE
tOEZ
0
OE Hold Time
tOEH
0
OE Lead Time Referenced to RAS
tOES
0
Transition Time (Rise and Fall)
tr
3
RAS Precharge Time
tRP
40
RAS Pulse Width
tRAS
RAS Pulse Width (Fast Page Mode)
30
15
15
0
35
15
15
15
0
17
0
20
20
15
0
0
ns
20
0
0
ns
50
3
60
10,000
,70
10,000
80
10,000
ns
tRASP
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
tRSH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tACO
20
ns
10
CAS to RAS Precharge Time
tCAP
10
10
10
ns
13
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
10
10
10
ns
RAS Hold Time from CAS Precharge
tRHCP
40
45
50
ns
Row Address Setup Time
tASR
5
5
5
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAl
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
10
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
tWCH
15
15
15
ns
15
WE Pulse Width
twp
10
10
15
ns
15
50
20
10,000
20
20
ns
10,000
25
ns
ns
80
50
ns
ns
20
70
45
'50
70
20
10,000
3
12
ns
0
50
ns
60
NEe
MC-421000AD72F
Parameter
tRAe = 60 ns
Symbol
MIN.
MAX.
tRAe = 70 ns
MIN.
MAX.
tRAe = 80 ns
MIN.
Unit
Notes
MAX.
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tDH
10
15
15
ns
16
Write Command Setup Time
twes
0
0
0
ns
17
CAS to WE Delay Time
tewD
38
40
45
ns
17
RAS to WE Delay Time
tRWD
93
105
115
ns
17
CAS Precharge to WE Delay Time
tePWD
60
65
70
ns
17
Column Address to WE Delay Time
tAWD
58
65
70
ns
17
WE Lead Time Referenced to RAS
tRWL
25
25
25
ns
WE Lead Time Referenced to CAS
tewL
15
15
15
ns
CAS Setup Time (CAS before RAS Refresh)
tesR
10
10
10
ns
CAS Hold Time ICAS before RAS Refresh)
teH"
10
10
10
ns
WE Setup Time
tWSR
10
10
10
ns
WE Hold Time
tWHR
15
15
15
ns
Refresh Time
tREF
16
16
16
ms
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 J.lS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. ICC1, IcC3, Icc4 and Iccs depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. IcC4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. IcCl and IcC3 are measured assuming that address can be changed once or less during RAS::;
IMAX.) and CAS <': VIH (MIN.).
VIL
8. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H IMIN.) = 2.4 V
V,L
IMAX)
=0.8 V
.----------~-----,ii,
______________
I
I
,
I
,
1
I
1
I
~
tT = 5 ns
I
I
I
-+-f+tT
=5 ns
(2) Output timing specification
VOH
IMIN I
= 2.4 V
VOL
IMAXI
= 0.4 V
:::::::~I...---.-J}-233
NEe
MC-421000AD72F
10. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAO
=:;
tRAD (MAX.1
and
tACO
s: tRCD (MAX.)
tRAC (MAX,)
tRAC (MAX.)
tRAD
>
tRAD (MAX.)
and
tACO
S tRCD (MAK)
tAA (MAX.)
tRAD + tAA (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRCD > tRCD (MAX.)
tRAD IMAX.) and tRCD IMAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data wi" be available. Therefore, the input conditions tRAD ~ tRAD IMAX.)
and tRCD
~
tRCD IMAX.) wi" not cause any operation problems.
11. Loading conditions are 1 TTL and 100 pF.
12. tOFF IMAX.) and tOEZ IMAX.) define the time at which the output achieves the condition of Hi-Z and
are not referenced to VOH or VOL.
13. tcnp IMIN.) requirements should be applied to RAS/CAS cycles.
14. Either tRCH IMIN.) or tHHIl (MIN.) should be met in read cycles.
15. tWPIM)N.) is applied to l-!-T
K
1--:-o+r---tGo:+----C -- o
E
------
detail of ® part
detail of @ part
W
1t
{C1JII
>
X
G
0
ITEM
A
MILLIMETERS
INCHES
133.35:1:0.13
5.25:1:0.006
B
11.43
0.450
C
0
E
36.83
6.35
0.250
54.61
2.150
G
6.35
0.250
H
I
1.27 (T.P.)
8.89
0.050 (T.P.)
0.350
0.925
1.450
J
23.495
K
42.18
1.661
L
17.78
0.700
M
25.4
1.000
N
p
4.0 MAX.
0.158 MAX.
1.0
0.039
a
R 2.0
R 0.079
R
4.0:1:0.1
0-157~8:88~
5
fl3.0
1'>0.118
T
U
V
W
1.27:1:0.1
4.0 MIN.
0.05:1:0.004
0.157 MIN.
0.25 MAX.
0.010 MAX.
1.0:1:0.05
X
2.54
0.039:1:0.002
0.100
Y
3.0 MIN.
0.118MIN.
Z
3.0 MIN.
0.118MIN.
M168S-50A4
236
PRELIMINARY DATA SHEET
~EC
MOS INTEGRATED CIRCUIT
MC . . 422000AA64FB
2M -WORD BY 64-BIT DYNAMIC RAM MODULE
FAST PAGE MODE
Description
The MC-422000AA64FB is a 2 097 152 words by 64 bits dynamic RAM module on
which 8 pieces of 16M DRAM ( J.l.PD 4218160) are assembled.
This module provide high density and large quantities of memory in a small space
without utilizing the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
- 2 097 152 words by 64 bits organization
- Fast access and cycle time
Power consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
MC- 422000AA64-60
60ns
110ns
3.74w
MC- 422000AA64-70
70ns
130ns
3.53 w
Family
MC- 422000AA64-80
BOns
150ns
Active
3.32 w
Standby
378mW
(CMOS level)
- 1 024 refresh cycles/16 ms
- CAS before RAS refresh, RAS only refresh, Hidden refresh.
- 16B-pin dual in-line memory module (pin pitch
=1.27 mm)
- Single +S.OV±O.2SV power supply
D·3612A (Japan)
The information in this document is subject to change without notice.
237
MC-422000AA64FB
Ordering information
Part Number
Package
MG- 422000AA64FB-70
60ns
70ns
16B-pin Dual In-line
Memory Module
MG- 422000AA64FB-80
BOns
Edge connector: Gold plating
MG- 422000AA64FB-60
23B
Access time
(MAX.)
(Socket Type)
Mounted devices
8 pieces of
uPD 4218160LE
(400mil SOJ)
[Single side]
MC-422000AA64FB
Pin Configuration
1GB-pin Dual In-line Memory Module Socket Type (Edge Connector: Gold plating)
0
0
GND
1/032
1/033
1/034
1/035
Vee
Vee
1/036
1/037
1/038
1/039
V04
V05
V06
V07
NC
GND
1/040
1/041
1/042
11043
11044
NC
GND
VOS
V09
VO 10
VO 11
VO 12
Vee
Vee
1/045
1/046
1/047
NC
GND
NC
NC
VO 13
VO 14
VO 15
NC
GND
NC
NC
Vee
NC
CAsii
riAS1
~
GND
NC
GND
AI
A3
A5
A7
A9
NC
NC
Vee
0
Vee
m
CAs'i
~
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
156
159
160
161
162
163
164
165
166
167
168
GND
VOO
VO 1
V02
V03
NC
80
GND
NL
RAS3
CAs5
e;w
~
Vee
NC
NC
1/048
1/049
GND
1/050
1/051
1/052
1/053
Vee
1/054
NC
NC
NC
NC
1/055
NC
11056
GND
1/057
1/056
1/059
1/060
Vee
1/061
1/062
11063
NC
GND
PD2
PD4
PD6
PDS
IDI
Vee
~
AO
A2
A4
PO and 10 Table
A6
A8
NC
NC
Vee
NC
NC
GND
QE2...
RAS2
CAs4
~
~
Vee
NC
NC
VO 16
VO 17
GND
VO 18
VO 19
V020
V021
Vee
V022
NC
NC
NC
NC
V023
NC
V024
GND
V025
V026
V027
V028
Vee
V029
V030
V031
NC
GND
POI
PD3
PD5
PD7
IDO
Vee
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
ACCS8SS
Time
Pin
Name
Pin
No.
60ns
70ns
SOns
POI
79
H
H
H
PD2
163
L
L
L
PD3
60
H
H
H
PD4
PD5
154
L
L
L
L
L
L
PD6
165
H
S2
PDS
166
H
H
H
L
PD7
H
H
H
81
L
I DO
83
GND
GND
GND
I Dl
167
GND
GND
GND
Note) H: VOH, L: VOL
AO - A9 , 80 : Address Inputs
VO 0-11063 : Data In puIs I Outputs
RASO-RAS3: Row Address Strobe
CASO-CAS7 : Column Address Strobe
WEO,WE2 : Write Enable
OEO,OE2 : Output Enable
PDE
: Presence Detect Enable
PD1- PDB : Presence Detect Pins
IDD,IDI
: Ident~y pins
: Power Supply
Vee
: Ground
GND
: No connection
NC
77
7S
79
80
81
82
S3
S4
0
239
MC-422000AA64FB
Block Diagram
RASO
RAS2
RASl
RAsa
OEO
OE2
WEO
WE2
CAsii
[CAS RAS WE
1/00
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/0 B
CASl
IIOB
1/09
1/010
1/011
1/012
1/013
1/014
1/015
DO
UCAs
VO 16
VO 14
1/013
1/016
1/015
1/014
1/013
1/012
1/011
VO 10
V09
1/012
1/011
1/010
1/09
FiAS WE i5E
1/016
1/017
1/010
V019
1/020
V021
1/022
V023
01
CAS3
1/024
V025
V026
1/027
V028
1/029
V030
1/031
[CAS RAS WE
1/01
1/02
V03
V04
V05
1/06
1/07
IIOB
UCAs
[CAS
CAS2
i5E
UCAs
UGAS
VO 16
VO 15
1/014
1/016
1/015
1/014
1/013
1/034
V035
1/036
1/037
1/03B
1/039
04
CAS5
1/040
1/041
1/042
1/043
1/044
1/045
1/046
1/047
WE i5E
05
CAS7
0056
0067
1/058
1/059
V060
V061
62
-t>
Al toA9-t>
240
..
AO: 02, 03, 06, 07
.. 001007
1/013
1/016
1/015
1/014
1/013
1/012
1/011
1/010
1/09
1/012
1/011
1/010
V09
[CAS
03
UCAs
1/016
VO 16
VO 15
VO 14
V013
V012
NC or GNO
PoE~
POl
i5E
06
to POB ~Vooor GNO
Vee D:1:
.. 00 10 07
GNOD
T C()'C7 .. 001007
FiAS WE OE
07
UCAs
va
va 63
100 to 101 D
VOl
V02
V03
1/04
V05
1/06
1/07
IIOB
UCAS
V04B
0049
V050
V051
0052
0053
1/054
1/055
AO -t>--."~AO: 00, 01, 04, 05
80
02
CASB
V012
VO 11
1/010
V09
V09
(CAS RAS WE
CAS4
1/032
1/033
[CAs RAS
1/01
1/02
1/03
1/04
1/05
1/06
1/07
IIOB
i5E
MC-422000AA64FB
ABSOLUTE MAXIMUM RATINGS
Parameter
Remark
Symbol
Condition
Rating
Unit
V
Voltage on Any Pin Relative to GND
VT
-1.0 to +7.0
Supply voltage
vee
-1.0 to +7.0
Output current
10
V
50
rnA
Power dissipation
PD
10
W
Operating temperature
Topt
Oto+70
Storage temperature
Tstg
-55 to +125
'C
'C
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device in not meant to be operated under conditions outside the limits
described in the operational sections of this specification. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
(NOTES : 1 , 2)
MIN.
TYP.
5.0
MAX.
Unit
5.25
V
Vcc+ 1.0
V
Supply voltage
vee
4.75
High level input voltage
VIH
2.4
Low level input voltage
VIL
-1.0
+0.8
V
Ta
0
70
'C
MAX.
Unit
Ambient temperature
CAPACITANCE (Ta=2SoC ,f=1 MHz)
Parameter
Input capacitance
Data Input!
Output capacitance
Symbol
Test condition
MIN.
TYP.
CI1
AO-A9, BO
20
pF
C 12
WE 0, WE2
20
pF
C 13
RASO- RAS 3
45
pF
C 14
--CASO-CAS7
20
pF
C 15
OEO,OE2
20
pF
C I/O
1100 - 110 63
20
pF
241
MC-422000AA64F
DC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
PARAMETER
TEST CONDmON
SYMBOL
--RAS , CAS Cycling
Operating Current
Standby Current
-RAS only refresh current
led
tRc=tRc (MIN.) , IO=OrnA
Iec2
1ec3
Operating Current
(Fast Page Mode)
Icc4
IceS
refresh current
Input Leakage Current
Output Lcakage Current
MAX.
lRAc=6Ons
712
lRAc=7Ons
672
lRAc=8Ons
632
RAS , CAS
~
Vrn (MIN.)
80
RAS , CAS
~
Vcc-0.2V
72
--RAS Cycling, CAS
~
Vrn
lRAc=6Ons
712
lRAc=7Ons
672
fRc=fRc(MIN.),IO=OrnA
lRAc=8Ons
-RAS
632
lRAc=6Ons
432
lRAc=7Ons
392
-~ VIL , CAS Cycling
tpC=tpc MIN. , 1O=OmA
--CAS before RAS
MIN.
tRc=fRC(MIN.)
IO=OrnA
tRAc=8Ons
352
lRAc=6Ons
712
lRAc=7Ons
lRAc=8Ons
672
Vl=Oto 5.5V
-RAS
all other pins not under test = OV
others
NOTES
rnA
3,4,7
rnA
rnA
3,4,7
rnA
3,4,6
rnA
3,4
632
-10
+10
-5
+1
-10
+10
II(L)
Io( l)
UNIT
~A
Outputs are disabled (Hi - Z)
~A
VO=Oto 5.5V
242
High level output voltage
VOl!
IO=-5rnA
Low level output voltage
VOl.
IO=+4.2rnA
2.4
V
0.4
V
MC-422000AA64FB
AC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Notes 8,9
(1/2)
tRAC= 60ns
PARAMETER
tRAC= 70ns
tRAC= 80ns
UNIT NOTES
SYMBOL
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Random Read or Write Cycle Time
tRC
110
-
130
-
150
-
ns
Read Modify Write Cycle Time
tRWC
173
195
-
215
-
ns
45
-
50
-
ns
Fast Page Mode Cycle Time (Read or Wlite)
tPC
40
Read Modify Write Cycle Time (Fast Page Mode)
tPRWC
85
-
90
-
105
-
ns
Access Time from RAS
tRAC
-
60
-
70
80
ns
10,11
Access Time from CAS
tCAC
-
20
-
25
-
25
ns
10,11
Access Time from Column Address
tAA
-
35
-
40
-
45
ns
10,11
Access Time from CAS Precharge
tACP
-
40
45
-
50
ns
11
Access Time from OE
tOEA
-
20
-
25
-
11
tRAD
15
30
15
.15
17
25
,10
ns
RAS to Column Address Delay Time
liS
10
CAS to Data Setup Time
tCU
0
-
()
()
liS
11
OE to Data Setup Time
tOU
0
()
0
-
IlS
II
Output Buffer Turn-off Delay Time(CAS)
tOFF
0
t:I
()
0
15
IlS
12
OE to Data Delay Time
tOED
13
-
15
15
-
ns
Output Buffer Turn-off Delay Time(OE)
tOEZ
0
13
0
15
0
15
ns
OE Command Hold Time
tOEH
0
-
0
-
0
ns
ns
I)
OE to RAS inactive Setup Time
tOES
0
-
0
-
0
-
Transition Time ( Rise and Fall )
tT
3
50
3
50
3
50
ns
RAS Precharl!:e Time
tRP
40
-
0;0
-
....6{l
-
...M.
RAS Pulse Width( Random Rcad Write Cvcle)
tRAS
60
10000
70
10000
80
10000
ns
RAS Pulse Width ( Fast Pal'c Mode)
tRASP
1i0 1120;000
70 125000
RO
125000
ns
RAS Hold Time
tRSH
15
-
18
-
20
-
ns
CAS Pulse Width
tCAS
10;
10000
20
10000
20
10000
ns
CAS Hold Time
tCSH
60
-
70
-
80
-
ns
20
45
...20..
5.0.
--.2.i
....6Q.
12
...ns. L1O.
RAS to CAS Delav Time
tRCD
CAS to RAS Precharge Time
tCRP
5
-
5
-
5
CAS Precharge Time
tCPN
10
-
10
-
10
CAS Precharge Time(Fast Page Mode)
tCP
10
-
10
-
10
RAS Prechar!!e CAS Hold Time
tRPC
5
5
-
5
RAS Hold Time from CAS Precharge
tRHCP
40
-
-
45
-
50
-
ns
Row Address Set Up Time
tASR
5
-
5
-
5
ns
-
12
-
0
-
ns
ns
13
ns
ns
ns
Row Address Hold Time
tRAH
10
-
10
Column Address Set Up Time
tASC
0
-
0
Column Address Hold Time
tCAH
15
-
...l5..
-
...l5..
Column Address Lead Time Referenced to RAS
tRAL
30
-
35
-
40
-
Lead Command Setup Time
tRCS
0
-
..1l.S
tRRH
0
0
-
Jl.
Read Command Hold Time Referenced to RAS
-
Jl.
0
-
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
-
0
-
0
-
ns
14
Write Command Hold Time Referenced to CAS
tWCH
10
-
10
-
15
-
ns
15
ns
...IlS..
ns
243
MC·422000AA64FI
(212
tRAC=6Ons
PARAMETER
tRAC= 70ns
!RAC = 80ns
SYMBOT
UNIT NOTES
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write Com and Set-Up Time
tWP
10
-
10
-
15
-
ms
Data-in Seup Time
lOS
0
-
0
-
0
-
ns
16
Data-in Hold Time
tDH
10
-
15
-
15
-
ns
16
Write Com and Setup Time
tWCS
0
-
0
-
0
-
ns
17
CAS to WE Delay Time
tCWD
38
-
40
-
45
-
ns
17
RAS to WE Delay Time
tRWD
93
-
105
-
115
-
ns
17
65
-
70
-
ns
17
65
-
70
ns
17
15
CAS Precharge Delay Time Referenced to WE (Fast Page Mode) tCPWD
60
Column Address Delay Time Referenced to WE
tAWD
58
Write Command Lead Time Referenced to RAS
tRWL
25
-
25
-
25
-
Write Command Lead Time Referenced to CAS
tCWL
15
-
15
-
15
-
ns
!
CAS Setup Time for CAS before RAS Refresh
tCSR
5
5
-
5
-
ns
!
CAS Hold Time for CAS hcfow RAS Refresh
tCHR
10
-
10
-
10
-
ns
WE Hold Time
tWHR
15
-
15
-
15
-
ns
Refresh Time
tREF
-
16
-
16
-
16
ms
244
ns
,
MC-422000AA64FB
Notes:
1. All voltages are referenced to GND.
2. After power up, wait more than 100 I1s and then, execute eight CAS before RAS or RAS
only refresh cycles as dummy cycles to initialize intemal circuit.
3. Icc1, Icc3, Icc4 and Icc5 depend on cycle rates (tRC and tpc) .
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during
each fast page cycle.
7. Icc1 and Icc3 are measured assuming that address can be changed once or less during
RAS~VIL(MAX.) and CAS~VIH(MIN.).
8. AC measurements assume tr =5ns .
9. AC Characteristics test condition
(1) Input timing specification
VlH (MIN.).2.4V------~---,
,
VlL (MAX.). O.8V- .... --........
:
I
I
~
I
I
tr.5ns
,
!
I
I
~
I
I
tr.5ns
(2) Output timing specification
VOH(MIN.).2.4V-----~
~
r
VOL(MAX.).O.4V-----~' - - _ _oJ
10. For read cycles, access time is defined as follows:
Input Conditions
tRAo ;:;; tRAO(MAX.) and tRCO ;:;; tRCO(MAX.)
Access Time
tRAC(MAX.)
Access Time from RAS
tRAC(MAX.)
tRAD > tRAD(MAX.) and tRCD ;:;; tRCD(MAX.)
IM(MAX.)
tRAD + tAA(MAX.)
tRCD > tRCD(MAX.)
tCAC(MAX.)
tRCD + tCAC(MAX.)
tRAD(MAX.) and tRCD(MAX.) are specified as reference points only ; they are not restrictive
operating perameters. They are used to determine which access time (tRAC. 1M or toAc)
is to be used for finding out when output data will be available. Therefore, the input
conditions
tRAD~tRAD(MAX.)
and
tRCD~tRCD(MAX.)
will not cause any operation problems.
11. Loading conditions are 1 TILs and 100 pF.
12. tOFF(MAX.) defines the time at which the output achieves the condition of Hi-Z and are not
referenced to VOH or VOL.
-- --
13. tCRP(MIN.) requirement should be applied to RAS I CAS cycles.
14. Either tRCH(MIN.) or tRRH(MIN.) should be met in read cycles.
15. twP(MIN.) is applied to late write cycles or read modify write cycles. In ear1y write cycles,
twcH (MIN.) should be met.
16. toS(MIN.) and tDH(MIN.) are referenced to the CAS falling edge in ear1y write cycles. In late
write cycles and read modify cycles, they are referenced to the WE falling edge.
17. If twcs~twcs (MIN.), the cycle is an ear1y write cycle and the data out will remain Hi - Z
through the entire cycle. If
tRWD~tRWD (MIN.) , tCWD~tcwO(MlN.), tAwo~tAWO(MIN.)
and topwo~
tCPWD(MIN.) , the cycle is read modify write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is met, the state of the data out is indeterminate.
245
Timing Chart
Please refer to Timing Chart 8, page 443.
246
MC-422000AA64FB
Package Drawing
UNIT: mm
133.35
127.35
3.000
9.00 max
1.27+0.10
8.89
11.43
36.83
54.61
65.675
85
94
o ITIIIIIIIIl
95
124
125
168
111111111111111/111111111111111
DDoDD
11:1
Detail A
a
a
Detail B
11:1
Detail C
~~Oo
+~
247
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC-422000AB72F
2 M-WORD BY 72-BIT DYNAMIC RAM MODULE
FAST PAGE MODE (ECC)
Description
The MC-422000AB72F is a 2,097,152 words by 72 bits dynamic RAM module on which 9 pieces of 16 M
DRAM: JlPD4217BOO are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 2,097,152 words by 72 bits organization
• Fast access and cycle time
Powor consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-422000AB72-60
60 ns
110 ns
5.53W
MC-422000AB72-70
70 ns
130 ns
5.06W
MC-422000AB72-80
80 ns
150 ns
4.59W
Family
Active
Standby
383mW
(CMOS level input)
• 2,04B refresh cycles/32 ms
• CAS before RAS refresh, RAS only refresh, Hidden refresh
• 16B-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Single +5.0 V ±0.25 V power supply
Ordering Information
Part number
Access time
(MAX.)
MC-422000AB72F-60
60 ns
MC-422000AB72F-70
70 ns
MC-422000AB72F-80
80 ns
C·3S42 (Japan)
Package
Mounted devices
168-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
9 pieces of PPD4217800G5
(400 mil TSOP(II»
[Double side)
The information in this document is subject to changa without notice.
249
NEe
MC-422000AB72F
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
o
0
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
146
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
250
0
GND
1/036
11037
1/038
V039
Vee
11040
11041
11042
1/043
GND
1/00
1/01
1/02
1/03
Vee
1/04
1/05
1/06
1/07
11044
GND
V045
1/046
1/047
11048
11049
Vee
I/O 50
I/O 51
11052
1/053
GND
NC
NC
Vee
--oNC
--oNC
--oNC
NC
NC
GND
A1
A3
A5
A7
A9
NC
NC
Vee
1/08
GND
1/09
110 10
11011
I/O 12
I/O 13
Vee
1/014
I/O 15
1/016
1/017
GND
NC
NC
Vee
NC
BO
GND
NC
NC
NC
NC
~
Vee
NC
NC
V054
1/055
GND
V056
V057
11058
1/059
Vee
1/060
NC
NC
NC
NC
V061
11062
11063
GND
V064
1/065
1/066
1/067
Vee
1/068
1/069
1/070
1/071
GND
PD2
PD4
PD6
PD8
ID1
Vee
PO and 10 Table
WEi
CASO
NC
Access Time
Pin
Name
Pin
No.
60 ns
70 ns
80 ns
PD1
79
H
H
H
PD2
163
L
L
L
A10
NC
Vee
PD3
80
L
L
L
PD4
164
H
H
H
NC
NC
GND
PD5
81
L
L
L
PD6
165
H
L
H
L
R8SQ
OEO
GND
AO
A2
M
A6
AS
on
RAS2
CAS4
PD7
82
H
H
\Nt;>
PD8
166
L
L
L
100
83
GND
GND
GND
101
167
GND
GND
GND
NC
Vee
NC
NC
I/O 18
I/O 19
GND
11020
I/O 21
1/022
1/023
Vee
1/024
NC
NC
NC
NC
1/025
1/026
1/027
GND
110 28
11029
1/030
11031
Vee
11032
11033
V034
V035
GND
PD1
PD3
PD5
PD7
IDO
Vee
Remark H : VOH,
L:
VOL
AO - A10, BO : Address Inputs
I/O a -I/O 71 : Data Inputs/Outputs
RASa, RAS2 : Row Address Strobe
CAS 0, CAS4
Column Address Strobe
WEii, WE2
Write Enable
OEO,OE2
Output Enable
POE
Presence Detect Enable
PD1 - PD8
Presence Detect Pi ns
IDa, 101
Identity Pins
----
Vee
0
GND
Power Supply
Ground
NC
No connection
NEe
MC-422000AB72F
Block Diagram
RASO
OEO
WEO
CASO
RAS2
...
::,....
j
+
1/00 0--------1/01 0--------I/O 2 0--------1/03 0--------1/04 0--------1/05 0--------1/06 0--------1/07 0---------
1/0 8 CAS RAS WE OE
1/08 0--------1/09 0--------1/010 0--------1/011 0--------1/012 0--------1/013 0--------1/014 0--------1/015 0---------
1/0 8 CAS RAS WE OE
1/016 0--------I/O 17 0--------1/018 0--------1/019 0--------1/020 0--------1/021 0--------1/022 0--------1/023 0---------
I/O 8 CAS RAS WE OE
1/07
1/06
1/05
1/04
1/03
1/02
1/01
DO
I
1/07
1/06
1/05
1/04
1/03
1/02
1/01
01
1/07
1/06
1/05
1/04
1/03
1/02
1/01
02
D3
BO
Al-Al0
j
+
1/040 0--------1/041 0--------1/042 0--------1/043 0--------1/044 0--------1/045 0--------1/046 0--------1/047 (}4--~
I/O 1 CAS RAS WE OE
1/02
1/03
1/04
1/05
1/06
1/07
I/OS
05
j
1/048 0 - - ....
1/049 (}4-~
I/O 50 o----~
1/051 0--------1/052 0--------1/053 0--------1/054 0--------1/055 0---------
j
I/O 1 CASRAS WE OE
1/02
1/03
1/04
1/05
1/06
1/07
I/OS
D6
I
1/056 0--------I/O 57 0--------I/O 58 0--------1/059 0--------1/060 0--------1/061 0--------1/062 0--------1/063 0---------
j
1/0 1 CAS RAS WE OE
1/02
1/03
1/04
1/05
1/06
1/07
I/OS
D7
I
j
1/064 0--------1/065 0--------1/066 0--------1/067 0--------1/068 0--------1/069 0--------1/070 0--------1/071 0---------
110 1 CAS RAS WE OE
I/O 2
1/03
1/04
1/05
1/06
1/07
I/OS
D8
I
I
1/032 0--------1/033 0--------1/034 0--------1/035 0--------1/036 0--------1/037 0--------1/038 0--------1/039 0---------
....
I
1/0 S CAS RAS WE OE
1/07
1/06
1/05
1/04
1/03
I/O 2
1/01
WE2
CAS4
I
I
1/024 0--------1/025 0--------1/026 0--------1/027 0--------1/028 0--------1/029 0--------1/030 0--------1/031 0---------
::::
::::
I
1
AO
...
OE2
::::
1/0 8 CAS RAS WE OE
1/07
1/06
1/05
1/04
1/03
1/02
1/01
Dol
o--J>-- AO : DO - D4
o--J>-- AO : D5 - DS
o--J>-- DO-DS
Remark DO - 08: }LP04217800
PDE
PDl - PD8
IDO. IDl
e>----;..
o------
tRCD
> tRCD (MAX.)
tRAD (MAX.I and tRCD 5 tRCD (MAX.I
Access Time
Access Time from'RAS
tRAC(MAX.1
tRAC (MAX.I
tAA(MAX.1
tRAD
+ tAA (MAX.I
tCAC(MAX.1
tRCD
+ tCAC (MAX.I
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAD <:: tRAD (MAX.)
and tRCD <:: tRCD (MAX.) will not cause any operation problems.
11. Loading conditions are 2 TTLs and 100 pF.
12. tOFF (MAX.) and tOEZ (MAX.) define the time at which the output achieves the condition of Hi-Z and
are not referenced to VOH or VOL.
13. tCRP (MIN.) requirements should be applied to RAS/CAS cycles.
14. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
15. twP(MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH(MIN.)
should be met.
16. tDS (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write
cycles and read modify cycles, they are referenced to the WE falling edge.
17. If twcs;;: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWD <:: tRWD (MIN.), tCWD <:: tCWD(MIN.), tAWD <:: tAWD (MIN.) and tCPWD <:: tCPWD (MIN.), the cycle
is read modify write cycle and the data out will contain data read from the selected cell. If neither
of the above conditions is met, the state of the data out is indeterminate.
256
Timing Chart
Please refer to Timing Chart 7, page 429.
257
NEe
MC-422000AB72F
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A
a:
s
- I-Y
z-
F-'OrO
(OPTIONAL HOLES) t&. rrrrrnf, ,
iM
J
0
v-9--
00 G
0
---
0
~
-[]]
I-
K
I~G
C
0
E
~ ITU""""''''''Ei''''''''U~'''''''''''''''jj''''''jj ~
detail of ® part
detail of @ part
W
1t
~=H
G
ITEM
A
B
C
1t
0
0
E
G
H
J
K
L
M
N
P
Q
INCHES
5.25:1:0.006
0.450
1.450
0.250
2.150
0.250
0.050 (T.P.)
0.350
0.925
1.661
0.700
1.000
0.158 MAX.
0.039
AO.079
A
4.0:1:0.1
0.157~8:88~
s
U
1/13.0
1.27:1:0.1
4.0 MIN.
V
0.25 MAX.
1/10.118
0.05:1:0.004
0.157 MIN.
0.010 MAX.
W
1.0:1:0.05
0.039 ~8:88~
X
2.54
Y
Z
3.0MIN.
3.0MIN.
T
258
MILLIMETERS
133.35:1:0.13
11.43
36.83
6.35
54.61
6.35
1.27 (T.P.)
8.89
23.495
42.18
17.78
25.4
4.0 MAX.
1.0
A2.0
0.100
0.118 MIN.
0.118 MIN.
MI88S-50A8
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC .. 422000LAB72F
3.3 V OPERATION 2 M-WORD BY 72-BIT DYNAMIC RAM MODULE
FAST PAGE MODE (ECC)
Description
The MC-422000LAB72F is a 2,097,152 words by 72 bits dynamic RAM module on which 9 pieces of 16 M
DRAM: IlPD4217800L are assembled.
This module provides high density and large quantities of memory in
il
Slllilll sj1i1ce without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for nob! II)duction.
Features
• 2,097,152 words by 72 bits organization
• Fast access and cycle time
Power consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-422000LAB72·A60
60 ns
110 ns
3.2BW
MC-422000LAB72-A70
70 ns
130 ns
2.95W
MC-422000LAB72-ABO
BO ns
150 ns
2.63W
Family
Active
Standby
147.6 mW
(CMOS level input)
• 2,048 refresh cycles/32 ms
• CAS before RAS refresh, RAS only refresh, Hidden refresh
•
168-pin dual in-line memory module (pin pitch = 1.27 mm)
• Single +3.3 V ±0.3 V power supply
Ordering Information
Part number
Access time
(MAX.)
MC-422000LAB72F-A60
60 ns
MC-422000LAB72F-A70
70 ns
MC-422000LAB72F-ABO
BO ns
1110343EJ5VODSOO (Japan)
Mounted devices
Package
16B-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
9 pieces of
IlPD4217BOOLG5
(400 mil TSOP(II))
[Double side]
The information in this document is subject to change without notice.
259
NEe
MC-422000LAB72F
Pin Configuration
1GB-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
0
0
GND
11036
11037
11038
11039
GND
1100
1101
1102
1103
1/040
11041
1/042
11043
1104
1/05
1/06
1107
Vee
Vee
11044
GND
1/045
11046
11047
~-..o 1/048
~-~O 11049
- 0 Vcr.
-~Ol/050
~OI/()!)l
·0110 !,?
OI/O!,:1
GNIJ
NC
NC
PD and ID Table
Vee
NC
NC
NC
NC
NC
GND
Al
A3
A5
A7
A9
NC
NC
Vee
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
260
0
NC
80
GND
NC
NC
NC
NC
POE
Vee
NCO-NCO----GNDO-0120r{/\-S-;! 0
Cl\SIi 0-- ~
NC 0
We2 O--~
VrcO--NCONCO1/0 180~-~
..
~
NC
NC
I/O 54
1/055
GND
1/056
11057
11058
11059
GND
1/020
I/O 21
1/022
1/023
11060
NC
NC
NC
NC
11061
1/062
11063
GND
11064
11065
11066
1/067
1/024
NC
NC
NC
NC
I/O 25
I/O 26
11027
GND
1/028
1/029
11030
1/031
11068
11069
11070
1/071
GND
PD2
PD4
PD6
PD8
IDl
1/032
I/O 33
1/034
1/035
GND
PDl
PD3
PD5
PD7
IDO
Vee
Vee
Vee
1/019~-~
Vee
Vee
Vee
41
4/
4:1
44
~~
40
'Il
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Access Time
Pin
Name
Pin
No.
60 ns
70 ns
80 ns
PDl
79
H
H
H
PD2
163
L
L
L
PD3
80
L
L
L
PD4
164
H
H
H
PD5
81
L
L
L
PD6
165
H
L
H
PD7
82
H
H
L
PDB
166
L
L
L
IDO
83
GND
GND
GND
ID1
167
GND
GND
GND
Remark H:
VOH,
L:
VOL
AO-Al0,SO: Address Inputs
I/O 0 - I/O 71 : Data Inputs/Outputs
RASO, RAS2 : Row Address Strobe
CASO, CAS4
Column Address Strobe
WEO, WE2
Write Enable
OEOi OE2
Output Enable
PDE
Presence Detect Enable
PDl - PD8
IDO, ID1
GND
Presence Detect Pins
Identity Pins
Power Supply
Ground
NC
No connection
Vee
0
NEe
MC-422000LAB72F
Block Diagram
RASO
RAS2
WED
":::
v
CASO
o--{)
OED
WE2
":::
CAS4
n--[:;
OE2
j
I
1/00 a . -
I/O 8 CAS RAS WE OE
a . - I/O 7
I/O 2 a . - I/O 6
....
j
I
I/O 40 a . -
I/O 1 CAS RAS WE DE
1/041 0 . - - I/O 2
I/O 42 a . - 1/03
1/01
1/03 0 . - - I/O 5
I/O 43 a . - 1/04
I/O 44 a . - I/O 5
00
1/04 a . - 1/04
I/O 5 a . - I/O 3
1/045 a . - 1/06
1/06 a . - I/O 2
1/046 a . - I/O 7
1/07 a . - I/O 1
1/047 a . - I/O 8
I
05
j
!
j
I/O 8 a . - I/O 8 CAS RAS WE DE
1/048 0 - - - I/O 1 CAS RAS WE DE
I/O 9 a . - 1/07
1/049 0------ 1/02
I/O 10 a . - 1/06
a.12 a . 13 a . 14 a . 15 a . -
I/O 50 0-
- 1/03
I/O 51 0-
- I/O 4
- 110 ~
- 110 G
- 1/07
...... 1/08
1/011
I/O 5
I/O
1/04
I/O 52 0-
1/03
I/O 53 0--
I/O
I/O
I/O
01
I/O 2
I/O 54 0- -
I/O 1
I/O 55 ()4
!
j
!
I/O 16 a . - I/O 8 CAS RAS WE DE
I/O 50 0-
I/O 17 a . - 1/07
I/O 57 0--
j j
_ I/O 1 CflSllflS WI: OE
- I/O 2
I/O 58 0 . - - 1/03
I/O 18 a . - 1/06
I/O 19 a . - I/O 5
I/O 59 a . - I/O 4
02
1/020 a . - 1/04
I/O 21
.
06
a . - 1/03
1/061
a . - 1/06
I/O 22 a . - I/O 2
I/O 62 a . - 1/07
1/023 a . - 1/01
I/O 63 a . - 1/08
I
07
1/060 a . - I/O 5
!
I
!
I/O 24 a . - I/O 8 CAS RAS WE DE
1/064 a . - 110 1 CAS RAS WE DE
1/025 a . - I/O 7
I/O 65 a . - 1/02
I/O 26 a . - I/O 6
I/O 66 a . - 1/03
I/O 27 a . - I/OS
I/O 67 a . - 1/04
03
I/O 29 a . - 1/03
I/O 68 a . - 1/05
I/O 69 a . - I/O 6
I/O 30 a . - 1/02
I/O 70 a . - I/O 7
I/O 28 a . - I/O 4
1/031
a . - 1/01
I/O 71
I
08
a . - 1/08
I
I/O 32 a . - I/O 8 CAS RAS WE DE
I/O 33 a . - I/O 7
1/034 a . - I/O 6
I/O 35 a . - I/O 5
04
I/O 36 ( ) 4 - - - 1/04
I/O 37
~---.
1/03
...
I/O 2
I/O 39 0 ... ··· --- ... 1/01
1/038 ~-----
PDE
AD
80
A 1 - A 10
0-----{>--- AD : DO - D4
0-----{>--- AD : D5 - D8
0-----{>--- DO - D8
Remark 00 - 08 : JLP04217800L
PDl - PD8
0------;,.
0-------<1-
IDO. IDl 0
Vee 0
GND 0
Vee or GND
NC or GND
:l: CO _ C8 • DO - D8
T
- DO - D8
261
NEe
MC-422000LAB72F
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-0.5 to +4.6
V
Supply voltage
Vee
-0.5 to +4.6
V
Output current
10
20
mA
Power dissipation
Po
11
W
Operating ambient temperature
TA
o to +70
·C
Storage temperature
T5tg
-55 to +125
·C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
MIN.
TYP.
3.3
MAX.
Unit
Supply voltage
Vee
3.0
3.6
V
High level input voltage
V,H
2.0
Vee + 0.3
V
Low level input voltage
V,L
-0.3
+0.8
V
Operating ambient temperature
TA
0
70
·C
MAX.
Unit
20
pF
Capacitance ITA
=25 ·C, f =1 MHz)
Parameter
Input capacitance
Data InpuVOutput capacitance
262
Condition
Symbol
Symbol
Test Condition
MIN.
TYP.
CIl
AD - A10, 80
C"
WEO, WE2
20
C"
RASO,RAS2
50
C"
CASO, CAS4
20
CIS
OEO,OE2
20
CliO
1/00 - 1/071
20
pF
NEe
MC-422000LAB72F
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Iccl
Test condition
RAS. CAS Cycling
tRC = tRC (MIN. I
10 = 0 rnA
Standby current
Icc,
RAS. CAS
---RAS. CAS
RAS only refresh current
Operating current
Icc3
Icc.
(Fast page mode)
~
V,H IMIN.!
~
Vcc - 0.2 V
Icc,
refresh current
Input leakage current
Ii ILl
MIN.
Unit
Notes
910
rnA
3,4,7
tRAC = 70 ns
820
tRAC = 80 ns
730
10= 0 rnA
82
10 = 0 rnA
RAS Cycling
CAS ~ V,H (MIN.I
tRC = tRC (MIN.I
10 = 0 rnA
tRAC = 60 ns
RAS :5 V,L (MAX.I, CAS Cycling
tpc = tpc (MIN.I
10 = 0 rnA
CAS before RAS
MAX.
tRAC = 60 ns
--
RAS Cycling
tRC = tRC (MIN.I
10 = 0 rnA
V, = 0 to 3.6 V
41
910
tRAC = 70 ns
820
tRAC = 80 ns
730
tRAC = 60 ns
640
tRAC = 70 ns
550
tRAC = 80 ns
460
tRAC = 60 ns
910
tRAC = 70 ns
820
tRAC = 80 ns
/RAS
rnA
rnA
3,4,5,7
rnA
3, 4, 6
rnA
3, 4
730
-5
+5
p.A
All other pins not under test = 0 V / Others
-5
+1
+5
p.A
0.4
V
Output leakage current
10(LI
Vo = 0 to 3.6 V
Output is disabled (Hi-Z)
-5
High level output voltage
VOH
10 = -2.0 rnA
2.4
Low level output voltage
VOL
10 = +2.0 rnA
V
263
NEe
MC-422000LAB72F
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
Symbol
tRAC = 60 ns
MIN.
tRAC = 70 ns
MIN.
MAX.
tRAC = 80 ns
MIN.
Unit
Notes
MAX.
Read/Write Cycle Time
tRC
110
130
150
ns
Read Modify Write Cycle Time
tRWC
173
195
215
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Read Modify Write Cycle Time (Fast Page Mode)
tPRWC
85
90
100
Access Time from RAS
tRAC
60
70
80
ns
10, 11
Access Time from CAS
tCAC
20
23
25
ns
10, 11
Access Time Column Address
tAA
35
40
45
ns
10, 11
Access Time from CAS Precharge
tACP
40
45
50
ns
11
Access Time from OE
tOEA
20
23
25
ns
11
RAS to Column Address Delay Time
tRAD
15
40
ns
10
CAS to Data Setup Time
tClZ
0
0
0
ns
11
OE to Data Setup Time
tOlZ
0
0
0
ns
11
Output Buffer Turn-off Delay Time from CAS
tOFF
0
ns
12
OE to Data Delay Time
tOED
13
Output Buffer Turn-off Delay Time from OE
tOEZ
0
OE Hold Time
tOEH
0
--
30
13
15
0
35
15
15
13
0
17
0
ns
15
15
15
0
0
ns
15
0
12
ns
OE Lead Time Referenced to RAS
tOES
0
tT
3
RAS Precharge Time
tRP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
...
RAS Hold Time
tRASP
60
125,000
70
125,000
80
125,000
ns
tRSH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tRCO
20
CAS to RAS Precharge Time
tCRP
5
5
CAS Precharge Time
tCPN
10
10
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
40
45
50
ns
Row Address Setup Time
tASR
5
5
5
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAl
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRAH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tACH
0
0
0
ns
14
WE Hold Time Referenced to CAS
tWCH
10
10
15
ns
15
WE Pulse Width
twp
10
10
15
ns
15
--
0
ns
Transition Time (Rise and Fall)
-_
264
MAX.
50
3
0
50
50
18
10,000
20
20
ns
10,000
80
50
25
ns
ns
20
70
45
ns
50
60
18
10,000
3
ns
ns
60
ns
10
5
ns
13
10
ns
NEe
MC-422000LAB72F
Symbol
Parameter
tRAe = 60 ns
MIN.
MAX.
tRAe = 70 ns
MIN.
MAX.
tRAe = 80 ns
MIN.
Unit
Notes
MAX.
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tOH
10
15
15
ns
16
Write Command Setup Time
twes
0
0
0
ns
17
CAS to WE Delay Time
tcwo
38
43
45
ns
17
RAS to WE Delay Time
tRWO
93
105
115
ns
17
CAS Precharge to WE Delay Time
tepwo
58
65
70
ns
17
Column Address to WE Delay Time
tAWO
58
65
70
ns
17
WE Lead Time Referenced to RAS
tRWL
25
25
25
ns
WE Lead Time Referenced to CAS
tewL
15
15
15
ns
CAS Setup Time (CAS before RAS Refresh)
tesR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
teHR
10
10
10
ns
WE Setup Time
tWSR
10
----_ .. -.--10.
10
ns
WE Hold Time
tWHR
15
"..J
15
Refresh Time
tREF
-_.
32
32
. - r-
32
ns
.. - i 1115
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 f1s and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. icc', Icc3, Icc4 and Iccs depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. Icc, and Icc3 are measured assuming that address can be changed once or less during RAS::;
IMAX.I
a.
and CAS
VIL
~ VIH IMIN.I.
AC measurements assume tT
=
5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H IMIN I = 2.0 V
.----------~-----,,
,,
V,L (MAKI = 0.8 V
,,
,
,
,,
, ,
, ,
I
: :
: :
.:-
IT = 5 ns
tT = 5 ns
______________
I
I
~
I
I
I
(2) Output timing specification
VOH (MIN I = 2.0 V
VOL (MAX) = 0.8 V
:::::::=\'-------Jr
265
NEe
MC-422000LAB72F
10. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD :5 tRAD (MAX.) and tRCD :5 tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.,
tRAD > tRAD (MAX.) and tRCD :5 tRCD (MAX.)
tAA(MAX.)
tRAD + tAA (MAX )
tRee> tRCO (MAX.)
teAc (MAX.)
tRCD + tCAC (MAX.)
tRAD IMAX.) and tRCD IMAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAD <': tRADIMAX.)
and tRCD <': tRCD IMAX.) will not cause any operation problems.
11. Loading conditions are 1 TTL and 100 pF.
12. tOFF IMAX.) and tOEZ IMAX.) define the time at which the output achieves the condition of Hi-Z and
are not referenced to VOH or VOL.
13. tCRP IMIN.) requirements should be applied to RAS/CAS cycles.
14. Either tRCH IMIN.) or tRRH IM)N.) should be met in read cycles.
15. tWPIMIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH IMIN.)
should be met.
16. tDS IMIN.) and tDIl IMIN.) are referenced to the CAS falling edge in early write cycles. In late write
cycles and read modify cycles, they are referenced to the WE falling edge.
17. If twcs <': twcs 1M IN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWD <': tRWDIMIN.), tCWD <': tCWDIMIN.), tAWD <': tAWDIMIN.) and tCPWD <': tCPWD IMIN.), the cycle
is read modify write cycle and the data out will contain data read from the selected cell. If neither
of the above conditions is met, the state of the data out is indeterminate.
266
Timing Chart
Please refer to Timing Chart 7, page 429.
267
NEe
MC-422000LAB72F
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
~--------------------A----------------------~
Rs~bO~= 0
't
(OPTIONAL HOlES $.
.;J.-~[8J
J-
K-----H
-~~.
LI
D
B -~~-~----- C -----+.+~------E --------~
LG
Lo
~DU""III11DIIID""""I""""'DIIID ~
detail of
®
part
detail of
X
@
part
ITEM
A
B
C
0
01
02
E
G
H
K
L
M
N
P
Q
268
MILLIMETERS
133.35±0.13
11.43
36.83
6.35
2.0
3.125
54.61
6.35
1.27 (T.P.)
8.89
23.50
43.18
17.78
25.4±0.13
4.0 MAX.
1.0
R2.0
INCHES
5.25±0.006
0.450
1.450
0.250
0.079
0.123
2.150
0.250
0.050 (T.P.)
0.350
0.925
1.70
0.700
1.000±0.006
0.158 MAX.
0.039
RO.079
R
4.0±0.1
0.157~g:gg~
s
CP3.0
T
U
V
1.27±0.1
4.0 MIN.
0.25 MAX.
cpO.118
0.05±0.004
0.157 MIN.
0.Q10 MAX.
W
1.0±0.05
0.039~g:gg~
X
Y
Z
2.54±0.10
3.0 MIN.
3.0 MIN.
0.100±0.004
0.118MIN.
0.118MIN.
M168S-50A8
DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC-424000AB72F
4 M-WORD BY 72-BIT DYNAMIC RAM MODULE
FAST PAGE MODE (ECC)
Description
The MC-424000AB72F is a 4,194,304 words by 72 bits dynamic RAM module on which 18 pieces of 16 M
DRAM: tlPD4217400 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
•
4,194,304 words by 72 bits organization
• Fast access and cycle time
Powor consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-424000AB72-60
60 ns
110 ns
10.73 W
MC-424000AB72-70
70 ns
130 ns
9.79W
MC-424000AB72-80
80 ns
150 ns
8.84W
Family
Active
•
2,048 refresh cycles/32 ms
•
CAS before RAS refresh, RAS only refresh, Hidden refresh
•
168-pin dual in-line memory module (Pin pitch
Standby
430 mW
(CMOS level input)
= 1.27 mm)
• Single +5.0 V ±0.25 V power supply
Ordering Information
Part number
Access time
(MAX.)
MC-424000AB72F-60
60 ns
MC-424000AB72F-70
70 ns
MC-424000AB72F-80
80 ns
Mounted devices
Package
168-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
18 pieces of jlPD4217 400G3
(300 mil TSOP(II))
[Double side]
The information in this document is subject to change without notice.
Ie-35gB (Japan)
269
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MC-424000AB72F
Pin Configuration
16B-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
0
0
GND
1/036
1/037
1/038
I/O 39
Vee
1/04
1/05
I/O 6
1/07
1/044
GND
1/045
1/046
1/047
1/048
1/049
1/08
GND
1/09
I/O 10
1/011
I/O 12
1/013
1/050
1/051
1/052
--01/053
-OGND
--ONC
-oNC
Vee
NC
NC
NC
NC
NC
GND
A1
A3
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
270
0
Vee
1/040
1/041
1/042
1/043
Vee
-0
GND
1/00
1/01
I/O 2
1/03
Vee
I/O 14()-4
1/015
1/016()-4
I/O 17
GND
NC
NC
PD and ID Table
Vee
WED
CASO
NC
RASO
OED
GND
AD
A2
A4
Access Time
Pin
Name
Pin
No.
60 ns
70 ns
80 ns
PD1
79
H
H
H
H
A5
A7
A9
NC
NC
PD2
163
H
H
A10
NC
PD3
80
L
L
L
Vee
Vee
PD4
164
H
H
H
NC
NC
GND
PD5
81
L
L
L
PD6
165
H
L
H
L
NC
80
GND
NC
NC
NC
NC
PDE
Vee
A6
AS
()F.20-~
RA"S"70-"
CAS4
PD7
82
H
H
WE20-~
PD8
166
L
L-
100
83
GND
GNO
GNO
101
167
GNO
GNO
GNO
NCO-
NC
NC
1/054
1/055
GND
1/056
1/057
1/058
1/059
Vee 0
NC
NC
I/O 18
I/O 19
GND
1/020
1/021
1/022
1/023
1/060
NC
NC
NC
NC
1/061
1/062
1/063
GND
1/064
1/065
1/066
1/067
1/024
NC
NC
NC
NC
1/025
1/026
1/027
GND
1/028
1/029
1/030
1/031
Vee
Vee
1/068
1/069
1/070
1/071
GND
PD2
PD4
PD6
PD8
ID1
Vee
Remark H : VOH,
L:
L
VOL
Vee
AO - A10, 80 : Address Inputs
I/O 0 - I/O 71 : Data Inputs/Outputs
---RASO, RAS2 : Row Address Strobe
CASO,CAS4
Column Address Strobe
WEO, WE2
Write Enable
OEO,OE2
Output Enable
POE
Presence Detect Enable
P01 - PD8
Presence Detect Pi ns
100.101
Identity Pins
Vee
Power Supply
GND
Ground
----
Vee
1/032
1/033
1/034
1/0350
GND
PD1
PD3
PD5
PD7
IDO
NC
Vee
0
No connection
NEe
MC-424000AB72F
Block Diagram
RASO 0 - - - - - - - - - ,
OEoo---C~----r---'
RAS20--------,
OE20---C~---_+--,
WE00--4~~----r-.
WE20--~~~----+__,
CASO o---;;:o~---,
CAS4 o---;;:o~---.
r----:~_;::!::~",.....,;!::__,
r----:~_;::!::;_;:::!~~
1100
1/01
1/02
1/03
1/036
1/037
1/03B
1/039
1/04
1/05
1/06
1/07
1/040
1/041
I/OB
1/09
1/010
1/011
1/012
I/O 13
1/014
1/015
1/04B
1/049
1/050
1/051
1/0160--....
1/0170--....
I/O 1B
1/019
1/052
1/053
I/O 54
1/020
1/021
1/022
1/023
1/05B
1/059
1/0240--+/
110 25v---.
1/026
1/027
1/060
1/061
I/O 62
1/063
1/02B
1/029
1/030
1/031
1/064
1/065
1/066
1/067
1/0320--+/
1/033
1/0340--+/
1/035
1/06B
1/069
1/070
1/071
AO 0 - { > - AO : 00 - OB
BOo-{>-AO:09-017
A1-A100-{>- 00-017
PDE~
P01 - POB ~ Vee or GND
IDO, ID1 0 > - - - - - - NC or GND
Vee 0
Remark DO - 017 : ,uP04217400
015
GNOO
::!:
•
T CO -C1 :
DO-D17
DO-D17
271
NEe
MC-424000AB72F
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Supply voltage
Vcc
-1.0 to +7.0
V
Output current
10
50
mA
Power dissipation
Po
20
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
Tstg
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
MIN.
TYP.
5.0
MAX.
Unit
Supply voltage
Vcc
4.75
5.25
V
High level input voltage
V,H
2.4
Vcc+ 1.0
V
Low level input voltage
Vil
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
·C
MAX.
Unit
20
pF
Capacitance (TA
=25 ·C. f = 1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
272
Condition
Symbol
Symbol
Test Condition
MIN.
TYP.
Cil
AD· Al0, BO
C"
WEO, WE2
20
C"
RASO, RAS2
78
C"
CASO,CAS4
20
C"
OEO,OE2
20
CliO
1/00 -1/071
20
pF
NEe
MC-424000AB72F
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Test condition
Symbol
Icc,
MAX.
Unit
Notes
RAS. CAS Cycling
tRAC = 60 ns
2.044
mA
3.4.7
tRC = tRC 1M IN.!
tRAC = 70 ns
1.864
tRAC = 80 ns
1.684
10 = 0 mA
Standby current
RAS only refresh current
Operating current
Icc2
Icc3
Icc.
(Fast page mode)
RAS. CAS ~ VIH IMIN.!
10=OmA
100
RAS. CAS ~ Vcc - 0.2 V
10 = 0 mA
82
RAS Cycling
CAS ~ V,H IMIN.!
hc = tRC IMIN.!
10 = 0 mA
tRAC = 60 ns
2.044
tRAC = 70 ns
1.864
tRAC = 80 ns
1.684
RAS ~ VIlIMAX.!. CAS Cycling
tRAC = 60 ns
1.324
tpc = tpc IMIN.!
tRAC = 70 ns
1.144
10 = 0 mA
CAS before RAS
Iccs
refresh current
tRAC = 80 ns
964
RAS Cycling
tRAC = 60 ns
2.044
tRC = tRC 1M IN.!
tRAC = 70 ns
1.864
10 = 0 mA
Input leakage current
h IL!
MIN.
V! = 0 to 5.5 V
tRAC = 80 ns
IHAS
I
All other pins not under test = 0 V Others
Output leakage current
lOlL!
Vo = 0 to 5.5 V
mA
mA
3.4.5.7
mA
3.4.6
mA
3.4
1.684
-10
+10
-5
+1
-10
+10
pA
pA
Output is disabled (Hi-Z)
High level output voltage
VOH
10 = -5.0 mA
Low level output voltage
VOL
10 = +4.2 mA
2.4
V
0.4
V
273
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MC-424000AB72F
AC Characteristics (Recommended Operating Conditions unless otherwise noted) Notes 8, 9
Parameter
Symbol
tRAC = 60 ns
MIN.
274
MAX.
tRAC = 70 ns
MIN.
MAX.
tRAC = 80 ns
MIN.
Unit
Notes
MAX.
Read/Write Cycle Time
tRC
110
130
150
ns
Read Modify Write Cycle Time
tRWC
175
195
220
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Read Modify Write Cycle Time (Fast Page Mode)
tPRWC
85
Access Time from RAS
tRAC
60
70
80
ns
10, 11
Access Time from CAS
tCAC
20
23
25
ns
10, 11
Access Time Column Address
tAA
35
40
45
ns
10, 11
Access Time from CAS Precharge
tACP
40
45
50
ns
11
Access Time from OE
tOEA
20
25
ns
11
RAS to Column Address Delay Time
tRAO
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
0
0
ns
11
OE to Data Setup Time
tOLZ
0
0
0
ns
11
Output Buffer Turn-off Delay Time from CAS
tOFF
0
0
ns
12
OE to Data Delay Time
tOED
15
Output Buffer Turn-off Delay Time from OE
tOEZ
0
OE Hold Time
tOEll
0
0
0
ns
OE Lead Time Referenced to RAS
tOES
0
0
0
ns
Transition Time (Rise and Fall)
tT
3
RAS Precharge Time
tRP
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
125,000
70
125,000
80
125,000
ns
10,000
18
90
30
15
105
23
15
35
15
15
15
50
0
3
17
0
ns
20
20
15
50
50
0
3
ns
20
50
60
18
ns
12
ns
ns
RAS Hold Time
tRSH
15
CAS Pulse Width
tCAS
15
20
CAS Hold Time
tCSH
60
RAS to CAS Delay Time
tRCO
20
ns
10
CAS to RAS Precharge Time
tCRP
5
5
5
ns
13
CAS Precharge Time
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
40
45
50
ns
Row Address Setup Time
tASR
5
5
5
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAl
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
\wCH
10
10
15
ns
15
WE Pulse Width
twp
10
10
15
ns
15
10,000
70
40
20
20
ns
10,000
80
50
25
ns
ns
60
NEe
MC-424000AB72F
tRAC = 60 ns
Symbol
Parameter
MIN.
MAX.
tRAC = 70 ns
MIN.
MAX.
tRAC = 80 ns
MIN.
Unit
Notes
MAX.
Data-in Setup Time
tDS
0
0
0
ns
16
Data-in Hold Time
tOH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS to WE Delay Time
tcwo
40
43
50
ns
17
RAS to WE Delay Time
tRWO
95
105
120
ns
17
CAS Precharge to WE Delay Time
tcPWO
58
65
70
ns
17
Column Address to WE Delay Time
tAWO
60
65
75
ns
17
WE Lead Time Referenced to RAS
tRWL
25
25
25
ns
WE Lead Time Referenced to CAS
tCWL
15
15
15
ns
CAS Setup Time (CAS before RAS Refresh)
tCSR
5
5
5
ns
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
WE Setup Time
tWSR
10
10
10
ns
WE Hold Time
tWHR
15
15
15
ns
Refresh Time
tREF
32
32
32
ms
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. Iccl, Icc3, Icc4 and Icc5 depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icc3 is measured assuming that all column address inputs are held at either high or low.
6. Icc4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. Iccl and Icc3 are measured assuming that address can be changed once or less during RAS:S; VIL
(MAX. I and CAS <:: VIH (MIN.I.
8. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
V,H (MIN.) = 2.4 V
VIL (MAlO = 0.8 V
.----------~-----ii,
,
I
,
I
I
I
I
I
______________
,
I
tT = 5 ns
I
,
I
I
---+--fttT = 5 ns
(2) Output timing specification
VOH (MIN.I = 2.4 V
VOL (MAlO = 0.4 V
~::::~:~~}275
NEe
MC-424000AB72F
10. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD :5 tRAD (MAX.I and tRCD :5 tRCD (MAX.I
tRAC {MAX.'
tRAC (MAX. I
hAD> tRAD (MAX.I and tRCD :5 tRCD (MAX. I
tAA (MAX.)
tRAD + tM (MAX.I
tRCD > tRCD (MAX.I
tCAC (MAX.I
tRCD + tCAC (MAX.I
tRAO (MAX.I and tRCO (MAX.I are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAO;:: tRAO (MAX. I
and tRCO ;:: tRCO (MAX.I will not cause any operation problems.
11. Loading conditions are 2 TTLs and 100 pF.
12. tOFF (MAX.I and tOEZ (MAX.I define the time at which the output achieves the condition of Hi-Z and
are not referenced to VOH or VOL.
13. tCRP (MIN.I requirements should be applied to RAS/CAS cycles.
14. Either tACH (MIN.I or tRRH (MIN.I should be met in read cycles.
15. tWP(MIN.1 is applied to late write cycles or read modify write cycles. In early write cycles, twCH (MIN.I
should be met.
16. tos (MIN.I and tOH (MIN.I are referenced to the CAS falling edge in early write cycles. In late write
cycles and read modify cycles, they are referenced to the WE falling edge.
17. If twcs ;:: twcs (MIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWO;:: tAWO (MIN.I, tcwo ;:: tcwo (MIN.I, tAWO;:: tAWO (MIN.I and tcPWO;:: tcPWO (MIN.I, the cycle
is read modify write cycle and the data out will contain data read from the selected cell. If neither
of the above conditions is met, the state of the data out is indeterminate.
276
Timing Chart
Please refer to Timing Chart 7, page 429.
277
NEe
MC-424000AB72F
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A
detail of
® part
detail of
® part
W
tr
~
0
ITEM
A
MILLIMETERS
133.35±0.13
B
Q
11.43
36.83
6.35
54.61
6.35
1.27 (T.P.)
8.89
23.495
42.18
17.78
25.4
4.0 MAX.
1.0
R2.0
INCHES
5.25±0.006
0.450
1.450
0.250
2.150
0.250
0.050 (T.P.)
0.350
0.925
1.661
0.700
1.000
0.158 MAX.
0.039
RO.079
R
4.0±0.1
0.157~8:88~
s
(p3.0
1.27±0.1
4.0 MIN.
0.25 MAX.
1.0±0.05
2.54 MIN.
3.0 MIN.
3.0 MIN.
(p0.118
0.05±0.004
0.157 MIN.
0.010 MAX.
0.039±0.002
0.100 MIN.
0.118 MIN.
0.118 MIN.
M168S-50A2
C
-ru0
0
E
G
H
K
L
M
N
P
T
U
V
W
X
Y
Z
278
DATA SHEET
NEe
I (Japan)
MOS INTEGRATED CIRCUIT
MC-424000AC72F
4 M-WORD BY 72-BIT DYNAMIC RAM MODULE
FAST PAGE MODE (ECC)
Description
The MC-424000AC72F is a 4,194,304 words by 72 bits dynamic RAM module on which 18 pieces of 16 M
DRAM: JlPD4216400 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
•
4,194,304 words by 72 bits organization
•
Fast access and cycle time
Power consumption
(MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
MC-424000AC72-60
60 ns
110 ns
B.B4W
MC-424000AC72-70
70 ns
130 ns
7.90W
MC-424000AC72-BO
BO ns
150 ns
6.95W
Family
Active
Standby
430 mW
(CMOS lovol input)
• 4,096 refresh cycles/64 ms
• CAS before RAS refresh, RAS only refresh, Hidden refresh
•
168-pin dual in-line memory module (Pin pitch
= 1.27 mm)
• Single +5.0 V ±0.25 V power supply
Ordering Information
Part number
Access time
(MAX.)
MC-424000AC72F-60
60 ns
MC-424000AC72F-70
70 ns
MC-424000AC72F-BO
BO ns
Mounted devices
Package
16B-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
1B pieces of jLl'D4216400G3
(300 mil TSOP(II)
[Double side]
The Information In this document is subject to change without notice.
279
NEe
MC-424000AC72F
Pin Configuration
16B-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
0
0
85
86
87
88
89
90
91
92
93
94
GND
I/O 36
1/037
1/038
1/039
Vee
1/04
I/O 5
1/06
1/07
1/044
GND
1/045
1/046
1/047
1/048
1/049
1/08
GND
1/09
I/O 10
1/011
I/O 12
I/O 13
I/O 50
I/O 51
I/O 52
I/O 53
GND
I,C
-ONC
-OVec
-ONC
-oNC
-oNC
NC
NC
GND
Al
A3
A5
A7
A9
All
NC
Vee
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
0
280
Vee
1/040
1/041
1/042
1/043
Vee
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
GND
1/00
1/01
I/O 2
1/03
NC
BO
GND
NC
NC
NC
NC
POE
Vee
NC
NC
I/O 54
I/O 55
GND
1/056
1/057
1/058
1/059
Vee
1/060
NC
NC
NC
NC
1/061
I/O 62
I/O 63
GND
1/064
1/065
1/066
1/067
Vee
1/068
I/O 69
1/070
1/071
GND
PD2
PD4
PD6
PD8
IDl
Vee
Vee
I/O 14
I/O 15
I/O 16
I/O 17
GND
NC
NC
PO and 10 Table
Vee
WEll
CASU
NC
Pin
Name
Access Time
Pin
No.
60 ns
70 ns
80 ns
PDl
79
H
H
H
PD2
163
H
H
H
Al00--NC
PD3
80
L
L
L
Vee
PD4
164
H
H
H
NC
NC
GND
PD5
81
L
L
L
PD6
165
H
L
H
il)'ioO
OlOO-~
GNIlOi\OO-~
A20-~
A40~~
A60--AS
o---~
0E2
RAS2
PD7
82
H
H
L
NC
WE2
PD8
166
L
L
L
IDO
83
GND
GND
GND
ID1
167
GND
GND
CAS4
Vee
NC
NC
I/O 18
I/O 19
GND
1/020
1/021
1/022
1/023
Remark H :
GND
VOH.
L:
VOL
Vee
1/024
NC
NC
NC
NC
1/025
1/026
1/027
GND
I/O 28
I/O 29
1/030
1/031
AO-A11.BO: Address Inputs
I/O 0 - I/O 71 : Data Inputs/Outputs
----
RASO. RAS2 : Row Address Strobe
Vee
1/032
1/033
1/034
1/035
GND
PDl
PD3
PD5
PD7
IDO
Vee
0
CASO. CAS4
Column Address Strobe
WEO. WE2
Write Enable
OEO.OE2
PDE
Output Enable
Presence Detect Enable
PDl - PD8
Presence Detect Pins
100.101
Identity Pins
Vee
GNO
Power Supply
Ground
NC
No connection
NEe
MC-424000AC72F
Block Diagram
RASO 0 - - - - - - - - ,
RAS20--------,
OEoo--D~---~--.
OE2o--D~---~--.
WEOo--C~----+-.
WE20--C~----+-.
CASO O--D~-----,
CAS4 O--f)~-----,
I/O 0 o---~I/O 4
I/O 1
1/03
I/O 2
I/O 2
1/03
I/O 1
1/040---+1
I/O 5 o---.J I/O 3
1/06
1/02
Ifa 7
DO
Ifa 36
Ifa 37
1/038
1/039
01
If0 40
1/041
Ifa 42
1/043
",,'f_O_l_.--;---;_.....
r----:;::!::;:~~::;_:~
Ifa 8
Ifa 9
I/O 10
1/011
Ifa 44
1/045
I/O 120---.J
Ifa 130---+1
1/0140---+1
Ifa 48 ()~ ..- ~ I/O 1 CAS liAS
I/O 49 ()~ .. ~ I/O 2
012
I/O 50 o~-~ 1/0:1
I/O 47
03
o~
~
I/O 4
WE
Ifa 15 O---~~--r-....,._r--.,..J
Ifa 51 O---~'_"/_O_.l_;_-,-___r-,.....
1/0160---+1
1/0170---+1
Ifa 180---+11/0 2
I/O 19
Ifa 1
Ifa 52
1/053
Ifa 54
I/O 55
04
Ifa 20 o---~I/O 4
Ifa 21 0---+1
Ifa 22
Ifa 23
11056
110 57
110 58
110 59
1/024
Ifa 25
Ifa 26
11060
11061
11062
Ito 63
'fa 27 O---~~--r_-r---'--r-J
Ifa 28<>--+1
Ifa 29
1/030<>--+1
Ito 31 <>--~~-r---""-r---r.J
Ifa 64
1/065
1/066
I/O 67
1/032
1/033
1/034
Ifa 35
Ifa 68
1/069
Ifa 70
Ifa 71
o----J>--- AO : DO - 08
o----J>--- AO: 09 - 017
A1-Al1 o----J>--- 00-017
AO
BO
Remark DO - 017 : pP04216400
017
POE~
POl - P08
100. 101
o-----.e:J-- Vee or GNO
NC or GNO
0
Vee 0.----::1:---. 00-017
T CO-C1 00-017
GNOO
?
281
NEe
MC-424000AC72F
Electrical Specifications Notes 1,2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Unit
Rating
Voltage on any pin relative to GND
Vr
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
rnA
Power dissipation
Po
20
W
Operating ambient temperature
TA
o to +70
'C
Storage temperature
Tstg
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthisspecification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Paramoter
Supply voltage
Condition
Vee
MIN.
TYP.
MAX.
Unit
4.75
5.0
5.25
V
High level input voltage
V,H
2.4
Vee + 1.0
V
Low level input voltage
V,L
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
'C
MAX.
Unit
Capacitance ITA
= 25 'C, f = 1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
282
Symbol
Symbol
Test Condition
MIN.
TYP.
CII
AD - A11, BO
20
C"
WEO, WE2
20
C'l
RASO,RAS2
78
C"
CASO,CAS4
20
CIS
OEO,OE2
20
Cve
1/00 - 1/071
20
pF
pF
NEe
MC-424000AC72F
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
Icci
Test condition
MIN.
RAS, CAS Cycling
1,684
tRC = tRC IMIN.!
tRAC = 70 ns
1,504
tRAC = 80 ns
1,324
10 = 0 mA
Standby current
Icc2
10 = 0 mA
100
RAS, CAS ~ Vcc - 0.2 V
10 = 0 mA
82
RAS Cycling
CAS ~ V,H IMIN.!
tRC = tRC IMIN.!
10 = 0 mA
tRAC = 60 ns
1,684
tRAC = 70 ns
1,504
tRAC = 80 ns
1,324
RAS, CAS ~ V,H IMIN.!
--
RAS only refresh current
Operating current
IcOl
Icc.
(Fast page mode)
--RAS S; VIL IMAX.!, CAS Cycling
tRAC = 60 ns
1,324
tpc = tpc 1M IN.!
tRAC = 70 ns
1,144
10 = 0 mA
CAS before RAS
Iccs
refresh current
tllAC = 80 ns
964
RAS Cycling
tllAC" 60 ns
1,684
tRC = tRC IMIN.!
tllAC :....I 70 ns
. .... .. _-----IliAC" 00 m;
10=OmA
Input leakage current
II IL!
V, = 0 to 5.5 V
lOlL!
Vo = 0 to 5.5 V
Output is disabled (Hi-Z)
High level output voltage
VOH
10 = -5.0 mA
Low level output voltage
VOL
10 = +4.2 mA
_
"'-'r
All other pins not undor tost
Output leakage current
MAX.
tRAC = 60 ns
RAS
u
0 V alhum
1,504
...
------
-----
Unit
Notes
mA
3,4,7
mA
mA
3,4,5,7
mA
3,4,6
mA
3,4
1,324
-
-10
---.
!·10
..~--
-5
1·1
-10
+10
2.4
/lA
pA
V
0.4
V
283
NEe
MC·424000AC72F
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
tRAC = 60 ns
MIN.
284
MAX.
tRAC = 70 ns
MIN.
MAX.
tMC = 80 ns
MIN.
Notes 8, 9
Unit
Read/Write Cycle Time
tRC
110
130
150
Read Modify Write Cycle Time
tRWC
175
195
220
ns
Fast Page Mode Cycle Time
tpc
40
45
50
ns
Read Modify Write Cycle Time (Fast Page Mode)
tpRWC
85
Access Time from RAS
tRAC
90
Notes
MAX.
ns
105
ns
60
70
80
ns
10, 11
Access Time from CAS
tCAC
20
23
25
ns
10, 11
Access Time Column Address
tAA
35
40
45
ns
10, 11
Access Time from CAS Precharge
tACP
40
45
50
ns
11
Access Time from OE
tOEA
20
23
25
ns
11
ns
10
RAS to Column Address Delay Time
tRAD
15
CAS to Data Setup Time
telz
0
0
0
ns
11
OE to Data Setup Time
taLz
0
0
0
ns
11
Output Buffer Turn-off Delay Timo from CAS
taFF
0
ns
12
DE to Data Dolay Time
tOEa
15
Output Buffer Turn-off Delay Time from OE
taEz
0
OE Hold Time
taEH
0
OE Lead Time Referenced to RAS
tOES
0
Transition Time (Rise and Fall)
tT
3
RAS Precharge Time
tRP
40
RAS Pulse Width
tRAS
RAS Pulse Width (Fast Page Mode)
30
15
15
0
35
15
15
15
0
17
0
40
20
20
15
0
0
ns
20
0
ns
12
ns
0
ns
0
50
3
60
10,000
tRASP
60
125,000
RAS Hold Time
tRSH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Dclay Time
tRCD
20
ns
10
CAS to RAS Prccharge Time
tCRP
5
5
5
ns
13
CAS Prechargo Timo
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Mode)
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
40
45
50
ns
Row Address Setup Time
tASR
5
5
5
ns
Row Address Hold Time
tRAH
10
10
12
ns
Column Address Setup Time
tASC
0
0
0
ns
Column Address Hold Time
tCAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
tRAL
30
35
40
ns
Read Command Setup Time
tRCS
0
0
0
ns
50
3
70
10,000
80
10,000
ns
70
125,000
80
125,000
ns
50
18
20
10,000
70
40
20
20
ns
10,000
80
50
25
ns
ns
60
18
10,000
50
ns
ns
60
Read Command Hold Time Referenced to RAS
tRRH
0
0
0
ns
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twCH
10
10
15
ns
15
WE Pulse Width
twp
10
10
15
ns
15
14
NEe
MC-424000AC72f
= 60
tRAC
Symbol
Parameter
MIN.
ns
tRAC
MAX.
MIN.
= 70
ns
tRAC
MAX.
MIN.
= 80
ns
Unit
Notes
16
MAX.
Data·in Setup Time
tDS
0
0
0
ns
Data·in Hold Time
tDH
10
15
15
ns
16
Write Command Setup Time
twcs
0
0
0
ns
17
CAS to WE Delay Time
tewD
40
43
50
ns
17
RAS to WE Delay Time
tRWD
95
105
120
ns
17
CAS Precharge to WE Delay Time
tCPWD
58
65
70
ns
17
17
Column Address to WE Delay Time
tAWD
60
65
75
ns
WE Lead Time Referenced to RAS
tRWL
25
25
25
ns
WE Lead Time Referenced to CAS
tewL
15
15
15
ns
CAS Setup Time (CAS before RAS Refresh)
tCSR
5
5
5
ns
CAS Hold Time (CAS before RAS Refresh)
tCHR
10
10
10
ns
WE Setup Time
twSR
10
10
10
ns
WE Hold Time
twHR
15
15
15
ns
Refresh Time
tREF
64
64
64
ms
Notes
1. All voltages are referenced to GND.
2. After power up, wait more than 100 J1S and then, execute eight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. Iccl, 1eC3, IeC4 and Iccs depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Iec3 is measured assuming that all column address inputs are held at either high or low.
6. IeC4 is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. Iccl and IeC3 are measured aSSllming that address can be changed once or less during RAS ~ VIL
(MAX.) and CAS ~ VIH (MIN.).
S. AC measurements assume IT = 5 ns.
9. AC Characteristics test condition
(1) Input timing specification
VIH IMIN.I
= 2.4 V
VIL IMAX.l
=0.8 V
···········~······i
i
______________
..
:
I
I
:
I
~
t1 = 5 ns
.. .
,
I
I
: :
,:-
tT =5 ns
(2) Output timing specification
VOH IMIN.l
= 2.4 V
VOL IMAltI
=0.4 V
285
NEe
MC-424000AC72F
10. For read cycles, access time is defined as follows:
Input Conditions
tRAD ~ tRAD (MAX.I and tRCD ~ tRCD (MAX.I
tRAD
> IRAD IMAX.I
tRCD
> tRCD IMAX.I
and tRCD ~ tRCD IMAX.I
Access Time
Access Time from RAS
tRACIMAX.1
tRAC IMAX.I
tAAIMAX.1
tRAD
+ IAA IMAX.I
tCACIMAX.1
tRCD
+ tCAC IMAX.I
tRAO (MAX.( and tRCO (MAX.( are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAO ~ tRAO (MAX.(
and tRCO
~
tRCO (MAX.( will not cause any operation problems.
11. Loading conditions are 2 TTLs and 100 pF.
12. tOFF (MAX.( and tOEZ (MAX.( define the time at which the output achieves the condition of Hi-Z and
are not referenced to VOH or VOL.
13. tCRP (MIN.( requirements should be applied to RAS/CAS cycles.
14. Either tRCH (MIN.( or tRRH (M(N.( should be met in read cycles.
15. tWPIMIN.( is applied to late write cycles or read modify write cycles. In early write cycles, twCH(MIN.(
should be met.
16. tos (MIN.( and tOH (MIN.( are referenced to the CAS falling edge in early write cycles. In late write
cycles and read modify cycles, they are referenced to the WE falling edge.
17. If twcs
~
twcs (MIN.(, the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWO ~ tRWO (MIN.(, tewo ~ tcwo (MIN.(, tAWO ~ tAWO (MIN.( and tcPWO ~ tcPWO (MIN.(, the cycle
is read modify write cycle and the data out will contain data read from the selected cell. If neither
of the above conditions is met, the state of the data out is indeterminate.
286
Timing Chart
Please refer to Timing Chart 7, page 429.
287
NEe
MC-424000AC72F
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A
y
s
(OPTIONAL HOLES)
J-r~---H~--~K~--~
E
D
C
r[j'[j'DID"'I~IIIIj'[j'D'D~
detail of
® part
detail of
® part
W
-li-
~x
D
ITEM
A
B
e
-ll
it
D
E
P
G
H
I
D
K
J
L
M
N
P
Q
INCHES
5.25±0.006
0.450
1.450
0.250
2.150
0.250
0.050 (T.P.)
0.350
0.925
1.661
0.700
1.000
0.156 MAX.
0.039
RO.079
O. 157~g:gg~
R
4.0±0.1
s
~3.0
~0.116
T
1.27±0.1
4.0 MIN.
0.25 MAX.
1.0±0.05
2.54 MIN.
3.0 MIN.
3.0 MIN.
0.05±0.004
0.157 MIN.
0.010 MAX.
0.039±0.002
0.100 MIN.
0.118 MIN.
0.118 MIN.
M16BS-50A2
U
V
W
X
Y
Z
288
MILLIMETERS
133.35±0.13
11.43
36.83
6.35
54.61
6.35
1.27 (T.P.)
8.89
23.495
42.18
17.76
25.4
4.0 MAX.
1.0
R2.0
PRRELIMINARY DATA SHEET
NEe
MOS INTEGRATED CIRCUIT
MC-424000LAB72F
3.3 V OPERATION 4 M-WORD BY 72-BIT DYNAMIC RAM MODULE
FAST PAGE MODE (ECC)
Description
The MC-424000LAB72F is a 4,194,304 words by 72 bits dynamic RAM module on which 18 pieces of 16 M
DRAM: IlPD4217400L are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply lino for noiso roduction.
Features
• 4,194,304 words by 72 bits organization
• Fast access and cycle time
Access time
(MAX.)
Family
RtN cycle time
(MIN.)
Power consumption
(MAX.)
Active
MC-424000LAB72-A60
SO ns
110 ns
S.52W
MC-424000LAB72-A70
70 ns
130 ns
5.B7W
MC-424000LAB72-ABO
BO ns
150 ns
5.22W
•
2,048 refresh cycles/32 ms
•
CAS before RAS refresh, RAS only refresh, Hidden refresh
•
168-pin dual in-line memory module (Pin pitch = 1.27 mm)
•
Single +3.3 V ±0.3 V power supply
Standby
1BOmW
(CMOS level input)
Ordering Information
Part number
Access time
(MAX.)
MC-424000LAB72F-A60
60 ns
MC-424000LAB72F-A70
70 ns
MC-424000LAB72F-ABO
80 ns
Package
Mounted devices
168-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
18 pieces of IlPD4217400LG3
(300 mil TSOP(II)
[Double side!
The Information In thl. document ...ublect to chen"e without notice.
Ml0520EJ5VODSOO (Japan)
289
NEe
MC-424000LAB72F
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
o
PO and 10 Table
Access Time
Pin
Name
Pin
No.
60 ns
70 ns
P01
79
H
H
H
P02
163
H
H
H
P03
80
L
L
L
H
80 ns
P04
164
H
H
PD6
81
L
L
L
PD6
166
H
L
H
PD7
82
H
H
L
PD8
166
L
L
L
100
83
GND
GND
GND
101
167
GND
GND
GNO
Remark H:
VOH.
L:
VOL
AO - A10. BO : Address Inputs
I/O 0 -I/O 71 : Data Inputs/Outputs
RASO. RAS2 : Row Address Strobe
CASO. CAS4
Column Address Strobe
WED, WE2
Write Enable
OEO,OE2
Output Enable
POE
Presence Detect Enable
P01 - PD8
Presence Detect Pins
100,101
Identity Pins
Vee
Power Supply
GND
Ground
NC
0
No connection
NEe
MC-424000LAB72F
Block Diagram
RASO
OEO
WEO
CASO
RAS2O-----------'
OE2o-oD~------~---.
WE2o-~--------~,
!
•
CAS4 o-oD~---.
1/00
1/01
1/02
1/03
I/O 4 CAS RAS WE OE
1/03
DO
1/02
1/01
1/04
1/05
1/06
1/07
I/O 4 CAS RAS WE OE
1/03
D1
1/02
I/O 1
1/08
1/09
I/O 10
1/011
I/O 4 CAS RAS WE OE
1/03
02
1/02
1/01
1/012
1/013
1/014
1/015
I/O 4 CAS RAS WE OE
1/03
03
1/02
I/O 1
1/016
1/017
1/018
1/019 e>--I>
I/O 4 CAS RAS WE OE
1/03
D4
1/02
1/01
1/020 e>--I>
1/021
I/O 22 e>--I>
1/023
I/O 4 CAS RAS WE OE
1/03
D5
1/02
1/01
1/024
I/O 25
1/026 e>--I>
I/O 27
I/O 4 CAS RAS WE OE
1/03
D6
1/02
I/O 1
1/028 e>--I>
1/029 e>--I>
1/030 e>--I>
1/031 e>--I>
I/O 4 CAS RAS WE OE
1/03
07
1/02
1/01
1/032
1/033
1/034
1/035
I/O 4 CAS RAS WE OE
1/03
08
1/02
1/01
r-----,:;:!:::,-;:::!:::-::::!~~
1/036
1/037
1/038
1/039
+ + + +
~
~
~
~
~
~
~
~
~
~
+ ~
~
~
1/040
1/041
1/042
1/043
~
1/044
1/045
1/046
1/047
~
1/048
1/049
1/050
1/051
+
1/052
1/053
1/054
1/055
~
1/056
1/057
1/058
1/059
~
1/060
1/061
1/062
1/063
+ + + +
1/064
1/065o.--~
1/066
1/067
+ + ~ ~
AO 0 - [ > - - - AO: 00- 08
BOo-[>---AO: 09-017
A1-Al00-[>--- 00-017
1/068
1/069o.--~
1/070
1/071
POE~
P01- P08~ Vee or GNO
100. 101
Remark 00 - 017 : pP04217400L
NC or GNO
0
Vee 0
GNOo
:2:
•
=r CO-C1 ?
00-017
00-017
291
NEe
MC-424000LAB72F
Electrical Specifications Notes 1, 2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-0.5 to +4.6
V
Supply voltage
Vee
-0.5 to +4.6
V
Output current
10
20
mA
Power dissipation
Po
20
W
Operating ambient temperature
TA
oto +70
'C
Storage temperature
.Tota
-55 to +125
'C
Caution Exposing the device to stress above tho.. Iistad in Absolute Maximum Ratings could ceu..
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operationalsaction of this specification. Exposure to AbsoluteMaximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Condition
MIN.
TYP.
3.3
MAX.
Unit
Supply voltnge
Vee
3.0
3.6
V
High level input voltage
VIH
2.0
Vee + 0.3
V
Low level input voltage
VIL
-0.3
+0.8
V
Oporating nmbiont temperature
TA
0
70
'C
MAX.
Unit
20
pF
Copacitance
(TA
= 25 'C, f =1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
292
Symbol
Symbol
Test Condition
MIN.
TYP.
CII
AO-A10,aO
CI2
WEO,WE2
20
CI3
RASO, RAS2
78
Cf4
CASO, CAS4
20
CIII
OEO,OE2
20
ClIO
1/00 - V071
20
pF
NEe
MC-424000lA1B72f
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Symbol
IccI
Test condition
=tAc IMIN.)
= 0 rnA
tRC
10
Standby current
RAS only refresh current
Operating current
IC02
IcC3
ICC!
0.2 V
RAS Cycling
CAS ~ V,H IMIN.)
tAC =tAc IMIN.)
10 = 0 mA
RAS S V,LIMAX.), CAS Cycling
=tpc IMIN.)
10 = o rnA
tpc
(Fast page model
CAS before RAS
RAS, CAS ~ V,H IMIN.)
---RAS, CAS ~ Vcc -
lea;
refresh current
Output leakage current
lOlL)
High level output voltage
VOH
Low level output voltage
VOL
Unit
Notes
1,810
rnA
3,4,7
1,630
1,450
100
1,810
3,4,6,7
rnA
3,4,6
rnA
3,4
1,450
1,270
1,090
910
lRAC
0
60
n~
1,810
~
70
liS
1,630
tRAC ,,8011"
1.450
V,=Ot03.6V
All other pins not undor tOgt = 0 V Othuru
-5
-5
+1
Vo = 0 to 3.6 V
Output is disabled (Hi-Zl
-5
+5
10 =-2.0 rnA
2.4
10 = +2.0 rnA
rnA
1,630
lilAC
,~
rnA
50
=tRC IMIN.)
10 = 0 rnA
I'IL)
MAX.
RAS Cycling
tRC
Input leakage current
MIN.
= 60 ns
tRAC =70 ns
tRAC =80 ns
10 = 0 rnA
10 = 0 rnA
tRAC = 60 ns
tRAC =70 ns
tRAC = 80 ns
tRAC = 60 ns
tRAC =70 ns
tRAC = 80 ns
tRAC
RAS, CAS Cycling
+5
/IA
JJA
V
0.4
V
293
NEe
MC-424000LAB72F
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
ReadlWrite Cycle Time
294
Symbol
tRc
tllAC
=60 ns
tllAC
=70 ns
tllAC
=80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Not•• 8, 9
Unit
130
160
ns
175
196
220
ns
ns
110
Notes
Read Modify Write Cycle Time
bIwc
Fast Page Mode Cycle Time
tPC
40
45
60
Read Modify Write Cycle Time (Fast Page Model
tl'IIWC
85
90
105
Access Time from RAS
WC
60
70
80
ns
10, 11
Access Time from CAS
teAc
20
23
25
ns
10, 11
Access Time Column Address
tv.
35
40
45
ns
10, 11
Access Time from CAS Precharge
tAc~
40
45
50
ns
11
Access Time from OE
tOEA
15
18
20
ns
11
RAS to Column Address Delay Time
WD
15
40
ns
10
CAS to Data Setup Time
tCLZ
0
0
0
ns
11
OE to Data Setup Time
toLZ
0
0
0
ns
11
Output Buffer Turn-off Delay Time from CAS
tOfT
0
ns
12
OE to Data Delay Time
tOED
15
Output Buffer Turn-off Delay Time from OE
toEZ
0
OE Hold Time
tOEH
0
OE Lead Time Referenced to RAS
tOEB
0
Transition Time (Rise and Fall)
tr
3
RAS Precharge Time
t".
40
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Model
tRABP
60
125,000
70
125,000
80
125,000
ns
RAS Hold Time
tMH
15
CAS Pulse Width
tCAS
15
CAS Hold Time
tCSH
60
RAS to CAS Doloy Time
tRCD
20
ns
10
CAS to RAS Procharge Time
tCRP
5
5
5
ns
13
CAS Precharge Timo
tCPN
10
10
10
ns
CAS Precharge Time (Fast Page Model
tcp
10
10
10
ns
RAS Precharge CAS Hold Time
tRPC
5
5
5
ns
RAS Hold Time from CAS Precharge
tRHCP
40
45
50
ns
Row Address Setup Time
lAsR
5
5
5
ns
Row Address Hold Time
lIIAH
10
10
12
ns
Column Address Setup Time
lAsc
0
0
0
ns
Column Address Hold Time
teAH
15
15
15
ns
Column Address Lead Time Referenced to RAS
WL
30
35
40
ns
Read Command Setup Time
tRcs
0
0
0
ns
Read Command Hold Time Referenced to RAS
!ftRH
0
0
0
ns
14
Read Command Hold Time Referenced to CAS
tRCH
0
0
0
ns
14
WE Hold Time Referenced to CAS
twcH
10
10
15
ns
15
WE Pulse Width
twr
10
10
15
ns
15
30
15
15
0
36
15
15
15
0
15
20
3
10,000
20
25
12
ns
50
n.
ns
ns
10,000
80
50
ns
ns
20
70
40
20
60
18
18
0
ns
0
50
50
10,000
20
0
0
3
0
20
0
50
17
ns
ns
n.
60
NEe
MC-424000LAB72F
Symbol
Parameter
tllAC
=60 ns
tllAC
=70 ns
tllAC
=80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Notes
Data·in Setup Time
tos
0
0
0
ns
16
Data-in Hold Time
tDH
10
15
15
ns
16
Write Command Setup Time
twca
0
0
0
ns
17
CAS to WE Delay Time
tcwD
40
43
50
ns
17
RAS to WE Delay Time
tllWD
95
105
120
ns
17
CAS Precharge to WE Delay Time
tcowu·
68
65
70
ns
17
17
Column Address to WE Delay Time
tAwo
60
65
76
ns
WE Lead Time Referenced to RAS
tAw!.
26
26
26
ns
WE Lead Time Referenced to CAS
tcwL
16
15
16
ns
CAS Setup Time (CAS before RAS Refresh)
tcsR
6
6
5
ns
CAS Hold Time (CAS before RAS Refresh)
tcHR
10
10
10
ns
WE Setup Time
twaR
10
10
10
ns
WE Hold Time
twHR
16
15
16
Refresh Time
tllEF
32
32
ns
32
ms
Not••
1. All voltages are referenced to GND.
2. After power up, wait more than 100 JlS and then, execute oight CAS before RAS or RAS only
refresh cycles as dummy cycles to initialize internal circuit.
3. ICCI, Icea, IcC! and Iccs depend on cycle rates (tRC and tpc).
4. Specified values are obtained with outputs unloaded.
5. Icea is measured assuming that all column address inputs are held at either high or low.
6. IcC! is measured assuming that all column address inputs are switched only once during each
fast page cycle.
7. Icc! and Icea are measured assuming that address can be changed once or less during RAS S VIL
IMAX.1 and CAS ~ VIH IMIN.I.
8. AC measurements assume tT = 5 ns.
9. AC Characteristics test condition
(1)
Input timing specification
VIH IMIN.!
= 2.0 V
VIL IMAX.!
=0.8 V
tr
=
ns
tr=5ns
(2) Output timing specification
VOH IMIN.!
=2.0 V
VOL 1MAX.!
=O.B V
::::~:=('------')-295
NEe
MC-424000LAB72F
10. For read cycles, access time is defined as follows:
Input Conditions
13.
14.
15.
16.
17.
296
Access Time from RAS
tAAO S tAAO IMAX.1 and tRCO S tAco 1MAlC.1
lIlAc IMAlC.I
lIIAclMAXJ
tAAO > tAAO IMAX.1 and tACO S tAco 1MAlC.1
fAA IMAlC.I
tllAD + fAA 1MAlC.1
. tCAC IMAXJ
tRCo + !CAc 1MAlC.1
tACO > tRCD 1MAlC.1
11.
12.
Access Time
tRAD (MAX.! and tRCD (MAX.! are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, 1M or tCAC) is to be used for
finding out when output data will be available. Therefore, the input conditions tRAo ~ tRAD (MAX.!
and tRCD ~ tRCD (MAlt! will not cause any operation problems.
Loading conditions are 1 TIL and 100 pF.
tOFF (MAX.! and tOEZ (MAX.! define the time at which the output achieves the condition of Hi-Z and
are not referenced to VOH or VOL.
tCRP (MIN.! requirements should be applied to RAS/CAS cycles.
Either tRCH (MIN.! or tRRH (MIN.! should be met in read cycles.
twp (MIN.! is applied to late write cycles or read modify write cycles. In early write cycles, twCH (MIN.)
should be met.
tos (MIN.! and tOH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write
cycles and read modify cycles, they are referenced to the WE falling edge.
Iftwcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWD ~ tRWO (MIN.!, tCWD ---- AD : DO, 01
0-£>---- AD : 02, 03
A 1 - A9 0-£>---- DO - 03
AD
80
PDE~
POl - PD8
o-----ce:J-
100, 101 0
Vee or GNO
NC or GNO
Vee 0>---::1:-'---' 00-03
GNDO
Remark
DO - 03 : J,tP04218165
=r CO-C3 • 00-03
303
NEe
MC-421000FA64FB
Electrical Specifications
Notes 1, 2
Absolute Maximum Ratings
Symbol
Parameter
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
mA
Power dissipation
Po
6
W
Operating ambient temperature
TA
oto +70
'C
Storage temperature
Tat.
-65 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthisspecification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Condition
MIN.
TYP.
5.0
MAX.
Unit
Supply voltage
Vee
4.75
5.25
V
High level input voltage
VIIi
2.4
Vee + 1.0
V
Low level input voltage
VIL
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
'C
Capacitance ITA
= 25 'C, f = 1 MHz)
Parameter
Input capacitance
Data Input/Output capacitance
304
Symbol
Symbol
Test Condition
MIN.
TYP.
MAX.
Unit
CII
AO - A9, BO
20
pF
Gil
WEO, WE2
20
Gil
RASO, RAS2
45
GI'
CASO - CAS7
20
G",
OEO,OE2
20
Cva
1/00 -1/063
20
pF
NEe
MC-421000FA64FB
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
RAS. CAS Cycling
Operating current
Icc 1
MIN.
tRAc=60 ns
MAX.
Notes
rnA
1.2.3
700
tRC = tRcIMIN.)
10=0 rnA
Unit
660
tRAc=70 ns
RAS. CAS 5; VIH IMIN.). 10 = 0 rnA
68
Standby current
Icc2
rnA
RAS. CAS 5; Vcc - 0.2 V. 10 = 0 rnA
64
RAS only refresh current
Icc3
RAS Cycling
CAS 5; VIH IMIN.)
tRc = tRC IMIN.)
lilAC = 60 ns
700
tllAC =70 ns
660
tIlAC" 60 I1Il
600
tHPC = tHPC IMIN.)
10 = OmA
tHAC u 70
flU
460
RAS Cycling
lilAC u 60 n tRAO (MAX.) and tRCO S tRCO (MAX.)
tAA (MAX.)
tRAO + tAA (MAX.)
tRCO > tRCO (MAl<.)
tCAC (MAX.)
tRCO + tCAC (MAl<.)
tRAO(MAX.) and tRCO(MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAO E; tRAO(MAl<.) and tRCO E;
tRCO/MAX.) will not cause any operation problems.
2. tCRP(MIN.) requirement is applied to RAS, CAS cycles.
Read Cycle
Symbol
Parameter
tRAc
=60 ns
MIN.
Access Time from RAS
tRAC
-
Access Time from CAS
tCAC
Access Time from Column Address
tAA
Access Time from OE
tOEA
3D
Column Address Lead TIme Referenced to RAS
tRAL
Read Command Setup Time
tRCS
0
Read Command Hold TIme Referenced to RAS
tRRH
0
tRAC = 70 ns
Unit Notes
MAX.
MIN.
MAX.
60
-
70
-
23
ns
20
35
20
-
ns
1
23
ns
1
40
ns
1
0
-
0
-
ns
2
35
ns
Read Command Hold Time Referenced to CAS
tRCH
0
-
0
-
ns
2
Output buffer Turn-off Delay TIme from OE
tOEZ
0
13
0
15
ns
3
CAS Hold Time to OE
tCHO
5
-
5
-
ns
ns
Notes 1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAD:iii tRAO (MAX.) and tRCO:iii tRCO (MAX.)
tRAC (MAX.)
tRAC (MAl<.)
tRAD > tRAO (MAX.) and tRCO:iii tRCO (MAX.)
tAA(MAX.)
tRAO + tAA (MAX.)
tRCO > tRCO (MAl<.)
tCAC (MAX.)
tRCO + tCAC (MAl<.)
tRAD(MAX.) and tRCO(MAX.) are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAc,1M or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAO E; tRAD(MAX.) and tRCO E;
tRCO(MAX.) will not cause any operation problems.
2.
3.
Either tRCH(MIN.) or tRRH(MIN.) should be met in read cycles.
tOEZ(MAl<.) defines the time when the output achieves the condition of Hi-Z and is not refernced VOH or
VOL.
307
NEe
MC-421000FA64FB
Write Cycle
Parameter
Symbol
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
-
10
-
ns
1
10
-
ns
1
12
0
-
ns
0
-
ns
-
ns
3
-
ns
3
WE Hold Time Referenced to CAS
twCH
10
WE Pulse Width
twP
10
WE Lead Time Referenced to RAS
tRWL
15
WE Lead Time Referenced to CAS
tCWL
10
WE Setup Time
twcs
0
OE
17
tOEH
0
-
Data-in Setup Time
tos
0
-
0
Data-in Hold Time
tOH
10
-
10
Hold Time
Note.
MAX.
Unit Notes
ns
ns
2
1. tWP(MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH(MIN.)
should be met.
2. If twcs
~ twcsIMIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
3.
tDsIMIN.) and tDHIMIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles
and road modify writo cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
tRAC
Pnrameter
Symbol
=60 ns
MIN.
Read Modify Writc Cyclo Time
tRWC
133
RAS to WE Delay Timo
tRWD
87
MAX.
-
tRAC
Unit
Note
MAX.
157
-
ns
99
-
ns
1
ns
1
ns
1
CAS to WE Delay Timo
tCWD
32
-
37
Column Address to WE Delay Timo
tAWD
52
-
59
Note 1.
=70 ns
MIN.
If twcs ~ tWCS(MIN.) the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWD ~ tRWD(MIN.), tCWD ~ tCWD(MIN.), !Awo ~ tAWO(MIN.), and tCPWD ~ tCPWD(MIN.), the cycle is a
read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.
308
NEe
MC-421000FA64FB
Hyper Page Mode
tRAC
Symbol
Parameter
Read I Write Cycle Time
tHPC
=60 ns
tRAc
=70 ns
Unit Notes
MIN.
MAX.
MIN.
MAX.
25
-
30
-
ns
RAS Pulse Width
tRASP
60
~25 OO(
70
12500C
ns
CAS Pulse Width
tHCAS
10
10000
12
10000
ns
CAS Precharge Time
tcp
10
-
10
-
ns
Access Time from CAS Precharge
tAcp
-
40
-
45
ns
CAS Precharge to WE Delay Time
tCPWD
52
-
69
ns
45
-
76
-
ns
5
-
ns
1
2
RAS Hold Time from CAS Precharge
tRHcP
40
Read Modify Write Cycle Time
tHPRWC
66
Data Output Hold Time
tOHC
5
OE to CAS Hold Time
tOCH
5
-
6
OE Precharge Time
tOEP
5
-
5
-
ns
twez
0
13
0
15
ns
3,4
WE Pulse Width
tWI'Z
10
-
10
-
ns
4
Output Buffer Turn-off Delay from RAS
,tom
0
13
0
15
ns
3.4
Output Buffer Turn-off Delay from CAS
tOFc
0
13
0
15
ns
3.4
Output Buffer Turn-off Delay from
Notes 1.
2.
WE
-
ns
ns
tHPC(MIN.1 is applied to access time from CAS
If twcs !: tWCS(MIN.I, the cycle is an early write cycle and the data out will remain Hi - Z through the
entire cycle. If tRWD !: tRWD(MIN.I, tCWD !: tCWDIMIN.I, tAwo !: tAWO(MIN.I, and tCPWD !: tCPWD(MIN.I, the cycle is
a read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.
3.
tOFclMAXl, tOFR(MAXI and tweZIMAX.1 define the time when the output achieves the condition of HI.Z and
4.
To make I/Os to Hi·Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The
is not referenced to VOH or VOL.
effective specification depends on'state of each signal.
(1) RAS, CAS: Inactive (at the end of read cycle)
WE : inactive, OE : active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE: inactive"DE : inactive ... tOEZ is effective.
---
---
---
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive
~the end of read cycle)
WE,OE:active and either tRRH or tRCH must be met.. • twez, twPz are effective.
309
NEe
MC-421000FA64FB
Re f res h C;ycIe
Parameter
CAS Setup Time
tRAC" 70 ns
MIN.
MAX.
MIN.
MAX.
tCSR
5
-
5
-
tCHR
10
RAS Precharge CAS Hold Time
tRPe
5
-
WE Hold Time (Hidden Refresh Cycle)
twHR
15
-
CAS Hold Time
310
tRAC = 60 ns
Symbol
(CAS before RAS Refresh)
10
5
15
Unit
ns
ns
ns
ns
Note
Timj.ng Chart
Please refer to Timing Chart 9, page 457.
311
NEe
MC-421000FA64FB
168 PIN DUAL IN-UNE MODULE (SOCKET TYPE)
A
-
l=
-+
S
(OPTIONAL
z- r--
-y
I
,.-...
I[:~:::::~::::]
.. t-[8J
J
CI
~CI
..
HOLEs} ,"!nmm'1....
®J
0 [~:::~~:~:::]I
It
{II
0
--r\-®
K
1-8
'l,
G
~
detail of
e
E
'lro
mnmm U111111111 """""""""6"""1111 '" """""""""""""" ~
®
detail of
part
@ part
02
v
x
ITEM MILLIMETERS
A
133.35:1:0.13
B
11.43
C
36.83
0
6.35
01
2.0
D2
3.125
54.61
E
G
6.35
H
1.27 (T.P.)
8.89
J
23.495
K
42.18
L
17.78
M
25.4:1:0.13
N
9.0 MAX.
1.0
P
Q
R2.0
R
4.0:1:0.1
0.157:8:g~
S
T
U
;3.0
1.27:1:0.1
4.0 MIN.
0.25 MAX.
;0.118
0.05:1:0.004
0.157 MIN.
0.010 MAX.
W
1.0:1:0.05
0.039:8:rJ
X
2.54:1:0.10
3.0 MIN.
3.0 MIN.
0.100:1:0.004
0.118 MIN.
0.118 MIN.
M1685-60A&
V
Y
Z
312
INCHES
5.25:1:0.006
0.450
1.450
0.250
0.079
0.1230
2.150
0.250
0.05 (T.P.)
0.350
0.925
1.881
0.7000
1.000:1:0.006
0.355 MAX.
0.039
RO.079
PRELIMINARY DATA SHEET
\lEe/
MOS INTEGRATED CIRCUIT
MC..422000FA64FB
2 M·WORD BY 64·BIT DYNAMIC RAM MODULE
HYPER PAGE MODE
Description
The MC-422000FA64FB is a 1,048,576 words by 64 bits dynamic RAM module on which 8 pieces of 16 M
DRAM: pPD4218165 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the
surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• Hyper page mode (EDO)
• 2,096,152 words by 64 bits organization
• Fast access and cycle time
Access time
(MAX.)
R/W cycle time
MC-422000FA64-60
60 ns
104 ns
MC-422000FA64-70
70 ns
Family
•
•
•
•
(MIN.)
Hyper page
mode cycle Time
(MIN.)
25 ns
124 ns
30 ns
Power consumption
(MAX.)
Active
Standby
3.73W
357 mW
3.52W
(CMOS level input)
1,024 refresh cyclesl16 ms
CAS before RAS refresh, RAS only refresh, Hidden refresh
168-pin dual in-line memory module (Pin pitch = 1.27 mm)
Single +5.0 V ±O.25 V power supply
Ordering Information
Part number
Access time
(MAX.)
MC-422000FA64FB-60
60 ns
MC-422000FA64FB-70
70 ns
Package
168-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plating
Mounted devices
8 pieces of I'PD4218166LE
(400 mil SOJ)
[Single side!
The Information In this document Jo subject to chang" without notlcD.
M10559EJ1VODSOO (Japan)
313
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MC-422000FA64FB
Pin Configuration
16B-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plating)
o
0
GND
VOO
VO 1
VO 2
V03
Vee
V04
VO 5
1/06
V07
NC
GND
NC
GND
V040
V041
V042
V043
V044
V08
1/09
VO 10
VO 11
VO 12
V045
V046
V047
VO 13
VO 14
VO 15
Vee
NC
GND
NC
NC
Vee
NC
CAS1
CAS3
NC
NC
GND
Al
Vee
NC
GND
NC
NC
Pin
No.
60 ns
70 ns
P01
79
H
H
A6
P02
163
L
L
NC
NC
P03
80
H
H
Vee
P04
164
L
L
NC
NC
GND
ITE2
P05
81
H
H
P06
165
H
L
P07
82
H
H
A2
A4
A3
A9
Vee
125
126
127
12B
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
314
0
NC
BO
GND
NC
NC
ViS5
u;.s,-
Access Time
Pin
Name
OEO
GND
AO
A5
A7
NC
NC
PO and ID Table
Vee
WEi
CASO
CAS2
FiASli
AS
RA!r1
CA54
CAS6
WE2
P08
166
H
H
100
83
GNO
GNO
V048
V049
NC
NC
VO 16
VO 17
101
167
GNO
GNO
V051
V052
V053
VO 18
VO 19
VO 20
VO 21
Remark H: VOH, L :VOL
V054
VO
mE
Vee
Vee
NC
NC
GND
VOSO
Vee
GND
Vee
NC
22
NC
NC
NC
NC
VO 23
NC
V056
VO 24
V057
V058
V059
V060
VO 25
VO 26
VO 27
V02B
NC
NC
NC
NC
V055
GND
Vee
V061
V062
V063
NC
GND
P02
P04
P06
P08
IDI
Vee
GND
Vee
V029
V030
V031
NC
GND
POI
P03
P05
P07
IDO
Vee
0
AO - A9, BO :
I/O 0 - I/O 63 :
RASO - RAS2:
CASO - CAS7:
WEO, WE2
OEO,OE2
POE
P01 - P08
100,101
Vee
GNO
Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Presence Detect Enable
Presence Detect Pins
Identity Pins
Power Supply
Ground
NC
No connection
NEe
MC-422000FA64FB
Block Diagram
RASOo--------,
RAS2
RASlO------------+-------------~
RAS3
OEO
OE2
WEO
WE2
LCAS
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
UCAS
1(016
1/015
1/014
1/013
1/012
1(011
1/010
1(09
CAS4
LCAS
VOl
V02
1/03
D4
D2
BO 0----[>-- AO : 02. 03. 06. 07
Al-A9o----[>-- 00-07
1/041(}4I/O 42 (}4- --_.
I/O 43 (}4---I/O 44(}4 --
------
--
RAS WE OE
VO 16
VO 15
V014
VO 13
VO 12
VOll
V010
V09
LCAS
RASWE
5E
VOl
V02
V03
V04
V05
V06
D3
1/07
VOS
UCAS
D7
V016
V015
1/014
1/013
1/012
1/011
V010
1/09
POE~
POl - POS o------{J-- Vee or GNO
IDO. 101 0
VccO
GNOo
Remark DO· D7 : I'PD4218165
De
UCAS
LCAS RASWE OE
1/01
1/02
1/03
1/04
1/05
1/06
1/07
OS
I(OS
UCAS
1/016
1(015
1(014
1(013
1(012
1(011
1(010
1(09
AO 0----[>-- AO : DO. 01. 04. 05
V04
V05
V06
V07
V08
NC or GNO
:to
• 00-07
,-CO-C7, 00-07
315
NEe
MC-422000FA64FB
Electrical Specifications Notas 1, 2
Absolute Maximum Ratings
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
Vr
-1.0 to +7.0
V
Supply voltage
Vee
-1.0 to +7.0
V
Output current
10
50
mA
Parameter
Power 'dissipation
Po
6
W
Operating ambient temperature
TA
oto +70
'C
Storage temperature
Toto
-55 to +125
'C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of thio specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Condition
MIN.
TYP.
MAX.
Unit
Vee
4.75
5.0
5.25
V
High level input voltage
VIH
2.4
Vee + 1.0
V
Low level input voltage
VIL
-1.0
+0.8
V
Operating ambient temperature
TA
0
70
'C
Capacitance (TA
=25 'C, f =, MHz)
Parameter
Input capacitance
Data Input/Output capacitance
316
Symbol
Supply voltage
Parameter
Symbol
Test Condition
MIN.
TYP.
MAX.
Unit
Cil
AD - A9, 80
20
pF
CI2
WEO,WE2
20
CI3
RASO - RAS2
45
CI4
CAS!)' - CAS7
20
Cft;
OEO,OE2
20
ClIO
1/00 - V063
20
pF
NEe
MC-422000FA64FB
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current
Test condition
Symbol
Icci
RAS. CAS Cycling
tRC = tRcIMIN.)
10= 0 mA
MIN.
tRAc=60 ns
MAX.
Unit
Notes
mA
1.2.3
710
tRAc=70 ns
670
RAS. CAS ~ V,H IMIN.). 10 = 0 mA
76
Standby current
Icc2
mA
RAS. CAS ~ Vcc - 0.2 V. 10 = 0 mA
68
RAS only refresh current
IC03
RAS Cycling
CAS ~ V,H IMIN.)
tRC = tRC IMIN.)
10= 0 mA
RAS ~ V,L IMAX.)
Operating current
(Hyper page model
IcC4
CAS Cycling
tHPC = tHPC IMIN.)
10= 0 mA
RAS Cycling
CAS before RAS
refresh current
Input leakage current
Output leakage current
Icc5
lOlL)
710
tRAc=70 ns
670
tRAc=60 ns
510
tRAc=70 ns
470
tRAc=60 ns
710
tRAc=70 ns
670
tAc = tRC IMIN.)
10= OmA
II (L)
tRAc=60 ns
VI = Oto 5.5 V
all other pins not under test = 0 V
Vo = Oto 5.5 V
I RAS
-10
+10
lathers
-5
+1
-10
+10
mA
1.2.3,4
mA
1.2.6
mA
1.2
IlA
IlA
Output is disabled (Hi·Z)
High level outputvoltageLo\,\
VOH
10=-2.5 mA
level output voltage
VOL
10 = +2.1 mA
Notes
2.4
V
0.4
V
1. icC" IC03, Icc4, Icc5 depend on cycle rates (tAc and tHPC).
2.
Specified values are obtained with outputs unloaded.
3. Icci and IC03 are measured assuming that address can be changed once or less during RAS :i!
VIL(MAX.) and CAS ~ VIH(MIN.).
4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page cycle.
317
NEe
MC-422000FA64FB
AC Characteristics (Recommended Operating Conditions unl... otherwi.. noted)
AC Characteristics Test Conditions
(2) Output timing specification
(1) Input timing specification
VIH IMIN.) = 2.4
V---------~-----
VOH IMIN.)
I
I
I
I
I
'ii
VIL IMAX.) = 0.8 V·------------
I
I
_.
I
I
14
tT=2ns
I
I
I
I
= 2.4 Vn----_-:::_-.-~
VOL IMAX.) =
I
0.4
"'\
m
V------------\..\,,____-JI
.. : ;..
tT=2ns
(3) Loading conditions are 100 pF + 1 TTL.
Common to Read, Write Cycle
Parameter
tRAC
=60 ns
tRAC
=70 ns
Unit Notes
MIN.
MAX.
MIN.
MAX.
124
-
ns
60
-
ns
10
-
ns
Read I Write Cycle Time
tRC
104
RAS Precharge Time
tRP
40
CAS Precharge Time
tCPN
10
-
RAS Pulse Width
tRAS
60
10000
70
10000
ns
CAS Pulse Width
tCAS
10
10000
12
10000
ns
ffAS
Hold Time
tRSH
10
-
ns
CAS Hold Time
tCSH
40
-
12
60
-
ns
RAS to CAS Delay Time
tRCO
14
45
14
52
ns
RAS to Column Address Delay Time
tRAD
12
30
12
35
ns
1
CAS to RAS Precharge Time
tCRP
5
-
5
-
ns
2
Row Address Setup Time
lAsR
5
-
6
-
ns
Row Address Hold Time
tRAH
10
-
10
-
ns
Column Address Setup Time
lAsc
0
-
0
tCAH
10
12
OE Lead Time Referenced to RAS
tOES
0
-
ns
Column Address Hold Time
CAS to Data Setup Time
tCLl
0
Data Setup Time
tOll
0
-
OE to Data Delay Time
tOED
13
-
15
OE to
318
Symbol
0
0
0
ns
ns
-
ns
ns
ns
Masked Byte Write Hold Time Referenced to RAS
tMRH
0
-
0
-
ns
Transition Time (Rise and Fall)
tT
1
50
1
50
ns
Refresh Time
tREF
-
16
-
16
ms
1
•••
NEe
MC-422000FA64FB
Notes 1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
Access Time from RAS
tRAO;S tRAO (MAX.) and tRCO;S tRCO (MAX.)
tRAC (MAX.)
tRAC (MAlt)
tRAO > tRAO (MAX.) and tRCO;S tRCD (MAX.)
tAA(MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD(MAX.) and tRCO(MAX.1 are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD ~ tRAO(MAX.) and tRCD ~
tRCD(MAX.) will not cause any operation problems.
2. tCRP(M)N.) requirement is applied to RAS, CAS cycles.
Read Cycle
Parameter
Symbol
!RAc
~
MIN.
-
60 ns
tRAC
~
70 ns
Unit Notes
MAX.
MIN.
MAX.
60
-
70
ns
1
20
-
23
ns
1
35
-
40
ns
1
Access Time from RAS
tRAc
Access Time from CAS
tCAC
Access Time from Column Address
tAA
-
Access Time from OE
tOEA
-
20
-
23
ns
Column Address Lead Time Referanced to RAS
tRAL
30
-
35
-
ns
Read Command Setup Time
tRCS
0
0
-
ns
Read Command Hold Time Referenced to RAS
tRRH
0
0
-
ns
2
0
0
-
ns
2
3
-
Read Command Hold Time Referenced to CAS
tRCH
Output buffer Turn-off Delay Time from OE
tOEZ
0
13
0
15
ns
CAS Hold Time to OE
tCHO
5
-
5
-
ns
Notes 1. For read cycles, access time is defined as follows:
Input Conditions
Access Time
tRAO;S tRAO (MAX.I and tRCO:S tRCD (MAX.I
tRAO
> tRAO (MAX.I and tRCD:i2
tRCD
> tRCD (MAX.I
tRCD (MAX.I
Access Time from RAS
tRAC (MAX.I
tRAC (MAX.)
tAAIMAX.1
tRAD + tAA (MAX.I
tCAC IMAX.)
tRCD + tCAC (MAX.I
tRAD(MAX.) and tRCD(MAX.1 are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD
ii: tRAD(MAX.) and tRCD
~
tRcDIMAX.1 will not cause any operation problems.
2. Either tRCHIM)N.1 or tRRHIMIN.1 should be met in read cycles.
3. tOEZIMAX.) defines the time when the output achieves the condition of Hi-Z and is not refernced VOH or
VOL.
319
NEe
MC-422000FA64FB
Write Cycle
Parameter
Symbol
tRAC
=60 ns
tRAC
=70 ns
MIN.
MAX.
MIN.
MAX.
-
WE Hold Time Referenced to CAS
tWCH
10
twp
10
-
10
WE Pulse Width
WE Lead Time Referenced to RAS
tRwL
15
-
17
WE Lead Time Referenced to CAS
tCWL
10
-
12
WE Setup Time
twcs
0
-
0
10
DE: Hold Time
tOEH
0
-
0
Data-in Setup Time
tDS
0
-
0
Data-in Hold Time
tDH
10
-
10
Unit Notes
ns
1
ns
1
ns
ns
ns
2
ns
ns
3
ns
3
Notes 1. tWP(MIN.1 is applied to late write cycles or read modify write cycles. In early write cycles, twCH(MIN.1
should be met.
2.
If twcs ;;; tWCS(MIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.
3.
tDS(MIN.1 and tDHIMIN.1 are referenced to the CAS falling edge in early write cycles. In late write cycles
and read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter
Symbol
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
Unit
Note
Read Modify Write Cycle Time
tRWC
133
-
157
-
ns
RAS to WE Delay Time
tRWD
87
99
-
ns
1
37
1
59
-
ns
ns
1
CAS to WE Delay Time
tCWD
32
-
Column Address to WE Delay Time
tAWD
52
-
Note 1.
If twcs ;;; twCS(MIN.1 the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWD ;;; tRWD(MIN.I, tCWD ;;; tCWDIMIN.I, tAWO ;;; tAwoIMIN.I, and tCPWD ;;; tCPWDIMIN.I, the cycle is a
read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.
320
NEe
MC-422000FA64FB
Hyper Page Mode
tRAC = 60 ns
Symbol
Parameter
MIN.
MAX.
tRAC = 70 ns
MIN.
MAX.
Unit Notes
Read I Write Cycle Time
tHPC
25
30
-
ns
RAS Pulse Width
tRAsP
60
2500C
70
12500C
ns
CAS Pulse Width
tHCAS
10
10000
12
10000
ns
CAS Precharge Time
tcp
10
-
10
-
ns
Access Time from CAS Precharge
tAcp
-
40
-
45
ns
CAS Precharge to WE Delay Time
tcpwo
52
-
59
-
ns
tRHcP
40
45
-
ns
Read Modify Write Cycle Time
tHPRWC
66
75
tDHC
5
OE to CAS Hold Time
tacH
6
-
5
-
ns
Data Output Hold Time
-
OE Precharge Time
tOEr
6
-
6
-
ns
Output Buffer Turn-off Delay from WE
tWEZ
0
13
_._._---.
16
ns
3,4
WE Pulse Width
tWI'Z
10
-..
-010
-
ns
4
Output Buffer Turn-off Delay from RAS
tom
0
13
0
15
ns
3.4
Output Buffer Turn-off Delay from CAS
tOFc
0
13
0
15
ns
3.4
RAS Hold Time from
Notes 1.
2.
CAS Precharge
------
-
- - - - - ---- ---.
5
1
2
ns
ns
tHPCIMIN.) is applied to access time from CAS
If twcs ~ twcsIMIN.), the cycle is an early write cycle and the data out will remain Hi - Z through the
entire cycle. If tRWD
s= tRWDIMIN.), tCWD s= tCWDIMIN.), tAwo s= tAWQlMIN.), and tCPWD s= tCPwoIMIN.), the cycle is
a read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.
3.
tDFCIMAX.), tOFRIMAlC.) and tweZIMAX.) define the time when the output achieves the condition of Hi-Z and
4.
To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The
is not referenced to VOH or VOL.
effective specification depends on state of each signal.
(1) RAS, CAS: Inactive (at the end of read cycle)
WE : inactive, OE : active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE : inactive, OE : inactive '" tOEZ is effective.
---
---
---
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive
(at the end of read cycle)
WE,OE:active and either tRRH or tRCH must be met.. • twez, twPz are effective.
321
NEe
MC-422000FA64FB
Ref res h C;YCIe
tRAC
Parameter
322
Symbol
MIN.
CAS Setup Time
tCSR
5
CAS Hold Time (~ before RAS Refresh)
tCHR
10
RAS Precharge CAS Hold Time
tRPC
5
WE Hold Time (Hidden Refresh Cycle)
twHR
15
=60 ns
tRAc
=70 ns
MIN.
MAX.
-
5
-
-
10
MAX.
5
15
-
Unit
ns
ns
ns
ns
Note
Timing Chart
Please refer to Timing Chart 9, page 457.
323
NEe
MC-422000FA64FB
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
f-----A------I
detail of
® part
detail of
® part
ITEM
A
B
C
MILLIMETERS
INCHES
a
133.35±0.13
11.43
36.83
6.35
2.0
3.125
54.61
6.35
1.27 (T.P.)
8.89
23.495
42.18
17.78
25.4±0.13
9.0 MAX.
1.0
R 2.0
R
4.0±0.1
0.157~g:gg~
S
T
U
V
113.0
1.27±0.1
4.0 MIN.
0.25 MAX.
110.118
0.05±0.004
0.157 MIN.
0.010 MAX.
o
01
02
E
G
H
I
J
K
L
M
N
P
5.25±0.006
0.450
1.450
0.250
0.079
0.1230
2.150
0.250
0.05 (T.P.)
0.350
0.925
1.661
0.7000
1.000±0.006
0.355 MAX.
0.039
R 0.079
W
1.0±0.05
0.039~g:gg~
X
Y
Z
2.S4±0. 10
3.0 MIN.
3.0 MIN.
0.1 00±0.004
0.118 MIN.
0.118 MIN.
MI68S-50A7
324
PRELIMINARY DATA SHEET
~EC
MOS INTEGRATED CIRCUIT
MC 422000FB72F
a
2M -WORD BY 72-81T IDYNAMIC RAM MODULE
HYPER PAGE MODE (ECC)
Description
The MC-422000FB72F is a 2 097 152 words by 72 bits dynamic RAM module on
which 9 pieces of 16M DRAM ( uPD 4217805) are assembled.
This module provide high density and large quantities of memory in a small space
without utilizing the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
- Hyper page mode ( EDO)
- 2 097 152 words by 72 bits organization
- Fast access and cycle time
Access time
(MAX.)
Family
RIW cycle time
(MIN.)
Hyper page mode
cycle time (MIN.)
Power consumption
(MAX.)
Active
MC- 422000FB72-60
60 ns
104 ns
MC- 422000FB72-70
70ns
124 ns
25 ns
5.51w
30 ns
5.04w
Standby
368mw
(CMOS level)
- 2 048 refresh cycles/32 ms
-
-
-
- CAS before RAS refresh, RAS only refr~sh , Hidden refresh.
- 168-pin dual in-line memory module (pin pitch 1.27 mm)
=
- Single +5.0 V±0.2SV power supply
Ordering information
Part Number
Access time
(MAX.)
Package
MC- 422000FB72F-60
60ns
168-pin Dual In-line
Memory Module
MC- 422000FB72F-70
70ns
Edge connector: Gold plating
M1 0549EJ1 VODSOO (Japan)
(Socket Type)
Mounted devices
9 pieces of
uPD 421780SGS
(400mil TSOP)
[Double side]
The information in this document is subject to change without notice.
325
MC-422000FB721
Pin Configuration
168-pin Dual In-line Memory Module Socke, Type (Edge Connector: Gold plating)
o
o
GND
1/036
I/O 37
1/038
1/039
Vee
VOO
VOl
V02
V03
Vee
V04
V05
V06
V07
1/044
GND
I/O 45
GND
1/0<40
I/O 41
I/O 42
1/043
I/O 46
I/O 47
1/048
1/049
Vee
1/050
I/O 51
I/O 52
1/053
GND
NC
NC
Vee
NC
NC
NC
NC
NC
GND
AI
A3
A5
A7
A9
NC
NC
Vee
'25
126
'27
'28
'29
130
131
132
133
'34
'35
136
'37
'38
139
140
141
142
143
144
145
146
147
148
149
150
161
152
153
164
155
'68
157
'58
'59
160
161
162
163
164
165
166
'67
168
326
0
GND
NC
80
GND
NC
NC
NC
NC
I'lrr"
Vee
NC
NC
1/054
I/O 55
GND
I/O 66
I/O 57
1/066
I/O 59
Vee
1/060
NC
NC
NC
NC
I/O 61
1/062
1/063
GND
1/064
1/065
1/068
1/067
Vee
1/068
1/069
I/O 70
I/O 71
GND
PD2
PD4
PD6
PD6
101
Vee
V08
V09
VO 10
VO "
V012
VO'3
Vee
V014
VO 15
VO 16
VO 17
GND
NC
NC
Vee
~
CAs5
NC
§W
GND
AO
A2
A4
A6
A8
A'D
NC
PO and 10 Tabla
Vee
Pin
Name
Pin
No.
POI
PD2
PD3
PD4
PD5
PD6
P07
PDB
79
163
NC
NC
GND
~
eo
164
81
165
Acc8888 Time
60ns
70na
H
H
L
L
L
L
H
H
GND
H
L
H
82
H
H
168
L
L
GNO GND
I DO
B3
GNO GNO
167
10'
Nole) H: VOH, L: VOL
NC
NC
NC
NC
VO O-VO 71 : Data Inputs I Outputs
CAS4
NC
~
Vee
NC
NC
VO '8
VO '9
V020
V021
V022
V023
Vee
V024
H
AO - AID, BO: Address Inputs
V025
V026
V027
ro'iSO, fiAS2 : Row Address Strobe
CASo, CAS4 : Column Address Strobe
WED, WE2 : Write Enable
GND
V028
V029
V030
V03'
Vee
V032
V033
V034
V035
GND
POI
PD3
P05
PD7
100
Vee
0
OED, 0E2
: Output Enable
POE
: Presence Detect Enabla
POl- PDa
100, 101
Vee
GND
: Presence Delect Pins
: Iden,ity pins
: Power Supply
: Ground
NC
: No connection
MC·422000FB72F
Block Diagram
RASo
CEo
WEo
CASo
RAs2
...
5E"2 0-[>
~
~
I
....
CAS TiAS ~ ~
1/00
1/01
1/02
1103
1/08
1/04
1/05
1/06
1/07
1/04
1/03
1/02
1/01
1/08
1108 CAS RAS WE OE
1/09
1/010
1/011
1107
1106
1105
1/012
1/013
11014
1/04
1/07
1/06
1105
01
1103
1102
1101
1/01B
1/019
11020
11021
1I0B
CAS
1107
1106
1105
~ OE
1/023
1103
1102
1101
1/024
1/08 CAS RAS WE OE
11025
1/07
1/06
11022
I
1/026
1/027
1/028
1/029
11030
1/031
03
1104
I
1/032
1/033
1/034
1/035
1/036
1/037
1104
1103
1/038
1/039
1102
1101
05
1/044
1/045
1/046 0 - - 1/047 0 - - -
1/05
1/06
11048
11049
11050
11051
11052
11053
11054
11055
1/01 CAS RAS WE OE
1107
1/08
I
1/02
1/03
1/04
I
06
1105
1/06
1107
1I0a
I
I
1/01 CAS RAS WE OE
11056
11057
11058
11059
11060
11061
11062
11063
1/02
1/03
1/04
07
1105
1106
1107
IIOB
I
I I I
1101 CAS RAS
11064
11065
11066
11067
WE
OE
1102
1/03
1104
11068
11069
11070
11071
1/03
1/02
1/01
IIOB
1102
1103
1104
I
1/05
I
I
1101 CAS RAS WE OE
1/040
1/041
1/042
I
RAS
02
1/04
::::
....
I
I
1/016
1/017
CAs4
...
11043
DO
I
1/015
WE2
08
1/05
1/06
1/07
1/08
I
CAS RAS ~ ~
1/07
1/06
1105
04
AO
0-[>
..
AO: DO to D4
BO
-i>
..
AO:D5toD8
A1toA1~DOtoDB
NC or GND
100 to 101 •
PoE~
PD1 to PDB
o---q--- Vee or GND
Vee 0
GND.
:L CO- C8 ~
T
DO to 08
~ 001008
327
MC-422000FB72F
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Remark
Condition
Rating
Unit
Voltage on Any Pin Relative to GND
VT
-1.0 to +7.0
V
Supply voltage
vee
-1.0 to +7.0
V
Output current
10
50
mA
W
Power dissipation
PD
11
Operating temperature
Topt
Oto+70
Storage temperature
Tstg
-55 to +125
t
t
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device in not meant to be operated under conditions outside the limits
described in the operational sections of this specification. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
(NOTES: 1,2)
MIN.
TYP.
4.75
5.0
MAX.
Unit
5.25
V
Vec+ 1.0
V
High level input voltage
vee
vm
2.4
Low level input voltage
VIL
-1.0
+0.8
V
Ta
0
70
t
Supply voltage
Ambient temperature
CAPACITANCE (Ta=2St ,f=1 MHz)
Parameter
Input capacitance
Data Inputl
Output capacitance
328
MIN.
MAX.
Unit
CII
AO-AlO,BO
20
pF
CI2
'Wn1I,wn
20
pF
CI3
m1l,~
50
pF
CI4
20
pF
CIS
CAS'lJ, ~
t'mU, mn
20
pF
CVO
II00-J1071
20
pF
Symbol
Test condition
TYP.
MC-422000FB72F
DC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
PARAMEmR
Operating Current
Icd
Standby Current
Icc2
m
only refresh current
led
Operating Current
(Hyper Page Mode)
Icc4
CAS before RAS
iceS
refresh current
Input Leakage Current
Output Leakage Current
mST CONDmON
SYMBOL
MIN.
IRAc=6Ons
1RAc=70ns
RAS ,CAS Cycling
mc=lRc (MIN.) , lO=OmA
1050
960
RAS ,CAS
~
VIII (MIN.)
90
RAS ,CAS
~
Vcc-O.2V
70
--RAS Cycling, CAS
1RAc=6011s
1050
1RAc=70ns
960
Vn.. ,CAS Cycling
UIPC=UIPC (MIN .), IO=OmA
1RAc=600s
1RAc=70ns
870
mc=mc(MJN.)
IO=OmA
IRAc=6Ons
780
1050
1RAc=70ns
960
~
VIII
mc=mc(MIN.),IO=OmA
-RAS
~
--
VI=O to 5.25V
RAS
-10
+10
all other pins not under test = OV
others
-5
+1
-10
+10
II(L)
IO(L)
MAX.
Outputs are disabled (Hi - Z)
UNIT NOms
rnA
3,4,7
rnA
rnA
3,4,5,7
rnA
3,4,6
rnA
3,4
~
J.LA
VO=<> to 5.25V
High level output voltage
VOH
I0=-5.0mA
Low level output voltage
VOL
IO=+4.2mA
2.4
V
0.4
V
329
MC-422000FB721
AC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Notes 8,9
(1/2)
tRAc
PARAMETER
MIN.
tRAc
MAX.
-
Random Read or Write Cycle Time
IRC
104
Read Modify Write Cvcle Time
IRWC
133
Access Time from RAS
tRAC
60
Access Time from CAS
tCAC
Access Time from Column Address
tAA
Access Time from CAS Precbarge
tACP
Access Time from OE
tOEA
-
=70ns
UNIT NOlES
RAS to Column Address Delay Time
tRAD
CAS to Data Setup TlUIe
DE to Data Setup TlUIe
MIN.
MAX.
124
-
ns
70
157
ns
ns
lOll
23
ns
10,11
40
ns
10,11
45
ns
11
20
-
23
ns
11
12
30
12
35
ns
10
tCLZ
0
0
11
0
ns
11
OE to Data Delay Time
tOED
13
15
-
ns
tOLZ
-
Output Buffer Turn-off Delay Time from OE
tOEZ
0
13
0
15
ns
OE HoldTime
tOEH
0
0
0
-
ns
0
-
ns
1
50
1
50
ns
20
35
40
0
ns
12
OE Lead Time Referenced to RAS
tOES
Transition TlUIe ( Rise and Fall )
IT
RAS Precbarge Time
IRP
40
-
50
-
ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
ns
RAS Hold TlUIe
IRSH
10
12
-
ns
CAS Pulse Width
tCAS
10
12
10000
n.
CAS Hold Time
tCSH
40
-
50
-
ns
RAS to CAS· Delay Time
tRen
1<1-
45
14
52
_ns
10
tCRP
5
5
-
ns
13
tCPN
to
CAS to RAS
Prcchar~e
Time
CAS Prcchafl!e Time
330
=60ns
SYMBOL
RAS Prechafj!e CAS Hold Time
IRPC
RAS Hold TlUIe from CAS Prcchnrl!e
IRHCP
Row Address Setup Time
tASR
5
Row Address Hold TlUIe
tRAH
to
Column Address Setup Time
tASC
0
Column Address Hold Time
tCAH
to
Column Address Lead Time Referenced to RAS
tRAL
30
Read Command Setup Time
IRCS
0
Read Command Hold TlUIe Referenced to RAS
tRRH
0
Read Command Hold TlUIe Referenced to CAS
IRCH
0
WE Hold Time Referenced to CAS
tWCH
10
WE Pulse Width
tWP
10
Data-in Setun Time
IDS
0
Data-in Hold TlUIe
IDH
10
Write command Setup Time
tWCS
0
CAS to WE Delay Time
tCWD
32
RAS to WE Delay Time
IRWD
87
Column Address to WE Delay T1UIe
tAWD
52
5
40
10000
-
to
5
45
5
to
0
t2
35
0
0
0
10
10
0
10
0
37
99
59
-
-
-
ns
ns
ns
ns
n.
ns
ns
ns
ns
ns
14
ns
14
ns ItS
ns
15
n. IH,
ns
16
ns
17
ns
17
ns
17
ns
17
MC-422000FB72F
(2/2)
tRAc = 60ns
PARAMETER
WE Lead Time Referenced to RAS
WE Lead Time Referenced to CAS
CAS Setuo Time for CAS before RAS Refresh
CAS Hold Time for CAS before RAS Refresh
WE Setup Time
WE Hold Tune
tRWL
tr.WT.
tCSR
tCHR
tWSR
tWHR
tREF
Refresh Tune
tRAc= 70ns
UNIT NOTES
SYMBO
MIN.
MAX.
MIN.
15
10
5
10
-
17
12
5
10
-
10
-
15
-
32
10
15
-
MAX.
-
ns
ns
ns
ns
-
ns
-
ns
32 ms
HYPER PAGE MODE
tRAe ~ ti()l1~
PARAMETER
= 70ns
UNIT NOTES
MIN.
Read I Write Cycle Tune
IItAC
SYM80L
25
MAX.
MIN.
-
30
70
-
10
1RAs" Pulse Width
tHPC
tRASP
CAS Pulse Width
tHCA~
125,000
10 10,000
CAs Precbar2e Time
tCP
10
CAS Precbar2e to WE Delav Time
tCPWD
52
Read Modify Write Cycle Tune
Data Output Hold Time
OE to CAS Hold Time
OE Precbar2e Time
tHPRWC
tOHC
lOCH
tOEP
66
CAS Hold Time to OE
tCHO
5
Output Buffer Tum-off Delay from WE
WE Pulse Width
tWEZ
tWPZ
0
10
Output Buffer Tum-off Delay from RAS
tOFR
0
Output Buffer Tum-off Delay from CAS
tOFC
0
60
5
5
5
12
59
75
MAX.
-
ns
125,000 ns
10,000 ns
- ns
- ns
-
17
ns
5
5
5
- ns
- ns
-
5
13
0
10
0
ns
15 ns
ns
15 ns
18
13
13
0
15 ns
12, 18
-
18
- ns
-
12, 18
18
12, 18
Note.:
1. All voltages are referenced to GND.
2. After power up, walt more than 100 [.IS and then, execute eight CAS before RAS or RAS
only refresh cycles as dummy cycles to Initialize intemal circuit.
3. ICC1, Ice3, ICC4 and ICC5 depend on cycle rates (tRC and tHPC ) .
4. SpecHled values are obtained with outputs unloaded.
5. ICC3 is measured assuming that all column address inputs are held at either high or low.
6. ICC4 is measured assuming that all column address Inputs are switched only once during
each Hyper page cycle.
7 ICC1 and ICC3 are measured assuming that address can be changed once or less during
RAS:aVIL(MAX.) and
CAS~VIH(MIN.).
8. AC measurements assume tT =2ns .
331
MC-422000FB721
Notes:
9. AC Characteristics test condition
(1) Input timing specification
VIH (MIN.):2.4V ••••••••••• ~
VIL (MAX.)
=O.Bv·· · ==f1
~
tT • 2"1
11:-
~
VOH (MIN.) =2.4V
L
n.m~
VOL (MAX.) = O.BV •••••
.1
tT 2na
(2) Output timing specification
==\
~
10. For read cycles, access time is defined as follows:
input Conditions
Acce!sTime
Acce!S Time from RAS
tRAD :Ii IRAD(MAX.) and IRCD :Ii IRCD(MAX.)
IRAC(MAX.)
tRAC(MAX.)
tRAD > tRAD(MAX.) and tRCD :Ii tRCD(MAX.)
tAA(MAX.)
tRAD +tAA(MAX.)
IRCD > tRCD(MAX.)
tCAC(MAX.)
tRCD + tCAC(MAX.)
tRAO(MAX.) and tRCO(MAX.) are specified as reference points only; they are not restrictive
operating parameters. They are used to determine which access time (tRAC, tAA or tCAC)
is to be used for finding out when output data will be available. Therefore, the input conditions
tRAD;?;tRAD(MAX.) and tRCD;?;tRCD(MAX.) will not cause any operation problems.
11. Loading conditions are 2 TTLs and 100 pF.
12. tOFC (MAX.), tOFR(MAX.), tWEZ (MAX.) and tOEZ(MAX.) defines the time when the output achieves the
condition of Hi-Z and are not referenced to VOH or VOL.
13. tCRP(MIN.) requirement is applied to RAS I CAS cycles preceded by any cycles.
14. Either tRCH(MIN.) or tRRH(MIN.) shouid be met in read cycles.
15. tWP(MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
16. tOS(MIN.) and tOH(MIN.) are referenced to the CAS falling edge in early write cycles. In late
write cycles and read modify cycles, they are referenced to the WE failing edge.
17. If tWCS;?;tWCS (MIN.) , the cycle is an early write cycle and the data out will remain Hi- Z through the
entire cycle. If tRWO;?;tRWD (MIN.) , tCWOiS;tCWO(MIN.) ,tAWDiS;tAWO(MIN.) and tCPWOiS;tCPWD(MIN.),
the cycle is a read modify write cycle and the data out will contain data read from the selected cell.
If neither of the above conditions is met, the state of the data out is indeterminate.
18. To make VO to Hi-Z in read cycle, It is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1) RAS, CAS: inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE: active, OE: active...tWEZ, tWPZ are effective.
332
WE: inactive, OE: inactive ...tOEZ is effective.
Timing Chart
Please refer to Timing Chart 10, page 473.
333
MC-422000FB72F
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
OUTLINE DRAWINGS
A
-
z-
t-Y
a:
S~~O
-
00
".-...
, ,
(OPTIONAL HOLES) ~ ,~,
f&i
I--[]]
J
~~
t-
00:[
K
c
o
E
~ 0""""""'0"""0"'' ' ' ' ' ' ' ' 0' '0 ~
detail of
® part
detail of
@
part
ITEM
A
0
5.25:1:0.006
0.450
1.450
0.250
2.150
0.250
0.050 (T.P.)
0.350
0.925
1.661
0.700
1.000
0.158 MAX.
0.039
RO.079
R
4.0:1:0.1
0.157~g:gg~
s
1/13.0
1.27±0.1
4.0 MIN.
0'.25 MAX.
1/10.118
0.05:1:0.004
0.157 MIN.
0.010 MAX.
C
0
E
G
,m '=+f
fi
>
H
x
G
o
J
K
L
M
N
P
T
U
V
W
1.0:1:0.05
0.039~g:gg~
X
2.54
3.0MIN.
3.0 MIN.
0.100
0.118 MIN.
0.118 MIN.
Y
Z
334
INCHES
133,35:1:0.13
11.43
36.83
6.35
54.61
6.35
1.27 (T.P.)
8.89
23.495
42.18
17.78
25.4
4.0 MAX.
1.0
R2.0
B
ill
MILLIMETERS
MI68S-SOA6
PRELIMINARY DATA SHEET
[\lEe
MOS INTEGRATED CIRCUIT
MC-422000LFB72F
3.3 V OPERATION 2M -WORD BY 72-BIT DYNAMIC RAM MODULE
HYPER PAGE MODE (ECC)
Description
The MC-422000LFB72F is a 2 097 152 words by 72 bits dynamic RAM module on
which 9 pieces of 16M DRAM ( ~PD 4217805L) are assembled.
This module provide high density and large quantities of memory in a small space
without utilizing the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
- Hyper page mode ( EDO)
- 2 097 152 words by 72 bits organization
- Fast access and cycle time
Access time
(MAX.)
Family
RIW cycle time
(MIN.)
MC- 422000LFB72-A60
60 ns
104ns
MC- 422000LFB72-A70
70ns
124 ns
Hyper page mode
cycle time (MIN.)
Power consumption
(MAX.)
Active
Standby
25ns
3.28w
147.6mw
30 ns
2.95w
(CMOS level)
- 2 048 refresh cyclesl32 ms
-CAS before RAS
refresh. RAS only refresh. Hidden refresh.
- 168-pin dual in-line memory module (pin pitch
=1.27 mm)
- Single +3.3 V±O.3V power supply
Ordering information
Part Number
Access time
(MAX.)
Package
MC- 422000LFB72F-A60
60ns
168-pin Dual In-line
Memory Module
MC- 422000LFB72F-A70
70ns
Edge connect9r: Gold plating
H0042EJ4VODSOO (Japan)
(Socket Type)
Mounted devices
9 pieces of
uPD 4217805LG5
(400mil TSOP)
[Double side]
The information In this document is subject to change without notice.
335
MC-422000LFB7:
Pin Configuration
16B-pin Dual In-line Memory Module Socket Type (Edge Connector: Gold plating)
o
0
GND
110 36
11037
11038
11039
VOO
VO 1
V02
V03
11041
11042
11043
V04
V05
1106
V07
Vee
11040
11044
V09
VO 10
VOll
VO 12
VO 13
11053
0
VOB
GND
11045
11046
11047
GND
NC
NC
Vee
NC
NC
NC
NC
NC
GND
AI
A3
A5
A7
A9
NC
NC
Vee
336
Vee
GND
110 4B
110 49
Vee
110 50
110 51
110 52
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
GND
NC
BO
GND
NC
NC
NC
NC
~
Vee
NC
NC
11054
11055
GND
11056
110 57
11058
11059
Vee
110 SO
NC
NC
NC
NC
Vee
14
15
VO
VO
VO
VO
16
17
GND
NC
NC
Vee
m
CASO
NC
~
GNO
AO
A2
A4
A6
A8
Al0
NC
Vee
NC
NC
GND
~
CAS4
NC
m
Vee
NC
NC
V018
VO 19
Pin
No.
POI
PD2
PD3
PD4
PD5
P06
79
163
80
164
81
165
PD7
PD8
166
I DO
101
83
167
82
Acesess Tlma
SOns
70ns
H
H
L
L
L
L
H
H
H
H
H
L
L
GND
GNO
H
H
L
GNO
GNO
V020
V021
V022
V023
Vee
V024
NC
NC
NC
NC
V025
GND
11064
11065
11066
110 67
Vee
l106B
GND
11070
110 71
GND
PD2
PD4
PD6
PD8
101
Vee
Pin
Name
Note) H: VOH, L: VOL
GND
11061
11062
11063
11069
PO and 10 Table
AD - Al0, BO : Address Inputs
VO o-VO 71 : Oala Inputs I Outputs
RASO, RAS2 : Row Address Strobe
CASO, CAS4 : Column Address Strobe
WED, WE:! : Write Enable
OEo, 0E2 : Output Enable
POE
: Presence Detect Enable
P01- POB : Presence Detect Pins
100, 101
: Identity pins
Vee
: Power Supply
GNO
: Ground
NC
: No connection
110 26
V027
V02B
V029
V030
V031
Vee
V032
V033
V034
V035
GND
POI
PD3
PD5
PD7
100
Vee
o
MC-422000LFB72F
Block Diagram
RAsO
5Eo
WEo
RAS2
....
::
-y
CASO
1
-V
1/00
IIOB CAS RAS WE OE
1/01
1/07
1/06
1/02
1/03
00
~
WE2
CAs4
1/040
1/041
1/042
1/043
1/05
1/04
1/05
1/06
....
C5E'2
:::.....
-
I
1/01 CAS RAS WE OE
1102
1/03
1/04
05
1/07
1/04
1/03
1/02
1/01
IIOB
IIOB CAS RAS WE OE
1/04B
1/01 CAS RAS WE OE
1/09
1/07
1106
1/049
1/010
1/02
1/03
1/011
1/05
1/012
1/013
I
1/044
1/045
1/046
1/047
1/05
1/06
1107
IIOB
I
I
11050
01
1/051
1/04
1/052
1/053
11054
1105
1/06
1107
11055
1108
I
06
1/014
1/04
1103
1/02
1/015
1/01
1/016
1I0B CAS RAS WE OE
1/056
1/01 CAS RAS WE OE
1/017
1107
1106
11057
1I05B
1/02
1/03
1/059
1/04
11060
11061
I
I
1/01B
1/019
1/020
1/021
1/022
1/023
1/024
1/025
1/026
1/027
1/02B
1/029
1/030
1/031
--
1/05
02
1/034
1/035
1/036
1/037
1/03B
1/039
I
07
11062
1/05
1/06
1/07
11063
IIOB
1I0B CAS RAS WE OE
1/064
1/01 .CAS RAS WE OE
1/07
1/06
1/065
1/066
1102
1/03
1/067
1/04
1I06B
1/069
1/070
1/05
1/06
1/07
1/071
IIOB
1/04
1/03
1/02
1101
I
1/05
03
1104
1/03
1/02
I
I
1/01
J
1/032
1/033
I
I I I
08
J
1I0B CAS RAS WE OE
AO - t > - -....IJIoo- AO : DO 10 04
1107
1/06
80 - t >
~DO to DB
A1 to A10-t>
1/05
1/04
1/03
1/02
1/01
.. AO:D510DB
04
lootolD1 oO------NCorGND
PDE~
PD1 to PDB ~Vee orGND
Vee 0
GNDo
:oL c c t>-DO to DB
T 0- 8 ... DOtoD8
337
MC-422000LFB7:
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Remark
Condition
Rating
Unit
Voltage on Any Pin Relative to GND
VT
-0.5 to +4.6
V
Supply voltage
vee
-0.5 to +4.6
V
Output current
10
20
rnA
Power dissipation
PD
11
W
Operating temperature
Topt
Oto +70
Storage temperature
Tstg
-55 to +125
'C
'C
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device in not meant to be operated under conditions outside the limits
described in the operational sections of this specification. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN.
TYP.
Supply voltage
vee
3.0
3.3
High level input voltage
VIH
2.0
Low level input voltage
VII.
-0.3
+0.8
V
Ta
0
70
'C
Paramcter
Ambient temperature
Symbol
Condition
(NOTES: 1 ,2)
MAX.
Unit
3.6
V
Vcc+0.3
V
CAPACITANCE (Ta=2SoC ,f=1 MHz)
Parameter
Input capacitance
Symhol
338
MIN.
TYP.
MAX.
Unit
AO-AlO,BO
20
pF
C 12
20
pF
50
pF
20
pF
CIS
W'Irn, WE2
RASO, Ri\S2
CASO, "CAS4
OEO, run
20
pF
CliO
1/00-1/071
20
pF
CD
CI4
Data Input!
Output capacitance
Test condition
CII
MC-422000LFB72F
DC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
PARAMETER
Operating Current
led
Standby Current
1cc2
RAS only refresh current
lec3
Operating Current
(Hyper Page Mode)
1ec4
CAS before RAS
refresh current
IceS
Input Leakage Current
II(L)
Output Leakage Current
TEST CONDmON
SYMBOL
IO(L)
RAS ,CAS Cycling
tRc=tae (MIN.) , IO=OmA
MIN.
MAX.
tRAc=6Ons
910
bw:=7Ons
820
RAS ,CAS
~
VIII (MIN.)
82
RAS ,CAS
~
Vcc-O.2V
41
--RAS Cycling, CAS
~
VIII
tRc=tac(MIN.),IO=OmA
-RAS
--
l!!; VII. ,CAS Cycling
tHPC=tHPC (MIN.),IO=OmA
tRc=tac (MIN.)
10=0mA
tRAc=6Ons
910
bw:=7Ons
820
IRAc=6Ons
bw:=7Ons
tRAc=6Ons
730
bw:=7Ons
820
820
910
VI=Oto3.6V
RAS
-5
+5
all other pins not under test = OV
others
-5
+1
-5
+5
Outputs are disabled (Hi - Z)
VO=Oto 3.6V
High level output voltage
VOH
IO=-2.0mA
Low level output voltage
VOL
IO=+2.0mA
2.4
UNIT
NOTES
rnA
3,4,7
rnA
rnA
3,4,5,7
rnA
3,4,6
rnA
3,4
J1A
J1A
V
0.4
V
339
MC-422000LFB721
AC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Notes 8.9
(1/2)
tRAC= 70ns
tRAC= 60ns
PARAMETER
MIN.
340
uNiT
SYMBOL
MAX.
MIN.
MAX.
-
ns
70
NOTES
Random Read or Write Cycle Time
tRC
104
tRWC
133
-
124
Read Modify Write Cycle Time
Access Time from RAS
tRAe
-
60
ns
1011
Access Time from CAS
tCAC
-
20
23
ns
10,11
Access Time from Column Address
tAA
35
40
ns
10,11
Access Time from CAS Precharge
tACP
45
ns
11
Access Time from OE
tOEA
-
20
-
23
ns
11
RAS to Column Address Delay Time
tRAD
12
30
12
35
ns
10
CAS to Data Setup Time
tCLZ
0
-
0
ns
11
OE to Data Setup Time
tOLZ
0
-
0
ns
11
OE to Data Delay Time
tOED
13
-
15
-
40
157
ns
ns
Output Buffer Turn-off Delay Time from OE
tOEZ
0
13
0
15
ns
OE HoldTime
tOEH
0
0
tOES
0
0
-
ns
OE Lead Time Referenced to RAS
-
Transition TlDle ( Rise and Fall )
tT
1
50
1
50
ns
RAS Precharge Time
tRP
40
-
50
-
ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
ns
RAS Hold Time
tRSH
10
-
12
-
ns
CAS Pulse Width
tCAS
10
10000
12
10000
ns
CAS Hold Time
12
ns
tCSH
40
-
50
-
ns
RAS to CAS
DelaY~me
tRCO
14
45
14
52
ns
10
CAS tn RAS
Prechar~e Time
-
ns
13
RAS Pre charge CAS Hold Time
tRPC
RAS Hold Time from CAS Precharl!e
tRHCP
Row Address Setup Time
tASR
5
Row Address Hold Time
tRAH
10
Column Address Setup Time
tASC
0
Column Address Hold Time
tCAH
10
-
Column Address Lead Time Referenced to RAS
tRAL
30
-
35
Read Command Setup Time
tRCS
0
-
0
Read Command Hold Time Referenced to RAS
tRRH
0
-
0
Read Command Hold TlDle Referenced to CAS
tRCH
0
-
WE Hold Time Referenced to CAS
tWCH
10
-
0
10
WE Pulse Width
tWP
10
Data-in Setun Time
lOS
0
10
-
tCRP
5
CAS I'recharl!e Time
tePN
10
5
40
Data-in Hold TlDle
lOH
Write command Setup Time
tWCS
0
CAS to WE Delay Time
tCWD
32
RAS to WE Delay Time
tRWD
87
Column Address to WE Delay TllIle
tAWD
.52
5
10
5
4<;
5
10
0
12
10
0
10
0
37
99
59
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
-
ns
14
-
ns
16
ns
17
ns
17
ns
17
ns
17
-
n. 11,\
ns
15
ns 116
MC-422000LFB72F
(2/2)
ruC= 60ns
PARAMETER
ruc= 70ns
SYMBO
UNn NOTES
MIN.
MAX.
MIN.
WE Lead Time Referenced to RAS
tRWL
15
-
17
WE Lead Time Referenced to CAS
tCWT
10
-
12
CAS SetuD Time for CAS before RAS Refresh
tCSR
5
-
5
CAS Hold Time for CAS before RAS Refresh
tCHR
10
10
WE Setup Time
tWSR
10
WE Hold Time
tWHR
15
-
Refresh Time
tREF
-
32
MAX.
-
ns
ns
15
-
-
32
ms
10
ns
ns
ns
ns
HYPER PAGE MODE
ruc= 70ns
tRAC= 60ns
PARAMETER
SYMBOL
UNn NOTES
MIN.
MAX.
MIN.
MAX.
tHPC
25
-
30
RAs Pulse Width
tRASP
60
125,000
70
125,000 ns
CAS Pulse Width
tH(~AS
10
10,000
12
10,000 ns
tCP
10
- ns
CAS Precharl(e to WE Delay Time
tCPWD
52
-
10
59
-
ns
Read Modify Write Cycle Time
tHPRWC
66
-
75
-
ns
Data Output Hold Time
tDHC
5
-
5
tOCH
5
OE Precharge Time
tOEP
5
5
CAS Hold Time to OE
tCHO
5
-
ns
OE to CAS Hold Time
5
Output Buffer Tum-off Delay from WE
tWEZ
()
WE Pulse Width
tWPZ
10
Output Buffer Tum-off Delay from RAS
tOFR
0
13
Output Buffer Tum-off Delay from CAS
tOFC
0
13
Read I Write Cvcle Time
CAS Precharl(e Time
5
13
-
ns
ns
17
18
ns
ns
18
15
ns
12,18
10
-
ns
18
0
15
ns
12,18
0
15 ns
12,18
()
Notes:
1. All voltages are referenced to GND.
2. After power up, wait more than 100 J.lS and then, execute eight CAS before RAS or RAS
only refresh cycles as dummy cycles to initialize internal circuit.
3. ICC1, ICC3, ICC4 and ICCS depend on cycle rates (tRC and tHPC ) .
4. Specified values are obtained with outputs unloaded.
5. iCC3 is measured assuming that all column address inputs are held at either high or low.
6. ICC4 is measured assuming that all column address inputs are switched only once during
each Hyper page cycle.
7. ICC1 and ICC3 are measured assuming that address can be changed once or less during
RAS;:;iVIL(MAX.) and
CAS~VIH(MIN.).
8. AC measurements assume IT =2ns .
341
MC-422000LFB72
Notes:
9. AC Characteristics test condition
(1) Input timing specification
VIH(MIN.)=2.0V ••••••~
••• -
.
.
!
VIL (MAX.) = O.BV --------- :
~
j:
~
tT=2ns
tT:::2ns
(2) Output timing specification
VOH (MIN.) = 2.0V
VOL (MAX.) = O.BV
L
f
nm~
----.==\
10. For read cycles , access lime is defined as follows:
Input Conditions
Access Titnl
Access Time from RAS
tRAD :lii tRAD(MAX.) and tRCD :lii tRCD(MAX.)
tRAC(MAX.)
tRAD > tRAD(MAX.) and tRCD :lii tRCD(MAX.)
tAA(MAX.)
tRAD + tAA(MAX.)
tACO> tRCD(MAX.)
tCAC(MAX.)
tRCD + tCAC(MAX.)
tRAC(MAX.)
tRAD(MAX.) and tRCD(MAX.) are specified as reference points only ; they are not restrictive
operating parameters. They are used to determine which access time (tRAC, tAA or tCAC)
is to be used for finding out when output data will be available. Therefore, the input conditions
tRAD;;;tRAD(MAX.) and tRCD;;;tRCD(MAX.) will not cause any operation problems.
11. Loading conditions are 1 TTLs and 100 pF.
12. tOFC (MAX.), tOFR(MAX.), tWEZ (MAX.) and tOEZ(MAX.) defines the time when the output achieves the
condition of Hi-Z and are not referenced to VOH or VOL.
13. ICRP(MIN.) requirement is applied 10 RAS I CAS cycles preceded by any cycles.
14. Either tRCH(MIN.) or tRRH(MIN.) should be met in read cycles.
15. tWP(MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
16. tDS(MIN.) and tDH(MIN.) are referenced to the CAS falling edge in early write cycles. In late
write cycles and read modify cycles, they are referenced to the WE falling edge.
17. If tWCS;;;tWCS (MIN.) , the cycle is an early write cycle and the data out will remain Hi - Z through the
entire cycle. If tRWD;;;tRWD (MIN.) , tCWD;;;tCWD(MIN.) ,tAWD;;;tAWD(MIN.) and tCPWD;;;tCPWD(MIN.) ,
the cycle is a read modify write cycle and the data out will contain data read from the selected cell.
II neither of the above conditions Is met, the state of the data out is indeterminate.
18. To make I/O to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each Signal.
(1) RAS, CAS: inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) 80th RAS and CAS are active or either RAS or CAS is active (in read cycle)
-
-
WE: active, OE: active...tWEZ, tWPZ are effective.
342
WE: inactive, OE: inactive ...tOEZ is effective.
Timing Chart
Please refer to Timing Chart 10, page 473.
343
MC-422000LFB72
Package Drawing
A
00
uJ
[BJ
1.1
®
B
part
C
E
Lo
detail of
® part
ITEM
A
B
C
0
01
02
E
G
H
I
J
K
L
M
N
P
a
MILLIMETERS
133.35:t0.13
11.43
36.83
S.35
2.0
3.125
54.61
6.35
1.27 (T.P.)
8.89
23.50
43.18
17.78
25.4:!:0.13
4.0 MAX.
1.0
R2.0
INCHES
5.25:t0.006
0.450
1.450
0.250
0.079
0.123
2.150
0.250
0.050 (T.P.)
0.350
0.925
1.70
0.700
1.000:!:0.00S
0.158 MAX.
0.039
RO.079
0.157~8:88~
A
4.OtO.l
s
~3.0
~0.118
T
U
V
1.27tO.l
4.0 MIN.
0.25 MAX.
0.05tO.004
0.157 MIN.
0.010 MAX.
W
1.0.tO.05
0.039~8:88~
X
Y
2.54tO.l0
3.0 MIN.
3.0 MIN.
0.100tO.004
0.118 MIN.
0.118 MIN.
M16SSoS0A8
Z
344
--L
-llT
K-
J
detail of
t:
. 0 --'-
PREliMINARY DATA SHEET
MOS DINlTEGRATED CIRCUIT
M(c...424000FC72F
iilM -WORD BY 12-IBIT DVb\IIAMIC RAM MODULE
IHIYPEfR PAGE MODE (IEee)
Description
The MC-424000FC72F is a 4 194 304 words by 72 bits dynamic RAM module on
which 18 pieces of 16M DRAM ( /.L PO 421640S) are assembled.
This module provide high density and large quantities of memory in a small space
without utilizing the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
- Hyper page mode ( EDO)
- 4 194 304 words by 72 bits organization
- Fast access and cycle time
Access time
(MAX.)
Family
RIW cycle time
(MIN.)
Hyper page mode
cycle time (MIN.)
Power consumption
(MAX.)
Active
MC- 424000FC72-60
60 ns
104 ns
25 ns
8.82w
MC- 421000FC72-70
70ns
124 ns
30 ns
7.88w
Standby
106mw
(CMOS level)
- 4 096 refresh cycles/64 ms
-
~
~
- CAS before RAS refresh I RAS only refresh I Hidden refresh.
- 1S8-pin dual in-line memory module (pin pitch
=1.27 mm)
- Single +S.S V±0.2SV power supply
Ordering information
Part Number
Access time
(MAX.)
Package
MC- 424000FC72F-60
60ns
168·pin Dual In-line
Memory Module
MC- 424000FC72F-70
70ns
Edge connector: Gold plating
1i1105~BEJ1VODSOO
(Socket Type)
Mounted devices
18 pieces of
uPD 421640SG3
(300mll TSOP)
[Double side]
The information in this document is subject to change without notice.
(Japan)
345
MC-424000FC72
Pin Configuration
168-pin Dualln-line Memory Module Socket Type (Edge Connaclor : Gold plating)
0
0
GND
V03S
VOl
V02
V03
V040
V041
V042
V04S
V04
V05
V06
V07
V044
GND
V04S
V046
V047
V048
V049
Vee
VOSO
VOSI
VOS2
VOS3
GND
NC
NC
Vee
NC
NC
NC
NC
NC
GND
AI
A3
AS
A7
A9
All
NC
Vee
346
0
voo
V037
V038
V039
Vee
12S
126
127
128
129
130
131
132
133
134
135
136
137
136
139
140
141
142
143
144
146
146
147
148
149
150
lSI
162
163
154
155
168
157
168
159
160
161
162
163
164
165
166
167
168
GND
NC
80
Vee
V08
GND
V09
VOIO
VOII
VOl2
VOl3
Vee
VOl4
VOIS
VOl6
VOl7
GND
NC
NC
Vee
~
CAsii
NC
§W
OND
AO
A2
A4
AU
NJ
AID
NC
NC
OND
~
Vee
NC
NC
NC
NC
V054
VOSS
GND
VOSS
V067
VOS8
V069
Vee
VOGO
NC
NC
NC
NC
VOGI
V062
V063
GND
V064
VOSS
V066
V067
CAS4
NC
m
Vee
VOl8
VOl9
GND
V020
V021
V022
V023
Vee
V024
NC
NC
NC
NC
V026
V026
V027
GND
V028
V029
V030
V031
Vee
Vee
V069
V070
V071
V032
V033
V034
V035
vosa
GND
PD2
PD4
PD6
PDB
101
Vee
Pin
NC
Vee
OND
NC
NC
NC
NC
~
PD and ID Table
GND
POI
PD3
PDS
PD7
100
Vee
Neme
POI
PD2
PD3
PD4
PD5
PD6
PD7
PD8
100
101
41
42
43
44
45
46
47
48
49
50
51
62
63
54
55
Pin
No.
79
163
80
164
81
165
B2
166
63
167
Aee1918 Time
60nl 7On8
H
H
L
H
H
H
L
H
H
H
H
L
H
L
H
L
GND
GND
GND
GND
Note) H: VOH, L: VOL
56
57
68
59
60
61
62
63
64
65
67
68
AO - All, 80 : Address Inputs
: Dala Inputs I Outputs
nASii, ~ : Row Address Strobe
~,~ : Column Address Strobe
WEii, WE2 : Write Enable
70
71
POE
I/O o-VO 71
66
OEO, 0E2
69
72
POl- PDQ
73
74
7S
76
IDO, 101
Vee
GND
NC
77
78
79
80
81
62
63
64
0
: Output Enable
: Presan08 Detect Enable
: Prasan08 Detect Pins
: Idenlity pins
:PowerSupp~
: Ground
: No conneclion
MC-424000FC72F
Block Diagram
RAsO - - - - - - - .
RAS2~----""'I
0Eci - I > - - - - - - l l - - - ,
0E2 - D - - - - - I - -....
~~~----+--.
~.;~~~~~~~
WE2 -~---.....--.
CAS4 O-;;>-;=::;:;b.J,.~~
110 0
1101
1102
1103
11038
11037
11038
11039
I/O 3 CAS
1/04
1/02
RAs WE OE
00
I/O 1
1104
1105
1106
1107
11040
11041
11042
11043
1108
1109
11010
1I011----~~-r__.~r-~
11044
11045
11046
11047
11012
11013
11014
11015
11048
11049
11050
11051
11016
11017
11018
11052
11053
11054
1I019----~~-r__.~r-~
110 55 -----..::.:~"T'""""T--r-......
11020
11021
11022
11023
11056
11057
11056
11059
11024
11025
11026
11060
11061
11062
1I027----~~-r_.,-r-.,-J
110 63 ~-~::.::..."T'"-r.....,.-,....I
11028
11029
11030
I/O 31
11064
11065
11066
11067
11032
11033
1/034
11035
11066
11069
11070
11071
010
1102
1103
1104
011
1102
1103
013
1103
1104
017
100 to 101 0-.- - - - - NC or GNO
AD 0-..£>--....... AD: 00 to 08
BO 0-..£>
Al to Al00-..£>
liP" AD: 09 to 017
.. 00 to 017
'PDE-,..
POl to P08 ~ Vr;corGNO
Vr;c 0-.-"'1:L'""C-O'-C-l..
, ..... DO to 017
GNO D
T
.. DO to 017
347
ABSOLUTE MAXlIMUM llU.1'JING§
Parameter
Symbol
Unit
VT
-1.Oto+7.0
V
Supply voltage
vee
-1.0to +7.0
V
50 .
10
rnA
W
20
Power dissipation
PD
Operating temperature
Topt
Oto+70
Storage temperature
Tstg
-55 to +125
'C
'C
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device in not meant to be operated under conditions outside the limits
described in the operational sections of this specification. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
~COMMlENJ[»EJ[»
OPERA 'JrITNG CONIDlIT'JrTION§
(NO'll'lES: 1,2)
MIN.
TYP.
MAX.
Unit
Supply voltage
vee
4.75
5.0
5.25
V
High level input voltage
VIH
2.4
Vec+ 1.0
V
Low level input voltage
vn.
-1.0
+0.8
V
Ta
0
70
'C
Paramcter
Ambient temperature
Symbol
CAPACI1'ANCE (1'a=25'C
Parameter
Input capacitance
Data Input!
Output capacitance
348
Rating
Voltage on Any Pin Relative to GND
Output current
Remark
Condition
?
Symbol
Condition
f[=1l MlHIz)
Test condition
MIN.
TYP.
MAX.
Unit
CI1
AO-AlO,BO
20
pF
CI2
WE 0, WE2
20
pF
CI3
RASO,RAS2
78
pF
CI4
CASO, CAS4
20
pF
CIS
OEO, OE2
20
pF
20
pF
CIIO
I/O 0-1/0 71
DC CHAlRACl'ElRJISl'ICS
(Recommended Operating ConditiollDS Wlless othell'Wise noted)
PARAMETER
SYMBOL
Operating Current
led
Standby Current
Iee2
TEST CONDmON
RAS ,CAS Cycling
btc=tRc (MIN.) , IO=OmA
InAc=6Ons
1680
1nAc=70ns
1500
~
VIII(MIN.)
100
RAS ,CAS
~
Vcc-O.2V
82
Iee3
--RAS Cycling, CAS
Operating Current
(Hyper Page Mode)
Icc4
--- Cycling
RAS ;;;; Vn.. ,CAS
CAS before RAS
refresh current
leeS
Input Leakage Current
II(L)
lOlL)
MAX.
RAS, CAS
RAS only refresh current
Output Leakage Current
MIN.
IRAc=6Ons
1680
lRAc=70ns
1500
lRAc=60ns
1680
tHPC=tHPC (MIN .),IO=OmA
tnAc=7Ons
btc=btc (MIN.)
IO=OmA
1500
1680
1nAc=70ns
~
VIII
btc=btc (MIN.) , IO=OmA
tnAc=6Ons
1500
+lO
VI=O to S.2SV
RAS
-10
all other pins not under test = OV
others
-5
+1
-10
+lO
Outputs arc disabled (Hi - Z)
VO=O to 5.2SV
High level output voltage
VOH
IO=:-S.OmA
Low level output voltage
VOL
IO=:+4.2mA
2.4
UNIT
NOTES
rnA
3,4,7
rnA
rnA
3,4,5,7
rnA
3,4,6
rnA
3,4
JI.A
JI.A
V
0.4
V
349
MC-424000FC721
AC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Notes 8,9
(112)
IRAc = 60ns
PARAMETER
MIN.
Random Read or Write Cycle Time
tRC
104
Read Modify Write Cycle Tune
tRWC
133
Access Time from RAS
tRAC
tCAC
-
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precbarge
Access Time from OE
RAS to Column Address Delay Time
tAA
IACP
tOEA
-
MAX.
-
60
20
35
40
20
30
MIN.
UNIT NOms
MAX.
157
-
-
70
124
12
45
23
35
-
ns
ns
11
-
40
0
0
-
0
0
OE to Data Delay Time
tCU
tOU
tOED
13
-
15
-
OUlDut Buffer Turn·off Delav Time from OE
tOEZ
0
13
0
15
OE HoldTime
tOEH
0
-
0
OE Lead Time Referenced to RAS
Transition Tune ( Rise and Fall )
RAS Precbarge Tune
RAS Pulse Width
RAS Hold Tooe
0
-
1
50
40
-
60
10
10
10,000
00 Pulse Width
tOES
tT
tRP
tRAS
tRSH
tCAS
CAS Hold Tooe
tCSH
40
RAS to CAS DelavT101e
CAS to RAS Precbarll:e Time
tRCD
14
tCRP
tePN
5
10
tRPC
5
40
CAS Precbarl!e Time
RAS Precbarll:e CAS Hold Tune
RAS Hold Tooe from CAS Precbarl!e
Row Address Setup Time
Row Address Hold Tooe
tRHCP
IASR
tRAH
5
10
Column Address Setup Time
lAse
Column Address Hold Time
Column Address Lead Time Referenced to RAS
teAH
0
10
tRAL
30
Read Command Setup Tune
tRCS
tRRH
0
tRCH
tWCH
0
10
WE Pulse Width
Data-in SetuD Time
Data-in Hold TIme
Write command Setup Time
tWP
tDS
10
0
tDH
tWCS
10
0
CAS to WE Delav Time
RAS to WE Delay Time
Column Address to WE Delay TIme
tCWD
32
87
Read Command Hold Tooe Referenced to RAS
Read Command Hold Tune Referenced to CAS
WE Hold Ttme
to CAS
tRWD
IAWD
0
52
10000
45
-
-
-
-
-
ns
1011
10,11
10,11
12
-
ns
ns
ns
ns
ns
ns
ns
23
tRAD
CAS to Data Setup Tune
OE to Data Setup Tooe
350
IRAc=70ns
SYMBOL
0
1
50
70
12
12
-
n.
52
5
10
-
5
45
5
10
0
12
35
0
0
0
10
10
n
10
0
37
99
59
ns
-
50
14
-
-
-
-
11
12
ns
10.000
1'0,000
11
10
ns
ns
ns
ns
ns
ns
50
11
ns
ns 110
ns
13
n.
ns
DS
ns
n.
ns
ns
ns
ns
ns
14
ns
14
15
DS
ns 15
ns 116
ns
ns
16
17
ns
17
ns
ns
17
17
MC-424000FC72F
(2/2)
IRAc=60ns
PARAMETER
WE Lead Time Referenced to RAS
I'WE l.ead Time n
Ito~
IRAc = 70ns
IUNfI NOTES
SYMBOl
tRWL
tl"WT
MIN.
MAX.
15
10
-
CAS SetuD TlDle for CAS before RAS Refresh
tCllR
5
CAS Hold Time for CAS before RAS Refresh
tCHR
10
WE SetuD Time
tWSR
10
WE Hold TlDle
tWHR
15
Refresh TlDle
tREF
MIN.
-
-
-
-
64
17
12
5
10
10
15
-
MAX.
-
ns
ns
-
ns
ns
ns
ns
64
ms
HYPER PAGE MODE
IRAc=70ns
1RAC=6Ons
PARAMETER
IUNTI NOTES
SYMBOL
MIN.
MIN.
MAX.
MAX.
tHPc.
25
-
30
IRIS PoI.e Width
tRAllP
60
125,000
70
CAS Pulse Width
CAS Precharlle Time
tHCAll
10
10,000
12
- ns
125,000 ns
10,000 ns
tCP
10
-
10
- ns
CAS Precharlle to WE Delav Time
Read Modify Write Cycle TlDle
tCPWD
tHPRWC
52
59
75
- ns
Read I Write Cvcle TlDle
-
Data Output Hold Time
tOHC
OE to CAS Hold Time
tOCH
66
5
5
OE Precbarge Time
tOEP
5
CAS Hold TlDle to OE
tCHO
5
Output Buffer Tum-off Delay from WE
tWPZ
0
WE Pulse Width
tWPZ
10
tOFR
0
13
0
tOPC
0
13
0
Output Buffer Tum-off Delay from RAS
Output Buffer Tum-off Delay from CAS
13
-
17
- ns
5
-
5
- DB
5
- ns
DB
18
5
- DB
0
15 ns
12, 18
10
- ns
15 ns
15 ns
18
18
12, 18
12, 18
Notes:
1. All voltages are referenced to GND.
2. After power UP. walt more than 100 lIS and then, execute eight CAS before RAS or RAS
only refresh cycles as dummy cycles to Initialize Intemal circuit.
3. ICC1, ICC3, ICC4 and ICCS depend on cycle rates (tRC and tHPC ) .
4. Specified values are obtained with outputs unloaded.
5. ICC3 is measured assuming that all column address Inputs are held at either high or low.
6. ICC4 Is measured assuming that all column address Inputs are switched only once during
each Hyper page cycle.
7. ICC1 and ICC3 are measured assuming that address can be changed once or less during
RAS;:aVIL(MAX.) and CASii:VIH(MIN.).
B. AC measurements assume tT =2ns •
351
MC-424000FC721
Notes:
9. AC Characteristics test condition
(1) Input timing specificatiOll
VIH (MIN.) = 2.4V •••••••••••
-r----\
V,L(MAX.)=o.sv·····:::::fl
;:
lL
...,....,...
::
~
tT.2M
tT.2na
(2) Output timing specification
L
r-
VOH(MIN.)=2.4V··_·=J:
VOl (MAX.) :o.sv •••••
=\
10. For read cycles, access time Is defined as follows:
Input Conditions
IRAD :i IRAD(MAX.) and IRCD :i IRCD(MAX.)
Acc:eas Tim>
IRAC(MAX.)
IRAD > IRAD(MAX.) and IRCD :i IRCD(MAX.)
tAA(MAX.)
IRAD + tAA(MAX.)
IRCD > IRCD(MAX.)
ICAC(MAX.)
IRCD+ICA~)
Acc:eas Tim> from RAS
IRAQtMAX~
tRAD(MAX.) and tRCD(MAX.) are specHled as reference points only ; they are not restrictive
operating parameters. They are used to determine which access time (tRAC, fAA or tCAC)
Is to be used for finding out when output data will be available. Therefore, the Input conditions
tRAD~tRAD(MAX.) and tRCD~tRCD(MAX.) will not cause any operation problems.
11. Loading conditions are 2 TTLs and 100 pF.
12. tOFC (MAX.), tOFR(MAX.), tWEZ (MAX.) and tOEZ(MAX.) defines the time when the output achieves the
condition of HI-Z and are not referenced to VOH or VOL.
13. tCRP(MIN.) requirement Is applied to RAS I CAS cycles preceded by any cycles.
14. Either tRCH(MIN.) or tRRH(MIN.) should be met In read cycles.
15. tWP(MIN.) Is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
16. tDS(MIN.) and tDH(MIN.) are referenced to the CAS falling edge In early write cycles. In late
write cycles and read modify cycles, they are referenced to the WE failing edge.
17. If tWCS~tWCS (MIN.), the cycle Is an early write cycle and the data out will remain HI- Z through the
entire cycle. H tRWD~tRWD (MIN.) , tCWD~tCWD(MIN.) ,tAWD~tAWD(MIN.) and tCPWD~tCPWD(MIN.),
the cycle Is a read modify write cycle and the data out will contain data read from the selected cell.
H neither of the above conditions Is met, the state of the data out Is Indeterminate.
18. To make
va to HI-Z In read cycle, it is necessary to control RAS, CAS, WE, OE as follows.
specHlcatlon depends on state of each Signal.
(1) RAS, CAS: inactive (at the end of read cycle)
WE: Inactive, OE: active
tOFC is effective when RAS Is Inactivated before CAS Is Inactivated.
tOFR Is effective when CAS is Inactivated before RAS Is Inactivated.
(2) Both RAS and CAS are active or either RAS or CAS Is active (In read cycle)
-WE: active, OE:
- active...tWEZ, tWPZ are effective.
352
WE: Inactive, OE: Inactive...tOEZ Is effective.
The effective
Timing Chart
Please refer to Timing Chart 10, page 473.
353
MC-424000FC721
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
OUTLINE DRAWINGS
rOOOIDIDIIU~"IIOOID'D~
detail of ® part
detail of @ part
W
o illllx
~
L-o-J>
ITEM
A
B
C
I
II
I
I
I
~
ill
D
0
K
L
M
N
P
Q
6.35
1.27 (T.P.)
8.89
23.495
42.18
17.78
25.4
4.0 MAX.
1.0
R2.0
R
4.0:1:0.1
0.157~:gg~
S
.,03.0
T
1.27:1:0.1
4.0 MIN.
0.25 MAX.
1.0:1:0.05
2.54 MIN.
3.0 MIN.
3.0 MIN.
1/10.118
0.05:1:0.004
0.157 MIN.
0.010 MAX.
0.039:1:0.002
0.100 MIN.
0.118MIN.
W
X
Y
Z
6.35
54.61
INCHES
5.25:1:0.006
0.450
1.450
0.250
2.150
0.250
0.050 (T.P.)
0.350
0.925
1.661
0.700
1.000
0.158 MAX.
0.039
RO.079
E
G
H
I
U
V
354
MILLIMETERS
133.35:1:0.13
11.43
36.83
0.118MIN.
M188S-50AZ
PRELIMINARY DATA SHEET
\lEe
MOS INTEGRATED CIRCUIT
MC-424000lFC72F
3.3 V OPERATION 4M -WORD BY 72-BIT DYNAMIC RAM MODULE
HYPER PAGE MODE (ECC)
Description
The MC-424000LFC72F is a 4 194 304 words by 72 bits dynamic RAM module on
which 18 pieces of 16M DRAM ( IJ. PO 4216405L) are assembled.
This module provide high density and large quantities of memory in a small space
without utilizing the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
- Hyper page mode ( EDO)
- 4 194 304 words by 72 bits organization
- Fast access and cycle time
Access time
(MAX.)
Family
R1W cycle time
(MIN.)
Hyper page mode
cycle time (MIN.)
Power consumption
(MAX.)
Active
MC- 424000LFC72-A60
60ns
104ns
25 ns
5.87w
MC- 424000LFC72-A70
70ns
124 ns
30 ns
5.22w
Standby
180mw
(CMOS level)
- 4 096 refresh cycles/64 ms
refresh. RAs only refresh. Hidden refresh.
- 168-pin dual in-line memory module (pin pitch = 1.27 mm)
-CAS before RAS
- Single +3.3 V±0.3V power supply
Ordering information
Part Number
Access time
(MAX.)
Package
MC- 424000LFC72F-A60
60ns
168-pin Dual In-line
Memory Module
MC- 424000LFC72F-A70
70ns
Edge connector: Gold plating
110043EJ4VODSOO (Japan)
(Socket Type)
Mounted devices
18 pieces of
uPD 4216405LG3
(300mil TSOP)
[Double side]
The infonnation in this document is subject to change without notice.
355
MC-424000LFC7:
Pin Configuration
16B-pin Dual In-line MemOlY Module Socket Type (Edge Connector: Gold plating)
0
0
GND
11036
11037
11038
110 39
Vee
11040
110 4t
11042
11043
11044
GND
110 45
11046
V047
11048
11049
Vee
11050
11051
110 52
110 53
GND
NC
NC
Vee
NC
NC
NC
NC
NC
GND
AI
A3
A5
A7
A9
All
NC
Vee
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
356
0
NC
80
GNO
NC
NC
NC
NC
~
Vee
NC
NC
GND
VOO
VO t
V02
V03
Vee
V04
V05
V06
V07
V08
GND
V09
VO 10
VO 11
VO 12
VO 13
Vee
14
15
VO
VO
VO
VO
16
17
GND
NC
NC
Vee
wrn
CASO
NC
~
GND
i\O
A2
M
AG
A8
AlO
NC
Vee
NC
NC
GNO
~
HAS2
CAS4
NC
m2
Vee
NC
NC
11054
11055
VO 18
VO 19
GND
GND
11056
11057
11058
11059
V020
V021
V022
V023
Vee
11060
NC
NC
NC
NC
110 61
11062
11063
Vee
V024
NC
NC
NC
NC
V025
V026
V027
GNO
GNO
11064
V028
V029
V030
V031
110 65
11066
11067
Vee
11068
110 69
110 70
110 71
GNO
P02
P04
P06
P08
101
Vee
PO and 10 Table
Vee
V032
V033
V034
V035
GNO
POI
P03
P05
P07
100
Vee
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin
Name
Pin
No.
POI
P02
P03
P04
PD5
P06
P07
P08
79
163
80
164
81
165
82
166
100
101
83
167
Accsess Time
60ns
70ns
H
H
H
H
L
H
L
H
H
H
H
L
GNO
GNO
H
L
H
L
GNO
GNO
Note) H: VOH, L: VOL
AO - All, 80 : Address Inputs
I/O O-VO 71 : Data Inputs I Outputs
RASO, FiA§2 : Row Address Strobe
CASO, CAS4 : Column Address Strobe
WEii, WE2 : Write Enable
OEO, OE2 : Output Enable
POE
: Presence Detect Enable
POl- PD8 : Presence Detect Pins
100, 101
: Identity pins
Vcc
: Power Supply
GND
: Ground
NC
: No connection
0
MC-424000l1FC721F
Block Diagram
RAS2 0---------""1
0E2 c-I>----~--.
WE2 e-j>----:I---.
RASOCC---------:-tl
OEO
c-I>
;A~~:e
I
liD 0 c---- liD 4
1/01
1/02
1/03
1/02
1/04
1/05
1/06 0---1/02
110 7
CAS4
CAS RAs
WE
DE
1/037 c - - 1/02
1/0380--1/03
1/04
1/039
DO
1/04011041
1/042
1/043
01
r..:1/""O;..l~;__""1""_r-,--'
1108
110 9 c---- 110 3
1/010
1/02
I/O-We-- lin :J
1/()4SO--- I/O :!
1/050e- 1/0 :1
110510--- 1/0-1
1/02
04
1/056
1/057
1/058
11059
05
1/024
1/025
1/026
1/032
1/033
1/034
1/035
1102
1/01
07
1/064
1/065
1/066
1/067
08
1/068
1/069
1/070
1/071
100 to 101 c
AD 0 - [ > - - > AO : DO to 08
BO
o--t>-c> AO : 09 to 017
Al to All 0 - [ > - - > 0 0 to 017
CAS
RAS WE
DE
010
011
012
013
1/03
014
1/03
016
1103
1/04
017
1/060
1/061
1/082
1/063
1/027 - r . . :I/" "O;..l:.....;__"'T'"-"'_r-'
1/02
1/030
110310-- 1/01
1/03
1104
11054
1/055
r..:IJ""O;..l:.....;__............._..-l
1/020
1/021
1/022
1/023
09
1/0470--- 1/0 -I
1/012
1/013
110 19
1/0 1
1102
1/03
1104
I/O-l!,o- 1/02
02
110 11 -r..:I/""O;..l~;__"'T'"-'--..-'
1/018
C-D--;::::::::;~.J:='==-:!:-I
RAs WE DE
1/036 c - 1/0 1 CAS
POl to
NCorGNO
Pi5E~
poe
Vee or GNO
Vee c
GNDc
::i: C(}'Clf> DO to 017
4"
i>-DO to 017
357
MC-424000LFC7~
ABSOLUTE MAXIMUM RATINGS
Parameter
Remark
Symbol
Condition
Rating
Unit
Voltage on Any Pin Relative to GND
VT
-0.5 to +4.6
V
Supply voltage
vee
-0.5 to +4.6
V
Output current
10
20
rnA
Power dissipation
PD
20
W
Operating temperature
Topt
Oto +70
Storage temperature
Tstg
-55 to +125
'C
'C
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device in not meant to be operated under conditions outside the limits
described in the operational sections of this specification. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN.
TYP.
3.0
3.3
High level input voltage
vee
vm
Low level input voltage
VIL
-0.3
+0.8
V
Ta
0
70
'C
Parameter
Supply voltage
Ambient temperature
Symbol
Condition
(NOTES: 1 ,2)
2.0
MAX.
Unit
3.6
V
Vcc+0.3
V
CAPACITANCE (Ta=25"C ,f=1 MHz)
Parameter
Input capacitance
Data Input!
Output capacitance
358
Symbol
MAX.
Unit
CI1
AO-Ai1,DO
20
pF
CI2
WEQ,wn
20
pF
C 13
RASQ,
RAS2
78
pF
C 14
CASQ, ~
20
pF
CIS
tRAD(MAX.) and IRCD ;:;; IRCD(MAX.)
tAA(MAX.)
IRAD + tAA(MAX.)
tRCD > tRCD(MAX.)
tCAC(MAX.)
tRCD + tCAC(MAX--l
tRAD(MAX.) and tRCD(MAX.) are specified as reference points only ; they are not restrictive
operating parameters. They are used to determine which access time (tRAC, tAA or tCAC)
is to be used for finding out when output data will be available. Therefore, the input conditions
tRAD~tRAD(MAX.)
and
tRCD~tRCD(MAX.)
will not cause any operation problems.
11. Loading conditions are 1 TTLs and 100 pF.
12. tOFC (MAX.), tOFR(MAX.), tWEZ (MAX.) and tOEZ(MAX.) defines the time when the output achieves the
condition of Hi-Z and are not referenced to VOH or VOL.
13. tCRP(MIN.) requirement is applied to RAS I CAS cycles preceded by any cycles.
14. Either tRCH(MIN.) or tRRH(MIN.) should be met in read cycles.
15. tWP(MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be mel.
16. tDS(MIN.) and tDH(MIN.) are referenced to the CAS falling edge In early write cycles. In late
write cycles and read modify cycles, they are referenced to the WE falling edge.
17. If tWCS~tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi - Z through the
entire cycle. If tRWD~tRWD (MIN.) , tCWD~tCWD(MIN.) ,tAWD~tAWD(MIN.) and tCPWD~tCPWD(MIN.),
the cycle is a read modify write cycle and the data out will contain data read from the selected cell.
If neither of the above conditions is met, the state of the data out is indeterminate.
18. To make VO to HI-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1) RAS, CAS: Inactive (at the end of read cycle)
WE: Inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE: active, OE: active...tWEZ, tWPZ are effective.
362
WE: inactive, OE: Inactive ...tOEZ is effective.
Timing Chart
Please refer to Timing Chart 10, page 473.
363
MC-424000LFC72
Package Drawing
A
II:
- r-Y
z-
~1a.!H1~DDDDD
0
..
~
DODD ]
0
~
-+-00
J
r-
K
I L!LG
D
C
E
~rnDDo""'~"""DoDD1
detail of
@ part
-nW
t~ gt Ix
ITEM
A
MILLIMETERS
133.35±0.13
B
M
N
Q
11.43
36.83
6.35
54.61
6.35
1.27 (T.P.)
8.89
23.495
43.18
17.7B
25.4
4.0 MAX.
R2.0
R
4.0±0.1
O.157:g:gg~
s
413.0
1.27±0.t
4.0 MIN.
0.25 MAX.
1.0±0.05
2.54 MIN.
3.0MIN.
3.0 MIN.
¢O.ttB
0.05±0.004
0.t57 MIN.
0.010 MAX.
0.039±0.002
0.100 MIN.
O.ttB MIN.
0.t18 MIN.
M168S-SOA3
c
D
E
G
H
D
J
K
L
T
U
V
W
X
Y
Z
364
INCHES
5.25±0.006
0.450
1.450
0.250
2.150
0.250
0.050 (T.P.)
0.350
0.925
t.700
0.700
1.000
0.t58 MAX.
RO.079
Timing Chart 1
365
Read Cycle
IRC
IRAS
IRP
ICSH
V,HV,L-
Address
V,HV,L-
V,HV,L-
L....L...L...L...L...L..+...L.....L.....L.....L.-{
Cll
1/0
VOHVOL-
Hi-Z
Hi-Z
367
Early Write Cycle
IRC
IRP
IRAS
RAS
V,HV,LIcsH
IRSH
IRCO
CAS
lCAS
V,HV,L-
Address
\wCH
WE
VIII
VII
I",;
I/O
368
V,HV,L-
IOH
xxxxxxxxxxi_Oatain~
Fast Page Mode Read Cycle
IRASP
IRP
V,HV,L-
Address
V,HV,L-
1/0
VOHVOL-
Remark
In the fast page mode, read and write cycles are available for each of the consecutive CAS cycles within
the same RAS cycle.
369
Fast Page Mode Early Write Cycle
Address
VIIIVII~
1/0
V,HV,L-
Remark In the fast page mode, read and write cycles are available for each of the consecutive CAS cycles within
the same RAS cycle.
370
CAS Before RAS Refresh Cycle
lAC
IAAS
V,HV,L-
Remark Address, WE: Don't care 110: Hi-Z
RAS Only Refresh Cycle
t--------tllAS
t~__
_ ____ .,I-' _______-'I"'AC"--_ _ _ _ _---1
~,.!.',____. ~
tRAS
V,HV,L-
ICAP
Address
V,HV,L-
Remark WE: Don't care 110: Hi-Z
371
Hidden Refresh Cycle (Read)
tAC
tAC
tAAS
tAAS
V,HVIL-
tCAP
tACO
tASH
tCHA
tCPN
V,HV,L-
Address
V,HVIL-
V,HV,L-
L-L-.......'--'.......'-'\-''--'~
tAAC
!cAC
tCll
I/O
372
VOH- .••••••••••••••••••••••••••••• ~~:~••••••••••••••••••••••
VOL-
Data out
Hi·Z
Hidden Refresh Cycle (Write)
tRC
tRC
tRAS
tRAS
V,HV,L-
Address
VIHVIL-
WE
V,HVIL-
I/O
V,HVIL- ~t£...J"--lL...lJ~~~...JL..l£.~ ~_ _ _ _ _Jo
twcs
!wCH
373
· Timing Chart 2
375
Read Cycle
tRC
tRAS
RAS
tRP
V,HVILtCSH
tRSH
tRCO
CAS
tCPN
tCAS
V,HVILtRAl
Address
V,HV,l-
V,HV,ltllA!:
. -1M'
I-----\'~~~
1/0
VOt+VOl-
Hi-Z
Data out
Hi-Z
377
Early Write Cycle
tRC
tRAS
VIII-
VIltCSH
CAS
Address
WE
V,HV,L-
V,HV,L-
VIII
V,,-
1/0
378
V,HV,L-
Fast Page Mode Read Cycle
Address
WE
V,HVIL-
V,HV,l-
VOHI/O VOl-
Remark In the fast page mode, read and write cycles are available for each of the consecutive CAS cycles
within the same RAS cycle.
379
Fast Page Mode Early Write Cycle
tRASP
tRP
VIHVll-
Address
I/O
VIItVll- .
VIIIVll-
L..:;1L...l1L...l~r....lor...l/ II-_ _ _ _--.Ji
Remark· In the fast page mode, read and write cycles are available for each of the consecutive CAS cycles
within the same RAS cycle.
380
CAS Before RAS Refresh Cycle
tRC
tRAS
RAS Only Refresh Cycle
tRC
tRAS
tRP
tnA~
Address
Remark WE: Don't care
I/O: Hi-Z
381
Hidden Refresh Cycle (Read)
tRC
tRC
tRAS
tRAS
Address
V,HV,L-
V,H-
V,L-
I/O
382
Z-Z-L-L-'-''--''r-''--''-'
VOH- •••••••••••• _••••••••••••••••• ~!:~
VOL-
......................
Data out
Hi-Z
Hidden Refresh Cycle (Write)
tRC
tRC
tRAS
Address
V,HVIl-
WE
V,HVIL-
twcs
I/O
tRAS
twCH
V,HV,L- .......'--"'-"-><......................._>1-3 "--_ _ _ _.1' ,,-lL....lt....lL...lL.lL....:IL..lL..Jj~-lL...l£....lL....lL...lL.~IL..lL..Jj~:....lI:-lL-lL~
383
Timing Chart 3
385
Read Cycle
IRe
tAP
blAs
RAS
VIHVILIeSH
tRSH
tAcD
CAS
IePN
leAs
VIHVILlRAL
AddI8Ss
WE
VIHVIL-
VIHVIL-
110 VOH- _____________________
VOL-
tIL:~
______________________________________ _
Dalaout
___
J:!i:_~
___ _
387
Early Write Cycle
RAS
VIHVIL-
tcsH
CAS
VIHVIL-
Address
VIHVIL-
WE
VIHVIL-
110 VIHVIL-
388
.....l~...l..~~~~~...l.....p--+_-I-_ _ _ _ _ _-t-L.-'-.L...L...j~-'--'-.L-L..L...j~-'--'-.L...
~'-K~...K....K..K...l"-ll'-K~
.._ _ _ _ _ _ _ _ _-JI
"-'~~...K...x....K..K...l~~...K...x....K..K..l~
Hyper Page Mode Read Cycle
tRP
IRABP
~
IRHcp
CAS
VIHVIL-
Address
VIHVIL-
WE
VIHVIL-
]X)J
1Hc...
tACO
~
~
~
IHpc
tHCAB
tCBH
~
~
.. H ~
It--.,
Row
1----
~
~
~
~
~
tCPN
Jt
tRAL
~
~ ~
~~
Col.
~~
Col.
~
~
//////t
.'---
IoFR
IoFC
-,
,
~~
IAcp
.IM
IRAc
1M
bc
1M
Data out
bc
~
~
'/
~
~
_________________ 1;:11: _'!;. __________ ~
Remark
j
KXX )( )(
Col.
IAcp
ICAc
leu
I/O
t_
IHCAB
~
I
VOHVOL-
~
)0--0-
Data out
---0-
Data out
)0----
In the hyper page mode,read and write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
389
Hyper Page Mode Read Cycle (WE Control)
tesH
CAS
VIH-
Addl8ss
VIH-
WE
I/O
VIL-
VIL-
VIHVIL-
VOHVOL-
••••••• _ •••••••••
Remark
390
tI!:.~ ........ .
In the hyper page mode,read and write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
Hyper Page Mode Early Write Cycle
VIH-
RAS
VIL-
CAS
VIL-
VIH-
Addl8ss
VIHVIL-
VIH-
I/O
"'t"'7'I:-7I:"'X'~7\ v------~
VIL-
Remark
In the hyper page mode,read and write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
391
Hyper Page Mode Read and Write Cycle
V'HV'LtcaH
CAS
V'HV'L-
Address
V'HV'L-
WE
V'HV'L-
11/0
VOHHi-Z
VOL- -- --- ------------------ ---------
11/0
V'HV'L-
Remark
392
__________
In the hyper page mode,road and write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
':!t:~
_____________ .
CAS Before RAS Refresh Cycle
-
CPS
VIHVIL- ____- L ______- L __________
~~
______L __ _ _ _ _ _ J
Remark Address,WE - Don't care VO - Hi - Z
RAS Only Refresh Cycle
tRP
-
VIH-
RAS
VIL-
tR.l.fl
-----'II
- - VIHCPS VIL-
Address VIHVL-
Remark WE - Don' care, VO - HI - Z
393
Hidden Refresh Cycle (Read)
IRA.
tRcD
fAA.
lAsH
IcPN
tCHR
Address
IRCB
IRAc
bc
IeLZ
.•• _. -_. ---_•• -_.- -~:?:- _. -_. -_. -_.-_. -_.- _. ----_.
394
Dalaout
Hidden Refresh Cycle (Write)
VIHVIL-
VIiVII.-
Address
VIHVL\wca
WE
V'fIVIl.IDs
110
IDH
VIHVIl.-
395
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Timing Chart 4
397
Read Cycle
IRe
tRIoS
RAS
VIHVILIeSH
IReD
CAS
lAsH
!cAs
VIHVILIRAL
AddnIss
VIHVIL-
WE
VIHVIL- .I-.l-I.....
J / // / / /
dl-tOFF
~
Data out
Hi-Z
1)--------_.
Remark In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle,
435
Fast Page Mode Early Write Cycle
Address
1/0
V,HV,L- '
V,HV,L-
Remark DE: Don't care
In the fast, page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
436
Fast Page Mode Late Write Cycle
tRASP
RAS
tRP
tRHCP
V,HV,LtCSH
CAS
V,HV,L-
Address
V,HV,L-
tpc
tRSH
V,HV,L-
110
Hi-Z
._---------------
Remark In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
437
Fast Page Mode Read Modify Write Cycle
tAASP
Address
V,HVIL-
VI/!-
VII-
VIH-
VII-
I/O
VOHVOl-
I/O
Remark
438
In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
CAS Before RAS Refresh Cycle
IRC
IRAS
V,HV,l-
V,HV,l-
twSR
twHR
Remark Address, DE: Don't care
I/O: Hi-Z
RAS Only Refresh Cycle
IRC
IRAS
IRP
lRAS
V,HV,l-
tCRP
Address
V,HV,l-
Remark WE, OE: Don't care
I/O: Hi-Z
439
Hidden Refresh Cycle (Read)
tRC
tRC
tRAS
tRAS
VIHVIL-
Address
VIHVIL-
VIHVIL-
VIHVIL-
tCLZ
I/O
440
VOHVOL-
Hi-Z
Data out
Hi-Z
Hidden Refresh Cycle (Write)
tRC
tRC
tHAS
RAS
tHAS
V,HV,L-
tCRP
CAS
V,HV,L-
Address
V,HV,L-
WE
V,HV,L-
twcs
I/O
tweH
V,HV,L- L...l"-l'--l'-lo~:....loI;...x;...x...lt...JI ~_ _ _ _ _.JI
Remark OE: Don't care
441
Timing Chart 8
443
Read Cycle
IRC
lRAS
lAP
Address
laz
vo
VOH Vex. _
Hi-Z
445
Early Write Cycle
Address
V..
VL
WE
VII
VL
va
V..
VL
fIIm.II:k OE : Don't care
446
Late Write Cycle
IRC
IA..
RAS
VIH
VL
ICSH
lASH
CAs
VH
VL
ICAS
Address
IIlE1l
1/0
~ .........~!:.~ ....... .
lOll
Dalain
447
Read Modify Write Cycle
tRWC
IRAS
RAS
VH
VL
ICSH
tACO
CAS
VH
VL
Address
VH
VL
WE
VII
VL
OE
VH
VL
XXXXXX>........................
110
110
448
lASH
tCAS
Voo _
Vo.. _
Hi·Z
.....................................................
Hi·Z
Fast Page Mode Read Cycle
lRASP
RAS
IRHCP
losH
CAS
tnl'
Vo<
VL
Ipc
v"
VL
Address
WE
vo
Val
Va. -_
Bmn.m:k
•••••••••••••••••t!i.:Z••.•....••..•..•
..t!i.:_~.
In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
449
Fast Page Mode Early Write Cycle
RAS
v.. _
VL _
v.. _
CAS
VL _
Address
v.. -
VL _
v.. _
WE
VL -
va
VII _
VL _
Bmnmk
450
OE : Don't care
In the fast page mode, read, Jlrite and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
Fast Page Mode Late Write Cycle
RAS
CAS
Address
V..
VL
v..
VL
V..
VL
WE
va
VCYrlVa. -
.BJm.m:k
In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
451
Fast Page Mode Read Modify Write Cycle
RAS
Address
aE
VOH _
va VOL _
va
In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
452
CAS Before RAS Refresh Cycle
RAS
.B.!In.!lrk
Address, WE, OE : Don't care
1/0 : Hi - Z
RAS Only Refresh Cycle
I ...
CAS
Address
Bmnm:k
WE, OE : Don't care
1/0: Hi-Z
453
Hidden Refresh Cycle (Read)
IRe
IRe
I...
I...
RAS
ICHI
ICPN
VOH _
CAS
Address
Vo. _
VOH _
VOL
-
VOH _
WE
VOL
-
VIIO _
OE
VOL
-
10EA
ICAe
IOLZ
la.z
I/O
454
VOH
VfYo. -_ ••••••••••••••••••••••••••••••• 1.1]:.1:.. ••••••••••••••••••••••
.•.....•....t!i.:.~.•..........
Hidden Refresh Cycle (Write)
IRe
IRe
IRAS
IRAS
RAS
V..
Address
V'L
Iwcs
t-_.::two:::.:....,_ .
V'H _
VII. -
va
V'H
V.. _
.Bmwu:k
DE : Don't care
455
Timing Chart 9
457
Read Cycle
lAP
IRAS
RAS
VHVLICSH
CAS
V..VL-
Address
V..VL-
WE
VHVL-
OE
VHVL-
10lZ
1=
va
Van-
Hi-Z
V01.- ---- ------ --- -- - -- -- -- ---- -- -- -- --- -- - - -- ---- ------ -- -- -- ---- ---
10...
DalaoUl
HI-Z
459
Early Write Cycle
top
RAS
V..VL1csH
CAS
VIHVL-
VIH-
Address Vu.-
vo
VIH-
VL-~~~~~~~~ ~________________~~~~~~~~~~~~~~~
Remerk OE : Don't care
460
Late Write Cycle
RAS VUlV ..lasH
CAS VOl-
Vo.-
VIH-
Address VII..-
461
Read Modify Write Cycle
RAS
V..-
V..-
Address V.. V'LtAwn
Icwn
WE V'H-
VL- '-~-L~~~~L-'I
lCEH
lCEA
OE
V'H-
V..-~~~~~~~~~~~~~~__¥
leAC
I/O
~~-
XXX>OOOO---------- -
1011
fils
Data In
10lZ
I/O
462
VOHHi-Z
VOL- ------------------------------
Hi-Z
--------------.------------------
Hyper Page Mode Read Cycle
RAS
CAS
Address
WE
V'HV'L-
V'HV'L-
V'HV'L-
IHpc
ICSH
~
IHCAS
IReD
~
~
~
J
IHCAB
t:.~~D.~
~
Col.
XX
ROW:~
!cP
~
}Ii
~n
~~
Col.
Col.
:)
m~
DE
~
I
IRAL
~
~
1l'
'--
lAsH
IHCAB
tOFR
toFC
:xx
'--=
-,
X-
~
~ f-+
I- !RAH ~
\;
LL//IJ
....
toep
tCAe
tCAe
toep
V'HV'L-
~
!RtlCP
V'HV'L-
\\\\ ,\\\\\\-$i
....
.
Jll
4
\\"S:
~
-
}
!RAe
....
VD
VOHVOL-
~
_______________t'!: __________
~
~
~
tCAc
;.
Data out
~--O
Data out
toez
--0
Data out
---
RllImark In the hyper page mode, read,write and read modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
463
Hyper Page Mode Read Cycle (WE Control)
IRASP
RAS
tRHCP
VIHV..ICSIf
CAS
VIHV.. -
Address
V..VIL-
WE
V,HV,L-
OE
V,HV,L-
VO
Va..-
Vr:Itf- •••••••••••••••tl!:l. ...•......
Remark In the hyper page mode, read,write and read modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
464
Hyper Page Mode Read Cycle (OE Control)
RAS Vt1VLICSH
10f'<:
IRsH
Address Vt1VL-
VOH-
HI-Z
1/0 VOl- -------------------------
Rom ark In the hyper page mode, read,write and read modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
465
Hyper Page Mode Early Write Cycle
Addross
~::=
V,H,-
V,L- --l~...I....l....1.."'+-+-+__-'lI-__~++__-+_ _--i'---t+__-+..J....c...-'-"-""'~-L....L._
va
Dalaln
[)alan
Data in
Remark 1. OE: Don't care
2. In the hyper page mode, read,write and read modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
466
Hyper Page Mode Late Write Cycle
V..- - - - " ' "
V..-
tRltCP
CAS
Address V,HVOL-
V,H- --,-r-r-r..,.-ofr-----'\I
VOL- I.....ot--'....L....L-J
va
Remark In the hyper page mode, read,write and mild modify write cycles are available
for each of the consecutive CAS cyclos within thu same
RAS cycle.
467
Hyper Page Mode Read Modify Write Cycle
tRASP
RAS V ..Vn.-
CAS V,H-
V,l-
Add
VIH-
ress V,l-
VO
Hi-Z
VDl- .----------------
VDH-
va ~:=
.----------------------
Remark In the hyper page mode, read,write and read modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
468
Hyper Page Mode Read and Write Cycle
RAS
InHCP
VIHVu.leaH
CAS
VIHVII.-
Address
VIHVL-
WE
VIHVII.-
DE
VIHVL-
vo
VOHHi.Z
Va..- ................................
va
VIHVL-
"1iI.~
_ _ _...lI:.-lo~_ _-"r
••••••••••I:!t:!-. •••••••••••••.
Remark In the hyper page mode, read,wrlte and read modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
469
CAS Before RAS Refresh Cycle
tN:
CAS VOlVo.-
----~~------~------------~--------~----------~~
Ramark Address, WE, OE : Don't care
I/O : Hi-Z
RAS Only Refresh Cycle
tAP
CAS Vr.tV..-
AddressV'HV'L-
Remark WE, OE : Don't care 1/0: Hi-Z
470
tRAS
Hidden Refresh Cycle (Read)
IRe
RAS
V,HV,L-
CAS
V,HV,L-
Address
V,HV,L-
IRSH
leMA
twHn
WE
V,HVL-
tolZ
IZ
VOH1/0 VOL-
•••••••••••••••••':!!:!:. •••.•••.••..••••••••••••
Data Out
471
Hidden Refresh Cycle (Write)
IRe
RAS V,I---------- -------- tcxz
VOH-
Hi-Z
va V~-------------------------------
478
Hi-Z
Hyper Page Mode Read Cycle
RAS
tRHCP
VIHVIL-
IcsH
CAS
Address
WE
VIHVIL-
VIHVIL-
VIHVIL-
IAcp
OE
VO
VIHVIL-
IAA
tcAc
VOH- •••••••••••••••t't:l. ..•.......
VOL-
Remark In the hyper page mode, read,write and ruad modify write cycles are available
for each of the consecutive CAS cyclos within the same RAS cycle.
479
Hyper Page Mode Read Cycle (WE Control)
tRASP
RAS
VIHVa.-
tCSH
CAS
V'HV'L-
Address
VIHVL-
WE
V'HV'L-
OE
V'HV'L-
VO
Vot.-
VCH- ••• _•••• _••••••t1i:! •••••••• __
Data out
Remark In the hyper page mode, read,write and read modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
480
Hyper Page Mode Read Cycle (OE Control)
Address VHVL-
va
VOHHI-Z
Va..- -------------------------
Remark In tho hyper page mode. read.wrlte and read modify write cycles are available
for each of the consecutive CAS cycles withIn the same BAS cycle.
481
Hyper Page Mode Early Write Cycle
Address V,H-
VOL-
V,H-
V,L- ..........~......~"-f-1-+--+----t--H---+---fo-lH---+-"-''-'............''-''-''-'-
V,H-
VO
V,L- ........................,"-"' 1 ' - - - - - - ' 1
Remark 1. OE: Don't care
2. In the hyper page mode, read,write and read modify write ~cles are available
for each of the consecutive CAS cycles within the same RAS cycle.
482
Hypor Page Modo Late Writo Cycle
tRAIl,
V.. V..-
Address
V'HV'L-
WE
V'HV'L-
OE
V'HV'L-
VO
Remark In the hyper page mode, read,write and rood modify write cycles are available
for each of the consecutive CAS cycles within the same RAS cycle.
483
Hvper Pogo Mode Read Modify Write Cycle
-
V'H-
CAS VIl-
Addresa VV..-
IL-
VOH-
Hi-Z
VO VOL- -----------------
VIH-
VO V..- ----------------------Remark In the hyper page mode, read.write and read modify write cycles are available
for each of the consecutive CAS cycles within the same AAS cycle.
484
Hvper Page Mode Read and Write Cvcla
bwlp
ImlCP
VIHVILIcBH
CAS
VIHVL-
Address
VIHVIL-
WE
VIHVL-
OE
VIHVL-
I/O
VOHHi-Z
Va..- ----------------------------- ••• 1171'----,..Il;-'~_____f
••••••••• Jj~:l_.. •••••••••••••.
IDB
IDH
VO
Romom In the hyper page mode, read,wrlte and read modify write cycles are available
for each of tho consecutive CAS cycles within the same RAS cycle.
485
CAS Before RAS Refresh Cycle
CAS
VIHVIL- _ _~~_-I+__-4_ _ _ _ _ _---14_ _ _ _--'1I-_ _ _ _ _ _...l....J
Remerk 1. Address, OE : Don't care
2.1/0: Hi-Z
RAS Only Refresh Cycle
tAAS
Remark 1. OE : Don't care
2.1/0: Hi-Z
486
Hidden Refresh Cycle (Read)
IRe
RAS
IRc
V'HV'L-
latA
V'HV'L-
Address
V'HV'L-
IwtrR
WE
OE
VIHV..-
VIIt-
V..-
VOH110 VOL-
• ________________t'l
:~
LZ
_______________________
•
Data Out
487
Hidden Refresh Cycle (Write)
IRe
RAS V,IIVIL-
CAS V,IIV,L-
Address VIH-
VL-
WE
V,IIV,L-
Remert DE: Don't care
488
Source Exif Data:
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