1995_National_Application_Specific_Analog_Products_Databook 1995 National Application Specific Analog Products Databook

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APPLICATION SPECIFIC
ANALOG PRODUCTS
DATABOOK
1995 Edition

Audio Circuits.
Video Circuits
Automotive
Special Functions
Surface Mount
Appendices/Physical Dimensions

II
PI

II
II
II
[I

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iii

Table of Contents
Alphanumeric Index .......................................................... .
Additional Available Linear Devices ............................................ .
Industry Package Cross Refere,:!cE(l Guide ....................................... .
Section 1 Audio Circuits
Audio Power Amplifiers

viii
xii
xxvi

. ,

Audio Power Amplifiers-Selection Guide ....................................... .
1-4
LM380 Audio Power Amplifier .........•........................................
1-6
LM383/LM383A 7W Audio Power Amplifier ..........................."... .'......•
1-10
LM384 5W Audio PowerAll1plifier .......................... ,~ ..... '.' '.' .... .' ..... .
1-14
1-19
LM386 Low Voltage Audio Power Amplifier ................. ~ ....... .' ..........• : .
LM388 1.5W AudiO Power Amplifier ............... ~ ........ ; ....... '......... ~; ..
1-24
LM3S'9 Low Voltage Audio Power Amplifier with NPN Transistor Array .............. .
1-30
lM390 1W Battery Operated Audio Power Amplifier .............................. .
1-38'
LM391 Audio Power Driver: ................................................... .
1-43
LM831 Low Voltage Audio Power Amplifier ...................................... .
1-54
LM1875 20W Audio Power Amplifier ........................................... .
1-66
Lf,,'11876 Dual 20W Audio Power Amplifier with Mute and Standby Modes ........... .
1-7~
LM1877 Dual Audio Power Amplifier ........................................... .
1-73
1-78
LM1896/LM2896 Dual Audio Power Amplifiers ....... ; ........................... .
, LM4700 Overture™ 30W Audio Power Amplifier with Mute and Standby Modes ..... .
1-86
LM2876 High-Perlormance 40W Audio Power Amplifier with Mute .......•...........
1-87
LM2877 Dual 4W Audio Power Amplifier ...........' ...... , ...................... . 1-103
LM2878 Dual 5W Audio Power Amplifier ........................................ . 1-110
LM2879 Dual'iJW AUdio Power Amplifier ............ ,': .....•...................•. '1-117
LM3875 High Performance 56W Audio Power Amplifier .........................•.. 1-124
LM3876 High Performance 56W Audio Power Amplifier with Mute .................. . 1-140
LM3886 High-Performance 68W Audio Power Amplifier with Mute .................. . 1-156
LM4860 1W Audio Power Amplifier with Shutdown Mode ......................... . 1-173
LM4861 %W Audio Power Amplifier with Shutdown Mode ........................ . 1-182
LM4862 350 mW Audio Power Amplifier with Shutdown Mode ..................... . 1-189
LM4880 Dual 200 mW Audio Power Amplifier with Shutdown Mode ...........•..... 1-190
Audio Controls

Audio Control-Selection Guide ............................................... .
LM1036 Dual PC Operated TonelVolume/Balance Circuit ........................ .
LM1971 JA-Pot 62 dB Digitally Controlled Audio Attenuator with Mute ................ .
LM 1972 JA-Pot 2-Channel 78 dB Audio Attenuator with Mute ....................... .
LM 1973 JA-Pot 3-Channel 76 dB Audio Attenuator with Mute ....................... .
LMC835 Digital Controlled Graphic Equalizer .................................... .
LMC1982 Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable
Stereo Inputs ............................................................. .
LMC1983 Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable
Stereo Inputs ............................................................. .
LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel
Input-Selector ............................................................. .

1-191
1-192
1-201
1-202
1-211
1-220
1-235
1-246
1-257

Audio Operational Amplifiers

Audio Operational Amplifiers-Selection Guide .................................. .
LM387 /LM387 A Low Noise Dual Preamplifier ................................... .
LM833 Dual Audio Operational Amplifier ........................................ .
LM837 Low Noise Quad Operational Amplifier ................................... .
LM6142 Dual and LM6144 Quad High Speed/Low Power 17 MHz Rail-to-Rail
Input-Output Operational Amplifiers .......................................... .

iv

1-269
1-270
1-274
1-283
1-289

Table of Contents (Continued)
Section 1 Audio Circuits (Continued)
Audio Noise Reduction
Audio Noise Reduction-Selection Guide ....................................... .
LM1131A/LM1131B/LM1131C Dual Dolby B-Type Noise Reduction Processor ...... .
LM1894 Dynamic Noise Reduction System DNR® ............................... .

1-300
1-301
1-306

Section 2 Video Circuits
Video Circuits-Selection Guide ............................................... .
Video-Definition of Terms ................................................... .

2-3
2-6

Video Preamplifiers
LM1201 Video Amplifier System ............................................... .
LM1202 230 MHz Video Amplifier System ...................................... .
LM1203 RGB Video Amplifier System .......................................... .
LM1203A 150 MHz RGB Video Amplifier System ............................ ; ... .
LM1203B 100 MHz RGB Video Amplifier System ................................ .
LM1204 150 MHz RGB Video Amplifier System .................................. .
LM1205/LM1207 130 MHz/85 MHz RGB Video Amplifier System with Blanking ..... .
LM1208/LM1209 130 MHz/1 00 MHz RGB Video Amplifier System with Blanking .... .
LM1212 230 MHz Video Amplifier System with OSD Blanking ..................... .
LM1281 85 MHz RGB Video Amplifier System with On Screen Display (OSD) ........ .

2-8
2-21
2-37
2-51
2-67
2-81
2-99
2-121
2-143
2.144

CRT Drivers
LM2416/LM2416C Triple 50 MHz CRT Drivers ................................. ..
LM2418 Triple 30 MHz CRT Driver ............................................ ..
LM2419 Triple 65 MHz CRT Driver ............................................. .
LM2427 Triple 80 MHz CRT Driver ............................................. .

2-145
2-149
2-153
2-160

Video Special Functions
LM1291 Video PLL System for Continuous Sync Monitors ........................ ..
LM 1295 DC Controlled Geometry Correction System for Continuous Sync Monitors .. .
LM1391 Phase-Locked Loop ................................................... .
LM1823 Video IF AmplifierIPLL Detector System ................................ .
LM 1881 Video Sync Separator ............................................... ..
LM1882. 54ACT174ACT715 Programmable Video Sync Generators ............... .
LM2889 TV Video Modulator ................................................. ..

2-165
2-174
2-183
2-188
2-195
2-203
2-215

Flat Panel Display Circuits
LM61 04 Quad Gray Scale Current Feedback Amplifier ............................ .
LM8305 STN LCI? Display Bias Voltage Source ................................. ..
LMC6008 8 Channel Buffer .................................................. ..

2-224
2-228
2-229

High Speed Amplifiers
LM6152 Dual/LM6154 Quad High Speed/Low Power 45 MHz Rail-to-RailI/O
Operational Amplifiers ..................................................... .
LM6161 ILM6261 ILM6361 High Speed Operational Amplifiers .................... .
LM6162/LM6262/LM6362 High Speed Operational Amplifiers .................... .
LM6164/LM6264/LM6364 High Speed Operational Amplifiers .................... .
LM6165/LM6265/LM6365 High Speed Operational Amplifiers .................... .
LM6171 Voltage Feedback Low Distortion Low Power Operational Amplifier .. ; ...... .
LM6181 100 mA, 100 MHz Current Feedback Amplifier ........................... .
LM6182 Dual 100 mA Output, 100 M Hz Dual Current Feedback Amplifier ........... .
LM7131 Tiny High Speed Single Supply Operational Amplifier ..................... .
LM7171 Very High Speed High Output Current Voltage Feedback Amplifier ......... .

2-232
2-233
2-240
2-248
2-256
2-263
2-277
2-294
2-315
2-337

High Speed Buffers
LM6121 ILM6221 ILM6321 High Speed Buffers ......... ; ........................ .
LM6125/LM6225/LM6325 High Speed Buffers .................................. .

v

2-338
2-344

Table of Contents (Continued)
Section 3 Automotive
Power SwitcheslPeripheral Drivers
Peripheral Drivers .............................................. '. . . . . . . . . . . . . .
Peripheral Drivers Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Current ; .................................................... .-. . . . . . . . . . .
DP731 0/DP831 0/DP7311/DP8311 Octal Latched Peripheral Drivers ...............
DS1631/DS3631/DS1632/DS3632/DS1633/DS3633/DS1634/DS3634 CMOS Dual
Peripheral Drivers ..........................................................
DS2003/DS9667/DS2004 High Current/Voltage Darlington Drivers ............. ;...
DS3658 Quad High Current Peripheral Driver ................ : . . . . . . . . . . . . . . . .. . . .
DS3668 Quad Fault Protected Peripheral Driver ........ . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3680 Quad Negative Voltage Relay Driver. . . . . . . . . . . .. . . . . . . . . . . . . . . . .. . . . . .. .
DS55451 12/3/4, DS75451 12/3/4 Series Dual Peripheral Drivers. . . . . . . . . . . . . . . . . . .
LM1921 1 Amp Industrial Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1950 750 mA High Side Switch ...................................... ; ..'. . . . .
LM1951 Solid State 1 Amp Switch ......... ~ . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . .
LM9061 Power MOSFETDriver with Lossless Protection ..........................
LMD18400 Quad High Side Driver. .. . .... . .. ....... ... .. .. . ........ . . ... . ..•...
Voltage Regulators
Low Dropout Voltage Regulators-Definition of Terms. ....... .. . ... . .. . . ... . .. .. ..
Low Dropout Regulators Selection Guide . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1577/LM2577 SIMPLE SWITCHER Step-Up Voltage Regulators. . . . . . . . . . . . . . . . .
LM2925 Low Dropout Regulator with Delayed Reset ......................... ; . . . .
LM2926/LM2927 Low Dropout Regulators with Delayed Reset. . . . . . . . . . . . . . . . . . . . .
LM2931 Series Low Dropout Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2935 Low Dropout Dual Regulator .............. '........... ;. . . . . . . . . . . . . . . . .
LM2936 Ultra-Low Quiescent Current 5V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2937 500 mA Low Dropout Regulator... ..... .. .... ..... .. . .. ....... .. ........
LM2940/LM2940C 1A Low Dropout Regulators..................................
LP2950/ A-XX and LP2951 / A-XX Series of Adjustable Micropower Voltage
Regulators ..............................'. .. .. .. .... ...... ... .. . . .. .. .... ..
LM2984 Microprocessor Power Supply System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automotive Application Specific Standard Products
Automotive Application Specific Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM903 Fluid Level Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 1042 Fluid Level Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1815 Adaptive Variable Reluctance Sensor Amplifier...........................
LM1819 Air-Core Meter Driver .... )... .... ... ......... .... .. . ... ... .......... ...
LM1830 Fluid Detector. . ... ... ... ... .. .. ..... .. .. ... .. .. .. . .. . ..... . .... ... ...
LM1946 Over/Under Current Limit Diagnostic Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1949 Injector Drive Controller ...............................................
LM9044 Lambda Sensor Interface Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM2907/LM2917 Frequency to Voltage Converter ........ '. . . .. . . . . . . . . . . . . . . . . . . .

3-3
3-4
3-5
3-6
3-13
3-18
3-23
3-26
3-29
3-32
3-44
3-49
3-54
3-62
3-74
3-90
3-91
3-92
3-114
3-120
3-128
3-136
3-144
3-149
3-154
3-164
3-179
3-192
3-193
3-199
3-206
3-210
3-218
3-224
3-235
3-243
3-247

Section 4 Special Functions
Display Drivers
Display Driver Selection Guide .............................................. ;. . 4 - 3
LSI Display Driver ............................................................
4-4
DS0026 5 MHz Two Phase MOS Clock Drivers ............ '...................... ~
4-6
DS75491 MOS-to-LED Quad Segment Driver ....................................
4-13
DS75492 MOS-to-LED Hex Digit Driver..........................................
4-13
DS75494 Hex Digit Driver. . . . . . . . . . . .. . . . .. . . . . . . . .. . . . . . . . . . .. . . . . .. . . . . . . . . . .
4-16

vi

Table of Contents (Continued)
Section 4 Special Functions (Continued)
LM3909 LED Flasher/Oscillator ............................................... .
LM3914 Dot/Bar Display Driver ............................................... .
LM3915 Dot/Bar Display Driver ............................................... .
LM3916 Dot/Bar Display Driver ............................................... .
MM5450/MM5451 LED Display Drivers ........................................ .
MM5452/MM5453 Liquid Crystal Display Drivers ................................ .
MM5480 LED Display Driver .................................................. .
MM5481 LED Display Driver .................................................. .
MM5483 Liquid Crystal Display Driver .......................................... .
MM5484 16-Segment LED Display Driver ....................................... .
MM5486 LED Display Driver .................................................. .
MM58241 High Voltage Display Driver .......................................... .
MM58341 High Voltage Display Driver .......................................... .
MM58342 High Voltage Display Driver .......................................... .
Radio Circuits
LM565/LM565C Phase Locked Loops ......................................... .
LM567/LM567C Tone Decoders .............................................. .
LM1596/LM1496 Balanced Modulator-Demodulators ............................ .
LM1865 Advanced FM IF System .............................................. .
LM1868 AMlFM Radio System ................................................ .
LM 1893/LM2893 Carrier-CurrentTransceiver ................................... .
LMC567 Low Power Tone Decoder ............................................ .
LMC568 Low Power Phase-Locked Loop ....................................... .
Timers and Oscillators
LM122/LM322/LM3905 Precision Timers ...................................... .
LM555/LM555C Timers ................................................. , .... .
LM556/LM556C Dual Timers ................................................. .
LM566C Voltage Controlled Oscillator .......................................... .
LMC555 CMOS Timer ........................................................ .
MM5368 CMOS Oscillator Divider Circuit ................................•.......
MM5369 17 Stage Oscillator/Divider ........................................... .
Ground Fault Interrupters
LM1851 Ground Fault Interrupter ........................................ '...... .
Section 5 Surface Mount
Packing Considerations (Methods, Materials and Recycling). . . . . . . . . . . . . . . . . . . . . . . .
Board Mount of Surface Mount Components ...... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Soldering Profiles-Surface Mount ...............................
AN-450 Small Outline (SO) Package Surface Mounting Methods-Parameters and
Their Effect on Product Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
Land Pattern Recommendations ...............................................
Section 6 Appendices/Physical Dimensions
Appendix A General Product Marking and Code Explanation .......................
Appendix B Device/ Application Literature Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . .
Appendix C Summary of Commercial Reliability Programs. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix D Military Aerospace Programs from National Semiconductor. . . . . . . . . . . . . .
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . ..
Appendix F How to Get the Right Information from a Datasheet . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

vii

4-18
4-25
4-40
4-58
4-78
4-84
4-91
4-95
4-99
4-102
4-105
4-110
4-115
4-120
4-125
4-133
4-139
4-144
4-158
4-1,66
4-188
4-192
4-196
4-208
4-216
4-220
4-224
4-227
4-230
4-233
5-3
5-19
5-23
5-24
5-35
6-3
6-4
6-10
6-11
6-21
6-26
6-30

Alpha-Numeric Index
54ACT715 Programmable Video Sync Generator ..................... ; ...................... 2-203
74ACT715 Programmable Video Sync Generator .................. ; ..... : ............... ; ... 2-203
AN-450 Small Outline (SO) Package Surface Mounting Methods-Parameters and Their
Effect on Product Reliability ...............................•.............................. 5-24
Board Mount of Surface Mount Components ...................... ; .•............... '......... 5-19
DP731 0 Octal Latched Peripheral Driver ..................... ;,' ......... , ..................... 3-6
DP7311 Octal Latched Peripheral Driver ......................... '...... '... ~ ....... ; ........... 3-6
DP8310 Octal Latched Peripheral Driver ...................................................... 3-6
DP8311 Octal Latched Peripheral Driver ...................................................... 3-6
DS0026 5 MHz Two Phase MOS Clock Drivers .•..................... ; ........................ 4-6
DS1631 CMOS Dual Peripheral Driver ......................... ; ..................•.......... 3-13
DS1632 CMOS Dual Peripheral Driver .................................... ; .................. 3-13
DS1633 CMOS Dual Peripheral Driver ......................... ; ..................... ; ....... 3-13
DS1634 CMOS Dual Peripheral Driver ............................ ~ .......................... 3-13
DS2003 High Current/Voltage Darlington Driver ..................... ; '........................ 3-18
DS2004 High CurrentlVoltage Darlington Driver ............................................ ; . 3-18
DS3631 CMOS Dual Peripheral Driver ......................... , , .. ; ......................... 3-13
DS3632 CMOS Dual Peripheral Driver ....................................................... 3-13
DS3633 CMOS Dual Peripheral Driver ......................•............. ~ ........ ~ ......... 3-13
DS3634 CMOS Dual Peripheral Driver ...........................................'............ 3-13
DS3658 Quad High Current Peripheral Driver ....................... , ......................... 3-23
DS3668 Quad Fault Protected Peripheral Driver ....... ;' ...................................... 3-26
DS3680 Quad Negative Voltage Relay Driver ..........•......... '............................. 3-29
DS9667 High Current/Voltage Darlington Driver .............................................. 3-18
DS55451 Series Dual Peripheral Driver .............................................. ·........ 3-32
DS55452 Series Dual Peripheral Driver ................................................. : .... 3-32
DS55453 Series Dual Peripheral Driver ............................................ : ......... 3-32
DS55454 Series Dual Peripheral Driver .......................... , ........................... 3-32
DS75451 Series Dual Peripheral Driver ...................................................... 3-32
DS75452 Series Dual Peripheral Driver ...................................................... 3-32
DS75453 Series Dual Peripheral Driver ...................................................... 3-32
DS75454 Series Dual Peripheral Driver ...................................................... 3-32
DS75491 MOS-to-LED Quad Segment Driver ............................. " ................. 4-13
DS75492MOS~to-LED Hex DigitDriver ....................................................... 4-13
DS75494 Hex Digit Driver ...............•.............................•.................. '.. ,4-16
Land Pattern Recommendations ............................................. ; ............. 5-35
LM122 Precision Timer ..........................................•........................ 4-196
LM322 Precision Timer ........................... " .....................•.. ; ........... ~' ... 4-196
LM380 Audio Power Amplifier ............ " ........................................... ; ....... 1-6
LM383 7W Audio Power Amplifier .......................................... '................. 1-10
LM384 5W Audio Power Amplifier ............................................ : ........•...... 1-14
LM386 Low Voltage Audio Power Amplifier .......... ~ ......•.•... , .......................... 1-19
LM387ILM387A Low Noise Dual Preamplifier ....... ; ................... " . '....... , .......... 1-270
LM388 1.5W Audio Power Amplifier ...................... , ...............•.................. 1-24
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array ............................ 1-30
LM390 1W Battery Operated Audio Power Amplifier .............. , . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 1-38
LM391 Audio Power Driver ........................ , .......... ,' ............ , ... " ............... 1-43
LM555 Timer ........................... ,', ........... , ..... : ............................ , . , " 4-208
LM55SC Timer ................................................................... ; .... " .. 4-208
LM556 Dual Timer .................................................................. , .... 4-216
LM556C Dual Timer ..................................................................... 4-216

viii

Alpha-Numeric

Index(continUed)

LM565 Phase Locked Loop ............................................................... 4-125
LM565C Phase Locked Loop ............................................................. 4-125
LM566C Voltage Controlled Oscillator ...................................................... 4-220
LM567 Tone Decoder. ................................................................... 4-133
LM567C Tone Decoder .................................................................. 4-133
LM831 Low Voltage Audio Power Amplifier .................................................. 1-54
LM833 Dual Audio Operational Amplifier .................................................... 1-274
LM837 Low Noise Quad Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-283
LM903 Fluid Level Detector. .............................................................. 3-193
LM1036 Dual DC Operated Tone/Volume/Balance Circuit .................................... 1-192
LM1042 Fluid Level Detector .......................................................•..... 3-199
LM1131 Dual Dolby B-Type Noise Reduction Processor ...................................... 1-301
LM1201 Video Amplifier System ..............................................................2-8
LM1202 230 MHz Video Amplifier System .................................................... 2-21
LM1203 RGB Video Amplifier System ....................................................... 2-37
LM1203A 150 MHz RGB Video Amplifier System ............................................. 2-51
LM1203B 100 MHz RGB Video Amplifier System ........................ , .................... 2-67
LM1204 150 MHz RGB Video Amplifier System ............................................... 2-81
LM1205 130 MHz RGB Video Amplifier System with Blanking .................................. 2-99
LM1207 85 MHz RGB Video Amplifier System with Blanking ................................... 2-99
LM1208 130 MHz RGB Video Amplifier System with Blanking ................................. 2-121
LM1209 100 MHz RGB Video Amplifier System with Blanking ................................. 2-121
LM1212 230 MHz Video Amplifier System with OSD Blanking ................................. 2-143
LM1281 85 MHz RGB Video Amplifier System with On Screen Display (OSD) ................... 2-144
LM1291 Video PLL System for Continuous Sync Monitors .................................... 2-165
LM1295 DC Controlled Geometry Correction System for Continuous Sync Monitors .............. 2-174
LM1391 Phase-Locked Loop ............................................................. 2-183
LM1496 Balanced Modulator-Demodulator ... ~ ......................................,....•... 4-139
LM1577 SIMPLE SWITCHER Step-Up Voltage Regulator .... ; ......•..................' ........ 3-92
LM1596 Balanced Modulator-Demodulator .............................................. ; .. 4-139
LM1815 Adaptive Variable Reluctance Sensor Amplifier ...................................... 3-206
LM1819 Air-Core Meter Driver ......................................................'...•.. 3~210
LM1823 Video IF Amplifier/PLL Detector System ............................................ 2-188
LM1830 Fluid Detector ........................................................•.......... 3-218
LM1851 Ground Faultlnterrupter .. ,' .......... ; .................. '! . . . . . . . . . . . . . . . . . . . . . . . . . 4-233
LM1865 Advanced FM IF System ............................................,.............. 4"144
LM1868 AM/FM Radio System ........................................................... 4-158
LM1875 20W Audio Power Amplifier .............. '..........................•............... 1-66
LM1876 Dual 20W Audio Power Amplifier with Mute and Standby Modes ....................•... 1-72
LM1877 Dual Audio Power Amplifier ........................ ,.,............................... 1-73
LM1881 Video Sync Separator ............................................................ 2-195
LM1882 Programmable Video Sync Generator .............................................. 2-203
LM1893 Carrier-Current Transceiver ...... ~ ...... _......................................... 4-166
LM1894 Dynamic Noise Reduction System DNR® ..... ; '..................................... 1-306
LM1896 Dual Audio Power Amplifier ........................................................ 1-78
LM1921 1 Amp Industrial Switch ............................... ; ..... ; ..... ; ................ 3-44
LM1946 Over/Under Current Limit Diagnostic Circuit. ........................................ 3-224
LM1949 Injector Drive Controller ..........•............................................... 3-235
LM1950 750 rnA High Side Switch .......................................................... 3-49
LM1951 Solid State 1 Amp Switch .......................................................... 3-54
LM1971 p.Pot 62 dB Digitally Controlled Audio Attenuator with Mute ............................ 1-201

ix

--::::r-

Alpha-Numeric

Index(continued)

LM1972 /LPot 2-Channel 78 dB Audio Attenuator with Mute ................................... 1-202
LM1973 /LPot 3-Channel 76 dB Audio Attenuator with Mute ..................................• 1-211
LM2416 Triple 50 MHz CRT Driver ......................................................... 2-145
LM2416C Triple 50 MHz CRT Driver ....................................................... 2-145
LM2418 Triple 30 MHz CRT Driver ......................................................... 2-149
LM2419 Triple 65 MHz CRT Driver .................................... ; .................... 2-153
LM2427 Triple 80 MHz CRT Driver ......................................................... 2-160
LM2577 SIMPLE SWITCHER Step-Up Voltage Regulator .. ~ ........•.......................... 3-92
LM2876 High-Performance 40W Audio Power Amplifier with Mute .............................•. 1-87
LM2877 Dual4W Audio Power Amplifier .................................................... 1-103
LM2878 Dual 5W Audio Power Amplifier .................................................... 1-110
LM2879 Dual 8W Audio Power Amplifier .................................................... 1-117
LM2889 TV Video Modulator .............................................................. 2-215
LM2893 Carrier-CurrentTransceiver ....................................................... 4-166
LM2896 Dual Audio Power Amplifier ........................................................ 1-78
LM2907 Frequency to Voltage Converter ............. '.' .................................... 3-247
LM2917 Frequency to Voltage Converter ...................•............................... 3-247
LM2925 Low Dropout Regulator with Delayed Reset ......................................•.. 3-114
LM2926 Low Dropout Regulator with Delayed Reset ......................................... 3-120
LM2927 Low Dropout Regulator with Delayed Reset ....•.................. ; ................. 3-120
LM2931 Series Low Dropout Regulators .................................................... 3-128
LM2935 Low Dropout Dual Regulator ...................................................... 3-136
LM2936 Ultra-Low Quiescent Current 5V Regulator ........................................... 3-144
LM2937 500 mA Low Dropout Regulator ......•....... ; ..................................... 3-149
LM2940/LM2940C 1A Low Dropout Regulators ............................................. 3-154
LM2984 Microprocessor Power Supply System .............................................. 3-179
LM3875 High Performance 56W Audio Power Amplifier ....................................... 1-124
LM3876 High Performance 56W Audio Power Amplifier with Mute .............................. 1-140
LM3886 High-Performance 68W Audio Power Amplifier with Mute ....•........................ 1-156
LM3905 Precision Timer ............. , .................................................... 4-196
LM3909 LED Flasher/Oscillator ............................................................ 4-18
LM3914 Dot/Bar Display Driver .............................................................. 4-25
LM3915 Dot/Bar Display Driver ........................................ : ................... 4-40
LM3916 Dot/Bar Display Driver ..................•......................................... 4-58
LM47000verture™ 30W Audio Power Amplifier with Mute and Standby Modes .................. 1-86
LM4860 1W Audio Power Amplifier with Shutdown Mode ..................................... 1-173
LM4861 %W Audio Power Amplifier with Shutdown Mode .................................... 1-182
LM4862 350 mW Audio Power Amplifier with Shutdown Mode ................................. 1-189
LM4880 Dual 200 mW Audio Power Amplifier with Shutdown Mode ............................ 1-190
LM61 04 Quad Gray Scale Current Feedback Amplifier ....................................... 2-224
LM6121 High Speed Buffer ............................................................... 2-338
LM6125 High Speed Buffer .............•..............•.•.................................. 2-344
LM6142 Dual High Speed/Low Power 17 MHz Rail-to-Raillnput-Output Operational Amplifier ..... 1-289
LM6144 Quad High Speed/Low Power 17 MHz Rail-to-Raillnput-Output Operational Amplifier .... 1-289
LM6152 Dual High Speed/Low Power 45 MHz Rail-to-Raill/O Operational Amplifier ............. 2-232
tM6154 Quad High Speed/Low Power 45 MHz Rail-to-Raill/O Operational Amplifier ............ 2-232
LM6161 High Speed Operational Amplifier ................ ; .•............................... 2-233
LM6162 High Speed Operational Amplifier .................................................. 2-240
LM6164 High Speed Operational Amplifier .................................................. 2·248
LM6165 High Speed Operational Amplifier .................................................. 2·256
LM6171 Voltage Feedback Low Distortion Low Power Operational Amplifier .................... 2·263

x
-"""'-

Alpha-Numeric

Index(continUed)

LM6181 100 rnA, 100 MHz Current Feedback Amplifier ....................................... 2-277
LM6182 Dual 100 rnA Output, 100 MHz Dual Current Feedback Amplifier ....................... 2-294
LM6221 High Speed Buffer ............ , .....................•............................ 2-338
LM6225 High Speed Buffer .......................... , .................................... 2-344
LM6261 High Speed Operational Amplifier .................................................. 2-233
LM6262 High Speed Operational Amplifier .................................................. 2-240
LM6264 High Speed Operational Amplifier .................................................. 2-248
LM6265 High Speed Operational Amplifier ....................................... , .. , ....... 2-256
LM6321 High Speed Buffer ............................................................... 2-338
LM6325 High Speed Buffer ..................... , ......................................... 2-344
LM6361 High Speed Operational Amplifier .................................................. 2-233
LM6362 High Speed Operational Amplifier .................................................. 2-240
LM6364 High Speed Operational Amplifier .................................................. 2-248
LM6365 High Speed Operational Amplifier .................................................. 2-256
LM7131 Tiny High Speed Single Supply Operational Amplifier ................................. 2-315
LM7171 Very High Speed High Output Current Voltage Feedback Amplifier ..................... 2-337
LM8305 STN LCD Display Bias Voltage Source ............................................. 2-228
LM9044 Lambda Sensor Interface Amplifier ................................................. 3-243
LM9061 Power MOSFET Driver with Lossless Protection ...................................... 3-62
LMC555 CMOS Timer ... , ................. , .................. , ............. , .. , .. , . , ..... 4-224
LMC567 Low Power Tone Decoder .................................... , ................... 4-188
LMC568 Low Power Phase-Locked Loop ................................................... 4-192
LMC835 Digital Controlled Graphic Equalizer ................................................ 1-220
LMC1982 Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo
Inputs ............................................................................•.. 1-235
LMC1983 Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable Stereo
Inputs ............................................................................... 1-246
LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel
Input-Selector ........................................................................ 1-257
LMC6008 8 Channel Buffer ............................................................... 2-229
LMD18400 Quad High Side Driver .......................................................... 3-74
LP2950/ A-XX Series of Adjustable Micropower Voltage Regulators ..................... , ...... 3-164
LP2951 / A-XX Series of Adjustable Micropower Voltage Regulators ............................ 3-164
MM5368 CMOS Oscillator Divider Circuit ................................................... 4-227
MM5369 17 Stage Oscillator/Divider ....................................................... 4-230
MM5450 LED Display Driver ............................................................... 4-78
MM5451 LED Display Driver .......................................................... , .... 4-78
MM5452 Liquid Crystal Display Driver ....................................................... 4-84
MM5453 Liquid Crystal Display Driver ....................................................... 4-84
MM5480 LED Display Driver ............................................................... 4-91
MM5481 LED Display Driver ............................................................... 4-95
MM5483 Liquid Crystal Display Driver ....................................................... 4-99
MM5484 16-Segment LED Display Driver ................................................... 4-102
MM5486 LED Display Driver .............................................................. 4-105
MM58241 High Voltage Display Driver ..........................•.................... , ..... 4-110
MM58341 High Voltage Display Driver ..................................................... 4-115
MM58342 High Voltage Display Driver ..................................................... 4-120
Packing Considerations (Methods, Materials and Recycling) ...................................... 5-3
Recommended Soldering Profiles-Surface Mount ........................................... 5-23

xi

Additional Available Linear Devices
ADC0800 8-Bit AID Converter ....................... ~ ........... Section 2
ADC0801 8-Bit p.P Compatible AID Converter .. ; .................. Section 2
ADC0802 8-Bit p.P Compatible AID Converter ..................... Section 2
ADC0803 8-Bit p.P Compatible AID Converter ..................... Section 2
ADC0804 8-Bit p.P Compatible AID Converter ..................... Section 2
ADC0805 8-Bit p.P Compatible AID Converter ..................... Section 2
ADC0808 8-Bit p.P Compatible AID Converter with 8-Channel
Multiplexer .................................................. Section 2
ADC0809 a-Bit p.P Compatible AID Converter with 8-Channel
'Multiplexer .................................................. Section 2
ADC0811 8-Bit Serial I/O AID Converter with 11-Channel
Multiplexer .................................................. Section 2
ADC0816 8-Bit p.P Compatible AID Converter with 16-Channel
Multiplexer ... " .............................................. Section 2
ADC0817 8-Bit p.P Compatible AID Converter with 16-Channel
Multiplexer ....•..................•.......................... Section 2
ADC0819 8-Bit Serial I/O AID Converter with 19-Channel
Multiplexer .................................................. Section 2
ADC0820 8-Bit High Speed p.P Compatible AID Converter with
Track/Hold Function ......................................... Section 2
ADC0831 8-Bit Serial I/O AID Converter with Multiplexer Options .... Section 2
ADC0832 8-Bit Serial I/O AID Converter with Multiplexer Options .... Section 2
ADC0833 8-Bit Serial I/O AID Converter with 4-Channel Multiplexer .. Section 2
ADC0834 8-Bit Serial I/O AID Converter with Multiplexer Options ... ; Section 2
ADC0838 8-Bit Serial I/O AID Converter with Multiplexer Options .... Section 2
ADC0841 8-Bit p.P Compatible AID Converter; .................... Section 2
ADC0844 8-Bit p.P Compatible AID Converter with Multiplexer
Options ............ '.....•.... ; .... " ........................ Section 2
ADC0848 8-Bit p.P Compatible AID Converter with Multiplexer
Options .................................................... Section 2
ADC0851 8-Bit Analog Data Acquisition and Monitoring System ...... Section 1
ADC0852 Multiplexed Comparator with 8-Bit Reference Divider ...... Section 2
ADC0854 Multiplexed Comparator with 8-Bit Reference Divider ...... Section 2
ADC0858 8-Bit Analog Data Acquisition and Monitoring System ...... Section 1
ADC08031 8-Bit High-Speed Serial I/O AlD.Converter with
'
Multiplexer Options, Voltage Reference, and Track/Hold
, Function .................................................... Section 2
ADC08032 8-Bit High-Speed Serial I/O AID Converter with
Multiplexer Options, Voltage Reference, and Track/Hold
Function ........................... '......................... Section 2
ADC08034 8-Bit High-Speed Serial I/O AID Converter with
Multiplexer Options, Voltage Reference, and Track/Hold
Function .................................................... Section 2
ADC08038 8-Bit High-Speed Serial I/O AID Converter with
Multiplexer Options, Voltage Reference, and Track/Hold
Function .......................•... '.............•........... Section 2
ADC08061 500 ns AID Converter with S/H Function and Input
Multiplexer ..................................... ; .. '; '..•...... Section 2
ADC08062 500 ns AID Converter with S/H Function and Input
Multiplexer ................................•................. Section 2

xii

Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
, Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition

Data Acquisition

Data Acquisition

Data Acquisition

Data Acquisition
Data Acquisition
Data Acquisition

Additional Available Linear Devices (Continued)
ADC08131 a-Bit High-Speed Serial I/O AID Converter with
Multiplexer Options, Voltage Reference, and Track/Hold
Function ................................... '................. Section 2
ADC08134 8-Bit High-Speed Serial I/O A/D Converter with
Multiplexer Options, Voltage Reference, and Track/Hold
Function .................................................... Section 2
ADC08138 8-Bit High-Speed Serial 110 AID Converter with
Multiplexer Options, Voltage Reference, and Track/Hold
Function .................................................... Section 2
ADC08161 500 ns AID Converter with S/H Function and 2.5V
Bandgap Reference ......................................... Section 2
ADC08231 8-Bit 2 p.s Serial I/O AID Converter with MUX, Reference,
and Track/Hold ............................................. Section 2
ADC08234 8-Bit 2 p.s Serial I/O AID Converter with MUX, Reference,
and Track/Hold .................•........................... Section 2
ADC08238 a-Bit 2 p.s Serial I/O AID Converter with MUX, Reference,
and Track/Hold ............................................. Section 2
ADC12H030 Self-Calibrating 12-Bit Plus Sign Serial I/O AID
Converter with MUX and Sample/Hold ......................... Section 2
ADC12H032 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converter with MUX and Sample/Hold ....................... , . Section 2
ADC12H034 Self-Calibrating 12-Bit Plus Sign Serial I/O AID
Converter with MUX and Sample/Hold ... ", .... "., ... ", ..... Section 2
ADC12H038 Self-Calibrating 12-Bit Plus Sign Serial I/O AID
Converter with MUX and Sample/Hold ... , .. '.... , .............. Section 2
ADC12L030 3,3V Self-Calibrating 12-Bit Plus Sign Serial I/O AID
Converter with MUX and Sample/Hold ."., .... ", ..... , ....... Section 2
ADC12L032 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O AID
Converter with MUX and Sample/Hold " ....... , ....... , ....... , Section 2
ADC12L034 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O AID
Converter with MUX and Sample/Hold"." .. ,.,.,.,.,.,."", ,Section 2
ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O AID
Converter with MUX and Sample/Hold .,., ..... " ......... , .... Section 2
ADC1 001·1 O-Bit p.P Compatible AID Converter, , , , , . , . , , . , ••. , , . , , Section 2
ADC1005 1O-Bit p.P Compatible AID Converter .................... Section 2
ADC1031 1O-Bit Serial I/O AID Converter with Analog Multiplexer
and Track/Hold Function ..................................... Section 2
ADC1034 1O-Bit Serial I/O AID Converter with Analog Multiplexer
and Track/Hold Function .............................. " ..... Section 2
ADC1038 1O-Bit Serial I/O AID Converter with Analog Multiplexer
and Track/Hold Function ..................... ; .............. ; Section 2
ADC1061 10-Bit High-Speed p.P-Compatible AID Converter with
Track/Hold Function ........................................ ,Section 2
ADC1205 12-Bit Plus Sign p.P Compatible AID Converter ........... Section 2
ADC1225 12-Bit Plus Sign p.P Compatible AID Converter ........... Section 2
.ADC1241 Self-Calibrating 12-Bit Plus Sign p.P-Compatible AID
Converter with Sample/Hold .................................. Section 2
ADC1242 12-Bit Plus Sign Sampling AID Converter ................ Section 2
ADC1251 Self-Calibrating 12-Bit Plus Sign AID Converter-with'
Sample/Hold ......... , .•......................•............ Section 2

xiii

Data Acquisition

Data Acquisition

Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
. Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
,Data Acquisition
Data Acquisition

Additional Available Linear Devices (Continued)
ADC10061 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold .•......•.....•.....•..... ; ...... '.•..•......... Section 2
ADC10062 1O-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold ...................•....... '....... i • • • : • • • • • • • • • Section,2
ADC10064 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold ...•........................................... Section 2
ADC1 0154 10-Bit Plus Sign 4 ,..,S ADC with 4- or 8-Channel MUX.
Track/Hold and Reference ..............•.....•.............. Section 2
ADC1 0158 1O-Bit Plus Sign 4 ,..,S ADC with 4- or 8-Channel MUX,
Track/Hold and Reference ......•............•...•...... ; ..•. Section 2
ADC10461 10-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold .....•..................•...................... Section ,2
ADC10462 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold •.•................... , ......... '....•...' ....... Section 2'
ADC10464 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold ............................•..•....•.......... Section 2
ADC10662 1O·Bit 360 ns AID Converter with Input Multiplexer and
Sample/Hold ........................... " ................... Section 2
ADC10664 1O-Bit 360 ns A/D Converter with Input Multiplexer and
Sample/Hold .....•..............................'•.......... Section 2
ADC10731 10-Bit Plus Sign Serial 110 AID Converter with MUX.
Sample/Hold and Reference .................................. Section 2
ADC10732 10-Bit Plus Sign Serial 110 AID Converter with MUX,
Sample/Hold and Reference .................................. Section 2
ADC10734 1O~ait Plus Sign Serial 110 AID Converter with MUX,
Sample/Hold and Reference .................. , '" ............ Section 2
ADC10738 10-Bit Plus Sign Serial 110 AID Converter with MUX,
Sample/Hold and Reference ........ ; ......................... Section 2
ADC10831 1O-Bit Plus Sign Serial 110 AID Converter with MUX,
Sample/Hold and Reference ...•..........................•... Section 2
ADC10832 1O-Bit Plus Sign Serial 110 AID Converter with MUX,
Sample/Hold and Reference ....... ; ...................•...... Section 2
ADC10834 1O-Bit Plus Sign Serial 110 A/D Converter with MUX,
Sample/Hold and Reference .........•....................•... Section 2
ADC10838 1O-Bit Plus Sign Serial 110 A/D Converter with MUX,
Sample/Hold and Reference .................................. Section 2
ADC12030 Self-Calibrating 12-BitPlus Sign Serial 110 A/D Converter
with MUX and Sample/Hold ................................... Section 2
ADC12032 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter
with MUX and Sample/Hold ...........•..... '.................. Section 2
ADC12034 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter
with MUX and Sample/Hold ................................... Section 2
ADC12038 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter
with MUX and Sample/Hold ................................... Section 2
ADC12062 12-Bit, 1 MHz, 75 mW AID Converter-with Input
Multiplexer and Sample/Hold ..........................•...... Section 2
ADC12130 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter
with MUX and Sample/Hold .........•.....•.....' .........•... ; Section 2
ADC12132 Self-Calibrating 12-Bit Plus Sign Serial 110 AID Converter
with MUX and Sample/Hold ...........................•....... Section 2

xiv

Data Acqllisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
,Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data AcquiSition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
,Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition

Additional Available Linear Devices (Continued)
ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter
with MUX and Sample/Hold ................................... Section 2
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign AID
Converter with Sample/Hold .................................. Section 2
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D
Converter with Sample/Hold .................................. Section 2
ADC12662 12-Bit, 1.5 MHz, 200 mW AI D Converter with Input
Multiplexer and Sample/Hold ................................. Section 2
ADC16071 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converter .. Section 2
ADC16471 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converter .. Section 2
AH0014 Dual DPDT-TILlDTL Compatible MOS Analog Switch ...... Section 8
AH0015 Quad SPST-TILlDTL Compatible MOS Analog Switch ..... Section 8
AH0019 Dual DPST-TIL/DTL Compatible MOS Analog Switch ...... Section 8
AH5010 Monolithic Analog Current Switch ........................ Section 8
AH5011 Monolithic Analog Current Switch ........................ Section 8
AH5012 Monolithic Analog Current Switch ..............•......... Section 8
AH5020C Monolithic Analog Current Switch ....................... Section 8
AN-450 Small Outline (SO) Package Surface Mounting
Methods-Parameters and Their Effect on Product Reliability ..... Section 9
AN-450 Small Outline (SO) Package Surface Mounting
Methods-Parameters and Their Effect on Product Reliability ...•. Section 5
AN-450 Small Outline (SO) Package Surface Mounting
Methods-Parameters and Their Effect on Product Reliability ..... Section 6
Board Mount of Surface Mount Components .•.................... Section 6
Board Mount of Surface Mount Components ...................... Section 5
Board Mount of Surface Mount Components ...................... Section 9
DAC0800 8-Bit 0/ A Converter ................................... Section 3
DAC0801 8-Bit 0/ A Converter ........................•.......... Section 3
DAC0802 a-Bit 0/ A Converter ................................... Section 3
DAC0806 8-Bit D/ A Converter ................................... Section 3
DAC0807 8-Bit 0/ A Converter ................................... Section 3
DAC0808 8-Bit 0/ A Converter ..•................................ Section 3
DAC0830 8-Bit p.P Compatible Double-Buffered D/ A Converter ...... Section 3
DAC0831 8-Bit p.P Compatible Double-Buffered D/ A Converter ...... Section 3
DAC08328-Bit p.P Compatible Double-Buffered 0/ A Converter ...... Section 3
DAC0854 Quad 8-Bit Voltage-Output Serial 0/ A Converter with
. Readback .................................................. Section 3
DAC0890 Dual 8-Bit p.P-Compatible 0/ A Converter ......•......... Section 3
DAC1006 p.P Compatible, Double-Buffered 0/ A Converter ...•...... Section 3
DAC1007 p.P Compatible, Double-Buffered 0/ A Converter .......... Section 3
DAC1008 p.P Compatible, Double-Buffered 0/ A Converter .......... Section 3
DAC1020 10-Bit Binary Multiplying 0/A Converter ................. Section 3
DAC1021 1O-Bit Binary Multiplying 0/ A Converter .......... ; ...... Section 3
DAC1022 1O-Bit Binary Multiplying 0/ A Converter ................. Section 3
DAC1054 Quad 1O-Bit Voltage-Output Serial 0/ A Converter with
Readback .................................................. Section 3
DAC1208 12-Bit p.P Compatible Double-Buffered 0/ A Converter ..... Section 3
DAC1209 12-Bit p.P Compatible Double-Buffered 0/ A Converter ..... Section 3
DAC1210 12-Bit p.P Compatible Double-Buffered 0/ A Converter ..... Section 3
DAC1218 12-Bit Binary Multiplying 0/ A Converter ................. Section 3
DAC1219 12-Bit Binary Multiplying 0/ A Converter ................. Section 3

xv

Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
PowerlCs
Operational Amplifiers
Operational Amplifiers
PowerlCs
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition

Additional Available Linear Devioes(ContinUedl
DAC1220 12-Bit Binary Multiplying 01 A,Converter ............ ' .. :d.~ Section 3
Data Acquisitibn
Data Acquisition
DAC122212-Bit Binary Multiplying 01 A Converter ................. Section 3
DAC1230 12-Bit ,..,p Compatible Double-Buffered 01 A ,Converter: .... Section 3
. Data Acquisition
Data Acquisition
DAC123112-Bit ,..,p Compatible Double-Buffered 01 A Converter ..... Section 3
DAC1232 12-Bit ,..,p Compatible Double;:Buffered 01 A Converter: . : .. Section 3
Data Acquisition
DH0006 Current Driver ......•.................................. Section 5
Operational Amplifiers
DH0034 High Speed Dual Level Translator ...•..•.....•........... Section 5· 'Operational Amplifiers
I3H0035 Pin Diode Driver .... ""~ .•............................... Section 5
Operational Amplifiers
Operational Amplifier.s
Land Pattern Recommendations, ... ; ........., .............:........ Section 6
Land Pattern ,Recommendations :;.,:; ..•... ,c •.•••••••••••••••••••• '. : •• Section 5
. Power ICs
Land Pattern Recommendations.; ......•.............. ,', ........ Sectiorr9
. Data Acquisitibn
LF111 Voltage Comparator ............................. \ ....... Section 3
Operational, Amplifiers
LF147 Wide Bandwidth Quad JFET Input Operational Amplifier.; ..•.. Section 1
Operational Amplifiers
LI1155 Series Monolithic JFET Input Operational Amplifiers .......... Section 1
Operational Amplifiers
LF156 Series Monolithic JFETlnput Operational Amplifiers •..... ; ... Section 1, Operational Amplifiers
LF157 Series Monolithic JFET Input Operational Amplifiers ..... ; ..•. Section 1
Operational Amplifiers
LF19a Monolithic Sample and Hold Circuit ....................... ;'Section 6.
Data Acquisition
LF211 Voltage Comparator ..................................... Section 3
Operational Amplifiers
LF29a Monolithic Sample and Hold Circuit .. ; ....................c. Section 6
Data AcqUisition
LF311 Voltage Comparator ..................................... Section 3
Operational Amplifiers
Operational Amplifiers
LF347 Wide Bandwidth Quad JFET Input Operational Amplifier •..... Section 1
LF351 Wide Bandwidth JFET Input Operational Amplifier ........... Section 1
Operational Amplifiers
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier ....... Section 1
Operational Amplifiers
LF39a'Monolithic Sample and Hold Circuit ......................•.. Section 6.', .
Data Acquisition
LF411 l,.ow Offset, Low Drift JFET Input Operational Amplifier .; ..•.. Section 1 ,Operational Amplifiers
Operational Amplifiers
LF412.Low Offset, Low Drift Dual JFET Operational Amplifier ...•.... Section 1
LF441 Low Power JFET InputOperational Amplifier ................ Section 1 .Operational Amplifiers
LF442 Dual Low Power JFET Input Operational Amplifier ........... Section 1
Operational Amplifiers
LF444. Quad Low Power JFET Input Operational Amplifier ........... Section 1
Operational Amplifiers
LF451 Wide"Bandwidth JFET Input Operational Amplifier ........... Section 1
Operational Amplifiers
Operational Amplifiets
LF453 Wrde-Bandwidth Dual JFET Input Operational Amplifier ....... Section 1
LF11201 Quad SPST JFET Analog Switch ........................ Section a
Data AcqUisition
Data Acquisition
LF11202 Quad SPST JFET Analog Switch ............ '....• , • ,...... Secti.on a
LF11331 Quad SPST JFET Analog Switch, •...•.•....•............ Section a
Data Acquisition
LF11332 QuadSPST JFET Analog Switch .....•. : ................ Section a
Data Aoquisition
LF11333 Quad SPST JFET Analog Switch ... ; ............... ; .... Section a
Data Acquisition
LF13006 Digital Gain Set ....................................... Section 6
Data Acquisition
LF13007 Digital Gain Set .......................... !. ...... : ..... Section 6
Data Acquisition
LF13201 Quad SPST JFET Analog Switch ...•..................... Section a
Data Acquisition
LF13202 Quad SPST JFET Analog Switch ...........,.' ..... '.•.•.. : Section a
Data Acquisitioh
LF13331 Quad SPST JFET Analog Switch .... : •...•.............. Section a
Data.Acquisition
,,' Data Acquisition
LF13332 Quad SPST JFET Analog Switch ......................... Section a
Data Acquisition
LF13333 Quad SPSTJFET Analog Switch ..............••'; ...•... Section a .
LF,1350a a-Channel Analog Multiplexer ..............••....•. ; .... Section a
Data Acquisition
LF13509 4-Channel Differential Analog Multiplexer .......•... ; ..... Section a .
Data Acquisition
LH0002 Buffer ................................................ Section 2, Operational Amplifiers
LH0003 Wide Bandwidth Operational Amplifier ..................... Section 1
Operational Amplifiers
L.H0004 High Voltage Operational Amplifier ........ " .......•...... Section. 1 " ,Operational Amplifiers
LH002.1 .1;0 Amp Power Operational Amplifier .....•............... Section 1·
Operational 'Amplifiers
LH0024 High Slew Rate Operational Amplifier ..................... Section 1 . Operational Amplifiers
LHOO32 Ultra Fast FET-lnputOperational Amplifier ..•............. ;Sec:tion 1
Operational Amplifiers

xvi

Additional Available Linear Devices (Continued)
LH0033 Fast and Ultra Fast Buffers .............................. Section 2
LH0041 0.2 Amp Power Operational Amplifier ....................• Section 1
LH0042 Low Cost FET Operational Amplifier ...................... Section 1
LH0063 Fast and Ultra Fast Buffers .............................. Section 2
LH0070 Series BCD Buffered Reference .......................... Section 4
LH0071 Series Precision Buffered Reference ...................... Section 4
LH0094 Multifunction Converter ................................. Section 5
LH0101 Power Operational Amplifier ............................. Section 1
LH1605 5 Amp, High Efficiency SWitching Regulator ................ Section 3
LH2111 Dual Voltage Comparator ............................... Section 3
LH2311 Dual Voltage Comparator ............................... Section 3
LH4001 Wideband Current Buffer; ............................... Section 2
LH4002 Wideband Video Buffer .............. " .................. Section 2 .-LM10 Operational Amplifier and Voltage Reference ........•....... Section 1
LM12 80W Operational Amplifier ...............•. " .... : ......... Section 4
LM 12H454 12-Bit + Sign Data Acquisition System with
Self-Calibration .............................................. Section 1
LM 12H458 12-Bit + Sign Data Acquisition System with
Self.Calibration .........•.................................... Section 1
LM12L438 12-Bit + Sign Data Acquisition System with Serial 110
and Self-Calibration .......... ; ............................... Section 1
LM12L45412-Bit + Sign Data Acquisition System with
- Self-Calibration ........ ; ..................................... Section 1
LM12L45812-Bit + Sign Data Acquisition System with
Self-Calibration .........................................•.... Section 1
LM34 Precision Fahrenheit Temperature Sensor ................... Section 5
LM35 Precision Centigrade Temperature Sensor ................... Section 5
LM45 SOT-23 Precision Centigrade Temperature Sensor ........... Section 5
LM50 Sintlle Supply Precision Centigrade Temperature Sensor ...... Section 5
LM78LXX Series 3-Terminal Positive Regulators ....... ; .. -......... Section 1 '
LM78M~X Series 3-Terminal Positive Regulator ................... Section 1
LM7BS40 Universal Switching Regulator Subsystem ............... Section 3
LM78XX Series Voltage Regulators .............................. Section 1
LM79LXXAC Series 3-Terminal Negative Regulator ................ Section 1
LM79MXX Series 3-Terminal Negative Regulators ................. Section 1
LM79XX Series 3-Terminal Negative Regulators ................... Sectton 1
LM 101 A Operational Amplifier ... ; ............................... Section 1
LM102 Voltage Follower ........................................ Section 2
LM105 Voltage Regulator ....................................... Section 1
LM106 Voltage Comparator .......•............................. Section 3
LM107 Operational Amplifier .................................... Section 1
LM108 Operational Amplifier .................................... Section 1
LM109 5-Volt Regulator ........ , .•............................. Section 1
LM110 Voltage Follower ........................................ Section 2
LM111 Voltage Comparator .•.....•............................. Section 3
LM 113 Reference Diode ................................ '........ Section 4
LMl-17 3-Terminal Adjustable Regulator ................... -. ...... Section 1
LM 117HV 3-Terminal Adjustable Regulator ....................... Section 1
LM 118 Operational Amplifier ... " .....•......................... Section 1
LM119 High Speed Dual Comparator ............................. Section 3
LM 120 Series 3-Terminal Negative Regulator ....................... Section 1

xvii

Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Data Acquisition
Data Acquisition
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Power ICs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
Power ICs
PowerlCs
Operational Amplifiers
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
Operational Amplifiers
_Operational Amplifiers
Data Acquisition
PowerlCs
PowerlCs
Operational Amplifiers
Operational-Amplifiers
PowerlCs

Additional Available linear Devices'{continUed)
LM123 3-Amp, 5-Volt Positive Regulator •.......•................. SeCtion 1
LM 124 Low Power Quad Operational Amplifier .•................. , Section 1 '
LM125 Dual Voltage Regulator .. ; .....•......•.................. Section 1
LM129 Precision Reference .. ; .........•........................ Section 4
LM131 Precision Voltage-to-Frequency Converter ..•....•....•..... Section 2
LM133 3-Amp Adjustable Negative Regulator ..........•..•..... , .Section 1
LM 134 3-Terminal Adjustable Current Source ..................... Section 4
LM134 3-Terminal Adjustable Current Source .......•.........•... Section 5
LM135 Precision Temperature Sensor ..•..•......................,Section 5
LM136-2.5V Reference Diode ................................... Section 4
LM136-5.0V Reference Diode ................................... Section 4
LM137 3-Terminal Adjustable Negative Regulator ..•............... Section 1
LM137HV 3-Terminal Adjustable Negative Regulator (High Voltage) .. Section 1
LM138 5-Amp Adjustable Regulator ....•..............•..•...... ,Section 1
LM139 Low Power Low Offset Voltage Quad Comparator ........... Section 3
LM140 Series 3-Terminal Positive Regulator ....•.•............... Section 1
LM140L Series 3-Terminal Positive Regulator ...............•..... Section 1
LM143 High Voltage Operational Amplifier ........................ Section 1
LM145 Negative 3-Amp Regulator ............................... Section 1
\ LM146 Programmable Quad Operational Amplifier ..•...•.......... Section 1
LM148 Quad 741 Operational Amplifier ................•.•..•..... Section 1
LM149 Wide Band Decompensated (Av(MIN) = 5) ........... '..... Section 1
LM150 3-Amp Adjustable Regulator ......................•....... Section 1
LM 158 Low Power Dual Operational Amplifier .••.............•.... Section 1
LM160 High Speed Differential Comparator .....................•. Section 3
LM161 High Speed Differential Comparator ....................... Section 3
LM169 Precision Voltage Reference ..•......................•... Section 4
LM185 Adjustable Micropower Voltage Reference ............... :. Section 4
LM185-1.2 Micropower Voltage Reference Diode ..•.....•......... Section 4
LM185-2.5 Micropower Voltage Reference Diode •...........•....• Section 4
LM193 Low Power Low Offset Voltage Dual Comparator ............ Section 3
LM194 Supermatch Pair ........................................ Section 5
LM195 Ultra Reliable Power Transistor ......•............•....... Section 5
LM199 Precision Reference ..................................... Section 4
LM201 A Operational Amplifier ................................... Section 1
LM205 Voltage Regulator ...........•..................•... " .... Section 1
LM207 Operational Amplifier .................................... Section 1
LM208 Operational Amplifier ..' .................................. Section 1
LM210 Voltage Follower ...... : ........•...•.................... Section 2
LM211 Voltage Comparator ................•...•.•.............• Section 3
LM218 Operational Amplifier .... : •.....•........................ Section 1
LM219 High Speed Dual Comparator .....•.•...............•..•.. Section 3
LM221 Precision Preamplifier ......•............... , ., ........•• Section 1
LM224 LoW Power Quad Operational Amplifier .......•.....•...... Section 1
LM231 Precision Voltage-to-Frequency Converter ........•.•.•..... Section 2
LM234 3-Terminal Adjustable Current Source ..................... Section 4
LM234 3-Terminal Adjustable Current Source ..................... Section 5
LM235 Precision Temperature Sensor ..•..•..................... ; Section 5
LM236-2.SV Reference Diode .• , ................................ Section 4
LM236-5.0V Reference Diode ................................... Section 4
LM239 Low Power Low Offset Voltage Quad Comparator ........... Section 3

xviii

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Operational Amplifiers
PowerlCs
Data Acquisition
Data Acquisition
, PowerlCs
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
PowerlCs
Power ICs
Power ICs
Operational Amplifiers
PowerlCs
\ PowerlCs
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
Operatiol1al Amplifiers
Operational Amplifiers
Operational Amplifiers
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Operational Amplifiers
Operational Aniplifiers
Operational Amplifiers
Data Acquisition
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Operational Amplifiers

Additional Available Linear Devices (Continued)
LM246 Programmable Quad Operational Amplifier ................. Section 1
LM248 Quad 741 Operational Amplifier .......•................... Section 1
LM258 Low Power Dual Operational Amplifier ..................... Section 1
LM261 High Speed Differential Comparator ....................... Section 3
LM285 Adjustable Micropower Voltage Reference ................. Section 4
LM285-1.2 Micropower Voltage Reference Diode .................. Section 4
LM285-2.5 Micropower Voltage Reference Diode .................. Section 4
LM293 Low Power Low Offset Voltage Dual Comparator ............ Section 3
LM299 Precision Reference ..................................... Section 4
LM301A Operational Amplifier ................................... Section 1
LM302 Voltage Follower ........................................ Section 2
LM305 Voltage Regulator ................•...................... Section 1
LM306 Voltage Comparator ..................................... Section 3
LM307 Operational Amplifier .................................... Section 1
LM308 Operational Amplifier .................................... Section 1
LM309 5-Volt Regulator .......................•................ Section 1
LM310 Voltage Follower ..........•............................. Section 2
LM311 Voltage Comparator .............................. '" ...• Section 3
LM313 Reference Diode ........................................ Section 4
LM317 3-Terminal Adjustable Regulator .......................... Section 1
LM317HV 3-Terminal Adjustable Regulator .....•.......•......... Section 1
LM317L 3-Terminal Adjustable Regulator ......•.....•............ Section 1
LM318 Operational Amplifier .................................... Section 1
LM319 High Speed Dual Comparator ............•................ Section 3
LM320 Series 3-Terminal Negative Regulator ...................... Section 1
LM320L Series 3-Terminal Negative Regulator .........•.......... Section 1
LM321 Precision Preamplifier ..........................•........ Section 1
LM323 3-Amp, 5-Volt Positive Regulator .......................... Section 1
LM324 Low Power Quad Operational Amplifier ...•................ Section 1
LM325 Dual Voltage Regulator .........•........................ Section 1
LM329 Precision Reference ..................................... Section 4
LM330 3-Terminal Positive Regulator .•....................•...... Section 2
LM331 Precision Voltage-to-Frequency Converter .................. Section 2
LM333 3-Amp Adjustable Negative Regulator .........•.....•..... Section 1
LM334 3-Terminal Adjustable Current Source ..................... Section 4
LM334 3-Terminal Adjustable Current Source ..................... Section 5
LM335 Precision Temperature Sensor ............................ Section 5
LM336-2.5V Reference Diode ................................... Section 4
LM336-5.0V Reference Diode ..•...........•.•....•............. Section 4
LM337 3-Terminal Adjustable Negative Regulator .................. Section 1
LM337HV 3-Terminal Adjustable Negative Regulator (High Voltage) .. Section 1
LM337L 3-Terminal Adjustable Regulator ......................... Section 1
LM338 5-Amp Adjustable Regulator .............................. Section 1
LM339 Low Power Low Offset Voltage Quad Comparator ........... Section 3
LM340 Series 3-Terminal Positive Regulator ...................... Section 1
LM340L Series 3-Terminal Positive Regulator ..................... Section 1
LM341 Series 3-Terminal Positive Regulator ..•................... Section 1
LM343 High Voltage Operational Amplifier ........................ Section 1
LM345 Negative 3-Amp Regulator ............................... Section 1
LM346 Programmable Quad Operational Amplifier ................• Section 1
LM348 Quad 741 Operational Amplifier •......................•... Section 1

xix

Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Data Acquisition
Data Acquisition
Data Acquisition
Operational Amplifiers
Data Acquisition
Operational Amplifiers
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Data Acquisition
PowerlCs
Power ICs
Power ICs
Operational Amplifiers
Operational Amplifiers
Power ICs
Power ICs
Operational Amplifiers
PowerlCs
Operational Amplifiers
Power ICs
Data Acquisition
Power ICs
Data Acquisition
• PowerlCs
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Power ICs
PowerlCs
Power ICs
PowerlCs
Operational Amplifiers
PowerlCs
PowerlCs
Power ICs
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers

Additional Avallable Linear 'Devices (Continued)
LM349 Wide Band Decompensated (Av(MIN) = 5) ...•'.•. ,..'; .....• Section 1
Operational Amplifiers
LM36o. 3-Amp Adjustable Regulator ....•............•............ Section 1
PowerlCs
LM358 LowPower Dual Operational Amplifier .................. ; .. Section 1 " Operational Amplifiers
LM359 Dual, High Speed, Programmable Current Mode (Norton)
Amplifier ............... '..........................• , .... ;: ... " Section 1
Operational Amplifiers
LM360 High Speed Differential Comparator ............... ';., ..... '•. Section 3
Operational Amplifiers
LM361 High Speed Differential Comparator ........... ,: ; ......... Section 3
Operational Amplifiers
LM368-2.5 Precision Voltage Reference .......... ; .. ; ..• ; ... '..... Section 4
Data Acquisition
Data Acquisition
LM368-5.o. ,Precision Voltage Reference •......................•.. Section 4,
LM368-1o. Precision Voltage Reference ........................... Section 4,
' ,Data Acquisition
Data AcquiSition
LM369 Precision Voltage Reference ................•....•....... Section 4
LM376 Voltage Regulator ....................................... Section 1 "
Power,ICs
LM385 Adjustable Micropower Voltage Reference ................. Section 4
Data Acquisition
", Data AcquiSition
LM385-1.2 Micropower Voltage,Reference Diode .................. Section 4
LM385-2.5 Micropower Voltage Reference Diode .................. Section 4
Data,Acql:lisition
LM392 Low Power Operational Amplifier /Voltage Comparator ....... Section 1 ',Operational Amplifiers
LM39a Low Power low Offset Voltage Dual Comparator ............ Section 3
Operational Amplifiers
LM394 SupermatchPair .' •.•.................•.................. Section 5
Operational Amplifiers
LM395 Ultra Reliable Power Transistor ........................... Section 5
Operational Amplifiers
LM399 Precision Reference. " ..•............................. : .. Section 4
Data Acquisition
lM431 A Adjustable Precision Zener Shunt Regulator ..........
Section 3 ,
''Power ICs
LM611 Operational Amplifier and Adjustable Reference ........ ;' .. '.. Section 1,' ,Operational,Amplifiers
LM612 Dual-Channel Comparator and Reference .................. Section 3 , ,Operational ,Amplifiers
LM613 Dual Operational Amplifier, Dual Comparator, and Adjustable
,Operational Amplifiers
Reference ................................................... Section 3
LM613 Dual Operational Amplifier, Dual Comparator, and Adjustable
Reference .................. ; ..•............................ Section' 1 '" Operational Amplifiers
LM614 Quad Operational Amplifier and Adjustable Reference ....... Section 1
Operational Amplifiers
LM615 Quad Comparator and Adjustable Reference ......... ; ...•,. SectionS
Operational Amplifiers
LM628 Precision Motion Controller ............................... Section 4
PowerlCs
LM629 Precision Motion Controller ..•.................•.......... Section 4
Power ICs
LM675,Power Operational Amplifier ................•............. Section 1.; Operational Amplifiers
LM7o.9 Operational Amplifier .'.1. •••.•.••..•.•.•.•...•; .•...•..•.. ' .Section 1
Operational,Amplifiers
LM71 0. Voltage Comparator .... ':......................... ',' ...
Section 3, Operational Amplifiers
LM723 Voltage Regulator ....................................... Section 1
Power ICs
,LM725 Operational Amplifier .........•.......................... Section 1 ,Operational Amplifiers
LM741 Operational Amplifier ...•............•................... Section .1 .. Operational Amplifiers
LM747 Dual Operational Amplifier ..........•..................... Section 1
Operational Amplifiers
LM748 Operational Amplifier .................................•.. Section 1 ,OperationalAmplifiers
LM759 Power Operational Amplifier ...............•... '... ;'. : ..... Section 1
Operational Amplifiers
.LM760 High Speed Differential Comp~rator ......• ; ..•........•.•. '. Section 3
Operational Amplifiers
Qp!3rational Amplifiers
LM1458 Dual Operational Amplifier ..................•........... Section 1
LM1558 Dual Operational Amplifier .............................. Section 1, Operational Amplifiers
LM15.75 SIMP-LE SWITCHER 1A Step-Down Voltage Regulator ...... Section 3
Power les
LM1575HV SIMPLE SWITCHER 1A Step-Down Voltage Regulator ... Section 3
Power ICs
LM1577 SIMPLE SWITCHER Step-Up Voltage Regulator ..... ; ..... Section 3,
Power ICs
LM1578A Switching Regulator ...........•......•................ Section 3 ,
Power ICs
LM1801 Battery Operated Power Comparator ........•......•... ".Section ,3 :' Operational Amplitiers
LM1875 20. Watt Power Audio Amplifier •.......................... Section ,1
Operational Amplifiers
Operational Amplifiers
liM 1877 Dual Power Audio Amplifier .................•• ', .........• Section ,1
LM18~6 DualPower Audio Amplifier .............•..............' •. section 1
Operational Amplifiers
0, • •

,

•

d.

xx

Additional Available Linear Devices (Continued)
LM2524D Regulating Pulse Width Modulator ...................... Section 3
LM2574 SIMPLE SWITCHER 0.5A Step-Down Voltage Regulator .... Section 3
LM2574HV SIMPLE SWITCHER 0.5A Step-Down Voltage
Regulator ........................•...... , .................... Section 3
LM2575 SIMPLE SWITCHER 1A Step-Down Voltage Regulator ...... Section 3
LM2575HV SIMPLE SWITCHER 1A Step-Down Voltage Regulator ... Section 3
LM2576 SIMPLE SWITCHER 3A Step-Down Voltage Regulator ...... Section 3
LM2576HV SIMPLE SWITCHER 3A Step-Down Voltage Regulator ... Section 3
LM2577 SIMPLE SWITCHER Step-Up Voltage Regulator ........... Section 3
LM2578A Switching Regulator ................................... Section 3
LM2587 SIMPLE SWITCHER 5A Flyback Regulator ................ Section 3
LM2877 Dual 4 Watt Power Audio Amplifier ....................... Section 1
LM2878 Dual 5 Watt Power Audio Amplifier ....................... Section 1
LM2879 Dual 8 Watt Audio Amplifier ............................. Section 1
LM2896 Dual Power Audio Amplifier .............................. Section 1
LM2900 Quad Amplifier ......................................... Section 1
LM2901 Low Power Low Offset Voltage Quad Comparator .......... Section 3
LM2902 Low Power Quad Operational Amplifier ................... Section 1
LM2903 Low Power Low Offset Voltage Dual Comparator ........... Section 3
LM2904 Low Power Dual Operational Amplifier .................... Section 1
LM2924 Low Power Operational AmplifierlVoltage Comparator ...... Section 1
LM2925 Low Dropout Regulator with Delayed Reset ............... Section 2
LM2926 Low Dropout Regulator with Delayed Reset ............... Section 2
LM2927 Low Dropout Regulator with Delayed Reset ............... Section 2
LM2930 3-Terminal Positive Regulator ........................... Section 2
LM2931 Series Low Dropout Regulators .......................... Section 2
LM2935 Low Dropout Dual Regulator ............................. Section 2
LM2936 Ultra-Low Quiescent Current 5V Regulator ................ Section 2
LM2937 500 rnA Low Dropout Regulator .......................... Section 2
LM2940/LM2940C 1A Low Dropout Regulators ................... Section 2
LM2941 ILM2941 C 1A Low Dropout Adjustable Regulators .......... Section 2
LM2984 Microprocessor Power Supply System .................... Section 2
LM2990 Negative Low Dropout Regulator ......................... Section 2
LM2991 Negative Low Dropout Adjustable Regulator ............... Section 2
LM3001 Primary-Side PWM Driver ............................... Section 3
LM3045 Transistor Array ........................................ Section 5
LM3045 Transistor Array ........................................ Section 1
LM3046 Transistor Array ........................................ Section 5
LM3046 Transistor Array ........ ' ............................... Section 1
LM3080 Operational Transconductance Amplifier .................. Section 1
LM3086 Transistor Array ........................................ Section 1
LM3086 Transistor Array ........................................ Section 5
LM3101 Secondary-Side PWM Controller ......................... Section 3
LM3146 High Voltage Transistor Array ............................ Section 5
LM3301 Quad Amplifier ......................................... Section 1
LM3302 Low Power Low Offset Voltage Quad Comparator .......... Section 3
LM3303 Quad Operational Amplifier .............................. Section 1
LM3403 Quad Operational Amplifier .............................. Section 1
LM3411 Precision Secondary RegulatorIDriver .........•.......... Section 3
LM3420-4.2, -8.4. -12.6 Lithium-Ion Battery Charge Controller ....... Section 2.
LM3524D Regulating Pulse Width Modulator ...................... Section 3

xxi

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PowerlCs
PowerlCs
Power ICs
PowerlCs
Power ICs
PowerlCs
PowerlCs
Power ICs
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
PowerlCs
PowerlCs
PowerlCs
Power ICs
Power ICs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
Power ICs
Power ICs
PowerlCs
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
PowerlCs
PowerlCs
PowerlCs

Additional Available Linear Devices(continUed)
LM3578A Switching Regulator ................................... Section 3
Power ICs
LM3875 High Performance 40 Watt Audio Power Amplifier .......... Section 1 . Operational Amplifiers
LM3900 Quad Amplifier ......................................... Section 1
Operational Amplifiers
LM3940 1A Low Dropout Regulator for 5V to 3.3V Conversion ....... Section 2
PowerlCs
LM3999 Precision Reference ... , ..........................-...... Section 4
Data Acquisition
LM4040 Precision Micropower Shunt Voltage Reference ............ Section 4
Data Acquisition
Data Acquisition
LM4041. Precision Micropower Shunt Voltage Reference ............ Section 4
LM4250 Programmable Operational Amplifier; .............•...... Section 1 .Operational Amplifiers
LM4431 Micropower Shunt Voltage Reference .................... Section 4
Data Acquisition
Operational AmpJifiers
LM61 04 Quad Gray Scale Current Feedback Amplifier .............. Section 1
Operational Amplifiers
LM61 04 Quad Gray Scale Current Feedback Amplifier .............. Section 4
LM6118 Fast Settling Dual Operational Amplifier ............ , ...... Section 1
Operational Amplifiers
LM6121 High Speed Buffer •................•................... Section 2
Operational Amplifiers
LM6125 High Speed Buffer ........... , ......................... Section 2
Operational Amplifiers
LM6132 Dual High Speed/Low Power 7 MHz Rail-to-RailIlO
Operational Amplifier ......................................... Section 1
Operational Amplifiers
LM6134 Quad High Speed/Low Power 7 MHz Rail-to-Raill/O
Operational Amplifier •.....................................•. Section 1
Operational Amplifiers
LM6142 Dual High Speed/Low Power 17 MHz Rail-to-Rail
Input-Output Operational Amplifier.............•........ ~ ....... Section 1
Operational Amplifiers
LM6144 Quad High Speed/Low Power 17 MHz Rail-to-Rail
Input-Output Operational Amplifier ............................. Section l'
Operational Amplifiers
LM6152 Dual High Speed/Low Power 45 MHz Rail-to-Rail
Input-Output Operational Amplifier ............................. Section 1
Operational Amplifiers
LM6154 Quad High Speed/Low Power 45 MHz Rail-to-Rail
Input-Output Operational Amplifier ............................. Section 1
Operational Amplifiers
LM6161 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
Operational Amplifiers
LM6162 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
LM6164 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
LM6165 High Speed Operational Amplifier ........................ Section 1
LM6171 Voltage Feedback Low Distortion Low Power Operational
Operational Amplifiers
Amplifier .................................................. ~. Section 1
LM6181 100 mA, 100 MHz Current Feedback Amplifier ............. Section 1
Operational Amplifiers
LM6182 Dual 100 mA Output, 100 MHz Dual Current Feedback
Operational Amplifiers
Amplifier .................................................... Section 1
LM6218 Fast Settling Dual Operational Amplifier ................... Section 1
Operational Amplifiers
LM6221 High Speed Buffer ..................................... Section 2
Operational Amplifiers
Operational Amplifiers
LM6225 High Speed' Buffer ..................................... Section 2
Operational Amplifiers
LM6261 High Speed Operational Amplifier ........................ Section 1
LM6262 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
Operational Amplifiers
LM6264 High Speed Operational Amplifier ........................ Section 1
LM6265 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
Operational Amplifiers
LM6313 High Speed, High. Power Operational Amplifier ............. Section 1
LM6321 High Speed Buffer ..................................... Section 2
Operational Amplifiers
LM6325 High Speed Buffer ..................................... Section 2
Operational Amplifiers
Operational Amplifiers
LM6361 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
LM6362 High Speed Operational Amplifier ........................ Sec~ion 1
LM6364 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
LM6365 High Speed Operational Amplifier ........................ Section 1
Operational Amplifiers
Operational Amplifiers
LM6511 180 ns 3V Comparator. .................................. Section 3

xxii

Additional Available Linear Devices (Continued)
LM7121 Tiny Very High Speed Low Power Voltage Feedback
Amplifier ...................... '.............................. Section 1
LM7131 Tiny High Speed Single Supply Operational Amplifier ....... Section 1
LM7171 Very High Speed High Output Current Voltage Feedback
Amplifier .................................................... Section 1
LM7800C Series 3-Terminal Positive Regulator .................... Section 1
LM8305 STN LCD Display Bias Voltage Source .................... Section 4
LM9140 Precision Micropower Shunt Voltage Reference ............ Section 4
LM12434 12-Bit + Sign Data Acquisition System with Serial 1/0 and
Self-Calibration .............................................. Section 1
LM12454 12-Bit + Sign Data Acquisition System with
Self-Calibration .............................................. Section 1
LM12458 12-Bit + Sign Data Acquisition System with
Self-Calibration .............................................. Section 1
LM 13600 Dual Operational Transconductance Amplifier with
Linearizing Diodes and Buffers ................................ Section 1
LM13700 Dual Operational Transconductance Amplifier with
Linearizing Diodes and Buffers ................................ Section 1
LM 18293 Four Channel Push-Pull Driver .......................... Section 4
LM77000 Power Operational Amplifier ............................ Section 1
LMC660 CMOS Quad Operational Amplifier ....................... Section 1
LMC662 CMOS Dual Operational Amplifier ........................ Section 1
LMC6001 Ultra Ultra-Low Input Current Amplifier ................... Section 1
LMC6008 8 Channel Buffer ..................................... Section 4
LMC6022 Low Power CMOS Dual Operational Amplifier ............ Section 1
LMC6024 Low Power CMOS Quad Operational Amplifier ............ Section 1
LMC6032 CMOS Dual Operational Amplifier ....................... Section 1
LMC6034 CMOS Quad Operational Amplifier ...................... Section 1
LMC6041 CMOS Single Micropower Operational Amplifier .......... Section 1
LMC6042 CMOS Dual Micropower Operational Amplifier ............ Section 1
LMC6044 CMOS Quad Micropower Operational Amplifier ........... Section 1
LMC6061 Precision CMOS Single Micropower Operational Amplifier .. Section 1
LMC6062 Precision CMOS Dual Micropower Operational Amplifier ... Section 1
LMC6064 Precision CMOS Quad Micropower Operational Amplifier .. Section 1
LMC6081 Precision CMOS Single Operational Amplifier ............ Section 1
LMC6082 Precision CMOS Dual Operational Amplifier .............. Section 1
LMC6084 Precision CMOS Quad Operational Amplifier ............. Section 1
LMC6462 Dual Micropower, Rail-to-Raillnput and Output CMOS
Operational Amplifier ......................................... Section 1
LMC6464 Quad Micropower, Rail-to-Raillnput and Output CMOS
Operational Amplifier ......................................... Section 1
LMC6482 CMOS Dual Rail-to-Raillnput and Output Operational
Amplifier ............................................•....... Section 1
LMC6484 CMOS Quad Rail-to-Raillnput and Output Operational
Amplifier ..................................... , .............. Section 1
LMC6492 Dual CMOS Rail-to-Raillnput and Output Operational
Amplifier .................................................... Section 1
LMC6494 Quad CMOS Rail-to-Raillnput and Output Operational
Amplifier .................................................... Section 1
LMC6572 Dual Low Voltage (3V) Operational Amplifier ............. Section 1
LMC6574 Quad Low Voltage (2.7V) Operational Amplifier ........... Section 1

xxiii

Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Operational Amplifiers
Operational Amplifiers
Power ICs
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
. Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers

Additional A vaiiableLinear Devices (Continued)
LMC6582 Dual Low Voltage, Rail-to-Raillnput and Output CMOS
Operational Amplifier ..•.....•........................•....... Section 1
Operational Amplifiers
LMC6584 Quad Low Voltage, Rail-to-Raillnput and Output CMOS '
Operational Amplifier .................. ; ...................... Section 1
Operational Amplifiers
LMC6681 Single Low Voltage, Rail-to-Raillnput and Output CMOS
Amplifier with Powerdown ...•~ ................................ Section 1
Operational Amplifiers
LMC6682 Dual LowVoltage, Rail-to-Raillnput and Output CMOS "
Amplifier with Powerdown, ... '................. , ............... Section 1
Operational Amplifiers
LMC6684 Quad Low Voltage, Rail-to-Raillnput and Output CMOS, .
Operational Amplifiers
Amplifier with Powerdown ... " ................................ Section 1
LMC6762 Dual Micropower, Rail-to-Raillnput and Output CMOS
, Comparator .............................•................... Section 3
Operational Amplifiers
LMC6764 Quad Micropower, Rail-to-Raillnput and Output CMOS
Comparator ...................................•............. Section 3
Operational Amplifiers
LMC6772 Dual Micropower Rail-to-Raillnput and Open Drain Output
CMOS Comparator .......................................... Section 3
Operational Amplifiers
LMC6774 Quad Micropower Rail-to-Raillnput and Open Drain Output
CMOS Comparator ..... ~ .................................... Section 3
Operational Amplifiers
LMC7101 Tiny Low Power Operational Amplifier with Rail-to-Rail
Input and Output ........... ; .......•........................'. Section ,1
Operational Amplifiers
LMC7111 Tiny,CMOS Operational Amplifier with Rail-to-Raillnput
Operational Amplifiers
and Output ................................................. Section' 1
Operational Amplifiers
LMC7211 Tiny CMOS Comparator with Rail,to-Raillnput ............ Section 3
LMC7221 Tiny CMOS Comparator with Rail-to-Raillnput and Open
Drain Output .. ; ........ ; ............................... ; .... Section 3
Operational Amplifiers
,: Power les
LMC7660 Switched Capacitor Voltage Converter ...... ~ ......... ; .Section 3
LMD18200 3A, 55V H-Bridge .................................... Section 4
PowerlCs
LMD18201 3A, 55V H-Bridge .................................... Section 4
PowerlCs
LMD18245 3A, 55V DMOS Full-Bridge Motor Driver.'............... Section 4
PowerlCs
LMF40 High,Performance 4th-Order Switched Capacitor Butterworth
Low-Pass Filter ........ ,' ..................................... Section 7
Data Acquisition
LMF60 High Performance 6th"Order Switched, Capacitor Butterworth·
Low-Pass Filter.·., ; ....... '.............. ;., ... i,.; ;'.; .......... Section 7
, Data Acquisition
LMF90 4th-Order ElliptiC Notch Filter ...................•.... , .... Section 7
Data Acquisition
LMFtOO High Performance Dual Switched Capacitor Filter .......... Section 7
Data AcqUisition
Data Acquisition
LMF380 Triple One-Third Octave Switched Capacitor Active Filter •.. Section 7
LP311 Voltage,Comparator ... ; ................................. Section 3
Operational Amplifiers
LP339 Ultra-Low Power Quad Comparator .........•.............. Section 3 . Operational Amplifiers
LP395 Ultra Reliable Power Transistor ............................ Section 5
Operational Amplifiers
LP29501 A-XX Series of Adjustable Micropower Voltage Regulators .. Section 2
PowerlCs
LP2951 I A-XX Series. of Adjustable Micropower Voltage Regulators .. Section 2
PoweflCs
LP2952 Adjustable Micropower Low-Dropout Voltage Regulator ..... Section 2
PowerlCs
LP2953 Adjustable Micropower Low-Dropout Voltage Regulator ..... Section. 2
PowerlCs
LP2954 5V Micropower Low-Dropout Voltage Regulator ............ Section 2
PowerlCs
LP29/:i6 Dual Micropower Low-Dropout Voltage Regulator ........... Section 2
PowerlCs
LP2957 5V Low-Dropout Regulator for IA-P Applications ...........•. Section 2
PowerlCs
LP2980 Micropower SOT, 50 rnA Ultra Low-Dropout Regulator ...... Section 2
PowerlCs
LPC660 Low Power CMOS Quad Operational Amplifier' ........ ; .... Section 1, , Operational Amplifiers
LPC661 Low Power CMOS Operational Amplifier .................. Section 1
Operational Amplifiers
Operational Amplifiers
LPC662 Low Power CMOS Dual Operational Amplifier. , ............ Section 1
Data Acquisition
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter ...... SectiOn 7

xxiv

Additional Available Linear Devices (Continued)
MF5 Universal Monolithic Switched Capacitor Filter ................ Section 7
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter ...... Section 7
MF8 4th Order Switched Capacitor Bandpass Filter ................ Section 7
MF10 Universal Monolithic Dual Switched Capacitor Filter ........... Section 7
OP07 Low Offset, Low Drift Operational Amplifier .................. Section 1
Packing Considerations (Methods, Materials and Recycling) ......... Section 5
Packing Considerations (Methods, Materials and Recycling) ......... Section 6
Packing Considerations (Methods, Materials and Recycling) ......... Section 9
Recommended Soldering Profiles-Surface Mount ................. Section 9
Recommended Soldering Profiles-Surface Mount ................. Section 6
Recommended Soldering Profiles-Surface Mount. ................ Section 5
TL081 Wide Bandwidth JFET Input Operational Amplifier ........... Section 1
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier ....... Section 1

xxv

Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Operational Amplifiers
PowerlCs
Operational Amplifiers
Data Acquisition
Data Acquisition
Operational Amplifiers
PowerlCs
Operational Amplifiers
Operational Amplifiers

til

Nat ion a I S'e m i c 6 n due to ,r

Industry Package Cross-Reference Guide

NSC

CJ
~

~=

~
In

©
CJ

NSC

p,A

Signetics

Motorola

TI

AMD'

Sprague

4/16 Lead
Glass/Metal DIP

0

0

I

L

Glass/Metal
Flat Pack

F

F

Q

F

F,
S

F

TO-99, TO-100, TO-S

H

H

T,
K,
L,
DB

G

L

H

8-, 14- and 16-Lead
Low Temperature
Ceramic DIP

J

R,
0

F

U

J

0

H

KC

K

OA

K

N

T,
P

N,
V

P

P

A,
B,

0

R

W\fWW
~

0

D
m

(Steel)
K
TO-3

KS
K

(Aluminum)

8-, 14- and 16-Lead
Plastic DIP

xxvi

P,

N

M

NSC

PO
~;

t=
~
mil
G

TO-263
3-& 5-Lead

TO-220
3-&5-Lead
TO-220
11-,15- & 23-Lead

NSC

/-LA

Signetics

Motorola

TI

AMD

Sprague

8

T

U

KC

U

T

Low Temperature
Glass Hermetic
Flat Pack

W

F

TO-92
(Plastic)

Z

W

M

8

8

F

W

F

P

LP

0

0

L

ow

LW

~
GUUUUttJ
RRRRRRRRRR

80

(Narrow Body)
(Wide Body)

WM

D

•

1::11::11::11::1

!:It:l 1::1 I:H:I 1::1

fUUUUUUUUiRJ
~

80T-23
5-Lead

M5

xxvii

8,

0

CD
'1:1

:;

NSC

NSC
/LA

Signetics

Motorola

TI

AMD

Sprague

pcc

V

Q

A

FN

FN

L

EP

LCC
Leadless Ceramic
Chip Carrier

E

L1

G

U

FKI
FG/FH

L

EK

"8
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CD
CD
CD

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xxviii

Section '1 '
Audio Circuits

•

Section 1 Contents
Audio Power Amplifiers
Audio Power Amplifiers-Selection Guide .............................................
LM380 Audio Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM383/LM383A 7W Audio'Power Amplifier............................................
LM384 5W Audio Power Amplifier ....................................................
LM386 Low Vo!tage Audio Power Amplifier ............................................
LM388 1.5W Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array. . . . . . . . . . . . . . . . . . . . .
LM390 1W Battery Operated Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM391 Audio Power Driver ..........................................................
LM831 Low Voltage Audio Power Amplifier..... ..... ..... ........... ........ ...... ....
LM1875 20W Audio PowerAmplifier ..................................................
LM1876 Dual20W Audio Power Amplifier with Mute and Standby Modes..................
LM1877 Dual Audio Power Amplifier......... ... ................ ............ ......... .
LM1896/LM2896 Dual Audio Power Amplifiers... ....................... ..... ......... .
LM4700 Overture™ 30W Audio Power Amplifier with Mute and Standby Modes ............
LM2876 High-Performance 40W Audio Power Amplifier with Mute ........................
LM2877 Dual4W Audio Power Amplifier...............................................
LM2878 Dual 5W Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . .. . . . . . . . . . . . . .
LM2879 Dual 8W Audio Power Amplifier. . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . .. . . . . . . . . . . . .
LM3875 High Performance 56W Audio Power Amplifier............ ............ ..........
LM3876 High Performance 56W Audio Power Amplifier with Mute ..'. . . . . . . . . . . . . . . . . . . . . . .
LM3886 High-Performance 68W Audio Power Amplifier with Mute ........................
LM4860 1W Audio Power Amplifier with Shutdown Mode ................................
LM4861 %W Audio Power Amplifier with Shutdown Mode...............................
LM4862 350 mW Audio Power Amplifier with Shutdown Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM4880 Dual 200 mW Audio Power Amplifier with Shutdown Mode.......................
Audio Controls
Audio Control-Selection Guide......................................................
LM1036 Dual DC Operated Tone/Volume/Balance Circuit... ..................... .......
LM1971 Jl-Pot 62 dB Digitally Controlled Audio Attenuator with Mute. . . . . . . . . . . . . . . . . . . . . . .
LM 1972 Jl-Pot 2-Channel 78 dB Audio Attenuator with Mute . . . . .. . . . . .. . . . . . . . . . . . . . . . . . .
LM1973 Jl-Pot 3-Channel76 dB Audio Attenuator with Mute. . . . . . . . . . . . .. . . . . . . . . . . . . . . . .
LMC835 Digital Controlled Graphic Equalizer. . . . . . . . . . . . . .. . .. . . . . .. . . . . . . . . . . . . . . . . . . .
LMC1982 Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo
Inputs. .... .................................... ................ ........... ... ....
LMC1983 Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable Stereo
Inputs......... ...... ................... ... ................ ..... ........ . ... .....
LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel
Input-Selector ...................................................................
Audio Operational Amplifiers
Audio Operational Amplifiers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM387/LM387A Low Noise Dual Preamplifier..........................................
LM833 Dual Audio Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
LM837 Low Noise Quad Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM6142 Dual and LM6144 Quad High Speed/Low Power 17 MHz Rail-to-Raillnput-Output
Operational Amplifiers ............................................................

1-2

1-4
1-6
1-10
1-14
1-19
1-24
1-30
1-38
1-43
1-54
1-66
1-72
1-73
1-78
1-86
1-87
1-103
1-110
1-117
1-124
1-140
1-156
1-173
1-182
1-189
1-190
1-191
1-192
1-201
1-202
1-211
1-220
1-235
1-246
1-257
1-269
1-270
1-274
1-283
1-289

Section 1 Contents (Continued)
Audio NOise Reduction
Audio Noise Reduction-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1131A1LM1131B/LM1131C Dual Dolby B-Type Noise Reduction Processor............
LM1894 Dynamic Noise Reduction System DNR® ......................................

1-3

1-300
1-301
1-306

tfJ

.'

National Semiconductor

'.!'

.

.

..

.'

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,

., .

"

, .

.. '

Audio PoWer Amp SE!lection Guide

Supply
Voltage

Part
Number

Power(THD ,;;;1% Typ)
Power Specified as Continuous RMS

Power (THD ,;;; 10% Typ)
Power Specified as Continuous RMS

40

ao

160

40

ao

160

3V

LM4860
LM4861
LM831

O.6W
O.6W
O.1W

O.4W
O.4W
O.07W

O.2W
O.2W
NA

O.76W
O.76W
O.15W

O.5W
O.5W
O.44W

O.3W
O.3W
NA

5V

LM4860
LM4861
LM4862
LM4880
LM386
LM388
LM831
LM1896

1.55W
1.3W
NA
NA
O.25W
O.6W
O.25W
O.7W

1.15W
1.15W
O.350W
O.200W
O.25W
O.35W
O.1W
O.45W

O.6W
O.6W
NA
NA
O.15W
O.25W
NA
NA

1.9W
1.75W
NA
NA
O.32W
O.8W
O.4W
1.1W

1.45W
1.45W
O.5W
O.3W
O.3W
O.5W
O.44W
1.3W

O.85W
O.85W
NA
NA
O.2W
O.35W
NA
NA

12V

LM380
LM383
LM384
LM386
LM1877
LM2877
LM2878
LM2896

1.5W
3.5W
NA
O.25W
1.5W
1.5W
1.5W
3W

1W
NA
NA
O.6W
1W
1W
1W
2W

NA
NA
NA
O.6W
O.55W
O.55W
O.55W
NA

2.25W
4.7W
1.75W
O.35W
1.75W
1.75W
2W
4.25W

1.5W
NA
NA
O.8W
1.3W
1.3W
1.3W
2.5W

NA
NA
NA
O.95W
O.75W
O.75W
O.75W
NA

14V

LM380
LM383
LM384
LM386
LM1877
LM2877
LM2878
LM2879

2.5W
2W
NA
NA
2W
2W
2W
NA

1.75W
NA
NA
O.6W
1.3W
1.3W
1.3W
1.25W

NA
NA
NA
1W
O.85W
O.85W
O.85W
NA

3.25W
5.5W
3.25W
NA
2.5W
2.75W
2.75W
NA

2.25W
NA
NA
O.8W
1.75W
1.75W
1.75W
2W

NA
NA
NA
1.6W
1W
1W
1W
NA

LM1877
LM2877
LM2878
LM2879
LM380
LM384
LM391 *
LM1875
LM1876
LM2876
LM3875
LM3876
LM3886

2W
2.5W
NA
NA
NA
NA
NA
20W
15W
25W
45W (Vs = ±25V)
45W (VS = ±25V)
68W (Vs = ±28V)

2W
3W
4W
7W
4W
5.5W
80W'
20W
15W
40W
56W
56W
63W

NA
1.75W
NA
NA
2.5W
NA
NA
NA
NA
22W
30W
30W
33W

2.5W
3.7W
NA
NA
NA
2.5W
NA
25W
NA
35W
56W (Vs = ±25V)
56W (Vs = ±25V)
87W(VS = ±28V)

3W
4.25W
4.75W
8W
5W
7W
NA
30W
20W
50W
70W
70W
78W

NA
2.3W
NA
NA
3.25W
5W
NA
NA
NA
26W
39W
39W
41W

(Vs=
(Vs=

6\1?
6\1?

(Vs=

6\1?

(Vs= 16V)

20V&Above

(Vs= 2OV)
(Vs= 20\l?
(Vs= 20V)
(VS = 28V)
(Vs= 22\1?
(VS = 26V)
(Vs= ±40V)
(Vs= ±25V)
(Vs= ±22V)
(Vs= ±30V)
(Vs= ±35V)
(VS = ±35V)
(Vs= ±35V)

"

• The LM391 is an Audio Power Driver designed to drive external transistors.

I
1-4

Audio Power Amp Selection Guide (Conlinued)
Typical THO
Ratings

THO Measurement
Conditions

Supply
Range (V)

Singlel
Dual

Package
(Pin Count)

2.7Vlo 5.5V
2.7VI05.5V
1.8V10 6V

Single
Single
Dual

SO(16)
SO(8)
DIP(16), SO(16)

0.72%
0.45%
0.25%

@Vs=5V
Po = lW
Po = 0.5W @Vs= 5V
Po = 0.05W @Vs= 3V

0.72%
0.45%
0.45%
0.10%
0.25%
0.10%
0.25%
0.11%

Po
Po
Po
Po
Po
Po
Po
Po

=
=
=
=
=
=
=
=

lW
0.5W
0.35W
0.2W
0.125W
0.5W
0.05
0.5W

@Vs= 5V
@Vs= 5V
@Vs= 5V
@Vs= 5V
@Vs = 6V
@Vs=12V
@Vs = 3V
@Vs= 6V

2.7V 10 5.5V
2.7VI05.5V
2.7Vlo5V
2.7V105V
4Vlo 18V
4Vl012V
1.8V10 6V
3Vlo 10V

Single
Single
Single
Dual
Single
Single
Dual
Dual

SO(16)
SO(8)
SO(8)
SO(8)
SO(8), DIP(8)
DIP(14)
DIP(16), SO(16)
DIP(14)

0.50%
0.20%
0.25%
0.25%
0.055%
0.07%
0.14%
0.14%

Po=
Po=
Po=
Po =
Po=
Po =
Po=
Po =

4W
2W
4W
0.125W
,
lW
lW
2W
lW

@Vs= 22V
@Vs = 14.4V
@Vs = 22V
@Vs = 6V
@Vs = 14V
@Vs=14V
@Vs= 22V
@Vs=12V

10Vlo 22V
5Vl020V
12Vlo 26V
4Vlo 18V
6Vl024V
6Vl024V
6Vl032V
3Vto 15V

Single
Single
Single
Single
Dual
Dual
Dual
Dual

DIP(14), DIP(8)
TO-220(5)
DIP(14)
SO(8), DIP(8)
DIP(14), SO(14)
SIP(II)
SIP(II)
SIP(II)

0.20%
0.20%
0.25%
0.25%
0.055%
0.07%
0.15%
0.05%

Po=
Po=
Po=
Po =
Po =
Po =
Po=
Po =

4W
2W
4W
0.125W
lW
lW
2W
lW

@Vs=
@Vs =
@Vs=
@Vs =
@Vs=
@Vs =
@Vs =
@Vs=

10Vto 22V
5Vlo20V
12Vlo 26V
4Vlo 18V
6Vl024V
6Vl024V
6Vl032V
6Vl032V

Single
Single
Single
Single
Dual
Dual
Dual
Dual

DIP(14), DIP(8)
TO-220(5)
DIP(14)
SO(8), DIP(8j
DIP(14), SO(14)
SIP(II)
SIP(II)
TO-220(11)

0.055%
0.07%
0.15%
0.05%
0.20%
0.25%
0.01%
0.02%
0.08%
0.06%
0.06%
0.06%
0.03%

Po = lW
Po = lW
Po= 2W
Po = lW
Po= 4W
Po=4W

6Vl024V
6Vl024V
6Vl032V
6Vl032V
10Vto 22V
12Vl026V
±10Vlo ±50V
16Vl060V
20Vl054V
20Vl060V
20Vl084V
20Vlo84V
20Vl084V

Dual
Dual
Dual
Dual
Single
Single
Single
Single
Dual
Single
Single
Single
Single

DIP(14), SO(14)
SIP(II)
SIP(II)
TO-220(11)
DIP(14), DIP(8)
DIP(14)
DIP(16)
TO-220(5)
TO-220(15)··
TO-220(11)* •
TO-220(11)* *
TO-220(11)*·,
TO-220( 11)"'

Po
Po
Po
Po
Po
Po

=
=
=
=
=
=

22V
14.4V
22V
6V
14V
IV
22V
12V

@Vs= 14V
,@Vs = IV
@Vs = 22V
@Vs=12V
@Vs = 22V
@Vs = 22V
*
@Vs= ±25V
20W
15W/ch@ Vs = ±22V
@Vs= ±30V
25W
@Vs= ±35V
40W
40W
@Vs = ±35V
@Vs= ±28V
60W

.. Isolated packages available,

1-5

II

=

:; I!fINational Semiconductor

LM380 Audio Power Amplifier
General Description
The lM380 is a power audio amplifier for consumer applicaA selected part for more power on higher supply voltages is
tion. In order to hold system cost to a minimum, gain is . available as the lM384. F.or mote information see AN-69.
internally fixed at 34 dB. A unique input stage allows inputs
to be ground referenced. The output is automatically self
Features
centering to one half the supply voltage.
.
• Wide supply voltage range
The output is short circuit proof with internal thermal limiting.
• low quiescent power drain
The package outline is' standard dual-in-line. A copper lead
• Voltage gain fixed at 50
frame is used with the center three pins on either side com• High peak current capability
prising a heat sink. This makes the device easy to use in
• Input referenced to GND
standard p-c layout.
• High input impedance
Uses include simple phonograph amplifiers, intercoms, line
•
low distortion
drivers, teaching machine outputs, alarms, ultrasonic driv• Quiescent output voltage is at one-half of the supply
ers, TV sound systems, AM-FM radio, small servo drivers,
voltage
power conve.rters, etc.
• Standard dual-in-line package

Connection Diagrams (Dual-In-line Packages, Top View)
BVPASS t

14 Ys

NDN-INVERTING INPUT 2

13 Ne

Ne 1

NON·INVERTING INPUT 2

']



~

4.~

TA=2rc-

I-

~
~

co

15
30

1-t-11-H-t-+-I-H-t--/

1.2

II:

3.0

I ~:r-~HH-~+-HH-+-'

Z.o

I

c

'1.0

.£

~ 0.6/~il-·7+-+-H--+-l

e

o
1.0

10

12

14

16

II

2D

22

h(·t-1I-H---,;t-+-I-H-hlll

0.4

~~EM=t::E~~~II~
lW'

L

0.2

100 200

500

v+ SUPPl V VOL rAGE IV)

10

~

I.D

co~ I.'
t;

1.'

~ '.0

i

5.0

! 4.0

5k 10k '2Dk

",-In

0.4

eo..... - ....

HEATStNK'TWO
COPPER WINOS
SEE fiG. PAGE 4

e

w

I

c

u

!

co

1.0:2.1

&.0

'. - OUTPUT POWER (WATTSI

15

/

l'

D.l

'ruT "'2W

... = 4011

I

10

0.1

0.2

100

10k

1k

lOOk

240'
3DO'

380'
1M

111M

lOdI

1111

II

IIU

U

, 5(1f

-

-

-

~

~

2~1

1.

2UI

....

10dl

=:::

U7(1f-

III!III
'NO

BY~l~I~APACITOR

-IVeel. IV

I

J

IIIII
,

o

COdl

I I
I I

y- ~'l%THO

120'

lit. =10 "

10

r-

I I

A/

80'

Supply Decoupllng vs
Frequency

1..1/
V.!.
~THO r-

Ie 0.3 f--L -1\-110

c;

D.S

I\-j"

I'

0'

III
PjAfEI

2D

SOdl

1/

./

Vee fllV

~~L

Z5

Device Dissipation vs
Output Power

i
&u

Vee" ltV

0.2

III

fREQUENCY (H.I

0.5

I-1kHz

~ 3.0

2.0
I 1.0
§! 0
~
D.1

2k

LEVELl

48

FREQUENCY (H')

Total Harmonic Distortion
vs Output Power

is

lk

~~~:I[.

Output Voltage Gain and
Pha,e vs Frequency

1-t-11-H-t-+-I-H-t--I

1.4

~

~

"I

~,

I

2.0 '--T"'1m-r"T""I"'T'I-~'
1.1 1-t-11-H-t-+-Ht~v= 8n
1.6

.,..

I-

• 0.5 I.D '1.5 2.1 2.5 3.D U 4.14.5 U

Total Harmonic Distortion
vs Frequency

..

-

OUTPUT POWER MATTS!

~

i

;:;

4.5 5.D

5.0
4.0

~

28'

OUTPUT POWER IWATTSI

10.0

5

~ 1'-..
~1-'

111%
. ·OIST.
LEVEL

u

Power Suppiy Current VB
Supply Voltage
.
9.0

I
1% OIST.
L VEL

~'r-I~

":>

OUTPUT POWER IWATTSI

!

Device Dissipation vs Output
Power-16fi Load

1.0

~

--

D
<

TLlH/6977 -12

111111111
0.3

0.4

OUTPUT POWER (WATTSI

0.5

llHI

110Hz

1kHz

111111
1011Hz'

fREQUENCY
TL/H/6977 -7

1-8

Typical Applications
Phono Amplifier

O,'~

CRYSTAL

CARTRIDGE

TL/H/6977 -6

Bridge Amplifier

v,

v,

TL/H/6977 -9

Intercom

v,

LISTEII

I

L__________________________
-

I

I
I
I
I
I
I
:

TALK

~

-FOR STABILITY WITH
HIGH CURRENT LOADS

TL/H/6977 -10

II

Phase Shift Oscillator

bUMz

TL/H/6977 -11

1-9

.~

~tfI
~:
National Semiconductor
ell)

co
ell)

~

LM383/LM383A 7W Audio Power Amplifier
General Description

Features

The LM383 is a cost effective, high power amplifier suited
for automotive applications. High current capability (3.5A)
enables the device to drive low impedance loads with low
distortion. The LM383 is current limited and thermally protected. High voltage protection is available (LM383A) which
enables the amplifier to withstand 40V transients on its supply. The LM383 comes in a 5-pin TO-220 package.

•
•
•
•
•
•
•
•
•

High peak current capability (3.5A)
Large output voltage swing
Externally programmable gain
Wide supply voltage range (5V-20V)
Few external parts required
Low distortion
High input impedance
No turn-on transients
High voltage protection available (LM383A)

• Low noise
• AC short circuit protected

Equivalent Schematic
5

L.~~~--~---+

+INPUT

______" __ __ ____ __________________
~

~

~

Vs

-4~-oGNO

-INPUT
TL/HI714S-1

Connection Diagram
Plastic Package

~:~T--~~;O~UT~{~~~S~~~
rO
~

l~:~l_~V~+~-~GN~OI~~~I~~~~)
-

45 SUPPLY
OUTPUTVOLTAGE

2
INVERTING INPUT
3 GROUND
1 NON·INVERTING INPUT
TLlHI714S-2

Order Number LM383T or LM383AT
See NS Package Number T05B

1-10

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Peak Supply Voltage (SO .[!ls)
LM383A (Note 2)
LM383

40V
25V

Operating Supply Voltage

20V

Output Current
Repetitive
Non-repetitive

3.SA
4.SA

Electrical Characteristics Vs =
Parameter

Input Voltage

- 60·C to + 150·C

Lead Temperature (Soldering, 10 sec.)

14.4V, TTAB

=

25·C, Av

=

Conditions

100 (40 dB), RL

=

4!l, unless otherwise specified
Typ

Max

6.4

7.2

8

V

45

80

mA

20

V

Excludes Current in Feedback Resistors
5

Units

1S0

kn

30

kHz

= 4!l, THD

4.7
7.2

W
W

= 40., THD = 10%

5.1
7.8

W
W

5.5
8.6
9.3

W
W
W

7
10.S
11

W
W
W

0.2
0.2

%
%

40

44

dB
dB

2

/LV

40

pA

Bandwidth

Gain

Output Power

Vs
RL
RL
Vs
RL
RL
Vs
RL
RL
RL
Vs
RL
RL
RL

=

=

40dB

= 1 kHz
= 10%
= 2!l, THD = 10%
= 13.8V, f = 1 kHz
13.2V, f

= 2!l, THD = 10%

=

14.4V, f = 1 kHz

= 4!l, THD = 10%

4.8
7

=
=

2!l, THD = 10%
1.6!l, THD = 10%
= 16V,f = 1 kHz
= 4!l, THO = 10%
= 20., THO = 10%
= 1.6!l, THO = 10%

= 2W, RL = 40., f =
= 4W, RL = 20., f =
Rs = 50!l,f = 100Hz
Rs = 500., f = 1 kHz
Po
Po

260"C

Min

Input Resistance

Ripple Rejection

O"Cto +70·C

Storage Temperature

Supply Voltage Range

THD

15W

Operating Temperature

DC Output Level
Quiescent Supply Current

±O.SV

Power Dissipation (Note 3)

1 kHz
1 kHz
30

Input Noise Voltage

Rs = 0, 15 kHz Bandwidth

Input Noise Current

RS = 100 k!l, 15 kHz Bandwidth

Note 1: A 0.2 p.F capacitor in series with a III resistor should be placed as close as possible to pins 3 and 4 for stability.
Note 2: The LM383 shuts down above 25V.
Note 3: For operating at elevated temperatures, the device must be derated based on a 150"'C maximum junction temperature and a thermal resistance of 4'C/W
junction to case.

1-11

II

Typical Performance Characteristics
~1

.

Device Dissipation vs,
, ,Ambient Temperature
II

-t-

14

i

12

co
;::

10

z

Power Dissipation vs
Output'Power '
16

'

, , At-4

r-

RL

..

;
o

I I I J
I I I I
o

II H

H~

iiii

10

..

M U

y.~

• " " ,12
OUTPUT POWER (Wj

024

w

~

>
I

..
..~

II

6B

"

H

ZO

-H

I--t-+-I+ttttl--+-+++H++I

10
0
100

1k

ll1k

100.

-CD

Io..;:l-+l-tttttl--I-t++H+!J

100

12

t-t-t-

1-"1-'"

21

o

10k;

o 2

4

«

8 8 II 12

II II ZD

VSUPPLY (VI

Distortion vs Frequency
II
I-AV= 100
VS-1UV
I-RL =4

I
RL~Z ~
I

10

VI

£

V
VI...!

5co

4 L-4

VI'

II

~

o

2

4

&

6r. ~

,5W

1

I

8

o

10 12 ~4 1& 18 20

20

50 108 200 SOD 1., 2.

OUTPUT POWER (WI

VSUPPLY (VI
"'"

II II

10

I

I-

o

,.

«

~I-'"

30

Distortion vs Output Power

"18 ~HO~'~

~

ii:

-60 L--L..L.I.l.1JUJ.I,.""';L..;.I...L.I.llJ.U
1M

, Output Power vs
Supply Voltage

14

40

FREQUENCY (H,I ,

ZO

..

It..

-so t---++l-tttttl--I-t++Hffi

FREQUENCY (H,I

i

.!

60

l-

,

5'

6 8 II 12

E~CL'UO~S C~RR~,J IN
fEEDIACK RESISTORS

8D

C

I--t-+-I+ttttl--+-+++H++I

I..

~

10

1-++I-ttHtt-t-lI-+HfHl

,co
;:: -20
w

~

co

c

-10

'

Supply Current vs
Supply Voltage

As-50

;.

U
10

I'

V'THO-10l1 '

OUTPUT POWER (WI

Supply Ripple Rejection
vs Frequency

•

k'v~v
i ,J

:z
o

14

lDO

C

I
IL JL ~

C

if,

L fo'

tTHO-3Y

VS=15~

w

Open,Loop Gain
vs Frequency

....

1/

is

TA - AMIIENTTEMPERATURE (OC),

Ii
S

v~-zJv- r- -

lZ

co

2~~ HE~T SI.!;'" r--..

w

-"2

14

i

'T

f

.

Power Dissipation va'
Output Power
'

,~c.J HEA~ SlJK

I

'd

iNFrE iEAT,.,~K-

"j'

~k.1It 20~

FREQUENCY'(H,I

:~

Output Swing vs
Supply Voltage

Distortion vs Frequency
10

ZO
_AV=I00
VS'" '4.4V
-RL=Z

~ ~L~~ ~
I

II

I
..

i...

18

1

14
IZ

RL-4~

r;..-'

II

~

~

co

~~

~

~ "RL -z-t-

Z.5W

1

o
ZD

60 100 ZIO 601 1k Zk

o

6. 10k ZO.

FREQUENCY (HzI

o

Z 4

6

I 10 12 14 18 18 20
VSUPPLY (VI
TL/H/714S-4

1-12

Typical Applications
Single Amplifier .

412

TUHI7145-3

16W Bridge Amplifier

Vs

Vs

14.4V

14.4V

O.hF"*

10.F

--1

SIGNAL
INPUT,

1M

TUH/7145-5

Component Layout
Single Amplifier
Vs

= 20V

RL

=

II

41l

Heatsink from:
Staver Company
41 Saxon Ave.

P.O. Drawer H
Bay Shore, NY 11706
Tel: (516) 666·6000

TL/H/7145-6

1-13

~

~

~

r----------------------------------------------------------------------------,

tfI

Nat ion a I S e m i con due tor .'

LM384 5W Audio Power Amplifier
General Description

Features

The LM384 is a power audio amplifier for consumer application. In order to hold system cost to a minimum, gain is
internally fixed at 34 dB. A unique input stage allows inputs
to be ground referenced. The output is automatically selfcentering to one half the supply voltage.
'
The output is short-circuit proof with internal thermal limiting. The package outline is standard dual-in-line. A copper
lead frame is used with the center three pins on either side
comprising a heat sink. This makes the device easy to use
in standard p-c layout.
Uses include simple phonograph amplifiers, intercoms, line
drivers, teaching machine outputs, alarms, ultrasonic drivers, TV sound systems, AM-FM radio, sound projector systems, etc. See AN-69 for circuit details.

Schematic Diagram

•
•
•
.•
•
•
•
•

Wide supply voltage range
Low quiescent power drain
Voltage gain fixed at 50
High" peak current capability
Input referenced to GND
High illput impedance
Low distortion
Quiescent output voltage is at one half of the supply
voltage
• Standard dual-in-line package

,...----------------4. . .----..

-0() V.(141

,5

25k
25k

OUTPUT

(81
BYPASS

.5

(11

25k
lk

-IN
(61

.....~~-O.IN
(ll.

ISOk

(3,4.5.10.11,121

(11 GNO

GND
TLlH/7843-3

1-14

Absolute Maximum Ratings
Storage Temperature

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
2aV
Supply Voltage
Peak Current
Power Dissipation (See Notes 3 and 4)

Operating Temperature
Lead Temperature (Soldering, 10 sec.)

260·C

Thermal Resistance
8JC
8JA

1.3A
1.67W
±0.5V

Input Voltage

-65·C to + 150·C
O·Cto +70·C

30·C/W
79·C/W

Electrical Characteristics (Note 1)
Parameter

Symbol
liN

Input Resistance

ISlAS

Bias Current

Av

Gain

POUT

Output Power

Conditions

Min

Typ

Max

150
Inputs Floating

THD

=

kn

100

10%, RL

=

an

40

50

5

5.5

Units

nA
60

VIV
W

IQ

Quiescent Supply Current

a.5

VOUTQ

Quiescent Output Voltage

11

V

BW

Bandwidth

450

kHz

POUT

=

2W, RL

=

an

25

mA

V+

Supply Voltage

Isc

Short Circuit Current (Note 5)

1.3

A

PSRRRTO

Power Supply Rejection Ratio
(Note 2)

31

dB

12

Total Harmonic Distortion
THD
POUT = 4W, RL = an
Note t: V+ ~ 22V and TA ~ 25'C operating with a Slaver V7 heat sink for 30 seconds.
Note 2: Rejection ratio refarred to the output with CBYPASS ~ 5 I'F, freq ~ t20 Hz.
Note 3: The maximum junction temperature of the LM384 is t50"C.
Note 4: The peckage is to be derated at t5'C/W junction to heat sink pins.
Note 5: Output is fully protected against a shorted speaker condition at all vollages up to 22V.

26

0.25

1.0

V

%

Heat Sink Dimensions
Staver "V7" Heat Sink
Staver Company

41 Saxon Ave.
P.O. Drawer H
Bay Shore,'N.Y.
Tel: (516) 666-8000

"1.6

T \\\\\\\\
II/l/l"-

~

1.35

~v-;~
1---'1.5

II
TL/H17843-4

1-15

"'It
CD

~.

Typical Performance Characteristics
Device Dissipation vs
Ambient Temperature
12.0

. Thermal Resistancli vs
Square Inches

IfIfl!1U "(~T.,.J Iz-~

J..!v
Z4V

b

......
~;..Ii

zzv ~ ..... ~

zov 7'i"Joo

3% OIST. LEVEL

r-Y ~·IIIlIIOIJ. JvL
'srAVEJ

.~," JEA+ SI~K

23451

30

OUTPUT POWER (WI

7

1911

OUTPUT POWER IWl

Device Dissipation va
Output Power-40 Load

7r---r--T""'::--r--r---,

OUTPUT POWER !WI
TL/H/7843-5

1-16

Block and Connection Diagrams
Dual-In-Line Package

BYPASS

BYPASS I

14 Vs

NON·INVERTING INPUT 2

13 NC

Vs

INPUT

12J

11 GND'

Your

10

INPUT

GND

INVERTING INPUT 6

9

NC

GNU 1

a

VOUT

GND
TL/HI7843-1

-Heatsink Pins

TLlHI7843-2

Top View
Order Number LM384N
See NS Package Number N14A

Typical Applications
Typical 5W Amplifier
+22V

11III,....1------t

an

TL/HI7843-6

Bridge Amplifier

•
TL/H17843-7

1-17

Typical Applications (Continued)
Intercom

V.

I.'"F

b.

Co

':' 5II/lF

LISTEN

•

LISTEN

ITALK

,
I

l'0.'"F
L __________________________
'For stability with
high current loads

!
I
I

~

"~
TL/HI7843-8

Phase Shift Oscillator

v.

TL1H17843-9

1-18

ttlNational Semiconductor

LM386 Low Voltage Audio Power Amplifier
General Description
The LM386 is a power amplifier designed for use in low
voltage consumer applications. The gain is internally set to
20 to keep external part count low, but the addition of an
external resistor and capacitor between pins 1 and 8 will
increase the gain to any value up to 200.
The inputs are ground referenced while'the output is automatically biased to one half the supply voltage. The quiescent power drain is only 24 milliwatts when operating from a
6 volt supply, making the LM386 ideal for battery operation.

Features
•
•
•
•

Battery operation
Minimum external parts
Wide supply voltage range
Low quiescent current drain

4V-12V or 5V-18V
4 mA

•
•
•
•
•

Voltage gains from 20 to 200
Ground referenced input
Self-centering output quiescent voltage
Low distortion
Eight pin dual-in-line package

Applications
• AM-FM radio amplifiers
• Portable tape player amplifiers
• Intercoms
• TV sound systems
• Line drivers
• Ultrasonic drivers
• Small servo drivers
• Power converters

Equivalent Schematic and Connection Diagrams
Dual-In-Llne and Small Outline
Packages

r-------------------------~----_1~V,

GAIN

GAIN

-INPUT - - ,................

BYPASS

+INPUT

v,

GND

-I~PUT

TL/H/697S-2

Top View

4

~-4~"----------"--~~~-----1~----~~GND

TL/H/6976-1

Order Number LM386M-1,
LM386N-1, LM386N-3 or LM386N-4
See NS Package Number
M08AorN08E

Typical Applications
Amplifier with Gain = 20
Minimum Parts

Amplifier with Gain

II

= 200

2SIJpF

~'~I:~)

V,N

TL/H/6976-4
TL/H/6976-3

1-19

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Soldering Information
Dual-In-Line Package
Soldering (10 sec)
Small Outline Package
Vapor Phase (60 sec) ,
Infrared (15 sec)

HiV

Supply Voltage (LM386N-1, -3, LM386M,-1)
Supply Voltage (LM386N-4)

22V

Package Dissipation (Note 1) (LM386N)
(LM386M)

1.25W
0.73W
-6S>C to + 150·C

Operating Temperatu'ie

O·Cto +70"C

Junction Temperature

>'("'

Electrical Characteristics

+ 150"C

TA = 25~C

Parameter

Conditions

Operating Supply Voltage (Vsl
LM386N-1, -3, LM386M-1
LM386N-4

Output Power (POUT)
LM386N-1, LM386M-1
LM386N-3
"
LM386N-4

Min

Typ

4
5

Quiescent Current (la)

4

Vs = 6V, VIN = 0
,

+215·C
+ 220"C

See AN-450 "Surface Mounting Methods and The,ir Effect
,on Product Reliability", for other methods of. sOldering surface mou,ilt device~.
Thermal Resistance
37"C/W
8Jc(DIP)
1()7"C/W
8JA(DIP)
35·C/W
8JC (SO Package)
8JA (SO Package)
172"C/W

±0~4V

Input Voltage
Storage Temperature

+ 260"C

"-

"

Vs = 6V, RL = 811, THD = 10%
VS"" 9V, RL = 811,THD = 10%
Vs = 16V, RL = 3211, THD = 10%

av,

250
500
700

Max

Units

12
18

V
V

8

mA

325
700
1000

mW
mW
mW

Voltage Gain (AV)

Vs ;"
f = 1 kHz
10 p.F from Pin 1 to 8

26
46

dB
dB

Bandwidth (BW)

Vs = 6V, Pins 1 and 8 Open

300

kHz

Total Harmonic Distortion (THD)

Vs = 6V, RL =811, POUT = 125 mW
f = 1 kHz, Pins 1 and 8 Open

0.2

%

. Vs = 6V, f = 1 kH~, CBYPASS = 10 p.F
Pins 1- and 8 Open, Referred to Output

50

dB

50
250

kl1
nA

Power Supply Rejection Ratio (PSRR)
Input Resistance (RIN)
Input Bias Current (IBIAS)

Vs = 6V, Pins 2 and 3 Open

Note 1: For operation in ambient temperatures above 25"C, the device must be derated based on a 150"C maximum junction temperature and 1) a thermal
resistance of 80"ciw junction to ambient for the dual~n-line package and 2) a thermal resistance of 170"C/W for the small outline package.

Applicatiol), Hints
GAIN CONTROL
To make the LM386 a more versatile amplifier, two pins (1
and 8) are provided for gain control. With pins 1 and 8 open
the 1.35 kl1 resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 1 to 8, bypassing ~he 1.35 kl1 resistor, the
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capacitor, the gain can be set to any value from 20
to 200. Gain control can also be done by capacitively coupiing a resistor (or FET) from pin 1 to ground.

INPUT BIASING
The schematic shows that both inputs are biased to ground
with a 50 kl1 resistor. The base current of the irput transistors is about 250 nA, so the inputs are at about 12.5 mV
when left o,pen. If" the dc source resistance driving the
LM386 is higher than 250 kl1 it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kl1, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50: mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.

Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker- bass response by frequenq, shaping the feEldback path. This is done with a series RG from pin 1 to 5 (paralleling the intElmal 15 kl1 resistor). For 6 dB effective bass boost: R "" 15 kl1, the lowest
value for good stable operation is R = 10 kl1 if pin 8 is
open. If pins 1 and 8 are bypassed then R as low as 2 kl1
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9.

When using thE! LM386 with higher gains (bypassing the
1.35 kl1 resistor between pins 1 and 8) it is necessary to
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 p.F capacitor or a short to ground depending on the dc source reSistance on the driven input.
1-20

Typical Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output)
vs Frequency

Quiescent Supply Current
vs Supply Voltage

&0 r-TTTTTlllrT"lTrmr-rTTmlr-TTTTT1III

~

4

5,

•

..... ~

~~

..

;
co

Sf!

4.

t

;;i
~

t

11 .11

I

....
~
II

~

co

>

I.
I.

~co

10

to

211

,_
11k

lk.

i!
Ii

1.1
,.I

i
I
!

1.4

i

I

V

1.0

./

k-

~

I

...,..... '-,

/ ' Vs-"
Y,-IV

r-

I

Distortion vs Output Power

:: ::~!

I I

I

....."

D.2

o

28

V
o

Sf! 108 ZOI SOD lk Zk

t:tmlIlIbitiiltttltI

0.081

5k 10k ZDk

Device Dissipation vs Output
Power-80 Load

3!lTHO
LEVEL

...L
..... 1l1li THO

LEVEL

D.2
D.3
U
OUTPUT POWER \WI

=

1.4

j:

1.2

~

...

1.0

Device Dissipation vs Output
Power-160 Load
.

/

i

.~

I

-I 1

I

Vs -1ZV

... i7'I-y.~ 'I

aU

•.2
1.1

1 1 1

11.8

~a: •.0

D.Dl
D.1
POWER OUT (WArnl

1.0

1.1

I

1III-+++If1111--+-fll-HHI

f _ ,.'" 1fII-+++ifllll--+--I!-HIHI

125 mW
/Iv - ZU. tC, .• - DI

FREQUENCY tHzl

1
D.l

45BII"81112

D••

1M

rv.!'zv,;.;,

1.2

DA
D.2

R, -In

4-

11 0"......-nmIl"""!"T1'1T1T1r""1""TImm

I

Z.D

1.1

0.1

I

-

..-

-

o

'OUT"

DA

~

1
1

1.4

I ...

V.-BV

~

~

2.1

II

~

~ .,!

:r.

SUPPLY VOLTAGE IVOLTSI

1.Z

Device Dissipation vs Output
Power-40 Load

i

lOOk

1111

1k

Distortion vs Frequency

FREQUENCY tHzl

1.1

~~

.

100

=

[\

D

~
~~

~

2.0

l!ll!l!

31

./.

~

FREQUENCY 1Hz)

111111111

40

ft'

co

12

c!1~I\t

c

R~-~

~

20

Voltage Gain vs Frequency
Sf!

10

~

h1i-Hl.....tttlfHll'>fttt

SUPPLY VOLTAGE IVOLTSI

&D

~

~

ii

•

=
c

3D

..
I
1

HmrH:loHft-HIHJIIH+++f1lll

Peak-to-Peak Output Voltage
Swing vs Supply Voltage

~ !L'.V"~'iii'THO
LEVEL

n

1~.THO

• 0.1 D.2 1.3 DA D.• D.' 1.7 ... 0.1 1.1

OUTPUT POWER till

II

5

D••

a.1

::!!&...
i::

CI

0.2

o

I.Z 0.4 1.& 0.11.0 1.2 1.4 1.1 1.1 2.1
OUTPUT POWER \WI
TL/H/6976-5

1,21

Typical Applications

(Continued)

Amplifier with Gain = 50

Low Distortion Power Wlenbrldge .Oscillator
3ID

Yo

TUH/6976-6

TL/H/6976-7

Amplifier with Bass Booat

Square Wave Oscillator

v.

TUH/6976-8

TUH/6976-9

Frequency Response with Bass Boost
Z7
Z6
Z5
iii
:!!

z

......C
...
...~
co
>

~

Z4

J

I .

Z3
ZZ
ZI

II

",
\

~

ZO

19
18
17
20

......

50 100 ZOO 500 lk 2k

5k 10k ZOk

FREOUENCY (Hz)
TL/H/6976-10

1-22

Typical Applications

(Continued)

AM Radio Power Amplifier
Cc

FROM~
DETECTOR ..,.....,

+1
25o,.F

47

+

TO.0

5"F

In
SPEAKER

'::"

TL/H/6976-11
Note 1: Twist supply lead and supply ground very tightly.

Note 4: R 1Cl band limits Input signals.

Not. 2: Twist speaker lead and ground very tightly.

Note 5: All components must be spaced very close to IC.

Note 3: Ferrite bead is Ferroxcube KS'()OI·001/3B with 3 turns of wire.

•
1-23

!

:!i

t!lNational Semiconductor

LM388 1.SW Audio Power Amplifier
General Description
The lM388 is an audio amplifier designed for use in medium
power consumer applicatiOns: The glilin is internally set to
20 to keep external part count low, but the addition of an
external resistor and capacitor between pins 2 and 6 will
increase the gain to any value up to 200.
'
The inputs are ground referenced while the output is automatically biased to one half the supply voltage.

Features
•
•
•
•
•

Minimum external parts
Wide supply voltage range
Excellent supply rejection
Ground referenced input
Self-centering output quiescent voltage.

•
•
•
•

Variable voltage gllin
low distortion
. Fourteen pin dual-in-line package
low voltage operation, 4V

Applications
• AM-FM radio amplifiers
• Portable tape player amplifiers
• Intercoms
• TV sound systems.
• lamp drivers
• line drivers
• Ultrasonic drivers
• Small servo drivers
• Power converters

Equivalent Schematic and Connection Diagrams
Dual-In-Llne Package

14

15k

V.

BOOT
STRAP
9

14 Vs

BYPASS
GAIN

a.{

13
VOUT

GAIN
-INPUT

-INPUT

TL/H/7846-2

5Dk

Top View
3.4.5.
10.11.12

GNO
TL/H17846-1

1-24

Order Number LM388N-1
See NS Package Number N14A

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

Operating Temperature

15V

Package Dissipation 14-Pin DIP (Note 1)

±0.4V

Storage Temperature

150'C

Lead Temperature (Soldering, 10 sec.)

260'C

Thermal Resistance
6JC
6JA

8.3W

Input Voltage

O'Cto +70'C

Junction Temperature

30'C/W
79'C/W

-65'C to + 150'C

Electrical Characteristics TA = 25'C, (Figure 1)
Parameter

Symbol

Conditions

Min

Typ

Max

Units

12

V

23

rnA

Vs

Operating Supply Voltage
LM3B8

10

Quiescent Current
LM38B

V,N = 0
Vs = 12V

POUT

Output Power (Note 2)
LM388N-1

R1
Vs
Vs

Av

Voltage Gain

Vs
12V, f = 1 kHz
10 poF from Pins 2 to 6

BW

Bandwidth

Vs

THO

Total Harmonic Distortion

Vs
12V, RL = 80, POUT = 500 mW,
f = 1 kHz, Pins 2 and 6 Open

0.1

PSRR

Power Supply Rejection Ratio
(Note 3)

Vs = 12V, f = 1 kHz, CBYPASS = 10 poF;
Pins 2 and 6 Open, Referred to Output

50

dB

R'N

Input ReSistance

50

kO

250

nA

4
16

=
=
=
=

R2 = 1800, THO
12V, RL = BO
6V, RL = 40

=

=
=

12V, Pins 2 and 6 Open

10%
1.5
0.6

2.2
O.B

23

26
46

W
W
30

dB
dB

300

10

Input Bias Current
Vs = 12V, Pins 7 and 8 Open
IBIAS
Note 1: Pins 3, 4, 5, 10, II, 12 at 25'C. Derate at 15'C/W above 25'C case.
Note 2: The amplifier should be in high gain for full swing on higher supplies due to input voltage limHations.
Note 3: If load and bypass capacHor are returned to Vs (Figure 2), rather than ground (Figllf9 1), PSRR is Iypicaily 30 dB.

kHz
%

1

Typical Performance Characteristics
Maximum Device Dissipation vs
Ambient Temperature
10

.."

i

;:

I.
~
w

9
8
7
8
5
4
3
2

50

I I
I I

40

......
I'

STAVER y.

IN. Ill.

~ CO~~jJOll
~
FREE AIR

'".
~
i..
~

H~~~

;;;

INFINITE HEAT SINK

r-

1 ~F~"L~7aJ~
0

Power Supply Rejection Ratio
(Referred to the Output) vs
8D Frequency

Quiescent Supply Current vs
Supply Voltage

3G
ISC/W

H-c-

20

::=~

IO

./
",.

V-

:::~I-

10 20 30 40 50 6B 70 80 90 100
T. - AMBIENT TEMPERATURE rei
Nott: 2 oz. cop,.r foil, ......... PC 1totnI.

V

i

0

50

mill

~v

40

I.F.

3G

1/

II

111m

Vs -l2V
Ay -21dB '

.&,.F

1/

20

II

10

I

0
0

4

I

12

SUPPLY VOLTAGE (VI

18

28

10

108

Ii

11111

I_

FREOUENCY (HzI

TUIi17846-5

1-25

•

co
co

~

r-------------------------------------------------------------------------------------~

Typical Performance Characteristics
Peak-to-Peak Output Voltage
Swing vs ~upply Voltage

Voltage Gain vs Frequency

2Dr--;~-.--~---r~~

'-

1
.
w

~

11.

If

:a

!

~

III

co

2D

..~

I-

.

~

co

48
31

•

.!

~
"&
"~

.

~

co

..II!
c
:;!

12

II

l-

I:!

I
101,

ZO

10

l

•co
~
~"

!r;;r~
==
fc~:!:z --

1.0

lDk

IDOk

0.1

--

1.0

2D

~T:~

a

A.-Zao

r---. .:"'I-r'

~

ri-

50 loa zoo 601 1k Zk

-I-

51 10k ZDk

Device Dissipation vs
Output Power-80 Load

Z.I

1---+-+-+---1--1

1.i

I---i---t---+-~--~

I"

1.0

b .......:t---il-

\
w

~
co

a-IV

~V.~V
o

..!!

i

III"THD
LEVEL

II

"

2.5 .--.....,--........,--........,---,---,

I-

0.1

G.Ol

0.2 ~
0.1
0.18

Device Dissipation vs Output
Power-40 Load

-J

1/

u

FREDUENCY 1Hz)

/1/ ~vrZV

~

II

r-.

D.I

1M

5

~
;::

V. = lZV
RL =30
PD· 0.5W

I

FREDUENCY IHzI

~

i.c

10

OM
lk

SUPPLY VOLTAGE IVI

Distortion vs Output Power

..."

F

II

o ........--'__.....L__......__........__- '

~

i!

1110 III

II

Distortion vs Frequency

..

III

18
12

(Continued)

D.&

',' Z

POWER OUTPUT !WI

OUTPUT,POWER !WI

DUTPUT POWER !WI

Device Dissipation vs
Output Powefi-160 Load
Z.5

~v

~..

~_
D

o

JlITHD
LEVEL
IIKTH0 LEVELj

Vs-IV

1

I.D

U

OJ;

z.a

z.&

OUTPUT POWER !WI
TlIH/7846-6

Application Hints
GAIN CONTROL

output dc level may shift due to the additional dc gain. Gain
control can also be done by capacitively coupling a resistor
(or FEn from pin 6 to ground, as'in Figure 7.

To make theLM3.88 a more versatile amplifier, ~9 pins (2
and 6) are provided for gain control. With pins 2 and 6 open,
the 1.3.5 kO resistor sets the gain at 20 (26 dB). If a capacitor is put from pins 2 to 6, bypassing the 1.3.5 kO resistor,
the gain will go up to 200 (46 dB). If a resistor is placed in
series with the capacitor, the gain can be set to any value
from 20 to 200. A low frequency pole in the gain response is
caused by the capacitor working against the external resistor in series with the 1500 internal reSistor. If the capacitor
is .eliminated and a resistor connects pins 2 to 6 then the

Additional external components can be 'placed in parallel
with the internal feeSlback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 6 to 13. (paralleling the internal 15 kO resistor). For 6 dB effective bass boost: R "" 15 kO, the lowest
value for good stable operation is R = 10 kO if pin 2

1-26

Application Hints (Continued)
beta is the value required for the current in Rl and R2:

is open. If pins 2 and 6 are bypassed then R as low as 2 kO
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9 VIV.

(Rl

+ R2)

=

Po (Vs/2) - VeE
lOMAX

INPUT BIASING
The schematic shows that both inputs are biased to ground
with a 50 kO resistor . The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM388 is higher than 250 kO it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kO, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.

Good design values are VeE = 0.7V and Po = 100.
Example: 1 watt into 80 load with Vs = 12V.
10 MAX

(Rl

+ R2)

.
= ~2Po
- - = 500
mA
RL

= 100 (12/2) - 0.7) = 10600

0.5

To keep the current in R2 constant during positive swing
capacitor Ce is added. As the output swings positive Ce lifts
Rl and R2 above the supply, maintaining a constant voltage
across R2. To minimize the value of Ce, Rl = R2. The pole
due to Ce and Rl and R2 is usually set equal to the pole
due to the output coupling capacitor and the load. This
gives:

When using the LM388 with higher gains (bypassing the
1.35 kO resistor between pins 2 and 6) it is necessary to
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ,..F capacitor or a short to ground depending on the dc source resistance on the driven input.

4Cc
Cc
Ce"'-e<-

Po

25

Example: for 100 Hz pole and RL = 80; Cc = 200,..F and
Ce = 8 ,..F, if Rl is made a diode and R2 increased to give
the same current, Ce can be decreased by about a factor of
4, as in Figure 4.
For reduced component count the load can replace R1. The
value of (Rl + R2) is the same, so R2 is increased. Now Ce
is both the coupling and the bootstrapping capaCitor (see
Figure 2).

BOOTSTRAPPING
The base of the output transistor of the LM388 is brought
out to pin 9 for Bootstrapping. The output stage of the amplifier during positive swing is shown in Figure 3 with its
external circuitry.
Rl + R2 set the amount of base current available to the
output transistor. The maximum output current divided by

Typical Applications
Vo

Rl
510

Vo

TUH/7846-3

TL/H/7846-4

FIGURE 1. Load Returned to Ground
(Amplifier with Gain = 20)

FIGURE 2. Load Returned to Vs
(Amplifier with Gain = 20)

1-27

•

Typical Applications (Continued)

£

r---------~--OVs

r.

F
__...__"1",""...o Vs

TUHI78A6-7

FIGURE 3

TUHI7846-8

FIGURE 4. Amplfler with Gain =,200 and Minimum CB

v.

TO,I.F

270

+
V,N

270

22,.F

22,.F

270

+
"270

' • .o",F

10k»04.......-~

Vs

~

6V'

Vs

~

12V '

RL~

41'1

Po~

RL~

an

Po~4W

TUH17846-9

1.0W

FIGURE 5. Bridge Amp
Vi

o.l.F

T

510

27

BYPASS

2&

..

25

ii
:!!

Z4

~
w

23
Z2

c

21

"

20
II
18
17

CD

~~--...- _.......... "'~t-OVo

!:;
>

~

I
I

\

,
......

ZB

r-..

50 IIID 211D 500 Ik 2k

5k 10k 20k

FRED.UENCY (Hz)

TL/H/7846-11

TL/HI7846-10

FIGURE 6a. Amplifier with Bass Boost

1-28

FIGURE 6b. Frequency Response
with Bass Boost

Typical Applications (Continued)
Vso--4~"'----,

510

BYPASS

dh

-::: I'

2.7

TALK

TALK

------t--OOUSTEN

REMOTE

TUH/7846-12

FIGURE 7.ln~ercom

lDpF
FERRITE
BEAD

4.1

+1
25DpF

~D.lpF

8!l

SPEAKER

'::'

TLlH17846-13

FIGURE 8. AM Radio Power Amplifier
Note 1: Twist supply lead and supply ground very tightly.

Note 4: AI Cl band limits input signals.

Note 2: Twist speaker lead and ground very tightly.

Note 5: All components must be spaced very close to IC.

Nota 3: Ferrite bead is Ferroxcube K5-001·001/3B with 3 turns of wire.

1-29

II

~

~

t!lNational Semiconductor

LM389 Low Voltage Audio Power Amplifier
with NPN Transistor Array
'.
•
•
•
•

General Description
The LM389 is an array of three NPN transistors on the same
substrate with an audio power amplifier similar to the
LM386.
The amplifier inputs are ground referenced while the output
is automatically biased to one half the supply voltage. The
gain is internally set at 20 to minimize external parts, but the
addition of an external resistor and capacitor between pins
4 and 12 will increase the gain to any value up to 200.
The three transistors have high gain and excellent matching
characteristics. They are well suited to a wide variety of applications in DC through VHF systems.

Low quiescent current drain
Voltage gains from 20 to 200
Ground referenced input
Self-centering output quiescent voltage
Low distortion

Transistors
• Operation from 1 /LA to 25 rnA
• Frequency rangeJrom DC to 100 MHz
• Excellent matching

Applications
•
•
•
•
•
•
•

Features
Amplifier
• Battery operation
• Minimum external parts.
• Wide supply voltage range

AM-FM radios
Portable tape recorders
Intercoms
Toys and games
Walkie-talkies
Portable phonographs
Power converters

Equivalent Schematic and Connection Diagrams

.-----------_--_-0' v,

"

1J

-18M

TUHI7847-1

Dual-In-Llne Package
su•

•

~

~

VOUT

Va

~

m_

u

n

n

~

a

u

GAil

-III

CI

.,

II

u:

Order 'Number LM389N
See NS Package Number N18A

1-30

TLlH17847-2

Absolute Maximum Ratings
Collector to Base Voltage, VCBO
Collector to Substrate Voltage, VCIO
(Note 2)
Collector Current, Ic
Emitter Current, IE
Base Current, IB
Power Dissipation (Each Transistor) TA ,:;; + 70'C
Thermal Resistance

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
15V
Supply Voltage
Package Dissipation (Note 1)
1.S9W
±O.4V
Input Voltage
Storage Temperature
- 65'C to + 150'C
Operating Temperature
O'Cto +70'C
Junction Temperature
150'C
Lead Temperature (Soldering, 10 sec.)
260'C
12V
Collector to Emitter Voltage, VCEO

Electrical Characteristics TA =
Symbol

I

Parameter

15V
15V
25mA
25mA
5mA
150mW
24'C/W
70'C/W

°JC
OJA

25'C

I

Conditions

I Min I Typ I Max I Units

AMPLIFIER
Vs

Operating Supply Voltage

IQ

Quiescent Current

POUT

Output Power (Note 3)

Av

Voltage Gain

Vs = 6V, f = 1 kHz
10 poFfrom Pins 4 to 12

4
6

Vs = 6V, VIN = OV
THD = 10%

Vs = 6V, RL = SO
Vs = 9V,RL = 160

250

325
500

23

26
46

BW

Bandwidth

Vs = 6V, Pins 4 and 12 Open

250

THD

Total Harmonic Distortion

Vs = 6V, RL = SO, POUT = 125 mW,
f = 1 kHz, Pins 4 and 12 Open

0.2

PSRR

Power Supply Rejection Ratio

Vs = 6V, f = 1 kHz, CBYPASS = 10 poF,
Pins 4 and 12 Open, Referred to Output

RIN

Input Resistance

IBIAS

Input Bias Current

Vs = 6V, Pins 5 and 16 Open

VCEO

Collector to Emitter
Breakdown Voltage

IC = 1 mA, IB = 0

VCBO

Collector to Base
Breakdown Voltage

Ic = 10poA,IE = 0

VCIO

Collector to Substrate
Breakdown Voltage

IC = 10 poA, IE = IB = 0

VEBO

Emitter to Base
Breakdown Voltage

IE = 10 poA,lc = 0

HFE

Static Forward Current
Transfer Ratio (Static Beta)

le=10poA
Ic=1mA
Ic=10mA

30
10

12

V

12

mA
mW
mW

30

dB
dB
kHz

3.0

%

50

dB

50

kO

250

nA

12

20

V

15

40

V

15

40

V

6.4

7.1

100

100
275
275

TRANSISTORS

7.S

V

hoe

Open-Circuit Output Admittance

Ic = 1 mA, VCE = 5V, f = 1.0 kHz

20

VBE

Base to Emitter Voltage

IE = 1 mA

0.7

0.S5

V

IVBE1-VBE21

Base to Emitter Voltage Offset

IE = 1 mA

1

5

mV

VCESAT

Collector to Emitter
Saturation Voltage

Ic = 10 mA, IB = 1 mA

0.15

0.5

V

CEB

Emitter to Base Capacitance

VEB = 3V

1.5

pF

CCB

Collector to Base Capacitance

VCB = 3V

2

pF

CCI

Collector to Substrate
Capacitance

VCI = 3V

3.5

pF

hie

High Frequency Current Gain

Ic = 10 mA, VeE = 5V, f = 100 MHz

1.5

pomho

5.5

Note 1: For operation in ambient temperatures above 25'"C, the device must be derated based on a 150"C maximum junction temperature and a thermal resjstance
of 66'C/W junction

to ambient.

Note 2: The collector of each transistor is isolated from the substrate by an integral diode. Therefore, the collector voltage should remain positive with respect to
pin 17 at all times.
Note 3: If oscillation exists under some load conditions, add 2.70 and 0.05 ,...F series network from pin 1 to ground.

1-31

cnr---------------------------------------------------------------------------------~

co '

i

.....

Typical Amplifier Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output) .
vs Frequency

Quiescent Supply Current
vs Supply Voltage
10

~

-

.......

r-

5

C!.

I

9

10

11

12

10.

~

..~,.

1.8

..Ii
..!'"
'"
.:t

1.6
1.4
1.2

!!

....

10

I;

8
100

,.

111<

108k
FREQUENCV (Hzl

2.0

l

>=
to

20

'M

1.8

-4.,.00

>= D.6
1.&

.~

VVs-gV \

ll:

1.3
1.2

0.1
1.1

0.2

0.3

I
I
0.4

OUTPUT POWER (WATTSI

I

456181101112

:: ::'z 1ItIt-+tt1iltt1-+-lfH1lHlI

I f · 1kHz 1ItIt-+tt1iltt1-+-IH1lHlI

.

i

;l!

...

!

'"
50 100 210 &00 I. Zk

.11

v!

-,'2V

D.1

I

0.&

&It "k 20k

1 l-t+ttttHl---H+HIHI--If++f-IHII

oc::t:t:l:tlIllb"","",WiIIIIo",uWllJl
0.001

(Hz!

OA

1.0

Device Dllllilpation vs Output
Power-160 Load

0.5

f-::;I--' ~~CONTINUOUS
DiSSIPATION
I

0.3

D.2

~AiIM,k.

0.1
0.0'
POWER OUT (WATTSI

I

Va ...r,t 4'0ll0IST._
r.~ .,..;~
LEVEl

! D.' ~Vs-&V
1.5

~

Device Dissipation vs Output
Power-80Load

D.5

r--

i1i

o

i..'" ...

4

"

G.4
0.2

0.9

-

Distortion vs Output Power

l
i!!

I I

0.8
0.&

1.0

I
MAXIMUM
CONTINUOUS
l$$IrATION
OIST.
LEVEl
'<":nIOIST.
LEIVEl

G.4

;;

_I

FREQUE~CV

e ... - ~i..
. /I
i"""
i.. If ....V'''''W
"
./
1.1

Vs" IV
R, -8u

~

I'

10 r-"""TTI11!r"-nrrnrmr~"""11111

1.0

Device Dissipation vs Output
Power-40 Load
\

..~

::::

SUPPL V VOLTAGE (VOL TSI

POUT "'125mW
Av ;28dBtC.,12-0)

21

1.1

t-Vs=U/ ,

""'

lOOt

Distortion vs Frequency

...

I,! 1)ltJ

cJ !!~~

30

,.

-100

~

R';'~
V 8

~ ~ ....... r-

FREOUENCV (Hzl

I I I III/{

40

~

~
~~

~

Voltage Gain vs Frequency
50

10

Ie

60

;;

Peak-to-Peak Output Voltage·
Swing vs Supply Voltage

,.~
....

7

&

---

. SUPPL V VOLTAGE (VOL TSI

'"..~

.~
.:;;
....!:;
.

i2

~~ ~~::~T. r-

~l

I

I
0.1 0.2 0.3 0.4 0.& 0.& 0.1 0.8 0.1 1.0
OUTPUT POWER (WATTS)

0.1 0.2 0.3 0.4 0.5 0.60.1 0.1 U 1.1
OUTPUT POWER (WATTSI
TL/HI7847 -3

1-32

Typical Transistor Performance Characteristics
Forward Current Transfer Ratio
vs Collector Current

i
"
..5

Saturation Voltage vs
Collector Current

Open Circuit Output Admittance
vs Collector Current

!~

Z&O

SOD

Ie" lOla

;;
.!

..
.""

400

zao

w

w

C

~

.... ZOI

:li

.

I-

tOO

~
....

~

1.1

0

~

•. 1

0.01

1

10

~~~E!I~I
~

~

"$

;;

&0

O.al

0.1

COLLECTOR CURRENT (mAl

..i!i
[;l

;:;

-

o

,.

100

c

;:: 110

c

CI

i

~

150 C-

>

Tn

~

~

~

OYNAM~

300

-

10

0.1

COLLECTOR CURRENT (mAl

1.0

10.0

COLLECTOR CURRENT (..AI
TL/H17847-4

Z. Noise Voltage vs Frequency

-

~w
~
~

">
!!!
"

lZ

r

10
I

r-

..

-

..<:

~

-

Ie "HnA

..
."!!!

Ie

i l'ri,~,

11

10

/'

8

III II

1l1li

",

)

..
..."
~

u

1ft

10

100

8

~

"
I

J

7l1li

14

/'

L

388

/

ZIO

,

108

o

lZ
10

Co:.- l-""'" V

400

o

210

18

c
Ii 608

1/11<

o

FREQUENCY (Hz)

goe and Co. vs Collector
Current

&DO

o

0.1

1.,

FREQUENCY CHz}

8l1li

VCE'-SV

''''looM"z

~

'e"11jU\

o

•

~

r--Ie "10mA

10

100

-

" It
~ 14" 1\

High Frequency Current Gain
vs Collector Current

Noise Current vs Frequency

Vo.

:~~;.:~HZ

-

I
12

,'10

I

;: 16.

"~

!:i
!:
;:

lil

t

i

goe and Coe vs Collector
Current

,.. ::;..c."",

120

B

.,

~

60

~

"

40

J 20o

18

~ 16
14

/

IZ

Roo

tOO

I

10

V 1/

•

/

V

VeE =6V
':1MHz

/

.,0,214,8

10

Ie - COLLECTOR CURRENT (mAl

10.

IZ

7k

{'
I

~"

!:i
!:
~
:::;

~"

~
o

o

4

Contours of Constant Noise
Figure
ZI

I

140

~
~

o
10

Ie - COLLECTOR CURRENT (mAl

{'

2

Ie - COLLECTOR CURRENT (mA)

§
~

u

4.

.

g; Z.

...s:

51

ii:
CI

I

tE

,

700

4df=Ef'!ji

6.

[VeE! 5"2 dB
BW-2kHz

''''1 MHz

~a

'"

~H'

401
ZIa
100

""'-6 ••

I~'L'

~~

,l;:
0.1

0.3

1.0

3.0

10

Ie - COLLECTOR CURRENT (mAl

TLlHI7847-5

1-33

III

Application Hints
bypass theunusEid input, 'preventing degradation of gain
and possible instabilities. This is done with a 0.1 p,F capacitor or a short to llround depending on the dc source resist·ance of the driven input.

Gain Control
To make the LM389 a r,nore versatile amplifier, two pins (4'
and 12) are provided' for gain control. With pins 4 and 12
open, the 1.35 kO ~eslstor sets the gain at 20 (26 dB). If a
capacitor is put from ,pin 4 to 12, bypassing the 1.35 kO
resistor, the gain will go up to 200 (46 dB). If a, resistor is _
placed in, series with the capacitor, the gain can be set to
any value from 20 to 200. A low frequency pole in the gain
response is caused by the capacitor working against the
external resistor in series with the 1500 internal resistor. If
the capacitor is eliminated and a resistor connects pin 4 to
12, then the output dc level may shift due to the additional
dc gain. Gain control can also be done by capacitlvely coupling a resistor (or FET) from pin 12 to ground.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for Individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This Is done with a series RC from pin 1 to 12 (paralleling the internal 15 kO resistor). For 6 dB effective bass boost: R .. 15 kO, the lowest
value for, good stable operation is R = 10 kO if pin 4 is
open. If pins 4 and 12 are bypassed then R as low as 2 kO
can be used. This restriction is because the amplifier is only
compensated' for closed-loop gains greater than 9VIV.

Supplies and Grounds
The LM389 has excellent supply rejection and does not require a well regulated supply. However; 10 elill)inate possi,ble high frequency stability problems, the supply should be
decoupled to ground with a 0.1 p,F capacitor. The high current ground of the output transistor, pin 18, is brought out
separately from small signal, ground, pin 17. If the two
ground leads are returned separately to supply then the parasitic resistance in the power ground lead will not cause
stability problems. The parasitic resistance in the signal
ground can cause stability probillms and it should be minimized. Care should also be taken to insure that the power
dissipation does not exceed the maximum dissipation of the
package for a given temperature. There are two ways to
mute the LM389 amplifier. Shorting pin 3 to the supply voltage, or shorting pin 12 to ground will turn the amplifier off
without affecting the input signal.
Transistors
The three transistors on the LM389 are general pu~ose
devices that can be used the same as other small signal
transistors. As long as ,the 'currents and voltages are kept
within .the absolute maximuin limitations, and the collectors
are never at a negative potential with respect to pin 17,
there is no limit on the way they can be used.

Input Biasing
The schematic shows that both inputs are biased to ground
with a 50 kO resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM389 is higher than 250 kO it will contribute ve~ little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kO, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.
'

For example, the emitter-base breakdown voltage of 7.1V
can be used as a zener diode at currents from 1 p.A to
5 mAo These transistors make good LED driver devices,
VSAT is only 150 mV when sinking 10 mAo
In the linear region, these transistors have been used in AM
and FM radios, tape recorders, phonographs and many other' applications. Using the characteristic curves on noise
voltage and noise current, the level of the collector current
can be set to optimize noise performance for a given source
'impedance. Some of the circUits that have been built are
shown in Figures 1-7. This is by no means a complete list
of applications, since that is limited only by the deSigners
imagination.

When using the LM389 with higher gains (bypaSsing the
1.35 kO resistor between pins 4 and 12) it is necessa~ to

Ys

~:~

,-( H"-(~
LOCAL OSC
& MIXER

1ST
IF

'3
14

-(
15

L - -"2'N"'O-..I

DETECTOR

IF

OUTPUT AMPLIFIER & SPEAKER
TUHI7847-B

FIGURE 1. AM Radio

F34

Application Hints (Continued)

t-------~~D~k~------_t------._------_1~--------~.~.~~-------1~~--O·V

T'20,..

HEAD

])

Uk

'5k

M.C

D
Uk

'00
22k

...

All swHches in record mode

O.II2pF

Head characteristic 280 mH/300n
Uk

TL/H17847-7

FIGURE 2. Tape Recorder
+1ZV
1.30

5••

i

P."'"

••

+

"

+

II.

.10

T

4
',..

TUH17847-8

FIGURE 3. Ceramic Phono Amplifier with Tone Controls

1-35

Application Hints (Continued)
FM
DETECTOR
OUTPUT

·,zv

"
~O"PF
VOL

••
TLlHI7847 -9

FIGURE 4. FM Scanner Noise Squelch Circuit
V.
ON RATE
11-7H~

1&

./rtl

FRED
(25.-.610 ~

f~ _ _
' __

.k

O.6eR 1 Cl

TL/H17847-10

FIGURE 5. Siren
+.2V
.k

+loY

12810

5••

2.n

~O"PF

'T
(fr
1
remo 0 eq."; 2". (R + 10k)C
TL/HI7847-11

FIGURE 6. Voltage-Controlled Amplifier or Tremolo Circuit

1-36

r-------------------------------------------------------------------------,
Application Hints (Continued)

~

~

w

m

12V

v.

NC

TUH/7847-12

FIGURE 7. Noise Generator Using Zener Diode

•
1-37

!

~ ~National

Semiconductor

LM390 1W Battery Operated Audio Power Amplifier
General Description
The LM390 Power Audio Amplifier is optimized fOr 6V, 7.5V,
9V operation into low impedance loads. The Ql!in is internally set at 20 to keep the external part c~Llnt low, but the
addition of an external resistor and caPl\citor between"pinS
2 and 6 wil increase the gain to anyivalue up to 200. The
inputs are ground referenced while the output is automati'
cally biased to one half the supply voltage.
.I ',• •

.,

-,'

,>

Battery operation
1W output power
Minimum external parts
Excellent SUpply rejection
Ground referenced input

Self-centering output quiescent voltage
Variable voltage,gain
Low distortion
Fourteen pin dual-in-line package

'ArJplicat,ons
• AM-FM radio amplifiers
• Portable tape player amplifiers
•
•
•
•
•
•
, ..

Features '
•
•
•
•
•

•
•
•
,.

Intercoms
TV ,sound systems
Lamp drivers
Line drivers
Ultrasonic drivers
Small servo drivers
Power cOhverters'

Equivalent Schematic and Connection Diagrams

••

r---------------------~q~M~-1~----~-Ovs
.Ik

Dual-In-Llne Package

STRA'
I

BYPASS

'

14 Vs

13
......1M...-4I-'VIIY-+----"'·OJ".......---f--....,I------+-ci
VOUT

GAIN

-INPUT

-INPUT

""

BOOT

STRAP
+IIPUT

TL/H/7848-2
3,4,&,

ID.1I.12

'--............~--------..........--.....----.....----------......-o .NO
TlIH/7848-1

1-38

Order Number LM390N
See NS Package Number N14A

Absolute Maximum Ratings
Operating Temperature
. Junction Temperature
Lead Temperature (Soldering. 10 sec.)
Thermal Resistance
8JC
8JA

If Military/Aerospace specified devices are required.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
10V
Package Dissipation 14-Pin DIP (Note 1)
8.3W
±0.4V
Input Voltage
-6S"Cto +1SO"C
Storage Temperature

Electrical Characteristics TA =
Symbol

O"Cto +70"C
1SO"C
260"C
30"C/W
79"C/W

2S"C. (Figure 1)

Parsmeter

Conditions

Vs

Operating Supply Voltage

10

Quiescent Current

Vs = 6V. VIN = 0

Typ

Min

Max

4
10

Units

9

V

20

mA

30

dB
dB

POUT

Output Power

Vs = 6V. RL = 40. THO = 10%

0.8

1.0

Av

Voltage Gain

Vs = 6V. f = 1 kHz
10 ""F from Pin 2 to 6

23

26
46

BW

Bandwidth

Vs = 6V. Pins 2 and 6 Open

300

THO

Total Harmonic Distortion

Vs = 6V. RL = 40. POUT = SOO mW
f = 1 kHz. Pins 2 and 6 Open

0.2

PSRR

Power Supply Rejection Ratio

Vs = 6V. f = 1 kHz. CBYPASS = 10 ""F.
Pins 2 and 6 Open. Referred to Output
(Note 2)

so

dB

SO

kO

2S0

nA

Input Resistance

RIN

10

Input Bias Current

Vs = 6V. Pins 7 and 8 Open
Above 25"C case, derate at 15"C/W iunction to case, or 85'CIW Junction to ambient
Note 2: If load and bypass capacitor are retumed to Vs (FIgure 2), rather than ground (F1{JIJffJ 1). PSRR is typically 30 dB.

IBIAS

W

kHz
1

%

Note 1: Pins 3. 4, 5, 10. II, 12 at 25"C.

Typical Performance Characteristics
10

1

8

..

i

8
7

;:

6

f

iii

15
~

u

;

16

11

&

c

n •••• v·,·

r-liiI:

3
2

I-

I' ....IW
I•. ~.:~

car;

OIL

~ ......
r::,i:Jw

'IIEEAI

H;;::i.,!"~ll""::::
ICOI RFOll tp.c.IIARD)

oI

.
~.

.!

1'0..

i£!!:!!~.-

4

II!

10

0

Peak-to-Peak Output Voltage
Swing vs Supply Voltage

1

l!:

:II
c

~

..
..
>

I-

I!:

RL~-

I
I

7
RL
6
&

i.;'

-,n '7

7'~""

Z
4

5

&

....c
..

I!fI

iiii

..

5

7

&

SUPPLY VOLTAGE (V)

•

41

SUPPLY VOLTAGE (V)

I

1/

I

\I

..
..~
..
..I
.. o.z

Pa~ -'&DO'...

4.8

~

!1i

u

Ii

..

1.1

I

1-' kHz

2.D
..............

A~'ZB6
-"'1

I.,...

D••
\U

;;,I

l-

~

IIOk

FREQUENCY 1Hz)

'M

~V-~D

/'

V·
/
/

1I

I

l-

0
10k

'DDt

Distortion vs Frequency

c

tt

,..

Ik

110

'0

~ 1.0

21

III

AV-!"B

.&pF

FREQUENCY (H.)

\I

7

21

l~s=W'lI

If

0

>

, •

IpE

'I

~!!.!

311

If

40

11m lnill

J!'I~I

31

9

~~-Iq,.F

:il

I
I

I

;

IIIII

;;r

~

",

3

•

H~!

6D

Voltage Gain vs Frequency

~

RL -4n
4~ ~~.

t

./

~

10

:!!

Ih "'-:1-'"

./'"
[.;'1"

8

T. - AMBIENT TE_RATURE rCl
Nail: Zoz. copper foil._......... PC .....

I

./

12

6

...

;;r
:!!

! •z

011213041 &BH 7810 I I ' .

9

II

~

I"

'NFIIIITE HEATSII"

J J 1
111
111

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

Quiescent Supply Current vs
Supply Voltage

Maximum Device Dissipation
VB Ambient Temperature

0.1
10

&0 I .

zao

&10 lk 2k &k 10k 20k
FREQUENCY (H.)

Tl/HI7848-5

1-39

•

Typical Performance Characteristics

Device Dissipation vs
Output Power 40 Load .

Distortion vs Output power
i_t

10.•

1.2

f=1kHz

1.0

VS'SV

m 3.0 :~:~
~

"

iiI

~

0.1

1.0
0.3

!

~I::::::~~II~!DII

c

e'

0.1

1.0

Ii ...

~

(Continued)

i!!l

D.I

~ u

~"

0.2

:Device DIssipation vs
. Output Power 80 Load

nn-r--:C;;;:P"""""f":;t:"TI

V'"~'l;f'f T~b.~ ~~

1I

;f.~'fVs·1.6V,'

J~

•.1
•.6

0.5

,.~

HrJfr+I--+--1~m-,.JrTHO=lo%-

1.13 0.16 0.1

0.3

0.1 I.D

r- -

VS=9V

l .... ~

VS' 1.5V

I-'

0.4

I I

lc I

THO'3l\ ;"

-,

~-:L"

VS"IV
0.3

~ VS "6V

II

I'

I;'"

,~.1'

a.2

.
HH-+-+-+-+-+-+--+-I

0

IA

POWER OUTPUT IWI

0.8

1.2

\.6

0

2.0

,THrlr"

,

I I
I l

0.1

L-...J....L..J...u..L.w...---L--'-.J",J"Ji.J"LU

0.01

..I J.

0.8

,

0.2

0.4

0.6

0.8

I

OUTPUT POWER IWI

OUTPUT POWER IWI

TUHI7848-6

Application Hints
Gain Control
To make the LM390 a more versatile amplifier, two pins (2
and 6) are provided for gain control. With pins 2 and 6 open,
the 1.35 kO resistor sets the gain at 20 (26 dB). If a capacitor is pUt from pin 2 to 6, bypassing the 1,35 kO resistor, tlie
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capacitor, the gain can be s,et to any value from ~O
to 200. A low frequency pole in the gain response is caused
by the capacitor working against the external resistor in serillS with the 1500 internal resistor. If tlie capacitor is eliminated and a resistor connects pin 2 'to 6 then the output dc
level may shift due to the additional dc gain: Gain control
can also be done by capacitively coupling a'resistor (or
FET) from pin 6 to ground, as in Figure 7.

bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ,...F capacitor or a short to ground depending on the dc source resistance on the driven input.
Bootstrapping
The base of the output transistor of the LM390 is brought
out to pin 9 fQr Bootstrapping. The output stage of the amplifier during positiVe swing is s/1own in Figure 3 with its
external circuitry.
.
. Al+ Ai set the amount of .base current avail8.ble to the
output transistor. The maximum output current divided by
beta is the value required for the current in· A 1 and A2:
(A1 +A2) =

Input ~Iasli'l"

Po (Vs/2)

- VeE
lOMAX
Good design values are VSE = 0.7V and Po = 100.
EXlI;mple 0.8 watt into 40 load with Vs = 6V.
PO
.
lOMAX = - - = 632mA
AL

Additional external components can be placed in parallel
with the inlernal feedback resistors to tailor the gain and
frequency response forJndiVidual applications. For example,.
we can compensate· poor speaker bass response by frequenCY'shaping the. feedback path. This is done with a series AC .from pin 6 to 13 (paralleling the internal 15 kO resistor). For6 dB effectiVe basslboost: A "" 15 kO, the 10w9$t
valu~ for good stableopEiration is A = 10 kO if pin 2is
open. If pins 2 and 6 are bypassed then A as low as 2 kO
can .be used.. This r,estriCtlon is because the amplifier is 'only
compensated for cIO~ed-IOOP gains greater than 9 VIV.

/:f

(A1 + A2) = 100 (6/2) - 0.7) '=
0.632
3640
To keep the current in. A2 constant during positive swing
capacitor Cs is added. As the outpl,lt swings positive Cs lifts
AI and A2 above the supply, maintaining a consUlnt voltage
across A2. To minimize the value·of Ce, A1 = A2. The pole
due to Cs and A1 and A2 is usually set equal to the pole
dUe to the output coupling capaCitor and theioad. This
"
.
gives:

.."-

The sql1ematic shows that both inputs are biased to ground
with a 50 kO resistor. T,he base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left oPen: "If the dc source resistance drivinQ the
LM390 is higher than 250 kO it will contribute very little
additional offset (about 2.5 mV at the input, 50 O1V at t\:le
output). If the dc source resistance is less than 10 kh, then
shorting It)e unused input IQ ground will keep the offset low
(about 2.5 mV at the input 50 mV at the outputj~ For dc
source resisll!.nces between theSe values we can eliminate.
excess :Offset: by putting a resistor from the unused input to '
ground, equal in value to the dc source resistance. Of
course all offset problems are 'eliminated if the input is capacitively c o u p l e d . '

4Cc

Cc'

Cs""-""Po
25
Exampl.e: for 100 Hz pole and AI. = 40; Cc = 400 ,...F and
Cs = 16 ,...F, if A1 is made a diode and A2 increased to giVe
the same current, Cs can be decreased by about factor of
.4,. as in Rgl,fre 4.
.

a

For reduced component count the load can replace AI. The
value of (AI. + A2) is the same, so A2 is increased. Now Cs
is both the coupling and the bootstrapping capaCitor (see
Figure 2).
.

When USing the LM390 wi.th higher gains (bypassing' the
1.35 kO resisto~ ~etween pins 2 and 6) it is ne~ssaryto.

1-:40

Typical Applications
6V

6V

TLlHI7848-4

TL/HI7848-3

FIGURE 2. Load Returned to Supply
(Amplifier with Gain = 20)

FIGURE 1. Load Returned to Ground
(Amplifier with Gain = 20)

{ r.

r----.....-oVs
RI

F
_ ..._ ..._ oO Vs

14

BYPASS

.-=-dh

RZ
CB

-

Cc

I

I

7

+1·,
TLlHI7848-7

FIGURE 3

TLlHI7848-8

FIGURE 4. Amplifier with Gain = 200 and Minimum CB
BV

128

IZD

FIGURE 5. 2.5W Bridge Amplifier
1-41

TLlHI7848-9

Typical Applications (Continued)
Vs

27

.'

21

lBt1

,
z 23 , I
'c
I
Z2
25

.. iii
~

24

......
c
I-

21

>

ZO

'

4701'1'

.
J

I:'o~T·'·

.

~

\

.

/'

,

~

,

......

18
17

ZO

50 100 ZOO 500 lk Zk }k 10k 2111c

2.7

":"

.

1\ ,

FR~OUENCY

(Hz)

TUHI7848-11

':"

TUH/7848-IO

.' FIGURE 6(b). Frequency Response
with Bass Boost

FIGURE 6(a). Amplifier with Bass Boost

TALK

TALK

MASTER

REMOTE

.....----+---0 LISTEN
TUHI7848-12

FIGURE 7. Intercom
liD

Cc
FROM~

DETECTOR~

Rl

10k

,

~i~~~-'------~

...,,:

!&O"1d
F

I ..

SPEAKER

-;t:"
FIGURE 8. AM Radio Power Am~lIfler
Nota 1: Twist supply lead and supply, ground very tightly.

._

..

-

Note 4: RICI benillll(1lts input signals.
. Nota ~ All components mu~t be spaced yery close to IC.

Nota 2: Twist speaker lead and groU/1d very tightly.

Nota 3: Ferrite bead is

-

O.ljAf

F~rroxcube Ks.ool :00,/38 with 3 turns of wir!':

1·42

TLlHI7848-13

!....
CO

t!lNational Semiconductor

LM391 Audio Pow.er Driver
General Description

Features

The LM391 audio power driver is designed to drive external
power transistors in 10 to 100 watt power amplifier designs.
High power supply voltage operation and true high fidelity
performance distinguish this IC. The LM391 is internally protected for output faults and thermal overloads; .circuitry providing output transistor protection is user programmable.

•
•
•
•
•
•
•

±50V max
0.01%
3 p.V
90 dB

High Supply Voltage
Low Distortion
Low Input Noise
High Supply Rejection
Gain and Bandwidth Selectable
Dual Slope SOA Protection
Shutdown Pin

Equivalent Schematic and Connection Diagram
r---~--~----------~----------"-----------1~--~-oI&

y+

2&k

2&k

+-() 8

L...__

OUTPUT SOURCE

....--+-() 10 +1 LIMIT

~

a...._I-+--o 11 + SOA
...--------+-0 9 OUTPUT SENSE
r-...I-+--o 12 -SOA
':Io....-----+~O

13 -I LIMIT

...------...--------+-0 5

OUTPUT SIN.K

25k

21i1c

L...____~~----~~----~~--------------~~~I.

yTUH/7146-1

Dual·ln·Llne Package
y-

+IN

y+

-IN

SHUTDOWN

COMPC

-I LIMIT

RIPPLE C
SINK

-SOA DIODE

BIAS

+SOA DIODE·

BIAS

+1 LlM.IT
OUTPUT SENSE

SOURCE

TL/HI7146-2

Top View
Order Number LM391N.100
See NS Package Number N16A

1-43

Absolute Maximum Ratings

Supply Voltage
LM391N-100

Storage Temperature
Operating Temperature

±50Vor +100V

Parameter

2OOC/W
63°C/W

8JC

;;" 90%,
V+ MAXar:'ld
V- = 90% V-MAX')
.

, I/Iin

C9"dltlons
,Gurrent in Pin 15

"

Typ

Max

5

6

"

V/N = 0
V+ -7
V- ;+-7"

Positive

Output Swing

~egative

Drive Current

Solirce (Pin 8)
Sink (Pin' 5)

Noise (20 Hz-2O kHz)

Input Referred

Supply Rejection

Input Referred

Total Harmonic Distortion

f=1kHz
f=20kHz

2600C

8jA

Electrical Characteristics TA= 25"C (The following..are
,' for V+
Quiescent Current
LM391N-100

OOCto +700C

Thermal Resistance

1 mA

,

Shutdown Current (Pin 14)

-65°C to + 1500C

:l~ad Temp. (Soldering, 10sebl)

Supply Voltage less 5V

Input Voltage

. ',1.39W

Package Dissipation (Note 1)

If Milltary/Aeroapace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

V+ -5
+ 5

Units
mA
V

,V-

V

5
5

mA
mA
3

, 70

90
0.01
0.10

dB
"

0.25

%
%

Intermodulation Distortion

60 Hz, 7 kHz,4:1

0.01

%

Open Loop Gain

f=1kHz

5500

VIV

Input Bias Current
Input Offset Voltage

0.1

1.0

5

20

Positive Current limit VeE

Pin 10-9

650

Negativ!! Current Limit VeE

Pin 9-13

650

Positive Current Limit Bias CurrElnt

Pin 10:

10

100

Negative Current ,Limit Bias Currel1t

Pin 13

10

100

mV
mV
mV

Pin 14 Current Commenlll
"
Minimum pin 14 current required for shutdown is 0.5 mA, and must not exceed 1 mAo
Maximum pin 14 curreFlt for amplifier not shut down is 0.05 mAo
The typical shutdown sWitch point current is 0.2 mAo
Note 1: For operation in ambient tempe(8luresabove 2,5"C, the device must be derated based on a 15O"C maximum iunction temperature and a thermal resistance
of 90"ClW iunction to ambient.

Typical Applications

.I'"

, '.

*
y-

.7

.

.

ct..
~

+~

Tl/HI7146-3

FIGURE 1. LM391 with External Components-Protectlon Circuitry Not Shown

1-44

Typical Performance Characteristics

lao

~e

1"

.. 141
E
-a

.

•

la

Ii

I.

Ii!
I;

..

!!

/

V

./

60
41

~

I~ I'-"

.

1"

!:i
iii
~

" NEJnv~
=;
....
I:w
... "

fifii
w..

"'

!!

31

:=

Ii

"'

II

110

1.

fOk

1_

'\..
1M

11M

FREOUENCV (HERTZ!

a.5

.

Total HarmoniC Distortion VB
AB BlaB Current

0.4

f!ZI~'"

SJ..L Y
MTlfCR

11

10

50 101100 lao lk Ik 5k 10k 10k
FREOUEICY (HERTZ)

ID

,00mVESUPPL Y

:I-

4D CC-·pFWtTH
lMORESlSTOR

10
0

I I

AV'IO

OM

I

Iii

iiI

= "50

..

III

CC' 5.F

10

0.111

AV-za

Input Referred Power Supply
Rejection VB Frequency

I

"
l'

0.11

ID .. llDZIO ... lk Zk 5k 11k ZIk
FREOUEICY (HERTZ!

Open Loop Gain VB Frequency

/

~ 8.18

/

UI

.ID
.31
"0
SUPPLY VOLTAGE (VOLTS)

.10

lilI.H

J

0.114

I
I

~

!! 1.2'

1.11

...

, / RLoin

v..

Av-110 I

D.H

Av-IDIJ

=....
1.1'

V

D.3Z

I

'.1'

V

I..

I

'.11

/'

I; .11
II
I

'.11

RL-,n

121

DAD

I.ZO

I
I
I

l!' III

Total Harmonic Distortion VB
Frequency (RL = 40)

Total Harmonic Distortion VB
Frequency (RL = 8ll)

Output Power VB Supply Voltage
_

'"
I I

..THOUTCR

I I

ZI sa 101211 511 .. Zk
CR ~ Ilc FREQUENCY (HERni

'\.1"
~

.. 1.2.

.

i!!

,.'"

1.3

u~
'.1

•

I

I'-...

RL-'A

RV· n
5 10 15 II 25 31 31 41 45 18
AI BlAB CURRENT C11ILLlAMPS)

TUHI7148-4

Pin Descriptions
Pin No.

Pin Name

Comments

1
2
3
,4
5
6

+ Input
-Input
Compensation
Ripple Filter
Sink Output
BIAS
BIAS
Source Output
Output Sense
+ Current Limit
+SOADiode
-SOADiode
- Current Limit
Shutdown
V+
V-

Audio input
Feedback input
Sets the dominant pole
Improves negative supply rejection
Drives output devices and is emitter of AB bias VBE multiplier
Base of VBE multiplier
Collector of VBE multiplier
Drives output devices
Biases the IC and is used in protection circuits
Base of positive side protection circuit transistor
Diode used for dual slope SOA protection
Diode used for dual slope SOA protection
Base of negative side protection circuit transistor
Shuts off amplifier when current is pulled out of pin
Positive supply
Negative supply

7
8
9

10
11
12
13
14
15
16

1-45

•

External Components (Figure 1)
Component

Typical Value

CIN

1 :p.F

',4,

\,>,

,.

"

Comments
Input coupling capacitor sets a low·frequency pole with RII+
1

"

, fL =

2wRINQN
\

100k

Sets input impedance and DC bias to input.

Rf2

100k

Feedback resistor; for minimum Qffset volta~ at the outpUt this should be equal to RIN.

Rf1

5.1k

Feedback resistor that works with Rf2 to set the voltage ·gain.

RIN

.

Av= 1

,

,

+'~
, 1

.

Cr

10 p.F

Feedback capacitor. This reduces the gain to unity at DC fQr minimumottsSt voltage at the
output. Also sets a low frequency pole with Rf1'
"
1
fL=--2wRf1Cr

Ce.

5pF,

Compensation capacitor. Sets gain bandwidth product and a high frequency pole.
1
GBW
GBW = 2w5000Cc' fh =

Tv

Max fh for stable design :::: 500 kHz.
RA

3.9k

AB bias resistor.

RB

10k

AB bias potentiometer.Adjust to.set bias current in the output stage.

CAB

0.1 p.F

Bypass capacitor for bias. This improves high frequency distortion and transient response.

CR

5pF

Ripple capaCitor. This improves negative supply rejection at midband and high frequencies.
CR, if used, must equal Cc.

Reb

100.0

Bleed resistor. This removes~ored charge in output transistors.

Ro

2.7.0

Output compensation resi~o~. This resistor and Co compensate the output stage. This value
.
will vary slightly for different output devices.

Co

0.1,...F

Output compensation capaCitor. This works with RO to form a zero that cancels fp of the
output power transistors.
.'

RE

0.3.0

Emitter degeneration resistor. This resistor giyes thermal stability to the output stage
quiescent current. .IRC PW5 type.

RTH

39k

Shutdown resistor.' Sets the'amount of current pulled out of pin 14 during shutdown.

C2,C'2

1000pF

Compenl!ation capacitors for protection circuitry.,

XL

10n115,...H

Used to isolate capacitive loads, usually 20 turns of Wire wrapped around a 10.0, 2W resistor.

,.

.,

'"

1·46

Application Hints
To prevent thermal runaway of the AB bias current the following equation must be valid:

GENERALIZED AUDIO POWER AMP DESIGN

Givens:

Power Output

(JJA :!> Re (.BMIN + 1)
VceOMAX(K)

Load Impedance
Input Sensitivity

where:

Input Impedance

(JJA is the thermal resistance of the driver transistor, junction to ambient, in ·C/W.

Bandwidth
The power output and load impedance determine the power
supply requirements. Output signal swing and current are
found from:
VOpeak = ~2 RL Po

IOpeak =

j?
PO

--

RE is the emitter degeneration resistance in ohms.
,8min is that of the output transistor.

(1)

VCEOMAX is the highest possible value of one supply from
equation (3).

(2)

K is the temperatUre coefficient of the driver base-emitter
voltage, typically 2 mV I·C.
0

RL
Add 5 volts to the peak output swing (Vop) for transistor
voltage to get the supplies, i.e., ± (Vop + 5V) at a current
of lpeak' The regulation of the supply determines the unloaded voltage, usually about 15% higher. Supply voltage will
also rise 10% during high line conditions,
max supplies :::: ±(VOpeak

+ 5)(1 + regulation)(1.1)

Often the value of Re is to be determined and equation (5)
is rearranged to be:
R

(3)

(JJA (VceOMAX) K
,8MIN + 1

(6)

0

POMAX = 0.4 POMAX
The power diSSipation in the driver transistor is:

~ ~Po RL =

VOAMS
(4)
VIN
VINAMS
Normally the gain is set between 20 and 200; for a 25 watt,
ohm amplifier this results in a sensitivity of 710 mV and 71
mV, respectively. The higher the gain, the higher the THD,
as can be seen from the characteristics curves. Higher gain
also results in more hum and noise at the output.

(7)

J5i)AIVEA(MAX) = PoMAX
(6)
,8MIN
Heat sink requirements are found using the following formu-

a

las:
(9)
(10)

The desired input impedance is set by RIN. Very high values
can cause board layout problems and DC offsets at the output. The bandwidth requirements determine the size of Cj
and Cc as indicated in the external component listing.

o

E~

The maximum average power dissipation in each output
transistor is:

The input sensitivity and output power specs determine the
required gain.
Av

(5)

where:
TjMAX is the maximum transistor junction temperature.
T AMAX is the maximum ambient temperature.

The output transistors and drivers must have a breakdown
voltage greater than the voltage determined by equation (3).
The current gain of the drive and output device must be high
enough to supply IOpeak with 5 mA of drive from the LM391.
The power transistors must be able to diSSipate approximately 40% of the maximum output power; the drivers must
dissipate this amount divided by the current gain of the outputs. See the output transistor selection guide, Table A.

(JJA is thermal resistance junction to ambient.
(JSA is thermal resistance sink to ambient.
(J JC

is thermal reSistance junction to case.

is thermal resistance case to sink, typically 1·C/W for
most mountings.

(Jcs

II

1-47

~ r---------------------------------------------~--------------------------------------.

~
:IE

....

Application Hints (Continued)
PROTECTlOI+CIRCUITRY "

':,':;

,

The protection circuits of the LM391 are very flexible and
should be tailored to the output transistor's safe operating
area. The protection V-I·charaCteristics, circuitry, and resistor formulas are described below. The diodes from the output to each supply prevent the output voltage from exceeding the supplies and harming the output transistors. The output will do this if the protection Circuitry is activated While
driving an inductive load.
'" .
TURN-DN DELAY
It is otten desirable to delay the tUrn-ON' of the, power amplifier. This is easily implemented by putting a reSistor in series
with a capaCitor from pin 14 to groUnd. The value of the

.
""......"'""'"..................,

"":"

resistor is sat. to limit !~e cUrrent to, less than 1 mA ,,(the
absolute maximum). This resistor with the.capacitor gives a
time constant of RC. The tum-ON delay is app(oidmateiy'2
time constants.
Example:
Amplifier with maximum supply of 30V. like the 2OW. 80
example in the data sheet. requiring a delay of 1 second.
Time delay =. 2RC' •

MaxV+

R=-1 rnA
So:
R = 30k. Solving for C gives 16.7 ,.F. Use C = 20 ,.F with
a30Vrating.

Prptectlo,", Circuitry with ,External Co",po~nts ,;

Prot4!ctlon Characteristics

",

OUT'UT

13

TUHnl46-6

ezlS FOR STABILITY .. ,880pF
'.

i

.v--....--....~..........
'TI.lHI7146-5

'Protection Circuit Resistor Fonnulas (V., = V+)
Type of Protection

RE,R'

Rt,R't

'R2,R'2

Rs.R's

Current Umit

RE =.!
IL

Not Required

Short

Not Required

Single Slope SOA
Protection

RE =.!
IL

"')
Rt=R2 (VM
- "-, -

1 kO

Not Required

Dual Slope SOA
Protection
(VB = V+)

RE =.!
IL

"')
Rt=R2 (VM
- "-, -

1 kO

R3=R2[~-1]
ILRE - '"

Note: 4> is the current limit VBE vol\dge. 650 mV. Assumptions: V+ > >
transistors.

4>. VM > > 4>. V+ is the load supply voltage. VM is the maximum rated VeE of the output

OSCILLATIONS & GROUNDING
Most power amplifiers work the first time they are turned on.
They also tend to oscillate and have excess THO. Most oscillation problems are due to inadequate supply bypassing
and/or ground loops. A 10 ,..F. 50V electrolytic on each
power supply will stop supply-related oscillations. However.
if the signal ground is used for these bypass. caps the THO
is usually excessive. The signal ground must return to the
power supply alone. as must the output load ground. All
other grounds--bypass. output R-C, protection. etc.• can tie
together and then return to supply. This ground is called
high frequency ground. On the 40W amplifier schematic all
the grounds are labeled.
Capacitive loads can cause instabilities. so they are isolated
from the amplifier with an inductor and resistor in the output
lead.

Application Hints (Continued)
TRANSIENT INTERMODULATION DISTORTION
There has been a lot of interest in recent years about transient intermodulation distortion. Matti Ctala of University of
Oulu. Oulu. Finland has published several papers on the
subject. The results of these investigations show that the
open loop pole of the power amplifier should be above 20
kHz.
To do this with the LM391 is easy. Put a 1 MO resistor from
pin 3 to the output and the open loop gain is reduced to
about 46 dB. Now the open loop. pole is at 30 kHz. The
current in this resistor causes an offset in the input stage
that can be cancelled with a resistor from pin 4 to ground.
The resistor from pin 4 to ground should be 910 kO rather
than 1 MO to insure that the shutdown circuitry will operate
correctly. The slight difference in resistors results in about
15 mV of offset. The 40W. 80 amplifier schematic shows
the hookup of these two resistors.

AB BIAS CURRENT
To reduce distortion in the output stage. all the transistors
are biased ON slightly. This results in class AB oiJ9ration
and reduces the crossover (notch) distortion of the class
stage to a low level. (see performance curve. THO vs AB
bias). The potentiometer, RB. from pins 6-7 is adjusted to
give about 25 mA of current in the output stage. This current
is usually monitored at the supply or by measuring the voltage across RE.

e

BRIDGE AMPLIFIER
A switch can be added to convert a stereo amplifer to a
single bridge amplifer. The diagram below shows where the
switch and one resistor are added. When operating in the
bridge mode the output load is connected between the two
outputs. the input is VIN #1. and VIN #2 is disconnected.

Typical Applications (Continued)
Bridge Circuit Diagram
5.1k

5.n

lOOk

lOOk

YSTEREO

I
Tl/H17146-7

Output Transistors Selection Guide
TableA.
Power
Output

.Output Transistor

Driver Transistor
PNP

NPN

PNP

NPN

20W@80
30W@40

MJE711
MJE171
043C8

MJE721
MJE181
042C8

TIP42A
2N6490

TIP41A
2N6487

40W@80
60W@40

MJE712
MJE172
043C11

MJE722
MJE182
042C11

2N5882

2N5880

1-49

II

..

~

r-------------------------------------------------------------------------------------~

Application Hints (COntinued)
A20W, a~; 30W,,4~.AMPL.IFIER

Solving for. c,:

GiY.,ens:
Rower Output

,. ,.'

"
c,~ 2'ITRf1fL = 7.~ p.F;use 1~ ,:,,'1=
,

2OWint080
,30Wint040

Input Sensitivity
Input Impedance .

Ttie recommended value for Cc is 5 pF fOr gains of 20 or
larger. This'gives a.gain-bandwidth product of S.4 MHz and
a resulting bandwidth of 320 kHz, better than required.

·1VMax
100k

B~ndWidth

The breakdown voltage requirement is set by the maximum
supply; we need a minimum'of 58V"and Will use SOV. We
must now' select a SOV power transistor With reasonable
beta at IOpeak,3.87A: The TIP42, TIP41 complementary' pair
are SOV, SOW·transistOrs with a minimum beta of 30 at 4A.
The driver transistor must supply tha base drive given 5 mA
drive from the LM391. The MJE711 , MJE721 complementary driver transistors are SOV devices with a minimum beta of
40 at 200 rnA. The 'driver transistors should be much faster
(higher tT) than the oLitput tran!!istors to insure that the R-C
on the output will prevent instability.

20 Hz-20 kHz ± 0.25 dB

Equlltions (1) and (2) give:
·20W/SO

VOP= 17.9V

lop = 2.24A

30W/40

Vop = 15.5V

lop = 3.8tA

Thei:efore the supply required is:
± 23V @ 2.24A, reducing to ...
±21V@ 3.87A
With 15% regulation and high line we get ±29V from equation (3).
' ,
'
Sensitivity and' equation (4) set minimum gain:
Av

~ 420. x 8 =

To find the heat sink required for each output transistor we
use, equations (7), (9), and, (1 0): ,
(7)
, J5D = 0.4 (30) ;= 12W

12.S5

, 1

150"C - 65"C
(JJA : : : , 2
,~7.9"C/WforTAMAX = 5~C

We will use again of 20 w,ith resulting sensitivity of S32 mY.
Letting RIN equal 100k gives tha required input Impedance.
For low DC offsets at the output we let Rf2 = 100k. Solving
for Rf1 gives:

(JSA

s; 7.9 -

(9)

2.1 - 1.0 = 4.aoC/W(10)

If both transistors are mounted on one heat sink the thermal
resistance should be halved to 2.4"C/W.

Rf2 = 100k
100k
Rf1 = 20 _ 1 = 5.2Sk; use 5.1k

The maximum average power dissipation in each driver is
found using equation (8):

J5DRIVl:R(M~X)=

The bandwidth requirement must be stated as a pole, i.e.,
the 3 dB frequency. Five times away from a pole gives 0.17
dB down, which is better than the required 0.25 dB. Therefore:

12
30 = 400 mW

Using equation (9):
(JJA';:

20
fL=S=4Hz
, fh.= 20k x 5 = 100 kHz

1-50

155 - 55
'--0:4""
=

237"C/W

Application Hints (Continued)
Since the free air thermal resistance of the MJE711,
MJE721 is 100"C/W, no heat sink is required. Using this
information and equation (6) .we can find the minimum value
of RE required to prevent thermal runaway.
R ;;, 100 (30)(0.002) - 0
E
30 + 1
- .190

The data points from the curve are:
VM = 60V, VB = 23V, IL = 3A, I~ = 7A
Using the dual slope protection formulas:
0.65
RE =
= 0.220

3

(6)

R2 = 1k

We must now use the SOA data on the TIP42, TIP41 transistors to set up the protection circuit. Below is the SOA
curve with the 40 and 80 load lines. Also shown are the
desired protection lines. Note the value of VB is equal to the
supply voltage, so we use the formulas in the table.

RI = 1k (60 0.65
- 0.65) :::: 91k
R3 = 1k

(7(0.22~~ 0.65 -

1) :::: 24k

Note that an RE of 0.220 satisfies equation (6). The final
schematic of this amplifier is below. If the output is shorted
the current will be 1.8A and VCE is 23V. Since the input is
AC, the average power is:
short
= %(1.8)(23) :::: 21W
This power is greater than was used in the heat sink calculations, so the transistors will overheat for long-duration
shorts unless a larger heat sink is used.

D.C. SOA of TIP42, TIP41
Transistors
8r-~--~--~--r-~--,

150

U~.--~IU~~Z~U~~3U~-4~U~~--~
VeE (VOLTS)
TUHI7146-8

Typical Applications (Continued)
20W-a0, 30W-40 Amplifier with 1 Second Tum-oN Delay
V+--t------------------~~_.---------_.---_e~

Uk

III
-ZI VTO -zav
v---e_---------4~----~e-----~~~~

TLlHI7146-9
• Additional protection for LM391 N; Schottky diodes and R .. 1000.

1-51

Application Hints (Continued)
A 40WISO, &OW140 AMPLIFIER "

Since,a heat sink is required on the driver; we should investigate the output stage thermal stability at the same time to
optimize the design. If we find a value of'RE that is good for
the protection circuitry, we can then use equation (5l'to find
the heat sink required for the drivers.

Given:

4OW/80

Power Output

60W/40
Input Sensitivity

1VMax

Input Impedance

Tlie SOA characteristics of the 2N5882, 2N5880 transistors
are show.n in the following curve along with a desired protection line. . .

100k
.. 20 Hz-20 kHz ± 0.25 dB

Bandwidth
Equations (1) and (2) give:
40W/80

VOPeak = 25.3Y

60W/40
VOPeak .;, 21.9V:
Therefore the. supply required is:'
± 30.3V
± 26.9V

@

@

The minimum gain from equation !4) is: .

,,\

1\

6
4

f-SOA

.

.,

~ ..-

~

V

K \

"It••

.... ~~

1

a

The input impedance and bandwidth are the same as the 20
watt amplifier so the components are the same.

Cc =

7

-

\

\.l"

'"

Av;;" 18,
We select a gain of 20; resulting sensitivity is 900 mY.

,

•~

I
=

With 15% regulation and high line we get ±38.3V using
equation (3).

RIN = 100k

II!:

JOP~k = 5.48A

3.16A, reducing to ...
5.4BA •

RI I = 5.1k

soA 2N5882, 2N5880

.',

IOPeak = 3.16A

~

"

40 LOAO

f-10LOAD .

\.~
~ IiPR

.... ,~ ~

a W H m

TECTION

~

~

H "

M "

. . 'VeE (VDL TSI

5pF

TLlHI7146-10

RI2 = 100k
Cr = 10 p.F
The maximum supplies dictate using 80V devices. The
2N5882, 2N5880 pair are 80V, 160W transistors with a minimum beta of 40 at 2A and 20 at 6A. This corresponds to a
minimum beta of 22,5 at 5.5A (Iopeak). The MJE712,
MJE722 driver pair are 80V transistors with a minimum beta
of 50 at 250 mA, This output combination guarantees IOpeak
with 5 rnA from the LM391.

The desired data pOints are:
VM

= 80V

Va

= 47V

. IL = 3A

I~

= 11A

Since the break voltage is not equal to the supply, we will
use two resistors to replace R3 and move Va.

Circuit Used
V+ .

Output transistor heat sink requirements are found using
.
equations (7), (9), and (10):

Po

= 0.4 (60) := 2,4W
• (7)
200-55
.
9JA:5:. --24-- = 6.O"C/WforTAMAX = 55·C. (9).
9SA :5:. 6.0 - 1.1 - 1.0 ';"'3.9"C/W
,

.

(10)

For both output transistors on one heat sink the thermal
resistance should be 1.9"C/W.
Now using equation (8) we find the power dissipation in the
driver:
.
_
.
24
(8)
PORIVER = 20= 1;2W
. . . 150 - 55
s: ~ = 7~C/W

TLlHI7146-11

'. ~. Thevenln Equivalent

(9)

9JA

Where: RTH VTH - V-

.TLlHI7146-12

','

1-52

R~ " R~

[-1!L
1
R~ + R~

Application Hints (Continued)
The formulas for RE, RI , and R2 do not change:
0.65
RE = 3A = 0.220

The easiest way to solve these equations is to iterate with
standard values. If we guess R; = 62k, then R~ = 47.12k;
use 47k. The Thevenin impedance comes out 26.7k, which
is close enough to 25.55k.
Now we will use equation (5) to determine the heat sinking
requirements of the drivers to insure thermal stability:

80 - 0.65
= 120k
0.65
The formula for Rs now gives RTH when the V+ in the formula becomes VB.
RI = 1k

RTH = R2

=

kR~B_

8 :5: 0.22 (20 + 1) :::: 570C/W
JA
40 (0.002)

This value is lower than we got with equation (9), so we will
use it in equation (10):
8SA:5: 57 - 6 "'- 1 = 50"C/W
(10)
This is the required heat sink for each driver. For low TIM
we add the 1 MO resistor from pin 3 to the output and a
910k resistor from pin 4 to ground. The complete schematic
is shown below.
If the output is shorted, the transistor voltage is about 28V
and the current is 5A. Therefore the average power is:

 - 1 ]

1k [11 (0.2:;- 0.65 - 1]

=

25.55k

VTH is the additional voltage added to the supply voltage to
'
get VB.
VTH = -(VB - V+) = -(47 - 30) = -17V
Now we must find R; and R~ using the Thevenin formulas.
Putting VTH, V-, and RTH into the appropriate formulas reduces to:

R~ = 0.76 R;

and

25.55k = R~

Typical Applications

(5)

short PO = %(28) 5 = 70W
This is much larger than the power used to calculate the
heat sinks and the output transistors will overheat if the output is shorted too long.

II R~

(Continued)

40W-SO, 6OW-40 Amplifier
27VT031V

+

TIO~F
120k~

-.

nn

5.lk

+

~O~F

SHUTDOWN

r--n-'5~~W
Ik

•

IRc-PW!i

120k

1N4003

12k

nn
'High Frequency Ground

47k

-27 V TO -31 V

"Input Ground

"'··Speaker Ground

TUH/7146-13

Note: All Grounds Should be Tied Together
Only at Power Supply Ground.

t Additional protection for LM391 N; Schottky diodes and R "" 1000.

1-53

.. ,-----------------------------------------------------------------------------,
~
Nat ion a I S e m ,i C .on due tor

= til

\

LM831 Low.voltage ~lJdio Power Amplifier
General Description'

Features

The LMS31 is a dual audio power amplifier optimized for
very low VOltage operation; The LMS31 has 'twa indepen~
dent amplifiers, giving stereo or higher power bridge (BTL)
operation from tw6- or three-cell power supplies.
The LMS31"uses a patented compensation technique to raduce,high-frequency radiation for optimum performance, in,
AM ,radio applications.: This compensation also results in
lower distortion and less wide-band noise.

•
•
•
•
•

The input is direct-coupled to the LM831. eliminating the
usual coupling'capacitor. Voltage gain is 'adjustable with a
single resistor.

Low voltage operation, 1.SV to 6.0V
High power, 440 mW, SO, BTL, 3V
Low AM radiation
Low noise
Low THO

Applications
•
•
•
•

Portable tape recorders
Portable radios
Headphone stereo
Portable speakers

Typical Application
Dual Amplifier with Minimum Parts

10k~

_ _ _ _ _ _ _.,

~1D!<

,J.,'

+

4~

L.!+
16
15
BYP Av

14
+IN

13
-IN

LMUI

16kQ
16kll
16k11

BOil

R,

Av

+IN

-IN

1°·1

+n
M~

TUH/6754-1
AV=46dB,BW~250

Hz 10 35 kH~,
POUT = 220 mW/Ch.RL ;" 4(l

1-54

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vs
Input Voltage, Y,N
Power Dissipation (Note 1), Po

Storage Temperature, T slg
Junction Temperature, Tj
Lead Temp. (Scldering, 10 sec.), h
Thermal Resistance
8Jc(DIP)
8JA(DIP)
8JC (SO Package)
8JA (SO Package)

7.5V
±O.4V
1.3W (M Package)
1.4W (N Package)
-40·C to + 85·C

Operating Temperature (Note 1), Topr

- 65·C to

+ 150·C
+ 150"C
+ 260"C
2rrC/W
75·C/W
20"C/W
95·C/W

Electrical Characteristics
Unless otherwise specified, T A = 25·C, Vs = 3V, f = 1 kHz, test circuit is dual or BTL amplifier with minimum parts.
Symbol

Parameter

Conditions

Vs

Operating Voltage

10

Supply Current

Y,N = 0, Dual Mode
Y,N = 0, BTL Mode

Vos

Output DC Offset

Y,N = 0, BTL Mode

R'N

Input Resistance

Av

Voltage Gain

Y,N = 2.25 mVrms , f = 1 kHz,
Dual Mode

PSRR

Supply Rejection

Vs = 3V

POD

Power Out

Vs = 3V, Rl = 40,
10% THO, Dual Mode

POOL

Power Out Low, Vs

Poe

Typ

Tested Limit

Unit (Limit)

3
3

1.8
6

V(Min)
V(Max)

5
6

10
15

mA(Max)
mA(Max)

10

50

mV(Max)

25

15
35

k(Min)
k(Max)

46

44
48

dB (Min)
dB (Max)

46

30

dB (Min)

220

150

mW(Min)

Vs = 1.8V, Rl = 40,
10% THO, Dual Mode

45

10

mW(Min)

Power Out

Vs = 3V, Rl = 80,
10% THO, BTL Mode

440

300

mW(Min)

Poel

Power Out Low, Vs

Vs = 1.8V, Rl = 80,
10% THO, BTL Mode

90

20

mW(Min)

Sep

Channel Separation

Referenced to Vo

52

40

dB (Min)

Ie

Input Bias Current

1

2

/LA (Max)

EnO

Output Noise

Wide Band (250 - 35 kHz)

250

500

/LV (Max)

THO

Distortion

Vs = 3V, Po = 50 mW,
f = 1 kHz, Dual

0.25

1

% (Max)

+ 200 mVrms @ f =

=

1 kHz

200 mVrms

Note 1: For operaHon in ambient temperatures above 25"C, the device must be derated based on a 150"C maximum junction temperatura and a thermal resistence
01 9S"C/W junction to ambient lor the M package or 9O"C/W junction to ambient lor the N peckage.

Connection Diagram
Dual-In-Une Package

BTLR
Av
+INPUT

'-'"
...!.
2.
...!. ..,

-

-INPUT

5
BOOTSTRAP -

SIGNAL GROUND
OUTPUT

..!.
.l
..!.

~
~

r- ~
13

4

,
POWER GROUND

~

~

-

utt

~

..!!
.!2.

•

BYPA$S
Av
+INPUT
-INPUT
BOOTSTRAP
POWER GROUND
OUTPUT

to!. POWER SUPPLY
TUH/6754-2

Top View
Order Number LM831M or N
See NS Package Number M16B or N16E

~
CW)

~

r-----------------------------------------------------------------------------------------------,
Typical Performance Characteristics
Supply Current vs Supply 'Voltage .

. PSRR vs Supply Voltage
80

10

:

NO SIGNAL
70

',"

BO

~L~

.

1

Ir'
r

:!!.

DUAL MODE

I

2kHz. 5 kHz

'50

I~HZ

4G
30

-

480Hz

-I/'

1UHz

200H

20
DUALMOOE
RAV"'O, c.. -o
V"'lNB - 2OGmV.M.

10

o

I-'
o

0.5

1

1.5

2 2.5 3 3.5 4
SUPPLY VOLTAGE (V)

4.5

5

5.5

D
1.5

&

Supply Current vs Temperature

2.5

3.5
4.5
SUPPLY VDLTAGE (V)

5.5

PSRR vsSupply Voltage
BO
7D

BT.L~E

V
V
~
~

r"",

OUALJOOE .

6D

'", ,

50

roo',

!

.....

Ii

""!!

4G

-

311

Tr- 4OOC

III'

I

~UAL MOOE.
F-1 kHz
VSWlNG - 2IJDmVRM.

. 10

- NOS\ONAL

o
-50

-25

25
50
TEMPERATURE

75

lOG

125

1.5

DC Output vs Supply Voltage
2.75

V

2.25

,.

~
!il

/

1.75

V

v

60

V

1kHz

iii

4G

:::

30

i

J

1110kHZ

AOGHZ

20
.

OU~LMDOE

r. CH-A TD CH-B

10

0.25

o

!

50

.'1

v..,CH-r' C~-B

0.5

5.5

70

V
1/

D.75

3
3.5
4
4.5.
SUPPLY VOLTAGE (V)

80

V

1.5
1.25

2.5

Separation vs Supply Voltage

3

2.5

GAIN_34 fB
(.... -24011: Cow-27D pF)

-;; ;"..ol ::::..,

If

Ycc=3V

GAIN-46 dB
(...... 011. C.. -O pF)

Vour- 200( mV
D D.5

1 1.5

2

2.5

3

3.5

4

4.5

5

5.5

o

6

1.5

SUPPLY VOLTAGE

2.5

3.5
4
4.5
SUPPLY VOLTAGE (V)

5.5

TUH/6754-4

1·56

Typical Performance Characteristics (Continued)
Power Output VB Supply Voltage
70

r.- t--

u

I

i

40

m

30

i!i

i

l/

.~

I

II
:~3V, '::H.ATO CH.B+l-AA-+-I!-+.II+UU---1

10

VaUT-~ mV
50 100

I

500 lK 2K
FREQUENCY (Hz)

511

10K

~

~

III

I I I

2GO

~

III

I'

'-1kHz
THO_l0%

0.01

2GK

""'"

.--r

~R'''~- t--

0.05

0.02

D~~~_~LL~~~~UW~~

20

0.1

DUAl., R,-40 I--

I;'

~

/

0.2

~

2G

,-10

1/

IG

50

BTL,

1.5

2.5

5.5

3
3.5
4
U
SUPPLY VDlYADE (VI

Power Output VB Temperature

Gain VB Frequency
10

80

75
70
65
80

!

i

55
50
45
40

GAlN-45 dB
(RAY-on, eaw- DpFl

V

35
30

1.01"1'nlln
111111

.

1111

BAI,.'':':34·.
(".-24DO,·eaw-270 pFI

25
20
15
10
5

i~.

II 111111

~

0,5

1.2

I

0,1
0.05
BTLMiIoE

o
20

50 100 2GO

YHD~rD%
0.01
-50

500 lK

2K 51( 10K 2GK 5GK lOOK
FREQUENCY (Hz)

65

.'"

i

MIt-

35

II

I\..

11111

"- "I

rmr

45
40

GAlN-40 dB
(".-2400, C.. -270 pF)

3D
25

"

2G
15

11

DUAL MODE

Vee -3V
ITl

Vee-3V, RL-40

~~~

5

o

125

'" 4B

!J!!!52 Ja I I
(",,:,,~, eaw-II

, ; 50

!

100

mil

11111 I II .

80
.

75
25
50
TEMPERATURE (OCI

50

1111

75
70
65

)

-25

Bandwidth VB BW CapaCitance

GaIn VB Frequency
80

¥Ce-IV, IIL-IO

1.02

Vee-3V
DUAL MODE

2G

50 100 200

500 11 2M

61(

o

1l1li 2GK 501 lOOK

GAlN-45dB
10·

FREQUENCY (Hzl

2D

50

100

.200

500

1000

BW CAPACITOR (pF)
TUH/6754-5

1-57

~

i

r------------------------------------------------------------------------------------------,
~"

Typical Performance Characteristics.(continued)

...I

DuatMode; RL = '4tl'Dlstortlon vs Frequency

Dual Mode,RL = 8tl Distortion vs Frequency

~

~

"

,

..

'

1

!

0.5

I

0.2

!

,~011.'.~.u

~

~1~:·"'\Ar_

~'Caw ,

0.1

,1:;

I
ro

O.~

(lIAy.2400,

DUAL MODE, R,-1Il
0.02 l~cc.1.8 TO IV '
~.TI~~I (CO,STjl
0.01
20
50 100 200
500 lK 2K
FREQUENCY (Hzl

-~:i7~,~ (C~NSn
20

200

50 100

I

500 lK
FREQUENCY (Hzl

2K

I...t"

5K 10K 20K

Distortion vs Power Output (Note 2)

"
==

BAiM'.34 4B'

0.05

.41
0.01

111·1

0.1

0.05
0.02

(RAy.OII, Caw=O pFI

,

'5

FI~

BAIN-414B

0,5 i

Caw. 278 ~I ~

m'

5K

10K

Distortion vs Power Output (Note 2)

10

,

~

10 kHz

,!

l,

0.5

,'I=
5

.'

lr;;t

0.2
0.,1

II;

0.5

=
~

0.2

~

1 kl

0.1

r- DUAL MODE

-Vee-3V, R,-41l

~ CliiRjYilOli1i
0.01
0.001 0.002 0.005 0.01 0.02 0.05 0.1
POWER OUTPUT (WATT)

0.02

0.2

0.5

1

i

~

i

O'I~I'II'II~mll~11

0.05
0.02

0.01··~~_

'0.5

1

Power Dissipation vs Power Output

iI ~111~111~1~~~1
~
0.5
0.2

n;:~;~~,o

.0:01
0.001 0.002 0.005 0.01 0.02 0.05' 0.1 0.2
POWER OUTPUT (WATTI

Power Dissipation vs Power Output

Ii!

iz,

O.OS"

0.05
0.02

-"

[

0.5
0.2
0.1
0.05.

I

0.02
0.01

0.005~
0.002
0.001 L-J...I~WIL--Ju..L.l.JJWL.""""..u..I.LIJ,IU--'-U..1
0.0010.0020.005 0.OlD.02 0.05 0.1 0.2 '0.5 t.. 2 5
POWER OUTPUT (WATTI

,. Q.OO2 '-'-"".""--' .."t-ttltIIIt-+tttlllltt-l-+H
. 0.001 ~~~~~~~~-L~UW~~WU
. 0.1101 0.0020.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2
POWER OUTPUT (WATTI
TLlH/6754-6

r-

a:
4»

Typical Performance Characteristics (Continued)
BTL Mode, RL =

...

w

ao Distortion vs Frequency

Device Dissipation vs Ambient Temperature

10
1.8
1.8

..

BAIN-4B dB
(R•• -OO. Cow-O pFI

;- 0,5

i

z

1.2

~

0.8

Iii

0.6

51

0.2

OAIN-34 dB
(ft•• -24OO. Cow-270 PF)F

0.1

i
if
e

FREEAlft

1.4

r--....

900 C/W

......

r-....

........

.......

0.05
0.4

BTL MODE. ft, _ BO
Vee-l.BTO BV

0.02

0.2

~Uli~~r~ (CO~STil
20

50

100 200
5D0 lK 2K
FREQUENCY (Hzl

5K

o

10K 2DK

Distortion vs Power Output (Note 2)

o

10

20

3D 40 50 60 70 80
AMBIENT TEMPERATURE (OCI

90

100

Supply Current vs Power Output

10

1000
500

!!

z

i

200

~H;'

:c

!.

i."

0.5

...

1kHz

0.2

f

iil

0.1

~

100
50

2D

~

10

0.D5

.!rL

BTL MODE
0.02

Vee-3V, RL-80

c.w-R.,=o

0.01
0.001 0.002

_'1 Will

0.0D5 0.01 0.02 0.05 0.1
POWER OUTPUT (WATTI

0.2

0.5

1
0.0010.0020.0050.010.020.050.1 0.2 0.5 1
POWER OUTPUT (WATT I

1

2

5 10

Power Dissipation vs Power Output
2

¥ecls!
¥ec-5

i

0.5

il!l

0.2

;

I

¥ec-4V

~

0.1

~

0.05

~z

~

II

I
THOl3~
.,.v!..2V 'IHO';'10%
V -3V

~

0.02

BTL MODE
RL-In,

'1~111~HZ

0.01
0.DD10.D02D.DDSO.Dl0.D2 O.IIS 0.1 0.2 0.5
POWER OUTPUT (WATTI

Note 2: 1 kHz curve is measured with 400 Hz-30 kHz Filter.
1

2

TLlH/6754-7

1-59

¥" ~------------------------------------------------------------------------------------,

r&

::&

Typical Applications

....I

. BTL Amplifier with Minlmu,m P!lrts

Av

+IN

L.".---...;.!.~

3

10~

..

VI~]

lOll"';"--------'
,L/H/6154~8

AV

~

52 dB, BW

POUT

f"

~

~

250 Hz to 25 kHz'

440 mW, RL

~

sn

.BTL Amplifier for HI·FI Quality
330pF

0.47,.F

an

+

. ~',

'II.
10k ~------_-!
330 pF

TUH/6754-9
AV

~

40dB,BW

POUT

~

~

20 Hz to 20 kHz

440 mW, RL

~

81l

(Dynamic Range Over SO dB)

t-60

I"'"

!....

Typical Applications (Continued)
Dual Amplifier for HI-FI Quality

~~.~
- .~
r-~~~~~~~~~~+-~-,

AV
•

+.7p

~

+IN
3

.400

.2p +

~

~':l

'~+--------'
TL/H/6754-10

Av

~

34 dB. BW

POUT

~

~

50 Hz to 20 kHz

2l!O mW ICh. RL

~

40

(Dynamic Range Over 80 dB)

Low-Cost Power Amplifier (No Bootstrap)
D.33,..

~:

~1
1 .,,,.
+

.71h

,.

15

ayp

Av

14
+IN

13
-IN

-

LMa31

12
BSP

+

3~

11~ •

aND

160,..F

Vo

FI>-

Vs

47,..1+

~

*120.

III

•
1

Av

•

+1.

3

~
lh
•

- PS(.
-IN

5

GND

;"

Vo
8

+

+
- '-0.33'"

;J;

"'"

'Ok

TLlH/6754-11

POUT

= 150mW/Ch.BW = 300 Hz to 35 kHz
BTL Mode is also possible

'For 3-cell applications. the 120k resistor should be changed to 2OK.

1·61

_

CO)

CD

~

r-------------------------------------------------------------------------~

LM831 Circuit Description

Refer to the external component diagram and equivalent ~hematic;
T~e

The power supply is applied to Pin 9 and is filtered by re!\istor R1 and capacitor CBY on Pin 16. This filtered voltage' at
Pin 16 is used to bias all of the LM831 circuits except the
power output stage. Resistor Ro generates a biasing current
that sets the output DC voltage for optimum output power
for any given supply voltage.

capapilor CNF on Pin 2 provides unity DC gain for maximum DC accuracy.
02 provides voltage gain and the rest of the devices buffer
the output load from 02'S collector.
Bootstrapping of Pin ,5 by CBS allows maximum output
Swing and improved supply rejection.

Feedback is provided to the input transistor 01 emitter lily
Rs and R7.

Rs is provided for bridge (BTL) operation.

External Component Diagram

v,.

fan

v,.

"'}--------'
TL/H/6754-12

1-62

r

3:
CO
w
....

LM831 Equivalent Schematic

(")

:::;'

n
c

::;:

BOOTSTRAP (B)

12

0,

i

BOOTSTRAP (A)

'"

"

"

""

fIJ
n

05
R2

50 n

""I

5011

j
0'
::l

VSUPPLY

350n

g

a
::::I

!
...

BTLR

~

16k

OUTPUT (B)

loot

F

1

I

~511

16k

~

15

R6

131 4
141 3
+ INPUT (B) + INPUT (A),

R7

I

r::=

~

I

~OU~:T(A)

-INPUT (B) -INPUT (A)

Ql

!R

R8
23k
11

,

POWER GROUNO (B)

24k

"

.••_9_ _~

24k

,

23k

'"

'07

SIGNAL GROUND

6

POWER GROUND (A)
TL/H/6754-13

~£8W'

II

External Components (Refer to External Component Diagram),'
Component

Comments
Required to stabilize output stage.

Co

"

"

,

'

"
Output coupling capacitors for Dual Mode. Sets a low-freqllency pole in
.,'
the frequency response:,
,
1
fL=--21TCcRL

Cc

"

·f.,',·'

"

"

i

Min

Max

Q.33 p.F

1 p.F

100 p.F

10,000 p.F

CBS

Bootstrap capacitors. Sets aiow-frequency pole in the power,BW.
Recommended value i s '
,
1
Cas = 10e2W;efLeRL
,

22 p.F or
(short Pins
'4& 12t09)

470 p.F

Cs

Supply ,bypass. Lilrger values improve low-battery performance by
reducirig supply ripple.
'
.

47,..F

10,000 ,..F

CBY

Filters the supply'for improved low-voltage operation. AlsO'sets
'
,
turn-on delay.
.,

47 p.F

470,..F

CNF

Sets a low-frequency response. Also affects turn-on delay.
,
1
fL =
'21TeCN~(RAV+ 80)

10 p.F

100 p.F

0.1,..F

1,..F

"

In BTL Mode, CNf on Pin 15 can be reduced WIthout affecting the
frequency response. However, the tUrn-on "POP" will be worsened.
CBTl

Used only in theE!ridge Mode. Connects the output of the first amplifier to
the inverting input of the other through an internal resistor. Sets a lowfrequency pole in one-half the frequ~ncy response.
"
'
"
:'
"1"
II =
,
21T-CBTLe1~k

CBW

Improves clipping waveform and sets the 'high-h-equencY bandwidth.
Works with an intemal16k resistor. (This equation applies for RAV ~ O.
For 46 dB application, see BW-CBW-curve.)
f _
1, '
H - 2-n:eCBWe16k

See table belOW

RAV

Used to reduce the gain and irnprove the distortion and Signal to noise. If
this Is desired, CBW must also be used.

See table below

,
Caw

RAY

TypicalAv

Min

Short'

46 dB
40 dB

82

34dB

240

28 dB

560

,

'

,I.

Max

Open

4700pF

100pF

4700pF

270pF

4700pF
;

500pF

•

"
"
"

{:,

1-64

..

4700pF

Printed Circuit Layout for LM831 N

(Foil Side View) Refer to External Component Diagram

A·CH INPUT

SUPPLY

TL/H/6754-14

Note: Power ground pattem should be as wide as possible. Supply bypass capacitor should be as close to the IC as possible. Output compensatibn capacitors
should also be close to the IC.

•
1·65

..... r-------------------------------------------------------------------------,
~

~ f}1Nation~1

Semiconductor

LM1875 20W Audio, PowEtr
Amplifier"
.
,

'

'

'~,

General Description'

,',

F.atures

The LM1875 is a monolithic power amplifier offering:,very
low distortion and high quality performance for consumer
audio applications.
"';'"
The LM1875 delivers 20 watts into a 40 or 80 load on
± 25V supplies. Using an 80 load lind ± 30V supplies, over ,;
3() watts of power may be delivered. The amplifier is d~
signed to operate with a minimum of external components.,
Device overload protection consists of both internal currer'lt '
limit and thermal shutdown.
The LM1875 design takes advantage of advanced circuit
techniques and processing to achieve extremely low distortion levels even at high output power levels. Other outstanding features include high gain, fast slew rate and a wide
power bandwidth, large output voltage swing, high current
capability, and a very wide supply range. The amplifier is
internally compensated and stable for gains of 10 or greater.

Connection Diagram

_, Up to 30 wattS,outputpower
_ Avo typically 90 dB
_ Low distortion: 0.015%, 1 kHz, 20 W
Wide power ~ndWidth: 70kHz
_ "Protection for i.c and DC short circuits to ground
_ Thermal protection Vlith parole cirCl,lit
_ High current Capability: 4A
"_ Wide supply range 16V.:sOV
_ 'Internal olltput pr'ptection diodes
_ 94 dB ripple rejection

Ii

- Plastic power package T0-220

Applications
_
_
_
_
_

High performance audio systems
Bridge amplifiers
Sterep"phonographs
Servo amplifiers '
Instrument systems

Typical Applications
+ Vee
C3
O. lpF

Cl

T

411-80

':"

2.2""

~N1j

1

1'M
':"

Tl/H/5030-1

Front View

Order Number LM1875T
See NS Package Number TOSB

C2

,+22""
TL/H/5030-2

1-66

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors tor availability and specifications.
Supply Voltage
60V
Input Voltage
-VEE to Vcc

Storage Temperature
Junction Temperature

-65°C to + 150"C

~
....
co
......

CI'I

150"C

Lead Temperature (Soldering. 10 seconds)
8JC
8JA

26O"C
3°C
73"C

Electrical' Characteristics
Vcc= +25V. -VEE= -25V. TAMBIENT=25°C. Rl =8n. Av=20 (26 dB). fo=1 kHz. unless otherwise specified.
Conditions

Typical

Tested Limits

Units

POUT = OW

70

100

mA

THD=1%

25

Parameter
Supply Current
Output Power (Note 1)
THD (Note 1)

POUT=20W.fo=1 kHz
POUT=20W. fo=20 kHz
POUT=20W.Rl=4n.fo=1 kHz
POUT=20W. Rl =4n. fo=20 kHz

Offset Voltage
Input Bias Current
Input Offset Current
Gain-Bandwidth Product

0.Q15
0.05
0.022
0.07

W

0.6

%
%
%
%

±1

±15

.mV

±0.2

±2

pA

0

±0.5

fo=20kHz

5.5

Open Loop Gain

DC

90

PSRR

Vcc.1 kHz. 1 Vrms
VEE. 1 kHz. 1 Vrms

95
83

Max Slew Rate

20W. 8n. 70 kHz BW

8

Current Umit ,

VOUT = VSUPPlY -10V

4

Equivalent Input Noise Voltage

RS=600n. CCIR

3

0.4

",A
MHz
dB

52
52

dB
dB

V/",s
3

A
",Vrrns

Note 1: Asslimes the use of a heat sink having a thermal resistance of I'C/W and no insulator with an ambient temperature of 25'C. Because the output limiting
circuitry has a negative temperature coefficient, the maximum output power delivered to a 40 load may be slightly reduced when the tab temperature exceeds
55'C.

Typical Applications

(Continued)
Typical Single Supply Operation
Rl
22k

4-

R2
22k

C4
Vee 0.1 pF

I
I b_.
..J;..C2
CI T'O,.F
,:k
I.OF _

"p: 1M

~~OO"F

1~5

'='
4

LMI875

---.!

/3

R7
I

•

C6

1~_

T

C5- ....
0.22 F

C3
10,.F

n'
'='

'1

R5
1l1li

'="200k
R6

+
TlIH/5030-3

1-67

Typical Performance Characteristics
THD vs Power Output
1.0

g

I
I

Pow.,r Output Vs Supply
Voit8l!e'
'

THD vs Frequency
"0.1

=l,t

35

Vs = t25V

''''

'1\ = 84
30 tHD = III

, IIJJ8
Po= 10W
IIJJ8

"

0lI7

/

gOJl6
0.1 =iii

,1\ =

i!l ::

~ ~IIL

~

:-..

RL = 411

.....
0.D2

1\=84

,

1/

./

'

,/

1

o

o

o

211 50100200iIOOlk2lc 5I<111<2IIk

100

POWER OUTPUT (W)

100
90
90

........ /

1

r.....

NEfA1IVE SUPPlY" ~

80

50

,,-

g

35

f-II--llir-f-+-+-+-+-!

~

:

l-~t'IoHt-'-T"-'F'-F,

m 211

«I

tj 151""'......a:-+"..a.~++--I
~ 10~~~~~~~~1

30 INPUT REFDIIISl'
211 Is 0
10 '1\ 4

=
=

-5h,~wtr.~~~~~~

1 Vnno

o

o~~~~~~~~~

211 50 100200 500 lk 2Ic

510152112530
SUPPlY ~TAGE (tV) ;

30

45 .--,--,--..-.,.-.,.-.,.....,....,
«I FPiL'lNf'F'N=.I1E1-'H::;:EA+f-=SINK=t"-+-+--l

1'1.6

POSIIIV£ SUPPlY

10

10 15 ~ ,25
SUPPlY VOLTAGE (tV)

Device Dissipation vs
Ambient Temperaturet

PSRR vs Frequency

100

o
o

5

FMQUENCY (Hz)

Supply Current vs Supply
Voltage

,"""

f-- 'r--j

0.01 "

'.
11'

111111"
.,.0

0.1

\..

D.03

V

o

51< 111< 2IIk

l00I2111~190

211 «I 80 90

TA - AIIBENr TEIIPERAlIJR[ ("C)

FMQUENCY (Mz), '

tcf>'NTERFACE - '"C/W"
See Application Hints,

Povier Dlstjipatlon vs
Power Output

.

50

g

~
iii
~

I

45
«I
35

30
25
211
15
10
0
0

,/ ...

--

.,

'-,

.,.q-1

_"!-

45 RL = 84

fg=lkHz

Vs = t2SV

L

30

It!

1~

~"

1\=411
fg=lkHz

10 15 211 25
POWER OUTPUT (W)

30

~

I:

Vs = t2IIV

1

'

.::- «I
~ :lii

--+---

1'" "Ys= tl~

"10

./

.~

Vs = t2IIV r--

~y's=:t;5vE I-ci

I
,,15

10

..... r--. ~

",

"'\..

i:

135
~

~+-~H*~~~~~,45

~

-5~+-~H**--r++~~'~

-60
-135
-180

-10
-15
~

1M

,ill

-6

211

25

-25-20-15-10 -5 0 5 10 15 211 25

30

OUlPllT VOLTAGE (V)

300

=~~pFl80

211

10ilc

~

~

Inp!Jt Bias Current
, vs Supply Voltage

~;:~

15

,

Vs = t25V

.,/... ......

POWER QUlPUT (W)

25

,

\

,,"-'"

Vs = t30V

o
o

30

........

..... ~

Open Loop Gain and
Phase vs Frequency

W

lOUT vs VOurCurrent LimlU
Safe Operating Area BOundary

50

---

Vs = t30V

-- --

"Power DI\SSlpation vs
Power Output

.~

10M

~7001: '"

~250 -e--~r--

;2110

"

TA

B 150
12... 100

i

........

= O'C

ro-

r- r-

50

o
o

5

10

15, 211

25

30

~~'( VOLTAGE (tV)

FREQUENCY (Hz)

TLiH/S03O-4

'Thermal shUidown with infinite heat sink
"Thermal shutdown with '"CIW heat sink

1-68

Schematic Diagram

•
1·69

U) ~--------------------------------------------------------------------------------~

....t;

:!i

Application Hints
CURRENT LIMIT AND SAFE OPERATING AREA (SOA)
PROTECTION

STABILITY
The LM1875 is designed to be stable when operated at a
closed-loop gain of 10 or greater, but, as with any other
high-current amplifier, the LM1875 can be made to oscillate
under certain conditions. These usually involve printed circuit board layout or output/input coupling.
Proper layout of the printed circuit board is very important.
While the LM1875 will be stable when installed in a bOard
similar to the ones shown in this data sheet, it is sometimes
necessary to modify the layout somewhat to suit the physical requirements of a particular application. When. designing
a different layout, it is important to return the load ground,
the output compensation ground, and the low level (feedback and input) grounds to the circuit board ground point
through separate paths. Otherwise, large currents flowing
along a ground conductor will generate voltages on the conductor which can effectively act as signals at the input, resulting in high frequency oscillation or excessive distortion.
It is advisable to keep the output compensation components and the 0.1 p.F supply decoupling capacitors as close
as possible to the LM1875 to reduce the effects of PCB
trace resistance and inductance. For the same reason, the
ground return paths for these components should be as
short as possible.
Occasionally, current in the output leads (whi,ch'function as
antennas) can be coupled through the ,air to the amplifier
input, resulting in high-frequency oscillation .. This: normally
happens when the source impedance is high or the input
leads are long. The problem can be eliminated by placing a
small capaCitor (on the order of 50 pF to 500 pF) across the
circuit input.
,

A power amplifier's output transistors can be damaged by
excessive applied voltage, current flow, or power dissipation. The voltage applied to the amplifier is limited by the
design of the external power supply, while the maximum
current, passed by the output devices is usually limited by
internal circuitry to some fixed value. Short-term power dissipation IS usually not limited in monolithiC audio power amplifiers, and thiS can be a problem when driving reactive
loads, Which may draw large currents while high voltages
appear on the output transistors. The LM1875 not only limits
current to around 4A, but also reduces the value of the limit
current when an output transistor has a high voltage across
it.
When driving' nonlinear reactiVe loads such as motors or
loudspeakers with built-in protection relays, there is a possibility that an amplifier output will be connected to a load
whose terminal voltage may attempt to swing beyond the
power supply voltages applied to the amplifier. This can
cause degradation of the output transistors or catastrophic
failure of the whole circuit. The standard protection for this
type of failure m~hanlsm is a pair of diodes connected be, tween the output of the amplifier and the supply rails. These
are part of the. internal circuitry of the LM 1875, and needn't
be added externally When standard reactive loads are driven.

THERMAL PROTECTION
The LM1875 has a sophisticated thermal protection scheme
to prevent long-term thermal stress to the device. When the
temperature on the die reaches 170"C, the LM1875 shuts
down. It' starts operating again when the die temperature
drops to about 145"C, but if the temperature again begins to
rise, shutdown will occur at only 150"C. Therefore, the device is allowed to heat up to a, relatively high temperature if
the fault cor'ldition is temporary, but a sustained fault will
limit the maximum die temperature to a lower value. This
greatly reduCes the stresses imposed on the IC by thermal
cycling, which in tum improves its reliability under sustained
fault conditions.

Most power amplifiers do not drive highly capacitive loads
well, and the LM1875 is no exception. If the output of the
LM1875 is connected directly to a capacitor with no series
resistance, the square wave response will exhibit ringing if
the capaCitance is greater than about 0.1 p.F. The amplifier
can typically drive load capacitances liP to 2 p.F or so without OSCillating, but this is not recommsn<\ed. If highly capacitive loads are expected, a resistor (at least .10) should be
placed in series with the output of the LM1875. A method
commonly employed to protect amplifiers from low impedances at high frequencies is to couple' to the load through a
100 resistor in parallel with a 5 p.H inductor.

.Since the die temperature is directly dependent upon the
heat sink, the heat sink should be chosen for thermal resistance low enough that. thermal shutdown will not be reached
during normal operation. Using the best heat sink possible
within the cost and space constraints of the system will improve' the long-term reliability of any power semiconductor
device.

DISTORTION
The preceding suggestions regarding circuit board gro,unding techniques will also help to prevent excessive distortiqn
levels in audio applications. For low THO, it is also necessary to keep the power supply traces and wires separated
from the traces and wires connected to the inputs· of the
LM1875. This prevents the power, sup!'ly currents,' which
are large and nonlinear, from inductively coupling to the
LM1875 inputs. Power supply wireS should be'twisted together and separated from the circuit board. Where these
wires are soldered to the board, they should be perpendicular to the plane of the board at least to a distance of a
couple of inches. With a proper physical layout, THO lellels
at 20 kHz with 10W output to an 80 load should be less
than 0.05%, and less than 0.02% at 1 kHz.

POWER DISSIPATION AND HEAT SINKING
The LM1875 must always be operated with a heat sink,
even when it is not required to drive a load. The maximum
idling current of the device is 100 rnA, so that on a 60V
power supply:an unloaded LM1875 must dissipate 6W of
power. The 54°C/W junction-to-ambient thermal resistance
of a TO-220 package would cause the die temperature to
rise 324°C above ambient, so the thermal protection circuitry will shut the amplifier down if operation without a heat
sink is attempted.

1-70

Application Hints (Continued)

,

In order to determine the appropriate heat sink for a given
application, the power dissipation of the LM1875 in that application must be known. When the load is resistive, the
maximum average power that the IC will be required to dissipate is approximately:

If a mica insulator is used, the thermal resistance will be
about 1.6°C/W lubricated and 3.4°C/W dry. For this example, we assume a lubricated mica insulator between the
LM1875 and the heat sink. The heat sink thermal resistance
must then be less than
4.2°C/W - 'Z'C/W -1.6°C/W = O.6°C/W.

VS2
PO(MAX):::: 2'/T 2RL + Po

This is a rather large heat sink and may not be practical iii
some applications. If a smaller heat sink is required for reasons of size or cost, there are two alternatives. The maximum ambient operating temperature can be reduced to
50"C (12'Z'F), resulting in a 1.6"C/W heat sink, or the heat
sink can be isola~d from the chassis so the mica washer is
not needed. This will change the required heat sink to a
1.'Z'C/W unit if the case-to-heat-sink interface is lubricated.

where Vs is the total power supply voltage across the
LM1875, RL is the load resistance, and Po is the quiescent
power dissipation of the amplifier. The above equation is
only an approximation which assumes an "ideal" class B
output stage and constant power dissipation In all other
parts of the circuit. The curves of "Power Dissipation VII
Power Output" give a better representation of the behavior
of the LM1875 with various power supply voltages and resistive loads. As an example, if the LM1875 is operated on a
50V power supply with a resistive load of 80, it can develop
up to 19W of internal power diSSipation. If the die temperature is to remain below 150"C for ambient temperatures up
to 70"C, the total junction-to-ambient thermal resistance
must be less than
150"C - 70"C
19W

Note: When using a single supply, maximum transfer of heat away from the
LM1875 can be achieved by mountiilg the device directly to the heat
sinJc (tab is at ground potential); this avoids tho use of a mica or other
type insulator.

The thermal requirements can become more difficult when
an amplifier is driving a reactive load. For a given magnitude
of load impedance, a higher degree of reactance will cause
a higher level of power dissipation within the amplifier. As a
general rule, the power dissipation of an amplifier driving a
60" reactive load (usually considered to be a worst-case
loudspeaker load) will be roughly that of the same amplifier
driving the resistive part of that load. For example, a loudspeaker may at some frequency have an impedance with a
magnitude of 80 and a phase angle of 60". The real part of
this load will then be 40, and the amplifier power dissipation
will roughly follow the curve of power dissipation with a 40
load.

4.'Z'C/W.

Using 8Jc='Z'C/W, the sum of the case-to-heat-sink interface thermal resistance and the heat-sink-to-ambient thermal resistance must be less than 2.'Z'C/W. The case-toheat-sink thermal resistance of the TO-220 package varies
with the mounting method used. A metal-to-metal interface
will be about 1°C/W if lubricated, and about 1.'Z'C/W if dry.

Component Layouts
SplHSupply

Single Supply

III
GND

GNO

Tl/H/S03O-7

TL/H/5030-6

1-71

Ie

~ tfI~atio~al

PRELIMINARY

Semiconductor

LM1876 Overture'rM A~diopowerAmplifierSeries
D,ua120W Audio Power. Amplifier
with Mute and Stand,by Modes
General Description

Key.Specificatio.ns

The LM1876 is a stereo au~io amplifier capable of delivering tYpically 20W per channel of'coritinuQus average butput
power into'a 40. or 80. load With lass than 0.1 % (THO + N).
Each amplifier has an ind9P,El:ndent smooth transition fadein/out mute and a powerq<;lnserving standby mode which
can be controlled by external logic.
The performance of the LM1876, utilizing its Self Peak Instantaneous Temperature ("Ke) (SPiKe™) Protection Circuitry, places it in a class above discrete. and hybrid amplifi- .
ers by providing an inherently, dynamically protected Safe
Operating Area (SOA). SPiKe· Protection m$8ns that these
parts are safeguarded at the output against overvoltage, undervoltage, overloads, including thermal runaway and instantaneous temperature peaks.

• THO+Nat1 kHzal.2x15Wcontinuousaverage
output power into 40. or 80
0.1 % (max)
• THO+N at 1 kHz at continuous average
output ,power of 2 x 20W into 80.
0.009% (typ)
4.2 mA (typ)
• Standby current

Features
•
•
•
•
•

SPiKe Protection
Minimal amount of external components necessary
Quiet fade-in/out mute mode
Standby-mode
Isolated 15-lead TO-220 package

Applications
• High-end stereo TVs
• Component stereo
• Compact stereo

Typical Application

Connection Diagram
Vee

Isolated PlastiC Package
Vcc B

2(15)

Standby B

Audio

Input

3(1)

CD
,.....

Standby A
+ In II

OUTPUT

Rt.
400r80

Cs

E

CD

+ In B
- In B
Mute B

VEE

o

.....

:E
..J

GNO B

'- In Ii.
Mule A
GNO A
VEE

Oul A

R;

Vee A

20kO

Oul B

lkO

TUH/12072-2

Top View

'Co
10J.'

FI
TUH/12072-1

FIGURE 1. Typical Audio Amplifier Application Circuit
Note: Numbers in parentheses represent pinout for amplifier B.
'OptIonal component dependent upon specific design requirements.

1-72

Order Number LM1876TF
See NS Package Number TF15B

,-------------------------------------------------------------------------,
I!J1National Semiconductor

~

...!!3
iii:

......

LM 1877 Dual Audio Power Amplifier
•
•
•
•
•

General Description
The LM1877 is a monolithic dual power amplifier designed
to deliver 2W/channel continuous into 80 loads. The
LM1877 is designed to operate with a low number of external components, and still provide flexibility for use in stereo
phonographs, tape recorders and AM-FM stereo receivers,
etc. Each power amplifier is biased from a common internal
regulator to provide high power supply rejection, and output
point centering. The LM1877 is internally compensated
for all gains greater than 10.

Wide supply range, 6V-24V
Very low cross-over distortion
Low audio band noise
AC short circuit protected
Internal thermal shutdown

Applications
•
•
•
•
•
•
•

a

Features
• 2WIchannel
• -65 dB ripple rejection, output referred
• - 65 dB channel separation, output referred

Multi-channel audio systems
Stereo phonographs
Tape recorders and players
AM-FM radio receivers
Servo amplifiers
Intercom systems
Automotive products

Connection Diagram
Dual-In-Llne Package
or Surface Mount Package
liAS
OUTPUT 1

OND

Order Number LM1877M-9 or LM1877N-9
See NS Package Number M14B or N14A

aND
aiD

INPUT 1
FEEDBACK 1

TLlH17913-1

Top View

Equivalent Schematic Diagram

II

..
..
,
-FEEDBACK 1

•

"

-FEEDBACK2

...PUTl

1-73

TLlH/7913-2

Absolute Maximum Ratings
Lead Temperature
N-Package Soldering (10 sec.)
M-Package Infared (15 sec.)
M-Package VaPor Phase (60 sec.)

It Military/Aerospace specified devices are reqUired,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Junction Temperature

2~V.

±d.7V

.'

O'Cto '+70"C

'.

-65'Cto

+150'C

Thermal Resistance
9JC (N-Package)
9JA (N-Package)
9JC (M-Package)

iii"~\.

260"C
220"C
215'C
30"C/W
79"C/W
2,C/W
114'C/W

"~I,

.9~A (~-PackagE!l)

15O'C

Electrical Characteristics
Vs = 20V, TA = 25'C, (See Note 1)'flL'''' 80, Av ;:' .·fiO (34, dB) unless other:wise specified
Parameter

Conditions

Total Supply Current

Po= OW

Output Power
LM1877

THO = 10%
Vs = 20V, RL = 80,
Vs =. ·12V, RL = 80

Total Harmonic Distortion
LM1877

Min

25

50,

mA

1.3

W/Ch
W/Ch

Po = 50 mW/Channel

0.075

%

Po = 500 mW/Channel

0.045

%

Po = 1 W/Channel

0.055

%

Vs -6

Vp-p

-70

dB

-60

dB

,

"

f = 1 kHz, Vs = 14V

",

Channel Separation

CF = 50 ILF, CIN = 0.1 ILF,
f = 1 kHz, Output Referred
-50

Vs = 20V, Vo = 4 Vrms
Vs = 7V. Vo = 0.5 Vrms
CF = 50 ILF, CIN = 0.1 ILF,
f = 120 Hz, Output Referred

-50

Vs = 20V, VRIPPLE = 1 Vrms
Vs = 7V, VRIPPLE = 0.5 Vrms

-65

dB

-40

dB

2.5,

ILV

0.80

mV

70

dB

15

mV

Equivalent Input Noise
RS = 0, CIN = 0.1 ILF,
BW = 20 Hz-20 kHz, Output Noise Wideband

,

Rs = O,CN = 0.1 ILF,Av2OO
Open Loop Gain

Units

2.0

RL=80

Noise

Max

'.

Output Swing

PSRR Power Supply
Rejection Ratio

Typ

Rs ="0, f = 100 kHz, Ri:. = 80

Input Offset Voltage
"

Input Bias Current
Input Impedance

Open Loop

DC Output.Level

Vs =,20V

9

50

nA

4

MO

10

11

V

Slew Rate

2.0

VlILS

Power Bandwidth

65

kHz

Current Limit

1.0

A

Note 1: For ope'!lJic>n at ambient terl1fJ!'rature. greater than 25"0, the LM1877 must"'! derated based on a maxi~um 150"0 junction temperature.

.
"

::.

i

.;;

.1-74

r-

....
CD

I:

Typical Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output) va
Frequency

Device Dlaalpatlon va
Ambient Temperature

....

IZ.D

f,...... ,

.•

i

....

U

I ...
...

......

lU

-

I.D

i~.;":.:

rl""'

rl

~

5

Z.D

"""F~!!!;III

11

j

:u:- =,
:-.::-

,- ...
~

,',,~

II Z i l l a

.

1-1M'ffIII1-H+

;

4G

i..

31

Channel Separation (Referred
to the Output) va Frequency

IDIIEtd-!.

I

"i..

I

~~tRI~LE,'1
~~
VRIPPLE·1.3 V_
V~I...i.E""IV~

-

II

IZ

14

a

L.L.JWJJII~.1WI....u.LIIIII....u

II

II

101

Average Supply Current va
POUT

III

iiil

qo

iI

It

Ilk

"

/

\:
c

" ......

I

G.I

...
i

...~
..

..
i

1.01
10

III

It

lit

zzv

i~4V ".

L-4I!1TLo f'/ T '
31"HO

"/I1ZV'"
a

•

a

.....
~

101

Ilk

Ik

IIIk

II

"I

UI

IIIk

II

101

IkIlk
FREDUENCY (1111

I'"

Output Swing va Supply
Voltage

VS'ZIV
RL'1Il

u

..

BO

I
i

....

a

....

~

ZI

101

It

V

IZ

l

....

•
PllWER OUTPUT (WICHANNELI

~

Ilii; I~

II

3

!

1"1

c~~I~.F

Open Loop Gain va
Frequency
III

~

IC:?lil:-I iF

FREDUENCY (HzI

lit - In

IIV

a.

Ii

Ic

"I

Power Dissipation (W)
Both Ch8nnels Operating

v.

~I('"

Ii

U

I

I

VO·_IIIV,.

•

POWER OUTPUT IW/CHAN.ELI

t.-' .....ZIV

cay'.· ... F
VCC'1¥

11

II

g

~!!
c

I
•

Channel Separation (Referred
to the Output) va Frequency

Total Harmonic Distortion
va Frequency

II

I•

lit

It
FREDUENCY (1111

Total Harmonic Distortion
va Frequency

.•

5. ZDI

11111111 I

FREDUENCY (Hz!

Ii
~

10

4G

IlIIt

i

.!

i..

i"iiTiiIll .L

S.F

FREDUENCY (H.I

IUPPLYVOLTABE M

.."

!caYPAlS' !oF

I.

"YPAII' •
C.. • ..I,;F
_
VRIPPLE • I V_
"IZlIII
AV'"

I

I

..

II

II

•

.r.

FREDUENCY (l1li

Power Supply Rejection Ratio
(Referred to the Output) va
Supply Voltage

/.

'/

18

50 1110 II

.....
.....

VRWPLE·IV...
1:•• • . . .7p.F
AV'"

III""

a

TA - . .IIEIT T_ERATURE rCI

r

IJ
II

ZI la~

I

~++IHIfI--l+

II

11

I=: •50

.. I-I4-lMI-I'I-ti'

i:
i

t'''',·· j'

II

i·
•

Power Supply Rejection Ratio
(Referred to the Output) va
Frequency

11k

lOOk

FREDUENCY (l1li

..

III

,V

"

t'

,4

a

/

I'
a

II

II

ZD

ZI

SUPPLY VOLTAGE IVI
TL/H17913-3

1-75

•

Typical Applications
Stereo Phonoqraph Amplifier with Bass Tone Control

+
IOhF
."'T'"
.. ;..;&..

510k

~.

}

,

,"

+)
500I'F

~Il ~~}r

2.7n
.'.

I ..
I
_.
I '. -,.......-t--...,
I

STEREO
CERAMIC
CARTRIDGE

T

-

. In

0.1 I'F

-'

I

I
I

.

~.

rQT

'Jf

,

':'"

~
":"'

51.

I.

+ ,
.

. ·188"F·

..T
.. '
~

,'

.
TL/H17913-4

, i.'.

Inverting Unity Gain Amplifier

Frequency Respori.eof Bass Tone cOiltrol .
ii

...

:!!
co
II:

i

e...

85
56

...

'45

:

3&

.TONE.~

CONTROL FLAT'

...==
§:

2&
1&

1/

~

:i
:::

Vs

MAXIMUM

F ~ BOOST
- ~ESPONSE

[)o

."

.~,

~AXIMUM

.

CUT
. RESPONSE

1 1 1.
20 &0188288 . . .

n

'.1

IilclllkU.·

FREQUEilcy (Hz)
.TLlHI7913-5

1-76

Typical Applications (Continued)
Stereo Amplifier with Ay = 200

!·'I
F

Un

.

RL
lu

TO.

1 "F ":"

I3,4,5, -~
I
~A8GND

I

lOOk

51.

+
TIO'F
TUH/791S-7

Non-Inverting Amplifier Using Spilt Supply
Zk

+
~5'F

Typical SpI" Supply

1II1II

Y+jj~
D,I.F '::'

r
-11

14

--,

I

TUHI791S-9

llIIIk

TUHI791S-8

1-77

•

U)

Vi
~

i~

r--------------------------------------------------------------------------------,

tJ1

Nat ion a I S em i c ~n due t,~, r

LM1896/LM2896 Dual Audio Power Amplifier
'Features

General Description
The LM1896 is a high performance 6V stereo power amplifier designed to deliver 1 watt/channel into 40 or 2 watts
bridged monaural into 80. Utilizing a unique patented compensation scheme, the LM1896 is ide~ for senSitive AM
radio applications. This new circuit technique exhibits lower
wideband noise, lower distortion, and leSs AM racliation than
conventional designs. The amplifier's wide supply range
(3V-9V) is ideal for battery operation. For higher supplies
(Vs> 9V) the LM2896 is available in an 11-leadsingle-inline package. The LM2896 package has been redesigned,
resulting in the slightly degraded thermal characteristics
shown in the figure Device Dissipation vs Ambient Temperature.
'

•
•
•
•
•
•
•
•
•

Low AM radiation
Low noise
3V, 40, stereo Po = 250 mW
Wide supply operation 3V -15V (LM2896)
Low distortion
No torn on "pop"
Adjustable voltage gain and bandwidth
Smooth waveform~lippinl!
Po = 9W I:!ridged, LM28S6

Applications
• Compact AM-FM radios
.' StereO tape recorders and players
• High power portable stereos

Typical Applications
.-:-....- -.....ob 

;

,:,,"

RIl' ,

T
Figure 4~ Brldg~ Ampll~ler Connection

C13
TLlHI7920~10

Printed Ci~cuit Layout
less'tlian 50 kO to prevent an input-output oscillation. This
oscillation is dependent on the gain and the proximity of the
bridge elements Rs and Cs to the (+) input. If the bridge
mode is not used. do not insert Rs. Cs into the PCB.
To wire the amplifer into the bridge configuration. short the
capacitor on pin 7 (pin 1 of the LM1896) to ground. Connect
together the nodes labeled BRIDGE and drive the capacitor
connected to pin 5 (pin 14 ofthe LM1896) ..

Printed Circuit Board Layout
FlfJure 5 and Figure 6 show printed circuit board layouts for
the LM1896 and LM2896. The circuits are wired as stereo
amplifiers. The signal' source ground should return to the
input ground shown 'on, the boards: Returning the loads to
power supply ground thro,ugh a separate wire will keep the
THO at its lowest value. The'inputs should be terminated in

"

~

,

COMPONENT SIDE

FIGURE 5_ Printed Circuit Board Layout for the LMI896
1-84

TLlHI7920-11

Printed Circuit Layout (Continued)

VIN!
BRIDGE
INPUT

INPUT
GROUND

COMPONENT SIDE
TL/H17920-12

FIGURE 6. Printed Circuit Board Layout for the LM2896

1-85

d
....-~ pNational

.PRELIMINARY

Semiconductor

LM4700 Overture~ Audio Power Amplifier Series
30W Audio Power Amplifier with
Mute and Standby Modes, .
General Description

Key Spec,ifications

The LM4700 is an audio power amplifier capable of delivering typically 30W of continuous average output power into
an 80 load with less than 0.8% (THO + N) from 20 Hz to
20 kHz.
The LM4700 has an independent smooth transition .fade-inl
out mute and a power conserving standby mode which can
be controlled by external logic.
The performance of the LM4700, utilizing its Self Peak Instantaneous Temperature ("Ke) (SPiKe™) Protection Gircuitry, places it in a class above discrete and hybrid amplifiers by providing an inherently, dynamically protected Safe
Operating Area (SOA). SPiKe Protection ll1eans that these
parts are completely safeguarded at the output against
overvoltage, undervoltage, overloads, including thermal runaway and instantaneous temperature peaks.

• Typical THO.+ N from 20 Hz to 20 kHz
at 30W of continuous average output
power into 80
.
• THO + N at 1 kHz at continuous
average OIJtput power of 25W into 80
.. THO+ Nat 1 kHz at a continuous
. average output power of 30W into 80

0.08% (typ)
0.1% (max)
0.009% (typ)

Features
•
•
•
•
•

SPIKe Protection
Minimal amount of external components necessary
Quiet fade-in/out mute function
Power conserving standby-mode
ii-lead TO:220 isolated package

.Applications
• Component stereo
• Compact stereo

Typical Application

Connection Diagram
Plastic Package
11
10

I.
AUDIO
INPUT

(C>t--¥Ofy---1

9

V,N -

7

MUTE
GND

a

o

OUTPUT

\
an

STANDBY
V,N +

6
5

Ne
Ne

4

VEE
OUTPUT

3
2

Ne

1

Vee
TUH/12369-2

Top VIew
20 kn

RSN

Order Number LM4700TF
See NS Package Number TF11 B

4.7n

CsN
IO.ljLF
TL/H/12369-1

FIGURE 1. TypIcal AudIo Amplifier ApplicatIon CIrcuIt

1-86

t!lNational Semiconductor
LM2876 Overture™ Audio Power Amplifier Series
High-Performance 40W Audio Power Amplifier w/Mute
General Description

Features

The LM2876 is a high-performance audio power amplifier
capable of delivering 40W of continuous average power to
an 80 load with 0.1 % (THO + N) from 20 Hz-20 kHz.

•
•
•
•
•

The performance of the LM2876, utilizing its Self Peak Instantaneous Temperature ("Ke) (SPIKe™) Protection Circuitry, puts it in a class above discrete and hybrid amplifiers
by providing an inherently, dynamically protected Safe Operating Area (SOA). SPIKe Protection means that these
parts are completely safeguarded at the output against
overvoltage, undervoltage, overloads, including shorts to
the supplies, thermal runaway, and instantaneous temperature peaks.
The LM2876 maintains an excellent Signal-to-Noise Ratio of
greater than 95 dB(min) with a typical low noise floor of
2.0 ",V. It exhibits extremely low (THO + N) values of
0.06% at the rated output into the rated load over the audio
spectrum, and provides excellent linearity with an IMO
(SMPTE) typical rating of 0.004%.
.

40W continuous average output power into 80
75W instantaneous peak output power capability
Signal-to-Noise Ratio :;, 95 dB (min)
An input mute function
Output protection from a short to ground or to the
supplies via internal current limiting circuitry
• Output over-voltage protection against transients from
.
inductive loads
• Supply under-voltage protection, not allowing internal
biasing to occur when IVEEI + IVeel ,;; 12V, thus eliminating tum-on and tum-off transients
• 11-lead TO-220 package

Applications
•
•
•
•
•

Component stereo
Compact stereo
Self-powered speakers
Surround-sound amplifiers
High-end stereo TVs

Typical Application

Connection Diagram
Plastic Package (Note 8)

V+

:-t

11
10

+ Cs

INPUT

Rg 1 kn

I

CO
.....

0

10knl

GND

CD
N

:E

-I

Ne
VIN +
VIN MUTE

4

HC
NCW
VOUTPUT
NC
V+
TLlH/II775-2

Top View
Order Number LM2876T
orLM2876TF
See NS PaCkage Number TA 11B for
Staggered Lead Non-Isolated
PackageorTF11B" for
Staggered Lead Isolated Package
tConnect Pin 5 to V + for Compatibility with LM38B6.
"Preliminary: Call your local National sales rep. or
distributor for availability.
TLlH/II775-1

FIGURE 1. Typical Audio Amplifier Application Circuit
"Optional components dependent upon specific design requirements. Re1er 10 the ExtemaJ Components Description section for a component functional descripllon.

1-87

•

Absolute Maximum Ratings (Notes 1. 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
72V
Supply Voltage Iv+ 1+ lv-I (No Signal)
Supply Voltage Iv+I+lv-1 (Input Signal)
70V
Common Mode Input Voltage
(V+ or V-') and
Iv+1 + Iv'-I ::;; 60V
Differential Input Voltage
60V
Output Current
Power Dissipation (Note 3)

Internally Limited

ESD Susceptibility (Not~4)
Junction Temperature (Note 5)
Soldering Information
T Package (10 seponds)

125,W
30nOV

-'40"C to + 15O"C

storage Temperature
Thermal Resistance
8JC
8JA

,
,Operating Ratings (Notes 1 !!nd2)
'

"

l°C/W
,43"C/W

"

' Temperature Range
-20°C::;; TA ::;; +85°C
,TMIN::;; TA::;; TMAX
SupplyVoltagelV+1 +IV~I
20Vto60V
: NOla: Operation is guaranteed up to SOV, however, distortion may be intra,duced from SPIKe Protection Circuitry W proper thermal considerationa are not taken into 8CCQUnt. F!efer to the Thermal Conslders.>

150"C

tions section for more Information.
(See SPIKe Protection,Response)

26O"C

Electrical Characteristics (Notes 1. 2) T~efOIlOvvingspecificationsapPIYfOrv+

= +30V. V- =

-30V~ IMUTE

= -0.5 mA with RL = 80 unless otherwise specified. Limits apply for TA = 25°C.
LM2876
Symbol

' Conditions

Parameter

Iv+1 + lv-I Power Supply Voltage (NOte 10)

Typical
Umlt
(Note 6) (Note 7)

"

, Vpin7- V- ~ flV

18

20
60

, V (min)
V (max)

pin 8 Open or at OV. Mute: On
Current out of P'iri'8 ;> 0.5 mAo
Mute: Off

115

80'

dB (min)

THD +·N = 0.1% (max)
f=lkHz;f=20kHz

40

25

W(min)

"

AM

"Po

Mute Attenuation

Output Power (Continuous Average)

Units
(Umits)

Peak Po

Instantaneous Peak Output Power

THD+ N

Total Harmonic Distortion Plus Noise

25W. 20 Hz ::;; f ::;; 20 kHz
Av = 26 dB

"SR

Slew Rate (Note 9)

VIN = 1.2 Vrms. f = 10 kHz.
Square-Wave. RL = 2 kO

'1+

Total QuieSCent Power Supply Current VCM = OV. Vo = OV.lo .; OA

·Vos

Input Offset Voltage'

VCM

18

Input Bias Current

VCM = OV. 10 ',;, <>

rnA

lcis

Ihput Offset Current

VCM = OV.lo = OmA

10

Output Current Limit

Iv+1 = lv-I = 10V.tON = l'Oms. Va = OV

'Vod

Output Dropout Voltage (Note 11)

·PSRR

Power Supply Rejection Ratio

75

W

0.06

%
V/p.s(min)

9

5

24

50

mA(max)

1

10

mV(max)

0.2

1

p.A(max)

0.01

0.2

p.A(max)

4

3

A (min)

Iv+ -Vol. V+ = 20V.lo = + 100 mA
Ivo-v-I. V- = -20V.lo ";',-100 mA .

1.5
2.5

4
4

V (max)
V (max)

V+ = 30Vto 10V. V- = -30V.
VCM = OV. 10 ":" 0 mA
V+ = 30V. V- = -30Vto -'10V.
VCM = OV. 10 = 0 mA' '

125

85

dB (min)

110

85

dB (min)

==

av. 10 = 0 mA

" ~,.

",

'DC Electrical Test; refer to Test Circutt # I.
...AC Electrical Test; refer to Test CircuU #2.

1-88

Electrical Characteristics (Notes 1, 2)
The following specifications apply for V+
Limits apply for TA = 2SoC. (Continued)

=

+30V, V- = -30V,IMUTE = -O.S mAwith RL

=

80 unless otherwise specified.
LM2876

Symbol

Parameter

'CMRR

Common Mode Rejection Ratio

Conditions

Units
(Limits)

Typical
{Note 6)

Umlt
(Note 7)

V+ = SOVto 10V, V- = -10Vto -SOV,
VCM = 20Vto -20V,l o = 0 mA

110

7S

dB (min)

11S

80

dB (min)

8

2

MHz (min)

8

",V (max)

'AVOL

Open Loop Voltage Gain

Iv+1 = lv-I =30V, RL = 2 kO, 4VO = 40V

GBWP

Gain-Bandwidth Product

Iv+1 = lv-I = 30V
fo = 100 kHz, VIN = SO mVrms

··eIN

Input Noise

IHF-A Weighting Filter
RIN = 6000 (Input Referred)

2.0

SNR

Signal-to-Noise Ratio

Po = 1W, A-Weighted,
Measured at 1 kHz, Rs = 2S0

98

dB

Po = 2SW, A-Weighted,
Measured at 1 kHz, Rs = 2S0

112

dB

Ppk= 7SW, A-Weighted,
Measured at 1 kHz, Rs = 2S0

117

dB

0.004
0.006

0/0

Intermodulation Distortion Test

IMD

60 Hz, 7 kHz, 4:1 (SMPTE)
60 Hz, 7 kHz, 1:1 (SMPTE)

'DC Electrical Test; refer to Test CircuK #1.
"AC Electrical Test; refer to Test Clrcufi #2.
Nota 1: All voltages are measured wtth respect to the GND pin (pin 7), unless otherwise specified.

Note 2: Absolute MIlXimum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions lor which the devica is
functional, but do not guarantee specific performance limfiB. EIBCIricaI Charac/8ris1icS stste DC and AC electrical specifications under particular test conditions
which guarantee specific performance limfiB. This assumes thet the device is wHhin the Operating Ratings. Specifications are not guaranteed lor parameters where
no IimH is given, however, the typical value is a good indication 01 device performance.

Note 3: For operating at case temperatures above 25"C, the device must be derated based on a 15O"C maximum Junction temperature and a thermal resistsnce 01
8JC

= 1.0 'C/W ijunction to case). Reier to the Thermal Resistsnce ligure in the Application Information ""ction under Thermat Considerations.

Nota 4: Human body model, 100 pF discharged through a 1.5 kll resistor.
Nota 5: The operating junction temperefure maximum Is 15O"C, however, the Instsnteneous Sale Operating Area temperature Is 2SO"C.
Nota

6: Typicals are measured at 2S'C and represent the paramabic norm.

Nota 7: LlmfiB are guaranteed to National's AOQL (Average Outgoing Quality Leveij.
Nota 8: The LM2876T package TAllB is a non-isoiated package, setting the teb 01 the device and the heat sink at V- potential when theLM2876 is directly
mounted to the heat sink using only thermal compound. II a mica wssher is used in addition to thermal compound, 8cs (case to Sink) is increased, but the heat sink
will be Isolated lrom V-.
Note 9: The leedbacl< compensation network IlmfiB the bandwidth 01 the closed-loop response and so the slew rate will be reduced due to the high Irequency rolloil. Wfihout leedback compensation, the slew rate is typically larger.
Nota 10: V- must have at least -9V at fiB pin with reference to ground in order lor the under-vottage protection circuKry to be disabled.
Note 11: The output dropout vohege is the supply vohege minus the clipping vohege. ReIer to the Clipping Vottag& vs Supply Voltage graph In the typical
Performance Characterlsllca aect/on.

1-'89

•

Test Circuit # 1 ·(DC Electrical Test Circuit)
24.9 kn

200kn

OUTPUT

'50 kn

49.90.

. 49.9ll.

SOURCE
TLlHI11775-3

Test Circuit #2 ··(ACElectricaITestCircuit)
Rtl 20 kn

Ri 1 kn

C, 50·pF Rt2 20 kll.
y+

OUTPUT

Cc

220 pF

"2kn
lit.

SOURCE

yTLlH/II775-4

1·90

r-----------------------------------------------------------------------------~

Single Supply Application Circuit

r
iii:

~

Gt

V+

R,1 20kll
·RSN

Ri
lkll

,(;,

2.711

'C1

50 pf 'R,2 20 kll

'CsN
IO.ll'f

IOl'fI

TL/H/ll17S-S

FIGURE 2. typical Single Supply Audio Amplifier Application Circuit
·Optional components dependent upon specific design requirements. Refer to the External

Components Description section for a componenl functional description.

Equivalent Schematic (excluding active protection circuitry)
V+

lk

MUTE

GND*

1.lk

0.45
OUTPUT

•

+IND--+-f
-IN

800

150

0..5
VTL/H/1117S-6

1-91

~,
~

::&
.....

External Components Description (Figures 1 and 21
Functional Description

Components
1.
2.

AIN
AA

3.
4.
5.

CA
C
As

6.

'CC

7.
8.

Ai
'Ci

9.
10.

Alt
'Af2

11.
12.

OCt
AM

13.
14.

CM
°ASN

15.

°CSN,

16.
17.

°A

18.
19.

Cs
S1

°L

Acts as a volume control by setting the voltage 'level allowed to the amplifier's input terminals.
Provides DC voltage biasing for the single supply operation and bias current for the positive input
terminal.
Provides bias filtering.
Provides AC coupling at the input and output of. the amplifier for single supply operation.
Prevents, currents from entering the amplifier's n0l"!-inverting inpJt which may be passed through to
the load up()~ power-down of the system due to the low input impedance of the circuitry when the
unqer-voltage circuitry is off. This phenomenon occurs when the supply voltages are below 1.5V.
Aeduces the gain (bandwidth oUhe amplifier) at high frequencies to avo~ quasi-saturation
oscillations of the output transistor. The capacitor also suppresses external electromagnetic
switching noise created from fluorescent lamps.
Inverting input resistance to provide AC Gain in conjunction with Af1.
Feooback capacitor. Ensures unity gain at DC. AlsO a low frequency pole (highpass roll-off) at:
fc = 1/(27TAi Ci)
Feedback resistance to provideAC Gain in conjunction with Ai.
At higher frequencies feedl;lack resistance works with Ct to provide lower AC Gain in conjunction
with An and Ai. A high freqliency pole (Iowpass roll-off) exists at:
fc = [An AI2 (s + 1/Ar.;Pd]t[(Alt + AI2)(S + 1/Ct(Alt + AI2»l
Compensation capacitor that works with Alt and AI2 to reduce the AC Gain at higher frequencies.
Mute resistance~set.up to allow 0.5 mA to be drawn from pin 8 to ,turn the muting function off.
AM is calcUlated using: AM ::;; (Iv EEl - 2.6'1)/18 where 18,~' 0,5 mA., Aefer to the Mute,
Attenuation vs Mute Current curves in the Typical Performance Characteristics section.
Mute capacitance set up to create a large time constant for turn-on and turn-off muting.
Works with CSN to stabilize the output stage by creating a pole that eliminates high frequency
.,
oscillations.
Works with ASN to stabilize the output stage by creating a pole that eliminates high frequency
OSCillations.
' .
,fc = 1/(27TASNCSN)
Provides high impedance at high frequecies so that Rmay decouple a highly capacitive load
and reduce the Q of the series resonant circuit due to capacitive load. Also provides a low
impedance at low frequencies to short out A and pass audio signals to the load.
,
Provides power supply filtering and bypassing,
Mute switch that mutes the music going into the amplifier when opened.

'Optional components dependent upon specific design requirements. Refer to the Application Information section for more information,

OPTIONAL EXTERNAL COMPONENT INTERACTION

Although the optional external components have specific desired functions that are designed to reduce"the bandwidth and
eliminate unwanted high frequency oscillations they may cause certain undesirable effects when they interact. Interaction may
occur for components whose reactances are ,in close proximity to one another. One example would' be the coupling capacitor,
Ce, and the compensation capacitor, Cf. These two components act as low impedances to certain frequencies which will couple
signals from the input to the output. Please take careful note of basic amplifier component functionality when designing in these
components.
The optional external components shown in Figure 2 and described above are a~plicable in both single and split voltage supply
configurations.
'
,

1-92

Typical Performance Characteristics

~

3

\ 1\ \
~
\
\\~
~.\
~

,
\

1
\"'1

Te

!!

1\
1'-

::::::: IOml
lOCi

20

.0

.J

"

t*l1~-+ttI

i

1-H-1W1tI..:"I'-!-Io

40

HI-tl-ltllFI"H

20

1-H-I-fffHl-+-I+

o L....l...J.J.JUJ.W.---'-J.J.
0.1
COLLECTOR-EWITTER VOLTAGE (V)

1/6.T 20.00 kHz

Vs =

100

Vs

.3

I- OUT
IV

5 p.

1:.+

~

0.2

iii

......

~

~

0.1

o

o

150

100

II

,,
, /'
, "

Clipping Voltage (-VEE)
Clipping Voltage (+VCC>

'\ = 8n

~

-50
,TIME (;...)

50

Clipping Voltage vs
Supply Voltage

0••

is 0.3

F-

CASE TEMPERATURE (oc)

~

IN

10V

o

-50

Vs = :t30V
~

= ±20V

10

0.5

v, =uov

= OA

t~OV t--

20

Input Bias Current vs
Case Temperature
1\ "" ao

10

30

o
10

Vo = ov

I
I

.0

PULSE WIDTH (m.)

t..y.2adB

VsrT
I
I

-5

Pulse Response

:l:20V

I
I

10

PULSE WIDTH (m.)

200 .----rrlTTTnr-rTT

60

=~::.

o

0.1

80

50

-5

o

O~~~~'----~~-L~

.0

VCE =
70V
60V
50V
40V
30V

-

..'"~

40

50

TC = 25°C
TJ = 250°C

E:

30

Supply Current vs
Output Voltage
TO-220

"i"

20

10

SUPPLY VOLTAGE (tV)

Pulse Thermal
Resistance

1-+--+-1'--+--+ TO-220

Tc= 125°C

"'"

I
&I

10

TIWE(m.)

Pulse Thermal
Resistance

20

§

\

o

COLLECTOR-EMITTER VOLT AGE (V)

o

-5

2m.

10V

.0

8Q

60

I '0 = OA
J
'Te=' ,,2e

125°C

i'"

I ...

~ ["-.. ...... lm.1

25°C

:=

~

O.5ma

o

Te

.... 84

"- 0"1
f',

TO-220

50

Vs ., t30V

I/AT 50.00kH.

O.lm

1\

TJ '" 250°C

o

Supply Current vs
Supply Voltage

SPIKe™
Protection Response

Safe Area

-

'/

,'V
:;. ~ .......
2

50

100

TEMPERATURE (OC)

150

10

15

20

25

30

SUPPLY VOLTAGE(tV)

TUHIT 1775-7

1-93

Typical Performance Characteristics

(Continued)

"~I',

THD + Nvs
Output P~wer
~IIIEj':f:FTPl

g
z

+

Q

j!:

0.001
100

10

. lk

10k

10m

100k

FREQUENCY (Hz)

THD, -+;

g.
t

!II Distribution

THD
40

50

36

45

g

28

t

~

~

~

S
eo

il!

~

~

~
!<

32

:g

20
16

\

25

I\.

•o

"-I '

15

,

o

10

0.04

0.08 0.12 0.16
0.2
0.06
0,1
0.1' 0.18

0,02

o

50

60

70

SO

80

100

1.0 - -, - - - - - - - - - - - - - - - - - - - - - - ... - - - - - - - - - -

1.6

1.2

1.0

1.9

1.6

1.3

~

~

f" -

-

-

-

90 - - - - 50 - - -

~

2.4

1.9

1.7

3.0

2.5

2.1

1.8

1.5

I

3.8

3.2

2.8

2.4

2.0

1.6

1.2

4.3

3.8

3.3

2.8

2.3

1.8

1.3 - - - - - -" -. 126- - - - 20- - --

7.1

6.1

5.5

4.8

4.1

3.5

2.8

2.1

q

132

11.3

9.8

8.8

7.8

6.8

5.8

4.8

3.6

2.8

138----10---0

120

25

I ':
I

15

= 1 kHz

rHO

50

I I

< 0.1%

J J .iov
I I

j.;"

Vs

I

= :t25V

I
Vs =

10 ~

'2 0V

I I
I I
10

20

30

OUTPUT POWER (w)

~

~

10 20 30 40 50 60 70 80 90

50

Output Pow,r vs
Supply Voltage
60
THO

~

I

30
20

i

10 IL

Vs

t'

Vs

o

I
10

Vs

='30V

~

.i5VI-

~

5

=i20V I

o
40

TLlH/1177S-9

f = 1 kHz
THO < 0.'"

~

20

OUTPUT POWER (w)

~ N ~ O.O~~

50 f = 1 kH::
THO + N:S 0.15"

- I-- "'i'/,
V

20Hz::S f ~ 20kHz

40

A-.

30

/.
'7

20

I/.

1/

10

I
30

..

vcc.lv+I+lv-1

'\ =8n I

40

I

' ..

Power DIssipation va
Output Power

1J

'\ =, ani

.

,

1.1 - - ",- - - - - - - - - - - - - - - - 114- - - - 30- - - -J--+-+-+-+,+-,f-:.r-+--l

5.1

30

o
o

-

30 35 40

-r-r--r-,,--,-,--r.n
-.--c-8n,"".,.

II

s

20

25

~
~
6n':
1.1 - - - - - - - - - - - - -~-- - - - - -'- -- - - - - - . 102- ---40----J--+-+-+-+++t--.r-,f-l
I :,
1.4
1.1
108
35

f

~

20

Maximum Power Dissipation
vs Supply Voltage

Po.w

110

1.3

Power Dissipation vs
Output Power
40

15

TL/H/1177S-8

Note: The maximum heet sink thermal resistence values. 0SA. in the teble above
~ O.~C/W due to thermal ~pound,

~

10

E3 ROOM: 35% OF THO

were C8lcula~ using a 0cs

50

5

'\ (n)

Max Heatslnk Thermal Resistance ("C/W)
at the SpeCified Ambient Temperature ("C)
.0

\

30

20

0.004' 0.008 0.012 0.Q16 0.020
0.002 0.006 0.010 0.014 0.018

= 25°C

Vs = :l:30VOC
+ N .:s 0.08%

20Hz:S f:S 20kHz

35

E3 THO: ," OF THO

TA

I
THO

1/\

40

28
U

o

100

Output Power vs
Load Reslstan~

+ N Distribution

40
32

10

OUTPUT POW~R (w)

36

o

0.1

OUTPUT POWER (W)

'/",'=sn

.......
... =.~'=

~

o
40

50

o

10

15

20

SUPPLY VOLTAGE

25

(.v)

30

35

TLlHI11775-10

1-94

Typical Performance Characteristics

.-i:
N
CD

(Continued)

~

G)

IMD 60 Hz, 4:1

IMD 60 Hz, 7 kHz, 4:1

1
==30.00856 E1120.0000k
O. 1

E
~
ill

1\ -

811 ..

~

======
i

12.000
1.8462
-8.30B
-18.....6
-28.62

0.00 1

0.000 1
2k

10k

20k

FREQUENCY (Hz)

7kHz 4:1

-38.71

-48.92
Ii: -59.08
~ -69.23
-79.38
-89.54
-99.7
-109.8
-120.0
6.00k B.40k 6.80k 7.2Ok 7.60k B.OOk
6.20k 6.80k 7.00k 7.4Dk 7.BOk
FREQUENCY (Hz)

•

1\

E
~

E
~

0.1

ill
0.010
0.001
0.0005
0.1

.........

0.0 1

ill

~

0.0

=Bll=====

I~.AP

10

!

-.40.00

E

~

-60.00

ill

~

,''

-100.0

10k

IMD 60 Hz, 7 kHil, 1:1
50

Jo H~

-60.00

0.000 1
2k

FREQUENCY (Hz)

Mute Attenuation
vs Mute Current

0.1
0.010

I..t.

I,.

0.001
0.0005
0.1

-120.0
6.00k 6.40k 6.80k 7.2Ok 7.60k 8.00k
6.20k 6.60k 7.00k 7.4Dk 7.80k
FREQUENCY (Hz)

20k

100

IJO
7kHz 1:1

-20.00

0.00 1

10
OUTPUT POWER (W)

IMD 60 Hz, 7 kHz 1:1
20.000

20.0000k~

§0.02101
O. 1

10

IhiD 60Hz

IMD 60 Hz, 1:1
1

50

~ r- H7.06000k t AP

~

0.0 1

IMD 60 Hz, 7 kHz, 4:1

10

100

OUTPUT POWER (w)

Mute Attenuation
vs Mute Current

Large Signal Response
25

Y1llll1n

111111
111111
111111
f = 1 kHz. 20 kHz
1111111
111111

1111/ '1111111

20
0;;;

40

.3

52

20

IIIIIY

tWIll

60

111m

1111111
111111
1111111
111111
Vs = ± OV
1\ = an

BO
100

=: 0 dB
.. = 26dB

Vo = , VRMS

120
0.001

1111111

0.01

0.1

10

20

.3

~

60

2

80
100

-=:'
f= 20kH

Vs

= ::I:3QV

~

10

g

0.001

1'1111111 III. .. =

0.01

26

0.1

Vs = :UOV
= Bll
THD < 10%

1\

Vo::; 14.1VRMS1\=811
= OdS

o

100

10

lk

PIN 8 MUTE CURRENT (rnA)

Power Supply
Rejection Ratio

1111111
1111111

100

-PSRR

60

1M

120

Vs ::: :l:30V
Tc = 2S 0 C

100

CNRR
0;;;

0

80

.3
z

60

lOOk

Open Loop
Frequency Response

120

1IIIIIm

10k

FREQUENCY (Hz)

Common-Mode
Rejection Ratio

+PSRR

100

11
~

V

120 f= 1kHz

PIN 8 MUTE CURRENT (rnA)

120

!

40

~

0

60
40

40

0

Vs = :t30Y

20

Te = 25°C

20

20
10

100

lk

10k

FREQUENCY (Hz)

100k

1M

0
10

100

lk

10k

FREQUENCY (Hz)

lOOk

1M

100

lk

10k

lOOk

1M

FREQUENCY (Hz)

TLlH/11775-11

1-95

~ r-------------------------------------------------------------------~

Ii;
N

:E
~

Application Information
GENERAL FEATURES
Mute Functlon!'The mUtirig function of the LM2876 allows'
the user to r;nut!llhe music going into the amplifier by drawing less"than 0.5 rnA out of, pin 8 of the device. This is
accomplished as shown in t.he Typical Application Circuit
where the resistor RM is choSen with reference to your negative supply voltage and is used in conjuction with a switch.
The switc~(when opened)cuts.off th!l current flow from
pin 8 to V-, ,thus placing the'LM2876 into mute mode. Refer
to the Mute Attenuation vS.Mute Current curves in the Typi~
cal Perfo!'inance Charaqterlstlca section for values of at- '
tenuation per current' out· of pin 8. The resistance RM is
calculated by the following equation:
RM (IVEEI - 2.6V)1I8
where 18 ~ 0.5 rnA.
Under-Voltage Protection: Upon system power-up the under-voltage· protection circuitry 'allows the power supplies
and their ~rrespqnding caps to .c6me up close to their full
values before turning on the LM2876 such that no DC output spikes occur. Upon tum-off, the omput of the LM2876 is
brought to ground before the power supplies such that no
transients occur at power-down.
OVer-Voltage Prot.,ctlon: The LM2876 contains oveivoltage protection cirCUitry that limiUi the output current to approximately 4Apeak while alsO proViding voltage Clamping,
though not through internal clamping diodes. The clamping
effect is quite the same, however, the output transistorS are
designed to work alternately by sinking large current spikes.
SPIKe Protection: The LM2876 is protected from instantaneous peak-temperature streSSing by the power transistor
array. The Safe Operating Area graph in the Typical P.erformanee Characteristics section shows the area of device operation where the SPiKe Protection Circuitry is not
enabled. The waveform to the right of the SOA graph exemplifies how the dynamic protection will cause wavetorm distortion when enabled.
Thermal Protection: The LM2876 has a sophisticated thermal protection scheme to prevent long-term thermal streSs
to the device. When the temperature on the die reaches
165°C, the LM2876 s.huts down: It starts operating again
when the die temperature drops to about 155°C, but inhe
temperature again begins to rise, shutdown will ocCur again
at 165"C. Therefore the device is allowed to heat up to a
relatively high temperature if the fault condition is temporary, but a sustained fault will cause the device to cycle in a
Schmitt Trigger fashion between the thermal shutdown temperature limits of 165°C and 155°C. This greatly reduces the.
stress imposed on the 10 by thermal cycling, which in turn
improves its reliability under sustained fault conditions.
Since the die temperature is directly dependent ~pon the
heat sink, the heat sink should be chosen as discussed in'
the Thermal' Consideratlohs:'section, such that thernial "i,
shutd~wn will not be reached during normal operation. Us-

ing the best heat sink possible within the cost and space
constraints of the system will improve .the long-term reliability of any PQwer semiconductor device.
THERMAL CONSIDERATioNS,
Heat Sinking
The choiCe. of a heat sink for a high-power audio amplifier is
made entirely to keep the die temperature at a level such
.that the therm!ll protection circuitrY does not operate under
normal circumstances. The heat sink should be' chosen to
, disl\ipate the maximum IC power for ~ given supply voltage
.and rated load.
'
With high-power pulses of longer duration than 100 ms, the
case temperature will heat up drastically without the use of
, a heat sink. Therefore the case temperature, as measllred
at the center of the package bottom, is entirely dependent
on heat sink design and the mounting of the IC to the heat
sink. For the design of a heat sink for your audio amplifier
application refer to the Determining The Correct Heat
Sink section.
Since a semiconductor manufacturer has no control over
which heat sink is used in a particular amplifier design, we
can only inform the system designer of the parameters and
the method,.needed in the determination of a heat sink. With
this in mind, the system designer must choose his supply
voltages, a rated load, a deSired output power level, and
know the ambient temperature surrounding the device.
TheSE;! parameters are in addition to knowing the maximum
junction temperaturE;! and the thermal resistance of the IC,
both of which are provided by National S.miconductor.
As a benefit to the system deSigner we have provided Maxi!"um power Dissipation vs Supply VOlta!il6S curves for various loads in the Typical Performance' Chat8cterlstica
seCtion, giving an accurate figure for the maximum thermal
resistance required for a partieularamplifier design. This
data was based on 9JC = 1°C/W and 9cs = O.2"C/W. We
also provide a section regarding heat sink determination for
any audio amplifier design where 9cs may be a different
vaille. It should be noted that the idea,bElhind dissipating the
maximum power within the IC is'to proVide the device with a
i low resistance to convection heat transfer such as a heat
sink. Therefore, it is necesSary for the system' desigl)er to be
conservative in his heat sink calculations. As a rule, the lower the thermal resistance of the heat sink the higher the
amount of power that may be dissipated. ihis is of course
guided by the cost and size requirements of the system.
Convection cooling heat sinks are available commercially,
and their manufacturers should be ~nsulted tor ratings.
Proper mounting of the IC is requirec:t ,to minimize the thermal drop between the package and the heat sink. The heat
sink must also have enough metal unde~ the' ,pa:ckage to
conduct heat from the center of the package bottom' to the
fins without excessive temperature drop.

1-96

~------------------------------------------------------------------------------------,

A thermal grease such as Wakefield type 120 or Thermalloy
Thermacote should be used when mounting the package to
the heat sink. Without this compound, thermal resistance
will be no beller than 0.5·C/W, and probably much worse.
With the compound, thermal resistance will be 0.2·C/W or
less, assuming under 0.005 inch combined flatness runout
for the package and heat sink. Proper torquing of the
mounting bolts is important and can be determined from
heat sink manufacturer's specification sheets.
Should it be necessary to isolate V- from the heat sink, an
insulating washer is required. Hard washers like beryluum
oxide, anodized aluminum and mica require the use of thermal compound on both faces. Two-mil mica washers are
most common, giving about 0.4·C/W interface resistance
with the compound.
Silicone-rubber washers are also available. A 0.5·C/W thermal resistance is claimed without thermal compound. Experience has shown that these rubber washers deteriorate and
must be replaced should the IC be dismounted.
Determining Maximum Power Dissipation
Power dissipation within the integrated circuit package is a
very important parameter requiring a thorough understanding if optimum power output is to be obtained. An incorrect
maximum power dissipation (Po) calculation may result in
inadequate heat sinking, causing thermal shutdown circuitry
to operate and limit the output power.

sink can be calculated. This calculation is made using equation (4) and is based on the fact that thermal heat flow parameters are analogous to electrical current flow properties.
It is also known that typically the therma( reSistance, 8JC
(junction to case), of the LM2876 is I·C/W and that using
Thermalloy Thermacote thermal compound provides a thermal resistance, 8cs (case to heat sink), of about O.2"C/W
as explained in the Heat Sinking section.

~

G»

Referring to the figure below, it is seen that the thermal
resistance from the die (junction) to the outside air (ambient)
is a combination of three thermal resistances, two of which
are known, 8JC and 8cs. Since convection heat flow (power
dissipation) is analogous to current flow, thermal resistance
is analogous to electrical resistance, and temperature drops
are analogous to voltage drops, the power dissipation out of
the LM2876 is equal to the following:
POMAX = (TJrnax - TAmb)/8JA
where 8JA = 8JC + 8cs + 8SA
TJmax

TAmb
~

IIJJC

••

8cs

-

lisA

POMAX

----~~~.-----4.
IIIJA
TLlH/11n5-12

The following equations can be used to acccurately calculate the maximum and average integrated circuit power disSipation for your amplifier deSign, given the supply voltage,
rated load, and output power. These equations can be di"
rectly applied to the Power. Dissipation vs Output Power
curves in the Typical Performance Characteristics section.
Equation (1) exemplifies the maximum power dissipation of
the IC and equations (2) and (3) exemplify the average IC
power dissipation expressed in different forms.
POMAX = Vee2/21T2RL
where Vee is the total supply voltage

r-

~

Application Information (Continued)

But since we know POMAX, 8JC, and 8sc for the application
and we are looking for 8SA, we have the following:
8SA = [(TJrnax - TAmb) - POMAX (8JC + 8cs») /POMAX(4)
Again it must be noted that the value of 8SA is dependent
upon the system designer's amplifier application and its corresponding parameters as described previously. If the ambient temperature that tl1e audio amplifier is to be working
under is higher than the normal 25·C, then the thermal resistance for the heat sink, given all other things are equal,
will need to be smaller.
Equations (1) and (4) are the only equations needed in the
determination of the maximum heat sink thermal resistance.
This is of course given that the system designer knows the
required supply voltages to drive his rated load at a particular power output level and the parameters provided by the
semiconductor manufacturer. These parameters are the
junction to case thermal resistance, 8JC, TJmax = 150·C,
and the recommended Thermalloy Thermacote thermal
compound resistance, 8cs.

(1)

POAVE = (VOpk/Rt.llVee/1T - VOpk/2)
(2)
where Vee is the total supply voltage and VOpk = Vee/1T
POAVE = Vee VOPk/1TRL - VOpk2(2RL
(3)
where Vcc is the total supply voltage.
Determining the Correct Heat Sink
Once the maximum IC power dissipation is known for a given supply voltage, rated load, and the desired rated output
power the maximum thermal resistance (in ·C/W) of a heat

1-97

•

Application Information (Continued)
SIGNAL-TO-NOiSE RATIO

TypiCal' signal-ta-nolse figures are listed for an A-weighted
filter which is commonly used in ~he measurement Of noise.
The 'shape ohll weighting filters is Similar, with the peak of
the, curve usually occurring in the 3 kHz-7 kHz region as
': ,'"
'
shown below.

Iii the m~~ur$~ent of th~ signal-to-noiseratio; misinterpre.
tations 'of the numbers actually 'measured are common. One
amplifier maY'Sound I'nucti quieter than another, but due to
improper testing techniques, they appear equal in'measurements. This'is often the case when comparing iniegrated
circuit designs to discrete amplifier designs. Discrete transistor amps often "run' out of gain" at high 'frequencies and
therefore have 'small bandwidths to noise as indicated' balow.'
80

2

~

z

60

~ 40

INTEGRATED CIRCUIT,

20

--...,........-+ ••', /'

.

...

TLlH/11775-14

SUPPLY BYPASSING

20

The LM2876 has excellent power supply rejection, and does
I)ot require a regulated supply. However, to eliminate polISible oscillations all op amps and power oP amps should have
their supply leads bypassed wilh low-inductance capaCitors
having short leads and located, close to the package terminals. Inadequate power supply bypassing will manifest itself
by a low frequency oscillation known as "motorboating" or
by high frequency instabilities. These instabilities can be
eliminated through rnl,lltiple bypassing utili2;ing a large tantaluin, or electroJytic capacitor (10 p.F or larger) which is used
to absrir:b, low frequency variations and a small ceramic ca~
pacitor (0.1 p.F) to prevent any highfreql!ency feedback
through the power supply lines.

TL/H/11775-13

Integrated circuits have additional open loop gain allowing
additional feedback loop gain in order to lower harmonic
distortion and improve frequency response. It is this additional bandwidth that can lead to erroneous signal-to-noise
measurements if not considered during the measurement
process. In the, ,typical example ab9ve" the difference in
bandwidth appears small on a log sca,le but ,the factor 01.10
in bandwidth, (200 kHz to ~ MHz) can result in',a 10 dB
theoretical difference in the signal-to-noise 'ratio (white
noise is proportional to the Square root of the bandWidth in a
system). '
",

If adequate bypassing is not provided the current in the supply leads which is a rectified component of the load current
may, I}El fed: back into internal cirCUitry. This signal causes
10w'diStortion at high frequencies requiring that the supplies
be bypassed at the, package terminals with an electrolytic
Capacitor of 470 p.F or more. '

I~ comparing audio amplifierS it is necessarY to me~ure the
magnitude of noise in the audible bandwidth by using a
"weighting" filter.1 A "weighting" filter alters the fnliq!,lency
response in order to compensate for the average tiuman
ear's sensitivity to the frequency spectra. The weighting filters at the same'time provide the bandwidth limiting as discussed in the previous' paragr8Pl!.
In addition to noise filtering, differing meter types give,different noise .readings. Meter responses include:
1. RMS reading,

LEAD INDUCTANCE
Power op amps are sensitive to inductance in the output
lead; particularly with heavy capacitive loading. Feedback to
the input should be taken directly from the output terminal,
minimizing common inductance with the load.
Lead inductance can also cause voltage surges on the supplies. With long leads to the power supply, energy is stored
in,thelead inductance when the output is shorted. This energy can be dl,lmped back into the supply bypass capacitors
when the short is removed. The magnitude of this transient
is reduced by increasing the size of the bypass capacitor
near the IC. With at least a 20 p.F local bypass, these voltage surges are important only if the lead length exceeds a
couple feet (> 1 p.H lead inductance). Twisting together the
supply and ground leads minimizes the effect.

2. average responding,
3. peak reading, and
4. quasi peak reading.
Although theoretical noise analysis is derived using true
RMS based calculations, most actual measurements are
taken with ARM (Average Responding Meter) test equipment.
Reference 1: CCIR/ARM: A Practical Noise Measurement
Method; by Ray Dolby, David Robinson and Kenneth Gundry, AES Preprint No. 1353 (F-3).

1-98

Application Information (Continued)
The load current IL will be much larger than input bias current II, thus V1 will follow the output voltage directly, i.e. in
phase. Therefore the voltage appearing at the non-inverting
input is effectively positive feedback and the circuit may oscillate. If there were only one device to worry about then the
values of A1 and A2 would probably be small enough to be
ignored; however, several devices normally comprise a total
system. Any ground return of a separate device, whose output is in phase, can feedback in a similar manner and cause
instabilities. Out of phase· ground loops also are troublesome', causing unexpected gain and phase errors.
The solution to most ground loop problems is to always use
a single-point ground system, although this is' sometimes
impractical. The third figure below is an example of a singlepoint ground system.

LAYOUT, GROUND LOOPS AND STABILITY
The LM2876 is designed to be stable when operated at a
closed-loop gain of 10 or greater, but as with any other hlghcurrent amplifier, the LM2876 can be made to oscillate under certain conditions. These usually involve printed circuit
board layout or output/input coupling.
When designing a layout. it is important to return the load
ground, the output compensation ground, and the low level
(feedback and input) grounds to the circuit board common
ground point through separate paths. Otherwise, large currents flowing along a ground conductor will generate voltages on the conductor which can effectively act as signals
at the input, resulting in high frequency oscillation or excessive distortion. It is advisable to keep the output compensation components and the 0.1 ",F supply decoupling capacitors as close as possible to the LM2876 to reduce the effects of PCB trace resistance and inductance. For the same
reason, the ground return paths should be as short a$ possible.
'

The single-point ground concept should be applied rigorously to all components and all circuits when possible. Violations of single-point grounding are most common among
printed circuit board designs, since the circuit is surrounded
by large ground areas which invite the temptation to run a
device to the closest ground spot.. As a final rule, make all
ground returns low resistance and low inductance by using
large wire and wide traces.

I.n general, with fast, high-current Circuitry, all sorts of prob:
lems can arise from improper grounding which again can be
avoided by returning all grounds separately to a common
point. Without isolating the ground signals and returning the
grounds to a common pOint, ground loops may occur.
"Ground Loop" is the term used to describe situations occurring in ground systems where a difference in potential
exists between two ground points. Ideally a ground is a
ground, but unfortunately, in order for this to be true, ground
conductors with zero resistance are necessery. Since real
world ground leads -possess finite resistance, currents running through them will cause finite voltage drops to exist. ·If
two ground retum lines tie. into the same path at different
points there will be a voltage drop between them. The first
figure below shows a common ground example where the
positive input ground and the load ground are returned to
the supply ground point via the same wire. The addition of
the finite wire resistance, R2, results in a voltage difference
between the two pOints as shown below.

Occasionally, current in the output leads (which function as
antennail) can be coupled through the air to the amplifier
Input, resulting in high-frequency oscillation. This normally
happens when the source impedance is high or the input
leads are long. The problem can be eliminated by placing a
small capaCitor, Ce. (on the order of 50 pF to 500 pF)
across the LM2876 input terminals. Refer to the External
Components Description section relating to component
interaction with Cj.

REACTIVE LOADING
It is hard for most power amplifiers to drive highly capacitive
loads very effectively and normally results in oscillations or
ringing on the square wave response. If the· output of the
LM2876 is· connected directly to a capacitor with no series
resistance, the square wave response will exhibit ringing if
the capacitance is greater than about 0.2 ",F. If highly capacitive loads are expected due to long speaker cables, a
method commonly employed to p~otect amplifiers from low
impedances at high frequencies is to couple to the load
thro~gh a 10n resistor In parallel with a 0.7 ",H inductor.
The Inductor-resistor combination as shown in' the Typical
Application Circuit isolates the feedback amplifier from the
load by providing high output impedance at high frequencies
thus allowing the 10n resistor to decouple the capacitive
load and reduce the Q of the series resonant circuit. The LA
combination also provides low output impedance at low frequencies thus shorting out the 1on resistor and allowing the
amplifier to drive the series AC load (large capacitive load
due to long speaker cables) directly.

~,

'"""
GROUN~f---1

TUH/11 n5-15

1-99

•

I....

Application Information

(Continued)

GENERALIZED AUDIO POWER AMPLIFIER DESIGN "

DESIGN A 25W(ll{} AVDIO AMPLIFIER

The system 'designer usually knows Some of'the'101l0wl'ng
parameters when starting a'n au~io ampr.fier design:

Given:.
Power 'Output
, Load ,Impedance
Ihput Level
Input Impedance
Bandwidth
Equations,(1)' and (2) give:

Input Level
Desired Power Output
Input Imped8nce'
";,,,
Load Impedance
, Maximum Supply Voltage
"l;IantjlNidth
The power output and load impedance Qe~ermine the power
supply requiremen~"however, d,~pending upon the applipation ~me system designers may be ,limited to certain maxi,
mum supply voltages. .If, the designer does have a powEir
supply limitatiqn, hE! should cho,ose, a practical I,oad impedanqe which' would allow the' amplifier to provide the desired
output power,J~~eping in mind thE! current lilliiting Gap~ili­
ties of the device. In any Case, 'the output ,aignal sWing and
current are found from (where Po is the average' output
.."
power):

25w/I:ln
V~peak = '20.0V
1~~1ik = 2:SA
Therefore the s,upply required is: ± 24.0V @ 2.5A
With ,15% regulation and l1igh line the final supply voltage is
±30.36V using equation (3). At this pOint it is ,a good idea to
chec~,th~ Power Outputvs Supply. Voltage to ensure that
the. cequir\ld output power is obtainable frOm the device
whire maintainiQg low THD + N, It is also good to check the
PO,wer Dissipation vs Supply Voltage to ensure that the de1!icecan handle the internal power diSSipation. At the same
time designing in a relatively practical sized heat sink with a
low thermal resistaQpe i,s also, important. Refer to Typical
Perfor'manCtl Characteristics graphs and the Thermal
Consrderatlons section for more information.
The minimum gain fro,m equation (4) is:
Av ~ 14

VOpeak = ~, ' •
(1)
lopeak = ,~(2 Pp)/RL
(2)
To determine the maximum supply voltage the foliolNing parameters must be' considered. Add the dropout lIoltage (4V
for LM2876) to the peak output swing, VOpelik, , to get the
supply rail value (i.e. ± (Vopeak + Vod), at a current'of
lopeak)' The regulation of the supply determines the unloaded voltage, usually ab04t15% higher. Supply voltage will
al,lIo ,rise 10% dllring high line,cOllditions. Therefore, the
maximum supply voltage ,is obtained from. the foliolNing
equlj.tic:m:

We select a gain of 15 (Non-Inverting Amplifier); resulting in
II sensitjvity of 942.!3 mV.
Letting RIN equal 100 kO gives, the required input impedance, however, this would eliminate the "volume control"
unless an additional input impedance was placed in series
witl:l the 10 kO potentiometercthat:is depicted in Figure 1..
Adding the additional 100 kft' resistor would ensure'the minumum required input impedance.

Max. supplies :::: '± (Vopeak + Vod)(1 + regulation)(1.1) (3)
The input sensitivity and the output power specs determine
the minimum required gain as depicted' b'el~ , .
'

,~

\,~

:'

,

, 25W
80
1V(max)
, 100kO
20 Hz-20 kHz ± 0.25 dB

Av ~(~Po RLl/(VIN) = Vo.mslVin.ms
(4)
Normally the gain is set between 20 and 200; for a 40W, 80
audio amplifier this results in a, sensitivity of 894 mV and
89 mV, respectively. Although higher gain, amplifiers provide
greater ,output power and dynamic headroom capabilities,
there are ,certain shortcomings that go along'with the so
called "gain.',' The input referred' noise floor, is increased
and hence the SNR is;Worse. With the increase in gain,
there is also a reduction of the power bandwidth, which., results in a decrease in feedback thus not allowing the amplifier to respond quickly enough ,to' nonlinearities. This decreased ability to respond ,to nonlinearities increases the
THD + N specification.
The desired input impedance is set by RIN. Very high values
can cause board layout problems and DC offsets at the output. The value for the feedback resisflmc9,Rfl, should be
chosen tO'be a relatively large value (10kO-100 kO), and
the other feedback resistance, Ri, is calculated using standard op amp configuration gain equations, Most aiJdio amplifiers are deSigned 'from 'the non-inverting :amplifier configuration.
"

For low DC otfSet!t at the output we let Rfl = 100 kO.
Solving for'Ri (Non-lnverting'Amplifier) gives the following:'
t;li = Rf;/(Av -1) = 100k/(15 - 1) = 7.1 kO;use6.1~kO
The bimdlNidth requirement must be stated ,as a pole, i.e.,
the 3 dB frequency. Five times away from a poie gives
0.17 dB dOwn, which ill better thlin the required 0.25 dB.
Therefore:
fL = 20 Hz/5 = 4 Hz
fH;' 20kHz x 5 = 100kHz
At this pOint, it is a good idea to ensure that the Gain-BandINidth Product for the part will provide the designed gain out
to the upper 3 dB point of,1.00 kHz. This is why the minimum
GBWP of the LM2876 is impOrtant.
GBWP ~ Av x f3dB = 15 X 100kHz = 1.5 MHz
GBWP = 2.0 MHz (min) for the LM2876
Solving for the low frequency roll-off capacitor, Ci, we have:
Ci

1-100

~

1/(2'71" Ri fLl = 5.9 p.F; use 10 p.F.

Definition of Terms
Input Offset Voltage: The absolute value of the voltage
which must be appUed between the input.terminals through
two equal resistances to obtain zero output voltage and current.
Input Bias Current: The absolute value of the average of
the two inplAt currents with the output voltage and current at
zero.

Headroom: The margin between an actual signal operating
level (usually the power rating of the amplifier with. particular
supply voltages, a rated load value, and a rated THD + N
figure) and the level just before clipping distortion occurs,
expressed in decibels.
Large Signal Voltage Gain: The ratio of the output voltage
swing to the differential input voltage required to drive the
output froni zero to either swing limit. The output swing limit
is the supply voltage less a specified quasi-saturation .voltage. A pulse of short enough duration to minimize thermal
effects is used as a measurement signal.
'
Output-Current Limit: The output' current with a fixed output voltage and a large input overdrive. The limiting current
drops with time once SPiKe protection circuitry is activated.

Input Offset Current: The absolute value of the difference
in the two input currents with the output voltage and current
at zero.
.
Input Common-Mode Voltage Range (or Input Voltage
Range): The range of voltages on the input terminals for
which the amplifier is operational. Note that the specifications are not guaranteed over the full common-mode ·voltage range unless specifically stated.

Output Saturation Threshold (Clipping Point): The output
swing limit for a specified input drive beyond that required
for zero output. It is measured with respect to the supply to
which t,he output is swinging.
Output ReSistance: The ratio of the change in output volt"ge tci'the change in output current with the output around
zero.
,
"
Power Dissipation Rating: The power that can be dissipated for a specified time interval without activating the protection circuitry. For time intervals in excess of 100 ms, dissipation capability is determined by heat sinking of the IC package rather than by the IC itself.
Thennal Resistance: The peak, junction-temperature rise,
per unit of internal power dissipation (units in ·C/W), above
the' ·case temperature as measured at the center of the
package bottom.
The DC thermal reSistance applies when one output transistor is operating continuously. The AC thermal resistance applies with the output transistors conducting alternately at a
high enough frequency that the peak capability of neither
transistor is exceeded.

Common-Mode ReJection: The ratio of the input commonmode voltage range to the peak-to-peak change in input
offset voltage over this range.
Power Supply Rejection: The ratio of the change in input
offset voltage to the change in power supply voltages producing it.
Quiescent Supply Current: The current required from the
power supply to operate the amplifier with no load and the
output voltage and current at zero.
Slew Rate: The internally limited rate of change in output
voltage with a large amplitude step function applied to the
.
input.
Class B Amplifier: The most common type of audio power
amplifier that consists of two output devices each of which
conducts for 180" of the input cycle. The LM2876 is a
Quasi - AB type amplifier.
Crossover Distortion: Distortion caused in the output
stage of a class B amplifier. It can result from inadequate
bias current providing a dead zone where the output does
not respond to the input as the input cycle goes through its
zero crossing point. Also for ICs an inadequate frequency
response of the output PNP device can cause a turn-on
delay giving crossover distortion on the negative gOing transition through zero crossing at the higher audio frequencies.
THO + N: Total Harmonic Distortion plus Noise refers to
the measurement technique in which the fundamental component is removed by a bandreject (notch) filter and all remaining energy is measured including harmonics and noise.
Signal-to-Noise Ratio: The ratio of a system's output signal
level to the system's output noise level obtained in the absence of a signal. The output reference signal is either
specified or measured at a specified distortion level.
Continuous Average Output Power: The minimum sine
wave continuous average power output in watts (or dBW)
that can be delivered into the rated load, over the rated
bandwidth, at the rated maximum total harmonic distortion.

Power Bandwidth: The power bandwidth of an audio amplifier is the frequency range over which the amplifier voltage gain does not fall below 0.707 of the flat band voltage
gain specified for a given load and output power.
Power bandwidth also can be measured by the frequencies
at which a specified level of distortion is obtained while the
amplifier delivers a power output 3 dB below the rated output. For example, an amplifier rated at 60W with ,;; 0.25%
THD + N, would make its power bandwidth measured as
the difference between the upper and lower frequencies at
which 0.25% distortion was obtained while the amplifier was
delivering 30W.
Gain-Bandwidth Product: The Gain-Bandwidth Product is
a way of predicting the high-frequency usefulness of an op
amp. The Gain-Bandwidth Product is sometimes called the
unity-gain frequency or unity-gain cross frequency because
the open-loop gain characteristic passes through or crosses
unity gain at this frequency. Simply, we have the following
relationship: ACL1 x f1 = AcL2 X f2
Assuming that at unity-gain (ACL1 = 1 or (0 dB» fu = fi =
GBWP, then we have the following: GBWP = AcL2 X f2
This says that once fu (GBWP) is known for an amplifier,
then the open-loop gain can be found at any frequency. This
is also an excellent equation to determine the 3 dB point of
a closed-loop gain, assuming that you know the GBWP of
the device. Refer to the diagram on the following page.

MusiC Power: A measurement of the peak output power
capability of an amplifier with either a signal duration suffiCiently short that the amplifier power supply does not sag
during the measurement, or when high quality external power supplies are used. This measurement (an IHF standard)
assumes that with normal music program material the amplifier power supplies will sag insignificantly.
Peak Power: Most commonly referred to as the power output capability of an amplifier that can be delivered to the
load; specified by the part's maximum voltage swing.

1.101

•

Definition of Terms (Continued)
Blampllflcatlon: The-technique of splitting the audiofreQuency spectrum into two -sections and using individual
power amplifiers to drive a separate-woofer and tweeter.
Crossover frequencies for the amplifiers' us",ally vary between 500 Hz and 1600 Hz. "Biamping" has the advantages of allowing smaller power amps to produce !l given
sound pre,ssure level and reducing distortion effects prodused bY, overdrive in one part of ,the ,frequency spectrum
affecting the other part., ,

This ref8fS to,a weighted noise measurement for-a, Dolby B
type noise reduction system. A filter characteristic Is used

that gives a closer correlation Qf the measurement with the
subjective annoyance of noise to the ear. Measurements
made with this f~ter cannot ,necessarily be related ,to unweighted noise measurements by some fixed conversion
factor since the answers obtained will depend on the spectrum of the noise source.
s.P.I,.: Sou,nd Pressure'Level.:...usuallY measured with a microphone/meter combination calibrated to a pressure le,vel
of 0.0002 ""Bars (apprQxJmatllly the threshold heari(1g level).
,
S.P.L. = 20 Lpg,10P/0.ooQ2 dB
'
where P is the R.M.S: sound pressure in microbars.'
(1 Bar =1 atmosphere =,14.5Iblln2,= 194dB S.P.L.).

c.CJ.R.iA;R.M.:
Literally: International Radio cQnsul1ative Committee
Average Responding Meter,'
"

DOMINATE POLE OF ,
(THE OPEN-LOOP RESPONSE

I

OPEN-LOOP VOLTAGE GMN"
,A' (dB)
Ac'.!.

'I'

,

,L~

-

I
' AC GAIN
_1- _ _
,
:
I
LO~S =

t

, 'I:1_,

,",L
A,c (- -

-II - - - - - -

~20 dB/DECADE

UNITY-GAIN FREQUENCY
l ' O f TH,E,, OP AMP

(UNI1:Y GAIN) 0 dB ............_ _+1- - - ; - - - ' - - - '

'p

'2

'1

lu

INPUT FREQUENCY. F(LOG SCALE)
TlIH/11nS-16

1-102

t!lNational Semiconductor

LM2877 Dual4W Audio Power Amplifier
General Description
The LM2B77 is a monolithic dual power amplifier designed
to deliver 4W/channel continuous into 80 loads. The
LM2877 is designed to operate with a low number of external components, and still provide flexibility for use in stereo
phonographs, tape recorders and AM-FM stereo receivers,
etc. Each power amplifier is biased from a common internal
regulator to provide high power supply rejection and output
Q point centering. The LM2877 is internally compensated
for all gains greater than 10, and comes in an 11-lead single-in-line package.

Features
• 4W/channel
• - 68 dB ripple rejection, output referred
• -70 dB channel separation, output referred

•
•
•
•
•

Wide supply range, 6-24V
Very low cross-over distortion
Low audio band noise
AC short circuit protected
Internal thermal shutdown

Applications
•
•
•
•
•
•
•

Multi-channel audio systems
Stereo phonographs
Tape recorders and players
AM-FM radio receivers
Servo amplifiers
Intercom systems
Automotive products'

Connection Diagram
(Slngle-ln-Line Package)
BIAS

...!.r.--""\...../r---r--....

OUTPUT'....!.

o

INPUT'...!
FEEDBACK

,....!

*TAB"!
7
FEEDBACK 2 -

o

INPUTZ..!

OUTPUTZ

II

....!!

y+..!!L...-_ _ _ _- - '
TLIHI7933-1

Top View
Order Number LM2877P
See NS Package Number P11A
'Pln 6 must be connected to GND.

1-103

Absolute Maximum Ratings
If Military/Aerospace specified devices are required, ".'
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

26V

Input Voltage

O"Cto +70"C

Electrical Characteristics Vs= 20V, T TAB =
Total Supply Current

150"C

Lead Temperature (Soldering, 10 sec.)

260"C

25·C, RL

=

80, Av

. , Cis"'C!itlons

Parameter
Po

25

=
=
=

'.'

1.5

f = 1 kHz, Vs'= 20V
Po =·50 mW/Channel
Po = 1W/Channel
Po = 2W/Channel
f = 1 kHz, Vs = 12V, RL
Po = 50 mW/Channel
Po = 500 mW/Channel
Po = 1W/Channel

=

RL

=

Rejection Ratio

Vs
Vs

Input Offset Voltage

=

0.1 ",F, f

Rs

,

=

=

7V, VRIPP~E

=

=
=

0, CIN

=

=

0.1 ",F, Av

=

Open Loop

DC Output Level

Vs = 20V

%
%
%

=
=

1

%
%
%
Vp•p

-50

-70
-60

dB
dB

-50

-68
-40

dB
dB

2.5

",V

0.80

mV

20 Hz-20 kHz
200

...

80

Input Bias Current
Input Impedance

'.'

120 Hz

1 Vrms
0.5 Vrms

0, f = 1 kHz, RL

1

1.kHz,

=: 20V, VRIPPLE =

Equivalent Input Noise
Rs = 0, CIN = 0.1 ",F, BW
Output Noise Wideband
Rs

Open Loop Gain

50 ",F, CIN

V

Vs-4

80

Output Referred .

mA

W
W
W
W

d.25
0.20
0.15

CF = 50 ",F, CIN = 0.1 ",F, f
Output Referred
Vs = 20V, Vo = 4 Vrms
Vs = 7V, Vo = 0.5 Vrms
CF

Units

50, .

40

Channel Separation

PSRR Power Supply

Max

4.5
3.6
1.9
1.0

0.,1
. .0.07
0.07

=

10"C/W
55·C/W

. 24

4.0

1.8V .
1l1V,RL = 40
12V, RL=:. 80

Output Swing

Noise

Typ

= Ow.

f = .1 kHz"THD ~ 10%, TTAB "" 25·C
Vs = 20V

"

50 (34 dB) unless otherwise specified.

6'

Vs
Vs
'Vs
Distortion, THO

=:'

'

Min

Operating Supply Voltage
Output Power/Channel

-65·Cto t150"C

Junction Temperature
Thermal Resistance
8JC
8JA

±0.7V

Operating Temperature

,

. Storage Temperature

70

dB

15

mV

50

nA

4

9

10

MO
11

V

2.0

V/",s

Power Bandwidth "

65

kHz

Current Limit

1.0

A

Slew Rate

Note 1: For operation at ambient temperature greater than 25°C1 the LM287'1-must'be derated based on a maximum 150"C junction temperature using a thermal

resistance which depends upon device mounting techniqUeS,

"

'1·104

Equivalent Schematic Diagram

=

..
r-----....,t--4""':>!
N

,

w
w

II.

I

.....
N

.

...-----It-o()E
"+

...

..

r-----~I_O()~

"+

III

1'-105

Typical Performance Characteristics
Device Dissipation vs
Ambient Temperature

,.

ALU_TIIICICNIII-1111I1CM

.~••• I..r~~:...

')(t-U:~,;" u'e/.

1.h1.4"31·C/~~

~I

:~:::::~.\'

.J::"'I........

,~

..·CJW

I

I I

I-R-LMIIIi1'Hiiiiinl--+1tH1tItI

i:

i
..

I

40

.' I.

5
i

..

•

II!

c

-

a

1.

IZ

14

..•8
I:!

:,\;HI~HANNELS DRIVEN

8DO

!II
I'"

..

tiJillnlllll

~,~. O=F

40
I.

18

.k

180

lllll

••

C:~ ~1~~Il..J ~F
IIIIII~

10

II
10k

Ik

100

IDDk

FREQUENCY (H,.

FREIlUEIICY (lbl

Total Harmonic Distortion
vs Frequency

Total HarmoniC Distortion
vs Frequency

z.

I-- I--

10

~co

.Iii
co

V

Ii
co

Ic

V

0.1

"~
~

..
o

D.5 1.1 1.6 Z.I U

100

3.0 3.6 4.0.

PDW£R OUTPUT twlCHANNELI

I I
I I

RLOln

ZDV

,,;'

1~I'V
~iV T'"
o

IIV

THO-3%

~
~

"""

THO-III%

I I

II

I
POWER OUTPUT (w/CHANNELI

.k

10k

lOOk

0.01

I.

100

FREQUENCY (H,1

Power I)lsslpatlon vs
Power Output

I

1"1

~IulllL 11

II

co

o

F- e•• • O.I.F

40

IIIIIk

1/

4011

CBYPASS- SO.F
VCC-1V
Vo = 500 .. Vrms
Av'50

711

i.

1,...0- I-"'"

iiii
c zao
=

i

..

vcc-zav
VOUT - 4 Vrm.

10

Channel Separation (Referred)
to the Output) vs Frequency

!

11111

5

18k

lk

ID

caYPAss-I~~~ ~

aD

Average Supply Current vs
Power Output
lID

.00

FREDUENCY (H,)

~~

SUPPLY VOLTAGE (VI

1...

10~~~-++H~-r~1tItI

10k

lk

,.

~

CBYPASSC.N'O••• F
_
VR.PPLE - • V.mo
1-1ZUH,
AV-50

ZI

Channel Separation (Referred)
to the Output) vs Frequency

='"co

VRIPP~E .' 0.1 V,..;

i

1. I-tttffiltl'-1+
FREQUENCY (Hz)

ii

~ ~~R.I',PlE.• ~.~
VR.PPlE - OJ v ....

ZO

8

3G

10

'I.'j.,.

II

ii :
iii

01020314011011070110
la-AMBIENT TEMPBlATUIE lOCI

NO.SE ;d-.!.

!

;

II

Power Supply Rejection Ratio
(Referred to the Output) VB
Supply Voltage

~
II ••

Power SUpply Rejection Ratio
(Referred to the Output) vs
Frequency
711

!:
i

FEMII.·C"

1

a

I

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

Open 1.00p Gain vs·
Freqult!1Cv
..

!..

ii

.."'

!

II

lI!

40

!:i

'"

I"
r-...

Z8

,;'

12

V

I
~

,

~

~

lDk

lOOk

FREQUENCY (Hz)

.IM

V

V'
a

lk

i/

V

to

8
1l1li

.00k

RL -an

VS-2OY
RL -In

10

=-

lDk

Output Swing vs Supply
Voltage
1&

1l1li

Ik

FREQUENCY (Hz)

4

•

I

ro

12

~

ro n

ZU

SUPPLY VOLTAGE (VI

TL/HI7933-3

1-106

Typical Applications
Stereo Phonograph Amplifier with Bass Tone Control

+

T

IOOPF

lk
11k
51l1li

II.

STEREO
CERAMIC
CARTRIDGE

51.

..33pF

1k

+
T'DDPF
TUH17933-4

iii

65

:!.
oJ

~
z
c

.......
'~"'

55

Frequency Response of Bass Tone Control

r- ~ ~ESPONSE
TONE.l'
CONTROL FLAT

45

Yo

C

Z

35

C

...

25

~

15

CD

~

II

MAXIMUM
BOOST

~

1/

./

't'

,

./

4XIMUM
CUT
RESPONSE

I
20

I I

50 100 200 500 lk 2k

5k 1l1li 20k

FREOUENCY (Hz)
TUHI7933-5

1·107

. Typical Applications (Continued)
Stereo Amplifier with Ay = 200
.j

VSo-....,......

,

..

T

.... loak

'.r,

"

U.F

I
I
'I
;~

I . ~

r

,8"1,',, _'.

~ID

TL/H17933-6

i

Non-I~vertlng Amplifier Using Split Supply
if

2k

lOOk

v+jj J-J..
O.I.F ":'

r-I 6

--,
"

I

>"'r:

I

L ____ ~J:
2k

lOOk

TYPICAL SPLIT SUPPLY
TL/H17933-7

1-108

.-----------------------------------------------------------------------------'r
Typical Applications

!II:

N

(Continued)

~

.....

Window Comparator Driving High, Low Lamps
r-~f---------._----._--O~

. lk

LOW

10

TL/H/7933-8

Truth Table

VIN

High

Low

<%V+
%V+ to%V+
>%V+

Off
Off
On

'On
Off
Off

--'

Application Hints
The LM2877 is an improved LM377 in typical audio applications. In the ~M28n. the iniernal voltage regulator for the
input stage is generated from the voltage on pin 1. Normally.
the input common-mode range is within ±0.7V of this pin 1
voltage. Nevertheless. the commcm-mode range can be increased by externally forcing the voltage on pin 1. One way
to do this is to short .pin 1 to the positive supply. pin 11.

The only special care required with the LM28n is to limit
the maximum input differential voltage to ± 7V. If this differential voltage is exceeded. the input characteristics may
change.

Figure 1 shows a power op amp application with Av = 1.
The 100k and 10k resistors set a noise gain of 10 and are
. dictated by amplifier stability. The 10k resistor is bootstrapped by the feedback so the input resistance is domi.nated by the 1 MO resistor.
lOOk
12V

II

> .....--oVOUT

10k

2.7{1.
1M

-12V

TO.'

/l F

TtlHI7933-9

FIGURE 1

1-109

CD

;S

r---------------------------------------------------------------------------~

d

.

:!i pNational

Semiconductor

LM2878 Dual 5 Watt Power Audio Amplifier
General Description

Features

The LM2878 is a high voltage stereo power amplifier designed to deliver 5W/channel continuous into 80 loads. The
amplifier is ideal for use with low regulation power supplies
due to the absolute maximum rating of 35V and its superior
power supply rejection. The LM2878 is designed to operate
with a low number of external components, and still provide
flexibility for use in stereo phonographs, tape recorders, and
AM-FM stereo receivers. The flexibility of the LM2878 allows it to be used as a power operational amplifier, power
comparator or servo amplifier. The LM2878 is internally
compensated for all gains greater than 10, and comes in an
11-lead single-in-line package (SIP). The package has been
redesigned, resulting in the slightly degraded thermal characteristics shown in the figure Device Dissipation vs Ambient Temperature.

•
•
•
•
•
•
•

Wide o~erating range 6V -32V
5W/channeloutput
60 dB ripple rejection, output referred
70 dB channel separation, output referred
Low crossover distortion
AC short circuit protected
Internal thermal shutdown

Applications
•
.•
•
•

Stereo phonographs
AM-FM radio receivers
Power op amp, power comparator
Servo amplifiers

Typical Applications
Frequency Response
of Bass Tone Control

.

..

65

=

BOOST
~
~ ~ESPONSE
55 I -

:s

S1k

C>

SIlk

MAXIMUM

8

........IIM,......+-+<'l1Ok

,~

45

~

TONe.l'
CONTROL FLAT

\/

~

::

:cco

35

.:......

"7 ~ ,....~~~PONSE
AAXIMUM

I

15
20

\

50 100 200 500 lk 2k

5k 11k 20k

FREQUENCY (Hzl

TL/HI7934-2
STEREO
CERAMIC
CARTRIDGE

51k

+

T

'IIPF
TL/H/7934-1

FIGURE 1. Stereo Phonograph Amplifier with Bass Tone Control
1-110

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

35V

Input Voltage (Note 1)

±0.7V

Operating Temperature (Note 2)

O'Cto +70'C

Electrical Characteristics Vs =
Parameter
Total Supply Current

Storage Temperature

+ 150'C

Lead Temperature (Soldering, 10 sec.)

+ 260'C

Thermal Resistance
8JC
8JA

10'C/W
55'C/W

22V, T TAB = 25'C, RL =

Conditions

ao, Av =
Min

Po= OW

Operating Supply Voltage

50 (34 dB) unless otherwise specified.
Typ

Max

Unlta

10

50

mA

6

32

V

5.5
1.3

W
W

0.20

%

Po = 0.5W

0.15

%

Po=2W

0.14

%

Vs - 6V

Vp-p

-50

-70

dB

-50

-60

dB

-60

dB

±13.5

V

10

mV

Equivalent Input Noise
Rs = O,CIN =0.1,..F
BW = 20 - 20kHz

2.5

,..V

CCIR-ARM

3.0

,..V

Output Noise Wideband
Rs = 0, CIN = 0.1 ,..F, Av = 200

o.a

mV

Rs = 510, f = 1 kHz, RL = 80

70

dB

Output Power/Channel

f = 1 kHz, THO = 10%, TTAB = 25'C
f = 1 kHz, THO = 10%, Vs = 12V

Distortion

f = 1 kHz, RL =
Po = 50mW

5

ao

ao

Output Swing

RL =

Channel Separation

CBYPASS = 50 ,..F, CIN = 0.1 ,..F
f = 1 kHz, Output Referred
Vo = 4Vrms

PSRR Power Supply
Rejection Ratio

-65'C to + 150"C

. Junction Temperature

CBYPASS = 50 ,..F, CIN = 0.1 ,..F
f = 120 Hz, Output Referred
VripPle = 1 Vrms

PSRR Negative Supply

Measured at DC, Input Referred

Common-Mode Range

Split Supplies ± 15V, Pin 1
Tied to Pin 11

Input Offset Voltage
Noise

Open Loop Gain
Input Bias Current
Input Impedance

Open Loop

DC Output Voltage

Vs = 22V

10

Slew Rate
Power Bandwidth

3 dB Bandwidth at 2.5W

Current Limit

100

nA

4

MO

11

12

V

2

VI,..S

65

kHz

1.5

A

Note 1: ±O.7V applies to audio applications; for extended range. see Application Hints.
Note 2: For operation at ambient tempsratura greater than 25'C. the LM2878 must be derated based on a maximum t 50'C lunction temperature using a \hennal
resistance which depends upon device mounting techniques.

1-111

II

Ty,pical. Performance Characteristics

10

!:
z

3x31N DO

C'/W.\\

"~""~EATJ........ :',

,3

-

FREE~R"C'W

,1

1

o

. 0

-.
S

;0.,

"

40

~

30

.
.

,I:

;:

~

rrtr

100

Channel Separation
(Referred to the Output) vs
Frequency

I'

t\

111l1li

~

..

.

u

14,18

ZZ

Z6

30

'0.0
5.0

:

Z.O
f.Q

V'

0,6

,.

\.

0.1

~

:\4

ID

"

Rl-lil
VCC" ZZV

50 100 ZOO ,00 lk Zk, 5k 10k ZOk

I~S-IIV
Rl"aSl

10

.

I
;,

1.Q
••

u

I..

...
.
~

>

~

~

80

c,;I,

c

0.1

::!

Irv

..

A~' 5~r-

..

100

~

40

~

zo

0.0'

'.

60 ,'DO 100 600 ,. 2k -ik 10k ZOk

0.11

FREQUENCY (H.I

0.'

1.Q

POWER OUT IW/CHANNELI

Power Output/Channel ~s
SUpply Voltage
RL=an

..-::Ii?'

Open Loop Gain vs
Frtlquency

;::

m·

::&

FREQUENCY (HzI,

'0

RL~IJ

vc~·

0.01

oIfliJlr.·

i!

'Po' 0.5W

-e o.o~

.O~

, \.PrZ.OW

Total Harmonic Distortion
vsPowerOut

ri
. 1 1

./

our

fREQUENCY (HI)

/11/
.YI

10k

~

0.02

:r:..:.t=:

./

,

. 0.01
,ZO

V 50

=
~ D.O~

0.1
0,06

;' E

~V' koo

(

O,Z

!:

-

10

~ 0.2

~

0.5

'c"

'Total Harmonlc'Distortlon
vs Frequ~ncy

,.~

Z,O
I,D

u

SUPPlY VOLTAGE IVI

iii

18,0
6,0

l

iii

10

,.

Total Harmonic Distortion
vii Frequency

.
..~.
.....

JJJJjj

CBYPASS - 58,,¥' "--'
CIN'O.I.F ,
'-110Hz "A,V - 60

10

~

10

FREQUENCY (Hzl

UVrm~,5Iv~. - '

r.:::~lM!IIY.iIH'IttttI--+ttttttH

3G

,I:

FREQUENCY (Hzl

0

i!

40

10k

10

_f-VRIPPLE -1.0 Vrm.

WII

f-::-HtHllll-:HIMIMII--+-++1tHtf

f

1

80
60

60

.. zo

'80

ti
:$

I--t+ttl111J.-+~Ili"'*I=mm

~

i

;:::,""-

ro H • ~ ~'~ ro
lA-AMBIENI lEMP£RA1URE '"C)

r-

68

1

~ .. : !PC/W

Power Supply Rejection
Ratio (Referred to the
9utput) vs SupplyVoll!Ige
70

j

z

;;"""~SS1S

~ ~~,

4

I

70 r-rTTmm--rnT~~~nmn

lS·C/W

6 ~.4~~:=:J.~~~

,:i....

lIlstlo(Rflferred to the' "
Output) vs Frequency'"

I .IoW.tNUM fHIClCNESS ... lI'....CH I
1)(1~~~~/~

'~

';~ow~f Supply j:!ejeCtion "

PoWer Supply ReJeq~ion '
Ratio (Referredtd the' "
auJput) vs Frequency

Device Dlsslpatlonvs' '" " ,,\ ,',."
Ambient Temperature

10i

10
,,!

I,

lk

10k

Il10k

'M

FREQUENCY'(Hzl

Power Dissipation VS
Power Out
.l

.~,

THO" 10%

/

,5

/

"

./

./

.... ~
8

1

'0

V'
'I

'4 18

11

10 12

SUPPLY VOLTAGE (VI

POWER OUTPUT (w/CHANNELI

1-112

TUH17934-3

m
c

.a

:iii!"

I»

CD
~

en

()

J
CD

11

----

5k

v+

3

I»

c:r
c

BIAS

T

I

0/

ii'

...

CO
I»

3

,

~
~

Co>

3Dk

5k

RsUB

5
-FEEDBACK 1

3

GND

6
TAB

4 01
08
+INPUT 1
+INPUTZ

_1
-FEEDBACK 2
TL/H17934-4

8l8~W'

II

CD r-------------------------------------------------------------------------------------~

~

I.....

Connection Diagram

Application:Hints
The LM2878 Is an improved LM378 in typical audio applications. In the LM2878, the internal voltage regulator for the
input stage is generated from the voltage on pin 1. Normally,
the input common-mode range is within ± O.7V of this pin 1
voltage. Nevertheless the common-mode range can be increased by externally forcing the voltage on pin 1. One way
to do this is to short pin 1 to the positive supply, pin 11.
The only special care· required with the LM2878 is to limit
the maximum input differential voltage to ± 7V. If this differential voltage is exceeded~ the input characteristics may
change.
Aguf'8 2 shows a power op amp application with Av = 1.
The 1OOk and 10k resistors set a noise gain of 10 and are
dictated by amplifier stability. The 10k resistor is bootstrapped by the feedback so the input resistance is dominated by the 1 Mfl resistor.

Single-in-Une Package
BIAS
OUTPUT 1

GNO

o

lOOk
15V

ItHe
TUH/7934-5

VINo-_t-"'"'4

Top View
'Pin 6 must be connected to GND.

1M

Order Number LM2878P

See NS Package Number P11A

>-+-OVOUT

2.m

TO"I'F
TL/HI7934-6

FIGURE 2. Operational Power Amplifier, Av

1-114

= 1

External Components (Figure3)

1. R2, R5, R7, R10 Sets voltage gain Av = 1 + R2/R5 for
one channel and Av = 1 + R10/R7 for
the other channel.
2.R4,Ra
Resistors set input impedance and supply bias current for the positive input.

6.C4,ca

1
fL = 21TR4C4

Works with Co to stabilize output stage.
Improves power supply rejection (see
Typical Performance Characteristics).
Stabilizes amplifier, may need to be larger depending on power supply filtering.

3.RO
4.C1
5. C11

Input coupling capacitor. Pins 4 and a
are at a DC potential of Vs/2. Low frequency pole set by:

7.C5,C7

Feedback capacitors. Ensure unity gain
at DC. Also low frequency pole at:
1
fL = 21TR5C5

Works with Ro to stabilize output stage.
Output coupling capacitor. Low frequency pole given by:

a.co
9. C2, C10

1
fL = R11'RLC2

Typical Applications (Continued)
Vs

HZ
1II1II

lOOk

l1Hc

C2

I
I
I

:'1F
2.m
an
RL

Co_

Tl.l'FI~
':'
I

"

un

zan

MOTOR

lOOk

T

O1PF
•

Cl0

~~\
T Co

O•lpF

1

un

-

RIO
R7
51'

+

T

1011k

T

C7
10pF

O1PF
•
TL/H/7934-8

FIGURE 4. LM2878 Servo Amplifier In
Bridge Configuration

TL/H/7934-7

FIGURE 3. Stereo Amplifier with Ay = 200

1-115

•

Typical Applications (Continued)
i~ -

..---o+\r'

',> ':.--

r-.;-o..:"'-"""~"""'+-lk

, , VIN

0/4V+
On
,i '

10,

TL/HI7934-9

FIGURE 5. Window Comparator Driving High, Low Lamps

1"('·

1-116

. ~,

r-------------------------------------------------------------------------.~

~

tt/National Semiconductor

CD

LM2879 Dual8W Audio Amplifier
General Description
The LM2879 is a monolithic dual power amplifier which offers high quality performance for stereo phonographs, tape
players, recorders, AM-FM stereo receivers, etc.
The LM2879 will deliver 8W/channel to an 8n load. The
amplifier is designed to operate with a minimum of external
components and contains an internal bias regulator to bias
each amplifier. Device overload protection consists of both
internal current limit and thermal shutdown.

Features
•
•
•
•

Avo typical 90 dB
9W per channel (typical)
60 dB ripple rejection
70 dB channel separation

•
•
•
•

Self-centering biasing,
4 Mn input impedance
Internal current limiting
Internal thermal protection

Applications
•
•
•
•
•
•
•
•
•
•

Multi-channel audio systems
Tape recorders and players
Movie projectors
Automotive systems
Stereo phonographs
Bridge output stages
AM-FM radio receivers
Intercoms
Servo amplifiers
Instrument systems

Connection Diagram and Typical Application

Stereo Amplifier

Plastic Package

o

11

Y+

10

OUTPUT 2
GND
INPUTZ

9

8

,...

7
6

FEEll8Al;K 2

5

FEEDBACK 1

3
2
1

INPUT 1
GND
OUTPUT 1
BIAS .

•

-,

Ne

111M

'-1 I---_-Qo"""t+
L',.,

..

'Il0l<

+ Co

TDPYIEW
TUH/5291-1

T-"

1D1k

..

II1PIIU-1.-=....~-.......-~-=-t
1.1,,1

Order Number LM2879T
See NS Package Number TA 11 B

II
'TAB must be connected to GND.
Tl/H/5291-2

FIGURE 1

1-117

~

~
N
:::i

....

r-----------------------------------------------------------------------------,
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Seles
Office/Distributors for availability and specifications.
Supply Voltage
35V
Input Voltage (Note 1)
± O. iv
Operating Temperature (Note 2)
O"C to + 70"C

Electrical Characteristics vs';' 2SV, TTAB =
Parameter
Total Supply Current

25°C, Ri. ==

so, Av

Typ

Distortion

f= 1 kHz, RL=80
Po= 1 W/Channel

6
'6

Output Swing

RL=SO
CBYPASS;" 50 p.F, C,N = 0.1 p.F
f = 1 kHz, Output Referred
VO=4Vrms
CBYPASS=50 ~F, C'II/=0.1 p.F
f = 120 Hz, 'Output Referred
Vripple= 1 VrmS
Measured at bc, Input Referred

Open Loop Gain

VS,=2SV

dB

-50

-60

dB

-60

dB

±13.5

V

10

mV

2.5
3.0
0.8

",V
,..V
mV

70

dB

100

nA

.4

MO

14

V

2

V/p.s

Slew Rate
Power Bandwidth

3 dB Bandwidth at 2.5W

..

65

Current Limit
Nota 1: The input voltage range is normally limited

%

-:-70

Input ~ias Current
DC Output Voltage

1

-50

Equivalent Input Noise
Rs=0,C'N=0.1,..F
BW=20 -20kHz
CCIR-ARM
Output Noise Wideband
Rs=O, C'N=0.1 p.F, Av=200
Rs=510,.f= 1 kHz, RL =80
Open Loop

I"~

Vp-p

Split Supplies ±15V, Pin 1
Tied to Pin 11

Input Impedance

V
W

Vs-6V

Input Offset Voltage
Noise

mA

·S
0.05

Channel Separation

Units

Max
65
32 .

'·12,

f=1 kHz, THO=10%, TTAB=25°C

PSRR Negative Supply

1°C/W
.,.43"C/W

50 (34 dB), unleSs otherwise specified.

Po=OW

Output PowerlChannel

Common-Mode Range

=

. Min

Conditions

Operating Supply Voltage

PSRR Positive Supply

·-65°6to +.150°C
15O"C
260"C

Storage Temperature
Junction Temperature
Lead Temp. (Soldering, 10 seconds)
ESO r!lting to be determined.
Thermal ReSiStance
.
IIJC
IIJA

kHz

1.5
to

A

±o.7y w~h respect to pin 1. This range may be _nded by shorting pin 1 to the positive supply,

Nota 2: For operirtion at ambient lemparelure greater lhary 25"C. the LM2879 must be derated basad on a maximum 15O'C junction temperature. Thermal
resistance, junctio~ to case, .is :J'CIW. Thermal resistance, case to ambient, is 4O'C/W.

Typical Performance Characteristics
Device Dissipation vs
Ambient Temperature

Open Loop Gain vs
Frequency

22

NiiHfll-+tIHlIH+ltr'VS'2ZV

H~~~~~+mMR~L'Hm

!.

!

=

01020304010107080

TA-AMIIIENT TEMPERATURE COCI

11~~-r~-r--~~~~

110 rT'TTI11IrTnTllrTTITI1111""'1rT1'111111

2Ii I-+-".;;'IIFI.""ITE;;;,;;HEAT.."S;;,;IINKO;-+-I

2L...-L...-L...-L...-L.....IL.....IL.....IL......J

Power Dissipation vs
Power Output

!:I

•
• ,....

~

l8

Ii

1..

I.

FREQUENCY (HzI

J':...J..THD

1M

~~"

2IV
24V

..,

22V

r-~

~.6vH-+-+-'+=1-kI-HZ-i

2

~
lk

28V

!HI~er·~~,r~+-T~HD-I

• I.

41

1111

r-

rJ :.2KIOV

10

•

10

""=111
,-.-f1+--+1-+--+1-+--+ /Iv
-10
o

1 2 J 4 •

•

7 •

• W

POWER OUTPUT (W/CHANNRI
TLlH/6291-3

1-118

Typical Performance Characteristics
Supply Current vs Output
Power
BOD

l~

70D

fII'

U600

§!f5
u.,

E;

400

80

zl.01JI

70

!ill!!

EI

30

~

o

i
~

Av=50
Rl=BD
vcc=~v

0.5

t~

;a! .
~ 0.02
0.01

I

~~=r
~ '-1\,.

~

POiO'p:r-

"

~

... "

til
z

:ii !
u
'"

CVALUES ARE RIPPLE FiLTER
100
lk
10k
FREOUENCY IHzI

10

Total Harmonic Distortion
V8 Frequency
10

I

II
.!Vs=2OY.Av=50
I.

10

0234567
OUTPUT POWER IW/CHANNELI

Ii

1""

lOOk

m

I!II!

~

III I II

Av=~
~

~

~ ~.02
0.01

i
~

/

~

15
10

Avl~

1=1 kHz
Rl=BIl

20

I....

~

~

V
/

~

/
o

20 50 100 200 500 lk 2k 5k 10k 20k
FREOUENCY IHzI

10

15

20
25
VSUPPLY IVI

30

35

Power Output/Channel vs
Supply Voltage

10

10

!:

ii ~II_I"I

Rl-8D

9 THO=10%

I/'

I

1.0

I.J

I

0.1

I

~ 0.01
0.1
1.0
POWER OUT {W/CHANNELI

lOOk

Output Swing vs Vs

~

Total Harmonic Distortion
va Power Output

IiII

CBYl'ASs=50 ""
50 Vcc=28V
Av=50
Vour=4 Vlms
Rl=BIl
40
10
100
lk
10k
FREOUENCY IHzI

25

' ' ' ' .... _....

0.2
0.1
~ 0.05

20 50 100 200 50D lk 2k 5k 10k 20k
FREOUENCY IHzI

0.01

~CIN =~.Jo1y ""lI\i

60

Total Harmonic DI8tortion
va Frequency
10.0
Rl-BIl
~ 5.0 Po=0.5W
z
52 2.0 Vcc=28V
1.0
a 0.5

b~ !IJ.l ~I

"T"kIJ. i
Tl'm.."'\.

70

co

_i1

~Ih
iii'" 20

1\v=50. Vs=28V. Rl=BIl.I=1 kHz

f-

!z

IJ

I I

60 20 ~F
I I
50

i~ 40

/
II

o

80

!

~~

'I'

::oc 300

Channel Separation
(Referred to the Output)
Frequency

Supply Rejection V8
Frequency

,-

I"

500

iI:

IL

(Continued)

10

•

~
1

o

I"
& 810121416182022242&28

SUPFLY VOLTAGE IVI
TLlH/5291-4

1-119

LM2879

m
.a

c
~
CD

:::J

W

::r
CD

-

3
I»

( ;'

c

iii'

co
DJ

3

..:;.
~

~

4.61 c)a

5
-F~EDBACK

1

+INPUT 1

+INPUT 2

7
.-FEEDBACK 2

. GND09
TL/H/5291-.5

!i:

Typical Applications

N

CD

......

CO

Two·Phase Motor Drive

o

C2
0.1 pF

Ne

Rl
27k

C5

~

R3'

271<
2.7

R4

R7

2700

1011

TO.

TO"I'F
~

l 1'F

~

TL/H/5291-6

12W Bridge Amplifier
0.1,.F

SIGNAL
INPUT

----II 1 - - -.....- - - - - - - - - .

I

·IM

~

1M

0.47,.F

10k
TLlH/5291-7

1-121

Typical Applications

(Continued)

Simple Stereo Amplifier with Bass Boost
, '.ft,.F

2.7

1.

r

2k

+

TO.

11

,.

1 1"

0

-r1,.F

"

':'

.INPUT1~
CF

,1I11III

'.I,.F

1

+
-r2ll!,.F

"1'UT2~

10

I
I

1I11III

I

':'

CF
0.1,.F

I.

L

2k

+
l'S,.F

2.7

lOOk

T

0.11"

TL/H/5291-8

Power Op Amp (Using Split Supplies)
1lI0II

,.
10k

2.7

-:c- 0.1 I'F
V-

T
':"

1·122

':'
O.l,.F

TLlH/5291-9

Typical Applications (Continued)
Stereo Phonograph Amplifier with Bass Tone Control
+

Tl00~F
O.33~

lk

':'

10k

I'
~'
':' I

:'19

1M

STEREO
CERAMIC
CARTRIDGE

1M

I ':'
I +
I 1'50~
I
I

5DO~

Vs

m

TO.l~F-

500~

~.'.

:,]m

O.033~

TO.l~5l0k
lOOk

5lk
lk

+

1'100~
TUH/5291-10

Frequency Response of
Bass Tone Control

!

I

&5

..

45

~

35

~

!..

~

L

~
55

25

i: 15

I I I
:t:~UM_ -I-

cri~::O~ S!ESPONSE- -IFLAT

,

~

'4AXIMJM- CUT

'ES~NfE- 1--

I I I.
20 50 100 200 500 1k 2k 5k 10k 20k
FREQUENCY (Hz)
TLlH/5291-11

1-123

~ r---------------------------------------------------------------------------~

~d
~

P

, ...

Nat ion a I S~.",: ico ~"~ u"c

,.

tl? "

LM3875 Overture™ 'AudioPowerAmplifierS~Hes

,

High-Performance 56W Audio Power Amplifier
General Description

',,, ' Features

The LM3875 is a high-performance audio power amplifi~r
capable of delivering 56W of continuous average power to
an 80 load with 0.1 % (THO + N) from 20 Hz-20 ,kHz~'

• 56W continuous average output power into 80
• 100W instantaneous peak output power capability
• Signal-to-Noise Ratio > 95 dB (min)

The performance of the LM3875, utilizing its Self Peak In-< '. Output protection from a short to ground or to the
; 'supplies via internal current limiting circuitry
stantaneous Temperature rKe) (SpIKe) Protection Circuit•
Output over-voltage' prote,ctlon against transients from
ry, puts it in a class above discreteiand hybrid amplifiers by
in~uctlve: I?~d~:,
, ,.~'
providing an inherently, dynamically protected Safe Operating Area (SOA). SPIKe Protection means that these parts' • Supply uni:ler-voltage protect jon, not allowing internal
biasing to occur when IVEEI +, Ivccl ,,; 12V, thus elimiare completely safeguarded at the output against overvoltnating turn-on arid tum-off transients
age, undervoltage, overloads, including shorts to the sup., ,1 qead JO-220 ,pack,age
plies, thermal runaway, and instantaneous temper~ture
peaks.
" "
,

Applications

The LM3875 maintains an excellent Signal-to-Noise Ratio of ,
'
greater than 95 dB(min) with a typical low noise floor of' • Component stereo
.. COmpact stereo
:
2.0 p.V. It exhibits extremely low (THO + N) values of
0.06% at the rated output into the rated load over tlie ,,"udio ",. Self~powere,d speakers
spectrum, and provides Eixclillient lihearity with an iMO
IJ" Sllrround-spur;ld ,amplifier~,
(SMPTE) typical rating of 0.004%.
• High-end steted, tvs
'
"

, Connection Diagram

Typical Application
,
V+

......
Plastic Package (Note 8)

INPUT

:t

11
10

Ra 1 kn

9
II)

.....

10knl

0
Rt.

sn

CD

8
7

CO)

...

:E

4
3

Ne
Ne
Ne
VIN VIN +
Ne
Ne
VOUTPUT
Ne
V+
TLlH/11449-2

Rff 20

Top View

kn

"

Ri
1 kn
• ~" '1 •

.! .,

FIGURE 1. Typical Audio Amplifier Application Circuit
·Optional components dependent upon specific design requiremehts. Refer to

nents Description section for a component function description.

1he External Oompo"J~:

1-124

Order Number LM3875T or LM3875TF
See NS Package Number TA 11 B for
Staggered Lead Non-Isolated
Package or TF11B for Staggered
Lead Isolated Package

Absolute Maximum Ratings (Notes 1, 2) ,
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Iv+ I ~ lv-I (No Signal)
Supply Voltage Iv+ 1'+ lv-I (Input Signal)
Common Mode Input Voltage

94V

84V
(V+ or V-·) and
Iv+1
lv-I,,; 80V,

+

Differential Input Voltage

60V

OutpUt Current

Internally Limited

Power Dissipation (Note 3)

125W

ESD Susceptibility (Note 4)

2500V

Junction Temperature (Note 5)

150"C

Soldering Ihformation
T package (10 seconds)

260"C

Storage Temperature

-40'Cto + 150"C

Thermal Resistance
6JC
6JA

1'C/W
43'C/W

Operating Ratings (Notes 1, 2)
Temperature Range
-20'C"; TA ,,; +85'C
TMIN ,,; TA"; TMAX
20Vto84V
SupplyVoltagelV+1 + lv-I
Note: .operation is guaranteed up to 84V, however, distortion may be intra·
duced from the SPIKe Protection Circuitry when operating above 70V
H proper thermal considerations are not taken into account Refer to
the Thermal Considerations section for more information, (See SPIKe
Protection Response)

Electrical Characteristics (Notes 1, 2) The following specifications apply for V+ = + 35V, V- = -35Vwith
RL = 80 unless otherWise specified. Limits apply for T A == ;;!5'C.
' '
LM3,875
Pa~ameter

Symbol

Conditions

Typical
Limit
(Note 6) (Note 7)

Iv+1 + lv-I Power Supply Voltage
··P.o ..

Output Power (Continuous Average)

THD + N = 0.1% (Max)
f=1kHz,f=20kHz

PeakPe

Instantaneous Peak Output Power

THD+ N

Total Harmonic Distortion Plus Noise

40W, 20 Hz ,,; f ,,; 20 kHz
AV = 26·dB

"SR

Slew Rate (Note 9)

VIN = 1.414 Vrms, f = 10 kHz
Square-wave, RL = 2 kO

56

Units
(Limits)

20
84

V (Min)
V (Max)

40

W(Min)

100

W

0.06

%

11

5

VI,..s(Min)

30

70

mA(Max)

1

10

mV(Max)

*1+

Total Quiescent Power Supply Current VCM = OV, Ve = OV, 10 = 0 mA

'Ves

Input Offset Voltage

VCM = OV, 10 = 0 mA

19

Input Bias Current

VCM = OV, 10 =

a mA

0.2

1

,..A(Max)

0.01

0.2

,..A(Max)

6

4

A (Min)

1.6
2.7

5
5

V (Max)
V (Max)

120

85

120

85

los

Input Offset Current

VCM = OV, 10 = 0 mA

10

Output Current Limit

Iv+ I = lv-I = 10V, ton = 10 ms, Ve = OV

'Vod

Output Dropout Voltage (Note 10)

Iv+ - Vol, V+ = 20V,I o = +100 mA
Ivo - V-I, V- = -20V,l o = -100 mA

*PSRR

Power Supply Rejection Ratio

V+ =
Vcm =
V+ =
Vcm =

40Vto20V, V- = -40V,
OV,lo = 0 mA
40V, V- = -40Vto -20V,
OV,lo = 0 mA

dB (Min)

'CMRR

Common Mode Rejection Ratio

V+ = 60Vto20V, V- = -20Vto -60V,
Vcm = 20Vto -20V,l o = 0 mA

120

80

dB (Min)

*AveL

Open Loop Voltage Gain

Iv+1 = lv-I = 40V, RL = 2 kO, /). Ve = 60V

120

90

dB (Min)

GBWP

Gain-Bandwidth Product

Iv+1 = lv-I = 40V
fe = 100 kHz, VIN = 50 mVrms

8

2

MHz (Min)

'*eIN

Input Noise

IHF - A Weighting Filter
RIN = 6000 (Input Referred)

2.0

8.0

,..V(Max)

'DC Electricat Test; refer to Test Circuit #1.
"AC Electrical Test; refer to Test Circuit #2,

Electrical Characteristics

(Notes 1, 2) The following specifications IlPplyforV+ =

Rl = 80 unless otherwise specified. I-irnits apply for TA = 25°C.

+ 35V, 'y-

... LM:J875
Symbol

SNR

IMD

Parameter

Signal-to-Noise Ratio

Interrnodulation Distortion Test

= -35V With

(Contin~ed)

Conditions

Typical
(Note Ii)

Llrnlt
(Noten

Units
(Umits)

Po = 1W, A-Weighted,
Measured at 1 kHz, Rs = 250

98 dB

dB

Po = 40W, A-Weighted,
Me~ured at 1 kHz, Rs = 250

114dB

dB

Ppk= 100W, A-Weighted,
Measured at 1 kHz, Rs = 250

122dB

dB'

60 Hz, .., kHz, 4:1 (SMPTE)
60 Hz, 7 kHz, 1:1 (SMPTE)

0.004
0.006

%

..

'DC Electrical Test; refer tc Test Circuit # 1.
"AC Electrical Test; refer tc Test CireuH #2.
Note 1: All voltages are measured with respect to supply GND, unless othe(wise specified.
Note 2: AbsoIul9 Maximum Ratings indicate IImRs beyond which damage io the device may occur. Opsrsting Rslfngs indicate conditiol)S for which the devica is
functional, but do not guarantee specifIC performance limits. E/ecIricsI Chsrscterlstics stste DC and AC electrical specHicatlcns under particular test condilioris
which guarantee spaclfic performance limRs. This assumes that the device is within the Oparating Ratings. Specifications are not guaranteed for parameters wihere
no limit is givlln, however, the typical value is a good indication of device performance.
Nota 3: For oparating at case temperatures above 25"C, the device must be derated based on a 150'C maximum junction temperature and a thermal reslstsnce·of
9JC = 1.O'C/W Ounction tc case). Refer tc the Thermal Resistance figure In the Application Information section under Thermal Considerations.
'Nots 4: Human body model, 100 pFdischarged through a 1.5 kO resister.
Nots 5.: The operating junction temperature maximum is 150'C, however, the instsnteneous Safe Operating Area temperatUre is 25O'C;
Nota 6: Typlcals are measured at 25"C .and represent the parametric norm.
Note 7: Limits are guaranteed to National's AOOL (Average Outgoing Quality Level).
Nota 8: The LM3875T package TA 11 B is a non·isoIated package, setting the tab of the device and llie heet sink at V.: Potential when the LM3875 Is direCtly
mounted tc the heat sink using only thenmal compound. If a mica washer is used in addition tc thenmal compound, 9cs (case tc sink) is increased, but the heat sink
will be isolated from V- .
Note 9: The feedbeck compansation network IImHs the bandwidth of the closed·loop response and so the 81_ rate will be reduced due tc the high frequency roll·
off. Without feedback compensation,the sI_ rate is typically 16V1,...
.
.
Nots 10; The output dropout voltage is the supply voltage minus the clipping voltage. Refer tc the Clipping Voltags vs. Supply Voltage graph in the Typical
Performance CharacteriisllcB section.

1-126

I

Test Circuit # 1 ·(DC Electrical Test Circuit)
24.9 kll

200 kll

OUTPUT

50 kll

49.911

49.911

SOURCE
TLlH/11449-3

Test Circuit # 2 (•• AC Electrical Test Circuit)
Ri 1 kll

Rr1 20kll

Cf 50 pI

Rr2 20 kll

v+

OUTPUT

Cc

220 pf

SOURCE

R 1011

v-

1-127

1\
2kll

TL/H/11449-4

•

Single Supply Application Circuit
Vi:

INPUT

RA 100 kO

,~~,~~~----~--~
Rt.
80

~1 20 kO

'RSN

Ri

no
'Ci

10j.!F

I

2.70

'<1

50 pi '~2 20 kO

I

'CSN

0.1 j.!F
TL/HI11449-5

FIGURE 2. Typical Single Supply Audio Amplifier Application Circuit
'Optional components dependent upon specHic design requirements. Refer to the External Components Description section for a component function description.

Equivalent Schematic (Excluding active protection circuitry)
V+

0.45
+IN

0---+--1

OUTPUT

-IN

0.45

VTL/H/11449-6

1-128

External Components Description

(Figures 1 and 2)

Functional Description

Components
1.
2.
3.
4.
5.

RIN
RA
CA
C
Rs

6.

'Ce

7.

B.

Ri
'Ci

9.
10.

Rlf
'R'2

11.
12.
13.

°C,
'RSN
'CSN

14.
15.

°L
OR

16.

Cs

Acts as a volume control by setting the voltage level allowed to the amplifier's input terminals.
Provides DC voltage biasing for the single supply operation and bias current for the positive input terminal.
Provides bias filtering.
Provides AC coupling at the input and output of the amplifier for single supply operation.
Prevents currents from entering the amplifier'S non-inverting input which may be passed through to the load
up.;m power-down of the system due to the low input impedance of the circuitry when the under-voltage
circuitry is off. This phenomenon occurs when the supply voltages are below 1.5V.
Reduces the gain (bandwidth of the amplifier) at high frequencies to avoid quasi-saturation oscillations of the
output transistor. The capacitor also suppresses external electromagnetic switching noise created from
fluorescent lamps.
Inverting input resistance to provide AC Gain in conjunction with Rll.
Feedback capacitor. Ensures unity gain at DC. Also a low frequency pole (highpass roll-off) at:
fc = 1/(2'11" Ri Ci).
Feedback resistance to provide AC Gain in conjunction with Ri.
At higher frequencies feedback reSistance works with Ct to provide lower AC Gain in conjunction with Rf1
and Ri. A high frequency pole (Iowpass roll-off) exists at:
fc = [Rf1 RI2](S + 1IRI2 Ctl 1[(Rf1 + RI2)(S + 1ICt (Rf1 + R,2l)J.
Compensation capaCitor that works with Rf1 and RI2 to reduce the AC Gain at higher frequencies.
Works with CSN to stabilize the output stage by creating a pole that eliminates high frequency oscillations.
Works with RSN to stabilize the output stage by creating a pole that eliminates high frequency oscillations.
fc = 1/(2'11"RSN CSN).
Provides high impedance at high frequencies so that R may decouple a highly capacitive load and reduce the
of the series resonant circuit due to capacitive load. Also provides a low impedance at low frequencies to
short out R and pass audio signals to the load.
Provides power supply filtering and bypassing.

a

'Optional components dependent upon specific design requirements.

Refer

to the Application Information saclion for more information.

OPTIONAL EXTERNAL COMPONENT INTERACTION
Although the optional external components have specific desired functi.ons that are deSigned to reduce the bandwidth and
eliminate unwanted high frequency oscillations they may cause certain undesirable effects when they interact. Interaction may
occur for components whose reactances are in close proximity to one another. One example would be the coupling capaCitor,
Ce, and the compensation capacitor, Ct. These two components act as low impedances to certain frequencies which will couple
Signals from the input to the output. Please take careful note of basic amplifier component functionality when designing in these
components.
The optional external components shown in Figure 2 and described above are applicable in both single and split voltage supply
configurations.

•
,

1-129

,

Typical Performance Characteristics

,"

Supply Current vs '
, Supply Voltage

SPIKe
Protection Response

Safe Area

100

=:t40V

Vs

""t

Vo = OV
= OA

1\ = a4

"~,,

f,=\kH't

...

\

10
.

'"
.5
~

i
i'"

\

I

\

\

'

<.>

\1'"

\

\..

5ms

10,
20

60

J

125°C

~O

2S oC

o

TC = 25°C
TJ = 2S0 lle
TO-220

7

y0-220

20

~O

30

50

SUPPLY VOLTAGE (tV)

Supply Curre",t vs
Output Voltage

Pulse Thermal Resistance

1J = 2S0 oC
I-~-f----i~+--+ tw = lOOms

I
I

10

TlWE (ms)

Pulse Thermal Resistance

-sooe

Ir
II

20

80

COLLECTOR-EMITTER VOLTAGE (V)

J

I I
I Te =

60

o

OL-~~~~~--~~~

o

80

-+-ttttttK--H+ttttfl

Vs = +20Y +30V .40V
O~~L-L-~~~~~

o

20

40

60

80

10

COllECTOR-EMITTER VOLTAGE (V)

Pulse Power Limit
100

.~
'i'5

~
in

~

i

80

1J ;; 2S00C
tw '" lOOms
TO-220

...

,......

60

,

,

-..

in

'!;!"

75 0 C

20

40

60

iiil

40

I"

o
-so

100

'7

::?

~

~

0,3

..

0,2

~

~

30

SUPPLY VOLTAGE(iV)

35

~o

AT = +5.000 rna

I.......

r-...

0,1

-50

\\
\["-

3

'\,

i

r-

o
25

150

Peak Output Current

= '30V

1\
\

i3

2
20

.3

o.~

100

10
Vs

-.;c

50

CASE TEMPERATURE ('c)

PULSE WIDTH (mo)

.J
y

;::;::

v51 = 'l'oV 1--

o

10

"

uov

lv5 = HOV

20

Te = 125°C

v,,,.,.HEEl

'/

Vs =

Input Bias Current vs
ease Temperature

Clip In9 Voltage (+Vcc )

~ V"
15

60

0,5

Rt. =811

10

~

i3

Tc .. 75°C

0,1

ov

.5

Tc ~ 2,5~~,

~o

=

= OA

-.;c 80

II
II
II

120

Clipping Voltage
vs Supply Voltage
CHpp'"

Vo
~

TO-220

COllECTOR-EMITTER VOLTAGE (V)

:f

100

, 1J = 2S00C

160 1\

80

40

Supply Current vs
Case Temperature

60

~
~

I
I

20

Pulse Power Limit

~

125°C

20

0

OUTPUT VOLTAGE (V)

~

25°C

40

i'5

~'

TC =

~20

PULSE WIDTH (ms)

200

B

-~O

100

100

CASE TEMPERATURE ('C)

150

20V
30V
40V

.. V
-5

-10
50

VC[ ;;

I 5V

30V

'.V

/Ir'
{(V-

....

O.SY

I SV
C.Sms

o
TIWE (ms)

TLlH/II449-7

Typical Performance Characteristics

(Continued)

THO + Nvs
Output Power

THO + N vs Frequency

THO + Nvs
Output Power

50
10

g

i

g

z
+

c

z
+

c

0.1

j!:

j!:

0.010

0.1

Output Power (w)

THO Distribution

THO Distribution

100
90

g
1;

15

~

!:!

~

10

FREQUENCY (Hz)

SO

I I fa =20Hz
I I TA=_25 0 C
I I Vcc ->35V
~-¥4-

SO
70
60

I

50

E

AVG: 0,00824103

1111":0.0012

30
20
10

~

o

o

i

56
48

!:!

32
24
16
8

o

0.004 0.008 0.012 0.016 0.020
0.002

0.006 0.010 0.014

60

=20 kHz

-

:g

40

THD+N (%)

I I
I
I

= 25°C

40

;~O=+±:5~~.O8%
20Hz:::; f:s 20kHz

\.
.......

20

....... 1--.

10
S

10

15

20

25

I\.

(n)

30

THO+N (%)

50

60

70

SO

100

90

35

Maximum Power Dissipation
vs Supply Voltage

110

1.3

1.0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 90 - - - - 50· - - -r-'-"'''''-'-'4-/l''''''s'"'/I:-1:

1.6

1.2

1,-0

1.9

1.6

1.3

96

45
6/1

1.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • 102 - - - • 40 - - - -

2.4

1.9

1.7

1.4

1.1

3.0

2.5

2.1

1.8

1.5

108

3.S

3.2

2.S

2.4

2.0

1.6

1.2

5.1

4.3

3.8

3.3

2.8

2.3

1.8

1.3 ---- - - - - - 126- - - '20- ---

7.1

6.1

5.5

4.8

4.1

3.5

2.8

2.1

1.5

132

11.3

9.8

8.S

7.8

6.8

5.S

4.8

3.S

2.8

138----10---0

II

35

I

120

25

/'

15

' ..

Power Dissipation vs
Output Power

i!i

40

tl

30

~

~

~

'"
!;:
~

0

10

20

30

fo

= 1 kHz

40

50

60

OUTPUT POWER (w)

20HZ S fS2jkHZ

~
e; 50
i£

40

!;

.

5

20

,.
e:

... = 4n

fo = 1 kHz

0

10

20

30

40

OUTPUT POWER (w)

50

60

I

1//

o

0

II

1.1/

30

10
60

II. = sn

... =sn

THD+ NSO.1%

~

0

..

THO + N:S 0.03"
f"" 1 kHz

70

50

,.'"

10

..

Output Power vs
Supply Voltage

80

is

20

I

':

TUH/II449-15

tl

is

.

•

vcc.lv+l+Jv-1

Power Dissipation vs
Output Power

60

50

•
:

10 20 30 40 50 60 70 80 90

Note: The maximum heat sink thermal resistance values, 0 SA. in the table above
were calculated using a 0cs = O.2'CIW due to thermal compound.

60

I

1.1------------------·114----30---/

~

40

TUH/11449-8

Max Heatslnk Thermal Resistance rC/W)
at the Specified Ambient Temperature rC)
TA

ft-

~o 30

-0.025 0.025 0.075 0.125 0.175
-6.946E-19 0.05
0.1
0.15
0.2

0.018

~-

50

1111":0.023

=::1;

100

(w)

Output Power vs
Load Resistance

I\.rt-

- -

10

0.1

Output Power

IAVG:O.03113IU
SIGMA: 0.00709903
MAX: 0.064

40

~

I I I I
I I I I
I I Ll

tOm

TA = 25°C
Vee = >35V

64

~

SIGNA:O.OOO2B0711

MAX:O.OOSI

40

10

n

100

o

",
10

~

15 20 25 30 35 40

SUPPLY VOLTAGE (.v)
TUH/II449-16

1-131

II

Typical Performance Characteristics

~0.00882

E

12.000

I.~~! --,~

E~ 20.0000k ~

...

O. I

1\.

=

·-·IS.46
72!1.62

an

i'

"'38.77
. "48.92

3

t:"

ill.

'

.

"

''','

IMD 60 Hz, 7 kHz, 4:1

IMD6()~Z,4:1
1

(Contirrued)

':l~

0:010

f""-t-t-t-HI-I-HHH
I-t-t-l-Hl-hHHH
I-t-t-t-HI-I-HHH

,..-I-~

-II-,~'-HHH

-69.23
·S9.0S

Ic-H-'4"""
1-1-1-[
. .,..il-.....
j-l-IrlHi

~i9.3S t-I-t-I+

0,010

II,..,................

I.'

FF-f-.1!Fl'-rrHHH

0,001

-109.8
-120.0
'1
a.OOk a.40k'· a.80k .7.2Ok 7.aOk S.OOk
6.20k 6,60k 7.0ak 7.4Dk 7,80k

0.00 I

10k

~AP

f>:-l-l-l-HI'-'-f-HHH

"S9,S4

'-99.7
2k

'

20k

0.0005

0.1'

10

100

Output Power (w)

FREQUENCY (Hz)
fREQUENCY (Hz)

IMD ~ Hz, 7 kHz, 1:1

IMD 60 HlI!,1:1 ,
I

20.000

~ 20.000.0k ~

::::::::j0.020S.6

0, I

-20.00

~

-40.00

,.

. -60.00

3

~

;....-

0.010

~

0.0

1\. = an

IMD 60 Hz, 7 kl;lZ, 1:1

I~AP

~,

-J,

If adequate bypassing is not provided the current in the supply leads which is a rectified component of the load current
may be fed back into internal circuitry. This signal causes
low distortion at high frequencies requiring that the supplies
be bypassed at the package terminals with an electrolytic
capacitor of 470 ,...F or more.

LEAD INDUCTANCE
Power op amps are sensitive to inductance in the output
lead, particularly with heavy capacitive loading. Feedback to
the input should be taken directly from the output terminal,
minimizing common inductance with the load.
Lead inductance can also cause voltage surges on the supplies. With long leads to the power supply, energy is stored
in the lead inductance when the output is shorted. This energy can be dumped back into the supply bypass capacitors
when the short is removed. The magnitude of this transient
is reduced by increasing the size of the bypass capacitor
near the IC. With at least a 20 ,...F local bypass, these voltage surges are important only if the lead length exceeds a
couple feet (> 1 ,...H lead inductance). Twisting together the
supply and ground leads minimizes the effect.

R2

VI = (11 +

URt

v2 = iL (R2 + VI )

LAYOUT, GROUND LOOPS AND STABILITY
The LM3875 is designed to be stable when operated at a
closed-loop gain of 10 or greater, but as with any other high--

TVH/II449-13

1-135

•

Application Information (Continued)
leads·are long. The problem can be .eliminated boy placing a
small capaCitor, Ce,;(on the order of 50 pF",500 pF) across
the LM3875 input'terminals. Refer to the External Components Description section relating to component interaction :~i1h Gj.

The I'oad current JL will be much ,larger than input bias current 11 "thus V1 Will follow the output voltage directly, i.e.; in
phase. Therefore the voltage appearing at the non-inverting
inpl,lt is ,effectively positivE! flledback ,md the circuit may oscillate. If there were only one device to worry about then the
,values of F!1 and R2 'would probably be small enough to be
ignored;'h~wever,several devices normally comprise a total
syste!1l' Any gr<)unc\ {eturn of a sE1Piirate device, whose out~
put is in phalle, can feedbac,k in a similar manner and,cause
instabiliti~. Out, oj phase ground loops also are troubles9me, c~using.!lnel(pected gain ~ndphase,errors.
The,solution to most ground loop problems is,to,always use
a single-point ground' system, although this is '·sometimes
impractical. The thifd figure above is an example of a singlepOint,gr6lund system.,'

REACTIVE LOADING

'0

It. ii:; hard' for most pOwer amplifiers drive, highly capacitive
loads veri effectively and normally results' in oscillations 'or
ringing on the square wave response. If the output' of the
LM3875 is connected directly to a capaCitor with no series
resistance, the square wave response will exhibit ringing if
the capacitance is greater than about 0.2 ""F. If highly capacitive loads are expected due to long speaker cables, a
method commonly employed to protect amplifiers from low
impedances at high frequencies is to couple to the load
through a 10n resistor in parallel with a 0.7 ""H inductor.
The inductor-resistor combination as shown in the Typical
Application Circuit isolates the feedback amplifier from the
load by providing high output impedance at high frequencies
thus allowing the 1on resistor to decouple the capacitive
load and reduce the Q of the series resonant circuit. The LR
combination also provides low output impedllnce at low frequencies thus shorting out the 10n resistor and aliowing the
amplifier to drive the series RC load (large capaCitive load
'
due to long speaker cables) directly.

The single-point ground concept should be applied rigordus-

·Iy to all components and all circuits, when possible. Violations of, single-point grounding are most common among
printed circuit board designs, since the circuit is surrounded
by large ground areas which invite the temptation to run a
device ·to the closest ground spot. As a final rule; make all
ground returns low resistance and, low ind,uctance by l!sing
large wire and, wide traces.
Occasionally, current in the output'leads (which function as
antennas) can be coupled ·through the air ,to the amplifier
input, resulting in high-frequency oscillation. This normally
happens when ,the source impedance is high.or the input

1-136

r-----------------------------------------------------------------------------,~

Application Information

!!:

DESIGN A 40W/SO AUDIO AMPLIFIER
Given:

GENERALIZED AUDIO POWER AMPLIFIER DESIGN
The system designer usually knows some of the following
parameters when starting an audio' amplifier design:

Power Output
Load Impedance
Input Level
Input Impedance
Bandwidth

Input Lel(el
Load Impedance
'Bandwidth

Desired Power Output
Input Impedance
Maximum Supply Voltage

~
~

(Continued)

The power output and load impedance determine the power
supply requirements, however, depending upon the application some system designers may be limited to certain maximum supply voltages. If the designer does have a !;lower
supply limitation, he should choose a practical load impedance which would allow the amplifier to provide the desired
output power, keeping in mind the current limiting capabilities of the device. In any case, the output signal swing and
Current are found from {where Po is the average output
power):

40W

ao

1V(max)

100kO
20 Hz-20 kHz ± 0.25 dB

Equation (1) and (2) give:

40W/80
Vopeak = 25.3V
lopeak = 3.16A
Therefore the supply required is: ± 30.3V @~.16A
With 15% regulation and high line the final supply voltage is
± 38.3V using equation (3}. At this point it is a good idea to
check the Power Output vs Supply Voltage to ensure that
the required output power is obtainable from the device
while maintaining low THD + N. It is also good to check the
Power Dissipation vs Supply Voltage to ensure that the device can handle the internal power dissipation. At the same
time designing in a relatively practical sized heatsink with a
low thermal resistance is' also i,mportant. Refer't9 Typical
Performance 'Characteristics graphs and the Thermal
Considerations section for more information.

.J2"RLi5O

Vopeak =
(1)
lopeak = J(2 Po)/RL,
(2)
To determine the maximum supply voltage the following parameters must be considered. Add the dropout voltage
(5 volts for LM3875) to the peak output swing, Vopeak, to. \let
the supply rail value, (i.e. + Vopeak
Vod) at a current of
lopeakl. The regulation of the supply determines the ljnloaded voltage, usually about 15% higher. Supply voltage will
also rise 10% during hi'gh line conditions. Therefore, the
maximum supply voltage is obtained from the following
equation:
'

+

The minimum gain from equation (4) is: Av ~ 18
We select a gain of 21 (Non-Inverting Amplifier); resulting in
a sensi,tivity, of 894 mV.
Letting R'N' equa! 100 kO gives ihe required input impedance, however, this would eliminate the "volume control"
unless an additional input impedance was plaq!ld il1 series
with the 10 kO potentiometer that is depicted in' Figure 1.
Adding the additional 100 kO resistor would ensure the minimum required input impedance.

max. supplies::::: ± (Vopeak + Vod(1 + regulation)(1.1) (3)
The input sensitivity and the output power specs determine
the minimum required gain as depicted below:
Av ~ (Jpo RLl/(V'N) = VormslVinrms
(4)
Normally the gain is set between 20 and 200; fora 40W, 80
audio amplifier this results in a sensitivity of 894 mV, and
89 mV, respectively. Although higher gain amplifiers provide
greater output power and dynamic headroom capabilities,
there are certain shortcomings that go along with the so
called, ':gain". lh~ input referred noise floor is increased
and hence the SNR is worse. With the increase in" gain,
there is also a reduction of the power bandwidth which results in a decrease in feedback thus not allowing tlie amplifier to respond as quickly to nonlinearities. This decreased
ability to respond to nonlinearities increases the THD + N
,
. '
specification. '

For low DC offsets at the output we let RI1 = 100 kO.
Solving for Ri (Non-Inverting Amplifier) gives the following:
Ri = R'11/(Av - 1) = 100k/(21 -1) = 5 kO; use 5.1 kO
The bandwidth requirement must be stated as a pole, i.e.,
the 3 dB frequency. Five times away from a pole give
0.17 dB down, which is better than the required 0.25 dB.
Therefore:
fL = 20 Hz/5 = 4 Hz
fH = 20kHz x 5 = 100kHz
At this pOint, it is a good idea to ensure that the Gain Bandwidth Product for the part will provide 'the designed gain out
to tlie upper 3 da point of 100 kHz. This is why the minimum
GBWP of the LM3875 is important.
GBWP = Av xf3dB=21 X'100kHz';' 2:1 MHz

Thj3 desired input impedance is set by R'N' Very, high values
can cause board layout problems and DC offsets at the output. The value for the feedback resistance, RI1, should be
chosen ,to be a relatively large value (10 kO-100 kfi), and
the other feeclback resistanCE;!, Ri, is qalculated using standard op amp configuration gain equations. Most audio amplifiers are designed from the non-inverting amplifier config-

GBWP = 2:0, MHz (min) for LM~815
Solving for the low frequency roll-off capacitor, Ci, we have:
Ci> 1/(21T Ri fLl = 7.8 ,..F; use 10 ,..F,

u~ation.

1-137

II

~ r-------------------------------------------------------------------~

~

~

Definition of Terms
Input Offset Voltag!': The absolute,valu~;,oft\1e voltage
which must be applied between the input terminals through
two equal resistances to obtain zero output voltage and current.

Headroom: ,The margin between an act!.!al signal,operati"g
level (usually the, power rating (If the amplifier, with particular
supply v9Itage!;, a'rated ,load value, and a rated THO + N
figure) and the level jiJst befor~ ~Iipping distortion occurs.
el/'presseil in d e c i b e l s . '
'

Input Bias Current: The absolute value 6f the 'aver~g,!l of
the two input currents with the output voltage and current at
zero.,
' ,

Large Signal Voltage Gain: The ratio of the output voltage
swing to, the differential input voltage required to drive the
output from zero 'to' either swing limit. 'l'he-autput swing limit
is the supply voltage less a specified quasi-saturation volt,
age. A pulse ofiihort enough duration to minimize thermal
effects is used as "a measurement signill.

Input Offset Current: The absolute value of the diff~rence
in the two input currents with the ciUtput voitage and current

,

~~~

Input Common,Mode Voltage Range (or Input Voltage
Range): The range of voltages on the input terminals for
which the amplifier is operational. Note that,the specifications are not guaranteed over the' full common-mode voltage range unless specifically stated. '

Output-CurrentUmli~ The output current with a fixed output voltage
a large input overdrive.'The limiting current
drOps witli time once SPiKe protec~on circuitry ,is activated.

and

Common-Mode Rejection: The nitio of the input commonmode voltage range to the peak-ta-peak change in input
'"
offset voltage over this 'range.

qutput Satu....tlon Thre.;hold (CUpping p~lnt): Th~ output
swing limit for a specified input drive beyond that required
for zero output. It is measured with respect to the supply to
which the output is swinging.

Power supply ReJection: The ~atio of the change in input
offset voltage to the, c~ange in power supply, voltages producing it. '
,
"

Output Retslstance: The ratio of the change in output voltage to the charige in output current with the output around
zero:
'

Quiescent Supply Current: Th~ ~~rrent r8quired from' the
power supply to operate the amplifier with no load and the
out'put voltage and current at

Power Dlssipatlon'lfating: The power that can be dissipated for a,sp6cifie,d tilJ'l8 interval without activating the protection circuitry. For tim~ 'i~tervals)n e~cess, 011 00 ms, dissipation cap~bility is determined by hea, \linking of the IC pa~k~
a!l;e rather than by th~ IC itself.
"
"
"

zero.'

,

Slew Rate: The internally limited rate cit' ch~nge in output
voltage with a large amplitude step function 'applied to the
input.

Thermal Resistance: The peak. junction-tem'perature rise.
per unit of inter!'lal power dissipation (units in ·C/W), above
measured at the Center of the
the case temperature
package bottom.

Cla,ss B AriJpllfler: the moSt c:ommon type 6faudio power
amplifier that ,consists ,of two Qutput deviqes each of which
conducts for 180" of the input cYcle~ ,he lM3875 is a
Quasi-AB type amplifier.
'

as

The DC thermal reSistance applies when one output transistor is operating continuously. The Ac thermal resistance applies with the output transistors conducting alternately at a
high enough frequency that the peak capability of neither
transistor is exceeded. :

Crossover Distortion: DistortiOn caused in the output
stage of a class '13 amplifier. It c~n result from inadequate
bias current providing a dead zorie where the output does
not respond to the input as the input cycle goes through its
zero crossing pOint. Also for 'Ies an inadequate frequency
response of the output PNP device can cause a" turn-on
delay giving crossover distortion on the negative going transistion through zero crossing at ,the higher audio frequencies.

Power Bandwidth: The power bandwidth of an audio amplifier is tife frequenCy range over which the amplifier'voltage gain does ncit fall below 0.707 of the flat band voltage
gain specified for given load and output power. '

a

THD + ,N: Total !iarmoni~ Pistortion PlUS' Noise refer:li\ to
the measurement technique in,which the fundamenll!.1 eamponent is removed by a bandreject (notch) filter and all remaining energy is measured including harmonics arid noise,

,'.,:

can

be measured by the" frequencies
Power l;lancNvidth alSo
at which a specified level of distortion is obtained while the
amplifier deiiilers a pOwer output de below the rated output. For example, ail amplifier rated allloW viit~ :";0.2~%
THO + N. would make its power bandwidth measured;as
the difference between the upper and lower frequencies at
whicil' 0.25% diiitortion was obtained while the amplifier was
delivering 30W. ' , ,
' "
-, " '

:3

Signal-to-Nolse ~atio: The ratio of a system's output Signal
level to the syst~I)1's output noise level obtained in the absence of a' signal. The output reference signal is either
specified cir measured at a specified distortion level.

Gain-BandWidth Product: The Gain-Bandwidth Product is
a way of predicting the high-frequency usefulneSs Of an op
amp. The Galn-Bandwidth Product is sometimes called the
unity-gain frequency; or unity-gain cross frequency because
the open-loop gain characteristic passes through or crosses
unity gain at this frequency. Simply. we have the following
relationship:

Continuous Average Output Power: 'The minimum sine
wave continuous average power output in watts (or dBW)
that can be delivered into the rated load, over the rated
bandwidth, at the rated maximum total harmonic distortion.
MusiC Power: A measurement of the peak output power
capability of an amplifier with either a Signal duration sufficiently short that the amplifier power supply does not sag
during the measurement, or when high quality external power supplies are used. This measurement (an IHF standard)
assumes that with normal music program material the amplifier power supplies will sag inSignificantly.

AcL1 X f1 = ACL2 X f2
Assuming that at unity-gain
(AcL1 = 1 orO dB) fu = f1 = GBWP,
then we have the following:
GBWP = AcL2 X f2

Peak Power: Most commonly referred to as the power output capability of an amplifier that can be delivered to the
load; specified by the part's maximum voltage swing.
1-138

Definition of Terms (Continued)
This says that once fu (GBWP) is known for an amplifier,
then the open-loop gain can be found at any frequency. This
is also an excellent equation to determine the 3 dB point of
a closed-loop gain, assuming that you know the GBWP of
the device. Refer to the diagram below.
BI-ampllflcatlon: The technique of splitting the audio frequency spectrum into two sections and using individual
power amplifiers to drive a separate woofer and tweeter.
Crossover frequencies for the amplifiers usually vary between 500 Hz and 1600 Hz. "Biamping" has the advantages of allowing smaller power amps to produce a given
sound pressure level and reducing distortion effects produced by overdrive in one part of the frequency spectrum
affecting the other part.

C.C.I.R./ A.R.M.:
Literally: International Radio Consultative Committee
Average Responding Meter
This refers to a weighted noise measurement for a -Dolby B
type noise reduction system. A filter characteristic is used
that gives a closer correlation of the measurement with the
subjective annoyance of noise to the ear. Measurements
made with this filter cannot necessarily be related to unweighted noise measurements by some fixed conversion
factor since the answers obtained will depend on the spectrum of the noise source.
S.P.L.: Sound Pressure Level-usually measured with a microphone/ meter combination calibrated to a pressure level
of 0.0002 ,...Bars (approximately the threshold hearing level).
S.P.L. = 20 Log 1OP10.0002 dB
Where P is the R.M.S sound pressure in microbars.
(1 Bar = 1 atmosphere = 14.5 Ib.lin2 = 194 dB S.P.L.).

DOMINATE POLE OF
(THE OPEN-LOOP RESPONSE
AVOL

- - - - DC GAIN
I

OPEN-LOOP VOLTAGE GAIN
I
I
A (dB)
AcL2 - - -:-

I

-r-

AC GAIN
LOSS

I
I
AcL1 - - -1- - - -I - - -

= -20 dB/DECADE

I

UNITY-GAIN FREQUENCY
.J
0F THE OP AMP

I

I-I

fp

12

(UNITY GAIN) 0 dB L---'-_ _-;-_ _~~"---'

11

fu

INPUT FREQUENCY, F(LOG SCALE)
TLlH/11449-14

II

1-139

U)

r-~~~------~~----~--~----~--------~~~~--~~----------~-------------'

i
d
~ P ~ a t ion ~'

Semi

<;f"O

n due tor

.~ \ ; I

LM3876 Overtu,re™AUdiO power ~~plifier se~~~
H,igh-PerfflrmanCe ,56W Auciio Power AmplifietwIMute" ,
.,;'

General Description

Features

56W continuous average,o\ltput po~~r int({8!}',
100W illlltantaneQus pe~k output pOWllr' capabil,ity 'I
Signal-to-Noi~e Ratio :;;, 95 dB (min)
,
An input mute function
Output protection from a short to ground or to the supplies via internal current limiting circuitry
Output over-voltage protection against transients from
inductive loads
Supply under-voltage protection, not allowing internal
biasing to occur when IVEEI + IVeel ,;;; 12V, thus eliminating turn-on and turn-off transients
• 11-lead TO-220 package

•
•
•
.,1.
•
The performance of the LM3876, utilizing 'its Self Peak In- '
•
stantaneous Temperature rJ 0.5 mA,
Mute: Off

120

80

dB (min)

THD + N = 0.1% (max)
f = 1 kHz;f = 20kHz

56

40

W(min)

'"

Peak Po

instantaneous Peak Output Power

THD+ N

Total Harmonic Distortion Plus Noise

40W, 20 Hz ,;;; f ';;;,20 kHz
Av = 26dB

··SR

Slew Rate (Note 9)

VIN = 1.2 Vrms, f = 10 kHz,
Square-Wave, RL = 2 kn

'1+

Total Quiescent Power Supply Current VCM = OV, Vo = OV,lo = OA,lmute = OA

'Vos

Input Offset Voltage

VCM = OV, 10 = 0 mA

18

Input Bias Current

VCM = OV, 10 = 0 mA

los

Input Offset Current

VCM =OV, 10 ,,;; 0 mA

10

Output Current Limit

Iv+1 = lv-I = 12V, toN = 10 ms, Vo = OV

6

4

A (min)

'Vod

Output Dropout Voltage (Note 11)

Iv+ -Vol, V+ = 20V, 10 = + 100 mA
Ivo-v-I, V- = -20V,l o = -100 mA

1.6
2.7

5
5

V (max)
V (max)

'PSRR

Power Supply Rejection Ratio

V+ = 40Vto 20V, V- = -40V,
VCM = OV, 10 = 0 mA
V+ = 40V, V- = -40Vto -20V,
VCM = OV, 10 = 0 mA

120

85

d8(min)

120

85

dB (min)

'DC Electricsl Test; refer to Test Circun #1.
uAC Electrical Test; refer to Test Circuit #2.

1-141

100

W

0.06

%

11

5

V//Ls (min)

30

70

mA(max)

1

15

mV(max)

0.2

1

/LA (max)

0.01

0.2

/LA (max)

,

Electrical Characteristics

"
i,
','
(Notes 1, 2)
The following specifications apply forV+ = ,t35V, V- "7 -35V,IMUTE = -0.5 mA with RL = 8.0. unless otherwise specified.
'"
Limits apply for T A = 25°C. (Continued)

LM3876
Symbol

°CMRR

Parameter

Common Mode Rejection Ratio

V+ = 60Vto20V, V- =, -20Vto -60V,
VOM = 20Vto -20V,l o = 0 mA

°AVOL

Open Loop Voltage Gain

GI;IWP

Gain-Bandwidth Product

Iv+1 = lv-I = 40V, RL =2 k.o."aVo = SOV
Iv+1 = IY-I = 40V
f6 = 100 kHz, VIN = 50 mVrms

.oeIN,

Input Noise

IHF-A Weighting Filter
RIN ;", 600.0. (Input Referred)

SNR

Signal-to-Noise Ratio

Po = 1W, A-Weighted,
Measured at 1 kHz, Rs = 25.0.
Po =' 40W, A-Weighted,
Measured at 1 kHz, Rs = 250
Ppk= 100W, A-Weighted,
Measuredaf 1 kHz, Rs = 250

IMD

Intermoduiation Distortion Test

"

Units

Conditions

Typical

Limit

(Note 6)

(Note 7)

120

80

dB (min)

120

90

dB (min)

8

2

MHz (min)

2.0

8

",V (max)

(Limits)

98

dB

114

dB

122

dB

60 Hz, 7 kHz, 4:1 (SMPTE)

0.004

60 Hz, 7 kHz, 1:1 (SMPTE)

0.006

%

'DC Electrical Test; refer to Test ClrcuH # I .
.. AO Electrical Test; refer to Test ClrcuH # 2.
N0i'! 1: All voltages are measured with respect to the GND pin (pin 7),

u~less

otherwise specHied.

Note 2: Absoluts Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specHic performance limits. Electrical CharactarislicS state DC and AC electrical specHlcations under particular test conditions
which guarantee specHic performance limits. This assumes that the device is within the Operating Ratings. SpecifICations are not guaranteed for parameters where
no limit Is given, however, the typical value Is a good Indication of device performance.,
Note 3: For operating at case temperatures above 25'C, the device must be derated based on a 15O"C maximum junction temperature and a thermal resistance of
9JC = 1.0 'C/W ijunction to case). Refer to the Thermal Resistance figure in the Application Information section under Thermal Con.~rallon..
Nole 4: HUl)1an bOdy model, 100 pF discha,.ged through a I.S k!l resistor.
NOle 5: The operating junction, temperature maximum is ISO'C, however, the instantaneous Safe Operating Area temperature is 2SO'C.
Nole 6: Typicals are measured at 2S'C and represent the parametric norm.
Nole 7: Umits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: The LM3876T package TAIIB is a non-isolated peckage, setting the tab of the devieS and the heat sink at V- potential when the LM3876 Is direclly
mounted to the heat sink using only thermal compound. If a mica washer is used in addHion to thermal compound, 9cs (case to sink) Is Increesed, but the heat sink
, will 'be isolated from V-.
NotS' 9: The feedback corripensation netWork limits the bandwidth of the closed-loop ~esponse and so the slew rate will be r8duced due to the high irequency rOlIoff. Wlthou! feedback compensation, the slew rate is typically 16V1 ,",S.
Note 10: V- must have at least'-9V at Hs pin wHh reference to gr<\Und in order for the

~nder-voltage

protection circuHry to ba disable.

3

~

I
I
I

r80 r70
60
50

CC-

--

10

g
~

.';'0.;028,

I

!

I I I I
I I I I
ILL
0.006

0.010

0.01-4

Output Power vs
Load Resistance

50
45

60

40

50

~
Q...0

15
10
5
0

0.004 0.008 0.012 0.016 0.020
0.002

r-- - ~~o=+t:5~D~.08"

~ r--

.0

20Hz:s; f:s; 20kHz

-

\..

30

"'

20
10

0.04

0

0.018

100

10

OUTPUT POWER (W)

35
30
25
20

i

SIGNA: 0.000756119
IoIAX:O.OO71

C-

o
o

fo = 20 Hz
TA=25°C
Vee = i35V

f--IAVG:D.D0331296

L....

0.1

THD+ N Distribution

TES"'-Rt =I ~t

--r-c-r-

r40 r30 r20 r-

100

OUTPUT POWER (W)

0.02

THO<" (%)

0.08

0.06

0.12

0.10

0.16

0.14

0.20

5

10

15

20

25

Rt

(a)

0.18

30

35

40

THO

"-

~

80

1\

~

60

DISCRETE

~

---~-

40

1

INTEGRATED CIRCUIT

20

/\
200

2k 6k 20k

rREQUENCY (Hz)

- .....

TUH/11832-14

...
20 200

;;:

...

...o:::;
'"""

! I\

r

Ii:

SUPPLY BYPASSING

2k 20k 200k 2M

The LM3876 has excellent power supply rejection and does
not require a regulated supply. However, to eliminate possible oscillations all op amps and 'power op amps should have
their supply leads bypassed with low-inductance capacitors
having short leads and located close to the package terminals. Inadequate power supply bypassing will manifest itself
by a low frequency oscillation known as "motorboating" or
by high frequency instabilities. These instabilities can be
eliminated through multiple bypassing utilizing a large tantalum or electrolytic capacitor (10 ",F or larger) which is used
to absorb low frequency variations and a small ceramic capacitor (0.1 ",F) to prevent any high frequency feedback
through the power supply lines.

rREQUENCY (Hz)
TL/H/11832-13

Integra:ted circuits have additional open loop gain allowing
additional feedback loop gain in order to lower harmonic
distortion and improve frequency response. It is this additional bandwidth that can lead to erroneous signal-to-noise
measurements if not considered during the measurement
process. In the typical example above, the difference in
bandwidth appears small on a log scale ~ut the factor of 10
in bandwidth, (200 kHz to 2 MHz) can result in a 10 dB
theoretical difference in the signal-to-noise ratio (white
noise is proportional to the square root of the bandwidth in a
system).

If adequate bypassing is not provided the current in the supply leads which is a rectified component of the load current
may be fed back into internal cirCUitry. This signal causes
low distortion at high frequencies requiring that the supplies
be bypassed at the package termina:ls with an electrolytic
capacitor of 470 ",F or more.

In comparing audio amplifiers it is necessary to measure the
magnitude of noise in the audible bandwidth by using a
"weighting" filter.l A "weighting" filter alters the frequency
response in order to compensate for the average human
ear's sensitivity to the frequency spectra. The weighting filters at the same time provide the bandwidth limiting as discussed in the previous paragraph.
In addition to noise filtering, differing meter types give different noise readings. Meter responses include:

LEAD INDUCTANCE
Power op amps are sensitive to inductance in the output
lead, particularly with heavy capacitive loading. Feedback to
the input should be taken directly from the output terminal,
minimizing common inductance with the load.
Lead inductance can also cause voltage surges on the supplies. With long leads to the power supply, energy is stored
in the lead inductance when the output is shorted. This energy can be dumped back into the supply bypass capacitors
when the short is removed. The magnitude of this transient
is reduced by increasing the size of the bypass capaCitor
near the IC. With at least a 20 ",F local bypass, these voltage surges are important only if the lead length exceeds a
couple feet (> 1 ",H lead inductance). Twisting together the
supply and ground leads minimizes the effect.

1. RMS reading,
2. average responding,
3. peak reading, and
4. quasi peak reading.
Although theoretical noise analysis is derived using true
RMS' based calculations, most actual 'measurements are
taken with ARM (Average Responding Meter) test equipment.
Reference 1: CCIR/ARM: A Practical Noise Measurement
Method; by Ray Dolby, David Robinson and Kenneth Gundry, AES Preprint No. 1353 (F-3).

1-151

•

~r-~----------------------------------------------~--~
.....
,":
~

:2
..J

Application Information

~ /' .'

(Continued)

The load current IL will be much' larger than input bias current II, ~hus V1 ,will follow the, output 1I0itage directly, i.e. in
phase. Therefore th,e voltage BlJpearing at the non-inverting
input is, effecti)lely positive feedback and the circuit may ,oscillate. If there, were only one device to worrY about then the
values of R1 an9 R2 would probably. be s,mall enough to be
ignored; \:lowever, severalc;levices r:lormally comprise a total
system. Any ,ground return of a, separate device, whose output is in phase, can feedback in,a similar manF1er and cause
instabilities. Out of phase ground' loops also are troublesome, causing unexpected gain and phase errors.
The solution to most ground loop problems is to always use
a single-point ground system, although this is sometimes
im~ractical. The third figure below is an examplE1 of a singlepOint ground system.
'

LAYOUT,GROUNDLOOPSANDSTABILITY
The LM38,76 is designed fo be:stSble when operated at a
closed-loop ~ain of 10' or greater, but as with any other hlghcurrent amplifier, the LM3876 can be made to oscillate under certain conditions. These usually involve printed circuit
board layout or output/input coupling.
When designing a layout, it is important to return the load
ground, the output compensation ground, and the low level
(feedback and input) grounds to the circuit board common
ground point through separate paths. Othetwlse, large currents flowing along ground 'conductor, will generate voltages on the conductor which can effectively act as signals
at the input, resulting in high frequency oscillation or excessive distortion. It is advisable to keep the output compensation components and the 0.1 ",F supply decoupling capacitors as close as possible to the LM3876 to reduce the effects of PCB trace resistance and inductance. For the same
reason, the ground return paths should be as short as possible.
'

a

The single-point ground concept should be applied rigorously to all components and all" cirCUits when possible. Violations of single-point grounding are 1110st common among
printed circuit board designs, since the circuit is surrounded
by large ground areas which invite the temptation to run a
device to the closest ground spot. As a final rule, make all
ground returns low resistance ll-nd low inductance by using
large Wire and wide traces;'
"
"

In general, wit~ fast, high-current circuitry, all sorts of problems can arise,'from improper grounding which again can be
avoided by returnin!! all:grounds separately ~o a common
point. ,Withput isolating the ground,signals and returning the
grounds to a common point, ground 10QPs may occur. ,
"Ground Lo,op" is the term usa,dto, describe situations OCcLJrring in ground systems where, a difference in potential
exists between, two ground pOints. Ideally a grpund is a
ground, but unfortunately, in order for thi$ to be true, wound
conductors with zero resista!,\ce are necessary. Since real
world ground leads possess finite resistance, currents running through them will cause finite voltage drOps to exist. If
two 9rQflnd r!3turn lines tie into the ,sall)e path at different
poi,nts there will be a voltage drop between them. The first
figure belo~ shows a common grQund example where the
positive input ground and the load ground are returned' to
the $upply ground point vi,a the same wire. The addition of
the finite wire resistance, R2, result\l in a voltage difference
between the two points as shown below.

Occasionally, current in the ,output leads (which function as
antennas) c;:an be coupled thrQ~gb the' air to the amplifier
input, rElsulting in high-frequency oscillation. This normally
l1appens when the sourcEl impedance is high or the input
leads are long. The problem can be eliminated by placing a
small capaCitor, Ce, (on the order of 50 pF to 500 pF)
across the LM3876 inpu~ terminals. Refer to, the External
Components Description section relating to .component
interaction with c,.
REACTIVE LOADING
It is hard for ~ost power amplifiers to drive highly capacitive
loads very effectively and normally results in oscillations or
ringing on the square wave response. If the output of the
LM3876 is connected directly to a capaCitor with no series
resistance, the Sq'uare wave response will exhibit ri'nging if
the capacitance is greater than abOut 0.2 ",F. 11 highlycapacitive loads are ,expected due'to long speaker ,cables, a
method commonly ,employed to protect amplifiers 1rom low
impedances at high frequencies is to couple to the load
through a 10n resistor in parallel with a 0.7 jJ.H inductor.
The inductor-resistor combination as shown 'in the TyjJical
Application Circuit isolates the feedback amplifier from the
load by providing high output impedance at high frequencies
thus allowing the, 1on resistor to decouple the cIIPacitive
load and redllce the O,of the se~es resonant circuit. The LR
combination also provides low output impedance at lo~ frequencies thus shorting out the 10n resistor and allowing the
amplifier to drive the sElries RC load (large capaCitive load
due to Icing ~Pe~ker cab.'~s) dir!3ctly. '

'".~,~~.

,~",p

Rt.
.....,-IIM,...,--.......~I\r--I

t IL

TUH/11832-15

1-152

Application Information (Continued)
GENERALIZED AUDIO POWER AMPLIFIER DESIGN

DESIGN A 40W/8n AUDIO AMPLIFIER

The system designer usually knows some of the following
parameters when starting an audio amplifier design:
Desired Power Output
'
Input Level
Input Impedance
Load Impedance
Maximum Supply Voltage
Bandwidth
The power output and load impedance determine the power
supply requirE!ments, however, depending upon the application ,some system designers may be limited to certai'n maximum supply voltages. If me designer 'does have a power
supply limitation, he should choose a practical load impedance which would allow the amplifier to provide the desired
output power, keeping'in mind the current limiting capabilities of the device. In any case, the output signal swing and
current are found from (where Po' is the average output
power):
'

Given:
Power Output
Load Impedance
,Input Level
Input Impedance
Bandwidth

40W
80,
1V(max)
100kn
20 Hz-20 kHz ± 0.25 dB

Equations (1) and (2) give:
40W/8n
Vopeak = 25.3V
lopeak = 3.16A
Therefore the supply required is: ± 30.3V @ 3.16A
With 15% regulation and high line the final supply voltage is
± 38.3V using equation (3). At this point it is a good idea t9
check the Power Output vs Supply Voltage to ensure that
the required output power is ,obtainable from the device
while ml!intlilining low THO + N. It is also good to chec\( the
Power Dissipation vs Supply Voltage to ensure that the device can handle the internal power dissipation. At the sal)1e
time designing in a relatively practical sized heat sink with a
low thermal resistance is also important. Refer to Typical
Performance Characteristics' graphs and the Thermal
Considerations section for more information.
'Ail ~ 18
The minimum gain from equation (4) is:

Vopeak = J2R[l5()
(1)
lopeak = J(2 Po)/RL
, (2)
To determine the maximum sllPply voltage the following parameters must be considered. Add the dropout voltage (5V
for LM3876) to the peak output swing, Vopeak, to get the
supplr. rail value (i.e. ± (Vopeak + Vod) at a current of
lopeak). The regulation of the supply determines the unloaded voltage, usually about 1'5% higher. Supply voltage will
also rise 10% during high line conditions. Therefore, the
maximum supply voltage is obtained from the following
equation:
'
,

We select a gain of 21 (Non-Inverting Amplifier); resulting in
a sensitivity of 894 mY.
Letting RIN equal 100 kn gives the required input impedance, however, this would eliminate the "volume control"
unless an additional input impedance was placed in series
with the 10 kn potentiometer'that is depicted in Figare 1:
Adding the additional 100 kn resistor wOl,lld ensure the minumum required input impedance.

Max. supplies :::: ± (Vopeak + Vod)(1 + regulation)(1.1) (3)
The input sensitivity and the output power specs determine
the minimum requirec;! gain as depicted below:

Av ~(JP~ RLl/(VIN) = VormslVinrms
(4)
Normally the gain is set between 20 and 200; for a 40W, 80,
audio amplifier this results in a sensitivity of 894 mV ,and
89 mY, respectively. Although higher gain amplifiers provide
greater output power and dynamic headr90m capabilities;
there are certain shortcomings that go along with the, so
called,"gain.", The input referred noise floor is increased
and hence the SNR is worse. With the increase il") gain,
there is also a reduction of the power bandwidth which results in a decrease in feedback thus not allowing the amplifier to respond quickly enough to nonlinearities. This decreased ability to respond to nonlinearities fncreases the
,
THO + N specification.

For low DC offsets at the output we let Rfl = 100 kn.
Solving for Ri (Non-Inverting Amplifier) gives the following:
Ri ='Rfl/(Av,-1) = 100k/(21 -1) =,5 kn; use 5.1 kn.
The blmdwidth requirement must be stated as a, pole, i.e.,
the ,3',dB frequency. Five times away from a ,pole gives
0.17 dB down, which is 'better than the required 0.25 dB.
Therefore:
fL = 20 Hz/5 = 4 Hz
fH = 20kHz x 5 = 100kHz
At this pOint, it is a good idea to ensure that the GaineBandwidth Product 'for the part
provide the designed gain out
to the upper 3 dB point of 100 kHz. This is why the minimum
GBWP of the LM3876 is important.

will

The desired input impedance is set by RIN' Very high values
can cause board layout probl,ems and DC offsets at the output. The value for the feedback resistance, Rfl, should be
chosen to be a relatively large value (10kn':'10p kn), and
the other feedback resistance, Ri" is calculated using standardop amp configuration gain equations. Most audio amplifiers are designed from the non-inverting amplifier configuration.

GBWP ~ Av

x f3 dB = 21 X 100 kHz = 2;1 MHz

GBWP = 2.0 MHz (min) for the LM3876
Solving for the low frequency rc;>lI-off capacitor, Ci, we have;
Ci

1-153

~

1/(2'11" Ri ftJ = 7.8 p.F; use 10 p.F.

II

~ r---------------------------------------------------------------------~

=
::::E

..lJ

Definition of Terms
Input Offset Voltage: The, absolute value of the voltage
which must be applied between the input terminals through
two. equal resistances to obtain zero output voltage and current.
(n!lut Bias Current: The absolute value of'the 8vefage of
the two input currents with the output voltage. an!! current' at
zero.
.

Headroom; The margin between an actual signal operating
level (usually the power rating of the amplifiE!r with particular
supply ,(oltages, arated load value,. and a rated THO + N
figure) and the level just before clipping distortlon occurs,
eXpressed in decibels.
'
, ,
Large Signal Voltage Gain: The ratio of the outP~t voltage
swing to the differential input voltage requfred to drive ihe
output from"zero to either swing limit. The output swing litnit
is 'the supply voltage less a speCified 'quasi-saturation voltage. 'A pulse of short enough duration to minimize thermal
effects IS used as a measurement signal.
Output-Cur..ent Limit: The output cuire~t with a fixed output voltage and a large input overdrive., The limiting current
drops with time once ~PIKe protEiclior,J ,circuitry is activated.

Input Offset Current: The absolute value of the difference
in the two input currents with the iJutput voltage and current
at zero.
Input Common-MOde Voltage Range (or Input Voltage
Range): The range of- voltages' on the iriput terminals for
whiCh the amplifier is operational. Note that thespecificatlo'ris· are not 'guaranteed over the full common-mode voltagll range unless specifically stated.

Output Saturation Threshol!i (qllpplng Point): The output
swing limit for a specified input drive beyond that required
for zero output. It is measured with respect to the supply to
which the output is swinging.
Output Resistance: The ratio of the change in output voltage to the change in 'output Current with"the output around
zero.

Common-Mode ReJection: The ratio of the input cominonmode'voltage range to the- peak-to-peak .change in input
offset voltage over this range. '
Power Supply ReJection:' The ratio of the c~ange in input
offset yoltage to the qhange in power supply voltages pro,
ducing it.
. ' , ,
'
"
Quiescent Supply Curre~t; The,current required from the
power supply to operate 'the amplifier With no load and the
'
output voltage and current at zero.
Slew Rate: The internally limited rate of change i~ output
voltage with a large amplitude step function applied to the
input.
'
,"

Power Dlsslpatlo':',Rating: The power ttlat can be dissipated for a specifi,ed time interval without activati,ng the protectio.n circuitry. For time intervals in excess of 100 ms, dissipa~ion eapa\lility is determined \ly heat sinking of the IC package rather than by,the IC itself.
Thermal Resistance: The peak, junction-temperature rise,
per unit of internal power dissipation (units in 'C/W), above
the case temperature as measured at the center of the
paCKage bottom.
'

Class B Ampllfle~; the ~ost C<1!llmon type of audio power
amplifier t~at, consists of two Qutput devicE!.$. e!lch .of which
conducts for 18/r of the.,input cycle. The LM3876 is a
Quasi-AB type amplifier. '.
""

The DC thermal resistance applies when one output transistor is operating continuously. The AC therrnalresistance applies with the output transistors conducting alternately at- a
high enough frequency that the peak capability of neither
transistor is exceeded,.

C,rossover Distortion: Distorti,on cau!l6d in the" output
sta~e of a class Bamplifier: It can' result from inadequate
bias current providing a dead zone where the output does
not, respond to the input as the input cycle goes through its
zero, crossing point. Also for ICs an ina:dequate frllquency
response of the· output PNP dellice ;can calise a turn-on
delay giving crossover distortion on the negative going transition through zero crossing at the higher audio frequencies.

Power Bandwidth: The power bandwi~h 'of an audio am·
plifier is the frequency range over which the amplifier voltage gain does not fall below '0.707 of the llat band vOltage
gain specified for a given load and output power.
'
Power bandwidth also can be measured by the frequencies
at which a !lpeeified level of distortion is obtained while the
amplifier delivers a power output 3 dB below the rate!! output. For example, an amplifier rated at 6,OW w,ith ,,; 0.25%
THO + N, would make its power bandwidth measured as
the difference between the upper and lower' frequencies at
which 0.25% distortion 'was obtained while the amplifier was
delivering 3 0 W . '
, ,

THO + N: Total Harmonic Distortion plus Noise refers to
the. mel!-surement technique in which the fundamElntal component is removed by a bandreject (notch) filter and all remaining energy is measured including harrnonics and noise.
Signal-to-Nolse Ratio: The ratio of a system's output signal
level. to the system's output noise ,level ob~ined in ,the absence of a signal. The output' reference sigl)al is either
measured at a: specified distortion level.
specified

or

G~in-Bandwldth Product: 'The Gain-Bandwidth Product is
a ~ay of predicting the high-fr~quen<;Yusefulness 01an oi>
amp, The Gain-Bandwidth ,Product is sometimes called the
unity-gain frequency or unity-gain cross frequency because
the open-loop gain characteristic passes through or crosses
unity gain at this frequency. Simply, we have the following
relationship: AcL1 x f1 = AcL2 X f2
Assuming that at unity-gain (AcL1 = 1 or (0 dB» fu = fi =
GBWP, then we have the following: GBWP = AcL2 X f2
This says that once fu (GBWP) is known for an amplifier,
then the open-loop gain can be found at any frequency. This
is also an excellent equation to determine the 3 dB point of
a closed-loop gain, assuming that you know the GBWP of
the device. Refer to the diagram on the follOwing page.

Continuous Average Output Power: The minimum sine
wave continuous average power output in watts (or dBW)
that can be delivered into the rated load, over the rated
bandwidth, at the rated maximum total harmonic distortion.
Music Power: A measurement of the peak output power
capability of an amplifier with either a Signal duration suffiCiently short that the amplifier power supply does not sag
during the measurement, or when high quality external power supplies are used. This measurement (an IHF standard)
assumes that with normal music program material the amplifier power supplies will sag insignificantly.
Peak Power: Most commonly referred to as the power output capability of an amplifier that can be delivered to the
load; specified by the part's maximum voltage swing.

1-154

Definition of Terms (Continued)
Blampllflcatlon: The technique of splitting the audio frequency spectrum into two sections and using individual
power amplifiers to drive a separate woofer and tweeter.
Crossover frequencies for the amplifiers usually vary between 500 Hz and 1600 Hz. "Biamping" has the advantages of allowing smaller power amps to produce a given
sound pressure level and reducing distortion effects prodused by overdrive in one part of the frequency spectrum
affecting the other part.

This refers to a weighted noise measurement for a Dolby B
type noise reduction system. A filter characteristic is used
that gives a closer correlation of the measurement with the
subjective annoyance of noise to the ear. Measurements
made with this filter cannot necessarily be related to unweighted nOise measurements by" some fixed conversion
factor since the answers obtained will depend on the spectrum of the noise source.
S.P.L.: Sound Pressure Level-usually measured with a microphone/meter combination calibrated to a pressure level
of 0.0002 ,...Bars (approximately the threshold hearing level).
S.P.L. = 20 Log 10P/0.0002 dB

e.C.I.R.!A.R.M.:

Literally: International Radio Consultative Committee
Average Responding Meter

where P is the A.M.S. sound pressure in microbars.
(1 Bar = 1 atmosphere = 14.5Ib/in2 = 194 dB S.P.L.).
DOMINATE POLE OF
(THE OPEN-LOOP RESPONSE
AVOL

- - ..: - DC GAIN

OPEN-LOOP VOLTAGE GAIN
"
A (dB)
A"I;L2 - - -: -

I

AC GAIN

-t - :

I
I
AcL1 - - -:- - - -,
(UNITY GAIN) 0 dB

Ip

LOSS = -20 dB/DECADE

-:.=..=.

I

I

I

12

1,

I

UNITY-GAIN FREQUENCY
OF THE OP AMP

lu

INPUT FREQUENCY, F(LOG SCALE)
TL/H111832-16

•
1-155

",J
'., ,,'

'l,

,:.:

.',-

LM3886 OvertureTM'~UdiopowerA~PlifierSerles"1 , "'"
High~Performance68WAudio Power Amplifier w/Mule
'!

"

:~'

,

,

~

Ge'neral De$.cr~fJti.on

':'"

.

",

,

"I

Features

The LM3886.is a fligh-Pllrformance' audio power amplifier : • 68W coni. avg. output power into 40 at Vee =' ± 28V
• 38W cont. avg. output power into 80'at Vec = ±28V
capable of delivering, 68W of con~inuous average power to a
40 load and 38W into 80 With 0.1 % (THO + N) from
• 50W cont. avg. output power Intb 8ri~t Vec'"" ±35V
20 Hz-20 kHz:' " " " ' "
. "
",,
• 135W instantaneous peak output power capability
The performance ~f the LM3886, utilizingiis Self Peak I~­
• Signal-to-Noise Ratio :?: 92 dB
stantaneous Temperature ("Ke) (SPiKe) Protection CircuitII!' An input ~ute function
ry, puts it in a class above discrete and hybrid amplifiers ·by
.'Output protection from a short to ground or to the
providing an inherently, dynamically protected Safe Operatsuppl!es via internal current limiting circuitry
ing Area (SOA). SPIKe Protection means that these p,arts
• Output over-VOltage protection against transients from
are completely safeguarded at the output against overvolt-'
inductive loads
age, undervoltage, overloads, including shorts to the sup, ., Supply under-voltage protection, not allowing internal
plies, thermal runaway, and instantaneous temperattlre
biasing to~occur when IVEEI + IVeci ,,; 12V, thus
peaks.
eliminating turn-on and turn-off transients
The LM3886 maintains an excellent Signal-to-Noise Ratio of
•
11-lead TO-220 package
greater than 92 dB with a typicallciw n!lise floor of 2.0 fLY' It
exhibits extremely low (THO + N) values of 0.03% at the
rated output into the rated load over the audio spectrum,
and provides excellent linearity with an IMO (SMPTE) typical
rating of 0.004%.

AppUcallon~,

!,.

• Component stereo
,." •. ComRact stereo
• Self-powered speakers
• Surround-sound amplifiers
• High-end stereo TVs

Typical Application

Connection Diagram
V+

Plastic Package (Note 8)
INPUT

:1~

11
10

.. ~It--JWov----t
Rs

lkn

ca

0
"-an

.:E
-

9

NC
VIN +
VIN-

MUTE

CD
CD

GND
NC
V+
V-

CO)

::I
..J

3
2

OUTPUT
NC
V+
TUH/11833-2

V-

Top View

Rfl 20 kn

Ri
1 kn
·Ci
IOI"FI
TlIH/11833-1

FIGURE 1_ Typical Audio Amplifier Application Circuit
'Optional components dependent upon specific deSign requirements. Refer to the Extemal Compo·
nents Description section for a component functional deSCription.

1-156

Order Number LM3886T
orLM3886TF
See NS Package NumberTA11B for
Staggered Lead Non-Isolated
Package or TF11 B* for
Staggered Lead Isolated P~ckage
'Preliminary: cali you local National Sales Rep.
or distributor for availability

Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devlees are required,
please contact the National Semiconductor Sales
Office/Distributors for ,~vallabllity and specifications.

Soldering Information
T Package (10 seconds)

94'1(

Supply Voltage IV+I+ lv-I (No Signal)
Supply Voltage Iv + I + lv-I (Input Signal)

Iv+1 + lv-I :s: 80V
Differential Input Voltage (Note 12)

Temperature Range
-200C:s: TA:S: +85·C
TMIN:S: TA:S: TMAX
Supply Voltage Iv+1 + lv-I
20Vt084V
Note: Operation Is guaranteed up to 84V. however. distortion may be introduced, from SPIKe Protection Circuitry if proper thermal considera-

Internally Limited

Power Dissipation (Note 3)

125W

ESD'Susceptibility (Note 4)

3000V

Junction Temperature (Note 5)

1500C

1·C/W
43·C/W

Operating Ratings (Notes 1, 2)

60V

Output Current

- 40·C to + 1500C

Thermal Resistance
8JC
8JA

84V
(V+ orV-) and

Common Mode Input Voltage

260·C

Storage Temperature

tions are not taken into account. Refer to the Thermal Considera-

tions Section for more information.
(See SPIKe™

Protection Response)

(Notes 1, 2) The f~1I0wing specifications apply for V + = + 28V, V- = - 28V,'
IMUTE = -0.5 mAwith RL =,40. unless otherwise specified. Limits apply for TA = 25·C.

Electrical Characteristics

LM3886
Symbol

Parameter

Conditions

Iv+1 + lv-I Power Supply Voltage (Note 10)

AM

"Po

Mute Attenu,ation,

Outpui Power (CQntinuo~s Average)

Typical
Limit
(Note 6) (Note 7)

Units
(Limits)

Vpin7 - V- :2: 9V

18

20
84

V (min)
V (max)

'Pin 8 Open or at ~V, Mute: On
Current out of Pin 8 > 0.5:mA,
Mute: Off

115

80

dB (min)

68
38
50

60,
30,

,0
W(min)
W(min)
W

THD + N = 0.1% (max)
f=1kHz;f=20kHz
Iv+1 = lv-I = 28V, RL = 40.
Iv+1 = lv-I = 28V,RL = 80.
Iv+1 = lv-I = 35V, RL = 80.

,

Instantaneous Pea]< ,Output Power

THD+ N

Total Harmonic Distortion Plus Noise

··SR

Slew Rate (Note 9)

'1+

Total Quiescent Power Supply Current VCM = OV, Vo = OV, 10 = OA

'Vas

Input Offset Voltage

VCM = OV, 10 = 0 mA

18

Input Bias Current

VCM = OV, 10 = 0 mA

0.2

1

p.A (max)

los

Input Offset Current

VCM = OV, 10 = 0 mA

0.01

0.2

p.A(max)

10

Output Current Limit

Iv+ I = lv-I = 20V, tON = 10 ms, Va = OV

11.5

7

A (min)

'Vod

Output Dropout Voltage (Note 11)

Iv+ -Vol, V+ = 28V, 10 = +100mA
Ivo-v-I,v- = -28V, 10 = -100mA

1.6
2.5

2.0
3.0

V (max)
V (max)

'PSRR

Power Supply Rejection Ratio

V+ = 40Vt020V, V- = -40V,

120

85

dB (min)

VCM = OV, 10 = 0 mA
V+ = 40V, V- = -40Vto -20V,

105

85

dB (min)

;,

135

,W

Peak Po

60W,RL = 40.,
30W,RL = 80.,
20I:lz:S:f:S:20kHz
Av = 26dB
VIN = 2.0Vp-p, tRISE = 2 ns

VCM = OV,lo = OmA
'DC Electrical Test; refer to Test Circuit #1.
"AC Electrical Test; refer to Test Circuit #2.

1-157

0.03
0.03

%
%

19

8

V/p.s (min)

50

85

mA(max)

1

10

mV(max)

•

Electrical Characteristics (Notes 1,2)
The following specifications apply for V
Limits apply for T A

=

t, =, + 28V, V-

=

-28V, IMUTE, '"' -0.5 mA Yl'itn RL'" 40 unless ,o.thel1ll(ise specified.

25°C. (Continued), '

,

,

c'

LM3aa6
Units

Symbol

Parameter

Conditions

'CMRR

Common Mode Rejection Ratio

= 60Vto20V, V- = ,-20Vtp -60V,
VCM = 20V'to -20V, 10 = 0 mA
Iv+1 = lv-I = 28V, RL = 2kO, AVo = 40V
Iv+1 = lv-I = 30V
fQ = 100 kHz, VIN = 50 mVrms

'AVOL

Open Loop Voltage Gain

GBWP,

Gain-Bandwidth Product

"elfll

Input Noise

IHF-A Weighting Filter
"

SNR

V+

Signal-to-Noise Ratio

09 6000 (Input Referred)
Po = 1W, A-Weighted,
Measured at 1 kHz, Rs = 250
po. = 60W" A-Weighted,

RIN.

Measured at 1 kHz, Rs '"' 250;
IMD

Intermodulation Distortion Test

'DC Electrical

Tes~

ri3fer to Test Circuil # 1,

"AC Electrical

T~

refer to Test CircuH #2,

'Typical

Unlit

(Note 6)

(Note 7)

110

85

dB (min)

115

90

dB (min)

8

2

MHz (min)

2.0

10

!LV (max)

(Umlts)

92.5

dB

110

dB

60 Hz, 7 kHz, 4:1 (SMPTE)

0.004

60 Hz, 7 kHz, 1:1 (SMPTE)

0.009

%

NoI8'l: All voltages are,measured with respect to the GND pin (pin 7), unless otherwise specified.
Note 2: Absolute MBXirrwm Ratings indicate limits beyond whi9h damage to the device may occur. Operating Ratings indicate c,onditions for which the device is
functional, but do not guarantee specific perfonnance limits. El9ctrtcatChsrscterlstiCs state DC and AC electrical specifications under particular test conditions
which guarantee specific performance limits. This assumes that the device is WHhln the Operating Ratings. Specifications are not guaranteed for parameters where
no limn is given, however, the typical value is a good indication of device performance.
Note 3: For operating at case temperatures above 25'0, the device must be derated based on a 15O"C maximum iunction temperature and a thermal resistance of
8JC ~ 1.0 'C/W ijunCtion to case). Refer to the Thermal Resistance figure in th9 Application Information sectiol! uooer Thermal Consideration..
Note 4: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 5: The ope;ating iunCtion temperature maximum is 15O"C, hoWever, the instantaneous
Note

safe Operating Area temperature is 250'C.

6:, Typicals are measured at 25'C and represent the parametric nOrm.

Note 7: LimUs are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: The LM3886T' peckage TAllB is a non~solated peckage, setiing the tab of the device and the hast sink at V- potential when the LM3886 is directly
mounted to the heat sink using only t~ermal CQmpound. If a mlc!t washer is used in addition to thermal compcund, 'tics (caSe to, sink) is increased, but the heat sink
will be isol'lled from V-.
Note 9: The feedback cOrnp&nsation network limns the bandwidth of the closed:loop response and so the slew rate will be reduced due to the high frequency roll·
off. Without feedback ccmpensatlon, the slew rate is typically larger.
Note 10: V- must have at least -9V at Us pin wRh reference to ground in order for the under.voRage proteCtion circuitry to be disabled.

Note 11: Tho output dropout voltage is tho supply voltage minus the clipping voltag,e, Ref.ir to the ClippinJl Voltage YO Supply VORage graph in the typical
Performance CharacteristiCs section.
Note 12: The Differential Input Voltage Absolute Maximum Rating is based on supply voltages of V+

1-158

=

+40V and V- ~ -40V.

r-----------------------------------------------------------------------------~

r

~

Test Circuit # 1 '(DC Electrical Test Circuit)

ien
24.9 kfl

200kfl
220 pF
OUTPUT

49.9fl

49.9fl

50kfl

49.9fl

SOURCE
TLlH/11833-3

Test Circuit # 2 "(AC Electrical Test Circuit)
Rfl 20 kfl

Ri 1 kfl'

<;

50 pF Rt2 20 kfl

v+

OUTPUT

Cc 220 pF
SOURCE

v-

TL/H/11833-4

•
1-159

Single Supply Application Circuit
V+

R"

20 kl!
*RSN

Ri
1 kl!

'Ci
10 I'F

I

2.7l!

.~ 50 pF 'R,2 20 kl!

'CSN

.. .I. ~.1 I'F

I

I

TUH/I1833-5

FIGURE 2. Typical Single. Supply AudlQ Amplifier Application Circuit
·Optional components dependent upon specific design requirements. Refer to the Ext,ernal
Components Description section for a component functional description. :.
.

Equivalent Schematic (excluding active protection circ~itry)
V+

~UTE

GND~

1.1k

150

0.45
OUTPUT

L

+IN
-IN

0.45
VTL/HI11833-8

1-160

External Components Description
Components
1.
2.

RIN
RA

3.
4.
5.

CA
C
Rs

6.

·Cc

7.
8.

Ri
·Ci

9.
10.

Rfl
°Rf2

11.
12.

RM

13.
14.

CM
*RSN

15.

*CSN

16.
17.

°L

18.
19.

Cs
51

oCt

OR

(Figures 1 and 2)

Functional Description

a

Acts as volume control by setting the voltage level allowed to the amplifier's input terminals.
Provides DC voltage biasing for the single supply operation and bias current for the positive input
terminal.
Provides bias filtering.
Provides AC coupling at the input and output of the amplifier for single supply operation.
Prevents currents from entering the amplifier's non-inverting input which may be passed through to
the load upon power-down of the system due to the low input impedance of the circuitry when the
under-voltage circuitry is off. This phenomenon occurs when the supply voltages are below 1.5V.
Reduces the gain (bandwidth of the amplifier) at high frequencies to avoid quasi-saturation
oscillations of the output transistor. The capacitor also suppresses external electromagnetic
switching noise created from fluorescent lamps.
Inverting input resistance to provide AC Gain in conjunction with Rf1.
Feedback capacitor. Ensures unity gain at DC. Also a low frequency pole (highpass roll-Off) at:
fc = 1I (21TRi Ci)
Feedback resistance to provide AC Gain in conjunction with Ri.
At higher frequencies feedback resistance works with Cf to provide lower AC Gain in conjunction
with Rfl and Ri. A high frequency pole (Iowpass rOil-off) exists at:
fc = [Rfl Rf2 (s + 11Rf2Ct)1 I [(Rfl + Rf2)(S + 1/Ct(Rfl + Rf2»1
Compensation capacitor that works with Rfl and Rf2 to reduce the AC Gain at higher frequencies.
Mute resistance set up to allow 0.5 mA to be drawn from pin 8 to turn the muting function off.
-+ RM is calculated using: RM ,;;; (IVEEI - 2.6V)/l8 where 18 ~ 0.5 mA. Refer to the Mute
Attenuation vs, Mute Current curves in the Typical Performance Characteristics section.
Mute capacitance set up to create a large time constant for turn-on and turn-off muting.
Works with CSN to stabilize the output stage by creating a pole that eliminates high frequency
oscillations.
Works with RSN to stabilize the output stage by creating a pole that eliminates high frequency
oscillations.
fe = 1/(21TRSNCSN)
Provides high impedance at high frequecies so that R may decouple a highly capacitive load
and reduce the Q of the series resonant circuit due to capacitive load. Also provides a low
impedance at low frequencies to short.out R and pass audio signals to the load.
Provides power supply filtering and bypassing.
Mute switch that mutes the music going into the amplifier when opened.

·Optional components dependent upon specific design requirements. Refer to the Application Information section for more information.

OPTIONAL EXTERNAL COMPONENT INTERACTION

Although the optional external components have specific desired functions that are designed to reduce the bandwidth and
eliminate unwanted high frequency oscillations they may caus!l certain undesirable effects when they interact. Interaction may
occur for components whose reactances are in close proximity to one another. One example would be the coupling capacitor,
Ce, and the compensation capacitor, Gj. These two components act as low impedances to certain frequencies which will couple
signals from the input to the output. Please take careful note of basic amplifier component functionality when designing in these
components.
The optional external components shown in Figure 2 and described above are applicable in both single and split voltage supply
configurations.

1-161

III

Typical Performance Characteristics
SPiKe
Protection Response

Sale Area
10

, ,,

'I'
~ \
\.\ I\,
~
TO-220

o

~

"-

\

I........

I

O'.2ms

~

•. ,J.
~::1

i"...::
~

20

40

60

.\.

Tc=2 ac
Tc = 7 Soc

A 'l
""fc"2S 0 C

\'"

~

~'

20

I I

10

~

TJ
25~oC
TO-220

-

Supply Current vs
Output Voltage

ill

60V

;;

L,..oo
~

SOV
.OV
30V

-

I"""

~

80

is

60

a

.0

I I J

5
70V

ffi

g;

~

Ol

10

COLLECTOR-EM lITER VOLTAGE (V)

I I I

r-I,.~

:r:t-

t--~..

NNIII
II II II

20

VS

I

o

0.1

= OA

10

Te = 25°C

~\ij
;;i

40

30

100

Te = 25°C

veE =

80

20

SUPPLY VOLTAGE (tV)

10

~

OC

I I

I

o

=

=7SoC

Tc

Tr

Pulse Thermal Resistance

o
60

-~~'r

F

Sma,

i!:

40

.0

a

o

=

20

~

\

I I
I I

TI"E (m.)

TJ 250°C
TO-220
lw = 100m.

o
o

60

80

Pulse Thermal Resistance

---

~

5

\

COLLECTOR-EMITTER VOLTAGE (v)

Ih

.

\

10'Y

100ml

If
II

'"

b

'w'

" "' 0"1'
.......

Te = 25°C
TJ '" 250°C

o

80

\ I\ ,
\

III
\1

SIlPply Current vs
Supply Voltage

= t20V'i, 'I

lis i

tjOV

-50 -f~ -30 -~o -10 0 10 20 30 40 50

100

PULSE WIDTH (m.)

OUTPUT VOLTAGE (V)

Supply Current vs
\
~

120

~

~
illis
~

:(

,

80

r...

TJ=~~&

10-220
tw;; lOOms

~

TC = 7SoC
40

r-

r-... l'..

500

~

~

TC = 25°C

TY'Tc" "

'\

illis

300

ffi

200

..

~
......

Te

'\

100

10

40

60

80

C

Yc,UIrs"i

C

i"')

60

ia

40

i

20

IIIIIIL J

0:1

'- ,::Vs = t20V

-50

100

Clipping Voltage vs
Supply Voltage
3,5

:E:
~

~

z

g;

0.3
0.2

~

0.1

~

~

§!

.

..,.

0'

50

100

150

CLIPPING VOLTAGE (-VEE)~

CL'P~'NG VOLTAGE (+Vcc)\'

,." =an

3.0

2.5

li1

t

............

~

2.0

.....
~

f--

1\

~~

d
1.5

I"-

o
-50

-

•.0

0.4

a

I I
Vs::; :t30V

Clipping Voltage vs
Supply Voltage

Vs = :f:30V

-3

~ t46V

CASE TEMPERATURE (DC)

0.5
~

Vs

= ov

Vo

'0 = OA

I" I
II

PULSE WIDTH (m.)

Input Bias Current vs
Case Temperature

-

I
I

o

10

COLLECTOR-EMITTER VOLTAGE (v)

r--- I'-..

~

Tc =75°,C

1/

~

=25

.
5

I
I
I

1\

:(
~
~

80

TJ = 250°C
TO-220

.00

o

o
o

CaSe Temperature

Pulse Power limit'

Pulse Power Limit
160

1.0
50

100

CASE TEMPERATURE (DC)

150

15

20

25

30

SUPPLY VOLTAGE (tV)

35

40

10

15

20

25

30

35

40

SUPPLY VOLTAGE (tV)

TLlH/11833-7

1-162

Typical Performance Characteristics
THO

+ N vs Frequency

THO

g

g

z

z

Q

Q

+

(Continued)

+ N vs Frequency

THO

+ N vs Frequency

0.1

+

~

~
~

0.010

100
FREQUENCY (Hz)

THO

lk

10k

lOOk

FREQUENCY (Hz)

+ N vs Output Power

THO

FREQUENCY (Hz)

+ N vs Output Power

THO

+ N vs Output Power

50
10

g

g

z

z

+
Q

~

+
Q

0.1

~

0.Q10

g
z

+

0.1

Q

~

0.010

0.001
10m

0.1

10

0.001
10m

100 200

0.1

OUTPUT POWER (W)

THO

+ N vs Output Power
50

10

10

+

~

10

THO

g
z

+

0.1

Q

~

0.010

0.1

10

0.001
10m

100 200

+ N vs Output Power

THO,. N vs Output Power

THO

50

50

50

10

10

10

g

g

z

z

6

0.1

~

0.010

0.001
10m

10

OUTPUT POWER (W)

100 200

10

100 200

+ N vs Output Power

g
z

6

0.1

~

0.010

0.1

0.1

OUTPUT POWER (w)

OUTPUT POWER (W)

OUTPUT POWER (W)

THO

+ N vs Output Power

10

0.001
10m

100 200

100 200

10

50

0.010

0.1

~

+ N vs Output Power

z
Q

0.1

OUTPUT POWER (w)

g
0.1

0.010

+
Q

10m

100 200

0.00201

z

~

THO

50

g
6

10

OUTPUT POWER (W)

0.001
10m

0.1

0.010

0.001

0.1

1-

10

OUTPUT POWER (W)

100 200

10m

0.1

10

100 200

OUTPUT POWER (W)

TL/H/11833-17

1-163

III

Typical Performance Characteristics
THO
"110

.g

99
"

77

~

66

i

I I
II

-,--

55 ; -

'w

~

~

44
33

-

1

55

~

44

,-

O. 1

E

i
~

+ N Distribution

.-;r--.:I-

0:025

.,-+- I-

E

51

Output Power vs
Load Resistance

+ N Distribution

I I I, I

TA = 25°C'

0.0625
0.05 - 1 - -

100

T

80

o AVG : 0.00899799

"",-'

-3.....73a-19

lp2' 204 '306
408
510
153
255
357
459

0,

ObS6~va~;on

;35V~

f--

= t2.8 vac

I--

~~DH;: f«02'O%kH;

1\ K
"-

- r-

..:......

-.

o

,0

'102 ,204
306
408
510
"51
153' 255
357
459

Obllervation Number

/ ' 'vs

20

,'I"

I II

-0.0125

\

rE 40

I

v.. ~

L\

~, 50

SIGWA , 0.00160294
~ 0'.0375 - I - - , MAX, 0.012_ - I WIN, 0.006
~ 0.025 -I- - ' N, 498
"0.0125

, III
o

0.01 0.028 0.0.46 0.064 0.082 0.1
0.019 0.037 0.055 0.073 0.091

THD + N (%)

I\. ,= 4n., VSUP = '28V. (%)

0.075

'L1"8 L

0.01 25

o

THO@ 1 kHz. Av - 21, Po - 60W.

0.0875

WAX, 0.006 _ _ _
WIN, 0.001

-3.473e-19

-0.0125

O. 1

THO@ 20'Hz. Ay = 21. Po • 50W.
I\. = 4n.: VSUP = >28V. (%)

0.0375

110

I\. = 4n

THO

I I I I
-,.......,....... ° ~~GM~,~'~~ici'o";891 J67

0.05

30
25

THD + N (%)

fA = 2.5 0 C

0.0625

'35

-0.0125 0.0125 0.0375 0.0625 0.0875
-3.4738-190.025
0.05
0.075
0.1

T

0.075

~

~,

. Vee = :l:28V

THD + H (%)

0.0875

40

~

~Hz

o

-0.0125 O.Of~5 0.0375 0.0625 0.0875
-3.473&-19 0.025
0.05
0.075
0.1

+ N Distribution

45

g
CJ

f,,= 1
TA =25°C

11

I\. = 4n

THO

"

AVG , 0.00899799 .1-1 SIGMA, 0.00160294
-I MAX, 0.01~-tt
_I MIN, 0:005
N , 498

66 ;c-

~

THO
50

I I I
I I

~ ~~

Vee = :t28V

1

I
I

~ 77 -

f,,= 26Hz
TA = 25°C

22

110
99
88

g

AVG , 0.0024759 I
r-I SIGWA: O,OOD581767
H MAX', 0.00~i=f
1-1 MIN, 0.001
N , 498

-

+ N Distribution

THO

I I
I I

'I

88

~

+ N Distribution

(Continued)'

10

20

30

I\. (n)

Number

TLlH/11833-8

Max Heatslnk Thermal Resistance ("C/W)
at the Specified Ambient Temperature ("C)
40..

50

60

70

1.3

t.o ,- - - - - - - - - - - - - - - - -

1.6

1.2

1.9

' 80
~

" 90

100

110

Tc.oC

1.3

Po· W

- - - - - - - - - - - - - - - - - - - -, 90 - - - - 50 - - - -r--r--.--.---,-r--r--.--,--,
8ll,'

1.0

(&

Maximum Power
Dissipation vs
Supply Voltage

96
1.1 -- - - - - - - _,e.,_ -- -~~,~~ - __ "C

2.4

1.9

1.7

1.4

1.1

3.0"

2.5

2.1 "

1.8

1.5

1.1'

3.8

3.2

2.8 "

2.4

2.0

1.06

6n

- - -- -- - -

~-

-',":' -

- '_ ....... ..:. - - - - - - - 114- --

35

-30-:""--I-+-+-+--1---,~~'--.·I-·-+--j
/

1.2,;

120

5.1

4.3 '

3:8

3.3

2.8

2.3

1.8

7.1

6.1

5.5

4.8

4.1

3.5

2.8

2.1

1.5

132

11.3

9.8

8.8

7.8

6.8

5.8

4.8

. 3.8

2.8

138----10---0

I

,.

15

:

I

..

10 20 30 40 50 60 70 80 90

Note: The maximum heat sink thermal resistance values. 0 SA. in the table above
~

I

2~,:: '

1.3-·--·----126----2Q-~-"

were calculated using a 0 cs

•

--I-+-+-+--1--'+-II++"'-.,t-:,f---i

102- - - -40- 108

~-

45

vcc.lv+i+lv-I

O.:!'C/W due to thermal compound.

TL/H/11833-9

OutpuJ Power· '

PowerDluipation
vs Output Power

-,vs Supply Voltage

100

:E
l5
:;:

,m

80

THO+N

.<

!'t

I

I I I

0.1 %
Vs ;: :t:35V

50

'Js .. ticv
40

~.
~

I\. = 4n
fa = 1 k~z

20

vs~ ;25J-

/,

~ I- ,~ i' Itl~vRf
20

-40

60

OUTPUT POWER (w)

80

100

;g
~

~
in
l!1'
~
~

f=

100 r-,---'-'''"I\.'''=,:-:nr;;-I\.C=5;;nr ,'''I\.''''8''n:-r

=8n
1 kHz

80 THD <~O.I%

~~' uov

i

Vs~5t-

i'l

60

.....

40

I20

1-0

'Vs -;:-'t30Vr-i
v, = U5V 'j
Vs = t20V

J::~ f.::

o
o

20

HD+H < 0.1

80

:E

I I

-40

60

OUTPUT POWER (W)

80

100

~

I

.'60\

II

4Q

"i

I
I

'/

,V.V

20

0
0

to

20

30

40

50

SUPPLY VOLTAGE (tv)
TL/H/11833-10

1-164

Typical Performance Characteristics
IMD 60 Hz, 4:1

(Continued)

IMD 60 Hz, 7 kHz, 4:1
12.000
1.8.62
-8.308
-18."
-28.62

~ 17.06000k t AP
I\.

i -38.77
3-48.92
a: -59.08
~

IMD 60 Hz, 7 kHz, 4:1
50
10

= .0,

g
!i:

Vee = H8V

0.1

~

-69.23
-79.38
-89.54
-99.7
-109.8

0.0001 L-......JL-..I-..I-.l...J....L.JU-_ _- '
2k

10k

0.010
0.001

-120.0

0.0005

6.00k UOk 6.SDk 7.20k 7.60k 8.00k
6.2Dk 6.601< 7.00k 7.•Ok 7.BDk
FREQUENCY (Hz)

20k

FREQUENCY (Hz)

IMD 60 Hz, 1:1
1

D. 1

g
Ii:

0.0 1

Vee

I-"o.oo

= :t28Y

~

.

,

-100.0

I

0.000 1
2k

FREQUENCY (Hz)

Mute Attenuation vs
Mute Current

0.1

~

0.010

'1111
D.ODI
0.0005

-120.0
6.00k UOk 6.SDk 7.20k 7.60k 8.00k
6.2Ok 6.60k 7.0Ok 7.~ 7.SDk
FREQUENCY (Hz)

20k

10k

!i:

III

-so.oo

0.00 1

10

g

1

~ -60.00

100

IMD 60 Hz, 7 kHz, 1:1

1\.' = ~n,' I

-20.00

10

50

I~_AP

t:rr8oll

0.0

.n,

V,N = 788 mVRM~
Po = 3DW, Vee = <28W, ~
NO FILTERS
=

0.1

OUTPUT POWER (w)

IMD 60 Hz, 7 kHz 1:1
20.000

~ 0.00978 ~_ 20.0000k~
I\.

10m

10m

0.1

10

OUTPUT POWER

Mute Attenuation VB
Mute Current

100

(w)

Large Signal Response
3D

20

20

.0

.0

.:!!.

60

!Jl
ijl

~

'iO
3

60
80
100

S
f=20kHz

WJIIII'

vs~ ;3:~

~~~

120
0.001

Vo
111111

111111
0.01

'"

= 1 VRIIIS = OdS
II lAy

100

= 26dB

0.1

80
VD

120
0.001

10

PIN 8 MUTE CURRENT (mA)

120

I.I.WII1.

'a?i
3

i

Ay •

0.1

E
10
Vs

o

100

10

= <30V

I\. = 8n
THD < 10"
lk

PIN 8 MUTE CURRENT (mA)

Power Supply
Rejection Ratio

120

+PSRR

I

100

-PSRR

'iO
3

80

.0

lOOk

1M

Open Loop
Frequency Response
120

Vs" nov
Tt = 250<:

Vs

= :t 30V

Te

= 2 5°C

100

'iO
3
z

80

~
~

""

10k

FREQUENCY (Hz)

Common-Mode
Rejection Ratio

IlIlIml

100

0.01

=

Vs = <30V
I\. =811
17.9VRWS = OdB
26dB

20

~

60

'"

.0

3D

80

60
PHASE

60

°
~

if:
.0

AIN

1'l1li

20

Vs '"' UOV

90
120
150

Tc '" 2SoC

20

20
10

100

lk

10k

FREQUENCY (Hz)

lOOk

1M

0
10

100

lk

10k

FREQUENCY (Hz)

lOOk

1M

100

lk

10k

lOOk

1M

180
10M

FREQUENCY (Hz)

Tl/H/I1833-11

1·165

•

I....

Application Information
ing the best heat sink possible within the cost and space
, : constraints of the system will improve the 10ng-tElflTl reliabili,ty of any, power semiconduct9r device.

GENERAL FEATURES
Mute FunctIOn:,The mutirig fun~on of the LM3886 allows
the usefto mute the music'going-into the amplifier by drawing less than ,0.5 rnA Qut, of pin' 8 of the device. This is
accomplished as shOWn in, the Typical Application Circuit
where tbe, resistor RM is t;h~n with reference to ,your negative supply voltage and is il.sed in conjuction with a switch.
The switch (when opened) cuts ,off the current flow from
thus placing the LM3886 into mute mode. Refer
pin 8 to
to the Mute Attenuation vs Mute: Current curves in the TypIcal Performance ChilractetlsUi:s section for valUes of attenuatidn
current out of' pin 8. The resistance AM is
calculated by the following equation:

',.HERMALCONSIDERATIONS .
Heat Sinking
"
The choice of a heat sink for a hjQh-power audio amplifier is
. made entirely to keep the die temperature at' a level such
that ttie thermal protection circui,try does not operate under
normal circumstances. The heat sink should be chosen to
dissipate the maximum IC poWer for 'a given supply voltage
and rated load.

V-:-,

'per

With,high;Power pulses of longer.duration than 100 mil, the

case temperature will heat up drastically without the use of

RM (IVEEI - 2.6V)1I8

a heat sink. Therefore the case temperature, as measured
at the center of the package bottom, is entirely dependent
on heat sink design and the mounting of the IC to the heat
sink., For the design of a heat sink ,for your audio amplifier
application refer to the Determining The Correct Heat
Sink section.
'

where 18 ;;:: 0.5 mAo
Under-Voltage Protection: Upon system power-up the under-voltage ,protection circuitry, allows the power supplies,
and their corresponding caps to 90me up close to their full
values before turning on the LM:3as6 such that no DC output spikes occur. Upon turn:.off, the output of the LM3886 is
brought to ground before .the power supplies suc:h that no
transients occur at pOwe~-d01Nll'

Since a ,semiconductor manufactur.er has no control over
heat sink is used In a particular amplifier deSign, we
can only, inform the system designer of the parameters and
the method, needed in the deterrnination of a heat sink. With
. this in mirn:l, the system designer must choose his supply
. VOltages, "a rated load, a deSired output power level: and
know the ambient temperature' surrounding the device.
Th8se parameters are in addition to knowing the maximum
junction temperature and the thermal resistance of the IC,
both of which are provided by National Semiconductor.
whi~h

Over-VoIt8ge Prot~IOn:rhe LM3886 contains overvoltage protection circuitry that limItS the output current to apprOximately 11Apeak while alSo'providing voltage clal')'lplng,
though not throl,lgh internal damping diodes. The clamping
effect is quite the same, hoviever, the 9utput transistors are
designed to work alternately by sinking large current spikes.

'.,',

"

SPIKe Protection: The LM3886 is protected from instantaneous peak-temperature stressing by the power transistor
array. The Safe Operating Area graph in the Typical Performance Characteristics section shows the area 6f device operation where the SPIKe Protection Circuitry is not
enabled. The wa"eform to l~.e right of the SOA graph exemplifies how the qynamic protection will cause wavefonn distortion when en.,bled:
Thermal Protection: The LM3886 has a sophisticated thermal protection scl1eme to prevent long-term thermal stress
to the device. When the temperature on the die· reaches
165°C, the; LM3886 shuts down. It starts operating again
when the die Jen'1perature drops to about 155°C, but if the
temper~ture again begiris. to rise; shutdown will occur ,again
at 16~C. Therefore the device is allowed to heat up to a
relatively high temperature if the fault condition is temporary, but a sustained fault will cause the device to cycle in a
Schmitt Trigger fashion between the thermal shutdown temperature limits of 165"C and 155°C. This greatly reduces the
by thermal cycling, which in tum
stress imPClsed on th~
improves its reliability under sU$tained fault conditions.

As a benefit to the system deSigner we have provided Maximum Power Dissipation vs Supply Voltages curves for various loads in the Typical Performance Cha..acterlstlcs
section, giving an accurate figure for'the maxinllim thermal
,. resistance required for a particular. amplifier design. This
data,was based on 6JC = 1°CIW and 6es = O.~C/W. We
also proVide a section regatding heat sink determination for
any, audio amplifier design Where' 6es may be a different
value. It should be noted that the idea behind dissipating the
m~mum power within t~e 10 is to provide th~ device with a
, low resistance to convection' heat transfer such as a heat
Slr;1k. Therefore, it is necessary for the system deSigner to be
conseIV.tive in his heat sink calculations.:As a rule, the lowElf ,the thermal resistance of the heat sink the higher the
amount of power that may be dissipated. This is of course
guided by the cost and size requirements of the system.
Convection cooling heat sinks are available commerCially,
lind ttteir manufacturers should be consultEld ,for ratings.

Ie

Since the die temperatl!(8 is directly dependent upon the' ,
heat sink, the heat sink should. ~ chosen as discussed iii ..
the. Thermal· Con.alderatlons section, such that thermal
shutdown
not be rEIiIched doring normal opef!ltion. Us.,

, Proper mounting of the IC Is required to minim~e the thermal, drop between the package, and the hellt s,ink. ,The heat
sink must also have enqlJgh metal under the papkage to
<:ondL\Ct 'heat from the ce,nter of the package;pottom to the
fins without excessive tern~ture' drop;

Win

'

,
~,

'

1-166

.---------------------------------------------~------------------I~

iii:
w

Application Information (Continued)
A thermal grease such as WaKefield type 120 or Thermalloy
Thermacote should be used when mountil)g the package to
the heat sink. Without this. compound, thermal resistance
will be no better than O.soC/W, and probably much worse.
With the compound, thermal resistance will be O.2"C/Wor
less, assuming under O.OOS inch combined flatness runout
for the package and heat sink. Proper torquing of the
mounting bolts is important and can be determined from
heat sink manufacturer's specification sheets.

sink can be calculated. This calculation is made usin!! equation (4) and is based on the fact that thermal heat flow parameters are analogous to electrical current flow Properties.
It is also known that typically the thermal resistance. 6JC
(junction to case), .of the LM3886 is 1°C/W and that using
Thermalloy Thermacote thermal compound provides a thermal resistance, 8cs (case to. heat sink), of about O.2"C/W
as explained in the Heat Sinking section.
Referring to the figure below,' it is seen that the thermal
resistance from the die (junction) to the outside air (ambient)
is a combination of three thermal resistances, two of which
are known, 6JC and 6cs. Since convection heat flow (power
dissipation) is analogous to current flow, thermal resistance
is analogous to electrical resistance, and temperature drops
are analogous to voltage drops, the power dissipation out of
the LM3886 is equal to the following:'

Should it be necessary to isolate V- from the heat sink, an
insulating washer is required. Hard washers like beryluum
oxide, anodized aluminum and mica require the use of thermal compound on both faces. Two-mil. mica washers are
most common, giving about 0.4°C/W interface resistance
with the compound.
Silicone-rubber washers are also available. A O.soC/W thermal resistance is claimed without thermal compound. Experience has shown that these rubber washers deteriorate and
must be replaced should the IC be dismounted.

PoMAX = (TJmax - TAmtJ/6JA
where 6JA = 6JC + 6cs + 6SA

Determining Maximum Power Dissipation

TJmax

Power dissipation within the integrated eircuit package is a
very important parameter requiring a thorough understanding if optimum power output'is to be obtained. An incorrect
maximum power dissipation (Po) calciJlation may result in
inadequate heat sinking, causing thermal shutdown Circuitry
to operate and limit the output power.

"JC

•

"sA

•
TUH/11833-12

But since we know PoMAX, 6Je, and 6sc for the application
and'we are looking for 6SA, we have the following:
6SA = [(TJmax - TAmtJ - PoMAX (6JC + 6esl] /POMAX(4)
Again it must be noted that tile value of 6SA is dependent
upon the system deSigner's amplifier application and its corresponding parameters as described previously. If the ambient temperature that the audio amplifier is to be working
under IS higher than the normal 2SoC, then the thermal resistance for the heat sink, given all otlier things are equal.
will need to b9 smaller.

(1)

where Vee is the total supply voltage

Equations (1) and (4) are the only equation.s need~ in the
determination of the maximum heat sink thermal resistance.
This is 6f course given that the system designer knows the
required supply voltages to drive his rated load at a particular power output level and the parameters provided by the
semiconductor manufacturer. These parameters are the
junction to case thermal resistance, 6JC, TJmax = 15O"C,
and the recommended Thermalloy Thermacote thermal
compound resistance, 6es.

PoAVE = (VOPk/RLl[Veel1T - VOpk/2]
(2)
where Vee is the total supply voltage and VOpk = Veel1T
PoAVE = Vec VOPk/1TRL - VOpk2/2RL
where Vee is the total supply voltage.

---,--'1M
"JA

Equation (1) exemplifies the maximum power dissipation of
the IC and equations (2) and (3) exemplify the average IC
power di.ssipation expressed in different forms,
PoMAX = Vci::2/21T2RL

"cs
PDMAX

The foilowing equations can be used to aaccurately calculate the maximum and average integrated circuit power dissipation for your amplifier design, given. the supply voltage,
rared load, and output power. These equations can be directly applied to the Power Dissipa~ion vs Output Power
curves in the Typical Performance Characteristics section.
'
.

.

TAmb

~

(3)

Determining the Correct Heat Sink
Once the maximum IC power dissipation is known for a given supply voltage, rated load, and the desired rated output
power the maximum thermal resistance (in °C/W) of a heat

1-167

I

Application Information (Continued)
SlGNAVTo-NOlSE RATIO

Typical signal-to-noise figures are listed for an A-weighted
fiiterwhicti is commonly uSed in the measurement of noise.
The shape of all weighting fiiters is Similar, with the peak of
the curve usually occurring in the 3 kHz-7 kHz region as
shoWn below.
.

In the measurement of the signal~fa-noise ratio, misl~terpre­
tationli of tM numbers actually measured are common. One
amplifier may soundinuch :quieter than another, but due to
improper testing techniques, they appear equal in measurements. This is often the case when comparing Integrated
circuit designs tei disCrete amplifier designs. Discrete transistor amps often "run out of gain" at high frequencies and
therefore have small bandwidths to noise as indicated below.

~

::::>

!::
....I

0..,

...

::II

80
DISCRETE
INTEGRATED CIRCUIT

20

200

20

-\/.

FREQUENCY (Hz)
TUHfl1833-14

SUPPLY BYPASSING

2k 20k 200k 211

The LM3886 has excellent power supply rejection and does
not require a regulated supply. HoweVer, to eliminate possible oscillations all op amp,s and power op amps should have
their supply leads .bypassed with low-inductal')ce capacitors
having short leads I!nd located close to the pac«age terminals. Inadequate power supply bypassing will manifest itself
by a low frequency oscillation known as "motorboating" or
by high frequency instabilities. These instabilities can be
eliminated through multiple bypassing utilizing a large tantalum Or electrolytic capacitor (10 p.F or larger) which is used
to absorb low frequenCy variations and small ceramic capaCitor (0.1 p.F) to' preve~t any high frequency feedback
thrOugb the power sUpply lines.
If adequate bypassing is not provided the current in the supply leads which. is a rectified component of the load current
may be fed back into' internal circl,litry. This signal causes
low distortion at high frequencies requiring that the supplies
be bypassed at the package terminals with an electrolytic
capacitor of 470 p.F or more.

FREQUENCY (Hz)
TUHfll833-13

Integrated circuits have additional open loop gain allowing
additional feedback loop gain. in order to lower harmonic
distortion and improve frequency response. It is this additional bandwidth that ·can lead to erroneous signal-to-noise
measurements if not considered during the measurement
process. In the typical example above, the difference in
bandwi~ appears small on a log scale but the factor of 10
in bandwidth, (2OQ kHz to 2 MHz) can resu~ in a 10 dB
theoretical difference in the signal-ta-noise ratio (white
noise is proportional to the square root of the bandwidth in a
system).·
.
.

a

In companng audio amplifjers it is neqessa/)' to measure the
magnitude of noise in the audible bandwidth by. using a
"weighting" filter.1 A "weighting~,~filter alterS the frequency
resPonse in order to compensate for the average human
ear's sensitivity to the frequency spectra. Th~ weighting fil~
ters at the same time provide the bandWidth limiting as discussed in the previOus paragraph.
In addition to noise filtering, differing meter types giVe different noise readings. Meter responSes include:
1. RMS reading,
2. average responding,
3. peak reading, and
4. quasi peak reading.
Although theoretical noise analysis is derived using true
RMS based calculations, most actual measurements are
taken with ARM (Average Responding Meter) test equipment
Reference 1: CCIRtARM: A Practical Noise Measurement
Method; by Ray Dolby, David Robinson and Kenneth Gundry, AES Preprint No. 1353 (F-3).

LEAD IN~UCTANCE

Power op amps are sensitive to inductance in the output
lead, particularly with heavy capacitive loading. Feedbac::k'to
the input should be taken directly from the output terminal,
minimizing common inductance with the load.
Lead inductance can also cause voltage surges on the sup.,
plies. With long leads to the power supply, energy is stored
in the lead inductance when the output is shorted. This energy can be dumped back into the supply bypass capacitors
when the short is removed. The magnitude of this transient
is reduced by increasing the size of the bypass capacitor
near the IC. With at least a 20 p.F local bypass, these voltage surges are important only if the lead length exceeds a
couple feet (> 1 p.H lead inductance). Twisting together the
supply and ground leads minimizes the effect.

1-188

Application Information (Continued)
LAYOUT, GROUND LOOPS AND STABILITY
The LM3886 is designed to be stable when operated at a
closed-loop gain of 10 or greater, but as with any other highcurrent amplifier, the LM3886 can be made to oscillate under certain conditions. These usually involve printed circuit
board layout or output/input coupling.
When designing a layout, it is important to return the load
ground, the output compensation ground, and the low level
(feedback and input) grounds to the circuit board common
ground point through separate paths. Otherwise, large currents flowing along a ground conductor will generate Yoltages on the conductor which can effectively act as signals
at the input, resuHing in high frequency oscillation or excessive distortion. It is advisable to keep the output compensation components and the 0.1 p.F supply decoupling capacitors as close as possible to the LM3886 to reduce the effects of PCB trace resistance and inductance. For the same
reason, the ground return paths should be as short as possible.
In general, with fast, high-current circuitry, all sorts of problems can arise from improper grounding which agliin can be
avoided by returning all grounds separately to a common
point. Without isolating the ground signals and returning the
grounds to a common point, ground loops may occur.
"Ground Loop" is the term used to describe situations 0ccurring in ground systems where a difference in potential
exists between two ground points. Ideally a ground is a
ground, but unfortunately, in order for this to be true, ground
conductors with zero resistance are necessary. Since real
world ground leads possess finite resistance, currents running through them will cause finite voltage drops to exist. If
two ground return lines tie into the same path at different
points there will be a voltage drop between them. The first
figure below shows a common ground example where the
positive input ground and the load ground are returned to
the supply grouild point via the same wire. The addition of
the finite wire resistance, R2, results in a voltage difference
between the two points as shown below.

The load current IL will be much larger than input bias current I" thus V1 will follow the output voltage directly, i.e. in
phase. Therefore the voHage appearing at the non-inverting
input is effectively positive feedback and the circuit may oscillate. If there were only one device to worry about then the
values of R1 and R2 would probably be small enough to be
ignored; however, several devices normally comprise a total
system. Any ground retum of a separate device, whose output is in phase, can feedback in a similar manner and cause
instabilities. Out of phase ground loops also are troublesome, causing unexpected gain and phase errors.
The solution to most ground loop problems is to always use
a single-point ground system, although this is sometimes
impractical. The third figure !lelow is an example of a singlepoint ground system.
The single-point ground concept should be applied rigorously to all components and all circuits when possible. Violations of single-point grounding are most common among
printed circuit board deSigns, since the circuit is surrounded
by large ground areas which invite the temptation to run a
device to the closest ground spot. As a final rule, make all
ground returns low resistance and low inductance by using
large wire and wide traces.
Occasionally, current in the output leads (which function as
antennas) can be coupled through the air to the amplifier
input, resulting in high-frequency oscillation. This normally
happens when the source impedance is high or the input
leads are long. The problem can be elimineted by placing a
small capacitor, Ce, (on the order of 50 pF to 500 pF)
across the LM3886 input terminals. Refer to the External
Components Description section relating to component
interaction with Gj.
REACTIVE LOADING
It is hard for most power amplifiers to drive highly capacitive
loads very effectively and normally results in oscillations or
ringing on the square wave response. If the output of the
LM3886 is connectad directly to a capacitor with no series
resistance, the square wave response will exhibit ringing if
the capaCitance is greater than about 0.2 p.F. If highly capacitive loads are expected due to long speaker cables, a
method commonly employed to protect amplifiers from low
impedances at high frequencies is to Couple to the load
through a 100 resistor in parallel with a 0.7 p.H inductor.
The inductor-resistor combination as shown in the Typical
Application Circuit isolates the feedback amplifier from the
load by providing high output impedance at high frequencies
thus allowing the 100 resistor to decouple the capacitive
load and reduce the Q of the series resonant circuit. The LR
combination also provides low output impedance at low frequencies thus shorting out the 100 resistor and allowing the
amplifier to drive the series RC load (large capacitive load
due to long speaker cables) directly.

'".~, ~,

GROUN~~
R2

v1 = (11 + U~

v2 = It. (R2 + v1 )

Tl/H/11833-15

1-169

Application Information

(Continued)

,

GENERALlZED'AUDIO POWER AMPLIFIER DESIGN'

DESIGN A 40W/40 AUDIO AMPLIFIER. ':,

The system designer usually knows some of the following
parameters when starting
aucf", amplifier design:
De~ired Power Output
' .. Input LeVel
. Input 'implldance
load Irnpediinpe
Bandwidth
M!lXlifiiirilSupply Voltage .

Gillen:"
'.'
Power Outpot "
.Load Impedance
Input level
Input Impedance
"Bandwidth' ..
Equations (1) and (2) give:

an

The power output and load imp~da~c~' d~t~rmine the pow~r

supply requirements, however, depending !lPorLlhe applieation~me_ systl!lm designers may b~ limited to ce~n mllXimum supply voltages. If the designer does have a PQw~r
supply Iinjitation, tie should choose a practical loadimpedanee INtiicfi iNoOld allOw the' amplifier to piovide the desired
ouiput'po~er, ~,Ileping in mind .the durrent liiTllting c~pabili~
ties of the deVice. In any case, the output signal sWing and
current are found from (where Po is 'tiie average outpUt'
poWer}:
.

.. -'

Ii',

40W
40
1V(max)
1OOkO
20 Hz-20 kHz ± 0.25 dB

.40W/4!i VoPeak = 17.9"1 .Iopeak"" .!I.5A
Therefore the supply required is: ?i21 1()V @1I.5A , .
With 15% regulation and high line the final supply voltage i~
±26.6V IJsingequation (3). At;thispoirlt it is a good ide~ to
check the Powjilr Outp~t vs SupplY Voltage to ensure. tha~
Ule rE!quired output. power. is obtainable from the device
while maintaining low. THO + N. It is also good to check the
Power 'Pissipation ys Supply Voltage to ensure that the davice can handle the internal power dissipation. At the same
time designing in a relatively practical sized heat sink with. a
low thermal resistance js also important. Refer to Typical
Perlormilnce Character~C8 graphs and the lhermal
Conllllie.r,ttonll section for more 'information.

Vop~=~(1)
lopeak = ~(2 Po)/RL
(2)
To determine the maximum sl,lpply voltage the follOwing parameters must be con~ered. Add the dropout voltage (4V
for LM3886) to Ule peak output.swiOg, Vopeak, to get the
supply rail value (i.e. ± (Vopeak + VocI) at a current of
lapeak>. Th.e regulation of the supply determines the unloaded.voltage,usually about.1/i% higher. Supply voltage will
• I,so. r~10% during h!gh'iipe conditiQfls. T,herefore".the
maximum supply )(oltage~ obtained frp,A'l, the follpwing
~.l!ation:
. ....
' •.. ,'
.

The minimllm gain from equation (4) is.:
Av ~ .~~.6.
We select a gain of 13 (Non-Inverting Amplifier); resulting iii
a sensitivity pf 973 mV•.
Letting RIN equal 1()0 kO gives the required· input impedance, ,however, this would,elimitlate the ··..volume· control"
unless an additional input impedance was placed In' series
with the 10 kO potentiometer that is depicted in Figure 1,
Adding the additionaI100'kO resistor would·ensure the minumum required input impedance.
For lo~ DC offsets at .the output we let Ru = '1 ()() krt.
Solving forRi (Non-Inverting Amplifier) gives the following:

M!IX. supplies := ± (Vopeak + Vod)(1 + regulation)(1.1) (3)
The inp,," sensitivity and the output power-specs determine
the minimum 'required gain as depicted below: .
Av ~(~Po RLl/(VIN) = VormslVinrms'
(4)
Normally the gain is set between 20 and 200; for a 40W, 80
audio ~mplifier ,.this results in a Sl!Insitivity of8~4 mV and
8~ mV, respecti1lely. Although higher gainllmplifiers provide
greater. output power and dynamic. headroom· capabilities,
there are. oertai!) shortcomings th~t. go along with the SO
c.alled ·~gain.'~ The input referred noise floor. is inCrease!!
and he,nce the ,SNR is· worse. With. the :jncrease in gain,.
there is also a 'reductioh of the power bandWidth which rasvita in a dec;rease in f~l:lack; tlJus npt allowing the ampllfier to rellpond. quickly enough. to .nonliflea~~es. Tl;li$ decrea~d ability to respond to nonlineari~ies in,creases the
THO T N specification.
TIre desired· input impedance is set by·RIN; Very high values
can cause board layout problems and DC·offsets at,the output. The value fOr, the feedback resiStance; Rtl, should be
chosen to' be a relatively 'Iar,ge value (10· kO-1 00 kO), and
the other feedback resistance, Ri, is calculated tlsing.$tandard op arTlP configuration gain equations.·.Most audio amplifiers are 'designed from the non-inverting amplifier configuration.
" ,

R.i= Rt; I(.~~ - 1) = 100k/,{t3:"'1) =, 8.a kO; use 8.2 kO
The bandwidt/l requirement must be statE!!l as a pole, i.e.,
tl:1e 3 dB frequency. ~iye times' away. from a .pole. gives
0.17 dB down, whiqh.is bEltter than the required 0.2fi dEl.
Therefore:
fL = 20 Hz/5 = 4 Hz
fH;= 20 kHz x 5 = 100 kHz
At this pOint, it is a good idea to ensure that the Gain-Bandwidth Product for ·the part wilFprovide the designed gain out
to the upper 3 dB point of 100 kHz. This is why the minimum
GBWP of the lM3886 is important. ;
GBWP ~ Av x f3 dB = 13 x 100 kHz = 1.3 MHz
GBWP = 2.0 M,H;Z (min) for the lM3886
SOlving for the low f~equenCy roll-off capacitor, Ci, we have:
Ci ~ 1/(2"11" RifU = 4.85 p.F; use 4.7 p.F.

1-170

Definition of Terms

,,:,'

Input Offset Voltage: The absolute value of the voltage
which must be applied between the input terminals through
two equal resistances to obtain zero output voltage and current.
Input Bias' Current: The absolute value of the average of
the two input currents with the output voltage and current at
zero.
Input Offset Current: The absolute value of the difference
in the two input currents with the output voltage and current
at'zero.
Input Common-Mode Voltage Range (or Input Voltage
Range): The range of voltages on the input terminals for
which the amplifier is operational. Note that the specifications are not guaranteed over the full common-mode voltage range unless specifically stated.

Headroom: The margin between an actual signal operating
level (usually the power rating of the amplifier with par.ticular
supply voltages, a rated load value, and a rated THO + N
figure) and the level just before clipping distortion occurs,
'I
expressed in decibels.
Large Signal Voltage Gain: The ratio of the output voltage
swing to the differential input voltage required to drive the
output from zero to either swing limit. The output swing limit'
is the supply voltage less a specified quasi-saturation voltage. A pulse of short enough duration to minimize thermal
effects is used ~s a me!lSurement Signal.
.
Output-Current Limit: The output current with a fixed output voltage and a large input overdrive. The limiting current
drops with time once SPIKe protection Circuitry is activated.
Output Saturation Threshold (Clipping POint): The output
swing limit for a specified input drive beyond that required
for zero output. It is measured with respect to the supply to
which the output is swinging.
Output Resistance: The ratio of the change in output voltage to the change in output current with the output around
zero.

Common-Mode ReJection: The ratio of the input commonmode voltage range to the peak-to-peak change in input
offset voltage over this range.
Power Supply ReJection: The ratio of the change in input
offset voltage to the change in power supply voltages producing it.
Quiescent Supply Current: The current required from the
power supply to operate the amplifier with no load and the
output voltage and current at zero.
Slew Rate: The internally limited rate of change in output
voltage with a large amplitude step function applied to the
input.
Class B Amplifier: The most common type of audio power
amplifier that consists of two output devices each of which
conducts for 180" of the input cycle. The LM3886 is a
Quasi-AB type amplifier.
Crossover Distortion: Distortion caused in the output
stage of a class B amplifier. It can result from inadequate
bias current providing a dead zone where the output does
not respond to the input as the input cycle goes through its
zero crossing point. Also for ICs an inadequate frequency
response of the output PNP device can cause a turn-on
delay giving crossover distortion on the negative going transition through zero crossing at the higher audio frequencies.

Power Dissipation Rating: The power that can be dissipated for a specified time interval without activating the protection circuitry. For time intervals in excess of 100 ms, dissipation capability is determined by heat sinking of the IC package rather than by the IC itself.
Thermal Resistance: The peak, junction-temperature rise,
per unit of internal power diSSipation (units in ·C/W), above
the'case temperature as measured at the center of the
package bottom.
The DC thermal resistance applies when one output transistor is operating continuously. The AC thermal resistance applies with the output transistors conducting alternately at a
high enough frequency that the peak capability of neither
transistor is exceeded.
Power Bandwidth: The power bandwidth of an audio amplifier is the frequency range over which the amplifier voltage gain does not fall below 0.707 of the flat band voltage
gain specified for a given load and output power.

THO + N: Total Harmonic Distortion plus Noise refers to
the measurement technique in which the fundamental component is removed by a bandreject (notch) filter and all remaining energy is measured including harmonics and noise.
Slgnal-tOoNolse Ratio: The ratio of a system's output signal
level to the system's output noise level obtained in the absence of a signal. The output reference signal is either
specified or measured at a specified distortion level.
Continuous Average Output Power: The minimum sine
wave continuous average power output in watts (or dBW)
that can be delivered into the rated load, over the rated
bandwidth, at the rated maximum total harmonic distortion.

Power bandwidth also can be measured by the frequencies
at which a specified level of distortion is obtained while the
amplifier delivers a power output 3 dB below the rated output. For example, an amplifier rated at 60W with s: 0.25%
THO + N, would make its power bandwidth measured as
the difference between the upper and lower frequencies at
which 0.25% distortion was obtained while the amplifier was
delivering 30W.
Gain-Bandwidth Product: The Gain-Bandwidth Product is
a way of predicting the high-frequency usefulness of an op
amp. The Gain-Bandwidth Product is sometimes called the
unity-gain frequency or unity-gain cross frequency because
the open-loop gain characteristic passes through or crosses
unity gain at this frequency. Simply, we have the following
relationship: AcLl x fl = AcL2 X f2
Assuming that at unity-gain (AcL1 = 1 or (0 dB)) fu = fi =
GBWP, then we have the following: GBWP = AcL2 X f2
This says that once fu (GBWP) is known for an amplifier,
then the open-loop gain can be found at any frequency. This
is also an excellent equation to determine the 3 dB point of
a closed-loop gain, assuming that you know the GBWP of
the device. Refer to the diagram on the follOwing page.

MusiC Power: A measurement of the peak output power
capability of an amplifier with either a signal duration sufficiently short that the amplifier power supply doas not sag
during the measurement, or when high quality external power supplies are used. This measurement (an IHF standard)
assumes that with normal music program material the amplifier power supplies will sag inSignificantly.
Peak Power: Most commonly referred to as the power output capability of an amplifier that can be delivered to the
load; specified by the part's maximum voltage swing.

1-171

Definition of Terms (Continued)
Blampllflcatlon: .The technique of splitting the audio frequency spectrum into, twG· sections and· using .individual

Tl:lis refers to a weighted noise measurement for a Dolby B
type noise. reduction system. A fiitercharacteristic is used
that gives a closer c;orrelation of .the measurement with, the
subjective annoyance of noise to the ear. Measurements
made with this fiiter cannot necessarily be related to unweighted .noise measurements by some fixed. conversion
factor since the answers obtained will depend on the spectrum of .the noise source.

power amplifiers to drive a separate woofer.and tweeter.
Crossover frequencies for the amplifiers usually vary between SOO Hz and 1600 Hz. "Biamping" has the advantages of ~lIowing smallllr power amps to produce a given
sound pressure level and reducing distortion effects pro(juslild by overd~ve in one part of· the frequency speCtrum
affecting the other part.

S.P.L;'Sound Pressure Level--l!sually meaSured with a microphone/meter combination calibrated to a pressure level
of. 0.0002 poBars (approxif1'l8tely the threshold hearing IE!IIel).
S.P.l. ;., 20 Log 10P/0.0002 dB

C:C.I.R;/~R.M.:··

literally: International Radio Consultative Committee
, Average Responding Meter

where P is the R.M.S. sound pressure in microbars.
(1 Bar = 1 atmosphere = 14.Slb/in2 = 194dBS.P.1.).

/

DOMINATE POLE OF
THE OPEN~LOOP RESPONSE

I

I

OPEN-LOOP VOLTAGE GAIN
A (dB)'
. lie
!!'
'. L2

I

.,'.

t:

- - -'- - :

AC GAIN

.
"
lleL1 - :.. - I- - - - - - - .
",

'

LOSS'i' -20dB/DECADE

I_i

I

UNITY-GAIN FREQUENCY
OF THE OP AMP .

(UNITY GAIN) 0 dB '--.,....._ _+I_ _+~~....I
. fp
f
f
fu
2
1
INPUT FREQUENCY. F(LOG SCALE)
. TLlH/11833-16

,,';'

1-172

IfINational Semiconductor

LM4860 Boomer@> Audio Power Amplifier Series
1W Audio Power Amplifier with Shutdown Mode
General Description

Key Specifications

The LM4860 is a bridge-connected audio power amplifier
capable of delivering 1W of continuous average power to an
80 load with less than 1 % (THO + N) over the audio spectrum from a 5V power supply.

• THO + N at 1W continuous average
output power into 80

Boomer audio power amplifiers were designed specifically
to provide high quality output power with a minimal amount
of external components using surface mount packaging.
Since the LM4860 does not require output coupling capacitors, bootstrap capacitors or snubber networks, it is optimally suited for low-power portable systems.

• Instantaneous peak output power
• Shutdown current

1% (max)

>2W
0.6 p.A (typ)

Features
• No output coupling capacitors, bootstrap capacitors, or
snubber circuits are necessary
• Small Outline (SO) power packaging
• Compatible with PC power supplies
• Thermal shutdown protection circuitry

The LM4860 features an externally controlled, low-power
consumption shutdown mode, as well as an internal thermal
shutdown protection mechanism. It also includes two headphone control inputs and a headphone sense output for external monitoring.
.

• Unity-gain stable
• External gain configuration capability
• Two headphone control inputs and headphone sensing
output

The unity-gain stable LM4860 can be configured by external
gain setting resistors for differential gains of 1 to 10 without
the use of external compensation components.

•
•
•
•
•

Applications
Personal computers
Portable consumer products
Cellular phones
Self-powered speakers
Toys and games

Typical Application

R,
10 kll

Connection Diagram

Small Outline Package

12

11

VDD

GAIN-OUT
GND

1

•

16 GND

HP-SENSE

15 Vo2
14. 'N

GND

13 -IN

BYPASS

12 Voo

SHUTDOWN

Audio
Input

~C, 11,
-= l"f 10kll

13

-IN

14

.,N

Yo1 10

40 kll

1\.

40 kll

811

HP-INI

11 GAIN-OUT

HP-IN2

10 Vol

GND

9 GND

Vo2 15
TUH/11988-2

5 Bypass

c"
O.I"f

•

Top View

.::r:
-= 6 HP-INI

Order Number LM4860M
See NS Package Number M16A

7 HP-IN2

3 HP-Sens.
2 Shutdown

GNO
1,4,8,9,16

TUH/II988-1

FIGURE 1. typical AudiO Amplifier Application Circuit

1-173

•

o ,-----------------------------------------------------------------------------,
Absolute Maximum Ratings

•

.CD

IE
..I

Supply Voltage

:.:"

Storage Temperature,
Input Voltage
",(',

Small Outline Package
Vapor Phase (60 sec.)
• Inffllred (15 sec;i. .

6_Q.V;';

,vct

':':':O.3VtOVOD +'O.SV

.,

"~I

"

ESD Susceptibility (Note 5)

. ,~" . 'ifsobov

'

,:' ~~hction Temperature ,

fOr":ather mBfhods of ,'Soldering . surface

Operating Ratings

"2S0V

"t

'Rfi/fSbillry"

mount devices.

Internally limited

Power Dissipation
ESD Susceptibility (Note 4) ..•.

215'C
2200C

.~,

.S~. A.N45~~'lu'f!i~· Mounti~g a'nd th8ir ~~ on Prod-

, ~~~'C,J~:t 1sr~ ,.'",

.'
I

Soldering Information ',. "~

\,

If Milltary/A.rospace specill.d devices are required,"
pl.... contact the National Semiconductor Sales
Ofllce/Dlstrlbutors for availability and specifications.

.Te.mp!lratllre Rimge
'.. TMIN s; TA'S; TMAl(
Supply Voltage '

1500C
'
I,:,

,

Electrical Characteristics (Nptes1. 2) . . . .

,

.·....:.200C s; TA '" +a5'C
S; Vee s; 5.5V

£iV

. "

'.

.

T~e following specifications apply for Vee = 5V,.RL,= ao unl!3!1S otherwise specifi~d, LimitsliPply,fo~ TA = 25'C.
~

"

,'p,

"

'.

.'.i

Param.ter',(,'

Symbol

..

,

..

,

,.

~dltlons

':.

,,"

, . !-M4860

;.

.

Typlcill
(Not. 6)

'.

"

."
Voo

Supply Voltage
""

I

Ibo

,.

,.

"

,','

..

~;'

"

' bule'scent Power Supply Current

-,",1

Vo ;., OV,lo

"

'= OA (NotIl8)

')

Shutdown Current

Vpin2 = VOO (Note 9)

Vas

Output Offset Voltage

Po

Output Power

THD+N

Total Harmonic Distortion :t. Noise

PO"'! 1 Wrms; 20 Hz S; f s;. 20'kHz

PSRR

Power Supply Rejection Ratio

vpd =

;

.~.,

,

'.

V1N=

2.7
5.5

V (min)
. V (max)

• 15.0

mA(max)

50.0

mV(max)

1.0

W(min)

0.6

Iso

.;

'.

7.0

Units
(Umlts)

LImit
(Note 7)

ov

",A

5.Q

. THD + N F,-1% (max); f "" 1. kHz

1.• 15

"

4.9V to 5.W

.. "IN'" OVto 5V, Vod = (Vol - Vo2J

'.

.

0~72'

%

65

dB
.1.0

.Vod

Output Dropout Voltage.

VII:I.

. HP-INHiQh.l~pWVoJtage

HP-SENSE = OV to 4V

.2.5

VIL

HP-IN Low Input Voltage

HP-SENSE = 4V to OV

2.5

VOH

HP-SENSE High Output Voltage

10 = 500p.A

2.a

2.5

V (,"in)

VOL

HP-SENSE Low Output Voltage

10 = -500p.A

0.2'.

o.a

V (max)

..

0.6

V (max)
V
V

Nota 1;.,AII ~~~ ~ m~ with respect to the ground pins, unless otherwise speclfled,
Note 2: Abso/u!B M8xImutn Ratings indicate limits beyond which d8!Jl8lJe to, the. d.eviCQ"may"occur. Operating Ratings indicate conditions for which the device Is
functio(1lll, bUt'do not guara'"~. specific performance limits. E1sctrli:a1 ChBtactl1rlslics state. DC and AC electrical specifications under particular test condRlons
which' guarantee speclflc perfor'niance limits. this assumes thet the ~ is within the O~rating Ratings, Speclflcalions
riot guaranteed for parameters where

,re

no..lll1'lt Is·glven. however. the typical value Is a good Indication of dilVice perfonnance.

,

~ 3. The maximum power dias;p..llan. must be derated at elevated temperatures and is d1cta~ by TJMAXo IIJA. 8Jlllthe ~ent temperlltUre TA. The maximum
allowable'power dissipation is PIilMAX .; (TJMAX - T,,)18JA or the number given in the Absolute Maximum Ratings, WhicheVer is lower. For the LM4860, TJMAX
+ 150"C,: and the typical junctioMo-ambient thermal resistance, wl1$n board mounted. Is 10C1'C/W,
,.
Nota 4: Human body model, 1\lO'pF discharged through a 1.5 kfl resistor•
"

'P,

,
,

. Nota 5: Machine Model, 200 pF:"240 pF discharged through all pins.
Nota 8: Typicals are measured al-25'C SlId represent the. ~etrk norm.,
Nota .7: :Umits are guaranteed 10 National's AOOL (Avarage Outgo/Os! Quality Level). .

'.

Nota 8: The ,qUieSQel)t ROWel' .supply current depends on the offset vol. when Ii' pnicucal load is connected to the a,m,;lfler.
Note 9:' Shutdown current has a wide distribution. For Powar Manage'menl;,e1)8itiVe desipns. contecf your local National.Semiconductor Sales Office,
,~. ';'

:;

.'

""J.

:~

'I,'"

1-174

~.,::

.

,,' !

." "

=

High Gain Application Circuit
Cf

5 pr

C;

AUdior,'
Input

4.7

",r

all

1,4,a,9,16 GND
TUH/11988-3

FIGURE 2. Stereo Amplifier with AVD = 20

Single Ended Application Circuit

20kll

AUdiOr
Input

1 ",r

'''"~..,..
-,

TUH/11988-4

FIGURE 3. Single-Ended Amplifier with Av = -1
'Cs and CB size depend on specifIC application requirements'and constraints. TyPical values of Cs and CB are 0.1 p.F.

"Pin 2, 6, or 7 should

b~, con~ected

to Voo to disable the amplifier or to GND to enable the amplifier. These pins should nol be left floating.

"'l'hese components create !I "dummy" load for pin a for stability purposes.

1-175

•

External Components Description (FlfJures 1,2)
Functional Description'

Components
1. RI

Inverting input resistance which sets the closed-loop gain in conjunction with Rt. This resistor also forms a high
pass filter with Cj atfe = 1/(271' RI Cj). '

2. Cj

Input coupling capacitor which blocks DC voltage at the amplifier's input terminals. Also creates a highpass filter
with Ri atfe = 1/ (271' Ri Cj).

3. Rt

Feedback resistance which sets.closed-loop gain in conjunction with Ri.

4. Cs

Supply bypass capacitor which provides power supply filtering. Refer to the Application Information section for
proper placement and selection of supply bypass capacitor.

5. Ce

Bypass pin capaCitor which provides haif supply filtering. Refer to Application Information section for proper
placement and selection of bypass eapacitor.

6.

Used when a differential gain of over 10 is desired. Ct in conjunction with Rt creates a low-pass filter which
bandwidth limits the amplifier and prevents high frequency oscillation bUrSts. fe = 1/ (271' Rt Ct)

Ct'

0

'Optional component dependent upon sp8cH;c design requirements. Refer to the AppItCatton Infom!a\IOn section for more in formation.

Typical Performance Characteristics
THO+ N VI Frequency

TflO -+ N VI FreqUitncy

THO + N VI Frequency
10

0.1

100
FREQUENCY (Hz)

10k

0

loOk

10

r.=0.1I'F 'i".01'~

III

b· L~+85~~

0.1
OUTPUT POWER (w)

11111

0.01
20m

1111
1"r

O. 1
f=

o

'~.. =~

THO + N vs Output Power

1

nlll

0.1

L

FREQUENCY (Hz)

10

~

O. 1

0.0 1
20m

o.

THO +.N VI Output ~ower

THO + N VI Output Power
10

1

lk

FREQUENCY (Hz)

1kHZ.,.;.= 8,n.1
' ,~~vil

0.1
OUTPUT POWER (w)

20.

Voo':+~~~
",d=2

0.0 1
20m

0.1
OUTPUT POWER (w)

TUH/11988-5

1-176

Typical Performance Characteristics
Supply Current vs Time
In Shutdown Mode

Supply Current va
Supply Voltage
a.o

4.5
4.0
~

.3
~

ia

i

3.5

~

-

3.0

lilt = 0, Vpl., = 4.5V ~

"t

=

VDO

an

~

= +5V

-5
I<

~

2.5

a

2.0
1.5
1.0

~

il:

;;:

\

0.5
0.0

"

0.5

1.0

1.5

2.0

2.5

3.0

"t=co

,

B

1/

1.25

~

1.00

21~

0.75

a
ei

~

0.50

I\.

0.25
0.00
-25

SUpply Current Distribution
vs Temperature
10

75

125

175

Power Dissipation
vs Output Power

I.1'T

II

I

~jjI!\I-:d;:"I:"I'~~#IM§;I

25

AMBIENT TEMPERATURE (OC)

SUPPLY VOLTAGE (V)

Ap
lm~~
100!,

./

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

LM4860 Noise Floor
vs Frequency

~

Power Derating Curve
1.50

= OV

Vp1N1

7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0

TINE (He)

~

(Continued)

~

~

....

~

0.5

IO},

lk

2.00
Voo
1.75
1.50

'\, = 16ll

0

20

40

60

80

100

0.0 0.250.500.751.001.251.501.75

TENPERATURE (OC)

OUTPUT POWER (w)

Output Power VI
Supply Voltage
=

2.0
+5V

= 1 kHz
THO+N < ,,,
f

B

1.25

1.5

~

~

0.75

~

§

0.50

50

40

GAIN
-45

~n

1.0

'riTr"
~
= 16n

"t

0.5

'i-rrr-

0.25

0.00

1111

0.0

45

1111
l1li1

}I

~

1.00

Open Loop
Frequency Responae

~
rr-r'

f = 1 kH;l,
THD+N < 1"

ffi

~

= an

0.0

-40 -20

10k 20k

Output Power vs
Load ReSistance

g

I'

o

FREQUENCY (Hz)

~

= +5VJ

VDD

"t=co
1/l L.LUJJJLIL.L.L
20
100

B

'\

0 510152025305540455055606570

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

LOAD RESISTANCE (n)

SUPPLY VOlTAGE (V)

'Gi'
3
z

~

30

0

PHASE

-90

20
-135
10

-180

o
fO

~

!II

if

-225
100

lk

10k lOOk

1M

ION

FREQUENCY (Hz)

III

Power Supply
Rejection Ratio
70

40

H+ttltlll--tt

30 1..-..L"-WWL-.1.J.J.llWL...L.1.
fO
100
lk

10k

fOOk

FREQUENCY (Hz)
TLlHI1198B-6

1-177

Application Information
BRIDGE CONFIGURATION EXPLANATION
As shown in F/{/1H8 1, the LM4860 has two operational amplifiers internally, 'allOWing for a few different amplifier configurations.,The first amplifier's gain is externally configurable, while the second amplifier iSi(1ternally fIXed in a unitygain, inverting configuratiOn, The closed-loop gain of the
first amplifier is set by selecting the ratki of Rt to Ri while the
second 'amplifier's g~n is fixed by the two internal 40kO
resistors. Figure 1 shows that the output of amplifier one
serves as the input to amplifier two which results in both
amplifiers prod,ucingsignals identical in magnitude, but out
of phase 180".: ConSequently, ~he, differential gain for the IC
is:
Avd ':" 2 • (Rt/Ri)
By driving the load differentially through outputs VOl and
V02. an amplifier configuration commonly referred to as
"bridged mode" is E/stabJ.ished. Bridged mode,operation is '
different from thll classical,single-ended amplifier configuration where one, side of its load is connected to ground.
A bridge amplifier design has a few distinct advantagEIS over
the single-ended configuration, as it provides diffE/rential
drive to the' load, thus doubling output swing for a specified
supply voltage.' Consequently, four times the output power
is pOssij)le as compared to"a single-ended amplifier under
the same cOnditions. Thi~ increase in attainable output power assumes that 'thE/' amplifier, is not" current limited or
clipped. In order to choose an Imlplifier's Closed-loop gain
without causing excessive Clipping which will damage high
frequency transducers used' in loudspeaker systems, please
refer to the Audio Power Amplifier De81gn section.
A bridge configuration, such as the one used in Boomer
Audio Power Amplifiers, also creates a second advantage
over single-ended amplifiers. Since the differential outputs,
VOl and V02, are biased at half-supply, no net DC voltage
exists across the load. This eliminates the need for an output coupling capllcitor which. is required in a single supply,
single-ended amplifi~r,configuration. Without an outputcoupiing capacitor in a single suPPly single-ended amplifier; the
half-supply biaS' acroSs itJe load. would result in both increased internai.,IC p()w~r'dissipation and also permanent
loudspeaker damage. An outpUt coupling capaCitor forms a
high pass filter with the load requiring that a large value
such as':"70 p.F.,be usedwith'an 80 load to preserve low
frequency response. Thisoombination does not produce a
flat response down to 20 Hz, but does offer a compromise
between printed circuit bOard size and system cost, versus
low frequency response.

heatslnking. From Equation 1, assuming a 5V power supply
,and 'an 80 load, the maximum power di~ipation point is
," 625 rWN. The maximum power diSsipation point obtained
,from Equation 1 must not be greater than the power dissipal tion thafresults from Equation 2:,
POMAX = (l'JMAX - TAl/9JA
(2)
For the LM4860 surface mount package, 8JA = 100"C/W
and TJMAX = 150"C. Depending on the ambient tE/mpera,ture, TAi of the system surrOllndings, Equation 2, can be
used to find tlie maximum internal power dissipation sup, ported by the IC packaging., If the result, of Equation 1 is
greater than that of Equation 2, then either the supply voltage must be decreased6r tlie load impedanCe increased.
For the typical application of a 5V power supply, with an 80
load, the maximum ambient temperature possible without
violating the maximum junction temperature is approximately SlrC, provided that device operatiol) is around the maximimi power dissipation point. Power'dissipation is a function
, 'of output power and thus, if typical operation is not around
the maximum power dissipation point, the ambient temperature can be increased. Refer to the Typical Pedormance
CharacterisUcs curves for power dissipation information for
lower output powers.
'
POWER SUPPLY BYPASsiNG "
As with any power amplifier, proper supply byp~ing is critical for low noise performance and hlghjlower supply rejection. The capacitor location on both' the bypass and power
supply pins should be as close to the device as possible. As
displayed in the Typical' Performance Characteristics
section, the effect of a larger half-supply bypass capacitor is
improved low frequency THO + N due to increased half-supply stal:!ility. Typical applications emplqy a 5V regulator with
1Q p.F and a 0.1 p.F bypass capac;itorS which aid in supply
stability, but do not eliminate the ri8ed for bypassing the
, supply nodes of the LM4860. The selection of bypass capacitors, especially Ca, is thus dependant upon desired low
frequency THD + N, system cost, and size constraints.

SHUTDOWN FUNCTION
In order to red~ce power consumption while not in use, the
, LM4860 ,contains a shutdown pin to externally tum off \he
amplifier's bias circuitry. The shutc;lown feature turns the
, amplifier off when a logic high, is placed on the shutdown
pin. 'Upon going into shutdown, the output is immediately
disconnected from the speaker. There is a built-in threshold
which produces a drop in quiescent current to 500 p.A typically. For a 5V power supply, this threshold occurs when
2V-3V is applied to the shutdown pin. A typical quiescent
POWER DISSIPATION
CUITent of 0.6 p.A results when the supply voltage is applied
Power diSsipation is a major concern when designing a suc'" ' , ',"10 the'shutdown pin. In many applications, a microcontroller
cessful amplifier, whether the amplifier is bridged or singleor microprocessor output is used to control the shutdown
ended. A direct consequence of the increased power deliv, cirCuitrY which provides a quick, smooth transition into shutered to the load by a bridge amplifier is an increase in inter-' , , dOVIO. Another solution is to use a single-pole, single-throw
nal power dissipation. Equation 1 states the maximum POWswitch that whlln closed, is connected to ground and ener dissipation point for a bridge amplifier operating at a giv, ,,"abies the amplifier. If the switch is open, then a soft pull-up
en supply voltage and driving a specified output load.
resistpr of 47 kO will disable the LM4860. There are no soft
pull-down resistors inside the LM4860. so a definite shutPOMAX = 4· (VOO)2/(21T2RL)
(1)'
doWn pin voltage must be appliied externally, or the internal
Since the LM4860 has two operational amplifiers in one
,:1ogic gate will be 111ft floating which could disable the amplifipackage, the maximum internal power dissipation i~ 4 timElfi
er unexpectedly.
that of a single-ended amplifier. Even with this substantial
increase in power dissipation, the LM4860 does not require

1-178

Application Information

(Continued)

HEADPHONE CONTROL INPUTS
The LM4860 possesses two headphone control inputs that
disable the amplifier and reduce 100 to less than 1 mA when
either one or both of these inputs have a logic-high voltage
placed on their pins.
Unlike the shutdown function, the headphone control function does not provide the level of current conservation that
is required for battery powered systems. Sin~e the quiescent current resulting from the headphone control function
is 1000 times more than the shutdown function, the residual
currents in the device may create a pop at the output when
coming out of the headphone control mode. The pop effect
may be eliminated by connecting the headphone senSing
output to the shutdown pin input as shown in Figure 4. This
solution will not only eliminate the output pop, but will also
utilize the full current conservation of the shutdown function
by reducing 100 to 0.6 /lA The amplifier will then be fully
shutdown. This configuration also allows the designer to
use the control inputs as either two headphone control pins
or a headphone control pin and a shutdown pin where the
lowest level of current consumption is obtained from either
function.
Fl{lUre 5 shows the Implementation of the LM4860's headphone control function using a single-supply headphone
amplifier. The voltage divider of R1 and R2 sets the voltage
at the HP-IN1 pin to be approximately 50 mV when there are
no headphones plugged into the system. This logic-low voltage at the HP-IN1 pin enables the LM4860 to amplify AC
signals. Resistor R3 limits the amount of current flowing out
of the HP-IN1 pin when the voltage at that pin goes below
ground resulting from the music coming froni the head- '
phone amplifier. The output coupling cap protects the headphones by blocking the amplifier's half-supply DC voltage.
The capacitor also protects the headphone amplifier from
the low voltage set up by resistors R1 and R2 when there
aren't any headphones plugged into the system. The tricky
point to this setup is that the AC output voltage of the headphone amplifier cannot exceed the 2.0V HP-IN1 voltage
threshold when there aren't any headphones plugged Into
the system, assuming that R1 and R2 are 100k and 1k,
respectively. The LM4860 may not be fully shutdown when
this level is exceeded momentarily, due to the discharging
time constant of the bias-pin voltage. This time constant is
established by the two 50k resistors (in parallel) with the
series bypass capaCitor value.

When a set of headphones are plugged into the system, the
contact pin of the headphone jack is disconnected from the
signal pin, interrupting the voltage divider set up by resistors
R1 and R2. Resistor R1 then pulls up the HP-IN1 pin, enabling the headphone function and dissbling the LM4860
amplifier. The headphone amplifier then drives the headphones, whose impedance is in parallel with resistor R2.
Since the typical impedance of headphones are 320, resistor R2 has negligible effect on the output drive capability.
Also shown in Figure 5 are the electrical connections for the
headphone jack and plug. A 3-wire plug consists of a Tip,
Ring, and Sleave, where the Tip and Ring are Signal carrying conductors and the Sleave is the common ground return. One control pin contact for each headphone jack is
sufficient to indicate to control inputs that the user has inserted a plug into a jack and that another mode of operation
is desired.
For a system implementation where, the headphone amplifier is designed using a split supply, the output coupling cap,
and resistor R2 of FIf1IJf'B 5, can be eliminated. The functionality described earlier remains the same, however.
In addition, the HP-S'ENSE pin, although it may be connected to the SHUTDOWN pin as shown in Ftgure 4, may still be
used as a control flag. It is capable of driving the input to
another logic gate or approximately 2 mA without serious
loading.

ee

LM4860

I

6

HP-INl _

7

~'" I ~

3

HP-SEN~

2

SHUTDOWN

TL/HI11988-7

FIGURE 4. HP-SENSE Pin to
SHUTDOWN Pin Connection
I

•
1-179

C)

!:::E

....

r---------------------------------------------------------------------------------,
Application Information (Continued)
Voo
Rl
100kn

= 5V

LM4860'
Ul

100kn
, , R3

HP-INl
7

HP-IN2

3
2

.~ ~.!~20-·,-F--~-R2--~----------,
,

"

::
~

.. (

Cc

220 pF

n.

SHUTDOWN,

ro.::i;-~-i~"\~OO

" - - - ,_ _ _ _.L..:

,

~

~:1W
• Shutdown current
' ' ,,'
0.6 p.A (typ) ,

Features
• No outPut coupling capaCitors, bootstrap capacitors, or
snubber circuits are necesSary'
'
• SRillil Outline'(Sc) pack8ging,
• Compatible with PC poWer supplies
• Thermal shutdown protection circuitry
• Unlty-gain stable
• External Gain Configuration Capability

Applications
•
•
•
•
•

Personal computers
Portable consulTlE1r products
Cellular phonl'S
Self-powered speakers
Toys and games

Typical Application

" Connection. DI.gr,m
VDD

ts·

o"pr~

.;

, e

20kll

, 'VOD .

..

'Small Outline Package

-IN
Vol

3

5

SH,UTDOWilO'
,
8
V,O'2,
BYPASS 2
7
GND
,

+1"
40k.o.

+IN

3

, -IN

4,

' 6 VDD
'

5

Vol

TUH/1.1988-2 ,

40kn

''ropVlew
50kll

Order Number 1.M4881M
, See NS Package
,'Number Mo8A

,Vo2 8'

2 By.....

c"
D.,;.r~

" '..

Voo/2,

SDkO

1 Shutdown

GND

TL/H/11988-1

FIGURE 1. Typical AudiO Amplifier Application Circuit

1-182

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National SemIconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
6.0V
/,
Storage Temperature
- 65'C to + 150"C
Input Voltage
-0.3V to Voo + 0.3V
Power Dissipation (Note 3)
Internally limited
ESD Susceptibility (Note 4)
3000V
ESD Susceptibility (Note 5)
250V
150"C
Junction Temperature

Soldering Information
Small Outline Package
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220"C
See AN-450 "Surface Mounting and their Effects on Product Reliability" for other methods of soldering surface
mount devices.

Operating Ratings
Temperature Range
TMIN ~ TA ~ TMAX
Supply Voltage

-20"C ~ TA ~ +85"C
2.7V ~ Voo ~ 5.5V

Electrical Characteristics (Notes 1, 2)
= 5V, Rl = 80 unless otherwise specified. Limits apply for TA =

The following specifications apply for Voo

25'C.

LM4861

Symbol

Parameter

Voo

Supply Voltage

100

Quiescent Power Supply Current

Iso

Shutdown Current

Vos

Output Offset Voltage

Po

Output Power

THD+N

Total Harmonic Distortion + Noise

PSRR

Power Supply Rejection Ratio

Conditions

= OV, 10 = OA (Note 8)
Vp in1 = Voo (Note 9) .
VIN = OV
THD+N = 1% (max);f = 1 kHz
Po = 500 mWrrns; 20 Hz ~ f ~ 20 kHz
Voo = 4.9V to 5.1V
VIN

Typical
(Note 6)

6.5

Umlt
(Note 7)
2.7
5.5

V (min)
V (max)

10.0

mA(max)

50.0

mV(max)

0.50

W(min)

IJA

0.6
5.0

Units
(Umlts)

0,:45

%

65

dB

Note 1: All voltages are measured wfth respect to the ground pin, unless otherwise specified.
Note 2: Absolute MBXimum Ratings indicate IlmRs beyond which damage to the device may occur. Opsrslfng Ratings indicate conditions for which the davice is
functional, but do not guarantee specific performance limits. E/sctrics/ Chsracterls/Jcs stete DC and AC electrical specifications under psrticular test conditions
which guarantee specific performance limits. This assumes that the device Is within the Operating Ratings. Specifications are not guaranteed for parameters where
no limit Is given, however, the typical value Is a good indication of device performance.
Note 3: The maximum power dissipation must be derated at elevated temperatures and ~ dictated by TJMAXo 9JA, and the ambient temperature TA. The maximum
allowable power dissipetion is POMAX ~ (TJMAX - TAll9JA or the number given In the Absolute Maximum Ratings, whichever is lower. For the LM4861 , TJMAX ~
l5O"C, and the typical iuncUon-to-ambient thermal resistence, when board mounted, is 17rrC/W.
Note 4: Human body model, 100 pF discharged \I1rough a 1.5 .kn"resistor.
Note 5: Machine Model, 220 pF-240 pF discharged through all pin•.
Note 6: Typical. ara measured at 25'C and reprasentthe parametric norm.
Note 7: UmRs ara guaranteed to Nationai's AOQL (Average Outgoing Quality LeveO.
Note 8: The quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier.
Note 9: Shutdown current has a wide distributicn. For power management sensitive designs, cOntact your local National Semiconductor Sales Office.

i....

~ .-------------------------------------------------------------------------------------~

!

~

High Gain Application Circuit
Cf

5pF

100kn

C,

'AUdiO~
Input

1\
an

4.7 J.'F

--

TI.IH/11~-3

FIGURE 2. Audio Amplifier with AVO = 20

Single Ended Application Circuit

20kn

c,
AUdiOr
Input

1 J.'F

Tl/H/ll~-4

FIGURE 3. Single-Ended Amplifier with Av

=

-1

'Cs and Cs size depend on specific application requirements and oonstraints. Typical vaiues of Cs and CB are 0.1 ,.F.
"Pin 1 should be oonnec1ed to Veo to disable the amplifier or to GND to enable the amplifier. This pin Should no1 be left floating.
'''These oomponants create a "dummy" load for pin 8 for stabiroty purpcses.

1-184

r-----------------------------------------------------------------------------, r

!:

External Components Description (Figures 1,2)
Components

i

Functional Description

1. Ri

Inverting input resistance which sets the closed-loop gain in conjunction with RI. This resistor also forms a high
pass filter with Ct atle = 1/(2"11" Ri Ci).

2. Ci

Input coupling capacitor which blocks DC voltage at the amplifier's input terminals. Also creates a highpass filter
with Ri atle = 1/(2"11" Ri C;}.

3. RI

Feedback resistance which sets closed-loop gain in conjuncticn with Ri.

4. Cs

Supply bypass capaCitor which provides power supply filtering. Refer to the Application Information section for
proper placement and selection of supply bypass capacitor.

5. Ce

Bypass pin capacitor which provides half supply filtering. Refer to the Application Information section for
proper placement and selection of bypass capacitor.

6.

Cj.

Used when a differential gain of over 10 is desired. Cj in conjunction with RI creates a low-pass filter which
bandwidth limits the amplifier and prevents high frequency oscillation bursts. fe = 1/(2"11" RI Cj)

'Optional component dependent upon specific design requirements. Refer

to the Application Information section for more Information.

Typical Performance Characteristics
THD + N va Frequency

THD + N va Frequency

THD + N va Frequency

10

0.1

0.01

10
FREQUENCY (Hz)

FREQUENCY (Hz)

10

lk

10k

lOOk

FREQUENCY (Hz)

THD + N va Output Power

THD+ N va Output Power
10

100

THD + N va Output Power

~
10~.

p

1.0

=O.lpf

111111

,".0pF

1

11111

g

G,=O.I"F

r.=O.I"F

z

+

o. 1

"i!'

0.1
= 811.

I

0.0 1
20m

f

Voo":,;;V2

0.1
OUTPUT POWER (w)

= 1 kHz, I\. = an,
VDD == +5V,
"'d= 2

0.01
20m

0.1
OUTPUT POWER (W)

O".~
1=20kHz. f\ =811.
VDD +SV.

=

0.01

LL.l.l.WJJLi.-L_ _..:"':::,d_=2;.a

20m

0.1
OUTPUT POWER (W)

TL/H/II986-5

1-185

-

Typical Performance Characteristics

(Continued)

(""

. SupplyCurreritva Time
In Shutdown MC?CIe

.

.3
~

z

..0
3.5

f - ~~ = 0, VplNl = 4'5V~
. I\. = 80

r--

Yoo

3.0

= +5V

1-+,"+-+-117"'+-+-+-1
1-+-+-+=>"'11-+-+-+-1
/F-+-+-+-+"-l
"51-+-~-+-I1-+-+-+-I
4.0 1--+-.'1/-1--+-+--+-+-1
3.5 1-+.1+-+-11-+-+-+-1
3,0 1--+-+-+-11-+-+--+-1
2,5 1--+-+-+-11-+-+-+-1

'.

rl

.2.0

it 1.5
iil
1,0

1\

0.5
0.0

"

0,5

1.0

1.5 .. 2.0

~,5

10

0." I--r+-+-I"'\rl--I-+--+

~

i

I-+-+-+-II-+\.~-+--+
\
. 0.0 L.--'-..l....-L-L--\_L.-lL..-l
0.2

-25

100!,

f= 1 kHz

,.

a

-40 -20,

Output Power vs
2.00 rT-rT"l-r-r-rT-r.:-~=
VDD = +5V
1.50

i

1.25

g

0.75

1.00

2.0
f~ fkHz
JHD+H16JA

AVd = 2 ~ (Rf/Rj)

By driving the load differentially through outputs VOt and
V02, an amplifier configuration commonly referred to as
"bridged mode" is established. Bridged mode operation is
different from the classical single-ended amplifier configura,tion where one side of its lOad is connected to ground.
A bridge amplifier design has a few distinct advantages over
the single-ended configuration, as it provides differential
driVe to the' load, thus doubling output swing for a specified
supply voltage. Consequently, four times the output power
is possible as compared to a Single-ended amplifier under
the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or
clipped. In order to choose an amplifier's closed-loop gain
without causing excessive Clipping which will damage high
frequency transducers used in loudspeaker systems, please
refer to the Audio Power Amplifier Design section.
A bridge configuration, such as the one used in Boomer
Audio Power Amplifiers, also creates a second advantage
over single-ended amplifiers. Since the differential outputs,
VOt anp V02, are biased at half-supply, no net DC voltage
exists across the load. This eliminates the need for an output coupling capaci~or which is required in a singlE! supply,
single-ended IImplifier configuration. Without an output coupling capaCitor in a single supply, single-ended ampljfier, the
half-suppl}i'bias across the load would result in both increas8d internal IC power 'dissipation and also permanent
loudspeaker damage. An output coupling capacitor forms a
high pass 'filter with the load requiring that a large value
sl!~h as 470 p.F be used wi~h an 80 load to preserve low
(requency response. This combinatipn does not produce a
flat response down to 20 Hz, but does offer a compromise
between printed circuit board size and system cost, versus
low frequency response.
'

PQWER SUPPI,.Y BYPASSING
As with any power amplifier, proper supply bypassing is critical for low ,noise performance and high power supply rejection. The capacitor location on ,both the bypass and power
supply pins should be as close to the device as possible. As
displayed in the Typical Performance Characteristics
section, the effect of a larger half supply bypass capacitor is
improved low fn;!quency THD + N due to increased halfsupply stability. Typical applications employ a 5V regulator
with 10 p.F and a 0.1. p.F bypass Capacitors which aid in
supply stability, but dc)'not eliminafethe need'for bypassing
the supply nodes of the LM4861. The selection of bypass
capacitOrs, especially CB, 'is thus dependant upon desired
low ltequency THD + N, system c~, and size conStraints.

SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the
LM4861 contains a shutdown pin to externally, turn off the
amplifier's bias circuitry. The shl!tdown feature turns the
amplifier off when a logic high is placed on the Shutdown
pin. Upon going Into ~/1utdoWn, the output is immediately
disconnected from the speaker. There is a built-in threshold
wh,ich produces a drop in quiescent current to 500 p.A typically. For a 5V power supply, this threshold occurs when 2V3V is applied to the 'shutdown pin. A typical quiescent currerit of 0:6 p.A results when the supply voltage is applied
the shutdown pin: 'In many' applications, a microcontroller or
microprocessor output Is used'to control the ,shutdown ci~­
cuitry which provides a, quick, smooth transition into shutdown. Another solution· is to"use a single-pole, single-throw
switch that wheN 'closed, is connected to ground arid enables the amplifier. If the switch is open, then a soft pull-up
resistor of 47 kO will disable ~he LM4861. There are no soft
pull~down resistors ins~e the LM4861 , so a definite shutdown pin voltage must be applied externally, or the internal
logic gate will be left floating which could disable the iunplifi'
erunexpectedly.

to

POWER ~ISSIPATION
Power dissipation is a major concern when designing a sue,cessful amplifier, whether the amplifier is bridged or singleenlled. A. direct consequence of the increased power delivered to the load by a \lridge amplifier is ,an increase in, internal power diSSipation. Equation 1 sllltes the maximum power dissipation point for a bridge amplifier operating at a given supply voltage and driving a specified output load.
POMAX = 4·(VOO)2/(21T2RLl

(2)

For the LM4861 surface mount package, 6JA = 17O"C/W
and TJMAX = '150"C., Depending on the ambient temperature, TA, of the system surroundings, Equation 2 can be
used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation 1 is
greater than that of Equation 2, then either the supply voltage must be decreased or the load impedance increased.
For tile typical application of a 5V power supply, with an 80
load, the maximum ambient temperature possible, without
violating the maximum junction temperature is approximately 44°0 provided that device operation is around the maximum power dissipation point. Power dissipation is a function
of output power and thus,if typical operation is not around
the maximum power dissipation pOint, the ambient temperature can be increased. Refer to the Typical Performance
Characteristics curves for power dissipation information for
lower output powers.

(1)

Since the LM4861 has two operational amplifiers in one
package, the maximum internal power dissipation is 4 times
that of a single-ended amplifier. Even with this substantial

1-187

•

Application Information (Continued)
HIGHER GAINAtiDIOAMPLIFIEFf

AUDIO POWERAMI'tIFIER DESIGN

The LM48~i i~' unity-gain s~le. and 'requi~s no exJernal
cOmPoQe~ beside~. gain-setting resi~rs, an inp~t C()upiing capacitor, and proper supply bypassing, in the tYPiiial
application. However, if a, cl~-Ioop differential gain of
greater than 10 is required, tl)en a fe~back capacitor is
needed, as shown in Figure 2, to bandWidth limit the amplifier. This feedback capacitor creates a IOW'pass filter that
eliminates unwanted high frequency oScillations. Care
should be taitehwhen calculating the '.,..3 dB frequency,in
that an incorrect combination of RI and C,will cause rolloff
before 20 kHz. A typical combination of feedback resistor
and capacitor that will not produce' audio band high frequency folloff is Rf = 100 kG and'C, = 5 pF. TheSEl"components
result in a -3 dB point of approximately 320 kHz. Once the
differential gain of' the amplifier has been calculated, a
choice Of Rf will result, and C, can then be calculated from
the formula stated in the External Components Description section."
'.

Design. a 5OO!"W I
Given:
Power Output
Load Impedance

lripu~level

Input ImpedanCe
Bandwidth

'," I '

ao AudIO Am",lfler
'500 ITIWrrns
,
80
1 Vrms(max)
.
20kO
20 Hz-20 kHz ±b.25 dB

A designer must first determin~. the needetl supply rail.to
obtain the' specified output power. CalcUlating the 'required
supply rail involves knowing two parameters, Vapeak and
also the dropout voltage. The latter is typically 0.7V. Vopeak
can be determined from equation 3.
VopEIak = ~(2RLPO) ,
(3)
·For 500 mW of output power into an 80 load, the required
VOpeak is·2.8aV. A minumum supply rail of 3.53V results
from adding Vapeak and Vod- But 3.53V is not a standard
voltage that exists in many applications and for this reason,
a supply rail of 5V is designated. ElCtra supply voltage creates dynamic headroom that allows the LM4861 to reproduce peakS in excess of 500 mW without clipping the signal.
At this time, the deSigner must make sure that, .the P9wer
supply chqice. alol)g with the output impedance does ,not
violate the conditions explained in thE! Po_r. DI88I. .tlon
section.
Once the power dissipation equations have been. addressed, the required differential gain can be determined
from Equation 4.

VOiCE-BAND
AUDIO
AM~LIFIER
.
.
,
MaRY applications, such as telephony, only require ,a voiceband frequency ~ponse. ·Such an applica~on usually requires a flat frequency response from 300 Hz to 3.5 kHz. By
adjusting the component values. of Figure 2, this common
application requirement can be implemented. The combination cif Ri and;C; form a high()aSs filter while Rt and C, form a
Iowpass filter. Using the typical voice-band .frequency range,
with a passband differential·gain of approximately 100, the
following values of Ri' Cj, Rf, and C, follow from tHe'equations stated in the ElCternal Components Description section.
'

Avd ~ 2* ~(PoRLl/(VIN) = VorrnslVinnns
Rf/Ri = Avd/2
From equation 4, the minimum AviJ is: Avd = 2

. RI ';"10, kO, Rf = 510k ,0, .. 0.22./IoF; and C, = 15 pF
FlVetimesiaway from a ':3 dB ppint is 0.17 dB down from
theflatband r.esponSs. Withthis selection of components,
tile resulting -3 dB points, fL and fH' are 72 Hzand 20 kHz,
respectively, r~ulting in a flatblind frequency resPonse of
ilEIt!erthan ± 0.25 dB with a rollpff of 6, dB/octave outside
of the passband. If a steeper rolloff is required, other common bandpass filtering techniques can be used to achieve
/ligher order filters.

(4)
.' (5)

Since th~ c!eSiredinput impedance was 20kO, 'and ~h.a
Avd.of 2, a ratio of 1:1. of Rf to Ri resul~ in I\n al.locationof
RI = Rf = 20 kO. Si.nce the Avd was less than '1 0, a feedback capacitor is not needed. The final design step is' to
address the bandwidth requirements which must be stated
a pair of -3 dB frequency p,oints. Five times away from a
- 3 db pOint Is 0.17 dS down from passband response
wlJich is better than the required ±0.25dB specified. This
fact results in low and high frequency pole. of 4 Hz and
100 kHz respectively. As stated in the External Compo'nents section, Ri in eonjl.uiction with C; create a highpaSs
. , '
·filter. " .

as

SINGLE-ENDED AUDIO AMPLIFIER
Although the,typicai application for the LM4,861 is a bridged
monoaural amp, it can' also be used to. ,drive a load singleendedly'in applicatlQns, such as PC cards, which require
that ·one. side of the ,load is. tied to ground. F/{/Ufe 3 shows a
cOmmon single-en(led applicatlo~" where VOl is' used to
drive ,the sPElBker. This output is cpupled through a 470 /IoF
capaCitor, which blocks the h8lf~supply DC bias ~hat el0.5W
• Instantaneous peak output power
0.7 p.A (typ)
• Shutdown Current

Features
• No output coupling capacitors, bootstrap capacitors or
snubber circuits are necessary
• Small Outline or DIP packaging
• Unity-gain stable
• External gain configuration capability
• Pin compatible with LM4861

Applications
• Portable Computers
• Cellular Phones
• Toys and Games

Typical Application

Connection Diagram
Small Outline and DIP Package

Cs

SHUTDOWN 1 •

0.1 ",F:::J::
20kn

BYPASS 2
IN' 3
4 -IN

Vol 5

-IN 4

3 'IN
10kn

TL/H/12342-2

50kn

Top View
Order ".umber LM4862M, LM4862N
See NS Package Number M08A or
N08E

2 Bypass

Ca

O.l"'F~

50kn
1 Shutdown

Bia.s

TUH/12342-1

FIGURE 1. Typical Audio Amplifier Application Circuit

1-189

•

•·ffI

o~------------------------------------------------------------------------,

~.

!i~ t~i~~ n a I

S em i co n'du c tor

\"

LM4880 Boomer@ Audio Power Amplifier Series .
. Dual 2.00'mW ,Audio Power Amplifier witttShutdown' Mode'
,

General Description',

."

Key Specifications

The LM4880 is a dual audio power amplifier capable of deIivering200 mW of continuous average poweF'to an 80 load
, with less than 0.1 % (THO + .III) using a 5V power supply.
Boomer audio power amplifiers were designed specifically
. to provide high quality output power with a minimal amount
of external components using surface mount ·padkaging.
Since the LM4880 d~Iil'not rE!Quire bootstrap ~pacito(S or
; snubber networks, it is optimally suited for low-pOWEll; Ilorta..
ble systems.
The LM4880 features an externally contJ;oll~d, low-power
consumption shutdown mode, as well as an internal thermal
shutdown protection mechanism. .
.
.
'.'. .
The unity-gain stable LM4880 can
gain-setting resistors.

b~ configur~d by external

~

',"l

I

I.' •

'.

TtiO +, N at~200

IT!W continuOUIi\ averllge
.rO.1% (max)
output power iot080,
• THO +N at 75 mW continuous 'average'
output power into 320
.. 0.1% (max)
0.7 p.A (typ)
.Shutdpwn Current
~'.

j'

Features.
• No bootstrap capacitors, or Snubber circuits are necessary
• Small Outline (SO) packaging
• Unity-gain stable
• External gain configurati~,il capability

Applications
• Headphone Amplifier
• Personal Computers
• CD-ROM Players

Typical Application

Connection Diagram
Cs

.~

O.IPF~

20kA
~

Audio

Ir~t

20kn

2 IN A

. Small Outline Package

O~TAO·
'. "a

-Ll~F

VDD
7 0UtB ,

,INA.

50kn

BYPASS 3
GND 4

6 IN B . •.
.

5 SHUTDOWN.
TLlH/12343-2

Top View

<:s

O.IPF~

.'

Audio
Input

50kn
Co
470 pF

Ri

tt

20kn

~
20 kn

'~,:an

6 IN 8

GND 4

TLlH/12343-1

FIGURE 1. Typical Audio Amplilier Applicatlon'CirCuit

1-.190

Order Number LM4880M
See NS' Package
. Number M08A

t!lNational Semiconductor

Audio Control'
Selection Guide

Part
Number

Description

# of
Supply
Audio
Range
Channels

THO

SNR
(Typ)

(Typ)

SeparaUon
(Typ)

Package
(Pin
Count)

CommunlcaUon
Interface

75 dB'

Dip(20)

DC Control

AddlUonal
Comments

LM1036

Dual DC Operated
TonelVolumel
Balance Circuit

2

8Vto
18V

80 dB

' 0.05%

LM1971

1·Channel
Digitally·Controlied
Audio Allenuatcr

1

4.5Vto
12V

64 dB

0.001%

NA

SO(8)

Serial
MICROWIRE

"Clickless"
Transitions

LM1972N

2·Channel
Digitally-Controlled
Audio Attenuatcr

2

4.5Vto

120 dB

0.0008%

HOdB

Dip(20),
SO(2O)

Serial
MICROWIRE

Daisy Chain
Capability,
"Clickless"
Transitions

3·Channel
Digitally·Controlied
Audio Allenuator

3

120dB

0.0008%

HOdB

Dip(20),
SO(20)

Serial
MICROWIRE

Daisy Chain
Capability,
"Clickless"
Transitions

Digitally·Controiled
Stereo Tonel
Volume/Balance
Control

4

95 dB

0.008%

80 dB

Dip(28),
PLCC(28)

LMC1983

Digitally·Controlied
Stereo Tonel
Volume/Balance
Control

6

,6Vto
12V

LMC1992

Digitally·Controlied
Stereo Tonel
Volume/Balance
Control

8

LMC835

Digitally·Controlied
7·Band Stereo
Graphic Equalizer

2

LM1973N

LMC1982

12V

4.5Vto
12V

6Vto
12V

Serial
'"

Intermetal
Bus (1M)

95 dB

0.008%

so dB

Dip(28),
PLCC(28)

6Vto
12V

105 dB

0.03%

95 dB

Dip(28),
PLCC(28)

Seiiill
"MICROWIRE

5Vto
16V

114dB

Q.0015%

NA

Dip(28), ,
PLCC(28)

SElrial

1·191

Serial
Intermetal
Bus (1M)

Few Extemal
Components
Required

Two Selectable
Stereo Inputs
w/Stereo
Enhance and
Loudness Control
Three Selectable
Stereo Inputs
w/Loudness
Control
Four Selectable
Stereo Inputs
wi Fader Control
±6dBor ±12dB
Gain Ranges
w/25 Steps Each

a~ tflNational Semiconductor
LM 1036 Dual DC Operatld
Tone/Volume/Balance Circuit
General Description

Features

The LM1036 is a DC controlled tone (bass/treble), volume
and balance circuit for stereo applications in car radio, TV
and,audio systems. An a!lditional control Input allows loud.'
ness comp~nsatioh to be simply effected.
Four control inputs provide control of the bass, trebie, balance and volume functions through application of DC voltages from a remote control system or, altematively, from'
four potentiometers which may be biased from a zener regulated supply provicied on the circuit. .

•
•
•
•
•

Wide supply voltage range, 9V to 16V
Large volume control range, 75 dB typical
Tone control, ±lS"dB typical
Channel ~paration, 75 dB typical
Low distortion,O.06% typical for' an input level of 0.3
Vrms
• High signal to noise, 80 dB typical for an input level of
0.3 Vrms
• Fe~ external components required

Each tone response is defined by a single capacitor chosen
to give the desired characteristic.

Block and Connection Diagram
D~I.ln.Llne .Packagt!

INTERNAL SUPPLY DECOUPlE~~=::;-'7--'" 20 GND
INPUT 1
18 TRE8LE CAPACITOR 2

TREBLE CAPACITOR 1

17 ZENER VOLTAGE

TREBLE CONTROL INPUT
AC BYPASS 1

AC BYPASS 2

BASS CAPACITOR 1

BASS CAPACITOR 2

LO,UDNESS COMPENSATION
CONTROL INPUT

lASS CONTROL INPUT

OUTPUT 1
12 VOLUME CONTROL INPUT

BALANCE CONTROL INPUT
GND
TOP VIEW

Order Number LM1036N
See NS Package Number N20A

1·192

TUH/5142-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
16V
Control Pin Voltage (Pins 4,7,9,12,14)

Operating Temperature Range
Storage Temperature Range

O"Cto +70·C
-65·C to + 150·C

Power Dissipation

lW

Lead Temp. (Soldering, 10 seconds)

260"C

Vee

Electrical Characteristics Vee = 12V, TA= 25·C (unless otherwise stated)
Parameter
Supply Voltage Range

Conditions

Min

Pin 11

Supply Current

35

Zener Regulated Output
Voltage
Current

Pin 17

Maximum Output Voltage

Pins 8,13; f= 1 kHz
Vcc=9V, Maximum Gain
Vee=12V

Maximum Input Voltage
(Note 1)

Typ

9

Max

Units

16

V

45

mA

5

V
mA

5.4

0.8

0.8
1.0

Vrms
Vrms

Pins2,19;f=1 kHz, Vee=9V
Flat Response, Vcc= 12V
Gain = -10dB

1.3

1.1
1.6

Vrms
Vrms

20

30

k{1

Input Resistance

Pins 2,19; f= 1 kHz

Output Resistance

Pins 8,13; f= 1 kHz

Maximum Gain

V(Pin 12)=V(F?in 17); f= 1 kHz

-2

0

Volume Control Range

f= 1 kHz

70

75

Gain Tracking
Channell-Channel2

f= 1 kHz
odB through -40 dB
-40 dB through -60 dB

Balance Control Range

Pins8,13;f=1 kHz

{1

20

1
2

2

dB
dB

3

dB
dB

1
-26

-20

dB
dB

Bass Control Range
(Note 2)

f=40 Hz, Cb=0.39).LF
V(Pin 14)=V(Pin 17)
V(Pin 14)=OV

12
-12

15
-15

18
-18

dB
dB

Treble Control Range
(Note 2)

1= 16 kHz, C;,=O.Ol p.F
V(Pin 4) = V(Pin 17)
V(Pin4)=OV

12
-12

15
-15

18
-18

dB
dB

Total Harmonic Distortion

1=1 kHz, VIN=0.3Vrms
Gain=OdB
Gain=-30dB

0.06
0.03

0.3

%
%

Channel Separation

f = 1 kHz, Maximum Gain

Signal/Noise Ratio

Unweighted 100 Hz-20 kHz
Maximum Gain, 0 dB = 0.3 Vrms
CCIR/ ARM (Note 3)
Gain = 0 dB, VIN = 0.3 Vrms
Gain= -20 dB, VIN=1.0Vrms

Output Noise Voltage at
Minimum Gain
Supply Ripple Rejection

60

75

CCIR/ ARM (Note 3)

75

dB

80

dB

79
72

dB
dB

10

. 200 mVrms, 1 kHz Ripple

35

16

50

Control Input Currents

Pins 4, 7,9,12,14(V=0V)

-0.6

Frequency Response

- t dB (Flat Response

250

dB
-2.5

20 Hz-16 kHz)
Note 1: The maximum permissible input level is dependenl on lone and volume sellings. See Application Noles.
Note 2: The lone control range is defined by capacilors

eb and ct. See Application Noles.

Note 3: Gaussian noise, measured over a period of 50 rns per channet, with a CCIA filter referenced to 2 kHz and an average-responding meter.

1-193

p.V

p.A
kHz

Typical Performance Characteristics
Volume Control
Characteristics

lL

-28

i

)

-10

V

o

J

D CNAliNElZ

-4
-8

-21

"

I
4
VI2 - CONTR1IL VOL_ IVI

-24
-28

B'

-10 t--H'Ir-t-

i

10

i

1_11---+--+-7f

Ik

-20

ZOk

-311

, ..,40

20

110

Input Signal Handling vs
Supply Vol"ge

!.2.1

1.'
kHz
FlAT FREQUENCY

§2A ,~l!i!~
1.8

I/'

1.8

L

UUOO6

§!1.2

610,21.,6182022

6

10

0

100

SOD

5l

10

_

~i-o- r-.",
!'o,

I: :

FLAT FREDUENCY RESPONSE
BAlANCED BAINS

311

-10,-20 ,-311 -41 -50
lAIN (dBI
.. , '

"SUPPLY VOLTAGEIVI,

CIIIIDtT~Em
PtN rC1!"N
,1 PlNIZ' ,
28

I:
i

U FREIIIIEIICY RESPONSE ' - IAlAIIIIBIIAIIII

t.oa

i.o'

l....- ~

ID

'.01 I.' kHz

J.
I

'''''
',;/

i'",
i'

Channel Separation vs
Frequency

"""

g •.D3
~O.U

,

1"""'''.....

F8EOUENCY IHzl

,

0.04

!2.0

21'

~

0.05

1<2.2

-10

THOvsGain

0."

1~·-lua.

$2.1

Il1O
5'
FREQUENCY (HzI

r-...

-50

L-J-J'-'---'--L....I.-...I.-J-J

FREDUENCY 1Hz)

i

,

-10

i"'-r-i-- 2D rr;" !'o""

r-+-I~~"';" ":"'~'-'..I!--'H

, , -1& 1""'~-+--t-t-~~t"'1

-15

'0

Loudness Compensated
Volume Characteristic

-10

-zO L...-.........'-'---":-'--'-................

i

I
2
3
4
6
V4 OR V14 - CONTROL VOLTAGE IVI

Tone Characteristic (Gliln
vs Frequency)
2O,--'-:"--r--r--.-r--r-,.--,

I
0

CUT
41 H~ DR 16kHz

o

1

10

100

1/

":15

11

20

1/

-ID

II~~-+~~+-~~

! 5I-H~t""t+-t;oo.,-t-1
i _5 1---t-l-7F--t-+-~-+-I

V

:

L'l

15 Ioc:;-t-i--;;

11.4
1

0

i

-5

1/

/

I

;.' 5

iz

1\
\

;/

o

IGOST
41 Hz GR'II kHz

10

VI - CONTROl VOLTAGE (VI

Tone Characteristic (Gain
V8 Frequency)

!!

,

I

I_II

Tone Control'Ch.racterlstlc'
15

-L

7"" r"\. CHANNEll

1/

I. -12

1=1 'Hz,

~If'

-II

~

¥wI-_II9':'

'I

'. i

"'r

Balance Control
Characteristic

_

-'-

,z -41

v'

21

loa
SOD
5k
FREGUENCY IIIJI " "

10k

.'c.

Loudness Control
Characterisllc
lt5

".-100 lIlY
~ CDNJRDLI FLAT

20

!

i

15

Output Noise Voltage
vsGain

.

ID

\

-5
8

D.5

I
2 3 4
VT-CONTIOL VOLTAGE IVI

i

I- ~

!\.

•

, l·D

r...

~

.,

o

,

llINE CIINTROLI FlAT
IAlANCED lAIN.
CClR FIIlE8

:::::::l4D Hz
, 1& kHz ......

'~

-•

~:.r,

-48
-10
lAIN Idtl

:=uaC:/l' ~;.
aAwcED UlNa :'

,!U MAXIMUM UIN ,.....~
Vee ~12V ..J ~L"oI . ~II
D.I

! ....

.

0.82

,

~.-:"

~

0.01

Yt:c-av
-20

THO vs Input Voltage

-10

....

•.0

0.2

U

0.6

1.8

1.1

INPUT vOlJAGE IVlml1 '
TUH/51~-2

1-194

Application Notes
TONE RESPONSE

LOUDNESS COMPENSATION

The maximum boost and cut can be optimized for individual
applications by selection of the appropriate values of Ct (treble) and Ct. (bass).
The tone responses are defined by the relationships:

A simple loudness compensation may be effected by applying a DC control voltage to pin 7. This operates on the tone
control stages to produce an additional boost limited by the
maximum boost define!! by Cb and Ct. There is no loudness
compensation when pin 7 is connected to pin 17. Pin 7 can
be connected to pin 12 to give the loudness compensated
volume characteriStic as illustrated without the addition of
further external components. (Tone settings are for flat response, Ct. and Ct as given in Application Circuit.) Modification to the loudness characteristic is possible by changing
the capacitors Cb and Ct for a different basic response or,
by a resistor network between pins 7 and 12 for a different
threshold and slope.

1

+ 0.00065 (1

- 8b)

·C

Bass Response =

J(J) b
1

+ 0.OO0658b
j(J)Ct.

Treble Response =

1 + j(J)5500(1 - alll"'·
_-=-__
-,-_-,,-"l...:.
1 + j(J)55008tCt

Where ab=at=O for maximum bass and treble boost respectively and 8b = at = 1 for maximum cut.

SIGNAL HANDLlI'IG

For the values of Ct. and Ct of 0.39 p.F and 0.Q1 p.F as
shown in the Application Circuit, 15 dB of boost or cut is
obtained at 40 Hz and 16 kHz.

ZENER VOLTAGE
A zener voltage (pin 17=5.4V) is provided which may be
used to bias the control potentiometers. Setting a DC level
of one half of the zener voltage on the control Inputs, pins 4,' '
9, and 14, results in the balanced gain and flat response
condition. Typical spread on the zener voltage is ± 100 mV
and this must be taken into account if control signals are
used which are not referenced to the zener voltage. If this is
the case, then they will need to be derived with similar accuracy.

The volume control function of the LM1036 is carried out in
two stages, controlled by the DC voltage on pin 12, to improve signal handling cap/lbility and provide a reduction of
output noise level at reduced gain. The first stage is before
the tone control processing and provides an initial 15 dB of
gain reduction, so ensuring that the tone sections are not
overdriven by large input levels when operating with a low
volume setting. Any combination of tone and volume settings may be, used provided the output level does not exceed 1 Vrms, Vcc=12V (0.8 Vrms, Vcc=9V). At reduced
gain « -6 dB) the input stage will overload if the input level
exceeds 1.6 Vrms, Vcc=12V (1.1 Vrms, Vcc=9V). As
there is volume control:on the input. stages, the inputs may
be operated with a,lower'overload margin than would otherwise be acceptable, allowing a possible improvement in signal to noise ratio.

•
1-195

~

S!

::E
;.J

Application Circuit
. 47k .
....~,.,.,...<47k

BASsCONTIIGL

;J;D.22",

·LM1D38N

47",

P lri~

LOUDNESS

COMPENSATION

0.47",

IlALAHCE CONTROL

Ct

O,Dl";';

47k
t-------------,.,.,~----~--------_.<4~ ~~L

TUH/5142-3

Applications InfQrmat,iQn

O~TAINING MODIFIE!) RESPONSE CURVES.
The LM1036 is a dual DC controlled bass, treble, balance
and volume integrated circuit ideal for stereo audio systems.
In the various applications where the LM1036 can be used,
there may be requirements for responses different to those
of the standard application circuit given in the data sheet.
This application section details some of the simple variations possible on the standard responses, to assist the
choice of optimum characteristics for particular applications.

Figures 2 and 3 show the effect of changing the response
defining capacitors Ct and Cb to 2Ct, Cb/2 and 4Ct, Cb/4
respectively, giving increased tone control ranges. The values of the bypass capaCitors may become significant and
affect the lower frequencies in the bass response curves.
18

15
10

I

TONE CONTROLS
Summarizing the relationship given in the data sheet, basically for an increase in the treble control range Ct must be
increased, and for increased bass range Cb must be reduced.
Figure 1 shows the typical tone response obtained in the
standard application circuit. (Ct=O.01 p.F, Cb=O.39 p.F).
Response curves are given for various amounts of boost
and cut.

-5

i

21

15

0

-20

Ii

100

5DI
5k
FREGUBICY (Hzl

...,!. i!!~

51!

CllNTIIILIWIIIE,

2.0

...

1.4
0.7

!

is:

0.' :3

2Dk

2.0
1.4 ..

I

-10

!

-15

M ~

-21

...-1~

21

Co/4

III

1

::: I~

~~

1lIIII.~
.......: ,.~

-~

5.4

4.7~

v.;
~

-5

L-.L..Jc..-L..::....:::;,;.!:....-L~

21

"

5DI

~ 1-.....;
10
~

u

3.4C
2.7 •

TL/H/5142-5

5

-~
-D

100

4.I:!j

~~

Co/Z ZI:o

1

FIGURE 2. Tone Characteristic (Gain VB Frequency)

i

1-~IdIIII"'--HH~kf""!

~

5.4

4.7 ~

~

FllEGUBlCYIHzI

~;j;;;;;~~HH~~"i 3.4
-5

12

-10

5.4 !!i,..
4.7 i
10 F"'~Irl~HH---1f4:..1 4.0 3

U

~~

-15

15

z

I"'lI

,.

0

21

i

,-

g.

-1. '...-

II

21 ....-TSTAII-r-.c-U"'IT-'
DAR
OAPI'\JCAT1-r-'-"'IIN-C-,
IRC

--

IIICRfAIEO CONTROL _

2.7

,~

~t-

Co

5DI

r-

51<

2•• !
1.4i

0.7 ;
D.O :3

ZIIk

FREDUEIICY IHzI

20k

TL/H/5142-6

FIGURE 3. Tone CharacteristiC (Gain VB Frequency)

TLlH/5142-4

FIGURE 1. Tone CharacteristiC (Gain VB Frequency)

1-196

,-----------------------------------------------------------------------------,
Applications Information (Continued)
for greater control range also has the effect of flattening the
tone control extremes and this may· be utilized, with or without additional modification as outlined above, for the most
suitable tone control range and response shape.

Figure 4 shows the effect of changing Ct and Cb in the
opposite direction to Ct/2, 2Cb respectively giving reduced
control ranges. The various results corresponding to the different Ct and Cb values may be mixed if it is required to give
a particular emphasis to, for example, the bass control. The
particular case with ~/2, Ct is illustrated in Figure 5.

LOUDNESS CONTROL
The loudness control is achieved through control of the
tone sections by ·the voltage applied to pin 7; therefore, the
tone and loudness functions are not independent. There is
normally 1 dB more bass than treble boost (40 Hz-16 kHz)
with loudness control in the standard circuit. If a greater
difference is desired, it is necessary to introduce an offset
by means of Ct or Cb or by changing the nominal control
voltage ranges.
Figure 7 shows the typical loudness curves obtained in the
standard application circuit at various volume levels
(~= 0.39 p.F).

A similar effect may be obtained for the bass response by
reducing the value of the AC bypass capacitors on pins 5
(channel 1) and 16 (channel 2). The internal resistance at
these pins is 1.3 kO and the bass boost/cut will be approximately 3 dB less with Xc at this value. An example of such
modified response curves is shown in Rgure 6. The input
coupling capacitors may also modify the low frequency response.
It will be seen from Figures 2 and 3 that modifying Ct and Cb

10

!z

0

il

-5
-10

20
INCREASED BASS CONTROl. RAN8E
15 F"'-c:-+-+-+--+-I-t71 5.4
4.7
10 t--±-"'P'oIk---+--+-t--t7lll':;;;l 4.0

....

S
z

15

REDUCED CONTROL RANCIE

~~

--

,

~

EI'i

-I--::: ijiIII

I--::; t?
~

2C!a Ct/2

-15

5.4 12
4.7
ai
4.0 !=i
3.4
2.7 ::I
z
2.0 co

100. 500
FREDUENCY (Hzl

5k

~

z

.
-.
3

il

0.7 ~
0.0 co

-20
20

iii

Ai

1.4

o
~

Other Advantages of DC Controls
The DC controls make the addition of other features easy to
arrange. For example, the negative-going peaks of the output amplifiers may' be detected below a certain level, and
used to bias back the bass control from a high boost condition; to prevent overloading the speaker with low frequency
components.

Restriction of Tone Control Action at High or Low Frequencies
It may be desired in some applications to level off the tone
responses above or below certain frequencies for example
to reduce high frequence noise.
This may be achieved for the treble response by including a
resistor in series With Ct. The treble boost and cut will be 3
dB less than the standard circuit when R = Xc.

20

r-

i:
.....

5 j;;;;;;f:;;;j;;;;j~ti--t~~., 3.4
0
2.7
-5

1-"'1"''''1=:iIo'!II~-+-+''''''Ilod'''''1

Ii
ai

I

2.0
1....

!

-lIi

F--+::....,~-+-+-+-I~-'O '.7
-15 bo"""'++-r-r-r-l-t-'l 0.0 ...
3
-20
20
100
500·
5k
2011
FREOUENCY (Hzl

20k
TUH/5142-7

TUH/5142-8

FIGURE 4. Tone Characteristic (Gain vs Frequency)

FIGURE 5. Tone Characteristic (Gain vs Frequency)

10

2O..--r-T"""'---"'-"-'''''-'''''''

STANDARD MPUCIIT10N CIRCUIT

15
10

i
z

5
0

il

-5

-10

r--...
;-20 I - r-r--o ,.....,

1....-i-++-311....a-~~.....
1-t-I-,If-+--t-Pot--1H

r--

! -3D 1-"
1"-1'0.
-40

-10

'"

-50

-15

. . 7 C1IIINEmII TO . . 12

-60
100

500

Ilk

20

20k

FREOUENCY (HzI

"'-

•

.... ~t-"

...... ~
l..-"

i.-'

~_'.39""

100
500
FREOUENCY (Hzl

C.=0.01""

5k

20k
TL/H/5142-10

TUH/5142-9'

FIGURE 7. Loudness Compensated Volume
Characteristic

FIGURE 6. Tone Characteristic (Gain vs Frequency)

1-197

Applications Information (Continued)
Figures 8 and ,9 illustrate the loudness characteristics obtained,with Ct, changed.to'Cb/2 and Ct,/4 respectively, Ct
being kept at the nominal 0.01 ,...F~ These values naturally
modify the bass tone response as in Figures 2 and 3.
With pins 7 (loudness) and 12 (volume) directly connected,
loudness control starts at typicaily - 8 dB volume, with most
of the control action compl~te by -30 dB.

ance, this is easily done and high value resistors may be
used for minimal additional loading. II is possible to reduce
the rate Of onset of control to extend the active range to
-50 dB· volume control and below.
The control on pin 7 may also be divided down towards
ground bringing the control action on earlier. This'is illustrated in Figure 12, With a suitable level shifting network between pins 12 and 7, the onset of loudness control and its
rate of change may be readily modified.

Figures .1 () and 11 show the effect of resistively offsetting
the voltage applied to pin ,7 towards the control reference
voltage (pin 17). B~use th~ control inputs are high imped10

-10

i

-20

i

-30

z

-40

10

INCIIE Iseo ~ASS IJESPONSE

.... - ~
r-..... r-...
--,..... 1'",r.i

Q,lZ

;/

1-30

"

'r--.

,

.............
......

"

Q,/4 Ct

-50
-80

sao

100

i"'

-40

I" ~ './"

-80
20

1- 28

f""
~

I""':"

-50

'-10

.... 1-

I--

INCllEASBI BASS RESPONSE

III

20

ZGk

".-

,

I,...; "
I,...; '-,
;/

sao

100

5k

ZGk

FREOUENCY (Hzl

FREOUENCY (Hzl
TUH/S142-11

TUH/S142-12

FIGURE 8. Loudness Compensated Volume
Characteristic
10

-10

is

-20

~

-30

-40 b
-50
:':80

10

=::'~~1If

•
!z

FIGURE 9. Loudness Compensated Volume
Characteristic

I-

i

f""
---- f""

-50

Co-D.• "

!:i=I.I1"

'5011
III
FREQUEIICY (Hzl

-30

-40

"

..~1'7·
laD

iii"
a-ZG

.... ~I-

....... ~

"171.'~

ZG

-1 •

....

..... ~

::-::.":.:r';F

-80

ZGk

1---

r-

100..

'"
~zil~l

!'.....

... " ,.'......

20

100

o
-10

(-20
z
i -30

-

r-

r-.
-40
-80

TUH/S142-14

--

~:"U:.~ar:'':
I-

..... , "

i" .....
I'
......
~
1"r-.... .......
~

I,...; '-,

P' -

~

20
,

20k

FIGURE 11. Loudness Compensated Volume
Characteristic

""":'~~

-50

..... ~ i'-"

500
III
FREQUENCY (Hzl

TL/H/S142-13

FIGURE 10. Loudness Compensated Volume
Characteristic
10

-

....
.... ~ I-

100

V

/

-'
Co-o....
c,=0.11,.F

508
5k
FREOUENCY (Hzl

20k
TL/H/S142-1S

FIGURE 12. Loudness Compensated Volume Characteristic

1.198

~--------------------------------------------------~~

Applications Information (Continued)
When adjusted for maximum boost in the usual application
circuit, the LM1036 cannot give additional boost from the
loudness control with reducing gain. If it is required, some
additional boost can be obtained by restricting the tone control range and modifying Ct, Cb, to compensate. A circuit
illustrating this for the case of bass boost is shown in Figure
13. The resulting responses are given in Figure 14 showing
the continuing loudness control action possible with bass
boost previously applied.

USE OF THE LM1036 ABOVE AUDIO FREQUENCIES
The LM1036 has a basic response typically 1 dB down at
250 kHz (tone controls flat) and therefore by scaling Cb and
Ct, it is possible to arrange for operation over a wide frequency range for possible use in wide band equalization
applications. As an example Flflure 15 shows the responses
obtained centered on 10 kHz with ~=0.039 ,...F and
Ct=0.001 ,...F.

....
§

10
TOP VIEW

TL/H/5142-16

FIGURE 13. Modified Application Circuit for Additional Bass Boost with Loudness Control

10

20

~~~T--r-r'--T-T-'

.lx..UM am AND TlEBU_
15 ~

o

i

~

10

-10

!z

-20 I-"'I-!rj..;~:-+-+-t--t~....,

! -30

ili

-5

-40

~-+-+-+

-10

-50

I-+-IH-I--+-+-+-+-1

-15

-20
100

500
511
FREQUENCY (Hz)

20k

1\
1./

P"
20D

TUH/5142-17

V

.J,.., I" .... v

eoeD.
Ct=D.~"" j

0

I'..

1\

~Q1.UM WI MDTREILE CUT~

1

lk

5k
IiDII
FREQUENCY (Hz)

20Dk
TL/H/5142-18

FIGURE 14. Loudness Compensated Volume
Characteristic

FIGURE 15. Tone Characteristic (Gain vs Frequency)

1-199

II

LM1036

en

3'

iNTEiiNAL _
11 SUPPLY

~7kI)

f !_.
"'t~.l
CH 2

VOLUME

WWME AND BALANCE

· 1 1 · (!) r ..

II

--jO::-

--I';""A ~

Il._.L..

r~

1~'1

"2~
Ci'
a.

en

n

:::r
CD
3

!.
0'
c

ii'

3l1li

co
Dl
3
'0
iil
(')

Uk

~

10

~

iil

~

""
20

100
3(18)

TREBLE CAlllCiTOR

" Connections reversed

C
'!:
~

~

u;

4
TREBLE CDIITRDL

7
LDUiIN£SS
COMPENSATiIIH

14
BASS
CONTROL

PRELIMINARY

tflNational Semiconductor

LM1971
,..,Pot™ Digitally Controlled 62 dB
Audio Attenuator with Mute
General Description

Key Specifications

The LM1971 is a digitally controlled single channel audio
attenuator fabricated on a CMOS process. Attenuation is
variable in 1 dB steps from 0 dB-62 dB. A mute function
disconnects the input signal from the output, providing a
minimum of 80 dB of attenuation. The attenuation curve can
be customized through software to fit the desired application.
The performance of a ,..Pot is demonstrated through its ability to instantly change attenuation levels without audible
clicks or pops, excellent signal-to-noise ratio (80 dB minimum), and low Total Harmonic Distortion plus noise
(THD+N) of 0.01%.

•
•
•
•

The LM1971 is controlled by a 3-wire serial digital interface
which is TTL and CMOS compatible. The LM1971 receives
data that selects the desired attenuation setting on the
DATA line. The LOAD/SHIFT line enables the data input
registers and the CLOCK line provides system timing. Additionally, the interface is compatible with National Semiconductor's HPC line of microcontrollers.

•
•
•
•
•

Total harmonic distortion + noise
0.01 % (typ)
Frequency response
20 kHz (-3 dB) (min)
Attenuation range (excluding mute)
62 dB (min)
Signal-to-noise ratio
80 dB (min)

Features
• 3-wire serial interface
• 80 dB mute attenuation
• Pop and click free attenuation changes

Applications
Music reproduction systems
Sound reinforcement systems
Electronic music (MIDI)
Personal computer audio control
Communication systems

Typical Application

Connection Diagram
Small Outline Molded Package or
Dual-In-Llne Plastic Package
Lt.l1971

Audio
Input

a

4
Digital
Control

5
6

IN

OUT

r=t>r~~;o
Output

_ I

•

Analog Ref -

1

Output -

2

7 .... Voo

Digital Gnd -

3

6 I- Clock

Load/Shift -

4

5

1/2 Lr412ACN

aI-Input

I- Data

LD/SHH
TL/H/12353-2

DATA

Top View

CLOCK

TUH/12353-1

FIGURE 1. Typical Audio Attenuator Application Circuit

1-201

Order Number LM1971M
orLM1971N
See NS Package Number
M08A or NOSE

II

~

S)

,----------------------------------------------------------------------------,

~ lfIN~:tional

Semiconductor·

LM1972',··
JLPot™ 2-Channel 78dB Audio Attenuator with Mute
General Description

Key Specifications

The LM1972 is a digitally controlled 2-,channel 78dB audio
attenuator fabricated on a CMOS process. Each channel
has attenuation steps of 0.5dB from OdB-47;5dB, 1.0dB
steps from 48dB-78dB, with a mute function attenuating
104dB. Its logarithmic attenuation curve ~an be Customized
through software to fit the desired application.
The performance of a ",Pot is demonstrated through its e!Ccellent Signal-to-Noise Ratio, extremely low (THD+N), and
high channel separation. Each ",Pot contains a l:!1ute function that disconnects the input signal from the output, providing a minimum attenuation of 96dB. Transitions between
any attenuation settings are pop free.
The LM1972's 3-wire serial digital inter:face is TTL and
CMOS compatible; receiving data that selects a channel
and the desired attenuation level. The Data-Out pin of the
LM1972 allows multiple ",PotS to be daisy-chained together,
reducing the number of enable and data lines to
routed
for a given application.

•
•
•
•
•
•

Typical Application

Connection Diagram

be

Total Harmonic Distortion + Noise
0.00;3% (max)
Frequency response"
100 kHz (-3dB) (min)
Attenuation range (excluding mute)
l8dB (typ)
Differential attenuation
.
± 0.25dB (max)
Signal-ta-noise ratio (ref. 4 Vrms)
110dB (min)
Channel separation
100dB (min)

Features
•
•
•
•

3-wire serial interface
Daisy-chain capability
104dB mute attenuation
Pop and click free attenuation changes

Applications
• Automated studio mixing consoles
• Music reproduction systems
•. Sound reinforcement systems
• Electronic music (MIDI)
• Personal computer audio pontrol

Dual-In-Llne Plastic or
Surface Mount Package
GND AC
OUTI

AUDIO
OUT#1

1.

20

IN2

2

19

GND2

GNDI

Vss l

INI

OUT2

GND AC

GND AC

GND AC
LNI972
Ul

AUDIO
OUT#2

VDD 2

Vss 2

GNO AC

LOGIC GND

VDD 1
DATA-OUT

CLOCK

DATA-IN

LOAD/SHIFT

TLlH/1197B-2
TL/H/1197B-l

FIGURE 1. Typical Audio Attenuator Application Circuit

1-202

Top View

Order Number LM1972M or LM1972N
See NS Package Number M20B or N20A

r

Absolute Maximum Ratings

....

iii:

(Notes I, 2)

CD

......

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Soldering Information
N Package (10 sec.)
Storage Temperature

Supply Voltage (Voo-Vss)
Voltage at Any Pin
Power Dissipation (Note 3)

Operating Ratings (Notes I, 2)

+ 260"C

N

- 65·C to + 15O"C

15V
Vss - 0.2V to Voo + 0.2V
150mW
2000V
150·C

ESD Susceptability (Note 4)
Junction Temperature

Temperature Range
TMIN S;TA S;TMAX
Supply Voltage (Voo - Vss)

TUIN

TA

O"C

S;TA

TUAX
S; +70"C
4.5Vto 12V

Electrical Characteristics (Notes I, 2)
The following specifications apply for all channels with Voo = +6V, Vss = -6V; VIN = 5.5 Vpk, and f = 1 kHz, unless
otherwise specified. Limits apply for TA = 25·C. Digital inputs are TTL and CMOS compatible.
LM1972
Symbol

Parameter

Conditions

2

4

mA(max)

0.003

% (max)

OdB Attenuation for VIN
VCH measured@ -78dB

110

100

dB (min)

Inputs are AC Grounded
@ -12dB Attenuation
A-Weighted

120

110

dB (min)

Supply Current

Inputs are AC Grounded

Total Harmonic Distortion plus Noise

VIN = 0.5 Vpk @ OdB Attenuation

XTalk

Crosstalk (Channel Separation)

SNR

Signal-to-Noise Ratio

ILEAK

Mute Attenuation

104

Attenuation Step Size Error

OdB to -47.5dB
-48dBto -78dB

Absolute Attenuation Error

Attenuation @OdB
Attenuation @ - 20dB
Attenuation @ -40dB
Attenuation @ - 60dB
Attenuation @ - 78dB

Channel-to-Channel Attenuation
Tracking Error

Attenuation @OdB, -20dB, -40dB, -60dB
Attenuation @ - 78dB

Analog Input Leakage Current

Inputs are AC Grounded

LOAD/SHIFT

I

-l
CLOCK

DATA-OUT

OLD A7

0.03
19.8
39.5
59.3
76.3

10.0

• • •
I- >150 ns

-l

96

dB (min)

±0.05
±0.25

dB (max)
dB (max)

0.5
19.0
39.0
57.5
74.5

dB (min)
dB (min)
dB (min)
dB (min)
dB (min)

±0.5
±0.75

dB (max)
dB (max)

100

nA(max)

Ir-

>150 ns

• • • ~

XXx\'

DATA-IN~

Units
(Limits)

Limit
(Note 6)

0.0008

Is
THD+N

AM

Typical
(Note 5)

A7

A6

OLD A6

• • • ~

A5

OLD A5

OLD A4

B -

VALID DATA

• • •

ZZZZ

FIGURE 2. Timing Diagram

1-203

V(A7

- UNKNOWN/DON'T CARE
TLlH/11978-3

•

Electrical Characteristics (Notes 1,2)
The following specifications apply for all channels with VOO = +6V, VSS = -6V, VIN = 5.5 Vpk, and,f = 1 kHz, unless
otherwise specified. Limits apply for TA = 25°C. Digital inputs are TIL and CMOS compatible. (Qontinued)
LM1972

Symbol

Parameter

'''f'

Conditions
/'

Units
(Umits)

Typical
(Note 5)

Umlt
(Note 6)

40

20
60

kO(min)
kO(max)

1.0

±100

nA(max)

2

MHz (max)

RIN

AC Input Impedance

Pins 4, 20, VIN = 1.0 Vpk, f = 1 kHz

liN

Input Current

@

Pins 9~ 10, 11

fCLK

Clock Frequency

VIH

High-Lever Input Voltage

@

Pins 9,10,11

2.0

V (min)

VIL

Low-Level Input Voltage

@

Pins 9,10,11

0.8

V (max)

Data-Out Leve,ls (Pin 12)

Voo= 6V, Vss=OV

0.1
5.9

V (max)
V (min)

@

OV

< VIN < 5V

3

Note 1: All voltages are measured with respect to GNO pins (1, 3, 5,6, 14, 16, 19), unless otherwise specified.
Note 2: Absolute MBXimuin Ratings indicate limits beyond which dama98 10 the device may occur. Operating Ratings indicate conditions for Which the devica is
functional, but do not guarantee specific performance limits. E/sctrica/ Charac_tics state DC and AC electrical specHications under particular test conditions
which guarantee specifIC performance limits. This assumes that the device is within the Operating Ratings. SpecHicatlons are not guaranteed for parame/ers where
no limit is given, however, the typical value is a good indication of device performance.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 8JA, and the ambient temperature TA. The maximum
allowable power dissipation is PO = (TJMAX - TAl/8JA or the number given in the Absolute Maximum Rating,s, whichever is lower. For the LM1972, TJMAX =
+ 15O"C, and the typical junction-Io-ambient thermal resistance, when board mounted, Is 65"C/W.
Note 4: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 5: Typical. are measured at 25"C and represent the parametric norm.
Note 6: Umits are guarenieed to National's AOOL (Avera98 Output Quality leve~.

"

1-204

,-----------------------------------------------------------------------------, r
!'II:

....

Pin Description

CC)

Signal Ground (3, 19): Each input has its own independent
ground, GND1 and GND2.

Data-out (12): This pin is used in daisy-chain mode where
more than one "Pot is controlled via the same data line. As
the data is clocked into the chain from the "C, the preceding data in the shift register is shifted out the DATA-OUT pin
to the next "Pot in the chain or to ground if it is the last "Pot
in the chain. The LOAD/SHIFT line goes high once all of the
new data has been shifted into each of its respective registers.

Signal Input (4, 20): There are 2 independent signal inputs,
IN1 and IN2.
Signal Output (2, 17): There are 2 independent signal outputs, OUT1 and OUT2.
Voltage Supply (13, 15): Positive voltage supply pins, V001
and V002.
Voltage Supply (7, 18): Negative voltage supply pins, VSS1
and VSS2. To be tied to ground in a single supply configuration.
AC Ground (1, 5, 6, 14, 16): These five pins are not physically connected to the die in any way (i.e., No bondwires).
These pins must be AC grounded to prevent Signal coupling
between any of the pins nearby. Pin 14 should be connected to pins 13 and 15 for ease of wiring and the best isolation, as an example.
Logic Ground (8): Digital Signal ground for the interface
lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.

......

N

Connection Diagram
GND AC- 1.

191-GND2

GND1- 3

181-Vss 1

IN1- 4

17 1-0UT2

GND AC- 5

16 I-GND AC

GND AC- 6

15 !-Voo2

Vss2- 7

Clock (9): The clock input accepts a TTL or CMOS level
signal. The clock input is used to load data into the internal
shift register on the rising edge of the input clock waveform.

LOGIC GND- 8
CLOCK- 9

Load/Shift (10): The load/shift input accepts a TTL or
CMOS level signal. This is the enable pin of the device,
allowing data to be clocked in while this input is low (OV).

20 I-IN2

OUT1- 2

LOAD/SHIFT -

10

14 I-GND AC
131- Voo1
12I-DATA-OUT
11I-DATA-IN
TL/H/1197B-4

Data-In (11): The data-in input accepts a TTL or CMOS
level signal. This pin is used to accept serial data from a
microcontroller that will be latched and decoded to change
a channel's attenuation level.

•
1-205

Typical Performance Characteristics
SUpply 'Current V8
Supply Voltage

Nol8e Floor Spectrum by FFT
Amplitude V8 Frequency

SUpply Current V8
Temperature
0.0
-20.0

.'

-40.0

-

cil -80.01-1-I-'-HHHHH'---I'---I

~

~

..... I-'""

HH-t--+--+-+-+++--f

-60.01-'-1-I-HHHHH'---I'---I
.. -100.0 .....f-f-HHHHHHH
-120.0 t-I-I-I-I-HHHH'---I
-140.0

1IfllI............~.......~

-160.0 I-'-I-'-I-'-I-'-I-'-I-'-I-'-HH'---I

o
8

10

11

-180.00,'"=.0:-'-7
4,0:,k:-'-::-8.0:,k--'-:I"'Z.'=Ok--'-:I-:6.'=Ok--'-:2::!0.0k·
2.0k B.Ok 10.0k 14.0k 18.0k

12

FREQUENCY ~Hz)

TEWPERATURE (OC)

SUPPLY VOLTAGE (V)

THO vs VOUT at
1 KHzbyFFT
Voo - Vss = 12V

THO V8 Freq by FFT
VOO - VSs = 12V
1

I

:Crosst;llk Test

-lg:g rr.V"',.~'~I;;'I~vp~p=;;n~lo:=::;cH;';I=;@i:"::'Od::'iiB:'I.r.Ap;:]

_ _ THD (11)

CH2@ 0.-20.-40.-78dB

r-'

:~g:g
-11 .
10
9
-30.0 11IOHZ150n.

!XXX
2EJXXXX/X,
V(A7

ZZZZ

FIGURE 2. Timing Diagram
,1-212

~

.' J I

• • •

DATA~IN

Units
(Limits)

0.0008

IS
THD+N

Mute Attenuation '

Limit
{Note 6)

- UNKNOWN/DON'T CARE
Tl/H/11958-3

Electrical Characteristics

(Notes 1, 2)
The following specifications apply for all channels with Vee = +6V, VSS = -6V, VIN = 5.5 Vpk, and f =
otherwise specified. limits apply for T A = 25'C. Digital inputs are TTL and CMOS compatible. (Continued)

1 kHz, unless

. LM1973
Symbol

Parameter

Conditions

Units
Typical

Limit

(Note 5)

(Note 6)

40

(Limits)

20

kO(min)

60

kO(max)

±100

nA(max)

2

MHz (max)

RIN

AC Input Impedance

Pins 2, 4,18, VIN = 1.0 Vpk, f = 1 kHz

liN

Input Current

@ Pins 9, 10, 11 @ OV

fCLK

Clock Frequency

VIH

High-Level Input Voltage

@Pins9,10,11

2.0

V (min)

VIL

Low-Level Input Voltage

@ Pins 9, 10, 11

0.8

V (max)

Data-Out Levels (Pin 12)

Vee=6V, Vss=OV

0.1

V (max)

5.9

V (min)

< VIN < 5V

1.0
3

Note I: All voHages are measured with respect to GNO (pins 1,3, 5, 14, 17), unless otherwise specWied.
Note 2: Absolute MaxImum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the devica is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specWications under particular test conditions
which guerantee specific performance limits. This assumes that the devica is wilhln the Operating Ratings. Specifications are not gueranteed for parameters where
no limit is given, however, the typical value is a good Indication of device performance.
Note 3: The maximum power dissipation must be dereted at elevated temperatures and is dictated by TJMAXo 8JA, and the ambient temperature TA. The maximum
allowable power dissipation is PO ~ (TJMAX - TAl/8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LM1973N, TJMAX ~
+ 150"C, and the typicaljunction-lo-ambient thermal resistance, when board mounted, is 65"C/W.
Note 4: Human body model, 100 pF discharged ·through a 1.5 kG resistor.
Not. 5: Typicals are measured at 25·C and represent the parametric norm.
Note 6: Umits are guaranteed to National's AOOL (Average Output Quality LeveQ.
Note 7: At the present time the Crosstalk measurement is specified as a typical only, which is due to a hardware limitation of the automated. test eqUipment.

•
1-213

Pin Description
Signal Ground (1, 5,17): Each input has its own independent ground, GND1, GND2, and GND3.
Signal Input (2, 4, 18): There are 3 indePendent signal inputs, IN1, IN2, and IN3.
Signal Output (6; 16, 20): There are 3 independent Signal
outputs, OUT1, OUT2, and OUT3.
Voltage Supply (13, 15): Positive voltage supply pins, VOOI
and VOO2.
Voltage Supply (7,19): Negative voltage supply pins, VSSI
and VSS2. To be tied to ground in a single supply configuration.
AC Ground (3, 14): These two pins are not physically connected to the die in any way (i.e., No bondwires). These pins
must be AC grounded to prevent signal coupling between
any of the pins nearby. Pin 14 should be connected to pins
13 and 15 for ease of wiring and the best isolation.
Logic Ground (8): Digital signal ground for the interface
lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.
Clock (9): rhe clOck input accepts a TIL or CMOS level
signal. The clock input is used to load data into the internal
shift register on the rising edge of the input clock waveform.
load/Shift (10): The load/shift input accepts 'a TIL or
CMOS level signal. This is the enable pin of the devk;e,
allowing data to be clocked in while this input is low (OV).
Data-In (11): The data-in input accepts a TIL or CMOS
level signal. This pin is used to accept serial data from a
microC9ntrolier that will be, latched and decoded to change
a channel's attenuation level.

Data..()ut (12J:"This pin is used in daisy-chain mode where
more than one ~Pot is controlled via the same data line. As
the data is clocked into the chain from the ~C, the preceding data in the shift register is shifted out the DATA-OUT pin
to the next ~Pot in the chain or to ground if it is the last ~Pot
in the chain. The LOAD/SHIFT line goes high once all of the
new data has been shifted into each of its respective registers.

Connection Diagram
GND2- 1.
IN2- 2
GND AC- 3

20 -OUT2
19 -Vss l
18 -IN3

IN1- 4

17 -GND3

GND1- 5

16 -OUT3

OUTt- 6

15 -Voo 2
14 -GND AC

Vss2- 7
LOGIC GND- 8
CLOCK- 9
LOAD/SHIFT -

10

13 -Voo l
12 -DATA-OUT
11 -DATA~I,N
TLlHI11958-4

1-214

Typical Performance Characteristics
Supply Current vs
Supply Voltage

Noise Floor Spectrum by FFT
Amplitude vs Frequency

Supply Current vs
Temperature
0.0

[ -139. 14~

-20.0

~ Qd!oooij

Ap

-40.01-t-t-t-t-HHHHH

-

r-'"

..- r-

-60.01-1-1-1-I-HHHH--1

..... -

i -80.01-1-1-1-t--HHHHH
.., -100.0 1-t-t-I-I-HHHH--1
-120.01-1-1-1-1-I-HHH--1
-140.0

iII'~IIMjIllolfIi'!ll""• •~

-160.0 1 - I - I - I - I - r r H H H
OL-~~~

0
10

B

II

o

12

20

__L-~-L~~
60
BO

-IBO.O 0"::.0~-:-4."'Ok~':"B.Ok::-"'1"'2.'::Ok-LI"'6.'::Ok-'-:2::'0.0k
2.Ok 6.Ok 10.Ok 14.0k IB.Ok,
fREQUENCY (Hz)

TEWPERATURE (Oc)

SUPPLY VOLTAGE (V)

THOvsVOUTat
1 kHz by FFT
VOO - VSS = 12V

THO vs Freq by FFT
Voo - Vss = 12V
0.1

Crosstalk Test

O. I
____ THO (,,)

0.01

g

~

c

c

"

0.0 I

g

"

0.001

0.00 I

0.000 I
100

Ik

10k

0.1

lOOk

0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0

%

c+

"

0.001

100

Ik

10k 20k

FFT of 20 kHz THO

0.001

0.010•

g
0.010

OdB
- 6dB
20

10

FFT of 1 kHz THO

0.1

~

-20dB

fREQUENCY (Hz)

THO + Nvs
Frequency and Amplitude

%

-4

-80.0

-90.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0

fREQUENCY (Hz)

g

-II

g
0.0001

•

0.001

%

+

~ 0.0001
10"

10"

I"0"'.0~-2."'Ok~-4.0"'k~B"'.0"'k-LB,-J.0'-k-LI,-J0.Ok
1.0k 3.0k 5.0k 7.0k 9.0k

I" O.Ok 20.0k
40.0k
60.0k
BO.Ok
10.Ok
30.Ok
50.0k
70.0k

fREQUENCY (Hz)

fREQUENCY (Hz)

fREQUENCY (Hz)

THO + N va Amplitude
f = 20 HZ, Voo = ±6V
VIN into CH1 @ 0 dB

THO + N vs Amplitude
f = 1 kHz, Voo = ±6V
VIN Into CH1 @ 0 dB

THO + N vs Amplitude
f= 20kHz,Voo = ±6V
VIN into CH1 @ 0 dB

0.1
0.1,,_

g

0,,1"_

%

c+ 0.010

"

O.OOIII~~'II~MI

0.001

0.0001

0.00015_LJOU.mllo!....I--~---'-"uu.w....~L.....J....J...J

50m 0.1
INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

o.oo0'sLJoU.mllo!....I--~'-'--uu.w....--..J~...J...J

INPUT VOLTAGE (V)

TUH/11958-6

1-215

•

Application Information

"

ATTENUATION STEP SCHEME

LM1973 Channel Attenuation
vs Digital Step Value
(ProgrammecU.OdB Ste")-

The fundamental attenuation step scheme for the LM1973
""Pdt IS shown in FigureS. This attenuation step scheme,
however, can be changed through programming techniques
to fit different application. requirements. One such exarriple
would be a constant logarithmic attenuation scheme of 2dB
steps for. a panning function as shown in Figure: 5. The only
restriction to the customization of attenuation schemes are
the given attenuation levels and their corresponding data
bits shown in Table I. The device will change attenuatic;lO
levels only when a channel address is recognized. When
recognized, the attei'luatiori"level will be changed corre· .
sponding to the data bits shown in Table I. As shown.in
Figure 6, an LM1973 can be·configured with a mono audio
signal level control and with., a' panning control which sepa·
rates the mono signal into left and right channels. This cir·
cuit may utilize the fundamental attenuation scheme of the
LM1973 for the level control, but also possess a constant·
2dB panning control for the left and right channels as stated
earlier.

0

............ Attenuation Point t

-10

,

-20
0;,

3
.~

~

!

1
tJ

-...

-30
-40

2.0dB St.

-50
-60

-....

-70
-80
·90

Nute Point

-100
0

10

20

~

___ Attenuation

TLlH/II958-15

POinU
MONO
AUDIO-IN

-20
0;,

3

i

!

~

~

LEVEL

-30

LM1973
Ul

-50

~
....

.....--

...

LEn
AUDIO-OUT

PAN-L

-

...

RIGHT
AUDIO-OUT

PAN-R

LOdS St. s

-40

40

FIGURE 5. LM1973 2.OdB Attenuation Step Scheme

or--.
O.SdB St. s

30

Digital Step Value

LM1973 Channel Attenuation
vII,Dlgltal Step Value
-10

...

I

-60·

2.0dS St. s

-70
-80
·90

TLlH/I1958-8

Nut. Point

~IOO'

o·

10

20

30
0i~it81

4.0

50

80

FIGURE 6. Mono Level Cont!'C)i with Panning Circuit

80

70

INPUT IMPEDANCE

Step Value

The input impedance of • p.Pot is constant at a nominal
40 kO. To eliminate any unWanted DC components from
propagating through the device it is common Ie? use 1 ""F
input coupling caps. This is nOt neces~ry, however, if the
dc offset from the previous stagE! is negligible. For higher
performance systems, input coupling caps are .preferred,

TLlH/I1958-7

FIGURE 3. LM1973 Attel:luatlon Step Scheme
LM1973 Channel Attenuation
vs Digital Step Value
(Programmed UdB Steps)
0

OUTPUT IMPEDANCE

____ Attenuation Point

-10
-20
0;,

3

i

.~
~

~

-30

1.0dB'Ste

-40
-50 .
-60

,

'2.0dB St. s

-70

The output of a ""Pot varies typically between 25 kO and
. 35 kO and changes nonlinearly with step changes. Since a
,. ""Pot is made up of a resistor ladder network with a logarith·
mic attenuation, the output impedance is nonlinear. Due to
this 'Configuration, a ""Pot cannot be 'col)sidered as a linear
potentiometer, but can be considered only as a logarithmic
.attenuator.
It should be noted that the linearity ofa !loPot cannot be
me.sured directly without a buffer because th", input imped.
ance of most measurement systems is not high enough to
pr()vide the required accuracy. Due to the low impedance of
the measurement system, the output of the ""Pot would be
loaded down and an incorrect readiflg will resUlt. To prevent
loading from occurring, a JFET input op amp should be used
as the buffer/amplifier. The performance of a ""Pot is limited
only by the performance of the external buffer/amplifier.

'.

-80
-90
Nute Point

-100
0

lQ

20

30

40

50

60

70

80

Digltal'Step Value

TL/H/I1958-14

FIGURE 4. Ui1973 1.0dB and 2.0dB
Attenuation Step Scheme

1·216

Application Information (Continued)
MUTE FUNCTION

TABLE I. LM1973 Micropot Attenuator
Register Set Description

One major feature of a ,...Pot is its ability to mute the input
signal to an attenuation level of 104dB as shown in Figure 3.
This is accomplished internally by physically isolating the
output from the input while also grounding the output pin
through approximately 2 kn.

LSB

MSB

Address Register (Byte 0)

00000000

The mute function is obtained during power-up of the device
or by sending any binary data of 01001111 and above (to
11111111) serially to the device. The device may be placed
into mute from a previous attenuation setting by sending
any of the above data. This allows the designer to place a
mute button onto his system which could cause a microcontroller to send the appropriate data to a ,...Pot and thus mute
any or all channels. Since this function is achieved through
software, the designer has a great amount of flexibility in
configuring the system.

Channel 1

00000001

Channel 2

00000010

Channel 3

Data Register (Byte 1)
Contents

DC INPUTS
Although the ,...Pot was designed to be used as an attenuator for signals within the audio spectrum, the device is capable of tracking an input DC voltage. The device will track DC
voltages to a diode drop above each sl,lpply rail.
One point to remember about DC tracking is that with a
buffer at the output of the ,...Pot, the resolution of DC tracking will depend upon the gain configuration of that output
buffer and its supply voltage. It should also be remembered
that the output buffer's supply voltage does'not have to be
the same as the ,...Pot's supply voltage. This could allow for
more resolution when DC traCking.

Attenuation Level dB

00000000

0.0

00000001

0.5

00000010

1.0

00000011

1.5

.....

....

00011110

15.0

00011111

15.5

00100000

16.0

00100001

17.0

00100010

18.0

.....
.....

....

SERIAL DATA FORMAT

00111110

46.0

The LM1973 uses a 3-wire serial communication format that
is easily controlled by a microcontroller. The timing for the
3-wire set, comprised of DATA-IN, CLOCK, and LOAD/
SHIFT is shown in Figure 2. Figure 8 exhibits in block diagram form how the digital interface controls the tap
switches which select the appropriate attenuation level. As
depicted in Figure 2, the LOAD/SHIFT line is to go low at
least 150 ns before the rising edge of the first clock pulse
and is to remain low throughout the transmission of each
set of 16 data bits. The serial data is comprised of 8 bits for
channel selection and 8 bits for attenuation setting. For both
address data and attenuation setting data, the MSB is sent
first and the 8 bits of address data are to be sent before the
8 bits of attenuation data. Please refer to Figure 7 to confirm
the serial data format transfer process.

0011 1111

47.0

01000000

48.0

01000001

50.0

0100 0010

52.0

.....
.....

....

01001100

72.0

01001101

74.0

01001110

76.0

01001111

100.0 (Mute)

01010000
.....
.....

100.0 (Mute)

11111110

100.0 (Mute)

11111111

100.0 (Mute)

MSB

....

MSB

-+1

LM 1973
DATA-IN

I
ATTENUATION SETTING

CHANNEL SELECTION

BYTE 1

BYTE 0
TL/H/II958-9

FIGURE 7. Serial Data Format Transfer Process

1-217

•

~

G;

:::E

..a

r-----------------------------------------------------------------------,
Application Information (Continued)
p.Pot SYSTEM ARCHITECTURE

Your

The p.Pot's digital riiterface is essentially a shift register,
where serial data is shifted in, latched, and then decoded.
As new data is shifted into the DATA-IN pin, the previously
latched data is 'shiftl!d out 'the DATA-OUT pin. Once the
data is shifted in, the LOAD/SHIFT line ,goes high, latching
in the new data. The data is then decoded and the appropriate switch is activated to set the desired attenuation level
for the selected channel. This process is continued each
and every time an attenuation change is made. Each channel is updated, only, when tl'lilt'ehannel is selected for an
attenuator.c!1ange or ~he ,system is powered do~n and then
back up again. When the p.Pot is powered up, each channel
is placed into the muted mode.

. Tap Switches

TL/H/11958-11

FIGURE 9_ p.Pot Ladder Architecture
DIGITAL LINE COMPATIBILITY ,
The ,p.Pot's digital interface section is compatible with either
TIL or CMOS logic due to',the shift register inputs acting
upon a threshold voltage of 2 diode drops or approximately
1.4V.

p.Pot LADDER ARCHITECTURE
Each channel of a p.Pot has its own independent resistor
ladder network. As shown in Figure 9, the ladder consists of
multiple R1/R2 elements which make up th~ atten!lation
scheme. Within each element there are tap switches that
select the appropriate attenuation level corresponding to
t,he data bits in Table I. It can be seen ,In Figure 9 that the
input impedance for the channel is a constant value regardless of which tap switch is selected, while the output impedance varies according to the tap switc!,! selected.

DIGITAL DATA-oUT PIN
The DATA-OUT pin is available for daisy-chain system configurations where multiple p.Pots will be used. The use of the
daisy-chain' configuration allows the system deSigner to use
only one DATA and one LOAD/SHIFT line per chain, thus
simplifying PCB trace layouts.
In order to provide the highest level of 'channel separation
and isolate any of the Signal lines from digital noise,' the
DATA-OUT pin should be terminated through a 2 kO resistot if not used. The pin may be left floating, however, any
signal noise on that line may couple to adjacent lines creating higher noise specs.

LOAD/SHIFT

CLOCK

INTERNAL BUS
SHIFT
REGISTER

TO MULTIPLE
. ATTENUATOR
CONTROLS

DATA-IN,

GND1

GND2
TLlH/1195B-10

FIGURE 8.p.Pot System Arcl:lltecture

1-218

Application Information

(Continued)

DAISY-CHAIN CAPABILITY
Since the ",Pot's digital interface is essentially a shift register, multiple ",Pots can be programmed utilizing the same
data and load/shift lines. As shown in Figure 10, for an
n-",Pot daisy-chain, there are 16n bits to be shifted and
loaded for the chain. The data loading sequence is the
same for n-",pots as it is for one ",Pot. First the LOAD/
SHIFT line goes low, then the data is clocked in sequentially
while the preceding data in each ",Pot is shifted out the
DATA-OUT pin to the next ",Pot in the chain or to ground if it
is the last ",Pot in the chain. Then the LOAD/SHIFT line
goes high; latching the data into each of their corresponding
",Pots. The data is then decoded according to the address
(channel selection) and the appropriate tap switch controlling the attenuation level is selected.

Third, the output of a ",Pot needs to see a high impedance
to prevent loading and subsequent linearity errors from
ocurring. A JFET input buffer provides a high input impedance to the output of the ",Pot so that this does not occur.
Clicks and pops can be avoided by using a JFET input buffer/amplifier such as an LF412ACN. The LF412 has a high
input impedance and exhibits both a low noise floor and low
THO + N throughout the audio spectrum which maintains
signal integrity and linearity for the system. The performance of the system solution is entirely dependent upon the
quality and performance of the JFET input buffer/amplifier.
LOGARITHMIC GAIN AMPLIFIER,
The ",Pot is capable of being used in the feedback loop of
an amplifier, however, as stated previously, the output of the
",Pot needs to see a high impedance in order to maintain its
high performance and linearity. Again, loading the output will
change the values of attenuation for the device. As shown
in Figure II, a ",Pot used in the feedback loop creates a
logarithmic gain amplifier. In this configuration the attenuation levels from Table I, now become gain levels with the
largest possible gain value being 76dB. For most applications 76dB of gain will cause signal clipping to occur, however, because of the ",Pot's versatility the gain can be controlled through programming such that the Clipping level of
the system is never obtained. An important point to remember is that when in mute mode the, input is disconnected
from the output. In this configuration this will place the amplifier in its open loop gain state, thus resulting in severe
comparator action. Care should be taken with the programming and design of this type of circuit. To provide the best
performance, a JFET'input amplifier should be used.

CROSSTALK MEASUREMENTS
The crosstalk of a ",Pot as shown in the Typical Performance Characterlatlcs section was obtained by placing a
signal on one channel and measuring the level at the output
of another channel of the same frequency. It is important to
be sure that the signal level being measured is of the same
frequency such that a true indication of crosstalk may be
obtained. Also, to ensure an accurate measurement, the
measured channel's input should be AC grounded through a
1 ",F capacitor.
CLICKS AND POPS
So, why is that output buffer needed anyway? There are
three answers to this question, all of which are important
from a system point of view.
The first reason to utilize a buffer/amplifier at the output of a
",Pot is to ensure that there are no audible clicks or pops
due to attenuation step changes in the device. If an onboard bipolar op amp had been used for the output stage,
its requirement of a finite amount of DC bias current for
operation would cause a DC voltage "pop" when the output
impedance of the ",Pot changes. Again, this phenomenon is
due to the fact that the output impedance of the ",Pot is
changing with step changes and a bipolar amplifier requires
a finite amount of DC bias current for its operation. As the
impedance changes, so does the DC bias current and thus
there is a DC voltage "pop".
Secondly, the ",Pot has no drive capability, so any desired
gain needs to be accomplished through a buffer/non-inverting amplifer.

LM1973
Ul

COPS
DATA LINE
11
!,CONTROLLER
LOAD/SHIFT LINE 10

TLlH/11958-13

FIGURE 11. Digitally-Controlled
Logarithmic Gain Amplifier Circuit

LM 1973
U2

LM1973
U3

12-11

12-11

,'0

r'O

I
1 !,POT IN CHAIN
REQUIRES 16-BIT
DATA STREAM

2 !,POTS IN CHAIN
REQUIRE 32-BIT
DATA STREAM

12~

3 !,POTS IN CHAIN
REQUIRE 48-BIT
DATA STREAM

FIGURE 10. n-",Pot Dalsy-Chalned Circuit

1-219

•

LM1973
Un

11

10

12

RT
2k
n !,POTS IN CHAIN
REQUIRE 16n-BIT
DATA STREAM
TLlH/I1958-12

~~

tfI

Na, t ion. a I S e m i con due tor

LMC835 Digital Controlled Graphic Equalizer
General Description

Features

The LMC835 is a monolithic, digit.lly-controlled graphic
equalizer CMOS LSI for Hi-Fi audio. The LMC835 consist.s
of a Logic section and a Signal Path section made of analog
switches and thin-Him silicon:chromium resistor networks.
The LMC835 is used with external resonator circuits to
make a stereo equalizer wilh seven bands, ± 12 dB or ± 6
dB gain range and 25 steps each. Only three digital inputs
are needed to controi the equalization. Tile LMC83fj makes
it easy to build a p.P-controlied equalizer.
The signal path is designed for very. low noise and distor-·
tion, resulting in very high performance, compatible with
PCM audio.

•
•
•
•
•
•

No volume controls required
Three-wire interface
14 bands, 25 steps each
±12 dB or ±6 dB gain ranges
Low noise and distortion
TTL, CMOS logiC compatible

Applications
•
•
•
•
•

Hi-Fi equalizer
Receiver
Car stereo
Musical instrument
Tape equalization

• Mixer
• Volume controller'

Connection Diagrams
Dual-liI-L1ne Package

Molded Chip carrier Package

21 A.GND
21

AIM.

AIMI

AiMI

26

AIM3

25 24 23 22 21 20 19
AINI

"N6

26

18

Le1.

27

17

VDD
DATA

AnI.

AIM7

"N5

LCl

LCI

A.GND

LC2

Lca

. "N 1
"N2

LC3

LC1D

LC4

LCl1

LC5

LC12

LCI

LCla

LC7

LC14

V"

'iuD

CLOCK
D.GND

Vss

TLlH/6753-26

Top View

DATA

UNO
CLOCK.

STROBE

Order Number LMC835V
See NS Package V28A

14
TLlH/6753-1

Top View
Order Number LMC835N
See NS Package N28B

1-220

m

DO
01
02

8-BIT
03
SHIFT
REGISTER F,D::4-+-+-++...._ .....

0'

n

4·TO·16 DECODER

LATCH

~

I

C

i'

CO

DATA

Dl

17
-.oV+

3

.....
AIN40

,

•

RdC
7.3k
3
AIII3o--

-~

A,.,

-Ai1

AAM~M~~M~~AAAA~~

!; h II !! ;

2

0--;

II II
II

Rd2
7.3k

II II

I

A,., 0 •
Rib ~

~ RdC

Uk!

!

i£

3.4k~6

OR

Sb
RbC

Rbb

3.4k

'IWV..

R2C
t--+-+-+-+++-HI:,.....-o-_;:=

~_.......:::RI?IoC~
-o--_---.:.PO""\M,..

+-H-~""-O.J!N1r-1 R5lI55k

II
II .1
II II
II ,1
.1

1a"'O~I\/\r-tR4b2Ik

o---J\IIIIw,.:::::
o----IV~Rlb.k

Aut, o-.....-+-t

+---o....-o---...Jy~ROb3k

RbO
7.3k
26

AutsO---<

L

Rbi

A'N5~

.; h

I.I'..II ;:
"..1 II
I..

dB

:t12dB

Uk
25

1111

BOOST

2B

A.DNO

II II
II
II II
II II
I;
II II
II
II II
II I
II II
II II
II II
.. II

II

~_~

II

U

I' II
II II
II
II II
II
II ..
II II
II II
I II
II II
II II
II II
I' II

h

iI II !I !I

II
I.
II
II

II
II
;.

II

;1 '1
II
P II

II

.'
I'

'I
I,

;111
II '1

II

n
I: I;
II II '.

II

.1. II"

I'I
•
I
II
II
I
II

II
II

I
.1
.1
.,
II
..

II
II
II
I.
"

II
'1
I
.'

'I
'1
I'
I.:
,I II
•

'1

I
II

_

~~~~~~~

7.3k

,

I'

16

I'

16

16

16

I'

011

024

023

022

021

028

01.

01.

LC7

LCI

,

I
LCI

LC2

07
LC3

01
LC4

09
LCI

OlD
LCI

LCI

LCI.

Lcn

LC12

LC13

LC14
TUH/6753-2

SE8:>."

II

Absolute Maximum Ratings

Operating Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

SuppIY,(oltage, Voo-Vss
Digital Ground (Pin 13)
Digital Input (Pins 14, 15, 16)

Supply Voltage, Voo-Vss

18V

Allowable Input Vo1.l!lge (Note 1)

Analog Input (Pins 1, 2, 3, 4, 25, 26, 27)
(Note 1)

Vss-0.3V

toVoo+0.3Y
Storage Temperature, Tstg
- 6O"C to + 150"C
Lead Temperature (SOldering, 10 sec), N Pkg
+ 260"C '
Lead Temperature, Y Pkg
Vapor Ph~ (60 sec)
Infrared (1Ssecl

5Vt016V
Vssto Voo
VsstoVoo
Vssto Voo
-4O"Cto +85°6

Operating Temperature, Topr

+215°C
+ 220"C

Electrical Characteristics (Note 2) Voo= 7.5V, Vss = -7.5V, A.GND;" OV
LOGIC SECTION
Symbol

Test Conditions

Parameter

Typ

" Tested
Limit
(Note 3)

0.Q1
0.Q1
1.3
0.9,

0.5
0.5
5
5

0.5
,0.5
5
5

Design
' Umlt
(Note 4)

Unit'
(Limit)

IOOL
ISSL
IOOH
ISSH

Supply Current

Pins 14,15, 16areOV
Pins 14, 15, 1,6,are OV
Pins 14,15,16 are 5V
Pins 14, 15, 16 are 5V

mA(Max)
mA(Max)
mA(Max)
mA(Max)

VIH

High-Level Input Voltage

@Pins14, 15, 16

1.8

2.3

2;5

V (Min)

VIL

Low.Levellnput'Voltage

@Pins14,15', 16

0.9

0.6

0.4

V (Max)

fo

Clock Frequency

@Pin14

2000

500

500

kHz (Max)

tw'IS'mT

Width of S'fB Input

See Figure 1

0.25

1

1

",s(Min)

lsetup

Data Setup Time

See Figure '1

0.25

1

1

p.S(Min)

thold

Data Hold Time

See Figure 1

0.25

1

1

",s(Min)

tcs

Delay from Rising Edge of ~
to S'i'lJ

See Figure 1

0.25

1

1

",s(Min)

liN

Input Curient

@Pins14, 15, 16 OV1"""'=
Va- :t:7.IV. T._UoC:::

....Z

II
FtIEIIUEIICY (Hz)

0.11

-II -U D 25 II 75 lDO 125
TEMPlUTUIE (OC)

I. D~~ §==tlsti·lJill~ll-LHz~AII

•

~ '.n

D••

1
.0..

"-I:#mR=FtII~!!lJ

--FLAT

D.17

~

0•11

=

-

D."

r.;-~;-:=";","-':::"IIIIFI'_

~ "'Z

o.n

0.1

I

1

D 1 Z I 4 5 • 7 • • lD
SUPPLY VOLTUE (:t: V)

II; '.11
II.•

!

3

--

•

•

~

1.114

4

I-I

I•

/'

1.15

! I.DI
II 1.12
! 1.11
II
1
I ....

I ·

,
I

FLAT ~ - THD 1%- r- -

Nominal Resistor
vs Temperature

Ys-:t:7."

o

i

I

Ro-IIIO
:t:1ZdIRANIIE

-1

-2

i

-3
-4

-5

-I

4
3
2
1

o

11

101
II
1.
FIIElIUEIICY 'HZ)

lG111

_

-

Idl,_

I
Idl
..I
3d.

U.
Idl
FLAT

-50 -25 D 25 II 75 III 125
Tl!MPERATURE ,OC)
TL/H/6753-10

1-227

~

Typical Applications

';..I

27k

Uk

1-------::::==::;:---.. .

0 You,"

H,,""",,--+ + 15VOCIN

+75V
27k

P- • • - • • - •• - • • - • • - •• -~
I
II
..
"
"
II
II
I
I Zl II Z2 II Z3 II Z4 " Z5 II Z6 " Z7 I
•
"
"
II
"
II
"
I

1..D.GNO
__ ..1
LMC835

I

'"
..
'II , "
..
II
•
I 11" 1211 Z3 U 24 II Z5" 16" 17 I

47. IL_JL_jL_JL_JL_JL~JL_j
"
"
'..
"
"
"
I

17k

H ....- - .
27k

~"""'...-:-I~

,"15V

>-""-'M~

-15VDCIN

.....------------..;....;....,0 VOUTA

-15V,
Tl/H/67S3-11

FIGURE 7. Stereo 7-,Band Equalizer

TABLE I: Tuned Circuit Elements
PIN "LC"

00=3.5, Ql2dB= 1.05
Z1

fo (Hz)

Z1
Z2
Z3
Z4
Z5
Z6
Z7

63
160
400
1k
2,5~

6.3k
16k

Co(F)

CL(F)

, ,0.1,...
6'.033,...
0.015,...
0.0068",
0. 022"" 0,0033,...
0.01.,...
,0.0015,...
0,0047,...
680p
1,...
0.47,...
0.15,...
0.068,...

RL(O)

Ro(O)

100k
100k
100k
82k
82k
62k
47k

680
680
680
680
680
680
680

"

PIN 2, 3 OR 26

r~d--'
':CD~,IODk
I
c
'
I

Ro

L,

I RL,
I'

+
-

'
LM833

I

',I
,I

Lo=CL RL Ro '

10=_1271",/lQ'CO

Oo=~Co~ ,
Q12dB=flo~90 '

L.::. .. _ _ _ :"

(159011-55k#16k#11k#8k#3 III!I

, Tl./H/6753-12

FIGURE 8. Tuned Pi'rcult for St,reo '
7-Band Equalizer (Figure 1)

1-228

Typical Applications (Continued)
Performance Characteristics (Circuit of Figure 1)
LMC835 Gain vs Frequency
LMC835 Gain vs Frequency
@ ± 12 dB Range
@ ± 12 dB Range
(1 kHz Boost or Cut)
(All Boost or Cut)

i

16

16~

12

12Sl1=n

i

4

i

4

i... -40

0
"'-4

-I

-I

-12HHIfj.~

-12

-16
10

100

FREOUENCY (Hz,

lK

10K

lOOK

, FREQUENCY (~z'

L~C835 Gain vsl"requency

LMC835 Gain vs Frequency
@ ±6.dB Range
.
(1 kHz Boost or Cut)

±6dBRange
(All Boost or Cut)
@

I

!i_2:

-4."

!

'"'
!-2
-4
-6

-6
-8

-8
10

100'

lK

10K

lOOK

lQ

180

lK

10K

lOOK

F~EQUENCY (Hz,

FREQuENCY (Hz,

TUH/6753-13

+·15V

470
>"'~W_-------------oVOUT

27k

-=

10k

21

27.

A,GNO Allis

23

24
LCI

LCI

22
LCID

21

20

LCll LC12

,. ,.

III

+7,5V

lOOk

DATA
STROH
17

LC13 LC14

Vat

Lc&

Vas

.i

LMCI35
LCI

LC2

LC3

LC4

LCI

I

I

10

LC7
11

12

---+

UNO
-7.5V

..

111

......

..-..-.

1111·

I II II 1211 Z3 .. 14 II 15 .. 1611 Z71
•
••
II
II
..
..
II
I
~-~.-~.-~.-

FIGURE 9. 12-Band Equalizer
1-229

TUH/6753-14

U)

r---------------------------------------------------------------------------------~

H

Typical Applications (Continued)

~

TABL£li. Tuned Circuit Elements
PIN "Le"

00=4.7, Q'2dB= 1.4
fo (Hz}
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12

16
31.5
63
125
250 '
500
1k
2k
4k
8k
16k
32k

Co(F)

CL(F)

RL (0)

Ro(O)

3.3,...
15,...

0.47,...
0.22,...

1,...'

0.1p.

100k
110k
100k
91k
82k
100k
82k
91k
110k
82k
62k
68k

680
680
680
680
680
680
680
680
680
680
680
510

0.39,...
;0.068,...
0.22,...· .' 0.033,...
0.1,..
0.015,...
0,01,...
0.047,...
. 0.022p.
0.0047,...
0.01,...
0.0022,...
0.0068,...
0.001,...
.. 680p
0.Q015,...
4Z0p

o.boaa,...

PIN 26

r~-,~'I

leo

lOOk

.'

I

l'

I~

I

I RL
1
I
_ _ ·__ .JI ;.
L~

(15901l-55k#16k#11k#8k#3 kll)

TLlH/6753-15

FIGURE 10. Tuned Circuit for
12-Band Equalizer (Figure 9)

, r.

Pertormance Characteristics (Circuit of Figure 9)
. 12 Band Equalizer Application
LMC835. Galil vs Frequency
@±6dBRange '
(A" Boost .or CIlt)

LMC835 1a Band' E.Q. Application
Gam ". Fr.quency
@ ±12dB~ange
(1 kHz 8008t Of Cut)
I• • •
'
12

ii
~

I

D

!

4

z

D

i

-2

-4

-4

-I

-6

-12

-I.

lD

100

lK

18K

lD

10D

lOOK

lK

10K

lDOK

FREQUENCY (Hz)

FRE~UENCY (Hz)

I.

12 Band Equalizer App"cation
LMC835 Gain vs Frequency
@ ± 12 dB Range
(A" Boost or cUt)
"~';"I ,a.: •• h:: ~';::4,':'I ... ~l11l1l1i

LMC835 12 Band E.Q. Application
Gain vs Frequency
@ ±6dBRange
(1 kHz Boost or Cut)

• •IIIIII. . . 'IIII·
,'.""'IIIIUllli"
.. , ,'jl.'." jl" ,,'fjl'-j,r
" .... '".1\ 1IIIi

•

8. .

j'

~'.!i'," .'.~I

.,'~II',I •• :.~

II

·t It U III,' tl',1111
'A'r","I',.·,~llh,'

'.I·J~',I, '. "".1,' ~"'.""I" """:1.'1

!i : ..... "..

'AI',t,'

,,"~

.',.~,"._

,.

•• ;'

,j

I:' . "~":\, 'i
-' ... .. ,

.~ ,."~,"

,''''

r

~_.,

,

,

!

.... _ . . . '

~.~

i

,,"'1 .. ~'" !'.... 1~,· .I,'" '".",':, . . ,.f,fll
-4 ~,,",
'I' •. '" ',','.4 IL"I,' I~l"·.il Ii!;

-I

";'1

.." II'.' ".

- , - " --"

IIl'II", 'I ,I ",",'1 1",1
.".o'III.Uj',11

... jill
-12~ .I;'..:..
111" •• ',111,
'10'1-;;.11111
~f

100

lK

10K

-4gllll~

-6

-1&~
'lD

-2

-8

lOOK

10

FREQUENCY (Hz)

100

lK

10K

lOOK

FREQUENCY (Hz)
TLlH/6753-16

1·230

~--------------------------------------------------------------------~r

I:

Typical Applications (Continued)
PIN

"LC"

PIN 2, 3 OR 26

rHd--'
Ico
I

La = CL. Rlo Ro

I~o I

I
I
I

RL

-

00

=

.fCORci2
RoOo

I

+

CI'I

1
Fo=~

100k

ICL

a

Q12dB

= Ro + 15'C

I
I
I

LM833

v+

L.l ____ J

(159D!1-55k#16k#llk#8kQ3 kill
TL/H/6753-25

v••

'>-41.......WIr-....:..j /----------00 """TO
ll111k

,-,,-,,-,,-,r-,,-,r-'

11111111111111
1 ZI II Z2 II Z3 II Z4 .. Z5 .. Z& I I Z7 I

Vo.

•

..

••

II

II

II

II

I

.-----+ Voo IV 70 15V
DATA

STROlE

~~~~~~~~~~~~~~~~

11111

"

CLOCK

I'f

UNO

lOOk

'>_.......\M~

t---~------ ...--oVoUT

7.3k

~JN.--'

,I

12 dB

11.8da

r-L--,;----....o;:--·
1---.--.-- --+..,.....T-

I

_I~_J
RLEAK

odB
..,.110

10"'0

TLlH/6753-21

TL/H/6753-22

FIGURE 15. Effect of RLEAK

REDUCING EXTERNAL COMPONENTS
The typical application shown in Figure 7 is switching noise
free. The DC-coupled circuit in Figure 16 is also switching
noise free, except at 12 dB/6 dB switch turn ON/OFF. This
switching noise is caused by the Ibias and Vollse! of the op

amps. Selecting a low Iblas and Vollset op amp can minimize
the switching noise due to the 12 dB/6 dB switch. The DCcoupled application can also eliminate the RF= 100k resistors with only a 0.5 dB gain error at 12 dB boost or cut.

ACCOUPLING

DC COUPLING

lOOk

·".r
LMC835

LMC835

TL/H/6753-24
TLlH/6753~23

FIGURE 16. Reducing External Components .

1-234

,-------------------------------------------------------------------------, r

Ii:

o....

I!J1National Semiconductor

~
N

LMC1982
Digitally-Controlled Stereo Tone
and Volume Circuit with Two Selectable Stereo Inputs
General Description
The LMC1982 is a monolithic integrated circuit that provides
volume, balance, tone (bass and treble), enhanced stereo,
and loudness controls and selection between two pairs of
stereo inputs. These functions are digitally controlled
through a three-wire communication interface. There are
two digital inputs for easy interface to other audio peripherals such as stereo deCoders. The LMC1982 is designed for
line level input signals (300 mV-2V) and has a maximum
gain of -0.5 dB. Volume is set at minimum and tone controls are flat when supply voltage is first applied.
Low noise and distortion result from using analog switches
and poly-silicon resistor networks in the signal path.
Additional tone control can be achieved using the LMC835
stereo 7-band graphic equalizer connected to the
LMC1982's SELECT OUT/SELECT IN external processor
loop.
.

Features
• Low noise and distortion
• Two pairs of stereo inputs

•
•
•
•
•
•
•
•
•
•
•

Enhanced stereo function
Loudness compensation
40 position 2 dB/step volume attenuator plus mute
Independent left and right volume controls
Low noise-suitable for use with DNRcII and Dolbycll
noise reduction
External processor loop
Signal handling suitable for compact discs
Pop-free switching
Serially programmable: INTERMETAL bus (1M) interface
6V 10 12V single supply operation
28 Pin DIP or PLCC package

Applications
•
•
•
•
•

Stereo television
Music reproduction systems
Sound reinforcement systems
Electronic music (MIDI)
Personal computer audio control

Block and Connection Diagrams
23
22
21
20
R SELECT OUT R SELECT IN R TONE IN R ·TONE OUT

19
R OP AMP OUT

~:o--+
G~5O--+
25
R.INPUTI
4
L.INPUTI
24
R. INPUT2
5
L.INPUT2

INPUT
AND
MODE
SELECT

18
R LOUDNESS

l

17
R ENHANCE ST.
6.51<4

•

I.Sk4

*Loudn...

Y+/2

16
RIGHT
OUT

,Oft
1501<4

LOGIC
AND·
CONTROL

l.5k4
50k4
14
BYPASS
501<4

13
LEFT
OUT

150k4

F

Y+/2

6
7
L SELECT OUT L SELECT IN

8
L TONE IN

9
L TONE OUT

10
LOP AMP OUT

11
L LOUDNESS

28
DATA
1
CLK
27
10
2
DIGITAL INPUT 1
3
DIGITAL INPUT 2

gEnhanCtd storeo

12
L ENHANCE ST.
TLlH/ll028-1

1-235

Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are requlr8d,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
SuppIyVoltage(V+ - GNO)

Lead Temperature
I
N Package, (Soldering, 10 Seconds)
V Package, (Vapor Phase, 60 Seconds)
Infrared, (15 Seconds)
.' ' •.

15V

GND - 0.2V to V+ + 0.2V
Voltage at any Pin
Input Current at any Pin (Note 3)
;·5mA
Packa!!e Input Current (Note 3)
",1,

Power Dissipation (NJie'4)

20mA
sbo~w

Junction Temperature

. -65°l!l#) -b150"C

Storage Temperature

ESO S,usceptabilily iNote 5)

+ 260"C
.215°C
22O"C

,.

2kV

,.' OpEt,rating. R__tings (Notes'1' and 2)"
Temperature Range
LMC1982CIN, LM91982CIY,
Supply Voltage Range (V+ - V-)

+ 125°C

I,"

•

TMIN S; TA S; TMAX
-40"C S; TA S; +85°C
6\1 to 12V

,

,

,.

Electrical.Characteristic$ ,The'fq!low\ng

specifications apply,for V+ = 9V,' fiN ,= 1 kHz, input signal
,(300 mY) applied to I~PUT 1, volume. = 0 dBJ. bass = 0 dB, treble ~ 0 dB, enhanced stereo is off, and. loudness is off unless
'
.
.
"
.
,
.
otherwiSe specified. All limits apply for TA = I j ~ + 25°C.
.. i

Symbol

Parameter

IS

Supply Curre!lt

Y,N

Input Voltage

THD

Typical ,,·'Umlt
(Note 6)·· (Note i)'

C.ondltJc;ms

.'.

,.

..
Clipping Level (1,.0% THD),
Select Out (Pins 6, 23)'-'

Totai Harmonic Distortion

';.'

15

2.0

2.3

.mA(max)
Vrms(min)

"

. Left and Right channels;
Output Pins'13,16
.
.!
Y,N ",,; 0.3 Vrms;
. f'N";"'100 'Ht, 1 kHz,10 kHz
vi~'=
Vms';
fiN
100Hz; 1 kHz
",N
2.0 Vrms;
fiN
10 kHz
Y,N = 0,5 Vrrns; Bass and Treble
Tone Controls Set at M8)dmuRl
Y,N
0.3 Vrms; Volume
Attenuator at - 20 dB, Bass and Treble
., '. TOrle Controls Set at Maximum

".

.

"

'.

I

0.008

0.1

% (max)

1.0

% (max)

0.5

1.0

. % (max)

0.07

0.5

% (max)

0.06

0.15

% (max)

2.0

4.0

mV(max)

11!

20

mV(max)

,150
26

200
40

o (max)
o (max)

,1)0

72
35

kO(max)
kO(min)

0.5

1.5

dB (max)

80

78
82

dB (min)
dB (max)

2.0
=
=
=

',:

25

Unit
(Umit)

0.4
,",1

=

:,!

.'

=

DC Shifts

Y,N
0.3 Vrms; Between Any
Two Adjacent Control Settings
Y,N
0.3 Vrms:
All Mode and Input Positions

=

.
ROUT

AC Output Impedance "

Pins 6, 23, (4700 to Grou~d at input)
Pins 13,16

R'N

AC Inpui'lmpedance

Pins 4, 5, 24, 25

.

:,?;'.,'

"
.~~

Volume. AttElnuator
. . Range

,.. Pins 13,16; Volume
AttenuatiOn at 010001 OXXxOOOOOO (0 dB)
010001 OXXX1 01 XXX (60 dB);
(Relative to A~nuation at
the 0 dB Setting)

,

"

,.

Volume Step Size ...

"'!"

'"

All Volu~e Attenuation Settings '
from 01 0001 OXXX1(>1 XXX (Sb dB) to
, 01 0001 OXXXOOOOOO:(O dB) (Note 9)

Chann8i-to:Channei Volume
Tracking Error .,'

AI~Volume Atterija,tionSettings .,
from 01 OQ01 0XXX1 01 XXX (80 dB)
to 010001 OXXXOOOOOO (Q dB)

Mute Attenuation

Y,N

.,

= 1.0 Vrms
, .. 1-236

'~'

2.0

.

'. 1.5,
2.5

dB (min)
dB (min)

±0.1

±1.5

dB (min)

105

86

dB (max)

...

Electrical Characteristics The following specifications apply for V+ = 9V, fiN ;= 1 kHz, input signal (300 mV)
applied to INPUT 1, volume = 0 dB, bass = 0 dB, treble = 0 dB, enhanced stereo is off, and loudness is off unless otherwise
specified. All limits apply for TA = TJ = + 25°C. (Continued)
Symbol

' Conditions

Parameter

Typical
(NoteS)

LImit
(Note 7)

Unit
(Limit)

Bass Gain Range

fiN = 100 Hz, Pins 13, 16

±12

±10.0
±14.0

dB (min)
dB (max)

Bass Tracking Error

fiN = 100 Hz, Pins 13; 16

±0.1

±1.5

dB (max)

Bass Step Size

fiN = 100 Hz, Pins 13,16
(Relative to Previous Level)

2.0

1.5
2.5

dB (min)
dB (max)

Treble Gain Range

fiN = 10 kHz, Pins 13, 16

±12

·±10.0
±14.0

dB (min)
dB (max)

Treble Tracking Error

fiN = 10 kHz, Pins 13,16

±0.1

±1.5

dB (max)

Treble Step Size

fiN = 10 kHz, Pins 13, 16
(Relative to Previous Level)

2.0

1.5
2.5

dB (min)
dB (max)

E:nhanced Stereo Cross Coupling

(Note 10)

-4.4

-2.5
-6.9

dB (min)
dB (max)

Frequency Response

VIN Applied to Input 1 and Input 2;
fiN = 20 Hz - 20 kHz
(Relative to .Signal Amplitude at 1 kHz)

±0.1

±f.O·

dB (max)

11.5

13.5
9.5
8.5
4.5

dB (max)
dB (min)
dB (max)
dB (min)

Loudness

Volume Attenuator = 40 dB, Loudness
on (See Figure 5)
Gain at 100 Hz (Referenced
to Gain at 1 kHz)
Gain at 10kHz (Referenced
to Gain at 1 kHz)

6.5

Signal-ta-Noise Ratio

VIN = 1.0 Vrms, A Weighted,
Measured at 1 kHz, RS = 4700

95

90

Channel Balance

All Volume Settings

0.2'

1.0

dB (max)

Channel Separation

Input Pins 4, 25: Output Pins 13, 16;
VIN = 1.0 Vrms (Note 8)
4700 to AC Ground on Unused Input

80

60

dB (min)

95

60

dB (min)

32

28

dB (min)

Input-Input Isolation

dB (min)

PSSR

Power Supply Rejection Ratio

fClK

Clock Frequency

5.0

1.0

MHz (max)

VIN(l)

Logic'''1'' Input Voltage

Pins 1, 27, 28 (1M Bus)
Pins2,3

1.3
2.9

2.0
5.5

V (min)
V (min)

VIN(O)

Logic "0" Input Voltage

Pins 1,27,28 (1M Bus)
Pins 2,3

0.4
1.2

0.8
3.5

V (max)
V (max)

V+ = 9 Voc;200 mVtrns; 100Hz
Sinewave Applied to Pin 26

Pin 28 (1M Bus)
2.0
V (min)
Logic "1" OUtput Voltage
VOUTCll
0.8
V (max)
Pin 28 (1M Bus)
Logic "0" Output Voltage
0.4
VOUTIOI
Note 1: Absolu1e Maximum !'Iatings ind~ limits beyond which damage to lf1e deiVce may occur. Operating Ratings Indicate conditions fdr which the device Is
functional, but do not guarantee. specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specillcetions apply only for ths test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are specified with respect to ground.
Note 3: When the inpUt wltege (VII~) at any pin exceeds the power supply VOltages (VIN < V- or VIN > V+) the absolutevalUEI of the c..rent at that pin should be
limited to 5 mA or less. The 20 mA paci\age input current limits the number .of pins thst can exceed the power supply witeges with 5 mA current limtt to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAXo 8JA, and the ambient temperature TA. The maximum
allowable power dissipation is Po = (TJMAX - TAJ/9JA or the number giVen In the Absolute Maximum Ratings, whicheve[ Is lower. For ths LMCl982CIN, TJMAX =
+ 125"C, and the typical iunction-to-ambienl thermal resistance, .when board mounted, Is 67"CIW.
Note 5: Human body model; 100 pF discharged through a 1',5 kG r..slstOr.
'
;1'
Note 6: Typicels are at TJ ~ 25'C and r'epresent the mo~ likely parametl1c nmm.
';.:.
Note 7: Umits are guaranteed to National's AOOL (Average Outgoing Ouafrty Levell.
Note 8: The Input-Input Isolation is tested by drtving one Input and measurtng the ~ when the undriven input are' sel8cted.
Note ".The Volume Step Size is defined 'as the change in _nuaticn between any1WO adjacent wlume attenuation'S9ttJniIs. The nolnioai Volume Step Size is
2da
.
,
I',.

+

Note 10: Enhanced Stereo crOss Coupiing is a measure of the ratio between ths undriven right channel output signal and the drtven left channel ouIputsignai. It is
measured by driving the left inputs with a 300 mV""" signal while the right inputs are grounded,
"
'

1-237

..

II

Typical Performance Characteristics
Supply Current
vs SUj)ply Voltage
3D

1.=25"<:

:1

i

Output Plnl: 13. 1a
RL =
tHD=IlI>
~~....ttenu.t.r~

/V

15

~

Y+=9V

/

20

'V

10

0.6

'"

~
,, I

~_+_

t--r-

...

D.02

"~

~A,:~;c

I

-70
2
:!.

i

\

~

~
o

IDO

10

AC LOAD IMPEDANCE (kll)

z

~

"

lil

i

o.s

'""

'~

!11

"
i!'"

'"
!l!

JJ

=

-'tOUT 30 mVrml

i!
e

r/

Vour =100mVrJII1

Vour=300mVI'IIII

0.0
0.0

0.5

1.0

L5

2.5

2.0'

e

D.D5

Tone Control Response
with Equal Bass and,
Treble,Control Settings

111111111 1,1 111111 11111

1.=25"<:
-30<11

Input Pins: •• 25
Output Pin.: 13, 16
Tone nat

~:;.~~, pinllj~!lIt611 i 111m 11111

RIGH~II~HANNEL

Mute Activated

.."j::fff1

D.D4

/

VIN = 1Vrma

D.D3
D.D2
D.DI
D.DD

10

-

/

LEFI
CHANNEL

I
-12OdB

"

'/,
...".. VIM =0.3VnM

100

Ik

10k

'"

-135dB
10

1DDk

1111111
111111
1111111
'1'

100'

FREQUENCY (Hz)

INPUI VOLTAGE (V,m.)

!

OdB

0.06

lOOk

10k

Mute Gain
vs Frequency

\='25"<:
V =BV

g om

Ik

100

FREQUENCY (Hz)

D.D8

.I.

Input PIn.: ".25
Output Pin.: 13.16

~

10

THD vs Frequency

In'

a

Rl'ght

-110

80

VOLUME ATYEHUAnON (dBj'

THDvsVIN
(~OUT Constant)
TA=25~
v·+ = 9V

80

20

ovtput- (Left chann" driven)
L,ft. 0utf»iIt-- (fUght channel driYtn)

-105

3~~~~--L-~~~~

'Z

r----r-;;-::-=:---r-~.,

z

Ton. FI.t

0.2 ' \

1.0

100

10

Channel Separation
vs Frequency

0.4 _\

g

'\

AC LOAD IMPEDANCi:(~lI)

k---+-+-:-I Output PIns: 13.16

Volume Attenuation =OdB

Ton. Flat

Tone FI.t

O.DO

,8101214,16

-+--+-1

VOUT = IV""
O.lp.1 PI." 6. 23. ~ ~IJ,

Pin,',

oulp'l
13.16
Volume Attenuation =0 dB

e

IA = 25"<:
f-+-+-i,v'+ =BV
Input Pins: Grounded

I I II
I I II

rm•

\

D.01

CCIR Output Noise
vs VolUme Setting

03r--r-r.~~~-r~rnTm

OUT

r--

SUPPLY VOLTAGE ,(V)

THDvs
I,.oad Impedance

v'
= 9V
V
=1V

-

""z

J

SUPPLY VQLTAGE (V)

-f-

i

D.03

;!i

,2

12

10

4

0:D4 ; -

ttl1Hl
II II

TA =25OC

~

Ii

/

~

o

O~~~~--L-~~~~

g
~

/

/

I

-

g

Tone rlet

V

UI

0.D5

1.=25"<:

V

Y+=9V

26

THDvs
LOad Impedance

Outpu,t Voltage
vs Supply Voltage

Ik

lbic

lOOk

FREQUENCY (Hz)

.Loudness Response
vs' Frequency

Select Input Impedance
,vs Frequency

I

, 1,=25"<:
, 'V'=BV
Input~: pins? 22

I

M,AX. CUT

.'DOIe "'F=-LA"'T";;;;~:--j--+--I

i!!

.........

100

lie

10k

FREQUENCY (Hz)

lDOIe

100

11<

IDk

FREQUENCY (Hz)

lOOk

Ik ~_-'-~_..L--_....;:.AX::::.;';:OO::STCJ
10
100
Ik
10k
IDOk
FREQUENCY (Hz)
Tl/H/lI028-3

1-238

Connection Diagram

~

\,.../
CLOCK- 1

28

.-

27 ~ID

DIGITAL INPUT 1- 2
DIGITAL INPUT2 -

~DATA

!5

26~V+

3

N
~

~

:!! :!!

LEfT INPUT 1- 4

25 ~ RIGHT INPUT 1
24 ~RIGHT INPUT 2

0

~

:!!

!5

~

~ s.

..
0

id t; :!! ... '"
t! ~ ~ g ~
0

LEfT INPUT 2 -

5

LEfT SELECT OUTPUT -

6

LEFT SELECT INPUT -

7

22 ~RIGHT SELECT INPUT

18

LEFT TONE INPUT -

8

21 ~RIGHT TONE INPUT

17 - RIGHT ENHANCED STEREO

LEfT TONE OUTPUT -

9

20 ~RIGHT TONE OUTPUT

23 ~RIGHT SELECT OUTPUT
LMC1982

LEfT OP AMP OUTPUT- 10
LEfT LOUDNESS -

19i-RIGHT OP AMP OUTPUT

11

181-RIGHT LOUDNESS

LEfT ENHANCED STEREO- 12
LEfT OUTPUT- 13

17

~RIGHT

ENHANCED STEREO

16

~RIGHT

OUTPUT

DATA -

28

CLOCK -

1

RIGHT OUTPUT

15 - GROUND

DIGITAL INPUT 1 -

2

14

DIGITAL INPUT 2 -

3

13 - LEFT OUTPUT

LEFT INPUT 1 -

15~GROUND

BYPASS- 14

16
LMC1982

RIGHT LOUDNESS

4
'5

6

!

::::)

to-

12

A.

Q..

!:

:~ I-ti
~....I

Top View

-

Order Number LMC1982CIN
See NS Package Number N28B

8

..
;oJ :;:

:::l
A.

D.

Q..

!en

~ ~ ~

%
0
...

t:

""'!

t: ~ :I ....

LEfT ENHANCED STEREO

9 10 11

~ ~::J ~ ::J~ ::::»~

~ ~

TUH/ll028-2

7

BYPASS

wa..

~

2

r-

...:

.....

g
9

t:

""!

t: ~ .....
:I

§

TUH/ll028-12

Top View
Order Number LMC1982CIV

See NS Package Number V28A

Pin Description
CLK (1)

The INTERMETAL (1M) Bus clock is applied to the CLOCK pin. This input accepts
a TTL or CMOS level signal. The input is
used to clock the DATA signal. A data bit
must be valid on the rising clock edge.
DIGITAL INPUT Internally tied high to V+ through a 30 kO
1 & 2 (2, 3)
pull-up resistor, these inputs allow a peripheral device to place any single-bit, active
low digital information onto the 1M Bus. It is
then sent out to the controlling device
through the DATA pin. Examples of such
information could include indication of the
presence of a Second Audio Program
(SAP) or an FM stereo carrier.
INPUTS 1 & 2 These are the LMC1982's two stereo input
(4, 25; 5, 24)
pairs.
SELECT OUT The selected INPUT signal is available at
this output. This feature allows external sig(6,23)
nal processors such as noise reduction or
graphic equalizers to be used. This output
can typically sink 1 mA. These pins should.
be capacitively coupled to pins 7 and 22,
respectively, if no external processor is
used.
These are the· inputs that an external signal
SELECT IN
(7,22)
processor uses t9 return a. signal to the
LMC1982. These pins should be capacitively coupled to pins 6 and 23, respectively, if no external processor is used.
TONE IN
(8,21)

TONE OUT
(9,20)

Tone control amplifier output. See the Application Information section titled "Tone
Control Response".

OPAMP
OUT (10,19)

These outputs are used with external tone
control capaCitors. Internally, this output is
applied to the volume attenuators.

LOUDNESS
(11,18)

. The output signal on these pins is a voltage
taken from the volume attenuator's
-40 dB tap point. An external R-C network is connected to these pins.

ENHANCED
STEREO
(12,17)

An external R-C network is connected
across these pins. This provides left-right
channel cross-coupling and cancellation to
create an enhanced stereo channel separation effect.
The output Signal from these pins drives a
stereo power amplifier. The output can typically sink 1 mA.

MAIN
OUTPUT
(13,16)
BVPASS(14)

A 10 J.LF capacitor is connected between
this pin and ground to provide an AC
ground for the internal half-supply voltage
reference.
.

GROUND (15) This pin is connected to analog ground.
V+ (26)
This is the power supply connection. The
LMC1982 is operational with supply voltages from 6V to 12V. This pin should be
bypassed to ground through a 1.0 J.LF capacitor.

These are the inputs to the tone control
amplifier. See the Application Information
section titled "Tone Control Response".

1-239

•

~'r-------------------------------------------------------------------------------------~

!
~

Pin Description
10 (27)

(Continued)

"',,'

This is thE! IDENTITY digital input that, when
low, signals the LMC1982 to receive, from a
controlling d8vice, a 'device address (40H47H), present'on the DATA line.

,

.:1','

This is th~ serial" data input for communications sent by Ii coiltroller. The controller must
have open drain outputs used with external
pull-up resistors. The data rate has" a maximum"frequency of 1 Mliz. The LMC1982 requires ..lS bits of data to control or change a
function: the first 8 bits' select the LMC1982
and one of eight function.s. The, final eight bits
set the function to a desired value., The data
must tie valid on the rising edge of the CLOCK
input Signal.
'

TABLE I.'IM Bus Programming Codes tor LMC1982

'

', ..
Function,

, Address

Data

Function
Selected

Input Select + Mute

XXXXXXOO
XXXXXX01
XXXXXX10
XXXXXX11

INPUTt
INPUT2
N/A
MUTE

Loudness, Enhanced Stereo

XXXXXXOO

LOUdneSs OFF
Enhanced Stereo OFF
Loudness ON
Enhanced Stereo OFF
Loudness OFF
Enhanced Stereo ON
Loudness ON
Enhanced Stereo ON

(A7!AO)

",

01000000' "

01000001

DATA (28)

XXXXXX01
XXXXXX10

'r,.1.

XXXXXX11
"

01000010

Bass

XXXXOooO
' XXXX0011
XXXX0110
XXXXl001
XXXX11XX

-12dB
·-SdB
FLAT
+SdB
+12 dB

Trebie

, XXxxooqo

-1,2 dB
...,SdB
.FLAT
' +SdB,
+12dB

"

,,'

Q10oo011

xxx><0011

l.

XXXX0110
XXXXloo1
XXXX11XX

,i

" Left Volume

01000100
.

~

,

,1

"

01000101

Right Volume

,
" ,i

01000110

Mode Select

,
,.",

01000111
','

R~d

Digital Input 1
or
Digital Input 2
on 1M Bus

XXOOOOOO
XX010100
',', .
XX1 01 XXX
XX1JXXXX

'

'

"

OdS
-40 dEl

~8ddB

-80 dB

i XXOOOOOO

XX010100
XX101XXX
,XX11,XXXX

OdB
-40 dB ,
-80 dEI'
-'I!OdB

XXXXX100
XXXXX101
, XXXXX11X

Left Mono
Stereo
Right Mono

,

XXXXXXb1Do '

00 ::=Digitallriput 1
01 ,,; bigitallnput 2

"
"

..

General Information
the stereo balance function. F1!Jure 1 shows the connection
diagram of a typical lMC1982 application.

The lMC1982 is a .CMOS/bipolar building block intended
for high fidelity audio signal processing. It is designed for
line level inputs signals (300 mV - 2V) and has a maximum
gain of -0.5 dB. While the lMC1982 is manufactured with
CMOS processing, NPN transistors are used to build low
noise op amps. The combination of CMOS ·switches, bipolar
op amps, and poly-silicon resistors make it possible to
achieve an order of magnitude quality improvement over
other bipolar circuits that use analog multipliers to accomplish gain adjustment. Internal circuits set the volume to
minimum, tone controls to flat, the mute to on, and all other
functions off when power is first applied. Individual left and
right volume controls are software programmed to achieve

The lMC1982 has internal decoding logic that allows a microprocessor (p.P) or microcontroller (p.C) to communicate
directly to the audio control circuitry through an INTERMETAl (1M) Bus interface. This three-wire interface consists of a
bi-directional DATA line, a Clock (ClK) input line, and an
Identity (10) line. Address and function selection data
(8 bits) are serially shifted from the controller to the
lMC1982. This is followed by 8 bits of function value data.
Data present in the internal shift register is latched and the
instruction is executed.

DIGITAL DIGITAL
INPUT 2 INPUT 1 ClK DATA

ID

2

0.47 JLF
0.0082 JLF

lMC1982

240 pF .;;..::;:..::.:=---_~

I

240 pF

12

0.22 JL F

1.5kD.

+

17

13

16

14

15

"., f:::"
-

:c
10 JLF

lOUT

10 kD.

680 kD.

ROUT
0.047 JLF

TUH/11028-5

FIGURE 1. Typical Application

•
1-241

Application Information
couple the SELECT OUT signals directly to pins 7 and 22,
respetively.

INPUT SELECTOR
The LMC1982's input selector and mode cOntrol are' shoWn
in Figure 2. fhe input. selector selects one of two stereo
signal sources or a mute function with typical attenuation of
100 dB. The selected signals are then sent to a mode control matrix. As shown in Table I, the matrix provides normal
stereo or can direct either 'channel to both LEFT or RIGHT
SELECT OUTPUTs. The third matrix mode is normal stereo.
The control matrix output is buffered and appears on each
channel's respective SELECT OUT pin (6, 23). Switching
noise is kept to a minimum whim mute is selected by using a
50 kO bias resistor.
Noise performance is optimized through the use of emitter
followers in the mode control matrix's output. Intemal 50 kO
resistors are connected to each input selector pin tQ provide
the proper bias point for the emitter follower buffers. Each
internal 50 kO bias resistor is connected to a common halfsupply (V+ /2) source. This produces a voltage at pins 6
and 23 (SELECT OUn that is 1.4V below' V+ 12 (typically
3.1V with V+ = 9V). Since a DC voltage is present at the
input pins (4, 5, 24, and 25), input Signal should be AC coupled through a 1 ,...F capacitor.
The output signal at pins 6 and 23 can be used to drive
exteral audio processing circuits such. as noise reduction
(LM1894-DNR or Dolby) or graphic equalizers (LMC835). It
is important that if any noise reduCtion is 'used it be placed
ahead of any tone controls or equalizers in thE!, external circuit path to preserve the frequency spectrum of the selected input signal. Otherwise, any frequency equalization could
prevent the proper operation of the noise reduction circuit. If
no external processor is used, a capacitor should be .used to

MINIMUM LOAD IMPEDANCE
The LMC1982 jlmployS emitter-followers to buffer the ~
lected stereo channels. The buffered sjgnals are available
at pins 6 and 23, (SELECT OUn. The SELECT OUT buffers
operate with a typical bias current 1 mAo
The Electrical Specifications table lists a maximum input signal of 2.0 Vrms (2.5 VpeaJJ.for 1% THD at the SELECT OUT
pins. This distortion level is achieved when the minimum AC
load impedance seen by the SELECT OUT pins, is 2.5 kO
(2.5V/1 mA). Using lower load impedances results in clipping at lower output levels. If the load impedance is DC-cou'pled; an increased quiescent current can flow. Latch-up may
occur if the total emitter current exceeds 5 mAo Thus, maximum output voltage can be increased and much lower dis'tortion levels can be achieved using load impedances of at
least 25 kO.
INPUT IMPEDANCE
The input impedance of pins 4, 5, 24 and 25 is defined by
internal bias resistors and is typically 50 kO.
The SELECT IN pins have an input impedance that varies
with the BASE and TREBLE control settings. The input impedance is 100 kO at DC and 19 kO at 1 kHz when the
controls are set at 0 dB. Miniinum input impedance of
30.4 kO at DC and 16 kO at 1 kHz occurs when maximum
boost is selected. At 10 kHz the minimum input impedance,
with the tone controls flat, is 6.8 kO and, with the tone controls at maximum boost, is 2.5 kO.

50kn'x4

RIGHT INPUT 1 O-....-+--I-It--oQ...
RIGHT INPUT 2 o---4--1-1t--o

51: Input Sala.t
52: Mod. Sale.t

RIGHT SELECT OUT

50knx4

y.
LEFT INPUTI o-.....-+--1-1t---OLEFT INPUT 2 o--.....
SIL...............-O''''!luta

'"1:::1h::g

LEFT SELECT OUT

TL/H/ll028-6

FIGURE 2. Input and Mode Select Circuitry

1-242

Application Information

(Continued)
EXTERNAL SIGNAL PROCESSING
The SELECT OUT pins (6 and 23) enable greater system
design flexibility by providing a means to implement an external processing loop. This loop can be used for noise reduction circuits such as DNR (LM1894) or multi-band graphic equalizers (LMC835). If both are used, it is Important to
ensure that the noise reduction circuitry precede the equalization circuits. Failure to do so results in improper operation
of the noise reduction circuits. The system shown in Figure
3 utilizes the external loop to include DNR and a multi-band
equalizer.

response is achieved when C2 = C3. However, with
C2 = 2(C3) and the tone controls set to "flat", the frequency response will be flat at 20 Hz and 20 kHz, and + 6 dB at
1 kHz.
The frequency where a tone control begins to deviate from
a flat response is referred to as the turn-over frequency.
With C = C2 = C3, the LMC1982's treble turn-over frequency is nominally
1

frr

The bass turn-over frequency is nominally

TONE CONTROL RESPONSE
Bass and treble tone controls are included in the LMC1982.
The tone controls used just two external capacitors for each
stereo channel. Each has a corner frequency determined by
the value of C2 and C3 (see Figure 4 ) and internal resistors
in the feedback loop of the internal tone amplifier. The maximum-boost or cut is determined by the data sent to the
LMC1982 (see Table I).
The typical tone control response shown in Typical Performance Curves were generated with C2 = C3 = 0.0082 JA.F
and show the response for each step. When modifying the
tone control response it is important to note that the ratio of
C3 and C2 sets the mid-frequency gain. Symmetrical tone

INPUll

= 2'ITC(14 kO)

1

fsr

= 2'ITC(30.4 kO).

when maximum boost is chosen. The inflection points (the
frequencies where the boost or cut is within 3 dB of the final
value) are for treble and bass
1

frl
f

= 2'ITC(1.9 kO)

_
1
BI - 2'ITC(169.6 kO)

INPUT
AND
NODE

INPUT 2

SELECT
I
I

I
I
I
I , . I

I
I

i---------·---------~----------·

I

DIGITAL
INPUT I

LOGIC
AND

DIGITAL
INPUT2

CONTROL

III
TL/H/11028-7

FIGURE 3. System Block Diagram Utilizing the External Processing Loop (One Channel Shown)

1-243

i....

Application Information (Continued)

(.)

::::::&
-I

As shown in Table I, loudness, and enhanced, stereo are
controlled through the samEi' address. It is: important to remember to, set, both functions to, the correct value any time
either of thase ,function!! is updated. ',",:

C2
,', : O.boB2l'r ",
7 {22}
IN

( 'j')

8 2

'~,~1",""""

"','

,C

"

56kA ...Li20pr.

11(18) ,', ,'"

"1<:4 ,'.
,T.

l

R

gs221'r
:5kn

TUH/ll028-9
I ,

V+/2
TLIlir11028-8

FIGURE 4. The Tone Control Amplifier
Increasing the values of C2 and, C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Curves will shift left
when C2 and C3 are increased and shift right when C2 and
C3 are decreased. With C2 = C3 = 0.0082 ,...F, 2 dB steps
are achieved at 100Hz and 10kHz. Changing C2 and C3 to
0.01 ,...F shifts the 2 dB per step frequency to 72 Hz and
8.3 kHz. If the tone control capacitors size is decreased
these frequencies will increase. With C2 = C3 = 0.0068 ,...F
the 2 dB steps take place at 130 Hz and 11.2 kHz.
LOUDNESS
The human ear has less sensitivity to high-and low frequencies relative to its sensitivity to mid-range frequencies between 2 kHz and 6 kHz for any given acoustic leyel. The low
and high frequency sensitivity: decreases faster than the
sensitivity to the mid-range frequencies as the acouStic level'
drops. The LMC1982's loudness function can be used to
help compensate for the decreased sensitivity by boosting
the gain at low ,and"high frequencies as the volume control
attenuation inCrE!8ses (SE!e the curve labeled "Gain vs Frequency with Loudness Active").
The LMC1982's loudness function uses external components R1, R2,C4 and C5, as/ShOwn in Figure 5, to select the
frequencies where bass and ,treble boost begin. The amount
of boost is dependent 011 the volume attenuator's setting.
The loudness characteri$tic, with the volume attenuator set
at 40 dB, haS a transfer function of
'
,
, ,
vo

(sC5R2 + lj[sC4(Rl

+ 156k)+ 1]

,Vi" = (s2)C4C6R2(163k) ;'1-; s[C4(156k) + C5(4.9R2 + 156k)1 + 1
The external componentS R1 and C4 can be eliminated and
pin 10(19) left open if bass boost is the only desired loudness characteristic.

FIGURE 5. Loudness Control Circuit

ENHANCED
sTEREO,
,
,
The LMC1982 has an enhanced,stereo eff,ect that can be
achieved by cross-coupling reverse, phase illformation be,
tween the left and right slereo channels. This feature can
h~lp improve the apparen(ster90 channeilleparation when,
because of, cabinet or equipment limitations, the iett and
right speakers are closer to ,~achother than optimum.'
En/1anced stereo is, created by conneCtIng an external frequency shaping RC network between the OUTPUT operational amplifiers' inverting inputs through an internal CMOS
switch (see Figure 6). The external network couples 60% of
each chlinnel's output to" the oppOsite channel's inverting
input. This cancels a pOrtidn of the Signal common to both
channels.

0.0471'r
C6

TUH/ll028-10

FIGURE 6. EnhanCed Stereo Circuit
The desired 60% cros8-(X)upling is accomplished through
the internal 6.5 kO ftledback resistor'and an external 10 kO
resistor. Bass frequency cancellation is prevented by using
a 0.047 ,...F coupling capaCitor to couple Ohly frequencies
above 330 Hz. Switching noise (s eliminated by using a
680 kO resistor acroSs the Cl.04i ,...F. R3, R4 and C6 can be
eliminated if enhanced stereo is not desired.
As shown in Table I, enhanced stereo and loudness are
controlled through the same address. It is important to remember to set both functions to the correct value any time
either of these functions is updated.
";(

1-244

Application Information (Continued)
SERIAL DATA COMMUNICATION

not all data bits are needed by each function. The extra bits
shown as "X"s ("don't cares") are position holders and
have no affect on a respective function. They are necessary
to properly position the data in the lMC1982's internal data
shift register. Unexpected results may take place if these
bits are not sent.
The lMC1982's internal data shift register can handle either
a 16-bit word or two 8-bit serial data transmissions. It is the
final 8 bits of data receilled before the 10 line goes high that
are used as the lMC1982 selection and function addresses.
The final eight bits after the 10 line returns high are used to .
change a function's operating point. ClK must be stopped
when the final 8 data bits are received. The data stored in
the internal data latch remains unchanged until the 10 is
pulsed, Signifying the end of data transmission. When 10 is
pulsed, the new data in the data shift register is latched into
the data latch and the selected function takes on a new
operating point.
A complete description and more information concerning
the 1M Bus is given in the appendix of ITT's CCU2000 datasheet.

The lMC1982 uses the INTERMETAl serial bus (1M Bus)
standard. Serial data information is sent to the lMC1982
over a three wire 1M Bus consisting of Clock (ClK), Data
(DATA), and Identity (10). The DATA line is bidirectional and
the ClK and 10 lines are unidirectional from the microprocessor or micontroller to the lMC1982. The lMC1982's bidirectional capability is accomplished by using an open drain
output on the DATA line and an extemal1 kG pull-up resistor.
The lMC1982 responds to address values from 01000000
(40H) through 01000111 (47H). The addresses select one of
the eight available functions (see Table I). The 1M Bus'lines
have a logic high standby state when using TTL logic levels.
As shown in Figure 7, data transmission is initiated by low
levels on ClK and 10. Next, eight address bits are sent. This
address information includes the code to select one of the
lMC1982's desired functions. Each address bit is clocked in
on the rising edge of ClK. The 10 line is taken high after the
eight bits of address data are received by the lMC1982.
The controlling system continues toggling the ClK line eight·
more times. Data that determines the selected function's
operating point is written into, or single bit information on
DIGITAL INPUT 1 or DIGITAL INPUT 2 is read from; the
lMC1982. Finally, the end of transmission is signalled .by
pulSing the 10 line low for a minimum of 1 ,..s. The transmitted function data is latched and the function changes to its
new setting.
Table I also details the serial data structure, range,. and bit
aSSignments that sets each function's operating point. The
volume and tone controls' function control data binarily increments from zero to maximum as the function's operating
point changes from 80 dB attenuation to 0 dB attenuation
(volume) or -12 dB to + 12 dB (tone controls). Note that

ID

--,!-__________

-I1

250n •

DIGITAL 110
The lMC1982's two Digital Input pins, 2 and 3, provide single-bit communication between a peripheral device and the
controller over the 1M Bus. Each pin has an internal 30 kG
pull-up resistor. Therefore, these pins should be connected
to open collector/drain outputs. The type of information that
could be received on these lines and retrieved by a controller include FM stereo pilot indication, power on/off, Secondary Audio Program (SAP), etc.
According to Table I, the logic state of DIGITAL INPUT 1
and DIGITAL INPUT 2 is latched and can be retrieved over
the 1M Bus using the read command (47H). The single-bit
information sent on the 1M Bus is active low sinc!, these
lines are internally pulled high.

~I

1

'-250 no

eLK

Tl/H/11028-11

FIGURE 7. LMC1982'siNTERMETAL Serial Bus Timing

1-245

•

!~ tfI N

4 t

i

0"'.4

I Semiconductor

LMC1983
Digitally-Controlled Stereo Tone and Vol.unie
Circuit with T~r.eeSelectable Stereo Inputs.
General Description·. .
The LMC1983 isa monolithic integrated circuit that provides
voiume, balance; tone (bass and treble); loudness controls
and selection betWeen three pairs of stereo inputs. These
functions
digitally comro"ed ll)rough a t!'Iree-wire communication Interface. There are two digital inpUts for easy
interface to other audio peripherals such as stereo decoders. The LMC1983 is designed for line level input signals
(300 mV-2V) and has.a maximum gain of ":0.5 ·dB. Volume
is set at minimum and 'tone conti'olsare flat when supply
.
voltage is first applied.

are

Low noise and distortion result from using analog switches
and. poly-silicon resistor networks in the signal ~th.
Additional tone control can be achieved using the LMC835
stereo 7-band graphic equalizer . connected to the
LMC1983's SEI£CT OUT/SELECT llil ext:emal processor
loop.

Features

•
•
•
•

Loudness compensation
40 position 2 dB/step volume attenuator'plus mute
IndependElnt left and right volume control$
Low noise-suitable for use. ,with DNR" and Dolby"
noise reduction
External processor loop
Signal handling suitable for compact discs
Pop-free sWitching
Seria"y programmable: INTERMETAL bus (1M) intertace
6V to 12V Single supply operation
28 Pin DIP. or PLCC Package

•
•
•
•
•
•

Applications
•
•
•
•
•

Stereo television
Music reproduction systems
Sound reinforcement systems
Electronic music (MIDI)
Personal computer audio control

• Low noise and-distortion
• Three pairs of stereo inputs

Block Diagram
22
RSELECTOUT

21
RSELECTIN

20
RTONEIN

19
RTONEOUT

18
17
ROPAMPOUT RlOUDNESS

26

. y'
15

16

GND

RIGHT
OUT

RINPUT 1 25
llNPUT 1

04

26
DATA

RINPUT 2 204

L INPUT 2

5

1.5kQ

LOGIC
AND

RINPUT3 23
i',.

LlNPUT 3

L..+_____-+

6

'LOUDNESS

COIITRDl

1
eLK
27
ID
2

DIGITAL
INPUT 1

L..--~Ir'~ITAL
INPUT 2

14o-H~~
BYPASS

7
LSELECTOUT

13

> ......I-oLm
OUT

6
LSELECTIN

9
LTONEIN

10
LTONEOUT

11

12

LOPAMPOUT LLDUDNESS

TUHI11279-1

1-246

r-

Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+ - GND)

Storage Temperature

GND - 0.2VtoV+ + 0.2V

Voltage at any Pin
Input Current at any Pin (Note 3)

20mA

Power Dissipation (Note 4)

500mW

Junction Temperature

+ 125°C

~
w

+ 260"C
215°C
220"C

ESD Susceptability (Note 5)

5mA

Package Input Current (Note 3)

-65°C to +15O"C

Lead Temperature
N Package, (Soldering, 10 Seconds)
V Package, (Vapor Phase, 60 Seconds)
Infrared, (15 Seconds)

15V

a::
.....

(')

2kV

Operating Ratings (Notes 1 and 2)
Temperature Range
LMC1983CIN, LMC1983CIV

TMIN S; TA S; TMAX
-40"C S; TA S; +85°C

Supply Voltage Range (V+ - V-)

6V to 12V

Electrical Characteristics The following specifications apply for V+ = 9V, fiN = 1 kHz, input signal
(300 mY) applied to INPUT 1, volume = 0 dB, bass = 0 dB, treble = 0 dB, and loudness is off unless otherwise specified. All
limits apply for T A = T J = + 25°C.
Symbol

Parameter

Conditions

Is

Supply Current

VIN

Input Voltage

Clipping Level (1.0% THO),
Select Out (Pins 7, 22)

THO

Total Harmonic Distortion

Left and Right channels;
Output Pins 13, 16
VIN = 0.3 V rms;
fiN = 100 Hz, 1 kHz,10 kHz
VIN = 2.0 Vrms;
fiN = 100 HZ,1 kHz
VIN = 2.0Vrms;
fiN = 10 kHz
VIN = 0.5 Vrms; Bass and Treble
Tone Controls Set at Maximum
VIN = 0.3 Vrms; Volume
Attenuator at - 20 dB, Bass and Treble
Tone Controls Set at Maximum

DC Shifts

VIN = 0.3 Vrms; between Any
Two Adjacent Control Settings
VIN = 0.3 Vrms;
All Mode and Input Positions

Typical
(Note 6)

Limit
(Note 7)

15

25
2.0

0.008

0.1

% (max)

0.4

1.0

% (max)

0.5

1.0

% (max)

0.07

0.5

% (max)

0.06

0.15

% (max)

2.0

4.0

mV(max)

18

20

mV(max)

200
40

o (max)
o (max)

72
35

kO(max)
kO(min)

0.5

1.5

dB (max)

80

78
82

dB (min)
dB (max)

2.0

1.5
2.5

dB (min)
dB (min)

±0.1

±1.5

dB (min)

±2.0

dB (min)

86

dB (max)

AC Output Impedance

Pins 7, 22, (4700 to Ground at Input)
Pins13,16

150
26

RIN

AC Input Impedance

Pins 4, 5, 23, 24, 25

50

Volume Step Size

Channel-to-Channel
Tracking Error

Mute Attenuation

Pins 13, 16; Volume
Attenuation at 010001 OXXXOOOOOO (0 dB)
010001 OXXX1 01 XXX (80 dB);
(Relative to Attenuation at
the 0 dB Setting)
All Volume Attenuation Settings
from 01 0001 OXXX1 01 XXX (80 dB) to
0100010XXXOOOOOO (0 dB) (Note 9)
All Volume Attenuation Settings
from 010001 OXXX1 0011 0 (76 dB) to
01 0001 OXXXOOOOOO (0 dB)
from 010001 OXXX1 01 XXX (80 dB) to
010001 OXXX1 00111 (78 dB)
VIN

=

105

1.0 Vrms
1-247

mA(max)
Vrms(min)

2.3

ROUT

Volume Attenuator Range

Unit
(Limit)

•

Electrical Characteristics The following specifications apply for V+
applied to INPUT 1, volume = 0 dB, bass
for TA = TJ = + 25"C. (Continued)
Symbol

Parameter

,

==

= 9V, fiN' = 1 kHz, inpuf signal (300 'mVJ
0 dB, treble =, 0 dB, and loudness is off unless othllrwise specified. Alilirnits apply
i
~:

'

Conditions

Typical
(Note 6)

Limit'
'(Note 7)

Unit'
(UmH)

Bass Gain Range

fiN = 100 Hz, Pins 13, 16

±12

±10.0
±14.0

dB (min)
dB (max)

Bass Tracking Error

fiN = 100 Hz, Pins 13, 16

±0.1

±1.5

dB (max)

fiN = 100 Hz, Pins 13, 16
': (Relative to Previous Level)

2.0

1.5
2.5

dB (min)
dB (max)

Treble Gain Range

fiN = 10 kHz, Pins 13,16

±12

±10.0
±14.0

dB (min)
dB (max)

Treble Tracking Error

fiN = 10 kHz, Pins 13, 16

±0.1

±1.5

dB (max)

Tre!>le Step Size

fiN = 10kHz, Pins 13, 16
(Relative to Previous Level)

2:0

1.5
2.5

dB'(min)
dB (max)

Frequency Response

VIN Applied to Input 1 and Input 2;
fiN = 20 Hz - 20 kHz
(Relative ta Signal Amplitude at 1 kHz)

±0.1

±1.0

dB (max)

11.5

13.5
9.5
8.5
4.5

dB (max)
dB (min)
dB (max)
dB (min)

Bass Step Size

Loudness

Volume Attenuator = 40 dB, Loudness
on (See Figure 5)
Gain at 100Hz (Referenced
to Gain at 1 kHz)
Gain at 10kHz (Referenced
to Gain at 1 kHz) ,

6.5

Signal-ta-Noise Ratio

VIN = 1.0 Vrms, A Weighted,
Measured at 1 kHz, Rs = 4700

95

90

dB (min)

Channel Balance

All Volume Settings

0.2

1.0

dB (max)

Channel Separation

Input Pins 4, 25: Output Pins 13, 16;
VIN = 1.0 Vrms(Note 8)

80

60

dB (min)

Input-Input Isolation

4700 to AC Ground on Unused Input

95

60

dB (min)

PSSR

Power Supply Rejection Ratio

V+ = 9 Vee; 200mVrrns, 100 Hz
Sinewave Applied to Pin 26 '

32

28

dB (min)

felK

Clock Frequency

5.0

1.0

MHz (max)

VIN(1)

Logic "1" Input Voltage

Pins 1, 27, 28 (1M Bus)
Pins2,3

1.3
2.9

2.0
5.5

V (min)
V (min)

VIN(O)

Logic "0" Input Voltage

Pins 1, 27, 28 (1M Bus)
Pins2,3

0.4
1.2

0.8
3.5

V (max)
V (max)

VOUT(1t
VOUT(O)

Logic "1" Output Voltage

Pin 28 (1M Bus)

2.0

V (min)

Logic "0" Output Voltage

Pin 28 (1M Bus)

0.4

0.8

V (max)

Note 1: Absolute Maximum RatingS indicate limits beyond which damage to the deivc$ may. occur. Operatil)g Ratings indicate conditions for which the device Is
functional, but do not guarantee specifIC performance limits. For guaranteed speCffications and last coriditionS, .... the Electrical Characteristics. The gueranteed
specifications apply only for the test conditions lislad. Some performance characteristics may degrade when the device Is not operatad under the listed test
conditions.
'Note' 2: All voltages are specified with respect to ground.
Note 3: W~ the Input voltage (VIW at any pin exceedslha power supply voltages (VIN < V- qr VIN > V+) the absolula value of the curreO\ at thet pin should be
limited to 5 rnA or less. The 20 rnA package input current limits the number of pins thet can exceed the power supply voltages with 5 mA current limit to four.
Note 4: The maximum power dissipelion must be deratad at elevalad temperatures and is dictated by TJMAX, IIJA' and the ambient temperature TA. The maximum
allowable poWer dissipation is Po = (TJMAX - TAJ/llJA Or the number given in the Absolute Maximum Ratii.gs, whichever Is lower. For the LMCl983C1N, TJMAX =
+ 125"C, and the typical junction-to-ambient thermal resistance'when board mounted, is 67"C/W.
Note 5: Human body modal; '100 pF discharged through a 1.5 kIl resistor.
Note 8: Typicals are at TJ = + 25'C and represent the most likely perametric norm.
Note 7: Umlts are guaranteed to National's AOOL (Average Outgoing Quality Level) .
Note 8: The Input.lnput Isolation Is tested by driving one input and 'lH'IISUring the output when the undriven input are selected.
Note 9: The Volume Step Size Is defined as the change In _nuation between any two adjacent volume attenuation setIIngs. The nominal Volume Slap Size is

2i1Ei.

,

1-248

Typical Performance Characteristics
Supply Current
vs Supply Voltage
30

TA = 25°C
V"=9V

25

~

i

1\=
THD-

t"

~
o
10

4

I.'"

0.4

,.l'i
.,~

~

o

3
10

100

o

AC LOAD IMPEDANCE (kll)

0.08

,I

g
z

S!
I;;

Output Pins: 13.16

~

-Vour=50mVrm'

VOUT. tOO mVrm •

JJ

t:l

VOI/T-300""",

0.0
0.0

1.0

0.5

1.5

2.0

10

20

Channel Separation
vs Frequency

,...

-70,--,...,....".=;:--,--...,
,. C75

Iii'

80

~

-80

I

-85

z

-

40

!
i!i

-90
-95
-100
-lOS

BO

100

2.5

I~PUT VOLTAGE (Vnn,)

Mute Gain
vs Frequency

Y+=9V

~

0.03

1/

VIN = 1Vrm

0.02

/

0.01

/

0.00

10

100

Ik

./
~
.... 0.3V...
10k

lOOk

FREQUENCY (Hz)

Tone Control Response
with, Equal Bass and
Treble Control SeHlngs

10k

Ik

FREQUENCY (Hz)

Input Plnl: .4, 25
0.08
Output Pins: 13,16
, 0.05 Tone Flat
0.04

~

100

AC LOAO IMPEDANCE (kA)

TA = 25°C

0.07

S!

l'i
~

'\

I

18

THD vs Frequency

TA = 25°C
V+=9V
Input Pins: ., 25

e

\

0.01

VOLUME ATTENUATION (dB)

THDvsVIN
(VOUT Constant)
1.0

14

\
\

I

12

Tone Flat

Tone Flat

Output Pin.: ~3. 16
Volume AUenuatlon = 0 dB
Ton. Flit

r-

0.00
10

Output Pins: 13,16

\
\

0.2

0.02

~

TA = 25°C
v+ =9V
Input Pinl: Grounded

~::~:~ ~~~~u6~t~o!I=lol~.

r-

i!i

I 111111

,~
.

V'=9V

g

II III
IIIIII

TA = 25°C

,--

0.8

0.03

CCIR Output Noise
vs Volume SeHlng

y+ =9V
YOUT = lYnn.

Your: IVrms

SUPPLY VOLTAGE (V)

THDvs
Load Impedance

-

TA =25~C

-

~

I

oJ

SUPPLY VOLTAGE (V)

O.B

~

I-

S!

2

12

0.04

I;;

V

/

o

g

I'

Tone FI.t

,/

10

.:

~

/

:~~"'A\Ion_~

./

15

"u

0.05

Output Pinl: 13. 16

V

20

IE

THDvs
Load Impedance

TA = 25°C
y+ =9V

~

'C
~

Output Voltage
va Supply Voltage

FREQUENCY (Hz)

Loudness Response
vs Frequency

Select Input Impedance
va Frequency
1M

18dB .....:l:l:lfltII-l-y, ...+-++I11III--7+

~

~
:!

Iii'

~

,~,

, OdS

~

,

'iE

-adS

~

lOOk
,

:~:-.~

WAX B()OS1'

.~

10k a..a and Treble

~

- _ . -12dB
- - O'dB
+12d8

..jIIII-_.

"'Ik

10k

FREQUENCY (Hz)

10

lOOk

FREQUENCY (Hz)

'100

"

WAX-;;;;

Ik

100

"AX CUT
FLAT

Settingai.

!;

10

I

v'=

S

adB

TA = 25°C
9V
Input.: pin. 71 22

Ik

10k

lOOk

FREQUENCY (Hz)

TL/H/11279-9

1-249

•

CO)

, CIO
CD
.,...

Connection Diagram

.;

:~

(J

:E
...J

CLOCK

~

DATA

.~,

10

DIGITAL INPUT 1
DIGITAL INPUT 2'"
LEFT INPUT 1
LEFT INPUT 2

y+

25

RIGHT INPUT 1

24

, LEFT, INPUT 3

l!;

~

!i:

!i:

5...

~,

RIGHT INP,UT ,2,

...t;

l!;

~

26

~

0

,

VI

~

l!;

Ii!
g

'"~ !i:~

RIGHT INPUT 3

LEFT SELECT OUTPUT

RIGHT SELECT OUTPUT

LEFT SELECT INPUT
LEFT TONE INPUT

LEFT LOUDNESS
LEFT IIAIN OUTPUT'

RIGHT LOUDNESS

DATA

RIGHT IIAIN OUTPUT

' CLOCK

GROUND

RIGHT OP AIotP OUTPUT

DIGITAL INPUT 1

BYPASS

RIGHT LOUDNESS

DIGITAL INPUT 2

RIGHT TONE OUTPUT

LEFT- ~P AIotP OUTPUT

RIGHT OP AIIP OUTPUT

10

RIGHT TONE INPUT

LEFT,TONE'OOTPUT,

BYPASS

y+

RIGHT SELECT INPUT

13

16

RIGHT IIAIN OUTPUT

14

15

GROUND

LEFT INPUT 1

12

LEFT LOUDNESS

...t; t; ~
...z ...~
g g
§ § '~"'
§

TL/H/11279~2

l!;

Top View

..
0

Z

Order Number LMC1983CIN
See NS Package.Number N28B

::II

'TL/H/I1279-10

Top View
Order Number LMC1983CIV
See NS Package Number V2aA

Pin Description
CLK (1)

DIGITAL INPUT

1 & 2 (2,;3)

The INTERMETAL (1M) Bus clock is applied to the CLOCK pin. This input ac-'
cepts a TIL or CMOS level signal. The
inpulis used to clock the DATA Signal. A
data bit must be valid on the rising clock
,edge. '

lntern~lIy tied high to V + through a" 30 kO ,pull-up resistor, these inputs allow
, a 'peripherat device to place any singlebit, active low 'digital information onto the
1M, Bus. It ;s then sent out to the controlling device through the DATA pin. Exam,pies ot such information could include in,dicatioh 'Of thll presence of a Second Au'dio Program (SAP) or an FM stereo carPi- .
er.

INPUTS 1, 2 & ,3 rhese are the LMC1983's three stereo
(4, 25; 5, 24;
input pairs.
6,23),
SELECT OUT
The selElCted INPUT signal is available
(7,22)
at this output. This feature allows exter'nal signal processors such
noise, reduction or graphic equalizers to be u~d. ,
This output can typically sink.1 mAo
Thesepins shOUld be capacitively coupled to pins 8 and 21, respectively, if no
e~~rnal processor is used.
'

TONE IN
(9,20)

These are the inputs to the tone control
amplifier. See the Application Information section titled "Tone Control Response".

TONE OUT
(10,19)

Tone control amplifier output. See the
Application Information section titled
"Tone Control Response".

OPAMP
OUT (11, 18)

These outputs are used with external
tone control capaCitors. Internally, this
output is applied to the volume attenuators.

LOUDNESS,
(12,17)

The output signal on these pins is a voltage'taken froni the volume attenuator's
-40 dB tap point. An external R":C network is connected to these pins.

MAIN
OUTPUT
(13,16)

The output signal from these pins drives
a stereo power amplifier. The output can
typically sink 1, mA~

BYPASS (14)

A 10 ,..F capaCitor is coMected between
this pin and ground to provide an AC
ground ,for the internal half-supply voltage ~eference.
",

_II

SELECT IN
(8,21)

These are the inputs that an external signal.procesSor uses to return a Signal to
the LMC1983. These pins sl)6uld be capaci~vely coupled to pins 7. and 22, 'respectively, if no external processor is

used.
1-250

:~~OUND (15)

This pin is co~nected to 'analog ground.

V+ (26) ,

Thislsthe'P9Wer,sljpply connection. The
LMC1983il!! opat'ational with.supply voltages from ,!,V to 12V. 1his' pin should be
byp~ed t6:9round through a 1.0 ,..F capacit~.
'

.10(27)

This"is th'& IDENTITY digitill input that,
when low; signals the LMC1983 to receive, from a controlling device, a device
address (40H-47H); present on the
DATA line.

Pin Description

op amps, and poly-silicon .resistors make it possible to
achieve an order of magnitude quality. improvement over
other bipolar circuits that use analog multipliers to accomplish gain adjustment. Internal circuits set the volume to
minimum, tone controls to flat, the mute to on, and all other
functions off when power is first applied: Individual left and
right volume controls are software programmed to achieve
the stereo balance function. Figure 1 shows the connection
diagram of a typical lMC1983 application.
The lMC1983 has internal decoding logic that allows a
microprocessor (,...1") or microcontroller (,...C) to communicate directly to the audio control circuitry through an
INTERMETAl (1M) Bus interface. This three-wire interface
consists of a bi-directional DATA line, a Clock (ClK) input
line, and an Identity (10) line. Address and function selection
data (8 bits) are serially shifted from the controller to the
lMC1983. This is followed by 8 bits of function· value data.
Data present in the internal shift register is latched and the
instruction is executed.

(Continued)

DATA (28) This is the serial data input for communications
sent by a controller. The controller must have
open drain outputs used with external pull-up
resistors. The data rate has a maximum frequency of 1 MHz. The lMC1983 requires 16
bits of data to control or change a function: the
first 8 bits select the lMC1983 and one of eight
functions. The final eight bits set the function to
a desired value. The data must be valid on the
rising edge of the CLOCK input Signal.

General Information
The lMC1983 is a CMOS/bipolar building block intended
for high fidelity audio Signal processing. It is designed for
line level inputs signals (300 mV - 2V) and has a maximum
gain of -0.5 dB. While the lMC1983 is manufactured with
CMOS processing, NPN transistors are used to build low
noise op amps. The combination of CMOS switches, bipolar
DIGITAL DIGITAL
I.NPUT 2 INPUT 1

elK

DATA

10

~
lEFT INPUT 1 .....---,

~
LEFT INPUT 2 .....---,
lEFT INPUT 3

~
'LMC1983

0.47 JlF
0.0082 JlF
10

19

11
240 pF

'''']
1.5ktl

+

•

240 pF

12
13

16

14

15

=!=

f""
1.5kll

-

10 JlF

LOUT

ROUT

FIGURE 1_ Typical Application

1-251

TLlH/11279-3

~pplicat'ortlnformati,~n
couple the ~\-EPT OUT signals direcUy to pins 8 and 21,
respectil(ely. ."'

I"PUTSE;LEcT dB. Minimum input impedance of
3.0.4 kG at DC and 16 kG at 1 kHz occurs when maximum
boost is selected. At 1.0 kHz the minimum input impedance,
with the tone controls flat, is 6.8 kG and, with the tone controls at maximum boost, is 2.5 kG.

~Y+/2

50 kD.x4
y+

RIGHT INPUT 1
RIGHT INPUT 2
RIGHT INPUT 3

).

51 : Input Select
52: lIod. Select

RIGHT SELECT OUT

."f

Y+/2
':"',"~,

. <',',

.50kilx4

LEFT INPUT 1
LEFT INPUT 2
LEFT INPUT 3

LEFT SELECT OUT

TLIH/11279-4

FIGURE 2. Input and Mode Select Circuitry

1-252

r-

Application Information (Continued)

"

Address
(A7-AO)

Function

Data

Function
Selected

01000000

Input Select + Mute

XXXXXXOO
XXXXXX01
XXXXXX10
XXXXXX11

INPUT1
INPUT2
INPUT3
MUTE

01000001

Loudness

XXXXXXXO
XXXXXXX1

Loudness OFF
Loudness ON

01000010

Bass

XXXXOOOO.
XXXX0011
XXXX0110
XXXX1001
XXXX11XX

-12dB
-SdB
FLAT
+SdB
+12dB

01000011

Treble

XXXXOOOO
XXXX0011
XXXX0110
XXXX1001
XXXX11XX

-12dB
-SdB
FLAT
+SdB
+12dB

01000100

Left Volume

XXOOOOOO
XX010100
, XX101xXX
XX11XXXX

OdB
-40dB
-BOdB
-BOdB

01000101

Right Volume

XXOOOOOO
XX010100
XX1 01 XXX
XX11XXXX

OdB
-40 dB
-BOdB
-BOdB

XXXXX100

L&ftMono
Stereo
Right Mono

01000110

Mode Select

XXXXX101
XXXXX11X
01000111

Read Oigitallnput 1
or
Oigitallnput 2
on 1M Bus

XXXXXX0100

.,

.,

1-253

(')

:wI

TABLE I. 1M Bus Programming Codes for LMC1983

•.

iC

00.= Oigitallnput 1
01 = Digital Input 2

~

~

r---------------------------------------------------------------------------------,

....

Application Information (Continued)

:5

EXTERNAL SIGNAL PROCESSING

(,)

The SELECT OUT pins (7 and 22) enable greater $y$tem
design flexibilitY by .provlding a meims to implement an extemal processing loop. This loop ea.n be used for noise reduction circuits such as DNA (LM1894) or multi-band graphic equalizers (L:MC835). If both are used, it is important to
ensure that the noise reduction circuitry precede the 6I!Iualization circuits. Failure to do so results in improper operation
of the noise reduction circuits. The system shown in Figure
3 utilizes the extemal loop to include DNR and a multi-band
equalizer.

,".

The frequency where a tone control begins to deviate from
a flat re!sponse is referred to as the tum-over frequency.
With C = C2 ,.; C3, the LMC1983's treble tum-over fre.
quency is nominally

frr =

1
fBT = 21TC(30.4 kO)

Bass and treble tone controls are included in the LMC1983.
The tone controls use just two external capacitors for each
stereo channel. Each has a comet frequency determined by
the value of C2,aQd C3 (see Figur~ 4 ) and intemal resistors
in the feedback loop of the intemal tone amplifier. The maximum-boost or cut is determined by the data sent to the
LMC1983 (see Table I).

when maximum boost is chosen. The inflection paints (the
frequencies where the boost or cut is within 3 dB of the final
value) are for treble and bass

1
fTI = 21TC(1.9 kO)

The typical tone control response !Shown in Typical Performance Curves were generated with C2 = C3 '= 0.0082 ",F
and show the re!Sponse for each step. When modifying the
tone control response it is important to note that the ratio of
C3 and C2 sets. the mid-frequency gain. Symmetrical tone·

INPUT 1

INPUT 3

1
21TC(14 kO)

The bass tum-over frequency is nominally

TONE CONtROL RESPONSE

INPUT 2

f

response is achieved when C2 = C3. However, with
.. C2 =' 2(C3fand'the tone controls set to "flat", the frequency response will be flat at 20 Hz and 20 kHz, and +6 dB at
1 kHz.

f

_
1
BI - 21TC(169.6 kO)

INPUT
AND
NODE
SELECT
I
I

I
I '

I
I

I
I

i---------·---------·----------·
I

I

DIGITAL
INPUT 1
DIGITAL
INPUT 2

LOGIC
AND
CONTROL

TL/H/11279-5

FIGURE 3. System Block Diagram Utilizing the External Processing Loop (One Channel Shown)

1-254

r-----------------------------------------------------------------------------~ ~

Application Information

iii:

(Continued)

8(21)

9(20)

10 (19)

11(18)

SELECT IN

TONE IN

TONEOUT

OPAWPOUT

of boost is dependent on the volume attenuator's setting.
The loudness characteristic, with the volume attenuator set
at 40 dB, has a transfer function of .
~

v,

=

o....

!

(sC5R2 + 1)[sC4(Rl + 156k)+ 1)
(s2)C4C5R2(I63k) + s)C4(156k) + C5(4.9R2 + 156k)) + 1

The external components R1 and C4 can be eliminated and
pin 11 (18) left open if bass boost is the only desired loudness characteristic.
11(18)

Rl

~220PF

0

12 (17)

V+/2

PF

R~.Skn

TlIH/11279-6

FIGURE 4. The Tone Control Amplifier
Increasing the values of C2 and C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Curves will shift left
when C2 and C3 are increased and shift right when C2 and
C3 are decreased. With C2 = C3 = 0.0082, 2 dB steps are
achieved at 100 Hz and 10 kHz. Changing C2 and C3 to
0.01 p.F shifts the 2 dB per step frequency to 72 Hz and
8.3 kHz. If the tone control capaCitors' size is decreased
these frequencies will increase. With C2 = C3 = 0.0068 p.F
the 2 dB steps take place at 130 Hz and 11.2 kHz.

Tl/H/11279-7

FIGURE 5. Loudness Control Circuit
SERIAL DATA COMMUNICATION
The lMC1983 uses the INTERMETAl serial bus (1M Bus)
standard. Serial data information is sent to the lMC1983
over Ii three wire 1M Bus consisting of Clock (ClK), Data
(DATA), and Identity (10). The DATA line is bidirectional and
the ClK and 10 lines are unidirectional from the microprocessor or micontroller to the lMC1983. The lMC1983's bidirectional capability is accomplished by using an open drain
output on the DATA line and an external 1 kO pull-up resistor.
The lMC1983 responds to address values from 01000000
(40H) through 01000111 (47H)' The addresses select one of
the eight available functions (see Table I). The 1M Bus' lines
have a logic high standby state when using TTL logic levels.
As shown in Figure 6, data transmission is initiated by low
levels on ClK and 10. Next, eight address bits are sent. This
address information includes the code to select one of the
lMC1983's desired functions. Each address bit is clocked in
on the rising edge of ClK. The 10 line is taken high after the
eight bits of address data are received by the lMC1983.

LOUDNESS
The human ear has less sensitivity to high and low frequencies relative to its sensitivity to mid-range frequencies between 2 kHz and 6 kHz for any given acoustic level. The low
and high frequency sensitivity decreases faster than the
sensitivity to the mid-range frequencies as the acoustic level
drops. The lMC1983's loudness function can be used to
help compensate for the decreased sensitivity by boosting
the gain at low and high frequencies as the volume control
attenuation increases (see the curve labeled "Gain vs Frequency with loudness Active").
The lMC1983's loudness function uses external components R1, R2, C4 and C5, as shown in Fl(Jure 5, to select the
frequencies where bass and treble boost begin. The amount

ID

IC"'

,T,gs22

I!-__________----!!

-I

r250ns

1

'-250 no

ClK

DATA

AD

AI' A2 • A3 • A4 • A5 • A6' A7' DO • 01 • 02 • 03 • D4 • 05

06' D7 • - TL/H/11279-8

FIGURE 6_ LMC1983'sINTERMETAL Serial Bus Timing

1-255

•

~ r-------------------------------------------------------------------------~
ClO

....

G)

(,J

~

Application Information (Continued)
The controlling systemoontinues toggling,thE! eLK line eight
more ,times. Data that determines the 'selected fonction~s
operating point is written into, or' single,blt informatiol'l on
DIGITAL INP\,JT 1 or DIGlTAL INPUT2 is read from, the
LMC19~3\Fin~Iy,,~he end,opra~SmiSSi(ln is,lIignaled by
pulsing the 10 ,Ii':l~ ,I()w for a minimum of 3 p.s. The, transm~.
t~ funCtion data ,is latched and ,thEl funCtion' qMng!!8 to its
new!ietting.
""

• ! ~

change a functiol)'s operating point. CLK must be stopped
wi'len the final 8 data bits are received. The data stored in
the internal data latch remains unchanged until the 10 is
pulsed, signifying the end of. data transmission. When 10 is
puls9d, the neW data in ,the data shift register is latched into
the ~ata latch and the selected fum:ti.on takes on a
operating point.

new

A compiete description and more information concerning
the 1M Bus is given in the appendix of In's CCU2000 data·
sheet.
",",'" '

Table I also details the serial data structure, ~arige, and bit
assignments that sets each funCtion's operating point. The
volume and tone controls' funCtion control data binarily in·
crements from zilro to maximum as the function's operating
point changes from 80 dB attenuation to '0 dB attenuation
(volume) or -12 dB-to + 12 dB (tone controls). Note that
not all data bits are ne6!ied by each function. The extra bits
shown as "X"s {'~don't cares") are position holders and
have no affect on a rellPective control. They are necessary
to properly position the data in the LMC1983's internal data
shift register. Unexpected results may take place if these
bits are not sent.
-, ,,'

DIGlTALIIO
TheLMC1983's two Digital Input pins, 2 and 3, provide sin·
gle·blt communication between a peripheral device and the
controller over the 1M Bus. Each pin has an internal 30 kG
pull·up resistor. Therefore, these pins should be connected
to open colleqtorI drain outputs. The type of i~formation that
could be received on these lines and retriev9d by a control·
ler include FM stereo pilot indication, power on/off,Second.
ary Audio Program'(SAP), etc.
According to, Table I, the logic state of DIGITAL'INPUT 1
arid DIGITAL INPUT 2 is latched and can be retriev8d over
the 1M, Bus using the read command (47H)' The single·bit
irifon,natl9,n sent on the, 1M Bus is ,active low since these
lines -are ,intern~11y pulled high.

The LMC1983's internal d,ata shiftregi~er,~fJ l'Iandleeith,er
a 16-blt ,word or two 8-blt serial data transmissions. It is the
flnal8, bits of d~ta ,re.cEliv~d' bef()re the 10 line goes high that
are,used as tli!! ,LMC1983 selection and function addresses.
The firi~leig~i bits after the 10 I,ne returqs hIQh ~r,e used to

'.

':.

'.

,,\

" ,~

1-256

"

tflNational Semiconductor

LMC1992 Digitally-Controlled Stereo Tone and Volume
Circuit with Four-Channel Input-Selector
General Description

Features

The LMC1992 is a monolithic integrated circuit that provides
four stereo inputs, bass and treble tone controls, and volume, balance, and front-rear fader controls. These functions
are digitally controlled through a three-wire communication
interface. All of the LMC1992s functions are achieved with
only three external capacitors per channel. It is designed for
line level input signals (300 mV - 2V) and has a maximum
gain of 0 dB.
The internal design is optimized for external capaCitors having values of 0.1 ,...F or less. This allows the use of chip
capacitors for coupling and tone control functions.
Low noise and distortion result from using analog switches
and thin-film silicon-chromium resistor networks in the signal path.
Volume and fader are at minimum and tone controls are flat
when supply voltage is first applied.

•
•
•
•
•
•
•
•
•

Additional tone control can be achieved using the' LMC835
stereo 7-band graphic equalizer connected to the
LMC1992's select-out/select-in external processor loop.

•
•
•
•

Low noise and distortion
Four stereo inputs
40 volume levels including mute
20 fader levels
All attenuators have a 2 dB of attenuation per step
Front/back fade control
External processor loop
Only three external components per channel
Serial programmable: standard MICROWIRETM
interface
Single supply operation: 6V to 12V supply voltage
Protection address (similar to 058906)
DC-coupled inputs
Single supply operation

Applications
• Automotive audio systems
• Sound reinforcement systems
• Home entertainment-stereo television and music reproduction systems
• Electronic music (MIDI)

Block and Connection Diagrams
I

28

Y+

ClOCK

2

27

BYPASS

DlA8LE

3

26

RlGHTINI'\JTI

DATA

LEFT INPurl

4

23

RIGHT 1NPtJT2

LEFT 1NPUT2

5

24

RIGHT 1NI'\JT3

LEFT 1NPUf3

6

23

RIGHT INPUT4

LEFT INPUT4

7

22

RIGHT SELECI OUT

LEfT SELIC! our

8

21

RIGHT SELEClIN

LEFT SnlCT IN

9

20

RIGHT TONE IN

LEFT TONE 1M

10

19

RIGHT TONE our

LEFT TONE OUT

11

18

RIGHT OP ....P our

lIFT OP AMP OUT

12

17

RIGHT REAR our

our
LEFT FRONT our

13

16

RIGHT FRONT our

14

15

GROUND

LEFT REAR

UlCI992

Tl/HI1 0789-2

Order Number LMC1992CCN
See NS Package Number N28B
TUH/l0789-1

left channel shown, Pin numbers in parentheses are for the right channel.

1-257

Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required;
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

Supply Voltage (V+ - GND)

ESO Susceptibility (Note 5)
Pins9,10, 11,19, 20,21

15V
GND - 0.2V to V+

Voltage at Any Pin
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
Junction Temperature

- 65°C to

Lead Temperature
N Package, Soldering, 10 sec.

+ 0.2V
5mA

+ 1500C
+ 2600C
2000V
850V

Operating Ratings (Notes 1 and 2)

20mA

Temperature Range
LMC1992CCN

500mW
125°C

TMIN S; TA S; TMAX
OOC S; TA S; 700C

Supply Voltage Range (V+- V-)

6Vto 12V

Electrical Characteristics The following specifications apply for V+ = 8V, fiN = 1 kHz, input signal applied to
channel 1, volume
25°C.
Symbol

= 0 dB, bass = 0 dB, treble = 0 dB, and faders =

Parameter

Is

Supply Current

VIN

Input Voltage

VOUT

Output Voltage

THO

Total Harmonic Distortion

0 dB unless otherwise specified. All limits TA

Typical
(Note 6)

Conditions

Units
(Umlt)

27.0

mA(max)

2.3

2.0

Vrms(min)

Clipping Level (1.0% THO),
, Outputs (Pins 13, 14, 16, 17)

1.2

0.65

Vrms(min)

0.15
0.03

0.3
0.1

% (max)

6.5

30.0

p.Vrms (max)

5.0

20.0

p.Vrms (max)

100
80

150
120

.0 (max)
.0 (max)

All Four Channels
Volume Attenuator at 0 dB, Input Level 0.3 Vrms
Volume Attenuator at -20 dB,lnput Level 0.6 Vrms

= on
= on

Output Noise

All Four Channels CCIR/ ARM Filter, Rs

EnOUT

Output Noise

All Four Channels CCIR/ ARM Filter, Rs
Volume Attenuator = -80 dB

ROUT

DC Output Impedance

Pins 8, 22
Pins 13, 14, 16, 17

OC Input Impedance

Pins 4, 5, 6, 7, 23, 24, 25, 26

Volume Attenuator Range

Pins 16, 17; Volume Attenuation at
0101110100X (0 dB); (Absolute Gain)
01()11000000 (80 dB); (Relative to Attenuation at
' the 0 dB setting)
"

,Volume Step Size

All Volume Attenuation Settings from 01011001010
(60 dB) to 01011101 QOX (0 dB) (Note 9)

Channel-ta-Channel Volume
Tracking Error

Fader Attenuation from 1XXXOOOOOO
(40 dB) to 1XXX1010X (0 dB)

Fader AttenuatiOn Range

Pins 16, 17; Fader Attenuation at
011 XXX1 01 OX (0 dB); (Absolute Gain)
011XXXOOOOO (40 dB); (Relative to Attenuation at
the 0 dB setting) ,

Fader Step Size

Umlt
(Note 7)

Clipping Level (1.0% THO),
Select Out (Pins 8, 22)

EnOUT

RIN

= TJ =

All Fader Attenuation Settings from 011 XXXOOOOO
(40 dB) to 011XXX1010X (0 dB) (Note 10)

1-258

2

~(max)

M.o

-1.0

-1.5

dB (max)

~O.O

75.0

dB (min)

2.0

0.7
4.3

dB (min)
,dB (max)

±0.5

±1.0

dB (max)

-1.0

-1.5

dB (max)

40

38.0

dB (min)

2.0

1.0
4.5

,dB (min)
dB (max)

Electrical Characteristics The following specifications apply for V+ = 8V, fiN =
channel 1, volume
25"C. (Continued)

Symbol

=

0 dB, bass

=

0 dB, treble

=

0 dB, and faders

Parameter

=

1 kHz, input signal applied to
0 dB unless otherwise specified. All limits TA = TJ =

Conditions

Typical

(Note 6)

Umlt
(Note 7)

Units
(Limit)

=
=
=

100 Hz, Pins 14, 16

±12

±10.0

dB (min)

100 Hz, Pins 14,16

±0.1

±1.0

dB (max)

2.0

1.0
3.0

dB (min)
dB (max)

=
=
=

10kHz,Pins14,16

±12

±10.0

dB (min)

10 kHz, Pins 14,16

±0.1

±1.0

dB (max)

1.0
3.0

dB (min)
dB (max)

?O

kHz
kHz (min)

Bass Gain Range

fiN

Bass Tracking Error

fiN

Bass Step Size

fiN
100 Hz, Pins 14, 16
(Relative to Previous Level)

Treble Gain Range

fiN

Treble Tracking Error

fiN

Treble Step Size

fiN
10 kHz, Pins 14,16
(Relative to Previous Level)

2.0

Frequency Response

-3dB
- 0.3 dB (Relative to Signal Amplitude at 1 kHz)

450

=
=
=

Channel Separation

VIN

Input-Input Isolation

VIN

PSRR

Power Supply Rejection Ratio

V+
8 Vee; 100 mVp_p,
100 Hz Sinewave Applied to Pin 28

fCLK
VIN(l)
VIN(O)

1.0 Vrms

97

70

dB (min)

1.0 Vrms (Note 8)

90

70

dB (min)

40

31

dB (min)

Clock Frequency

1.0

0.5

MHz (max)

Logic "1" Input Voltage

1.3

2.0

V (min)

Logic "0" Input Voltage

0.4

0.8

V (max)

Note 1: Absolute Maximum Ratings indicate limHs beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specHications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are specHied with respect to ground.

Note 3: When the input voltage (YIN) at any pin exceeds the power supply voltages (YIN < V- orVIN> V+) the absolute velue of the current althat pin should be
IimHed to 5 mA or less. The 20 mA package input current limHs the number of pins thet .can exceed the power supply voltages wHh 5 mA current IimH to four.
Note 4: The maximum power dissipation must be de-rated at eleveted temperatures and is dictated by TJMAXo 4>JA, and the ambient temperature TA. The maximum
allowable power dissipation is PO = (TJMAX - T!J18JA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMCI992CCN, TJMAX
= 125"C, and the typicaljunction-Io-ambient thermal resistance, when board mounted, is 67"C/W.
Note 5: Human body model; 100 pF discharged through a 1.5 kG resistor.
Note 6: Typlcals arB at TJ

= 25"C and rapresent the most likely parametric norm.

Note 7: UmHs are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: The Input-Input IsOlation is tested by driving one input and measuring the front outputs when the undrivan h,puts arB selected.
Note 9: The Volume Step Size is defined as the change in attenuation batween any two adjacent volume attenuation sellings. The nominal Volume Step Size is

2 dB.
Note 10: The Fader Step Size is defined as the change in attenuation between any two adjacent fader attenuation settings. The nominal Volume Step Size is 2 dB.

•
1-259

Typical Rerformance"Characteristics
Quiescent Current vs
24 Supply Voltage

Maximum Output Swing vs
Supply Voltage

2S

n

1

250 _ _' Vci=OdB

I J..'I, J J. U
~ts:Pln. 13,14, 16,17/",
v+=8V. '
VIN =300mV
THD=IX
fll=1 kHz

~

i

TA =25"C
v+=8V

.t

iii

Output Noise Voltage
vs Frequency

T -25"C

20
'18
16
14
::> .12
u
10
.~
8
a..

'."

..

--VOL =.-80 dB

2OOrtHffi~~~t#~1+~

I

~

,~

~.

150'

..s

"

100

~

4

2

I

0
0

12

4

8 10 12
SUPPLY VOlTAGE (V)

o

o

14

2

4

6

8

10

TLlH/10789-3

'.Total Harmonic Distortion '.

1:0

II III
J.IJJIJl

- - VII =300mV
'
Inpuls: pins 4,26
- - Outputs: pin. 13, 14, 16, 17

o.s
" D.6

.'"
0

'.

\

Q.2

0.0

1

~
~
!o!

,0.16 ~

:!!

i!le

"

"

r. .

,

0.12

10

o
o

',100

z

iU!

.. 01
z

z

~
!o!

TA=25"C·1 . ,
v+=8V .
004 Inputs: pin. 4,26
Outputs; pin.
. 14,
. 16 ,

z

!ii'
:!

~

'"
~

e
100

1000

10000

100000

FREQUENCY (Hz)
TLlH/10789-9

I
I
I
I

0.2

o
o

~

~

200

-10<11 -

li' -20<11

...

.i

f-

vs Frequency
TA=25"C 1111111

'~%om~llilll

Hr-tttt+ttHlilriiiiP'uts:
a, P~.Inii::.:!,4Y&lT1:n2r1:6~
0

-30<11 -:'
,.- ,

~"':plnsl'"l.'

!;l -40<11

-70<11-60<11-

-

100
600

I-

!i: -60<11 .;;..

,~
..,
~

~

~.80

~ -50<11 ":""

,

;:!!

~enuation

I

0'&

30 80

TL/H/10789-8

0<11-

'--VO=3OmV
---Vo=100mV
----Vo=300mV

0

Ii

-90

~

VOLUME S[TTING (-dB)

TLlH/10789-7

g
-eo

W.20 30

SELECT OUT LOAD (kA)

Total Harmonic Distortion
vs Input Voltage

~

IV

Ton. Control flat
I--- I - Inputs: pin. 4,26 1 - OutpUtS:"'n. 13,14,16,1'1

1

OJ!

........

TA=25!>C

1;l/H/1~789-6

li'

" 1".

I-- I - v+= 8V I
Rs=oa I,

I'-

OUTPUT LOAD RESISTANCE: (kA)

.',

'Of

Inputs: pins' 4, 26
Outputs: pins 8,:n

0.10

100 .

10

CCIR Output Noise Voltage

\

0.14

100000

6 vs Volume S._tlng .

v+=8V'
VII ='300 mV

0.18

10000

TLlHi10789-5

TA=25"CI:~~

g

z

\

'OA

1000

FREQUENCY (Hz)

Total Harmonic Distortion'
va Select OutAC Load
Q.2O

1

1.00

14

TLlH/l0789-4

1.2 vs'Output AC Load

~:~~~

12

SUPPLY VOlfAGE' (y)

800 1000 1200

INPUT VOLTAGE (mY)
TL/H/10789-10

lk

10k

lOOk

FREQUENCY (Hz)
TLlH/10789-11

Typical Performance Characteristics
Tone Control Response
with Equal Bass and
Treble Control Settings

(Continued)

Tone Control Response
",Ith Reciprocal Bass and
Treble Control Settings

Treble Tone Control
Response

20

20

2O~~~-r~mrTTnrn~'

16

16
12
8
4
0
-4

16~~~~H*~++Hffi~~

12
8
4

'iii'
~

o

~

-4

-a

-a

-12

-12
-16
-20

-16
-20

L-L...L.J..::===:"=.:":":";c;:..;.;.......w

20

100

8~~~~H*~+t~~~

20

20k

lk

12~~~~H*~++Hlli~~

100

FREQUENCY (Hz)

20

20k

lk

TL/H110789-12

Select In Impedance
YS Frequency
1.011

TA=25"C

16 H±l:l#tll-~HtII~+++
300k

12 H=FIi~rt-,HtII~+++
8 H-++I_~H-ffiIHl-+++

lOOk

4H:EEERIII-o<1'iE
o H++HfIII--E

S.

~

-aHTl'ffllll'.;~tttttH*

-12 H~ItlIf'!4+++I C.=Ci·=o.o082~"'1
-161-f"FHtttfI-~f+H.-ll·"

""\

-... ~---',-

30k

10k Ba.. and Treble
SoUingo:
-----12d8
3.Ok -OdS
•_.-+I 2dS

-

J

L...J...LJ.LWL:C==;';;:":=.:':";;::..;.;.J

lk

v+=8V
Inputs: plno 9,21

-......

---

~

-4 H±±:I:iOIII"'%Il

100

20k

TUH/l0789-14

TL/H110789-13

2O.---...,;,.,-rmr........,.,."m.-.,..,..

20

lk

FREQUENCY (Hz)

.Bass Tone Control
Response

-20

100

FREQUENCY (Hz)

I.Ok
10

20k

FREQUENCY (Hz)

100

1.0k

10k

.
lOOk

Frequoncy (Hz)
TUH/l0789-15

TL/Ht10789-16

Connection Diagram
DATA

•1

28

v+

ClOCK

2

27

BYPASS

ENABLE

3

26

RIGHT INPUT 1

LEFT INPUT 1

4

2S

RIGHT INPUT 2

LEFT INPUT2

S

RIGHT INPUT 4

LEFTINPUU

RIGHT SElECT OUT

LMC1992

LEFT SELECT OUT

II

RIGHT INPUT 3

LEFT INPUl3

LEFT SElECT IN

RIGHT SELECT IN
RIGHT TONE IN

LEFT TONE IN

10

RIGHT TONE OUT

LEFT TONE OUT

11

RIGHT OP AMP OUT

LEFT OP AMP OUT

12

RIGHT REAR OUT

LEFT REAR OUT

13

RIGHT FRONT OUT

LEFT FRONT OUT

14

GROUND
TUH/l0789-17

1-261

Pin Description
DATA(I)

CLOCK(2)

~(3)

This is the serial data input for communications sent by a controller. The data rate has a
maximum frequency of 500 kHz. The
, LMC1992 requires 11 bits of data to control
or change a function: the first two bits, a 1
and 0, select the LMC1992, the next three
bits select a function, and the final six bits set
the function to a desired value. The data
must be valid on the rising edge of the
CLOCK input signal.
The CLOCK input accepts a TIL or CMOS
'level clocking Signal. The input is used to :
clock the DATA input signal and determines
when a data bit is valid.

REAR OUT
(13, 17)

This pin's output signal is intended for the
rear amplifiers in a four speaker stereo system. The output can typically sink 350 p.A.
FRONT OUT This pin's output Signal is intended for the
(14, 16)
front amplifiers in a four speaker stereo system. Tlie output can typically sink 350 p.A.
, GROUND
(15)
V+ (28)

This is the system ground connection.

This is the power supply connection. The
LMC1992 is operational with supply voltages
from 6V to 12V. It is recommended that this
pin Is bypassed with 0.1 p.F capacitor.
BYPASS (27) A 10 p.F capacitor is connected between this
pin and ground.

This input accepts a logic low signal' wilen a
controller is addressing the LMC1992. When
i:IiIABIE is active, the LMC1992 responds to
input Signals present on the DATA and
CLOCK inputs.
'

General Information
The LMC1992 is a CMOS/bipolar high quality building block
intended for high fidelity audio signal processing. It is deSigned for line level input Signals (300 mV - 2V) and has a
maximum gain of -1 dB. While the LMC1992 is manufactured with CMOS processing, NPN transistors are used to
build low noise op amps. The combination of CMOS
switches, bipolar op amps, and SiCr resistors make it possible to achieve an order of magnitude quality improvement
over other bipolar circuits that use analog multipliers to accomplish gain adjustment.

INPUT 1-4 Four two-channel analog inputs are available
(4-7,23-26) on the LMC1992. These pins should be dc-biased to mid-supply.
SELECT OUT The selected INPUT Signal is available at this
(8, 22)
output. This feature allows the use of extemal
signal processing such as :noise reduction or .
graphic equalizers. This output can typically
sink 1 mA.
SELECT IN This is the input that an external signal proc(9,21)
essor uses to return a signal to the LMC1992.
, This is the input to the tone control amplifier.
TONE IN
(10,20)
See the Application Information section titled
"Tone Control Response".

The LMC1992, has internal decoding logic that allows a
computer (p.P) to communicate ~irectly to the audio control
circuitry through a standard MICROWIRE interface. This
three-wire interface consists of a DATA input line, a CLOCK
input line, and an ENABLE line. When the 8'lABLE line is
low, data can be serially shifted from the controller to the
LMC1992. As the EiiIAEiLE line goes through the low-tohigh transition, any additional data is ignored. Data present
in the internal shift register is latched and the instruction is
executed.
Figure 1 shows the connection diagram of a typical
LMC1992 application.

Tone control amplifier output. See the Application Information section titled "Tone Control Response".
OP AMP OUT This output is used externally with the tone
(12, 18)
control capacitors. Internally, this output is
applied to the volume attenuators.

TONE OUT
(II, 19)

y+ (+8V)
DATA
FROII I'P CONTROLLER

ClOCK
ENABLE

\...-/

I

28

2

27

3

26

LEFT INPUTt
04
LEFT INPUT2 5

25
204

LEFT INPUT 3 6
LEFT INPUT04
7
LIIC1992
o.11'~ SELECT OUT 8
SELECT IN
9
TONE IN
0.00821'rr:
10
TONE OUT
11
0.0082 ~ OP AIIP OUT 12
I' LEFT REAR OUT
13
'
,
TO POWER AMPS LEFT FRONT OUT
104
LEFT

23
22
21
20
19
18

Vee

t

BYPASS

+

RIGHT INPUT 1
RIGHT INPUT 2

-

RIGHT INPUT 3
RIGHT INPUT 04
SELECT ouT
SELECT IN
TONE IN
TONE OUT
OP AMP OUT

~.I I'F

-~.O0821'F
~.O0821'F

RIGHT' REAR OUT
17
16 RIGHT FRONT OUT TO POWER AMPS

IS

~

RIGHT

FIGURE 1_ Typical Connection Diagram
1-262

O.~

10 F

TLlH/10789-18

Applications Information
MINIMUM LOAD IMPEDANCE

cV+

The LMC1992 employs emitter-follower buffers at pins 8
and 22 (SELECT OUT), 13 and 14 (LEFT FRONT and
REAR OUTPUTs), and 16 and 17 (RIGHT FRONT-andREAR OUTPUTs) that buffer output signals. Typical bias
current of 1 mA is used for the SELECT OUTPUT buffers
and 350 p.A for the LEFT-and-RIGHT, FRONT-and-REAR
OUTPUT buffers.

10kA

I
10~f·L~

Rl
50 kA

10kA

-:.!:-

The Electrical Specifications table lists a maximum input signal of 2.3 Vrms (3.25 Vpeakl for 1 % THO at the SELECT
OUT pins. This distortion level is achieved when the minimum ac load impedance seen by the SELECT OUT pin is
3.25 kO (3.25V/1 mA). For the LEFT-and-RIGHT, FRONTand-REAR OUTPUTs, the typical maximum output is 1.2
Vrms (1.55 VpeaiJ. Therefore, the minimum load impedance
is 4.43 kO (1.55 V 10.35 mA). Trying to use a lower impedance results in a clipped output signal. Therefore, the
chance of clipping can be greatly reduced and much lower
distortion levels can be achieved by using load impedances
that are an order of magnitude higher than shown here.

O'I~f~4:

Input 'V
Signal

I

Pln4

-

TUH/l07B9-20

FIGURE 2. Input Bias Network
To allow for variations and part tolerances, 10 kO is a good
choice for this minimum dc load impedance.

INPUT IMPEDANCE
For ac coupled input signals the input impedance value is
determined by bias resistor R1, as shown in F/{//Jre 2. A
directly coupled input signal will see an emitter follower's
nominal input impedance of 2 MO.
The SELECT IN pins have an input impedance that varies
with the BASS and TREBLE control settings. The input impedance is 96 kO at dc and 27 kO at 1 kHz when the controls are set at 0 dB. Minimum input impedance of 28 kO at
dc and 24 kO at 1 kHz occurs when maximum boost is
selected. At 10 kHz the minimum input impedance, with the
tone controls flat, is 8 kO and, with the tone controls at
maximum boost, is 3 kO.

For applications that require dc coupling and the INPUTs
biased to V+ 12, the minimum load impedance will differ
from that detailed in the above discussion. The emitter followers may be potentially operating at high currents because there is a dc voltage V+ 12 - 0.7V at the SELECT
OUT pins; dc resistance to ground will result in increased
current flow. Latch-up may occur if the total emitter current
exceeds 5 mAo This current is a combination of the emitter
follower's 1 mA current source and 4 mA drawn by the external load. Therefore, to prevent this possibility, the minimum dc load impedance should be
Vpeak + (V+ 12 - 0.7V)
4mA
= 16380

STEREO SIGNAL INPUTS
When operating with a single supply voltage, the stereo signal inputs must be dc biased to one-half of the supply voltage, as shown in Figure 2. As an example, with a supply
voltage of 8V, all signal sources should have a dc bias of
4V. The maximum input signal level of 6.5 V p•p (for 1 %
THO) would then swing from 0.75V to 7.25V. Input-ta-input
crosstalk can be minimized by using a separate dc bias circuit for each ster~ ilJPut pair.

Vpeak = 3.25V
V+ = 8V
To allow for variations and part tolerances, 2.0 kO is a good
choice for this minimum dc load impedance.

EXTERNAL SIGNAL PROCESSING

When dc coupling is used at the LEFT-and-RIGHT, FRONTand-REAR OUTPUTs, the output emitter followers will be
operating at a nominal dc voltage of V+ 12 - 2(0.7V).
Latch-up may occur if the total emitter current exceeds
1 mAo This current is a combination of the emitter follower's
0.35 mA current source and 0.65 mA drawn by the external
load. Therefore, to prevent this possibility, the minimum dc
load impedance should be
Vpeak + (V+ 12 - 2(0.7V»
0.65mA
= 9kO

The signal present at the selected input will be available at
the SELECT OUT pins 8 (left) and 22 (right). The dc bias
voltage at those pins will be one base-emitter voltage, approximately 0.7 Vdc, below the source because of the internal emitter follower. Therefore, if the selected input has a
bias of 4.0 Vde the dc component at pins 8 and 22 will be
about 3.3 Vde.
The LMC1992's SELECT OUT emitter followers allow additional signal sources using emitter follower outputs (such as
multiple LMC1992s) to be "wired-ORed" together. When
this feature is in use, the input channel of the LMC1992 not
in use should be set to "open" input codes 01 OOOXXOOOO or
01000XX011X.

Vpeak = 3.25V
V+ = 8V

1-263

Applications Information (Continued)
CLOCK
I'P CONTROLLER t-:S::E=:RI~AL'-D~A:':TA~-""'---'

--.••

LMC1992
FUNCTIONS

••
•••
•••
••

SELECT

•

TONE CONTROL
BASS - TREBL& '

Nlc

._--------.SELECT OUT

"

••

8

TUH/10789-1,9

,FIGURE 3. System Block D!agram Showing Inc,uslon of'DNRGD NoiSe
Recluctlcm (LM1894) .nd Equallze~ (LMC835) (One Channel Only-~MC1992)
The SELECT OUT pins (8 and 22) enable greater system
design flexibility by providing a means to implement an ex·
temal processing loop. This loop can be used for noise reduction circuits such as DNA (lM1894) or mulit·band graph.
ic equalizers (lMC835). It is important to ensure that if both
are used, the noise reduction circuitry precede the equaliza·
tion circuits. I=ailure to do so will result in improper operation
of the noise reduction c!rcuits. The system shown in Figure
3 utilizes the external loop to include DNA and a multl·band
equaliz~r.
'

The typical tone control response shown in the Typical Per'
formance Curves were' generated with C2 = C3 ='
0.0082 j£F and show the response for each step. When
modifying'the tone coritrol response it is important to note
that the ratio of C3 and C2 sets the mid·frequency gain.
Symmetrical tone response is achieved when C2 = C3.
However, with C2 = 2(C3) and the tone controls sat to
"flat", the frequency response will be flat ,at 20 Hz and 20
kHz, and + 6 dB at 1 kHz.
The frequency where a tone control begins to deviate from
a flat response will be referred to as the tum-over freQuen.
cy. With C = C2 = C3, the lMC1992's treble tum·over
frequency is nominally

AUDIO MUTE

A mute function with attenuation' of 100 dB is possible with
the volume control set to .,..80 dB and, the INPUT select
code sat to 01000XXOOOO (open circuit). ,

In =

TONE CONTROL RESPONSE

2'ITC(14.2 kO)

The base 'turn-over frequency is nominally

Base and treble tone controls are included in'the lMC1992.
The tone Controls use just two external capacitors for each
stereo channel. Each has a comer frequencY determined by
the value of C2 and C3 (Fl{}ure 4) and internal resistors in
the feedback loop of the internal tone amplifier. The maxi~
mum amplitude boost or cut is determined by the data sent
to the lMC1992 (see Table I).

f

1

_

BT - 2'ITC(27.7 kO)

when maximum boost is chosen. The inflection points ,(the
frequencies where the' boost or cut is within 3 dB of ,the final
value) are for treble and bass
'

,

ITI =
f

1·264

1
2'ITC(2.3 kO)

_
1
Bl - 2'ITC(164.1 kO)

Applications Information (Continued)
C2
9(21)
IN

SERIAL COMMUNICATION INTERFACE

C3
0.0082,1&F
12(18)
11 (19)
OUT

0.0082,1&F
10(20)

F/{/ure 5 shows the LMC1992's timing diagram for its three
wire MICROWIRE interface. A controller's data stream can
be any length; once the correct device address is received
by the LMC1992, any number of data bits cen be sent; the
last nine bits occurring before "i:iiiAB[E goes high are used
by the LMC1992. The first two bits in a valid data stream are
decoded and used as device address bits. The LMC1992
uses a unique address of 1,0. The LMC1992 will not respond to information on the DATA line if any other address
is used. This allows other MICROWIRE serially programmable devices to share the same three-wire communication
bus. When ENABLE goes high, any further serial data is
ignored and the contents of the shift register is transferred
to the data latches. Only when information is received by
the data latches do any function or setting changes take
place. The first three of nine bits, select one of the
LMC1992s functions. The remaining six bits set the selected function to the desired value or position.
A data bit is accepted as valid and clocked into an internal
shift register on each rising edge of the signal appearing at
the LMC1992s CLOCK input pin. Proper data interpretation
and operation is ensured when EIiiABLE makes its falling
transition during the time when CLOCK is low. Erroneous
operation will result if the"i:iiiAB[E signal makes its falling
transition at any other time.

2.6 ko. 11.4 ko. 2.6 ko.
Treble
116.4ko.

Bass 116.4 ko.
509.2 ko.

Volume

V+/2
TUHI10789-22

FIGURE 4. The Tone Control Amplifier
Increasing the values of C2 and C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Curves will shift left
when C2 and C3 are increased and shift right when C2 and
C3 are decreased. With C2 = C3 = 0.0082, 2 dB steps are
achieved at 100Hz and 10kHz. Changing C2 and C3 to
0.01 p.F shifts the 2 dB per step frequency to 72 Hz and 8.3
kHz. If the tone control capacitors' size is decreased these
frequencies will increase. With C2 = C3 = 0.0068 p.F the 2
dB steps take place at 130 Hz and 11.2 kHz.
FADER FUNCTION
The four fader functions are all independently adjustable
and therefore no balance control is needed. Emulating a
balance control is accomplished through software by simUltaneously changing a channel's front and rear faders by
equal amounts. To satisfy normal balance requirements the
faders have an attenuation range of 40 dB.

CLOCK

DATA

I

DON'T CAREl

MSB

o

A2

I

LSB

Al

AO

os

D4

D3

D2

Dl

DO '

I

I

DON'T CARE

•

ENABLE

CHIP SELECT
ADDRESS

FUNCTION ADDRESS

DATA WORD

TUH/l0789-21

Note 1: Negative transRion on ~ cleers previous address. Clock must be low during transition.
Note 2: Additional don't care states may be inserted here lor eese 01 programming. (Optional.)
Note 3: PosRive transition on ENABLE latches in new data il the LMC1992 has been addressed. Clock can eRher be high or low during transition.

FIGURE 5. Clocking Data into the Standard MICROWIRE Interface
(Minimum Number of Bits In Data Stream)

1-265

Applications Information

(Continued)

TABLE I., Programming Codes for LMC1992
Address
A2
A1
. AD

Function
' Left Rear Fader

Data
D3
. D2

D1

DO

'MSB

N

N

N

LSB

-40 dB = XOOOOO
-20 dB = X01010
OdB = X1010X

D5

D4

X'·

·Values

1

1

1

1

1

0

Right Rear Fader

X

. MSB

N

N

N

LSB

-40 dB = XOOOOO
-20 dB = X01010
OdB = X1010X

1

0

1

Left Front Fader

X

MSB

N

N

N

LSB

-40 dB = XOOOOO
- 20 dB = X01010
OdS = X1010X

X

MSB

N

N

N

LSB

-40 dB = XOOOOO
-20 dB = X01010
OdB = X1010X

MSB

N

N

N

N

LSB

-80 dB = 000000
-40 dB =010100
OdB = 10100X

X

X

MSB

N

N

LSB

-12dB = XXOOOO
FLAT = XX0110
+12dB = XX1100

"

1

0

0

Right Front Fader

0

1

1

Volume

0

1

0

Treble.
"

0

0

1

Bass

X

X

MSB

III

N

LSB

-12dB = XXOOOO
FLAT = XX0110
+12dB = XX1100

0

0

0

Input Select

X

X

0

MSB

N

LSB

OPEN = XXOOOO
INPUT1 = XXOO01
INPUT2 = XX0010
INPUT3 = XX0011
INPUT4 = XX0100

Note 1: All attenualors 2 dB/step.
Note 2: Tone controls 2 dB/step

@

100 Hz and 10 kHz.

Note 3: Use of data that deviates from the values shown In the table may resuR in erroneous results.

SERIAL DATA FORMAT
Table I displays the required data format needed by the
LMC1992. Not shown is the 2-bit device address (10);
These two bits of information must precede the final nina.:
bits used as the data word. The. first three of these nine bits
is the function address.
The VOLUME, TONE, and FADER controls are deSigned to
increment their settings (in 2 dB steps) as the control data is
incremented by one LSB. Disregarding the device address
and the function address, the VOLUME input code increases from 000000 (-80 dB) to 10100X (0 dB). The TONE

controls' input code increases from XXOOOO (-12 dB) to
XX0110 (0 dB) to XX1100 (+12 dB). The code for the FADERs statts from XOOOOO (-;40 dB) and goes to X1010X
(0 dB).
The table shows that VOLUME is the only function that uses
all six bits to choose that function's setting. The remah'1ing
functions use less. than six bits; the unused bits are shown
as "X"s ("don't care';). While these "don't care" bits have
no effect on their respective function, the LMC1992 must
receive them for proper operation. If neglected, erroneous
or unknown results will occur.

,

Applications Information (Continued)
DATA TRANSFER EXAMPLE

DATA TRANSFER ROUTINE 2

The following routines, based on the flowchart shown in Figure 6, are examples of COPSTM microcontroller instruction
code that can be used to control the LMC1992 (see National Semiconductor's COPS Microcontrollers Databook for
more information). These routines arbitrarily select COPS
register 0 for 1/0 purposes. When these routines are entered, it is assumed that chip select is high, SK (clock) is
low, and SO (data) is low. These routines exit with chip select high and SK and SO low. Output port GO is arbitrarily
chosen to send the chip select signal to the LMC1992.
The 11 data bits needed to control the LMC1992 are assumed to be in the 4-bit registers, 13-15, with the 4 MSBs
in register 13. With this configuration there is an extra bit for
a data stream that is 12 bits long. As previously mentioned,
there can be any number of extra bits between the device
address and the function address.

This routine performs the same function as routine 1 while
preserving the contents of the data registers. This routine
takes only 21 ROM memory locations.

OUT1:

This general purpose routine handles all the overhead except loading data into registers 13-15. It sends the data
according to the conditions discussed above. The data will
be lost at the conclusion of the routine. This routine consumes only 17 ROM memory locations.

SEND:

LBI

0,13

SC
OGI

14

LEI

8

LD
XAS
XIS
JP
RC
OGI
LEI
RET

0,13

SC
OGI

14

LEI

8

JP
SEND1: XAS
SEND2: LD
XIS
JP
XAS
RC

DATA TRANSFER ROUTINE 1

OUTl:

LBI

SEND2
;DATA TRANSMISSION LOOP
;TURN-ON CLOCK
SEND1

CLRA
NOP
XAS
OGI 15
LEI 0
RET

;POINT TO START OF DATA
;WORD
;SET C TO ENABLE SK CLOCK
;SELECT EXTERNAL DEVICE GO
;= 0
;ENABLE SHIFT REGISTER
; OUTPUT

;POINT TO START OF DATA
;WORD
;SET C TO ENABLE SK CLOCK
;SELECT EXTERNAL DEVICE
GO ;=0
;ENABLE SHIFT REGISTER
;OUTPUT

;SEND LAST DATA
;WAIT 4 CYCLES - DATA
;GOING OUT
;TURN SK CLOCK OFF
;DE-SELECT DEVICE
;SET SO TO 0

;DATA TRANSMISSION LOOP
;TURN-ON CLOCK
SEND
15
0

;DE-SELECT EXTERNAL
DEVICE
;SET SO TO 0

II

1-267

cq

8l
,...

r-------------------------------------------------------------------------------------~

Applications Information (Continued)

,,';;

(,)

~

'"
"-'--"--'- SETUP INITIAL CONDIllONS ,
(clock "low"; ~nable "high") , _

---,-,--- ENABLE LMC1992's IIICROWlRE
INTERFACE
'

, SELECT lllC1992
WITH LEADING
"10" ADDRESS

FUNCTION ADDRESS AND
DATA WORD
'
OUTPUT lOOP (9BITS)

no

- - - DISABLE lIIC1992's IIICROWIRE
INTERFACE
TUHII0789-23

FIGURE 6. General Data Transmission Flowchart to Send Serial Data
to the LMC1992's MICROWIRE Compatible Dlgltallnputa

1·268

tflNational Semiconductor

Audio Op Amp
Selection Guide

Part
Number

Description
Precision
OpAmp

Input
Referred
Noise
Voitage

THO

Slew
Rate

GBW

PSRR

Supply
Range

Singlel
Duall
Quad

Package
(Pin
Count)

LM833

Dual Audio Amplifier

4.5 nV/;'RZ

0.002%

7V/p.s

15 MHz

100dB

±18V

Dual

50(8).
Dip(8).

LM837

Quad Audio Amplifier

4.5 nVl;'RZ

0.0015%

10Vlp.s

25 MHz

100dB

±18V

Quad

SO(14) •.
Dip(14)

LF347

Wide Bandwidth
JFET

20nVl;'RZ

0.02%

13V1p.s

4MHz

100dB

±18V

Quad

Dip(14).
SO(14)

LF351

Wide Bandwidth
JFET

25nVl;'RZ

0.02%

13V/p.s

4MHz

100dB

±18V

Single

50(8).
Dip(8)

LF353

Dual LF351

16nVl;'RZ

0.02%

13V/p.s

4 MHz

100 dB

±18V

Duai·

50(14).
Dip(14)

LF411

Low Offset. Low Drift
JFET

25nVl;'RZ

0.02%

15V1p.s

3 MHz

100 dB

±18V

Single

Dlp(8)

LF412

Dual LF411

25nVl;'RZ

0.02%

15V/p.s

3MHz

100 dB

±18V

Dual

Dip(8)

LF444

Low Power JFET
Quad

35 nVl;'RZ

0.02%

1V/p.s

1 MHz

100dB

±18V

Quad

Dip(14).
SO(14)

LM6142

High-Speed/Low
Power Dual

16 nVl;'RZ

0.03%

15V/p.s

10MHz

87dB

+1.8Vto24V

Dual

Dip(8).
50(8)

LM6144

High-Speed/LowPower Quad

16 nVl;'RZ

0.03%

15V/p.s

10MHz

87 dB

+1.8Vto24V

Quad

Dip(14).
SO(14)

II

1-269

~

!

t!lNational Semiconductor

.....

~

~

LM387/LM387A Low Noise Dual Preamplifier
General Description

Features'

The LM387 is a dual preamplifier for the amplification of low
level signals in applications requiring optimum noise performance. Each of the two amplifiers is completely independent. with an Internal power supply decoupler-regulator. providing 11.0 dB supply rejection and 60 dB channel separation. Other outstanding features include high gain (104 dB).
larg~ output voltage swing (Vee - 2V)p-p. and wide power
bandwidth (75 kHz. 20 Vp-p). The LM387A is a selected
version of the LM387 that has lower noise in a NAB tape
circUit. and can operate on a larger supply voltage. The
LM387 operates from a single supply across the wide range
of 9V to 30V. the LM387A operates on a supply of 9V to
40V.
The amplifiers are internally compensated for gains greater
than 10. The LN387. LM387A is available in an 8-lead dualin-linepackage. The LM387. LM387A .is biased like the
LM381. See AN-64 and AN-104.

•
•
•
•
•
•
•
•
•
•
•

1.0 P. V total input noise
Low noise
104 dB open loop
High gain
Single supply operation
9 to 30V
Wide supply range LM387
.
lM3,87A
,9 to 40V
110 dB
Power supply rejection'
Large output voltage swing (Vee - 2V)p-p
Wide bandwidth 15 MHz unity gain
Power bandwidth 75 kHz. 20 Vp-p
Internally compensated
Short circuit protected
Performance similar to LM381

Schematic and Connection Diagrams
Dual-In-Une Package

----I

.
.,

+'Im

I
I

,

-1100

-I•

I
I
'"

+IIIClI

.N•

I
I

v'"

OUTPUT (1)

DUTPUT(ZI

TL/HI7845-2

'-----+--t-014,51

"

Top View
Order Number LM3B7N or.LM387AN
See NS Package Number NOBE

TL/HI7845-1

Typical Applications
lOY

lOY

..,• ..---+-.JVo-.,.,..-..

...

'Ik

TL/H/7845-3

TL/H17845-4

FIGURE 1. Flat Gain Circuit (Ay = 1000)

FIGURE 2. NAB Tape Circuit
1-270

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the Netlonal Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
LM387
LM387A

Power Dissipation (Note 1)

O"Cto +70"C

Storage Temperature Range

-6S'C to + lS0'C

Lead Temperature (Soldering, 10 sec.)

+30V
+40V

Electrical Characteristics TA =

1.SW

Operating Temperature Range

2S'C, Vee = 14V, unless otherwise stated

Parameter

Conditions

Voltage Gain

Open Loop, f = 100 Hz

Supply Current

LM387, Vee 9V-30V, RL = 00
LM387A, Vee 9V-40V, RL = 00

Input Resistance
Positive Input
Negative Input

Typ

Min

Max

VIV

10
10

mA
mA

100
200

kO
kO

Input Current
Negative Input

O.S

Output Resistance

Open Loop

Output Current

Source
Sink

Output Voltage Swing

Peak-to-Peak

Units

160,000

SO

3.1

p.A

lS0

0

8
2

mA
mA

Vee- 2

V

lS

MHz

7S

kHz

Unity Gain Bandwidth
Large Signal Frequency
Response

260"C

20 Vp-p (Vee> 24V),
THD,;: 1%

Maximum Input Voltage

Linear Operation

Supply Rejection Ratio
Input Referred

f = 1 kHz

Channel Separation

f = 1 kHz

Total Harmonic Distortion

60 dB Gain, f = 1 kHz

0.1

O.S

%

Total Equivalent Input
Noise (Flat Gain Cricuit)

10 Hz-l0,OOO Hz
LM387 Figure 1

1.0

1.2

p.Vrms

300
110
40

mVrms
dB

60

dB

Output Noise NAB Tape
Unweighted
400
700
p.Vrms
Playback Circuit Gain of 37 dB
LM387AFigure2
Note 1: For operation in ambient temperatures above 25'C. the device must be derated based On a 150'C maximum'lunction temperature and a thermal reSistsnce
of 80'C/W Junction to ambient.

Typical Applications (Continued)
Two·Pole Fast Tum-oN NAB Tape Preamplifier

n"~
["+
~

Frequency Response of NAB
Circuit of Figure 2

24V

LM3I1

..

I

Ii
II

14.51

~.~
11k

46

"-

4D
31

3D
21
ZD

o.ojjpF

II
,~.

NAB PlAYBACK

r'\.

II
ID

a
11k

I'.

I"'

ID IDD • •11 I. Zk Ik laka.
FREIlUENCY 1Hz)
TLlH/7845-6

240

240,
~

+

20pF ...........

~

1.3k~

+

20 "F ..........

T

":::TL/H17845-5

1-271

,

Typical Performance Characteristics

~,

Large SignafFrequency
A~aln

Vccvslcc

13

~T-~~~~'-~'

12

I-+-+-+-t-lr-r--t-;

128

111 ~
100
10

11 I-+-+-+-t-l~r--t-;

i

ID~~~~~~~

;;;

.2

!!
c

ji

"'~

oo
10

..

III

r---

""

~~N r---

'\.
'HABE

~

,

a

.,

- : I
10 Ii
185 ..

1~D

11
•

"

110

1.

131
~ Iii
~ Iii
110'
10. G.lM 1M I .

m

~

II

i..

l'

= !:

;

\
\
\

~

I'

o

UII.! '''II.! lDO 'H. 1M
111M
FREDUENCY (H.,

FREDUENCY (Hri

SUPl'LY VOLTAGE M

140 dB
4.5 nV/./Hz
7 V/p.s (typ)
5 V/p.s (min)
15 MHz (typ)
10 MHz (min)
120 kHz
0.002%
0.3 mV
60"

• High gain bandwidth product
•
•
•
•

Wide power bandwidth
Low distortion
Low offset voltage
Large phase margin

Schematic Diagram (1/2LM833)

Connection Diagram

+~~8____~~________~__~~__~__~~__-1~

DurA

+Vcc

-INA

OUT a

+INA~--"'"

-INa

380

-VEE

~--""'+lNa

TlIH/5218-2

Order Number LM833M or LM833N
See NS Package Number
M08Aor N08E

TlIH/5218-1

Typical Application RIM Preamp

=-ir T-~
33 ""

I
I
IL":'___ -'I

470

.n
":'

16k

390

1"'110""
TL/H/5218-3

A.,
En

~

35 dB

f

~

O.33,.V

A Weighted

SIN

~

90 dB

~

1 kHz

A Weighted. VIN
@f~lkHz

1-274

~

10 mV

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclficatlons_
Supply Voltage .

36V

Vee-VEE

Differential Input Voltage (Note 1) VIO
Input Voltage Range (Note 1)
VIC
Power Dissipation (Note 2)

±30V
±15V

Operating Temperature Range

TOPR

-40 - 85°C

TSTG

-60 - 15O"C

DC Electrical Characteristics (TA =

=

1600V

±15V)

Conditions

=

21fioC
220"C

ESD tolerance (Note 3)

25°C, Vs

Parameter

260"C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

500mW

Po

Storage Temperature Range

Symbol

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

Min

Typ

Max

Unlta

Vas

Input Offset Voltage

0.3

5

mV

los

Input Offset Current

10

200

nA

Ie

Input Bias Current

500

1000

Av

Voltage Gain

RL

=

2kO, Va

YOM

Output Voltage Swing

RL
RL

=
=

10kO
2kO

Rs

100

=

±10V

VCM

Input Common-Mode Range

CMRR

Common-Mode Rejection Ratio

VIN

PSRR

Power Supply Rejection Ratio

Vs

=. ±12V
= 15-5V, -15- -5V

IQ

Supply Current

Va

=

Symbol

Parameter
Slew Rate

RL

GBW

Gain Bandwidth Product

f

=

dB

±12
±10

±13.5
±13.4

V
V

±12

±14.0

V

80

100

dB

80

100

dB

5

±15V, RL

Conditions

SR

110

OV, Both Amps

AC Electrical Characteristics (TA = 25°C, Vs =

=

nA

90

8

mA

2 kO)

Min

Typ

2kO

5

7

VI",s

100kHz

10

15

MHz

=

Design Electrical Characteristics (TA = 25°C, Vs =

Max

Units

±15V)

The following parameters are not tested or guaranteed.
Symbol

Parameter

Conditions

tNos/Il.T

Average Temperature Coefficient
of Input Offset Voltage

THO

Distortion

RL = 2 kO, f = 20-20 kHz
VOUT = 3 Vrms, Av = 1

en

Input Referred Noise Voltage

Rs

=

=

1000, f

=

in

Input Referred Noise Current

f

PBW

Power Bandwidth

Va = 27 Vpp, RL

fu

Unity Gain Frequency

Open Loop

M

Phase Margin

Open Loop

Input Referred Cross Talk

f

Note 1:

=

1 kHz

1 kHz

20-20 kHz

If supply voltage Is less than ± 15V. H is equal to supply voltage.

Note 2: This is the pennissible value al TA ,;; 85·C.
Note 3: Human body model, 1.5 kll in series with 100 pF.

1-275

=

2 kO, THO

s:

1%

Typ

Units

2

p.VI"C

0.002

%

4.5

nV/JHz

0.7

pAlJHz

120

kHz

9

MHz

60

deg

-120

dB

II

Typical Performance Characteristics

flOO

Maximum Power
DlssipaUon
vs Ambient Temperature

.

TOO

i!j800

.i

,ijg600

iiII!

is

-,

,

~

0
-50

50
100
TEMPERATURE I'C)

600

......

500
400

-

......IB~~; ::-;;

i"""'"

izoo

i!! 200

100

100

o

o

:::>

l

7
6

,.

400

..

£

5.

10
15
SUPPLY VOLTAGE I ± V)

TL/H/521B-5

Supply Current vs
Supply Voltage
TA=25'C
RL=" --

io-.

>- 300

-50 -25 0 25 50 75 100125
TEMPERATURE I'C)

-

TA=25'C

,i 600
...>-z 500

..

150

Input Blais Current va
Supply Voltage
.

700

II:
II:

TL/H/~lB-4

10

BOO

Va= ±15V

"300

:::>

:E
:::>200

I

Input Bias Current vs .
600 Ambient Temperature

TUH/S21B-6

DC Voltage Gain
vs Supply Voltage

DC Voltage Gain
vs Ambient Temperature
120

~

......

-

120
Va= ±15V
RL=2 kD

r- ~-

..

!

TA=25'C
RL=2 kD

110

~

~

..

--

i,....-o ~

z

100

g

90

1

o

60

o

10
15
SUPPLY VOLTAGE I ± V)

20

60

-50 -25 0 25 50 75 100 125
TEMPERATURE I'C)

TUH/521B-7

100

-

1000.

!

-I..tAS~-

'-.

"

~'

".'"11

1

-60 ~

.

- 90-0

III

-120111
.!!

~

o

~

!.

-150
-160

10 100 ·lk 10k lOOk 1M 10M
FREOUENCY 1Hz)

..'"

20

II:
:c

I
z
c
III
z

:i

10

i ' .....

1A=25'C
1=100 kHz

~

t;

:::>

Gain Bandwidth
vs Supply Voltage
30

Va= ±15V
1=100 kHz

20

.. TL/H/521B-9

Gain Bandwidth Product
vs Ambient Temperature
30

Vs= ±15V
R1L=2rD -30

1'-. GAIN

10
15
SUPPLY VOLTAGE.I ± V)

TUH/521B-B

Voltage Gain & Phase
vs Frequency
120

5

!. 20

r- r--

~- ~

.

I
III

z

10

:i
o

o
-50 -25 0 25 50 75 100 125
TEMPERATURE I'C)

TUH/521B-l0

TL/H/521B-l1

1-276

,
5

10
15
SUPPLY VOLTAGE I ± V)

20

TL/H/521B-12

Typical Performance Characteristics (Continued)
Slew Rate va
Ambient Temperature

.
~
~

w

li
II:

.
~

10
9
8
7
6

Slew Rate va
Supply Voltage

--sq.
I L

Vs= ±15V
RL=2 kllAv=l

F1LL1N~-

f-

~
~

5
4 ..n.~.
Yo
3
2k
2
1
0
-50 -25 0 25 50 75 100 125
TEMPERATURE (OCI

i

..
~

.,..

10
9
8
7
6
5

TA_25°C
RL=2kll
Av -1'

30

~

J,
FALLING

-lt1

J'L~'

4
3
2
1
0

,.~

...'"
:::>

t=

S

10

15

~

~

5

~
§:
...
~

0
-5 Io!o.

"'"

-10
-15

10
15
SUPPLY VOLTAGE (± VI

15
SUPPlY VOLTAGE ( ± VI

Vs=±15V
RL=10 kll

12

'"

11

100
iii'

..

~

II:

:IE

80

I-

40

!-

20

I

-

60

-

0
100

T

21<

.,..
lk

-

•

-

-

10k lOOk 1M
FREQUENCY (Hzl

lOOk
1M
FREQUENCY (Hzl

~Yo~

10M

PSRR vs Frequency
120

-- -

+PSRR
100
iii'
II:
II:

Ie

80

f'

TL/H/5218-17

M

Vs=±15V

,

,-PSRR
60

40

~

20

'-"W

RL=2kll -

Yo-

"-

I

\ ...

10k

o,
100

lk

10k lOOk 1M
FREOUENCY (Hzl

10M

TUH/5218-18

Distortion vs Frequency

:

V1=1V1'rns

lk

TL/H/5218-15

~

1

~2

\
\

0
100

2D

10
-50 -25 0 25 50 75 100 125
TEMPERATURE (OCI

20

I I

15V

I

-YoM

13

CMR va Frequency
VS-

10
5

10

TL/H/5218-16

120

...:::>

Maximum
Output Voltage va
Ambient Temperature

14

...

-20
5

15

co

:::>

"r----. ....

,.'"

TL/H/5218-14

20

~

20

~

.,..

5

Maximum
Output Voltage va
Supply Voltage
..",.

w

"-

Vs=±15V
RL=2kll
THOsl"

25

...~
!;

Yo

21<

TL/H/5218-13

TA_25°C
15 RL=10kll

Power Bandwidth

+..
1

lz

0.1

,

•

,i...'"
'"

,..'

is 0.01

2k

111
Yo=3 Vrms

1

.I
Yo=l Vrms

0.001
10M

Yo

"\;.

10

100

lk
10k
FREQUENCY (Hzl

TLlH/5218-19

lOOk

TUH/5218-20

1-277

•

~

~

Typical Performance Characteristics (Continued)
Spot Noise Current

Spot Noise Voltalle
10 vs Frequency

10

LM833f

1'A=~"C

Va= ±15V

....'

.

100

1'A=25"C
Vs= ±15V

~ N'
z~

Iil~

iB
Ii

0.5

iiE

0.2
0.1

1
lD

~:~requency

100

lk

10k

lOOk

1• •1
U--L-.......-'--'-'--'-'--'-......

lD

100

lk

--

'"
DIN~UDI~~

lDk

lDDk

~

,

~
"A'~W
~""n
LM833

0.1
100

FREQUENCY (Hz)

T.\=25"C
Va=±15V
lk

10k

lOOk

1M

SOURCE RESISTANCE (0)

TL/H/5218-22

TUH/5218-21

Noninvertlng Amp

i

7~_'~
~

1-t+t-1H++-H-++-I

FREDUENCY (Hz)

.,

Input Referred Noise Voltage
vs SOurce Resistance

TUH/5218-23

Nonlnverting Amp

!!

I

lOUT

i

IN

I

I :

nME (D.2 ,../DIY)

TIME (2 ,../DIY)
TUH/5218-24

TLlH/5218-25

Inverting A~p

nME (2 ,../DIY)
TUH/5218-28

Application Hints
Capacitive loads greater than 50 pF must be isolated from
the output. The most straightforward way to do this is to put
a resistor in series with the output. This resistor will also
prevent excess power dissipation if the output is accidentally shorted.

The LM833 is a high speed op amp with excellent phase
margin and stability. Capacitive loads up to 50 pF will cause
little change in the phase characteristics of the amplifiers
and are therefore allowable.

1-278

Noise Measurement Circuit
Complete shielding is required to prevent induced pick up from external
sources. Always check with oscUloscope lor power line noise.

+Vct: -Va;

470

"
7'

AVERAGE RESPONOING
At VOLT METER

lk

390

lk

~------R~--~Y---P------~I ~'-------------------F-u-r-AM-~-.~Y-d-B+-~--"-------------------J
35 dB, 1=1 kHz
TL/H/5218-27

Total Gain: 115 dB @f = 1 kHz
Input Referred Noise Voltage: en = VO/560,OOO (V)

RIAA Preamp Voltage Gain, RIAA
Deviation va Frequency
50

Flat Amp Voltage Gain va
Frequency
90 Va -0 dB.

VJN-l0mV

35.0 dB, 11kHz

80

!z

~

20

li

~

10

:lI 50

~

~

o

f: HIIII
20

0

'"

11111111 1111I1 1

100
lk
FREQUENCY (Hz)

80. odB, 1-1 kHz

70
60

~

30
20

10

10k 20

100
lk
10k
FREQUENCY 1Hz}

lOOk
TUH/5218-29

TL/H/5218-28

1-279

•

Typical Applications
NAB Preamp Voltage Gain
70 vs Frequency

NAB Preamp

'Iut-l0 mv
34.5 dB, I -1 kHz

60

!

50

~

30

~

Vo

40

0

20

>

Av = 34.5

10

F = 1 kHz

.En

= 0.38,.V

0

20

. A Weighted

200k

100 .

lk
FREQUENCY (Hz)

10k 20k
TUH/5218-31

200

+
47 pF
TL/H/5218-30

Adder/Subtracter

Balanced to Single Ended
Converter

Sine Wave Oscillator

Yl-"",."....,

R
V2 -"",.".....

Vo

V2-WIl---....
Vo

Vo
Y3-...,...,."....,

Vl-"",.".........

Vo = Vl-V2 .

Y4 -"""""...
Vo = VI + V2 - V3 - V4

TL/H/5218-33

TUH/5218-32

Second Order High Pass Filter
(Butterworth)

Second Order Low Pass Filter
(Butterworth)
Cl
0.022pF

Rl
11k

Vo
Vo

TUH/5218-36
TUH/5218-35

H Rl = R2 = R

HC1=C2=C

C2=£!2

R2 = 20 Rl
Illustration is 10

= 1 kHz

Illustration is 10

1·280

=

1 kHz

Typical Applications (Continued)
State Variable Filter
H2
10k
R2
10k

Cl

Rl

Cl
0.01 ~F

0.01~

16k

YLP

TL/H/5218-37

Illustration is fO - 1 kHz, Q - 10, Asp

- 1
AC/DC Converter
Cl
10 ~F

R5

20k
R2

R3

R4

20k

10k

20k

01
IS1588
YO-IYINI

02
IS1588

TUH/5218-38

2 Channel Panning Circuit (Pan Pot)

Line Driver

3.41Rl

H2

51k

Rl
15k

VI

Rl
15k

o.~~~...._

HI

HI

15k

15k

Rl

...._ ...

+--.... Vo

TUH/5218-39

TUH/5218-40

1-281

III

~

~

r----------------------------------------------------------------------------------------,
Typical Application (Continued)
Tone Control

1

1

IL

= 2'lTR2Cl , ILB = 2'lTR1Cl

It!

= 2'lTR5C2' IHB' = 2'lT(Rl +

1

V,

HI

BOOST -BASS-CUT
H2

HI

11k

1lI0II

11k

Cl
0.05 pi'

1
R5

+ 2R3)C2

Illustration Is:

It. =

32H~,f~ = 320Hz
'H =11 kHz, 'HB = 1.1 kHz

Cl
0.05 pi'

2OdB---....:
ltdB - - - - - - - - -....

R3
11k

..

3 dB -------+-~
H5
3.lk

C2
0.005""

v.
R4

500k
BOOST-TREBLE-CUT

-20 dB - - - - '
IL

TLlH/5218-41

Iu

'HB

'H
TL/H/5218-42

Balanced Input Mic Amp
If R2 = R5, R3 = R6, R4 = R7

V~"

(1 +~)~(V2-Vl)
Rl

R3

10 Band Graphic Equalizer

Illustration is!
R3
10k
VO = 101(V2 - VI)
ll1k
~.-~~--~~~
R4

V,

":'

HI
200

- -,

-

r
CUI

HI
10k

'"

I
v.

R5
10k

RI
ll1k

v,

3k

c.

r

v,
Cl

HI

R7
10k

I

VI

.".

L

TLlH/5218-43

fO(Hz)

C1

C2

R1

R2

32
64
125
250
500
1k
2k
4k
8k
16k

0.12p.F
0.056p.F
0.033p.F
0.015p.F
8200pF
3900pF
2000pF
1100pF
510pF
330pF

4.7p.F
3.3p.F
1.5p.F
0.82p.F
0.39p.F
0.22p.F
0.1p.F
0.056p.F
0.022p.F
0.012p.F

75kO
68kO
62kO
68kO
62kO
68kO
68kO
62kO
68kO
51kO

5000
5100
5100
4700
4(,00
4700
4700
4700
5100
5100

At volume 01 change

Q

= ± 12 dB
= 1.7

Reference: "AUDIO/RADIO HANDBOOK", National Semiconductor, 1980, Page 2-61

1·282

t!lNational Semiconductor

LM837 Low Noise Quad Operational Amplifier
General Description

Features

The LM837 is a quad operational amplifier designed for low
noise. high speed and wide bandwidth performance. It has a
new type of output stage which can drive a 6000 load, making it ideal for almost all digital audio, graphic equalizer, preamplifiers, and professional audio applications. Its high performance characteristics also make it suitable for instrumentation applications where low noise is the key consideration.
The LM837 is internally compensated for unity gain operation. It is pin compatible with most other standard quad op
amps and can therefore be used to upgrade existing systems with little or no change.

• High slew rate
• Wide gain bandwidth product
•
•
•
•
•
•

Power bandwidth
High output current
Excellent output drive performance
Low input noise voltage
Low total harmonic distortion
Low offset voltage

10 Vlp-s (typ)
8 V I p-s (min)
25 MHz (typ)
15 MHz (min)
200 kHz (typ)
±40mA
>6000
4.5 nV/.JHZ
0.0015%
0.3 mV

Schematic and Connection Diagrams
114 Quad

~-----------,----------------,--oV~

Dual·ln·Llne Package
OUTt

I -.....--....--~ OUT

-tNt
+INt

-:11-=::...1

Vee
+IN2-:-1~~

-IN2
OUT2
TL/H/9047-2

Top View

~

__

~~

________

~

__________

~

__

~

__

~V~

TLJH/9047 -1

1-283

Order Number LM837M or LM837N
See NS Package Number M14A or
N14A

•

~

(f)

'CD

....::E

r-----------------------------------------------------------------------------,
Absolute Maximum Ratings
, Soldering Information
Dual·ln-Une .package
Soldering (10 seconds)
260"C
Smail Outline Package
V~r Phase (60~nds) ,
215°C
Infrared (15 seConds)
220"C
ESD rating is to be determined.
See AN-450 "Surface' M6u~ting Methbd;'and Their Effect
on ProdiJct Reliability" for other methods of sOldering sur·
face mCiunt devices.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/DIstributors for availability and specifications.
Supply Voltage
VcclVee
±18V
Differential Input Voltage (NOte 1) VIO
±30V ~"
Common Mode Input Voltage
(Note 1)
±.15V
,1.2W(N)
Power Dissipation (Note 2)
830 mW(M)
, Operating Temperature Range
TOPR -40"C to'+ 85°C
Storage Temperature Range
TSTG -60"C to + 150"C

DC Electrical Characteristics TA =
Symbol

25°C, Vs = ±15V.

Parameter'

"

Condition

Min

Typ

Max

Units

5

mV

Vos

Input Offset Voltage

los

Input Offset Current

IB

Input Bias Current

Av

Large Signal Voltage Gain

RL = 2kO, Vol!JT =; ±10V

90"

110

YOM

Output Voltage Swing

RL = 2kO

±12

±13.5

RL = 6000

±10

±12.5

V

±12

±14.0

V

Rs = 50n

",

0.3
10

" ,2QQ

500

1000

nA
nA

I

dB
V

VeM

Common Mode Input Voltage

CMRR

Common Mode Rejection Ratio

VIN = ±12V

80

100

dB

PSRR

F'oWElr Supply Rejection Ratio

Vs = 15'''- 5, -15 - -5

80

100

dB

Is

Power Supply Current

RL =

QO,

Four Amps

10

15

mA

"

AC Electrical ,Characteristics TA =
Symbol

25°C,Vs ";"±15V

Parameter

Condition

SR

SlewR~te

RL = 6000

GBW

Gain Bandwidth Product

f

=

100 kHz, RL

Design Electrical Characteristics TA =
Symbol
PBW,

Typ

8

10

Vlp.s

15

25

MHz

6000

Max

Units

25°C, Vs =, ± 15V (Note 3)

Parameter
, PoWer Bandwidth

=

Min

Condition
V6 = 25 Vp_p, RL = 6000, THO

enl

Equivalent Input NoiSe Voltage

JISA, Rs = 1000

en2

Equivalent Input Noise Voltage

f =

in

Min

< 1%

Typ
200

Max

Units
kHz

0.5

p.V

1kHz

4.5

nV/,fHz

Equivalent Input Noise Current

f = 1 kHz

0.7

pAl,fHz

THO

Total Harmonic Distortion

Av = 1, VOUT = 3 Vrms,
f = 20 - 20 kHz, RL = 6000

0.0015

%

fu

Zero Cross Frequency

Open Loop

12

MHz

Phase Margin

Open Loop

45

deg

Input-Referred Crosstalk '

f=20-20kHz

m
AVos/AT

Average TC of Input Offset Voltage

-120

dB

2

p.VloC

Note 1: Unless otherwise specified the absolute maximum Input voltage is equal to the power supply voltage.
Note 2: For operalion at ambient lemperalures above 25'C. Ihe device must be deraled based on a 150'C maximum junction temperature and a thermal
resistance. junction to ambien~ as follows: LM837N, 9O'C/W; LM837M. 15O'C/W.
Note 3: The following parameters are not tested or guarsnteed.

1-264

Detailed Schematic
1/4 QUAD

OUT

ANOlHER
CH •

...-----...,

TL/H/9047 -3

•
1-285

r-

C")

I

r------------------------------------------------------------------------------------------,
Typical Performance Characteristics

...I

Normalized Input Bias Current
vs Supply Voltage
'

Maximum Power Dissipation vs
Ambient Temperature
2.0

1.5

I

U
1.3
1.2

o.a
Q.6

Q.6

25 50 75 100 125 150

Q.5

o

10

15

15

TA=25OC

14

RL=-

13
12

Four Amps

10

,.

-~

-50 -2S 0

20

Positive Current Limit
20

VS=tI5V

Vs Lt\51

~=-

Four Amps

15

. .. -

11

10

25 50 75 100 125 150

AIIB1ENT TEMPERATURE (OC)

Supply Currentvs
Ambient Temperature

13
12

-

11

15

SUPPLY VOLTAGE (tV)

Supply Current vs
Supply Voltage

-- . ..

~

.....

o.a
o:J

TEMPERATURE (OC)

14

1.1
1.0
0.9

0.7
D.5

I

VS=tI5V

1.3
1.2

-- - -

0.9

I
-50 -2S 0

.

U)

"'

Ypkg

o

TA=25"C

1.1

NPkg

Normalized Input Bias Current
va Ambient Temperature
1.5
1.4

r-

I'-~

10

I

""-~
JOC

I

,

;-boc

)-' I
-Joe
'j

I

5

o

10

15

'SUPPLY VOLTAGE (V)

Negative Current Limit
-20

I

I

.... r--10

r..,
~-i
250C

o

o

\~5OC

10

5
ii!

-5

'"

Maximum Output Voltage
vs Supply Voltage

Maximum Output Voltage
va Supply Voltage

~=2kA

14

14~~~~~!j
.VOIIA)(

13 ~

12~+-+-+-+-+-+-~1

13
12

111-+-+-+-+-+-+-+--1

11

-12

~ -13I-F-I=*--,!VOIIAX~~;j;-;;t--j

- -14 1-+-+-+-+-+-+-+--1
-15

I--.l..-J-..J..--'--'--'-..J....,..J

-50 -25 0

25 50 75 100 125 150

AIIBENT TEMPERATURE (OC)

.....

10

15

.

-s

VS=tI5V.

20

o

r-

..........

.......

10

15

20

SUPPLY VOLTAGE (tV)

Power Bandwidth

~=6OOA

+voIWI:

'"

.........

-10

-20

o

.......
./

-15

Maximum Output Voltage
vs Ambient Temperature
15

15 Vs=tI5V. RL=2kA

'"

0

10

SUPPLY VOLTAGE (tV)

Maximum Output Voltage
vs Ambient Temperature

I -11 1-+-+-+-+-+-+-+--1
f--f-t-+-+--+-+-t--I

~

..........
...........

OUTPUT SINK CURRENT (rnA)

~~

l
~~

./

...
...

TA=25OC
RL=6OOA

15

./

-15

10 20 30 40 50 60 70 80 90 100

20

.,

TA=25OC

-10

-20

10 20 30 40 50 60 70 80, 90 100
OUTPUT SOURCE CURRENT (rnA)

15

l
~~

o

AIIBIENT TEMPERATURE (OC)

20

Vs Lt\5V

I

o

5
-50 -25 0 25 50 75 100 125 150

20

Vs=t 15V.RL= 600A
TA-25OC.1HO 1 MO to
Typ
(Note 5)

Conditions

Input Offset Voltage

TCVos

s: TJ s:

-40"C

-65°C to + 150"C
150"C

5.0V DC Electrical Characteristics

Parameter

s: 24V

50mA
260"C

Unless otherwise specified, a" limits guaranteed for TJ = 25°C, V+
V + 12. Boldface limits apply at the temperature extremes.

Symbol

1.8V i. V+

Vmin
0.1

0.1

0.133

0.133

4.86

4.86

4.80

4.80

V
max
V
min

5.0V DC Electrical Characteristics
Unless Otherwise Specified, All limits Guaranteed for TJ = 25'C, V+ = 5.0V, V- = OV, VCM = Vo = V+ 12 and RL >. 1 MO
to V+ /2. Boldface Ilmlia apply at the temperature extremes. (Continued)

Symbol

Isc

Parameter

Output Short
Circuit Current
LM6142

Sourcing

13

Sinking

Isc

Output Short
Circuit Current
LM6144

24

Sourcing

8

Sinking

Is

Supply Current

LM6144AI
LM6142AI
Limit
(Note 6)

Typ
(Note 5)

Conditions

22

Per Amplifier

650

LM6144BI
LM6142BI
Limit
(Note 6)

10

8

4.9

4

3S

35

10

10

5.3

5.3

3S

35

6

6

3

3

3S

3S

8

8

4

4

35

35

Units

mA
min
mA
max
mA
min

rnA
max
mA
min
mA
max
mA
min
mA
max

800

800

IJoA

880

880

max

5.0V AC Electrical Characteristics
Unless Otherwise Specified, All limits Guaranteed for TJ = 25'C, V+ = 5.0V, V- = OV, VCM = Vo = V+ 12 and RL > 1 MO
to Vs/2. Boldface limits apply at the temperature extremes.

Symbol

SR
GBW

m

Parameter

Slew Rate
Gain-Bandwidth Product

Conditions

8 Vp_p @ Vee 12V
Rs>1kO

25

f=50kHz

17

Phase Margin

38

Amp-to-Amp Isolation

130

en

Input-Referred
Voltage Noise

f = 1 kHz

in

Input-Referred
Current Noise

f = 1 kHz

Total Harmonic Distortion

f = 10 kHz, RL = 10 kO,

T.H.D.

Typ
(Note 5)

16
0.22

1-291

0.003

LM6144AI
LM6142AI
Limit
(Note 6)

LM6144BI
LM6142BI
Limit
(Note 6)

15

13

13

11

10

10

e

e

Units

V/p.s
min
MHz
min
Deg
dB
nV

{HZ
pA

{HZ
%

2.7V DC Electrical Characteristics

' ..

~.".

Unless Otherwise Specified, All Limits Guaranteed for TJ = 25~C, V+ = 2.7V, V- '" OV, VCM = Vo = V+ /2 and RL
to V+ /2. Boldface limits apply at the temperature extreme

Symbol

Vos
Ie
los

Parameter

Typ

Conditions

."

(Note 5)'

Input Offset Voltage

0.4

Input Bias Current

150

4

Input Offset Current

RIN

Input Resistance

CMRR

Common Mode
Rejection Ratio
Power Supply
Rejection Ratio

VCM

Input Common-Mode
Voltage Range

Av

Large Signal
Voltage Gain

RL = .10k

Vo

Output Swing

RL = 10kO

1.8

2.5

4.3

mV
max

250

300

nA

82.

82.

max

30

30

80

80

nA
max
MO

dB
min

76
79
-0.25

0

0

Vmin

2.95

2.7

2.7

V max
V/mV
min

55
0.01,9

Per Amplifier

510

0.08

0.08

0.112

0.112

2.66

2:66

2.28

2.28

Conditions

GBW

Gain-Bandwidth Product

f=50kHz



LM6144AI
LM6142A1
Umlt
(Note 6)

LM6144BI
LM6142BI
Limit
(Note 6)

>

1 MO

Units

9

MHz

36

Oeg

6

dB

24V Electrical Characteristics
Unless Otherwise Specified, All Limits Guaranteed for TJ = 25°C, V+ = 24V, V- = OV, VCM = Vo = V+ 12 and RL
to Vs/2. Boldface limits apply at the temperature extreme

Symbol

Vos

Parameter

Conditions

Input Offset Voltage

18

Input Bias Current

los

Input Offset Current

Typ
(Note 5)
1.3

288

MO

OV"; VCM"; 23V

114

OV,,; VCM"; 24V

100

PSRR

Power Supply
Rejection Ratio

OV,,; VCM"; 24V

VCM

Input Common-Mode
Voltage Range

Output Swing

RL = 10kO

GBW

Supply Current
Gain-Bandwidth Product

dB
min

87
-0.25

0

0

V min

24.25

24

24

V max
VlmV
min

500
0.07
23.85

Is

Per Amplifier

,750

f=50kHz

mV
max

nA
max

Input Resistance

Vo

3.8

4.8

5

Common Mode
Rejection Ratio

RL = 10k

2

4.8

Units

nA
max

RIN

Large Signal
Voltage Gain

LM6144BI
LM6142BI
LImit
(Note 6)

1 MO

174

CMRR

Av

LM6144AI
LM6142A1
LImit
(Note 6)

>

18

0.15

0.15

0.185

0.185

23.81

23.81

23.82

23.82

V
max
V
min

1100

1100

p.A

1150

1150

max
MHz

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may ocCur. Operating Ratings Indicate conditions for which the device is
Intended to ,be functional, but specific performance Is not guaranteed. For guaranteed specifocations and the test conditions, see the Electrical Charectenstics.
Note 2: Human body model, 1.5 kG in series with 100 pF.
Note 3: Applies to both Single-supply and splR-supply operation. Continuous short circuH operation at elevated ambient temperatura can reautt in exceeding the
maximum allowed junction tempe

250.
20.0.
150.

Vs = 10V

I

I

10.0.

I

50.

lDDk

0
-50.

..... lDk

I\,

~

~ -tOO
l!;

2k

-150
-20.0.
-250.
0

1 2 3

4 5

6 7 8

9 10.

DUTPUT VDLTAGE (v)

TLlH/12057-3

1.294

r-

ill:

Typical Performance Characteristics

....
...
G)

TA = 25'C, RL = 10 kO Unless Otherwise Specified (Continued)

Output Voltage vs
Source Current

Output Voltage vs
Source Current

10

'4

i

~

~

~

'4

10

~

~

!;i

~

lil

G)

...

10

i

B
0.1

ill:

.......

100

z

B

~

Output Voltage vs
Source Current

100

'4

I\)
.....
r-

!;i

~

0.1

0.1

0.01
10

100

1000

10000

100

OUTPUT SWING FROU V+ (mV)

Output Voltage vs
Sink Current

.

~

'4

10

~

0.1

in

§

~

0.01

§

0.001

10

~

10

100

1000

10

iB
l;!

0.1

in

I

0.01

0.1

10000

0.1

0.01

0.001

0.001
0.1

10000

100

'4

B
l;!

1000

Output Voltage vs
Sink Current

i

~

i<

100

OUTPUT SWING FROM V+ (mV)

100

100

B
in

10000

Output Voltage vs
Sink Current

Ei
g;
l;!

1000

OUTPUT SWING FROU V+ (mV)

OUTPUT SWING FRON V- (mV)

10

100

1000

1

10000

10

100

1000

v-

OUTPUT SWING FROM V- (mV)

OUTPUT SWING FROM

Gain and Phase vs Load

Distortion + Noise
vs Frequency

10000

(mV)

TL/H/I2057-4

Gain and Phase vs Load
120
100

.,
3

z

~

D.

80
60

'," -"

qj

~
1\ =10k IIl00pF!J!'

40
20

10

100

lk

1\ =10k

~ I\~

11\

"

'1--.-

Go;,

10k

lOOk

-20

180

120

150

100

-66

VS=5V

~

1M

120
90
60

. .,
3

~

if

-68

.,

80
60

0

'0

if

~

z

~

30

20

3

-72

~

-74

is

-78

~

=

Vs 2.4V
Vo = IOVpp'

-70

-76

1/

-80

".

.,/

-82

-30
10M

100

lk

FREQUENCY (Hz)

10k

lOOk

-8', k

1M

FREQUENCY (Hz)

2k

..

8k
20k
6k 10k

'Ok 80k
60k lOOk

FREQUENCY (Hz)

GBW vs Supply
25.00

i
~

S 15.00

I
~

GBW at 100kHz ~

20.00

10.00

5.00

/"

ffqa~

L
~\~
11\.....

~

".

V

0.00 1

8
6

20.0
10

60

80
100

SUPPLY VOLTAGE (V)

TUH/I2Q57-11

1-295

•

Typical Performance Characteristics

.',

TA = 25"C. RL = 10 kO Unless Otherwise Specified (Continued)
Open Loop Galn.va
Load, av Supply
120 r--r-,-......-,---,--,
100

r--..

or
....,

lit. •

Open L:oop 'Gain va
Load, 5V ·Supply
120 r---r-,--r-.,.,--r---.

IN

::::--ko-

100

! 80r-~~~f"~~++-+-+-~
'~~

~

..

~

§
~
O

z

60r--HL-~~~t--+~

1\ = 10k'
lit. =

40

~

....~

Ik

§

1-"'"' ,:~

~.~

o I---+--+---+-+--+".Irl,

~ 20r-+-+--+~~-~~
o 1--+--+-+-+--+'~-""~

.-20 '----'-_'----'-'-_-'---L---'

.-20 L---L._-'--'-_-'---L---'

..,~

10

.100

Ik

10k lOOk

1M

!

~

.•

60r--#~t-~~+--+~
1It." 10k
. ';~
~~-+-+--+~~-+~
1\.=lk

20~~~+--+-~~~

120

1\. = IN

80r--r~r~-+--t--+~
zr',~

!

Open Loop Gain va
Load, 24V Supply

ION

10

100

rREQUENCY (Hz)

Ik

10k lOOk

1M

§z
~
O

10M

3

~

:

Croaatalk va Frequency
140 1----FI'1'IoIoWl--+tttttttr-+++I+Ht1

105
100

25 .

.~

95

10

15

20

25

\.

i

120

1-'+tttHIII--ttttttttl'''d-++I+Ht1

110

r-l-Hftfllll-t+H1+Hf-+-PtItlfll

90L-LWWlliL-LLUU~~LWW

60
10

30

100

80.0 ~
70.0.
~

NEG P5R

i! -40.0 r-+-t--+I~
"'t-,:Fl
"'

10k

0.1

lOOk

I

•

1-+-t-::-:l-:::+~~.JJ9--f

20,0
10.0 1--+_+-'PO"'S'r'P""S,,"R.+~_,..-;
0.0 '---'---'-_.l--,-_,-,r\.........,
10 100 Ik 10k lOOk IN 10M

1000
600
600
400

~

200

~

100
SO
60.
40

g
tl
~

!
is

"

10
0.01

0.1

rREQUENCY (Hz)

I

'"

10

100

Noise Current va Frequency

~....

'\.

20

10

. FREQUENCY (kHz)

Noise Voltage va Frequency

~
....

60.0 Vs = 3V +."'1,.-+--11-+-1

I'"

Ik

rREQUENCY (Hz)

PSRR va Frequency

.30.0

I'

65

100.0 Vs = 10V
I
90.0 ~ Vs =' 5V +-1--;

50,0

,,~
20r--+-t--+~+-~~,

'\.

SUPPLY VOLTAGE (V)

~

.;..~

40r--+~t--+~~~-,

150 r-rnmnu-rr="-T"T"rTTIm

r-....

90

~~

~

rREQUENCY (Hz)

115

'"

..

Ol--+-+--+-+--+~~

Vs = 10V

!

= 10k

-20 L--'-_-'---L_-'---'_..J
10 100 Ik 10k lOOk 1M lOY

r---r---r--~-,-,

110

1\.= 1M

1\. " k

CMRR ·va Frequency
120

5

~

60

rREQUENCY (Hz)

Unity Gain Freq va Vs

o

.

100~
/ ":-:-'
80
......

II'
i'l
tl
~

100

10
S'
6
4
2
I
0.6
0.6
0.4
• 0.2
\ 0.1

1000

0.1

rREQUENCY (Hz)

I

10

100

1000 10000

rREQUENCY (Hz)

TL/H/I2057-5

NE va R Soure.'
20
IS

I

16

'"

14

=>

10

3

~
~

.

~

~

~

12
6
6
4
2
0
. 100

lk

10k

lOOk

RsoURCE (n)

1-296

1M

10M

TL/HI12057-12

r-

.....
.....
I:
en

LM6142/44 Application Ideas
Slew Rate va IJ. VIN
Vs = ±5V

The LM6142 brings a new level of ease of use to opamp
system design.
55
50

With greater than rail-to-rail input voltage range concern
over exceeding the common-mode voltage range is eliminated.
Rail-to-rail output swing provides the maximum possible dynamic range at the output. This is particularly important
when operating on low supply voltages.

.:

45

'iii"

.....:I.
~

...,.;
"'"
'"
~
en

The high gain-bandwidth with low supply current opens new
battery powered applications, where high power consumption, previously reduced battery life to unacceptable levels.
To take advantage of these features, some ideas should be
kept in mind.

.0
35
30
25
20
15
10
5""::'

.SLEW

Ih

..

/I

= ..

..

-

N
.....
r-

.. .'

I:
en

'

-SLEW

~

OL-~~~~

__~~-L-J

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

ENHANCED SLEW RATE

DIFFERENTIAL INPUT VOLTAGE, (V)

Unlike most bipolar opamps, the unique phase reversal prevention/speed-up circuit in the input stage causes the slew
rate to be very much a function of the i",put signal amplitude.
Figure 1 shows how excess input signal, is routed around
the input collector-base junctions, directly to the current mirrors.

TLlH/120S7-7

FIGURE 2
This effect is most noticeable at higher supply voltages and
lower gains where incoming signals are likely to be large.
This new input circuit also eliminates the phase reversal
seen in many opamps when they are overdriVen.

The LM6142/44 input stage converts the input voltage
change to a current change. This current change drives the
current mirrors through the collectors of 01-02, 03-04
when the input levels are normal.

This speed-up action adds stability to the system when driving large capacitive loads.

If the input signal exceeds the slew rate of the input stage,
the differential input voltage rises above two diode drops~
This excess Signal bypasses the normal input transistors,
(91-04), and is routed in correct phase through the two
additional transistors, (05, 06), directly into the current mirrors.
This rerouting of excess signal allows the slew-rate to increase by a factor of 10 to 1 or more. (See Figure 2.)

Capacitive loads decrease the phase m~in of"all opamps.
This is caused by the output resi,stance of the amplifier and
the load capacitance fOrming an R-C phase lag network.
This can lead to overshoot, ringing and oscillation. Slew rate
limiting can also cause additional lag. Most opamps with a
fixed maximum slew-rate Will lag further and further behind
when driving capacitive loads even though the differential
input voltage raises. With the LM6142, the ,lag causes the
slew rate to raise. The increased slew-rate' ke8ps the output
following the input much better. This effectively reduces
phase lag. After the output has caught up with the i'nput, the
differential input voltage drops down and the amplifier settles rapidly.

DRIVING CAPACITIVE LOADS

As the overdrive increases, the opamp reacts, better than a
conventional opamp. Large fast pulses will raise the slewrate to around 30V to 60Vl p.s.

.IN

•

-IN
OUT

TLlHI12057-6

FIGURE 1

1-297

LM6142/44 Application Ideas
(Continued)
These features allow the LM6142 to, drive capacitive loads
as large as 1000 pF at unity gain and not oscillate. The
scope photos (Flf}ure 3a'and 3b) above show the LM6142
drMng a 1000 pF load. In Flf}ure 3a, the upper trace is with
no capacitive load and the lower trace is with a 1000 pF
load. Here we are operating on ±12V supplies with a 20
Vp-p pulse; Excellent response is obtained with a Ct of
10 pF. In Figu~ 3b, the supplies have been reduced to
±2.5V, the pulse is 4 Vp-p and Ct is 39 pF. The best value
for the compensation capacitor is best established after the
board layout is finished because the value is dependent on
board stray capacity, t!le value of the feedback resistor, the
closed loop gain and, to some extent, the supply voltage.
Another effect that is oommon to all opamps is the phase
shift caused by the feedback resistor and the input capacitance. This phase shift also reduces phase margin. This effect is taken care of at the same time as the effect of the
capacitive load when' the capaCitor is placed across the
feedback resistor. ,
The circuit shown in Figure 4 was used for t~se scope
photos.

1,nF
~

TUH/12057-10

FIGURE 4

Typical Applications
FISH FINDERI DEPTH SOUNDER_
The LM6142/44 is an excellent choice for battery operated
fish finders. The low supply current, high gain-bandwidth
and full rail to rail output swing of the LM6142 provides an
ideal combination for use in this and similar applications.

ANALOG TO DIGITAL CONVERTER BUFFER
The high capacitive load driving ability, rail-to-rail input and
output range with the excellent CMf:! of 82 dB, make the
LM6142/44 a good choice for buffering the inputs of A to D
converters.

3 OPAMPINSTRUMENTATION AMP WITH RAIL·ToRAIL INPUT'AND OUTPUT
Using the LM61'44, a :3 opamp instrumentation amplifier with
rail-to-rail inputs and rail to rail output can be made. These
features make these instrumentation amplifiers ideal for single supply systems.
Some manufacturers use a preciSion voltage divider array of
5 ,resistors to divide the common-mode voltage to get an
input range of rail-to-rail or greater. The problem with this
method is that it also divides the signal, so to even get unity
gain, the amplifier must be run at high closed loop gains.
This raises the noise and drift by the intemal gain factor and
lowers the input impedance. Any mismatch in these precision resistors reduces the CMR as well. Using the LM6144,
all of these problems are eliminated.

TL/H/12057-8

FIGURE Sa

In this example, amplifiers A and B act as buffers to the
differential stage (Figure 5). These buffers assure that the
input impedance is over 100 MO and they eliminate the
requirement for preCision matched resistors in the input
stage. They also assure that the difference amp is driven
from a voltage source. This is necessary to maintain the
CMR set by the matching of R1-R2 with R3-R4.
R2
TUH/12057 -9

FIGURE3b

~Lt.46144
+

R3

R4

TUH/12057-13

FIGURE 5
1-298

The gain is set by the ratio of R2/R1 and R3 should equal
R1 and R4 equal R2. Making R4 slightly smaller than R2
and adding a trim pot equal to twice the difference between
R2 and R4 will allow the CMR to be adjusted for optimum.
With both rail to rail input and output ranges, the inputs and
outputs are only limited by the supply voltages. Remember
that even with rail-ta-rail output, the output can not swing

past the supplies so the combined common mode voltage
plus the signal should not be greater than the supplies or
limiting will occur.

SPICE MACROMODEL

A SPICE macromodel of this and many other National Semiconductor opamps is available at no charge from the NSC
Customer Response Group at 800-272-9959.

•
1-299

til ~

, ,

,"

,":",

Ii flo na " .S e"m ,i c 0. n due t or
, ~

'~""

..

"

.-

"

.,

'"

~,~

>

•

Au~iO .Noise Reduction

"

Selection Guide

Part
Number

NR
Type

NR
Effect

Encoding
Required

Singlel
Dual

LM1131

Dolbyil>

10dB

Yes

Dual

LM1894

DNRiI>

12dB

No

Dual

1..aoO

!

Decode
SIN

SUpply
Range

Package
(Pin Count)

so dB

5Vto20V

Dip(18)

76 dB

4.5Vto 18V

Dip(14),50(14)

E
........
....

t!lNational Semiconductor

W

~

Ii:....
....
W
....

LM1131A/LM1131B/LM1131C
Dual Dolby® B-Type Noise Reduction Processor
General Description
The LM1131 is a monolithic integrated circuit specifically
designed to realize the Dolby B-Type noise reduction system.
The circuit includes two completely separate noise reduction processors and wi" operate in both encode and decode
modes. It is ideal for stereo applications in compact equipment or for mono applications in 3-head equipment where
, two processors with very closely matched internal gains are
required.

Features
• Stereo Dolby noise reduction with one IC

!!!

• Wide supply voltage range, 5V-20V
• Very high signal/noise ratio, 79 dB encode, 90 dB decode (CCIR/ARM)
• Very close gain matching for 3-head recorders
• Close matching to standard Dolby characteristics
• Very low temperature drift of Dolby characteristics
• High signal handling capability, > +20 dB (VS = 20V)
• Fu"-wave rectifier in both channels
• Operates with both Single and split supply voltages
ill Exce"ent transient response characteristics
• Minimal input switch-on transients
• Reduced number of external components per channel
• Improved input protection

Ii:
....
....
W
....
o

Available to licensees of Dolby laboratories licensing CoJporatlon, San, Francisco, from whom licensing and application Information must be obtained.

Schematic Diagram (1 channel shown only)

•
TLfHf6858-1

1-301

u....

....
C')

....~
ID
....

....
....

C')

:i
:c....
....
....

Absolute Maximum Ratings
Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
26O"C
Small Outline Package
Vapor Phase (60 seconds)
215°C
Infrared (15 seconds)
220"C
See AN-450 "Surface'Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications..
Supply Voltage
24V
Operating Temperature Range
- 20"C to + 70"C
Storage Temperature Range
-65°Cto + 150"C

'.

C')

:i

Electrical Characteristics
Vs = 12V, TA = 25°C unless otherwise specified. 0 dB refers to Dolby level and is 580rriV, measured at TP1 and TP2.
Parameter

Min
Supply Voltage Range

"

LM1131B

LM1131A

. Conditions

Typ

5

Supply Current

Max

Min

20

5

20

Typ

' LM1131C
Max

Min

20

5

20

Voltage Gain
(Pins 7-10 and 14-11)
(Pins 10-9 and 11-12)

1 kHz Decode
1 kHz Decode

19.2
-0.5

19.7
0

20.2
0.5

18.7
-0.5

19.7
0

Difference in Voltage

1 kHz Noise

-0.2

0

0.2

-0.5

0

-60

-90

-60

77

79
82
90
92

0
-16.2
-17.3
-21.7
-22.3
-30.1

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

Typ

Unlta
Max
20

V
mA

20

20.7
0.5

18.2
-1.0

19.7
0

21.2
1.0

dB
dB

0.5 .

-1.0

0

1.0

dB

-90

-60

-90

dB

75.5

79
82
90
92

74

79
82
90
92

dB
dB
dB
dB

0.2
-16.7
-17.8
-22.2
-22.8
-30.3

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

-0.5
-17.2
-18.3
-22.7
-23.3
-30.6

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

Gain between Channels Reduction OFF
Crosstalk between
Channels

1 kHz,OdB

Signal/Noise Ratio
at Pins 9 and 12
Encode

(Note 1)

Decode
Encode Characteristics

Variation in Encode
Characteristic's
Temperature
Voltage
Distortion
Signal Handling

Rs = 10kO
Rs=1kO
Rs = 10kO
Rs=1kO
10 kHz, 0 dB
1.3 kHz, -20 dB
5kHz, -20dB
3kHz, -30dB
5 kHz, -30 dB
10 kHz, -40 dB

O"C-70"C
5V-20V
1 kHz,OdB
10 kHz, 10 dB
1 kHz, Dist = 0.3%
Vs = 5V
, Vs = 7V
Vs = 12V
Vs = 20V

Input Resistance

Pins 7 and 14

Output Resistance

Pins 9 and 12
Pins 10 and 11

1.0
-15.2
-16.3
-20.7
-23.0
-29.1

<±0.5
<±0.2
0.03
0.2

14.0
45

<±0.5
<±0.2
0.03
0.2

0.1

6.5
10.5
16.0
21.0

14.0

65

80

30
30

55
55

45

1.2
-14.7
-15.8
-20.2
-20.8
-28.9

'0.1

6.5
10.5
16.0
21.0

<±0.5
<±0.2
0.03
0.2

,

14.0

65

80

30
30

55
55

45

0.2

6.5
10.5
16.0
21.0

dB
dB
dB
dB
dB
dB

dB
dB
%
%
dB
dB
dB
dB

65

80

kO

30
30

55
55

0
0

Note 1: Gaussian noise, measured over a period of 50 ms per channel, with a CCIR filter referencad to 2 kHz and an average-respondlng mater.

1-302

1.5
-14.2
-15.3
-19.7
-20.3
-28.6

~
....
....
w
....

Typical Performance Characteristics
Supply Current vs Supply Voltage
(1 kHz, 0 dB; NR ON)

~

Signal Handling vs Supply Voltage

~
....
....w
....
m

22

.....

20

30

~ i""'"

8

V

12

14

iii:
....
....w
....
o

V
12

18

18

......
r-

V

II

8

20

'/

I

10

10

V

'"

./

V

..

...

... ...

..

10

.....
..... .....

..... ....

.....
14

... ...

... ...

.

... ...

8

8

Supply VoItIIge (V)

10

12

14

18

18

20

Supply Voltage (VI
TUH/6858-2

Signal to Noise Ratio vs Source Impedance
Encode Mode (CCIRtARM)

Gain VB Frequency (NR OFF)
32

82
80

28

~'18

24

1'18

P7-PlO
(PI4;;P11I

ii20
:!!

i 18

.... 74

172

I~

P7-PI
(Pl4-PI21

12

70

8

ea

4

10

100

lK

lOOK

10K

o
0.1

Sou ..... Impedlnee ( {} I

10

1000

100

Frequ-.cy (kHz)
TUH/6858-3

Back to Back Response Error vs Frequency and
Supply Voltage (Standard DOlby Encoder)

o

1:12:2OV

+1
0
-1
+1
0

1:12:2OV

~-10

-40
10

20

DOC
-+2II"C
O'C
___0: +215: +'II"C

-40
100

-

+'II"C_

10

0.1

•

+1
0
-1
+1
0

+'II'C_

-+2Ii"C

+1
0
-1
+1
0
-1

~1:12:2OV

0.1

D:+2Ii:+7B"C

~IJ

_1:12:2OV

1-30

0: +215: +7&"C

o

:;::i

':12:2OV

5-20

!

Back to Back Response Error vs Frequency and
Temperature (Encode Temperature + 25"C)

:;::j

OJ
+1
0
-1
+1
0
1

20

100

Frequency (kHz)

Frequency (kHz)

TUH/6858-4

1·303

Application Notes
SUPPLY VOLTAGE
LMl131 may operate wHh either single or l!plit supply voltages.
'

NOISE REDUCTION SWITCH
Noise reduction OFF is normally effectecl .by means of a
mechanical switch which open-circuits the sidechain input.
An alternative method,which permits the control of NR OFF
by means of a DC voltege is shown in F/fIuf6 1. The DC
control voltage forces 'the internal impedance to a minimum
value and heavily attenuates the sidechain input. When using this circuit the following points should be noted:
a) Signal boost in ,encode mode (I\ignal c,ut in de!:ode) is
, ,reduced by increasing DC volteges on pins 3 and 18. A
voltage of approximately 3V above signal ground is adequate to achieve NR OFF.
b) Supply current may be increased significantly by high pin
, 3/18 foreing voltages. Thus, values for V3 and Fi3 should
ideally be chosen such that pin 3/18 forced voltage is
only 3V-:5V greater. than Signal ground. Maximum permi$Sible voltage on pin 3/18 is equal to supply voltage.
c) When electrical NR switching is used in this way, NR OFF
signal level is slightly affected by the restriction that the
internal variable impedance cannot achieve zero impedance. Thus, at 10 kHz-l0 dB, a residual boost in encode
(or cut in decode) of approximately 0.4 dB remains. At
low frequencies this value reduces to insignificant levels.
This is not the case for mechanical,NR switching.

Single Supply Voltage "
Pin 1 is conneCted to ground, pin 20 to Vs.
Pins 8 and 13 are internally generated reference voltages
set to approximately half-supply. They should be connected
together externally.
A 220
capacitor must be connected between pins 8 and
13 and ground, Device tum-on time is delayed by the rise.
time of pins 8 and 13.

p.F

Split Supply Voltag~
Pin 1 is connected to the negative supply, pin 20 to the
pOsitive supply. Pins 8 and 13 ~e connected.to OV and no
capacitor is required. Device turn-on time is delayed only by
the rise times of the supply voltages.
SIGNAL GAIN AND FILTERING
It should be noted that LM 1131 has only one internal preamplifier, AB, with no prOvision for interconnectidn of a low
pass filter to remove bias or multiplex tones. In addition,
main chain gain has been reduced by 6 dB in comparison
with LMll12/LMl 011.
If a low pass filter is requirecl it should be connectecl at the
input of the LMl131. Pre-adjustment at Dolby input level
may then be perform~, at the input of LMl131 if required.
V3

I
20

19

18

17

16

15

14

6

7

13

12

11

9

10

tLB.

~

D

R3

OfF

LM1131
!

1

2

5

4

3

J:

,

.,

L

INPUT
10pF'
,10pF+ , ~15K

",,:

8

.. '

47K

270K

t:r-

,

0.1

0.33

UK

I

SlDECHAIN I/P

I

0.0047
0.033 .

~O.OO

MONITOR OIP

----1

I SIGNAL GROUND
y-

yTLlH/685B-5

FIGURE 1. LM1131

D~de

Processor with Electrical NR Switch (1 Channel Shown)

1-304

Ii:....
....

Test Circuit Encode Mode (components shown for channel 1 only)

....

Co)

v+

~

2D

r

~
........
....

I

Co)

~

~
....

....
....
o
Co)

lov
I

I
I

Note 1: Where not othelWise specified ccmponent tolerances are

±IQ%

L,

Note 2: For LM1131AN use 2%
ccmponents for C304, R303, R305.
(5% ccmponents may cause errors
up to ± 0.3 dB).

Signal

~~~____+-__4 -__~UL~__~~~~~

v-

TUH/6858-6

Connection Diagram
Dual-In-Una and Small Outllna Packages
2D POSITIVE SUPPLY

NEGAnVE SUPPLY
DECOUPLING

2

1.

RECTIFIER OUTPUT

I

1. REcnFlER OUTPUT

VARIABLE IMPEDANCE
CONTROL
AMPLIPIER D
~EDBACK DECOUPLING
BIDECHAIN INPUT

4

AMPLIFIER AB
, INPUT

..J
W

Z
Z

7

«
::I:
U

SIGNAL GROUND
AMPUFIER EK
OUTPUT

DECOUPU~

17 VARIABLE IMPEDANCE

N
..J

W

18 AMPUFlIR D

Z
Z

«::I:

18 8/DECHAIN INPUT

U

CONTROL

III

~EDBACKDECOUPUNG

14 AMPUFIER AB
INPUT
11 8/GNAL GROUND

•

AMPLIFIER EK
OUTPUT

MONITOR OUTPUT 10

_/TOR OUTPUT

TUH/6858-7

Order Number LM1131AN, LM1131BN, LM1131CM or LM1131CN
See NS Package Number M20B Dr N20A

1-305

i:=!i

t!lNational Semiconductor
LM1894 Dynamic Noise Reduction System DNR®
General Description
The LM 1894 is a stereo noise reduction circuit for use with
audio playback systems. The DNR system is non-complementary, meaning it does not require encoded source material. The system is compatible with virtually all prerecorded
tapes and FM broadcasts. Psychoacoustic masking, and an
adaptive bandwidth scheme allow the DNR to achieve 10
dB of noise reduction. DNR can save circuit board space
and cost because of the few additional components required.
..

Features

• Compatible with all prerecorded tapes and FM
• 10 dB effeCtive tape noise reduction CCIR/ARM
weighted
• Wide supply range, 4.5V to 18V
• 1 Vrms input overload

Applications
•
•
•
•
•

Automotive radio/tape players
Compact portable tape players
Quality HI-FI tape systems
VCR playback noise reduction
Video disc playback noise reduction

• Non-complementary noise reduction, "single ended"
• Low cost external components, no critical matching

Typical Application
CII
10F

+
CB
U470F

e12

0.0033 "F

13

12

LEFT
OUTPUT

LMII94

0.1

CI
ofT
":'

RIGHT
INPUT

Cl
C2
10F

1I.10F~

C3
0.0033,.F

·r~~-:

TO VOLUME
CONTROL AND
POWER AMPLIFIERS

RIGHT
OUTPUT

*R2

C4

loF

+
'RI + R2 = I kn Iolal.
See Application Hinls.

TUH/791B-l

FIGURE 1. Component Hook-Up for Stereo DNR System
Order Number LM1894M or LM1894N
See NS Package Number M14A or N14A

1-306

Absolute Maximum Ratings
If Military/Aerospace sp,clfled devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

Soldering Information'
Dual-In-Line Package
Soldering (10 seconds)

20V

Input Voltage Range, Vpk

Vs/2
O"Cto +70"C

Operating Temperature (Note 1)

215·C
220"C

See AN-450 "Surlace Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

-65·Cto + 150"C

Storage Temperature

260"C

Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

Electrical Characteristics
Vs

=

8V, TA

=

25·C, VIN

= 300 mV at 1 kHz, circuit shown in Figure 1 unless otherwise specified
Conditions

Parameter
Operating Supply Range
Supply Current

Vs

=

Min

Typ

Max

4.5

8

18

V

17

30

rnA

-0.9

-1

-1.1

VIV

3.7

4.0

4.3

V

1.0

dB

1400

Hz

8V

Units

MAIN SIGNAL PATH
Voltage Gain

DC Ground Pin 9, Note 2

DC Output Voltage
Channel Balance

DC Ground Pin 9

-1.0

Minimum Balance

AC Ground Pin 9 with O.l".LF
Capacitor, Note 2

675

965

Maximum Bandwidth

DC Ground Pin 9, Note 2

34

46

kHz

Effective Noise Reduction

CCIRIARM Weighted, Note 3

-10

-14

dB

Total Harmonic Distortion

DC Ground Pin 9

0.05

0.1

%

Input Headroom

Maximum VIN for 3% THD
AC Ground Pin 9

Output Headroom

Maximum VOUT for 3% THD
DC Ground Pin 9

Signal to Noise

BW = 20 Hz-20 kHz, re 300 mV
AC Ground Pin 9
DC Ground Pin 9
CCIRIARM Weighted re 300 mV
Note 4
AC Ground Pin 9
DC Ground Pin 9
CCIR Peak, re 300 mV, Note 5
AC Ground Pin 9
DC Ground Pin 9

27

82
70

1.0

Vrms

Vs -1.5

Vp-p

79

77

dB
dB

88
76

dB
dB

77

dB
dB

64

Input Impedance

Pin 2 and Pin 13

14

20

Channel Separation

DC Ground Pin 9

-50

-70

dB

Power Supply Rejection

C14

-40

-56

dB

=

k!l

100,...F,

VRIPPLE = 500 mVrms,
f = 1 kHz
Output DC Shift

26

Reference DVM to Pin 14 and
Measuree Output DC Shift from
Minimum to Maximum Bandwidth, Note 6.

1-307

4.0

20

mV

•

i

i....

". ".,

Electrical Characteristics

Vs = SV, TA = 25°C, VIN = 300 mV at 1kHz, Circuit shown in Figure t unless otherwise specified (Continued)

I ."

Parameter

. Conditions

".I.

I

MI!).

Typ

I.

Max ,

I

UnitS

CONTROL SIGNAL PATH
: Summing Amplifier Voltage Gain

..

.' Both Channels Driven

0.9

1

1.1

VIV

Gain Amplifjer Input Impedance
Voltage Gain

Pin 6
Pin6to PinS

24
21.5

30
24

39
26.5

kn
VIV

Peak Detector Input Impedance

Pin 9

560

700

S40

n

Voltage Gain

Pin 9to Pin 10

30

,33

36

. VIV·

Attack Time

.M88llUred to 90% of Final Value
with 10kHz Tone Burst
.Measured to 90% of Final Value"
10 kHz Tone Burst
Minimum Bandwidth to Maximum
Bandwidth

300

500

700

,..s

45

60

75

rns

3.S.

V

DeCay Time

'with

DC Voltage Range

1.1

Note 1: For operation In ambient temperature above 25'C. the device must be derated based on a 15O'C maximum junction temperature and a thermal resil\lance
of 1) 8CY'C/W junction to ambient for the duaJ~""line package, and 2) 1000C/W junction to ambiant for the small ouUine package.
Note 2: To fotce the DNR system Into maximum bandwidth, DC grouild the input to the pBak d8tect0r, pln'9. A negative temperature coeffIcientof -0.5%/'C on
the bandwidth, reduces the maximum baridWidth at Incfeasec:t ambient temperature or higher package dissipation. AC ground pin 9 or pin 6 to select minimum
bandwldIfl. To ~ minimum aild maximum bandWidth, """ Appllctlon HInts.
Note 3: The !I1axlmum noise reduction CCIRIARM weighted is about 14 dB. This is accomplished by ~hanglng the bandwidth from maximum to minimum. In actual
operation, minimum ba.-!1 is not selected, a nomina! minimum bandwidth of about 2 kHz gives -10 dB of noise reduction. See Appficetion Hints.
Note 4: The CC1RI ARM weighted nols/' ,is.meesured with a 40 dB gain ampllller between the DNR system and the CCIR weighting filter; it Is then Input referred.
Note 5: Meesured using the ,Rhode-Schwartz psopIio~eter.
.
Note 6: Pin 10 is DC fotced haH way between the maximum .bendwidth DC level and minimum bandwidth DC.leveI. An AC 1 kHz signal Is .then appfled to pin 10. Its
peak-Io-peak amplitude is Voc (max BW) - Voc (min BW).
. . , .
"."
•

Typical Performance Characteristics
Supply Current vs
Supply Voltage
~

...... i--'"

at t-t--t-t-7I,,"+-f-t-I

vi-'

.i

i

1&

..B

11r-+-+-+-~~-+~~

co

I

81

V

ZI

V

II

;;;

.•

7G

s

II

~

/

Power Supply Rejection
Ratio (Referred to the
Output) vs Frequency
la

IIIIIID

.. fULLiI

;,tWo

MI

~.

:-

.

;!
III

41

!...

I

co

4G

I

CI4·1.~f

Y;,I.l,~~
11'

SUPPLY VOLTAGE IV!

111

co

at
II

.

.~

30

II!

!
•

!..

II

II:

Ir-+-+-+-~~-+~~

Channel SeparatIOn
(Referred to the Output)' .
VB Frequency

t.

il

'f~~:;~-'
[;t.

21
'CI'j'
D
lD

"I.

'.'

fREOUENCY IItz)

~
-

~~

1.

I l lk

1.

fREDDENCY (liz!

..

-3 dB Bandwidth
vs FreqUency and
.Control Signal

GaIn of Control Path
VB Frequency (with

THD vs Fr~uency
0.11 r--r--r-r--r--r-r--r-T"""I

lDr--r--r-r--r-T""r--r-~

g a.. I--t-Hf--HH-IH-I

~ .~~r-.
I--t-t-r'f--t--'~/''i>rie.~
...

!

v~!J.J
.iHz
DM""'~~~~

I--t--r.-t--t--t-r.--t-t-l

I~~~--~~~~~

28 111812111 101 1. 2k 1111110 2110
fREDUENCY IItz)

'j . II

-ID

CONtROL 'AlII

-311
-40

r-: - ",

VI·i~"r

A~IPOTHzI

I

I

•

,.-

fREDUENCY 1Hz!

5.

1.

ZI

::

/

I

·c

ZIIII

18kHz

:'~\~1

10 t-H-i~1I-1-tt

co -11

~-'--L......L~L......L-L--L-L...J

at ID lID DB 101 lk 2k

i..
~

'\

SIGNAL AT PtN foZmV

3G

a

! l l i i l z I r)~.\
~ 21 I-'-+-H--,.i. r-t .... Nt ~
-

IJII IIlIiVl

j; 4G 1-++f+HlIII--.4rwlTltliuT 1

:f

5k .....

~

0.12

10 kHz FM Pilot Filter)

al rTTT1T11Ir"nlmlll~""""'=mt

r-1-Vl~~1-++ t-ffl-tlffil-H-iitlllhl-t+

-B I-Ju.J.WIII--L.J...UJIUL-LJ.J.

100

1.
FREDoENCY 1Hz!

I.

TLlH/~18-2

1-308

Typical Performance Characteristics

(Continued)

Main Signal Path
Bandwidth vs
Voltage Control
2D

Peak Detector Response

1&

I--

12

I--

INPUT

I-I--

•1.

~

1.

'--

1"

1.

BANDWIDTH (H.,

~K~~-4--+--+~~~~--~-+~

TLlH/7918-3

DETECTOR
OUWUT~~-4--+--+~~·~~--~~~

TIIofE:20 ms/ON

TLlH/7918-4

Output Response

INPUT 1-+-+

DNR

ouwurl-+-+

TIME: 20 ms/ON

T1./H/7918-5

External Component Guide (Figure 1)
Component
C1

C2,C13

C14

ca,C12

Value
0.1,.,.F100 ,.,.F

·1,.,.F

25,.,.F1oo,.,.F
0.0033,.,.F

Purpose
May be part of power
supply, or may be addad to suppress power
supply oscillation.
Blocks DC, pin 2 and
pin 13 are. at DC potential of Vs/2. C2,
C13 form a low frequency pole with 20k
RIN···
1
fL =
21TC2RIN
Improlles . power supply rejection.

Component Value
C4, C11
1,.,.F

Purpose
Output coupling capacitor. Output
is at DC potential of Vs/2.

C5

0.1,.,.F

Works with R1 and R2 to attenuate low , frequency transients
which could, disturb control path
operation.
1
fs = 21T C5 (R1 + R2) = 1.6 kHz

C6

0.001,.,.F

Works with input resistance of pin
6 to form part of control path frequency weighting.
fs =

ca

Forms integrator with
internal gm block and
op amp. Sets bandwidth conversion gain
of 33 Hz/,.,.A of gm
current.

1-309

0.1,.,.F

1 . = 5,3 kHz
21T C6 R1PINS
. Combined with La and CL forms
19 kHz filter for FM pilot This is
only required in FM applications
(Note 1).

•

...
0)

~

External Component Guide (Figure 1)

....

(Continued)

::IE

Component
L8,CL

C9

Value
4.7mH,
O.o15,...F
0.047,...F

C10

1,...F

R1,R2

1 kO

R8

1000

as

Purpose
Forms 19 kHz filter for FM pilot. La is Toko coil CAN1A185HM· (Note 1).
Works with input resistance
of pin 9 to form part of control
path frequency weighting.
1
f9 = 2 C9R
= 4.8 kHz
,
'/1'
PIN9
Set attack and decay time of
peak detector.
Sensitivity resistors set the
noise threshold. Reducing attentuation causes larger signals to be peak detected and
larger bandwidth in main signal path. Total value of R1 +
R2 should equal 1 kO.
Forms RC roll-off with
This "is only required in FM
applications.

Figure 3 is an interesting curve and deserves some discussion. Althougl:1 the output of the DNR system is a linear
function of input signal, the -3 dB bandwidth is not. This is
due to the non-linear nature of the control path. The DNR
system has a uniform frequency response, but looking at
the -3 dB bandwidth on a steady state basis with a single
frequency input can be misleading. It must be remembered
that a single input frequencY can only give a single -3 dB
bandwidth and the roll-off from this point must be a smooth
-6 dB/oct.

A more accurate evaluation of the frequency response can
be seen in Figure 4. In this case the main Signal path is
frequency swept, while the control path has a constant frequency applied. It can be seen that different control path
frequencies each give a distinctive gain roll-off.

ca.

• Toko America Inc., 1250 FeehanviHe Drive, Mt. Prospect IL 60056
Note 1: When FM applications are not required, pin 8 and pin 9 hook-up as

follows:

peak detector input determine the, frequency weighting
shown in the typical performance curves. The 1 ,...F capacitor at pin 10, in conjunction with ,internal resistors, sets the
attack and decay times. The voltage is converted into a
proportional current which is fed into the gm blocks. The
bandwidth sensitivity to gm current is 33 Hz/,...A. In FM
stereo applications at 19 kHz pilot filter is inserted between
pin a and pin 9 as shown in Figure' 1.

__ ~
r. rr:
CI

PF

I

TL/H17918-6

Circuit Operation
The LM1894 has two signal paths, a main signal path and a
bandwidth control path. The main path is an audio low pass
filter comprised of a gm block with a variable current, and an
op amp configured as an integrator. As seen in Figure 2, DC
feedback constrains, the low frequency gain to Av = -1.
Above the cutoff frequency of the filter, the output decreases at -6 dB/oct due to the action of the 0.0033 ,...F capacitor.
'
The purpose of the control paths is to generate a bandwidth
control signal which replicates the ear's sensitivity to noise
in the presence of a tone. A single control path is used for
both channels to keep the stereo image from wandering.
This is done by adding the right and left channels together
in the summing amplifier of Figure 2. The R1, R2 resistor
divider adjusts the incoming noise level to open slightly the
bandwidth of the low pass filter. Control path gain is about
60 dB and is set by the gain amplifier and peak detector
gain. This large gain is needed to ensure the low pass filter
bandwidth can be opened by very low noise floors. The capaCitors between the summing amplifier output and the

Psychoacoustic Basics
The dynamic noise reduction system is a low pass filter that
has a variable'bandwidth of 1 kHz to 30 kHz, dependent on
music spectrum. The DNR system operates on three principles of psychoacoustics.
. ",1. White noise can mask pure tones. The total noise energy
required to mask a pure tone must equal the energy of the
tone itself. Within certain limits, the wider the band of masking noise about the tone, the lower the noise amplitude
need be. As long as the total energy of the noise is equal to
or greater than the energy of the tone, the tone will be inaudible. This principle may be turned around; when music is
present, it is capable of masking noise in the same bandwidth.
2. The ear cannot detect distortion for less than 1 ms. On a
transient basis, if distortion occurs in less than 1 ms, the ear
acts as an integrator and Is unable to detect it. Because of
this, Signals of sufficient energy to mask noise open bandwidth to 90% of the maximum value in less than 1 ms. Reducing the bandwidth to within 10% of its minimum value is
done in about 60 ms: long enough to allow the ambience of
the music to pass through, but not so long as to allow the
noise floor to become audible.
3. Reducing the audio bandwidth reduces the audibility of
noise. Audibility of noise is dependent on noise spectrum, or
how the noise energy is distributed with frequency. Depending on the tape and the recorder equalization, tape noise
spectrum may be slightly rolled off with frequency on a per
octave basis. The ear sensitivity on the other hand greatly
increases between 2 kHz and 10kHz. Noise in this region Is
extremely audible. The DNR system low pass filters this
noise. Low frequency music will not appreciably open the
DNR bandwidth, thus 2 kHz to 20 kHz noise is not heard.

1-310

.-----------------------------------------------------------~~

a::
....

Block Diagram
CHZIO

CHZ OUTPUT

CHI OUTPUT

CHilO

~

V+

~

---.1-1

"

I

...._ _-I-..JV.281c~..., .
.........JIJZ~IIk""""....

--+=-o ~:~UT

CHZO~I3T_....~.,.,.. . ._I

INPUT

I
I

BYPA§~~~---'--_+-~~-----------~-_1r_~

I
I
I
I
I

I

I

27k

31k

I.ZV"'~""'"

I
I
I

..

700

I

I

L ____ _

_J

6

!:.-

OUTPUT

I

GAIN AMP
INPUT

GAIN AMP
OUTPUT

PEAK
OETECTOR
INPUT
TUH17918-7

FIGURE 2
20
10

I
IODmV

-10

:;

3DmV

--20

. .....
~

I

VIN- 300 IIIV

0

limY

-30

iii

>

-III

:~:.::~

-70

-n
ZD

I-+-H":'::H-fY.f"d'od

~

I
I

-50

-10

'"
~ -ZD I-+-H-H

3mV

co

:kllz

-3D
FILTER -

50 110 201 6DI Ik 2k

f-+~o ~~~~~~~~~

ZD

6k Ilk 2Bk

51 100 zoo SOD lk 2k

!lie llIk ZDk

FREQUENCY (Hzl

FREOUENCY (Hz)
TL/H/7918-8

TUH17918-9

FIGURE 3. Output vs Frequency

FIGURE 4. - 3 dB Bandwidth va
Frequency and Control Signal

Application Hints
The DNR system should always be placed before tone and
volume controls as shown in Figure 1. This is because any
adjustment of these controls would alter the noise floor
seen by the DNR control path. The sensitivity resistors R1
and R2 may need to be switched with the input selector,
depending on the noise floors of different sources, i.e., tape,
FM, phono. To determine the value of R1 and R2 in a tape
system for instance; apply tape noise (no program material)
and adjust the ratio of R 1 and R2 to open slightly the bandwidth of the main signal path. This can easily be done by
viewing the capacitor vol1age of pin 10 with an oscilloscope,
or by using the circuit of Figure 5. This circuit gives an LED
display of the voltage on the peak detector capacitor. Adjust
the values of R1 and R2 (their sum is always 1 k.!l) to light
the LEDs of pin 1 and pin 18. The LED bar graph does not
indicate signal level, but rather instantaneous bandwidth of
the two filters; it should not be used as a signal-level indica-

tor. For greater flexibility in setting the bandwidth sensitivity,
R1 and R2 could be replaced by a 1 kO potentiometer.
To change the minimum and maximum value of bandWidth,
the integrating capacitors, C3 and C12, can be scaled up or
down. Since the bandwidth is inversely proporlional to the
capaCitance, changing this 0.0039 jAoF capaCitor to
0.0033 jAoF will change the typical bandwidth from 965 Hz34 kHz to 1.1 kHz-40 kHz. With C3 and C12 set at 0.0033
jAoF, the maximum bandwidth is typically 34 kHz. A double
pole double throw switch can be used to completely bypass
DNA.
The capacitor on pin 10 in conjunction with intemal resistors
sets the attack and decay times. The attack time can be
altered by changing the size of C10. Decay times can be
decreesed by paralleling a resistor with C10, and increased
by increasing the value of C10.

1-311

•

Application Hints (Continued)
signal-to-noise measurement circuit is shown in Figure 6.
The DNA system should be switched from maximum bandwidttt to nominal bandwidth with tape noise as a signal
souree. The reduction in measured noise is the signal-tonoise ratio improvement. .

When measuring the amount of noise reduction of the DNA
system, the frequency response of the cassette should be .
flat to 10 kHz. The CelA weighting network has substantial,
gain to 8 kHz and any additional roll-off il1 the cassette player will reduce the benefits of DNA noise reduction. A typical

18

15

14

13

LM3115

4

1k

FROM PIN 10"":-_ _ _ _ _ _ _ _ _ _ _ _1-_.....
IN·LMI894'"

430
lID

TLlH17918-10

FIGURE 5. Bar Graph Display of Peak Detector Voltage

CASSETTE

CCIR
WEIGHTING
FILTER

AVERAGE
RESPONOIND
METER
TLlH/7918-11

FIGURE 6. Technique for Measuring SIN Improvement of the DNR System

1-312

Application Hints (Continued)
FOR FURTHER READING

Noise Masking

Tape Noise Levels

1. "Masking and Discrimination", Bos and De Boer, JAE8,
Volume 39, #4,1966.

1. "A Wide Range Dynamic Noise Reduction System",
Blackmer, 'dB'Magazine, August-September 1972, Volume
6, #8.

2. "The Masking of Pure Tones and Speech by White
Noise", Hawkins and Stevens, JAE8, Volume 22, #1, 1950.
3. "Sound System Engineering", Davis Howard W. Sams
and Co.

2. "Dolby B-Type Noise Reduction System", Berkowitz and
Gundry, Sert Journal, May-June 1974, Volume 8.
3. "Cassette vs Elcaset vs Open Reel", Toole, AudioscenB
canada, April 1978.
4. "CCIRI ARM: A Practical Noise Measurement Method"
Dolby, Robinson, Gundry, JAES, 1978.
'

4. "High Quality Sound Reproduction", Moir, Chapman Hall,
1960.
5. "Speech and Hearing in Communication", Fletcher, Van
Nostrand, 1953.

Printed Circuit Layout
DNR Component Diagram

v+

GND

VDUTlo---~

TLIH1791B-12

•
1-313

Section 2
Video Circuits

fII

Section 2 Contents
Video Circuits-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video--Definition of Terms .............. , . .. . . . .. .. . .. . .. . . . . . . . .. . .. .. . . . . . .. .. .. ..
Video Preamplifiers
LM1201 Video Amplifier System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1202 230 MHz Video Amplifier System .............................................
LM1203 AGB Video Amplifier System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1203A 150 MHz AGB Video Amplifier System.......................................
LM1203B 100 MHz AGB Video Amplifier System .......................................
LM 1204 150 MHz AGB Video Amplifier System. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . .
LM1205/LM1207 130 MHz/85 MHz RGB Video Amplifier System with Blanking ............
LM1208/LM1209130 MHz/100 MHz AGB Video Amplifier System with Blanking ..... ;.....
LM1212 230 MHz Video Amplifier System with OSD Blanking ............................
LM1281 85 MHz AGB Video Amplifier System with On Screen Display (OSD). . . . . . . . . . . . . ..
CRT Drivers
LM2416/LM2416C Triple 50 MHz CAT Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2418 Triple 30 MHz CAT Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2419 Triple 65 MHz CAT Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2427 Triple 80 MHz CAT Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Special Functions
LM1291 Video PLL System for Continu~us Sync Monitors ...............................
LM1295 DC Controlled Geometry Correction System for Continuous Sync Monitors. . . . . . . . .
LM1391 Phase-Locked Loop ........................................•................
LM1823 Video IF Amplifier/PLL Detector System.......................................
LM1881 Video Sync Separator.......................................................
LM1882. 54ACT174ACT715 Programmable Video Sync Generators.....................
LM2889 TV Video Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flat Panel Display Circuits
LM61 04 Quad Gray Scale Current Feedback Amplifier ..................................
LM8305 STN LCD Display Bias Voltage Source ..............................•.........
LMC6008 8 Channel Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High Speed Amplifiers
LM6152 DuallLM6154 Quad High Speed/Low Power 45 MHz Aail-to-AailllO Operational
Amplifiers .......................................................................
LM6161/LM6261/LM6361 High Speed Operational Amplifiers...........................
LM6162/LM6262/LM6362 High Speed Operational Amplifiers...........................
LM6164/LM6264/LM6364 High Speed Operational Amplifiers...........................
LM6165/LM6265/LM6365 High Speed Operational Amplifiers...........................
LM6171 Voltage Feedback Low Distortion Low Power Operational Amplifier ...............
LM6181 100 mA, 100 MHz Current Feedback Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM6182 Dual 100 mA Output, 100 MHz Dual Current Feedback Amplifier ................. ,
LM7131 Tiny High Speed Single Supply Operational Amplifier. . . . . . . . . • . . . . . . . . . . . . . . . . . .
LM7171 Very High Speed High Output Current Voltage Feedback Amplifier ................
High Speed Buffers
LM6121/LM6221/LM6321 High Speed Buffers ........................................
LM6125/LM6225/LM6325 High Speed Buffers ........................................

2-2

2-3
2-6
2-8
2-21
2-37
2-51
2-67
2-81
2-99
2-121
2-143
2-144
2-145.
2-149
2-153
2-160
2-165
2-174
2-183
2-188
2-195
2-203
2-215
2-224
2-228
2-229

2-232
2-233
2-240
2-248
2-256
2-263
2-277
2-294
2-315
2-337
2-338
2-344

tfI

National Semiconductor

Video Circuits Selection Guide
Video Preamplifiers

Device

Pixel
Clock
Rate
(MHz)

Typical
trlt,

(ns)

Bandwidth
(MHz)

Gain
(V/V)

Supply
Voltage
(V)

Comments

Package

LM1202

460

1.5/1.5

230

20.0

12

20-Pin
DIP

• Single Amplifier
• OV to 4V DC control on all functions
• Contrast control tracking for RGB applications

LM1212

460

1.5/1.5

230

20

12

20-Pin
DIP

• Single Amplifier System with OSD Blanking
• OV to 4V DC control on all fUActions
• Contrast control tracking for RGB applications

LM1204

300

2.0/2.3

150

6.5

12

44-Pin
PLCC

• Triple Amplifier System
• Output stage Blanking with adjustable Blanking
level
• OV to 4V DC control on all functions

LM1203A

300

2.5/3.4

150

6.5

12

28-Pin
DIP

• Triple Amplifier System
• OV to 12V DC brightness and contrast control

LM1205

260

2.6/3.6

130

7.0

12

28-Pin
DIP

• Triple Amplifier System with blanking
• OV to 4V DC control on all functions
• Spot killer

LM1208

280

2.8/3.4

130

7.0

12

28-Pin
DIP

• Triple Amplifier System with blanking
• OV to 4V DC control on all functions
'"
• Spot killer
• Full Range Drive Control (40 dB)

LM1201

220

2.5/3.0

110

8.0

12

16-Pin
DIP

• Single Amplifier
• OV to 12V DC brightness and contrast control

LM1209

200

3.2/3.6

100

7.0

12

28-Pin
DIP

• Triple Amplifier System with blanking
• OV to 4V DC control on all functions
• Spot killer
• Full Range Drive Control (40 dB)

LM1203B

200

3.3/3.7

100

6.5

12

28-Pin
DIP

• Triple Amplifier System
• OV to 12V DC brightness and contrast control

LM1207

170

4.3/4.3

85

7.0

12

28-Pin
DIP

• Triple Amplifier System with blanking
• OV to 4V DC control on all functions
• Spot killer

LM1281

170

4.3/4.3

85

7.0

12

28-Pin
DIP

• Triple Amplifier and OSD System
• Output stage Blanking
• OV to 4V DC control on all functions

LM1203

140

517

70

6.0

12

28-Pin
DIP

• Spot killer

2-3

• Triple Amplifier System
• OV to 12V DC brightness and contrast control

•

CRT Drivers

Device

Pixel
Clock
Rate
(MHz)

LM2427

160

Typical
tr/tf
(n8)

(MHz)

Gain
(V/V)

SUpply
Voltage
(V)

80

-13

80

Bandwidth

Package

,
3.5

12~Pin

In-Une
Plastic

'

Commenta

• Triple charinel CRT driver
• 50 Vpp output swing
• Closed loop design

LM2419

130

5

65

-15

80/12

11-Pjn
TO-220

• Triple channel CRT driver
• 5Q Vpp output swing
• Open loop design

LM2416

100

8

50

-13

80/12.

11-Pin
TO-220

• Triple channel CRT driver
• ·50 Vpp outpui swing
• Open loop design

LM2418

60

12

30

·-19

90/12

11-Pin
TO-220

• Triple channel CRT driver
• 50 Vpp output swing
• Open loop design

Video Channel Recommendations

Video
Preamplifier

LM1204
LM1205
LM1203A
LM1281
LM1281
LM1205
LMl203B
LM1207
LM1203

+

CRT
Driver

Typical
Calculated
Video
Channel
. , Ir/It (ns)

LM2427
LM2427
LM2427
LM2427
LM2419
LM2419
LM2419
LM2416
LM2418

6·
6.5·
6.5·
7·
7
7
7.5
10
15

'Estimated t,/1r includes affects of compensation networks

,.

2-4

Video Special Functions
Supply
Voltage

Device

Function

Package

Comments

LM1291

Horizontal
TimeBase

12V

28-Pin DIP

• Video PLL systems for Continuous Sync Monitors (15 kHz-135 kHz)
• Includes Sync Separator and clamp pulse generator
• Video mute signal indicates change in H input frequency

LM1295

Geometric
Correction

12V

24-Pin
Narrow DIP

• All correction terms are DC controlled (OV to 4V range)
• Vertical dynamic focus control signal
• Ramp generation for vertical deflection

LM1391

Horizontal
PLL

Over 10V

8-Pin DIP

• Built-in 8.6V regulator
• Unear balanced phase detector
• DC controlled output duty cycle

LM1823

Video
IFAmp&
PLLDet.

12V

28-PinDIP

• True synchronous video detector using PLL
• 9 MHz video bandwidth
• Excellent small-signal detector linearity

LM1881

Sync
Separator

5V-12V

8-PinDIP
8-PinSO

• Generates compOSite sync, vertical sync, back porch clamp pulse, and
Odd/Even field

LM1882

Sync
Generator

5V

20-PinDIP
20-PinPLCC

• 130 MHz maximum clock frequency
• Control via register programming with NTSC default values
• Interlaced and Non-Interlaced Formats

LM2889

TV Video
Modulator

12V

14-PinDIP

• Low distortion FMsound modulator
• Excellent oscillator stability
• DC channel switching

•
2-5

•

~

'0

r-~------------------------------------------------------------------------------,

.

tfI Nationa~ Semiconductor
""'"

c

,
o

:e

Video

.. Definition of 'Terms
~-

,

'a

:;;:
Active Video Signal: That portion of the video signal which· .
is above the blanking level and contains the picture informa-'
tion.
.

Continuous Sync: A circuit or monitor that has-the capability to lock on a range of different horizontal and vertical frequencies. The wide variety _of different video standards
makes a continuous sync monitor very desirable to prevent
e~rly' obsolescence.
- .

Arc Protection: Circuitry in the electronic systems connected to the CRT, to prevent them from being damaged by higl1.
voltage arcs within the CRT.
.
'. .
.

Contrast The range of dark and light values in a picture.
Cro...talk: An undesired signal interfering with a desired
Signal.
CRT: Cathode Ray Tube (display tube)

Arcover: An 'intemal arc between electrodes in- the CRT, '
which can aPiJly high voltages to the CRT terminals:
Aspect Ratio: The ratio of picture width to picture. height.
_
_
For the NTS9 ,system this is 4:3,
Back Porch: The section of the composite. video signal batween the trailing edge of the horizontal sync pulse and the
end of the blanking pulse period (wherrpicture information
begins).
-

CRT Driver: An amplifier which increases the 4 to 7V signal
output from a preamplifier up to 50 volts, for driving the
cathode of a CRT.
.
-

-

EMI: Electromagnetic Interference. Signals radiated or conductiKf from an electronic system which' can interfere with
the operation of another electronic system.

Bandwidth: The frequen~ at which the sine wilve response of an amplifier has dropped 3 dB below the amplitude at a lower reference frequency. The reference frequency needs to be specified where the frequency response of
the amplifier is very flat. The bandwidth frequency should be
at least 10 times the reference frequency. The output level
of the amplifier must be specified for the bandwidth specification.
Black Level: The DC voltage level in the picture signal
which corresponds to beam cut-off on the display tube.

Equalizing Pulses: Pulses of one half the width of the horizontal sync pulses. They are used to help the vertical sync
system of the monitor accommodate the half line difference
in the number of scan lines on successive fields in an interlaced standard.
Field: One half of a complete picture interval in an interlaced standard. A field will contain either all the odd numbered scanning lines or all the even numbered scanning
lines in the picture. For a non-interlaced standard the field
and frame are the same and is the complete picture interval.
Fly-back: See Horizontal Retrace.
Frame: A complete picture. For an interlaced standard, a
frame consists of two interlocking fields.

Blacker-than-Black: The amplitude region in the video signal that extends below the reference black level. The blacker-than-black is usually used for blanking.
Blanking: A portion of the video signal whose instantaneous amplitude makes the vertical and horizontal scan retrace not visible on the display tube.
Blanking Period: The period in the video signal where the
level is reduced to the blanking level, below which the display electron beam is cut-off. This allows non-visible retrace
of the beam from the right side of the display to the left side
at the end of each scan line (horizontal blanking) and nonvisible return of the electron beam from the bottom of the
display to the top.

Front Porch: The section of the composite video signal batween the end of the picture information on a horizontal line
(start of blanking) and the start of the horizontal synchronization pulse.
Gain: An amplifier output voltage divided by Input voltage. A
negative value of gain means the amplifier is an inverting
amplifier.
Horizontal Blanking: The blanking signal at the end of
each horizontal line that prevents the retrace of the display
tube electron beam from being visible.

Blooming: Defocussing of the picture in regions where the
brightness is too high.
Clamping: A process that established a fixed DC voltage
level for the picture signal. This is important for maintaining
the correct picture black level.
Composite Video Signal: A video signal that also contains
the sync information. For an RGB color system the sync
information is normally in the green video. Other RGB color
systems may have the sync information in all three video
signals. Many systems use separate syncs (no sync signal
on any of the video signals). These systems would have no
composite video signal.

Horizontal Retrace: The rapid return of the scanning electron beam from the right side of the raster to the left side.
Horizontal Scan Rate: The frequency at which the electron
beam in a monitor is being deflected horizontally.
Interlace: A scanning process in which each adjacent line
belongs to the alternate field. Note: most video standards
for monitors do not use interlace.

2-6

Large Signal Bandwidth: The bandwidth of an amplifier
where the output is specified near or at its largest expected
output swing. For CRT drivers the specified output is typically between 40 Vpp and 50 Vpp. For video preamps the
specified level is typically 4 Vpp.

RGB Video Abbreviation for Red, Green, and Blue video.
This means that there are three separate signals going to
the monitor for video, each signal represents one' of the
three colors. Monitors used with various computers today all
use RGB video.

Multi Sync: A circuit or monitor that has the capability to
lock on a discrete number of preselected different video
standards.

Smear: A picture condition where the displayed video levels
have an error with respect to what should be displayed. This
condition is normally due to thermal shifts in the CRT driver
due to a major change in the picture. As an example, if a
black box is displayed in the center of the screen with a
white background, the white background after the box may
be either more white than the background, or slightly darker
than the white background. This shift in the white level in the
horizontal direction after the black box is called smear.
Spark Gap: A component connected between CRT pins
(cathodes, G1, G2) and ground, to limit the arcover voltages
appearing on the CRT pins.
Sync: Abbreviation for synchronizing or synchronization.

Noise: In a video picture, 'noise' refers to random interference producing a salt and pepper pattern over the picture.
Overshoot: An (excessive) response to a unidirectional signal change. Overshoot is often used deliberately to enhance the appearance of the displayed picture.
Pairing: A partial or complete failure of interlace in which
scan lines of alternate fields fall in pairs, one on top of the
other.
Pixel: Contraction of the words picture element. A picture
displayed on a monitor is divided into very small segments,
called pixels.

Sync Level: The level of the synchronizing pulse tips.
tR/t.,: Rise timeltall time. During a video signal tranSition
from one level to another, the time required to go between
the 10% and 90% paints of the transition.

Pixel Clock Rate: The rate at which pixels of the incoming
video are occurring.
Preamplifier: An amplifier which increases the nominal
0.7V video signal to the 4 to 7V level, as part of a video
amplifier. Usually contains other functions, such as brightness, contrast and clamping.
Raster: The area on the face of the display tube that is
scanned by the electron beam. This is not always entirely
visible since monitors sometimes employ overscan so that
the edges of the raster are hidden by the faceplate.

Vertical Blanking: The blanking signal at the end of each
field.
Vertical Frequency: the rate at which a complete field is
scanned.
.
Vertical Retrace: The return of the electron beam from the
bottom of the display to the top after a complete field has
been scanned.
Vertical Scan Rate: The frequency at which the electron
beam in a monitor is being deflected verlically.
Video: The visible portion of the video signal representing
the picture. Also referred to as active video.

Resolution (Horizontal): The amount of resolvable detail in
the horizontal direction of the picture. This depends on the
high frequency and phase response of the monitor..
Resolution (Vertical): The amount of resolvable detail in
the vertical direction of the picture. This depends primarily
on the number of scan lines that are used and secondarily
on the size (shape) of the electron scanning beam.

2-7

_ r----------------------------------------------------------------------------,

~

~

Se~iconductor

tJ1'National

LM 120 1 Video Amplifier System
• Provisions for external gain set and peaking of video
amplifier
.

General Description
The LM1201 is a wideband video amplifier system intended
for high resolution monochrome or ",GB, monitor applications. In addition to the widel;land video amplifier the
LM1201 contains a gated differential input black level ciamp
comparator for brightness control' and an attenuator circuit
for contrast control. The LM 1201 also contains a voltage
reference for the video input. For medium resolution AGB
color monitor applications also see the LM1203 Video Amplifier System data sheet.

Features
• Wideband video amplifier (200 MHz @ - 3 dB)
• Attenuator circuit for contrast control (>40 dB range)
• Externally gated comparator for brightness control

• Video input voltage referenCe
• Low impedance output driver

Typical Applications
•
•
•
•
•
•
•
•

CAT videq amplifiers
Video switches
High frequency video pr\ilamplifiers
Wideband gain controls
PC monitors
Workstations
Facsimile machines
Printers

Block and Connection Diagram
VIDEO

IN
16

Vce l
15

CONTRAST
CAP

14

CONTRAST
CAP

13

Vce 2

DRIVE

Vce 3

12

11

10

ClAMP (-) .

9

504

504

567

2

GNDI

ClAIotP
CAP

50.0.

CONTRAST

ClAMP

ClAMP (+)

GATE
FIGURE 1
Order Number LM1201M or LMI201N
See NS Package Number MISA or NISE

2-8

GND 2

8
VIDEO
OUT

Tl/H/l0006-1

r-

Absolute Maximum Ratings
- 65·C to + 150"C
Storage Temperature Range (TSTG)
Lead Temperature (Soldering, 10 sec.)
265·C
ESD Susceptibility
2kV
Human body model: 100 pF discharged through a 1.5 kG
resistor

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee Pins 10, 12, 15
to Ground Pins, 1, 7
13.5V
Voltage at Any Input Pin (VIN)
Vee ~ VIN ~ GND
Video Output Current (IB)
28mA
Package Power Dissipation at TA = 25·C
1.56W
(Above 25·C derate based on (6JA and TJ)
80·C/W
Package Thermal Resistance (6JA) N16E
Package Thermal Resistance (6JA) M16A
100"C/W
Junction Temperature (TJ)
150"C

Operating Ratings

Electrical Characteristics See Test Circuit (Figure 2), TA =
DC Static Tests S9 Open; V4 =
Symbol

(Note 4)

Temperature Range
Supply Voltage (Vce>

10.8V

O"Cto +70·C
13.2V

s: Vcc s;

25·C;VCC1 = VCC2 = VCC3 = 12V

6V;V5 = OV;V6 = 2.0V unless otherwise stated

Parameter

Is

Supply Current

Va

Video Input Reference Voltage

Conditions
Vee Pins 12,15 Only

Typical

Tested
Limit
(Note 1)

Design
Limit
(Note 2)

Units
(Limits)

45

57

2.65

2.4

mA(max)
V(min)

2.95

V(max)

116

Video Input Bias Current

(Va-V16)/10 kG

5.0

20

p.A(max)

VSl

Clamp Gate Low Input Voltage

Clamp Comparator On

1.2

0.8

V(min)

VSH

Clamp Gate High Input Voltage

Clamp Comparator Off

1.6

2.0

V(max)

ISl

Clamp Gate Low Input Current

Vs = OV

-0.5

-5.0

p.A(max)

ISH

Clamp Gate High Input Current

Vs = 12V

0.005

1

p.A(max)

12+

Clamp Cap Charge Current

V2 = OV

1

0.55

mA(min)

12-

Clamp Cap Discharge Current

V2 = 5V

-1

-0.55

mA(min)

VBl

Video Output Low Voltage

V2 = OV

0.5

0.9

V(max)

VBH

Video Output High Voltage

V2 = 5V

8.5

8.0

V(min)

VOS

Comparator Input Offset Voltage

±0.5

±25

mV(max)

V6-V9

AC Dynamic Tests S9 Closed, Vs =
Parameter

Symbol
Avmax

Video Amplifier Gain

OV, V6 = 4V
Conditions

V4 = 12V

Typ

Tested
Limit (Note 1)

8

5.5

Design
Limit (Note 2)

Units
(Limits)
VIV(min)

b.Av5V

Attenuation @ 5V

Ref: Av max, V4 = 5V

-10

dB

b.Av2V

Attenuation @ 2V

Ref: Av max, V4 = 2V

-45

dB

THD

Video Amplifier Distortion

V4 = 5V, Vo = 1 Vp-p

0.3

%

f(-3dB)

Video Amplifier Bandwidth (Note 3)

V4 = 12V, Vo = 100 mVrms

200

tr

Output Rise Time (Note 3)

Vo = 4Vp_p

2.5

ns

tf

Output Fail Time (Note 3)

Vo = 4Vp-p

3

ns

Note 1: These

170

MHz(min)

parameters are guaranteed and 100% production tested.
Note 2: Design limits are guaranteed (but not 100% production tested). These limits are not used to calculate outgoing quality levels.
Note 3: When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuR board without socket is recommended.
Note 4: Operating Ratings indicate condRions of which the device is functional, but does not guarantee specific parformance IimHs. For guaranteed spacifications
and test condRions, see Eleclrical Characteristics. The guaranteed specifications appiy only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
2-9

B:
.....
~
.....

..________~~------._--~---~~~----._()v~
+12V
200n

10
V~3

R3

R9

LU1Z0l D.U.J.

10k

10k

TL/H/l0006-2

FIGURE 2. LM1201 AC/DC Test Circuit
.Note: When Vs ,;; O.8V and 89 is closed, DC feedback around the Video Amplifier Is provided by the clamp comperator. Under these ccndltions sine wave or 50%
duty cycle square waves can be used for _ purposes. The low frequency dominant pole is determined by C2·at'l'ln 2. GapeciIor C9 at pin 9 preVents overloading
the «lamp comparator invarting .Input. See applications section for additional information.

GNO

, S!--....-'\/th....

3304

5.lk
.43k

1000 pF
TUHI10006-3 '

FIGURE 3. Typical Application of the LM1201

• 30n resistor is added to the Input pin for protection agelnst current surges coming from the 10 ,.F Input capacitor. By Increasing this resistor to well over loon
the rise and fall times of the LMI201 can be Increased for EMI considerations.
.
.
.

2-10

APPLICATIONS INFORMATION
supplied by coaxial ~ble which is terminated in 750 at the
monitor input and internally (l.C coupled to the video amplifier. T~e input signal is approximately 1V peak-to-peak in aniplitude and at the input of the high voltage video section,
approximately 6V peak-to-peak. At the cathode of the CRT
the video signals can, be as high as 60V peak to peak. The
block in Figure 4 'labeled "Video Amplification with DC Controlled Gain/Black Level" contains the function of the
LM1201 video amplifier system.

Fl{}ure 4 shows the block diagram of a typical analog monochrome mon~or. The monitor is used with CAQ/CAM work
stations, PCS, arcade games and in a wide range of other
applications that benefit from the use of high resolution display terminals. Monitor characteristics may differ in such
ways as sweep rates, screen size, or in video amplifier
speed ,but will still be generally configured as shown in FI{}ure 4. Separate horizontal and vertical sync signals may be
required or they may be cOntained as a composite signal in
the video input signal. The video input signal is usually

Sync In

V

VERllCAL/HORIZONTAL SWEEP
AND POWER SUPPLY'
CIRCUITS

H

VIdeo In

Contrast

TLlH/10006-4

FIGURE 4.,Typlcal MonochromeMonHor Block DIagram

2-11

9-

~

....

:5

r------------------------------------------------------------------------------------------,
Circuit Description

fl{Jure5.. is a block diagram of, the l-M1201 along ~th the
colltr$t an,d brightn~ss controls. The' coritrast control. is S
Dc operated attenuator wHich varies the AC gain of, tile
amplifier Wittio,Ut introducing
signal diStortions or DC
output shi~. The brightness control funCtion requii"es Ii
"sample and, hpld" circuit (black leV'el clamp) which holds
the DC bias of 'the video amplifier and CRT cathQdes constant during the black level reference portion ofthe Video
waveform. The clamp comparator, when gated'on during
this reference period, will charge or discharge the clamp
capacitor until the non-inverting input of the clamp comparator matches that of the invert(ng input voltage which was'set
by the brightness control.
'
Figure 6 is a simplified schematic of the LM1201 video amplifier along with the recomlYlended external; componen~.
The IC pin numbers are circled with all external compOne~ts "
shown outside of the dashed line. The video input is applied

to pin 16 ~ia the 1Op.F coupling capaCitor. '[)C bias to t~e
video input is 'through the 10 kO resistor which is connected
to the, 2.6V referenCe at 'pin 3. The IQw frequency roll-off df
the, amplifier is' set by these 'two compC!l1snts. Tral)siStor 01
bufferS the videa Signal to the base of 02. The 02 collector
current is th~n directed to the V~1 SUpply through 03 or to
VCC2 through 04'lmd the 500n load resistor depending
upon'the differential DC voltage at th~ ~es of, Q3 and 04.
The 03 and Q4 differential baSe voltage is determined by
the contrast 'control circuit which is described below. The
black level DC voltage at the collector of 04 is maintained
by 05 and 06 which are part of the black level clamp circuit
also described below. The video signal appearing at the collector of Q4 is then buffered by 07 and level shifted down
by Z1 and 08 to the base of 09 which will then provide
aclditional System gain.

any

Extemal
High Voltage
VIdeo

or',
75A~

Clamp Gate

Lr-----'
TL/H/l0006-5

FIGURE 5. Block Diagram of LM201 Video Amplifier with Contrast and Black Level Control

"

..

2-12

(')

::;'
()

C

::;
C
CD

+12VO

'u'

,

fI)
()

,

""I

i

~3

----------------------~~

0'
:::J

g

HV

RIO

a
<:
!

500D.

Video
In

~

Co>

50D.

T

75D.

'O

::I

Rload
500D.

LV

I'F

10k

--------1'-----y-------------10 pF)~ a
more efficient method of emitter pull down would be to connect a suitable resistor to a negative supply voltage. This
has the effect of a current sour~ pull down when the minus
supply voltage is -12V, and the emitter current is approximately 10 mAo The system gain will also iflcrease slightly
because less signal will be lost across the internal 500 resistor. Precautions must be taken to prevent the viQfiIO

.
I
I

-----------~---

output pin from going below ground since IC substrate currents may cause erratic operation. The collector current
from the video output transistor is returned to the power
supply at VCC3, pin 10. When making power dissipation calculations note that the datasheet specifies only the VCC1
and VCC2 supply currents at 12V. The IC power dissipation
contribution of VCC3 is dependent upon the video output
emitter pull dpwn load.
In normal operation the minimum black level voltage that
can be set at the video output pin is approximately 2V at
maximum coirtrast setting. In applications that require a lower black level voltage, a resistor (approximately 16 kO) can
be, added from pin 3 to ground. This has the effect of raising
the' DC voltage at the collector of Q4 which will extend the
range of the black level clamp by allowing 05 to remain
active. In applications that require video amplifier shutdown
due to fault conditions detected by monitor protection circuits, pin 3 and the wiper arms of the contrast and brightness controls can be grounded without harming the IC. This
assumes some series resistance between the top of the
control pptentiometers and Vcc.
F/{/ure '7 shows the internal construction of the pin 3 2.6V
rEiference 'circuit which is used to provide temperature and
supply voltage tracking compensation: for the video amplifier
input. The value 'of th&,external DC biasing resistors should
, not be larger than 10 kO when using more than one
LM1201 (e.g. in RGB systems) because minor differences in
input 'bias currents on the individual' video amplifiers may
~uSe, 01f~ets in gain.

Vcr,2

--------------- .
I

I

I
I
I

R28
12k

I

to Video Input

I
I
I
I
I
I

: Z3

Vee

I

10k

....~ Contrast
Control

+-JV\fIt-+--<~~_:f'

10k
. ...."...,."....-13

1l./H/l0006-7

FIGURE 7. LM1201 VIdeo Input Voltage Reference and Contrast Control Circuits

2-14

r-----------------------------------------------------------------------------~

Circuit Description

(Continued)
Figure 7 also shows how the contrast control circuit is configured. Resistors R23, R24, diodes 03, 04, and transistor
013 are used to establish a low impedance zero TC half
supply voltage reference at the base of 014. The differential
amplifier formed by 015, 016 and feedback transistor 017
along with resistors R27, R28 establish a differential base
voltage for 03 and Q4 in Ftgure 6. When externally adding
or subtracting current from the collector of 016, a new differential voltage is generated that reflects the change in the
ratio of currents in 015 and 016. To provide voltage control
of the 016 current, resistor R29 is added between the 016
collector and P!n 4. A capaCitor should be added from pin 4
to ground to prevent noise from the contrast control pot
from entering the IC.
FlfJUre 8 is a simplified schematic of the clamp gate and
clamp comparator section of the LM1201. The clamp gate
circuit consists of a PNP input buffer transistor (018), a PNP
emitter coupled pair referenced on one side to 2.1V (019,
020) and an output switch (021). When the clamp gate
input at pin 5 is high (>1.5V), the 021 switch is on and

shunts the 11 1mA current to ground. When pin 5 is low
«1.3V), the 021 switch is off and the 11 1mA current
source is mirrored or "turned around" by reference diode
05 and 026·to provide a 1mA current source for the clamp
comparator. The inputs to the comparator are similar to the
clamp gate inp4l except that an NPN emitter coupled pair is
used to control the current which will charge or discharge
the clamp capacitor at pin 2. PNP transistors are used at the
inputs because they offer a number of advantages over
NPNs. PNPs will operate with base voltages at or near
ground and will usually have a greater reverse emitter-base
breakdown voltage (BVebo). Because the differential input
voltage to the clamp comparator during the video scan period could be greater than the BVebo of NPN transistors,
resistor R34 with a value one half that of R33 or R35 is
connected between the bases of Q23 and 027. This resistor will limit the maximum differential input to 024, 025 to
approximately 350 mV. The clamp comparator common
mode range extends from ground to approximately 9V and
the maximum differantial input voltage is Vee and ground.

r-

....~
....~

Clamp
Gate
In

TLlH/10006-8

FIGURE 8. Simplified SChematiC of LM1201 Clamp Gate and Clamp Comparator Circuits

2-15

•

Applications Information
FJgUr6 9 shows the configuration of a high frequencY amplifier with nOn'gated DC feedback; Pin 5 is tied low to turn on
the clamp comparator (feedback amplifier)., The inverting input (pin 9) is connected to the amplifier output from a low

pass filter. Additional low frequency filtering is provided by
the clamp capaCitor. The Drive pin is grounded to allow for
the, widest range of:output signals. Maximum output SWing is
achieved ,when the DC output is set to approximately 4.5V.

.7J.1F'~"

13

14

12

11

10

lM1201
3

5

4

7

8
YOUT

,GND
+12Y

+12Y

330n

~

TL/H/l0006-9

FIGURE 9. High Frequency Ampllfler/AUenuator Circuit with Non-Gated DC Feedback (Non-Video Applications)

2-16

Applications Information

(Continued)
Figure 10 shows the LM1201 set up as a video amplifier
with biphase outputs. Because the collector of output transistor 012 is the only internal connection to VCC3, a 750
termination to the power supply voltage allows one to obtain
inverted video at pin 10. Black level on the non-inverted
video output (pin 8) is set to 1.5V by the voltage divider on
pin 6.
Figure 11 shows how a high frequency video switch may be
designed using multiple LM1201 devices. All outputs can

be OR'ed together assuming no more than one channel is
selected at any given time. Channel selection is accomplished by keeping the appropriate SELECT SWITCH open.
Closing the SELECT SWITCH on a given channel disables
that channel's output (pin 8) leaving it in a high impedance
state. A single pair of contrast and brightness potentiometers control the selected channel's gain and output DC
level.

r-____________. .~V~
+12V

...........------~>M_---.....-..
2004

O.lPF~

O.l p F

16

15

14

T

13

...7_5_4_ _ _

514

V

O.lpF

12

11

10

9

UA 120 1

3

"

5

<.lJO.5V~

2001}

7

754

Contrast
Control

TUH/l0006-10

FIGURE 10. Preclamped Video Amplifier with Blpha.. Outputs

fJI

2-17

..
~
....
~

r-------------------------------------------------------------------------------------~

Applications Information (Continued)
\

,Vee
---..ItJV\ro---.......- ......_-_...........O":.!2V

>,,'

r-...

"

" :.' r--U-'1.
15

9

LM1201
2

5

3

200n

8

7

6

,

\.

",

Solected
Open to .010ct',: O. ~ pF
Clo.. to dl..bl.

T

to
pin"

V

to
pin 5

Video
Out

to
pin 6

V~
+12V

,O"PF~
VIN

0.1 p.F

1 pF

~r

*

15

10

9

Lt.11201
lPF~

2

3

"

5

S.lected
Clamp
Gat. In

200n

6

7

8

Brightn...

TUH/10006-11

FIGURE 11. High Frequency Video Switch with Common Contrast and Brlghtneas Controls

2-18

Rise Time No Socket

,Rise Time In Socket

TllH/l0006-12

TllH/l0006-13

Fall nme No Socket

Fall Time In Socket

Tl/HI10006-14

TllH/l0006-15

HP8082 pulse generator
HP10241A 10:1 voltage divider
HP1120A 500 MHz FEr probe
Tektronix 2465A 350 MHz scope

• Actual output signal swings
4 Vp-p (10:1 divider Is used)
• Contraet Is set to maximum
• VIN '- sOo mVp-p
• RORIVE - 500
• Vertical scale Is actually tV/dlv and not
100 mV/dIv due to 10:1"attenuator used.
• Outputs are centered at 4V DC.

Scale for All Photos-Vert: 1VlDIY
Hartz: 5 ns/DIY

•
2-19

9- , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~

~

).'

".

".

,\'1:.

TL/H/l0006-16

Note: The p.c.b. layout shown above is .suitable for eValuating the performance of the LM1201. Although it is similar to the
typical application circuit of figure 3, there is no c.r.t. driver stage. Instead, a feedback resistor is connected between Pins 8 and
9 and the brightness control Is connected to Pin S. Again, for best results, a socket should not be used for the LM1201.

,-" ~

COMPONENT VALUES:
Rl
750, 5%, 114 watt, carbon composition
R3
10 kO, 5%, 114 watt, carbon composition
R4
500, 5%, 114 watt, carbon composition
R5
2000, 5%, 114 watt, carbon composition
RS
750, 5%, 114 watt, carbon composition
3300, 5%, 114 watt, carbon composition
R7
R8
S80 kO, 5%, 114 watt, carbon composition
R9
Rl0
Rll
R12
R13
R14
R15

10 kO, trim pot, helitrim model 91
5.1 kO, 5%,1/4 watt, carbon composition
43 kO, 5%, 114 watt, carbon composition
12 kO, 5%,1/4 watt, carbon composition
10 kO, trim pot, helitrim model 91
2 kO, 5%, 114 watt, carbon composition
2000, 5%, 114 watt, carbon composition

ICl
IC2

LM1201
LMl881

Cl
C2
C4
C5

C6
C7
C8
C9
Cl0
Cll
C12
C13
C14
C15

0.1 p.F, ceramic
0.1 p.F, ceramic
0.1 p.F, ceramic
0.1 p.F, ceramic
10 p.F/SV, electrolytic
0.1 p.F, ceramic
0.1 p.F, ceramic
0.1 p.F, ceramic
0.1 p.F, ceramic
0.1 p.F, ceramic
0.1 p.F, ceramic
100 p.F/15V, electrolytic
0.001 p.F, mica
0.1 p.F, ceramic

2·20

t!lNational Semiconductor

LM1202 230 MHz Video Amplifier System
General Description
The LM1202 is a very high frequency video amplifier system
intended for use in high resolution monochrome or AGB
color monitor applications. In addition to the wideband video
amplifier the LM 1202 contains a gated differential input
black level clamp comparator for brightness control. a DC
controlled attenuator for contrast control and a DC controlled· sub contrast attenuator for drive control.. The DC
. control for the contrast attenuator is pinned out separately
to provide a more accurate control system for AGB color
monitor applications. All DC controls offer a high input impedance and operate over a OV to 4V range for easy interface to bus controlled alignment systems. The LM1202 openites from a nominal 12V supply but can be operated with
supply voltages down to BV for applications that require reduced IC package power dissipation characteristics.

Features

• Externally gated comparator for brightness control
• OV to 4V high input impedance DC contrast control
(>40 dB range)
• OV to 4V high input impedance DC drive control
(±3 dB range)
• Easy to parallel three LM1202s for optimum color tracking in AGB systems
• Output stage clamps to O.65V and provides up to 9V
output voltage swing
• Output stage directly drives most hybrid or discrete
CAT amplifier stages

Applications
High resolution CAT monitors .
Video switches
Video AGC amplifier
Wideband amplifier with .gain and DC offset'control

• Wideband video amplifier
(L3dB = 230 MHz at Vo = 4 Vpp)
• t r• tf = 1.5 ns at Vo. = 4 Vpp

Biock and Connection Diagram

VIDEO OUT

ATTENUATOR IN+
ATTENUATOR IN-

1
2

CONTROL OUT+
CONTROL OUT-

3

GROUND

1------------'
1-____________-'

CLAMP CAP
DRIVE CAP
DRIVE CAP

1----------.

CLAMP(+)

SYSTEM Vee 1

0

CONTRAST CONTROL

8

DRIVE CONTROL

9

CLAMP(-)

I-----------...J
I------------------.....J

CLAMP GATE
GROUND

TL/H/11440-1

Order Number LM1202N or LM1202M
See NS Package Number N20A or M20B

2-21

•

Absolute Maximum Ratings (Note 1)

• !y'

JUnction Temperature (TJ)
Storage Temperature Range (Tstgl

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for avallabilHy and specHlcatlons.
Supply Voltage Vee Pins 4,7,16 t9
:,
Ground Pins 5, 13, 15

.'

.~

Vee ~ VIN ~ GND
Voltage at Any Input Pin (VIN>
2SmA
Video Output Current (117)
Package Power Dissipation' at A = 25°C
1.56W
(Above 25°C Derate Based 8JA and TJ)
Package Thermal ResistanCe (8JN
N20A
68"C/W
. , "
...
90"C/W
'M20B

t

.265°C
1.5kV

-20"C to +SO"C
SV S; Vee S; 13.2V

SupplyVoltage (Vee)

Electrical Characteristics
Test Circuit (Figure 1), TA
V19:= 4V, VS = 4V',,(9 = 4V, V14 ~ OV u,nless otherwise noted::
Symbol

1~C

Ope..a~iog Ratings (Note 2)
. Temperature Range

s.e

'DC

,'"

- 65°C to +'1 ~O"C

Lead Temperature
N Pa<;kage(Soldjlring,,10 sec.)
ESD SUsCeptibi6ty
Human Body Model: 100 pF Discharged
", .
through a 1.5k Resi!;tor

"3:5V"

"

.,

:-

==

"

Typical
(Note 3)

Conditions

Parameter

RLoad ,;"

Co (Note 5)

25°C, V4 = V7 = V16 = 12V, S1 Open,
Limit
(Note 4)

Units

4S,'

60

iijA'(max)

2.4

2

V (min)
V (max)

Is4,7,16

Total Supply Current

V6

Video Input Bias Voltage

V14L

Clamp Gate Low Input Voltage

, Clamp Comparator On

O.S

V14H

Clamp Gate High InputVoltage

'. Clamp Comparator Off

2

114L

Clamp Gate Low Input Current

V14 = OV

-0.5

114H

Clamp Gate High Input Current

V14 = 12V

0.005

112+

Clamp Cap Charge Current

V12 = OV

112-

Clamp Cap Discharge Current

V12 = 5V

V17L

Video Output Low Voltage

V12 = OV

V17H

Video Output High Voltage

V12 = 6V

Vos

' Comparator Input Offset Voltage

V1S - V19

,

,

SOO

. V (min)

p.A
p.A
500

p.A (min)

-500

',pA(min)

0.2

0.65

V (max)

10

9

V (min)

15

±50

mV(max)

'~'''':800

AC Electrical Characteristics
V19 = 4V, VS = 4V,
Symbol

..

',.'

l,.

va, =

See Test Circuit (FiglH8 1),lA = 25°C, V4 = V7 = V16 = 12V, S1 Closed,
4V, V14 = OVunlessotherwlse noted.
'

,

Parameter

Conditions

Typical
(N~tCl3)

Umit
(Note 4)

Units

16

VIV(min)

RIN

Video Amplilier Input Resistance

fiN = 12 kHz.

20

AV max

Video Amplifier Gain

Vs = 4V, Vg'= 4V

20

b.Av 2V

Attenuation at 2V

Ref: Av 'max, Va = 2V

'-6

llA.v O.5V

Attenuation at 0.5"

' Ref: Av max, Va= 0.5V

-38

-23

dB (rIlin)

kG

dB

b. Drive

b.,Gain Range

Vg= OVto4V

6

5

dB (min)

THD

Video Amplifier Distortion

Vo = 4 Vpp, fiN = 12 kHz

0.5

1

% (max)

'-a dB "

Video Amplifier Bandwidth (Note 6)

Vo = 4Vpp

230

Output Rise Time (Note 6)

Vo = 4Vpp

1.5

?

ns(max)

Output Fall Time (Note 6)

Vo = 4Vpp

1.5

2

ns(max)

tr,
tf

"

.'

.

'

MHz

"

,

2·22

Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings Indicate conditions for which the device is functional but do not glJlll"8O!lI9 SpecifIC performance limits. For guaranteed specifications and

test conditions see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions .listed. Some performance characteristics may
degrade when the device Is not operated under the listed test conditions.
Note 3: Typical specificatipns are specified at

+ 25"C and represent the most likely perametric norm.

Note 4: Tested limits are guaranteed to National's AOQL (Average Outgoing Ouality Level).
Note 5: The supply current specified is tho quiescent current for VCC1, VCC2 and VCC3 with RLoad ~ "", see F/gur9 1'8 test circuK. The total supply current also
depends on the output loed, RLoad. The increase in device power dissipation due to RLoad must be taken into aocount when operating the device at the maximum
.
ambient temperature.
Note 6: When measuring videc amplifier bandwidth or pulse rise and fall times, a double sided full ground plane prirried circuK board is recommended. The
measured rise and fall times are effective rise and fall times, taking into account the rise and fall times of the generator and the oscilloscope.

Test Circuit
10

VIDEO
OUT

Vee (+12V)

Vee (+12V)

LM1202
TOP VIEW

VIDEO

IN
51

30
CLAMP GATE

Uk

(4V)

iN
lOOk ~~I---....--t

•
DRIVE CAP 0.0 I pF
TLlH/11440-2

FIGURE 1. LM1202 Teat Circuit

2-23

Typical Performance Characteristics (Vee =

12V. TA = 25"C Ilnless otherwise specified)

QuiesCent Supply Current vs SUpply Voltage

"

~OAD~oJ

60

0

55

..s'<
...

50

:>

45

..'"
Z

-

.;'

40

~

CD'
.3

,/

z
52
!;(

35

./

-2
-3

:>

...
z

I-

!;(

V~

:>

'"

, / I-"""

./r

-1

~

V

I-

...........

Attenuation vs Drive Control Voltage

-4

/

-5

../

-6

30

7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5

~

/

V

V

~

0.5

1.0

1.5

2.0

2.5

3.0

3.5

TL/H/11440-12

TL/H/11440-13

Contrast vs Frequency

Drive vs Frequency

10

CD'
.3

~

-30

~
z

-50

z

9

Va =4V

~

..............

.....

CD'
.3

"'""'IIii

~

~

i'"

I

.
'"

Jv

~

I
I

"z

1"'\

,

II
;'

II

ov

-90

I

-1

1

10

100

1

400

fREQUENCY (MHz)

10

1\
100

400

,FREQUENCY (MHz)
TUH/11440-14

TL/H/11440-1S

Attenuation vs Contrast
Control Voltage
10

o

......

..... -10

/

-20
z'

~

~

i."..oo' . "

-

52

";1

II ,

va =1-

...

Va =4V

-70

,...

IVa =4V

7

-" I-.~

,./

0.40V
0.33V
0.27V

I-

:c
CI

---

0.9V
0.S4V

-10

4.0

DRIVE CONTROL (PIN 9) VOLTAGE

SUPPLY VOLTAGE PINS 4. 7 AND 16 (V)

~ -30

~ ~40

S -50
-60
-70

V
o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
CONTRAST CONTROL (PIN 8) VOLTAGE

2·24

TUH/II440-16

Circuit Description
Figure 2 shows a block diagram of the lM1202. video amplifier along with contrast and brightness (black level) control.
Contrast control is. a DC-operated attenuator which varies
the AC gain of the amplifier. Signal attenuation (contrast) is
achieved by varying the base drive to a differential pair and
thereby unbalancing the current through the differential pair.
As shown in Figure 2, pin 20 provides a 5.3V bias voltage for
the positive input of the attenuator (pin 1). Pin 3 provides a
control voltage for the negative input (pin 2) of the attenuator. The voltage at pin 3 varies as the voltage at the contrast
control input (pin 8) varies thus providing signal attenuation.
The gain is maximum (0 dB attenuation) if the voltage at pin
8 is 4V and is minimum (maximum attenuation) if the voltage
at pin 8 is OV. The OV to 4V DC-operated drive control at pin
9 provides a 6 dB gain adjustment range. This feature is
necessary for RGB applications where independent gain adjustment of each channel is required.

voltage at the minus input of the comparator matches the
voltage set at the plus input of the comparator. During the,
video portion of the signal, the clamp comparator is disabled
and the clamp capacitor holds the proper DC bias. In a DC
coupled cathode drive application, picture brightness function can be achieved by varying the voltage at the comparator's plus input. Note that the back porch clamp pulse width
(tw in FlflUrB 2) must be greater than 100 ns for proper
operation.

VIDEO AMPLIFIER SECTION (Input Stage)
A simplified schematic of lM1202's video amplifier input
stage is shown in FigurB 3. The 5.4V zener diode, 01, 06
and R2 bias the base of 07 at 2.6V. The AC coupled video
signal applied to pin 6 is referenced to the 2.6V bias voltage.
Transistor 07 buffers the video signal, VIN, and 08 converts
the voltage to current The AC collector current through 08
is Ice = VIN/R9. Under maximum gain condition, transistors
09 and 011 are off and all of Ice flows through the load
resistors R10 and R11. The maximum Signal gain at the
base of 013 is, AVl = -(R10 + R11)/R9 = -2. Signal
attenuation is achieved by varying the base drive to the differential pairs 09, 010 and 011, 012 thereby unbalancing
the collector currents through the transistor pairs. Base of
010 is biased at 5.3V by externally connecting pin 1 to pin
20 through a 100n resistor. Pin 2 is connected to pin 3
through a 100n resistor. Adjusting the contrast voltage at

The brightness or black level clamping requires a "sample
and hold" circuit which holds the DC bias of the video amplifier constant during the black level reference' portion of the
video waveform. Black level clamping, often referred to as
DC restoration, is accomplished by applying a back porch
clamp signal to the clamp gate input pin (pin 14). The clamp
comparator is enabled when t.he clamp signal goes low during the black level reference period (see FigurB 2). When
the clamp comparator is enabled, the clamp capacitor connected to pin 12 is either charged or discharged until the

T

VIDEO IN CI

RI

10 pF

75

C2

0.01

pr

RIO
510'

UV

R.l

lOOk*,

El

UV

SYSTEM Vee I
CONTRAST CONTROL

Rsl

DRIVE CONTROL

lOOk*,
WHITE

BLACK

I- BLACK LEVEL REFERENCE PERIOD
BACK PORCH CLAMP SIGNAL

U

--I I- tw > lOOn.

U

VOL';; 0.8V _

Ur------~::~V~OH~~~I~,8~V______~
Tl/H/II440-3

FIGURE 2. Block Diagram of the LM1202 Video Amplifier
with Contrast and Brightness (Black Level) Control

2-25

~ r---------------------~----------------------------------------------------------~

~
..-

~

Circuit Description (Continued)
pin Ii produces ~. cont\:6r \lOltage~t Ilin 3 w~k:h c'lriv~s!he
ba~ 1.5V) the 089 switch is
on and shunts the 200 p.A current from current source 090
to ground. When pin 14 is low « 1.3V) the 089 switch is off
and the 200 p.A current is mirrored by the current mirror
comprised of 091 and 075 (see Figure 8). Consequently
the clamp comparator comprised of the differential pair 074
and 077 is enabled. The input of the clamp comparator is
similar to the clamp gate except that an NPN emitter coupled pair is used to control the current that will charge or
discharge the clamp capacitor extemally connected from
pin 12 to ground. PNP transistors are used at the inputs
because they offer a number of advantages over NPNs.
PNPs will operate with base voltages at or near ground and
will usually have a greater emitter base breakdown voltage
(BVebo). Because the differential input voltage to the clamp
comparator during the video scan period could be greater
than the BVebo of NPN transistors, a resistor (R63) with a
value one half that of R60 or R68 is connected between the
bases of 071 and 079. The clamp comparator's common
mode range is from ground to approximately 9V and the
maximum differential input voltage is Vee.

2-29

LM1202

o

a"

c;::;:

---------------------------------------------------------------~---------.
i
lUI
Vee

In

R40
SDk

R44
2k

R47

.s"
:g.:::J

.~

RS3
6•.5k

&.4k

'I

'I I

RS4
13k
TO VIDEO AMP
011

9
a

I , :i'
I s:::
I ~
II
I
I

TO VI,DEO AMP
012

7.3V
JjIAS
R46
50

~

S.4V
Zener

R41
SDk

R42
100

'R48
12.8k

'RSI
10k

.

.

- - - - - - - - - - - - - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1- _ _ _ _ _ _ - .... _ _ _ _ _ _1_ - - , . - - - - _ ... - - ' - - - -

9

10

11

DRIVE CONTROL INPUT

DRIVE,CAP

DRIVE CAP

:.:'

,:
-TL/H/ll440-,7

FIGURE 6. Simplified Schematic of the LM1202 Drive Control

Circuit Description (Continued)
Vee

I'

R70
200

I
I
I
I

._-- -----------------------------------------14

CLAMP GATE INPUT
TLlHfll440-8

FIGURE 7. Simplified Schematic of the LM1202 Clamp Gate Circuit

2·31

Circuit Description

(Continued)

---------------------------------------~-------------Vee
RSt
100

R61
SOk

SO I'A

PUSH PULL OUTPUT CURRENT
TO CLAMP CAP

400l'A

SO I'A

I
t

12r-T---~------~--~

R60
SDk
R63 '

~ 400 J'A

2Sk
CURRENT SOURCE CONTROL
FROM CLAMP GATE

~' 200l'A

RSt
100

._--------------- --------------------------------- ---.
18
(+ )COM,PARATOR.. I,NPUT

(-)COMPARATOR INPUT
TL/H/I1440-9

FIGURE 8. Simplified Schematic of the LM1202 Clamp Comparator Circuit

2-32

r-----------------------------------------------------------------------------~ ~

....

!!I:

Applications of the LM1202
SINGLE VIDEO CHANNEL

RGB VIDEO PREAMPLIFIER

A typical application for a single video channel is shown in

Figure 10 shows an RGB video preamplifier circuit using

Figure 9. The video signal is AC coupled to pin 6. The

three LM1202s. Note that pins 1 and 2 of IC1 are connected
to pins 1 and 2 of IC2 and IC3 respectively. This allows IC1
to provide a master contrast control and optimum contrast
tracking. Adjusting the contrast voltage at pin 8 of IC1 will
vary the gain of all three video channels. Drive control input
(pin 9) of each LM1202 allows individual gain adjustment for
achieving white balance.

LM1202 internally biases the video signal to 2.6 Voc. Contrast control is achieved by applying a OV to 4V DC voltage
at pin 8. The amplifier's gain is minimum (i.e., maximum signal attenuation) if pin 8 is at OV and is maximum if pin 8 is at
4V. With pin 9 (drive control) at OV, the amplifier has a maximum gain of 10.
For DC restoration, a clamp signal must be applied to the
clamp gate input (pin 14). The clamp signal should be logic
low (less than 0.8V) only during the back porch (black level
reference period) interval (see Figure 2). The clamp gate
input is TTL compatible. Brightness control is provided by
applying a OV to 4V DC voltage at pin 19. For example, if pin
19 is biased at 1V then the video signal's black level will be
clamped at 1V. A 5100 load resistor is connected from the
video output pin (pin 17) to ground. This resistor biases the
output stage of the amplifier. For power dissipation considerations, the load resistor should not be much less than
5100.

2

The black level of each video channel can be individually
adjusted to the desired voltage by adjusting the voltage at
pin 19. In a DC-coupled cathode drive application, adjusting
the voltage at pin 19 of each IC will provide cutoff adjustment. In an AC-coupled cathode drive application, the video
signal is AC coupled and DC restored at the cathode. In
such an application, the video Signal's black level may be
clamped to the desired level by simply biasing pin 19 to the
black level voltage by using a voltage divider at pin 19.

•
2-33

Applications of the LM 1202 (Continued)

,\#'

(j"1.' ,
.'

!.

'II"·

IIi'

"
",':.:

'/

'J.,

'

. ,\

.

VIDEO
OUT

Vee (+12V)

Vee (+12V) ,

LM1202

TOP VIEW

VIDEO
IN

75
CLAMP GATE

iN
510

(4V)

0.01 J.1F
TlIHI11440-10

FIGURE 9. Typical LM1202 Application (Single Video Channel)

2-34

Applications of the LM1202 (Contiliued)

,~

+UV

.,14

"

e112

tIll

VUll'r~,.1I'f

,~

+12V
CIO!
50 p

r,*,

IIU

51

0100
JNS170
IIt:DVlMO

'"

""'''

AI04
17k

1103

"

,~

""
"

Rl14

't212

t21l

'VD.01PFi'·1I'F

."

C201

50I"'V

HZ1351

""

Vt5170
8LUEVlD[O

OUTPUT

RIO!

"

'00

H2V
1314

"

'V

,~

+I2V

50l"v
""

."

111351

ClU
0,Ol,llr

ellJ
'·7I'F

V

0300
2115170

GRUMVIOEO
OUTl'UT

fII

1303

"

O.Dlp

TL/H/11440-11

FIGURE 10. Typical RGB Application with Contrast, Drive and Black Level (Cutoff) Control

2-35

Power Down Characteristics

PC Board Layout Considerations

The LM1202 includes a built-in power down spot killer to
prevent a flash on the screen upon power down. The
LM1202's output voltage decreases as the device is being.
powered down, thus preventing a flash on the screen. In
some preamplifiers, the video output signal'may go high as
the device is being powered down. This may cause a whiterthan-white level at the output of the CRT driver, thus caus,
ing a flash on the screen;

For optimum performance and stable operation, a doublesided prin,ed circuit board with adequate ground plane and
power supply decoupling as close to the Vee pins as possible is recommended. For suggestions on optimum PC board
layout, please see the reference section below.

Reference
Ott, Henry W, Noise Reduction Techniques in Electronic
Systems, John Wiley & Sons, New York, 1976.

2-36

.-------------------------------------------------------------------------,~

IfI

...

!I:

S

Nat ion a I S e m i con duct or

LM 1203 RGB Video Amplifier System
General Description

Features

The LM1203 is a wideband video amplifier system intended
for high resolution RGB color monitor applications. In addition to three matched video amplifiers, the LM1203 contains
three gated differential input black level clamp comparators
for brightness control and three matched attenuator circuits
for contrast control. Each video amplifier contains a gain set
or "Drive" node for setting maximum system gain (Av = 4
to 10) as well as providing trim capability. The LM1203 also
contains a voltage reference for the video inputs. For high
resolution monochrome monitor applications see the
LM1201 Video Amplifier System datasheet.

• Three wideband video amplifiers (70 MHz @ -3dB)
• Inherently matched (±0.1 dB or 1.2%) attenuators for
contrast control
• Three externally gated comparators for brightness control
• Provisions for independent gain control (Drive) of each
video amplifier
• Video input voltage reference
• Low impedanCe output driver

Block and Connection Diagram
LIoI1203 RGB AIolP
(TOP VIEW)
Vee l

28 Vee l

CONlRAST CAP 2

27 R DRIVE

CONTRAST CAP 3

26 R CLAMP(-)

R VIDEO IN. 4

2S

R CLAIolP CAP 5
G VIDEO IN

R VIDEO OUT

24 R CLAIolp(+)

23 Vcc2

6

GROUND 7

22 G DRIVE

G CLAIolP CAP 8

21 G CLAIolp(-)

B VIDEO IN 9

20 G VIDEO OUT

B CLAIolP CAP

10

19 G CLAIolp(+)

V REF

11

18 B DRIVE

CONTRAST

12

17 B CLAIolP(-)

Vee l

13

16 B VIDEO OUT

CLAMP GATE

14

15 B CLAIolp(+)

TL/H/9178-1

FIGURE 1
Order Number LM1203N
See NS Package Number N28B

2-37

II

o~

~--------------------------------------------------------------------------------,

.S!
~

.,'

Absolute Maximum Ratings

-65°6 td~'t 150"C
Storage Temperature Range, :rSTG
If Military/Aerospace specified devices are required, '
please contact the National Semiconductor Sales
Lead Temperature, (Soldering, 10 sec.)
2(15°C
Office/Distributors for availability and specifications.
1 kV
ESD susceptibility
Supply Voltage, Vee Pins 1,13, 23, 28
. ,Hl!marrbo!lymddfJI:~i.100J)F:di~I'Iarg~~t~rough a.~.5 kG
(Note 1)
, ' ~{,: . , ,f·~'5V··.f'.·.;
.,.
"
resistdr'
""
,,'.
, , '"
,
Voltage at Any Input Pin, VIN
Vee ~ VIN ~ GND
Video Output Current, 116, 20 or 25
'~', !':,i i' 28mA
Operating Ratings (Npte 9)
,,"
:,',
2.5W f
Power'Dissipation, Po ",' '.,
, '. O"C to 70"C
.Temperature Range
(Abov~ 25°C):Derate Based on 9jA and TJI
. SupplVVoltage (Vee)'
" '. • ,
". I;,;, ". ~
Thermal Resistance, 9JA
50"C/W
150"C
, JU,!'Iction T~ItJP,er~wre, TJ
i:. '

Electrical Characteristics'SiHI Test CircUit (Flfluie 2), TA ,,;; 29"C;Va;,1.;;' .VCC2= 12Y ,
;..

..'

Parameter

L!tbel

Video

V11

I'"

Input~eierenCeyoitage,.

rYp
I::"

Vee 1 only
' •... , .

'.

'liested
Limit (Nots 2)

'"

73

. , ...

,.'.

2.4

,

,

. ,

Conditions

Supply Current

Is

•

.,

.',U"

'r'nA(max)

2.2

V(min)

20 :

Video Input,Bias Current

Any One Amplifier

5.0

V141

Clamp Gate L~ ~nputVoltage

Clamp Comparatots On

1.2

'0.8

V14h

Clamp Ga~ High Input Voltage

Clamp CoinparatOl'l! Off

,1,6·

2.0
·~~.O

1141

Clamp Gate Low InpUt current

V14 ~IJV

-p,5"

114h

,clamp GatJ High Input Current

V14 = 12V

0.005

Iclamp+

Clamp Cap Charge Current

V5,80r10 =OV,

'

Video Outptrt Low Voltage

Voh

VideO OutpOt High Voltag~ ,

V~,'8 or 10 ,=

aVo(2V)

Video O!Jtplllt Offset Voltage

Between Any Two Amplifiers I
V15 = 2V ,

aVo(4V)

,Yid!lO OutpUt Off$et Voltage

,

I '"

,

~

.........

""'j'

V(max)

,

,1

V(min)
,..A(max)
p,A(max)
pA(min)

~850

-500

p,A(min)

0..9

1.25

8~9
."
±0.5

8.2

850

V~, 8 or 10 =OV'

Vol

".'

pA(max)

500i;

'

' .-

Iclamp- . Clamp Cap Discharge Current . 'V5,80r'1Q=5V

V(max)

.,?,.6.,

.,

'Units
(Limits)

90.0

Ib

.'

DesIgn
Umlt (Note 3)

5V

..

±50'

Between AnyT~() Amplifi~~ .
V15=4V"
.:,
' ±0.5

V(max)

.,

V(min)
",

",

mV(max)

±'50

mV(max)

"

ACDynamic Tests S17,21,2(1CI~sed;V1A,=OV;V1p';' 4v;'U~le~~tlierwi~'stated
"",
SymbOl

Condltlo.nsl~

,arainettr

V12 = 12V; VIN = 560 mVp-p

6.0

maJi, V12,'''' 5V

~10

Ref: Av malt, "12 = 2V

'::::40

V12 = 12V'(Note5)

±0.5

Ref:Av

aAv5V
aAv2V

Typ

. '. Attenuatior @ 2'1

Avmatch

Absolute gain ~atch

aAv track1

Gain change b~een amplifiers

V12 = 5\( (Notes 5, 8)

±Q.1.

@

Av max

Units
(Umlts)
VlV(min)

4.5
•... .1
"

j

'dB
dB

.,

aAv track2

~ail! c!,!ang!lbEltween amplifiers

V12 = 2V~Notes'5, 8) ,

±0.3

THO

Video Amplifier Distortion

V12 = 3V, Vo = 1 Vp-p

0.5

f (-3 dB)

VideoAmJilifier.Bandwidtl:l>"
(Notes 4, 6)

V12,= '\.2V, ,",,-," " '
Vo = 100mVrms

: tr

DesIgn
Limit (Note 3)

Limit (Note 2)

",

, Video Amplifie~' Gairt

Avmax

"Test~d

. ""

Output Rise Time (Note 4)

Vo

Output Fall Time (Note 4)

Vo =4 VP-P', "".'

,=;

,4 Vp-p ,:

:

2-38

'n ,

j

,

.'

±0.5

dB(max)

±0.7

dB(max)

MHz
5

ns

7

ns

AC Dynamic Tests S17,21,26Closed;V14 = OV;V15 = 4V; unlessptherwisestated (Continued)
Tested
Limit (Note 2)

Typ

Symbol

Parameter

Conditions

Vsep
10kHz

Video Amplifier 10 k~z Isolation

V12

=

12V (Note 7)

Vsep
10MHz

Video Amplifier 10 MHz Isolation

V12

=

12V (Notes 4, 7)

Design
Limn (Note 3)

Units

-65

dB

-46

dB

Note 1: Vee supply pins I, 13,23,28 must be externally wired together to prevent internal damage during Vee power on/off cycles.
Nole 2: These parameters are guaranteed, and 100% production lested.
Nole 3: Design limits are guaranteed (but notlDq% production teated). These lim"s are not used to calculate outgoing quality levels.
Nole 4: When measuring vkleo amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed eireu" board without sockel is recommended. Video Amplifier 10 MHz isolation lest also requires this printed c~cuit board.
Note 5: Measure gain difference between any

two amplHiers. VIN

~

1 Vp·p.

Note 6: Adjust Input f~uency from 10 kHz (Avmax ref level) to the -3 dB comer frequency (f -3 dB).
Nole 7: Measure output levels of the other two undriven amplHiers relative to driven amplHier to determine channel separalion. Tenminate the undriven amplifier
inputs to simulate generator loading. Repeeltest at fiN ~ 10 MHz for Vsep ~ 10 MHz.
Note 8: t:.Av lrack is a measure of the ability of any two amplifiers to track each other and quantifies the malching of the three attenualors. Ills the difference in
gain change between any two amplifiers with Ihe Contrast Voltage V12 al eilher 5V or 2V measured relative to an Av max condition V12 ~ 12V. For example, al
Av max lhe three amplifiers gains might be 17.4'dB, 16.9 dB, and 16.4 dB and change to 7.3 dB, 6.9 dB, and 6.5 dB respectively for V12 ~ 5V. This yields the
measured typical ±0.1 dB channel tracking.
Note 9: Operating Ratings indicate conditions for which lhe device is functional. See Electrical Specifications for guaranleed performance limRs.

Vee

0.01

....- -...-n+12V

pf

~
~
~

I Vee 1

Vee 1

28

2

27

3

26

..

25

5

24

10K

~

0.1

JJf
'6

'7

, Vee 2

23

LM

1203

22

D.U.T.

V12
CONTRAST

8

21

9

20

10

19

II

18

12

17
16
IS

CLAMP GATE
'Peaking capacitors. See Frequency Response
using verious peeking cups graph on next psge.
TLlH/9178-2

FIGURE 2. LM1203 Test Circuit
2-39

Typical Performance Characteristics
Contrast vs Frequency

'iD'
.:!.
""

~

~
.5

<'!I

o VI2=12V
5V
-10
3V
-20
2.3V
-30
2V
-40
1.9V
-50
.-!"
-60
1.7V
-70

-

II
II

III

Crosstalk vs Frequency

o

-.
.....

!

......

! ::
c

:::

R

-60
-70 R

~

"'"

::lOOk

100M

1M

Frequency (Hz)

lOll

100M

Frequency (Hz)·
TLiH/9178-11

TLiH/9178-12

Attenuation vs Contrast. Voltage

Frequency Response Using
Various Peaking caps

+2
+1

-

o

-1
-2
-3

""

'iD'
.:!.

62.pF
50pF
33pF
OpF

c

0
-10

.... ~
1..;0' .....

-20

~c

-30

~

-SO

•

-40

I
'I

-60
~ ......
Vee 12V
-70
o 2 3 4 5 6 7 8 9 10 1112

=

-4
-5

~

~

r-

Ref:OdB=6V/V
10M

~

-10
-20
-30

I\.

Rdrlve = 100.0.

1M

lOll

100M

Contrast Voltage V12 (V)

Frequency (Hz)

TLiH/9178-14
TLiH/9178-13

Pulse Response

.RIse & Fall TImes
Vert.

Horiz.

= W/Div.
= 10 na/Div.

-GND
TL/H/9178-15

2-40

~~--------~--------~~~+

V

100 I'r

28
O.ll'r

~

,~''"..

VIDEO
IN

75Jl

.~~''"''
IN

7SJl

~ll'r

RED DRIVE
SICI

2

27

3

26

4

25
TO RED
CASCODE
DRIVER

O.ll'r

10K~

5

24

23
10K

TO HV
SUPPLY
lK

GREEN DRIVE

VIDEO OUT
60V P-P

SIJl
7

22
LM1203

8

,'~''"..
IN

7SJl

21

20
390Jl

10K

~.I}1F

+
10}lr~

CONTRAST
CONTROL

~O.ll'r

10

19

11

18

12

17

13

16

14

15

CUTOFF
ADJ.

10K

TUH/9178-3

FIGURE 3. LM1203 Typical Application
• 300 resistors are added to the Input pins for protection against current surges coming through the 10 "F input capacitors. By increasing these resistors to well
over 1000 the rise and fall times of the LMI203 can be increased for EMI considerations.

2-41

fII

~ r-----------------------------------------------------------------------~--------,

~

i....

Applications Information
Figure 4 shows the block diagram of a typical analog RGB
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of
other applications that benefit from the use of color display
terminals. The RGB color monitor chara(:teristics may, differ
in such ways as sweep rates, screen size, CRT color, trio
spacing (dot pitch), or in video an'lplifier bandwidths but will
still be generally configured as shOWn in F/{Jure 4. Separate
horizontal and vertical sync signals 'may be required or they
may be contained in the green video input signal. The video,
input signals are usually supplied by coax cable which is
terminated in 750 at the monitor input and internally a~ COu-

pled to the video amplifiers. These input signals are approxi'm",tely 1 volt peak to peak in amplitude and at the input of
the high voltage video Section, approximately 6V peak to
peak. At the cathode of the CRT the video Signals can be as
high as SOV peak to peak. One important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range. The
Figure 4 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function of the
LM1203 which contains the three matched video amplifiers,
contrast control and brightness control.

V0--+--1

'SYNC IN

Ho--+--I

VERTICAL / HORIZONTAl SWEEP
AND POWER SUPPLY
, CIRCUITS

VIDEO IN

Ro--++--I
G 0--+"'-1

VIDEO AMPUFIC,IITION
WITH GAlNioc

B

CONTROL

CONTRAST

BRIGHTNESS

FIGURE 4. Typical RGB Color Monitor Block Diagram

2-42

TLlH/9178-4

Circuit Description
Figure 5 is a block diagram of one of the video amplifiers
along with the contrast and brightness controls. The contrast control is a dc-operated attenuator which varies the ac
gain of all three amplifiers simultaneously while not introducing any signal distortions or tracking errors. The brightness
control function requires Ii "sample and hold" circuit (black
level clamp) which holds the dc bias of the video amplifiers
and CRT cathodes constant during the black level reference
portion of the video wav!lform. The clamp comparator,
when gated on during this reference period, will charge or
discharge the clamp capacitor until the plus input of the
clamp comparator matches that of the minus input voltage
which was set by the brightness control.
Figure 6 is a simplified schematic of one of the three video
amplifiers along with the recommended external compo- ,
nents. The IC pin numbers,are circled with all external components shown outside of the dashed line. The video input
is applied to pin 6 via the 10 IlF coupling capacitor. DC bias

to the video input is through the 10 kll resistor which is
connected to the 2.4V reference at pin 11. The low frequency roll-off of the amplifier is set by these two components.
Transistor 01 buffers the video signal to the base of 02.
The 02 collector current is then directed to the Vee 1 supply directly or through the 1k load resistor depending upon
the differential DC voltage at the bases of 03 and 04. The
03 and 04 differential base voltage is determined by the
contrast control circuit which is described below. RF decoupiing capacitors are required at pins 2 and 3 to insure high
frequency isolation between the three video amplifiers
, which share these common connections. The black level dc
voltage at the collector of 04 is maintained by 05 and Q6
which are part of the black level clamp circuit also described
below. The video signal appearing at the collector of 04 is
then buffered by 07 and level shifted down by Z1 and 08 to
the base of 09 which will then provide additional system
gain.

1.lU203
LOW VOLTAGE
VIDEO

EXTERNAL
HIGH VOLTAGE
VIDEO

> ....._-..,CRT
CATHODE

I
I

TLlH/9178-5

FIGURE 5. Block Diagram of LM1203 VIdeo Amplifier with Contrast and Black Level Control

•
243

LM1203

o

g'::;:
c

I

j

O·

:J

g

g.

1

VIDEOi'
IN

10}'F

7SA

t

TO ClAMP COMPARATOR (+) INPUT

TUH/9178-6

FIGURE 6. Simplified LM1203 Video Amplifier Section with Recommended External Components

Circuit Description (Continued)
The "Drive" pin will allow the user to trim the 09 gain of
each amplifier to correct for differences in the CRT and high
voltage cathode driver gain stages. A small capacitor
(33 pF) at this pin will extend the high frequency gain of the
video amplifier by compensating for some of the internal
high frequency roll off. To use this capacitor and still provide
variable gain adjustment. the 5UI and series 1000 pot
should be used with the red and green drive pins. The 910
resistor used with the blue drive pin will set the system gain
to approximately 6.2 and allow adjustment of the red and
green gains to 6.2 plus or minus 25%. The video signal at
the collector of 09 is buffered and level shifted down by
010 and all to the base of the output emitter follower 012.
Between the emitter of 012 and the video output pin is a
400 resistor which was included to prevent IIpurious oscillations when driving capacitive loads. An external emitter resistor must be added between the video output pin and
ground. The value of this resistor should not be lellS than
3900 or package power limitations may be exceeded when
worst case (high supply. max supply current. max temp) calculations are made. If negative going pulse slewing is a
problem because of high capacitive loads (> 10 pF). a more
efficient method of emitter pull down would be to connect a
suitable resistor to a negative supply voltage. This has the
effect of a current source pull down when the minus supply
voltage is -12V and the emitter current is approximately

10 mAo The system gain will also increase slightly because
lellS signal will be lost across the internal 400 resistor. Precautions must be taken to prevent the video output pin from
going below ground because IC substrate currents may
cause erratic operation. The collector currents from the video output transistors are returned to the power supply at
Vee 2 pin 23. When making power dissipation calculations
note that the data sheet specifies only the Vee 1 supply
current at 12V. The IC power dillSipation contribution of
Vee 2 is dependent upon the video output emitter pull down
load.
In applications that require video amplifier shut down because of fault conditions detected by monitor protection circuits. pin 11 and the wiper arms of the contrast and brightness controls can be grounded without harming the IC. This
assumes some series resistance between the top of the
control pots and Vee.
Figure 7 shows the internal construction of the pin 11 2.4V
reference circuit which is used to provide temperature and
supply voltage tracking compensation for the video amplifier
inputs. The value of the external DC biasing resistors should
not be larger than 10 kO because minor differences in input
bias currents to the individual video amplifiers may cause
offsets in gain.

.------------------------------

: vcc ....._ ..._ ..._ ...__........___..
I

TO VIDEO INPUT
10K

I R21
14K3

R28
12K
R29
8K

I

I
I

IZ3
10K

.I

TL/H/9178-7

FIGURE 7. LM1203 Video Input Voltage Reference and Contrast Control Circuits

2-45

•

~ r---------------~~~--~--------------~------~~----~~~----------------~

~
..-

!I

Circuit Description (Continued)
FIg/Jr9 7 also shows how the contrast,control circuit is con-

figured: 'ResistOrs R23,24, diOdes 133,4 alld transistor Ot3
are used to establish a'iow impe.dancezero ,TC half'supply
voltage'reference at the base of 014. The differential amplifier fOrmed by 016,16 and feedback transistor'017 along
with resistors' R27, 28 establish a diferential, base voltage
for 03 and Q4 in Figure 6; When externally adding or subtracting current from the collector of a16, a new differential
voltage is generated that reflects the change in the ratiO of
currents in 016 and 01-6. To'provide voltage control of the
016 current, resistor R29 is added between the 016 collector, and pin' 12. A capacitor should be added .from pin 12 to
ground to prevent, noise from the contrll$t control POt from
entering the IC.
F/{/ure'8 is a simplified schematic of the clamp gate and
clamp comparator sections of the LM1203. The clamp gate
circuit consists of a PNP input buffer transistor (018), a PNP
emitter coupled pair referenced on one side to 2.1 V,~019,
20) and an output switch (021). When the clamp gate input
at pin 14 is high ,(> 1.5V) the 021 switch is on and'shunts

the It 860 p.A current to ground. When pin, 14 is low (,< 1.3V)
theQ21 switch 'is off and the 11 860 p.A current'soorce is
mirrored or "turned around" by reference diode 06 and 026
to provide a 860 p.A current source for the clamp comparetor(s). The inputs to the comparator are similar to the clamp
gate input except that an NPN emitter coupled pair is used
to control the' current which Will charge or discharge the
clamp capacitors at pins 6; 8, or 1O~ PNPtransistors are
usEid at the inputs because they offer number of advantages over NPNs. PNPs will operate with base voltages at or
near ground and will usually have a greater reverse emitter
base breakdown voltage (BVebo). Because the differential
input voltage to the clamp comparator during the video scan
period could be greater than the BVebo of NPN transistors a
resistor (R34) With a value orle half that of'R33 or R36 is
connected between the bases of 023 and 027. This resistor will limit the' maximum differential input to 024, 26 to
approximately 360 mY. The clamp comparatoroommon
mOde range is from ground to approldmately 9V and the
maximum differential input voltage'is Vee and ground.

a

ClAMP
GATE

IN

...

"+---------~--

TO OTHER
COIoIPARATORS

TlIH/9178-8

FIGURE 8_ Simplified SCJ:lematic of LM1203 CI,mp Gate and Clamp Comparator Circuits

Additional Applications of the LM 1203
Figure 9 shows how the lM1203 can be set up as a video
buffer which could be used in low cost video switcher applications. Pin 14 is tied high to turn off the clamp comparators. The comparator input pins should be grounded as
shown. Sync tip (black level if sync is not included) clamping
is provided by diodes at the amplifier inputs. Note that the
clamp cap pins are tied to the Pin 11 2.4V reference. This
was done, along with the choice of 2000 for the drive pin
resistor, to establish an optimum DC output voltage. The

contrast control (Pin 12) will provide the necessary gain or
attenuation required for channel balancing. Changing the
contrast control setting will cause minor DC shifts at the
amplifier output which will not be objectionable as the output is AC coupled to the load. The dual NPN/PNP emitter
follower will provide a low impedance output drive to the AC
coupled 750 output impedance setting resistor. The dual
500 p.F capacitors will set the low frequency response to
approximately 4 Hz.

r - -...- - - - - - - - -....--Cl+12V

0.1

V
~

.r

lpf

7~

01

28
2

27

3

26

4

25

5

24

6

23

7

22

lpf

~'r

lMI2D3
8

21

9

20

10

19

11

18

12

17

13

16

14

15

lpf

7~

03

04

~V

1Pf

TUH/9178-9

FI~URE 9_

RGB. Video Buffer with Diode Sync Tip Ciampa and 750 Cable Driver

2-47

Additional Applications of the LM 1203 (Continued)
Figure 10 shows the configuration for a three channel high

When diode 04 at Pin 11 is switched to ground the input
video signals will be DC shifted down and clamped at a
voltage near ground (approximately 250 mV). This will dis·
able the video amplifierS and force the output DC level low.
The DC outputs from other similarly configured LM1203s
could overide this lower DC level and provide the output
sighals to the 750 cable drivers. In this case any additional
LM1203s would share the same 3900 output resistor. The
maximum DC plus peak white output voltage should not be
allowed to exceed 7V because the "off" amplifier output
stage could suffer internal zener damage. See Fif!,ure 8 and
text for a description of the internal configuration' of the vid·
eo amplifier.

frequency amplifier with non gated DC feedback. Pin 14 is
tied low to turn on the clamp comparators (feedback amplifi·
ers). The inverting inputs (Pins 17. 21. 26) are connected to
the amplifier outputs from a low pass filter. Additional low
fre~uency filtering is provided by the clamp caps. The drive
resistors can be made variable or fixed at values between 0
and 3000. Maximum output swings are achiaved when the
DC output is set to approximately 4V. The high frequency
response will be dependent upon external peaking at the
drive pins.

+12V
0.1

V

28
0-300A

~

.r

30A

'1
'1 ".

27

2

26
25

,r

10K

24
6

23

7

22

0-300n

10K

?t ".

50A

1 pr

V

LM1203

~

21

8

20

10K

~

10

19

11

18

....- - - t · 1 2

17

13

16

14

15

TLlH/9178-10

FIGURE 10. Three Channel High Frequency Amplifier with Non-gated DC feedbeCk (Non-video Applications)

2-48

r---------------~------------------------------------------------------------,

r-

...

iC

B

J3
Cl::!::
O.IP.F*,

~

~~

0.1 p.F

rtf
0.1 p.F

I

~F

~F

~t-

LII1203
ICI

28

2

27

3

26

~- r.~F
R2410~ 7
ROUT

R23200n.
4

:-0

25

3900.

5

24 ~

6

23

7

22

8

21

J4

C21
ILl p.F

~F

R7

~t
W~

~P.F

10K

J2

cl1lhoirl

~
Jl

I
CONTRAST
CONTROL

C15

It

0~11 p.F

9

R19

390n.

10

19 ~

11

18

12

17

Cl~L33 F

"

"7

RI8'''00~ '7
BOUT

R172004

r-o

16
15

C14

10-

H

~7

0.1p.~

5KI.

~~

r-o

20

14

E+::-::
Cl~ ...Cl~ ...
Rll
43K

GO UT

R20 200n.

R16
3904

RIO

"

R21 100~7

13

;.IP.~P.~

"7

'C,~

R5
10K

i

R9
54

1

~100P.F

R22

R2
10K

i

R8
OK.

C23

'-..../

Cl~

l000pF

R1312K

8

O.IJol~

2

7

OlE

3

6

4

5 ~

1

'-..../

R14
10K
BRIGHTNESS
CO NTROL
R15
2K

Cl~

L111881
1C2

vo-

~7

Jg17

R12
680K
~

~ ~.IP.F
TLlH/9178-16

FIGURE 11. LM1203/LM1881 Application Circuit for PC Board

2-49

•

2-50

I!J1National Semiconductor

LM1203A
150 MHz RGB Video Amplifier System
• Three externally gated comparators for brightness
control
.
.

General Description
The LM1203A is an improved version of the popular
LMl203 wideband video amplifier system. The device is intended for high resolution RGB CRT monitors. In addition to
three matched video amplifiers, the LM1203A contains
three gated differential input black level clamp comparators
for brightness' control and three matched attenuator circuits
for contrast control. Each video amplifier contains a gain set
or "Drive" node for setting maximum system gain or providing gain trim capability for white balance. The LM1203A also
contains a voltage reference for the video inputs. The
LMl203A is pin and function compatible with the LM1203.

• Provisions for individual gain control (Drive) of each
video amplifier
• Video input voltage reference
• Low impedance output driver

Improvements over LM1203
•
•
•
•

Features

150 MHz vs 70 MHz bandwidth
VOUT low: 0.15V vs 0.9V
t,.,tf:4nsvs7ns
Built in power down spot killer

Applications

• Three wideband video amplifiers 150 MHz @ -3 dB
• Matched (±O.l dB or 1.2%) attenuators for contrast
control

• High resolution RGB CRT monitors
• Video AGC amplifiers
• Wideband amplifiers with gain and DC offset controls

Block an~ Connection Diagrams
r-------------~~----------~_,
Lfj 1203A RGB AMP
(TOP VIEW)

~---------------1~~--------------~

Vee l

1

CONTRAST CAP

2

27 R DRIVE

CONTRAST CAP

3

2& R CLAMP(-)

R VIDEO IN

4

25 R VIDEO OUT

R CLAMP CAP

5

G VIDEO IN

6

23 Vee 2

GROUND

7

22 G DRIVE

G CLAMP CAP

8

B VIDEO IN

9

20 G VIDEO OUT

B CLAMP CAP

10

19 G CLANP(+)

V REF

11

18 B DRIVE

CONTRAST

12

1=1=======lf:-~

1+1=======I:t1

~=~::::::r~

14

24 R CLANP(+) .

21 G CLAMP(-)

fII

17 B CLAMP(-)

Vee 1 13 ~-----:-------------+'
CLAMP GATE

28 Vee 1

t------I

16 B VIDEO OUT

15 B CLANP(+)

TUH/11441-1

FIGURE 1
Order Number LM1203AN
See NS Package Number N28B
2-51

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vcc)
Pins I, 13, 23, 2B (Note 3)
13.5V
Peak Video Output Source Current
(Any One Amp) Pins 16, 20 or 25
2BmA
Voltage at Any Input Pin (VIN)
VCC ~ VIN ~ GND
Power Dissipation, (Po) (Above 25·Cderate
2.5W
based on (JJA and TJ)

Thermal Resistance «(JJN

50"C/W

Junction Temperature (TJ)

150"C

ESD Susceptibility (Note 4)

2kV
~65·Cto

Storage Temperature
Lead Temperature (Solderil1g, 10 sec.)

150·C
265"C

Operating Ratings (Note 2)
- 20"C to

Temperature Range

DC Electrical CharacteristicsseeTestCirC~it(Figure2), TA =

+ BO·C

10.BV ~ Vcc';;; 13.2V

, Supply Voltage (VCC)

25·C; VCC1 = VCC2 = 12V. S17, 21, 26 '

Open; V12 = 6V; V14 = OV; V15 = 2.0V unless otherwise stated.

Symbol

. Parameter

I

Conditions

Is

Supply Current

VII

Video Input Reference Voltage

VCC1

,

+ VCC2, RL =

00

(Note 7)

Typical
(Note 5)
70
2.B

Lhnlt
(Note 6)

Units

95

mA(max)

2.5

V (min)

3.1

V (max)

Ie

Video Input Bias Current ,

7

20

p.A(max)

V14L

Clamp Gate Lowlilput Voltage

Clamp Comparators On

1.2

O.B

V (max)

V14H

Clamp Gat~ High Input Voltage

plamp Comparators Off

1.6

2.0

V (min)

114L

Clamp Gate Low Input Current

V14 = OV

-1

-5.0

p.A(max)
,p.A(max)

, Any One Amplifier

,.'

114H

Clamp Gate High Input Current

V14 = 12V

0.07

0.2

ICLAMP+

Clamp Cap Charge Current

V5, B or 10 = OV

750

500

p.A (min)

ICLAMP-

Clamp Cap Discharge Current

V5,Borl0 = 5V

-750

-500

p.A(min)

VOL

Video Output Low Voltage

V5, Bor 10 = OV

0.15

0.5

V (max)

VOH

Video Output High Voltage

V5,80rl0 = 5V

7.5

7

V (min)

AVO(2V}

Video Output Offset Voltage

BetWeen Any Two
Amplifiers, V15 =2V

2

±25

mV(max)

AVO(4V}

Video Output Offset Voltage

Between Any Two
Amplifiers, VI5 = 4V

2

±25

mV(max)

,

,
"

.'.<

"

','
2-52

AC Electrical Characteristics See Test Circuit (Figure 2), TA = 25°C; VCCl = VCC2 = 12V. 817, 21, 26
Closed; V14
Symbol

=

OV; V15

=

4V unless otherwise stated.
Parameter

Conditions

Typical

Limit

(Note 5)

(Note 6)
4.5

Units

AVmax

Video Amplifier Gain

V12

Attenuation @ 5V

Ref: Av max, V12

-8

dB

t..AV2V

Attenuation @ 2V

-30

dB

AVmatch

Absolute Gain Match @ Av max

±0.3

dB

t..A Vtrackl

Gain Change Between Amplifiers

±0.1

dB

t.. A Vtrack2

Gain Change Between Amplifiers

±0.3

dB

THO

Video Amplifier Distortion

1

%

f(-3dB)

Video Amplifier Bandwidth

= 12V, VIN = 560 mVpp
= 5V
Ref: Av max, V12 = 2V
V12 = 12V (Note 8)
V12 = 5V (Notes 8, 9)
V12 = 5V (Notes 8, 9)
V12 = 3V, Vo = 1 Vpp
V12 = 12V, Vo = 4 Vpp

6.5

t..A V5V

(Notes 10, 11)

(No External Peaking Capacitor)

100

MHz

150

MHz

3

ns

4

ns

-70

dB

-50

dB

f(-3dB)

VIV(min)

= 12V, Vo = 4 Vpp

Video Amplifier Bandwidth

V12

(Notes 10,11)

With 18 pF Peaking Cap from
Pins 18, 22 and 27 to GND

tr

Output Rise TIme (Note 10)

Vo

= 4Vpp

(No External Peaking Capacitor)
tf

Output Fall Time (Note 10)

Vo

= 4Vpp

(No External Peaking Capacitor)
Vsep 10kHz

Video Amplifier 10kHz Isolation

V12

V sep l0MHz

Video Amplifier 10 MHz Isolation

V12

= 12V (Note 12)
= 12V (Notes 10,12)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the davica may occur.
Note 2: Operating Ratings indicate conditions for which the device is IuncIional, but do not guarantee speclfic performance fimits. For guaranteed specHications
and test conditions, see the Electrical Characterislips. The guaranteed speciflC8tions apply only for the test conditions listed. Some performance characteristics
may degrade when the devica is not operated under the listed test conditions.
Note 3: Vee supply pins 1, 13, 23, 28 must be externally wired together to prevent internal damage during Vee power on/oil cycles.
Note 4: Human body model, 100 pF discharged through a 1.5 kll resistor.
Note 5: Typical specifications are specified at

+ 25"C and represent the most likely parametriC norm.

Note 6: Tested limits are guaranteed to National's AOOL (Average Outgoing Quality Level).
Note 7: The supply current specHied is the quiescant current for Vee1 and VCC2 with RL = 00, see Figure 2's test circuit The supply currant for VCC2 (pin 23) also
depends on the output load. With Video output at 2V 00, the additional currant through VCC2 is 18 mA for Figure 2's test circuh.
Note 6: Measure gain dillerenca between any two amplifiers. VIN

= 1 Vpp.

Note 9: ~ Av tracI< is a meesure of the ability of any two amplifiers to track each othar and quantifies the matching of the three attenuators.,it Is the dillerenca in gain
change between arry two amplifiars with the contrast voltage (V12) at ehhar 5V or 2V measured relative to an Av max condhion, V12 = 12V. For example, at
Av max the three amplifiers' gains might be 17.4 dB, 16.9 dB and 16.4 dB and chenge to 7.3 dB, 6.9 dB, and 6.5 dB respectively for V12 = 5V. This yields the
measured typical ± 0.1 dB channel tracking.
Note 10: When measuring video amplifier bendwidth or pulse rise and fall times, a double sided full ground plane printed cireutt board without socket is
recommended. Video amplifier 10 MHz isolation test also requires this printed circuit board.
Note 11: Adjust input frequency from 10kHz (AV max referenca level) to the - 3 dB comer frequency (f -3 del.
Note 12: Measure output levels of the other two undriven amplifiers relative to the driven ampl~ier to determine channel separation. Terminate the undriven
amplifier inputs to simulate generator loading. Repeat test at fiN = 10 MHz for Vsep = 10 MHz.

•
2-53

~.--------------------------------------------------------------------,

~

,"

0.01
I'F

!

vee
+12V

,",

1 Vee 1,

Vee 1

28

30 V:OlI'F

10K

~

0.1
I'F

2

27

3

26

4

25

5

24

Vee 2

10K

LII
1203A
D.U.T.

7

~0.1I'F

8

23

BLACK
LEVEL
SET

22

21

20

10

19

11

18

12

17

13Veel

16

14

15

CLAIIP GATE

Tl/H/II441-,2

,FIGURE 2. LM1203A Test Circuit

.

.

.

~.

Typical Performance Characteristics Vee = 12V, TA = 25"Cunlessotherwisespecified
Contrast va Frequency

lOOk

111

1011
FREQUENCY (Hz)

2·54

10011
TUH/II441-3

Typical Performance Characteristics Vee = 12V, TA = 25°C unless otherwise specified (Continued)
Crosstalk vs Frequency
'GREEN (IIAX CONTRAST)

0
~

3

z
2
~
::>
z

......
•

...,

.- ~

-20

~
RED ~

-40

P

A

~ f(

-60

~

...-:~

,

BLUE)

I

-80
111

lOOk

1011

10011

FREQUENCY (Hz)
TLlH/11441-4

Frequency Response Using Various Peaking caps
f- VOUT

=

4 Vpp
CONTRAST
12V
BRIGHTNESS
4V
2 f- RoRIVE
loon

=
=

=

33 pF

~

3

.
z

:c

24pF

0

............

-1

'Il-18 pF
~OpF

..........

-2

\I~

-3

\

I\" .\
1011

111

10011

FREQUENCY (Hz)
TL/H/11441-5

Attenuation vs Contrast Voltage

~

-12

z
0
;:

-18

3

•::>z

......
•

--

VOUT = 4Vpp
BRIGHTNESS = 4V

0
-6

~

/"
J

-24

I
I

-30
-36
-42

-48
-52

o

2.4

4.8

7.2

9.6

12

CONTRAST VOLTAGE V12 (V)
TL/H/11441-6

2-55

ct

.CO) .

0
C'\I

~,

::::E ,
.;.J

~~--------~--------~~-'+

~I'OO'~F

"
30

1':".'

VIDEO
IN

G

. 0.1 ~F

7511

10K

~

2

27

3

26

"

25

5

2"

, T.O RED
CASCODE
DRIVER

10 ~F"711'

'~l:

-,,:
IN

28

o.ol~F

23
10K

GREEN DRIVE

VIDEO OUT
60V p-p

5111
7

22
LM1203A
21

8

".'

20
39011

10K

7511

~.I~F
+

16

19

II

18

CUTOFF
·ADJ.

9111

10~~
12

17

13

16

14

15

*O.OI~F

39011

TO BLUE
CASCODE
DRIVER

~~

max

CONTRAST
CONTROL

10K
BLACK LEVEL
(BRIGHTNESS)
CONTROL

10K

BLACK LEVEL
GATE IN
TL/H/II441-7

'47n resistors are added to the Input pins for protection against current surges coming Irom the 10,.F capacitors. By increasing these resistors to well over loon
the riee and fall times of the LMI203A can be Increased for EMI considerations.

FIGURE 3. LM1203A TyplCllI Application

2-56

Applications Information
Figure 4 shows the block diagram of a typical analog RGB
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of
other applications that benefit from the use of color display
terminals. The RGB color monitor characteristics may differ
in such ways as sweep rates, screen size, CRT color trio
spacing (dot pitch), or in video amplifier bandwidths but will
still be generally configured as shown in Figure 4. Separate
horizontal and vertical sync signals may be required or they
may be contained in the green video input signal. The video
input signals are usually supplied by coax cable which is
terminated in 750 at the monitor input and internally AC
coupled to the video amplifiers. These input signals are approximately 1V peak to peak in amplitude and at the input of
the high voltage video section, approximately 6V peak to
peak. At the cathode of the CRT the video signals can be as
high as 60V peak to peak. One important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range. The
Figure 4 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function of, the
LMl203A which contains the three matched video amplifiers, contrast control and brightness control.

Circuit Description
Figure 5 is a block diagram of one of the video amplifiers
along with the contrast and brightness controls. The contrast control is a DC-operated attenuator which varies the '
AC gain of all three amplifiers simultaneously while not introducing any signal distortions or tracking errors. The bright- '
ness control function requires a "sample and hold" circuit
(black level clamp) which holds the DC bias of the video
amplifiers and CRT cathodes constant during the black level
reference portion of the video waveform. The clamp comparator, when gated on during this reference period, will
charge or discharge the clamp capaCitor until the plus input
of the clamp comparator matches that of the minus input
voltage which was set by the brightness control.
'

VIDEO AMPLIFIER SECTION
Figure 6 is a simplified schematic of one of the three video
amplifiers along with the recommended external components. The IC pin numbers are circled and all external com!l(men~s are s~own ~utside the dashed line. The video input
IS applied to Pin 6 via a 10 ,...F coupling capacitor. DC bias
for the video input is through the 10k resistor connected to
the 2.8V reference at pin 11. The low frequency roll-off of
the amplifier is set by these two components. Transistor 01
buffers the video Signal to the base of 02. 02's collector
current is then dir~cted to the VCCl supply directly or
through the 2k load resistor depending upon the differential
DC voltage at the baSes of 03 and 04. This differential DC
voltage is generated by the contrast control circuit which is
described in the following sections. A 0.01 ,...F decoupling
capaCitor in series with a 300 resistor is required between
pins 2 and 3 to ensure high frequency isolation between the
three video amplifiers which share these common connections. The video signal is buffered by 05 and 06 and DC
level shifted by the voltage drop across R5. The magnitude
of the current through R5 is determined by the voltage at pin
8. The voltage at pin 8 is set by the clamp comparator output current which charges or discharges the clamp hold capaCitor during the black level period of the video waveform.
Transistors 09 and 010 are Darlington connected to ensure
a minimum discharge of the clamp hold capaCitor during the
time that the clamp capacitor is gated off. 07, 08 and R6
form a current mirror which sets a voltage at the base of
011. 011 buffers the video signal to the base of 012 which
provides additional signal gain. The "Drive" pin allows the
u:*,r to trim ~e 012 gain of each amplifier to correct for gain
differences In the CRT and high voltage cathode driver gain
stages. A small capaCitor (several pico-Farads) from the
"Drive" pin to ground will cause high frequency peaking and
Slightly improve the amplifier's bandwidth.

V 0---1--1

SYNC IN
H 0---11---1

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS

•

VIDEO IN

G 0---11-+-1

8o-.....-~

VIDEO AIIPLI~ICATION
WITH GAIN / DC
CONTROL

CONTRAST

BRIGHTNESS

FIGURE 4. Typical RGB Color Monitor Block Diagram

2-57

TL/HI11441-8

Circuit Description (Contin~edi
<'"
For' ihdMdual gain adjus'tni~nt of each 'vkteoChannel, a51 0
resistor in setieswlth a 1000 potentiometer'should be:us8a
with the red and QJ:een chanriel drhle pinil: A 910 resistor
used With'the blue channel dtivepin setS'the"biue chaimel
amplifier gain at approximately 6.2. The 1000 potentiOmeter
at ~e red and green channel dHv$ Pins allow a gain O,f 6.2
with ± 25% gain adjustment Ttie video signal at th8 Collector of 012 Is buffered and leVel shifted dowri by 013, Q14
andQ1'5,to the'base of the output em itt"" follower 016. A
500 deCoupling resistor is included in series with tile emitter
of,016111iil the video output pin so as'to prevent oscillatioris
wtieiidrivinQ capacitive' loads:
extem8l' resistor' should
be cOnnected betWeen the video oUtput pin and ground.

An

.

'

'.

. .,

The value of this resistor st\9uld not be less than 39(l0 or
else, packa!l$POWIlf, lim~tions, may be exceeded, under
worst<;ase oonditions (high supply voltage, maximum current, t:l"I8Idmum, ta~rature). The Cj)lIector current from ~
video QUtpt/t ,transistor of each video channel is returned to
the power supply at VCC2., pin 23. When making power dissipation calculations note that the data sheet specifies only
the VCC1 arul.,,\lCC2 supply current at 12V supply voHage
with no, pull down resistor at, the output (i.e., RL = op. see
test circuit Figure 2). The Ie power dissipation ,due to VCC2.
is -4~"";"'-.

CRT
CATHODE

,I

CLAMP GATE

J
FIGURE 5_ Block Diagram ofLM1~3A Video Amplifier with Contrael and,Jlack Level Control

,',"

TLlH/11441-9

,-----------------------------------------------------------------------------, r

...~

a:

Circuit Description (Continued)

~

Yee
, +12Y

23
Ycc2

Rl0
,50

R3

2k

016

R14
50

5, 10

O.lI'F
CLAMP
CAP

----------- _..

18 27

16

25

T
V

TLlH/11441-10

FIGURE 6. Simplified Schematic of LM1203A Video Amplifier Section with Recommended External Componente

•
2-59

~r'~~----------------~~~--~----------------------------------~

51

Circuit Description

:IE

INPUT REFERENCE AND CONTRAST CONTROL
SECTION
F/{/ure 7 shows the input refereflce anc;l C9.ntraSt control circuitry. A temperature compenSated 2.8V reference voltage
is made. available at pin 11. Th~' extemal DC biasing resistors shown should not be larger than 10k because minor
differencas in input bias currents of the individual video amplifiers may cause offsets in gain. Figure 7 also shows how
the contrast c:ontrol circuit is configured. R21, R22, 022,
023 and 024 establish a low impedance zero TC half supply voltage reference at the base of 025. The differential
amplifier formed by 027, 028 and feedback tranSistor 029
along with R28 and R29 establish a differential base voltage
for 03 and 04 in Figure 6. When extemally adding or subtracting current frolJ1 the colle.ctor of 028, a new differential
voltage is generated that reflects the change in the ratio of
currents in 027anc;l 028. To allow voltage control of the
current through 028, resistor R27 is added between the
collector 028 and pin 12. A caPacitor should be connected
from pin 12 to ground to prevent noise from the contrast
control potentiometer from entering the IC.

...

(Continued)
(Figure 8) consists of a PNP input buffer transistor (046), a
PNP emitter coupled pair (047 and 049) referenced on one
side to 2.1 V and an output switch transistor 053. When the
clamp gate input at pird4 is high (>1.5V) the 053 switch is
on and shunts the 200 p.A CUrrent from current source 054
to ground. When pin 14 is low « 1.3V) the 053 switch is off
and the 200 ,.,A current is mirrored by the current mirror
comprised of 055 and 036 (see Figure 9). Consequentiy
the clamp comparator comprised of the differential pair 035
and 037 is enabled. The input of each clamp comparator is
similar to the clamp gate except than an NPN emitter coupled pair is used to control the current that will charge or
discharge the clamp capacitors at pins 5, 8 and 10. PNP
transistors are used at the inputs because they offer a number of advantages over NPNs. PNPs will operate with base
voltages at ·or near ground andwill·usually have a greater
emitter base breakdown voltage (BVebo). Because the differential input voltage to the clamp comparator during the
video scan period could be greater than the BVebo of NPN
transistors, a resistor (R37) with a value one haH thatof R36
or R39 is connected between the bases of 034 and 038.
The clamp comparator's common mode range is from
ground to apprOximately 9V and the maximum differential
input voltage is Vee and ground.

CLAMP GATE AND CLAMP COMPARATOR SECTION
Figures 8 and' 9 show simplified schematics of the clamp
gate and clamp comparator cirCuits. The clamp gate circuit

--~---------------------------~-----------vee
R28

R27

12k

8k

10k

TO VIDEO
INPUT
029

R26
200

I

R30

200

TO VIDEO
AMP
03 BASE

TO VIDEO
AMP
04 BASE

R25

R29

10k

4.7k

R31
10k

------------------------------------------_.

TLlH/11441-11

FIGURE 7. Simplified SchematiC of LM1203A Video Input Reference and Contrast Control Circuits

2-60

Circuit Description

(Continued)

R55
25k

CURRENT SOURCE
CONTROL TO CLAMP
COMPARATORS

Q46

R54
50k

R47
200

14

CLAMP GATE
INPUT

TUH/11441-12

FIGURE 8. Simplified Schematic of LM1203A Clamp Gate Circuit

•
2-61

Circuit Description (Continued)

R43
400

50 ",A 50 ",A

~

R46
100

~

045
4X

400 ",A

~

PUSH PULL OUTPUT CURRENT
TO CLAMP CAP(S)

r-__~~__~Q_3S~

L-0~3_7__~~__- ,

R36
50K
, R37

Q34 ": 2Sk
CURRENT SOURCE
CONTROL FROM
CLAMP GATE

R32
500

R33

R34

500

10k

R35
100

15

R38

500

24

17

19

26

21

(+) COMPARATOR INPUT

(-) COMPARATOR INPUT
Tl.IH/11441-13

FIGURE 9. Simplified Schematic of LM1203A Clamp Comparator Circuits

2-62

r-----------------------------------------------------------------------------, r
i:
....
Additional Applications of the LM 1203A
Sync input signal may have either polarity. The back porch
clamp signal applied to LM1203A's pin 14 allows clamping
the video output signals to the black reference level, thereby providing DC restoration. The back porch clamp pulse
width is determined by the time constant due to the product
of R 11 and C15. For fast horizontal scan rates, the back
porch clamp pulse width can be made narrower by decreasing the value of R11 or C15 or both. Note that an MM74C86
Exclusive-OR gate may also be used, however, the pin out
is different than that of the MM74HC86.

Figure 10 shows the configuration for a three channel high
frequency amplifier with non gated DC feedback. Pin 14 is
tied low to tum on the clamp comparators (feedback amplifiers). The inverting inputs (Pins 17, 21, 26) are connected to
the amplifier outputs from a low pass filter. Additional low
frequency filtering is provided by the clamp caps. The drive
resistors can be made variable or fixed at values between
00 and 3000. Maximum output swings are achieved when
the DC output is set to approximately 4V. The high frequency response will be dependent upon external peaking at the
drive pins.

~

~

For optimum performance and maximum bandwidth, high
speed buffer transistors (01, 02 and 03 in F/{/ure 11) are
recommended. The 2N5770 NPN transistors maintain high
speed at high currents when driving the inputs of high voltage CRT drivers.

Figure 11 shows a complete RGB video preamplifier circuit
using the LM1203A. A quad Exclusive-OR gate
(MM74HC86) is used to generate the back porch clamp signal from the compoSite sync input signal. The compoSite H

+12V
0.1

V
0.01

30

,~
,~

28
0-30011

",r
2

27

3

26

4

25

5

24

, 6

23

7

22

47Q

10k
47Q

~

0-30011

LIot1203

10k

f4

~

8

21

9

20

, 10

19

11

18

12

17

13

16

14

15

10k

~
1 ",r

V

•

10k

TUH/11441-14

FIGURE 10. Three Channel High Frequency Amplifier with Non-gated DC Feedback (Non-video Application)

2-63

~..-

Additional Applications of the LM 1203A (COntinued)

::E

.....

LM1203AN

1124

R25
51

27

TOP VIEW
26
RED
VIDEO
IN

25

24
GREEN
VIDEO
IN

23

22

21
BLUE
VIDEO
IN

20

10

19

11

18

12

17

13

16

14

15

GREEN

t--++'W\r-(") VIDEO
OUT

Cll

101'F~

C13
O.II'F*

BLUE

t--+.......w.-{] VIDEO
OUT

CONTRAST
Re
10k

EXTERNAL

+/ - H SYNC IN

TUH/11441-18

FIGURE 11. LM1203A Appli.catlonll Circuit

2-64

r-----------------------------------------------------------------------------'r
!!II::
....
LM 1203A vs LM 1203
LM1203A is an improved version of the LM1203 RGB video
amplifier system and is pin and function compatible with the
LM1203. LM1203A's output voltage can swing as low as
0.15V as opposed to 0.9V for the LM1203. This eliminates
the need for a level shift stage between the preamplifier and
the CRT driver in most applications.
The LM1203A also offers faster rise and fall times of 4 ns vs
7 ns for ,the LM1203 and 100 MHz bandwidth vs 70 MHz for
LM1203. With a peaking capacitor across the drive resistor,
LM1203A's bandwidth ~n be extended t9 150 MHz. Because of LM1203A's wide bandwidth, the device mayoscillate if plugged directly into an existil19 LM1203 board. For
optimum performance,and stable operation~ a double sided

printed circuit board with adequate ground plane and power
supply decoupling as close to the Vee pins as possible is
recommended. Figure 12 shows the layout of the PC board
for F/{Jure 11's circuit. For suggestions on optimum PC
board layout, please see the reference section below.
The LM1203A also includes a built-in power !town spot killer
to prevent a flash on the screen upon power down. In some
preamplifiers, the video output signal may go high as the
device is being powered down. This may' calise a whiter
than white level at the output of the CRT driver, thus causing a flash on the screen.
'

~

~

REFERENCE
Ott, Henry W. Noise Reduction Techniques in Electronic
Systems, John Wiley & Sons,NElW York, 1976.

VIDEO IN

GND

9

,q369~1-

RI

VCC

GND

R

R34

VCC

J3
J3 J4

~
d- -

-D-

23

VEE

vmEO OUT'

~~

VEE

B d
~ !8--'

R

c; ~"lMl~3A
~ R~
~
R3~i~R2 i~
=~ ~ R2B ..L
, ~,
~R29CzjI-C CI9T
C7+

JLdl'

R4

G

,~
, CI1, J2 a ':=IfJ2

RIS RI9
RIS
Rv-D-~

~

~

~]
-il-

~
~
-D-9~D
~

B

-HSYNC DI

RI5

11

R9

-i1-0
C3S

EXTERNAL SYNC IN

*:7

G'
~

'-------'- ..L
cR!II
ClsT
R32

B

R33

RII:
TCI5
!.L
fLRG R43
JII
:
RI2
J5
..L •
CI4 T LMI4ILRZ-5
CONTRAST

-D-

R3II'

~"

-iI-as ~ aE

JIB

+ .....C13

RS

-D-D--l'----'~CI7

-d- aE

--Lfi, --£J-

G
V

CONTROL

T

R 13

---c:J-::.:

BRIiHTNESS

0V

CONTROL

NATDNAL
SEM)[O NDUCTO R
LM 121113A
RG B AMPLFIER
SYSTEM REV A
12112/91
TL/H/II441-16

FIGURE 12{a). PC Board Silk Screen

2-65

•

~
CII)

g

r--------------------------------------------------------------------,
',1'

Additional Applications of the LM1203A (Continued)

~

.'i

t

TL/H/11441-17

FIGURE 12(b). PC boardlliyout of bottom side. Top side of PC board (not shown) Is full ground plane.

2-66

t!lNational Semiconductor

LM1203B
100 MHz RGB Video Amplifier System
General Description

Features

The LM1203B is an improved version of the popular
LM1203 wideband video amplifier system. The device is intended for high resolution RGB CRT monitors. In addition to
three matched video amplifiers. the LM1203B contains
three gated differential input black level clamp comparators
for brightness control and three matched attenuator circuits
for contrast control. Each video amplifier contains a'gain set
or "Drive" node for setting maximum system gain or providinggain trim capability for white balance. The LM1203B also
contains a voltage reference for the video inputs. The
LM1203B is pin and function compatible with the LM1203.

• Three wideband video amplifiers (100 MHz @ -3 dB)
• Matched (±0.1 dB or 1.2%) attenuators for
contrast control
Ii Three externally gated comparators for
brightness control
• Provisions for individual gain control (Drive) of each
.
.
video amplifier
• Video input voltage reference
• Low impedance output driver
• Stable on a Single sided board

Improvements over LM1203

Applications
• High resolution RGB CRT monitors
• Video AGC amplifiers
• Wideband amplifiers with gain and DC offset controls

• 100 MHz vs 70 MHz bandwidth
0.15V vs 0.9V
3.7 ns vs 5 ns

• VOUTlow:

• tr. t(.

• Built in power down spot killer

Block and Connection Diagrams
28-Lead Molded DIP
LM 1203B RGB AMP
(TOP VIEW)
Veel

I

28 -Vee1

CONTRAST CAP

2

27 R ORIVE

CONTRAST CAP 3

26 R CLAMP(-)

R VIDEO IN 4

25 R VIDEO OUT

R CLAMP CAP

5

24 R CLAMP(+)

G VIDEO IN

6

23 Vee 2

GRDUND

7

22 G ORIVE

G CLAMP CAP

8

21 G CLAMP(-)
20 G VIDEO OUT

B VIDEO IN 9
B CLAMP CAP

10

19 G CLAMP(+)

V REF

II

18 8 DRIVE

CONTRAST

12

CLAMP

~=~=T"'"

17 8 CLAMP(-)

Veel

13~----~------------~

16 B VIDEO OUT

Gill

14 ~-----I

15 8 CLAMP(+)

TLlH/II489-1

Order Number LM1203BN
See NS Package Number N28B
- 2-67

.

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are req~ired.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vcc)
Pins 1, 13, 23, 28 (Note 3)
13.5V
Peak Video Output Source Current
(Any 1A) Pins 15, 20, or 25
28mA
Voltage at Any Input Pin (VIN)
Vcc :

...z

-60

~

S

~

Co)

GREEN IIAX CONTRAST

~

~

i:

""'II~ ~

L i""'"'

-Y

i...IIII ",

,.

.... rr
,j'

II

~D

-80

lOOk

III

lOll

lOOt.1

FREQUENCY (Hz)

TUH/114B9-4

Frequency Response Using Various Peaking Caps
2 VOUT '" 4Vpp

CONTRAST'" 12V
BRIGHTNESS'" 4V
0 IfoRIVE'" loon

'iii'

-1

z

-2

'"

-3

~

:c

---

..............:

-4
-5

51 pF
36.J!f

24 pF

"' ,
~

~~
i . \.,
o pFl'\.

l

~

lOll

III

100l0I

FREQUENCY (Hz)

TL/H/114B9-5

Attenuation vs Contrast Voltage
VOUT '" 4Vpp
BRIGHTNESS =: 4V

0
-6

'iii' -12
~
z -18
g -24

.....
::>

z

-30

S

-36

/'

......-

i"""

--

r-

I
I

-42
-48
-52

o

2.4

4.8

7.2

9.6

12

CONTRAST VOLTAGE V 12 (V)
TUH/114B9-6

2·71

•

+.

~100PF
28
30

R

0.01 pF
2

27 I-+-~Vv--¥'Iv-"

3

26

H-----,

10~F 47

-+-.

,~ f,t.:n~M"'-1-0K--r-Io-.1- P- F-I
G,

RED DRIVE

51n

10pF 47

v·

,~ ~,t.::~M-+'-1-0-K---I

25H--....
390n

TO RED
CASCODE
DRIVER

5

24

6

23

7

22

1-I....~M~WIr"-t

21

H-+----,

TO HV
SUPPLY

lK
GREEN DRIVE

VIDEO OUT
60V P-P

51n
LM1203B

8
9

390n'
10

19

11

18

H-+-"\M-...,

12

17

H-+---,

CUTOFF
ADJ.

91n

16H-+-.....+-+
15

CONTRAST
CONTROL

BLACK LEVEL
(BRIGHTNESS)
CONTROL

TLIH/11489-7

FIGURE 3. LM1203B Typical Application

2-72

Applications Information
F1{lure 4 shows the block diagram of a typical analog RGB
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of
other applications that benefit from the use of color display
terminals. The RGB color monitor characteristics may differ
in such ways as sweep rates, screen size, CRT color trio
spacing (dot pitch), or in video amplifier bandwidths but will
still be generally configured as shown in Figure 4. Separate
horizontal and vertical sync signals may be required or they
may be contained in the green video input signal. The video
input signals ara usually supplied by coax cable which is
terminated in 750 at the monitor input and internally AC
coupled to the video amplifiers. These input signals are approximately 1V peak to peak in amplitude and at the input of
the high voltage video section, approxmiately 5V peak to
peak. At the cathode of the CRT the video signals can be as
high as 60V peak to peak. One important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range. The

Figure 4 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function of the
LM1203B which contains the three matched video amplifiers, contrast control and brightness control.

Circuit Description
Figure 5 is a block diagram of one of the video amplifiers
along with the contrast and brightness controls. The contrast control is a DC-operated attenuator which varies the
AC gain of all three amplifiers simultaneously while not introducing any signal distortions or tracking erros. The brightness, control function requires a "sample and hold" circuit
(black level clamp) which holds the DC bias of the video
amplifiers and CRT cathodes constant during the black level
reference portion of the video waveform. The clamp comparator, when gated on during this reference period, will
charge, or discharge the clamp capacitor until the plus input
of the clamp comparator matches that of the minus input
voltage which was set by the brightness control.

Vo--+--i

SYNC IN

Ho--+--t

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS

VIDEO IN

Ro--+-t--1
G 0--+--1

VIDEO AMPLIFICATION
WITH GAIN / DC
CONTROL

CONTRAST

TL/H/11489-8

FIGURE 4. Typical RGB Color Monitor Block Diagram
LM12038
LOW VOLTAGE
VIDEO

EXTERNAL
HIGH VOLTAGE
VIDEO

>~,.....-..,CRT
CATHODE

•
TL/H/11489-9

FIGURE 5. Block Diagram of LM1203B Video Amplifier with Contrast and Black Level Control
2-73

ir=------~~------~~~----~--~----~~--------~------~

g

Circuit Description (Continued)

:;;

V~D~O AMPLIFIER'SECTION '
F/{/ure 6 is ~,simplified schematic of one of the three ~ideo
amplifiers 81ori~ 'wit/;I the reco~l"ernt~ eideinai ~mpOc

:::i

tions. The video signal ,is buffered by 05 and as and DC
level shifted by the voltage drop across R5. The ,magnitLJde
of the current through'R5,is determined by the voltage at pin
8. !he voltage at pin 8 is set by tne clamp,comparator out'
put current which char{l9S or discharges the Clamp hold capacitor during the black level period of 'the video ,waveform.
Transistors 09 and 010 are'dariington'connectedto ensure
~ Minimum discharge of the clamp hold capacitor dUring the
time that the'clamp capacitor is gated off. 07, as and, R6
form a cun'entmirror which sets' a voltage at the base',of
011. 011 buffers the video signal to the base of 012 whiCh
provides additional signal gain. The ''Orive'' pin 'allows the
user to trim the 012 gain of each amplifrer to correct for gain
differences in the'-CRT and high voltage cathode drivsr gain
stages. A 'small capacitOr (several'pico-Farads) frOm the
"Drive" pin to groLind will cause high frequency peaking and
slightlY Improve the amplifier's bandWidth. '
'
,
i=or individual gain adjustment of each video'channef a 510
resistor in series with a: '1 000 potentiometer should be used
with the red and green channel drive pins. A 910 resistor
used with the blue channel drive pin sets the blue channel
amplifier gain at approximately 6.2. The 1000 potentiometers at the red and green channel drive pins allow a gain of
6.2 with ± 25% gain adjustment. The video signal at the

nents. The IC pin numbers are circled and aU extemal cOm!X>nen~ are shown outside the, dash,ed Ii,,~., The video input
IS applied to pin 6 via a 10 ,...FcoiJpllng capacito(and 470
resistor. The' resistor is added to IiInlt tl'lecurrent through
the inputpin should the app!i9d voltage rise above Vcc br
drop below groUnd. The performance of the LM1l!03B is not
degraded by thEi'470 resistor. However if EMI is a cOncern
this resistor can be increased to well over 1000 where th~
rise and fall times will become loriger. DC bias for the video
input is throuqh the 10k r8siStor connectecfto the 2.8V reference at pin 11. The loW frequency roll·offot the amplifier is
set by the'10k resiStor and'the 10,...F capacitor; Transistor
01 buffers the videa signal to the baile of 02. 02's collectot
current is "then directed to the VCC1 supply direcflyor
through the 4k load resistor depending upon the differential
DC voltage at the bases of 03 and'Q4. This dlfferentiamC
voltage is generated by the contrast control circuit which is
described in the following sections. A
,...F decoupling
capacitor in series with a 300 resistor is required betWeen
pins 2 and 3 to ensure high frequency isolation between the
three video amplifiers which share these common ,connec-

a

om

Vee
+12V

R3
4k

----------- ..

--------~----------

16 25

VIDEO
OUT

TL/H/I1489-10

FIGURE 6. Simplified SchematiC of LM1203B Video Amplifier Section
with Recommended External Components
.

.

.'"

';.'

2-74

.

'

.-----------------------------------------------------------~~

....

Circuit Description (Continued)
collector of 012 is buffered and level shifted down by 013,
014 and 015 to the base of the output emitter follower 016.
A 500 decoupling resistor is included in series with the emitter of 016'and the video output pin so as to prevent oscillations when driVing capacitive loads. An external resistor
should be connected between the video output pin and
ground. The vaiue -of this resistor should not be less than
3900 or else package power limitations may be exceeded
under worse case conditions (high supply voltage, maximum
current, maximum temperature). The' collector current from
the video output transistor of each video channel is returned
to the power supply at VCC2, pin 23. When making power
dissipation calculations note that the data sheet specifies
only the VCC1 and VCC2 supply current at 12V supply voltage with no pull down resistor at the output (i.e., RL = 00,
see Test Circuit Rgure 2). The IC power dissipation due to
VCC2 is dependent upOn the external video output pull down
resistor.
'

INPUT REFERENCE AND CONTRAST
CONTROL SECTION
Figure 7 shows the input referenca and contrast control cirCUitry. A temperature compensated 2.8V reference voltage
is made available at pin 11. The externel DC biasing resistors shown should not be larger than 10k because minor
differences in input bias currents of the individual video amplifiers may cause offsets in gain. FI{JIJffJ 7 also shows how
the contrast control circuit is configured. R21, R22, 022,
023, and 024 establish a low impedance zero TC half supply voltage reference at the base of 025. The differential
amplifier formed by 027, 028 and feedback transistor 029
along with R28 and R29 establish a differential base voltage
for 03 and Q4 in Figure 6. When externally adding or subtracting current from the collector of 028, a new differential
voltage i,s generated that reflects the change in the ratio of
currents in 027 and 028. To allow voltage control of the
current through 028, resistor R27 is added between the
collector 028 and pin 12. A capacitor should be connected
from pin 12 to ground to prevent noise from the contrast
control potentiometer from entering the IC.

a
at

p-------------------------------------------.

1
1
1
1
1
1

10k

' , V e e

R16

R28
12k

R27
8k

200

TO VIDEO
INPUT

029

10k

R26

R30

200

200

TO VIDEO
AMP
03 BASE

RU

R17
5k

,I

10k

,

R25
10k

TO VIDEO
AMP
04 BASE

R29
4.7k

R31
10k

,

.-----------------------------------------~-.
TUH/11489-11
FIGURE 7. Simplified Schematic of LM1203B Video Input
Reference and Contrast Control Circuits

2-75

II

mr---------------------------------~--------------------~

m
~

:E
...J

Circuit Description (Continued)
similar to the clamp gate except the\ an t-IPN, emitter coupled pair is used to control the .current that will charge· Qr
dlsctlarge the clamp capacitors at pins .5,8, and. 10. PNP
transistors ara used at the inputs because they offer a number of adl/antages over NPNs. PNPs will operate with base
voltages at or near ground and will usually have a greater
emitter base breakdown voltage (BVebo). Because the dif'erential. input voltage to the clamp com~tor during the
video scan period could be greater than the BVebo of NPN
transistors, a resistor (R37) "with a'Value one han that of R36
or.R39 is connected between the bases of 034· and 038.
The .. clamp comparator's common mode {angeis from
ground to apprOximately 9V and the maximum differential
input voltage is Vee and ground.

CLAMP GATE AND C.LAMP
COMPARATOR SECTION
Figures 8 and 9 s!1ow. simplified schematics of. the clamp
gate and clamp comparatorcl~cuijs. The clamp gate circuit
(F/(/Uf'9 8) consists of a PNP Input buffer. transi$lO!' (046), a
F'NP emitter coupled pair (047 and a49) referenced on one
side to 2.1 V and an outPut switch transistor a53. When the
clamp gate input at pin 14 islligh (> 1.5V) the a53 switch is
on and shunts the 200 p.A current from current source a54
to ground. When pin 14 is low « 1.3V) the a53 switch is off
and the 200 .p.A current is mirrored by the current mirror
comprised of a55 and 036 (see F.'I{}Uf'9 9). Consequently
t~clamp comparator comprised of the differential pair a35
arid 037 is enabled. The input of each clamp comparator is
Vee .

RS5

2Sk

QSl ~------------~Q~S2~------------~Q~S~4~--~~--------.

200 p.A

R49
42k

R48

SOk

RSO
20k

~

RS2
23k.

Q47

CURRENT SOURCE
CONTROL TO CLAMP
COMPARATORS

Q53

R51
10.Sk

R53
500

R54

SOk

CLAMP GATE
INPUT

TLlHI11489-12

FIGURE 8. Simplified Schematic of LM1203B Clamp Gate Circuit

2-76

Circuit Description

(Continued)

R43
400

50 p.A 50 p.A

~

R46
100

~

040

042

045

4X

1X

4 X

400 p.A

400 p.A

~

PUSH PULL OUTPUT CURRENT
TO CLAMP CAP(S)

~

035

r---.-+-----~

037

~-----r~--~

038

R35
100

R40

R38

100

500

15 24
17 26
--------------~-----------------------------21

19

(+) COMPARATOR INPUT

(-) COMPARATOR INPUT
TUHI11489-13

FIGURE 9. Simplified Schematic of LM12038 Clamp Comparator Circuits

2-77

Additional Applications of the LM 12038
Figure 10 shows the configuration for a three channel high
frequency amplifier With non gated' DC feed~ck. Pin '14 is
tied low to tum on the cil!mp com~ators (f~back amplifiers). The inverting inputs (Pins 17. 21. 26) are connected to
the amplifier outputs from a loW pass filter. Additional low
frequency filtering is proVided by the clamp Caps. TJ:le'drive

resistors can be made variable or fixed at values between
and 3000. Maximum output swings are achieved when
the DC output is set to approximately 4V. The high frequen'cy response wiil be dependent upon extemal peaking at the
,driv~ pins.

on

+12V
O.IJ.1 F V28
0-300n

0.01 J.lF

30n

2

27

3

26

4

25

5

24

6

23

7

22

47n

'1~ ".

10K

0-300n

50n

LIof1203B

~.,.

50n

v1

8

21,

9

20

10

19

11

18

12

17

13

16

14

15

10K

O.IJ.1F

lJ.1FV-

GAIN
ADJUST
10K

TUH/11489-14

FIGURE 10. Three Channel High Frequency Amplifier with Non-Gated DC Feedback (Non-Video Applications)

2-78

Additional Applications of the LM 12038 (Continued)
the back porch clamp pulse width can be made narrower by
decreasing the value of R11 or C15 or both. Note that an
MM74C86 Exclusive-Or gate may also be used, however,
the pin out is different than that of the MM74HC86.
For optimum performance and maximum bandwidth, high
speed buffer transistors (01, 02, and 03 in F;gure 11) are
recommended. The 2N5770 NPN transistors maintain high
speed at high currents when driving the inputs of high voltage CRT drivers.

F/{//Jre 11 shows a complete RGB video preamplifier circuit
using the LM1203B. A quad Exclusive-OR gate
(MM74HC86) is used to generate the back porch clamp signal from the composite sync input signal. The composite
H Sync input signal may have either polarity. The back
porch clamp Signal applied to LM1203B's pin 14 allows
clamping the video output signals to the black reference
level, thereby providing DC restoration. The back porch
clamp pulse width is determined by the time constant due to
the product of R11 and C15. For fast horizontal scan rates,

C5
RED
VIDEOO......-'YVv--Jt-......- - - - I
IN
RED
t---t-IIN\r-4~ VIDEO
OUT

24
GREEN
VIDEOO.....~M~II+...- - - - I
IN

23

22

H-t-'INI"

21
BLUE
VIDEOO.....--\~-lt-+-4_----I
IN

10

19

11

18

12

17

Cll

101'F~

GREEN
t--t-t-IIN\r-4~ VIDEO
OUT

H-t-'INI.,

13
14

15

BLUE
t--t-IIN\r-4~ VIDEO
OUT

CONTRAST

R8
10k

VO.

C12
l I'F

EXTERNAL

+/ -

H SYNC IN

°

R1

~-r~~~---------~~r~

C14
O.lI'F

V
TUH/11489-15

FIGURE 11_ LM1203B Applications Circuit
2-79

LM 12038 versus LM 1203
The LM1203B also includes a built in power down spot killer
to prevent a flash on the screen upon power down~ In some
preamplifier;s, the video output signal may go high as the
device is being powered down.. This may cause a whiter
than white level at the output of the CRT driver thus causing
a flash on the screen.
.

I,M1203B is an improved version of the LM1203 RGB video
ampli(ier lIystem and is pin and function compatible with the
LM1203. LM~203B's putpllt voltage can swing 8$ low as
0.15V as opposed to 0.9V for.the LM1203. This eliminates
the need fora level shift stage between the preamplifier and
thE/ CRT driver in most applications.
The LM1203B alsooffe~s·faster rise and fall times of 3:7 ns
versus 5 ns for the LM1203, resulting in .100 MHz bandwidth
versus 70 MHz for LM1203. A peaking capacitor across the
drive resistor is necessary to obtain these rise and fall times.
The LM1203B is stable on a weiliayed out single sided PC
board, but due to its wider bandwidth the device may oscil·
late if plugged directly into an existing LM1203 board. For
suggestions on optimum PC board layout, please refer to
the PC board layout given in the LM1203A data sheet. The
ground plane is not necessary for the LM1203B due to its
lower bandwidth.

Reference
Ott, Henry W., "Noise Reduction Techniques in Electronic
Systems", John Wiley & Sons, New York, 1975.

2·80

f}1National Semiconductor

LM1204 150 MHz RGB Video Amplifier System
General Description

Features

The LM1204 is a triple 150 MHz video amplifier system
designed specifically for high resolution RGB video display
applications. In addition to three matched video amplifiers,
the LM1204 contains a DC operated contrast control, a DC
operated drive control for each amplifier, and a dual clamping system for both brightness control and video blanking.
The LM1204 also contains a back porch clamp pulse generator which is activated by an extemally supplied ± H/HV
sync signal or by an extemal composlte video signal. The
± H/HV sync input will have priority over the composite video input. A single - H/HV sync output is provided for the
automatically selected sync input signal. The back porch
clamp pulse width is user adjustable from 0.3
to 4 '"'S.
The LM1204 video output stage will directly drive most
Hybrid or discrete CRT amplfier input stages without the
need for an extemal buffer transistor. The device has been
designed to operate from a 12V supply with all DC controls
operating over a OV to 4" range providing for an easy interface to serial digital buss controlled monitors.

•
•
•
•
•

Built-in video blanking function
Built-in sync separator for composite video input
Includes DC restoration of video Signals
Back porch clamp pulse width user adjustable
DC control of brightness, contrast, blanking level, drive
and cutoff
• DC controls are OV to 4V for easy interfacing to a
digitally controlled system

Key Specifications
• 150 MHz large signal bandwidth (typ)
• 2.3 ns rise/fall times (typ)
• 0.1 dB contrast tracking (typ)
• ± 3 dB drive (.1 gain) adjustments on R, G, B channels
(typ)

'"'S

Applications
• High re89lution CRT monitors
• Video AGC amplifier
• Wideband amplifier with gain and DC offset control

Block Diagram and Connection Diagram
Top View
~

Jl
R VIDEO IN

!

Jl

~

~

~

~

I

8

Jl

I
~

>H

!

~
II

"::;iii

7

NTRAST
~
AI

---

A2

A GAIN ADJ.

37

a BUNKING CAP

ONTRAST
~
AI

---

A2

A GAIN ADJ.

NTRAST
~
AI

---

COMPOSITE

VIDEO SYNC
SEPARATOR

n

I8

Jl

A2

A GAIN ADJ.

~

i

BACK
PORCH
CLAWP
GENERATOR

BLANKING

iiiGHTNESS
CoNriiAST

I

~ '~" '~" ~~

§
j;

I;

%

"i-

~

~

+/-

HSYNC
PROCESSOR

8
~

Ordering Information
Order Number LM1204V
See NS Package Number V44A
2-81

~

I
TUHI11238-1

Absolute Maximum Ratings

(Note 1)

If MilitarylAerospace specified devices are required, '"
please contact the National Semiconductor Sales
OffIce/Dlatrlbutors for availability and specifications.
Supply Voltage. Vee
Pins 2, 4, 6,19, 31, 41, 44 (Note 3)

Voltage,at Any Input-Pin, VIN

GND

:s: Villi:;;: Vee

,Maximum ±H Sync Input Voltage',·

5.5Vpp

2~oC

Lead Temperature __, , ' " ,
Vapor Phase (60 seconds)
Infrared (15 seconds) "

I

,

~qt0700C

Temperature Flange
2.4W

:

'215°C
2200C

, Operating Ratings (Note 2)

' ,

OaraHl Based on 8JA And T J)

2.5kV
-s!f'c to' 1500C

" . , C"" ,

Storage Temperature

13.5V
30mA

Hiooc

ESP su~eptibility (Note4)

"i.",
i,

'S2°C/W

Junction Temperature, TJ

",

Peak Video Output Source CUrrent
(Any One Amplifier) Pins 30, 35 or 39

Power DisSipation, PO (AbOve

'\' Thermal Resistance, 9JA

Supply Voltage,

Vee

10.8V:S: Vee,:i:,13.2V

DC Electrical Charact~ristlcsJ\li,deo Amplifier Section)

The following specifications apply for V6c (pins 2, 4, 6, 19, 31, ,36, 41 and 44) = 12V and T A = 25"C unless otherwise specified.
S~ = B, S2 = B, S3, 4, 5 closed~ y~ 13, 15 = 2V, V20, 21;,22, 24, 48-= 0.5Y-unless otl:lerwisespecified; see test circuit,
Figure 1.
"
'
'",",'
",
,

, ,

Symbol

Parameter

No Video or Sync Input
Signals, Sl = A

Is

Supply Current

Is

Input Bias Current
(Pin 9, 13, 15, 20, 21 or 22)

124h

IFB

Sl = A

-

Typical
(Nota 5)

!rImlt
"lIote6).
1.25' .

100
'0.3

2

0.01

2

'"

V24 = 4V

,

V24, = OV

Blank Gate Input Low CUrrent

2

Feedback Input Current
(Pin 28, 33 or 38)

' ,

5

pA
. (Max)

pA
(Max)

pA
(Max)

150

ISlank+

Blank Cap Charge CUrrent

V32,37,42 = OV

185

75

pA(Min}

ISlank-

Blank Cap Discharge Current

V32,37,42 = 5V

-185

-75

pA(Min}

Iss

Blank Cap Bias Current (Pins 32; 37; ,42)

IClamp+

Clamp Cap Charge Current

IClamp-

Blank Cap DiScharge Current

Ice
V24h
V241

,
"

,

Blank Gate Input High Current
,',

1241

CondltloDs'

,

V5,10,14 = OV

185

75

pA(Min)

V5,10,14 =' 5V

-185

-75

pA(Min}

2

V (Min)

0.8

V (Max)

2

50

mV
(Max)

8.7

7

Y(Min}

0.1

0.5

V(Max}

0.5

V(Min}

4

V(Max}

Clamp Cap BiasCurr,nt (Pins 5, 10, 14)

20
Input Signal is Not Blanked

Blank Gate High Input Voltage
Blank Gate Low Input Voltage

Input Signal is Blanked

Blank Comparator Offset Voltage

Voltage between V43 and
Any One Video Ol,ltput

' "

VH

Video Output High Voltage
(Pins 30, 35, 40)

VL

Video Output Low Voltage ,
(Pins 30, 35, 40)

VCM43

Common Mode Range of Blank
Comparator (Pins 43, 28, 33, 38) ___

nA

20

RL= 3500
" V28, 33, 38 = OV' '

nA

"

RL = 350ftV28,~3, 38 = 4V

\

:

.{

2-82

DC Electrical Characteristics (Sync Separator/Processor Section)
The following specifications apply for Vee (Pins 2, 4, 6, 19, 31, 36, 41 and 44) = 12V and TA = 25°C, unless otherwise
specified. S1 = B, S2 = B, S3, 4, 5 closed, V9, 13, 15 = 2V, V20, 21, 22, 24, 43 =0.5V, unless otherwise specified; see Test
Circuit FlfJlJre 1.
Typical
(NoteS)

Limit
(Note 6)

Units

- H Sync Output Logic High (Pin 26)

4.2

2.4

V(Min)

- H Sync Output Logic Low (Pin 26)

0.1

0.4

V{Max)

Symbol

Parameter

-HVOH
-HVOL

Conditions

Quiescent DC Voltage at ± H
Sync Input

V23

3

V

AC Electrical Characteristics (Video Amplifier Section)
The following specifications apply for Vee (Pins 2, 4, 6, 19, 31, 36, 41 and 44) = 12V and TA =. 25°C, unless otherwise
specified. S1 = B, S2 = B,
4, 5 closed, V9, 13, 15,21,24,43 = 4V, V20 = 2V, unless otherwise specified; see Test Circuit

sa,

Figure 1.
Symbol

Parameter

Conditions

RIN

Video Amplifier Input Resistance

AVmax

Maximum Video Amplifier Gain

aAVtrack

Amplifier Gain (Contrast)
Tracking (Note 7)

aAV2V

Attenuation at 2V

Ref:Avmax

Attenuation at 0.5V

Ref: Avmax V21 = 0.5V
V9,13,15 = OVto4V

. aAVO.5V

10

fiN = 12kHz

V21 = 2V

aGain

a Gain Range (Pins 9, 13, 15)
Max Brightness Tracking Error (Note 8)

L3dB

Video Amplifier Bandwidth (Note 9)

THO

Video Amplifier Distortion

VOUT = 1 Vpp, f = 12 kHz

Video Output Rise Time (Note 9)

iF

Video Output Fall Time (Note 9)

VISO(l MHz)
VISO (130 MHz)

,

Umit
(Note 6)

20

aVo

tR

Typical
(NoteS)

VOUT = 3.5 Vpp

Units
kO

5.5

VIV(Min)

0.1.

dB

6

dB

28

20

dB(Min)

±3

dB

100

rriv

150

MHz

·0.3

%

Square Wave Input
VOUT = 3.5 Vpp, RL = 3500

2.0

ns

Square Wave Input
VOUT = 3.5 Vpp, RL = 3500

2.3

ns

Video Amplifier 1 MHz
Isolation (Notes 9,10)

-50

dB

Video Amplifier 1.30 MHz
Isolation (Notes 9,10)

-10·

dB .

•
2-83

AC Electrical'Characteristics (Sy.nc Separ.ator/Processor Section)
The following specifications apply for Vee (PinS 2, 4, 6,.19, 31, 36, 41 and 44) = 12V and TA = 25°C, unless otherwise
specified. S1 .. A, S2 = B, 83, 4, 5 closed, V9, 13, 15, 20., 21, 43
2V, unless otherwise specified; see Test Circuit Figure ,1
and Timing Diagram for input waveform.

=

Symbol

Parameter

V18{Min)
V18(Max)
V23

Conditions

Composite Video Input Voltage
(Pin 18)
Composite Video Input Voltage
(Pin 18)

S2 = A,lnput = 10.% Duty
Cycle, Testfor Loss of BP
Pulse at Pin 26

± H Sync Input Voltage (Pin 23)

Input = 10.% Duty Cycle
S2 ";'A, Pin 26 = ,BP Output

,!;lack Porch Clamp Pulse Width
atV24 = ,tV
Back Porch Clamp Pulse Width
atV24 = 4V
.' Maximum ± H Sync Input Frequency
Max Duty Cycle of Active High
H Sync (Pin 23)
Max Duty Cycle of Active Low
H Sync (Pin 23)

Test for Loss of Sync
at Pin 26

Ipdll

± H Sync Inputto - H Sync
Output Low Delay

Input = 10.% Duty Cycle

tpdhl

±H Sync Inputto -H Sync
Ol,ltput High Delay

DHI
"

DLO

I

Input'= 10.% Duty Cycle

Typical
. (Note 5)

Umlt
(No~6)

0..15
2

1.4

30.0.

6()o.

Vpp
(Min)
Vpp
(Max)
Vpp
(Min)

1.6
1

Units

,...s.
(Max)
ns
(Max)

600.

KHz

22

%

22

%

10.0.

ns

65

ns
.'

tpd1

± H Sync Input Trailing Edge to
Back Porch Clamp Output Delay

Input = 10.% Duty Cycle,
S2=A

1pd12

Composite Video Input to - H
Sync Output Low Delay

Input = 10.% Duty Cycle'

tpdh2

Composite Video Input to - H
Sync Output High Delay

Input = 10.% Duty Cycle

tpd2

Composite Video Input Trailing
Edge to Back Porch Clamp Output Delay

Input = 10.% Duty Cycle
S2=A

tpdl2-tpdll

Composite Video and ± H Sync Input
to - H Sync Output Delta Delay'

Input = 10.% Duty Cycle

70.

ns,

10.6

ns

68

ns

78

ns

6

ns

1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, sea the Electrical Cheracteristics. The gusranteed specificationa apply only for the test conditions listed. Some perlormanca characteristica
may degrade whan the device Is not operated under the listed test conditions.
Nota 3: Vee supply pins 2,4,6,19,31,36,41 and 44 must be exlemallywired ~to praventlntemal damage during Vee power on/off cycle.
Note 4: Human body model, 100 pF discharged through a 1.5 kG resistor.
Nota 50 Typical specifications are specified at + 25"C and represent the most likely parametric norm.
Nota 6: Tested limits are guaranteed to National's AOOL (Average Outgoing Quality LeveQ.
Note 7: ~v tracking Is a measure of the ability of any two amplifiers to track each other and quantifieS the matching of the three attenuators. It is the difference in
gain change between any two amplifiers with the contrast voitage, V21, at either 4V or 2V measured relative to an Av max condition V21 = 4V. For example, at Av
max, the three arnplHier gains might be 17.4 dB, 16.9 dB and 16.4 dB and change to 7.3 dB, 6.9 dB and 6.5 dB respectively for V21 = 2V. This yields the messured
typical ± 0.1 dB channel tracking.
Note 8: Brightness tracking error Is measured with all three vkieo channels set for equal gain. The measured value Is IImHed by the resolution of the measurement
Note

Nolli 2:

,f·

equipment.

Note 9: When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed cl.cuH board is recommended. Video
amplifier isolation tests also require this printed circuH boord. The measured rise and fall times are effective rise and fall times, taking Into account the rise and fall
times of the generator.
Note 10: Measure output levels of either undriven amplifier relative to the driven amplifier to determine channel isolation. Terminate the undriven amplifier Inputs.

2-84

.-----------------------------------------------------------------------------~ ~

Typical Performance Characteristics
Attenuation vs Contrast
Control Voltage (f = 12 kHz)

'ii1

~

~is

5i

-10

~'"

-20

'ii1
~

z

~
is

-30

-40

5i

-50

-60

Attenuation vs Drive
Control Voltage (f = 12 kHz)

..,.....

V"

-1

-2
-3

V

-4

./

-70
o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

CONTRAST CONTROL VOLTAGE V21 (V)

1-

.

~3.0
N

>

~
~

5

1.8

1.&
1.4

'"

1.2
1.0 H-+-+-+-'H-++-H-+~
~ 0.8 H-+-+-+-'H-++-H-+~

~60~2~4~&~B-,0~12-,L4~II-I~B~20-~~N

'"

EXTERNAL +/- H SYNC INPUT DUTY CYCLE V23 (II)

•

3.0

~
i

2.5

~

1.5

-10

'ii1
~

-20

~
!C

-30

'"

~

-40
-50

IV

;;;

-

...
...I

-70

.ucHrNESS,
IMX 6"M

Vm •

IV

'"

~~:IV:: ~T~~ Va·

lOOk

IMEG

r

0
o

lOMEG

lOOWEIl

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

V_=4V

-1
'ii1

-2

z

51

-3

!C

'"
is

-4

5i

-s
-&

-7

fREOUENCY (Hz)

.......

Drive Control vs Frequency

~

.,..70C1mYpp

-60

\

1.0
0.5

BACK PORCH CLAWP WIDTH COHTROI. VOlTAGE V22 (v)

.

"1,.4'1

J

2.0

Contrast vs Frequency

~

!

4.0
3.5

DRIVE CONTROL VOlTAGE VI, 13 OR 15 (V)

Minimum External ± H
Sync Input Level (Vpp)
vslnput Duty Cycle (%)

2.11
2.&
2.4
2.2
2.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.D

o

~

Back Porch Clamp Pulse
Width vs Pin 22 Voltage

S

S

-6

~

1

!

V

-5

ill:
....

Vee = 12V, T A = 25°C unless otherwise specified

'"

I'
I'

5.lV

2.1"1
Z.OV

~

1..4'1

-

I'
£

0.71'1

ovl

lOOk

I MEG

....mas,Vzo. tV
''',,''V,:s'"''M-:SV
"""
"". ......" ... '111 .

IDUEG

10Dum

fREQUENCY (Hz)

Crosstalk vs Frequency

.....

R

-10
'ii1
~

I
~

-20
-30

-40
-50
-&0
-70

m
Bore

lOOk

lMEG

lOum

lOOum

fREOUENCY (Hz)
TL/H/I1238-2

2~85

LM1204

- - - -......, -O!~2V

".

.......

(UV)

RED
VIDEO@)

*

1,

~I

1

I,

~I

1

;l

.,

0

RED

VIDEO
OUT

IN

BLUE
VIDEO@)
IN

O:I~~

I·,

OUT

~

. . . . . .O

I----_-_~

GREEN
VIDEO@)
IN

1I

1M

GREEN
VIDED
OUT

)1 1
O.lpF

0.11"

COMPOSITEt-t
IN"
VIDEO
•
iH/HV
SYNC
IN

V

V

_ _ _WI

V
•.
"WI'"

I'~T

BP WIDTH OUT FOR SI =A. S2=A

~
-~1"""------------------...J
"

TLlH/11238-3

FIGURE 1. LM1204 Test Circuit

Timing Diagram
2Vpp

H SYNC
INPUT
OR
SYNC ON GREEN
INPUT
:I;

- H SYNC
OUTPUT

BACK PORCH
CLAMP PULSE OUTPUT
TUH/11238-4

Input/Output Stages
- H Sync Output Stage

Composite Video Input

5V (INTERNAL REGULATOR)

- H SYNC OUTPUT

TUH/11238-6

TL/H/11238-5

. Video Output Stage

r-~-------'~~-'-----------'----9----oV~
2K

8k

500
(PINS 30,35,40)

800

TUH/11238-21

2-87

Input/Output Stages (Continued)
± H/HV Sync Input

Video Input Stage

r - - - -....-o 5.8V (lNTERNAL,RE!lULATOR} •

VIDEO IN

-

(PINS 7,11. 17)

TUH/11238-7

TUH/II238-8

Pin Descriptions
Vce (Pins 2, 4, 6, 19,
All Vee pins must be externally wired together. For stable operation, each Stipply pin should be
31,36,41,44)
'bypassed with a 0.01 p.F and a 0.1 p.F capacitor connected as close to the pin as is possible.
Contrast Cap (Pins 1, 3) An external decoupling capaCitor of value 0.1 p.F should be connected between pins 1 and 3 for
contrast control.
'
A 0.022 p.F to 0.1 p.F capacitor should be connected from this pin to ground. This capaCitor allows
R Clamp Cap (Pin 5)
clamping of the red channel video signal to the reference black level.
B Clamp Cap (Pin 10)
A 0.022 p.F to 0.1 p.F capaCitor should be connected from this pin to ground. This capaCitor allows
clamping of the blue channel video signal to the reference black level.
G Clamp Cap (Pin 14)
A 0.022 p.F to 0.1 p.F capaCitor should be connected from this pin to ground. This capacitor allows
clamping of the green channel video Signal to the reference black level.
R Video In (Pin 7)
This is the input for the red channel video Signal, the signal should be AC coupled to the input through
a 10 p.F capaCitor.
B Video In (Pin 11)
This is the input for the blue channel video Signal, the signal should be AC coupled to the input
through a 10 p.F capacitor.
G Video In (Pin 17)
This Is the input for the green channel video signal, the signal should be AC coupled to the input
through a 10 p.F capacitor.
R t:.. Gain (Pin 9)
This is the gain adjustment pin for the red video channel. A OV to 4Voc voltage is applied to this pin to
vary the gain of the red channel.Usually, the red channel is set for maximum gain and the gains of the
blue.and green channels are reCtuced relative to the red channel until white balance is achieved on
the GRT screen.
'
B t:.. Gain (Pin 13)
This IS ilie gain adjustment pin for the blue video cllarinel. ov to 4 Voc voltage is applied to this pin
to vary the gain of the blue channel.
G t:.. Gain (Pin 15)
This is the gain adjustment pin for the green ,video channel. A OV to 4 Voe voltage is applied to this pin
to vary the gain of the green channel.
Compose Video Input
This is the sync separat9l" inpUt pin. 'For Sync on Green systems, the green channel video signal
(Pin 18)
should be AC coupled to pin 18 through a 0.1 p.F capacitor.
Brightness Control
If the LM1204'is used without blanking then this pin should be biased at 2.0 Voc. Brightness control
(Pin 20)
for all three video channels is' now controlled by pin 43 (blank level adjust pin). See Figure 4. If the
LM1204 is used with blanking then this pin allows the user to simultaneously DC offset the video
portion of the output Signals of all three chanr,Jels thus allowing brightness control (See FJgllre 5).
Contrast Control
This pin simultaneously controls the gain of all three video channels. A OV to 4 Voc input voltage is
(Pin 21)
applied to this pin, with OV corresponding to minimum gain (i.e., maximum attenuation of video signal)
and 4V corresponding to maximum gain (i.e., minimum attenuation of the video signal).

A

2-88

Pin Descriptions (Continued)
Back Porch Clamp Width
Adjust (Pin 22)

± H Sync In (Pin 23)

Blank Gate In (Pin 24)

Integrator Cap (Pin 25)
- H Sync Out (Pin 26)

G Feedback (Pin 28)

B Feedback (Pin 33)

The LM1204 provides DC restoration or clamping during the back porch interval of the video signal.
The width of LM1204's internally generated back porch clamp signal can be varied by applying a OV
to 4 Vee voltage to this pin. The back porch clamp signal width can be varied from approximately
0.3 ,...s to 4.0 ,...s by applying 4V to 0.5V respectively. By connecting the blank gate input pin (pin 24)
to Vee, the back porch clamp pulse can be monitored on the -H Sync output pin (pin 26). See
Figures 4 and 5. By connecting pin 22 to Vee, the LM1204 functions as a non-gated amplifier
requiring no clamping. See Section 4 under application hints for further information.
This is the extemal sync input pin, it accepts a negative or positive polarity signal, either horizontal
sync or a composite sync (1.2 Vpp minimum amplitude). The LM1204 also provides a negative
polarity (TTL compatible) horizontal sync or composite sync output on pin 26. If the composite video
input (pin 18) is not used then an H Sync signal should be AC coupled to this pin through a 0.1 ,...F
capacitor. The ± H Sync input has prioritY over the composite video input if both signals are present.
This is the blank gate input pin. The LM1204 allows video blanking at the preamplifier. If blanking is
desired then a TTL compatible, negative polarity blanking signal should be applied to this pin. During
the blanking interval, all three video outputs are level shifted to the blank level set by the voltage at
.
pin 43. If blanking is not required then, pin 24 should be biased at 4V.
Connecting pin 24 to Vee will cause pin 26 to output the internally generated back porch clamp
signal. The user can observe the change in back porch width as the Potential at pin 22 is varied (see
FI{Jures4and 5).
A 0.1 ,...F capacitor should be connected from this pin to ground. This capacitor allows tlie LM1204 to
integrate the ± H Sync input signal and genreate the proper polarity switch for - H Sync output.
This output pin provides a negative polarity horizontal sync signal for other system uses. There is
approximately 100 ns delay between the ± H Sync input signal at pin 23 and the - H Sync output
signal at pin 26.
Connecting pin 24 to Vee will cause pin 26 to output the internally generated back porch clamp
signal. The user can observe the change in back porch clamp pulse width as the potential at pin 22 is
varied (See Figures 4 and 5).
This is the cutoff adjustment input for the green video channel. The green video output Signal from
pin 30 is fed back to this input through a potentiometer thus allowing the user to individually adjust
the cutoff (black reference) level for each gun. The signal level at this pin should be between 0.5V
and4V.
This is the cutoff adjustment input for the blue video channel. The. blue video output signal from pin
35 is fed back to this irput through a potentiometer thus allowing the user to individually adjust the
cutoff (black reference) level for each gun. The signal !evel at this pin should be between 0.5V and

4V.
R Feedback (Pin 38)

G Video Output
(Pin 30)
B Video Output
(Pin 35)
R Video Output
(Pin 40)
G Blank Clamp Cap
(Pin 32)
B Blank Clamp Cap
(pin 37)"·
R Blank Clamp Cap
(Pin 42)
Blank Level Adjust
(Pin 43)

GND (Pins 8,1216,27,
29,34,39)

This is the cutoff adjustment input for the red video channel. The red video output signal from pin 40
is fed back to this input through a potentiometer thus allowing the user to individualy adjust the cutoff
(black reference) level for each gun. The signal level at this pin should be between 0.5V and 4V.
This is the green channel video output.
This is the blue channel video output.
This is the red channel video output.
A 0.022 ,...F to 0.1 ,...F capacitor should be connected from this pin to ground. This capacitor allows
blanking for the green video channel.
A 0.022 ,...F to 0.1 ,...F capaCitor should be connected from this pin to ground. This capacitor allows
blanking for the blue video channel.
A 0.022 ,...F to 0.1 ,...F capacitor should be connected from this pin to ground. This capacitor allows
blanking for the red video channel.
This pin serves two functions depending on whether the LM1204 is used with blanking or without
blanking. If blanking is not selected then pin 20 should be biased at 2.0 Vee and pin 43 assumes the
role of brightness control. Varying the potential at pin 43 will simultaneously DC offset the video
output signals of all three channels (See Fl{Jure 4). If the LM1204 is used with blanking then during
the blanking interval, all three video output signals will be level shifted to the blank level. The desired
blank level can be set by adjusting the potential at pin 43. Brightness control is now made possible
by varying the potential at pin 20. Adjusting the brightness control DC offsets the video portion of the
signal relative to the fixed blank level (all channels are affected simultaneously). See Fl{Jure 5.
Ground. All ground pins must be connected to the ground plane.

2-89

•

gr-------------------------------------------------------------~

C"I
....

::!i

ment for each channel is d~n~ byv~rying the feeq~ck voltage at each of the A, G and B feedback il'iputS '(Ping 38', 28
'and 33). For example, cutoff adjustment farthe green channel is done 'bY potentiometer A8 shown in Figure 2. ' ' ' ,
~djusting ,the contrast corrtrol ,(potentiometer A3 in Figure
2) varies the peak to peSk amplitude (includ&S sync tip if
present), of all ,three video outPut signals relative to their
, Qlack reference level. The I:. Gain adjust (.pins 9,15 and 13
for R, G, and B channels resp8ctively) allows the user to
individually adjust the AGo gain of each channel~ 'For example
the AC gain Of the green'chennel is adjusted using potentiometer A5 as shown 11\ Figure 2. Normally the red channel
is'set for maximum gain and the gains of the blue and green
channels are reducect until,white balance is achieved on the
CAT monitor's screen. FlfJure 4 shows the adjustments for
operation,without blanking.

Applications Hints
TIIeU"t12(l4 is a wideband video amplifier system deSigned
specificallyJor high resolution AGB CRT monitors. The, device Includes circuitry, for DC restoration of video, signals
and also allows. contrast and brightness oontrol, DC restora- ,
tion is done during the back porch interval of the video signal. An internal sync separator generates 'a back, porch
clamp signal either from a "Sync on Green" signal applied
to the composite video ,input (pin 18) or from an e1dernally
supplied ±H,.S¥,"p sign'al . The lM,1204 ,fil'llt lOOks 'at the
.±H Sync inJll.lt (pin 23), ,if an external horizontal',sync signal
IS not present then the device synCS,off the composite video
input. The internally generated back pOrCh clamp .pulse
width is user adjustable.
A blanking ,function is ~I~ included. Th~ allOws the use~ to,
cutoff the beam current in the CArs guns during the blank-" '
ing interval thereby pfeventing horizontal r9trace lines from
being visible. Normally blanking is done, by a.pplying a high
voltage pulse at the grid. HoYlev~, blanking at the cathode
Using the LM1204leads'to ease 'of design and lowered Cost.
Figure 2 shows the, block diagram Of the green video chan-,
nel an~ the control lOgiC. T.he two modes of opera.tl6n, with
and witho~t blanking, are described below in detail."
,
<-

2.0 Operation with Blanking
Much of what was' discussed, in Section 1.0 also applies
when the LM1204'is used with the blanking function. However, there are notable'differences as described herein. For
operation with, blanking, a TIL, compatible blanking signal
must be,applied to the blank gate input (pin 24).
During the blanking, period, the blanking comparator conn&cts, switch 52 to position X (See Figure 2). This causes
the LM1204 to level shift the video output signal to the blank
level. Adjusting A9 will adjust the blank level of all three
,channels. Indivld\JBI ,bl~nk"I~el adjustment for each channel is done by 'varying the ,feedback voltage at each of the
A, G. ~nd B feedback i~.puts (pin 38, 28 and 33). In FlflUre 2
this IS d9ne by, adjusting potentiometer R8 for the green
chal).,el.
During the video portion of the Video signal, S2 is connected
to position Y. Brightn8$s control is now accomplished by
varying the potertial at the brightness control pin (pin 20).
Adjusting R6 offsets the 'video portion of all three output
signals relative to the fixed blank level, restoring the DC
level of the video signal. Figure 5 shows the adjustments for
operation with blanking.
',

1.0 Operation' without Blanking
For operation without blanking, the bla,nk gate input (pin 24)
should"be connected to +4V. This causes the blank cilmparator to connect switch S2 to'position Y(See Figure2j.
Furthermore, the brightness control, input pin (pin 20) should
be biased at a potenti~ lietween 1V (Min) and 3.8V (Max), it
is best. to bias this pin !it 2V. The video signal is AC Coupled
to the Input of the LM1204 as shown for the green channel
in Figure 2. During the back porch interval of the video signal (See Figure 3), thEl' internally generated back porch
clamping pulse goes lOW, causing sWitch&s S1 A and S1 B to
be closed.,The closure of S1 A causes gin 1 to charge capacitor C2 to a potential determined by the DC voltage at pin
20. This allows gm1 to set up an average DC bias for the Ac',
coupled video signal at the input of A1. When the ,back
porch clamping .pulse is high, S1A and S1B are opened.
With S1 A open, gm 1 is effectively disconnected from C2, C2
now holds the DC bias voltage. The transconductance
stage gm1 therefore functions as a sample and hold d&llice
and holds the input of A1 at the desired DC bias.
The LM1204 uses black level clamping at the back porch of
the video signal to accomplish DC restoration. The transconductance stage gm2 is enabled during the back porch
clamp periOd to provide a sample and hold function. During
the back porch clamp period, DC feedback from LM1204's
video output is compared with the voltage set by potentiometer A9. Depending on A2's output voltage, C6 is either
charged or discharged so ,that the feedl?ack loop ,consisting
of gm2 and A2 is stabilized and the output is clamp8d to the
black level. All this occurs during the Qack porch clamp period" During the video portion of the signal', gln2 is disabled
and C6 holds, the fixed blapk level reference Voltage. T~
begipning of $Sch new line on the raster always starts
a fixed, refeten~black level thus .restoring ,the DC coinponent of each line.
" , "

from

A2 is a summing amplifi~r that ,adds ~ DC off~t:component
from gm2 to\the video !lig~ from ,the multiplier. Adjusting
A9 will DC offset the output signals of all three cljannels
thus providing brightn&SS control. Individual cutoff adjust-

3.0 Stability Considerations
For optimum performance' and stable operation, a, double
sided PC board with adequate ground plane is &ssential.
Moreover, soldering the LM1204 on to the PC board will
yield best results. Each supply pin (pins 2, 4, 6, 19, 31, 36;
41 an~ 44) shouilj be bypassed with a 0.01 ",F and a 0.1 ",F
capaCitor connected as close to the supply pin as is possible. ,
"
When driving tl)eLM1204 from a 750 vid&a soufc.e"the
cable is terminatecjl/iith 750 to minimize reflections caused
by transmission,line ~&cts., However, the input impedance
C?f, LM1204 is capaCfitive and is also affected, by the'stray
C~4:lltance of the, J;'C board. Thus the input lI'npedance is a
function of frequency. This ch8ng&s the Impedance onlle
'~able termination. Tills can introduce overShoot and ringing
In LM1204's pulse response. A 1000 r&sistor in seri&s with
the' blocking capacitOr at the video input will minimize over, shoot and ringing (see Figure 8). The value of the resistor is
empineally determined.· 1000 is' a good starting value.
, SinCe the LM1~04 is a ~ide bandwidth amplifier with high
gai,n at!1igh freqiUlnci&s, thed9vlce may oscillate when driving a latge C8.pacitive/inductive load. To prevent oscillation
the 'amplifier's gain is rolled off at high frequenci&s: This i~
accomplished by an AC network comprised of a,resiStor'in

2-90

3.0 Stability Considerations (Continued)

Non-Gated High
Frequency Application

series with a capacitor connected from the video output pin
to ground (see Test Circuit, Figure 1). A 1100. to 200'.l
resistor in series with 10 pF is quite adequate for most applications. However, if oscillations don't cease then the value
of the resistor should be decreased or the value of the capacitor should be increased or a combination of the two.

By connecting the back porch width adjust pin (pin 22) to
Vee, the LM1204 functions as a non-gated amplifier requiring no sync or blanking signals. Figure 9 shows a triple high
frequency amplifier with variable gain and DC offset control.
In this mode' of operation, filtered DC feedback must be
provided to pins 28, 33 and 38 as shown in Figure 9.

LM1204
CRT
VIDEO
AMPLIFIER
R.B

4V

RI
BRIGHTNESS
CONTROL

R.B

%>

R4

n-..!!!...J-------t;;;;..-~ ~~P~:H ADJUST
0/- H ~L::23:.t,_S_Y_NC_PR_OC_ESSO-=TRJ.;;21;....-_--o _ H SYNC OUTPUT
INPUT .......,.

1.4V

0

24 _

25

C3
INTEGRATING T
CAPACITOR ~

•

BLANK
•
COIIPARATOR'
•

--.I

BLANK GATE

INPUT
TUH/II238-9

FIGURE 2. Block DIagram Showing Timing Chrcuitry and Green Video Channel

COMPOSITE VIDEO
SIGNAL

-

h

REFERENCE. BLACK LEVEL
(CUTOFF VOLTAGE)

VIDEO --LSYNC~
PORTION------rPORTIONl.

BLANKING
PERIOD

CLAMPING PULSE

---u

c:=

IL:

S1 A, B OPEN

- H SYNC PULSEr--_ _ _ _....,

1J

r:..
---u-

:=t

BACK PORCH
CLAMP PERIOD

S1 A, B CLOSED

-=t.F

U

H SYNC PERIOD
TUH/11238-10

FIGURE 3. ComposHe Video and Timing Signals

2-91

4V
R"
~

BO
~ GAIN
~ GAIN

GAIN

- H SYNC OUTPUT

R. G. B VIDEO INPUT
7.11.17

2S

40.35.30

Vee
+I2V

R. G. B FEEDBACK
38.28.33
(CUTOfF ADJUST)

:------J
! !

4V

BLANK GATE
INPUT
Sl-

Vee
+12V

+4V

BP
CUIIP
WIDTH
ADJUST

lOOk

BLANK LEVEl ADJUST
.(FOR BRIGHTNESS CONTROL)
TLlH/11238-11

~
Ls-

CONTRAST CONTROL VARIES AC GAIN (PEAK TO PEAK AMPLITUDE)
RELATIVE TO THE FIXED BlACK REFERENCE LEVEL (AU THREE CHANNELS).
SEE DASHED WAVEFORII.

. . VIDEO

SYNC

..FL<'
--"~-~.' WV

~CK :FER;CE LEVEL

~ GAIN ALLOWS INDIVIDUAL
ADJUSTMENT OF AC GAIN OF
EACH CHANNEl.

"
•

"

~

..

TIP

.

~

"

~

- H SYNC OUTPUT. PIN 26
(WITH PIN 24 AT +4V)

n==-

INTERNAL BACK PORCH CUIIP PULSE OUTPUT.
PIN 26 (",TH PIN 24 CONNECTED TO Vee)

-WI-- BP WIDTH ADJUSTABLE FROM
0.31'1 TO 41'1
TL/H/11238-12

R. G. B FEEDBACK ALLOWS INDIVIDUAL
4DJUSTIIENT OF BLACK REFERENCE (CUTOFF)
LEVEL FOR EACH. CHANNEL.

TLlH/11238-13

BLANK LEVEL ADJUST DC OFFSETS THE ENTIRE WAVEFORM.
ALLOWING BRIGHTNESS CONTROL (ALL THREE CHANNELS).
SEE DASHED WAVEFORM.

TLlH/11238-14

FIGURE 4. LM1204 Adjustments without Blanking

2-92

4V

lOOk
- H SYNC OUTPUT

R, G, B VIDEO INPUT

26

7,11,17

40,35,30

R, G, B FEEDBACK

38,28,33
CRT CATHODE

(INDIVIDUAL BlANK LEVEL ADJUST)

20
4Vo--....- - - .

BLANK GATE
INPUT

.cl------...,

Sl~
Vee

+12V

A

BLANKING PULSE

--, r---::::J
LJ

r::-- -

--w--

BP
WIDTH
ADJUST

4V

-OV

BLANKING PERIOD

BLANK LEVEL ADJUST DC OFFSETS THE ENTIRE WAVEFORM
TO SET BLANK LEVEL (ALL THREE CHANNELS). SEE DASHED
WAVEFORM.
lOOk

BLANK LEVEL ADJUST
VIDEO OUTPUT _ _ _ _~_...I_"

~

VIDEO

AT CRT BLANK PEDESTAL

SYNC
TIP

,

r

,BLANKING SIGNAL APPLIED TO PIN 24

-,1...-_........r- BLANKING PERIOD

--,L-..Jr -

- H SYNC OUTPUT, PIN 26
(WITH BLANKING SIGNAL
APPLIED TO PIN 24)

INTERNAL BACK PORCH CLAMP PULSE OUTPUT,
PIN 26 (WITH PIN 24 CONNECTED TO Vee)

CONTRAST CONTROL VARIES AC GAIN (PEAK
TO PEAK AMPLITUDE) OF VIDEO PORTION
RELATIVE TO THE FIXED BLANK REFERENCE
LEVEL (ALL THREE CHANNELS).
A GAIN ALLOWS INDIVIDUAL ADJUSTMENT
OF AC AND DC GAIN OF EACH CHANNEl.

VIDEO OUTPUT _ _ _...,~_...,.....
AT CRT BLANK PEDESTAL

~ 0.3}1s

INCREASED BLANK
PEDESTAL DUE TO
BRIGHTNESS CONTROL

BP WIDTH ADJUSTABLE FROM
TO 41's

BRIGHTNESS CONTROL DC OFFSETS
THE VIDEO PORTION OF THE SIGNAL
RELATIVE TO THE FIXED BLANK
LEVEL. ALSO INCREASES OR

,,

/ ' NEW BlACK
/'
LEVEl"

" ,
""• ""•

DECREASES THE BLANK PEDESTAL

HEIGHT. SEE DASHED WAVEFORM.

TL/H/11238-1S

FIGURE 5. LM1204 Adjustments with Blanking

2-93

•

LM1204

~

0.1

"CI

~

Vee
R VIDEO OUT

R
VIDEO
IN

R13
40k
C14

HI
75D

I

~

----t

"CI

CRT VIDEO AMPLIfiER

=1>-1...
Al

"2-

(GREEN CHANNEL)

ooo,~~ ~

~

V+
+BOV

O·

4 GAIN ADJ.

::J
(I)

=1>-1

~.

~~~~ ~

' . A GAIl! ADJ.

,

o
c

A2

TO CRT CATHODE

=1>-1
.

~

.

m~~ ~

4 GAINAD,I.

LM1204

G

COMPOSITE
VIDEO SYNC
SEPARATOR

VID~~ OO-....._-4.~'·;..jI~

if

BLANKING
BRIGHTNESS

BACK PORCH
CLAMP
GENERATOR

Vee

+/-

HSYNC
PROCESSOR

G VIDEO OUT

--_.-

G FEEDBACK

"

(CUTOfF ADJUST),

10PF

- 4V

TLlH/II238-18

FIGURE 6. The LM1204 driving C8acode CRT ~o amplifiers arid operating without blanking. Brightness control Is accomplished by potentiometer R12 (See F/gure4
for explanation of adjustments). Each
pin should be bypassecl with a 0.01 p.F and a 0.1 p.F capaCitor connected as close to the pin as Is possible.

Vee

~~.

Vee

»

R VIDEO OUT

"a

CRT VIDEO AMPLIFIER

'2

(GREEN CHANNEL)

"
."" ..,:
~ommY~

&

V+
+60V

0'

:

:::lI

fIJ

o

~i'

~~~
"

c

i

"n: :

i'"

~~~
AI

I))

3:

4 GA1N_ ADJ.

.

A2

1

_

LM1204

G

VID~~

COMPOSITE
VIDEO SYNC
SEPARATOR

Oo-_,_. .

,;::-·:JI~

BLANKING
BRIGHTNESS

BACK PORCH
CLAMP
GENERATOR

+/-

HSYNC
PROCESSOR

G VIDEO OUT

G FEEDBACK
(CUTOFF ADJUST)

-=

BRIGHTNESS

- -=

CONTRAST

BP

WIDTH
ADJUST

BLANK
GATE
IN

BLANKING SIGNAl

~INGPERIOD
TUH/1123B-17

FIGURE 7. The LM1204 driving cascode CRT video amplifiers and operating with blanking. The video signal Is level shifted to the user adjustable blank level
during the blanking period. Brightness control DC offsets the video signal relative to the fixed blank level and is accomplished by potentiometer R7. See FIgure 5
for explanation of adjustments. Each Vee pin should be bypassed with a 0.01 ,...F and a 0.1 ,...F capacitor connected as close to the pin as is possible.

tOi:un

II

I~

:::i

....

Typical Applications Circuits (Continued)
02
27k'

~C4S

(+4V)

~22 ~21

..
88.

BLUE'
VIDEO.~+t-_.......jHr--::;::....o1-l

• 23

022

IN

RED
VIDEO CC!3+.,..-I.-~I-+="""'"I
IN

00. '20

Rlt.

110

GREEN

.11

VIDEO~+~_,",",IHr--::;:"'1-I

R17

.

IN

.,lpF

tH/HV

SYNC (~--1---------~~------------~--------------~
IN

75

TLIH/11238-18

FIGURE 8. Complete circuitry for an RGB CRT video board using the LM1204 anet LH2426AS.
The video output signals from LH2426AS are AC coupled and diode clamped to greater than 80V.

2-96

Typical Applications Circuits (Continued)

411/2W

...
...

11

471/2W

8

47 liD

".

6

NC

4

NC

12

220k

"o--W~t---+-{

" --+-l
.. o--Wlr-.....
CRT SOCKET

TL/H/11238-20

FIGURE 8. (Continued)

•
2-97

OC OfFSET CONTROL
(ALL THREE CHANNELS)

0.1

Vcc
Rt3
50k

VIN 1

I -to
Ct4

Rt
75/1

={;>-1

I'F

mown H?-

A GAIN ADJ.

A2

=1>4 ~wnH?={;>-1"
H?-

"

i

AI

,

'

A,GAIN ADJ.

--=

A GAIN ADJ.

,

.A2

LM1204

VIN3~~7:~1

COMPOSITE
VIDEO SYNC
SEPARATOR

BLANKING
BRIGHTNESS

BACK PORCH
CLAMP
GENERATOR

+/-

H SYNC
PROCESSOR'

tOk

tOI'F
OC OFFSET CONTROL, "OUT3

i.

'."

-.

TL/H/II238-19

FIGURE 9. Three channel high frequency amplifier with gain and DC off88t~ntrol (non-video application). Each Vee pin should be
bypaesed with a 0.01 p.F and a 0.1 p.F capacitor co.nriected as close to the pln,as fs possible.
'

t!lNational Semiconductor

LM 1205/LM 1207
130 MHz/85 MHz RGB Video Amplifier System with
Blanking
General Description
The LM1205/LM1207 is a very high frequency video amplifier system intended for use in high resolution RGB monitor
applications. In addition to the three matched video amplifiers, the LM1205/LM1207 contains three gated single ended input black level clamp comparators for brightness control, three matched DC controlled attenuators for contrast
control, and three DC controlled sub-contrast attenuators
providing gain trim capability for white balance. All DC control inputs offer high input impedance and an operation
range from OV to 4V for easy interface to bus controlled
alignment systems. The LM1205/LM1207 also contains a
blanking circuit which clamps the video output voltage during blanking to within 0.1 V above ground. This feature providel! blanking capability at the cathodes of the CRT. A spot
killer is provided for CRT phosphor protection during powerdown.

Features
• Three wideband video amplifiers 130 MHz (LM1205) @.'
-3 dB (4 Vpp output)
• Matched (± 0.1 dB or 1.2%) attenuators for contrast
control

• Three externally gated single ended input comparators
for cutoff and brightness control
• OV to 4V, high input impedance DC contrast control
(>40 dB range)
• OV to 4V, high input impedance DC drive control for
each video amplifier (-6 dB to 0 dB range)
• Spot killer, blanks output when Vee < 10.6V
• capable of 7 Vpp output swing (Slight reduction in
bandwidth)
• Output stage blanking
• Output stage directly drives most hybrid or discrete
CRT drivers

Applications
•
•
•
•

High resolution RGB CRT monitors
Video AGC amplifiers
Wideband amplifiers with gain and DC offset controls
Interface amplifiers for LCD or CCD systems

Block and Connection Diagram

TLlH/11881-1

FIGURE 1
Order Number LM1205N or LM1207N
See NS Package Number N28B

2-99

Absolute Maximum Ratings (Note 1)

Operating Ratings

If Military/Aerospace specified devices are requlrec:i.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vcc)
Pins 3, 11, 22, 23, 25 (Note 3)
15V
"'
Peak Video Output Source Current
(Any One Amp) Pins 17, 20 or 26
28mA
Voltage at Any Input Pin (VIN)
Vcc ~ VIN ~ GND
Power Dissipation (Po)
(Above 25°C Derate Based on 8JA and TJ)
2.5W
50"C/W
Thermal Resistance (8JAl
Junction Temperature (TJ)
15O"C
ESD Susceptibility (Note 4)
2kV
Pins 12,13 and 14
1.9,kV
Storage Temperature
- 65°C to 15O"C
Lead Temperature (Soldering, 10 sec.)
265°C

Temperature Range
Supply Voltage (Vee>

(Note 2)
-20"Cto 80"C
10.8V s; Vcc s; 13.2V

I
"

DC Electrical Characteristics See DC Test Circuit (Figure 2), TA = 25°C; Veel = VCC2 = 12V. V12 = 4V;
= OV; Vcut-off = 1.0V; V13 = 4V; Vdrive = 4V unless.otherwise stated.

V14

Symbol

Conditions '

Parameter

Is

Supply Current

V4,6,9

Video Amplifier Input Bi.sVoltage

RIN

Video Input Resistance

V141
Vl4h

Veel

Typical
(Note.S)

Umlt
(Note 6)

Units

90

105

mA(max)

+ VCC2, RL = 00 (Note 7)

2.8

V

Any One Amplifier

20

kO

Clamp Gate Low Input Voltage

Clamp Comparators On

1.2

0.8

Clamp Gate High Input Voltage

Clamp Comparators Off

1.6

2.0

V (min)

1141

Clamp Gate Low Input Current

V14

-:-1

-5

pA(max)

114h

Clamp Gate High Input Current

0.01

1.0

p.A(max)

Iclamp

Clamp Cap Charge Current

Clamp Comparators On

±750

±500

pA(min)

Ibias

Clamp Cap .Bias Discharge Current

Clamp Comparators Off

500

V131

Blank Gate Low I'nput Voltage

Blank Gate On'

1.2

0.8

V (max)

V13h

Blank Gate High Input Voltage

Blank Gate Off

1131

Blank Gate Low Input Current

113h

Blank Gate High Input Current

VOL

Video Output Low Voltage

VOH

Video Output High Voltage

VO(1V)

Video Black Level Output Voltage

aVO(tV)

Video a Black Level Output Voltage

VoL
i3

-40

0

1=
«

1/

RED,
~

-50

.? P

-60

~
BLUE I

/'

"

~

\,

,~

~

"

~

W

-70
-80

100

10 '
FREQUENCY (MHz)

LM1205 Contrast vs Frequency

'iii'
.3

"

V12 = 4.0V
= 1.45V

-10

...
/~
...z

-20

0

.!:!
z

-50

:;;:

-60

'"

-70

.......
~

= 0.65V

-

= 0.34V

-30

= 0.25V'
= 0.20V

-40

...... l"'--4
I~
TJ

l\
I>

VOUT = 4 Vpp (REF)
rVE=r'4

1,

10'

100

FREQUENCY (MHz)
,UH/11881-5
J"

,LM1205 Drive vsFrequency

,

I
o
-1
, ~2

-3
-4
-5
-6

VOUT = 4 Vpp (REF)
CONTRAST = 4V

VORIVE = 4.0V

I'

- 3.0V
~

~

2.SV

I\\.\.
,\'\

= 1.7V
= 1.2V
= 0.6V

,\.

= O.OV

,\., '\

I
I

\\\
\ '\ I
10
FREQUENCY (MHz)

2-102

100
TUHI11881-6

Typical Performance Characteristics

Vee = 12V. TA = 25"C unless otherwise specified (Continued)

LM1207 Crosstalk vs Frequency
GREEN (MAX CONTRAST .I: DRIVE)

~

-10

a;~

z

-30

;::

-40

0

«
z&oJ

:::>

5

r-......

-20

"'"
J,f

-50

b Io==~

-60
-70

'\.

RED

~

l"t

I'

J'r'Ii

'BLUE

V1.4'
10

100

FREQUENCY (MHz)

TL/H/11881-7

LM1207 Contrast vs Frequency
V12 - 4.ov'

a;-

-10

~

-20

t;

-30

~
z
0
'-'
......

-40

z:

;;:

-60

'"

-70

«

-50

Your = 4 Vpp (REr)
~DRIVE

= 1.44V
= 0.65V
= 0.38V

-

= 4V

t:-:--,.. C"-,
k~
I~

- 0.27V

!-"

= 0.21V

10

-"'[7

100

FREQUENCY (MHz)
TL/H/11881-8

LM1207 Drive vs Frequency
VORIVE

!
!t:
ii:
c

......
z
;;:

'"

-1
-2
-3
-4

-5
-6

~ 4.0V

.111

--.....
--:--....
c:---.
---....
---

= 3.2V
= 2.5V
= 1.8V
= 1.2V
= 0.7V
= O.IV

:::::::--

I
I

_I.

Your = 4 Vpp (REF)
CONTRAST

.....
......
.....

......
......

......

= 4V

l'
l\

1\\
l'I\'\

'\ 1"\1\ .\ \

10

100

FREQUENCY (MHz)
TLtH/I1881-9

2·103

•

Applications Information
Vee (+12V)

LM1205N/
LM1207N
30

RED
1--~~:'t"----1h CUT-Off

TOP VIEW
RED
VIDEO
OUT

RED
VIDEO
IN

BLUE
VIDEO
IN

t-.-;;..--......----1r+-{V20

GREEN
VIDEO
OUT

GREEN
DRIVE
CONTRAST
BLUE
VIDEO
OUT

BLUE
I---=-~:'t"----' DRIVE
100

TLlH/11881-10

FIGURE 2. LM1205N/LM1207N DC Test Circuit

2-104

Applications Information

(Continued)
Vee (+12V)

100 }.IF

RED
DRIVE

LM1205N/
LM1207N
30

RED
VIDEO
OUT

TOP VIEW

t - - t - -.....---+-{V26
390

OUTPUT TO
A LOAD
OVER lOOk

I\.
RED
VIDEO
IN

GREEN
VIDEO
IN

BLUE
VIDEO
IN

GREEN
DRIVE

4V

•

CONTRAST

BLUE
DRIVE

TLlH/11881-11

FIGURE 3. LM1205N/LM1207N AC Test Circuit
2-105

~ r-------------------~----------------~~----~--------~--~----------------,

....~

:=E
;;.J

Applications Information (Continued)

.~

,...

,'.1.,'

Vee (+I2V)

....~

:i

lOO}.lr

'Lt,11205N/
Lt,11207N
30

+

. RED

t--~-:-::'t'--"";"'h CUT-orr

TOP VIEW
RED
1--+--"+---H."".,o'Ir-('V26 VIDEO
430
OUT'

RED
VIDEO
IN

BLUE
VIDEO
IN

430

GREEN
V20 VIDEO
OUT'

GREEN
CUT-orr

GREEN
DRIVE

~I7

430

BLUE
VIDEO
OUT'

BLUE
CUT-orr

, 5011 TERMINATION TO
BE USED AT OUTPUTS
TUH/11881-12

FIGURE 4. LM1205N/LM1207N PCB Test Circuit

r-----------------------------------------------------------~~

Applications Information

(Continued)
Figure 5 shows the block diagram of a typical analog RGe
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of
other applications that benefit from the use of color display
terminals. The RGB color monitor characteristics may differ
in such ways as sweep rates, screen size, CRT color trio
spacing (dot pitch), or in video amplifier bandwidths but will
still be generally configured as shown in Figure 5. Separate
horizontal and vertical sync Signals may be required or they
may be contained in the green video input signal. The video
input signals are usually supplied by coax cable which is
terminated into 750, at the monitor input and internally AC
coupled to the video amplifiers. These input signals are approximately 1V peak to peak in amplitude and at the input of
the high voltage video section, approximately 5V peak to
peak. At the cathode of the CRT the video signals can be as
high as 60V peak to peak. One important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range. The
Figure 5 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function. of the
LM1205/LM1207 which contains the three matched video
amplifiers, contrast control and brightness control. The
LM1205/LM1207 also provides the capability to blank at the
cathode of the CRT.

Functional Description
Figure is is a detailed block diagram of the green channel of
the LM1205/LM1207 along with the recommended external
components. The IC pin numbers are circled and all external
componen1s are shown outside the dashed line. The other
two video channels are identical to the green channel, only
the numbers to the pins unique to each channel are different. The input video is normally terminated into 75.0. The

termination resistor depends on the impedance of ,the coax
cable being used, 750, being the most common impedance
used in video applications. The video signal is AC coupled
through a 10 ",F capacitor to the input, pin 6. 'There is no
standard for the DC level of a video signal, therefore the
signal must be AC coupled to the LM1205/LM1207. Internal
to the LM1205/LM1207 is a 2.8V reference, giving the input
video an offset voltage of 2.8V. This voltage was selected to
give the input video enough DC offset to guarantee that the
lowest vOltage' of the 'video signal at pin 6 is far enough
above ground to keep the LM1205/LM1207 in the active
region. The 2000, resistor at the input is for ESD protection
and for current limiting during any voltage surge that may
occur at the input, driving pin 6 above Vee. The input video
signal is buffered by - A 1. In this circuit description an Inverting amplifier is shown with a "-" (minus' sign) in front of
the amplifier designation. The output of - A 1 goes to the
contrast and drive attenuator sections.
The contrast and drive control sections are virtually identical. Both sections·take a OV to 4V input voltage, 4V giving
the maximum gain for either the contrast or the drive. This is
a high impedance input, allowing for an·easy interface to 5V
DACs. One may also use 100k potentiometers with no degradation in performance. The contrast control section is
common to all three channels. It converts the input voltage
at pin 12 to a couple of internal DC voltages that control the
gain of the contrast attenuator. Referring to the Attenuation
vs Contrast Voltage under typical performance characteristics note that a 4V control voltage results in no attenuation
of the video Signal. A 0.25V control voltage results in' an
attenuation of 40 dB. Again note that these internal control
voltages are common to all three channels. To minimize
crosstalk, these voltages go to pins 1 and 2. MiniJl'lizing
crosstalk is done by adding the flC network shown in the
block diagram (Figure 6).

vo-~~-I

SYNC IN

Ho--II--I

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS

VIDEO IN

G 0----1'-'---1

VIDEO At.lPLlfICATION
WITH GAl N / DC
CONTROL

CONTRAST

BRIGHTNESS

FIGURE 5. Typical RGB Color Monitor Block Diagram

TLlH/11881-13

....
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en

r=

!:
~

~

Functio.nal Description (Continued)
Thfi! OV.to 4V drive contr()1 signal comes' in on pin 18. Each
challnel has its own drive section, thereforE! the crosstalk
compensation needed for the contrast control voltages is
not required for the drive cpntrol, thus no extemal pins for
the drive control. The drive attenuator gives an attenuation
range from 0 dB to -6 dB. A small gain ,adjustment range
for the dr!ve. attenuator is desirable and intentionally designed because the drive is used only to balance the overall
gain of each color channel, giving the .correct color tempera'
ture on t~e CRT.

to the inverting input of the clamp comparator via the .voltage divider formed by the 5000 and 4k resistors. - A4 will
be close to the seme output as - A3 and will temperature
track due to the similar design of the two output stages.
However, the current at the output of -A4 will be ten times
the current at the output of-A3. To balance both outputs,. a
load resistance of 3900 needs to be connected from pin 20,
the green video output pin, to ground. Another input to - A4
is the blank pulse. When a negative going blank pulse is
applied to pin 13, the output oBhe LM120S/LM1207 is driven to less than O.tV above ground. Using the timing shown
in Figure 7 for the blank pulse, the output of the LM120S1
LM1207 will be less than 0.1V during the inactive portion of
the video signal. This is a "blacker than black" condition,
blanking the CRT at the cathodes. By using the blank function of the LM120S/LM1207 no grid blanking is necessary.
Note that the DC restor~tiol'l is done by feeding. back the
video signal from .- A3, but blanking is done at - A4. By
using the two output stages, .blanking can be done at the
CRT cathodes; and at the same time activate the DC restoration loop;

The output of the, drive attenuator stage goes to A2, the
amplifier in the DC restoration section. The video signal
goes to the non'lnverting input of A2. The invertir:lg side of
A2.goes to the output of gm1, the clamp comparator, and
the clamp capacitor at pin 8.
During the back porch period of the video signal a negative
going clamp pulse from pin 14is applied to the clamp comparator, turning on the comparator. This period is where the
black level of the video signal at the output of the LM120S1
LM1207 is compared to the desired black level which is.set
at pin 19. F/{/ure 7 shows the timing of the clamp pulse
relative to the video signal. The clamp capacitor is ctrarged
or discharged by gm1, generating the correction voltage
needed at the inverting .input of A2 to set the video output to
the correct DC level. Removing the clamp pulse turns off
gm1 with the correction voltage being maintained by the
clamp capacitor during active video. Both the clamp pulse
and ·the blank pulse at pin 13 are TTL voltage levels.

VCC1 goes to pins 3, 11, and 2S (see Figure 1). These three
pins are all internally connected. For proper operation of the
LM120S/LM1207'it is necessary to connect all the VCC1
pins to the input power to the PCB and bypass each pin with
a 0.1 p.F capacitor. VCC2 is the input power at pins 22 and
23 for the three output stages. This is a separate power
input from VCC1, there are no internal connections between
the two different power inputs. There must be a com'lection
on tile PCB between VCC1 and VCC2. Pins 22 and 23 must
be bypassed by a parallel connection of a 10 p.F and 0.1 p.F
capacitors. The gro!lnd, connections for the LM120S1
LM 1207 are at pins 7, 21, and 24. All three ground, pins are
internally connected, .and these pins must also be connected externally to a good ground plane for proper operation of
the LM120S/LM1207.

There are actually two output sections, ,- A3 and - A4. Both
sections have been designed to be identical, except - A4
has more current drive capability. The output transistor
shown is part of - A4; but has been shown separately so
the user knows the configuration of the output stage. - A3
does not go to the outside world, it is used for feeding back
the video Signal for DC restoration. Its output goes directly

2-108

Functional Description

(Continued)
30

r-----------

-----------------,

GRE~~ VI~~:

*
!
75

4V

lOOk

OTHER TWO
CHANNELS

4Vl
100k*

~O.l~F :

GREEN
VIDEO
OUT

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390

500

}-____+-____

+4V

~--~~~:------+-4-k-----------------------{" ·",.,1""
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~

~ O. 1 ~F ~ ___________________________ ~
TL/H/11881-14

FIGURE 6. Block Diagram of LM1205/LM1207 Video Amplifier

w

input is applied to pin 6 via a 10 ,iF coupling capacitor and a

30a resistor. The resistor is added to limit the current
VIDEO

CLAMP
PULSE

......U'"--',---.......,'u:,

--"~--

1]"",
I
I

through the input pin should an applied voltage surge rise
above Vee or drop below ground. The performance of the
LM1205/LM1207 is not degraded by the 30a resistor. However, if EMI is a concern this resistor can be increased to
well over 100a where the rise and fall times will start to
become longer. DC bias to the input pin is provided by 05
and its associated input circuitry. Z1 is a 5.6V zener that
generates the input bias voltage. 01 is a buffer to the zener
reference voltage with 5.0V generated at its emitter. 03 and
04 are connected as diodes. 02 is close to being a diode in
this circuit. This configuration will give about 2.0V at the
collector of 02. R2 and R3 are a voltage divider, setting the
base of 05 to about 3.5V. This sets the emitter of 05 to
about 2.BV, the bias voltage of the video input. This bias
voltage is necessary to assure that the entire video signal
stays within the active operating region of the LM12051
LM1207. The bias voltage goes' through R6, a 20k resistor,
to the video input at pin 6. R4 and R6 are of the same value

'

,
,

BLANK
PULSE

" TTL LEVELS

,
I

TTL LEVELS
TLlH/11881-16

FIGURE 7. Timing Diagram

Circuit Description
VIDEO AMPLIFIER INPUT STAGE
Figure 8 is a simplified schematic of one of the three video
amplifiers input stage along with the recommended external
components. The IC pin numbers are circled and all external
components are shown outside the dashed line. The video

2-109

fII

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....~

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....~

:::::&
....I

Circuit Description (Continued)
cuits. Each channel has its own drive control circuit. Increasing the voltage to the base of 011 increases the video
'gain ,(drive) of the LM1205/LM1207. R10 and R11 are of
the same value, but R10 is common to both 010 and 011.lf
all the current is flowing through 010, the video amplitude
would only be half of the ma,ximum gain (all current flowing
through 011). This gives the drive control a total gain adjustment range of 6.dB. Since the drive control is only used
to balance the color of each channel a small adjustment
range is desirable. 012 through 017 are part of the final
section shown in Figure ,8. DC restoration is done at this
stage. The clamp comparator (Figure 11) drives the clamp
cap at pin 8 to a voltage that sets the correct black level of
the video signal. This cap is also connected to the base of
017.017 and 016 are one half of the darlington differential
pair. The clamp cap voltage establishes the current flow
throllgh R16, 015, and R15. With the bases of 014 and
015 held to the same voltage' the current through 015 is
mirrored into 014 and the other half of the differential pair,
012 and 013. By this current mirror the voltage at the collector of 014 is set to the correct DC value"for the vid~
signal by controlling the voltage drop across R13, completing the DC restoration.

and R4 is used to compensate for beta variations of the
transistors. Note that the bias voltage passes through three
diode drops (05, 06, and 07) before setting the voltage
across R9. 02, 03, and 04 also provide three diode drops
to the bias voltage at the base of 05, temperature compensating for the diode drops of 05,06, and 07. This insures
that the bias voltage across R9 remains very constant over
temperature, providing an accurate bias current for the differential transistor pair 08 and 09, thus assuring proper operation of the contrast control.
,
06 serves as a buffer to the input video, signal. Its emitter
drives the base of 07. Thus the video signalmodu,lates the
current flowing through R9; which in turn modulates the currents through the differential pair formed by 08 and 09. The
current flow through 08 and 09 Is controlled by a D,C voltage from the Contrast Control circuit. This DC voltage is
common to all three channels. Increasing the" voltage to the
base of 09 with respect to the base of 08 increases the
current flow through 09. A higher current flow through 09
increases the video gain (contrast) of the LM1205/LM1207.
010 and 011 also form a differential pair at the collector of
09. The operation of this differential pair is similar to 08 and
09. The DC control voltage is from the Drive Control cir-

Vee

PUSH PULL CURRENT

~~-.--~~--~--~---.--~~~~----~~--~~----.__, F~WCUMP

COMPARATOR
FIGURE II

R2
1.5k

R3
t.Sk

Rt6

3000
TO VIDEO AMP
OUTPUT STAGE
FIGURE 14

RtS

tOO

.----~------- -------------------------------------~
30 ' 4 9

VIDEO INPUT

,FIGURE 8. Simplifiet;l $che~tlc of LM1205/LM1207 Video Amplifier Input Stage

'2-110

TUHItI88i-16

Circuit Description

(Continued)
channels. In the balanced condition the voltage at pin 2 will
also be two diode drops below YzVcc, giving a well balanced drive to the differential pair consisting of 08 and 09
in the video amplifier input stage. With the contrast voltage
set to OV, the voltage at pin 2 will increase by about 400 mV
to 500 mY. A 4V contrast voltage decreases the voltage at
pin 2 by about 400 mV to 500 mV from the balanced condition. Reviewing Figure 8 note that decreasing the voltage at
pin 2 will decrease the current flow through 08. Thus the
current flow through 09 increases, increasing the gain of
the LM1205/LM1207. So increasing the contrast control
voltage at pin 12 increases the gain of the LM12051
LM1207. The contrast control voltage from 046 and 050 is
common to all three channels. To minimize crosstalk it is
necessary to add a decoupling capacitor of 0.1 jJ-F across
R37 and R40. Since this can only be done externally, these
two nodes are brought out to pins 1 and 2. The 300 resistor
is added in series with the capacitor for improving stability.
To prevent a destructive current surge due to shorting either
pins 1 or 2 to ground R38 was added for current limiting.

CONTRAST CONTROL

Figure 9 is a simplified schematic of the Contrast Control
circuit. The output of this circuit is common to all three channels. A reference voltage is generated by Z2, 034, 035,
R30, and R31. 036. 039, and 041 are all current sources
that arc controlled by the reference voltage. The contrast
signal has a OV to 4V range with its input at pin 12. R32 is
used for current limiting any voltage surge that may occur at
pin 12. Note that the input stage (037, 038, and 042) are
all PNP transistors. This configuration is necessary for operation down to near ground. At 044 the input voltage is converted to a current by R33. The input stage will apply the
same voltage across R33 as is applied at the input and with
no temperature variations from the transistors. 037 is connected to a current source (036) to keep a constant current
flow through 037 and a predictable diode voltage for the
bass-emitter of 037. 040 is connected as a diode and is
biased by the current source 039. The current through 040
is mirrored into 043, giving a current bias for 042. Again this
is done to give a predictable diode voltage for 042. 041 is a
current source for both 038 and 042. With the current
through 042 already established, the rest of the current
from 041 flows through 038. As one can see the input voltage is accurately reflected across R33 with no temperature
coefficients from the input stage of the contrast control circuit.

DRIVE CONTROL

Figure 10 is a simplified schematic of the Drive Control circuit. Each channel has its own drive control circuit. This
circuit is almost identical to Figure 9, the contrast control
circuit. It will be easier to cover the differences between the
two circuits instead of going through virtually the same circuit description. Note that the input stage is exactly the
same. The generation of the reference voltage at the right
hand side of Figure 10 is slightly different than the circuit in
Figure 9. In the drive control circuit the reference voltage at
the base of 072 is to be %Vcc. In the contrast control
circuit the reference voltage at the base of 051 was to be
YzVcc. To generate the %Vcc R57 and R58 form a 2 to 1
voltage divider. With the two to one ratio it is now necessary
to have three transistors connected as diodes, which are
074, 075, and 076. 073 is the buffer for this voltage divider
and its emitter is exactly %Vcc with temperature compensation. R52 and R53 also differ from their corresponding
resistors in Figure 9, R36 and R39. The value difference is
so the base of 066 is also at %Vce when the input drive
voltage is at 2V. R38 in Figure 9 was needed for current
limiting at the output pins. Since each channel has its own
drive control circuit no filtering is required, eliminating the
need for external pins. With no external pins no current limiting is necessary; thus the 1k resistor is not used in the drive
control circuit.

Pin 1 of the contrast control output is held at a constant
voltage two diode drops below YzVce. To generate this reference the base of 051 is held at exactly YzVce. R44 and
R45 form a voltage divider. With both 053 and 054 connected as diodes the voltage at the junction of R44 and R45
is YzVcc plus one diode drop. 052 is a buffer to this reference voltage, generating exactly YzVcc at its emitter. 051 is
used to drive the bases of 049 and 050 to one diode drop
below the reference voltage. 050 is used to further buffer
the reference voltage to the base of 09 (sse Figure 8) and
the corresponding transistors in the other channels. 048 is
used to bias the collector of 049 to YzVce, the same voltage as the collector of 047 when the differential pair is balanced. This keeps the characteristics of 047 and 049 well
matched. Going back to 044 and R33; these parts set up a
current source that varies the current through R36. With a
2V contrast voltage the differential pair is balanced, meaning that the voltage drop across R36 is Yz Vce. 045 buffers
the voltage at R36, driving the bases of 046 and 047. 046
further buffers the voltage, driving the bass of 08 (see Figure 8) and the corresponding transistors in the other two

fII

2-111

~

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....
an
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....
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N

,---,-----------------------------------------------------------------------------,
Circuit Description

(Continued)

--------------------------------------------------------------.
Vee
,

,

'

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RU,I
10k

R36
9.4k

R45
10k

R42
10k

TO VIDEO AMP
08 BASE

.. _-------

- ---- --- -- - - - - -- -- - - -FIGURES- --

4V

l

TO VIDEO AMP
09 BASE

----------------rlGURE 8

12 CONTRAST CONTROL INPUT

~ ~O.I}'r
TL/H/11881-17

FIGURE 9. Simplified Schematic of LM1205/LM1207 Contrast Control
p----------------------------------------------------- ---------~

I
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073

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R57
6.5k
R58
13k'

I

066

R49
5.6k

--------

R50
10k

TO VIDEO
AMP
BASE 010
rlGURE 8
R51
10k

TO VIDEO
AMP
BASE 011
rlGURE 8
R53
12.8k

R54
10k

R55
10k

-----------------------------------------------------.
TL/H/11881-18

FIGURE 10. Simplified Schematic of LM1205/LM1207 Drive Control
2·112

r-

Circuit Description

B:
....

(Continued)
capacitor with 450 p.A. In this balanced condition the charge
and discharge current are equal, thus the voltage across the
clamp capacitor remains unchanged.

CLAMP COMPARATOR CIRCUIT

Figure 11 is a simplified schematic of the clamp comparator
circuit. 085 and its input transistors, 081 and 082 are one
half of the differential pair. The base of 081 is connected to
pin 19 via R62. This is the positive input to the comparator.
088 and its input transistors, 090 and 091 are the other
half of the differential pair. The base of 092 is connected to
the junction of R19 and R20 in Figure 14 via R73. This is the
negative input to the comparator. R73 is included only to
match the input characteristics of the positive input, which
requires the 1000 resistor. The negative comparator input is
the feedback from the output stage as briefly described in
the block diagram and covered in more detail in the output
stage circuit description. 086 is ~he current source for the
differential pair. It is turned on and off by the output of the
clamp gate circuit (Figure 12).0102 of the clamp gate circuit has a current flow of about 225 p.A when it is turned on.
This current is mirrored into 086. Assume that the inputs to
the comparator are equal, making the differential pair balanced. In this condition 085 and 088 each have a current
flow of 113 p.A. Looking at the 085 side of the circuit, 084
will also have 113 p.A of current flow. 080 is set up as a
current mirror to 084, but its emitter resistor is one fourth
the emitter resistance of 084. Thus the current flow for 080
is four times the current flow thru 084, or 450 p.A. 083 has
been added to help drive the base of 080, increasing the
accuracy of the current mirror. The collector of 080 directly
charges the capacitor as a current source of 450 p.A. R65 is
added to discharge the charge stored in the bases of 080
and 084. This is necessary to quickly turn off the current
charge of the clamp capacitor as the comparator section is
turned off. 087, 089, and 090 work in exactly the same
way. However, the collector of 091 drives another current
mirror with the 450 p.A. This current flows thru 078. 077 is a
current mirror with 078, thus 450 p.A also flows thru 077.
079 has been added to help drive the base of 077, again
adding to the accuracy of the current mirror. Since 077 is on
the ground side of the circuit it discharges the clamp

Going back to the input stages, note that both inputs, 081
and 092, are driven by a 50 p.A current source. This keeps
both transistors turned on even when the differential pair,
085 and 088, is turned off. 082 and 090 are added to help
drive the bases of 085 and 088 respectively. R64 and R72
are added to help discharge the charge stored in the bases
of 085 and 088 as these two transistors are turned off.
Since the input stage remains active the differential pair is
quickly turned off. The comparator can also be more quickly
turned on with the input stages remaining active. R67 is
used to assure that the potential difference across the differential pair is minimal during turnoff. Without R67 there
could be a little extra charge or discharge of the clamp capacitor during turnoff, creating an error in the black level of
the video signal. Now assume that the input to pin 19 is
slightly higher than the reference voltage to the negative
input of the comparator. The voltage at the base of 085 is
now higher than the base of 088. This creates an increased
current flow thru 085 and an equal decrease of current flow
thru 088. This current change is multiplied by four in the
increase of current flow thru 080. Likewise the current flow
thru 077 and 091 is decreased by four times the current
change in 088. In the extreme case the current flow thru
080 can increase to 900 p.A and there would be no current
flow thru 077. 080 does charge the clamp capacitor, thus
the voltage across the capacitor will increase. The above is
all reversed when the input to 092 rises above the input
level of 081. If the base of 086, the current source to the
differential pair, is forced close to ground, then there is no
current flow thru 086 and the differential pair, 085 and 088.
With the current flow thru the differential pair set the zero,
all the current mirrors would also have no current flow. Thus
the voltage on the camp capacitor would remain constant,
the deSired result during active video.

~

UI
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r-

B:
....
N
CI
......

fII

2-113

Circuit Description

(Continued)

---------------~---~~-----~-------~--~----------~
Vee
.
•
. R63
100

R65

5Qk

50 p.A 50 p.A

R66
400

R71
100

••
...••

•

Q84

PUSH PULL
OUTPUT CURRENT
TO CLAMP CAP
FIGURE 8 '

450 p.A

Q85

QB8

R67

. C/82

25k

tURRENT SOURCE
CONTROL FROM
ClAMP GATE
FIGURE 12

225J.iA

. (-) COMPARATOR
INPUT FROM
VIDEO AMP
. FIGURE 14
R73

R6B
500

••
••
••
•

------------------~-------------~-~

+4V

!

TUH/11881-19

FIGURE 11. Simplified Schematic of LM1205/LM1207 Clamp Comparator Circuit

input for current limiting during any possible voltage surge at
pin 14. With no resistors at the emitters of 096 and 098 this
circuit will quickly switch. Below 1.4V (1.2V typical) 095 is
turned on and 097 is turned off. Above 1.4V (1.6V typical)
097 is turned on and 095 is turned off. With 097 turned on
0100 is also turned on. This pulls the current thru R79 to
ground, turning off 0102 and 0103. Remember 0102 is a
current mirror to 086 in the clamp comparator. With 0102
turned off, the clamp comparator is also turned off. When
the input signal goes below 1.2V, 097 and 0100 will be
turned off. This allows 0102 to turn on, turning on the clamp

CLAMP GATE CIRCUIT

Figure 12 is a simplified schematic of the Clamp Gate circuit. A voltage reference is setup by Z3 and by 0104 and
0105 connected as diodes, generating a 7V base drive to
094, 099 and 010.1. 094 is used to bias the input stage.
This stage is deSigned to accept TTL levels at pin 14. 095
and 097 form a differential pair. The base of 097 is set to
2.1V by 099 driving the voltage divider formed by R77 and
R78. In a balanced condition the base of 095 is also at
2.1 V. 096 is connected as a diode and the current flow thru
it is mirrored into 098. Also the input to pin 14 would be one
diode drop below 2.1 V, or around 1.4V. R74 is added to the

2-114

r-----------------------------------------------------------------------------'r
....s::::
Circuit Description (Continued)
comparators of the three video channels. 0103 is added to
help drive the base of 086 in the clamp comparator, increasing the accuracy of the current mirror. 0101 drives
R79 and R80. This sets the current thru 0102, thus setting
the current thru 086 of the clamp comparator.

drive the cathode driver stage well above the black level,
cutting off the beam current in the CRT. This prevents the
bright spot from occurring when the monitor is turned off,
preserving the phosphor of the CRT. The CRT will also have
its beam current cut off during the time the monitor is first
turned on. This is not a critical period for the CRT since the
filaments have not warmed up to generate a current flow.
The comparator along with R89, R90, and 0115 all form the
spot killer circuit. 0115 acts the same as 0106. When 0115
has a high signal at its base it is turned off and the outputs
of the LM1205/LM1207 are in the normal operating mode.
A low signal at the base of 0115 turns on this transistor,
blanking the outputs of the LM1205/LM1207. 0115 is driven by the output of the comparator. The inverting input of
the comparator is connected to an internal 1.2V reference.
The non-inverting side is connected to a resistor divider network, R89 and R90. When Vee is above 10.6V the non-inverting input is above the 1.2V reference, therefore the output of the comparator is high. This high output turns off
0115. Once the Vee drops below 10.6V the comparator's
output goes low, turning on 0115 which forces the outputs
into the blanking mode.

BLANK GATE CIRCUIT
Figure 13 is a simplified schematic of the Blank Gate circuit.
With the exception of the simple output stage and the spot
killer circuit, this circuit is almost identical to the clamp gate
circuit. The only difference is that the output stage is driven
from the opposite side of the differential pair. Thus 0111 is
connected as a diode instead of 0109. With the input at pin
13 at a low level 0108 is turned on, also turning on 029, the
output transistor. 029 is part of the blanking circuit in the
output stage shown in Figure 14. When 029 is turned on the
output is clamped to a blanking level that is "blacker than
black", allowing blanking to be done on the cathodes of the
CRT.
The spot killer circuit is used to force the outputs of the
LM1205/LM1207 into blanking when the Vee drops below
10.6V. Forcing the outputs to a blacker-than-black level will

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....

II.)
C)
~

Vee

CURRENT SOURCE CONTROL
TO CLAMP COMPARATOR
FIGURE 1.1
R81
SOk

fII

CLAMP GATE' INPUT
TL/H/11881-20

FIGURE 12. Simplified Schematic of LM1205/LM1207 Clamp Gate Circuit

2-115

Circuit Description (Continued)

r-----------------------------------------Vee

R88

25k

R89

9.4k'

Ql07

Ql12

7V

TO VIDEO AMP

t----t----+--... OUTPUT STAGE
FIGURE 14
R87

10.5k

BLANK GATE INPUT
TUH/11881-21

FIGURE 13. Simplified SChematic of LM1205/LM1207 Blank Gate Circuit
VIDEO AMPLIFIER OUTPUT STAGE WITH BLANK
CIRCUIT

emitter-followers these transistors also give current gain to
the signal. 033 comes close to also giving a diode drop to
the Signal, the voltage drop across R27 being insignificant.
R27 has been added to give some isolation between 033
and the internal circuits of the lM1205/lM1207, adding to
the stability of the device. 033 also has R29 in its emitter for
isolation from capacitive loads and current limiting from any
possible voltage surges. R28 is at the collector of 033 is
also for current limiting from voltage surges and minimizing
crosstalk between the three channels through the Vee line.
To match the loading of the feedback section the output at
pin 20 should have a load of 390!t To minimize power consumption the feedback section uses resistor values 10
times larger than those at pin 20. The current source at the
emitter of 033 provides for the capability to set the black
level as low as 0.5V.
The video Signal does go thru a number of diode drops at
the output stage. One may be concerned that the tracking
over temperature could be a problem. The feedback section
has been designed to temperature track the output stage.
The feedback for DC restoration eliminates the temperature
coefficients of the diode junctions. The remaining section to
be covered is the blanking section. This section comprises
of 025 thru 029. 026 thru 028 are connected as diodes.
025 provides current gain to this stage to adequately pull
down the base of 030 during blanking and also adding another diode potential. During blanking the base of 030 will
be four diode drops above ground, plus the saturation volt-

Figure 14 is a simplified schematic of the Video Amplifier
Output Stage including the blanking circuit. 018 serves as a
buffer between the DC restoration stage shown in Figure 8
and the output stage. A current source is used to fix the
current flow thru 018 keeping it well within its operating
range. The emitter of 018 drives the bases of 019 and 024
with the current thru 024 being twice that of 019. 019,
along with 020 thru 023 duplicate the actual output stage
going to pin 20. 019 inverts the video signal (note that the
video signal was inverted at 07 in Figure 8). With two internal inversions of the video signal in the lM1205/lM1207,
the output is non-inverted. The collector of 019 gives a gain
of -10 to the video signal and drives the base of 020. 021
through 023 are all connected as diodes with the emitter of
023 driving R19 and R20. The junction of R19 and R20 is
connected to the base of 092 via R73 (shown in Figure 11),
this being the feedback to the negative input of the clamp
comparator. This stage is independent of the actual output
stage at pin 20, but is where the feedback is done for DC
restoration. Therefore it is possible to blank the actual output stage below the black level without affecting the DC
restoration feedback loop. 024 is the equivalent part of 019
in the actual output stage. It also inverts the video signal
with a gain of -10 and drives the base of 030. 030 thru
032 each give a diode drop to the level of the video Signal,
similar to being connected as diodes. Being connected as

2-116

Circuit Description

Figure 15 is almost identical to the schematic shown in Figure 4. The only difference between the two schematics is
that in Figure 15 each channel has individual adjustments
for both drive and cutoff, making this circuit a good design
for monitor applications. Each CRT will have a slightly different cutoff voltage for each color, making it necessary to
provide separate adjustments in order to accurately set the
cutoff for each color. The gain of each color of the CRT is
also slightly different; if the color temperature of the display
is to be accurately set then each channel of the LM1205/
LM1207 must have individual gain adjustments. Thus each
channel has its own drive control. Once the drive control is
set, the gain between the three color channels will closely
track as the contrast is adjusted. All the jumpers needed to
design a single sided PC board are shown in the schematic.
The resistors and jumpers with no reference designation are
the connections between the PC board and the connectors
mounted on the PC board. CNl thru CNS are BNC connectors.

(Continued)

age of 029. There are also four diode drops from the base
of 030 to the output, pin 20. Therefore during blanking pin
20 will be less than 100 mV above ground, enabling the
designer to blank at the cathode of the CRT. R23 is added
to quickly turn off 025 by discharging its base when the
blanking signal is removed.
Figure 14 also shows the power and ground pins to the
LM1205/LM1207. All the VCC1 pins (pins 3,11,25) are all
internally connected together. A 0.1 ,.F bypass capacitor
must be located close to each pin and connected to ground.
Further bypassing is done by a 100 ,.F capacitor. This capacitor needs to be located on the board close to the
LM1205/LM1207. Pins 22 and 23 are the VCC2 pins. A
10 ,.F and a 0.1 ,.F bypass capacitors must be located
close to pins 22 and 23. Correct bypassing of pins 22 and
23 is very Important. If the bypassing is not adequate then
the outputs of the LM1205/LM1207 wiil have ringing, or
even worse they may oscillate. The ground side of the bypass capacitors at pins 22 and 23 must be returned to a
ground plane with no interruptions from other traces between these capacitors and the ground pins 21 and 24 of
the LM1205/LM1207.

A 30n resistor is in series with each of the video inputs. A
voltage surge may occur at these inputs when either the
inputs are first connected to another system, or when the
system is powered up before the monitor is turned on. If this
voltage surge exceeds the supply voltage (at ground potential if the monitor is not powered up) of the LM1205/
LM1207, or goes below ground, current will flow through the
parasitic devices of the LM1205/LM1207. This current is
limited by the 30n resistors, preventing a potential catastrophic failure. A loon resistor is added to the Blank Gate

Applications of the LM 12051
LM1207
Figure 15 is the schematic of the demonstration board designed at National. Figure 16 is the actual layout of the demonstration board. Note that the schematic shown in
Vee 1

Vee 2

11)-+--.......

R17
4k

R21
2k

2sH--.......
Q25

26
2.4k

(TO 50n
TERMINATION)

II

FROM BLANK
GATE
FIGURE 13

.....- - - - - + - ( 2 4

R22
200

7~----~~-4------~--~--~----~---'----~--------~~21

~------------------------------------------

TUH/11881-22

FIGURE 14. Simplified Schematic of LM1205/LM1207 Video Amplifier Output Stage with Blank Circuit

2-117

~ r---------------------------------------------------------------------------------~

....~

:i.....

II)

~
....

:s

Applic~tions

of ~he LM'1,205/LIYI 1.207 (Continued)

and Clamp Gate il)puts. These, two resistors also limit the
current during a voltage surge. A larger resistor is, requirfild
b.ecau~ these inputs are DCcoupled,allowing ttle currerit
to continuously fl,ow into these inputs before the monitor is
turned on. 1000 resistors ,are not recolT\mendeC\ at the video inputs because this resistance value will start to roll off
the .frequency response of the LM1205/LM1207.
Not~ that the layout,shown in Figure 16 does have· a very
extensive ground plane. One must remember that the
LM1205lLM1207 is a 130 MHz/85 MHz part and a single
sided board is difficult to successfully design. A grqund
plane similar to the layout shown in Figure 16 must be provided for good performance of the LM1205/LM120Z when
using either a Single sided or double sided board. The layout
of this board demonstrates the importance of grounding.
The results of this layout are shown in Figures 178 through
17d. In these photographs the LM1205 rise time was 2.25
ns and its fall time was 3.00 ns. For the LM1207, the rise
time was 4.1'0 ns and the fall time 3.85 ns. The output was a
4 Vpp ,signal and the cutoff voltage was set to 2V. The

CN1~

overshoot will subsequently be filtered out by the loading
effects of the CRT driver stage and the CRT itself. When the
LM1205/LM1207 is designed into a video board one must
keep the ground to the CRT. driver stage separate from the
ground of the LM1205/LM1207, connecting the two
grounds together only at one point National Semiconductor
also manufactures a line of CRT drivers. Please contact National for additional information. These drivers greatly simplify the driver, design allowing for shorter design cycles. Of
cou~e the LM1205/LM1207 can also be designed with Ii
discrete driver stage. Figure 18 shows a design using a simpie cascode CRT driver. The LM1205/LM1207 block would
be the same schematic as shown in Figure 15.
REFERENCES

Zahid'Rahim, "Guide to CRT Video Design," Application
Note 861, National Semiconductor Corp., Jan. 1993
Ott, Henry W. Noise Reduction Techniques in Electronic
Systems, John Wiley & Sons, ,New York, 1976

1Rll
7S

son

SCOPE

CN2~

1R12
7S

son

SCOPE

CN3~
1m
7S

,,).

son

SCOPE

BLANK GATE
CNS

CN4

CLAMP GATE

FIGURE 15. Demons~ration Board Schematic

2-118

TL/H/11881-23

---------------------------------------------------------------------------, r
!!:
....
. Applications of the LM 1205/LM 1207 (Continued)
N
o

CII
.....
r

....

!!:

~
.....

FIGURE 16. Demonstration Board Layout

fII

2·119

~ r-------------------------------~-------------------------------------------------

....~
~

Applications of the LM1205/LM1207 (Continued)

~

~

:i
....

i"UH/11881-25

FIGURE 17a. LM1205 Rise Time

FIGURE 17b. LM1205 Fall Time

TL/H/11881-28

TUH/11881-27

FIGURE 17d. LM1207 Fall Time

FIGURE 17c. LM1207 Rise Time
TO HV
SUPPLY

4V

t---.-+

TO LV

SUPPLY

271---.......
26~--e---------~

390

LM1205/
LM1207
TL/H/11881-29

FIGURE 18. LM120S/LM1207 Typical Application

2-120

t!lNational Semiconductor

LM 1208/LM 1209
130 MHz/100 MHz RGB Video Amplifier System
with Blanking
General Description
The LM1208/LM1209 is a very high frequency video amplifier system intended for use in high resolution RGB monitor
applications. In addition to the three matched video amplifiers, the LM1208/LM1209 contains three gated single ended input black level clamp comparators for brightness control, three matched DC controlled atlenuators for contrast
control, and three DC controlled drive attenuators providing
independent full range gain control in each channel for wide
range white balance. All DC control inputs offer high input
impedance and an operation range from OV to 4V for easy
interface to bus controlled alignment systems. The
LM1208/LM1209 also contains a blanking circuit which
clamps the video output voltage during blanking to within
0.1 V above ground. This feature provides blanking capability at the cathodes of the CRT. A spot killer is provided for
CRT phosphor protection during power-down.

Features
• Three wideband video amplifiers 130 MHz
(4 Vpp output)

@

-3 dB

• Matched (± 0.1 dB or 1.2%) atlenuators for contrast
control
• Three externally gated single ended input comparators
for cutoff and brightness control
• OV to 4V, high input impedance DC contrast control
(>40 dB range)
• OV to 4V, high input impedance DC full range gain control (Drive) for each video channel (>40 dB range)
• Spot killer, blanks outputs when Vee < 10.6V
• Capable of 7 Vpp output swing (slight reduction in
bandwidth)
• Output stage blanking
• Output stage directly drives most hybrid or discrete
CRT drivers

Applications
•
•
•
•

High resolution RGB CRT monitors
Video AGC amplifiers
Wideband amplifiers with gain and DC offset controls
Interface amplifiers for LCD or CCD systems

Block and Connection Diagram

TL/H/llB84-1

FIGURE 1
Order Number LM1208N or LM1209N
See NS Package Number N28B
2-121

Absolute Maximum Ratings (Note 1)

Operating Ratings (Note 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Temperature Range
Supply Voltage {Vee>

Supply Voltage {Vee>
Pins 3, 11, 22, 23, 25 (Note 3)
15V
I":
Peak Video Output SourcE! Current
"
(Any One Amp) Pins 17, 20 or 26
28mA
Voltage at Any Input Pin (VIN)
Vcc ~ VIN ~ GND
Power Dissipation (Po) ,
2.5W
(Above 25'C Derate Based on (JJA and TJ)
50'C/W
Thermal Resistance «(JJA)
150'C
Junction Temperature (TJ)
ESD Susceptibility (Note 4)
2kV
Pins12,13,and 14
1.9kV
' - 65'C to 150'C
Storage Temperature
Lead Temperature (Soldering, 10 sec.),
265'C

-2O"c to 80'C
10.8V

.

,

!
;,

'

,

= 25'C; VCCl = Vee2 = 12V. V12 =

"

Ccin~ltlons

Parameter

,

..

Is

Supply Current

V4,6,9

Video Amplifier Input Sias Voltage

~

VCCl

"

13.2V

"

DC Electrical Characteristics See DC Test Circuit (Figure 2), TA
V14 = OV; Vcut-off = 1.0V; V13 =4V; Vdrive = 4\1 unless otherwise stated.
Symbol

s: VCC s:

+ VCC2, RL =

00

'.

(Note 7)

Typ!cal
(Note 5)

Limit
(Note 6)

so

105

2.8

"

4V;

Units

mA(max)
V

RIN

Video Input Resistance

Any One Amplifier

20

V141

Clamp Gate Low Input Voltage

Clamp Comparators On

1.2

0.8

V14h

Clamp Gate High Input Voltage

Clamp Comparators Off

1.6

2.0

.V(min)

1141

Clamp Gate Low Input Current

V14 = OV

-1

-5

,.,.A(max)

114h

Clamp Gate High Input Current

V14 = 12V

0,01

1.0

,.,.A(max)

Iclamp

Clamp Cap Charge Current

Clamp Comparators On

±750

±500

,.,.A(min)

Ibias

Clamp Cap Bias Discharge Current

Clamp Comparators Off

500

V131

Blank Gate Low Input Voltage ,

Blank Gate On

1.2

0.8

V (max)

V13h

Blank Gate High Input Voltage

Blank Gate Off

1.6

2.0

V (min)

...

. V13 = OV

kO
V (max)

nA

-8.5

-11.0

,.,.A(max)

V13 = 12V

O.ot

1.0

,.,.A (max)

Video Output Low Voltage

,VCill-off = OV

0.15

0.5

V (max)

VOH

Video Output High'Voltage

Vcut.off = '9V

7.5

7

V (min)

VO(lV)

Video Black Level Output Voltage

'Vcut-off = .1V

1.0

.1VO(1V)

Video .1 Black Level Output Voltage

Between Any Two Amplifie~,
Vout-off = 1V

Vodblanked)

Video Output Blanked Voltage

V13 = OV

112,15,18 or 28

Contrast/Drive Control Input CurrenI'

116,19and27

Cut-Off Control Input Current (Alllnp,uts)

Vout-off = OV to 4V

-500

VSPOT

Spot Killer Voltage

Vee Adjusted to ~ctivate

10.4

1131

Blank Gate Low Input Current

113h

Blank Gate High Input Current

VOL

. Vcontrast = VdriVe == OV.t04V

"

.,
.:',':

,.

"

2-122

V (Note 8)
mV(max)

±100
35

70

-250

mV(max)
nA
nA

10.8

V (max)

AC Electrical Characteristics

See AC Test Circuit (Figure 3), T A = 25·C; Vee1 = VCC2 = 12V. Manually
adjust Video Output pins 17, 20, and 26 to 4V DC for the AC test unless Cltherwise stated. (NC?te 14).
Symbol
AVmax

Conditions

Parameter
Video Amplifier Gain

V12 = 4V, VIN

=

635 mVpp

Vdrive = 4V
liAV2V

Contrast Attenuation @ 2V

Ref: Av max, V12 = 2V

liAvo.25V

Contrast Attenuation @ 0.2SV

Ref: Av max, V12 = 0.2SV

liDrive2V

Drive Attenuation @2V

Ref: Av max, V drive

=
=

2V

Typical

Limit

(Note 5)

(Note 6)

Units

7.0

6.0

V/V(min)

16.9

lS.6

dB (min)

-6

dB

-40

dB

-6

dB

-40

dB

liDriveO.25V

Drive Attenuation @0.2SV

Ref: Av max, Vdrive

AVmatch

Absolute Gain Match @ Av max

V12 = 4V, Vdrive = 4V (Note 9)

±0.3

dB

AVtrack1

Gain Change Between Amplifiers

V12 = 4V to 2V (Notes 9, 10)

±0.1

dB

THD

Video Amplifier Distortion

Vo = 1 Vpp,f = 10kHz

1

%

f(-3dB)

Video Amplifier Bandwidth

V12 = 4V, Vdrive

(Notes 11,12)

Vo

Video Output Rise Time (Note 11)

Vo = 4Vpp

tr(Video)

t,(Video)

Video Output Fall Time (Note 11)

=

=

0.2SV

4V,

4Vpp

Vo = 4Vpp

LM120B

130

LM1209

100

LM120B

2.B

LM1209

3.2

LM120B

3.4

LM1209

3.6

MHz

ns

ns

Vsep 10 kHz

Video Amplifier 10 kHz Isolation

V12 = 4V (Note 13)

-70

dB

Vsep 10 MHz

Video Amplifier 10 MHz Isolation

V12 = 4V (Notes 11, 13)

-SO

dB

tr(Blank)

Blank Output Rise Time (Note 11)

Blank Output = 1 Vpp

7

ns

t,(Blank)

Blank Output Fall Time (Note 11)

Blank Output

7

ns

tpw(Clamp)

Min. Back Porch Clamp Pulse Width

200

ns

=

1 Vpp

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate condHions for which the device is functional, but do not guaranlee specijic psrformance limits. For guaranteed spscijications
and test conditions, see the Electrical Characteristics. The guaranteed specification. apply only for tho test conditions listed. Some performance characteristics
may degrade whon the device is nol opsrated under the listed test conditions.
Note 3: Vee supply pins 3, II, 22, 23, 25 must be externally winsd together to prevent internal damage during Vee power on/off cycles.
Nole 4: Human body model, 100 pF discharged through a 1.5 kll resistor.
Note 5: Typical specijications are spscijied al + 25"'C and represent the most likely psremetric norm.
Note 6: Tested IimHs are guaranteed to National's AQQL (Average OutgOing QualHy Level).
Note 7: The supply current specified is the quiescent current for Vee1 and VCC2 wHh RL = 00, see F/guffl 2:' test circuit. The supply currentlor VCC2 (pin 23) also
depsnds on tho output load. WHh video output at 1V DC, the additional current through VCC2 is 8 mA for FI{}IJf6 2'. test circuH.
Note 8: Output voltage is depsndent on load resistor. Test circuH uses RL .;, 3901l.
Note 9: Measure gain difference between any two amplifiers. VIN

= 635 mVpp.

Note 10: I!.Av track is a measure of the ability of any two amplijiers to track each other and quantijies the matching of the three attenuaters. It is the difference in
gain change between any two amplifiers wHh the contrast voHage (V12) at either 4V or 2V measured relative to an Av max condHion, V12 = 4V. For example, at Av
max the three amplijiers' gains might be 17.1 dB, t6.9 dB and t6.8 dB and change \0 11.2 dB, 10.9 dB, and 10.7 dB respsctlvely for V12 = 2V. This yields the
measured typical ± 0.1 dB channel tracking.
Nole 11: When measuring video amplifier bandwidth or pulse rise and fall times, a double si(jed full ground plane printed circuit board without socket is
reccmmended. Video amplifier 10 MHz isolation test also requires this printed circuH board. The reason for a double sided full ground plane PCB is that large
measurement variations occur in single sided PCBs.
Note 12: Adjust input frequency from 10 MHz (Av max reference level) to the -3 dB corner frequency (f-3 del.
Nota 13: Measure output levels of the other two undriven amplijiers relative to the driven amplHler to determine channel separation. Terminate the undriven
amplHier inputs to simulate generator loading. Rapeat test at 'IN = 10 MHz for Veep 10 MHzNote 14: During the AC tests the 4V DC level is the center vOHage of the AC output signal. For example, if the output is 4 Vpp the signal will swing between 2V DC
and 6V DC.

2-123

en

~

~
!'j

r---------------------------------------------------------------------------------Typical Performance Characteristics (vcc =

12V, TA= 25°C unless otherwise specified)

-

Attenuation vs Contrast.Voltage
i,..;" I-"

-10

/

'CD' -20

",

is

-60
-70

is

OOT
4 Vpp @ 0 dB DRIVE
4V

-40

!;;; -50

/

OUT = 4 Vpp @ 0 dB CONTRAST = 4V

-30

a I
I
5
~

-40

-50

1

o

f-" ~

",

~

=
=

-30

a... I
I
~

",

-10

'

~

-40

-80

r~

""-

,:::::?""

""""

'BLUE

0=::::

-60
-70

A

RED

'"

~

V/
V

100

10
FREQUENCY (MHz)

TUH/II884-4

LM1208 Contrast vs Frequency
VI2

'

-30

~

02

-40

"z:
=<

-50

0

'"

".

- 0.63V

= 0.36V
= 0.23V

1\""~
~Ib

- 0.14V

Your = 4Vpp (REFL
CONTRAST 4V

-60

=

-70

10

100

FREQUENCY (MHz)
TL/H/II884-6

2·124

Typical Performance Characteristics (vcc =

12V, TA = 25D C unless otherwise specified) (Continued)

LM1209 Crosstalk vs Frequency
GREEN (MAX CONTRAST

a:

DRIVE)

-10


...z

S

-20
BLUE

-30
-40
-50
-60
-70
-80

./

.... .-..-

~

-

....:: :=~~

/

-"
/

/

III

'\.

"-v

IV

RED

10

100

FREQUENCY (MHz)

TlIH/11884-25

LM1209 Contrast vs Frequency

= 4.OV
= 1.41Y

V12

.,

-10

.3

-20

~

gz

-30

<.>

-50

In

0

'z
:;;:
<>

-40

r--.....

r--.... 1""-

- 0.62V

= 0.37V

-

= 0.27V

= 0.22V

-60

"'\.\.

I?""'" ~A
V

f-"

-70

10

VOUT
DRIVE

= 4 Vpp
= 4V

(REF)

1

100

FREQUENCY (MHz)

TlIH/11884-26

LM1209 Drive vs Frequency

,
--..

VORIVE - 4.OV
-10
-20

~

-30

iil

-40

...>

'"
':z

-50

<>

-60

:;;:

= 1.37V
= 0.54V
= 0.28V
= 0.15V

r--..

-....

'\ \.
~

= O.OOV

~

7'

=

VOUT
4 Vpp (REF)
CONTRAST
4V

-70

10
FREQUENCY (MHz)

2-125

=

I

100
TL/H/11884-27

Applications ,Information
Vee (+12V)
100 }Of

RED
DRIVE

30

LM1208N/
LM 1.209N
TOP VIEW

RED
CUT-Off

RED
VIDEO
IN

GREEN
CUT-Off
4V

GREEN
DRIVE

CONTRAST

1-----+----' ~~I~i

TL/H/I1884-7

FIGURE 2. LM1208N/LM1209N DC Test Circuit

Applications Information

(Continued)
Vee (+12V)

IOOI'F

REO

LM1208N/
LM1209N
30

DRIVE

TOP VIEW

RED
VIDEO
IN

GREEN
VIDEO
IN

Vee (+12V)
DC OUTPUT
ADJUST

I
10k

BLUE
VIDEO
IN

GREEN
DRIVE

4V

CONTRAST

BLUE
DRIVE

TLlH/118B4-8

FIGURE 3. LM1208N/LM1209N AC Test Circuit

2·127

Applications Information (Continued)
Vee (+12V)

100}'F'

+

RED
DRIVE
O.ll'r

LM1208N/
LM1209N
30

TOP VIEW

RED
CUT-orr

RED
VIDEO

OUT'

RED
VIDEO
IN

BLUE
VIDEO
IN

V2D

GREEN
VIDEO

OUT'

430

GREEN
CUT-orr

GREEN
DRIVE

V17

430

BLUE
VIDEO

OUT'

BLUE
CUT-orr

• 50n TERMINATION TO
BE USED AT OUTPUTS

TLlH/11B84-9

FIGURE 4. LM1208N/LM1209N PCB Test Circuit

2-128

Applications Information

termination resistor depends on the impedance of the coax
cable being used, 750. being the most common impedance
used in video applications. The video signal is AC coupled
through a 10 ,..F capacitor to the input, pin 6. There is no
standard for the DC level of a video Signal, therefore the
signal must be AC coupled to the LM120S/LM1209. Internal
to the LM120S/LM1209 is a 2.SV reference, giving the input
video an offset voltage of 2.SV. This voltage was selected to
give the input video enough DC offset to guarantee that the
lowest voltage of the video signal at pin 6 is far enough
above ground to keep the LM120S/LM1209 in the active
region. The 2000. resistor at the input is for ESD protection
and for current limiting during any voltage surge that may
occur at the input, driving pin 6 above Vee. The input video
signal is buffered by - A 1. In this circuit description an inverting amplifier is shown with a "-" (minus sign) in front of
the amplifier designation. The output of - A 1 goes to the
contrast and drive attenuator sections.
The contrast and drive control sections are virtually identical. Both sections take a OV to 4V input voltage, 4V giving
the maximum gain for either the contrast or the drive. This is
a high impedance input, allowing for an easy interface to 5V
DACs. One may also use 100k potentiometers with no degradation in performance. The contrast control section is
common to all three channels. It converts the input voltage
at pin 12 to a couple of internal DC voltages that control the
gain of the contrast attenuator. Referring to the Attenuation
vs Contrast Voltage under typical performance characteristics note that a 4 V control voltage results in no attenuation
of the video signal. A 0.25V control voltage results in an
attenuation of 40 dB. Again note that these internal control
voltages are common to all three channels. To minimize
crosstalk, these voltages go to pins 1 and 2. Minimizing
crosstalk is done by adding the RC network shown in the
block diagram (Figure 6).

(Continued)

Figure 5 shows the block diagram of a typical analog RGB
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of
other applications that benefit from the use of color display
terminals. The RGB color monitor characteristics may differ
in such ways as sweep rates, screen size, CRT color trio
spacing (dot pitch), or in video amplifier bandwidths but will
still be generally configured as shown in Figure 5. Separate
horizontal and vertical sync signals may be required or they
may be contained in the green video input signal. The video
input signals are usually supplied by coax cable which is
terminated into 750. at the monitor input and internally AC
coupled to the video amplifiers. These input signals are approximately 1V peak to peak in amplitude and at the input of
the high voltage video section, approximately 5V peak to
peak. At the cathode of the CRT the video signals can be as
high as 60V peak to peak. One important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range. The
Figure 5 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function of the
LM120S/LM1209 which contains the three matched video
amplifiers, contrast control and brightness control. The
LM120S/LM~209 also provides the capability to blank atthe
cathode of the CRT.

Functional Description
Figure 6 is a detailed block diagram of the green channel of
the LM120S/LM1209 along with the recommended external
components. The IC pin numbers are circled and all external
components are shown outside the dashed line. The other
two video channels are identical to the green channel, only
the numbers to the pins unique to each channel are different. The input video is normally terminated into 750.. The

vo---1t--t

SYNC IN
H 0---11--1

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS

VIDEO IN

Ro---H-I
Go---.....-I

VIDEO AMPLIFICATION
WITH GAIN / DC
CONTROL

CONTRAST

HV
CRT
VIDEO

1-----..

BRIGHTNESS

FIGURE 5. Typical RGB Color Monitor Block Diagram

2-129

TL/H/11884-10

~ r-------------------------------------------------------------------~

~
.....
::E
...I

.......

~
.....

::E
...I

Functional De,cription (Continued)
The OV to 4V drive control signal comes .in on pin 1S. Each
channel has its own drive section, therefore the crosstalk
compensation needed for the contrast control voltages is
not require~ for the drive control, thus no external pins for
the. drive control. The drive attenuator features a full range
g~in c~ntrol over 40 dB. rhilil gives no :attenuation of the
video signal with a 4V control. voltage. A 0.25V control voltage results in an .attenuation of 40 dB.

,.',

age divider formed by the 500n and 4k resistors . .,..A4,will
be close to the same output as - A3 and willtemperalure
track'due to the .similar design of the two output stages.
However, the current at the output of ,~A4 will be ten times
the current at ,the output of - A3. To balance both outputs, a
load.resistance of 390ft needs to be connected from"pin 20,
the green video output pin, to ground. Another input to "" A4
is the., blank pulse. When .a negative ,going blank pulse is
applied to pin'13, the output of the LM120S/LM1209 is driven to less than ,0.1 V above ground. USing the timing shown
in F/{Jure 7 for the blank pulse, the output of the LM120S1
LM1209 will be less than O.W during the inactive portion of
the video signal., This is a "blacker than black", condition,
blanking the CRT at the cathodes. By using the blank function of theLM120S/LM1209 no grid blanking is necessary.
Note that the DC restoration is done by feeding back. the
video Signal from -A3, but blanking is done at -A4. By
using the two output stages, blanking' can be done'at the
CRT cathodes, and at the same time activate the DC restoration loop.

The output of the drive attenuator stage goes to A2," the
amplifier in the DC restoration section. The video signal
goes to the non-inverting input of A2. The inverting side of
A2 goes to the output of gml, the clamp comparator, and
the clamp capacitor at pin S.
During the back porch period of the video signal a negative
going clamp pulse from pil114 is applied'to the clamp comparator, turning on the comparator. This period is where the
black level of the video signal at the output of the LM 120S1
LM1209 is compared to the desired black level which is set
at pin 19. Figure 7 shows the timing of the clamp pulse
relative to the video signal. The clamp capacitor is charged
or discharged by gml, generating the correction voltage
needed at the inverting input of A2 to set the video output to
the correct DC level. Removing the clamp pulse turns off
gml with the correction voltage being maintained by the
clamp capacitor during active video. Both the clamp pulse
and the blank pulse at pin 13 are TIL voltage levels.
There areaclually two output sections, - A3 and - A4. Botti
~ctions have been designed to be identical, except -A4
has more current drive capability. The output transistor
shown is part of - A4, but has been shown separately so
the user knows the configuration of the output stage. - A3
does' not go to the outside world, it is used for feeding back
the video signal for DC restoration: Its output goes directly
to the inverting input of the clamp comparator via the volt-

VCC1 goes to pins 3, 11 and 25 (see Figure 1). These three
pins are all internally connected. For proper operation of the
LM1201i/LM1209 it is necessary to connect all the VCC1'
pins to the input power to the PCB and bypass each pin with
a 0.1 ".F capacitor. VCC2 is the input power at pins 22 and
23 for the three output stages. This is a separate power
input from VCC1, there are no internal,connections between
the two different power inputs. There must be a connection
on the PCB between VCC1 and VCC2. ,Pins 22 and 23 must
be bypassed by a parallel connection of a 10 ".F and 0.1 ".F
capacitors. The ground connections for the LM120QI
LM1209 are at pins 7,21, and 24. All three ground pins are
internally connected, and these pins must also be connected externally to a goqd ground plane for proPer operation of
the LM120S/LM1209.

2-130

Functional Description

(Continued)

r-----------

-----------------~

I

GRE~: VI~~:

*75

!
*

4V

OTHER TWO
CHANNELS

lOOk

4Vl
lOOk

GREEN
VIDEO

OUT

+4V

J-t-o.-,-~·'! ,..,
:~

CHANNELS
I
~ O. I ~F ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ :- _________ ~

TLlH/11884-11

FIGURE 6. Block Diagram of LM1208/LM1209 Video Amplifier
W

input is applied to pin 6 via a 10 p.F coupling capacitor and a
300. resistor. The resistor is added to limit the current
through the input pin should an applied voltage surge rise
above Vee or drop below ground. The performance of the
LM120S/LM1209 is not degraded by the 300. resistor. However, if EMI is a concern this resistor can be increased to
well over 1000. where the rise and fall times will start to
become longer. DC bias to the input pin is provided by 05
and its associated input circuitry. Z1 is a 5.6V zener that
generates the input bias voltage. 01 is a buffer to the zener
reference voltage with 5.0V generated at its emitter. 03 and
04 are connected as diodes. 02 is close to being a diode in
this circuit. This configuration will give about 2.0V at the
collector of 02. R2 and R3 are a voltage divider, setting the
base of 05 to about 3.5V. This sets the emitter of 05 to
about 2.SV, the bias voltage of the video input. This bias
voltage is necessary to assure that the entire video Signal
stays within the active operating region of the LM120S/
LM1209. The bias voltage goes through R6, a 20k resistor,
to the video input at pin 6. R4 and R6 are of the same value
and R4 is used to compensate for beta variations of the

VIDEO

,

1J ',

,..;..,_ _ _~...
I

CLAt.lP
PULSE

,

,
I

I

I

Uri,,---.,...""I,U," TTL LEVELS
,

BLANK
PULSE

,

TTL LEVELS
TL/H/11884-12

FIGURE 7. Timing Diagram

Circuit Description
VIDEO AMPLIFIER INPUT STAGE

Figure 8 is a simplified schematic of one of the three video
amplifiers input stage along with the recommended external
components. The IC pin numbers are Circled and all external
components are shown outside the dashed line. The video

2-131

en
o

r---------------------------------------------------------------------------------~

N

,...

Circuit Description (Continued)

::::E

transistors. Note that the bias voltage passes through three
diode drops (05, 06, and 07) before setting the voltage .
across R9. 02, 03, and 04 also provide three diode drops
to the bias voltage at the base of 05, temperature compensating for the diode drops of 05,,06, and 07. This insures
that the bias voltage across R9 remains very constant over
temperature, providing an accurate bias current for the differential transistor pair 08 and 09, thus assuring proper operation of the contrast control.
06 serves as a buffer to the input video signal. Its emitter
drives the base of 07. Thus the video signal modulates the
current flowing through R9, which in turn modulates the currents through the differential pair formed by 08 and 09. The
current flow through 08 and 09 is controlled by a DC voltage from the Contrast Control circuit. This DC voltage is
common to all three channels. Increasing the voltage to the
base of 09 with respect to the base of 08 increases the
current flow through 09. A higher current flow through 09
increases the video gain (contrast) of the LM1208/LM1209.
010 and 011 also form a differential pair at the collector of
09. The operation of this differential pair is similar to 08 and
09. The DC control voltage is from the Drive Control cir-

...I

......

~
,...

:E
...I

cuits. Each channel has its own drive control circuit. Increasing the voltage to the base of 011 increases the video
gain (drive) of the LM1208/LM1209. At a 4V control voltage
the gain of the I,.M1208/LM1209 is at maximum, with all the
currant flowing through 011. If all the current was flowing
through 010, the video signal attenuation would be over
40 dB, the maximum attenuation. 012 through 017 are part
of the final section shown in Figure 8. DC restoration is done
at this stage. The clamp comparator (Figure 11) drives the
clamp cap at pin 8 to a voltage that sets the correct black
level of the video Signal. This cap is also connected to the
base of 017. 017 and 016 are one half of the darlington
differential pair. The clamp cap voltage establishes the current flow through R16, 015, and R15. With the bases of
014 and 015 held to the same voltage the current through
015 is mirrored into 014 and the other half of the differential pair, 012 and 013. By this current mirror the voltage at
the collector of 014 is set to the correct DC value for the
video signal by controlling the voltage drop across R13,
completing the DC restoration.

p-----------------------------------------------~-vee
PUSH PUll CURRENT
FRO" CLAt.lP
COMPARATOR
rlGURE 11

R2
1.5k

R3
1.5k

R16

3000
TO VIDEO AMP
OUTPUT STAGE
fiGURE 14

R5
2.9k

~------------

------------------------------------TL/H/II884-13

FIGURE S. Simplified Schematic of LM 120S/LM 1209 Video Amplifier Input Stage

2-132

Circuit Description (Continued)
channels. In the balanced condition the voltage at pin 2 will
also be two diode drops below 'IoVcc, giving a well balanced drive to the differential pair consisting of Q8 and Q9
in the video amplifier input stage. With the contrast voltage
set to OV, the voltage at pin 2 will increase by about 400 mV
to 500 mY. A 4V contrast voltage decreases the voltage at
pin 2 by about 400 mV to 500 mV from the balanced condition. Reviewing Figure 8 note that decreasing the voltage at
pin 2 will decrease the current flow through Q8. Thus the
current flow through Q9 increases, increasing the gain of
the LM1208/LM1209. So increasing the contrast control
voltage at pin 12 increases the gain of the LM1208/
LM1209. The contrast control voltage from Q46 and Q50 is
common to all three channels. To minimize crosstalk it is
necessary to add a decoupling capaCitor of 0.1 /LF across
R3? and R40. Since this can only be done externally, these
two nodes are brought out to pins 1 and 2. The 30n resistor
is added in series with the capacitor for improving stability.
To prevent a destructive current surge due to shorting either
pins 1 or 2 to ground R38 was added for current limiting.

CONTRAST CONTROL

Figure 9 is a simplified schematic of the Contrast Control
circuit. The output of this circuit is common to all three channels. A reference voltage is generated by Z2, Q34, Q35,
R30, and R31. Q36, Q39, and Q41 are all current sources
that are controlled by the reference voltage. The contrast
signal has a OV to 4V range with its input at pin 12. R32 is
used for current limiting any voltage surge that may occur at
pin 12. Note that the input stage (Q3?, Q38, and Q42) are
all PNP transistors. This configuration is necessary for operation down to near ground. At Q44 the input voltage is converted to a current by R33. The input stage will apply the
same voltage across R33 as is applied at the input and with
no temperature variations from the transistors. Q3? is connected to a current source (Q36) to keep a constant current
flow through Q3? and a predictable diode voltage for the
base-emitter of Q3? Q40 is connected as a diode and is
biased by the current source Q39. The current through Q40
is mirrored into Q43, giving a current bias for Q42. Again this
is done to give a predictable diode voltage for Q42. Q41 is a
current source for both Q38 and Q42. With the current
through Q42 already established, the rest of the current
from Q41 flows through Q38. As one can see the input voltage is accurately reflected across R33 with no temperature
coefficients from the input stage of the contrast control circuit.

DRIVE CONTROL
Figure 10 is a simplified schematic of the Drive Control circuit. Each channel has its own drive control circuit. This
circuit is almost identical to Figure 9, the contrast control
circuit. It will be easier to cover the differences between the
two circuits instead of going through virtually the same circuit description. Note that the input stage is exactly the
same. The generation of the reference voltage at the right
hand side of Figure 10 is slightly different than the circuit in
Figure 9. In the drive control circuit the reference voltage at
the base of Q?2 is to be %VCC. In the contrast control
circuit the reference voltage at the base of Q51 was to be
'IoVcc. To generate the %Vcc R5? and R58 form a 2 to 1
voltage divider. With the two to one ratio it is now necessary
to have three transistors connected as diodes, which are
Q?4, Q?5, and Q?6. Q?3 is the buffer for this voltage divider
and its emitter is exactly %Vcc with temperature compensation. R52 and R53 also differ from their corresponding
resistors in Figure 9, R36 and R39. The value difference is
so the base of Q66 is also at %Vcc when the input drive
voltage is at 2V. R38 in Figure 9 was needed for current
limiting at the output pins. Since each channel has its own
drive control circuit no filtering is required, eliminating the
need for external pins. With no external pins no current limiting is necessary, thus the 1k resistor is not used in the drive
control circuit.

Pin 1 of the contrast control output is held at a constant
voltage two diode drops below 'IoVce. To generate this reference the base of Q51 is held at exactly 'IoVcc. R44 and
R45 form a voltage divider. With both Q53 and Q54 connected as diodes the voltage at the junction of R44 and R45
is 'IoVcc plus one diode drop. Q52 is a buffer to this reference voltage, generating exactly YzVcc at its emitter. Q51 is
used to drive the bases of Q49 and Q50 to one diode drop
below the reference voltage. Q50 is used to further buffer
the reference voltage to the base of Q9 (see Figure 8) and
the corresponding transistors in the other channels. Q48 is
used to bias the collector of Q49 to 'IoVce, the same voltage as the collector of Q4? when the differential pair is balanced. This keeps the characteristics of Q4? and Q49 well
matched. Going back to Q44 and R33; these parts set up a
current source that varies the current through R36. With a
2V contrast voltage the differential pair is balanced, meaning that the voltage drop across R36 is YzVce. Q45 buffers
the voltage at R36, driving the bases of Q46 and Q4? Q46
further buffers the voltage, driving the base of Q8 (see Figure 8) and the corresponding transistors in the other two

•
2-133

Circuit Description

(Continued)

.---------------------~-----------------------------------------~I
I
I

R44 I
10k'

R45
10k

R33
5.6k

R34
10k'

. R39
8.8k

R35
10k

TO VIDEO AMP
Q8 BASE

- - - - - - - - - - - - - - - - - - - - - FIGURES - --

4V

1.
~

R41
10k

R42
10k

TO VIDEO AMP
Q9 BASE'
-~----

.I

FIGURE 8
-----------------~

12" CONTRAST CONTROL INPUT
"f0.l J'F

.
0.1 J'F
TL/H/11884-14

FIGURE 9. Simplified Schematic of LM1208/LM1209'Contrast Control

~-------4V

l __

~

------------------------------------------------------

--{151S28DRIVE CONTROL INPUT

"f0.l J'F
TLlH/11884-15

FIGURE 10. Simplified Schematic of LM1208/LM1209 Drive Control

2·134

r-----------------------------------------------------------------------------~ ~

Circuit Description

CLAMP COMPARATOR CIRCUIT

Figure 11 is a simplified schematic of the clamp comparator
circuit. 085 and its input transistors, 081 and 082 are ol)e
half of the differential pair. The base of 081 is connected to
pin 19 via R62. This is the positive input to the comparator.
088 and its input transistors, 090 and 091 are the other
half of the differential pair. The base of 092 is connected to
the junction of R19 and R20 in Figure'14 via R73. This is the
negative input to the comparator. R73 is included only to
match the input characteristics of the positive input, which
requires the 1000 resistor. The negative comparator input is
the feedback from the output stage as briefly described in
the block diagram and covered in more detail in the output
stage circuit description. 086 is the current source for the
differential pair. It is turned on and off by the output of the
clamp gate circuit (Figure 12).0102 of the clamp gate circuit has a current flow of about 225 ,..A when it is turned on.
This current is mirrored into 086. Assume that the inputs to
the comparator are equal, making the differential pair balanced. In this condition 085 and 088 each have a current
flow of 113 ,..A. Looking at the 085 side of the circuit, 084
will also have 113 ,..A of current flow. 080 is set up as a
current mirror to 084, but its emitter resistor is one fourth
the emitter resistance of 084. Thus the current flow for 080
is four times the current flow thru 084, or 450 ,..A. Q83 has
been added to help drive the base of 080, increasing the
accuracy of the current mirror. The collector of 080 directly
charges the capacitor as a current source of 450 ,..A. R65 is
added to discharge the charge stored in the bases of 080
and 084. This is necessary to quickly turn off the current
charge of the clamp capaqitor as the comparator section is
turned off. 087, 089, and 090 work in exactly the same
way. However, the collector of 091 drives another current
mirror with the 450 ,..A. This current flows thru 078. 077 is a
current mirror with 078, thus 450 ,..A also flows thru 077.
079 has been added to help drive the base of 077, again
adding to the accuracy of the current mirror. Since 077 is on
the ground side of the circuit it discharges the clamp

...~

!:

(Continued)
capacitor with 450 ,..A. In this balanced condition the charge
, and discharge current are equal, thus the voltage across the
clamp capacitor remains unchanged.
Going, back to the input stages, note that both inputs, 081
and 092, are driven by a 50 ,..A current source. This keeps
both transistors turned on even when the differential pair,
085 and 088, is turned off. 082 and 090 are added to help
drive the ~bases of 085 and 088 respectively. R64 and R72
, are added to help discharge the charge stored in the bases
of 085 and 088 as these two transistors are turned off.
Since the input stage remains active the differential pair is
quickly turned off. The comparator can also be more quickly
turned on with the input stages remaining active. R67 is
used to assure that the potential difference across the differential pair is minimal during turnoff. Without R67 there
could be a little extra charge or discharge of the clamp capacitor during turnoff, creating an error in the black level of
the video signal. Now assume that the input to pin 19 is
slightly higher than the reference voltage to the negative
input of the comparator. The voltage at the base of 085 is
now higher than the base of 088. This creates an increased
current flow thru 085 and an equal decrease of current flow
thru 088. This current change is multiplied by four in the
increase of current flow thru 080. Likewise the current flow
thru 077 and 091 is decreased by four times the current
change in 088. In the extreme case the current flow thru
080 can increase to 900 ,..A and there would be no current
flow thru 077. 080 does charge ,the clamp capacitor, thus
the voltage across the capacitor will increase. The above is
all reversed when the input to 092' rises above the input
level of 081. If the base of 086, the current source to the
differential pair, is forced close to ground, then there is no
current flow thru 086 and the differential pair, 085 and 088.
With the current flow thru the differential pair set the zero,
all the current mirrors would also have no current flow. Thus
the voltage on the camp capacitor would remain constant,
the desired result during active video.

2-135

co

"r-

...

!:

~
CQ

Circuit Description (Continued)
p~------------~-------~--------------------.~---vee

PUSH PULL
OUTPUT CURRENT
TO CLAMP CAP
FIGURE 8

085

088

R64

50k
R67

082

25k

(-) COMPARATOR
INPUT FROM
VIDEO AMP
FIGURE 14
R73

CURRENT SOURCE
CONTROL FROM
CLAMP GATE
FIGURE 12

R68

500

(+ ) COMPARATOR INPUT

+4V

!

16

~

----------------------------------~

27

0.1 ",F
CUT-OFF ADJ.
TL/HI11884-16

FIGURE 11. Simplified Schematic of LM1208/LM1209 Clamp Comparator Circuit

CLAMP GATE CIRCUIT
Figure 12 is a simplified schematic of the Clamp Gate cir·

input for current limiting during any possible voltage surge at
pin 14. With no resistors at the emitters of 096 and 098 this
circuit will quickly switch. Below 1.4V (1.2V typical) 095 is
turned on and 097 is turned off. Above 1.4V (1.6V typical)
097 is turned on and 095 is turned off. With 097 turned on
0100 is also turned on. This pulls the current thru R79 to
ground, turning off 0102 and 0103. Remember 0102 is a
current mirror to 086 in the clamp comparator. With 0102
turned off, the clamp comparator is also turned off. When
the input signal goes below 1.2V, 097 and 0100 will be
turned off. This allows 0102 to turn on, turning ~n the clamp

cuit. A voltage reference is setup by Z3 and by 0104 and
0105 connected as diodes, generating a 7V base drive to
094,099 and 0101. 094 is used to bias the input stage.
This stage is designed to accept TTL levels at pin 14. 095
and 097 form a differential pair. The base of 097 is set to
2.1V by 099 driving the voltage divider formed by R77 and
R78. In a balanced condition the base of 095 is also at
2.1V. 096 is connected as a diode and the current flow thru
it is mirrored into 098. Also the input to pin 14 would be one
diode drop below 2.1V, or around 1.4V. R74 is added to the

2·136

~------------------------------------------------------~r

....

i:

Circuit Description

(Continued)
comparators of the three video channels. 0103 is added to
help drive the base of 086 in the clamp comparator, increasing the accuracy of the current mirror. 0101 drives
R79 and R80. This sets the current thru 0102, thus setting
the current thru 086 of the clamp comparator.

drive the cathode driver stage well above the black level,
cutting off the beam current in the CRT. This prevents the
bright spot from occurring when the monitor is turned off,
preselVing the phosphor of the CRT. The CRT will also have
its beam current cut off during the time the monitor is first
turned on. This is not a critical period for the CRT since the
filaments have not warmed up to generate a current flow.
The comparator along with R89, R90, and 0115 all form the
spot killer circuit. 0115 acts the same as 01 OS. When 0115
has a high signal at its base it is turned off and the outputs
of the LM1208/LM1209 are in the normal operating mode.
A low signal at the base of 0115 turns on this transistor,
blanking the outputs of the LM1208/LM1209. 0115 is driven by the output of the comparator. The inverting input of
the comparator is connected to an internal 1.2V reference.
The non-inverting side is connected to a resistor divider network, R89 and R90. When Vee is above 10.6V the non-inverting input is above the 1.2V reference, therefore the output of the comparator is high. This high output turns off
0115. Once the Vee drops below 10.6V the comparator's
output goes low, turning on 0115 which forces the outputs
into the blanking mode.

BLANK GATE CIRCUIT
Figure 13 is a simplified schematic of the Blank Gate circuit.
With the exception of the simple output stage and the spot
killer circuit, this circuit is almost identical to the clamp gate
circuit. The only difference is that the output stage is driven
from the opposite side of the differential pair. Thus 0111 is
connected as a diode instead of 0109. With the input at pin
13 at a low level 0108 is turned on, also turning on 029, the
output transistor. 029 is part of the blanking circuit in the
output stage shown in Figure 14. When 029 is turned on the
output is clamped to a blanking level that is "blacker than
black", allowing blanking to be done on the cathodes of the
CRT.
The spot killer circuit is used to force the outputs of the
LM1208/LM1209 into blanking when the Vee drops below
10.6V. Forcing the outputs to a blacker-than-black level will

g.....

....~

g

-------------------------------------------~
R82
25k

7V

R79
23k

CURRENT SOURCE CONTROL
TO CLAMP COMPARATOR
FIGURE 11
R81
SOk

14

FII

CLAMP GATE INPUT
TLfHfl1884-17

FIGURE 12. Simplified Schematic of LM1208/LM1209 Clamp Gate Circuit

2-137

Circuit Description

(Continued)

_0-'_ . . _________ . . '__ ________'___ . . _________ ';',___
'"

~

'I

,:1

1

ti."

,.:
7V

, Ql07

1
1
1
1
1
1
,I

R8S
42k

1
1
1
1

R86
'20k

t----+----+---+ 6~T~~i~tA~
FIGURE 14

R87 '
10.Sk

-------------------------------~
B~ANK GATE INPUT,

TL/H/11884-1B

FIGURE 13. Simplified Schematic of LM1208/LM1209 Blank Gate Cireuit
VIDEO AMPLIFIER OUTPUT STAGE WITH BLANK
CIRCUIT
Figure 14 is a simplified schematic of the Video Amplifier
Output Stage including the blanking circuit. 018 serves as a
buffer between the DC restoration stage shown in Figure 8
and the output stage. A current source is used to fix the
current flow thru 018 keeping it well within its operating "
range. The emitter df Ot 8 drives the bases of 019 and 024
with the current thru 024 being twice that of 019. 019,
along with Q20 thru 023 duplicate the actLial output stage,
going to pin',20. 019 inverts the video signal (note that the
video signal was inverted at 07 in Figure8j. With two inter·
nal inversions of the video signal in the LM1208/LM1209,
the output is non-inverted. The collector of 019 gives a gain ,
of -10 to the video signal and drives'the base of 020. 021' '
through 023 are all'connected as diodes with the emitter of
023 driving R19 and R20. The junction ,of R19 and R20 is
connected to the base of 092 via R73 (shown in Figure 11),
this being the feedback to the negative input of the clamp
comparator. This stage is independent of the actual output
stage at pin 20, but is where the feedbac~ is done for DC
restoration. Therefore it is possibiEi
blank the actual d~t- '
put stage below the black level without affecting the DC
restoration feedback loop. 024 is the equivalent part of 019
in the actual output stage. It also inverts the video signal
with a gain of -10 and drives the base of 030.030 thru
032 each give a diode drop to the level of the video signal,
similar to being connected as diodes. Being connected as
emitter-followers these transistors also give current gain to

to

2-138

the signal. 033 comes close to also giving a diode drop to
the signal, the voltage drop across R27 being insignificant.
R27 has been added to give some isolation between 033
and the internal circuits of the LM1208/LM1209, adding to
the stability of the device. 033 also has R29 in its emitter for
isolation from capacitive 'loads and current limiting from any
pos!lible voltage surges. R28 is at the collector of 033 is
also for curr~iit limiting from voltage surges and minimizing
crosstalk between the three channels through the Vcc line.
To match the loading of the feedback section the output at
'pin 20 should haves load of 3900. To minimize power consumption the feedbaqk' section uses resistor values 10
times larger than those at pin 20. The current source at the
emitter of 033 provides for the capability 'to set the black
level as low as 0.5V.
The video signal does go thru a number of diode drops at
the output stage. One may be concerned that the tracking
over temperature could be a problem. The feedback section
has been designed to tElmperature track the output stage.
The feedback for DC restoration eliminates the temperature
cqefficients <;>f the diode june,tions. The remaining section to
be covered 'is the blanking section. This section comprises
of 025 thru 029. 026 thru 028 are connected as diodes.
025 provides current gain to this stage to adequately pull
down the base of 030 during blanking and also adding another diode potential. During blanking the base of 030 will
be four diode drops above ground, plus the saturation volt-

.-----------------------------------------------------------------------,~

Figure 15 is almost identical.to the schematic shown in Figure 4. The only diff~rence between the two schematics is
that in· Figure 15 each channel has individual adjustments
for both drive and cutoff, making this' circuit a good design
for monitor applications. Each CRT will have a slightly different cutoff voltage for each color, making it necessary to
provide 'separate adjustments in order to accurately set the
cutoff for each color. The gain of each color of the CRT is also
slightly different; if the color temperature of the display is to
be accurately set then each channel of the LM 120S1
LM1209 must have individual gain adjustments. Thus each
channel has its own drive control. Once the drive control is
set, the gain between the three color channels will closely
track as the contrast is adjusted~ All the jumpers needed to
design a single sided PC board are shown in the schematic.
The resistors and jumpers with no reference designation are
the connections between the PC board and the connectors
mounted on the PC board. CN1 thru CNS are BNC connectors.

Circuit Description

(Continued)
age of 029. There are also four diode drops from the base
of 030 to the output, pin 20. Therefore during blanking pin
20 will be less,than 100 mV above ground, enabling the
designer to 'blank at the cathode of the CRT. R23 is added
to quickly turn off .025 by discharging its base when the
blanking signal is removed.
Figure 14 also shows the power and ground pins to the
LM120S/LM1209. All the VCC1 pins (pins 3; 11, 25) are all
internally connected together. A 0.1 ,...F bypass capacitor
must be located close to each pin and connected to ground.
Further bypassing is done by a 100 ,...F capacitor. This capacitor needs to be located on the board close to the
LM120S/LM1209. Pins 22 and 23 are the VCC2pins. These
pins may need a ferrite bead in series with the input power.
A 10 ,...F and a 0.1 ,...F bypass capacitors must be located
close to pins 22 and 23. Correct bypassing of pins 22 and
23 is very Important. If the bypassing is not adequatEi then
the outputs of the LM120S/LM1209 will have ringing, or
even worse they may oscillate. The ground side of the bypass capacitors at pins 22 and 23 must be returned to a
ground plane with no interruptions from other traces between these capacitors and the ground pins 21 and 24 of
the LM120S/LM1209.

A 30n resistor is in series with each of the video inputs. A
voltage surge may occur at· these inputs when either the
inputs are first connected to another system, or when the
system is powered up before the monitor is turned on. If this
voltage surge exceeds the supply voltage (at ground potential if the monitor is not powered up) of the LM120S/
LM1209, or goes below ground, current will flow through the
parasitic devices of the LM120S/LM1209. This current is
limited by the 30n resistors, preventing a potential catastrophic failure. A 100n reSistor is added to the Blank Gate
and Clamp Gate inputs. These two resistors also limit

Applications of the LM12081
LM1209
Figure 15 is the schematic of the demonstration board designed at National. Figure 16 is the actual layout of the demonstration board. Note that the schematic shown in
Vee 1

----------------------------~-------------.

Vee 2

3~----~~~~~~----~--------,

4.

R17

11}-+----i

R21

2k

25~----i

FROM
VIDEO AMP
INPUT
STAGE
FIGURE 8

26
2.4k

(TO son
TERMINATION)

FROM BLANK
GATE
FIGURE 13

t-----i--(24

R22

200

7~------~~~----~---+--~----~--~~---+--------~_i21

TL/H/11884-19

FIGURE 14. Simplified SchematiC of LM1208/LM1209 Video,Amplifler Output Stage with Blank Circuit

2-139

....
==

~
......

....~

g

Applications of the LM12081LM1209 (Continued)
the current during a voltage surge. A larger resistor ia required because these, inputs are Db coupled, allowing' the
current to, continuously flow into thes~ inputs before the
monitor is ,turned on. 1000 resistors are not recommended
at the video inputs because this resistance value will.start to
roll off the frequency response of the LM1208/LM1209.
Note that the layout shown in Figure 16 does have a very
extensive ground' plane. One must remember, that the
LM1208/LM1209 is a 130 MHz/100 MHz part and a single
sided board is difficult to successfully design. A ground
plane similar to the layout shown in Figure 16 must be provided for good performance of the LM1208/LM1209 when
using either a single sided or double sided board. The layout
of this board demonstrates the importance of grounding.
The results ,of this layout are shown in Figures 118 through
11d. In these photographs the LM1208 rise time was
2.40 ns and the fall time was 3.00 ns. For the LM1209, the
rise time was 3.05 ns and the fall time was 3.45 ns. The
output was a 4 Vpp signal and the cutoff voltage was set to
2V. The overshoot will subsequently be filtered out by the

loading effects of the CRT driver stage and the CRT itself.
When the LM1208lLM1209 is deSigned into a video board
one must keep the ground to the CRT driver stage separate
from the ground of the LM1208/LM1209; connecting the
two grounds together only at one point National Semiconductor also manufactures a line of CRT drivers. Please contact NatiOnal for additional information. These drivers greatly simplify the driver design allowing for shorter deSign ,cycles. Of course the LM1208/LM1209 can also be designed
with a discrete driver stage. Figure 18 shows a design using
a simple cascade CRT driver. The LM1208/LM1209 block
would be the same schematic as shown in Figure 15.

REFERENCES
Zahid Fiahim, "Guide to CRT, Video Design," Application
Note 861, National Semiconductor Corp., Jan. 1993
Ott, Henry W. Noif;e Reduction Techniques in Electronic
Systems, John Wiley & Sons, New York, 1976

Jl

C4

0.1 "F

CN1~
lRll
75

5011
SCOPE

CN2~
lR12
75

5011
SCOPE

CN3~
lR13
75 '

5011
SCOPE

CN5@}-----+---'A1Io-j-I
CN4 (~--C::L;,::AM:;,P...:G;;;.AT:.::E+_--w,._H

TL/H/I1884-20

FIGURE 15_ Demonstration BoaRiSchematlc
2-140

,--------------------------------------------------------------------------, r
i:

....

Applications of the LM1208/LM1209 (Continued)

I\)

i.....
r

iI:
....

~

TUH/11884-21

FIGURE 16. Demonstration Board Layout

til

2·141

Applications of the LM1208/LM1209 (Continued)

, ,

:.

TL/H/11884-23

TL/iVi1884-22
.,;

FIGURE 17a. LM1208 Rise Time,

FIGURE 17b. LM1208 Fall Time

TLlHt11884-28

TL/H/11884-29

FIGURE 17c. LM1209 Rise Time

FIGURE 17d. LM1209 Fall Time

1 - -......

TO LV
SUPPLY

2 7 t - -........
26~--.---------~

LM120B/
LM1209

390

TLlH/11884-24

FIGURE 18. LM1208/LM1209 Typical Application

2·142

r

tt/National Semiconductor

PRELIMINARY

LM1212
230 MHz Video Amplifier System with OSD Blanking
General Description
The LM1212 is a very high frequency video amplifier system
intended for use in high resolution monochrome or RGB
color monitor applications with 05D. In addition to the wideband video amplifier the LM1212 contains a gated differential input black level clamp comparator for brightness control, a DC controlled attenuator for contrast control and a
DC controlled sub contrast attenuator for drive control. The
DC control for the contrast attenuator is pinned out separately to provide a more accurate control system for RGB
color monitor applications. All DC controls offer a high input
impedance and operate over a OV-4V range for easy interface to bus controlled alignment systems. During the 05D
window, the output is blanked to < O.4V. The LM1212 operates from a nominal 12V supply but can be operated with
supply voltages down to 8V for applications that require reduced IC package power dissipation characteristics.

Features

• Externally gated comparator for brightness control
• OV to 4V high input impedance DC contrast control
(> 40 dB range)
• OV to 4V high input impedance DC drive control
(±3 dB range)
• Ouput blanked to < 0.4V for 05D window
• Easy to parallel three LM1212s for optimum color
tracking in RGB systems
• Output stage clamps to 0.65V and provides up to 9V
output voltage swing
• Output stage directly drives most hybrid or discrete
CRT amplifier stages

Applications
•
•
•
•

High resolution CRT monitors with 05D
Video switches
Video AGC amplifier
Wideband amplifier with gain and DC offset 9Qntrol

• Wideband video amplifier
(f -3 dB = 230 MHz at Va = 4 Vpp)
• t r, tl = 1.5 ns at Va = 4 Vpp

Block and Connection Diagram

VIDEO OUT
BLANK GATE
GROUND
ATTENUATOR REF

1

CLAMP CAP

1 - - - - - - - - - - - -....

DRIVE CAP
DRIVE CAP

CLAMP(+)
CLAMP( -)
SYSTEM Vee 1

[!]
CLAMP GATE
GROUND

TL/H/12354-1

Order Number LM1212M or LM1212N
See NS Package Number M20B or N20A

2-143

!!I:
....
....
N
N

~ ~------------------------------------------------------------------------------------,

~

~

tflNational Semiconductor

ADVANCE INFORMATION

LM1281
85 MHz RGB Video Amplifier System with On Screen
Display (OSD)
General Description

Features

The LM1281 is a full feature video amplifier with aso inputs, all within a 28-pin package. This part is intended for
use in monitors with resolutions up to 1024 x 768. The video
section of the LM1281 features three matched video amplifiers with blanking. All of the video amplifier adjustments
feature high input impedance OV to 4V DC controls, providing easy interfacing to bus controlled alignment systems.
The OSO section features three TIL inputs and a DC contrast control. The switching between the OSO and video
section is controlled by a single TIL input. Although the
OSO signals are TIL inputs, these signals are internally processed to match the OSO low level to within 100 mV of the
video black level. When adjusting the drive controls for color
balance of the video signal, the color balance of the OSO
display will track these color adjustments. The LM1281 also
features an internal spot killer circuit to protect the CRT
when the monitor is turned off. For applications without
OSO insertion please refer to the LM1205 or LM1208 data
sheets.

• Three wideband video amplifiers 85 MHz @ -3 dB
(4 Vpp output)
• TIL OSO inputs, ,50 MHz bandwidth
• On chip blanking, outputs under 0.1 V when blanked,
• Video/OSO switch speed of 7 ns
• Independent drive control for each channel for color
balance
• OV to 4V, high impedance DC contrast control with over
40 dB range
• OV to 4V, high impedance DC drive control (0 dB to
-12 dB range)
.
• OV to 4V, high impedance DC OSO contrast control
with over 40 dB range
• Capable of 7 Vpp output swing (slight reduction in
bandwidth)
• Output stage directly drives most hybrid or discrete
CRT drivers

Applications
• High resolution RGB CRT monitors requiring OSO capability

Block and Connection Diagram
Red OSD Input

1

1------.

Gr.en OSD Input

2

1----.

Video/OSD Switch

4

I-.-+-+-+_---'

RGB Cutoff Adjust

Red Video In

5

1-+-+-1--'

Red Clamp Cap

Green Drive Adjust

Blue OSD Input

Blue Drive Adjust

Red Video Out
Ground

7

Gr.en Video In ~J--+-+---'

Ground
Green Video Out

Ground

Gr.en Clamp Cap

Blue Video In

Blue Video Out
Blue Clamp Cap

Video Contrast

Blank Gate

OSD Contrast

Clamp Gate

TL/H/12355-1

FIGURE 1. Order Number LM1281N
See NS Package Number N28B
2-144

,-------------------------------------------------------------------------, r
ill:
N

.".

.....

t!lNational Semiconductor

G)

......

r
ill:

N
.".

LM2416/LM2416C Triple 50 MHz CRT Driver

.....

G)

o

General Description

Features

The LM2416 contains three wide bandwidth, large signal
amplifiers designed for large voltage swings. The amplifiers
have a gain of -13. The device is intended for use in color
CRT monitors and is a low cost solution to designs conforming to VGA, Super VGA and the IBM® 8514 graphics standard.

• 50 Vpp output at 45 MHz drives CRT directly
• Rise/fall time typically 8 ns with 8 pF load
• 65V output swing capability

The part is housed in the industry standard 11-lead TO-220
molded power package. The heat sink is floating and may
be grounded for ease of manufacturing and RFI shielding.

Applications
• CRT driver for RGB monitors
• High voltage amplifiers

Schematic and Connection Diagram

(One Section)
~____________'-~"~V+

11
10

V+
VOUT3
BIAS 3

8
1
5
4

3

2

VIN3
BIAS 2
VIN2

GND
VOUT2
VOUT1
BIAS 1
VIN1

R2

+-____________....

_5~

PIN 1 DESIGNATOR

GND

TL/K/10738-2

Top View
TL/K/10738-1

Order Number LM2416T or LM2416CT
See NS Package Number TA 118

II

2-145

,

Absolute Maximum Ratings
Supply Voltage, V+

+85V

Power Dissipation, Po

10W
- 25·C to + 1000C

Storage Temperature Range, T STG
Operating Temperature Rang~( TeASE
Lead Temperature (Soldering:

- 20·C to + 900C

< 10 sec.)

'3000C
4kV

ESD Tolerance

Electrical Characteristics

v+ = 80V, CL = 8 pF, DC input bias, 'VIN
otherwise noted.
Parameter

Symbol

If Military/Aerospace specified devices are required,
please contact the National Semiconductor ,Sales
Office/Distributors for availability and specifications.

= 3.6 Voc- 50 Vppoutput swing, VelAS = '+ 12V. See Figure 1. Til = 25·C unless
LM2416

Conditions

Icc

Supply Current
(per Amplifier)

No lliput or
Output Load

Ll12416C

Units

Min

Typical

Max

Min

Typ

Max

18

22

26

16

22

28

mA

38

35

42

48

Voc

= 3.6V

VOUT

Output Offset Voltage

VIN

42

46

Ir

Rise Time

10% to 90%
(Note 3)

8

13

12

16

ns

t,

Fall Time

10% to 90%
(Note 3)

8

13

12

16

ns

BW

Bandwidth

-3dB

Av

Voltage Gain

OS

Overshoot

Figure 1

0

0

LE

Linearity Error

(Note 1)

8

10

42
-11

-13

35
-15

-10

MHz

-13

-16

%
%

Gain Matching,
(Note 2)
0.2
0.5
I!J.Av
Note 1: Linearity Error is, defined as the veriation in smell ,Signal gain from + 20V to + 70V output With a 100 mV AC, 1 MHz, input signel,
Note 2: Calculated value, from Voltage Gain test on each ?hannel.
Nole 3: Guaranteed parameter, not tested.

Test Circuit: '

fBie.

200

0.47p

,~.~

1'6'8~
360

_

dB

Typical Performance
Characteristics

o8OV

2'7.9~

VIV

VOUT

3,4,10

LM2416 Frequency Response

I

10 504 Scop.

, 4950

G,± O~~F
8pF'

0-

!il"
~

~

O.otpF

3.6V

0

TL/K/10738-3

-3

• 8 pF Is total load capacitance. It li1c1lJdes all parasitic·capacitance.

FIGURE 1. Test Circuit (One Section)

Figure 1 shows a typical test circuit for evaluation of the
LM2416. This circuit is designed to allow testing of the
LM2416 in a 50n environment such as a pulse generator,
oscilloscope or network analyzer.

I

10

100

FREQUENCY (MHz)

TUK/10738-4

LM2416 Pulse Response
80

....

70

~c:.

~

60

50

\

\

40

\

30

,

20
0

20

40

60

TIME (nS••)

TUK/10738-5

2·146

.-----------------------------------------------------------------------------'r
i:
LM2416-Theory of Operation
Thermal Considerations
....
The LM2416 is a high voltage triple CRT driver suitable for
The transfer characteristics of the amplifier are shown in
I\)
~

VGA, Super VGA, IBM 8514 and 1K by 768 non-interlaced
display applications. The LM2416 features 80 volt operation
and low power dissipation. The part is housed in the industry
standard 11 lead TO-220 molded power package. The heat
sink is floating and may be grounded for ease of manufacturing and RFI shielding.
The circuit diagram of the LM2416 is shown in Figure 2. 01
and R2 provides a conversion of input voltage to current,
while 02 acts as a common base or cascode amplifier stage
to drive the load resistor R1. Emitter followers 03 and 04
isolate the impedance of R1 from the capacitance of the
CRT cathode, and make the circuit relatively insensitive to
load capacitance. The gain of this circuit is - R1/R2 and is
fixed at -13. The bandwidth of the circuit is set by the
collector time constant formed by the load resistor R1 and
associated capacitance of 02, 03, 04, and stray layout capacitance, Proprietary transistor design allows for high
bandwidth with low operating power.

Figure 3. Power supply current increases as the input signal
increases and consequently power dissipation also increases.

The LM2416 cannot be used without heat sinking. Figure 3
shows the power dissipated in each channel over the operating voltage range of the device. Typical "average" power
dissipation with the device output voltage at one half the
supply voltage is 1.8W per channel for a total dissipation of
5.4W package dissipation. Under white screen conditions,
i.e.: 15V output, dissipation increases to 3W per channel or
9W total. The LM2416 case temperature must be maintained below 90"C. If the maximum expected ambient temperature is 50"C, then a heat sink is needed with thermal
,resistance equal to or less than:
R

th

~
r
i:

~
....

~

= (90 - 50'C) = 4 4'C/W

9W

.

The Therrnalloy #6400 is one example of a heatsink that
meets this requirement.
WARNING: THE LM2416 IS NOT PROTECTED AGAINST
OUTPUT SHORT CIRCUITS. The minimum resistance the
LM2416 can drive is 600n to ground or V + .

LM2416
90

§'
0

c:.

VCCI

...

OUTPUT

C)

!:J

§!
I-

:::>

J!:

INPUT

:::>
0

80
70
60
50
40
30
20
10

........

-

"- ~

POWER

VOLTAGE

~

"

2

3

4

0

~

2.0

'"

!!!
Q

'"

~

,r

%

g,

1/
/' r-....

./

o

-

~~
3.0

......

-

1.0

15
~

"-

567

INPUT VOLTAGE
TUK/10738-7

FIGURE 3. LM2416 DC Characteristics

TUK/10738-6

FIGURE 2. LM2416 CRT Driver
(One Section)

fII

2-147

~)oo!,r

*' RED~

*

.t. 1

5111

'271-+--JoJ"""'-''NIrl
10011

261-+--------,

200

500

251-+----~--_+----~

~+- c~igrr
24

~7

23

5.1k

~'!'r

75

An

GREEN DRIVE

10k

5111

221-++JoJ"""--''NIrl
LM1203

10011

~

75

211-++------,
B

10!,r

•

7511

10k

It--

r-ir-=---

"(,.

S.lk

500

C
......~~~~+~~~------~9
V;o;:O
IN

LM2416

10

Vo.;!'r

--------1"

r-_ _

10

!'r~

r----------I12

=fV

171-++--------.

~--~._----~--I13

O.OI!,r
--14

75

10
10k,

Sk

10k

~~

()
BLACK LEVEL
GATE IN

~7

T
V

BLACK LEVEL
(BRIGHTNESS)
CONTROL
O• l !'r

11

5.1k

-=3

1000pr

~r~~
-

100V

-

+BOV
TL/K/l073B-B

FIGURE 4. Typical Application LM1203·LM2416 Application
application, feedback is local to the LM 1203. An alternative
scheme would be feedback from the output of the LM2416
to the positive clamp inputs of the LM1203. This would provide slightly better black level control of the system.

A typical application of the LM2416 is shown in Figure 4.
Used in conjunction with a LM1203, a complete video channel from monitor input to CRT cathode is shown. Performance is satisfactory for all applications to 1k by 768 non-interlaced. Typical rise-fall times are 12 ns, with better than
50V pop drive signals available to an 8 pF load. In this

2-148

.--------------------------------------------------------------------------------, r-

i!i:

I~

l!fINational Semiconductor

LM2418 Triple 30 MHz CRT Driver
General Description

Features

The LM2418 contains three large signal voltage amplifiers
designed to directly drive CRT cathodes for VGA Color
Graphics Displays. Output swings greater than 50 Vpp are
achieved with a 90V power supply. The nominal voltage
gain of each amplifier is -19 with gain matching of 1.0 dB
between amplifiers.

•
•
•
•
•
•
•

Packaging is the industry standard molded 11 lead TO-220.
The heatsink tab is isolated and may be grounded to improve RFI shielding and simplify assembly.

50 Vpp output at 30 MHz drives CRT directly
Rise/fall time typically 12 ns with 8 pF load
65V output swing capability
Optimized output stage for low crossover distortion
Gain matching of 1 dB
Voltage gain of -19
Includes oscillation supression resistors

Applications
• CRT driver for RGB monitors
• High voltage amplifiers

Schematic and Connection Diagram

(One Section)
11
10

9

8

3.4.10
Your

7

6

2.7.9, o----<_Wlr--I

5

VSIAS

4

R3

1.6.8o-_r
VIN

3

__-I

2

V+
VOUT3
BIAS 3
V1N3
BIAS 2
V1N2

GND
VOUT2
VOUT1
BIAS 1
VIN 1

R2

1-----.....

- 0 5 GND

PIN 1 DESIGNATOR
TL/K/11125-1

FIGURE 1

TLlK/11125-2

Top View
Order Number LM2418T
See NS Package Number TA 11 B

2-149

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V+

- 20·C to + 10eoC

Operating Temperature Range, TCASE

300·C

Lead Temperature (Soldering, <10 sec.)
ESO Tolerance

tbd

+95V
- 25·C to + 10eoC

Storage Temperature Range, TSTG

Electrical Characteristics
v+ = 90V, CL = 8.pF, DC input bias, VIN = 3.6 Vec. 50 Vpp output swing, VBIAS = + 12V. TA = 25·C unless otherwise noted.
Symbol

LM2418

Conditions

Parameter

Max

Units

Min

Typ
18

26

mA

46

53

60

Vec

Icc

Supply Current (per Amplifier)

No Input or Output Load

VOUT

Output Offset Voltage

VIN= 3.6V

tr

Rise Time

10% to 90% (Note 3)

12

20

ns

tf

Fall Time

10% to 90% (Note 3)

12

20

ns

-3dB

30

MHz

BW

Bandwidth

Av

Voltage Gain

OS

Overshoot

LE

Linearity Error

(Note 1)

8

%

b.Av

Gain Matching

(Note 2)

1.0

dB

-17

-19

-23

5

Note 1: Linearity Error Is defined as Ihe variation in small signal galn from + 20V 10 + 70V oulpul with a 100 mV AC.
Note 2: Calculaled value from Voltags Gain lesion each channel.
Note 3: Guaranteed parameter, nollested.

1 MHz.

VIV
%

inpul signal.

AC Test Circuit
Figure 2 shows a typical test circuit for evaluation of the LM2418. This circuit is deSigned to allow testing of the LM2418 in a 50n
environment such as a pulse generator, oscilloscope or network analyzer.
f2V Bia.

±.

Vou,

2,7,911

3.4.10

0.471'F

~~

r

to50.nScope
4950 ..., II

1.6.8
5 ; X : b 8pF'

c,.

360

O.OII'F

_ . I-

I~

O.II'F

-=-=

V,N
3.6 VDC

TL/K/11125-3

'S pF is total load capacitance. II includes all parasitic capacitance.
FIGURE 2. Test Circuit (One section)

Typical Performance Characteristics
LM2418 Frequency
Response

LM2418 Pulse
Response

VOUT=5 OVpp

YT=IO

0

~

i

80

E

-2

i

-4

I

1.
I
VT=90Voc

80

ti.=8pF

\

40

20

-8

0
1

10

0

100

20

40

80

80

100

TIME (n.)

FREQUENCY (MHz)

TLlK/11125-5

TL/K/11125-4

FIGURE 3

2-150

r-----------------------------------------------------------------------------,
LM2418-Theory of Operation
The LM2418 is a high voltage triple CRT driver suitable for
VGA display applications. The LM2418 features 90V operation and low power dissipation. The part is housed in the
industry standard 11-lead TO-220 molded power package.
The heat sink is electrically isolated from the circuitry and
may be grounded for ease of manufacturing and RFI shielding.

capacitance probe to match the output of the LM2418 to a
500 cable and load. Typical AC performance of the circuit is
shown in Figure 3. The input signal is AC coupled to the
base of 01, while a DC bias of 12V is applied to the base of
02 (See Figure 2).

The circuit diagram of the LM2418 is shown in Figure 1.01
and R2 provide a conversion of input voltage to current,
while 02 acts as a common base or cascade amplifier stage
to drive the load resistor R1. Emitter followers 03 and 04
isolate the impedance of R1 from the capacitance of the
CRT cathode, and make the circuit ,relatively insensitive to
load capacitance. The gain of this circuit is - R1/R2 and is
fixed at -19. The bandwidth of the circuit is set by the
collector time constant formed by the load resistor R1 and
associated capacitance of 02, 03, 04, and stray layout capacitance. Diodes D1 and D2 provide forward bias to the
output stage to reduce crossover distortion at low signal
levels, while R3 provides a DC bias offset to match the output level characteristics of the LM1203 RGB Video Amplifier
System. Proprietary transistor design allows for high bandwidth with low operating power.

The transfer characteristics of the amplifier are shown in
Figures 4 and 5. Power supply current increases as the input signal increases and consequently power dissipation
also increases.
The LM2418 cannot be used without heat sinking. Figure 5
shows the power dissipated in each channel over the operating voltage range of the device. Typical "average" power
dissipation with the device output voltage at one half the
supply voltage is 1.8W per channel for a total dissipation of
5.4W package dissipation. Under white screen conditions,
i.e., 20V output, dissipation increases to 3.0W per channel
or 9W total. The LM2418 case temperature must be maintained below 100"C. If the maximum expected ambient temperature is SO"C, then a maximum heat sink thermal resistance can be calculated:

90

N

~

..,

'"

!i!

c..,
IL

z-'

~~
0 ...

=>=>

2 ....

50

21L

x!;

IL~

~o

/
.".
VOLTAGE , /

40

2.0

/t

~>I:

oz
;::z

o
4

= 4.4"

"'~

-:;
z..,

~

3

(100"C - SO"C)
9W

PRECAUTION: THE LM2418 IS NOT PROTECTED
AGAINST OUTPUT SHORT CIRCUITS. The minimum resistance the LM2418 can drive is 8000 to ground or V+.

C;:;O
en",

1.0

/

2

=

70

V

10

th

V+ '" 90V

/

SO

>
....=>

e:
=>

VOLTAGE'

....~

CD

Thermal Considerations

Figure 2 shows a typical test circuit for evaluation of the
LM2418. This circuit is designed to allow testing of the
LM2418 in a 500 environment such as a pulse generator
and a scope, or a network analyzer. In this test circuit, two
resistors in series totaling 4.95 kO form a wideband low

80

r

i:

/

L

~

./

F-j;Ow[R
i"""

~

zd
1.5

~~

IL:E:

C;:;O

!!!'"
", ...
IL

1.0 ffi~

~~

~

0.5

55 60 65 70 75 80 85 90 95

6

v+ (V)

INPUT VOLTAGE (V)
TL/K/11125-7

TL/K/11125-9

FIGURE 4. LM2418 DC Characteristics

FIGURE 5_ LM2418 Output Swing
and Power Characteristics

•
2-151

.~...

co. ,---------------------------------------------------------------------------------,

Typical Application
A typical application of the' LM2418 is shown in Figure 6.
Used in conjunction witl" an LM1203, a complete video
channel from monitor inpu1 to CRT cathode is shown. Per·
formance is satisfactory for all applications up to 640 by 480
lines. Typical rise/fall times of this circuit are 15 ns, with

ii:i
Ii +

VIDEO
IN

-

Tv+
+12V

1

'-'

ii~2
~~

o I'F
7511
10k

ii~

better than 50 Vpp drive signals,available to a 10 pF load. In
this application, feedbaCk is local.to theLM1203, an altema··
tive scheme would feed back from the output of the LM2418
to the positive clamp inputs oHhe LM1203. This would pro·
vide better black level control of the system.

::::!:;; 100 I'F

"*

28

10011

3

26

4

25

5

24

VIDEO
IN

+

VIDEO
IN

5111
7

oI'F
II

7511

10 I'

10k

~I'F

F~
max

CONTRAST
CONTROL

,~

22
10011 ~7

8

21

9

20

10

19

11

18

12

17

13

16

14

15

75

500

E+- GREEN
"7 ~'I'F

I

~UTOFF

V

E~

O.OII'F

r-I-

75

GREE.r

LM1203

5111

t

C~{gFF

E+-

23

6

V II~I'F

LM2418T

~7 ~'I'F

10k

7511

~

500

o I'F
Ii +

.n

RED DRIVE

5111

27

BLUE
CUTOFF

.- "7 500 ~ II'F

10k

E+-

~7 ~
5kt

75

10

min" '" O.II'F
10k

--..iL
BLACK LEVEL
GATE IN

10k
10k

E-

.. >'

f

BLACK LEVEL
(BRIGHTNESS)
CONTROL

11

1000 pF
O•' I'F

Dr---j~
-

100V

-

+90V
TUK/11125-10

FIGURE 6. Typical Application LM1203-LM2418 Application

2-152

r-------------------------------------------------------------------------,

r
i:
N

....
CD
~

f}1National Semiconductor

LM2419
Triple 65 MHz CRT Driver
General Description

Features

The LM2419 contains three wide bandwidth, large signal
amplifiers designed for large voltage swings. The amplifiers
have a gain of -15. The device is intended for use in color
CRT monitors and is a low cost solution to designs conform·
ing to 1024 x 768 display resolution.
The device is mounted in the industry standard 11-lead
TO-220 molded power package. The heat sink is electrically
isolated and may be grounded for ease of manufacturing
and EMIIRFI shielding.

•
•
•
•
•

50 Vpp output swing at 65 MHz
Rise/Fall time 5 ns with 12 pF load
60 Vpp output swing capability
Pin and function compatible with LM2416
No low frequency tilt compensation required

Applications
• CRT driver for SVGA, IBM 8514 and 1024
I display resolution RGB monitors

x 768

Schematic and Connection Diagrams
One Channel

...---....--oV+

11
V+

11
10

VOUT3
VSIAS3

VOUT

VIN3

3,4,10

7
R3

VSIAS2

VSIAS

2,7,9

6

0

150

II

R4
550

5
4

VIN
1,6,8

3

VIN2
GND
VOUT2
VOUT1

2
VSIASI
VIN1

0
TL/H/11442-1

PIN 1 DESIGNATOR
TUH/11442-2

Order Number LM2419T
See NS Package Number i A 118

2-153

PI

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required;,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+)
+8SV
-2S·Cto +100"C
Storage Temperature (TSTG)
- 20·C to + 90"C
Operating Case Temperature, TCase
Lead Temperature (soldering < 10 sec.)
300"C
ESD Tolerance
2kV

,,'

Electrical Characteristics
Unless otherwise spe'cifi6d, the fol/owing"specifications apply fon/+ = 80V, DC input bias, Y,N DC
swing; frequency = 1 MHz; VSi~ = 12V;CL = 12 pF; TA = 2S·C; see test circuit, Figure 1.
Symbol

Mlh
(Note 3)

'Parameter

Conditions

Icc

Supply Current (per Amplifier)

Iriput/OutputOpen Circuit

IS

Bias Current (Pins 2 or 7 or 9)

VOUT

Output Offset Voltage

=

3.9\1; SO Vpp output

Typ
(Note 2)
27

,.,

Max
(Note 3)

Units
(Limit)

40

mA

I'

mA

11
40

SO

tr

Rise Time

10% to 90%

S

tf

Fal/Time

90% to 10%

S

Av

Voltage'Gain

OS

,Overshoot

Y,N: fr, tf < 2 ns

LE

,!-inearlty Error

VOUT

AAvmatch

Gain Matching

-13

-'-1S

60

V
ns
ns

-18

VIV

8

= 2SV to 7SV

%

8

%

0.3

dB

Note 1: Absolute Maximum Ratings inaicate limits beYllnd which damage to the device may occur. ~ guaranteed SPecifications apply only for the test conditions
Ii~~d. Some P,9rforrhance chara~eristics may d~ra~ when the device is not operated under the ligted test conditions.

Nole 2: Typical specifications are at 25'C and represent the most likely parametric norm.
Note 3: MinIMax lim"s are guaranteed to National's AOQL (Average Outgoing Qua/"r Level).

,

Typical, Performance
Characteristics

.

TA

= 2S·C, Test Circuit-Figure 1
Frequency ResponSe

v+
+80V

~100;'F
~toov

N~O.O;=-"F
_,

VB1AS

VIN +12V 0.47 J.'F

'B;:

~~,

390

0.01 "F

, ..

GND

J:;<;.
I ' 1 2 PF

o,~~

~

~

Z

:;;:

-

'"

"

-6dB
-9dB

\

TL/H/I1442-3

pF is the tol1" load' capacit8nce and'includes the test fixture capacitsnce.
'12

73dB

-t2dB

3.9V

:1

+

0

'CD

VIN ~

,

\
.~.

_

4950

,+3dB

VOUT
to son SCQpe
or Network Analyzer

IN

10M

100M

fREQUENCY (Hz)

FIGURE 1. Test Circuit (One Section)

TUH/11442-4

2-154

small signal cross over distortion. R,esistor R3 is used to
prevent 02 from oscillating at high frequencies.

Typical Performance
Characteristics (Continued)

. . . - - -.....-OY+

TA = 25"C, Test Circuit-Figure 1

Rl
Ik

Pulse Response

03
01 ~,

_ _ _ I· .. · · · · · · · · · · · · ·

,I

>

15

~
o

~
....
>

Your

r-

····~~·_""··_I

04
R3
YBIAS

02
150

\

R4
550

~ 01

Y,N

-

.. \\l..:..:.;.-.I--+-...,..If. ... .... .... ....

R2
70

HORIZ: 10 n./DIV
TL/H111442-5
TL/HI11442-7

FIGURE 2. Schematic Diagram of
One Section of LM2419

Test Circuit
Figure 1 shows a typical test circuit for evaluation of the
LM2419. The input signal is AC coupled into the input of
LM2419 and is referenced to 3.9V DC using an external
3.9V DC bias through a 390n resistor. The test circuit is
designed to allow testing of the LM2419 in a 50n environment such as a 50n oscilloscope or network analyzer. The
4950n resistor in series with the output of the LM2419
forms a 100;1 voltage divider when connected to a 50n
oscilloscope or network analyzer.

Application Hints
POWER SUPPLY BYPASS
Since the LM2419 is a wide-bandwidth ampli~ier with greater
than 10,000 V/
slew rate, proper power sUPI?'Y bypassing
is critical for optimum performance. Improper power supply
bypassing can result in large overshoot, ringing and oscil/ation. A 0.01 ",F ceramic capacitor should be connected as
close to the supply pin as is practical (preferably less than
%" from the supply pin). The lead' length of the 0.01 ",F
ceramic capaCitor should be as small as is practical. In addition, 10 ",F -100 ",F electrolytic capaCitor should be connected from the supply pin to ground. The electrolytic capacitor should be placed reasonably close to the LM2419's
supply pin.

"'S

Theory of Operation
The LM2419 is a high voltage triple CRT driver suitable for
SVGA, IBM 8514 and 1024 x 768 display resolution monitors. The device is packaged in the industry standard
11 lead TO-220 moldE;ld power package. The heat sink is
electrically isolated and may be grounded for ease of manufacturing and RPI/EMI shielding.

ARC PROTECTION
The LM2419 must be protected from arcing within the CRT.
To limit the arcover voltage, a 200V spark gap is recommended at the cathode. Clamp diodes D1 and D2 (as
shown in Figure 3) are used to clamp the voltage at the
output of LM2419 to a safe level. The clamp diodes used
should have high current rating, low series impedance and
low shunt capaCitance. Resistor R2 in Figure 3 limits the
arcover current while R1 limits the current into LM2419 'and
reduces the power dissipation of the' output transistors
when the output is stressed beyond the supply' voltage.
Having large value resistors for R1 andR2 would be desirable but this has the effect of reducing rise and fall times.

The schematic diagram of LM2419 is shown in Figure 2. 01
and R2 provide a conversion of the input voltage to current
while 02 acts as a common base amplifier to drive the load
resistor, R1. Resistor R4 along with R2 sets up the DC bias
at the base 0!"01. Emitter followers 03 and 04 isolate R1
from the capacitive load at the output, thus making the rise
and fall times relatively insensitive to the. load capaCitance.
The gain of the amplifier is -R1/(R2 II R4) and is fixed at
approximately -15. The bandwidth of LM2419 is primarily
limited by the time constant due to R1 and the capacitances
associated with D1, 02, 03 and 04. Diode D1 is used to
provide some bias voltage for 03 and 04 so as to reduce

2-155

....

~ r-------------------------------------------------~--------------------------,

~

~

Application Hints (COntinued)
11.+
+8011.

Cl
100),F*

.

100V~

.......

k1; •
11

LII2419

o.:.---------tV

V1N l
(From Video Preamplifier)

~:-

01

.4~FDH400

C4
~O.Ol)'F

3

R1
""
20

5

Cathode

R2,....!;!.,..

~ ~OV

51
O.l)'H
- t- D2
.. ~ FDH400

..1.Spark Gap

-::~ND
TLlH/11442-8

FIGURE 3. Typical Application Circuit (One Channel)
IMPROVING RISE AND FALL TIMES
Because of an emitter follower output stage, the rise and fall
times of the LM2419 are relatively unaffected by capacitive
loading. However, the series resistors Rl and R2 (see Figure 3) will reduce the rise and fall times when driving the
CRT's cathode which appears as a capacitive load. The capacitance at the cathode typically· ranges from 8. pF to
12 pF.
To improve the ris~ and fall times at the cathode, a small
inductor is often used in series with the output of the amplifier. The inductor L1 in Figure j paaks the' amplifier's frequency respOnse at the cathode, thus improving rise and fall
times. The inductor value is empirically determined and is
dependent on the load. An inductor vall.le of 0.1 ""H is a
good starting value. Note that peaking tlTe amplifier's frequency response will increase the overshoot.

Table I. LM2419 Output Overshoot
vs Capacitive Loading for a Typical Device
Input Signal
trltf

5pF

8pF

11 pF

1.2 ns

4%

6%

7%

8%

7ns

4%

5%

6%

7%

CL
15pF

GAIN VS OUTPUT DC LEVEL
Figure 4 shows LM2419's gain versus output DC .level. A
100 mVpp AC signal is applied at the LM2419's input and
the input Signal's DC level is swept. As can be seen from
Figure 4, the amplifier'S gain is constant at approximately
15.4 (VOUT = 1.54 Vpp) for Qutput DC level between 35V
and 65V. Thus the amplifier's output response is linear for
output voltage between 35V and 65V. If the output voltage
is less than 35V or more than 70V, the amplifier's output
response becomes non-linear (note the change in gain, Figure 4). For optimum performance, it is recommended that
LM2419's output low voltage beat 25V or above. For a
50 Vpp swing, the output high voltage is 75V. With an output
signal swing from 25V to 75V, LM2419~s linearity error is
measured at 8%.

REDUCING OVERSHOOT.
LM2419's overshoot is a function of both the input signal
rise· and fall times and the capacitive loading. The overshoot
is increased by either more capacitive loading or faster rise
and fall times of the input signal.
Table I shows the overshoot for a typical device with different capacitive loads and different input signal rise and fall
times. As can be observed from Table I, overshoot is large
for large capacitive loads and faster input sig\1al rise and fall
times. In an actual application, the LM2419 is driven from a
preamplifier with rise and fall times of 3 ns to 7 ns. When
drivel) from LM1203 preamplifier (see. application Circuit,
Figure 6) the overshoot is 10% with 12 pF capacitive load.
The overshoot can be reduced by including a resistor in
series with LM2419's output as in Figure 3. Larger \l.alue
resistors forRl ·and R2 would reduce overshoot but this
also increases the rise and fall times at the output. Frequen,
cy peaking using an inductor in series with the output may
restore the bandwidth.

15.5 .--r--r---r--,r---.-.,-...,--,--,.--r-...,.--,--,
15.4

V

15.3

'>

15.2

II

~ 15~1
~

15

:i
... 14.9

'" 14.8

r~

I

,

I

1

I[

14.7
14.6

t-+-++-+--t-lr-t-+-+-+-t-1l-i

14.5 '---'--'--'--'---'---''----'---'--'--'--'---'---..
20 25 30 35 40 45 50 55 60 65 70 75
VOUT (DC)
TL/H/11442-9

FIGURE 4. Gain vs VOUT (DC), VIN = 100 mVpp

2-156

Application Hints (Continued)
THERMAL CONSIDERATIONS
LM2419's transfer characteristic and power dissipation versus DC input voltage is shown in Figure 5. Power supply
current increases as the input voltage increases, consequently power dissipation increases. For the LM2419, the
worst case power dissipation occurs when a white screen is
displayed on the CRT. Considering a 20% black retrace
time in a 1024 x 768 display resolution application, the average power dissipation for continuous white screen is less
than 4W per channel with 50 Vpp output signal (black level
at 75V and white level at 25V). Although the total power
dissipation is less than 12W for a continuous white screen,
the heat sink should be selected for 13W power dissipation
because of the variation in power dissipation from part to
part.

The LM2419 requires that the package be properly heat
sunk under all operating conditions. Maximum ratings require that the device case temperature be limited to 90"C
maximum. Thus for 50"C maximum ambient temperature
and 13W maximum power dissipation, the thermal resistance of the heat sink should be:
6sa ";; (90-50)'C/13W = 3'C/W
SHORT CIRCUIT PROTECTION
The output of LM2419 is not short circuit protected. Shorting the output to either ground or to V + will destroy the
device. The minimum DC load resistance the LM2419 can
drive without damage is 1.6 k!l to ground or V+. However,
driving a 1.6 k!l load for an extended period of time is not
recommended because of power dissipation considerations. If the LM2419 is used to drive a resistive load then the
load should be 10 kO or greater.

For thermal and gain linearity considerations, the output low
voltage (white level) should be maintained above 20V. If the
device is operated at an output low voltage below 20V, the
power dissipation might exceed 4.7W per channel (i.e., 14W
power dissipation for the device). Note that the device can
be operated at lower power by reducing the peak to peak
video output voltage to less than 50V and clamping the video black level close to the supply voltage.

RGB Video Application
A complete video section for an RGB CRT monitor is shown
in Figure 6. The LM1203 video preamplifier and the LM2419
include almost all the circuitry required between the video
input connection and the CRT's cathodes. However, an externally generated back porch clamp signal is required to
accomplish DC restoration of the video signal.
Figure 6 's circuit is excellent choice for a non-interlaced
1024 x 768 display resolution application. With 50 Vpp output swing and 12 pFload, the rise/fall time for Figure 6 's
circuit was measured at 7.5 ns. In this application, feedback
is local to the LM1203. For detailed information on the
LM 1203, please refer to the LM 1203 data sheet.

90
80
70
60

~ 50
>-

:::>

~

""

40
30

0

""

5W

POWER

r"\..
~

20
10

vour

I-"'"

V

JII'

"

I"

~~

o4W

~

PC BOARD LAYOUT CONSIDERATIONS

3W

For optimum performance, adequate ground plane, isolation
between channels, good supply bypassing and minimizing
unwanted feedback are necessary. Moreover, the length of
the signal trace from the preamplifier to the LM2419 and
from the LM2419 to the cathode should be as short as is
practical. The following book is highly recommended:
Ott, Henry W, Noise Reduction Techniques in Electronic
Systems, John Wiley & Sons, New York, 1976.

2W
~

1W

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
VIN (v)
TL/H/11442-10

FIGURE 5. VOUT and Power Dissipation vs VIN

2-157

...
~

~r-~------------------------------------

__

--------------------~

Application Hints (Continued)

.
0.1 j.F

,

,...
TV+
+12V '

~ ,1-.....
1·;,:;.:.:'-"::'\J~~~~~::,~---, +
,L

*"

28

"V,:iL 2
fJ~

3

10k'"
'
IIF

~~ . I RED
:~~ CUTOFF

0.1 IIF

r--\ f--

V .

DRIVE

500

~~~~'1~+~~---------i4
VIDEO
IN

R~~

511l.r
~ 33pr ,IPOll~7

II

IOIlF

100 IIF

5

~7

75

~~~~1~+~~~-------i6
II

VIDEO
IN

75
LM2419

500

E+-

10k

~~'0

I

GREEN
CUTOFF

~7
5111

10

IIF~, r--,-----I

+

11
12,

CONTRAST
, CONTROL

E~

V

16'

13

O.OII1 F

max

17

"

'...-1-

14

E+--

'

15

...... 1

~7

BLUE'
CUTOFF

500

min ~ ~ 0.1 IIF

~7 ~

,75

10
~ 10k

-~

BLACK LEVEL
GATE IN

10k
~. 10k

BLACK LEVEL
(BRIGHTNESS)
CONTROL

E........
~7 ~O.II1F

11

1000 pF

_Ln---j~
-

100V

-

+80V
TL/HI11442-11

FIGURE 6. Typical VGAlSVGA Application

2·158

:a-

+80

"0

"2-

n'

!.
O·
:l
:c

+LJ,
+12

R22
22

-

01

S·

Mr-Rl

R13
390

RED

02

( I)

l'

VIDEO
INPUT

GREEN
VIDEO

INPUT

r

R3

C6

33

10~~

~

L
M
2
4
1
9

R4
75

"ffi

S:

+12

-=

+80

R14
10

~

R24
22

R15
390

'"
co

03*

R25
33

IGREEN I

04

Ir~~10~~
C8

BLUE
VIDEO
INPUT

R6
75

+12

Ii

+80

+4

ICONTRASTR7

I
10

~I-----,

R,2,6

05"

R27
R32;

r;;;";;';'1E

~~
06

10k

.

I BLANK 10------:"-:--::-.
R9
10k

I CLAMP 10

I
...

,~

I BLUE
~IVE

R21
10k

TLlH/11442-12

Diodes FDH400
Unmarked capacitors 0.1 /LF

FIGURE 7. Typical SVGAlXGA Application

----.

6~t~I\I1

~

N

~

r----------------------------------------------------------------------------,
ttlNational Semiconductor

LM2427
Triple 80 MHz CRT Driver
General Description

Features

The LM2427 is a high performance triple CRT driver for
simplifying color monitor designs. The device contains three
large signal transimpedance amplifiers, and provides direct
cathode drive capability. A plastic power package and pinto-pin compatibility make the LM2427 ideal for new designs
or as a low cost replacement for designs using the LH2426
or CR5527.

•
•
•
•

Low-cost plastic power package
Typical rise/fall times of 3.5 ns
80 MHz video bandwidth at 50 Vpp with 8 pF load
Operation from 80V power supply

Applications
• CRT driver for color monitors
• Drives CRT cathode directly
• Pin-to-pin compatible with the LH2426 and CR5527
CRT drivers

Schematic and Connection Diagrams
(One Section)
r---~------~--~~----._--OV+

1,5,9
R5

R6

12 Vour 3
11 GND 3

0

10 VIN 3

9
03

V+ 3
Your 2

R4

GND 2
VIN 2
R11

V+ 2
Your 1

Your
4,8,12
Cl

3

0

2

0
04

1

GND 1
VIN 1
V+ 1

Pin 1 Designator
TLJH/11967-2

Top View

VIN o---I~..,..""'+-I
2,6,10

Rl

Order Number LM2427T
See NS Package Number MKT-TA12A
R9

'------4.----.....----...._-0 GND
3,7,11
TL/H/11967-1

2-160

,-----------------------------------------------------------------------------, r
i:
PI)

Absolute Maximum Ratings

Storage Temperature Range, TSTG
Operating Temperature Range, TCASE
Lead Temperature (Soldering, 10 sec.)
ESD Tolerance

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V +
+ 85V
Safe Operating Power Consumption
14W

- 25'C to + 100'C
-20'Cto +90'C
300'C
TBD

Electrical Characteristics V + = 80V, RG = 4300, Cl = 47 pF, CL = 8 pF, 50 Vpp output swing with 40V DC
offset. See Figure 1. TCASE = 25'C unless otherwise noted.
Parameter

Symbol

LM2427

Conditions
Min

Supply Current (per Amplifier)

Icc

No Input or Output Load

Units

Typical

Max

24

30

rnA

VINDC

Input Offset Voltage

1.4

1.6·

1.8

V

VOUTDC

Output Offset Voltage

34

40

46

V

tR

Rise Time

10% to 90% (Note 1)

3.5

ns

tF

Fall Time

90% to 10% (Note 1)

3.5

ns

Av

Voltage Gain

LE

Linearity Error

VOUTfrom +10Vto +70V(Note2)

t:..Av

Gain Matching

(Note 3)

-11

-13

-14

VIV

5

%

0.2

dB

Nole 1: Inpul signal: t" tf < 1.5 ns, fin ~ 1 MHz.
Nol. 2: Linearity error is defined as: The variation in small signal gain from + 20V to + 70V output with a 100 mVAC, 1 MHz, input signal.
Note 3: Calculated value from voltage gain test on each channel.

Typical Performance Characteristics
Typical Test Circuit (One Section)

Pulse
Generator

Cl

+80Y

O'O~l~J"F r.417,:-JPF

~

IL.

~'5'9
2,6,10

0.47J"F
.

Rc
430n

4950n 0.01 J"F

L..
2.27~4.:.:,8:!.,:.:12'+--'W'lr__I~1
m ~
~
T

~
~'7'11

Y
toOUT
son Scope

-'ICL

_
TLlH/11967-3

Note: ell total load capacitance, includes all parasitic capacitances.

FIGURE 1. Test Circuit (One Section)
This test circuit Is used for both characteristic plots.

Typical Rise Time vs Capacitive Loading
5.0,---,.---,-----,r--,---,----,

Typical Fall Time vs Capacitive Loading
5.0,---...,-----,--,---,---,.-----,

4.5 1----+---1--+--+---+ 50Ypp

4.51----+--+--+---+--+---l

g

4.0

;::

~

3.5

"

3.0

0

"'

2.5
2.0

-~

-5

8

11

13

11

Capacitive Load (pFJ

13

Capacitive Load (pF)

TL/H/11967-10

TL/H/11967-5

2-161

~
PI)

.....

~ r-----------------------------------------------------------------------------------------~

N

~

::e
....I

Bypassing the resistor"with a ,capacitor of /lbouj 17 pF,)NiII
restore the rise and fall times but will' result in some' overshoot. (Figure 2b)

Test Circuit
Figure 1 shows a typical test circuit for evaluation of the
LM2427. This circuit is designed ,to allow testing o,f the
LM2427 in a 50n environment, such as a pulse generator,
oscilloscope or network analyzer. The 4950n resistor in series with the output of the LM2427 forms a 100:1 voltage
divider when connected to a 50n-input oscilloscope or network analyzer. To calibrate pulse generator, set to 2.4 Vpp
into 50n.

Adding a resistor in ser'ies with,the 47 pF capacitor will reduce the overshoot but also increases the rise and fall
times. (Figure 2c)

THEORY OF OPERATION
The LM2427 is a triple channel transimpedance amplifier for
CRT's, suitable for SVGA, XGA, IBM and Macintosh display
resolution monitors. The LM2427 is pin-to-pin compatible
with the LH2426 and CR5527 CRT drivers. The device is
packaged in the industry standard 12-lead SIP TO-220
molded plastic power package. The heat sink is electrically
isolated and may be grounded for ease of manufacturing
and RFI/EMI shielding.
Applying an input current to t'he LM2427 will result in an
output voltage. An input current of about ± 4.5 mA will provide a full output swing of ± 25V. A resistor in series with the
input converts the device into a voltage amplifier; with a
resistor value of 430n the voltage gain becomes -1~.
The LM2427 is a two stage amplifier configured in a push- '
pull configuration' (see schematic on front page). 02 is biased by resistors R4 and R5, 01 gets its bias through a
5700n feedback resistor and the input biasing current. The
bases of 01 and 02 are capacitively coupled and, therefore,
02 will be actively driven.
The emitter resistors of 01 and 02 are bypassed with small
capacitors. This increases the gain of the stage for high
frequencies and increases the bandwidth of the amplifier.
Emitter followers 03 and 04 isolate the input stage from the
output capaCitance load, and minimizes the circuit sensitivity
to load capaCitance.
The power supply pin is intemally bypassed. If low frequencies are present in the power supply line, an electrolytic
capaCitor is recommended.

The addition of a second capacitor offers a compromise
between the above networks by improving the rise and fall
times at the expense of some ove!$hoot. (Figure 2d)
Suggested values ' for the' resistorS and capaCitors are
shown, however, optimum values may 'differ depending
upon the stray inductances and capacitances present in different board layouts.

b

65V Hh~~~:;:-=iiIIIII-----

15VL---~--~---L--~----L---~

TINE (ns)

430.0

a)

47 pF

b)

~
430.0

Application Hints
The LM2427 is designed as a triple power amplifief for delivering red, green, and blue video Signals to a cathode ray
tube (CRn. It can provide a 50V output swing and energize
a 12 ns pixel at a CRT cathode with 8 pF of capacitance.
As with any CRT driver, when designing a video amplifier
board with the LM2427, careful attention should be paid at
reducing stray capaCitance along the entire video Signal
path. This is especially important in tM path between the
output of the CRT driver and the cathodes, because any
additional capacitance load will increase rise and fall times
and will result in reduced picture quality.

0)

0

c~
430.0
30.0

47 pF

d)
430.0

INPUT NETWORKS
The voltage gain and the response of the amplifiers can be
set by adding an R-C network to the input.
A 430n resistor in series with the input will set the voltage
gain to -13, but this will increase the rise and fall times of
the system (see Figure 2a).

TUH/11967-6

FIGURE 2. Influence of Input Networks
on Switching Performance

2-162

r-----------------------------------------------------------------------------,
Application Hints (Continued)

N

TILT AND OVERSHOOT COMPENSATION

PROTECTING AMPLIFIER OUTPUT
FROM TUBE ARCING
During normal CRT operation, internal arcing may occasionally occur. Spark gap protectors will limit the maximum voltage, but to a value that is much higher than allowable on the
LM2427. This fast, high voltage, high energy pulse can damage the LM2427 output stage. The addition of two current
limiting resistors of 500 to 1000 total, and clamping diodes
01 and 02, will provide protection but will slow down the
response. The diodes should have a fast transient response, high peak current rating, low series impedance and
low shunt capacitance. FDH400 or equivalent diodes are
recommended. Adding a series peaking inductor of 100 nH
to 150 nH will restore the bandwidth and provide additional
protection. (See Figure 5)

When a low frequency square is displayed on a monitor
screen, some tilt may appear on the video signal due to the
large power and thermal dissipation changes in the input
transistors. This problem is illustrated in Figure 3.

T

Video signal

.m

r-

The value of the inductor can be calculated from:
(Ro + Rt + R21 2 C
Lp =
L
2.4

Smear caused by tilt

.V"

where CL is the total load and Ro is the intrinsic high frequency output resistance of the amplifier, generally 1600.

(Brighter than
background)

..11'"'"

.:,:,.

01 R2

> ....WIr"""....-'vVv....ryy,..,.... OUT

IN>.......,.,.,~~-I

Screen

02

TL/H/11967-7

FIGURE 3. Tilt on a Low Frequency
Signal and Its Effects
The tilt can be compensated by adding an external RC feedback network as shown in Figure 4. The RC feedback helps
by reducing the gain of the amplifier during the edge transition for a duration corresponding to r. The values of Rand
C should be selected so that the gain is reduced (.6.V = 0)
for the duration of the tilt (r).

TLlH/11967-9

FIGURE 5. One Section of the LM2427
with Tilt Compensation, Arc Protection
and Peaking Inductance lp in the Output
SHORT CIRCUIT PROTECTION
WARNINGI
To provide maximum output speed, the LM2427 does not
have short circuit protection. Shorting the output can destroy the device.

c

·---Rr----·

SUPPLY BYPASSING

._------_.

r
i!:

Although the LM2427 has internal supply bypassing, some
values of supply line inductance can cause ringing in the
supply lines. If this occurs, an additional bypass capacitor or
a low-pass filter should be placed as close as possible to
the supply (V+) pins of the LM2427.

TLlH/11967-B

FIGURE 4. RC Feedback Network for Tilt Compensation

CAPACITIVE LOADS

To find the value of resistor R, the following formula can be
used:
(100 - x%)
R=
x%
RF

The LM2427 is designed to drive capacitive loads, however,
the very high output slew rate of about 13,700 VI JJ-s can
result in charging currents of over 200 mA into a 20 pF load.
These very high currents can damage the output transistors.

where x% is the percentage value of .6. V to the peak-topeak output swing (Vpp). RF is internally fixed to 57000.
The value of capacitor C is determined by:

HEAT SINKING
Power consumption by the LM2427 will depend on the supply voltage used, the output loading, the peak-to-peak output swing and the operating frequency. Since the LM2427
will dissipate up to 14W, an external heatsink is always required. The maximum allowed case temperature is 90'C. To
calculate maximum heatsink thermal resistance, use the following formula:

C = r/R
where r is the duration of the tilt.
For optimum results in a specific application, the values for
Rand C may need to be tested and adjusted in the given
application board.

R
th

2-163

= (90'C - Max Ambient)
14
.

"'N......"

r-.

~
::E
...I

r---------------------------------------------------------------------------------,
PC BOARD LAYOUT CONSIDERATIONS
Input pins 2, 6 and 10 are amplifier ,summing junctions. All
connections to these points should be as short as possible
and should be separated from other signals. The com'ponents connected to these pins should be located close to
the LM2427, and the total conductor length connected to
these points should be no more than one inch.
For optimum performance, an adequate ground plane, isolation between channels, good supply bypassing and minimizing unwanted feedback are necessary. Also, the length of
the signal traces from the preamplifier to the LM2427 and
from the LM242i to the CRT cathode should be as short as
possible. The following references 'are recommended:
Ott, Henry W., "Noise Reduction Techniques in Electronic
Systems': John Wiley & Sons, New York, 1976.
"Guide to CRT Video Design': National Semiconductor Application Note 861.

2-164

r-----------------------------------------------------------------------~r

:s:::
PRELIMINARY .....
~
.....

f}1National Semiconductor

LM1291
Video PLL System for Continuous Sync Monitors
General Description

Features

The LM1291 is an integrated horizontal time base solution
specifically designed to operate in continuous sync video
monitors. It accepts all presently defined computer sync signals and generates the drive signal for a horizontal (line)
output stage. The system automatically selects the active
input based on the following -(highest to lowest) priority: (1)
separate H and V sync, (2) HV (composite) sync, and (3)
composite video. Polarity-corrected H/HV and V sync outputs are provided, along with logic flags which show the
respective input polarities.

• VCO precision trimmed on chip-no trimming or loop
tuning required
• No costly high-precision components needed
• Low phase jitter (1.3 ns at 100 kHz)
• DC controlled H phase and duty cycle
• Frequency agile-30 kHz to 125 kHz with no external
adjustment
• Video mute signal indicates changes in H input
frequency
• Input signal prioritization
• Clamp pulse position and width control
• Clamp pulse continues in absence of H sync
• Resistor-programmable minimum and maximum VCO
frequency
• X-ray shutdown input
• Under-voltage lockout for Vee < 9.5V
• Horizontal output transistor forced off during flyback
pulse

The IC contains an FVC (frequency-to-voltage convertor)
which sets the free-running frequency of the VCO (voltagecontrolled oscillator). This technique allows operation over
the entire frequency range, 30 kHz-125 kHz, using just one
optimized set of external components.
A second phase detector is included which compensates
for storage time variation in the horizontal output transistor;
the picture's horizontal position is thus independent of temperature and component variance.
The LM1291 provides DC control pins for H Drive duty cycle
and H Drive phase.

Applications
• Horizontal and vertical sync processor for continuous
sync monitors
• Wide frequency range phase-locked loop

Connection Diagram
'-./

CLAMP CNTL -

1

CLAMP PULSE -

2

V1DEO MUTE -

3

26 -FVC CAPI

F MAX- 4

25 -FVC CAP2

F MIN- 5

24 - v CAP

28 -VCO IN/POI OUT
27 -FVC OUT

VREF CAP- 6
VCC -

23 - H DRIVE PHASE
22 -PHASE DET 2 CAP

7

V SYNC IN- 8
CaMP VIDEO IN -

•

21 -GND
20 -H DRIVE OUT

9

19 - v POL OUT

H/HV CAP- 10

18 -FLYBACK IN

H/HV SYNC OUT- 11
H/HV SYNC IN- 12

17 -V SYNC OUT

H/HV POL OUT- 13

16 -X-RAY SHUTDOWN

H DR DUTY CNTL- 14

15 -H DRIVE

EN
TL/H/12323-1

FIGURE 1
Order Number LM1291N
See NS Package Number N28B

2-165

Absolute Maximum Ratings

(Notes 1 & 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
14V
Supply Voltage
Input Voltage, Voe
Pins 15,23
Pins 4, 5
PinsS,2S
Pins 1, 9, 12, 14, 16, 1S

Junction Temperature (TJ)

- 65'C to + 150'C

Lead Temperature (Soldering, 10 sec.)

5V
SV
10V
Vee
2.5W

Power Dissipation (Po)
(Above 25'C Derate Based on (}JA and T J)
Thermal Resistance «(}JAl

150"C
2kV

ESD Susceptibility (Note 5)
Storage Temperature

265'C

Operating Ratings (Note 2)
Operating Temperature Range
Supply Voltage (Vee)

-20"Cto +SO"C
10.SV ~ Vee ~ 13.2V

50"C/W

Electrical Characteristics See Test Circuit (Figure 2); TA =
Conditions

Parameter
Supply Current
Jitter

H Sync frequency = 100 kHz
(NoteS)

Minimum composite video
input voltage

Pin 9, cap coupled (0.01 ,..F),
sync tip to black level

DC clamp level, composite
video input
Clamp charging current,
composite video input

25'C; Vee = 12V
Typical
(Note 6)

Limit
(Note 7)

Units

30

40

rnA (max)

1.3

nsp-p
0.14

.Vpp(min)

2.0

Voe

1

rnA

H/HV sync input amplitude

Cap coupled, 10% duty cycle

1.0

Vpp(min)

V sync input amplitude

Cap coupled, 1 % duty cycle

1.0

Vpp(min)

High level output voltage VOH,
(Pins 2, 11, 13, 17, 19)

IOH = -100,..A

4.3

4.0

Voc(min)

Low level output voltage VOL,
(Pins 2,11,13,17,19)

IOL = 1.6mA

0.25

0.4

Voc(max)

Video Mute low level output
voltage

IOL=2mA

0.4

Voe(max)

Mute detection voltage
threshold

AV, IFVCCap 1 - FVC Cap 21
for Mute Output low

100

mV

Flyback input threshold

Positive-going flyback pulse

1.4

V

Under-voltage lockout

Vee below threshold:
H Drive Output open (unlatched)

9.5

V

Frequency to voltage gain

30 kHZ ~ fH ~ 125 kHz

0.047

V/kHz

VCO gain constant

fveo = 100 kHz

1.34 x 105

RadlsN

PDl Phase Detector gain constant

fveo = 100 kHz

130

fveo = 60 kHz

7S.1

fvco = 30kHz

'39.0

Frequency to voltage linearity

30 kHz

~

fH

VCO linearity

30 kHz

~

fvco

~

,..AlRadian

125 kHz

1.0

%.

~

1.0

%

125 kHz

2-166

r-

Electrical Characteristics See Test Circuit (Figure 2); T A =
Parameter

25·C; VCC

=

Typical
(Note 6)

Conditions

Limit
(Note 7)

Units

H Drive duty cycle control
gain

DC input OV-4V; 30%-70%
allowed

0.1

THIV

H Drive Phase control gain

(Note 9)

47

·/V

PD1 Phase detector leakage current

+ VCO input bias current
=

1

IJ-A(max)

H Drive low level output voltage

IOL

100 mA

0.8

V (max)

H Drive EN low level input voltage

H Drive output active

0.8

V (max)

H Drive EN high level input voltage

H Drive output open (unlatched)

2.0

V (min)

X-ray Shutdown threshold voltage

Above threshold
H Drive Output Open (Latched)

1.65
1.8

V (min)
V(max)

H/HV Sync out
propagation delay chang~

H/HV in vs. Comp Video in

Clamp Pulse width

(back porch) RSET
(back porch) RSET
(sync tip) RSET

Clamp Pulse Delay

=

=
=

1.72

15k; VSET
15k; VSET

15k; VSET

=

=
=

32

ns

OV

0.4

IJ-s

1.5V

1.4

IJ-s

0.6

IJ-s

0.1

IJ-s

0.025TH

s

8.2

V

4V

(back porch) Trailing edge H/HV Sync In
to leading edge clamp pulse
(sync tip) Leading edge H/HV Sync In
, to leading edge clamp pulse

Internal Ref voltage at pin 6

No load

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur,

Note 2: Operating Ratings indicate conditions f9r which the device is functional. but do not guarantee specific performance limits, For guaranteed specifications
and test condHions. see the Electrical Characteristics. The guaranteed spec~ications apply only for the test condHions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND. unless othBlWise spec~ied.
Note 4: The maximum power dissipetion \1lust be derated at elevated temperatures and is dictated by TJm... 8JA and the ambient temperature. TA. The maximum
allowable power dissipetion at any elevated temperature is Po = (TJmax - TAll8JA or the number given in the Absolute Maximum Ratings. whichever is lower. For
this device. TJmax = 150"C. The typical thermal resistance (8JAl of these parts when board mounted follow: LM1291N 50"C/W.
Note 5: Human Body model. 100 pFcapacHor discharged through a 1.5 kfi resistor.
Note 6: Typicals are at TA = 'TJ = 25"C and represent most likely perametric norm,
Note 7: Tested limits are guaranteed to'National',s AOQL (Average Outgoing Quality Level).
Note 8: Measured wHh hp 53310A Modulation Domain Analyzer. 50 ms sample window.
Note 9: Phase limits: + ( 0,35 -

t~B ). -0.15. expressed as a fraction of the horizontal period TH. where tOFB is the horizontal output transistor tum·off delay

from the rising edge of H Drive to the FBP peak. A positive phase value represents a phase lead of the FBP peak with reference to the leading edge of H sync.

2-167

....
....~

i:

12V (Continued)

LM1291

C~~~r

I

§)I)-------------<,-·r ""

CLA~P

PULSE

VIDEO

o

_

~

a

15k

~3.6k

lOOk

4.7k

1

~.

I 21

c

~

4.7 nF

(g

22k
r ~IN

•••

~t"l

~UTE

r MAX

1 .:.

+12Y~

VCO/POI OUT
+12V

~

en

+12V

2k

o

I

+

@

@rVCOUT

SL
3ps

REF

V
CAP

Vee
+12V
V SYNC
IN

8:1

lID

1 P'

~

1P'

23

~

V'@OIfDRIVE
,
PHASE

CO~P

VIDEO IN

H/HV SYNC ... ,,'
OUT - -

H/HV SY'ffi

!
V

~

470

+
_

~

~

H DR g~ir

1 ~;:;RIVE

I pF

Iotr
i

L-_ _ _ _ _ _--<@ r~YBACK

[ill

I r+

V SYNC
OUT

L - - - 2 k- - - - I

H/HVb3~@

1-

@ ------------------------.---.~
-

12Y

L _________@

1

@

~HM60wN

H DRIVE
ENABLE

Ik
$BNC

@ ~~~~NA
TLlH/12323-2

FIGURE 2

.-----------------------------------------------------------------'r
....a::::
Block Diagram
~
....
H/HV Cap

H/HV Pol Out H/HV Sync Out
11

V Sync
Out

Comp
Video In

H/HV
Sync In

1 Clamp
......_ _ _
Cntl

12

Clamp
Pulse

rvc

Cap 2

r----------

Video
Nute

H Dr
g~lr

rvc

Cap 1

H Drive
Out

rvc

Out

VCO
In/POI
Out

+--;:=====:--1
28

.-JI"--_

re-,

61
r Min r Max VREr

211
Cap GND

71
Vee

~h~f!
down

23

22

H Drive
Phase

Fly back Phase Det
In
2 Cap
TLlH/12323-3

FIGURE 3

Pin Descriptions
See Figures 4 through 19 for input and output schematics.

F MAX (Pin 4): Maximum VCO Frequency. A resistor to
ground sets the upper limit of the VCO in case of too high H
sync frequency. F MAX is approximately I.B x 109/(RMAX
+ 5000).

CLAMP CNTL (Pin 1): Clamp Control. See CLAMP PULSE
(Pin 2) description. A control voltage of OV to 4V applied to
this pin through a 15k resistor sets the position and width of
the negative-going clamp pulse. A voltage below 2V positions the pulse on the back porch of the horizontal sync
pulse and decreasing voltage narrows the pulse. A voltage
above 2V sets the pulse within the H sync pulse (slightly
delayed from the leading edge) and increasing voltage narrows the pulse. At the boundary of the switchover between
the two modes, there is a narrow region of uncertainty resulting in oscillation, which should be no problem in most
applications. If there is no H Sync and this pin is high, a
clamp pulse will be generated from the VCO. This feature is
useful with On Screen Displays which must display a message in the absence of sync inputs.
Note: The veo frequency goes 10 F MIN in Ihe absence of H sync.

F MIN (Pin 5): Minimum VCO Frequency. A resistor to
ground sets the lower limit of the VCO. This is the frequency
that the VCO goes to in the absence of H sync. F MIN is
approximately 7.5 kHz + 5.6 x 108 /(RMIN + 5000).
VREF CAP (Pin 6): This is the output of the internal bandgap based B.2V reference, which needs bypassing for low
noise. The bypass cap should be connected via a short path
to pin 21 (ground). The path should not be connected to !lny
part of the circuit that has noise currents. The capacitor
should be a minimum of 470 ,...F aluminum or tantalum electrolytic capacitor.
Vee (Pin 7): Vee (12V nominal) should be bypassed to
ground (Pin 21) via a short path with a minimum of 47 ,...F
aluminum or tantalum electrolytic capacitor.

CLAMP PULSE (Pin 2): This output provides a negative-going pulse for DC restoration or clamping in video systems.
The pulse can be pOSitioned coincident with the H sync
pulse or on the back porch. The pulse width can be adjusted
with the clamp control voltage.

V SYNC IN (Pin 8): Vertical Sync Input. V sync can be a
positive or negative going 1.0 Vpp minimum Signal, capacitively coupled with a 1 ,...F (;Ir larger capacitor. The input
resistance is approximately 50k and is biased at 5.2V.
V SYNC IN has priority over composite sync and composite
video. See Figure 6 for the input schematic.

VIDEO MUTE (Pin 3): This "open collector" output goes
low if there is a sudden change in H sync frequency. It can
be used to blank video or for other chores. The rate and
amount of frequency change causing Video Mute is set by
the values of the capacitors at FVC 1 (Pin 26) and FVC 2
(Pin 25). Video Mute is high in the absence of H sync. See
Figure 5 for the output schematic.

COMP VIDEO IN (Pin 9): Composite Video Input. This is the
sync input used for composite video; i.e., sync on green,
and is the default input when no signals are present at
V SYNC IN and H/HV IN. The signal must have negative
going sync tips which are at least 0.14V below black level.
See Figure 7 for the input schematic.

2-169

•

~

~
'P,'"

:I

.------------------------------------------------------------------------------------------,
Pin Descriptions (Continued)
HtHV CAP (Pin 10): Horizontal Capacitor. The H/HV Cap is
the integration cap for the circuit that detects the polarity
and existence of the horizontal sync pulses. A 1 ",F aluminum or tantalum electrolytic capacitor is recommended.
HtHV SYNC OUT (Pin 11):' H/HV Sync Out is the composite sync output. The sync pulses are negative-going with
width equal to the sync input. H/HV Sync Out is a low level , '
in the absence'of H/HV sync input. This output can drive a
standard TTL input and is CMOS compatible. See Figure 4
for the output schematic.

V POL OUT (Pin 19): Vertical Polarity Out is a DC Signal
showing the polarity of the vertical sync input. A low level
';' indicates positive-going sync and a high level negative-go,ing. The output is low in the absence of vertical sync. This
,output can driye (i !!tan(lard TTL output and is compatible
with CMOS. See Figure 9 for the output SChematic.

HtHV SYNC IN (Pin 12): Horizontal or Composite Sync Input. H/HV sync can be a positive or negative-goin!! 1.0 Vpp
minimum sync signal, capacitively coupled with a 0.1 ",F or
larger capacitor. The input resistance is approximately 18k
into a circuit with clamp levels of approximately 1.9V and
2.6V. See Figure 8 for the input schematic. If this input is not
used, the sync input end Of its coupling cap should be connected to ground directly or via a resistor of 4700 or less,
H/HV POL OUT (Pin 13): H/HV Polarity Out is a DC signal
showing the polarity of the H/HV Sync input. A low level
indicates positive-going sync,. a high level negative-going,
The output is low in the absence of H sync. This output can'
drive a standard TTL input and is CMOS compatible. See
Figure 9 for the output schematic.
'
H DRIVE DUTY CNTL (Pin 14): Horizontal Duty Cycle Control. A OV to 4 V control voltage applied to this pin sets the
duty cycle of the horizontal drive output (pin 20), with a
range of approximately 30% to 70%. 2V sets the duty cycle
to 50%. See Figure 10 for the input schematic.•

H ORIVE OUT (Pin 20): Horizontal Drive Out is a negativegoing signal for driving the horizontal deflection system.
H Drive Out is an open collector output capable of sinking
up to 100 mA. Its duty cycle and its phase with respect to
H sync are DC controlled. When the output is low, the horizontal yoke driver is on and when high the driver is off. See
Figure 5 for the output schematic.
GND (Pin 21): System ground. All LM1291 filter components and bypass capaCitors should be connected to this
pin via short paths.
PHASE DET 2 CAP (Pin 22): Phase Detector 2, Cap is the
'filter capaCitor for the circuit that keeps the phase error be'tween the flyback pulse and H Drive Out constant.
H DRIVE PHASE (Pin,23): A control voltage applied to this
pin' sets the phase of the flyback pulse with respect to the
leading edge 'of H sync. See Figure 14 for the input schematic.
V CAP (Pin 24): The Vertical Cap is the integration capaci'tor for the circuit that detects the polarity and existence of
the vertical sync pulses.
FVC CAP 2 (Pin 25): The Frequency to Voltage Converter
CapaCitor 2 is the filter capaCitor for the longer time constant filter for the Video Mute comparator.

H DRIVE EN (Pin 15): Horizontal Drive Enable. This pin
turns the Horizontal Drive Output on and off with a TTL level
signal,with low on and high off. See· Figure 11 for the input
schematic.
"

FVC CAP 1 (Pin 26): The Frequency to Voltage COnverter
CapaCitor 1 is the filter capacitor for the Frequency to Voltage CQl)verter and is also the shorter time. constant filt,er for
the Video Mute comparator. ' ,

X·RAY SHUTDOWN (Pin 16): This pin turns off the Horizontal Drive Output if its voltage equals or exceeds an internal reference of approximately 1.7V. The output is latched
high, and Vee has'to be reduced to below approximately 2V
to clear the latched condition; i.e., power must be turned Off.
This feature provides "X-Ray protection" by checRing CRT
anode,voltage level through a resistive divider from a power
supply. voltage that is proportiQnal to the CRT voltage: See
Figure 12 for the input schematic.

FVC OUT (Pin 2n: The Frequency to Voltage Conver:t.er
Output. is a DC voltage proportional to fr~uency and is
used to'set the free-running frequency of the, Voltage Controlled Oscillator. This signal goes to the VCO input via a
resistor which is part of the PLL, filter. The voltage range is
approximately,O.6V to 6.0V for 15 kHz to 125 kHz. See Figure 15 for: the output schelllatic.
VCO IN/POI OUT (Pin 28): The Voltage Controlled Oscillator input and' Phase Detector 1 output are, connected internally at this pin. The phase locked loop, filter components
are connected here. See Circuit Description for information
about this pin. '

V SYNC OUT (Pin 17): Vertical Sync Out is a negative going
pulse occurring approximately 0.3 horiiontal lines 'after the
beginning of the vertical interval. V Sync Out is a low level in
the absence of vertical sync. V Sync Out width is'thesame
as V Sync In, and is 3to 5 lines longer fOr H/HV Sync Inand
Comp Video In. This output can drive a standard TTL input
and is compatible with CMOS. See Figure·4, for the output
schel)1atic.
FLYBACK IN (Pin 18): This is a positive-going pulseirom
the horizontal def!ection circuit thaI is compared,to the VCO
phase in phase detector 2, whose output is used to control
the phase of Horizontal Drive Out. This compensates for
time delay changes in the horizontal deflection circuitry"with
temperature, etc. to keep the display position CQnstant. See
Figure 13 for the inputsche,rnatic. '
",

2-170

Input/Output Schematics
Vee -.--4---,
40k
4.3V

-1.-,.........-;
TUH/12323-5

FIGURES
700

I...----+-oU
CLAMP PULSE
H/HV OUT
V SYNC OUT

TL/H/12323-4

FIGURE 4
S.2V

V SYNC
IN

Ok
~

+2V

~,~~b 0--.....- -.....1-----1

TL/H/12323-6

IN

FIGURE 6

~

i

TL/H/12323-7

FIGURE 7

2.6V

H/HV
SYNC

lr-.-..___....

4.3V-t......

k
'8V
_....,.jV

IN

H/HV POL OUT
V POL OUT
L9V

TUH/12323-8

FIGURE 8

TUH/12323-9

FIGURE 9

2-171

•

y-

~
y-

~

r------------------------------------------------------------------------------------------,
Input/Output Schematics (Continued)
H DRIVE
DUTY CNTL
H DRIVE

SOk

EN

1.4V

SOk
TVH/I2323-11

FIGURE 11
TL/H/I2323-10

FIGURE 10
r--+--W~

Vee
1.5V

10k
10k
1--I~HM......~rw-o X-RAY
SHUT

1.8V

TL/H/I2323-13

FIGURE 13

OOWN

TVH/I2323-12

FIGURE 12

H DRIVE
PHASE

lk

TVH/12323-14

FIGURE 14

FVC
OUT

TVH/12323-15

FIGURE 15

2-172

:J
"0
CLAMP CNTL

CLAMP PULSE

~~E~12~~

VIDig ~g~6
BLANKING
VCC
+12V

~.

15k

ORF~~Mpg~~

w..~-----~

~

"0

":2S
~"' !

+------------.,

II
_+-__..,

• ,..

V SYNC IN

"2-

~.

o::l·

,
+12V

H DRIVE
PHASE
FROM DAC

220

lW

f2ji)

v

,~O D~~VRlzOUT
~~

.

~

(j

r

H/HV SYNC 4
OUT

H/HV

.!L

htJ

I

......._ -.....

~ rl~F
r--

L..._ _ _....._

SY~2 @~,-------

+----------'

~~6~A~~~,~
DEFL

75

H/HV b3~
TO ~P PORT

¥OP~~ ~~llT

L.._ _ _ _ _- .

L.._ _ _ _ _ _~-

10k

¥O SJr~T °OU;C

~Hn~60WN

~+12V

TLlH/I2323-16

FIGURE 16

~6~~W'

II

~ ~---------------------------------------------------------------------,

fQ

~

tJ1

'PRELIMINARY, '

Nat i on a I S e m i con due tor

LM1295
DC Controlled Geometry Correction System
for Continuous Sync Monitors
General Description

Features

The LM1295 is specifically designed for use in a continuous
sync monitor. The injection-locked vertical oscillator operates from 50 Hz to 100 Hz. covering all known video monitors. A differential output current is provided in order to prevent ground interaction.

•
•
•
•
•

The IC provides two outputs composed of the summation of
DC controlled 1st and 2nd order output terms. The first output corrects for EW pincushion and trapezoid. The second
corrects for parallelogram and bow.
A DC controlled output is provided for vertical dynamic ,focus correction.
The IC is packaged in a 24-pin narrow DIP packl:\ge and
operates on a single 12\1 power supply. '
'

Vertical "scanning frequency 50 Hz-100 Hz
DC ~ntrolled correction term amplitudes
Up to 125 kHz bandwidth for dynamic input signals
'Minimum extemal parts count
Multiple IC connection for convergence applications
flexibility
• 1 % vertical amplitude stability over temperature
• Compatible with the LM1291 HoriZOntal PLL in a
HIV system
• Dynamic vertical deflection correction for second anode
high voltage drop

• Both positive .and negative going correction signals

Connection Diagram
GND- 1

24 ~+v DRIVE

V HEIGHT- 2

23 ~-v DRIYE
22 ~RYERT

4Y'CAP- 3
V SYNC IN';" 4

21 I-RYERT

8Y'CAP- 5

20 I- OSC CAP,

V DYN HEIGHT -

6

191-21 CAP

Ycc -

7

18 I-ALC CAP

VREF CAP- 8
H DYN WIDTH -

17 I-GND
~6 ~Y DYf'! FOCUS

9

E-W PIN CNTL- 10

15 I-v DYN FOCUS CNTL

H TRAP CNTL- 1,.

14 I-H DYN CNTR

H PARA CNTL- 12

131-H BOW CNTL
" TUH/12324-1

FIGURE 1

Order Number LM12!15N
NS 'Package Number N24C

S~

2-174.

r-

!!II:
.....

Absolute Maximum Ratings (Notes 1 and 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

5Vpp

Power Dissipation (Note 4)
(Above 25·C Derate Based on IJJA and TJ)

1.8W

Thermal Resistance (IJJA)

1.8kV
-65·Cto

265·C

Operating Ratings (Note 2)
-20·Cto +80"C

Operating Temperature Range
Supply Voltage 
Input Voltage
(DC, pins 2, 6,10,11,12,13,15)

70"C/W

10.8V

s:

Electrical Characteristics SeeTestCircuit(F,gure2);TA =
Parameter

Icc

Supply Current

Vref

Internal ref voltage at pin 8

Rin

Input resistance

Ffr

Free-run frequency

Vee

s:

13.2V
4V

Input Voltage
(AC, pin 4)

Symbol

+ 150·C

Lead Temperature (Soldering, 10 sec.)

5V

Input Voltage (AC, Pin 4)

150"C

ESD Susceptibility (Note 5)
Storage Temperature

14V

Input Voltage
(DC, pins 1, 2, 6,10,11,12,13,15)

Junction Temperature (TJ)

4Vpp

25·C;Vee = 12V.

Conditions
All Control Inputs = 3V

Typical
(Note 6)

Limit
(Note 7)

Units

25

35

mA(max)

30

kO(min)

8.2
Pins6,1'O-13,15

50

V

Hz

45

Fmax

Maximum frequency

Cntlbw

Control inputs bandwidth

Pins6,10-13,15

100

Hz

125

kHz

Vhts

Vertical height temperature
stability

V Height = 4V, V Dyn Height = 3V,
TA = O"Cto 70"C (Note 10)

1

%

Vdiff

Vertical differential output
current

V Height = 4V, V Dyn Height = 4V,
Pin 24 minus Pin 23

Vsynh
Vsynl

V sync high.input voltage
V sync low input voltage

Vcmrr

Vertical output CMRR

Vo = 1V to 4V, V Height = 2V,
V DynHeight = 3V

30

dB

Vpssr

Vertical output PSSR

Vcc = 10.8Vto 13.2V, V Height = 2V,
V Dyn Height = 3V

30

dB

1

mA(min)

2.4
0.8

V (min)
V (max)

Vertical peak output voltage

RL = 10k

6

Vertical ramp distortion

(Note 8) V Height = 4V,
V Dyn Height = 3V

1

%

Vsoerr

Vertical parabola distortion

(Note 9) V Height = 2.2V,
V Dyn Height = 3V

8

%

CRfo

First order (ramp) correction,
H Dyn Cntr (pin 14)

Pin 12 = OV
Pin 12 = 4V
V Dyn Height = 3V, V Height = 4V,
parabola nulled

2.50
2.25

Vpp

CRfo

First order (ramp) correction,
H Dyn Width (pin 9)

Pin11 = OV
Pin 11 = 4V
V Dyn Height = 3V, V Height = 4V,
parabola nulled

0.85
0.75

Vpp

2-175

5

Vpp (min)

Vop-p
Vrerr

~

CII

Electrical Characteristics See Test Circuit (Figure 2);TA = 25°C;, Vee =
Symbol

CPso

Parameter

Limit','
(Note 7)

Typlca!
(Note 6)

Conditions

Pins 10, 13, 15 = OV
Pins 10, 13, 15 = 4V
V Dyn Height = 3V, V Height
ramp nulled for H Dyn Cntr
and H Dyn Width

Parabola correction range,
H Dyn Cntr (pin 14),
H Dyn Width (pin 9),
,V Dyn Focus (pin 16)

12V. (Continued)
Units

1.2
1.0

Vpp

= 4V,

Vodc

Output DC bias

Pins 9, ,14 and 16; all control
inputs at 2.2V

4.0

Voc

10

Output current

Pins 9,14 and 16

5.0

mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damsge to the device may occur.
Note 2: Operating Ratings indicate condRions for which the device is functional, but do not guarantee specific performance IimRs. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device Is not operated under,the listed test conditions.
Note 3: All voRages are measured with respect to GND, unless otherwise specified.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax. (JJA and the ambient temperature, TAo The maximum

allowable power dissipation at any temperature is Po ~ (TJmax - TAll8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device. TJmax ~ 150"C. The typical thermal resistance (8JAl of these parts when board mounted follow: LM1295N 70"C/W.
Note 5: Human body model, 100 pF capacitor discharged through a 1.5 kO resistor.
Note 6: Typicals are at TA

~

TJ

~

25'C and represent most likely parametric norm.

Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Nota 8: The deviation from a straight line drawn through measured points at 5% and 95% of the ramp is used to calculate distortion.
Distortion ~ 100 (deviation. volts)/(95% value - 5% value, volts). Deviations are measured at y, and % of the ramp time,penod.
Note 9: The deviation from 'a theoretical parabola drawn through the apex of the actual parabola is used to calculate distortion.
Distortion ~ 100 (deviation, volts)/(theoreflcal parabola, voRs) at measuring point. Nine points are measured.
Nota 10: The amplitude stabilRy varsus temperature is typically 1% or less when a standard 10k 5% Y.W carbon film resistor is connected between pins 21 and 22
and located close to the package. The negative temperature coefficient of the resistor corrects for the negative temperature coefficient of the LM1295. The typical
amplitude stability of the LM129~ by itseij is 2%.

Test Circuit
+12V

r---i~)+V DRIVE

1Dl1---...-----+O J-V DRIVE
VSYNCIN(O~---------~--~GD

V DYN
HEIGHT
+12V

~lg~~(O~+----------~rn

l i ] ] i - - - - - - - - o f o ) V DYN FOCUS

1rni-----i---ofo)H

E-W PIN
CNTL

DYN CNTR

H TRAP
CNTL
H BOW CNTL

H PARA
CNTL

V DYN FOCUS
CNTL

TUH/12324-2

FIGURE 2

2·176

Typical Performance Characteristics
TA = 25°C, F = 100 Hz, VHeight = 4V, VDynHeight = 3V, Test Circuit-Figure 2

H Dyn Width Output (Pin 9)

H Dyn Width Output (Pin 9)

6.5 V ,.--"':--r-...,--r-...".."-r-'r......,-;"'r--I
Pin 10=OV
Pin 11 = OV

6.5 V ,.---r--r-...,--r-..."..-'-r--;'......,""':"'r--I
Pin 10=OV
Pin 11 = 4V

500mV

500mV

Idiv

Idiv

trig'd

trig'd

1. 5 V '--.L-"--"--'-'%--'--'--'--'---'
-9.16 ms
2 ms/div
10.84 ms

1. 5V '--.L-"--"--'-.%--'--'--'--'---'
-9.16 ms
2 ms/div
10.84ms

H Dyn Width Output (Pin 9)

H Dyn Width Output (Pin 9)
6.5 V ,.--"':--r--r--r-..."..';""''''''':''......,'''':'''r-'!
Pin 10 = 4V
Pin 11 = OV

6.5 V ,-r-r--r--r-..."..":"""--i-......,--',r-'!
Pin 10 = 4V
Pin 11 = 4V

500mV

500mV

Idiv

Idiv

trig'd

trig'd

1. 5V '--"---'--'-...J....~--'----L---L--J'--'
-9.16 ms
10.84 ms
2 ms/div

1. 5 V '--"---'--'-...J....~--'----L---L--J--'
-9.16 ms
10.84 ms
2 ms/div

H Dyn Ctr Output (Pin 14)

H Dyn Ctr Output (Pin 14)

6.5V ,-.-.--r--r-...".."""'"""T"""'-r-'!
Pin 12=OV
Pin 13=4V

6.5V ,-.-.-..,--r-...".."""'"""T--r-..--,
Pin 12 = 4V
Pin 13=4V

500mV

500mV

Idiv

Idiv

trig'd

trig'd

I

1. 5 V '--"---'--'--'--Z..---L---L---L_'--'
-9.16 ms
2 ms/div
10.84 ms

1.5 V '--"---'--'-...J....~--'----L---L--J'--'
-9.16mo
10.84 mo
2 mo/div

TlIH/12324-10

2-177

II

Typical Performance Characteristics
TA = 25°C,

6.S\(

(Continued)

= 4V, VDynHeight = 3V, TestCircuit~Flgure2

F = 100 Hz, VHeight

H Dyn Cntr Output (Pin 14)

6.SV

,

H Dyn Cnt~putput(Pln14)

Pin 12=OV
Pin 13 = OV

Pin 12=4V
Pin 13 = OV

sao mV
Idiv

SOOmV
Idiv

trig'd

trig'd

1. SV L..-.1-...L...-'--'-....L....J..--l.--,-I_L.......J
-9.16 ms
2 ms/div
'. 10.84 ms

1.5 V L..-J.......J-...L.......L.......L...J...--l.---L---JL.......J
-9.16 ms
2 ms/div
10.84ms

V Dyn Focus Output (Pin 16)

6.SV

V Dyn Focus Output (Pin 16)

r-,...:-,--,-,-..,.,..."r--r--,---r-..,

6.SV

Pin lS=OV

Pin IS = 4V

SOOmV
Idiv

SOOmV
Idiv

trig'd

trig'd

1. S V L..-.1-...L,--'--'-....L....J..--l.....,.J_L.......J
-9.16 ms
2 ms/div
10.84 ms

1. SV L..-J.......J-...L.......L.......L...J...--l.---L---JL.......J
-9.16 ms
10.84 ms
2 ms/div

+ V Drive Output (Pin 24)

- V Drive Output (Pin 23)

8Vr-,--~,-~~~~~-~

8Vr-,--,-~~~~~~~~

IV
Idiv

IV
Idiv

trig'd

trig'd

_2VL..-.1-...L...-'--'-....L...J...--l.---L---JL.......J
-7.96 ms
12.04 ms
2 ms/div

_2V~.1-...L...-'--'-....L....J..--l.~_L.......J

-7.96 ms

2 ms/div

12.04 ms
TUH/12324-11

2-178

Circuit Description
(See Figure 3, Block Diagram)

multipliers used· as voltage controlled amplifiers, one for
horizontal trapezoid correction and the other for horizontal
parallelogram correction.

The LM1295 has outputs which provide signals for correcting the following CRT distortions: Vertical de-focusing, EaslWest pincushion, horizontal trapezoid, horizontal parallelogram and horizontal bow. The amount and polarity of the
corrections are controlled by voltages between OV and 4V.
The corrections track the vertical output amplitude.

PARABOLIC FUNCTION GENERATOR
The parabolic function generator makes a parabolic waveform from the vertical ramp. Its output goes to three multipliers used as voltage controlled amplifiers, one each for
V Dyn Focus, E-W Pin, and H Bow.

The LM1295 has five major sections: the vertical oscillatorl
amplifier, the parabolic function generator and three voltage-controlled channels with the correction term outputs.

VOLTAGE CONTROLLED AMPLIFIERS
The V Dyn Focus voltage controlled amplifier is controlled
by the V Dyn Focus Cntl input. Its output goes to an op amp
whose output is V Dyn Focus. The voltage controlled amplifier has zero gain at approx. 2V input, maximum positive
gain at 4V, and maximum negative gain at OV. The E-W Pin,
H Bow, H Trap and H Para voltage controlled amplifiers are
identical to the V Dyn Focus stage, each adjusted by its
corresponding Cntl input. The bandwidth of the Cntl inputs
is greater than 125 kHz. The E-W Pin and H Bow amplifiers
have the parabolic waveform as their input, and the H Trap
and H Para amplifiers have the vertical ramp as their input.
The parabolic waveform and the ramp amplitudes track the
vertical output amplitude so the correction amplitudes follow
accordingly. The outputs of the E-W Pin amplifier (parabola)
and the H Trap amplifier (ramp) are summed together in an
op amp summing circuit, with H Trap weight 'fa that of E-W
Pin. The output of the summing amplifier is H Dyn Width,
uSed for correcting E-W pincushion and horizontal trapezoid
distortion. The outputs of the H Bow amplifier (parabola)
and the H Para amplifier (ramp) are summed together similarly, with H Bow and H Para equally weighted. The output
of the summing amplifier is H Dyn Cntr, used for correcting
horizontal bow and horizontal parallelogram distortion. All
three op amp outputs are identical structures and are typical
low output impedance type op amp outputs, capable of sinking or sourcing 5 mA minimum.

VERTICAL OSCILLATOR
The vertical oscillator is an injection-locked ramp generator
with automatic level control. The automatic level control
maintains the oscillator output ramp height with changes in
input frequency. The oscillator requires negative-going TIL
level vertical sync pulses, wider than 200 ns, to lock. In the
absence of vertical sync, the oscillator free runs at the low
end of the" frequency range, typical 48 Hz. The vertical output amplitude is controlled by a voltage between OV and 4V
on the V Height input with a range of about 1.8 to 1, and by
a voltage between 3V and 4V on the Vertical Dynamic
Height input with a range of about 1.3 to 1. The control
bandwidth of the V Height input is low due to the automatic
level control, but that of the Vertical Dynamic Height is
greater than 125 kHz. The oscillator has a circuit, requiring
an external capaCitor, 2f Cap, that prevents the oscillator
from locking at twice the vertical sync frequency. The oscillator ramp voltage is converted into differential currents superimposed on DC currents of about 315 p.A for each output. The voltage to current conversion gain is inversely proportional to the value of the resistor connected between the
Rvert pins (21 and 22). Differential current outputs are provided instead of VOltage to avoid ground noise. The ramp
voltage goes to the parabolic function generator and to two

Block Diagram
RVERT

r~~~~~

V Sync in'

__cr~24

+ Vertica' Drive

2' Vertical
1---<")-.-

V Height
God

RVERT

0-:.

-+0-----'

:ei~~~ -.:j~

Drive

Vic (12V)

17

~GND

_ _ _ _ _ _ _ _ _ _---J

":'

0-:.,8V Cap
o.!.V'EF Cap

V Oy"

Focus
Cntl

15

4'O+--------t----'

">4_.0.....1.6. V Oy"

Focus

02-4Vcap

Cotl -+0+----'

H Trap

11

.>4-.0_ HOy"

Width

orr

[-w Cnt!
Pin -;t<>-jl-:==:--t=:j:==~_---.:J
10

14

>-1-.0-+ H Oyn Cotr
H Para 12

cotl-:~~;=====-::~
__J===~3=~..J-'\'t"~>--4rv---'
-.:'

H a••
Cotl

TUH/12324-3

FIGURE 3
2-179

~r---------------------------------------------------------~

&I
.-

:!i
..J

Pin Descriptions
See Figures 4 througtl 8 for Input and Output schematics..
GND (Pin 1): This pin should be connected to the power
ground at pin 17.

H Trap Cntl (Pin 11): Horizontal Trap,ezoidControl. A voltage of OV to 4V adjusts the polarity and the amount of vertical ramp in the Horizontal Dynamic Width (pin 9) output. At
approximately 2V. the amount is zero. From 2V to 4V. the
amplitude increases and the ramp. is positive-going. From
2V to OV. the amplitl,Jde increases and the ramp is negativegoing.
.
H Para Cntl (PIn 12): Horizontal Parallelogram Control. A
voltage of OV to 4V adjusts the polarity and the amount of
vertical ramp in the Horizontal Dynamic Center (pin 14) output. At approximately 2V. the amount is zero. From 2V to
4V. the amplitude increases and the ramp is positive-going.
From 2V to OV. the amplitude increases and the ramp is
negative-going.
.

V Height (Pin 2): Vertical Height. A voltage between OV and
4V on this pin controls the amplitude of the +V and -V
Drive currents with increasing voltage giving increasing current. The control range is approximately 1.8 to 1. The response time is slow. being limited by the automatic level
control loop.
4 V Cap (Pin 3): 4 Volt Cap Capacitor. A 10.p.F capacitor.
aluminum electrolytic or tan1alum. should be connected between pin 3 (positive side) and GND (pin 17) to bypass the
internal 4V reference.
V Sync In' (Pin 4): Vertical Sync Input. The vertical sync
input takes a negative-going TTL level pulse which injection
locks the vertical oscillator to the vertical sync frequency if it
is above the LM1295 minimum frequency. The input threshold level is approximately 2V. so pulses other than TTL level
are satisfactory as long as they cross the 2V threshold with
at least a 400 mV margin either side. The input should be
DC coupled: The minimum pulse width is approximately
200 ns.

H Bow Cntl (Pin 13): Horizontal Bow Control. A voltage of
OV to 4V adjusts the polarity and the amount of parabola in
the Horizontal Dynamic Center (pin 14) output. At approximately 2V. the amount is zero. From 2V to 4V. the amplitude
increases and the parabola is positive-going. From 2V to OV.
the amplitude increases and the parabola is negative-going.
H Dyn Cntr (PIn 14): Horizontal Dynamic Center. This output consists of the sum of the vertical ramp and the parabola derived from the ramp. The amplitude and polarity of the
ramp signal is DC controlled by H Para Cntl (pin 12) and of
the parabola by H Bow Cntl (pin 13). The·difference between this output and the Horizontal Dynamic Width output
is in the weighting of the ramp. which is equal to the parabola; i.e.• with the H Para and H Bow Cntls at !IV. the output is
1 part parabola and 1 part ramp. Horizontal Dynamic Center
is used to correct for parallelogram and bow distortion. The
output stage is similar to a standard op-amp output. The
bandwidth from either of the 2 control pins to the output is
DC to greater than 125 kHz.

8 V Cap (Pin 5): 8 Volt Capacitor. A 100 p.F capacitor. aluminum electrolytic or tantalum. should be connected between pin 5 (positive side) andGND (pin 17) to bypass the
internal 8V reference.
V Dyn Height (Pin 6): Vertical Dynamic Height. A voltage
between 3V and 4V on ttlis pin controls the amplitude of the
+ V and - V Drive currents with increasing voltage giving
increasing current. The control range is apprOximately
1.3 to 1. The bandwidth of this input is DC to. greater than
125 kHz in contrast to the slow Vertical Height input.
Vee (PIn 7): Power. 12V nominal. Vee should be bypassed
to GND (pin 17) with a 10 p.F aluminum electrolytic or tantalum capacitor.

V Dyn Focus Cntl (PIn 15): Vertical Dynamic Focus Control. A voltage of OV to 4V adjusts the polarity and the
amount of parabola in the Vertical Dynamic Focus (pin 16)
output. At approximately 2V. the amount iszero. From 2V to
4V. the amplitude increases and the parabola is positivegoing. From 2V to OV. the amplitude increases and the parabola is negative-going.

Vref Cap (Pin 8): Voltage Reference Cap. A 10 p.F capacitor. aluminum electrolytic or tantalum. should be connected
between pin 8 (positive side) and GND (pin 17).
H Dyn Width (Pin 9): Horizontal Dynamic Width. This output
consists of the sum of the vertical ramp and the parabola
derived from the ramp. The amplitude and polarity of the
ramp signal is DC controlled by H Trap Cntl (pin 11) and of
the parabola by E-W Pin Cntl (pin 10). The weighting of the
ramp is Va the parabola; i.e.• with the H Trap and E-W Pin
Cntls at 4V. the output is 3 parts parabola and 1 part ramp.
Horizontal Dynamic Width is used to correct for trapezoid
and east-west pincushion distortion. The output stage is
similar to a standard op-amp output. The bandwidth from
either of the 2 control pins to the output is DC to greater
than 125 kHz.
E-W Pin Cntl (Pin 10): East-West Pincushion Control. A
voltage of OV to 4V adjusts the polarity and the amount of
parabola in the Horizontal Dynamic Width (pin 9) output. At
approximately 2V. the amount is zero. From 2V to 4V. the
amplitude increases and the parabola is positive-going.
From 2V to OV. the amplitude increases and the parabola is
negative-going.

V Dyn Focus (PIn 16): Vertical Dynamic Focus. This output
consists of the parabola derived from the vertical ramp. The
amplitude and polarity are controUed by V Dyn Focus Cntl.
The output stage is similar to Ii standard op-amp output.
The bandwidth from the control pin to the output is DC to
greater than 125 kHz.
GND (Pin 17): Ground. This is the power supply ground for
the 12V supply and the point to which the bypass capacitors
are returned. ;
ALC Cap (Pin 18): Automatic Level Control Capacitor. This
capaCitor is part of the level control circuit that maintains
constant vertical height in spite of vertical sync frequency
changes. The recomm'ended value is 4.7 p.F. aluminum
electrolytic or tantalum capacitor. If the veo capacitor value
is changed. this capaCitor value should change in the same
ratio. A 300k reSistor should be connected from this pin to
ground.
2f Cap (Pin 19): Double freqyency CapaCitor. This capacitor
prevents the vertical oscillator from locking at twice the vertical sync frequency. The recommended value is 0.47 p.F. If
the veo capacitor value is changed, this capacitor value
.should change in the same ratio.

2-180

Pin Descriptions (Continued)
Osc Cap (Pin 20): Oscillator Capacitor. This is the vertical
oscillator capacitor. The recommended value is 0.1 ",F. The
value can be changed to change the minimum frequency.
Rvert (Pin 21): Vertical Resistor. One end of the Vertical
Resistor connects to this pin. This resistor determines the
gain of the vertical ramp current generator. The gain is inversely proportional to the resistance. It is recommended
that this be a standard 5% %W carbon film resistor whose
negative temperature coefficient corrects for the negative
temperature coefficient of the LM 1295. The resistor should
be located near the LM1295. The recommended value is
10 kO.
Rvert (Pin 22): Vertical Resistor. The other end of the Vertical Resistor connects to this pin.

- V Drive (Pin 23): - Vertical Drive. This is the negativegoing vertical ramp output current of the differential pair.
The ramp current waveform is superimposed on a direct
current of approximately 315 ",A. The waveform amplitude
is determined by the Vertical Height (pin 2) control voltage
and the Vertical Dynamic Height (pin 6) control voltage. The
current can be converted into voltage by a resistor (typically
10 kO) to ground or by a differential amplifier using the differential c\Jrrents as inputs. The voltage compliance of the
output is typically 6V.

+

V Drive (Pin 24): + Vertical Drive. This is the same as
- V Drive except it is the positive-going output current of
the differential pair.

Input/Output Schematics

TL/H/12324-B

FIGURES

2-181

Typical Application
LM 1295
GNO

TO VERTICAL
OEFL YOKE

......----''--+-----{I1 v HEIGHT
+---1IF--[!]4V CAP

v SYNC ..-tr
..'-'+-t~~1~a~'~O~"~F;~~V SYNC IN

TO H WIDTH
ONE-SHOT
r--------------. (CAP
CHARGING
CURRENT)

+ 12V 0-.....---'
TL/H112324-9

Note: LM1295 is designed to drive a differential input vertical deflection amplifier. The LM1295. however. can also drive a single-ended input vertical deflection
amplifier by just using eRhar the

+ V drive or

- V drive pins.

FIGURE 9

t!lNational Semiconductor

LM1391 Phase-Locked Loop
General Description
• Output transistor with low saturation and high voltage
swing
." APC of the oscillator with a synchronizing signal·
• DC controlled output duty cycle
• ± 300 Hz typical pull-in
• Linear balanced phase detector
• Low thermal frequency drift
• Small static phase error,
• Adjustable DC loop gain

The LM1391 integrated circuit has been designed primarily
for use in the horizontal section of TV receivers, but may
find use in other low frequency signal processing applications. It includes a stable veo, linear pulse phase detector,
and variable duty cycle output driver.

Features
• Internal active regulator for improved supply rejection
• Uncommitted collector of output transistor

Schematic Diagram
PRE·DRIVER

OSCILLATOR

OSCILLATOR
TIMING

REGULATOR
REGULATOR

.",,

.,

260

VOLTAGE

••

Uk

,

.,

PHASE DETECTOR

.14
330

,..11

Z2

5

PHASE

DETECTOR
OUTPUT

OU~~~:~~o-'_-+_.......
OUTPUT

R2

RJ

6.8k

15k

,.,...

.

.3

...

.Z1

,
'"

.26

15'

.13

.2

'"

SYNC
INPUT

TlIH17889-1
(0) Pin 4 Base of 016 (LM1391) for use with (+) flyback pulse

fII

2-183

Absolute Maximum Ratings
If Military/Aerospace specified devices are required;
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Flyback Input Voltage (Pin 4)

Supply Current

Operating Temperature Range (Ambient)

40mAoc

Output Voltage

40VoC

Output Current

3OmAoc

Sync Input Voltage (Pin 3)

5.0Vp-p

Power Dissipation (Package Limitation)
Plastic Package (Note 1)

1000mW
O'Cto +70'C

.Storage Temperature Range

-65'C to + 150'C

Lead Temperature (Soldering, 10 sec.) .

260'C

5.0Vp-p

Electrical Characteristics TA =
Parameter

25'C (see test circuit, all switches in pOSition
Conditions

Regulated Voltage (Pin 6)

Is = 22mAoc

1)

Min

Typ

Max

8.0

8.6

9.2

Supply Current (Pin 6)

Units
Voc

20

Collector-Emitter Saturation Voltage.
of Output Transistor (Pin 1)

101 = 20mA

mAoc

0.30

Pin 4 Voltage

0.40

Voc

2.0

Voc

Oscillator Pull-in Range

AdjustRH

±300

Hz

Oscillator Hold-in Range

AdjustRH

±900

Hz

Static Phase Error

af = 300 Hz

0.5

P.s

Free-running Frequency Supply
Dependance

S1 in position 2

±3.0

HzNoc

Phase Detector Leakage (Pin 5)

All switches in position 2

Sync Input VOltage (Pin 3)

2.0

Sawtooth Input Voltage (Pin 4)

1.0

Maximum Oscillator Frequency

±1.0

p.A

5.0

Vp-p

3.0

Vp-p

500

kHz

Note 1: For operation in ambient temperatures above 25'C, the device must be derated based on a t 50'C maximum iunction temperature and a thermal resistance
of t 20'C/W junction to ambient.

Typical Performance Characteristics
Frequency Drift vs Warm-Up
Time
30
20

-

r-

REFERENCE FREQUENCY
'0'" 15.150 Hz

150
100

- r- r-

7.0
REFERENCE FREOUENCY

'0

-20
-30

e"

...
~

~

-50

r-

-100

.j,:~o

rs
::~ ::2~OC':~~~:~:~=

-150

-40

-200

x 106 - -200ppm'-C

1.

30 45

60

75 90 105 120

TIME Is)

0

10

I--

~~

-50
0

-

r-

u

0

\. ........

fo '" 15, 750Hz

6.0

50

•

REFERENCE FREQUENCY

6.5

= 15.150 Hz

10

-10

Output Duty Cycle vs VM
Voltage

Frequency vs Temperature

20 30

40

50 60 70

AMBIENT TEMPERATURE ( C)

80

">:E
>

5.5
5.0

,;"

4.'

[....-

4.0
3.5
3.0
2.5

..,0

~

'"

10 20 30 40 60 80 70 80 90
PIN 1 OUTPUT DUTY CYCLE (%)

TL/HI7B89-3

2-184

Application Information
The following equations may be considered when using the
LM1391 in a particular application.
R201 = R301 =

DC Loop Gain

ILP '" 3.2 X 10- 5 Rofo Hz/rad

Noise Bandwidth

Vee - 8.6
0.02
n

1
fa"" ---C- Hz 1.5k';; Ro
0. 6R o a

< 51k
Damping Factor

R204'" lORa
C203 = C204 '" 600

'TI"Rx2
K" --CCILP

f~(HZ) F

2 Ry

Test Circuit

Vee
3DV

1k

O+?,4V
,A

2k

1k

2

12k

6800pF

150k

S2

12",PULSE}
{ +SOY FOR
lM1391 ----.

TUH17889-4

Connection Diagram
Dual-In-Llne Package
DuTY CYCLE
CONTROL

OSCILLATOR
TIMING

REGULATDR
VOLTAGE,

PHASE
DETECTOR
OUTPUT

OUTPUT

GND

SYNC
INPUT

SAWTOOTH
INPuT

Top View

Order Number LM1391N
See NS Package Number NOSE
2-185

TUH17889-2

.r-----------------------------------------------------------------------------------------------,

~
G)'
C')
~

:::I

Typical Applications

....

VCC
24V TYP

RI06
2.7k
RIDS
14k

RI~~ ~t---if-1
HOLD
RI04

r-____

CID2

~~----~-~~~~~~12-D-k~~Di·O~

R110
1.2k
1/2W

LMI391

TO YOKE

Rill
3.9k
12~.

FL YBACK PULSE
+4DV FOR LM1391

-2DV
NEG
"SYNC
TL/H17889-5

FIGURE,1. TV Horizontal Processor
'VCC
24VTYP

R201

R203
3k

11204

R206
2.7k
R207
2.4k

RO

FRED
TRIM

-

Co

Ry

'='

~

R202
1.5k

LM1391'

3 VP'p INPUT
SYNCHRONIZING SIGNAL

FIGURE 2.GeneraIPutposePha.e~Lock Loop
(See' Applications Information)
2·186

TUH17889-6

,-----------------------------------------------------------------------------,
Typical Applications (Continued)
Vee
24VTYP

FREn ADJ

RlOl
Rl06
2Sk

RlOS
2.Sk

Rl02
1.7k

RlOl
lk

Rl04
l.lk

Rl07
I.Sk
LMI391

T

el01 '

PULSE·WIDTH
MODULATION
TL/H17889-7

FIGURE 3. Variable Duty Cycle Oscillator
(See Applications Information)

2·187

~

iiC
....
~
....

~ r---~-----------------------------------------------------------------------'

~

~

t!lNational Semiconductor

LM1823 Video IF Amplifier/PLL Detector System
General Description

Features

The LM1823 is a complete video IF signal processing sYstem on a chip. It contains a 5-stage gain-controlled IF amplifier, a PLL synchronous amplitude detector, self-contained
gated AGC, and a switchable AFC detector. The increased
flexibility of the LM1823 makes it suitable for wide variety
of television applications where high quality video or sound
carrier recovery is required. These include home receiver
video IFs, cable and subscription TV decoders, and parallel
sound IF/intercarrier detector systllms. Typical operating
frequencies are 38.9 MHz, 45.75 MHz, 58.75 MHz, and
61.25 MHz.

•
•
•
•
•
•
•
•
•
•
•
•

a

Low differential gain and phase
IF and detector pin compatible with LM1822
Common-base IF inputs for SAW filters
True synchronous video detector using PLL
Excellent stability at high system gains
Noise-averaged gated AGC system
Uncommitted AGC comparator input
Internal AGC gate generator
Superior small-signal detector linearity
AFC detector with adjustable output bias
9 MHz video bandwidth
Reverse tuner AGC output

Test Circuit Measure parameters at indicated test pOints
V2B

12V

10k

Vour 0.01

IFOU~

...

...._ ....-oY27

V1o-...y;.IIIthe IF output load, ,a capacitive divider may be 'Used ,from pin 1 to pin 28 in which 'the
series equivalent capacitance resonate~ with the coil. :

FIGURE 3. Prlnt~d CIrcuIt Layout (Co.nponent SIde).

2-194

,",'

TLlH/5222-5

tflNational Semiconductor

LM 1881 Video Sync Separator
General Description

Features

The LM1881 Video sync separator extracts timing information including composite and vertical sync, burst/back porch
timing, and odd/even field information from standard negative going sync NTSC, PAL·, and SECAM video signals with
amplitude from 0.5V to 2V p-p. The integrated circuit is also
capable of providing sync separation for non-standard, faster horizontal rate video signals. The vertical output is produced on the rising edge of the first serration in the vertical
, sync period. A default vertical output is produced after a
time delay if the rising edge mentioned above does not occur within the externally set delay period, such as might be
the case for a non-standard video signal.

• AC coupled composite input signal
• > 10 kO input resistance
• <10 mA power supply drain current
• Composite sync and vertical outputs
• Odd/even field output
• Burst gate/back porch output
• Horizontal scan rates to 150 kHz
• Edge triggered vertical output
• Default triggered vertical output for non-standard video
signal (video games-home computers)

Connection Diagram
LM1881N
Vee
8 1------05-12V

COMPOSITE
SYNC OUTPUTo-------I
0.1 pF
COMPOSITE
VIDEO INPUTO----I

I

2

7 I--~~~-O ODD/EVEN OUTPUT

4

" - - - - - - 0 BURST/BACK PORCH
5 ...
OUTPUT

VERTICAL
SYNC OUTPUTo-------I

COMPOSITE
VIDEO INPUT
COMPOSITE

::fi====~=::fj;::::::;i==J:=:;J=:::;i==;==~=;::==;:;==;;:=t=

SYNCOUTPUT:=t::::::::t=::1=::=t::=1~::t=::=t::::::=t::~~::t:::~:::t::

VERTICAL
SYNC OUTPUT
BURST OUTPUT

- i ...- - - . ; 1"-';1"-.;

r---------

ODD/EVEN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _",;,.,._ _ _
OUTPUT ...

TL/H/91S0-1

Order Number LM1881M or LM1881N
See NS Package Number M08A or N08E

'PAL in this datasheet refers to European broadcast TV standard "Phase Alternating Line'", and not to Programmable Array Logic.

2-195

•

Absolute Maximum Ratings
Storage Temperature Range
-65'Gto + 150"C
ESD Susceptibility (Note 2)
2kV
Soldering Information
Dual-In-Line Package (10 sec.)
260"C
Small Outline Package
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting Methods and their Effect on
Product Reliability" for other methods of soldering surface
mount devices.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
13.2V
Input Voltage
3 Vpp (Vee = 5V)
6 Vpp (Vee:;" 8V)
Output Sink Currents; Pins 1, 3, 5
5mA
2mA
Output Sink Current; Pin 7
11{)OmW
Package Dissipation (Note 1)
Operating Temperatore Range
O'C - 70"C

Electrical Characteristics
Vee

= 5V; Rset = 680 kO; TA

= 25'C;Unless otherwise specified

Parameter
Supply Current
DC Input Voltage

Conditions
Outputs at Logic 1

Vee
Vee

= 5V
= 12V

, Pin 2

Input Threshold Voltage

Note 5

Input Discharge Current

Pin 2; VIN

= 2V

Input Clamp Charge Current

Pin 2; VIN

= 1V

RSET Pin Reference Voltage

Pin 6; Note 6

Composite Sync. & Vertical
Outputs

lOUT = 40,..,A;
Logic 1

Typ

Tested
Umit (Note ~)

5.2
5.5

10
12

mAmax
mAmax

1.5

1.3
1.8

Vmin
Vmax

70

55
85

mVmin
mVmax

11 .

6
16

,...Amin
,..,Amax

Design,
Limit (Note 4)

Units
(Limits)

0.8

0.2

mAmin

1.22

1.10
1.35

Vmin
Vmax

lOUT = 1.6mA
Logic 1

=
=
Vee =
Vee =

5V
12V

3.6

2.4
10.0

Vmin
Vmin

Burst Gate & Odd/Even
Outputs

lOUT = 40,..,A;
Logic 1

Vee"; 5V
Vee = 12V

4.5

4.0
11.0

Vmin
Vmin

CompoSite Sync. Output

lOUT

-1.6 mA;Logic 0; Pin 1

0.2

0.8

Vmax

Vertical Sync. Output

lOUT

-1.6 mA; Logic 0; Pin 3

0.2

0.8

Vmax

-1.6 mA; Logic 0; Pin 5

0.2

0.8

Vmax

-1.6 mA; Logic 0; Pin 7

0.2

0.8

Vmax

230

190
300

,..,smin
,..,smax

4

2.5
4.7

,..,smin
,..,smax

65

32
90

,..,smin
,..,smax

Burst Gate Output
Odd/Even Output

=
=
lOUT =
lOUT =

Vee
Vee

5V
12V

4.5

4.0
11.0

Vmin
Vmin

Vertical Sync Width
Burst Gate Width

2.7 kO from Pin 5 to Vee

Vertical Default Time

Note 7

Note 1: For operation in ambient temperatures above 2S'C, the device must be derated based on a 15O'C maximum iunction temperature and a package thermal
resistance of 110' C/W, iunction to ambient.
Note 2: ESO susceptibility test uses the "human body model, 100 pF discharged through a 1.S kG resistor".
Note 3: Typicals are at TJ ~ 2S'C and represent the most likely parametric norm.
Note 4: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 5: Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
Note 6: careful attention should be made to prevent parasHlc capacitance coupling from any output pin (Pins 1, 3, S, and 7) to the RSET pin (Pin 6).
Nole 7: Delay time between the start of vertical sync (at input) and the vertical output pulse.

2-196

Typical Performance Characteristics
Rae! Value Selection
Vertical Serration
Pulse Separation

Vertical Default
Sync Delay Time
vs Rset
m

VB

'~QO =:"":"!-:--::-='::-::-.,...,----:--:-r:----:.
'200 I----t-""-'-+=+--"~~

!
w

~

,.

O.B

'000

BOO r---t-+~~~

O.B

600

0..1

I--+_~~~

!/

0.2
OL-~-~-~-~~

5

'0

'5

20

25

0.0

30

o

VERTICAL SERRATION
PULSE SEPARATION

0.6

t;

.2'

0.4

o.6
0.4

40

80

80

o

,00

o

'0
BURST/BLACK LEVEL
GATE TIME

10

r-- r-- r300

Supply Current vs
Supply Voltage

~oo

V

200

'00

/

/

(1'.)

-

0.2
0.0

/

0.2

Vertical Pulse
Width vs Temperature

v

I

V

(".)

1.0

co

/

0.8

0.0
20

(".)

~

V

Burst/Black Level
Gate Time vs Rut
0

VERTICAL DEFAULT SYNC
DELAY TIME

Vertical Pulse
Width vs Rset

0.8

/

,.

~oo

VERTICAL PULSE WIDTH

500

•o

'0

I

o
20
TEMPERATURE (DC)

60

70

o

'0

'2

Vee

(".)
TL/H/9'50-2

2-197

-

~

:l

,-----------------------------------------------------------------------------~

Application Notes
from between 40 ns to as much as 200 ns due to this filter.
Tqis much delay will not usually be significant but it does
contribute to the sync delay p~(lduCE!d by any additional signal processing. Since the original video,ll)ay also undergo
processing, the need for lilTle delay, correction will depend
on the total system, not just'the sync stripper.

The LM 1881 is designed to strip the synchronization signals
from composite video sources that are in, or similar to, the
N.T.S.C. form,at.lnput signals with pOSitive polarity video (increasing signal vOltage signifies increasing scene brightness) from 0.5V (p-p) to 2V (p-p) can be accommodated.
The lM1881 opera/es from a single supply voltage between
5V DC and 12V ~C. The only required external components'
beside power supply and set current decoupling are the input coupling capacitor and a single reSistor that:sets internal
current levels" allowing the LM 1881 to be adjusted for
source signaJs with line' scan frequencies differing from
15.734 kHz. Four major sync signals are available from the
IIC: composite sync including both horizontal,and vertical
scan timing information; a vertical sync pulse; a burst gate
or back porch clamp pulse; and an oddleven output. The
oddl even output level identifies which video field of an inter,
laced video source is present at the input. The outputs from
the LM1881 can be used to gen-Iock video camera/VTR
signals with graphics,sources, provide identification of video
fields for memory storage, recover suppressed orcontaminated sync signals, and provide timing references for the
extraction of coded or uncoded data on specific video scan
lines.

VERTICAL SYNC OUTPUT
A vertical sync output is d~rived by internally integrating the
composite sync waveform, (Figure 3). To understand the
generation of the vertical sync pulse, refer to the lower left
hand section Figure 3. Note that there are'two comparators
in the section. One comparator has an internally generated
voltage reference called V1 going to one of its inputs. The
other comparator has an internally generated voltage referance called V2 going to one of its inputs. Both comparators
have a common input at their non inverting input coming
from the internal integrator. The internal integrator is used
for integrating the composite sync lIignal. This signal comes
from the input side of the compOSite sync buffer and are
positive going sync pulses. The capacitor to the integrator
is internal to the LM 1881. The capacitor charge current is
set by the value of the external resistor Rsat. The output of
the integrator is going to be at a ,low voltage during the
normal horizontal lineS becaus~ the' integrator has a very
short time to charge the capacitor, which is during the horizontal sync period. The equalization pulses will keep the
output voltage of the integrator at about. the same level,
below the Vl. During the vertical sync period the narrow
going,positive pulses shown in Figure 2 is called the serration pulse. The wide negative portion of the vertical sync
period is called the vertical sync pulse. At the start of the
vertical sync period, before the first Serration pulse occurs,
the integrator now charges the capacitor to a much higher
voltage. At the first serration pulse the integrator output
should be between Vl and V2. This would give a high level
at the output of the comparator with V1 as one of its inputs.
This high is clocked into the "0" flip-flop by the falling edge
of the serration pulse (remember the sync signal is inverted
in this section of the LM1881). The "0" output of the "0"
flip-flop goes through the OR gate, and sets the RIS flipflop. The output of the RIS flip-flop enables the internal
oscillator and also clocks the OOO/EVEN "0" flip-flop. The
OOO/EVEN field pulse operation is covered in the next sec- ,
tion. The output of the oscillator goes to a divide by 8 circuit,
thus resetting the RIS flip-flop after 8 cycles of the oscillator. The frequency of the oscillator is established by the
internal capacitor going to the oscillator and the external
output of the RIS flip-flop goes to pin 3 and is
Rsat. The
the actual vertical sync output of the LM 1881. By clocking
the "0" flip-flop at the start of the first serration pulse
means that the vertical sync output pulse starts at this point
in time and lasts for eight cycles of the internal oscillator as
shown in Figure 2.

To better understand the LM1881 timing information and
the type of signals that are used, refer to Figure 2(8-e)
which shows a portion of the Composite video signal from
the end of one field through the beginning of the next field.

COMPOSITE SYNC OUTPUT
The composite sync output, Figure 2(b), is simply a reproduction of the signal waveform below the composite video
black level, with the video completely removed. This is obtained by clamping the video signal sync tips to 1.5V DC at
Pin 2 and using a comparator threshold set just above this
voltage to strip the sync Signal, which is then buffered out to
Pin 1. The threshold separation from the clamped sync tip is
nominally 70 mV which means that for the minimum input
level of 0.5V (p-p), the clipping level is close to the halfway
point on the sync pulse amplitude (shown by the dashed
line on Figure 2(8). This threshold separation is independent of the signal amplitude, therefore, for a 2V (p-p) input
the clipping level occurs at 11 % of the sync pulse amplitude. The charging current for the input coupling capacitor is
0.8 mA, whereas the discharge current is only 11 p.A, typically. This allows relatively small capacitor values to be
used-O.1 ,.F is generally recommended.
Normally the Signal source for the LM1881 is assumed to be
clean and relatively noise-free, but some sources may have
excessive video peaking, causing high frequency video and
chroma components to extend below the black level reference. Some video discs keep the chroma burst pulse present throughout the vertical blanking period so that the burst
actually appears on the sync tips for three line periods instead of at black level. A clean composite sync signal can
be generated from these sources by filtering the input signal. When the source impedance is low, typically 750, a
6200 resistor in series with the source and a 510 pF capacitor to ground will form a low pass filter with a corner frequency of 500 kHz. This bandwidth is more than sufficient to
pass the sync pulse portion of the waveform; however, any
subcarrier content in the signal will be attenuated by almost
18 dB, effectively taking it below the comparator threshold.
Filtering will also help if the source is contaminated with
thermal noise. The output waveforms will become delayed

"a"

How Rsat affects the integrator and the internal oscillator is
shown under the Typical Performance Characteristics. The
first graph is "Rset Value Selection vs Vertical Serration
Pulse Separation". For this graph to be valid, the vertical
sync pulse should last for at least 85 % of the horizontal half
line (47% of a full horizontal line). A vertical sync pulse from
any standard should meet this requirement; both NTSC and
PAL do meet this requirement (the serration pulse is the
remainder of the period, 10% to 15% of the horizontal

2-198

r-----------------------------------------------------------------------------,~

!!I:
....
co
co
....

Application Notes (Continued)
_S!_ART_0_F_Fl_EL_D_1..:.(0_OO--'>+--,-_ _ _ _ _ _ VERTICAL BLANKING INTERVAL - - - - - - - - - 1
EQUALIZING
PULSES

h-l
63.51'1

:.jl31.81'1

--I- SERRATED -I-- EQUALIZING --I
I VERllCAL PULSE I PULSES I

~

--II2301'1 typ

--------~----------~

----I

2.41'1

~------~~---

000 FIELD
EVEN FIELD

I-rI

--11-

41'S typo

63.5I's

TLlH/9150-3

FIGURE 2. (a) Composite Video; (b) Composite Sync; (c) Vertical Output Pulse;
(d) Odd/Even Field Index; (e) Burst Gate/Back Porch Clamp

8

SUPPLY
VOLTAGE

REG

VIDEO
INPUT

.~~I'~F~2-t_+-__+lr---,

7

0001 EVEN
FIELD
INDEX

510 PF,I

YER~;~~ o--f------+-I

t-----f-()ot---......,

RsET

680k

5

'Components Optional,
See Text

BURST GATEI
BACK PORCH
CLAMP

TLlH/9150-4

FIGURE 3

2-199

Application Notes (Continued)
half line). Remember this pulse is a positive pulse at the
integrator bul negative in Figure 2. This graph shows how
long it takes the integrator to charge its internal capaoitor
above VI.
WITH Rset too large the charging current of the integrator
will be too small to, charge the capacitor above VI, thus
there will be no vertical synch output pulse: As mentioned
above, Rset also sets the frequency of the internal oscillator.
If the oscillator runs too fast its eight cycles will be shorte(
than the vertical sync portion of the composite sync. Under
this condition another vertical sync pulse can be generated
on one of the later serration pulses after the divide by 8
circuit resets the RIS flip-flop. The first graph also shows
the minimum Rse! necessary to prevent a double vertical
pulse, assuming that the serration pulses last for only three
full horizontal line periods (Six serration pulses for NTSC).
The actual pulse width of the vertical sync pulse is shown in
the "Vertical Pulse Width vsRsat" graph. Using NTSC as an
example, lets see how these two graphs relate to each other. The Horizontal line is 64 P.s long, or 32 p.s for a horizontal half line. Now round this off to 30 p.s. In the "Rsat Value
Selection vs Vertical Serration Pulse Separation" graph the
minimum resistor value for 30 p.s serration pulse separation .
is about 550 kO. Going to the "Vertical Pulse Width vs Rsat" '
graph one can see that 550 kO gives a vertical pulse width
of about 180 p.s, the total time for the vertical sync period of
NTSC (3 horizontal lines). A 550 kO will set the internal
oscillator to a frequency such that eight cycles gives a time
of 180 p.s, just long enough to prevent a double vertical
sync pulse at the vertical sync output of the LM 1881.
The LM1881 also generates default vertical sync pulse
when the vertical sync period is unusually long and has no
serration pulses. With Ii very long vertical sync time the integrator has time to Charge its internal capaCitor above the
voltage level V2. Since there is no falling edge at the end of
a serration pulse to clock the "0" flip-flop, the only high
signal going to the OR gate is from the default comparator
when output of the integrator reaches V2. At this time the
RIS flip-flop is toggled by the default comparator, starting
the vertical sync pulse at pin 3 of the LM1881. If the default
vertical sync period ends before the end of the input vertical
sync period, then the fl1-lIing edge of the vertical sync (positive pulse at the "0" flip-flop) will clock the high output from
the comparator with V I as a reference input. This will retrigger the OSCillator, generating a second vertical sync output
pulse. The "Vertical Default Sync Delay Time vs Rsat"
graph shows the relationship between the Rsat value and
the delay time from the start of the vertical sync period before the default vertical sync pulse i\l generated. Using the
NTSC example again the smallest resistor for Rset is 500
kO. The vertical default time delay is about 50 p.s, much
longer than the 30 P.s serration pulse spacing.
A common qUestion is how can one :calculate the required
Rsat with a video timing standard that has no serration pulses during the vertical blanking. If the default vertical sync is
to be used this is a very easy task. Use the,,"Vertical Default

a

Sync Delay Time vs Rsat" graph to select the necessary
Rsat to give the desired delay time for the vertical sync output signal. If, second pulse is undesirable, then check the
"Vertical Pulse Width vs Rset" graph to make sure the vertical output pulse will extend beyond the end of the input
vertical sync period. In most systems the end of the vertical
sync period may be very accurate. In this case the preferred
design may be to start the vertical sync pulse at the end of
the vertical sync period, similar to starting the vertical sync
pulse after the first serration pulse. AVGA standard is to be
used as an example to show how this is done. In this standard a horizontal line is 32 p.s ,long. The vertical sync period
is two horizontal nl"lllS long, or 64 p.s. The vertical default
sync delay time must be longer than the vertical sync period of 64 p.s. In this case Rset must be larger than 680 kO.
Rset must still be small enough for the output of the integrator to reach V I before the end of the vertical period of the
input pulse. The first graph can be used to confirm that Rsat
is small enough for the integrator. Instead of using the vertical serration pulse separation, use the actual pulse width of
the vertical sync period, or 64 p.s in this example. This graph
is linear, meaninfl that ,a value as large as 2.7 MO can be
used for Rsat (twic", the value as the maximum at 30 p.s).
Ol!e to leakage currents it is advisable to keep the value of
Raet under 2.0 MO. In this example a value of 1.0 MO is
selected, well above the minimum of 680 kO. With this value
for Rse! the pulse width of the vertical sync output pulse of
, the LM1881 is about 340 p.s.

a

ODD/EVEN~IELlj PULSE

An unusual feature of, LM1881 is an output level from Pin 7
that identifies the video field present at the input to the
LM1881. This can be useful in frame memory storage applications or in extracting test signals that occur only in alter, nate fields. For a compOSite video signal that is interfaced,
one of the two fields that make up each video frame or
picture must have a half horizontal scan line period at the
end of the vertical scan-i.e., at the bottom of the picture.
This is called the "odd field" or "field 1". The "even field"
or "field 2" has a complete horizontal scan line at the end of
the field. An odd field starts on the leading edge of the first
equalizing pulse, whereas the even fillid starts on the leading edge of tlie second equalizing pulse of the vertical retrace interval. Figure 2(a) shows the end of the even field
and the start of the odd field.
To detect the oddleven fields the LM1881 again integrates
the composite sync waveform (Figure 3). A capaCitor is
charged during the period between sync pulses and discharged when the sync pulse is present. The period between normal honzontal sync pulses is enough to allow the
capaCitor voltage to reach a threshold level of a comparator
that clears a flipflop which is also being clocked by the sync
waveform. When the vertical interval is reached, the shorter
integration time between equajizing pulses prevents this

2-200

Application Notes (Continued)
threshold from being reached and the Q output of the flipflop is toggled with each equalizing pulse. Since the half line
period at the end of the odd field will have the same effect
as an equalizing pulse period, the Q output will have a different polarity on successive fields. Thus by comparing the Q
polarity with the vertical output pulse, an odd/even field index is generated. Pin 7 remains low during the even field
and high during the odd field.

signal (VIRS) and line 21 is reserved for closed caption data
for the hearing impaired. The remaining lines are used in a
number of ways. Lines 17 and 18 are frequently used during
studio processing to add and delete vertical interval test
signals (VITS) while lines 14 through 18 and line 20 can be
used for Videotex/Teletext data. Several institutions are
proposing to transmit financial data on line 17 and cable
systems use the available lines in the vertical interval to
send decoding data for descrambler terminals.
Since the vertical output pulse from the LM1881 coincides
with the leading edge of the first vertical serration, sixteen
positive or negative transitions later will be the start of line
14 in either field. At this pOint simple counters can be used
to select the desired line(s) for insertion or deletion of data.

BURSTIBACKPORCH OUTPUT PULSE

In a composite video signal, the chroma burst is located on
the backporch of the horizontal blanking period. This period,
approximately 4.8 ,..S long, is also the black level reference
for the subsequent video scan line. The LM 1881 generates
a pulse at Pin 5 that can be used either to retrieve the chroma burst from the composite video signal (thus providing a
subcarrier synchronizing signal) or as a clamp for the DC
restoration of the video waveform. This output is obtained
simply by charging an internal capacitor starting on the trailing edge of the horizontal sync pulses. Simultaneously the
output of Pin 5 is pulled low and held until the capacitor
charge circuit times out--4 ,..S later. A shorter output burst
gate pulse can be derived by differentiating the burst output
using a series CoR network. This may be necessary in applications which require high horizontal scan rates in combination with normal (60-120 Hz) vertical scan rates.

VIDEO LINE SELECTOR
The circuit in Figure 4 puts out a single video line according
to the binary coded information applied to line select bits
bO-b7. A line is selected by adding two to the desired line
number, converting to a binary equivalent and applying the
result to the line select inputs. The falling edge of the
LM1881's vertical pulse is used to load the appropriate
number into the counters (MM74C193N) and to set a start
count latch using two NAND gates. Composite sync transitions are counted using the borrow out of the desired number of counters. The final borrow out pulse is used to turn on
the analog switch (CD4066BC) during the desired line. The
falling edge of this signal also resets the start count latch,
thereby terminating the counting.
The circuit, as shown, will provide a single line output for
each field in an interlaced video system (television) or a
single line output in each frame for a non-interlaced video
system (computer monitor). When a particular line in only
one field of an interlaced video signal is desired, the odd/
even field index output must be used instead of the vertical
output pulse (invert the field index output to select the odd
field). A Single counter is needed for selecting lines 3 to 14;
two counters are needed for selecting lines 15 to 253; and
three counters will work for up to 2046 lines. An output buffer is required to drive low impedance loads.

APPLICATIONS

Apart from extracting a composite sync Signal free of video
information, the LM1881 outputs allow a number of interesting applications to be developed. As mentioned above, the
burst gate/backporch clamp pulse allows DC restoration of
the original video waveform for display or remodulatlon on
an R.F. carrier, and retrieval of the color burst for color synchronization and decoding into R.G.B. components. For
frame memory storage applications, the odd/even field level allows identification of the appropriate field ensuring the
correct read or write sequence. The vertical pulse output is
particularly useful since it begins at a precise time-the rising edge of the first vertical serration in the sync waveform.
This means that individual lines within the vertical blanking
period (or anywhere in the active scan line period) can easily be extracted by counting the required number of transitions in the compoSite sync waveform following the'start of
the vertical output pulse.
The vertical blanking interval is proving popular as a means
to transmit data which will not appear on a normal T.V. receiver screen. Data can be inserted beginning with line ~ 0
(the first horizontal scan line on which the color burst appears) through to line 21. Usually lines 10 through 13 are
not used which leaves lines 14 through 21 for inserting signals, which may be different from field to field. In the U.S.,
line 19 is normally reserved for a vertical interval reference

MULTIPLE CONTIGUOUS VIDEO LINE
SELECTOR WITH BLACK LEVEL RESTORATION

The circuit in Figure 5 will select a number of adjoining lines
starting with the line selected as in the previous example.
Additional counters can be added as described previously
for either higher starting line numbers or an increased number of contiguous output lines. The back porch pulse output
of the LM1881 is used to gate the video input's black level
through a low pass filter (10 kO, 10 ,..F) providing black level
restoration at the video output when the output selected
line(s) is not being gated through.

2-201

fII

Typical Applications
+5Vo-~~--------~--,---~~~------------~~-----,

680k4

2k4

.

,.

6200

.

O.I".r

~~-----------~~~------------~~~~--~~
VIDEO
INPUT

,...................- _.....,

SELECTED VIDEO
LINE OUT

TL/H/9150-5

FIGURE 4. Video Line Selector

...

+5Vo-'---~~----'-~~----~--------------~-----9--------------------

6200

0.1

~~----~+------~----~~--;--+----~
VIDEO

INPUT

+5V

2k4
10kll

o.oOl/loF

~---~

O.1/loFJ:

••

:.. ----------_
-=
.

.....----..... SELECTED VIDEO
LlNE(S) OUT

TL/H/9150-6

FIGURE 5. Multiple Contiguous Video Une Selector With Black Level Restoration

2·202

.-----------------------------------------------------~~

.....

!•

t!lNational Semiconductor

Ii:.....

LM 1882.S4ACT17 4ACT71S
LM 1882-R.S4ACT17 4ACT71S-R
Programmable Video Sync Generator
General Description
The 'ACT715/LM1882 and 'ACT715-R/LM1882-R are
20-pin TTL-input compatible devices capable of generating
Horizontal, Vertical and Composite Sync and Blank signals
for televisions and monitors. All pulse widths are completely
definable by the user. The devices are capable of generating Signals for both interlaced and noninterlaced modes of
operation. Equalization and serration pulses can be introduced into the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate ·horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the system architecture. Line rate and field/frame rate are all a
function of the values programmed into the data registers,
the status register, and the input clock frequency.
The 'ACT715/LM1882 is mask programmed to default to a
Clock Disable state. Bit 10 of the Status Register, Register
0, defaults to a logic "0". This facilitates (re)programming
before operation. '
The 'ACT715-R/LM1882-R is the same as the
'ACT715/LM1882 in all respects except that the

~

'l"

::D

•

UI

'ACT715-R/LM1882-R is mask programmed to default to a
Clock Enabled state. Bit 10 of the Status Register defaults
to a logic "1". Although completely (re)programmable, the
'ACT715-R/LM1882-R version is better suited for applications using the default 14.31818 MHz RS-170 register values. This feature allows power-up directly into operation,
following a single CLEAR pulse.

Features
• Maximum Input Clock Frequency> 130 MHz
• Interlaced and non-interlaced formats available
• Separate or composite horizontal and vertical Sync and
Blank signals available
• Complete control of pulse width via register
programming
• All inputs are TTL compatible
• 8 mA drive on all outputs
• Default RS170/NTSC values mask programmed into
registers
• 4 KV minimum ESD immunity
• 'ACT715-R/LMt/182-R is mask programmed to default
to a Clock Enable state for easier start-up into
14.31818 MHz RS170 timing

Pin Assignment
forLCC

Pin Assignment for
DIP and SOIC

\J

I?DsDs°4~

O2 -

3

18 t- [jHBYTE

03 04-

4

17 t-LOAO

5

16t-OOO!MN

05 -

6

15 t-HSYNVDR

06-

7
8

14 r-VCSYNC

Dr-

2

1Il1II1]]1ID!I]

20 t-vcc
19 t-ADORjDATA

1

CLR III ~
GNO IiQJ
CLOCK Il] ~
VCBLANK Ii]!
HBLHOR IilI ~

>
>

CLR- 9

12 r- VCBLANK
11 t-CLOCK

~

[II O2

~ [It0l
~ moo

~ ~ Vee
~ Ii]J AODR/DATA

-:::.o(Jl(JlOO"

13 r-HBLHDR

GNO- 10

§.....
UI

•

UI

Connection Diagrams

00 01-

~....

Tl/F/10137-1

Order Number LM1882CN or LM1882CM
For Default R5-170, Order Number LM1882-RC::N or
LM1882-RCM

2-203

TUF/10137-2

~....

§
.....
~

Logic Block Diagram

ADDR/DATA
LHBYIE
LOAD

OOO/EVEN

CLR

VCSYNC
VCBLANK

HBLHDR

............::>

CLOCK

HSYNVDR
TUF/10137-3

Pin Description
There are a Total of 13 inputs and 5 outputs on the
'ACT715/LM1882.
Data Inputs DO-D7: The Data Input pins connect to the
Address Register and the Data Input Register.
ADDR/DATA: The Ai5l5R'/DATA signal is latched into the
device on the falling edge of the LOAD signal. The signal
determines if an address (0) or data (1) is present on the
data bus.
lIHBYTE: The [/HBYTE signal is latched into the device
on the falling edge of the ,LOAD Signal. The signal determines if data will be read into the 8 LSB's (0) or the 4 MSB's
(1) of the Data Registers. A 10n this pin when an ADDRI
DATA is a 0 enables Auto-Load Mode.

ODD/'EVER: Output that identifies if display is in odd (HIGH)
or even (LOW) field of interlace when device is in interlaced
mode of operation. In noninterlaced mode of operation this
output is always HIGH. Data can be serially scanned out on
this pin during Scan Mode.
VCSYNC: Outputs Vertical or Composite Sync signal based
on value of the Status Register. Equalization and Serration
pulses will (if enabled) be output on the VCSYNC signal in
composite mode only.
VCBLANK: Outputs Vertical or Composite Blanking signal
based on value of the Status Register.
HBLHDR: Outputs Horizontal Blanking Signal, Horizontal
Gating signal or Cursor Position based on value of the
Status Register.
HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating
Signal or Vertical Interrupt signal based on value of Status
Register.

LOAD: The LOAD control pin loads data into the Address or
Data Registers on the rising' edge. ADDR/DATA and
LlHBYTE data is loaded into the device on the falling edge
of the LOAD. The LOAD pin has been implemented as a
Schmitt trigger input for better noise immunity.

Register Description

CLOCK: System CLOCK input from which all timing is derived. The clock pin has been implemented as a Schmitt
trigger for better noise immunity. The CLOCK and the LOAD
signal are asynchronous and independent. Output state
changes occur on the falling edge of CLOCK.
CLR: The CLEAR pin is an asynchronous input that initializes the device when it is HIGH. Initialization consists of setting all registers to their mask programmed values, and initializing all counters, comparators and registers. The
CLEAR pin has been implemented as a Schmitt trigger for
better noise immunity. A CLEAR pulse should be asserted
by the user immediately aiter power-up to ensure proper
initialization of the registers-even if the user plans to
(re)program the device.

All of the data registers are 12 bits wide. Width's of all pulses are defined by specifying the start count and end count
of all pulses. Horizontal pulses are specified with-respect-to
the number ,of clock pulses per line and vertical pulses are
specified with-respect-to the number of lines per frame.
REGD-STATUS REGISTER
The Status Register controls the mode of operation, the
Signals that are output and the polarity of these outputs. The
default value for the Status Register is '0 (000 Hex) for the
'ACT715/LM1882 and is "512" (200 Hex) for the 'ACT715R/LM1882-R.

Note: A CLEAR pulse will disable the CLOCK on the 'ACT715/LM1 882 and
will enable the CLOCK on the 'ACT715-R/LM1882-R.

2-204

Register Description

.:...

(Continued)

Bits 0-2

HORIZONTAL INTERVAL REGISTERS

The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses.
REG1- Horizontal Front Porch
REG2- Horizontal Sync Pulse End Time
REG3- Horizontal Blanking Width

B2 B1 Bo VCBLANK VCSYNC HBLHDR HSYNVDR

0 0 0 CBLANK
(DEFAULT)
0 0 1 VBLANK
0 1 0 CBLANK
0 1 1 VBLANK
1
1
1
1

0
0
1
1

0
1
0
1

CBLANK
VBLANK
CBLANK
VBLANK

CSYNC

HGATE

VGATE

CSYNC
VSYNC
VSYNC

HBLANK
HGATE
HBLANK

VGATE
HSYNC
HSYNC

CSYNC
CSYNC
VSYNC
VSYNC

CURSOR
HBLANK
CURSOR
HBLANK

VINT
VINT
HSYNC
HSYNC

REG4- Horizontal Interval Width
VERTICAL INTERVAL REGISTERS

The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.

Bits 3-4

B4

B3

0
0
(DEFAULT)
0
1
0
1
1
1

# of Clocks per Line

REGS- Vertical Front Porch
REG6- Vertical Sync Pulse End Time

Mode of Operation

REG7- Vertical Blanking Width
REG8- Vertical Interval Width

Interlaced Double Serration and
Equalization
Non Interlaced Double Serration
Illegal State
Non Interlaced Single Serration
and Equalization

•

~

...

CD
CD

~
:::D

•

(II

~
...~
......

(II

•

(II

# of Lines per Frame

EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS

These registers determine the width of equalization and serration pulses and the vertical interval over which they occur.
REG 9- Equalization Pulse Width End Time
REG10- Serration Pulse Width End Time
REGll- Equalization/Serration Pulse Vertical
Interval Start Time
REG12- Equalization/Serration Pulse Vertical
Interval End Time

Double Equalization and Serration mode will output equalization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse. In
Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.

CD
CD
N

~
~...
......

Cf1

:::D

VERTICAL INTERRUPT SPECIFICATION REGISTERS

These Registers determine the width of the Vertical Interrupt Signal if used.

Bits 5-8
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates an output pulse active
LOW. A value of 1 indicates an active HIGH pulse.
BS- VCBLANK Polarity
B6- VCSYNC Polarity
B7- HBLHDR Polarity
B8- HSYNVDR Polarity

REGl3- Vertical Interrupt Activate Time
REGl4- Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS

These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating signals.
REG1S- Horizontal Cursor Position Start Time
REGI6- Horizontal Cursor Position End Time
REG17- Vertical Cursor Position Start Time

Bits 9-11
Bits 9 through 11 enable several different features of the
device.
B9- Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
Bl0- Disable System Clock (0)
Enable System Clock (1)
Default values for Bl0 are "0" in the 'ACT715/
LM1882 and "1" in the 'ACT715-R/LM1882-R.
Bll- Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for internal
testing only.

REGl8- Vertical Cursor Position End TIme

Signal Specification
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS

All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not O. All values of the horizontal timing registers are
referenced to the falling edge of the Horizontal Blank Signal
(see Figure 1). Since the first CLOCK edge, CLOCK # 1,
causes the first falling edge of the Horizontal Blank reference pulse, edges referenced to this first Horizontal edge
are n + 1 CLOCKs away, where "n" is the width of the
timing in question. Registers 1, 2, and 3 are programmed in
this manner. The horizontal counters start at 1 and count
until HMAX. The value of HMAX must be divisible by 2. This

2-205

•

Signal Specification

(Continued)

HMAX/2
TLlF/l0137-4

FIGURE 1. Horizontal Waveform Specification
limitation is imposed because during interlace operation this
value is internally divided by 2 in order to generate serration
and equalization' pulses at 2 x the horizontal 'frequencY.
Horizontal signals will change on, the falling edge of. the
CLOCK Signal. Signal specifications are shown below.
Horizontal Period (HPER) = REG(4)x ckper

Vertical
Vertical
Vertical
Vertical

Frame Period (VPER) = REG(8) X hper
Field Period (VPER/n) = REG(8) X hper/n
Blanking Width = [REG'(7) - 11 x hper/n"
Syncing Width = [REG(6) _ REG(5)1 x hper/n

I BI k' W'dth = [REG(3) - 11 x ckper
H ·
onzonta an Ing I
Horizontal Sync Width
= [~EG(2), - REG(1)1 x ckper
Horizontal Front Porch
,= ,[REG(1) - 11 x ckper

where n = 1 for noninterlaced
n = 2 for interlaced '

Vertical Front Porch

=

[REG(5) - 11 x hper/n

COMPOSITE SYNC AND BLANK SPECIFICATION
CompOSite Sync and Blank signals are created by logica!ly
ANDing (ORing) the active LOW (HIGH) signals of the corresponding vertical and horizontal components of these signals. The CompOsite Sync signal may also include serration
and/or equalization pulses. The Serration pulse interval occurs in place of the Vertical Sync interval. Equalization pulses oCCur preceding and/or following the Serration pulses.
The width and location of these pulses can be programmed
through the registers shown below. (See Figure 28.)
Horizontal Equalization'PW = [REG(9) - REG(1)J x ckper
REG 9' = (HFP) + (HEQP)

VERTICAL SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines
per frame. This is true in both interlaced' and noninterlaced
modes of operation;, Care must be taken ·to not specify the
Vertical Registers in terms of lines per field." Since the first
CLOCK edge, CLOCK' ;I' 1, causes the first falling edge of
the Vertical Blank (first Horizontal Blank) reference pulse,
edges referenced to this f,irst edge are n + 1 lines away,
where "n" is the width of the timing in question'. Registers 5,
6, and 7 are programmed in this mannef. Also. in the interlaced mode, vertical timing is based on half-lines. Therefore
registel:S 5, 6, and 7 m\lst contain a value twice the to~1
horizontal (odd and even) plus 1 (as described above). in
non-interlaced mode, all vertical timing is baslld on wholelines. Register 8 is' alV'ays baSed on whole-lines and does
not add 1 for the first cloCk. The vertical coUl)ter starts at
the vafue of 1 and 'counts until the valu~ of VMAX. No' ~e:
strictions exist on the values placed in, the vertical registers.
Vertical Blank will change on the leading: ed!!e of HBLANK.
Vertical Sync will change on the leadi~g edge of HSYNC.
"
',
(See Figure 2A.)

+1
= tREG(4)/n

+ REG(1) REG(10)1 x ckper
REG Hj = (HFP) + (HPER/
2) - (HSERR) + 1
Where n = 1for noninterlaceCl Single serration/equalization
n = 2 for noninterlaced double
serration/equalization
n = 2 for interlaced operation
Horizontal,Serration PW

2-206

Signal Specification

(Continued)
HBWK

VMAX

REGS

t--+--.JREG6
TLlF/10137-5

FIGURE 2A. Vertical Waveform Specification

HBLANK
CSYNC

I:
'I
,I
VSYNC~~~~==1==
REGS

REG.

I

REG12

REGll

1
~'-+----------I----""::::~----+----------..j
EQUALIZATION / SERRATION INTERVAL

TLlF110137-12

FIGURE 2B. Equalization/Serration Interval Programming
HORIZONTAL AND VERTICAL GATING SIGNALS

and Bit 2 of the Status Register is set to the value of 1. The
Cursor Position generates a single pulse of n clocks wide
during every line that the cursor is specified. The signals are
generated by logically ORing (ANDing) the active LOW
(HIG H) signals specified. by the registers used for generating Horizontal· and Vertical Gating signals. The Vertical Interrupt signal generates a pulse during the vertical interval
specified. The Vertical Interrupt signal will change in the
same manner as that specified for the Vertical Blanking signal.

Horizontal Drive and Vertical Drive outputs can be utilized
as general purpose Gating Signals. Horizontal and Vertical
Gating Signals are available for use when Composite Sync
and Blank signals are selected and the value of Bit 2 of the
Status Register is O. The Vertical Gating signal will change
in the same manner as that specified for the Vertical Blank.
Horizontal Gating Signal Width = [REG(16) - REG(15)1
ckper
Vertical Gating Signal Width

x

= [REG(18) - REG(17)1 x

Horizontal Cursor Width = [REG(16) - REG(15)1 x ckper
Vertical Cursor Width = [REG(18) - REG(17)] x hper
Vertical Interrupt Width = [REG(14) - REG(13)] x hper

hper
CURSOR POSITION AND VERTICAL INTERRUPT
The Cursor Position and Vertical Interrupt signal are available when Composite Sync and Blank signals are selected

•
2-207

Addressing Logic
time the High Byte is written the address counter is incremented by 1. The counter has been implemented to loop on
the initial value loaded' into the address register. For example: If a value of 0 was written into the address register then
the counter would count from 0 to 18 before resetting back
to O. If a value of 15 was written into the address register
then the counter would count from 15 to 18 before looping
back to 15. If a value greater than or equal to 18 is placed
into the address register the counter will continuously loop
on this value. Auto addressing is initiated on the falling edge
of LOAD when ADDRDATA is 0 and LHBYTE is 1. Incrementing and loading oi data registers will not commence
until the falling edge of LOAD after ADDRDATA goes to 1.
The next rising E!dge of LOAD will load the first byte of data.
Auto Incrementing is disabled on the falling edge of LOAD
after ADDRDATA and LHBYTE goes low.

The register addressing logic is composed of two blocks of
logic. The first is the address register and counter
(ADDRCNTR), and the second is the address decode
(ADDRDEC).

ADDRCNTR LOGIC
Addresses for the data registers can be generated by one of
two methods. Manual addressing requires that each byte of
each register that needs to be loaded needs to be addressed. To load both bytes of all 19 rE!gisterswould require
a total of 57 load cycles (19 address and 38 data cycles).
Auto Addressing requires that only the initial register value
be specified. The Auto Load sequence would require only
39 load cycles to completely program all registers (1 address and 38 data cycles). In the auto load sequence the
low order byte of the data register will be written first followed by the high order byte on the next load cycle. At the

Manual Addressing Mode
. Load RIsing Edge

LQad Failing Edge .

Cycle '"
1
2

Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
'Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load

3
4
5

6
Add,
REG (m)
D7-DO

~ ~ ~
Lbyte
(m)

Hbyte
(m)

Load Address m
Load Lbyte m
Load Hbytem
Load Address n
Load Lbyte n
Load Hbyte n
Add,
REG (n)

,I

Lbyta
(n)

X

~

Hbyte
(n)

LOAD

'0

ADOR/DATA
[/HBYTE

I

L--'
I

\

\

I

\

r

\
TLlF/l0137-7

Auto Addressing Mode
Cycle '"

Load Falling Edge

Load Rising Edge

1

Enable Auto Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable M/lnual Addressing

Load Start Address n
Load Lbyte (n)
Load Hbyte (n); Inc Counter
Load Lbyte (n+ 1)
Load Hbyte (n + 1); Inc Counter
Load Address

2
3
4
5
6

Add,
REG (n)

Lbyta
(n)

Hbyte
(n)

D7-DO

* *

LOAD

ADOR/DATA
L!HBYTE

\
I

I

~ ~ ~
Lbyte
(n+l)

Hbyte
(n+l)

Add,
REG (m)

5

\

\
TL/F/l0137-8

2-208

I"'"

....
CO

i:

Addressing Logic (Continued)
ADDRDEC LOGIC
The ADDRDEC logic decodes the current address and generates the enable signal for the appropriate register. The
enable values for the registers and counters change on the
falling edge of LOAD. Two types of ADDRDEC logic is enabled by 2 pair of addresses, Addresses 22 or 54 (Vectored
Restart logic) and Addresses 23 or 55 (Vectored Clear logic). Loading these addresses will enable the appropriate logic and put the part into either a Restart (all counter registers
are reinitialized with preprogrammed data) or Clear (all registers are cleared to zero) state. Reloading the same
ADDRDEC address will not cause any change in the state of
the part. The outputs during these states are frozen and the
internal CLOCK is disabled. Clocking the part during a Vectored Restart or Vectored Clear state will have no effect on
the part. To resume operation in the new state, or disable
the Vectored Restart or Vectored Clear state, another nonADDRDEC address must be loaded. Operation will begin in
the new state on the rising edge of the non-ADDRDEC load
pulse. It is recommended that an unused address be loaded
following an ADDRDEC operation to prevent data registers
from accidentally being corrupted. The following Addresses
are used by the device.

ADOR _ _ _ _

~X

ADDRDEC Address

~

•• DUMMY address cannot b. ADDRDEC Address

CO
N

•

~
....
CO
CO

LOAD

~\----l.....---.."--\
• OUTPUTlCOUNT FREEZES
• PART IS IN RESTARTICLEAR
• ORIGINAL PROGRAMMED COUNT
DATA IS RELOADED INTO COUNT
REGISTERS (VECTOR RESTART)
• ALL REGISTERS CLEARED TO
ZERO (VECTOR CLEAR)

f

COUNT RESUMES ATl
PIXEL ONE
(RESTART ONLY)

TUF/10137-9

FIGURE 3. ADDRDEC Timing
GENLOCKING

The 'ACT715/LM1882 and 'ACT715-R/LM1882-R is designed for master SYNC and BLANK signal generation.
However, the devices can be synchronized (slaved) to an
external timing signal in a limited sense. USing Vectored
Restart, the user can reset the counting sequence to a given location, the beginning, at a given time, the riSing edge of
the LOAD that removes Vector Restart. At this time the next
CLOCK pulse will be CLOCK 1 and the count will restart at
the beginning of the first odd line.

Address 0
Status Register REGO
Address 1-18 Data Registers REG1-REG18
Address 19-21 Unused
Address 22/54 Restart Vector (Restarts Device)
Address 23/55 Clear Vector (Zeros All Registers)

~

:u

•

~
.....

~

.....
....

(II

•

(II

~.....
~.........

Cf1
:u

Preconditioning the part during normal operation, before the
desired synchronizing pulse, is necesasry. However, since
LOAD and CLOCK are asynchronous and independent, this
is possible without interruption or data and performance corruption. If the defaulted 14.31818 MHz RS-170 values are
being used, preconditioning and restarting can be minimized
by using the CLEAR pulse instead of the Vectored Restart
operation. The 'ACT715-R/LM1882-R is better suited for
this application because it eliminates the need to program a
1 into Bit 10 of the Status Register to enable the CLOCK.
Gen Locking to another count location other than the very
beginning or separate horizontal/vertical resetting is not
possible with the 'ACT715/LM1882 nor the 'ACT715-RI
LM1882-R.

Address 24-31 Unused
Address 32-50 Register Scan Addresses
Address 51-53 Counter Scan Addresses
Address 56-63 Unused
At any given time only one register at most is selected. It is
possible to have no registers selected.
VECTORED RESTART ADDRESS
The function of addresses 22 (16H) or 54 (36H) are Similar
to that of the CLR pin except that the preprogramming of
the registers is not affected. It is recommended but not required that this address is read after the initial device configuration load sequence. A 1 on the ADDRDATA pin (Auto
Addressing Mode) will not cause this address to automatically increment. The address will loop back onto itself regardless of the state of ADDRDATA unless the address on
the Data inputs has been changed with ADDRDATA at O.

SCAN MODE LOGIC

A scan mode is available in the ACT715/LM1882 that allows the user to non-destructively verify the contents of the
registers. Scan mode is invoked through reading a scan address into the address register. The scan address of a given
register is defined by the Data register address + 32. The
internal Clocking signal is disabled when a scan address is
read. Disabling the clock freezes the device in it's present
state. Data can then be serially scanned out of the data
registers through the ODD/EVEN Pin. The· LSB will be
scanned out first. Since each register is 12 bits wide, completely scanning out data of the addressed register will require 12 CLOCK pulses. More than 12 CLOCK pulses on the
same register will only cause the MSB to repeat on the output. Re-scanning the same register will require that register
to be reloaded. The value of the two horizontal counters and
1 vertical counter can also be scanned out by using address
numbers 51-53. Note that before the part will scan out the
data, the LOAD signal must be brought back HIGH.

VECTORED CLEAR ADDRESS
Addresses 23 (17H) or 55 (37H) is used to clear all registers
to zero simultaneously. This function may be desirable to
use prior to loading new data into the Data or Status Registers. This address is read into the device in a similar fashion
as all of the other registers. A 1 on the ADDRDATA pin
(Auto Addressing Mode) will not cause this address to automatically increment. The address will loop back onto itself
regardless of the state of ADDRDATA unless the address
on the Data inputs has been changed with ADDRDATA at O.

2-209

•

Addressing Logic (Continued)

"

Normal d!lvi<;e oP!lratjon can be resumec;l by loading in a
non-scan address. As the scanning olthe registers is a nondestructij/e scan, the device will resume correct operation
from the 'point at which it was"halted.

Reg
REGO
REGO

RS170 Default Register Values
The tables below shOw the values programmed for the
RS170 Format (using a 14.31818 MHz 'clock signal) and
how they compare against the actual EIA RS170 Specifications. The default signals that will be output are CSYNC,
CBLANK, HDRIVE and VDRIVe. The device initially starts at
the beginning olthe odd fieid of interlace, All signals have
active low pulses and the clock is disabJ.E!d at power up.
Registers 13 and 14 are not involved in the actual signal
information. If the Vertical Interrupt was selected so that a
pulse indicating th!l active lines would be, output.

DValueH
0
,024
23

"

OOp, ' Status Register (715'/LM181l2)
40/l Status Register (715:Fil~~1882-R)

REGl
REG2
FlEG3
REG4

, '91'

157
910

017 HFP End TIme ".'
05B H$YNC Pulse EndTime
09D HBLANK Pulse' End 'Time '
38E Total Horizontal Clocks'

REG5
REG6
REG7
'REG8

7
13
41
525

007 VFP End Time ,',
OOD VSYNC Pulse End Time
029 VBLANKPulse End Time
200 Total Vertical,Lines

,57
REG9
REG10 410
REGll
1
REG12 ' 19

"

Register Description'

039
19A
001
013

,

Equalization Pulse End Time,
Serration Pulse'Start Time
Pulse Interval Start'Fime
Pulse 'Interval End Time

..

41
REG13
029
REG14 ,526 ' 20E

Vert\callnterrupt Activate Time
Vertical Interrupt Deactivate Time

REG15
REG16
REG17
REG18

Horizontal Drive Start Time,
Horizontal Drive End Time
Vertical Drive Start Time
Vertical Drive End Time

911
92
1
21

38F
05C
001
015

Rate
14.3181.8 MHz
15.73426 kHz
59.94 Hz
29.97 Hz

"

Input Clock
Line Rate
Field Rate
Frame Rate

,

PerlQC\
69.841 ns
63.5,5~ P.s
16.683ms
33.367 ';'s

RS170 Horizontal Data
Signal

Width

HFP
HSYNCWidth
HBLANK Width
HDRIVE Width
HEOPWidth
HSERRWidth
HPERiod

%H

p.s

22 Clocks
68 Clocks
156Clo<;ks
91 Clocks
34 Clocks
68CI6cks
910 Clocks

"

,

1.536
4.749
10.895
6.356
2.375
4.749'
63.556

Specification (p.s)
1.5 ±0.1

,"

7.47
17.15
lb.oo
3.74
7,.47
,100,

4~7 ±0.1
10.9 ±O.,2
O.lH ±0.OQ5H
2.3 ±0.1
4.7 ±0.1

RS170 Vertical pata

VFP
VSYNCWidth
VBLANK Width
VDRIVE width
VEOP Intrvl
VPERiod (field) ,
VPERiod (frame)

3 Lines
3 Lines
20 Linlls
11.0 Lines
9 Lines
262.5 Lines
525 Lines

190.67
190.67
1271.12
699.1l:!

7.62
4.20
3.63

16.683ms
33.367,ms '

.. ,'

-

6 EOP Pulses'
6 Serra~on, Pulses
0.075V ± 0.005V
p.04V ± O,OP6V
,9 Lines/Field
,16.683 msl-Field
, 33.367 ms/Frame

",.,

;

2-210

Absolute Maximum Ratings (Note 1)
If Military/Ae~ospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors fO,f availability and specifications.

Junction Temperature (TJ)
Ceramic
Plastic

Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,

-0.5Vto +7.0V

Supply Voltage (Vee>
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee +0.5V
DC Input Voltage (VI)

-20 rnA
+20 rnA

temperature and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.

-0.5Vto Vee +0.5V

DC Output Diode Current (10K)
Va = -0.5V
va = Vee +0.5V
DC Output Voltage (Va)

Recommended Operating
Conditions

-20 rnA
+20mA

Supply Voltage (Vee)

-0.5VtoVee +0.5V

DC Output Source
or Sink Current (10)

±15mA

DC Vee or Ground Current
per Output Pin (Icc or IGNO)

±20mA

4.5Vto 5.5V

Input Voltage (VI)

OVtoVee

Output Voltage (Va)

OV to Vee

Operating Temperature (TA)
74ACT
54ACT

- 65·C to + 150·C

Storage Temperature (TSTG)

175·C
140·C

Minimum Input Edge Rate
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V

- 40"C to + 85·C
-55·Cto + 125·C

(~V/~t)

125 mV/ns

DC Characteristics For 'ACT Family Devices over Operating Temperature Range (unless otherwise specified)

Symbol

ACT/LM1882

54ACT/LM1882

74ACT/LM1882

TA = -55"C
to + 125·C
CL = 50pF

TA = -40"C
to + 85·C

Parameter

Vee
(V)

TA = +25·C
CL = 50pF

Minimum High Level
Output Voltage

4.5
5.5

4.49
5.49

Typ
VOH

4.5
5.5
VOL

Maximum Low Level
Output Voltage

4.5
5.5

0.001
0.001

4.5
5.5

Units

Conditions

Guaranteed Limits

=

4.4
5.4

4.4
5.4

4.4
5.4

V
V

lOUT

3.86
4.86

3.7
4.7

3.76
4.76

V
V

·VIN = VILIVIH
10H = -8mA

0.1
0.1

0.1
0.1

0.1
0.1

V
V

lOUT

0.36
0.36

0.5
0.5

0.44
0.44

V
V

=

-50 ",A

50 ",A

. 'VIN = VILIVIH
10H = +8mA

10LD

Minimum Dynamic
Output Current

5.5

32.0

32.0

rnA

VOLD

=

1.65V

10HO

Minimum Dynamic
Output Current

5.5

-32.0

-32.0

rnA

VOHO

=

3.85V

liN

Maximum Input
Leakage Current

5.5

±0.1

±1.0

±1.0

",A

lee

Supply Current
Quiescent

5.5

8.0

160

80

",A

VIN

=

Vee, GND

ICCT

Maximum ICC/Input

5.5

1.6

1.5

rnA

VIN

=

Vee - 2.1V

0.6

• All outputs loaded; thresholds on input associated with input under test.

Note 1: Test Load 50 pF, 500n to Ground.

2-211

VI

=

Vee,GND

fII

AC Electrical Characteristics

Symbol

Parameter

Vee.
(V)

ACT/LM1882

54ACT/LM1882

74ACT/LM1882

TA = +25°C
CL = 50pF

TA;" ~55"C
to + 125"C
CL = 50pF

TA= -4C)"C
to +85"C
CL=SOpF

Min

Max

Units

Max

Min

Typ

5.0

170

190

130

150

MHz

5.0

190

220

145

175

MHz

5.0

4.0

13.0

15.5

3.5

19.5

3.5

18.5

ns

Clock to ODDEVEN
(Scan Mode)

5.0

4.5

15.0

17.0

3.5

22.0

3.5

20.5

ns

Load to Outputs

5.0

4,0

11.5

16.0

3.0

20.0

3.0

19.5

ns

fMAXI

Interlaced fMAX
(HMAX/2 is ODD)

fMAX

Non-Interlaced fMAX
(HMAX/2 is EVEN)

tpLH1
tpHL1

Clock to Any Output

tpLH2
tpHL2
tpLH3

Max

:

Min

AC Operating Requirements
Symbol

Parameter

Vee
(V)

ACT/LM1882

54ACT/LM1882

74ACT/LM1882

TA = +2!rC

TA = -55"C
to + 125"C

TA = -40"C
to +85°C

Typ
tsc
tsc

Control Setup Time
ADDR/DATA to LOADL/HBYTE to LOAD-

1sd

Data Setup Time
D7..:DOto LOAD +
Control Hold Time
LOAD- toADDR/DATA
LOAD- to LlHBYTE

the

Units

Guaranteed Minimums

5.0

3.0
3.0

4.0
4.0

4.5
4.5

4.5
4.5

ns
ns

5.0

2.0

4.0

4.5

4.5

ns

5.0

0
0

1.0
1.0

1.0
1.0

1.0
1.0

ns
ns

thd

Data Hold Time
LOAD+ to D7-DO

5.0

1.0

2.0

2.0

2.0

ns

tree

LOAD + to CLK (Note 1)

5.0

5.5

7.0

8.0

8.0

ns

twldtwld+

Load Pulse Width
LOW
·HIGH

5.0
5.0

3.0
3.0

5.5
5.0

5.5
7.5

5.5
7.5

ns
ns

twclr

CLR Pulse Width HIGH

5.0

5.5

6.5

9.5

9.5

ns

twek

CLOCK Pulse Width
(HIGH or LOW)

5.0

2.5

3.0

4.0

3.5

ns

Note 1: Removal of Vec10red

Reset or Restart to Clock.

Capacitance
Parameter

Typ

Units

Conditions

CIN

Input CapaCitance

7.0

pF

Vee = 5.0V

CpO

Power DisSipation
Capacitance

17.0

pF

Vee = 5.0V

Symbol

2-212

~------------------------------------------------------------------------------------,

AC Operating Requirements

(Continued)

ri:
.....

gg

N

•

LOAD

ri:
.....

gg

CLOCK

~
::D

•

en

OUTPUTS

~

_ _ _ _oJl

Do-o, _ _ _-'l~~~.../I'----

LOAD

~

--"""'I---t.ld---Ir----""'\I
I ' - - - -....' / - - t.'d - - . J '......-

.....
en

•

en

LHBYTE
ADDRDATA

~....

"",,.---""\1.,.----"",,.-----TL/F/l0137-6

FIGURE 4. AC Specifications

Additional Applications Information
POWERING UP
The 'ACT715/LM1882 default value for Bit 10 of the Status
Register is O. This means that when the CLEAR pulse is
applied and the registers are initialized by loading the default values the CLOCK is disabled. Before operation can
begin, Bit 10 must be changed to a 1 to enable CLOCK. If
the default values are needed (no other programming is required) then Figure 5 illustrates a hardwired solution to facilitate the enabling of the CLOCK after power-up. Should control signals be difficult to obtain, Figure 6 illustrates a possible solution to automatically enable the CLOCK upon power-up. Use of the 'ACT715-R/LM1882-R eliminates the
need for most of this circuitry. Modifications of the Figure 6
circuit can be made to obtain the lone CLEAR pulse still
needed upon power-up.
Note that, although during a Vectored Restart none of the
preprogrammed registers are affected, some signals are affected for the duration of one frame only. These signals are
the HOrizontal and Vertical Drive signals. After a Vectored
Restart the beginning of these signals will occur at the first
CLK. The end of the signals will occur as programmed. At
the completion of the first frame, the signals will resume to
their programmed start and end time.

PREPROGRAMMING "ON·THE·FLY"
Although the 'ACT715/LM1882 and 'ACT715-R/LM1882-R
are completely programmable, certain limitations must be
set as to when and how the parts can be reprogrammed.
Care must be taken when reprogramming any End Time
registers to a new value that is lower than the current value.
Should the reprogramming occur when the counters are at a
count after the new value but before the old value, then the
counters will continue to count up to 4096 before rolling
over.
For this reason one of the following two precautions are
recommended when reprogramming "on-the-fly". The first
recommendation is to reprogram horizontal values during
the horizontal blank interval only and/or vertical values during the vertical blank interval only. Since this would require
delicate timing requirements the second recommendation
may be more appropriate.
The second recommendation is to program a Vectored Restart as the final step of reprogramming. This will ensure
that all registers are set to the newly programmed values
and that all counters restart at the first CLK position. This
will avoid overrunning the counter end times and will maintain the video integrity.

20

7
4
A
C
T
7
1
5

CLEAR

LOAD

TIME
CLEAR INPUT

10

19

ADDR/DATA

18

I/H

17

LOAD INPUT

16

ODDEVEN

BYTE

15

VDRIVE

14

CSYNC

13

HDRIVE

12

CBLANK

11

CLOCK

TUF/l0137-10

FIGURE 5. Default RS170 Hardwire Configuration
2-213

~.........
en

•
::D

Additional Applications Information (Continued)
Vee

Rl

GND
2

CI

I

M
M
7
4
H

C
Rl

Vee

4
2
3
A

16
15

14

C2

Rl

13

CLEAR PIN

12

LOAD PIN
. (NOT NECESSARY
FOR 'ACT7~5-R/
LM 1882-R

11
10

I

C1
TL/F/l0137-11

Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND

Components
Rl: 4.7k
R2: 10k

Cl: 10 I'F
C2: 50 pF

FIGURE 6. Circuit for Clear and Load Pulse Generation

2·214

Ii:
N

co
co

f}1National Semiconductor

CD

LM2889 TV Video Modulator
General Description

Features

The LM2BB9 is designed to interface audio and video signals to the antenna terminals of a TV receiver. It consists of
a sound subcarrier oscillator and FM modulator, video
clamp, and RF oscillators and modulators for two low-VHF
channels.
The LM2BB9 allows video information from VTRs, video disk
systems, games, test equipment, or similar sources to be
displayed on black and white or color TV receivers.

• Pin for pin compatible with LM1BB9 RF section
• Low distortion FM sound modulator (less than 1 %
THO)
• Video clamp for AC-coupled video
• Low sound .oscillator harmonic levels
• 10V to 16V supply operation
• DC channel switching
• Excellent oscillator stability
• Low intermodulation products

Block and Connection Diagrams (Dual-In-Line Package)
AUDIO
INPUT

14 SOUND
SUPI'lY

1

VIDEO 2
CLAMP

GROUNO

r--. ____

4

-t-=-=-11 =~

1

Order Number LM2889N
See NS Package Number N14A

CH B
TANK

10 VIDEO
REFBlEHCE

6
CHA
TANK

9 CH A

OUTPUT

1

8 CH B
OUTPUT

TOP VIEW

DC Test Circuit
14

lOOk

13

V.

Is

~Vs

+

12V

--.;a

12

Uk

11

}CHB
}CHA
+
v,

1k

10
9

1k

8

lk

5.1k

-=

+
Vc

*"0.,,,,,

1M

TUH/5079-1

2-215

Absolute Maximum Ratings
Storage Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

18Vee
700mW

Power Dissipation Package (Note 1)
Operating Temperature Range

- 55·C to + 150·C

(V14-V13) Max

± 5Vee

(V12-V8) Max

7Vee

(V12-V9) Max

?Vee
2600C

Lead Temperature (Soldering, 10 seconds)

OOCto +700C

DC Electrical Characteristics
(DC test circuit, all switches normally pos. 1, Vs= 12V, VA=2V, VB=Ve=10V)
Parameter

Conditions

Min

Supply Current Is
Sound Oscillator Current al13

Change VA from - 2V to + 2V

".

Change SW2 from Pos. 1 to Pos. 2

Video Clamp Voltage V2
Unloaded
Loaded

SW3Pos.3

Max

Units

10

16

25

mA

0.2

0.35

0.6

mA

Sound Oscillator Zener Current 113
Sound Modulator Audio Current al13

Typ

5.0

0.85

mA

0.9

mA

5.25
5.1

5.5

Vee
Vee

Video Clamp Capacitor Discharge
Current (Vs-V2)/105

SW3Pos.2

Ch. A Oscillator OFF Voltage, V6, V7

SW1 Pos.2

Ch. A Oscillator Current Level 17

VB=10V, Ve=11V

2.5

3.5

Ch. B Oscillator Current Level 14

SW1 Pos. 2, VB=10V, Ve=11V

2.5

3.5

5.0

mA

Ch. A Modulator Conversion Ratio
aV9/(V11-V10)

Measure a V9 by Changing from
Ve=10V, Ve= 1W, to VB=1W,
Ve= 10V; Divide by V11-V10

0.3

0.50

0.75

VIV

Ch. B Modulator Conversion Ratio
aV8/(V11-V10)

'SW1 Pos. 2, Measure a
by
Changing from VB= 10V, Ve=1W,
to VB= 1W, Ve= 10V; Divide by
V11-V10

0.3

0.50

0.75

VIV

20

/-LA

2

Ch. B Oscillator OFF Voltage V4, V5

mVee
5.0

2

mA
mVee

va

AC Electrical Characteristics (ACtestcircuit, Vs=12V)
Parameter

Conditions

Min

Typ

Max

Units

3.4

Vp-p

Sound Modulator Deviation

af/aVIN, SW1 Pos. 2, Change VIN from 1.4V
to 1.0V, Measure af at Pin 13, Divide as Shown

250

Hz/mV

Ch.3 RF Oscillator Level vB, v7

Ch. Sw. Pos. 3,f= 61.25 MHz, Use FET Probe

550

mVp-p

Ch. 4 RF Oscillator Level, v4, v5,

Ch. Sw. Pos. 4, f=67.25 MHz, Use FET Probe

550

mVp-p

RF Modulator Conversion Gain VOUT/(V10-V11)

Ch. Sw. Pos. 3, f = 61.25 MHz. (Note 2)

10

mVrmslV

Sound Carrier Oscillator Level (V13)

Note 1: For operation in ambient temperatures above 25"C. the deVIce must be derated besed on a 15O"C maximum iunction temperature and a thermal resistance

of BO"C/W iunction to ambient.
Note 2: Conversion galn shown is measured with 750 input RF meier which makes the AC RF outpulload 37.50.

2-216

r-

Design Characteristics (AC test circuit, Vs = 12V)
Parameter

Typ

Units

Sound Modulator Audio THO at ± 25 kHz Deviation, VIN must be 1 kHz Source,
Demodulate as Shown in Figure 1

0.8

%

Sound Modulator Input Impedance (Pin 1)

1.5

kO

Sound Modulator Bandwidth

100

kHz

See Curves

Oscillator Supply Dependence, Sound Carrier, RF
Oscillator Temperature Dependence (IC Only)
Sound Carrier
RF

-15
-50

ppml'C
ppml'C

RF Oscillator Maximum Operating Frequency (Temperature Stability Degraded)

100

MHz

30

dB

5
3

%
degrees

-12
-20

dB
dB

RF Modulator
Carrier Suppression (Adjust Video Bias for Minimum RF Carrier at VQUT
and Reference to VQUT with 3V Offset at Pins 10 and 11, See Applications
Information, RF Modulation Section)
3.58 MHz Differential Gain
Differential Phase
2.5V Vp-p Video, 87.5% Mod
Output Harmonics below RF Carrier
2nd,3rd
4th and Above
Input Impedance, Pin 10, Pin 11

1 MO//2pF

AC Test Circuit
1 SWI

14

..L
-:;t".

0.01

r--"22:it-- 1-1

~

I~'
+---f' ~ I :~K5&741tM
iL ______
5l~ ...1I

I
....1_3_ _ _--f-t-

-~I~F
,-

7.5k

VIDEO

12

INPUT

TO.001~F
240

4

11

21I2V..l.68pF

TURNS,c

240

'e,.

.!. T O.OOI~F

CH ",--CH4
SWI __

1

_

·240

TURNSY

1110

240

T

5

10

'~

+~

1:'

6

2112f.t

CH3

VIDEO

.,-'

l..

T

75PF
75

7

O.001 "F

POUT

~--------------------------------------------------~~~
,_ i.! 12V
10~*

TLlH/5079-2

2-217

~
N
CO
CO
CD

en

I

r-------------------------------------------------------------------------------------~

5pF

Test Circuit

TO PIN 13
OF LM2889

....I

-1 H - -.....

16

I

14

13
LM3089
12

t'1_1_ _ _ _""""4_~

~0.1""
j-:l:;.O_ _ _-,~

9.1k

l

0.18mH

II
I
TOKO I
L
K5674:.JI
I ______
TUH/S079-3

FIGURE 1.4.5 MHz Sound FM Demodulator

Typical Performance Characteristif,:s (Refer to AC test circuit unless noted)

~
i
iii

Sound Carrier Oscillator
Supply Dependence
(fo = 4.5 MHz, Pin 1 Open)

12
10

i§

, ~""""

8

-4

I

-8

5

~-lo

~-20 ~
0S-30

'f'
~

iii... 4o

I/'

a- 60

::Ii -80
- 90

10 11 12 13 14 15 16 17 18

10 .11 12 13 14 15 16 17 18

SUPPLY VOLTAGE (VI

SUPPLY VOLTAGE (VI

FM Sound Modulator
Dynamic Characteristics
(fMOD = 1 kHz)

14 1'l'7."""~:>177."",,,,"'777."""'!:a

TO

12

:!!

'F-+-+-+-+++-I
6 t-t-+-+-+-+++-I

;

4

§

...i

60

z

50

±!.

110

iIE

,

~-7D
"-

RF Modulator CommonMode Input Range
Pins .10, 11 (Circuit'
Diagrams)

~

.....

1/

!-5o

If

-6

=

i

~

i
I:= -20
i

RF Oscillator Frequency
Supply Dependence
10 (fO=67.25 MHz)

;

8 .....

2.35

;!

~

40

DEVlAnD

;tiii ,,_30

1:::o::::Jt::::i:::±",±::±::±:±:"J

iii 10
IE

o

o

10 11 12 13 14 15 16 17 18

~'f'

THO

1.7
1.35

~~

il

II- ....
~~

1.0 ; ;
0.7

0.35

~

0

60 60 100 1m 140160

AUDIO INPUT. PIN 1 (mVrmsl

2-218

J

~
om 40

SUPPLY VOLTAGE (VI

V

./

I~

2.0 ~~

TL/H/S079-4

r-----------------------------------------------------------------------------,
Circuit Description (Refer to Circuit Diagrams)
The sound carrier oscillator is formed by differential amplifier 03, 04 operated with positive feedback from the pin 13
tank to the base of 04. Frequency modulation is obtained
by varying the 90 degree phase shifted current of 09. 014's
emitter is a virtual ground, so the voltage at pin 1 determines the current R11, which ultimately modulates the collector current of 09.
The video clamp is comprised of devices 058-060. The
clamp voltage is set by resistors R40, R41, R49, and R50.
The t:. VBE/R42 current sets the capacitor discharge current. 059 and the above mentioned resistor string help
maintain a temperature stable clamp voltage.
The channel B oscillator consists of devices 024 and 025
cross-coupled through level-shift zener diodes 022 and
023. A current regulator consisting of devices 017-021 is
used to achieve good RF stability over temperature and

supply. The channel B modulator consists of multiplier devices 028-031,034 and 035. The top quad is coupled to
the channel B tank through isolating devices 026 and 027.
A DC potential between pins 10 and 11 offsets the lower
pair to produce an output RF carrier at pin 8. That carrier is
then modulated by both the sound subcarrier at pin 10 and
the composite video signal at pin 11. The channel A modulator shares pin 10 and 11 buffers, 032 and 033, with channel B and operates in an identical manner.
The current flowing through channel B oscillator diodes
022, 023 is turned around in 036-038 to source current
for the channel B RF modulator. In the same manner, the
channel A OSCillator 054-057 uses tum-around 049-051
to source the channel A modulator. One oscillator at a time
may be activated by its current turn-around, and the other
oscillator/modulator combination remains off.

Circuit Diagrams
SOUND
TANK

SOUND
SUPPLY

13

14

R13
10k

C2
15pF

q

R3
lk

TL/H/5079-5

2-219

~

iii:

~

CD
CD

LM2889

o

:;"C
CHANNEL B

CHANNEL B
TANK

OUTPUT

=--=-

RF
SUPPLY

;:;

CHANNEL A
TANK

CHANNEL A

c

=--=- .

OUTPUT

i"

CO
CD

....

R45
3&0

R43
3&0

R39
1k

R40
Bk

3(II

i2

R46

3&0

054

022

~

< ~R3&
2k7
1k

---

I\)

~

CLAMP
INPUT
1155

R38
2k7

lR42
5k1

1:
':'

I 032

VIDEO 0 111
INPUT

~

033 ~ VIDEO BIAS
AND SOUND INPUT

R47

750

':'

':'

':'

':'

':'

':'

':'

':'

':'
TLlHI5079-6

r-----------------------------------------------------------------------------, r

i:

Applications Information
SOUND FM MODULATOR
Frequency deviation is determined by the Q of the tank circuit at pin 13 and the current entering the audio input, pin 1.
This current is set by the input voltage VIN, the device input
impedance (1.5 kO), and any impedance network connected externally. A signal of 60 mVrms at pin 1 will yield about
± 25 kHz deviation when configured as shown in Ftgure 2.

RF MODULATION
Two RF channels are available, with carrier frequencies up
to 100 MHz being determined by L-C tank circuits at pins
4/ 5 and 6/7. The signal inputs (pins 10 and 11) are common to both modulators, but removing the power supply
from an RF OSCillator will also disable that modulator.
The offset between the two signal pins determines the level
of the RF carrier output. To preserve the DC content of the
video signal, amplitude modulation of the RF carrier is done
in one direction only, with increasing video (toward peak
white) decreasing the carrier level. This means the active
composite video signal at pin 11 must be offset with respect
to pin 10 and the sync pulse should produce the largest
offset.
The largest video signal (peak white) should not be able to
suppress the carrier completely, particularly if sound transmission is needed. This requires that pin 10 be biased
above the largest expected video signal. Because peak
white level is often difficult to define, a good rule to follow is
to bias pin 10 at a level which is four times the sync amplitude above the sync tip level at pin 11. For example, the DC
bias at pin 10 with 0.5V sync clamped to 5.2V on pin 11,
should be 5.2+ (4XO.5)=7.2V.

VIDEO CLAMP
When video is not available at DC levels within the RF modulator common-mode range, or if the DC level of the video is
not temperature stable, then it should be AC-coupled as
shown in the typical applications circuit (Figure 2). The
clamp holds the horizontal sync pulses at 5.2V for Vs = 12V.
The clamp coupling capacitor is charged during every sync
pulse and discharged when video information is present.
The discharge current is approximately 20 pA This current
and the amount of acceptable tilt over a line of video determines the value of the coupling capacitor C1. For most applications 1 ,...F is sufficient.

Typical Application
SDUNDSUPPLV+-+=-+-_--------,

R12
3.9k

RID
&.III

CH4

CID

'---+'....._____"':1100/\7.--_ _.. ID.,"':" ~:k

CH 3

L4
O.47,dt
L5

0.47 ""

R13
2110

R6

1110
V,
12V
TL/H/5079-7

FIGURE 2. Two Channel Video Modulator with FM Sound

2-221

i

~ r-------------------------~----------~----------------------------------_,

I

~

Pin 2-Video Clamp: ,The video ,clamp restores the DC
component to AC-coupled video. The video is AC-coupled
to the clamp via C3. DecreasingC3 wifl.cause a larger tilt
between vertical sync pulses ,in the clamped video waveform.

Applications Information (Continued)
When the signal inputs are exactly balanced, ideally there is
no RF carrier at the output. Circuit board layout is critical to
this measuremen~. For optimum performanc.e, the output
and supply deooupling. Circuitry should be configured as
shown in Figu;e 3.
.

Pin 3-Ground: Although separate on the chip level, all
ground terminate at pin 3.
Pins 4/S-:-Channel 4 Oscillator: Pins 4 and 5 are the collector outputs of the channel 4 oscillator. L1 and C5 set the
oscillator frequency defined by fo= 0.1591 v'[1'cK Increasing,L1 ~iII decrea~ the oscillator frequency while decreasing L1 will increase the oscillator frequency. Decreasing C5
will increase the oscillalor frequency, and lower the tank Q
causing possible drift problems. Ri! lind R3 are the oscillator
loads Which determine the oscillator amplitude and the tank
Q. Increasing these resistors 'increases the Q and the oscillator amplitude, possibly overdrivil'!g the RF modulator,
which will incre,ase output RF harmonics. Decreasing R2
and R3 reduces the tank Q and may cause'increased drift.
C4 is an RF decoup,ing capaCitor. Increasing C4 may iesult
in less effective decoupling at RF. Decreasing C4 may i[1troduce RF to supply coupling.
',

PIN 12 -I1--t---1~~O Vs

-L~12

R7~ 0.1,.F.
~0'OO.1
'75
.
PIN 8

-+-....1
I

'"

OUT~UT

":'

RF
CONNECTOR
TLlH/5079-8

RF decouple supply directly to oUtput ground.

FIGURE 3. Correct RF Supply Oecoupling
The video clamp level is derived from a resistive divider con·
nected to supply (VS). To maintain good supply rejection,
pin 10, which is biased externally, should·also be referenced
to supply (see Figure 2).
.,

Pins 617-Channel3 Oscillator; Pins 6 and 7 are the channel 3 oscillator outputs. Every component at these pins has
the same purpose and effect as those at pins 4 and 5.
Pin 8-Channel 4 RF Output: Pin 8 is the channel 4 RF
output and R13 is the load resistor. The RF signal is AC
coupled via C15 to the output filter which is a two channel
VSB filter. L5 is parallel resonant with the filter input capacitance minimizing loss in the output network. R14 terminated
the filter output.
,Pin &-Channel 3 RF Output: Pin 9 is the channel 3 RF
,output with all components performing the same functions
as those in the pin 8 description.

Pin Description (Refer to Figure 2)
Pin 1-Audlo Input: Pin 1 is the audio input to the sound
FM generator. Frequency deviation is proportional to the
signal at this pin. A pre·emphasis network comprised of R1,
C2, and the device input impedance yields the following response with an 80 mVrms audio input.
Pre-Emphasis Network
Response

r-"":""'_-'----j--'

i

25

~

ro ~------~----/--~-i

i

i
,..

is

I

15

/

10

r:;::;:;;;-r:'---I
~

5t----+----I
O'---~--'---'-----'

200

2k
AUOIO INPUT FREQUENCY (Hz)

rok
TLlHl5079-9

Increasing R1 lowers the boost frequency. and decreases
deviation below the boost frequency. Increasing C2 only
lowers the boost frequency. C1 is a coupling capaCitor, and
must be a low impedance compared to the sum of R1 and
the device input impedance (1.5 kO).

Pin 1G-RF ~odulator Sound Subcarrier Input: Pin 10 is
one of the RF modulator inputs and may be used for video
or sound. It is used as a sound subcarrier input in Figure 2.
RB, R9, and R10 set the DC bias on this pin which determines the modulation depth of the RF output (see Applica, . tion Notes). R12 and Cll AC-couple the sound subcarrier
from the sound mOdulator'to the RF modulator. R12 and
R11 form' a resistive divider that determines the level of
sound at pin 10, which in turn sets the picture carrier to
sound subcarrier ratio. Increasing the ratio of R11 tR12 will
increase the sound subcarrier at the output. C10 forms an
'AC ground. preventing RB, R9, and R10 from having any
effects on the circuit other than setting the DC potential at
pin 10. R11 and R12 also effect the FM sound modulator
(see pin 13 description).

2·222

Pin Description (Continued)
Pin 11-Video Input: Pin 11, when configured as shown, is
the RF modulator video input. In this application, video is
coupled directly from the video clamp. Alternatively, video
could be DC-coupled directly to pin 11 if it is already within
the DC common-mode input range of the RF modulator (see
curves). In any case, the video sync tip at pin 11 must have
a constant DC level independent of video content. Because
of circuit symmetry, pins 10 and 11 may be interchanged.
Pin 12-RF Supply: Pin 12 is the RF supply, with C12 and
C7 serving as RF decouple capacitors. Increasing 'C12 or
C7 may result in less effective RF decoupling, while decreasing them may cause supply interaction. It is important
that C7 be grounded at the R F output ground.
Pin 13-Sound Tank: Pin 13 is the collector output of the
sound oscillator. L3 and C13 determine the oscillating frequency by the relationship fo=0.159IVL3C13. Increasing
L3 or C13 will lower the operating frequency, while decreasing them will raise the frequency. L3 and Ct3, also help
define the Q of the tank, on which FM modulator deviation level depends. As C13 increases, Q increases, and
frequency deviation decreases. Likewise, decreasing C13 .
increases deviation. The other, factor concerning Q is the

external resistance across the tank. The series combination
R11 +R12 usually dominates the tank Q. Decreasing this
resistive network will decrease Q and increase deviation. It
should be noted that because the level of phase modulation
of the 4.5 MHz Signal remains constant, variation in Q will
not effect distortion of the frequency modulation process if
the audio at pin 1 is left constant. The amplitude of the
sound subcarrier is directly proportional to Q, so increasing
the unloaded Q or either of the resistors mentioned above
will increase the sound subcarrier amplitude. For proper operation of the frequency modulator, the sound subcarrier
amplitude should be greater than 2 Vp-p.
Pin 14-Sound Supply: Pin 14 is the sound supply and C14
is an RF decouple capacitor. Decreasing C14 may result in
increased supply interaction.

Printed Circuit Layout
Printed circuit board layout is critical in preventing RF feedthrough. The location of RF bypass capacitors on supply is
very important. Figure 4 shows an example of a properly
layed out circuit board. It is recommended that this layout be
used.

TLlH/5079-10

FIGURE 4. Printed Circuit Board and Component Diagram
(Component Side 1X)

2-223

~ ~------------------------------------------------------------------------------------,

$:!

~

tflNat,ional Semiconductor
LM6104
Quad Gray Scale Current Feedback Amplifier
General Description

Features (Typical unless otherwise noted)

The LM6l 04 quad 'amplifier meets the requirements of battery operated liquid crystal displays by' providing high speed
while maintaining low power consumption,
Combining this high speed with high integration, the
LM6l04 conserves valuable board space in portable systems with a cost effective, surface mount quad package.
Built on National's advanced high speed VIPTM (Vertically
Integrated PNP) process, the LM6l 04 current feedback architecture is easily compensated for speed and loading conditions. These features make the LM6l 04 ideal for buffering
grey levels in liquid crystal displays.

•
•
•
•
•
•

Low power.
Slew rate
-3dB bandwidth (RF = 1 kn)
High output drive
Wide operating range
High integration

Is = 875 p.Alamplifier
1OOV/ p.s
30 MHz
±5V into lOOn
Vs = 5V to ±12V
Quad surface mount

Appllca~ions
•
•
•
•

Grey 'level buffer for liquid crystal ,displays
Column buffer for portable'LCDs
Video distribution amplifiers, video line drivers
Hand-held, high speed signal conditioning

Typical Application
LCD Buffer Application for Grey Levels

TL/H/11979-1

Connection Diagram
14 OUTPUT 4

OUTPUT 1
INVERTING INPUT 1...:..a.......lr--'
,NON-INVERTING 3
INPUT 1 4
V+
NON-INVERTING 5
INPUT 2
INVERTING INPUT 2 ----.,---, ---,

13 INVERTING IN~UT 4
12 NON-INVERTING
11 INPUT 4
V10 NON-INVERTING
INPUT 3
9 INVERTING INPUT 3
8 OUTPUT 3

OUTPUT 2

TL/H/11979-2

Order Number LM6104M
See NS Package Number M14A

2-224

Absolute Maximum Ratings (Note 1)
Storage Temperature Range
Maximum Junction Temperature
ESO Rating (Note 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
24V
Supply Voltage
±6V
Oifferentiallnput Voltage
Input Voltage
± Supply Voltage
Inverting Input Current
15mA
Soldering Information
215·C
Vapor Phase (60s)
2200C
Infrared (15s)

Electrical Characteristics
The following specifications apply for V + = av,

V-

-65·C';; TJ';; +150·C
150·C
2000V

Operating Ratings
4.75Vto24V
Supply Voltage Range
Junction Temperature Range (Note 3)
-20· ,;; TJ ,;; +ao·c
LM6104M

= -5V, RL = RF = 2 kO and o· ,;; TJ ,;; 60·C unless otherwise noted.
LM6104M

Symbol

Conditions

Parameter

Typical
(Note 4)

Limits
(Note 5)

Units

Vas

Input Offset Voltage

10

30

mVmax

18

Inverting Input Bias Current

5.0

20

/A-Amax

Non-Inverting Input Bias Current

0.5

2

/A-Amax

Is

Supply Current

Va = OV

3.5

4.0

mAmax

Isc

Output Source Current

Va = OV
IIN(-) = -100/A-A

60

45

mA
min

Output Sink Current

Va = OV
IIN(-) = 100 /A-A

60

45

mA
min

Positive Output Swing

IIN(-) = -100/A-A

6.5

6.1

Vmin

Va

Negative Output Swing

IIN(-) = 100 /A-A

-3.5

-3.1

V max

PSRR

Power Supply Rejection Ratio

Vs = ±4to ±10V

70

60

dB min

100 mV pp

40

30

dB min

10

5

MOmin

@

100 kHz

RT

Transresistance

SR

Slew Rate

(Note 6)

100

55

V//A-smin

BW

Bandwidth

Av =-1
RIN=RF=2kO

7.5

5.0

MHz

Amp-to-Amp Isolation

RL=2kO
F = 1 MHz

60

dB

V+ - 1.4V
V- + 1.4V

V

60

dB

240

ns

CMVR

Common Mode Voltage Range

CMRR

Common Mode Rejection Ratio

ts

Settling Time

0.05%, 5V Step, Av = -1
RF = Rs = 2 kO, Vs = ±5V

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions. Operating ratings indicate condijions the device is intended to be functional. but device perameter specifications
may not be guaranteed under the condijions.
Note 2: Human body model 1.5 kll and 100 pF. This is a class 2 device rating.
Note 3: Thermal resistance of the SO package is 9IrC/W. When operating at TA = 8O"C, maximum power dissipation is 700 mW.
Note 4: Typical values represent the most likely parametric norm.
Note 5: All limits guaranteed at operating temperature extremes.

Note 6: Av = -1
and 5.6V to 0.6V.

wijh

R'N

=

RF = 2 kll. 51ewrate is caiculatedfrom the 25% to the 75% point on both rising and falling edges. Output.wing is -O.BVto +5.BV

2-225

•~

CD

:E

Typical Performance Characteristics

....I

Frequency Response vs
Closed Loop Gain

Amplifier to
Amplifier Isolation

70r;TITmr"rnmrTTmmrTn~

120

60~+H~++~~~~~~

Av--I~:itW
R,=
2kll

110

5°rt~~~~-H~~~~
~o~~~~~rttffifflr~~

~~

20~~~tH~~~~+W~
10~~~~HI~~~~~

o

J

Am Iifier #2 and #3

~

+25 0 C

,r-

#4

-<25°C

70

-10
-20

60

-30
0.Q1

10

1

100

10

6

10

S

g

R,=lkn ....

I!:
,0

--2
200

600

1000

1~00

=5.1 kll
ill = 10kll

-25
-30 V+ = BY
-35
-40

v- = 5V

TA

=+25°C

"'J

I

-1

~

:::
-2

~

!i1
~

1.0 and negative output voltages.
-25

0 '

FREQUENCY (MHz)

-3

50

75

LM6104 OUtput Voltage
vs Sink Current

---- - "
:--

~~

5
:?

I.---

Vs = .5V

Vs = :t5V

-~

. 0

25

rtMPERATliRE (OC)

LM6104 Output Voltage
vs Source Current

~

Curves apply, to both positive

I

100

10

TIME (ns)

Q

VOUT Referred to Supplies
Vs = ±5V
liN = ± 100 /LA

I!Un

IIIIII
IIIIII

0.1

1800

1.4

~

-20

I I

12

'+7.SmA LOAD

-15

~

R,=2kn

""

-10

il

R,~~.~kll

10

R, = 2kn

-5

3
z

II

!:;
'~

8

SUPPLY VOLTAGE (±V)

R,= 1 kll

0

R,= 10kn

~

1000

Frequency Response vs RF
Ay = -1,RF = RG

V+ =8V
v- = -5V
TA = 25°C

~

100

FREQUENCY (kHz)

Large Signal Pulse Response
Av =-1

-200

o
o

50

0.1

FREQUENCY (MHz)

5

III
III

+85 0 C

80

3: '90

III
III

Am lifier # 1 Dri v.n

100

S

30~~~~~~~~~~

Supply Current vs
Supply Voltage,
5

1

10

20

30

40

50

o

60

OUTPUT SOURCE CURRENT (rnA)

10

20

30

40

50

60

OUTPUT SINK CURRENT (rnA)

TL/H/119i9~3

2-226

Applications Information
CURRENT FEEDBACK TOPOLOGY

Bandwidth and slew rate are inversely proportional to the
value of RF (see typical curve Frequency Response vs RF).
This makes the amplifier especially easy to compensate for
a desired pulse response (see typical curve Large Signal
Pulse Response). Increased capacitive load driving capability is also achieved by increasing the value of RF.
The LM6104 has guaranteed performance with a feedback
resistor of 2 kG.

The small-signal bandwidth of conventional voltage feedback amplifiers is inversely proportional to the closed-loop
gain based on the gain-bandwidth concept. In contrast, the
current feedback amplifier topology, such as the LM6104,
enables a signal bandwidth that is relatively independent of
the amplifier'S gain (see typical curve Frequency Response
vs Closed Loop Gain).
.

FEEDBACK RESISTOR SELECTION: RF
Current feedback amplifier bandwidth and slew rate are
controlled by RF. RF and the amplifier's internal compensation capacitor set the dominant pole in the frequency response. The amplifier, therefore, always requires a feedback resistor, even in unity gain.

CAPACITIVE FEEDBACK
It is common to place a small lead capacitor in parallel with
feedback resistance to compensate voltage feedback amplifiers. Do not place a capaCitor across RF to limit the bandwidth of current feedback amplifiers. The dynamic impedance of capaCitors in the feedback path of the LM6104, as
with any current feedback amplifier, will cause instability.

•
2-227

II)
C)

:s~d

pNa~ional

PRELIMINARY

.Semiconductor

LM8305-STN LCD Display Bias Voltage Source
General Description

Features

The LM8305M contains 'five buffered voltage sources to
provide the voltage ratios required to drive a standard STN
LCD display panel using a time-multiplexed voltage waveform to lICtivate, or deactivate, a .pixel once every picture
frame. The internal resistor array features a binary weighted
array to allow the user to select the proper ratio for the
display being driven. The user can use an external resistor
to set the ratio, if desired.
The LM8305 has a maximum operating supply voltage of
50V to support higher multiplexing rates.
The LM8305 also features an internal high side PNP switch,
and an independent voltage comparator with an internal
bandgap reference.

•
•
•
•
•
•

High operating voltages, 50V maximum
Internal resistor array with binary weighting
Ratios from 1/6 to 1/37
Optional external· resistors
High-side PNP switch from Vee
Separate voltage comparator circuit with band-gap voltage reference
• Surface mount 24-pin package

Typical Application

Connection Diagram
Cnd

1°

24

Vcc

On/Off

23

Switch Out

VC2

22

VREF1

V1N2

21

VREF2

RX1

20

VO

RX2

19

V1

RX3

18

V2

RX4

17

V3

RX5

16

V4
Reset

RX6

10

15

VC1

11

14

Gnd

VSense

VOO
TLlH/12345-2

Top View

See NS Package Number M24B
Order Number LM8305M

2-228

r-------------------------------------------------------------------------, r

iii:

i

ttJNational Semiconductor

LMC6008
8 Channel Buffer
General Description
The LMC6008 octal buffer is designed for use in an active
matrix liquid-crystal display (AM LCD), specifically to buffer
the gray-level voltages going to the inputs of the column
driver integrated circuits. In an 8-gray-level (S12 color) or
16-gray-level (4096 color) AM LCD, the function of the column drivers is to switch the gray-level voltage inputs to the
AMLCD columns. Thus, the voltage buffers must be able to
drive the column capacitance of the entire display panel.
The LMC6008 AC characteristics, including settling time,
are specified for a capacitive load of 0.1 ",F for this reason.
The LMC6008 contains 4 high-speed buffers and 4 lowpower buffers. The high-speed buffers can provide an output current of at least 2S0 mA (minimum), and the low-power buffers can provide at least 1S0 mA (minimum). The highspeed buffers are intended to be used for the highest graylevel voltages (VO, V1, V2, V3 in an 8-gray AMLCD). By
including the 2 types of buffers, the LMC6008 is able to
provide this function while consuming a supply current of
only 6.S mA (maximum). The buffers are a rail-to-rail deSign,
which typically swing to within 30 mV of either supply.

The LMC6008 also contains a standby function which puts
the buffer into a high-impedance mode. The supply current
in the standby mode is a low SOO ",A max. Also, a thermal
limit circuit is included to protect the device from overload
conditions.

Features
• High Output Current:
High Speed Buffers
Low Power Buffers
• Slew Rate:
High Speed Buffers
Low Power Buffers
• Settling Time, CL = 0.1 ",F
• Wide Input/Output Range
• Supply Voltage Range'
• Supply Current
• Standby Mode Current

2S0 mA min
1S0 mA min

1.7 V/",s
0.8SV/",s

"'S

16
max
O.W to Vee - 0.1V min
SV to 16V
6.S mA max
SOO ",A

Applications
• AMLCD voltage buffering
• Multi-voltage buffering

Connection Diagram

Ordering Information
Package

24-PlnSO
1

vee-~
2
INl

3"

IN2
IN3 ..!o5
IN4

NC IN5
IN6
IN7
INS

24-Pin

24

~GND
23

-D>- ~

~

j.;:'

.....

Rail

M24B

Tape & Reel

OUT2

19

~

NC

~

PGND

lS

7

&;0:-'

•

~
16
-WI-- OUT6

* ..
~

12

M24B

21 OUT3
J'.....
20
14.7"-r- OUT4

.!.g Js-->___--1i-l_7 0UT5

Vee -

LMC60081M

~------------+-----+-------~

Surface Mount LMC6008IMX

1 > - - - - 1 - OUTl

6

STD-BY -

'-../

Temperature Range NSC
Transport
- 40"C to + 85'C Drawing
Media

::OUT7
-IS">-I-- OUTS
13
~ GND
TUH/12321-1

Top View
Note: Buffers 1. 3, 5 and 7 are High Speed and
Buffers 2, 4, 6 and 8 are Low Speed.

2-229

Absolute Maximum Ratings (Note 1)

Operating Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
ESD Tolerance (Note 2)
2000V
Voltage at Input Pin
V+ + 0.4V, V- - 0.4V
Voltage at Output Pin
V+ + 0.4V, V- - 0.4V
Supply Voltage (V+ - V-)
16V

Supply Voltage .'
Temperature Range

Lead Temperature
(soldering, 10 sec.)

4.5V ~ V+ ~ 16V
-20"Cto +100·C

Thermal Resistance (8JA>
M Package, 24-Pin Surface Mount

.< .

50"C/W

260·C

Storage Temperature Range
Junction Temperature (Note 4)
Pow~r Dissipatio~',(Note 4)

- 55°C to + 150°C
150·C

',.

Interna!l,y Limited

,

DC Electrical Characteristics
Unless otherwise specified, all limits guarantlled for TJ
Symbol

=

25·C, Vee

=

=

VOS

Input Offset Voltage

Av

Vo

IB

Input Bias Cun:ent

ILP

Peak Load Current

Hi Speed Buffers
Vo = 13Vpp

ILP

Peak Load Current

Lo Speed Buffers
Vo = 13Vpp

Rs

=

O.

Typ
(Note 5)

Conditions

Parameter

=

14.5Vand RL

10k,!}

LMC6008
Limit
(Note 6)

Units

25

mVmax

0.985 .

10Vpp

",

.'

,"

VIV

300

nAmax

-250

mAmax

+250

mAmin

-150

mAmax

+150

mAmin

VERR

Output Voltage Difference
(Note 9)

VIH

Standby Logic
High Voltage

3.30

V min

VIL

ISTANDBY Logic
Low Voltage

1.80

V max

.IIH

Standby High Input Currerit .

1.0

p,A max

IlL

Standby Low Input Current

1.0

p,Amax

10 (STD.By)

Output Leakage Current

VSTD-BY

5

",A max

35

=

=

mVmax

High

=

lee

Supply Current

VIL

6.5

mAinax

ISTD-BY

Standby Current

VSTD-BY

500

",A max

PSRR

Power Supply Rejection Ratio

5V

55

dB min

Vo

Voltage Output Swing

Low, VIN

7.25V

= High
< Vee < 14.5V

0.1
'. 'Vee - 0.1
,.

2-230

Vmin
V max

AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, Vee = 14.5V and RL =

Symbol

Parameter

Conditions

on.

Typ
(Note 5)

LMC6008
Limit

Units

(Note 6)
Buffers 1, 3, 5, 7 (Note 3)

1.70

V//Ls min

Buffers 2, 4, 6, 8 (Note 3)

0.85

V//Ls min

16

/Ls max

Standby Response Time ON

10

/Ls max

tOFF

Standby Response Time OFF

10

/Ls max

PBW

Power Bandwidth

45

KHz min

0.1

/LF max

SR

Slew Rate

ts

Settling Time

tON

(Notes 3, 7)

Va = 10 Vppfor Hi-Speed
Va = 5 Vpp for Lo-Speed
(Note 3)

CL

Load Capacitance

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions. see the Electrical Characteristics.
Note 2: Human body model, 1.5 kn in series with 100 pF.
Note 3: The Load is a series connection of a 0.1 ,.F capacRor and a 1n resistor.
Note 4: The maximum power dissipation is a function of TJ(maxl' 8JA, and TA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(max) - T"j18JA, wherelhe iunction-to-ambient thermal resistance 8JA = 5fJ'C/W. If the maximum allowable power dissipation is exceeded, the thermal
limR circuR will limit the die temperature to approximately 16O"C. All numbers apply for packages soldered directly into a PC board.
Note 5: Typical Values represent the most likaly parametric norm.
Nota 6: All limits are guaranteed by testing or statistical analysis.
Note 7: The settling time is measured from the input transRion to a point 50 mV of the final value, for both rising and falling transitions. The input swing is 0.5V to
13.5V for buffers 1, 3. 5, 7 and 3.75V to 10.25V for buffers 2, 4, 6, 8. Input rise time should be less than 1 ,.s.
Note 8: High·Speed Buffers are 1, 3, 5, 7 and Low-Speed Buffers are 2, 4, 6, 8.
Note 9: Output Voltage Difference is the difference between the highest and lowest buffer output voltags when all buffer inputs are at identical voltages.

•
2-231

~

Ln

r----------------------------------------------------------------------------,

~. ~National

PRELIMINARY

Semiconductor

C\I

Ln
.....

~ LM6152 Dual and LM6154 Quad
High Speed/Low Power
45 MHz Rail-to-Raill/O Operational Amplifiers
General Description

Features (For 5V Supply)

Using patent pending circuit topologies, the LM6152/54
provides new levels of speed vs power performance in applications where low voltage supplies or power limitations
made compromise necessary. With only 1.5 mA/amp supply current, the 45 MHz bandwidth of this device supports
new portable applications where higher power devices unacceptably drain battery life.
In addition, the LM6152/54 can be driven by voltages that
exceed both power supply rails, thus eliminating concerns
over exceeding the common-mode voltage range. The railto-rail output swing capability provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages. The
LM6152/54 can also drive capacitive loads without oscillating.

•
•
•
•
•
•
•

Operating on supplies of 1.8V to over 24V, the LM6152/54
is excellent for a very wide range of applications, from battery operated systems with large bandwidth requirements to
high speed instrumentation.

Rail-to-rail input CMVR
Rail-to-rail output swing
Wide gain-bandwidth:
Slew rate
Low supply current
Wide supply range
Fast settling time:
-Gain

• PSRR

-0.25V to 5.25V (maxImin)
( 0.01V to 4.99V (maxImin)
45 MHz (typ) @ 50 kHz
30 VI /Ls (typ)
1.51 Amp (typ)
1.8V to 24V
108 dB (typ) with RL = 10k
87 dB (typ)

Applications
•
•
•
•

Portable high speed instrumentation
5V signal conditioning amplifiersl ADC buffers
Bar code scanners
Wireless communications

Connection Diagrams
S-Pln DIP/SO

14-Pln DIP/SO
OUT A

OUTA~I-_

v+

tiN A

OUT B

-IN A

-IN B

v+

L.....-+;"'+IN B

+IN B

-IN A
+IN A

v

4

TL/H/12350-1

-IN B

-IN C

OUT B

OUT C

Top View

TL/H/12350-2

Top View

Ordering Information
Temperature Range
Package

Industrial
- 40"C to + S5"C

NSC
Drawing

8-Pin Molded DIP

lM6142AIN, LM6142BIN

N08E

8-Pin Small Outline

LM6142AIM, LM6142BIM

MOSA

14-Pin Molded DIP

LM6144AIN, LM6144BIN

N14A

14-Pin Small Outline

lM6144AIM, LM6144BIM

M14A

2-232

....

i:

....
....
i:

G)

tt/National Semiconductor

....
......

LM6161/LM6261/LM6361
High Speed Operational Amplifier

....
......
....
i:

G)

G)

N

G)

General Description

Features

The LM6161 family of high-speed amplifiers exhibits an excellent speed-power product in delivering 300 V I,..s and
50 MHz unity gain stability with only 5 mA of supply current.
Further power savings and application convenience are
possible by taking advantage of the wide dynamic range in
operating supply voltage which extends all the way down to
+5V.

•
•
•
•
•
•
•
•
•

These amplifiers are built with National's VIPTM (Vertically
Integrated PNP) process which provides fast PNP transistors that are true complements to the already fast NPN devices. This advanced junction-isolated process delivers high
speed performance without the need for complex and expensive dielectric isolation.

G)
Co)
G)

High slew rate
High unity gain Ireq
Low supply current
Fast settling
Low differential gain
Low differential phase
Wide supply range
Stable with unlimited capacitive load
Well behaved; easy to apply

300 V/,..s
50 MHz
5mA
120 ns to 0.1 %

....

<0.1%
0.10
4.75V to 32V

Applications
• Video amplifier
• High-frequency filter
• Wide-bandwidth signal conditioning
• Radar
• Sonar

Connection Diagrams
20-LeadLCC
.-----VosADJUST

YosADJUST----,

10-Lead Flatpak

?

Nee::::;: •

Vos

ADJUST~

INVINPu:~3

43

LM8181W

NON-INVINPI1T

v-~--."-

2

:1: 2019'8

Me

? V o s ADJUST

==
__

INY.INPUT_

17

I

?v+
?VOUTPUT
NC

5

NOM-IHY. INPUT _

_ _ _....

LU81'1E

16

910111213

.

.
7

;---V+

15

:----- VOUT

TL/H/9057-13

See NS Package Number W10A

v-----'
TL/H/9057-14

See NS Package Number E20A

q
Vas
Adjust

2.!· 31

INY
Input

NI
Input
TUH/9057-5

Temperature Range
MIlitary
-55"C';; TA';; +125'C

Commercial
O"C,;;TA';; +70"C

Package

LM6261N

LM6361N

8-Pin
Molded DIP

NOSE

LM6361J

8·Pin
Ceramic DIP

J08A

LM6361M

S·Pin Molded
SurfaceMt.

MOSA

20·Lead
LCC

E20A

10-Pin
Ceramic Flatpak

Wl0A

LM6161J/863
5962·8962101PA
LM6261M
LM6161 E/SS3
5962-89621012A
L~6161W/8S3

5962-8962101 HA

NSC

Industrtal
-25"C';; TA ,;; +85'C

2-233

See NS Package Number J08A,
N08EorM08A

Drawing

•

....

CD
CO)

CD

..........
::&

..-

~

~
......
..-

....
CD
::&
....
CD

Absolute Maximum Ratings

(Note 12)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
SupplyVoltage(V+ -V-)
36V
Differential Input Voltage (Note 8)
±8V
Common-Mode Voltage Range
(V+ - 0.7V) to (V- - 7V)
(Note 10)
Output Short Circuit to GND (Note 1)
Continuous
Soldering Information
Dual-In-Line Package (N, J)
Soldering (10 sec.)
260'C
Small Outline Package (M)
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C

See AN-450 "Surface Mounting Methods imd Their Effect
on Product Reliability" for other methods of soldering ,surface mount devices.
Storage Tt!'mp Range
-65'C to + 150'C
~
Max Junction Temperature
150'C
±700V
ESDTolerance (Notes 6 aOO 7) ,
'

,:

1

"

Operating Ratings (Note 12)
Temperature Range (Note :2)
LM6161
LM62a1
LM6361
Supply Voltage Range

TJ ~ + 125'C
TJ ~ +85'C
O'C ~ TJ ~ +70'C
4.75Vt032V

-55'C

~

-25'C~

DC Electrical Characteristics
The following speCifications apply forSupply Voltage = ± 15V, VCM = 0, RL :2: 100 kO and Rs = 500 unless otherwise noted.
Boldface limits apply for TJ = TMIN to TMAX; all other limits TJ =' 25'C.

Symbol

Parameter

Vas

Input Offset Voltage

Vas
Drift

Input Offset Voltage
Average Drift

Ib

Input Bias Current

los

Input Offset Current

los
Drift

Input Offset Current
Average Drift

Conditions

TyP

5

LM616,1

LM6261

LM6361

Limit
(Notes 3, 11)

Limit
(Note 3)

Limit
(Note 3)

Units

7
10

7
9

20
22

mV
Max

10
2

3
8

3
5

5
8

Max

150

350
800

350
800

1500
1900

,nA
Max
nArC

325

kO

RIN

Input Resistance

Differential

Il')put Capacitance

Ay=+1@10MHz,

AYOL

Large Signal
Voltage Gain

Your = ±10V,
RL = 2 kO (Note 9)

750

RL = 10 kO (Note 9)

2900

VCM

Input Common-Mode
Voltage Range

Supply = ± 15V

CMRR

Common-Mode
Rejection Ratio

-10V~VCM'~

PSRR

Power Supply
Rejection Ratio

±10V

Va

Output Voltage
Swing

Supply = ± 15V
and RL = 2kO

~

V±

~

+10V
±16V

p.A

0.4

CIN

Supply = +5V
(Note 4)

p.V/'C

' 1.5

pF
550
300

550
400

400
350

VIV
Min

+14.0

+13.9
+13.8

+13.9
+13.8

+13.8
+13.7

Volts
Min

-13.2

-12.9
-12.7

-12.9
-12.7

-12.8
-12.7

Volts
Min

4.0

3.9
3.8

3.9
3.8

3.8
3.7

Volts
Min

1.8

2.0
2.2

2.0
2.2

2.1
2.2

Volts
Max

94

80
74

80
78

72
70

dB
Min

90

80
74

80
78

7,2
70

dB
Min

+14.2

+13.5
+13.3

+13.5
+13.3

+13.4
+13.3

Volts
Min

-13.0
-12.7

-13.0
-12.8

-12.9
-12.8

Volts
Min

-13.4

VIV

DC Electrical Characteristics

(Continued)
The following specifications apply for Supply Voltage = ± 15V, VCM = 0, RL ;;, 100 ko. and Rs = 500. unless otherwise noted.
Boldface limits apply for T J = T MIN to T MAX; all other limits T J = 25'C.

Symbol

Parameter

Conditions

Vo (Continued)

Output Voltage
Swing (Continued)

Supply = +5V
and RL "" 2 ko.
(Note 4)

Typ

4.2
1.3

Output Short
Circuit Current

Source
Sink

Is

Supply Current

65
65
5.0

LM6161

LM6261

LM6361

Umit
(Notes 3, 11)

Limit
(Note 3)

Limit
(Note 3)

Units

Volts
Min

3.5

3.5

3.4

3.3

3.3

3.3

1.7

1.7

1.S

2.0

1.9

1.9

30

30

30

20

25

25

30

30

30

20

25

25

6.5

6.5

6.S

8.8

8.7

8.9

Volts
Max
mA
Min
mA
Min
mA
Max

AC Electrical Characteristics
The following specifications apply for Supply Voltage = ±15V, VCM = 0, RL ;;, 100 ko. and Rs = 500. unless otherwise noted.
Boldface limits apply for T J = T MIN to T MAX; all other limits T J = 25'C.

Symbol
GBW

Parameter

Conditions

Gain-Bandwidth
Product

@f= 20 MHz

Slew Rate

Av = +1 (NoteS)

Typ

50

Supply = ±5V
SR

LM6161

LM6261

LM6361

Limit
(Notes 3, 11)

Limit
(Note 3)

Limit
(Note 3)

Units

40

40

35

30

35

32

MHz
Min

200

200

200

V/p.s

180

180

180

35
300

MHz
Min

Supply = ± 5V (Note S)

200

Vlp.s

PBW

Power Bandwidth

VOUT = 20Vpp

4.5

MHz

is

Settling Time

10V Step to 0.1%
Av = -1, RL == 2 ko.

120

ns

45

Deg

m

Phase Margin

AD

Differential Gain

NTSC,Av = +4

<0;1

%

D

Differential Phase

NTSC,Av = +4

0.1

Deg

enp..p

Input Noise Voltage

f = 10 kHz

15

nV/~

ini1"P

Input Noise Current

f = 10kHz

1.5

pA/~

Note 1: Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 1500C.
Note 2: The typical junction-to·ambient thermal resistance of the molded plastic OIP (N) is 105'C/W. the molded 'plastic SO (M) package is ISS"C/W. and the
cerdip (J) package is 12S'C/W. All numbers apply for packages soldered directly into a printed circuit board.
Note 3: Limits are guaranteed by testing or correlation.
Note 4: For single supply operation, the following conditions apply: V+ = SV, V- = OV, VCM = 2.SV, VOUT = 2.SV. Pin 1 & Pin 8 (Vos Adjust) are each
connected to Pin 4 (V-) to realize maximum oUlput swing. This connection will degrade Vos, Vos Drift, and Input Voltage NOise.
Note 5: CL ,;; S pF.
Note 6: In order to achieve optimum AC performance, the input stage was designed without protective clamps. Exceeding the maximum differential input voltage
results in reverse breakdown of the bese..,mitter junction of one of the input transistors and probable degradation of the input parameters (especially Vos, los, and
Noiee).
Note 7: The average voltage that the weakest pin combinations (thoee involving Pin 2 or Pin 3) can withstand and still conform to the datasheet limits. The test
circuR used consists of the human body model of 100 pF in series with IS000.
Nota 8: VIN = 8V step. For supply = ±SV, VIN = SV step.
Note 9: Voltage Gain is the total output swing (20V) divided by the input ~ignal required to produce that swing.
Note 10: The voltage between V+ and eRher input pin must not exceed 36V.
Note 11: A military RETS electrical test specification is available on request. At the time of printing, the RETS6161 X specs ~mplied with all 801 _ _ IimRs in this
column.
Note 12: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test condRions, see the Electrical Characteristics.
The guaranteed spacifications appiy only for the test conditions listed.

2-235

.~
CD

.-------------------------------------------------------------------------------------~

Typical Performance Characteristics (RL = 10kO. TA = 25°C unless otherwise specified)

:!I.....

Supply Current vs
Su~ply Voltage ,

.~

CD

Common-Mode
Rejection Ratio

!:120

+~OC

::::E

.....
.....

I!

...I

1,-55°C

c;;
.-

8

ro

8

~

U"U

'\.

o

m

10

100

+/- SUPPlY VOLTAGE (V)

I

~

".

i*:
2

1M

1

10M

:!
i!

Io!!:

I'll

50

i""" ..... ..... ~25"I:

I"

-

-40

ro

8

U

~

~

t; 100

~

I

Vs=!15V
Vo" !IOY

o

/,

g

20

i

,

Nogat~

0

........

o
10pF l00pF

,

Vs =!I5V
Av = +1

1 nF

:1/

"

0
10pF

10nF l00nF 11'1"

l00pF

LOAD CAPACITANCE

-55"C

Rrj21<4

IIV

"~

1 nF

10nr.

~600

I-

~600

~

~

~

248

l00nF

I I

fI'

"

~

-""'""L

+125"1:

[ - ~ +25"1:

V"

I

'/

-55"1:

~200
Vs=! 15Y
1

10

8

ro u

U

~

m

+/- SUPPLY VOLTAGE (V)

ia

r0.1

+125"C

Gain vs Supply Voltage

111111
r- lIJll
25"C. 125'1:
........
r-55OC

o

+~OC

1'1
o

1000

80 r-

I-

~

-

k::: :;..-

~ F"" i.-'"

1\ .\

Voltage Gain
vs Load Resistance

20

10nF l00nF 11'1"

Vsw~,
!v=+1

CAPAC1I1VE LOAD

80

~
1 nF

", ./

'1-=1 1 pF

.......

Slew Rate

I\cr= Olpf

1 ,/ \

1M

LOAD CAPACITANCE

Overshoot vs
capacitive Load

~

\\

1

lIMP£RATURE (OC)

Slew Rate vs
Load Capacitance

,

r-... ~

0

0.1
10pF l00pF

-55 -35-15 5 25 45 65 85 105125

+/- SUPPlY VOLTAGE (V)

~\

10k lOOk

Vs =:t15V

I

=====

50

~

lk

Gain-Bandwidth Product
vs Load capacltlilnce

.......

!PO

10

8

100

"

FREQUENCY (Hz)

20

4

10

1000

t,.

60

10

o

I,Ok lOOk

70

..... ~- ~

40

lk

o

Propagation Delay
Rise and Fall Times

.J..+-

1.1.
50 --,-55OC

~

fREQUENCY (Hz)

Gain-Bandwidth
Product
80

,

p-

NogaUVO
....... ~

-

80 I--

i\.

I:

:::IE
.....

4

!

100

I:

CD

2

100

iii

+125"1:

o

Power Supply
Rejection Ratio

, 0

248

100

8

I
I
I
ro

-lit. " 21<4
~ m

U U

+/- SUl'l'LY VOLTAGE (V)

LOAD RESISTANCE (1<4)

TL/H/9057 -6

2·236

r-

E
....

Typical Performance Characteristics

en
....
......

(RL = 10 kn, TA = 25'C unless otherwise specified) (Continued)

Differential Gain (Note)

Ii:

Differential Phase (Note)

en
~
....
......

Ii:

en
~
....
TL/H/9057 -8

Not.: Differential gain and diflerential phase measured for four series
LM6361 op amps configured as unity-gain followers, in series with an
LM6321 buffer. Error added by LM6321 is negligible. Test performed using
Tektronix Type 520 NTSC test system.

TLlH/9057 -7

Step Response; Av =

+1

TL/H/9057-1

(50ns/div)

Input Noise Voltage

Input Noise Current

~

~

!

~ 1000

..s.
~
!i.!

!:j

~z

i

"-

100

0

10
1

Power Bandwidth
32

1000

10,000

10

100

lk

FREQUENCY (Hz)

--

10k

lOOk

iii
0

100

24

'-

= t15V

Vs

~
lIfD

2B

r\.

="

< ",

20

16
12

10

z

1
1

10

100

lk

FREQUENCY (Hz)

-

10k

lOOk

1'\
D
0.1

10

100

FREQUENCY (MHz)
TLlH/9057 -9

2-237

.-

ia::&

........

~------------------------------------------------------------------------------------~

Typical Performance Characteristics
(RL = 10 kO, T A = 25°C unless otherwise specified) (Continued)

.~

::&
....
."CD
....
CD

~

Open-Loop
Frequency Response

Open.Loop
Frequency Response

CD

s

~

~

~

~
~

20

~
I

"

.. 1

'-

60
40

Output Impedence

lOok (Open.Loop)

60

80

~.

GAIN

'-.1

18C)'

).

1
1

0

lk

10k lOOk

1M

270

",

-20

!2
,:!j

"- PHASE·I"- ~
10M 100M

360

1
I

!.

50

;!!;

40

~

180 .

1'0..

~

30

I';

10

~

-10

~

20

270

9

360

l

-20

~o

lG

1M

10M

FREOUENCY (Hz)

~.,

lG

100M

~

§

I

I

1I
'i:'

......

10k

lk

--

100

o

lk

10k

FREOUENCY (Hz)

Common-Mode Input
Saturation Voltage

lOOk

111

'10M

100M

FREaUENCY (Hz)

Bias Current vs
Common-Mode Voltage

Output Saturation Voltage
V+

8

~, -11-+~t::I:~:!=:l-~

~r-t-+-+-+-+-+-+-1

lr-r-+-+-+-+-+-+-1
~L-~~~~~~~~

2

•

6

+/-

8

W n

~

~

SUPPLY YOLTAG£ (V)

~

~

~r-t-t-+-+-+-+-+-1

,~

~I--I--HHHHC""'-4

~
j'~
.5

:~

I

-55"(; _

,.

1'1-'-+-+-+-+-+-+-+rl

1

~ L-L-~.l.-.J...,.~+--'-.J

o

246

+/-

8 W

n

~

SUPPLY VOLTAG£ (V)

~

~

--

-15 -10

I-- ~

.J5"C
.125"C

-5

0

-

10

15

COMMON-MODE VOLTAGE (V)
TLlH/9057 -12

Simplified Schematic

TL/H/9057-3

2-238

,-----------------------------------------------------------------------------, r
iii:
G)

Applications Tips

The LM6361 has been compensated for unity-gain operation. Since this compensation involved adding emitter-degeneration resistors to the op amp's input stage, the openloop gain was reduced as the stability increased. Gain error
due to reduced AVOL is most apparent at high gains; thus,
for gains between 5 and 25, the less-compensated LM6364
should be used, and the uncompensated LM6365 is appropriate for gains of 25 or more. The LM6361, LM6364, and
LM6365 have the same high slew rate, regardless of their
compensation.
The LM6361 is unusually tolerant of capacitive loads. Most
op amps tend to oscillate when their load capacitance is
greater than about 200 pF (especially in low-gain circuits).
The LM6361's compensation is effectively increased with
load capacitance, reducing its bandwidth and increasing its '
stability.
'

however, improve the stability and transient response and is
recommended for every deSign. 0.01 !l-F to 0.1 !l-F ceramic
capaCitors should be used (from each supply "rail" to
ground); if the device is far away from its power supply
source, an additional 2.2 !l-F to 1O!l-F of tantalum may provide extra noise reduction.
Keep 'all' leads short to reduce stray capaCitance and lead
inductance, and make sure ground paths are low-impedance, especially where heavier currents will be flowing.,
Stray capaCitance in the circuit layout can cause signal coupling across adjacent nodes and can cause gain to unintentionally vary with frequency.
Breadboarded circuits will work best if they are built using
generic PC boards with a good ground plane. If the op amps
are used with sockets, as opposed to being soldered into
the circuit, the additional input capacitance may degrade
circuit performance.

Power supply bypassing is not as critical for the LM6361 as,
it is for other op amps in its speed class. Bypassing will,

....
....
.....
G)

r

iii:

~

....
.....
G)

I~
....

Typical Applications
Offset Voltage Adjustment

1 MHz Low-Pass Filter

V+

~
_76

150pF"
Cl

>-t--VOUT

3+

~

10k.n

V-

lOOK
TLlH/90S7 -4

TL/H/90S7-10

t1 % tolerance
·Matching determines filter precision

fo

= (211" J(RI

R2 Cl C2\)-1

Modulator with Dlfferentlal-to-Slngle-Ended Converter
+12V
MODULATION
BALANCE
2k

10k

50k

51

10k

lk

+12V
3.9k

51
3.9k

7
CARRIER - - - - l H I - - -......--.;.----1 8
MODULAnON _ _
...._ _ _ _ _ _-I
1
INPUT
4
.....;;~.:;;;..

~

3.9k

6
LM10496

10

OUTPUT
9
-12

5
9.1k

-12V
TLlH/90S7-11

2-239

•

tfI National

Semiconductor

"

,

LM6162/LM6262/LM6362
High Speed Operational.Amplifier
G,eneral Description
The LM6362 family of high-speed amplifiers exhibits an excellent speed-power product, delivering 300 V/ p.s and
100 ,MHz gain-bandwidth product (stable for gains a,s lo,w as, .
+ 2 ~r -1) with only 5 mA of, supply current. Further power
savings and application convenience are possible by taking
advantage of the .wide dynamic range in operating supply
voltage which extends all tlie way down io + 5V.
These amplifiers are built with National's VIPTM (Vertically
Integrated PNP) process which provides fast transistors that
are true complements to the already fast NPN devices. This
advanced junction-isolated process delivers high speed performance without the need for complex and expensive dielectric isolation.

•
•
•
•
•
•
•

5mA
120 nslo 0.1%
<0.1%
<0.1'
4.75V to 32V

Low supply current
Fast settling time
Low differential gain
,
Low differential phase
Wide supply range
Stable with unlimited capacitive load
Well behaved; easy to apply

Applications
• Video amplifier
• Wide-bandwidth signal conditioning for image processing (FAX, scanners, laser printers) , '.
..
• Hard disk drive preamplifier
• Error amplifier for high-speed switching regulator
'

Features
• High slew rate
• High gain-bandwidth product

300 V/p.s
100 MHz

Connection Diagrams
2G-Lead LCC ,

V,,""""

,,

INV.1NPUT--i

IiOtHNV. INPut---i

··
,

·
,

V·

_L

.I.
:l

:1: 10

II

12

13

"
"
"

Nee:=:!; •

vos~u:~
INY INPUT

II

LMI182E

10

1G-Pln Ceramic Flatpak
VOSADJUST

17

;--V'

IS

;--VOUT

Vos

~NC
LM8182W

NON-IHV INPUT

~~"A~un
V'
VOUTPUT
NC

V-~

TLlH/ll061-15

Top View

See NS Package Number W10A

T

~J~

,1 .I :f
Vour

P~

:,1 ',!. 'J, 'J"'Vos,.... .....
."..

TL/H/ll061-2

See NS Package Number NOSE,
MOSAorJOSA

TLlH/ll061-14

Top View
See NS Package Number E20A
Temperature Range
Military
-55'C";; TA";; +125"C

Industrial
-25'C ,,;; TA";; +S5'C

Commercial
O"C ,,;; TA ,,;; +70"C

LM6162N

LM6262N

LM6362N

LM6162J/883
5962-9216501PA
LM6262M

LM6362M

Package

NSC
Drawing

8-Pin MoidedDIP

N08E

8-Pin Ceramic DIP

J08A

, 8-Pin Molded Surface Mt.

M08A

LM6162E/883
5962-92165012A

20-LeadLCC

E20A

LM6162W/883
5962-9216501 HA

10-Pin Ceramic Flatpak

W10A

2-240

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+ -V-)
36V
±'8V
Differential Input Voltage (Note 2)
(V+ -0.7V) to
Common-Mode Input Voltage
(V- - 0.3V)
(Note 3)
Output Short Circuit to GND (Note 4)
Soldering Information'
Dual-In-Line Package (N)
Soldering (10 seconds)
Small Outline Package (M)
Vapor Phase (60 seconds)
Infrared (15 seconds)

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
Storage Temperature Range
-65·C:5: TJ:5: +150·C
Max Junction Temperature
1500C
ESD Tolerance (Note 5)
±1100V

Operating Ratings

Continuous

Temperature Range (Note 6)
LM6162
LM6262
LM6362
Supply Voltage Range

260·C
215"C
2200C

-55·C:5: TJ:5: +125·C
-25·C:5: TJ :5: +85·C
O·C:5: TJ :5: +700C
4.75Vt032V

DC Electrical Characteristics
These limits apply for supply voltage = ±15V, VCM = OV, and RL ~ 100 kO, unless otherwise specified. Limits in standard
typeface are for TA = TJ = 25·C; limits in boldface type apply over the Operating Temperature Range.
Symbol,

Parameter

Typical
(Note 7)

Conditions

Vos

Input Offset Voltage

±3

I!.Vos
I!.Temp

Input Offset Voltage
Average Drift

7

Ibias

Input Bias Current

2.2

LM6162
Limit
(Note 8)

LM6262
Limit
(Note 8)

LM6362
Limit
(Note 8)

Units

±5
±8

±5
±8

±13
±1S

mV
max
/LvrC

.3
6

4
6

max

±350
±600

±1500
±1900

nA
max

/LA

los

Input Offset Current

±150

I!.los
I!.Temp

Input Offset Current
Average Drift

0.3

nArC

RIN

Input Resistance

180

kO

CIN

Input Capacitance

AVOL

Large Signal
Voltage Gain

Your = ±10V, RL
(Note 9)

VCM

Input Common-Mode
Voltage Range

Supply

Differential

±350
±800

3
5

2.0

RL

= 2 kO

= 10kO
= ± 15V

1400

pF
1000
500

1000
700

800
650

+14.0

+13.9
+13.8

+13.9
+13.8

+13.8
+13.7

V
min

-13.2 '

-12.9
-12.7

-12.9
-12.7

-12.9
-12.8

V
max

4.0

3.9
3.8

3.9
3.8

3.8
3.7

V
min

1.6

1.8
2.0

1.8
2.0

1.9
2.0

V
max

6500

Supply = +5V
(Note 10)

VIV
min
VIV

CMRR

'Common-Mode
Rejection Ratio

-10V:S: VCM:S: +10V

100

83
79

83
79

76
74

dB
l1)in

PSRR

Power Supply
Rejection Ratio

±10V:S: Vs:S: ±16V

93

83
79

83
79

76
74

dB
min

Vo

Output Voltage
Swing

Supply

+13.5
+13.3

+13.5
+13.3

+13.4
13.3

V
min

-13.0
-12.7

-13.0
-12.8

-12.9
-12.8

V
mal(

= ±15V. RL = 2 kO

+14.2
-13.4

2-241

fII

DC Electrical Characteristics

c.
(Continued)
'.'
"
These limits apply.for supply voltage = ± 15V, VCM = o.V, and RL .~.1o.O k~, unless otherwise,sP!lCified, UrT)its in star,ldard
typeface are for TA =. TJ. "" 25"C;,limits ill "oldface type apply m

LM6362
Linilt
(Note 8)

.'-

80.

90.'

55

65

65

20.0.

20.0.

20.0.

180

180

180

Units

75

MHz
min
MHz
Vlp.s
min

V/p.s

20.0.

VaUT= 2o.Vpp

4.5

lo.V step, toO.l%
Av = -l,RL = 2kO

10.0.

Phase Margin

Av= +2

45

DiffElrent(al Gain '

NTSC,Av = +2

<0..1

.'

LM6262
Limit
(Note 8)

70.
30.0.

Supply = ±5V

LM6162
Limit
(Note 8)

,

MHz
ns;

..

deg

,

%

Differential Phase

NTSC,Av; =. +2

<0..1

deg

en'

Input Noise Voltage

,f = 10. kHz .

10.

nV/y'H~

in

Input NOi.se Current

·f = 10. kHz

1.2

pAly'Hz

.,

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the
devioe beyond its rated operating conditions.
Note 2: The ESD proteCtion circuitry between the Inputs will bagln to conduct when the dlfferantial input voltage reaches av.
Note 3: a) In addH\on, the·voHage between the V+ pin and eHher Input pin must not excaed 36V.
b) When the voHage applied to an input pin is driven more than 0.3V below the negative supply pin voltage. a substrate diode begins to conduct Current
through this pin must then be kept less than 20 inA to limit damage from self-heating.
Note 4: Although the output current is internally limned, continuous short-clrcuH operation at elevated ambient temperature can result in exceeding the maximum
alloWed iunction iemperature ofl·sOIc.
.
Note 5: This value is the average voltage that the _kest pin combinations can withstand and still contorm to the datasheet limi~ The test circuit used consists of .
the human body model, 100 pF in series with lSOOIl.
Note 6: The typical thermal resistance, luOOtion-to:ambient, of the molded plastic DIP (N package) is 10S'C/W. For the molded plastic SO (M pa,ckege), use.
155'C/W. All numbers apply for packages soldered directly Into a printed circuit board.
Note 7: lypical values are for TJ - 25'C, and represent the most likely parametric norm.
Note 8: Umits are guaranteed; by testing Or correlation;
.
.
Note 9: VoHage Gain is the total output swing (2OV) dMdem

Phase Margin

Ay = +5

AD

Differential Gain

NTSC,Ay = +10

<0.1

%

<1>0

Differential Phase

NTSC, Ay = + 10

<0.1

Deg

e np•p

Input Noise Voltage

F=10kHz

8

nV/,fHz

inp_p

Input Noise Current

F = 10 kHz

1.5

pAl,fHz

Note 1: Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150"C.
Note 2: The typical junction-to-ambient thermal resistance of the molded plastic DIP (N) is 105'C/Watt, the molded plastic SO (M) package is 155°C/Watt, and the
cerdip (J) package is 125°C/Walt. All numbers apply for packages soldered directly into a printed circutt board.
Note 3: Limits are guaranteed by testing or correlation.
Note 4: For single supply operation, the following conditions apply: V + ~ 5V, V - ~ OV, VCM
connected to Pin 4 (V-) to realize maximum output swing. This connection wHi degrade Vos.

~

2.5V, VOUT

~

2.5V. Pin 1 & Pin 8 (Vas Adjust) are each

Note 5: Cl ,;; 5 pF.
Note 6: In order to achieve optimum AC performance, the input stage was designed without protective clamps. Exceeding the maximum differential input voltage
results in reverse breakdown of the base-emitter junction of one of the input transistors and probable degradation of the input parameters (especially Vos, los, and
Noise).
Note 7: The average voltage that the weakest pin combinations (those involving Pin 2 or Pin 3) can wtthstand and still conform to the datasheet limtts. The test
circuit used consists of the human body model of 100 pF in series with 15000.
Note 8: VIN ~ 4V step. For supply ~ ± 5V, VIN ~ tv step.
Note 9: Voltage Gain is the total output swing (20V) divided by the input signal required to produce that swing.
Note 10: The voltage between V+ and either input pin must not exceed 36V.
Note 11: A military RETS electrical test specification is available on request. At the time of printing, the LM6164J/883 RETS spec complied with the Boldface
limits in this column. The LM6164J/883 may also be procured as Standard Military Drawing #5962-896240IPA.

fI

2-251

~

I::E

r-------------------------------------------------------------------------------------,
Typical Performance Characteristics

....

(RL

= 10 kfi. TA = 2SoC unless otherwise specified)

..;.I

;

Supply Current vs
Supply Voltage

+25~
I'-ssoc

~

....

Common-Mode
Rejection Ratio

-

+125OC

CD

r-

CD

~

o

2

4

8 W

6

~

U

~

~

100

I

811

\

811

I

~

\.
\

o
100

lk

+/- SUPPLY VOLTAGE

10k lOOk

70

"

!

lL

20

6

8

W

~

U

~

10

so

= tl5V

"\.POSmYE

r"'\.'i
]\

1000

~ p=:;

\
\
I'-...

o

10nF l00nF 1,.

1M

1111

Vs = t15V
f = 20 MHz

--

'"
"-

0.I
lOp!" lOOp!"

5 25 45 65 65 105 125

Cylo~
U1

lOp!"

,,

Slew Rate

2~_

~

k::: :;;.-r+25OC

~ ..... i--" -+I25OC

~.

~ 1/

IIV
1//

1\
1 nF

10nF l00nF 1,.

400

Vs = t15V
I-- "v =.,+5
Rr = 2k4

Cy=lpF

lOOp!"

1 nF

LOAD CAPACITANCE

Overshoot vs
Load Capacitance

,~

NmAnvE\

10k lOOk

Gain-Bandwidth Product
vs Load Capacitance

TEMPERATURE (OC)

Slew Ratevs
Load Capacitance

lOp!" lOOp!" 1 nF

lk

Vs = t15V
,Vo = ilOY

+/- SUPPLY VOLTAGE (V)

Vs

100

1

-ss -35 -15

~

,

~

o

1111

\po

o

'0

o

I

NEIlAlM'

10

.... ....

10

4

I

20

40

2

~

40

~ so

r= V

i

~0SI11YE

811

FREQUENCY (Hz)

It!

so

~ i-"" ~ +1~ .....
i-"" io"'"'

110

tr

811

-55;;" ~ .....

1:3

100

Propagation Delay
Rise and Fall Time

Produ~

I

120

~

FR£QUfNCY (Hz)

Gain-Bandwidth

j200

1M

!:

i

20
10

Power Supply
Rejection Ratio

10nF

o

2

l00nF

4

6

8 W

~

U

~

~

+/- SUPPLY VOLTAGE (V)

LOAD CAPACITANCE

Voltage Gain vs
Load Resistance

Gain vs Supply Voltage
4J)

I

~
~3.0

I

~
~

i

20

0~~~-w~~y~S~=~t~15~V
0.1

1

10

/

/

2.0

IV

+25"C

~

-55"C

f//"

I

r

In

o

246

100

.....

~ I-r-

I
I
8

W

~

U

~

~

+/- SUPPLY VOLTAGE (V)

LOAD RESISTANCE (kll)

TLlH/9153-5

2-252

Typical Performance Characteristics
(RL

=

10 kO, T A

=

25°C unless otherwise specified) (Continued)

Differential Gain (Note)

Differential Phase (Note)

TUH/9153-7

Note: Differential gain and differential phase
measured for four series LM6364 op amps in series with an LM6321 buffer. Error added by
LM6321 is negligible. Test performed using Tektronix Type 520 NTSC test system. Configured
with a gain of + 5 (each output attenuated by
80%)

TL/H/9153-6

Step Response;Av = +5

TLlH/9153-1

TIME (50 ns/div)

Input Noise Voltage

Input Noise Current

Power Bandwidth

1000

1000

32
28

~
~

~~
~

100

"

lliD < 1:1

16
12

z

1

10

II~s JlW

211

.......

10

1
1

~

24

I"\..

100

lk

FREQUENCY (Hz)

l11e

1011e

10

100

lk

FREQUENCY (Hz)

-

10k

1011e

'\
o

0.1

1

10

100

FREQUENCY (MHz)
TUH/9153-9

2·253

~

~

U)

~

r---------------------------------------------------------------------------------,
Typical Performance Characteristics
(RL = 10 kO, T A = 25°C unless otherwise specified) (Continued)

~

~

Open-Loop
. Frequency Response .

::iii

.....

100

~

....
:I
.....

"

111

U)

!

Open-Loop
Frequency Response

"'\

60

'.

lOOk

110

;l!

GAII4

~

'''\

!/!

"-

~

PHASE

I

;!j

~

-20
lk

Output Resistance
Open-Loop

10k lOOk

III

90

~

lOll 100II

I 8G

270
lG

~>
~.

50

40 ~

;·1

30

~

10

I~

GAII4

20

90

..... i::1-

PHASE

II

-10

II

-20
III

rREOUEHCY (Hz)

lOll

I 80

\

10k

I

lk

;!j

i'

~

100

~

!I!

I

\

270

100II

.......

g

0

5

""'"
lk

10k

lOOk.

III

100II

rREOUENCY (Hz)

FREQuENCY (Hz)

yt Output Saturation Voltage

Bias Current vs
Common-Mode Voltage

Common-Mode Input
yt Saturation Voltage

\
lOll

10

lG

5

E
~

~++-M+-I--l

-I

~ ~~~~+-+-+-+-+-~

~
~

i

-

¥
.1

1

1
~~~~~~~~~~

2

1

4

6

8

W U

U

~

+/- SUPPlY VOLTAGE (V)

~

~=2~

~

246 8 W U U
+/~ SUPtoLY VOLTAGE (V)

~

a

-5~ac

-

I

o

.....

-

:mac
1:mac

-5
10
COIOION-IIOOE VOLTAGE (V)

-15 -10

15

TL/H/9153-13

Simplified Schematic

TUH/9153-3

2·254

r-----------------------------------------------------------~~

Applications Tips
The lM6364 has been compensated for gains of 5 or greater (over specified ranges of temperature, power supply voltage, and load). Since this compensation involved adding
emitter-degeneration resistors in the op amp's input stage,
the open-loop gain was reduced as the stability increased.
Gain error due to reduced AVOL is most apparent at high
gains; thus, the uncompensated lM6365 is appropriate for
gains of 25 or more. If unity-gain operation is desired, the
lM6361 should be used. The lM6361, lM6364, and
lM6365 have the same high slew rate (typically 300 VI p.s),
regardless of their compensation.
The lM6364 is unusually tolerant of capacitive loads. Most'
op amps tend to oscillate when their load capacitance is
greater than about 200 pF (in low-gain circuits). However,
load capacitance on the lM6364 effectively increases its
compensation capacitance, thus slowing theop amp's response and reducing its bandwidth. The compensation is
not ideal, though, and ringing or oscillation may occur in
low-gain circuits with large capacitive loads. To overcompensate the lM6364 for operation at gains less than 5, a

series resistor-capacitor network should be added between
the input pins (as shown in the Typical Applications, Noise
Gain Compensation) so that the high-frequency noise gain
rises to at least 5.
Power supply bypassing will improve the stability and tran-.
sient response of the lM6364, and is recommended for ev- ,
ery design. 0.01 p.F to 0.1 p.F ceramic capaCitors should be
used (from each supply "rail" to ground); if the device is far
away from its power supply source, an additional 2.2 p.F to
10 p.F (tantalum) may be required for extra noise reduction .
Keep all leads short to reduce stray capaCitance and lead
inductance, and make sure ground paths are low-impedance, especially where heavier currents will be flowing.
Stray capacitance in the circuit layout can cause signal coupling between adjacent nodes, so that circuit gain unintentionally varies with frequency.

....mm

~

Ii
~
.......
!!I:
m
~

.-

•

Breadboarded circuits will work best if they are built using
generic PC boards with a good ground plane. If the op amps
are used with sockets, as opposed to being soldered into
the circuit, the additional input capacitance may degrade
circuit performance.

Typical Applications
Noise-Gain Compensation for Gains,,:; 5

Offset Voltage Adjustment

y+

Rr

_76

~

v·

3+

'I

V-

>-+-- VOUT

100k

TL/H/915S-10

Video-Bandwidth Amplifier
1 pF
TL/H/915S-11

RXCX :. (2".025 MHz)-l

5 Rx - A1 +, RF(l + R1/R2l

7500

•

TL/H/915S-12

2-255

~

!

:;....

,-----------------------------------------------------------------------------,
tflNational Semiconductor

~

~
::Ii
CD

LM6165/LM6265/LM6365

.... High Speed Operational Amplifier
CD
....CD
,;.J

~

:s

Features

General Descriptic»n

The

LM~165

family. of high-speed amplifiers exhibits an excellen~. speed-power product in delivering 300· VI p.s and
72.5 MHz GBW(stable for gains as low as + 25) with only
5
of supply cllrrent. Further power savings and application CQnvenience are possible ·by taking advantage of the
wide dynamic range in operating supply voltage which ex.
tends all the way down to + 5V.

•
•
•
•
•
•
•
•

rnA

These amplifiers are built with National's VIPTM .(Vertically
Integrated PNP) process which produces fast PNP transistors that are true complements to the already fast NPN devices. This advanced junction-isolated process deliVers high
speed performance without the need for complex and expensive dielectric isolation.

300 V/p.s
725 Ml;lz
5mA
80 ns.to 0.1%
<0,1%
<0.1'
4.75V t032V

High slew rate
High GBW product
Low supply current
Fast settling
Low differential gain
Low differential phase
Wide supply range
Stable. with unlimited capacitive load

Applications
• Video amplifier
• Wide-bandwidth signal conditioning
• Radar
• Sonar

Connection Diagrams
10-Lead Flatpak
Top View

Nee::::::; •

F,=JNC
~:vos ADJUST

Vos ADJUSTC:::::::;
lNV

'Npu~5

2D-LeadLCC
Top View

LM811SW

NON-INV INPUT~

v-~

'" '''''''---'-L 1.-----'" """"
3

v+

VOUTPUT

~Nt

TL/H/9152-14

Order Number LM6165W/883
See NS Package Number W10A

2

4
INV.IIlPUT-

Ie
17

.
&

NOM-IIIY.IIlPUT-

'II 20"

~!

5

LII81I1E

1

,

r--V+

15
15

10

11

12

13

r--VOUT

,.

~~ ~Jv

,____....J
TLlH/9152-15

Order Number LM6165E/883
See NS Package Number E20A

Adjust

Input

3JI

4(

v-

Input
TL/H/9152-8

Order Number LM6165J/883
SeeNS Package Number J08A
Order Number LM6365M

Temperature Range

NSC

Industrial
-25"'C ,;; TA ,;; +8S'C

Commercial
O'C';; TA';; +70'C

Package

LM6265N

LM6365N

8-Pln
Molded DIP

N08E

8-Pln
Ceramic DIP

J08A

B·Pin Molded
Surface MI.

MOBA

LM6165E/863
5962-89625012A

2O-Lead
LCC

E20A

LM6165W883
5962·8962501 HA

100Pin

Wl0A

C&ramic Flatpak

Military
-S5"'C,;;TA';; + 125"C

LM6165J/883
5962-6962501 PA
LM6365M

2-256 .

See NS Package Number M08A

Drawing

Order Number LM6265N or
LM6365N
See NS Package Number N08E

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications_
Supply Voltage (V+ - V-)
36V
±8V
Differential Input Voltage (Note 6)
Common-Mode Voltage Range
(V+ - 0.7V) to (V- - 7V)
(Note 10)
Output Short Circuit to GND (Note 1)
Soldering Information
Dual-In-Line Package (N, J)
Soldering (10 sec.)
Small Outline Package (M)
Vapor Phase (60 sec.)
Infrared (15 sec.)

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
Storage Temp Range
-65'Cto + 150'C
Max Junction Temperature (Note 2)
150'C
±700V
ESD Tolerance (Notes 6 and 7)

Operating Ratings

Continuous

Temperature Range (Note 2)
LM6165, LM6165J/883
LM6265
LM6365
Supply Voltage Range

260'C
215'C
220'C

-55'C";; TJ";; +125'C
-25'C ,,;; TJ ,,;; +85'C
O'C,,;; TJ ,,;; +70'C
4.75Vto 32V

DC Electrical Characteristics
The following specifications apply for Supply Voltage = ± 15V, VCM = 0, RL :;, 100 kn and Rs "" 500. unless otherwise noted.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits T A = TJ = 25'C.

Symbol

Parameter

Conditions

Vas

Input Offset Voltage

Vas
Drift

Input Offset Voltage
Average Drift

Ib

Input Bias Current

los

Input Offset Current

los
Drift

Input Offset Current
Average Drift

RIN

Input Resistance

CIN

Input Capacitance

AVOL

Large Signal
Voltage Gain
(Note 9)

VOUT = ±10V,
RL = 2kn

VCM

Input Common-Mode
Voltage Range

Supply = ±15V

Typ

1

LM6165

LM6265

LM6365

Limit
(Notes 3, 11)

Limit
(Note 3)

Limit
(Note 3)

Units

3
4

3
4

6
7

mV
Max

3

Differential

2.5

3
6

3
5

5
6

)J.A
Max

150

350
800

350
600

1500
1900

nA
Max

0.3

nArC

20

kn

6.0

pF
7.5
5.0

7.5
6.0

5.5
5.0

+14.0

+13.9
+13.8

+13.9
+13.8

+13.8
+13.7

V
Min

-13.6

-13.4
-13.2

-13.4
-13.2

-13.3
-13.2

V
Min

4.0

3.9
3.8

3.9
3.8

3.8
3.7

V
Min

1.4

1.6
1.8

1.6
1.8

1.7
1.8

V
Max

102

88
82

88
84

80
78

dB
Min

104

88
82

88
84

80
78

dB
Min

+14.2

+13.5
+13.3

+13.5
+13.3

+13.4
+13.3

V
Min

-13.4

-13.0
-12.7

":'13.0
-12.8

-12.9
-12.8

V
Min

10.5

RL = 10kn

V/mV
Min

38

Supply = +5V
(Note 4)

CMRR

Common-Mode
Rejection Ratio

-10V";; VCM ,,;; +10V

PSRR

Power Supply
Rejection Ratio

±10V,,;; V± ,,;; ±16V

Va

Output Voltage
Swing

Supply = ± 15V,
RL 2kn

=

)J.vrc

2-257

•

.~ , .
.(', .
(Continued)
The following speoifications apply for Supply Voltagli! '7 ±.15V, VCM =< O,lk ~ .1pO kf} and Rs
Bpldface limits apply for TA = T J = TMIN to T Max;' all other limits TA ,; TJ = 25~C.

DC Electrical Characteristics

,

Symbol

Vo
(Continued)

Par.meter

Conditions

Typ

Output Voltage
Swing (Continued)

Supply = +5V
RL = 2 kO (Note.4)

4.2

..

LM6365

Umit
(Notes 3, 11)

Ul)'lit
(Note 3)

Umlt
(Note 3)

Units

V
. Min

65

Sink
Is

5.0

3.5

3.5

3.4

3.3

3.3

3.3

1.7

1.7

1.8

2.0

1.9

1.9

30

30
25

25

20

65

Supply Current

.'-

. LM6265

1.3
Source

500 unless.otherwise noted.

LM6165

,

Output Short
Circuit Current

=

--

V
. Max
mA
Min

30

30

30

30

rnA

20

25

25

M.in

6.5

6.5

6.8

8.8

8.7

8.9

~

,,

mA
Max

AC Electrical Characteristics

The following specifications apply for Supply Voltage = ± 15V, "CM = 0, RL ~·1 00 kO and Rs = 500 unless otherwise noted.
Boldface limits apply for T A = TJ = T MIN lo T MAX; all other limits TA = TJ = 25°C. (Note 5)

Symbol
GBW

Parameter
Gain Bandwidth

Conditions

F

=

20 MHz

Typ
725

,

. LM6365

LM6165

LM6265

Limit
(Notes 3, 11)

Limit
(Note 3)

Umlt
. (Note 3)

575

575

500

200

200

350
Product .
SR

Supply = ±5V

Slew Rate

Av

=

+ 25 (Note 8)

= ±5V
= 20Vpp

Supply
Power Bandwidth
Product

VOUT

ts

Settling Time

10V Step to 0.1%
Av = -25, RL = 2 kO

=

MHz
Min

500
300

200

180
PBW

Units

V/jJ-s
Min

200
4.5

MHz

80

ns

45

O8g

m

Phase Margin'

Av

AD

Differential Gain

NTSC, Av

=

+ 25

<0.1

%

D

Differential Phase

NTSC, Av

= + 25

<0.1

Deg

enp..p
inp_p

Input Noise Voltage

F

Input Noise Current

F = 10kHz

=

+25

5

nV/.JHz

1.5

pAl.JHz

10kHz

Note 1: Continuous short-clrcuH operatiOn at elevated ambient temperature can resuR In ex~eding the maximum allowed junclion temperature of 150"C.
Note 2: The typical junction·to-ambientthermal resistance of the molded plastic DIP (N) is 105"C/Wall. and the molded plastiC SO (M) package is 1S5"C/Wall. and
the cerdip (J) package is 1.2S"ClWall. All numbers apply for packages soldered directly into a printed circuit board.
Note 3: All limits guaranteed

bY testing or 9Orrelation.1

4: For single.supply operation. the following cQnditiOns apply: V+ = 5V. V- = OV. VCM = 2.5C. VOUT = 2.5V. Pin 1 & Pin 8 (V05 Adjust) are each
con·nected to Pin 4 (V -) to realIZe maxlmwnoutput Swing. This connection will degrade Vos.
N~te

Note 5: ci. :;;; 5 pF.
Nota 6: In order to achieve optimum AC parformance. the input stage wos designed wHhout protective clamps. Exeeding the maximum di.fferential input voltage
resul1s in reverse breakdown of the base...miller junction of one of the input transistors and probable degradation of the input parameters (especially Vos. los. and
Noise).
Note 7: The average voHage that the weakest pin combinations (those invt>lving Pin 2 or Pin 3) can withstand and still conform to the datasheel IimHB. The test
circuH used consists of the human body model of 100 pF in series wHh 15000..
Neite 8: Y,N = O.8V stap. For supply = ± 5V, Y,N = O.2V stap.
Note 9: Voltage Gain is the total ~utput Swing (20V) divided by the input Signal required to produce that Swing.
Nole 10: The voltage between V+ and eHher input pin must not exceed 36V.
Note 11: A miliIs!Y.RETS electricaLtest specification is available on request. At the time of printing, the LM6165J/883 RETS spec complied with the .o~
Iimi1s in this column. T.he LM6165J/883 may also be procured os Standerd.MIlHary Drawing #5962·8962501PA
2-258

r-

...

iii:

Typical Performance Characteristics RL = 10 k!l. TA = 25°C unless otherwise specified
Supply Current vs
Supply Voltage

+25~

Common-Mode
Rejection Ratio

~

i

-

1T-55oc

+12SOC r--'-

2

4

6

8

100

i

10 12 14 16 18

\

80

60

~
§
~

~I

~

.."..

~

700
600

• 25"S,..

I / ' -I

500

10

100

lk

10k lOOk

......

-

....s

50

i!!

30

...

/

100
2

4

6

1
1

1

8

10

",

I
10pF l00pF

I

/'I

400

=tlSV

~55ai:

.Ja

Ay = +25

Rr = 2k4

II

",.
1 nF

o
10nF l00nF

1,.r

10pF

~ ,/"

1'1

o

l00pF

1 nF

10nF

2

l00nF

6 8 W g U
t SUPPLY VOLTAGE (y)

4

LOAD CAPAC1TANCE

Output Impedance
(Open-Loop)

.....

10k

5

14

i!i

12

a

10

III
1!i

z

S

¥

~

Ij
<§
~
i!!

lk

~

.....

100

~

8

",

"

'/',-

§ .-

0

~

I
j.....

i-""

.25OC

..J-SjOC

lOOk

1M

10M

2

100M

r-

I

2

o

10
10k

~

~ r-

,

I

lk

~

Gain vs Supply Voltage
16

lOOk

I

_

iTV

~

I
I

1,.r

k:::: ~.25OC
-::::. :;;-" i..--' -.12SOC

~

(/~= lpF

\

10nF l00nF

Slew Rate

. Vs

cr = OPYI

20

1nF

LOAD CAPACITANCE

"
i : ,,

NEGA~\

= t15V

"-

30

g

1M

"

Overshoot vs '
Capacitive Load

\\

10pF l00pF

Vs

TEMPERATURE (OC)

,,\

10k lOOk

1000

-55 -35,-15 5 25 45 65 65 105 125

'\.POSmvE

lk

Gain-Bandwidth Product vs
Load Capacitance

= t15V
= tIDY

Vs
"VO

o

Slew Ratevs
Load Capacitance

\

100

\po

10

Vs = t15V

~

FREQIlENCY (Hz)

"'1".00-

40

t SUPPLY VOLTAGE (y)

o

10

It

'

12 14 16 18

400

10M

20

~

200

1M

~ ~p::::

'r

60

.125OC_ I-

400

300

NEGATIVE

Propagation Delay,
Rise and Fall Times

-55OC.."..

800

\

o

70

-....-yOUT
TUH/9152-11

y.
TUH/9152-12

RX ex
IR1

+

;"

1/(211" • 25 MHz)

RF (1

+

R1 IR2)1 ~ 25 Rx

;'

,

1 MHz Voltage-to-Frequeney Converter
(fOUT = 1 MHz for VIN = 10V)

';': lOOpF

o-IOY INPUT

-'\,,.,,.,...I\f/!Y---............

....-~:--- Output

~-t~w_

LlA385-2.5
2.2~F

Offset
Adjust

All diodes 1N914

2-262

,

TLlH/9152-13

r-

il:

en
.....

.....
.....

tflNational Semiconductor

LM6171 High Speed Low Power Low Distortion Voltage
Feedback Amplifier
General Description

Features (Typical Unless Otherwise Noted)

The LM6171 is a high speed unity-gain stable voltage feedback amplifier. It offers a high slew rate of 3600V/,...s and a
unity-gain bandwidth of 100 MHz while consuming only 2.S
mA of supply current. The LM6171 has very impressive AC
and DC performance which is a great benefit for high speed
signal processing and video applications.

•
•
•
•
•
•
•
•

The ± 1SV power supplies allow for large signal swings and
give greater dynamic range and signal-to-noise ratio. The
LM6171 has high output current drive, low SFDR and THO,
ideal for ADC/DAC systems. The LM6171 is specified for
± SV operation for portable applications.
The LM6171 is built on National's advanced VIPTM III (Vertically Integrated PNP) complementary bipolar process.

Easy:To-Use Voltage Feedback Topology
Very High Slew Rate
Wide Unity-Gain-Bandwidth Product
-3 dB Frequency @ Av = + 2
Low Supply Current
High CMRR
High Open Loop Gain
Specified for ± 1SV and ± SV Operation

3600V/,...s
100 MHz
62 MHz
2.S mA
110 dB
90 dB

Applications
•
•
•
•
•
•
•
•
•

Multimedia Broadcast Systems
Line Drivers, Switchers
Video Amplifiers
NTSC, PAL® and SECAM Systems
ADC/DAC Buffers
HDTV Amplifiers
Pulse Amplifiers and Peak Detectors
Instrumentation Amplifier
Active Filters

Typical Performance Characteristics
Large Signal
Pulse Response
Av = + 1, Vs = ± 15

Closed Loop Frequency Response
vs Supply Voltage (Av = + 1)
Vs -:t 15 i

/

~
0:

>

:;;

/

e

0

·iii

V

r---

<.:>

">
>-

=>
~
=>

Vs =:t2.75, ......
Vs = :tl0
......
Vs =:t5

-10

-I

I

~

0

-20

l
1M

10M

100M

Frequency (Hz)

Connection Diagram

TIME (20 ns/div)

\.J

~
y-.!

1.
+IN 1
-IN

Ordering Information
Temperature Range
Package

Industrial
- 40"C to + 85'C

~N/C
~y+

~ OUTPUT

~N/C
TL/H/12336-1

TLlH/12336-9

TL/H/12336-S

8-Pin DIP/SO
N/C..!..

If

S-Pin
Molded DIP

LM6171AIN
LM6171 BIN

S-Pin
Small Outline

LM6171 AIM, LM6171BIM
LM6171AIMX, LM6171BIMX

Top View

2-263

Transport
Media

NSC
Drawing

Rails

NOSE

Rails
Tape and Reel

MOSA

•

....
....
....
CD
::::&

....I

Operating Ratings (Note 1)

Absolute Maximum Ratings (Note 1)

. Supply Voltage

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
ESDTolerance (Note 2)
2.5kV
Supply Voltage (V 'I- -V-)
36V
Differential Input Voltage (Note 11)
±10V

2.75V

Junction Temperature Range
LM6171AI, LM6171BI

-40"C

s: V+ s: 18V

s: TJ s:

Thermal Resistance (IIJ,v
N Package, 8-Pin Molded DIP
M Package, 8-Pin Surface Mount

+85°C

108°C/W
172°C/W

Common-Mode
V+ -1.4VtoV-+ 1.4V
Voltage Range
Output Short Circuit to Ground (Note 3)
Continuous
Storage Temperature Range
- 65°C to + 150"C
Maximum Junction Temperature (Note 4)
150"C

±

15V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C,
V+ = + 15V, V- = -15V, VCM = OV, and RL = 1 kO. Boldface limits apply at the temperature extremes
Symbol
Vas

Parameter·

Conditions

Input Offset Voltage

TCVos

Input Offset Voltage Average Drift

Ie

Input Bias Current

lOS

Input Offset Current

RIN

Input Resistance

1.5

1
0.03
Common Mode

40

Differential Mode

4.9

Open Loop
Output Resistance

CMRR

Common Mode
Rejection Ratio

VCM= ±10V

Power Supply
Rejection Ratio

Vs = ±15V-±5V

VCM

Input Common-Mode
Voltage Range

CMRR

Av

Large Signal Voltage
Gain (Note 7)

RL = 1 kO

Output Swing

LM6171BI
Limit
(Note 6)

~

60dB

RL=1kO

110
95

3

6

8

3

3

4

4

p.A
max

2
3

2
3

p.A
max

83
13.3
-13.3

RL = 1000

11.6
-10.5

2·264

mV
max

p'vrc

MO
0
80

75

75

70

85

80

80

75

±13.5
90

Units

5

14

RL = 1000
Va

LM6171AI
Umlt
(Note 6)

6

Ro

PSRR

Typ
(Note 5)

dB
min
dB
min
V

80

80

70

70

70

70

80

80

12.5

12.5

12

12

-12.5

-12.5

-12

-12

9

9

8.5

8.S

-9

-9

-8.5

-8.5

dB
min
dB
min
V
min
V
max
V
min
V
max

r-

5:
....

± 15V DC Electrical Characteristics (Continued) Unless otherwise specified, aU limits guaranteed for

.....
....

TJ = 25°C, V+ = +15V, V- = -15V, VCM = OV, and RL = 1 kO. Boldfacalimits apply at the temperature extremes
Symbol

Parameter

Conditions

Continuous Output Current
(Open Loop) (Note 8)

Sourcing, RL = 1000
Sinking, RL = 1000

Continuous Output Current
(in Linear Region)
Output Short
Circuit Current

ISC

Sourcing, RL = 100
Sinking, RL

=

100.

116
105

LM6171AI
Limit
(Note 6)

LM6171BI
Limit
(Note 6)

90

90

85

85

90

90

85

85

Units
mA
min
mA
max

100

mA

80

mA

Sourcing

135

mA

Sinking

135

mA

Supply Current

IS

Typ
(Note 5)

2.5

4

4

4.5

4.5

mA
max

± 15V AC Electrical Characteristics
V+

=

Symbol
SR

GBW

+ 15V, V- = -15V, VCM

=

OV, and RL

Parameter
Slew Rate (Note 9)

=

Unless otherwise specified, aU limits guaranteed for TJ = 25°C,
1 kO. Boldfacalimits apply at the temperature extremes
Conditions

Typ
(Note 5)

Av = +2, VIN = 13Vpp

3600

Av = +2, VIN = 10 Vpp

3000

Unity Gain-Bandwidth Product
- 3 dB Frequency

100

LM6171AI
Limit
(Note 6)

LM6171BI
Limit
(Note 6)

Units

V/p.s
MHz

Av= +1

160

MHz

Av= +2

62

MHz

m

Phase Margin

40

deg

ts

Settling Time (0.1 %)

Av = -1, VOUT = ±5V
RL = 5000

35

ns

Propagation Delay

VIN = ± 5V, RL = 5000,
Av= -2

6

ns

AD

Differential Gain (Note 10)

D

Differential Phase (Note 10)

en

Input-Referred
Voltage Noise

f = 1 kHz

Input-Referred
Current Noise

f = 1 kHz

in

0.03

%

0.5

deg

12
1

2-265

nV

./Hz
pA

./Hz

....
....'"
co

::IE

...I

± 5V DC Electrical
V+

=

+5V, V-

Symbol
Vos

=

-5V, VCM

Characterist~s Unless otherWise specified, all' limits guaranteed for TJ = 25°C,

= av, and

1 ko.. Boldface limits apply at the temperature extremes
Conditions

Input Offset Voltage
Input Offset Voltage
Average Drift

18

Input Bias Current

RIN

=

Parameter..

TCVos

los

RL

1.2

1
0.03
Common Mode

40

Differential Mode

4.9

Ro

Open Loop
Output Resistance

CMRR

Common Mode
Rejection Ratio

VCM

Power Supply
Rejection Ratio

Vs

VCM

Input Common·Mode
Voltage Range

CMRR

Av

LargeSignal Voltage
Gain (Note 7)

RL

PSRR

Output Swing

RL

=

=

=
=
=

±2.5V

105

±15Vto ±5V
~

60 dB

1 ko.

95

84

1000.

80

1 ko.

3.5

RL = 1000.

3.2
-3.0

Sourcing, RL = 1QOo.
Sinking, RL

Isc

Is

Output Short
Circuit Current

3

6

5

8

=

1DOn

32
30

Sourcing

130

Sinking

100

Supply Current

2.3

2·266

Units
I

mV
max

p'vrc
2.5

2.5

3.5

3.5

1.5

1.5

2.2

2.2

p.A
max
p.A
max
Mo.
0.

80

75

75

70

85

80

80

75

±3.7

-3.4

Continuous Output Current
(Open Loop) (Note 8)

LM6171BI
Limit
(Note 6)

14

RL
Vo

LM6171AI
Limit
(Note 6)

4

Input Offset Current
Input Resistance

Typ
(Note 5)

dB
min
dB.
min
V

75

75

85

85

70

70

80

80

3.2

3.2

3

3

-3.2

-3.2

-3

-3

2.8

2.8

2.5

2.5

-2.8

-2.8

-2.5

-2.5

28

28

25

25

28

2.8

25

25

dB
min
dB
min
V
min
V
max
V
min
V
max
mA
min
mA
. max
mA
mA

3

3

3.5

3.5

mA
max

±5V AC Electrical Characteristics
V+

=

+5V, V-

=

-5V, VCM

=

Unless otherwise specified, all limits guaranteed for T J
OV, and RL = 1 kO. Boldface limits apply at the temperature extremes

Parameter

Symbol

SR

Slew Rate (Note 9)

GBW

Unity Gain-Bandwidth

Conditions

Av = +2, VIN = 3.5 Vpp

Product
-3 dB Frequency

m

Phase Margin

ts

Settling Time (0~1

%)

Differential Gain (Note 10)

<1>0

Differential Phase (Note 1 0)

en

± 1V, RL

= 5000,

57

deg

48

ns

8

ns

0.04

%

0.7

deg
nV

11

f = 1 kHz

Input-Referred

Units

MHz

Voltage Noise
in

(Note 6)

MHz

45

f = 1 kHz

Input-Referred

Limit

(Note 6)

70
130

Av = - 2
AD

LM6171BI

Limit

VIJl-s

Av = +2

VIN =

LM6171.AI

25'C,

750

Av = +1

Av = -1, VOUT = +1V,
RL = 5000

Propagation Delay

Typ
(Note 5)

=

,JHz
pA

1

Current Noise

,JHz

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device,may occur. Operating Ratings indicate condHions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test condHions, see the Electrical Characteristics.
Note 2: Human body model, 1.5 kn in series wHh 100 pF.
Note 3: Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150"C.

Note 4: The maximum power dissipation is a function of TJ(max), 8JA, and TA. The maximum allowable power dissipation at any ambient temperature is Po
(TJ(max) - T/J18JA. All numbers apply for packages soldered direqtly into a PC board.
Note 5.: Typical Values represent the most likely parametriC norm.

=

Note 8: All limRs are guaranteed by testing or statisticsi analysis.
Note 7: Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For Vs
+5V, VOUT = ±IV.
Note 8: The open loop output current is the output swing wHh the loon load resistor divided by that resistor.

=

± 15V, VOUT

=

± 5V. For Vs

=

Nota 9: Slew rate is the average of the rising and falling slew rates.
Note 10: Differential gain and phase are measured with Av
Note 11: Differential input voltage is measured at Vs

=

=

+ 2, VIN

= 1 Vpp at 3.58 MHz and both input and output 75n terminated.

±15V.

•
2-267

.... r-----------------------------------------------------------------------------------------------,
Typical Performance~hai'acteri~tlcs Unless otherwise noted. TA ~ 25"C
~

!Io-

CD

\'

~

"

"

,'tI;.'

Supply Current;/S
SUPPly Voltage

..

3.5

J

J 125"C

..........

I.... .....

2.5

t

a

I.....

J

~

..... r1 r~
.....
~
rr /
A

V- i"

1.5

-:;-

I

25"C
T= -55°C

.5

V

3

1.1

1
..=

r--., r--.,

1.0

u

Temperature

~

/

-100
110

/

y

-150

8c

/

>

~

-, 2

150 ~

1

60

15

~

1

10 100

lk

10k lOOk 1M

Frequency (Hz)

v·

10M

~

.....

.~.1Jc

I

60

!
~

-

-2 -4r C "-

-3

If'

E-

1 8S'oC 25°C
-.0 -30 -20 -10 0 10

90 120

PSRR va Frequency

Vs=.:I:1SV
VIN = lVpp

.~

80
/

Posltive J

60

"

50

~
~

.0
30

Po.lllv~::"

70

"- \..

70

20 30 .0

Output Current (rnA)

90
eN.gatl".

r-

-1

V-

30

\2JOC

1~

-4
0

Vs = '5V

S5 OC-I,

:E:

d50C r- f-

T

25 50 75 100 125

1

I

....-,-.ooC

20

0
1

Vs = :l:5~..../

Output Voltage
va Output Current

-jOOC,_

SO

",

t'-..
l/" ~

"

Temperature (Oe)

Vs =·15V

90

1\

20

,Vs ='15V

r-..."

SO
-55 -40 -25 6

PSRR va Frequency

~

.0

-

r""

"'~5"C\

100

=t5V

Vs = '15V-

........ k'

'30
120

Output Current (rnA)

I V

80

,...

1

10

-1 4
85°C
-1 5
-120 -90 -60 -30

CMRR vs Frequency
100

"

Short Circuit Current
vs Temperature (Sourcing)

1.0

......

85°C

i -, 1

25 50 75 100 125

Vs

I\.

Temperature (Oe)

Output Voltage
va Output Current

Temperature (Oe)

~

105 125

-

-5

-1 3

120

I"

I\.

110

3
2
1
1

~
-1

1.,...-01"""

-160
-55 -40 -25 0

-10

•

./l

Vs='15V~

-1.0

.
E

/

Vs =·5V-

>

0.6

Common "ode Voltage' (V)

C -120

at -130

=:15V f-/

......

90
O.S
-15

1/

;; r--

Vs

100

(Oe)

-

-90

!

a~

0.9

Short Circuit Current
va Temperature (Sinking)
-80

1.0

160

~

~

~

1.2

0.4
-55_ 35 -15 5 25 .5 65 85105125

i""
Temperature

;,

1

0.8

VS =±15V

1.2

0.7
-55 -35 -15 5 25 .5 65 85 105 125

1-

1.4

1.3

....... ~

0.8

I

Vs= :I:.l.5V

......V

...:.:

(Oe)

1.1

~

l""-

1.6

Input Offset Voltage vs
Common Mode Voltage

Vs = <15V

~K..

o.g

1

"~

II

1.8

S'

.5

"

1
-55 -55 -15 5 25 .5 65,

V~= <~v
...... r--.,

.V

r

2.0

I

Vs=rv

1.3
1.2

I-"" f.""

1.5

Input Bias Current
vs Temperature
-:;-

rI

F-n::~ ~

~

I

...... 1-""

~I-'"

a

10
15
20
7.5
12.5
17.5
Supply V.,tage «v)

2.5

2.5

~

Input Offset Voltage vs
'Temperature
'

,.f."" f.""
I--"

~.

..... ~

-:;-

.5

Supply Current va
Temperature·· '.

,,~

ILNegstiv8

!

60

~

SO

Vs = :l:5V

" " VIN = O.5Vpp

~

40
30

~
~

20
10

100

lk

10k lOOk

Frequency (Hz)

1M

10M

10

100

lk

10k lOOk

1M

10M

Frequency (Hz)

TLlHII2336-3

2-268

Typical Performance Characteristics Unless otherwise noted, TA =
Open Loop
Frequency Response
lID

lID

Vs =i:15V

60

60

......

20

$

0

Ii'

~

90 3

J

r"'~

-20

20

~

0

c

45

'"

40

~

lID

Vs = :tsv

80 ......

40

Gain Bandwidth Product
vs Supply Voltage

Open Loop
Frequency Response

80",

~

......

~
3
]
90

i""'I

\

-20

]

1

J

1M

10k

lOOk

1M

frequency (Hz)

70
60

•

1001\

~

':;
:!!

80

50
40

3

c

1"-

60

.!i

~

\

70

']

30
0

!
!

-

r--r-.,

20

,/ "

90

;j

c

;j

95

Vs=:tlSV

/"

85

80
0

~

I

\

1

"'-

100

r

!

i

oc

tOOk

1

Vs = :tsv

~

0

-55°C

500

1000

1500

Vs =..!ill

.....
...........
I

8

:

~

"-

10

0.10
lk

100

1

tOOk

10k

10

100

lk

10k

Slew Ratevs
Input Voltage
3000

~ 3000

/

~ 2500
..! 2000

8

:

~

1500

en

1000

500
0.10

I

10

100

Ik

Frequency (Hz)

10k

lOOk

0
0

2500

/

'i
"-

2000

i

t

/

;;;

1500

10

Supply Voltage (:l:V)

IS

/

""

~
Vs 1=.\5V

1000

500

/
5

I

<:.

/

.l!

lOOk

Frequency (Hz)

4000

~

2000

Input Current Noise
vs Frequency

t

3500

..........

25°C

Load Resistor (a)

Slew Ratevs
Supply Voltage

1

125°C

It,

~

Vs=.m

!

It,

75
2000

1500

......

I

Frequency (Hz)

~

20

17.5

-

\.

Input C",rrent Noise
vs Frequency
10

80

!

10
10k

/'

~

\..2rC

1000

85

~

~

lk

15

12.5

10

:

10

10

7.5

Vs =:tSY

Frequency (Hz)

t

3

c

_'t

,.,.

~

'-'25°C

100

!
t
!t

i\

10

2.5

Large Signal
Voltage Gain
vsLoad

~

~

5

Supply Voltage (iV)

Input Voltage Noise
vs Frequency

VS=:tlSV

:

0

load Resistor (n)

Input Voltage Noise
vs Frequency

!
t
!t

.t 1-55~C
40

Vs -t,15V

~

500

Capacitive Load (pF)

100

50

100M

(

ro~ ~ ~IOOlrol~I~I~roo

125°C

90

--

~

II

c

Large Signal
Voltage Gain
vsLoad

90

at 215°C

l!iY'I
'I' 1~8t

frequency (Hz)

Gain Bandwidth
Productvs
Load Capacitance
~
3
]

' 10M

4~

80

:!!

0

100M

10M

~'\

90

"l!
.!i

$
lOOk

IJI

100

:;

45

0
10k

2SoC (Continued)

0
I

r2

/
3

4

5

6

7

8

9 10

Input Volta.ge (Vp_p)

Tl/HI12336-4

2-269

Typical Performance Characteristics Unless otherwise noted, TA =
Open Loop Output
' Impedance vs Frequency

Slew Ratevs
Load Capacitance
2500
2000

~

~
0::

~

1500'
,

1000

500
0
0

:s

i

Sinking

"- .........
100

200

-

I

400

lOOk

10N

1M

lOON

Large Signal
Pulse Response
Ay = + 1, Vs == ± 15V

'>'

1\

i'

I

';

:=

'>'

~

1\

~

0

1\

Large Signal
Pulse Response
Ay = +2, VS= ±15V

-

e

1\

§

TINE (20 "sid;,)

~E
0
Q

\

g
TIME (20 "sid;,)

Small Signal
Pulse Response
Ay = +1, Vs = ±15V

'>'

Q

~
~
~

\

TINE (20 "s/dl,)

Small Signal
Pulse Response
Ay = -1, Vs= ±5V

0

g

'>'

i

~
g

~E

J

Large Signal
Pulse Response
Ay '" + 2, Vs = ± 5V

~

';

~

1\

TINE (20 "sid;,)

TIME (20 na/div)

'>'
~

I
1/

I

~

g

>'

~

10k

Large Signal
Pulse Response
Av= -1,Vs= ±5V

'>'

~

srl11i~i

5

100M

Large Signal,
Pulse Response
Av = -1, Vs = ±15V

~,
0

10N

FREQUENCY (Hz)

Small Signal
Pulse Response
Ay = -1, Vs = ± 15V

Q

1M

FREQUENCY (Hz)

TINE (2 "sid;,)

E

srwml~
10k ,,' lOOk

LOAD CAPACITANCE (pr)

~

~
g

15

:!

10
500

Large Signal
Pulse Response
Ay = + 1, Vs = ±5V

~

~~

10

TittlE (20 ns/div)

~

w

15

~

300

20

:s

20

w

'>'

~

25

p_p
VS=.t1SV

\\

"

Open Loop Output
Impedance vs Frequency

Vs ='15V

25

IYour ='"20V=+2

1

25'C (Continued)

II

~

g
TINE (20 "sid;,)

TINE (20 "sid;,)

TLlHI12336-6

2-270

Typical Performance Characteristics Unless otherwise noted, TA =
Small Signal
Pulse Response
Ay = + 1, Vs = ±5V

Small Signal
Pulse Response
Ay = +2, Vs = ±15V

Small Signal
Pulse Response
Ay = +2, Vs = ±5V

'>

'>

~E
""

~E
""

&

r

II

\

Closed. L!)op Frequency
Response vs Supply
Voltage (Ay = + 1)

Closed Loop Frequency
~esponse vs Supply
Voltage (Ay = + 2)

I I

I

I

r-t -I

V5 =.2.75

.,

I I
I I
1M

f-

~

-20

10M

100M

-

-20

-

10M

15

220 pF

\

100M

Closed Loop Frequency
Response vs Capacitive
Load (Ay = + 2)
IS

I

III

13

220 pFJ

I

V5 =·5V
100pf

y

50 F
1.5pF

I

50pf

Z

I
1.5 pf

z

1\
\

1\
,\
\
\

~

-3

III

-I

100M

~

-5
1M

300U

1\

-3

-5

10M

10M

FREQUENCY (Hz)

1M

100M 200M

10M

Total Harmonic Distortion
vs Frequency

I

10

Vs = :tlSV
Av = 1
10
I\. = 2.5 kn
Vo = 20Vp_ p

V5 = .5V
Av = 1
1

g

g

"

I

Vs

J

= 2.5 kn
Yo = 5 Vp_p

~

= :l:15V

.Iv

I

"

,'I

= 2
I\. = 2.5kn
Va = 20 Vp_p

g

o. I

~
~

"

0.1

~
~

I
0.0 1

0.01

Total Harmonic Distortion
vs Frequency
10

I\.

100M 200M

fREQUENCY (Hz)

FREQUENCY (Hz)

Total Harmonic Distortion
vs Frequency

0.1

10M

fREQUENCY (Hz)

-1

100

I
I

3

= 1.5 pF-

1M

'1. = 220 pf
f-c..=50pf
lit = 100pf

1M

V5 =015V
100pF

YI~

.,

'1. = 100pF
' I"
'1. = 50pF
I

-

-20

100M

I

13
II

i26 ~F:-.,

G.

l
II.

Closed Loop Frequency
Response vs Capacitive
Load (Ay = +2)

Ys = :l:5V

IL.
-10

-10

FREQUENCY (Hz)

Closed Loop Frequency
Response vs Capacitive
Load (Ay = + 1)

I I III
I I III

V

I
I

I
1M

I

J\

I-- --=rs=tIO
-I V5 =·5

fREQUENCY (Hz)

'1.' =

V5 =.2.75

f--.

I

....,.~

-10

V5 =·5

Vs = t15V

I

51 = 1.5

I

~

V

Vs =:l:l0

-20

Closed Loop Frequency
Response vs Capacitive
Load (Ay = + 1)

I

10

3

-

\

V5 =015,

V5=01S,

-10

I

N

\

TIME (20 ,./dlv)

TIME (20 ns/div)

"i!'

25°C (Continued)

0.01

I0.001

0.00 I
10k

lOOk

1M

Frequency (Hz)

lOW

100M

0.001
10k

lOOk

1M

Frequency (Hz)

10M

100M

10k

lOOk

1M

10M

100M

Frequency (Hz)

TLlH/12336-7

2-271

Ell

~

r-..

.~

r-----------------------------------------------------------------------------------------------,
Typical Performance Characteristics Unless otherwise noted. T A =
Total1iarmonlc Distortion
vs Frequency
10

25°C (Continued)

Undlstorted Output Swing
vs Fr:equency

Undlstorted Output Swing
vs Frequency

,..~-.."mnr--rT

Vs = i5V

Av = 2
,. Rc = 2.5kll
Yo = s,vp_p
0.1

0.01

0.001
10k

lOOk

10M

1M

100M

Frequency (Hz)

Frequency (Hz)

Undlstorted Output Swing
vs Frequency
30

,

~

r-r-TTllrTTTTrll l ....-r ~

25~1""~111
Hf+'.ulJJIL-'-H'

20

1% t.l,ax.
Distortion'

5

r:

VS=

~~~~
~ kll 1M

"
r-r-rnl"111111r-I"T"TTllnnr-2~"
~M.x"""'.

r-

2~-

tl.+.l!lllf-l-IHffIHI

, IW

Distortion

o '-'_____w..L
lOOk

30

25 F=j~mtlF=I~IM· JDistortion

1\[\l

15

Frequency (Hz)

1-H+tttttllllllr-t-++f4llr-+++l+Hll

10' ,

'"''

Vs

.5

c-

10M

= ±15V

Rc = 70011
Av = 1

lOOk

1.8

-++++HAA1*,++I1!HI

1M

~

10M

Frequency (Hz)

100M

r--....

1.6

1

N

1.~

~

~

1.2 ~
1

0.8
. Q.6.

o~------~~~~~~

100M

Total Power
Dissipation vs
Ambient Temperature

Undistorted Output Swing
vs Frequency

;stortion

15 I--++rn"IImr=i-++
11
10

Frequency (Hz)

1

1
I"J

8 Pin DIP,

1"!-...1

.......

\ 1 1"f--+",r'8+-p-ln~sf-0-4'......+-.......-l"-l

I--+--+-+-+--If-......""'i-~
I--t--+-I+I-t--+--i---i
o '--L.-..JIL.-..JIL.-..JL.-..JL.-..JL-J

0.4

0.2

-~O

-20

0

20

~O

60

80

100

TEMPERATURE (Oc)

TLlH/12336-8

2-272

r-----------------------------------------------------------------------------,
LM6171 Simplified Schematic

~

i:
G)

.....
.....
'"

TUH/12336-10

2-273

Application Information
LM6171 Performance Discussion

duce errors in measurement. Instead, the probes can be
grounded directly by removing the ground leads and probe
jackets and using scope probe jacks.

The LM6171 is a high speed, unity-gain stable voltage feedback amplifier. It consumes only 2.5 mA supply current
while providing a gain-bandwidth product of 100 MHz and a
slew rate of 3600VI ,..s. It also has other great features such
as low differential gain and phase and high output current.
The LM6171 is a good choice in high speed circuits.
The LM6171 is a true voltage feedback amplifier. Unlike current feedback amplifiers (CFAs) with a low inverting input
impedance and a high non-inverting input impedance, both
inputs of voltage feedback amplifiers (VFAs) have high impedance nodes. The low impedance inverting input in CFAs
will couple with feedback capaCitor and cause oscillation.
As a result, CFAs cannot be used in traditional op amp circuits such as photodiode amplifiers, I-to-V converters and
'
integrators.

COMPONENTS SELECTION AND FEEDBACK RESISTOR
It is important in high speed applications to keep all component leads short because wires are inductive at high frequency. For discrete components, choose carbon composition-type resistors and mica-type capacitors. Surface mount
components are preferred over discrete components for
minimum inductive effect.
large values of feedback resistors can couple with parasitic
capacitance and cause undesirable effects such as ringing
or oscillation in high speed amplifiers. For LM6171, a feedback resistor of 51an gives optimal performance.

Compensation for Input
CapaCitance

LM6171 Circuit Operation

The combination of an amplifier'S input capacitance with the
gain I!9tting resistors adds a pole that can cause peaking or
oscillation. To solve this problem, a feedback capacitor with
a value

The class AB input stage in LM6171 is fully symmetrical and
has a similar slewing characteristic to the current feedback
amplifiers. In the LM6171 Simplfied SchematiC, 01 through
04 form the equivalent of the current feedback input buffer,
RE the equivalent of the feedback f,esistor, and stage A buffers the inverting input. The triple-buffered outp"ut stage isolates the gain stage from the load to· provide low output
impedance.

CF > (RG X CIN)/RF
can be used to cancel that pole. For LM6171, a feedback
capacitor of 2 pF is recommended. Figure 1 illustrates the
compensation circuit.

LM6171 Slew Rate Characteristic
The slew rate of LM6171 is determined by the current available to charge and discharge an internal high impedance
node capacitor. The current is the differential input voltage
divided by the total degeneration resistor RE. Therefore, the
slew rate is proportional to the input voltage level, and the
higher slew rates are achievable in the lower gain configurations.

YIN ~""'''''-'''I---4H

Your

=::: GN
I

.........

When a very fast large Signal pulse is applied to the input of
an amplifier, some overshoot or undershoot occurs. By
placing an extemal series resistor such as 1 kn to the input
of LM6171, the bandwidth is reduced to help lower the overshoot.

TL/H/12336-11

FIGURE 1. Compensating for Input Capacitance

Power Supply Bypassing
Bypassing the power supply is necessary to maintain low
power supply impedance across frequency. Both positive
and negative power supplies should be bypassed individually by placing 0.01 ,..F ceramic capacitors directly to power
supply pins and 2.2 ,..F tantalum capaCitors close to the
power supply pins.

Layout Consideration
PRINTED CIRCUIT BOARDS AND HIGH SPEED OP
AMPS
There are many things to consider when designing PC
boards for high speed op amps. Without proper caution, it is
very easy and frustrating to have excessive ringing, oscillation and other degraded AC performance in high speed circuits. As a rule, the signal traces should be short and wide
to provide low inductance and low impedance paths. Any
unused board space needs to be grounded to reduce stray
signal pickup. Critical components should also be grounded
at a common point to eliminate voltage drop. Sockets add
capacitance to the board and can affect frequency performance. It is better to solder the amplifier directly into the PC
board without using any socket.

USING PROBES
Active (FET) probes are ideal for taking high frequency
measurements because they have wide bandwidth, high input impedance and low input capacitance. However, the
probe ground leads provide a long ground loop that will pro-

TL/H/12336-12

FIGURE 2. Power Supply Bypassing
2-274

r-----------------------------------------------------------------------.~

iii:

....
......

Application Information (Continued)
Termination

en

....

In high frequency applications, reflections occur if signals
are not properly terminated. Figure 3 shows a properly terminated signal while Figure 4 shows an improperly terminated signal.

> .....IIy~-....-VOUT

TLlH/12336-13

FIGURE S. IsolatIon ResIstor Used
to Drive CapacItIve Load

20nsldlv
TL/H/12336-14

FIGURE 3. Properly TermInated Signal

l00nsldiv
TLlH/12336-16

FIGURE 6. The LM6171 Driving a 200 pF Load
with a SOO Isolation Resistor

Power Dissipation
The maximum power allowed to dissipate in a device is defined as:
Po = (TJ(max) - TfJJ/8JA
Where Po is the power dissipation in a device
TJ(max) is the maximum junction temperature
T A is the ambient temperature
8JA is the thermal resistance of a particular package
For example, for the LM6171 in a so-a package, the maximum power dissipation at 25°C ambient temperature is
730 mW.

TLlHI12336-15

FIGURE 4. Improperly TermInated SIgnal
To minimize reflection, coaxial cable with matching characteristic impedance to the signal source should be used. The
other end of the cable should be terminated with the same
value terminator or resistor. For the commonly used cables,
RG59 has 750 characteristic impedance, and RG5a has
500 characteristic impedance.

Thermal resistance, 8JA, ,depends on parameters such as
die size, package size and package material. The smaller
the die size and package, the higher 8JA becomes. The apin DIP package has a lower thermal resistance (10aoC/W)
than that of a-pin SO (172"C/W). Therefore, for higher dissipation capability, use an a-pin DIP package.

Driving Capacitive Loads
Amplifiers driving capacitive loads can OSCillate or have ringing at the output. To eliminate oscillation or reduce ringing,
an isolation resistor can be placed as shown below in Figure
5. The combination of the isolation resistor and the load
capacitor forms a pole to increase stablility by adding more
phase margin to the overall system. The desired performance depends on the value of the isolation resistor; the bigger the isolation resistor, the more damped the pulse response becomes. For LM6171, a 500 isolation resistor is
recommended for initial evaluation. Figure 6 shows the
LM6171 driving a 200 pF load with the 500 isolation resistor.

The total power dissipated in a device can be calculated as:
Po = Po + PL
Po is the quiescent power dissipated in a device with no
load connected at the output. PL is the power diSSipated in
the device with a load connected at the output;' it is not the
power dissipated by the load.
Furthermore,
Po = supply current
with no load

x total supply voltage

Pl = output current x (voltage difference
between supply voltage and output
voltage of the same supply)

2-275

~ r-------------------------------------------------------------------------------------~

r-.
.....

C#

:=!I

Application Information (Continued)
Pulse Width ModulatOr

For example. the total power dissipated by the LM6171 with
Vs = ± 15V and output voltage of 10V into 1 kO load resistor (one end tied to ground)' is
PD=PO+PL
= (2.5 mAl x (30V) + (19 mAl
= 75mW + 50mW
'
= 125 mW

Rl

R4
S10A

x (15V - 10V)

.....-

>-+-~-

VOUT

Application Circuits
Fast Instrumentation Amplifier
"

.

"

VI

R~

'1 ~A
:Rl
SI0A',
/1

R6

lkA:

.JL/H/12336-19
I~'{f'

Design Kit

R3

A design kit is available for the LM6111. The1design kit con,
tains: '

VOUT

51D'l, ,

•
•
•
•

114
,510:0

V2

R5

R7

tkn

1 kA

High Speed Evaluation Board
LM6171 in 8-pin DIP Package
LM6171 Datasheet
Pspice Macromodel Diskette With the LM6171 Macromodel,'
,
, ";'~

• An Amplifier Selection, ,Guide
TUH/I2336-17

Pitc~Pack'

V1N=V2-Vl

A pitch pack is
contains: ."

II R6 = R2. R7 = R5 and R' = R4

VOUT =~(, +2f!!) =3'
VIN

R2

avaiiablef~rtlW'LM61i1~+he
,

"

pitch pack

"

• High Speed Evaluation Board
• LM61'71"1~ S-pin DIP Package
• LM6171 Datasheet
• Pspice Macroinodel 'Dlske.tteWith1he l-M6171 Macromodel'

R3

MuHivlbrator
Rl

Contact your local National Semiconductor sales office to
obtain a pitch pack.
~~~-...-

....- - VOUT

TLlH/12336-18

f = ------..:.'-'- - -

2(R'~ln(1+2~))

1= 4 MHz

2-216

Ii....

f:}1National Semiconductor

LM6181100

....
Q)

mA, 100 MHz Current Feedback Amplifier

General Description

Features (Typical unless otherwise noted)

The LM61B1 current-feedback amplifier offers an unparalleled combination of bandwidth, slew-rate, and output current. The amplifier can directly drive up to 100 pF capacitive
loads without oscillating and a 10V signal into a 50n or 75n
back-terminated coax cable system over the full industrial
, temperature range. This represents a radical enhancement
in output drive capability for an B-pin DIP high-speed amplifier making it ideal for video applications.
Built on National's advanced high-speed VIPTM II (Vertically
Integrated PNP) process, the LM6181 employs currentfeedback providing bandwidth that does not vary dramati'cally with gain; 100 MHz at Av = -1, 60 MHz at Av =
-10. With a slew rate of 2000V/ ,.S, 2nd harmonic distortion
of -50 dBc at 10 MHz and settling time of 50 ns (0.1%) the
LM61B1 dynamic performance makes it ideal for data acquisition, high speed ATE, and precision pulse amplifier applications.

•
•
•
•
•
•
•

Slew rate
' 2000 V /,.s
Settling time (0.1 %)
50 ns
Characterized for supply ranges
± 5V and ± 15V
Low differential gain and phase error
0.05%, 0.04·
High output drive
± 10V into 100n
Guaranteed bandwidth and slew rate
Improved performance over EL2020, OP160, ADB44,
LT1223 and HA5004

Applications
•
•
•
•
•

Coax cable driver
Video amplifier
Flash ADC buffer
High frequency filter
Scanner and Imaging systems

Typical Application

---t

v i n -.....

VIN

50n CABLE

50n

(2V/div)

VOUT
(2V/div)
Tl/H/11328-1

Cable Driver

TIME (5Dns/div)
TUH/11328-2

Connection Diagrams (For Ordering Information See Back Page)
8-Pln Dual-In-Llne Package IN)I
Small Outline IM-8)

N/c
INVERTING INPUT
NON'-INVERTING INPUT
V-

16-Pln Small Outline Package 1M)

• v-

N/c,

INVERTING INPUT
NON-INVERTING INPUT

V+
OUTPUT

N/c

·Heat Sinking

TUH/11328-3

Order Number LM61811N, LM6181AIN,
LM6181AMN, LM6181AIM-8, LM61811M-8
or LM6181AMJ/883
See NS Package Number J08A, M08A or N08E

pins (Note 3)

• vNle
Nle
N/c
• V-

1

16

V-'

2

15

N/e

3

N/c
N/c
N/c

4

5
6

7
B

V+
10

'-----1t"-'-- OUTPUT
9

V- •
TL/H/11328-4

Order Number LM61811M or LM6181AIM
See NS Package Number M16A

2-277

Absolute Maximum Ratings

(Note 1)
It Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltag~ , ' "
Differential Input Voltage

. '.

,

" Output Short Circuit
Storage Temperature Range
Maximum Junction Temperature
ESD Rating (Not~ 2)
"
'

:*' 1.8V

±6V
± Supply voliage
,15mA

Input Voltage'
Inverting 'Input Current

SOldering Information
Dual-In-Line Package (III) Soldering (10 sec)

260"C

Small Outline Package (M)
Vapor Phase (60 seconds)
Infrared (15 seconds)

215'C
220"C

Operating RatlngJ

Thermal Resistance (6JA. 6JCl
8·pin PIP (N) ,
.
, 8-pinSa (M-8)
16-pin SO (M) ,

LM6181AM

== 1 kO imlells otherwise noted. B~'clfac.
lM6181AI

2.0

3.0

2.0

4.0
5.0

TC Vos Inp,utOffsetVoi1alle (:lrift

,'i~~ri!ng Input Bias Cum~nt,,'

Ie

\,'.1

'

'j

'"

;"

....

0.5

3.0

max

5.0

10

10

0.3

0.5

Vs = ±4.5V. ±16V

0.5

0.05

-10V;;; VCM;;; +10V

0.5

0.3

Common Mode Rejection Ratio

60

-10V;;; VCM;;; +10V

0.5

Vs = ±·4.5V. ± 16V

..'

80

AV = -1. f = 300 kHz

Output Voltage Swing

"

70

0.3

12

11

RL = 1000

130

0.1
60'

2-278

0.5
50

80

70

0.1

10

11.

11

60
80

100

85

0.5
50
70

85

dB
min
dB
min

0.2,

o

10

MO
, min

12

11
11

11

8.0
130

max

50

11
10

p,A/V

0.75

0.5

70

12

0.5

3.0
1.0

50

11
11

75

0.3

0.5

10

100

0.05

.0.75

7.5
Output Short Circuit Current

0.5

0.75

4.5

1.5

"

0.2

0.2
10

RL = 1 kO

0.5

0.05

0.5
50

0.3

3.0

0,,75
0.1

Powet Supply Rejection Ratio' I

0.5

0.3

3.0

!'lOn-Inverting Input Resistance,

ISC

p,A

1.5

3.0

'70

Vo

17.0

10

Non-lnvertinglnputBiasCurrent -10V;;; VCM;;; +10V
Common Mode Rejection.

,

p,VI'C
10

12.0

30

1.5

Inverting Input Bias Current
Common Mode Rejection

OUtput Resistance

5.0

30

,50

RO

5.0

mV
max

nArC

" ,,

N6n~ll)vertipgl;,Put,Biasquri;e.nt

PSRR

5.0
~.5

30

Power Supply Rejection

CMRR

1.5

3.5
5.0

2.0

3.0

Inverting Input .Bi~S CurrenfDrift ' ' ,

Ie:
'. Invprting Input Si~s Curren1Ys'",:. ... ± 4.5V. ± 16V
PSR " Po~r Supply Aejecti~n
., "

Ie
CMR

5.0

0.5

,

CurrenrDrift

3.0

12.0

l'Iion~lnvertin9.lnput,Bias'

"

LM61811

,I' 3.5"
5.0

2.0

Non::inverting Input Bias Cu":~rit
\.

TC Ie

.~;

102-C/W.4ZOC/W
153"C/W.42"C/W
, 70"C/W. 38'C/W

Typical Limit Typiclli U~it Typical Llnlit Units
(Note 4) (Note 5) (Note 4) (Note 5) (Note 4) (Note 5)

Conditions

Input Offset Voltage

Vos

7Vt032V

Junction Temperat1.lre Range (Note 3) ,
LiIt16181AM
-55'C;;; TJ ;;; +125'C
LM6181AI. LM61811
-40"C;;; TJ $: +85'C

± 15V DC Electrical Characteristics

Parameter

150"C
",±3000V

Supply Voltage Range

The following specifications apply for Supply Voltage = ± 15V. RF' == 8200. arid RL
limits apply at the temperature extremes; all other limits TJ =, 25"C. ,

Symbol

'. iNote 7)
-65'C;;; TJ;;; +150"C

10

V
' min

8.0
130

100

85

mA
min

r-

a::::
en

± 15V DC Electrical Characteristics (Continued)
The following specifications apply for Supply Voltage = ± 15V, RF = 820n, and RL = 1 kn unless otherwise noted. Boldface
limits apply at the temperature extremes; all other limits TJ = 25'C.
LM6181AM
Symbol

Parameter

Transimpedance

ZT

Conditions

Typical
(Note 4)

RL = 1 kn

LM6181AI

Limit
(Note 5)

Typical·
(Note 4)

1.0

1.8

1.8

0.5
RL = loon

1.4

No Load, Vo = OV

7.5

1.4

V+ - 1.7V
V- + 1.7V

Input Common Mode
Voltage Range

1.0

1.8

7.5

Units
Limit
(Note 5)
0.8

0.4
1.4

0.4

10

10

0.7

V+ - 1.7V
V- + 1.7V

Mn
min

0.35
7.5

10

10

10
VCM

Typical
(Note 4)

0.8

0.4
Supply Current

Is

LM61811

Limit
(Note 5)

0.5

0.8

....
C»
....

10
V+ - 1.7V
V- + 1.7V

mA
max
V

± 15V AC Electrical Characteristics
The following specifications apply for Supply Voltage = ± 15V, RF = 820n, RL = 1 kn unless otherwise noted. Boldface
limits apply at the temperature extremes; all other limits TJ = 25'C.
LM6181AM
Symbol

BW

Parameter

Closed Loop Bandwidth
-3dB

Conditions

LM6181AI

LM61811

Typical
Limit Typical
Limit Typical
Limit
(Note 4) (Note 5) (Note 4) (Note 5) (Note 4) (Note 5)

Av= +2

100

100

100

Av = +10

80

80

80

Av = -1

100

80

100

80

100

Av = -10

60

60

60

PBW

Power Bandwidth

Av= -1,Vo=5Vpp

60

60

60

SR

Slew Rate

Overdriven

2000

2000

2000

Av= -1,Vo'= ±10V,
RL =; 150n (Note 6)

1400

Is

Settling Time (0.1 %)

Av= -1,Vo= ±5V
RL = 150n

t r, tf

Rise and Fall Time

tp
in(+)

1000

1400

1000

1400

80

1000

Units

MHz
min

V/",s
min

50

50

50

Vo = 1 Vpp

5

5

5

Propagation Delay Time

Vo = 1 Vpp

6

6

6

Non-Inverting Input Noise
Current Density

f=lkHz

3

3

3

pAl.;Hz

iri(_)

Inverting Input Noise
Current Density

f = 1 kHz

16

16

16

pAl.;Hz

en

Input Noise Voltage Density f = 1 kHz

4

4

4

nVl.;Hz

ns

Second Harmonic Distortion 2Vpp,10MHz

-50

-50

-50

Third Harmonic Distortion

2Vpp, 10 MHz

-55

-55

-50

Differential Gain

RL = 150n
Av= +2
NTSC

0.05

0.05

0.05

%

RL = 150n
Av= +2
NTSC

0.04

0.04

0.04

Deg

Differential Phase

2-279

dBc

•

±

5V DC Electrical Characteristics:
"
The fOllowing specifications apply for Supply Voltage = ;t5V, RF ;"" 8200., and RL = 1 kn unl~ss otherwise',noted. Boldface
limits apply at the temperature extremes; all other limits TJ = 25°C.
\
LM6181AM

',.

Symbol

Vos

Parameter

LM6181AI

Input Offset Voltage

1.0

2.0

1.0

3.0
TCVos Input Offset Voltage Drift
Ie

"

Inverting Input
Bias Current

Ie
PSR

5.0

i.e

1.5

-,

3.0

3.0

Vs = ±4.0V, ±6.0V

0.3

0.5

0.3

0.05

0.5

+2.5V

Common Mode
Rejeqtion Ratio

-2.5V:S: VCM

:s:

+2.5V

PSRR

Power Supply
Rejection Ratio

Vs = ±4.0V, ±6.0V

RO

Output Resistance

,

Av = -1,1 = 300kHz

RIN

Non-Inverting
Input Resistance

Vo

Output Voltage Swing

0.3

0.5

0.05

0.5

0.3

0.12

50

47
80

70

RL = lOOn

80

/l-A
max

5.0

70.

/l-AIV
max

1.5
0.12

0.5

0.5
57

50

47
80

64

dB
min

84
0.

8

8

8

Mn
min

2.6

2.25

2.6

2.2

2.0
75

1.4

0.75

1.0

0.5

6.5

8.5

2.2

2-280

,,2.6

2.0
75

2.2

0.75
0.5

1.0

8.5

1.0

mA
min

0.4

Mn
min

0.2
6.5

8.5

8_5

8.5
V+ - 1.,7V
V- + 1.7V

V
min

0.6

0.3

0.25
6.5

75

70

0.4
1.0

2.0

2.0
100

70
1.4

2.25

2.25

2.0
100

8.5
V+ - 1.7V
V- +1.7V

2.25

2.25

0.25
No Load, Vo = OV

50

1.0

0.25

0.35

=: won

0.3

70

70

RL

0.5

0.5

0.5

0.25

100
RL =1 kn

0.5

1.0

0.25

2.0
Output Short
Circuit Current

0.05

47

70

RL = 1 kn

0.5

0.5
57

2.2

Input Common Mode
Voltage Range

3.0

1.0

1.0

1.0
57

0.3

0.5

1.0
0.12

0.5

0.5

0.5

0.5

:s:

Supply Current

/l-vrC

nArC

Inverting Input Bias Current Vs = ±4.0V, ±6.0V '
Power Supply Rejection

Transimpedance

mV
max

17.5

27.0
0.25

3.0

-2.5V:S: VCM

VCM

1.5

Non-Inverting Input
Bias Current Drift

Non-Inverting Input
Bias Current
Common Mode Rejection

Is

5.0

50

+2.5V

ZT

10

50

:s:

Isc

2.5

22
0.25

3.0'

3.5

50

Inverting Input Bias purrent -2.5V:S: VCM
Common Mode Rejection

CMRR

, 1.5

1.0

Inverting Input Bias
Current Drift

Non-lrlVerting Input
,Bias Current
Power Supply Rejection
Ie
CMR

10

22
0.25

2.0

2.5
2.5

2.5
5.0

, Non-Inverting Input
Bias Current
TCle

LM61811

Typical
Limit
Typical
Limit
Typical
Umlt Units
(Note 4) (Note 6) (Note 4) (Note 5) (Note 4) (Note 5)

Conditions

V+ - 1.7V
V- + 1.7V

mA
max
V

r-

± 5V AC Electrical Characteristics
The following specifications apply for Supply Voltage = ± 5V, RF = 8200, and RL = 1 kO unless otherwise noted. Boldface
limits apply at the temperature extremes; all other limits TJ = 2SOC.
LM6181AM
'Parameter

Symbol

BW

Conditions

LM6181AI

50

50

Av = +10

40

40

Av =-1

55

35

55

Units

50
40
35

55

35

MHZ
min

375

V/ILS
min

Av = -10

35

35

35

PBW

Power Bandwidth

Av= -1,VO=4Vpp

40

40

40

SR

Slew Rate

Av = -1, Vo = ±2V,
RL = 1500 (Note 6)

500

1s

Settling Time (0.1 %)

Av = -1, Vo = ±2V
RL = 1500

50

50

50

tr, tl

Rise and Fall Time

Vo = 1 Vpp

8.5

8.5

8.5

1p

Propagation Delay Time

Vo = 1 Vpp

8

8

8

in(+)

Non-Inverting Input Noise
Current Density

f = 1 kHz

3

3

3

pAl.JHz

in(_)

Inverting Input Noise
Current Density

f = 1 kHz

16

16

16

pAl.JHz

en

Input Noise Voltage Density

f = 1 kHz

4

4

4

nVl.JHz

Second Harmonic Distortion

2Vpp,10 MHz

':'45

-45

-45

Third Harmonic Distortion

2Vpp,10MHz

-55

-55

-55

Differential Gain

RL = 1500
Av= +2
NTSC

0.063

0.063

0.063

%

RL = 1500
Av= +2
NTSC

0.16

0.16

0.16

Deg

Differential Phase

375

500

375

500

ns

dBc

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate condHionslhe device is intended to
be functional, but device parameter specifICations may not be guaranteed under these conditions. For guaranteed specifications and test condHions, see the
Electrical Characteristics.
Note 2: Human body model 100 pF and 1.5 kG.
Note 3: The typical junction-te-ambient thermal resistance 01 the molded plastic DIP(N) package soldered directly into a PC board is 10Z'ClW. The junction-to-ambient thermal resistance of the S.O. surface mount (M) package mounted flush to the PC board is 7f1'C/W when pins I, 4, 8, 9 and 16 are soldered to a total 2 in2
1 oz. copper trace. The 16-pin S.O. (M) package must have pin 4 and at less! one of pins 1, 8, 9, or 16 connected to V- for proper operation. The typical junctionto-ambient thennal resistance of the S.O. (M-8) package soldered directly into a PC board is 153"C/W.
Note 4: Typical values represent the most likely parametriC norm.
Note 5: All IimHs guaranteed al room temperature (standard type faea) or at operating temperature extremes (bold face type).
Note 6: Measured from + 25% to + 75% of output waveform.
Note 7: Continuous short clrcuH operetlon at elevated ambient temperature-can 'result irrexceeding the maximum allowed junction temperature 01 15f1'C. Output
currents in excess

~f

± 130 rnA over a long term basis may adversely affect reliability.

Note 8: For guaranteed MIIHary Temperature Range parameters see RETS6181X.

2-281

CD

LM61811

Typical Limit Typical
Limit
Limit Typical
(Note 4) (NoteS) (Note 4) (Note S) (Note 4) (NoteS)

Closed Loop Bandwidth -3 dB Av= +2

....
....

en
==

•

....

GO

~

....
::IE

Typical Performance Characteristics
CLOSED-LOOP
FREQUENCY RESPONSE
Vs = f 15V; R, ;= 82Oll;
R(= lkO

I--

~~~

I-- -~

~I~~

-

f- _1~~I~lll
0.8

1111
11111
1M

10M

0.8

f1M

I\. = lk ....
I\. = 100
I\. = 150

,

90°

i

135°

e

180°

t:

i

~

-

i'

10M

.1,

II
1M

10M

iii

~
"

Vs

Vs = t7.SY

~\

Vs =:I:5Y

llt
II14MI·

~

10111 .

z

1i

~

I-'-

1M

I\. = 1.
I\. = 150
I\. • 100

z

~

g

135 0

ffI-1M

I\. = lk
I\. = 150
I\. • 100
10M

\
100M

100M

NON-INVERTING GAIN
FREQUENCY RESPONSE
Vs = ±15V;Av = +2;
R, = 8200
O·

135°

'ti'

90°

~

~
t:

iii

i

.45°

~

e

e
z

1i

6.8

~ ~.

~

10M

I\.
I\.
I\.

100M

iii

= lk
= 150
= 100
I II

10M

e ~

100111

INVERTING GAIN
FREQUENCY RESPONSE
Vs= ±5V;Av= -10;
R, = 8200
180 0
135 0

90°

~

~

z

iii

1i

~

g

.~

i\

1

~

45°
0°

~ 20dB

20.8

~

I\.
I\.
I\.
1M

= lk
= 150
= 100
I III

10M

~

100M

e

90· . ~
135°
180° t:

1

180 0 ~

6.8

10M

II

O·

1i

1M

INVERTING GAIN
FREQUENCY RESPONSE
Vs = ±15V;Av = -10;
R, = 8200

90·

~\

l\\
1\\\

III

.45°
O·

0.8

NON-INVERTING GAIN
FREQUENCY RESPONSE·,
Vs = ±5V;Av = +2;
R, = 8200

~
e

=j:'2.5V
= tlDV

~WIL

100M'

e

1111

45·

100M

vs' = :l:7.SV
Ys = :t5v

"N.I~\\\

~
~

100M

.....

~,

180·

135° fij'

t:

iii

Vs = .tf5V

INVERTING GAIN
FREQUENCY RESPONSE
Vs = ±5V;Av'= -1;
R, = 8200

90°
45° ::::
O·
t:

~,

10M

Ys

t10V

180·

oda

180°

f-

11111111
'·11111111
11111111

111111
1111
1M

-

FREQUENCY RESPONSE
vaSUPPLY VOLTAGE
Av = -1; R, = 8200;
RL = 1500

J, 1=1l\~J
vs"

e

100M

I\. = lk
I\. = 150
I\. = 100

1M

Ys = :t12.SV

~

45 0

I III

11111111
11111111

O·
.45° -

I",

-...
z

~
100M

9;;. i

I\. • lk
I\. = 150
I\. = 100

~

10M

O·

1
0.8

FREQUENCY RESPONSE
va SUPPLY VOLTAGE
Av = -);R, =.8200;
RL= lkO

INVERTING GAIN
FREQUENCY RESPONSE
Vs = ±15V;Av = -1;
R, = 8200

1i

z

1i

I-'~'~'~'~

1M

~

I-I--

I-'~ '1'~~

111111

100M

~

-...

~e

I-'~ 11'~IJ

111111

I'
I

~g

,~ ~I~l~

\\

UNIT GAIN
FREQUENCY RESPONSE
Vs = ±5V;Av = +1;
R, = 8200

~

UNITY GAIN
FREQUENCY RESPONSE
Vs = ±15V;A'; = +1;
R, = 8200

CLOSED·LOOP
FREQUENCY RESPONSE
Vs = ± lSV; R, = 8200;
RL = 1500

.~I~I~llll

f- ~I~

TA = 25·CUhless'otherwisenoted,.

~

E
~

~
t:

iii

1M

I\.
I\.
I\.

= lk
= 150'"
= 100'"

10M

~

-

~

if

lOON
TL/H111328-5

2·282

Typical Performance Characteristics

~

en
.....

TA = 25°C unless otherwise noted (Continued)

CO

.....
NON-INVERTING GAIN
FREQUENCY RESPONSE
Vs = ±15V;Ay = +10;
Rf = 8200

NON-INVERTING GAIN
FREQUENCY RESPONSE
Vs= ±5V;Ay= +10;
Rf = 8200

NON-INVERTING GAIN
FREQUENCY COMPENSATION
Vs = ±15V;Av = +2;
RL = 1500

t-~ ~Imu

0°

1
1

I--

I\.

1M

I\. = lk
= 150 • 100

~

Iii

1\

10M

1

~

I\. =
I\. =
I\. =

I-I-I--

fOOM

II ill
II ill
1M

100W

ION

120

9

r-' -550C
~~1250C

80

E

8~+250C

~

3

60

~

= :t'5V

Vs"=.5V~

20

-3

-8

1.0

1.5

2.0

2.5

3.0

3.5

OO

80
.70
60

-55°C

50
.0
30
100

lk

1000

TRANSIMPEDANCE
vsFREQUENCY
Vs = ±5V
RL= lkO

130

130
120

130

110

110

110

100
90

g-

90

80

~

80

~

80

70

:;r

70

!r

60

60

50
.0

50

•0

30

30

lOOk

I.

ION

57mV

30

10k

25mV

EDGE 5mV

II

IIlV

-0.2"
+0.2"

-0.2"

RISING
EDGE

-43mV
-19.6ns

lOOk

1M

10.

lOON

180•.4ns

10k

lOOk

IN

100M

SUGGESTED Rf and Rs for CL
Av = - 1; RL = 1500

LI
1I

5dB PEAKINil

+0.25"

START

vs··~

-0.25"

J

Sf....,

1000

+0.25"

~

-0.25"

~

RISING
EDGE

-19.6ns

,.

10000

-25mV

20ns/dlv

10.

70

..

+0.2" FALLING

lrAV

100M

60

SETTLING RESPONSE
Vs = ±5V; RL = 1500;
Vo = ±2V;Ay = -1

±

10mV

10M

50

lk

lOON

SETTLING RESPONSE
Va =
15V; RL = 1500;
Vo = ±5V;Ay = -1

FALLING

I.

100

g-

10k,

lOOk

120

00

lk

10k

TRANSIMPEDANCE
va FREQUENCY
Vs = ±5V
RL = 1000

120
100

EDGE

100

R LOAD (n)

TRANSIMPEDANCE
va FREQUENCY
Vs = ±15V
RL = 1000

:;r

:;;r

I-- +12S0C
usoe

F
I--

Rf • R. (kn)

!

g~

-0 t--12
-15
10

o
0.5

110

0

~

lOON

130

12

11.

ION

TRANSIMPEDANCE
va FREQUENCY
Vs = ±15V
RL = 1 kO

15

100

:\ Ys

~ ~ 1,~~~~

-~I=lm~l.

lkn
150
100

OUTPUT SWING vs
RLOAO PULSED, Vs = ± 15V,
liN = ±200 ,.A, V,N+ = OV

120

\

~ ~ '/i~~

-

11111

1M

BANDWIDTH va Rf" Rs
Ay= -l,RL= lkO

1.!.

f1
~ 20dB

177

100

ULJ

10
20ns/div

180.4ns

Vs = :I::'5V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Rf • Rs (kn)

TLlH111328-6

2-283

Typical Performance Characteristics

SUGGESTED lit
and Rs FOR CL '
Ay = +2; RL = 1500

SUGGESTED RI"
and RsF:ORCL
Ay= -1
10000

SUGGESTED RI
and RSFOR CL
Av = ,-1\2

10000

10000
5dB PEAKING

5dB PEAKING

VS '·5V ...

1000

.e

,r'17fV

~

s • O1SV-

I'

j I I I

1.0

I-"

= :I::5Y

Vs

.e

100

10,I
0.5

5dB PEAKING

Vs = :t:5V

1000

~

C

~

,TA= 25°Cunless otherwise noted (Continued),

I I

1.5 ' 2.0

2.5

.y I r Vs •

, 100

I

0.5

3.5

1.0

1.5

II

2.0

2.5

I
3.0

I I I I I I I

10
3.5

0.5

1.5

1.0

RH Ro (kll)

Rf. R. (kll)

OUTPUT IMPEDANCE YS FREQ
Vs = ±15V;Ay = -1
lit = 8201l

Vs • O1SV

" 100

1'1 I II' I

10

3.0

1/1'

O1SV

2.0

I
2.5

I
3.0

3.5

RH Ro (kll)

OUTPUT IMPEDANCE V8 FREQ
Vs = ±5V;Av = -1
RI = 8200

, PSRR (VS +) VB FREQUENCY
, 70
&0
50

f6H+H1f1111--I+

16 H+HIHfIt+I+flIIIf-;.tCI-I+HIH

:s.S' (

H-t-hflfHl-boKtltlll-+l+fIlHI--I

'ii1
.3

~

(a
Vs'
:l:15V

30
20
10

Vs =
05V

CII:

0.251'9+HfIfHI-t+ttItlll-+I+fIIHI--I
200

20

20

FREQUENCY (MH.)

~

70
60
'50

1111111111
1111111111
111111 III

40
30

+15V

Vs

10k

l00fc

1M

IllIml

70
60
50

=

Vs

1M

ION

lOON

100

E

':::

E

='

:t:'5V

vs'
.sv

10

1

10M

fOOM

fk

10k

lOOk

1M

10M

100M

FREQUENCY (Hz)

FREQUENCY (Hz)

SLEW RATE VB
TEMPERATUREAy = -1;
,RL = I~OIl, Va = ± 15V

INPUT CURRENT
NOISE V8 FREQ!JENCY

10000.~
SLEW RATE

f[

~

S
~

7

1000

NEGATIVE

~i!~~~~~~~~
SLEW RATE
POSITIVE

0.01

0.1

10

100

FREQUENCY (kHz)

SLEW RATE VB
TEMPERATUREAy = -1;
RL ,;", 1500, Vs = ±5V
SLEW iiATE
1000.~
POSITIVE
SLEW RATE
NEGATIVE

++++H-I-HH

10011111

100l1li_
10UUUU~~~~~UUUU

100
FREQUENCY (kH.)

l00fc

INPUT VOLTAGE NOISE
vs FREQUENCY

CMRR VB FREQUENCY

111111
111111
111111
lk

10k

FREQUENCY (Hz)

Vs =
+SV

,20
10
0

lk

FREQUENCY (MH.)

PSRR (Vs-) Y8 FREQUENCY

'ii1
.3

200

-60 -(a -20

a

20

(a

60 60 100 120

TEMPERATURE (Oc)

10~~~~~UUUUUUUU~

-60 -(a -20

a

20 40 60 80 100 120

TEMPERATURE ,(Oc)

TUH/11328-7

2-284

Typical Performance Characteristics

riii:
G)

....

TA = 25"C unless otherwise noted (Continued)

CO
....
-3 dB BANDWIDTH
V8 TEMPERATURE
Ay- -1
140

Vs

12.

!

~

= :l:15V

"'=,.

100

!

Vs = :tI5V
... = 100D

§

!;!

;:

60

"'-,.

::I

I.

llUll

Vs" :l:5V

6O~
40
-60 -40 -20

Vs=:l:SV

a

9

a

a

7
6

]
PROPAGA.TlON DELAY

"

;:

TEMPERATURE (Oc)

!

9
PROPAGATION DELAY

FALl. TIME

8
RISE TIME

,

FALL TIME

5

]
~

~

7

... ,
7

RISE TIME

.5

6

~

5

4

4

3

3

2
-6D -40 -2D 0 20 40 60 60 100 120

2
-60 -40 -20 0 20 40 60 80 100 120

9

•

8

a

-IMLIT:M~

5

!

PROPAGATION DELAY

!;!

TEMPERATU.E (Oc)

SMALL SIGNAL PULSE
,RESPONSE va TEMP, Ay - -1
Vs - ±5V; RL - 1000
9

'

~.l,~AJ..~,~~ JE~Ji

I

M

,

7

FALL TIME
RISE TIME

;:

i.f'

4
RISE TlWE
3
-80 -40 -20 0 20 40 60 60 100 120

SMALL SIGNAL PULSE
RESPONSE va TEMP, Av - -1
Vs- ±5V;RL-lkO

7

7

,

PROPAGATION DELAY

5

TEMPERATURE (oc)

SMALL SIGNAL PULSE
RESPONSE va TEMP, Av - -1
Vs - ±15V;RL - 1000

~

a

PROPAGATION DELA!.f+f

TEMPERATURE (Oe)

!

SMALL SIGNAL PULSE
RESPONSE va TEMP, Av - -1
Vs - ± 15V; RL - 1 kO

ID

8

FALL TIME

TEMPERATURE (Oc)

SMALL SIGNAL PULSE
RESPONSEvsTEMP,Av - +1
Vs - ±5V;RL - 1000
9

RISE TlUE

2
-60 -40 -20 0 20 .40 60 80 100 120

-80 -.to -20 0 20 40 &0 80 100 120

10

7

6 PROPAGATION DELAY

5

3

FALL TIME

2
20 40 60 80 100 120

SMALL SIGNAL PULSE
RESPONSEvsTEIiIP,Av - +1
Vs - ± 15V; RL - 1000

7

•

RISE TIME

3

SMALL SIGNAL PUL/IE
RESPONSE va TEMP,Av - +1
Vs - ±5V; RL - 1 kO

]:

~

5

TEWPERATURE (Oc)

•

I.

9

•

1\ = 100n

SMALL SIGNAL PULSE
RESPONSE va TEMP, Av - + 1
Vs - ± 15V; RL = 1 kO

!.
~

5

PROPAGATION DELAY
FALL TIME
J..I'"
RISE TIME

"
5

FALL TIME

RISE TIIlfE

4
3,

-60 -40 -20 0 20

.w

60 80 lDO 120

4

4

3

3
-60 -40 -20 0 20 40 60 80 100 120

-60 --40 -20 0 20 .40 60 80 100 120

TEMPERATURE (Oc)

SMALL SIGNAL PULSE
RESPONSE va TEMP, Ay - +2
Vs - ±15V;RL - 1 kO

SMALL SIGNAL PULSE
RESPONSEvsTEMP,Av - +2
Vs - ±15V; RL - 1000

SMALL SIGNAL PULSE
RESPONSE vs TEMP,Ay - +2
Vs - ±5V:RL - 1 kO

13

13

13

12

12

12

II

:11

II

10

10

10

!

9

!;!

8

;:

TEMPERATURE (Oc)

TEMPERATURE (00)

,
7

5

:! •
~

~

PROPAGATION DELAY

RISE TINE

4
-'0 -40 -20 0 20 40 60

FALL TIME

eo 100 120

TEMPERATURE (Oc)

8

PROPAGATION DELAY

]:

9

!;!

8

;:

7

PROPAGATION DELA!J.+'

FALL TIME
RISE TIME

7

,

.,SE TIME

5

FALL TIME

4

-ao -40 -20

0 20 40 60

eo

TEMPERATURE (oc)

100 120

6

5
4
-'0 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (Oc)

TL/H/11328-29

2-285

Typical Petformance Characteristics

13

12
11

SMALL.SIGNAL PULSE
RESPONSE va TEMP, Av =
Vs= ±5V;Ri.,,; lOOn

"

;:

~ALL SIGNAL PULSE

+2

'.
H-tH-iPROPAGI.TIOK D~I.Y

12

FALL TIME

10

]:

RISE TIME

9

";<

-5

8

REsPoNSE va TEMP, Ay = -10
Vs = ±15V;RL = lkn

11

10

10

9

8

"

7

]:

5

•

"

12

11

11
PROPAGATION DELAY

-5
~

'"

;:

7

13
11
10

9

8

!

"PROPAOATIOK DELAY

!

7

9

8

PROPAGA.TION OMY

7

6
5

5

5

•

•

•

FALL TIME-t:I;;

RISE TIME

3

-60 -.0 -20 0 20

.4()

-eo -.a -20

60 80 100 120

SMALL SIGNAL PULSE
I;IESPONSE VB :teMP, Av =
Vs = ±5V; RL = an
13

13

.12

12

12
11 FALL TIME

,'; H+t+ PROPAGATioK DELAY

8
7
6

PROPA(;ATIOK DELAY

FALL TIME

!

~

8

'"

i

;:

RISE TIME

•

3
-60 -40 -20 0 20

9 fALL TIME

6
5

3
-60

60, 80 100 120

:::I

•
-.a -20

:l:15V

3.0

3.0

2.5

1.0

s:-

--

TEMPERATURE (DC)

OFFSET VOLTAGE
va TEMPERATURE
..0
3.5

>'S 1.5

3
-60 -.0-20 0 20 40 80 80 100 120

0 20 40 80 80 100 120

TEN~ERATURE (DC)

M

2.0

PROPAGATION DELAY

8
7

6

•
40

-~

.s

Ys

TRANSIMPEDANCE
vsTEMPERATURE
5.0

= :l:5V

U
..0

Vs

=:I:~5V

3.5

2,5

"a

2.0

II

3.0
2.5

N .2.0

>.1.5
1.0
0.5

0.5

+ 10

RISE TINE

9

5

OFFSET VOLTAGE
VB TEMPERATURE
Vs

!
!II
;:

TEMPERATURE (DC)

4Jl

10

RISE TIME

(OC)

SMALL,SIGNAL PULSE
RESPONSE va TEMP, Ay =
Vs = ±5V; RL = loon

+ 10

13

9

0 20 40 80 80 100 120

TE~PERATURE

TEMPERATURE (DC)

+ 10

+ 10

12

8

5

.s

SMALL SIGNAL PULSE
RESPONSE VB TEMP, Ay =
Vs= ± 15V; RL = lkn

6

11
10

s:-

TEMPERATURE (DC)

10
";<

RISE TIME

SMALL SiGNAL PULSE
RESPONSE VB TEMP,Ay =
Vs = ± 15V; RL = lOOn

; ,

RfSEflME

4
-60 -40 -20 0 20 40 60 80 100 120

120

FALL TINE

TEMPERATURE (DC)

i!!

~ ,100

RISE TIME

FALL TIME

-60 -.0 -20 0 20 .0 60 80 100 120

!

fALL 11"[

6

SMALL SIGNAL PULSE
RESPONSE va,TEMP, Av = -10
Vs", ±5V;RL = loon

12

8

h PROPACATION DE~

TEMPERATURE (Oc)

SMALL SIGNAL PULSE
RESPONSE vii TEMP, Av = -10
Vs = ±5V;RL = 1 kn

;:

7

RISE TiMEt

-60 -.0 -20 0 20 .40 60

TEWPERATURE (OC)

!

'"

5

5

10

8

.fALL~

•

-60 -.0 -20 0 20 40 60 80 100 120

SMALL SIGNAL.pULSE
RESPONSE VB TEMP, Av = -10
Vs = '± 15V; AL = loon

9

~

;:

PROPAGATIOK DELAY

.6

6

12

11

~

;:

7

I

TA = 25°C unless otherwise nOted (Continued)

10- r-

"'"

,

0
-55 -35 -15 5 25 45' '6~, 85 IDS '25

0
-55 -35 ciS 5 25 .5 65 85 105 125

TEMPERATURE (DC)

TEMPERATURE (DC)

1.5
1.0
0.5

f-

...

-- I\.~ -~

-

~ i===-

\~o.

-

I\.~l\_ - I

0.0
:-55 -35 -15 5 25 ..

.

os

65 105 125

TEMPERATURE (DC)

TLlH/I132B-B

2-286

Typical Performance Characteristics

.:en....

TA = 25°C unless otherwise noted (Continued)

....

co

TRANSIMPEDANCE vs
TEMPERATURE

QUIESCENT CURRENT
V8 TEMPERATURE

co~
~

PSRR va TEMPERATURE

10r-r-r-~;-'-'--r-r,

5.0
4.5
Ys = :t5V
4.0
3.5
3.0

9

2.5
2.0
1.5 ' 1.0
0.5

~

.....

I\.

= 1 kll

'-.J.-./o'"'

Vs

= i15V

Vs

=t:SV

100

" 0.6
;;
..,
c
0.4
0.2

0.0
-60

I

0JA =. 102°e/W

1.4

in
V1

I

1.8
·1.6

1'\
'\.

.........
..........

.........
-40

-20

020406080

100

120

140

TA AMBIENT TEMP (Oe)
TLlH/1132B-30

N-Package

2.0

~
:z
0
;::
---+-o Your

lkn

,-

TL/H/1132B-24

FIGURE 8

V- ','

82M

82M
f-3dB
,

1

~--

21TRC

'w;.

TUH/1132B-22

7a

(O.5V/div)

VOUT
(ZV/div)

TLlHi11S2B-25

FIGURE 9. Open-Loop Overdrive Recovery Time of 5 ns,
and 25 ns from Test Circuit In Figure 8

7b :,

"

TL/H/llS2B-2S

FIGUI'IES7a..b:RC Li!plts'Amplifler
.Bandwidth to 50 r,lHZ;EIi!'linatlng
Peaking, In the Resulting PUI,se Respense

2-292

Typical Performance
Characteristics (Continued)
The large closed-loop gain configuration in Figure 10 forces
the amplifier output into overdrive. Figure 11 displays the
typical 30 ns recovery, time to a linear output value.

The common-mode input of the circuit in Figure 10 is exceeded by a 5V pulse resulting in a typical recovery time of
310 ns shown in Figure 12. The LM6181 supply voltage is
±5V.

v;n-.....---I

son

Your
(2V/div)

Ison

TL/H/11328-26

FIGURE 10

VIN

(2V/div)

TLlH/11328-28

Your

FIGURE 12_ Exceptional Output
Recovery from an Input that
Exceeds the Common-Mode Range

(5V/div)

VIN

(0.5V/div)

TIME (50 Ds/div)
TLlH/11328-27

FIGURE 11. Closed-Loop Overdrive Recovery
Time of 30 ns from Exceeding Output
Voltage Range from Circuit In Figure 10

Ordering Information
Temperature Range
Package

8-Pin
Molded DIP

Military
-55"Cto + 125"C
LM6181AMN

8-Pin Small Outline
Molded Package

LM6181AMJ/883

NSC
Drawing

LM6181AIN
LM6181IN

N08E

LM6181AIM-8
LM61811M-8

M08A

LM6181AIM
,"LM61811M

16-Pin
Small Outline
8-Pin
Ceramic DIP

Industrial
- 40"C to + 85°C

M16A
J08A

2-293

i

•

I

~
co

~

r--------------------------------------------------------------------------------,

til

Na t ion a I S e m i con du c tor

LM6182 Dual
1QOrn~Outpu.,
"

,

'j;

I

•

.~:

.' 1

100 MHz Current Feedback Amplifier

• ,

','.

Genera, D~sc:..,iption " .'.' ..,

'

Features (Typical unless otherwise noted)

",

The\.,fjil6182· dual currenUSedl)ack amplifier offE!':s an unparallel\Kf .cPmbi~tioil.of banqwidth,sIEilw-ra~e, ,and O\ltput.,
current. .Each aniplifier can. directly drive 82V !lignal into a
500 or ,750 back'~erniinated coax cable system over the
fUIHpdu,m;~1 tempetature' range. This represents radical
erlhanceii1eri,tih output drivQ capabilltYJor a dual 8-pin highsp~'amplifi~r making it ideaifbr "ideb appllp,atlons.
BUilt on National's, adyanced,~igh-speed VIP II'I'M (Vertically
Integra!ed "PNP), process, the .LM61 ~2 '!IrripI9Yfl. currentfeedback .providing bandwidth that does not varY dramatically with gain; 100 MHz,atAv = -1,60 MHz at Av =
-10. With a slew rate of 2000 V/ ".sec, 2nd harmonic distortion of "':50 dBc at 10 MHz and settling time of 50 ns
(0.1 %), the two independent amplifiers of the LM6182 offer
performance that is ideal for data acquisition, high-speed
ATE, and precision pulse amplifier applications.
See the LM6181 data sheet for a single amplifier with these
same features.

a

•
•
•
•
•
•
•
•

Slew Rate
2000 V /".s
Closed Loop Bandwidth
100 MHz
Settling Time (0.1%)
50 ns
Low Differential Gain and Phase Error
0.05%, 0.040
RL = 1500
Low Offset Voltage
2 mV
High Output Drive
± 10V into 1500
Characterized for Supply Ranges
± 5V and ± 15V
Improved Performarl(;e o~lflr OP260, and LT1229.

Applica~io~s:.
•
•
•
•
•

';

Coax CablEid5r;iver ''',
Professional ~tudio Video E'q~ipmerlt •...
Flash APC'aUffEjr i ... ; · , j . '
PC and WorkstatiOn Vid8() Bp8~~
Fa(l$imilean - -....-V02

TUH/11926-12

TL/H/11926-11

XT (Crosstalk Rejection) = VOl
V02

CMRR

PSRR(VS+)

y'

Resistors
Matched to ±0.02%

Test
Signal 0---,
Input
•
35 J-LF

0.1 J-LF

r-I

..L.l. .
-=

820.0.

TUH/11926-13

TUH/11926-14

2·302

Typical Performance Characteristics
Inverting Gain
Frequency Response
Vs = ±15V,Ay = -1, Rt = 8200

(Continued) Vs = ±15VandTA = 25°C unless otherwise noted.

Inverting Gain
Frequency Response
Vs = ±5V,Ay = -1, Rt = 8200

180

90

°

t:

'5
z

~

o

OdB

~
\l
':;
g

"t. =
"t. =

~

1 kll

il:

IsDn

~

~
e
z

.5
OdB

~

0

~

It = 100

lOW

lOOt.!

lOOk

6dB
It

~

\l

It

~

1M

= 1 kn
= 150

lOOk

100M

180

i;i

t
~

lQ1j

IN

°

I

111111111

10M

90
1 35

i

"t. ,~":,OO~
lOON

FREQUENCY (Hz)

Inverting Gain vs
- 3 dB Bandwidth
Rt = 8200

- 3 dB Bandwidth vs
RtandR.,Ay = +2
-;;'00.0

45

Q

~

90

e

!

0

t
180 ~

~

~

~

1 3S
6dB

~

.J:I

1M

I'\~VSi'I'5r It=iklnt

~

80

~ = 1'5Oll

~

60~-++~~~

1\

0.5

lOON

1.0

1.5

2.5

3.0

3.5

10

INVERTING GAIN

(kn)

~

i.'

Ol

H-'k-l"'......2i

:::_:

i'"

40

I;

~~~~:w~

20LJ-LJ-~~~~~-L~

11 0

'"

90

60

8

NON-INVERTING GAIN

Vs

=:l:5V

5°H-~++ffiH-I"~"rH~~~
40
30

2

H-ttlt-H-Ht-t-I'IlH-'.vs = :l:15V

7oH-ttII-I-I~~IiH~rt+m-l

i'"

20

12

H-ttlt-H. .+-HHH-tHt+ttIt-l

100 H-ttII-I-I1!Pti1IiH-ttit+ttII-I
80 H-+tIt-H-Ht-+-HiIP'I~

V i'" "t. =150n

~

Ol

130 =lJJT'T11'JT"",rrn-rnTTTTlT..,

120 FFfflI~-Ht-t-HHH-tHt+ttIt-l

"t. =1 kllkO'"

60

S

Translmpedance vs
Frequency
RL=1kO

~

80

~
3

:-+"'1"-";;<-+-1

10

Rs

100

H"""d-!"'fo-.t=

o

2.0
&

- 3 dB Bandwidth vs
Supply Voltage
Ay =-1

120~

40

"t. = 150ll

"r

. : : ~~!~Sl~~l~
60

~~~r-I
"Or-l~~=F~~~=T+-I

7 20r-l:-t--+-t-+-+-~--++-I

~

Vs = '5V

Non-Inverting Gain vs
- 3 dB Bandwidth
Rt = 8200

::; 100
~ 80

~

=
~

FREQUENCY (Hz)

~

..,~....,."-'

"t. = 1 f:1t

Vs = '5V

0.0

10M

vs7'15,

"0.0

7 20.0

1111 It = 100
111111111
lOOk

80.0

~ 60.0

!:I
il:

"t. = lkn"t. = 150

~

~

·5

120.0

..

.3

~

~

z

FREQUENCY (Hz)

Non-Inverting Gain
Frequency Response
Vs = ±5V,Ay = +2,Rt = 8200

~

t:

1'11111111

FREQUENCY (Hz)

z

~

Q

~
e

°

~

~: :::f

~

g

111111111 I
1M

135
90

It = loon

lOOk

..

180

1 35

Non-Inverting Gain
Frequency Response
Vs= ± 15V, Ay= +2, Rt=8200

10

12

14

16

H-l-tlH-+ltHUlll-+I-+UtlllI+ti
LHt-t+HtW

w..J.J.IW....LI.JJJ.....I.IIII..I.11J.1J.1I1...J...JJ
IW....L..J.J.IUI

lk

10k

SUPPLY VOLTAGE (OV)

Transimpedance vs
Frequency
RL = 1500

lOOk

IN

ION

lOON

FREQUENCY (Hz)

Settling Respon$8
Vs = ± 15V, RL = 1500
Ay=-1,VO=±5V

•

130
120

~
.....
>

110

'"

.3

100
90

~

80

S

70

Iil

Vs

60

,~s =

50

E

= :t15V

30
lk

10k

lOOk

§

f-HH-t-t-+-+++-I-O.l%

-

\l

;;;

'"

1M

f-HH:-t-+--+--++-t--I +0.1"

..

'5V

11111 11111
11111 11111

'0

0

10M

-32 ns

100M

218 ns
TIME (25 n./OIV)

FREQUENCY (Hz)

TUH/11926-15

2-303

N
CD

U;

~

Typical Performance Characteristics
Settling Response
Vs = ±5V, Rl == 1500
Ay = -1,.Vo = ±2V

(Continued) Vs = ± 15VandTA = 25°CunlessothelWisenoted.

Long Term Settling Time
Response Vs = ± 15V,
Rl= 1500,Ay= -1,Vo= ±5V

. Suggested Rt and
Rs for Cl, Ay = -1
10000
Fo, 6·db Peakln

S'

1\

~E

==l-tHI-I-I-I-I-H +0.1%

~

.....

§

.....

I-HI-tt-I-I-I-I-I-H -0.1 %

+0.1%

~

-0.1%

9

1000

~E::I::::

100

K. f\vs~'~V k~.,;=

Q

"inz

Vs = '5V

VS=:tSV Rl

'"

VS=:tlSV

0.5

198 ns

Rr

10000

128

II

64

Fo, 6 db Peakln

::;:::::::::::;::

3.0

3.5

& Rs (kll)

60
50

16

40

~
';l
~,{

100

Vs = <15V

'-I

S
,.\'

1.0

1.5

2.0

20

1.0

I\. = ISDn
2.5

30
2

10

0.5
0.25

L

10
0.5

,,=

VS,= ~S~
~50n
VS =.5V!'t. =00
Vs -'5V I\.

-00'1=

~

3.0

-10

0.125
0.3

3.5

10

100

1k

FREQUENCY (MHz)

70

I I
2.5

70_111

11111
III

32

2.0

PSRR(Vs+)vs
Frequency, Ay = 2,
Rt = Rs = 8200

Output Impedance vs Frequency
Ay = -1, Rl = 8200

Suggested Rt and
RsforCuAy = +2

3

1.5

TI~E (20 I'./OIV)

TIME (25 ,,/DIV)

1000

1.0

=OOE

I\. -150n

I

10

-52 ns

I\. = 15011

PSRR (VS-) vs
Frequency, Ay = 2,
Rt = Rs = 8200

100k

1N

10M

lOON

FREQUENCY (Hz)

CMRR vs Frequency
Rt = Rs = 8200

=+mimi

10k

Input Voltage NOise
vs Frequency
100".

60

~

50

:5
w

30
40.
20

~

10

li'"

-10
lk

10k

1~

lOOk

lOW

100~

lk

FREQUENCY (Hz)

IN

ION

1
10

100W

VS=t1SV

1\

INVERTING INPUT

~

I

I

NON-INVERTING INPUT
1
10

1111111111111111111
100

lk

10k

FREQUENCY (Hz)

lOOk

~

1000

lk

10k

lOOk

Slew Rate vs Supply Voltage
Ay = -1, RL = 1500
10000

:!'SIllV' se'r rAj'
10

100

FREQUENCY (Hz)

10000

~
!jj
!z

lOOk

Slew Rate va Temperature
Ay = -1,Rl = 1500

100

:;:

10k

FREQUENCY (Hz)

Input Current Noise
vs Frequency

'"
.!

10

NEGA~~~ :~:: RATE I Vs=:l:SV

.

'"

POSITIVE~

~
~

1000

NEGATIVE SLEW RATE

POSITIVE SLEW RATE

vs=:tsv

.rrn i'I"I'tI' I

100
-60-40-20 {) 20 40 60 80100120
TEWPERATURE (OC)

100
4

10

12

14

16

SUPPLY VOLTAGE (tV)

TLlH/11926-16

2-304

Typical Performance Characteristics
Distortion vs Frequency
Vs = ±15V,Av = +2,
RL = 150.0, Vo = 2Vp·p
-20
-30

0.-

~

1111
1111

1111
1111

1111

1111

-30

0.~

1111
1111

111111
111111

1111

111111

-50

<5

-60

:;;

0

-80
0.1

10

Distortion vs Frequency
Vs = ±5V,Ay = -1,
RL = 150.0, Vo = 2Vp·p

Crosstalk Rejection vs
Frequency

1111

120

111111

2nd HARMONIC

-40

g

IIIIf
IJ/I
1/11'

-50

1111

~

-60

<5

10
FREQUENCY (MHz)

-30
m
~

0.1

0.~

z

0

~

3rd HARMONIC

80

til
~

60

'" 1=

~

~

-80
10

100

25

10

100

I- Vs = ~';'sv

.....

20

10

r- Vs

.'10

- 3 dB Bandwidth
vs Temperature, Ay =

= :t5V

111111111
111111111

o

"

0.1

100

10

100

FREQUENCY (MHz)

Small Signal Pulse Response
vs Temperature, Ay = -1,
Vs = ± 15V, RL = 1 k.o

+2
10

100 r=c:rrrrrrrrnrnrnrn..,
120

Vs =., 5V '" = I kll

f!i{.l
~III

1
3
~

11111
0.1

FREQUENCY (MHz)

- 3 dB Bandwidth
vs Temperature, Ay = -1

11111

IIUII

15

0.1

FREQUENCY (~Hz)

11111

IIIIL

Maximum Output Voltage
Swing vs Frequency
(THD,;; 1%)

20
0.1

3rd HARWONIC

-60

FREQUENCY (MHz)

111m!

40

l'l

'/

11111
2nd HARMONIC

-80

~111'I!Il

~

-70

-50

100

II~s ~ ~~~
Av = +2

11111111
100 RL 1=1,1 ~~II I-

11111
11111

-70

1111
1111

FREQUENCY (~Hz)

-20

iii

0

3rd HARMONIC

111111
111111

-80
100

-40

<5

-70

1111

!z
:;;

-60

3rd HARMONIC

Distortion vs Frequency
Vs = ±5V,Ay = +2,
RL = 150.0, Vo = 2Vp·p
-30

'/

-50

~
~

-70

D

-20

2,d HAR~ONIC /

-40

z

z

0

iii

= ±15VandTA = 25 C unless otherwise noted.

Distortion vs Frequency
Vs = ±15V,Ay = -1,
RL = 150.0, Vo = 2Vp·p
-20

2nd HARMONIC

-40

(Continued) Vs

v =±!5V ~ ~ IJoi;j

60HrHrHrHr.~~~~~~

lil'ITi'

~

PROPAGATION OE';!:!

4~sl=I.~J '" =1 kll

~ 40~~~~~~~~~

IAll TIME

60
Vs = '5V ~ = 150n

20LLLLLLLLLULULULU~

-60 --40 -20 0

40
-60 -40 -20 0 20 4-0 80 80 100 120

20 -40 60 80 100 120

TEMPERATURE (DC)

10

RISE

]
w

"<=

TIM~ttttt

-60 -40 -20 0 20 40 60 80 100120
TEMPERATURE (OC)

Small Signal Pulse Response
vs Temperature, Ay = + 2,
Vs = ±15V,RL = 150.0
10

!ltp~ ~PA~GA~TI~ON~D~[l~AYil~ ~
RISE TIlliE

3

3

TEMPERATURE (Oc)

Small Signal Pulse Response
vs Temperature, Ay = + 2,
Vs = ±15V,RL = 1 k.o

10

FALL TIME

3
-60-40 -20 0 20 40 60 80100120

TEMPERATURE (oc)

Small Signal Pulse Response
vs Temperature, Ay = -1,
Vs = ± 15V, RL = 150.0

p~OnGtll~

RISE TIME

rAlL TIME

-60 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (Oc)

RISE TIME

3
-60-40 -20 0 20 -40 60 80100120
TEWPERATURE (Oc)

TL/HI11926-17

2-305

. _-Typical Performance Characteristics

Settling Time vs
Output Step, RF = 8200
RL = 1500,Av = -1

Settling Time vs
Output Step, ~F = 8200
RL = 1500,Av "= -1
Vs = :t5V

.,

(Continuedi Vs = ±15VandTA = 25DCunlessotherwisenoted.

f-+

Vs = :t15V

1%1/

10

H-

Vs = ±15V

Rr = 820n

9

0.1%

0.1%

/'

Small Signal Pulse Response
vs CI~-Loop Gain
RL = 1k

8

VOUT - i100mY
11,11111

1%

PROPAGATION DELAY

1%

-1

....

0.1%

0.1%

f - - 1%

I

-2
-3

-6

W

W

~

~

~

2

W

~

W

~

TIME (ns)

~

~

~

1

10

TINE (ns)

Small Signal Pulse Response
vs Closed-Loop Gain
RL = 1500

15

Small Signal Pulse Response
vs Supply Voltage
Av = +2,RL = 1k

Vos vs Temperature

12

0.0
-0.5

10

-1.0
-1.5
PROPAGATION DELAY

..

'>
E

~

""H+

;:

20

CLOSED-LOOP GAIN

-2.0
-2.5

>'lj-3.0

RISE TINE

-3.5

fALL TIME

-4.0

vs J=I. 5

-- -

I-

s ....

V =,.,15V

-4.5

o
10

15

o

20

'5

Zt vs Temperature
1\,1=

±l0

-5.0
-55 -35 -15 5

±l5

SUPPLY VOLTAGE (V)

CLOSED-LOOP GAIN

Zt vs Temperature

I. vs Temperature
15

1\,1= l~a

l~oa

14

N

2

,"
vs=*:y ~ ......

....

1~

1

=o

vrr

p

'"'"

-55 -35 -15 5

25 45 65 85 105 125

r-

.... i--" t:: ~=:t5Y

o
-55 -35 -15 5

TENPERATURE (DC)

PSRR vs Temperature

25 45 65 65 105 125

TEMPERATURE (DC)

25

~

-

~

/
13

_IA

12

..s

1

.-

vJ1v

.-

Vs =:tSV

I

10
-55 -35 -15 5

65 85 105 125

-

r- r--I--.

r-

25 45 65 85 105 125

TEMPERATURE (DC)

TEMPERATURE (DC)

CMRR vs Temperature

Ib (+ ). vs Temperature

68
66

58

5

25

~

65 85 105 125

TENPERATURE (DC)

..;.. vsl±1lsv

, " ......,
...... r--.,
vrT r--- r--:'.... "

56
-55 -35 -15 5

~

.3

:£

'"
r--

Vs
-1

-2
-3

~~

~s=il~r-

TEMPERATURE (DC)

--

. I
I

-4

-5
25 45 65 85 105125

=:l:5V

-55 -35 -15 5

25 45 65 85 105 125

TEMPERATURE (DC)

TUH/I1926-18

2-306

I......

Typical Performance Characteristics
Vs = ±15V and TA = 25°C unless otherwise noted. (Continued)

Ib (-) VB Temperature

C»
N

Ib (+ ) PSR VB Temperature

10

Ib ( -) PSR VB Temperature

0.5

0.5

0.4

v..
/,

<"

.3

,

.,

0
-2
-4
-6
-8

- -

".....

f-Vs =tI5V

-

~V!

~

S
.3

0.3

+

0.2

.,

f-

0.'

S'

~ 0.3

.3

,

0.1

1

1
1
-10
-55 -35 -15 5 25 45 85 85 105125

v~

o

.,

-

Vs = ::I:SV

TEWPERATURE (Oe)

Ib (-) CMR VB Temperature

Isc! ±) VB Temperature
150

~

11
+

0.2

O. 1

o

140

0.5

$

~"

'"

-55 -35-15 5

,

N

0.2

i" .....

.$>

0.1

VSitrv

vSi

o

tr

.5

TEMPERATURE (Oe)

_:.:l

\

V

-55 -35 -15 5

25 -'5' 65 85 105125

r--- .......

1'...
IVs =:t:5V

90

25 45 '35 85 IDS 125'

50
-55 -35 -15 5

TEMPERATURE (Oe)

~

f- Vs =:l:5V
-1

12

1 1
1 1

-5
-55 -35 -15 5

= '""'

f- Vs=:t:1SV
~

-3
-6

... = IsDn f---c

-9

... = 1 kn

-4

25 45 65 85 105 125

... = 1 kll
... = IsDn

0

-3

"

Output Swing VB Temperature
15

... = 15011

-2

""

TEMPERATURE (Oe)

... " 15011

go

"

70
60

I-":"

1 1 1
I'" =1 kll

I

100

V~=+5J

80

Output Swl!lg VB Temperature

:

1

~

120
-:;;; 110

\.

0.3

11

i'- I""- .......

130

i\

0.4

.3
~

'Vs =::I:15V

TEWPERATURE (Oe)

Vs = :t:5V

0.3

r- t- 4:lV . . . .V

o

O.S

0.4

-

-55 -35 -15 5 25 45 65 85 105125

Ib (+ ) CMR VB Temperature
0.5

r--..

0.1

-55 -35 -15 5 25 45 85 85 105 125

TEWPERATURE (oe)

S
..3

0.2

-12

L 1

-15
-55 -35 -15 5

25 45 65 85 105125

TEMPERATURE (Oe)

... = 1 kn

-

25 45 65 85 105125

TEWPERATURE (Oe)

TLlH/11926-19

2-307

•

~

....
CD

co

:i

.---------------------------------------------------------------------------------,
Typical Applications
CURRENT FEEDBACK TOPOLOGY
For a conventional voltage feedback amplifier the resulting
small-signal bandwidth is inversely proportional to the desired gain to a first order approximation based on the gainbandwidth concept. In contrast, the current feedback amplifier topology, such as the LM6182, transcends this limitation
to offer a signal bandwidth that is relatively independent of
the closed loop gain. Figures 1A and 18 illustrate that ·for
closed loop gains of -1 and - 5 the resulting pulse fidelity
suggests quite similiar bandwidths for both configurations.

>-~~-VOUT

TLlH/11926-22

FIGURE 2. Rt Sets Amplifier Bandwlclth and Rs is
Adjusted to Obtain the Desired Closed-Loop Gain, Ay,
Although this RI value will provide good results for most
applications, it may be advantageous to adjust this value
slightly. Consider, for instance, the effect on pulse responses with two different configurations where both the closedloop gains are + 2 and the feedback resistors are 820.0,
and 1640.0, respectively. Figures 3A and 38 illustrate the
effect of increasing RI while maintaining the same closedloop gain - the amplifier bandwidth decreases. Accordingly,
larger feedback resistors can be used to slow down the
LM6182 and reduce overshoot in the time domain response. Conversely, smaller feedback resistance values
than 820.0 can be used to compensate for the reduction of
bandwidth at high closed-loop gains, due to 2nd order effects. For example Figures 4A and 48 illustrate reducing RI
to 500.0 to establish the desired small signal response in an
amplifier configured for a closed-loop gain of + 25.

YOUT
(0.1V/DIV)

TIME (5nstDIV)
TLlH/11926-20

1A.Ay = -1

YOUT
(0.5V/DIV)
YOUT
(O.1V/DIV)

YIN
(0.5V/DIV)
TIME (5ns/D1V)

TIME (20nS/DIV)
TL/H/11926-21
TL/H/11926-23

1B.Ay = -5

3A. Rt = 820.0

FIGURE 1A, 1B. Variation of Closecl-Loop Gain from -1
to - 5 Yields Similar Responses.
FEEDBACK RESISTOR SELECTION: Rt
Selecting the feedback resistor, RI, is a dominant factor in
compensating the LM6182. For general applications the
LM6182 will maintain specified performance with an 820.0
feedback resistor. The closed-loop bandwidth of the
LM6182 depends on the feedback resistance, RI. Therefore, Rs, and not RI, is varied to adjust for the desired
closed-loop gain as demonstrated in Figure 2.

VOUT
(0.5Y/DIV)

YIN
(O.5V/DIV)
TIME (20ns/DIV)
TLlH/11926-24

3B. Rt = 1640.0
FIGURE 3A, 3B. Increase Compensation by Increasing
Rt,Ay = +2
2-308

Typical Applications

(Continued)
is specified for a feedback resistance of 820fl. Decreasing
the feedback impedance below 8200 extends the amplifier's bandwidth leading to possible instability. Capacitive
feedback should therefore not be used because the impedance of a capacitor decreases with increasing frequency.

Vour

(0.5V/DIV)

VIN
(50mV/DIV)
TIME (2ns/DlV)
TUH/11926-25

4A.Rf = 8200

TL/H/11926-28

FIGURE 6. Current Feedback Amplifiers are Unstable
with Capacitive Feedback
For voltage feedback amplifiers it is quite common to place
a small lead compensation capacitor in parallel with feedback resistance, Rt. This compensation serves to reduce
the amplifier's peaking. One application of the lead compensation capacitor is to counteract the effects of stray capacitance from the inverting input to ground in circuit board layouts. The LM6182 current feedback amplifier does not require this lead compensation capacitor and has an even
simpler, more elegant solution.
To limit the bandwidth and peaking of the LM6182 current
feedback amplifier" do not use a capacitor across Rt as in
Figure 7. This actually has the opposite effect and extends
the bandwidth of the amplifier leading to possible instability.
Instead, simply increase the value of the feedback resistor
as shown in Figure 3.

VOUT
(0.5V/DIV)

VIN
(50mV/DIV)
TIME (2ns/DIV)
TUH/I1926-26

4B. Rf = 5000
FIGURE 4A, 4B. Reducing Rf to Increase Bandwidth for
Large Closed-Loop Gains, Ay = + 25
The extent of the amplifier's dependence on Rt is displayed
in Figure 5 for one particular closed-loop gain.

Non-inverting applications can also reduce peaking and limit
bandwidth by adding an RC circuit as illustrated in Figure 8.

120.0

II

""N'100.0

\

:<:

~ 80.0
:<:

~ 60.0

-

1

~

\

z
:: 40.0

.,..,

11 _

Js J:tJv ~ ~ 1 ~Il -

~'\: .1 I
~~

20.0
0.0

I
:11 kill

15
~vVsl:t151 ~: 1

::;

I

VSi:t1151"

~s::t5V

0.5

1.0

1It.: 15011
1.5

Rr

2.0

2.5

3.0

3.5

&: Rs (kill
TLlH/11926-27

FIGURE 5. -3 dB Bandwidth Is Determined By
Selecting Rf.
CAPACITIVE FEEDBACK
Current feedback amplifiers rely on feedback impedance for
proper compensation. Even in unity gain current feedback
amplifiers require a feedback resistor. LM6182 performance

TL/H/I1926-29

FIGURE 7. Compensation Capacitors Are Not Used with
the LM6182, Instead Simply Increase Rf to Compensate

2-309'

~

r------------------------------------------------------------------------------------------,

=
~
CD

Typical Applications (Continued)
pensation capacitor. The current feedback amplifier is
therefore not traditionally slew rate limited. This enables
large s'~wJ'ate& responses of 2000 V / p.S. The non-inverting
configuration slew rate is also determined by input stage
limitations. Accordingly, variations 01 slew rates occur for
different circuiHppologfes.

+15V' ,
IOl'f

~
'::"

O.ll'f

1.-

DRIVING CAPACITIVE LOADS
The LM6182 can drive significantly larger capacitive loads
than many current feedback, amplifiers. This is extremely
valuable for simplifying the design of coax-cable drivers. Although the LM6182 can directly drive as much as 100 pF of
load capacitancs\vithout oscUlating, the reS!Jlting response
will be a function of the feedback resistor value. Figure 98
illustrates the small-signal pulse response of the LM6182
while driving a 50 pF load. Ringing perSists for approximately 100 ns. To achieve pulse responses with less ringing either the feedback resistor can be increased (see Typical
Performance Characteristics "Suggested Rt and Rs for
CL"), or resistive isolation can be used (100-510 typically
works well). Either technique, however, results in lowering
the system bandwidth.
Figure ,108 illustrates the improvement obtained by using a
470 isolation resistor.

>----1- VOUT

-15V

820n

82an

TUH/11926-30

S~

820n
+15V

82an

VOUT
(0.5V/DIV)

>----.....- VOUT

son
~15V

V,N

TUH/11926-32

(O.5V/DIV)

9A
TIME (20ns/DIV)
TL/H/11926-31

SB
FIGURE SA, SB. RC Limits Amplifier Bandwidth to 50
MHz, Eliminating Peaking In the Resulting Pulse
Response as Compared to Figure3A

VOUT
(0.2V/DIV)

Y,N

SLEW RATE CONSIDERATIONS
The slew rate characteristics of current feedback amplifiers
are different than traditional voltage feedback amplifiers. In
voltage feedback amplifiers, slew rate limiting or non-linear
amplifier behavior is dominated by the finite availability of
the 1st stage tail current'charging the compensation capacitor. The slew rate of current feedback amplifiers, in contrast,
is not constant. Transient current at the inverting input is
proportional to the current available to the amplifier's com-

(0.2V/D1V)

TIME (20ns/DIV)
TUH/11926-33

9B
FIGURE 9A, 9B. AV = -1, LM61S2 Can Directly Drive
50' pF of Load CapaCitance with 100 ns of Ringing
Resulting In Pulse Response

2-310

r-----------------------------------------------------------------------------'r
i:
en
Typical Applications (Continued)
....
nal power dissipation can be minimized by operating at reQ)

820n

duced power supply voltages, such as ± 5V.
Optimum heat dissipation is achieved by using wide circuit
board traces and soldering the part directly onto the board.
Large power supply and ground planes will improve power
dissipation. Safe Operating Area (S.O.A.) is determined using the Maximum Power Derating Curves.
The 16-pin small outline package (M) has 5 V - heat sinking
pins that enable a junction-ta-ambient thermal resistance of
70'C/W when soldered to 2 in2 1 oz. copper trace. A Vheat sinking pin is located on each corner of the package
for ease of layout. This allows high output power and/or
operation at elevated ambient temperatures without the additional cost of an integrated circuit heat sink. If the heat
sinking capabilities of the S.O. package are not needed, pin
4 and at least one of pins 1,8,9, or 16 must be connected to
V - for proper operation.

+15V

820n
47n

>--+....J

-3

100

z
2
....

80

...........'"

'"

60

0

40

~
;;J

111111

= ±ISV
= +2

Vs
Av

1\ = \ ~~I

~IIIIII

~

1\1=1~

"

+sv

.....

I/)
I/)

u
'"

. VIN -

"

1 kn

20
0.1

10

.....---...;.;..-1

, son
250n

100

-SV

FREQUENCY (IotHz)
TL/H/11926-38
TL/H/11926-41

FIGURE 12. Crosstalk Rejection
The LM6182 crosstalk effect is minimized in applications
that cascade the amplifiers by preceding amplifier A with
amplifier B.

GND

START-UP TIME
Using the circuit in Figure 13, the LM6182 demonstrated a
start-up time of 50 ns.

v+

= ±5V

>---'-Vo
TIME (SOns/OIV)

820n

TLlH/11926-42

FIGURE 14. Open Loop Overdrive Recovery Times of
5 nsand 30ns
The large closed-loop gain configuration in Figure 15forces
the amplifier output into overdrive. The typical recovery time
to a linear output value is 15 ns.

0.1 ",F

t

10 ",F

t

-5V

= yTL/H/11926-39

FIGURE 13. Start-Up Test Circuit

2-312

Typical Applications (Continued)
+15V

SPICE MACROMODEL

V,N-.....- - - i

>---1p--.....-

A spice macromodel is available for the LM6182. Contact
your local National Semiconductor sales office to obtain an
operational amplifier spice model library disk.

Your

50n
lS0n

Typical Application Circuits
UNITY GAIN AMPLIFIER
The LM6182 current feedback amplifier is unity gain stable.
The feedback resistor, Rt, is required to maintain the
LM6182's dynamic performance.

50n

TL/H/11926-43

>--"'-VOUT
TLlH/11926-47

FIGURE 17. LM6182Is Unity Gain Stable
NON-INVERTING GAIN AMPLIFIER
Current feedback amplifiers can be used in non-inverting
gain and level shifting functions. The same basic closedloop gain equation used for voltage feedback amplifiers applies to current feedback amplifiers: 1 + Rt/Rs.

TL/H/11926-44

>--"'-VOUT

FIGURE 15. 15 ns Closed Loop Output Overdrive
Recovery Time Generated by Saturating the Output
Stage of the LM6182
The common-mode input range of a unity-gain circuit is exceeded by a 4V pulse resulting in a typical recovery time of
20 ns shown in Figure 16.

TLlH/11926-46

FIGURE 18. Non-Inverting Closed Loop Gain Is
Determined with the Same Equation Voltage Feedback
Amplifiers Use: 1 + Rf/Rs

+5V

V,N-.....- - - t

INVERTING GAIN AMPLIFIER
The inverting closed loop gain equation used with voltage
feedback amplifiers also applies to current feedback amplifiers.

>--,-Vour

50n
-5V

a20n

>--"'-VOUT

TL/H/11926-45

TL/H/11926-49

VOUT
(2V/DIV)

FIGURE 19. Current Feedback Amplifiers Can Be Used
for Inverting Gains, Just Like a Voltage Feedback
Amplifier: - Rf/Rs

GND

Y,N
(2V/DIV)

GND
TIME (20ns/DIV)
TL/H/11926-46

FIGURE 16. Output Recovery from an Input that
Exceeds the Common-Mode Range

2-313

II

C'I

co

~

:i

Typical Application Circuits (Continued)

Ordering Information

SUMMING AMPLIFIER
The current feedback topology of the LM6182 provides significant performance advantages over a conventional voltage feedback amplifier used in a standard summing circuit.
Using a voltage feedback amplifier, the bandwidth of the
summing circuit in Figure 20 is limited by the highest gain
needed for either signal V1 or V2. If the LM6182 amplifier is
used instead, wide circuit bandwidth can be maintained relatively independent of gain requirements.

Military
-55'C to + 125'C
8-pin
Molded
DIP

...

VI
RSI
V2

Temperature Range
Package

,y

RS2

1

16-pin
Small
Outline

Rr
KLM6182

LM6182AMN

Industrial
-40'Cto
+ 85'C

NSC
Drawing

LM6182AIN
LM61821N

N08E

LM6182AIM
LM61821M

M16A

If Military/Aerospace specified devices are required. contact the National
Semiconductor Sal,!,s Office or Distributors for availability and specifications.

>--.....- VOUT

~v

TL/H/11926-50

FIGURE 20. LM6182 Allows the Summing Circuit to Meet
the Requirements of Wide Bandwidth Systems
Independent of Signal Gain

2-314

r-

iii:

.....
....

t{lNational Semiconductor

....Co:!

LM7131
Tiny High Speed Single Supply Operational Amplifier
General Description

Features

The LM7131 is a high speed bipolar operational amplifier
available in a tiny SOT23-5 package. This makes the
LM7131 ideal for space and weight critical designs. Single
supply voltages of 3V and 5V provides good video performance, wide bandwidth, low distortion, and high PSRR and
CMRR. This makes the amplifier an excellent choice for
desktop and portable video and computing applications.
The amplifier is supplied in DIPs, surface mount 8-pin packages, and tiny SOT23-5 packages.
Tiny amplifiers are so small they can be placed anywhere on
a board close to the signal source or next to an A-to-D input.
Good high speed performance at low voltage makes the
LM7131 a preferred part for battery powered designs.

• Tiny SOT23-5 package saves space-typical circuit layouts take half the space of SO-8 designs.
• Guaranteed specs at 3V, 5V, and ±5V supplies
• Typical supply current 7.0 mA at 5V, 6.5 mA at 3V
• 4V output swing with + 5V single supply
• Typical total harmonic distortion of 0.1 % at 4 MHz
• 70 MHz Gain-Bandwidth Product
• 90 MHz -3 dB bandwidth at 3V and 5V, Gain = +1
• Designed to drive popular video AID converters
• 40 mA output can drive 500. loads
• Differential gain and phase 0.25% and 0.75' at Av =
+2

Applications
•
•
•
•
•

Driving video AID converters
Video output for portable computers and PDAs
Desktop teleconferencing
High fidelity digital audio
Video cards

Connection Diagrams
S-Pln DIP/80-S
NC
INVERTING INPUT

.!.
L

NON-INVERTING ~
INPUT
4

v- -'-

'--"

~

5-Pin SOT23-5

'"""'w··

.!NC

~y+

v-

.i OUTPUT

2

NON-INVERTING 3
INPUT

.iNC

+ -

4 INVERTING
INPUT

TUH/12313-1

TL/H/12313-2

Top View

Package

Ordering
Information

Top View
NSCDrawlng
Number

Package
Marking

Supplied as

8-Pin DIP

LM7131ACN

NO~E

LM7131ACN

8-Pin DIP

LM7131BCN

N08E

LM7131BCN

rails

8-PinSO-8

LM7131ACM

M08A

LM7131ACM

rails

8-PinSO-8

LM7131BCM

M08A

LM7131BCM

rails

8-PinSO-8

LM7131ACMX

M08A

LM7131ACM

2.5k units tape and reel

rails

8-PinSO-8

LM7131BCMX

M08A

LM7131BCM

2.5k units tape and reel

5-Pin SOT 23-5

LM7131ACM5

MA05A

A02A

250 units on tape and reel

5-Pin SOT 23-5

LM7131 BCM5

MA05A

A02B

250 units on tape and reel

5-Pin SOT 23-5

LM7131ACM5X

MA05A

A02A

3k units tape and reel

5-Pin SOT 23-5

LM7131 BCM5X

MA05A

A02B

3k units tape and reel

2-315

PI

Absolute Maximum Ratings (Note 1)
Lead Temperature (soldering, 10 sec)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
2000V
ESD Tolerance (Note 2)
±2.0
Differential Input Voltage
(V+)+0.1V, (V-) ...: 0.3V
Voltage at Input/Output Pin
Supply Voltage (V+ - V-)

Storage Temperature Range
Junction Temperature (Note 4)

Operating Ratings
Junc1ion Temperature Range
LM7131AC, LM7131BC

±5mA

Current at Ou1put Pin (Note 3)

±80mA

Current at Power Supply Pin

±80mA

150'C

2.7V

Supply Voltage (V+ - V-)

12V

Current at Input Pin

260'C
- 65'C to + 150'C

O'C ,;;. TJ ,;;. + 70'C

Thermal Resistance (6JN
N Package, 8·Pin Molded DIP

115'C/W

SO-8 Package, 8-Pin Surface Mount

165'C/W

M05A Package, 5-Pin Surface Mount

325'C/W

3V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ =
3V, V- = OV, VCM

= Vo = V+ 12 and RL = 1500. Boldface limits apply atthe temperature extremes.

Symbol

Parameter

Vos

Input Offset Voltage
Average Drift

18

Input Bias Current

los
CMRR
CMRR
+PSRR
-PSRR

VCM

Typ
(Note 5)

Conditions

Input Offset Voltage

TCVos

0.02

20

Input Offset Current

0.35

Common Mode
Rejection Ratio·

OV ,;;. VCM ,;;. 0.85V
(Video Levels)

75

Common Mode
Rejection Ratio

0.85V';;' VCM ,;;. 1.7V
(Mid-Range)

70

Positive Power Supply
Rejection Ratio

V+
V+

Negative Power Supply
Rejection Ratio

VV-

Input Common-Made
Voltage Range

V+
For CMRR ;" 50 dB

CIN

Voltage Gain

LM7131AC
Limit
(Note 6)

25'C, V+

LM7131BC
Limit
(Note 6)

2

7

4

10

10

= 3V, V- = OV
= 3Vt06.5V
= -3V, V+ = OV
= -3Vto -6.5V
= 3V

RL = 1500, Vo
to 1.250V

= 0.250V

Common-Mode
Input Capacitance

30

40

3.5

3.5

5

5

60

60

55

55

55

55

50

50

65

65

eo

75

65

65

eo

80

60
2

2-316

30

40

eo

0.0

=

Units
mV
max
",VI'C

75

2.0
AVOL

,;;,.V ';;'12V

0.0

0.0

0.00

0.00

1.70

1.70

1.80

1.80

55

55

50

50

",A
max
",A
max
dB
min
dB
min
dB
min
dB
min
V
min
V
max
dB
pF

3V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ =
3V, V-

=

OV, VCM = Vo = V+ 12 and RL

Symbol

Vo

=

Parameter

1500. Boldface limits apply at the temperature extremes. (Continued)

Typ
(Note 5)

Conditions

Output Swing
High

V+ = 3V, RL = 1500
terminated at OV

2.6

Low

V+ = 3V, RL = 1500
terminated at OV

0.05

V+ = 3V, RL = 1500
terminated at 1.5V

2.6

V+ = 3V, RL = 1500
terminated at 1.5V

0.5

High
Low

LM7131AC
Limit
(Note 6)

LM7131BC
Limit
(Note 6)

2.3

2.3

2.0

2.0

0.15

0.15

0.20

0.20

2.3

2.3

2.0

2.0

0.8

0.8

1.0

1.0

Units
V
min
V
max
V
min
V
max

Vo

Output Swing
High

V+ = 3V, RL = 6000
terminated at OV

2.73

V
max

Vo

Output Swing
Low

V+ = 3V, RL = 6000
terminated at OV

0.06

V
max

Isc

Output Short Circuit
Current

Sourcing, Vo
Sinking, Vo

Is

Supply Current

V+

=

=

OV

65

3V

40

= + 3V

6.5

45

45

40

40

25

25

20

20

8.0

8.0

8.5

8.5

3V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+
3V, V-

=

OV, VCM

=

Vo

=

V+ 12 and RL

=

rnA
min
rnA
min
rnA
max

=

1500. Boldface limits apply at the temperature extremes.

LM7131AC
Umlt
(Note B)

LM7131BC
Umit
(Note 6)

Parameter

Conditions

Typ
(Note 5)

Total Harmonic Distortion

F = 4 MHz, Av = + 2
RL = 1500, Vo = 1.0Vpp

0.1

%

Differential Gain

(Note 10)

0.45

%

Differential Phase

(Note 10)

0.6

SR

Slew Rate

RL = 1500, CL
(Note 7)

=

5 pF

SR

Slew Rate

RL = 1500, CL
(Note 7)

=

20 pF

Symbol
T.H.D.

GBW

120

Units

°

V//J-S

100

V/p.s

Gain-Bandwidth Product

70

MHz

Closed-Loop - 3 dB
Bandwidth

90

MHz

2-317

•

5V

Electrical Characteristics

DC
Unless otherwise spesified, all limits guaranteed for TJ = 25°C, V+ =.
5V, V- = OV. VCM'= Vo = V+ /2 and RL = 1500. Boldface limits apply at the temperature extremes.
Symbol

Vos

Parameter

Input Offset Voltage
Average Drift

18

Input Bias Current

CMRR
CMRR
+ PSRR
-,PSRR

VCM

(Note 5)

Input Offset Voltage

TCVos

los

Typ

Conditions

0.02

20

Input Offset Current

0.35

Common Mode
Rejection Ratio

OV ~ VCM ~ 1.85V
(Video Levels)

75

Common Mode
Rejection Ratio

1.85V ~VCM ,;; 3.7V
(Mid-Range)

70

Positive Power Supply
Rejection Ratio

V+ = 5V, V- = OV
V+ = 5Vto 10V

75

Negative Power Supply
Rejection Ratio

V- = - 5V, V+ = OV
V- = - 5Vto -10V

75

Input Common-Mode
Voltage Range

V+ = 5V
For CMRR ~ 50 dB

0.0

Voltage Gain

RL = 1500. Vo ,;.
0.250V to 2.250V

70

,

CIN

Common-Mode
Input Capacitance

Vo

Output Swing
High

V+ = 5V, RL = 1500
terminated at OV

4.5

Low

V+ = 5V, RL = 1500
terminated at OV

0.08

V+ = 5V, RL = 1500
terminated at 2.5V

4.5

V+ = 5V, RL = 1500
terminated at 2.5V

0.5

High
Low

LM7131BC
Limit
(Note 6)

2

7

4

10

10

4.0
AVOL

LM7131AC
Limit
(Note 6)

Units
mV
max
/LVrC

30

30

40

40

3.5

3.5

5

5

65

65

60

60

55

55

50

50

65

65

60

60

65

65

60

60

- 0.0

- 0.0

0.00

0.00

3.70

3.70

3.60

3.60

60

60

55

55

/LA
max
p.A
max
dB
min
dB
min
dB
min
dB
min
V
min
V
max
dB
min
pF

2
4.3

4.3

4.0

4.0

0.15

0.15

0.20

0.20

4.3

4.3

4.0

4.0

0.8

0.8

1.0

1.0

V
min
V
max
V
min
V
max

Vo

Output Swing
High

V+ = 5V, RL = 6000
terminated at OV

4.70

V
max

Va'

Ouptut Swing
Low

V+ = 5V, RL = 6000
terminated at OV

0.07

V
max

Isc

Output Short Circuit
Current

Sourcing, Vo = OV
Sinking, Vo = 5V

Is

Supply Current

V+ = +5V

65
40
7.0

2-318

45

45

40

40

25

25

20

20

8.5

8.5

9.0

9.0

mA
min
mA
min
mA
max

5V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ =
5V, V- = OV, VCM = Va = V+ 12 and RL = 1500. Boldface limits apply atthe temperature extremes.
Symbol
T.H.D.

LM7131AC
Limit
(Note 6)

LM7131BC
Limit
(Note 6)

Parameter

Conditions

Typ
(Note 5)

Total Harmonic Distortion

F = 4MHz,Av = +2
RL = 1500, Va = 2.0Vpp

0.1

%

Differential Gain

(Note 10)

0.25

%

Units

Differential Phase

(Note 10)

0.75

°

SR

Slew Rate

RL = 1500, CL = 5 pF
(Note 8)

150

V/p.s

SR

Slew Rate

RL = 1500, CL = 20 pF
(Note 8)

130

V/p.s

GBW

Gain-Bandwidth Product

70

MHz

Closed-Loop - 3 dB
Bandwidth

90

MHz

11

nV
--

en

Input-Referred
Voltage Noise

f = 1 kHz

in

Input-Referred
Current Noise

f = 1 kHz

viHz
pA

3.3

viHz

± 5V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ =

25°C, V+

= 5V, V- = 5V, VCM = Va = OV and RL = 1500. Boldface limits apply at the temperature extremes.

Symbol

Vas

Parameter
Input Offset Voltage

TCVos

Input Offset Voltage
Average Drift

18

Input Bias Current

los
CMRR
+PSRR
-PSRR
VCM

Typ
(Note 5)

Conditions

0.02

20

Input Offset Current

0.35

Common Mode
Rejection Ratio

-5V,;; VCM ,;; 3.7V

Positive Power Supply
Rejection Ratio

V+ = 5V, V- = OV
V+ = 5Vto 10V

75

Negative Power Supply
Rejection Ratio

V- = -5V, V+ = OV
V- = -5Vto -10V

75

Input Common-Mode
Voltage Range

V+ = 5V, V- = -5V
For CMRR ~ 60 dB

-5.0

Voltage Gain

LM7131BC
Limit
(Note 6)

2

7

4

10

75

RL = 1500,
Va = -2.0 to +2.0

2-319

70

Units
mV
max
p.VloC

10

4.0
AVOL

LM7131AC
Limit
(Note 6)

30

30

40

40

3.5

3.5

15

15

65

65

80

80

65

65

80

80

65

65

80

80

-5.0

-5.0

-15.0

-15.0

3.70

3.70

3.80

3.80

55

55
SO

so

p.A
max
p.A
max
dB
min
dB
min
dB
min
V
min
V
max
dB

fII

± 5V DC Electrical Characteristics

Unlessotherwisespecified,alllimits.guaranteedforTJ = 25°C, V+
= 5V, V- = 5V, VCM = Vo = OV and RL = 1500. Boldface limits apply at the temperature extremes. (Continued)·

Symbol

Parameter

CIN

Common-Mode
Input Capacitance

Vo

Output Swing
High
Low

Isc

Typ
(Note 5)

Conditions

V+ = 5V, V- = -5V
RL = 1500
terminated at OV

Sourcing, Vo = -5V
Sinking, Vo = 5V

Is

Supply Current

LM7131BC
Limit
(Note 6)

2
4.5

65
40

V+ = +5V, V- = -5V

Units

pF

-4.5

Output Short Circuit
Current

LM7131AC
Limit
(Note 6)

7.5

4.3

4.3

4.0

4.0

-3.5

-3.5

-2.5

-2.5

45

45

40

40

25

25

20

20

9

9

10

10

± 5V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed forTJ =

V
min
V
max
mA
min
mA
min
mA
max

25°C, V+

= 5V, V- = 5V, VCM = Vo = OV and RL = 1500. Boldface limits apply atthe temperature extremes.

LM7131AC
Limit
(Note 6)

LM7131BC
Limit
(Note 6)

Parameter

Conditions

Typ
(Note 5)

Total Harmonic Distortion

F = 4 MHz, Av = - 2
RL = 1500, Vo = 4.0Vpp

1.5

%

Differential Gain

(Note 10)

0.25

%

Differential Phase

(Note 10)

1.0

°

SR

Slew Rate

RL = 1500, CL = 5 pF
(Note 9)

150

V/p.s

SR

Slew Rate

RL = 1500, CL = 20 pF
(Note 9)

130

V/p.s

Gain-Bandwidth Product

70

MHz

Closed-Loop -3 dB
Bandwidth

90

MHz

Symbol
T.H.D.

GBW

Units

Note 1: Absolute maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional. but specific perfonnance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical characteristics.
Note 2: Human body model, 1.5 kll in series with 100 pF.
Note 3: Applies to both single-supply and split-suppty operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150"C.

Note 4: The maximum power dissipation is a function of TJ(max), 6JA, and TA. The maximum allowable power dissipation at any ambient temperature is Po =
(TJ(msx)' TAlI8JA. All numbers apply for packages soldered directly into a PC board.
Note 5: Typical values represent the most likely parametric norm.

Note 6: All limits are guaranteed by testing or statistical analysis ..
Note 7: Connected as voltage follower with I.SV step input Number specified is the slower of the posHive and negative slew rates. V+ = 3V and RL = 15011
connected to I.SV. Amp excHed with 1 kHz to produce Vo = 1.5 Vpp.
Note 8: Connected as Voltage Follower with 4.0V step input. Number specified Is the slower of the posHive and negative slew rates. V+ = SV and RL = 1500
connected to 2.SV. Amp excited with 1 kHz to produce Vo = 4 Vpp.
Note 9: Connected as Voltage Follower with 4.0V step input. Number specified is the slower of the posHive and negative slew rates. V+ = SV, V- = -SVand
RL = 15011 connected to OV. Amp excited with 1 kHz to produce Vo = 4 Vpp.
Note 10: Differential gain and phase measured with a 4:5 MHz signal into a 15011 load, Gain = + 2.0, between 0.6V and 2.0V output.

2-320

Typical Performance Characteristics
LM7131 Supply Current vs
Supply Voltage

LM7131 Input Current vs

LM7131' Input Current vs
Temperature @ 3V

10r-~'--r~-.--r-~'-,

9~+-+-~~~-+-+-+-1

-12

t

-15

<3
;;

-18

£"

~ 150
VIN VOUT

-9

I.--

-21
-24

'1

IV

.... r-

I.-- .-

3

"

5

6

7

8

9

10

11

30
25
20
15
10

o;?

H-+-+~+-t-+-H-+-+-fI

..3

5H-+~~+-H-++-t-Hl

t

H-+~~+-H-hM-+-~

a

0
-5

.=

-10
-15

i

H-t-+++-+-t-If1-t-+---l
-15
f--i;:~~~u=t+j
-20 Ir-

"[ -10
E

0.5

-30

2.5

1.5

Vs=i'SV= 150,_

~
~

'"<.>

o

750

1I1
lH-ttttIIt-tttttlll-tttttIIII-:-'-Hl!IJII-:-!IIIIIIIIIII:':':4III

675

250

I-+ttttIIHttttllIH-tttl1IIf ~ = 5k

200

H'WIIH+HlIIH-HHHH

:ll

150

H-flNIH+HlIIH-HHHH

~

!

100

1000

~

525

g>

20
10
0
I

10

100

1000

10k

10

lOOk

100 1000 10k lOOk 1M

Idlv

LM7131 Cable Driver
Ay = +2@ +3V
2.SV

INPUT

SOOmV

~

Idlv

~E -,-

60
50

o
o

40

E

0
10M 100M

'- .....

"--

II

"'
OUTPUT

SOOmV
Idlv

10

~
0
0

OUTPUT

20

,.;

..... -1-

I

"'

30

10M 100M

Frequency (Hz)

LM7131 Cable Driver
Ay = +1 @ +3V

70

100 1000 10k lOOk 1M

40
30

5V

10

Htllll-ttIIIBHilil-fttIIJl-tttVs =+3V]
~ = 150 II
HtllHf-fttIIJHiIil-HlIIIII-ttt YOUT = 1V

Frequency (Hz)

80

10t.l

50

~
~

0

INPUT
500 mV

It.l

70

75

90

lOOk

60

150

100

8i

..
g>

LM7131 PSRR vs
Frequency @ 5V

3

80

3

Frequency (Hz)

..

90

= 5k

375

lOOk

10k

100

300

10k

1000

LM7131 PSRR vs
Frequency @ 3V

III

450

50 H-H!fIIH~IIH-HHHH
o '-UWWI'-UWWI'-U.IllIII=
10

IIIIIII~

~= 225

100 H-H!fII~+HlIIH-HHHH

I

100

Frequency (Hz)

Js1~1~12.I~J

600

Vs=:I: 1.5V

11111111

VIN = 1Vp_:pp :+HtI-flIIIIII-+HI1II

10

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

LM7131 Voltage Noise vs
Frequency @ 5V

350 rrmrn..-rTTmIlrl11T1lr'rmrmrnnmn

~
~

1IIIIm

Vs = +/-2.5Vf-HIINfHIIIH-I1IIIII

Y,N (V)

LM7131 Voltage Noise vs
Frequency @ 3V

..

110
100
90
80
70
60
50
40
30
20
10
0

~

Y,N (v)

300

LM7131 CMRR vs
Frequency @ 5V

5V

@

20406080 100120140

Case Temperature (C)

-25

LJ......L....L.LJ--L....L~L.1~

o

-40-200

-20

H++-H-+++-H-+---l

-25
-30

20 40 60 80 100 120 140

Input Voltage

=

-5

".

-2 1
-24

LM7131 Input Current vs

H-+-+~+-t-+-H-+-+~
Vs = +3V
H-+-+~+-t-+RI 150
H-+-+~+-t-+­

.....

,.

Case Temperature (C)

30 r;-'~-r-r.-~r;-'-r'

-

= IV

-30

LM7131 Input Current vs
Input Voltage @ 3V

<~.>

VIN = VOUT

= 150

-27

-40 -20 0

Supply Voltage (V)

25
20
o;? 15
..3 10

-9

-18

£"

~

~

~ -15

~

-30

12

I
Vs "'+5V

-6

......... -12

-27
OL-~~~-L-L-L~~~

5V

-3

V,=+3"+
== =

-6

@

o

I

-3

3

Temperature

ov
tfi

SOOmV

--

1..-1-

Idlv

-2.5V

r--

1-50ns/div

Frequency (Hz)

TL/H/12313-3

2-321

~

~
.....

....

r-----------------------------------------------------------------------------------------------,
Typical Performance Characteristics

(Continued)

:::&

LM1,131 Cable Driver
Ay = +10@+3V

LM7131 Driving 75'
,RG-59Ay = +2@ +3V

LM7131 Driving 5'
RG-59AV = +2@ +3V
2V

2V

,5V

INPUT
200 mY

INPUT

1~~V

/div

OV

~~

-~

CABLE
OUTPUT
200 mV
/div

......

OV .. ~-f-'

-

I

OUTPUT
500 mY

OV

di. -~

LM7131 Cable Driver
Ay = +2@ +5V

5V

LM7131 Driving 5' RG-59
Ay = +2@ +5V
2V

5V

INPUT
500mV

INPUT
500 mY
/div

/div

INPUT
200 mV
/div

.... -

.... r-~

OUTPUT

-I-

~~

50 .s/di.

'-"-

....

II

OUTPUT
500 mV

OV.r

r-

50 ns/dlv

LM7131 Cable Driver
Av = +1,@+5V

5}~i~V

\
\

/div

50 n,/div

, -~

_

.... ....

- ....

.... -1-

-~

Idiv

OV.r

'--~

~-

(g]

50 ••/dl.

LM7131 Driving 75' RG-59
Ay = +2@ +5V

CABLE
OUTPUT
200 mV
/div

OV ..

(g]

....

~

I-~

50 ••/di.

LM7131 Cable Driver
Ay = +10@ +5V

(g]

LM7131 Driving Flash
AID LoadAy = -1 @ +5V

5V

2V

~~

~I-

5V
INPUT
500mV

Idiv

'-"CABLE
OUTPUT

II

OUTPUT

2~~I~V
OV.r

-I-

....

1 ....

50.s/dl.

1-

5~~II~V
OV.r

1\
\

--

(g]

50 .s/di.

lM7131 Driving Flash
AID LoadAy = + 1 @ +5V

....

.... ~

(g]

LM7131 Driving Flash
AID LoadAy = +2@ +5V

LM7131 Driving Flash
AID Load Ay = +5 @ +5V

5V

5V

5V

INPUT
500 mY

INPUT

1~fvV

/div

.... - ....

-IOUTPUT

OUTPUT

5~~I~V
OV.r

50.s/dlv IQ]

L-L...:L.J--'--l.----'-~:_L...L...I

50 .s/di.

(g]

500mV
/div

OVr
50.s/di.

(g]

50 .s/div

"

(g]

TL/H/12313-4

2-322

,-----------------------------------------------------------------------------,
Typical Performance Characteristics (Continued)

r
......
.....

i:
w
.....

LM7131 Driving Flash
AID LoadAv = +s@ +SV
With 2 pF Feedback Capacitor

LM7131 Driving Flash
AID Load Ay = + 10 @ +SV
SOOmV

5V

INPUT
100mV
/div

INPUT
100mV
/div

-rI

I
I

,,

OUTPUT
SOOmV
/div

OUTPUT
SOOmV
/div

-SOOmV
OV.r
50 ns/div

50 ns/div

ITIl

ITIl
TL/H/12313-6

TLlH/12313-5

LM7131 Bode Plot
@ 3V, SV and 10V
Ref Level 0.000 dB IDiv 1.000 dB

SV-;-..

3V

Ii!

IJP

-OdB

Spl" Supplies

AV

10V

=

+1

RL = 150n

-3dB
3V

,\
lOOk

10M

.114

START 100 000.000 Hz

100M

STOP 200 000.000 Hz

TLlH/12313-7

LM7131 Single Supply
Bode Plot @ 3V, SVand 10V
Ref Level 0.000 dB IDiv 1.000 dB

3~_
~~

OdB

Single Supplies

Av = +1

10V

RL

= 150n

-3dB

3V
SV
lOOk

1M

10M

START 100 000.000 Hz

2-323

~

~
100M

STOP 200 000.000 Hz

TLlH/12313-8

...."'"

-~------------------------------------~

('I)

::E

Application Information
The LM7131 is a high speed complementary bipolar amplifier which provides high perlormance at single supply voltages. The LM7131 will operate at ±5V split supplies, +5V
single supplies,and +3V single supplies. It can provide improved performance for ± 5V designs with an easy transition to +5V single supply. The LM7131 is a voltage feedback amplifier which can be used in most operational amplifier circuits.

and disk drive write heads. The small size of the SOT23-5
package can allow it to be placed with a pre-amp inside of
some rotating helical· scan video head (VCR) assemblies.
This avoids long cable runs for low level video signals, and
can result in higher signal fidelity ..
Additional space savings parts are available in tiny packages from National Semiconductor, including low power amplifiers, precision voltage references, and voltage regulators.

The LM7131 is available,!n three package types: DIPs for
through hole designs, 50-8 surface mount packages and
the SOT23-5 Tiny package for space and weight savings.

Notes on Performance Curves and
Datasheet Limits

GENERAL INFORMATION

The LM7131 has been designed to meet some of the most
demanding req'uirements for single supply amplifiers-driving analog to digital converters and video cable driving. The
output stage of the LM7131 has been specially designed for
the dynamic load presented by analog to digital converters.
The LM7131 is capable of a 4V output range with a +5V
single supply. The LM7131's drive capability and good differential gain and phase make quality video possible from a
small package with only a + 5V supply.

Important:

Performance curves represent an average of parts, and are
not limits.
SUPPLY CURRENT VB SUPPLY VOLTAGE

Note that this curve is nearly straight, and rises slowly as
the supply voltage increases.
INPUT CURRENT vs INPUT VOLTAGE

BENEFITS OF THE LM7131

This curve is relatively flat in the 200 mV to 4V input range,
where the LM7131 also has good common mode rejection.

The LM7131 can make it possible to amplify high speed
signals with a single + 5V or + 3V supply, saving the cost of
split power supplies.

COMMON MODE VOLTAGE REJECTION

EASY DESIGN PATH FROM ± 5V to

Note that there are two parts to the CMRR specification of
the datasheet for 3V and 5V. The common mode rejection
ratio of the LM7131 has been maximized for signals near
ground (typical of the active part of video Signals, such as
those which meet the RS-170 levels). This can help provide
rejection of unwanted noise pick-up by cables when a balanced input is used with good input resistor matching. The
mid-level CMRR is similar to that of other single supply op
amps.

+ 5V SYSTEMS

The DIP and 50-8 packages and similar ± 5V and single
supply specifications means the LM7131 may be able to
replace many more expensive or slower op amps, and then
be used for an easy transition to 5V single supply systems.
This could provide a migration path to lower voltages for the
amplifiers in system designs, reducing the effort and expense of testing and re-qualifying different op amps for each
new design.
In addition to providing a design migration path, the three
packages types have other advantages.
The 01 Ps can be used for easy prototyping and through hole
boards. The 50-8 for surface mount board designs, and
using the SOT23-5 for a smaller surface mount package can
save valuable board space.

BODE PLOTS (GAIN VB FREQUENCY FOR Ay =

+ 1)

The gain vs. frequency plots for a non-inverting gain of 1
show the three voltages with the 1500. load connected in
two ways. For the single supply graphs, the load is connected to the most negative rail, which is ground. For the split
supply graphs, the load is connected to a voltage halfway
between the two supply rails.
DRIVING CABLES

SPECIFIC ADVANTAGES OF S0T23-5 (TINY PACKAGE)

Pulse response curves for driving 750. back terminate cables are shown for both 3V and 5V supplies. Note the good
pulse fidelity with straight 150 loads, five foot (1.5 meter)
and 75 foot (22 meter) cable runs. The bandwidth is reduced when used in a gain of ten (Av = +10). Even in a
gain of ten configuration, the output settles to < 1% in
about 100 ns, making this useful for amplifying small signals
at a sensor or signal source and driving a cable to the main
electronics section which may be located away from the
signal source. This will reduce noise pickup.

The SOT23-5 (Tiny) package can save board space and
allow tighter layouts. The low profile can help height Ii~ited
designs, such as sub-notebook cOlllPuters, consumer Video
equipment, personal digital assistants, and some of the
thicker PCMCIA cards. The small size can improve signal
integrity in noisy environments by placing the amplifier closer to the signal source. The tiny amp can fit into tight spaces
and weighs little. This makes it possible,,'to design the
LM7131 into places where amplifiers could not previously
fit.
The LM7131 can be used to drive coils and transformers
referenced to virtual ground, such as magnetic tape heads

Please refer to Figures 1-5 for schematics of test setups
for cable driving.

2-324

r-

Application Information

s::

....,
....
W
....

(Continued)

rek
P6204 1 GHz
FETX10tp
10~// 1.7pF
(1.t2 prj

+Vs

rek
P6204 1 GHz
FEr X10
1°r/121rit

1:

+0.3V
\0 IN
+2V

>--+-~-~ RL

(0.15 prj

---~~~--I

75

75

TLlH/12313-9

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 1. Cable Driver Av =

+1

rek
P6204 1 GHz
FET X1
10M/ /1.7 pF
(1.t2 prj

°

+D.15V

RL
(0.15 pF)

@-

,tfv IN..L----"......t---I

75

75

TLlH/12313-1D

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 2. Cable Driver Av =

+2

•

1:

+0.15V
\0 IN
+1V

---~~~--I

TL/H112313-11

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 3. Cable Driver 5' RG·59

2-325

~
CO)

-;::

r-----------------------------------------------------------------------------------------------,
Application Information

(Continued)

:E
....I

2k

+Vs

Tek
P6204 1 GHz
rET Xl0
10!,//1.7pr
t 1.12 prj

1:

+0.15V
to IN
+1V

---......;::.......--1

TL/H/12313-12

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 4. Cable Driver 75' RG-59

220

2k

~Tek

r-Yo"'""-4I----..J\M,.....-..:;..--, P6204 1 GHz
rET Xl0

Tek
P6204 1 GHz
rEr Xl0
10!-t//1.7pr
t 1.72 prj

+VS

10~//1.7pr

t 1.12 prj

1:

RL
(0.15 prj

+0.3V
to IN
+2V

TL/H/12313-13

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 5. Cable Driver Gain of 10 Av =

2·326

+ 10

.-----------------------------------------------------------------------.r
Application Information

i:

(Continued)

......-..
Co)

DRIVING TYPE 1175 FLASH AID LOADS

The circuits in Figures 6-11 show a LM7131 in a voltage
follower configuration driving the passive equivalent of a
typical flash AID input. Note that there is a slight ringing on
the output. which can affect accurate analog-to-digital conversion. In these graphs, we have adjusted the ringing to be
a little larger than desirable in order to better show the settling time. Most settling times at low gain are about 75 ns to
< 1% of final voltage. The ringing can be reduced by adding a low value (approximately 500.0) feedback resistor from
the output to the inverting input and placing a small (picofar-

ad range) capacitor across the feedback resistor. See Figures 9 and 10 for schematics and respective performance
curves for flash AID driving at Av = + 5 with and without a
2 pF feedback capacitor.
See section on feedback compensation. Ringing can also
be reduced by placing an isolation resistor between the output and the analog-to-digital converter input-see sections
on driving capacitive loads and analog-to-digital converters.
Please refer to Figures 6-11 for schematics of test setups
for driving flash AID converters.

2k

50

+Vs

>t:L
__---4~~E----,~kl

GHz
FET Xl 0
10MII1.7pF
(1.12 pF)

• 0.1 J'FI CHrTm

47~F

TANT

20pF

I
TLlH/12313-14

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 6. Flash AID Ay

T8k

+Vs

P6204 1 GHz
FET Xl 0
10MI/1.7pF
(1.12pF)

= -1

•

~t:L___~~(:",-""""~kl
(2.2 pF)

GHz

FET Xl0
1O!A 1/ 1. 7)PF
\1.12pF

/

50

30n

• O. 1 J'F CHIP CAP

4~~~ ~1~~
20pF

I
TLlH/12313-15

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 7. Flash AID Ay =

2-327

+1

~

Cf)

~

r------------------------------------------------------------------------------------------,
Application Information

(Continued)

::!I
Tok
P6204 1 GHz
'FET Xl0
10!oi/ /1.7 pF
(1.12 pF),

·0.1 }'f1 CH~PTm
47!f.f TANT
20pf

I
TL/H/12313-16

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 8. Flash AID Ay =

+2

Tok
P6204 1 GHz
fET Xl0
10" / /1.7 pf
(1.1-2 prJ
+O.IV

to

, (2.2PF)/

+0.5V
50

30n
• 0.1 }'fl CHJPTm
47!f.f TANT
20pF

I
TUH/12313-17

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 9. Flash AID Ay =

2·328

+5

Application Information

r!:

....
....
~

(Continued)

Co:»

1"'~""'''''''''-'''.J>yVlt-....:~;.....,P620~Ok,

x

Tok

FET 1GHz
0
10!ot111.7pF
(1.72pF)

+Vs

P6204 1 GHz
FET X10
10!ot111.7pF
(1.12pF)

+0.1V

\0

(2.2PF)/

+0.5V
50

30n

• O. 1 J'F, CH~PTm
47!f..F TANT
20pF

I
TL/H/12313-18

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 10. Flash AID Ay =

+ 5 with Feedback Capacitor

220

2k

~TOk

r-y.,,.,,...........--""""Mr--~--.
Tok

P6204 1 GHz
FET X10
10!ot 111.7 pF
(1.12 pF)

+0.5V

\0
+2.5V

1N

+Vs

P6204 1 GHz
FET X10
10!ot111.7pF
(1.12 pF)

@-

-L
30n

I

20PF
TLlH/12313-19

Numbers in parentheses are measured
fixture capacitances w/o OUT and load.

FIGURE 11. Flash AID Ay =

+ 10

II

2-329

Using the LM7131
No load powerNo load LM7131 supply current - 9.0 mA
Supply voltage is 5.0V
No load LM7131 power - 9.0 mA x 5.0V = 45 mW

LIMITS AND PRECAUTIONS
Supply Voltage

The absolute maximum supply voltage which may be .applied to the LM7131 is 12V. Designers should not-design for
more than 10V nominal, and carefully check supply tolerances under all conditions so that the voltages do not exceed the maximum.

Power with loadCurrent out is 2.0V/150 0. = 13.33 mA
Voltage drop in LM7131 is 5.0V (supply) (output) = 3.0V

Power dissipation 13.33 mA x 3.0V = 40 mW
Total Power = 45 mW + 40 mW = 85 mW
0.085
Temperature Rise = 0.085 W x 325°/W = 27.625
degrees
Junction temperature at 40° ambient = 40 +
27.625 = 67.6225°.
This device is within the 0° to 70° specification limits.
The 325° /W value is based on still air and the pc board land
pattem shown in this datasheet. Actual power dissipation is
sensitive to PC board connections and airflow.

Differential Input Voltage
Differential input voltage is the ciifference in voltage between the non-inverting (+) input and the inverting input
( -) of the op amp. The absolute maximum differential input
voltage is ±2V across the inputs. This limit also applies
when there is no power supplied to the op amp. This may
not be a problem in most conventional op amp designs,
however, designers should avoid using the LM7131 as comparator or forcing the inputs to different voltages. In some
designs, diode protection may be needed between the inputs. See Figure 12.
Gain of +2

SOT23-5 power dissipation may be increased by airflow or
by increasing the metal connected to the pads, especially
the center pin (pin number 2, V -) on the left side of the
SOT23-5. This pin forms the mounting paddle for the die
inside the SOT23-5, and can be used to conduct heat away
from the die. The land pad for pin 2 can be made larger
and/or connected to power planes in a multilayer board.
Additionally, it should be noted that difficulty in meeting performance specifications for the LM7131 is most common at
cold temperatures. While excessively high junction temperatures will degrade LM7131 performance, testing has confirmed that most specifications are met at a junction temperature of 85°C.

75n

Input

Protection

Diodes

2.0V

!.

Rl

249n

TL/H/12313-20

See "Understanding Integrated Circuit Package Power Capabilities", Application Note AN-336, which may be found in
the appendix of the Operational Amplifier Databook.

FIGURE 12
Output Short Circuits

The LM7131 has output short circuit protection, however, it
is not designed to withstand continuous short circuits, very
fast high energy transient voltage or current spikes, or
shorts to any voltage beyond the power supply rails. Designs should reduce the number and energy level of any
possible output shorts, especially when used with ± 5V supplies.

Layout and Power Supply Bypassing
Since the LM7131 is a high speed (over 50 MHz) device,
good high speed circuit layout practices should be followed.
This should include the use of ground planes, adequate
power supply bypassing, removing metal from around the
input pins to reduce capaCitance, and careful routing of the
output signal lines to keep them away from the. input pins.

A resistor in series with the output, such as the 750. resistor
used to back terminate 750. cables, will reduce the effects
of shorts. For outputs which will send signals off the PC
board additional protection devices, such as diodes to the
power rails, zener-type surge suppressors, and varistors
may be useful.

The power supply pins should be bypassed on both the negative and positive supply inputs with capaCitors placed close
to the pins. Surface mount capaCitors should be used for
best performance, and should be placed as close to the
pins as possible. It is generally advisable to use two capacitors at each supply voltage pin. A small surface mount capaCitor with a value of around 0.01 microfarad (10 nF), usually a ceramic type with good RF performance, should be
placed closest to the pin. A larger capacitor, in usually in the
range of 1.0 p.F to 4.7 p.F, should also be placed near the
pin. The larger capaCitor should be a device with good RF
characteristics and low ESR (equivalent series resistance)
for best results. Ceramic and tantalum capaCitors generally
work well as the larger capaCitor.
For Single supply operation, if continuous low impedance
ground planes are available, it may be possible to use bypass capacitors between the + 5V supply and ground only,
and reduce or eliminate the bypass capaCitors on the Vpin.

Thermal Management

Note that the SOT23-5 (Tiny) package has less power dissipation capability (325°/W) than the SO-8 and DIP packages
(115° /W). This may cause overheating with ± 5 supplies
and heavy loads at high ambient temps. This is less of a
problem when using + 5V Single supplies.
Example:
Driving a 1500. load to 2.0V at a 40°C (104 OF) ambient
temperature. (This is common external maximum temperature for office environments. Temperatures inside equipment may be higher.)

2-330

Using the LM7131

(Continued)

Capacitive Load Driving
The phase margin of the LM7131 is reduced by driving large
capacitive loads. This can result in ringing and slower settling of pulse signals. This ringing can be reduced by placing
a small value resistor (typically in the range of 22.0-100.0)
between the LM7131 output and the load. This resistor
should be placed as close as practical to the LM7131 output. When driving cables, a resistor with the same value as
the characteristic impedance of the cable may be used to
isolate the cable capacitance from the output. This resistor
will reduce reflections on the cable.

Driving Flash AID Converters (Video Converters)
The LM7131 has been optimized to drive flash analog to
digital converters in a + 5V only system. Different flash AID
converters have different voltage input ranges. The LM7131
has enough gain-bandwidth product to amplify standard video level signals to voltages which match the optimum input
range of many types of AI D converters.
For example, the popular 1175 type 8-bit flash AID converter has a preferred input range from 0.6V to 2.6V. If the input
signal has an active video range (excluding sync levels) of
approximately 700 mV, a circuit like the one in Figure 13 can
be used to amplify and drive an AID. The 10 ",F capacitor
blocks the DC components, and allows the + input of the
LM7131 to be biased through R clamp so that the minimum
output is equal to VRB of the AID converter. The gain of the
circuit is determined as follows:
Output Signal Range = 2.6V (V top) = 0.6V (V bottom) = 2.0V
Gain = Output Signal Range/Input Signal = 2.857
= 2.00/0.700

Input Current
The LM7131 has typical input bias currents in the 15 ",A to
25 ",A range. This will not present a problem with the low
input impedances frequently used in high frequency and video circuits. For a typical 75.0 input termination, 20 ",A of
input current will produce a voltage across the termination
resistor of only 1.5 mY. An input impedance of 10 kn, however, would produce a voltage of 200 mV, which may be
large compared to the signal of interest. Using lower input
impedances is recommended to reduce this error source.

Gain = (Rt/Rt) +1 = (249.0/133.0) +1
R isolation and Ct will be determined by the designer based
on the AID input capacitance and the desired pulse response of the system. The nominal values of 33.0 and 5.6
pF shown in the schematic may be a useful starting point,
however, signal levels, AID converters, and system performance requirements will require modification of these
values.

Feedback Resistor Values and Feedback Compensation
Using large values of feedback resistances (roughly 2k) with
low gains (such gains of 2) will result in degraded pulse
response and ringing. The large resistance will form a pole
with the input capacitance of the inveriing input, delaying
feedback to the amplifier. This will produce overshoot and
ringing. To avoid this, the gain setting resistors should be
scaled to lower values (below 1k) At higher gains (> 5)
larger values of feedback resistors can be used.
Overshoot and ringing of the LM7131 can be reduced by
adding a small compensation capacitor across the feed
back resistor. For the LM7131 values in pF to tens of pF
range are useful initial values. Too large a value will reduce
the circuit bandwidth and degrade pulse response.
Since the small stray capacitance from the circuit layout,
other components, and specific circuit bandwidth requirements will vary, it is often useful to select final values based
on prototypes which are similar in layout to the producti,on
circuit boards.

The isolation resistor, R isolation should be placed close to
the output of the LM7131, which should be close to the AID
input for best results.
R clamp is connected to a voltage level which will result in
the bottom of the video signal matching the Vrb level of the
AID converter. This level will need to be set by clamping the
black level of the video signal. The clamp voltage will depend on the level and polarity of the video signal. Detecting
the sync signal can be done by a circuit such as the LM1881
Video Sync Separator.
Important Note: This is an illustration of a conceptual use of the LM7131,
not a complete design. The circu~ designer will need to modify this for input
protection, sync, and possibly some type of gain control for varying signal
levels.

Reflections
The output slew rate of the LM7131 is fast enough to produce reflected signals in many cables and long circuit
traces. For best pulse periormance, it may be necessary to
terminate cables and long circuit traces with their characteristic impedance to reduce reflected signals.
Reflections should not be confused with overshoot. Reflections will depend on cable length, while overshoot will depend on load and feedback resistance and capacitance.
When determining the type of problem, often removing or
drastically shortening the cable will reduce or eliminate reflections. Overshoot can exist without a cable attached to
the op amp output.

Some AID converters have wide input ranges where the
lower reference level can be adjusted. With these converters, best distortion results are obtained if the lower end of
the output range is about 250 mV or more above the Vinput of the LM7131 more. The upper limit can be as high as
4.0V with good results.

Driving the ADC12062

+ 5V 12-BIT AID Converter

Figure 14 shows the LM7131 driving a National ADC12062
12 bit analog to digital converter. Both devices can be powered from a single + 5V supply, lowering system complexity
and cost. With the lowest signal voltage limited to 300 mV
and a 3.8V peak-to-peak 100 KHz signal, bench tests have
shown distortion less than - 75 db, signal to noise ratios
greater than 66 db, and SINAD (Signal to noise + distortion)
values greater than 65 db. For information on the latest single supply analog-to-digital converters, please contact your
National Semiconductor representative.

2-331

fII

~

~

r:

~

r------------------------------------------------------------------------------------------,
Using the LM7131

Video

(Continued)

1

0.6V

2.0V

VRB

VRT

BoUom
Top
Reference Reference

RisQlation
>--~~"IIfy----I VIN

10 }'F

7511

TMCI175
Flap'h

AID
CO,nverter

5.6 pF
TLlHI1231,3-21

FIGURE 13

••.-----------------------~------ADC12062
VIN1 :

'Input signal

»-------------....;-.;:1--

(Through Multiplexer)

Rwux

VIN2 •

••
•
••
••
•

MUX OUT'
+5V
Input signal> ___ _
(Direct)

ADC IN'

RSW
S/H~To Compo rotors

•• Switch
.l.. c
IIN
••
••
•
._------------------------------

TLlH/12313-22

FIGURE 14. Buffering the Input with an LM7131 High Speed Op Amp

2·332

Using the LM7131

(Continued)

CCD Amplifiers

For additional space savings, the LM4040 precision voltage
reference is available in a tiny SOT23-3 package.

The LM7131 has enough gain bandwidth to amplify low IEivel signals from a CCD or similar image sensor and drive a
flash analog-to-digital converter with one amplifier stage.

Video Gain of + 2
The design of the LM7131 has been optimized for gain of
+2 video applications. Typical values for differential gain
and phase are 0.25% differential gain and 0.75 degree differential phase. See Figure 12.

Signals from CCDs, which are used in scanners, copiers,
and digital cameras, often have an output signal in the 100
mV-300 mV range. See Figure 15 for a conceptual diagram. With a gain of 6 the output to the flash analog-todigital converter is 1.8V, matching 90% of the converter's
2V input range. With a -3db bandwidth of 70 MHz for a
gain of + 1, the bandwidth at a gain of 6 will be 11.6 MHz.
This 11.6 MHz bandwidth will result in a time constant of
about 13.6 ns. This will allow the output to settle to 7 bits of
accuracy within 4.9 time constants, or about 66 ns. Slewing
time for a 1.8V step will be about 12 ns. The total slewing
and settling time will be about 78 ns of the 150 ns pixel valid
time. This will leave about 72 ns total for the flash converter
signal acquisition time and tolerance for timing Signals.
Fqr scanners and copiers with moving scan bars, the
SOT23-5 package is small enough to be placed next to the
light sensor. The LM7131 can drive a cable to the main
electronics section from the scan bar. This can reduce
noise pickup by amplifying the signal before sending on the
cable.

Improving Video Performance
Differential gain and phase performance can be improved
by keeping the active video portion of the signal above
300 mY. The sync signal can go below 300 mV without affecting the video quality. If it is possible to AC couple the
signal and shift the output voltage slightly higher, much better video performance is possible. For a + 5V Single supply,
an output range between 2.0V and 3.0V can have a differential gain of 0.07% and differential phase of 0.3 degree when
driving a 1500 load. For a + 3V single supply, the output
should be between 1.0V and 2.0V.
Cable Driving with + 5V Supplies
The LM7131 can easily drive a back-terminated 750 video
cable (1500 load) when powered by a + 5V supply. See
Figures 2, 3 and 4. This makes it a good choice for video
output for portable eqUipment, personal digital devices, and
desktop video applications.

AID Reference Drivers
The LM7131's output and drive capability make it a good
choice for driving analog-to-digital references which have
suddenly changing loads. The small size of the SOT23-5
package allow the LM7131 to be placed very close to the
AID reference pin, maximizing response. The small size
avoids the penalty of increased board space. Often the
SOT23-5 package is small enough that it can fit in space
used by the large capaCitors previously attached to the AID
reference. By acting as a buffer for a reference voltage,
noise pickup can be reduced and the accuracy may be increased.

The LM7131 can also supply +2.00V to a 500 load to
ground, making it useful as driver in 500 systems such as
portable test equipment.
Cable Driving with + 3V Supplies
The LM7131 can drive 1500 to 2.00V when supplied by a
3V supply. This 3V performance means that the LM7131 is
useful in battery powered video applications, such as camcorders, portable video mixers, still video cameras, and portable scanners.

r----'I
0+-- V.lamp
. _--_.1

Rclamp I

r-.J\I'\fIr--il-c;r

tI

+5V

Data
Out

TLlH/12313-23

FIGURE 15. CCD Amplifier

2-333

.......... .------------------------------------------------------------------------------------------,
C")

Using the LM7131

:::::E

....I

(Continued)

Audio and High Frequency Signal Processing
The lM7131 is useful for high fidelity audio and signal processing. A typical lM7131 is capable of driving 2V across
1500 (referenced to ground) at less than 0.1 % distortion at
4 MHz when powered by a single 5V supply.

Good AC performance will require keeping the output further away from the ,supply rails. For a + 5V, supply ~nd relatively high impedance load (analog-to-digital converter input) the following are suggested as an initial starting range
for achieving high (> 60 dB) AC accuracy Upper output level-:~pproximately O.BV to 1V below the positive (V +) rail.
lower output levelApproximately 200 mV-300 mV above the negative rail.
The lM7131 very useful in virtual ground systems as an
output device for output loads which are referenced to OV or
the lower rail. It 'is also useful as a driver for capacitive
loads, such as sample and hold circuits, and audio analog to
digital converters. If fast amplifiers with rail-to-rail output
ranges are needed, please see the National Semiconductor
lM6142 datasheet.

Use with 2.5V Virtual Ground Systems
with + 5V Single Supply Power
Many analog systems which must work on, a single + 5V
supply use a 'virtual ground' - a reference voltage for the
signal processing which is usually between + 5V and OV.
This virtual ground is u:;ually halfway between the top and
bottom supply rails. Yhisis usually + 2.5V for + 5V systems
and +' 1.5V for + 3V systems.
The lM7131 can_be used in single supply/virtual ground
systems driving loads referenced to 2.5V. The output swing
specifica,tions in the data sheet show the tested voltage limits for driving a _1500 load to a virtual ground supply for
+3Vand +5V. A look at the output swing specifications
shows that for heavy loads like 150 ohms, the output will
swing as close as one diode drop (roughly, 0.7V) to the
supply rail. This leaves a relatively wide range for + 5V systems and a somewhat narrow range for + 3V systems., One
way to increase this output range is to have the output load
referenced to ground-this will allow the output to swing
lower. Another is to use higher load impedances. The output
swing specifications show typical numbers for Swing with
loads of 6000 to ground. Note that these typical numbers
are similar to those for a 1500 load. T,hese typical numbers
are an indication of the maximum OC performance of the
lM7131.
'
,

0/A Output Amplifier
The LM7131 can be used as an output amplifier for fast
digital-to-analog converters. When using the lM7131 with
converters with an output voltage range which may exceed
the differential input voltage limit of ±2V, it may be necessary to add protection diodes to the inputs. See Figure 16.
For high speed applications, it may be useful to consider low
capaCitance schottky diodes. Additional feedback capacitance may be needed to control ringing due to the additional
input capacitance from the 0/A and protection diodes.
When used with current output 01 As, the input bias currents
may produce a OC offset in the output. This offset may be
canceled by a resistor between th,e positive input and
ground.

The sinking output onhe lM713l is somewhat lower than
the amplifier's sourcing capability. This means that the
lM7131 will not drive as much current into a load tied to 2.5
Vas it will drive into a load tied to OV.

Spice Macromodel
A SPICE macromodel of the lM7131 and many other National Semiconductor op amps is available at no charge
from your National Semiconductor representative.

0/ A CONVERTER
loul

1--¥.fY--.....- -...--+--1

Very-S-m-.-II-re-'-isl..lor

.J

Low capacitance /

Schottky

diode.

TL/H/I2313-24

FIGURE 16. 01 A Ouput Amplifier

2-334

r-----------------------------------------------------------------------------~~

!!I:

......
....
....

SOT-23-5 Tape and Reel Specification

Co)

TAPE FORMAT
Tape Section

#Cavaties

Cavity Status

Cover Tape Status

Leader
(Start End)

o (min)

Empty

Sealed

75 (min)

Empty

Sealed

3000

Filled

Sealed

Carrier
Trailer
(Hub End)

250

Filled

Sealed

125 (min)

Empty

Sealed

o (min)

Empty

Sealed

TAPE DIMENSIONS

0' 0.061 :1:0.002 TYP.
[ I.SS:l:O.os]

BAT
TANGENT
POINTS

+'::;===,fl'''!!tt__

RO.012 TYP

[0.3]

ALL INSIDE RADII

0' 0.041 :1:0.002 TYP.
[1.0HO.OS]

DIRECTION or rEED - - - -

:L

~

0.012

/"~".
[0.3]
GAGE LINE
SECTION B-B

K

R 1.181 MIN. "

[30]

----~
BEND RADIUS
NOT TO SCALE

TLlH/12313-25

8mm

0.130
(3.3)

0.124
(3.15)

0.130
(3.3)

0.126
(3.2)

Tape Size DIMA DIMAo DIMS DIM So

0.138 ±0.002 0.055 ± 0.004
(3.5 ±O.O5)
(1.4 ±O.11)
DIMF

2-335

DIMKo

0.157
(4)

0.315 ±O.012
(8 ±O.3)

DIMP1

DIMW

.- r---------------------------------------------------------------------------------,
C")

.-

:i"'"

SOT·23·5 Tape and Reel Specification

(Continued)

REEL DIMENSIONS

TAPE SLOT

r

A

N

'L
~
SCALE: 3X

/
8mm
Tape Size

TL/H/12313-26

7.00 0.059 0.512 0.795 2.165 0.331 +0.059/-0.000 0.567 W1 + 0.078/-0.039
330.00 1.50 13.00 20.20 55.00 8.4 + 1.50/-0.00 14.40 W1 + 2.00/-1.00
A

B

C

D

N

W1

2-336

W2

W3

ADVANCE INFORMATION

t!lNational Semiconductor

LM7171 Very High Speed High Output Current
Voltage Feedback Amplifier
General Description

Features (Typical Unless Otherwise Noted)

The LM7171 is a voltage feedback amplifier optimally designed for Av > 1 operation. It provides a very high slew
rate at 41 OOV/ /A-s and a wide gain-bandwidth product bandwidth of 200 MHz while consuming only 6.5 mA of supply
current. It is ideal for video and high speed signal processing applications such as ultrasound and pulse amplifiers.
With 100 mA output current, the LM7171 can be used for
video distribution, transformer driver and laser diode driver.

•
•
•
•
•
•
•
•
•

The ± 15V power supplies allow for large signal swings and
give greater dynamic range and signal-to-noise ratio. The
LM7171 offers low SFDR and THO, ideal for ADC/DAC systems. In addition, the LM7171 is specified for ± 5V operation for portable applications.
The LM7171 is built on Nationals advanced VIPTM III (Vertically integrated PNP) complementary bipolar process.

Typical Performance

HDSL and ADSL Drivers
Multimedia Broadcast Systems
Professional Video Cameras
Video Amplifiers
Copiers/Scanners/Fax
HDTV Amplifiers
Pulse Amplifiers and Peak Detectors
CATV/Fiber OptiCS Signal Processing

..2..
-IN 2.

II

16·Pln Wide Body SO

a-Pin DIP/SO

'-.../

N/C

~

Applications
•
•
•
•
•
•
•
•

Connection Diagrams

Large Signal Pulse Response
Ay = + 2, Vs = ± 1SV

'>

Easy-To-Use Voltage Feedback Topology
4100V//A-s
Very High Slew Rate
200 MHz
Wide Gain-Bandwidth Product
220 MHz
-3 dB Frequency @ Av = +2
6.5mA
Low Supply Current
85 dB
High Open Loop Gain
100 mA
High Output Current
0.01 %, 0.02'
Differential Gain and Phase
Specified for ± 15V and ± 5V Operation

3

+IN-

v-~

=f>,-

~

-

6

.2.
-IN 2N/C ...!.
+IN 2 - +
N/C .!.
v- .!...
N/C ..!.
N/C

OUTPUT

~N/C
TL/H/12351-1

Top View

\....../

N/C ...:....

!... N/C
2... v+

Temperature Range
Industrial
- 40'C to + a5'C

Military
- SS'C to + 12S'C

LM7171 AIN, LM7171 BIN
5962-9553601 QPA'

8-PinCDIP

16-Pin
Small Outline

"::"'N/C
OUTPUT

..!..!... N/C
..!..£...N/C

!.... N/C

Top View

Ordering Information

S-Pin
Small Outline

l!...v+

TL/H/12351-2

TL
~

Latch-Up
Voltage
(Note 1) (V)

D855451
DS55452
D855453
D855454

3·18
3·18
3-18
8
8
8
8

3-13
3-13
3-13

65
80

3-23
3-26

4.4

3-29

55
55
55
55

3-32
3-32
3-32
3-32

3-1~

Note 1: Latch-up voltage is the maximum voltage the output can sustain when switching an inductive load.
Note 2: 058310 inverting, posHive edge latching.
Note 3: 0$8311 inverting. fall through latch.
Note 4: 053668 35V. latch·up with output fault protection.
Note 5: 083680 has a differential input circuit.

HIGH CURRENT SWITCH SELECTION GUIDE
Continuous
Current

Peak
Current

1

1.0A

2.0A

4.5Vto26V

none

LM1950'

1

750mA

1.4A

4.75Vto26V

none

LM1951"

1

1.0A

2.5A

4.5Vto26V

Error Flag

LMD18400'

4

1.0A

3.0A

6Vto 28V

Device
LM1921'

Driversl
Package

Input Voltage
Range

Diagnostics

~

Error Flag
Thermal Shutdown Flag
Data Output provides switch status feedback, output load fault conditions and thermal and overvoltage
shut-down status.

.,All incorporate Automotive transient protection.

tflNational Semiconductor

High Current Switch Selection Guide

Device

Driversl
Package

Continuous
Current

Peak
Current

Input Voltage
Range"

Diagnostics

Page
No.

LM1921

1

1.0A

2.0A

4.5Vto 26V

None

3-44

LM1950

1

750mA

1.4A

4.75Vto26V

None

3-49

LM1951

1

1.0A

2.5A

4.5Vto26V

Error Flag

3-54

LMD18400

4

1.0A

3.0A

6Vto26V

Error Flag
Thermal Shutdown Flag
Data Output provides switch
status feedback, output
load fault conditions
and thermal and
overvoltage shutdown status .

3-74

• All devices incorporate Automotive transient protection.

•
3-5

tflNational Semiconductor

DP7310/DP8310/D,P7311/DP8311
Peripheral Drivers '

Oct~1

Latched

• All outputs simultaneously sink rated current "DC" with
no thermal derating at maximum rated temperature
• Parallel latching or buffering
• Separate activ~ low eliables for easy data bussing
• Internal "glitch free" power up clear
• 10% Vee tolerance

General Description
ThE! DP731 0/8310, DP7311/8311 Octal Latched Peripheral
Drivers provide the function of latching eight, bits of data
with open collector outputs, each driving up to 100 mA DC
with an operating voltage range of 30V. Both devices are
designed for low input currents, high input/output voltages,
and feature a power up clear (outputs off) function.

Applications

The DP7310/8310 are positive edge latching. Two active
low write/enable inputs are available for convenient data
bussing without external gating.
The DP7311/8311 are positive edge latches. The active low
strobe input latches data or allows fall through operation
when held at logic "0". The latch9$ are cleared (outputs off)
with a logic "0" on the clear pin.

•
•
•
•
•
•
•
•
•

Features
• High current, high voltage open collector outputs
• Low current, high voltage inputs

High cljrrent high voltage drivers
Relay drivers
Lamp drivers
I.,ED drivers
TRIAC drivers ,
Solenoid drivers
Stepper motor drivers
Level translators
Fiber-optic LED drivers

Connection Diagrams
Dual-In-Llne Package

Dual-In-Llne Package

WEt

20

Vee

CD!

20

vee

DI4

19

DI4

19

STH

DI3

18

WE2
DI5

DI3

18

DI5

DI2

17

016

012

17

016

011

0P73101 16
DP8310 15

017
018

011

DOl

0P73111 16
DP8311 15

017

001
D02

14

D03

13

D08
D07

D02

7

D03

004

9

12

006

004

GNO

10

11

005

UNO

10

018

14

D08

13

007

12

006

11

005

TUF/5246-1

TLIF15246-2

Top View

Top View
Order Number DP7310J, DP7311J,
DP8310N or DP8311N
See NS Package Number J20A or N20A

3-6

C

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

7.0V

Input Voltage

35V

Output Voltage

35V

Maximum Power Dissipation" at 25'C
Cavity Package
DP8310/DP8311
Storage Temperature Range

"V
......

Operating Conditions

(Note 1)

Supply Voltage (Vee)

Min
4.5

Max
5.5

Units
V

Temperature
DP7310/DP7311
DP8310/DP8311

-55
0

+125
+70

'C
'C

Input Voltage

30

V

Output Voltage

30

V

W

.....

C)

.......
C

"V

......

W
.....
.....

C

"V
CD
W

.....
C)

1821 mW
2005mW
- 65'C to + 150'C

C

"V

Lead Temperature (Soldering, 4 sec.)
260'C
'Derate cavity package 12.1 mWrC above 25'C; derate molded package
16.0 mW I'C above 25'C.

~
.....

.....

DC Electrical Characteristics DP7310/DP8310, DP7311 /DP8311 (Notes 2 and 3)
Symbol

Parameter

VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

VOL

Logical "0" Output Voltage
DP7310/DP7311
DP8310/DP8311

IOH

Logical "1" Output Current
DP7310/DP7311
DP8310/0P8311

Conditions

Min

Typ

Max

2.0

Units
V

0.8

V

0.35

0.4
0.5

V
V

Data outputs latched to
logical "1", Vee = Min.
VOH = 25V
VOH = 30V

2.5

500
250

p.A
p.A

0.1

25

p.A

1

250

p.A

Data outputs latched to
logical "0", Vee = Min.
IOL = 75 rnA
IOL = 100mA

IIH

Logical "1" Input Current

VIH = 2.7V, Vce = Max

II

Input Current at Maximum Input
Voltage

VIN = 30V, Vee = Max

IlL

Logical "0" Input Current

VIN = 0.4V, Vee = Max

-215

-300

p.A

-0.8

-1.5

V

100
100
88
88

125
152
117
125

mA
rnA
rnA
rnA

40
40
25
25

47
57
34
36

rnA
rnA
rnA
rnA

Vclamp

Input Clamp Voltage

liN = 12mA

lceo

Supply Current, Outputs On

Data outputs latched to a
logical "0". All Inputs are
at logical "1", Vee = Max.

DP7310
DP8310
OP7311
DP8311
lee1

Supply Current, Outputs Off

Data outputs latched to a
logic "1". Other
conditions same as leeo.

DP7310
DP8310
DP7311
OP8311

3-7

•

....('I)

~

c
Ci
..-

AC Electrical Characteristics DP7310/DP8310:Vcc =
Symbol

Parameter

-55"0 to + 125°C

4.5V. TA =

Conditions

Min

Typ

Max

Units

40

120

ns

70

150

ns

tpdO

High to Low Propagation Delay
Write Enable Input to Output

(Figure 1)

......
..-

tpdl

Low to High Propagation Delay
Write Enable Input to Output

(Figure 1)

"
C

tSETUP

Minimum Set-Up Time
Data in to Write Enable Input

tHOLD = Ons
(Figure 1)

Ci
..('I)

tpWH.
tpWL

Minimum Write Enable Pulse
Width

(Figure 1)

"C

tTHL

High to Low Output Transition Time

(Figure 1)

16

lTLH

Low to High Output Transition Time

(Figure 1)

38

70

ns

CIN

"N" Package (Note 4)

5

. 15

pF

('I)

co

D.
C

..('I)

D.

D.

AC Electrical Characteristics DP7311 IDP8311: Vee =
Symbol

Parameter

45

20

ns

60

25

ns
35

ns

5V. TA = 25°C

Conditions

Min

Typ

Max

Units

30

60

ns

70

100

ns

tpdO

High to Low Propagation Delay
Data In to Output

(Figure 2)

1pdl

Low to High Propagation Delay
Data to Output

(Figure 2)

!sETUP

Minimum Set-Up Time
Data in to Strobe Input

tHOLD = 0 ns
(Figure 2)

0

-25

1pWL

Minimum Strobe Enable Pulse Width

(Figure 2)

60

35

1pdC

Propagation Delay Clear to Data Output

(Figure 2)

1pwc

Minimum Clear Input Pulse Width

(Figure 2)

tTHL

High to Low Output Transition Time

(Figure 2)

20

35

ns

tTLH

Low to High Output Transition Time

(Figure 2)

38

60

ns

70
60

ns
ns
135

25

ns
ns

(Note 4)
Input Capacitance--Any Input
5
15
pF
Nol. 1: "'Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides condHions for actual device
oparation.
Note 2: Unless otherwise specHied minImax limits apply across the -55'C to + 125'C temperature range for the DP7310/DP7311 and across the O'C to +70'C
for the DP8310/DP8311. All typical values are for TA = 25'C, Va;; = 5V.
Note 3: All currents into device pins shown as posHive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
Note 4: Input capecHance is guaranteed by periodic testing. treST = 10kHz at 300 mV, TA = 25'C.
CIN

3-8

r-----------------------------------------------------------------------.c
."
...,
Logic Table
....
OP7310/0P8310
OP7311/0P8311
Co)

~

Oata
Input

Oata
Output

01 1-8

001-8

X
0

Q

1

0

1
1
1

0
0

0

1

0

1

0

0

1

1
1

0

X
X
X

Q
Q
Q

Write
Enable 1
WE1

Write
Enable 2
WE2

0
0
0

...r
...r

...r
...r

0

1

Clear
CLR

1

Oata
Input

Oata
Output

01 1-8

001-8

1

X

Q

0
0
X

0
1

1
0
1

Strobe
STR

X

X =
1 =
o =
Q =

...r

Don't Care
Outputs Off
Outputs On
Pre-existing Output
= Positive Edge Transition

C
."

...,

....
....

Co)

c

~

....

Co)

C)

C

."
CD

....
....

Co)

Block Diagrams
OP7310/0P8310

..
..
••

DATA (Dl8)
IN 8

.•

a-1t=:::t=::f-;;:-1

DATA DUT 8
(DD8)

WRITE ENAlll!...l
(WEl)
WRITE ENA!Il.L2

(WE2)~""--""

TUF/5246-3

."

OP731110P8311

~

DATA IN 1 :

DATA

-~

(~2~ O--llt=:::t=::f-;LA~;:c:Hl ~
•
••
•
..

DATA IN 8

.••

o-_-I-_~_-r-.L...-,

(018)

C('Mi~

,..

~" ~DATAOUTl
"

r::..m
DATA OUT 8
(008)

_....r......._--,

STIIlIBE
(m)
TUF/5246-4

3-9

•

-i_ r----------------------------------------------------------------------------,-

I

Switching Time Waveforms

Q

.....
o

DP7310/DP8310

C ")

~.....

-

3Y

, DATA INPUT

C ")

Ii:
Q

-fi:

3Y

WEl DR WEZ
OY---~--rl

'C»

v+----=;....~

OUTPUT

VOL

Q

TUF/S248-S

DP7311/DP8311
3V
DATA INPUT
OV

3Y

STIr
ov--4--~I-..I

n---4---~-;....-_r-----;....~-----~

roi
OV

Y+
OUTPUT

VOL

TL/F/S246-8

Switching Time Test Circuits
5Y

5Y

r---:.''':---, v+ = lOY

V+ =10V

RL=1002

RL=101K1

OUT

OUT

INPUT

J.

CL=50pF

TUF/S246-7

TUF/S248-8

'WEI - OV When lhe Input = WE2

Pulse Generator Characteristics:
Zo = 5O!I,I,= If = 5ns

FIGURE 1. DP7310/DP8310

FIGURE 2. DP7311/DP8311

3·10

r-----------------------------------------------------------------------.c
::sw
Typical Applications DPB310/11 Buffering High Current Device (Notes 1 and 2)
....
PNP High Current Driver

~

NPN High Current Driver
30V MAX.

C

V+

30V MAX

-a

~.

w
....
....

......

c

1 OF.
OUTPUTS

;g

1 OF.
OUTPUTS

....

w

o
......
C

VTL/F/5246-10

TL/F/5246-9

VMOS High Current Driver

Circuit Used to Reduce Peak
Transient Lamp Current

Yo

VB=6.3V

Ra

VB - VL)
RB= ( ~ RL

Rs

=

(-6.31--1) IBn = 95.4'" loon

1 OF.
OUTPUTS

RB

100
TLlF/5246-11
TL/F/5246-12

Eight Output/Four Output Fiber Optic LED Driver
DP8311100 mA Drivers

DP8311 Parallel Outputs (200 mAl Drivers·

v+
100mA I
MAX. t

10F.
OUTPUTS
FALLTHROUOH
MODE

V+
2DIImA I
MAX. t

Ro

Ro

~LEO

~LEOTO

1 OF 4
OUTPUTS
FALLTHROUGH
MODE

FIBER OPTIC

TO
FIBER OPTIC

TLlF/5246-13

'Parallel only adjacent outputs
TLlF/5246-14

3-11

~
....
....

........ '

~
C;
....

Typical Applications

o

(Continued)

8-Bit Level Translator-Driver
+5
v+

CO)

~

o
.....
....

,:fx

LOAD OR
OUTPUT PULL·UP

INPUT

vtc

....

. 181N" BOUTI

,...
CO)

a.
C;

Digital Controlled 256 Level
Power Supply from 1.2V to 30V

0'

•

....

A~~~~~LE

r- YaUT

REGULATORS
240

r'"

---1---ov

DP83\1

+5

~I LM117 SERIES ~

YIN _

'R

D
A
T
A

C

CUi

O~I

N~N

ito

T
R

8

P
U
T
S

o
L

B
U
S

Tl/F/5246-15

D
A
T
A

D
P
8
3
I
D
1
I
I

Jw,

SETSMAX
YaU T

D
U
T
P
U
T
S

"="

J;'lR
9IE2
'SETS YaUT

....
Tl/F/5246-16

200 mA Drive for a 4 Phase Blfllar Stepper Motor

Reading the State of the Latched Peripherals
v+

+VSTEPPER

3DV MAX.

S

DATA 8US

D
A
T

Y

A

S
T
E

I
N

OPB310

DPB310

DATA BUS
IN

OUT

M
8
U
S

S

Y ADDRESS

I7lIW

'High level Input
Voltage must not
Exceed Vee of the
DM81lS96

S
T 1I0W
E
M 1I0R

ADORESS/CE
'Parallel only
adjacent outputs

OM81LS96'
TRI·STATE
OCTAL
8UFFER

TlIF15246-17

Gi

iii

Tl/F/5246-18
Notel:Always use good Vee bypass and ground techniques to suppress transients caused by peripheral loads.
Note 2: Printed circuit board mounting is required if these devices are operated at maximum rated temperature and current (all outputs on DC).

3-12

f}1National Semiconductor

OS1631/0S3631/0S1632/0S3632/0S1633/0S36331
OS 1634/0S3634 CMOS Dual Peripheral Drivers
General Description
The DS1631 series of dual peripheral drivers was designed
to be a universal set of interface components for CMOS
circuits.
Each circuit has CMOS compatible inputs with thresholds
that track as a function of Vee (approximately 'Iz Vee>. The
inputs are PNPs providing the high impedance necessary
for interfacing with CMOS.
Ou1puts have high voltage capability, minimum breakdown
voltage is 56V at 250 I'A
The outputs are Darlington connected transistors. This allows high current operation (300 mA max) at low internal
Vee current levels since base drive for the output transistor
is obtained from the load in proportion to the required loading conditions. This is essential in order to minimize loading
on the CMOS logic supply.
Typical Vee = 5V power is 28 mW with both outputs ON.
Vee operating range is 4.5V to 15V.
The circuit also features outpu1 transistor protection ifthe
Vee supply is lost by forcing the output into the high impe-

dance OFF state with the same breakdown levels as when
Vee was applied.
Pin-outs are the same as the respective logic functions
found in the following popular series of circuits: DS75451,
DS75461. This feature allows direct conversion of present
systems to the MM74C CMOS family and DS1631 series
circuits with great power savings.
The DS1631 series is also TIL compatible at Vee = 5V.

Features
•
•
•
•
•

CMOS compatible inputs
PNP's
High impedance inputs
56V min
High output voltage breakdown
300 mA max
High output current capability
Same pin-outs and logic functions as DS75451 and
DS75461 series circuits
• Low Vee power dissipation (28 mW both outputs "ON"
at 5V)

Connection Diagrams (Dual-In-Line and Metal Can Packages)
Vee

12

A2

A'

81

Xf

X2

Ycc

GND

AliI

TUF/5816-1

Top View
Order Number DS1631J-8
or DS3631N

GND

XI

TL/F/5816-2

6NO

Top View
Top View
Order Number DS1632J-8
Order Number DS1633J-8
or DS3632N
or DS3633N
See NS Package Number J08A or N08E

U

AI

AI

.,

XI

•••

Top View

(Pin 4 is electrically connected to the
case.)

(Pin 4 is electrically connected to the
case.)

(Pin 4 is electrically connected to the
case.)

Order Number DS1632H
Order Number DS1633H
See NS Package Number H08C
3-13

GND

Top View
Order Number DS1634J-8
or DS3634N

TUF/5816-7

Top View

XI

TL/F/5816-4

GND

TL/F/5816-6

Top View

Order Number DS1631H

Vee

TL/F/5816-3

G.D

TL/F/5816-5

ll2A2X2

TL/F/5616-8

Top View
(Pin 4 is electrically connected to the

case.)

Order Number DS1634H

Absolute Maximum Ratings

Operating Conditions

(Note 1)
If Military/Aerospace specified devices are required.,
please contact the National Semiconductor Sales
Offlce/Olstributors for availability and specifications.
Supply Voltage
Voltage at Inputs

Supply Voltage, Vee
OS1631/0S1632/
OS1633/0S1634

16V
··-0.3VtoVee +"().3V

Output Voltage

bS3631 10536321
OS3633/0S3634

S6V

Storage Temperature Range

-6S'C to + 1SO"C

Maximum Power Dissipation' at 2S'C
Cavity Package
1133mW
Molded Package
1022mW
TO-S Package
787mW
Lead Temperature (Soldering, 4 sec.
260"C
~Derate cavity package 7.6 mwrc ·above 25"C; derate molded package
B.2.mwrc above 25'C; derate T0-5 package 5.2 mwrc above 25'C.

Temperature, T A
OS1631/0S1632(
OS1633/0S1634

Max

4.S

1S

V

4.7S

1S

V

-l)S

+12S

'C

0

+70

'C

OS3631 10536321
OS3633/0S3834

Electrical Characteristics (Notes 2 and 3)
Symbol

I

Parameter

ALL CIRCUITS
VIH

VIL

Logical "1" Input Voltage

Logical "0" Input Voltage

I

(Figure 1)-

Units

I Min I Typ I Max IUnits

Conditions .

(Figure 1)

.'

Min,

Vee = SV.

3.S

2.S

V

Vee = 10V

8.0

S

V

Vee = 1SV

12.S

7.S

V

Vee = SV

2.S

1.S

V

Vee = 10V

S.S

2.0

V

:=

7.S

2.S

V

IIH

Logical "1" Input Current

Vee = 1SV, VIN = 1SV, (Figure2j

0.1

10

/J- A

IlL

Logical "0" Input Current

VIN = O.4V, (Figure 3)

Vee = SV

-SO

-120

/J- A

Vee = 1SV

"':200

-360

/J- A
V

Vee

1SV

VOH

Output Breakdown Voltage Vee;=; 1SV, IOH = 2S0 /J-A, (F/{Jure 1)

VOL

Output Low Voltage

S6

6S

Vee = Min, (Figure 1),
OS1631, OS1632,
IOL = 100 mA
OS1633,OS1634
IOL= 300mA

0.8S

1.1

V

1.1

1.4

V

Vee = Min, (Figure 1),
OS3631, OS3632,
OS3633, OS3634

IOL = 100 mA

0.8S

1.0

V

IOL = 300mA

1.1

1.3

V

VIN = OV, (Figure 4)

Vee = SV

Output Low

7

11

mA

Vee = 1SV

Both Drivers

14

20

mA

Vee = SV, VIN = SV

Output High

2

3

mA

7.S

10

mA

OS16311053631
lee(o)

Supply Currents

(Figure 4)

lee(1)

.'

Vee = 1SV, VIN ",,'1SV Both Drivers

FlL =

tpD1

Propa.gation to "1"

Vee = SV, TA = 2S'C, CL = 1S pF,
(Figure 5)

SOO, VL = 10V,

tpDO

Propagation to "0"

Vee = SV, TA ~ 2S'C, CL = 1S pF, RL = SOO, VL = 10V,
(Figure 5)

SOO

ns

7S0

ns

OS1632/0S3632
lee(o)

Supply Currents

8

12

mA

18

23

mA

2.S

3.S

mA

Vee = 1SV

9

14

mA

Vee = SV,TA = 2S~C, CL = 1S pF, RL = SOO, VL = 10V,.
(Figure 5)

SOO

ns

7S0

ns

(Figure'4)

Vee = SV, VIN = Sv. '
Vee = 1SV, VIN

VIN = OV, (Figure 4)

lee(1)
tpD1

Propagation to "1 ",

tpDo

' Propagation to "0"

Vee = SV

=;'

Output Low

1SV
Output High

Vee = SV, TA = 2S'C, CL = 1S pF, RL = SOO,''VL = 1OV,

(Figure$)

:

3-14

Electrical Characteristics (Notes 2 and 3) (Continued)
Symbol

I

Parameter

I

I Min I Typ I Max I Units

Conditions

OS1633/083633
lee(o)

8upply Currents

VIN = OV, (Figure 4)

Output Low

Vee =5V
Vee = 15V

(Figure 4)

lee(l)

Output High

Vee = 5V, VIN = 5V
Vee = 15V, VIN = 15V

7.5

12

16

23

2

4

7.2

15

rnA
rnA
rnA
rnA

tpOl

Propagation to "1"

Vee = 5V, TA = 25°C, CL = 15 pF, RL = 50n, VL = 10V,
(Figure 5)

500

ns

tpDO

Propagation to "0"

Vee = 5V, TA = 25°C, CL = 15pF, RL = 50n, VL = 10V,
(Figure 5)

750

ns

(Figure 4)

7.5

12

18

23

OS1634/083634
leelO)

8upply Currents

Output Low

Vee = 5V, VIN = 5V
Vee = 15V, VIN = 15V

VIN = OV, (Figure 4J

leC(l)
tpOl

Propagation to "1"

Output High

3

5

Vee = 15V

11

18

Vee = 5V, TA = 25°C,CL = 15 pF, RL = 50n, VL = 10V,
(Figure 5)

500

Vee = 5V

rnA
rnA
rnA
rnA
ns

Propagation to "0"

Vee = 5V, TA = 25°C, CL = 15pF, RL = 50n, VL = 10V,
750
ns
(Figure 5)
Note 1: "Absolute Maximum Ratings" are those values beyond which tha safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant 10 imply that the devices should be operated at thase limits. The table of "Electrical Characteristics" provides condHions for actual device
operation.
Note 2: Unless otherwise specified minImax IimHs apply across the -55"C 10 + 125"C temperature range for the DS1631, 081632, 081633 and 081634 and
across the O'C 10 +70'C range for the 083631, 083632, 083633 and DS3634. All typical valUes are forTA = 25°C.
Note 3: All currents into device pins shown as posHive, out of device pins as negative, all voltages referenced 10 ground unless otherwiss noted. All values shown
as max or min on absolute value basis.

tpoo

Test Circuits
Vee

L~
V,HO-V,L 0--

-~

SEE
TEST
TABLE

r"'" ...

B

_~

~
CIRCUIT
UNDER
TEST

Y
~

-Id

~IOL

-

"

.

Vo~

+~

-=::

~

VOH

SEE
TEST
TABLE

Input
Under
Test

Othl!f
Input

Apply

Measure

083631

VIH
VIL

VIH
Vee

IOH
IOL

VOH
VOL

083632

VIH
VIL

VIH
Vee

IOL
IOH

VOL
VOH

083633

VIH
VIL

GNO

IOH
IOL

VOH
VOL

VIH
VIL

" GNO

IOL
IOH

VOL
VOH

Circuit

083634

TL/F/5816-9

Output

VIL
VIL

Not.: Each Input is tested ssparately.
FIGURE 1. VIH, VIL, VOH, VOL

3·15

•

Test Circuits (Continued)

TL/F/5816-10

Each Input is tested ssparately.

FIGURE 2.I'H

I?~ J
r-1--- 1

Vee

'OCH

Vee

y

DPEN

~B.A

OPE
:

ICCL

v.......ri A

.1

'~B

I
I

I.

L-':'""~--I'
':" GND

.,~

. Both gates are tested

TLIF15816-11

slmUltaneo~s~.

FIGURE 4: ICC for AND and NAND Circuits .

Note A:. Each Input Is tested separately.
Note B: When testing 081633 and 081634 input not under test is grounded.
For all other circuits tt is at Vee.

FIGURE 3. I,L

Schematic Diagram (Equivalent Circuit~
r---. .--------------~~--~t__oVCC

INPUT

OUTPUT

I

LOGIC
AND LEVEL
TRANSLATION
ELE.MENTS

I

L __ .J

112 of cirouit sbown

GNO
TLlF/5816-15

3·16

Switching Time Waveforms
5.0V

INPUT

10V

~

RL = 50

053631,
053632

I

VCCi5V

I

PULSE
GENERATOR
(NOTE 11
~

OUTPUT
CIRCUIT
UNOER
TEST

X

T~

=15 pF

OTE2)

I
0S3633,
053634

GNO

I

T

--

OV

TLlF/5816-13

5.0V
INPUT

D51631
051633

w-----+~~------------------------~

i - - - - - - - - - O . I i I J . - - - - - - - -...
$ 5.0 ••

5.ov----H4~-:--------------:::::'\l
INPUT

051632
D51634
OV

VOH

-----:::::::'\1

90%

OUTPUT

VOL------~-~~---------------_4
TLlF/5816-14

Note 1: The pulse generator has the following cheracteristics: PRR

~

500 kHz. loUT'" 50n

Note 2: CL includes probe and jig capecitance

FIGURE 5. Switching Times

&I

3·17 .

~ r-------------------------------------------------------------------------------~

8

~....,...

;'.\

I 082003/089667/082004
I
~

....

tflNational Semiconductor

High Current/Voltag, Darlington Drivers

General Descriptlon

The DS2003/DS9667/DS2004 are c«;>mprised of seven high
voltage, high current NPN Darlington transistor pairs. All
units feature common emitter, open collector outputs. To
maximize their effectivene$S, tl:lese units,. contain s\,!pprllssion diodes for inductive loads and appropriate emittlilr base
resistors for leakage.
The DS2003/DS9667 has a series base resistor to .each
Darlington pair, thus allowing operation directly with TIL or
CMOS operating at supply voltages of 5.0V.

The DS2003/DS9667IDS2004' offer solutions to a great
many interface needs, inCluding solenoids, relays, lamps,
small motors, and LEDs. Applications requiring sink currents
beyond the capability of a single output may be accommodate? by paralleling the outputs.

Features

The DS2004 has an appropriate input resistor to allow direct
operation from CMOS or PMOS outputs operating from supply voltages of 6.0V to 15V.

•
•
•
•
•
•

Connection Diagram

Order Numbers

16·LeadDIP
IN A
IN B
IN C
IN D
IN [
IN

r

IN G

'-./

1

16

2

15

3
4
~

5

...
...
....
~

6

~

7

GNO.....!.

~

4141-

14

~.

12

13

~
~

10

I

9

11

Seven high. gain Darlington pairs
High output voltage (VCE = 50V)
High output current (Ic = 350 mAl
TTL, PMOS, CMOS compatible
Suppression diodes for inductive loads
Extended temperature range

JPackage
Number
J16A

N Package.
Jltumber
N16E

M Package
. Number
M16A

OS2003
OS9667

DS2003MJ
DS2003TJ
DS2003CJ
DS9667MJ
DS9667TJ
DS9667CJ

DS200.3TN
DS2003CN
DS9667TN
DS9667CN

DS2003TM
DS2003CM

OS2004

DS2004MJ
DS2004TJ
OS2004CJ

DS2004TN
DS2004CN

DS2004TM
OS2004CM

OUT A
OUT B
OUT C
OUT D
OUTE
OUTF
OUT G
COMMON

,:1

TUF/9647-1

Top View

'Ii

3-18

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature Range
Ceramic DIP
-6S·Cto +17S·C
-6S·Cto +1S0·C
Molded DIP
Operating Temperature Range
OS2003M/OS9667M
052004M
D52003T1059667T
052004T
052003C/059667C
052004C

- SS·C to
- SS·C to
-40·Cto
-40·C to

Lead Temperature
Ceramic DIP (Soldering, 60 seconds)
300"C
26S·C
Molded DIP (Soldering, 10 seconds).
Maximum Power Dissipation· a~ 2S·C
Cavity Package
2016mW
1838mW
Molded Package
S.O. Package
926mW
*Derate cavity package t 6.13 mWI'C above 25"C; derate molded DIP package 14.7 mWI'C above 25'C. Derate S.O. package 7.4 mWI'C.
Input Voltage
30V

+ 12S·C
+ 12S·C
+10S·C
+ 10S·C

SSV
6.0V
SOOmA

Output Voltage
Emitter-Base Voltage
Continuous Collector Current

O"Cto +8S'C
O"Cto +8S·C

Continuous Base Current

2SmA

Electrical Characteristics TA = 2S·C, unless otherwise specified (Note 2)
Symbol
ICEX

Parameter
Output Leakage
. Current

Conditions

II(ON)

Collector-Emitter
5aturation Voltage

Input Current

II(OFF)

Input Current
(Note 4)

VI(ON)

Input Voltage
(NoteS)

Typ

=

Max

Units

100

= 1.0V (Figure 1b)
052004
Ic = 3S0 mA, Ie = SOO p.A (Ftgure 2) (Note 3)
Ic = 200 mA, Ie = 3S0 p.A (Figure 2)
Ic = 100 mA, Ie = 2S0 p.A (Figure 2)
VI = 3.8SV (Figure 3)
052003/059667
052004
VI = S.OV (Agure 3)
VI = 12V (Figure 3)
TA = 8S·C for Commercial
Ic = SOO p.A (Figure 4)
VCE = 2.0V, Ic = 200 mA (Figure 5)
052003/059667
VCE = 2.0V, Ic = 2S0 mA (Figure 5)
VCE = 2.0V, Ic = 300 mA (Figure 5)
052004
VCE = 2.0V,lc = 12S mA (Figure 5)
VCE = 2.0V, Ic = 200 mA (Figure 5)
VCE = 2.0V, Ic = 27S mA (Figure 5)
VCE = 2.0V,lc = 3S0 mA (Figure 5)
VCE

VCE(Sat)

Min

TA = 8S·C for Commercial
VCE = SOV (Figure 1a)

p.A

SOV, VI

SOO

SO

1.2S

1.6

1.1

1.3

0.9

1.1

0.93

1.3S

0.3S

O.S

1.0

1.4S

100

V

mA

p.A
2.4
2.7
3.0

V

S.O
6.0
7.0
8.0

CI

Input Capacitance

1S

30

pF

tpLH

Turn-On Delay

O.S VI to O.S Vo

1.0

p.s

tpHL

Turn-Off Delay

O.S VI to O.S Vo

1.0

p.s

IR

Clamp Diode
Leakage Current

VR

SO
100

p.A
p.A

=

SOV (Agure 6)

TA
TA

=
=

2S·C
8S·C

1.7
Clamp Diode
IF = 3S0 mA (Figure 7)
2.0
V
Forward Voltage
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at thesa limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: All limits apply to the complete Darlington series excapt as specHied for a single device type.
Note 3: Under normal oparating condHions thesa units will sustain 350 rnA per output with VCE (Sat) = 1.6V at 70'C with a pulsa width of 20 ms and a duty cycle of
30%.
Note 4: The II(OFF) current IimH guaranteed against partial turn-on of the output.
Note 5: The VI(ON) voltage limit guarantees a minimum output sink current per the specHied test conditions.

VF

3-19

Typical Performance Characteristics

.

,

I

,

Collector Curre'nt vs
Saturation Voltage
800
E

,

iB

E

,

I

~

~

«

600

f
TYPICAL
(SINGLE DEVICE)

200

I

"

0
0.5

0

I,

TYPICAL

~

,
/

./ UNIT

~:::

1.5

'/

SATURATION VOLTAGE - V

.,

E

2.0

1.5

iB

'/ "
.. ..
..;

MAX

1.0

,

.. .

"..

0.5""""

....
TYP

~

~
~
~

0
5.0 6.0

7.0

8.0

9.0

10

INPUT VOLTAGE - V

11

L'
,

1.0

I

0.5

#

400

600

2.0 3.0

INPUT CURRENT - )J.A

Ds2004
Input Current vs
Input Voltage

12

~

200

NUMBER OF
OUTPUTS
CONDUCTING
SIMULTANEOUSLY
TA = 70 0 C

"

I

100
20

I I
40

~

"

60

DUTY CYCLE - "

\\ ~\ \ \
\~\ r'\

2
;

\ ~ \. ~ '3 i'
} X l'- i'

300

300

r-.. ......

r--. ......

80

5.0

6.0

7.0

8.0

9.0

100

.:

Peak Collector Current vs
Duty Cycle and Number of
Outputs (Ceramic Peckage)
400

\\ l\ \.

4.0

INPUT VOLTAGE - V

Peak Collector Current vs
Duty Cycle and Number of
Outputs (Molded Package)
400

,'"

/

0

200

0

1.5

i

/

V

I

8

0
1.0

V

I
100

~B

,

/

I

,200

«

2.0

E

/

I

,

I J'
MAX/ TYP,

MAX/

300

§

-:.. .,'

I

2.5

I

(2 PARAllELED DEVICES)'"

400

Collector Current vs
Input Current
400

~YPICA~_----j -

«

082003/089667
Input Current vs'
Input Voltage

1

....

~\\ ~~ 2 \
~
200 NUMBER ;\t\ ~'\.

""

OF OUTPUTS\~
CONDUCTING
SIMULTANEOUSLY"~ :::---...
100 TA = 70°C
I

~

0

20

40

60

80

100

DUTY CYCLE - "

TL/F/9647-6

3-20

c

tJ)
N

Equivalent Circuits

(:)

OS2004

.......--COMMON

052003/059667

r---~~~----O~

2.7k.o.
IN ---J\M......---I

COMMON
OUT

10.5 kn

IN

---'W_.....--!

(:)
Co)

.......
C

tJ)
CD
G)
G)

...,
.......
cen

N

g

oIiIo
TL/F/9647-5

TUF/9647-3

Test Circuits
OPEN +50V

OPEN +50V

OPEN

OPEN

TL/F/9647-7

TL/F/9647-8

FIGURE 18

FIGURE 1b

TLlF/9647-9

FIGURE 2
OPEN

OPEN +50V

OPEN

.>(:>-......-- OPEN

TLlF/9647-11

TL/F/9647-10

TUF/9647-12

FIGURE 4

FIGURE 3

FIGURE 5
+50V

OPEN
OPEN
TUF/9647-14

FIGURE 7
TUF/9647-13

FIGURE 6

•
3-21

Typical Applications
Buff~r

for Higher Current Loads

v1

V2

16
2

15
14

3
4
5

13

052003/
059667

12

6

11

7

10

8

9

TTl
OUll'UT
TUF/9647-16

TTL to load,

VI
16

Tl/F/9647-17

3·22

tflNational Semiconductor

053658 Quad High Current Peripheral Driver
General Description
The OS3658 quad peripheral driver is designed for those
applications where low operating power, high breakdown
voltage, high output current and low output ON voltage are
required. A unique input circuit combines TTL compatibility
with high impedance. In fact, its extreme low input current
allows it to be driven directly by a CMOS device.
The outputs are capable of sinking 600 mA each and offer a
70V breakdown. However, for inductive loads the output
should be clamped to 35V or less to avoid latch-up during
turn off (inductive fly back protection-refer AN-213). An onchip clamp diode capable of handling BOO mA is provided at
each output for this purpose. In addition, the OS3658 incor_porates Circuitry that guarantees glitch-free power up or
down operation and a fail-safe feature which puts the output
in a high impedance state when the input is open.
The molded package is specifically constructed to allow increased power diSSipation over conventional packages. The
four ground pins are directly connected to the device chip
with a special copper lead frame. When the quad driver is
soldered into a PC board, the power rating of the device
improves significantly.

Applications
•
•
•
•
•
•

Relay drivers
'
Lamp drivers
Solenoid drivers
Hammer drivers
Stepping motor drivers
Triac drivers

Connection Diagram

•
•
•
•

LED drivers
High current, high voltage drivers
Level translators
Fiber optic LED drivers

Features
•
•
•
•
•

•
•
•
•
•
•
•
•
..
•
•
•

Single saturated transistor outputs
Low standby power, 10 mW typical
High impedance TTL compatible inputs
Outputs may be tied together for increased current capacity
High output current
600 mA per output
2.4A per package
No output latch-up at 35V
Low output ON voltage (350 mV typ @ 600 mAl
High breakdown voltage (70V)
Open collector outputs
Output clamp diodes for inductive fly back protection
NPN inputs for minimal input currents (1 pA typical)
Low operating power
Standard 5V power supply
Power up/down protection
Failsafe operation
2W power package
Pin-for-pin compatible with SN75437

Truth Table

Dual-In-Llne Package
INA

INB

EN

GND

UNO

-Vee

INC

IND

IN

EN

OUT

H
L
H
L

H
H
L
L

L
Z
Z
Z

= High state .
= Low state
Z = High impedance state

H
L

OUT A CLAMP lOUT B

aNO

GND

OUT C CLAMP 2 OUT D
TL/F/5819-1

Top View
Order Number DS3658N
See NS Package Number N16E

3-23

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V

Supply Voltage
Ambient Temperature

..

Input Voltage
Output Voltage
Output Current

Continuous Power Dissipation
@ 25°C Free-Air (Note 5)
Storage Temperature Range

Min
4.75
0

Max
5.25
70

Units
V
°C

15V
70V
1.5A
2075rnW
- S5°C to + 1500C

Lead Temperature (Soldering, 4 sec.)

2S00C

Electrical Characteristics (Notes 2 ar'ld 3)
Symbol

Parameter

Min

Conditions

VIH

Input High Voltage

VIL

Input Low Voltage

IIH

Input High Current

VIN = 5.25V,Vcc = 5.25V

IlL

Input Low Current

VIN = 0.4V

Typ

Max

2.0

Units

V
0.8

V

10

p.A

±10

p.A

1.,0.

>••

VIK

Input Clamp Voltage·

.11 = -12 rnA

-0.8

-1.5

V

VOL

Output Low Voltage

IL = 300mA

0.2

0.4

V

IL = SOO rnA (Note 4)

0.35

Vce·= 70V, VIN = 0.8V

0.7

V

100

p.A

ICEX

Output leakage CUrrent

VF

Diode Forward Voltage

IF= OOOmA

IR

Diode Leakage Current

VR = 70V

Icc

Supply Current

All Inputs High

SO

85

mA

All Inputs Low

2

4

mA

Max.

Units

1.0

1.S

V

100

p.A

Switching Characteristics (Note 2)
Symbol

tpHL

Parameter

Conditions

Min

Tum On Delay

RL = 600, VL = 30V

.Typ
22S

500

ns

2430
Turn Off Delay
ns
RL = son, VL = 30V
8000
tpLH
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated atlhsse limits. The table of "Electrical Characteristics" provides conditions for actual devica operation.
Note 2: Unless otherwise specHled, minImax limits apply across Ihs O'C to +70'C temperature range and the 4.75V to 5.25V power supply range. All typical
values are for TA - 25'C and Vee = 5.0V.
Note 3: All currents into device pine are ahown as posijive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute value baSis.
Note 4: All sections of this quad circuij may conduct rated current simultaneously; however, power dissipatioljl averaged over a short interval of time must fall within
specified continuous dissipation ratings.
Note 5: For operation over 25'C free-ainemperature, derate linearly to 1328 mW @ 70'C @ the rate of 16.6 mW/'C.

3-24

AC Test Circuit

Switching Waveforms
Vee

30V

3V
INPUT

::{.1.5V
OV

30V
OUTPUT

OUT

VOL
3OpF*

~

10%
TLlF/5B19-3

-::4,5, 12, 131
TL/F/5B19-2

*Includes probe and jig capacitance

Typical Applications
Stepping Motor Driver

Lamp Driver

5V

r-

tl1

5V

V+

Ll*

~
2

......

3

::>

9, la, 15, 16

...~

DATA BUS

..

r---

~

!! 9,10,15,16

DS36S8

)

r

L3*

CONTROL

~

LEVELS

~
Lf

DS36S8

7

L4*

14

EN

....

~

14

--+

J.!' 5, 12, 13

EN

4,5,12,13
TLlF/5B19-4
*L1, l2. L3, L4 are the windings of a bifilar stepping motor

TLlF/5819-5

"VMOTOR is the supply voltage of the molar

3-25

DS3668 'Quad
Fault Protected Peripheral Driver
,
'

General Descr.iption

Applications

The OS3668 quad peripheral driver is designed for those
applications where low operating power, high breakdown
voltage, high output current and low output ON voltage are
required. Unlike most peripheral drivers available, a unique
fault protection circuit is incorporated on each output. When
the load current exceeds 1.0A (approximately) on any output for more than a built-in delay time, nominally 12 ,...s, that
output will be shut off by its protection circuitry with no effect
on other outputs. This condition will prevail until that protection circuitry is reset by toggling the corresponding input or
the enable pin low for at least 1.0 ,...S. This built-in delay is
provided to ensure that the protection circuitry is not triggered by tum-on surge currents associated with certain
kinds of loads.
The OS3668's inputs combine TTL compatibility with high
input impedance. In fact, its extreme low input current allows it to be driven directly by a MOS device. The outputs
are capable of sinking 600 rnA ea9h and offer a 70V breakdown. However, for inductive loads the output should be
clamped to 35V, or less to avoid latch up during tum off
(inductive' fly·back protection - refer AN-213). An on-chip
clamp didcle capable of handling 800 rnA is provided at
each output for this pulp'ose. In addition, the OS3668 incorporates qircuitrY ,that guarantees glitch-free power up or
down operation and a fail-safe feature which puts, the output
in a high impedance state when the input is open.

•
•
•
•
•
•
•
•
•

The molded package is specifically constructed to allow increased power dissipation over conventioryal packages. The
four ground pins are directly connected to the device chip
with a special copper lead frame. When the quad driver is
soldered into a PC board, the power rating of the device
improves significantly.

Connection Diagram
INA

INB

Relay drivers
Solenoid drivers
Hammer drivers
Stepping motor driverS
Triac drivers
LED drivers
High current, high voltage drivers
Level translators
Fiber optiC LED drivers

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Output fault protection
High impedance TTL compatible inputs
High output current-600 rnA per output
No output latch-up at 35V
Low output ON VOltage (550 mV typ @ 600 rnA)
High breakdown voltage (70V)
Open collector outputs
Output clamp diodes for inductive fly-back protection
NPN inputs for minimal input currents (1 ,...A typical)
Low operating power
Standard 5V power supply ,
Power up/down protection,
Fail-safe operation
2W power package
Pin-for·pin compatible with SN75437

Truth Table

Dual·ln·Llne Package
EN
aND
aND
Ycc

INC

IND

I','

OUT A CLAMP 1 OUT B

UND

BND

OUT C CLAMP 2 OUT D

IN

EN

OUT

H
L
H

H
H
L

L

L

L
Z
Z
Z

H

~

High state

L

~

Low state

Z

= High impedance state
Order Number DS3668N
See NS Package Number N16E

TL/F/5225-1

Top View

3-26

Absolute Maximum Ratings (Note 1)

Operating Conditions

If MllltarylAerospace specified devices are required,
please contact the National Semiconductor Sales
OfflcelDlstrlbutors for availability and specifications.
Supply Voltage
7.0V

Supply Voltage

Input Voltage

15V

Output Voltage

70V

Continuous Power Dissipation
@ 25'C Free-Air(5)
Storage Temperature Range

Min
4.75

Max
5.25

0

70

Typ

Max

Units

0.8

V

20

!,-A

±10

!,-A

Ambient Temperature

Units
V
'C

2075mW
- 65'C to

+ 150'C

Lead Temperature (Soldering, 4 seconds)

260

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min
2.0

VIH

Input High Voltage

VIL

Input Low Voltage

V

IIH

Input High Current

VIN = 5.25V, Vcc = 5.25V

IlL

Input Low Current

VIN = 0.4V

VIK

Input Clamp Voltage

11= -12mA

-0.8

-1.5

V

VOL

Output Low Voltage

IL = 300mA

0.2

0.7

V

IL = 600 mA (Note 4)

0.55

1.5

V

100

!,-A

1.0

ICEX

Output Leakage Current

VCE = 70V, VIN = 0.8V

VF

Diode Forward Voltage

IF = 800mA

IR

Diode Leakage Current

VR = 70V

Icc

Supply Current

Allinput5 High

62

All Inputs Low

20

ITH

Protection Circuit
Threshold Current

1.2

1.6

V

100

!,-A

80

mA
mA

1

1.4

A

Typ

Max

Units

Switching Characteristics (Note 2)
Symbol

Parameter

Conditions

Min

tpHL

Turn On Delay

RL = 60n, VL = 30V

0.3

1.0

!,-5

tpLH

Turn Off Delay

RL = 60n, VL = 30V

2

10.0

!,-5

tFZ

Protection Enable Delay
(after Detection of Fault)

6

12

!,-5

Input Low Time for
1.0
!,-5
Protection Circuit Reset
Note 1: "Absolute Maximum Ratings" are those valuas beyond which tha safety of the devica cannot be guaranteed. They are not meant to imply that the devica
should be operated at these IimHs. The table of "Electrical Characteristics" provides condHions for actual device operation.
Nota 2: Unless otharwise specified, minImax limns apply across the O"C to +70"C temperature range and the 4.75V to 5.25V power supply range. All typical
values are for TA = 25"C and Vee = 5.0V.
Note 3: All currents into devica pins ere shown as posHlve; all currents out of devica pins are sl)own as negative; all voHages are referencad to ground, unless
otharwise specmed. All values shown as max or min are so classified on absolute value basis.
Nota 4: All sections of this quad eireuH may conduct rated current simuHaneously; however, power dissipation averaged over a short interval of time must fall within
specified continuous dissipation ratings.
Nota 5: For operation over 25"C free-air temperature, derate linearly to 1328 mW @ 70"C @ the rate of 16.6 mWrC.
tRL

3-27

AC Test Circuit

Switching Waveforms
Vee

30V
3V

INPUT

OUTPUT

•

ov 4'.OV

:~
~
TLlF/5225-3

TlIF/5225-2
'Includes probe and Jig capacitance.

Typical Application
Stepping Motor Driver
¥MOTOR**

5V

...

tll
1

~

2

....
I
::>

~

3

9, 10, 1&, 1& L
DATA BUS

,

-

DS3888

L3*

6

~

7

14

8

....

-

...J!.

~

EN

-

.J!' 5, 12, 13
'L1, L2, L3, L4 are the windings of a bifllar stapping motor.

TLlF/5225-4

"VMOTOR Is the supply voltage of the motor.

Protection Circuit Block Diagram
OUTPUT

INPUT

ENABLE

CURRENT
SENSING
CIRCUITRY

TLlF/5225-5

3-28

t!lNational Semiconductor

DS3680 Quad Negative Voltage Relay Driver
General Description
The DS;3680 is a quad high voltage negative relay driver
designed to operate over wide ranges of supply voltage,
common-mode voltage, and ambient temperature, with
50 rnA sink capability. These drivers are intended for switching the ground end of loads which are directly connected to
the negative supply, such as in telephone relay systems.
Since there may be considerable noise and IR drop between logic ground and negative supply ground in many applications, these drivers are deSigned to operate with a high
common-mode range (± 20V referenced to negative supply
ground). Each driver has a common-mode range separate
from the other drivers in the package, which pemits input
signals from more than one element of the system.

The driver outputs incorporate transient suppression clamp
networks, which eliminate the need for external networks
when used in applications of switching inductive loads. A
fail-safe feature is incorporated to insure that, if the + IN
input or both inputs are open, the driver will be OFF.

Features
•
•
•
•
•
•
•

-10V to - 60V operation
Quad 50 rnA sink capability
TTL/LS/COMS or voltage comparator input
High input common-mode voltage rangE'
Very low input current
Fail-safe disconnect feature
Built-in output clamp diode

With low differential input current requirements (typically
100 /LA), these drivers are compatible with TTL, LS and
CMOS logiC. Differential inputs permit either inverting or
non-inverting operation.

Connection Diagram

Logic Diagram

Dual-In-Line Package

~GNO

+A IN...!...
- AIN

2

r1LOUT A

-8 IN....!

r1LOUT 8

+8 IN.:....!

rlLOUT C

+c IN.2..

rlLOUT D

-C IN-i

rL-vEr-

~+OIN

-0 IN...!.

TLiF 15821-1

Top View
Order Number DS3680J, DS3680M or DS3680N
See NS Package Number J14A, M14A, N14A

TLlF/5821-2

Truth Table
Differentla,'riputs

Outputs
On
Off

Open

Off

3-29

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-70V
Supply Voltage (GNDto VEE-, and Any Pin)
Positive Input Voltage (Input to GND) •.
20V
-5V
Negative Input Voltage (Input to VEE-)
Differential Voltage (+ IN td -IN)
±20V
Inductive Load
'-L:S:,5h
Il5;:50mA
-100mA
Output Current',
Storage Temperature
-65'C to + 150'C
Maximum Power Dissipation· at 25'C
Cavity Package
1433mW
1398mW
Molded Dip Package
SO Package
1002mW
Lead Temperature (Soldering, 4 seconds)
2SOOC
• Derate cavity package 9.6 mWI'C aboVe 25'C; derate molded dip peckage 11.2 mW/'C aboVe 25"C; derate SO peckage 8.02 mWI'C aboVe
25'C.

Recommended Operating
ConditiOns

' ,

Supply Voltage (GND to VEE -)
Input Voltage (Input to GND)
Logic ON Voltage ( :\- IN)
Referenced to -IN
Logic OFF Voltage (-I' IN)
Referenced to -IN
Temperature Range

Min
-10
-20,

Max
-60
20

Units
V
V

2

20

V

-20
,-25

0.8
+85

V
'C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

,Max

Units

2.0

1.3
1.3

0;8

V

40
375

100
1000

jJ.A
/LA

-5
-100

p.A
p.A

VIH

Logic "1" Input Voltage

Vil

Logic "0" Input Voll/ige

IINH

Logic "1" Input Current

VIN = 2V
VIN = 7V

IINL

Logic "0" Input Current

VIN = 0.4V
VIN = -7V

-0.01
-1

VOL

Output ON Voltage

IOl = 50mA

-1.6

-2.1

V

-100

/LA

V

IOFF

Output Leakage

VOUT = VEE-

-2

IFS

Fail-Safe Output Leakage

VOUT = VEE(Inputs Open)

-2

-100

p.A

IlC

Output Clamp Leakage Current

VOUT = GND

2

100

p.A

Vc

Output Clamp Voltage

ICLAMP = - 50 mA
Referenced to VEE-

-2

-1.2

V

Vp

Positive Output Clamp Voltage

ICLAMP = 50 mA
Referenced toGND

0.9

1.2

V

IEE(ON)

ON Supply Current

All Drivers ON

-2

-4.4

mA

IEE(OFF)

OFF Supply Current

All Drivers OFF

-1

' ":100

p.A

tpD(ON)

Propagation Delay to Driver ON

L =1h, Rl= 1k,
VIN =3V Pulse

1

10

,...S

L = 1h, RL = 1k,
1
10
/Ls
, VIN = 3V Pulse
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range".
they are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
tpD(OFF)

Propagation Delay to Driver OFF

operation.

Note 2: Unless otherwisa specified. the min/max limits of the table of "Electrical Characteristics" apply wHhin the range of the table of "Operating CondHions". All
typical values are given for VEE- - 52V. and TA - 25'C.
Note 3: All current into device pins shown as positive. out of the device as negative. All voltagas are referenced to ground unless otherwisa noted.

3-30

Schematic Diagrams
15k

GND

----l
I
I

I
I

I

.....+-...~MH-OVOUT
(1/4 CIRCUIT SHOWN)
TLlF/5821-3

TL/F/5821-4

3-31

I!fINational Semiconductor
',' ""Y'"

OS55451/2/3/4, OS75451/2/3/4 Series
Dual Peripheral Drivers
General Description

Features

The 057545X series of dual peripheral drivers is a family of
versatile devices designed for lise in systems that use TTL
logic. Typical applications include high speed logic buffers,
power drivers, relay d~vers, lamp drivers, M05 drivers, bus
drivers and memory drivers.
"

•
•
•
•
•
•
•
•

The 0555451/0575451, 055545210575452, 05554531
0575453 and 055545410575454 are dual peripheral AND,
NAND, OR and NOR drivers, respectively; (positive logiC)
with the output of the logic gates internally connected to the
bases of the NPN output transistors.

300 mA output current capability
High voltage outputs
No output latch-up at 20V
High speed switching
Choice of logic function
TTL compatible diode-clampe(j inputs
Standard supply voltages
Replaces TI "A" and "8" series

Connection Diagrams (Oual-In-Line and Metal Can Packages)
Vee

az

AZ

AI

al

VI

yz

Vee

82

A2

GNO

AI

81

Y1

Y2

Vee

az

AZ

GNU

AI

al

VI

VZ

GNO

AI

al

GNO

VI

TLlF/5824-2

TL/F/5824-3

TL/F/5824-4

TLlF/5824-5

Top View
Order Number DS55451J-8,
DS75451M or DS75451N

Top View
Order Number DS55452J-8,
DS75452M or DS75452N

Top View
Order Number DS55453J-8,
DS75453M or DS75453N

TOp View
Order Number DS55454J-8,
DS75454M or DS75454N

See NS Package Numbers J08A, M08A' or N08E
'See Note 5 and Appendix E regarding S.O, package power dissipation constraints.
Vee

Vee

GND
TL/F/5824-7

TLlF/5824-6

Top View

Top View

Order Number DS55451H

Order Number DS55452H

TL/F/5824-8

Top View

(Pin 4 is in Elecbical Contact with the Case)

See NS Package Number HOSe .

3-32

Order Number DS55453H

Lead Temperature (50ldering, 4 sec.)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
5upply Voltage, {Vee> (Note 2)

7.0V

Input Voltage
Inter-Emitter Voltage (Note 3)

5.5V

30V

Output Current (Note 5)
0555451/0575451, 0555452/0575452,
0555453/0575453,055545410575454

300mA

260"C

Operating Conditions
Min
Max
Units
5upplyVoitage, {Vee>
055545X
4.5
5.5
V
057545X
4.75
5.25
V
Temperature, (Till
·C
-55
055545X
+125
·C
057545X
0
+70
t Derate cavity package 7.3 mW fOC above 25°C; derate molded package
7.7 mWfOC above 25°C; derate TO·S package 5.1 mW/oC above 2SOC;
derate SO package 7.56 mWfOC above 25"C.

5.5V

Output Voltage (Note 4)
OS55451 10575451, 0555452/0S75452,
OS55453/0S75453,OS55454/0575454

0575451/2/3/4 Maximum Power (Note 5)
Oissipation t at 25·C
Cavity Package
Molded OIP Package
TO-5 Package
50 Package

-65·C to + 150"C

5torage Temperature Range

Absolute Maximum Ratings (Note 1)

1090mW
957mW
760mW
632mW

Electrical Characteristics
0555451/0575451, 0555452/0575452, 0555453/0575453, 055545410575454 (Notes 6 and 7)
Symbol

Parameter

VIH

High-Level Input Voltage

Vil

Low-Level Input Voltage

VI

Input Clamp Voltage

VOL

Low-Level Output Voltage

Conditions

. Vee

=

Min,ll

Vee = Min,
(Figure 7)

=

=

0.8V

IOl

=

2V

IOl

IOL
Vee = Min,
(Figure 7)

II

Input Current at Maximum
Input Voltage

Vee

=

Units

0.8

V

V

-1.5

V

0555451, 0555453

0.25

0.5

V

0575451, 0575453

0.25

0.4

V

0555451,0555453

0.5

0.8

V

0575451, 0575453

0.5

0.7

V

0555452, 0555454

0.25

0.5

V

0575452, 0575454

0.25

0.4

V

0555452, 0555454

0.5

0.8

V

0575452, 0575454

0.5

0.7

V

300

/LA

0575451,0575453

100

0555452, 0555454

300

0575452, 0575454

100

!LA
!LA
!LA

1

mA

-12 mA

Vil

VIH

High-Level Output Current

Max

2

IOl

IOH

Min Typ

(Figure 7)

VOH

=

=
=
=
=

100 mA

300mA

100 mA

300mA

30V VIH

=

2V

Vil

=

0.8V

0555451,0555453

Max, VI = 5.5V, (Figure 9)

40

!LA

-1.6

mA

7

11

mA

11

14

mA

11

mA

13

17

mA

52

65

mA

71

mA

IIH

High-Level Input Current

Vee = Max, VI = 2.4V, (Figure 9)

IlL

Low-Level Input Current

Vee

leCH

5upply Current, Outputs High Vee = Max, VI = 5V
(Figure 10)
VI = OV

0555451/0575451
0555452/0575452

VI = 5V

0555453/0575453

8

=
=
=
=

OV

0555454/0575454

OV

0555451/0575451

5V

0555452/0575452

56

OV

0555453/0575453

54

68

mA

VI = 5V

0555454/0575454

61

79

mA

=

VI
leel

5upply Current, Outputs Low

-1

Max, VI = 0.4V, (Figure 8)

Vee = Max, VI
(Figure 10)
VI
VI

3-33

•

I"',

Switching Characteristics

0555451/0575451, 0555452/0575452, 0555453/0575453, 055545410575454 (Vee ='5V, TA
Symbol
tpLH

Parameter

.'

Propagation Delay Time, Low-to-High
Level Output

CL = 15 pF, RL = 500,
10::::: 200 mA, (Figure 14)

Propagation Oelay Time, High-to-Low CL = 15 pF, RL = 500,
Level Output
10'::::: 200 mA, (Figure 14)

25°C)

'"

Typ' M~

"Min

U,nlts

0555451/0575451

18

25

0555452/0575452

26

35

ns

18 ' 25

' ns

0555453/0575453

tpHL

=

CondItions

oil,'

,',

ns

0555454/0575454

27

~5"

0555451/D5754S1

18

25

ns

0555452/0575452

24

35

ns

0555453/0875453

16

25

ns

055545410575454

24

35

ns

5

8

ns

7

12

ns

tTLH

Transition Time, Low-to-High Level
Output

CL = 15 pF, RL
(Figure 14)

=

500,10 ::::: 200mA,

trHL

Transition Time, High-to-Low Level
Output

CL = 15 pF, RL
(Figure 14)

=

500,10 ::::: 200 mA,

VOH

High-Level Output Voltage after
5witching

Vs = 20V, 10 ::::: 300 mA, (Figure 15)

Vs - 6.5

"

ns

mV

"

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the d~ce cannot be gU,arsnteed, Except for "Operating Temperature Range"
they are not meant to imply that the devices should be opsrated at these limits. The table of "Electrical Characteristics" provides condHions for actual device
opsratlon. '
"
Note 2: Voltage values are with respect to network ground terminal unless otherwise specified,
Note' 3: The voltage between two emitters of a multiple-emitter transistor.

,

Nota 4: The maximum voltage which should be spplied to any output when H is in the, "OFF" state, ,

,

:, '

Nota 5: Eloth halves of these dual circuHs may conduct rated current simultaneously; however, power dissipstio~ averaged over,a, shOl'! time intarval must fall within
the continuous disslpation rating,
'
Nota ~: U~less otherwise specified minImax IimHs apply across the - 55'C to + 1'25-C temperature ra"ge fOr the OS55450 series and across the O'C to + 70'C
r~e for the OS7545X series. All typicals are'given for Vee = +5V and TA = 25"C.
Nota 7: All currents into device pins shOWl' as posHiv~, out of device pinS as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute ~ue baSis.

,

",

,

"

"

,,'

,',
,",

j

,

00

:

3-34

I

Truth Tables (H =

high level. L = low level)

OS55453/0S75453

OS55451/0S75451
A

B

L
L
H
H

L
H
L
H

Y
. L (ON State)
L (ON State)
L (ON State)
H (OFF State)

A

B

y

L
L
H
H

L
H
L
H

L(ON State)
H (OFF State)
H (OFF State)
H (OFF State)

OS55452/DS75452

OS55454/0S75454

A

B

Y

A

B

Y

L
L
H
H

L
H
L
H

H (OFF State)
H (OFF State)
H (OFF State)
L(ONState)

L
L
H
H

L
H
L
H

H (OFF State)
L(ON State)
L (ON State)
L (ON State)

Schematic Diagrams
DS55451/DS75451

1-...... _ _...._

........._

OS55453/0S75453

~""'--""----""_"""-O

....-0 •••

...

TL/F/5824-13

TUF/5824-11

Resistor ~Iues shown are nominal.

Resistor values shown are nominal.

OS55452/0S75452

OS55454/0S75454

r - -......---.-~r-----ov'"

~""'--""'-""'-

__""'' ' ' ' '...-..oG••

L -.....- -....- - - -........_~~...._o •••

TUF/5824-14

TUF/5824-12

Resistor values shown are nominal.

Resistor values shown are nominal.

•
3-35

~

1ft

~

1ft

.....
~

r---------------------------------------------------------------------------------,
DC Test Circuits
Vee

~

V,.

~
~

1ft
~

TL/F/5824-15

~
......
....

TUF/5824-17

TL/F/582~-16

Both inputs are tested simultaneously.

FIGURE 1. VIH. VOL

Each input is tested separately.

Each input is tested separately.

FIGURE 2. Vil. VOH

FIGURE 3. Vb III

1ft

~

v""

~

V,n;;;=J-.......

Vee

OPEN

V,

~

~

1ft

~
......
CO)

TUF/5824-18

TL/F/5824-19

Each input is tested separately.

Each input is tested separately.

FIGURE 4. Ib IIH

FIGURE 5. lOS

TL/F/5824-20

Both gates are lested simultaneously.

FIGURE 6. ICCH. ICCl

1ft

~

~~

Circuit
Vee

~

~..........

0855451

SEE~I""

V,.

VOlt

TEST

TABLE

0855452

:';\IOL

~

!~
TL/F/5824-21

Apply

VIH

VIH

VOH

IOH

VIL

Vee

IOL

VOL
VOL

Measure

VIH

IOL

VIL

Vee

VOH

IOH

0855453

VIH

Gnd

VOH

IOH

VIL

VIL

IoL

VOH

0855454

'VIH'

Gnd"

IOL

VOL

VIL

VIL

VOH

IOH

~

VOL

Output

Other
Input

VIH

1ft
1ft

Input
Under,
Test

FIGURE 7. VIH. VII•• 10H. VOL
Vee

4.iV

OPEN
Note A: Each input is tested separately.
Note B: When lesting 0555453/0575453,
055545410575454, input not
under test is grounded.
For all other ctrcuits it Is at 4.5V.
.

TUF/5824-22

OPEN

Each input is tested separately.

Vee

OPEN

Vee

OPEN

V,n....L...I~...

V,

Both gates are tested simultaneously.

. TUFl5824-23

FIGURE 9. 110 IIH

FIGURE 6. Vb Vil

'::"

Both gates are tested simultaneously.

TUF/5824-24

FIGURE 10. ICCH. ICCl for AND. NAND Circuits

'::"

TUF/5824-25

FIGURE 11. ICCH. ICCl for OR. NOR Circuits

3-36

AC Test Circuits and Switching Time Waveforms
INPUT

lAV

Vee

OUTPUT

5V

RL =400
"All diod•• ".IN3064

GNO

111%
INPUT

~"

CL =15pF

~(NOTE2)

':'

..

rJ"'·
911%

W

111%

OV
t.HL

~

~)L
1.5V

Note 1: The pulse generator has the following characteristics: PRR

3V

1.5V

1.5V

0.5,..

OUTPUT

TUF/5824-26

~

VOH

VOL
TUF/5824-27

1 MHz, ZOUT '" SOil.

Note 2: CL includes probe and jig capacitance.

FIGURE 12. Propagation Delay Times, Each Gate
10V

RL =50
OUTPUT

CL =15 pF

SUB

J.~'

-

':'

TL/F/5824-28

3V
INPUT
OV
~5ns

t.-J
1(111%

OUTPUT

TLlF/5824-29
Note I: The pulse generalor has the following characteristics: duty cycle,;; 1 %, loUT'" SOO.
Note 2: CL includes probe and jig capacitance.

FIGURE 13. Switching Times, Each Transistor

3·37

•

AC Test Circuits and Switching ·Tlme WavefOrms (Continued)
INPUT

IDV

Z.4V

1

...--1_00UTPUT

TLlF/5824-30

~~-----3.OV
INPUT
08654&1
08&&4&3

~~-------------~~-~--------------OV
I-------------~O

.... --------------i~

:;;&.0 ..
~~------------=~+_r_------------3.0V

1\.ll:l:.._ _ _ _ _ OV

VOH
OUTPUT
~~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _~--~--___ V~

IT1.H

tTHL

Note 1: The pulse generator has 'the following chOracteristics: PRR ~ 1.0 MHz. toUT '" 5011.
Note 2: CL includes probe and jig capacitance.

FIG!,JRE 14. Switching Times of Complete Drlv~rs

3·38

TLlF/5824-31

AC Test Circuits and Switching Time Waveforms

(Continued).

v, = ZIV

' - _....- ...-0 OUTPUT

TL/F15824-32

--j

r:S;5M

ll-:S;IOnI

== h_4O;os______:; 0%;:J:.W+_,85:"_

___
. ---:

INPUT

g:::

11~------::;ri:t-t-----=:s;-1-0

..
---3v

I.BV

~-----OV

111%

\_______r__:

OUTPUT

TL/F/5824-33

Note 1: The pulse generator has the following characteristics: PRR

= 12.5 kHz, loUT :=

50n.

Note 2: CL includes probe and jig capacitance.

FIGURE 15. Latch-UP Test of Complete Drivers

Typical Performance Characteristics
....~

'"e
!:;
0

>
z

0.6
Ie
= 10
I.
(NOTE 8)
-

0.6

0

;::

e

II:

=
le

en

0.4

TA=+7~

0.3

~

0.2

:l;

0.1

0
I-

.~
0

•

V

II:

iii

IJ

~

TA- + 26"C

r-~Air~; II
10

20

40

70 100

200

400

COLLECTOR CURRENT (rnA)
TL/F/5824-37

FIGURE 16. Transistor Collector-Emitter Saturation Voltage vs Collector Current

3-39

Typical Applications
R·

5Vo-+-Ir---~~~

_ _-t'--_ _-t"--___

rr.-,---+ { - t -......"'\

INPUT A
STROBE
INPUT B

TL/F/5824-46

'Optional keep-alive resistors maintain off-state lamp current at :::: 10% to reduce surge current.

FIGURE 17. Dual Lamp or Relay Driver

5Vo----p--,
1.

-+-.....,1----,

INPUT 0-....

}

DS15451

COMPLEMENTARY OUTPUTS FOR:
GO/NO-GO INDICATORS
MOS CLOCK DRIVERS
BIPOLAR RELAYS

4

TLlF/5824-47

FIGURE 18. Complementary Driver

3-40

Typical Applications

(Continued)

wo---~~----~~----------------------~~~--~~~

I.
TEST
"I"

l

INPUTo--o_-<)-J

0575452

390

....

TEST

310

TL/F/5824-48

FIGURE 19. TTL or DTl Positive Logic-level Detector

5Vo-~--~~----~~-----------------------,--__- - - - - - ,

0575452

311
3Ok*

470
INPUT

TL/F/5824-49

'The 1wo input resistors must be adiusted for Ihe level of MOS input.

FIGURE 20. MOS Negative Logic-level Detector

&Vo-------~----------------------_,
Ik

• __~~.() y = Ai. is

,.

V=AI'S

•

INPUT A

STROlE

05754&3

INPUT B

4

TLlF/5824-50

FIGURE 21. logic Signal Comparator
9-41

Typical Applications (Continued)
wo-------.-----------------------~
A
SIGNALS FROM}
PEAK DETECTORS

Ik

0-:.:.----+-----,

...----0 OUTPUT

OS71453

I"
TLlF/5824-51

'If inputs are unused. they should be connected to + 5V through a 1k resistor.

A

H

OUTPUT

~-------------H
TLlF/5824-62

Low output occurs only when inputs are low simultaneOusly.

FIGURE 22. In-Phase Detecto~

wo----------.----~------------------~--~
Ik

...

___-t___~~---_+----

r

Ik

-_+__oYI.Ai

5.

YI-A+B

INPUT A
INPUT B

YZ'YI.~=(A'BIC

OS75454·

Y2 =Yf+c. Ai. c

INPUT C

4

TL/F/5824-53

J:IGURE 23. Multifunction ·Logic-Signal Comparator

3·42

Typical Applications (Continued)
5Vo----------.----------------------~--_,
FROM ALARM {
TRANSDUCERS

ALARM
RELAY

0--+-....--;----..,
381

3tO

r-"L.:----1r:----t=----r,

0175454

FROM ALARM {
TRANSDUCERS

0--+-....- - - - - -.....
381

390
TL/F/5824-54

FIGURE 24. Alarm Detector

•
3·43

~

C\I

r--------------------------------------------------------------------------------,

:3~d
pNational Semiconductor
LM19211 Amp Industrial Switch
General Description

Features

The LM1921 Relay Driver incorporates an integrated power
PNP transistor as the main driving element. The advantages
of this over previous integrated circuits employing· NPN
power elements are several. Greater output voltages are
available off the same supply for driving grounded loads;
typically 4.5 volts for a 500 rnA load from a 5.0 volt supply.
The output can swing below ground potential up to 57 volts
negative with respect to the positive power supply. This can
be used to facilitate rapid decay times in inductive ·Ioads.
Also, the IC is immune to negative supply voltages or transients. The inherent Safe Operating Area of the lateral PNP
allows use of the IC as a bulb driver or for capacitive loads.
Familiar integrated circuit features such as short circuit protection and thermal shutdown are also provided. The input
voltage threshold levels are designed to be TIL, CMOS,
and LSTIL compatible over the entire operating temperature range. If several drivers are used in a system, their
inputs and! or outputs may be combined and wired together
if their supply voltages are also common.

• 1 Amp output drive
• Load connected to ground
• Low input-output voltage differential
• + 60 volt positive transient protection
• - 50 volt negative transient protection
• Automotive reverse battery protection
• Short circuit proof
• Internal thermal overload protection
• Unclamped output for fast decay times
• TIL, LSTIL, CMOS compatible input
• Plastic TO-220 package
• 100% electrical burn-in

Applications
•
•
•
•
•
•

Relays
Solenoids
Valves
Motors
Lamps
Heaters

Typical Application Circuit

VON/OFFo---~IQ~N-:---I-~5

VOLTAGE
_
OUTPUT 2 100 nF

orr
TL/H/5271-1

FIGURE 1. Test and Application Circuit

Connection Diagram
TO·Z20 5 LEAD

I~.I

I

4GROUNO
~ "'1'"
3 GROUND
2 OUTPUT (Vour)
1 SUPPLY (Vccl

Front View
Order Number LM1921T
See NS Package Number T05A

3-44

TL/H/5271-2

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Seles
Office/Distributors for availability and specifications.
Supply Voltage
Operating Range
Overvoltage Protection (100 ms)

Internally Limited

Internal Power Dissipation
Operating Temperature Range

- 40"C to + 125·C

Maximum Junction Temperature

150"C
- 65·C to + 150"C

Storage Temperature Range

4.75Vto 26V
-50Vto +60V

Lead Temp. (Soldering, 10 seconds)

230"C

Electrical Characteristics (Vcc= 12V, IOUT= 500 mA, TJ= 25·C, VON/c:wF= 2V, unless otherwise specified.)
Parameter
Supply Voltage
Operational
Survival
Transient

Conditions

Typ

100 ms, 1 % Duty Cycle

Tested Limits
(Note 1)

Design Limits
(Note 2)

Min

Max

Min

Max

4.75
-15
-50

26
60

6

24

Units

V
Voc
V

Supply Current
VON/C5FF=O
VON/OFF=2V

Input to Output
Voltage Drop

lour=OmA
IOUT=250mA
IOUT=500mA
IOUT=1A

0.6
6
285
575
1.3

IOUT=500mA
IOUT=1A

0.5
1.0

Short Circuit Current

1.4

1.5
10
350
700
1.5
0.8
1.0

Output Leakage Current

VON/~=O

ON/OFF Voltage
Threshhold

6V,;;Vcc';;24V

ON/CWf' Current

15
32

Inductive Clamp
Output Voltage

VON/~=O, lOUT = 100 mA

Fault Conditions
Output Current
ON/CWf' Floating
Ground Floating
Reverse Voltage
Reverse Transient
Overvoltage
Supply Current

Pin 5 Open
Pin 3 & Pin 4 Open
Vcc=-15V
Vcc=-50V
Vcc=+60V
Pin 1 & Pin 2 Short, No load

A
A

50

p.A

0.8

2.0

V
V

26

36

0.1

Overvoltage Shutdown
Djc
9ca

3.0

.75

1.3

Thermal Resistance
junction-case
case-ambient

V
V

2.0

6V,;;Vcc,;;24V

0.8
10

2.0

p.A

30

0.1
0.1
-0.01
-100
0.01
10

V

·C/W
·C/W

3
50
-60

mA
mA
mA
mA
A

-120

-45.

V

50
50

/LA

-1
1
40

p.A
mA
mA
mA
mA

Note 1: Guaranteed and 100% production tested.
Note 2: Guaranteed, not necessarily 100% production tested. Not used to calculate outgOing AQL. Limits are for the temperature range of -4Q'C.:Ti': 150'C.

3-45

•

...

s:...

....
:IE

r-------------------------------------------------------------------------------------~

Typical Performance Characteristics
Output Voltage Drop

'Device Operatlng,Current

.....
CI

CI'

,

~

-

0.6

~

0.4

CI

0.2

~

~

-

o

-40

0.5

,,'f'

10uTLoo.l

o

...""""""

200 40D 600 BOD
OUTPUT CURRENT (mAl

o

40. 80
120 160
JUNCTION TEMPERATURE('CI

Output Voltage Drop

E

i
!
i
i

...

,
t..I'

~' 0.2

Jl

0.1

oL

L

E

Ii

"

o 100 200 30D 4D0 500 60D 700 800
OUTPUT CURRENT (mAl

VON/OFF .IV

25
20

15
10

I.
!:
I:

II

z

I

2

o
-40

. 20
0
20
40
SUPPLY YOlJAGE(VI

60

-

II~
NO HEAT SINK

r--

o 10 20 30 40 80 60 70 80 90
AMBIENT TEMPERATURE j'CI
TLlH15271-8

TlIHI5271-7

ON/m:F Current vs.
Junction Temperature

Threshold Voltage va.
SUpply Voltage

ON/OFF Current vs.
ON/m:F Voltage

so

30 VCC-12V
VIN-2V

I

~ZS

I

125'\

.. .....

~

o
-50;-25 0 25 50 7& 100
JUNCTION TEMPBlATURE ('CI

125

ZS'C

'':::::

"\

1.20

i

1

-

-- C

8

20
15

I~

10

z
o

I--

5

VCC=2BV

tf-- r-- rvcct4iv I--

,
fi

0510111202530
SUPPlY YOLJAGE (VI

TLIH/5271-13

I

2

3

4

5

8

ON/Off YOIJME (VI

TLlH15271-14

TlIH/5271-15

Equivalent Block Diagram

Vee

-- --

I I
II ~r-o~] HrT,INK,_ r-

I:

II

IN~IN~E

1.....+-' ' -

1-1- I- HEATSINK I-

16
14

i5

-5
-10

TLlH/5271-6

-

TLlH15271-5

Maximum Power
Dlsalpatlon (T0-220)

20

I:

L

I

'051015202530
Vcc(VI

~l~~Q I

3D

IL
~

.

,

o

1O00

Output Voltage (VOUT)
35

O.B
0.7
0.6
0.5
0.4
0.3

".

TL/H/5271-4

TL/H/5271-3

1.0
0.9

1.5

11.0
~

I

::>
I

g

J

lOUT. _IIA '.

CI

>

~

C'

D••

w

co

, Peak Output Current (VOUT)

400

.

~

¢r.
Vee

.....

o--....------t------------~,....

l

ON/Ofi'

5

,

2

3

4

OUT

100 nF

OUTPUT

TLlH/5271-12

FIGURE 1
3-46

0

~'
()

C

Yee

::+

tn

()
~

CD

3
I»

( ;'

Your

....~
'":"

'":"

R16

400

~ ~

I I I~ I I
R15

DON/orf

R18

_0

lIt I

f

j

9 ~. I f:-" I~
TL/H/5271-9

~~6U"

II

~ r-----------------------------------------------------------------------------------------~
N
G)
~

~

Application Hints

combined zener and diode breakdown should be less than
45 volts.
The LM1921 can be used alone as a simple relay or solenoid driver where a rapid decay of the load current is desired, but the exact rate of decay is not critical to the system. If the output is unclamped as in Figure 1, and the load
is inductive enough,-the negative flyback transient will cause
the output of the IC to breakdown and behave similarly to a
zener clamp. Relying upon the IC breakdown is practical,
and will not damage or degrade the IC in any way. There are
two considerations that must be accounted for when the
driver is operated in this mode. The IC breakdown voltage is
process and lot dependent. Clamp voltages ranging from
- 60 to -120 volts (with respect to the supply voltage) will
be encountered over time on different devices. This is not at
all critical in most applications. An important consideration,
however, is the additional heat dissipated in the IC as a
result. This must be added to normal device dissipation
when considering junction temperatures and heat sinking
requirements. Worst case for the additional dissipation can
be approximated as:
Additional Po = 12 x L x f (Watts)
I = peak solenoid current (Amps)
where:

HIGH CURRENT OUTPUT
The 1 Amp output is fault protected against overvoltage. If
the supply voltage rises above approximately 30 volts, the
output will 'automatically shut down. This protects the internal circuitry and enables the IC to survive ~igher voltage
transients than would otherwise be expected. The 1921 will
survive transients and DC voltages up to 60 volts on the
supply. The output remains off during this time, independent
of the state of the input logic voltage. This protects the load.
The high current output is also protected against short circuits to either ground or supply voltage. Standard thermal
shutdown circuits are employed to protect the 1921 from
over heating.

FLYBACK RESPONSE
Since the 1921 is designed to drive inductive as well 8l! any
other type of load, inductive kickback can be expected
whenever the output changes state from on to off (see
waveforms on Figure 1). The driver output was left unclamped since it is often desirable in many systems to
achieve a very rapid decay in the load current. In applications where this is not true, such as in Figure 2, a simple
external diode clamp will suffice. In this application, the integrated current in the ind\lctive load is controlled by varying
the duty cycle of the input to the driver IC. This technique
achieves response characteristics that are desirable for certain automotive transmission solenoids, for example.
For applications requiring a rapid controlled decay in the
solenoid current, such as fuel injector drivers, an extemal
zener and diode can be used as in Figure 3. The voltage
rating of the zener should, be such that it breaks down before the output of ttle LM1921. The minimum output breakdown voltage of the IC output is rated at - 57 volts with
respect to the supply voltage. Thus, on a 12 volt supply, the

L = solenoid inductance (Henries)
f = maximum frequency input signal (Hz)
For solenoids where the inductance is less than ten millihenries, the additional power dissipation can be ig~ored.
Overshoot, undershoot, and ringing can occur on certain
loads. The simple solution is to lower the Q of the load by
the addition of a resistor in parallel or series with the load. A
value that draws one tenth of the current or DC voltage of
the load is usually sufficient.

OIIIput

LM1921

~~~:~~ - - - - + - - -..

O('/.l":~1---LO-AO. . (~~I-I-L-..,

(PIN 2)

~ ~;N4001

TLlH/5271-10'

TLlH/5271-11

FIGURE 2_ Dlode·Clamp

FIGURE 3
Zener clamp for rapid controlled current decay

3-48

,-------------------------------------------------------------------------,

~

iii:
....

~
Q

tflNational Semiconductor

LM1950 750 mA High Side Switch
General Description

Features

The LM1950 is a high current, high side (PNP) power switch
for driving ground referenced loads. Intended for industrial
and automotive applications the LM1950 is guaranteed to
deliver 750 mA continuous load current (with typically 1.4
Amps peak) and can withstand supply voltage transients up
to +SOV and -50V. When switched OFF the quiescent
current drain from the input power supply is less than
100 /loA which can allow continuous connection to a battery
power source.
The LM 1950 will drive all types of resistive or reactive loads.
To obtain a rapid decay time of the energy in inductive
loads, the output is internally protected but not clamped and
can swing below ground to at least 54V negative with respect to the input power supply voltage.

•
•
•
•
•
•
•
•
•
•
•

The ON/OFF input can be driven with standard 5V TTL or
CMOS compatible logic levels independent of the Vee supply voltage used. Built in protection features include short
circuit protection, thermal shutdown, over-voltage shutdown
to protect load circuits and protection against reverse polarity input connections. The LM1950 is available in a 5-lead
power TO-220 package and specified over a wide - 40'C to
125'C operating temperature range.

•
•
•
•
•

Typical Application

750 mA continuous output drive current
Less than 100 /loA quiescent current in OFF state
Low input! output voltage drop
+ SOV/ - 50V transient protection
Drives resistive or reactive loads
Unclamped output for fast inductive decay tmies
Reverse battery protected
Short circuit proof
Overvoltage shutdown to protect loads
TTL/CMOS compatible control input
Thermal overload protection

Applications
Relay driver
SolenoidlValve driver
Lamp driver
Load circuit switching
Motor driver

+4.75 TO 26V

O.ll'r

I
Vee SUPPLY
1

V~

OV
ON

r-1 °oN~fffiT-or-r~----------~
-I Lov 5

+5V

Vee - 54V
OUTPUT

orr

~-----.......~~'"., .
GROUND

4

3 GROUND

I II[
RELAY
LOAD

TUH/11237-1

'Required for stability

Connection Diagram
TO 220, 5 Lead

:"'/~

4 GROUND
3 GROUND

, """" (,~ l
1 SUPPLY (Vee)
TUH/11237-2

Front View
Order Number LM19S0T
See NS Package Number TOSA

3-49

&I

Absolute Maximum Ratings

(Note 1)
Storag~

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
26V
Continuous
Transient (1";;: 100 ms)
-SOVto +E!ov
-1SV
Reverse Polarity (continuous)
Internally Limited

Load Inductance
Maximum Junction Temperature

-6S·C tei + 1S0·C
230·C
2000V

Operating Ratings

-0.3Vto +6.0V

OnlOff Voltage
Power DiSsipation

Temperature Range.

Lead Temperature
. (Solderil)g,10 seconds)
ESD Susceptibility (Note 2)

1S0mH
1S00C

(Note 1)

Temperature flange (TA)

- 400C to + 12S·C

Supply Vol~ge Range
Thermal Resistances;
Junction to Case (9j-el
Case to Ambient (9 c -a>

4.7SVto 26V

3·C/W
SOOC/W

Electrical Characteristics
Vcc = 14V, lOUT = 1S0 mA unless otherwise indicated. Boldfacelimils apply over the entire operating temperature range,
-40·C ;;: TA ;;: 12S·C, all other specifications are for TA = TJ = 2S·C
Limit

Units
(Limit)

4.7S/4.75
26/26
-1S/-15
60/60
-SOl-50

V (Min)
"(Max)
Voc(Min)
V (Max)
V (Min)

20

100/100

I£A(Max)

S
27S
SSO
B2S

10/10
3S0/350

700/700
9S0/950

mA(Max)
mA(Max)
mA(Max)
mA(Max)

0.30
O.SO
0.7S

0.S/0.6
0.711.0
1.1/1.4

V (Max)
V (Max)
V (Max)

1.S

1.0/0.75
2.0/2.0

A (Min)
A (Max)

10

50/50

I£A (Max)

1.4

O.BIO••
2.0/2.0

V(Min)
V (Max)

0.1
1
50

5/10
10/20
100/100

I£A (Max)
I£A (Max)
I£A (Max)

33

27/27
37/37

V (Min)
V (Max)

= 2V to O.BV,
lOUT = 100 mA

-45

-120/-120
-40/-40

V (Max)
V (Min)

OutpulTurn-On Delay

VON/OFF 0.8V to 2V

4.2

20

I£s

Output Turn-Off Delay

VON/OFF 2V to O.BV

4.5

20

I£s

Parameter

Conditions

Typical

Supply Voltage
Operatiorial
Survival
Transient
Supply Current

Input to Output
Voltage Drop

t = 1 mS,1" = 100 ms,
1% dutycycle
VON/rn=F'
VON/rn=F'
lOUT =
lOUT =
lOUT =
lOUT =

= O.BV
= 2.0V
OmA
2S0mA
SOOmA
7S0mA

lOUT = 2S0mA
lOUT = SOOmA
lOUT = 7S0mA

Short Circuit Current
Output Leakage Current

V6N/~= O.BV

ON/OFF Input
Threshold Voltage
ON/OFF Input Current

VON/rn=F' = O.BV
VON/~= 2.0V
VON/OFF = 5.25V

Overvoltage Shutdown
Threshold
Inductive Clamp
. Output Voltage

VONl~

Note 1: Absolute Maximum Ratings indicate IimRs beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional. but do not guarantee specific performance limits. For guaranteed specifications and test condHions, see the Electrical Characteristics.
Note 2: Human body model, 100 pF discharged through a 1.5 kll resistor.

3-S0

Typical Performance Characteristics
Output Voltage Drop
vs Temperature

Output Voltage vs Vee
35

I\. = 504

'VON/OFF = 2V

30

~

~
~

~

~

25

~

~

II

20
15

~~

L

10

~

~,?

1/

0

-5
-40

II

0.•
lOUT

0.6

-20

20

40

80

I

~

/"

I
11

I
I

~

o

10

15

20

25

30

./

ON/OFF Input Current
vs ON/OFF Input Voltage

400

600

I

2

~
~

I

V

I~

--

10 20 30 40 50 60 70 80 90

/

~
9
F

1.30

~

-

1.45
1.40

i

J

-

~

I--~

-4d!c - r- 2~1c

1.35

1.25

II

1.20

-40

4

1

On/OFF Input Threshold
Voltage vs Supply Voltage

o

3

o

1.50

/

../

o
o

~H~TS!NK - f-

AMBIENT TEMPERATURE (DCi

.1l.

/

-

10

"""

NO HEAT SINK

800

Vee = 12V
VON/OFF = 2V

20

~

ON/OFF Input Current
vs Temperature

50

,

r- - r-

o
200

10

~

HEAT SINK

10

.~

/

IJFINI~E

r-

1 1
1 1

~

1/

20

-

-

14
12

OUTPUT CURRENT (mA)

60

.~

I

./

40

18
16

:g

V

/

Vee (V)

::>
<.>

100 ZOO 300 400 500 800 700 800
OUTPUT CURRENT (mA)

v

oV
o

o

30

o

180

Maximum Power
Dissipation

80
60

/

II"

20

.5

L

0.5

§

120

V

o/

Operating Current
vs Load Current

V

1.0

40

~

'i'

100

1.5

.3

0.5
0.4
0.3
0.2
0.1

,?

80

l..V

JUNCTION TEMPERATURE (DC)

2

!

40

-40

Peak Output Current

B

~~

I

SUPPLY VOLTAGE (V)

§

i

I

= SOOmA

I
loUT = 100mA

0.2

1.0
0.9
0.8
0.7
0.8

~

I

0.4

o

-10

3

Output Voltage Drop
vs Output Current

1.0

40

80

120

160

o

10

JUNCTION TEUPERATURE (DC)

INPUT VOLTAGE (V)

15

ZO

25

30

SUPPLY VOLTAGE (V)
TL/H/11237-3

Turn-On Delay Time
vs Temperature

8.0

'I

.3

!

Tum-Off Delay Time
vs Temperature

Delay Time Definitions

•.0

7.0

7.0

6.0

6.0

5.0

---

4.0
3.0
2.0

L

V

'I.3
,.;::

ONjOFF

-

5.0
4.0

~

3.0
2.0

1.0
-40

I--I-"

80

120

180

JUNCTION TEMPERATURE (DC)

-40

I
I

'oN - - ' ; -

V

.

I V

::~CgO%

OUTov ---:./10%

'oFF
40

80

120

160

JUNCTION TEMPERATURE (DC)

TL/H/11237-11

TUH/11237-12

3-51

OFF

~
I

I
I
I

o
40

ON

OV.:::!J,

1.0

o

+5V

OFF-'~

INPUT

:

:~

--! !-TLlH/11237-10

&I

o~--~------------------------------------------------~

'1ft

~

::E
....

Application Hints
The LM1950 can be used alone as a simple relay or solenoid qriver where a rapid decay of the load current is desired, but the exact rate of decay is not cri~,cal to the system. If the output is unclamped as, in Figure 1, ,and the load
is inductive enough, the negative flybaqk transient'will cause
the output of the IC tobrea,kClown and !lehave similarly to a
zener clamp. Relying upon the IC breakdown is ,practical
and will not damage or degrade the IC in any way. There are
two considerations that must be accounted for when the
driver is operated in this mode. The IC breakdown voltage is
process and lot dependent,' Output clamp voltages ranging
from -40V to -1201/ (with Vee supply of 14V) will be encountered over time on different devices. This is not at all
critical in most applications. An imponant consideration,
however, is the additional heat dissipated in the IC as a
result. This must be added to normal device dissipation
when conSidering junction temperatures and heat sinking
requirements. Worst case for the additional dissipation can
be approximated as:
Additional PD = 12 x Lx f(Watts)
Where: I = Peak Solenoid Current (Amps)
L = Solenoid Inductance (Henries)
f = Maximum Frequency Input Signal (Hz)
For solenoids where the inductance is less than ten milli'henries, the additional power dissipation can be ignored.
Overshoot. undershoot. and ringing can occur on certain
loads. The simple solution is to lower the Q of the load by
the addition of a resistor in parallel or series with the load. A
value that draws one tenth of ,the current or DC voltage of
the load is usually sufficient.

HIGH CURRENT OUTPUT
The 750 mA output f~ult protected against overvoltage. If
the supply I{oltage rises above approximately 3pV. the output will automatically shut down. This protects the internal
circuitry and enables the IC to survive higher voltage tra~­
sients than would otherwise be expected. The LM1950 will
survive transients and DC voltages up to SOV on the supply.
The output remains off during this time, independent of the
state of the input logic voltage. This protects the lo~d. The
high current output is also protected against short circuits to
either ground or supply voltage. Standard thermal shutdown
circuits are employed to protect the LM1950 from over heating.

Is

FLYBACK RE~NSE
Since the LM1950 is designed to drive inductive as well as
any other type of load, inductive kickback can be expected
whenever the output changes state from ON to OFF (See
Waveform on Figure 1). 'The driver output was left unclamped since it is often desirable in many ,systems to
achieve a very rapid decay in the load current In applications 'where this is not true, such as in Figure 2, ,a simple
external diode clamp will suffice. In this application, the integrated current in the inductive load is controlled by varying
the duty cycle of the input to the drive IC. This t~chnique
achieves response characteristics that are desirable for certain automotive transmission solenoids, for example.
For applications requirin~ a rapid controlled decay in the
solenoid cuirent, such as fuel injector drivers, an' external
zener and diode can be used as in Figure 3. The voltage
rating of the zener should be such that it breaks down before the output of the LM1950. The minimum output breakdown voltage of the IC output is rated at - 54V with respect
to the supply voltage.

For frequency stability of the switch, a 0.1 p.F or larger output bypass capacitor Is required.

V~O-~~------~----------~--------1-1

ON/Ori'
ON

'"''"~
• TL/H/11237-4

FIGURE 1
OUTPUT
OUTPUT - -...- - - - ,

OUTPUT
OUTPUT - -....._ - -..

LM1950

LM1950

(PIN2)

(PIN2)
LOAD

II

L

/

16V

RL

TL/H/11237-5

TL/H/11237-6

FIGURE 2. Diode Clamp

FIGURE 3. Zener Clamp for Rapid
Controlled Current Decay
3-52

Circuit sCrematic

~

•
3·53

.- r--------------------------------------------------------------------------------,
~

~

t!lNational Semiconductor

LM 1951 Solid S,tate1 Amp Switch
General Description

Features

The LM1951 is a high current, high voltage, high side (PNP)
switch with a built-in error detection circuit.
The LM 1951 is guaranteed to deliver 1 Amp output current
and is capable of withstanding up to· ± 85V transients. The
built-in error detection provides an error flag output under
the following fault conditions: output short to ground or supply, open load, current limit, overvoltage or thermal shutdown. The LM1951 will drive all types of resistive or inductive loads. The output has a built-in negative voltage clamp
( ::::; - 30V) to provide a quick energy discharge path for'
inductive loads. The LM1951 features TTL and CMOS compatible logic input with hysteresis. Switching times, both turn
on and turn off, are 2 "'S (Ctoad < 0.005 ",F). In addition, its
quiescent current in the OFF state is typically less than
0.1 ",A at room temperature and less than 10 ",A over the
entire operating temperature and voltage range.
The LM 1951 features make it well suited for industrial and
automotive applications.

• 0.1 ",A typical quiescent current (OFF state)
• 1 Amp output current guaranteed
• ± 85V transient protection
• Reverse voltage protection
• Negative output voltage clamp
• Error flag output
• Internal overvoltage shutdown
• Internal thermal shutdown
• Short circuit proof
• High speed switching (up to 50 kHz)
• Inductive or resistive loads
• Low ON resistance (1 n m8j 26V), overcurrent (lOUT> 1.3A), undercurrent
(lOUT < 2 mAl, output short circuit to ground, output short
circuit to supply, and junction temperature greater than
1500C. By connecting a 2 kO resistor from the error flag
output to a 5V supply a logiC output to a microprocessor is
provided.

For inductances above 1H, care should be taken to see that
the output current does not exceed a value that could damage the clamp. While 800 mA is acceptable for the device
running at 25°C ambient on a heatsink, derate this current
for smaller heatsinks or higher ambient temperatures to limit
the junction temperature to 1500C. Alternatively, an external
clamp or resonating capacitor can be added to handle any
combination of load inductance, load current, and device
temperature. This is especially important if the output current is boosted, such as the application shown in Figure 3. A
peak power of 750W could be developed in the internal
clamp if an inductive load is switched without external
clamping.
Another case where the clamp's power capability may be
exceeded is when driving a solenoid. The inductance of a
solenoid is greatest when energized, with the plunger pulled
in. As the plunger is pulled out of the solenoid, the inductance goes down. Under certain conditions of high solenoid
inductance and fast mechanical time constants, the current
may actually Increase when the solenoid is turned OFF.
Since the energy stored in an inductor cannot change instantaneously, the current must increase to conserve energy when the inductance decreases. This condition is traced
by observing the load current with a current probe and storage oscilloscope.
Load capacitances larger than 1 nF will slow rise and fall
times. Inductive loads having a capacitive component larger
than 1 nF will also exhibit overshoot. Furthermore, ringing

The error flag can give seemingly false indications in a number of situations. Slewing large capacitive loads (> 100 nF)
can drive the LM1951 into temporary current limit, producing a momentary error indication. Incandescent lamps and
DC motors require an inrush current that will also cause a
temporary current limit and error indication. Large inductive
loads (>50 mH) initially appear as open circuits, falsing the
error flag. The error flag pulses for about 1 ,...S when any
load is turned ON since the output is initially at ground. In
microprocessor systems these false indications are easily
ignored in software. In discrete logic circuits utilizing a latch
at the error flag output, some filtering may be required.
An internal current sink (10 ,...A minimum) is co'nnected to
the input, pin 5. If this pin is left open it is guaranteed to pull
low, switching the LM1951 OFF. This characteristi« is important under certain fault conditions such as when the ,control line fails open cirucit.
,
Although the input threshold has hystereSiS, the switch
pOints are derived from a very stable band-gap reference. In
many applications, such as Figures 5 and 7, the LM1951
input can replace an extenal reference and comPi!rator.
The input (pin 5) is clamped at -0.7V and includes a series
resistance of approximately 30 kO. This pin tolerates negative inputs of up to 1 mA without affecting the performance
of the chip.

3-61

CD

(II

.- r--------------------------------------------------------------------------------,

!
:i d
P Nat ion a I

,S e m i c, 0 n due tor

LM9061
Power'MOSFET Driver with Lossless Protection'
General Description

Features

• Built-in charge pump fOr gate overdrive of high !lids
The LM9061isa charge-pu",p deYice~hich provides the
drive applications
'
,
gate drive to any size external power MOSFET configured
as a high side driver or s,witch. A CMOS logic compatible
• Lossless protecti(ni of the power 'M9~FET
ON/OFF input con,trols the 9utput gate driV~, voltage., In the
• Programmable MOSFET protection voltage
ON state, the charge pump voltage, which is well above the
• Progri!mmable delay of protection latch-OFF
available Vee supply, is directly applied to the gate' of the
• Fast turn-ON (1.5 ms max with gate ,capacitance of
MOSFET. A built-ih 1SV zener clamps the 'maximum gate to
25000:pF)
source voltage of the MOSFET. When Commanded OFF a
• Undervoltage shut OFF with Vee < 7V
110 /J-A current sink discharges the gate capacitances of
• Overvoltage shut OFF with Vee> 26V
the MOSFET for a gradual turn-OFF characteristic to mini• Withstands 60V supply transients '
mize the, dor,a~ion of inductive load transient voltages and
• CMOS logic compatible ON/OFF'control input
further protect the power MOSFET.
• Surface mount and dual in-line packages available
Lossless protection of the power MOSFET is a key feature
of. the LMIl061. The voltage drop (Vos) across, the power
Applications
device is continually monitored and compared'agai~t an
externally programma~le t~reshOJd voltage. A small current
• Valve, relay apd solenoid drivers
sensing resistor in series With,the load, which ,causes,a loss
• Lal1)p drivers
of available energy, is not required f9r the protection circuit- " • DC,motor PWM drivers
ry. Should t~~ 'Vos voitage, due to excessive load current,
• Logic comrolled power supply dilltribution switch
exceeq'the threshold voltage, the output is latched OFF in ,a
• Electronic circuit breaker
more gradual fashion (through a 10 IJ-A output current sink)
after a program'mable delay time interval. ,. ,
Designed for the automotive application environment the
L~9()61 has a \'fide operating temperatur~ range of -'-4Q"C
to + 125°C, remains operational with Vee up to 26V, and
can withstand 60V power supply transients. The LM9061 is
availabie'in an 8-pin small outline package, and an 8-pili
dual in-line package.

Typical Application

Connection Diagrams'

--0--

Sense 1 __________
Threshold 2

~

8 Delay
7 On/Off

Ground 3 -

- - 6 IREF

Output 4 - - -

- - - 5 Vee
TL/H/12317-3

Top Vie"'!

0-

Order Number LM9061M
See NS Package Number M08A

Sen .. 1 Threshold 2 - -

..

~.'

:'

TL/H/12317-1

8 Daley
- - 7 On/Off

Ground 3 - -

- - 6 ~[F

Output 4 - -

- - 5 Vee

TL/H/12317-2

Top View

Order Number LM9061N
See NS Package Number N08E

3-62

Absolute Maximum Ratings

Operating Ratings

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Reverse Supply Current

-0.3VtoVcc

Ambient Temperature Range

-40'Cto 125'C

Thermal Resistance (8J-Al

20mA
Vcc + 15V

Voltage at Sense and Threshold
(through 1 kO)

7Vt026V

ON/OFF Input Voltage

60V

Output Voltage

(Note 2)

Supply Voltage

LM9061M

150'C/W

LM9061N

100'C/W

-25Vto +60V
-0.3V to Vee + 'O.3V

ON/OFF Input Voltage
Junction Temperature

150'C

Storage Temperature

- 55'C to 150'C

Lead Temperature (Soldering, 10 seconds)

26O'C

DC Electrical Characteristics
7V ,,; Vee ,,;20V, RREF = 15.4 kn, -40'C ,,; TJ ,,; + 125'C, unless otherwise specified.
Symbol

I

Parameter

I

Conditions

I

Min

I

Max

I

Units

POWER SUPPLY
10

Quiescent Supply Current

ON/OFF = "0"

ICC

Operating Supply Current

ON/OFF = "1",
CLOAO = 0.025,...F,
Includes Turn-ON
Transient Output Current

5

mA

40

mA

ON/OFF CONTROL INPUT
VIN(O)

ON/OFF Input Logic "0"

VOUT = OFF

VIN(1)

ON/OFF Input Logic "1"

VOUT = ON

3.5

1.5

V

VHYST

ON/OFF Input HystereSiS

Peak to Peak

0.8

2

V

liN

ON/OFF Input Pull-Down Current

VON/OFF = 5V

50

250

,...A

Vee + 7

Vcc + 15

V

0.9

V

11

15

V

V

GATE DRIVE OUTPUT
VOH

Charge Pump Output Voltage

ON/OFF = "1"

VOL

OFF Output Voltage

ON/OFF = "0",
ISINK = 110}loA

VCLAMP

Sense to Output
Clamp Voltage

ISINK(Normal-OFF)

ISINK(Latch-OFF)

ON/OFF = "1",
VSENSE =VTHRESHOLO

Output Sink Current,
Normal Operation

ON/OFF = "0",
VOELAY = OV,
VSENSE =VTHRESHOLO

75

145

,...A

Output Sink Current with
Protection Comparator Tripped

VOELAY = 7V,
VSENSE < VTHRESHOLO

5

15

,...A

75

88

,...A

1.15

1.35

V

PROTECTION CIRCUITRY
IREF

Threshold Pin Reference Current

VREF

Reference Voltage

ITHR(LEAKAGE)

Threshold Pin Leakage Current

Vee = Open,
7V ,,; VTHRESHOLO ,,; 20V

10

,...A

ISENSE

Sense Pin Input Bias Current

VSENSE= VTHRESHOLO

10

,...A

6.74

15.44

}loA

5

6.2

V

2

10

mA

0.4

V

VSENSE =VTHRESHOLO

DELAY TIMER
10ELAY

Delay Pin Source Current

VTIMER

Delay Timer Threshold Voltage

lOIS

Delay Capacitor Discharge Current

VOELAY = 5V

VSAT

Discharge Transistor Saturation Voltage

lOIS = 1 mA

3-63

•

....CD
I....I
0

AC Timing Characteristics
7V ,,; Vee ,,;20V, RREF = 15.4 kll, -40·C ,,; TJ ,,;
specified.
Symbol

TON

TOFF (Normal)

TOFF(Latch-OFF)

TDELAY

+ 125·C, CLOAD

Parameter

= 0.025 ",F, CDELAY = 0.022 ""F, unless otherwi~

Conditions

Output Turn-ON Time

Min

CLOAD = 0.025 ",F
7V,,; Vee ,,; 10V, VOUT ~ Vee + 7V
10V,,; Vee"; 20V, VOUT ~ Vee + 11V

Max

Units

1.5
1.5

ms
ms

Output Turn-OFF Time,
Normal Operation
(Note 4)

CLOAD = 0.025 j!.F
Vee = 14V, VOUT ~ 25V
VSENSE = VTHRESHOLD

4

10

ms

Output Turn-OFF Time,
Protection Comparator Tripped
(Note 4)

CLOAD = 0.025 ",F
Vee = 14V, VOUT ~ 25V
VSENSE = VTHRESHOLD

45

140

ms

Delay Timer Interval

COELAY = 0.022 ",F '

8

18

ms

Note 1: Absolute,Maximum Ratings Indicate the limits beyond which damage to the deviee may occur.
Note 2: Operating Ratings indicate conditions for which the device is intended to be functional, but may not meet the guaranteed specific perlotTrn!nce limits. For
guaranteed specifications and test conditions see the Electrical Characteristics.
N"te 3: ESD Human Body Model: 100 pF discharged through 15000 resistor.

OFF are not production tested, and therefore are not specifically guaranteed. Umlts are provided for riIIerenee purposEos
only. Smaller load capacitances will have proportionally faster tum-ON and tum-OFF times.

Note 4: The AC Timing specifications for T

Block Diagram
load
Power

Supply

Vee

Supply

Ground
TLlH/12317-4

3-64

Typical Operating Waveforms
Normal
II--- Operation

VIN (1)

ON/OFF Input
Pin 7
VIN(O)

Excessive
Load Current

-.J

~

I

L

Your

Pin 4

VSOURCE

v Gate

10 Source

I
I
I
I
I
I
I
I

Load
Current

OA

I

- : TOELAY

t --- j

I

l--

7.SV - - - - - - - - - - - - - - - - - - - - - - - S.SV _______________________ ...1 __
VDELAY
Pin 8

Protection
Comparator
Oulpul
Delay
Comparator
Oulpul

- --,------..,

I
I

OV _ _-JL-_ _ _ _ _ _ _-J~I

01

~,._ _ _ _...Jr-----,Ul-I.--.;-------------

0 - - - - - - - - - - - - - - - -....

L

TLlH/12317 -5

•
3-65

....
§

...

Typical Electrical Characteristics

:::E

Operating Supply Current
vsVcc

Standby Supply Current
vsVcc

Output Voltage
vsVcc
50r---~----,---~r_--~

50,.----,----,.----,----.
TA = 25°C

40

3r_--~--_+----r_~

f----f---h.,./+--l

V

30f----+--~+---~1_--~

V

t

.3
1r_~_r----r---_r--~

OWL__L -__

~

o

10

__

20

~

!

10f---+t----+---~1_--~

0---

__

30

20f---~----+---~1_---l

~

o

40

10

20

Vee (V)

vee~uJ

-3

J

  • ...

.........

~ 0.5

=20V

Ve:;7V ...........................

~~

0~~~--4-~--~~~

o

2

4

6

8

10

12

Output Voltage Above Vee

Delay Threshold
vs Temperature

f----+--f----+--f----+--f-----1
I--I--I--I--P'-I.:-f',-+--I

2.0
~

Ambient Temperature (e)

Reference Voltage
vs Temperature .

.
1 245

/'

40

TA

/

9.0 L-...L--1__-1--1.__L-...L--1
-50 -25 0 25 50 75 100 125

Ambient Temperature (e)

1.250

I

o

100 L--L__L.-L__L.-L~L-~
-50 -25 0 25 50 75 100 125

:?::

1.1.

Latched (Fault) Turn-Off j

in

1105f--I---r--I---r--I---f--l

1
:i

Vee ~ uJ

30

Output Source Current
vs Output Voltage

r--r--r--r-'-r--r--r-~

e
110

20

Vee (V)

Output Sink Current
vs Temperature

120r--r--r--r--r--r--r_~

Normal Turn-Off

10'

40

Vee (V)

Output Sink Current
vs Temperature
~

30

10r---++----~--~~--~

14

(v)

Delay Charge Current
vs Temperature

11.0

r--.--.--,.-....,.--,--.-.

10.5

f----+--I-+--t-+--t---l

Vee l= uv

4:

-3

1i
:

:1i

---

f----+-:::::;l._-l"''''f''-+-+--l
-~
9.5 f----+--t-+--t-+--t---l

10.0

9.0 L-...L---L__L.......L---L__L.......J
-50 -25 0 25 50 75 100 125
Ambient Temperature (e)

TL/H/12317-06

3-66

~--------------------------------------------------~r

~

Typical Electrical Characteristics (Continued)

8

....
0)

Timing Definitions
Vee + 15V ---i--':r---,;--C---i
Vee +llV---l- 1
vee + 7V - - -j - :
Gate Drive

Output Voltage V e

I

:

__ ~

orr (Normal 110 pA)

1

ell
-+I
~TON

1
1

1

1

1

Vorr ---: ~------+----- 1
OV
1
1
1
,

7.5V

-:
:.!
:

:
---:--------+
:

VOELAY

1

- : TOELAY

1

5V

1-

-=jz------\i

J-!
ov

VON/orr

'orr(Latch orr)

1
1

--i---or
1
1

:-Torr(Normal)

1

• 1

VTlMER ---I -

1
1

OV

1

1

~
I

TL/H/12317-07

Application Hints
When commanded ON by a logic "1" input to pin 7, the gate
drive output, pin 4, rises quickly to the Vee supply potential
at pin 5. Once the gate voltage exceeds the gate-source
threshold voltage of the MOSFET, VGS(ON), (the source is
connected to ground through the load) the MOSFET turns
ON and connects the supply voltage to the load. With the
source at near the supply potential, the charge pump continues to provide a gate voltage greater than the supply to
keep the MOSFET turned ON. To protect the gate of the
MOSFET, the output voltage of the LM9061 is clamped to
limit the maximum VGS to 15V.
It is important to remember that during the Turn-ON of the
MOSFET the output current to the Gate is drawn from the
Vee supply pin. The Vee pin should be bypassed with a
capaCitor with a value of at least ten times the Gate capacitance, and no less than 0.1 ",F. The output current into the
Gate will typically be 30 rnA with Vee at 14V and the Gate at
OV. As the Gate voltage rises to Vee, the output current will
decrease. When the Gate voltage reaches Vee, the output
current will typically be 1 rnA with Vee at 14V.
A logic "0" on pin 7 turns the MOSFET OFF. When commanded OFF a 110 ",A current sink is connected to the
output pin. This current discharges the gate capaCitances of
the MOSFET linearly. When the gate voltage equals the
source voltage (which is near the supply voltage) plus the
VGS(ON) threshold of the MOSFET, the source voltage
starts following the gate voltage and ramps toward ground.
Eventually the source voltage equals OV and the gate continues to ramp to zero thus turning OFF the power device.
This gradual Turn-OFF characteristic, instead of an abrupt
removal of the gate drive, can, in some applications, minimize the power dissipation in the MOSFET or reduce the
duration of negative transients, as is the case when driving
inductive loads. In the event of an overstress condition on
the power device, the turn OFF characteristic is even more
gradual as the output sinking current is only 10 ",A (see
Protection Circuitry Section).

BASIC OPERATION
The LM9061 contains a charge pump circuit that generates
a voltage in excess of the applied supply voltage to provide
gate drive voltage to power MOSFET transistors. Any size
of N-channel power MOSFET, including multiple parallel
connected MOSFETs for very high current applications, can
be used to apply power to a ground referenced load circuit
in what is referred to as "high side drive" applications.
Figure 1 shows the basic application of the LM9061.
Load Supply
1k

Load

7

~o.lpr

ON/orr
TL/H/12317-8

FIGURE 1. Basic Application Circuit

3-67

§
~

r-----------------------------------------------------------------------------~

Application Hints (Continued)
TURN ON AND TURN OFF CHARACTERISTICS

"The load is still fully energized until time t5 when the gate
voltage has reached a potential of the source voltage (Vee)
plus the VGS(ON) threshold voltage of the MOSFET. Be,tween time t5 and t6, the VGS voltage remains constant and
the source voltage follows the gate voltage. With the voltage on CGO held conStant the discharge rate now becomes
110/-LA/CGo,
At time 16 the source voltage reaches OV. As the gate
moves below the VGS(ON) threshold the MOSFET tries to
turn OFF. With an inductive load, if the current in the load
has not collapsed to zero by time 16, the action of the
MOSFET turning OFF will create a negative voltage transient (flyback) across the load. The negative transient will
be clamped to -VGS(ON) because the MOSFET must turn
itself back ON to continue conducting the load current until
the energy in the inductance has been dissipated (at time
t7).

The actual rate of change of the voltage applied to the gate
of the power device is directly dependent on the input capacitances of the MOSFET used. These times are important
to know if the power to the load is to be applied repetitively
as is the case with pulse width modulation drive. Of concern
are the capacitances from gate'to drain, CGO, and from gate
to source, CGS. Figure 2 details the turn ON and turn OFF
intervals in a typical application. An inductive load is assumed to illustrate the output transient voltage to be expected. At time t1, the ON/OFF input goes high. The output,
which drives the gate of the MOSFET, immediately pulls the
gate voltage towards the Vee supply of the LM9061. The
source current from pin 4 is typically 30 mA which quickly
charges ~O and CGS. As soon as the gate reaches the
VGS(ON) threshold of the MOSFET, the switch turns ON and
the source voltage starts rising towards Vee. VGS remains
equal to the threshold voltage until the source reaches Vee.
While VGS is constant only CGO is charging. When the
source voltage reaches Vee, at time t2, the charge pump
takes over the drive of the gate to ensure that the MOSFET
remains ON.
'

MOSFET PROTECTION CIRCUITRY
A unique feature of the LM9061 is the ability to sense excessive power dissipation in the MOSFET and latch it OFF
to prevent permanent failure. Instead of senSing the actual
current flowing through the MOSFET to the load, which typically requires a small valued power resistor in series with
the load, the LM9061 monitors the voltage drop from drain
to source, VOS, across the MOSFET. This "Iossless""technique allows all of the energy available from the supply to be
conducted to the load as required. The only power loss is
that of the MOSFET itself and proper ,selection of a partic;:ular power device for an application will minimize this concern. Another be!1efitof thi,s technique is tha! all'aep,lications use only standard inexpensive 1J4W or less resistors.

The charge pump is basically a small internal capacitor that
acquires and transfers charge to the output pin. The clock
rate is set internally at typically 300 kHz. In effect the charge
pump acts as a switched capacitor resistor (approximately
67k), connected to a voltage that is,clamped at 13V above
the Sense input pin of the LM9061 which is equal ~o the Vee
supply in typical applications. Th~ gate voltage rises above
Vee in an exponential fashiQn with a time constant dependent upon the sum of ~O and CGg. At this time however
the load is fully energized. At time 13, the charge pump
reaches its maximum potential and the switc:h remains ON.

To utilize this lossless protection technique requires knowledge of key characteristics of the power MOSFET used. In
any application the emphasis for protection can be placed
on either the'.pDwer MOSFET or on the amount'of current
delivered to the load, with the assumption that the selected
MOSFET can safely handle the maximum load current.

At time t4, the ON/OFF input goes, low to turn OFF the
MOSFET and remove .power from the load. AI this time the
charge pump is disconnected and an internal 110 p.A current sink begins to discharge the gate input capacitances to
ground. The disqharge rate (/1VI/1T) is equal to HO pA/
(CGo + CGS)·

Vcc

,

,?;tu~ff :: j

,

,

_L_L_____ I

Vcc+f5V--~-:-1

1

Vcc+VGS ON - -

t - - - ~ - - - - - - -1 - - - - -

VOUT

I
I

t

I
I,
r

, VGS

g~

I
I

I
I
I

1

1

VSOURCE

,

CGS

-

I
I

'I

I
I

~

+-

1

1

I

I

VGS ON " -

1....

"

1
1
1
I

1
'\

I

I

1
1
1
I
I

I

I

~---~------~-----~~-­
f - - - - - t ---

-VGS ON - - ~ -~ - - ~ - - - - - 15V--'--I-'

"OV

VOUT

(Gale)

,- .:-::-.::.:-.3.:-.:-.:-.:-.:-.:-';.:-.:-.:-_-.:-';.:-.:-_--1 - -..0.100--

VCC - -

VGS

1

-E
Ct;o

1
1 '

1

1

, (Gale)

,

I

1
I

I

I

1

1
1 ,
1
1 __ ~ _ _ _ _ _ _ ~ _____
~I_ _;....__;..:

~

I

r -- -1- -

1" 12

13

- - - - . , - - - - - , - - -., - - -.,

14

1516

- FIGURE 2. Tum ON and Turn OFF Waveforms
3-68

17

TLlH/12317-9

.-----------------------------------------------------------------------------~

Application Hints (Continued)
To protect the MOSFET from exceeding its maximum junction temperature rating, the power dissipation needs to be
limited. The maximum power dissipation allowed (derated
for temperature) and the maximum drain to source ON resistance, ROS(ON), with both at the maximum operating ambient temperature, needs to be determined. When switched
ON the power dissipation in the MOSFET will be:

Two resistors connect the drain and source of the MOSFET
to the LM9061. The Sense input, pin 1, monitors the source
voltage while the Threshold input, pin 2, is connected to the
drain, which is also connected to the constant load power
supply. Both of these inputs are the two inputs to the protection comparator. Should the voltage at the sense input ever
drop below the voltage at the threshold input, the protection
comparator output goes high and initiates an automatic
latch-OFF function to protect the power device. Therefore
the switching threshold voltage of the comparator directly
controls the maximum VOS allowed across the MOSFET
while conducting load current.
The threshold voltage is set by the voltage drop across resistor RTHRESHOLO. A reference current is fixed by a resistor to ground at IREF' pin 6. To precisely regulate the reference current over temperature, a stable band gap reference
voltage is provided to bias a constant current sink. The reference current is set by:

VOS2
POISS=--ROS(ON)
The VOS voltage to limit the maximum power dissipation is
therefore:
VOS (MAX) = ~Po (MAX) X ROS(~N) (MAX)
With this restriction the actual load current and power dissipation obtained will be a direct function of the actual
ROS(ON) of the MOSFET at any particular ambiElnt temperature but the junction temperature of, the power device, will
never exceed its rated maximum.
To limit the maximum load current requires an estimate of
the minimum ROS(ON) of the MOSFET (the minimum
ROS(ON) of discrete MOSFETs is rarely specified) over the
required operating temperature range.

§....

VREF
IREF=-RREF
The reference current sink output is intemally connected to
the threshold pin. IREF then flows from the load supply
through RTHRESHOLO. The fixed voltage drop across
RTHRESHOLO is apprOximately equal to the maximum value
of VOS across the MOSFET before the protection comparator trips.

The maximum current to the load will be:
ILOAO (MAX) =

r
a::::

VOS

:::--=--

ROS(ON) (MIN)
The maximum junction temperature of the MOSFET and/or
the maximum current to the load can be limited by monitoring and setting a maximum operationalllalue for the drain to
source voltage drop, Vos. In addition, in the event that the
load is inadvertently shorted to ground, the power device
will automatically be turned-OFF.
In all cases, should the MOSFET be switched OFF by ~he
built in protection comparator, the output sink current is
switched to only 10 p.A to gradually turn OFF the power
device.

It is important to note that the programmed reference current, serves a multiple purpose as it is used internally for
biasing and also has a direct effect on the internal charge
pump switching frequency. The deSign of the LM9061 is
optimized for a reference current of approximately 80 ,..,A,
set with a 15.4 kO ±1% resistor for RREF. To obtain the
guaranteed performance characteristics it is recommended
that a 15.4 kO resistor be used for RREF.
The protection comparator is configured such that during
normal operation, when the output of the comparator is low,
the differential input stage of the comparator is switched in

Figure j illustrates how the threshold Voltage for the internal
protection comparator is established.

load

-----.,

Supply

I
I
2:

RTHRESHOLD

1.25V

To
'Int.rnal
Bias
Start O.'ay Timer
Normal

S

•

RSENSE
_'SENSEI
I

lk

Load

I
I

TLIH112317-11

FIGURE 3. Protection Comparator Biasing
3-69

Application Hints (Continued)
DELAY TIMER

a .manner that there is virtually no current flowing into the
non"inverting input of the comparator.' Therefore, only IREF
flows through resistor RTHRESHOLO. All of the Input bias
current; 20 p.A maximum, for· the comparator input stage
(twice the ISENSE specification of 10 p.A maximum, defined
for equal potentials on each of the comparator inputs) however flows into the inverting input through resistor RSENSE.
At the comparator threshold, the current through RSENSE
will be no more than the ISENSE specification of 10 p.A.

To allow the MOSFETto conduct currents beyond the prO'
tectiotl threshold ·for a brief period of time, a delay timer
fUnction is provided. This timer delays theaetual latching
01=Pof the MOSFET for a programmable interval. This feature is important to drive loads which require a surge of
current in excess of the normal ON current upon start· up, or
at any point in time, such as lamps and motors. Figure 4
details the delay timer circuitry. A capacitor connected from
the Delay pin 8, to ground sets the delay time interval. With
the MOSFET turned ON and all conditions normal, the output of the protection comparator is low and this keeps the
discharge transistor ON. This transistor keeps the delay capaCitor discharged. Should a surge of load current trip the
protectiorl comparator high;· the discharge transistor turns
OFF and an internal 10 p.A current source begins linearly
charging the delay capaCitor.

To tailor the VOS (MAX) threshold for any particullir fapplication, the resistor RTHRESHOLO ~n be selected per the following formula:
.
VOS (MAX) =

VREF X RTHR
.
R
":".(ISENSE X I'ISENSE)
REF
.

.

+ VOS

.

where RREF = 15.4 kO, 'ISENSE is the input bias current to
the protection comparator, RSENSE is the resistor connected to pin 1 and VOS is the offset voltage of the protection
comparator (typically in the range of ± 10 mV).

If the surge current, with excessive VOS voltage, lasts long
enough for the capaCitor to charge to the timing comparator
threshold of typically 5.5V, the OUtPllt of the comparator will
go high to set a flip-flop and immediately latch the MOSFET
OFF. It will not re-start until the ON/OFF Input is toggled
low then high.

The resistor RSENSE is optional, but is strongly recommended to provide transient protection for the Sense pin, especially when driving inductive type loads. A minimum value of
1 kO will protect the pin from transients ranging from - 25V
to + SOV. This resistor should be equal to, or less than, the
resistor used forRTHRESHOLO. Never set'RSENSE to a value
larger than RTHRESHOLO. When the protection comparator
output goes high, the total bias current for the input stage
transfers from the Sense pin to the Threshold pin, thereby
changing the voltages present at the inputs to the comparatOf. For consistent switching of the comparator right at the
desired threshold point, the voltage drop that occurs at the
non-inverting input (Threshold) should equal, or exceed, the
rise in voltage at the inverting input (Sense).

The delay time interval is set by the selection of COELAY and
can be found from:
T
OELAY =

(VTIMER X COELAY)
IOELAY

where typically VTIMER = 5.5V and IOELAY = 10p.A.
Charging of the delay capaCitor is clamped at approximately
7.5V which is the internal bias voltage for the 10 p.A current
source.

MINIMUM DELAY TIME

In automotive applications the load supply may be the battery of the vehicle whereas the Vee supply for tlie LM9061
is a switched ignition supply. When the Vee supply is
switched OFF there is always a concern for the amount of
current drained from .the battery. The only current drain under this condition is a leakage current into the Threshold pin
which is less than 10 p.A.

A minimum dl'llay time interval is required in all applications
due to the nature of the protection Circuitry. At the instant
the MOSFET is commanded ON, the voltage across the
MOSFET, Vos, is equal to the full load supply voltage because the source is held at ground by the load. This condition will immediately trip the protection comparator. Without
a minimum delay time set, the timing comparator will trip
and force the MOSFET to latch OFF thereby never allOwing
the load to be energized.

A bypass capaCitor across RREF is optional and is used to
help keep the reference voltage constant in applications
where the Vee supply is subject to high .Ievels of transient
noise. This bypass capaCitor should tie .no larger than
0.1 p.F, and is not needed for most applications.

Vee

5.5V

VTlMER

r>-__

Fr.om ON/OFF °l:put
OFF:.J

....I-_ _ _ _ _ _,

:

start Delay Time~

From Protection Comparator

>----------...1

Normal
TL/H/12317-12

FIGURE 4. Delay Timer

3-70

r-----------------------------------------------------------------------------~

Application Hints (Continued)

r
i:
CD

o
en

REVERSE BATTERY

To prevent this situation a delay capacitor is required at pin
8. The selection of a minimum capacitor value to ensure
proper start-up depends primarily on the load characteristics
and how much time is required for the MOSFET to raise the
load voltage to the point where the Sense input is more
positive than the Threshold input (TSTART-UP). Some experimentation is required if a specific minimum delay time characteristic is desired. Therefore:

The LM9061 is not protected against reverse polarity supply
connections. If the Vee supply should be taken negative
with respect to ground, the current from the Vee pin should
be limited to 20 mA. The addition of a diode in series with
the Vee input is recommended. This diode drop does not
subtract significantly from the charge pump gate overdrive
output voltage.

C
(IDELAY X TSTART-UP)
DELAY =
VTIMER

....

LOW BATTERY
As an additional protection feature the LM9061 incorporates
an Undervoltage Shut-OFF function. If the Vee supply to the
package drops below 7V, where it may not be assured that
the MOSFET is actually ON when it should be, circuitry will
automatically turn OFF the power MOSFET.

In the absence of a specific delay time requirement, a value
for CDELAY of 0.1 ",F is recommended.
OVER VOLTAGE PROTECTION

The LM9061 will remain operational with up to +26V on
Vee. If Vee increases to more than typically +30V the
LM9061 will turn off the MOSFET to protect the load from
excessive voltage. When Vee has returned to the normal
operating range the device will return to normal operation
without requiring toggling the ON/OFF input. This feature
will allow MOSFET operation to continue in applications that
are subject to periodic voltage transients, such as automotive applications.

Figure 6 shows the LM9061 used as an electronic circuit
breaker. This circuit provides low voltage shutdown, overvoltage latch OFF, and overcurrent latch OFF. In the event
of a latch OFF shutdown, the circuit can be reset by shutting
the main supply off, then back on. An optional reset switch
on the ON/OFF pin will allow a "push-button reset" of the
circuit after latching OFF.

For circuits where the load is sensitive to high voltages, the
circuit shown in Figure 5 can be used. The addition of a
zener on the Sense input (pin 1) will provide a maximum
voltage reference for the Protection Comparator. The Sense
resistor is required in this application to limit the zener current. When the device is ON, and the load supply attempts
to rise higher than (VZENER + VTHRESHOLD), the Protection
comparator will trip, and the Delay Timer will start. If the high
supply voltage condition lasts long enough for the Delay
Timer to time out, the MOSFET will be latched off. The ON/
OFF input will need to be toggled to restart the MOSFET.

Supply

Load Supply 7V to 18V

Ik

42k

Reset

I

~

TLlH/12317-14

FIGURE 6. Electronic Circuit Breaker

Scaling of the external resistor value, from Vee to the ON/
OFF input pin, with the internal 30k resistor can be used to
increase the startup voltage. The circuit operation then becomes dependent on the resistor ratio and Vee providing an
ON/OFF pin voltage being above the ON threshold rather
than the LM9061 low Vee shutdown feature.
DRIVING MOSFET ARRAYS
The LM9061 is an ideal driver for any application that requires multiple parallel MOSFETs to provide the necessary
load current. Only a few "common sense" precautions need
to be observed. All MOSFETs in the array must have identical electrical and thermal characteristics. This can be
solved by using the same part number from the same

ON/OFF
TLlH/12317-13

FIGURE 5_ Adding Over-Voltage Protection

3-71

•

Application Hints (Continued)
manufacturer for all of the MOSFETs in the array. Alsd, all
MOSFETsshouid have the;same style heat sink or,ideally,
all mounted on the' same heat sink. The electrical connection of the MOSFETs should get special attention. With typical ROS(ON) values in the range of tens of. milli-Ohms,. a
·poor electrical connection for one of the MOSFETs can render it useless in the circuit.
Figure 7 shows a circuit with four parallel NDP706A
MOSFETs. This particular MOSFET has a ,typical ROS(ON)
of 0.013Q with a TJ of ~5°C, and 0.0200 with a TJ of
+125°C.
., ,

With the Vos threshold voltage being set to 500 mV, this
circuit will provide a typical maximum load current of 150A
at 25°C, and a typical maximum load current of 100A at
125°C. The maximum dissipation, per MOSFET, will be
nearly 20W at 25°C; and 12.5W at 125°0. With up to 20W
being dissipated by each of the four devices, an effective
heat sink will be required to keep the TJ as low as possible
when operating near the maximum load currents.

100 Amp

. Load

.LOAD
SUPPLY

6.2k
0.47 J.'F

SWITCHED

SUPPLY

. ON/OFF
Input
TL/H/12317-15

FIGUR~ 7. Driving Multiple MOSFETs

3-72

Application Hints (Continued)
Load Supply

ON/OFF
TUH/12317-16

FIGURE 8. Increasing MOSFET Turn On Time
INCREASING MOSFET TURN ON TIME
The ability of the LM9061 to quickly turn on the MOSFET is
an important factor in the management of the MOSFET
power dissipation. Caution should be exercised when attempting to increase the MOSFET Tum On time by limiting
the Gate drive current. The MOSFET average dissipation,
and the LM9061 Delay time, must be recalculated with the
extended switching transition time.
Figure 8 shows a method of increasing the MOSFET Turn
On time, without affecting the Turn Off time. In this method
the Gate is charged at an exponential rate set by the added
external Gate resistor and the MOSFET Gate capacitances.
Although the LM9061 will drive MOSFETs from any manufacturer, National Semiconductor offers a wide range of
power MOSFETs. Figure 9 shows a small sample of the
devices available.

Part

ID

VDSS

ROSION)

Package
TO-220

NDP706A

75A

60V

0.0150

NDP706B

70A

60V

0.0180

TO-220

NDP708A

60A

80V

0.0220

TO-220

NDB708A

60A

80V

0.0220

TO-263

NDP606A

48A

60V

0.0250

TO-220

NDP606B

42A

60V

0.0280

TO-220

NDP608A

36A

80V

0.0420

TO-220

NDB608A

36A

80V

0.0420

TO-263

NDP508A

19A

80V

0.0800

TO-220

NDB508A

19A

80V

0.0800

TO-263

NDP408A

11A

80V

0.1600

TO-220

NDS9410

7A

30V

0.030

S0-8

NDS9936*

5A

30V

0.050

SO-8

NDS9945*

3.5A

60V

0.100

SO-8

• Dual

FIGURE 9. Recommended DMOS Power MOSFETs

3-73

•

tflNational Semiconductor

LMD18400
Quad High Side Driver
General Description

'Features

The LMD18400 is a fully protected quad high side driver. It
contains four common-drain DMOS N-channel power
switches, each capable of switching a continuous 1 Amp
load (>3 Amps transient) to a common positive power supply. The switches are fully protected from excessive voltage,
current and temperature. An instantaneous power sensing
circuit calculates the product of the voltage across and the
current through each DMOS switch and limits the power to a
safe level. The device can be disabled to produce a "sleep"
condition reducing the supply current to, less than 10 /l-A.
Separate ON/OFF control of each switch is provided
through standard LSTLLlCMOS logic compatible inputs.
A MICROWIRETM compatible serial data interface is built in
to provide extensive diagnostic information. This information
includes switch status readback, output load fault conditions
and thermal and overvoltage shutdown status. There are
also two direct-output error flags to provide an immediate
indication of a general system fault and an indication of excessive operating temperature.

• Four independent outputs with > 3A peak, 1A continuous current capability
• 1.30 maximum ON resistance over temperature
• True instantaneous power limit for each switch
• High survival voltage (60 Voe, 80V transient)
• Shorted load (to ground and supply) protection
• Overvoltage shutdown at Vee > 35V
• LS TTLICMOS compatible logic inputs and outputs
• < 10 /l-A supply current in "sleep" mode
• -5V output clamp for discharging inductive loads
• Serial data interface for 11 diagnostic checks:
- Switch ON/OFF status
- Open or shorted load
- Operating temperature
- Excessive supply voltage
• Two direct-output error flags'

The LMD~ 8400 is packaged in a special power diSSipating
leadframe that reduces the junction to case thermal resistance to approximately 20"C/W.

•
•
•
•
•

Applications
Relay and solenoid drivers
High impedance automotive fuel injector drivers
Lamp drivers
Power supply switching
Motor drivers

Typical Application

Connection Diagram

20
9
10

Switch
Select

""

Inputs

12

Inl
In 2
In 3

IO.OII'F

In 4

10kn

13

Error

+5V

0
0

...

Out 1

00

::E

Out 2

..J

Thermal

18

ThIiiMi

Shutdown

Out 3

Clock

Diagnostic

Output ...

18

output :5

Out ...

19

Thermal Shutdown

16

Ground

...

Ground

C

15

Ground

Clock

..J

14

C charge pump (Cop)

Data Output

13

Error

Input 1

12

Input ...

II

Input :5

0
0

00

::E

10

TL/Hlll026-2

Order Number LMD18400N
See NS Package Number N20A

Data Output

-=

17

Ground

Input 2

,CS

Data Output

Vee

19

Chip Select

C

Error

20

Enabl.

tnabl.

Enable

Output I
Output 2

-

TL/H1I1026-1

3-74

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Survival Voltage (Pin 20)
Transient (t = 10 ms)
Continuous

80V
-0.5Vto +60V

Output Transient Current (Each Switch)

6A

Output Steady State Current (Each Switch)

1A

Logic Input Voltage (Pins 4, 7)

16V

ESD Susceptibility (Note 2)

2000V

Power Dissipation (Note 3)

5W
Internally Limited
150"C

Junction Temperature (TJMax)
Storage Temperature Range

3.75A

Output Transient Current (Total, All Switches)
Logic Input Voltage (Pins 3, 9, 10, 11, 12)

Error Flag Voltage

-65·Cto + 150"C

Lead Temperature (Soldering, 10 Sec.)

+ 260"C

Operating Ratings (Note 1)

-0.3Vto +16V

-40"C to + 125·C

Ambient Temperature Range (Till

-0.3Vto +6V

Supply Voltage Range

6Vt028V

Electrical Characteristics Vee = 12V, cCP = o.ot ,...Fd, unless otherwise indicated. aoldfae.limits apply
over the entire operating temperature range, - 40·C ,;; TA ,;; + 125·C, all other limits ar~ for T A = TJ = + 25·C.
Parameter

Conditions

Typical
(Note 4)

(Note~)

Limit

Units
(Limit)

0.04
7.5

10
15

,...A(Max)
mA(Max)

7.5

15

mA(Max)

0.01

10,

,...A(Max)

0.8

1.3

o (Max)

1.2
2.4
0.6

0.8

A (Min)
A
A

DC CHARACTERISTICS
Supply Current

Output Leakage

Enable Input
Enable Input
Enable Input
Open Loads

=
=
=

OV
5V, Inputs
5V, Inputs

Enable Input = OV, Inputs
(Pins 1, 2, 18, 19)

= 1A, (Note 6)
= 12V, (Note 6)
= 6V, (Note 6)
= 28V, (Note 6)
- Vo = 4V, (Note 6)

=
=

OV
5V

=

OV

RdsON

lOUT

Short Circuit Current

Vee
Vee
Vcc

Maximum Output Current

Vee

3.75

A

Load Error ThreShold Voltage

Pins 1, 2,18,19

4.1

V

Open Load Detection Current

Pins 1, 2,18,19

150

,...A

Negative Clamp Output Voltage

10

=

-5

1A, (Note 6)

35

Overvoltage Shutdown Threshold

V
40

' 0.75

Overvollage Shutdown HystereSiS
Error Output Leakage Current

VPin13

Thermal Warning Temperature

VPin 13

Thermal Shutdown Temperature

VPin 17

= 12V
< 0.8V
< 0.8V

0.001

V (Max)
V

10

,...A(Max)

145

·C

170

·C

•
3·75

«:)
«:)

:....
c

Electrical Characteristics

Vee = 12V, CcP = 0.Q1 p.F, uolessotherwise indicated. Boldface limits apply
over the entire operating temperature range,. -40'C :5: TA :5: + 125'C, all other limits ar!!!; for T A = TJ "" + 25'C. (Continued)

,

::::E
....

Parameter

Conditions

Typical
(Note 4)

Limit
(Note 5)

!,Jnlts
(Limit)

5

10

p.s(Max)

15

p.s(Max)

AC CHARACTERISTICS
Switch Turn-On Delay
(Id(ON»

Enable (Pin 3) = 5V,
lOUT = 1ft.

Switch Turn-On Rise
Time (toN)

lOUT = 1A

Switch Turn-Off Delay
(tdOFF)

Enable (Pin 3) = 5V,
lOUT = 1A

Switch Turn-Off Fall
Time (tOFF)

lOUT = 1A

Enable Time (tEN)

7

..

p.s(Max)

0.5

2

0.15

1

p.s(Max)

Measured with Switch 1,
Pin 9 = 5V

30

50

p.s(Max)

Error Reporting Delay
(tError)

Enable (Pin 3) = 5V,
Switch 1 Load Opened

75

150

p.s(Max)

Data Setup Time (tos)

CL = 30pF

200

500

ns(Min)·

TRI-STATEQI> Control (t1H' toH)

Pin 8, Hi-Z Enable Time

1

MHz (Max)

2

.. 3

Data Clock Frequency

p.s

DIGITAL CHARACTERISTICS
Logic "1" Input Voltage

Pins3,4,7,9,10,11,12

2.0

V (Min)

Logic "0" Input Voltage

Pins 3, 4, 7, 9,10,11,12

0.8

V (Max)

Logic "1" Input Current

Pins 4, 7

0.001

1

p.A(Max)

Logic "0" Input Current

Pins 4, 7

-0.001

-1

p.A(Max)

TRI-STATE Output Current

Pin 8, Pin 4 = 5V
Pin 8 = OV

0.05
-0.05

10
-10

p.A(Max)
/LA (Max)
/LA (Max)

Enable Input Current

Pin3 = 2.4V

12

2S

Channel Input Resistance

Pins9,10,11,12

75

25

k.o.(Min)

Error Output Sink Current

Pin 13 = 0.8V

4

1.8

mA(Min)

Logic "1" Output Voltage

Pin8
lOUT = - 360 /LA
lOUT = -10/LA
lOUT = -10p.A

4.4
5.1

2.4
4.S
S.S

V (Min)
V (Min)
V (Max)

0.4

V (Max)

5

3

/LA (Min)

360

250

/LA (Min)

Logic "0" Output Voltage

Pin 8
lOUT = 100 !LA

Thermal Shutdown Output
Source Current

Pin 17 = 2.4V

Thermal Shutdown Output
Sink Current

Pin 17 = 0.8V

3-76

Electrical Characteristics Notes
Nota 1: Absolute Maximum Ratings indicate limits beyond which damage to the devioa may occur. Operating Ratings indicate condHions for which the device is'
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Nota 2: Human body model; 100 pF discharge through a I.S kll resistor. All pins except pins 8 and 13 which are protected to l000V and pins 1, 2, 18 and 19 which
are protacted to SOOV.
Nota 3: The maximum power dissipation is a function of TJMax' 6JA, and TA and is IimHed by thermal shutdown, The maximum allowable power dissipation at any
ambient temperature is Po = (TJMax - TA)/6JA. If this dissipation is exceeded, the die temperature will rise above ISO"C and the devioa will eventually go into
thermal Fhutdown. For the LMDI8400 the junction-te-ambient thermal resistsnoa, 6JA, is 6fJ'C/W. With sufficient heatsinking the maximum continuous power
dissipation for the package will be, IOCMax2 X RON(Max) X 4 switches (IA2 x 1.311 x 4 = S.2W).
Nole 4: Typical values are at TJ

=

+2S'C and represent the most likely parametric norm.

Note 5: All limits are 100% production tested at + 2S'C, Limits at temperabJre extremes are guaranteed through correlation and acoapted Statistical Quality
Control (SQC) methods,
Nota 6: Pulse Testing lechniques used. Pulse width is < S ms with a duty cycle < 1 %.

Timing Specification Definitions
SwItchIng Turn ON/OFF
[nable

Enable Turn-ON

= 5V

Channell Input

= 5V

+5V

+5Y

[nable
Input

Channel
Input

- - # - - - - 50%

OV

OV

Your

Your
Switch
Output

Switch
Output

1
OV _ _ _.I1

10%

O Y - -...."

TLlH/l1026-4

TL/H/ll026-3

Error ReportIng Delay
Channel

Data Setup TIme

1 output open circuited.

+5V

+5V

Chip Select

Channell
Input

OV

OV

+5V

+5V
Error nag
output

Clock

50%

OV

OV

TLlH/l1026-6

TLlH/ll026-5

•
3-77

Typical Performance Characteristics
For all curves, Veo = 12V, Temperature is the junction temperature unless otherwise noted.

Switch ON Resistance
vs Temperature

Maximum Power
DiSSipation vs
Ambient Temperature

"Sleep" Mode Supply Current
vs Temperature

1.3

1.2

I'

V

1.1

Sz

BJl'\ r-I\
=
f\

I.akage current.

10

II

0

}

1

= ov

Enable

Outputs ground6d
Include. output

0.9

...

vi-""

0.7

1/

I.....

t-

0.6
80

120

40

160

TEMPERATURE (OC)

80

120

160

II
o

o
40

BO

120

160

!

!

~

= lA

r-

+--I-+-+--H

i!:

I
i

I'L

BO

120

4
-40

160

1.6

~~

~

1.2

'l:
;:

1.0

160

r-

I
'LOAD

120

160

1.1

= 1A

...

40

80

120

160

40

BO

TEMPERATURE (Oc)

Enable Threshold Voltage
vs Temperature

E

140

100

I'

V

~

!il

80

Error Output Voltage
vs Sink Current

1//
40

1.5

i
80

TEMPERATURE (OC)

120

16b

LlVv

2.0

1---c~-4-+-+-+~-+-+--l

E

1..1 I...-L-.!--'-'--'--'---'-....L..-'--'
-40
40
BO
120
160
TEMPERATURE (OC)

~I II

>§
1.0

i!:

............

40
-40

--

~

II

120

60

120

3.0
(Pin. 9,10, II, 12)

!'

80

11.6

160

~

40

TEMPERATURE (OC)

Switch Select Logic Input
Resistance vs Temperature

~

r-r-

3.6
M

1.8

,..... 1-'"

TEMPERATURE (OC)

!
~

r-1"

3.8

Turn OFF Time
vs Temperature

J

b-"~

0L-L-~~~~-L~~

40

160

1A

t::±:t::I:+1'-1r-tfii
0

120

TEMPERATURE (OC)

1 1
ILOAO = lA

20

-40

1'1"-

3.2
-40

3or-~H~-4-+-+~~

10

80

r--.

01.0

Tum ON Delay Time
vs Temperature

5°,..-,--r-r11-'-1r-T""T""T--t"-1
ILOAO

4.2

NEGATIVE CLAMP VOLTAGE

Turn ON Rise Time
vs Temperature

r-

~

~

V.

~

E

01.4

3

TEMPERATURE (OC)

40

~

-200t

V

V

0.5

"~

40

01.6

II
lL

V

I' '~

Error Sense Threshold
Voltage vs Temperature

~

250C

J

~I-~

V

-40

0

I' "

AMBIENT TEMPERATURE (OC)

I

j...."" 1-1-

-40

Clamp Characteristics
va Temperature
1500c

1.5

o

1

TEMPERATURE (OC)

Short Circuit Current
vs Temperature

t~

11

)
40

~~~~k r-

f'..1

i-""

-40

Infinite

330 C/W

o
o

2SOC

Vv

~~ V
2

4

6

8

10

SINK CURRENT (mA)
TLlH/l1026-7

3-78

Functional Block Diagram
OUTPUT 1

1 r------~~---...,

OUTPUT 2

2

r-----------...,
.--+--+--+.....-+--r-----f 18

OUTPUT 3

fiiE'iiWAL
SHUTDOWN

GROUND

G::t..
rGGROUND

CLOCK

7

r--t-+"I>

Applications Information
BASIC OPERATION
High-side drivers are used extensively in automotive and
industrial applications to switch power to ground referred
loads. The major advantage of using high-side drive, as opposed to low-side drive, is to protect the load from being
energized in the event that the load drive wire is inadvertently shorted to ground as shown in Figure.1. A high-side
driver can sense a shorted conditi.on and open the power
switch to disable the load and eliminate the excessive current drain on the power supply. The LMD18400 can control
and protect .uP to four separate ground referenced loads.

The LMD18400 can be continually connected to a live power source, a car battery for example. while !!rawing .Iess than
10 IJoA from the power source when put into a "sleep" condition. This "sleep" mode is enacted by taking the Enable
Input (pin 3) low. During this mode the supply current for the
device. is typically only 0.04 1JoA. Special low current consumption standby circuitry is used to hold the DMOS
switches OFF to eliminate the possibility of supply voltage
transients from turning on any o( thilioads (a common problem with MOS power devices). When in the "sleep" mode,
all diagnostic and logiC circuitry is inactive. When the Enable
Input is taken to a logic 1, the switches become "armed"
arid ready to respond to their control input after a short,
30 /Jos, enable delay time. This delay interval prevents the
switches from transient turn-on. Figure 2 shows the switch
control logiC,

. yw
High Side Drive

nsed1l

Short can be ..
and tho switch can bo
oponed

,.L'

.

,:".

Load

Output

TLlH/11026-9

Low Side Drive
Enable

- -......--ov+

c~~~:~ 0------1
Load

ShT:t~::r~ 0---....1
O¥;~~~=:!~ o----....J

:

,.L

Short will onorglzo
thaloed

TLlH/11026-11

FIGURE 2. Control Logic for Each Power Switch
Each DMOS switch is turned ON when its gate is driven
approximately 3.5V more positive than its. source voltage.
Because the source of the switch is the output terminal to
the load it ca.n be taken to a voltage very near the Vee
supply potential. To ensure that there is sufficient voltage
available to drive the gates. of the DMOS device a charge
pump circuit is built in. This circuit is controlled by an internal
300 kHz oscillator and using an external 10 nF capacitor
connected from pin 14 to ground generates a voltage that is
approximately 20V greater than the Vee supply voltage.
This provides sufficient gate voltage drive for each of the
switches which is applied under command of standard 5V
logic input levels.

.1
TL/H/11026-10

FIGURE 1. High-Side VB Low-Side Drive
.
The LMD18400 combines low voltage CMOS logic control
circuitry with a high voltage DMOS process. Each DMOS
power switch has an individual ON/OFF control input. WhIm
commanded ON, the output of the switch will connect the
load to the Vee supply through a maximum resistance of
1.30 (the ON resistance of the DMOS switch). The voltage
applied to the load will depend upon the load current and
the designed current capability of the LMD18400. When a
switch is commanded OFF, the load will be disconnected
from the supply except for a small leakage current of typically less than 0.Q1 /JoA.

The turn-on time for each switch is approximately 12 /JoS
when driving a 1A load current. This relatively slow switching ~ime is beneficial in minimizing electromagnetic interierence (EMI) related problems created from switching high
current levels.

3-80

r

Applications Information

Ii:

(Continued)

The LMD18400 has extensive protection circuitry built in.
With any power device, protection against excessive voltage, current and temperature conditions is essential. To
achieve a "fail-safe" system implementation, the loads are
deactivated automatically by the LMD18400 in the event of
any detected overvoltage or over-temperature fault conditions.
Voltage Protection
The Vee supply can range from -0.5V to +60 VDe without
any damage to the LMD18400. The CMOS logic circuitry is
biased from an internal 5.1 V regulator which protects these
lower voltage transistors from the higher Vee potentials. In
order to protect the loads connected to the switch outputs
however, an overvoltage shutdown circuit is employed.
Should the Vee potential exceed 35V all of the switches are
turned OFF thereby disconnecting the loads. This 35V
threshold has 750 mV of hysteresis to prevent potential oscillations.
Additionally, there is an undervoltage lockout feature built
in. With Vee less than 5V it becomes uncertain whether the
logic circuitry can hold the switches in their commanded
state. To avoid this uncertainty, all of the switches are
tumed OFF when Vee drops below approximately 5V.
Figure 3 illustrates the shutoff of an output during a OV to
80V Vee supply transient.

. . OV

.....-

-

- ~
.oj ~

8

~

Switch comes 'on'
to conduct load
current

VOUTh-

I-

Vour

!

IL

OV--5V

-1.'
TL/H/11026-13

FIGURE 4. Turn-OFF Conditions with an Inductive Load

When the output inductance produces a negative voltage,
the gate of the DMOS transistor is clamped at OV. At
-3.5V, the source of the power device is less than the gate
by enough to cause the switch to turn ON again. During this
negative transient condition the power limiting circuitry to
protect the switch is disabled due to the gate being held at
OV. The maximum current during this clamping interval,
which is equal to the steady state ON current through the
inductor, should be kept less than 1A. Another concern during this interval has to do with the size of an inductive load
and the amount of time required to de-energize it. With larger inductors it may be possible for the additional power dissipation to cause the die temperaure to exceed the thermal
shutdown limit. If this occurs all of the other switches will
turn OFF momentarily (see section on Thermal Management).

.......

OV~~~+-+-+-~~~~~
40V

I.......

+3.5V _ -

vee

Your

CD

---""-0 Vee

Over/Under
Voltage Shutdown

SOV

...
C

The LMD18400 has been deSigned to drive all types of
loads. When driving a ground referenced inductive load
such as a relay or solenOid, the voltage across the load will
reverse in polarity as the field in the inductor collapses when
the power switch is turned OFF. This will pull the output pin
of the LMD18400 below ground. This negative transient
voltage is clamped at approximately -5V to protect the IC.
This clamping action is not done with diodes but rather the
power DMOS switch turning back on momentarily to conduct the inductor current as it de-energizes as shown in
Figure 4.

PROTECTION CIRCUITRY

f--t--+--+-++-+-+-+-I-I

r..... '-

Vert: 20VIDIV Harlz: 10 ms/DIV

Power Limiting

TLlH/11026-12

FIGURE 3. Overvoltage/Undervoltage Shutdown

The LMD18400 utilizes a true instantaneous power limit circuit rather than simple current limiting to protect each
switch. This provides a higher transient current capability
while still maintaining a safe power dissipation level. The
power dissipation in each switch (the product of the Drain-to
Source voltage and the output current, Vds X lOUT) is con-

3-81

•

Applications Information

(Continued)
This dynamic current limiting of the switches is beneficial.
when driving lamp ,~nd large capacitive loads. Lamps require ~Ia:r.geinrush current, on the order of 10 times the
normal operating current, when first switched on with it cold
filament. The LMD18400 will limit this initial current to the
level where 15W is diSsipated in the switch'. ft,s th!l fil~ment
warms IJP the voltage across the lamp ,increases thereby
decreasing the voltage across the switch which permits
more current to fully light the lamp. With limited inrush curent the lifetime of a lamp load is increased significantly.
Figure 6 illustrates the soft turn-on of a lamp load.
The same principle of increasing output current as the voltage across the load increases ,allows large capacitive loads'
to be charged more quickly by an LMD18400 driver than as
opposed to a driver with a fixed 1A current limit protection
scheme.. Figure 7 shows the output response while driving a
large capacitive load.

tinually monitor,ed and limited to 15W by varying the gate
voltage and therefore the ON resistance of the switch. Basically the ON resistance will be as low as possiQle until 15W
is being disSipated. To maintain 15W, the ON, resistance
increases to reduce the ,load current. This results in a decrease of the output voltage. For resistive loads, the output
voltage when in power limit will be:

VOUT (in Power Limit) =

Vee -

NeC 2

60 RL .'

2

This provides a maximum transient current and drain-tosource voltage characteristic as shown in Figure 5.

"~

3r-~~----+----+--~1-----r---~

2

Thermal Protection

I" i ' (
/

The die temperature of the LMD18400 is continually monitored. Should any conditions cause the die temperature to
rise to + 170·C, all of the power switches are turned OFF
automatically to reduce the power dissipation. It is important
to realize that the thermal shutdown affeCts all four of tlie
switches together. That iS,if just one switc;:h load is enough
to heat the die to the thermal shutdown threshold, all of the,
other switches, regardless of their ppwer dissipation conditions, will be switched OFF. All of the switches will be re-enabled when the die temperature has cooled to approximately + 160·C. Until the high temperature forcing conditions
have been removed the switches will cycle ON and OFF
thus maintaining an average die temperature of + 165·C.
The LMD1 8400 will signal that excessive temperatures exist
through several diagnostic output signals (see Diagnostics).

" 1 5 Watt Power Limit

,
-----;.-_..1

1~--~----+-~~~~1-----r---~

V

On Resistance
Current Limit

I
5

10

15

20

25

30

SWITCH DR~IN - SOURCE VOLTAGE (V)
TUH/11026-14

FIGURE 5. Maximum Output Current with
Instanta!:'e9us Power Limiting
Driving a Lamp
Vee

= 12V

- 12V, 2A

Driving a Large
Capacitive Load

Lamp ±-+-+-+-+--l

=
=

Vee 12V
CLOAD 4700l'Fd -t--t--+-+--l

Your

OV

..... 1--

~I

v

Vert: 5V/DIV Horlz: 100 ms/DIV
, TUH/11026-15

FIGURE 6. Soft Turn-On of a Lamp Load
Vert: 5V/DIV Horlz: 20 ms/DIV

The steady state current to the load is limited by the package power dissipation, ambient temperature and the ON resistance of the switch which has a positive temperature coefficient as shown in the Typical Performance Characteristics.

TL/H/11026-16

FIGURE 7. Driving a Large Capacitive Load

3-82

r-----------------------------------------------------------~r

Applications Information

s::::

(Continued)

DIAGNOSTICS

tion, one for each channel in succession (see Load Error
Detection).

The LMD18400 has extensive circuit diagnostic information
reporting capability. Use of this information can produce
systems with intelligent feedback of switch status as well as
load fault conditions for troubelshooting purposes. All of the
diagnostic information is contained in an 11-bit word. This
data can be clocked out of the LMD18400 in a serial fashion
as shown in Figure 8. The shift register is parallel loaded
with the diagnostic data whenever the Chip Select Input is
at a Logic 1 and changes to the serial shift mode when Chip
Select is taken to a Logic O. The Data Output line (pin 8) is
biased internally from a 5.1 V regulator which sets the Logic
1 output voltage. This pin has low current sourcing capability
so any load on this pin will reduce the Logic 1 output level
which is guaranteed to be at least 2.4V with a 360 ",A load.

Bits 5 through 8 provide a ~eadback of the commanded
ON/OFF status of each switch.

o
....

§

A unique feature of the LMD18400 is that it provides an
early warning of excessive operating temperature. Should
the die temperature exceed + 145°C, bit 9 will be set to a
Logic O. Acting on this information a system can be programmed to take corrective action, shutting OFF specific
loads perhaps, while the LMD18400 is still operating normally (not yet in thermal shutdown). If this early warning is
ignored and the device continues to rise in temperature, the
thermal shutdown circuitry will come into action at a die temperature of + 1700C. Should this occur bit 10 of the diagnostic data stream will be set to a Logic 0 indicating that the
device is in thermal shutdown and all of the outputs have
been shut OFF.

The data interface is MICROWIRE cOmpatible in that data is
clocked out of the LMD18400 on the falling edge of the
clock, to be clocked into the controlling microprocessor on
the rising edge. Any number of devices can share a common data output line because the data output pin is held in a
high impedance (TRI-STATE) condition until the device is
selected by taking its Chip Select Input low. Following Chip
Select going low there is a short data setup time interval
(500 ns Min) required. This is necessary to allow the first
data bit of information to be established on the data output
line prior to the first rising clock edge which will input the
data bit into the controller. When all 11 bits of diagnostic
data have been shifted out the data output goes to a Logic 1
level until the Chip Select line is returned high.

The final data bit, bit 11, indicates an overvoltage condition
on the Vee supply (Vee is greater than 35V) and again indicates that all of the drivers are OFF.
The diagnostic data can be read periodically by a controller
or only in the event of a general system error indication to
determine the cause of any system problem. This general
indication of a fault is provided by an Error Flag output (pin
13). This pin goes low whenever any type of error is detected. There is a built-in delay of approximately 75
from the
time an error is detected until pin 13 is taken low. This is to
help mask short duration error conditions such as may be
caused by driving highly capacitive loads (>2 ",F). A lamp
load may generate a shorted load error for several hundred
milliseconds as it turns on which should be ignored.

"'S

Figure 8 also indicates the significance of the diagnostic
data bits. The first 4 bits indicate an output load error condi-

CHIPSELE~ -----,~:~------------------------------------------------------------~r__
CLOCK

DATA OUTPUT

Tri-State
BIT

#

2
CHI

CH2

CH3

4

5

CH4

CHI

~----''Vr----'

ERROR STATUS

CH2

7

8

CH3

CH4

10

11

~--------'V~--------~
ON/orr STATUS

LOAD OK

SWITCH orr

LOAD ERROR

SWITCH ON

[

TL/H/11026-17

FIGURE 8. Serial Diagnostic Data Assignments

3-83

-

C)

~
ell>

....
Q
~

r-------------------------------------------------------------------------------------,
Applications Information (Continued)
The Error Flag output pin is an open drain transistor which
requires a pull-up resistor to a positive voltage of up to lBV.
Typically this pull-up is to t.he same.5V supply which is biasing the Enable input and any other external logic circuitry.
The Error Flag pins of several LMD18400 packages can be
connected together with just one pull-up resistor to ·provide
an all-encompassing general system error indication. Upon
detection of an error, each device could then be polled for
diagnostic information to determine the source of the fault
condition.

LOAD ERROR DETECTION
An important feature of the LMD18400 is the ability to de'
tect open or shorted load connections. Figure 10 illustrates
the detection circuit used with each of the drivers.

Vee

A second direct output error flag is for an indication of Thermal Shutdown (pin 17). This active low flag provides an immediate indication that the die temperature has reached.
+ 170"C and that the drive to all four switches has been
removed. This output is pulled up to.the internal 5.1V logic
regulator through a small (5 p.A) current source so use of a
buffer on this pin is recommended.
+S.%V Bias

...../"1

Active Low
Error Indication ~

.;,.W

+5V

Reference -

TUHI11026-19

FIGURE 10- Detection Circuitry
for Open/Shorted Loads

47kn

+-......_1-0'7_.-... ~~::~~:a:hutdown

J

o

,

A voltage comparator monitors the voltage to the load and
compares it to a fixed 4.1 V reference level. When a switch is
OFF, the ground referenced load should have no voltage
across it. Under this condition, an internal 50 kO resistor
connected to Vee will provide a small amount of current to
the load. If the load resistance is large enough to create a
voltage greater than 4.1V an Open Load Error will be indicated tor that switch. The maximum load resistance that will
not generate an Open Load Error when a switch is OFF cali
be found by:

r- 1 Shutdown
"FeU $.""

--I

Input

Open CoUeclor

Inverter or Buffer
LMD18400
TUH/l1026-18

FIGURE 9_ Thermal Shutdown Flag and Shutdown Input
A useful feature of pin 17 is that it can also be used as a
shutdown input. Driving this pin low immediately switches all
of the drivers OFF, just the same as if thermal shutdown
temperatures has been reached, yet all of the control logic
and diagnostic circuits remain active. This is useful in designing "fail-safe" systems where the loads can be disabled
under any sort of externally detected system fault condition.
The diagnostic logic however does not distir'lguish between
normal thermal shutdown or the fact .that pin 17 has been
driven low. As such, various switch errors and an over-temperature indication will be reported in the diagnostic data
stream.

RMax = V 4.1 V BV x 50 kO; for no Open Load Indication
ee - 4.
To make this Open Load Error threshold more sensitive, an
external pull-up resistor can be added from the output to the
Vee supply.
Also when a switch is commanded OFF, should the load be
shorted to the Vee supply, this same circuitry will again indicate an error.
When a switch is commanded ON, the load is expected to
have a voltage across it that approaches the Vee potential.
If the output voltage is less than the 4.1 V threshold an error
will again be reported, indicating that the load is either shorted to ground or that the driver is in power limit and not able
to pull the output voltage any closer to Vee. The minimum
load resistance that will not generate a. Shorted Load Error
when a switch is ON can be found by:

Figure 9 illustrates the use of pin 17 as both an output thermal shutdown flag and as an input to shut down only the
switches. Directly tying pin 17 to + 5V will prevent the internal thermal shutdown circuitry from disabling the switches.
For reliability purposes however this is not recommended as
there will then be no limit to the maximum die temperature.

RMin =

Refer to the Truth Table for a summary of the action of
these direct-output error flags.

3-84.

4.1V{Vee - 4.1V)
15W
; for no Shorted Load Error

Applications Information (Continued)
Figure 11 indicates the range of load resistance for normal
operation, open load, and shorted load or power limit indication.
40k

S...

.......
...iii

I
I
I
Detected as an
"xopen Load

\

20k

(.)

z

10k

If ,..,.

II)

II<

...9
0

The LMD18400 is packaged with a special leadframe that
helps dissipate heat through the two ground pins on each
side of the package. The thermal resistance from junctionto-case (IIJcl for this package is approximately 20"C/W.
The thermal resistance from junction-to-ambient (IIJA>, without any heatsinking, is approximately 60'C/W. Figure 12 illustrates how the copper foil of a printed circuit board can
be designed to provide heatsinking and reduce the overall
junction-to-ambient thermal resistance.

I

~

30k

Careful calculation of the worst case total power dissipation
required at any point in time, together with providing sufficient heatsinking will prevent this from occurring.

1k

Normal Operation

10

5

~

0
5

10

.........

15

~ ~
Detected as a

20

The power dissipation in each switch is equal to:
-

(Vee - VOUT)2
or -'--='=-R--=------1 Enable

10kJl.
13
+5V 0-.....-.J\IV'v'-1-t Error
Error ~--+-----I

.

Oull

::Ii

Oul2

0
0

IlO

Q

2

IN4001

...J

17

Thermal Shuldown
HC126

CS

Clock
Diagnostic
Dala Oulpul

4

Thermal

Oul3

18

CS
Clock

Ou\4

Dala Oulpul

S
Schottky
Diode

19

Lamp
Load

16

INS819

recommended
TLlH/ll026-26

3-88

ri:

Applications (Continued)

C
....

CO
~

o
o

Simple Light "Chaser"

Shlfl
R.glat~r

O.lpF

...

5Hz,to 10Hz O-~---Clock

+5V

••••

TUH/ll026-29

Parallelling switches for higher current capability. Positive temperature coefficient of the switch ON resistance
provides ballasting to evenly share the load current between the switches. Any combination of switches can be
paralleled. Required peak load current will depend upon the motor load. Motor speed control can be provided by a
PWM signal of up to 20 kHz applied to the motor drive Input lines.

TlIH/ll026-30

3-89

tJ1

Nat ion a I S e m i con du c tor

Low-Dropout Voltage Regulators
Definition of Terms
Dropout Voltage: The input-voltage differential at which
the circuit ceases to regulate against further reduction in
input voltage. Measured when the output voltage has
dropped 100 mV from the nominal value obtained at (VOUT
+ 5V) input, dropout voltage Is dependent upon load current and junction temperature.
Input Voltage: The DC voltage applie(j to the input terminals with respect to ground.
Input-Output Differential: The voltage difference between
the unregulated input voltage and the relllliated output voltage for which the regulator will operate.

Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.
Long Term Stability: Output voltage stability under accelerated life-test conditions after 1000 hours with maximum
rated voltage and junction temperature.
Output Noise Voltage: The rms AC voltage at the output,
with constant load and no input ripple, measured over a
specified frequency range.
Quiescent Current That part of the positive input current
that does not contribute to the positive load current. The
regulator grQund lead current.
Ripple Rejection: The ratio of the peak-to-peak input ripple
voltage to the peak-to-peak output ripple voltage.
Temperature Stability of VO: The percentage change in
output voltage for a thermal variation from room temperature to either temperature extreme.

Lllle Regulation: The change In output voltage for a
change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantlyaffected.

3-90

Output
Current
(A)

1.0
0.75
0.5

0.1

'"~

0.05

Output
Voltage

Device

(V)

LM2940
LM2940C
LM2925
LM2935
LM2926
LM2927
LM2937
LM2984
LM2931
LM2931C
LP2950C
LP2950AC
LP2951
LP2951C
LP2951AC
LM2936

Typical
Dropout
Voltage

5,8,12,15
5,9,12,15
5
Two 5V Outputs
5
5
5,8,10,12,15
Three 5V Outputs
5
Adj. (3 10 29)
5
5
5, Adj. (1.24V to 29)
3.0, 3.3, 5, Adj. (1.24V 10 29)
3.0,3.3,5, Adj. (1.24V 10 29)
5

Typical
Quiescent
Current
(mA)

Reverse
Polarity
Protection

(V)'

Maximum
Input
Voltage
(V)

(V)

(V)

0.50
0.50
0.82
0.82
0.35
0.35
0.50
0.53
0.30
0.30
0.38
0.38
0.38
0.38
0.38
0.4

26
26
26
26
26
26
26
26
24
24
30
30
30
30
30
40

10
10
3
3
2
2
2
14
0.400
0.400
0.075
0.Q75
0.Q75
0.Q75
0.075
0.009

-15
-15
-15
-15
-18
-18
-15
-15
-15
-15

+60"/-50
+45/-45
+60"/-50
+60"/-50
+80"/-50
+80"/-50
+60"/-50
+60"/-35
+60"/-50
+60"/-50

"Guaranteed maximum dropout voltage at full load over temperature.
"Positive transient protection value also indicates the regulator's load dump capability.

-15

Transient
Protection

+60/-50

Operating
Temperature
(Tj·C)

Page
No.

-5510 + 150
010+150
-4010 +150
-4010 +150
-4010 +125
-4010 +125
-40 to +125
-40 to +150
-40 to +125
-40 to +125
-4010 +125
-40 to +125
-55to +150
-4010 +125
-4010 +125
-4010 +125

3·154
3·154
3·114
3·136
3·120
3·120
3·149
3·179
3·128
3·128
3·164
3·164
3·164
3·164
3·164
3·144

~
~

~

r

0

:e

c...

0

..
.....

"0

0

c:

::D
CD

ca
c:

........
Q
;:I

~

V)
~

-.
~

C"')

0
~

~
~

Dr

.....

0

0

fI)

C"')

~

en
CD

-n

..o·
CD

::::J
C)

c:

a:
CD

ep!n9 UO!I:>eles SJOl81n6el:llnodoJQ M01

iii

f}1National Semiconductor'

LM 1577/LM2577 Series,
SIMPLE SWITCHER® Step-Up Voltage Regulator
General Description

Features

The LM1577/LM2577 are monolithic integrated circuits that
provide all of the power and control functions for step-up
(boost), flyback, and forward converter switching regulators.
The device is available in three different output voltage versions: 12V, 15V, and adjustable.
Requiring a minimum number of external components,
these regulators are cost effective, and simple to use. Listed
in this data sheet are a family of standard inductors and
flyback transformers designed to work with these switching
regulators.

•
•
•
•

Included on the chip is a 3.0A NPN switch and its associated protection circuitry, consisting of current and thermal limiting, and undervoltage lockout. Other features include a 52
kHz fixed-frequency oscillator that requires no external components, a soft start mode to reduce in-rush current during
start-up, and current mode control for improved rejection of
input voltage and output load transients.

Requires few external COmponents
NPN output sWitches ,3.0A, can stand off: 65V
Wide input voltage range: 3.5V to 40V
Current-mode operation for improved transient
response, line regulation, arid current limit
• 52 kHz internal oscillator
• Soft-start function reduces in-rush current during,
start-up
• Output switch protected by current limit, under-voltage
lockout, and thermal shutdown

Typical Applications
• Simple boost regulator
• Flyback and forward regulators
• Multiple-output regulator

Typical Application
+5V
INPUT

1

IN5821
100J.'H.f'

O.'J.'F

T

I
-

12V@S800mA

~_......,"'~-",--",,-o() REGULATED OUTPUT
VOUT = 1.23V (I + RI/R2)
.-5.a...;
IVI;;.N_ _4..1'I..S...
WITCH
• R1
+

0---.-+
~___........r

T""'"

COMP

17.4k
...2=:--.....
FEED__.1 BACK
~ R2

----; LM2577-ADJ
...._ _. -_

2.2k

1

3 GND

1

680 J.'F

_

2k

-='=-=

Note: Pin numbers shown
are for T0-220
package.

m

TL/Hh,468-,

Ordering Information
Temperature
Range

~:' ,

Type

-40"C:>: TA:>: +125°C 24-Pin Surface Mount
16-Pin Molded DIP
5-Lead Surface Mount
5-Straight Leads
5-Bent Staggered Leads
-55°C:>: TA:>: +150"C4-PinTO-3

NSC

Output Voltage

Package
12V

15V

ADJ

Package Package
Drawing

LM2577M-ADJ
M24B
LM2577M-12
LM2577M-15
LM2577N-ADJ
LM2577N-12
LM2577N-15
N16A
LM2577S-12
LM2577S-ADJ
LM2577S-15
TS5B
, LM2577T-ADJ
LM2577T-12
LfI.12577T-15
T05A
LM2577T-12
LM2577T-15
T05.o
LM2577T-ADJ
Flow LB03
Flow LB03
flow LB03
LM1577K-12/883 LM1577K-15/883 LM1577K-ADJ/8,83 K04A

3-92

SO
N
TO-263
TO-220
rO-220
TO-3

Absolute Maximum Ratings

Operating Ratings

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

45V

Output Switch Voltage
Output Switch Current (Note 2)

65V
6.0A

Power Dissipation

3.5V :s; VIN :s; 40V

Supply Voltage
Output Switch Voltage

OV:S; VSWITCH :s; 60V

Output Switch Current

ISWITCH :s; 3.0A

Junction Temperature Range
LM1577
LM2577

-55·C:S; TJ:S; +150·C
-400C:S; TJ:S; +125·C

internally Limited
-65·Cto + 150·C

Storage Temperature Range
Lead Temperature (Soldering. 10 sec.)

2600C

Maximum Junction Temperature

150·C

Minimum ESD Rating
(C = 100 pF. R = 1.5 kn)

2kV

Electrical Characteristics-LM1577-12, LM2577-12
Specifications with standard type face are for TJ = 25·C. and those in bold type face apply over full Operating Temperature
Range. Unless otherwise specified. VIN = 5V. and ISWITCH = o.
Symbol

Parameter

Conditions

Typical

LM1577-12
Limit
(Notes 3, 4)

LM2577-12
Limit
(Note 5)

11.60/11.40
12.40/12.60

11.60/11.40
12.40/12.60

Units
(Limits)

SYSTEM PARAMETERS Circuit of Figure 1 (Note 6)
VOUT

Output Voltage

AVOUT
AVIN

Line Regulation

AVOUT

Load Regulation

ALOAD
'Ii

Efficiency

VIN = 5Vto 10V
ILOAD = 100 mAt0800 mA
(Note 3)

12.0

VIN = 3.5V to 10V
ILOAD = 300 mA

20

VIN = 5V
ILOAD = 100 mAt0800 mA

20

VIN = 5V. ILOAD = 800 mA

80

VFEEDBACK = 14V (Switch Off)

7.5

V
V(min)
V(max)

50/100

50/100 .

mV
mV(max)

50/100

50/100

mV
mV(max)

%

DEVICE PARAMETERS
Is

Input Supply Current

ISWITCH = 2.0A
VCOMP = 2.0V (Max Duty Cycle)
Vuv

fo

VREF

AVREF
AVIN

Input Supply
Undervoltage Lockout

ISWITCH = 100 mA

Oscillator Frequency

Measured at Switch Pin
ISWITCH = 100 mA

10.0/14.0

mA
mA(max)

50/85

50/85

mA
mA(max)

2.70/2.65
3.10/3.15

2.70/2.65
3.10/3.15

V
V(min)
V(max)

48/42
56/62

48/42
56/62

kHz
kHz(min)
kHz(max)

11.76/11.84

11.76/11.84
12.24/12.36

V
V(min)
V(max)

25
2.90

52

Output Reference
Voltage

Measured at Feedback Pin
VIN = 3.5V to 40V
VCOMP = 1.0V

Output Reference
Voltage Line Regulator

VIN = 3.5Vt040V

12

12.24/12.36
7

mV

9.7

kO

RFB

Feedback Pin Input
Resistance

GM

Error Amp
Transconductance

ICOMP = -30 p.A to + 30 p.A
VCOMP = 1.0V

370

Error Amp
Voltage Gain

VCOMP = 1.lVto 1.9V
RCOMP = 1.0 MO
(Note 7)

80

AVOL

10.0/14.0

3·93

515/615

225/145
515/615

p.mho
p.mho(min)
p.mho(max)

50/25

50/25

VIV
VIV(min)

225/145

Characteristics-LM1577·-12,

Electrical
LM2577-12 (Continued)
Specifications witl1 standard type face are for TJ = 25°C, and those in bold type face apply over full Operating Temperature
~ange. Unless otherwise specified, VIN= 5V, and ISWITCH = O.
Symbol

Parameter

Typical

Conditions

LM1577-12
Limit
(Notes 3, 4)

LM2577-12
Limit
(Note 5)

2.2/2.0

~.2/2.0

V
V(min)

0.40/0.55

0.40/0.55

V
V(m8l<)

±130/±90
±30b/±400

±130/±90
±300/±400

p.A
p.A(min)
p.A(max)

2.5/1.5
7.5/9.5

2.5/1.5
7.5/9.5

p.A
p.A(min)
p.A(max)

93/80

93/90

%
%(min)

Units
(Limits)

DEVICE PARAMETERS (Continued)
Error Amplifier
Output Swing

Iss

D

Upper Limit
VFEEDBACK = 10.0V

2.4

Lower Limit
VFEEDBACK = 15.0V

0.3
±200

Error Amplifier
Output Current

VFEEDBACK = 1O.OV to 15.0V
VCOMP = 1.0V

Soft Start Current

VFEEDBACK = 10.0V
VCOMP = OV

5.0

VCOMP = 1.5V
ISWITCH = 100 mA

95

Maximum Duty Cycle

AISWITCH
AVCOMP

Switch
Transconductance

IL

Switch Leakage
Current

VSWITCH = 65V
VFEED!3ACK = 15V (Switch Off)

10

Switch Saturation
Voltage

ISWITCH = 2.0A
VCOMP = 2.0V (Max Duty Cycle)

0.5

VSAT·

12.5

NPNSwitch
Current Limit

AN

300/800

300/800

/LA
p.A(max)

0.7/0.9

0.7/0.9

V
V(max)

3.7/3.0
5.3/8.0

3.7/3.0

4.5

3-94

5.318.0

A
A(min)
A(max)

Electrical Characteristics-LM1577-15, LM2577-15
Specifications with standard type face are for TJ = 25'C, and those in bold type face apply over full Operating Temperature
Range. Unless otherwise specified, VIN = 5V, and ISWITCH = O.

Symbol

Parameter

Conditions

Typical

LM1577·15
Limit
(Notes 3, 4)

LM2577·15
Limit
(Note 5)

14.50/14.25
15.50/15.75

14.50/14.25
15.50/15.75

V
V(min)
V(max)

50/10Q

50/100

mV
mV(max)

50/100

50/100

mV
mV(max)

Units
(Limits)

SYSTEM PARAMETERS Circuit of Figure 2 (Note 6)
VOUT

aVOUT

Output Voltage

Line Regulation

VIN
aVOUT

Load Regulation

alLOAD
'Ij

Efficiency

VIN = 5Vto 12V
ILOAD = 100 mA to 600 mA
(Note 3)

15.0

VIN = 3.5V to 12V
ILOAD = 300 mA

20

VIN = 5V
ILOAD = 100 mA to 600 mA

20

VIN

=

5V, ILOAD

=

600 mA

80

%

DEVICE PARAMETERS
Is

Input Supply Current

VFEEDBACK
(Switch Off)

=

7.5

18.0V

10.0/14.0

ISWITCH = 2.0A
VCOMP = 2.0V
(Max Duty Cycle)
Vuv

fo

VREF

aVREF
aVIN

=

Input Supply
Undervoltage
Lockout

ISWITCH

Oscillator Frequency

Measured at Switch Pin
ISWITCH = 100 mA

50/85

mA(max)

2.70/2.«55
3.10/3.15

2.70/2.65
3.10/3.15

V
V(min)
V(max)

48/42
56/62

48/42
56/62

kHz
kHz(min)
kHz(max)

14.70/14.55
15.30/15.45

14.70/14.55
15.30/15.45

V
V(min)
V(max)

52

Measured at Feedback Pin
VIN = 3.5V to 40V
VCOMP = 1.0V

Output Reference
Voltage Line Regulation

VIN

3.5V to 40V

15

10

mV

12.2

kll

RFB

Feedback Pin Input
Voltage Line Regulator

GM

Error Amp
Transconductance

ICOMP = -30,..A to +30,..A
VCOMP = 1.0V

300

Error Amp
Voltage Gain

VCOMP = 1.1Vto 1.9V
RCOMP = 1.0 Mil
(Note 7)

65

AVOL

50/85
2.90

100 mA

mA
mA(max)
mA

25

Output Reference
Voltage

=

10.0/14.0

170/110
420/500

1701110
420/500

,..mho
,..mho(min)
,..mho(max)

40/20

40/20

VIV
VIV(min)

•
3-95

Electrical Characteristics-LM1577-15, LM25'77-15 (COntinued)
with standard type face ara for T J = 25D C, and those in bold
Range. Unless otherwise specified, VIN = 5V, and ISWITCH = O.

Specific~tions

Symbol

Parameter

Conditions

''
'"f
type face ,apply over full Operating ,Temperature

Typical

LM1577·15
Limit
(Notes 3, 4)

LM2577·15
Limit
(Note 5)

,2.2/2.0

2.2/2.0

V
V(min)

0.410.55

0.40/0.55

V
V(max)

±130/±90
±300/±400

±130/±90

Units
(Limits)

DEVICE PARAMETERS (Continued)
Error Amplifier
Output Swing
"

UpperUmit
VFE;EDBACK

Soft Start Current

Iss

Maximum Duty
Cycle

D
~ISWITCH
~VCOMP

Switch
Transconductance

IL

Switch Leakage

=
=

18.0V

0.3

VFEEDBACK
12.0V to 18.0V
VCOMP = 1.0V
VFEEDBACK = 12.0V
VCOMP = OV

±200

±300/±400

5.0

2.5/1.5
7.5/9.5

2.5/1.5,
7.5/9.5

93/90

93/90

95

VCOMP = 1.5V
ISWITCH = 100 mA

12.5
VSWITCH = 65V
VFEEDBACK = 18.0V
(Switch Off)

10 '

Switch Saturation
Voltage

ISWITCH = 2.0A
VCOMP = 2.0V
(M!\X Duty Cycle)

0.,5

NPNSwitch
Current Umit

VCOMP = 2.0V

4.3

Cur~ent

VSAT

12.0V

~owerUmit
VFEEDBACK

Error Amp
, Output Current

2.4

=

.'
(

,

3·96

p,A
p,A(min)
p,A(max)
p,A
' , p,A(min)
p,A(max)
%
%(min)
AN
p,A

300/600

300/600

p,A(max)

0.7/0.9

0.710.9

V(max)

3.7/3.0
5.3/6.0

3.7/3.0
5.3/6:0

A
A(min)
A(max)

V

,'

!i:
.....

Electrical Characteristics-LM1577-ADJ, LM2577-ADJ
Specifications with standard type face are for TJ = 25°C, and those in bold type face apply over full Operating Temperature
Range. Unless otherwise specified, VIN = 5V, VFEEDBACK = VREF, and ISWITCH = o.
Symbol

Parameter

Typical

Conditions

LM1577·ADJ
Limit
(Notes 3, 4)

LM2577·ADJ
Limit
(Note 5)

Units
(Limits)

VOUT

I!NOUT/
AVIN

Line Regulation

AVOUT/
AILOAD

Load Regulation

"I

Efficiency

Input Supply Current

11.60/11.40
12.40/12.80

11.60/11.40
12.40/12.80

V
V(min)
V(max)

50/100

50/100

rnV
mV(max)

50/100

50/100

mV
mV(max)

12.0

VIN = 3.5V to 10V
ILOAD = 300 rnA

20

VIN = 5V
ILOAD = 100 mA to 800 mA

20

VIN = 5V, ILOAD = 800 mA

80

VFEEDBACK = 1.5V (Switch Off)

7.5

ISWITCH = 2.0A
VCOMP = 2.0V (Max Duty Cycle)
Vuv

fo

%

Input Supply
Undervoltage Lockout

ISWITCH = 100 rnA

Oscillator Frequency

Measured at Switch Pin
ISWITCH = 100 mA

mA
mA(max)

50/85

50/85

rnA
mA(max)

2.70/2.85
3.10/3.15

2.70/2.85
3.10/3.15

V
V(min)
V(max)

48/42
56/82

48/42
56/82

kHz
kHz(min)
kHz(max)

1.214/1.208
1.246/1.254

1.214/1.208
1.246/1.254

V
V(min)
V(max)

52

AVREF/
aVIN

Reference Voltage
Line Regulation

VIN = 3.5V to 40V

IB

Error Amp
Input Bias Current

VCOMP = 1.0V

ErrorArnp
Transconductance

ICOMP = - 30 p.A to
VCOMP = 1.0V

ErrorArnp
Voltage Gain

VCOMP = 1.1V to 1.9V
RCOMP = 1.0 Mil (Note 7)

800

Error Amplifier
Output Swing

Upper Limit

2.4

VFEEDBACK = 1.0V

AVOL

10.0/14.0

2.90

Measured at Feedback Pin
VIN = 3.5Vt040V
VCOMP = 1.0V

GM

10.0/14.0
25

Reference
Voltage

VREF

N
U1

.....
.....
:!.

VIN = 5Vto 10V
ILOAD = 100 rnA to 800 rnA
(Note 3)

DEVICE PARAMETERS
Is

i:

~

SYSTEM PARAMETERS Circuit of Figure 3 (Note 6)
Output Voltage

U1
.....
.....
.....
r

1.230

0.5

mV

100

+ 30 p.A

Lower Limit
VFEEDBACK = 1.5V

300/800

300/800

nA
nA(max)

2400/1800
4800/5800

2400/1800
4800/5800

p.mho
p.mho(min)
p.rnho(max)

500/250

500/250

V/V
V/V(min)

2.2/2.0

2.2/2.0

V
V(min)

0.40/0.55

0.40/0.55

V
V(max)

3700

0.3

3-97

CD

(II

Electrical Characteristics--LM:157,7-ADJ,LM2577-ADJ, (Continued)

'.

Specifications.with standard type face are for TJ = 25'C, and those in bold type face apply over full Operating Temperature
Range. Unless otherwise specified, VIN = 5V, VFEEDBACK ;= VREF, and ISWITCH = O.

Symbol

Parameter

Conditions

' Typical

LM1577-ADJ

LM2577-ADJ

Limit

Limit

(Notes 3, 4)

(Note 5)

±130/±90

±130/±90

".A
p.A(min)

±300/±400

±300/±400

p.A(max)

2.5/1.5

2.5/1.5

p.A(min)

7.5/9.5

7.5/9.5

p.A(max)

9~/90

93/90

%(min)

Units
(Limits)

DEVICE PARAMETERS (Continued)

Iss

Error Amp

VFEEDBACK = 1.0V to 1.5V

Output Current

VCOMP = 1.0V

Soft Start Current

VFEEDBACK = 1.0V

±200

5.0'

VCOMP = OV

D

Maximum Duty Cycle

95

VCOMP = 1.5V
ISWITCH = 100 mA

.
.....

ReOMP '" 10 MO

.......

100

, ,

80

TEMPERATURE (Oe)

20

Error Amp Transconductance
vs Temperature

\j 325

""

15

15V VERSIONS

~

.3

Error Amp Voltage
Gain vs Temperature

~

25

o

TEMPERATURE (Oe)

~

,

0

I

12V VERSIONS

ReaMP'" 10 YO

600
-50 -25

/

0.0

-1.0

400

180

1000

./

V

SUPPLY VOLTAGE (V)

250

160

....

V-

i--"

1.0

~

Error Amp Transconductance
vs Temperature

300

75 100 125 ISO

4.0

-2.0

W

50

vs Supply Voltage

~

ADJ VERSIONS

1.40 0

3.0

<3

5

25

5.0

.5
~

i

200
-50 -25 0

1800

z

">
~

I

400

Error Amp Voltage
Gain vs Temperature

~

......

/

TEMPERATURE (Oe)

0,

0

15V VERSIONS

. / V"

12V VERSIONS

">

ii'
o

V

SUPPLY VOLTAGE (V)

Error Amp Transconductance
vs Temperature

~
~

./

t:.. Reference Voltage

1/

o

40

......

TEMPERATURE (Oe)

-2.0

o

I-"""

14.90
-50 -25

75 100 125 150

4.0

~
<2 -1.0

A~J V~RSI6NS

160

50

12V VERSIONS

~.

~

4500
4000

25

6.0

SUPPLY VOLTAGE (V)

5000

~ 14.98

t:.. Reference Voltage
vs Supply Voltage

ADJ VERSIONS

0.3

......

~

5.0

0.5
0.4

15.04

~ 15.02

g 15.00
~ '-4.9&
~ 14.94

......

I-

TEMPERATURE (Oe)

t:.. Reference Voltage
vs Supply Voltage

~

~

N
CII

15V VERSIONS

14.92

11.90
-50 -25

75 100 125 ISO

ri:

E: 15.06

11.9 2

1.222

-so

~

./

Reference Voltage
vs Temperature

15.08

-

12.06

!i1

15.10

f2V VERSIONS

..... 12.04

1.220

1

......

12.08

./

~ 1.230

I

12.10

CII

......
......

60
-50 -25 0

25

50

~

~

100

'-

I',

r-.. .......

~

~
I'-..

75 100 125 150

TEMPERATURE (oe)

120

z

ReaMP '" 10 MG

80

~

60
40
-50 -25

0

25

50

......

r---

75 100 125 150

TEMPERATURE (oe)
TLlH/II468-2

3-99

•

Typical Performance Characteristics
Quiescent Current
vs Temperature
50

-:c
oS

a
~

25

z

~

20

i:!

15

§

IS• ,: CH

ISWITCH

45

a

'0
35

B

30

z

~

25

i:!5

20

~

~ 2A -

ISWITCH = 1A

10

-:c
oS

1 1

......

5.0

I\.

50

ISWITCH = 3/1.

"
.....

= 100 mA

./

o

5
25

50

75 100 125 150

o

-

0.5

TEMPERATURE (OC)

Current Limit Response
vs Overdrive

1.4

2

1.2

~'"

0.8 ~40

ill

0.6

i'-- ....

0 = 0.2

2.0

2.5

3.0

'3.0
-50 -25

CA)

0

25

50

75 100 125 150

TEMPERATURE (OC)

Switch Transconductance
vs Temperature

1

.\1./125

"\{l

~ ....
~

0.4
0.2

1

o

1

100

~

0.8

i

0.7

~

-

.........

1

O. 9
\ 150

!

1.0

1.5

.........

3.5

1.0

1.8

~

1.0

~

i'..

01.0

Switch saturation Voltage
va Switch Current

2.0

;:

a'"

[.....-'"

1

'.5

'2

SWITCH CURRENT (A)

Tlm~

1.6

3:

D~ ~

,. "" ""..... ---r

15

0

V

0= 0.9

10
-50 -25 0

Current Umit
vs Temperature

55

50% DUTY CYCLq

'0
35
30

Quiescent Current
vs Switch Current

I J L

45

(Continued)

150°C

~

JJI?

, '1/
""~

0.6
0.5

~
<

~ "/'. , . , -55°C

~ O.~
0.3
~ 0.2

~~

~

O. 1

~

13

I"....

" r--..

12

~

11

~

10

"

~

"\

8

200 300 400 500 600 700 800

0.5

CURRENT LIMIT OVERDRIVE (mA)

1.0

1.5

2.0

2.5

-50 -25

3.0

0

SWITCH CURRENT (A)

Feedback Pin Bias
Current vs Temperature

25

50

75 100 125 150

TEMPERATURE (oC)

Oscillator Frequency
vs Temperature

220
200

!

iB
!(l
iii

180
160
,.0
120
100
80

v '\

53

'N'

\

1/

!

""

I" .......

60
-50 -25 0

52

25

50

~
S

50

e:

49

V

~

ADJ VERSIONS

1\
\.

".......

.8
'7

75 100 125 150

-50 -25

TEMPERATURE (OC)

0

25

50

J

75 100 125 150

TEMPERATURE (OC)

TUHI11468-3

Maximum Power DIssipation
(T0-263) (See Note 9)

~

9 JA = 32°e/w

""''--

Your

+680 pF
CoUT

TLlH/11468-26

L

= 415-0930 (AlE)

COUT

o = any manufacturer

= Sprague Type 6730

Note: Pin numbers shown
are for TO·220 le of Fl{Jure 8 which crossreferences the inductor codes to the part numbers of three
different manufacturers. Gomplete specificaiions for these
inductors are available from the respective manufacturers.
The inductors listed in this table have the following characteristics:

Rc

VIN(min)2
Select a resistOr less than or equal to this value, and it
should also be no greater than 3 kfi.
B. Calculate the minimum valUe for GoUT using the following
two equations.

AlE' ferrite, pot-core inductors; Benefits of this type are
low electro-magnetic ihterlerehce (EM I), small physical
size, and very low power dissipation (cote lOSS). Be careful not to operate these Inductors too far beyond their
maximum ratings for EeT ahd peak current, as this will
saturate the core.

GoUT~_0_.1_9_X__
L_X~R~c_X~IL~O~AD~(~m=ax~)
VIN(min)

_
__1_05__
X_L..:.:,»
COUT~ V",IN",(m""i",n),--X__R""c,--X=(II-:I,:,N(",m!!!.in:t,),.,.+_(:..3-;;.7,...4_X
487.800 X VOUT3
The larger of these two values is the minimum value that
ensures stability.

Renco: ferrite, bobbin-core inductors; Benefits are low
cost and best ability to withstand E-T and peak current
above rated value. Be aware that these inductors generate more EMI than the other types, and this may interfere
with signals sensitive to noise.

SOhott

Fiulse

Renco

L47
L68
L100
L150
L220
L330
L470
L680

67126980
67126990
67127000
67127010
67127020
67127030
67127040
67127050

PE-53112
PE-92114
PE - 92108
PE - 5311S
PE- 52626
PE- 52627
PE-53114
PE-52629

RL2442
RL2443
RL2444
RL1954
RL1953
RL1952
RU951
RL1950

H150
H220
H330
H470
H6BO
H1000
H1500
H2200

67127060
67127070
67127080
67127090
67127100
67127110
67127120
67127130

PE-53115
PI: - 53116
PE - 53117
PE - 53118
PE-53119
PE - 53120
pI:; - 53121
PE - 53122

RL2445
RL2446
RL2447
RL1961
RL1960
RL1959
RL1958
RL2448

x VOUT

and

Pulse: powdered iron, toroid core inductors; Benefits are
low EMI and ability to withstand EeT and peak current
above rated value better than ferrite cores.

Inductor
Code

s: _75_0_X---"IL":,oA7l'0::..(m""ax"")!;-X_V,,,,o><,u:r2,..,

C. Calculate the minimum value of Co

.:.58:c:...5,=X~V""ou",r2:--X,--Go==U'-!.T
Gc;;;,Rc2 x VIN(min)
The compensation capacitor is also part of the soft start
circuitry. When power to the regulator is turned on, the
switch duty cycle is allowed to rise at a rate controlled by
this capacitor (with no control on the duty cycle, it would
immediately rise to 90%, drawing huge currents from the'
input power supply). hi order to operate properly, the soft
start circuit requires Cc ~ 0.22 p.F.

Miinufacturer's Part Number

The value of the output filter capacitor is normally large
enough to require the use of aluminum electrolytic capacitors. Figure 9 lists: several different types that are recommended for SWitching regulators, and the following parameters are used to select the proper capacitor.
Working Voltage (WVDq/; Choose a capaCitor with a working voltage at least 20% higher than the regulator output
voltage.
Ripple Current: This is the maximum RMS value of current
that charges the capacitor during each switching cycle. For
step-up and flyback regulators, the formula for ripple current
is
- ILOAD(max) x D(max)
I
RIPPLIi(RMS) =
1" D
(max)
Choose a capaCitor that is rated at least 50% higher than
this value at 52 kHz.
Equivalent Serie$ Resistance (ESR): This is the primary
cause of output ripple voltage, arid It also affects the values
of Rc and Cc needed to stabilize the regulator. As a result,
the preceding calculations for Co and Rc are only valid if
ESR doesn't exceed the maximum value specified by the
following equations.

SChott Corp., (612)475-1173
1000 Parkers Lake I=ld., Wayzata, MN 55391
Pulsll Engineering, (619) 268-2400
P.O. Box 12235, San Diego, CA 92112
Reneil Electronics Inc., (516) 586-5566
60 Jeffryn Blvd. East, Desr Park, NY 11729

FIGURE 8. Table of Standardized Inductorslnd
Manufacturer's Part Nuinbers
2. Compensation Network (Re, ee) and Output Capacitor (COUT) selection
.

ESR

Rc and Co form a pole-zero compensation network that
stabilizes the regulator. The values of Rc and Cc are mainly
dependant on the regulator voltage gain, ILOAD(max), Land
COUTo The following procedure calculates values for Rc,
Cc, and COUT that ensure regulator stability. Be aware that
this procedure doesn't necessarily result in Rc and Cc that
provide optimum compensation. In order to guarantee optimum compensation, one of the standard procedures for
testing loop stability must be used, such as measuring VOUT
transient response when pulsing ILOAD (see Figure 13).

s: 0,01

X VOUT and
IRIPPLE(P-P)

s: 8.7

X (10)- 3 x VIN
ILOAD(max)

where
I
_ 1.15 X ILOAD(max)
RIPPLE(P-P) 1
D
- (max)
Select a capacitor with ESR, at 52 kHz, that Is less than or
equal to the lower value calculated. Most electrolytic capacitors specify ESR at 120 Hz which is 15% to 30% higher
than at 52 kHz. Also, be aware that ESR increases by a
factor of 2 when operating at - 20"C.

3-106

Application Hints (Continued)
In general, low values of ESR are achieved by using large
value capacitors (C ~ 470 p.F), and capacitors with high
WVOC, or by paralleling smaller·value capacitors.

ground with a good quality, low ESR, 0.1 p.F capacitor
(leads as short as possible) is normally sufficient.
If the LM 1577 is located far from the supply source filter
capacitors, an additional large electrolytic capacitor (e.g.
47 p.F) is often required.
5. Diode Selection (D)

3. Output Voltage Selection (R1 and R2)
This section is for applications using the LM1577·AOJI
LM2577·AOJ. Skip this section if the LM1577·12/LM2577·
12 or LM1577·15/LM2577·15 is being used.
With the LM1577·AOJ/LM2577·AOJ, the output voltage is
given by
VOUT

=

1.23V (1

The switching diode used in the boost regulator must with·
stand a reverse voltage equal to the circuit output voltage,
and must conduct the peak output current of the LM2577. A
suitable diode must have a minimum reverse breakdown
voltage greater than the circuit output voltage, and should
be rated for average and peak current greater than
ILOAO(max) and IO(PK). Schottky barrier diodes are often fa·
vored for use in switching regulators. Their low forward volt·
age drop allows higher regulator efficiency than if a (less
expensive) fast recovery diode was used. See Figure 10 for
recommended part numbers and voltage ratings of 1A and
3A diodes.

+ R1/R2)

Resistors R1 and R2 divide the output down so it can be
compared with the LM1577·AOJ/LM2577·AOJ internal
1.23V reference. For a given desired output voltage VOUT,
select R I and R2 so that
R1 = VOUT _ 1
R2
1.23V
4. Input Capacitor Selection (CIN)
The switching action in the step·up regulator causes a trian·
gular ripple current to be drawn from the supply source. This
in turn causes noise to appear on the supply voltage. For
proper operation of the LM1577, the input voltage should be
decoupled. Bypassing the Input Voltage pin directly to

VOUT
(max)

Cornell Dublier-Types 239,250,251, UFT, 300,
or 350
P.O. Box 128, Pickens, SC 29671
(803) 878·6311
Nlchicon-Types PF, PX, or PZ
927 East Parkway, Schaumburg, IL 60173
(708) 843·7500

Fast Recovery
3A

20V

1N5817
MBR120P

1N5820
MBR320P

30V

1N5818
MBR130P
110003

1N5821
MBR330P
310003

40V

1N5819
MBR140P
110004

1N5822
MBR340P
310004

MBR150
11D005

MBR350
310005

Sprague-Types 6720,6730, or 6740
Box 1, Sprague Road, lanSing, NC 28643
(919) 384·2551

50V

United Cheml-Con-Types LX, SXF, or SxJ
9801 West Higgins Road, Rosemont, IL 60018
(708) 696·2000

100V

FIGURE 9. Aluminum Electrolytic CapaCitors
Recommended for Switching Regulators

Schottky
1A

1A

3A

1N4933
MUR105
1N4934
HER102
MUR110
100L1

MR851
300L1
MR831
HER302

FIGURE 10. Diode Selection Chart

•
3·107

Application Hints (Continued)
cal performance of this regulator is shown in Figures 12 and
13. The switching waveforms observed during the operation
of this circuit are shown in FlfJure 14.

BOOST REGULATOR CIRCUIT EXAMPLE

By adding a few external components (as shown in Figure
11), the LM2577 can be used to produce a regulated output
voltage that is greater than the applied input voltage. Typi-

TLlH/II46B-13
Note: Pin numbers shown are for T0-220 (l) package.

FIGURE 11. Step-up Regulator Delivers 12V from a 5V Input
11.990
11.985

~ 11.980
ll: 1,.975

i

...
f::0
f::0
0

1\

= 1511

,
........ .....

11.970
11.965

...... ........

11.960
11.955
.11.950
4.0 5.0 6.0 7.0 B.O 9.0 10.0 11.0

INPUT VOLTAGE (V)

TL/H/II468-14

FIGURE 12. Line Regulation (Typical) of Step-Up Regulator of Figure 11

A[O
BoomA
[

B

400mA

TL/H/I1468-16

FIGURE 14. Switching Waveforms of Step-Up
Regulator of Figure 11

TL/H/II46B-15

FIGURE 13. Load Transient Response of Step-Up
Regulator of Figure 11

A:
B:
C:
D:

A: Output Voltage Change. 100 mV/d... (AC-coupled)
B: Load current. 0.2 AId..
Horizontal: 5 msJdlv

Switch pin voltage. 10 Vld..
Switch pin current. 2 AId..
Inductor current, 2 AId..
Output ripple voltage. 100 mVldiv (AC-coupled)

Horizontal: 51'8/dlv

3-10&

.-----------------------------------------------------------------------------~

r

....

!:

Application Hints (Continued)
Where ~ILOAD(max) is the sum of the load current (magnitude) required from both outputs. Select a resistor less than
or equal to this value, and no greater than 3 kO.

FLYBACK REGULATOR
A Flyback regulator can produce single or multiple output
voltages that are lower or greater than the input supply voltage. Figure 15 shows the LM1577/LM2577 used as a flyback regulator with positive and negative regulated outputs.
Its operation is similar to a step-up regulator, except the
output switch contois the primary current of a flyback transformer. Note that the primary and secondary windings are
out of phase, so no current flows through secondary when
current flows through the primary. This allows the primary to
charge up the transformer core when the switch is on. When
the switch turns off, the core discharges by sending current
through the secondary, and this produces voltage at the
outputs. The output voltages are controlled by adjusting the
peak primary current, as described in the step-up regulator
section.

B. Calculate the minimum value for

~COUT (sum of COUT

at both outputs) using the following two equations.
COUT ~

_
0_.1_9_X_R...;:c=--X_L..:.p_X_~_'.:;LO::::A"'D"'("'m=ax::t1

15V

x

V'N(min)

and

U1
......

::::!
r

!:
I\)
U1
......
......

..I'f

_
COUT~ V.!!.IN""(m.!!!i,."nl,:-X-:-R::-c:-X_N.,.,2c::X:-:,-:(V""IN.!l(/.:"m,,,inL.1_+,.,,(3:..:..7.:..4_X-,-10.:..5.".X_L..:.p.!.!.ll
487,800 X (15V)2X (15V + V'N(min) x N)
The larger of these two values must be used to ensure regulator stability.
SWITCH
VOLTAGE

Voltage and current waveforms for this circuit are shown in
Figure 16, and formulas for calculating them are given in
Figure 17.

DIODE
VOLTAGE

FLYBACK REGULATOR DESIGN PROCEDURE

-rl- -"r-T - -.
_L_.L.....J __ L ov -------------

VSW~Fr)
SAT

:~ :O::j--t:::
vR -

1. Transformer Selection

PRlhiARY
CURRENT

A family of standardized flyback transformers is available for
creating flyback regulators that produce dual output voltages, from ±10V to ±15V, as shown in Figure 15. Figure
18 lists these transformers with the input voltage, output
voltages and maximum load current they are designed for.

DIODE
CURRENT

--

-

j

41p( PKI

Ip(PKI-ILU1--- - - - --

'T

0-

--

----

Io(PK)-~---------

- -- - -----

Io~~-

0-

-

-

-TLlH/11468-17

2. Compensation Network (Cc. Rc) and
Output CapaCitor (COUT) Selection

FIGURE 16. Flyback Regulator Waveforms

As explained in the Step-Up Regulator Design Procedure,
Cc, Rc and COUT must be selected as a group. The following procedure is for a dual output flyback regulator with
equal turns ratios for each secondary (i.e., both output voltages have the same magnitude). The equations can be
used for a single output regulator by changing ~ILOAD(max)
to ILOAD(max) in the following equations.
A. First. calculate the maximum value for Rc.
Rc"; 750 X ~ILOAD(maxl X (15V + V'N(minIN)2
V'N(min)2

D1

+VOUT

•

Lp

-VOUT

4
SWITCH

R1

.I:

•

CoUT

F.B.I------.
LM2577-ADJ

COhiP

R2

TLlH/11468-18

T1

~

Pulse Engineering, PE·65300

01, 02

~

1N5821

FIGURE 15, LM1577-ADJ/LM2577-ADJ Flyback Regulator with ± Outputs
3-109

If

~

,...

Application Hints (Continued)

t;

Duty Cycle

VOUT + VF
N (VIN - VSAT) + VOUT + VF
VOUT
N (VIN) + VOUT

D

N

~

~....

Primary Current
Variation

~

Peak Primary
Current

alp

D (VIN - VSAT)
Lp x 52,000

Ip(pK)

N l:ILOAD alpK
-X--+-'Ij
1- D
2

Switch Voltage
when Off

VSW(OFF)

Diode Reverse
Voltage

VR

VOUT+ N (VIN- VSAT)

Average Diode
Current

ID(AVE)

ILOAD

ID(PK)

ILOAD + allND
1- D
2

Peak Diode
Current

VIN +

;:::

VOUT + VF
N

6A

Short Circuit
Diode Current

;:::N"

Power Dissipation
of LM1577/LM2577

0.250 (N l:ILOAD
1-D

Po

r

+

NILOADD V
50(1 - D) IN
N - T sfo
T
R' _ number of secondary turns
- ran rmer ums alia - number of primary tums

'1 ~ Transformer Efficiency (typiCally 0.95)
l:ILOAD ~ I + ILOADI + I-ILOADI

FIGURE 17. Flyback Regulator Formulas
This formula can also be used to calculate the maximum
ESR of a single output regulator.
At this pOint, refer to this same section in the Step-Up Regulator Design Procedure for more information regarding
the selection of CoUT.

C. calculate the minimum value of Cc

=»

Cc <: .: . 58;:..:.:..5_X_Co=U"-!T_X-=-,"V~O.>!.UT!.:-:-X-,(V.::..O",,U~T:.....,,+-,(V.::..I~N~!m~ln~)_X....cN
Rc;2 x VIN(mln) x N
D. calculate the maximum ESR of the +VOUT and -VOUT
output capacitors in parallel.
ESR+IIESR_

s:

8.7 X 10-3 X VIN!min) X VOUT X N
l:ILOAD(max) x (VOUT+ (VIN(min) x N»

3-110

.-----------------------------------------------------------------------------~ ~

....

Application Hints (Continued)
3. Output Voltage Selection

back regulator generates more noise at the input supply
than a step-up regulator, and this requires a larger bypass
capacitor to decouple the LM1577/LM2577 VIN pin from
this noise. For most applications, a low ESR, 1.0 p.F cap will
be sufficient, if it is connected very close to the VIN and
Ground pins.

This section is for applications using the LM1577-ADJI
LM2577-AOJ. Skip this section if the LM1577-12/LM257712 or LM1577-15/LM2577-15 is being used.
With the LM1577-AOJ/LM2577-AOJ, the output voltage is
given by

In addition to this bypass cap, a larger capaCitor (:;' 47 p.F)
should be used where the flyback transformer connects to
the input supply. This will attenuate noise which may interfere with other circuits connected to the same input supply
voltage.
6. Snubber Circuit
A "snubber" circuit is required when operating from input
voltages greater than 10V, or when using a transformer with
Lp :;, 200 p.H. This circuit clamps a voltage spike from the
transformer primary that occurs immediately after the output
switch turns off. Without it, the switch voltage may exceed
the 65V maximum rating. As shown in Figure 19, the snubber consists of a fast recovery diode, and a parallel RC. The
RC values are selected for switch clamp voltage (VCLAMP)
that is 5V to 10V greater than VSW(OFF)' Use the following
equations to calculate Rand C;

VOUT = 1.23V (1 + R1/R2)
Resistors R1 and R2 divide the output voltage down so it
can be compared with the LM1577-AOJ/LM2577-AOJ internal 1.23V reference. For a desired output voltage VOUT,
select R1 and R2 so that
R1 = VOUT -1
R2
1.23V
4. Diode Selection
The switching diode in a flyback converter must withstand
the reverse voltage specified by the following equation.
VIN
VR = VOUT+"N
A suitable diode must have a reverse voltage rating greater
than this. In addition it must be rated for more than the
average and peak diode currents listed in Figure 17.
5. Input CapaCitor Selection
The primary of a flyback transformer draws discontinuous
pulses of current from the input supply. As a result, a flyInput
Voltage

Dual
Output
Voltage

Maximum
Output
Current

100 p.H
N= 1

5V
5V
5V

±10V
±12V
±15V

325mA
275mA
225mA

=

10V
10V
10V
12V
12V
12V

±10V
±12V
±15V
±10V
±12V
±15V

700mA
575mA
500mA
800mA
700mA
575mA

15V
15V
15V

±10V
±12V
±15V

900mA
825mA
700mA

Transformer
Type

1

2

=

Lp

Lp

N

3

=

Lp

N

200 p.H
0.5

=

250 p.H
0.5

=

C :;,

0.02 X Lp X Ip(pK)2
(VCLAMP)2 - (VSW(OFF»2

s:

(VCLAMP + VSW(OFF) - VIN)2 X (19.2 X 10- 4 )
Lp X Ip(pK)2
2
Power dissipation (and power rating) of the resistor is;
R

P = (VCLAMP +

V~W(OFF)

- VINr/R

The fast recovery diode must have a reverse voltage rating
greater than VCLAMp.
VIN

RC

'""~t ':

+5'i Y

Jl!t

1...-........-1.10IIII""'11......

fAST RECOVERY DIODE

SWITCH

Transformer
Type
1
2
3

Manufacturers' Part Numbers
AlE

Pulse

Renco

326-0637
330-0202
330-0203

PE-65300
PE-65301
PE-65302

RL-2580
RL-2581
RL-2582

LM2577
TLlH/1146B-19

FIGURE 19. Snubber Circuit

FIGURE 18. Flyback Transformer Selection Guide

3-111

!!I:
en

.....

~
~

a::
~
~

fC

:I.

m

Application Hints (Continued)

',':

FLYBACK REGULATO~ CIRCUIT ExAMPLE
The 6ircuit of Figure 20 produces ± 15V (at ?2~ lilA each)
from a single 5V input. The output regulation of this circuit is
shown in Figures 21' and 22, while the load transient response is shown in Figures 23 arid 24. Switching waveforms
seen in this circuit are shown in Figure 25.

"

,

01

+VOUT

.... ,.

Tl
l:N

•
Lp

,+ 15V @225rnA

Jr---..~*\J'. ...' ....-

II [0~_~
.... •

I

.....
L--O
~ 470}'F

~CoUT
-VOUT

02

'1....

-,lW@225rnA

".....

4
SWITCH

F . B . I - - - - -....

Rc

LM2577-15

2k

Cc

=r 0~47

}'F

/l.
-

T1 - Pulse Engineering, PE:65300
01,02 = 1N5621

15.180

NOTE: PIN NUIotBERS
SHOWN ARE FOR TH E
TO-220 (T) PACKAGE.

GNO

3

,
TLlH/11466-20

FIGURE 20. Flyback Regulator Easily Provides D~al"Outputs

Rt. -

15.240

Rt. -

60n

15.160

~

15.140

....
C>

......

15.120

-'
0

15.100

::::>

15.080 '

...>
...""
::::>
0

60n

15.220

(+ 15V OUTPUT)

(-15V OUTPUT)

~

""\

15.180

§!

...
...""

15.160

::::>

15.140

::::>

15.060

15.200

....
C>
~

0

\

\

15.120

15.040

15.Hio

15.020L...L.-"----'---'--'--......L.-'-----'--'
4.0 '6.0 8.0 10.012:0 14.0 16.0 18.0

15.080 L...L._'----'---'-_'---'---'----'...J
4.0 6.0 8.0 10.012.0 14.0 16.0 18.0

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)
TL/H/11468-21

TL/H/11466-22

FIGURE 21. Line Regulation (Typical) of Flyback
Regulator of Figure 20, +"15V Output

FIGURE 22. Line Regulation (Typical) of Flyback
R~glliator of Figure 20, -15V Output
\

3-112

".

,-----------------------------------------------------------------------------, r
i:
....
Application Hints (Continued)
UI

:::I
......

r
i:
I\)

A -loom:

:::I

[

100mV
(

A

loomV

UI

ff

-100m:

::::lI.

m

B(

200mA

IOOmA

100mA

200mA

o

TUH/II488-24

FIGURE 24. Load Transient Response of Flyback
Regulator of Figure 20, -15V Output

TL/H/11468-23

FIGURE 23. Load Transient Response of Flyback
Regulator of FIgure 20, + 15V Outpu1

A: Output Voltage Change, 100 mVldiv
B: Output Current, 100 mAldiv
Horizontal: 10 rns/dlv

A: Output Voltage Change, 100 mVldiv
B: Output Current, 100 mAldiv
Horizontal: 10 rns/dlv

DC

0
TL/H/11488-25

FIGURE 25. Switching Waveforms of Flyback Regulator of FIgure 20, Each Output Loaded with 60n
A:
B:
C:
D:

Switch pin voltage, 20 Vldiv
Primary current, 2 A/div
+ 15V Secondary current, 1 Aldiv
+15V Oulput ripple voltage, 100 mV/div
Horizontal: 5 ""/div

3-113

~

C'I

~

r-------------------------------------------------------------------------,
I!J1National Semiconductor

LM2925 Low Dropout Regulator with Delayed Reset
General De~cription, ,

Features

The LM2925 features a low dr~pout, high current regulator.
Also included :or'l-chip is a reset'lunction with an externally
set delay time:Upon power up, or after the detection of any
error in the regulated putput, the resllt pin remains in the
active low state for the duration of the delay. Types of errors
detected ihchide any that caOse the output to become
unregulated: low input voltage, thermal shutdown, short circuit, input transients, etc. No external pull-up resistor is necessary. The current charging the delay capaCitor is very low,
allowing long delay times.
Designed primarily for automotive applications, the LM2925
and all regulated circuitry are protected from reverse battery
installations or twO-battery jumps. During line transients,
such as a load dump (60V) when the input voltage to the
regulator can momentarily exceed the specified maximum
operating voltage, the 0.75A regulator will "automatically
shut down to protect both internal circuits and the load. The
LM2925 cannot be harmed by temporary mirror-image insertion. Familiar regulator features such as short circuit and
thermal overload protection are also provided.

•
•
•
•
•
•
•
•
•
•
•

5V, 750 mA Qutput
Externaily set delay for reset
Input-output differential less than 0.6V at 0.5A
ReverSe battery proteqtion
60V load dump protecti(:m
- 50V reverse transient protection
Short circuit protection
Internal thermal overload protection
Available in plastiC TO-220
Long delay times available
P + Product Enhancement tested

Typical Application Circuit

j
-'-Cl*

*l~F

11
INPUT
OUTPUT
VOLTAGE VOLTAGE

VOUT 5V
750mA

~
+

C2**

*10~F
RESE~...! RESET
FLAG

·Required if regulator is located far from
power supply filter.

LM2925

• ·COUT must be at least 10 ,...F to maintain
stability. May be increased without bound

to maintain regulation during transients.

~ELAY

GNO

P

.,....C3
0.1

*

Locate as close as possible to the regula-

tor. This capaCitor must be rated over the
same operating temperature range as the
regulator. The equivalent series resistance (ESR) of this capaCitor is critical;
see curve.

~F

TL/H/526B-l

FIGURE 1. Test and Application Circuit

Connection Diagram
TO-220 5-Lead

1~.1

1'MW'~

4 DELAY
3 GROUND
2 OUTPUT VOLTAGE (VOUT)
1 INPUT VOLTAGE (VIN)

I

FRONT VIEW

TL/H/526B-2

Order Number LM2925T
See NS Package Number T05A

3-114

Absolute Maximum Ratings
Operating Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage
Operating Range
Overvoltage Protection

150'C

Storage Temperature Range

-65'Cto + 150'C

Lead Temperature
(Soldering, 10 seconds)

26V
60V
Internally Limited

Internal Power Dissipation (Note 1)

-40'Cto + 125'C

Maximum Junction Temperature

260'C

ESD rating is to be determined

Electrical Characteristics for VOUT
VIN = 14V, C2 = 10 ,.,.f, 10 = 500 mA, TJ = 25'C (Note 3) (unless otherwise specified)
Parameter

Min

Conditions

Typ

Max

Units

Note 2
Output Voltage
6V~ VIN ~ 26V, 10 ~ 500
-40'C~ TJ ~ +125'C

Line Regulation

9V
6V

~
~

VIN
VIN

~
~

V

mA,
4.75

16V, 10 = 5 mA
26V, 10 = 5 mA

5.00

5.25

4
10

25
50

10

50

mV
mV

Load Regulation

5mA~10~500mA

Output Impedance

500 mADC and 10 mArms,
100 Hz-10 kHz

200

Quiescent Current

10 ~ 10mA
10 = 500mA
10 = 750mA

3
40
90

10 Hz-100 kHz

100

,.,.Vrms

20

mV/1000 hr

Output Noise Voltage
Long Term Stability

fo=120Hz

66

Dropout Voltage

10= 500mA
10 = 750mA

0.45
0.82

Maximum Operational
Input Voltage
Maximum Line Transient

Vo ~ 5.5V

Reverse Polarity Input
Voltage, DC

Vo

Reverse Polarity Input
Voltage, Transient

1 % Duty Cycle,
100. Load

~

- 0.6V, 100. Load
T ~

100 ms,

mA
mA
mA

100

Ripple Rejection

Current Limit

mV
mo.

dB
0.6

V
V

0.75

1.2

A

26

31

V

60

70

V

-15

-30

V

-50

-80

V

Electrical Characteristics for Reset Output
VIN = 14V, C3 = 0.1 ,.,.F, TA = 25'C (Note 3) (unless otherwise specified)
Parameter

Conditions

Min

Typ

Max

Units

Note 2
Reset Voltage
Output Low
Output High

ISINK = 1.6 mA, VIN = 35V
ISOURCE = 0

4.5

Reset Internal Pull-up Resistor
Reset Output Current Limit

VRESET = 1.2V

Delay Current

Cs = .005 fJoF
Cs = 0.1,.,.F
Cs = 4.7,.,.Ftantalum
Pin 4

0.6
5.5

V
V

30

ko.

5

mA

4.5

V

150

12
250
12

300

ms
ms
s

1.2

1.95

2.5

,.,.A

VOUT Threshold
Delay Time

0.3
5.0

Note 1: Thermal resiatance without a heat sink for junction to case temperature is 3°C/W (TO-220). Thermal resistance for TO·220 case to ambient temperature is
5Q°C/W.
Note 2: These parameters are guaranteed and

100% production tested.

Note 3: To ensure constant junction temperature, low duty cycle pulse testing is used.

3-115

U)

eN

~

~

r------------------------------------------------------------------------------------------,
Typical Circuit Waveforms
60V

INPUT

26V

vm:,~~

14V

14¥
O¥

(VI

5V

OUTPUT
¥O\.TAIIE
PIN 2

OV

O¥

(VI

R£SeT
¥O\.TAGE
PIN 5

O¥

(VI

svmM
CONDITION

I

TURN
ON

LOAD
DUMP

I

LOW V,N

I

I

Your

LINE NOISE, ETC.

I

THERMAL
SHUTDOWN

SHORT
CIRCUIT

TURN
OFF
TLlH/5268-3

FIGURE 2

Typical Performance Characteristics
Reset Voltage

Reset Voltage

6

Delay Time

2.4

HIGH
IR=O

2.0

105

;; 1.6

10'

;;;

~~

f--

-

LOW
IR=I.6mA

10'

-

f--

i

-

1.2

~"

0.8

0.4

o

I

O·

V

103
100
10

1 10 100
DELAY CAPACITOR l/=

RESET CURRENT (mAl

Reset Voltage
on Power-up

cJ=O

:IE

II"
V'

0.1

40
BO
120 160
JUNCTION TEMPERATURE ('CI
TLlH/5268-4

6

w

5:!!

0.0

-40

!

180
-40

..........

"

40
80 120 160
JUNCTION TEMPERATURE I'C)
TL/H/5268-8

/
./

V

""""

V
20
-40

0
40
BD
120' 160
JUNCTION TEMPERATURE ('Cl
TL/H/5268-9

Typical Performance Characteristics
Dropout Voltage

(Continued)

OJI~---jl---+--+--+---l

O'&~---jl---+--+--+---l

5!

lOUT = 500 mA

_

D.4~EEt=D
D.2 ~---jIc-IO-UT--~,"'OOo-m-A+---+---I

O~~--_I~~--~~

o

-.40

80

120

~ 25

0

,

I-ot---T-I!!!!!'I'....
I!!!!!\-.....-I-~

II
-10 t-+-t-+--Il~II-+--+-I

~;

:1;:-

iii

-201~~~~~~~~~~
3

~! 0~

w

~Q

o

160

10

20 30 40
TIME (pa)

JUNCTION TEMPERATURE (OC)
TL/H/526B-l0

~
w
iil
~
iii

80

rrmr

70

~H-H!+Hf-+l+ttt-

60

!z

~

joo-.

60

ijl

-

50

~
iii

40

30

60

~~-~-~-~~

o

150 300 450 600
OUTPUT CURRENT (mA)

750

TL/H/526B-12

Quiescent Current

Output Voltage
6

1

lOUT =500 mA
C2=10,.F

50 ~H4Hm~~mm-+1+ffiffi

60

i5

40

:::>

20

ex

3OL-J....1.JJ.IWL....L.Ju..wIlll-.J-LJL.WUI

V

0-'
0
150

10k

100
lk
FREQUENCY (Hz)

i/

80

i13
~

40 r-H-H!+Hf-+l+Hffir-++H~

10

10=120 Hz
70

100 , . - - - , - - , - - , - - - , - - - ,

VoUT

I

50

80

TL/H/526B-ll

Ripple Rejection

!

Ripple Rejection

Line Transient Response

20,--,--,--,-.,---,---.---,
~""i 10 t--il\~r--t-+-t-+--I

450

300

4
3

/

V

RL=1011',-,H-+-+-+++-1

5

2
1

H+-t-H+-t-iI--I-t--I

-1

~~~~-t-~-f-~~--l

-2

~-L~~...J....~-L~

-40 -20 0
20
40
60
INPUT VOLTAGE (V)
TLlH/526B-15

75D

600

OUTPUT CURRENT (mA)

TL/H/526B-13

TUH/526B-14

<"

.§.

i13

I.

.J

lOUT = 500 mA
40
3D

i5

20

ex

10

~

-

Quiescent Current

so

-

I.

lOUT = 250 mA

Quiescent Current

]:

0

I

100

mA

75

i5'"

50

'5

25

:::>

\loJTJoJmA

II

'"
I!l

0

40

80

120

160

JUNCTION TEMPERATURE (OC)

-20

0

20

B

40

60

Maximum Power
Dissipation (TO-220)

,.,.

~ ~:~:~illIN~nN~fT[~~H~EA~T~Sf~N[K~:~~~

I--I/---:::,*",-+-r-+-I

H-+++-+-H-+--+,III

18

16~~~~~~~~~~

14~~~~~~~~-+~
~I+-+--If---+-+---l

...

1.0

c

0.5 f-+l.I---l--Ir--+--I--t

~

10~ 1-~~~t=j==1==i~~~~~~~~

H-+++-+-H-++-I

12

I ' 1O"C W HEAT SINK

10

I

:

i""r--.

4

o ~...J....~_-'--'-_L-...J

o

5

20

10 15
25
INPUT VOLTAGE (V)

0.2
0.4o

30

0102030405060
TIME •• sl
TL/H/526B-l B

TLlH/526B-17

Peak Output Current

I

r-+-+-+--+--J'I-~~~-t

1::
0 1-.....-t1..,./'+--+...14....lr-~
~ s -50 t-~.--ll--+--+-+-+---I
~ ;-100 r-+"~-+--+-+-+-I
-150 1:--+--+-+--+---1-+--1
g 0.8 f--+-+-t-+-t-t--T
"!Z 0.6

~~

INPUT VOLTAGE (V)

TUH/526B-19

1.5

150 "-'--r-'r-'--r-'r-~

t-+-+-+--+-+-+---I

lou~=olm~

-40

~!

9 i:l

0

-40

g

J.

,il=r

§
ex

lOUT = 50 mA

Load Transient Response

125

r--- NO HEAT ~INK

i""

FT'T"1H-+-I-4-,j;;;;±;::l

2
I
o~~~~~~~~~--~

o

1020 3D 40 50 60 70 80 90100
AMBIENT TEMPERATURE (ac)

TL/H/526B-20

TL/H/526B-21

3-117

Output Capacitor ESR

$
tl
z

i!

,.,..

100

CaUT = 10pF

'/}/ ~

10

ST~~LE - ~
REGION

~

'"

~

§

1

<&

/

0.1

~
:::>

S

0.01

0

100

20D

300

400

SOD

OUTPUT CURRENT (mA)
TL/H/526B-22

•

Definition of Terms

Application Hints

Dropout Voltage: The input-output voltage differential at
which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has
dropped100 mV from the nominal value obtained at 14V
input, dropout voltage is dependent upon load current and
junction temperature.
Input Voltage: The DC voltage applied to the input terminals with respect to ground.

EXTERNAL CAPACITORS
The LM2925 output capacitor is required for stability. Without it, the regulator output will oscillate, sometimes by many
volts. Though the 10 ",F shown is the minimum recommended value, actual Size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) also effects the IC stability. Since
ESR lIaries from one brand to the next, some bench work
may be required to determine the minimum capacitor value
to use in production. Worst-case is usually determined at
the minimum junction and ambient temperature and maximum load expected.
Output capacitors can be increased in size to any desired
value above the minimum. One possible purpose of this
would be to maintain the output voltages during brief conditions of negative input transients that might be characteristic of a particular system.
Capacitors must also be rated at all ambient temperatures
expected in the system. Many aluminum type electrolytics
will freeze at temperatures less than -30"C, reducing their
effective capacitance to zero. To maintain regulator stability
down to -40"C, capacitors rated at that temperature (such
as tantalums) must be used.

Input-Output Differential: The voltage difference between
the unregulated input voltage and the regulated output voltage for which the regulator will operate.
Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not Significantly affected.
Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.
Long Term Stability: Output voltage stability under accelerated life-test conditions after 1000 hours with maximum
rated voltage and junction temperature.
Output Noise Voltage: The rms AC voltage at the output,
with constant load and no input ripple, measured over a
specified frequency range.
Quiescent Current: The part of the positive input current
that does not contribute to the positive load current. The
regulator ground lead current.
Ripple Rejection: The ratio of the peak-to-peak input ripple
voltage to the peak-to-peak output ripple voltage.
Temperature Stability of Vo: The percentage change in
ouput voltage for a thermal variation from room temperature
to either temperature extreme.

RESET OUTPUT
The range of values for the delay capacitor is limited only by
stray capacitances on the, lower extreme and capacitance
leakage on the other. Thus, delay times from microseconds
to seconds are possible. The low charging current, typically
2.0 microamps, allows the use of small, inexpensive disc
capaCitors for the nominal range of 100 to 500 milliseconds.
This is the time required in many microprocessor systems
for the clock oscillator to stabilize when initially powered up.
The RESET output of the regulator will thus prevent erroneous data and/or timing functions to occur during this part of
operation. The same delay is incorporated after any other
fault condition in the regulator output is corrected.

3-118

r-

i:

Circuit Schematic

N

CD

N
UI

~r------+----~~-----+------~

'-i--------I----1~.......;:,..,...-I11

II

3-119

~

r----------------------------------------------------------------------------,

1ld
~ pNational

i~

Semiconductor

LM2926/LlVi2927
Low Dropout Regulator with Delayed Reset
General Description
The LM2926 is a 5V, 500 mA, low dropout regulator with
the L4947 and TLE4260 alternatives. The LM2926 is pindelayed reset. The microprocessor reset ,flag is set low by , for-pin compatible with the LM2925.
thermal shutdown, short circuiis, overvoltage conditions,
dropout, and power-up. After the fault condition is corrected,
Features
the reset flag remains low for a delay time determined by
• 5% output accuracy over entire operating range
the delay capacitor. Hysteresis is included in the reset cir• Dropout voltage typically 350 mV at 500 mA output
cuit to prevent oscillations, and a reset output is guaranteed
• Externally programmed reset delay
down to 3.2V supply input. A latching comparator is used to
• Short circuit proof
discharge the delay capacitor; which guarantees a full reset
• Reverse battery proof
pulse even when triggered by a relatively short fault condi• Thermally protected
tion. A patented quiescent current reduction circui( drops
the ground pin current to 8 mA at full load when the input• LM2926 is pin-for-pin compatible with the LM2925
output differential is 3V or mo~e.
• P + Product Enhancement tested
Familiar PNP regulator features such as reverse battery protection, transient protection, and overvoltage shutdown are
Applications
included in the LM2926 making it suitable for use in automo• Battery operated equipment
tive and battery operated equipment.
• Microprocessor-based systems
The LM2927 is electrically identical to the LM2926 but hase: ' • Portable 'instruments
different pin-out. The LM2927 is pin-for-pin compatible with

Typical Application

Unregulated

Input

'Required n regulator is located far (>2') from power supply filter.
"Co must be at least 10 "F to maintain stability, May be increased without
bound to maintain regulation during transients. Locate as close as possible
to the regulator. This capacitor msut be rated over the same operating temperature range as the regulator. The equivalent series resistance (ESR) of
this capacitor is critical; see curve under Typlcal Performance CharacterIstics.

Delayod

Roset

5

LM2926

~

_ _-VO=5V,500mA

Output

TL/H/l0759-1

Connection Diagrams and Ordering Information
S-Lead TO-220

iiiiii

Front View

Order Number LM2926T
See NS Package Number TOSA

4
5
3
2
1

DELAY
CAPACITOR
DELAYED
RESET OUTPUT
GROUND
OUTPUT VOLTAGE (Vo)
INPUT VOLTAGE (VIN)
TUH/l0759-2

iiiiiii

S-Lead TO-220

Front View

Order Number LM2927T
See NS Package Number TOSA

~4
5 DELAY
OUTPUTCAPACITOR
VOLTAGE (Vo)

3 GROUND
2 DELAYED RESET OUTPUT
1 INPUT VOLTAGE (VIN)
TL/H/l0759-14

3-120

Absolute Maximum Ratings (Note 1)
If Military/ Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
0

Input Voltage
Survival
t = 100ms
t = 1 ms
Continuous

2kV

Power Dissipation (Note 3)

Internally Limited
150"C

Junction Temperature (TJMAX)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

BOV
-50V
-1BVto +26V

Reset Output Sink Current

ESD Susceptibility (Note 2)

Operating Ratings

260"C

(Note 1)

Junction Temperature Range (TJ)

10mA

-40"Cto + 150"C

-40'C to + 125'C

Maximum Input Voltage

Electrical Characteristics VIN =

14.4V, Co

Parameter

=

10 ,...F, -40'C

s: TJS:

26V

125'C, unless otherwise specified.
Typ
(Note 4)

Conditions

Limit
(Note 5)

Units
(Limit)

4.85

V (min)
V
V (max)

REGULATOR OUTPUT
Output Voltage

5 mA s: 10 s: 500 mA,
TJ = 25'C

5
5.15

5 mA

s:

'0

s:

5.25

V (min)
V
V (max)

2S

mV
mV(max)

50

mV
mV(max)

60

mV
mV(max)

3

mA
mA(max)

30

mA
mA(max)

10

mA
mA(max)

60

mA
mA(max)

200

mV
mV(max)

300

mV(max)

600

mV
mV(max)

700

mV(max)

800
3

mA(min)
A
A (max)

60

dB (min)

4.75

500 mA
5

Line Regulation

10
10

Load Regulation
Quiescent Current

10

10
10

Dropout Voltage (Note 6)

10
10
10
10

Short Circuit Current

=

S mA

10
Quiescent Current at Low VIN

=

=
=
=
=
=
=
=

s:

smA, 9V

10

16V

s: VIN s:

SmA, 7V

s:

s:

VIN

1

26V

3

s: SOO mA

S

SmA

2

SOOmA

8

SOmA, VIN

=

SOO mA, VIN
SmA, TJ

=

SV

=

3
2S

6V

2S'C

60

SmA
SOO mA, TJ

= SOOmA
= 8V, RL =

VIN

=

3S0

2S'C

10
2

=

Ripple Rejection

fRIPPLE

Output Impedance

10

Output Noise

10 Hz to 100 kHz, 10

=

120 Hz, VRIPPLE

1 Vrms, 10

50 mAdc and 10 mArms @ 1 kHz

=

50 mA

Long Term Stability
Maximum Operational Input Voltage

=

Continuous

=

SO mA
100

mO

1

mVrms

20

mV/1000 Hr
26

3-121

V (min)

Electrical Characteristics
VIN'.= 14.4V,

Co

= 10 ,...F, -40"C ,:S;: TJ :s;: 125°C, unless otherwise specified (Continued)

Parameter

Conditions

Typ
(Note 4)

Umit
(Note 5)

Units
'(Limit)

80

V (min)

REGULATOR OUTPUT (Continued)
Peak Transient Input Voltage

VO:S;: 7V, RL = 1000, tf = 100 ms

Reverse DC Input Voltage

Vo :2: -0.6V, RL = 1000

-18

V (min)

Reverse Transient Input Voltage

tr = 1 ms; RL = 1000

-50

V (min)

-80
-400

mV(min)
mV
mV(max)

0.4

V (max)

RESET OUTPUT
Threshold

I:.vo Required for Reset Condition (Note 7)
-250

Output Low Voltage

ISINK = 1.6 mA, VIN = 3.2V

Internal Pull-Up Resistance

0.15
30

kO
ms

Delay Time

CDELAY = 10 nF (See Timing Curve)

19

Minimum Operational VIN
onPQwerl!p

Delayed Reset Output :s;: 0.8V,
ISINK = 1.6 mA, RL = 1000

2.2

Minimum Operational Vo
on Power Down

Delay Reset Output :s;: 0.8V,
ISINK = 10,...A, VIN = OV

3.2
0.7

V
V (min)
V

DELAY CAPACITOR PIN
Threshold Difference (b.VDELAY)

Change in Delay Capacitor Voltage Required for
Reset Output to Return High

4.1

V (min)
V
V (max)

1.0

,...A (min)

3.0

,...A
,...A(max)

3.5
3.75

Charging Current (IDELAY)
2.0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional. but do not guarantee specific performance limits. For guaranteed specHications and test conditions. see the Electrical Characlarfstlc..
Nota 2: Human body model; 100 pF discharged through a 1.5 kll resistor.
Nota 3: The maximum power dissipation Is a function of TJMAX. and 8JA> and TA, and is IimHed by thermal shutdown. The maximum allowable power dissipation at
any ambient temperature Is Po = (TJMAX-TpJI8JA. If this dissipation is exceeded, the die temperature will rise above 150'C and the device will go into thermal
shutdown. For the LM2926 and LM2927, the iunction-to-ambient thermal resistance Is 53'C/W, and the iunctlon·t~se thermal resistance is :r'C/W.
Note,4: Typicals are at TJ = 25"C and represent the most likely perametric norm.
Note 5: Umits ere 100% guaranteed by production testing.
Note 6: Dropout voitsge is the input· 0.7V.

EXTERNAL CAPACITORS
The LM292617 output capacitor is required for stability.
Without it, the regulator output will oscillate at amplitudes as
high as several volts peak-to-peak at frequencies up to
500 kHz. Although 10 ,...F is the minimum recommended
value, the actual size and type may vary depending upon
the application load and temperature range. Capacitor
equivalent series resistance (ESA) also affects stability. The
region of stable operation is shown in the Typical Performance Characteristics (Output Capacitor ESA curve).
Output capacitors can be increased in size to any desired
value above 10 ,...F. One possible purpose of this would be
to maintain the output voltage during brief conditions of input transients that might be Characteristic of a particular
system.
Capacitors must also be rated at all ambient temperatures
expected in the system. Many aluminum electrolytics freeze
at temperatures below -30·C, reducing their effective capaCitance to zero. To maintain regulator stability down to
- 40·C, capacitors rated at that temperature (such as tantalums) must be used.

N
CD
N

en
......

ri:

N
CD
N

.....

....~------~-+-1~~
Rl

~

-=-=-

DELAYED RESET
The delayed reset output is deSigned to hold a microprocessor in a reset state on system power-up for a programmable
time interval to allow the system clock and other powered
circuitry to stabilize. A full reset interval is also generated
whenever the output voltage falls out of regulation. The circuit is tripped whenever the output voltage of the regulator
is out of regulation by the Aeset Threshold value. This can
be caused by low input voltages, over current conditions,
over-voltage shutdown, thermal shutdown, and by both
power-up and power-down sequences. When the reset circuit detects one of these conditions, the delay capacitor is
discharged by an SCA and held in a discharged state by a
saturated NPN switch. As long as the delay capacitor is held
low, the reset output is also held low. Because of the action
of the SCA, the reset output cannot glitch on noise or transient fault conditions. A full reset pulse is obtained for any
fault condition that trips the reset circuit.

Resistor

R3
30kJl

.~""'-----I

RE5rt~

External Pull-up

100kJl

SOkJl

.....-1-....... Delayed Reset Output
Q2

TL/H/10759-6

FIGURE 1, Delay Reset Output

The static reset characteristics are' shown in Figure 2. This
shows the relationship between the input voltage, the regultor output and reset output. Plots are shown feir various external pull-up resistors ranging in value from 3 kO to an
open circuit. Any external pull-up resistance causes the reset output to follow the regUlator output until 02 is biased
ON. COELAY has no effect on this chBracteristic.

When the output regains regulation, the SCA is switched off
and a small current (IOELAY = 2 p.A) begins charging the
delay capacitor. When the capacitor voltage increases
3.75V (I1VOELAY) from its discharged value, the reset output
is again set HIGH. The delay time is calculated by:
delay time = COELAY 11 VOELAY
IOELAY

TIME (pa)

(1)

TUH/l0759-7

FIGURE 2. Reset Output Behavior during Power-Up

or

Figure 2 is useful for determing reset performance at any
particular input voltage. Dynamic performance at power-up
will closely follow the characteristics illustrated in Figure 2,
except for the delay added by COELAY when Vo reaches 5V.
The dynamiC reset characteristics at power-down are illustrated by the curve shown in Figure 3. At time t = 0 the input
voltage is instantaneously brought to OV, leaving the output
powered by Co. As the voltage on Co decays (discharged
by a 1000 load resistor), the reset output is held low. As Vo
drops below 0.7V, the reset rises up Slightly should there be
any external pull-up resistance. With no external resistance,
the reset line stays low throughout the entire power down
cycle. If the input voltage does not fall instantaneously, the
reset signal will tend to follow the performance characteristics shown in Figure 2.

delay time z 1.9 X 106 COELAY
(2)
The constant, 1.9 x 106, has a ±20% tolerance from device to device. The total delay time error budget is the sum
of the 20% device tolerance and the tolerance of the external capaCitor. For a 20% timing capacitor tolerance, the
worst case total timing variation would amount to ± 40%, or
a ratio of 2.33:1. In most applications the minimum expected
reset pulse is of interest. This occurs with minimum COELAY,
minimum I1VOELAY, and maximum IOELAY. I1VOELAY and
IOELAY are fully specified in the Electrical Characteristics.
Graphs showing the relationship between delay time and
both temperature and COELAyare shown in the Typical
Performance Characteristics.

3-125

•

Applications Information

(Continued)

SYSTEM DESIGN CONSIDERATIONS
Many microprocessors are specified for operation at 5V
± 10%, although they often continue operating well outside
this range. Others, such as certain members of the COPS
family of microcontrollers, are specified for operation as low
as 2.4V.

-

9V Battery ...-~.......;::.t

Delayed
Re..t
Output

RL = 100A
Co= 10pF
Cdalay =0

VIN

5

"

BaHery Powered Regulator with Flashing
LED for Low BaHery Indication

~

5V/500 rnA

\

3

~o~r

2

VRESET

~

R=~10k

•

Rr ~
k

o

Your
LM2926/27

o

LN3909

~
500 1000 1500 2000 2500 3000

+

100pF

nME (ps)
TL/H/l0759-8

FIGURE 3. Reset Output Behavior during Power-Down
Of particular concern is low voltage operation, which occurs
in battery operated systems when the battery reaches the
end of its discharge cycle. Under this condition, when the
supply voltage is outside the guaranteed operating range,
the clock may continue to run and the microprocessor will
attempt to execute instructions. If the supply voltage is outside the guaranteed operating range, the instructions may
not execute properly and a hardware reset such as is supplied by the LM 292617 may fail to bring the processor under control. The LM292617 reset output may be more efficiently employed in certain applications as a means of defeating memory WRITE lines, clocks, or external loads, rather than depending on unspecified microprocessor operating
conditions.
In critical applications the microprocessor reset input should
be fully characterized and guaranteed to operate until the
clock ceases oscillating.

TLlH/l0759-9

General Microprocessor Configuration
VINo----~·

Delayed

Reset

Your

5V/5oornA

LN2926/27

Output

INPUT TRANSIENTS
The LM292617 are guaranteed to withstand positive input
transients to BOV followed by an exponential decay of
T = 20 ms (tf = 100 ms, or 5 time constants) while maintaining an output of less than 7V. The regulator remains
operational to 26 Voc, and shuts down if this value is exceeded.

AooRESS
BUS

pP

TL/H/l0759-10

3-126

Applications Information

(Continued)

Using the Reset to De-Activate Power Loads. The LM1921 is a Fully Protected 1 Amp High-Side Driver.
VIN

o-.....- - - - - - - - -.........:+~I----.
1 ~F
.----'-.....;.::;;;...,

Delayed
Reset
Output

.J:.

VOUT

5V/500 rnA

LM2926/27

.I.
TUH/l0759-11

Generating an Active High Reset Signal

Using the Reset to Ensure an Accurate Display
on Power-Up or Power-Down
VINo-...- - - - - - -.....-+""I1---.

I~F

Delayed
Reset
Output

.J:.

LM2926/27

lk
TLlH/l0759-12

I1J.1F
Reset

Tl/H/l0759-13

•
3-127

....

~

('

'

:; t!lNational Semiconductor
.

..~',. "

LM2931 Series Low Dropout Regulators
General Description·

Features

The LM2931 positive voltage regulator features a very low
quiescent current of 1 mA or less when ·supplying 10.rnA
loads. This unique characteristic and the extremely low input-output differential required for proper regulation (0.2V
for output currents of 10 mAl make the LM2931 the ideal
regulator for standby power systems. Applications include
memory standby circuits, CMOS and other low power processor power supplies as well as systems demanding. as
much as 100 mA of output current.
Designed originally for automotive applications, the LM2931
and all regulated circuitry are protected from reverse battery
installations or 2 battery jumps. During line·translents, such
as a load dump (60V) when the input voltage to .the regula-·
tor can momentarily exceed the specified maximum operat-.
ing voltage, the regulator will automatically shut down to
protect both internal circuits and the load. The LM2931 cannot be harmed by temporary mirror-image insertion. Familiar
regulator features such as short circuit and thermal overload
protection are also provided.

•
•
•
•
•
•
•
•
•
•
•

The LM2931 family includes a fixed 5Voutput (±3.8% tolerance for A grade) or an adjustable output with ON/OFF pin.
Both versions are available in a TO-220 power package,
TO-263 surface. mount. package, and an 8.-lea!! surface
mount package. The. fixed output version is also available in
the TO-92 plastic package.

Very low quiescent current
Output current in excess of 100 mA
Input-output differential less than 0.6V
Reverse battery protec~ion
SOV load dump protection
- 50V reverse transient protection
Short circuit protection
Internal thermal overload protection
Mirror-image insertion protection
Available in TO-220, TO-92, TO-263 or 50-8 packages
Available as adjustable with TIL compatible switch

Output Voltage Options
Output
Number

Part Number

Package
Type

LM2931T-5.0,lM2931AT-5.0 3-Lead TO-220
5V

LM2931S-5.0, LM2931AS-5.0 3-Lead TO-263
LM2931Z-5.0, LM2931AZ-5.0 T0-92
LM2931M-5.0, LM2931AM-5.0 8-Lead SO

Adjustable, LM2931CT

5-Lead TO-220

3V to 24V

LM2931 CS

5-Lead TO-263

LM2931CM

8-Le.adSO

Typical Applications
LM2931 Fixed Output
VIN
UNREGULATED
INPUT

LM2931

C~';l GN~ln

LM2931 Adjustable Output
Vee

VOUT
REGULATED
OUTPUT

+ C2**

T

R3
51k

10hF

OFF

TUH/5254-4

ON/OFF

'Required if regulator . is located far from POWl'r supply. ~ller.
"C2 musl be al leas1 I 00 ,.F to maintain slability. May be increased without
bound 10 maintain regulation during transients. Locate as close as possible
to the regulator. This capacitor must be rated over the same operating temperature range as the regulator. The equivalent series resistance (ESR) of
this capacitor is critical; see curve.

LMZ931
ADJUSTABLE

ON

TL/H/5254-5
RI + R2
VOUT ~ Reference Voltage X -R-INote: Using 27k for RI will automatically compensate for errors in Vour due
to the input bias current of the ADJ pin (approximately I pA).

3-128

Connection Diagrams and Ordering Information
FIXED SV OUTPUT
TO-220 3-Lead Power Package

TO-263 Surface-Mount Package

O....:;~:JIL...J~====~:~

T A B U S OUTPUT
GND
GND

LI

INPUT
TL/H/5254-11

TL/H/5254-6

Front View

Top View

Order Number LM2931T-S.O or LM2931AT-S.O
See NS Package Number T03B

TL/H/5254-12

Side View
Order Number LM2931S-S.0 or LM2931AS-S.O
See NS Package Number TS3B
8-Pin Surface Mount
OUT- , .

8 rlN

GND- 2

7 r-GND

GND- 3

6 rGND

TQ-92 Plastic Package
O U T B IN

GND

NC· - ........
" __5...r- NC·
ONe

~

TL/H/5254-8

Bottom View

TL/H/5254-7

Not internally connected

Order Number LM2931Z-S.0 or LM2931AZ-S.O
See NS Package Number Z03A

Top View
Order Number LM2931M-S.O or LM2931AM-S.O
See NS Package Number M08A
ADJUSTABLE OUTPUT VOLTAGE
TO-220 S-Lead Power Package

TQ-263
5-Lead Surface-Mount Package

[Io~~~]I[~oJI~~~~~ ~ t~8~f

TAB O S OUT
GND
b~D
ON/OFF
ADJUST

TUH/5254-9

TL/H/5254-13

Front View

Top View

Order Number LM2931CT
See NS Package Number TOSA

rC:::h.

TL/H/5254-14

Side View
Order Number LM2931CS
See NS Package Number TSSB
8-Pln Surface Mount
OUT- , .

8 r-IN

GND -

2

7 r GND

GND- 3

6 r-GND

ADJ - ..4_ _ _5...r- ON/OFF
TUH/5254-10

Top View
Order Number LM2931CM
See NS Package Number M08A

3-129

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage
26V
Operating Range
Overvoltage Protection
LM2931A, LM2931CT, LM2931CSAdjustabie
60V
50V
LM2931

Internal Power Dissipation
(Notes 1 and 3)

Internally Limited

Operating Ambient Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)
ESD Tolerance (Note 4)

- 40"C to

+ 85'C
125'C

-65'Cto

+ 150"C
230'C
2000V

Electrical Characteristics for Fixed 5V Version
VIN = 14V, 10 = 10 rnA, TJ = 25'C, C2 = 100 ,...F (unless otherwise specified) (Note 1)
LM2931A·5.0
Conditions

Parameter

Typ
Output Voltage

5
6.0V :s;; VIN :s;; 26V, 10 = 100 rnA
-40"C:s;; Tj :s;; 125'C

Limit
(Note 2)

LM2931·5.0
Typ

Limit
(Note 2)

5.19
4.81

5.25
4.75

VMAX
VMIN

5.25
4.75

5.5
4.5

VMAX
VMIN
mVMAX
mVMAX

Line Regulation

9V:S;; VIN:S;; 16V
6V S VIN S 26V

2
4

10
30

2
4

10
30

Load Regulation

5 rnA s .10 s 100 rnA

14

50

14

50

Output Impedance

100 mADC and 10 mArms,
100 Hz-l0 kHz

200

Quiescent Current

10 S 10mA,6V S VIN S 26V
-40'C S Tj :s;; 125'C
10 = 100 rnA, VIN = 14V, Tj = 25'C

0.4

1.0

0.4

15

30

15

200

10 Hz-l00 kHz, COUT = 100,...F

Long Term Stability

1.0

mAMAX
mAMIN

500

""VrmsMAx

20

20

mV/l000 hr

Ripple Rejection

fo = 120Hz

80

55

80

10 = lOrnA
10 = 100 rnA

0.05
0.3

0.2
0.6

0.05
0.3

33
RL = 5000, Vo S 5.5V,
T = 1 ms, T S 100 ms

Reverse Polarity Input
Voltage, DC

Vo

Reverse Polarity Input
Voltage, Transient

T = 1 ms,

~

dBMIN
0.2
0.6

VMAX
VMAX

26

VMAX
VMIN

33
26

Maximum Line Transient

mAMAX

500

Dropout Voltage
Maximum Operational
Input Voltage

mVMAX
mOMAX

5
Output Noise Voltage

Units
Limit

70

60

70

50

VMIN

-30

-15

-30

-15

VMIN

-80

-50

-80

-50

VMIN

-0.3V, RL = 5000
T

:s;; 100 ms, RL = 5000

Note 1: See circuit in Typical Applications. To ensure constant junction temperature, low duty cycle pulse testing is used.
Note 2: Alilimijs are guaranteed for TJ - 2S'C (standard type face) or over the full operaUng juncUon temperature range of - 40"C to + 12S'C (bold type face>Note 3: The m8ldmum power dissipation is a function of maximum junction temperature TJmax, total thermal resistance 8JA, and ambient temperature TA. The
maximum allowable power dissipation at any ambient temperature is Po - (TJmax - T/'J18JA. II this dissipation is exceeded, the die temperature will rise above
15O"C and the LM2931 will go into thermal shutdown. For the LM2931 in the TO-92 package, 8JA is 195'C/W; in the 50-8 package, 8JA is 16O'C/W, and in the TO220 package, 8JA is SO"C/W; and in the T0-263 package, 8JA Is 73'C/W. If the TO-220 package Is used with a heat sink, 8JA is the sum of the package thermal
resistance junction-to-case of 3'C/W and 1he thermal resistance added by the heat sink and thermal interface.
If the TO-263 package is used, the thermal resistance can be reduced by increasing the P.C. board copper area thermally connected to the package: Using O.S
square inches of copper area, (JJA is 50°C/W; with 1 square inch of copper area, (JJA is 37"C/W; and with 1.6 or more square inches of copper area, 8JA is 3?!C/W.

Note 4: Human body model. 100 pF discharged through I.S kfi.

3-130

Electrical Characteristics for Adjustable Version
VIN = 14V, VOUT = 3V, 10 = 10 mA, TJ = 25°C, R1 = 27k, C2 = 100,..F (unless otherwise specified) (Note 1)
Parameter

Conditions

Reference Voltage

Typ

Limit

Units
Limit

1.20

1.26
1.14

VMAX
VMIN

1.32
1.08

VMAX
VMIN

24
3

VMAX
VMIN
mVIVMAX

10 ~ 100 mA, -40°C:;; Tj :;; 125°C, R1 = 27k

Measured from VOUT to Adjust Pin
Output Voltage Range
Line Regulation

VOUT

+

Load Regulation

5mA

~

Output Impedance

100 mAce and 10 mA,ms, 100 Hz-10 kHz

40

Quiescent Current

10 = 10mA
10 = 100mA

During Shutdown RL = 500n

0.4
15
0.8

10 Hz-100 kHz

100

",V,mslV

0.4

%/1000 hr

Output Noise Voltage

0.6V :;; VIN :;; 26V

0.2

1.5

10:;; 100mA

0.3

1

Long Term Stability

%MAX
mOIV

1
1

mAMAX
mA
mAMAX

Ripple Rejection

fo=120Hz

0.02

Dropout Voltage

10:;; 10mA
10 = 100mA

0.05
0.3

0.2
0.6

VMAX
VMAX

33

26

VMIN

70

60

VMIN

-30

-15

VMIN

-80

-50

VMIN

2.0
2.2

1.2
3.25

VMAX
VMIN

20

50

,..AMAX

Maximum Operational Input
Voltage
Maximum Line Transient

10 = 10 mA, Reference Voltage:;; 1.5V

T = 1 mS,T:;; 100ms
Reverse Polarity Input
Voltage, DC

Vo;;' -0.3V, RL = 500n

Reverse Polarity Input
Voltage, Transient

T = 1 ms,

On/Off Threshold Voltage
On
Off

Vo=3V

T :;;

%IV

100 ms, RL = 500n

On/Off Threshold Current

•
3-131

~ .-------------------------------------------------------~------------------------,

t")

~

:s

Typical Performance Characteristics
Drqpout Voltage

Dropout Voltage

0.6

I I

i: ,

10.2 .,.,.
i

0.1

I

-

i

I

r~

10=10mA

80

:E

I

,

2.0
1.0

2.0

4.0
5.0.
Input YoIIIge (V)

3.Q

Output Current (mA)

Output at Voltage Extremes

Line Transient Response

6;0

Load Transient Response

VIN' VOUT = 'IV
C2 1= 100~F".

LM2931·5.O
1\ z SOOO

10

~

~

100

50

120

Junction Temperetu.. (C)

12

0

V

J I
40

1'5

3.0

~

IQ=SOmA

~

i

4.0

, -~

E

10 = 100 mA_

.--t""""

LM2931·5.O
10 = 100 mA

5.0

I

!

1

Low Voltage Behavior
6.0

0.6

8
6

1o

I

2

I

L I-....

II

ISO H~+-+-+-"'+-H-+-l

o·t;tt:tt1::ttW;1j

-2
-20 -10

0 10 20 30 40

so

Time

1nput~(V)

Peak Output Current
500 -

1400

Tj

J

(~s)

Quiescent Current

Quiescent Current
25

I

1300

i~

.U

1 ZOO
o

C 25

-~

.!.

T = 8S"C
,;'
I..l.~

~
u

11

1

'i! 20

i

= -40'C

•

i

15

u

10

j
~

~

100

o
o

10

20

o

30

~~

o

30

Quiescent Current

~ =ll00lmA -

I

-

I--

~ z ~ ~1
10

= 10 mAl

-S
-20 -10 0 10 20 30 40
Input VoIIIge (V)

so

75

~~ - r-

60

d

f - - r- 101=

o
-40

10

100

/

~
lk

I

10k lOOk 1M

Frequency (Hz)

80

120

Ripple Rejection

I

1

40

~mL - r-

85

C2 = 100 ~F TANT

LM2931·5.O
1o=10mA

o

-

-

Junction Tempe....... ('C)

tI'~

i :so
45

I

1o=50mA

.11

90

C2 = 100 pF AWM

j:

I I 11

-

I

80

I I I

I"F--I...J

15
10

Ripple Rejection
85

I I I
r-- I--

60

20

Output Current (mA)

Input Voltage (V)

35

45

Time (Ill)

VIN = 14V

2S"C

30

15

45

30

600

o

30

15

60

80

I

75

...

55

II :
60

50
45

10 = 120 Hz

I
o

25

50

75

100

Output Current (mAl
TL/H/5254-2

3·132

r-

iii:

Typical Performance Characteristics

.....

Operation During load
Dump

Output Impedance
10

N
CD
W

Reference Voltage
1.30

lIn:~1-5.

10= lOrnA

E

Jr-...

1

~
~

i

V

1

LII42931CT ADJUSTABLE

1.28
1.26

1.24
1.22

......

1.20
1.18

r-...

1.16

.......

1.14

......

1.12

0.0 1
1

1.10

10

100

lk

10k

tOOk

It.!

100

FREQUENCY (Hz)

Maximum Power Dissipation
(SO-8)

.......

0.8

......

£

0.7

g

.......

o.s

t-....

0.5
0.4

300

400

.......

~

illis

i

0.3
0.2

o

AI.lBIENT TEMPERATURE (oc)

i

"'I.. I I
"'I...N

i!'

8 JA =37°C/W-""""

r .,....,..."

f-

o

o

-t-1"

I=
JA

~

,to-.

..... I':

i3'Cj;~
1 I· 1 ~:::t

10 20 30 40 50 60 70 80 90100
AMBIENT TEMPERATURE ('c)

o.s
0.5

-

~

-

0.4
0.3
0.2

~
g
~

~

t-....
,...

I
I I
I

18

21

24

I
I

~

0.12S" LEAD LENGTH

-

~ROM PC BOARD

:;::...

I" JAR. " r--:

0.+" LEAD
LENGTI-I FRO

~
~

I

0.1

I

0

o

10 20 30 40 50 60 70 80 90100

10 20 30 40 50 60 70 80 90
A"BIENT TE"PERATURE ('c)

OnlOff Threshold

:s

9 JA = 32°C/W

illis

:--.

0.7

AMBIENT TEMPERATURE ('C)

Maximum Power Dissipation
(To-263) (See Note 3)

I I

'~"

0.8

~

i"""t--.

NO HElrs'NK

15

Maximum Power Dissipation
(To-92)

£z

t--.

-

12

0.9

r-+--

10 20 30 40 50 60 70 aD 90

....:!JA = 50'C/W

9

1.0

22
INriNITE HEAT SINK
20
18
16
14
12
10 ~r-- ~'C W HEAT SIN
8

o

.....t. I ...... ~

o

OUTPUT VOLT AGE (V)

o. 1
o

500

Maximum Power Dissipation
(T0-220)

1.0
0.9

200

TIME(ms)

Output CapaCitor ESR

4.0
CoUT'" 100 ~F

LM2931CT ADJUSTABLE

3.8

Vo=5V

3.6
3.4
3.2

OFF

3.0

1

;'

2.8

V"

2.6

~
STABLE

o.

2.4

"

2.2
2.0

REGION

1

o

1
9

12

15

18

OUTPUT VOLTAGE (V)

21

24

20

40

60

80

100

OUTPUT CURRENT (mA)

TUH/5254-3

•
3-133

..-

('I)

0»

~

Schematic Diagram
V,No-9------------------------------1~--------------~

.,

5V:28!k

ADJ:oo

"IZ
30k

HZ
5V: 100k
ADJ:oo
RI8

14.7k
GND

TL/H/5254-1

3·134

Application Hints
One of the distinguishing factors of the LM2931 series regulators is the requiremont of an output capacitor for device
stability. The value required varies greatly depending upon
the application circuit and other factors. Thus some comments on the characteristics of both capacitors and the regulator are in order.

At this point, ths procedure for bench testing the minimum
value of an output capacitor in a special application circuit
should be clear. Since worst-case occurs at minimum operating temperatures and maximum operating currents, the
entire circuit, including the electrolytic, should be cooled to
the minimum temperature. The input voltage to the regulator
should be maintained at 0.6V above the output to keep internal power dissipation and die heating to a minimum.
Worst-case occurs just alter input power is applied and before the die has had a chance to heat up. Once the minimum value of capacitance has been found for the brand
and type of electrolytic in question, the value should be doubled for actual use to account for production variations both
in the capacitor and the regulator. (All the values in this
section and the remainder of the data sheet were determined in this fashion.)

High frequency characteristics of electrolytic capacitors depend greatly on the type and even the manufacturer. As a
result, a value of capacitance that works well with the
LM2931 for one brand or type may not necessary be sufficient with an electrolytic of different origin. Sometimes actual bench testing, as described later, will be the only means
to determine the proper capacitor type and value. Experience has shown that, as a rule of thumb, the more expensive and higher quality electrolytics generally allow a smaller
value for regulator stability. As an example, while a highquality 100 ,..F aluminum electrolytic covers all general application circuits, similar stability can be obtained with a tantalum electrolytic of only 47 ,..F. This factor of two can generally be applied to any special application circuit also.

Definition of Terms
Dropout Voltage: The input-output voltage differential at
which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has
dropped 100 mV from the nominal value obtained at 14V
input, dropout voltage is dependent upon load current and
junction temperature.
Input Voltage: The DC voltage applied to the input terminals with respect to ground.
Input-output Differential: The voltage difference between
the unregulated input voltage and the regulated output voltage for which the regulator will operate.
Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected.
Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.

Another critical characteristic of electrolytics is their performance over temperature. While the LM2931 is deSigned
to operate to -40'C, the same is not always true with all
electrolytics (hot is generally not a problem). The electrolyte
in many aluminum types will freeze around -30'C, reducing
their effective value to zero. Since the capacitance is needed for regulator stability, the natural result is oscillation (and
lots of it) at the regulator output. For all application circuits
where cold operation is necessary, the output capacitor
must be rated to operate at the minimum temperature. By
coincidence, worst-case stability for the LM2931 also occurs at minimum temperatures. As a result, in applications
where the regulator junction temperature will never be less
than 25'C, the output capacitor can be reduced approximately by a factor of two over the value needed for the
entire temperature range. To continue our example with the
tantalum electrolytic, a value of only 22 ,..F would probably
thus suffice. For high-quality aluminum, 47 ,..F would be adequate in such an application.

Long Term Stability: Output voltage stability under accelerated life-test conditions after 1000 hours with maximum
rated voltage and junction temperature.

Another regulator characteristic that is noteworthy is that
stability decreases with higher output currents. This sensible
fact has important connotations. In many applications, the
LM2931 is operated at only a few milliamps of output current or less. In such a circuit, the output capacitor can be
further reduced in value. As a rough estimation, a circuit that
is required to deliver a maximum of 10 mA of output current
from the regulator would need an output capacitor of only
half the value compared to the same regulator required to
deliver the full output current of 100 mAo If the example of
the tantalum capacitor in the circuit rated at 25'C junction
temperature and above were continued to include a maximum of 10 mA of output current, then the 22 ,..F output
capacitor could be reduced to only 10 ,..F.

Output Noise Voltage: The rms AC voltage at the output,
with constant load and no 'input ripple, measured over a
specified frequency range.
Quiescent Current: That part of the positive input current
that does not contribute to the positive load current. The
regulator ground lead current.
Ripple Rejection: The ratio of the peak-to-peak input ripple
voltage to the peak-to-peak output ripple voltage at a specified frequency.
Temperature Stability of Vo: The percentage change in
output voltage for a thermal variation from room temperature to either temperature extreme.

In the case of the LM2931 CT adjustable regulator, the minimum value of output capacitance is a function of the output
voltage. As a general rule, the value decreases with higher
output voltages, since internal loop gain is reduced.

3-135

•

~ r-------~------------------------------------------------------------------_,

(f)

~

tfI

Na t i 0 na I S e m ,i

0 0

n due tor

LM2935 Low Dropout Dual Regulator
General Description

Features

The LM2935 dual 5V regulator provides a 750 mA output as
well as a 10 mA standby output. It features a low quiescent
current of 3 mA or less when supplying 10 mA loads from
the 5V standby regulator output. This unique characteristic
and the extremely low input-output differential required for
proper regulation (0.55V for output currents of 10 mAl make
the LM2935 the ideal regulator for power systems that include standby memory. Applications include microprocessor
power supplies demanding as much as 750 mA of output
current.
Designed for automotive applications, the LM2935 and all
regulated circuitry are protected from reverse battery installations or 2 battery jumps. During line transients, such as a
load dump (60V) when the input voltage to the regulator can
momentarily exceed the specified maximum operating voltage, the 0.75A regulator will automatically shut down to' protect both internal circuits and the load while the standby
regulator will continue to power any standby loa(j. Tile
LM2935 cannot be harmed by temporary mirror-image insertion. Familiar regul,ator',featurE1s such as short circuit and
thermal overload protection are also provided.

•
•
•
•
•
•
•
•
•
•
•
•
•

Two 5V regulated outputs
Output current in excess of 750 mA ,
Low quiescent current- standby regulator
Input-output differential less than 0.6V at 0.5A
Reverse battery protection
60V load dump protection
- 50V reverse transient protection
Short circuit protection
Internal thermal overload protection
Available in 5-lead TO-220
ON/OFF switch controls high current output
Reset error flag
P+ Product Enhancement tested

Typical Application Circuit
'Required '" regulator is located far Irom power
supply filter.

INPUT
VOLTAGE

OUTPUT 2
Your 5V
VOLTAGE
~ C2' ~50 mA

~10~F

Rl

20k

RESET
FLAG

o-...___,......;4~' :~HI

*

5
GND

I

13

...
1 _ _ _ _---'

C3"

ulation during transients. Locate as close as possible to the regulator. This capa~or must be rated over the' same 'operating temperature range
as the regulator, The equivalent series resistance
(ESR) of this capaCitor is critical; see curve.

LM2935 '

(FOR Your ONLY)

"CoUT must be at least 10 p.F to maintain stability.
May be increased ~hout bound to maintain reg-

STANDBY 5V
OUTPUT 10 mA

10 ~F

*

TUH/5232-1

FIGURE 1. Test and Application Circuit

Connection Diagram
TD-220 5-Lead

1~.1 I

~ 5 STANDBY OUTPUT

4 SWITCH/RESET
3 GROUND
2 OUTPUT VOLTAGE (Vour)
1 INPUT VOLTAGE (V'N)
TL/H/5232-8

Front View

Order Number LM2935T
See NS Package Number T05A

3-136

Absolute Maximum Ratings
Internal Power Dissipation (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage
Operating Range
26V
OverVoltage Protection
60V

Operating Temperature Range

Internally Limited
-40'Cto

+ 125'C

-65'Cto

+ 150'C

Maximum Junction Temperature

150'C

Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

230'C

Electrical Characteristics for VOUT
VIN = 14V, 10 = 500 mA, TJ = 25'C (Note 4), C2 = 10,...F (unless otherwise specified)

Parameter

Conditions

Output Voltage

6V:5:VIN:5:26V, 5 mA:5:lo:5:500 mA,
-40'C:5:TJ:5: 125'C (Note 2)

Line Regulation

9V:5:VIN:5:16V, 10=5 mA
6V:5:VIN:5:26V.lo=5 mA

Typ

Tested
Limit
(Note 3)

Units
Limit

5.00

5.25
4.75

VMAX
VMIN

4
10

25
50

mVMAX
mVMAX

10

50

mVMAX

Load Regulation

5 mA:5: 10:5: 500 mA

Output Impedance

500 mADC and 10 mArms, 100 Hz-10kHz

200

Quiescent Current

10:5: 10 mA, No Load on Standby
10 = 500 mA, No Load on Standby
10 = 750 mA, No Load on Standby

3
40
90

10 Hz-100 kHz

100

""Vrms

20

rriVl1000hr

Output Noise Voltage
Long Term Stability

mO
mA
100

mAMAX
mA

Ripple Rejection

fo=120Hz

66

Dropout Voltage

10=500mA
10=750mA

0.45
0.82

0.6

VMAX

Current Limit

1.2

0.75

AMIN

Maximum Operational
Input Voltage

31

26

VMIN

70

60

V

-30

-15

V

Maximum Line Transient

Vo:5:5.5V

Reverse Polarity Input
Voltage, DC

dB

Reverse Polarity Input
Voltage, Transient

1 % Duty Cycle, T:5: 100 ms,
100 Load

-80

-50

V

Reset Output Voltage
Low
High

R1 =20k, VIN=4.0V
R1 =20k, VIN= 14V

0.9
5.0

1.2
6.0
4.5

VMAX
VMAX
VMIN

Reset Output Current

Reset=1.2V

ON/OFF Resistor

R1 (± 10% Tolerance)

5

mA
20

kOMAX

Note 1: Thermal resistance without a heat sink for junction to case temperature is 3°C/W(T0-220). Thermal resistance for TO·220 case to ambient temperature is

so- C/W.

Note 2: The temperature extremes are guaranteed but not 1OO~ production tested. This parameier is not used to calculate outgoing AQL.
Note 3: Tested Limits are guaranteed and 100% tested in production.

Note 4: To ensure constant junction temperature, low duty cycle pulse testing is used.

3-137

•

Electrical Characteristics for Standby Output
10=10 mAo VIN=14V. S1 open. CoUT=10 ,..F. TJ=25°C (Note 4). (unless otherwise specified)
Standby Output
Conditions

Parameter

Typ

Tested
Limit

Units
Limit

5.00

5.25
4.75

VMAX
VMIN

Output Voltage

10:S:10mA.6V:S:VIN:S:26V.
-40"C:S:TJ:S:125°C

Tracking

VOUT-Standby Output Voltage

50

200

mVMAX

Line Regulation

6V:S:VIN:S:26V

4

50

mVMAX

Load Regulation

1 mA:S:lo:S:10 mA

10

50

mVMAX

Output Impedance

10 mAoc and 1 mArms.100 Hz-10 kHz

1

Quiescent Current

10:S:10 mAo
VOUT OFF (Note 2)

2

Output Noise Voltage

10 Hz-100 kHz

Long Term Stability

0
3

mAMAX

300

,..V

20

mV/1000 hr
dB

Ripple Rejection

fo= 120 Hz

66

Dropout Voltage

10:S:10 mA

0.55

0.7

VMAX

70

25

mAMIN

70

60

VMIN

-30

-15

VMIN

-80

-50

VMIN

Current Limit
Maximum Operational
Input Voltage

Vo:S:6V

Reverse Polarity Input
Voltage. DC

Vo~

Reverse Polarity Input
Voltage, Transient

1% Duty Cycle T:s: 100 ms
5000,Load

-0.3V. 5100 Load

Typical Circuit Waveforms
80V

~

INPUT
VOIJA6E 14V
PIN 1

31V

"'

(V)

SI~:': OPEN

(V)

RESET
VOIJAGE
PIN.
(V)

ov-

V

ov-

OPEN

av

\1

~

~

ov

I

U U

I

5V

5V

5V

L/

I ---.J

I~
~

5V

~

(V)

SymM
COHomOH

14V

C

5V

STANDBY

VOLTAGE
PINS

?r-t.D

5V

OUTPUT
VOLTAGE
PlH2

3V

TURN
ON

LOAG
DUMP

LOWVJN

UHE NOISE. ETC.

Vaur

SHORT
CIRCUIT

THERMAL
SHUTDOWN

TURN
OFF '
TLlH/5232-2

FIGURE 2

3·138

r-------------------------------------------------------------------------------------, r-iii:
Typical Performance Characteristics

N
CD
Co)

CII

Dropout Voltage (VOUT)

Dropout Voltage (VOUT)

~ 1.0

~

!

III
~
~ 0.8

I

loor=5OO mA

is 0.4

~

i

~

t-:;

0.2

;!

1

0
-40

40

80

120

~

0.9
~ 0.8
.... 0.7
~ 0.6
~ 0.5
is 0.4
~ -0.3

- ~J=loL-

0.6

160

~
!!

Dropout Voltage (VSTBY)

1

0.9
~ 0.8
~ 0.7
0.6
III 0.5

L

~

~

0.4

0.3
§ 0.2
~ 0.1
~
o
!!
o

1..00'

0
0 100 200 300 400 500 600 700 800

JUNCTION TEMPERATURE 1°C)

10

OUTPUT CURRENT ImA)

Low Voltage Behavior

15

20

OUTPUT CURRENT ImA)

Output Voltage (VOUT)

lour =500 mA
ISTTiY =10 mA

oil!!!!.

l?

~

0.2
0.1

,...

i

Output Voltage (VSTBY)
RL-5000

RL=lOO

II

Vsr~~ "Your
~

rJ
I~
-1

o

o

2 3 4 5 6
INPUT VOLTAGE IV)

1

7

8

'-

0

20

40

-2

60

1i i

... l$ -

10

Load Transient Response
(VOUT)

A

... -

1

~l

""'"" IV

I'"

II

~!

~

.J

0

~!!!i

IL

-50

I'

-150

40

50

o

60

TIME (pa)

30 40
TlME(pa)

Load Transient Response
(VSTBY)

Peak Output Current (VOUT)

150 r-.,..--r-~.,..--r-~-'
100
50

10

20

g

0.8

=:! ~

0.6
0.4

I-+-+-t-+-+-t--I
l--±--+-+---il--+-+--:I

I-"t,""-+,...-f--t--+--il---'f

il
::I--Ir-+-t--Ir-+-t--I
~B
r-+-+-t--+-+-+-01

5
O'---'---'--L.-L........--l~
0102030405060
TIME (pa)

50

Iii

B

0.2

I-

o

60

10

20

30

40

50

60

TIME (pa)

Peak Output Current (VSTBY)
100

I-+-+-if-+-+-+-f

t--I-+--+-+-+---iH

'-+-+_+-+-+_+-01

i!l-100
-150
~i" 20

150
100
50

i ;-100

IY

l!!
.. iii 0 r
lI!o-;:;
ti ~ ~ -50 1--+--+-+--1--+-+--1

g

60

40

Line Transient Response
(VSTBY)

-

20 30

20

INPUT VOLTAGe IV)

:I

o

-40 -20

INPUT VOLTAGE IV)

lOUT =500 mA

IA

-1

-40 -20

Line Transient Response
(VOUT)
20

~

-2

g

~

1.5

....
II!
::>

C

60

co

20

iI':i

0-

o

.......
::>
0-

~

I

co 0.5

I

o

10

15

20

INPUT VOL1AGE IV)

25

30

40

o

•

i""""
~

o-

1.0

~
::>

/

80

S-

V

~

II
o

10

20

30

40

50

80

INPUT VOLTAGE IV)
TUH/5232-3

3-139

U)

~
N
::::i

r---------------------------------------------------------------------------------,
Typical Performance Characteristics

....

120
110

Quiescent Current (VOUT)
5

S10PEN
VuUTOFf

I

-

I

i!!! :au

,"

20
10

o'!""'"
o

"aoo

100 200

o

4011 500 600 700 800

o

61 OPEN
VuUT OfF

1

I

=

_ _ I"':=500~

I:

15

20

lOUT =250 lIlA
..... -4I~=I&O~

o

-40

25

Quiescent Current
lOUT = 7111 mA'=

-

Iii

Quiescent Current (VSTBY)
51 OPEN

8

f=

YoUT OFF

I
,I

lQO

~, 80

Isr=t~ ~

lOUT =
_IlIA

DonA

40
8CI
120 1&0
, ',JUNCTION TEMPERATURE ('C)

Ripple Rejection
VsTIY ""...

'"

...:!!. '.'70 z

~

10

...~ 50 IE

~

40

1

au10

80

VQUT
IoUT=&OOmA
~=10,.F ;-

I-

"-

"-

lk '
100
FREOUENCY (Hz)

-

Ripple Rejection (VSTBY)
10

I,

,

~

I.
i

30
10k

OutP/It Impe,!fance

o

150 380 450 &00
OUTPUT CURRENT (mA)

750

Reset on Startl.!P

10

8

§

Rl=100
\

I....

10=120 Hz ,

7,

,

80
50

40

3D

,

°

5
10
15
20
OUTPUT CURRENT (mA)

25

Maximum Power
Dissipation (To-220)
22
20
18
16

r-~~=zlJk

~

11'''j01- >--

20 30 40 50 &0
INPUT VOLTAGE (V)

1o=120"z

IlTIy=10 mA
C3=10,.F

l-

°-20 -10 ° 10

-20 -10 0 10 20 30 40 50 &0
INPUT VlIIJAIIE (V)

Ripple Rejection (VOUT)

10-

~

f-t-

40
10 120 1&0
JUNCTION TEMPERATURE ('C)

9

Ism .10mA

i-120

~

I:

11

-40

INFilITE HEAT SINK

"
12

II

~
co

/

IlTIy=10mA

&0

lOUT =

o

E,

10',

110

e--- lsJY=10 ImA-

1

10

l40

IITIY=O mA

I

V'

Quiescent Current (VOUT)
80
70

STANDlY ~UTPUT CURRENT (mA)

Quiescent Current (VSTBY)
4

~

,5

,VouT-,OUTPUT CURRENT (IlIA)

co

/

I

' .... 80
ii! 70
~ 80

ill

,Qulellcent C,ur...nt (VSTBY)

•

181 ,=:10mA

11:

(Contim.led)

0.1

,/
0.81
10

100
1k
FREOUENCY (Hz)

10k

o

1/

"

1.1
01234,5678
INPUT VOLJAIIE (V)

10
8

.....

r-:,
o
o

1O'C WHEAT SINK

NO ~EAT JINK

....

10 20' 3D '40 50' 60 70 80 90 100

AllBIEHT TEIIPWTURE (OC)
TL/H/5232-4

3-140

Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.
Long Term Stability: Output voltage stability under accelerated life-test conditions after 1000 hours with maximum
rated voltage and junction temperature.

Typical Performance
Characteristics (Continued)
Output Capacitor ESR
(Standby Output, Pin 5)

g

Output Noise Voltage: The rms AC voltage at the output,
with constant load and no input ripple, measured over a
specified frequency range.

100

!j
z
;!

Quiescent Current: The part of the positive input current
that does not contribute to the positive load current. The
regulator ground lead current.

'"~

Ripple Rejection: The ratio of the peak-to-peak input ripple
voltage to the peak-to-peak output ripple voltage.
Temperature Stability of VO: The percentage change in
output voltage for a thermal variation from room temperature to either temperature extreme.

fa
~

'"'"en

§
~

:::>

8'

Application Hints
2

"

6

8
OUTPUT CURRENT (rnA)

10

EXTERNAL CAPACITORS
The LM2935 output capaCitors are required for stability.
Without them, the regulator outputs will oscillate, sometimes
by many volts. Though the 10p.F shown are the minimum
recommended values, actual size and type may vary depending upon the application load and temperature range.
CapaCitor effective series resistance (ESR) also factors in
the Ie stability. Since ESR varies from one brand to the
next, some bench work may be required to determine the
minimum capaCitor value to use in production. Worst-case is
usually determined at the minimum ambient temperature
and maximum load expected.

TL/H/5232-9

Output CapaCitor ESR
(Main Output, Pin 2)

= lO!'F

CooT

~

~0 ~ ' / / /
' / / / '//~
[:::,
STABLE
REGION
~
~
'//,

K//.
~

//, //,

//.

/j

Output capacitors can be increased in size to any desired
value above the minimum. One possible purpose of this
would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system.

0.1

:::>

8'

0.01

o

100

200

300

400

500

CapaCitors must also be rated at all ambient temperatures
expected in the system. Many aluminum type electrolytics
will freeze at'temperatures less than - 30·C, reducing their
effective capacitance to zero. To maintain regulator stability
down to -40·C, capacitors rated at that temperature (such
as tantalums) must be used.

OUTPUT CURRENT (rnA)
TLlH/5232-10

Definition of Terms
Dropout Voltage: The input-output voltage differential at
which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has
dropped 100 mV from the nominal value obtained at 14V
input, dropout voltage is dependent upon load current and
junction temperature.
Input Voltage: The DC voltage applied to the input terminals with respect to ground.

No capacitor must be attached to the ON/OFF and ERROR
FLAG pin. Due to the internal circuits of the IC, oscillation on
this pin could result.
STANDBY OUTPUT
The LM2935 differs from most fixed voltage regulators in
that it is equipped with two regulator outputs instead of one.
The additional output is intended for use in systems requiring standby memory circuits. While the high current regulator output can be controlled with the ON/OFF pin described
below, the standby output remains on under all conditions
as long as sufficient input voltage is applied to the IC. Thus,
memory and other circuits powered by this output remain
unaffected by positive line transients, thermal shutdown,
etc.

Input-output Differential: The voltage difference between
the unregulated input voltage and the regulated output voltage for which the regulator will operate.
Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the averagb chip temperature is not significantlyaffected.

The standby regulator circuit is designed so that the quiescent current to the Ie is very low «3 mAl when the other
regulator output is off.

3-141

•

Application ijints (Coniin\ledl.

'
In applications, vVhere the standby output 'is not need~d, it
mily be disabled by conflecting a resistor from the 'standby
output to the supply voltage. This eliminates the n~4i!d ,for a
more expensive capacitor on the output to prevent unwanted oscillations. The value of the resistor depehds upon the
minimum input voltage expected for a given system, Since
the standby output is shunted with an internal 5.7V zener
(Figure 3), the current through the' external resistor should
be sufficient to bias R2 and R3 up' to this point. Approximately 60 p,A will suffice, resulting in a 10k external resistor
for most appli9ations (Fl{lure 4).

ON/OFF AND ERROR FLAG PIN
This pin has the ability to serve a dual purpose if
desired. When controlled in the manner shown in Figure 1
(common in automotive systems whereS1 is the ignition
switch), the pin also serves as an output flag that is active
low whenever a fault bondition is detected with the high
current regulated output. In other words, under normal
operating conditions, the output voltage of this pin is high
(5V). This is set by an internal clamp. ·If· the high current
output becomes unregulated for any reason (line transients,
short circuit, thermal shutdown, low input voltage, etc.) the
pin switches to the active low state, and is capable of sinking several milliamps. This output signal can be used to initiate any reset or start-up procedure that may be required of
the s y s t e m . '
.

RD

101c

The ON/OFF pin can also be driven directly from open collector logic circuits. The only requirement is that the 20k
pull-up resistor remain in place (Figure 5). This will not affect
the logic gate since the voltage on this pin is limited by the
internal clamp in the LM2935 to 5V.

STANDBY
OUTPUT
LMH35

I

..1.
1'C3

LM2935

I

-!

CMOS MM74C04

OR EQUIVALENT

TLlH/5232-6

DElAYED
RESET

FIGURE 4. Disabling Standby Output to Eliminate C3

OUT

HIGH CURRENT OUTPUT
Unlike the standby regulated output, which must remain on
whenever possible, the high current regulated output is fault
protected against overvoltage and also incorporates thermal shutdown. If the input voltage rises above approximately 30V (e.g., load dUmP), this output will automatically shutdown. This protects the internal circuitry and enables the IC
to survive higher voltage transients than would otherwise be
expected. Thermal shutdown is effective against die overheating since the high current .output is the dominant source
of power dissipation in the IC.

TL/H/5232-11

FIGURE 6_ Reset Pulse on Power-Up
(with approximately 300 ms delay)

Rl
20k

LM2935

DM7405
TLlH/5232-7

FIGURE 5. Controlllng"ON/OFF Terminal with
a Typical Open Collector Logic Gate

3-142

o::;'

()

$WITCH/RESET

4

C

::;:

"'"

w
~

CD

3

!(;'
P17

•

~
t;

[PIa

v,"'
R33

1311
STANDBY

R3

H4

131

N28

GNU
TL/H/5232-5

FIGURE 3

S£6~W'

iii

~

:l

t!lNational Semiconductor

LM2936 Ultra-Low Quiescent Current 5V Regulator
General Description

Features

The LM2936 ultra-low quiescent current regulator features
low dropout voltage and low current in the standby mode.
With less than 15 IJA quiescent current at a 100 IJA load,
the LM2936 is ideally suited for automotive and other battery operated systems. The LM2936 retains all of the features that are common to low dropout regulators including a
low dropout PNP pass device, shorl circuit protection, reverse battery protection, and thermal shutdown. The
LM2936 has a 40V operating voltage limit, -40"C to
+125'C operating temperature range, and ±3% output
voltage tolerance over the entire output current, input voltage, and temperature range. The LM2936 is available in
both a TO-92 package and an S-pin surface mount package
with a fixed 5V output.

• Ultra low quiescent current (10 :s: 15 /LA for
10 :s: 100 /LA)
• Fixed 5V, 50 mA output
• Output tolerance ± 3% over line, load, and temperature
• Dropout voltage typically 200 mV @ 10 = 50 mA
• Reverse battery protection
• - 50V reverse transient protection
• Internal short circuit current limit
• Internal thermal shutdown protection
• 40V operating voltage limit

Typical Application
• Required if regulator is located more than 2" from power supply filter
c,apacHor,
.. Required for stability, Must be rated for 10 "F minimum over intended
operating temperature range, Effective series resistance (ESR) is critical,
see curve. Locate capacHor as close as possible to the regulator output and
ground pins, CapacHence may be increased without bound.

Input- -

V,N

LM2936

Vol-I~'-Output

TUH/9759-1

Connection Diagrams
To-92 PlastiC Package (Z)

8-PlnSO (M)
IN

GND

GND

a

TUH/9759-2

Bottom View

OUT

Order Number LM2936Z-5_0
See NS Package Number Z03A

GND

GND

NC

NC

TL/H/9759-6

Top View
Order Number LM2936M-5_0
See NS Package Number M08A

3-144

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
+60V, -50V
Input Voltage (Survival)
ESD Susceptability (Note 2)
1900V
Power Dissipation (Note 3)
Internally limited
Junction Temperature (TJmaxl
150"C

Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

-65·C to + 150·C
260"C

Operating Ratings
Operating Temperature Range
Maximum Input Voltage (Operational)

-40·C to + 125·C
40V

Electrical Characteristics
VIN = 14V, 10 = 10 rnA, TJ = 25·C, unless otherwise specified. Boldface limits apply over entire operating temperature range
Parameter
Output Voltage

Line Regulation
Load Regulation

5.5V ~ VIN ~ 26V,
10 ~ 50 rnA (Note 6)

Long Term Stability
Ripple Rejection
Dropout Voltage

S.1S

Vmax

VIN

~

16V

5

10

6V

~

VIN

~

40V, 10 = 1 rnA

10

30

10

30

10

30

~

~

10

10
~

~

5 rnA

50 rnA

10 = 30 mAdc and 10 mArms,
~

~

450

mVmax
mVmax
mO

9

15

p.Amax

24V

0.20

0.50

mAmax

10 = 50 rnA, 13V ~ VIN ~ 24V
10 Hz-100 kHz

1.5

2.5

mAmax

500

10 = 100 p.A, 8V
10 = 10mA,8V

Output Noise Voltage

Vmin
V

~

100 p.A

Units

4.8S
5

f = 1000Hz

Quiescent Current

Tested
Umit
(Note 5)

9V

5 rnA
Output Impedance

Typical
(Note 4)

Conditions

~

VIN
VIN

~

24V

p.V,ms
mV/1000 Hr

20
V'ipple = 1 Vrms, fripple = 120 Hz
10 = 100 p.A

60

40

0.05

0.10

dBmin
Vmax

10 = 50 rnA

0.20

0.40

Vmax

-15

Vmin

-80

-50

Vmin

-0.1

-600

p.Amax

~

Reverse Polarity
DC Input Voltage

RL = 5000, Vo

Reverse Polarity
Transient Input Voltage

RL = 5000, T = 1 ms

Output Leakage with
Reverse Polarity Input

VIN = -15V, RL = 5000

Maximum Line Transient

RL = 5000, Vo

Short Circuit
Current

VO= OV

~

-0.3V

5.5V, T =40 ms
120

60

Vmin

250

mAmax

65

mAmin

Note 1: Absolute Maximum Ratings indicate lim"s beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specmed operating ratings.
Note 2: Human body model, tOO pF discharge through a 1.5 kll resistor.
Note 3: The maximum power dissipation is a function of TJmax. 9JA. and TA' The maximum allowable power dissipation at any ambient temperature is
Po = (TJrnax - TAl/ElJA. If this dissipation is exceeded, the die temperature will rise above 150'C and the LM2936 will go into thermal shutdown. For the
LM2936Z, the iunctioMo·arnbient thermal resistance (ElJAl is 195'C/W. For the LM2936M, 8ja is 160'C/W.

Nola 4: Typicals are at 25'C (unless otherwise specmed) and represent the most likely parametric norm.
Note 5: Teslad limits are guaranteed to National's AOQL (Average Outgoing Quality Level) and 100% tested.
Note 6: To ensure constant junction temperature, pulse testing is used.

3-145

to

!

r---------------------------------------------------------------------------------,
Typical Performance Characteristics

:i

Maximum Power
Dissipation (To-92)

o.s

1.0

Dropout Voltage

Dropout Voltage

o.s

0,9

TJ='isoc

0.8

0.7
0.8

u.s
0.4

I-

Q.3

~

0.2
0.1
0.0
-40

120

40

50

20
J=25C1t

150

1"'" ----

I I

I-"-

0.

o

o

10

20

;m

40

Quiescent Current
VIN =14V

VIM = 14V

r-- TJ =25OC

1o=100)'A

/

[,\10= 100)'A
10

1
110=0)'A

I I

-10
-20 -10 0

2

10 20 30 40 50 60

o

-50

INPUT VOLTAGE (V)

I

I

i
CI

1.8

3.0

1.6

2.5

1.4

I

1,5

I

o
o

V'

20

30

40

50,

OUTPin" CURRENT(mA)

Output Capacitor ESR
100 r.;---:="""T--r-""T""--=~

I

IM=14

-

10

1o~501mA

1.2
0.8
0.6

I

o.s
o

10 =110 mA

10
INPUT VOLTAGE (V)

0.4

1o=10mA

0.2

I

-u.s
-10

150

./

1.0

1o=50mA

1.0

-2D

100

Quiescent Current
2.0

TJ =25OC

2.0

50

JUNCIlON TEMPERATURE(OC)

Quiescent Current
4.D
3.5

50

OUTPUT CURRENT(mA)

Quiescent Current

18
16

14
12
10

, llo=lmA
20

100

Q.3

JUNCIlON TEMPERATURE(OC)

Quiescent Current

I I
1\ I I

--

IOUT=10mA

50

AMBIENT TEMPERATURE(OC)

60

-

IouT:!O....

;m

o
-!iO

0.001
50

100

JUNC110N TEMPERATURE (OC)

150

L....J-.!....J.....J....J.....J.....j....J......l....J

o

10

20

50

OUTPUT CURRENT(mA)
TL/H/9759-3

3·146

~------------------------------------------------------------------------------------,

ri:

Typical Performance Characteristics (Continued)

N

CD

Co)
Q)

Peak Output Current

Peak Output Current

2SO

250
TJ =25"C

!

200

I

- -

ISO

5

.-

100

5
'"
~

~

I

so
o

o

f

<'
.s

ISO

I:

100

'"'"
~

!i~~:;C

200

I
5

Current Limit

V.. = 14V

,-

)

/'

t--

L

o
o

o
10

20

IS

1
1

so

25

-SO

INPUT VOLTAGE (V)

100

SO

150

SO

JUNCllON TEMPERATURE ("C)

100

150

200

250

OUTPUT CURRENT (rnA)

Output at
Line Transient Response
~

Voltage Extremes
12

0.D6

Cour= 10J.'f
~Eo.G4 10=IOmA
f~ ~ 0Jl2 V.. = 14V
"'~ 0

10

lD

,

-().()4

~

z

§'"

~~

'4

~

II

D.4

Q2

0.8

D.6

lD

1.2

Load Transient Response

S

"'~
a!Z

...i~

a

20

30

~

~

40
30

40

50

60

1

10

40
30
20
10
0

1
rJ

100

lk

10k lOOk

1M

FREQUENCY (Hz)

Output Impedance
10.0

,1/

b-!

\

-o.D6

l'

/

\

-().()4

10

1e=IOmA
TJ =25"C

I

1\

60

Low Voltage Behavior
5D

I

50

INPUT VOLTAGE (V)

D.06 Cour=IOJ.'F

~E Q.04
!;i! D.02

VIN =14V,

1a=IOmA
70 Cour=IOJ.'F

20
-10 0

1.4

TIME (ms)

0
~~
5-oJl2

~

-2
0.0

~

iii

II

~£000.06
17

T=25'C

II

§-oJl2

~~

Ripple Rejection
80

RL =5OOA

I

V'N= 14V,
10=30mA
Cour=IOp

lL

/

,

n

I'-'
ID
10

20

30

40

50

60

1.0W3IIo4D5D6.0

T1ME{j.s)

INPUT VOLTAGE (V)

O. I
1

10

100

Ik

10k lOOk

1M

FREQUENCY (Hz)

TLlH/9759-4

Applications Information
Unlike other PNP low dropout regulators, the LM2936 remains fully operational to 40V. Owing to power dissipation
characteristics of the TO-92 package, full output current
cannot be guaranteed for all combinations of .ambient temperature and input voltage. As an example, consider an
LM2936 operating at 2SoC ambient. Using the formula for
maximum allowable power dissipation given in Note 3, we
find that PO max = 641 mW at 2SoC. Including the small
contribution of the quiescent current to total power dissipation the maximum input voltage (while still delivering 50 mA
output current) is 17.3V. The device will go into thermal
shutdown if it attempts to deliver full outpu1 current with an
input voltage of more than 17.3V. Similarly, at 40V input and
25°C ambient the LM2936 can deliver 18 mA maximum.

Under conditions of higher ambient temperatures, the voltage and current calculated in the previous examples will
drop. For instance, at the maximum ambient of 12SoC the
LM2936 can only dissipate 128 mW, limiting the input voltage to 7.34V for a SO mA load, or 3.S mA output current for
a 40V input.
While the LM2936 maintains regulation to 60V, it will not
withstand a short circuit above 40V because of safe operating area limitations in the internal PNP pass device. Above
60V the LM2936 will break down with catastrophic effects
on the regulator and possibly the load as well. Do not use
this device in a design where the input operating voltage
may exceed 40V, or where transients are likely to exceed
60V.

3-147

•

LM2936
In
J:l

- rO~

4
i"

049

k

~

D4

- ~

~

C

•t 052

t

O~

......

~ ~.

~!~

~

~

3

~Q.48

.....

O~

~

-I

O}

~I5

)06

t.::.

•

053t

~

·08

~

035
Ct
038

039

~

~"""032

i"
3

~43

028

0!J..t

C:;"

c
ii1

037

O!!l

07~jRI3

017

I»

co

RI5

:t~

~

055 of

036

~

R3

D3

':3'

CD

044

r02

()

"

R5

R6



V-

0.4
0.3
0.2
0.1

oV

......

/'

~.

i'"

~

~

~

0.8
0.7

......

0.4

r-"

0.3

0.1

100

200

300

400

g

5.00

~

4.98

"<

-S

15

!;i

~

.~

I- -

SOOmA

I-

250 mA

§

r-

5~A
o

o

-40

-

~

5

80

"",+-+-+-+---j-+-+-+-I

I-+-+-+-+---j-+-+-+-I
1-+-+-+++-+-+--1--1

4.94
4.92

40

80

40

120

Quiescent Current vs
Output Current
10

VOUT = 5V -

80

TA

il

50

~
§

40

VJN

_

"<

-S
!;i

e-

20 !

I

Y

I,

= 14V

Your = SV
TJ = 25°C

8

7

V

~
il

0.5A

".

.... 1---

~

~

D.25A

30

I

/

§

0.05A

o
o

120

= 25°C

70
60

V

o
10

15

20

25. 30

o

35

100

INPUT VOlTAGE (V)

TEMPERATURE (OC)

Line Transient Response .

120

80

TEMPERATURE (OC)

90

10

40

1--6'+-"'I''''t'''9'''''+-"""d,--l

i!: ~96t-t--I-+-l--t-+-t~--I

100

10

I-+-+-+-+---j-+-+-+-I
I-+-+-+-+---j-+-+-+-I

Quiescent Current vs
Input Voltage

20

~
§

5.02

-+-+---j---j+-+--1

= loon

TEMPERATURE (Oc)

Quiescent Current vs
Temperature

-S
~

5.04

~

~

0.25A

0.05A

-~

500

E

t-""

OUTPUT CURRENT (mA)

"<

.....

0.2 I.--'

0.0

o

I.--'

"..

0.5

I\.

t-t--c+-+-+-+--I--I--I--I

5.06

0.5A

0.6

'-'-'T"--r-r--'-'-'-'T":i"1

5.10
5.08

I
I
I

0.9

TJ = 25°C

Output Voltage vs
.' Temperature

200

300

400'

500

OUTPUT CURRENT (mA)

Load Transient Response

Ripple Rejection

40

Your = 5V
'oUT = SOmA
T,. = 25°C

1\

l

-10

,

"-

0

10

20

30

I-I-I-- .

50

Vmn '" 5V

t-+-+-t-+-+-t--I

-1

60

TIME (1'.)

2!
~

1.0

VIN - 14V
CaUT = 10 ~F TANT.
loUT = 25mA
Your = 5V

20

~
z

~

t-tI-HlIIII-t+HIIJ-t+I. .-j,ljl1IIH

~

O. 1 t-tlnllIII-t+ltII,Hlllllf-+tlI1IIIII-t

is

i(

~

0.01

1

2

3

4

t-ttttffiHtttlH-tttlIII-I-HtIHlt-Hiiillll
lk

10k

FREQUENCY (Hz)

t-tttttlH-tttt1Rt-+

40

I-+fHlIIIl-tl-Hllif-t
10

100

~

12
10
8

lOOk

1M

1\

lOOk

1M

9 JA

=320C/~

N

I'kl'-.

10 o C/W HEAT SINK

.......

9JA=37'C/

\

r-.....
~

.......

~

-40

10k

Maximum Power Dissipation
(TO-263) (See Note 2)

16
14

lk

FREQUENCY (Hz)

NO HEAT SINK

.......

\

o
100

50

INFINITE HEAT SINK

18

2
10

1=tIl1=I:tlll::j:

Maximum Power
Dissipation (TO·220)
22

I

0

60

TINE (1001")'

Output Impedance
10

=

70

-50

40

VIM = IOV
CaUT = to pf
lOUT
50 mA

o
40

80

120

AMBIENT TEMPERATURE (OC)

o

:--;['0..

-~~ ~::::;I ~ ~ nrc/;:: ;:::~
I TJA

'1',

10 20 30 40 50 60 70 80 90100
AMBIENT TEMPERATURE (Oc)

TL/H/1128D-3

3-152

Typical Performance Characteristics
Low Voltage Behavior

=

louT
SOD rnA
TJ = 25°C

/

Your = 5V

Low Voltage Behavior
14

V

ioUT

12

:€

/

= 500 mA

TJ = 25°C

It,1

L

Your

o
o

10

Output at Voltage
Extremes

Output at Voltage
Extremes

=

20

11

loon

I

0

~

Your

20

loon

12

I

6

9

12

15

18

Output Capacitor ESR

S

100
COUT = 10 Jo'F'

Your

0

z

= SV

~

~

11
=

Your

/
INPUT VOLTAGE (V)

rtl

12

Your = f2V

/
o
o

14

Your = 15V

i

I
I
10

=

~

Your = 5V

J
-2
-30 -20 -10

<':.

1
11.
=BV

I

1\

16

voui= 10V

fi II

S

J

A

12

§

INPUT VOLT AGE (V)

1\

= 8V

I

INPUT VOLTAGE (V)

10

~~

VOUT =,~V

lOUT = 500 rnA
TJ '" 25°C

15

:€

/

~

12

= tOV

A

0

o

Your

-

Low Voltage Behavior
18

I

I \I

~~

)

I

10

~
~
~

o

(Continued)

i!l

~

12V

f

z
~

;;
5

30

-4
-30 -20 -10

-40

INPUT VOLTAGE (V)

8
0

10

20

30

-40

100

INPUT VOLTAGE (V)

200

300

400

500

OUTPUT CURRENT (mA)

Peak Output Current

3

i I.0l-+-+-+-+++-+-+--l
~

g~

0.5

I-+-+-+-+++-+-+--l

TEMPERATURE (Oc)

TL/H/11280-4

Typical Application
UNREGULATED _ ....-..;;.~
INPUT

~~~_ REGULATED

..

OUTPUT

TL/H/I1280-1

'Required if the regulator is located more than 3 inches from the power supply filter capacitors.
"Required for stability. Cou1 must be at least 10 ,.F (over the full expected operating temperature range) and located as close as possible to the regulator. The
equivalent series resistance, ESR, of this capacHor may be as high as 30.

3-153

•

g

;1fI
National
~
n

Semiconductor

C;

~ LM2940/LM2940C 1A Low Dropout Regulator

:5

General Description
The LM2940/LM2940C positive voltage regulator features'
the ability to source 1A of output current with a dropout
voltage of typically 0.5V and a maximum of 1V over the
entire temperature range. Furthermore, a quiescent current
reduction circuit has been included which reduces the
ground current when the differential between the input voltage and the output voltage exceeds approximately sV. The
quiescent current with 1A of output current and an input-output differential of 5V is therefore only SO mA. Higher quiescent currents only exist when the regulator is in the dropout
mode 

!i;

......

~

i'l

f-"
f-"

~

~

500 rnA

~

10mA

~

-40

40

80

TEMPERATURE (Oc)

5.00

U8
4.96

--

4.94
U2

120

-40

160

40

..
i
.!-

r\.

100

~

r'00mA

60

50

160

1A

I
I
I

40

V,N = 1.4V
Vo = 5V
TJ = 25 0 e

30

15

20

~

10

1:]

r500mA

40

120

QuIescent Current

160

80

80

TEMPERATURE (Oe)

180

120

-

4.90
80

200

140

... f-"

...

_I"""

r-r-7'

t;;~-

~f-"

20

I

o

§

5.02

QuIescent Current

..

I
I

~

z

5.04

TEWPERATURE (OC)

~IN =ro+5V

40

=>

.... f-"

I
-40

QuIescent Current
va Temperature

..

~

100 rnA

OUTPUT CURRENT (mA)

50

i
I

0.2

1000

Sl

-I--'
500~

5.06

~

I A......

o
.400

~

0.7

0.1
200

Output Voltage
va Temperature

Dropout Voltage
va Temperature

Dropout Voltage

o
120

160

o

10

15

20

25

INPUT VOLTAGE (v)

30

35

o
o

0.2

0 ..4

0.6

0.8

1.0

LOAD CURRENT (A)

TL/H/8822-9

•
3-159

Typical Performance Characteristics
Line Transient Response
~>

.~.!.

g~

~~

§~

30
·20
10
0
-10
-20
-30

Load Transient Response

,,j:!:'::'
~~

~~
~>

II

~w

g"

3:

,,~~

3V

~g;

B

OV

-10 0

10

20

30

40

50

(Continued)

0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
1.0

_
r--i- _
f-Ir--i- _
f-I- -

VIN = UV
C,lUT=22I'f
TJ =25 0 C
VO =5V.

t~f=

Ripple Rejllctlon
95

V,N = 10V I••
COUT = 22,uf'
85 IO=10mA
Yo =5V
75

.,
3

~

-I""'

!;i

65

iii

55

.,~

45

0.5

o

35
-10

60

10

30

20

40

10

Maximum Power
Dissipation (TO-220)

Output Impedance
10.00

S

Vo

~

1.00

~
3!

0.50

~

§

22
20

V,N = 10V '"_
5.00 CoUT = 221'f
IO=50mA
.2.00

~

=5V

z

~

0.20

~

0.10

~

22
20

INfiNITE HEAT SINK

~

18
16

14

~

14

~

"

~

0.05

1OoC/ W HEAT SINK

~

e;

-N

I

lk

10k lOOk

1M

Maximum Power
Dissipation (TO-3)

18
16
12
10

100

fREQUENCY (Hz)

TIME (1'.)

INfiNITE HEAT SINK

I'\.

12
10

....

8

"'t--.I

~

1'1-..

10 o C/W HEAT SINK

I

,.... ....

NO HEAT SINK

0.02

r-

o

0.0 1
10

100

1k·

10k lOOk

o . 10

1M

fREQUENCY (Hz)

o

o

20 30 40 50 60 70 80 90100

NO HEAT SINK
10 20 30 40 50 60 70 80 90100

AMBIENT TEMPERATURE (OC/W)

AMBIENT TEMPERATURE (OC)

TL/H/B822-4

Maximum Power Dissipation
(TO-263) (See Note 3)

I

I

0JA. = 32 0 C/W

N

I

N...N

a JA = 37°C/W

.....

...... ~

~""'" r--~~ ~~fo

=~otiw';;::~
.,. 'i

a '
JA '1'

0102030405060708090100
AMBIENT TEMPERATURE (Oc)

~',

.

3-160

TL/H/8822-10

Typical Performance Characteristics
Low Voltage Behavior

Low Voltage Behavior

5.0

I.
'0 ' IA
TJ = 25°C

2

Vo

4.0

//

= 5V

~

~

0

>

3.0

~
~

2.0

/

1.0

I

~

6

1.0

V

/

12

2

V

'0'
TJ
Vo

IA

I:

5.0

a.o

'0 ' IA _I

12

= 10V

2

12

10

o

o

I

/

/

10

i

a

9

12

15

i

/

16

2

~

10

12

o

o

,.

16
~

~

0

§

10

20

Output at
Voltage Extremes

30

-4
-30 -20 -10

40

16

= 10V

2

15

~

/
V

-5
-30 -20 -10

0

10

40

.0

Voltage Extremes
20

Vo = 12Y

2

12

~

/
/

~

30

20

Output at

I\.1.,Jon

0

20

10

25

~

INPUT VOLTAGE (V)

0

- -

INPUT VOLTAGE (V)

20

i

I
/

~

Voltage Extremes
1\.1. IJon

30

= 9V

12

INPUT VOLTAGE (V)

25

18

I\.1.,Jon
Vo

~

/
/
-4
-30 -20 -10

...0

15

Voltage Extremes

2

Output at

10

12

Output at

12

INPUT VOLTAGE (V)

Vo

I

lL

/

/

INPUT VOLTAGE (V)

1\.1. IJon
Vo • 8V

~
30

18

20

~

20

15

/

Vo = 15V

12

~

20

-2

~

'0 ' IA _I
15 TJ = 25°C

2
!:;

Voltage Extremes

I~on

12

Low Voltage Behavior

~

Output at

10

a

INPUT VOLTAGE (V)

/

Voltage Extremes

0

(

o

INPUT VOLTAGE (V)

I

20

/

/

o
o

18

Vo' 5V

2

Vo • 12V

Output at

-30 -20 -10

o

,.

18
'0 ' IA
TJ :;; 25°C

/

INPUT VOLTAGE (V)

1\.1.

12

/

Low Voltage Behavior

~

!:;

!

/

~

/

,.

15 TJ = 25°C

~

12

~

/

,

IA

= 25°C

Vo = 9V

INPUT VOLTAGE (V)

Low Voltage Behavior

~

~~

/

o
o

18

Vo

2

~

INPUT VOLTAGE (V)

2

15 TJ

8V

10

~

'.0

'0'

= 25°C

!;

3.0

Low Voltage Behavior
18

~

0

2.0

(Continued)

-4
-30 -20 -10

0

1\.1. IJon
Vo = 15V

15

I

i
10

20

INPUT VOLTAGE (V)

30

40

•

I

10

/
-5
-30 -20 -10

0

10

20

30

40

INPUT VOLTAGE (V)
TL/H/8822-5

3-161

Typical Performance Characteristics (Continued)
Peak Output Current

Output Capacitor ESR

S

100~--~--~---r--~---.

3.0

= 221'F
I-----+----l----l Vo = 5V
<:OUT

101-----+----l----+--~--~

.:5
....
~

...... VIN = 14V

2.0

i'"

'"

'"
i:l
....
~

1.0

5
o

0.01'----'-----'----...1---.....1...----'
o
200
400
600
800 1000

-40

o

40

80

120

160

TEMPERATURE (OC)

OUTPUT CURRENT (rnA)
TL/H/~822-6

TL/H/8822-8

Equivalent Schematic Diagram

TL/H/8822-1

3-162

,-----------------------------------------------------------------------------'r

i:

Connection Diagrams

~

U)
~

o

TO-3 Metal Can Package (K)

(TO-220) Plastic Package

r
i:
~

U)

~

o
TLlH/8822-2

Front View
Order Number LM2940CT-5.0, LM2940CT-9.0,
LM2940CT-12, LM2940CT-15, LM2940T-5.0,
LM2940T-8.0, LM2940T-9.0,
LM2940T-10 or LM2940T-12
See NS Package Number T03B

TLlH/8822-7

a

Bottom View
Order Number LM2940K-5.0/883,
LM2940K-8.0/883, LM2940K-12/883, LM2940K-15/883
See NS Package Number K02A

(TO-263) Surface-Mount Package

TAB IS
GND

OUTPUT
GND
INPUT
TLlH/8822-11

Top View

TLlH/8822-12

Side View
Order Number LM2940CS-5.0, LM2940C5-9.0, LM2940CS-12,
Lr.II2940CS-15, LM29405-5.0, LM2940S-8.0,
LM294OS-9.0, LM2940S-10 or LM29405-12
See NS Package Number TS3B

3-163

IfI

Nat ion a I S e m i. con due tor

LP29501 A-XX and LP29511 A-XX Series
of Adjustable Micropower Voltage Regulators
General Description
The LP2950 and LP2951 are i'nicropower voltage regulators
with very low quiescent current (75 p.A typ.) ahd very low
dropout voltage (typ. 40mV at light loads and 380 mV at
100 rnA). They are ideally suited for use in battery-powered
systems. Furthermore, the quiescent current of the
LP2950/LP2951 increases only slightly in dropout, prolonging battery life.
The LP2950-5.0 in the popular 3-pin TO-92 package is pincompatible with olde~ 5V regulators. The 8-lead LP2951 is
available in plastic, ceramic dual-in-line, or metal can packages and offers additional system functions.
One such feature is an error flag output which warns of a
low output voltage, often due to falling batteries on the input. It may be used for a power-on reset. A second feature
is the logic-compatible shutdown input which enables the
regulator to be switched on and off. Also, the part may be
pin-strapped for a 5V, 3V, or 3.3V output (depending on the
version), or programmed from 1.24V to 29V with an· external
pair of resistors.
Careful design of the LP2950/LP2951 has minimized all
contributions to the error budget. This includes a tight initial

tolerance (.5% typ.); extremely good load and line regulation (.05% typ.) and a very low output voltage temperature
coefficient, making the part useful as ·a low-power voltage
reference.

Features
•
•
•
•
•
•
•
•
•
•

5V, 3V, and 3.3V versions available
High a~uracy output voltage
Guaranteed 100 rnA output current
Extremely low quiescent current
Low dropout voltage
Extremely tight load and line regulation
Very low temperature coefficient
Use as Regulator or Reference
Needs minimum capacitance for stability
Current and Thermal Limiting

LP2951 versions only
• Error flag warns of output dropout
• Log.ic-cOnt~olled electronic shutdown
• Output programma!Jle from 1.24 to 29V

Block Diagram and Typical Applications
LP2951/A-XX

LP29501A-XX

Il

Your
:s 100 mA

SEE APPLICATION
HINTS
SEE APPLICATION
HINTS

1.23V
REFERENCE

...--------------- •.........:
TLlH/8546-25

TUH/8546-1

3-164

Connection Diagrams
T0-92 Plastic Package (Z)

Dual-In-Llne Packages (N, J)
Surface-Mount Package (M)

OUTPUTBINPUT

•

OUTPUT

INPUT

SENSE

GND

TL/H/8546-2

FEEDBACK

SHUTDOWN

Bottom View

GROUND

Order Number LP2950ACZ-3.0, LP2950CZ-3.0,
LP2950ACZ-3.3, LP2950CZ-3.3 LP2950ACZ-5.0
or LP295OCZ-5.0
See NS Package Number Z03A

VTAP

4

ERROR
TLlH/8546-26

Top View
Order Number LP2951CJ, LP2951ACJ, LP2951J,
LP2951J/883 or 5962-3870501MPA
See NS Package Number J08A
Order Number LP2951ACN, LP2951CN, LP2951ACN-3.0,
LP2951CN-3.0, LP2951ACN-3.3 or LP2951CN-3.3
See NS Package Number N08E
Order Number LP2951ACM, LP2951CM,
LP2951ACM-3.0, LP2951CM-3.0,
LP2951ACM-3.3 or LP2951CM-3.3
See NS Package Number M08A

Metal Can Package (H)

Leadless Chip Carrier (E)

INPUT

OUTPUT

INPUT

/

\

•

3

2

1

9

10

11

8

GND

GROUND

TL/H/8546-24
TL/H/8546-19

Top View

Top View

Order Number LP2951E/883 or 5962-3870501M2A
See NS Package Number E20A

Order Number LP2951 H/883 or
5962-3870501MGA
See NS Package Number H08C

•
3-165

><
~
.,..
~

Ordering Information

~

......
C)

~

('C)

3.3V

TO·92(Z)

LP2950ACZ·3.0
LP2950CA·3.0

LP2950ACZ·3.3
LP2950CZ·3.3

LP2950ACZ·5.0
LP2950CZ·5.0

-40 < TJ < 125

N (N·08E)

LP2951 ACN·3.0
LP2951CN·3.0

LP2951ACN·3.3
LP2951CN·3.3

LP2951ACN
LP2950CN

-40 < TJ < 125

M (M08A)

LP2951 ACM·3.0
LP2951CM·3.0

LP2951 ACM·3.3
LP2951CM·3.3

LP2951ACM
LP2951CM

,-40 < TJ < 125

LP2951ACJ
LP2951CJ

-40 < TJ < 125

LP2951J
LP2951J/883
5926·3870501MPA

-55

~

~

i

110

.....
~~~

500
400
300
100
50

o
25 50 75 100125150

TEWPERATURE (Oe)

INPUT VOLTAGE (V)

Dropout Voltage
500 r-T""l'TTTmr-rTTmnr-T"TTTTnn

~
t ....

"

~

120

......

=100mA

, 0

Dropout Voltage
600

~

130

IL

o

25 50 75100125150

TEMPERATURE (Oe)

g

100
-75 -50-25 0

V

S
a

TEMPERATURE (oC)

150

3

5V OUTPUT

140

5V OUTPUT

100

~

2

10

z

90

is

,t

-75-50-25 0

10

110

~
~

i

-

4,94

1

o

I
I
I

Quiescent Current
'<
-3

4.96

5V OUTPUT

z

50

~=~- 1--

160

5V OUTPUT

4,98

Quiescent Current

a

15

INPUT VOLTAGE (VOLTS)

5.04

120

~

100

-

1
I

,r,

125

Output Voltage vs.
Temperature of 3
Representative Units

INPUT VOLTAGE (VOLTS)

'<
-3

150

lNPui VOLTAGE (VOLTS)

Input Current

i

175

o

o

LOAD CURRENT (mA)

ia

~=iOkh

200

25
10

~

i

I

5V OUTPUT

225

~
~

0.1

~

'<

250

V OUTPUT

'<

c

Input Current

Dropout Characteristics

lq

-

400

f-I+HttHf-+l+H-HlI--++H1ttlll

300

I-H+++I111--+-++fjjjjj--H-III'I-HlI

200

f-H-jcl+HIl--++l-I+hlil'/4-W1+lHl

.... f-~-f-

-75 -50-25 0

Jfr

25 50 75 100125150

TEWPERATURE (Oe)

10:

~H1lIjjll
100}'A

lmA

10mA

100mA

OUTPUT CURRENT

TL/H/8546-3

3-170

r

Typical Performance Characteristics
LP2951
Minimum Operating Voltage

LP2951
Feedback Bias Current

2.2

~

2.,

~~

\

i

r--- ......

'.9

i,.

I..

r-. .....

'"

1.7
1.6
-75 -50 -25

a

r

II

-10

~

~

-30
-75-50-25

25 50 75 100 125 150

2.0

-

"<

oS

1

1 1 1

J J±
~:rT 1

~

~YlTERESIS

z

~

50k RESISTOR

I--

l/

1.5
1.0

JL
I~

J

~

0.5

lj
0.0

12345678

-2.0 -1.5 -1.0 -0.5

0.1

~

50
mV

~

!;

:=

-50
mV

5

BV
~~

II

z~

-~

6V
4V

0.5 0.6 0.7 0.8 0.9

~

~'"

-100

L

<;. = I},'

50
_

J

'II"

-40

Your

VOUT=15VI+
'00

'00

'00

=5V

~Ii

~A

f-

t--

:E:

16

20

~~

-2
c: -100 0

Output Impedance

Ripple Rejection

,

~

0

iil

0.2

~

0.1

it

0.05

'"

0..02

FREQUENCY (Hz)

1M

.p <;. =, ~F

i'

1

I- <;'=IO},'

IL = 10 rnA
V,. =BV-

VOUT=5V -

100 200 300 400 500 600 700

80


3
z

70

0

60

~

50

iil

40

it

~

'"

30

20
lOOK

800

90

80

0.5

600

Ripple Rejection

90

3
z

400

TIME (~,)

TIME (ms)

10

10K

200

I-

e~
'2

lK

L1J

0

~~

~A

TIME (ms)

CL = 1 J.'F_

=

IL

rnA - I

rnA

1.0

IL 1 rnA
VOUT =5V -

H

<;. ='O}'F

-60

'00

'00

II'

7

~ ~ -20

><

I

f-

>~

a

t

LP2951
Enable Transient

60

50

.....

TIME (~,)

~s:- ~o
5.5 20 ~

~
0-50

0.5

~

CII

Line Transient Response
100
mV

BO

'> 150
.5 100

~

"--"-_..L--'_--'-_.l..---'

Load Transient Response

200

~
~
~

-250

OUTPUT LOW VOLT AGE (V)

250

~
;!!

1"--7'I'-+-+--I---+--j

~'"

0.00.1 0.2 0.3

Load Transient Response

~

-200

TA = -55°C

~

INPUT VOLTAGE (V)

~

1---+""7''''T-7'>If--I---+--j

"U

FEEDBACK VOLTAGE (V)

,.. T) '2~OC

/11

z
iii

lJ~

~
.e

-100

2550 75'00'25150

2.5

50k RESISTOR TO 1
EXTERNAL 5V SUPPLY

1---+--4---bdF--+--j

LP2951
Comparator Sink Current

1VOUI - svl
YI

a

-50

TEMPERATURE (DC)

LP2951
Error Comparator Output

I--

iu~

-20

TEMPERATURE (DC)

~

~

'0

lZ

1.8

'"'iiZ

o

LP2951
Feedback Pin Current

20

2.0

'"z

~

(Continued)

la

•

70

6D
50
40
3D

Iff
FREQUENCY (Hz)

FREQUENCY (Hz)

TLlH/8546-4

3-171

Typical Performance Characteristics

(Continued)

LP29~1 Output Noise

Ripple Rejection
80

LP2951 Divider Resistance

3.5 r-1-nTTTTl,---rnTl"'1rr-rn"TTTTTI
\. = 50 rnA

70

'"
3

~.

60 IL=100mA

z
0

~

iil
l!:

'"

50
40

./
"",'

[\

.= 1 J.'F \

-

Cl

I

30 ------, V'M = 6V
Your = 5V

\

20
10

1f1

10'

10'

I

"-l/

10'

10'

o
If!'

10'

Shutdown Threshold Voltage

~
9

1.4

~

1.2

~
z

1.0

!!!

g
S
ill

"-

">
.5

"- I'..REGULATOR orr
.,...,

.,..

~

REGULATOR ON

~
~

0.8

~

0.6

-75 -50 -25' 0

-

~

LP2951 Maximum
Rated Output 'Current

25 50 75 100 125 150

TE"PERATURE (DC)

\.=100~

ia

i

80 I---t--\j---'~...

1-+-l-\--BM<

0.05

.?<

:i

470

CD

CI'I

VTAP

FB

.....
.....

2N3906

VOUT

r'" I

LP2951
#1

+

ER'Roii
4

><
><

ERROR
fLAG

=,."

GNO

~

10 kll
4.all

R, •

LP2951

NICAO

FB

GNO

220

•
4.7

t - -......~....,."t SO

100

t - - - -..... ,% ENT.I;-"'f
OUTPUT

• Early warning flag on low input voltage

ERROR

• Main output latches off at lower input voltages

LP2951

• Battery backup on auxiliary output

SHUTDOWN 3 SO
INPUT

Operation: Reg. # l's Vou• is programmed one diode drop above 5V. Its error
flag becomes active when Yin s: 5.7V. When Yin drops below 5.3V. the error
flag of Reg. # 2 becomes active and via Ql latches the main output off.
When V'n again exceeds 5.7V Reg. # 1 is back in regulation and the early
warning signal rises. unlatching Reg. # 2 via 03.

Latch Off When Error Flag Occurs
tHigh input lowers Vout to 2.SV

TUH/8546-14

Open Circuit Detector for
4 -+ 20 mA Current Loop
+5y
YOUT

VOUT

FB
RESET

GNO

4

4.7 kll

.4 ----+- 20mA

R,

R2

OUTPUT'

+

I"

IN
4001

VOUT
LP2951

TLlH/8546-12

• HIGH FOR
'L < 3.5 rnA
360

MIN. VOLTAGE'" 4V

3·175

TL/H/8546-15

Typical Applications (Continued)
Regulator with State-ot-Charge Indicator

.39kll

+VIN

RESET

...----j:llJlo-,

ERROR

SENSE

+ VOUT = 5V

VOUT

+
I1JJ.F

LP2951
. 3 SD

+

-=.l..

FB

SV
LEAD-ACID
BATTERY

100kll

< 5.8V"
1%

100kll

< S.OV"
Cl-C4
LP339

1%

100kll

< 6.2V"

TUH/B546-16

'Optional Latch off whe~ drop out occurs. Adjust R3 for C2 Switching when Vin is 6.0V.
"Outputs go low when Vln drops below designated thresholds.

Low Battery Disconnect
For valuesshown, . Regulator shuts down when Vin

< 5.5V and turns on again at 6.0V. Current drain in disconnected mode is '" 150/lA.

6V
SEALED
..=. LEAD-ACID
BATTERY
_
SOURCE
+

.l..

+VIN
MAIH V+
VOUT
LP2951

~ 400 kll'
FOR 5.5V

SENSE

2

MEMORY V+

SD

lJJ.F

'Sets disconnect VoHage

r
+

20ll
+'

,;;. HI-CAD
BACKUP
BATTERY

.l

TL/H/B546-17

"Sets disconnect Hysteresis

3-176

,-----------------------------------------------------------------------------, "U
~

Typical Applications

~

(Continued)

o
.....

System Overtemperature Protection Circuit

~

+VIN

~

"U

10kA
5° PRE-SHUTDOWN FLAG

~AU~X~.~SH~U~rno~W~N+_~3 SD
INPUT

N
CD

en
.....

~

LP2951
VOUT ...1_ _ _ _ _• __________ _
GNO

4
TEMP.
SENSOR

~~

Fa
7

><
><

EXTERNAL CIRCUIT
PROTECTED FROM
OVER TEMPERATURE
(V+ GOES OFF WHEN
TEMP.> 125°)

8.2kA

TLlH/8546-18

lM34 for 125'F Shutdown
lM35 for 125'C Shutdown

Ell

3-177

LP29501 A-XX, LP2951lA.;XX
t/)

IN

n

:::r
CD

3D)

(i"

c

iii"
co

r;;

R27

,I

I.

IvTAP

3

R28

~

al

50kn

13kn

---- DENOTES CONNECTION ON
LP2950 ONLY

___ 1 ,

•

•

•

1 GND
TL1H/8546-23

/JI1National Semiconductor

LM2984 Microprocessor Power Supply System
General Description
The LM2984 positive voltage regulator features three independent and tracking outputs capable of delivering the power for logic circuits, peripheral sensors and standby memory
in a typical microprocessor system. The LM2984 includes
circuitry which monitors both its own high-current output and
also an external !-,P. If any error conditions are sensed in
either, a reset error flag is set and maintained until the malfunction terminates. Since these functions are included in
the same package with the three regulators, a great saving
in board space can be realized in the typical microprocessor
system. The LM2984 also features very low dropout voltages on each of its three regulator outputs (O.BV at the rated output current). Furthermore, the quiescent current can
be reduced to 1 mA in the standby mode.
Designed also for vehicular applications, the LM2984 and
all regulated circuitry are protected from reverse battery installations or 2-battery jumps. Familiar regulator features
such as short circuit and thermal overload protection are

also provided. Fixed outputs of 5V are available in the plastic TO-220 power package.

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Three low dropout tracking regulators
Output current in excess of 500 mA
Fully specified for - 40'C to + 125'C operation
Low quiescent current standby regulator
Microprocessor malfunction RESET flag
Delayed RESET on power-up
Accurate pretrimmed 5V outputs
Reverse battery protection
Overvoltage protection
Reverse transient protection
Short circuit protection
Internal thermal overload protection
ON/OFF switch for high current outputs
P+ Product Enhancement tested

Typical Application Circuit
5V

i:LI,.F

RRST

5V, 500 rnA

II

r-----.. . .I"];
..

----"IO

I-+---t--~ VOUT

J:.+
l"

VaUFF£R

r
1+

10 pF

...1!.10,.F

LM2984

MONITOR OUT 1-+-------1 PPMON
RESET IN

5Y. 100 rnA

1---t-----1

8
-

RESET

PERIPHERAL
SENSORS

ON/OFF INPUT

RT
STANDBY
MEMORY

5V. 5 mA
GoUT must be at least 10 p.F to
maintain stability. May be increased
without bound to maintain regulation

during transients. Locate as close as
possible to the regulator. This capac·

Order Number LM2984T
See NS Package Number TA 11 B

itor must be rated over the same operating temperature range as the
regulator. The equivalent series resistance (ESR) of this capacitor is

critical; see curve.

3-179

TL/H/11252-1

Absolute Maximum Ratings
Internal Power Dissipation
Internally limited
-40"Cto + 125·C
Operating Temperature Range (TN
150·C
Maximum Junction Temperature (Note 1)
-65·Cto + 150"C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
230·C

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage
",
6C')V
Survival Voltage « 100 ms)
Operational Voltage
26V

ESD Susceptability (Note 3)

2000V

Electrical Characteristics
VIN = 14V, lOUT = 5 mA, COUT = 10 ,..F, unless otherWise indicated. aoldface type relers to limits over the entire operating
temperature range, -40·C s: TA s: + 125·C, all other limits are 10rTA = Tj = 25·G(Note6).
Typical

Liniit
(Note 2)

Units

5.00

4.85/4.75
5.15/5.25

Vmin
Vmax

9V

2

25/25

mVmax

7V

5

50/50

mVmax

12

50/50

, mVmax

Parameter

Conditions

VOUT(Pin11)
Output Voltage
Line Regulation

Load Regulation

5 mAS: 10 ;;" 500 rnA
6V s: VIN s: 26V

s: VIN s: 16V
s: VIN s: 26V
5 mA s: lOUT s: 500 rnA

Output Impedance

250 mAde and 10 mArms,
10= 120Hz

24

Quiescent Current

lOUT = 500mA

38

100/100

mAmax

lOUT = 250mA

14

50/50

mAmax

Output Noise Voltage

10 Hz-100 kHz, lOUT = 100 mA

Long Term Stability
Ripple Rejection
Dropout Voltage

100

,..V

20

mV/1000 hr

70

60/50

dBmin

lOUT = 500mA

0.53

0.80/1.1

V max

lOUT = 250mA

0.28

0.50/0.70

Vmax

0.92

0,75/0.80

Amin

32

26/28

Vmin

65

60/80

Vmin

-30

-15/-15

Vmin

-55

-35/-35

Vmin

10 = 120 Hz

Current limit
Maximum Operational
Input Voltage

mO

Continuous DC

s: 6V, ROUT =

s:

Maximum Line Transient

VOUT

Reverse Polarity
Input Voltage DC

VOUT:;;: -0.6V, ROUT = 1000

Reverse Polarity Input
Voltage Transient

T

s:

1000, T

100 ms

100 ms, ROUT = 1000

3·180

Electrical Characteristics (Continued)
VIN = 14V. Ibuf = 5 mAo Cbuf = 10 ""F. unless otherwise indicated. Boldface type refers to limits over the entire operating
temperature range. -40·C :s: T A :s: + 125·C. all other limits are for TA = Tj = 25·C (Note 6).
Parameter

Conditions

Typical

Umit
(Note 2)

Units

5.00

4.85/4.75
5.15/5.25

Vmin
Vmax

Vbuffer (Pin 10)
Output Voltage
Line Regulation

5mA:s: 10:S: 100mA
6V:s: VIN:S: 26V
9V:s: VIN:S: 16V

2

25/25

mV max

7V:S: VIN:S: 26V

5

50/50

mVmax

Load Regulation

5 mA :s: Ibuf :s: 100 mA

15

50/50

mVmax

Output Impedance

50 mAtlc and 10 mAnns.
fo=120Hz

200

Quiescent Current

Ibut = 100 mA

8.0

Output Noise Voltage

10 Hz-100 kHz. lOUT = 100 mA

100

""V

20

mV/1000 hr

Long Term Stability
Ripple Rejection

fo= 120Hz

Dropout Voltage

Ibuf = 100 mA

Current Limit
Maximum Operational
Input Voltage

Continuous DC

Maximum Line
Transient

Vbuf:S: 6V. Rbuf = 1000.
T:S: 100ms

Reverse Polarity
Input Voltage DC

Vbuf;;' -0.6V. Rbuf = 1000

Reverse Polarity Input
Voltage Transient

T :s: 100 ms. Rbuf = 1000

mO
15/15

mAmax

70

60/50

dBmin

0.35

0.50/0.80

Vmax

0.23

0.15/0.15

Amin

32

26/26

Vmin

65

60/60

Vmin

-30

-15/-15

Vmin

-55

-35/-35

Vmin

Electrical Characteristics
VIN = 14V. Islby = 1 mAo CSlby = 10 ""F. unless otherwise indicated. Boldface type refers to limits over the entire operating
temperature range. -40·C :s: TA :s: + 125·C. all other limits are for TA = Tj = 25·C (Note 6).
Parameter

Conditions

Typical

Limit
(Note 2)

Units

5.00

4.85/4.75
5.15/5.25

Vmin
Vmax

2

25/25

mVmax
mVmax
mVmax

Vstandby (Pin 9)
Output Voltage

1 mA :s: 10 :s: 7.5 mA
6V:S: VIN:S: 26V

Line Regulation

9V:s: ViN:S: 16V
7V:S: VIN:S: 26V

5

50/50

Load Regulation

0.5 mA :s: lOUT :s: 7.5 rnA

6

50/50

Output Impedance

5 mAtlc and 1 mArms• fo = 120 Hz

Quiescent Current

0.9

0

Islby = 7.5 mA

1.2

2.0/4.0

mAmax

Islby = 2 mA

0.9

1.5/4.0

mAmax

3·181

•

Electrical Characteristics (Continued)
VIN = 14V,Isiby = 1 mA, Cslby = 10 p.F, unless.otherwise indicated. Boldface type refers to limits over the entire operating
temperature range, - 40·C :s: TA :s: + 125·C, al\ other limits are for T A = Tj = 25·C (Note 6).
Parameter

Typical

Conditions

Limit
(Note 2)

Units

Vstandby (Pin 9) (Continued)
Output-Noise Voltage

10 Hz-100 kHz,lslby

=

1 mA

Long Term Stability

=

Ripple Rejection

fo

Dropout Voltage

ISlby
Islby

p.V

20

mV/1000 hr

70

60/50

dBmin

1 mA

0.26

0.50/0.60

V max

7.5 mA

0.38

0.60/0.70

V max

15

12/12

mAmin

120Hz

=
=

100

Current Limit
Maximum Operational
Input Voltage

4.5V :s: Vslby ,;; 6V,
Rslby = 10000

65

60/60

Vmin

Maximum Line
Transient

VSlby:S: 6V, T:S: 100 ms,
RSlby = 10000

65

60/60

Vmin

Reverse Polarity
Input Voltage DC

Vslby;;;' -0.6V,
Rslby = 10000

-30

-15/-15

Vmin

Reverse Polarity Input
Voltage Transient

T

-55

-35/-35

Vmin

:s:

100 ms, Rslby

=

10000

Electrical Characteristics
VIN = 14V, COUT = 10 p.F, ~ut = 10 p.F, Csiby = 10 p.F, unless otherwise indicated. Boldface type refers to limits over the
entire operating temperature range, - 400C :s: T A ,;; + 125·C, all. other limits are for T A = Tj = 25·C (Note 6).
Parameter

Conditions

Typical

Limit
(Note 2)

Units

±30

±100/± 100

mVmax

±30

±100/± 100

mVmax

±30

±100/± 1()0

mVmax

5.00

4.50/4.50
5.50/5.50

Vmin
V max

5.00

4.50/4.50
5.50/5.50

Vmin
Vmax

5.00

4.50/4.50
5.50/5.50

Vmin
V max

5.00

4.50/4.50
5.50/5.50

Vmin
V max

Tracking and Isolation
Tracking
VOUT-Vslby
Tracking
Vbut-Vslby

lOUT';; 500 mA, Ibut
ISlby:S: 7.5 mA
lOUT = 5 mA, Ibut
Islby :s: 7.5 mA

:s:

=

5 mA,

100 mA,

VOUT-Vbu!

lOUT :s: 500 mA, Ibu! ,;; 100 mA,
Islby = 1 mA

Isolation·

ROUT

=

10,lbut:S: 100 mA

ROUT

=

10,I sibY

Tracking

Vbu! from VOUT
Isolation"

:s: 7.5 mA

Vstby from VOUT
Isolation'

:s:

Rbu!

=

10, lOUT

Rbu!

=

10,lstby :S: 7.5 mA

500 mA

VOUT from Vbu!
Isolation"
Vslby from Vbu!

'Isolation refers to the ability of the specified output to remain within the tested limits when the other output is shorted to ground.

3·182

Electrical Characteristics (Continued)
VIN = 14V, lOUT = 5 mA, Ibuf = 5 mA, Istby = 5 mA, Rt = 130 kfi, Ct = 0.33,...F, Cmon = 0.47 ,...F, unless otherwise indicated,
Boldface type refers to limits over the entire operating temperature range, - 40·C ,;; TA ,;; + 125·C, all other limits are for TA =
TJ = 25·C (Note 6)
Parameter

Conditions

Typical

Limit
(Note 2)

Units

Computer Monitor/Reset Functions
Ireset Low

VIN

= 4V, Vrst = O.4V

5

2/0.50

mAmin

Vreset Low

VIN

= 4V, Irst = 1 mA

0.10

0.40/0.40

Vmax

Rtvoltage

(Pin 2)

1.22

1.15/0.75

Vmin

1.22

1.30/2.00

Vmax

50

45/17.0

mSmin

50

55/80.0

mSmax

Power On Reset
Delay

V""Pmon = 5V
(Tdly = 1.2 Rt Ctl

aVOUT Low
Reset Threshold

(Note 4)

aVOUT High
Reset Threshold

(Note 4)

Reset Output
Leakage

V""Pmon

= 5V, Vrst = 12V

""Pmon Input
Current (Pin 4)

V""Pmon
V""Pmon

-350

-225/-175

mVmin

-500/-550

mVmax

225/175

mVmin

750/800

mVmax

0.Q1

1/5.0

,...Amax

= 2.4V

7.5

25/25

,...Amax

= O.4V

0.01

10/15

,...Amax

1.22

0.80/0.80

Vmin

1.22

2.00/2.00

Vmax

600

""Pmon Input
Threshold Voltage
,...p Monitor Reset
Oscillator Period

V""Pmon = OV
(Twindow = 0.82 RtCmon)

50

45/30

mSmin

50

55/70

mSmax

,...p Monitor Reset
Oscillator Pulse Width

V""Pmon = OV
(RESETpw = 2000 Cmon)

1.0

0.7/0.4

mSmin

1.0

1.3/2.10

mSmax

Minimum ,...p Monitor
Input Pulse Width

(Note 5)

Reset Fall Time

Rrst

= 10k, Vrst = 5V, Crst ,;; 10 pF

0.20

1.00/1.00

Reset Rise Time

Rrst

= 10k, Vrst = 5V, Crst ,;; 10 pF

0.60

1.00/1.50

,...smax

On/Off Switch Input
Current (Pin 8)

VON

7.5

25/25

,...Amax

0.01

10/10

,...Amax

1.22

0.80/0.80

Vmin

1.22

2.00/2.00

Vmax

2

= 2.4V
VON = O.4V

On/Off Switch Input
Threshold Voltage

,...S
,...smax

Note 1: Thermal resistance without a heatsink for junction-te-case temperature is 3°C/W. Thermal resistance case-to-ambient is 400C/W.

Note 2: Tested Limits are guaranteed and 100% production tested.
Note 3: Human body model, 100 pF capacitor discharged through a 1500n resistor.
Note 4: Intemal comparators detect when the main regulator output (VOUT) changes from the measured output voltage (with VIN ~ 14V) by the specified amount.
.l.VOUT High or .l.VouT Low, and set the Reset Error Flag low. The Reset Error Flag is held low until VOUT returns to regulation. The Reset Error Flag is then
allowed to go high again after a delay set by Rt and Ct. (see application section).
Note 5: This parameter is a measure of how short a pulse can be detected at the J-tP Monitor Input. This parameter is primarily influenced by the value of Cmon.

(See Application Hints Section.)
Note 6: To ensure constant junction temperature, low duty cycle pulse testing is used.

3-183

Block Diagram
"
Y,N
ON/OFF SWITCH

11

1

8
ON/OFF
THERIIAL SHUTDOWN

rl-+

!lV.SOOmA
REGULATOR

i;i-

SV. 7.SmA
REGULATOR

....

~S.SV

POWER-UP
RESET
TIllER

L
I.

9

b,

::c.

4.0V

-

V,N
I
SV. 100mA
REGULATOR

3

I
I

10

PEAK DETECTOR
COIIPUTER RESET
TIMER/OSCILLATOR

5
CyON

,-

----f'"' .

7
_

1-

.I.

-

VSTANDBY

CsrBY

~,

::c.
-

4

",p 1I0NITOR

VOUT

CoUT

Y,N
1

VOUT
COt.tPAR~ TOR

2

~,

::c.
-

VBUFFER

CaUF

i~T

RESET

TL/H/11252-2

Pin Description
Pin Name

Pin No.
1

VIN
Rt
Ct
P.Pmon
C mon

2
3
4

5
6

Ground
Reset

7

ON/OFF

8
9

Vstandby
Vbuffer
VOUT

10
11

Comments
Positive supply input voltage
Sets internal timing currents
Sets power-up reset delay timing
.Microcomputer monitor input
Sets p.C monitor timing
Regulator ground
Reseterror flag output
Enables/disables high current regulators
Standby regulator output (7.5 rnA)
Buffer regulator output (100 rnA)
Main regulator output (500 rnA)

External Components
Component

Typical Value

Component Range

Gt
Gtc
Rtc

1 JIoF
130k
0.33p.F
0.01 JIoF
10k

0.47 JIoF-10 JIoF
24k-51Ok
0.033 JIoF-3.3 JIoF
0.001 JIoF-0.1 JIoF
1k-100k

Cinon

0,47 JIoF

0.047 JIoF-4.7 JIoF

10k

5k-100k

Cstby

10 JIoF

10 JIoF-no bound

Cbuf

10 JIoF

10 JIoF-no bound

COUT

10 JIoF

10 JIoF-no bound

CIN

Rt

R,sl

Comments
Required if device is located far from power supply filter.
Sets internal timing currents.
Sets power-up reset delay.
Establishes time constant· of AC coupled computer monitor.
Establishes time constant of AC coupled computer monitor. (See
applications section.)
Sets time windpw for coinputer monitor. Also determines period and pulse
width of computer malfunction reset. (See applications section.)
Load for open oollector reset output. Determined by computer reset input
requirements.
A 10 JIoF is required for stabilitY but larger values can be used to maintain
regulation during transient conditions.
A 10 JIoF is required for stabilitY but larger values can be used to maintain
regulation during transient conditions.
A 10 JIoF is required for stabilitY but larger values can be used to maintain
regulation during transient conditions.

3-184

riii:

Typical Circuit Waveforms

N

CD

co

35V

~

31V
INPUT
VOLTAGE
PIN I
ON/OFF
SWITCH
PIN 8
OUTPUT
VOLTAGE
PIN 11
STANDBY
OUTPUT
PIN 9
TIMING
CAPACITOR
PIN 3

".6V

14V
OV
5V

OV

6V

5V

OV
5V
OV
2V

OV
RESET
VOLTAGE
PIN 7
J'P MONITOR
VOLTAGE
PIN"

5V

OV
5V

1111

OV
TURN
ON

HIGH
VIN

II
HIGH
VOUT

III
LOW
VOUT

III

/

COMPUTER
MALFUNCTION

II
TURN
OFF

J'P
MALFUNCTION

Tl/H/11252-3

Connection Diagram

/

TO- 220 11-LEAD
TAB IS GROUND

11

0

"

MAIN OUTPUT

10

BUFFER OUTPUT

9

STANDBY OUTPUT

8

ON/OFF SWITCH

7

RESET ERROR FLAG

6

GROUND

5

J'P MONITOR CAPACITOR

"
3

TIMING CAPACITOR

2

TIMING RESISTOR

J'P MONITOR INPUT

INPUT VOLTAGE
Tl/H/11252-4

Order Number LM2984T
See NS Package Number TA 11 B

3·185

~

;

r---------------------------------------------------------------------------------,
Typical Performance Characteristics

...I

Dropout Voltage (VOUT)

Dropout Voltage (Vbuf}
0.6

1.2

~

~

O.B

;:l
~

I

I

0.5

1.0

~

IoUT=500mA

0.6
0,4 ~

..... i--'"

CH1

-

I-IoUT = 250 mA

0.2

~~

I

-eo

0,4

!-

0.3

l- I -

0.2

-25 0

25

= 50 MA

so

25

I

./

O~~~--~~~~~

0.3

0.4

0.5

o

0.6

OUTPUT CURRENT (A)

1.6

I-

2D

4D

50

50

100

IoUT=2mA

0.1

o

-SO -25 0

25 SO 75 100 125 150

Dropout Voltage (Vatby)
1.0

~

~

0.2

0.2

0.2

~

./

0.1

..~

~~

V

o
o

L-

Dropout Voltage (Vbuf}
r--r--r---r--r---r---,

O.BI--+--t----+--+---+--l

0,4

0.3

I-

JUNCTlOtf TEMPERATURE (oC)

O.B
0.6

~

JUNCTION TEMPERATURE (OC)

1.0

~

-1-- --

I ! _I
I-- _~UT·7.5mA

~

75 100 125 ISO

1.0

;:l

O.S
0.4

~

Ii!

I
I

-50 -25 0

50 75 100 125 150

Dropout Voltage (VOUT)

~

leiUT

0.1

JUNCTION TEMPERATURE (OC)

~

r-l~~I- ....

o

o

Dropout Voltage (Vatby)
0.11

O.B
0.6
1,,00-

0,4
0.2

o

120

i"'"'

o

10

OUTPUT CURRENT (mA)

OUTPUT CURRENT (mA)

SOD Peak Output Current (Vbuf}

SO Peak Output Current (VBtby)

'<

400

4D

iil

300

Peak Output Current (VOUT)

I
:5

§
il

!

1.2

~

V,N = 14V

0.6

~

0,4

0

o
-so

30

Y,N = 14V

i"'"'
200

2D

100

10

o
-25 0

25

50 75 100 125 ISO

'<

~

iil
~
&

so
40

20

Quiescent Current (Vbuf}
16

V,N = 14V
~ur = 'STBY = 0

~

"'=

~

_IoUT=500mA

..... ~ Io~T=150

iA

-- f--

I I I

o

-so

I

-25 0

25

so

75 100 125 ISO

JUNCTION TEMPERATURE (oc)

-so

iil
S
&

-25 0

4

--

f--

-- l- iot'=150

YIN

= 1.4V

Your Ofr

iour = 100 mA

r

r-- --

1 l J

-50 -25 0

75 100 125 ISO

I I I

b-

o

so

4.0 Quiescent Current (Vatby)

loUT = 'STOY = 0
12

25

JUNCtiON TEMPERATURE (OC)

I V,N' 14V

~

I I I

25 SO 75 100 125 150

JUNCTION TEMPERATURE (OC)

Quiescent Current (VOUT)

-- I-V,.= UV

o

-50 -25 0

JUNCTION TEMPERATURE (Oc)

BO

f-

25

so

75 100 125 ISO

JUNCTIOtf TEMPERATURE (ae)

O~~~~~~--L-~~

-so

-25 0

25

50 75 100 125 ISO

JUNCTION TEMPERATURE (oc)
TLlH/11252-5

3-186

Typical Performance Characteristics

Quiescent Current (Vbud

Quiescent Current (VOUT)
100

'<
.5

I

1

80
80

./

40

./

tl

&

./

20

o

./

o

-~
100

I

3.0

16

'<
.5

2.S

I

2.0

12

~
&

300

400

SOO

600

o

20

~:;

50

""\

40
30
20

I I I

~

['0..

10

'"
-10
-10 -S

0

S

'<
.5

IS

i

10

~L.JSO~AI I I
I I I

&

10

IS

20 2S 30

~

)

o
o

Quiescent Current (VSlby)

1sraY='IOmA-

I

/

'aur=SOmA

-10 S

S

10

IS

20

2S

30

7

Output Voltage (Vbud

~

-20

20

-40

20

-Igur"/
50mA

40

Low Voltage Behavior (Vstby)

6

/

/

o
INPUT VOLTAGE (vl

-20

INPUT VOLTAGE (vl

I

5

30

,

V.

4

20

Rs'rOY" I kO

Low Voltage Behavior (Vbud

lour =500 mA

I

Output Voltage (VSlby)

7

INPUT VOLTAGE (vl

V

mA

-I

-40

Low Voltage Behavior (VOUT)

IouT=2S0mA

10

i

INPUT VOLTAGE (vl

,
20

ISTBly =

-I
-10

INPUT VOLTAGE (vl

-I
-20

10
OUTPUT CURRENT (mAl

-S

INPUT VOLTAGE (vl

o
o

120

RaUF -1000

......

-40

100

O.S

lauF·100mA

~

RoUT = 1000

-I

80

f--~

4

INPUT VOLTAGE (vl

Output Voltage (VOUT)

60

-f- f--

Quiescent Current (Vbud

U

j

40

20

I I I

60

~
&

I.S
1.0

OUTPUT CURRENT (mAl

Quiescent Current (VOUT)
70

IU

-

o
200

U

..,.

./'

OUTPUT CURRENT (mAl

'<
.5

Quiescent Current (Vslby)

20



+ --L-AV2

and for AV1 > AV2, RTH Air> RTH Oil, AV will increase as
the probe length in air increases. For best results the probe
needs to have a high temperature coefficient and low thermal time constant. One way to achieve this is to make use
of resistance wires held in a suitable support frame allowing
free liquid access. Nickel cobalt iron alloy resistance wires
are available with resistivity 50 ,...Ocm and 3300 ppm temperature coefficient which when made up into a probe with 4
x 2 cm 0.08 mm diameter strands between supports (10
cm total) can give the voltage vs time curve shown in Figure
2 for 200 mA probe current. The effect of varying the probe
current is shown in Rgure 3. To avoid triggering the probe
failure detection circuits the probe voltage must be between
0.7V and 5.3V (VREG - 6V), hence for 200 mA the permissible probe resistance range is from ,3.50 to 240. The example given has a resistance at room temperature of gO
which leaves plenty of room for increase during measurements and changes in ambient temperature.

USEfUL
RANGE
OF
PROBE

e.g.
16cm

Various arrangements of probe wire are possible for any
given wire gauge and probe current to suit the measurement
range required, some examples are illustrated schematically
in Figure 4. Naturally it is necessary to reduce the probe

TLlH/B709-7

FIGURE 4
3-203

&I

Application Notes (Continued)
CIRCUIT OPERATION

""',

1) Thermo-Resistive Probes

4.3V

These prob~s require measurements to be made of their
resistance before and after power has been dissipated in
them. With a probe connected as probe 1 in the connection
diagram the LM1042 will start a measurement when pin 8 is
taken to a logic low level (Va < 0.5V) and the internal timebase ramp generator will start to generate the waveform
shown in Figure 5. At 0.7V, Tl, the probe current drive is
switched on supplying ~ constant 200 rnA via the external
PNP transistor and the probe failure circuit is enabled. At 1V
pin 1 is unclamped and C1 stores the probe voltage corresponding to this time, T 2. The ramp charge rate is now reduced as Or charges toward 4V. As the 4.1V threshold is
passed a current sink is enabled and CT now discharges.
Between 1.3V and 1.0V, T3 and T 4, the amplified pin 1 voltage, representing the change in probe voltagE! since T 2 (and
as the current is ,constant this is proportional to the resistance change) is gated onto the memory capacitor at pin 14.
At 0.7V, T 5, the probe current is switched off and the measurement cycle is complete. In the event of a faulty probe
being detected the memory capaCitor is connected to the
regulated supply during the gate period. The device leakage
at pin 14 is a maximum of 2 nA to give a long memory
retention time. The voltage present on pin 14 is amplifed by
1.2 to drive pin 16 with a low impedance, ± 10 mA capability, between 0.5V and 4.7V. A new measurement can only be
started by taking pin 8 to a low level again or by means of
the repeat oscillator.

Vg

1.0V

TUH/8709-9

FIGURE 6
80

g..,

60

V

::IE

1=

..is

V

./

40

/

!li

20

V

/
o

o

30

60

80

100

120

TUH/8709-10

FIGURE 7
3) Second Probe Input

4V

A high impedance input for an alternative sensor is available
at pin 7. The voltage applied to this input is amplified and
output at pin 16 when the input is selected with a high level
on, pin 8. The gain is defined by the feedback arrangement
shown in Figure 8 with adjustment possible at pin 10. With
pin 10 open the gain is set at a nominal value of 1.2, and
this may be increased by connecting a resistor between pin
10 and ground up to a maximum of 3.4 with pin 10 directly
grounded. A variable resistor may be used to calibrate for
the variations in sensitiility of the sensor used for probe 2 .

lV
OV

II

.J :
I

::.

PROBE CURRENT

: SECOND MEASUREMENT GATE PULSE

Jl

'
::L
II

ij

PIN 16

FIRST MEASUREWENT CLAMP
TL/H/8709-8

FIGURE 5
2) Repetitive Measurement
With a capacitor connected between pin 9 and ground the
repeat oscillatpr will run with a waveform as shown in Figure
6 and a thermo-resistive probe measurement will be triggered each time pin 9 reaches a threshold of 4.3V, provided
pin 8 is at a logic low leveL The repeat oscillator runs independently of the pin 8 control logic.

TL/H/8709-11

FIGURE 8
POWER SUPPLY REGULATOM

The' arrangement of the feedback for the supply regulator is
shown in Figure 9. The circuit acts to maintain pin 15 at a
constant 6V and when directly connected to pin 11 the regulated output is held, at 6V. If required a resistor R may tie
connected between pins 15 and 11 to increase the output
voltage by an ,amount corresponding typically to 1 mA flowing in R. In this way a variable 'resistor may be used to trim
out the production tolerance of the regulator by adjusting for
VREG ;;" 6.2V.
'

As the repetition rate is increased localized heating of the
probe and liqu'id being measured will be the main consideration in determining the minimum acceptable measurement
intervals. Measurements:will tend to become more dependent on the amount of fluid movement changing the rate of
heat transfer away from the probe. The typical repeat time
versus timing capaCitor value is shown in Figure 7.
3-204

~--------------------------------------------------~E

Application Notes (Continued)

--------.

.---------------

I

I

-4----~------~

....

CI

t

6

•I
I

I

I
I
I

·-~-I

.---------------

. TUH/8709-12

FIGURE 9

------_ ..
I

PROBE CURRENT REFERENCE CIRCUIT
The circuit defining the probe circuit is given in Figure 10. A
reference voltage is obtained from a bandgap regulator derived current flowing in a diode resistor chain to set up a
voltage 2 volts below the supply. This is applied to an amplifier driving an external PNP transistor to maintain pin 3 at 2V
below supply. The emitter resistance from pin 3 to supply
defines the current which, less the base current, flows in the
probe. Because of the sensitivity of the measurement to
probe current evident in FI{J/Jre 3 the current should be adjusted by means of a variable resistor to the desired value.
This adjustment may also be used to take out probe tolerances.

Tl/H/8709-13

FIGURE 10
TYPICAL APPUCATIONS CIRCUIT
A typical automotive application circuit is shown in FI{J/Jre 1!
where the probe selection signal is qbtained from the od
pressure switch. At power up (ignition on) the oil pressure·
switch is closed and pin 8 is held low by R4 cauSing a probe
1 (oil level) measurement to be made. Once the ~ngine has
started the oil pressure switch opens and 01 pulls pin 8 high
changing over to the second auxiliary probe input The capacitor C5 holds pin 8 high in the event of a stalled engi~
so that a second probe 1 measurement can not occur In
disturbed oil. Non-automotive applications may drive pin 8
directly with a logic signal.

TUH/8709-14

FIGURE 11. Typical Application Circuit

3-205

•

-~

~ r-~----------------------------------------------------------------------,

tt/National,Semiconductor

LM1815 Ad~ptive Variable Reluctance Sensor Amplifier
General Description

Features

The LM1815 Is an adaptive sense amplifier and default gating circuit for motor control applications. The sense amplifier provides '8 one-shot pulse output whose leading edge
coincides with the negative-going zero crossing of a ground
referenced'input signal such as from a variable reluctance
magnetic pick-up coil.
In normal operation, this timing reference signal is processed (delayed) externally and returned to the LM1815. A logic
input is then able to select either the timing reference or the
processed signal for transmission to the output drIVer stage.
The adaptive sense amplifier operates with a positive-going
threshold which is derived bY peak deteCting the Incoming
signal and dividing this dOwn. Thus the input hysteresis varies with Input signal' amplitude. This ,enables the circuit to
sense in situations wliere the high speed noise is greater
than the low speed Signal amplitude. Minimum input signal
is 100 mVp-p.
' ,
'

•
•
•
•
•
•

Connection Diagram

Truth Table

RC
TIMING

NC

REFERENCE
PULSE OUT

IM'UT

BATED
SWCf ,OUTPUT

Adaptive hysteresis
Single supply operation
Ground referenced input
True zero crossing timing reference
Operates from 2V to 12V supply voltage
Handles inputs from 100 mV to over 120V with external
resistor
• CMOS compatible logic

Applications
•
•
•
•
•

SIgnal
Input

TIMING
PULS£
INPUT

LM111&

NC

GND

SIGNAL
INPUT

IIc

THRESHOLD
ADJUST

NC'

Position sensing with notched wheels
Zero crossing switch
Motor speed control
Tachometer
Engine testing

PEAK
DETECTOR
CAPACrrOR

TVH/7893-1

Top View

Order Number LM1815M or LM1815N
See NS Package Number M14A or N14A

3-206

Input
Select ,

Timing
Input

Gated
Output

Pulses

L

X

Pulses

X

H

Pulses

Pulses

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speCifications.
Supply Voltage
12V
Power Dissipation (Note 1)
Operatng Temperature Range

Storage Temperature Range
Junction Temperature (Note 2)

-S5"Cto

+ 150"C

+ 125"C

Input Current
Lead Temperature (Soldering, 10 sec.)

±30mA
2SO"C

1250mW
- 40"C to + 125"C

Electrical Characteristics (TA = 25"C, Vee = 10V, unless otherwise specified, see Figuf9 1)
Parameter

Conditions

Operating Supply Voltage
Supply Current

fiN = 500 Hz, Pin 9
Pin 11 = 0.8V

Reference Pulse Width

fiN

Input Bias Current

VIN

=

Min

Typ

Max

Units

2.5

10

12

V

3.S

S

mA

100

130

,..s

5

,..A

2V,
70

12

20

28

kG

Zero Crossing Threshold

= 1 Hzt02kHz
= 2V, (Pin 9 and Pin 11)
VIN = OV dc, (Pin 3)
VIN = 5 Vrms, (Note 3)
VIN = 100 mVp-p, (Pin 3)

25

mV

Logic Threshold

(Pin 9 and Pin 11)

0.8

1.1

2.0

V

VOUTHigh

RL

7.5

8.S

VOUTLOW

ISINK

Input Arming Threshold

Pin 5 Open, VIN ,;;: 135 mVp-p
Pin 5 Open, VIN ~ 230 mVp-p

Input Bias Current
Input Impedance

Output Leakage Pin 12

=

200

1 kG, (Pin 10)

=

nA

V

0.3

0.4

30

45

SO

mV

40

80

90

%OfV3Pk

25

mV

10

,..A

0.1 mA, (Pin 10)

Pin5toV+

200

Pin5toGnd

-25

V

mV

= 11V
112 = 2mA

0.01

V12

0.2
0.4
V
Saturation Voltage P12
Note 1: For operation at elevated temperatures. the device must be derated based on a 125'C maximum junction temperature and a thermal resistance of srrC/W
(DIP). 120 'C/W (80-14) junction to ambient
Note 2: Temporary excursions to 15O"C can be tolerated.
Note 3: Measured at input to external 18 kIl resistor. IC contains 1 kIl in series with a diode to attenuate the input signal.
nWING
REFERENC[

''9

y'

t=O.673RC

R

1501<4

o.OOt"'F"

~

II'UT
SEl£CT

GATED
OUTPUT

PUlSE

INPUT

OUT

L II<4I
-=
5.6kA

1,3

OIE-!IIICII
TC 0
lR"

11

.'2

g

10

8

fR
~

~
~

LW1StS

~

l'

•

.....

~

14

. 3

=

18k4

V~9\

~

1

5

16

7

~f-i
0E1Ecr0t! -

WACII1lR

FIGURE 1. LM1815 Adaptive Sense Amplifier

3-207

1.6YA

~
TL/HI7893-2

~

=e

::I!

Schem~tic Diagram

.:.I

iI

;1'

~.

I

~"
iii .

~

~

~

II

...a!

r-

u

"

~!
0-

§

~1

.

~,

I.

;'

,

.

~

iii

11=2
I

~ L

~~

~I'

;!~
il:

'\V

'

'

\r
;~

&loll

~111

I~

~

r1L
~iII

Ii

L:J~:!

;:5

~l
..

~iII

1=&

Lf

it!;

~

?&.
a

II

iii,L

,L

~'

_£
.....

"0/'

2i1

. ill

~

;

H

U

L.;:T

, '

II

9'

~

~]~

.' '

§

:0

ill!l .

\.~

..

I

~iI

M

~

..

'1

:a

~'d

ii,

, ,Y

~.

'i

~

iJ..~"

0-

,

:~~

rtl!lrtL

rl~

¥

...~~

~,,-

'N

Eil

~

:<

"M
;;='

..

.. • =
TVHn893-4

3·208

~
.....
C»

,

INPUT
THRESHOLD
VOLTAGE

.....

UI

Tl/H/7893-3

FIGURE 2. U111.815 Oscillogram.

Application Hints
idly as the input signal amplitude increases, and decays by
virtue of the resistor connected externally at pin 7 to track
decreases in the input signal.

Input Clamp
The signal input at pin 3 is internally clamped. Current limit
is provided by an external resistor which should be selected
to allow a peak current of 3 mA in normal operation. Positive.
inputs are clamped by a 1 kO resistor and series diode,
while an active clamp limits pin 3 to -350 mV for negative
inputs (see R4, 012, 011 in internal schematic diagram).

Note that since the input is clamped, the waveform observed at pin 3 is not identical to the waveform obServed at
the variable reluctance sensor. Similarly, the voltage stored
at pin 7 is not identical to the peak voltage appearing at
pin 3.

Operation of Zero Cr088lng Detector

MODE 2, Pin 5 connected to V +. The input armirg threshold is fixed at 200mV minimum when pin 5 is connected to
the positive supply. The chip has no output for signals of
less than 200 mV peak, and triggers on the next negativegoing zero crossing when the threshold is exceeded.

The LM1815 is designed to operate as a zero crossing detector, triggering an internal one shot on the negative-going
edge of the input signal. Unlike other zero crossing detectors, the LM1815 cannot be triggered until the input signal
has crossed an "arming" threshold on the positive-going
portion of the waveform. The arming circuit is reset when
the chip is triggered, and subsequent zero crossings are
ignored until the arming threshold is exceeded again. This
threshold varies depending on the connection at pin 5.
Three different modes of operation are possible:

MODE 3, PIn 5 ground.d~ With pin 5 grounded, the input
arming threshold is set to OV (± 25 mV maximum). Positivegoing zero crossings arm the chip, and the next negative
zero crossing triggers it.
The one shot timing is set by a resistor and capacitor connected to pin 14. The output pulse width is

MODE 1, Pin 5 open. The adaptive mode./s selected by

pulse width = 0.673 RC

(1)

leaving pin 5. open circuit. For input signals of less than
135 mVp-p, the input arming threshold is typically 45 mY.
Under these conditions the input signal must first cross the
45 mV threshold in the positive direction to arm the zero
crossing detector, and then cross zero in the negative direction to trigger it. If the signal is less than 30 mV peak (minimum rating in Electrical Characteristics), the one shot is
guaranteed to not trigger.

In some systems it is necessary to externally generate pulses, such as during stall conditions when the variable reluctance sensor has no output. External pulse inputs at pin 9
are gated through to pin 10 when Input Select (pin 11) is
pulled high. PIn 12 is a direct output for the one shot and is
unaffected by the status of pin 11.

Input Signals of greater than 230 mVp-p cause the arming
threshold to track at 80% of the peak input voltage. A peak
detector (pin
stores a value relative to the positive input
peaks to establish the arming threshold. Input Signals must
exceed this threshold in the positive direction to arm the
zero crossing detector, which can then be triggered by a
negative-going zero crossing. The peak detector tracks rap-

grounded.

Input/output pins 9, ·11, 10 and 12 are all CMOS logic compatible. In addition, pins 9,11 and 12 are TIL compatible.
Pin 10 is not guaranteed to drive a TIL load.

n

Pins 1, 4, 6 and 13 have no internal connections and can be

3-209

•

en
....

~

r-----~~--~----------------------~--------------------------------------_,

t!lNational Semiconductor

LM 1819 Air-Core Meter Driver
General Description

Features

The LM1819 is a function generato~/driver for air-core
(moving-magnet) meter movements. A Norton amplifier and
an NPN transistor are included on chip for signEIl conditioning as required. Driver outputs are self-centering and develop ±4.5V swing at 20 mAo Better than 2% Ii~arity is guaranteed over a full 305-degree operating range.

•
•
•
•

Self-centering 20 mA outputs
12V operation'"
Norton amplifier
Function generator

Applications
• Air-core meter driver
• Tachometers
• Ruggedized instruments

Typical Application
Vu,=IUV

'1M
85
87
SIGNAL 1_7 Uk
Uk
FM.~t+~~-1~-----1~~~
POINTS
R6

II "
01'
lN4007

10k

R3

lot
IIoEJI

Uk
DZ
2N4746 t
18V·

+ C3
~~,.Ft ....___....,
<

RI

IW

Uk

R2"
3301<

CI'
IOnF

PART NO, M1203

MOVING MAGNET METERtt
TlIH/5263-1

FIGURE 1. Automotive Tachometer Application. Circuit shown operates,
with 4 cylinder engine and deflects meter pOinter (270") at 6000 RPM.

Order Number LM1819M or LM1819N
See NS Package Number M14A or N14A
'TRW Type X463UW Polycarbonate Capacitor
"RN60D Low TC Resistor (± 100 ppm)
tComponents Required for Automotive Load Dump Protection
ttAvailable from FARIA Co.
POBox 983, Uncasville, CT 06382
Tel. 203-848-9271

3-210

....
iii:

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V+ (pin 13)
Power Dissipation (note 1)

Operating Temperature

-40"Cto +85'C
-65'C to -150"C

Storage Temperature
Lead Temp. (Soldering, 10 seconds)

20V

CO

26O"C

BVCEO

1300mW

.....
.....

CO

20VMIN

Electrical Characteristics Vs = 13.1V TA = 25'C unless otherwise specified
Symbol
Is
VREG

VREF

Pln(s)

Conditions

Supply Current

Parameter

13

Zero Input Frequency
(See Figure 1)

Regulator Voltage

11

IREG

Regulator Output Resistance

11

IREG

Reference Voltage

4

IREF

Reference Output Resistance

4

Norton Amplifier Mjrror Gain
hFE

NPN Transistor DC Gain
Function Generator Feedback
Bias CUrrent
Drive Voltage Extremes,
Sine and Cosine
Sine Output Voltage
with Zero Input

k

5,6

=
=

Min

8.1

OmA

2, 12
2

8.5

Max

Units

65

rnA

8.9

V

13.5

0 rnA to 3 rnA

= OmA
IREF = 0 JJA to 50 p.A

1.9

IBIAS '" 20 p.A

0.9

{}

2.1

2.3

V
k{}

5.3

9, 10
1

Typ

1.0

1.1

125
Vl

=

5.1V

=

ILOAD
Va

=

rnA

±4

±4.5

V

-350

0

20mA

VREF

=

1.0

Function Generator Linearity

FSD

Function Generator Gain

Meter Deflection//!;.Va

305'
50.75

53.75

+350

mV

±1.7

%FSD

56.75

'IV

Note 1: For operation above 2S'C, the,LM1819 must be derated based upon a 12S'C maximum junction temperature and a thermal resistance of 76"C/W which
applies for the device soldered in a printed clrcuR board and cparatlng in a sUII"';r ambient

Application Hints
AIR-CORE METER MOVEMENTS

H fields (Figure 3(c)). H is proportional to the voltage applied
to a coil. Therefore, by varying both the polarity and magni·
tude of the coil, voltages the axle assembly can be made to
rotate a full 360". The LM 1819 is designed to drive the me·
ter through a minimum of 305'.

Air·core meters are often favored over other movements as
a result of their mechanical ruggedness and their indepen·
dence of calibration with age. A simplified diagram of an air·
core meter is shown in Figure 2. There are three basic
pieces: a magnet and pointer attached to a freely rotating
axle, and two coils, each oriented ata right angle with reo
spect to the other. The only moving part in this meter is the
axle assembly. 111e magnet will tend to align itself with the
vector sum of ti fields of each Coil, where H is the magnetic
field strength vector. If, for instance, a current passes
through the cosine coil (the reason for this nomenclature
will become apparent later) as shown in Figure 3(8), the
Illagnet will align its magnetic axis with the coil's H field.
Similarly, a current in the sine coil (Figure 3(bJ) causes the
magnet to align itself with the sine H field. If currents are
applied simultaneously to both sine and cosine coils, the
magnet will turn to the direction of the vector sum of the two

-

POINTER ""'"'IIi:

;;""AXLE

~r ib
MAllNET~

~~
~l ~Vf)

-.nooooCOSINECOll

t;; ~ IIy

SINE COIL

&I
TLlH(5.263-2

FIGURE 2. Simplified Diagram of an Air Core Meter.

3-211

,......
en

CD

~

r---------------------------------------------------------------------~----------~--~

Application Hints (Continued)

N

COSIIE
COIL

COSINE

COSINE
COIL

COIL

)",',

TLlH/6263-3

00

.~

~

FIQ!JRE 3, Mag!)et and pointer pOsItIon are controlled
In an air-all'e meter the axle assembly is supported by two
nylon bushings. The torque exerted on the pointer is much
greater than that found in a. typical d' Arsonval movement. In
contrast to a d'Arsonval movement, where calibration is a
function ·of spring and magnet characteristics, air-core meter calibration is only affected by the mechanical alignment
of the drive coils. Mechanical calibration, once set at manufactura, can not change.

Comparing [3] to [2] we see that if HSINEvaries as the sine
of 6, and HCOSINE varies as the cosine of 6, we will generate a net H field whose direction is the same as 6. And since
.the axle aSsembly aligns itself With the .net H field, the pointerwill always point in the diraction of 6.
THELM1819
Included in the LM1819 is a function gSnerator whose tWo
outputs are designed to vary approximately as the sine and
coSine of an input. A minimum drive of ±20 mA at ±4V is
available at pins 2· (sine) and 12·(cosine). The common side
of each coil is returned to a 5.1 V zener diode reference and
fed back to pin 1.

Maldng pointer position a linear function of some input is a
matter of properly ratioing the drive to each coil. The H field
contributed by each coil is a function of the applied .current,
and the current is a function of the coil voltage. Our desired
result is to have 6 (pOinter deflection,measured in degrees)
proportional to an input voltage: ,
6=kV1N
[1]
Where k is a constant of proportionality, with units of degrE!ss/volt. The vector sum of each coils' H field must follqw
the deflection angle 6. We know that the axle assembly
always points in the direction of tl1e vector sum of HSINE
and HCOSINE. This diraction (see Figure 4) is found from the '
formula:
(6)=arctan { I HSINE III HCOSINE II
Recalling some basic trigonometry,
(6) == arctan(sin (6) I cos(6 ))
IIcasM+HSIlIE .

bY the", field generated by the two dWe coils.

[2]

For the function generator, k '" 540 IV ,(in equation 1). The
input (pin 8) is internally connected to the Norton amplifier's
OUtput,VIN as considered in equation [1] is actually the difference of the voltages at pins· 8 (Norton outputlfunction
generator input) and 4. Typically the reference voltage at pin
4 is 2.1V. Therefore,
6=k(Va-VREF) = 54 (Ve-2.1)
.14]
As Va varies from 2.1V to 7.75V, the function generator will
drive the meter through the chip's rated 3050 range.
Air-core meters are mechanically zeroed during manulacture such that when only th.e cosin", coil is driven, the pointer indicates zero degrees deflection. HOweVer, in some applications a slight trim or offSet may be requited. This is
accomplished by sourcIng Or sinking a DC CUrrent ofa few
microamperes at pin 4~ . .. .
.

, [3]

"HIIIiE

A NClrton amplifier 'is avail~lefor conditioning .'various input
signals and driving the function generator. A Norton amplifier was chosen since it makeS simple frequency to'voltBge
comierter. While the:non-inverting input (pin 6) bias is at one
diodedrpp above gt()Und,the inverting input (5) iii
~.1V,
equal to the pin 4 reference. Mjrrorgain r~maiQs essentially
flat to IMIRROR = 5 mAo The .Norton amplifier's OutP!lt (8) is
designed to source current into its load. To bYP8!lS the Norton amplifier simply ground the non-inverting· input, tie the
Inyer.tii'lg input the referen~,anddrive pinS (Norton
put/function generator input) d i r e c t l y . ' .' .

a

at

to

/"'.)

oOt;

An NPN~nsistor is included on chip for buffering and
~quaring inp~ signals.JtS,u"fulness 'il! exempiified in Fig-

TLlH/6263-4

ures 1 & 6 where an ignition·pulse Is converted to a rectan-

FIGURE 4. The vector 8um of HCostNE and HSINE points
In a direction 6 mea8ured In a clOckwise direction from

gular waveform by an RC network and the transistor. The
emitter is internally connected to ground. It is important not
to allow the base to drop below -5Vdc, as damage may
occur. The 2.1V reference previously described is derived
from an 8.5V regulator at pin 11. Pin 11 is used as a stable
supply for collector loads, and currents of up to 5 mA are
easily accommodated.

HcoSlNr

3-212

Application Hints (Continued)
TACHOMETER APPLICATION

The charge pump Circuit in Figure 1 can be operated in two
modes: constant input pulse width (C1 acts as a coupling
capaCitor) and constant input duty cycle (C1 acts as a differentiating capaCitor). The transfer functions for these two
modes are quite diverse. However, deflection is always directly proportional to R2 and ripple is proportional to C2.
The following variables are used in the calculation of meter
deflection:

A measure of the operating level of any motor or engine is
the rotational velocity of its output shaft. In the case of an
automotive engine the crankshaft speed is measured using
the units "revolutions per minute" (RPM). It is possible to
indirectly measure the speed of the crankshaft by using the
signal present on the engine's ignition coil. The fundamental
frequency of this signal is a function of engine speed and
the number of cylinders and is calculated (for a four-stroke
engine) from the formula:
f=ner>/120
(Hz)
(5)

~bol

description
number of cylinders

n

where n = number of cylinders, and er> = rotational velocity of
the crankshaft in RPM. From this formula the maximum frequency normally expected (for an 8 cylinder engine tuming
4500RPM) is 300 Hz. In certain specialized ignition systems
(motorcycles and some automobiles) where the coil waveform is operated at twice this frequency (j=er>/60). These
systems are identified by the fact that multiple coils are used
in lieu of a single coil and distributor. Also, the coils have
two outputs instead of one.
A typical automotive tachometer application is shown in Ftgure 1. The coil waveform is filtered, squared and limited by
the RC network and NPN transistor. The frequency of the
pulse train at pin 9 is converted to a proportional voltage by
the Norton amplifier's charge pump configuration. The ignition circuit shown in Figure 5 is typical of automotive systems. The switching element "S" is opened and closed in
synchronism with engine rotation. When "5" is closed, energy is stored in Lp. When opened, the current in Lp diverts
from "5" into C. The high voltage produced in Ls when "5"
is opened is responsible for the arcing at the spark plug.
The coil voltage (see FI{J/Jre ~ can be used as an input to
the LM1819 tachometer circuit. This waveform is essentially
constant duty cycle. D4 rectifies this waveform thereby preventing negative' voltages from reaching the Chip. C4 and
R5 form a low pass filter which attenuates the high frequency ringing, and R7 limits the input current to about 2.5mA.
R6 acts as a base bleed to shut the transistor OFF when
"5" is closed. The collector is pulled up to the intemal rl!gulator by RREG. The output at pin 9 is a clean rectangular
pulse.
'

er>, er>IDLE engine speed at redline and idle, RPM
8
pointer deflection at redline, degrees
8
charge pump input pulse width, seconds
VIN

peak to peak input voltages, volts
maximum desired ripple, degrees
function generator gain, degrees/volt
f, flDLE input frequency at redline and idle, Hz
Where the NPN transistor and ,regulator are used to create a
pulse VIN=8.5V. Acceptable ripple ranges from 3 to 10 degrees (a typical pointer is about 3 degrees wide) depending
on meter damping and the input frequency.
The constant pulse width circvit is designed using the following equations:
118
k

(1)

100p.A<

(2)

Cl ~ 108
Rl

(3)
(4)

~~<3 mA

R2=~ = 120R1 8
VIN8kf

,

1

C2

VINner>8k

R2118flDLE

1

R2118ner>IDLE

The constant duty cycle equations are as follows:
RREG ~ 3 kO
Rl s; VINX104 -RREG
Cl s; 8/10(RREG+Rl)
Rz = 8/3.54ner>Cl=8/425fCl

C:! =' 425Cl/118 ,
The values in Figure 1 were caiculated with n = 4,
er>=6000RPM, 8=270 degrees, 8=1 ms, VIN is
VREG-0.7V, and 118='3 degrees in the constant duty cycle
mode. For distributqrless ignitions these same equations will
apply if er>/60 is substituted for f.

Many ignition systems use magnetic, hall effect or optical
sensors to trigger a solid state switching element at "5."
These systems (see the LM1815) typically generate pulses
of constant width and amplitude suitable for driving the
charge pump directly.

II

3-213

.,.

~ .-~----------------------~------~--~------------~----~---------------,

.,.
CD

:5

Equivalent Schematic

3-214

Typical Applications
11

REO

Ram
OUTPUT
TO CHAR8E
PUMP

SPllRK

PWG
04

R7

H5

C4

LM1B1S

10

R8
7.14

TUH/5263-9

FIGURE 5. Typical Pulse-Squaring Circuit for
Automotive Tachometera.

--1

OPENED

"s"

CLOSED

COIL
WAVEFORM

':

I

L

C2

~------'~~~L

Cl

-1~~.....I

OUTPUT ~ B.5V .....,
CHARGE PUMP OV
- - _..

TL/H/5263-11
TUH/5263-10

FIGURE 6. Waveforms Encountered In Automotive
Tachometer Circuit.
'

FIGURE 7. Tachometer Charge Pump.

Voltage Driven Meter with Norton Amplifier Buffer
V+ =13,IV

Hz

120
lW

R2"
13GK

COSINE

•

Rl
lOOk

TL/H/5263-5

Deflection = 54 (YIN -. 7)R2/R,

(degrees)

o to 305' deflection is obtained wi1h .7 to 5V input
'Full scale deflection is adjusted by trimming R2.

3·215

Typical Applications (Continued)
Unbuffered Voltage DrIven Meter'
V+ =13.1V

COSIIIE

114733

Tl/H/5263-6
Deflection = 54(VIN - 2.1)

. (degrees)

o to 30S' deflection is obtained for inputs of 2.1 to 7.7SV.
Full scale dellecUon Is edjusted by 1rimming the input voltage.
,\

Current Driven Meter
V+ =13.1V

liz

120
lW

R2*
5INI

COSINE

TlIH/5263-7
DellecUon=54R21IN

(degrees)

Inputs of 0 to 100 pA deoect'~ ~ o io. 27a'.
'Full scale dellecUon Is edjusted·,by 1rimming R2.

9-216

...
....
CD

ill:

Typical Applications (Continued)

....

CD

Level Shifted Voltage Driven Meter
V+ =13.1V

Hz

120
1W

COSINE

1M

1M

1M

TI.lH/5263-8

Deflection = 54VIN

(degrees)

Inputs of 0 to 5.65V deflect the meter through a range of 0 to 305".
Full scale deflecUon is adjusted by bimming the input voltage.

&I

3-217

~

~

I!fINational Semiconductor

LM 1830 Fluid ,Detector
General Description

Features

The LM1830 is a monolithic bipolar integrated circuit designed for use in fluid detection systems. The circuit is ideal
for detecting the presence, absence, or level of water, or
other polar liquids. An AC signal is passed through two
probes within the fluid. A detector determines the presence
or absence of the fluid by comparing the resistance of the
fluid between the probes with the resistance internal to the
integrated circuit. An AC sigrial is used to overcome plating
problems incurred by using a DC source. A pin is available
for connecting lin external resistance in cases where the
fluid impedance is of a different magnitude than that of the
internal resistor. When the probe resistance increases
above the preset value, the oscillator signal is coupled to
the base of theopen-collector output transistor. In a typical
application, the: output could be used to drive a LED, loud
speaker or a low current relay.
'

•
•
•
•
•
•

Low external parts count
Wide supply operating range
One side of probe input can be grounded
AC coupling to probe to prevent plating
Internally regulated supply
'AC or DC 9utput

Applications
•
•
•
•
•

~everage dispensers
Water softeners
I~rigation
Sump pumps
Aquaria

•
•
•
•

RadiatOrS
Washinginachines
Reservoirs
Boilers

Logic and Connection Diagram
Dual-In-Une Package
DICILLATOR

Vco

OUTIIIT
fAnF)

DUTPIT

OICILLATOR
CAPACITOR

Ie

Ie

DlTEeroR

FILTlR

IND

III'"

CAP

Ie

Ne

_ILLATOR
OUTPUT

lie

ORILLATOR
WAClTDR

TD'VIEW

Order Number LM1830N
See NS Package Number N14A

3-218

TUH/5700-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
28V
Power Dissipation (Note 1)
1400mW

Output Sink Current
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

20mA
-40"Cto +85°C
- 40"C to + 15O"C
260"C

Electrical Characteristics (V + = 16V, TA = 25°C unless otherwise specified)
Parameter

Conditions

Typ

Max

Units

Supply Current

5.5

10

rnA

Oscillator Output Voltage
Low
High

1.1
4.2

Min

Internal Reference Resistor
Detector Threshold Voltage
Detector Threshold Resistance

V
V

13

8

25

660
5

Output Saturation Voltage
Output Leakage
Oscillator Frequency

lo=10mA
VPIN12=16V
Cl=O.OO lp.F

10

15

0.5

2.0
10
12

7

4

kO
mV
kO
V

IJA
kHz

Nota 1: The maximum junction temperature rating of the LMI830N is 150'C. For operation at elevated temperatures, devices in the dual-in-Hne plastic package
must be derated based on a thermal resistance of 89'C/W.

Schematic Diagram
OSCILLATOR
OUTPUT

VCC
I.

10k

OSCILLATOR
OUTPUT
(RREFI

O"IOIAL
OETECTOR FILTER
'IPUT CAPACITOR

13

Ii

~

12

1311
101<

8.111<

2ft

2&k

lV',4 ~~

OUTPUT

•

10

--....1 Ok

~

..... ,
30k

1

CI

~~

~
.......

~

P"' )

_~:I

GIO

7

CI

~

~

TL/H/S700-2

•
3-219

Typical Performance Characteristics

I
i~

51
~

,.

1.1&

1.DI

11r--r~r--r~~-r~

·JA·2&"C

--

I'

.::!

..
j
='
i'i:H

1
5

\
o

&11111125.
SUppi YVOLTAGE (V)

II!

..

it'

•

15

II

II

25

31

Detector Threshold Voltage
vs Temperature
VCC·IIV-

II

i:
I'

.."..

V

f""

r- f...

.".,

~

~

..

21141

1

. . . 1•

.........

.'

MlIIENT TEMPERATURE rCI

I

I

2141

••

1.

;

'

..

........

.......

........

H

ia

'"

t

ill

IOIH

V~C'I~-

I',
II
14
II

,..
~

co

if

.

I'

•

....

I

J

i

I
41

"

..

. OSCillator Frequency vs
Ambient Temperature

Output Saturation Voltage va
Output Current'

!C

21

7

AMIIENT TEMPERATURE ret

VOL

10

I'

10 1.

TEMPERATURE rCI

"
··Ii,"

"- ~

11

.,

.... - 2 I . 2 I 4 I

II:

": :1

V C"IIV'

.. ·11

Vee '18V

VOH

•

~

12

MIIIENT TEWfRATURE rCI

OscIDator VOH and VOL
vs Ambient Temperature

...... -2,

•

i!:

I

o

25.

13

I

~ f-"'"

...........

211

Probe Threshold Resistance
vs Temperature

i

J""--. .
i"...-'

15

BUWlY VOLTAGE M

za

II

.10

BUWlY VOLTAGE M

Reference Resistor vs "",blent
Temperature

~

I' 1--+-+--+-+--i~cI

I

U

.~

Power Supply Currerit vs
Suppiy Volta,,~

25

T~'2&,,~ .'

1.1

§
II:

Threshold Re_nee vs Supply
Voltage
"

Nonnallzed OscIllator Frequency
; va Supply Voltage

101

OUTPUT CUI\RENT. (PINI2I.lIIIA!

rl
II!

tP""
~!.
15

S51

§~

~s

~

.
.

o

-411 -20

I

21

48

BO

I.

lDO

_lENT TEMPERATURE ret

Equivalent Resistance vs
Concentration of Several
Solutions

411

4111
3511

ZII
2GII
III
I.

~

-

II

o

~4

JCI

,....
110

1.011

D.81

8.1

COICENTRATION (OIM1MOLECUlAR
EQUIVAlENTS/lITREI
TLlH/5700-9

3-220

Application Hints
The LM1830 requires only an external capacitor to complete the oscillator circuit. The frequency of oscillation is
inversely proportional to the external capacitor value. Using
O.OOl,...F capacitor, the output frequency is approximately 6
kHz. The output from the oscillator is available at pin 5. In
normal applications, the output is taken from pin 13 so that
the intemal13k resistor can be used to compare with the
probe resistance. Pin 13 is coupled to the probe by a blocking capacitor so that there is no net dc on the probe.

It is possible to calculate the resistance of any aqueous
solution of an electrolyte for different concentrations, provided the dimensions of the electrodes and their spacing is
known.
The resistance of a Simple parallel plate probe is given by:
R= l000.~ 0
c.p
A
where

Since the output amplitude from the oscillator is approximately 4 VeE, the detector (which is an emitter base junction) will be turned "ON" when the probe reSistance to
ground is equal to the internal 13 kO resistor. An internal
diode across the detector emitter base junction provides
symmetrical limiting of the detector input signal so that the
probe is excited with ± 2 VeE from a 13 kO source. In cases
where the 13 kO resistor is not compatible with the probe
resistance range, an external resistor may be added by coupling the probe to pin 5 through the external resistor as
shown in Figure 2. The collector of the detecting transistor
is brought out to pin 9 enabling a filter capaCitor to be connected so that the output will switch "ON" or "OFF" depending on the probe resistance. If this capacitor is omitted,
the output will be switched at approximately 50% duty cycle
when the probe resistance exceeds the reference resistance. This can be useful when an audio output is required
and the output transistor can be used to directly drive a loud
speaker. In addition, LED indicators do not require de excitation. Therefore, the cost of a capacitor for filtering can be
saved.

d=separation of plates (cm)
c=concentration (gm. mol. equivalent/litre)
p = equivalent conductance
(0-1 cm2 equiv. -1)
(An equivalent is the number of moles of a substance that
gives one mole of positive charge and one mole of negative
charge. For example, one mole of NaCI gives Na + + CI- so
the equivalent is 1. One mole of CaCI2 gives Ca + + + 2CIso the equivalent is 1/2.)
Usually the probe dimensions are not measured physically,
but the ratio dl A is determined by measuring the resistance
of a cell of known concentration c and equivalent conductance of 1. A graph of common solutions and their equivalent
conductances is shown for reference. The data was derived
from D.A. Macinnes, "The Principles of ElectrochemiStry,"
Reinhold Publishing Corp., New York., 1939.
In automotive and other applications where the power
source is known to contain significant transient voltages, the
internal regulator on the LM1830 allows protection to be
provided by the simple means of using a series resistor in
the power supply line as illustrated in Figure 4. If the output
load is required to be returned directly to the power supply
because of the high current required, it will be necessary to
provide protection for the output transistor if the voltages'
are expected to exceed the data sheet limits.

In the case of inductive loads or incandescent lamp loads, it
is recommended that a filter capaCitor be employed.
In a typical application where the device is employed for
senSing low water level in a tank, a simple steel probe may
be inserted in the top of the tank with the tank grounded.
Then when the water level drops below the tip of the probe,
the resistance will rise between the probe and the tank and
the alarm will be operated. This is illustrated in F/{/ure 3. In
situations where a non-conductive container is used, the
probe may be designed in a number of ways. In some cases
a simple phono plug can be employed. Other probe designs
include conductive parallel strips on printed circuit boards.

Conductive Fluids
City water
Seawater
Copper sulphate solution
WeakaQid
Weak base
Household ammonia
Water and glycol mixture
Wet soil
Coffee

A=area of plates (cm2)

Although the LM1830 is designed primarily for use in sensing conductive fluids, it can be used with any variable resistance device, such as light depend8nt resistor or thermistor
or resistive position transducer.
The following table lists some common fluids which may
and may not be detected by resistive probe techniques.

Non-conductlve fluids
Pure water
Gasoline
Oil
Brake fluid
Alcohol
Ethylene glycol
Paraffin
Dry soil
Whiskey

3-221

&I

Typical Applications Vee =

16V

Vee

Vee

1200

1200

~

....,...

LED

ILl....

.

.

13

FlLTtR

GROUND

"

FIGURE 2. Application Using External
Reference Resistor

, FIGURE 1. Test Circuit

Vee
Vee
,1200
a.U1 ..f

15DO

~

LED

.

FILTER

GROUND

"

r~])])
1
PIIDTO'

''':'"

L,D,R,

THE-'R

TRAIIIIITDA

TLIH/S700-4
Output Is activated when Rp Is approximately graaler Ihan % RREF

FIGURE 3. Basic Low Level Warning Device
with LED Indication

.FIGURE 4. Direct Coupled AppllcaUons

3-222

.-----------------------------------------------------------------------------'r
Typical Applications Vee =

....

i:

16V (Continued)

~

Low Level Warning with Audio Output

C)

Vee
, ... a

III

1600

High Level Warning Device
Vee

onlDIIAL

~:~::~:~

470

2.

RESISTOR

D.DD1pF

'4

Vee

TL/H/5700-5

The Output is suitable for driving a sump pump
or opening a drain valve, etc.

3-223

•

~

~

tfI

Nat ion a I S e m i con du c lor, ,,'

LM1946 Over/Under Current Limit Diagnostic Circuit
General Description

•Features

The LM1946 provides the industrial or automotive system
designer with over or under current limit detection superior
to that of ordinary transistor or comparator-based circuits.

• Five independent comparators
• Capable of 20 mA per output
• Low 1l,0000er drain
, • User ~t input threshold voltages
• Reverse batterY protection
• 60V load dump protection on supply and all inputs
• Input common mode range exceeds Vee
• . Short circuiJ protection
• Thermal overload protection
• Prove-out test pin
• Available in plastic DIP and SO packages

Each of the five independent comparators can be !lsed to
monitor a separate load as either an over current or under
current limit detector. Two comparators monitoring a single
load can function as a current window monitor. '
Current is sensed by monitoring the voltage drop across the
wiring harness, pc board trace, or external sense resistor
that feeds the load.
Provisions for compensating the user set limits fo~ wiring
harness resistance variations over temperature and supply
voltage variations are also available.
When a limit is reached in one of the comparators, it turns
on its output which can drive an external LED or microprocessor.
One side of the load can be grounded (not possible with
ordinary comparator designs), which is important for automotive systems.
'

Applications
• Lamp fault deteptor
• Motor stall detector
• Power supply bus mOnitoring

Typical Application Circuit-Lamp Fault Detector (Il > 1A)

R6

lK
Vre!

',!set ,

__...-....1TEST

I-=

OFF fOR ILAMP > 1AMP
ON FOR ILAIIP< lAMP
R5
30K

Wv-4

GND

TL/H/8707-2

FIGURE 1

3-224

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee and Input Pins)
Survival Voltage (T s: 100 ms)
Operational Voltage

Output Short Circuit to Ground or Vee

- 400C to + 85·C

Maximum Junction Temperature

+ 1500C
-65·Cto + 1500C

Storage Temperature Range

-50Vto +60V
9Vto26V

Internal Power Dissipation (Note 1)

Continuous

Operating Temperature Range (TA)

Lead Tempereture (Soldering. 10 sec.)

+ 2600C

ESD Susceptibility (Note 3)

Internally Umited

600V

Electrical Characteristics 9V s: Vee s: 16V.lset = 20 p.A. Tj = 25"C (unless otherwise specified)
Parameter

Conditions

Quiescent Current

All Outputs "Off"

Reference Voltage

= 10 p.A
9V s: Vee s: 16V.lret =

Min

5.8

Iret

Reference Voltage
Une Regulation

=

10/LA

20 p.A

Iset Voltage

lset

Input Offset Voltage

At Output Switch Point. Vo
9V s: VCM s: 16V

1.20

Input Offset Current

IIN(+~ - IINt-).9V

Input Bias Current

IIN(+) or IIN(-). 9V

=

2V

s: VCM s: 16V
s: VCM s: 16V

Input Common Mode
Voltage Range

18.00

Typ

Max

Units

1.40

3.00

mAclc

6.4

7.0

Vdc

±5

±50

mVdc

1.40

1.60

Vdc

±1.0

±5.0

mVdc

±0.10

±1.00

p.~c

20.00

22.00

P.Adc

26.0

Vdc

4.00

Maximum Positive
Input Transient

Either Input. T

s:

100 ms

Maximum Negative
Input Transient

Either Input. T

s:

100 ms

Output Saturation
Voltage

= 2 rnA. 9V s: Vee s: 16V
= 10 mAo 9V s: Vee s: 16V
Vo = 0Ydc. Comparator "ON"

Output Short Circuit
Current

60

70

V

-50

-60

V

10

0.80

1.00

Vdc

10

1.00

1.20

Vdc

45

120.0

mAoo

0.01

1.00

p.Aoo

1.25

2.00

Vdc

=

20

OVdc' Comparator "off"

Output Leakage Current

Vo

Test Threshold
Voltage

At Switch Point on Any Output
Vo = 2V (Note 2)

0.80

Test Threshold
Current

,.

0.2

~c

Note 1: Thermal resistance from junction to ambient Is typically 53"C/W (beard mounted).
Note 2: The test pin is an active high input, i.e. all five will be forced high when this pin is driven high.
Note 3: CESO

~

100 pF, RESO

~

1.5k

I

•

..

I
!

I

3·225

CD

~

....

::Ii

Connection Diagram
+

'20: '

In 1

OUTPUT 1

\".'

+
In 2

+
,In 3

3
19

4

OUTPUT 2

5
18

OUTPUT 3

6

Vee
VREF

ISET

+
In 4

GROUNO '

-

7
8

13

+
In 5

12
10

OUTPUT 4

,OUTPUT 5

11

TEST/RESET
TLlH/8707-20

Order Number LM1946N or LM1946M
See NS Package Number M20B or N20A

Typical Test Circuit
gV~Vee~16V

OUTPUT
SECTION

Your

REFERENCE
SECTION

VREF (5V)

TLlH/8707 -23

Simplified Comparator Schematic
-INPUT

+ INPUT '

TLlH/8707 -24

3-226

Typical Performance Characteristics
Quiescent Current
vsVee

VsatVSlo

Quiescent Current

va Vee

5

2.0
1.11

o
o

!

....-

....- ---

~

4

r~ l-

I

i

I

-

~I"'"

-6
10

15

211

10

25

lauI(mA)

16

-so -30

2.0

--

1.8

-

..........

...., . /

40

0

110

120

~

-.41)04011012111110

1110

lIWP(OC)

lIWP("C)

lset vs Temperature

Iset vs Temperature
50

50

R3=27OK
Rhoo

40

40

iIO

-

20
10

o

-

___ I"'"

!

1

110

1201110

Iset vs Temperature
50

R3=oo
R4=570K
Ycc=l2Y

iIO

iIO

20

211

10

10

0

..41)040

..41)

0

n:wP(OC)

40

110

120

R3=510K
R4=1.IM
Ycc=l2Y

-

~

o

-.41)04011012111110

1110

lIWP(OC)

lIWP(OC)

Test Threshold

1.4

III

Common Mode Lower Limit
i

1.8

1.2

50

71l

....

~

..41)

iIO

7.4

....

"

0

10

Vref VS Temperature

211
10

-10

Ycc(voIIs)

Vset va Temperature

Peak 10 vs Vee

-

14

Ycc(voIIs)

110

50

12

-

..;....

- -

i-"'"
~

.........

./

o.s
2.0
-.41)04011012111110

-40

lIWP(OC)

0

40

110

1211

1110

lIWP(OC)
TL/H/8707-4

3-227

Application Hints
THEORY OF OPERATION: UNDERoCURRENT LIMIT
DETECTOR,

+

TUH/8707-6
Lamp Fault Datector

,"

.1,"

FIGURE 3. Equivalent Automotive Lamp Circuit
The diagram of Figure 3 represents the typical lamp circuit
found in most automobiles. Switch S1 represents a cJ8sh-' .
board switch, discrete power device, relay and/or flasher
circuit used for tum signals. Sense resistor Rs can be an
actual circuit component (such as a 0.1 n 1W carbon resistor) or it.ean represent the resistance of some or all of the
wiring han1ess. The load, represented here as a single bulb,
can just as easily be two or more bulbs in parallel, such as
front and rear parking lightl;, or left and right highbeams, etc.
One of the easiest methods to electronically monitor proper
bulb operation is to sense the voltage developed across Rs
by the bulb current IL. If a fault occurs due to an open bulb
filament, the load current, and sense voltage Vs, drop to
zero (or to half their former values in the case of two bulbs
wired in parallel). A comparator circuit can then monitor this
sense voltage, and alert the system or system user (e.g.
power an LED) if ,this sen~ voltage drops below a predeter- ,
mined level (defined as the threshold voltage).
'
Typical sense voltages range from tens'to hundreds of millivolts. Not only does this sense voltage vary nonlinearly with
the battery voltage, it may vary significantly with ambient
temperature depending on the temperature coefficient (TC)
of the sense resistor or wiring hamess. Since these, nonlinear characteristics can' vary from system to system, and
sometimes even within a singh,; system, provisions must be
made to accommodate them. There are two general methodologies to, accomplish this.
The first method uses only one bulb per monitoring Circuit. A
sense resistor is selected to give 50-100 mV of sense voltage in an operational circuit, and a comparator threshold
detecting voltage of approximately 10 mV is set. Even if
component tolerances, battery line variations, and temperature coefficients cause 'the sense voitSge to vary 3:1 or
more, circuit operation will'not,be affeCted.
'
The second method must be used if two or more bulbs are
wired in parallel and it is necessary to detect if any single
lamp fails. This is often desirable as'l,it reduces the number
of comparators and displays and system· cost by at least a
factor of two. In this case, the sense voit8ge will drop by
only half (or less) of it's original value. For example,"a nominal 100 mV drop across the sense resistor will drop to
50 mV if one of two bulbs faiL Therefore, Ii threshold detection voltage between 50 and 1,00 mV is required (sirlee a

10 mV threshold would alert the system only if both bulbs
faill'l.lI). Yet a fixed threshold of 75 mV may not work if the
Il9minal100 mV sense voltage can vary 3:1 due to the factors mentioned earlier. What is required is a Comparator with
a threishold-detecting voltage that tracks the nominal sense
voltage as battery line and ambient temperature change.
Thus"while the sense vo~ge may nominally be anywhere
from 50 to 150 mV, the threshold voltage will always be
roughly 75% of it, or 37 mV to 112 mV, and wiH detect the
.
failure of either of two. bulbs.
The LM1946 integrated circuit contains five Comparators espeCially designed for lamp monitoring requirements. Since
all lamps in a system share the same battery voltage and
ambient temperature, accommodations for these variations
need to be made only once at the,IC, and each threshold of
the five comparators then tracks these variations.
SETTING THE COMPARATOR THRESHOLO VOLTAGE
The threshold voltage at which the campllfator output
changes state is user-set in order to accommodate the
many possible system designs. The input bias currents are
purposely high to accomplish this, and are each equal to the
user-set current into the lset pin (more Oil this later). Typically around 20 pA, the effect of this across the sense resistor Rs compared to a typical load measured in amps is negligible and can be ignored. However, when 'resistors R1 and
R2 (Figure 4) are added to the circuit, a shift in tlie threshold
voltage is effected. This oCcurs since each input has been
affectlld by different IR drops. The LM1946 behaves like
any other comparator iii that the output switches when the
input voltage at the IC pins is zero millivolts (ignoring offset
voltage for the moment). If the output therefore has just
switched states due to just the right threshold voltage
across the sense resistor, then the sum of voltages around
the resistor loop should equal' zero: '

51

Rl

Ise\"Rl

lis

, COMPARATOR
outPUT

VlHRSHLD
R2

Ise\" R2
LOAD

TUH/8707-9
Vlhrshld

= Isst (Rl

FIGURE 4.lnpllt Bias Current
Vthrshld + ,Iset. R2 - Voffset - lset. R1 = 0
Assuming Voffset -< "thrshld:
Vthrshld = lset,. R1 - Iset. R2
Vthrshld = lset (R1 - R2)

- R2)

Application Hints (Continued)
Vret5.0mV). It is this requirement
that guarantees that the output will not be in an erroneous
high state upon power-up or whenever S1 is closed. (Should
this feature be unnecessary to a particular application circuit, the methqdology describ6d can be replaced with a simple capacitor across the comparator input pins).

Rl

.,~~
R2a
3.9K

R2b
1.2K
TLlH/8707 -16

a. Open-Circuit Detector
RIa

RIb

5.1K

lK

R5~

O.14~
R2
lK

TLlH/8707 -17

b. Over-Current Limit Detector
FIGURE 16. Input Noise FIRers for
Various Application Circuits

II

L1

Rl
lK

R5
L2

c:

II

lK

lK

10K

*o~'·
.. .... =f0~;~
--~
'
lK

R2

5.1K
TL/H/8707-18

FIGURE 17. Additional Noise Filters

•
3-233

LM1946
0
:::;'

Vee

17

0

n

c

~

en
n

::r
CD

3
I»

C)"

Vour
0

181319
12

20

'"
'"

II JJd26 J~i IJ= fo30 t 7.37 ~

N

I JI I

=b!,16

:7

I

.jIo.

TESTPINll~

GND
14
Tl/HIS707-3

FIGURE 18

I

r-------------------------------------------------------------------------,~

....
~

I:

I!J1National Semiconducto.T

LM1949 Injector Drive Controller
General Description

Features

The LM1949 linear integrated circuit serves as an excellent
control of fuel injector drive circuitry in modern automotive
systems. The IC is designed to control an external power
NPN Darlington transistor that drives the high current injector solenoid. The current required to open a solenoid is several times greater than the current necessary to merely hold
it open; therefore, the LM1949, by directly sensing the actual solenoid current, initially saturates the driver until the
"peak" injector current is four times that of the idle or "holding" current (F/{Jure 3-F/{Jure 7). This guarantees opening
of the injector. The current is then automatically reduced to
the sufficient holding level for the duration of the input
pulse. In this way, the total power consumed by the system
is dramatically reduced. Also, a higher degree of correlation
of fuel to the input voltage pulse (or duty cycle) is achieved,
since opening and closing delays of the solenoid will be
reduced.

•
•
•
•
•
•
•
•
•
•
•
•
•

Normally powered from a 5V ±10% supply, the IC is typically operable over the entire temperature range (-55"C to.
+ 125°C ambient) with supplies as low as 3 volts. This is
particularly useful under "cold crank" conditions when the
battery voltage may drop low enough to deregulate the
5-volt power supply.

Low voltage supply (3V-5.5V)
22 mA output drive current
No RFI radiation
Adaptable to all injector current levels
Highly accurate operation
TTL/CMOS compatible input logic levels
Short circuit protection
High impedance input
Externally set holding current, IH
Internally set peak current (4 x IH)
Externally set time-out
can be modified for full switching operation
Available in plastic B-pin miniDIP

Applications
•
•
•
•

Fuel injection
Throttle body injection
Solenoid controls
Air and fluid valves
• DC motor drives

The LM1949 is available in the plastic miniDIP, (contact factory for other package options).

Typical Application Circuit

.I
I
I
I
I
I

SENSE
5 GND

TL/H/5062-1

FIGURE 1. Typical Application and Test Circuit
Order Number LM1949M or LM1949N
See NS Package Number M08A or N08E

3-235

•

.or-----------------------------------------------------------------------------,
Q»

9'"

::IE

....

Absolute Maximum Ratings

It Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Oftlce/Dlatrlbutors tor availability and speclflcatlons.
Supply Voltage
8V
Power Dissipation (Note 1)
1235mW

Input Voltage Range
Operating Temperature Range
Storage Temperature Range
Junction Temperature' ,
Lead Temp. (Soldering 10 sec.)

..iO.3Vto Vee
-4O"C to +U!5"C
-65·Cto +15O"C

-

1500C
2600C

Electrical Characteristics (Vcic=5.5V, V'N=2.4V, Tj=25"C, Figure 1, unless~therwise specified.)
Symbol
, lee

COnditione

Paremater
Supply Current
Off
Peak
Hold

Typ

Y,N = OV
Pin & = 0\1
Pin 8 Open

11
28
16
1.4
1.2

VOH

Input On Level

Vee = 5.5V
Vee = 3.0V·:

VOL

Input Off Lwei

Vee = 5.5V
Vee = 3.0V

Ie

Input Current .

,.

lOp

Output Current
Peak
Hold

"

Min

~i!l'8 = OV
Pin 8 Open

Vs

Output Saturation Voltage

10mA,V'N=.OV

Vp
VH

Sense Input
Peak Threshold
Hold Reference

Vee'= 4.75V

t

Time-out, t

HRM

1.0
0.7

1.35
1.15

-25

3

-10
-1.5

-22
-5

23
54.
26

'.

rnA
rnA
rnA

2.4
1.6

V
V
V
V

-1:25

p.A

rnA
mA

0.2

0.4

88

386
94

' 415
102

90

,,100

110

350

Units

V
mV
mV

%

NOTE 1: For operation in ambient temperatures allow 25"C, the device must be derated basad on a 15O'C maximum junction temperature and a thermal
resistance of 10CY'C/W junction to ambient

Typical Circuit Waveforms
BAmRY VOLTAIE

Vun

IV)

11M
"11

V8LTABE

IW ______~~~~~----~
IOV
ImAL BATTERY VOLTAIE
"t:OI.D CRAlK- til LOW BAmRY VlLTAGE
W

I

IV

IV)

W
IV...-J

IEllE I.PUT
VOLT~

TilER
PIli

. V8LTABE
IV)

Vz

QIV~W:a~

liIV

OV

\.
TUH/5062-2

3-236

7C)-

W

.~ ~

V"

RII

R7~

:r
CD
3

-

R3

Hi

KGI

rtlij

Q5

---:J

1....1125

I»

C;'

o

Q4

-) ·1 ITt I

~'

14

Dl
3

HZ

HVJ

TIMER

~

Q8

Q8

OS

Q~

I

rR33

RII

t

II

112!

RII I
115

~'

1-_.....'IoR""13

PJtj
R7

R.t-t I

~I
[R171

m

OSI

II

OOMP

H2O

.~

RII

~

1311

.~:
f
-. SUPPlY
GROUND

65

~7
'--------..I.

.>
R34

H

2

1

SElIE 04
Tl/H/5062-3

FIGURE 2. LM1949 Circuit

6t6Un

iii

Typical Performance Characteristics
Quiescent Current vs
Supply Voltage
30

12

125
!i

V11= DY
110 TI=25'C

=
g
=

i

~
~

./

o

If

0

o

1

SUPPlY VOLTAGE tvl

;;;400

E3.0 TI=25'C

. '-

.1.0
=

~ IiOH

~

,- ..... .....

i.. 3lO
...al3B&

I

1lI37D

5"1085

112

il.O1

110

!

.....

1.00
./

I:
Ii! .17

~

o

1

I

o

1

3

,c=u,

i•

Vee =IlDY

a

.'

5

o

Vct;=3.OV

I

a

30 BD 10 120 1&0

15~+-4-~-+~~~d

~ 10 rT=!==F~B:3
g 51-t-+--+

a 3D 80 90 120 1&0
JUNCnON TEMPERATURE I'CI

-80 -30

Input Voltage Thresholds
vs Junction Temperature
3.5

-

I I

-80.aD 0 30 10 10 120 1&0
JUlcnOI TEMPERATURE I'CJ

12.5
...iu -! C· UV
!1.1 - ON

§!1.O

...

Sense Input Peak Voltage
vs Junction Temperature
;;;405
.1.400

1113.0

'" 15
pjC~b~=
3.0
10..
~ 10 Vee"
1. IVee=UV H LD 0;;;::

..

I

=

JUNCnON TEMPERATURE I'CI

E

120 ~K

-r--

=25
I.. 20 r.:--I-:~-.I:-~"'="-1f-+--I
OL-.l--~..L-...l-...L--L......J

·80.so

_3D

2 3 4
5
SUPPLY VOLTAGE IYI

1 30

V•• =DY

... 8

Output Current vs
Junction Temperature

!25
•

1

3&r-r--r-,-,-,....-,--,

14

4

o

Quiescent Supply Current
vs Junction Temperature

Quiescent Supply Current
vs Junction Temperature

SUPPLY VOLTABE IYI

3&

2
3 4
5
SUPPlY VOLTAGE tvl

I;

j

\

~ID

SUPPlY VOLTAGE IYI

9i

!!pOO

:195
...
!!

Normalized Timer Function
vs Supply Voltage
E1.D3
TI'25'C
11.G2

TI,25°C

!101

.....

--

Sense Input Hold Voltage
VB Supply Voltage

!!

0123451

"""" VOLTAlE tvl
SUPPlY

-

0123458

1110

E380
1 375

511.5

o

o

2 3 4
5
SUPPLY VOLTAGE IVI

==
01

HOLD

I

TI"25'C

!385

;2.0

I

Sense Input Peak Voltage
vs Supply Voltage

Input Voltage Thresholds
vs Supply Voltage

;2.5

PEAK-

HOJ

l..' I

0123458'

II

I

I

15

TI=25'C

P~ ~

120

i

35

I

V.N' rAV,
TI=n'e

1'8 :

,;'

•::1.&

Output Current vs
Supply Voltage

Supply Current vs
Supply Voltage

-OF

!385

§! • ~ ~

ON

l:

OFF

I. -

VCC = 3.DV

~11.5

a

~385

1375

111370

-80 .so a 3D 110 10 120 1&0
JUNCnON TEMPERATURE I'CJ

·10

" ~u~ 1'-00..

Vce ·3.DY

Vce =

'II

......

:""0

......

......
.ao a 30 BD 90 120 150
JUNCTION TEMPERATURE I'CI
TUH/5062-4

3-238

r-----------------------------------------------------------------------------, !I:rTypical Performance Characteristics
Sense Input Hold Voltage
vs Junction Temperature
_115

E

~105

9~ 10095
....:::>
~

i

90

-

1.04

I
I i

~

Vcc " 3.0V

i

I

r- rs

!

85
80
-60·30 0 30 60 90 120 150
JUNCTION TEMPERATURE I'CI

~ 1.00
~

!:I .99
c

I
I

I

~ 1.01

Vcc " 5.5V

LM1949N Junction
Temperature Rise Above
Ambient va Supply Voltage

Normalized Timer Function
vs Junction Tempereture

! 1.03
~ 1.02

:- 110

....

(Continued)

~

VCC" 3.0V

...J-.l-

1·9a

i

i

14

I

:

Vcc . 5.5V

~

!

I--

I

!
t t
.97
·60 -30 0 30 60 90 120 150
JUNCTION TEMPERATURE I CI

o

_90'10 DUTY
ICYC~

.JI'"

"""i~~WY
CYC E
~

01234567
SUPPLY VOLTAGE IVI
TlIH/5062-5

Application Hints
The injector driver integrated circuits were designed to be
used in conjunction with an external controller. The LM1949
derives its input signal from either a control oriented processor (COPSTM), microprocessor, or some other system. This
input signal, in the form of a square wave with a variable
duty cycle and/or variable frequency, is applied to Pin 1. In
a typical system, input frequency is proportional to engine
RPM. Duty cycle is proportional to the engine load. The circuits discussed are suitable for use in either opan or closed
loop systems. In closed loop systems, the engine exhaust is
monitored and the air-to-fuel mixture is varied (via the duty
cycle) to maintain a perfect, or stochiometric, ratio.

age and the saturation voltage of 01' The drop across the
sense resistor is created by the solenoid current, and when
this drop reaches the peak threshold level, typically 385 mV,
the IC is tripped from the peak state into the hold state. The
IC now behaves more as an op amp and drives 01 within a
closed loop system to maintain the hold reference voltage,
typically 94 mV, across Rs. Once the injector current drops
from the peak leval to the hold level, it remains there for the
duration of the input signal at Pin 1. This mode of operation
is preferable when working with solenoids, since the current
required to overcome kinetic and constriction forces is often
a factor of four or more times the current necessary to hold
the injector open. By holding the injector current at one
fourth of the peak current, power dissipation in the solenoids and 01 is reduced by at least the same factor.

INJECTORS
Injectors and solenoids are available in a vast array of sizes
and characteristics. Therefore, it is necessary to be able to
design a drive system to suit each type of solenoid. The
purpose of this section is to enable any system designer to
use and modify the LM1949 and associated circuitry to
meet the system specifications.
Fuel injectors can usually be modeled by a simple RL circuit.
Figuf6 3 shows such a model for a typical fuel injector. In
actual operation, the value of Ll will depend upon the status
of the solenoid. In other words, Ll will change depending

In the circuit of Figuf6 1, it was known that the type of injector shown opens when the current exceeds 1.3 amps and
closes when the current then falls below 0.3 amps. In order
to guarantee injector operation over the life and temperature range of the system, a peak current of approximately 4
amps was chosen. This led to a value of Rs of 0.10. Dividing the peak and hold thresholds by this factor gives peak
and hold currents through the solenoid of 3.85 amps and
0.94 amps respectively.
Different types of solenoids may require dHferent values of
current. The sense resistor Rs may be changed accordingly.
An 8-amp peak Injector would use Rs equal to .050, etc.
Note that for large currents above one amp, IR drops within
the component leads or printed circuit board may create
substantial errors unless appropriate care is taken. The
sense input and sense ground leads (Pins 4 and 5 respectively), should be Kelvin connected to Rs. High current
should not be allowed to flow through any part of these
traces or connections. An easy solution to this problem on
double-sided PC boards (without plated-through holes) is to
have the high current trace and sense trace attach to the
Rs lead from opposite sides of the board.

Tl/H/5062-6

FIGURE 3. Model of a Typical Fuellnlector
upon whether the solenoid is open or closed. This effect, if
pronounced enough, can be a valuable aid in determining
the current necessary to open a particular type of injector.
The change in inductance manHests itself as a breakpoint in
the initial rise of solenoid current. The waveforms on Page 2
at the sense input show this occurring at approximately 130
mV. Thus, the current necessary to overcome the constrictive forces of that particular injector is 1.3 amperes.

TIMER FUNCTION
The purpose of the timer function is to limit the power. dissic
pated by the injector or solenoid under certain conditions.
Specifically, when the battery voltage is low due to engine
cranking, or just undercharged, there may not be sufficient
voltage available for the Injector to achieve the peak current. In tl:Je Figure 2 waveforms under the low battery condition, the injector current can be seen to be leveling out at 3

PEAK AND HOLD CURRENTS
The peak and hold currents are determined by the value of
the sense resistor Rs. The driver IC, when initiated by a
logic 1 signal at Pin 1, initially drives Darlington transistor 01
into saturation. The injector current will rise exponentially
from zero at a rate dependent upon Ll, Rl, the battery volt-

3-239

•

Timer Function (Continued)
amps, or 1 al1:lp below ,~he normal threshold. Since continuous ope~tio,ri '~t 3,a~ps mill( overheat the injectors, tl;le
timer. funCtion on the IC will force the transition into the hold
state after one, time Constant (the time constant is equal to' ' '
RA). The timer is reset at the end of each input pUlse. For
systems where the timer function is not needed, it can be
disabled by grounding Pin 8. For systems where the initial
peak state is not required, (i.e., ~re the soleQoid current
rises immediately to the hold level), the timer can be used to
disable the peak function. This is done by setting the time '
constant equal to, zero, (i.e., Or = 0). Leaving RT in place is ,
recommended. The'timer will then complete its time-out and
disable the peak condition before the solenoid current has
had a chance to rise abOve the hold level.
The aCtual range of the timer in injection systems will probably never vary much from the 3.9 milliseconds shOwn in'
Figure'1. However, the actual useful range of the timer extends from microseconds to seconds, depending on the
component values chosen. The useful range of RT is approximately, 1k to 240k. The capacitor CT is limited only by
stray capacitances for low, values and by leakages for large
values.
The capacitor reset time aUhe end of each controller pulse
is determined by the supply voltage and the capacitor value.
The Ie resets the capacitor to an initial voltage (VeE! by
discharging it with a current of approximately 15 mA., Thus,
a 0.1 ,...F. cap is reset in approximately, 25 ,...s.
;,'

L
,
,

INPUT VoLTAGE'
PIN 11'1

':"

I

.

4
3
2
I
0

INJECTOR

CURRENTIAI

1

I,
'I

I
1

I

4
3
2

CURRENT IiI

1

.1
I

1

I
I
I

I
II

4 I
I

I
I

I
I

2

I

1

I

.

, 0 I
v~.:

Qi COUECTOR
VOLTABEM,
,

'

I

.

:

3 l lI"
L. J L
:
I

ZENER

CURRENT IAI

,

oI

I'

.

I.

'
"I

r

III

I

I',

,
.

I

BATT

I

o
Tl/H/5062-7

COMPENSATioN
>
Compensalion of, the ,error amplifier prOVides Iltability'tor the
9ircuit during the hold state. ,ExtE!rnal compensation (from
Pln 2 to Pin 3) allows each design to be tailored for the
charecteri~s oUl:1e system andlor 'YPE! of Darlington power, devk;e used. In the ,vast ~ority of designs, the val\le or
type of the compensation caPacitor is,nClt critical. Va,lues of
100 pF to 0.1 ,...F wol"k well w~h the cirCUit of Figu(8 1. The
value shOwn of .01 ,...F (diSC) provides $ close optimum in
choice between lilconomy, sPeed, I!n,:l nOI~ immunity. In
systems, inereased, phase and' gain margin may be
ac;q\lired by bypassing the' cOllector of 01 to grOUnd with an
appropriately rated 0:1 ,...F. capaci~r: This is, hQw~r, rarelY
necessary.
'
'

FIGURE 4. Clrcul.tWaveforma

amplifier keeps 01 off until the injector current has decayed
to the proper value. The disadvantage of this particul,ar configuration is that the ungrounded zener is more difficuh to
heat sink if that becomes neceSsary.
' .
The Second purPQS8 of Zl is to prOVIde system transient
protection. Automotive systems are susceptible' to a vast
arrey of voltage trans~nts on tl14i1 b~ttery line. ThOugh their
duration is usually only millisecqnds long, '0,1 could suffer
permanent damage unless buffered by thEi injector and Zl.
This is orie reason why a zener is preferrEid over a clamp
diode back to the battery line, the other reason being long
d~cay ~mes.
.
,

some

'BATT .

FLYBACK ZENER
The purpose of zener Zl is twofold. Since the load is inductive, a voltage spike is produced at the collector of 01 anytime the injector current is reduced. 'This occurs at the peakto-hold transition, (when the current is .reduced to one fourth
of its peak value), and also at the end of each input pulse;
(when the current is reduced to zero). The zener provides a
current path for the inductive kickback; limiting the voltage
spike to the zener value and preventing 01 from damaging
voltage levels. Thus, the rated'zener voltage at the 'system
peak current must be less than the guaranteed minimum
breakdown of 01: Also, even while Zl is cdnducting the
majority of the injector cUITent during the peak-to-hold transition (see Figure 4), 01 is operating at the hold current
level. This fact is easily overlooked and, as described in the
follOwIng text, can't!9 corrected if necessary. Since the error
amr;lifier in the ic demands 94 mV across Rs, 01 wil.be
biased to p'tOliide exactly that. Thus; the safe operating ai'eil
(SOA) of 01' must inClUde the hOld cur.rent with a 'Vee of Zl
volts; For' systems where this is not desired, the zener ari::
citlEi may bE! 'reconneCted to thatep of Rs'as shown in Fi{jure 5. Since the voltage across ti'i$ sense resistor nOw accurately portrays the injector current at all times, the error

--.,I
I

ILl

IINJECTOR
I
I

'

--"'"

-"

TUH/5062-8

FIGURE 6. Alternate Conflguratlon for Zener Z1

3-240

r-----------------------------------------------------~~

...

POWER DISSIPATION
The power dissipation of the system shown in F/{Jure 1 is
dependent upon several extemal factors, including the frequency and duty cycle of the input waveform to .pin 1. Calculations are made more difficult since there are many discontinuities and breakpoints in the power waveforms of the
various components, most notably at the peak-to-hold transition. Some generalizations can be made for normal operation. For example, in a typical cycle,of operation, the majority of dissipation occurs during the hold state. The hold state
is usually much longer than the peak state, and in the peak
state nearly all power is stored as energy in the magnetic
field of the injector, later to be dumped mostly through the
zener. While this assumption is less accurate in the case of
low battery voltage, it nevertheless gives an unexpectedly,
accurate set of approximations for general operation.

The LM1949 can be easily modified to function as a switcher. Accomplished with the circuit of F/{JUre 7, the only additional components required are two external resistors, RA
and Rs. Additionally, the zener needs to be reconnected, as
shown, to Rs. The amount of ripple on the hold current is
easily controlled by the resistor ratio of RA to Rs. RB is kept
small so that sense input bias current (typically 0.3 mAl has
negligible effect on VH. Duty cycle and frEiquency of oscillation during the hold state are dependent on the injector
characteristics, RA, Rs, and the zener v91tage as shown in
ttie following equations.
,
VH
Hold Current :::: Rs

The following nomenclature refers to Figure 1. Typical values are given in parentheses:
Rs

=Sense Resistor (0.10)

VH

=;' Sense

Minimum Hold Current ::::

Input Hold Voltage (.094V)

Vp

=Sense Input Peak Voltage (.385V) "

Vz

= Z1 Zener Breakdown Voltage (33V)

VBATT

= Battery Voltage (14V)

L1

= Injector Inductance (.OO2H)

R1

= Injector Resistance (1 n)

n

= Duty Cycle of Input Voltage of Pin 1 (0 to 1)

f

= Frequency of Input (10Hz to 200Hz)

Ripple or

+ VH2)

«VZ-VSATT) e Rs

RB
1
Hold:::: - e Vz e RA
RS

VBATT
-v;-

Duty Cycle of fo ::::

Component Power Dissipation
VSAT
Po:::: n e ( 1 -VBATT)
- - e--eVH
Vz
Rs
VSAT = 01 Saturation Volt @ - 1 Amp (1.5V)

VH
Po :::: n e VBATT • Watts
Rs
Zener Dissipation:

(Vp2

~I

(VH- :Bevz)
R:

fo :::: RS e RA e VSATT e (1 _ VBATT)
L1 RS
Vz
Vz
fo = Hold State Oscillation Frequency

01 Power Dissipation:

Pz :::: Vz e L1 e f e

!

Pz ::::

2) Watts

VSATTeVH

n e -=":':R-=-s-'"

VseVz
PRA::::--R1
As shown, the power dissipation by 01 in this manner is
substantially reduced. Measurements made with a thermocouple on the bench indicated better than a fourfold reduction in power in 01. However, the power dissipation of the
zener (which is independent of the zener voltage chosen) is
increased over the circuit of F/{Jure 1.

Injector Dissipation:
VH 2
PI :::: n e R1 e Watts
RS2
Sense Resistor:
VH2
PR :::: n"'""'2 Watts
Rs

Vp2

PR (worst case) :::: n RS2 Watts
5V
SWITCHING INJECTOR DRIVER CIRCUIT

INPUT VOLUIE
PilI IV)

The power dissipation of the system, and especially of 01,
can be reduced by employing a switching injector driver circuit. Since the injector load is mainly inductive, transistor 01
can be rapidly switched on and off in a manner similar to
switching regulators. The solenoid inductance will naturally
integrate the voltage to produce the required injector current, while the power consumed by 01 will be reduced. A
note of caution: The large amplitude switching voltages that
are present on the injector can and do generate a tremendous amount of radio frequency interference (RFI). Because
of this, switching circuits are not recommended. The extra
cost of shielding can easily exceed the savings of reduced
power. In systems where switching circuits are mandatory,
extensive field testing is required to guarantee that RFI cannot create problems with engine control or entertainment
equipment within the viCinity.

OV
4OO111V -

/

SENSE INPUT VOlTAlE
PlI4(mVJ
OV

Vz
VIATT

01 COUECTOR
VOLTAIE IV)

,

-

-

....

b

OV
TUH/5062-9

FIGURE 6. Switching Waveforms

3-241

•

+IF.:.:.:.......-o() vCc~ 5V
Z1
33V

5W

, . SENSE

5 GND

TUH/5062-10

FIGURE 7. Switching Application Circuit

3-242

t!lNational Semiconductor

LM9044 Lambda Sensor Interface Amplifier
General Description
The LM9044 is a precision diff~rential amplifier specifically
designed for operation in the automotive environment. Gain
accuracy is guaranteed over the entire automotive temperature range (-40"C to + 12S0C) and is factory trimmed prior
to package assembly. The input circuitry has been specIfically designed to reject common-mode signals as much as
3V below ground on a single positive' power supply. This
facilitates the use of sensors which are grounded at the
engine block while the LM9044 itself is grounded at chassis
potential. An external capacitor sets the maximum operating
frequency of the amplifier, thereby filtering high frequency
transients. Both inputs are protected against accidental
shorting to the battery and against load dump transients.
The input impedance is typically 1 MO.
The output op amp is capable of driving capacitive loads
and is fully protected. Also, internal circuitry has been pro-

vided to detect open circuit conditions on either or both inputs and force the output to a "home" position (a ratio of
the external reference voltage).

Features
• Normal circuit operation guaranteed with inputs up to
3V below ground on a single supply
• Gain factory trimmed and guaranteed over temperature
(±3% of full-scale from -4O"C to +125"C)
• Low power consumption (typically 1 mAl
• Fully protected inputs
• Input open circuit detection
• Operation guaranteed over the entire automotive temperature range (-40"C to + 12S0C)
• Single supply operation

Schematic and Connection Diagrams
r-~--~-r--~--~---;----+----+---;--~~--~-1~---[]~

-Vtto

+YIo

~--~----~------------------~--------~--~~------~-----[]UD
TLlH/6744-1

Plastic Chip Carrier Package

-=

5

17vCC

• 8

. 18.

NOII-~ 7

.'5Ry

• 8

14.

i;r;:;r-m-';';I""l'Ir
'Pins',3,4,6,8,9,lO,l',13,14,16,l8, 19 are
lrim pins and should be left floating.

3-243

Order Number LM9044V

see NS Package Number V20A

'.
•

r---------------------------------------~----------------------------------------,

8

Absolute Maximum Ratings

:!

If Military/Aerospace specified devices are reqiilr8cl.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Vee Supply Voltage (RVee
VREF Supply Voltage

=:

15 kfi)
'.

DC Input Voltage (Either Input)

, Operating Temperature Range '

- 3V to + 16V
± 60V

~?We~ Dissipation (see Note 6 ) , . '

1350 mW

OUtput Short Circuit Duration

Indefinite

-65"0' to'~ 150"C

Soldering Information
"
PIIlSIiq C"ip ~ p"ckage
;
Vapor Phase (60 seconds)
215"C
Infrared (15 seconds)
, ' ,,220"C
See AN-450 "SurfaCe Mounting MEithods and THeir Effect
on Product Reliability" fOr other methods of soldering sur"
, ,faceinount devices: '

± 60V
-0.3V to +6V

Input Transients (Note 1)

1...-,40"C,t6<;* 125"C

Storage Temperature Range

Electrical Characteristics Vee:it 12V; VREF ";'5V.-4O"C:S: TA':s: 125°C unless otherwise noted
Parametar,

(Note 2) , " ( N o t e 3)

Conditions'
'1.

,'.

Min

Typ

Differential Voltage Gain

VOIF=o>O.5V
-1V:S:VCM:S: + 1V

4.41,

4.50

Galn Error (N~e 5)

O:S:VOIF:S:1V
-1V:S:VCM:S:+1V

-'2

o

lib

Min

-3
,0.95

1.20,

±0.38

-25

O:s:VOIF:S: 1V
-1V:S:VCM:S:+1V

-65

Vee Supply Current

Vee = 12V. RVee=15k

300

500

VREF Supply Current

4.75V:S:VREF:S:5.5V

0.5

" 1.0

Open Circuit Output Voltage

One or Both Inputs
Open. -1V:S:VCM:S:+1V

Short Circuit Qutput Current
Vee ,Power Supply Rejection
Ratio

%/FS

±0.38

±1.5

Mil

/-LA
-150

'/-LA

rnA
V

50

,dB

0.371

0.397

0.423

Output Grounded

1.0

2.7

5.0

Vee = 12V. RVee= 15K
VOIF=0.5V
,,'

50

65

dB

60

74

dB

0.365

VREF Power Supply
Rejection Ratio

'. \;

4.00

-3

-1
Input Referred "
-1V:S:VCM:S:+1V
VOIF=0.5V

1.20

-45

Common-Mode Voltage:
Range (Note 4)

3

"-100

OV:S:VDIF:S:1V,
-3V:S:VCM:S:+1V

DC Common-Mode
Rejection Ratio

o

±0.65

!lSjVOIF:S:1V',
-3V:S:VCM:S:+1V
Inverting Input Bias Current

VIV

Mil
, 0.70

O:S:VOIF:S:1V
-1V:S:VCM:S:+1V

4.64

,3.00

O:S:VOIF:S:1V
-3V:s:VCM:S: +1V
Non-Inverting Input Bias
Current

4.5Q

%/FS

0:S:VOIF:S:1V,
-3V:S:VCM:S:+ 1V '
O:S:VOIF:S: 1V
-1V:S:VCM:S:+1V

Units
Max

VIV
4.36

Differential Input Resistance

Typ

0.397.

0.429

XVREF

rnA

Note 1: this test is performed with a 10000 source Impedance.
(

Note 2: These parameters are guarantead and 100% production 1est8d.
Note 3: Thase parameters will be guarariteed but not 100% ill'oduc1lon testad.
Note 4: The LM9044 has lINn deaignad to comrnon-mode I!> -3V. but production taatlng i. only performad al ± W.
Note 50 Gain error Is given aa a percent of full-scale. Full-sCale Is definad aa W,at the Input and 4.5V al the output
Note 6: For operation in ambient temperatures above 25'C ,the davios must be' derated besad on a maximum junction temperature of 15O"C and a thermal
resistance of IWCIW junction to ambient

3-244

Typical Performance Characteristics
Inverting Input Bias Current
va Temperature

Non-Inverting Input Bias
Current vs T.mperature
a~"~-T~-r~~

150

1125
.'11D

D

it

75

"-

'"

(50

.!..

25

-50 -25 0, 25 50 75 111D 125 150
TEMPERATURE (OCI

Vee Supply' Current vs
Temperature, "

VREF SUpply Current vs
,Teinperature

I1

f-0.4
Ii -

--- -

GO .•

II

0.5

v.!=5~OV

0.8

0.4

'.G= 0.3

i

0.1
-50 -25 0 25 50 75 100 125 150

TEMPERATURE (OCI

DIfferential Gain va
Temperature

4 Current vs Temperature

u

I

2

'"

Vg;=12V

I-RVcc 15k

.. 0.2

Short Circuit Output

I
I
I

-

»

0.2
-50 -25 0 25 50 75 111D 125 150
TEMPERATURE (OCI

1

......

o

OL--L......J'--1......L.....L.....L-L.....J
-50-25 0 25 50 75 111D125 150
TEMl'EllATURE (OCI

1

...... ......

4.TIIII

4.650

1'0 ....

...... .....

14•II1II
......

I:::
f4.a

......

iSUIID

4.350

---

-

i-'"

4.311D
-50 -25 0 25 50 75 111D 125 150
TEMPERATURE (OCI

0
-50-25 0 25 50 T5 111D125 150
TEMPERATURE (OCI

3-245

TLlH/6744-3

•

I

Typical Performance Characteristics (Continued)

..;I

Voltage Gain va Frequency

CMRR v.Frequency
80

111m
iiO

!

10

i

0

CF=hF

1,

CF~'~~P

~. -10

~

10

10lr

lk

~REQUENCY

10k

II!

60 .............

i

40

!

20 t-HiftIIII-+t

I

o 1+f+Hfll-+t

lOOk

10

(Hz)

VREF Power Supply
Rejection

lOOk

80

I.

!:
I

100,
lk
10k
FREOUENCY (Hz)

Vee Power Supply Re/ection

80

I

I+ItfIIII-+t

H+I+IIItI-++

""

,

20 I+ItHHII-+t

.,

, RVec-ll kO
CF-o pF
Vee-12 Vue:

0

-20

lilllll'I~'m1

-20
10

100

lk
10k
FREQUENCY (Hz)

lOOk

10

100

1k

10k

FREQUENCY (Hz)

Test Circuit
Vee
(IV-laV)

VREF

15k

(4.75V-5.50V)

RF

GND
TLlH/6744-5

3-246

lOOk
TL/H/6744-4

iJ1Nafional Semiconductor

LM2907/LM2917 Frequency to Voltage Converter
General Description
The LM2907, LM2917 series are monolithic frequency to
voltage converters with a high gain op amp/comparator designed to operate a relay, lamp, or other load when the input
frequency reaches or exceeds a selected rate. The tachometer uses a charge pump technique and offers frequency
doubling for low ripple, full input protection in two versions
(LM2907-B, LM2917-B) and its outputswings to ground for a
zero frequency input.

Applications
• Over/under speed sensing
., Frequency to voltage conversion (tachometer)

Advantages
•
•
•
•

• Frequency doubling for low ripple
• Tachometer has built-in hysteresis with either differential input or ground referenced input
• Built-in zener on LM2917
• ±0.3% linearity typical
• Ground referenced tachometer is fully protected from
damage due to swings above Vee and below ground

Output swings to ground for zero frequency input
Easy to use; VOUT = fiN X Vee X R1 X C1
Only one RC network provides frequency doubling
Zener regulator on chip allows accurate and stable frequency to voltage or current conversion (LM2917)

Features
• Ground referenced tachometer input interfaces directly
with variable reluctance magnetic pickups
• Op amp/ comparator has floating transistor output
• 50 mA sink or source to operate relays, solenoids, maters, or LEOs

•
•
•
•
•
•
•
•
•

Speedometers
Breaker point dwell meters
Hand-held tachometer
Speed governors
Cruise control
Automotive door lock control
Clutch control
Hom control
Touch or sound switches

Block and Connection Diagrams Dual-In-Line and Small Outline Packages, Top Views
y'

TL/HI7942-1

Order Numbe,r LM2907M-8 or LM2907N-B
See NS Package Number M08A or NOBE

N'

.,

.,

y'

.,

TL/H/7942-2

Order Number LM2917M-8 or LM2917N-B
See NS Package Number M08A or NOBE

N'

N'

N'

TUHI7942-3

Order Number LM2907N
See NS Package Number N14A

N'
TL/HI7942-4

Order Number LM2917M or LM2917N
See NS Package Number M14A or N14A
3·247

Absolute Maximum Ratings (Note 1)

,
Supply Voltage
Supply Current (ZEiiler Optkins)
Collector Vollage
"
'Dlfferentialtlnput Vollage,
;
Tachometer
Op Amp/Comparator
~r

Input Vollage Range
Tachometer LM2907-B, LM2917-B
LM2907; LM2917
Op Amp/Comparator

",2BV
25mA
2BV

.,

,

2BV
2BV
t
±2BV
O.OVto +2BV
O.OVto +2BV

..

:,~,

'.1

.

1200mW
15BO,mW

~4l'PC~ H5"C

"

·c.'

-65"C to + 15O"C

Storage Temperature Rang~
Soldering Information
"Dual-In-Uns Package
Soldering (10 seConds)
Smail Outline Package
Vapor Phase (60 seconds)
' Infiared(15 seConds)

"

"

,

.,
Power Dissipation
LM2907-8, LM2917-B
LM2907-14, LM2917-14
,,, (SeeNote1)
.' ,', , :
' ,: Operati~g Temperatuht'Range

If Military/Aerospace specified devices are required,'
please contact the National Semiconductor Seles
OffIce/Dlatrlbutors for availability and specifications.

"

.<

260"C
215°C
220"C

See AN450 "~urfaceMou;'tin,9 Methods ancj Their Effect
on Product Reliability" for other methOds Oflioldering surface mount devices.

"

Electrical Characteristics Vcq =

I

Symbol

Parameter

12V09- TA = 25"C,seetestcircuit

I

I

Conditions

I,

Min

Typ'

I

I

Max

Units

TACHOMETER
Input Thresholds

YIN = 25QmVp-p@ 1kHz (Note 2)

Hysteresis

VIN = 250 mVp-p @ 1 kHz (Note 2)

Offset Voltage
LM2907/LM2917
LM2907-B/LM2917-B

VIN = 250 mVPi' @ 1 kHz (Note 2)

,±10

±,25,

±40

mV

30

,.I

'.

mV

,3,5 "
'.;.'. 5

.10
15

mV
mV

1

!JA

Input Bias Current

VIN = ±50 mVoc

0.1

VOH

Pin 2

VIN = +125mVoc(Note3)

B.3

V

VOL

Pin2:

" 2.3

V

12,13

Output Current

V2 = V3 = 6.0V (Note 4)

13

Leakage Current

12=O,V3=0

K

Gain Constant

.

,

,',

, VIN = -125mVoc(Note3)

140

!JA
!JA

240
0.1

,(Note3)

Linearity

1BO

fiN = 1 kHz, 5 kHz, 10kHz (Note 5)

0.9

1.0

1.1

-1.0

0.3

+1.0

%

OP/AMPCOMPARATOR
Vos,

VIN;= 6.0V

3

10

mV

ISlAS:

VIN = 6.0V

50

500

,nA

'0

Input Common-Mode Voltage

"

Vollage Gain
,"'f'

"

Vcc- 1.5V

V/mV

50

rnA

Output Sink Current

Vc = 1.0

Output sOurce Current

VE = Vee -2.0

10

Saturatil:," Voltage

ISINK = 5mA

0.1

,

ISINK = 20mA

'.

40

ISINK = 50 rnA

. ,,: ~;'. '

rnA

1:0

,

i

0.5

,V

1.0

V

1.5

V

,

I

,

,,'

"

"

.

,

..

.'

,.

,',

'. ..
3-24B

V

200

~."

,

'

Electrical Characteristics Vee =
Symbol

I

12 VOC. TA = 25"C. see test circuit (Continued)

I

Pal'l!lmeter

I

Conditions

Min

I

Typ

I

Max

I

Units

ZENER REGULATOR
Regulator Voltage

7.56

ROROP = 4700

Series Resistance

10.5

Temperature Stability

+1

TOTAL SUPPLY CURRENT

V
15

0
mVI"C

-6

3.a

mA

Note 1: For operation in ambient te"""""tures above 25"C. the device must be derated based on a 15O"C maxlmum junction temperature and a thermal resistance
0I10l"C/W junction Ie ambient for LM2907-8 and LM2917-8, and 7!1'C/W iunction Ie ambient lor LM2907·14 and LM2917·14.
Nota 2: Hysteresis is the sUR)

+ VTH - (- Vni). offset voltage Is their dillerenca. See test circuit

Nota 3: VOH is equal Ie % x Vrx; - I Vee. VOL is equal Ie -Y. x Vrx; - 1 VeE th'''elore VOH - VOL
12/13, are the two lactcrs that cauae the tachometer gain constant Ie vary from 1.0.

= Vrx;/2. The difference, VOH -

VOlo and the mirror gain,

Nota 4: Be sure when choosing the time ccnstant R1 x C1lhat R1 Is such thai the maximum anticIpeIed ou1pUI voltage at pin 3 can be.reached with 13 x R1. The
maximum value lor R1 Is limited by the output resistanca 01 pin 3 which Is greater than 10 MO typically.
Nota 5: Nonlinearity is defined as the deviation 01 VOUT (@ pin 3) lor liN
C1 = 1000 pF, R1 = 68k and C2 = 0.22 mFd.

=

5 kHz from a straight line defined by the VOUT

General Description (Continued)
The op amp/comparator is fully compatible with the tachometer and has a floating transistor as its output. This
feature allows either a ground or supply referred load of up
to 50 mAo The collector may be taken above Vee up to a
maximum VeE of 2aV.
The two basic configurations offered include an a-pin device
with a ground referenciJd tachometer input and an internal
connection between the tachometer output and the op amp
non-inverting input. This version is well suited for single
speed or frequency switching or fully buffered frequency to
voltage conversion applications.

@

1 kHz and VOUT

@

10kHz.

The more versatile configurlltions provide differential tachometer input and uncommitted op amp inputs. With this
version the tachomet!"r input may be floated and the op
amp- becomes suitable for active filter conditioning of the
tachometer output.
Both of these configurations ar!! available with an active
shunt regulator connected across the power leads. The regulator clamps the supply such that stable frequency to voltage and frequency to current operations are possible with
any supply voltage and a suitable resistor.

Test Circuit and Waveform
TACHOMETER
INPUT

+IBIAS

OPAMP
SECTION

Tachometer Input Threshold Measurement
V2

+

/)7

NEGATIVE
INPUT
THRESHO_LD_...L_ _ _ _

J

.

~

!

1

/ ../ POSITIVE
INPUT

-t___...JU

THRESHOLD

!.

VIN TACHOMETER

TUHfl942-7

T

CI- ..... ,c
TACHOMETER
INPUT

/

TL/H/7942-6

3-249

•

Typical Performance Characteristics
Zener Voltage V8
Temperature

Total SUpply Current

I."
I.M
1.12

,

4GC

==+;~ ~""

i

UI

S

1.51

ffi

7.14
1.52

>

m

N" '

1.11

II

II

Normalized Tachometer
Output V8 Temperature

Tachometer Currents 12
and 13 va Supply Voltage

-

I"-

LMHDI

I"...

I

iUI2

I ...

210

lID

~~
I:.:=:

5

25

45

H

15

E
..=

LIt'2911 C41GU'-

I
I

0.1

-35

-'5

5

0.1
0.1

!
45

65

•

1&

38

z

34
32

i :
..

i

!

~

V "..

24V

21

IIV

I

i.-

>

1/ ~"

~
Z4 • 2
22
2D

l

LUll 1411'"

-15 -3& -15 & 21 45
TEMPERATURE I"CI

I

1.1

~

1.1

1.2

IS

15

fli

-

I--

-3& -.& & 25 4&
TEMPERATURE I"CI

H

u

c

1.4

.

D.2

..•

~ i"'"
+WC .....

.....

V

18

12':

.....

2D

31

41

SOURCE CURRENT ImAl

15

Vee = "V

'='.HI

R1C1 .. 3.1 - l.hll

'.3

IS: t--..

I' ~
L_I

1.1

~
LM21111411!!1

Op Amp Output Transl8tor
Characterlatlca
,1.1

I.J

I I

15

I.D
U.

....LM2I11'12Y'14"1~
'"

+lIi"C

""

UV V ",..
IV'

D

I

....

..-"

V

a.1

!

II

L_

I.'
2.1
2.4
2.2
2.D

U

IV

-

D.'

~
=

3.'

.....

IIV

5 IS 45
TEMPERATURE I+CI

...
...
. ...
li!

R.·la
Cl ·'.II ..fd

LM2II1

1&

",

-3& -Ii

Op Amp Output Translator
Characteristics

i :

"

..

Tachometer Unearlty V8 R1

1.1

Tachometer Input Hystere818
V8 Temperature

~

120

'.D

D.2

TEIWERATURE I'CI

I

'88

Vee "'2V
'=I.HI

D.I

z

21

-2~

JOlt

~ 18.

-411'C

I.D

~ D.4

LM2101

0.2

.... ...
.
a '.&
. '.3
I
fli

CI -I.II ..Ff

U

;

I I ••• 2 .4 16 II 2D 22 24 2. 2'

l

'''''H,
Rl'''''

0.4

.

Tachometer Unearlty
vs Temperature

f-VCC: ·12V

45

~

SUPPLY VOLTAGE IV'

1.'

~

lUG

.20

Tachometer Linearity
V8 Temperature

1.1
1.1
D.I
D.5

21D

140

TEMPERATURE I"CI

...
....
.

'"

'

21

210

241

Irc ""..-

~

5

Tachometer Currents 12
and 13 V8 Temperature

.40

11

-35 -15

21i"C

c

J:'

LMHII1411m
,.....

"

-35 -.5

,

~

..~ .n

l"-

LII2I1114111!1'

::;D.JM

~

221

I/'

;7~

TEMPERATURE I"CI

21D
24D

....

~

II'

TEMPERATURE I"CI

!li .....

c

..

SUPI'l YVOLTAGE IVI

11.012
z1 . •
!a_

iii

45

25

211

r10 '' .•
·•
:,.

:! ...

·'1'" Hz

10_
-35 -15', 5

FREQUENCY· 200 Hz

.-

s···
It_

Il0l1

~

FREQUENCY

:,.
i
I'·
..~.1.112

41tn

1.41

gl.111

fli

5'··
;1
....

~

1.41

I • 1. 12 ,. 1. " 21 22 M H II

i!

g'.I'o

Vee -'IV

~ 1.10

..

'!!::

!::t::=""

I
I

•

Normalized Tachometer
Output V8 Temperature

a

'.4
1.2

~

'.0

J

1.6

~
~

.11", V
2&;s..

1.1

'" ....

",

1.4

~

D.2

~

i""'1

-"'"'
II

21
31
40
SINK CURRENT I...,
TL/H/7942-5

Applications Information
The LM2907 series of tachometer circuits is designed for
minimum extemal part count applications and maximum versatility. In order to fully exploit its features and advantages
let's examine its theory of operation. The first stage of operation is a differential amplifier driving a positive feedback
flip-flop circuit. The input threshold voltage is the amount of
differential input voltage at which the output of this stage
changes state. Two options (LM2907-8, LM2917-8) have
one input intemally grounded so that an input signal must
swing above and below ground and exceed the input
thresholds to produce an output. This is offered specifically
for magnetic variable reluctance pickups which typically provide a single-ended ac output. This single input is also fully
protected against voltage swings to ±28V, which are easily
attained with these types of pickups.

The size of C2 is dependent only on the amount of ripple
voltage allowable and the required response time.

CHOOSING R1 AND C1
There are some limitations on the choice of R1 and C1
which should be considered for optimum performance. The
timing capacitor also provides internal compensation for the
charge pump and should be kept larger than 500 pF for very
accurate operation. Smaller values can cause an error current on R1, especially at low temperatures. Several considerations must be met when choosing R1. The output current
at pin 3 is internally fixed and therefore Vo/R1 must be less
than or equal to this value. If R1 is too large, it can become
a significant fraction of the output impedance at pin 3 which
degrades linearity. Also output ripple voltage must be considered and the size of C2 is affected by R1. An expression
that describes the ripple content on pin 3 for a single R1C2
combination is:

The differential input options (LM2907, LM2917) give the
user the option of setting his own input switching level and
still have the hysteresis around that level for excellent noise
rejection in any application. Of course in order to allow the
inputs to attain common-mode voltages above ground, input
protection is removed and neither input should be taken
outside the limits of the supply voltage being used. It is very
important that an input not go below ground without some
resistance in its lead to limit the current that will then flow in
the epi-substrate diode.

Vee
VRIPPLE = 2

f

x

R1

pk-pk

12
MAX - C1 x Vee

USING ZENER REGULATED OPTIONS (LM2917)
For those applications where an output voltage or current
must be obtained independent of supply voltage variations,
the LM2917 is offered. The most important consideration in
choosing a dropping resistor from the unregulated supply to
the device is that the tachometer and op amp circuitry alone
require about 3 mA at the voltage level provided by the
zener. At low supply voltages there must be some current
flowing in the resistor above the 3 rnA circuit current to operate the regulator. As an example, if the raw supply varies
from 9V to 16V, a resistance of 4700 will minimize the zener voltage variation to 160 mV. If the resistance goes under 4000 or over 6000 the zener variation quickly rises
above 200 mV for the same input variation.

The output circuit mirrors this current very accurately into
the load resistor R1, connected to ground, such that if the
pulses of current are integrated with a filter capacitor, then
Vo = ic x R1, and the total conversion equation becomes:
fiN X C1

fiN X C1 )

12

As a final consideration, the maximum attainable input frequency is determined by Vee, C1 and 12:

AQ
.
Vee
T
= Ic(AVG) = C1 x 2"" x (2fIN) = Vee x fiN X C1

x

x

It appears R1 can be chosen independent of ripple, however response time, or the time it takes VOUT to stabilize at a
new voltage increases as the· size of C2 increases, so a
compromise between ripple, response time, and linearity
must be chosen carefully.
/

Following the input stage is the charge pump where the
input frequency is converted to a dc voltage. To do this
requires one timing capacitor, one output resistor, and an
integrating or filter capacitor. When the input stage changes
state (due to a suitable zero crossing or differential voltage
on the input) the timing capacitor is either charged or discharged linearly between two voltages whose difference is
Vee/2. Then in one half cycle of the input frequency or a
time equal to 112 fiN the change in charge on the timing
capacitor is equal to Vee/2 x C1. The average amount of
current pumped into or out of the capacitor then is:

Vo = Vee

C1
(
Vee
X 1C2

x-

xK

Where K is the gain constant-typically 1.0.

Typical Applications
Minimum Component Tachometer
VC1: = 15V

+Vm = 87 Hz/V

'INIAPMI

lilt<

TUHI7942-8

3-251

....

~ .-------------------------------------~------------------------------------------,
~

;;
.........
',...

Typical Applications (Continued)
;,;'
, ',,- :
l'
'''Speed Switch" ,LOad Is EnerglZ~When fiN ~,2Rc

fJ

,

Vc:c = 8-NV

:!

TL/H/7942-9

Zener R8gulated Frequency to Voltag, Convert~r
Va;

= 12V

470

lOOk _

r

+ Your =

88 Hz/V

1.,.... F _

TL/HI'7942-10

Breaker Point Dwell Meter
B+4-----------~----------~~--9_--__,

1.

4JD

POINTS+----...

TLlHI7942-11

3-252

r-----------------------------------------------------------------------------,~

iii:

Typical Applications (Continued)

i...........

Voltage Driven Meter Indicating Engine RPM
Vo = 6V @ 400 Hz or 6000 ERPM (8 Cylinder Engine)

~

iii:

-

B+o------1~----~----~--------------~._--_,

~

......

DISTRIBUTOR

P
~REAKER~

10k

+

1

POINTS

TLIH/7942-12

Current Driven Meter Indicating Engine RPM
10 = 10 mA @ 300 Hz or 6000 ERPM (6 Cylinder Engine)
B+o-------.----------------1~--_,

10k

BREAKER
POINTS
10k

a,az.FT

21k
~

':"

TLlHI7942-13

Capacitance Meter
VOUT = 1V-10V for Cx = 0.01
(R = 111k)

to 0.1 mFd

15V

•

SDk

+

5k

VOUT

TLIH/7942-14

3-253

....

~r-------------------------------------------------------~

I

:!j::::

Typical Applications (Continued)
Two-Wire aemote Speed Switch

~

l--o

y.~....I-J\.AJ"'"'. .- - - 4.....--·-iL__C_~_~N_R:_:_T__

.....- -. .

vee

...J

. .- - - - I

I

_-------OGND

J

TUHI7942-15

100 Cycle Delay SwItch
Vee

V3

Ie

Vee x Cl
V3 steps up in voltage by the amount~

1110

TLIH/7942-16

Example:
If C2
V3

NO.
OF CYCLES

for each comPlete input cycle (2 zero crossings)

= 200 Cl after 100 consecutive input cycles.
= 112 Vee

3·254

Typical Applications (Continued)
Variable Reluctance Magnetic Pickup Buffer Circuits
Precision two'shot output frequency
equals twice input frequency.
Pulse width

~ Vcc~.
2 12

Pulse height ~ VZENER

VARIABLE
RELUCTAIICE
M'G.ETIC

~
fa)

PICKUP

,.JUUl
TLlHI7942-39
TLlHI7942-17

Finger Touch or Contact Switch
r-------------------.-------~5T015V

Q

R

INPUT
(60 Hz!
CONTACT
PLATE

Q

TLlH/7942-19

TL/H/7942-18

Flashing LED Indicates Overspeed
---4~--------------~t_--OI4V

430

68

150

•

f,.

Flashing begins when fiN:> 100 Hz.

'Y

Flash rate increases with input frequency
Increase beyond trip poinL

LED

TLlHI7942-20

3-255

Typical Applications

,~'

(Continued)

,

Frequency to Voltage Converter WIth 2 Pole Butterworth F,JHer to Reduce Ripple
Vee

Tl/HI7942-21

Your

f ..

Output latches when

fIN=~...!..

A1 + A2AC
. Aeset by removing Vee.''>

Tl/H/7942-22

3-256

TUH/7942-23

Typical Applications (Continued)
Some Frequency SwHch Applications May Require Hysteresis In the
Comparator Function Which can be Implemented In several Ways:
12V

so

10k
411

12V

I ..

TLlHI7942-25
VOUT

10.sl--.......

ut===~======~
5.94 6.01

V3

____
V3

TLlHI7942-27

TLlH/7942-28

3-257

.... r---------------------------------------------------------------------------------,
~

~

Typical Applications (Continued)

!i

Changing the Output Voltage for an Input Frequency of Zero
_....;.----OIOV

~

:i
VOUT

f'N

0--"""
+
10k VOUT

r!:7 -=

1

2

3

4

5

6

7

f,N (kHz)

TLlHI7942-30

zoo

TLlHI7942-29

Changing Tachometer Gain Curve or Clamping the Minimum Output Voltage
lOV

91k

Your
BV

"

3V
2V
IV

f'N (kHz)

TLlHI7942-32

-

-

TLlHI7942-31

3-258

Anti-Skid Circuit Functions
"Select-Low" Circuit

..----------------------------~

~,o------------------------WHEEL

I:~~~ o-------------------------+--------~

VOUT

WHEel NO 1

I
WHEEL SPEED

TUHI7942-34

r-~~~----i4~~~~~--------4_----------__6+
1k

VOUT

Your is proporlionallo the lower of the
two input wheel speeds.

TUHI7942-33

"Select-High" Circuit

v"o-----------______________~----------------------------_,
WHEElI:riU~

o-------------------------+-------__~
You,

VOUT
I

WHEel SPEED

TL/H/7942-36

r-~~~~------------~----------~------------.+
You,

J.-

Your is proportional 10 the highar of
the

two input wheel speeds.

TL/HI7942-35

v~o-------------

"Select-Average" Circuit
____________
_____________________________,
~

',o-------------------------~----------,

',0----------+-----,

r

c

•
rUH/7942-37

3·259

"
·0-

LM2907ILM2&1.7

m

c

r;;-------------,
, , , ~9 " , .

BIAS
r----,
I

0' AMP CO~"ARATOR

i'

1

10

\
I

i'

....
W
:::r

:J

1
1

1
1

oz 1
03\

1
I
1
1
I

i

.a

-:

CD

3

....

II

n

1

c

I

.z',

\
I
...J

01

iii
3

I'~;

I
I

oiz\

1
1

0131

I
I
I

I

-I
1

1

I

z-

\

IL

___

~

~qol

.A -

I

_ _ _ _ _ .JI

·0 \

INPUT HYSTERESIS AMPLIFIER

I

_____

~

L -

-

-

-

-

-

-

-

-

~

_ _ _ _ .JI

CHARGE PUMP

T!-'Hl7942-38

'This connection made on LM2907-8 and LM2917-8 only.
"This connection made on LM2917 and LM2917-8 only.

Section 4
Special Functions

•

Section 4 Contents
Display Drivers
Display Driver Selection Guide ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
LSI Display Driver ..................................................................
4-4
DS0026 5 MHz Two Phase MOS Clock Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6
DS75491 MOS-to-LED Quad Segment Driver.................. ........................
4-13
DS75492 MOS-to-LED Hex Digit Driver. . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .
4-13
DS75494 Hex Digit Driver.. ................. ....... .......... ..... .... ........ ......
4-16
LM3909 LED Flasher/Oscillator..... .................................................
4-18
LM3914 Dot/Bar Display Driver ........ ,..... .............. .................... ..... .
4-25
4-40
LM3915 Dot/Bar Display Driver ....... . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3916 Dot/Bar Display Driver . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-58
MM5450/MM5451 LED Display Drivers ...............................................
4-78
4-84
MM5452/MM5453 Liquid Crystal Display Drivers ............ . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5480 LED Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-91
MM5481 LED Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-95
MM5483 Liquid Crystal Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-99
MM548416-Segment LED Display Driver............... ...... ......................... 4-102
MM5486 LED Display Driver......................................................... 4-105
MM58241 High Voltage Display Driver ................................................ 4-110
MM58341 High Voltage Display Driver ................................................ 4-115
MM58342 High Voltage Display Driver ................................................ 4-120
Radio Circuits
LM565/LM565C Phase Locked Loops................................................ 4-125
LM567/LM567C Tone Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . 4-133
LM1596/LM1496 Balanced Modulator-Demodulators............... .................. .. 4-139
LM1865 Advanced FM IF System..................................................... 4-144
LM1868AM/FM Radio System ....................................................... 4-158
LM1893/LM2893 Carrier-CurrentTransceiver . .. . . .. . . . . . . . . . . . . . . . . . . . . . .. .. . . .. . . . . . . 4-166
LMC567 Low Power Tone Decoder. .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . .. 4-188
LMC568 Low Power Phase-Locked Loop. . . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . .. . . 4-192
Timers and Oscillators
LM122/LM322/LM3905 Precision Timers............................................. 4-196
LM555/LM555C Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-208
LM556/LM556C Dual Timers.. ....... .......... .................. ................... 4-216
LM566C Voltage Controlled Oscillator. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-220
LMC555 CMOS Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-224
MM5368 CMOS Oscillator Divider Circuit .................. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-227
MM536917 Stage Oscillator/Divider.................................................. 4-230
Ground Fault Interrupters
LM1851 Ground Fault Interrupter. ..... .......... ............. ........................ 4-233

4·2

t!lNational Semiconductor

Display Drivers

National's comprehensive family of display drivers provides
direct interface to all of the common display technologieslight-emitting diode (LED), liquid crystal display (LCD), and
vacuum fluorescent (VF),

for direct or multiplexed interface to large complex VF panel
arrays or 5 x 7 (or larger) dot-matrix character strings. Each
of the drivers are cascadable for further expansion. Application note AN-371 provides further details and other application information.

FUNCTION SIMILAR FAMILY

THE MM5450 SERIES-LED

Each driver utilizes a simple serial-data input channel, onchip shift register, latches and buffer/driver outputs. The
serial input channel allows direct interface to most microprocessors, including COPSTM, NSCBOOTM, 8080 series,
and TMS1000 series. Besides a serial-data input, each driver requires a clock input. Some offer a latch (data) input
and/or data output for easy cascade interconnect of additional drivers.

National's MM5450 series of LED display drivers rounds out
this comprehensive product family. This popular series offers direct drive of LED displays by providing up to 25 rnA of
current drive per LED segment.

MOS/LSI DISPLAY DRIVERS

CMOS/LSI
Many of the products in the display driver family utilize
CMOS technology. Detailed features/functions of the 12member dispiay driver family are high-lighted in the following product guide.

Once loaded, the shift register data can be transferred to
the on-chip latches, which then output to the buffer/ driver
and respective display. This buffer/driver is where each provides the unique driver interface desired by the particular
display technology-LED, LCD, or VF.

In addition, National offers a line of bipolar segment and
digit drivers with a broad range of output sink and source
currents.

THE MM58241 SERIES-VF
Each of the products in the MM58241 series provides highvoltage (several up to 8OV) drive of VF displays. All are ideal
OUTPUT
32

OUTPUT
1

-- --

-- - BLANKING
CONTROL

32 OUTPUT
BUFFERS

- - -32 LATCHES

I-

---DATA
IN

CLOCK

{>1

32-BIT
SHIFT REGISTER

DATA
OUT

•

'(.,.

ENABLE

Tl/XX/01OO-1

FIGURE 1. Typical Block Diagram
4-3

IJ1

,

National Semiconductor

"

t,> ;

:

'.

LSI· Di,splayDriver
Selection Guide

!

Display'
Technology .

product

'

,

Features

'Numbsr

••, j

, 3~-segment, direct/multiplexed drive to 6OV, data enable, brightness control,
cascadable, 40-pin DIP or 44-pin PeC package.

Vacuum
Fluorescent (VF)

MM58241

VF

MM58341

32-segment, direct/m~itipleXed .drive'to 35V, data enable, brightness control,
,cescadable, 40-pin DIP or 44-pin PCC package. '.

VF

MM58342

20-0 (

......-........... 1-(--rl(

°:r-f:-~v-4M"'H.""",""'+--f
pw·u~

t,-t,s:.11.

*
·
i

."f:::1:::L", f

-4>0-LL
.J

r
":'"

~

r

0 OUTPUT

f600Pf
TUF/5853-13

':"

TL/F/5853-12

FIGURE 1

+',.

PIlLS! GEl
IIIPUT

TUF/5853-15

TUF/5853-14

FIGURE 2
4-9

ringing of the clock about the Vss level is, particularly critical.
If the Vss - 1 VOH is not maintained, at aI/times, the infor.
mation stored in the memory could be altered. Referring to
Figure 1, if the threshold voltage of a transistor were -1.3V,
the clock going to Vss - 1 would mean that all the devices,
whose gates are tied to that clock, would be only 300 mV
from turning on. The internal circuitry needs this noise margin and from the functional description of the RAM it is easy
to see that turning a clock on at the wrong time can have
disastrous results.

Typical Applications
AC Coupled MOS Clock Driver
<:>-"'--0 VOUT

V = 20V X

20V X (_1_) = 0.35V
CL+Ce
56+1
This has been a hypothetical example to emphasize that
with 20V low rise/fall time transitions, parasitic elements
can not be neglected. In this example, 1 pF of parasitic
capaCitance could cause system malfunction, because a
7404 without a pull up resistor has typically only 0.3V of
noise margin in the "1" state at 25°C. Of course it is stretching things to assume that the inductance, L, completely isolates the clock transient from the 7404. However, it does
point out the need to minimize inductance in input/output as
well as clock lines.

-15V
L xaV
lL·~

c

10'"F·2OV
• 20. 10'..... lA

~=

TL/F/5853-19

FIGURE 4. Clock Waveforms (Voltage and Current)
Because of the amount of current that the clock driver must
supply to its capacitive load, the distribution of power to the
clock driver must be considered. Figure 4 gives the idealized voltage and current waveforms for a clock driver driving
a 1000 pF capaCitor with 20 ns rise and fall time.

The output is current, so it is more meaningful to examine
the current that is coupled through a 1 pF parasitic capacitance. The current would be:

As can be seen the current is significant. This current flows
in the Voo and Vss power lines. Any significant inductance
in the lines will produce large voltage transients on the power supplies. A bypass capacitor, as close as possible to the
clock driver, is helpful in minimizing this problem. This bypass is most effective when connected between the Vss
and Voo supplies. The size of the bypass capacitor depends on the amount of capaCitance being driven. Using a
low inductance capaCitor, such as a ceramic or sliver mica,
is most effective. Another helpful technique is to run the
Voo and Vss lines, to the clock driver, adjacent to each
other. This tends to reduce the lines inductance and therefore the magnitude of the voltage transients.

AV
1 X 10- 12 X 20
I = Ce X At =
20 X 10 9
= 1 mA
This exceeds the total output current swing so it is obviously
significant.
Clock coupling to inputs and outputs can be minimized by
using multilayer printed circuit boards, as mentioned previously, physically isolating clock lines and/or running clock
lines at right angles to input/output lines. All of these techniques tend to minimize parasitic coupling capacitance from
the clocks to the signals in question.
In conSidering clock coupling it is also important to have a
detailed knowledge of the functional characteristics of the
device being used. As an example, for the MM5262, coupling noise from the cj>2 clOCk to the address lines is of no
particular consequence. On the other hand the address inputs will be sensitive to noise coupled from cj> 1 clock.

While discussing the clock driver, it should be pointed out
that the 050026 is a relatively low input impedance device.
It is possible to couple current noise into the input without
seeing a significant voltage. Since the noise is difficult to
detect with an oscilloscope it is often overlooked.

4-11

III

i

Packaging Information

0.039

(1.000)

r ,\r
0.039
(1.00)

0.080 MAX
(2.030)

+

s'

~1j (C__ . )~.ll
0.008
(0.200)

-

0.280 _
(6.804)

0.025

+-r
4'

R 0.008
(0.200)

0.02B±0.002
(0.720±0.050) - .
TVP
0.050±0.004
(1.270J.!'.100)

-(0.650)
TUF/5853-21

8-Lead SUrface Mount Package
Order Number DS0026CL

4-12

tflNational Semiconductor

DS75491 MOS-to-LED Quad Segment Driver
DS75492 MOS-to-LED Hex Digit Driver
General Description

Features

The 0575491 and 0575492 are interface circuits designed
to be used in conjunction with M05 integrated circuits and
common-cathode LEOs in serially addressed multi-digit displays. The number of drivers required for this time-multiplexed system is minimized as a result of the segment-address-and-digit-scan method of LED drive.

•
•
•
•
•

50 rnA source or sink capability per driver (0575491)
250 rnA sink capability per driver (0575492)
M05 compatability (low input current)
Low standby power
High-gain Darlington circuits

Schematic and Connection Diagrams
DS75491 (each driver)

DS75492 (each driver)

v
(1.7," 141

~---.

(14,3,5,8, 10,121

A -"'-"II'V'Io-f--I

11,2.&,7," 131

A-"~M,,-"-I

4k

4k

TLlF/58S0-1

TLlF/58S0-2

DS75491 Dual-In-Line Package
4A

14

lA

4E
13

IE

4C

12

lC

v..
11

GNO

3C

DS75492 Dual-In-Une Package
3E

3A

lA

10

2C

14

2E

ZA

IV

BY

13

2V

BA

12

2A

Vas

11

GNO

TL/F/58SO-S

Top View

4-13

&V

4A

10

3A

3V

4V
TL/F/58S0-4

Top View
Order Number DS75491N, DS75492M or DS75492N
See NS Package Number M14A or N14A

5A

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DS75491 DS75492
Input Voltage Range (Note 4t
-5VtoVss,
Collector Output Voltage (Note 5)
10V
10V
Collector Output to Input Voltage

10V

Emitter to Ground Voltage (VI ~ 5V)
Emitter to Input Voltage

10V
5V'

Voltage at Vss Terminal witH Respect
to any Other Device Terminal

10V

10V

50mA
200mA

250mA
600mA

Collector Output Current '
Each Collector Output
All Collector Outputs

DS75491
600mW

Continuous Total Dissipation
Operating Temperature Range

O'Cto +70'C

Storage Temperature Rang\!

-65'C to + 150'C

' Lead Temp. (Soldering, 10 sec)

300"C

Maximum Power Dissipation
at 25'C
1207mW·
Molded Package
"Derate mOlded package 9.66 inWI'C above 25·C.
tOerate molded package 10.24 mWI'C above 25'C,

10V

DS75492
600mW

300'C

1280 mWt

Electrical Characteristics Vss = 10V (Notes 2 and 3)
Symbol

Conditions

Parameter

Min

Typ

Max

Units

0.9

1.2

V

DS75491
"ON" State Collector Emitter Voltage

veE ON

Input = 8.5V through 1 kO, ITA = 25'C
VE = 5V, Ie = 50 mA
TA= 0-70'C

I

Ie OFF

"OFF" State Collector Current

II

Input Current at Maximum Input Voltage

VIN = 10V, VE = OV, Ie = 20 mA

IE

Emitter Reverse Current

VIN = OV, VE = 5V, Ie = 0 rnA

Iss

Current Into Vss Terminal

Ve = 10V,
VE = OV

I liN = 40 p.A
I VIN = 0.7V
2.2

1.5

V

100

p.A

100

p.A

3.3

mA

100

p.A

1

mA

1.2

V

DS75492
VOL

Low Level Output Voltage

Input = 6.5V through 1 kO, ITA = 25'C
lOUT = 250mA
I TA = 0-70'C

IOH

High Level Output Current

VOH = 10V I liN = 40 p.A

II

Input Current at Maximum Input Voltage

\lIN = 10V, IOL = 20 mA

Iss

Current Into Vss Terminal

0.9

I VIN = 0.5V
2.2

1.5

V

200

p.A

200

p.A

3.3

mA

1

mA

Switching Characteristicsvss = 7.5V, TA = 25'C
Symbol

I

I

Parameter

Conditions

I I I I
Min

Typ

Max

Units

DS75491
tpLH
tpHL

Propagation Delay Time, Low·to-High Level Output (Collector) I VIH = 4.5V, VE = OV,
I
Propagation Delay Time, High-to-Low Level Output (Collector) I RL = 2000, CL = 15 pF I

I 100

ns

I 20

ns

DS75492
Propagation Delay Time, Low-to-High Level Output
ns
I VIH = 7.5V, RL = 390, I
I 300
I CL = 15pF
Propagation Delay Time, High-to-Low Level Output
ns
tpHL
I
30
I
NOIe 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. E~cept for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation,
Nole 2: Unless otherwise specified min/max limits apply acros,s the O'C to + 70"C temperature range for the 0875491 and 0875492.
Nota 3: All currents into device pins shown as positive, out of device pins as negative, all vottages referenced to ground unless otherwise noted. All values shown
tpLH

as max or min on absolute value basis.

NOIe 4: The Input is the only device terminal which may be negative with respect to ground.
Nota 5: Vottege values are with respect to network ground terminal unless otherwise noted.

4-14

AC Test Circuits and Switching Time Waveforms
OS75491

OS75492
7.SV

7.5V

......O----4~OUTPUT

">C~Y-41""'-OUTPUT

CL "15pf

JINOTEZI

CL =15pF

I1NOTE21

TL/F/5830-5
TLlF/5830-6

I---=' 10 n.

--I

I I -------- V,H
:""""""---'=""--,-I
I

INPUT
I

111%

:

I
111%

ov

_---V

I

I
I
I
I
OUTPUT

OH

I

I

I

I
I

I

I

I

I

I
I
I

I

I
I
I

I

....L-4--l

Note 1: The pulse generator has the following characteristics: ZOUT ~

I

I

~tpLH--l

son, PRR

~

100 kHz,

tw

~

1 p.s.

TLlF/5830-7

Note 2: CL includes probe and jig capacitance.

II
4-15

~

§

t!lNational Semiconductor

DS75494 Hex Digit Driver
General Description

Features

The 0575494 is a hex digit driver designed to interface between most MOS devices and common cathodes configured LED's with a low output voltage at high operating cur;
rents. The enable input disables a\l the outputs when taken
high.
.

•
•
•
•
•
•
•

150 mA sink capability
Low voltage operation
Low input current for MOS compatibility
Low standby power
Display blanking capability
Low voltage saturating outputs
Hex high gain circuits

Schematic and Connection Diagrams
Vee (18)

INPUT

Dual-In-Llne Package
OUT5
IN 5
OUT4

vee

IN 6

NC

IN lOUT lOUT 2

OUT 6

IN 4

CE

4k

(2.5.7.10.121

TO OTHER
INPUrs
CHIP ENABLE

6.&11

(9)

IN 2

OUT 3

IN 3

GNO
TL/F15832-2

TopYiew
GNO (I)

Order Number DS75494N
See NS Package Number N16A

TL/F/5832-1

Truth Table

x~

Enable

YIN

YOUT

0
0
1

0
1

1
0
1

X

don't care

4-16

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
10V
Input Voltage
10V
Output Voltage
10V
Storage Temperature Range

Supply Voltage, VCC
Temperature, TA
DS75494

Min
3.2

Max
8.8

Units
V

0

+70

'C

-65'C to + 150'C

Maximum Power Dissipation' at 25'C
Cavity Package
Molded Package
Lead Temperature (Soldering 4 seconds)
'Derate molded package 10.9 mW/'C above 2S'C.

1433 mW
1362 mW
260'C

Electrical Characteristics (Notes 2 and 3)
Symbol
IIH

Parameter
Logical "1" Input Current

IOH

VOL
Icc

Vcc

= Min, VIN = 8.8V

Min Typ Max Units

IVCE = 8.8Vthrough 100k
IVCE = 8.8V

= Max, VIN = -5.5V
Logical "1 " Output Current Vcc = Max, VOH = 8.8V VIN = 8.8V through 100k, VCE = OV
VIN = 8.8V, VCE = 6.5V through 1.0k
Logical "0" Output Voltage Vee = Min,lOL = 150 mA, VIN = 6.5Vthrough 1.0k,
DS75494
VCE = 8.8Vthrough 100k
Logical "0" Input Current

IlL

Conditions

2.0

mA

2.7

mA

-20

/LA

400

/LA

400

/LA

0.25 0.35

V

Vcc

I
I

Supply Currents

One Driver "ON", VIN = 8.8V
VCC

= Max

D875474

8.0

mA

100

/LA

100

/LA

40

/LA

0.04

1.2

/Ls

13

100

ns

IVCE = 6.5Vthrough 1.0k
IVIN = 8.8V through 100k

All Other Pins to GND

All Other Pins to GND
toFF

Output "OFF" Time

toN

Output "ON" Time

= 20 pF, RL = 240, Vee = 4.0V, See AC Test Circuits
CL = 20 pF, RL = 240, VCC = 4.0V, See AC Test Circuits
CL

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

Note 2: Unless otherwise specijied minImax lim~s apply across the O'C to + 70'C range for the DS75494.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

AC Test Circuit and Switching Time Waveforms
Vee
)

V'No--

~

V

I--TF
Vss

~ RL

.~ ~Il

_

f 9O%

90%

V'N
10%

0

VOUT

T. = IOns
T. = 10 os

!-T.

10%

\

~50"

1---0.2ms-1---0.2 ... -

- ' - CL

T 2 0 PF
±10"
VOUT

TLIF15832-3

0.6V
t~

tpOFF

~90%
~2.2V

-

-~

t-- lpON
TLlF15832-4

4-17

III

i='l

t!lNational Semiconductor

LM3909 LED FlasherIOsciliator
General Description

Features

The LM3909 is a monolithic oscillator specifically designed
to flash Light Emitting Diodes. By using the timing capacitor
for voltage boost, it delivers pulses of 2 or more volts to the
LED while operating on a supply of 1.5V or less. The circuit
is inherently self-starting, and requires addition of only a battery and capacitor to function as an LED flasher.

• Operation over one year from one C ·size flashlight cell
• Bright, high current LED pulse
• Minimum external parts

Packaged in an 8-lead plastic mini-DIP, the LM3909 will operate over the extended consumer temperature range of
- 25°C to + 70"C. It has been optimized for low power drain
and operation from weak batteries so that continuous operation life exceeds that expected from battery rating.
Application is made simple by inclusion of internal timing
resistors and an internal LED current limit resistor. As
shown in the first two application circuits, the timing resistors supplied are optimized for nominal flashing rates and
minimum power drain at 1.5V and 3V.
Timing capaCitors will generally be of the electrolytic type,
and a small 3V rated part will be suitable for any LED flasher
using a supply up to 6V. However, when picking flash rates,
it should be remembered that some electrolytics have very
broad capacitance tolerances, for example - 20% to
+100%.

• Low cost
• Low voltage operation, from just over 1V to 5V
• Low current drain, averages under 0.5 mA during
battery life
• Powerful; as an oscillator directly drives an 80 speaker
• Wide temperature range

Applications
• Finding flashlights in the dark, or locating boat mooring
floats
• Salelil and adve~ising gimmicks
• Emergency locators, for instance on fire extinguishers
• Toys and novelties
• Electronic applications such· as trigger and sawtooth
generators
• .Siren for toy fire engine, (combined 'oscillator, speaker
driver)
.• Warning indicators powered by 1.4V to 200V

Schematic Diagram

Connection Diagram

Typlcal1,5V Flasher
RLIM

Dual-In-Llne Package

r - - - - - - - - -,

y'

SLOW
RC

••

y'

NC

8

•
3.
FAST

OUT

NC

4
y-

RC
TL/H/7969-2

Top View
Order Number LM3909N
See NS Package Number N08E

3k

L. _ _ _ _ _ _ _ _ _ .J
TL/H17969-1

4-18

Absolute Maximum Ratings
Operating Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation
V+ Voltage

Lead Temperature (Soldering, 10 sec.)

-25"Cto +70"C
260"C

500mW
6.4V

Electrical Characteristics
Conditions
(Applications Note 3)

Parameter
Supply Voltage

Min

(In Oscillation)

Typ

Max
6.0

V

0.55

0.75

mA

1.0

1.3

Hz

1.15

Operating Current
Flash Frequency

300 JLF, 5% Capacitor

0.65

1.1

Units

kHz

High Flash Frequency

0.30 JLF, 5% Capacitor

Compatible LED Forward Drop

1 mA Forward Current

Peak LED Current

350 JLF Capacitor

45

mA

Pulse Width

350 JLF Capacitors at % Amplitude

6.0

ms

Typical Applications

..

2.1

1.35

(See applications notes on following page)
Triac Trigger

1
.".
COM

~

~

3.3

~:+
I.F

~

75

lb.

b

Is

5

P

4

Provides 40 mA. 10 1'8 pulses at about 8 kHz.
Triac gate may be pulse lransfonner isolated if
desired.

O.015.F

LM3909
~ I.

II

12

-1.4V FROM BATTERY OR
SOLAR CELL WITH SpF
.YPASS CAPACITOR. DRAIN
NOMINALl V 5 mAo
TUH/7969-3

4·19

V

en
en
CW)

C)

r---------------------------------------------------------------------------------,
Typical Applications (Continued)(See applications notes below)

:::::E
...I

Warning Flasher High Voltage Powered

Typical Operating Conditions

y.

Rs

~

LM3909

V+

Nominal
Flash Hz

CT

Rs

RFB

V+RANGE

6V
15V

2
2

400",F
180 ",F

1.5k
lk

5V-25V
13V-50V

100V

1.7

180 ",F

1k
3.9k
43k
lW

lk

85V-200V

CT

TLIHI7969-4

1.SV Flasher
0.7
...... 10-

0.6

.! 0.5
z
C
~

.....
LM39D9

+

~

0.4

ii:

0.3

...

>

1.5Y

"

./

C

,

V

V

D.Z
0.1
1.0

1.1

1.2

1.3

1.4

1.5

1.6

BATTERY VOLTAGE (VI
TLIHI7969-6

Estimated Battery Life
(Continuous 1.SV Flasher Operation)
TUHI7969-5

Type

Size Cell

Note: Nominal flash rate: 1 Hz.

M
C

D

Standard

Alkaline

3 months
7 months
1.3 years

6 months
15 months
2.6 years

Note: Estimates are made from our tests and manufacturers
data. CondiUons are fresh batteries and room temperature. Clad
or "leek-proof" batteries are recommended for any application
of five months or more. Nickel cadmium cells are not recommended.

APPUCATIONS NOTES
Note 1: All capaCitors shown are electrolytic unless marked otherwise.

Note 2: Flash rates and frequencies assume a ± 5% capacitor tolerance. Electrolytics may vary - 20% to

+ 100% of their stated value.

Note 3: Unless noted, measurements above are made with a 1.4Y supply, a 25'C ambient temperature, and an LED with a forward drop of 1.5V to 1.7V at 1 mA
forward current.
Note 4: Occasionally a flasher circuit will fail to oscillate due to an LED defect that may be missed because it only reduces light output 10% or so. Such LEOs can
be identified by a large increase in conduction between 0.9V and 1.2V.

4-20

Typical Applications (Continued) (See applications notes on previous page)
3VFlasher

Minimum Power at 1.SV

NSLSOZ1

+

LM3909

+

LM3909

. : . 3V

I.SV

100pF

300~F

3V

TL/H17969-6

Nelte: Nominal flash rate: 1.1 Hz. Average lORAIN ~ 0.32 rnA.

TUHI7969-7
Note: Nominal flash rate: 1 Hz. Average

IORAIN~O.77

rnA.

Fast Blinker

TRANSLUCENT

LM3909

D~c::J--~~

I.SV

TL/H/7969-11

4

Note: Winking LED inside, locates light in total darkness.

lk

TLlHI7969-9
Note: Nominal flesh rate: 2.6 Hz. Average lORAIN ~ 1.2 mAo

4·21

Typical Applications (Continued) (See applications notes above)
Flashlight Finder

SHORT 1-8 FOR
SINGLE CEll :pGHTS

STRI~.

CONTACT
PASSES
(lNSULATEOI THROUGH
CASE BOTT!lM

\
RING CONTACT ON
BULIi ASSEMBL Y

TLlH/7969-10

Note: LM3909, capacitor, and LED are Installed in a whHe translucent cap on the flashlight's back end. Only one
contact strip Qn addition to the case connectionlls needed for flasher power. Drawing current through the bulb
simplifies wiring and causes negligible loss since bulb resistance cold is Iypicslly less than 20.

4 Parallel LEOs

~

High Efficiency Parallel Circuit

~

39

39

~

39

39

~

39

~

39

39
NSL50210R
NSLD02 OR
NSL5024

~

+

~

1.5V

39

+

200

200

LM3909

LM3909

4

150

1.5V

4

110\lj,F

500a"F

lV

150

3V

TLlH17969-12

TLlH/7969-13

Note: Nominal flesh rala: 1.3 Hz. Average lORAIN = 2 rnA.

Note: Nominal flash rate: 1.5 Hz. Average lORAIN

4·22

= 1.5 rnA.

Typical Applications (Continued) (See applications notes above)
1 kHz Square Wave
1.2
1.0

.......
.....'"..
~

... •••
c

SVMMETRV
10k

O.2/JF

r

lM1909

c
>

'"c

4

+

0.6
0.4

-- --

D.2

I.SV

1m.

2 ...

TL/H17969-15

OUT

Nota: Output voltage through a 10k load to ground.

Tl/HI7969-14

"Buzz Box" Continuity and Call Checker

Variable Flasher

~'2-'6n

D

SPEAKER
NSLSOZ7

I
I

+

1.5V

Z.4I<
LM3IOI

75

2.5.

TEST
PROBES

Ik

lM3909

+
TLlHI7969-17

Note: Flash rate: 0 Hz-20 Hz.

1.5V

TLlHI7969-16

Nota: Differences between shorts, coils, and a few ohms of resistance can be
heard.

4·23

Typical Applications (Continued) (~e applications notes above)
LED Booster

Incandescent Bulb Flasher
+6V

O.I~F

75

lMJ909
LMJ9D9

4

+

1.5V

#41

TLlH/7969-1 B

Note: High efficiency. 4 mA drain. Continuous appearing light obtained by supplying
short, high current, pulses (2 kHz) to LEOs with higher than battery voltage available.

TLlH17969-19

Note: Flash rate: 1.5 Hz.

Emergency Lantern/Flasher
75

PRtJ

+
LMJ909
':"6V

TLlHI7969-20

Note: Nominal flash rate: 1.5 Hz.

4·24

f}1National Semiconductor

LM3914 Dot/Bar Display Driver
General Description
The LM3914 is a monolithic integrated circuit that senses
analog voltage levels and drives 10 LEOs, providing a linear
analog display. A single pin changes the display from a
moving dot to a bar graph. Current drive to the LEOs is
regulated and programmable, eliminating the need for resistors. This feature is one that allows operation of the whole
system from less than 3V.

Much of the display flexibility derives from the fact that all
outputs are individual, DC regulated currents. Various effects can be achieved by modulating these currents. The
individual outputs can drive a transistor as well as a LEO at
the same time, so controller functions including "staging"
control can be performed. The LM3914 can also act as a
programmer, or sequencer.

The circuit contains its own adjustable reference and accurate 10-step voltage divider. The low-bias-current input buffer accepts signals down to ground, or V-, yet needs no
protection against inputs of 35V above or below ground.
The buffer drives 10 individual comparators referenced to
the precision divider. Indication non-linearity can thus be
held typically to %%, even over a wide temperature range.
Versatility was designed into the LM3914 so that controller,
visual alarm, and expanded scale functions are easily added
on to the display system. The circuit can drive LEOs of many
colors, or low-current incandescent lamps. Many LM3914s
can be "chained" to form displays of 20 to over 100 segments. Both ends of the voltage divider are externally available so that 2 drivers can be made into a zero-center meter.
The LM3914 is very easy to apply as an analog meter circuit. A 1.2V full-scale meter requires only 1 resistor and a
single 3V to 15V supply in addition to the 10 display LEOs. If
the 1 resistor is a pot, it becomes the LEO brightness control. The simplified block diagram illustrates this extremely
simple external circuitry.

The LM3914 is rated for operation from O·C to + 700C. The
LM3914N is available in an 18-lead molded (N) package.

When in the dot mode, there is a small amount of overlap or
"fade" (about 1 mV) between segments. This assures that
at no time will all LEOs be "OFF", and thus any ambiguous
display is avoided. Various novel displays are possible.

The following typical application illustrates adjusting of the
reference to a desired value, and proper grounding for accurate operation, and avoiding oscillations.

Features
•
•
•
•
•
•
•
•
•

Orives LEOs, LCOs or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 100 steps
Internal voltage reference from 1.2V to 12V
Operates with single supply of less than 3V
Inputs operate down to ground
Output current programmable from 2 mA to 30 mA
No multiplex switching or interaction between outputs
Input withstands ±35V without damage or false outputs
Ii LEO driver outputs are current regulated, open-collectors
• Outputs can interface with TTL or CMOS logic
• The internal 10-step divider is floating and can be referenced to a wide range of voltages

Typical Applications
OV to 5V Bar Graptl Meter
r-+--1--~~~~--'--'--1-~--~-­ VLED

I
I
I
I

//I

//I

//I

//I

//I

//I

//I

••

.3

//I

//I

//I

"

II

LED
NO.1.

LED

1"0.•
I
I
....L
u.,....,...

Note 1: Grounding method is typical of al/ uses.
The 2.2 I'F tantalum or 10 I'F aluminum electrolytic capaCitor is needed if leads to the LED sup·
ply are 6" or longer.

"

LM3914

I

I

I
I
L...--I---I-------I---I--.....-v'
L.------t:~-...

&AV-.IV

Ref Out V - 1.25 (1
12.5

ILED

"'Fi1

TL/H/7970-1

4-25

+

*)

•

Absolute Maximum Ratings
Storage Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor sales
Office/Distributors for availability and specifications.
Power Dissipation (Note 5)
Molded DIP (N)

1365mW

Supply Voltage

25V

Voltage on Output Drivers

25V

Input Signal Overvoltage (Note 3)

215·C
220"C

See AN·450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

±35V
10mA

Reference, Load Current

+ 150"C
260"C

Plastic Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

-100mVtoV+

Divider Voltage

-55·Cto

Soldering Information
Dual-In-Une Package
Soldering (10 second!\)

Electrical Characteristics (Notes 1 and 3)
Parameter

I

I

Conditions (Note 1)

Min

I

Typ

I

Max

I

Units

COMPARATOR
Offset Voltage, Buffer and First·
Comparator
Offset Voltage, Buffer and Any Other
Comparator

, OV s: VRLO = VRHI
ILED = 1 mA

s: 12V,

OV s: VRLO = VRHI
ILED = 1 mA ,

s: 12V,

Gain (AILEDI AVIN)

IL(REF)= 2 mA,lLED = 10 mA

Input Bias Current (at Pin 5)

OV

Input Signal Overvoltage

NoGhange in ,Display

s: VIN s: V+

3

- 1.5V

3

'10

mV

3

15

mV
mA/mV

8
25

-35

100

nA

35

V

VOLTAGE-DIVIDER
Divider Resistance

Total, Pin 6 to 4

Accuracy

(Note 2)

8

12

17

kO

0.5

2

%

1.28

1.34

V

VOLTAGE REFERENCE
Output Voltage

0.1 mA s: IL(REF) s: 4 mA,
V+ = VLED = 5V

s: V+

1.2

Line Regulation

3V

:s;; 18V

0.01

0.03

%IV

Load Regulation

0.1 mA s: IL(REF) s: 4 mA,
V+ = VLED = 5V

0.4

2

%

Output Voltage Change with
Temperature

O·C s: T A s:
V+ = 5V

+ 70·C, IL(REF) =

1 rnA,

%

1

Adjust Pin Current

75

120

p.A
mA

OUTPUT DRIVERS
LED Current

V+ = VLED = 5V, IL REF) = 1 mA ,

LED Current Difference (Between
Largest and Smallest LED Currents)

VLED = 5V

LED Current Regulation

2V

s: VLED s: 17V

10

13

ILED = 2mA

0.12

0.4

ILED = 20mA

1.2

3

ILED = 2mA

0.1

0.25

ILED = 20mA

1

3

Dropout Voltage

ILED(ON) = 20 mA, 'vLED = 5V,
AILED = 2mA

Saturation Voltage

ILED = 2.0 rnA, IL(R~F) = 0.4 mA

Output Leakage, Each Collector

(Bar Mode) (Note 4)

4-26

7

1.5

mA

mA

V

0.15

0.4

V

0.1

10

p.A

r!:
Co)

Electrical Characteristics (Note 1) (Continued)

I

Parameter

I

Conditions (Note 1)

Min

I

Typ

I

....
.,..

CD

Max

I

Units

10

I

p.A

OUTPUT DRIVERS (Continued)
Output Leakage

I

(Dot Mode) (Note 4)

I
I

Pins 10-18
Pin 1

I
I

I

60

I

0.1
150

I
I

I

p.A

I

rnA

450

SUPPLY CURRENT
Standby Supply Current
(All Outputs Off)

I
I

V+
V+

=
=

5V,IL(AEF)

= 0.2 mA
= 1.0 rnA

20V, IL(AEF)

I
I

I
I

2.4
6.1

I

J

4.2
9.2

j

rnA

Note 1: Unless otherwise stated, all specifications apply with the following conditions:
VREF, VRHI, VRLO ,. (V+ - 1.5V)
3 Voc ,. V+ ,. 20 Voc
3 Voc ,. VLED ,. V+
OV ,. VIN ,. V+ - 1.5V
-0.015V,. VRLO ,. 12 Voc
TA ~ +25"C, Il(REF) ~ 0.2 rnA, VLED = 3.0V, pin 9 connected to pin 3 (Bar Mode).
-0.015V,. VRHI ,. 12 Voc
For higher power dissipations, pulse testing is used.
Note 2: Accuracy is measured refened to + 10.000 Voc at pin 6, with 0.000 Voc at pin 4. At lower full·scale voltages, buffer and comparator offset voltage may add
significant error.
Note 3: Pin 5 input current must be

lim~ed

to ± 3 mAo The eddition of a 39k resistor in series with pin 5 allows ± l00V signals without damage.

Note 4: Bar mode results when pin 9 is within 20 mV of V+ . Dot mode results when pin 9 is pulled at le""t 200 mV below V+ or left open circuit. LED No.1 0 (pin 10
output current) is disabled pin 9 Is pulled 0.9V or more below VLED.

n

Note 5: The maximum junCtion temparature of the LM3914 is 1WC. Devices must be derated for oparation at elevated temperatures. Junction to ambient thermal
resistance is 55"C/W for the molded DIP (N package).

Definition of Terms
Accuracy: The difference between the observed threshold
voltage and the ideal threshold voltage for each comparator. Specified and tested with 10V across the intemal voltage divider so that resistor ratio matching error predominates over comparator offset voltage.

LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLEO) as
measured at the current source outputs. As the forward voltage of an LED does not change significantly with a small
change in forward current, this is equivalent to changing the
voltage at the LED anodes by the same amount.
Line Regulation: The average change in reference output
voltage over the specified range of supply voltage (V+).

Adjust Pin Current: Current flowing out of the reference
adjust pin when the reference amplifier is in the linear region.
Comparator Gain: The ratio of the change in output current
(ILEO) to the change in input voltage (VIN) required to produce it for a comparator in the linear region.

Load Regulation: The change in reference output voltage
(VAEF) over the specified range of load current (IL(AEF»'
Offset Voltage: The differential input voltage which must
be applied to each comparator to bias the output in the
linear region. Most significant error when the voltage across
the intemal voltage divider is small. Specified and tested
with pin 6 voltage (VAHI) equal to pin 4 voltage (VALO).

Dropout Voltage: The voltage measured at the current
source outputs required to make the output current fall by
10%.

Input Bias Current: Current flowing out of the signal input
when the input buffer is in the linear region.

•
4-27

Typical Performance Characteristics
Supply Current vs
Temperature

Operating Input Bias
Current vs Temperature

... r--,--,--r--,......,

Reference Voltage vs
Temperature

-....

~

w

~

~

10.10 ~

.....

w

~
""

10.20

I
1.29
1.28

1D.OI;;:
AD(USTED TO 10YI_

:

r-F+'NGRrUNO~-

S

LCEF

:;1
~

~

1.21
I

2&

D

15

51

TEMPERATURE COCI

c

84

;:

82

..
§..
w

I

.i
iI:

~I 121---'-1f--f--I--t---,-j
i:

8&

"r--....

.0

f'...

18

!C!

1.0

~:.;
~~

0.• f--t--t

I!:l

..........

,,->

0.4

Z

~='
leg;
~~

,16

II!

-2&

25

15

58

"

liD

•

TEMPERATURE rCI

Input Current Beyond
Signal Range (Pin 5)

V'~2~

I

I-

DIVIDER V' llV

TAI'7~~t

30

OJ

II

it
;l!

...
n

C

-3

C
.!

l!:

20

0.4
0.2
0

1&

=

38 41

v'

1.12
I

1.10

lUI

~

w

LM381~ I--

1.06

DIVIDFR

u

:: 1.04

~

~

~

1.OD

....
0.96
-25

'/
2&

DIVIDER PARALLEL
WITH STABLE
Ok RESISTOR
&0

TEMPERATURE rCI

15

!
".
"
:!:

A
VJ_---

t; 1.12
II:

~

I

100

i

25

11.'

i

J--~-~-'--~-~-l

;
•

e
~
e

11..

Iii

~

ZA

~

C:::l::::,:~~'-"r"l' Z.3 '

L...-''--=-=-........_-'-_.... 2.2
0.& 1•• 1.&

z.o

10

Z.i 3.1 3.1 ...

Common-Mode Limits

-1.0 _

~EFER~ED TO JOSITIV~_
SUPPLY VOLTAGE

2.

11

"'-tv

lmA

,,,-25'"£

.....
~ ...
~.....
~

;(

_

-1.1i

I

~

-2.0

j
-

NEGATIVE COMMO'oMDDELIMIT INCLUDES GROUND
20

40

TEMPERATURE

60

rei

25

Output Characteristics
12

-0.&

1&

LEO SUPPLY VOLTAGE (VI

REFERENCE LOAD CURRENT CmAl

"N

21

11..& . . . - . . , . . , - - , - - . - , - - ,

V

,/
D

Total Divider Resistance
vs Temperature

15

LED Driver Current,
Regulation

/

II

10

0

LED CURRENT CmM

'TA·my

D

.... -30 -20 -10 0 10

U

0.&

LED tURRENT (mAl

I'

I;;

:=

0"

7 ~rlc

S

2&

ZD

~ 'II!
~

)1'

20

1.2

LED Current vs
Reference Loading

u

8.5

1&

1.0

>

0'--'--'--'--""'--'
10

aw

l!i
!;i
g;

0.2

1.8

~

~

f--f--7.t~-I--I---,-j

LED Driver Saturation
Voltage
1.4

!<

D.8 I--f--I-~~'

~,.

15

&0

TEMPERATURE ("CI

LED Current-Regulation
Dropout
r---r-.....,.-"'"",--Y--"

U

"

il

25

TEMPERATURE rCI

Reference Adjust Pin
Current vs Temperature

""
--~

2550n

80

ILIREFI"~"'"

V-

I
D.2

11.4

...

D.I

1.0

OUTPUT VOLTAOEM
TL/H17970-2

4·28

.-----------------------------------------------------------------------------, r
!!I:
w
Block Diagram (Showing Simplest Application)
U)

.....

~

r - - - - - LM39« - - - - - ,
1
COMPARATOR
1
1 OF 10

LED
V+

10

lk

lk

lk

lk

REF
OUT

Ik

1
7

THIS LOAD
DETERMINES
LEO
BRIGHTNESS

+

REFERENCE
VOLTAGE
SOURCE
1.25V

Ik

':" REF
ADJ

1
lk

8

Ik

V+~3

RLO

lk

lk

14

MODE
SELECT
AMPLIFIER

1 CONTROLS
9

TVPE OF
DISPLAY. BAR
OR SINGLE
LED

1
1

V-~
I':"

III

1

-==- _________ .J1

L __

TL/H17970-3

4-29

Functional Description
The simplifed LM3914 block diagram is to give the general
idea of the circuit's operation. A high input impedance buffer
operates with signals frolTl ground to 12V, and is protected
against reverse and overvoltage signals. The signal is then
applied to a series of 10 comparators; each of which is biased to a different comparison level by the resistor string.
In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. In this case, for each
125 mV that the input signal increases, a comparator will
switch on another indicating LED. This resistor divider can
be connected between any 2 voltages, providing that they
are 1.5V below V+ and no less than V-. If an expanded
scale meter display is desired, the total divider voltage can
be as little as 200 mY. Expanded-scale meter displays are
more accurate and the segments light uniformly only if bar
mode is used. At 50 mV or more per step, dot mode is
usable.

spite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead to a number of novel displays or ways of indicating input overvoltages, alarms, etc.
MODE PIN USE
Pin 9, the Mode Select input controls chaining of multiple
LM3914s, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current 1, then flows through the output set resistor R2 giving an output voltage of:
Your = VREF (1R
+2
R1 )
o

'L

I
t

r
I

+ IADJ R2

7RI

L

~EF

,

00

Mode Pin Functional Description

I
I

LM3914
REF
REF
OUT_ _ ADJ -

o

-

Dot Display, Single LM3914 Driver: Leave the Mode Select pin open circuit.
Dot Display, 20 or More LEOs: Connect pin 9 of the first
driver in the series (i.e., the one with the lowest input voltage comparison pOints) to pin 1 of the next higher LM3914
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30, 40, or more LED displays. The last LM3914 driver in the chain will have pin 9
wired to pin 11. All previous drivers should have a 20k resistor in parallel with LED NO.9 (pin 11 to VLED).

This pin actually performs two functions. Refer to the simplified block diagram below.

-.J
f9

Block Diagram of Mode Pin Function
OUTPUT NO. 9

8

OUTPUT NO. 10

9

~IADJ

VDUT

CONTROLLED DRIVE {
(FROM COMPARATORS)

R2

H - - I - - - - .......

TL/H17970-4

Since the 120 /LA current (max) from the adjust terminal
represents an error term, the reference was deSigned to
minimize changes of this current with V + and load changes.
CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant deTL/H/7970-5

4-30

Mode Pin Functional Description

(Continued)

DOT OR BAR MODE SELECTION

ticeable when using high-efficiency LEDs in a dark environment. If this is bothersome, the Simple cure is to shunt LED
No. 11 with a 10k resistor. The 1V IR drop is more than the
900 mV worst case required to hold off LED No. 10 yet
small enough that LED No. 11 does not conduct Significantly.

The voltage at pin 9 is sensed by comparator Cl, nominally
referenced to (V+ - 100 mY). The chip is in bar mode
when pin 9 is above this level; otherwise it's in dot mode.
The comparator is designed so that pin 9 can be left open
circuit for dot mode.
Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than
20 mV below V+ for bar mode and more than 200 mV below V+ (or open circuit) for dot mode. In most applications,
pin 9 is either open (dot mode) or tied to V+ (bar mode). In
bar mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.

OTHER DEVICE CHARACTERISTICS
The LM3914 is relatively low-powered itself, and since any
number of LEDs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEDs OFF) is 1.6 mA (2.5 mA max). However, any reference
loading adds 4 times that current drain to the V + (pin 3)
supply input. For example, an LM3914 with almA reference pin load (1.3k), would supply almost 10 mA to every
LED while drawing only 10 mA from its V+ pin supply. At
full-scale, the IC is typically drawing less than 10% of the
current supplied to the display.

DOT MODE CARRY
In order for the display to make sense when multiple
LM3914s are cascaded in dot mode, special circuitry has
been included to shut off LED No. lOaf the first device
when LED No. 1 of the second device comes on. The connection for cascading in dot mode has already been described and is depicted below.

The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and often an annoying flicker.
An "overlap" is built in so that at no time between segments
are all LEDs completely OFF in the dot mode. Generally 1
LED fades in while the other fades out over a mV or more of
range (Note 2). The change may be much more rapid between LED No.1 0 of one device and LED No.1 of a second
device "chained" to the first.

As long as the input Signal voltage is below the threshold of
the second LM3914, LED No. 11 is off. Pin 9 of LM3914
No. 1 thus sees effectively an open circuit so the chip is in
dot mode. As soon as the input voltage reaches the threshold of LED No. 11, pin 9 of LM3914 No.1 is pulled an LED
drop (1.5V or more) below VLED. This condition is sensed by
comparator C2, referenced 600 mV below VLED. This forces
the output of C2 low, which shuts off output transistor Q2,
extinguishing LED No. 10.

The LM3914 features individually current regulated LED
driver transistors. Further internal circuitry detects when any
driver transistor goes into saturation, and prevents other circuitry from drawing excess current. This results in the ability
of the LM3914 to drive and regulate LEDs powered from a
pulsating DC power source, i.e., largely unfiltered. (Due to
possible oscillations at low voltages a nominal bypass capacitor conSisting of a 2.2 ,.,.F solid tantalum connected from
the pulsating LED supply to pin 2 of the LM3914 is recommended.) This ability to operate with low or fluctuating voltages also allows the display driver to interface with logic
circuitry, opto-coupled solid-state relays, and low-current incandescent lamps.

VLED is sensed via the 20k reSistor connected to pin 11.
The very small current (less than 100 ,.,.A) that is diverted
from LED No.9 does not noticeably affect its intensity.
An auxiliary current source at pin 1 keeps at least 100 ,.,.A
flowing through LED No. 11 even if the input voltage rises
high enough to extinguish the LED. This ensures that pin 9
of LM3914 No.1 is held low enough to force LED No.1 0 off
when any higher LED is illuminated. While 100 ,.,.A does not
normally produce significant LED illumination, it may be no-

Cascading LM3914s In Dot Mode

VLED

~

IjJ

NO. 11
11

u+

TUH17970-6

4-31

...~

~r-----------------------------------------------------------------------'

Typical Applications (Continued)

::::Ii!

....I

ZerO-Center Meter, 2G-Segment

-

,~

~
LED
NO.1

,

~

,~

430110)

AI

~~

~~

~

~

AI

.

."

~~

'-

-:.:

~

---',8

~

N

.., ~

"""11

.,6

~

,

,

., ~
~

115

,~

~

~~

.'-

~
~~

~

-::

.~

'iii

.~

~

14

."

-('ii

r'3

iii

'iii
."
- f-

-=1

LED
0 • 1•

10

LM3914
y+
2

l'

-d:-

~

~

~ ~lk*

~21

~

I

sia

RLO
4

5

~

120
LM337

3

RHI

REF OUT REF ADJ MODE
8
I
1

I!..-

150

I~F**'

)~

I
-,,1.3V

Jv

SVDC

N
LED N0.11

/'

/~~

N

N

."

~~

18

11

'-

N

."

-

'-

1&

N

N

N

N

~~ ~~ ~~

~~

15

14

13

12

N

--

."

11

N

~~LED
NO, 20
10

LM3914

L......Jl

2

y+

RLO

3

4

sia
5

RHI

REF OUT REF ADJ MODE
9

I!..- 7

•

,,-Uk
~

INPUTSIG
TL/H17970-7

4-32

~----------------------------------------------------------------------------'r

Typical Applications (Continued)

==
~
....

Expanded Scale Meter, Dot or Bar

~

~::fE1~:'~~c
Ii. &-0-& MAX)

t

VLED
III

III

III

III

/1/

/1/

III

III

III

/1/

LEO

LEO

NO.1

NO.IO

18

11

16

15

14

13

12

\I

10

DOT

2.2.F*

LM3914
REF OUT

REF
ADI

'This applicalion illustrates that the LED supply
needs practically no filtering

Calibration: With a precision meter between pins
4 and 6 adjust At for voRage Vo of t.20V. Apply
4.94V to pin 5. and adjust A4 until LED No.5 just
lights. The adjustments are non-interacting.

TL/H17970-8

Application Example:
Grading 5V Regulators
Highest No.
LED on

Color

VOUT(MIN)

10
9
8
7
6

Red
Red
Yellow
Green
Green

5.54
5.42
5.30
5.18
5.06

5
4
3
2
1

Green
Green
Yellow
Red
Red

5V
4.94
4.82
4.7
4.58
4.46

III
4-33

Typical Applications (Continued)
"Exclamation Point" Display
III

III

III

III

III

/1/

III

/1/

/1/

III

11

11

11

15

14

13

12

II

10

158
LED

NO. 18

lM3914

5V--e---------------~

3V-,...,
DV....J

Uk

L..

LEOs light up as illustrated with the upper I~ LED
indicating lhe ac1uel inpul voltage. The display
appears 10 increase resolution and provides an
analog Indication of overrange.
TLlH17970-9

1 kHz pulse rale ., 10% duty cycle

Indicator and Alarm, Full-Scale Changes Display from Dot to Bar
/1/

/1/

/1/

/1/

III

III

III

III

1/1

III

"

17

1.

11

14

13

12

11

10

LED
NO.1

lM3914
MODE

':'

'The input 10 lhe Dol·Bar Swilch may be taken
from calhodes of other LEOs. Display will change
to bar as soon as the LED so selec1ed begins 10
light.
TL/H/7970-10

4·34

Typical Applications (Continued)
Bar Display wih Alarm Flasher
VLEO 5V
100

N

."

N
~,

-:..

~

LED
NO. I

18

N

."

...
11

N

-

~,

.,,.

N

~

16

N

."

15

~

14

N

N

N

~~ ~~
12

13

,.

N

."

."

~

AI

LED

~
10

II

;:~

lM3914

L-Jl

~

v+

RLD

3

-¥

SIG

J5

AHI
6

REF OUT REF ADI MODE
7
9

~

470
1.2k
Full·scale causes the full bar display to flash. If
.
.
.
the Junction of R1 and C1 IS connected to a dlf~
ferent LED cathode, the display will flash when
that LED lights, and at any higher input signal.

.

TL/H/7970- I 1

Adding Hysteresis (Single Supply, Bar Mode Only)
y+
16V)

1

., ,
N

LED
NO. I

...

-~ ~ , -., ~
N

N

N

~

II

17

18

N

N

IS

14

VLED
OUT

, , -., ~
N

~ ~ ~ ~ ~ :..

ADJ

11

I.Fk

N

N

~

12

13

,

LM337H

N

I

IN

~ ~ LED
ND.1U

11

10

REF
ADJ
8

MODE
8

lM3914
V-

L-Jl

~

y+
3

RLO
4

SIG

1
6

RHI

REf OUT

I!...Uk

7

110

2.7
CARSON

10
Hysteresis is 0.5 mV to 1 mV

•

----

TLlH/7970-12

•
4-35

"'III'
,..

~

:E

Typical Application

(Continued)

Operating with a High Voltage Supply (Dot Mode Only)

....I

...

Uk

Uk

'W

The LED currents are approximately to mA, and
the LM3914 outputs operate in saturation for
minimum dissipation.

'w

1N4.:z

...

,,
N

N

111

N

,

~

N

N

111

N

,r r ~ r

~

,

N

N

r

V

~r
LED

LED
NO.1

'0. 10
18

"

11

12

13

14

15

"

11

LM3914

L.Jl

"LO

SlG

3

~

l'

~

3.4V·

REF

REF

v'

"H' OUT AOJ
!.!..- 7 ~

MODE

I'

~Ir 111
'This point is partially regulated and decreases in
voltage with temperature. Voltage requirements
...
of the LM3914 also decrease with temperature. 2N2SOfi

&II

..J.
TL/H17970-13

2G-Segment Meter with Mode Switch

N

·The exact wiring arrangement of this schematic

LEO
NO.1

111

shows the need for Mode Select (pin 9) to sense
the V+ voltage exactly as it appears on pin 3.

18

N

N.

r ~ ~~

11

~

, ,,
N

~ ..

"

N

111

~

,.

15

N

N

" "
12

13

N

~r

,.

LEO
NO.l0

,.

11

LM3914

---1'

-¥

v'

"LO

3

-¥

".,

SlG

• •

"EF

"EF
AOJ

••T

,

MODE

;.zv*
l.u*

..J.

,

N

N··' 111

\.

~,

,, ,
N

N

~

LED
NO.11

tJ -r~

J

11

11

"

15

111

,.

,

N

N
~,

,

N

5Voc

N

~,

,,0

NO.21

12

13

10

11

LM3914

,

,

v-

v'

RLO

J

~

•

SlG

•

SIO. OV-Z.4V

".,

"EF

"EF

O.T
ADJ
7
8
2.4V

MODE

I!.-

,....

'Programs LEOs to 10 mA

4-36

•

TUH/7970-14

r-------------------------------------------------------------------------------------, ri:
Application Hints
CD
....
Three of the most commonly needed precautions for using
NON-INTERACTING ADJUSTMENTS FOR EXPANDED
Co)

the LM3914 are shown in the first typical application drawing (see page 9-108) showing a OV-SV bar graph meter.
The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from Signal sources, reference ground and bottom of the resistor string (as illustrated) to a single point
very near pin 2 is the best solution.

~

SCALE METER (4.5V to 5V, Bar or Dot Mode)
This arrangement allows independent adjustment of LED
brightness regardless of meter span and zero adjustments.
First, VI is adjusted to SV, using R2. Then the span (voltage
across R4) can be adjusted to exactly O.SV using R6 without
affecting the previous adjustment.
R9 programs LED currents within a range of 2.2 mA to
20 mA after the above settings are made.

Long wires from VLED to LED anode common can cause
oscillations. Depending on the severity of the problem
O.OS ,...F to 2.2 ,...F decoupling capacitors from LED anode
common to pin 2 will damp the Circuit. If LED anode line
wiring is inaccessible, often similar decoupling from pin 1 to
pin 2 will be sufficient.

Greatly Expanded Scale (Bar Mode Only)
REF
RLO

RHI

~.-"';>s

If LED turn ON seems slow (bar mode) or several LEDs light
(dot mode), oscillation or excessive noise is usually the
problem. In cases where proper wiring and bypassing fail to
stop oscillations, V + voltage at pin 3 is usually below suggested limits (see Note 2, page 9-108). Expanded scale meter applications may have one or both ends of the internal
voltage divider terminated at relatively high value resistors.
These high-impedance ends should be bypassed to pin 2
with at least a 0.001 ,...F capacitor, or up to 0.1 ,...F in noisy
environments.

REF

OUT

-

AOJ

-')7-

~

Rl

_

100
1%

-

:
•
•

R2
250

PINS OF
LM3914

VI -1.1V

I

:~

R3
200

•

R4

.~ 1%

12

•
•

Power diSSipation, especially in bar mode should be given
consideration. For example, with a SV supply and all LEDs
programmed to 20 mA the driver will dissipate over 600 mW.
In this case a 7.S0 resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 ,...F solid tantalum capacitor
to pin 2 of the LM3914.

!O.I~F

Turning OFF of most of the internal current sources is accomplished by pulling positive on the reference with a current source or resistance supplying 100 ,...A or so. Alternately, the input signal can be gated OFF with a transistor
switch.

R5
100

:~ 15

VI

R6

:~ 909
.~ 1%

":~
TLIH17970-15

ADJUSTING LINEARITY OF SEVERAL STACKED
DIVIDERS

Other special features and applications characteristics will
be illustrated in the following applications schematics.
Notes have been added in many cases, attempting to cover
any special procedures or unusual characteristics of these
applications. A special section called "Application Tips for
the LM3914 Adjustable Reference" has been included with
these schematics.

Three internal voltage dividers are shown connected in series to provide a 30-step display. If the resulting analog meter is to be accurate and linear the voltage on each divider
must be adjusted, preferably without affecting any other adjustments. Tq do this, adjust R2 first, so that the voltage
across RS is exactly 1V. Then the voltages across R3 and
R4 can be independently adjusted by shunting each with
selected resistors of 6 kO or higher resistance. This is possible because the reference of LM3914 No.3 is acting as a
constant current source.

APPLICATION TIPS FOR THE LM3914 ADJUSTABLE
REFERENCE
GREATLY EXPANDED SCALE (BAR MODE ONLY)

The references associated with LM3914s No.1 and No.2
should have their Ref Adj pins (pin 8) wired to ground, and
their Ref Outputs loaded by a 6200 resistor to ground. This
makes available similar 20 mA current outputs to all the
LEDs in the system.

Placing the LM3914 internal resistor divider in parallel with a
section ("" 2300) of a stable, low reSistance divider greatly
reduces voltage changes due to IC resistor value changes
with temperature. Voltage VI should be trimmed to 1.1 V first
by use of R2. Then the voltage V2 across the IC divider
string can be adjusted to 200 mY, using RS without affecting
VI. LED current will be approximately 10 mAo

If an independent LED brightness control is desired (as in
the previous application), a unity gain buffer, such as the
LM310, should be placed between pin 7 and R1, similar to
the previous application.

4-37

.... r---------------------------------------------------------------------------------,
~

G)
C")

~

Application Hints (Continued)

Non-Interacting Adjustments for Expsnded scale Meter (4.5V to 5V, Bar ,or Dot Mode)
REF

,RB
Uk

REF
ADJ

" 10V

OUT

R1
10k

R9
20k
LED
BRIGHTNESS

R4
523
4,5V
R5
4.32k
1%

TUH17970-16

Adjusting Unearlty of Several Stacl4;ed Divider.

~.",[

-,. {
;,

Rl
549
1%

Other Applications
R2
200

•
•
•
•
•
•
•
•

"Slow"-fade bar or dot display (doubles resolution)
20-step meter with single pot brightness control
10-step (or multiples) programmer
Multi-step or "staging" controller
Combined controller and process deviation meter
Direction and rate indicator (to add to DVMs)
Exclamation point display for power saving
Graduations, can be added to dot displays. Oimly light
every other LED using a resistor to ground
• Electronic "meter-relay"-display could be circle or
semi-circle
'
• Moving "hole" display-indicator LED is dark, rest of
bar lit
• Drives vacuum-fluorescent and LCDs using added passive ,Parts

3V
R3
549
1%
2V
R4
549

IV

-.. ",f

R5
511
1%

-

TL/HI7970~17

4-38

r-----------------------------------------------------------------------,~

i.....

Connection Diagrams
Dual-In-Llne Package

olio.

Plastic Chip Carrier Package
18
LED NO.1

DIVIDER (LOW END)

4

18

LED 4

SIGNAL INPUT

5

17

LED 5

DIVIDER (HIGH END)

6

16

LED 6

NIC

7

15

LED 7

REFERENCE OUTPUT

B

14

LEDB

~~

!:!

9
'" ...

......

Q

~

LED NO.2

DIVIDER
(LOW END)
SIGNAL INPUT
DIVIDER 6
(HIGH END)
REFERENCE OUTPUT

...

REFERENCE ADJUST

...fI

10 LEDNO.l0

MODE SELECT

Q

0

:::IE
TLlH/7970-18

TL/H17970-19

TopYiew

TopYiew

Order Number LM3914Y
See NS Package Number Y20A

Order Number LM3914N
See NS Package Number N18A

4·39

~

:i~d
P Nat i,o n a I

S e m i con due tor

LM3915 Dot/Bar Display Driver
General Description
The LM3915 is a monolithic integrated circuit that senses
analog voltage levels and drives ten LEOs, LCOs or vacuum
fluorescent displays, providing a logarithmic 3 dB/step analog display. One pin changes the display from a bar graph to
a moving dot display. LED current drive is regulated and
programmable, eliminating the need for current limiting resistors. The whole display system can operate from a single
supply as low as 3V or as high as 25V. .

The LM3915 is very versatile. The outputs can drive LCOs,
vacuum fluorescents and incandescent bulbs as well as
LEOs of any color. Multiple devices can be cascaded for a
dot or bar mode display with a range of 60 or 90 dB.
LM39l5s can also be cascaded with LM39l4s for a linear/
log display or with LM39l6s for an extended-range VU meter.

Features

The IC contains an adjustable voltage reference and an accurate ten-step voltage divider. The high-impedance input
buffer accepts signals down to ground and up to within 1.5V
of the positive supply. Further, it needs no protection
against inputs of ± 35V. The input buffer drives 10 individual
comparators referenced to the precision divider. Accuracy is
typically be:tter than 1 dB.
.

•
•
•
•
•
•
•
•
•
•
•
•

The LM39l5's 3 dB/step display is suited for signals with
wide dynamic range, such as audio level, power, light intensity or vibration. Audio applications include average or peak
level indicators, power meters and RF signal strength meters. Replacing conventional meters with an LED bar graph
results in a faster responding, more rugged display with high
visibility that retains the ease of interpretation of an analog
display.

3 dB/step, 30 dB range
Drives LEOs, LCOs, or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 90 dB
Internal voltage reference from 1.2V to l2V
Operates with single sUj)ply of3V to 25V
Inputs operate down to ground
Output current programmable from 1 mA to 30 mA
Input withstands ±35V without damage or false outputs
Outputs are current regulated, open collectors
Directly drives TTL or CMOS
The internal 10-step divider is floating and can be referenced to a wide range of voltages

The LM3915 is rated for operation from O"C to + 70"C. The
LM39l5N is available in an la-lead molded DIP package.

The LM3915 is extremely easy to apply. A 1.2V full-scale
meter requires only one resistor in addition to the ten LEOs.
One more resistor programs the full-scale anywhere from
1.2V to l2V independent of supply voltage. LED brightness
is easily controlled with a single pot.

Typical Applications
OV to 10V Log Display

r-

I

I
I
I
Cl

3VIfIY

76
-25

50

25

15

o

101

o

10

TEMPERATURE 1°C)

V.~28J

I

DIVIDER v = 10V

:c
.5
ill

...

.

E

!!

1.5

30

1.0

25

0.5

~ :c.5

c

)'

-1

-z

...

... .,...~
!
of

n

i'l

ill

~

of

"7 ~r7

10

25

/~

/

20
TA 25O'l1'"
0

15

/

10

/

~

-3
-40 -30 -20 -10 0

ZO

LED Current vs
Reference Loading

TA1.,oo~t

-

15

LEO CURRENT ImA)

Input Current Beyond
Signal Range (Pin 5)

...

TA"O°C-

20

30

o

40

o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
REFERENCE LOAD CURRENT ImA)

Total Divider Resistance
vs Temperature

~

i.

1.12

I

1.10

I

1.08

:=u

.ill

:; 0.98
2;

.
.

!

.,

A

1.02

Output Characteristics
12

-0.5

~EFER~ED TO JOSITIV~_

25

DIVIDER PARALLEL
WITH STABLE
lk RESISTOR
50

TEMPERATURE rc)

V+-5V
TA=Z5°C

i3

75

100

\mA

I

-1.5

J:
t - - NEGATIVE CDMMON-MODELIMIT INCLUDES GROUND
20

40

TEMPERATURE I"C)

60

ao

~oo""

L.

SUPPLY VDLTAGE

0.96

-25

1.

~ -z.o

./L_-/'

Common-Mode Limits

_
~ -1.0

DIVI~ER

1.04

~ 1.00

~

LM39:V -

!! 1.06

t;

v·

j

1;..""
~IO""
lUREF)' ~oo ""

V

I
0.2

0.4

0.6

1.8

1.1

OUTPUTVOLTAGEIV)

TUH/5104-3

4-43

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

..-.

~'

Block Diagram (Showing Simplest Application)

:i

.:' r - - -

I

~

T

'." .' '.

I

LEO

T!:i3m:-::; - - - - ,
COMPARATOR
1 OF 10

10

'" v·

I

6.63k

1
1

I
I
I

••6Sk

1

LED PROGRAM
CURRENT

I

I.
I
REF I
OUT 1
THIS LOAD .
OET.ERMINES
LEO

REFERENCE
VOLTAGE
SOURCE
1.2V

BRI~HTNESS

- 1

I
1

V+-1
.1

1
RLO 1•
MODE
SELECT
AMPLIFIER

I

CONTROLS
TYPE OF
DISPLAY, BAR
DR SINGLE
LED

.1

~'
SIG
IN

5

I ':"

+

l _____. ________ J

TLlH/51 04-4

4·44

Functional Description

LM3915 Output Circuit

The simplified LM3915 block diagram is included to give the
general idea of the circuit's operation. A high input impedance buffer operates with signals from ground to 12V, and is
protected against reverse and overvoltage signals. The signal is then applied to a series of 10 comparators; each of
which is biased to a different comparison level by the resistor string.

PIN 1, PINS 10-18

In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. In this case, for each
3 dB that the input signal increases, a comparator will
switch on another indicating LED. This resistor divider can
be connected between any 2 voltages, providing that they
are at least 1.5V below V+ and no lower than V-.

TL/H/5104-6

Outputs may be run in saturation with no adverse effects,
making it possible to directly drive logic. The effective saturation resistance of the output transistors, equal to RE plus
the transistors' collector reSistance, is about 50!!.. 'It's also
possible to drive LEOs from rectified AC with no filtering. To
avoid oscillations, the LED supply should be bypassed with
a 2.2 p.F tantalum or 10 p.F aluminum electrolytiC capacitor.

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:

VOUT = VREF ( 1 +

:~)

MODE PIN USE
Pin 9, the Mode Select input,' permits chaining of multiple
LM3915s, and controls bar or dot mode operation. The follOwing tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).

+ IADJ R2

Dot Display, Single LM3915 Driver: Leave the Mode Select pin open circuit.
Dot Display, 20 or More LEOs: Connect pin 9 of, the first
driver in the series (i.e., the one with the lowest input voltage comparison pOints) to pin 1 of the next higher LM3915
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30 or more LED displays.
The last LM3915 driver in the chain will have pin 9 left open.
All prevjous drivers should have a 20~' resistor in parallel
with LED #9 (pin 11 to VLED).

TL/H/51 04-5

Since the 120 p.A current (max) from the adjust terminal
represents an error term, the reference was designed to
minimize changes of this current with V + and load changes.
For correct operation, reference load current should be between 80 p.A and 5 mAo Load capaCitance should be less
than 0.05 p.F.

Mode Pin Functional Description
This pin actually performs two functions. Refer to the simplified block diagram below.

CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant despite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead ,to a number of novel displays or ways of indicating input overvoltages, alarms, etc.

Block Diagram of Mode Pin Function
OUTPUT NO. 9

CONTROLLED DRIVE {
(FROM COMPARATORSI

"""",---f---.-I
v2

The LM3915 outputs are current-limited NPN transistors as
shown below. An internal feedback loop regulates the transistor drive. Output current is held at about 10 times the
reference load current, independent of output voltage and
processing variables, as long as the transistor is not saturated.
'High for bar

4-45

TLlH/5104-7

~ r-----------------------------------------------------------------------------~

:;;,
CO)

::E

Mode Pin Functional Description
(Continued)

,

'

'...I

DOT OR BAR MODE SELECTION

OTHER DEVICE CHARACTERISTICS

The voltage at pin 9 is sensed by comparator C1, nominally
referenced to (V+ - 100 mV). The chip is in bar mode
when pin 9 is above this level; otherwise it's in dot mode.
The comparator is designed so that pin 9 can be left open
circuit for dot mode.
Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than 20
mV below V+ for bar mode and more than 200 mV below
V+ (or open circuit) for dot mode. In most applications, pin
9 is either open (clot mode) or tied to V + . (bar mode). in bar
mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.

The LM3916 is relatively low-powered itself,and since any
number of LEOs 'can be powered from about 3,V, it is a very
efficient (lisplay driver. Typical standby supply current (all
LEOs OFF) is 1.6 mAo However, any reference loading adds
4 times that current drain to the V + (pin 3) supply input. For
example, an LM3916 with a 1 mA reference pin load (1.3k)
would supply almost 10 mA to every LED while drawing only
10 mA from its V+ pin supply. At full-scale, the Ie is typically
drawing less than 10% of the current supplied to the display.
The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and often an annoying flicker.
An "overlap" is built in so that at no time are all segments
completely off in the dot mode. Generally 1 LED fades in
while the other fades out over a mV or more of range. The
change may be much more rapid between LED # 10 of one
device and LED # 1 of a second device "chained" to the
first.

DOT MODE CARRY
In order for the display to make sense when multiple
LM3915s are cascaded in dot mode, special circuitry has
been included to shut off LED # 10 of the first device when
LED # 1 of the second device comes on. The connection for
ca!;cading, in dot mode has already been described and is
depicted below.
'

Application Hints

As long as the input signal voltage is below the threshold of
the second LM3915, LED # 11 is off. Pin 9 of LM3915 # 1
thus sees effectively an open circuit so the chip is in dot
mode. As soon as the input voltage reaches the threshold
of LED # 11, pin 9 of LM3915 # 1 is pulled an LED drop
(1.5V or more) below VLED. This condition is sensed by
comparator C2, referenced 600 mV below VLED. This forces
the output of C2 low, which shuts off output transistor Q2,
extinguishing LED # 1O.

The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of ,the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from signal sources, reference ground and bottom of the resistor string to a single point very near pin 2 is
the best solution.
Long wires from VLED to LED anode common can cause
oscillations. Depending on the severity of the problem
0.05 JLF to 2.2 JLF decoupling capacitors from LED anode
common'to pin 2 will damp the circuit. If LED anode line
wiring is inaccessible, often similar decoupling from pin 1 to
pin 2 will be sufficient.
If LED turn ON seems slow (bar mode) or several LEOs light
(dot mode), oscillation or excessive noise is usually the
problem. In cases where proper wiring and bypassing fail to
stop oscillations, V+ voltage at pin 3 is usually below suggested limits. Expanded scale meter applications m,ay have
one or both ends of the internal voltage divider terminated
at relatively high value resistors. These high-impedance
ends should be bypassed to pin 2 with at least a 0.001 JLF
capacitor, or up to 0.1 JLF in noisy environments.

VLED is sensed via the 20k resistor connected to pin 11.
The very small current (less than 100 ,.tA) that is diverted
from LED #9 does not noticeably 'affect its intensity.
An auxiliary current source at pin 1 keeps at least 100 JLA
flowing through LED # 11 even if the input voltage rises high
enough to extinguish the LED. This ensures that pin 9 of
LM3915 # 1 is held low enough to force LED # 10 off when
any higher LED is illuminated. While 100 JLA'does not 'normally produce significant LED illumination, it may be noticeable when using high-efficiency LEOs in a dark environment.
If this is bothllrsome, the simple cure is to shunt LED # 11
with a 10k resistor. The 1V IR drop is more than the 900 mV
worst case required to hold off LED # 10 yet small enough
that LED # 11 does not conduct significantly.

Cascading LM3915s In Dot Mode

....
~

ND.1D

11

10

u +

MODE

TL/H/5104-B

4-46

Application Hints (Continued)
Power dissipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEOs
programmed to 20 mA the driver will dissipate over 600 m~.
In this case a 7.50. resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 p.F solid tantalum capacitor
to pin 2.

Display circuits using two or more LM3915s for a dynamic
range of 60 dB or greater require more accurate detecti?n.
In the preCision half-wave rectifier of Figure 2 the effective
diode offset is reduced by a factor equal to the open-loop
gain of the op amp. Filter capacitor C2 charges through R3
and discharges through R2 and R3, so that appropriate selection of these values results in either a peak or an average
detector. The circuit has a gain equal to R2/R1.
It's best to capacitively couple the input. Audio sources frequently have a small DC offset that can cause significant
error at the low end of the log display. Op amps that slew
quickly, such as the LF351 , LF353, or LF356, are needed to
faithfully respond to sudden transients. It may be necessary
to trim out the op amp DC offset voltage to accurately cover
a 60 dB range. Best results are obtained if the circuit is
adjusted for the correct output when a low-level AC signal
(10 to 20 mV) is applied, rather than adjusting for zero output with zero input.
For precision full-wave averaging use the circuit in Figure 3.
Using 1% resistors for R1 through R4, gain for positive and
negative signal differs by only 0.5 dB worst case. Substituting 5% resistors increases this to 2 dB worst case. (A 2 dB
gain difference means that the display may have a ± 1 dB
error when the input is a nonsymmetrical transient). The
averaging time constant is R5-C2. A simple modification
results in the precision full-wave detector of Figure 4. Since
the filter capacitor is not buffered, this circuit can drive only
high impedance loads such as the input of an LM3915.

TIPS ON RECTIFIER CIRCUITS
The simplest way to display an AC signal using the LM3915
is to apply it right to pin 5 unrectified. Since the LED illuminated represents the instantaneous value of the AC waveform, one can readily discern both peak and average values
of audio signals in this manner. The LM3915 will respond to
positive half-cycles only but will not be damaged by signals
up to ±35V (or up to ± 100V if a 39k resistor is in series
with the input). It's recommended to use dot mode and to
run the LEOs at 30 mA for high enough average intensity.
True average or peak detection requires rectification. If an
LM3915 is set up with 10V full scale across its voltage divider, the turn-on point for the first LED is only 450 mV. A
simple silicon diode rectifier won't work well at the low end
due to the 600 mV diode threshold. The half-wave peak
detector in Figure 1 uses a PNP emitter-follower in front of
the diode. Now, the transistor's base-emitter voltage cancels out the diode offset, within about 100 mV. This approach is usually satisfactory when a single LM3915 is used
for a 30 dB display.

RJ
Ik

v+ 15V TO nVI
R2

RI
10k

R4
Ik
INPUT*-1_~""'-I

lOOk

01
IN914

.........*'-1......- t -

CI
1 ~F

OUTPUT
INPUT

D2

-11-""",.".....--~f---t

01,02: lN914 or lN4148

R2

Average

Peak

R2

lk

lOOk

R3

lOOk

lk

1M

RJ

lOOk

Rl - R2forAv - 1
Rl - R2/Rl0 tor Av - 10
Cl - 10/RI

,~C Couple

':'

TL/H/51 04-9

FIGURE 1. Half·Wave Peak Detector

TL/H/5104-10

FIGURE 2. Precision Half·Wave Rectifier
C2

0.47
Cl
0.2

-.J

INPUT.

R4

1-4_--"",,.,..--....--,,,,,,.,..--.
200k

Rl
lOOk R2
lOOk

OUTPUT

01,02: lN914 or lN4148

TLlH/5104-11

FIGURE 3. Precision Full·Wave Average Detector
4-47

~r---------------------------------------------------------------'

'.-

m
~

Application Hints (Continued)

....

R6
20Dlc

&1

R4

0.2,

INPUT

--1
1

D4

200k ,

~"'---"NIr---"'--~~I---4
Rl

lOOk R2
lOOk

01,02,03,04: lN914or lN4148

TL/H/S104-12

FIGURE 4. P.,.clslon Full-Wave Peak Detector
CASCADI~G THE LM3915
To display signals of 60 or 90 dB dynamic ,range, multiple
LM3915s can be easily cascaded. Alternatively, i~ is possible to cascade an LM3915 with LM3914s for alogllinear
display or with an LM3916 to get an extended range VU
meter.
A simple, low cost approach to cascading two LM3915s is
to set the reference voltages of the two chips 30 dB apart
as in Figure 5. Pot~tiQmeter R1 is used to adjust the full
scale voltage of LM3915 #1 to 316 mV nominally while the
second IC'" reference i~ set at 10V by R4. The drawback of
this method is that the threshold of LED #1 is only 14 mV
and, since the LM3915, can have an offset voltage as high
as 10 mV, large errors can occur. This technique is not recommended for 60 dB displays requiring, good accuracy at
the first few display thresholds.

to,the lower LM3915 by 30 dB. Since two 1% resistors can
set the 'amplifier gain within ± 0.2 dB, a gain trim is unnecessary. However, an op amp offset voltage of 5 mV will shift
the first LED threshold as much as 4 dB, so that an offset
trim may be required. Note that a single adjustment can null
out offset in both the precision rectifier and the 30 dB gain
stage. Alternatively, instead of amplifying, input signals of
sufficient amplitude can be fed directly to the lower LM3915
and attenuated by 30 dB to drive the second LM3915.
To extend this approach to get a 90 dB display, another 30
dB of amplification must be placed in the signal path ahead
of the lowest LM3915. Extreme care is required as the'lowest LM3915 di!lplays input signals down to 0.5 mVI Several
offset nulls may be required. High currents should not share
the same path as the low level signal. Also power line wiring
should be kept away from signal lines.

A better approach shown in Figure 6 is to keep the reference at ,10V for both LM3915s and amplify the input signal

LM3915
NO.1

LM3915
NO.2

.,1,),,'1

-

TL/H/5104-13

FIGURE 5. Lovi Cost'Clrcoltfor60 dB Display
4-48

Application Hints (Continued)

LM3915
NO.2

LM3915
. NO.1

INPUT
(lOV FULL S.CALE)
TLlH/5l04-14

FIGURE 6. Improved Circuit for 60 dB Display
The circuit in Agure 8 shows how to add a LED intensity
control which can vary LED current from 9 mA to '28 mA.
The reference adjustment has some effect on LED intensity
but the reverse is not true.

TIPS ON REFERENCE VOLTAGE
AND LED CURRENT PROGRAMMING
SINGLE LM3915
The equations in Figure 7 illustrate how to choose resistor
values to set reference voltage for the simple case where
no LED intensity adjustment is required. A LED current of 10
mA to 20 mA generally produces adequate illumination.
Having 10V full-scale 'across the internal voltage divider
gives best accuracy by keeping signal level high relative to
the offset voltage of the internal comparators. However, this
causes 450 p,A to flow from pin 7 into the divider which
means that the LED current will be at least 5 mAo R1 will
typically be between 1 kn and 2 kn. To trim the reference
voltage, vary R2.

MULTIPLE LM3915s

Figure 9 shows how to obtain a common reference trim and
intensity control for two LM3915s. The two ICs may be connected in cascade for a 60 dB display or may be handling
separate channels for stereo. This technique can be extended for larger numbers of LM3915s by varying the values
of R 1, R2 and R3 in. inverse proportion to the number of
devices tied in. The ICs' internal references track within 100
mV so that worst case error from chip to chip is only 0.1 dB
for VREF = 10V.

LM3915

lM3915

RlO ZZk TVP

RlO 22k TVP RHI

RHI

r...llt/'ll'v-..,

r.Jlt/lllr- ..,
I

,

I

I

Rl

Adiust R2 to vary VREF
Pick Rl =

Pick R2

=

12.5V
ILED - VREF/2.2 kll
(VREF - 1.25V)
1.25V/RI

+

0.08 rnA

TL/H/5l04-15

FIGURE 7. Design Equations for Fixed LED Intensity

'9 mA

<

ILED

<

28 mA

@

VREF

=

10V

TLlH/5l04-16

FIGURE 8_ Varying LED Intensity

4-49

....

~r-------------------------------------------------------------~

~

:::Ii!

Application Hints (Continued)
10

...I

LM381&
NO.1

LM3Il&

NO.2

TL/H/5104-17

FIGURE 9. Independent Adjustment of Reference Voltage and LED Intensity for Multiple LM3915s
The scheme in Agure 10 is useful when the reference and
LED intenSity must be adjusted independently over a wide
range. The RHI voltage can be adjusted from 1.2V to 10V
with no effect on LED current. Since the internal divider here
does not load down the refe~ence, minimum LED current is
much lower. At the minimum recommended. reference load
of 80 '",A, LED current is about 0.8 mA. The resistor values
shown give a LED current range from 1.5 mA to 20 mA.

Other Applications
For increased resolution, it's possible to obtain a display
with a smooth transition between LEOs. This is accomplished by varying the reference level at pin 6 by 3 dBp-p as
shown in Figure 11. The Signal can be a triangle, sawtooth
or sine wave from 60 Hz to 1 kHz. The display can be run in
either dot or bar mode.
.
When an exponentially decaying RC discharge waveform is
applied to pin 5, the LM3915's outputs will switch at equal
intervals. This makes a simple timer or sequencer. Each
time interval is equal to RCt3. The output may be used to
drive logic, opta-couplers, relays or PNP transistors, for example.

At the low end of the intensity adjustment, the voltage drop
across the 510n current-sharing resistors is so small that
chip to chip variation in reference voltage may yield a visible
variation in LED intenSity. The optional' approach shown of
connecting the bottom end of the Intensity control pot to a
negative supply overbomes this problem by allowing a larger
voltage drop across the (larger) current-sharing resistors.

Typical Applications

LM3915
NO.1

r

70 L:;IS:- -,

I
I
I
I
I
I

I
I
I
I
I
I

~

-15Y

LM3915
NO.2

510

510

b... ___ .J

'Optional elreuR for Improved Intensily
matching at low curren'!'. SII9 text.
TL/H/5104-18

FIGURE 10. Wide-Range Adjustment of Reterence Voltage and LED Intensity for Multiple LM3915s

4-50

Typical Applications (Continued)

LM3I16

Uk
1.&..

INPUT
(UVTO '.V)

3.5Vp.,
IDHlTO 1kHz

TLlH/5104-19

FIGURE 11. OV to 10V Log Display with Smooth Transitions
Extended Range VU Meter

...

• 0..

"no"

UUhl
...E

L..---t--t------...- - - - - - -....---+---+---...... IIZV .. 2IV)

-!-------------------'

IIDV FULL ICALE'·'...........

This application shows that the LED supply requires minimal filtering.

L..____________________

*Sea Application Hints for optional Peak or Average Detector.

t Adjust R3 for 3 dB difference between LED

..
...

i.11t

-.~:::

Ik

# 11

and LED #12.
TL/H/51 04-20

Vibration Meter
..0
NO.1

LED

10.11

LED

Threshold

1

60mV
80mV
110mV
160mV
220mV
320mV
440mV
630mV
890mV
1.25V

2

-+

c:::::::I PIEZOELECTRIC
TRAI8DUCER

,.

"
":'

TLlH/5104-21

4-51

3
4
5
6
7
8
9
10

III

.... r---------------------------------------------------------------------------------,

~

g:

Typical Applications (Continued)

:::&

....I,

..

Indicator and Alarm, Full-Scale Changes DI~play From Dot to Bar

•

~III ~ r

III ~ , III ~

'111~ , III ~ III

, iii

'111

~ r III

~

'111

27k

ND.1I

11

"

"

I.

15

12

13

11

15k

.....-..J'

-¥

'A:LO

SI"

rDI
tNa14

DOT·8AR*
SWITCH

REF
OUT

RHI

-¥ ••-\~v

3

"'01

'N21I~

"

LM3I15

v'

r--

LED

LED
NO.1

I!..-

1

INPUT

U.

REF

"OJ

MODE

'::"

•

-¥

'The input to the dot bar switch may be taken from cathodes of other LEOs.

821

1011**

3.

120

.p

Display will change to bar as soon as the LED so selected begins to light.

'

"BRIGHTNEss"

"Optional. Shunts 100 ,.A auxiliary sink current away from
LED #1.
TUH/5104-22

60 dB Dot Mode Display

..

,.
HI

....,
LEO~

10.1

-li4

f~ f
11

-I'
~ f~ ~.III ,~ f
'"
-41

.

n

v-

L-J'

-45

11

..

11

(,ZVT02lVl

~-3I -71 -24 -2, -11 -,6 -12
III
~ f ~ f~ r~ f .;~ f ~f ,~ f~ ,~ ,~ f ~ ~.
,.;
-42

-.11

'"

M

13

-31

"

,

,. "-

11

',."
"
10

'~LO

* *
..J;.Cl
-Xu,

118
6

I.

n

'""

LMmI'

3

LED
NO.l1

AHI

REF
OUT

RE'

"OJ

v-

MODE

• •

I!...- 7

1

AI
I.

....

,,,.
R5

I~~
~3

'*

.
,. '"I. .

..

3

-11

-11

I.B

-3

f'" ;,.; r ~ f~ rL
'" . •
III

~

ED

D.2D

,3

1.

,2

11

RE.
OUT

RE'

'0

LMI81i

RLO

SI.

~

5

RHI

I!....-'

,OJ

•

,I

MODE

M2

.,

"

U.

R3

U ..

*

"='

,IIPUT

'Optional. Shunts 100 ,.A auxiliary sink current away from LED # 11.

('DY 'ULL.acALE)

TL/H/5104-23

4-52

Typical Applications (Continued)
Driving Vacuum. Fluorescent Display
v'

1lyro 15V

'N",

FILAMENT
LD

FILAME~I

VACUUM flUORESCENT
BAR GRAPH

R16
I"

SRID

':"

'Rl'

Rl1

R'

R12

R.

R13

R'

R"
R'S

"

R'
4.7k

16

17

15

14

13

11

12

10

lM3815

v-

v'

-¥
,---- ----- f------,
~~
j

3 '

---.J'

I

I

I

I
I

o"
AUDIO...J
INPUT,

R.
'IIIk

I

AI

:'
...

'OOk

'!,

....

T
U

..li-'-..,

I

'.

RLD

REF
OUT

'-¥

MODE

R4
12k

~

I
I
I

R'
7.5k
':"

I

r~

REF

, 'OJ, •

RH.

r

I
I
I
I
I
I
I
I
t
'.
I ______________
~o
l:.
JI.
-5V

S1G

A7 thru A15: 10k ± 10%
Dl, D2: lN914 or lN4148
'Half-wave peak detector,
See Application Hints.

-11V

TLlH/51 04-24

Low Current Bar Mode Display

AY AY AY ~ AY AY AJr AY AY AY LED
1ZZV~~-1,...LE~D......IH...."'....~I-9.+1~*t-i"....~'"'...~...."',NO.,D
yo

10,1

ID

LMHII

+

l'U

.....

112

Supply current drain is only 15 mA with ten LEDs illuminated.

4-53

TLlH/5104-25

--

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~

:IE.

Typical Applications (Continued)

...

Driving Liquid Crystal Display
LIQUID CRYSTAL BAR GRAPH

REF
ADJ
8

MODE

9

10k

'::"

1N4001

DDT
BAR

II

22 pF

T1

'::"
TLlH/5104-26

Bar Display with Alarm Flasher
'.

. ~N~ ~N~ ~N~

~ 'N~
LED
NO.1

~

18

11

16

100

.

'N~ ~N~ ~N~ ~
'N~ ~N~ 'N

~

15

14

13

12

frED
NO.IO
10

11

;~

LM3815

y+
L-JI

*

3

Rto

'*

SIG

15

Full·scale causes th;. full bar display to flash. If the
iunction of AI and Cl Is connected to a dlffetenl LED
cathode, the display will flash when that LED lights,
and at any higher Input signal.

Rl
1k

RHI
8

CI
II1O.F

REF OUT REF ADJ MODE
7
9

-¥

470

_...

Uk

TL/H/5104-27

4-54

Typical Applications (Continued)
Precision Null Meter
v'C'VTOIIVl

LED
NO.n

LIlli'.

1.

.

LED
00.1

LM",

....
VC-iVTD-lIV1

U

+

x....
Logarithmic response allows coarse and fine adiustments without chenging scale.

,"'UT

'="

Resolution rangeo from 10 mV at VIN - 0 mV to
500 mV at V,N - ±1.25V.
TLlH/51 04-28

v-

(-IVTO-lIV1

Operating with a High Voltage Supply (Dot Mode Only)
4IV

...
IW

Uk

IW

':4102

"111'
LED
NO.1

...Fill " ,

,
'Ill. 'Ill' .. Ill . ~111 ~ Ill' 'Ill
F-' 'Ill
I.

I.

11

"

I.

n

"

LED
NO. 10
10

11

LM3I1&

,

V'

---1'
3.4V·
The LED currents are approximately 10 mA, and
the LM3915 outputs operate In saturation for

-¥
~

RLO

-¥

IN::T

RHI

REF
OUT

l!.-

1

RE.
'D.

-¥

MJ:E

III

minimum dissipation.
'This point is partially regulated and decreases in
voltage with temperature. Voltage requirements
of the LM3915 also decrease with temperature.

SlG

2NZl85'*'-

...

*
4-55

TLlH/51 04-29

Typical Applications (Continued)
UghtMeter
LEO~

NO.1

,#~ ,id~ rid, ,fd, rid,
~, r#~ r#~. ,#~ r#~ ,#'-,#'
-~~ ~~ f-'rid~ r~'-rid, f~ f~
f-'
r,
~

,.

11

L..Jl

.¥

"

13

12

AEF

AEF

A",
8,

OUT

AOJ

1~

11

,.

,.

SI.

1

18

• •

1'2k

*

v-

MODE

,8

1

*

..

' 3

IS

'" 13

14'

12

~2~

•

SIO .

•

A",

•

AEF

AEF

OUT

AOj

Uk

~r:

IM3D1A"

"

12Dk
2%

'3+

·Re~stor

LM3DI",

, • T

1111P'

,H

MODE

II

i:-

3 +

4

,.

Uk

2%

1M"

~~
~~
-r

~~

.

fiEO

I.

",

-1-

•

7

i

-=-av

11

,j

LM3I15

ALa

,",

':"

~N

~'

'

LM3I15

ALa

3

,'
Off

,.

..

v-

~'

,

'I1G

value selects exposure

' 1/2 flstop resolution

·'

Ten flstop range (1000:1)
Typical supply current Is 8 rnA,
TL/H/5104-30

A"dlo PO~!I,r Meter,
1ZVTlIIV

Connection Diagram
Dual-In-Llne Package

1. LED NO.!

LED NO.1

17

v-

..

L11311I

LED NO.3

11 lED NO.4

DIVIDER 4
Ilm,'ENDI
SIGNAL INPUT

-

DIVIDER 6
IHIGH ENOl

.,

AI

REFERENCE OUTPUT 7
REFERENCE ADJUST •
MODE SELECT

HZ

U.

LDUItRAKER

TL/H/51 04-32

Top View
Order Number LM3915N
See NS Package Number N18A

TUH/5104-31

"

.1'

Load
Impedane.

R1

40

10k

80

18k

160

30k

See Application Hints for optional Peak
or Average Detector

,-----------------------------------------------------------------------------, r

5

Definition of Terms
Absolute Accuracy: The difference between the observed
threshold voltage and the ideal threshold voltage for each
comparator. Specified and tested with 10V across the internal voltage divider so that resistor ratio matching error predominates over comparator offset voltage.

measured at the current source outputs. As the forward voltage of an LED does not change significantly with a small
change in forward current, this is equivalent to changing the
voltage ilt the LED anodes by the same amount.

CD

.....

CI1

. Une Regulation: The average change in reference output
voltage (VREF) over the specified range of supply voltage
(V+).

Adjust Pin Current: Current flowing out of the reference
adjust pin when the reference amplifier is in the linear region.

Load Regulation: The change in' reference output voltage
over the specified range of load current (IL(REF).

Comparator Gain: The ratio of the change in output current
(ILEO) to the change in input voltage (VIN) required to produce it for a comparator in the linear region:

Offset Voltage: The differential input voltage which must
be applied to each comparator to bias the output in the
linear region. Most significant error whel] the voltage across
the intemal voltage divider is small.' Specified and tested
with pin 6 voltage (VRHI) equal to pin 4 voltage, (VRLO).
Relative Accuracy: The difference between any two adjacent threshold pOints. Specified and tested with 10V across
the 'internal voltage divider so that resistor ratio matching
error predominates over comparator offset voltage,

Dropout Voltage: The voltage measured at the current
source outputs required to make the output current fall by
10%.
.
Input Bias Current: Current flowing out of the signal input
when the input buffer is in the linear region.
LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLEO) as

•
4-57

~
.-

,-------------------------------------------------------------------------,

::d
:5 p N a ti 0 11: a I

S e m i con due to r .

LM39,16 Dot/Bar Display Driver
.Gener~1

Description

The LM3916 is a monolithic integrated circuit that senses.
analog voltage levels and drives ten LEOs, LCOs or vacuum
fluorescent displays, providing an electronic version of the
popular VU meter. One pin changes the display from a bar
graph to a moving dot display. LED current drive is regulated and programmable, eliminating the need for current limiting resistors. The whole display system can operate from a
single supply as low as 3V or as high as 25V.
The IC contains an adjusta!>le voltage reference and an accurate ten-step voltage divider. The high-impedance input'
buffer accePts signals down to ground and tip to within 1.5V
of the positive supply. Further, it needs no protection
against inputs of ± 35V. The input buffer drives 10 individual
comparators referenced to the precision divider. Accuracy is
typically better than 0.2 dB.
Audio applications include average or peak level indicators,
and power meters. ReplaCing conventional meters with an
LED bar graph results in a faster responding, more rugged
display with high visibility that retains the ease of interpretation of an analog display.
The LM3916 is extremely easy to apply. A 1.2V full-scale
meter requires only one resistor in addition to the ten LEOs.
One more resistor programs the full-scale anywhere from
1.2V to 12V independent of supply Voltage. LED brightness
is easily controlled with a Single pot.

The LM39.16 is very versatile. The outputs can drive LCOs,
vacuum fluorescents and. incandescent bulbs as well as
LEOs of any color. Multiple deVices can be cascaded for a
dot or bar mode display for increased range and/or resolution. Useful in other applications are the linear 'LM3914 and
the logarithmic LM3915.· .

Features
•
•
•
•
•
•
•
•
•
•
•
•

Fast responding electonic VU meter'
Drivers LEOs, LCOs, or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 70 dB
Internal voltage reference from 1.2V to 12V
Operates with single supply of 3V to 25V
Inputs operate down to ground
Output current programmable from 1 rnA to 30 rnA
Input withstands ± 35V without damage or false outputs
Outputs are current regulated, open collectors
Directly drives TTL or CMOS
The internal 10-step divider is floating and can be referenced to a wide range of voltages
The LM3916 is rated for operation from O·C to + 70·C. The
LM3916N is available in an 18-lead molded DIP package.

Typical Applications
OV TO 10V VU Meter
-28

-10

-1

-5

+1

-I

-3

+2

+3

VU

r-~--~--~--~--~--~--~--~--~--~_o 3V ';YLED .;y+

I

I
I

LED
, NO.1
CI

/1/

/1/

/1/

18

11

16

15

14

RLO

I

LED

13

/1/

12

11

10

SIG

,

"l

v+
12YTO 20Y

+~)

/1/

LM3II16

I
I

I
L _____ ...--+_...

VREF= ,.25V(1

/1/

,

DR 10"F"I'
ELECTROLYTIC

/1/

LED
NO.IO

TANT~~:~...L
ALUMINUM

/1/

+ R2X80I£A

9

RI
Uk

R2
7.Sk

Note 1: Capacitor Cl is required H
leads to the LED supply are 6' or
longer.

Note 2: CircuR as shown is wired for
dot mode. For bar mode, connect pin
9 to pin 3. VLEO must ba kept below
7V or dropping resistor should be
used to limit IC power dissipation.

=~+ VREF
Rl

2.2kO

TL/H17971-1

4-58

Absolute Maximum

Rati~gs

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation (Note 5)
Molded DIP (N)
1365 mW
Supply Voltage
25V
25V
Voltage on Output Drivers

Input Signal Overvoltage (Note 3)
Reference Load Current

10mA
- 55·C to + 150·C

Storage Temperature Range

Lead Temperature (Soldering. 10 seconds)

Electrical Characteristics (Notes 1 and 3)
Parameter

I

±35V
-100mVtoV+

Divider Voltage

I

Conditions (Note 1)

Min

260·C

I I
Typ

Max

3

10

mV

3

15

mV

I

Units

COMPARATORS
Offset Voltage, Buffer and First
Comparator

ov,;: VRLO = VRHI

Offset Voltage, Buffer and Any Other Comparator

OV';: VRLO

=

ILED

,;: 12V,

1 mA

=

VRHI ,;: 12V,ILED

Gain (AILEDI AVIN)

I{REEL = 2 mA,lLED

Input Bias Current (at Pin 5)

OV';: VIN ,;: (V+ -1.5V)

=

Input Signal Overvoltage

No Change in Display

=

1 mA
3

10 mA

8
25

-35

mA/mV
100

nA

35

V

VOLTAGE DIVIDER
Divider Resistance

Total, Pin 6 to 4

8

12

17

Relative Accuracy (Input Change
Between Any Two Threshold POints)

kO

(Note 2)
-1 dB ,;: VIN ,;: 3 dB
-7dB';: VIN';: -1 dB
-10dB';: VIN';: -7dB

0.75
1.5
2.5

1.0
2.0
3.0

1.25
2.5
2.5

dB
dB
dB

Absolute Accuracy

(Note 2)
VIN = 2,1,0, -1 dB
VIN = -3, -5 dB
VIN = -7, -10, -20dB

-0.25
-0.5
-1

+0.25
+0.5
+1

dB
dB
dB

1.28

1.34

V

VOLTAGE REFERENCE
1.2

Output Voltage

0.1 rnA,;: IL(REF) ,;: 4mA,
V+ = VLED = 5V

Line Regulation

3V,;: V+ ,;: 18V

0.01

0.03

%/V

Load Regulation

0.1 rnA ,;: IL(REF) ,;: 4mA,
V+ = VLED = 5V

0.4

2

%

Output Voltage Change with Temperature

O·C,;:TA';: +70"C,IL(REF)
V+ = VLED = 5V

=

1 rnA,

%

1

Adjust Pin Current

75

120

p.A

OUTPUT DRIVERS

=

=

LED Current

V+

LED Current Difference (Between Largest
and Smallest LED Currents)

VLED
VLED

LED Current Regulation

2V ,;: VLED ,;: 17V

Dropout Voltage

ILED(ON) = 20 mA
AILED = 2mA

Saturation Voltage

ILED

Output Leakage, Each Collector

Bar Mode (Note 4)

Output Leakage

Dot Mode (Note 4)

VLED

=
=

=

=

5V,IL(REF)

5V, ILED
5V, ILED

=
=

1 mA

7

2 mA
20 mA
ILED = 2mA
ILED = 20mA

@

VLED

2.0 mA, IL(REF)

=

=

0.4 mA

60
4-59

13

mA

0.4
3

mA
rnA

0.1
1

0.25
3

mA
mA

1.5

V

5V,

Pins 10-18
Pin 1

10
0.12
1.2

0.15

0.4

V

0.1

100

p.A

0.1

100

p.A

150

450

p.A

•

~:
G)
(II)

:::Ii

Electrical Characteristics (Note 1) (Continued)

I

Parameter

..J

!~:;,

,I"

,. I

Conditions (Note 1)

I.

Min

,SUPPLY CURRENT

Jyp

"

I,

Max

1

4.2
9.2

I

Units

\,
"

Standby Supply Current
(All Outputs Off)

1

V+ = +5V,IL(REF) = 0.2 mA
V:= +20V IL(REF) = 1.0mA

I:

1

2.4
6.1

; 1

mA
mA

Note 1: Unless otherwise stated, all specifications apply with the following conditions:
3 Voc ,;; V+ ,;; 20 Voe

-0.015V ,;; VRLO ,;; 12 Voe

TA ~ 25"C, IL(REF) ~ 0.2 mA, pin 9 connected to pin 3 (bar mode).

3 Voe ,;; VLEO ,;; V+

VREF, VRH!> VRLO ,;; (V+ - 1.5V)

For higher power dissipations, pulse testing is used.

-0.Q15V ,;; VRHI ,;; 12 Voe

OV ,;; VIN ,;; V+ - 1.5V

' . :'

Note 2: Accuracy is measured refer~, to + 3 dB ~ + 10.0,00 Yoc a,t pi,n 5, ,"';Hh -1: 1Q.000 Voc at pin 6, lind 0.000 Voe at pin 4. At lower !UII-scale voltages, buffer
and comparator offset voltage may add,signiflcant error. See tsbIe for threshold vOltages.
' '
Note 3: Pin 5 input current must be limited to

± 3 mAo The addition of a 39k resistor in series wHh pin 5 allows ± 1OOV signals wHhout damage.

Note 4: Bar mode results when pin 9 is wHhin 20 'mV of V+. Dot mode results when pin 9 is pulled at least 200 mV belowV+. LED #10 (pin 1'0 output current) is
disabled if, pin 9 is pulled 0.9V or more below VLEO.
'
'
Note 5; T~e maximum junction temperature ,of the LM3916 Is l00"C. Devices must be derated lor operation at elevated temperatures. Junction to ambient thermal
resistance Is 55"C/W for the molded DIP (N package).

LM3916 Threshold Voltage (Note 2)
Volts

dB

.,

.

3
2'± %
1 ± %
o± %
-1 ± Yz

Volts

dB

Min

Typ

Max

9.985
8.660
7.718
6.879
5.957

10.000
8.913
"'7.943
7.079
6.310

10.015
9.173
8.175
7.286
6.683

-3 ± Yz
,-5 ± Yz
.c..7 ± 1
-10 ± 1
-29 ± 1

,.

,I:.

4·60

Min

Typ

Max

4.732
3.548
2.818
1.995
0.631

5.012
3.981
3.162
2.239
0.708

5.309
4.467
3.548
2.512
0.794

Typical Performance Characteristics

...
I:

e

.!
"

B.O

Supply Current vs
Temperature

Operating Input Bias
Current vs Temperature

5.1

5.4

i

i'l

52

It

I

5.0

....

i

r--

!

S.B

i'l

>

iii

21

TEMPERATURE I'C)

Reference Adjust Pin
Current vs Temperature

..
..

c

""!i;

I.

50

75

TE_RATURE I'CI

LED Current-Regulation
Dropout

14

~r--.....

82

I:

!Iia
c

~

I'...

18

lil

~

r---...

78

~

25

-21

51

100

75

20
"
1&
LED CURRENT emA)

TEMPERATURE I'CI

Input Current Beyond
Signal Range (Pin 5)

V+:2~

I

DIVIDER V' IOV

r-

TAl.

LED Current vs
Referenced Loading

70'1+

1.5

30

1.1

25

0.5

~

I'
-2

-3

...c~
::i
...

!

7 ~1'7

-40 -38 -21 -1' 0

10 20

30

C

....... ~

V

2.

.!

!
~

TA'25"'lV
15

/

10

1/
o

4D

o

O.S 1.1 1.5 2.0 U

3.0 3.5 4.0

REfERENCE LOAD CURRENT (mA)

s
;

o!

Total Divider Resistance
vs Temperature
1.1'

J

:=

=1.00

8.11
-21

~

=
!!

-1.1 -

-

./
25

TEMPERATURE rCI

~mRJED TO JOSIT1V~
SUPPLY VOLTAGE

""5V
TA a 2SOC

75

100

I

lOlA

~OO""

/

'--::

~""

I

r..

~ -2.0

DIVIDER PARALLEL
WITH STABLE
Ik RESISTOR

50

10

~ -1.5

./I'
£J
__

1.12

:; 1.88

a

DIVI~ER

1.04

_ -0.5

v

LM3Il

E. 1.16

!

Output Characteristics
12

1

~ I.DO
~

Common-Mode Limits

1.12

-

NEOATIVE COMMON-MODELIMIT INCLUDES GROUND
20

41

TEMPERATURE C'CI

BO

8G

.J

'.to""

ILtREFI-~""

I

/
1.2

0.4

1.6

OJ

I.D

OUTPUTVOLTAGEIVI
TL/H17971-3

4-61

~
.....

~

~----~--~------------------------------------------------------------------,

Block Diagram

(Showing Simplest Application)

::&
..J

,- - -

I'

-

-

LM3In -

LEO

-- - -,

'COMPARATOR
I OF 10

Y'

I
10

~------+--M

____

lOll

810

864
LED PROGRAM
CURRENT

l8lI

1291

REF
OUT

7

THIS LOAD
DETERMINES
LED
BRIGHTNESS

REFERENCE
yoLTAGE
SOURCE
1.2Y

1031

-

REF
ADJ

I

819

8

- I
I

923

I
y+~

1631

I
I
RLO I 4

708

MODE
SELECT
AMPLIFIER

~

IN

5

9

I
I

CONTROLS
TYPE OF
DISPLAY, BAR
OR SINGLE
LED

~
I~

+

l ____________ J

TLlHI7971-4

4-62

Functional Description
LM3916 Output Circuit

The simplified LM3916 block diagram is included to give the
general idea of the circuit's operation. A high input impedance buffer operates with signals from ground to 12V, and is
protected against reverse and overvoltage signals. The signal is then applied to a series of 10 comparators; each of
which is biased to a different comparison level by the resistor string.
In the example illustrated, the resistor string is connected to
the internal 1.2SV reference voltage. As the input voltage
varies from 0 to 1.2S, the comparator outputs are driven low
one by one, switching on the LED indicators. The resistor
divider can be connected between any 2 voltages, providing
that they are at least 1.SV below V+ and no lower than V-.

'::"

INTERNAL VOLtAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.2SV between the REF OUT (pin 7) and REF AOJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R1 and, Since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:
VOUT = VREF (1

TUH/7971-6

Outputs may be run in saturation with no adverse effects,
making it possible to directly drive logic. The effective saturation resistance of the output transistors, equal to RE plus
the transistors' collector resistance, is about soo. It's also
possible to drive LEOs from rectified AC with no filtering. To
avoid oscillations, the LED supply should be bypassed with
a 2.2 p.F tantalum or 10 p.F aluminum electrolytic capacitor.
MODE PIN USE
Pin 9, the Mode Select input, permits chaining of multiple
devices, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) direct/yto pin
3 (V+ pin).

+ :~) + IAOJ R2

Dot Display, Single LM3916 Driver: Leave the Mode Select pin open circuit.
Dot Display, 20 or More LEOs: Connect pin 9 of the first
drivers in the series (i.e., the one with the lowest input voltage comparison points) to pin 1 of the next higher LM3916
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30 or more LED displays.
The last LM3916 driver in the chain will have pin 9 left open.
All previous drivers should have a 20k resistor in parallel
with LED #9 (pin 11 to VLEO).

TUH/7971-5

Since the 120 p.A current (max) from the adjust terminal
represents an error term, the reference was designed to
minimize changes of this current with V+ and load changes.
For correct operation, reference load current should be between 80 /LA and SmA. Load capacitance should be less
than O.OS p.F.

Mode Pin Functional Description
This pin actually performs two functions. Refer to the Simplified block diagram below.
Block Diagram of Mode Pin Function

CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant despite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead to a number of novel displays or ways of indicating input overvoltages, alarms, etc.

OUTPUT NO.9

CONTROLLED DRIVE {
(FROM COMPARATORS)

The LM3916 outputs are current-limited NPN transistors as
shown below. An internal feedback loop regulates the tranSistor drive. Output current is held at about 10 times the
reference load current, independent of output voltage and
processing variables, as long as the transistor is not saturated.

4-63

OUTPUT NO. 10

~f---I--_-r

.... ,-----------------------------------------------------------------------------,
~

~

::::IE

..J

Mode Pin Functional Description (Continued)

DOT OR BAR MODE SELECTION

. ,I· .

more) below VLED. This condition is sensed by comparato(
C2, referenced 600 mV below VLEO' This forces the output
of C2 low, which shuts off output trallsistorQ2, extinguishingLED #10.

The voltage at pin 9 is sensed by comparator Cl, nominally
referenced to (V + -100 mY). The chip is in bar mode when
pin 9 is above this level; otherwise it's in dot mode. The
comparator is designed so that pin 9 can be left open circuit
for dot mode.
Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than 20
mV below V+ for bar mode and more than 200 mV below
V+ (or open circui~, for dot mode. In most applications, pin
9 is either open (dot mode) or tied to V+ (bar mode). In bar
mode, pin 9 should be connected directly to pin 3. Large
c\lrrents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.

VLED is ~ensed via the 20k resistor connected to pin 11.
The very small current' (less than 100 p.A) that is diverted
from LED # 9 does not noticeably affect its intensity. '
An auxiliarY current source at pin 1 keeps at least 100 p.A
flowing through LED # 11 even if the input voltagEftises high
enough to extinguish the LED: This ensures that pin 9 of
driiler # 1 is held low enough to force LED # 10 off when
any higher LED is illuminated. While 100 J.i;J\ does not normally produce significant LED Illumination, it may be noticeable when using high-efficiency LEOs il'J,a:dark t;lnvironment.
If this is bothersome, the simple cure is to shunt LED # 11
(and LED #1) with a 10k resistbr. The 1V lR drop is more
than the 900 mV worst case required to' hold off LED' # 10
yet small enough that LED # 11 does not conduct significantly.
In some Circuits a number of outputs on the higher dElvice
are not used. Examples include the high resolution VU meter and the expanded range VU meter circuits .(see Typical
Applications). To provide the proper carry sense voltage in
dot mode, the LEOs of the higher driver IC are tied to VLED
through two series-connected diodes as shown in Figure 2.
Shunting the diodes with a 1k resistor provides a path for
driver leakage current.

DOT MODE CARRY
In order for display to make sense when multiple drivers are
cascaded in dot mode, special Circuitry has been' included
to shut off LED # 10 of the first device when LED # 1 of the
second device comes on. The connection for cascading in
dot mode has already been described and is depicted in
Figur8 1.
'
As long as the input signal voltage is below the thr!!shold of
the second driver, LED # 11 is off. Pin 9 of driver # 1 thus
sees effectively an open circuit so the chip is in dot mode.
As soon as the input voltage reaches the threshold of LED
# 11, pin 9 of driver # 1 is pulled an LED drop (1.5V .or

Vuo

Kt.
II

11

11

Ul311C/I&111

l.1l3I14/1&111

MO.I

10.2

u +

MODE

TL/HI7971-B

FIGURE 1. Cascading LM3914/15116 Series in Dot Mode
1N114 IN914

III

12

LMHI5. LM3516
NO.1

11

III

M

It

,.

13'

12

III

11

III

11

tMHI., LM3116
NO.2

Nt

TL/H/7971-9

FIGURE 2. C.scat\lng Drivers in Dot Mode with Pin 1 of Driver #2 Un\lsed

should be run at 20 mA to 30 mA,for high enough average
intenSity.
True average or peak detection requires rectification. If an
LM3916 is set up with 10V full scale across its voltage divider, the turn-on point for the first LED is only 450 mV. A
Simple silicon diode rectifier won't work well at the low end
due to the 600 mV diode threshold. The half-wave peak
detector in Figure (3 uses a PNP emitter-follower in front of
the diode. Now, the transistor's base-emitter voltage cancels out the diode offset, within about 100 mV. This approach is, usually satisfactory when a Single LM3916 is used
for a 23 dB display.

Mode Pin Functional
Description (Continued)
OTHER DEVICE CHARACTERISTICS
The LM3915 is relatively low-powered itself, and since any
number of LEOs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEOs OFF) is 1.6 mAo However, any reference loading adds
4 times that current drain to the V+ (pin 3) supply input. For
example, an LM3915 with a 1 mA reference pin load (1.3k)
would supply almost 10 mA to every LED while drawing only
10 mA from its V+ pin supply. At full-scale, the IC is typically
drawing less than 10% of the current supplied to the display.
The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and often an annoying flicker.
An "overlap" is built in so that at no time are all segments
completely off the dot mode. Generally one LED fades in
while the other fades out over a 1 mV range. The change
may be much more rapid between LED # 10 of one device
and LED # 1 of a second device cascaded.

Display circuits such as the extended range VU meter using
two or more drivers for a dynamic range of 40 dB or greater
require more accurate detection. In the precision half-wave
rectifier of 'Figure 4 the effective diode offset is reduced by a
factor equal to the open-loop gain of the op amp. Filter capaCitor C2 charges through R3 and discharges through R2
and R3, so that appropriate selection of these values results
in either a peak or an average detector. The circuit has a
gain equal to R2/R1.
It's best to capacitively couple the input. Audio sources frequently have a small DC offset that can cause significant
error at the low end of the log display. Op amps that slew
quickly, such as the LF351 , LF353 or LF356, are needed to
faithfully respond to sudden transients. It may be necessary
to trim out the op amp DC offset voltage to accurately cover
a 60 dB range. Best results are obtained if the circuit is
adjusted for the correct output when a low-level AC signal
(10 to 20 mV) is applied, rather than adjusting for zero output with zero input.

Application Hints
The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from signal sources, reference ground and bottom of the resistor string to a single point very near pin 2 is
the best solution.
Long wires from VLED to LED anode common can cause
oscillations. The usual cure is bypassing the LED anodes
with a 2.2 ,...F tantalum or 10 ,...F aluminum electrolytic capaCitor. If the LEd anode line wiring is inaccessible, often a
0.1 ,...F capacitor from pin 1 to pin 2 will be sufficient.
If there is a large amount of LED overlap in the bar mode,
oscillation or excessive noise is usually the problem. In
cases where proper wiring and bypassing fail to stop oscillations, V + voltage at pin 3 is usually below suggested limits.
When several LEOs are lit in dot mode, the problem is usually an AC component of the input signal which should be
filtered out. Expanded scale meter applications may have
one or both ends of the internal voltage divider terminated
at relatively high value resistors. These high-impedance
ends should be bypassed to pin 2 with 0.1 ,...F.
Power dissipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEOs
programmed to 20 mA the driver will dissipate over 600 mW.
In this case a 7.50. resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2,...F solid tantalum or 10 ,...F
aluminum electrolytic capacitor to pin 2.

V+ (IV TO 25VI
81
ll1k

,.
INPur*-4_""'IIr--I
84

01
11914

...............-

....-OUTPUT

82
1M

83

''''
'DC Couple
TL/H/7971-10

FIGURE 3. Half-Wave Peak Detector

,.

83
82

ll11Nr,
Cl
1';

INPUT"

~lMrl~_...D2......_

...

01.02: 1N914 or 1N4148

TIPS ON RECTIFIER CIRCUITS
The simplest way to display an AC signal using the LM3916
is to apply it right to pin 5 unrectified. Since the LED illuminated represents the instantaneous value of the AC waveform, one can readily discern both peak and average values
of audio signals in this manner. The LM3916 will respond to
positive half-cycles only but will not be damaged by signals
up to ± 35V (or up to ± 100V if a 39k resistor is in series
with the input). A smear or bar type display results even
though the LM3916 is connected for dot mode. The LEOs

Average Peak
R2

1k

R3

100k

R1

~

R2forAy

1k
~

R1

~

R2/10 for Ay

C1

~

10/R1

TL/H/7971-11

FIGURE 4. Precision Half-Wave Rectifier
4-65

100k

1
~

10

.... r---------------------------------------------------------------------------------,
U)

~
:IE

...

Application Hints (Continued)

For precision full-wave averaging U!19 the circllit in Figure 5.
Using' 1 % resistors for R1 through R4, gain for positivI! and
negative ,signal differs by only 0.5 dB worst case. Substituting 5% resistors increases this to 2 dB worst case: (A 2 dB
gain difference meansthat'the display may have a ±1' dB
error when the, input is a nonsymmetrical transient). The
averaging, time constant is R5.C2. A simple modification
results in the precision full-wave detector of FIgure 6. Since
the filter capacitor is not buffered, this circuit can drive only
high impedance loads such as the input of an LM3916.

fication Ct65. The LM3916's outputs con:espond to the meter indications specified with the omission of the - 2 VU
indication. The VU scale divisions differ slightly from linear
scale in order to 'obtain whole numbers in dB.

a:

Some of the most important specifications for an AC meter
are its dynamic'characteristics. These define how the meter
responds to transients and how fast the reading decays.
The VU meter is a relatively slow full-wave averaging type,
specified to reach 99% deflection in 300 ms and overshoot
by 1 to 1.5%. In engineering terms this means a slightly
underdamped second order response with a resonant frequency of 2.1 Hz and a Q of 0.62. FIgure 7 depicts a simple
rectifierIfilter circuit that meets these criteria.

AUDIO METER STANDARDS
VUMeter
The audio level meter most frequently encountered is the
VU,meter.lts characteristics are defined as the ANSI speci-

CZ
1.47
CI
O.Z

-.J

INPUT,

AI
61D

R5

2_

R4
ZOOk

Cl
D,Z

Hr--'\I\"""--+--~iIr---+

-.J

INPUT.

RI
lOOk RZ
lOOk

Z_
R4

04

Hr-......wlo-~-t---t..---+
RI
1 . 82
lOOk

OUTPUT

01,02,03,04: lN914 OR lN4148
Attack and decay time to DIN PPM
spec. Response down 1 dB for 10 ms
tone burst. Decays 20 dB in 1.5•.

01.02: lN914 or lN4148

TL/H/7971-12

TL/H/7971-13

FIGURE 5. Precision Full-Wave Average Detector

r.1

FIGURE 6. Precision Full-Wave Peak Detector

GAIN

R5

R6

10

100k
1M

43k
1OOk

R3

D.D47"F

3DDK

AUOIO~
INPUT

R4

IIDk

RI
2Dk R2
ZOk

R5

'RI

C3

Design Equatfona

"
01,

C2

2.0 0.56 ""F
1.0 0.056 ""F

1
R5- R6 - C2- C3

= "'rf=

177sec-2

C3

1 ( 1
1
1
1)
"'0
C2
R3 + R4
+ As + As = Q = 21,5 sec -

R3
Rl
OUTPUT

= 2R4
= R2 -<

R4

AI, A2: V. LF353
01,02: lN914 OR lN4148
'Reaches 99% level at 300 m. after applied
tone burst and overshoots 1,2%.

TL/H17971-14

FIGURE 7. Full-Wave Average Detector to VU Meter Specifications'

4-66

1

Application Hints (Continued)
Peak Program Meter

namic range, the LM3916 may be cascaded with the 3 dB/
step LM3915s. Alternatively, two LM3916s may be cascaded for increased resolution over a 28 dB range. Refer to the
Extended Range VU Meter and High Resolution VU Meter in
the Typical Applications section for the complete circuits for
both dot and bar mode displays.
To obtain a display that makes sense when an LM3915 and
an LM3916 are cascaded, the -20 dB output from the
LM3916 is dropped. The full-scale display for the LM3915 is
set at 3 dB below the LM3916's -10 dB output and the rest
of the thresholds continue the 3 dB/step spacing. A simple,
low cost approach is to set the reference voltage of the two
chips 16 dB apart as in Figure 5. The LM3915, with pin 8
grounded, runs at 1.25V full-scale. R1 and R2 set the
LM3916's reference 16 dB higher or 7.89V. Variation in the
two on-chip references and resistor tolerance may cause a
± 1 dB error in the -10 dB to -13 dB transition. If this is
objectionable, R2 can be trimmed.
The drawback of the aforementioned approach is that the
threshold of LED #1 on the LM3915 is only 56 mV. Since
comparator offset voltage may be as high as 10 mV, large
errors can occur at the first few thresholds. A better approach, as shown in Figure 9, is to keep the reference the
same for both drivers (10V in the example) and amplify the
input signal by 16 dB ahead of the LM3915. Alternatively,

The VU meter, originally intended for signals sent via telephone lines, has shortcomings when used in high fidelity
systems. Due to its slow response time, a VU meter will not
accurately display transients that can saturate a magnetic
tape or drive an amplifier into clipping. The fast-attack peak
program meter (PPM) which does not have this problem is
becoming increasingly popular.
While several European organizations have specifications
for peak program meters, the German DIN specification
45406 is becoming a de facto standard. Rather than respond instantaneously to peak, however, PPM specifications require a finite "integration time" so that only peaks
wide enough to be audible are displayed. DIN 45406 calls
for a response of 1 dB down from steady-state for a 10 ms
tone burst and 4 dB down for a 3 ms tone burst. These
requirements are consistent with the other frequently encountered spec of 2 dB down for a 5 ms burst and are met
by an attack time constant of 1.7 ms.
The specified return time of 1.5s to - 20 dB requires a 650
ms decay time constant. The full-wave peak detector of
FIGURE 6 satisfies both the attack and decay time criteria.

Cascading The LM3916
The LM3916 by itself covers the 23 dB range of the conventional VU meter. To display signals of 40 dB or 70 dB dy-

-10

-1

-6

-3

-1
10

LM3916

LM3916

Rl
1JIlk

VREFI ~ 1.25V
7.B9V
-1.25

~

6.31

~

VREF2 '" 7.B9V

16dS
RZ
9.D9k

INPUT I1.9V FULL-SCALE)

TL/H17971-15

FIGURE 8. Low Cost Circuit for 40 dB Display
-10

-7

-5

-3

RHI

6

REF
OUT
7

REF
ADJ

SIG
5

8

-=-

R3
Uk
RZ
33k

RHI
6

+2

REF
OUT

REF
ADJ

MODE

9

-=-

R4
6k

Rl
Uk

R5
7k

Rl + R2

-=-

-R-l-~6.31
~

+1

LM3911

LM3915

SIG
6

-1

16dS

INPUT
110V FULL SCALE)

FIGURE 9. Improved Circuit for 40 dB Display

4-67

TLlH17971-16

....

~r------------------------------------------------------------------------

~

:5

oauses 1 mA to flow from pin.7 into the divider which means
that the LED ourrent will be at least 10 mA: R 1 will typioally
be between 1 kfi and S kfi. To trim the reference voltage,
vary R2.

Application Hints (COntinued)
instead of amplifying, input signals.'of sufficient amplitude
oan be fed directly to the LM3916 and'attenuatedby:1,6'dB
to drive the LM3915.

The current In Agure 11 shoWs how'to add'S LED intensity
control which can vary LED ourrent from S mA to 28 mAo
Choosing VREF = SV lowers the ourrent drawn by the ladder, increasing the intensity adjustment range. The referenoe adjustment has some effect on LED intenSity but the
reverse is not true.

To~xtend this approach to get a 70 dB display, another
30 dB of amplifioation must be plaoed in the signal path
ahead of the lowest LM391'S. Extreme care is required as
the lowest LM3915 displays input signals down to 2 mVI
Several offset nulls may be required. High ourrents should
not share the same path as the low level signal. 'Also power
line wiring should be kept away from signal lines.

Multiple Drl~ers
Figure 12 shows how to obtain a oommon referenoe trim

TIPS Ot:! I:IEFERENCE VOLTAGE AND LED CURRENT
PROGRAMMING
'

and intensity control for two drivers. The two ICs may, be
connected in cascade or may be handling separate channels for stereo. This teohnique oan be extended for larger
numbers Of drivers by varying the values of R1, R2 and R3.
Beoause the LM391S has a greater ladder resistanoe, RS
was picked less than R7 in suoh a way as to provide,equal
reference load, currents. The ICs' internal referenoes track
within 100 mV so that worst oase error from chip to chip is
only 0.2 dB for VREF = SV.

Single Driver
The equations in Figure 10 illustrate how to choose resistor
values'to set referenoe voltage for the simple case where
no LED intenSity adjustment is required. A LED current of
10 mA to 20 mA generally produces adequate illumination.
Having 10V full-scale across the internal voltage divider
gives best accuracy by keeping signal level high relative to
the offset voltage of the internal oomparators. However, this

LM391.

LM3III
ALO IDIIlYP

RlO ,,,TYP RtU
r-~.,

"HI

r..JIIVY-..,

I

I

I

I

AI

Adjust R2 to vary VREF
PickRl

=

12,5V
ILED - VREF"kn

Pick R2

=

(VREF ~ 1.25V)
1.25V1Rl + 0.08 rnA

5 rnA ,;; ILED ,;; 28 rnA @ VREF

TL/H17971-17

= 5V

FIGURE 10. Design Equations for Fixed LEO Intensity ,
TUH17971-18

FIGURE 11. Varying LED IntenSity

ALO 10k TVP

RLO 22k TVP RHI

r..JIIVY-,

I

AHI

r~"I

I

I

05
Uk

5 rnA :,; ILED ,;; 28 rnA
@VREF = 5V

"::"
TUH/7971-19

FIGURE 12. Independent Adjustment of Reference Voltage and LED Intensity for Multiple Drivers

4-68

Application Hints (Continued)
The scheme in Figure 13 is useful when the reference and
LED intensity must be adjusted independently over a wide
range. The RHI voltage can be adjusted from 1.2V to 10V
with no effect on LED current. Since the internal divider here
does not load down the reference, minimum LED current is
much lower. At the minimum recommended reference load
of 80 p.A, LED current is about 0.8 mA. The resistor values
shown give a LED current range from 1.5 mA to 25 mA.

connecting the bottom end of the intensity control pot to a
negative supply overcomes this problem by allowing a larger
voltage drop across the (larger) current-sharing resistors.

Other Applications
For increased resolution, it's possible to obtain a display
with a smooth transition between LEDs. This is accomplished by superimposing an AC waveform on top of the
input level as·shown in Figure 14. The signal can be a triangle, sawtooth or sine wave from 60 Hz to 1 kHz. The display
can be run in either dot or bar mode.

At the low end of the intensity adjustment, the voltage drop
across the 510.0 current-sharing resistors is so small that
chip to chip variation in reference voltage may yield a visible
variation in LED intensity. The optional approach shown of

LM3916

r -;

,
,

L:;15:- - ,

I

~

,.

Uk

&.Ik

INTENS~~~

50k

,

,

LM3916

,II
,

510

,

510

-15V'

b... ___ .J
1.25V ,; VREF ,; IOV

'Optional circuit for improved intenSity
matching at low currentS. See text.

1.5 mA ,; ILED ,; 25 mA
TL/HI7971-20

FIGURE 13. Wide-Range Adjustment of Reference Voltage and LED Intensity for Multiple Drivers

LM3S18

INPUT

I.

(DV TO IDVI

2k

TL/H/7971-21

FIGURE 14. OV to 10V VU Meter with Smooth TransHlons

4-69

LM3916

;J

Extended Range VU Meter (Bar Mode)

~

lN4oo1

J€
lN4oo1

-411

-37

-34

-31

-28

-25

-22

-19

~'

»

~

"2-

n

Tl: 6.3 YAC CENTEIHAPPfO

...I!.

!.

0'
::J
o

~2.2
-1&

-13

-10

-7

-5

-3

-1

o

+1

+2

+3 dB

N~~~~~

LM3915

'~

YL:Jl

J"

y+

r~ r
RLO

SIG

LM391&
RNI

q

REF
OUT

REF
ADJ

8

R2
It

1

Y-

MODE

r

11

Ne

y+

~

RLO

SIG

-¥

RHI

REF
OUT

REF
ADJ

MODE

9

L!---r
SR,1
~lk

"
INPUT (7.IY FULL-IICALE)*

i
!

~18_ _~17~~~~~_ _~~~~_ _~

,

*-

a

Zk

I

....!~7

MODE

•

I

T

...

.....

.

REF .. REF
OUT AOJ
1

.:.L I •O I

,0;..
~

RHI

: ~ ~.

,

111,

I

SlG

y

"

' R7 thru Rls: IOk±10%

I

'01,02: lN914 or lN4149

I
I
I ______________
-BY:; -IBV
I
J

'Half-wave peak detector.
See Application Hints.

~

TL/H/7971-24

. Indicator and Alarm, Full-Scale Changes Display Fro," Dot to Bar

N
LEO
NO.1

N

N

N

N

N

N

N

N

N
LEO
NO.1

18

11

16

15

14

13

12

II

10

LM3IIIa

·ih~· input to the Dot-Bar swftch may
be taken from cathodes of other
LEOs. Display will change to ber as
• Soon as the LED so selected begins
to light.
'~Optional.

Shunts 100 p.A auxiliary
sink current away from LED # 1.
TL/H/7971-25

4-72

~
'a

~

:"2o·~

High Resolution VU Meter (Bar Mode)
~3

VU
,_~

'7LEDS

'_i'

-,.

-'3

• •

-'0

-I

-5

-6

-4

-3

~

-,

ovu

t~t~~ff*Nffft~ff
,.
,z
'6

17

'6

'5

"

'3

'1

+'
Ne

Ne

L'6

17

Ne

1,. 1,.

.i:'
+

+z

"

+3

N

+4

N

+5VU

N

N...1:.-

T'loF
"

n

"

"

LM38'6

..

14

I

~

* *

~

HI

33k

INPUT-

fDVU-11V..

Ii VU • 17.IIVI

~

~

(I)

I

II

~:

H3
Zk

(1ZVTO~ 4 •

3V~VLED~1V

• •

"#4

•

H'
13.2k
'li

HZ

3D.n
'li

-

HS
Uk

-=F
TUH/7971-26

'See Applicallon Hints fer optional peak er aver-

age de1ector.

~"'0562=
A' + A2
.

-5dB

er A' .. 0.788. A2

9~6£""

II

LM3916

~
'a

~
»
'a

High Resolution VU Meter (Dot Mode)
01
11114

-23VU

-10

~N~ ,N ~

~

-13

-8

N~ ~N

-I' ~11
..;

- 1.

~ ,N~ ~

- 15

11

~
~

I.R8"

y+.

N

14

-1

-2

/1./

~ ~.

13

~ t/l./~ ~
12

n.

OVU

/1./

11

~

....

-

,/1./

IC

IC

II.

10

111

- SIG -

RLD

3

* *
To

I,.

IC

h&

~

+2

..

~
.. ~.

, /1./
14

+3

N

~
~ ,N ~ ,N
f..

-

13

12

,.

+5 VI

+4

.- 11

N

It

LM391&

RHI

REF

..

ADJ

~l

5
·Rl
33.

REF
- OUT

o.

°

MODE

-

-

If

.

V11
IC

R3

...

2•
..........

*

I

V+
3

REF
OUT
1

*0 -- .R4
RLO

--S1G

5

RHI

[6

~

REF
ADJ

8

MODEl

Jc'

2.

R1

23.a

...

--10111'

1I+<2IV

HC

+1

-~.-

+

12V

'2.

.......

LM381.

.
V-

-3

-4

-8

02
11814

=R2
~ lO.n

IIPUTf
(UVU= IOV.
+5 VJI • 17.1aV)

._-

---

"OptiOnal

shunts 100 pA IIUXIliaiy sink current
away from LED # 1.

tSee Application Hints for optional peak or a_age detector.
R2
R1""+R2
'" 0.562 -

-5 dB

orRl ... 0.788oR2

~R&

:" 8.2•.

..~

TUHI7971-27

Io·
::I

(I

I

Typical Applications (Continued)
Displaying Additional Levels

Lal.

+

T

1...

'II'

11IVFULLSCA~V\ ~~-+--+...,..--4
HI
1.7111

R1
1.

1"

~ .. 0.794 = -2dB
A2

+

A3

A2

+

A3

+ A2 + A3" 0.562 =
or A2 = 0.259 • A3
and AI = 0.979' A3

AI

-5dB

TUH/7971-28

Operating with a High Voltage Supply (Dot Mode Only)
qy

1.

3.

1.

3.111

The LED currents are approximately 10 mA, and
LM3916 ouIputs operate In saturation for minimum dissipation.

liD

'This paint is partially regulated and decreases In
voltage with temparature. Vo!tsge requirements
of lhe LM3916 also decrease with temparetura.

TUH17971-29

4-75

~r-----------------------------------------------------------------------'

;

(II)

Typical Applications (Continued)

:!I

Low Current Bar MQde Display

+

~u
Supply current drain Is only 20 mA
with ten LEOs Uluminated @ 16 rnA.

TLlH/7971-30

Driving Liquid Crystal Display
LlGUID CRYSTAL BAR 8RAP11

1'1.11",
IIPUCES

MODE

DDT
lAB

TLlH17971-31

Bar Display with Alarm Flasher
VLED 5V

IH

~
LED

RI
Ii

'N'. 'N'. ~N~ ~N' 'N'. '111'.'N' 'N' 'iii' '111
~.

~'

~'

LED

NO.1

NO. 10

II

n

18

15

14

13

12

~
II

11

..-.
v+
~I

Full-scale causes the full bar display to
flash. If the junction of Rl and Cl Is connected to a different LED cathode, the di...
play will flash when thaI LED lights, and al
any higher input signal.

3

RLD

* *

SIG

Ii

:;;~
IIHI

•

REF OUT REF ADJ MODE

7

~

I

47.

1.2..

TL/HI7971-32

4·76

r-----------------------------------------------------------------------,~

...~==

Connection Diagram
Dual-In-Une Package

U

1
LEDND.l -

~

CD

LED NO.2

2

v--

~ LED NO.3

y+2

~ LED NO.4

DIVIDER 4
(LOWENDi5
SIGNAL INPUT -

~LEDND.5

DIVIDER &
(HIGHENDi -

~ LEDNO.1

REFERENCE OUTPUT

.2.

~ LED NO.8

REFERENCE ADJUST

..!

.,!!. LED NO.9

MODE SELECT -

14

~ LEDNO.&

t!! LED NO. 10

9

TL/H/7971-33

Top View
Order Number LM39l6N
See NS Package Number N18A

Definition of Terms
Absolute Accuracy: The difference between the observed
threshold voltage and the ideal threshold voltage for each
comparator. Specified and tested with 10V across the internal voltage divider so that resistor ratio matching error predominates over comparator offset voltage.
Adjust Pin Current: Current flowing out of the reference
amplifier pin when the reference amplifier is in the linear
region.
Comparator Gain: The ratio of the change in output current
(ILEO) to the change in input voltage (VIN) required to produce it for a comparator in the linear region.

change in forward current, this is equivalent to changing the
voltage at the LED anodes by the same amount.
Une Regulation: The average change in reference output
voltage (VREF) over the specified range of supply voltage
(V+).

Load Regulation: The change in reference output voltage
over the specified range of load current (IL(REF)'
Offset Voltage: The differential input voltage which must
be applied to each comparator to bias the output in the
linear region. Most significant error when the voltage across
the internal voltage divider is small. Specified and tested
with pin 6 voltage (VRHI) equal to pin 4 voltage (VRLO).
Relative Accuracy: The difference between any two adjacent threshold points. Specified and tested with 10V across
the internal voltage divider so that resistor ratio matching
error predominates over comparator offset voltage.

Dropout Voltage: The voltage measurad at the current
source outputs required to make the output current fall by
10%.
Input Bias Current: Current flowing out of the signal input
when the input buffer is in the linear region.
LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLEO) as
measured at the current source outputs. As the forward voltage of an LED does not change significantly with a small

4-77

~

,--------------------------------------------------------------------------------,

!
d Nat ion a I
~, P

S em i con due tor,

~

;7;

::IE
::IE

MM5450/MM5451 LED Display Drivers
General Description

Features

The MM5450 and MM5451 are monolithic MOS integrated
circuits utilizing N-channel metal-gate low threshold, "nhancement mode, and ion-implanted depletion mode devices. They are available in 4O-pin molded or cavity dual-in-line
packages. The MM5450/MM5451 is designed to dnve"common anode-separate cathode LED displays. A single pin
controls the LED display brightness by setting a reference
current through a variable resistor connected to Voo.

•
•
•
•
•
•
•
•

Continuous brightness control
Serial data input
No load signal required
Enable (on MM5450)
Wide power supply operation
TTL compatibility .'
34 or 35 outputs, 15 rnA sink capability
Alphanumeric capability
• (JJA DIP
Board = 49"C/W
Socket = 54°C/W

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Relay driver
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts

Block Diagram
voo
BRIGHTNESS
CONTROL

OUTPUT 34

. QUTPUTI

r-....---::-=:-:--...
24

IB

DATA ENAllE _54&0)

OUTPUT3S _&4&1) ~---"""'I~.,

SE:~~~ ~---~H
CLOCK ~---~.......

>----.. . .
TLlF/6136-1

FIGURE 1

4-78

Absolute Maximum Ratings
+

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin

Power Dissipation at
25"C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount

+ 12V
+ 85°C
65°C to + 1500C
+ 1500e

·Molded DIP Package board mount, BJA = 4g'C/W,
Derate 20.4 mWI'C above 25"C.
··Molded DIP Package, socket mount, 9JA = 54°C/W,
Derate 18.5 mWI'C above 25°e.

VSS - 0.3Vto VSS

Operating Temperature

- 25°C to

Storagd Temperature

-

Junction Temperature
Lead Temperature (Soldering, 10 sec.)

3000e

Electrical Characteristics T A within operating range, VDD =
Parameter

Conditions

4.75Vto 11.0V, VSS = OVunless otherwise specified

Typ

Min

Power Supply

Max

4.75

Power Supply Current

Excluding Output Loads

Input Voltages
Logical "0" Level (VtJ
Logical "1" Level (VH)

± 10 p.A Input Bias
4.75V,;; Vee';; 5.25V
Vee> 5.25V

-0.3
2.2
Vee - 2V

Brightness Input (Note 2)

0

Output Sink Current
Segment OFF
Segment ON

Brightness Input Voltage (Pin 19)

VOUT = 3.0V
VOUT = IV (Note 3)
Brightness Input = 0 p.A
Brightness Input = 100,.A
Brightness Input = 750 ,.A

0
2.0
15

Input Current 750 p.A

3.0

2.7

Units

11

V

7

rnA

0.8
Vee
Vee
0.75

V
V
V
rnA

10

p.A

10
4
25

mA
mA

p.A

4.3

V

±20

%

500
950
950

kHz
ns
ns

300
300

ns
ns

Output Matching (Note 1)
Clock Input
Frequency, fc
High Time, th
Low Time, ~

2.5W·
2.3W··

(Notes 5 and 6)

Data Input
Set-Up Time, los
Hold Time, teH

Data Enable Input
ns
Sat-Up Time, toES
100
Nots 1: Output matching is calculated as Iha percent variation (IMAX + IMINl/2.
Note 2: With a fixed resistor on the brightness Input pin, some variation in brightness will occur from one device to another. Maximum brightness input current can
be 2 mA as long as Note 3 and lunction temperature equation are compiled with.
Note 3: See Figures 5, 6, and 7 lor Recommended Operating Conditions and limits. Absolute maximum lor each output should bs IImitsd to 40 mAo
Note 4: The VOUT voltage should bs regulated by the user. See Figures 6 and 7 for allowable VOUT va lOUT operation.
Note 5: AC input waveform specification for tesl purpose: ... :s: 20 ns, It :s: 20 ns, I = 500 kHz, 50% ±10% duty cycle.
Note 6: Clock input rise and fall times must nOt exceed 300 ns.

Connection Diagrams
Dual-In-Llne Package
OUTPUT BIT

n-7

:::~:~:~

OUTPUT.TI44
aUDUTIIT'3";
OUTPUT liT 12-f
OUTPUT lIT 11-;'
OUTPUT lIT I'-=:
OUTPUT Irr I.,g.

"'*
OU1'PUTIIT1~
OUTPUT lIT I

Dual-In-Llne Package

-:!- OYTPUT liT "
~OUTPUT.T"
..g. OUTPUT lIT ZI

v.. -;.

VII~

.......

OUTPUTIIT'~
OUTPUT'IT&~
OUTPUTIIT4~
OUTPUT'1T3~
aU"UT.1T2~
DUTPUTIJT1~

OUTPUT liT
OUTPUT liT 13''';
OUlPUT lIT 12

-f

OUTPUTltTll~
OUTPUT'ITII~

OUTPUT IITIIi

~OUTPUTIJT2I
~OU"UTIlTn
~ OUTPUT IIT21
~ OUTPUT IInl
~OUTPUT'IT.
~OUTl'UT'113'
~OUTl'UT'IT32'
~ OUTPUT lIT D
~OU"UTBITM

OUTPUT liT I";;
OUTPUT liT l..g
OUTPUTIIT1";;

OUTPUT lIT 2.
; . OUTPUT IIT:n

~OUTPUT'IT22

_,

OU"UTIITI~
OUTPUTIIT&~

~:::::~:

~ OUTPUT liT 17

~ OUTPUT lIT 2.
~ OUTPUT liT 2.
~OU"UTIIT.

~OUT'UTIITM

OUTPUTIIT2..g

'..:!:

f::::·

T-

IT3I

~CLOCICI"

Voo"::

~CLOCKI"

~OUTPUTIJT24

~OUT1'UT'I132
~OU"UTIIT13

OU"UTIIT3~

OUTPUT lIT
IRIONTNESS CO_TaOL

.g.. OUTPUT IIT23

.g.. OUTPUT liT 31

OUTPUT liT 4 ~

-ll-mnmtr
-r.- DATA II

BRIGHTllEII CONTROL-;
VOO"':

~DUTpuT.lTla

..g.

:~=::~~:~
'4~

~OU1JlUT'ITZ1
~OU"UT8ITIZ
~aUTPUTIITU
~OUTPUTIITZ4

*"

.;. OUTfUT liT ,.

OUTPUT lIT " -;-

Tl/F/6136-3

TLlF/6136-2

Top View

Top View

FIGURE2b
FIGURE2a
Order Number MM5450N, MM5451N, MM5450V or MM5451V
See NS Package Number N40A or V44A
4-79

....

..,.

10
10

::E
::E
.....

Connection Diagrams (Continued)
Plastic Chip carrier'

!
I

;:!: ~ :!! ~
t:

CD

10

Ii Ii

:!!

t:

~

iii

t: t: t:

CD

CD

CD

CD

..

::I

Ii Ii

§ ~ § I,.~~ §~ ~ ~ §
!;; S S !;; S

!; !;; !;;

OUTPUT BIT 13

7

OUTPUT BIT 23

OUTPUT BIT 12

8

OUTPUT BIT 24

OUTPUT BIT 11

9

OUTPUT BIT 25

OUTPUT BIT 10

10

OUTPUT BIT 26

OUTPUT BIT 9

11

OUTPUT BIT 27

Nle,

Nle

I1I1545OV '

12

OUTPUT BIT 8

13

OUTPUT BIT 7

14

OUTPUT BIT 28
OUTPUT BIT 29

OUTPUT BIT 6

15

OUTPUT BIT 30

OUTPUT BIT 5

16

OUTPUT BIT 4

17

OUTPUT BIT 31
29

..,

N

- ...

iii

iii

U

Ii~ >~~
d
i:e: 8

t: t:

CD

CD

!;; ... S z

iii
;:!

Ii

OUTPUT BIT 32

~ Ii~
Ii

;!! 15 ...

~~i

§ 66~

..
~

CD

Tl/F/6136-13

Top View

Plastic Chip carrier

..
s s
§~06J1~~~ 50 i 50
;:!: ~

:e

~

~

~

t: t: t:

CD

Ii Ii

S ... ~ ~

... !;;

Ii

CD

CD

0

::I

N

t:

CD

Ii Ii

OUTPUT BIT 13

7
8

39
,38
37

OUTPUT BIT 23

OUTPUT BIT 12
OUTPUT BIT 10

10

36

OUTPUT BIT 26

OUTPUT BIT 9

11

35

OUTPUT BIT 27

Nle

12

34

Nle

OUTPUT BIT 8

13

33

OUTPUT BIT 28

OUTPUT BIT 7

14

32

OUTPUT BIT 29

OUTPUT BIT 6

15

31

OUTPUT BIT 30

OUTPUT BIT 5

16

30

OUTPUT BIT 31

OUTPUT BIT 4 , 17

29

OUTPUT BIT 32

OUTPUT BIT 11

11115451V

..,

N

t: t:

- ...

Ii~

CD

CD

~

i ~~

0

!;;

8

iii
>

U

iii iii

~ ~
d

~

.....,

OUTPUT BIT 24
OUTPUT BIT 25

~ ~

Ii Iii Iii
... !;; ~

~ 5

000

~

CD

TLlF/6136-14

Top View

4-80

Functional Description
Both the MM5450 and the MM5451 are specifically designed to operate 4- or 5-digit alphanumeric displays with
minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is
accomplished with 2 Signals, serial data and clock. Using a
format of a leading "I" followed by the 35 data bits allows
data transfer without an additional load signal. The 35 data
bits are latched after the 36th bit is complete, thus providing
non-multiplexed, direct drive to the display. Outputs change
only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 0.001 capacitor should be connected to brightness control, pin 19, to prevent possible oscillations.

There must be a complete set of 36 clocks or the shift regiSters will not clear.

A block diagram is shown in Figure 1. For the MM5450 a
DATA ENABLE is used instead of the 35th output. The
DATA ENABLE input is a metal option for the MM5450. The
output current is typically 20 times greater than the current
into pin 19, which is set by an external variable resistor.
There is an internal limiting resistor of 4000 nominal value.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.

When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its normal operation.
F/{/1Jf6 2 shows the pin-out of the MM5450 and MM5451. Bit

1 is the first bit following the start bit and it will appear on pin
18. A logical "I" at the input will tum on the appropriate
LED.

F1f}ure 3 shows the timing relationships between data, clock
and DATA ENABLE. A max clock frequency of 0.5 MHz is
assumed.

Tj = (VOUT) (lLEO) (No. of segments)(BJA>

+ TA

where:

Figure 4 shows the input data format. A start bit of logical
"I" precedes the 35 bits of data. At the 36th clock a LOAD

Tj = junction temperature, 150"C max

VOUT = the voltage at the LED driver outputs

signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

ILEO = the LED current
BJA = thermal coefficient of the package
T A = ambient temperature
BJA (Socket Mount) = 54°C/W

BJA (Board Mount) = 4goC/W
The above equation was used to plot Figure 5, Figure 6 and

Figure 7.

11"'="""-10%
--~1=10%

DATA ENABlE---(MM5450)
TUF/8136-4

FIGURE 3

4-81

Functional Description (Continued)
,,1

'

311

~..n..ruuu-u~
" ,

arMY

lIT 34

lIlT 31

r-"'\··"\r-\."~"'\r~
_ - - - ' ,,~~~J'--'~~J
~~J

{INTERN~"""""'---------~--'~
'r-I

, RESET'
(1IIlDItAL)

--------------,~ ~

TL/F/6136-5

,FIGURE 4. Input Data Format

Typical Performance Characteristics
,
.'
"

110

1.1
'(

....

~ 2.0 I----h~~

~ 1.51---f.,~~~~od---1

~

~

~'

1.0

2.1

TA"WC
Tj 0 1WClMAXi

r\ ~ ~.!
+~§~.,. ~"+

1.&

,1.01

••8.

"

60

80"

100

VOUT'2V

" "" ..... r--...

I\Jo(

o
o

&

ILED ImAi

TElll'ElIATURE (OC)

1 1

1\

28
10
1411218281421

«l

1

40
30

o
lD

VOUT-,IVHTAOI&OC

VOUT=I.&~_

&0

I ~r-~~~~~~
00

H

70
80

~

1.0

-

10

1&

20

FIGURE 7

Typical Applications
_DC
>IV

1k

2400
AV

11S=

!R
Ik

1
TL/F/6136-S

FIGURE 8. Typical Application of Constant Current Brlghtne.. Control

TLlF/6136-10

FIGURE 9. Brlghtne.. Control Varying the Duty Cycle

4-82

30

34

TLlF/6136-8

FIGURE 6

FIGURE 5

25

NUMBER,OP SEGMENTS

TLlF/6136-7

TL/F/6136-6

-

r-- -

Typical Applications

(Continued)

Basic Electronically Tuned Radio System
LED DISPLAY

AM
FM

IE :::J~O

I

~

--;--MM&4&D
DISPLAY
DRIVER

COPS
ELECTRONIC
TUNING
CONTROLLER

KEYBOARD

PLL
SYNTHESIZER

111

STATION
DETECT. ETC.
TL/F/6136-11

Duplexlng 8 Digits with One MM5450

CLOCK IN _ - - -...
DATA IN

_----..1

L..JV\f!r-+- VOD

BRIOHTNESS
CONTROL
'111>
TV.
TLlF/6136-12

4-83

iI

f}1National Semiconductor

~.

MM5452/MM5453 Liquid Crystal Display Drivers

:&
:&

• DATA ENABLE (MM5452)

General Description
The MM5452 is a monolithic integrated circuit utilizing
CMOS metal gate, low threshold enhancement mode devices. It is available in a 40-pin molded package. The chip can
drive up to 32 segments of LCD and can be paralleled to
increase this number. The chip is capable of driving a 4 '/2digit 7-segment display with minimal interface between the
display and the data source.
The MM5452 stores display data in latches after it is
clocked in, and holds the data until new display data is received.

Features
• Serial data input
• No load signal required

•
•
•
•
•

Wide power supply operation
nL compatibility
32 or 33 outputs
Alphanumeric and bar graph capability
Cascaded operation capability

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts
Remote displays

Block Diagram

DATA ENABLE -14521 _ _ _ _ _ _~I_-----....,
OUTPUT 33 (MMI4&l'"

s~~~~.------~~-----~S~------~~~~!!~~!J
CLOCK.------~I_----......i

~---------.....

TUF/6137-1

FIGURE 1

4-84

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OffIce/DIstributors for availability and speclflcatlons.

Storage Temperature

-65°C to + 150"C

Power Dissipation

300 mW at + 70"C
350 mW at + 25"C

Voltage at Any Pin
Operating Temperature

Junction Temperature
Lead Temperature (Soldering, 10 sec.)

Vss to Vss + 10V
O"Cto +70"C

+ 150"C
300"C

Electrical Characteristics
TA within operating range, Voo

=

3.0V to 10V, Vss

=

OV, unless otherwise specified

CondlHons

Parameter

Min

Power Supply
Power Supply Current

Max

Units

10

V

40
10

p.A
p.A

500

kHz

-0.3
-0.3

0.1 Voo
0.8

0.8Voo
2.0

Voo
Voo

V
V
V
V

-20

/loA

3
Excluding Outputs
OSC = Vss, BP IN @ 32 Hz
Voo = 5V, Open Outputs, No Clock

Clock Frequency
Input Voltages
Logical '0' Level
Logical '1' Level
Output Current Levels
Segments
Sink
Source
Backplane
Sink
Source

Voo < 4.75
Voo ~ 4.75
Voo> 5.25
Voo"; 5.25

Voo
Voo

=
=

3V, VOUT
3V, VOUT

=
=

0.3V
Voo - 0.3V

20

Voo
Voo

=
=

3V, VOUT
3V, VOUT

=
=

0.3V
Voo - 0.3V

320

Typ

p.A
-320

p.A
p.A

Output Offset Voltage

Segment Load 250 pF
Backplane Load 8750 pF (Note 1)

±50

mV

Clock Input Frequency, fc

(Notes 2 and 3)

500

kHz

High Time, th

950

ns

LowTime,lt

950

ns

Data Input
Set-Up TIme, tos
Hold Time, toH

300
300

ns
ns

Data Enable Input
100
ns
Set-Up Time, toes
Note 1: This parameter is guaranteed (not 100% production tested) over operating temperatura and supply voltage ranges. Not to be used In Q.A. lesting.
Note 2: AC input waveform 'or lest purpose:

Ir ,;

20 ns, I, ,; 20 ns, , = 500 kHz, 50%

± 10% duty cycle.

Note 3: Clock input rise and fall times must not exceed 300 ns.

•
4-85

~

!::::E

r-----------------------------------------------------------------------------,
Connection Diagrams

....

'~

::::E
::::E

Dual-In-Une package

Dual·ln·Une Package,

::::E

'"

Va
OUTPUT lIT 1J
OUTPUT liT 1.
OUTPUT liT 11
OUTPUT lIT 14
oUTPUTIIT 13
OUTPUT 81T lZ

4.

OUTPUT liT l'

:

..OUTPUlIIT 1.
OUTPUT lIT H

liT 11
OUTPUlIITl1
OUTPUT Bill' 1.

MMI4&2

OUTPUT 81T, 11

OUTPUT liT l'

OUTPUT 81T 2'

OUTPUT liT 1&

OUTPUT 81T 12

OUTPUT liT 14
oUl'UTBIT 13
OUTPUT liT 12

OUTPUT BIT Z3
OUTPUT liT Z4
OUTPUTllTZ&
OUTPUTBIT za
OUTPUT liT ZT

oUTP~T

OUTPUT liT I
oUTPUTllT1
15
oUTPUTlIT4
I'
OUTPUT lIT 3
11
oUTPUTBITZ
11
OUTPUT 81T 1

MIIIIW

11

IACKPLANE IN
BACKPLANE OUT

OUTPUT lIT 1

mnaarr
OATAIN
CLOCK I.

Voo

OUTPUT IITZ4

oUTPUTlITI
12
OUTPUT BI''I
'13
OUTPU! IITI
I'
oUTPUTIITs
15
oUTPUT'IIT4
1.
oUTPUTIIT3
oUTPUTlITZ

OUTPUT liT IZ

OSCIR :

oUTPUTBIT 12
OUTPUT BIT,n'

OUTPUT liT 11
,OUTPUT liT 10
oUTPUTBITI 10

OUTPUT BIT Z'
OUTPUT 'IT ZI
OUTPUT 11TH
OUTPUT liT 31 '

OUTPUT BITT

.j

Vss
'ollTPllT liT IT

OU,TPUT II,T ZS
OUTPUT liT za
31
OUTPUT IITZT
3D
OUTPUT liT za
21
oUTPUTBITZI
ZI
OUTPUT liT 3D
27
oUTPUTlIUl
26
OUTPUT liT IZ
Z5
oUTPUTBIT 33
BACKPLANE I.
8ACKPLAIIE OUT
DATA IN
CLOCK IN

oSCIN
VOO

TLlF/6137-2

Tl/F/6137-3

TopYlew
FIGURE2a

TopYlew
FIGURE2b

Plaatlc Chip carrier

Plastic Chip Carrier

O\IIPUTIII13

OUTPUT 811 23

0IITPUT,811 13

7

38

OUTPUT 811 23

OIITPUT III 12

OUTPUT 811 24

OUTPUT 81112

8

38

OUTPUT 811 24

OIITPUT III 11

oulPin' 811 25

OUTPUT 811 11

37

OUTPUT III 25
OUTPUT 811 26

I

OUTPUT Billa

OUTPUT BII za

OUTPUT 81110

1Ii

38

OUTPUT 8119

OUTPUT 811 27

OUTPUT 8119

11

35

OIITPUT 811 27

OUTPUT 811 za

OIITPUT 811 8

12

34

OUTPUT 811 28
O\IIPUT 811 29

OUTPUT 8118

11113452V

MM5453V

OIITPUT 811 ~
OUTPUT 8116

OUTPUT 811 29

OUTPUT 8117

13

33

14

OUTPUT 811 30

O\IIPUT 811 6

14

32

OUTPUT 811 30

OUTPUT BII 5

15

OUTPUT 811 31

OIITPUT 8115

15

31

OUTPUT 811 31

OUTPUT 8114

16

OUTPUT 811 32

OUTPUT 8114

16

30

OIITPUT 811 32

OUTPUT 811 3

17

Nle

OIITPUT 811 3

29

OIITPUT 811 33

i

I

UN-iS 8UiSlE~lEl

UN-iii

~ 'i'~ > '~~ ~ 'i~

8 u z iSiiS U

~1i,1i~>~~ ~
! II! ~~

i i , 1t

TLlF/6137-11

TopYlew

TLlF/613'7~12

TopYlew
Order Number MM5452N, MM5453N,
MM5452Y or MM5453Y
See NS Package Number N40A or Y44A

Functional Description
The MM5452 is specifically designed to operate 4 %-digit 7·
segment displays with minimal interface with the display and
the data source. Serial data transfer from the data source to
the display driver is accomplished with 2 signals, serial data
and clock. Since the MM5452 does not contain a character
generator, the formatting of the segment information must
be done prior to inputting the data to the MM5452. Using a
format of a leading "1" followed by the 32 data bits allows
data transfer without an additional load Signal. The 32 data

bits are latched after the 36th clock is complete, thus pro·
viding non-multiplexed, direct drive to the display. Outputs
change only H the serial data bits differ from the previous
time.
A block diagram is shown in F/{/ure 1. For the MM5452 a
DATA ENABLE is used instead of the 33rd output. If the
DATA ENABLE signal is not required, the 33rd output can
be brought out. This is the MM5453 device.

4·86

Functional Description (Continued)
F/flure 4 shows the input dats format. A stsrt bit of logical
"1" precedes the 32 bits of dats. At the 36th clock a LOAD

If the clock is not continuous, there must be a complete set
of 36 clocks otherwise the shift registers will not clear.

signal is generated synchronously with the high stste of the
clock, which loads the 32 bits of the shift registers into the
latches. At the low stste of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are ststic master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

Figure 28 shows the pin.:out of the MM5452. Bit 1 is the first
bit following the stsrt bit and it will appear on pin 18.
F1flUre 3 shows the timing relationships between dats, clock
and DATA ENABLE.
.

CLOCK

DATA

DATA ENABLE
(MM54521
TUF/6137-4

FIGURE 3
36
CLOCK
START BIT 1

DATA

BIT 3S

BIT 36

r----..
raare_~I!~$M

n._______

(INTER= _ _ _ _ _ _ _ _ _ _ _ _ _ _~r .,_ _ _ _ _ _ _ _ _ _.......

RESET _ _ _ _ _ _ _ _ _ _ _ _ _ _
(INTERNALI

~I

n

.,_ _ _ _ _ _ _ _ _ _ _ _.... '

• _ _ _ __

TUF/6137-5

FIGURE 4. Input Oats Format

II
4-67

Functional Description (Continued)

;;...

Figure 5. shows a typical application. Note, how the Input
data maps to the output pins and the display. The MM5452
and MM5453 do 1)Ot- have format restrictiol1ll. as all outputs

are controllable. This application assumes a specific display
pinout. Different display/driver connectionpattems will, of
course, yield a different input data format.

nt Identification

I

E/b
'1-

•

,

I

"

I
IP

01 Fl AI Bl 82 n

'r-

A2 B2 83 F3 A3 83 G4 F4 A4

.I,CI CII=II=I
1./_1.1_1. IJ. 1_1

1~~~~~HU~~"OO~~U""M

~

L

-

-

-

---

'--

--.,.-

---

L....-

"

":"

Vss

II
11

17

II

20
21

~

---.;

~r~
24

13
12
11
10

25
21

9

•
1

•

5
4

3
2
1
OeclN

Tl.Ol,.,T~

...6453

21
21
2.
31
31

32
IACKPLANE OUT
BACKPLANE IN
33.
DATA IN

I

~OCKIN

."-1-,

v+
DATA FORMAT
TIME-LEFT END
DECIIIAL
POINT

3RD
DECIMAL
POINT

2ND
DECIMAL
POINT

4TH
DECIMAL
POINT

NULLS

I

I

TlfF,f6137-6

Consult LCD manufacture,·. data sheet for specmc pinouts.
FIGURE 5" Typlcal4YrDlgit Display Application

4-88

~------------------------------------------------------~~

~

Functional Description (Continued)

G
.....

DISPLAY

~
~

~

w
y+

BACKPLANE

TUF/6137-7

'The minimum recommended value lor R for the oscillator input is 9 kn. An RC Ume oonstant of approximately
4.91 X 10-4 should produoe a backplane frequency between 30 Hz and 150 Hz.

FIGURE 6. Parallel Backplane Outputs

DISPLAY

BACKPLAN~

2 X BACKPLANE
DRIVE FREOUENCY

TUF/6137-B

FIGURE 7. External Backplane Clock

Figure 8 shows a four wire remote display that takes advantage of the device's serial Input to move many bits of display
information on a few wires.

Figure 9 is a general block diagram that shows how the
device's serial input can be used to advantage in an analog
display. The analog voltage input is compared with a staircase voltage generated by a counter and a digital-to-anaJog
converter or resistor array. The result of this comparison is
clocked into the MM5452, MM5453. The next clock pulse
increments the staircase and clocks the new data in.

USING AN EXTERNAL CLOCK
The MM5452/MM5453 LCD Drivers can be used with an
externally supplied clock, provided it has a duty cycle of
50%. Deviations from a 50% duty cycle result in an offset
voltage on the LCD. In Fl{lure 7, a flip·flop is used to assure
a 50% duty cycle. The oscillator input is grounded to prevent oscillation and reduce current consumptions in the
chips. The oscillator is not used.

With a buffer amplifier, the same staircase waveform can be
used for many displays. The digital-to·analog converter
need not be linear; logarithmic or other non-linear functions
can be displayed by using weighted resistors or special
DACs. This system can be used for status indicators, spec·
trum analyzers, audio level and power meters, tuniflg indicators, and other applications.

Using an external clock allows synchronizing the display
drive with AC power, internal clocks, or DVM integration
time to reduce interference from the display.

4-89

•

.. ~,

Functional Description (Continued)

'

DIIPlAY .

~-----1~---------'
DATA

----+-+.....

CLDC.

--....;.+-+.,...
-+_____...

. v- ____....

TlIF/6137-9

FIGURE 8. Four Wire Remote Display
LCD BAR IiRAPH DISPLAY

11111000000
COUNT
CLOCK

DATA IN

I'
"'START
liT

TL/F/6137-10

Dala is high umll stalrcase > Input·

FIGURE 9. Analog I;)laplay

4-90

tflNational Semiconductor'

MM5480 LED Display Driver
General Description
The MM5480 is a monolithic MOS integrated circuit utilizing
N-channel metal gate low threshold. enhancement mode
and ion-implanted depletion mode devices. It utilizes the
MM5451 die packaged in a 28-pin package making it ideal
for a 3% digit display. The MM5480 is designed to drive
common anode-separate cathode LED displays. A Single
pin controls the LED display brightness by setting a referenCe current through a variable resistor connected either to
Voo or to a separate supply of 11V maximum.

Features
• Continuous brightness control
• Serial data input

•
•
•
•

•

No load signal required
Wide power supply operation
TIL compatibility
Alphanumeric capability
3% digit displays

Applications
•
•
•
•
•

COPSTM microcontrollers or microprQcessor displays
Industrial control indicator
Relay driver
Digital clock, thermometer. CQunter. vl)ltmeter
Instrumentation readouts

Block Diagram
BRIGHTNESS

CONTROL

TL/F/6138-1

FIGURE 1

Connection Diagram
Dual-In-Llne Package

Vss

28

OUTPUT BIT 12

OUTPUT BIT 11

OUTPUT BIT 13

OUTPUT BIT 10

OUTPUT BIT I.

OUTPUT BIT

OIl1PUT BIT 16

OUTPUT BIT

OUTPUT BIT 17

OUTPUT BIT 15

OUTPUT BIT

MM5480

OUTPUT BIT 18

Order Number MM5480N

OUTPUT BIT 19

See NS Package Number N28B

OUTPUT BIT 20
OUTPUT BIT 3

10

OUTPUT BIT 21

OIl1PUT BIT 2

11

OUTPUT BIT 22

OUTPUT BIT 1

12

OUTPUT BIT 23

BRIGHT. CONT.

13

DATA IN

Voo

I.

15

CLOCK
TL/F/6138-2

Top View

FIGURE 2
4-91

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Vss - 0.3Vto Vss + 12V
Storage Temperature
-65"Cto + 150"C

.>!"'
Power Dissipation at 25"C
Molded DIP Package, Board Mount
2.4W·
2.1W··
Molded DIP Package, Socket Mount
150"C
Juncti9n Temperature ,
,
,
."
:'"
Lead Temperature (Soldering, 10 sec.) ,
300"C
'Molded DIP Package, Board Mount, 8JA = 5~C/W, Derate 19.2 mWrc
above 25"C.
"Molded DIP Package, Socket Mount, 9JA = '5I1'C/W, Derate 17.2 mW/'C
above 25"C.

Electrical Characteristics
TA = -25"C to
Symbol

+ 85"C, Voo

= 4.75V to 11.0V, Vss ='

Parameter

ov unless otherwise specified
Conditions

Voo

Power Supply

100

Power Supply Current

Excluding Output Loads

VIL

Input Voltage
Logical "0" Level

± 10 /LA Input Bias

VIH

Input Voltage
Logical "1" Level

4.75V

ISR

Brightness Input Current
(Note 2)

IOH

Output Sink Current (Note 3)
Segment OFF

IOL

Output Sink Current (Note 3)
Segment ON

VISR

Brightness Input V~ltage '
(Pin 13)

OM

Output Matching (Note 1)

Typ

Min

Max

4.75

s: VOO s: 5.25V

Voo> 5.25V

11

V

7

rnA

-0.3

0.8

V

2.2

VDO

V

Voo-2

Voo

V

0

0.75

rnA

10.0

!LA

10.0
4.0
25.0

/LA
rnA
rnA

4.3

V

±20

%

VOUT = 3.0V
, VOOT = 1V
Brightness Input = 0 /LA
Brightness Input = 100 p.A
Brightness Input = 750 !LA

0
2.0
15.0

Input Current = 750 !LA

AC Electrical Characteristics TA =

-25"Cto

2.7

3.0

+ 85"C, Voo =

Units

5V ±0.5V

Typ

Parameter

Conditions

Min

fc

Clock Input Frequency

(Notes 5 and 6)

DC

th

High Time

950

ns

tl

Low Time

950

ns

tos

Data Input Set-Up Time

300

ns

SymbOl

Max

Units

,,'

500

kHz

Data Input Hold Time
ns
tOH
309
Note 1: Output matching Is calculated as the percent vari,atiOl1 lrom (IMAX + IMIN)/2.
Note 2: WIth a fixed resistor on the brightness Input pin some variation In brightness will occur trorn,9ne device to another. Maximum brighlnees input current can
be 2 mA as long as Nole 3 and JUnctiOl1 temperature equation ara complied with.
Note,a; Absolute maximum for each output should be limited t040'mA
Note '" The VOUT'voI. should be regulated by the user.' ,
Nole 5: AC Input waveform specificatiOl1 for test purpoee: t, ,; 20 ns, It ,; 20 no. I = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock input rise and fall times must not exC8l!d 300 ns.

4-92

Functional Description
The MM5480 is specifically designed to operate 31ft-digit
alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data
source to the display driver is accomplished with 2 signals,
serial data and clock. Using a format of a leading "I" followed by the 35 data bits allows data transfer without an
additional load signal. The 35 data bits are latched after the
36th bit is complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the serial data
bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A
0.001 JIoF ceramic or mica disc capaCitor should be connected to brightness control, pin 13, to prevent possible oscillations.

There must be a complete set of 36 clOCks or the shift registers will not clear.
When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its normal operation.

Ftgure 5 shows the Output Data Format for the 5480. Because it uses only 23 of the possible 35 outputs, 12 of the
bits are 'Don't Cares'.
Figure 3 shows the timing relationships between data and
clock. A maximum clock frequency of 0.5 MHz is assumed.
For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.

A block diagram is shown in Ftgure 1. The output current is
typically 20 times greater than the current into pin 13, which
is set by an external variable resistor. There is an internal
limiting resistor of 4000 nominal value.

Tj = (VOUT) {I LED) (No. of segments) {8JN
where:

+ TA

Tj = junction temperature, 150"C max.
VOUT = the voltage at the LED driver outputs
ILED = the LED current
8JA = thermal coefficient of the package
T A = ambient temperature
8JA (Socket Mount) = 58°C/W
8JA (Board Mount) = 52"C/W

Figure 4 shows the input data format. A start bit of logical
"I" precedes the 35 bits of data. At the 36th clOCk a LOAD
signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

~~1---90%

---...l''c;;;;;;;..--10%

TUF16138-3

FIGURE 3

CLOCK

DATA

.----

---~.. .____ .
=

'-...

~r;._~~_.

n

LOAD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....§SSli-_ _ _--'
(INTERNAL)

L._ _ __

RESET
(lNTERNAL)
_______________

n

.....§S~

L-.
TUF16138-4

FIGURE 4. Input Data Format

FIGURE 5. Output Data Format

4-93

Functional Description (Continued)
7V

RAW DC
>9V

lll317

-"'""'1-1----....-----..

1-....

240A

119 _ fN

1k

FIGURE 6. Typical Application of Constant Current Brightness C~)ntrol

.
TL/F/6138-5

..TLI~/6138-6

FIGURE 7. Brightness Control Varying the Duty Cyel,

,, 123

Safe Operating Area
2.5

Basic 3YrDlgit Interface

....;-N;;;rn:;"""".,

.-----,~___r-

g2.0
~

~

1.5

!a

1.0

~

i ~r-~~~~~~

23

1

o~-~~~~~~~~

o

20

40

60

80

11115480

100

DISPLAY
DRIVER

TEIIPERATURE (OC)
TL/F/6138-7

11

a.OCK

DATA
TL/F/6138-B

4-94

f}1National Semiconductor

MM5481 LED Display Driver
General Description
The 5481 is a monolithic MaS integrated circuit utilizing Nchannel metal gate low threshold, enhancement mode and
ion-implanted depletion mode devices. It utilizes the
MM5450 die packaged in a 20-pin package making it ideal
for a 2 digit display. The MM5481 is designed to drive common anode-separate cathode LED displays. A singie pin
controls the LED display brightness by setting a reference
current through a variable resistor connected either to Voo
or to a separate supply of 11 V maximum.

Features
• Continuous brightness control
• Serial data input

•
•
•
•
•
•

No load signal required
Data enable
Wide power supply operation
TTL compatibility
Alphanumeric capability
2 digit LED driver

Applications
• cops or microprocessor displays
• Industrial control indicator
• Relay driver
• Instrumentation readouts

Block and Connection Diagrams
OUTPUT 14

OUTPUT 1

BRIGHTNESS
CONTROL

.:::t

0.001 p.F

DATA ENABLE _ _.:..:'3:...,_...
SERIAL DATA _ _..:.1~21--I
CLOCK _ _...lI~II--I " ) _ - - - -.....

TUF/6139-1

FIGURE 1
Dual-In-Llne Package
OUTPUT BIT 8

20

OUTPUT BIT 9

OUTPUT BIT 7

2

19

OUTPUT BIT 10

OUTPUT BIT 6

3

18

OUTPUT BIT 11

OUTPUT BIT 5

4

17

OUTPUT BIT 12

OUTPUT BIT 4

5

16

OUTPUT BIT 13

OUTPUT BIT 3

6

OUTPUT BIT 2

1.11.15481

15

Vss

7

14

OUTPUT, BIT 14

OUTPUT BIT 1

8

13

DATA ENABLE

BRIGHT CONT.

9

12

DATA IN

Voo

II

CLOCK
TUF/6139-2

Top View
FIGURE 2
Order Number MM5481N
See NS Package Number N20A
4-95

Absolute Maximum Ratings
Junction Temperature
+ 150"C
Lead Temperature (Soldering, 10 sec.)
300"C
'Molded DIP Package, Board Mount, 8JA = 61'C/W, Derate 16.4 mWrC
above 25'C.
"Molded DIP Package, Socket Moum, fJJA = 'S7'C/W, Derate i4.9 mW/'C
above 25'C.

It Military/Aerospace specified devices are requlredj
please contact the National Semiconductor Sales
Office/DIstributors for availability and specifications.
Voltage at Any Pin
VsstoVss + 12V
- 65·C to + 15O"C
Storage Temperature
Power Dissipation at 25·C
2W'
Molded DIP Package, Board Mount
1.8W··
Molded DIP Package, Socket Mount

Electrical Characteristics
TA

= - 25·C to + 85·C, voo = 4.75V to 11.0V, Vss = OV unless otherwise specified ,

Symbol

Parameter

Voo

Power Supply

100

Power Supply Current

VIL

Input Voltages
Logical "0" Level

VIH

Logical "1" Level

Conditions

ISR
IOH

Output Sink Current
(Note 3)
Segment OFF

IOL

Segment ON

VISR

Brightness Input Voltage
(Pin 9)

OM

Output Matching (Note 1)

Max

Excluding Output Loads
± 10 p.A Input Bias
4.75

s: Voo s: 5.25

Voo> 5.25
Brightness Input Current
(Note 2)

Typ

Min
4.75

Your = 1V(Note4)
Brightness Input = 0 p.A
,Brightness Input = 100 p.A
Brightness Input = 750 p.A
' Input Current

AC Electrical Characteristics TA =

-25°C to

0.8

V

Voo

'V

Voo - 2

Voo

V

0

0.75

mA

10.0

p.A

10.0
4.0
25.0

mA

4.3

V

±20

,0/0

2.7

3.0

+ 85·C, voo =

mA

2.2

0
2.0
15.0

= 750 p.A

V

7
-0.3

= 3.0V

Your

Units

11

p.A

mA

5V ± 0.5V

Parameter

Conditions

Min

fc

Clock Input Frequency

(Notes 5 and 6)

DC

th

High Time

950

ns

Low TIme

950

ns

300
300

ns
ns

Symbol

tl
tos
tOH

, Datalnput
Set-Up Time ,
Hold TIme

Typ

Max

Units

500

kHz

Data Enable Input
Set-UpTime
100
ns
Note 1: 0u1put matching Is calculated as the percent variation from IMAX + IMIN/2.
Note 2: With a fixed resister on the brightness input pin some variation in brightness will occur lrom one device to another. Maximum brighlnass input current can
be 2 mA as long as Note 3 and junction temperature aquation are compiled with.
Note 3: Absclute maximum for each output should be limited to 40 rnA.
Note 4: The VOIIT voltege should be regulated by the user.
Note 5: AC Input waveform specificeIIon for test purpose:. " ,;; 20 ns, It ,;; 20 no, I = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock Input rise and lall times must not exceed 300 ns,
tOES

4-96

Functional Description

Data Enable

The MM5481 uses the MM5450 die which is packaged to
operate 2-digit alphanumeric displays with minimal interference to the display and the data source. Serial data transfer
from the data source to the display driver is accomplished
with 2 signals, serial data and clock. Using a format of a
leading "I" followed by the 35 data bits allows data transfer
without an additional load signal. The 35 data bits are
latched after the 36th bit is complete, thus providing nonmultiplexed, direct drive to the display. Outputs change only
if the serial data bits differ from the previous time. Display
brightness is determined by control of the output current for
LED displays. A 0.001 ".F capacitor should be connected to
brightness control, pin 9, to prevent possible oscillations.

This active low signal enables the data input pin. If high, the
shift register sees zeroes clocked in.
To blank the display at any time, (i.e., power on), clock in 36
or more zeroes, followed by a 'one' (start bit), followed by
36 or more zeroes.
Figure 5 shows the Output Data Format for the MM5481.
Because it uses only 14 of the possible 34 outputs, 20 of the
bits are 'Don't Cares'. Note that only alternate groups of 4
outputs are used.
Ftgure 3 shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
0.5 MHz is assumed.

A block diagram is shown in Ftgure 1. The output current is
typically 20 times greater than the current into pin 9, which
is set by an external variable resistor. There is an internal
limiting resistor of 4000 nominal value.
Ftgure 4 shows the input data format. A start bit of logical
"1" precedes the 35 bits of data. At the positive-going-edge
of the 36th clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35 bits of
the shift registers into the latches. At the low state of the
clock a RESET signal is generated which clears all the shift
registers for the next set of data. The shift registers are a
static master-slave configuration. There is no clear for the
master portion of the first shift register, thus allowing continous operation.
There must be a complete set of 36 clocks (high/low edges)
.
or the shift registers will not clear.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.
Tj = (VOUT) (ILEO) (No. of segments) (6JAl
where:
Tj = junction temperature, 15O"C max.

+ TA

VOUT = the voltage at the LED driver outputs
ILEO = the LED current
6JA = thermal coefficient of the package
TA = ambient temperature
6JA (Socket Mount) = 67'C/W
6JA (Board Mount) = 61·C/W

F!!!!!!!!!!!!!!!!!!!!!IIii.--9OX
""_ _~-------J1=;=-10"

DATA ENABLE

TLlF/6139-3

FIGURE 3. Timing

a.OCK

DATA

~~

(INTERNAL)

- -_. . - - - =
____ ____________
. ---" - - - ' ~-~~-~

~

.. _--_.

~~-----~n·
SS. •

RESET
(INTERNAL)
_______________

n

~ss_______l

LTLlF/6139-4

FIGURE 4. Input Data Format

4-97

~ .-------~------------------------------------------------------------------------,

=:
La

Functional Description (continuecij'

:Ii!
:Ii!

FIGURE 5. Output Data Fe»rmat
RAW ,DC
>9V
IkA

TL/F/6139-5

FIGURE 6. Typical Application of Constant Current Brightness Control

TL/F/6139-6

FIGURE 7. Brightness Control V~rylng the Duty Cycle
Safe Operating Area

Basic Electronically Tuned Television System

2.5

g

14 SEG..ENTS
VOUT=1V
2.0 /---I----[~~O
-..!!t-----t>----{~!!:!~!!~rtll!!..DATA OUT

SERtAL
DATA -

CLOCK _~-I-----[>------J

TL/F/6140-1

FIGURE 1

=
iii

;!

iii

~

'Q'

~ !~~

i

5

>

z

~

.."

~

N

iii iii iii iii iii
~
~

iiii

OUTPUT BIT 11
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT lIT 8
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
DATA OUT
OSC IN

VDo

OUTPUT BIT 12

OUTPUT BIT 17
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 28
OUTPUT BIT 28
OUTPUT BIT 30
OUTPUT BIT 31

LOAD
23

lB
19
28

22

21

OUTPUT BIT 22

BACKPlANE IN
BACKPlANE OUT
DATA IN
CLOCK IN

TL/F/6140-2

OUTPUT BIT 11

38

OUTPUT BIT 23

Top View

OUTPUT BIT 10

37

OUTPUT BIT 24

FIGURE 2
Order Number MM5483MS or MM5483N
See SSOP Package Number MS40A
See NS Package Number N40A

OUTPUT BIT 9

OUTPUT BIT 25

OUTPUT BIT 8

OUTPUT BIT 26

OUTPUT BIT 7

OUTPUT BIT 27

OUTPUT BIT 8

OUTPUT BIT 28

OUTPUT BIT 5

14

OUTPUT BIT 4

15

31

OUTPUT BIT 29

OUTPUT BIT 3

16

30

OUTPUT BIT 2

OUTPUT BIT 30
OUTPUT BIT 31
N/C

"Z -ii
........

i

:;

!!

~ ~
~f

8~ !: !!
>'

Z

~ wz
'~ .~ w

"

!!

g
~

~
'"~

9"
TL/F/6140-7

Order Number MM5483V
See NS Package Number V44A

" 4-99

Absolute Maximum Ratings

'.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons~
Voltage at Any Pin
VsstoV~ + 10V
Operating Temperature
Storage Temperature

Power Dissipatio,\}

300 rriW at + 85'C
350 mW at + 25'C
+ 1500C

Junction Temperature
Lead Temperature
(Soldering, 10 seconds)

-400Cto +85'C
-65'Cto + 1500C

3000C

DC Electrical Characteristics
TA within operating range, Voo

=

3.0V to 10V, Vss

=

OV, unless otherwise specified

. Conditions

Parsmeter

Max

Units

10

V

9
17
35

15
25
45

p.A
p.A
p.A

1.5

2.5

/LA

0.9

2.0

V
V
V
V

Min

Power Supply

Typ

3.0

Power Supply Current

=

R = 1M,C
470pF,
Outputs Open
VOrl = 3.0V .
Voo = 5.0V
Voo = to.OV
OSC = OV, Outputs Open,
BPIN = 32 Hz, Voo = 3.0V

Input Voltage Levels
Logic "0"
Logic "1"
Logic "0"
LogiC "1"

Load, Clock, Data
Voo = 5.0V
Voo = 5.0V
Voo = 3.0V
Voo = 3.0V

Output Current Levels
Segments and Data Out
Sink
Source

Voo =:' 3.0V, VOUT
Voo = 3.0V, VOUT

=
=

0.3V
2.7V

20
20

p.A
p.A

BPOUT.
Sink
Source

Voo = 3.0V, VOUT
Voo'" 3.0V, VOUT

=
=

0.3V
2.7V

320
320

p.A
p.A

2.4
0.4

AC Electrical Characteristics Voo ~ 4.7V, Vss = OV unless otherwise specified
Parsmeter

Symbol
fc

Clock FrequenCy, "DO

=

teH

Clock Period High

I
I

Min

Typ

3V
(Notes 1, 2)

Max

Units

500

kHz

500

ns

tel

Clock Period Low

500

ns

tos

Data Set-Up before Clock

300

ns

tOH

Data Hole! Time after Clock

100

ns

tlW

Minimum Load Pulse Width

500

ns

tlTC

Load to Clock

400

1000

Clock to Data Valid

Note 1: Ac Input waveform specHication lor test purpose:

ns

400

750 .

ns

Ir ,. 20 ns." ,. 20 ns. 1= SOO kHz. SO% ±10% duty cycle.

Note 2: Clock input rise and Isil times must not exceed 300 ns.
NDIe 3: Output offset voltage Is ±50 mV with CseOMENT

= 2SO pF, CaP

= 87SO pF.

Functional Description
A block diagram for the MM5483 is shown in Figure 1 and a
package pinout is shown in Figure 2. Figure 3 shows a possible 3-wire connection system with a typical signal format
for Figure 3. Shown in Figure 4, the load input is an asynchronous input and lets data through from the shift register
to the output buffers any time it is high. The load input can
be connected to Voo for 2-wire control as shown in Figure
5. In the 2-wire control mode, 31 bits (or less depending on

the number of segments uSed) of data are clocked into the
MM5483 in a short time frame (with less than 0.1 second
there probably will be no noticeable flicker) with no more
clocks until new information is to be displayed. If data was
slowly clocked in, it can be seen to "walk" across the display in the 2-wire mode. An AC timing diagram can be seen
in Fl{Jure 6. It should be noted that data out is not a TTLCompatible output.

4-100

Functional Description (Continued)

8UK

LOAD
DATA

---

CLDCK---......~--+-----....

LOAD_------+--------+--_

TUF/6140-3

FIGURE 3. Three-Wire Control Mode

,~H

I

I

I

I

I

I

I

I

I

LDAD ______________~~~--------~f1TlMETUF/6140-4

FIGURE 4. Data Fonnat Diagram

CLOCK - - -......~------.......... - - - - - - _

TL/F/6140-5

FIGURE 5. Two-Wire Control Mode

CLOCK

DATA

I
LOAD _+-_ _-Jl

•

-'Lw-I-'LTC

--ItCDD

1-

\""----_

. .X. .~---

D:~~ ___...JX~----

TL/F/6140-6

FIGURE 6. Timing Diagram

4-101

Ii

tJ1

National Semiconductor.

MM5484 16-Segl1lent LED Pispl"y [)river
General Description
The MM5484 is a low threshold N-channel metal gate cirCljit
using low threshold enhancement and ion implanted d~ple­
tion devices. The MM5484 is available in a 22-pin molded
package and is capable of driving 16 LED segments. The
MM5484 is designed to drive common anode separate cathode LED displays.
. ..
..

Features

,l,\

•
.•
•
•
•

MM5484 is cascadeable
TIL comPatibility
.
No load Signal required
NOn multiplex display.
2% digit capabilit)'-MM5484

Applications··
.• COPSTM or microprocessor displays
.·Instrumentation readouts
• Industrial control indicator
• Relay driver

•

• Serial data input
• Wide power supply operation
• 16 output, 15 mA sink capability

Block and Connection Diagrams
16 SEGMENT OUTPUTS

ENABlE 0-....- - - 4

DATA
OUT

CUiCK..--"'I...._
DATA INo--.....;~--...1

FIGURE 1. M145484

Oual-In-Une Package

PLCC

013

22

014

21

011

016

20

010

06

016

ENA6LE

DATA IRIT

Yoo

012

MM5484

010
N/c

DATA OUT

CLOCK IN

vas

BATAIN

016

N/C

01

06

DATA IN

02

07

01

06
D5

02

12

09

MM5484V

VDD

ENABLE
CLOCK IN

20

11

vss
08

TLIF18141-3

Top View
TLIF16141-8

Order Number MM5484N
See NS Package Number N22A

Top.vlew
Order Number MM5484V
See NS Package Number V28A

4-102·

Absolute Maximum Ratings
If Military/Aerospace speclfled devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrtbutors for availability and specifications.
Voltage at LED Outputs
VOltage at Other Pins

Operating Temperature

-40°C to +'85"C

Storage Temperature

-400Cto + 1500C

Power Dissipation at 25°C
Molded DIP Package, board mount
Molded DIP Package;socket mount

Vss - 0.5V to Vss + 12V
Vss - 0.5V to VSS + 10V

'Molded DIP Package, board mount,
above 25°C.
derate 15.8m W

8JA

=

63°C/W,

• 'Molded DIP Package, socket mount,
derate 14.5m W'OC above 25°C.

8JA

=

69"C/W,

rc

,

2W'
1.8W··

Lead Temperature (Soldering, 10 sec.)

DC Electrical Characteristics Voo = 4.5V to 9V, TA =
Parameter

Conditions

-400C to +85°C unless otherwise specified

Min

Supply Voltage

Typ

Max

Units

9

V

10

mA

2.4

Voo + 0.5

V

0

0.8
±1
7.5

V
p.A
pF

0.5
50

V
V
p.A

1.0

V

4.5

Supply Current

5

Logic One
Input High Level VIH
Logic Zero
Input Low Level VIL
Input Current
Input CapaCitance

3000C

High or Low Level

OUTPUTS
Data Output Voltage
High Level VOH
Low level VOL
Segment Off
(Logic Zero on Input)

lOUT = 0.1 mA
lOUT = -0.1 mA
VOUT = 12V
REXT = 4000

Output Current Segment On
(Logic One on Input)
Output Voltage

lOUT = 15mA
Voo ~ 6V

Voo - 0.,5

0.5

AC Electrical Characteristics
(SeeF,gure3.)Voo
Symbol

=

4.5Vto 9V, TA

=

Parameter

-400Cto + 85°C unless otherwise specified
Conditions

Min

Typ

Max

Units

0.5

MHz

fc

Clock Frequency

th

High Time

0.95

~

Low Time

0.95

p.S

lst

Data Setup Time

0.5

p.s

tHt

Data Hold Time

0.5

p.S

ts2
lH2

Enable Setup Time

0.5

p.S

Enable Hold Time

0.5

p.s

lpd

Data Out Delay

p.s

0.5

Note 1: Under no condition should the power dissipated by the segment driver exceed 50 mW nor the entire chip power dissipation exceed 500 mW.

Note 2: AC input waveform specification lor test purpose: t, ,; 20 ns, tf ,; 20 ns, I
Note 3: Clock Input rise and fall times must not exceed 500 ns.

= 500 kHz. 50% ± 10% duty cycle.

4-103

p.s

Functional Description

"'.

The MM5484 is designed to drive LED displays directly. serial data transfer from the data source to the display driver is
accomplished with 3 signals, DATA IN, C,LOCK and ,ENABLE. The signal ENABLE .acts ~ an envelope and only
while this signal is at a logic '1'(10 the circuits recognize the
clock signal.
.
.'
While ENABLE is high, data on the serial data input is transferred and shifted in the internal shift register on the rising
clock edge, i.e. a logic '0' to logic '1' transition. .

When.the ENABLE signal goes to a low (logic zero state),
the contents of the shift register is latched and the display
will shOW the 'new data. While new data is being loaded into
the SR the display will continue to shQw the old data.
For the MM5484, data is output from the serial DATA OUT
pin on the falling edge of clock so cascading is made simple
with race hazards eliminated.
When the chip first powers on, an internal power on reset
signal is generated which resets the SR and latches to zero
so that the display will be off.

Timing Diagram

CLOCK

ENABLE------

DATA I N - - - - - - '

-II:-Ipd--~

..Jl

DATA D U T - - - -_ _ _ _ _ _ _ _

FIGURE 3

4-104

\\.------

tJ1

Nat ion a I S e m icon due tor

MM5486 LED Display Driver
General Description
The MM5486 is a monolithic MOS integrated circuit utilizing
N-channel metal-gate low-threshold, enhancement mode
and ion-implanted depletion mode devices. It is available in
a 40-pin molded dual-in-line package. The MM5486 is designed to drive common anode-separate cathode LED displays. A single pin controls the LED display brightness by
setting a reference current through a variable resistor connected to Vee.

Features
• Continuous brightness control
• Serial data input!outut

•
•
•
•

Extemalload input
Cascaded operation capability
Wide power supply operation
TTL compatibility
• 33 outputs, 15 mA sink capability
• Alphanumeric capability

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Relay driver
Digit81 clock, thermometer, counter, voltmeter
Instrumentation readouts

Block and Connection Diagrams
Dual-In-Llne Package
VIII

TLlF/6142-1

FIGURE 1

OUlPUT 81T 11
OUlPUT an 15
OUTPUT lIT 14
0U1PUT lIT 13
OUTPUT lIT 12
OUTPUT lIT 11
IIU'IM lIT 10
OUlPUT an.
OUTPUT lIT.
0U1PUT lIT 7
IIU'IM an I
OUTPIIT lIT 5
OUTPUT lIT 4
0U1PUT an 3
OUTPIIT lIT Z
OUlPUTan 1
DATA OUT
-'COIIT1IOL

vaa

6
OUTPUT BtT 12

5

.4

3

2

1 44 '3 42

7

41
31
31
17
31

12
13
14
11
11

..-

17

11
19
21

IIU'IM an 17
OUlPUT lIT 11
OUlPUTan 18
0U1PUT lIT III
0UlPUT lIT ZI
0U1PUT an 22
IIU'IM ann
0U1PUT lIT Z4
0U1PUT an Z5
IIU'IM lIT ZI
OUTPIIT lIT Z7
OUTPUT lIT ZI
OUTPUT lIT 2B
0U1PUT an 30
0U1PUT lIT 31
IIU'IM an It
0UlPUT lIT 113
LW
DATA IN
CUlClCIII
TLlF/6142-2

4' .40
39

OUTPUT BIT.22

38

Top View

OUTPUT BIT 23

Order Number MM5486N

9

OUTPUT BIT 2(

See NS Package Number N40A

OUTPUT BIT 9

10

OUTPUT BIT 25

OUTPUT BIT 8

11

N/C

12

OUTPUT BIT 11
OUTPUT BIT 10

FIGURE 2

OUTPUT BIT 26

MM5488V

N/C

OUTPUT BIT 7

13

OUTPUT BIT 27

OUTPUT Btl 6

1(

OUTPUT INT 28

OUTPUT BIT 5

15

OUTPUT BIT 29

OUTPUT BIT .4

16

OUTPUT BIT 3

17

OUTPUT BIT 30

29

OUTf'UT lilT 31

TLlF/6142-13

Order Number MM5486V
See NS Package Number V44A

4-105

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
. Office/Distributors for availability and specifications.
Voltage at Any Pin
VSS to Vss + 12V
Operating Temperature
- 25'C to + 85"C
-65'C t6 + 15O'C
Storage Temperature

Power Dissipation at 2S'C
2.5W·
Molded DIP Package, Board Mount
2.3W··
Molded DIP Package, Socket Mount
Junction Temperature
+ 150'C
Lead Temperature (Soldering, ·10 secOnds)
300'C
'Molded DIP Package, board Mount. 9JA = 4!1'CIW, Derate 20.4 mWrc
above 25"C.
"Molded DIP Package, Socket Mount, 9JA = 54'C/W, oeiate 18.5 mWrC
above 25"C.

Electrical Characteristics
TA within operating range, Voo
Symbol

= 4.75V to 11.0V, Vss = OV, unless otherwise ~ified

Parameter·

Condltlona

Voo

Power Supply

100

Power Supply Current

Excluding Output Loads

VIL
VIH

Input Vollages
LogiC "0" Level
Logic "1" Level

± 10 p,A Input Bias
4.75 s: VOO s: 5.25

IBR

Brightness Input (Note 2)

10H
10L

Output Sink Current (Note 3)
Segment OFF
Segment ON

VIBR

Brightness Input Vollage (Pin .19)
Output Matching (Note 1)

VOL
VOH

Data Output
Logical "0" Level
Logjcal"l" Level

fe
th

tr

VOUT = 3.0V
VOUT = W(Note4)
Brightness Input = 0 p,A
Brightness Input = 100 p,A
Brightness Input = 750 p,A

-0.3
2.2

Clock Input
Frequency
High Time
Low Time

Input Current

lOUT
lOUT

= 750 p,A

= 0.5mA
= 100 p,A

Max

. Units

11

V

7

mA

0.8
Voo

V
V

Voo-2

Voo

V

0

0.75

mA

. 10

p,A

10
4
25

mA
mA

40

mA

0
2.0
15

Maximum Segment Current

OM

Typ

4.75

Voo> 5.25

10

Min

3.0

Vss
2.4

2.7

p,A

4.3

V

±20

%

0.4
Voo

V
V

500

kHz
ns
ns

(Notes 5 and 6)
950
950

Data Input
Set-Up Time .
ns
300
tos
Hold Time
300
ns
tOH
Note 1: Output matching Is calculated as the percent variation (lMAX + IMIW/2.
Note 2: With a fixed resistor on the brightness input pin, some variation in brightness will oocur from ona device to another. Maximum brightnass input current can
be 2 rnA as long as Note 3 and junction temperature equation are complied with.
_
3: Absolute maximum for aach output shoUld be limited to 40 rnA.
Note 4: The Vour voltage should be regulated by the user. See FI(lUfSS 6 and Tfor allowable VOUT va lOUT operation.
_
5: AC Input waveform specification for test purpose:" " 20 08,,, " 20 ns, f·= 500 kHz, 50% ±10% duty cycle.
Note 8: Clock inpUt rise and fall times must not exceed 300 08.

4-106

Functional Description
When the chip first powers ON, an internal power ON reset
signal is generated which resets all registers and latches.
The leading clock returns the chip to its normal operation.

The MM5486 is specifically designed to operate four-digit
alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data
source to the display driver is accomplished with 3 signals,
serial data, clock, and load. The data bits are latched by a
positive-level load signal, thus providing non-mUltiplexed, direct drive to the display. When load is high, the data in the
shift registers is displayed on the output drivers. Outputs
change only if the serial data bits differ from the previous
time. Display brightness is determined by control of the output current for LED dIsplays. A 0.001 ,...F capacitor should
be connected to brightness control, pin 19, to prevent possible oscillations. The output current is typically 20 times
greater than the current into pin 19, which is set by an external variable resistor. There is an internal limiting resistor of
4000 nominal value.

Figure 3 shows the timing relationship between data, clock
and data enable. A maximum clock frequency of 0.5 MHz is
assumed.
For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations:
TJ = (VOUT) (lLEO)(No. of segments)(I1JIV
where:

+ TA

TJ = junction temperature, 150"C max.
VOUT = the voltage at the LED driver outputs
ILEO = the LED current

A block diagram is shown in Figure 1.

II JA = thermal coefficient of the package

Figure 4 shows the input data format. Bit "1" is the first bit
into the data input pin and it will appear on pin 17. A logical
"1" at the input will turn on the appropriate LED. The load
signal latches the 33 bits of the shift register into the latches. The data out pin allows for cascading the shift registers
for more than 33 output drivers.

T A = ambient temperature
I1JA (Socket Mount) = 54°C/W
I1JA (Board Mount) = 49"C/W
The above equation was used to plot Figure 6. Figure 7, and
FigureS.

1011
1011

--

'\.

TL/F/6142-3

FIGURE 3

LEADING
CLOCK' 1
CLOCK
BIT 1

LOAD

RElETn

(INTERNAL)

BIT 32

BIT 33

~~

_ _ _ _ _ _ _ _ _ _ _ _ • _ _ _ _ _ _ _ __
TL/F/6142-4

power ON.
FIGURE 4. Input Data Format

'This leading clock is necessary only after

Yoo

--------'

CLOCK

RESET
(INTERNAL) _ _ _ _ _ _ _- '
TLlF/6142-5

FIGURES

4-107

Typical Applications
110
,IUD I:--I- .!.
VO~T~I.0Y.
~ 2D t----I>'n.:,f7"Io::

1
i..

~1.51----J:;0%':~~~­

.,.0
I

.f

i:l

CIs 1---l'74<;.<;I"h".4S444<---'I

8.5H+lH-H+I++4+1--1

o~~~~~~~--~

O~~~~~~~~U

o

2D

40
III
III
Tt:Ill'ERATURE (OC)

.~

co

0481211ztJ2428

100

Ie
..
10 ~-+. _u~.l.Jy
·.1
I
III ~l'<
-1It"ty
MAX 1OUT-400IA
III
~ I'\:

:40

3D
ZO
I.

~

o

'"

"r- """'"

'0510ISztJ253D34

NUM8B1 OF sEGMENTS

ILED (IIIAI

TlIF/6142-8

TLlF/6142-7

Tl/F/6142-6

FIGURE 7

FiGURE 6

FIGURE8 '

_DC
>8Y
Z400
4.V

":'

1
":'

TlIF/6142-9

FIGURE 9. Constant Current Brightness Control

Tl/F/6142-IO

FIGURE 10. Brightness Control Varying the Duty Cycle

4-108

Ta=85·C

10

Typical Applications (Continued)
Basic Electronically Tuned Radio System
LED DISPLAY

AM

IC :::In

FM/O:::JU

PlL
SYNTHESIZER

KEYBIIAlID

STATlDN
DETECT. ETC.
Tl/F/6142-11

Duplexlng 8 Digits with One MM5486

MM5418

CLOCK IN ....- - -......
DATA IN ....- - - -....... L....<~I\r-+- VOO
BRIGHTNESS
CONTROL

LOAD ....- - - - - - - - - - - - - - '
TUF/6142-12

"This driver has 7 segments only.

4-109

II

.- r--------------------------------------------------------------------------------,

I til Nat ion a
~

I S e m i co n due to r

MM58241 High Voltage Display Driver
General Description

Features

The MM58241 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P- and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58241 is particularly suited for driving high voltage (SOV max) vacuum fluorescent (VF) displays (e.g., a 32-digit alphanumeric or dot matrix display).

• Direct interface to high voltage display
• Serial data input
• No external resistors required
• Wide display power supply operation
•. LSTIL compatible inputs
• Software compatible with NS display driver family
.' Compatible with alphanumeric or dot matrix displays
• Display blanking control input
• Simple to cascade

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive daShboards

Block Diagram
OUTPUT
32

OUTPUT
1

_.. -.BLANKING_--1+-_ _ _ _....
CONTROL

"-,",--VoIs

CLOCK-+l-"

ENABLE - - - -.....
TUF/5600-1

FIGURE 1

4-110

Absolute Maximum Ratings

Operating Conditions
Min

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlonL
Voltage at Any Input Pin
VOO + 0.3V to VSS - 0.3V
Voltage at Any Display Pin
VOO to VOO - 62.5V
62.5V
VOO + IVolsl
Storage Temperature

Max

Units

4.5

5.5

V

-55

-25

V

+S5

°C

Supply Voltage (Voo)
VSS = OV
Display Voltage (VOIS)
Temperature Range

-40

-65°C to + 150"C

Power Dissipation at + 25°C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount

2.2SW·
2.05W··

Junction Temperature

130"C

Lead Temperature
(Soldering, 10 sec.)

26O"C

·Molded DIP Package, Board Mount, 6JA
Derate 21.7 mWrC above +25°C.

=

··Molded DIP Package, Socket Mount, 6JA
Derate 19.6 mW
above + 25°C.

rc

46°C/W,

=

"

51°C/W,

DC Electrical Characteristics
TA

=

-40"Cto +S5°C, VOO

Symbol

=

5V ±0.5V, Vss

=

OV unless otherwise specified

Parameter

Conditions

Power Supply Currents
100
lOIS

Min

Typ

VIN = VSS or VOO, VSS = OV,
VOIS Disconnected
VOO = 5.5V, Vss = OV, VOIS = -55V
All Outputs Low

Max

Units

150
10

mA

".A

Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
VIL
VIH

Logic'O'
Logic '1'

(Note 1)

VOL
VOH
VOH

Data Output Logic Levels
LogiC '0'
Logic '1'
Logic '1'

lOUT
lOUT
lOUT

liN

CIN

Input Currents
DATA IN, CLOCK
ENABLE, BLANK

VIN

= 400 /LA
= -10/LA
= - 500 /LA
= OV or VOO

-10

Display Output Impedances

VOO = 5.5V, Vss

ROFF

Output Off (Figure 3a)

RON

Output On (Figure 3b)

VOIS =
VOIS =
VOIS =
VOIS =
VOIS';"
VOIS =

VOOL

Display Output Low Voltage

~

2.7V

@

lOUT

~

V
V

0.4

V
V
V

10

".A

15

pF

400
550
650
4.0
3.7
3.4

kO
kO
kO
kO
kO
kO

VOIS + 4

V

Voo - 0.5
2.S

Input capacitance
DATAIN,CLOCK
ENABLE, BLANK

Note 1: 74LSTTL VOH

O.S
2.4

=

OV

60
70
SO

-25V
-40V
-55V
-25V
-40V
-55V

3.0
2.6
2.3

VOO = 5.5V, lOUT = Open Circuit,
-55V";; VOIS ,,;; -25V

-400 pA, TTL VOH~ 2.4V

@

lOUT

~

-400 pA.

4-111

VOIS

''- r---------------------------------------------------------------------------------,

:::IiI
:Ii

AC Electrical Characterist"cs::rA;;Oc,c-400Cto + 85°C, Voo =
Symbof

Parameter

" Condition'

5V ±0.5V,··

Min

fe
tH
tL

Clock Input
Frequency
High Time
Low Time

(Notes 3 and 4)

tos
tOH

Data Input
Set-UpTime
Hold Time

100
100

tES
tEH

Enable Input
Set-UpTime
Hold Time

100
100

tcoo

Data Output
CLOCK Low to Data Out
Time

I'"

Typ

Max

Units

800

:.,Ig~

a:i
s

400II MAX

AT -CO"C, Vuls = -3OV
0.5

i

0

_!!:::..--l.-,-_ _..I-_ _-1_ _ _....L._ _--;. iouT(1IA1

0

0.5

1.5
TL/F/7925-4

FIGURE 3b. Output Impedance On

Timing Diagrams

:

~__~
__:___. I:=t;.lI: ~:. . -

For the purposes of AC measurement, VIH = 2.4V, VIL = O.SV.

FIGURE 4. Clock and Data Timings

4-123

TLlF17925-5

•

Timing Diagrams (Continued)

~RM::::::::::::::~I''----=\----'~'~::::::::::::~
Vall - - - - _ - - ' "
DIII'lAY
OUTPUT

YDII---

11./F/7925-6

FIGURE 5. Timings (Data Format)

Typical Application

:

4O-DIGIT BY 2·LlNE
5 x 7 MUIJIPLEXED
DDT MATRIX VACUUM
flUORESCENT (VF)
DISPLAY

----

---35
ANODES

MM5B348 '
DISPLAY
DRIVER 1
CLOCK I

I
I

I' ,1
DATA 11

f

2D
GRIDS

35
ANODES

----

MM5B348
DISPLAY,
DRIVER 2

MM5B342
DISPLAY
DIUVER 1

1

2D
GRIDS

---OUT
FA

1

DATA 12

f

DATA 22

MM611342
DlNY
DlUVER 2

1

I

,CLDCK,2
DATA 21
MICROPROCESSOR

ENABLE
BLANK

FI~~R~ 6. MlcroPrOce88Qr-ControlledWOrd Proce880r

4-124

11./F/7925-7

r-------------------------------------------------------------------------, r

i:

~

tflNational Semiconductor

~

~

LM565/LM565C Phase Locked Loop
General Description
The LM565 and LM565C are general purpose phase locked
loops containing a stable, highly linear voltage controlled
oscillator for low distOrtion FM demodulation, and a double
balanced phase detector with good carrier suppression. The
veo frequency is set with an external resistor and capacitor, and a tuning range of 10:1 can be obtained with the
same capacitor. The characteristics of the closed loop systern4andwidth, response speed, capture and pull in
rang&-may be adjusted over a wide range with an external
resistor and capacitOr. The loop may be broken between the
veo and the phase detector for insertion of a digital frequency divider to obtain frequency multiplication.
The LM565H is specified for operation over the - 55°C to
+ 125°C military temperature range. The LM565CN is specified for operation over the O"C to + 70"C temperature range.

Features
• 200 ppmrC frequency stability of the VCO
• Power supply range of ± 5 to ± 12 volts with
100 ppm/% typical
• 0.2% linearity of demodulated output

• Linear triangle wave with ' in phase zero crossings
available
• TTL and DTL compatible phase detector input and
square wave output
• Adjustable hold in range from ±1% to> ±60%

Applications
• Data and tape synchronization
•
•
•
•
•
•
•
•
•
•

Modems
FSK demodulation
FM demodulation
Frequency synthesizer
Tone decoding
Frequency multiplication and division
SCA demodulators
Telemetry receivers
Signal regeneration
Coherent demodulators

Connection Diagrams
Metal can Package
.vee

Dual-In-Une Package
-Vee

TIMING
RESISTOR

NC .

INPUT

NC

VCO
OUTPUT
PHASE COMPARATOR
VCO INPUT
REFERENCE
OUTPUT
VCO CONTROL
VOLTAGE

VCO CONTROL
VOLTAGE

PHASE COMPARATOR
VCO INPUT
TL/H17853-2

Order Number LM565H
See NS Package Number H10C

NC

INPUT

NC
+Vcc

TIMING
CAPACITOR
TIMING
RESISTOR
TL/H/7853-3

Order Number LM565CN
See NS Package Number N14A

•
4-125

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
±12V

Supply Voltage
Power Dissipation (Note 1)

1400mW

Differential Input Voltage

- 55'C to + 125'C
OOCto +700C

Storage Temperature Range

- 65'C to + 1500C

Lead Temperature (Soldering, 10 sec.)

Parameter

25'C, Vee = ±6V

Min
Power Supply Current

< V2, Va < OV

Input Impedance (Pins 2, 3)

-4V

veo Maximum Operating

Co = 2.7pF

LM~5C

LM565

Conditions

Frequency
Co = 1.5nF
Ro = 20 kG
fo=10kHz

Frequency

2600C

±1V

Electrical Characteristics AC Test Circuit, TA =

veo Free·Running

:

Operating Temperature Range
LM565H
LM565CN

Typ

Max

8.0

12.5

7

10

300

500

-10

0

Operating Frequency
Temperature Coefficient

+10

Min

Triangle Wave Output Voltage

2

Triangle Wave Output Linearity
4.7

Output Impedance (Pin 4)
45

1.0

2.4

3

5.4

kHz

-30

0

2

4.7

+30

40

%

ppm/'C

0.2

1.5

2.4

3

%IV
Vp.p

0.5

'%

5.4

VD-D

5
55

mA

500

-200

0.1

50

12.5

250

5

Square Wave Duty Cycle

8.0

kG

0.2

Square Wave Output Level

Max,

5

-100

Frequency Drift with
Supply Voltage

Units

Typ

50

kG
60

%

Square Wave Rise Time

20

20

Square Wave Fall Time

50

50

ns

1

mA

6600

HzlV

..

Output Current Sink (Pin 4)

0.6

veo Sensitivity

fo = 10kHz

Demodulated Output Voltage
(Pinn
-,

± 10% Frequency Deviation

Total Harmonic Distortion

± 10% Frequency Deviation

0.6

6600
250

Output Impedance (Pin 7)
DC Levsl (Pin 7)

1

300

400

0.2

0.75

200

3.5
4.25

Output Offset Voltage
IV7 - Vel

ns

300

450

0.2

1.5

3.5

4.5

4.75

30

100

4.0

mVp-p
%
kG

4.5

5.0

V

50

200

mV

500

AM Rejection

40

40

dB

.68

.68

Vlradian

30

Phase Detector Sensitivity Ko

500

p.VI"C

Temperature Drift of IV7 -, Vel

Note 1: The maximum iunction temperature of the LM565 and LM565C is + 15O"C. For operation at elevated temperatures. devices in the TQ.S peckage must be
derated based on a thennal resistance of + 15O"C/W junction to ambient or + 45'C/W junction to case. Thermal resistance of the dua~In-line package Is
+8S'C/W.

4·126

Typical Performance Characteristics
Power Supply Current as a
Function of Supply Voltage

Lock Range as a Function
of Input Voltage

VCO Frequency
lOOk

T.-d"C

j

Ii

I

11

L.

-

-:- -RI*~ J'
./

i

:Ii

.§1.3

r-

iu

I

-LL
u u a U H a

~

I.

Oscillator Output
Waveforms
Vcx:· ..V

I"

V

~

-

T.-~

"-

1.
!!

V

1iI

..

1H

~

I.

JolZh

"",--

hlZ

i

3!
i

!..

z.DI.

~

rl

•

1M

VCO Frequency as a
Function of Temperature

I. ~ :
iE
w

Vee =tlV

1.1
I..

a
-I..

........

r-...

E-1.I

~

1~1;1"'f

lilt
lOOk
FRERUENCY 11111

Ik

1-1.1

r-..

"""

!I-2.1

u
IA
"I NORMALIZEO
fRERUENCY

I

-10

a 21 .. 71 180 121
TEMPERATURE I"CI

~.

Hold In Range as a
Function of R6-7

T.-WC'
vcc·:tIV
~

ll-

II-

I-

l-

'-

fll-

§ 1.Dt. ~

i..

..

~,.

Loop· Gain vs Load
Resistance
LOt.

4.v

l..of

ZD

a.l2.

I,

h~

~~

II

Ii :

~

Vcc·ttlV:

1.. la140
:I

188

Phase Shift vs Frequency
T -25"C

II~-Wr

Ii

III
PEAKTO PEAK INM VOLTAGE I..VI

~

::

11111

l'

TOTALIUfPLY VOLTA8UVI

V

C-III,F

==

~~'1I11i

II1II11
11111

1.1

'/
~

C-D.01.F

-we

~ 1.4

./

u

TA

:~;_?IY

1.5

IS

./

I-lot

Vce-" V

=
'"'

1.1

./

~

'-

-

180

~

'Ik

~

l-

I~

ff-

II-

'lilt

lOOk

D.2
U
1.0
1.4
1.1
RELATIVE FREE RUNNING VCO FREtlUEIICY .

RESISTANCE IETWEEN PlNlI AND 711\1

TL/HI7853-4

III
4-127

LM565/LM565C

W

:J'
II

PHASE
COMPARATOR

REFERENCE
OUTPUT

veo

VCO
CONTROL
VOLTAGE

INPUT

R9
5.1k

AI
7.2k

CD

I

TIMING
RESISTOR

TIMING
CAPACITOR

3

VCO
,OUTPUT

+Vee

!.

n"

B12
3.Bk

"4-0VO:L~:E
(VJ-Va)
DEMODULATED
OUTPUT

48Ik

3D pF

1h'r
':"

-IV

SOU ARE WAVE
OUTPUT

TL/H17853-5

Nota: 8, open for output offset voltage 1Y7 - Val meesurement.

Typical Applications
2400 Hz Synchronous AM Demodulator
+lIV

... ...

.l1li4
DEMODULATED
OUTPUT

18k
II8k

LM1581

•

51'

Ilk

TLIH17853-6

4-129

Typical Applications (Continued)
FSK Demodulator (2025-2225 cpa)
+12V
10k

15k

r".,

Zk

Uk

OUTPUT TO

PR11TER
MAGNET
ORIVER

5~f

10k

TL/H/7853-7

FSK Demodulator with DC Restoration
+24V

120
" ' " SDIJF
150

10k

..L

15V

5O~V

"
DUTPUTTD

PRINTER
MAGIET
DRIVER

TL/HI7853-8

4-130

Typical Applications (Continued)
Frequency Multiplier (X 10)
+6V

=

f INPUT 10 kHz

100nF

01 ..........----{
lk r-.....--{
lk

Il00nF
....--+-------ofOUlPUr= 100 kHz

9

8

MM74C90

L..."';;;""'-O+6V
TLlHI7853-9

IRIG Channel 13 Demodulator
r----~t-~--------~---~-_()+6V

.01

470k

IN~ ""+-It---(

-

OUTPUT

47k

390k

-BV

R4
250k

4-131

1 ~F

~

III
TLlHI7853-10

Applications Information
In designing with phase locked loops such as the LM565,
',
'
the important parameters of interest are:

The nat\Jral bandwidth of the closed loop response may be
found 'from:

FREE RUNNING FREQUENCY
f ,",' 0.3

.RoCci

0, -

Asscciated with this is a damping factor:

LOOP GAIN: relates the amount of phase change betw~n
the input signal and the veo signal for a shift in input signal
frequency (assuming the loop' remains in lock). In servo theory, this is called the "velocity error coefficient."
Loop gain = KoKo

For 'narrow band applications where a narrow noise bandwidth is desired, such as applications involving tracking a
s'~wly varying carrier, a lead lag filter should be used. In
general, if 1/R,Ci < Ko Ko, the damping factor for the loop
becomes quite small resulting in large overshoot and possible instability in the transient response of the loop. In this
case" the natural frequency of the loop may be found from

(radi:~:seC)

Ko = phase detector sensitivity (

vOd~ )

ra Ian

The loop gain of the LM565 is dependent on supply voltage,
and may be found from:

1

f -

2'11'

n -

Ko Ko = 33.6 fo
Vc
fo = VCO frequency in Hz

1',

{KJ1000l)

AI

CZ~~CI
Connect Pin 3 to 2~8V 10 Invert outPut

TLlH/6975-~

TLlH/6975-7

PrecIsIon O8clllator Drive 100 mA Loads
+

LM5&7
VCO
TERMINAL
1+8lI)

CZ1'1'CI
TLlH/6975-6

AC Test Circuit

Applications Information
The center frequency of the tone decoder is equal to the
free running frequency of the VCO. This is given by

5V

1
fo " ' - - -

1.

1.1 R1C1
The bandwidth of the filter may be found from the approximation

Cl'
11033

BW = 1070

~foVci2 in % offo

Where:
VI = Input voltage (volts rms), Vi
C2 ..;. CapaCitance at Pin 2 (p.F)

TTT
C;

C;

SIGNAL +5V
INPUT

;

TLlH/6975-9
~ ~ 100kHz + 5V
'Nota: Adjust for 10 = 100kHz.

4-138

s: 200 mV

~National

Semiconductor.

LM 1596/LM 1496 Balanced Modulator-Demodulator
General Description

Features

The LM1596/LM1496 are doubled balanced modulator-demodulators which produce an output voltage proportional to
the product of an input (signal) voltage and a switching (carrier) signal. Typical applications include suppressed carrier
modulation, amplitude modulation, synchronous detection,
FM or PM detection, broadband frequency doubling and
chopping.

• Excellent carrier suppression
65 dB typical at 0.5 MHz
50 dB typical at 10 MHz
• Adjustable gain and signal handling
• Fully balanced inputs and outputs
• Low offset and drift
• Wide frequency r9sponSEt up to 100 MHz

The LM1596 is specified for operation over the -55"C to
+ 125·C military temperature range. The LM1496 is specifiecl for operation over the O·C to + 700C temperature range.

Schematic and Connection Diagrams
Metal can Package
I("

CARRIER 7(8)
INPUT
+

GAIN ADJUST

-CARRIER
INPUT

GAIN ADJUST

+CARRIER
INPUT

4(")

SIGNA\.
INPUT 1(1)
+
GAIN
ADJUST

BIAS

5(5)

TUH17887-2

BIAS

Top View
Note: Pin 10 is connected electrically to the
case through the device substrate.

Order Number LM1496H or LM1596H
See NS Package Number HOse
I("

10(14)
TUHI7887-1

Dual-In-Llne and Small OuUlne Packages

Numbers in parentheses show DiP connections.

+SIGNALIN
GAIN ADJUST
GAIN ADJUST
-SIGNAL IN
BIAS

14
2

13

3

12

I("

-OUTPUT
-CARRIER INPUT
+CARRIER INPUT
TUHI7887-3

Order Number LM1496M or LM1496N
See NS Package Number M14A or N14A

4-139

II

Absolute Maximum Ratings
Soldering Information

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Seles
Office/Distributors for availability and specifications_
Internal Power Dissipation (Note 1)
500mW
Applied Voltage (Note 2)
30V
±5.0V
Differential Input Signal (V7 - Va>

260"C

..

Vapor Phase (60 seconds)
Infrared (15 seconds)

Differential Input Signal (V4 - V 1)
±(5+ 15RO)V
Input Signal (V2 - V1, Vs - V4>
5.0V
12mA
Bias Current (15)
Operating Temperature Range LM1596 ":'55°Cto + 125°C
LM1496
O"C to + 70"C
Storage Temperature Range
-65"Cto +150"C

Electrical Characteristics (TA =

,.

• Dual-In-Line Package
Soldering (10 seconds)
• Small Outline Package

215°C
22O"C

See AN-450 "Surface Mounting Methods arid their eflects
on Product Reliability" for other methods of soldering surface mount devices.

25°C, unless otherwise specified, see test circuit)

Parameter

LM1596

CondHlons

LM1496

Units

Min Typ Max Min Typ MIx
Carrier Feedthrough

Carrier SuppreSSion

Transadmittance Bandwidth

Ve = 60 mVrms sine wave
fe = 1.0 kHz, offset adjusted
Ve = 60 mVrms sine wave
fe = 10kHz, offset adjusted
Ve = 300 mVpp square wave
fe = 1.0 kHz, offset adjusted
Ve = 300 mVpp square wave
fe =: 1.0 kHz, not offset adjusted
fs
fe
fs
fe

=
=
=
=

10kHz, 300 mVrms
500 kHz, 60 mVrms sine wave offset adjusted
10 kHz, 300 mVrms
10 MHz, 60 mVrms sine wave offset adjusted

50

RL = 500
Carrier Input Port, Ve = 60 mVrms sine wave
fs = 1.0 kHz, 300 mVrms sine wave
Signal Input Port, Vs = 300 mVrms sine wave
V7 - Va = 0.5Vdc

40

40

,...Vrms

140

140

,...Vrms

0.04

0.2

0.04

0.2

mVrms

20

100

20

150

mVrms

65

50

65

dB

50

50

dB

300

300

MHz

80

80

MHz

3.5

VIV

Voltage Gain, Signal Channel

Vs = 100mVrms,f= 1.0 kHz
V7 - Va = 0.5Vdc

Input Resistance, Signal Port

f = 5.0 MHz
V7 - Va= 0.5 Vdc

200

200

kO

Input Capacitance, Signal Port

f = 5.0 MHz
V7 - Va = 0.5Vdc

2.0

2.0

pF

40

40

kO

5.0

5.0

pF

Single Ended Output Resistance' f = 10MHz
Single Ended Output
Capacitance

f = 10MHz

2;5

3.5

2.5

Input Bias Current

(11 + 14)/2

12

25

12

30

Input Bias Current

(17 + 1a>/2

12

25

12

30

Input Offset Current

(11 -14)

0.7

5.0

0.7

5.0

Input Offset Current

(17 -Is)

0.7

5.0

5.0

5.0

Average Temperature
Coefficient of Input
Offset Current

(-55°C < TA < +125°C)
(O"C < TA < +70"C)

2.0

(la -19)

14

Average Temperature
Coefficient of Output
Offset Current

(-55"0 < TA < + 125°C)
(O"C < TA < + 70"0)

90

50

14

60

,...A
nArC

90

4-140

,...A
nArC
nAloC

2.0

Output Offset Current

,...A
,...A
,...A

nA/oC

r"

Electrical Characteristics (TA =
Parameter

I:
....
en

25°C, unless otherwise specified, see test circuit) (Contiotied)

Typ

Min
Signal Port Common Mode
Input Voltage Range

f8 = 1.0 kHz

Signal Port Common Mode
Rejection Ratio

V7 - Va = 0.5Vdc

CD

Ul1496

LM1696

Conditions

Max

Min

5.0

Units

Typ

Max

G)
.....
r"

......

I:

5.0

Vp-p

CD

G)

-85

-85

dB

Common Mode Quiescent
Output Voltage

8.0

8.0

Vdc

Differential Output Swing
Capability

8.0

8.0

Vp-p

+I)

Positive Supply Current

(Ia

Negative Supply Current

(110)

Power Dissipation

2.0

3.0

2.0

3.0

3.0

4.0

3.0

4.0

33

Note 1: LMI596 rating applies to case temperatures to
temparatures to + 70'C.

mA
mA
mW

33

+ 125"C; derate Unearly at 6.5 mWrc for ambient temperature above 75"C. LM1496 rating applies 10 case

Note 2: Vollage applied between pins 6-7. 8-1. 9·7. 9-8. 7-4. 7-1. 8-4. 6-8, 2-5, 3-5.

Note 3: Refer 10 retsl596x drawing lor apacifications 01 military LMI596H versions.

Typical Performance Characteristics
carrier Suppression V8
carrier Input Level

Carrier Suppression V8
Frequency

10

10

20

20

30
40

50

.... _f-

I"'i'.

_~500kHz

I'r-70
o

100

200

300

400

500

eo

-

70
D.05 0.1

Ie

~

r3fc

o.s 1.0

5.0 10

I
I I
I
I I
~PUT~ eoc\ ms I=a

"'"

V

~
~

-"
""

50

100

~

~

300 mY

i

100 mY

CARRO LEVEL (mVrms)

200

Slgnal-Port Frequency
Response

~

~mY

J

5.0 10

~

400 mY

150

o.s 1.0

CARRIER FREQUENCY (MHz)

Sideband and Signal Port
Transadmlttances vs
Frequency

Sideband Output vs
carrier Levels
2»

50

CARIIIER FREQU£NC"( (MHz)

CARRIER INPUT LEVEL (mVnno)

I

l,.;

30
40

fl'1.=10MHz
,~

eo

carrier Feedthrough vs
Frequency

0L--..:!!.==---0.1
1.0
10
100
1000
CARRER F£QUENCY (MHz)

_

-20

Re

A,= ,.+2
-30
..
o.ot
0.1

1.0

10

100

FREQUENCY (MHz)

TlIHI7887 -5

4-141

•

Typical Application and Test Circuit
Suppreased Carrier Modulator
lk
r----.--~~--._-------J~~------~--._--~O+12V

O.IJ.1f

1

lk

I

51

51

-- -==

i-

2.47J.1fI~

R.lk
2(2)
7(8)

3.9k

3(3)-=

3.9k

6(6) . . . - -.....-~ +Vo

CARRIER~II---_-4_""';'-I8(10)
INPUT "VCJIJ.lf
L.. 1596

Vs

..ODULATIONo-.-_ _ _......_---Il(l)
INPUT

9(12) Jo-o----....-O-Vo

r---+-......-I4(4)
~ 10k

10k

1014)

51

•
LJw.,,-j

CARRIER

O47 J.lf
Ih~'

...--

-:.:

NULL_

5(5)

51

-

I...---~O--..

I

.

6.8k

Numbers in parentheses show DIP connections.

-==

-8 V

TLlH/7887-4

Note: 51 Is closSO @ 10.7 MHz
TOK Electronics
TP041 D-180K or equivalent
Cu>70@10'7MHZ'Lto
resonate w/82 pF @ 10.7 MHz
•
14T . . . TOKO KAC-K2318HM or
equivalent

O

Comments
AC coupling for wide band AGC input
Buffer and AGC supply decoupling
IF decoupling capacitors
Meter decoupling capacitor
~C coupling for IF output
Regulator decoupling capacitor, affects SIN floor
Level mute/stop time constant
,AFT decoupling, affects stop time
Disables noise mute/stop
AC coupling for noise mute/stop threshold adjust
,
Supply decoupling
AGC output decoupling Capacitor
Wide band AGC threshold adjust
Gain set and bias for IF; R2 + R3 = 3300 to terminate ceramic filter
Sets full·scaIe on meter
'Deviation mute/stop window adjustment
Mute/ stop filter, affects stop time
Level mute/stop threshold adjustment
Level mute/stop threshold adjustment
Noise mute/ stop threshold adjustment, decrease resistor for lower
SIN at threshold. for optimum performance over temp. and gain varia·
tion, set this resistor value so that the signal level mute/stop threshold
occurs in the radio at 4SdB SIN (± 3 dB) in mono.
Load for open-collector stop output
AGC output load resistor for open-collector output .
Sets Q of quadrature coil affecting THO. SIN and recovered audio
Optimises minimum THO
Sets signal swing across quadrature coil, High Q is important to mini·
mize effect variation of Q has on both minimum THO and AFT offset
10.7 MHz quadrature coil: QUL > 70

TUHI7509-5

CF1,CF2

Murata SFE1 0.7ML or equivalent

10.7 MHz ceramic resonators provide selectivity; gcod group delay
characteristics important for low THO of system
4-148

r-----------------------------------------------------------------------------~ ~

....

iii:

Typical Application
LAYOUT CONSIDERATIONS

the input signal ground and the buffer ground, pin 19. The
ground terminal on CF2 should return to the ground side of
C4. The quadrature coil T1 and inductor L1 should be separated from the input circuitry as far as possible.

Although the pinout of the LM1865 has been chosen to minimize layout problems, some care is required to insure stability. The ground terminal on CF1 should return to both

m

PC Layout (Component Side)

TUHI7509-6

PERFORMANCE CHARACTERISTICS OF TYPICAL
APPLICATION WITH TUNER

5.5 dB nOise figure, and 30 dB of AGC range. The tuner was
driven from a 500 source. 75 p.s of de-emphasis was used
on the audio output, pin 15. The 0 dB reference is for ± 75
kHz deviation at 400 Hz modulation.

The following data was taken using the typical application
circuit in conjunction with an FM tuner with 43 dB of gain, a
Meter Output and
Signal-to-Noise
vs Tuner Input

til

.....,..,

10

Iii

0
~:!!. -10
a:fi- 20

:, -40
~i -50

2V

Ii! -70

1V

~

f

/
A~=, r-r -

~

iii- -38 3V

~e

'"I

\

-60
-80
-90

Total Harmonic Distortion vs
Tuner Input

./

•.1 1

...Je
IF "'.ROW 8MII
LOOP IS ACTUAT£O

, - i'.""'::::LD

\ I
/

/

I

i"- /""\1.,..,
/'

'::T~:HOLO

10 100 1k 10k 100k 1000k

TUNER INPUT (~VI

iii

10

1_

AUDIO

0

11.-10

'lr1--3020 L/

~

Iii

S,il-

.. 1-40
-60
~

~

Il100=400 Hz

mO+NOISE
"fISE

0.1

1

1_ 0
§~-10
ii =- -20

AUDIO

IL
l\

_1-40

1"-

&i-

AM Rejection vs Tuner
Input
10

iii- -30

\\
\.\.

60
70
-80
-90

iii

10 100 lk 10k 100k 1000k

TUNER INPUT (joY)

1\\
:\
'Y

~1-60

ail!
\!!

~

AM (30% MDOI

\..

~2 -50
-70
-80
-90

II \.
I"J.SE

1
0.1

1

10 100 1k 10k 100k 1000k

TUNER INPUT I/IV)
TlIHI7509-7

-3 dB limHing

30 dB quieting

= 0.9,.V
= 1.4,.V

Level stop/mute threshold = 1.4,.V
Deviation mute window (-3 dB)

=

II

±45 kHz

4-149

U) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

....
=
~

Application Notes
sponds to a weaker signal at the antenna of the radio.)n
chOOSing the correct value for R9 it is important toinake
sure tliat recovered audio belOw 75 kHz is tiot sufficient to
cause mute/stop action. This 'is because stereo and SCA
iritOrmatiOn are contain8d in the audio Signal up to 75 kHz.
Also note that the ultrasonic mute/stop circuit will not operate properiy unless a tuner is connected to the IF. This is
because, at low Signal levels, the noise at the tuner output
dominates any noise sources in the IC. Consequently, driving the IC directly with a 500 generator is much less noisy
than driving the IC with a tuner. and therefore not realistic.
The RC 'filter on pin 12 not only filters out noise from the
comparator output but controls the "feel" when manually
tuning. For eXample, 'a very .long time conStant will cause
the mute to remain active if you rapidly tune through valid
. strong stations and will only release the mute if you slowly
tune to a valid Station. Conversely, a short time constant will
allow the mute to kick in and 'out as one tunes rapidly
througtivalid Stations.
The adVantage in using the noise mute/stop approach versus the meter driven approach is that the point at which
mute/stop action occurs is directly related to the signal-tonoiSe ratio in the recovered audio. Furthermore, the mute/
stop threshold is not subject to production and temperature
variations in the meter output voltage at low signal levels,
and thus might be able to be set without a production adjustment of the radio. The .nolse mute/stop threshold is very
insensitive to temperature and gain variations. Proper operation of this circuit requires that the signal level mute/stop
threshold be set at a signal level that achieves 45 dB SIN
(± 3 dB) in mono. in a radio. In an electronically tuned radio,
the signal level stop threshold can be set to a much larger
level by. gain reducing the tuner (ie. pulling the ,AGe line) in
scan mode and then releasing the AGO once .the radio
stops ona station. In an environment where temperature
variations are minimal and manual adjUstment of the signal
level mute/stop threshold is desired, 'thEm the meter driven
approach is the best alternative.

ADJUSTABLE MUTE/STOP THRESHOLD
The threshold adjustments for the mute and stop functions
are· coi1trolled by the same pins. Thus, the term mute/stop
will be used to designate either function.
The adjuStable mute/stop threshold in the LM1865 allows
for user programming of the signal level at which muting or
stop indication takes place. The adjustment can be made in
two mutually exclusive ways. The first way i.s,to take a voltage divider from the meter output (pin 8) to the off channel
mute input (pin 13). When the voltage at pin 13 falls below
0.22V, an internal comparator is tripped causing muted or.
causing the stop output to go low. Adjustment of the voltage
divider ratio changes the Signal level at which this happens.
The second method of mute/stop detection as a function of
signal level is to use the presence of ultrasonic .,aise in the
recovered audio to trip the internal comparator. As the signal level at the antenna of the radio ~rops, the amount of
noise in the recovered audio, both audible and ultrasonic,
increases.
The recovered audio is internally coupled through a high
pass filter to pin 13 which' is internally biased above the
comparator trip pOint Large n8gative-going noise spikes will
drive pin 13 below' the comparator trip point and cause
mute/stop action. A simplified circuit is shOwn In F/{/t/f'8 4.
Since the input to the comparator is noise, the output of the
comparator is noise. Consequently, a mute/Stop filter on pin"
12 is required to convert output noise spikes to an average
DC value. This filter is not ne~ if pin 13 is driven from
.
the meter.
Adjustment of the mute/stop threshold in the noise mode is
accomplished by adjusting the pole of the high pass filter
coupled to the comparator Input. This is done with a series
CIlpaClt6r/resistor cornbination, R9 C11, from pin 13 to
ground. As the pole is moved higher in frequency (i.e., R9
gets smaller) more ultraSOnic noise is required in the recovered audio in order to initiate mute/stop action. This corre-

50k

+

,%O.35V
L _____ 1 3 - - - - - - -

m~lpFi
TL/HI7509-8

FIGURE 4. Simplified Level Mute/Stop Circuit

4-150

.

Application Notes (Continued)
Signal Level Stop Using the Meter Output, Pin 8
STOP TIME

As mentioned previously, R6 C8 is not necessary when the

An electronICally tuned radio (ETR) pauses at fixed intervals
across the FM band and awaits the stop indication from the
LM1865. If within a predetermined ' period of time, no stop
indication is forthcoming, the controller circuit concludes
that there is no valid station at that frequency and will tune
to ,the next interval. There are several time constants that
can affect the amount of time it takes the LM1865 to output
a valid stop indication on pin 16. In this section each time
cOnstant will be discussed.

meter output is used to drive pin 13. Consequently, this time
constant is not a factor in determining the stop time. However, the speed at which the meter voltage can move may
become important in this regard. This speed is a function of
the resistive load on pin 8 and filter capacitance, C5.
AGC Time Constant
In tuning from a strong station to a weaker station above the
level stop threshold, the AGC voltage will move in order to
try to maintain a constant tuner output The AGC voltage
must move sufficiently fast so that the tuner is gain increased to the point that the level stop indicates a valid
station. This time constant is controlled 'by R11' and C13.

Deviation Stop Time Constant
An offset voltage is generated by the AFT ,if the LM1865 is
tuned to either side of a station. Sinca deviation stop detection in the LM1865 is detected by the voltage at pin 14, it is
important that this voltage move fast enough to make the
deviation stop decision within the time allowed by the co,ntroller. The speed at which the voltage at pin 14 moves is
governed by the RC time constant R5 C9. This time constant must be chosen long enough to remove recovered
audio frol'll pin 14 and short enough to allow, for reasonable
stop detection time.

DISTORTION COMPENSATION CIRCUIT
The quadrature detector of ~e LM1865 has been designed
with a special circuit that compensates for distortion generated by tha non"linear phase characteristic of the quadrature coil. This circuit not only has the effect of reducing distortion, but also desensitizes the distortion as a, function of
tuning characteristic. As a result, low distortion is achieved
with a single tuned quad coil without the need for a double
tuned coil which is costly and difficult to adjust on a production basis. The lower distortion has been achieved without
any degradation of the noise floor of the audio output. Futhermore, the compensation circuit first-order cancels ,the effect of quadrature coil
on distortion.

Signal Level Stop Using Ultrasonic Noise Detection
As previously mentioned, the R6
time constant on pin 12
is necessary to filter the noise spikes on the output of the
internal comparator in the LM1865. This time constant also
determines the level stop time. When the voltage at pin 12
is above Ii threshold voltage of about 0.6V, the stop output
is low. The maximum voltage at pin 12 is about 0.8V. The
level stop time is dominated by the amount of time it takes
the voltage at pin 12 to fall from O.8V to 0.6V. The voltage at
pin 12 follows an exponential decay with RC time constant
given by R6
For example if R6 = 25k and C8 = 2:2 p.F
the stop time is given by

ca

a

When measuring the total harmonic distortion (THO) of the
LM1865, it is imperative that a low distortion RF generator
be used. In the past it has been possible to cancel out distortion in the generator by adjustment of the quadrature coil.
This Is because centering the quadrature coil at other than
the point of inflection on the S-curve introduces 2nd harmonic distortion which can cancel 2nd harmonic distortion
in the generator. Thus low THO numbers may have been
obtained wrongly. Large AFT offsets asymmetrical off tuning
characteristic, and less than minimum THO will be observed
if alignment of the quadrature coil is done with a high distortion RF generator.

ca.

0.6)
t = -(24k)(2.2 p.F) in ( 0.8
which yields t = 15 ms. It should be noted that the 0.6V
threshold at pin 12 has a high temperature dependence and
can move as much as 100 mV in either direction.

Care must also be taken in choosing ceramic filters for the
LM1865. It is important to use filters with good group delay
characteristles and wide enough bandwidth to pass enough
FM sidebands to achieve low distortiol:

4-151

Application Notes (Continued)
The LMl865 has been carefully designed to insure low AFT
offset current at the point of minimum THD. AFT offset current will cause a non;symmetric deviation mute/stop window about the point of minimum THO. No extemal AFT offset adjustment should be necessary with the LMl865. The
amount of resistance in series with the 18 poH quadrature
coil drive inductor, L1, has a significant effect on the minimum THO. This series resistance is contributed not only by
R13 but also by the 0 of L1. The 0 of L1 should be as high
as possible (Ie: 0:>50) in order to avoid production problems with the 0 variation 'of Ll; Once R13 has been optimized for minimum THO, 'adjustment ona radio' by radio
basis should be un-necessary.
'

With the LM1865 system, a low AGC threshold is achieved
whenever there are strong out-of-band signals that might
generate"an interfering 1M3 product, and a high AGC threshold is achieved if there are no strong out-of-band signals.
The high AGC threshold allows ,the receiver. to obtain its
best signal-to-noise ,performance when there Is no possibility of an 1M3 product. The low AGC threshold allows for
weaker desired stations to be received without gain-reducIng the tuner. It should be noted that when the AGC threshold is set low, there will be a signal-to,noise compromise,
but is assumed that it is more desirable to listen to a slightly
noisy station than to listen to an undesired 1M3 product. The
simplified circuit diagram (FlfJUre 5) of the AGCsystem
shows how the dual AGC thresholds are achieved.
Vm = 'W corresponds to a fixed in-band sillnallevel (defined as VNB) at the tuner output. VNB will be referred to as
the "narrow band threshold". VWB also corresponds to a
fixed tuner outPut which can either be an in-band or out-ofband signal. This fixed tuner output will be called the "wide
band threshold". Always VWB > VNB. R11 and C13 define
the AGC time constant. A reverse AGC system is 'shown.
This means that VAGe decreases to gain-reduce the tuner.
The LM1865 AGC output is an operi~ollector cuirent
source cap,able of sinking at least 1 mAo

DUAL THRESHOLD AGe
(AUTOMATIC LOCAL/DISTANCE SWITCH)
There is a well recognized need in the field for gain reducing
(AGGing) the front end (tuner) of an FM receiver. This gain
reduction is important in preventing 'OVerload of the frant
end which might ocCur for large signal inputs. Overloading
the front end with two out-of-band signals,' one channel
spacing' apart and one channel spacing from center frequency, or, two channel spacings apart and two channel
spacings from center frequency, will produce a third order
intermodulation product (1M3) which falls inband. This 1M3
product can completely block out a weaker desired station.
The AGC in thfi LM1865 has been specially designed to
deal with the problem of 1M3.
ANTEIINA

SELECnVlTY

•••
PIN a
METER OUTPUT

VMlC •
PlN1

1V

~()&H_C/.O_O:r_E_':z_ _ _ _ _ _ _ _ _ _ _~~~

;J;C13

liMe
TLlHI7509-9

FIGURE 5. Dual Threshold AGe
I, = GM, Vm only HVm > 1V
otherwise I,

=0

Gm,. Vwa = constants
iAGe = Gm2 Vo where G~ = 1,/26 mVand
Vo > VWB otherwise iAGC = 0

4-152

Application Notes (Continued)
First examine what happens with a single in-band signal as
we vary the strength of this signal. FIfJUf6S 6 and 7 illustrate
what happens at the tuner and AGe outputs.

In Figure 7 there is no AGe output until the tuner output
equals the wide band threshold. At this point both SW2 and
SW1 are closed and the AGe holds the tuner output in Figure 6 relatively constant.
Another simple case to examine is that of the single out-ofband signal. Here there is no AGe output even if the signal
exceeds "wB. There is no output because the ceramic filters prevent the out-of-band signal from getting to the input
of the IF. With no signal at the IF input there is no meter
output and SW1 is open, which means No AGe.
FIfJIIf8S 8 and 9 illustrate what happens at tha tuner and
AGe outputs when the strength of an in-band signal is varied in the presence of a strong out-of-band signal (i.e.,
greater than VWB) which is held constant at the tuner input.
For this example, the in-band signal at the tuner output will
be referred to as Vo (desired signal), and the out-of-band
signal as VUD (undesired signal).
In F/{/ure 9, we see that there is no AGe output until the
tuner output exceeds the narrow band threshold, VNB. At
this point Vm > 1V and SW1 closes. Further increase of the
desired signal at the tuner input results in an AGe current
that tries to hold the desired signal at the tuner output constant. This gain reduction of the tuner forces the undesired
signal at the tuner output to fall. At the point that VUD reaches the wide band threshold, no further gain reduction can
occur as Vo would fall below VWB (refer to Figure 5). At this
point, control of the AGe shifts from the meter output
(narrow band loop) to the out-of-band signal (wide band
loop). Here VUD is held constant along with the AGe

TUNER OUTPUT
SLOPE IS INVERSELY PROPORTIONAL
TO LOOP GAIN OF WIDE BAND AGC CIRCUIT

L------r.~------------------VW

FIGURE 6
REVERSE AGC OUTPUT

V+~----""""

~----~~------------~~---Vw
TL/HI7509-10

FIGURE 7

TUNER OUTPUT

------,
...................

va REACHES VWI

,------'n---\-....,

" ....

VIti

IN·8AHO SIGNAL
(Vo)

,
"

OUT·OF BAND SIGNAL
(Vuo)

L-----~~--~~----_r~----------V6
Viii
, ¥wi
(TUNER INPUT)
I
I

:

FIGURE 8

I

REVERSE AlIt: OUTPUT
y+~---.....

II
L-____________

~

______

~

______

~

___

VD

(TUNER INPUT)
Prime Indicates referenced to tuner input

FIGURE 9

4-153

TLlHI7509-11

i.::::&
.....

Application Notes (Continued)
voltage, while Vo is allowed to increase. Vo will increase
until 'it reaehes the ,level of the wide band threshold at the
runer,oIJtput When this occurs Vuo is no longer needed to
keep Vo > VWB as Vo takes over the job. Thus Vuo will
drop ,as the amount qf AGe increases, whUe Vo is held constant by the AGe.'""
When compared to the'simple case of a single in-band signal, we see that because of the presence of a strong out-ofband signal, AGe action has occurred earlier. For the simple
case, AGe started when Vo ~ VWB. For the two signal case
above, AGe started w~en Vo ~ VNB. Thus, the LM1865
achieves an early AGe when. there are strong adjaeent
channels that might cause 1M3, and a later AGe when these
signals aren't present.
For the range of signal levels that the tuner was gain-reducad and Vo < VWB thera was loss in signal-to-noise in
the recovered audio as compared to the case where there
was no gain reduction in this interval. Note. however, that
the tuner is not desensitized by the AGe to weak desired
ststions belo~ the nsnow bend threshold.

,

.'

NARROW BAND AGC THRESHOLD ADJUSTMENT'
Both the narrow. band and wide band.AGe thresholds are
user adjustable. This allows the user to optimize the AGe
response to a given tuner. Referring to Figure 5, when the
meter output exceeds 1V a comparator closes SW1. A simplified cirelli! diagram of this comparator is shown in Figure
10."

,

The 1K resistor in' series with pin 8 allows for an upward
adjustment of the narrow band threshold. This is accomplished by extemally loading pin 8 with a resistor. Figure 11
illustrates how this adjustment takes place.
From F/{/ure 11 it is apparent that loading the meter output
not only moves the narrow band threshold, but also decreases the meter output for a given input.
In general one chooses the narrow band threshold
based on what signal-to-noise compromise is considered
acceptable.

.............W l r - _ - - - - o :~~R OUTPUT

HIGH - SW1 CLOSED
LOW -SW1 OPEII
TlIHI7509-12

FIGURE 10_ Narrow Band Threshold Circuit

4

---------------------

METERLOAO=33k

L-~:::..-4==;-----J......Vo TUNER
TL/HI7509-13

FIGURE 11. Affect of Meter Load on Narrow Band Threshold

4-154

Application Notes (Continued)
VUD2 = out-of-band signal 800'kHz from center frequency and 400 kHz away from VUD1, applied to tuner input.

WIDE BAND AGe THRESHOLD ADJUSTMENT
There are a number of criteria that determine where the
wide band threshold should be set. If the threshold is set too
high, protection against 1M3 will be lost. If the threshold is
set too low, the front end, under certain input conditions,
may be needlessly gain-reduced, sacrificing signal-to-noise
performance. Ideally, the wide band threshold should be set
to a level that will insure AGe operation whenever there are
out-of-band signals strong enough to generate an 1M3 product of sufficient magnitude to' exceed the narrow band
threshold; Ideally, this level should be' high enough to allow
for a single in-band desired station to AGe the tuner, only
after the maximum signal-to-noise has been achieved.

In general, due to tuned circuits within the tuner, the tuner
gain is not constant with frequency. Thus, if the tuner is kept
fixed at one frequency while the input frequency is changed,
the output level will not remain constant. Figure 12 illustrates this.
It can be shown that for a given IMa, the combination of
VUDl and VUD2 that produces the smallest rms sum at the
tuner output is given by the equations:
VUD1 = 1.12

In order to insure that the wide band loop is activated whenever the 1M3 exceeds the narrow band threshold, VNB, determine the minimum signal levels for two out-of-band signals necessary to produce an 1M3 equal to VNB. Then, arrange for the wide band loop to be activated whenever the
tuner output exceeds the rms sum of these signals. There
are many combinations of two out-of-band Signals that will
produce an 1M3 of a given level. However, there is only one
combination whose rms sum is a minimum at the tuner output. 1M3 at the tuner output is given according to the
equation:
1M3 = aVUD1 2 VUD2 (assuming no gain reduction) (1)

(A2
IMa)Ya
A1 a

(2)

VUD2 = 0.794(A1 2 IMa)Ya

A22

(3)

a

Therefore, in order to guarantee that the AGe will be keyed
for an IMa = VNB we need only satiSfy the condition:

V 2 + [(A1)(112)

VWB:<:'

NB

.

(~VNB)V.]2
+
Al a

[A2 (0 794) (A12VNB)
.
A22 a

Y3]2 (4)

where a = constant dependent on the tuner;
The right hand term of equation (4) defines an upper limit for
VWB called VWBUL. VWBUL is the rms sum of all the signals
at the tuner output for two out-of-band Signals, VUDI and
VUD2 [as expressed in equations (2) and (3)1, applied to the
tuner input.

VUDl = out-of-band signal 400 kHz from center frequency, applied to tuner input;

TUNER GAIN

A

I

I
___ ..1I __ _

A2

:

I
I
I

I

------------...J.--.. . .--.. . .
I

fa

fa+
400 kHz

- - - - - - T U N E R INPUT FREQUENCY
fo+
800 kHz

TL/H17509-14

Define A = rune, gain at center frequency

Al
A2

= rune, gain at f 0 + 400 kHz
= rune, gain at f 0 + 800 kHz
FIGURE 12

•
4-155

•

~r-------------------------------------------------------------------~

:5

Application Notes (Continued)
In order to make the calculation. in equation (4), the constants a, A 1, A2 must first be determined. Th.is is done by
the following procedure:
1. Connect together two RF generators and apply them to
the tuner input. Sinoe the generators will terminate each
. other, remove the 500 termination at· the tuner input.
2. Connect a spectrum analyzer to the tuner output. Most
spectrum analyzers have 500 input impedances. To
make sure that this impedance does not load the tuner
output use a FET probe connected to the spectrum analyzer. The tuner output should be terminated with a ceramic filter.
S. Disconnect the AGC line to the tuner. Make sure that the
.
tuner is not gain-reduced.

If the wide band threshold was set to VWBUL, then whlln a
single in-band station reached the level VWBUL at the tuner
output, AGC action would start to take place. For .thiS reason it is hoped thafVWBUL is above the level that will allow
for maximum signal-to-noise. If, however, this· is not the
case, eonsidElration might be given to improving .the .intermodulation performance of the tuner.
. .
The lower limit for VWB is the minimum tuner output that
achieves the best ppssible signal-to-noise ratio in the recovered audio. In general, it is desirable to set VWB cloSer to
the upper limit rather than the lower limit. This is done to
prevent AGC action within the narrow band loop except
when there is a possibility of an 1M3 greater than VNB.
The wide band threshold at the pin 2.0 input to the LM1865
is fixed at 12 mVrms. Generally speaking, if pin 20 were
driven directly from the tuner output. VWB would be too low:
Therefore, in general, pin 20 is not connected directly to the
tuner output. Instead the tuner output is attenuated and then
applied to pin 20. Increasing attenuation incrllases the wide
band threshold, VWB.
Pin 20 has an input.impedanoe at 10.7 MHz that can be
modeled as a 5000 resistor in series with a 19 pF capaCitor,
giving a total impedance of 9400 L - 58". Thus an easy way
to attenuate the input to pin 20 is with the arrangement
shown in Figure 14.
Notice that pin 20 must be AC coupled to the tuner output
and that C1 is a bypass capacitor. R1 adjusts the amount of
attenuation to pin 20. The wide band threshold will roughly
increase by a factor of (R1 + 9400)/9400.

4. Adjust the two RF generators for about 1 mV input and to
frequencies 400 kHz and 800 kHz away from center fre-

quency (Figure 13).

.

5. Note the three output levels in volts.
.
6. Knowing the tuner input levels for V UD1 and VUD2 and
the resulting 1M3 just measured, "a" is calculated from
the formula:
a=

1M3
VUD1 2VUD2

(5)

where all levels are in volts rms. A typical value for "a"
might be 2 x 1()6.
7. A1 and A2 are calculated according to the following formulas
A1 =

V1
VINI
fo

A2=

+ 400kHz
V2

VINI
fo

AGe CIRCUIT USED AS A CONVENTIONAL AGC
If for some reason the dual AGC thresholds are not desired,
it is easy to use the LM1865 as a more conventional
LMS189 type of AGC. This is accomplished by AC coupling
the pin 20 input after the ceramic filters rather than before
the filters. Thus, as with the LMS189, only in-band signals
will be able to activate the AGC.

(6)

(7)

+ 800kHz

3300 OUTPUT

VI

IM~CE

.....

r---1~~~_
TUNER

~

~C~ER!!!AM~1C ALTER

er

"------' E:.

/b /0+.1dI.z /0+l1li kHz

-L.

TUHI7509-16

10=10.7 MHz

FIGURE 14. Wide Band Threshold Adjustment

TUHI7509-1S

FIGURE 13. Spectrum Analyzer Display of Tuner Output

4-156

Simplified Diagram

II

.s~

•

•"

.--+--+--~k
,-Hf---+-...j..l....~

,

.E .

.. -.i

~

E
~

i

i
4-157

~E

iii"

~

.

il

I

~=

"I

i

.~

tflNational Semiconductor

LM1868 AM/FMRadio System
General Description

Features·

The combination of the LMt.868 and an FM tuner will provide all the necessary functions for a 0.5 watt AM/FM radio.
Included in the LM 1868 are the audio power amplifier, FM
IF and detector, and the AM converter, IF, and detector.
The device is suitable for both line operated and 9V battery
applications.

• DC selection of AM/FM mode
• Regulated supply
• Audio amplifier bandwidth decreased in AM mode,
reducing amplifier noise in the AM band
• AM converter AGC for excellent overload
characteristics
• Low current internal AM detector for low tweet radiation

Block Diagram

61

12.

LMI88B

,,Ir=~----~====~==~~
I

L_

iL_Jl!1
~w

+ Cll

If~

Vs

I"
~

I

-+-_........__~__ ~ .J
TL/HI7909-1

Order Number I-M1868N
See NS Package Number N20A
Nota: See table for'coil data

4-158

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrlbutora for availability and specifications.
Supply Voltage (Pin 19)
15V
Package Dissipation
2.0W
Above TA = 25°C, Derate Based on
TJ(MAX) = 1500C and (JJA = 600C/W

Electrical Characteristics Test Circuit, TA =

I

Parameter

Storage Temperature Range

- 55°C to + 1500C

Operating Temperature Range
Lead Temperature (Soldering, 10 sec.)

OOCto +700C
2600C

25°C, Vs = 9V, RL = 80 (unless otherwise noted)

I

Conditions

I

Min

Typ

I

Max

I

Units

STATIC CHARACTERISTICS eAM = 0, eFM = 0
Supply Current

AM Mode, S1 in Position 1

Regulator Output Voltage (Pin 16)

3.5

Operating Voltage Range

4.5

22

30

mA

3.9

4.8

V

15

DYNAMIC CHARACTERISTICS-AM MODE
fAM = 1 MHz, fmod = 1 kHz, 300/0 Modulation, S1 in Position 1, Po = 50 mW unless noted
Maximum Sensitivity

Measure eAM for Po = 50 mW,
Maximum Volume

Signal-to-Noise

eAM=10mV

40

50

Detector Output

eAM = 1 mV
Measure at Top of Volume Control

40

60

85

mV

Overload Distortion

eAM = 50 mY, 800/0 Modulation

2

10

0/0

Total Harmonic Distortion (THO)

eAM = 10mV

1.1

2

0/0

8

p.V

16

dB

DYNAMICCHARACTERISTICs-FM MODEfFM = 10.7 MHz, fmod = 400 Hz, af = ±75 kHz, Po = 50mW, S1 in Position 1
- 3 dB Limiting Sensitivity

15

Signal-to-Noise Ratio

eFM=10mV

50

64

Detector Output

eFM = 10 mV, at = ±22.5 kHz
Measure at Top of Volume Control

40

60

AM Rejection

eFM = 10 mV, 300/0 AM Modulation

40

Total Harmonic Distortion (THO)

eFM = 10mV

45

p.V
dB

85

mV

50

dB

1.1

0/0

2

DYNAMIC CHARACTERISTICS-AUDIO AMPLIFIER ONLY t = 1 kHz, eAM = 0, eFM = 0, S1 in Position 2
THO = 100/0, RL 80
Vs = 6V
Vs = 9V

Power Output

250
500

325
700

mW
mW
kHz
kHz

Bandwidth

AM Mode, Po = 50 mW
FM Mode, Po = 50 mW

11
22

Total Harmonic Distortion (THD)

Po = 50 mW, FM Mode

0.2

0/0

41

dB

Voltage Gain

Typical Performance Characteristics (Test Circuit) All curves are measured at audio output
Quiescent Supply Current
vsVoltage

A~MbD

2.

"

~

I I

i

.J.-I-

S

FMIIDDE

"
12

FM Limiting Characteristics

I

11.1

~-3'Rr-...

u

•

10

12

SUPPLY VDLTAGE CV)

,.

0.32

\

I - I--- ••1

is
:: -71

"

U

1\

::-80
8

THD+N

1

10

100

,.

10'

IF INPUTVDLTAIIE lIN)

4-159

lUll

~

FM IF AM Rejection
S+N

D

l-1•

f .. -411 Hz

-41

."

Ii

E

_1111f-!I'·llHHz

~-&I

•

S+N

i -211/
:5

8
0

.

10

Ii

30

-20

if

3-41

5

I!:-&O

II

/

! -3D '/

-

10-..

"' "

AMR+/I

4j-UIikHz

I

.... 400 Hz
:" -II 31%"r MDD~LATID'
is

~

-1' 1 ,.

110

,.

I.

'''IPUT VDL TABE c,Nl

I ••

TL/HI7909-2

Typical Performance Characteristics

(Continued)

All curves are measured at audio output (Test CircujQ··

iii

..
f
.

II

MI

~

II:

II

..•
~

_II
'0.0

!l:....tO

o

i-31

.
~J.
~: ~U""""'_I
I
....
I ,
'III

It

,.

'1liiie

ftF UlPUTVOLTAGE flNl

!

1.1

~

0

III

MODULAno.

·11

!!l
0

3.2
TH

0

•
i

1.1

~

£

l

a

~~
;-1

I.Z

_

1.1

'·lklll

M·W...III

a," mV

Power Dissipation V8 Power
Out,RL = 160

I

I I I
I I I
I I I

I I
L

T

~';"nlo

I

!. • ~
,

~ H

=

~
It

I ...

I ....

11M.

'M

FREQUE.CY.1lbI

.Dlatertlon V8 Frequency
Amplifier Only

5 Audio

PgUT~II'"
RL ·en

vs"zv

~

I~""

T''''''

POU
ftL' en

II

'.,7 Mill

"'Z'4.11
IIJIIPLYVOLTAIElVI

I

Gain V8 Freqliency AUdio
Amplifier Only
'. . "

.... II.V!L-

AM MOO

,= Iklll

~.,ZV

""

'.-_111

",. I MHz

-7

'M

FMMODE

... ·IkHz

4

ao

=

J I
I I

AM MODE .

!$I-I

c

AM

-I

Power Dlaalpatlon V8 Power

Output, RL

F.

!-z ~r
~

..

3Recovered Audio va SUpply
I I
I

AM Characterlatlc8

:IlITH

VS'IV

;.oJ:..

/

''''THO
~

~:;:IV

••

AM/

I I I
IJ I

VS:"'IV

u

iJ

...

I.Z

1.1

U

/

..-'[/FM

1.20.41.11.11.11.2

OUTPUT POWER till

OUTPUT POWER !WI
TLlH/7909-3

Test Circuit

=~.
~-.---t--~~--~----------~-~--~'--------'~'
'I
17

..
,.

,

'1"1.111&"
-

I

''';

14

':'

"+~~ I

. 00"

15

13

Ir---'
II
II

.JI

1."'-........._ .....
L~_

FM

Note: See table for coil data

TL/H/7909-4

4-160

~

5.6pf

"~
""2&
0-

...

m ..

::~ ~"'"
'C
13"

:i'~'
::
43"

~

'="

Vs

en

CIS

....'~:n" ...,.. '.1.'

:::I

~
"

CIC

!

~

L5

'='

(

I
I

*

I

'="

DO

(1

••

.... ,.

I

. '......,...vs
Z2t

T .~.,

..v.

I ______ LI ___________
~

FM Perlormance (88 MHz-l08 11Hz)

AM Pertormanca (525 kHz-l650 kHz)

.30 dB quleling senslttvlty: 3.5 p.V

• Maximum sensitivity: 100 p.Vlm

• -3 dB IlmMlng sensitivity: 7 p.V

.20 dB quieting sensltlvfty: 250 p.Vlm
• Tweet*

~1
I

:
I
II

~

L

'='

CIA-

~'"1.1.'

~

L_

..

•e

R'
t ..

'='

worst case: 5%

rip,
CII

100 mVlm: 1.5%

'Tweet is an audio lone produced by the 2nd and 3rd harmonic of the IF
beating against the received signal. II is m.......ed as an equivalent modu·
lation leval: i.e., a 30% tweet has the same amplRude al the detector as a
desired signal with 30% modulation.

'='

v.

-=

'='

L _-'
TLIHI7909-5

II

898U..'
--~---~---.

-

--~---

-----

PC Board Layout

TL1H17909-6

Component Side

Typical Performance Characteristics Typical Application
All curves are measured at audio output
10

e

...."
.....
...

/

:il -10

co

-20

~

-30

:::>

~ -40

:::>
CI
CI

..
is
:::>

5ii
"-'
a:

S+N

~

-50
-60
-10

r<

S+N

~.

LV

e
:il -10

V

ill" -20

FMMOOE

\

10

'"
iii

...
......

~

\

:::>

1.-98MHZ,'~

61= ±15kHz
1m' 400 Hz

10

-30
-40

:::>

C>

~

100

CI

.

ili

:::>

lk

10k

lOOk

RF INPUT VOLTAGE (PVI

-5G

/

V
AM MODE

~ '"- r-..
'm -I kHz
I. -I MHz

,

N

r-

30" MODULATION
0.1

10

100

lk

RF FIELD STRENGTH (mV/ml
TL/H/7909-7

TLlHI7909-B

4-162

r-

a::
....
C»

IC External Components (Application Circuit)
Component

Typical

Comments

Value

Component

Typical

C1

100pF

Removes tuner LO from IF input

R9

240k

C2

0.1 p.F
0.01 p.F

Antenna coupling capacitor
FM IF decoupling capacitors

C19

1 p.F

C4,C5
C6,C9
R5

0.005 p.F } AM smoothing/FM de-emphasis
1k
network, de-emphasis pole is
given by.

Comments

Value

C7

10 p.F

C8

0.1 p.F

C20

0.1 p.F

R10

50

C21
R1

250 p.F
8k2

}

271" (C6

+ C9)

(:4\

~~)

C10

10 p.F

C11

0.1 p.F

Regulator decoupling capacitor

C12

10p.F

AC coupling to volume control

IF coupling

}

Regulator decoupling capacitor

C13

0.1 p.F

C14

50 p.F

Power supply decoupling

C15

0.1 p.F

Audio amplifier input coupling

R7
C16
C17

3k
} Roll off signals from detector in
0.001 p.F the AM band to prevent radiation
100 p.F
Power amplifier feedback
decoupling, sets low frequency
supply rejection

R8

16k

Power supply decoupling

Set AGC time constant
IF coupling

1
f1 '"

CD
C»

High frequency load for audio
amplifier, required to stabilize
audio amplifier
Output coupling capacitor
Sets Q of quadrature coil,
determining FM THO and
recovered audio

R2

12k

IF amplifier bias R

R3

5k6

Sets gain of AM IF and Q of AM
IF output tank

R4

10k

Detector load resistor

R6

50k

Volume control

C18

0.02 p.F

Power supply decoupling

R11, R12

1500

Terminates the ceramic filter,
biases FM IF input stage

01

1N4148

Optional. Quickens the AGC
response during tum on

AM detector bias resistor

Coil and Tuning Capacitor Specifications
Cl

AM ANT140 pF max 5.0 pF min
AM OSC 82 pF max 5.0 pF min
Trimmers 5 pF

Ll

640"H,Qu~200

Rp ~ 3k5@ F ~ 796kHz
(At secondary)

T1

FM 20 pF max 4.5 pF min
TOKO CY2-22124PT

Qu> 70@ 10.7 MHz,L to
resonetew/82pF@10.7MHz
TOKO KAC-K2318 or equivalent

AM antenna
1 mVlmeter induces
, approximately 100 "V
open circuit at the secondary

LO, l2 380 "H, QU > 80 @ F ~ 796 kHz

TOKO RWO-6A5105 or
equivalent

TUHI7809-10
T2

Qu> 14@455kHz,Lto
resonate w/180 pF @455 kHz
TOKO 159GC-A3785 or
equivalent

TokoAmerica
1250 Feehanville Drive
Mount Prospect, IL80056
(312) 297-0070

TUHI7909-9
L4
L5

SWG #20, N ~ 3Y,T, inner
diameter ~ 5 mm

TLlH17909-11
CFl

SWG #20, N = 3Y,T, inner
diameter = 5 mm

La

L = 0.44"H, N ~ 4Y,T,Qu ~ 70

L7

SWG # 20, N = 2 Y,T, inner
diameter = 5 mm

CF2

10.7 MHz ceramic filter
MURATA SFE 10.7 mA or
equivelent

TOKO CFU-090D or equivalent
BW > 4.8 kHz @455 kHz

TL/H/7909-12

Murata

2200 lake Park Drive

T3

Smyrna, GA 30080
(404) 436-1300

:Fr\
51:IJlrrc
TLlH17909-13

4-163

Apollo Electronics NS-l07C
or equivelent

•

Layout Considerations

Circuit Description (See Equivillent SCheniatiC)

AM SECTION

AMSECTI~N

Most problems in an AM radio design are associated with
radiation of undesired signals to the loopstick. Depending
on the source, this radiation can cause a variety of problems
including tweet, poor signal-tOonoise, and low frequency oscillation (motor boatin9)~ Although the level 'Of radiation from
the LM1868 is low, the overall radiO 'performance can be
degraded by improper PCB layout. Usted below are layout
considerations association with common problems.

The AM section consists of a mixer stage, a SEiparate lOcal
oscillator, an IF gain, block, an envelope detector, AGC circuits for controlling th,e IF and mixer gains, and a switching
circuit which ~isables the AM section in the FM mode.
"
Signals from ~he antenna are AC-couplt;ldinto pin 7, the
mixer input. This stage consists of a common-emitter amplifier driVing a differential amp which is switched by the local
oscillator. With no mixer AGC;' the current in the mixer is
330 pA; as the AGC is applied, the mixer current drops,
decreasing the gain, and also the input impedance drops,
reducing the signal at the input. The differential amp connected to pin 8 forms the local oscillator. Bias resistors are
arranged to"present a riegative impedance at pin 8. The
frequency of oscillation is determined by the tank Circuit, the
peak-to-peak amplitude is approximately 300 p.A times the
impedance at pin 8 in parallel with 8k2.

1. Tweet: Locate the loopstick as far as possible from deeg, R4, and R5. Orient C6, C9, R4;
tector components,
and R5 parallel to the axis of the loopstick. Return R8, C6,
C9, and C19 to separate ground run (see Typical Application PCB). '

ca,

a

2. Poor Slgnal-to-Nolse/Low Frequency Oscillation:
Twist speaker leads. Orient R,HI and C20 parellel to the axis
of the loopstick. Locate C11 away from the loopstick.

\
\

,

,\

\ 6

~I

1

,

~

1
1

1

1

1

1%

LoomlCK

1

After passing through the ceramic filter, the IF signals are
applied to the IF input. Signals at pin 11 are amplified by two
AGC controlled common-emitter stages and then applied to
the PNP output stage connected to pin 13. Biasing is arranged so thilt the current in the first two stages is set by
the difference between a 250 pA current source and the
Darlington device connected to pin 12.

/

When the AGC threshold is exceeded, the Darlington device
turns ON, steering current away from the IF into ground;
reducing the IF gain. Current in the IF is monitored by the
mixer AGC circuit.' When the current in thalF has dropped
to 30 pA, corresponding to 30 dB gain reduction in the IF,
the mixer AGC line begins to draw currt;lnt. This causes the
mixer current and input impedance to drop, as previously
described.

\
\
\
\

\

I

~

'-......,/
/
TUHI7909-14

In general, radiation results from current flowing.in a loop. In
case 1 this current loop results from decoupling detector
harmonics at pin 17; while in casa 2, the current loop results
from decoupling noise at the output of the audio amplifier
and the output of the regulator. The level of radiation picked
up by the loopstick is approximately proportional to: 1) 1/r3;
wherer is the distance from the center of the loopstick to
the center of the current loop; 2) SIN 6, where 6 is the angle
between the plane of the current loop and the axis of the
loopstick; 3) I, the current flowing in the loop; and 4) A, the
cross-sectional area of the current loop.

The IF output is level shifted and then peak detected at
detector cap C1. By loading C1 with only the base current of
the following d~e, detector currents are kept low. Drive
from the AGC is taken at pin 14, while the AM detector
output is summed with the FM detector output at pin 17.
FMSECTION
The FM section is composed of a 6-stage limiting IF driving
a quadrature detector. The IF stages are identical with the
exceptions of the input stage, which is run at higher current
to reduce noise, and the last stage, which is switched OFF
in the AM mode. The quadrature detector collectors drive a
level shift arrangement which allows the detector output
load to be connected to the regulated supply.

Pickup is kept low by short leads (low A), proper orientation
(6 ... 0 so SIN 6 ... 0), maximizing distance from sources to
loopstick, and keeping current levels low.
FMSECTION
The pinout of the LM1868 has been chosen to minimize
layout problems, however some care in layout is required to
insure stability. The input source ground should return to C4
ground. Capacitors C13 and C18 form the return path for
signal currents flowing in the quadratureeoil. They should
connect directly to the proper pins with short PC traces (see
Typical Application PCB). The quadrature coil and input circuitry should be separated from each other as far as possible.

AUDIO AMPLIFIER
The audio amplifier has an internally set voltage gain of 120.
The bandwidth of the audio amplifier is reduced in the AM
mode so as to'reduce' the output noise falling in the AM
band. The bandwidth reduction is accomplished by reducing
the current in 'the input stage.
REGULATOR
A series pass regulator provides biasing for the AM and FM
sections. Use of a PNP pass device allows the supply to
drop to within a few hundred millivolts of the regulator output and still be In regulation.

AUDIO AMPLIFIER
The standard layout considerations for audio amplifiers apply to the LM1868, that is: positive and negative inputs
should be returned to the same ground point, and leads to
the high frequency load should be kept short. In the case of
the LM1868 this means returning the volume control ground
(R6) to the same ground point as C17, and keeping the
leads to C20 and R10 short.
4-164

riii:

....co

Equivalent Schematic

en
co

HI.
8~

~i

~
~

g

-1:11•

I

5
9

e
~I'

I.

"
"

I'

~

!

4-165

~

II

~

r----------------------------------------------------------------------------,
dNational Semiconductor

;;;V"
II

~ LM 1893/LM2893 Carrier-Current Transceivert
General Description
Carrier-current systems use the power mains to transfer information between remote locations. This bipolar carriercurrent chip performs as a power line interface for half-duplex (bi-directional) communication of serial bit streams of
virtually any coding. in transmission, a sinusoidal carrier is
FSK modulated and impressed on most any power line via a
rugged on-Chip driver. In reception, a PLL-based demodulator and impulse noise filter combine to give maximum range.
A complete system may consist of the LM1893, a CC>PSTM
controller, and discrete components.

Features
•
•
•
•
•

Noise resistant FSK modulation
User-selected impulse noise filtering
Up to 4.8 kBaud data transmission rate
Strings of O's or l's in data allowed
Sinusoidal line drive for low RFI

•
•
•
•
•

Output power easily boosted 10-fold
50 to 300 kHz carrier frequency choice
TIL and MaS compatible digital levels
Regulated voltage to power logic
Drives all conventional power lines

Applications
•
•
•
•
•
•
•
•

Energy management systems
Home convenience control
Inter-offlCe communication
Appliance control
Fire alarm systems
Security systems
Telemetry
Computer terminal interface

Typical Application

CONTROLLER

TX/III
SEUCT

18

17

v+
1211
11

5.6V

12

Uk
47ft
TL/H/8750-1

FIGURE 1. Block diagram of carrler-eurrent chip with a complement of discrete components making a complete
Fo= 125 kHz, fDATA =360 Baud transceiver. Use caution with this clrcult-clangerousllne voltage Is pre. .nt.
tCarrier-Current Transceivers are also called Power Una Can1ar (PLC) tranaceMn.

4-166

Absolute Maximum Ratings
If Military/Aerospace specified devices

are

required,
please contact Ihe National Semiconductor Sales
Office/Distributors for availability and speC/ficatlons.
Supply voltage
Voltage on pin 12
Voltage on pin 10 (Note 1)
Voltage on pins 5 and 17
5.6 V DC zener current
Junction temperature: transmit mode
receive mode
Electro-Static Discharge (120 pF, 15000)

Maximum continuous dissipation, T A = 25°C,
plastic DIP N (Note 2): transmit mode
1.66W
1.33W
receive mode
-40 to 85°C
Operating ambient temp. range
-65 to 1500C
Storage temperature range
Lead temp., soldering, 7 seconds
2600C

30V
55V
41 V
40V
100mA
1500C
125°C
lKV

Note: Absolute maximum ratings indicate limits beyond

which damage to the device may occur. Electrical specifics·
tions are not ensured when operating the device above
guaranteed limits but below absolute maximum limits, but
there will be no device degradation.

General Electrical Characteristics
(Note 3). The test conditions are: V+ = 18V and Fo= 125 kHz, unless otherwise noted.
#
1

Parameter

Typical

Conditions

5.6 V Zener voltage, Vz

Pinll,lz=2mA

Test
Umlt
(Note 4)

5.6

Design
Umit
(Nots5)

Umlt
Units

5.2
5.9

V min.
V max.

2

5.6 V Zener resistance, Az

Pinll, Az=(Vz@10mA-Vz@1 mA)/(10 mA-l mAl

3

Carrier 1/0 peak survivable
transient voltage, VOT

Pin 10, discharge 1 ,..F cep. charged to VOT
thru <10

60

60

V max.

4

Carrier 1/0 clamp voltage, Voc

Pin 10,loc=10 mA, AX mode
2N2222 diode pin B to 9

44

41
50

V min.
V max.

5

Carrier 1/0 cfamp resistance, A10

Pin 10, loc= 10 mA

20

6

TXIRX low input voltage, VIL

Pin 5

1.B

O.B

V max.

7

TX/RX high input voltage, VIH
TX/RX low input current, IlL

Pin 5 (Note 9)

2.2

2.8

V min.

B

Pin 5 atO.B V

-2

-20

9

TX/RX high input current, IIH

Pln5at40V
10-4

-1
10

,..A min.
,..A max.
,..A min.
,..A max.

5

0

0

1

0

10

AX - TX switch-over time, TRT

TIme to develop 63% of full current drive thru pin 10

10

,..s

11

TX - AX switCh·over time, TTR

1 btttime, Te=1/(2FoATAl. TImeTTRisuser
controlled wtth CM, see Apps. Info.

2

bit

12

ICO initial accuracy of Fo

TX mode, Ao = 6.65 kO, «0 = 560 pF
Fo = (F1 + F2)/2

13

ICO temperature coefficient of Fo

TX or AX mode, (FOMAX-FOMINl/(TJMAX-TJMINl

-100

14

Temperature drift of Fo

TX or AX mode, -40,;;TJ,;;TJMAX

±2;0

125

113
137

kHz min.
kHz max.
PPMfOC

±S.O

% max.

Transmitter Electrical Characteristics (Note 3). The test Conditions are: V+ = 16 V and Fo= 125 kHz
unless otherwise noted. The trsnsmit center frequency is Fo, FSK low is F1, and FSK high is F2.
#
15

16

17

Parameter
Supply voltage, V + , range

Totel supply current, lOT

' Carrier 110 output current, 10

Conditions
Meets test 17 spec. at TJ = 25"C and:
I(F1 [14V]-F1 [18V])/F1 [18V]1 <0.01
I(F1 [24V]- F1 [1 BV])/F1 [lBVII <0.01

Pin

Pin 15.
12 high. lOT is 10 t~rough
pin 15 and the average current looc of the
Carrier 110 through pin 10

TypIcal

Test
Umlt
(Note 4)

DesIgn
Umlt
(NoteS)

13
40

14
24

23

' 52

79

mAmax.

is

Umlt
Units
V min.
V max.

lOOn load on pin 10

70

45

mAppmin.

18

Carrier 110 lower swing limit, VALC

Pin 10. Set internally be ALC.
2N2222 diode pin B to 9

4.7

4.0
5.7

V min.
V max.

19

THO of 10 (Note 6)

Q of 10 tank driving 100 line

1000 load, no tank

0.6
5.5

(F2- F1)/([F2+ F11/2)

4.4

20

FSK deviation, F2 - F1.

5.0
9

% max.
% max.

3.7
5.2

"4> max.

% min.

21

Data In. low input voltage, VIL

Pin 17

1.7

0.8

V max.

22

Date In. high input voltage, VIH

Pin 17 (Note 9)

2.1

2.B

V min.

23

Date In. low input current, IlL

Pin 17 at O.B V

-1

-10
1

24

Date In. high input current, IIH

Pin 17 at 40 V

,..A min.
,..A max.
,..A min.
,..A max.

10-4

4·167

-1
10

0

II

Receiver Electrical Characteristics

(Note 3). The test conditions are: V+= 18 V, Fo= 125 kHz,±2.2%:
deviation FSK, FOATA =2.4 kHz, VIN= 100 mVpp, in the receive mode, unless otherwise noted.
".

Parameter

#

Conditions

TypIcal

Test
Um"
(Note 4)

Dellgn .
Lim"
(NOI85)

Units

13••
2.

V min.
Vrnax...

Um"

25

Supply voltage. V+ , range

Functional r8Cejve~ (Note 7)

12
37

13
30

26

Supply current, lOT

lOT is pin 15 (Y+) plus pin 10
(Carrier 1/0) current 2.4 kO Pin 13 toGNO.

11

5
14

mAmin.
mAmax.

27 .

CarTier 1/0 input resistance, RIO

Pin 10

19.5

·14
30

kOmin.
kO max.

10

4.8

2.4

kBaud

±10

% min.

;: :

26

Max. dats rats, FMD

Functional receiver (Note 7), CF = 100 pF,
RF = 00, no tank,
2.4 kHz=4.8 kBaud

29

PLL capture range, Fc

CF=l00pF,RF=OO

±4O

±15

30

PLL Ioc;k range, FL

CF= 100 pF, RF=O 0

±45

±15

31

Receiver Input sensitivity, SIN

For a functional receiver (Note 8)
Referred to chip side (pin 10)
of the line-coupling XFMR: Fo = 50 kHz
Fo=300kHz
Referred to line side of XFMR:
(assuming a 7.07:1 XFMR)' Fo= 50 kHz
Fo=300kHz

1.8
2.0
1.4
0.26
0.29
0.20

10

2

0.1

% min.
12

mVRMS
mVRMS
mVRMS
mVRMS
mVRMS
mVRMS

32

Tolerable input dc voltage offset
range, VINDC

Pin 10 lower than pin 15 by VINDC

33

Dats Out breakdown voltage

Pin 12, leakage I,;; 20 p.A

70

55

V min.

34

Oats Out low output, VOL

Pin 12, sat voltsge at IoL = 2 mA

0.15

0.4

V max.

35

Impulse noise filler current, II .

Pin 13 charge and discharge current

±55

±45
±85

p.Amln.
p.Amax.

36

;Offset hold cap. bias voltsge, VCM

Pin 6

'2.0

1.3
3.5

V min.
V max.

37

Offset hold capacitor max. drive
current, IMCM

Pin 6. V(pin 3) - V(pln 4) = ± 250 mV

±55

±25
±80

p.A min.
p.Amax.

38

Offset hold bias current, IOHB

Pin 6, TX mode. Bias pin 6 as It selfbiased during test 31.

-0·5

-20

39

Phase com~ior current, Ipc

Bias pins 3 and 4 at 8.5 V
Ipc=l(pin3) + l(pin4), TXmode

100

50
200

,.Amin.
p.Amax.

40

Phase detector output resistsnce,
RpD

Pins 3 and 4.
RpD = (y@100p.A-V@50,.A)/(50p.A)

10

6
18

kOmln.
kOmax.

41

Phase detector demodulated output
voltage, VPD

Pin 3 to 4, measured after filtering
out the 2Fo component

100

60
180

mVppmin.
mVppmax.

42

Fest offset cancel voltsge "window"
-to-VPD ratio, VWIVPD

VPIN3-VPIN4 = ±VWINDOW + DC offset
Drive for· ± 1 p.A pin 6 cUrrent

0.95

0.70
1.20

VlVmin.
ViVmax.

43

Power supply rejection, PSRR

CL = 0.1 ,.F. PSRR = CMRR.120Hz

,

.

80

V max.

-40
40

nAmin.
nAmax.

dBmlri.

Note 1: More accurately, the maximum voltage silowed on pin lOis Voo and Voc ranges from 41 to SOV. Also, transients may reach above SOV; see the transien1
peak vollage charscteris1ic curve.
Note 2: The maximum _
dissipation rating should be derated for device operation above 2SOC to Insure Ihat the Junction temperature ramslns below the
maximum reling. Use a 8JA of 75"CIW for the N package using a socket In still air (which Is the worst case). ConsuItlhe Application Informstion secUon for more
detsli.
Note 3: The b~ values apply owr the full junction temperature rangs for the specified supply voltage rangs. All other numbers apply at TA = TJ= 25"0, Pin .
numbers refer to LMI893. LM2893 tested by shorting CarrIer In to CarTier Out and leating H as I!" LMI893.
Note 4: Guaranteed and 100% production tested.
Note.5: Guaranteed (but not 100% producti9R tested) over \he temperature and supply voltage ranges. These limlla are not used .to. calculate outgoing quality
19V91s.
Note 8: Total harmonic diatortion is measured using THD= [lRMS (all components at or above 2Fol]/[IRMS (fundamental)].
Note 7: Receiver function is defined as the error-free passage of 1 cycle of 50% duty-cycle 2.4 kHz square-wave deta (2 sequential 2081'S bits), with the first bit .
being a "1." All of the data transitions (edges) must fall within ± 10% (± 20.8 "...) of their noise-free position~ RX time delay is minimized by using no impulse noise
fillar cap. C; for this test
Note 8: During the sensitivity check, nOte 7 requirements are followed with these exceptions: (I) data rate FDATA = 1.2 kHz, (2) all of the data transitions must fall
within ± 20% (± ~ 1.6 "s) of their noise-free positions, and (3), a time-domaln filter capjlCiIor (C~ is used. The time delay of CI is Yo bH, or 208 "s. (CI is
approximately 6200 pF).
Note 9: For TTL compatibility use a pull-up resiator to increase min. VOH to above 2.8 V.

4-168

Typical Performance Characteristics (V+ = 18V, Fo = 125 kHz, circuit of Figure 1, pin numbers for
LM1893)

Total Current Consumption,
lOT, vs Supply Voltage

Total Current Consumption,
loT. vs Junction Temperature

78

.
;!
I

a'"

~

.i

60

Chip Bias Current,
IQ, vs Supply Voltage

BO
lor-IPllnI + IPIII15

50

I
~
.i

30
RXMOIIE

10

1or-IPIII1O + IptlllS

..

50

TX MODE

;

:

~

6
4

l

RX MODE

10

o
10

20

30

40

Ia = IpII115
-2
-10

-50-30 0 30 50 90 no 150
TJ-JUNCTION TEMPERATURE 1°C)

50

TX':OOE

8

!II

40

Y+ -SUPPLY VOIDGE CVl

..

12

110

60

i

40

28

78

I

TXMODE-

14

01020304050

Y+ -SUPPLY VOIJMlE CVl

Output Stage DC Current,
Chip Bias Current, 10,
v8·Junction Tempurature

I
g

lii

I

~
~

Output Stage DC Current,
looc. vs Output Voltage

60

VPI. . s3IV:

II

50

YPIN15 - YPIInG

5 !i
15-

40 1-I-lXMODE

28

10

4!i;

31

loDe - IPlrna

30

~

~+=IJ:~~l+=~

Hf-tIl!:::oII''T--t-t ,:.... > 3IIV:

0 H~""'+-HVp'~ _ 3l1li
10

28

30

40

2.
1

II:
1

0 ~

I

I

10

R"'Hi!!!rkl~I::::t-t-t-IRXIMbo~
lX IIDIi"Ef'l"ilillli;;H

IODe,VS

Junction Temperature

I

I..
~

!
o tttl::ttjtttjt::l:jjt:tt\

50

-60 '-30 0

PIN 10 VOIJMlE CVl

6O~T'T-rr-rr"'T"l""l""lrT'"rn
50
IPltlO

PI'oH+++++-1aoc -

40

lXMODE

: t-+H-H-i-H-++-t+t-f"I

~ oI ~:RX~MOD~E~**~W
~~~~~~~~W

30 60 90 128 150

-50 -30 0

30 60 90 120 150

TJ -JUNCTION TEMPERATURE I 'C)

TJ-JUNCTION. TEMPERATURE 1°C)

Transient Voltage Survival
vs Pulse Time

I-t+t++f"kt-t+t-H-t-t

Transmitter AC Output Current
vs Junction Temperature

Transmitter Sinusoid THD
vs Junction Temperature

120 rT"T'TT"T""I""IrrTTT'TT"T'

1100

~r-H-+-t++++++t-H

80

1-t-t+f"1!ot-t-t-t-t++-H-I

I

1 0 _

I-+--N-+t-H-Il~WAD

~101-+++++-H-HI-f"Ioo.r-t+t

~

: H+-IH-f-t-t-lH-t+f-+-PI

s

Q 10

O~~~~~~~~

-50 -3~ 0 30 10 90 120 150
TJ-JUNCTION TEMPERATURE 1°C)

ALC Voltage vs
Junction Temperature

S
,.
I

~

c
I

=

1.02

I!>

~~~~~~~~~

1.00 H-IH-P.....d-f;-I-++iiH

~ 0.99 I+-F.-I-+:t±t:-£'lrnl-t-HII

~

2

~ 0.98

~

::

l00PPMI"C

.r~I!> 1.01 H~~I-++i;-I-++iiH

I

0.97

0
-10 -30 0

30 10 90 120 150
TJ-JUNCTION TEMPERATURE 1°C)

30 60 90 128 150
TJ-JUNCTION TEMPERATURE lOCI

ICO Frequency VB

&'
5

-10 -30 0

Transmitter FSK Deviation
vs Junction TemP,erature

Junction Temperature
1.03 """"""""""rT"T"T"T""rT"T"T"T"l

E

l~~~~~I~cc_~Cb~

H-+t-H-+-t-+t-T-H-HH

-60 -30 0 30 60

90 128 150

TJ-JUNCTION TEMPERATURE I"C)

r

Ti! tO1j,-'1"'t-+H++-I
0.1 ....................................................................

4.9 I-+-+++t-H-+-I-+-+++t-l
;Z 4.8' I-+-+++t-H-+-I-+-+++t-l
I!; 4.7 1-+-+++++-11-+-1-+-++++__

it 4.1 ~H-Wrl-iI-+-t-+++++fI

I

4.5 I-+-H-++.,..d-++-t+-t*i

ie

4.3 H+-II-+-t+++-+-I-+-H-H

~.

4.4 1-+-++++-H-+-N::IoIf+t-l

4.2

ttJtt±ttttl::ttttjj

- 60 -30 0 -30 60 90 128 150
TJ-JUNCTION TEMPERATURE I"C)
TL/H/6750-38

4-169

~

I

~~--------------------------------------------------------------------~

m
N

.......

Typical Performance Characteristics

,;

(Continued)

:E

i

-

:!i

~u~ctlon T~!"perature

32'-

16
14 _

&" 21
::II

i

Ii
'"'

i
•
;•
::II

24

12

211

10

16

8

12

,.

&

t 1lI'Io M10WED DUTY m:LE

2

"

8
4

PLL Lock Range vs
Junction Temperature and Fo

Receiver Sensitivity vs

Maximum Data Rate VB
Junction Temperature

NOt K

·~fSlttFT NO LOOP FILTER.tt

4

I

i
i
•
;
•
::II

3~~~~~~~~

99.7% OF SQ. WAV.E EDGES
WlIHIN 40%-60% DUTY C LE

I

50 kHz

II

125 kHz

1 300 kHz

MAK. 'DATA

...

.0

. 0
0
-60-30 0 ·30 60 90 1211 150
TJ -JUNCTION TEMPERATURE r·CI

~MPONENT VALUES.

Fa;= 125. . kHz 'DATA =·2.4kHz
Fa =. 50 ~Hz. .
'DATA 0; U kHz

~&O -30 0

30 60 90 1211 150
TJ-JUNCTION TEMPERIITURE I"CI

TJ-JUNCTION TEMPERATURE ("CI

Receiver Sensitivity vs
PLL Lock Range and Loop Filter

Receiver Sensitivity vs
PI-I;. Lock Range and Fo

PLL ~~lIre" Lock Range VB
Junction Temperature

('00_.
0/"

dF .....j-.j,--+J.HI.luT IOF
locK
IN LOCK
LOCK

>-

!;

II-1o

IJ

: CAPTURE

r::
~~~~LO~CK:ttjU~TjO~Ftif!CK~
15- r.±::j":-,--,~I:±T+.I~+-IH-1IH
40-

_ 50 ...H,o;16.,H"'1o....
AJA;;.,;L.OOP;;;...;.Ft;:;U"':ER.......I...J1..............
-60 -30 0 30 60' 90 1211 150
. TJ-JUNCTION TEMPERATURE I"C)

I
I

70

60

60 ... I'!!
40
30

Fa=

I :•

::::,..-~"'"

\!!'

.."sa

-10

10

_

~~

30

II'I~'"
.~
.1

0.1 \-I...L..I...L.CIIooo6.lo£.J-'-LLJ..J

90 120 150

TJ-~ 1DIPERAnm:("C)

T

~ OUT
' ~ OF

LO,CK
tJ'LDOP FILTER I

-30 -.·'0 10
30
LOCK RANGE 1% OF Fa)

50

Offset Hold cap. Charge
Currenta vs Junction
,Telllperature
160 ,
140i

100;

v.

180

8O~

60
1 40
I 211

60 21
40i
20

I

II

tpCK

-50

50

OEV. -404%

100

PtL IN

OF \:

LOCK .
I

I. 1-'
Vpo
;;;
~·'21Ilr

i

IDATA· -1+41+--1
F"j'ILTER

OUT k-

u!!jfD

pt.... Detector Output
Voltage vs Junction
Temperature

•

lO.~_

-eo -30 0 30 •

III

LOCII RMOE 1'0\ lIF FU

Ij'

~O:!

-80 -30

0 30 60 90 1211 150
Tj-JUNCTION TEMPERATURE rCI

Data Out. Low Voltage vs
Pull Down,Curren.

Oftset Hold cap. Bias Current vs
Junction Temperature

f:fm

-30

"

H16H

I lo~~I'~!t~~~~~~

1~~~~~~~~~

-60 -30 .0 30 60 90 1211 150
T~;:-JUN'TION TEMPERATURE I"CI

1:

S

HIGH
IooTA

50 kHz

160
-140

•

>-

il°~111!

Ii

i!l

ImpulSe Noise Filter
Current va Junction
Temperature

1

100mwn

( 1-4\+-+1::;
l:tE

I4:11"
:
CHARGE

.5

~

~ .30

~

20

10

DISCHARGE'!Iii
MCM

FULL SWITCHING

OL..L..L...J....I....I-I...JL...L.J...J.....L..I....J....I

-60 -30 0 30 60 90 120 150
TJ-JUNCTION TEMPERATURE I"CI

Pin 7 Bias Voltage vs
Junction Temperature

a

I~.

I
~I

u

H-+++-H'2if!i..ol~+-I
~.~~H-~~~+4~

0'' ' ' .

10

COlLECTOR CURRENT ImAl
TL/H/6750-39

4-170

Dual-In-Llne Package

Application Information*
THE DATA PATH
The BI-LiNETM chip serves as a power line interface in the
carrier-current transceiver (CCT) system of Figure 3. Figure
4 shows the interface circuit now discussed. The controller
may select either the transmit (TX) or receive (RX) mode.
Serial data from the controller is used to generate a FSKmodulated 50 to 300 kHz carrier on the line in the TX mode..
In the RX mode line signal passes through the coupling
transformer into the PLL-based receiver. The recreated serial bit stream drives the controller.
With the IC in the TX mode (pin 5 a logic high), baseband
data to 5 kHz drive the modulator's Data In pin to generate
a switched 0.978111.0221 control current to drive the low TC,
triangle-wave, current-controlled oscillator to ± 2.2% deviation. The tri-wave passes through a differential attenuator
and sine shaper which deliver a current sinusoid through an
automatic level control (ALC) circuit to the gain of 200 current output amplifier. Drive current from the Carrier 110 develops a voltage swing on Tl'S (Figure 4) resonant tank
proportional to line impedance, then passes through the
step-down transformer and coupling capacitor Cc onto the
line. Progressively smaller line impedances cause reduced
signal swing, but never clipping-thus avoiding potential radio
frequency interference. When large line impedances threaten to allow excessive output swing on pin 10, the ALC
shunts current away from the output amplifier, holding the
voltage swing constant and within the amp's compliance'
limit. The amplifier is stable with a load of any magnitude or
"
phase angle.
In the RX mode (pin 5 a logic low), the TX sections on the
chip are disabled. Carrier signal, broad-band noise, transient
spikes, and power line component impinge of the receiver's
input highpass filter, made up of Cc and Tl, and the tank
bandpass filter. In-band carrier signal; band-limited noise,
heavily attenuated line frequency component, and attenuated transient energy pass through to produce voltage swing
on the tank, Swinging about the positive supply to drive the
Carrier 110 receiver input. The balanced Norton-input limiter
amplifier removes DC offsets, attenuates line frequency,
performs as a bandpass filter, and limits the signal to drive
the PLL phase detector differentially. The differential de- '
modulated output Signal from the phase detector, containing AC and DC data Signal, noise, system DC offsets, and a
large twice-the-carrier-frequency component, passes
through a 3-stage RC lowpass filter to drive the offset cancel circuit differentially. The offset cancelling circuit works
by insuring that the (fixed) ±50 mV signal delivered to the
data squaring ("slicing") comparator is centered around the
o mV comparator switch point. Whenever the comparator
signal plus DC offset and noise moves outside the carefully
matched ± 50 mV voltage "window" of the offset cancel
circuit, it adjusts its DC correction voltage in series with the
differential signal to force the signal back into the window.
While the Signal is within the ± 50 mV window, the DC offset
is stored on capacitor CM. By grace of the highly non-linear
offset hold capaCitor charging during offset cancelling, the
DC cancellation is done much more quickly than with an AC
coupling capacitor normally used in place of the offset cancel circuit. Since impulse noise spikes normally ring the signal symmetrically around 0 V, the fully bilateral offset cancel
topology affords excellent noise rejection. The switched current output of the comparator drives the impulse noise filter
integrator capaCitor that rejects all data pulses of less than
the integrator charge time. Noise appears as duty-cycle jitter
at the open collector serial data output.
4-171

ICO CAP 1

ICO FREQUEIICY

ICGCAP2

OATAIN
UMITEtI fiLTER

PllFltJElll
15

Pll FI\JER 2

lX/IIllULECT
OFFSET HOLD CAP

1.11l1li3

V'

1.

BROIINO

13

HOllE 1NlE8_

AU: ITAIIUTY

12

OATAOUT

BOOST EMmER

11

5.IVZEIIEII

IOII8TBASE

l'

CARRIER 110

TL/H/6750-2

Top View
Order Number LM1893N

See NS Package Number Nl8A
Small Outline & Dual-In-Llne Package
!CO CAP 1
!CO CAP 2

!CO FREQUENCY

DATA IN

PLL nLTER 1

LIlITER filTER

PLL FILTER 2

GROUND

v+

TX/iiX saECT

CARRIER IN

DFFSET HOLD CAP

NOISE INTEGRATOR

DATA OUT

ALe STABIUTY

5.6V ZENER

BOOST BASE

CARRIER OUT

Top View

TL/H/6750-41

Order Number LM2893M or LM2893N

See NS Package Number M20B or NZOA
FIGURE 2. Connection Diagrams

TLlH/6750-3

FIGURE 3. The block diagram of a carrler-current
system using the BI·Llne chip to Interface digital
controllers via the power line
'Unless othetwise noted, all pin references refer 10 LMI893, but hold true
for equivalent LM2893 pin.

II

LM1893/LM2893

•

"CI

'2.

g
0'

f~
Cc: ~

.

=I

5'

0-

CONTROLLER

HOT
GND
HUE

TX

TX/H

DATA

SELECT

~

·3

a

v+

Tl

18

0'

117

~

i
!

10

!

~

lie

TL/H/6750-4

FIGURE 4. Block diagram ot.a CCT syetemwlth thebooet and 5Y supply options shown In dashed boxes

Application Information (Continued)
Recommended
Value

#

Purpose

Effect of making the component value:
Smaller

Notes

Larger

Co

560pF
Ro 6.2kO

Together, Co and Ro Increases FO
set ICOFo.
Increases Fo
< 5.6 k not recommended.

± 5% NPO ceramic. Use low TC
Decreases FO
2 k pot and 5.6 k fixed R.
Decreases FO
> 7.6 k not recommended. Poor FoTCwith <5.6kRo.

CF 0.047 p.F

PLL loop filter pole

AF 3.3kO

PLL loop filter zero

Less noise immune, higher
fOATA' more PLL stability.
PLL less stable, allows
less CF. Less ringing.

More noise immune, lower
fOATA' less PLL stability.
PLL more stable, allows
more ~. More ringing.

Depending on AF value and
Fo, PLL unstable with large·
CF. See Apps. Info. CF
and RF values not critical.

Cc 0.22p.F

Couples Fo to line,
Cc and T 1 low-pass
attenuates 60 Hz.

Low TX line amplitude.
Less 60 Hz T 1 current.
Less stored charge.

Drives lower line Z.
More 60 Hz T 1 current.
More stored charge.

~ 250 V non-polar. Use 2Cc
on hot and neutral for max.
line isolation, safety.

Co

T1 Use
recommended
XFMA

Tank matches line Z,
bandpass filters,
isolates from line,
and attenuates
tranSients.

Tank Fo up or increase
L of T 1 for constant FO.
Smaller L: higher Fo or
increase Cc; decreased Fa
line pull.

Tank Fo down or decrease
L of T 1 for constant FO'
Larger L: lower Fo or
decrease Cc; increased Fo
line pull.

100V nonpolar,lowTC, ±10%
High large-signal needed.
Optimize for low Fo line
pull with control of Fo TC
andQ.

CA 0.1 p.F
AA 10kO

ALCpole
ALCzero

Noise spikes tum ALC off.
Less stable ALC.

Slower ALC response.
More stable ALC.

forCA~1oopF.

Limiter 50 kHz pole,

Higher pole F, more 60 Hz
reject. Fo attenuation?

Lower pole F, less 60 Hz
reject, more noise BW.

Any reasonably low TC cap.
300 pF guarantees stability.

0.033p.F

CL 0.047 p.F

60 Hz rejection.
CM 0.47 p.F

Holds RX path Vos

Or

Rejects short pulses Less impulse reject, less
like impulse noise.
delay, more pulse jitter.

0.047 p.F

a

AA optional. ALC stable

Less noise immune, shorter More noise immune, longer Low leakage ± 20% cap.
Vos hold, faster Vos aqui- Vos hold, slower Vos aqui- Scale with fOATA.
sition, shorter preamble.
sition, longer preamble.
More impulse reject, more
delay, less pulse jitter.

CI charge time Yz bit nom.
Must be < 1 bit worst-case.

Ac 10kO

Open-col. pull-up

Less available sink I.

Less available source I.

Ac~1.5 kO on 5.6 V

Az 12kO

5.6 V Zener bias

Larger shunt current,
more chip dissipation.

Smaller shunt current,
less V+ current draw.

1  200 MHz. AB > 24 Ohm.
Less 10, lower min. lite.
10=70[(10+AG)/AGl mApp.

CB ~47 p.F

Supply bypass

Transients destroy chip.

Less supply spike.

V+ never over abs. max.

ZA 5.W

Stop ALC charge
in RXmode

ExcessALC
current flow

ALC AX charging
not inhibited over TJ

ZA optional- 5.1 V
± 20% low leakage type

Dr

~44VBV

Carbon compo recommended.
IAF 110005 or 1N5819

FIGURE 5. A quick explanation of the external component function using the circuit of F1gun14. Values given are for V+ =
18 V. FO = 125 kHz, foATA = 360 Baud (180 Hz), using a 115 V 60 Hz power line

Component Selection
Assuming the circtJit of Figure 4 is used with something other than the nominal 125 kHz carrier frequency, 180 Hz data
rate, 18V supply voltage, etcetera, the component values
listed in F/fJUre 5 will need changing. This section will help
direct the CCT designer in finding the required component
values with emphasis placed on look-up tables and charts. It
is assumed that the designer has selected values for carrier
center frequency, Fo; data rate, fOATA; supply voltage, V+;
power line voltage, VL; and power line frequency, FL. If one
or more of those parameters is not defined, one may read
the data sheet and make an educated guess.

ance considerations only, are: 1) the higher the Fo the better, 2) the lower the maximum data rate the better, and 3)
the more time and frequency filtering the better.
Use Figure 5 as a quick reference to the external component function.
THE TRANSMmER

Co
Cantral to chip operation is the low TC of Fo emitter-coupled oscillator. With proper Co, the Fo of the 2VBE amplitude triangle-wave oscillator output may vary from near DC
to above 300 kHz. While Co may have any value, Co should

Maxims to keep in mind, based on CCT electrical perform4-173

III

Component Selection

(Continued)
be made above 10 pF so that parasitiC Capaci~nce is not
dominant. Excessive or unbalanced 'common-mode-togrpund capaCitance Should be avoided. A low temperature
coefficient (TC) of oapapitance «100 PPM/oC), such as a
monolithic NPO ceramic multilayer type, preserves low TC
of Fo. Figure 6 finds a Co value given Fo., '

Tl
, At this point, the beT system designer may choose to use
one of the recommended transformers or to design custom
Tl. Consult "The Coupling Transformer" section to help
with the deSign ofT1 if a new or boost-capable transformer
is needed. The', recommended 125 kHz transformer functions with an 10 of up to 600 mApp.
It is recommended that CCT systems use the recommended
transformers, described in Figure 7, for T1. The 3 transformers are optimized for use in the ranges of 50-100 kHz, 100200 kHz. and 200-400 ~Hz with unloaded O's (Ou) of' about
35, and 10adedO's (OU of about 12. Three secondary taps
are supplied with nominal 7.07, 10, and 14.1 turns ratios (N)
to drive industrial and residential power line impedances of
3.5, 7, and 140 respectively. All are inexpensive, all have
the same pin-outs for easy exchange in a PC board, and all
are small - on the order of 10 mm diameter at the base.

RO
Resistor Ro is used by the IC to generate a VeE/Rrelated
current that is multiplied by 2 to prodLice the 200 /LA ICO
control current that sets Fo. The control current TC ,"bUcks"
the VeE related tri-wave amplitude across Co to enect a low
TC of Fo. Vary Ro to trim Fo, within limits. Raising Fo more
than 20% abOllEl ,its untrimmed value by means of decreasing Ro more than 20% is not recommended. Low Ro, and
so high control current, risks ICO saturation and poor TC
under worst-Case conditions. Raising Ro reduces the demodulated signal amplitude from the phase detector; raiSing
Ro by more than a factor of 2 (1 octave) is not recommended.
Since lower TC pots are relatively costly, it is recommended
that Ro be made up of a 5.6 k fixed « 100 PPM/DC) resistor
with a 2 kO «250 PPMI"C) series pot.

CQ
Tank resonant frequency Fa must be correct to allow passag!! of transmitter signal to the line. Use Figure 8 to find
Co'S value. Trimming Fa to equal Fo is done with T I'S trimming slug. The inductance of T1 has a TC of + 150 PPM/oC
which may be cancelled by using a -150 PPM/DC cap such
as polystyrene. Since circulating current in the tank is %
ARMS, Co should have a low series resistance (a 1 0 series
tesistance is too much). Polypropelene caps are excellent,
"orange drop" mylars are adequate, while many other mylars are ,inadequate. A 100V rating is needed for transient
protection.

CA,andRA
Comporlents C",and RA control the dynamic characteristics
of the transmitter output envelope. Their values are not critical. Use the values given in Figure 5. CA ~nd RA are functions of loaded Tl tank 0, Ao, fDATA' and line impulse
noise. ,Any changes made in CA and RA should be made
based on empirical measurements of a CCT on the line.
Roughly, CA acts as an ALC pole and ~A an ALC zero.

50· ;;8i]1
I ~ = ~Ht1it
i 50 ~ 108

~II'~~~'

000
i... 5000

r-10.1Ii 100

1

10

(2Jd'o)iLl

!!<,5GOB
.O,di

i3

I

a 0.01 ,L-I...Ll.lWIIL-LJU.

Co

L1 • 18.9

I

100

8

1000

0.5

10

Po -CARRIER CEIITEII FREQUENCY (kHz)

100

1000

Ft-CARR,IER FftEQUENCY (kHz,
TL/H/6750-10

TLlH/6750-5

FIGURE 8. Find Co's value given Fo

FIGURE 8. Find Co's value knowing Fo

I

4:'~'~]3 E',n.o.9BO,," 731~~ J3
Ll

s
Bottom View
TL/H/6750-6

4

41/21.0.406,,"
2.31/21.0.245,,"

'S

125 kHz

S

5

I

4

TLlH/6750-7

E810T.2.00.H
71/21.1.13,,"

25112T.0.805,,"

~8~~~ J3,
4

TL/H/6750-6

Toko 707VX-A042YUK

5

1112 T. 0.056 ""

S

TL/H/6750-9

50kHz

300,kHz

Taka 707VX-A043YUK

Taka 161XN-A207YUK

FIGURE 7. The recommended T 1 tran.formers, available th"9ugh:
Taka' America, 1250 Feehanvllle Drive, MOllnt Prospect,lL, 60056, (312) 297·0070

4-174

E6
2

S

S

5,

I ::~:':~56,,"

Component Selection

(Continued)
neous power of greater than 1 kW has been measured using the recommended transformers). For self protection, the
Carrier I/O has an internal 44V voltage clamp with a 200
series rasistance. A parallel low impedance 44V external
transient suppression diode will then conduct the lion's
share of any current when transients force the Carrier I/O to
a high voltage.

Cc
Capacitor Cc's primary function is to block the power line
voltage from Tl'S line-side winding. Also, Cc and Tl'S lineside winding comprise a LC highpass filter. The self-inductance of T1 is far too low to support a direct line connection.
Ce must have a low enough impedance at Fo to allow T 1 to
drive transmitted energy onto the line. To drive a 140 power
line, the impedance of Cc should be below 140.

10l1li

i

Use Figure 9 to find the reactive impedance of Ce to check
that it is less than the line impedance. Then check Figure 10
to see that the power line current is small enough to keep
T1 well out of saturation; the recommended transformers
can withstand a 10 Amp-tum magnetizing force (1 Amp
through the worst-case 10 turn line-side winding) •
. Caution is required when choosing Cc to avoid series resonance of the series combination of Ce, the transformer inductance, and the reflected tank impedance. The low resistance of the network under series resonance will load the
line, possibly decreasing range. For your particular line coupling circuit, measure for series resonance using some expected line impedance load.

i

I
:::I

11111

TL/H/6750-12

FIGURE 10. The AC line-Induced current passed by Ce
1lIII0

~

100

10 =0.0247((10+Ra)/l0Ila)
TJ=25·C

~
c

rr-

i

lD

~
f=

.1

I""~

~

D.l

~IIIIIIII

1

lD

8

i

10

c-

r-

~

0.1

I

1
0.1
1
10
Cc-LlNE COUPLING CAPACITANCE (,.I'I

11111~.

I

~11

W

as

tJ 10

10

z

Ra
This base-bleed resistor turns
off quickly - important
since the amplifier output swing is about 200Vl,...s. An As
below about 240 will conduct excessive current and overload the chip amplifier and is not recommended.

e:

~I

a: 1l1li 55

B
li
ill

1
1l1li

Ra-CIAIN-SETTIN8 "(0)

TL/H/6750-13

FIGURE 11. Output amplifier current and required min.
Oa hte versus galn-settlng resistor RG

'--..L...,L..I.JUJ.IJL....-L...I.:Iool.l.L
:
defined as the fOllowing:',

giving an L2 of 0.98 p.H. Note that the recommended 125
kHz transformer mirrors these specifications. The resonating capacitor is'
1~'
",.
(27TFa)2 Ll '7', ,3,3.1, x ~O-::~

=;,

33 nF

',,"

Communication and System
Protocols '
' '.
.

N

Co =:

"

Audio 1'ransmission,

An iterative sol!Jtion is forced where line pull, .o.Fa. 1114st be
gueSSed to find aL and L,. L, is then used to check the line
pull guess; a large error reqUires a new guess. TrY Ii ,BW of
8.1% - that is 4.4% for deviation. 1% for TC o'-Fo. and
3.3% for ~Fa - giving 'aL = '11.5. ,
'
,
L, = .27T'x

',,', '

(11)

1. Communicatioftprotocof. a software method of enQOding
and decoding data that remains constant for,every tranllmis-

(16)

4.,182

,.....~......~-'!'"""..J!'..., FEAlURES

,. 'oNftorr=O.2mo

CARRIER
DE1ECr

2.

LII567

~11MlY=5mV

OR LESS

3. PARTS COUNT-',
4. NOISE INSENSIIIVE

EJ:_'OI'F
5V

TLlHf6750-33

FIGURE 30. A simple carrier amplitude detector with output low when carrier Is detected

LM'B93!PIN 3
PlN4~~...~~~~~-.......t-~~

2.7 J:500,.F

'-4~"'''''''''r~t
,

PIN 18 ' 10 of 39Dk
LM1I83-1 U..

TRANSMITTER
.

AUDIO IN
±1Vp

~ ±2.5.,A

'±2.2!1 DEY

TLlH/6750~34

FIGURE 31, A simple IIne!lr analog audio transmitter and receiver are shown. '
The carrier and 1.6V Inpuls are derived from the carrier detector of FIgure 30.
The remaining 2 LM339 comparatora may be used to build the carrier detector circuit.

Communication and System
Protocols (Continued)
sion in a system. Its first purpose is to put data in a baseband digital form that is more easily recognized as a real '
message at the receive end. Secondly, it incorporates encoding techniques to ensure that noise induced errors do
not easily occur; and when they do, they can always be
detected. Lastly, the software algorithms that are used on
the receive end to decode incoming data prevent the reCeption of noise induced "phantom" messages, and insure the
recovery of real messages from an incoming bit stream that
has been altered by noise.
2. System protocol: the manner in which messages are coordinated between nodes in a system. Its first purpose is to

4-183

ensure message retransmission to correct errors (handshake). Secondly it coordinates messages for maximum utilization and efficiency on the network. Lastly, it ensures that
messages do not collide on the network. Common system
protocols include master-slave, carrier detect multiple access, and token passing. Token passing and master slave
,have been found to be'the most useful Since they are inhereritly collision free.
Both protocols usually reside as software in a single microcontroller that is connected to the LM1893/2893 110. In any
case, some sort of intelligence is needed to process incoming and outgoing messages. UARTs have no usefulness in

III

Communication and System
Protocols (Continued)

transmission, using a random number of bits delay or a delay based on each transmitter's address, since each transceiver has a unique ~ddress.

carrier current applications since they do not have the intelligence needed to distinguish between real messages, and
noise induced phantoms.

An examPle of a simple transmission data packet is shown
in F/{/ure 32. The 8 bit 50% duty-cycle preamble is long
enough to allow reCEliver biasing with enough bits left over
to allow the receiver controller to detect the square-wave
that signals the start of a transmission. If there had been no
transmission for some time, the receiver would simply need
to note that a data transition had occurred and begin its
watch for a square-wave. If the receive controller deteC?led
the alternating-polarity data square-wave it would then use
the sync. bit to signal that the address and data were immediately following. The address data would then be loaded,
assuming the fixed format, and tested against its own. If the
address was correct, the receiver would then load and store
the data. If the address was not correct, either the transmissio~ was not meant for this receiver or noise has fooled the
receiver. In the former case, when the transmission was not
meant for the receiver, the controller should immediately
return to watching the incoming data for its address. If the
later case were true, then the receive controller would continue to detect .edges, tieing itself up by loading false data
and being forced to handshake. The square-wave detection
and address load and check routines should be fast to minimize the time spent in loops after being false-triggered by
noise. If the controller detects an error (a received data bit
that does not conform to the pre-defined encoding format) it
should immediately resume watching the LM1893's Data
Out for transmissions, the next bit would be shifted in and
the process r~peated.
.1

The difficulty in designing special protoeois arises out, of the
special nature of the AC line, an environment laden with the
worst imaginable noise conditions. The relatively low data'
rates possible over the AC line (typically less than 9600
baud) make it even more imperative that systems utiJize~he
most sophisticated means available to ensure netWork effi'
ciency.
With these facts in mind, the designer is referred to a publication intended to aid in the development of carrier current
systems. This is literature #570075 The Bi-Llne Carrier Current Networking System, a 200 pp. book. that fUnctions as
the "bible" of Bi-Llne system design. It has sections on
LM1893 circuit optimization, protocol design, evaluation kit
usage, critical component selection, and the Datacheckerl
DTS case study.

Basic Data Encoding (please refer to the previously mentioned publications for advanced techniques)
At the beginning of a received transmission, the first 0 to 2
bits may be lost while the chip's receiver settles to the DC
bias point required for the given' transmitter/feceiver pair
carrier frequency offset. With proper'. data encoding,.
dropped start bits can be tolerated and correct communication can take place. One Simple data encoding scheme is
.
now discussed.'

A line-synchronous CCT system passing 3 bits per half-cycle may replace the long 8 bit preamble and sync pulse with
a 2 bit start-of-transmission bias preamble. The receive controller might then assume that preamble always starts after
bit 1 (the first bit after zero-crossing) so that any data transition at a zero crossing must be the start of the address bits
and is tested as such. The line synchronous receiver operates. with a simpler controller than an asynchronous system.

Generally, a CCT system consists. of many transceivers that
normally listen to the line alall times (or during p~~r­
mined time windows), waiting for a transmission that directs
one or more of the receivers to operate. If any receiver finds
its address in the transmitted data packet, further action
such as handshaking with the transmitter is initiated. The
receiver might tell the transmitter, via retransmiSSion, that it
received this data, waiting for acknowledgement before acting on the received command. Error detecting and correcting codes may be employed throughout. The transmitter
must have the capability to retransmit after a time if no response from the receiver is heard - under the assumption
that the. receiver didn't detect its address because of noise,
or that the response was.missed becaose.,of noise or a line
collision. (A line collision happens when more than 1 transmitter operates at one time - causing one or more of the
communications to fail). After many re-transmissions the
transmitter might choose to give up. Collision recovery is
achieved by waiting some variable amount of time before re-

Di~ossion haS assumed that the controller has always
known when the Data Out is high or low. The controller
must sample at the proper time to check the Data Out state.
Since noise shows itself as pulse width jitter, symmetrically
placed about the no-noise SWitch-points, optimum Data Out
sampling is done in the center of the received data pulse.
The receive data path has a time delay that, at low data
rates; Is dominated by the impulse noise fiiter integrator and
is nominally Yz bit. At a 2 kHz data rate, an additional delay
of approximetely Y.o bit is added because of the cumulative
delay of the remainder of the receiver. Figure 33 shows, that
Data Out samplingoecurs conveniently af the transmitted

~~.,

II'~'I~'
nrc
..

.

III

" i . . ,

TUH/6750-35

FIGURE 32. A simple, encoded data pa!*et, generated by the transmit controller Is shown.
"
The horizOntal axis Is time where 1 bit time Is 1/(2fDATA>

4-184

Because the coupling transformer is used as a filter, the
LM1893 circuit is susceptible to pulling of the center frequency under conditions of changing line impedances or
when several LM1893 circuits are close in proximity on the
AC line. Because the tuned transformer has a high value of
"Q", ringing also occurs in the presence of impulsive noise.
This ringing occurs at the canter frequency and increases
the error rate of transmissions, especially at relatively high
data rates (> 2000 baud). Because it is the only tuned circuit
in the system, the selectivity characteristics leave a lot to be
desired.

Basic Data Encoding (Continued)

The LM2893, having separate receive input and transmit
output pins, removes the limitations on coupling transformer
design, allowing the design of circuits devoid of the previous
limitations.
The first enhancement that can be made with the LM2893
circuit is the use of a high permeability ferrite toroid for line
coupling along with a separate filter. The transformer would
be of broadband design (untuned) with two secondaries,
one for coupling to the transmit output and one for coupling
to the receive input. This allows impedance matching of
both the transmitter and receiver, with the result of quite a
bit more receive sensitivity.

TLIH/6750-36

FIGURE 33. Operating waveforms of a linesynchronized transceiver pair are shown. The diagram
shows how the transmitted data transHlons may be
used as received data sampling points
data, edges for the line synchronous data transmission
scheme mentioned in the previous paragraph. With the
asynchronous system suggested, the receive controller
must sample the Data Out pin often to determine, with several bits of accurilCY, where the' square-wave data transitions take place, average their positions assuming a
known data rate, and calculate where the center of the data
bits are and will continue to be as the address and data are
read. A long preamble is helpful. Software that continuously
updates the centeroOf-bit time estimate, as address and
data are received, works even better. Alternatively, a coding
scheme employing an embedded clock can be used.

Because of the increased signal and separate receive signal
path, a 3 or 6 db pad can be used before the selective
stages to eliminate pulling of the center frequency due to
changes in line impedance.
Another advantage of the toroidal transformer is that it can
be designed for use at very low line impedances due to its
inherent tight coupling.

SEPARATE FILTER

LM2893 Application Hints

Because of the separate receive path of the LM2893, a relatively high quality bandpass filter can be used for selectivity.
Inexpensive ceramic filters are available that have bandpass and center frequency characteristics compatible with
carrier current operation. Futhermore, the use of tl)ese filters allows multichannel operation, previously made difficult
by the Single tuned network of the LM1893. These filters are
easily cascaded for even more off-frequency rejection. If the
pad is added before the filter, there will be negligible pulling
due to changes in line impedance reflected through the coupling transformer.

The LM2893 is intended for advanced applications where
special circuitry is used in the transmit and receive paths.
The LM2893 makes this possible by featuring separate
transmit output and receive input pins.
Examples of enhancements that can be added to the basl~
LM1893/2893 circuit include separate transmit and receive
windings on the coupling transformer, high quality ceramic
or LC filters in the receive path, and simple impulse noise
blanking circuits.
In many applications, the additional performance to be
gained outweighs the extra cost of the additional circuitry.
More than likely, high performance industrial applications
such as building energy management will fit into this category, since they require the utmost in reliability.
Because of the specialized nature of individual LM2893 applications, it is not possible to give one circuit that will satisfy
all requirements for performance and cost effectiveness.
Therefore no specific application examples will be given.
Instead the subsequent text describes in general termS the
types of circuits that can be' used to increase performance
along with their advantages and disadvantages. It is intended to be a springboard for ideas.

LM2893 COUPLING NETWORKS
The main disadvantages of the typical LM1893 coupling
network are that it functions as the bandpass filter, has
loose coupling between primary and secondary, and has a
single secondary. The LM1893 coupling network was designed this way mainly because of the restraint that the car-,
rier input and output are tied together.

Alternatively, a Butterworth/Chebyshev bandpass LC filter
or an active filter can be used in place of the ceramic filter.

IMPULSE NOISE BLANKER
Although the LM2893 has adequate impulse noise rejection
'for most applications, there is reason to employ impulse
blanking to improve error rates in severe AC line environments. Typically, errors occur due to pulse jitter in the
LM1893/2893 data output that originates when the internal
time domain filter smooths out an incoming noise pulse.
The solUtion involves removing the impulse completely and
, • not simply trying to filter it. Moreover, the pulse should be
removed in the receive signal path before the selective portions of the circuit to eliminate ringing. This also allows the
.receiver filter to smooth out the blanks that also occur in the
desired incoming carrier signal.
If a carrier detect circuit is desired in conjunction with the
LM2893.it can be located after the filter and impulse blanker. 'Because impulse noise is removed, the falise triggering
that plagues these circuits will be greatly reduced.

4-185

•

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"

4. FCC, "Notice of Proposed Rule Making," Docket 20780,
adopted Apr. 14, 1976, (Proposed regulation)
5. Monticelli, Dennis M. and Michael E. Wright; "A Carrier
Current Transceiver IC for Data Transmission Over the
AC Power Lines;" IEEE J. Solid-State Circuits; vol. SC-17;
Dec. 1982; pp. 1158-1165; (LM1893 circuit description)
6. Lee, Mitchell;· "A New carrier Current TransceIver IC;"
IEEE Trans. on Consumer Electronics; vol. CE-28; Aug.
1982; pp. 409-414; (Application of LM1893)

References
1. Nicholson, J.R. and J.A. Malack; "RF Impedance of Power Lines and Line Impedance Stabilization Network in
Conducted Interference Measurements;" IEEE Transactions on Electromagnetic Compatibility; May 1973; (line
impedance data)
2. Southwick, A.A.; "Impedance Characteristics of SinglePhase Power Lines;" Conference Rae.; 1973 IEEE Int.
Symp. on Electromagnetic Compatibility; (line impedance
data)

3. Hayt, William H. Jr. and Jack E. Kemmerly; "Engineering
Circuit Analysis;" McGraw-Hili Books; 1971; pp. 447453; (linear transformer reflected impedance)

•
4-187

~

r----------------------------------------------------------------------------,

I IfIN

a ti (J .. a I S e In /C o. n due tor

LMC56.7 .Low Power Tpne De,coder,
General Description

Features

The LMC567 is a low power general purpose LMCMOSTM
tone decoder which is functionally similar to the industry
standard LM567. It consists of a twice frequency voltagecontrolled oscillator (VCO) and quadrature dividers which
establish the reference signals for phase and amplitude detectors. The phase detector and VCO form a phase-locked
loop (PLL) which locks to an input signal frequency which is
within the control range of the VCO. When the PLL is locked
and the input signal amplitude exceeds an internally pre-set
threshold. a switch to ground is activated on the output pin.
External components set up the oscillator to run at twice the
input frequency and determine the phase and amplitude filter time constants.

•
•
•
•
•
•
•
•
•
•

Functionally similar to LM567
2V to 9V supply voltagerilnge
Low supply current drain
No increase in current with output activated
Operates to 500 kHz input frequency
High oscillator stability
Ground-referenced input
HysteresiS added to amplitude comparator
Out-of-band signals and noise rejected
20 mA output current capability

Block Diagram (with External Components)
Vs
Rl
OUTPUT

----t

Vs

FILTER

8
OUTPUT

7

LOOP

GROUND

fiLTER
r---~--1t--i +2

INPUT

>-___3+-........
, veo

Rt

TIMING
RESISTOR

LIofC567

TL/H/8670-1

Order Number LMC567CM or LMC567CN
See NS Package Number M08A or N08E

4-188'

Absolute Maximum Ratings
If Military/Aerospace specified deYlces are required,
please contact the National Semiconductor Sales
Office/DIstributors for availability and specifications.
2Vp_p
Input Voltage, Pin 3
Supply Voltage, Pin 4
Output Voltage, Pin 8
Voltage at All Other Pins
Output Currant, Pin 8
Package Dissipation
Operating Temperature Range (TAl

-S5"Cto +1SO"C

Storage Temperature Range
Soldering Information
Dual-In-Line Package
Soldering (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (1S sec.)

10V
13V
VstoGnd

26O"C
21 SoC
220"C

See AN-4S0 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

30mA
SOOmW
- 2SoC to + 12SOC

Electrical Characteristics
Test Circuit, TA = 2SoC, Vs = SV, RtCt #2, Sw. 1 Pos. 0, and no input, unless otherwise noted.

Symbol
14

Parameter
Power Supply Current

Conditions
RtCt # 1, Quiescent
or Activated

Min

Typ

Max

Units

mAdc

0.3

Vs = 2V
Vs= SV

O.S

0.8

Vs= 9V

0.8

1.3

V3

Input D.C. Bias

0

mVdc

R3

Input Resistance

40

kO

18

Output Leakage

fo

Center Frequency,
Fosc + 2

1

RtCt #2, Measure Oscillator
Frequency and Divide by 2

Vs= SV

92

Center Frequency
Shift with Supply

fol9V - fol2V X 100
7fol5V

Vin

Input Threshold

Set Input Frequency Equal to fo
Measured Above, Increase Input
Level Until Pin 8 Goes Low.

20

27

30

4S

Output"Saf Voltage

Input Level> Threshold
Choose RL for Specified 18

X 100

O/O/V

11

V8

Foscl~~I~osclpl

2.0

17

mVrms

4S

Vs = 9V

L.D.B.W =

kHz

Vs= SV

Starting at Input Threshold, Decrease Input
Level Until Pin 8 goes High.

Measure Fosc with Sw. 1 in
Pos. 0, 1, and 2;

113

Vs= 2V

Input Hysteresis

Largest Detection
Bandwidth

103

1.0

AVin

L.D.B.W.

nAdc

10S

Vs= 9V
Afo

100

98

Vs = 2V

1.S

18 = 2mA

0.06

18 = 20mA

0.7

mVrms
0.1S

Vdc

Vs = 2V

7

11

1S

Vs = 5V

11

14

17

0/0

±1.0

0/0

Vs = 9V

1S

ABW

Bandwidth Skew

Skew = (Fosclp2 + Fosclpl - 1) X 100
2 FosclPO

f max

Highest Center Freq.

RtCt #3, Measure Oscillator Frequency and
Divideby2

700

kHz

Vin

Input Threshold
atfmax

Set Input Frequency Equal to f max measured
Above, Increase Input Level Until Pin 8 goes Low.

3S

mVrms

4-189

0

Test Circuit

;

Vs

rl

:lin

uu

-= 8.5k~~~

,1
SW.l
0

13
-=

1

..d~2

0.01 p.F

","~r

-= O.egl p.F

8

,~

V

..,....

1-

S

--

0.Ip. F

Rt

Ct' .

'#.1
#2
#3

100k
10k
5.1k

300pF·
300pF
62pF

V8

7q.
LMC567

3

504

Rtet

"

-

I

:U·'~

MEASURE Fose.-J
W1TH !:.10 pF PROBE
TL/H/8670-2

Typical Performance Characteristics
Bandwidth VB.
Input Signal Level

SuPPly Currentva•.
Operating Frequency
1.2

TA=~,Vs=5V

1.0

o.a

~

o.a

fa

/

1

~

~§!

~

RI=5.1 k.O.

!

'"

RI=I00kll

'0.4

If110

Ol

0

17

lIST CllCUII, Vs .. 5V,
250 AICII2

16

10k

lOOk

;to
:!;
~

150
100

1M

INPUT
0

246

t

i5.
!:l
M

~

tk,
,
:
:- r-,:

~.

1~

r-...

103
102

~

U

~

0

2 .4

6

8 10 12 14 16 18

8AHOWlDTH (:Ii

or Fol

r......

13
12
11

-50

~

0

3.0

1.5
lIST ctRCUII,AICIII

I

150

Frequency Drift
with Temperature

2.Q

g

0.5

r-...

~
~

100

lIST CIRCUli, Rlet #2

1.0

g

50

1£MPERAlURE (ac)

0
-0.5

vlJ
" .............

r\.

1.0

~

l!!

I

i'

-1.0

10
0

8 W

Frequency Drift
with Temperature

TA =25'C, Vs=5V

\

liIRESHo'iO..J -

15
14

8AHOWlDTH (I OF Fol

Bandwidth aa
a Function of C2

105

I

V-

50

INPUT FREQUENCY (Hz)

106

lIST CIRCUli, Vs=5V,AICI,2

200

0
lk

Largest Detection
Bandwidth va. Temp.

3110

,'.

r\

0

"

-1.0

Vs=5V
-2.0

~

-3.0

-1.5
-50

0

50

100

1£MPERAlURE (ac)

150

-50

0

50

100

150

1£MPERAlURE (ac)
TL/H/8670-3

.'

4-190

.-----------------------------------------------------------------------------,~

~

Applications I nformation (refer to Block Diagram)
GENERAL
The LMC567 low power tone decoder can be operated at
supply voltages of 2V to 9V and at input frequencies ranging
from 1 Hz up to 500 kHz.
The LMC567 can be directly substituted in most LM567 applications with the following provisions:
1. Oscillator timing capacitor Ct must be halved to double
the oscillator frequency relative to the input frequency
(See OSCILLATOA TIMING COMPONENTS).
2. Filter capacitors C1 and C2 must be reduced by a factor
of 8 to maintain the same filter time constants.
3. The output current demanded of pin 8 must be limited to
the specified capability of the LMC567.

INPUT PIN
The input pin 3 is internally ground-referenced with a nominal 40 kO resistor. Signals which are already centered on
OV may be directly coupled to pin 3; however, any d.c. potential must be isolated via a coupling capacitor. Inputs of
multiple LMC567 devices can be paralleled without individual d.c. isolation.

LOOP FILTER
Pin 2 is the combined output of the phase detector and
control input of the VCO for the phase-locked loop (PLL).
Capacitor C2 in conjunction with the nominal 80 kO pin 2
internal resistance forms the loop filter.
For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built in VCO
frequency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will begin to become narrower than the LDBW (see
Bandwidth as a Function of C2 curve). However, the maximum hold-in range will always equal the LDBW.

OSCILLATOR TIMING COMPONENTS
The voltage-controlled oscillator (VCO) on the LMC567
must be set up to run at twice the frequency of the input
signal tone to be decoded. The center frequency of the
VCO is set by timing reSistor At and timing capacitor Ct
connected to pins 5 and 6 of the IC. The center frequency
as a function of At and Ct is given by:
1
Fosc "" 1.4 At Ct Hz

OUTPUT FILTER
Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 Signal output of 719 Vs. When the
PLL is locked to the input, an increase in signal level causes
the detector output to move negative. When pin 1 reaches
2/3 Vs the output is activated (see OUTPUT PIN).
Capacitor C1 in conjunction with the nominal 40 kO pin 1
internal resistance forms the output filter. The size of C1 is a
tradeoff between slew rate and carrier ripple at the output
comparator. Low values of C1 produce the least delay between the input and output for, tone burst applications, while
larger values of C1 improve noise immunity.
Pin 1 also provides a means for shifting the input threshold
higher or lower by connecting an external resistor to supply
or ground. However, reducing the threshold using this technique increases sensitivity to pin 1 carrier ripple and also
results in more part to part threshold variation.

Since this will cause an input tone of half Fosc to be decoded,
1
Finput .. 2.8 At Ct Hz
This equation is accurate at low frequencies; however,
above 50 kHz (Fosc = 100 kHz), internal delays cause the
actual frequency to be lower than predicted.
The choice of At and Ct will be a tradeoff between supply
current and practical capacitor values. An additional supply
current component is introduced due to At being switched
to Vs every half cycle to charge Ct:
Is due to At = Vs/(4At)
Thus the supply current can be minimized by keeping At as
large as possible (see supply current vs. operating frequency curves). However, the desired frequency will dictate an
AtCt product such that increasing At will require a smaller
Ct. Below Ct = 100 pF, circuit board stray capacitances
begin to playa role in determining the oscillation frequency
which ultimately limits the minimum Ct.

OUTPUT PIN
The output at pin 8 is an N-channel FET switch to ground
which is activated when the PLL is locked and the input tone
is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs.
Apart from the obvious current component due to the external pin 8 load resistor, no additional supply current is required to activate the switch. The on resistance of the
switch is inversely proportional to supply; thus the 'sat' voltage for a given output current will increase at lower supplies.

To allow for I.C. and component value tolerances, the oscillator timing components wil! require a ~m. This is generally
accomplished by using a variable reSistor as part of At, although Ct could also be padded. The amount of initial frequency variation due to the LMC567 itself is given in the
electrical specifications; the total trim range must also accommodate the tolerances of At and Ct.

SUPPLY OECOUPLING
The decoupling of supply pin 4 becomes more critical at
high supply voltages with high operating frequencies, requiring C4 to be placed as close as possible to pin 4.

4-191

~

f8

~ ~ Nat ion a I

S e m i con d u

~ t o'r

LMC568 L,OwPower Phase~Locked LoOp
".,

General Description

Features

The LMC568 is an amplitude-linear phase-locked loop eon- , • Demodulates ± 15% deviation FM/FSK signals
sisting of a linear veo, fully balanced phase detectors, and
• Carrier Detect Output with hysteresis "
a carrier detect output. LMCMOSTM technology is employed
• Operation to 500 kHz input frequency
for high performance with low power consumption.
• Low THD-O.5% typ; for ±10% deviation
The veo has a linearized control range of ±30'11. to allow
• 2V to 9V supply voltage range
demodulatio.n of FM and FSK signals. ,Carrier detect is indi• Low supply current drain
cated when the PLL is locked to an input signal greater than
26 mVrms. LMC568 applications include FM SCA and TV
second audio program decoders, FSK ,data demodulators,
and voice pagers.

Typical Application (100 kHz input frequency, refer to notes pg. 4-194)
RH

.------------~-----------.I

I
I

I

001.8~1,...w.r_ti4H_VS

:

Ct

C3

~_i~6----9--~3~00~

DE-EIIPHASlS INPUT~t--=:~.....
0.01 pF

LMC568
rosc

SET
TO ,2 xINPUT rREO.
MEASURE WITH :S10 pr PROBE

---1
TLlH/9135-i

Order Number LMC568CM or LMC568CN
See NS Package Number M08A or, N08E

4-192

Absolute Maximum Ratings
Operating Temperature Range (TN

If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OffIce/Distributors for availability and specifications.
2Vp_p
Input Voltage, Pin 3
Supply Voltage, Pin 4
10V
Output Voltage, Pin 8
13V
Voltage at All Other Pins
Output Current, Pin 8

VstoGnd
30mA
500mW

Package Dissipation

- 25·C to + 125·C

Storage Temperature Range
-55·Cto + 150"C
Soldering Information
Dual-In-Une Package
Soldering (10 seconds)
260"C
Small Outline Package
Vapor Phase (60 seconds)
215·C
Infrared (15 seconds)
220"C
See AN-450 "Surface Mounting Methods and their Effect on
Product Reliability" for other methods of soldering surface
mount devices.

Electrical Characteristics
Test Circuit, TA = 25·C, Vs = 5V, RtCt #2, Sw. 1 Pos. 0; and no input unless otherwise noted.
Symbol
14

Parameter
Power Supply Current

V3

Input D.C. Bias

R3

Input Resistance

18

Output Leakage

fo

Center Frequency
Fosc +2

Conditions
RtCt # 1, Quiescent
or Activated

Min

Units

mAdc

Vs = 2V

0.75

1.5

Vs = 9V

1.2

2.4

0

RtCt # 2, Measure Oscillator
Frequency and Divide by 2

Vs = 5V

Center Frequency
Shift with Supply

folev - fol2V X 100
7 fol5v

Vin

Input Threshold

Sat Input Frequency Equal to fo
Measured Above, Increase Input
Level until Pin 8 Goes Low.

90

kHz

1.0

2.0

O/O/V

8

16

25

26

42

V8

Output 'Sat' Voltage

Input Level> Threshold
Choose RL for Specified 18

1.5

18 = 2mA

0.06
0.7

Vs=2V

30

Vs = 9V

4BW

Bandwidth Skew

Skew = (Fosclp2 + Fosclp1 - 1) x 100
.
2 Fosclpo

Vout

Recovered Audio

Typical Application Circuit
Input = 100 mVrrns, F = 100 kHz
Fmod = 400 Hz, ± 10kHz Dev.

Vs=2V

mVrms

45

18 = 20mA

Vs= 5V

osc PO

115

103
105

Vs= 9V

x 100

100

15

Starting at Input Threshold, Decrease Input Level
until Pin 8 Goes High.

Foscl~2 -I Fosclp1

1

Vs =.5V

Input HystereSiS

L.D.B.W. =

kG
nAdc

Vs = 2V

4Vin

Measure Fosc with Sw. 1 in
Pos. 0, 1, and 2;

mVdc

40
98

Vs = 2V

4fO

Largest Detection
Bandwidth

Max

Vs= 5V

Vs= 9V

L.D.B.W.

Typ
0.35

40

mVrms
0.15

55

Vdc

0/0

60
1

±5

0/0

170

Vs= 5V

270

Vs=9V

400

mVrrns

THD

Total Harmonic
Distortion

Typical Application Circuit
as Above, Measure Vout Distortion.

0.5

0/0

S+N
-N

Signal to Noise Ratio

Typical Application Circuit
Remove Modulation, Measure Vn
(S + N)/N = 20 log  (Ctl [I - 2(0.632 - r) - VCIVREF) wheie r is timing ratio and Vc is capacitor
saturation voltage. This reduces to t = (At> (CIllor all but the most critical applications.
Note 4: Sign reversal may occur at high temperatures (> IOO"C) where comperetor input current is predominately leekage. See Iypcisl curves.
Note 5: Reier to RETSI22X drawing of military LMI22H version for specifICations.

4-197

-

mA

200

2.5
25

1 MO

Rt

V

p.A

0.62
0.62

= 2.5V

nA

nA
1.2

25
4

0.5

•

Typical Performance Characteristics

•

u
u

T........

~P;E::~·

....

Com-..-,a...c:urt.iftt

Comparator ales CUrrent '

•

i ..

I
l,,·,..e
I
I

II ~~
2.1

CDilPARATlR '.PUT VOLTAGE fY)

,

.

'.. T.· ..... I
i
!i

~~,.J'RlLJ

t-!.. -lIrc
t:ti'~.C;(I(

·u
....
•

"'l
1"-1u

I '"
T .ZS·C

H

I
II
•

~~~~:-cf

:...

1.1.2

'(LM1221i.1I322)

Comparator Blaa CUrrent

T.... 1Z1"e
TRIIIER "III"

'--

11 - - - nEDTOyt+_+--l
II

COIIPARATDR _UT VOLTAGE WI

COMPARATOR _UT VOL"S. tV)

TUHI7788-3

SUpply Current

,~

Tttgger Il'Iput Charactetlstlcs

u TttggarThreehold
,

r ... ·-src

/"

1

£

I
II

H

31

4D

I. I'
iI"
•

•

y'M

Output nana_ Satul'!'lkln

C_rIaIIce at Low Currenta

I
I

r--- rt'.. ·,zrc

I

•

'/

i ..

T,,--n

14111111'8"

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WORSTeASl!·....

32

I

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l

T.. -II-C

.1..1.

.

n

II'

,.

T1mlng Error Due to

I I

T·i'~"

I I
IJ

• ,.

I I

-15

TEMPIRATUIE ( CI

Comparetor alae Current

-=I\I~

Q., .... ,...,....,.;_C--:'._II.

,,"'-II C

IATURATIOI VOLTAGE .VI

.... ~

J.

Collector Output Saturation
Character1at1c8 at HIgh CUrrent

10'"

--.L
~

r---

t

T.. lln;

It

weRlTC."'"

r-..

T~''''.

1
"

I I

.....

1

TRlIIER VOLTADE IVI

I.

/

.-

...-

i ,..

Ta·zr

I
1/

,.

~

"

,"

11

I
I
" L-o'-JUL..LJJL..--II._.J.I

u

,.

1M

lATVIAn•• VOL 'AGE (VI

I.

,.

I'

nMINI IlEIIITDR lui

Reference Regulation
"Ji

Ii

i

11

'I 1

11

I~

...

j.~
'".-ere
T·i''!"

II

I
w

11

·11
·11

II

•

..

I

....... ~~Ie started by the trigger terminal as soon
as the ground is released. A switching transistor is best for
driving V ADJ to as near ground as possible. Worst case sink
current is about 300 pA

In this application the logic terminal is normally held high by
R3. When a trigger pulse is received, 01 is turned on, driving the logic terminal to ground. The result of triggering the
timer and reversing the logic at the same time is that the
output does not change from its initial low condition. The
only time the output will change states is when the trigger
input stays high longer than one time period set by Rt and
Ct. The output pulse width is equal to the input trigger width
minus Rt • Ct. C2 insures no output pulse for short « RC)
trigger pulses by prematurely resetting the timing capacitor
when the trigger pulse drops. CL filters the narrow spikes
which would occur at the output due to propagation delays
during switching.

A timing cycle may also be ended by a positive pulse to a
resistor (R :5; Rt/100) in series with the timing capacitor.
The pulse amplitude must be at least equal to V ADJ (2.0V),
but should not exceed 5.0V:When the timing capacitor discharges, a negative spike of up to 2.0V will occur across the
resistor, so some caution must be used if the drive pulse is
used for other circuitry.
TRI1~~~~ 0----,

SV Switching Regulator
Figure 13 is an application where the LM122 does not use
its timing function. A switching regulator is made using the
internal reference and comparator to drive a PNP transistor
switch. Features of this circuit include a 5.5V minimum input
voltage at 1A output current, low part count, and good efficiency (> 75%) for input voltages to 10V. Une and load
regulation are less than 0.5% and output ripple at the
switching frequency is only 30 mY. 01 is an inexpensive
plastic device which does not need a heatsink for ambient
temperature up to 50"C. Dl should be a fast' switching diode. Output voltage can be adjusted between 1V and 30V
by choosing proper values for R2, R3, R4, and R5. For outputs less than 2V, a divider with 250n Thevinin' resistance
must be connected between VREF and ground with its tap
point tied to VADJ.

LOGIC

r----o~-I·VREf

COLLECTOR

.....- - - - i R I C

IM/JTII1

VAD.I.

1-.....- _ - 0 · . 0 " '

GND

;;r

DlstRET

TRANStSTOR
OALOGI!:
GATE

TLlH/7768-25

FIGURE 14. Cycle Interrupt
The output of the timer can be wire ORed with a discrete
transistor or an open collector logic gate output. This allows
overriding of the timer output, but does not cause the timer
to be reset until its normal cycle time has elapsed.
Using the LM122 as a Comparator
A built-in reference and zero volt common mode limit make
the LM122 very useful as a comparator. Threshold may be
adjusted from zero to three volts by driving the V ADJ terminal with a divider tied to VREF' Stability of' the reference
voltage is typically ± 1 % over a temperature range of
- 55'C to + 125'C. Offset voltage drift in the comparator is
typically 25 /LVI'C in the boosted mode and 50 /LVrC unboosted. A resistor can be inserted in series with the input
to allow overdrives up to ±50V as shown in Figure 15.
There is actually no limit on input VOltage as long as current
is limited to ± 1 mAo The resistor shown contributes a worst
case of 5 mV to initial offset. In the unboosted mode, the
error drops to 0.25 mV maximum. The capability of operating off a single 5V supply with internal reference should
make this comparator very useful."

01

2M3.IO
FAST
RECOVERY

RIC

EMITTER
GNO

cz
.,1

'No. 22 Wire Wound on Molybdenum Permalloy Core

TLlHI776B-24

FIGURE 13. SV Switching Regulator with
1 Amp Output and S.SV Minlinum ,'nput

Application Hints

I

I

Aborting a Timing Cycle
TheLM122 does not have an input specifically allocated to
a stop-timing function. If such a function is desired, it may be
accomplished several ways:

•

• Ground VADJ
• Raise RIC more positive than VADJ
• Wire "OR" the output

4-205

I

Application Hints (Continued)
"high" is 2.SV. R2 may be calculated from the divider equation with R1 to give these levels.

'V",

NON-lrMIITI"

..

ALTERNATE
TRlaOU-

,-,

VAH

TII'GGE.
IIIPUT

You,

COLLECTOR

HI

_:J!-'VIi_t---+-f

HIC

+15V

-I t--+'-:----,
~
o.01"F

.,.

ov

-W..- 1

r.=~=-~~

AI
4.n:

.....

L....:.:j~...:;:.

1."

"Timer Protected
Against Damage.
for up to

VOUT
(d5V)

sov

TLlH/7768-26

FIGURE 1S. Comparator with OV to 3V Threshold
Eliminating Timing Cycle Upon Initial
Application of Power
The LM122 will normally start a timing cycle (with no trigger
input) when V+ is first turned on. If this characteristic is
undesirable. it can be defeated by tying the timing capaCitor
to VREF instead of ground as shown in Figuf'9 16. This connection does not affect operation of the timer in any other
way. If an electrolytic timing capaCitor is used. be sure the
negative end is tied to the RIC pin and the. positive end to
VREF. A 1.0 kO resistor should be included in series with the
timing capacitor to limit the surge current load on VREF
when the capacitor is discharged.

...._ _- - - -....- - _ -I&V

TLlH/7768-28

"Select tor Proper Level Shift
Emitter Termina' or Emitter Load must be Tied to GND Pin of Timer

FIGURE 17. Operating Off Dual Supplies
Linearizing the Charging Sweep
In some applications (such as a linear pulse width moduiator) it may be desirable to have the timing capaCitor charge
from a constant current source. A simple way to accomplish
this is shown in Figuf'9 18.
v"

V'

R3

. - -....--1 VREF
c,

.,

uw.
., ...._-I.,c

RI
COllECTOR

t---....

VOUT

R2

4.n

Uk

":"

t-_____... ~~~:,~N

TLlH17768-27

FIGURE 16. Eliminating Initial Timing Cyel.

TLlH/7768-29

Using Dual Supplies

FIGURE 18. Temperature Compensated
Linear Charging Sweep
Q1 converts the current through R1 to a current source independent of the voltage across Ct. R2. R3. 01. and 02 are
added to make the current through R 1 independent of supply variations and temperature changes. (02 is a low TC
type) 02 and R3 can be omitted if the V+ supply is stable
and 01 and R2 can be omitted also if temperature stability is
not critical. With 01. 02. R2 and R3 omitted, the current
through R1 will change about 0.01S%I'C with a 1SV supply
and 0.1 %I"C with a S.OV supply.

The L.M122 can be operated off dual supplies as shown in
Figuf'9 17. The only limitation is that the emitter terminal
cannot be tied to ground. it must either drive a load referred
to V- or be actually tied to V- as shown. Although capaci.
tive coupling is shown for the trigger input (to allow SV triggering). a resistor can be substituted for C1. R2 must be
chosen to give proper level shifting between the trigger signal and the trigger pin of the timer. Worst case "10" on the
trigger pin (with respect to V-) is 0.8V. and worst case

4-206

riI:

Application Hints (Continued)

C1 ;;;,

....
....r-

.,

Triggering with Negative Edge
Although the LM122 is triggered by a positive going trigger
signal, a differentiator tied to a normally "high" trigger will
result in negative edge triggering. In Figure 19, R1 serves
the dual purpose of holding the trigger pin normally high and
differentiating the input trigger pulse coupled through C1.
The timing diagram included with Agure 21 shows that triggering actually occurs a short time after the negative going
trigger, while positive going triggers have no effect. The delay time between a negative trigger signal and actual starts
of timing is approximately (0.5 to 1.5) (R1 • C1) depending
on the trigger amplitude, or about 2.5 to 7.5 ,..s with the
values shown. This time will have to be increased for Ct
larger than 0.01 ,..F because Ct is charged to VREF whenever the trigger pin is kept high and must reset itself during the
short time that the trigger pin voltage is low. A conservative
value for C1 is:

~
~

D.ODl

1-....- - ,

TRIGGER-----.J
INPUT.

iI:

+v"
V+
I

n,

I
I

iI:

0

(II

TUH/n68-30

FIGURE 19. Timer Triggered by Negative
Edge of Input Pulse
possible connections are shown. In both cases, the output
of the timer is low during the timing period so that the positive going signal at the end of the timing period can trigger
the next timer. There is no limitation on the timing period of
one timer with respect to any other timer before or after it,
because the trigger input to any timer can be high or low
when that timer ends its timing period.

Ct

Chain of Timers
The LM122 can be connected as a chain of timers quite
easily with no interlace required. In Figure 20A and 2OB, two
VOUTtn

VOUTI21

TUH/nS8-31

(a)
VOUTIU

----,
:
r...1--.L...,

or

I

t--+

r-l
I I

I

t-t

t-.,.-

I

I
I
I I
"--I
t-....
i l
I
I

1-

VQUl'"

L'--r.J ~
I

I

~
TL/H17768-32

U
"LJ OUTPUT I
Jl TRIGGER INPUT

~
~

....rW
CD

I

10

---,L._. . .

w

OUTPUTl
OUTPUT 2

L..J

n..______

(b)
FIGURE 20. Chain of Timers
4-207

TL/H/n68-33

IfINationa.' Semiconductor

I" • •

LM555/lM555C Timer
General Description
The LM555 is a highly stable device for generating accurate
time delays or oscillation. Additional terminals are provid,ed
for triggering or resetting if desired. In the time delay mode
of operation, the time is precisely controlled by one external
resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately
controlled. with two external resistors and one capacitor.
The circuit may be triggered,and reset on falling waveforms,
and the output circuit can source or sink up to 200 mA or
drive TTL circuits.

Features
• Direct replacement for SE555INE555
• Timing from microseconds through hours
• Operates in both astable and monostable modes

•
•
•
•
•

Adjustable duty cycle
Output can source or sink 200 rnA
Output. and supply TTL compatible
Teniperaturestability better than 0.005% per·C
Normally on and normally off output

Applications
•
•
•
•
•
•
•

Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Unear ramp generator

Schematic Diagram

•

v~o--------1~t-~--~t-----~t-------------------~~-----.~~----,

022

.11
&.2 •

•3
50

R8
Uk
THRESHOLD

8

CONTROL &
VOLTAGE

.N.

TRIGGER

••
50

1

3
OUTPUT

2

'S
Sk

DISCHARGE

7

TL/H/7851-1

4-208

!Ie
CII

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and spe~flcatlons.
Supply Voltage
+18V
Power pisSipation (Note 1) .
760mW
LM555H, LM555CH
LM555, LM555CN
1180mW
Operating Temperature Ranges
O"Cto +70'C
LM555C
-55·Cto + 125·C
LM555

Electrical Characteristics (TA =

-6S·C to + 1S0·C

Storage Temperature Range
Soldering Information
Dual-In-Une Package
Soldering (1 () Seconds)
Small Outline Package
Vapor Phase (60 Seconds)
Infrared (15 Seconds)

260"C
215·C
220"C

See AN-4S0 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

25·C, Vee == + 5V to + 15V, unless othewise specified)

Limits
Parameter

Conditions
Min

Supply Voltage
Supply Current

Timing Error, Monostable
Initial Accuracy
Drift with Temperature .

3
10·

RA = 1k to 100 kO,
C = 0.1 ~F, (Note 3)

RA, Rs = 1k to 100 kO,
C = 0.1 J.LF, (Note 3)

Accuracy over Temperature
Drift with Supply

...

Threshold Voltage
Trigger Voltage.

Max

Min

18

4.5

5
12

4.8
1.45

Reset Voltage

0.4

Reset Current
Threshold Current

(Note 4)

Control Voltage Leyel

Vee = 15V
Vee = 5V

9.6
2.9

Pin 7 Leakage Output High
Vee = 15V, 17 = 15 mA
Vee = 4.5V, '7 = 4.5 mA

4-209

Typ
3
10

Units
Max
16

V

6
15

mA
mA

0/0

0.5
30

1
50

ppml"C

1.5
0.05

1.5
0.1

O/ON

1.5
90

2.25
150

ppml"C

2.5
0.15

3.0
0.30

O/ON

0.667

x Vee

5
1.67

V
V

0.667
Vee = 15V
Vee = 5V

Trigger Current

Pin 7 Sat (Note 5)
Output Low
Output Low

Typ

4.5
Vee = 5V, RL '= 00
Vee '=15V, RL = 00
(Low State) (Note 2)

Accuracy over Temperature
Drift with Supply
Timing Error, Astable
Initial Accuracy
Drift with Temperature

LM555C

LM555

5
1.67

5.2
1.9

0.01

0.5

0.5

1

0.1

0.4

0.1

0.25

10
3.33

10.4
3.8

1
150
70

0/0

0/0

0/0

0.5

0.9

0.5

1

V

0.1

0.4

mA

0.1

0.25

j.t.A

10
3.33

11
4

V
V

100

1

100

nA

100

180
80

200

mV
mV

0.4

9
2.6

J.LA

CII

CII
.....
r-

~
CII
CII

~

Electrical Characteristics TA = 25°C, Vcc = + 5V to + 15V, (unless othewise sPecified) (Continued)
Limits
Parameter

Conditions

LM555
Min

= 15V
= 10 rnA
ISINK = 50 rnA
ISINK = 100 rnA
ISINK = 200'mA
Vcc = 5V
ISINK = 8mA
ISINK = 5mA
ISOURCE = 200 rnA, Vcc = 15V
ISOURCE = 100 rnA, Vee = 15V
Vee = 5V

Output Voltage Drop (Low)

LM555C

Typ

Max

0.1
0.4
2
2.5

0.15
0.5
2.2

0.1

0.25

Min

Units

Typ

Max

0.1
0.4
2
2.5

0.25
0.75.
2.5

0.25

0.35

Vee

ISINK

Output Voltage Drop (High)

13
3

12.5
13.3
3.3

12.75
2.75

V
V
V
V
V
V

12.5
13.3
3.3

V
V
V

Rise Time of Output

100

100

ns

Fall Time of Output

100

100

ns

Note 1: For operating at elevated temperatures the device must be derated above 25"C based on a
resistance of 164'c/w (TO·5), 10000c/w (DIP) and 170"c/w (SO·B) junction 10 ambient
Note 2: Supply CUrTent when output high typically 1 mA less at Vee
Note 3: Tested at Vee

= 5V and Vee =

+ 150"C maximum junction temperature and a thermal

= 5V.

15V.

Note 4: This will datermine the maximum value of RA + RB for 15V operation. The maximum Iotal (RA + RB) Is 20 MO.
Note 5: No protection against excessive pin 7 currant is necesssry providing the package dissipation rating will not be exceeded.
Note 8: Refer 10 RETS555X drawing of military LM555H and LM555J versions for specifications.

Connection Diagrams
Metal Can Package

Dual-In-Llne and Small Outline Packages

G¥Nl~
TRIGGER

~:

2

OUTPUT

3

.. _
4

7

BND

DISCHARGE

....!

11- '-'J

..!...



t
iii

Q.3

T--IS·C

0.2

0.1

~I:"

D.2

0.3

TA

u
1.2

J ..-

~~ ~ +12S·C

"

+ZIOt

./
TA -+1ZloC

~

0.8
D.&

11.4
0.2

sVfVC:C $ISV

a
S

0.4

~

15

10

110

11

SUPPLY VOLTAGE (V)

LOWEST VOLTAGE LEVEL Of TRIGGER PULSE (X Vc:cl

ISOURCE (mAt

Low Output Voltage vs
Output Sink Current

Low Output Voltage vs
Output Sink Current

Low Output Voltage vs
Output Sink Current

i,...-"

I

o
1.1

f--t!-~·C

1.6

10

10
Vee" 5V
-SS·C

1.0~.

1.0

~

'.1~.
10

0.1~.

100

10

1200

1210

Of
II:

] 1010

!

....

810

tY

4ID

o

"
•

0.1

:;:

Vee ~ 1.V, 15V

III I
0.2

+2~· cl~~v.

:a:

Vee" S.DV

210

+JO'C

>

:5 IDO

100

ISINIC (mA)

Discharge Transistor (Pin 7)
Voltage vs Sink Current

~

II:

611

o

0.3

LOWEST VOLTAGE LEVEL Of TRIGGER PULSE (X Vc:cl

~

;;

!

F-n

J

10

-55~l-

FF

o

lao

II:

VV

4DD

280

1810

I +125~C r,

Vee =11V

T"'+25'C

.,. llGO

lID

10

liD

Output Propagation Delay vs
Voltage Level of Trigger Pulse

Output Propagation Delay vs
Voltage Level of Trigger Pulse

"">

0.1

Iao.. (IIIAI

IstNIC(mA)

.....~
....:;:

J

1·1 I

8.1

0.3

0.2

0.1

LOWEST VOLTAGE LEVEL Of TRIGGER PULSE (X Vc:cl

1.0

10

100

I.NK (rnA) PIN 1

Discharge TranSistor (Pin 7)
Voltage vs Sink Current

1008 ~-§El_~

~ 111

II

!

J

10

1.0
0.01

0.1

1.0

10

lID

I... " latA) PIN 7

TL/H/7851-4

4·211

Applications Information
MONOSTABLE OPERATION
In this mode of operatio h', the timer functions as a one-shot
(Figl.!ft(J 1). Tt"\~ ext~rl1~1 capacitor is initially held discnarg~ -:" '."
by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 Vee to pin 2, the flip-flop is'
set which both releases tlie short circuit across tne capacitor and drives the output high.
+5V TO +1&V

NORMALLY
"ON"' LOAD

f ~. "

Figure 3 is a nomograph for easy determination of R, C
values for '(arious time delays.
NOTE: In monostable operation, the trigger should be driven high before the end of timing cycle. ,
l00r-.--.--r.-7r~~"n

+Vcc

10

R.
DISCHARGE

. RL

I

THRESHOLD

LM555

I
NORMALLY
"OFF" LOAD

When the reset function is not in use, it is recommended
that it be connected to Vee to aVO!d'any'jiossibility of false
triggering.
. -'
,
."

CONTROL
5 VOLTAGE

OUTPUT

C'

~

0~1~~~~~~~~~~

,~L

101'11001'11 ... 10 ... 100 ..., Ii' 10. 100.

Id - TIME DELAY
TUH17851-7

TUH17851-5

FIGURE 3; Time Delay'

FIGURE 1. Mon08table
The voltage l!-cross the capacitor then increases expon~n­
tiallyfor a penod of t = 1.1 RA C, at the end of, which time
the voltage equals 2/3
The comparator then resets
the flip-flop which in turn discharges the capacitor and,
drives the output to its low state. Figure 2 shows the wave- "
fonns generated in this mode of operation. Since the charge
and the threshold level of the comparator are both directly
proportional to supply voltage, the timing internal is independent of supply.

ASTABLE OPERATION
.
,
If the circuit is connected as shown 'Figure 4 (pihs 2 and 6
connected) it will trigger itself and free run':8S a multivibrator.
The E!xtemal capaCitor charges throuQh RA + Rs and discharges through Rs. Thus the duty cycle may be precisely
set by the ratio of these two resistors.

In

Vee.

II

I

r--------------~~------~t_-o+V~

I

I
I

I

I

,',:'

.R.

~RL
I

I
I

11
vee =

11

l-

1/

I

I

~RL

1/
TL/H17851-6 .

5V

TIME = 0.1 ms/DIV.
RA = 9.1 kG

R.
LMS55

C·

Top Trace: Input 5V1Div.
Middle Trace< Output 5V/Div.
Sottom Trace: CapaCitor Voltage 2V1Div.

C = 0.01 "F

TL/H17851-8

FIGURE 2. Monostable Waveforms
During the timing cycle when the output is high, the further
application of a trigger pulse will not effect the circuit so
long as the trigger input is returned high at least 10 /Ls bafore the end of the timing interval. However theeircuit can
be reset during this time by the application of a negative
pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is againappllecl..

FIGURE 4. Astable
In this mode of operation, the capaCitor charges and discharges between 1/3 Vee and 2/3 Vee- As in the triggered
mode, the charge and discharge times, and therefore the
freq\lency are independent of the supply voltage.

.

,.~

4-212

Applications Information (Continued)

I

Figure 5 shows the waveforms generated in this mode of
operation.

II

J

i1 J
~

,V

'"

-~

.......,

..... i'\.

V

/:

-

....... .......

I-

I

-

FIGURE 7. Frequency Divider
PULSE WIDTH MODULATOR
When the timer is connected in the monostable mode and
triggered with a continuous pulse train, the output pulse
width can be modulated by a signal applied to pin 5. Figure
8 shows the circuit, and in Figure 9 are some waveform
examples.

FIGURE 5. Astable Waveforms
The charge time (output high) is given by:
t1 = 0.693 (RA + RS) C
And the discharge time (output low) by:

r--~I----~""-o+vcc

t2 = 0.693 (RB) C
Thus the total period is:
T = t1 + t2 = 0.693 (RA +2RB) C
The frequency of oscillation is:

7 DISCHARGE

TRIGGER

1
1.44
f="T= (RA+2RB)C

THRESHOLD

LM55&

MODULATION
INPUT

Figure 6 may be used for qu'ick determination of these RC
values.
'

0=

II

IU

U

Tl/H17851-11

Top Trace: OulpuI5V1Div.
Bottom Trace: Capacitor Vo~age IVlDiv.

The duty cycle is:

II

~

vee ~ 5V
Top Trace:lnpuI4V/Div.
TIME ~ 20 ,../DIV, Middle Trace: OUlpul2V1Div.
AA ~ 9.1 kll
Bottom Trace: Capacitor 2V1Div.
C ~ O,OI"F

TUH17851-9

vee ~ 5V
TIME ~ 20 "s/DIV.
AA ~ 3.9 kll
AB ~ 3 kll
C ~ 0.Q1 "F

II

J

OUTPUT

RB
RA + 2Rs

100
TUH17851-12

10

FIGURE 8. Pulse Width Modulator

.
~

.;;
~

!u

..

~

v

f'"'.;

......

0.1

I

.. 0.01
0.001
0.1

10

100

I~

r In

10k IU.

I II

, f - FREE·RUNNING FREQUENCY (Hz)

TlIH17851-10

I

FIGURE 6. Free Running Frequency

vee ~

FREQUENCY DIVIDER
The monostable circuit of Figure 1 can be used as a frequency divider by adjusting the length of the timing cycle.
Figure 7 shows the waveforms generated in a divide by
three circuit.

II

, :n "

B D

I 'II II n
I :11 II n

TUH/7851-13

5V
TIME ~ 0.2 ms/DIV.
AA ~ 9.1 kll
C ~ 0.Q1 "F

Top Trace: Modulation IVlDiv.
Bottom Trace: OUtput Voltage 2V/Div,

FIGURE 9. Pulse Width Modulator
PULSE POSITION MODULATOR
This application uses the timer connected for astable operation, as in Figure 10, with a modulating signal again applied
to the control voltage terminal. The pulse position varies
with the modulating signal, since the threshold voltage and
hence the time delay is varied. Figure 11 shows the waveforms generated for a triangle wave modulation signal.

4-213

II

Applications Information

(Continued)

...---41-----+-0 +Vee

r--4....- -V;.:C:::.,C--4...._+-O+VCC
RI
TRIGGER

RZ

OUTPUT

OUTPUT

TL/H17851-16

TL/HI7851-14

FIGURE 12
Figure 13 shows waveforms generated by the linear ramp.
The time interval is given by:
T = 2/3Vcc Re(R, + R2lC .
R, Vee - VBe (R, + R2)
VBe "" 0.6V

FIGURE 10. Pulse Position Modulator

,/

v

i'..

vee = 5V
TIME = 0.1 ms/DIV.
RA = 3.9 kG
Re=3kG

C

.......

,/

V

~ /'"

r

I

I

w

i-

TUHI7851-15
Top Trace: Modulation Input lV1Dlv.
Bottom Trace: Output 2V1Dlv.

u
./

./

= O.Q1"F

'"

./

'"
TL/H17851-17

FIGURE 11. Pulse Position Modulator

Vee = 5V
Top Trace: Input 3V1Dlv.
TIME = 20 "s/DIV. Middle Trace: Output 5V/DIY.
R, = 47 kG
Bottom Trace: CapaCitor Voltage lV1DIY.
R2 = 100 kG

LINEAR RAMP
When the pullup resistor, RA, in the monostable circuit is
replaced by a constant current source, a linear ramp is generated. Figure 12 shows a circuit configuration that will perform this function.

Re = 2.7 kn
C = O.G1"F

FIGURE 13. Unear Ramp
50% DUTY CYCLE OSCILLATOR
For a 50% duly cycle, the resistors RA and RB may be
connected as in Figure 14. The time period for the out-

4-214

Applications Information (Continued)
put high is the same as previous, t1 = 0.693 RA C. For the
output low it is t2 =
[(RA Rs)/(RA

Note that this circuit will not oscillate if Rs is greater than
1/2 RA because the junction of RA and Rs cannot bring pin
2 down to 1/3 Vee and trigger the lower comparator.

+ Rs)] C in [=~s-_2::]

ADDITIONAL INFORMATION
Adequate power supply bypassing is necessary to protect
associated circuitry. Minimum recommended is 0.1 ,...F in
parallel with 1 ,...F electrolytic.

Thus the frequency of oscillation is f = _1_
t1 + t2

Lower comparator storage time can be as long as 10 ,...S
when pin 2 is driven fully to ground for triggering. This limits
the monostable pulse width to 10 ,...S minimum.
Delay time reset to output is 0.47 ,...S typical. Minimum reset
pulse width must be 0.3 ,...S, typical.
Pin 7 current switches within 30 ns of the output (pin 3)
voltage.

LM555

OUTPUT

C
D.O'.f

TL/H17851-18

FIGURE 14.50% Duty Cycle Oscillstor

4·215

or-------------------------~----------------------------~

{§,

::IE
.....

'U;
II)

tflN

a t ,i,eJ 11: a I "S e m j, con due tor

II)

::IE,

Timer'
.
..... LM556/LM556C'Dual
..'"
.
,

'

,,

General Description;"

", -

The LM556 Dual timing circuit'is '8 highly stable controller"
capable of producing accurate time delays or oscillation~
The 556 is a dual 555. Timing is provided by an external
resistor and capacitor for each timing' function. The two tirn.
ers operate independently of each othllf,sharing only Vee
and ground. The ci,rcuits may be triggered and reset on failing waveforms. The output structures may sink or source
200 mA.
' ,

Features
_
_
_
_

Direct replacement for SE556/NE556
Timing from microseconds through hours
Operates in both astable and monostable modes
Replaces two 555 timers

Adjustable duty cycle

- Output can source or sink 200 rnA
- Output and supply TTL compatible
- Temperature stability better than 0.005% per·C
- Normally on and normally off output

Applications
_
_
_
_
_
_
_

Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator

Schematic Diagram
114)

v~O-------~--t-----~~-----1~------------------~~--~'-~----~
oz.

Rl1
Uk

RJ

5k

R6

'5k
(ZIl Vcc::1

R'

::~::~I"='.':::1)--------+------'

5k

15.1)

,¥'---+--o OUTPUT

GNO 0------.,

171

TRIGGER 0-------1----1
(6.11

TL/H/7852-2

Connection Diagram
Dual-In-Llne and Small Outline Packages
Vee

DISCHARGE

Order Number LM556J or LM556CJ
See NS Package Number J14A

THRESH·
OLD

Order Number LM556CM
See NS Package Number M14A
Order Number, LM556CN
See NS Package Number N14A

DISCHARGE THRESH
OLD

CONTROL
VOLTAGE

RESET

OUTPUT

TRIGGER

GND

TUH11852-1

Top View
4-216

Absolute Maximum Ratings

Power Dissipation (Note 1)
LM556J, LM556CJ
LM556CN
Operating Temperature Ranges
LM556C
LM556

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor phase (60 seconds)
Infrared (15 seconds)

1785mW
1620 mW

Parameter

LM556

Conditions

Supply Voltage

Timing Error, MOl'lostable
Initial Accuracy
Drift with Temperature

Trigger Voltage

3
10

Vee = 5V, RL = 00
Vee = 15V, RL = 00
(Low State) (Note 2)

RA = 1kto 100 kO, C = 0.1IJ.F,
(Note 3)

RA, Rs'= 1k to·100 kO,
C = 0.1 IJ.F, (Note 3)

Min

18

4.5

5
11

O/ON

1.5
90
2.5
0.15

2.25
150
3.0
0.30

0.1

0.5

0.5

1

0.1

9.6
2.9

Pin 1, 13 Leakage Output High
(Note 6)
Vee = 15V, 1= 15 mA
Vee = 4.5V, I = 4.5 mA

4-217

mA
mA

1.5
0.1

0.4

Vee = 15V
Vee = 5V

V

6
14

1.5
0.05

(Note 4)

Control Voltage Level and
Threshold Voltage

16

0/0
ppmrC

5.2
1.9

VTH = V-Control (Note 5)
VTH = 11.2V

3
10

Units
Max

0.75
50

5
1.67

Threshold Current

Typ

0.5
30

4.8
1.45

Reset Current

Pin 1, 13 Sat
Output Low
Output Low

LM556C
Max

Vee = 15V
Vee = 5V

Trigger Current
Reset Voltage

Typ

4.5

Accuracy over Temperature
Drift with Supply
Timing Error, Astable
Initial Accuracy
Drift with Temperature
Accuracy over Temperature
Drift with Supply

215·C
220"C

25·C, Vee = + 5V to + 15V, unless otherwise specified)

Min

Supply Current
(Each Timer Section)

260"C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

o·cio +70"C
- 55·C to + 125·C

Electrical Characteristics (TA =

-65·Cto + 150"C

Storage Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
+18V

4.5
1.25

0/0

0/0
ppmrC
0/0

O/ON

5
1.67

5.5
2.0

V
V

0.2

1.0

IJ.A

0.5

1

V

0.4

0.1

0.6

mA

0.03

0.1
250

0.03

0.1
250

IJ.A

10
3.33

10.4
3.8

10
3.33

11
4

V
V

1

100

1

100

nA

150
70

240
100

180
80

300
200

mV
mV

0.4

9
2.6

nA

Electrical Characteristics (TA = 25°C, Vee = + 5V to + 15V, unk!Ss otherwise specified) (Continued)
Parameter

LM5~

Conditions
Min

Output Voltage Drop (Low)

>.

Output Voltage Drop (High)

Vee = 15V
ISINK = 10 mA
ISINK = 50mA
ISINK ~ 100 mA
ISINK = 200 mA
Vee = 5V
ISINK = 8mA
ISINK = 5mA
ISOURCE = 200mA, VCC
ISOURCE" 100 mA, Vee
Vee = 5V

= 15V
= 15V

13
3

LM556C

Typ ..

Max

0.1
0.4
2
2.5

0.15
0.5
2.25

0.1

0.25

12.5
13.3
3.3

Min

12.75
2.75

Units

Typ

Max

0.1
0.4
2
2.5

0.25
0.75
2.75

0.25

0.35

V
V
V
V
V
V

12.5
13,3
3.3

V
V
V

Rise Time of Output

100

100

ns

Fall Time of Output

100

100

ns

Matching Characteristics
(Note 7)
Initial Timing Accuracy
0.05
0.2
0.1
2.0
%
±10
±10
Timing Drift with Temperature
ppml"C
Drift with Supply Voltage
0.1
0.2
0.2
0.5
%IV
Note 1: For operating at elevated temperatures the device must be derated based on a + 150'e maximum Junction temperature and a thermal resistance of
70'C/W (Ceramic), 7rC1W (Plastic DIp) and I100CIW (SO-14 Narrow).
Note 2: Supply current when output high typically 1 mA less at Vee = 5V.
Nota 3: Tested at Vee = 5V and Vee = 15V.
Nota 4: As reset voltage lowers, timing is inhibited and then the output goes low.
Note 5: This will determine the maximum value of RA + RB for 15V operation. The maximum total (RA + RB) is 20 Mil.
Nota 6: No protection against excessive pin I, 13 current Is nepessary providing the package dissipation rating will not be exceeded.
Note 7: Matching characteristics refer to the difference between performance characteristics of each timer section.
Note 8: Refer to RETS556X drawing for specifications of military LM556J version.

4-218

Typical Performance Characteristics
Supply Current vs Supply
Voltage (Each Section)

Minimum Pulse Width
Required for Triggering
u
Vee -15V

1.1

1
~
I

IZ

U

10

T a.,n"c

!.:
1.7

I ...
I ~!
I~

!

'-L.oI

B

i

T--H'C

1.1

...

o.z

~E:

~~ +25"C

i.

T-+~JC:-'

1.1

-55'C

~~

1.1
1.1
1.4

E

J

~~ ~ +IZ5'C

I.Z

I

~

D.I
l1.li

D.'
D.Z
I

D

II

5

LIlllEIT VOLTAGE LEVEL OF TRIOGER .vUE IX Veel

15

SUPPLY VOLTAGE IVI

lo~a

T.· +25"C

-

~

TA -+IZS"C

I

IV~VeeSI5V

10
IM)UIIJCI

«mAl

Low Output Voltage vs
Output Sink Current

Low Output Voltage vs
Output Sink Current

Low Output Voltage vs
Output Sink Current

High Output Voltage vs
Output Source Current
],l-i)_~LC

II~ii

II

I.D8§.

1m
II

lUi

~C-~~~~~LU~

I.D

ID

_InIAl

1210
, '"+21"C

>

110

..
....~ oaa

Vee - 5.DV

110

:f
IE

I

Vee ""IV

AI...

~~

ZID

o
D

1.1

0/
'0/0/

V~-lav.15V

Discharge Transistor
(Pin 1, 13)
Voltage VB Sink Current

..
.... oaa

D

~

~

.

S 100

+Z~·/,~ ~

E

j

'I

~
:f
If zoo

D.3

lUlU
+12&"C

+10·C ...

IOU

IS

III

N

o.z

>

:5

~

'I

r<-; !rIC

i

I•

>

i55,c I

•

D.3
U.2
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE IX Veel

Lawm VOLTAGE LEVEL OF TRlGBER PULSE IX Veel

IIG

ISiNK (iliA)

Output Propagation Delay vs
Voltage Level of Trigger Pulse

IZII

A 1110
IS

ID

IGU

I..,.KlntA)

Output Propagation Delay vs
Voltage Level of Trigger Pulse

:5

D'I~.

D.I~.

I'I~.

D.I

I.D

ID

lID

IIiNK hnA) ptN 1.13

Discharge Transistor (Pin 1, 13)
Voltage vs Sink Current

.

II

:: III

i!

I

i

>

I
1.1

1.1

II

".lmAII'tNI.13

4-219

110
TLlH/7852-3

or---------------~----------------------------------~

CD

~

t!fINational Semiconductor
,';"',

LM566Cyoitage Controlled Oscillator
General Description
The LM566CN is a general purpose voltage controlled oscil· '
lator which may be used to generate square and triangular
waves, the frequency of which is a very linear function of a
control voltage. The frequency is also a function of an exter·
nal resistor and capacitor.
The LM566CN is specified for operation over the &C to
+ 70"C temperature range.

Features

•
•
•
•

High temperature stability
~cellent supply voltage rejection
,1 0 to 1 f~equency range with fbeed capacitor
, '
Frequency programmable,by means of current, voltage,
, resist()r qr capacitor
' ,

Applications
•
•
•
•

FM modulation
Signal generation
Function generation
Frequency shift keying
To'ne generation

• Wide supply voltage range: 1OV to 24V
• Very linear modulation characteristics

III

Connection Diagram

Typical Application

Du~I.ln.Llne Package
BND

,.

1 kHz and 10 kHz, TTL Compat'ble
Voltage Cont~olled Oscillator
6V

• Vee

7 TIMING CAPACITOR ,
SQUARE WAVE
OUTPUT

6 TIMING RESISTOR

TRIANGLE
WAVE OUTPUT

MODULATION
INPUT

.",-+.....---!l
"k4~.c'7nr
"'7~r
2N2222

'"

, T,UHI7854-2

Order,Number LM566CN
See NS Package Number N08E

..,

....7114

~3V fOR 1kHz
-SYfw 10kHz

CON""
'.,. , L--~--""':'-c:-Jr'
3VlO5.!lV

I~~-------~~~~~~
0IJ1PIIT
'--~::::"'--------'----<: 0IJ1PIIT
~'=A""
TL/HI7854'-3

4-220,

,-----------------------------------------------------------------------------'r!!Ii:
Absolute Maximum Ratings

8:

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Supply Voltage
Power Dissipation (Note 1)
Operating Temperature Range, LM566CN
Lead Temperature (Soldering, 10 sec.)

26V
1000 mW
O'C to + 70'C
+ 260'C

Electrical Characteristics Vee =
Parameter

~

12V, TA = 25'C, AC Test Circuit
LM566C

Conditions
Min

Typ

Maximum Operating
Frequent::y

RO = 2k
CO = 2.7pF

0.5

1

veo Free-Running

Co = 1.5nF
Ro= 20k
fo = 10 kHz

-30

0

Frequency

%Vee

Input Voltage Range Pin 5
Average Temperature Coefficient
of Operating Frequency
Supply Voltage Rejection

Units
Max
MHz

+30
Vee

ppml'C

200
10-20V

0.1

Input Impedance Ph, 5
VCO Sensitivity .

For Pin 5, From
B-10V, fo = 10 kHz

FM Distortion

±100/0 Deviation

2

0.5

1

6.0

6.6

7.2

0.2

1.5

Maximum Sweep Rate

O/ON
MO

1

Sweep Range

0/0

kHzN
0/0
MHz

10:1

Output Impedance
Pin 3

0

50

Pin4

50

0

Square Wave Output Level

RLl = ,10k

5.0

5.4

Vp-p

Triangle Wave Output Level

RL2 = 10k

2.0

2.4

Vp-p

40

50

Square Wave Duty Cycle

60

0/0

Square Wave Rise Time

20,

ns

Square Wave Fall Time

50

ns

Triangle Wave Linearity

+ 1V Segment at
0.5
0/0
% Vee
Note 1: The maximum iunction temperature of the LM566CN is 150'C, For operation at elevated iunction temperatures, maximum power dissipation must be
derated based on a thennal resistance of 115'C/W, iunClion to ambient.

Applications Information
The LM566CN may be operated from either a single supply
as shown in this test circuit, or from a split (±) power supply. When operating from a split supply, the square wave
output (pin 3) is TTL compatible (2 mA current sink) with the
addition of a 4.7 kO resistor from pin 3 to ground.

A 0.001 ,..F capacitor is connected between pins 5 and 6 to
prevent parasitic oscillations that may occur during veo
switching.
fO =

2.4(V+ - Vs)
ROCoV+

where
2K

Triangle Wave Output
Characteristics

2.3

3.

Square Wave Output
Characteristics

.
~.
..

./

-0.7

R., PIN ITO GROUND Inl

r-

+I

2w

~

-0.5
-0.8

11110

~I/I

To - II·C
AC TEST CIRCUIT

7.0

o

.....

...~

+12

Ll
i/I'\.l L JL

wt_

-0.4

!

+,

25 50 1i 100 125

-8.3

i..

..
.. '" '"
...

Frequency Stability vs Load
Impedance (Triangle Output)

-0.1
-0.2

..

.51.01.12.02.53.0

!\:

+0.2
+0.1

AC TEST CIRC UIT
T,,= 25·C
Ru- 11K

100

~

.S

TEMPERATURE (·CI

SUfI'LV VOLTAGE (VI

Frequency Stability vs Load
Resistance (Square Wave
Output)

""

CONTROL VOLTAGE IV. - V.ICVI

~~

+••

-2.5
-15 -10 -25 0

5

~

II

ID"

~

I ~:::-2.'

.0

15

ID"

~r::;:::

!; -0.&

10

10'

~ 1.5

II
>

II'

AC TEST.CIRCUIT

z.a
Ii;

ii

Temperature Stability
u

MAXIMUM

~

~ 1.0

FREQUENCV (Hz!

10

.!

1.'

It
I

NORMALIZED FREIIUENCV

~

;

.DIIII

.0

1.1

f,,-we
AC TEST CIRCUIT

i

i\.

;5

UK

Normalized Frequency as a
Function of Control Voltage
1.0

l,,-2I°C
AC TUT C.RCUIT

o

101<4

2.1

AC TEST CIRCU.T

:i

l.5kD.

To-WC

z.a

lID

Ik

SOU.RED-1---"f-C::'

WA.VE OUTPUT

Ilk

RLI PlU TOBROUND Inl
10kA

TL/HI7854-5

TL/HI7854-6

4-223

--

~~

. PRELIMINARY' ,

/fINational Semiconductor

""t'

LMC555 CMOS Timer
General Description .

Features

The LMC555 is a CMOS version of the industry standard
555 series general purpose timers. It offers the same 'capa; .
bility of generating accurate time delays and frequencies but
with much lower power dissipation and supply current
spikes. When operated as a one-shot, the time delay is pre:
cisely controlled by a single external resistor and capacitor.
In the astable mode the oscillation 'frequency and duty cycle
are accurately set by two external resistors and one capacitor. The use of National Semiconductor's LMCMOSTM process extends both the frequency range and low supply capability.

•
•
•
•

Less than 1 mW typical.power dissipatiqn at 5V supply
3 MHz astable frequency ~pabilitY
'.
1.5V supply.operating voltage guaranteed
Output fully compatible with TTL and CMOS logic at 5V
.
supply

•
•
•
•
•

Tested to -10 mA, +50 mA output current levels
Reduced supply current spikes during o~tput transitions
Extremely low reset, trigger, and threshold currents
Excellent temperature stability
Pin-for-pin compatible with 555 series of timers '

Block and Connection Diagrams
GROUND

--+---,

LMC555

8

r-------,;-;......;,. v+
R

=IOOkA
R

2

'7·

,..---+-. D!SC~GE

TRIGGER --+------~-.

6

L....--_-t--

OUTPUT

RESET

THRESHOLD

--+-----'
TUH/8669-1

(Pinouts for Molded and Metal Can Packages are identical)

Order Number LMC555CH, LMC555CM or LMC555CN
See NS Package Number H08C, M08A or N~E

4-224

r-

I:

oen

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V8

15V

Input Voltages, V2, V4, V5, VS

-0.3V to Vs + 0.3V

Output Voltages, V3, V7

15V

Output Current 13, 17

-40"Cto +85'C·

Storage Temperature Range

-S5'C to + 150'C

Electrical Characteristics Test Circuit, T =
Symbol
18

V5

Parameter
Supply Current

Control Voltage

2SO"C
215'C
220"C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

100mA

Operating Temperature Range (Note 1)

en
en

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (SO seconds)
Infrared (15 seconds)

25'C, all switches open, FiESEi to Vs unless otherwise noted

Conditions

Min

Vs = 1.5V
Vs = 5V
Vs = 12V
Vs = 1.5V
Vs = 5V
Vs = 12V

0.8
2.9
7.4

Typ

Max

Units
(Limits)

50
100
150

150
250
400

/LA

1.0
3.3
8.0

1.2
3.8
8.S

V

V7

Discharge Saturation
Voltage

Vs = 1.5V, '7 = 1 mA
Vs = 5V, 17 = 10 mA

75
150

150
300

mV

V3L·

Output Voltage
(Low)

Vs = 1.5V, '3 =1 mA
Vs = 5V, 13 = 8 mA
Vs = 12V, '3 = 50 mA

0.2
0.3
1.0

0.4
O.S
2.0

V

Output Voltage
(High)

Vs = 1.5V, '3 = -0.25 mA
Vs = 5V, 13 = -2mA
Vs = 12V, '3 = -10 mA

1.0
4.4
10.5

1.25
4.7
11.3

V2

Trigger Voltage.

Vs =' 1.5V
Vs = 12V

0.4
3.7

0.5
4.0

12

Trigger Current

Vs = 5V

V4

Reset Voltage

Vs = 1.5V (Note 2)
Vs= 12V

0.4
0.4

0.7
0.75

V3H

V
O.S
4.3

pA

10
1.0
1.1

14

Reset Current

Vs = 5V

10

IS

Threshold Current

Vs = 5V

10

17

Discharge Leakage

Vs = 12V

1.0

100

t

Timing Accuracy

SW 2, 4 Closed
Vs = 1.5V
Vs = 5V
Vs = 12V

1.1
1.1
1.1

1.25
1.20
1.25

0.9
1.0
1.0

V

V
pA
pA
nA

ms

0.3

%/V

75

ppml"C

atlaVs

Timing Shift with Supply

Vs=5V±1V

atlaT

Timing Shift with
Temperature

Vs = 5V
- 4O"C s: T

fA

Astable Frequency

SW 1, 3 Closed
Vs = 12V

fMAX

Maximum Frequency

Max. Freq. Test
Circuit. Vs = 5V

3.0

MHz

tR, tF

Output Rise and
Fall Times

Max. Freq. Test Circuit
Vs = 5V,CL = 10pF

15

ns

s:

+ 85'C

Trigger Propagation Delay

4.0

4.8

5.S

kHz

Vs = 5V, MeasurE! Delay
100
ns
from Trigger to Output
• Refer to RETSC555X drawing for specifications of military LMC555H version.
Note 1: For operation at elevated temperatures, the device must be derated basad on a 150"C maximum iunction temperature and a thermal resistance of
111'C/W for the LMC555CN, 167'C/W for the LMC555CH, and 169'C/W for the LMC555CM. Maximum allowable dissipation at 25'C is 1126 mW for the
LMC555CN, 755 mW for the LMC555CH, and 740 mW for the LMC555CM.
Note 2: tf the RESET pin is to be used at temperatures of -WC and below Vs is required to be 2.0V or greater.
tpD

4-225

U)
:g

r---~----------------------------------------------------------------------------'

Test Circuit

o

:I

Maximum Frequency Te!tt Circuit
8

...........- - . -....-0 Vs
TRIGGER

:slf

-=

470
·2

.:c O.II'F

-=..

+
VS

.1-

7
200

OUTPUT
3

OUTl'UT

I

LWC555
5

4

Vs

RESET

2°O PF

Io.o01 1'F
TL/H/8669-3

TL/H/8669-2

Typical Applications
Variable Duty Cycle Oscillator

Monostable (One·Shot)

Vs

8

-U

:c. 0.1!'F

R,\

TRIGGER

~TPUT

2

7

3

6

(Vs)

7~------'

OUTPUT

-IltilRESET

2
3

Ie

LWC555
4

LMC555
RESET

5

(Vs)
TL/H/8669-5

TLlH/B669-4

tH

= 1.1

1.44
fose. = (RA + 2Ra)C

RAC (Gives time that output is high following trigger)

l'iEm overrides ~,

which can ovenide THRESHOLD. Therefore,
the trigger pulse must be shorter than tha desired Iii.

Rs

Duty Cycle

The minimum trigger pulse width is 20 ns.
The

~inimum

= RA + 2Re

(Gives fraction of total period
that outpuU~ low)

reset pulse width is 400 ns.

50% Duty Cycle Oscillator

8 t - -.....- -....--o Vs

7 t - - - - -...

2

ALTERNATE
OUTPUT

OUTPUT

RC.

1

fose = 1.4RcC
TL/H/866S-6

4·226

tflNational Semiconductor

MM5368 CMOS Oscillator Divider Circuit
General Description

Features

The MM5368 is a CMOS integrated circuit generating 50 or
60 Hz. 10Hz. and 1 Hz outputs from a 32 kHz crystal
(32.768 Hz). For the 60 Hz selected output the input time
base is divided by 546.133. for the 50 Hz mode it is divided
by 655.36. The 50/60 Hz output is then divided by 5 or 6 to
obtain a 10Hz output which is further divided to obtain a
1 Hz output. The 50/60 Hz select input can be floated for a
counter reset.

•
•
•
•
•
•
•
•

50/60 Hz output
1 Hz output
10Hz output
Low power dissipation
Fully static operation
Counter reset
3.5V-15V supply range
On-chip oscillator-tuning and load capacitors are the
only required external components besides the crystal.
(For operation below 5V it may be necessary to use an
- 1 MO pullup on the oscillator output to insure startup.)

Block and Connection Diagrams

~VDD

1M

1;8 PF
DECODE
1...._ _ _ _ _ _ _~~---+1 50/60 Hz
r
OUTPUT

&

SELECT
LOGIC

310Hz
OUTPUT
41Hz
OUTPUT
COUNTER RESET
(ON·CHIPI

TUF/6133-1

FIGURE 1
Dual-In-Line Package
50160 Hz OUT

VDD

Vss

50160 Hz SEL ECT

Order Number MM5368N
See NS Package Numbar N08E
OSC IN

1 Hz OUTPUT

4.

OSC OUT
TUF/6133-2

Top View '
FIGURE 2

4-227

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
-0.3V to Voo, + 0.3Y

16V

, Maxilnum Voo Voltage
Operating Voo Range
Lead Temperature (Soldering, 10 sec.)

3.5V';; Voo

~

15V
300'C

O'C to + 70'C
-65'C to + 150'C

Operating Temperature
Storage Temperature

Electrical Characteristics TA within operating ~ange, Yss =
Parameter

OV' .
Min

. Max,

. Units

10

p.A

fiN = 32 kHz, Voo ",; 3.5V
fiN = 32 kHz, Voo == 15V

60
1500

p.A

Maximum Input Frequenqy

Voo = 3.5V
Voo = 15V

64
500

kHz
kHz

Output Current Levels
Logical "1", Source
Logical "0", Sink

Voo"
VOH =
VOL =
Voo =
VOH =
VOL =

-400

p.A
p.A

-1500

p.A

Conditions

Quiescent Current Drain

Voo = 15V; 50/60 Select Floating

Operating Current Drain

Logical "1", Source
Logical "0", Sink
Input Current Levels
Logical "1" (IIH)
Logical "1" (IIH)
Logical "0" (IIU
Logical "0" (IIU

51/
Vss + 2:7V
Vss + 0.4V
9V
Vss + 6.7V
Vss + O.4V

Typ

400

1500

p.A

p.A

50/60 Select Input (Note 1)
Voo = 3.5V, VIN ~" 0.9 Voo
Voo = 15V, VIN ~ 0.9 Voo
Voo == 3.5V,VIN ~O.1 Voo
Voo = 15V, VIN ~ '0.1 Voo

50
3
20

p.A
mA
p.A
mA

Note 1: The input currant level test is performed by first measuring thaopen circuit voltage at the 50/60 Hz select pin. If the voltage is "high". make the IIH test. If
the voltage Is "low". make the IlL test The state of the 50160 Hz select pin may be changed by applying a pulse to esc IN .(pIn 6) while the 50/60 Hz pin is open
circuit.

Functional Description (Figure 1)
The MM5368 initially divides the input time base by 256.
From the resulting frequency (128 Hz for 32 kHz crystal) 8
clock period.s ar,e dropped or eliminated during 60 Hz operation and 28 clock periods are eliminated during 50 Hz operation. This frequency is then divided by 2 to obtain a 50 or
60 Hz output. This output is not periodic from cycle to cycle;
however, the waveform repeats itself every second. Straight
divide by 5 or 6 and 10 are used to obtain the 10Hz output
and the 1 Hz outputs.
The 60 Hz mode is obtained by tying pin 7 to Voo. The
60 Hz output waveform can be seen in Figure 3. The 10Hz

and 1 Hz outputs have an approximate 50% duty cycle. In
the 50 Hz mode the 50/60 select input is tied to VSS. The
50 Hz output waveform 'can be,seen in Figure 3. The 10Hz
output has an approximate 40% duty cycle and the 1 Hz
output has an approximate 50% duty cycle.
For the 50/60 Hz select input floating, the counter chain is
held reset, except for the initial toggle flip-flop which is
needed for the reset function. A reset may also occur when
the input is switched (Rgum 4). To insure the floating state,
current sourced from the input must be limited to 1.0 p.A and
current sunk by the input must be limited to 1.0 p.A for
Voo = 3.5V.

Timing Diagrams
60 Hz
OUTPUT
I

7.8m.-:
'1

I
I
I

50 Hz
OUtpUT

I
1-

:
:

L{

PHASE SHIFTED EVERY 8 CLOCKS DUE TO
ELIMINATION OF 1 INPUT CLOCK (i •••• 121 Hz CLOCK)

{

.

1 CLOCK DROPPED
rEVERY 5 128 Hz CLOCKS

L{

T.IM~ISEC

PHASE SHIFTED 3
DUE TO ELIMINATION OF 3
128 Hz CLOCKS
.

FIGURE 3. 50/60 Hz Output
4-228

}~

TLlF/6133-3

Timing Diagrams (Continued)
16kHz

FLOATING

~_---,r

INPUT _ _ _....
RESET _ _ _ _.....

. - -- ----- ---

'"'---_---InL._ _.....

50/60

SELECT _ _ _...I

TL/F/6133-4

Voo

TUF/6133-5

FIGURE 4. SO/60 Select and Reset

Typical Applications
RESET

LATCH

voo

r----.----------l'1 vu

NSB7B61
15
16

11

"""536B 10 Hz 1"3_ _ _ _1""12

L..._~~_~

OSC IN

MM74CI27

1Hz

'If the crystal used is a microwatt type an
R value will be required to limit power to
the crystal.
R~O

3.SV
SV

R

~

fOV

R

~

lOOK
330K

TLlF/6133-6

FIGURE 5. 10 Minute (9:59.9) Timer

•
4·229

$

!

t!lN4tion41 Semiconductor

MM5369 17 Stage Oscillator/Divider
General Description

Features

The MM5369 is a CMOS integrated'circuit with 17 binary
divider stages that can be used to generate a precise reference from commonly available high frequency quartz crystals. An internal pulse is generated by mask programming
the combinations of stages 1 through 4, 16 and 17 to set or
reset the individual stages. The MM5369 is advanced one
count on the positive transition of each clock pulse. Two
buffered outputs are available: the cyrstal frequency for tuning purposes and the 17th stage output. The MM5369 is
available in an 8-lead dual-in-line epoxy package.

• Crystal oscillator
• Two buffered outputs
Output 1 crystal frequency
Output 2 full division
• High speed (4 MHz at Voo = 10V)
• Wide supply range 3V -15V
• Low power
• Fully static operation
'. 8-lead dual-in-line package
• Low Current

Option
3.58 MHz to 60 Hz

• MM5369AA

Connection and Block Diagrams
Dual-In-Une Package

OSC OUT

TUNER
OUTPUT OSC OUT OSC IN

1B

7

5

6

OSC IN

DIVIDER
OUTPUT

TUNER

-

OUTPUT

-

TL/F/l0820-2

FIGURE 2

1
DIVIDER
OUTPUT

2
Vss

P

NC

14
NC

DIVIDER
OUTPUT

14

NC

113

NC

112

TUNER
OUTPUT OSC OUT

HC

111

8

9

10

TLlF/l0820-1

Top View
Order Number MM5369AAlN
See NS Package Number
N08E

-

'-

-

1
Vss

12
HC

P

NC

14
HC

15
HC

16

NC

7
OSC IN
TLlF/l0820-8

Order Number MM5369AA/M
See NS Package Number M14A

4-230

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin

-0.3V to Voo

Package Dissipation

Storage Temperature

16V
3Vt015V

Operating Vee Range

+ 0.3V

Lead Temperature (Soldering, 10 seconds)

ODC to + 70"C
- 65DC to + 150"C

Operating Temperature

500mW

Maximum Vee Voltage

300"C

Electrical Characteristics
TA within operating temperature range, Vss = GND,3V ,;;; Voo ,;;; 15V unless otherwise specified.

Parameter

Min

Conditions
Voo = 15V
Voo = 10V, fiN = 4.19 MHz

Frequency of Oscillation

Voo = 10V
Voo = 6V

DC
DC

1.2

2.5

mA

4.5

MHz
MHz

Units

2

Voo = 10V
Vo= 5V
500
500

Logical "1" Source
Logical "0" Sink
Output Voltage Levels

Max
10

Quiescent Current Drain
Operating Current Drain

Output Current Levels

Typ

Voo = 10V
10 = 10 ",A

Logical "1"
Logical "0"

9.0

V
1.0

V

Nota: For 3.58 MHz operation, voo must be ;, 10V.

Functional Description
A connection diagram for the MM5369 is shown in Figure 1
and a block diagram is shown in Figure 2.

DIVIDER
A pulse is genertaed when divider stages 1 through 4, 16
and 17 are in the correct state. By mask options, this pulse
is used to set or reset individual stages of the counter. Figure 4 shows the relationship between the duty cycle and the
programmed modulus.

TIME BASE
A precision time base is provided by the interconnection of
a 3,579,545 Hz quartz crystal and the RC network shown in
Figure 3 together with the CMOS inverter/amplifier provided
between the OSC IN and the OSC OUT terminals. Resistor
R 1 is necessary to bias the inverter for class A amplifier
operation. Capacitors C1 and C2 in series provide the parallei load capaCitance required for precise tuning of the quartz
crystal.

OUTPUTS
The Tuner Output is a buffered output at the crystal oscillator frequency. This output is provided so that the crystal
frequency can be obtained without disturbing the crystal oscillator. The Divide Output is the input frequency divided by
the mask programmed number. Both outputs are push-pull
outputs.

The network shown provides> 100 ppm tuning range when
used with standard crystals trimmed for CL = 12 pF. Tuning
to better than ± 2 ppm is easily obtainable.

4-231

Functional Description (Continued)

'-

110
'100

'\

OSC IN --~.,.- - - - - -,--,,..,
,..,.--

i;

8.

Rl

~ ~ Cl

'7 ~ 5-36pF
Voo OR

20M

r;;

1.. 1

:!l

3.579~~MHZ

~~
T

'CL = 12pF

---------......1

VSS (10V) _ .....

I

90

- - OSC OUT

~

Q

C2
30pF
TL/F/10820-3

'To be selected besed on xtal used

80
70
60
50
.010
30
20
10
0
0

If

/
~

~

~"

-

~

V

"I,'

~

,;.. ~

20 ,30

10

DUTY

FIGURE 3. Crystal Oscillator Network

.010

CYCL~

50

V
60

70

(%)
TL/F/10820-4

FIGURE 4. Plot of Divide-By vs:Duty Cycle

2.5

&>'

~----,r-

1,-,

I

"

~

"

2.0

1.5

26,875
COUNTS '

I

••

32~784.

COUNTS

59,659 COUNTS

It)

TL/F/10820-6

~

FIGURE 6. Output Waveform for the MM5369AA'

j!l 1.0
0.5
0
0

1

2

3

4

'5

14Hz
TUF/10820-5

FIGURE 5. Typical Curren~ ~raln
vs Oscillator Frequency

: 'I

4-232

.-------------------------------------------------------------------------,~

....
....

i:

co

tflNational Semiconductor

CI1

LM1851 Ground Fault Interrupter
General Description

Features

The LM1851 is designed to provide ground fault protection
for AC power outlets in consumer and industrial environments. Ground fault currents greater than a presettable
threshold value will trigger an external SCA-driven circuit
breaker to interrupt the AC line and remove the fault condition. In addition to detection of conventional hot wire to
ground faults, the neutral fault condition is also detected.
Full advantage of the U.S. UL943 timing specification is taken to insure maximum immunity to false triggering due to
line noise. Special features include circuitry that rapidly resets the timing capacitor in the event that nOise pulses introduce unwanted charging currents and a memory circuit that
allows firing of even a sluggish breaker on either half-cycle
of the line voltage when external full-wave rectification is
used.

•
•
•
•
,.

Internal power supply shunt regulator
Externally programmable fault current threshold
Externally programmable fault current integration time
Direct interface to SCA
Operates under line reversal; both load vs line and hot
vs'neutral
• Detects neutral line faults

Block and Connection Diagram
Vee

SCR
TRIGGER

TIMING
CAPACITOR

INVERTING
INPUT

SENSITIVITY
SET RESISTOR

NON·INVERTING
INPUT
TOP VIEW

Order Number LM1851M or LM1851N
See NS Package Number M08A or N08E

4-233

SENSE AMPLIFIER
OUTPUT

GNO
TL/H/5177-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Current
19mA
Power Dissipation (Note 1)
1250mW
Operating Temperature Range
-40'C to + 70'C
Storage Temperature Range
-55'Cto + 150'C

DC Electrical Characteristics
Parameter

Soldering Information
Dual-In-Line Package (10 sec.)
260'C
Small Outline Package
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
See AN-450 "Surface Mounting and Their Effects on Product Reliability" for other methods of soldering surface
mount devices.

TA= 25'C, 155= 5 mA
Conditions

Power Supply Shunt
Regulator Voltage

Pin 8, Average Value

Min

Typ

Max

Units

22

26

30

V

20

V

Latch Trigger Voltage

Pin7

15 '

Sensitivity Set Voltage

Pin 8to Pin 6

6

17.5 .
7

8.2

V

Output Drive Current

Pin 1, With Fault

0.5·

1

2.4

mA

Output Saturation Voltage

Pin 1, Without Fault

100

240

mV

100

0
mA

Output Saturation Resistance

Pin 1, Without Fault

Output External Current
Sinking Capability

Pin 1, Without Fault,
Vpin 1 Held to 0.3V (Note 4)

2.0

5

Noise Integration
Sink Current Ratio

Pin 7, Ratio of Discharge
Currents Between No Fault
and Fault Conditions

2.0

2.8

3.6

pA/poA

Min

Typ

Max

Units

3

5

7

mA

AC Electrical Characteristics TA = 25'C, iss = 5 mA
Parameter

Conditions

Normal Fault Current
Sensitivity

Figure 1 (Note 3)

Normal Fault Trip Time

5000 Fault, Figure 2 (Note 2)

18

ms

5000 Normal Fault,
Normal Fault with
18
ms
Grounded Neutral Fault
20 Neutral, Figure 2 (Note 2)
Trip Time
Note I: For operation in ambient temperatures above 25"C, the d!>Vlce must be derated based on a 125"C maximum junction temperature and a !hennal resistance
of 80'C/W junction to ambient for the DIP and 162!'C/W for the SO Package.
Note 2: Average of 10 trials.
Note 3: Required UL sensitivity tolerance is such thet external trimming of LMI851 sensitivity will be necessary.
Note 4: This externally applied current is in addition to the internal "oulput drive current" source.
7 TIMING
CAP

~

-IN Z

I ICR
TRIGGER
LMIIII
OP_
OUTPUT ..

..!.

..!!L.
=,::~

Ik

~ :-...v

8

I

+IN

llIIIk

I

.!..

Ran L -

Vce

Dj7jAf

"'Hz '"

GND •
I.IM

---3IV

T
TUH/SI77-2

FIGURE 1_ Normal Fault Sensitivity Test Circuit

4-234

Internal Schematic Diagram

TL/H/51n-3

4-235

Typical Performance Characteristics
Average Trip Time vs
Fault Current

1

Normal Fault Current
100 Threshold va RSET

11OG~~

;

e..
:::;

10.11111
~

~

!::

IV
RSET· 1"""11" x 10.911
~ SENSE TRANSFORMER 1000:1

I

!=all
100~11~~1
~

I

FI

~~

0.01

10

illa:

.!::

:;
~

10

O'---'L....I-.LJ.LIWL..,.-J....L.fJ.wJL-I-.LJ..UWU
I,D
0.1

,.
lOOk

TRIP TIME (SECONDS)

• See Block Diagram ,

,,..

'

w

l-oI;;;;=f---t--t-+-+-I

i

>

'

,B· 608
~
:I

I

..~
..
..•
'!;i
..i 0.1
~

lZ00 r-+-~~--r-+-~~

i!
;; 1000
!i;
100

10 _ _

Pin 1 Saturation Voltage va
External Load Current, IL

Output Drive Current va
Output Voltage

_ 1400 .-+,,--,.-----,---";--,---,.---,

1
=

111M

1M
RSElIO),

a:

4111

.1

ZOO

o L-"':""_"':""'---I._"---'--'

o

5

10

15

ZO

25

3D: 35

OUTPUT VOLTAGE' VPIN11Vl

10

10~

IL -EXTERNAL LOAD CURRENT ImA)
TL/H/5177-4

Circuit Description

-,

'

(Refer to Block and Connection Diagram)
The LM1851 operates from 26V as set by an intE1rnal shunt
regulator, 03. In the absence of a fault (If=O) the feedback
path status signal (Vs) is correspOndingly zero. Undfiir these
conditions the caPaCitor dischargll current. 11, $i18 quiescently at three times ,its threshold value. ITH. so that noise
induced charge on the timing capaCitor will be rapidly removed. When a fault current, If. is induced'in the secondary
of the external sense transformer, the operational amplifier,
A1, uses feedback to forc~ a virtual ground at the input as it

extracts I,. The' presencEI' of If during either half-cycle will
cause Vs to go high, which in turn changes 11 from 31TH to
ITH. Although ITH discharges the timing capaCitor during
bOth, half-cycles of the line. I, only charges the capacitor
during the half-cycle in which I, exits pin 2. Thus during one
half-cycle If-ITH charges the timing capacitor, while during
the other half-cycle ITH discharges it. When the capaCitor
,voltage reaches 17.5V, the"latch engages and turns off 03
permitting 12 to driv~ the gate of an seA.

~, :

4-236

r-

01)

A typical ground fault interrupter circuit is shown in Figure 2.
It is designed to operate,on 120 VAC line voltage with 5 mA
normal fault sensitivity.
A full-wave rectifier bridge and a 15k/2W resistor are used
to supply the DC power required by the IC. A 1 p.F bapacitor
at pin 8 used to filter the ripple of the supply voltage and is
also connected across the SCR to allow firing of the SCR on
either half-cycle. When a fault causes the SCR to trigger,
the circuit breaker is energized and line voltage is removed
from the load. At this time no fault current flows and the IC
discharge current increases from ITH to 31TH (see Circuit
Description and Block Diagram). This quickly resets both
the timing capacitor and the output latch. At this time the
circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A
1000: 1 sense transformer is used to detect the normal fault.
The lault current, which is basically the difference current
between the hot and neutral lines, is stepped down by 1000
and fed into the input pins of the operational amplifier
through a 10 jJ.F capacitor. The 0.0033 p.F capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4
are added to obtain better noise immunity. The normal fault
sensitivity is determined by the timing capacitor discharging
current, ITH. ITH can be calculated by:
7V
ITH=--+2
(1)
RSEl
At the decision point, the average fault current just equals
the threshold current, ITH.
ITH = If(rms) x 0 91

2

start-up (S1 closure) with both a heavy normal fault and a
20 grounded neutral fault present. This situation is shown diagramatically below.

'(1
,

GFI
~AL

RS

500

(O.BlIl

RG

1.6

~--~~~·~(-O.Z-II"---~1
TL/H/5177-5

UL943 specifies,,;; 25 ms average trip time under these conditions. Calculation of Ct based upon charging currents due
to normal fault only is as follows: '
,,;; 25 ms Specification
-3 ms GFI turn-on time (15k and 1 ",F)
- 8 ms Potential loss of one half-cycle due to fault current
sense of half-cycles only
-4 ms Time 'required to open a sluggish circuit breaker
,,;; 10 ms Maximum integration time that could be allowed
8 ms Value of integration time that accommodates component tolerances and other variables

Ct = I x

T

(5)

V

where T = integration time

V = threshold voltage
I = average fault current into
( 120 ~~(rms) )

1=

\

•

X

j

(4)

1000
The correct value for RSET can also be determined from the
characteristic curve that plots equation (3). Note that this is
an approximate calculation; the exact value of RSET depends on the specific sense transformer used and LM 1851
tolerances. Inasmuch as UL943 specifies a sensitivity "window" of 4 mA-6 mA, provision should be made to adjust
RSET on a per-product basis.
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the timing
capaCitor, Ct. Due to the large number of variables involved,
proper selection of Ct is best done empirically. The following
design example, then should only be used as a guideline.
Assume the goal is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GF1

x
\.

(

1turn)
1000 turns

•

current
division of
input sense
transformer
therefore:

f"'.
"l

Ct=

4-237

x
j

G)

'-,J
Ctcharging
on halfcycles only

Ct

(RG~
RJ
\.
•

heavy fault
current generated
(swamps ITH)

7V

1.5M 0

HOT

NEUTRAL

where If(rms) is the rms input fault current to the operational
amp and the factor of 2 is due to the fact that If charges the
timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have
7V
(3)
RSEl
If(rms) x 0.91
For example, to obtain 5 mA(rms) sensitivity 'for the circuit in
Agure 2 we have:
RSET ,5 mA x 0.91

o-!!!!!

LINE ' "

(2)

.

....
....
~

Application Circuits

x

(0.91)

'----v-J

X(0.911

0.01 p.F

(6)

rmsto
average
conversiqn

[G:) x (1.60~40.4) x (10~) x m 1x
17.5

j

portion of
fault current
shunted
aroundGFI

0.0008

(7)

CI1

Application Circuits (Continued)
in practice, the actual value of C1 will have to be modified to
include the effects of the neutral loop upon the net charging
current. The effect of neutral loop induced currents is diffi·
cult to quantize, but typically they sum with normal fault currents, thus allowing a larger value of C1.

For those GFI standards not requiring grounded neutral detection, a stili larger value capacitor can be used and better
noise immunity obtained. The larger capacitor can be accommodated because RN and RG are not present, allowing
the full fault current, I, to enter theGFI.
In .Figure 2, grounded neutral detection is accomplished by
feeding the neutral coil with 120 Hz energy continuously and
allowing some of the energy to couple into the sense transformer during conditions of neutral·fault.

For UL943 requirements, 0.015 ",F has been found to be
the best compromise between timing and noise.

Typica! Application
GNO/NEUTRAL
COIL

LOAD {HOT

SENSE
CDiL

MOY

}

NEUTRALo--+----t----<:r"j""lD------I

1-...;;;;;;.,.++------------1

I-=.:.....j~-o

CIRCUIT
BREAKER

10pF .

0.01l400Y

+

TANT

16k/2W

200,F
C,
0.016 8
'----+--+--,...:;.jYCC

GNOr-i-.....

Rsn*

0.01

+ 1.DIlF
TANT

• Adjust RSET lor desired sensitivity

TL/H/51n-6

FIGURE 2. 120 Hz Neutral Transformer Approach

4-238

LI~E

Definition of Terms
Normal Fault: An unintentional electrical path, Rs, between
the load terminal of the hot line and the ground, as shown
by the dashed lines.

Normal Fault plus Grounded Neutral Fault: The combination of the normal fault and the grounded neutral fault, as
shown by the dashed lines.
HOT

HOT
{
GFI

{
LINE
LINE

NEUTRAL

I

TLlH/5177-9

Grounded Neutral Fault: An unintentional electrical path
between the load terminal of the neutral line and the
ground, as shown by the dashed lines.

1

RLOAOI

-~t4"'

TL/H/5177 -7

LINE

NEUTRAL

HOT

NEUTRAL

TLlH/5177-8

i

•
4-239

Section 5
Surface Mount

II

Section 5 Contents
Packing Considerations (Methods, Materials and Recycling) .•...........................
Board Mount of Surface Mount Components . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • .. • . . . . . . .. . .
Recommended Soldering Profiles-Surface Mount .....................•...............
AN-450 Small Outline (SO) Package Surface Mounting Methods-Parameters and Their
Effect on Product Reliability. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . .
Land Pattern Recommendations ....................................................•

5-2

5-3
5-19
5-23
5-24
5-35

I!J1National Semiconductor

Packing Considerations (Methods, Materials and Recycling)
Transport Media
INTERMEDIATE CONTAINER
Tap. at R•• I

A" NSC devices art; prepared, inspected and packed to insure proper physical support and to protect during transport
and shipment. A" assembled devices are packed in one or
more of the following container forms-immediate containers, intermediate containers and outerI shipping containers.
An example of each container form is illustrated below.

Box

IMMEDIATE CONTAINER
Reel

TL/P/11809-4

\ ----~~_\
~_
_
\ J

TLlP/11809-1

Ie Device

Label

'"l:Je<~

\ Rail/Tube

TL/P/11809-5

Rail/Tube
TL/P/11809-2

Trays
TL/P/11809-6

OUTER/SHIPPING CONTAINER
TL/P/11809-3

II
TL/P/I1809-7

5-3

Methods of immediate carrier packing include insertion of
components into molded trays and rails/tubes, mounting of
components onto tape and reel or placement in corrugated
cartons. The immediate containers are then packed into intermediate containers (bags or boxes) which specify quantities of trays, rails/tubes or tape and reels. Outer/shipping
containers are then filled or partially filled with intermediate
containers to meet order q'uantity requirements and to fur- '
ther insure protection from transportation hazards. Additional dunnage filler material is required to fill voids within the
intermediate and outer/shipping containers.

General Packing Requirements

-

Impacts to the environment-it shall be 'reusable an~
recyclable.

Levels of Product Packing
':1

The first level of product packing is the immediate container.
The immediate container type varies with the product or
package being packed. In addition, the materials used In the
immediate container depend on the fragility, size and profile
of the product. The four types of in'lmei:liltte"containers used
by NSCare rails/tubes, trays, tape and reel,and rorrugated
,
and chipboard containers.
Rails/tubas are generally made of acrylic or polyvinyl chl6ride (PVC) plastics. The electrical characteristics of the materiai are altered by either intrinsically adding carbon fillers,
and/or topicaliy coating it with anti$tatic solution. Refer to
Table I for rail/tube material and recyclabillty information.

"

'

Optimum protection to the products-it must provide adequate protection from handling (electrostatic discharge) and transportation ~!1Zards;
'I,.

",

Ease of handling-it should ba easy to assemble, load
and unload products in and from it; and

' , IMMEDIATE CaNT-AINER

NSC packing methods and materials'are designed based'on
the following considerations:
-

-

TABLE I. PlastiC Rail/Tube and Stoppe~ Requirements

,

Rail

Package
Type

Material

DIP's
Plastic,

: Polyvinylchloride,
Polyvinylchloride
Polyvinylchloride '

Cen~mic

Sidebraze

Type

Code/Symbol
("ote 1)

"

OS/PVC
'
OS/PVC
OS/PVC

Stopper
Material

Code/Symbol
(Note 1)

Rtcyclability

Pin
Pin
Pin

Polyamide
Polyamide
Polyamide

07/PA
07/PA
07/PA

Yes
Yes
Yes

PLCC

Polyvinylchloride

OS/PVC '

Plug

Rubber

07/SBR

Yes

TapePak

Polyvinylchloride

OS/PVC

Plug

Rubber

07/SBR

Yes

Flatpack

Polyvinylchloride,

OS/PVC

Pin

Polymide

07/PA

Yes

Cerpack

Polyvinylchloride

OS/PVC

Pin

Polymide

07/PA

Ves

TO-220/202

Polyvinylchloride

OS/Pyc

Pin

Polymide

07/PA

Ves

T0-5/B
(in Carrier)

Polyvinylchloride

03/PVC

Pin

Polymide

07/PA

Yes

, ,

, Polyvinylchloride

OS/PVC

Plug

Rubber

07/SBR

Yes

PolYvi~ylchloride

OS/PVC

Plug

Rubber

07/SBR

Yes

SOP

:::

LCC
IBL-44i,;

):::i;:

",
Note 1: ISO 1043-1 International Standards-f'lastic Symbols.
SAE J1344 Marking of Plastic Parts,
ASTM D 1972-91 Standard Prac1lce for Generic Marking of Plastic Products.
DIN 6120. German Recycling Systems. RESY for paperbased and VGK for plastic paCking materials.
i

"

,

"

,

, ,,'

;

,:,"

"

"

Molded injection and vacuum formed trays can be either
conductive or static dissipative. Molded injection trays are
classified as either low-temperature or high-temperature

depending ·on the material type. Vacuum formed trays are
only used in ambient room temperature conditions. Refer to
Table II for tray material and recyclability information.

i

iii

Tray
Class

PQFP(AII)

Material

Recyclabllity
(Note 1)

Code/Symbol
(Note 1)
07/PES

Binding Type

High Temperature

Polyethersulfone

Yes

Low Temperature

Acrylonitrilebutadiene
Styrene

Yes

PGA,LDCC
CERQUADs
andLCC
(48 leads-125 leads)

Low Temperature
Only

ABS/PVC

Yes

07/ABS-PVC

Wire Tie

PPGA

Low Temperature
Only

Polyarylsulfone

Yes

07/PAS

Wire Tie

Tape and reel is a multi-part immediate container system.
The reel is made of either polystyrene (PS) material coated
with antistatic solution or chipboard. The emboss~ or cavity tape is made of either PVC or PS material. The cover tape

~

o
o

TABLE II. Tray Requirements
Package
Type'

~

i!S:

07!.~BS

Wire Tie or
Nylon Strap

CD

io

:::s
In

Wire Tie or
Nylon Strap

is made of polyester (PET) and polyethylene (PE) materials.
Refer to Table III for tape and reel material and recyclability
Information.

TABLE III. Tape and Reel Requirements
Reel
Package
Type

Material

carrier Tape

Cover Type
Code/
Symbol
(Note 1)

Code/
Symbol
(Note 1)

Material
'N/A

Material

Code/
Symbol
(Note 1)

Recyclability
(Note 1)

TO-92

Chipboard

Resy

SOP-23

Polystyrene
Chipboard

06/PS
Resy

Polystyrene

06/PS

Paper Tape
PVC

03/PVC

Yes

Yes

SOP,SSOP
and PLCC

Polystyrene
Polyethylene

06/PS

Polyester

07/PET-PE

PVC

03/PVC

Yes

Note 1: 150 1043·1 International Standards-Plastic Symbols.
SAE J1344 Marking of Plastic Parts.
ASTM D 1972-91 Standard Practice for Generic Marking of Plastic Products.
DIN 6120, Gennan Recycling Systems, RESY for paperllased and VGK for plastic packing materials.

,
5-5

•

Corrugated containers are generally constructed with fibreboard facings and a fluted corrugated medium in between
the facings. Chipboard containers are comprised of just one

fibreboard facing. Facings and corrugated medium are kraft
(brown) fibreboard, and generally single wall construction.
Refer to Table IV for material and recycl$ility information.

TABLE IV. Fibreboard Container R"qulrementa
P,ackMethod
Package
Type

Material

Container Type
Immediate (IMM)
Intermediate (INT)
Outer or Shipping (SHP)

Code'
Symbol
(Note 1)

Recyclability

T0-92/18,
TO-46/5,
TO-39;220,
T0-202/126,
TO-237

Corrugated
.(E070BOX)

Resy

IMM

Yes

All Products

Corrguated

Resy

INTandSHIP

Yes

All Products

3-PlyPaper
(Padpak)

Resy

Dunnage

Yes

All Products
PLCC

Plastic
Bubble Sheet

04/PE

Dunnage

Yes

Nota 1: ISO 1043·1 International Standards--Plas1ic Symbols.

SAE Jl344 Marking of Plas1lc Parts.
ASTM 01972-91 Standard Practica for Generic Marking of Plastic Products.
DIN 6120, German Recycling Systems, RESY for paperbased and VGK for plastic packing materials.

INTERMEDIATE CONTAINERS
The second level of product packing is the intermediate
container. Three types on intermediate containers are used
by NSC. They are plastiC bags, moisture barrier bags and
corrugated cartons/boxes.
Two types of plastiC bags are used and usage of each type
depends on the product or package being packed. Conductive bags are made of polyvinylchloride plastic material. The
electrical characteristics of the bag are altered by adding

carbon fillers which make the bag black (opaque) in color.
Conductive bags are used on products or packages that are
packed in ·Static dissipative (SO) rails/tubes. Static shielding
bags are made of two layers of SO polyethylene sheets with
a metallized film separating the sheets. Refer to Table V for
material and recyclability information.
Moisture barrier bags are used on rall/tube, tape and reel,
and tray packs for moisture sensitive products. NSC uses
National Metallizing'S Stratoguard™ 4.6.

5-6

TABLE V. Conductive and Static
Shielding Bag Requlrementa

Corrugated cartons/boxes are generally constructed with fibreboard facings and a fluted corrugated medium in between the facings. Facings and corrugated medium are kraft
(brown) fibreboards, and are generally of Single wall construction. Carton style varies with the product that it will contain. For example, packing of a rail/tube will require the use
of a carton with a roll end from lock (REFL) design. Other
products generally use the regular slotted container (RSC)
box. Refer to Table IV for material and recyclability information.

Mat'I
Package

Container

Meterlal

Type

Type

Type

and

Mat'l

Symbol Racyclability
(Note 1)

All Prod. in
Rails

Conductive Polyelhlene
Bag

TO·92/81 ,
Static
TO-46/5,
Shielding
TO·39/220, Bag
T0-202/126,
TO·3f237

Polyethlene
Alum. Larninant

04/PE

Yes

N/A

No

OUTER/SHIPPING CONTAINERS
The third level of product packing is the outer/shipping container. The outer/shipping containers use by NSC are similar to the corrugated containers used for immediate and intermediate packaging, but are heavier in facing thickness.
The style generally used is the regular slotted container
(RSC) box and can be Single, double or triple wall, depending on the total weight of products being transported or
shipped. Refer to Table IV for material and recyclability information.

TABLE VI. Drypack Bag Requlrementa
Package

Container

Matarlal

Type

Type

Type

TapePak
PLCC

Drypack

Met'l
and

Mat'l

Symbol Racyclability
(Nota 1)

Stratoguard™ 4.6

N/A

OTHER PACKING MATERIALS
Additional dunnage and void filler materials are required to
fill voids within the intermediate and outer/shipping containers. Two types of dunnage/filler material are Padpack and
bubble pack. Padpak is a machine processed, 3-ply kraft
paper sheet dunnage system. Refer to Table IV for material
and recyclability information.

No

Bag

(52·84L)
PQFP
Note 1: ISO 1043·1 International Standards-Plastic Symbols.
SAE J1344 Marking of Plastic Parts.
ASTM 01972-91 Standard Practios for Generic Marking of Plastic

Bubble pack is made of polyethylene plastiC sheets with air
pockets trapped in between the plastiC layers and can be
either static dissipative or conductive. Refer to Table IV for
material and recyclability information.

Products.
DIN 6120, German Recycling Systems, RESY for papsrbased and
VGK for plastic packlng materials

LII
5-7

'0

c
.2

l!
~

r-----------------------------------------------------------------------------,
Imn1~diate Container Pack Method$
' . .

.,'\

'J,',

'

.,'

"

'.'{

•

The following ~ble ,identifies the primary immediate ,container pack method for all hermetic and plastic packages offered by
Niltional Semiconductor. A secom;lary immediate container pack method is identified where applicable.
,

,

!o

Immediate Packing Method for Ceramic Packages

(,)
c:J)

c
:iii:

l

Primary
Immediate
Container

Secondary ,
Immediate
container

pa~kage
Type
(Code)

, PaCkage
Marketing
Drawing

, Method

Quantity

Ceramic Sidebrazed
Oual-ln'Line
Package (58)

008e

Rail/Tube

35

0140

Rail/Tube

25

016C

Rail/Tube

20

018A

'''Rail/Tube

20'

020A

Rail/Tube

020B

Rail/Tube

D240

Rail/Tube

15

024H

Rail/Tube

15

024K

Rail/Tube

15

0280

Rail/Tube

13

D28G

Rail/Tube

13

028H

Rail/Tube

13

040C

Rail/Tube

9

040J

Rail/Tube

9

048A

Rail/Tube

7

052A

Rail/Tube

7

E20A

Rail/Tube

50

EA20B

Rail/Tube

50

18
",,,

18

"

Ceramic Leadless
Chip Carrier (LCC)

E24B

Tray

25

E28A

Tray

28

EA028C

Tray

100

E32A

Rail/Tube

35

E32B

Rail/Tube

35

E32C

Rail/Tube

35

E40A

Rail/Tube

35

E44A

Rail/Tube

25

E48A

Tray

25

E68B

Tray

48

E68C

Tray

48

E84A

Tray

42

E84B

Tray

42

5-8

Method

' Quantity

Immediate Packing Method for Ceramic Packages (Continued)
Package

Type
(Code)

Ceramic Quad
J-Bend (CQJB)

Ceramic Quad
Flatpack
(CQFP)

Ceramic
Flatpack

Package
Marketing
Drawing

EL28A

Primary
'Immediate
Container

Secondary
Immediate
Container

Method

Quantity

Tray

96

EL44A

Tray

80

EL44B

Tray

80

EL44C,

Tray

80

EL52A

Tray

50

EL68A

Tray

44

EL68B

Tray

44

EL68C

Tray

44

EL84A

Tray

42

EL28B

Rail

15

Method

Quantity

EL64A

Box

36

E1100A

Tray

12

E1116A

Tray

12

E1132B

Tray

20

E1132C

Tray

20

EL132D

Tray

20

El164A

Tray

12

EL172B

Tray

12

EL172C

Tray

12

F10B

Carrier/Rail

19

Carrier/Box

200

F14C

Carrier/Rail

19

Carrier/Box

200

F16B

Carrier/Rail

19

Carrier/Box

200

•
5-9

Immediate Packing Method for'Ceramlc Packages (Continued)
paCk8ge
Type
(Cocie)
Ceramic Dual-InLine Package
(Cerdip)

,
Ceramic Small
Outline Package,
Wide

,""

Package
Marketing
Drawing

Secondary
Immediate
Container

Primary
Immediate
Container
Method

Quantity

J08A

Rail/Tube

40

J14A

Rail/Tube

25

J16A

Rail/Tube

25

J18A

Rail/Tube

20

J20A

Rail/Tube

20

J22A

Rail/Tube

17

J24A

Rail/Tube

15

J24AQ

Rail/Tube

15

J24B-O

Rail/Tube

15

J24CO

Rail/Tube

15

J24E

Rail/Tube

16

J24F

Rail/Tube

15

J28A

Rail/Tube

12

J28AQ

Rail/Tube

12

J28B

Rail/Tube

12

J28BQ

Rail/Tube

12

J28CQ

Rail/Tube

13

J32B

Rail/Tube

11

J32AQ

Rail/Tuba

11

J40A

Rail/Tube

J40AQ

Rail/Tube

J40BQ

Rail/Tube

e
e
e

MC16A

Rail/Tube

45

MC20A

Rail/Tube

36

MC20B

Rail/Tube

36

MC24A

Rail/Tube

30

MC28A

Rail/Tube

26

MC28B

Rail/Tube

26

.

5-10

Method

Quantity

l

Immediate Packing Method for Ceramic Packages (Continued)

~

Package
Type
(Code)
Ceramic Pin Grid
Array (CPGA)

Primary
Immediate
Container

Package
Marketing
Drawing

Method

Quantity

U44A

Tray

80

U68B

Tray

42

U68C

Tray

42

U68D

Tray

42

U68E

Tray

42

U75A

Tray

35

U84A

Tray

42

U84B

Tray

42

U84C

Tray

42

U99A

Tray

25

U100A

Tray

30

U109A

Tray

25

U120A

Tray

30

U120C

Tray

30

U124A

Tray

30

U132A

Tray

30

U132B

Tray

30

U144A

Tray

20

U156A

Tray

20

U156B

Tray

20

U169A

Tray

20

U173A

Tray

20

U175A

Tray

20

U180A

Tray

20

U223A

Tray

20

U224A

Tray

20

U257A

Tray

12

U259A

Tray

12

U299A

Tray

12

U301A

Tray

12

U303A

Tray

12

U323A

Tray

12

5·11

Secondary
Immediate
Container
Method

Quantity

:i"
CO

oo

I.
CD
i.o
Co

=
(II

.~ r-------------------------------------------------------------------------------------~

I-8
Or!

[1
0)

c

Immediate Packing Method for Ceramic Packages (Continued)
,.

"

Package
1)

~~
..... ::1

......

ffi ~

i!'''

",1 =24-25

_....::~~:::::;;....-- :

b;~~~:::;::::;::::;::+:::;::~::=:: T (Oe)
100 110 120 130 1.40 150 1601170 180

Ta
TL/P/II828-1

I;'IGURE 1_ Thermal Expansion and Gla.-

Conventional Wave Soldering
Most wave soldering operations occur at temperatures'between 24QoC-260"C. Conventional' epoxies for encapsulation have glass-transition temperatures between 140"C17o"C. An I.C. directly exposed to these temperatures risks
its long term functionality due to'epoxy/metal separation.

Fortunat~ly, there are factors that can reduce that. element
of r i s k : '
,

a

1. ThePW board has certain amau'lit of heat-sink effort
and tends to shield the components from the temperatur~ of the 1'Older (if they were placed on the .top side of
the board). In actual measurements, DIPs achieve a·temperature between 120"C-150"C in a 5-second pass over
the solder. This accounts for the fact that DIPs mounted
in the conventional manner are reliable.
2) ·11'1 conventional soldering, only the tip of each lead in DIP
would experience the solder temperature because the
epoxy and die are standing above the PW board and out
of the solder bath.
.

Effect on Packag~ Performance by
,Ep,qxy-Metal.Separation

Since Plastic DIPs and SMDs are encapsulated with a thermoset epoxy, the thermal, characteristics of the material
generally correspond to a TMA (Ther",o-Mechanical Analysis) graph, The critical parameters are (a) its Linear thermal
expansion characteristics and (b). its glass transition temperature after the epoxy has been fully cured. A typical TMA
graph is illustrated in F1[Jure 1. Note that t~1! ElPoxy changes
to a hig~er thermal ~xpanllion once it is subjected to temperatures exceeding its glass transition temperatUre. Metals
(as used on leadframes, for example) do not have this characteristic and generally will have a consistent Linear thermal
expansion over the same temperature I!llnge.

In walie soldering, it is necessary to use fluxes to assist the
solderability of the components and PW boards. Some facilities may even process the boards and components through
some form of acid cleaning prior to the soldering temperature. If separation occurs, the flux residues and acid residues (which may be present owing to inl!dequate cleaning)
will be forced into the pac,kage mainlY by cap,illary action as
the residues move away from the solder heat source. Once
the package is cooled, these. contaminants a~e now trapp~c;I
within the package and are available to diffuse,.with moisture
from the epoxy over time. It should be noted that electrical
tests performed immediately after soldering generally Will
give no,indication of this potential problem. In any case, the
end result will be COrrosion of the chip meta)ization over
time and premature failure of. the device.!n the field.

In any good ·reliable plastic pacl91010\1. their glaSs. tranSition; there is a small possibility of
separation at the epoxy-metal interface. However, If. ,the
package is slibjectE!d to temperature'above itsglass'transition temperature, the epoxy will expand much faster than
the metal and the probability of sep~ation is greatly in'
creased.

5-20

TABLE IV. Vapor Phase vs. Wave Solder

Vapor Phase/lR Reflow Soldering
In both vapor phase and IA reflow soldering, the risk of
separation between epoxy/metal can also be high. Maximum operating temperatures are 219'C (vapor phase) or
240'C (IA) and duration may also be longer (30 sec-60
sec). On the same theoretical basis, there should also be
separation. However, in both these methods, solder paste is
applied to the pads of the boards; no fluxes are used. Also,
the devices are not immersed into the hot solder. This reduces the possibility of solder forcing itself into the epoxyleadframe interface. Furthermore, in the vapor phase system, the soldering.environmel1t is "oxygen·free" and considered "contaminant free". Being so, it could be· visualized
that as far as reliability with respect ·to corrosion, both of
these methods are advantageous over wave soldering,

1. Vapor phase (60 sec. exposure @ 217'C)
= 9 failures/1723 samples
= 0.5% (average over 32 sample lots)
2. Wave solder (2 sec'total immersion @ 260'C)
= 16 failures/1201 samples
= 1.3% (average over 27 sample lots)
Package: SO-14 lead
Test:
Bias moisture test 85% A.H.
Device:

85'C for 2,000 hours
lM324M

In Table V we examine the tolerance of the Small-Outlined
(SOIC) package to varying immersion time in a hot solder
pot. SO-14 lead molded packages were subjected to the
bias moisture test after being treated to the various soldering conditions and repeated four (4) times. End point was an
electrical test after an equivalent of 4,000 hours 85/85 test.
Aesults were compared for packages by themselves
against packages which were surface-mounted onto a FA-4
printed wire board.

Bias Moisture Test
A bias moisture test was designed to determine the effect
on package performance. In this test, the packages are
pressured in a steam chamber to accelerate penetration of
moisture into the package. An electrical bias is applied on
the device. Should there be any contaminants trapped within the package, the moisture will quickly form an electrolyte
and cause the electrodes (which are the lead fingers), the
gold wire and the aluminum bond-pads of the silicon device
to corrode. The aluminum bond-pads, being the weakest
link of the system, will generally be the first to fail

TABLE V. Summary of Wave Solder Results

ControlNapor Phase
15 sec@ 215'C

This proprietary accelerated bias/moisture pressure-test is
significant in relation to the life test condition at 85'C and
85% relative humidity. One cycle of approximately 100
hours has been shown to be equivalent to 2,000 hours in
the 85/85 condition. Should the packages start to fail within
the first cycle in the test, it is anticipated that the boards with
these components in the harsh operating environment
(85'C/85% AH) will experience corrosion and eventual
electrical failures within its first 2,000 hours of operation.

Solder Dip
4Sec@260'C

Whether this is significant to a circuit board manufacturer
will obviously be dependent on the products being manufactured and the workmanship or reliability standards. Generally in systems with a long warranty and containing many
components, it is advisable both on a reputation and cost
basis to have the most reliable parts available.

Mounted

0/114

0/84

2/144 (1.4%)

0/85

Solder Dip
4Sec@26O'C

-

0/83

Solder Dip
6Sec@260'C

13/248 (5.2%)

1/76(1.3%)

Solder Dip
10 Sec @260'C

14/127 (11.0%)

3/79 (3.8%)

Package:
Device:

Test Results

Unmounted

SO-14 lead
lM324M

Since the package is of very small mass and experiences a
rather sharp thermal shock fOllowed by stresses created by
the mismatch in expansion, the results show the packages
being susceptible to failures after being immersed in excess
of 6 seconds in a solder pot. In the second case where the
packages were mounted, the effect of severe temperature
excursion was reduced. In any case, because of the repeated treatment, the package had failures when subjected in
excess of 6 seconds immersion in hot solder. The safety
margin is therefore recommended as maximum 4 seconds
immersion. If packages were immersed longer than 4 seconds, there is a probable chance of finding some long term
reliability failures even though the immediate electrical test
data could be acceptable.

The comparison of vapor phase and wave-soldering upon
the reliability of molded Small-Outline packages was performed using the bias moisture test (see Table IV). It is
clearly seen that vapor phase reflow soldering gave more
consistent results. Wave soldering results were based on
manual operation giving variations in soldering parameters
such as temperature and duration.

III
5-21

J9

r-------------------------------------------------------------------------------------~

i

I

o

1:
::;,

&
8

~

~

-

'0
§
o

::IE

'E

8

ID

Finally, Table VI examines the bias moisture test performed
on surface mount (SOle) components manufactured by various semiconductor houses. End pOint was an electrical test
after an equivalent of 6,000 hours in an 85/85 test Failures
were analyzed and corrosion was checked for in each case
to detect flaws in package integrity.

Summary
Based on the results presented, it is noted that surfacemounted components are as reliable as standard molded
DIP packages. Whereas DIPs were never processed by being totally immersed in hot solder wave during printed circuit
board soldering, surface mounted components such as
SOICs (Small Outline) are expected to survive a total immersion in the hot solder in order to capitalize on maximum
population on boards. Being constructed from a thermoset
plastic of relatively low T9 compared to the soldering temperature, the ability of the package to survive is dependent
on the time of immersion and also the cleanliness of material. The results indicate that one should limit the immersion
time of the package in the solder wave to a maximum of 4
seconds in order to truly duplicate the reliability of a DIP. As
the package size is reduced, as in a 50-8 lead, the requirement becomes even more critical. This is shown by the various man\lfacturers' performance. Results indi~te there is
room for improvement since not all survived the hot solder
immersion without compromise to lower reliability.

TABLE VI. U.S. Manufacturing Integrated Circuits
Reliability in Various Solder Environments
(4O FailurelTotal Environment)
Package
SO-8

Vapor
Phase
30 sec

Wave
Solder

ManufA
ManufB
ManufC

8/30'
2/30'
0/30

1/30'
8/30'
0/29

ManufD
ManufE
ManufF
NSC

1/30'
1/30"
0/30
0/30

2 sec

Wave
Solder
4 sec

Wave
Solder
6 sec

Wave
Solder
10 sec

0/30 12/30' 16/30'
2/30' 22/30' 20/30'
0/30
0/30
0/29

12/30' 14/30'
0/30
0/30
0/30
0/30
0/30
0/30

2130'
0/30
0/30
0/30

·Corroslon failures
"No Visual Defects..Non-corroslon failues
Test Accelerated Bias Moisture Test 85% R.H.f85"C. 6,000 equivalent

hours

5-22

::D

§

tflNational Semiconductor

:3
:3
CD

:::s

a.

Recommended Soldering Profiles-Surface Mount

Z-

en
o

...S"a::
CD

Wave
Solder
Ramp Up °C/sec

Dwell Time

~

183·C

Solder Temperature

SOC/sec

4°C/sec

24°C/sec

..

2°C/sec

Minimum

..

2°C/sec'

Maximum

135°C

N/A

N/A

Recommended

120·C

N/A

N/A

Minimum

110"C

N/A

N/A

Maximum

N/A

85 seconds

85 seconds

Recommended

N/A

75 seconds'

75 seconds'

Minimum

N/A

30 seconds"

Maximum

2SO"C

240"C'"

Recommended

2400C

..

Minimum
Dwell Time @ Max.

Maximum

..

215°C'

..

..

75

Minimum

..

70.econd.

Maximum

No Information

4·C/sec

4·C/sec

2·C/sec

Minimum

No Information

1 second

..

!
§
i:

oc

:::s

..

10 seconds

Recommended

"1J

219"C

5 second.

3 second.

CO

215·C·

4 seconds

Recommended

Ramp Down ·C/sec

Profile

Vapor
Phase

4°C/sec'

Maximum
Recommended

AT

IR

..
..

4·C/sec
2·C/sec

Note: Temperature In degrees celclue. NIA = Not Applicable.
b.T = The temperature differenIiaJ betwean the final preheat stage and the soldering stage. Temperature measured at the component lead area
'Will vary depending on board density, geometry, and package type.
"Will vary depending on package types, and board density.
"·For plastic packages; ceramic packages maximum may be 2SOOC.

•
5-23

National Semiconductor
Small Outline (SO) Package Application
Note 450 ,"
Surface Mounting Methods- Josip Huljev
w. K. Boey
Parameters and Their
Effect. on Product, Reliability,.
,

The SO (small outline) package has been developed to
meet customer demand for ever-increasing miniaturization
and component density.

COMPONENT SIZE COMPARISON'

-' ,
[gJ
5;0. Package

I

.e'

",'

"

I

L_.J

-I I-

TYPICALLy .....• WDIFIOCIHO

In order to achieve reliability performance comparable to
DIPs-SO packages are designed and built with materials
and processes that effectively compensate for their small
size.
All SO packages tested on 85%RA, 85°C were assembled
on PC conversion boards using vapor-phase reflow soldering. With this approach we are able to measure the effect of
surface mounting methods on reliability of the process. As
illustrated in Figure A no significant difference was detected
between the long term reliability performance of surface
mounted S.O. 'packages and the DIP control product for up
to 6000 hours of accelerated 85%/85°C testing.

SURFACE-MOUNT PROCESS FLOW

TUF/B766-1

The standard process fldwcharts for basic surface-mount
operation and mixed-lead insertion/surface-mount operations, are illustrated on the following pages.

" Standard DIP Package

Usual variations encountered by users of SO packages are:
, • Single-sided boards, surf~ge·mounted components only.
• Single-sided boards, mixed-lead inserted and.., surface·
mounted components .
• Double-sided boards, surface-mounted components only.

TUF/B766-2

Because of its small size, reliability' of the product assembled in SO packages needs to be carefully evaluated.
SO packages at National were internally qualified for production under the condition that they be of comparable reliability performance to a standard dual in line package under
all accelerated environmental tests. Figure A is a summary
of accelarated bias moisture test performance on 30V bipolar and 15V CMOS product asse~bled in SO a,nd DIP (control) packages.

• Double-sided boards, mixed-lead inserted and surfacemounted components.
In consideration ot these variations; it became necessary for
users to utilize techniques Involving wave soldering and adhesive applications, along with the commonly-used vaporphase solder reflow soldering technique.
,"

PRODUCTION FLOW
,

,

Basic Surface·Mount Production Flow

V+=15VCIIOS
30V BIPOLAR
85%RH/85OC
TEST CONOmON

DIP

o

2000

.woo

60DD

TEST TillE (HRS)
TL/F/B766-3

FIGURE A

TLlF/B766-4

5·24

Thermal stress of the packages during surface-mounting
processing is more severe than during standard DIP PC
board mounting processes. Figure 8 illustrates package
temperature versus wave soldering dwell time for surface
mounted packages (components are immersed into the
molten solder) and the standard DIP wave soldering process. (Only leads of the package are immersed into the molten solder).

Mixed Surface-Mount and Axial-leaded Insertion
Components Production Flow

SOLDER TEMPERATURE 26O"C

o

1 2 3 4 5 6 'I 8 9 10 SEC.

DWELL TIME
TUF/8766-6

FIGUREB

For an ideal package, the thermal expansion rate of the
encapsulant should match that of the leadframe material in
order for the package to maintain mechanical integrity during the soldering process. Unfortunately, a perfect matchup
of thermal expansion rates with most presently used packaging materials is scarce. The problem lies primarily with the
epoxy compound.
Normally, thermal expansion rates for epoxy encapsulant
and metal lead frame materials are linear and remain fairly
close at temperatures approaching 160"C, Figure C. At lower temperatures the difference in expansion rate of the two
materials is not great enough to cause interface separation.
However, when the package reaches the glass-transition
temperature (Tg) of epoxy (typically 160-165°C), the thermal expansion rate of the encapsulant increases sharply,
and the material undergoes a transition into a plastic state.
The epoxy begins to expand at a rate three times or more
greater than the metal leadframe, causing a separation at
the' interface.

TUF/8766-5

al

,

100 110 120 130 140 150 160,170 180
T9

T(OC)
Tl/F/8766-26

FIGUREC

5-25

The basic component-placement systems available are
classified as:

When this happens during a conventional wave soldering
process using flux and acid cleaners, process' residues and
even solder can enter the cavity created by the separati~n
and, become entrapped when the material cools. These
contaminants can eventually diff!lse into the interior of the
package, especially in the presence of moisture. The result
is eiie contamination, excessive leakage, and even catastrophic failure. Unfortunately, electrical tests performed immediately following soldering may not detect potential flaws.

(a) In-line placement
-

Fixed placement stations

-

Boards indexed under head and respective components placed

(b) Sequential placement
-

Most soldering processes involve temperatures ranging up
to 260"C, which far exceeds the glass-transition temperature of epoxy. Clearly, circuit boards containing SMD packages require tighter process controls than those used for
boards populated solely by DIPs.

-Individual components picked and placed onto boards
(c) Simultaneous placement
-

Agure 0 is a summary of accelerated bias moisture test
performance on the 30V bipolar process. '
Standard DIP package

Group 2 -

SO packages vapor-phase reflow soldered on
PC boards

Group 3-6 SO packages wave soldered on PC boards
dwell time 2 seconds

45-

dwell time 4 seconds

6-

dwell time 10 seconds

2000

-

X- Y moving table, multiple pickup heads system

-

Components placed on PCB by successive or simultaneous actuation of pickup heads

The SO package is treated almost the same as surfacemount, passive components requiring correct orientation in
placement on the board.
Pick and Place Action

dwell time 6 seconds

o

Multiple pickup heads
Whole array of components placed onto the PCB at
the same time

(d) Sequential/simultaneous placement

Group 1 -

Group 3 -

Either a X-V moving table system or a 8, X-V moving
pickup system used

4000

TEST TIME (HRS)
TL/F/S766-7

FIGURED
It is clear based on the data presented that SO packages
soldered onto PC boards with the vapor phase reflow process have the best long term bias moisture performance
and this is comparable to the performance of standard DIP
packages. The key advantage of reflow soldering methods
is the clean environment that minimized the potential for
contamination of surface mounted packages, and is preferred for the surface-mount process.

TUF/S766-S

BAKE
This is recommended, despite claims made by some solder
paste suppliers that this step be omitted.
The functions of this step are:

When wave soldering is used to surface mount components
on the board, the dwell time of the component under molten
solder should be no more than 4 seconds, preferrably under
2 seconds in order to prevent damage to the component.
Non-Halide, or (organic acid) fluxes are highly recommen(led.

• Holds down the solder globules during subsequent reflow
soldering process and prevents expulsion of small solder
balls.
• Acts as an adhesive to hold the components in place during handling between placement to reflow soldering.
• Holds components in position when a double-sided surface-mounted board is held upside down going into a vapor-phase reflow soldering operation.

PICK AND PLACE
The choice of automatic (all generally programmable) pickand-place machines to handle surface mounting has grown
considerably, and their selection is based on individual
needs and degree of sophistication.

• Removes solvents which might otherwise contaminate
other equipment.
• Initiates activator cleaning of surfaces to be soldered.
• Prevents moisture absorption.

5-26

~-------------------------------------------------------------------.~

The process is moreover very simple. The usual schedule is
about 20 minutes in a 65°C-95°C (dependent on solvent
system of solder paste) oven with adequate venting. Longer
bake time is not recommended due to the following reasons:

VAPOR-PHASE REFLOW SOLDERING
Currently the most popular and consistent method, vaporphase soldering utilizes a fluoroinert fiuid with excellent
heat-transfer properties to heat up components until the s61·
der paste reflows. The maximum temperature is limited by
the vapor temperature of the fluid,
.
The commonly used fluids (suppiied by 3M Corp) are:

• The flux will degrade and affect the characteristics of the
paste.
• Solder globules will begin to oxidize and cause solderability problems.

• FC-70, 215°C vapor (most applications) or i=X-38
• FC-71 , 253°C vapor (low-lead or tin-plate)

• The paste will craep and after reflow, may leave behind
residues between traces which are difficult to remove and
vulnerable to electro-migration problems.

HTC, Concord, CA, manufactures' equipment that utilizes
this technique, with two options:
• Batch systems" where boards are lowered in a basket and
subjected to the vapor from a tank of boiling fluid.

REFLOW SOLDERING

There are various methods for reflowing the solder paste,
namely;
•
•
•
•

• In-line conveyorized systems, where boards are placed
onto a continuous belt which transports them into a concealed tank where they are subjected to an environment
of hot vapor.

Hot air reflow
Infrared heating (fumaces)
Convectional oven heating
Vapor-phase reflow soldering

Dwell time in the vapor is generally on the order of 15-30
seconds (depending on the mass of the boards and the
loading density of boards on the belt).

• Laser soldering
For SO applications, hot air reflow/infrared furnace may be
used for low-volume production or prototype work, but vapor-phase soldering reflow is more efficient for consistency
and speed. Oven heating is not recommended because of
"hot spots" in the oven and uneven melting may result. laser soldering is more for specialized applications and requires a great amount of investment.

Vapor-Phase Profile
RECOMMENDED

( 1!120 DEG

HOT GAS REFLOWIINFRARED HEATING

A

A hand-held or table-mount air blower (with appropriate orifice mask) can be used.
'.. '

u

The boards are preheated to about 1WC and then subjected to an air jet at about 2600C. This is.a slow process and
results may be inconsistent due t6 iiarious heat-sink properties of passive components.

c/s.c )

. TillE
TL/F/8766-28

INFRARED REFLOW SOLDERING

In-Une Conveyorlzed Vapor-Phase Soldering

Use of an infrared furnace is currently the most popular
method to automate mass reflow; the heating is promoted
by use of IR lamps or panels. Early objections to this method were that certain materials may heat up at different rates
under IR radiation and could result in damage to those components (usually sockets and connectors). This has been
minimized by using far-infrared (non-focused) systems and
convected air.
Infrared Profile

•....... ~

J

-

.. _ L_
..

/"
. mID - -...... -1-aELT--"="=- ~~- --COILS

COILS

RECOMMENDED

c==:::>
LIQUID

IMMERSION HEATER
R

(131 DEG C/sec

TLlF/8766-9

)

The question of thermal shock is asked frequently because
of the relatively sharp increase in component temperature
from room temperature to 215°C. SO packages mounted on
representative boards have been tested and have shown
little effect on the integrity of the packages. Various packages, such as cerdips, metal cans and TO-5 cans with glass
seals, have also been tested.

A

o

50 100 150 199 250 300

TIME
TUF/8766-27

5-27

z

~

o

Vapor-Phase Furnace

Batch-Fed Production Vapor-Phase Soldering Unit
SECONDARY

PRIMARY

TL/F/8766-11

TL/F/8766-10

Solder Joints on a SO-14
pa~k~ge
on PCB
,
"

Solder Joints on a S0-14 Package on PCB

TLlF/8766-12

TL/F/8766-13

5-28

common and well-tried method. The paste is forCEld through
the screen by a V-shaped plastiC squeegee in a sweeping
manner onto the board placed beneath the screen.

PRINTED CIRCUIT BOARD
The SO package is molded out of clean, thermoset plastic
compound and has no particular compatibility problems with
most printed circuit board substrates.
The package can be reliably mounted onto substrates such
as:

The setup for SO packages has no special requirement
from that required by other surface-mounted, passive components. Recommended working specifications are:
• Use stainless-steel, wire-mesh screens, #80 or #120,
wire diameter 2.6 mils. Rule of thumb: mesh opening
should be approximately 2.5-5 times larger than the average particle size of paste material.

• G10 or FR4 glass/resin
• FR5 glass/ resin systems for high-temperature
applications
• Polymide boards, also high-temperature
applications

• Use squeegee of Durometer 70.
• Experimentation with squeegee travel speed is recommended, if available on machine used.

• Ceramic substrates
General requirements for printed circuit boards are:

• Use solder paste of mesh 200-325.
• Emulsion thickness of tW05" usually used to achieve a
solder paste thickness (wet) of about 0.008" typical.

• Mounting pads should be solder-plated whenever
applicable.
• Solder masks are commonly used to .prevent solder bridging of fine lines during soldering.

• Mesh pattern should be 90 degrees, square grid.
• Snap-off height of screen should not exceed YaH, to avoid
damage to screens and minimize distortion.

The mask also protects circuits from processing chemical
contamination and corrosion.

SOLDER PASTE

If coated over pre-tinned traces, residues may accumulate
at the mask/trace interface during subsequent reflow,
leading to possible reliability failures.

Selection of solder paste tends to be confusing, due to numerous formulations available from various manufacturers.
In general, the following guidelines are sufficient to qualify a
particular paste for producti.on:
• Particle sizes (see following photographs). Mesh 325 (approximately 45 microns) should be used for general purposes, while larger (solder globules) particles are preferred for leadless components.(LCC). The larger particles
can easily be used for SO packages.

Recommended application of solder resist on bare, clean
traces prior to coating exposed areas with solder.
General requirements for solder mask:
-

Good pattern resolution.

Complete coverage of circuit lines and resistance to
flaking during soldering.
- Adhesion should be excellent on substrate material to
keep off moisture and chemicals.
- Compatible with soldering and cleaning requirements.
-

• Uniform particle distribution. Solder globules should be
spherical in shape with uniform diameters and minimum
amount of elongation (visual under 100/200 x magnification). Uneven distribution causes uneven melting and subsequent expulsion of smaller solder balls away from their
proper sites.

SOLDER PASTE SCREEN PRINTING
With the initial choice of printed. circuit lithographic design
and substrate material, the first step in surface mounting is
the application of solder paste.
The typical lithographic "footprints" for SO packages are
illustrated below. Note that the 0.050" lead center-center
spacing is not easily managed by commercially-available air
pressure, hand-held dispensers.
Using a stainless-steel, wire-mesh screen stencilled with an
emulsion image of the substrate pads is by far the most

• Composition, generally 60140 or 63/37 Sn/Pb. Use 62/36
Sn/Pb with 2% Ag in the presence of Au on the soldering
area. Thi~ forrnulation.reduces problems of metal leaching
from soldering pads.
• RMA flux system usually used..
• Use paste with aproximately 88-90% solids.

,j"

II
5-29

RECp",,,,ENDEb SOLDER PADS FOR SO PACKA~ES
S()"B, SO-14, S()..16

SO-16L,SO-20

····1
r.. ... 'J.'
LI I I I

0.04S" %O.OOS"

.r····~

L••••
~-J

0.24S"

.

0.160"

--I I--

0.030" %O.OOS"

0.42

I-O.OSO" TYP
TL/F/8766-14

SOT-23

1-

0.030"

r.
.l,·

0.030" %0.00S"1

0.12

~0.005" ~

~OO~~;"

1- .~ I-:J.

TYP

TL/F/8766-15

I
-{ff.r-~

,I I
TUF/8766-18

Comparison of Particle Size/Shape of Various Solder Pastes
200 X Alpha (62/36/2)

200 X Kester (B3/3!)

TUF/8788-17

TL/F/8766-18

5-30

· Comparison of Particle Size/Shape of Various Solder Pastes (Continued)
Solder Paste Screen on Pads

200 x Fry Metal (63/37)

TL/F/8766-20

TUF/8766-19

200 ESL (63/37)

'J"UF/8766-21

5-31

o ,-----------------------------------------------------------------------------,

~
~

CLEANING

Hot-Air Rework Machine

The most critical process in surface mounting SO packages
is in the cleaning cycle. The package'is mounted very close
to the surfaee of the substrate and, has a tendency to collect
residue left behind. after reflow soldering.·.

Importa~t considerations in cleaning are:
• Time between soldering anC! 'cleaning to be as short as
possible. Residue should not be:allowed to solidify on the
substrate for long periods of. time, making it dit/icult to
dislodge.
• A low surface tension solvent (high penetration) should be
employed. CFC solvents are being phased out as they are
hazardous to the environment. Other approaches to
cleaning are cOmmercially available and should be investigated on an individual basis consi~ering local. and govern.
ment environmental rules.

TlIF/8766-23

lead tips or, if necessary, solder paste ean be dispensed
onto the palls using a varimeter.. Aftet being placed into
pOSition, the sOltler is rilflowed bY.8 hot-air jet or even a
standard soldering iron.
.

Prelete: or 1,1,1-Trichloroethane
Kester 5120/5121

WAVE SOLDERING

• A defluxer system which allows the workpiece to be subjected 'to a solvent vapor, followed by a rinse in pure solvent and.a high-pressure spray lance are the basic requirments ·forlow-volumll, production.

In a case where lead insertions are made on the same
board as surface-mounted components, there is a need to
include a wave-soldering operation in the process. flow.

ar"

• For volume.prixluction,·~ conveyorized, multiple,'hot solvent spray/jet system is recommended.

used:
Two options
• Surface mounted components are placed and vapor
, phase reflowed before auto-insertion of remaining components. The board is carried over a standard wave-solder
system and the underside of the board (only lead-inserted
leads) soldered.

• Rosin, being a natural occurring material, is not readily
soluble in solvents, and has long been a stumbling block
to the cleaning process. In recent developments, synthetic flux (SA flux), which is readily soluble in Freon TMS'
solvent, has been developed. This should be explored
where permissible.

• Surface-mounted components are placed in position, but
no solder paste is used. Instead, a drop of adhesive about
5 mils maximum. in height with diameter not exceeding
25% width of the Pa,ckage is used to hold down the package. The adhesive is cured and then proceeded to autoinsertion on the reverse side of the board (surface-mounted side facing down). The assembly is then passed over a
"dual wave" soldering system. Note that the surfacemounted components are immersed into the molten solder.
Lead trimming will pose a problem after soldering in the
latter case, unless the leads of the insertion components
are pre-trimmed or the board specially designed to localize
certain areas for easy access to the trim blade.
The controls required for wave soldering are:
• Solder temperatl:lre to be 240-260·C. The dwell time of
components under molten so.lder to be short (preferably
kept under 2 seconds), to prevent damage to most components'
and
semiconductor devices.
,
.

The dangers of an inadequate cleaning cycle are:
• Ion contamination, where ionic residue left on boards
would cause corrosion to metallic components, affecting
the performance of the board.
• Electro-migration, where ionic residue and moisture present on electrically-biased boards would cause dentritic
growth between close spacing traces on the substrate,
resulting in failures (shorts).

REWORK
Should there be a need to replace a compo,nent or re-align
a previously disturbed component, a hot air .system with appropriate orifice masking to protect surrounding compo.
nents may be used.
When rework is necessary in the field, specially-designed
tweezers that thermally heat the component may bEt Used to
remove it from its site. The replacement can be ,fluxed at the'
.
:~."
.'~
Hot-Air Solder Rework Station

- ,- - --c--------.

• RMA (Rosin Mildly Activated) flux or more aggressive OA
(Organic Acid) flux are applied by either dipping or foam
fluxing on boards prior to preheat and soldering. Cleaning
procedures are also more difficult (aqueous, when OA flux
is used), as the entire board has been treated by flux (unlike solder paste, which is more or less localized). Nonhalide OA fluxes are highly recommended.

MASeK

RETRACT POSITION

/

/

// 0
.

----

• Preheating of boards is essential to reduce thermal shock
on components. Board should reach a temperature of
about 1000C just before entering the solder wave.

HEAT SHIELD
BOARD DN

• Due to the closer lead spacings (0.050' vs 0.100' for
dual-in-line packages), bridging of traces by solder could
occur. The reduced clearance between packages also
causes "shadowing" of some areas, resulting in poor solder coverage. This is minimized by dual-wave solder systems.

x-v TABLE

HOT AIRTL/F/8766-22

5-32

Mixed Surface Mount and Lead Insertion

(b) Opposite Sides

(a) Same Side

-

tttt
PREHEAT

SOLDER FLOW
TUF/8766-24

A typical dual-wave system is illustrated below, showing the
various stages employed. The first wave typically is in turbulence and given a transverse motion (across the motion of
the board). This covers areas where "shadowing" occurs. A
second wave (usually a broad wave) then proceeds to perform the standard soldering. The departing edge from the
solder is such to reduce "icicles," and is still further reduced
by an air knife placed close to the final soldering step. This
air knife will blow off excess solder (still in the fluid stage)
which would otherwise cause shorts (bridging) and solder
bumps.

Dual Wave

AQUEOUS CLEANING
• For volume production, a conveyorized system is often
used with a heated recirculating spray wash (water temperature 130"C), a final spray rinse (water temperature
45-55°C), and a hot (120"C) air/air-knife drying section.
• For low-volume production, the above cleaning can be
done manually, using several water rinses/tanks. Fastdrying solvents, like alcohols that are miscible with water,
are sometimes used to help the drying process.
• Neutralizing agents which will react with the corrosive materials in the flux and produce material readily soluble in
water may be used; the choice depends on the type of flux
used.
• Final rinse water should be free from chemicals which are
introduced to maintain the biological purity of the water.
These materials, mostly chlorides, are detrimental to the
assemblies cleaned because they introduce a fresh
amount of ionizable material.

TL/F/8766-25

CONFORMAL COATING
Conformal coating is recommended for high-reliability PCBs
to provide insulation resistance, as well as protection
against contamination and degradation by moisture.
Requirements:
• Complete coating over components and solder jOints.
• Thixotropic material which will not flow under the packages or fill voids, otherwise will introduce stress on solder
jOints on expansion.
• Compatibility and possess excellent adhesion with PCB
material/components.
• Silicones are recommended where permissible in
application.

5-33

II

Qr-------------------------------------------------------~

~

~

SMD Lab Support
Techniques-Develop techniques for handling different
materials and processes in surface mounting.
Equipment-In conjunction with equipment manufacturers.
develop customized equipments to handle high denSity.
new technology packages' developed by National.
In-House Expertise-Availability of in-house expertise on
semiconductor research/development to assist users on
packaging queries.

FUNCTIONS

Demonstration-Introduce first-time users to surfacemounting processes.
Servlce-Invel!tigate problems experienced by users on
surface mounting. .
Reliability Builds-Assemble surface-mounted units for reliability data acquisition.

5-34

"l
::s

a.

tflNational Semiconductor

CD

3

::D

Land Pattern Recommendations

CD

g
3
3

CD

::s

a.

The following land pattern recommendations are provided as guidelines for board layout and assembly purposes.

a

These recommendations cover the following National Semiconductor packages: PLCC, PQFP, SOP, SSOP and TSOP.
For SOT-23 (5-Lead) and TO-263 (3- or 5-Lead) packages, refer to land patterns shown in the Physical Dimensions for MA05A
and TS3B or TS5B packages, respectively.

rr

Plastic Leaded Chip Carriers (PLCC)

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Lead Tip Lead Tip Lead Lead/Pad Inner Pad
Inner Pad
Outer Pad
Outer Pad Land
Body Body
Count
Size Size
to Tip
to Tip Width
Pitch
to Pad Edge to Pad Edge to Pad Edge to Pad Edge Width
No.
(mm) (mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
20

10.03

10.03

0.53

1.27

6.73

11.43 11.43

28

12.57

12.57

0.53

1.27

9.27

9.27

13.34

13.34

0.63

11.43 14.05

32

12.57

15.11

0.53

1.27

9.27

12.00

13.34

16.00

0.63

16.51

16.51

44

17.65

17.65

0.53

1.27

14.35

14.35

18.42

18.42

0,63

19.05 19.05

52

20.19

20.19

0.53

1.27

16.89

16.89

20.96

20.96

. 0.63

24.13 24.13

68

25.27

25.27

0.53

1.27

21.97

21.97

26.04

26.04

0:63

29.21

84

30.35

30.35

0.53

1.27

27.05

27.05

31.1.2

31.12

0.63

8.89

8.89

29.21

6.73

10.80

10.80

0.63

III
5-35

Plastic Quad Flat Packages (PQFP)

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Size

(mm) (mm)

7

7

'B'
A
A'
W
P
B
X
Lead Lead/Pad Inner Pad
Inner Pad
Outer Pad
Outer Pad
Land
Width
Pitch
to Pad Edge toPadEd~e to Pad Edge to Pad Edge Width

L

L'

No.

to Tip
(mm)

to Tip
(mm)

(mm)

(mm)

(mm)

(mm)

(mm)

(mm)

(mm)

40

9.29

9.29

0.26

0.50

7.50

7.50

9.78

9.78

0.30

Lead
Lead Tip Leadnp
COllnt

"

7

7

48

9.40

9.40

0.27

0.50

6.88

6.90

10.42

10.40

0.32

10

10

44

13.35

13.35

0.45

0.80

10.53

10.53

14.47

14.47

0.55

10

10

52

14.15

14.15

0.38

0.65

9.08

9.08

15.17

15.17

0.43

12

12

64

14.00

14.00

0.38

0.65

11.48

11.48

15.02

15.02

0.43

14

14

80

18.15

18.15

.0.38

0.65

13.08

13.08

19.17

1.9.17

0.43

14

20

80

17.80

23.80

0.35

0.80

13.50

19.50

18.50

24.50

0.40

14

14

100

17.45

17.45

0.30

0.50

13.08

13.08

18.47

18.47,

0.35

'14

20 • ",100

17.80 '

23.80

0.30

0.65

13.50

19.50

18.50

24.50

0.35,

20'

20

'100

24.30

18.30

0.40

0.65

21.28

15.28

25.32

19.32

0.45

24

24

132

24.21

24.21

0.30

0.64

21.67

21.67

25.23

25.23

0.40

28

28

120

32.15

32.15

0.45

0.80

27.88

27.88

33.17

33.17

0.55

28

28

128

31.45

31.45

0.45

0.80

28.03

28.03

32.47,

32.47

0.55

28

28

144

32.15

32.15

0.38

0.65

28.03

'28.03

33.17

33.17

0.43

28

28

160

32.40

32.40

0.38

0.65

29.48

29.48

33.42

33.42

28

28

208

30.60

30.60

0.30

0.50

28.08

28.08 '

31;62

31.62

5-36

I

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0.43
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0.35

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JEDEC Small Outline and Shrink Small Outline Packages (SOP and SSOP)

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Lead
Count
No.

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(In)

A

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Lead Tip
to Tip
(In)

W
Lead
Width
(In)

P
Lead/Pad
Pitch
(in)

Inner Pad
to Pad Edge
(in)

B
Outer Pad
to Pad Edge
(In)

Pad
Width
(in)

o·
i

X

SOP

0.150

8

0.144

0.244

0.020

0.050

0.094

0.294

0.028

0.150

14

0.144

0.244

0.020

0.050

0.094

0.294

0.028

0.150

16

0.144

0.244

0.020

0.050

0.094

0.294

0.028

0.300

14

0.3300

0.4100

0.0190

0.0500

0.2800

0.4600

0.0270

0.300

16

0.3300

0.4100

0.0190

0.0500

0.2800

0.4600

0.0270

0.300

20

0.3300

0.4100

0.0190

0.0500

0.2800

0.4600

0.0270

0.300

24

0.3300

0.4100

0.0190

0.0500

0.2800

0.4600

0.0270

0.300

28

0.3300

0.4100

0.0190

0.0500

0.2800

0.4600

0.0270

SSOP

0.150

20

0.185

0.241

0.010

0.025

0.145

0.281

0.014

0.150

24

0.185

0.241

0.010

0.025

0.145

0.281

0.014

0.300

48

0.340

0.420

0.012

0.025

0.300

0.460

0.016

0.300

56

0.340

0.420

0.012

0.025

0.300

0.460

0.016

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No.

to Shoulder

L
Lead Tip
to Tip

(mm)

(mm)

W
Lead
Width
(mm)

5,300

14

6.280

8.000

0.400

1.270

5.300

16

6.280

8.000

0.400

1.270

5.300

20

6.280

8.000

0.400

5.300

20

6.600

8.100

5.300

24

6.600

8.100

D

C

Lead
Count

Body

,Size
(mm)

Shoulder

A

P

X

B
Outer Pad
to Pad Edge

Lead/Pad .'
Inner Pad
Pitch
to Pad Edge
(mm)
(mm)

(mm)

Pad
Width
(mm)

5.010

9.270

0.600

5.010

9.270

0.600

1.270

5.010

9.270

0.600

0.400

0.650

5.584

9.116

0.451

0.400

0.650

5.584

9.116

0.451

SOP TYPE II

SSOPTYPEII

SSOPTYPEIII

7.500

I
I

40

TSOPTYPEI

18.500

32

I
I

8.900 .

19.000

I
I

10.500

20.200

I
I

0.350

0.250

I
I

0.650

0.500

I
I

7.884

17.984

I
I

11.516

21.216

I
I

0.452

0.301

Section 6
Appendicesl
Physical Dimensions

Section 6 Contents
Appendix A General Product Marking and Code Explanation .............................
Appendix B Device/Application Literature Cross-Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix C Summary of Commercial Reliability Programs ...............................
Appendix D Military Aerospace Programs from National Semiconductor...... . ......... . ..
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . . . . . . . . .
Appendix F How to Get the Right Information from a Datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

6·2

6-3
6-4
6-10
6-11
6-21
6-26
6-30

tflNational Semiconductor

Appendix A
General Product Marking & Code Explanation
LF

11
356

N

Package Type

IA+

I

0

GlasslMetal DIP
Ceramic Leadless Chip Carrier (LCC)
GlasslMetal Flat Pak (%" x %")
12 Lead TO-8 Metal Can (MIG)
Multi-Lead Metal Can (MIG)
4 Lead M/C (TO-5) } Shipped with
4 Lead M/C (TO-46)
Thermal Shield
Lo-Temp Ceramic DIP
8 Lead Ceramic DIP ("MiniDIP")
14 Lead Ceramic DIP (-14 used only when
product is also available in -8 pkg).
K
TO-3 M/C in Steel, except LM309K
which is shipped in Aluminum
TO-3 M/C (Aluminum)
KC
KSteel TO-3 M/C (Steel)
M
Small Outline Package
M3
3-Lead Small Outline Package
5-Lead Small Outline Package
M5
N
Molded DIP (EPOXY B)
N-01
Molded DIP (Epoxy B) with Staggered Leads
N-8
8 Lead Molded DIP (Epoxy B) ("Mini-DIP")
N-14
14 Lead Molded DIP (Epoxy B)
(-14 used only when product is also
available in -8 pkg).
P
3 Lead TO-202 Power Pkg
Q
Cerdip with UV Window
S
3,5,11, & 15 Lead TO-263 Surf. Mt. Power Pkg
3,5,11,15 & 23 Lead TO-220 PWR Pkg (Epoxy B)
T
Multi-lead Plastic Chip Carrier (PCC)
V
W
Lo-Temp Ceramic Flat Pak
WM
Wide Body Small Outline Package

R.;",,,,(Rilfer
""""'"
(OptioooJ'
to Appendix C)

E
F
G
H
H-05
H-46
J
J-8
J-14

Package Type (See Right)
Device Number (Generic Type)
and Suffix Letter (Optional)
A or B: Improved
Electrical
Specification
C,I, E or M: Temperature
Range
Device Family (See Below)

Device Family
ADC
AF
AH
DAC
OM
HS
LF
LH
LM
LMC
LMD
LP
LPC
MF
LMF

Data Conversion
Active Filter
Analog Switch (Hybrid)
Data Conversion
Digital (Monolithic)
Hybrid
Linear (BI-FETTM)
Linear (Hybrid)
Linear (Monolithic)
Linear CMOS
LinearDMOS
Linear (Low Power)
Linear CMOS (Low Power)
Linear (Monolithic Filter)
Linear Monolithic Filter

DATE CODE
1ST DIGIT - CALENDAR YEA.R
2ND DIGIT - 6-WEEK PERIOD
IN CALENDAR YEAR
3RD a: 4TH DIGITS - WAFER LOT COpE

DATE CODE
NON-MILITARY
2ND DIGIT - CALENDAR YEAR
3RD & 4TH DIGITS - CALENDAR WORK WEEK
MILITARY - 8831: M38510
I sa 2ND DIGITS - CALENDAR YEAR
3RD 6: 4TH DIGITS - CALENDAR WORK WEEK
(EXAMPLE: 9201 1ST WEEK OF 1992)

=

INDICATES PLANT
OF MANUFACTURE

MILITARY ONLY

[sD
INDICATES PLANT
OF MANUFACTURE

(ELECTROSTATIC DISCHARGE)
SENSITIVITY INDICATOR

LOGO
PART NUUBER
PIN 1 ORIENTATION

WAFER LOT
CODE
--.."cc...::=",-

TL/XX/OO27-3

PIN I ORIENTATiON

TL/XX/OO27 -2

6-3

t!lNational Semiconductor

Appendix B
DevicelApplication Literature Cross-Reference
Device Number

Application Literature

ADCXXXX .............. ; ....•.....•.......................................................................AN-i56
ADCSO ...................................................................................................AN-360
ADC080i ................ ; ..................•................ AN-233, AN-27i, AN-274, AN-280, AN-28i, AN-294, LB-53
ADC0802 ................................................................... AN-233,AN-274, AN-280, AN-281, LB-53
ADC0803 ............................•...................................... AN-233, AN-274, AN-280, AN-28i, LB-53
ADC0803i ................................................................................................AN-460
ADC0804 .......... ; ................................. AN-233, AN-274, AN-276, AN-280, AN-28i, AN-30i, AN-460, LB-53
ADC0805 ...........•...............•....................................... AN-~33,AN-274, AN-280, AN-28i, LB-53
ADC0808 ..................................................................................AN-247, AN-280, AN-28i
ADC0809 ............................•....................................•......•................AN-247,AN-280
ADC08i6 .................................... '...................................... AN-i93, AN-247, AN-258, AN-280
ADC08i7 ..................................................................................AN-247, AN-258, 'AN-280
ADC0820 .................................................................................................AN-237
ADC083i .........................................................................................AN-280, AN-28i
ADC0832 ....................................•..........•..................•......................AN-280,AN-28i
ADC0833 ..............................................................................•..........AN-280,AN-28i
ADC0834 ..... : ...................................................................................AN-280,AN-28i
ADC0838 .........•..•..............•...................•.........................................AN-280,AN-28i
ADCi00i ..................................................................................AN-276, AN-280, AN-28i
ADCi005 .................................................................................................AN-280
ADCi046i ................................................................................................AN-769
ADCi0462 .....................' ...... ;' .................................................................... AN-769
ADC10464 ...................................................................•..........................•.AN-769
ADCi0662 ..........•....................•................................................................AN-769
ADCi0664 .....................•..................................................•'....................... AN-769
ADCi2030 ................................................................................................AN-929
ADCi2032 .............•..................................................................................AN-929
ADCi2034 ................................................................................................AN-929
ADCi2038 ......•.......•.•...........•.......................•..............•............................AN-929
ADCi2H030 .... ; ... '.......................................................................................AN-929
ADCi2H032 ...............................................................................................AN-929
ADCi2H034 ................................•................................•.............................AN-929
ADCi2H038 ........ , ........•............•.. , ..................................................•..... , .... AN-929
ADCi2L030 .. , ..............•.............................................................................AN-929
ADCi2L032 ....................•..........................................................................AN-929
ADCi2L034 ...............................................................................................AN-929
ADCi2L038 .......•.......................................................................................AN-929
ADCi2i0 •.................................................................................,............... AN-245
ADCi244i ........................•.......................................................................AN-769
ADCi245i ........•................•........................•..............•..................•...........AN-769
DACXXXX .................................................................................................AN-i56
DAC0800 ..................................... , ........................................................... AN-693
DAC0830 .................................................................................................AN-284
6-4

Device!Application Literature Cross-Reference (Continued)
Device Number

Application Literature

DAC0831 .........................................................................................AN-27l,AN-284
DAC0832 .........................................................................................AN-27l , AN-284
DAC1006 ..................................•.......................................AN-27l, AN-275, AN-277, AN-284
DAC1007 ..........................................................................AN-27l, AN-275, AN-277, AN-284
DAC1008 .......................................................................... AN-27l, AN-275, AN-277, AN-284
DAC1020 ................................................................. AN-263, AN-269, AN-2293, AN-294, AN-299
DAC102l .................................................................................................AN-269
DAC1022 ................................................................................•................AN-269
DAC1208 .........................................................................................AN-27l,AN-284
DAC1209 .........................................................................................AN-27l , AN-284
DAC12l0 .........................................................•............................... AN-27l , AN-284
DAC12l8 .................................................................................................AN-293
DAC12l9 .................................................................................................AN-693
DAC1220 ......................................................................................... AN-253, AN-269
DAC122l .................................................................................................AN-269
DAC1222 .................................................................................................AN-269
DAC1230 .................................................................................................AN-284
DAC1231 ......................................................................................... AN-27l,AN-284
DAC1232 .........................................................................................AN-27l,AN-284
DAC1280 .........................................................................................AN-261,AN-263
DH0034 ...................................................................................................AN-253
DH0035 ....................................................................................................AN-49
INS8070 ..........•..................................................•....................................AN-260
LFlll ......................................................................................................LB-39
LF155 ..........................................................•.................................AN-263,AN-447
LF198 ............................................................................................AN-245, AN-294
LF311 ...........................................................................••....•..................AN-301
LF347 ....................................... AN-256, AN-262, AN-263, AN-265, AN-266, AN-301, AN-344, AN-447, LB-44
LF351 .......................................... AN-242, AN-263, AN-266, AN-271, AN-275, AN-293, AN-447, Appendix C
LF351 A ......................................................................•........................•...AN-240
LF351B ....•.............................................•............................................AppendixD
LF353 .................... AN-256, AN-258, AN-262, AN-263, AN-266, AN-27l, AN-285, AN-293, AN-447, LB-44, Appendix D
LF356 ..................................................... AN-253, AN-258, AN-260, AN-263, AN-266, AN-271, AN-272,
AN-275, AN-293, AN-294, AN-295, AN-30l, AN-447, AN-693
LF357 ......................................................................................AN-263,AN-447, LB-42
LF398 ......................................•........................ AN-247, AN-258, AN-266, AN-294, AN-298, LB-45
LF411 .............................................................................AN-294, AN-301 , AN-344, AN-447
LF4l2 .....................................................................AN-272, AN-299, AN-301, AN-344, AN-447
LF441 ............................................................................................AN-301 , AN-447
LF13006 ..................................................................................................AN-344
LF13007 ..................................................................................................AN-344
LF13331 ...............................................•..........•...............................AN-294,AN-447
LH0002 ....•................................................................ AN-13, AN-227, AN-263, AN-272, AN-30l
LH0024 ...............•..........•........................................................................AN-253
LH0032 ..........................•................................................................AN-242, AN-253
LH0033 ....................................•............................................... AN-48, AN-227, AN-253
LH0063 .•...................................................................................•.............AN-227
LH0070 ...............................•.......................•...........................................AN-301
LH0071 ........................................•........................•...•.............................AN-245
LH0094 ...................................................................................................AN-301
LH0101 .........................................................................................•.........AN-261
6-5

~ r-----------------------------------------------------------------------------~
C)

C

~

a:..

DevicelApplication Literature Cross-Reference (Continued)
Device Number'

Application Literature

LH1605 ................•....•..........................................•................•.................AN-343

'1

LH2424 ........•........•..•...........•.......•....•........•.•..••.•...•..•............................ ~ AN-867

Co)

LM10 .......•............................... AN-211. AN-247. AN-258. AN-271. AN-288. AN-299. AN-3OD. AN-460. AN-693

f

LM11 .................•....• , ..............••.••.•••..•........•........•.. AN-241. AN-242. AN-260. AN-266. AN-271

~

LM12 '.............. ; .......•.......•.•.................................................... AN-446. AN-693. AN-706
LM101 ....................•.......•.......•....•......•.....•.•..•..•. AN-4. AN-13. AN-20. AN-24. L8-42. Appendix A
LM101A ........•.•....... AN-29. AN-30. AN-31. AN-79. AN-241 AN-711. L8-1. L8-2. L8-4. L8-8. L8-14. L8-16. L8-19. L8-28

c
.2

LM102 ...... '.....................••.........•......................•....AN-4. AN-13. AN-30. L8-1. L8-5. L8-6. L8-11

:s.

LM105 ............••...............•..........................•....•..........................AN-23. AN-110. L8-3

tii
C)

i

LM103 .................................................................•...................•.......AN-110.L8-41
LM106 •.................•.................................................•.•...................AN-41. L8-6. L8-12
LM107 ................................................................. AN-20.AN-31. L8-1. L8-12. L8-19. Appendix A
LM108 ••....................................•....... AN-29. AN-30. AN-31. AN-79. AN-211. AN-241. L8-14. L8-15. L8-21
LM108A .......................•......................•................•.....•................AN-260.L8-15. L8-19
LM109 ....•.......•.......................................................................•.........AN-42. L8-15
LM109A ...........................................................................•.........•...•.......•..L8-15
LM110 .......... , .. " ., ................... , ........ , .......•...•.......... , ..•............. , ......... L8-11. L8-42
LM111 ...........................•.•............................•......... AN-41. AN-1 03. L8-12. L8-16. L8-32; L8-39
LM112 .; •...............................................•...........................•............••.......•. L8-19
LM113 ...................................•................................ AN-56. AN-110. L8-21. L8-24. L8-28. L8-37
LM117 ...........•...•.............•..............................•.......... AN-178. AN-181. AN-182. L8-46. L8-47
LM117HV ....••...................•.......•............•............•......................•....•.... L8-46. L8-47
LM118 ...............•...................•...............................•..• L8-17. L8-19. L8-21. L8-23. Appendix A
LM119 ................................................•.............................•......................L8-23
LM120 .......................•.........••..•........•.....••..••...........•.•.•.•.•••.•.......•..........AN~182
LM121 .............................................................•.........AN-79. AN-104. AN-184. AN-260. L8-22
LM121A •.............................................••.................................•..................L8-32
LM122 ...........••.................. : ..•...••••................•.....................•........•..•. AN-97. L8-38
LM125 ....... : ..................•..•.. : : ...................................................................•. AN-82
LM126 ...........................................................................•.................•.......AN-82
LM129 •.........•.•....••..................•..••...•.............................. AN-173. AN-178. AN-262. AN-266
LM131 •........ ."......•................................................................AN-210.AN-460. Appendix D
LM131A ...............................•...•........•................................•....................AN-210
LM134 ..... ;' ..........................•........... ; .......•.......................................• L8-41.AN-460
LM135 ..•................................................................. AN-225. AN-262. AN-292. AN-298. AN-460
LM137 ................. ; ...............•..........•.....•................................................... L8-46
LM137HV ...•..............••....................................•....•...•....•..•......................... L8-46
LM138 ......................' .........................................................•.....................L8-46
LM139 .. " . " •..•........ " .•..... , .• " ....•.......... , ••.•..•.•.... " . " ., ..•..•.•......•. , .. " ........... AN-74
LM143 ................................•...........................................................AN-127. AN-271
LM148 ..............................•.................................................................. , .. AN-260
LM150 ..•....•.....................................................................•........................L8-46
LM158 ...... ; ...........•.......•......•...............•..•..•......................................•.....AN-116
LM160 .....................................................................................................AN-87
LM161 ......................•....................•..••...•..•..........•...........•..........••...AN-87.AN-266
LM163 ...•................................•...•.•..••.•....•.............•...•.•.......•.....•....•........AN-295
LM194 .....................................••....................................•......•........•.AN-222. L8-21
LM195 .......................................................................•.•.......................•..•AN-110
LM199 ...................................' ....................•...•..........•..•.................. AN-161.AN-260
LM199A ..................................•.........•....•.......•.....•.•.........••.•.................•.•AN-161
LM211 ........•........•......•............................................................................ L8-39
6-6

Device/ Application Literature Cross-Reference (Continued)
Device Number

Application Literature

LM231 ....................................................................................................AN-2l0
LM231A .............. : ....... : ...........................................................................AN-2l0
LM235 ....................................................................................................AN-225
LM239 .....................................................................................................AN-74
LM258 ....................................................................................................AN-116
LM260 .....................................................................................................AN-87
LM261 .....................................................................................................AN-87
LM34 .....................................................................................................AN-460
LM35 .....................................................................................................AN-460
LM301A ...................................................................................AN-178, AN-18l, AN-222
LM308 ...........................................................,' . AN-88, AN-184, AN-272, LB-22, LB-28, Appendix 0
LM308A ............................................................................................AN-225, LB-24
LM309 ............................................................................................AN-178, AN-182
LM3ll ..................... AN-4l , AN-l 03, AN-260, AN-263, AN-288, AN-294, AN-295, AN-307, LB-12, LB·16, LB-18, LB-39
LM3l3 ....................................................................................................AN-263
LM3l6 .... , ...............................................................................................AN-258
LM3l7 ....................•..................................................................AN-178, LB-35, LB-46
LM3l7H ...... " .........................................•.................................................. LB-47
LM3l8 .............................................................................................AN-299, LB-2l
LM3l9 ............................................................•.......................AN-828, AN-27l, AN-293
LM320 ..............................................................................•.....................AN-288
LM321 ...............................................................................................•.....LB-24
LM324 ............................................. AN-88, AN-258, AN-274, AN-284, AN-30l, LB-44, AB-25, Appendix C
LM329 .................................................................... AN-256, AN-263, AN-284, AN-295, AN-30l
LM329B ........................................•............................................•............AN-225
LM330 ....................................................................................................AN-30l
LM331 .........................•...... AN-2l 0, AN-240, AN-265, AN-278, AN-285, AN-3ll, LB-45, Appendix C, Appendix 0
LM331A .......................................................................................AN-2l0, Appendix C
LM334 ....................................................................................AN-242, AN-256, AN-284
LM335 ....................................................................................AN-225, AN-26.3, AN-295
LM336 ....................................................................................AN-202,AN-247, AN-258
LM337 ......................................................................................................LB-46
LM338 ............................................................................................... LB-49, LB-5l
LM339 .....................................................................................AN-74, AN-245, AN-274
LM340 ...........•..................................................•.............................AN-l 03, AN-182
LM340L. ..................................................................................................AN-256
LM342 ....................................................................................................AN-288
LM346 .............................................................................................AN-202, LB-54
LM348 .............................................................................................AN-202, LB-42
LM349 ........•............................................................................................LB-42
LM358 ................................................. AN-1l6, AN-247, AN-271, AN-274, AN-284, AN-298, AppendixC
LM358A ...............................................................................................Appendix 0
LM359 ....................................•............................................•...........AN-278, AB-24
LM360 .....................................................................................................AN-87
LM361 .............................................................................................AN-87,AN-294
LM363 ..... " ............................. " ...... " .....•........................................ " ...... AN-27l
LM380 ............•................................................................................AN-69,AN-146
LM385 ..........................• : •........................ AN-242, AN-256, AN-30l, AN-344, AN-460, AN-693, AN-777
LM386 ...............................................•.....................................................LB-54
LM391 .............................................................•......................................AN-272
LM392 ...........................................................................•................AN-274, AN-286
6-7

DevicelApplication Literature Cross-Reference (Continued)
Device Number

Application Literature

LM393 ............................................................................AN-271 , AN-274, AN-293, A~-694
LM394 ...................................................... AN-262, AN-263, AN-271, AN-293, AN-299, AN-311, LB-52
LM395 .................................•... : ........ AN-178, AN-181, AN-262, AN·263, AN-266, AN-301, AN-460, LB-28
LM399 ....................................................................................................AN-f84
LM555 ..............................................................................................AN-694,AB-7
LM556 ...•.................. : .............•................................................................. AB-7
LM565 .............................................................•...............................AN·46,AN-146
LM566 ....................................................................................................AN-146
LM604 ....................................................................................................AN-4f50
LM628 ............................................................................................AN-693,AN-706
LM629 ....................................................................................AN-693, AN-694, AN-706
LM709 .................................... : ......................................................... AN-24, AN:30
LM710 ..............................................................................................AN-41, LB-12
LM725 ......................................................................................................LB-22
LM741 ........................................................................................AN-79, LB-19, LB-22
LM833 ....................................................................................................AN-346
LM1 036 ...................................................................................................AN-390
LM1202 ...................................................................................................AN-867
LM1203 ...................................................................................................AN-861
LM1204 ...................................................................................................AN-934
LM1458 ...................................................................................................AN-116
LM1524 ...........................................................................AN-272, AN-288, AN-292, AN-293
LM1558 ...................................................................................................AN-116
LM1578A ................................................................•..........................•......AB-30
L.M1823 ...................................................................................................AN-391
LM1830 ....................................................................................................AB-10
LM1865 ...................................................................................................AN-390
LM1886 ...................................................................................................AN-402
LM1889 ...................................................................................................AN-402
LM1894 ...................................................................................AN-384,AN-386, AN-390
LM2419 ...................................................................................................AN-861
LM2577 ...........................................................................................AN-776, AN-777
LM2876 ........................................................................ : .......................... AN-898
LM2889 ...........................................................................................AN-391, AN-402
LM2907 ................. : ................•................................................................ AN-162
LM2917 ...................................................................................................AN-162
LM2931 ................•....................•......................•.......................................AB·12
LM2931CT ..................................•..............................................................AB-11
LM3045 ...................................................................................................AN-286
LM3046 ...........................................................................................AN-146, AN-299
LM3089 ...................................................................................................AN-147
LM3524 ...........................................................................AN-272, AN-288, AN-292, AN-29~
LM3525A .................................................................................................AN-694
LM3578A ..................................................................................................AB-30
LM3875 ....................•..............................................................................AN;!l98
LM3876 ...................................................................................................AN-898
LM3886 ....................•......................•.......................................................AN-898
LM3900 ............................................................... AN-72, AN-263, AN-274, AN-278, LB-20, AB-24
LM3909 ...................................................................................................AN-154
LM3914 ......................................................................................AN-460, LB-48, AB-25
LM3915 ................................•..................................................................AN-386
LM3999 ...................................................................................................AN-161
6-8

DevicelApplication Literature Cross-Reference (Continued)
Application Literature

Device Number

LM4250 .............................................................................................AN-88, LB-34
LM6181 ...........................................................................................AN-813, AN-840
LM7800 ...................................................................................................AN-178
LM12404 ..................................................................................AN-906, AN-947, AN-949
LM12458 ..................................................................................AN-906, AN-947, AN-949
LM12H454 ................................................................................AN-906, AN-947, AN-949
LM12H458 ................................................................................AN-906,AN-947, AN-949
LM12L458 .................................................................................AN-90a, AN-947, AN-949
LM18293 .................................................................................................AN-706
LM78L12 .................................................................................................AN-146
LM78S40 .................................................................................................AN-711
LMC555 .........................................................................•................ AN-460, AN-828
LMC660 ...........•......................................................................................AN-856
LMC835 ..................................................................................................AN-435
LMC6044 .................................................................................................AN-856
LMC6062 .......................................................•.........................................AN-856
LMC6082 .................................................................................................AN-856
LMC6484 .................................................................................................AN-856
LMD18200 ........................................................................................ AN-694, AN-828
LMF40 .......................................................... , ........... , .. , .............. , ........... AN-779
LMF60 .......................................... , ................... , ........................... , .... , .... AN-779
LMF90 ............. , ......... , ...... , ............ , ... , .. , .. , ...... , ................ , .. , .. " ............... AN-779
LMF100 .............. , ...... , .................. " ............ , ..... , .............................. , ...... AN-779
LMF380 ., .........•...... , ................... , .. , ......... , ............................. , .......... ,., ... AN-779
LMF390 .........................•..... , ......... , ................................................. , ...... AN-779
LP324 ... , .................. , ..... , ....... , .. , ... ,., .. , ... , ...................... , ...... " ........ , ....... AN-284
LP395 ................................. , ......... , ... , ..... , .....................•.... , ................... AN-460
LPC660 ..... , .... ,.,., ....... , ..... , ............. , ......... , .... , ............ , .......... , ............ , ... ,AN-856
MF4 ................................... , ......... , ...... , .. , .............................................. AN-779
MF5 ........................................................ , ............................................. AN-779
MF6 ..... , ......... , ......................... , ...... , . , .... , .......... , . , ..... , ................... , .. , .... AN-779
MF8 ......................................................................................................AN-779
MF10 ............. , ......... , ................... , ...... , ..... , .................................... AN-307, AN-779
MM2716 .... , ... , ..... , .....•................. , ................................ ,., .. , ....... , .............. LB-54
MM54104 ...................................................................................AN-252, AN-287, LB-54
MM57110 ................ , ... , .... , .... ,., ............... ,., ... ,.,.,., ............ ,., .... , ........ , ....... AN-382
MM74COO., .................. , .................................... , ........ , .............. , .. , ............. AN-88
MM74C02 ...... , ... ,., ... , ......... , ......................... , ... , ............................. , .. , ... , .... AN-88
MM74C04 .................... , ...... , .............. , ................. , ...................... " ... , ......... AN-88
MM74C948 ............ , ...... , ............... , ............. , ............ , ..... , ........................... AN-193
MM74HC86 ............... , .. , ........ ,., ... ,." ............ , ...................... ,., ............ AN-861,AN-867
MM74LS138 ..... , ................................ , .......................................... , .............. LB-54
MM53200, ................... , .................. , .......... , ......... , ............ , ..... , ................. AN-290
2N4339 ............ , ............. , ..... , ....... , ..................... , ....... , ............... , ...... , ...... AN-32

6-9

tiJNati()nal Semiconductor

Appendix C
Summary of Commercial Reliability Programs
P + Product Enhancement
The P + product enhancement program involves dynamic
tests that screen out assembly related and silicon defects
that can lead to infant mortality and/or reduce the surviva-

bility of the device under high stress conditions. This program includes but is not limited to the following power
devices:
Package Types

Device

TO-3
KSTEEL

To-39
(H)

LM12

X

LM109/309

X

X

LM117/317

X

X

LM117HV1317HV

X

X

LM120/320

X

X

LM123/323

X

TO-220

(T)

DIP
(N)

SO
(M)

X

TO-263
(S)

X

X

LM133/333

X

LM137/337

X

X

LM137HV/337HV

X

X

LM138/338

X

X

LM140/340

X

X

LM145/345

X

LM150/350

X

LM195/395

X

X
X

X

X

X

LM2930/2935/2984

X

X

LM2937

X

X

LM2940/2941

X

X

LM2990/2991

X

LM2575/2575HV

X

LM2576

X

LM2577

X

LMD18200/18201

X

6-10

X
X

X

X

X

X

X

X

t;tINational Semiconductor

Appendix D
Military Aerospace Programs
from National Semiconductor
This appendix is intended to provide a brief overview of
military products available from National Semiconductor. The process flows and catagories shown below are
for general reference only. For further Information and
availability, please contact the Customer Response
Center at 1-800-272-9959, Military/Aerospace Mark,eting
group or your local sales office.
National Semiconductor's Military/Aerospace Program is
founded on dedication to excellence. National offers complete support across the broadest range of products with
the widest selection of qualification levels and screening
flows. These flows include:

Process Flows
(Integrated Circuits)

6-11

Description

JANS

OML products processed to
MIL-I-38535 Level S or V for Space
level applications.

JANB

OML products processed10
MIL-I-38535 Level B or 0 for
Military applications.

SMD

OML products processed to a
Standard Microcircuit Drawing with
Table I Electricals controlled by
DESC.

883

OML products processed to
MIL-STD-883 Level B for Military
applications.

MLP

Products processed on the
Mon!tored Line (Program)
developed by the Air Force for
Space level applications.

-MIL

Similar to MIL-STD-883 with
exceptionS noted on the Certificate
of Conformance.

MSP

Military Screening Products for
initial release of advanced
products.

MCP

Commercial products processed in
a military assembly. Electrical
testing performed at 25°C, plus
minimum and maximum operating
temperature to commercial limits.

MCR

Commercial products processed in
a military assembly. Electrical
testing performed at 25°C to
commercial limits

MRP

Military Ruggedized Plastic
products processed to avionics
requirements.

MRR

Commercial Ruggedized plastic
product processed in a commercial
assembly with electrical testing at
25°C.

MPC

Commercial plastic products
processed in a commercial
assembly with electrical testing at
25°C.

National offers both 883 Class Band 883 Class S product. The screening requirements for both classes of product are outlined in Table III.
As with SMDs a manufacturer is allowed to use his standard electrical tests provided that all critical parameters
are tested. Also, the electrical test parameters, test conditions, test limits and test temperatures must be clearly
documented. At National Semiconductor, this information
is available via our Table I (formerly RETS, Reliability
Electrical Test SpeCification Program). The Table I document is a complete description of the electrical tests performed and is controlled by our QA department. Individual
copies are available upon request.
Some of National's products are produced on a flow similar to MIL-STD-883. These devices are screened to the
same stringent requirements as 883 product, but are
marked as -MIL; specific reasons for prevention of compliancy are clearly defined in the Certificate of Conformance (C of C) shipped with the product.
• Monitored Une Program (MLP):is a non JAN Level S
program developed by the Air Force. Monitored Line
product usually provides the shortest cycle time, and is
acceptable for application in several space level programs. Lockheed Missiles and Space Company in Sunnyvale, California, under an Air Force contract, provides
"on-site" monitOring of product processing, and as appropriate, program management. Monitored Line orders
generally do not allow "customizing", and most flows
do not include quality conformance inspection. Drawing
control is maintained by the Lockheed Company.
• Military Screening Program (MSP): National's Military
Screening Program was developed to make screened
versions of advanced products such as gate arrays and
microprocessors available more quickly. Through this
program, screened product is made available for prototypes and breadboards prior to or during the QML activities. MSP products receive the 100% screening of Table III, but are not subjected to Group C and 0 quality
conformance testing. Other criteria such as electrical
testing and temperature range will vary depending upon
individual device status and capability.

• QML: The purpose of the QML program, which is administered by the Defense Electronics Supply Center
(DESC), is to provide the military community with standardized products that have been manufactured and
screened to the highest quality and reliability standards
in facilities that have been certified by the government.
To achieve QML status, manufacturers must- submit
their facilities, quality procedures and design philosophies to a thorough audit aimed at confirming their ability to produce product to the highest design and quality
standards. They must be listed on DESC's Qualified
Manufacturer List (QML) before devices can be marked
and shipped as QML product.
Two processing levels are specified within MIL-I-38535,
the QML standard: Class S (typically specified for
space and strategic applications) and Class B (used for
tactical missile, airborne, naval and ground systems).
The requirements for both classes are defined within
MIL-STD-883. National is one of the industry's leading
suppliers of both classes.
• Standard MicrOCircuit Drawings (SMD). SMDs are issued to provide standardized versions of devices offered under QML. MIL-STD-883 screening is coupled
with tightly controlled electrical test specifications t.hat
allow a manufacturer to use his standard electncal
tests. Table I explains the marking of JAN devices, and
Table II outlines current marking requirements for QMLI
SMD devices. Copies of MIL-I-38535 and the QML can
be obtained from the Naval Publications and Forms
Center (5801 Tabor Avenue, Philadelphia, PA 19120,
212/697-2179. A current listing of National's SMD offerings can be obtained from our authorized distribu·
tors, our sales offices, our Customer Response Center
(Arlington, Texas, 8171468-6300), or from DESC.
• MIL·STD·883. Originally intended to establish uniform
test methods and procedures, MIL-STD-883 has also
become the general specification for non-SMD military
product. MIL-STD-883 defines the minimum requirements for a device to be marked and advertised as
883-compliant. Design and construction criteria, documentation controls, electrical and mechanical screening
requirements, and quality control procedures are out·
lined in paragraph 1.1.2 of MIL·STD-883.

6-12

~

TABLE I, JAN S or B Part Marking

r

TABLE I-A, JAN Package Codes

J~~O/X~X_XXYYY

JAN
Package
Designation

Lead Finish
A = Solder Dipped
B = Tin Plate
C = Gold Plate
X = Any lead finish above

Screening Level

A
B
C
D

S or B

E

Device Number on
Slash Sheet

F
G
H
I

is acceptable

Device Package
(see Table II)

L---

' - - - Slash Sheet Number

' - - - - - for radiation hard devices
this slash is replaced by the
Radiation Hardness Assurance
Designator (M, 0, R, or H of

J
K
L
M
N
P
Q

MIL-I-38535)
' - - - - - - MIL-M-3851 0
' - - - - - - - - - JAN Prefix
TLlXX/0030-1

R
S
T
U

V
W

X
Y
Z
2
3

CD
::::I

Microcircuit Industry Description
14-pin %" x %" (Metal) Flatpak
14-pin 3/'0" x %" (Metal) Flatpak
14-pin %" x %" Dual-In-Line
14-pin %" x %" (Ceramic) Flatpak
16-pin %" x 1fe" Dual-In-Line
16-pin %" x %" (Metal or Ceramic) Flatpak
B-pin TO-99 Can or Header
10-pin %" x %" (Metal) Flatpak
1O-pin TO-1 00 Can or Header
24-pin Yz" x 1%" Dual-In-Line
24-pin %" x %" Flatpak
24-pin %" x 1%" Dual-In-Line
12-pin TO-1 01 Can or Header
(Note 1)
B-pin %" x %" Dual-In-Line
40-pin 3/'6" x 21j,e Dual-In-Line
20-pin %" x 11j,e Dual-In-Line
20-pin %" x Yz" Flatpak
(Note 1)
(Note 1)
1B-pin %" x '0/, .. Dual-In-Line
22-pin %" x 1 'Is" Dual-In-Line
(Note 1)
(Note 1)
(Note 1)
20-terminal 0.350" x 0.350' Chip Carrier
2B-terminal 0.450" x 0.450" Chip Carrier

Note 1: These letters are assigned to packages by individual detail specifi·
cations and may be assignad 10 differenl packages in different specifica-

tions.

6-13

-a
-a

a.

:;C'

?
~

;:;

...
...0

I»

"<

~
CD

0

'0

I»

n

CD

..."'0
...

0
CO
I»

3

-...
0

0

3

Z

I»

0'

::::I

!!!.

en
CD
3

(;'
0
::::I

a.

-...
C

n
0

'TABLE lloA: SMD Package Code.

TABLEII.,Standard Military Drawing
(SMD) Marking

SMD
Package
Designation

~

5962-9319502MXA

~'-"";"

,

C
0
E
F
G
H
I

(Solder)

"

,

Package Codes
(see Table IIA)
Class Designalor
M = t-lIL-STD-883
B or Q = Class B
SorV=ClassC

-

Microcircuit Industry Description
14-pin Flatpak
14-pinCDIP
16-pin C DIP
16-pin Flatpak
B-pin TO-99 Can
10-pin (Metal) Flatpak
1O-pin TO-l 00 Can
(N9te2)
(Note 2)
B-pinCDIP
20-pin LCC
20-Pin DIP

X
y

Device Number

Drawing Number -

P
2

Year of Issue
The .. / .. and "-" can
be replaced by RHA
designations
D=10krad
R = 100 krad

R

Note 2: Thesa letters are assigned to packages by individual detail specHi·
cations and may be assigned to different packages in different specifica-

tions.

rederal Siock Class
TL/XX/OO30-2

TABLE III. 100% Screening Requirements
ClassS

Screen

Method

ClauB
Reqmt

Method

Reqmt

1.

Wafer Lot Acceptance

5007

All Lots

2.

Nondestructive Bond Pull (Note 14)

2023

100%

3.

Inte'rnal Visual (Note 1)

2020, Condition A

100%

2010, Condition B

100%

4.

Stabilization Bake (Note 16)

100B, Condition C, Min
24 Hrs. Min

100%

100B, Condition C, Min
24 Hrs. Min

100%

5.

Temperature Cycling (Note 2)

1010, Condition C

100%

1010, Condition C

100%

6.

Constant Acceleration

2001, Condition E Min
y 1 Orientation Only

100%

2001, Condition E Min

100%

7.

Visual Inspection (Note 3)

B.

Particle Impact Noise Detection (PIND)

9.

y 1 Orientation Only
100%

2010, Condition A (Note 4)

100%

100%

Serialization

(Note 5)

100%

10.

Interim (Pre-Burn-In) Electrical Parameters

Per Applicable Device
Specification (Note 13)

100%

Per Applicable Device
Specification (Note 6)

11.

Burn-In Test

1015
240 Hrs. @ 125°C Min
(Cond. F Not Allowed)

100%

1015
160 Hrs.

Per Applicable Device
Specification (Note 3)

100%

12.

Interim (Post Burn-In)
Electrical Parameters

6-14

100%
@

125°C Min

TABLE III. 100% Screening Requirements (Continued)
ClassS

Screen

13.

Reverse Bias Burn-In (Note 7)

ClassB

Method

Reqmt

1015; Test Condition A, C,

100%

72

Hrs.

Method

Reqmt

@ 150"C Min

(Cond. F Not Allowed)
14.

15.

Interim (Post-Bum-In) Electrical

Per Applicable Device

Parameters

Specification (Note 13)

PDA Calculation

5% Parametric (Note 14),

100%

Per Applicable Device

100%

Specification
All Lots

5% Parametric (Note 14)

All Lots

3% Functional
16.

Final Electrical Test (Note 15)

Per Applicable Device

Per Applicable Device

a) Static Tests

Specification

SpeCification

1) 25°C (Subgroup 1, Table I, 5005)

100%

100%

2) Max & Min Rated Operating Temp.

100%

100%

1) 25°C (Subgroup 4 or 7)

100%

100%

2) Max and Min Rated Operating Temp.

100%

100%

100%

100%

(Subgroups 2,3, Table I, 5005)
b) Dynamic Tests or Functional Tests

(Subgroups 5 and 6 or 8, Table I,
5005)
c) Switching Tests 25°C
(Subgroup 9, Table I, 5005)
17.

Seal Fine, Gross

1014

100%

1014

(Note 8)
18.

Radiographic (Note 10)

2012 Two Views

100%

19.

Qualification or Quality Conformance

(Note 11)

Samp.

2009

100%

100%
(Note 9)

(Note 11)

Samp.

Inspection Test Sample Selection
20.

External Visual (Note 12)

100%

. Note 1: Unless otherwise specified, at the manufacturer's option, test semples lor Group S, bond strenglh (Method 5005) may be randomly selected prior to or
following internal visual (Method 5004), prior to sealing provided all other specification requirements are setisfied (e.g., bond strenglh requirements shall apply to
each inspection lot, bond lailuras shall be counted even ff the bond would have lailed internal visual).
Note 2: For Class B devices, this test may be replaced with thermal shock Method 1011, Test Condition A, minimum.
Note 3: At the manufacturer's option, visual inspection for catestrophlc failures may be conducted alter each 01 the thermal/mechanical screens, alter the
sequence or alter seal tesl Catastrophic lailures are defined as missing leads, broken packages, or lids 011.
Note 4: The PIND test may be performed In any sequence alter step 6 and prior to step 16. See MIL-I·38565 paragrsph 40.6.3.
Note 5: Class S devices shall be serialized prior to Interim electrical parameter measurements.
Note 6: When specified, all devices shall be tasted lor those parameters requiring delta calculations.
Note 7: Reverse bias bum-in is a requirement only when specilied in the applicable device specification. The order 01 performing burn·in and reverse bias burn-In
may be inverted.
Note 8: For Class S devices, the seal tast may be performed in any sequence between step 16 and step t 9, but nshall be performed alter all shearing and lorming
operations on the terminals.
Note 9: For Class B devices, the fine and gross seal tests shall be performed separately or together In any sequence and order between step 6 and step 20 except
that thay shall be performed alter all shearing and forming operations on the terminals. When 100% seal screen cannot be performed alter shearing and forming
(e.g., flatpaks and chip carriers) the seal screen shall be done 100% prior to these operations and a semple test (LTPD = 5) shall be performed on each inspection
lot following these operations. If the sample fails, 100% rescreening shall be reqUired.
Note 10: The radiographic screen may be performed in any sequence alter step 9.
Note 11: Samples shall be selected for testing in accordance with lha specffic device class and lot requirements of Method 5005.
Note 12: External Visual shall be performed on the lot any time alter step 19 and prior to shipment
Note 13: Read and record is required at steps 10 and 12 only lor those parameters for which post-burn-in delta measurements are specified. All parameters shall
be read and recorded at step 14.
Note 14: The PDA shall spply to 'all subgroup 1 parameters at 25°C and all delta paremeters.
Note 15: Only one view is required for Ilat packages and leadless chip carriers with leads on all four sides.
Note 16: May be performed at any time prior to step 10.

6-15

Military Analog Products Available from National Semiconductor
Device

Package
Styles
(Note 1)

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

HIGH PERFORMANCE AMPLIFIERS AND BUFFERS
Wide BW.Quad JFET Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
Low Offset, Low Drift JFET Input
Low Offset, Low Drift JFET Input-Dual
Low Power JFET Input
Low Power JFET Input-Dual
Low Power JFET Input-Quad

SMD/JAN
883
883
883
883
883
8B3/JAN
883/JAN
883
883
883

K

Buffer Amp
1.0 Amp Power Op Amp
High Slew Rate Op Amp
Ultra Fast FET-Input Op Amp
0.2 Amp Power Op Amp
PowerOpAmp

" .. MIL"
"-MIL"
"-MIL"
"-MIL"
"-MIL"
"-MIL"

LM10
LM101A
LM108A
LM118
LM124
LM124A
LM146
LM148
LM158A
LM158
LM611AM
LM613AM
LM614AM
LM709A
LM741
LM747

H
J,H,W
J,H,W
J, H
J,E,W
J,E,W
J
J, E
J, H
J, H
J
J,E
J
H,J,W
J,H,W
J,H

Super-Block™ Micropower Op Amp/Ref
General Purpose Op Amp
Precision Op Amp
Fast Op Amp
Low Power Quad Op Amp
Low Power Quad
Quad Programmable Op Amp
Quad 741 Op amp
Low Power Dual Op Amp
Low Power Dual Op Amp
Super-Block Op Amp/Reference
Super-Block Dual Op Amp/Dual Comp/Ref
Super-Block Quad Op Amp/Ref
General.Purpose Op Amp
General Purpose Op Amp
General PurPose Dual Op Amp

LM6118
LM6121
LM6125
LM6161
LM6162
LM6164
LM6165
LM6181AM
LM6182AM

J,E
H,J
H
J,E,W
J,E,W
J,E,W
J,E,W
J
J

VIP Dual Op Amp
VIP Buffer
VIP Buffer with Error Flag
VIP Op Amp (Unity Gain)
VIP Op Amp (Av > 2, - 1)
VIP Op Amp (Av > 5)
VIP Op Amp (Av > 25)
VIP Current Feedback Op Amp
VIP Current Feedback Dual Op Amp

LMC660AM
LMC662AM
LPC660AM
LPC662AM
LMC6482AM
LMC6484AM

J
J
J
J
J
J

Low Power CMOS Quad Op Amp
Low Power CMOS Dual Op Amp
Micropower CMOS Quad Op Amp
Micropower CMOS Dual Op Amp
Rail to Rail CMOS Dual Op Amp
Rail to Rail CMOS Quad Op Amp

883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD

5962-9209301
5962-9209401
5962-9209302
5962-9209402
5962-9453401
5962-9453402

OP07

H

Precision Op Amp

883

-

LF147
LF155A
LF156
LF156A
LF157
LF157A
LF411M
LF412M
LF441M
LF442M
LF444M

D,J
H
H
H
H
H
H
H,J
H
H

LHOO02
LH0021
LH0024
LH0032
LH0041
LH0101

H

0
K
H
G
G

6-16

883/SMD
883/JAN
883/JAN
883/JAN
883/JAN
883/JAN
883
883/JAN
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/JAN
.883/JAN
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD

/11906

-

-

/11904
/11905

-

-

5962-87604
/10103
/10104
/10107
/11005
11'1006

-111001

5962-8771002
5962-8771001

7800701
/10101
/10102
5962-91565
5962-90812
5962-90815
5962-89621
5962-92165
5962-89624
5962-89625
5962-9081802
5962-9460301

Military Analog Products Available from National Semiconductor (Continued)
Device

Package
Styles
(Note 1)

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

COMPARATORS
LFlll
LH2111
LM106
LMlll
LM119
LM139
LM139A
LM160
LM161
LM193
LM193A
LM612AM
LM613AM

H
J,W
H,W
J,H,E,W
J,H,E,W
J,E,W
J,E,W
J, H
J,H,W
J, H
J,H
J
J, E

LM615AM
LM710A"
LM711A'
LM760

J
J,H,W
J,H,W
J, H

Voltage Comparator
Dual Voltage Comparator
Voltage Comparator
Voltage Comparator
High Speed Dual Comparator
Quad Comparator
Precision Quad Comparator
High Speed Differential Comparator
High Speed Differential Comparator
Dual Comparator
Dual Comparator
Dual-Channel Comparator/Reference
Super-Block Dual Comparator/
Dual Op Amp/ Adj Reference
Quad Comparator/Adjustable Reference
Voltage Comparator
Dual LM710
High Speed Differential Comparator

"-MIL"
883/JAN
883/SMD
883/JAN
883/JAN
883/JAN
883/SMD
883/SMD
883/SMD
883
883/JAN
883/SMD
883/SMD

=

883
883/JAN
883/JAN
883/SMD

-

883/SMD
883/JAN
883/JAN
883/JAN
883/SMD
883/SMD
883
"-MIL"
883/JAN
883
883
883/JAN
883/JAN
883
883
883
883
883/JAN
883/JAN
883/JAN
883
883
883
883
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883
883/JAN
883/SMD
883/SMD

5962-89588
/10701BXA
/1 0701 BYA
/11703,/11704
7703402XA
7703402YA

/10305
8003701
/10304
/10306
/11201
5962-87739
8767401
5962-87572

/11202
5962-93002
5962-93003

/10301
/10302
5962-87545

"Formerly manufactured by Fairchild Semiconductor as part numbers ".A71 0 and ".A711.

LINEAR REGULATORS
Positive Voltage Regulators
LM105
LM109
LM109
LM117
LM117HV
LMI17HV
LM123
LM138
LMI40-5.0
LMI40-6.0
LMI40-8.0
LM140-12
LM140-15
LM140-24
LMI40A-5.0
LM140A-12
LM140A-15
LMI40K-5.0
LM140K-12
LM140K-15
LMI40LAH-5.0
LM140LAH-12
LM140LAH-15
LM150
LM2940-5.0
LM2940-8.0
LM2940-12
LM2940-15
LM2941
LM431
LM723
LP2951
LP2953AM

H
H
K
H,E,K
H
K
K
K
H
H
H
H
H
H
K
K
K
K
K
K
H
H
H
K
K
K
K
K
K
H,K
H,J, E
H, E,J
J

Adjustable Voltage Regulator
5V Regulator, 10 = 20 rnA
5V Regulator,l o = lA
Adjustable Regulator
Adjustable Regulator, 10 = 0.5A
Adjustable Regulator, 10 = 1.5A
3A Voltage Regulator
5A Adjustable Regulator
0.5A Fixed 5V Regulator
0.5A Fixed 6V Regulator
0.5A Fixed 8V Regulator
0.5A Fixed 12V Regulator
0.5A Fixed 15V Regulator
0.5A Fixed 24V Regulator
1.0A Fixed 5V Regulator
1.0A Fixed 12V Regulator
1.0A Fixed 15V Regulator
t.OA Fixed 5V Regulator
1.0A Fixed 12V Regulator
1.0A Fixed 15V Regulator
100 rnA Fixed 5V Regulator
100 rnA Fixed 12V Regulator
100 rnA Fixed 15V Regulator
3A Adjustable Power Regulator
5V Low Dropout Regulator
8V Low Dropout Regulator
12V Low Dropout Regulator
15V Low Dropout Regulator
Adjustable Low Dropout Regulator
Adjustable Shunt Regulator
Precision Adjustable Regulator
Adjustable Micropower LDO
250 rnA Adj. Micropower LDO

6-17

--

/10702

--

/10703
/10704

-

/10706
/10707
/10708

-

5962-89587
5962-90883
5962-90884
5962-90885
TBD

-

/10201
5962-38705
5962-9233601

Military Analog Products Available from National Semiconductor (Continued)

oel(IC~

Package
Styles
(Note 1)

Description'

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

LINEAR REGULATORS (Continued)
Negative Voltage Regulators
LM120-5.0
LM120-M
LM120-12
LM120-15
LM120-5.0
LM120-12
LM120-15
LM137A
LM137A
LM137
LM137HV
LM137HV
LM145-5.0
LM145-5.2

H
H
H
H
K
K
K
H
K
H,K
H
K
K
K

Fixed 0.5A Regulator, Your = -5V
Fixed 0.5A Regulator, VOUT;= -8V
Fixed 0.5A Regulator, VOUT = -12V
Fixed 0.5A Regulator, VOUT = -15V
Fixed 1.0A Regulator, VOUT = ~5V
Fixed 1.0A Regulator, VOUT = -12V
Fixed 1.0A Regulator, VOUT = -15V
Precision Adjustable Regulator
Precision Adjustable Regulator
Adjustable Regulator
Adjustable (High Voltage) Regulator
Adjustable (High Voltage) Regulator
Negative 3 Amp Regulator
Negative 3 Amp Regulator

883/JAN
883
883/JAN
883/JAN
883/JAN
883/JAN
883/JAN
883/SMD
883/SMD
883/JAN
883/SMD
883/SMD
883/SMD
883

/11501

/11502
/11503
111505
111506
/11507
7703406XA
7703406YA
/11803, /11804
7703404XA
7703404YA
5962-90645

-

SWITCHING REGULATORS
LM1575-5
LM1575-12
LM1575-15
LM1575-ADJ
LM1'575HV-5
LM1575HV-12
LM1575HV-15
LM1575HV-ADJ
LM1577-12
LM1577-15
LM1577-ADJ
LM1578
LM78S40·

J,K
J,K
J,K
J,K
K
K
K
K
K
K
K
H
J

Simple Switcher™ Step-Down, VOUT = 5V
Simple Switcher Step-Down, VOUT = 12V
Simple Switcher Step-Down, VOUT = 15V
Simple Switcher Step-Down, Adj VOUT
Simple Switcher Step-Down, VOUT = 5V
Simple Switcher Step-Down, VOUT = 12V
Simple Switcher Step-Down, VOUT = 15V
Simple Switcher Step-Down, Adj VOUT
Simple Switcher Step-Up, VOUT = 12V
Simple Switcher Step-Up, VOUT = 15V
Simple Switcher Step..up, Adj VOUT
750 mA Switching Regulator '
Universal Switching Regulato~'Subsystem

883/SMD
883/SMD
883/SMD
883/SMD
883
883
883
883
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD

5962-9~ 67201
5962-91,67301
5962-9167401
5962-9167101

-

5962-921670~

5962-9216801
5962-9216601
5962-89586
5962-88761

'Formerly manufactured by Fairchild Semiconductor as the p.A78S40DMQB.

VOLTAGE REFERENCES
LM103-3.0
LM103-3.3
LM103-3.6
LM103-3.9
LMl13
LMl13-1
LMl13-2
LM129A
LM129B
LM136M!.5
LM136A-5.0
LM136-2.5
LM136-5.0

H
H
H
H
H
H
H

Reference Diode, BV =
Reference Diode, BV =
Reference Diode, BV =
Reference Diode, BV=

Reference Diode with 5% Tolerance
Reference Diode with 1 % Tolerance
Reference Diode with 2'% Tolerance'

883/SMD
883/SMD
883/SMD

H
H
H

Precision Reference, 10 ppm/DC Drift
Precision Reference, 20 ppml"C Drift
2.5V Reference Diode, 1% VOUT Tolerance
5V Reference Diode, 1,% VOUT Tolerance
2.5V Reference Diode, 2% VOUT Tolerance
5V Reference Diode, 2% VOUT Tolerance

883/SMD
883/SMD
883
883/SMD
883
883

Ii
H
H

3.0V
3.3V
3.6V
3.9V

6-18

883/SMD
883/SMD
883/SMD
883/SMD

7702806
7702807
7702808,
7702809
5962-8671101
5962-8671102
5962-8671103
5962-8992101 XA
5962-89921 ()2XA

8418001

-

-

Military Analog Products Available from National Semiconductor (Continued)

Device

Package
Styles
(Note 1)

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

VOLTAGE REFERENCES (Continued)

-5962-9041401

LM169
LM185B
LM185BX2.5
LM185BY
LM185BY1.2
LM185BY2.5
LM185-1.2
LM185-2.5

H
H,E
H
H
H
H
H,E
H,E

10V Precision Reference, Low Tempco 0.05% Tolerance
Adjustable Micropower Voltage Reference
2.5V Micropower Reference Diode, Ultralow Drift
Adjustable Micropower Voltage Reference
1.2V Micropower Reference Diode, Low Drift
2.5V Micropower Reference Diode, Low Drift
1.2V Micropower Reference Diode, Low Drift
2.5V Micropower Reference Diode, Low Drift

883
883/SMD
883/SMD
883
883/SMD
883/SMD
883/SMD
883/SMD

LM199
LM199A
LM199A-20

H
H
H

Precision Reference, Low Tempco
Precision Reference, UltralowTempco
Precision Reference, UltralowTempco

883/SMD
883/SMD
883

LM611AM
LM612AM
LM613AM
LM614AM
LM615AM

J
J
J,E
J
J

Super-Block Op Amp/Reference
Super-Block Dual-Channel Comparator/Reference
Super-Block Dual Op Amp/DuaIComp/Dual Ref
Super-Block Quad Op Amp/Reference
Super-Block Quad Comparator/Reference

883
883/SMD
883/SMD
883/SMD
883/SMD

LH0070-0
LH0070-1
LH0070-2

H
H
H

Precision BCD Buffered Reference
Precision BCD Buffered Reference
Precision BCD Buffered Reference

"-MIL"
"-MIL"
"-MIL"

-

ADC08020L
ADC0851

J
J

883/SMD
883/SMD

5962-90966
TBD

ADC0858

J

883/SMD

TBD

ADC08061CM
ADC1 0061 CM
ADC10062CM

J
J
J

883/SMD
883/SMD
883/SMD

TBD
TBD
TBD

ADC10064CM

J

883/SMD

TBD

ADC1241CM

J

883/SMD

5962-9157801

ADC12441CM
ADC1251CM

J
J

883/SMD
883/SMD

5962-9157802
5962-9157801

ADC12451CM
DAC0854CM

J
J

883/SMD
883/SMD

TBD
TBD

DAC1054CM

J

883/SMD

TBD

LM12458M
LM12H458M

EL,W
EL,W

8-Bit pP-Compatible
8-Bit Analog Data Acquisition
& Monitoring System
8-Bit Analog Data Acquisition
& Monitoring System
8-Bit Multistep ADC
1O-Bit Multistep ADC
1O-Bit Multistep ADC w/Dual
Input Mutiplexer
1O-Bit Multistep ADC w/Quad
Input Multiplexer
12-Bit Plus Sign Self-Calibrating
with Sample/Hold Function
Dynamically-Tested ADC1241
12-Bit Plus Sign Self-Calibrating
with Sample/Hold Function
Dynamically-Tested ADC1251
Quad 8-Bit D/A Converter
with Read Back
Quad 10-Bit D/ A Converter
with Read Back
12-Bit Data Acquisition System
12-Bit Data Acquisition System

883/SMD
883/SMD

5962-9319501
5962-9319502

5962-8759404

5962-8759405
5962-8759406
5962-8759401
5962-8759402
5962-8856102
5962-8856101

-

-5962-9300201
5962-9300301
5962-9300401
TBD

DATA ACQUISITION

6-19

•

(

Military Analog Products Available from National Semiconductor (Continued)
Package
Styles
(Note 1)

Device

Description

Process
Flows
(Note 2)

6th Order Butterworth Lowpass
6th Order Butterworth Lowpass
4th Order Elliptic Notch
Dual 2nd Order General Purpose

883/SMD
883/SMD
883/SMD
883/SMD

"

SMD/JAN
(Note 3)

DATA ACQUISITION SUPPORT
Switched Capacitor Filt rs
LMF60CMJ50
LMF600MJ100
LMF90CM
LMF100A

J
J
J
J, E

Sample and Hold
LF198

H

Motion Control
LMD18200-2

I
I

D

I
I

Monolithic Sample and Hold

Dual 3A, 55V H-Bridge

I
I

SMD/JA

883/JAN

5962-90967
5962-90967
5962-90968
5962-9153301

I
I

5962-87608
/12501
5962-9232501

Note 1: D: Side-Brazed DIP
Note 2: Process Flows
JAN ~ JM38510, Level B
E: leedless Ceramic Chip Carrier
G: Metal Cen (TO-8)
SMD ~ Standard Mili1arY Drawing
H: Metal Cen (T0-39, T0-5, TO-99, TO-l 00)
883 ~ Mll-STD-883 Rev C
J: Ceramic DIP
-Mil ~ Exceptions to 883C noted on
K: Metal Cen (TO-3)
Certificate of Conformance
W: Flatpek
Note 3: Please cali your local sales office to determine price and availability of space-leitel products. Ali "LM" prefix products in this guide are availble with spacelevel processing.

6-20

~

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t!lNational Semiconductor

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Appendix E
Understanding Integrated Circuit
Package Power Capabilities

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INTRODUCTION
The short and long term reliability of National Semiconductor's interface circuits, like any integrated circuit, is very dependent on its environmental condition. Beyond the mechanicall environmental factors, nothing has a greater influence on this reliability than the electrical and thermal stress
seen by the integrated circuit. Both of these stress issues
are specifically addressed on every interface circuit data
sheet, under the headings of Absolute Maximum Ratings
and Recommended Operating Conditions.

Failure rate is the number of devices that will be expected to
fail in a given period of time (such as, per million hours). The
mean time between failure (MTBF) is the average time (in
hours) that will be expected to elapse after a unit has failed
before the next unit failure will occur. These two primary
"units of measure" for device reliability are inversely related:
MTBF =

However, through application calls, it has become clear that
electrical stress conditions are generally more understood
than the thermal stress conditions. Understanding the importance of electrical stress should never be reduced, but
clearly, a higher focus and understanding must be placed on
thermal stress. Thermal stress and its application to interface circuits from National Semiconductor is the subject of
this application note.

FACTORS AFFECTING DEVICE RELIABILITY

EARLY UFE

"

USEFUL UFE

o

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::;:

1
Failure Rate

Although the "bathtub" curve plots the overall failure rate
versus time, the useful failure rate can be defined as the
percentage of devices that fail per-unit-time during the flat
portion of the curve. This area, called the useful life, extends
between tl and t2 or from the end of infant mortality to the
onset of wearout. The useful life may be as short as several
years but usually extends for decades if adequate design
margins are used in the development of a system.
Many factors influence useful life including: pressure, mechanical stress, thermal cycling, and electrical stress. However, die temperature during the device's useful life plays an
equally important role in triggering the onset of wearout.

Figure 1 shows the well known "bathtub" curve plotting failure rate versus time. Similar to all system hardware (mechanical or electrical) the reliability of interface integrated
circuits conform to this curve. The key issues associated
with this curve are infant mortality, failure rate, and useful
life.

m

i

FAILURE RATES vs TIME AND TEMPERATURE
The relationship between integrated circuit failure rates and
time and temperature is a well established fact. The occurrence of these failures is a function which can be represented by the Arrhenius Model. Well validated and predominantly used for accelerated life testing of integrated circuits, the
Arrhenius Model assumes the degradation of a performance
parameter is linear with time and that MTBF is a function of
temperature stress. The temperature dependence is an exponential function that defines the probability of occurrence.
This results in a formula for expressing the lifetime or MTBF
at a given temperature stress in relation to another MTBF at
a different temperature. The ratio of these two MTBFs is
called the acceleration factor F and is defined by the following equation:

~ WEAHOUT TIME
TL/H/9312-1

FIGURE 1. Failure Rate vs Time
Infant mortality, the high failure rate from time to to tl (early

F = Xl = exp
X2

[~

K

(.!. _2..)]
T2

Tl

Where: Xl = Failure rate at junction temperature Tl

life), is greatly influenced by system stress conditions other
than temperature, and can vary widely from one application
to another. The main stress factors that contribute to infant
mortality are electrical transients and noise, mechanical
maltreatment and excessive temperatures. Most of these
failures are discovered in device test, burn-in, card assem-·
bly and handling, and initial system test and operation. Although important, much literature is available on the subject
of infant mortality in integrated circuits and is beyond the
scope of this application note.

X2 = Failure rate at junction temperature T2
T = Junction temperature in degrees Kelvin
E = Thermal activation energy in electron volts
(ev)
K = Boltzman's constant

6-21

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r-----------------------------------------------------------------------------,
However, the dramatic acceleration effect of junction temperature (chip temperature) on failure rate is illustrated in a
plot of the above equation for three different activation energies in F/fJure 2. This graph clearly demonstrates the importance of the relationship of junction temperature to device failure rate. For example, using the 0.99 ev line, a 30"
rise in junction temperature, say from 130·C to 160"C, .resuits in a 10 to 1 increase in failure rate.

e:;- 1001II<

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flows from the chip to the ultimate heat sink, the ambient'
environment. There are, two predominant paths. The first is
from the die to the die attach pad to the surrounding package material to the package lead frame to the printed circuit
board and then to the ambient. The second path is from the
package directly to the ambient air.
Improving the thermal characteristics of any stage in the
flow chart of Figure 4 will result in an improvement in device
thermal characteristics. Howev,er, grouping all these characteristics into one equation determining the overall thermal
capability of an integrated circuit/package/environmental
condition is possible. The equation that expresses this relationship is:

r--r-~-r---;'---r.....,.,

lOOk t-+-t-+--'-+~F--I
10k

TJ = TA + Po (8JA>
Where: TJ = Die junction temperature

1k
100

TA '"' Ambient temperature in the vicinity device
10

Po = Total power dissipation (in watts)
8JA = Thermal resistance junction-tOoambient
, 60

'90

'120 150 160 210

8JA: the therrpal resistance from' device junction-to-ambient
temperature, is measured and specified by the manufacturers of integrated circuitS. National Semiconductor utilizes
special vehicles and methOds to measure and monitor this
parameter. All circuit data sheets specify the thermal characteristics and capabilities of the packages available for Ii
giVen device under specific conditions-these package
power ratings directly relate to thermal resistance junctionto;ambient or 8JA.

JUNCTION TEMP£IIATURE (·C)
TUH/9312 C 2

FIGURE 2. Failure Rate as a Function
of Junction Temperature
DEVICE THERMAL CAPABILITIES
There are many factors which affect the thermal capability
of art integrated circuit. To understand these we need to
understand the predominant paths for heat to transfer out of
the integrated circuit package. This is illustrated by Figures
Sand 4.
'
'

Although National provides these thermal ratings, it is critical that the end user understand how to ulie these numbers
to improve thermal characteristics in the development of his
system using IC components.

Figure 3 shows a cross-sectional view of an assembled integrated circuit mounted into ,a ~rnted circuit board.

Figure 4is a flow chart showing how the heat genl;!rated at
the power source, the junctions of the integrat8ct circuit

DEVICE LEAD

TLlH/9312-3

FIGURE 3. Integrated ClrcuH SOldered Into a Printed Circuit Board (Cross-Sectional View)

DIE
JUNCTION
(ENERGY
SOURCE)

~

DIE

~

DIE
AlTACH

Mil

~

PACKAGE
MATERIAL

~

LEAD
FRAME

~

PRINTED
CIRCUIT
BOARD

AIRFtLM
AROUND
PIICKAGE

~

AMBIENT

~

AMBIENT

TUH/9312-4

, FIGURE 4, Thermal Flow (Predominant Paths)

6-22

r--------------------------------------------------------------------,~

DETERMINING DEVICE OPERATING
JUNCTION TEMPERATURE

The slope of the straight line between these two points is
minus the inversion of the thermal resistance. This is referred to as the derating factor.

From the above equation the method of determining actual
worst-case device operating junction temperature becomes
straightforward. Given a package thermal characteristic,
8JA, worst-case ambient operating temperature, TA(max),
the only unknown parameter is device power dissipation,
PD. In calculating this parameter, the dissipation of the integrated circuit due to its own supply has to be considered,
the dissipation within the package due to the external load
must also be added. The power associated with the load in
a dynamic (switching) situation must also be considered.
For example, the power associated with an inductor or a
capacitor in a static versus dynamic (say, 1 MHz) condition
is Significantly different.

.
1
Derating Factor = - - 8
JA
As mentioned, Figure 5 is a plot of the safe thermal operating area for a device in a 16-pin molded DIP. As long as the
intersection of a vertical line defining the maximum ambient
temperature (70·C in our previous example) and maximum
device package power (600 mW) remains below the maximum package thermal capability line the junction temperature will remain below 150"C-the limit for a molded package. If the intersection of ambient temperature and package
power fails on this line, the maximum junction temperature
will be 150·C. Any intersection that occurs above this line
will result in a junction temperature in excess of 150·C and
is not an appropriate operating condition.

The junction temperature of a device with a total package
power of 600 mW at 70·C in a package with a thermal resistance of 63·C/W is 10S·C.
TJ = 70·C

+ (63·C/W) x

(0.6W) = 10S·C

The next obvious question is, "how safe is 10S·C?"
MAXIMUM ALLOWABLE JUNCTION TEMPERATURES

!:

la-PIN
2.4 r.---+-.-....,I--_+_ I
2.0 1--t--+-+-M0'fED PACKAGE

iz

1.6

Ci
a:

I

MAXIMUM PACkAGE r--~ lY: THERMAL CAPABILITY r-OPERATING~ UNE
I
t--

1.2

~

AREA

I

0.8 Pu = 6011 ntII

_'"

SUII'E=-~BJA

I,

OPERATINSj
~
POINT irA =7O·C_-tI....::lll'rl---t

0.4

O~~~~J~~l

National Semiconductor has adopted these industry-wide
standards. For devices fabricated in a molded package, the
maximum allowable junction temperature is 150"C. For
these devices assembled in ceramic or cavity DIP packages, the maximum allowable junction temperature is
175·C. The numbers are different because of the differences in package types. The thermal strain associated with the
die package interface in a qavity package is much less than
that exhibited in a molded package where the integrated
circuit chip is in direct contact with the package material.

25

50

__~~
__~

75 100 125 150
TEMPERATURE (OC)

175
TL/H/9312-5

FIGURE 5_ Package Power Capability
VB Temperature
The thermal capabilities of all integrated circuits are expressed as a power capability at 25·C still air environment
with a given derating factor. This simply states, for every
degree of ambient temperature rise above 25·C, reduce the
package power capability stated by the derating factor
which is expressed in mWrC. For our example--a 8JA of
63·C/W relates to a derating factor of 15.9 mW

Let us use this new information and our thermal equation to
construct a graph which displays the safe thermal (power)
operating area for a given package type. Figure 5 is an example of such a graph. The end points of this graph are
easily determined. For a 16-pin molded package, the maximum allowable temperature is 150"C; at this point no power
dissipation is allowable. The power capability at 25·C is
1.9SW as given by the following calculation:

rc.

FACTORS INFLUENCING PACKAGE
THERMAL RESISTANCE
As discussed earlier, improving any portion of the two primary thermal flow paths will result in an improvement in
overall thermal resistance junction-to-ambient. This section
discusses those components of thermal resistance that can
be influenced by the manufacturer of the integrated circuit. It
also discusses those factors in the overall thermal resistance that can be impacted by the end user of the integrated
circuit. Understanding these issues will go a long way in
understanding chip power capabilities and what can be
done to insure the best possible operating conditions and,
thus, best overall reliability.

W
• _ TJ(max)-TA _ 150·C-25·C _
PD@25 C 8JA
63"C/W
- 1.9S

6-23

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What is an acceptable maximum operating junction temperature is in itself somewhat of a difficult question to answer.
Many companies have established their own standards
based on corporate policy. However, the semiconductor industry has developed some defacto standards based on the
device package type. These have been well accepted as
numbers thatrelate to reasonable (acceptable) device lifetimes, thus failure rates.

"a

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90

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SO

!55!~
j!:ti

70

;~,

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:!I=:!.

~~i

IE~'"
!5
~

"

2

"
AirFlow

When a high power situation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the vicinity of the package. The graph of Figure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16-pin molded DIP.
The thermal ratings on National Semiconductor's interface
circuits data sheets relate to the still air environment.

TLlH/9312-6

Lead Frame Material

Figure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 42 type lead
frame-these 'are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a significant impact in package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.
170

...

- ...

~"fi

-

a!~, 110

IEZu

ffi~'o

...

i

1

90

70
50
1

1.1

1.0

~ 0.9

i

III1 1UN
MOLDED~CME

~

,,~

... 0.8

16-PlN MOLDED OIP

~ BOARD MOUNT-STILL AIR

0$ ..

7!!!i
"i=:!.

4 5 '6 7 8910
TLlH/9312-B

FIGURE 6. Thermal Resistance vs Ole Size

130

3

FIGURE 8. Thermal Resistance vs
Board or Socket Mount

3 4 5 6 78910
DIE SIZE (kMIL2)

li~

~OCKET

DIE SIZE (kMIL2)

2

!!iii
"'IE

"I"-- r--.t'oo",

SO

""" t'.

60

150

~ t:---

70


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cc,

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il31

w

13 IE

,

w

1110
u_

90

110

Ole Size
Figure 6 shows a graph of oUr 16-pin DIP thermal resistance
as a function of integrated circuit die size. Clearly, as the
chip size increases the thermal resistance decreases-this
relates directly to having a larger area with which to dissipate a given power.

~

0.7

Z

0.6

i..

A~

I

J

KOVAR

0.5

1'""

DIE

fllf

lk MILt

~!2

""""""
III
o

500
10lI0
AIR FLOW (UNEAR FEET/MINUTE)
TL/H/9312~9

FIGURE 9. Thermal Resistance vs Air Flow

c~

'

Other Factors

I

A number of other factors influence thermal resistance. The
most important of these is using thermal epoxy in mounting
ICs to the PC board and heat sinks. Generally these techniques are required only in the very highest of power applications.

2'
3 4 5 6 78910
DIE SIZE (kMIL2)
TLlH/9312-7

FIGURE 7. Thermal Resistance vs
Lead Frame Material

Some confusion exists between the difference in thermal
resistance junction-to-ambient (IIJA) and thermal resistance
junction-to-case (IIJcl. The best measure of actual junction
temperature is the junCtion-to-ambient number since nearly
all systems operate in an open air environment. The only
situation where thermal resistance junction-to-case is important is when the entire system is immersed in a thermal bath
and the environmental temperature is indeed the case temperature. This is only used in extreme cases and is the exception to the rule and, for this reason, is not addressed in
this application note.

Board vs Socket Mount
One of the major ,paths of dissipating energy generated by
the integrated circuit is through the device leads. As Ii result
of this, the graph of Figure 8 comes as no surprise. This
comJ:1ares the thermal resistance of our 16-pin package soldered into a printed circuit board (board mount) compared
to the same package placed in a SOCk!!t (socket mount).
Adding a socket in the path between tl]e PC ,board and the
device adds another stage in the thermal flow path, thus
increasing the overall thermal resistance. The thermal capabilities of National Semiconductor's interface circuits are
specified assuming board mount conditions. If the devices
are placed in a socket the thermal capabilities should be
reduced by approximately 5% to 10%.

NATIONAL SEMICONDUCTOR
PACKAGE CAPABILITIES

Figures 10 and 11 show composite plots of the thermal
characteristics of the most common package types in the
National Semiconductor Linear Circuits product family. Figure 10 is a compOSite of the copper lead frame molded

6-24

The package power ratings are specified as a maximum
power at 25·C ambient with an associated derating factor
for ambient temperatures above 25·C. It is easy to determine the power capability at an elevated temperature. The
power specified at 25·C should be reduced by the derating
factor for every degree of ambient temperature above 25·C.
For example, in a given product data sheet the following will
be found:

package. Figure 11 is a composite of the ceramic (cavity)
DIP using poly die attach. These graphs represent board
mount still air thermal capabilities. Another, and final, thermal resistance trend will be noticed in these graphs. As the
number of device pins increase in a DIP the thermal resistance decreases. Referring back to the thermal flow chart,
this trend should, by now, be obvious.
RATINGS ON INTEGRATED CIRCUITS DATA SHEETS
In conclusion, all National Semiconductor Linear Products
define power dissipation (thermal) capability. This information can be found in the Absolute Maximum Ratings section
of the data sheet. The thermal information shown in this
application note represents average data for characterization of the indicated package. Actual thermal resistance can
vary from ± 10% to ± 15% due to fluctuations in assembly
quality, die shape, die thickness, distribution of heat sources
on the die, etc. The numbers quoted in the linear data
sheets reflect a 15% safety margin from the average numbers found in this application note. Insuring that total package power remains under a specified level will guarantee
that the maximum junction temperature will not exceed the
package maximum.

Maximum Power Dissipation' at 25'C
Cavity Package
1509 mW
Molded Package 1476 mW
• Derate cavity package at 10 mW I"C above 2S'C; derate molded package
at 11.8 mW I"C above 2S'C.

If the molded package is used at a maximum ambient temperature of 70"C, the package power capability is 945 mW.
PD@ 70·C=1476 mW-(11.8 mWI"C)X (70'C-25'C)
= 945mW

Cavity (J Package) DIP'
Poly Die Attach Board
Mount-Stlll Air

Molded (N Package) DIP'
Copper Leadframe-HTP
Ole Attach Board MountStili Air
130

...

~~

110

!!iii

9D

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;1.;:,

70

:t;

50

...'I::!.

30

;!!ii!i

In~~

20L-__

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1

15 5! •

7!§

__

2

L-~~~U

3

4 5 6 7 8910

DIE SIZE (kMll')
'Packages from 8- to 20·pin 0.3 mil width

TLlH/9312-11

22-pin 0.4 mil width
24- to 48·pin 0.6 mil width

3 45678910
DIE SIZE (kMll2)
'Packages from 8- to 20-pin 0.3 mil width

FIGURE 11. Thermal Resistance vs Ole Size
vs Package Type (cavity Package)

TL/H/9312-10

22-pin 0.4 mil width

TO-263 (S Package)
Board Mount, Still Air

24· to 40-pin 0.6 mil width

FIGURE 10. Thermal Resistance vs Ole Size
vs Package Type (Molded Package)

80

Surface Mount (M, MW Packages),
Board Mount, Still Air
180

...........

~g: 184:~

N.

SO-16-N

l'IoJ..

160

;~:~:::

50- 8-N

~

~

120

'u
","""

100

(NARROW
BODY)

(WIDE

80

.......z

50

Vi
....

40

'"....

SO-16-N

:-

60

...'"
'"
f!i

SO-U-N

~

"""

\

\

"

........

-'

........ ~

r--.

",-

1\

(I)

.......

....:- r;;::::

70

....
u

SO-20-W BODY)

140

~
'u
~

I'-..

30
20

o

1

2

COPPER roll AREA (sa. IN.)

SO-14-W
SO-16-W
SO-20-W

TL/H/9312-13

60

'For products with high current ratings (>3A). thermal resistance may be
lower. Consult product datasheet for more information.

lk

10k

lOOk

FIGURE 13. Thermal Resistance (typo *) for 3-,5-,
and 7-L TO-263 packages mounted on 1 oz.
(0.036mm) PC board foil

TLlH/9312-12

FIGURE 12. Thermal Resistance for "SO" Packages
(Board Mount)

6-25

~~--------------------------------------------------------------------~

~
lP

dNa, tiona I Semiconductor

APPENDIX F
How to Get the Right Information From a Data She'et'
Not All Data Sheets Are Created Alike, andFalse Assumptions Could Cost an Engineer Time and Money

By Robert A. Pease
When a new product arrives in the marketplace, it hopefully
will have a good, clear data sheet "I'ith it.

Every year, for the last 20 years, manufacturers have been
trying to explain, with varying success, why they do not measure the Zin per se; even though they do guarantee it.

The data sheet can show the prospective user how to apply
the device, what performance specifications are guaranteed
and various typical applications and characteristics. If the
data·sheet writer has done a good job, the user can decide
if the product will be valUable to him, exactly how well it will
be of use to him and what precautions to take to avoid
problems.

In other cases, the manufacturer may specify a test that can
be made only on the die as it is probed on the wafer, but
cannot be tested after the die is packaged because that
signal is not accessible any longer. To avoid' frustrating and
confusing the customer, some manufacturers are establishing two classes of guaranteed specifications:
• The tested limit represents a test that cannot be doubted, one that is actually perfprmed directly on 100 percent
of the devices, 100 percent ,of th~ time.
• The design limit covers other testS that may be indirect,
implicit or simply guaranteed by the inherent design of
the device, and is unlikely to cause a failure rate (on that
test), even as high as one part per thousand.

SPECIFICATIONS

The most important area of a data sheet specifies the characteristics that are guaranteed-and the test conditions that
apply when the tests are done. Ideally, all specifications that
the users will need will be spelled out clearly. If the product
is similar to existing products, one can expect the data
sheet to have a format similar to other devices.
But, if there are significant changes and improvements that
nobody has seen before, then the writer must clarify what is
meant by each specification. Definitions of new phrases or
characteristics may even have to be added as an appendix.

Why was this distinction made? Not just because customers
wanted to know which specifications were guaranteed by
testing, but because the quality-assurance group insisted
that it was essential to separate the tested guarantees from
the deSign limits' so that the P.QL (assurance-quality level)
could be improved from 0.1 percent to down below
100 ppm.

For example, when fast-settling operational amplifiers were
first introduced, some manufacturers defined settling time
as the time after slewing before the output finally enters and
stays within the error-band; but other manufacturers included the slewing time in their definition. Because both groups
made their definitions clear, the user was unlikely to be confused or misled.
However, the reader ought to be on the alert. In a few cases, the data-sheet writer is playing a specsmanship game,
and is trying to show an inferior (to some users) aspect of a
product in a light that makes it look superior (which it may
be, to a couple of users).

Some data sheets guarantee characteristics that are quite
expensive and difficult to test (even harder than noise) such
as long-term drift (20 ppm or 50 ppm over 1,000 hours).
The data sheet may not tell the reader if it is measured,
tested or estimated. One manufacturer may perform a 100percent test, while another states; "Guaranteed by sample
testing." This is not a very comforting assurance that a part
is good, espeCially in a critical oase where only a long-term
test oan prove if the device did meet the manufacturer's
speoification. If in doubt, question the manufacturer.

GUARANTEES
When a data sheet specifies a guaranteed minimum value,
what does it mean? An assumption might be made that the
manufacturer has actually tested that' speCification and has
great confidence that no part could fail that test and still be
shipped. Yet that is not always tlie case.

TYPICALS

Next to a guaranteed specification, there is likely to be another in a column 'labeled "typical".

It might mean that the manufacturer once, actually saw one
part as good as that. It could indioate that half the parts are
better than that specifioation, ~J1d half will be worse. But it is
equally likely to mean that; five years ago, half the parts
were better and half worse. It ·oould easily signify that a few
parts might be slightly better, and a few parts a lot worse;
after all, if the noise of an amplifier is extremely olose to the
theoretioal limit, one oannot expect to find anything much
better than that, but there will always be a few noisy ones.

For instance, in the early 'days of op amps (20 years ago),
the differential-input impedance might have been guaranteed at 1 Mll-but the manufacturer obviously did not measure the impedance. When a customer insisted, "I have to
know how you measure this impedance," it had to be explained that the impedance was not measured, but that the
base current was. The correlation between Ib and Zin permitted the substitution of this simple dc test for a rather
messy, noisy, hard-to-interpret test.

If the specification of interest happens to be the bias ourrent
(Ib) of an op amp,. a user can expect broad variations. For
example, if the specification is 200 nA maximum, there
might be many parts where Ib is 40 nA ononebatoh (where
the beta is high), and Ii month later, many parts where the Ib
is 140 nA when the beta is low.

Reprinted by pennission from Electronic Engineering Times.

6-26

Absolute Maximum Ratings (Note 11)
Lead Temp. (Soldering. 4 seconds)
TO-4S Package

If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
+35Vto -0.2V
Supply Voltage
Output Voltage
+SVto -1.0V
Output Current
Storage Temperature.

+300"C

TO-92 Package
Specified Operating Temp. Range (Note 2)

10mA

- 7soF to + 300°F

+2SO"C

TMINtoTMAX
-50°F to +300°F
-40°F to + 230°F

LM34. LM34A
LM34C, LM34CA
LM34D

- 7soF to + 35soF

TO-4S Package
TO-92 Package

*

+ 32"F to + 212"F

DC Electrical Characteristics (Note 1. Note 6)
LM34A
Parameter

Accuracy (Note 7)

Conditions

Typical

Tested
Limit
(Note 4)

+77"F
O°F
TMAX
TMIN

±0.4
±O.S
±0.8
±0.8

Nonlinearity (Note 8)

TMIN"; TA"; TMAX

±0.35

Sensor Gain
(Average Slope)

TMIN"; TA"; TMAX

+10.0

+9.9,
+10.1

Load Regulation
(Note 3)

TA = +77"F
TMIN"; TA"; TMAX
0,,; IL"; 1 mA

±0.4
±0.5

±1.0

Line Regulation (Note 3)

TA = +77"F
5V,,; Vs"; 30V

±0.01
±0.02

±0.05

75
131
7S
132

90

+0.5
+1.0

2.0

Quiescent Current
(Note 9)

Change of Quiescent
Current (Note 3)

TA
TA
TA
TA

Vs
Vs
Vs
Vs

=
=
=
=

=
=
=
=

+5V. +77'!F
+5V
+30V. +77"F
+30V

4V ,,; Vs ,,; 30V. + 77"F
5V,,; Vs"; 30V

Temperature Coefficient
of Quiescent Current

LM34CA
Design
Umit
(Note 5)

Typical

±2.0
±2.0
±0.7

Design
Limit
(Note 5)

Units
(Max)

±2.0
±3.0

of
of
of
of

±0.30

±O.6

of

+10.0

+9.9,
+10.1

mVrF. min
mVloF. max

±3.0

mV/mA
mV/mA

±0.1

mVIV
mV/v

139

".A
/LA

142

/LA

3.0

/LA
/LA

±0.4
±O.S
±0.8
±0.8

±1.0

Tested
Limit
(Note 4)
±1.0
±2.0

±0.4
±0.5

±1.0

±3.0

±0.01
±0.02

±0.05

±0.1

90

183

75
116
7S
117
0.5
1.0

2.0

3.0

+0.30

+0.5

+0.30

+0.5

/LA/OF

+5.0

+3.0

+5.0

OF

Minimum Temperature
for Rated Accuracy

In circuit of Figure 1,
IL = 0

+3.0

Long-Term Stability

Tj = T MAX for 1000 hours

±0.16

160
92

p.A

92

OF

±0.16

Note 1: Unless otherwise noted. these specifications apply: -50"F ,;; Tj ,;; + 300"F for the LM34 and LM34A; -40"F ,;; Tj ,;; +23O"F for the LM34C and
LM34CA; and +32"F ,;; Tj ,;; + 212"Fforthe LM34D. Vs ~ +5 Vdcand ILOAD ~ 50,.A in thecircu~of FtgU",2; +6 Vdcfor LM34 and LM34A for 230"F';; Tj ,;;
300"F. These specifications also apply from + 5"F to TMAX in the circult of FigutrJ 1.
Note 2: Thermal resistance of the TQ.46 package is 292"F/W iunction to ambient and 4:r'F/W iunction to case. Thermal resistance of the TO-92 package is
324"F/W junction to ambient.
Note 3: 'Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the Internal dissipation by the thermal resistance.
Note 4: Tested lim~ are guaranteed and 100% tested in production.
Note 5: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These lim~ are not used to
calculate outgoing qual~ levels.
Note 6: Specification in BOLDFACE TYPE apply over the full rated temperature range.
Note 7: Accuracy is defined as the error between the output voltage and 10 mVI"F times the device's case temperature at specijied conditions of voHage, current,
and temperature (expressed in "F).
Note 8: Nonlinear~ is defined as the deviation, of the output-voHag...versus-temperature curve from the best-fit straight line over the device's ratad temperature
raryge.

Note 9: Quiescent current is defined in the circuit of FtgU'" 1.
Note 10: Contact factory for availability of LM34CAZ.

-

* *Note Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its rated operating conditions (see Note
11:

1).

6-27

u..
>C

A Point-By-Point Look

!.
D..

Let's look a little more closely at the data sheet of the National Semiconductor LM34, which happens to be a temperature sensor.

is
c
0.127)

~:::

0.020
10.508)
MIN

/8.255 +1.016
~
-lU81
N20AIREVG)

20 Lead (0.300" Wide) Molded Dual-in-Line Package
NS Package Number N20B
All dimensions are in inches (millimeters)

~======~~~IZ~"I~

0.092 x 0.030
(2.337 x 0.762)
MAXDP

0.240-0.260
16.098-6.604)

PIN NO. llDENT

~

(:~~i:)-

0.032±O.o05~D
19

(0.813±0.121)
RAD

PIN NO.lI0ENT~

~~~~~~~~~
OPTION 2

0.290-0.325

C~'~I
I
I

9
I

IE,.---H----++-----i

r

7
0.008_0.01
j-J97.S0 ± ::\\-(0.203-0.381)

0.350 NOM

I

J
I

0.040 NOM
(1.016)

0.100.0.010

I

I-- (2.540 .0.254)-1

13.175-3.810)

(8.800)

N2OB(REVA)

6·43

o

~

0.260 to.005
16.604 ±0.127)

I~:~::)J

Ii
3"
CD

~~=======I1===II==I=&==14==1=3==I~Z=='I~___r

PIN NO. llDENT

~

All dimensions are in inches (millimeters)

In

0"
~

In

o

C

"i
~

r-----------------------------------------------------------------------------,
22 Lead (0.300" Wide) Molded Dual-in-Line Package
NS Package Number N22A
All dimensions are in inches (millimeters)

r---(!:.~~=!i'.!:) -----j

B
"~

I~ ~ ~ ~

.c
a.

0.062
HAD (1.575)
PIN NO. I
IDENT

g

"

~ ~ ~ ~ ~I

f

0.350 to.005
(8.890 to.127)

~r=;:::;=;:::~~F.!'Fi':'i"~~

~

0.100 ±0.010
(2.540 ±0.254)

(1.270 ±0.3811

(OA57 ±0.076)
N22A{REVD)

24 Lead (0.300" Wide) Molded Dual-in-Line Package
NS Package Number N24C
All dimensions are in inches (millimeters)
1.243 -1.270
(31.57 -32.2lI)
MAX

0.092
(2.337)
(2 PLS)

I

PIN NO.1

0.2lIO±0.005
(6.604±0.127)

IDENT

I
0.062
(1.575)
RAD

0.300-0.320

I

"~='J

TYP

~J

0.009-0.015
(0.229-0.381)

0.065

(1.651)

0.325 ~:::~~
fa 255 +1.016)
~ .
-0.381

0.040
(1.016)

-+----~

0.DT5±0.016
(1.905±0.381)

~
N24C(REV F)

6-44

28 Lead (0.600" Wide) Molded Dual-in-Line Package
NS Package Number N28B
All dimensions are in inches (millimeters)

fiN NO. 1 WEHr

1-_______ '.393-'.420 - - - - - - - + 1
(35.38 36.07)

0.125-0.145
(3.175-3.683)
N28B(REVE)

40 Lead (0.600" Wide) Molded Dual-in-Line Package
NS Package Number N40A
All dimensions are in inches (millimeters)

0.1182
(1.676)
RAD

PIN NO. tlDENT

1

8

@

~~

~~n=F.r~9m~~~F.r~95=rnrT.W9ffi=ffiF~~=rn~~=r~~O"V)
0.0&0

0.071:1:0.015

(1.906 '0.381)

6-45

!

.~
c

CD

11 Lead Molded TO-202
NS Package Number P11A

E

All dimensions are in inches (millimeters)

is

0.880 ± 0.005

1j

i

Go

(22.352±0.1271---~
0 134
(3 '.4041 x45° (P11A·21

0.128 -0.132
(3.251-3.3531 0.034 x45' (P11A.2)
DIA
(0.864)

( : : : xW (Pl1A·l)

,-----~ xW (Pl1A.ll

~t------~r~------~~~
0.463±0.005
(11.760±0.127)

0.082
(1.5751
RAD

EJECTOR PINS
0.001-0.009

i+---±---+ (0.025 -0.229)

EJECTOR PINS
0.125±0.005
(3.175±0.1271
BOTH SIDES
Of PACKAGE

0.050 ±0.015
(1.270±0.3Bll
0.025 ±0.003
(0.635 ±0,076)
(PllA·2)
0.01B±0,OO3
(0.457±0.076)
(Pl1A-l)
Pl1AtHf:VFl

3 Lead Molded TO-220
NS Package Number T03B
All dimensions are in inches [millimeters]
0.330-0.350 ~
[B.38-8.89]
0.100-0.120
[2.54-3.05]

B 0.149-0.153
[3.78-3.89]

r

0.400

~~:~~:

0.190-0.210
[4.83-5.33]

[10.16 ~::~~]

'--------'-~y-~~-~-~~~
L , --,
U
0.048-0.055
[1':22-1.40]

0.130-0.160 TYP'
[3.30-4.06]

PIN #1 10

TYP

0.027-'0.037
[0.69-0.94]

1.005-1.035
[25.53-26.29]

70

A

I- (
'r-

...L.-------t,:-----'-\
0.175-0.185 I
[4045-4.70] ..L

TL

.-_ _-1
LO....0-4-8_-0-.0....5-2L-+---....J.
[1.22-1.32)

TYP

0.525-0.555 )
[13.34-14.10]

I' 0.015 ~::::~ [0.38 ~:::~]
1-1.

-t

~ =q

0 105 +0..,0 [267+ 0.25 )
.

-0.0\5'

-0.38

SEATING PLANE

TAPERED
SIDES 1°

T038 (REV L)

6-46

r-------------------------------------------------------------------------------------lir.
~

5 Lead Molded TO-220
NS Package Number T05A

All dimensions are in inches [millimeters)

0.100-0.120
[2.54-3.05)

0.149-0.153

r

0.400

3

0.030-0.040

fJ [3.78-3.89)

5X

CD

[0.76-1.0~

::::II

!e.

o::::II
fn

+0.015

-0.005

___ _

[10.16~~:~~)

L,---~-----:
10.240-0.260

I

0.330-0.350

--I [6.10-6.60) I- [8.38-8.89)

~

0.057-0.D77
4X [1.45-1.96)

PIN ""1 10

SEATING PLANE
0.015
[0.38

+0.007
-0.001

TYP

~~:~~) ~

0.175-0.185 I
[4.45-4.70)

2

..L..

C=1==~L-:--::--fI-I-----------I__r

0.048I:J
[1.22-1.32)

0.1 05

( 0.525-D.555 )
[13.34-14.10)

[2.67

1.005-1.035
[25.53-26.29)

TAPER SIDES 10

~~:~:~
~~::: 1

TD5A (REV J)

5 Lead Molded TO-220
NS Package Number T05B
All dimensions are in inches (millimeters)

-

-11

0.3I1I-D.411

iiii.ii=1i.i7i
O.151±O.1IG!

D.l1D±D.I1D
Vii.iii±i.i5ii
12.~~.~)~~_~~~_,
I

1.1O'y!!'

-$ ,::::::::)
-.

PlNND.1
IDEHTlfJCATIOH

1

--t

1

~

D.055xD.D15
',·317XI.3I1)

,I.UII±D.254)

DES'MAX

,

..!:l!!.

I

,17.•)

~L

IL

----

0.115

~::: - - I

/•.311 +D.2114)
\"

:::::::

-a.051

~

--

1.105

iiii7i
1.171-D.ll1
,..-.----t-- i4.iiH.ii7i
--

::=:::

TYP

IEA1INB
I'IMI£

to5B(AEYf-1

6-47

5 Lead Molded TO-220
NS Package Number T05D
0.110 i 0.010
2.79:t 0.25

Ijl

-I
I

inches
All dimensions are in millimeters

O. 151:t 0.002
3.84:t 0.05

I

r

. 't

0.400~g:m

0.035 i 0.005 TYP
0.89:t 0.13

.

t
_-.1
-

J ;L
0.250 i 0;010
6.35 i 0.25

o.340io.Ol0
8.64:t 0.25

~

0.067 i 0.005 TYP
1.70iO.13

PIN ONE 10

0.,34iO. 015
3.40 i 0.38

1

0.0 15 ~g:gJ~

~~g:~g

--r l

TAPERED SIDES 10

0.343
0.324

"8.70

t

B.24

0.180 iO.005 1
4.57iO.13 ..l-

,....,r--+-.,-"1

1-.- I...L...+-...L.--I._____
~J

0.050
1.27 i 0.05

---+-1---r-I-~ SEATING PLANE
0.176 i 0.009
4.47 i 0.23

0.704
17.88 - - - - . ,

k------

T.50(.EVA) •

11 Lead Molded TO-220
NS Package Number TA 11 B
All dimensions are in inches (millimeters)
2x

O.I20±0.010

o.m

0.788±0.010
'----~ (20.01 ±0.254)

(4.496)

0.150±0.OO2
--..ri3.Bl0±0.0511

45' x (3.048±0.254j \

)/

---..j

0.110

0061 ±0.OO2

I

(2.794)

~il:549±0.061)

-

~~----"~-'·~~'-'-0.~~.1fO'O-'0--r~-M~
ji'f.7i±o154j

o.!eo

o

(21.84)

0.666

O'666±o,0~LE'OO) r-:::: __ ;;:;; I---t
1
.
-

5 x (22.00 ±O.506)

1

7' TVP

U&O±O.020

6X

I1X(::::j_~

0.067

i-- 'OX (1.702)
~0~.6~70~ -------l~
(17.02)

---t;,

I"

0.200±0.010

0.0:±0.:~OB;y~0.254)

---.. j.- (O.408±O.0511
6·48

0.169±0.010

I-- (4.293±0.254)

TA1'81REVAl

12 Lead Molded TO-220
NS Package Number TA 12A
All dimensions are in inches [millimeters]
1.188 to.Ol0
/ - - - - - - [30.18 t o . 2 5 ] - - - - + I
0.790 to. 005
0.204 to.005
[20.07 t o . 1 3 ] - - + - - I - [5.18 to.13]

4X R 0.075 to.OO 1
[1.91 to.03]

0.177 :to.005
[4.50 :to.13]
0.61 to.002
[1.55 to.05]

0.110 to.005
[2.79 to.13]

PIN #1 10

I

1

L

,

L

0.225 MIN TYP
[5.72]

0.100 to.Ol0 TYP
[2.54 to.25]

0.020 to.003 TYP
[0.51 to.08]

,

II-

--I

,

7° TYP

~ 0.095

:to.008 TYP
[2.41 :to.20]

0.035 to.003 TYP
[0.89 to.08]

-I,

0.160 :to.005
[4.06 :to.13]
0.089 to.O 10
[2.26 to.25]

',...--,'--___ [27.94
1.100 to.O 10 _ _ _ _.jl
1
to.25]

0.016 to.002
[0.41 to.05]

1

-I

TA12A (REV 8)

11 Lead Molded TO-220
NS Package NumberTF11B
All dimensions are in inches [millimeters]
0.783-0.793 ~
[19.89-20.14]
2 450

x

0.110-0.114

0.125-0.135
[3.18-3.43]

1/J0.149-0.153
[3.78-3.89]

x [2.79-2.90]

-rL

ili=====±====;1-

0.414-0.424
[10.52-10.77]

0.187-0.197

1'1"']
6 x 0.845-0.875
[21.46-22.23]

5x 0.851-0.881
[21.62-22.38]

-r:

-~

-

0.766-0.776
[19.46-19.71]

0.690-0.710
[17.53-18.03]
( 0.860)

([~2~gg] )

170 TYP

I'~~=~

1¥i=;:;:;=r;:;:;=r;:~'i'TFi~
PIN #1
IDENT

0.014-0.017 TYP
[0.36-0.43]

~o~~~=~:g~f

TYP

-lL
II

,
0.190-0.21 0-+~_+_-f_0.159-0.179
[4.83-5.33]
[4.04-4.55]
TF11B (REV c)

6-49

3 Lead Molded TO-263
NS Package Number TS3B
All dimensions are in inches [millimeters)

tOil"
I+--I"

-

I
I\,
--I 0.330-0.350 i-=
[B.3B-B.B9]
0.050 MAX
[1.27]

L----1= " -_7°
0.175=~.!~~ ~ I
[4.45-4.65] ..L
I

0.250
[6.35 ] MIN...,

Lo.02B-0.03B TYP
[0.71-0.97]
PIN· 1 ID
0 030
R [0.76] MAX TYP
0.015-0.030
[0.3B-0.76J 0.035

-- -

0.575
[14.61]

iD:-I

-EJ- ...l
-EJ-

0.425
[10.BO]

l

S-[0.B9]

0.OB5 TYP
[2.16]

'1

"-E3::~lO.'00

I-- [10.41]
0.410 --I

[2.54]
TYP
0.042 TYP
[1.07]

LEAD POSITION OVERLAY

I+-

!

0.20 o MIN
[5.0B

]~

BACK VIEW

TS3B (REV

cl

5 Lead Molded TO-263
NS Package Number TS5B
All dimensions are in inches [millimeters)

0.260-0.2BO
[6.60-7.11]
0.390-0.410
[9.91-10.41] "

L

-

--l

-I-'
....l

--lo.02B-0.03B
[0.71-0.97] TYP
0.330-0.350 ~ PIN., ID
[B.38-8.B9]

0.425
[10.80]

R [0~7361 MAX TYP
0.015-0.030
[0.38-0.76] 0.035

_ _ _ _ r--[0.89]

-.r::rT-....-l'":~::;:::-+-II~>:f:!..-=l!,---'--T 10 I0.004[0.1 0]1

ttl

l±I
TAPERED
0.048-0.052--.J
SIDES 1°
[1.22-1.32]
0°-6°
I
0.000-0.006 STAND-OFFJ~
[0-0.15]
0.490 MAX
[12.45]

t=

tOil

i1l-B-EJ-...l
5-:![
-B-1

I - - - 0.575
I
[14.61] -l

r

l

"
0.410
1--[1041]--1
.

0.085 TYP

[2.16]

0.067
[1.70J
TYP

0.042 TYP
[1.07]

LEAD POSITION OVERLAY

-T'

[~:.~~~] MAX

CONTROLLING DIMENSION: INCH

[~.23~~ MIN...,

r+--/--n

0.200 MIN
[5.08]
TS5S(REYS)

6-50

r-----------------------------------------------------------------------------~~

::T

20 Lead Molded Plastic Leaded Chip Carrier
NS Package Number V20A

';i
All dimensions are in inches [millimeters]

0.350

PIN # 1 IDENT

o

0.065

45 X [1.65]
4

l
~ r-IF"~' =l
~

0.31 OtO.020 TYP
[7.S7t0.S1]

_J

14
,

i

SEATING PLANE

13

--I I'0.200 TYP
[5.0a]

i-

0'

::::I
UJ

+ I

0.029tO.003 TYP
[O.74to.oa]
S

::::I
UJ

0.0 1HO.004 TYP
[O.43tO. 10]

1a

--I

3'
CD

~~:~~~

o [a.a9 ~~:~~ ]

0.020 ~IN TYP
[0.51]

0.050 TYP

[1.27]

I------+_ 0.1 OSto.O 15 TYP
[2.6HO.3a]

I----\-- 0.165-0.1 ao
[4.19-4.57]

TYP

V20A (REV L)

28 Lead Molded Plastic Leaded Chip Carrier
NS Package Number V28A
All dimensions are in inches [millimeters]

450 X 0.045
[1. 14)
0.029tO.003 TYP
[0.74tO.OS)
25

fr'"

0.0 HtO.004 TYP

0.410tO.020 TYP

11

~.u..::::"lDl':]'"

19
12
I

0.050 TYP

--I .....

SEATING PLANE

18

I [1.27]
I
I- [7.62)
0.300 TYP -l

0.1 05tO.0 15 TYP
[2.67tO.3S) ,
0.165-0.1 ao TYP -+~_+I
[4.19-4.57]

V28A(REVK)

6-51

~

o

II) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

j
I!

~

44 Lead Molded Plastic Leaded Chip Carrier
NS Package Number V44A
All dimensions are in inChes [millimeters]

:!

0.017:1:0.004 TYP
[0.43:1:0.10]

ON

~

A.

45 0 X 0.045
[1.14]
~----~~~----~~39

0.029:1:0.003 TYP
[0.74:1:0.08)
0.610:1:0.020
[15.49:t0.51j TYP

SEATING PLANE
17

18

L' 5'
--I

29

'28 0.050
[1.27] TYP

[2~~~;~:~!i

0.500
[12.70] TYP

TYP

0.165-0.180
1-----'+1- [4.19-4.57] TYP

V44A (REV K)

10 Lead Cerpack
NS Package Number W10A
All dimensions are in inches
0.080
0.055
0.035
0.026
TYP

0.270 MAX
0.050:1: 0.005
lYP

0.005 MIN TYP

i
10

0.370
0.250

I

0.270 MAX
GLASS

0.260
0.238

y,,,,
0.008
DETAIL A

0.370
0.250

,

0.006
0.004
TYP

J

6-52

WIOA (REV E)

5
0.045 MAX
TYP

3 Lead Molded TO-92
NS Package Number Z03A
All dimensions are in inches [millimeters]

1-

5 0 2 PLCS

...----"'"
,-""1===:2
SEATING

.- .

c=:::::J.-l

PLANE-k~2~~~]MIN

J 1.··""···"""'.M '''' """
[0.368-0.394]

1----1-- 0.135-0.145

. -----.

I
L:

o 0.175-0.185
[4.45-4.70]

~

I
I

I
I

:
I

:
I

•

EJECTION MARK
fa 0.065

0.090 MAX
[2.29]
(UNCONTROLLED
LEAD DIA)

6·

6.

: -

[3.43-3.68]

f

0.045-0.055
[1.14-1.40]

0.045-0.055 TYP
[1.14-1.40]

-..l

-J

0.016-0.021 TYP
[0.41-0.53]

R 0.090
[2.29]

10 0 2 PLCS

[1.65]
0.015 MAX
T [0.38]

Z03A (REV r)

6-53

NOTES

t!lNational Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
For datasheets on new products and devices still in production but not found in a databook, please contact the National
Semiconductor Customer Support Center at 1-800-272-9959.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090

ADVANCED BiCMOS LOGIC (ABTC, IBF, BiCMOS SCAN, LOW VOLTAGE
BiCMOS, EXTENDED TTL TECHNOLOGY) DATABOOK-1994
ABTC/BCT Description and Family Characteristics. ABTC/BCT Ratings, Specifications and Waveforms
ABTC Applications and DeSign Considerations. Quality and Reliability. Integrated Bus Function (IBF) Introduction
54174ABT3283 Synchronous Datapath Multiplexer. 74FR900/25900 9-Bit 3-Port Latchable Datapath Multiplexer
54174ACTQ3283 32-Bit Latchable Transceiver with Parity Generator/Checker and Byte Multiplexing
SCAN18xxxA BiCMOS 5V LogiC with Boundary Scan. 74LVT Low Voltage BiCMOS LogiC
VME Extended TTL Technology for Backplanes

ALS/AS LOGIC DATABOOK-1990
Introduction to Advanced Bipolar Logic • Advanced Low Power Schottky. Advanced Schottky

APPLICATION SPECIFIC ANALOG PRODUCTS DATABOOK-1995
Audio Circuits. Video Circuits. Automotive. Special Functions. Surface Mount

ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions • Peripheral Functions • LSIIVLSI Functions. Design Guidelines. Packaging

CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount

CLOCK GENERATION AND SUPPORT (CGS) DESIGN DATABOOK-1994
Low Skew Clock Buffers/Drivers. Video Clock Generators • Low Skew PLL Clock Generators
Crystal Clock Generators

COP8™ DATABOOK-1994
COP8 Family. COP8 Applications. MICROWIRE/PLUS Peripherals. COP8 Development Support

CROSSVOLTTM LOW VOLTAGE LOGIC SERIES DATABOOK-1994
LCX Family. LVX Translator Family. LVX Bus Switch Family. LVX Family. LVQ Family. LVT Family

DATA ACQUISITION DATABOOK-1995
Data Acquisition Systems • Analog-to-Digital Converters. Digital-to-Analog Converters • Voltage References
Temperature Sensors. Active Filters. Analog Switches/Multiplexers • Surface Mount

DATA ACQUISITION DATABOOK SUPPLEMENT-1992
New devices released since the printing of the 1989 Data Acquisition Linear Devices Databook.

DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides • Diodes. Bipolar NPN Transistors
Bipolar PNP Transistors. JFET Transistors. Surface Mount Products. Pro-Electron Series
Consumer Series. Power Components. Transistor Datasheets • Process Characteristics

DRAM MANAGEMENT HANDBOOK-1993
Dynamic Memo\y·Control • CPU Specific System Solutions. Error Detection and Correction
Microprocessor Applications

EMBEDDED CONTROLLERS DATABOOK-1992
COP400 Family • COP800 Family. COPS Applications • HPC Family - HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals - Microcontroller Development Tools

FDDI DATABOOK-1994
Datasheets - Application Notes

F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1992
Family Overview - 300 Series (Low-Power) Datasheets • 100 Series Datasheets - 11 C Datasheets
Design Guide. Circuit Basics - Logic Design -Transmission Line Concepts - System Considerations
POwer Distribution and Thermal Considerations - Testing Techniques - 300 Series Package Qualification
Quality Assurance and Reliability - Application Notes

FACTTM ADVANCED CMOS lOGIC DATABOOK-1993
Description and Family Characteristics. Ratings, Specifications and Waveforms'
DeSign Considerations. 54AC/74ACXXX. 54ACT/74ACTXXX. Quiet Series: 54ACQ174ACQXXX
Quiet Series: 54ACTQ/74ACTQXXX - 54FCT174FCTXXX - FCTA: 54FCTXXXA174FCTXXXA/B

FAST® ADVANCED SCHOTTKY TTL lOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms - Design Considerations. 54F174FXXX

FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook'
I
Contains application information on the FAST family: Introduction. Multiplexers. Decoders - Encoders
Operators. FIFOs. Counters - TTL Small Scale Integration. Line Driving and System DeSign
FAST Characteristics and Testing. Pac.kaging Characteristics

HIGH-PERFORMANCE BUS INTERFACE DATABOOK-1994
QuickRing - Futurebus+ IBTL Devices - BTL Transceiver Application NoteS - Futurebus+ Application Notes
High Performance TTL Bus Drivers - PI-Bus. Futurebus + IBTL Reference

IBM DATA COMMUNICATIONS HANDBOOK-1992
IBM Data Communications. Application Notes

INTERFACE: DATA TRANSMISSION DATABOOK-1994
TIAIEIA-232 (RS-232) - TIAIEIA-422/423. TIAIEIA-485 - Line Drivers - Receivers. Repeaters
Transceivers. Low Voltage Differential Signaling. Special Interface. Application Notes

LINEAR APPLICATIONS HANDBOOK"";"1994
The purpose of this handbOOk is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

lOCAL AREA NETWORKS DATABOOK-1993 SECOND EDITION
Integrated Ethernet Network Interface Controller Products - Ethernet Physical Layer Transceivers
Ethernet Repeater Interface Controller' Products. Token-Ring Interface Controller (TROPIC)
Hardware and Software Support Products - FDDI Products - Glossary and Acronyms

LOW VOLTAGE DATABOOK-1992
This databook contains information on National's expanding portfolio of low and extended voltage products. Product datasheets
included for: Low Voltage Logic (LVQ), Linear, EPROM, EEPROM, SRAM, Interface, ASIC, Embedded Controllers, Real Time
Clocks, and Clock Generation and Support (CGS).

MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors. Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller. SCSI Bus Interface Circuits. Floppy Disk Controllers. Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits. Rigid Disk Microcontroller Circuits. Disk Interface Design Guide

MEMORY DATABOOK-1994
FLASH. CMOS EPROMs • CMOS EEPROMs • PROMs. Application Notes

MEMORY APPLICATIONS HANDBOOK-1994
FLASH. EEPROMs • EPROMs • Application Notes

OPERATIONAL AMPLIFIERS DATABOOK-1995
Operational Amplifiers. Buffers. Voltage Comparators. Active Matrix/LCD Display Drivers
Special Functions • Surface Mount

PACKAGING DATABOOK-1993
Introduction to Packaging. Hermetic Packages. Plastic Packages. Advanced Packaging Technology
Package Reliability Considerations. Packing Considerations. Surface Mount Considerations

POWER IC's DATABOOK-1995
Linear Voltage Regulators • Low Dropout Voltage Regulators. Switching Voltage Regulators
Motion Control • Surface Mount

PROGRAMMABLE LOGIC DEVICE DATABOOK AND
DESIGN GUIDE-1993
Product Line Overview. Datasheets • DeSign Guide: Designing with PLDs • PLD Design Methodology
PLD Design Development Tools. Fabrication of Programmable Logic. Application Examples

REAL TIME CLOCK HANDBOOK-1993
3-Volt Low Voltage Real Time Clocks. Real Time Clocks and Timer Clock Peripherals. Application Notes

RELIABILITY HANDBOOK-1987
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs • Reliability and the Cost' of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Military/ Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. AN/ Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing

SCANTM DATABOOK-1994
Evolution of IEEE 1149.1 Standard. SCAN BiCMOS Products • SCAN ACMOS Products. System Test Products
Other IEEE 1149.1 Devices

TELECOMMUNICATIONS-1994
COMBO and SLiC Devices. ISDN. Digital Loop Devices. Analog Telephone Components. Software. Application Notes

VHC/VHCT ADVANCED CMOS LOGIC DATABOOK-1993
This databook introduces National's Very High Speed CMOS (VHC) and Very High Speed TTL Compatible CMOS (VHCn
designs. The databook includes Description and Family Characteristics. Ratings, Specifications and Waveforms
Design Considerations and Product Datasheets. The topics discussed are the advantages of VHCIVHCT AC Performance,
Low Noise Characteristics and Improved Interface Capabilities.

NATIONAL SEMICONDUCTOR CORPORATION .DISTRIBUTORS
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NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS (Continued)
MINNESOTA (Continued)
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Hamilton/Hallmark

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NEW JERSEY
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UTAH
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(613) 820-8313

Semed Electronics Ltd.
(613) 526-4866

Pointe Claire
Future Electronics Corp.
(514) 694-7710

Semad ElectronicS Ltd.
(514) 694-0660
Quebec

Future Electronics Corp.
(418)877-8686

Ville SI. Laurent
Hamilton/Hallmark
(514) 335-1000

Zentronics/Pioneer
(514) 737-9700

Willawdale
Electro Sonic Inc.
(416) 494-1666

Winnipeg
Electro Sonic Inc.

Pioneer Standard

(204) 783-3105

(414) 784-3480

Future Electronics Corp.

Mequon
Taylor Electric
(414) 241-4321

(204)944-1446

Zentronics/Pioneer
(204) 694-1957

IfI

Nat i p n a I S e m i .c 0 n d u c tor.
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AUSTRALIA

FRANCE

National Semiconductor
(Australia) Ply. Ltd.
Bldg. 16 Business Park Dr.

S.A.

National Semiconductor

Monash Business Park

3, Avenue Du Canada

Nottinghill Melbourne
Victoria 3166 Australia
Tel: (39) 558-9999
Fax: (39) 558-9998

Bat. ZETA - LP. 821 Les Ulio
F-91974 Courtaboeuf Cedex
France
Tel: (1)69183700
Fax: (1) 6918 37 69

Parc d'Affaires Technopolis

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National Semlconductorea
Do Brazil Ltds.
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Sao Paulo·SP Brazil 05418-000
Tel: (55-11) 212·5066
Fax: (55·11) 212-1181

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Nallonal Semiconductor
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Tel: (416) 678-2920
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National Semiconductor

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National Semiconductor
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Offlce
Room 1930
New Century Holel,
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CepitelGym
Beijing 100046, PRC
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Fax: 10-849-133 2

FINLAND
Natlonal semiconductOr

(U.K.) Ltd.
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SF-00810 HelSinki
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Tel: (0) 759-1655
Fax: (0) 759·1393

GERMANY
Nallonal Semiconductor
GmbH
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1).82256 FOrstenfeldbruck

Germany
Tel: (0·81-41)35-0
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Hong Kong Ltd.
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Ocean Centre
5 Canton Road
TsimohalSui, Kowloon
Hong Kong
Tel: (852)2737·1600
Fax: (652) 2736-9960

INDIA
National Semiconductor
India Ualaon Office
26 Cunningham Road
Bangalore 560052 India
Tel: 80-226-7272
Fax: 60-225-1133

ISRAEL
National Semiconductor Ltd.
Maskit Street
PO Box 3007
Herzlla B. 46104
lorael
Tel: (09) 59 42 55
Fax: (09) 55 83 22

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National Semiconductor s.p.A.
Strada 7, Palazzo·R/3
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Tel: (02) 57 50 03 00
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National Semiconductor
Japan Ltd.
SumHomo Chemical
Engineering Center Bldg. 7F
1-7-1, Nakase, Mihama-Ku
Chiba-CHy,
Chiba Prefecture 261
Japan
Tel: (043) 299-2300
Fax: (043) 299-2500

KOREA
National Semiconductor
(Far Easl) Ltd.
13th Floor, Dai Han
Ufe Insurance 63 Building
60 Voido-Dong
Voungdeungpo-KU
Seoul Korea 150-763
Tel: (02) 794-8051/3
(02) 785-0696/8
Fax: (02) 784·9054

MALAYSIA
National Semiconductor
SdnBhd
Bayan Lepas Free Trade Zone
11900 Penang Malaysia
Tel: 4-844-9061
Fax: 4-644-9073

MEXICO
Electronlca NSC de
Mexico SA
Juventlno Rosas No.1 t 8-2
Col Guadalupe Inn
Mexico, 01020 D.E. Mexico
Tel: (525) 661-7155
Fax: (525) 661·6905

PUERTO RICO
National Semiconductor
(Puerto RicO)
La Electronlca Bldg.
SuHe312, R.D. #1 KM 14.5
RioPiedias
Puerto Rico 00927
Tel: (909) 758-9211
Fax: (909) 763-6959

SINGAPORE
National Semiconductor
Asia Paclflc PIe. Ltd,
200 Cantonment Road # t 3-Ot
Southpoint Singapore 0208
Tel: (65) 225·2226
Fax: (65) 225-7080

SPAIN.
National Semiconductor GmbH
Calle Aguslin de Foxa, 27 (9'0)
E-29036 Madrid
Spain
Tel: (Ot) 7-33·29-54
Fax: (01) 7-33-80-18

SWEDEN
National Semiconductor AB
P.O. Box 1009
Grosshandlarvllgen 7
S·12123 Johanneshov,
SWeden
.
Tel: (08) 7 22 80 50
Fax: (08) 7 22 90 95

SWITZERLAND
National Semiconductor
(U.K.) Ltd.
Alte Winlerthurerstrasse 53
CH-8304 Wallisellen-ZQrich
Switzerland
Tel: (01) 8-30·27-27
Fax: (01) 8-30-19-00

TAIWAN
Nallonal Semiconductor
(Far Eaat) Ltd.
.
9/F, No. 44 Section 2
Chungshan North Road
Taipei, Taiwan, R.O.C.
Tel: (02) 521·3288
Fax: (02) 561-3054

U.K. AND IRELAND
Nallonal Semiconductor

(U.K.) Ltd.
The Maple, Kembrey Park
Swindon, Wiltshire SN2 6y)(
United Kingdom
Tel: (07-93) 61 41 41
Fax: (07-93) 52 21 90
Telex: 444674

UNITED STATES
National Semiconductor
Corporation
1 t 11 Wast Bardin Road
Arlington, TX 79017
Tel: (900) 272-9959
Fax: (800) 737·7018
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